1974_National_Interface_Integrated_Circuits 1974 National Interface Integrated Circuits
User Manual: 1974_National_Interface_Integrated_Circuits
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Edge Index
by Product Family
Here is the new INTERFACE catalog from National Semiconductor Corporation. It contains complete
information on all of National's INTERFACE products whether they be Linear, Digital, or MOS. It is
the first such catalog in the industry and we hope it becomes your most important INTERFACE guide.
For your convenience, two different Tables of Contents are provided. One lists the products by type-Line
Driver, Sense Amplifier, etc.-and the other lists the products alphanumencally by part number. Product
selection guides and a complete product applications section are also included.
Voltage Comparators
Level Translators/Buffers
Memory/Clock Drivers
Line 0 rivers/Receivers
Peripheral/Power Drivers
Display Drivers
Sense Amplifiers
Analog Switches
New Products
Applications
Physical Dimensions/Def. of Terms
National dDflS not assume any responsibility for use of any
CirCUliI)'
© 1974 National Semiconductor Corp
described, no CirCUit patent licenses are Implied, and National reserves the nght, at any il,me without notice, to change said CIrcuitry
Ordering Information
The ordering information for National deVices covered
LM
-,
139
-r-
In
this catalog is as follows:
F
LPAC~GE
L -_ _ _ _ _ _ _ _
DEVICE NUMBER
' - - - - - - - - - - - - - DEVICE FAMILY
DEVICE FAMILY
AH - Analog Hybrid
AM - Analog Monolithic
DH - DIgital Hybrids
DM - Digital Monolithic
LF
Linear FET
LH - Linear Hybrid
LM - Linear Monolithic
LX - Transducer
MH - MOS Hybrid
MM - MOS Monolithic
PACKAGE
D F G H J K N W-
Glass/Metal Dual-In-Line Package
Flat Package (0_25" wide)
TO-8 (12 lead) Metal Can
TO-5 (multi-lead) Metal Can
Glass/Glass Dual-In-Line Package
TO-3 Power Package
Molded Dual-I n-Line Package
Flat Package (0_275" wide)
DEVICE NUMBER
3, 4 or 5 digit number.
Suffix Indicators:
A - Improved Electrical Specification
C - Reduced Temperature Range
Devices are listed in the table of contents
by device number. With most of National's
The 1 denotes a Military temperature range
ture range device (-25°C to +85°C), and
+70°C). i.e_ LM111/LM211/LM311_
alpha-numerically by device family (LH, LM, LX, etc.) and then
proprietary linear circuits, a 1-2-3 numbering system is employed.
device (_55°C to +125°C), the 2 denotes an Industrial temperathe 3 denotes a Commercial temperature range device (O°C to
Exceptions to this are some hybrid circuits which employ a "C" suffix to denote the commercial temperature
range; and second-source products which follow the original manufacturers numbering system, i.e. LM710/
LM710C or LM1414/L.M1514.
Interface circuits and sense amplifiers employ a 55 as the first two digits for the
range part, and a 75 for the commercial part, i.e. LM5520/LM7520. Display drivers
receivers employ a 78/88 prefix. The 78 appl i,es to the military part, and the 88 to
i.e. DM7830/DM8830. And digital products employ a 54 as the first two digits for the
range part, and a 74 for the commercial part, i.e. DM5406/DM7406.
ii
military temperature
and line drivers and
the commercial part,
military temperature
Table of Contents
Edge Index by Product Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alpha·Numerical Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ii
ix
PRODUCT GUIDES
Interface Cross Reference Guide
Voltage Comparator Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmission Line Driver and Receiver Product Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Driver Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LED Drive[ Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Switch Cross Reference Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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xv
xvi
xvii
xviii
xix
xx
VOLTAGE COMPARATORS - SECTION 1
LF 111 Voltage Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LF211 Voltage Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LF311 Voltage Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LH2111 Dual Voltage Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LH2211 Dual Voltage Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LH2311 Dual Voltage Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM106 Voltage Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LMll1 Voltage Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM119 High Speed Dual Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM139 Quad Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM 139A Low Offset Voltage Quad Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM 160 High Speed Differential Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM161 High Speed Differential Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM206 Voltage Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM211 Voltage Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM219 High Speed Dual Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM239 Quad Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM239A Low Offset Voltage Quad Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM260 High Speed Differential Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM261 High Speed Differential Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM306 Voltage Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM311 Voltage Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ' ..
LM319 High Speed Dual Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM339 Quad Comparator ...... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM339A Low Offset Voltage Quad Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM360 High Speed Differential Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM361 High Speed Differential Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM529 High Speed Differential Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM710 Voltage Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM710C Voltage Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM711 Dual Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM711C Dual Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM760 High Speed Differential Voltage Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM1414 Dual Differential Voltage Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM1514 Dual Differential Voltage Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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1-1
1-1
1-1
1-7
1-7
1-7
1-9
1-15
1-25
1-29
1-34
1-37
1-39
1-9
1-15
1·25
1-29
1-34
1-37
1-39
1-12
1-20
1-27
1-29
1-34
1-37
1-39
1-39
1-41
1-44
1-47
1-50
1-37
1-53
1-53
LEVEL TRANSLATORS/BUFFERS - SECTION 2
DH0034
DM5406
DM5407
DM5416
High Speed Dual Level Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hex I nverter Buffer/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hex Buffer/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hex Inverter Buffer/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1
2-4
2-6
2-4
iii
LEVEL TRANSLATORS/BUFFERS - SECTION 2 (CONTINUED)
DM5417 Hex Buffer/Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM5426 Quad 2·1 nput TTL·MOS I nterface Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7406 Hex Inverter Buffer/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7407 Hex Buffer/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7416 Hex Inverter Buffer/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7417 Hex Buffer/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM74?6 Quad 2·lnput TTL·MOS Interface Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7800 Dual Voltage Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7802 High Speed MaS to TTL Level Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7806 High Speed MaS to TTL Level Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7810 Quad 2·lnput TTL-MaS Interface Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7811 Quad 2·lnput TTL-MaS Interface Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
OM7812 TTL·MOS Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7819 Quad 2·lnput TTL-MaS AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM8800 Dual Voltage Translator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8802 High Speed MaS to TTL Level Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM8806 High Speed MaS to TTL Level Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM8810 Quad 2·lnput TTL·MOS Interface Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8811 Quad 2·lnput TTL·MOS Interface Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8812 TTL·MOS Hex Inverter .................. '. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM88L12 TTL·MOS Hex Inverter/Interface Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM8819 Quad 2·lnput TTL·MOS AND Gate'. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2·6
2·8
2·4
2·6
2-4
2·6
2·8
2·10
7·1
7·1
2·13
2·13
2·13
2·18
2·10
7·1
7·1
2·13
2·13
2·13
2·16
2·18
MEMORY/CLOCK DRIVERS - SECTION 3
DH3467C Quad PNP Core Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DH3725C Quad NPN Core Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM55325 Memory Driver ..-".-;-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM75324 Memory Driver with Decode Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM75325 Memory Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .'
MH0007 DC Coupled MaS Clock Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MH0009 DC Coupled Two Phase MaS Clock Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MH0012 High Speed MaS Clock Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MH0013 Two Phase MaS Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MH0025 Two Phase MaS Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MH0026 5 MHz Two Phase MaS Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MH7B03 Two Phase Oscillator/Clock Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MH7807 Oscillator/Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MHB803 Two Phase Oscillator/Clock Driver ........... _ ................ _ . . . . . . . . . . ..
MH8804 Quad MaS Memory Driver ..... _ .... _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MH8805 Dual MaS Memory Driver _ .... _ ...... __ . _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . _
MH8807 Oscillator/Clock Driver ........ _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MH8808 Dual High Speed MaS Clock Driver ..................... _ .......... '.' . . . ..
3·1
3·3
3·11
3·5
3·11
3·1 B
3·20
3·22
3·24
3·28
3·31
3·40
9-7
3-40
9-6
9-6
9-7
3-44
LINE DRIVERS/RECEIVERS - SECTION 4
DM7820 Dual Line Receiver .... _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . ..
DM7820A Dual Line Receiver ....... _ .... _ ........... _ ...... _ ......... _ . _ . . . ..
DM7822 Dual Line Receiver ................ _ ...... _ ................ _ .. _ . . . . . ..
DM7830 Dual Differential Line Driver , ..... _ . _ .... _ . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7831 TRI-STATE® Line Driver .......... _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7832 TRI-STATE® Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ .... _
DM7833 Quad TRI-STATE® Transceiver .............. _ ................ _ . . . . . . . . ..
DM7834 Quad TRI-STATE® Transceiver _ .... _ .... _ . _ .... _ . . . . . . . . . . . . . . . . . . . . . . ..
DM7835 Quad TRI-STATE® Transceiver _ ................ _ . . . . . . . . . . . . . . . . . . . . . . ..
DM7836 Quad NOR Unified Bus Receiver ... _ ......... .'. . . . . . . .. . . . . . . . . . . . . . . . . ..
DM7837 Hex Unified Bus Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7838 Quad Unified Bus Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7839 Quad TRI-STATE® Transceiver ........ _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8820 Dual Line Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8820A Dual Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM8822 Dual Line Receiver. : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
iv
4-1
4-4
4-8
4-11
4-14
4-14
9-1
9-1
9-1
4-19
4-21
4-23
9-1
4-1
4-4
4·8
LINE DRIVERS/RECEIVERS - SECTION 4 (CONTINUED)
DM8830 Dual Differential Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM8831 TRI·STATE® Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM8832 TR I·STA TE® Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM8833 Quad TRI-5TATE® Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM8834 Quad TRI-STATE® Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM8835 Quad TRI-STATE® Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM8836 Quad NOR Unified Bus Receiver
DM8837 Hex Unified Bus Receiver
DM8838 Quad Unified Bus Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . , .............. .
DM8839 Quad TRI-STATE® Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM163 Dual TRI·STATE® Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM363 Dual TRI-STATE® Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM363A Dual TRI·STATE® MOS Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM1488 Quad Line Driver
LM1489 Quad Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM1489A Quad Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM551 07 A Dual Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM55108A Dual Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM55109 Dual Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM55110 Dual Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM55121 Dual Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM55122 Triple Line Receiver
LM55150 Triple Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM55154 Triple Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM751 07 A Dual Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM75108A Dual Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .' .. .
LM75109 Dual Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM75110 Dual Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM75121 Dual Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM75122 Triple Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM75123 Dual Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM75124 Triple Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM75150 Dual Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM75154 Triple Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM75207 Dual Line Receiver
LM75208 Dual Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4·11
4-14
4-14
9·1
9-1
9-1
4·19
4-21
4·23
9-1
4-30
4·30
4-30
4-25
4·28
4·28
4-30
4·30
4-37
4-37
4:40
4-42
9-4
9-4
4-30
4-30
4-37
4-37
4-40
4-42
4-45
4-47
9-.4
9-4
4-30
4·30
PERIPHERAL/POWER DRIVERS - SECTION 5
DH0006 Current Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DH0008 High Voltage High Current Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , .....
DHOOll High Voltage High Current Driver . . . . . . . . . . . . . . . . . . . , .............. , .....
DHOO16 High Voltage High Current Driver. , ... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . , .....
DH0017 High Voltage High Current Driver ... , . . . . . . . . . . . . . . . . . . . . , ......... , .....
DH0018 High Voltage High Current Driver . . . . . . . . . . . . . . . . . . . . . . , ...... , .... , .. , ..
DH0028 Hammer Driver ..................................... , .. , ...... , .....
DH0035 PIN Diode Switch Driver .. , . . . . . . . . . . . . . . . . . . . . . . . . . . . , ......... , .....
LM350 Dual Peripheral Driver . . . . . . . . . . . . . . . . . . , .... , . . . . . . . . . . . . . . . . . . , .....
LM351 Dual Peripheral Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM3611 Dual Peripheral Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM3612 Dual Peripheral Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM3613 Dual Peripheral Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM3614 Dual Peripheral Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM55325 Memory Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM75324 Memory Driver with Decode Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM75325 Memory Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM75450 Dual Peripheral Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM75451 Dual Peripheral Driver
LM75452 Dual Peripheral Driver
LM75453 Dual Peripheral Driver
LM75454 Dual Peripheral Driver
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
5-1
5-4
5-7
5-10
5-10
5-10
5-13
5-15
5-53
5-25
5-17
5-17
5-17
5-17
3-11
3-5
3-11
5-23
5-25
5-25
5-25
5-27
v
DISPLAY DRIVERS - SECTION 6
DM5441A BCD to Decimal Decoder/Nixie™ Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM5445 BCD to Decimal Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM5446A BCD to 7·Segment Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM5447A BCD to 7-Segment Decoder/Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM5448 BCD to 7·Segment Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54141 BCD to Decimal Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54145 BCD to Decimal Decoder/Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7441A BCD to Decimal Decoder/Nixie™ Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "
DM7445 BCD to Decimal Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7446A BCD to 7·Segment Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7447 A BCD to 7·Segment Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7448 BCD to 7·Segment Decoder/Driver .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM74141 BCD to Decimal Decoder/Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM74145 BCD to Decimal Decoder/Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM75491 MOS·to·LED Quad Segment Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM75492 MOS·to-LED Hex Digit Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM75493 Quad LED Segment Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM75494 Hex Digit Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7856 BCD to 7-Segment LED Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7858 BCD to 7·Segment LED Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7880 High Voltage 7-Segment Decoder/Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7887 8·Digit High Voltage Anode Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7889 8-Digit High Voltage Cathode Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7897 8-Digit High Voltage Anode Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8856 BCD to 7·Segment LED Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8857 BCD to 7·Segment LED Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8858 BCD to 7·Segment LED Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8859 TLL Compatible Hex LED Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8861 MOS to LED 5·Segment Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8864 LED Cathode Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8865 LED Cathode Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8866 LED Cathode Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8869 TTL Compatible Hex LED Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8880 High Voltage 7·Segment Decorder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8884A High Voltage Cathode Decorder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8885 MOS to High Voltage Cathode Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8887 8·Digit High Voltage Anode Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8889 8-Digit High Voltage Cathode Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8897 8·Digit High Voltage Anode Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
6·1
6·3
6·5
6-5
6·5
6-10
6·3
6·1
6·3
6-5
6·5
6·5
6-10
6·3
6-12
6-12
6·15
6-17
6-19
6-19
6·30
6·37
6-37
6·37
6·19
6·19
6·19
6·23
6-25
6·28
6·28
6-28
6-23
6·30
6·33
6-35
6·37
6·37
6·37
SENSE AMPLI FI ERS - SECTION 7
DM7802 Dual High Speed MaS Sense Amplifier ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7806 Dual High Speed MaS Sense Amplifier .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8802 Dual High Speed MaS Sense Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8806 Dual High Speed MOS Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM163 Dual TRI-STATE® MOS Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM165 MOS Sense Amplifier (MOS to TTL Converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM 166 MaS Sense Amplifier (MOS to TTL Converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM 167 MOS Sense Amplifier (MOS to TTL Converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM168 MOS Sense Amplifier (MOS to TTL Converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM363 Dual TRI·STATE® MOS Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM363A Dual TRI·STATE® MaS Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM365 MOS Sense Amplifier (MOS to TTL Converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM366 MOS Sense Amplifier (MOS to TTL Converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM367 MOS Sense Amplifier (MOS to TTL Converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM368 MOS Sense Amplifier (MOS to TTL Converter). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM3625 Dual High Speed MOS Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM5520 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM5521 Dual Core Memory Sense Amplifier
LM5522 Dual Core Memory Sense Amplifier
vi
7-1
7·1
7·1
7-1
4-30
9-3
9-3
9·3
9·3
4·30
4·30
9·3
9·3
9·3
9-3
9·4
7·5
7·5
7·5
SENSE AMPLIFIERS - SECTION 7 (CONTINUED)
LM5523 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM5524 Dual' Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM5525 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM5528 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM5529 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
lM5534 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM5535 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM5538 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM5539 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM55107A Dual MOS Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM55108A Dual MOS Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM7520 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM7521 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM7522 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM7523 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM7524 Dual C9re Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM7525 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM7528 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM7529 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM7534 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM7535 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , .. .
LM7538 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM7539 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM75107A Dual MOS Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM75108A Dual MOS Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM75207 Dual MOS Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM75208 Dual MOS Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7·5
7-5
7-5
7-5
7·5
7-5
7-5
7-5
7·5
4·30
4·30
7·5
7-5
7-5
7-5
7-5
7-5
7·5
7·5
7·5
7·5
7-5
7-5
4-30
4-30
4-30
4·30
ANALOG S'!VITCHES - SECTION 8
DPDT MOS Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Quad SPST MOS Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8·1
Dual DPST-TTL/DTL Compatible MOS Analog Switch .......................... . 8-1
Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ' ........... . 8·4
Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8·4
Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8·4
Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8·4
Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8·4
Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8·4
Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8·4
Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . 8-4
Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8·4
Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8·4
DPST Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8·11
Low Cost Analog Current Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13
Silicon N·Channel High Speed Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20
Silicon N-Channel High Speed Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8·20
Silicon N-Channel High Speed Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8·20
6-Channel MOS Multiplex Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8·22
AM370~ 8-Channel MOS Analog Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8·24
LF1650 Quad JFET Analog SWitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8·27
AH0014
AH0015
AH0019
AH0126
AH0129
AH0133
AH0134
AH0139
AH0140
AH0141
AH0142
AH0143
AH0144
AH0145
AH0146
AH0151
AHO,52
AH0153
AH0154
AH0161
AH0162
AH0163
AH0164
AH2114
AH5009
AM1000
AM1001
AM1002
AM2009
vii
ANALOG SWITCHES - SECTION 8 (CONTINUED)
LF2650 Ouad JFET Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LF3650 Ouad JFET Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM450 MaS Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM451 MaS Analog Switch~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,
MM452 MaS Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM454 4-Channel Commutator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM455 MaS Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4504 6-Channel MaS Multiplex Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM550 MaS Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM551 MaS Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM552 MaS Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM554 4-Channel Commutator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM555 MaS Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . . . ..
MM5504 6-Channel MaS Multiplex Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8·27
8-27
8·31
8-31
8-31
8-35
8-31
8-22
8-31
8-31
8-31
8-35
8-31
8-22
NEW PRODUCTS - SECTION 9
APPLICATIONS - SECTION 10
AN-22 Integrated Circuits for Digital Data Transmission
AN-33 Analog-Signal Commutation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AN-38 Appl ications of MaS Analog Switches .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AN-49 Pin Diode Drivers .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AN-53 High Speed Analog Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AN-76 Applying Modern Clock Drivers to MaS Memories. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AN-83 Data Bus and Differential Line Drivers and Receivers. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AN-84 Driving 7-Segment Gas Discharge Display Tubes with NS Circuits. . . . . . . . . . . . . . . . . . . ..
AN-87 Comparing the High Speed Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-99 Driving 7-Segment LED Displays with NS Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,
AN-l08 Transmission Line Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .,. . . . ..
PHYSICAL DIMENSIONS/DEFINITIONS OF TERMS - SECTION 11
viii
10-1
10-17
10-23
10-31
10-37
10-43
10-55
10-67
10-71
10-77
10-88
Alpha-Numerical Index
AH0014 DPDT Mas Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0015 Quad SPST MaS Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0019 Dual DPST-TTL/DTL Compatible MaS Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0126 Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0129 Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0133 Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0134 Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0139 Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0140 Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0141 Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0142 Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0143 Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0144 Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0145 Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0146 Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0151 Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0152 Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0153 Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0154 Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0161 Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0162 Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0163 Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0164 Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH2114 DPST Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH5009 Low Cost Analog Current Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AM1000 Silicon N-Channel High Speed Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AM1001 Silicon N-Channel High Speed Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AM1002 Silicon N-Channel High Speed Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AM2009 6-Channel MaS Multiplex Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AM3705 8-Channel MaS Analog Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DH0006 Current Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DH0008 High Voltage High Current Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DH0011 High Voltage High Current Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DH0016 High Voltage High Current Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DH0017 High Voltage High Current Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DH0018 High Voltage High Current Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DH0028 Hammer Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DH0034 High Speed Dual Level Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DH0035 PIN Diode Switch Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DH3467C Quad PNP Core Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DH3725C Quad NPN Core Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM5406 Hex Inverter Buffer/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM5407 Hex Buffer/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM5416 Hex I nverter Buffer/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM5417 Hex Buffer/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM5426 Quad 2-lnput TTL-MaS Interface Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM5441A BCD to Decimal Decoder/Nixie™ Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM5445 BCD to Decimal Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM5446A BCD to 7-Segment Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM5447 A BCD to 7-Segment Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM5448 BCD to 7-Segment Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54141 BCD to Decimal Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54145 BCD to Decimal Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7406 Hex Inverter Buffer/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7407 Hex -Buffer/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7416 Hex Inverter Buffer/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7417 Hex Buffer/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '...... .
DM7426 Quad 2-lnput TTL-MaS Interface Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-1
8-1
8-1
8-4
8-4
8-4
8-4
8-4
8-4
8-4
8-4
8-4
8-4
8-4
8-4
8-4
8-4
8-4
8-4
8-4
8-4
8-4
8-4
8-11
8-13
8-20
8-20
8-20
8-22
8-24
5-1
5-9
5-7
5-10
5-10
5-10
5-13
5-13
5-15
3-1
3-3
2-4
2-6
2-4
2-6
2-8
6-1
6-3
6-5
6-5
6-5
6-10
6-3
2-4
2-6
2-4
2-6
2-8
ix
DM7441A BCD to Decimal Decoder/Nixie™ Driver' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7445 BCD to Decimal Decoder/Driver . . . . . . . . . . . . . . . . '. . . . . . . . . . . . . . . . . . . . . . . ..
DM7446A BCD to 7·Segment Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7447A BCD to 7·Segment Decoder/Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7448 BCD to 7·Segment Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM74141 BCD to Decimal Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM74145 BCD to Decimal Decoder/Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM75491 MOS·to·LED Quad Segment Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "
DM75492 MOS·to·LED Hex Digit Driver .. " .... " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM75493 Quad LED Segment Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM75494 Hex Digit Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "
DM7800 Dual Voltage Translator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7802 Dual High Speed MOS Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7806 Dual High Speed MOS Sense Amplifier ., . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7810 Quad 2·lnput TTL·MOS Interface Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7811 Quad 2·lnput TTL·MOS Interface Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7812 TTL·MOS Hex Inverter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7819 Quad 2·lnput TTL·MOS AND Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7820 Dual Line Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7820A Dual Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7822 Dual Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "
DM7830 Dual Differential Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : . . . . . . . . . . . . ..
DM7831 TRI·STATE® Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7832 TRI·STATE® Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7833 Quad TRI·STATE® Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7834 Quad TRI·STATE® Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7835 Quad TRI·STATE® Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7836 Quad NOR Unified Bus Reciever .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7837 Hex Unified Bus Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7838 Quad Unified Bus Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7839 Quad TRI·STATE® Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7856 BCD to 7·Segment LED Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7858 BCD to 7·Segment LED Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7880 High Voltage 7·Segment Decoder/Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7887 8·Digit High Voltage Anode Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7889 8·Digit High Voltage Cathode Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7897 8·Digit High Voltage Anode Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8800 High Voltage 7·Segment Decoder/Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8802 Dual High Speed MOS Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8806 Dual High Speed MOS Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8810 Quad 2·lnput TTL·MOS Interface Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8811 Quad 2·lnput TTL·MOS I nterface Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8812 TTL·MOS Hex Inverter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM88L12 TTL·MOS Hex Inverter/Interface Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " ...
DM8819 Quad 2·lnput TTL·MOS AND Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8820 Dual Line Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8820A Dual Line Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8822 Dual Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . .'. . . . . . . . . . . . . . . . . . . . . . ..
DM8830 Dual Differential Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8831 TRI·STATE® Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : ........
DM8832 TRI·STATE® Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM8833 Quad TRI·STATE® Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8834 Quad TRI·STATE® Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "
DM8835 Quad TRI·STATE® Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8836 Quad NOR Unified Bus Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM8837 Hex Unified Bus Reciever. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8838 Quad Unified Bus Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8839 Quad TRI·STATE® Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8856 BCD to 7·Segment LED Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "
DM8857 BCD to 7·Segment LED Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8858 BCD to 7·Segment LED Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
x
6·1
6·3
6·5
6·5
6·5
6·10
6·3
6·12
6·12
6·15
6·17
2·10
7·1
7·1
2·13
2·13
2·13
2·18
4·1
4-4
4·8
4·11
4·14
4·14
9·1
9·1
9·1
4·19
4·21
4·23
9·1
6·19
6·19
6·30
6·37
6·37
6·37
2·10
7·1
7·1
2·13
2·13
2·13
2·16
2·18
4·1
4·4
4·8
4·11
4·14
4·14
9,1
9·1
9·1
4·19
4·21
4·23
9·1
6·19
6·19
6·19
DM8859 TTL Compatible Hex LED Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-23
DM8861 MOS to LED 5-Segment Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-25
DM8864 9-Digit LED Driver ........ ,. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-28
DM8865 LED Cathode Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6·28
DM8866 7·Dlgit LED Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-28
DM8869 TTL Compatible Hex LED Driver. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . 6-23
DM8880 High Voltage 7-Segment Decoder/Dnver. . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . .. 6·30
DM8884A High Voltage Cathode Decoder/Dnver . ~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-33
DM8885 MOS to High Voltage Cathode Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6·35
DM8887 8-Digit High Voltage Anode Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . .. 6-37
DM8889 8-Digit High Voltage Cathode Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-37
DM~897 8-Digit High Voltage Anode Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-37
LFlll Voltage Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . •. . . . . . . . . . . . .. 1-1
LF211 Voltage Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-1
LF311 Voltage Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1·1
LF1650 Quad JFET Analog SWitch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-21
LF2650 Quad JFET Analog SWitch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-27
LF3650 Quad JFET Analog SWitch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8·27
LH2111 Dual Voltage Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1·7
LH2211 Dual Voltage Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1·7
LH2311 Dual Voltage Comparator . . . . . . . . . . . . . . . . . . . . . . '. . . . . . . . . . . . . . . . . . . . . . . .. 1-7
LM106 Voltage Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1·9
LMlll Voltage Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-25
LMl19 High Speed Dual Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25
LM139 Quad Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-30
LM139A Low Offset Voltage Quad Comparator
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-34
LM160 High Speed Differential Comparator .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-37
LM161 High Speed Differential Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . .. 1-39
LM163 Dual TRI-STATE® Line Receiver . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . • 1-39
LM165 MOS Sense Amplifier (MOS to TTL Converter). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-3
LM166 MaS Sense Amplifier (MaS to TTL Converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
LM167 MOS Sense Amplifier (MaS to TTL Converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
LM168 MOS Sense Amplifier (MaS to TTL Converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-;3
LM206 Voltage Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '.•.............. 1-9
LM211 Voltage Comparator . . . . . . . . . . . . . . . . . . . . . _ .......... '. . . . . . . . . . . . . . . . . . . 1-15
LM219 High Speed Dual Comparator. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25
LM239 Quad Comparator. . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . _ .... . 1-29
LM239A Low Offset Voltage Quad Comparator . .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-34
LM260 High Speed Differential Comparator ... .............. . . . . . . . . . . . . . . . . . . . . 1-37
LM261 High Speed Differential Comparator. . . . . .. .. ...... . . . . . . . . . . . . . . . . . . . . . . . 1-39
LM265 MOS Sense ArT)pllfler (MaS to TTL Converter) . . . . . .. ........ . .............. . 9-3
LM266 MOS Sense Amplifier (MOS to TTL Converter) . . .. .... ... . . . . . . . . . . . . . . . . . . . 9-3
LM267 MaS Sense Amplifier (MaS to TTL Converter). . .................•..... . .... . 9-3
LM268 MaS Sense Amplifier (MaS to TTL Converter) . . .. ........ .. . .............. . 9-3
LM306 Voltage Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-39
LM311 Voltage Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
LM319 High Speed Dual Comparator .. .............. . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27
LM339 Quad Comparator. . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29
LM339A Low Offset Voltage Quad Comparator .. .... ......... . ................. . 1-34
LM350 Dual Peripheral Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
LM351 Dual Peripheral Dnver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
LM360 High Speed Differential Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-37
LM361 High Speed Differential Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-39
LM363 Dual TRI-STATE® Line Receiver ............... . . . . . . . . . . . . . . . . . . . . . . . . . 4-30
LM363A Dual TRI-STATE® MaS Sense f-mplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30
LM365 MaS Sense Amplifier (MaS to TTL Converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
LM366 MOS Sense Amplifier (MaS til TTL Converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
LM367 MOS Sense Amplifier (MOS to TTL Converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
LM368 MOS Sense Amplifier (MaS to TtL Converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
LM529 High Speed Differential Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-39
LM710 Voltage Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.41
xi
LM710C Voltage Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM711 Dual Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . ..
LM711C Dual Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM760 High Speed Differential Voltage Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM1414 Dual Differential Voltage Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . .
LM 1488 Quad Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM1489 Quad Line Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM1489A Quad Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '. . . . . . . . . . . . . . . . . . ..
LM1514 DualDifferential Voltage Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM3611 Dual Peripheral Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM3612 Dual Peripheral Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM3613 Dual Peripheral Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .'.':. . . . . . . . . . . . . ..
LM3614 Dual Peripheral Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM3625 Dual High Speed MOS Sense Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM5520 Dual Core Memory Sense Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM5521 Dual Core Memory Sense Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .•
LM5522 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM5523 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM5524 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . .
LM5525 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM5528 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM5529 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM5534 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM5535 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM5538 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM5539 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM55107A: Dual Line Receiver ........... ! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM55108A Dual Lme Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM55109 Dual Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM55110 Dual Line Driver ...................... .' . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM55121 Dual Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . • . • . . • . • . . . . . . . . . . . . . . • . ..
LM55122 Triple Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . • . . ..
LM55325 Memory Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . • . . . . . . . . . . . . . '. . . . . ..
LM7520 Dual Core Memory Sense Amplifier ............•.......•..................
LM7521 Dual Core Memory Sense Amplifier .......................•.•.....•.•.....
LM7522 Dual Core Memory Sense Amplifier . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM7523 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM7524 Dual Core Memory Sense Amplifier .......•......•........................
LM7525 Dual Core Memory Sense Amplifier ...................•.......••.....•....
LM7528 Dual Core Memory Sense Amplifier .....•...•.........•...................
LM7529 Dual Core Memory Sense Amplifier ...................•....•..............
LM7534 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . .
LM7535 Dual Core Memory Sense Amplifier .....•.•.................•.•...........
LM7538 Dual Core Memory Sense Amplifier .....••.•................•.............
LM7539 Dual Core Memory Sense Amplifier ............••.............•....•......
LM75107A Dual Line Receiver. . . . . . . . . . . . . . . . • . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . ..
LM75108A Dual Line Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . • . . . . ..
LM75109 Dual Line Driver . . . . . . . . . . . . . . . . . . . . • . . . . • . . . . . . . . . . . . . . . . . . . . . . . . .
LM75110 Dual Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM75121 Dual Line Driver. . . . . . • . . • . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . • ..
LM75122 Triple Line Receiver . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM75123 Dual Line Driver . . . . • . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . '......
LM75124 Triple Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM75150 Dual Line Driver ...............• : •....•.•..•....... : .............. :.
LM75154 Quad Line Receiver. . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM75207 Dual MOS Sense Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM75208 Dual MOS Sense Amplifier. . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . ..
LM75324 Memory Driver with Decode Inputs ..... : .....•................ : . . • . . . . . ..
LM75325 Memory Driver. . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . ..
LM75450 Dual Peripheral Driver •............................................•.
LM75451 Dual Peripheral Driver .............•...•....•........................
xii
1-44
1-47
1-50
1-37
1-53
4-25
4-28
4-28
1-53
5-16
5-16
5-16
5-16
9-4
7-5
7-5
7-5
7-5
7-5
7-5
7-5
7-5
7-5
7-5
7-5
7-5
4-30
4-30
4-37
4-37
4-40
4-42
3-11
7-5
7-5
7-5
7-5
7-5
7-5
7-5
7-5
7-5
7·5
7-5
7-5
4-30
4-30
4-37
4-37
4-40
4-42
4-45
4-47
9-4
9-4
4-30
4-30
3-5
3-11
5-21
5·23
LM75452 Dual Peripheral Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM75453 Dual Peripheral Driver ........... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM75454 Dual Peripheral Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MHOOO7 DC Coupled MOS Clock Driver. : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MH0009 DC Coupled Two Phase MOS Clock Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MH0012 High Speed MOS Clock Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . ..
MH0013 Two Phase MOS Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MH0025 Two Phase MOS Clock Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MH0026 5 MHz Two Phase MOS Clock Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MH7803 Two Phase Oscillator/Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MH7807 Oscillator/Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MHB;803 Two Phase Oscillator/Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MH8804 Quad MOS Memory Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MH8805 Dual MOS Memory Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MH8807 Oscillator/Clock Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MH8808 Dual High Speed MOS Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "
MM450 MOS Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM451 MOS Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM452 MOS Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM454 4-Channel Commutator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM455 MOS Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
M1I(I4504 6·Channel MOS MUltiplex Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM550 MOS Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM551 MOS Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM552 MOS Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . ..
MM554 4-Channel Commutator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM555 MOS Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5504 6-Channel MOS Multiplex Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5·23
5-23
5·26
3·18
3·20
3·22
3·24
3·28
3-31
3-40
9-7
3-40
9·6
9·6
9·7
3-44
8·31
8·31
8-31
8-35
8-31
8-22
8·31
8-31
8-31
8-35
8-31
8·22
xiii
Interface Cross Reference Guide
DEVICE
NUMBER
NATIONAL
PIN-FOR-PIN
EQUIVALENT
NATIONAL
FUNCTIONAL
EQUIVALENT
Texas Instruments
SN5500F
SN5524J
SN5525J
SN7500F
SN75154J
LM5524J
LM5524J
LM5525J
LM7524J
LM7524J
LM7524J
SN75Dl F
SN7502F
SN7520J
SN7520N
SN7521J
SN7521 N
SN7522J
SN7522N
SN7523J
SN7523N
SN7524J
SN7524N
SN7525J
SN7525N
SN7528J
SN7528N
SN7529J
SN7529N '
SN52710J
SN52710L
SN52710N
SN52710S
SN52711J
SN52711 L
SN52711N
SN52711S
SN55107J
SN55108J
SN55109J
SN55110J
SN55182J
SN55183J
SN72710J
SN72710L
SN72710N
SN72710S
SN72711 J
SN72711 L
SN72711N
SN72720N
SN72811S
SN75100L
SN75107J
SN75107N
SN75108J
SN75108N
SN75109J
SN75109N
SN75110J
SN75110N
SN75121J
SN75121N
SN75122J
SN75122N
SN75123J
SN75123N
SN75124J
SN75124N
SN75150J
SN75150N
~
DEVICE
NUMBER
LM7520J
LM7520N
LM7521J
LM7521N
LM7522J
LM7522N
LM7523J
LM7523N
LM7524J
LM7524N
LM7525J
LM7525N
LM7528J
LM7528N
LM7529J
LM7529N
LM710H
LM710H
LM710H
LM710H
LM711H
LM711H
LM711H
LM711H
LM55107J
LM55108J
LM55109J
LM55110J
DM7820AJ
DM7830J
LM710CN
LM710CH
LM710CN
LM710CH
LM711CN
LM711CH
LM711CN
LM1414N
LM711CH
DM8820D
LM75107J
LM75107N
LM75108J
LM75108N
LM75109J
LM75109N
LM75110J
LM75110N
LM75121J
LM75121N
LM75122J
LM75122N
LM75123J
LM75123N
LM75124J
LM75124N
LM75150J
LM75150N
SN75154N
SN75182J
SN75182N
SN75183J
SN75183N
SN75324J
SN75324N
SN75325J
SN75325N
SN75450AN
SN75450N
SN75451AP
SN75451P
SN75452P
SN75453P
SN75454P
SN75491N
SN75492N
SN75207J
SN75207N
SN75208J
SN75208N
NATIONAL
PIN-FOR-PIN
EQUIVALENT
NATIONAL
FUNCTIONAL
EQUIVALENT
LM75154J
LM75154N
DM8820AJ
DM8820AN
DM8830J
DM8830N
LM75324J
LM75324N
LM75325J
LM75325N
LM75450N
LM75450N
LM75451N
LM75451N
LM75452N
LM75453N
LM75454N
DM75491N
DM75492N
LM75207J
LM75207N
LM75208J
LM75208N
N8T13F
N8T14B
N8T14F
N8T238
N8T24B
N8T258
NE518A
NE518G
NES18K
NE526A
NE526G
NE526K
NE529A
NE529K
S5710T
S5711 K
S5711T
SE518A
SE518G
SE518K
SE526A
SE526G
SE526K
SE529K
LM1414J
Fairchild
Motorola
MC1414L
MC1440F
MC1440G
MC1440L
MC1441F
MC1441L
MC1488L
MC1489AL
MC1489L
MC1514L
MC1580L
MC1582L
MCl583L
MC1584L
MC1710CF
MC1710CG
MC1710CL
MC1710F
MC1710G
MC1710L
MC1711CF
MC1711CG
MC1711CL
MC1711F
MC1711G
MC1711L
LM7524J
LM7524J
LM7524J
LM7524J
LM7524J
LM1488J
LM1489AJ
LM1489J
LM1514J
DM7831J
DM7830J
DM7820J
DM7820AJ
LM710CH
LM710CH
LM710CH
LM710H
LM710H
LM710H
LM711CH
LM711CH
LM711CH
LM711H
LM711H
LM711H
Signetics
DM8880N
N5710A
N571QT
N5711A
N5711K
N7520B
N7521 B
N7522B
N7523B
N7524B
N7525B
N8T13B
DEVICE
NUMBER
DM8880N
LM710CN
LM710CH
LM711CN
LM711CH
LM7520N
LM7521 N
LM7522N
LM7523N
LM7524N
LM7525N
LM75121 N
U31962051 X
U31962059X
U31962151X
U31962159X
U31962251 X
U31962259X
U4L961451X
U4L961459X
U4L961551X
U4L961559X
U5B7710312
U5B7710393
USF7711312
U5F7711393
U5F7734312
U5F7734393
U6A7710312
U6A771 0393
U6A7711312
U6A7711393
U6A7750312
U6A7750393
U6A7760312
U6A7760393
U7B7524392
U7B7525393
U7B7761391
U7B7761392
U7B7761393
U7B961451X
U7B961459X
U7B961551X
U7B961559X
U7B961651X
U7B961659X
U7B961751X
U7B961759X
U7B964451X
9p!n~
NATIONAL
PIN-FOR-PIN
EQUIVALENT
NATIONAL
FUNCTIONAL
EQUIVALENT
LM75121J
LM75122N
LM75122J
LM75123N
LM75124N
LM3625N
LM306H
LM306H
LM306H
LM306H
LM306H
LM306H
LM361N
LM361H
LM710H
LM711H
LM711H
LM106H
LM106H
LM106H
LM106H
LM106H
LM106H
LM161H
DM7820D
DM8820N
DM7830D
DM8830N
DM7820D
DM8820N
DM7830D
DM8830D
DM7820D
DM8820N
LM710AH
LM710CH
LM711H
LM711CH
LM111H
LM311H
LM710AH
LM710CN
LM711H
LM711CN
LM111H
LM311H
LM160J
LM360J
LM7524J
LM7525J
LM7524J
LM7524J
LM7525J
DM7830D
DM8830N
DM7820D
DM8820N
LM1488J
LM1488J
LM1489AJ
LM1489AJ
DHOO11H
9:>U9J9j.9H SSOJ::) 9:>ep9:a.ul
Voltage Comparator Guide
><
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I
Supply
Device
Temperature
Range*
OTLfTTL
Fanout
(Volts)
v+ -=
Current
Input Offset
Current
Input Offset
Voltage
(+25G C)
1+2So C)
(+25°C)
M",
M"
InputBIiiS
Voltage
Tvp
{pAl
lpAI
M"
(mV)
Response
TImet
TVp
{nsl
Voltage
Gam
Package Type
LM106
Military
10
+ 12
20
40 max
' 40k
TO-5 F P
lM206
Industrial
10
V- "'-3
20
40 max
40k
TO-5 F P
10
To -12
25
40 max
40k
TO-5 F P
lM306
LM111
lH2111 (Note 1)
LM211
lH2211 (Note 1 )
lM311
LH2311 (Note 1)
Commercial
Military
±tS
04
200
200k
TO·5 DIP F P
Industrial
To+5
04
200
lOOk
TO·5 DIP F P
06
200
200k
TO-5 DIP F P
40k
TO-5 DIP F P
LM119
Military
2 (each Side)
±1S
LM219
Industrial
2 (each Side)
To +5
LM319
CommerCial
2 (each sidel
LM139
Mdltary
LM239
Industrial
LM339
CommerCial
LM139A
Military
LM239A
Industrial
25
And GND
CommerCial
1.'
075
80
075
80
40k
TO-5 DIP F P
80
40k
TO 5 DIP
025
13/15
200k
DIP F P
DIP
And GND
25
050
13ps
200k
Or From
25
050
13/15
200k
DIP
025
13/1s
200k
DIP F P
·2
To +36
25
050
13/1s
200k
DIP
And GND
25
050
131J;
200k
DIP
LM339A
Commercial
LMl60
Military
±45
10
16
3k
TO·5 DIP F P
LM260
Industrial
To
10
16
3k
TO·5 DIP
LM360
Commercial
±65
15
16
3k
TO-5 DIP
LM161
MIlitary
"
10
12
3k
TO-5 DIP F P
LM261
Industrial
10
12
3k
TO·5 DIP
3k
TO·5 DIP
LM361
Commercial
LM710
Military
LM710C
Commercial
LM711
Military
LM711C
CommerCial
LM1514
Military
LM1414
Commercial
And +5
V+
V
=
+ 12
"'-6
Low offset voltage Quad comparator
with DTLlTTlloglc levels.
Very tllgh speed, outputs compatible
With DTL!TTL logiC levels
Very high speed, With individual
strobes, DTL/TTL compattble
12
1750
TO·5
25
40
1500
TO-5 DIP
40
1500
TO·S
40
1500
TO-5 DIP
individual strobes
30
1250
DIP
30
1000
DIP
Dual LM710 with separate strobes,
IndiVidual outputs
Single, differential In, Single output
75
10
15
*14
20
-7
25
=
supplV Operation, Input common
mode range Includes ground
40
100
"MIlitary -5S0Cto +12S"C
(fldustrlal -2S"CIO+8SoC
Commerc.al O°C to + 70Q C
High speed dual comparator
15
-6
V*
Single, With strobe, will work from
Single supply, low bias current
20
V* - * 12
=
Smgle comparator With strobe, hIgh
speed and senSitivity, large fanout
Quad comparator deSigned for Single
T: ±18
To ±15
Comments
Tvp
35
tReSpoflse time IS Speclf,ed for 100 mV step ",put wtth 5 mV overdnve
Note 1 DualyerslOflofdey,ce
Dual differential, common output,
Transmission Line Driver and Receiver Product Guide
DEVICE
DRIVER OR
RECEIVER
COMMON MODE OR DIFFERENTIAL
INPUT
THRESHOLD
OUTPUT
LEVELS
POWER
SUPPLY
DESCRIPTION AND COMMENTS
DM7820/DM8820
Receiver
Differential
200mV
TTL
+5.0
Dual ±15V Common Mode Range
DM7820A/DM8820A
Receiver
Differential
200mV
TTL
+5.0
High Performance DM7820
DM7822/DM8822
Receiver
Differential/Common Mode
TTL
+5.0
Dual E IA Standard RS232
DM7830/DM8830
Dnver
Differential
TTL
TTL
+5.0
Dual
DM7831/DM8831
Driver
Differential/Common Mode
TTL
TTL
+5.0
TRI-STATE@ DM7830
DM7832/DM8832
Dnver
Differential/Common Mode
TTL
TTL
+5.0
DM7831 Without VCC Clamp Diodes
LM55107/LM75107
Receiver
DifferentIal
25mV
TTL
±5.0
10 mV Threshold LM55107
LM55207/LM75207
Receiver
Differential
10mV
TTL
±5.0
10 mV Threshold LM55107
Open Collector LM55107
~2.0
to +20
Dual
LM55108/LM75108
R'ec€lver
Differential
25 mV
TTL
±5.0
LM55208/LM75208
Receiver
Differential
10mV
TTL
±5.0
10 mV Threshold LM55108
LM163/LM363
Receiver
Differential
25 mV
TTL
±5.0
TRI-STATE@ LM55107
LM163A/LM363A
Receiver
DIfferential
10mV
TTL
±5.0
10 mV Threshold LM163
LM55109/LM75109
Driver
Differential
TTL
6.0mA
±5.0
Dual
LM55110/LM75110
Driver
Differential
TTL
12mA
±5.0
12 mA LM551 09
LM55121/LM75121
Driver
Common Mode
TTL
TTL
+5.0
Dual 50n or Coax Driver
LM55122/LM75122
Receiver
Common Mode
0.8 to 2.0
TTL
+5.0
Trtple with HysteresIs
LM55123/LM75123
Dnver
Common Mode
TTL
TTL
+5.0
LM55121 for I BM Interface
LM55124/LM75124
Receiver
Common Mode
0.7 to 1.7
TTL
+5.0
LM55123 for IBM Interface
DM7834/DM8834
Transceiver
Common Mode
TTL
TTL
+5.0
Quad TRI-STATE@ Hysteresis
DM7835/DM8835
Transceiver
Common Mode
TTL
TTL
+5.0
DM7834 with Strobed Receiver
DM7839/DM8839
Transceiver
Common Mode
TTL
TTL
+5.0
Non-inverting DM7834
DM7833/DM8833
Transceiver
Common Mode
TTL
TTL
+5.0
DM7839 with Strobed Receiver
DM7131/DM8131
Receiver
Common Mode
0.97 to 2.65
TTL
+5.0
6-Blt Comparator with Hysteresis
DM7136/DM8136
Receiver
Driver
Common Mode
0.97 to 2.65
TTL
+5.0
Expandable DM7131
LM1488
Common Mode
TTL
±7.0V
±90to 15
LM1489
Receiver
Common Mode
0.75 to 1.5
TTL
+5.0
Quad EIA Standard RS232 with Hysteresis
LM1489A
Receiver
Common Mode
0.75 to 2.25
TTL
+5.0
Higher NOise ImmUnity LM1489
Quad EIA Standard RS232
Note: In applications devices grouped with Comparators and Sense Amplifiers may be used at line receivers. Also deVices grouped With Peripheral drivers may be used as line drivers.
For additional application information reference:
National Application Note 22, IC's for Digital Data TransJl)ission
National Application Note 83, Data Bus and Differential Line Drivers and Receivers
National Application Note 108, Transmission Line CharacterIStics
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Peripheral Driver Guide
"@, I
GENERAL DESCRIPTION
Output
Breakdown
Voltage
(Volts)
Nominal
Series or Device Number
VCC
(Volts)
Maximum
Output
Leakage
Maximum
Output
On
Current
Current
liLA)
(mA)
Maximum
Output Current
(Volts)
VOL (Max)
At
Typical
Propagation
Delay
(ns)
LM75450 Series (LM75450, LM350,
LM75451, LM75452, LM75453, LM75454)
5.0
30
100
300
0.7
15
LM3611 Senes (LM3611, LM3612, LM3613, LM3614)
5.0
80
100
300
0.7
130
CONNECTION DIAGRAMS
v"
V"
82
.,
81
'2
X2
.,
Xl
82
C2
E2
SUB
B1
C1
E1
GN.
Vee
.2
X2
.,
Xl
B2
C2
E2
SUB
B1
C1
E1
GND
TOP VIEW
TOP VIEW
LM350
LM75450
.2
X2
v"
B2
Xl
GN.
.,
81
.2
X2
Vee
82
Xl
GNo
.,
81
.2
X2
Vee
B2
Xl
GN.
.,
81
A2
X2
Xl
GNo
TOP VIEW
TOP VIEW
TOP VIEW
TOP VIEW
LM75451
LM3611
LM75452
LM3612
LM75453 (LM351)
LM3613
LM75454
LM3614
LED Driver Selection Guide
SEGMENT DRIVERS
C
0
M
M
0
N
C
A
T
H
0
D
E
c
0
M
M
0
N
A
N
0
D
E
DIGIT DRIVERS
EE,"""m
B'""""u B""'~u B""wou Ei,"""m
EE""""u
B,,"pm
B""""u B"~"u
B ""n
B,,",~n
E]"",,m EE'""""u B'""""u
B""""u
E]"",~n Ej,,="n Ej,,",,"n
50 rnA/SEG.
DM8861
50 rnA/SEG.
(SOURCE
OR
SINK)
DM75493
30 rnA/SEG.
(SOURCE)
DM75491
.(SOURCE
OR
SINK)
DM8857*
50 rnA/SEG.
(SOURCE)
DM8858*
50 rnA/SEG.
(SOURCE)
DM7443*
2 rnA/SEG.
(SOURCE)
DM8856*
6 rnA/SEG.
(SOURCE)
OM8859
40 rnA/SEG.
(SINK)
DM8869
40 rnA/SEG.
(SINK)
OM7446A*
40 rnAISEG.
(SINK)
DM7447A*
40 rnA/SEG.
(SINK)
DMBB66
50 rnA/DIG.
(SINK)
DM8865
50 rnA/DIG.
(SINK)
DM75494
180 rnA/DIG.
.(SINK)
DM75492
250 rnA/DIG.
(SINK)
DM75491
50 rnA/SEG.
(SOURCE
OR
SINK)
DM8861
DM8864
50 rnA/DIG.
(SINK)
50 rnA/SEG.
(SOURCE
OR
SINK)
"Decoded
ax
~I~
__________________________________________________________________________________________________
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031
Analog Switch Cross Reference Guide
~
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------------------------------------------------------------------------------------------------------------~
National also builds analog switches to custom or pin-tor-pin second source requirements. Consult your local National sales office.
DEVICE
NUMBER
FUNCTION
NATIONAL
FUNCTIONAL
eQUIVALENT
DAS2133
OAS2136
OAS2137
SPOT - 100 ohm
SPOT - 50 ohm
Quad SPST - 50 ohm
Dual SPST - 50 ohm
Dual SPST - 50 ohm
Dual SPST - 50 ohm
Dual SPST - 50 ohm
AH2114 (pm for pm)
AH0162
2-AH0152
AH0152
AH0152
AH0152
AH0152
Fairchild
A3F3700 (xxx)
A313701 (xxx)
A6J3705 (xxx)
A6J3708 (xxx)
HAG3001 (lxx)
HAG3OO2 (xxx)
4CH MOS SWItch
GCHMOSMUX
BCHMOSMUX
8CHMOSMUX
4PST IObsolete}
SPOT - 400 ohm
MM450 SerIes
AM2009
AM3705 (pm for pm)
AM3705 (pm for pm)
AHOO15
AHOO14, AHOO19
General Instrument
MEM2009
MEM2017
MEM3705
NC450
NC451
NC2114
NC2126
NC2l37
6CHMOSMUX
6CHMOSMUX
8CH MUX with Decode
Dual SPST - 500 ohm
Dual SPST - 100 ohm
SPOT - 100 ohm
SPOT - 50 ohm
SPOT - 20 ohm
AM2009
AM2009
AM3705
AH0152
AHOl34
AH2114
AH0162
AH0146
(pIn for pin)
(pm for pm)
(pm for pm)
(pm for pm)
Intersd
IH5001
IH5002
IH5003
IH5004
IH5009 thru
tHS024 Senes
OG126 thru
OGl64 Senes
SPST - 300hm
SPST - SOohm
Dual SPST - 30 ohm
Dual SPST - 50 ohm
TTL Compatible - JFET
Analog Current SWItches
TTL Compatible - JF ET
Analog Voltage SWItches
G114 thru
G124 Senes
Multiple P-MOS Transls!ors
1/2 AH0133
lt2 AH0152
AH0133
AH01S2
AH5009 thru
AHS024 Senes (pm for pml
AH0126 thruAHOl64 Senes
(Pin for pm - see-note 1)
MM450 thru MM454 Senes
and AM2009
Sthcomx
OG110
DGM111
OG112
DG116
OG118
OGl20
OG121
OGM122
DGM123
FUNCTION
NATIONAL
FUNCTIONAL
eQUIVALENT
Obsolete - see OG501
AMJ705
TTL Compatlbte - JFET
AH0126 d'lru
Siliconlx (Con't)
Dixon
DAS2114
OAS2126
DAS2128
DAS2132
DEVICE
NUMBER
Dual SPST - 400 ohm
Dual SPST - 400 ohm
Dual SPST - 400 ohm
Obsolete - see DG 172
Obsolete - see DG172
Obsolete - see OG502
Obsolete - see OG502
Dual 2CH MUX - 4000
Obsolete - see OG501
1/2 AHOO15
1/2 AHOO15
1/2 AH001S
1/2 AH001S
AHOO15
AHOO1S
2-AHOO15
AHOO15
AM3705
DG125
DGl26thlu
OGl64 Senes
DGl69
OG171
OG172
OG173
OG175
OG181
OG182
DG1B4
OG185
OG187
OG1BB
OGl90
DG191
OG400 Senes
OG501
OG502
DG503
DG506
OG507
OG510
OG511
G114 mru
G124 Senes
G125 thru
G135 Series
SI3OO1
SI3OO2
SI3705
DEVICE
NUMBER
FUNCTION
NATIONAL
FUNCTIONAL
EQUIVALENT
Teledyne Semiconductor (Amalco)
Analog Voltage Switches
Obsolete - see DG 173
SPST - tOO ohm
4CH MUX - 400 ohm
OPDT - 400 ohm
SPOT - 2QO ohm
Dual SPST - 30 ohm
Dual SPST - 80 ohm
Dual DPST - 30 ohm
Dual OPST - 80 ohm
SPOT -30ohm
SPOT -BOohm
Dual SPSl - 30 ohm
Dual SPOT - 80 ohm
Dual SPOT - 80 ohm
BCH MUX - 200 ohm
Dual 4CH MUX - 200 ohm
8CH MUX - 400 ohm
8CH MUX - 400 ohm
8CH MUX - 400 ohm
8CH MUX - 400 ohm
Dual 4CH MUX - 400 ohm
Multiple PMOS TranSIstors
MultIple J-FET TranSistors
OPST - SOO ohm
SPOT - 500 ohm
8CH MUX - 400 ohm
AHOl64 Senes
(pm for pm - see note 1 J
AHOO14
AM1000
AHOO15
AHOO14
1/2 AHOO15
AH0133
AHOl34
AHOl29
AH0126
AHOl44
AH0143
2-AH0144
2-AH0143
See note 2
AM3705
2-AHOO15
AM3705
AM3705
AM3705
AM3705
2-AHOO15
MM450 thru MM454 Senes
and AM2009
AH5009 thru
AH5024 Sertes
1/2-AH0019
1!2-AH0015
AM3705 (pm for pm)
2107BE
2110BE
21148F
21268G
2127BG
2128BG
2130BG
21378F
21388E
21398E
2141BF/BH
214SBE
21478E
SPOT - 500 ohm
OPST - 500 ohm
Quad SPST - 500 ohm
Dual SPST - 50 ohm
SPOT - 2QO ohm
Dual SPST - SOO ohm
Dual SPST - 500 ohm
OuaISPST-500ohm
Dual SPST - 50 ohm
Dual sps'T - sao ohm
1/2 AH0126
1/2 AHOl26
AH2l14 (pm for pm)
AH0162
AH0152
2-AH0152
AH0152
AH0146
NSB035 (pm for pml
AH0152
AH0152
AH0152
AH0152
lOCH MOS MUX
6CHMOSMUX
6CHMOSMUX
6CHMOSMUX
AM3705
AM2009
AM2009
AM2009 (Pin for pml
SPST - 100 ohm
SPST - 500 ohm
SPDT~l00ohm
Texas Instrument
TMS6000
TMS6002
TMS6005
TMS6009
Teledyne - Crystalomcs
CAG6
CAG7
CAG10
CAG13
CAG14
CAG20
CAG21
CAG22
CAG23
CAG24
CAG27
CAG30
CAG513
COAl
CDA2
CDA4
COA5
COA6
COA11
COA18
SPST - 100 ohm
SPOT - 100 ohm
SPST ~ 500 ohm
Dual SPST - SOO ohm
SPST - 500 ohm
Dual SPST - 500 ohm
Dual OPST - 50 ohm
Dual DPST - 300 ohm
Dual DPST - 500 ohm
Dual SPST - 300 ohm
Dual SPST - 100 ohm
SPST - 600 ohm
Dual SPST - 500 ohm
SPST - 100 ohm
Dual SPST - 300 ohm
SPST - 100 ohm
SPST - 200 ohm
SPST ~ 100 ohm
SPST - 100 ohm
SPST - 50 ohm -
1/2-AHOl34
AH0143
AM1000
AHOl34, 1/2 AHOO15
AM1000
AHOl34, 1/2 AHOO15
AHOl54
AHOl54, AHOO19
AHOO19
AHOl34, 1/2 AHQ015
AHOl34
1/4 AHOO15
1/2 AHOQ15
112 AHOl34
lt2 AHOO15
1/2 AHOl34
1/2 AHOl34
1/2 AHOl34
1/2 AHOl34
AM1000
Note 1: These deVices have additional letter deSignations after part
Natlol'\8l's corresponding pkg and temp range codes are
num~s_
IntarSlISt
Siliconix
Designations
Letter "A"
Letter "S"
lett~r "L-'
letter "P"
Natto~
DesignatiOns
Mlhtary temperature range
IndustrIal temperature range
Flatpack
Dual-In-lme
Nolette..
letter "C"
letter "F"
letter "0"
Examples
OG129Al
oGl348P
AH0129F (pm for pm)
AHOl34CO (pm for pm)
Note 2. "400" series used to denote mdust1"tal temperature range product
Coding was changed to use "100" series and lett8l" "S"
Example
oG426 "" OG126S;;: AH0126C
r-
."
Voltage Comparators
~r."
N
~
r-
LF1111LF2111LF311 voltage comparators
."
W
general description
::t
Further, the LFlll can be used in place of the LMlll
errors due to input currents.
The LFlll, LF211 and LF311 are FET input voltage
comparators that virtually eliminate input current errors.
Designed to operate over a 5.0V to ±15V range the
LFlll can be used in the most critical applications.
elimin~ting
advantages
The extremely low input currents of the LF 111 allows
the use of a simple comparator in applications usually
requiring input current buffering. Leakage testing, long
time delay circuits, charge measurements, and high
source impedance voltage comparisons are easily done.
•
Eliminates input current errors
•
Interchangeable with LM 111
•
No need for input current buffering
Dual·ln·Line Package
connection diagrams*
Motal Can Package
Flat Package
v'
GROUND
INPUT
,
14 Ne
OND 1
13 Ne
NC
v'
OUTPUT
INPUT
v-
11
10
BALANCE/
STROBE
BALANCE
NOTE Pm 5 connected to bottom oipackBge
TOP VIEW
TOP VIEW
•
v- 0
- ' - -_ _....r- BALANCE
NOTE Pln4connec;tedtocase
.NO
12 NC
INPUT
NC
Dual·ln-Line Package
,
v'
"
INPUT
OUTPUT
INPUT
BALANCE
STROBE
OUTPUT
v'
BALANCE!
STROBE
BALANCE
TOP VIEW
Note Pm 6 connected to bottomotpackage
Order Number LF111H,
Order Number LF111F
LF211H or LF311H
See Package 3
See Package 11
*Pin connectIons shown on schematic diagram
and typical applications are for TO-5 package.
TOP VIEW
Order Number LF311N
See Package 20
Order Number LF111D,
LF211D or LF311D
See Package 1
Order Number LF311N-14
See Package 22
schematic diagram and auxiliary circuits
BALANCE/STROBE
6
v'
R2
JDk
BALANCE
•
v'
R3
R4
300
300
r---~~.-~--~---f----.----.--------~--.------------------;~·v·
R1
R2
'"
1J.
Offset Balancing
R9
R5
10
60.
7TL
STROBE
OUTPUT
......'
'---'-
Strobing
016
.
v-
:.~l
.NO
"Inere.... tyPlcIt common mode
lIewfrom 1.0V/psto laV/,..
Increasing Input
Stage Current*
1·1
............
absolute maximum ratings
M
LL
LFlll/LF211
...I
"....
....
N
Total Supply Voltage (V S4 )
Output to Negative Supply Voltage (V 74 )
Ground to Negative Supply Voltage (V 14)
Differential Input Voltage
Input Voltage (Note 1)
Power Dissipation (Note 2)
Output Short Circuit Duration
Operating Temperature Range
LF111
LF211
LF311
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
LL
...I
........
"[:
...I
electrical characteristics
LF311
36V
40V
30V
±30V
±15V
500mW
10 seconds
36V
50V
30V
±30V
±15V
500mW
10 seconds
-55°C to +125°C
-25°C to +85°C
~5°C to +150°C
300°C
O°C to +70°C
~5°C to +150°C
300°C
(LF111/LF211) (Note 3)
PARAMETER
CONDITIONS
MIN
TYP
MAX
Input Offset Voltage (Note 4)
T A = 25°C, Rs
0.7
4.0
mV
Input Offset Current (Note 4)
TA = 25°C, V CM = 0 (Note 6)
5.0
25
pA
Input Bias Current
TA = 25°C, VCM = 0 (Note 6)
20
50
pA
Voltage Gain
TA = 25°C
200
V/mV
Response Time (Note 5)
T A =25°C
200
ns
Saturation Voltage
V,N <::; ~5.0 mV, lOUT = 50 mA, T A = 25°C
0.75
Strobe On Current
TA = 25°C
3.0
Output Leakage Current
V ,N ~5.0 mV, V OUT = 35V, TA = 25°C
0.2
Input Offset Voltage (Note 4)
1.5
UNITS
V
mA
10
nA
6.0
mV
Input Offset Current (Note 4)
Vs = ±15V, VCM = 0 (Note 6)
2.0
3.0
nA
Input Bias Current
Vs = ±15V, V CM = 0 (Note 6)
5.0
7.0
nA
Input Voltage Range
V
V
+14
-13.5
V+ ~4.5V, V- =0
V ,N <::;-6.0 mV, ISINK <::; 8.0 mA
0.23
0.4
Output Leakage Current
V ,N ~ 5.0 mV, V OUT = 35V
0.1
0.5
/lA
Positive Supply Current
TA = 25°C
5.1
6.0
mA
Negative Supply Current
T A = 25°C
4.1
5.0
mA
Saturation Voltage
V
Note 1: This rating applies for ±15V supplies. The pbsitlve input voltage limit is 30V above the negative supply. The negative input voltage limit
is equal to the negative supply voltage or 30V below the positive supply, wh ichever is less.
Note 2: The maximum junction temperature of the LFll1 'is +150°C, the LF211 is +110°C and the LF311 is +B5°C. For operating at elevated
temperatures, devices in the TO-5 package must be derated based on a thermal resistance of +150°C/W. junction to ambient, or +45°C/W, junction
to case. For the flat package, the derating is based on a thermal resistance of +185° elW when mounted on a 1/16-inch-thick epoxy glass board with
ten, 0.03-inch-wide, 2-ounce copper conductors. The thermal resistance of the dual-in-line package is +100°C/W, junction to ambient.
Note 3: These specifications apply for Vs = ±15V and -55°C T A +125° C for the LF 111, unless otherwise stated. With the LF211, however,
all temperature specifications are limited to _25° C T A ~ +85° C and for the LF311 0° C ~ T A +70° C. The offset Voltage, offset current and bias
current specifications apply for any supply voltage from a single 5.0 mV supply up to ± 15V supplies.
Note 4: The offset voltages and offset currents given are the maximum values required to drive the output within a volt of either: supply with a
1.0 mA load. Thus, these parameters define an error band and take into account the worst case effects of voltage gain and input impedance.
Note 5: The response time specified (see definitions) is for a 100 mV mput step with 5.0 mV overdrive.
Note 6: For Input voltages greater than 15V above the negative supply the bias and offset currents will increase-see tYPical performance curves.
:s.
1·2
:s
:s
:s.
r-
tlectrical characteristics
"T1
....
....
....
........
(LF311) (Note 3)
MIN
CONDITIONS
PARAMETER
UNITS
r-
10
mV
5.0
75
pA
N
....
....
........
150
pA
W
TYP
MAX
2.0
'put Offset Voltage (Note 4)
T A = 25°C, Rs ::; 50k
'put Offset Current (Note 4)
TA
= 25°C, V CM = 0 (Note
,put Bias Current
TA
= 25°C, V CM = 0 (Note 6)
25
6)
'oltage Gain
TA
= 25°C
200
V/mV
lesponse Time (Note 5)
T A = 25°C
200
ns
;aturation Voltage
VIN ::; -10 mY, lOUT = 50 mA, T A = 25°C
0.75
;trobe On Current
T A = 25°C
3.0
)utput Leakage Current
VIN :::>: 10 mY, V OUT = 35V, T A = 25°C
nput Offset Voltage (Note 4)
Rs ::; 50k
nput Offset Current (Note 4)
Vs = ±15V, V CM = 0 (Note 6)
nput Bias Current
Vs = ±15V, V CM = 0 (Note 6)
0.2
nA
15
mV
1.0
nA
3.0
nA
V
V
,aturation Voltage
V+:::>:4.5V, V-=O
VIN ::; -10 mY, ISINK ::;.8.0 mA
0.23
0.4
V
'ositive Supply Current
T A = 25°C
5.1
7.5
mA
~egative
T A = 25°C
4.1
5.0
mA
Supply Current
"T1
....
....
mA
10
+14
-13.5
nput Voltage Range
r-
V
1.5
'Jote 1: This rating applies for ±15V supplies. The positive Input voltage limit IS 30V above the negative supply. The negative jnp~t voltage limit
s equal to the negative supply voltage or 30V below the positive supply, whichever IS less.
\lote 2: The maximum junction temperature of the LF111 IS +150°C, the LF211 IS +110°C and the LF311 is +85°C. For operating at elevated
'emperatures, devices in the TO·5 package must be derated based on a thermal resistance of +150°C/W, junction to ambient, or +4SoC/W. junction
:0 case. For the flat package, the derating IS based on a thermal resistance of +185° C/W when mounted on a 1/16~lnch-thick epoxy glass board with
:en, 0.03~inch·wide. 2~ounce copper conductors. The thermal resistance of the dual-In-line package IS +1000 e/W, junction to ambient.
\late 3: These specificatIOns apply for VS = ± 15V and _5S o e
T A :.S +12So C for the LF 111, unless otherwise stated. With the LF211, however,
III temperature specifications are limited to -2SoC T A :.S +8Soe and for the LF311 O°C :.S T A +700 e. The offset voltage, offset current and bias
:urrent specifications apply for any supply voltage from a single 5.0 mV supply up to ± 15V supplies.
\late 4: Tha offset voltages and offset currents given are the maximum values required to drive the output within a volt of either supply with a
1.0 mA load. Thus, these parameters define an error band and take into account the worst case effects of voltage gain and Input Impedance.
\Jote 5: The response time specified (see deflnltlohs) IS for a 100 mV mput step with 5.0 mV overdrive.
~ote 6: For Input voltages greater than 15V above the negative supply the bias and offset currents will Increase-see tYPical performance curves.
:s
:s
:s
typical applications
AI
3 9~
v+= 50V
A4
500
V+
R1
50V
'Ok
R5
10k
R1
lOOk
R3
10k
"'
'Ok
R3
10k
....-..
J~'
'
~
2N797
Q2
2N2222
~~~ ~~'
"':'"
tFI11
I
2
"
20k
+
4
1 7
SQUARE
~ ~~i:UT*
"
100k
>7'-~~OUTPUT
R4
J9k
R3
50k
"'TTL or OTl fanout of two
*Soltdtantalum
Low Voltage Adjustab!e Referonce Supply
100 kHz Free Running Multivibrator
"T1
Crystal Oscillator
1·3
...
u..
......
...
('t)
typical performance
...J
Input Bias Current
N
Input Bias Current
vs Temperature
vs Common Mode
u..
10,000
...J
......
:::
lL
1/
100
~
;;
\;
V
8.0
12
16
20
24
28
INPUT COMMON MOOE VOLTAGE (V)
w
'":;'"
"....>
~:0
"
;;
.s
w
'":;'"
"....>
~
5.0
I
4.0
20mV
3.0
2.0
5.0mV
2.0mV
1.0
'IV
~
Vs =±15V I--TA • 25'C
">
~
~
I I
-J I
IJ
I I
50V
I.)
0
I
~oo
-
3.0
20~V
I
20
5.0mV
10
2.0mV
1\
RL 160,
~~
..
I
I
~
"
.
-~, .1±15V- I---
~
....
:;;
f__
02
04
0.6
-10
-15
0
:; -50
> -100
;;
'"~"
I
>
~
VOUl
;;
v-
.§
~
'"'"
"
~
~
;
I TA
V"±15~t=25°C
~
3.0
~
2.0
1.0
,"
'iP'
'A"
!--'TA' 25'C
't-~"J
0.1
o
10
50
40
30
20
OUTPUT CURRENT (mAl
Supply Current
Input OverdirV8S
10
15
10
4.0
'.s...."
tVttr:"
:'
50
-
~
0_5.0
2K
lFll1
.sw
C-- ~~
Response Time for Various
.~
-
2.DmV
02
0.8
w
A
0.3
o
~
20mV
/
D.
TIME tus)
I v' I
1.0
!:'"
0.5 TA ::: _55°C,
-"I---~
>
z
-iA'ri-
TA • 125'C
01
06
;::
I I
~
Response Time for Various
Input Overdrives
15
10 5.0mV
5.0
0
-5.0
0.5
w
'"'"
I I
~
-50
ii:
0.8
0.6
~
Your
..,. Lfll1
....
0.4
-05
-1.0
Output Saturation Voltage
~DD
~
> -100
L+Fll1
0
0.2
o
DIFFERENTIAL INPUT VOLTAGE (mV)
Y'N -
w
'"'"
w
"
10
50V
.§
VOUT
50
50
40
;;
Y'N -
100
~
~
"
EMITTER
FOLLOWER
OUTPUT
08
I
TIME(~s)
'"'"
:;
">\;
:=
Response Time for Various
Input Overdrives
~
V,'30V _
TA '25'C_
IT
~
TEMPERATURE I'C)
Response Time for Various
Input Overdrives
~
I I
30
1.0
-55 -35 -15 5.0 25 45 65 85 105 125
1.0
40
40
:0
10
,
RL;: t.Ok
v++ = SOV
20
\;
V-
NORMAL OUTPUT
50
/
..e 1,000
...J
Transfer Function
60
~TA =+25°C
Your
1K
-
1li
LF111
ill
13
v-
-10
-15
100
50
0
~
~
I I I
I I I
8.0
TTT
......
POSITIVE SUPP;"'.--_
.......OUTPUT LOW
60
......
'.0
POSITTVE AND ~
-NEGATIVE SUPPLYI-
2.0
-rTi'GHI
'
i"
2.0
3.0
--
. . . r "'tI
TT
o
10
~
V,, ±1\V
-55 -35 -15 5.0 25 45 65 85 105 125
4.0
TEMPERATURE rCI
1
120
....
~
~
..
<:>\~
80
f-f-\:~~
60
r-
....
40
ili
20
o
1-4
,,- ~
... ~ t--
~ '\
E 100
.
~
6.0 r--r-..,--.,,--,---,---,
0.1
TA "'25°C
, tzS~
06
0.5
0.3
~
...Q~
~~/I/CUIT- CURRENT 0.2 z
§
o
10
5.0
OUTPUT VOLTAGE (VI
15
§Vs ",5V
5.0 f--I----l----l-~f__~~
<8
d.• 52
~
0.1
o
Leakage Currents
Supply Current
Output limiting Characteristics
140
~
".s
~
13
~
~
/
10- 8
~
3.0
B 10-
hH--,,...,,,,"
/
9
OUTPUT VOUT
"
50V -
w
2.0
"
t-f-1--+-
~--t'It--1I----1r--OUTPUT
02
IN9'4
A2
50.
"
D01~f
RO
'"
TTL
INPUT
"
1 5~F·
Digital Transmission Isolator
*Sohd tantalum
tAdlustto set clamp level
Precision Squarer
v'
LADDER
NETWORK
A'
4,""""---1,""""--''-1
10k
1
TTl
TO TTL
lOGIC
02
AI
*Valuesshown are fora
010 JOV logic swmg and
a 15V threshold
TTL "'Absorbs mducttve kickback of
STROBE relavand prOletts Ie from severe
voltage tranSients on V++ hne
Relay Driver with Strobe
Using Clamp Diodes to Improve Response
TTL Interface with High, Level Logic
FROM D/A NETWORK
v+· 50V
Al
4"
AJ
'"
TTL
A2
TTL
OUTPUT
OUTPUT
, ANALOG
INPUT
10<
TTL
STROBE
' - - - -....MAGNETIC
PICKUP
Detector for Magnetic Transducer
1-6
*R2 sets the companson level
At companson, the photodlOde
. . .- - ' has less than 5 0 mVacross It,
decreastng leakages by an order
of magnttude
Precision Photodiode Comaprator
*TVPICBI tnput current Ii
50 pA With tnputs strobed off
Strobing Off Both Input*
and Output Stages
r-
:I:
......
N
Voltage Comparators
.......
r-
:I:
LH2111/LH2211/LH2311 dual voltage comparator
general description
The LH2111 series of dual voltage comparators are
two LM 111 type comparators In a single hermetic
package. Featuring all the same performance char·
acteristics of the single, these duals offer in addi·
tion closer thermal tracking, lower weight, reduced
insertion cost and smaller size than two singles.
For additional information see the LMlll data
sheet and National's Linear Application Handbook.
N
N
:::t
.......
r-
fied for operation over the oOe to 70°C tempera·
ture range.
:I:
N
W
...
features
• Wide operating supply range
•
The LH2111 is specified for operation over the
_55°C to +125°e military temperature range. The
LH2211 is specified for operation over the _25°C
to +85°e temperature range. The LH2311 is speci·
±15Vtoa
single +5V
6nA
Low input currents
• High sensitivity
10llV
• Wide differential input range
• High output drive
connection diagram
±30V
50 rnA, SOV
auxiliary circuits
OUTPUT
GND!EMITTER)
""
"
10 GNO(EMlTIEII)
.
,.
Order Number LH2111D,
LH2211D or LH2311D
Strobing
Offset Balimci ng
See Package 2
Order Number LH2111 F,
LH2211 F or LH2311 F
See Package 5
"
*Increases typical common mode
slew from 7 OV/i.!sto 18V}j.IS
Increasing Input Stage Current*
Using Clamp Diodes to Improve Responses
Driving Ground-Referred Load
r - -......- .....-
V+=5V
""
ANALOG
INPUl
He
STROSE
*TYPlcal mput current IS
50 pA with IIlputs strobed off
Comparator and Solenoid Driver
Strobing off Both Input*
",
*Values shown are for a
oto JOV logiC sWing and
a 15V threshold
tMay be added to control
speed and reducesuSteptlbilityto nOise spikes
TTL Interface with High Level Logic
and Output Stages
1·7
absolute maximum ratings
Total Supply Voltage (V+ - V-I
Output to Negative Supply Voltage (V OUT - V-I
Ground to Negative Supply Voltage IGNO - V-I
Differenttallnput Voltage
Input Voltage (Note 1)
Power DIssipation (Note 2)
electrical characteristics
PARAMETER
36V
50V
30V
±30V
±15V
500mW
10 sec
-SS'C to 12S'C
-2SoC to 8SoC
Output Short Circuit Duration
Operating Temperature Range lH2111
LH2211
LH2311
Storage Temperature Range
oOe to 700e
-6S Q C to 150°C
3OO'C
Lead Temperature (Soldering, 10 sec)
- each side (Note 3)
CONDITIONS
LIMITS
LH2111
LH2311
7.5
UNITS
mV Max'
TA = 25'C, Rs';;50k
Input Offset Current (Note 4)
TA = 25'C
10
10
50
nAMax
Input 818S Current
TA = 25'C
100
100
250
nAMax
Voltage Gain
TA=25'C
200
200
200
V/mV Typ
Response Time (Note 5)
T A "'2SoC
200
200
200
ns Typ
Saturation Voltage
VIN -s:. -5 mV,l OUT
TA=25'C
Strobe On Current
TA = 25'C
Output leakage Current
VIN
:?: 5 mY,
1.5
3.0
V OUT :::: 35V
10
3.0
',
Input Offset Voltage (Note 4)
= 50 rnA
3.0
LH2211
1.5
3.0
10
1.5
V Max
3.0
nATyp
50
nAMax
TA = 25'C
Input Offset Voltage (Note 4)
lis';; 50k
4.0
20
Input Offset Current (Note 4)
10
mV Max
20
4.0
70
nAMax
Input Bias Current
150
150
300
nAMax
Input Voltage Range
±14
±14
±14
VTyp
Saturation Voltage
V';:>4.5V, V-=O
0.4
0.4
0.4
VMax
VIN~-5mV.lsINK~8mA
POSitIVe Supply Current
TA = 25'C
6.0
6.0
7.5
mAMax
Negative Supply Current
TA = 25'C
5.0
5.0
5.0
mAMax
Note 1: This rating applies for ±15V supplies. The positive input voltage limit is 30V above the negative supply. The negative
input voltage limit is equal to the negative supply voltage or 30V below the positive supply. whichever is less.
Note 2: The maximum junction temperature IS 150°C. For operating at elevated temperatures, devices in the flat package, the
derating IS based on a thermal resistance of 185'C/W when mounted on a 1/16-inch-thlck epoxy glass board with 0.03-inchwide, 2 ounce copper conductor. The thermal resistance of the dual-in-line package is trxtC/W. junction to ambient.
Nota 3: These specifications apply for VS= ±15V and -55'C", TA';; 125'C for the LH2111,-25'C,;;TA';;'85'Cforthe
LH2211. and O'C ,;;, T A ,;; 70'C for the LH2311. unless otherwise stated. The offset voltage, offset current and bias current
specifications apply for any supply voltage from a single 5V supply up to :t15V supplies. For the LH2311, VIN =±10 mV.
Note 4: The offset voltages and offset currents given are the maximum values required to dfive the output Within a volt of
either supply with a 1 rnA load. Thus, these parameters define an error band and take into account the worst case effects of
voltage gain and input impedance.
Note 5: The response time speCified is for a 100 mV mput step With 5 mV overdrive.
1-8
r
...s:
Voltage Comparators
oG)
'r
s:
LM106/LM206 voltage comparator
general description
The LM 106 and LM206 are high-speed voltage
comparators designed to accurately detect lowlevel analog signals and drive a digital load_ They
are equivalent to an LM710, combined with a two
input NAN D gate and an output buffer. The
circuits can drive RTL, DTL or TTL integrated
circuits directly_ Furthermore, their outputs can
switch voltages up to 24 V at currents as high as
100 mAo Other features include:
• Improved accuracy: 2 mV maximum worst case
offset.
• Fan-out of 10 with DTL or TTL
• Added I,ogic or strobe capability
• tJseful as a relay or lamp driver
• Plug-in replacement for the LM710.
N
oG)
• 40 ns maximum response time'
The devices have short-circuit protection which
limits the inrush current when it is used to drive
incandescent lamps, in addition to preventing
damage from accidental shorts to the positive
supply. The speed is equivalent to that of an
LM710_ However, they are even faster where buffers and additional logic circuitry can be eliminated
by the increased flexibility of the LM106 and
LM206. They can also be operated from any negative supply voltage between -3V and -12V with
little effect on performance.
The LM106 is specified for operation over the
-55°C to +125°C military temperature range. The
LM206 is specified for operation over the -25°C
to +85°C temperature range.
schematic and connection diagrams **
Metal Can
.
..
TOr VIEW
STROBE
"'---+--+--+-~--CQ'
.
Note Pm 4 connected to case
1~
"
&3Y
Order Number LM106H or LM206H
See Package 11
Flat Package
,
t---t----OUTPUT
INPUT
::r_....~""'_....___...._--<....._
....
..._-'1 .GROUND
Ne
Ne
GROUND
Ne
Ne
INPUT
"
INPUT
Ne.
Ne
,-
OUTPUT
STROBE
STROBE
Note. Pm 6 connected to bottom of package
Y-'
**PIII connectIOns shown art fOf TO-5 package
typical applications **
Lovel Detector and Lamp Driver
Y'
TOP VIEW
Order Number LM106F or LM206F
See Package 4
Fast Response Peak Detector
v*$Z4V
V+~12Y
......
01
Relay Driver
"
21(
Adjustable Threshold Line Receiver
INPUTS
1-9
cg
o
N
absolute maximum ratings
-'
"cg
Positive Supply Voltage
Negative Supply Voltage
Output Voltage
Output to Negative Supply Voltage
Differential Input Voltage
Input Voltage
~
...
o
~
-'
Power Dissipation (Note 1)
Output Short Circuit Duration
Operating Temperature Range
15V
-15V
24V
30V
±5V
LM106
LM206
Storage Temperature Range
Lead Temperature (soldering, 10 sec)
z7V
electrical characteristics
600mW
105ec
-55'C to 125'C
-25'C to 85'C
-65'C to 150'C
300'C
(Note 2)
CONDITIONS
PARAMETER
Input Offset Voltage
Note 3
Input Offset Current
Note 3
MIN
TYP
MAX
0.5
2.0
mV
3.0
~A
0.7
Input Bias Current
= 390n to +5V,
= 15pF
Response Time
Note 4, R L
CL
Saturation Voltage
V ,N
Output Leakage Current
Y,N?' 5 mY, 8V:::: VOUT :::: 24V
:::: -5 mY,
lOUT
= 100 mA
UNITS
10
20
~A
28
40
ns
10
1.5
V
002
10
~A
30
mV
electrical characteristics
The following specifications apply for T L ~ T A::;;; T H (Note 5)
I nput Offset Voltage
Note 3
Average Temperature Coefficient
of Input Offset Voltage
Input Offset Current
30
Note 3, T L';: T A
25'C';: T A
Average Temperature Coefficient
of I nput Offset Current
Input Voltage Range
';:
TH
5.0
15
~A
~A
25'C
45
~A
20
pA
TL';: T A
-7V
TH
';:
2. V- 2. -12V
V
±5.0
= 50 mA
1.0
V
lOUT = 16 mA
0.4
V
5.5
V
10
~A
Saturation Voltage
V ,N
:::: -5 mY,
Positive Output Level
V ,N
?, 5 mY, lOUT = -400 ~A
Output Leakage Current
Y'N
? 5 mY, 8V:::: VOUT :::: 24V
T L';: T A ';: 25'C
Strobe Current
V'trobe
25'C
2.5
< T A ';: T H
100
-17
= O.4V
Strobe ON Voltage
0.9
V'N=-5mV
-3.2
1.4
14
Strobe OFF Voltage
nArC
V
±5.0
Y'N :::: -5 mY, lOUT
pA
mA
V
2.2
V
55
10
mA
-1.5
-3.6
mA
Note 1: The maximum Junction temperature of the LM106 IS +150°C, while that of the LM206
IS +110° C For operating at elevated temperatures, devices In the TO-5 package must be derated
based on a thermal resistance of +150°C/W, Junction to ambient, or +45°C/W, Junction to case.
For the flat package, the derating IS based on a thermal resistance of +185°C/W when mounted
on a 1/l6-lOch-thlck epoxy glass board with ten, 0 03-lOch-wlde, 2-ounce copper conductors.
Note 2: These speCIfications apply for -3.0V 2: V- 2: -12V, V+ = 12V and T A = +25°C unless otherwise specified All currents Into device pinS are conSidered positive.
Note 3: The offset voltages and offset currents given are the maximum values reqUired to drive the
output down to 0.5V or up to 5.0V. Thus, these parameters actually defme an error band and take
into account the worst-case effects of voltage gam, specified supply voltage Variations, and common
mode voltage vanatlons
Note 4: The response time specified (see definitIOns) IS for a 100 mV Input step with 5.0 mV overdrive.
Note 5: All currents Into device pms are conSIdered positive.
1·10
~VrC
25°C';:T A ';:T H
';:
T A ';: 25'C
Differential Input Voltage Range
Negative Supply Current
7.0
3.0
nAte
';:
Saturation Voltage
Positive Supply Current
10
25
75
25'C';: T A
TL
Input Bias Current
1.8
0.25
25'C
';:
LM106
LM206
r-
s:....
o
(J)
typical performance characteristics
.......
r-
s:N
Transfer Function
-
10'
'o- ,
V+=+12V
V~'-6V-
.1
-
TA. -25"C
-
TA '"-55"C
.~.,.,..
,,
,
1/ ,';! "~5'C
,
t;
,
10,
10-
g§
10-
S
-
r"
~
~
.':ft
10-
T T
10+3
0 +0.1 +0.2 +0.3 +0.4 +0.5
+2
j;;;;-- j -
~ 0.8
I !
....
§! 06
V1N =-5mV
1,.-... ,,"_
+--
o
-15 -50 -25
25
c
:
)'+I~V
V-'-6V'-
.
V-'-6V-
f'..
YIN =-5mY
""
l'-
1
-75 -50 -25
Response Time For
Various Input Overdrives
Itt.,
1
;n
--
~25+5Di15+100"'125+15D
0
JUNCTION TEMPERATURE ("C)
TITl ,"
II
'ro,
5~~1· T""
I I
lUmY
2mV-
III I
Tn
TIn
v:"
v +12~:[
~ -50
> -100
50 15 100 125
=-6V
TAi+flc
i
o
20
40
&0
80
20
100 120
40
120
r---r-.,....-~--,--r-...,
f--+-+--+
'00
TA "_55°C
.~
>-
"J.,.".
14
>
>
~
2
I,..+--
80
100 tlO
Power Consumption
Negative Supply Current
Positive Supply Current
60
TlME!III)
TlME!""-
a:
~
Y·"'+12V
V'
2
0 +25 +50 +75 +100 +125
TEMPERATURE (OC)
n
B&
~
3
110
8
0 +25 +50 +75 +10111+125
o
-75 -50 -25
TEMPERATURE i'el
I.
I'"--- t-
V1N "'+5mY
~S~
0
"
r-... ....
Short Circuit Output Current
-
~
I"' ~
~
I,
I"'-
r-...
. -75 -50 -25
Y+".'2V
l-
~
-5
Response Time For
Various Input Overdrives
B
r-..
-r"V-;'-12V
0 +25 +50 +15 +100 +125
TEMPERATURE rei
r--- ~ls
1 10
::'-l
a:
a:
~~
j,.oo"
.....
Input Current
20
I ~
y+ = 10V
> 20
I..-
_3V:;~~~!m
40
30
1
TEMPERATURE (OC)
--"'"
I I
-15 -50 -25
-4
-3
r-- t-':"6ImA
o
~
L
)"2~~ 1\:+'15Vf--
-2
'-'- f-- f-':'OmA
;:j 0.2
f--
•
IL "SOmA
0.4 t--
-1
..
-3V?:.V-;:::-15V
D.
z
~
I
TA :-55<>C
+1
r--:
60
Positive Output level
o
S
-3V;'V->-'12v
1
--"I'IO~mA
f-
'
,
N--..
IfilUTVOlTAGE(mV}
Saturation Voltage
'0
~
V+=+12V_
INPUT VOLTAGE (mY)
2
~z
6
,,- 6
-0.3 -O.2...Q.1
;;
F
10-
W
o
so
: T:.=;Z:~l
~
o(J)
Voltage Gain
Transconductance
.j... ~""'ITA =+25"C
---
~-
1
90
z
0
-,-
aD
"'" ..... r--.,
•. 1'mv
~ t-V:1--.....
Q
~
1
Y+"+1ZV
y- .. -&v
10
a:
TA. =+125"&
I I
YIN "-5mV
60
..
50
-
r-..
r--.,
r-
30
+10
+12
POSITIVE SUPPLY VOLTAGEW)
+15
-3
-6
-9
-12
NEGATIVE SUPPLY VOL lAGE (V)
-15
-15 -50 -25
0
+25 ...50 +75 +100 +125
TEMPERATURE ("C)
1-11
Voltage Comparators
LM306 voltage comparator/buffer
general description
The LM306 is a high-speed voltage comparator
designed to accurately detect low-level analog signals and drive a digital load. It is equivalent to an
LM710e, combined with a two input NAND gate
and an output buffer. The circuit can drive RTL,
DTL or TTL integrated circuits directly. Furthermore, the output can switch voltages up to 24V at
currents as high as 100 mA_ Other features
include:
• Improved accuracy: 5 mV (max) offset
• Fan-out of 10 with DTL or TTL
• Added logic or strobe capability
• Useful as a relay or lamp driver
• Plug-in replacement for the LM710e.
• 40 ns maximum response time
The device has short-circuit protection which
limits the inrush current when it is used to drive
incandescent lamps, in addition to preventing
damage from accidental shorts. The speed is
equivalent to that of an LM710e. However, it is
even faster where buffers and additional logic
circuitry can be eliminated by the increased flexibility of the LM306. It can also be operated from
any negative supply voltage between -3V and
-12V with little effect on performance. The LM306
is identical to the LM 106,except that it is specified
over a oOe to 70°C temperature range.
schematic and connection diagrams**
....., "
r -.....----1r--.--t--+-~-
Metal Can
TOPVIEW
v·
"
"
."
'"~
...._ + _ " " , 1 OUTPUT
V'
Note Pln4connectedtocase
Otder Number LM306H
See Package 11
)...-.........,N-.-....- - -........--__- .....--'GAOUND
,_.
*"Pm conllet:tlOlIs shown are for TO 5 package
typical applications**
"
v+·nv
Fast Response Peak Detector
Level Detector and Lamp Driver
V++<24V
Adjustable Threshold Line Receiver
Relay Driver
OUTPUT
fO ~IO
*Optlonal for response tlmecolltrol
1-12
absolute maximum ratings
Positive Supply Voltage
Negative Supply Voltage
Output Voltage
Output to Negative Supply Voltage
Differential Input Voltage
Input Voltage
Power DIssipation (Note 1)
Output Short CirCUit Duration
Operating Temperature Range
Storage Temperature Range
Lead Temperature (soldering, 10 sec)
15V
-15V
24V
30V
±5V
±7V
600mW
10 sec
O°C to 70°C
_65°C to +150°C
300°C
electrical characteristics
(Note 2)
PARAMETER
MIN
CONDITIONS
TYP
MAX
Input Offset Voltage
Note 3
1.6
5.0
Input Offset Current
Note 3
1.8
5.0
Input Bias Current
Response Time
Note 4, RL ~ 39011 to +5V,
C L ~ 15 pF
Saturation Voltage
V,N.:o; -7mV, lOUT
Output Leakage Current
V,N
2':
~
100 mA
7mV,8V:S:;V OUT ::;24V
UNITS
mV
p.A
16
25
p.A
28
40
ns
0.8
2.0
V
0.02
2.0
p.A
6.5
mV
electrical characteristics
The following specifications apply for O°C::; T A::; 70°C (Note 5)
Input Offset Voltage
Note 3
Average Temperature Coefficient
of Input Offset Voltage
5
20
Input Offset Current
Note 3, O°C S T A < 25°C
25°CSTA S 70°C
Average Temperature Coefficient
of Input Offset Current
25°C:S;T A .:o;70°C
0° C :s; TA ::; 25° C
15
24
50
100
Input Bias Current
O°C S T A < 25°C
25°C S T A S 70°C
25
40
25
Input Voltage Range
-7V
2': V- ~ -12V
Differential Input Voltage Range
24
7.5
50
p.A
iJ.A
±5.0
V
±50
V
Saturation Voltage
V,N ::; -8 mV, lOUT
~
50 mA
1.0
V
Saturation Voltage
V,N:S; -8 mV, lOUT
~
16 mA
0.4
V
Positive Output Level
V,N
5.5
V
Output Leakage Current
2': 8 mV, lOUT ~ - 400 iJ.A
V,N 2': 8 mV, 8V::; V OUT ::; 24V
2.5
O°C S TA S 25°C
25°C < T A S 70°C
Strobe Current
V strobe
-1.7
= O.4V
Strobe ON Voltage
Strobe OFF Voltage
2.0
100
0.9
l"nk:S 16 mA
-3.2
1.4
1.4
Positive Supply Current
5.5
Negative Supply Current
-1.5
V
22
V
10
mA
-3.6
mA
Note 1: For operating at elevated temperatures, the deVice must be derated based on a 85°C maximum
Junction temperature and a thermal resistat:lce of 4SoC/W Junction to case or 150°C/W Junction to
ambient.
Note2: These specifications apply for -3V 2: V- 2. -12V, V+ == 12V and TA == 25°C unless otherwise specified All currents Into pins are considered POSitive
Note 3. The offset voltages and offset currents given are the maximum values required to dnve the
output down to 0 5V or up to 50V Thus, these parameters actually define an error band and take
Into account the worst-case effects of voltage gain, and mput Impedance, specified supply voltage
vanatlons, and common mode voltage variations
Note 4: The response time specified (see definitions) IS for a 100 mV Input step With 5 mV overdnve
Note 5. All currents Into deVice pinS are considered pOSitive
1-13
CD
o
M
typical performance characteristics
~
...J
Transfer Function
Transconductance
10·
10-
v+ =+12V
T
f----
,TJ~
,..
V~.-~V
T••10~
.Oo~
f
'2
g
lO-2
~
10-3
ill
lIT"'
B
~
• \'.1
"
CI
Voltage Gain
80
,
III
:; 60
r
..
.
.
.@
~
C
co
co
,0-'
lD-
r""40
c
10-6 TA =70"C
to-
7~' -
I
~
V+ .. +12V
>
-3V~V~~-12V
20
r:...
• 2"-2::,,
". !
rn
.....
+3 +2
INPUT VOLTAGE ImV)
-
a.
CD
"co~
..
1.0
"
0.2
:li
-
t
V+.+12V.......
0.4
-2
-3
Short Circuit Output Current
g
i!l
a:
a:
~
T
5
~
a:
U
a:
It - .,2V
eo
60
40
20
3
20
isa:
10
...
..
~
.....
v+
l::
+12V
V-· -6V
......
~~ .....
t-
>
."
..
.....
I
a:
~
20
~
40
:
~T.1 DoC
-
TA " 2&o e
-
T. _10°C
60
80
~
-60
>
-100
Y+·+12V
Y-'-6V
TA " +ZSoC
i
o
2D
48 88 10 100 120
a:
a>
I...
>
i
VIN "
::=-~
-5mV
hV ~
VIN =
~
~-
~
I!'::"'''
~
ill
>
i
20
40
~~
To_DoC
.,5
,.. 1--
::.:j..::F-
~TA'25°C
1 TAj10"C
tl2
~~
T.· 25°C
:;-
~
~~
jAtiOC
o
-3
-L
-9
6D
6D
'00 120
Power D'issipatio'n
120
1-.' . .
~
POSITIVE SUPPLY VOLTAGE IV)
1-14
. ••
.
TIMElno)
ITA'_olc
~
-3V2:Y-~-12V
,,0
>
Negative Supply Current
!,..",,:.:i
>o#'iii 10"'"..'
~co
TIMEC..)
~
~ ~
a
~
1
I':--,.
.;;; ~.
a:
80
;;
.!
Positive Supply Current
1
01"
·h,V
TEMPERATURE eC)
10
T
I iDmV
:;
.!
r-.
60
40
Input Overdrives
IIII
"'
-'.J
~+..:t>t.zttmY •
I ~1II,~.t-
~
a...
~"
.....
Response Time for Various
Response Time for Various
Input Overdrives
~
3D
t-...
JUNCTION TEMPERATURE 1°C)
I nput Current
C
" r--.
0.2
TEMPERATURE 1°C)
40
V1N "-5mV
;;
VIN " +5 mY
20
V-· -BV
..... ......
.....
-3V~V-~-12V
80
0.3
y+ =+12V
."e:
IL '"' -400 p.A
IL·'lmA
60
0.4
...
I, ~ 0 ~A
40
I I
I I
80
!::
20
v+= ,O\'
-4 -5
-- ILI-0
-3V ~ V- ~-12V
V1N"-SmV
IL.SOmA
0.6
-1
Positive Output Level
r-- I-I~ -1'00 ~A
0.8
>
co
;:
"...a:
-
0
n:...
INPUT VOLTAGE ImV)
Saturation Voltage
1.2
+1
......
V'., ..'.
W"
-0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5
-3V ~V- >-15V
r-...
r
•
100
;:
6D
..
60
2
40
.!
"'"
i
is
I
I
r-- t-
l- ~'IV"'-5IbV
I
v>+12V_
V ·-6V
r- ~
v'N"+5mv
l"- I--
~
....
20
-12
NEGATIVE SUPPLY VOLTAGE IV)
-15 '
20
40
60
TEMPERATURE rc)
80
~s
Voltage Comparators
LM1111LM211 voltage comparator
general description
• Differential input voltage range: ±30V
The LM 111 and LM211 are voltage comparators
that have input currents nearly a thousand times
lower than devices like the LM106 or LM710.
They are also designed to operate over a wider
range of supply voltages: from standard ±15V op
amp supplies down to the single 5V supply used
for IC ·Iogic. Their output is compatible with RTL,
DTL and TTL as well as MaS circuits. Further,
they can drive lamps or relays, switching voltages
up to 50V at currents as high as 50 mAo Out·
standing characteristics include:
• Power consumption: 135 mW at ±15V
Both the inputs and the outputs of the LM 111 or
the LM211 can be isolated from system ground,
and the output can drive loads referred to ground,
the positive supply or the negative supply. Offset
balancing and strobe capability are provided and
outputs can be wire OR' ed. Although slower than
the LM106 and LM710 (200 ns response time vs
40 ns) the devices are also much less -prone to
spurious oscillations. The LM 111 has the same pin
configuration as the LM106 and LM710.
• Operates from single 5V supply
The LM211 IS identical to the LM Ill, except that
its performance is specified over a _25°C to 85°C
temperature range instead of _55°C to 125°C.
• Input current: 150 nA max. over temperature
• Offset current: 20 nA max. over temperature
schematic diagram and auxiliary circuits **
. .
BAlANCE/STAOBE
R3
300
."
BALANCE
R4
300
AI
R2
IlK
13K
'If
..""
Offset aalancing
llllll
1_
1
t·
In
Q'
'_1111
,
STROJI
"
OUTPUT
Strobing
Rl]
4
,
*Increases tYPical common mode
slew from 70V//1sto 18V//-Is
Increasing tnput Stage Current*
GROUND
connection diagrams
Metal Can
Dual-In-Line
Flat Package
".
"'61"'.
BNO!
nNe
INPUT
3
+
INPIJT
•
-
Ne
5
V-
8
t
SALAN&!:
J
I
12 lie
I' v"
typical applications
..."'
m
BALANCEI
ST~OHE
Notf!. Pm 4 connllCted to case
Note Pm 5 connected to bottom of package
IINC
OUTPUT
BALANCE
STflOH~
Note Pm 6 connected to bottom of package
HIP VIEW
Order Number
LMlllH or LM211H
Order Number
LMlllF or LM211F
See Package 11
See Package 3
Order Number
LMlllD or LM211D
See Package 1
Detector for Magnetic Transducer
.. "'Pm connections shown are for metal can
1-15
...
::t
......-'
N
absolute maximum ratings
.......
Total Supply Voltage (V B4 )
Output to Negative Supply Voltage (V 74)
Ground to Negative Supply Voltage (V 14)
Differential Input Voltage
Input Voltage (Note 1)
Power Dissipation (Note 2)
Output Short Circuit Duration
Operating Temperature Range LMlll
LM211
Storage Temperature Range
Lead Temperature (soldering, 10 sec)
::t
-'
electrical characteristics
PARAMETER
36V
50V
30V
±30V
±15V
500mW
10 sec
_55°C to 125°C
_25°C to 85°C
_65°C to 150°C
300°C
(Note 3)
MIN
CONDITIONS
;
TYP
0.7
MAX
Input Offset Voltage (Note 4)
T A = 25°C, Rs::; 50k
Input Offset Current (Not~ 4)
T A = 25°C
Input Bias Current
T A = 25°C
60
Voltage Gain
TA = 25°C
200
V/mV
200
ns
4.0
Response Time (Note 5)
TA = 25°C
Saturation Voltage
VIN ::;-5 mV, lOUT = 50 mA
T A = 25°C
0.75
Strobe On Current
T A = 25°C
3.0
Output Leakage Current
VIN 2':5mV,
TA = 25°C
Input Offset Voltage (Note 4)
Rs::; 50k
3.0
UNITS
10
100
1.5
mV
nA
nA
V
mA
V OUT = 35V
0.2
10
4.0
Input Offset Current (Note 4)
Input Bias Current
20
nA
150
nA
±14
Input Voltage Range
nA
mV
V
Saturation Voltage
V+ 2': 4.5V, V- = 0
V IN ::; -6mV, I SINK ::;8 mA
0.23
0.4
V
Output Leakage Current
V IN 2':5mV, VouT=35V
0.1
0.5
I1A
Positive Supply Current
TA = 25°C
5.1
6.0
mA
Negative Supply Current
TA = 25°C
4.1
5.0
mA
Note 1: ThIs ratIng applies for ±15V supplies. The positive mput voltage limit IS 30V above the
negatIve supply, The negative mput voltage lImit is equal to the negatIve supply voltage or 30V below
the posItive supply, whichever IS less.
Note 2: The maxImum Junction temperature of the LM111 IS 150°C, while that of the LM?11 IS
11 DoC. For operating at elevated temperatures, devIces in the TO-5 package must be derated based on
a thermal resistance of 150o C/W, junctIon to ambient, or 4SoC/W, junction to case. For the flat
package, the der13ltlOg IS based on a thermal resIstance of 185 0 C/W'when mounted on a 1/16-lnch·thlck
epoxy glass board wIth ten, O.03-lOch-wide, 2-ounce copper conductors. The thermal resistance of the
dual-in-llOe package IS 100o C/W, junction to ambIent.
Note 3: These specifications apply for Vs = ±15V and -55°C ::;TA::; 125°C, unless otherwISe stated.
With the LM211, however, all temperature specifIcations are limIted to _25°C ~TA ::;850 C. The offset voltage, offset current and biBS current specifications apply for any supply voltage from a single 5V
supply up to ±15V supplies.
Note 4: The offset voltages and offset currents given are the maximum values reqUired to drive the
output within a volt of either supply wIth a 1 mA load. Thus, these parameters define an error band
and take Into account the worst case effects of voltage gain and Input Impedance.
Note 5: The response time specifIed (see definitions) IS for a 100 mV Input step with 5 mV overdrive.
1-16
r-
...~...
typical performance characteristics
Input Bias Current
I "put Offset Current
400
;;
.!
30
..~
......
r-
Offset Error
~
...
100
N
~
Vs = ±15V
c
1....
RAISED
(SHORT PINS_--;;;
5, 6, AND 8)
-" 300
....
~
~
;;;
....
~
">
il:
0:
20
i"
10
B
B 200
!!!
V,=+15V-
100
-
NDRMAl- f -
o
-55 -35 -15
5 25
....
RAISED
(SHORT PINS
......
""-; r-NoRMAL ~6,ANo81
i
-55 -35 -15 5
TEMPERATURE ("C)
1....
il:
0:
~
~
25°C
~
~
120
80
;;;
60
f
!!!
40
'"
-0.5
~
g
'z"
"'"
8'"
10M
1M
Transfer Function
60
,
r- NORMAL OUTPUT
R~FE~REdTo~uptLYVoLTAGES-
rr-
50
~
...'"
-1.0
~
::;
...
100
lOOk
O\Ok
INPUT RESISTANCE (m
v+
J,!=±\5~
0:
25 45 65 85 105 125'::l
Common Mode limits
T.
140
§
TEMPERATURE ("C)
I nput Characteristics
160
10
'"~
45 65 85 105 125
180
~
"....
i
!:;
-1.5
">
30
~
20
"
10
!;
0.4
_r-'"
....
0.2
40
RL '" lK
,
EMITTER
FOLLOWER
OUTPUT
:>
f- ~!:~:Yc-
V++ '" 50V
RL '" 600n
20
V-
-16 -12 -8
-4
0
4
12
B
-55 -35 -15
16
DIFFERENTIAL INPUT VOLTAGE (V)
Response Time for Various
..~
~
I
"
20.mV
!;
5mV
~
:>
",
.'"
!:;
I
'I
-
~""v
vlN
100
50
-
our -
+
I
I LOT I
"....>
~
02
!!!
,-
1\
5mV
\
t-J
;;
..
.!
,J
I
QutP ....t Saturation Voltage
.'"
~
Y'N -
~
VOUT
!:;
>
z
:MIII
~~
~ -SO
VS =±15Y- f -
i' =1
~ -100
f
0.2
"
",
>=:
'"g;
....
:i
25°1_ f -
0.5
TA
•
..'"
0.3
0.2
01
Response Time for Various
Input Overdrives
...
">
10
!;
"
-5
-10
;; -15
.!
..
20mV
5~~
V
/
2mV
~
:>
Response Time for Various
Input Overdrives
~
V
In
!:;
v'
"....>
.~
-
:>
VOUT
ZK
I
lMl11
I v-
8
~ -50
-100
~
II
c:
>
....
~
"
;;
I
Vs' ±15~t-T.· 25°C
..'"
15
10
5
• 0-
-l~ ~T~ =25°C
o
-5
-10
.! -15
~
!:;
V,N
2°i~ \
\.
5 mV
2 '!IV.!.
+
-
-
\.
100
50
"....>
50
48
30
Your
IlMl11
_
v-
±1~V -
, V,I.
T", 25,°C
-
0.7
....
il:
0:
100
~
t:
~
0:
U
80
"i5i
20
0:
....
0:
~
~ '---
TA "25°C
C 120
.!
,,-,
~to
~~
--\-~~
60
,
'40
;;L..s',f~
~/~CUIY-CURRENT
i!
~
0.3
"iii
;:
0.2
"z
0.1
::!
~
o
0
TIME 11<.1
0.6
0.5
0.4
.A
0
!!!
TIME ("')
28
10
Output Limiting Characteristics
~,. -
. .W\
~
~
!!!
.r"
~
140
~
15
.
OUTPUT CURRENT (mAl
~
!:;
-WC,
-f--~
0.4
TIME 11<.1
~
125°C ;---~
"
0.6
0.8
0.6
TA
0.7
o
04
.5
8.B
I
~
~
-.5
-1
DIFFERENTIAL INPUT VOLTAGE (mV)
~OIDn
~
2~V
0.8 !:
0.6
04
I
20~V
I
I I
I .vl
Ii:
.!
~
Vs = ±15V
fTA"'ZSoC
II
2mV
;;
I
I I
"
>
85 105 125
Response Time for Various
Input Overdrives
Input Overdrives
~
5 25 45 65
TEMPERATURE rC)
18
15
OUTPUT VOLTAGE (V)
1-17
....
....
N
typical performance characteristics (con't)
2!
....
......
....
Supply Current
....
....
:t
....
Supply Current
6~-r--.---r---"r-"T""-'
1~
Leakage Currents
11
I I
I I
.....
"
......
I I
I I
o
10
15
20
25
o
30
I" ~
-rrrll
I
o..,~
....
.~ ~
~,,,
-
,.'§.
I 1
-55 -35 -15 5
SUPPLY VOLTAGE (VI
.
c
Vs = ±ISV
T,," 15°C
I.
.j I
~1
I-
.v'
-
P'O1
lao
•
50
I
VOL.lT-
I
I
~
1-
U6'
0.4
D.2
co
B.Z
10
V-
o
o ro
m
H
01
~..
I
>
15
lOmV
5mV
~
ZorY.;
h,V';
ZmV
...
~
l-
-5
-10
;;; -15
/
2 .. V
IJ
~
~
,.
Your
ow
c
-50
=
> -100
I Ys=±15~
1 T,' 25'C
~
1
I-
1-22
TIME Iosl
TA " 26°C
+
VOI,IT
co
0.6
~
0.5
>
co
DA
co
0.3
0.1
DB
Response Time for Various
I"put Overdrives
.
..
..'"
>
15
II
I-
5'
I!:
0
;;;
.
-5
-10
ZO~!..
\
,\ 1\
5mV
ZmVl
1\
-..
.! -15
ow
c
~
-
100
50
v.I. tI~V
T'l = 25;C
co
>
i
v-
•
10
g
3D
50
OUTPUT CURRENT (mAl
Output Limiting Characteristics
.~=
,.-
'-'rr\.
-
0.2
D
01
'U
'"
.."~
!i
l-
I 1 1
O.Z
•.1
c
Vs - tl5V- IT, -Z5'C_
-50
~
w
-'
l-
I-
.5
D.I
~
i
~
v-
.!
Vs = 30V
T,' 25'C
-.5
-I
I
v;t>i.n
~ -100
c
v'
-
""
Output Saturation Voltage
,J
I
ow
~
£
'\
DIFFERENTIAL INPUT VOLTAGE (mV)
~
i
~
'L
n u
H
TIME (0,1
Input Overdrives
10
50
I
>
Response Time for Various
..
..
E
..'"
.. •
g
Input Overdrives
TIME (0,1
E
ow
EMmER
FOLLOWER
OUTPUT
RL -BOOn
Response Time for Various
I I
>
~
..
20
I!:
IA
E
I-
c
311
TEMPERATURE ('CI
I I
C
ow
~
co
>
!;
-1.5
II
Response Time for Various
'nput Overdrives
~
g
C
DIFFERENTIAL INPUT VOLTAGE (VI
E
ow
NORMAL OUTPUT
RL -Ik
Y++=40V
50
E
ow
25
o
..
..
..
..'"
i
..
..
Transfer Function
U
ow
I-
10M
1M
INPUT RESISTANCE (Sl)
y+
175
110
125
lOOk
TEMPERATURE rCI
. J. ~ ±\5~
I-
"""
NORMAL
i
I
I
I "put Characteristics
201
-
l-
TEMPERATURE ('CI
225
v. = ±.SV
10
Ill'
I-
I
"""-I. I
r- ~,R~
PINS
r- (SHORT
5, 6, AND BI
I-
;;; 2ao
~
ZO
VOUT
-
140
C
12.
I-
100
.!
~
!:
u
"
co
01
nOc
f--~~
68
'-
-
g
I
lII:
Ii
•
.....'~ ~
fI>~'
.."" •
i3
-
TA
D4
~.t~
0.3
7'.~II/CUIT-CURRENT
TIME wd
02
•• 1
20
o
0
I
0.6
05
0
10
OUTPUT VOLTAGE (VI
15
ill
.
I....
iii
:::!
!
typical performance characteristics (con't)
Supply Current
Leakage Currents
Supply Current
10
-
5
I
o
15
20
25
.
B
...;::,0-
SUPPLY VOLTAGE IVI
~
OUTPUT VO UT • 40~
10-9
INPUT V,N
10
• 15V " .
;
~
I
o ro H H
30
VS ,-+15V
§
POSITIVE SUPPLY OUTPUT LOW
POSITIVE AN;-;-NEGATIVE SUPPL YOUTPUT HIGH
10
10-8
Vs:;; ±1SV
~
TEMPERATURE
~
rei
ro "
45
35
55
TEMPERATURE
15
75
rei
typical applications
....
,--.---.-"
"'TTL
Detector for Magnetic Transducer
Zero Crossing Detector
Driving MOS Switch
on Fanout of two.
*Input polanty IS reversed
when usmg pm 1 as output
.
..
,...,
Of
100 kHz Free Running Multivibrator
1~151
Driving Gro... nd-Referred Load
1~'51
_+______+_
L - _...._ _ _ _ _ _ _....
.
=~:::
,
* Adjust tor symmetncal square
wave time when V,N '" 5 mV
tMmlmum capacitance 20 pF
MaK.rnurn frequency !i0 kHz
...
"
USing Clamp Diodes to 1mprove Response
10 Hz to 10 kHz Voltage Controlled Oscillator
...
,
*Valuesshownarefor
a qto 30V JOllie swmg
anda 15Vthreshofd.
tMay be added to control speed and reduce
susceptability to nOIse
spikes
TTL Interface with High Level Logic
Crystal Oscillator
Comparator and Solenoid Driver
1-23
typical applications (con't)
...
,~JI
,Low Voltage Adjustable Reference Supply
tAd/ust to settlamp level
Precision Squarer
Zero Crossing Detector driving MOS logic
Positive Peak Detector
Digital Transmission Isolator
Negative Peak Dectector
m
ounu'
*R2 sets the companson
'"
level At comparison, the
photodlOde has less than
STROll
5mVacrosslt,decteasmg
*TYPlcallnput current IS
50 pA With mpuh strobed off.
leakages by an order of
magnitude
Strobing off Both Input*
and Output Stages
Precision Photodiode Comparator
*Absorbsmductlveklckback of relay and
protectslCftomseverevoltagetranslIlnts
on v++Ime
Relay DrIVer with Strobe
...... , .
r-~~--t--
....
.
,.
Switching Power Amplifier
1-24
.
ON
Switching Power Amplifier'
r-
~
----
Voltage Comparators
CD
......
r~
N
--
CD
LM119/LM219 high speed dual comparator
general description
The LM119/LM219 are precision high speed dual
comparators fabricated on a single monolithic
chip. They are designed to operate over a wide
range of supply voltages down to a single 5V logic
supply and ground. Further, they have higher
gain and lower input currents than devices like
the LM710. The uncommitted collector of the
output stage makes the LM119 compatible with
RTL, DTL and TTL as well as capable of driving
lamps and relays at currents up to 25 mAo Out·
standing features include:
features
• Two independent comparators
• Operates from a single 5V supply
• Typically 80 ns response time at ±15V
•
Minimum fan-out of 2 each side
•
Maximum input current of 1 IlA over temperature
• I nputs and outputs can be isolated from system
ground
• High common mode slew rate
Although designed primarily for applications requiring operation from digital logic supplies, the
LM119 is fully specified for power supplies up to
±15V. It features faster response than the LM111
at the expense of higher power dissipation. However, the high speed, wide operating voltage range
and low package count make the LM 119 much
more versatile than older devices like the LM711.
The LM219 is identical to the LM119, except that
its performance is specified over a -25°C to 85°C
temperature range instead of _55.°C to 125°C.
schematic and connection diagrams
Dual-In-Line-Package
"'
'"
.
~l
RJ
' '"' 1:
Order Number LMl19D or LM219D
See Package 1
Metal Can Package
typical applications
Order Nu mber LM 119H or LM219H
See Package 12
Flat Package
-INPUT 1
Relay Driver
Window Detector
Order Number LM119F or LM219F
S.. Package 3
1-25
en
....
N
absolute maximum ratings
36V
36V
25V
18V
±5V
±15V
Total Supply Voltage
~
Output to Negative Supply Voltage
Ground to Negative Supply Voltage
Ground to Positive Supply Voltage
D,fferentlal Input Voltage
lI;put Voltage (Note 1)
...I
......
en
....
....
electrical characteristics
~
...I
PARAMETER
500mW
10 sec
-55'C to 125'C
_25°C to 85°C
_65°C to 150°C
300'C
Power DISSipation (Note 2)
OU,tput Short Circuit Duration
Operatmg Temperature Range LM119
LM219
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
(Note 3)
CONDITIONS
MIN
TYP
MAX
0.7
4.0
Input Offset Voltage (Note 41
T A = 25'C, Rs S 5k
Input Offset Current (Note 4)
T A = 25'C
30
75
Input Bias Current
T A = 25'C
150
500
Voltage Gain
T A = 25'C
10
25°C V s =±15V
ns
Y,N S -5 mY, lOUT = 25 mA
TA = 25°C
0.75
Output Leakage Currel'\t
Y,N 2 5 mY, V OUT = 35V
TA = 25°C
0.2
Input Offset Voltage (Note 41
RsS5k
1.5
Input BI8sCurrent
2
IlA
mV
100
nA
1000
nA
±13
Vs = ±15V
V' = 5V, V- = 0
2
1
Y,N
3
V
V
0.4
0.6
V
V
4.5V, V- = 0
Y,N S -6 mY, ISINK S 3.2 mA
TA ~ O°C
TA S O°C
Output Leakage Current
V
7
Input Offset Current (Note 4)
v+
nA
80
TA
SaturatIon Voltage
nA
V/mV
Response Time (Note 5)
Input Voltage Range
mV
40
Saturation Voltage
=
UNITS
2
0.23
5 mY, V OUT = 35V
1
10
DIfferential Input Voltage
IlA
±5
V
POSitive Supply Current
TA = 25°C, V+ = 5V, V- = 0
4.3
Positive Supply Current
TA=25'C Vs = ±15V
8
11.5
mA
Negative Supply Current
TA = 25°C Vs = ±15V
3
4.5
mA
mA
Note 1: For supply voltages less than ±15V the absolute maximum Input voltage is equal to the supply voltage.
Note 2: The maximum JunctIOn temperature of the LM119 IS 150°C, whIle that of the lM219 IS 110°C. For operating at
elevated temperatures, devices In the TO-5 package must be derated based on a thermal resistance of 150°C/W, junction to
ambient, or 4SoC/W, junction to case. For the flat package, the derating IS based on a thermal resIstance of 18SoC/W when
mounted on a 1/16-lnch-thlck epoxy glass board with ten, O.03-lnch-wide, 2-ounce copper conductors. The thermal resistance
of the dual-m-Ilne package IS 100° C/W, Junction to ambient.
Note 3: These specifications apply for Vs = ±15V and -55°C'::; TA .::; 12SoC, unless otherwise stated. With the LM219,
however, all temperature specIficatIOns are limited to - 2SoC ~ T A ~ 8SoC. The offset voltage, offset current and bIas current
specifications apply for any supply voltage from a smgle 5V supply up to ±15V supplIes.
Note 4: The offset voltages and offset currents given are the maximum values required to drive the output withm a volt of either supply WIth a 1 rnA load. Thus, these parameters define an error band and take Into account the worst case effects of
voltage gain and input Impedance.
Note 5: The response time specified (see definitions) IS for a 100 mV Input step with 5 mV overdrive.
typical performance cha racte risti cs
v+
250
Vs = ±15V
~
0-
I
!;
!
200
"-
~
;;
.......
BIAS
r- r-
100
50~
-
- ~I-
r-
TEMPERATURE
rei
...."
r-
60
vl,.iovlv -1.0
'l'k.-r-t-w.
S
-
I
"'hJ I
I I I I I r--..!.
;;
0--
"'w
~'"
5.0
40
..
I I I I I I
;;
0
0.8 r-Vs '" ±15V, Vs + '" S.OV, V- '" 0
0.4
!!~
.. -2.0
z
r... b.l J I
3.0
;;; -1.2
::;
g-1.6
8
0
-55-35 -15 5.0 25 45 65 85 105 125
1-26
-0.4
~-O.~
150
Response Time for Various
Input Overdrtves
Common Mode Limits
I nput Currents
1.2
vs· , t5V
0-<
",0~
>
REFERRED TO SUPPL Y VOLTAGES
I I I I I I I
v-55 -35 -15 5.0 25 45 6585 105 125
TEMPERATURE
nl
I II' ?l
2.0mV
I',
5.0mV
III
2.0
1.0
I
20mV
.J.J.
Vs '" 5.0V
RL '" 500n
1f'+·50V
TA '" 25°C
E 100
~i
.
50
0
>
0
50 100 150 200 250 300 350
TIME (nsl
Voltage Comparators
lM319 high speed dual comparator
general description
The LM319 is a precision high speed dual comparator fabricated on a single monolithic chip. It is
designed to operate over a wide range of supply
voltages down to a single 5V logic supply and
ground. Further, it has higher gain and lower
input currents than devices like the LM710. The
uncommitted collector of the output stage makes
the LM319 compatible with RTL, DTL and TTL
as well as capable of driving lamps and relays at
currents up to 25 mAo
features
• Two independent comparators
• Operates from a single 5V supply
• Typically 80 ns response time at ±15V
•
•
•
Minimum fan-out of 2 each side
Maximum input current of lilA
Inputs and outputs can be isolated from system
ground
• High common mode slew rate
Although designed primarily for applications
requiring operation from digital logic supplies, the
LM319 is fully specified for power supplies up to
±15V. It features faster response than the LM 111
at the expense of higher power dissipation. However, the high speed, wide operating voltage range
and low package count make the LM319 much
more versatile than older devices like the LM711.
The LM319 has its performance specified over a
oOe to 700e temperature range.
schematic and connection diagrams
Dualln-Line.package
Metal Can Package t
'~"
,
"
GilD 1 J
120unI/TI
.,,.Ul' 4
11 V·
_11I~Tl &
lQ ~"'UT'2
V-I
I
•• ",UTZ
,~
OUTPUT21
.61102
Order Number
LM319D
See package 1
tPm 5 connected to case.
Order Number
LH319H
See Package 12
LM319N
See Package 22
typical applications
Relay Driver
Window Detector
"Frequency adJust
tMusl be buffered for
RL
~
10 Megohms
Wide Range Variable Oscillator
1-27
absolute maximum ratings
fotal Supply Voltage
Output to Negative Supply Voltage
36V
36V
25V
18V
Ground to Negative Supply Voltage
Ground to Positive Supply Voltage
Power DISSipation (Note 2)
Output Short CIrcuit Duration
Operatmg Temperature Range LM319
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
±5V
Differential Input Voltage
Input Voltage (Note 1)
500mW
10 sec
OoC to 70°C
-65"C to 150'C
3OO'C
±15V
electrical characteristics
PARAMETER
(Note 3)
CONDITIONS
MIN
TYP
MAX
2.0
8.0
Input Offset Voltage (Note 4)
T A = 25'C, Rs ~ 5k
Input Offset Current (Note 4)
TA = 25'C
80
200
Input Bias Current
TA = 25'C
250
1000
Voltage Gain
TA = 25'C
8
nA
80
ns
TA = 25'C Vs = ±15V
Y,N ~
-10 mV, lOUT = 25 mA
T A =25'C
0.75
Output Leakage Current
V ,N ::?: 10 mV, V OUT = 35V
TA = 25'C
0.2
Input Offset Voltage (Note 4)
Rs~5k
V
1.5
Input Offset Current (Note 4)
Input Bias Current
10
p.A
10
mV
300
nA
1200
nA
±13
Vs = ±15V
V' = 5V, V-= 0
1
V+ ~ 4.5V, V- = 0
Y,N ,;;: -10
nA
V/mV
Response Time (Note 5)
Saturation Voltage
mV
40
Saturation Voltage
Input Voltage Range
UNITS
0.3
3
V
V
0.4
V
mV, ISINK ';;: 3.2 mA
±S
Differential Input Voltage
V
Positive Supply Current
T A = 2S'C, V+ = SV, V- = 0
4.3
Positive Supply Current
T A =2S'C Vs = ±lSV
8
12.5
mA
Negative Supply Current
TA = 25'C Vs = ±lSV
3
5
mA
mA
Note 1: For supply voltages less than ±15V the absolute maximum Input voltage IS equal to the supply voltage
Note 2: The maximum Junction temperature of the LM319 IS 85°C For operating at elevated temperatures, deVices In the
TO-5 package must be derated based on a thermal reSistance of 150°C/W, Junction to ambient, or 45°C/W, Junction to case
The thermal resistance of the dual-In-Ilne package IS 1oaoC/W, Junction to ambient.
Note 3: These specificatIOns apply for Vs = ±15V and -aoe::;: T A .::;;. 70o e, unless otherwise stated. The offset voltage,offset
current and bias current specifications apply for any supply voltage from a single 5V supply up to ± 15V supplies
Note 4: The offset voltages and offset currents given are the maximum values required to dnve the output wIthin a volt of
either supply with almA load Thus, these parameters defme an error band and take mto account the worst case effects of
voltage gain and Input Impedance
Note 5: The response tIme specified IS for a 100 mV Input step with 5 mV overdrive.
typical performance characteristics
I nput Currents
300
l- t--
~
~
:0
0:
~
~
-
BIAS
200
150
100
"
.s
10
OffSET
I-10
20
30
SLpPl~. V,; ±15J
4.0
I I I
I
I
~"
POSITIVE SUPPL V, Vs"
='
>
I
S,OV, Vs -
='
0
"
~~
40
30
~~
20mV
2.0
10
0
..s 100
1
20 I---TGArETPTV'j±151-
I
0
~
8.0
~
8 6.0
~
50
I I I I I I
,.... Posri'VE
>-
50
-
1/ Z
I 20mV
1/1
,rr,J.J.
50mV
I
Vs =SOV
RL" 500n
v++"
50
5 OV
TA '" 25°(;
0
>
40
50
TEMPERATURE rCI
1·28
60
12
Vs=±15V
250
Response Time for Various
I nput Overdrives
Supply Currents
60
70
0
10
20
30
40
50
TEMPERATURE rCI
60
70
0 . 50 100 150 200 250 300 350
TIME (ns)
r-
Voltage Comparators
...w3:
CD
.......
r-
3:
LM139/LM239/LM339 quad comparators
general description
The LM139 series consists of four independent
voltage comparators which were designed specifically to operate from a single power supply over a
wide range of voltages. Operation from split power
supplies is also possible and the low power supply
current drain is Independent of the magnitude of
the power supply voltage. These comparators also
have a unique characterIStic In that the Input
common·mode voltage range includes ground,
even though operated from a single power supply
voltage.
.......
r-
•
Allows sensing near GND
•
Compatible with all forms of logic
•
Power drain suitable for battery operation
3:
W
W
CD
features
•
•
Application areas Include limit comparators, simple
analog to digital converters; pulse, squarewave and
time delay generators; wide range VCO; MOS clock
timers; multivibrators and high voltage digital logic
gates. The LM139 series was designed to directly
interface with TTL and CMOS. When operated
from both plus and minus power supplies, the
LM339 will directly Interface with MOS logic where the low power drain of the LM339 IS a
distinct advantage over standard comparators.
•
•
advantages
•
N
W
CD
Wide single supply
Voltage range
or dual supplies
2 Voc to 36 Voc
±1 Voc to ±18 Voc
Very low supply current drain (0.8 mAl Independent of supply voltage (1 mW/compara·
tor at +5 V oel
35 nA
Low Input biaSing current
3 nA
Low Input offset current
and offset voltage
3mV
•
Input common-mode voltage range includes
ground
•
Differential Input voltage range equal to the
power supply voltage
•
Low output
saturation voltage
•
Eliminates need for dual supplies
schematic and connection diagrams
1 mV at 5jJ.A
70 mV at 1 mA
Output voltage compatible With TTL (fanout of
2), DTL, ECL, MOS and CMOS logic systems
Dual-In-Line and Flat Package
INPUT 4-
OUTPUT l OUTPUT 4
v'
OUTPUT 2 OUTPUT 1
V·
INPUT J+
INPUT l-
INPUT 1-
Order Number LMl39F
See Package 4
Order Number LM139D, LM239D or LM339D
See Package 1
Order Number LM339N
See Package 22
typical applications
+5V oc
+5V oc
+5V oc
v,
.
,
Driving TTL
Driving CMOS
Comparator with Hysteresis
1-29
absolute maximum ratings
Supply Voltage, V+
"
Dlffer.entlal Input Vcltage
-0,3 Voc to +36 Voc
Molded DIP
(LM339N)
Cavity DIP
Flat P~ck
(LM139D, LM239D & LM339D)
(LM139F)
aOc
LM339
LM239
LM139
S70mW
900mW
800mW
Lead Temperature (Soldering, 10 seconds)
electrical characteristics
(v+ = +5,0 V oc • see Note 4)
LM139
MIN
Input Offset Voltage
TA
Input Bias Current (Note 51
IINlt) or IIN(.) With Output
""
+25°C (Note 9)
Linear Range, T A
'"
~55°C to +125°C
-6SoC to +lS0°C
Storage Temperature Range
Continuous
CONDITIONS
In
TYP
to +70°C
-2SoC to +8SoC
Output Short,Clrcult to GND (Note 2)
PARAMETER
SOmA
Operating Temperature Range
36 V DC
Input Voltage
Power QIS~tpatlon (Note 1)
< ~O 3 Voe HNote 3)
Input Current (V IN
36 Voc or ±18 Voc
300°C
LM239, LM339
MAX
MIN
TYP
MAX
UNITS
±2
:+-50
;2
±S 0
mVoc
25
100
25
250
nAoe
+25°C
Input Offset Current
IINI+1 -IIN( I, T A'"
Input Common-Mode Voltage
iA =+25°C
+2S
Q
±3
C
±25
'5
V L 15
0
0
±50
nAoe
v+ -15
V DC
20
mADC
Range (Note 6)
Supply Current
DB
RL '" 00 On All Comparators
TA =+25°C
DB
20
Voltage Gain
RL ~ 15,k!2, TA = +25°C
200
200
V/mV
Large Signal Response Time
VIN "" TTL Logic SWing,
VREF == +14 Vec, VRL '"
5aVec and RL = 51 kn
300
300
ns
Response Tlme'(Note 7)
VRL '" 5 aVec and RL '"
6.1 kn, TA ==+2SoC
13
13
"S
Output Sink Current
VINi ) ~ +1 aVec, VIN~.) == a
and Vo $+15 Vec. TA '" +25°C
16
mADC
Saturation Voltage
VIN ( ) ~ +1 OV oc , VIN~tJ '" 0
and ISINK $ 4,0 rnA, TA == +25°C
Output Leakage Current
VINi +) ~+1 OV oc , VINI~) =0
and VOUT = sav DC , TA '" +25°C
Input Offset Voltage
(Note
Input Offset Current
IINi+) - IINi_)
Input Bias Current
IINi+) or IINI_) With Output
Linear Range
6
250
6
500
250
500
mVec
90
90
mVoc
±lOa
±150
nA DC
300
400
nAoc
V+-20
Voc
01
!:I)
In
Input Common-Mode Voltage
Range
16
0
nA DC
01
V+-2
a
0
Saturation Voltage
VIN(_J ~+l,OVDC' VIN (+) =0
and 'SINK $ 4.0 mA
700
700
mVoc
Output Leakage Current
VIN !+) ~ +1.0 Voe , VINH :: ()
and VO UT '" 30 Voe
1,0
10
~Aoc
Dlfferentlsl Input Voltage
(NoteS)
Keep All VIN'S~OVoc (or
V-, If used)
36
,6
V DC
Note 1: For operating at high temperatures, the LM339 must be derated based on +125°C maximum junction temperature and a thermal
resIStance of +175°C/W which applies for the deVice soldered in a printed CirCUit board, operating In a still air ambient. The LM239 and
LM139 must be derated based on a +150°C maximum Junction temperature. The low bias dissipation and the ON-OFF characteristic of the
outputs keeps the chip diSSipatIOn very small (Pd < 100 mW), prOVided the output tranSistors are allowed to saturate.
Note 2: Short CirCUits from the output to V+ ~an cause excessive heating and eventual destruction, The maximum output current IS
approximately 20 mA Independent of the magnitude of V+.
'
Note 3: .Thls ,Input current will only eXist when the voltage at any of the Input leads IS driven negatIve. It IS due to the collector-base
Jun~tlon of the Input PNP transistors becoming forward bIased and thereby acting as Input diode clamps. In addition to thiS diode action,
~here IS also Ia.!eral NPN paraSItiC transistor action on the IC chip. ThiS tranSistor action can cause the output voltages of the comparators
to go to the V voltage 'level (or to ground for a large overdrive) for the time duration that an input IS driven negatIVe. ThiS IS not destructive
and normal output state~ Will re·establish when the Input voltage. which was negative, agam returns to a value greater than -0.3 VOC.
Note 4: These specifIcations apply for. V+ = +5.0 VOC and -5SoC :S TA < +12SoC, unless otherWise stated With the LM239, all
temperature speclflca'tlons ar~ limited to -25° C :S T A :S +85°C and the LM339 temperature specifications are limited to 0° C :S T A ~ +70° C
'Note 5: The direction of the mput current IS out of the IC due to the PNP Input stage. ThiS current IS essentially constant, Independent of
the state of the output so no loading change eXists on the reference or Input lmes.
Note 6: The input common-mode voltage Of either mput Signal voltage should not be allowed to go negative by more than a 3V The upper
end of the common-mode voltage range IS V -1.5V, but either or both Inputs can go to +30 VOC without damage.
Note 7: The response time specified IS for a 100 mV mput step With 5.0 mV overdrive For larger overdrive Signals 300 ns can be obtatned,
see typical performance characteristics section.
Note 8: The pOSitive excursions of the lnput can exceed the power supply voltage level, and If the other mput voltage remains Within the
common-mode voltage range. the comparator Will prOVide a proper output state The low mput voltage state must not be less than -0.3 VOC
(or 0.3 VOC below the magnitude of the negative Dower supply voltage, If used).
Note 9: At output SWitch pOint, Va so: 1.4 VOC, RS =051 With V+ from 5 VOC to 30VOC, and over the full Input common mode range (0 VOC to V+
±1,5VDC)·
1-30
..
r-
i:
typical performance cha racteristics
Supply Current
1.0
C
.§
...
~
'"'"
1l
>
~
I
+-
I-T~
~
0.6
h7 ~
0.4
80
TA' -55"c...i--
0.8
--t::'25"C
..L
, V-"""
....
g
...
~
'"
B
...
-
TA=+70°C
r-
~
!!!
l-
.3
TA '+125"C-
20
30
TA
T.4."'+125°C
0
10
v+ -
Response Time for Various
~"
g~
riuT
rS~TURtTIOIN
1\ I T
A "
~
0.001
20
30
~V
2;V
I
CP
......
r-
i:
w
I
W
' TA '+25"C
CP
1
I£:;
0.01
40
SUPPLY VOLTAGE (V oc )
N
W
~TA"'-55°C
...'"= 0.01
iA·tCI-
~ r-
TA-+125°~
0.1
:i
+25°C
r-
i:
~~
~
=
i!!
6F {
01
1.0
10
100
10 - OUTPUT SINK CURRENT ImAI
Response Time for Various
Input Overdrives - Positive
Transition
,.,r-r---<;5""m7:V-'I:O::N::;PU~T~OV::::E-:::RD:::R::":IV;;;E
i-+-inI"""tt-1--1""::P4
1- Jr -t-t
J J-l
r-r-~~~~+-+-+-~
r-r-tt-IFt-2-t0_m~.. ~_,".,'":
~
100mV
..;
I
~
10
>
=O°C
Input Overdrives - Negative
Transition
4
:,
r-
~
:i
v+ - SUPPLY VOLTAGE IVDCI
6
5
.
'"
R'NICMI ",,11)9\1
I I
4l)
10
g
V'NICMJ '" 0 Voc
TAl. _i5°C
4l)
20
I
R
10
I
I
:[ 60
0.2
0
w
CP
......
Output Saturation Voltage
I "put Current
ol-H.....,.....,.-+-+-+++-I
0
-50
hI-HhH-I-+
1+
1+-11
I-+-+-+-+-+-+-+1-j1_IH
?> -tOO ~+-+-+-+-+-+T =~5°~_
~
-1A -1 -1
0.5
1.0
15
20
05
1.5
TIME 1.....1
application hints
The LM139 IS a high gain, wide bandwidth
device; WhiCh, like most comparators, can easily
oscillate if the output lead IS inadvertently allowed
to capacitively couple to the inputs via stray
capacitance. This shows up only during the output
voltage transition intervals as the comparator changes states. Power supply bypassing is not required to solve this problem. Standard PC board
layout is helpful as it reduces stray input·output
coupling. Reducing the input resistors to <10 kn
reduces the feedback signal levels and finally,
adding even a small amount (1 to 10 mV) of positive feedback (hysteresis) causes such a rapid transition that oscillations due to stray feedback are
not possible. Simply socketing the IIC and attaching resistors to the pins will cause input-output
oscillations during the small transition intervals
unless hysteresis IS used. If the input signal is a
pulse waveform, with relatively fast rise and fall
times, hysteresis is not required.
All pins of any unused comparators should be
grounded.
The bias network of the LM139 establishes a
drain current which is independent of the magnitude of the power supply voltage over the range of
from 2Voc to 30 Voc.
It is usually unnecessary to use a bypass capacitor
across the power supply line.
The differential Input voltage may be larger than
V+ without damaging the device. Protection should
be provided to prevent the Input voltages from
gOing negative more than -0.3 V DC (at 2SoC). An
input clamp diode and input resistor can be used
as shown in the applications section.
The output of the LM139 IS the uncommitted
collector of a grounded-emitter NPN output transistor. Many collectors can be tied ti>QethBr to provide an output OR'ing function. An output "pullup" resistor Can be connected to any available
power supply voltage within the permitted supply
voltage range and there is no restriction on this
voltage due to the magnitude of the voltage which
is applied to the V+ terminal of the lM139 package. The output can also be used as a simple SPST
switch to ground (when a "pull-up" resistor is not
used). The amount of current which the output
device can sink is limited by the drive available
(which is independent of V+) and the !3 of this
device. When the maximum current limit is
reached (approximately 16 mAl, the output tran·
sistor will come out of saturation and the output
voltage will rise very rapidly. The output satura·
tion voltage is limited by the approximately 60n
rsat of the output transistor. The low offset voltage
of the output transistor (1 m V) allows the output
to clamp essentially to ground level for small load
currents.
1-31
en
M
M
typical applications (con't)
:E
...I
.......
+5V oc
en
M
N
:E
...I
.......
en
M
~
:E
Yo
TEMPERATURE
SfNSING
...I
TMERMOCOUPLE
Ground Referenced Thermocouple
MOS to TTL Logic Translator
in Single Supply System
y'
(5Vocl
51k
+5V oc
.....
"-
\
I
lN9,4
P
- I
-/
'00
/
,M
+V~EF 4
'"
Remota Temperature Sensing
'60
+5 Voc
P
+V REP3
to,
Y"
36'
TTL to MOS Logic Converter
P
+15VDc
+VREf ~
'00
,.
A1
D1
lN914
A2
D2
IN914
'DOk
8t1pF
P
,M
to,
,M
Visible Voltage Indicator
·FOR LARGE RATIOS OF Rl/R2,
DI CAN BE OMITIED
Pulse Generator
1-32
typical applications (con't)
V'
V'
lOOk
'"
V;su
t
~
100 kHz
Vo
Vo
200k
lOOk
t= 100kHz
Crystal Controlled Oscillator
Squarewave Oscillator
V'
V'
lOOk
'00'
500pF
'"
'V,
FREnUENCV
>_.....-0
CONTROL
VOLTAGE
INPUT
OUTPUT 1
OUTPUT 2
.Ok
v+ = +30 Voe
+250 mVoe < Vc < +50 Voe
700 Hz < fa < 100 kHz
Two-Decade High-Frequencv
veo
V'
V·
+V'N
O-----i
Vo
Vo
Basic Comparator
Non~lnverting
,M
V·o-""'.........H
Comparator with Hysteresis
Inverting Comparator with Hysteresis
V'
• OR LOGIC GATE
WITHOUT PULL UP RESISTOR
Comparing Input Voltages
of Opposite Polarity
Output Strobing
1-33
m
Voltage Comparators
LM13.A/LM239A/LM33,A low offset voltage
quad comparators
general description
The LM1~9A series consists of four independent
precision voltage comparators with an offset voltage specification of 2 mV. max. for all four
comparators which were designed specifically to
operate from a single power supply over a wide
range of voltages. Operation from split power
supplies is also possible and the low power supply
current draiA is independent of the magnitude of
the power supply voltage. These comparators also
have a unique characteristic in that the input
common·mode voltage range includes ground,
even though operated from a single power supply
voltage.
• Eliminates need for dual supplies
• Allows sensing near GND
• Compatible with all forms of logic
• Power drain suitable for battery operation
features
• Wide single supply
Voltage range
or dual supplies
2 Vee to 36 Vee
±1 Vee to ±18 Voe
• Very low supply current drain (0.8 mA)independent of supply voltage (1 mW/com·
parator at +5 Veel
• Low input biasing current
35 nA
• Low input offset current
3 nA
and maximum offset voltage
2 mV
• Input common·mode voltage range includes
ground
Application areas include limit comparators, simple
analog to digital converters; pulse, squarewave
and time delay generators; wide range VCO; MOS
clock timers; multivibrators and high voltage digital
logic gates. The LM 1~9A series was designed to
directly interface with TTL and CMOS. When
operated from both plus and minus power supplies,
the LM~~9A will directly interface with MOS
logic-where the low power drain of the LM~~9A
is a distinct advantage over standard comparators.
• Differential input voltage range equal to the
power supply voltage
advantages
•
•
• Output voltage compatible with TTL, DTL,
ECL, MOS and CMOS logic systems
High precision comparators
• Reduced Vos drift over temperature
Low output
saturation voltage
schematic and connection diagrams
v'
1 mV at 5/JA
70 mV at 1 mA
Dual·ln·Line and Flat Package
OUTPUT J OUTPUT 4
GNO
OUTPUT2 OUTPUT 1
v·
,.
INPUT 4+
INPUT
q~
INI'UT3-
OUTPUT
INPUT 2-
INPUT 1-
INPUT 2+
TOP VIEW
Order Number LM139AF
See Package 4
'Order Number LMI39AD, LM239AOorLlllt339AD
See Package 1
Order Number LM339AN
See Package 22
typical applications
(v+ = 5.0 Veel
+5 Vile
+iVac
v'
Basic Comparator
1-34
Driving CMQ!l
Driving TTL
I"'"
...3C
absolute maximum ratings
Supply Voltage, v+
36 Voc or tIS Voc
W
CD
Input Current (VIN < -0.3 VOC) (Note 3)
SOmA
Operating Temperature Range
LM339A
O"c to +70"C
LM239A
-26"Cto+86"C
LM139A
~·Cto+126"C
Storage Temperature Range
~·Cto+1SO·C
Lead Temperature (Soldering, 10 seconds)
300"c
Differential Input Voltage
36VOC
Input Voltage
-0.3 VOC to +36 VOC
Power Dissipation (Note 1)
Molded DIP (LM339AN)
570mW
Cavity DIP (LM139AO, LM238AO,
and LM339AO)
900mW
(LMl38AF)
Flat Pack
SOOmW
Output Short·Circuit to GNO (Note 2)
Continuous
l>
.....
r-
3C
N
W
cp
l>
.....
r-
electrical characteristics
3C
(v+ = +5.0 Vee, see Note 4)
LMI39A
TVP
MAX
LM239A. LM339A
MIN
TVP
MAX
Input Offset Voltage
TA '" +2SoC (Note 9)
'1
±20
±,
±2.0
mV DC
Input BIas Current (Note 5)
IIN!+l or IINC-I With Output In
25
'00
25
250
nAoe
PARAMETER
CONDITIONS
Linear Range, T A
..
MIN
+2S'C
Input Offset Current
IIN(+) -IINI_l. TA = +2SoC
Input Common-Mode Voltage
TA '" +25°C
'3
±25
V+-15
0
±5
0
±50
nAoe
V+-l.5
Voe
Range (Note 61
Supply Current
OS
RL = oo,on all Comparators
OS
2.0
UNITS
2.0
W
W
CD
l>
mAce
TA=+2SoC
Voltage Gam
Large Signal Response Time
RL ~ 16kn, TA "'+25°C.
V+ == 15 Voe (To Support
Large Vo SWing)
50
'"
50
200
VlmV
300
300
VIN '" TTL LogiC Swmg, V REF '"
+1.4 Voe, VR L
200
ns
5 V oe • RL '"
;
6 1 kn and TA'"" +2SoC
Response Time (Note 7)
13
VRl =SVoc and RL =51 kfl,
'3
I'S
TA '" +2SoC
Output Smk Current
V tNH
2
+1 Voe. V1N(+1 =0.
and Vo S;:+1.5 Voe. TA
Saturation Voltage
:c
60
'6
mADe
'6
+2SoC
VtNH ~+1 Vae. V1N(+1 '" 0,
, and 'SINK
60
250
500
250
500
s;: 4 rnA. TA '" +25°C
Output Leakage Current
V1N(+1 ~ +1 Voe. V1NH '" 0
Input Offset Voltage
(Note 9)
Input Offset Current
IIN(+)-IINH
Input Bias Current
IINt+)
0'
0'
mVoc
nAoc
andVO =5 Voc. TA =+2SoC'
or liN 1_)
Linear Range
With Output In
0
Input Common-Mode Voltage
40
40
mVoc
±100
±150
nAoe
300
400
nAoc
V+-2.0
Voc
V+-20
0
Range
V1NH :;::: +1 Voc. V1N(+1 '" 0
and ISINK
4 rnA
700
700
mVoc
VINI+I ~ +1 Voe. V 1NH '" 0
and Vo - 30 Voc
, 0
'0
/JADe
Differential Input Voltage
Keep all VIN'S ~O Voc (or V-,If
V+
v+
Voc
INoteS)
used)
Saturation Voltage
s;:
Output Leakage Current
Note 1: For operating at hl~ temperatures, the LM339A must be derated based on a +125°C maximum Junction temperature and a thermal resistance
of +175"CIW which applies for the device soldered In a printed, circuit board. operating In a stili al( ambient The LM239A and LM139A must be derated
based on a +15O"C maxunum Junction temperature The low bias diSSipation and the ON-OFF charactenstlc of the outputs keeps the chip diSSipation very
small (Pd ~ 100 mW). prOVided the output transistors are allowed to saturate
'
Not. 2: Short Cll'<:UltS from the output to V+ can cause excessive heating and eventual destructIOn The maximum output current IS approximately 20 mA
Independent of the Illf9mtude, of v+
Note 3: ThiS input current Will only eXist when the voltage at any of the Input leads IS dnven negative It IS due to the collector-base Junction of the Input PNP
tranSIstors becommg forward biased and thereby acting as Input diode clamps In additIOn to th1s diode action. there IS also lateral NPN paraSitic transIStor
action on the IC chiP ThIS tranSIStor action can cause the output voltages of the comparators to go to the V+ voltage level (or to ground for a large overdrtve)
for the time duration that an Input IS driven negative Thill IS not destructive and normal output states Will re-establish when the Input voltage. which was
negative. again returns to a value greater than -0 3 VOC'
Note 4: These specifications apply for v+ = +5 Voc and -5SoC ::;;. T A ~ +125°C. unless otherwise stated With the LM239A all temperature specifications
ere limited to _25°C ~ TA S; +8SoC and the LM339A temperature speCifications are limited to DoC::;;' TA ::;;. +70°C
Not. 6. The direction of the mput current IS out of the IC due to the PNP Input stage ThiS current IS essentially constant, Independent of the state of
the output so no loading change eXists on the reference or Input hnes
Note 6:' The Input common-mode voltage or either Input Signal voltage should not be allowed to go negative by more than O.3V The upper end of the
common-mode voltage range IS V+ -1.5V. but either or both Inputs can go to +30 VOC Without damage
'
Note 7: The response tll'l1e speCified IS for a 100 mV Input step With 5 mV overdnve For larger overdrive Signals 300 ns can be obtained. see tyPical
performance characteristics section
Note 8. If the voltage applied to any Input exceeds V+. all four comparator outputs Will go to the high voltage level The low Input voltage state must not
be less than -0.3 Voe (or 0.3 VOC below the magn=tude of the negative power supply. If used)
Note I: At output SWItch point. VOai 1 4 Voe. RS"O{lwlth V+ from 5VOC to30VOC. andover the full Input common mode range IOVoCto V+ -,.SVOC)
'·35
typical performance characteristics
Supply Currant
1.0
"~
.s
0.8
a:
0.6
B
>
i
0.4
+-
0.2
I
~
r;~.0-
~
1
~ ~2S'C
~
7
TA=+70°C
~
40
"
20
0 Voc
g
R'NICM) ~ 109 S1
~
w
VIN leM)
'"
TA ·+125'C-
r-
10
v+ -
6.0
"iSs:
I-
:>-
!:;::
I
TA
~
,,"''"
1-"
is.§.
$TA·-SS'C
10
l-
1\ I TA =+2S"C
;)\ DOl
I
0
'A·tcl-
I
0
40
20
30
" 0001
~
~
0.01
40
, VI
I
I
I
~
" TA ·+25'C
0.1
v+ - SUPPLY VOL TAGE (V oc )
1.0
4.0
2j"'~
5 mV = INPUT OVERDRIVE
-;
I
-:i?"=
.
fOOmV
'M_
-
0
I I I
I I I
0
-50
iA·~sL
-100
!!
I "put Overdrives 6.0
~
5.0
I-
4.0
"
~>
:>-
3.0
~
C>
20
~
0
!:;~
INPUT OVERDRIVE
J
~> 100
"
2
!:;>
TA " 25°C
SO
I I
0
0.5
1.0
loS
2.0
TIME(p.)
Positive
= 100 rnA
0
O.S
II
··rP·"0"'
I I
!!
0
100
5mV
20mV
1.0
S.s
10
10 - OUTPUT SINK CURRENT (rnA)
Response Time for Various
2
~>
TA=+125°~
Transition
I
1.0
C>
'" +t25~C
-
01
§
~
f
I I/,'f
Q
"15
I"put Overdrives - Negative
Transition
.1-
3.0
1.0
>=
!!!
I tiUT tiF
S~TURIATIOIN
f-----
·Response Time for Various
5.0
20
-
'""
TA '" Due
SUPPLY VOLTAGE (V oc )
~.
:>
30
20
10
I-
is"c
I-
RL I~
0
T;.
ffi
I:
,"
,.
I
I
60
,
Output Saturation Voltage
I "put Current
80
TA • -SS'C....j.- l -
I
10
1.5
2.0
TIME (/.lS)
application hints
The LM139A is a high gain, wide bandwidth
device; which, like most comparators, can easily
oscillate if the output lead is inadvertently allowed
to capacitively couple to the inputs via stray
capacitance. This shows up only during the output
voltage transition intervals as the comparator
changes states. Power supply bypassing is not
required to solve this problem. Standard PC board
layout is helpful as it reduces stray input·output
coupling. Reducing the input resistors to < 10 kn
reduces the feedback signal levels and finally,
adding even a small amount (1 to 10 mV) of
positive feedback (hysteresis) causes such a rapid
transition that oscillations due to stray feedback
are not possible. Simply socketing the IC and
attaching resistors to the pins will cause input·
output oscillations during the small transition
intervals unless hysteresis is used. If the input
signal is a pulse waveform, with relatively fast
rise and fall times, hysteresis is not required.
All pins of any unused comparators should be
grounded.
The bias network of the LM139A establishes a
drain current which is independent of the magni·
tude of the power supply voltage over the range
of from 2 Vec to 30 Voc.
It is usually unnecessary to use a bypass capacitor
across the power supply line.
1·36
The differential input voltage may be larger than
V+ without damaging the device (see Note 8).
Protection should be provided to prevent the input
voltages from going negative more than -0.3 Vec
(at 25°C). An input clamp diode can be used as
shown in the applications section.
The output of the LM139A is the uncommitted
collector of a grounded·emitter NPN output tran·
sistor. Many collectors can be tied together to
provide an output OR'ing function. An output
pull·up resistor can be connected to any available
power supply voltage within the permitted supply
voltage range and there is no restriction on this
voltage due to the magnitude of the voltage which
is applied to the V+ terminal of the LM139A
package. The output can also be .used as a simple
SPST switch to ground (when a pull·up resistor is
not used). The amount of current which the
output device can sink is limited by the drive
available (which is independent of V+) and the Il
of this device. When the maximum current limit
is reached (approximately 16 mA). the output
transistor will come out of saturation and the
output voltage will rise very rapidly. The output
saturation voltage is limited by the approximately
60n rsa, of the output transistor. The low offset
voltage of the output transistor (1 mV) allows
the output to clamp essentially to ground level
for small load currents.
r-
3:
.....
CJ)
Voltage Comparators
o
"r-
3:
N
0')
o
LM160/LM260/LM360 high speed differential comparator
general description
features
The LM160/LM260/LM360 IS a very high speed
differential Input, complementary TTL output
voltage comparator with improved characterIStics
over the JJ.A7601JJ.A760C, for which It is a pin-forpin replacement. The device has been optimIZed
for greater speed, input Impedance and fan·out,
and lower Input offset voltage. Typically delay
varies only 3 ns for overdrive variations of 5 mV
to 500 mV.
•
Guaranteed high speed
•
Tight delay matching on both outputs
•
Complementary TTL outputs
•
High input impedance
Complementary outputs having minimum skew
are provided. Applications Involve high speed
analog to digital convertors and zero·crosslng
detectors In diSC file systems.
3:
•
Low speed variation With overdrive variation
Fan-out of 4
•
Low input offset voltage
•
Series 74 TTL compatible
""'----0 ...
INVERTING
OUTPUT I
CJ)
o
Meta' Can Package
Order Number LM160H, LM260H, or LM360H
See Package 11
Dual-In-Line Package
v+
'--t------o '"
W
20ns max
•
schematic and connection diagrams
"r-
OU11
UUTZ
GNU
r-tt-l
w+.-)
Order Number LM360N
See Package 20
Dual-In-Line and Flat Packages
"
Order Number LM160D, LM260D or LM360D
See Package 1
Order Number LM160F
See Package 4
1-37
ab.solute maximum ra't;ings
POSitive Supply Voltage
Negative Supply Voltage
Peak Output Current
Differential I nput Voltage
Input Voltage
+BV
-BV
v+
20 mA
±5V
?V 1N ~ V-
Operating Temperature Range
-5S0C to +12SoC
-2SoC to +8SoC
aOe to +70°C
-6SoC to +150°C
300"C
LM160
LM260
LM360
Storage Temperature Range
Lead Temperature (Soldenng, 10 sec)
electrical characteristics
(TM1N ~TA ~TMAX)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Conditions
Supply Voltage Vee +
Supply Voltage Vee
-
Input Offset Voltage
4.5
5
6.5
-45
-S
-6 S
V
5
mV
Rs ~ 200n
2
Input Offset Current
Input
Bla~
3
/-LA
20
/-LA
13
25
ns
12
20
ns
.S
Current
S
Output Resistance (Either Output)
VOUT=VOH
Response Time
TA
TA
TA
n
100
= 2Soe, Vs = ±SV (Note 1)
=2Soe, Vs = ±SV (Note 2)
= 2Soe, Vs =±5V (Note 31
V
14
ns
TA
2
ns
TA
2
ns
2
ns
Response Time Difference Between Outputs
(tPd of +V ,N1 1- (t pd Of-V ,N2 )
(tpd of +V ,N2 ) - (tp• of -V ,N1 )
(tPd of +V ,N1 ) - (tpd of +V'N21
(tpd Of-V,N,I- (tpd Of-V ,N2 1
Input Resistance
Input Capacitance
Average Temperature Coefficient of Input
Offset Voltage
= 25" e, (Note 11
= 25"e, (Note 1)
T A = 25°C, (Note 11
T A = 2Soe, (Note 1)
f = 1 MH2
f = 1 MHz
Rs = son
Average Temperature CoeffiCient of Input
Offset Current
Common Mode Input Voltage Range
Vs
=±6.5V
Differential Input Voltage Range
Output High Voltage (Either Output)
Output Low Voltage (Either Output)
POSitive Supply Current
Negative Supply Current
±4
2
ns
17
kn
3
pF
8
/-Lv/oe
7
nA/oe
±4.S
V
V
±5
=-320IlA, Vs =±4.5V
ISINK = 6.4 rnA
Vs = ±6.5V
Vs = ±6.SV
lOUT
2.4
V
3
.25
.4
V
18
32
rnA
-9
-16
rnA
Note 1: Response time measured from the 50% point of a 30 mVp_p 10 MHz sinusoidal input to the 50% point of the ·output.
Note 2: Response time measured from the 50% point of a 2 Vp_p 10 MHz sinusoidal input to the 50% point of the output.
Note 3: Response time measured from the start of a 100 mV input step with 5 mV overdrive to the time when the output
crosses the logic threshold.
1·38
r-
~s
Voltage Comparators
general description
features
The LM161/LM261/LM361 IS a very high speed
differential input, complementary TTL output
voltage comparator with Improved characterIStics
over the SE529/NE529 for which It IS a pin-far-pin
replacement- The device has been optimIZed for
greater speed performance and lower Input offset
voltage. TYPically delay varies only 3 ns for
over-drive variations of 5 mV to 500 mV. It may
be operated from op amp supplies (±15V).
•
Independent strobes
•
Guaranteed high speed
•
Tight delay matching on both outputs
•
Complementary TTL outputs
•
Operates from op amp supplies
•
Low speed variation with overdrive variation
...s:
...
"G)
r-
s:N
LM161/LM2611LM361 high speed differential comparators
Complementary outputs haVing minimum skew
are provided. Applications Involve high speed
analog to digital convertors and zero-crossing
detectors In dISC file systems.
...
"c:J)
r-
•
Low Input offset voltage
•
Versatile supply voltage range
schematic and connection diagrams
s:w
20 ns max
...
c:J)
±15V
Dual-I "-Line and Flat Package
"
Order Number LM361N
See Package 22
Order Number LM1610, LM261D or LM361D
See Package 1
Order Number LM161F
See Package 4
+-~==;:~=;::=~-c STROBi2
Metal Can Package
"
jflPllTI
Order Number LM161H or LM261H
See Package 12
logic diagram
"
STROBEl
Vel:
1-39
..
.....
...
....
CD
CW)
:E
absolute maximum ratings
operating conditions
Positive Supply Voltage, V+
Supply Voltage V+
LM16l/LM26l
LM361
Supply Voltage VLM16l/LM26l
LM361
Supply Voltage Vee
LM16l/LM26l
LM361
MIN
........
CD,
+16V
-16V
+7V
+7V
±5V
±6V
600mW
-65·C to +l50·e
Neget,ve Supply Voltage, VGate Supply Voltage, Vee
Output Voltage
N
:E
Differential Input Voltage
Input Common Mode Voltage
Power DISSipation
Storage Temperature Range
Operating Temperature Range
LM16l
LM261
LM36l'
Lead Temperature (Soldering, 10 sec)
........
CD
...
:E
TYP
5V
5V
l5V
l5V
-6V
-6V
-15V
-15V
4,5V
4.75V
5V
5V
5.5V
5.25V
-55·e to +125·e
-25·e to +B5·e
o·eto +70·e
300·e
electrical characteristics
(v+ '" +10V. Vee"" +5V, v- .. -10V, TMIN -s; TA s: TMAX • unless noted)
LIMITS
PARAMETER
CONDITIONS
LMt61/LM261
MIN
Input Offset Voltage
T A "'2SoC
Input Offset Current
T A "'2SoC
Voltage Gam
T A ""2SoC
Input ReslstanCf'
TA =2SoC,f= 1 kHz
logICal '~1" Output Voltage
Vee = 4 75V.
Strobe Input "0" Current
64
MAX
1
5
24
3
20
20
33
24
Vee = 525V,
4V
Vee "'475V
Output Short Circuit Current
Vee = 5 25V, VOUT =- OV
Supply Current 1+
V+ '" 1OV, V- = -10V,
Vee = 525V,
-55°C~TA ~ 125°C
Supply Current 1+
V+ '" lOY, V- '" -10V,
Vee" 5 25V,
OOC'S:TA '$;70"C
Supply Current 1-
V+ '" 10V, V- '" -10V,
Vee = 525V,
- 55°C ~ T A ~ 125"C
Supply Current I-
V+ '" 10V, V- = -lOY,
Vee = 5 25V,
O°C~TA "S:70"C
5
V/mV
"il
33
V
•
200
VSTROBE = 2 4V
Strobe Input "'" Voltage
~
.A
.A
4
rnA
Vee "'475V
30
2
3
5 rnA
rnV
.A
10
3
Vee'" 5 25V.
VSTFIOBE '"
TYP
20
Strobe Input "0" Voltage
Supply Current lee
3
Vee = 4 75V,
'SINK =
Strobe Input "'" Current
1
MIN
2
'SOURCE'" -
logical "0" Output Voltage
MAX
5
Input Bias Current
UNITS
LM361
TYP
V
200
.A
-16
-16
8
8
2
rnA
V
V
2
-18
-55
-18
-55
rnA
45
rnA
5
rnA
rnA
10
10
V+=10V,V-"'-10V,
Vce = 525V,
rnA
18
rnA
-55qC~TA~125°C
Supply Current Icc
'·40
'"
V+ .. 10V, V-· -lOV,
Vee = 525V.
O°C-S:TA -S:70oC
20
TRANSIENT RESPONSE
VIN = 50 mV OverdrIVe
Proplgltlon Dlliay Time hpdto)I
T A =2S"C
I.
20
Propagation Delay Time Itpdt1l1
TA = 2S"C
14
20
5
"
"2
MAX
""'
rnA
20
ns
20
m
'6
n.
Delay Between Output A and B
TA "'2S"C
2
Strobe Delay Time itpdlO)I
'fA" 2SoC
8
8
m
Strobe Delay Time ItpdU) I
,TA = 26°C
8
8
n.
r-
s:
::i
Voltage Comparators
o
LM710 voltage comparator
general description
saturating comparator applications. In fact, the low
stray and wiring capacitances that can be realized
with monolithic construction make the device difficult to duplicate with discrete components operating at equivalent power levels.
The LM710 is useful as a pulse height discriminator, a voltage comparator in high-speed AID converters or a go, no-go detector in automatic test
equipment. It also has applications in digital systems as an adjustable-threshold line receiver or an
interface between logic types. In addition, the low
cost of the unit suggests it for applications replacing relatively simple discrete component circuitry.
The LM710 is a high-speed voltage comparator
intended for use as an accurate, low-level digital
level sensor or as a replacement for operational
amplifiers in comparator applications where speed
is of prime importance. The circuit has a differential input and a single-ended output, with saturated
output levels compatible with practically all types
of integrated logic.
The device is built on a single silicon chip which
insures low offset and thermal drift. The use of
a minimum number of stages along with minoritycarrier lifetime control (gold doping) makes the
circuit much faster than operational amplifiers in
schematic· and connection diagrams
Metal Can
''''''''
. . -+----t:"
GItOItltD
OUTPUT
-~====t--.l~
NOb Pm4connllCtedtllcase
Order Number LM710H
See Package 11
typical applications·
Schmidt Trigger
Line Receiver With
Increased Output
Sink Current
"''"
I"PUT
Level Detector With
Pulse Width Modulator
-'"
Lamp Driver
OUTPUT
,-
*Pm connections shown are for metal can.
1-41
absolute maximum ratings
14.0V
-7.0V
lOrnA
±5.0V
±7.0V
Positive Supply Voltage
Negat.ve Supply Voltage
Peak Output Current
Differential Input Voltage
Input Voltage
Power Dissipation
TO-99 (Note 1)
Flat Package (Note 2)
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldeflng, 10 sec)
300mW
200mW
_55°C to + 125°C
_65°C to +150°C
300°C
electrical characteristics
(Note 3)
PARAMETER
Inpu. Offset Vol.age
CONDITIONS
TA
=25·C. Rs$2OO.Il
VCM
""
0.6
=25·C, V OUT = 1.4V
Input Of"'" Curren'
TA
TA = 2S·C
Voltage Gain
TA = 25·C
Output Resistance
TA = 25°C
TA
""
0.75
13
1250
MAX.
UNITS
2.0
mV
3.0
~A
20
1700
200
2SoC, VIN :5:-5 mV
::::
V OUT
TYP.
OV
Input Bias Current
Output Sink Current
MIN
2.0
mA
2.5
0
ns
40
Aesponie Time
{Not. 41
Inpu. Offset Voltage
Rs$ 2000, VeM = OV
Average Temperature
-SS·C$TASI25·C
Coefficient of Input
3.0
RsSSon
3.0
TA = 125·C
10
mV
~vtc
Offset Voltage
Input Offset Current
0.25
3.0
~
-5S·C
I.S
7.0
~
25·CSTASI25·C
5.0
TA
Average Temperature
Coefficient of Input
'
-55·CSTAS25·C
25
nAtC
15
75
nAtC
27
45
Offset Current
Input Bias Current
TA = -55·C
Input Voltage Range
V- = -7.0V
Common Mode Rejection RatiO
Rs';; 200n
80
Differential Input
Voltage Range
100
dB
V
±5.0V
1000
Voltage Gain
Positive Output Level
V
±5.0
V'N~5mV,
0::;
2.5
3.2
4.0
o
V
'OUT:::; -5 mA
Negative Output Level
VIN :::;-5 mV
Output Sink Current
TA '" 12SoC, VIN
V
-1.0
-0.5
S-5 mV
0.5
1.7
mA
$-5
1.0
2.3
mA
V OUT =oV
TA ==-5SoC, VIN
mV
VO UT =0
Positive Supply Current
VIN $-5 mV
Negative Supply Current
Power Consumption
V IN
:::;-5 mV
5.2
9.0
mA
4.6
7.0
mA
90
150
mW
lOUT =0 mA
Note 1: Rating applies for case temperatures to +12SoC, derate linearly at 5.6 mwtC for ambient temperatures above
+105"C.
Note 2: Derate linearly at 4.4 mwtC for ambient temperatures above +100°C.
Note 3: These speCIfications apply for V+ '" 12V, V- = -6.0V, -5SoC S TA :s. +125°C unless otherWise speCified. The Input
offset voltage and input offset cyrrent (see definitions) are speCified for a logiC threshold voltage of 1.8V at -55°C,
1.4V at +25"C, and 1.0V at +125"C.
Note 4: The response time specified (see definitIOns) is for a 100 mV Input step With 5.0 mV overdrive.
1-42
typical performance characteristics
v+~
12V
V-'-60V
;;
30
I.~
J;
~ 20
~
""" ---1:
U
'Ii"
C
~>
.
";A~~'C
fA· 25°C
TA • ~55°C
,
"
1800
"
10
30
1300
-75 -50 -25
50
20
i
10
!
500
.. be..
'-' ~~
'-'
L.....
[.;"
13
11
12
POSITIVE SUPPLY VOLTAGE 'VI
10
'14
V"I2V V-'-60V
'ouT-D.
TA -25 C
f-~SIT!VE
I\.
~
......
NEGA~IVJ __
~
~
!'.
1/ ~~ ~ '-'
Supply Currant
V-'-SOV
"-
..... ~
~
r-
o
0
26
50
-15 -50 -25 0 25 50 15 100 125·
TEMPERATURE ,'g
75 100 125
TEMPERATURE "CI
,
~ 40
30 20 mY
1UmY
20
> 10
~
.
~ 40
W
30
10~vl
'"
J I
20mV
II
Y+ .. 12V
V-"'-60V
T.. -25 C
"
~
~>
~
...L..I..
~
10 ILl
50
~ .. 50
V- '-SOV
>
0
~"100
;A~2:'CI
60
60
100
120
I
vno~vo,"
...
~
TIME In!)
~:~~V-
;;
~lDD
40
0
20
40
60
80
TIME Ins)
---
..I
V+= 12V
i
Output Voltage
Level
04 •
~"25 C -
0-10
.
0.2
30
~ 20
> 10
....
~ 0
50mV
~
\
0 20mY
W
20mV
;)I
0
INPUT VOLTAGf '~I
.
I I
~
20
-02
Common Mod,e Pul..
Response
!
20
-04
Response Time For
Various Input Overdrives
Response Time For
Various Input Overdrives
i
100II
~
Y+·l1V
~:~~v-
-75 -50 -26
~
"
>
1/
~
10
'\
o
W
1500
S-
0 25 50 75 100 125
TEMPERATURE lOCI
20
G
~
....
Input Offset Currant
Input Bias Current
~30
; ,I'-
;;
2000 f-- f-- 1-.(
w
'"
1500
~
~
I
..:c
z
1400
-10
1.... 25°C
2100
~
w
INPUT VOLTAGE (mV)
I
V"12V
V-'-60V
~ 1600
I"" -I""
-30
i"oo..
z
I- -i-!.t;0
3000
1700
~
I.
10
Voltage Gain
Voltage Gain
Transfer Function
40
100
TT
I
TI-
I I I I
I I
60
TIMElnl)
120
12~_
160
Maximum Pow.
Output Sink
Currant
Dissipation
35
Y+= 12Y
r'-I
6OV
~
w:: 20
~
10
,~
,
v.!
~~
;
~
~
f-+-+---1f-+--+--l-==""""'4
"
f- _
METAL-CAN PACKAGE
f--
f - r i (NOTE
MOUNTErfttf-11
__~-L__~~~~
-25 0 25 50 75 100 125
TEMPERATURE (OC)
_10L-~-4
-75
-so
10
-7~
-50 -25
0
25
50
TEMPERATURE 1°C)
75
100
125
o
'25
"
,
45
65
' 85
105
AM81ENT TEMI'ERATURE "CI
,
125'
1-43
Voltage Comparators
LM710C voltage comparator
general description
The LM710e is a high-speed voltage comparator
intended for use as an accurate, low-level digital
level sensor or as a replacement for operational
amplifiers in comparator applications where speed
is of prime importance. The circuit has a differen·
tial input and a single·ended output, with saturated
output leVels compatible with practically all types
of integrated logic.
with monolithic construction make the device difficult to duplicate with discrete components oper·
ating at equivalent power levels.
The LM710C is useful as a pulse height discriminator,a voltage comparator in high-speed AID converters or a go, no-go detector in automatic test
equipment. It also has applications in digital systems as an adjustable-threshold line receiver or an
interface between logic types. In addition, the low
cost of the unit suggests it for applications replacing
relatively simple discrete component circuitry.
The LM710e is the commercial/industrial version
of the LM710. It is identical to the LM710 except
that operation is specified over a oOe to +70o e
temperature range.
The device is built on a single silicon chip which
insures low offset and thermal drift. The use of a
minimum number of stages along with minoritycarrier lifetime control (gold doping) makes the
circuit much faster than operational amplifiers in
saturating comparator applications. In fact, the low
stray and wiring capacitances that can be realized
schematic* and connection diagrams
Metal Can Package
R..
15
2IK
Uk
'Note Pm 4 connectedte case.
Order Number LM710CH
See Package 11
"""
+-+----11::"
6ROUID
Dual-ln·Line Package
OUTPUT
--=====~-..1.~,
t+)INfUT
1
11
+Yoc(SUHLVI
-VccISUI'I'LYI'
.."
Order Number LM710CN
See Package 22
typical applications *
Line Receiver With
Increased Output
Sink Current
Schmidt Trigger
>';""',...-OUTPUT
''''''
Lev.1 Detector With
Lamp Driver
Pulse Width Modulator
v'
,,'
JUUL
*Pm connections shown are for metal can.
1-44
"""
absolute maximum ratings
Positive Supply Voltage
Negative Supply Voltage
Peak Output Current
Differential Input Voltage
Input Voltage
Power Dissipation (Note 1)
TO-99
Flat Package
Output Short Circuit Duration
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
14.0V
-7.0V
10mA
±5.0V
±7.0V
300mW
200mW
10 sec
O°C to 70°C
_65° C to +150°C
300°C
electrical characteristics
PARAMETER
Input Offset Voltage
(Note 2)
CONDITIONS
MIN
TYP
16
T A • 25°C, Rs <200n
MAX
50
UNITS
mV
VCM =OV
I"put Offset Current
TA "" 2SoC, V OUT = 1.4\1
Input Bias Current
T A ·25°C
18
16
Voltage Gam
TA '" 2SoC
Output Resistance
TA = 2SOC
Output Smk Current
TA = 2SoC, .6.VIN~ 10 mV
1000
50
25
1500
200
1.6
/lA
JJ.A
n
25
mA
V OUT = 0
Response Time
TA = 2SOC
40
ns
(Not. 3)
Input Offset Voltage
Rs:O;200u. V CM
Average Temperature
0°C~TA~70°C
Coefficient of Input
•
65
OV
50
Rs~50n
20
mV
/lvtc
Offset Voltage
75
Input Offset Current
Average Temperature
Coefficient of Input
/lA
25°C~TA:570°C
15
50
nAtC
0°C:O;TA:O;25°C
24
100
nAtC
25
40
Offset Current
oOe
Input Bias Current
TA =
Input Voltage Range
V-· -70V
±S.O
Common Mode Rejection Ratio
Rs ';;20on
70
dB
V
800
Voltage Gain
Positive Output Level
V
98
±5.0
DIfferential Input
Voltage Range
JJ.A
VIN ~10 mV
0-::;
lOUT
25
3.2
-1.0
-0.5
40
V
0
V
$-5 mA
Negative Output Level
VIN :::;-10 mV
Output Sink Current
VIN ::; -10 mY, V OUT
Positive Supply Current
VIN ':S-10 mV
Negative Supply Current
.:
OV
mA
0.5
5.2
90
mA
4.6
70
mA
150
Power Consumption
mW
Note 1: Ratings apply for ambient temperatures to +70°C
Note 2: These specificatIOns- apply for V+ = 12V, V- = 6 OV, O°C < T A < +70° C unless otherWise specified. The mput offset
voltage and Input offset current (see definitions) are speCIfied for aloglc threshold voltage of 1.5V at O°C, 1.4V at +25°C and
1.2V at +70° C.
Note 3: The response time specified (see definitIons)
IS
for a 100 mV mput step with 5.0 mV overdrive.
1-45
typical performance characteristics
Voltage Gain
Transfer Function
40
--
r- ~~=
lZV
II "-60V
30 t-T ... " 2SoC
~
;
1
20
2800
v~= 1211 ._
II "-6011
1600
z
~
1500
r--...
~
~
~
II
"'" ........
30
o
400
10
20
30
40
=
=
~ ......
"u
~
10
o
o
20
"-
40
50
60
10
o
10
20
;
~
~
20
10
~ 40
20mV
10mY
rC
~ 30
~o~VI
2{)mV
11 I
I
1/+= 1211
y-. -60V
30
~
20
~
10
~
lU
40
50
60
1-46
100
120
-04
-02
02
Response
;;
~~:~~~V-
~ 30
"'~20
IAo2Soc -
;:10
I'
~
60
80
TlME(ns)
04
Common Mode Pulse
50mV
40
V-"-60V
"0
TA "25°C
INPUT VOLTAGEM
I
0
~'N
20
14
NEGAtlVJ_
70
100
--
-~
""
LM'
~ou.
...t
~Ai 2;OC1
60
80
TIME Ins)
13
lOUT
r--.. ......
y+: lZV
V- =-60V
40
12
11
~
20mV
1\
0 20mV
0_10
~
v+,. 12V
I
u..L.
I I 1'1
'f,;.~- ~
"
I-P~S1T!VE
T... " 2SoC
20
10
~
10
Response Time For
Various Input Overdrives
Response Time For
Various Input Overdrives
~ 40
w. 30
.......
TEMPERATURE (OC)
TEMPERATURE ("CJ
ioo"""
,d~""
POSITIVE SUPPLY VOL rAGE (V)
v-,,-6dv
r-.. ..... ........
....... r--...
30
70
1/+" 1211
o
TO
60
-'
-'
-'
~
Supply Current
, ,
~
z"
50
Input Offset Current
V- =-60Y
~
YI
TEMPERATURE {OC)
v+: 1211
z 20
w
,.,,?0If!
800
Input Bias Current
~
1200
1300
1200
T~' 2~oC
1600
1400
INPUT VOLTAGE (mV)
..
I2400
2000
i"""'"
w
10
Voltage Gain
1700
120
I I
I I
I
I
40
80
TIME Ins.!
120
160
Voltage Comparators
LM711 dual comparator
general description
The LM 711 contains two voltage comparators
with separate differential inputs, a common out·
put and provision for strobing each side indepen·
dently. Similar to the LM710, the device features
low offset and thermal drift, a large Input voltage
range, low power consumption, fast recovery from
large overloads and compatibility with most Inte·
grated logic circuits.
With the addition of an external resistor network,
the LM 711 can be used as a sense amplifier for
core memories. The input thresholding, combined
with the high gain of the comparator, eliminates
many of the inaccuracies encountered with jcon·
ventional sense amplifier designs. Further, it has
the speed and accuracy needed for reliably detect·
ing the outputs of cores as small as 20 mils.
The LM711 is also useful In other applications
where a dual comparator with OR' ed outputs is
required, such as a double·ended limit detector. By
using common circuitry for both halves, the device
can provide high speed with lower power dissipa·
tion than two single comparators. The LM 711 is
available in either an 10·lead low profile TO·5
header or a 1/4" by 1/4" metal flat package.
schematic·· and connection diagrams
STRon
..~~,.
~--t---------~~~+----.----~--~----------.---
"
Note Pm 5 connected to case
Order Number LM711 H
See Package 14
typical applications··
Sense Amplifier
Wi~h
Supply Strobing
Double-Ended Limit Detector
With Lamp Driver
for Reduced Power Consumption*
.20
"
"
lN155
'"
lM111
02
21114032
...,....-..
~~~~~,:£,_
,os
STROBf
It
RI
Rl
12K
12K
"'".
UPPER
LIMIT
VOLTAGE
liMIT
VOlTAGf
FROM
SENSE
lII'HS
"'".
*Standby diSSipatIOn
IS
about 40 mW
* -Pm connections shown are for metal can
1-47
absolute maximum ratings
+14.0V
-7.0V
25mA
±5.0V
±7.0V
o to +6.0V
300mW
-55°C to 125°C
-65°C to 150°C
300°C
Positive Supply Voltage
Negative Supply Voltage
Peak Output Current
Differential Input Voltage
Input Voltage
Strobe Voltage
Internal Power Dissipation (Note 1)
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
electrical characteristics
CONDITIONS (Note 2)
PARAMETER
I nput Offset Voltage
(These specifications apply for T A = 25°C, V+ = 12V, V- = -6V)
MIN.
TYP_
1.0
Rs:S 200&1, V CM = 0
1.0
Rs :S200&1,-5VS: V CM S:+5V
I nput Offset Current
0.5
1"
Input Bias Current
Voltage Gain
25
750
UNIT
3.5
5.0
mV
mV
10.0
/J- A
75
/J- A
1500
Response Time (Note 3)
40
ns
Strobe Release Time
12
ns
I nput Voltage Range
V- = -7.0V
±5.0
Differentia I Input
Voltage Range
V
±5.0
Output Resistance
V
200
Positive Output Level
V IN
::::
10 mV
Loaded Positive 0 utput Level
V IN
::::
10 mV,l ouT =-5 mA
4.5
2.5
&1
5.0
3.5
V
V
Negative Output Level
V IN ::;-10 mV
-1.0
0
V
Strobed Output Level
VSTROBE:S 0.3V
-1.0
0
V
Output Sink Current
V IN ::;-10 mV, VOUT::::O
Strobe Current
VSTROBE = 100 mV
1.2
2.5
mA
Positive Supply Current
V IN ::;-10 mV
8.6
0.5
Negative Supply Current
130
The following specifications apply for -55°C:S T A
Input Offset Voltage
mA
mA
200
:s
4.5
6.0
Rs 200&1, V CM = 0
Rs:S 200&1
Input Offset Current
20
150
Average Temperature
Coefficient of Input
Offset Vo Itage
5.0
500
Voltage Gain
Note 1: Rating applies for case temperatures to +12SoC; derate linearly at 5.6 mW/oC for ambient
temperatures above 10SoC.
Note 2: The Input offset voltage and input offset current (see definitions) are specified for a logic
threshold voltage of 1.BV at -55'C, 1.4V at +25'C. and 1.0V at +125'C.
IS
mW
:s 125°C:
Input Bias Current
Note 3: The response time specified
mA
0.8
3.9
Power Consumption
1-48
MAX.
for a 100 mV Input step with 5 mV overdnve (see definitions).
mV
mV
/J- A
/J- A
J1vtc
typical performance characteristics
Voltage Gain
Transfer Function
Voltage Gain
3D00
50
40
~
TA = 25"C
..".
f- vV:""2V
'" -6 OV
12S"C
30
~
~
-55~C
~
2D
~
10
Ie
~;c
f-+-+-f-+-+--+-"'*--I
1300
-50
-30
-10
10
3D
TEMPERATURE
50
40
~
~
~
J.'
zo
10
~
20 mV
I
~
i
I-1"'T I
-10 mY
HZDmV
I I
1
v+" ,2V
V-"·6DV
Til. = 2SoC
'"
~
~
~
40
60
80
100
120
~
10
zo
I I
~
50mV
10
'mV
~
-10
10
20
30
40
V· =12V
v- =-60V
TA. = 25"C
J.'
"'
i
~
~
300
::l
~
"
~
10
~
"
au
+=+=
Y+ '" 12Y
V- 2 _60V
3D
\.
4D
1"'-
3D
,
-75
-50 -25
-,
'n~
" ~HRESi1OL~E-
'- .......
10
......
0
25
50
15
-
100 125
Power Consumption
V:'12~ .. _
=~6.0V
I
140
r-...
~
f
120
-15 -50 -25
~
Ito«
~
13D
120
25
50
75
100 125
.,,
f-t--t--t--t--t--t- v·
f--+-+-+-+-+-··l-,:.T~•.'t',:~,o:;'C--l
f-t--t--t--t--t--t--b........
~
f-t--t--t--t--I--t--t--+-+-I
~:tttttt1
1101-+
-50
-30
-10
10
3D
,
25
50
75
100
125
f'C)
3D
INPUT VOLTAGE (mV)
50
I
1
,
-.. 1\
i
,
20
100 LL-L-L-L-L-L-L-L.L-I
0
0
Maximum Power Dissipation
150 .-r-r-r-r-r-r---~
V+ =12V
= -B.DV
i!i
=
~EGA~IVE OUTPUT LEVEL
TEMPERATURE
Power Consumption
v
Iz
.10-'"
f---
-10
-15 -50 -25
TEMPERATURE reI
TIME (ns)
I.'
500
POSITIVE OUTPUT LEVel
-- f-.
40
50
"
160
120
408
Output Voltage Level
50
~
:3
200
3
10
13D
100
TIME (ns)
V·" 12V
y." -6 OV
~
.!II~
50
Input Bias Current
~
~
20mV
1.10
6D
~ "
=
>
Output Pulse Stretching With
Capacitive Loading
TlME!ns)
~
14
"
POSITIVE SUPPLY VOLTAGE (V)
v"'" 12V
Y-"-6DY
TA " 2SOC
I
Common Mode Pulse
Response
~
12
11
1 1
TlME(ns)
~
1
I I
zo
~
20
re)
~
=
>
50
~
.. - ~ F p
.....-r
40
~
I
..
l-
I
"
30
50mV
~
~
"..
V V
i--'"
Strobe Release Time for
Various Input Overdrives
Response Time for Various
Input Overdrives
~
~ ~-:
f--'-
50
INPUT VOLTAGE (mV)
I-
P
.(~\\"'Ioo-"
1500
.00
-1
~
.
,,
" .. f-+-+-f--1'~
"t--+--+--I
~ I~Of--+-+-f--+-+~-+--I
~
1
I
I
-,~~
2500
f-+-+"""~f--+-+--+-+--I
z ..DO
II,
~
f--"
"'r...Ir-+-+-+-+-~:: ~:~v
1700
IA
1
I
CAN PACKAGE
,~ M~TAL
M~UNI'O FlAIT PAICKA "
"
,
25
I
(rOTI' 11
I
'5
65
85
105
125
AMBIENT TEMPERATURE ('C)
1-49
(,)
.....
.....
,...
Voltage Comparators
:E
..J
LM711C dual comparator
general description
The LM711 C contains two voltage comparators
with separate differential inputs, a common output and provision for strobing each side independently. Similar to the LM710C, the device features
low offset and thermal drift, a large input voltage
range, low power consumption, fast recovery from
large overloads and compatibility with most integrated logic circuits.
With the addition of an external resistor network,
the LM711C can be used as a sense amplifier for
core memories. The input thresholding, combined
with the high gain of the comparator, eliminates
many of the inaccuracies encountered with con-
ventional sense amplifier designs. Further, it has
the speed and accuracy needed for reliably detecting the outputs of cores as small as 20 mils.
The LM711C is also useful in other applications
where a dual comparator with OR'ed outputs is
required, such as a double-ended limit detector. By
using common circuitry for both halves, the device
can provide high speed with lower power dissipation than two single comparators. The LM711 C is
the commercial/industrial version of the LM711.
It is identical to the LM711, except that operation
is specified over a O°C to 70°C temperature range.
schematic·· and connection diagrams
"
r-~~--------.---~--~--~~-t--------~~--~---,.
,.
Note Pm 5.connetted to case
Ordor Number LM711CH
See Package 14
lM1111C
Order Number LM711CN
See Package 22
typical applications··
Double-Ended Limit Detector
With Lamp Driver
Sense Amplifier With Supply Strobing
for Reduced Power Consumption·
, - -....- -....-+12V
R7
'"
DI
lN755
02
75V
LM1I1
:~~I':E
......
2N4032
~~_.
BUS
RI
12K
""'EA
LIMIT
STROBE
VOLTAGE
.n.
R2
12K
"'00
LOWER
LIMIT
VOLTAGE
fROM
ounUT
SENSE
LINES
":'
Ri
-'00
*Sta\ldby diSSipatIOn IS abou140 mW
1-50
**Pm connections shown are for metal can.
r-
s:-...I
......
absolute maximum ratings
Positive Supply Voltage
Negative Supply Voltage
Peak Output Current
Differential Input Voltage
Input Voltage
Strobe Voltage
I nternal Power Dissipation (Note 1)
Operating Temperature Range
Storage Temperatu re Range
Lead Temperature (Soldering, 10 sec)
("')
+14.0V
·7.0V
25mA
±5.0V
±7.0V
to +6.0V
300mW
O°C to 70°C
·65°C to 150°C
300°C
o
electrical characteristics
(The following specfications apply for TA = 25°C, V+ = 12.0V, V- = -6.0V unless otherwise specified)
PARAMETER
Input Offset Voltage·
CONDITIONS (Note 2)
MIN.
Rs S200£1, V CM = 0
Rs S 200£1, -5VS;:V CM S;:+5V
TYP.
1.0
1.0
I nput Offset Current
0.5
Input Bias Current
25
Voltage Gain
700
MAX.
5.0
7.5
UNIT
mV
mV
15
/J. A
100
/J. A
1500
Response Time (Note 3)
40
ns
Strobe Release Time
12
ns
Input Voltage Range
V-=-7.0V
Differential Input
Voltage Range
±5.0
V
±5.0
Output·'Resistance
V
200
Positive Output Level
VIN~ 10 mV
Loaded Positive Output Level
VIN 2: 10 mY, louT = -5 mA
4.5
2.5
3.5
-0.5
Negative Output Level
VIN :::;-10 mV
-1.0
Strobed Output Level
VSTROBE S 0.3V
-1.0
Output Sink Current
VIN :::;-10 mY, VOUT 2:0
Strobe Current
VSTROBE = 100 mV
1.2
Positive Supply Current
VIN :::;-10 mV
8.6
0.5
£1
5.0
0
0
0.8
130
Power Consumption
V
V
mA
2.5
mA
mA
3.9
Negative Supply Current
V
V
mA
230
mW
The following specifications apply for O°C S TA S +70°C:
Input Offset Voltage
RsS 200£1, V CM = 0
Rs S 200£1, -5Vs;:VCM S;:+5V
Input Offset Current
I nput Bias Current
Average Temperature
Coefficient of Input
Offset Voltage
Voltage Gain
5.0
6.0
10
mV
mV
25
/J.A
150
/J. A
/J.vtc
500
Note 1: Ratings apply for ambient temperatures to 70° C.
Note 2: The Input offset voltage and Input offset current (see definitIOns) are specifIed for a logic
threshold voltage of 1 SV at O°C, 1AV at 2SoC, and 1.2V at +70'C.
Note 3: The response time specified (see definitions) IS for a 100 mV Input step with 5 mV overdrive.
1·51
(.)
~
~
~
typical performance characteristics
Voltage Gain
Transfer Function
5.0
~+.I12~-
~
~
~
5
1100
IA'
1
lO
T. -10°C-
16
2.0
!
1&00
~
1500
t;
10
. --
-.
-5.0
-l.O
~
II
TA ·25"C- l- I--
-1.0
1.0
l.O
V-·-6.0V-
......
!<
~
~
50
1400
1200
5.0
o
'0
~ •
Y+"12V
Y-"'-6.0V
1A "'25°e
&0
80
5.0 mY
10
100120
~ ...
~
I
'mV
30
40
100
50
).12~
l
..........
.........
~
2.'
...
12.
16•
.......
20
10
300
400
SOD
Power Consumption
V- 0-6.0VlO
210
TlMEtns'
v- =....fi.Ov
:1
I.
"
13
Output Pulllll $tretching With
Capacitive L08'ling
TA "'25"e
;;
..
10
10
Input Bias Current
i
TIME( ...)
1-52
20
=12V
!<
~
60
TlME(ns)
~
~
2.amV
40
3.'
2.'
I
I
12
II
I I
•
~
I~
•.'""!""'T"
Common Mode Pulse
R_onse
~
~
~
;;;;; I-
v+= 12V
Y-=-iOY
14" 25°C
TlME!m)
v·
.2..~"
v,"
~""'", ...~::::;
POSITIVE SUPPLY VOLTAGE (VI
_
•
40
50
CCI
1/
~
!<
40
lO
L.-
V
,1·1
5.
20
t7
.00. ..... V
V
I I
10.
~
I
~~
.500 f -
Strobe Relaase Time for
Various Input Overdrives
II I if, / F-' 5.DmV 11
-10 mY
....,..-r I
til
2.'
-f2.0 mV
l
~
20
TEMPERATUR~
V.rio~s
1
SOO
20 mV
4'30
...
1300
10
~
....
I
'.=25°&
2500
200'
r--..
INPUT VOLTAGE (mY)
R_onse Time for
I"put Overdrives
300.
)'12~-
TA=DOCj;M-
r- v-· -6.0V
4.0
Voltage Gain
1800
.......
~
130
~
8
12.
I
II.
'"
-
v+-,zv
v- ......ov
! ...
.
lA" 25°e
-"
'00 L.L..LJ-L-L-L-L-L-L-I
o
'0
20
lO
40
50
TEMPERATURE fOCI
60
10
-60
"'30
-10
10
3.
INPUT VOLTAGE (mV)
Voltage Comparators
LM1514/LM1414 dual differential voltage comparator
general description
The LM1514/LM1414 isa dual differential voltage
comparator intended for applications requiring
high accuracy and fast response times. The device
is constructed on a single monolithic silicon chip.
The LM1514/LM1414 is useful as a variable threshold Schmitt trigger, a pulse height discriminator,
a voltage comparator in high-speed A-D converters,
a memory sense amplifier or a high noise immunity
line receiver. The output of the comparator is
compatible with all integrated logic forms. The
LM 1514/LM 1414 meetor exceed the specifications
for the MC1514/MC1414 and are pin-for-pin reo
placements. The LM1514 is available in the ceramic
dual-in-line package. The LM 1414 is available in
either the ceramic or molded dual-in-line package.
The LM1514 is specified for operation over the
_55°C to +125°C military temperature range. The
LM1414 is specified for operation over the O°C
to +70° C temperature range.
features
•
•
•
•
•
•
•
Two totally separate comparators per package
Independent strobe capability
High speed 30 ns typ
Low input offset voltage and current
High output sink current over temperature
Output compatible with TTUDTL logic
Molded or ceramic dual-in-line package
schematic and connection diagram
Dual·ln-Line Package
Order Number LM1414J or LM1514J
See Package 16
Order Number LM1414N
Sae Package 22
1-53
lilt
po
absolute maximum ratings
#
,
(Note
1)
.'
....::E
POSItive supply voltage
NegatIVe supply voltage
.......
+140V
-70V
10mA
±5.0V
±7.0V
Peak output current
Differential Input voltage
Input voltage
LO
po
::E
.....
electrical characteristics
PARAMETER
for T A
Power diSSipation (Note 21
Operating temperature Range
LM1514
LM1414
Storage temperature range
Lead temperature (soldermg, 10 sec)
\ 6OO,mW
_55°C to '12soe
to +70D C
_65°C to +150oe
300°C
aOe
= 25°C, V+ = +12V, V- = -6V, unless otherwise specified
CONDITIONS
MIN
LM1514
TVP
MAX
MIN
lM1414
TYP
MAX
Input Offset Voltage
R. Si 2000, VCM = OV, VOUT ' 1.4V
0.6
20
.1.0
5.0
Input Offset Current
VCM = av. VOUT = 1 4V
08
30
12
50
Input Bias Current
1250
VoltageGatn
Output Resistance
200
i50
i5.0
i5.0
Input Voltage Range
V-= -7.0V
i50
Common Mode Rejection RatiO
R. Si 2OOIl, V-· -7 OV
80
Positive Output Voltage
VIN ~7.0 mV.O-S; lOUT $-50 mA
2.5
3.2
Negative Output Voltage
VIN $-70 mV
-1.0
..(l.5
Strobed Output Voltage
VSTAOBE ~ O.3V
-1.0
Strobe "0" Current
VSTROBE ..
PositIVe Supply Current
VIN '5,-7 mV
NegatIVe Supply Current
Y,N '5,-7 mV
100 mV
Power Consumptton
100
pA
pA
70
4'.0
11
V
V
100
25
3.2
0
-1.0
-{l.5
-0.5
0
-10
-12
-2.5
180
(Noto3)
mV
1000
200
Differential Input Voltage Range
Rssponse,Time
25
20
UNITS
dB
40
V
0
V
-0.5
0
V
-1.2
-2.5
mA
18
18
mA
-14
-14
mA
300
mW
300
180
30
n.
30
LM1514/lM1414: The follOWing apply forT L s: TA ~T H (Note 4) unless Otherwise specified
Input Offset Voltage
Rs s::zoon, VOUT = 1.SV for T A"" T L
VCM =OV, VOUT = 1.0V forTA = TH
3.0
30
Voltage
50
3.0
VCM
-ov. VOUT= 1.SV, TA =TL
V CM "'OV, V OUT
7.0
3.0
= 1 OV, TA =TH
Y,N $--90 mV, V OUT ;;:::OV
2.8
75
7.5
mV
mV
pA
pVloC
pA
pA
800
1000
Gain
Output Sink Current
40
45
Input Bias Current
Temperature Coefficient of
Input Offset Voltage
Input Offset Current
6.5
6.5
4.0
1.6
25
mA
Note 1: Voltage values are With respect to network ground terminal. Positive current Isdeflned as current Into the referenced pin.
Note 2: LM1514 ceramic package: The maximum Junction temperature IS +1S0°C, for operating at elevated temperatures,
deVices must be derated linearly at 125 mW/oC LM1414 ceramic package' The maximum Junction temperature IS +95°C for
operating at elevated temperatures, devIces must be derated linearly at 12.5 mW/oe. LM1414 molded package: The maxImum
junction temperature IS + 11SoC, for operating at elevated temperatures, devices must be derated linearly at 6.7 mwtC.
Note 3: The response time specified (see DeflOitlons) for a 100 mV Input step With 5 mV overdrive.
Noto4: For LM1514, TL = -55°C, TH = +125°e. For LM1414, TL = oOe, TH = +70oe.
1·54
o
:I:
o
o
w
Level Translators/Buffers
~
.......
o
:I:
o
o
DH0034/DH0034C high speed dual level translator
w
~
(')
general description
features
The DH0034/DH0034C is a high speed level trans·
lator suitable for interfacing to MaS or junction
FET analog switches. It may also be used as 'a
universal logic level shifter capable of accepting
TTL/DTL input levels and shifting to CM L, MaS,
or SL T levels.
• Fast switching, tpdO: typically 15 ns; tpd 1 :
typically 35 ns
•
•
•
•
Large output voltage range: 25V
Input is TTL/DTL compatible
Low output leakage: typically 0.1 IlA
High output currents: up to ±100 mA
schematic and connection diagrams
Metal Can Package
Dual-in-Line Package
Nt
1
A,
2
14
Vee
•
Nt
B,3
GND
y.
GND
•
y.
,
OUTPUT' I
TOPVIEW
%CllcUitShown
Nt
GND
1
Order Number DH0034H
or DH0034CH
TOP VIEW
See Package 12
Order Number DH0034D
or DH0034CD
See Package 1
typical applications
TTL to IBM (SLTI Logic Levels
5 MHz Analog Switch
5.0V
ANALOG
l ----,I
r-----I
OUT
'10
.,..
I
OUTPUT 1
INPUT'
-.1V
INPUT 2
I
L.---·15
"'IV
J ____
DHDl34
OUTPUT I
I
I
.11
..I
.,..
2-1
(,)
~
CO)
absolute maximum ratings
o
o
J:
7.0V
-30V
Vee Supply Voltage
Negative Supply Voltage
Q
.......
~
CO)
Positive Supply Voltage
Differential Supply Voltage
Maximum Output Current
Input Voltage
Operating Temperature Range:
o
o
J:
Q
DHOO34
DHOO34C
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
electrical characteristics
PARAMETER
+25V
25V
100mA
+5.5V
-55°C to +125°C
O°Cto +85°C
_65°C to +150°C
300°C
(See Notes 1 & 2)
CONDITIONS
MIN
DHOO34
TYP
MAX
Vee = 4.5V
Vee = 4.75V
Logical "0"
Input Voltage
Vee = 5.5V
Vee = 4.75V
Logical "1"
Input Current
Vee = 5.5V, Y'N = 2.4V
Vee = 5.25V, Y'N = 2.4V
Logical "1"
Input Current
Vee = 5.5V, Y'N = 5.5V
Vee = 5.25V, Y'N = 5.5V
1.0
Logical "0"
Input Current
Vee = 5.5V, Y'N = O.4V
Vee = 5.25V, Y'N = 0.4V
1.6
Power Su ppl y
Power Supply
Current
Logic "1"
(Note 3)
Vee = 5.5V, Y'N = 4.5V
Vee = 5.25V, Y'N = 4.5V
(Note 3)
Vee = 5.5V, Y,N = OV
Vee = 5.25V, Y'N = OV
Logical "0"
Output Voltage
Vee = 4.5V, lOUT = 100 mA
Vee = 4.5V, louT = 50 mA
Output Leakage
Current
Vee = 5.5V, Y,N = 0.8V
V+· V-: 25V
Transition Time to
Logical "0"
Vee = 5.0V, V3: OV,TA : 25°C
V- = -25V, RL : 510n
15
25
Transition Time to
Vee = 5.0V, TA : 25°C
V- = -25V, RL : 510n
35
60
Logic "0"
Logical "1"
DHOO34C
TYP
2.0
V
0.8
V
0.8
40
IJA
40
mA
1.0
mA
1.6
30
37
36
38
37
48
V- + .50
V-+ .3
V- + .80
V- + .65
48
V- + .50 V- + .75
V-+ .3 V- + .50
0.1
mA
30
5
mA
0.1
Note 2: All typical values are for T A = 25"C.
2·2
from
Vee supply.
V
V
5
IJA
15
35
ns
35
65
ns
and O°C to +85°C for the DH0034C with a 510 ohm resistor connected between output and ground,
and V- connected to -25V. unless otherwise specified.
dra~n
UNITS
2.0
Note 1: These specifications apply over the temperature range _55°C to +12SoC for the DHOO34
Note 3: Current! measured is total
MAX
,
Logical "1"
Input Voltage
Current
MIN
C
::t
o
o
w
~
........
theory of operation
C
::t
o
When both inputs of the DH0034 are raised to
logic "1", the input AND gate is turned "on"
allowing 01's emitter to become forward biased.
01 provides a level shift and constant output current. The collector current is essentially the same
Vee - VeE
as the emitter wh ich is given by
R1
Approximately 7.0 mA flows out of 01's collector.
o
w
About 2 mA of 01's collector current is drawn off
by pull down resistor, R2. The balance, 5 mA, is
available as base drive to 02 and to charge its
associated Miller capacitance. The output is pulled
to within a VSAT of V-. When either (or both}
input to the DH0034 is lowered to logic "0," the
AND gate output drops to 0.2V turning 01 off.
Deprived of base drive 02 rapidly turns off causing
the output to rise to the V3 supply voltage. Since
02's emitter operates between 0.6V and 0.2V, the
speed of the DHOO34 is greatly enhanced.
~
n
applications information
1. Paralleling the Outputs
The outputs of the DH0034 may be paralleled to
increase output drive capability or to accdmplish
the "wire OR". In order to prevent current hogging by one output transistor or the other, resistors of 2 ohms/100 mA value should be inserted
between the emitters of the output transistors and
the minus supply.
2. Recommended Output Voltage Swing
The graph shows boundary conditions which
goVern proper operation lof the DH0034. The
range of operation for the negative, supply is
shown on the X axis and must be between -3V
and -25V. The allowable range for the positive
supply is governed by the value chosen for V-. V+
may be selected by drawing a vertical line through
the selected value for V- and terminated by the
boundaries of the operating region. For example, a
value of V- equal to -6V would dictate values of
25
...
20
15
co
>
5
iil
-5
-10
-15
~
~
=
>
t
~
>
~
V-<-3V
v+ -V-::;25V
I
10
-20
-25
.;'
.;'
JLI"""
~.OPERATING REGION r- ri;"
,/
I-'
V
-24
-I.
-12
-&
NEGATIVE SUPPLY VOL lAGE (-VI
V+ between -5V and +19V. In general, it is desirable to maintain at least 5V difference between
the supplies.
2-3
Level Translators/Buffers
DM5406/DM7406.DM5416/DM7416
hex inverter buffers/drivers
CD
o
~
......
~
genera I description
features
These TTL hex inverter buffers/drivers are fully
compatible for use with TTL and OTL logic circuits. Each inverter features high-voltage, opencollector outputs (OM5406/OM7406 30 volts
minimum breakdown and OM541610M7416 15
volts minimum breakdown). These inverters also
feature high sink current capability. (OM 5406,
OM5416 30 mA and OM7406, OM7416 40 mAIo
•
•
Q
.......
CD
o
~
an
~
Q
Input. clamp diodes
High voltage open·collector outputs
OM5406/DM7406
OM54161DM7416
• High sink current capability
DM5406, OM5416
DM7406, DM7416
• 15'"s-typical propagation delay time
30V
15V
,
30mA
40mA
schematic and connection diagrams
Dual-ln·Line and Flat Package
r-----t-----------.-------__ov~
••
••
3.
14
13
12
11
1D
OUTPUT
I.,UT o--4I~~
••
~--------
__----__----__----____o.N.
Note Component values shown Ire nomlllli
TOP VIEW
.N.
Order Number DM5406J, DM7406J,
DM5416J or DM7416J
See Package 16
Order Number DM5406N, DM7406N,
DM5416N or DM7416N
See Package 22
Order Number DM5406W or DM5616W
See Package 27
2·4
absolute maximum ratings.(Note
Supply Voltage
Input Voltage
Output Voltage
operating conditions
1}
7.0V
5.5V
30V
15V
_65°C to +150°C
300°C
DM5406/DM7406
DM5416/DM7416
Storage Temperature Range
Lead Temperature, (Soldering, 10 Seel
Supply Voltage
DM5406,DM5416
DM7406,DM7416
Temperature (T A)
DM5406,DM5416
DM7406,DM7416
MIN
MAX
4.5
4.75
5.5
5.25
-55
0
+125
70
"j.
., . UNITS
V
V
Output Sink Current
DM5406,DM5416
DM7406.DM7416
30
40
mA
rnA
electrical characteristics (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
2
Logical "1" Input Voltage
V
0.8
l,.oglcal "0" Input Voltage
Output Breakdown Voltage
DM5406/D M7406
DM5416/DM7416
UNITS
V
Vee = Max, 10FF = 250 !LA,
V 'N c O,8V
30
V
Vee"" Max"i oFF
15
V
:.
250 p.A,
V ,N =08V
Logical" 1" Output Current
DM5406/DM7406
DM5416/DM7416
Vec
Vee
= Max, V OH = 30V, V ,N = 0.8V
= Max, VOH = 15V, V,N = 0.8V
Logical "0" Output Voltage
Vee'" Min, } lOUT = Max.
VIN '" 2V.
lOUT = 16 rnA
Logical "1" Input Current
Vee = Max, VIN
Vee:' Max, VIN
Logical "0" Input Current
Vee = Max, VIN = O.4V
Supply Current - Logical" 1"
Vee = Max, VIN
logical "0"
= 2,4V
= S.5V
Propagation Delay to a Logical "0".
40
1
!LA
mA
mA
42
mA
Vee = Max, V 1N = 5V
27
38
mA
Vcc
lpd1
V
V
-1.6
V
'15
23
ns
10
15
ns
= 110U
= 5 OV, T A = 25°C,
C L = 15 pF, RL
-1.5
mA,
= 5.0V, T A = 25°C,
C l = 15 pF, RL
Propagation Delay to a Logical "1",
0.7
0.4
30
Vcc
tpdQ
!LA
!LA
= OV
Vce = 5.0V, l,N = -12
T A = 25°C
Input Clamp Voltage
250
250
= 110n
Note 1: "Absolute Maximum Ratings" are those values beyond which the operation of the deVice cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to Imply that the deVices should be operated at these limits. The table
of "Electrlcal Characteristics" provides conditions for actual deVice operation.
Note 2: Unless otherwise specified min/max limits apply across the _55°C to +12SoC temperature range for the OM 5406,
DM5416 and across the O°C to 70°C range for the DM7406,DM7416. All tYPlcals are gIven for VCC = 5.0V and TA = 25°C.
ac test circuit and switching time waveforms
Vee
INPUT
~
5V
>--t---o
OUTPUT
15pf
2·5
Level Translators/Buffers
OM5407/0M7407,OM5417/0M7417
hex buffers/drivers
,....
o
'It
,....
::E
general description
features
These TTL hex buffers/drivers are fully compatible
for use with TTL and DTL logic circuits. Each
buffer features high-voltage, open-collector outputs
(DM5407/DM7407 30V minimum breakdown and
DM5417/DM7417 15V minimum breakdown).
These buffers also feature high sink current capa·
bility (DM5407, DM5417 30 mA and DM7407,
DM7417 40 mAl.
•
•
Q
.......
,....
o
'It
Ln
::E
Q
Input clamp diodes
High voltage open·collector outputs
DM5407/DM7407
DM5417/DM7417
• High sink current capability
DM5407,DM5417
DM7407,DM7417
• 14 ns typical propagation delay time
• 145 mW typical power dissipation
30V
15V
30mA
40mA
schematic and connection diagrams
Dual-ln·Line and Flat Package
r-----t-----t---------Ov~
OUTPUT
INPUT
14
13
12
11
1D
0-_ _'
,.
L..--------....----....----....-c .N.
Note Component values sflown are nommal
TQPVIEW
G••
Order Number DM5407J, DM7407J,
DM5417J or DM7417J
See Package 16
Order Number DM5407N, DM7407N,
DM5417N or DM7417N
See Package 22
Order Number DM5407W or DM5417W
See Package 27
2·6
absolute maximum ratings
Supply Voltage
Input Voltage
Output Voltage
operating conditions
(Note 1)
7.0V
5.5V
JOV
15V
_65°e to +1500 e
3OQoe
DM5407/DM7407
DM5417/DM7417
Storage Temperature Range
Lead Temperature (Soldering, 10 secl
electrical characteristics
Supply Voltage (Vee I
DM5407,DM5417
DM7407,DM7417
Temperature (TAl
DM5407.DM5417
DM7407.DM7417
Output Sink Current
DM5407.DM54'17
DM7407.DM7417
MIN
MAX
UNITS
4.5
4.75
55
5.25
V
V
-55
0
+125
70
°e
°e
mA
mA
30
40
(Note 2)
PARAMETER
MIN
CONDITIONS
Loglca' "l"lnput Voltage
TVP
MAX
UNITS
V
2
0.8
Logical "0" Input Voltage
V
Output Breakdown Voltage
DM5407/DM7407
Vee = Max. IOFF = 25O#A. V IN
""
2.0V
30
DM5417/DM7417
Vee"" Max,I oFF
""
20V
15
LogIcal "0" Output Voltage
Vcc=MIn}
V ,N =08V
Loglca' "1" Input Current
Vee= Max
Vee = Max
V ,N
Vee"" Max
V ,N
V,N
Propagation Delay to a Logical "1",
'tpd1
V
V
V
0.7
04
V ,N = 24V
V ,N =5 5V
Vee = Max
- 0.4V
= 5.0V
=OV
=Max
Vce = 5.0V liN = -12 rnA, TA = 2SOC
Vee =5.0V, T A = 25°C, CL = 15 pF, RL = 1101l
Vce = 5.0V, TA = 25°C, CL = 15 pF, RL = 1100
Vee
V
lOUT = l6mA
Logical "0" Input Current
Propagation Oelay to a Logical "0", tpdQ
250$o!A, V"N
lOUT"'" Max
Supply Current - Logical "1"
Logical "0"
Input Clamp Voltage
""
40
1
jlA
rnA
-1.6
rnA
28
21
41
30
rnA
rnA
-1.5
V
20
30
ns
6
10
ns
Note 1: "Absolute MaXimum Ratmgs" are those values beyond which the operation of the device cannot be guaranteed. Except
for "Operatmg Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table
of "Electrlcal Characteristics" prOVides conditions for actual device operation.
Note 2: Unless otherwise specIfied mm/max limIts apply across the -55"t: to +125°e temperature range for the DM5407,
DM5417 and across the O°C to 700 e range for the DM7407, DM7417. All typieals are gIven for Vee = 5.0V and TA = 25°e.
ac test circuit and switching time waveforms
l r<1IH
Vcc=5V
"'UTJ'~
RL =110f!
I
OUTPUT
INPUT
":'
r'C'"'
OUTPUT
~ r;=
10.
t·
v
if<"'~
~]1~
,,.
'v
v
~cv~
m
oc
2-7
Level Translators/Buffers
DM5426/DM7426
quad 2-input TTL-MOS interface gate
general description·
These Series 54/74 compatible gates are high output voltage versions of the OM 5403 (SN5403).
OM7403 (SN7403)_ Their open-collector outputs
may be "pulled-up" to +15 volts in the logical
"1" state thus providing guaranteed interface between TTL and MOS logic levels_
In addition the devices may be used in applications
where it is desirable to drive low current relays or
lamps that require up to 15 volts_
features
•
15V standoff voltage
• Pin compatible with OM5403/0M7403
schematic and connection diagrams
Dual-In-Line Package
r----i~----o
v"
16K
.K
OUTPUT
,NPuTi o-::-+-~
'----+--0.0.
.N'
TOPYIEW
Order Number DM5426J or DM7426J
See Package 16
Order Number DM5426N or DM7426N
See Package 22
typical applications
"V
+12V
NSC MUS shift register
(Example MM5006)
..V ---,
Note. Normal voltages applied to MOS shift
reglsteTS have been shifted by +1 OV for thiS
application
2-8
L---12V
absolute maximum ratings
7V
5.5V
15V
Vee
Input Voltage
Output Voltage
Operating Temperature Range
OM 5426
OM 7426
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
electrical characteristics
PARAMETER
-55°C to 125°C
O°C to 70°C
-65°C to +150°C
300°C
(Note 1)
CONDITIONS
Input Diode Clamp Voltage
Vee = 5.0V, T A= 25°C
liN = -12 mA
Logical "1" Input Voltage
V
Logical "0" Input Voltage
4.5V
Vee = 4.75V
Logical "1" Output Current
4.5V
Vee = 4.75V VIN = 0.8V
MIN
4.5V
ee = 4.75V
2.0
TYP
MAX
UNITS
-1.5
V
V
,
0.8
50
V
fJA
V OUT = 12V
Logical "1" Output Breakdown
Voltage
4.5V
Vee = 4.75V V IN = OV
15
V
louT= 1 mA
V
Logical "0" Output Voltage
4.5V
V IN = 2.0V
ee= 4.75V
0.4
V
louT= 16mA
Logical "1" Input Current
5.5V
Vee = 5.25V V IN = 2.4V
40
fJA
Logical "1" I nput Current
5.5V
Vee = 5.25V VIN = 5.5V
1
mA
Logical "0" I nput Current
5.5V
Vee= 5.25V VIN =0.4V
-1.6
mA
Supply Current - Logical "0"
(Each Gate)
5.5V
V ee ='5.25V VIN = 5.0V
3.0
5.1
mA
Supply Current - Logical "1"
(Each Gate)
5.5V
Vee = 5.25V VIN =OV
1.0
1.8
mA
Propagation Delay Time to a
Logical "0", tpdO
Vee = 5.0V, TA = 25°C
COUT = 15 pF, RL = lk
8
17
ns
Propagation Delay Time to a
Logical "1 ", tpd1
Vee = 5.0V, TA = 25°C
COUT = 15 pF, RL = lk
14
24
ns
,
o
Nota 1: MiniMax units apply across the guaranteed temperature range -25°C to +125°e for the DM5426 and across the
oOe to +70 e for the DM7426 unles. otherwIse specified. All typlcals are gIven for Vee = 5.0V and TA = 25°C.
ac test circuit and switching time waveforms
.,y
~
v~
+24V/
Teo",
INPUT
J-L
\ -13V--
1
I
I
I
I
ounUT~
::
tllllO~
I
~I
f=1MHt
t.=,,=10111
","1011S
1
:-t
..
2·9
o
o
00
00
Level Translators/Buffers
:!
Q
........
o
o
....00
DM7800/DM8800 dual voltage translator
Q
general description
features
The DM7800/DM8800 are dual voltage translators
designed for interfacing between conventional TTL
or DTL voltage levels and those levels associated
with high impedance junction or MOS FET-type
devices_ The design allows the user a wide latitude
in his selection of power supply voltages, thus providing custom control of the output swing. The
translator is especially useful in analog switching;
and since low power dissipation occurs in the "off"
state, minimum system power is required.
•
:!
31 volt (max) output swing
•
1 mW power dissipation in nor~al state
•
Standard 5V power supply
•
Temperature range:
DM7800
DM8800
•
Compatible with all MOS devices
schematic and connection diagrams
Metal Can Package
OUTPUT X
TOI'VIEW
Order Number DM7800H
or DM8800H
See Package 12
typical applications
4-Channel Analog Switch
T
Bipolar to MOS I nteriacing
T
r------I
r lOi _ _ _ 4.l...,1
I
I
on
OR
SWITCH
I
MM&51
ANALOG INPUT
t·I
I
FO..r---.cCO I
2-H:f"JH">c.....t.+t1
ANALOG INPUT 2
I
INPUT
LEVElS
INPUT~~
L1---r
ANAlOGINPUTl
':'"
ANALOG INPUT 4
ANALOG OUTPUT
... Analog sllJIlals wlthm the range of +8V to -BV
rJ---0
on~MOSS"IFT
OR
REGISTER
TTL
OMJlOO
I
lEVElS~
TTL
I
_55°C to +125°C
O°C to +70°C
-IOV
c
s:.....
00
absolute maximum ratings
o
o
......
7.aV
Vee Supply Voltage
V 2 Supply Voltage
-3aV
+3aV
V 3 Supply Voltage
V 3,V 2 Voltage Differential
4aV
Input Voltage
5.5V
_65°C to +15aoC
Storage Temperature Range
Operating Temperature Range
_55°C to +125°C
DM78aa
aOc to 7aoC
DM88aa
3aaOc
Lead Temperature (Soldering, 1a sec)
electrical characteristics
c
s:00
00
o
o
(Note 1)
CONDITIONS
PARAMETER
~
DM78aa
DM88aa
Vee
Vee
Input Voltage
DM78aa
DM88aa
Vee ~ 4.5V
Vee - 4.75V
Logical" 1" I nput Current
DM78aa
DM88aa
Vee
Logical "1" Input Current
DM78aa
DM88aa
Vee ~ 5.5V
Vee - 5.25V
Y,N
DM78aa
DM88aa
Vee ~ 5.5V
Vee ~ 5.25V
Y'N ~ a.4V
DM78aa
DM88aa
Vee ~ 5.5V
Vee - 5.25V
Y'N ~ a.8V (Note 5)
Logical "1" Input Voltage
Logical
Logical
"a"
"a"
I nput Current
Output Leakage Current (Note 2)
~
~
Vee~
4.5V
4.75V
5.5V
5.25V
~
5.5V
Y'N = 2.aV (Note 5)
Power Supply Current
Logical "a" (Note 3)
(Each Gate)
DM78aa
DM88aa
Vee = 5.5V
Vee = 5.25V
Y,N
Power Supply Current
Logical" 1" (Note 3)
(Each Gate)
DM78aa
DM88aa
Vee ~ 5.5V
Vee ~ 5.25V
Y'N ~ av
Output Voltage
UNITS
V
Y'N ~ 2.4V
Vee = 4.5V
Vee ~ 4.75V
"a"
MAX
a.8
DM78aa
DM88aa
Logical
TYP
(Note 4)
2.a
TA ~ 25°C
Output Collector Resistor
MIN
~
-0.2
11.5
16.a
5
p.A
1
mA
-a.4
mA
1a
p.A
2a.a
kn
V2 +
4.5V
V
2.a
V
a.85
1.6
mA
a.22
a.41
mA
Output
TA ~ 25°C
C ~ 15 pF (Note 6)
25
70
125
ns
Transition Time to Logical "1" Output
TA ~ 25°C
C ~ 15 pF (Note 7)
25
62
125
ns
Transition Time to Logical
"a"
Note 1: Minimax limits apply across the guaranteed temperature range of -55°C to +12So,C for the DM7800 and
for the DM8800 unless otherwise specified.
Note 2: Current measured IS ~rawn from V3 supply.
Note 3: Current measured IS drawn from Vee supply.
Note 4: All typical values are measured at T A = 2Soe with Vee = S.OV, V2 = -22V, V3 = +8V.
Note 5: SpeCification applies for all allowable values of V2 and V3.
Note 6: Measured from 1.5V on Input to 50% level on output.
Note 7: Measured from 1.SV on Input to logic "0" voltage, plus lV.
oOe to +70°C
2·11
o
o
CO
CO
theory of operation
:E
The two input diodes perform the AND function
on TTL or DTL input voltage levels. When at least
one input voltage is a 10gicar"0", current from Vee
(nominally 5.0V) passes through R 1 and out the
input(s) which is at the low voltage. Other than
small leakage currents, this current drawn from Vee
through the 20 kn resistor is the on Iy source of
power dissipation in the logical "1" output state.
Q
.......
o
o
....CO
:E
Q
When both inputs are at logical" 1" levels, current
passes through R 1 and diverts to transistor 0 1 , turn·
ing it on and thus pulling current through R2 . Current is then supplied to the PNP transistor, O 2 , The
voltage losses caused by current through 0 1, D3 ,
and O2 necessitate that node P reach a voltage sufficient to overcome these losses before current begins to flow. To achieve this voltage at node P, the
inputs must be raised to a voltage level which is one
diode potential lower than node P. Since these levels
are exactly the same as those experienced with conventional TTL and DTL, the interfacing with these
types of circuits is achieved.
Transistor O 2 provides "constant current switching" to the output due to the common base connection of O 2 , When at least one input is at the
logical "0" level, no current is delivered to O 2 ; so
that its collector supplies essentially zero current
to the output stage. But when both inputs are raised
to a logical "1" level current is supplied to O2 ,
Since this current is relatively constant, the collector of O 2 acts as a constant current source for the
output stage. Logic inversion is performed since
logIcal "1" input voltages cause current to be supplied to O 2 and to 0 3 , And when 0 3 turns on the
output voltage drops to the logical "0" level.
The reason for the PNP current source, O2 , is so
that the output stage can be driven from a high
impedance. This allows voltage V2 to be adjusted
in accordance with the application. Negative voltages to -25V can be applied to V 2' Since the output will neither source nor sink large amounts of
current, the output voltage range is almost exclusively dependent upon the values selected for V2
and V3 .
Maximum leakage current through the output transistor 0 3 is specified at 10 J1A under worst-case
voltage between V2 and V3. This will result in a
logical "1" output voltage which is 0.2V below V3.
Likewise the clamping action of diodes D4 , Ds, and
D6, prevents the logical "0" output voltage from
falling lower than 2V above V2, thus establishing
the output voltage swing at typically 2 volts less
than the voltage separation between V 2 and V3'
selecting power supply voltage
The graph shows the boundary conditions which
must be used for proper operation of the unit. The
range of operation for power supply V 2 is shown
on the X axis_ It must be between -25V and -8V.
The allowable range for power supply V3 is governed by supply V2. With a value chosen for V2, V3
may be selected as any value along a vertical line
passing through .the V2 value and terminated by
the boundaries of the operating region. A voltage
difference between power supplies of at least 5V
should be maintained for adequate signal swing.
switching time waveforms
INPUT
OUTPUT---t-'"\
~
1_
10V
----+--~-,-'--~
2-12
cc
Level Translators/Buffers
3:3:
-..J-..J
........
COCO
.... 0
............
cc
DM7810/DM8810 quad 2-input TTL-MOS interface gate
DM78111DM8811 quad 2-input TTL-MOS interface gate
DM7812/DM8812 TTL-MOS hex inverter
3:3:
COCO
COCO
.... 0
........
c
3:
general description
These Series 54/74 compatible gates are high output voltage versions of the DM5401/DM7401
(SN 5401 /SN 740 1), DM5403/DM7403
(SN 5403/SN 7403), and DM5405/DM7405
(SN5405/SN7405). Their open-collector outputs
may be "pulled-up" to +14 volts in the logical "1"
state thus providing guaranteed mteFface between
TTL and MOS logic levels.
In addition the devices may be used In applications
where it IS deSIrable to drive low current relays or
lamps that require up to 14 volts.
-..J
....NCO
......
c
3:
CO
CO
....
N
schematic and connection diagrams
r------.------Ovoc
4K
~--_.--------ov"
16K
OUTPUT
INPUT
INPUTS
OUTPUT
0-:,-+-......
,.
L-----_---o
L - -.....-oGND
DM7810/DM8810, DM7811/DM8811
DM7812/DM8812
Dual·ln-Llne Package
Dual-I n-Line and Flat Package
GND
TOPVIEW
GND
TOP VIEW
DM7811/DM8811
DM7810/DM8810
Dual-In-Line and Flat Package
14
"
"
11
10
TOP VIEW
ORDER
NUMBER
PKG
SEE
ORDER
NUMBER
PKG
SEE
DM7810J
DM7811J
DM7812J
16
16
16
DM7810N
DM7811N
DM7812N
24
22
22
DM881OJ
DM881 tJ
DM8812J
16
16
16
DM8810N
DM8811N
DM8812N
22
22
22
ORDER
NUMBER
PKG
SEE
DM7811W
DM7812W
27
27
DM8811W
DM8812W
27
27
GND
DM7812/DM8812
2-13
·N
.... ....
0
CO
CO CO
Q .......
....... N
0
.... ....
CO
....
.... :E
Q
7V
5.5V
14V
-65°e to +150oe
3000 e
Vee
Input Voltage
Output Voltage
CO
:E
operating conditions
absolute maximum ratings
co :E
:E Q
Storage Temperature Range
Lead Temperature (Soldering, 10 second,)
Q
Supply Voltage (Vee)
DM78XX
DM88XX
Temperature (TA)
DM78XX
DM88XX
MIN
MAX
UNITS
4.75
4.75
5.25
5.25
V
V
-55
0
+125
+70
°e
°e
....
....
CO
CO
electrical characteristics
:E
(Note 1)
Q
.......
....
....
PARAMETER
fJZ
Input Diode Clamp Voltage
Vee = 5.0V, T A = 25°C
liN = -12 mA
Logical "1" Input Voltage
Vee = Min
Logical "0" Input Voltage
Vee = Min
Logical "1" Output Current
Vee = Min
V OUT = 10V
Logical "1" Output Sreakdown
Voltage
Vee = Min, V 1N = OV
lOUT = 1 mA
Logical "0" Output Voltage
Vee = Min, V 1N = 2.0V
IOUT= 16 rnA
Logical "1" I nput Current
Vee = Max, VU'J = 2.4V
40
Logical "1" Input Current
Vee = Max, V 1N = 5.5V
1
rnA
Logical "0" Input Current
Vee = Max, V ,N = 0.4V
-1.6
rnA
Supply Current - Logical "0"
(Each Gate)
Supply Current - Logical "1"
(Each Gate)
Propagation Delay Tirne to a
Logical "0", tpdQ
Vee = Max, V ,N = 5.0V
3.0
5.1
rnA
Vee = Max, V ,N = OV
1.0
1.8
rnA
Vee = 5.0V, T A = 25°C
COUT = 15 pF, RL = lk
4
12
18
ns
Propagation Delay Time to a
Logical "1", tpdt
Vee = 5.0V, T A = 25°C
COUT = 15 pF, RL = lk
18
29
45
ns
CONDITIONS
:E
MIN
TYP
MAX
-1.5
UNITS
V
Q
2.0
V
0.8
V ,N = 0.8V
V ,N = O.OV
250
40
V
/-LA
/-LA
14
V
0.4
V
/-LA
Note 1: Unless otherwise specified minImax limits apply across the _55°C to +12SoC temperature range for the DM78XX and
across the ooe to 700 e range for the DM88XX. All tYPical, are given for Vee = 5.0V and T A = 25°e.
typical applications
+10V
JK
I.
UK
I
GAOUND
yo--+--I'·PU'
OM1810, OMJ811, DMfJ812
Note. Normal voltages applied to MOS shltt
regIsters have been shifted by +10V for thiS
.pphcatlOn.
2-14
Yo--....--I1INPUT
L
CLOCK
+IDV---,
1
I
~
L-.-6V
OMlIIO, DMUl1, DMlln:
NSC MOS shih register
(Example MM506)
WI
!.
I
IL-_.,-vr'_.....
-1!V
NSC MOS ROM
(Example MM521)
00
s:s:
....,....,
--
ac test circuit and switching time waveforms
coco
~
~O
0 ........
s:O
+5V
(
R,
0-
~
~<~
r
INPUT
~
I
,~1.5V--1
I
I
I
I
I
I
COCO
_CO
. 0
'
o
I
s:
"~'l\Jr
:
COUT
coS:
I
I
I
I
I
tpdo _ _1
I
-s:
~
---50"~--- i
'
I
I
I
i~1
I~tpdl
I
I
I
i ')
I
........
o
f=1 MHz
-
t, '" t f = to ns
PW= 180ns
CO
CO
i ')
2-15
.......
N
co
co
:!
Level Translators/Buffers
c
DM88L12 TTL-MOS hex inverter/interface gate
general description
The DM88L 12 is a low power TTL to MOS hex
inverter element. The outputs may be "pulled up"
to +14V in the logical "1" state. thus providing
guaranteed Interface between TTL and MOS logic
levels. The gate may also be operated With Vcc
schematic and connection diagrams
.,
20'
le.els up to +14V Without resistive pull·ups at the
outputs and still providing a gua~anteed logical "1"
level of Vcc - 2.2V with an output current of
-200/lA.
Dual-In-Line and Flat Package
500
GNO
TOPVIEW
Order Number DM88L 12F
See Package 4
Order Number DM88L 12J
See Package 16
Note S"own
IS sehem~K:
Order Number DM88L 12N
See Package 22
fOI each mveltel
typical applications
TTL I nterface to MOS ROM
TTL Interface to MOS ROM
Without Resistive Pull-Up
With Resistive Pull-Up
NATIONAL MDS RDM
CEXAMPLEMM521)
switching time waveforms
ac test circuits
Vcc '140V
~
Voc' 511
1T. .,
',,'
2·16
••
--'"
~
1-- 1JV --1
"00.
IIliPUT
r"'"'
FORV cc '1411
FOR lice =50V
Figure 1
Figure 2
,
,
I
I
OUTPUTi\ir'
:
,
:
'
:
I---~~---:
I
I
"
I~~~:
:--1,..,
t, .t,~ IOn.
pw'10n",
c
absolute maximum ratings
Supply Voltage
Input Voltage
Output Voltage.
Storage Temperature Range
Lead Temperature (Solderong, 10 sec)
(Note 1)
'.
15V
5.5V
15V
~5°e to +15o"e
300°C
electrical characteristics
3:
operating ccnditions
Supply Voltage
DM78L12
DM88L12
00
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
-55
0
125
70
°e
°c
MAX
UNITS
Temperature
DM78L12
DM88L12
CONDIT~ONS
Logical "1" Input Voltage
Vec = 14.0V
Vee = Min
Logical "0" Input Voltage
Vec = 14.0V
Vee:: Min
TYP
MIN
V
V
1.3
1.3
2.0
2.0
13
1.3
07
0.7
V
V
V
12.0
15.0
118
145
Vec = 1.1V
V
V
Vec= 140V VIN = 0.7V
V IN =0.7V
Vee = Min
Vee =Min
VIN '* OV
lOUT = -200 IJA
lOUT = +200 IJA
lOUT = -5.0IJA
Logical "0" Output Voltage
Vec = 14.0V VIN = 2.0V
VIN = 2.0V
Vee = Min
IOUT= 12 mA
lOUT = 3.6 mA
Logical "1" Input Current
Vcc= 140V VIN = 2.4V
\lIN = 2.4V
Vee = Max
<1
<1
20
10
IJA
IJA
Vee = 14.0V VIN = 5.5V
VIN = 5.5V
Vee = Max
<1
<1
100
100
IJA
IJA
Logical "0" Input Current
Vee = 14.0V VIN = O.4V
V IN =O.4V
Vee= Max
-320
-100
-500
-180
IJA
IJA
Output Short CirCUit Current (Note 3)
Vee = 14.0V VOUT= OV
Vee = Max
VOUT= OV
-25
-50
-15
mA
mA
Supply Current - Logical ''I''
(Each Inverter)
V ee = 14.0V VIN = OV
Vee = Max
VIN = OV
0.32
0.11
050
0.16
rnA
mA
Vee = 14.0V VIN = 5.25V
VIN = 5.25V
Vee = Max
10
0.3
15
0.5
mA
mA
Logic,I"O"
0.5
0.2
-10
-3
-8
1.0
0.4
V
V
PropagatIon Delay to a Logical "0"
from I nput to Output, t"dO
Vee = 5.OV
TA = 25°C
See Figure 2
27
45
ns
Propagation Delay to a logical "0"
from I nput to Output, t".o
Vee = 14.0V
See Figure 1
TA = 25°C
11
20
ns
Propagation Delay to a Logical "1"
Vec = 5.0V
TA = 25°C
See Figure 2
79
100
ns
Vec = 14.0V
See Figure 1
TA = 25°C
34
55
ns
from Input to Output,
t"d1
(Note 4)
Propagation Delay to a Logical "1"
from Input to Output, tpd1
I')
(Note 2)
PARAMETER
Logical "1" Output Voltage
,..00...
Note 1: "Absolute Maximum Ratmgs" are those values beyond which the safety of the device cannot
be guaranteed. Except for "Operating Temperature Range" they are not meant to Imply that the
deviceS should be operated at these limits. The table of "Electrieal Characteristics" prOVides conditions
for actual device operation.
Note 2: Unless otherwiSe spacified minimax limits apply across the -55°e to +125·e temperature
range for the DM78L12 and across the o"e to +70·e range for the DM88L12. All typical. are
given for Vee = 5.0V and TA = 25"e, or for Vee = 14.0V and TA = 25"e.
Note 3: Only one output at a time should be shorted.
Note 4: t pdl for Vee = 5.0V IS dependent upon the reslstanes and capacitanes used.
2-17_
...
en
co
co
Level Translators/Buffers
::2
Q
.......
...
en
co
.....
::2
Q
OM7819/0M8819 quad 2-input TTL-MOS AN 0 gate
general description
The DM7819 is the high output voltage version of
the SN5409. Its open-collector outputs may be
"pulled-up" to +14 volts in the logical "1" state
thus providing guaranteed interface between TTL
and MOS logic levels.
schematic and connection diagrams
4K
2K
UK
lK
~Dual·1 n-Line
and Flat Package
Order Number DM7S19J or DM8819J
See Package 16
Order Number DM7S19N or DMBB19N
See Package 22
Order Number DM7819W or DM8819W
See Package 27
TOP VIEW
2·18
0
absolute maximum ratings
i:
.....
operating conditions
(Note 1)
00
....
CD
MIN
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
7.0V
5.5V
5.5V
-65°C to +125°C
300°C
electrical characteristics
Temperature (T A)
DM7819
DM8819
CONDITIONS
Logical "0" Input Voltage
Vee
= Min
Logical "1" Output Current
Vee
Vee
= Min, V ,N = 2 OV, V OUT = 10V
= Min, V,N = 4.5V, V OUT = 14V
Logical "0" Output Voltage
Vee
= Min, VIN = O.SV,
Logical
"a"
Input Current
Logical "0"
Input Clamp Voltage
5.5
5.25
V
V
-55
0
+125
70
°c
°c
TYP
MAX
20
=
Supply Current - Logical "1"
4.5
4.75
MIN
Vee
Logical "'" Input Current
UNITS
Min
....
CD
V
V
40.0
1.0
iJ.A
mA
04
V
V ,N = 2.4V
Max,
V ,N = 5.5V
40.0
10
iJ.A
mA
Vee = Max,
V ,N = O.4V
-1.6
mA
Vee = Max,
Vee = Max,
V ,N = 5V
V ,N = OV
21.0
33.0
mA
mA
-1.5
V
Vee =
lOUT
= 16 rnA
110
200
Vee = 5.0V, T A = 25°C, liN = -12 mA
Propagation Delay to a Logical "0" tpdO
DM7819
DM8819
Propagation Delay to a Logical "1" tpd1
DM7819
DM8819
Vee = 5.0V
T A = 25°C
16.0
24.0
ns
Vee = 5.0V
TA = 25°C
16.0
32.0
ns
Note 1: "Absolute Maximum Ratmgs" are those values beyond which the safety of the device cannot be guaranteed Except
for "Operatmg Temperature Range" they are not meant to Imply that the devices should be operated at these limits The table
of "Electrical Characteristics" provides conditIOns for actual device operatloon
0
Note 2: Unless otherwise specified min/max limits apply across the -55 C to +125 C temperature range for the OM7819
and across the O°C to 70°C range for the OM8819 All typlcals are given for Vee == 5 OV and T A = 2Soe
ac test circuit and switching time waveforms
~~
r---J~5V
--1
INPUT
"\
l
,~" I~---
J'--·. .
t".
'0%
OUTPUT-------'
f~1
0
00
00
UNITS
08
"-
i:
(Note 2)
PARAMETER
Logical "1"lnput Voltage
Supply Voltage (VCC)
DM7819
DM8819
MAX
MHz
1, ~q ~
10"1
PW=IOlln$
2·19
Memory/Clock Drivers
DH3467C quad PNP core driver
general description
typical characteristics
The DH3467C consists of four 2N3467 type PNP
transistors mounted in a 14-pm molded dual-m-line
package. The device is primarily intended for core
memory application requiring operating currents
in the ampere range, high stand-off voltage, and
fast turn-on and turn-off times.
Turn-ON Time
18 ns
Turn-OFF Time
45 ns
connection diagram
1A
Collector Current
Collector-Base Breakdown Voltage
120V typo
Collector Saturation Vbltage
at Ie = 1A
Collector Saturation Voltage
at Ie = O.5A
O.55V
O.31V
Dual-I n-Line Package
Order Number DH3467CD
See Package 1
Order Number DH3467CN
See Package 22
NC
TOP VIEW
-JOV
-3DV
,gn
,gn
SCOPE
SCOPE
200.11
2011n
lNDI6
PW=200ns
RISETlME.,;;Zns
t3-tj,
1&2<
_
-
I---+---'WY-I
"':"
IC '" 500 mA, ISl '" 50 mA, IS2 '" -50 mA
3-3
absolute maximum ratings
Collector to Base Voltage
Collector to Emitter Voltage
Collector to Emitter Voltage (Note 1)
Emitter to Base Voltage
Collector Current - Continuous
Power Dissipation (T A = 25°C)
Power Dissipation (T e = 25°C)
Operating Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec.)
SOV
SOV
50V
6V
1.0A
0.6W
1.5W
150°C Max
O°C to +SSoC
_65°C to +150°C
300°C
electrical characteristics- Each transistor (T A
PARAMETER
~.
= i5°C, unless otherwise specified)
CONDITI9.i\lS
--_...-
MIN
LIMITS
TYP
UNITS
Ie = 10 mA, Is = 0
50
V
Collector to Em itter
Breakdown Voltage (BV eEs )
Ie = 101lA, VSE =0
SO
V
Collector to Base
Breakdown Voltage (BV eso )
le= lO IlA,I E =O
SO
V
Em itter to Base
Breakdown Voltage (BV ESO )
le=O,I E = lO IlA
Collector Saturation
Voltage (VeE I Sat) ) (Note 2)
le= lA, Is = 100mA
Ie = 0.5A, Is = 50 mA
Ie = O.lA, Is = 10 mA
DC Pulse Current Gain (h FE ) (Note 2)
le=lA,VeE =5V
Ie = 0.5A, VeE = lV
Ie = O.lA, VeE = lV
Base Saturation
Voltage (VSE (Sat) (Note 2)
le= lA, Is = 100mA
Ie = 0.5A, Is = 50 mA
Ie = O.lA, Is = 10 mA
Collector Cutoff Current (leso)
IE = 0, Ves = 60V
Turn-ON Time
6.0
V
0.55
0.31
0.19
25
35
60
65
45
90
1.10
0.95
0.75
0.33
0.95
0.52
0.26
V
V
V
150
1.70
1.20
0.S6
V
V
V
1.70
IlA
Ie = 0.5A, ISl = 50 mA
(See test circuit)
lS
30
ns
Turn-OFF Time
Ie = 0.5A, ISl = 50 mA
IS2 = 50 mA
(See test circuit)
45
60
ns
High Frequency Current Gain
f = 100 MHz, Ie = 50 mA,
VeE = 10V
Common Base, Open Circuit, Output
Capacitance
IE = 0, Vee = 10V
10
pF
Common Base, Open Circuit, Input
Capacitance
Ie = 0, VSE = 0.5V
55
pF
2.5
4.5
4.S
40
Not. 1: Ratings refer to., a high-current POint where collector-ta-emltter voltage is lowest.
Not. 2: Pulse conditions. Length = 300 JJS, duty cycle = 1%.
3-4
MAX
Collector to Emitter
Sustaining Voltage (V eEo (sust)
Memory/Clock Drivers
LM75324 memory driver with decode inputs
general description
The LM75324 IS a monolithic memory driver
which features two 400 mA (source/sink I sWitch
pairs along with decoding capability from four
address lines. Inputs Band e function as mode
selection lines (source or slnkl while lines A and
D are used for sWltch·palr selection (output pair
VIZ or W/XI
•
features
•
Output capability
400 mA
High voltage outputs
•
Dual sink/source outputs
•
Internal decoding and timing circuitry
•
Fast sWitching times
•
Operation
oOe
•
DTLlTTL compatible
o.
Input clamping diodes
to +70o e
schematic and connection diagrams
r--1~~----------~~~--------------~----------~'~
....---------+-0 ~~::~TW
TIMING
INPUTS
DOTPUTX
~~~~:::-'_t-_~_-...:::;:==:t+=::;(SDURC£1
SOURCE
•
COLLECTORS
I'
MODESEHCT
ADDRESS
(SOC~Nc"~r-1_1~~=~
INPUTS
$WITCH PAIR
SEHCL. Do-...,.-t--t-J
v-------....-= ~~~~TZ
O';al-In-Line Package (J)
OUT'UT
GND
Z
l
(SINK)
OUTPUT SOUACEOUTPUT
Y
lice
COLLEt
Dual-I n-Line Package (N)
OUTPUT
X
W
(SDURCEI TORS (SOURtE) (SINKl
OUTPUT
GNo
t
OUTPUT
SOURCE
V
COLLEt
X
W
(SOURCE)
TORS
(SOl/ReF)
ISINKI
Z
ISINK)
Vcc
OUTPUT
OUTPUT
ADDRESS
IliPUTO
ADORESSltI--o+13V
TI033
}-...+-___-<: .,v
FIGURE 3. ICC (All Outputs Off)
3·8
test circuits and switching time waveforms (con't)
+35V
¢
_---------------,
I TIMING INPUTS
I
I
f------O
vco
~
+14V
I
I
I
Note 1 GNO A and B. apply +3 5V to C and D,
and measure Icc (output W IS on)
}-....-----o.'v
+35V
Nota2 GNOBandO,apply+35VtoAandC,
and measure Icc (output Z IS onl
Note3 GNDAandC,apply+J5VtoBandO,
and measure Icc (outputXISOO)
Note4 GNDCandO.apply+J5VtoAandB,
SEE
NOTES
and measure Icc (output Y IS on)
FIGUFl'E"II. ICC (One Output On)
+5V
rTiMiNiii'NPUi-S----------,
I
vcc
9f------O+
14V
I
I
I
'--I*"_0+13V
TlD33
Note 1 The mput waveform IS supphed by a
generator With the followmg charactenstlcs
t, "If" 10 liS, duty cycle S 1%, and ZOUT "'" SOn
Note 2 When measunng delay times at output X,
apply +5V to Input 0, and GNO A. When measunng
.,v
)-+~~--<......-o
OUTPUT X
delay times at output Y, apply +5V to mput A,
and GNO 0
Note 3 CL Includes probe and Jig capacitance
SEE
NOTE
,
Note 4 Unless otherWIse noted all resistors are 0 5W
L.-t-'-U>-1f-....- ....-OOUTPUT y
f - - - - '00 .. - - - - 1
.'v----+-I------_"
INPUT
II
90%
\
10%
_ ---I-'}OUTPUT
XOR V
'
-
~'.~
~
FIGURE 5. Source-Output SWitching Times
3·9
test circuits and switching time waveforms (con't)
+5V
ITiMiNGiNPliTs-----------,
V"9f------O
I
I
I
+14V
R,
53U
OW
(NON INDUCTIVE)
r~"}--""""-'\JVY-"";'O+23V
L-.I---o+13V
TID33
Note 1 The Input waveform IS supplied by a
generatofWlththefollowmgcharacterlSucs.
t, = If '" 10 ns, duty cycle:;; 1%, lOUT"" SOn.
Note 2 When measunng delay times at output
.,v
......-+T~MH-----o .,v
SEE
Note 3 CL Includes probe and Jig capacitance
NQTE
2
} -....-----oOUTPUT
'5V
----+---cr-------,.
INPut
ov
OUTPUT - - - - - - , .
FIGURE 6. Sink·Output Switching Time.
3·10
W, apply +5V to Input D, and GND A When
measuring delay times at output Z, apply +5V
to input A, and GND 0
~
3:
Memory/Clock Drivers
U1
U1
W
N
U1
......
~
3:
LM55325/LM75325 memory drivers
general description
The LM55325 and LM75325 are monolithic memory drivers which feature high current outputs as
well as Internal decoding of logic Inputs These CirCUits are designed for use with magnetic memOries
The CirCUit contains two 600 mA sink-switch
pails and two 600 mA source-switch pall s Inputs
A and B determine source selection while the
source strobe (S,) allows the selected source turn
on In the same manner, tnputs C and D determine
.....
U1
Sink selection while the sink strobe (S2) allows the
selected sink turn on
The LM55325 operates 0 ave I the }ull military
temperature range of -55 eta +125 C, while the
LM75325 operates from O°C to +70°C
Sink-output collectors feature an Internal pull-up
reSIStor In parallel with a clamping diode connected
to V CC2 This p,otects the outputs f,am voltage
surges associated with sWitching inductive loads
•
600 mA output capability
•
24V output capability
•
Dual sink and dual source outputs
The source stage features Node R which allows
extreme fleXibility In source CUrl ent selection by
controilingtheamount of base drive to each source
transistor ThiS method of setting the base d"ve
brings the power associated with the reslstol outSide the package thereby allOWing the CirCUit to
W
N
operate at higher source CUI rents fOI a given
lunctlon temperature If thiS method of source
current setting IS not desll ed, then Nodes Rand
R'NT can be shorted externally activating an
Internal reSistor connected from V CC2 to Node R
ThiS pi oVldes adequate base drive for source
currents up to 375 mA with V CC2 ~ 15V or
600 mA with V CC2 ~ 24V
U1
features
•
Fast sWitching times
•
Source base drive externally adjustable
•
I nput clamping diodes
•
DTLlTTL compatible
schematic and connection diagrams
Dual-In-Line Package
Order Number LM55325J or LM75325J
See Package 17
Order Number LM75325N
See Package 23
truth table
ADDRESS INPUTS
SOURCE
SINK
OUTPUTS
STROBE INPUTS
SOURCE SINK
SOURCE
A
B
C
0
51
S2
W
L
H
X
X
L
H
L
H
ON
OFF
OFF
OFF
OFF
OFF
H
X
X
X
X
L
H
H
X
X
H
L
H
L
X
X
X
X
H
H
H
H
H
H
X
X
L
L
x
SINK
y
OFF OFF
ON OFF
OFF ON
OFF OFF
OFF OFF
OFF OFF
Z
OFF
OFF
OFF
ON
OFF
OFF
H '" high level, L == low level, X == Irrelevant
NOTE
Not more than one output
IS
to be on at anyone time
3-11
It)
N
C")
It)
absolute maximum ratings
":e....
Supply Voltage V ee1
(Note 1)
Supply VolTdge V CC2
(Note 1)
7V
25V
55V
Input VO!\clgt' (Any Addle~~ 01 Strohe Input)
......
ContillUOLJ~
N
Opel riling Temper dlul e Rdnqe
Total DI~~lpallon at (at Belowl
170 C FtpeAII Tempf'lOUTPUT v
C,
25PF~
.r"-rr-----~H>ouTPUT
_ _ _ _ GNO
z
..J
."
Note 1 The pulse generator has the follOWing characteristiCS lOUT" 50n, duty cycle::; 1%.
Note 2 CL Includes probe and Jig capacitance
TEST TABLE
PARAMETER
OUTPUT UNDER TEST
Source collectors
tplH and tpHL
tpLH. tPHL.
tTLH, tTHL,
and t5
INPUT
CONNECT TO 5V
A and Sl
B. C. D and 52
Band 51
A.C. D and 52
Sink output Y
C and 52
A. B. D and 51
Sink output Z
o and
A. B. C and 51
52
FIGURE 9. Switching Times
+2011
350
OPEN
INPUT
VOL TAGE WAVEFORMS
::::1005
INPUT
200ns
(SEE
TEST
TABLE!
R,
1K
OUTPUT
""~O%
,,%
1/
10%
tTl'll
_ _ _ _GND
-I
Note 1 TIle pulse generator has the followrng charactenstlcs ZOUT
Note 2 CL mcludes probe and (Igcapacltance
=:
500, duty cvcle::; 1%
TEST TABLE
PARAMETER
OUTPUT UNDER TEST
INPUT
tTLH and tTHL
Source output W
Source output X
A and 51
B. C. D. and 52
Band 51
A. C. D. and 52
CONNECT TO 5V
FIGURE 10. Transition Times of Source Outputs
3·16
lOY.
tnM
r""
s::CIt
applications
CIt
W
N
CIt
External Resistor Calculation
A typical magnetic-memory word drive requirement
is shown In FIgure 11. A source-output transIstor
of one LM75325 delIvers load current (Id. The
sink-output transistor of another LM75325 sinks
this current.
After solVing for Rex,. the magnitude of the source
collector current (lcs) ·.IS determined from Equation 3.
......
(3)
The value of the external pull-up resIstor (Rex,)
for a particular memory application may be determined using the follOWing equatIon:
where:
CIt
W
N
CIt
16 [V CC2(mlnl - Vs - 2.21
Rext =
(1)
IL - 1.6JV CC2 (mlnl - Vs - 2.91
where:
Rext IS
In
The power dissipated In resIstor Rex' dUring the
load current pulse duration IS calculated uSing
Equation 2.
'
IL
:::::: (V CC2 (mln)
16
P Rex , IS
In
In
mAo
As an example. let V CC2 (mlnl = 20V and V L = 3V
while IL of 500 mA flows. Using Equatton 1:
16(20-3-2.2)
R
ext - 500 -:- i.6 (20 - 3 - 2.9)
= 0.5 kn
kn.
V CC2 (mlnl IS the lowest expected value of
V CC2 in volts. VS IS the source output voltage In volts with respect to ground. I L IS In
mAo
where:
Ics is
r""
s::
.....
-
(2)
Vs - 2]
mW.
500
PRext ""
16
[20 - 3 - 21 "" 470 mW
The amount of the memory system current source
(lcs) from Equation 3 IS:
Ics "" 0.94 (500) '" 470 mA
In thiS example the regulated source·output transIstor base current through the external pull-up
resistor (Rex,) and the source gate IS approximately
30 mAo ThiS current and Ics comprISe I L .
RUT
--,
~~~~~~TORS I
r-,---.
I
IL
lM~:;251
a..
~~~~J~:
A _ .JI
_
_____ _
1
~
-::-
r------+--,
I
IL
LM~:JE251
lM75325
SINK
_
____ _
Dissipation Derating Curve
1000
900
BOO
, 1
"l ]~~~'~VT
LM55325
I
_ _ .JI
Y OR Z
r-...
)00
600
500
400
300
200
H-
~-+__+--+__+--+~l~
DERATE
10,) mW/"C
100
J---:--f- FROM
)5"C-
o
)0
BO
90
100
110
120
130
TA - AMBIENT TEMPERATURE ( C)
GNa
Note 1 For clarity, partial l09lc dlagrlfIH of two lMli53Z6's It. shown
Mott2 Sour&eandslQkshoWPlt8lRdlfferlntpackages
FIGURE 11. Typical Application Data
FIGURE 12. Thermal Information
3-17
,...
(,)
o
o
o
Memory/Clock Drivers
::t
::?!
j::::
o
o
o
::t
::?!
MH0007/MH0007C dc coupled MOS clock driver
general description
features
The MH0007 is a voltage translator and power
booster designed for interfacing between conven·
tional TTL or DTL voltage levels and those levels
associated with inputs or clocks of MOS F ET type
devices. The design allows the user a wide latitude
in selection of supply voltages, and is especially
useful in normally "off" applications, since power
dissipation is typically only 5 milliwatts in the
"off" state.
• 30 volts (max) output swing
• Standard 5V power supply
• Peak currents in excess of ±300 mA available
• Compatible with all MOS devices
• High speed: 5 I\IIHz with nominal load
• External trimming possible for increased per·
formance
schematic and connection diagram
Vcr 9
R3
4K
10 V'
.,'00
.,
10 Pin TO-l00 Package
""
V'
INPUT 1
1
INPUT 2
GND 4
OUTPUT
INPUT
--~""-{'
TOP VIEW
.,
Order Number MH0007H
or MH0007CH
See Package 13
soon
....- - - -..._ _ _ _ , v·
typical applications
Switching Time Test Configuration
High Speed Operation
2K
INPUT
INPUT
INPUT
INPUT
>-....
)------~....-OUTPUT
--OUTPUT
ton == 30 ns} C "200 F
\'H==40 ns
3·18
L
P
s:
::t
absolute maximum ratings
electrical characteristics
o
o
o.....
8V
-40V
+28V
30V
5.5V
800mW
'500mA
-65"C to +'50"C
-55"C to +'25"C
O"C to +85"C
300"C
Vee Supply Voltage
V- Supply Voltage
V+ Supply Voltage
(V+ - V-I Voltage Differential
Input Voltage
Power Dissipation (T A ~ 25°C)
Peak Output Current
Storage Temperature Range
Operating Temperature Range MH0007
MH0007C
Lead Temperature (Soldering, '0 sec)
......
s:
::t
o
o
o.....
(')
(Note 1)
TYP
PARAMETER
CONDITIONS
MIN
Logical "," Input Voltage
Vee ~ 4.5V
Logical "0" Input Voltage
V ee ~ 4.5V
Logical"'" Input Current
Vee ~ 5.5V, V ,N ~ 5.5V
Logical "0" Input Current
Vee ~ 5.5V, V ,N ~ O.4V
Logical "'" Output Voltage
Vee ~ 5.5V, lOUT ~ 30 mA, V ,N ~ 0.8V
Vee ~ 5.5V, lOUT ~ , mA, V ,N ~ 0.8V
Logical "0" Output Voltage
(Note 2)
MAX
2.2
UNITS
V
0.8
'00
'.0
'.5
V+ - 4.0
V
/lA
mA
V
V+ - 2.0
V
Vee ~ 4.5V, lOUT ~ 30 mA, V ,N ~ 2.2V
V- + 2.0
V
Transition Time to
Logical "0" Output
C L ~ 200 pF (Note 3)
50
ns
Transition Time to
Logical "," Output
CL ~ 200 pF (Note 3)
75
ns
Note 1: Mm/max limits apply across the gU,aranteed range of _55°C to +125°C for the MHOOO7, and
from O°C to +85°C for the MH0007C, for all allowable values of V- and V+
Note 2: All tYPical values measured at T A
=
25°C with Vee'" 5 0 volts, V-
Note 3: TransitIon time measured from time V IN
fmal value.
=
=
-25 volts, v+
=
0 volts.
50% value until VOUT has reached 80% of
Allowable Val ues for V- and V +
Maximum Power Dissipation
V'
VOLTS
12
,.L
V""'7
I
1.0
~
~ 08
i=
~
i1i
06
'"
0.4
"'~
ckE
'f'
AM~'ENT
02
OPERATING
REGION
I
0
0
-"
~
I -.... .....
25
50
15
-
""
100
125
150
TEMPERATURE ("C)
3-19
M emo.ryI Clock 0 rivers
MH0009/MH0009C dc coupled two phase MOS clock driver
general description
features
The MH0009/MH0009C is high speed, DC coupled,
dual MOS clock driver designed to operate In
conjunction with high speed line drivers such as
the DM8830, DM7440, or DM7093. The transition
from TTLlDTL to MOS logic level IS accomplished
by PNP input transistors which also assure accurate
control of the output pulse width.
•
DC logically controlled operation
•
Output Swings - to 30V
•
Ouiput Currents -
•
l-ligl1 rep rate -
•
Low standby power
In
In
excess of ±500 mA
excess of 2 MHz
schematic and connection diagrams
12- Lead TO-S Package
¢,BIAS 3
oP,INPUT A
2 ¢,INPUT A
. - - 1 " ' - _ 1 2 9, OUTPUT
1fJ, INPUT 8 4 - - -.......-
v¢zINPUT8
--f
.......
5---.. . .
-~--t
.......-~-I1V·
6 ---+-~--[
v+ =+5.0V
'--1.-..... ,0
"
GNO 5
TOP VIEW
Order Number MH0012G
or MH0012CG
See Package 6
tNPUT2 3
COMP ..
""'
,
2
y-
typical application
(ac test circuit)
v-
3·22
~DV
timing diagram
s:
~
o
o
...a
absolute maximum ratings
v~ Supply Voltage
Maximum Output Load-See Figure 2
Differential (Pm lor 2 to
Pm
V+ Supply Voltage
5~
Power DISSipation-See Figure 1
Storage Temperature
Operatmg Temperature MHOO12
MHOD12C
Lead Temperdture (Soldering. 10 sec)
-40V
Differential (Pm 8 or 9
to Pm 1 or 2)
Input Current (Pm 3 or 7l
Peak Output Current
30V
±75 rnA
±lODO rnA
dc electrical characteristics
PARAMETER
15W
N
-65"C to +150°C
......
-55"C to +12SoC
O"C to +8S"C
s:
300°C
~
o
o...a
(Note 1)
CONDITIONS
MIN
Logic "1" Input Voltage
(Pms 7 and 3)
v+ - V-
Logic "0" Input Voltage
Wms 7 and 3)
V+-V-=20V,V OUT ?:'V+ -15V
LOfjlc "1" Output Voltage
Vf _ V- '" 20V, lOUT '" lmA,
TVP
MAX
UNITS
10
20
V
~ 20V, VOUT::;V- , 2V
04
06
V-
V
10
t
N
(')
V- + 20
V
VIN "'20V
Logic "0" Output Voltage
V' - V- '" 20V,
V 1N =04V
IDe (V- Supply)
V+-V-=20V,V 1N "'20V
lOUT'" -
v
lmA,
t _
15
V+ - 07
V
34
60
TVP
MAX
10
15
5
10
ns
35
50
ns
35
45
ns
mA
ac electrical characteristics
CONDITIONS (Note 3)
PARAMETER
MIN
Turn-On Delay (tON)
V· ~V-=20V.Vcc =50V
CL "200 pF. f =- 1 0 MHz
TA '= 25"C
Rise Time it,)
Turn-Off Delay (toFFI
Fall Time {til
UNITS
ns
Note 1: Characteristics apply for CirCUit of Figure 1. Min and max limits apply from -55°C to +125° C for the MH0012 and
from O°C to +85°C for the MH0012C. TYPical values are for TA = +25°C.
Note 2: Due to the very fast rise and fall times, and the high currents Involved, extremely short connections and good by
passing techniques are required.
Note 3:
All conditIOns apply for each parameter.
Maximum Output Load
Power Dissipation
Rise and Fall Times vs
load Capacitance
vs Voltage Swing vs Rise Times
40
1.5
~
"\
1.0
'"~
:£
"-I"\.
.5
C>
1.
>
;!
-;;
20
>,
"-
I--
i
1L
,\ \
30
~
C=~
10
~
~( •
. ."Q'to
"$
./Q
11r
~ 35
"
:; 30
~.
~"
~
IV· - V-I
-- ........
{-- 1'.... ..... ......
'" 25
:
-
I-V· - V- = 20V
..
20 I - TA
~
10
;;!
~
=25"C
~ 15
i=
"'
:-
5
-t-
-
:-
0
0
25
50
75
100
125
400
0
150 175
1200
800
1600
MAXIMUM OUTPUT LUAU (pfl
AM81ENT TEMPERATURE lOCI
Figure 1.
200
400
600
800
1000
LOAO CAPACITANCE, CL I.FI
Figure 2.
applications information
Power Dissipation ConSiderations
Where
The power diSSipated by the MHOOt2 may be
diVided mto three areas of operation"" ON, OFF
and swltchmg, The OFF power IS approximately
30 mW and IS diSSipated by R2 when Pin 3 IS In
the logiC "1" state The OFF power IS negllble and
will be Ignored In the subsequent diSCUSSion, The
ON power IS diSSipated primarily by 0 3 and Rg
and IS given by:
PON == I
"r iI IN
{V+ - v-f
+---1
R9
DC
111
DC'" Duty Cycle
==
ON Time
ON Time & OFF Time
VIN - V BE3
liN IS gIVen by - - R - , - - and equation (1)
becomes
PON
= [(VIN
-
~B,E3IIV-1
+
IV·R~ V-1 2 ]
For V tN = 2 5V, V SE3 = 0 7V. V+ "'OV. Vand DC = 20%, PON == 200 mW
The tranSient power mcurred dunng SWitching IS
given by'
PAC =- (v+ - y- 12 CLf
131
For V+ ;;: OV, V- == -20V, C L ;;: 200 pF, and
f '" 5.0 MHz, PAC "" 400 mW,
The total power is given by
DC 121
=
-20V,
PT "" PAC + PON
PT ::;:; PMAX
For the above example, P T = 600 mW.
141
3-23
Memory/Clock Drivers
MH0013/MH0013C two phase MOS clock driver
general description
features
The MH0013/MH0013C IS a general purpose clock
driver that IS deSigned to be driven by DTL or
TTL line drivers or buffers with high output cur·
rent capability. It will prOVide fixed width clock
pulses for both high threshold and low threshold
MOS devices. Two external Input coupling capa·
Cltors set the pu Ise width max Imum, below wh Ich
the output pulse width will closely follow the
Input pulse width or logiC control of output pulse
width may be obtained by uSing larger value input
• High Output Voltage Swings-up to 30V
• High Output Current Drive Capability-up to
500 mA
• High Repetition Rate-up to 5.0 MHz
• Pin Compatible with the MH0009/MH0009C
• "Zero" Quiescent Power
capacitors and no mput resistors.
schematic and connection diagrams
12·Lead TO·S Package
INPUT A,
02
. -. . . . . .- _ 1 2 OUTPUT A
INPUT A] 4
----+-_--r
DI
V'
5---_+-~-_+
11 V'
03
-Ir
INPUT 8, 6 - - -....-
INPUT 82
...
TOP VIEW
' -. . . . . .-
Order Number MH0013G or MH0013CG
.... 10 OUTPUT B
See Package 6
04
typical applications
+Vcc
c"
- - - --1
I
I
I
I
I
1/~D~8:!1~8~O_ _ _
J
c"
~~~~~
-OUTPUT
I
I
U..----
PUL~::-U
INPut
PUL
PULSE..
OUTPuX,
3·24
U
I
lJ
I
s:
::I:
absolute maximum ratings
0
0
...w
(V+ - V-) Voltage Differential
30V
±75mA
Input Current (Pin 2,4,6 or 8)
±600 mA
Peak Output Current
Power Dissipation (Figure 7)
1.5W
--65°Cto +150°C
Storage Temperature
_55°C to +125°C
Operating Temperature MH0013
DoC to +85°C
MHOO13C
300°C
Lead Temperature (Soldering, 10 sec 1/16" from Case)
........
s:
::I:
0
0
...w
(")
electrical characteristics
PARAMETER
(Note 1 and Figure 8)
MIN
CONDITIONS
LogIcal "0" Output Voltage
IOUT=-50mA IIN=lOmA
10uT =-10mA IIN=10mA
Logical "1" Output Voltage
lOUT = 50 rnA
Power Supply Leakage Current
(V' - V-I
Negative Input Voltage Clamp
liN =-lOmA
0;
lOUT = liN
v· - 3 a
v+ - 0
GIN
=
RIN '"
tfall (Note 2)
liN = 10 rnA
30V
=OmA
V" -
10
V- - 1 2
a 0022,uF
on
40
CL =OOOlJ.1F
tfall (Note 3)
Pulse Width (50% to 50%) (Note 3)
Pulse Width (50% to 50%) (Note 3)
7
V- + 1 5
td ON
td OFF (Note 2)
MAX
TV'
V
V
a5
V- + 20
V
V
100
JJA
V- - 0 8
V
20
35
35
50
30
60
50
80
40
70
120
340
420
490
GIN = 500 pF
15
RIN
=
20
CL
= 200 pF
On
UNITS
v+ - 1 0
n,
n,
n,
n,
n,
n,
n,
n,
n,
110
Positive Output Voltage Swmg
v" - 0
7V
V
Negative Output Voltage SWing
V- + 0 7V
V
Note 1: MiniMax limits apply over guaranteed operatIng temperature range of _55°C to +125°C for
MH0013 and O°C to '+85°C for MH0013C, wIth V- = -20V and V+ = OV unless o~herWlse specified,
TYPical values are for 25°C
Note 2: Parameter values apply for clock pulse WIdth determined by Input pulse WIdth.
Note 3: Parameter values apply for Input' pulse Width greater than output clock pulse width
TABLE I. Typical Drive Capability of One Half MH0013 at 70°C Ambient
FREQUENCY
MH,
PULSE WIDTH
TYPICAL RIN
"'
.'
2.
20
16
"
40
100
0
750
50
200
350
7
10
2.
20
16
20
200
10
1600
100
400
700
5
14
19
2.
20
16
10
200
0
2300
400
1000
1700
19
34
45
2.
20
16
05
500
10
4000
2800
5500
9300
130
183
24.
(V 3 - V2)
VOLTS
TYPICAL CIN
OUTPUT DRIve
CAPABILITY IN pFl
Rise TIME
LIMIT ns1
-
Note 1: Output load IS the maximum load that can be driven at 70°C without exceeding the package
rating under the given conditions.
Note 2: The rise time given is the minimum that can be used without exceeding the peak transient
output current for the full rated output load.
circuit operation
Input current forced into the base of 01 through
the coupling capacitor G'N causes 01 to be driven
into saturation, swinging the output to
V- + VeE (SAT) + VOIODEWhen the input current has decayed, or has been
switched, such that 01 turns off, 02 receives base
drive through R2, turning 02 on_ This supplies
current to the load and the output swings positive
to V+ - V EiE .
It may ·'tie noted that 01 always switches off
before 02, begins to supply current; hence, high
internal transient currents from V+ to V- cannot
occur.
3-25
CJ
...o
M
typical performance characteristics
o
FIGURE 2. Transient Power vs Rep.
Rate vs CL
FIGURE 1. Output Load vs Voltage
Swing
::J:
:E
I
"Mo...
tr
30
'"
10 ns
::J:
1\ :\." ~ I'....
:E
100
100
.! 600
~
.! 600
~
1\ \ ,\
"-\r\.
o
,,~
10
20 ns 30 ns 40 ns 50 ns 60 ns
1000
'"~
...f
400
in
300
1ll
~r--.....
"...'"'"
'"~
500
100
30
/
~
~,
20
2
10
IV.
/
40%
V ".,
~
".,
V I"'. V.
~ ;;-
. '50%
1 1 1
:!
~ 500
Ii
•
V
I
~
~pF
I
f.....-
;...--
w
~ 3000
w
";:!
I
2.0 3.0 4.0 5.0 6.0 1.0
r~
/
FOR TYPICAL APPLICATION
IOM183018830 DRIVER
=4300 pF
=1000 pf
CIN
CL
~ 2000
:3
OM8830 DRIVER
RIN
"on y
RIN = 10n
R1N :: 47n
25 45 65 85 105 125
KV
,/ /
/ ,/
P' . / .....
~ ~ ~ k' "'il. gon
~ 1000
'-
.,t.
R'N .20n,~
...
AMBIENT TEMPERATURE rCI
AVERAGE POWER ImWI
= 5V
Z
.J-t:I....I-- ~
-55 -35 -15 5
400
Vee
1
Illy
iii
~
300
/
~
,/
REPETITION RATE IMHz)
CIN = 2200 pF
Cl =100DpF -.........
%
300
200
J
1.0
TEST CIRCUIT IFIG. 81
£ 400
I"
I
.....r
FIGURE 5. Typical Clock Pulse VariatIons FIGURE 6. RIN vs CIN vs Pulse Width
vs Ambient Temperature
~
~
lIt ~
100
II /J" V
I J /'"''
II V /
REPETITION RATE IMHzI
600
30%
200
1 0 2.0 3.0 40 5.0 60 1.0
FIGURE 4. Average Internal Power vs
Output Swing vs Duty Cycle
20%
300
100
MAXIMUM OUTPUT LOAD I,FI
10%
in
::"
200
IV' - V-I· 20V
jAOGPF
400
z
1",,1
IOGOPfl
500
...f
1ll
3000
2000
FIGURE 3. Transient Power vs Rep.
Rate vs CL
~
~~
100
200
300
400
PULSE WIDTH Insl
FIGURE 7. Package Power Oerating
1.5
~
'"~
"'-
1.0
I"
f
"'-
.5
25
50
15
"
100
125
150 115
AMBIENT TEMPERATURE lOCI
ac test circuit
timing diagram
A Inpwtpulsewtdtb
> clock pulse
V
~
IN
Wli!th
5V
OV
Your
F"-=~-t----- Vl~ -16V
Figure 8
3·26
s:
:J:
pulse width
o
Maximum output pulse width is a function of the
Input driver characteristics and the coupling
capacitance and resistance. After being turned on,
the Input current must fall from ItS initial value
liN peak to below the input threshold current
I, N mi n ~ VB E /R I for the clock driver to turn
off. For example, referring to the test circuit of
Figure 8, the output pulse width, 50% to 50%, is
given by
+ ROC 'N In liN peak"" 400 ns.
liN min
For operation with the Input pulse shorter than
the above maximum pulse width, the output pulse
width will be directly determined by the input
pulse width.
PWOUT
=
Figure 4 gives various values of Internal power
versus au ptut voltage and duty cycle.
......
3 Input Power
:J:
fan-out calculation
The drive capability of the MHOOl3 is a function
of system requirements, I.e., speed, ambient temperature, voltage SWing, drive Circuitry, and stray
wIring capacity.
The following equations cover the necessary calculations to enable the fan-out to be calculated for
any system condition. Some tYPical fan·outs for
conditions are given in Table I.
TranSient Current
The maximum peak output current of the MHOOl3
IS given as 600 mAo Average transient current reqUired from the driver can be calculated from'
I
=
C L (V+ - V-)
TR
(I )
ThiS can give a maximum limit to the load.
Figure 1 shows maximum voltage sWing and
capaCitive load for various rise times
1. TranSient Output Power
The average transient power IP AC) diSSipated IS
equal to the energy needed to charge and discharge
the output capacitive load IC L ) multiplied by the
frequency of operation IF)
PAC = C L X (V+ - V-)2 X F
(2)
Figures 2 and 3 show transient power for two different values of (V+ - V-) versus output load and
frequency.
2. In ternal Power
"0" State
Negligible «3 mW)
o
o
....
w
(")
4 Package Power Dissipation
Total Average Power
+ td OFF + td ON + "2 (tfall + t nse )
TYPical maximum pulse width for various C, Nand
R'N values are given in Figure 6.
s:
The average Input power IS a function of the Input
current and duty cycle. Due to Input voltage
clamping, thiS power contribution IS small and can
therefore be neglected. At maximum duty cycle of
50%, at 25 c C, the average Input power IS less than
10 mW per phase for R,NC 'N controlled pulse
Widths For pulse Widths much shorter than
R,NC ,N , and maximum duty cycle of 50%, Input
power could be as high as 30 mW, Since I, N peak IS
maintained for the full duration of the pulse
Width
1
PW'N
o
....
w
=
TranSient Output Power +
Internal Power + Input
Power
Ty p i cal Example CalculatIOn for One Half
MH0013C
How many MM506 shift registers can be driven by
an MHOOl3C driver at 1 MHz uSing a clock pulse
Width of 400 ns, rISe time 30-50 ns and 16 volts
amplitude over the temperature range 0_70°Cl
Power Dissipation
From the graph of power dissipation versus temperature, Figure 7, It can be seen that an
MHOOl3C at 70°C can diSSipate IW Without a heat
Sink. therefore, each half can diSSipate 500 mW.
Transient Peak Current Limitation
From Figure 1 (equation I), it can be seen that
at 16V and 30 ns, the maximum load that can be
driven IS limited to 1140 pF.
Average I nternal Power
Figure 4 (equation 3) gives an average power of
102 mW at 16V 40% duty cycle.
Input power Will be a maximum of 8 mW
Transient Output Power
For one half of the MHOOl3C
500 mW = 102 mW + 8 mW
+ tranSient output power
390 mW = transient output power
USing Figure 2 (equation 2) at 16V, 1 MHz and
390 mW, each half of the MHOOl3C can drive a
1520 pF load. ThiS IS, however, In excess of the
load derived from the transient current limitatIOn
(Figure I, equatlo'n 1), and so a maximum load
of 1140 pF would prevail.
From the data sheet for the MM506, the average
clock pulse load IS 80 pF. Therefore the number
1140
.
of devlces,Arlven IS
or 14 registers.
---ail
"/" State
(3)
For nonsymmetrlcal clock Widths, drive capability
IS Improved.
3-27
Memory/Clock Drivers
MH0025/MH0025C two phase MOS clock driver
general description
features
The MH0025/MH0025C IS monolithic, low cost,
two phase MOS clock driver that IS designed to be
driven by TTUDTL line drivers or buffers such as
the DM932, DM8830, or DM7440. Two Input
coupll ng capacitors are used to perform the level
shift from TTUDTL to MOS logic levels. Optimum
performance In turn-off delay and fall time are
obtained when the output pulse IS logically controlled by the Input. However, output pulse widths
may be set by selection of the Input capacitors
eliminating the need for tight Input pulse control.
• 8·lead TO·5 or 8·lead dual·ln·line package
• High Output Voltage SWlngs~up to 30V
• High Output Current Drive
1.5A
Capablllty~up
to
• Rep. Rate: 1.0 MHz into> 1000 pF
• Driven by DM932, DM8830, DM7440(SN7440i
• "Zero" QUiescent Power
connection diagrams
Metal Can Package
Dual-I n-Llne Package
V·
N.C
8 N.C.
1
INPUT A 2
V'
V'
1 OUTPUT A
J
6
INPUT B 4
v'
5 OUTPUT 8
Note: Pm 4 connected to case.
TOP VIEW
TOP VIEW
Order Number MH0025H or MH0025CH
See Package 11
Order Number MH0025CN
See Package 20
typical application
ac test circuit
Inplltwaveform
PRR=O.5MHz
Vp-p" 5.0V
1,"'tl5:10ns
timing diagram
A Inpulpulsewldth
VOUT 1
>clllckpuise
B Inputpullrewldth
B 200n8
V'~ov
:;t~OCkPuISil
Cloc~pulse
output
VOUT 2
5V
IN
Width
Pulse width
A 1 O~s
V
~
•
OV
~90% u----V~,.-::rl-ldON ~\'---_ _ _ _
._.
IdON
10%
!j1J%
r-~OfF
5V
OV
V3 -DV
10%
50%
VOUT
*Ul,sselected high speed NPNsWitchmgtranslstor
~=-""':~'-j----- V2 '-15V
3-28
~
:x:
o
o
absolute maximum ratings
(v+ - v
) Voltage Differential
N
30V
100mA
1.5A
See Curves
-65°C to +150°C
_55°C to +125°C
O°C to +85°C
300°C
Input Current
Peak Output Current
Power Dissipation
Storage Temperature
Operating Temperature MH0025
MH0025C
Lead Temperature (Soldering, 10 sec)
electrical characteristics
PARAMETER
CJ'I
"~
:x:
o
o
N
CJ'I
n
(Note 1) See test circuit.
CONDITIONS
TYP
MIN
T doN
T r,se
C 'N = .001 !IF
Td oFF (Note 2)
R'N =
>-
T fall (Note 2)
P.w. (50% to 50%) (Note 3)
UNITS
15
30
ns
25
50
ns
30
60
ns
60
90
120
ns
100
150
250
ns
V+ - 1.0
V+ - 0.7V
on
C L = .001 !IF
T fall (Note 3)
500
-'
Positive Output Voltage Swing
MAX
= OV, lOUT = -1 mA
V ,N
V
V- + 1.5V
V-+ 0.7V
= 10 mA, IOUT= 1 mA
Negative Output Voltage Swing liN
ns
V
Note 1. MinIMax limits apply across the guaranteed operating temperature range of _55°C to +12SoC
for MH0025 and O'C to 85'C for MH0025C. TYPical values are for +2S'C.
Note 2. Parameter values apply for clock pulse width determined by Input pulse width.
Note 3. Parameter values apply for Input pulse width greater than output clock pulse width.
typical performance
Transient Power vs Rep. Rate
Package Power Derating
~
~
~
1.4 1.2
~
1.0
f
0.6
ill'"
!!i
"x
~
400
_.- MH0025H &MH0025CH STILL AIR
0.8
MH0025CN SOLDERED INTO PC
.s
2 OZ..01 IN. WIDE
I'-
-
1',
::''"i
:'\
25
50
'"
75 100 125 150
~
0
TEMPERATURE rCI
V
5
15
10
2400
~ 2000
'"~
1600
5
1200
C>
g
800
400
0
\i\.
~
.{
l",
f
40
"C>
20
/
IV+ -
V-)2f
MHlm5CN
MHO(IZ5C
/
/'
Vv'-)=I~V-
L'l
iR
10
20
10
40
50
60
70 85
(V' - y-j' (OCI
Poe = - - , , - -
CL
Output P.W. Controlled by CIN
DUTf'UTPUlSE WIDTH VS C,,, FOR tONG
v _v-· 20V lA
'2~
v-v
- 25 C
~
r--..
r-... i"'
..... i'....
/
DUTY CYCLE (%1
1100
r--.
MHIO!5C~V'_V-.'BVTA'IlI:?(
ZOV
l~
IN'UT,ULSES
FORINPut'UlSE <&5+ AGC, .. In
£
900
:!
:z:
'"
t-...
i'" I-...:
F""' I""'"
~
~
700
Jill
~RIV~R
500
~
ff-
r-+--
1/
. . . .:1...
DRIVER
I>
;.or
V
L.--
100
1 'f",'OO
~
1M,,.
OUTPUT PULSE WIDTH" INPUT PULSE WIDTH
PLUSH",
CO
iii
58!1'UllUP
I I I
MtllIOl.C V-·Y-·16V lA' 10 C
0.2 0.4 0.6 0.8 10 12 14 1.6 1.8 2.0
200
600
FREnUENCY (MH,I
C~
/
/
0
20
I
1200
ri
60
is
I
PULSE REPETITION RATE (MHz)
DC·M'.
1\ '<,
80
ill'"
V+-V-"'16V
Maximum Load Capacitance
2800
C>
;:: 100
iZ
V ~?b
X
/
120
:
~ V I,,:::: ~ PC: ~2Gllpf
:;.. (P'"
PAC"
~
Iz
CL ·J5()pF
~ 100
"-
0.2
200
140
Cl -150pF
XI
v' - V-=20V/
CL-IOOOpf
I I lL / ~7
I // V
'£ r/ . /
&"
V V
ill
~
0
100
DC Power (PDC) vs Duty Cycle
160
CL '151l0pF
/1 J
ill'"
f
0.4
0
-25
~
BOARD WITH 8 Cu CONDUCTORS
CL-2001l~1
(PMAXI Uk) - (V+ - V-)2 (DC) -5: (lPk) (t,)
L ~
(f)(lk},(V+ _ V-)2
v+ _V-
IMAX
IMIN
"
~
1000 1400 1800 2200
CIN (pF)
Peak turrent delivered by driver
VilE
06
R'1= 1k
3-29
(.)
Ln
N
applications information
o
o
:I:
Circuit Operation
:E
......
Input current forced Into the base of 0, through the
coupling capacitor CIN causes 0 1 to be driven into
saturation, sWinging the output to V- + Vce(sat) +
Ln
N
o
o
VOIOde'
:I:
When the input current has decayed, or has been
sWitched, such that 0 1 turns off, O2 receives base
drive through R2, turning O2 on. This supplies
current t9 the load and the output swings positive
to V+ - VSE'
:E
It may be. noted that 0 1 must switch off before
O2 begins to supply current, hence high internal
transients currents form V- to V+ cannot occur.
. - -......-<> ,
J
Ci__
....
i"J
L--~'--""'---O'.
f~i
i',~.,
INPUT
---'10""'"+--....
,. Y '''"..
0-......
~RNf : ~VMHZ
~;~.
':'
II
which IS voltage
switching time
waveforms
INPUT
I
I.
1
Y>---f--ll
1
I
I
~~'~
V·~-200V
3-32
"a" to logic "1
r-
OUTPUT
-=10%
/
,-____'\'v
111%
1'=:""---
s:
::t
typical performance characteristics
TO·S & DIP Power Ratings
MH0026CN SOLDfRED TO PC
BOARD WITH B CU CONDUCTORS
202 OJIN WIDE
_
MH0026G AND MH0026CG IN
~
ill~
08
~
04
20
illQ
15
'"
3;!
10
50
75
100
125
r-....
MH0026G AND
05
25
320
280
"'i'... /
...........
~
02
360
r-- - ~~'~i ~~RK~~THHE~~:-~lNOY
I-- f"YPE 215-1 9 OR EQUIV)
25
:5
::>=
06
Q
'"
400
30
10
~
DC Power (PDC) vs
Duty Cycle
TOMS Package Power Rating
12
"",>
~
1<
.5
240
'"
200
~
150
25
50
75
100
125
Frequency
800
1<
.5
700
'"3;!
600
~
I-
iil
el
500
400
11/
~ 300
~
200
100
/
,I,
V
J J
,/
Cl 200 pF........
I-
rlI I
I I I
~i--"I1.0
20
30
l'
i
500pF
:::
VI
/
' IV' - V-I'
'oc "~IDC)
20
~
~
75
r-
7,0
40
50
4'
.5
12
I-
10
iil
--
"
/
~
r-
50
-75 -50 -25
0
25
50
7L
/
2'
..:-~
05
75 100 125
10
20
1.5
25
INPUT VOLTAGE (V)
TEMPERATURE n;l
fREQUENCY (MHz)
80
v-::: OV
~
V"
V+ -V- - l1V
70
v+ '" 20V
z
65
60
TA =25 C
I-
60
4.0
~
V' -V-" 20V
30
I "put Current v~ I nput Voltage
14
I
CL ::: 0
(")
DUTY CYCLE (%)
DUTY CYCLE'" 20%
f= 1 MHz
•0
~
/
",
:0
10
16
.5
Vc," 1000 pF
1 1/ I I
",
o
o
N
en
V
V
l..Y
/.
150
S,:!pply Current vs Temperature
1 V+r v-::: 17V:
CL ", 2000 pF
X /'
LL
/
AMBIENTTEM'ERATURE I C)
Transient Power (PAC) vs
900
./
V'-V-"20V~
120
s:
:I:
V
v:V -V
-v:""'2V
llV"
160
40
I
L
TA ::: 25 C
CL~"" 0
'0
MHOi26CG liN STll( AIR
AMBIENT TEMPERATURE rC)
o
o
N
en
.......
Optimum Input Capacitance vs
Rise Time vs Load Capacitance
Fall Time vs Load Capacitance
25
25
20
:;:
>=
~
a;
v+
~ V'-V-"17V
-V-=20V
15
~
10
~
!
'"b
!
~
I-
..... 1-
15
/'
~
~
5
400
600
.00
1000 1200
/
o
,200
!
~
~
<;>
z
"'"
I-
oO
15
~
1_
I
V/V"
11
l/
,tON
10
I\..
V
~
V
r- r0
,.
15
>=
w
a;
10
]:
2~
50
I
15 100 125
TEMPERATURE fC)
500
~
~
200
V
300
~
~
100
1000
200
CL
j-V;"20V
]:
c,~OO~
, 15
w
I
">=
I
'"
~
0
c ; 500'PF
10
'r-i- i""""
~
CL
":~:
I
l
I
-75 -50 -25
0
25
50
7? 100 125
TEM.ERATURE.fC)
800
1000 1200
Fall Time vs Temperature
20
C~F
, ~:;;.CL
600
25
1000 pF
-
400
INPUT CAPACITANCE, CIN (pF)
Ir-V""20V
I
I
-75 -50 -25
20
~
..... r-.,
tOFF
800
600
Rise Time vs Temperature"'
25
I
13 r-V -V "20V
eiN '" CL '" 1000 pF
12
r- Ao '" SOil
600
V+-V-=20V
CL ::: 1000 pF
TA=25°C
LOAD CAPACITANCE IpF)
Turn-On & Turn-Qff Time
vs Temperature
1+
400
700
400
TA '" 25"C
LOAD CAPACITANCE IpF)
14
30
~
Ro'" 50S2
Q
200
/'
.;-
10
Ro '" sou
T A =2S C
Output Pulse Width
V-::: '15V to 20V
20
~
i-':
!
v+ -
.00
,)
I
:::
---
l-
0
/'
r.
T
I
-15 -50 -25
0
25
50
TEMPERATURE
75 100 125
fc)
3·33
(.)
"
typical applications (cont.)
N
o
o
::z:
:E
......
AC Coupled MOS Clock Driver
••v
CD
C,·
~Pf
N
o
o
::z:
:E
C,·
MHOO2lCN
~'PF
1
TWO PHASE
CLOCK TO
SHIFT REGISTERS
54n4SERIES
GATES AND FLOPS
-12V
*S~
applicatIons SBCtlon for detailed mformatlOn on mput/output deSIgn criterion.
DC Coupled RAM Memory Address or Precharge
Driver (Positive Supply Only)
+17Y
100pF
100,lF
MHOD28CN
l
TD ADDRESS
LINES ON
MMll03TYPE
MEMORY SYSTEM
1/20M14DD
Precharge Driver for MOS RAM Memories
.m
CQNTROl
~~+----r----~~~
MEMORY
UfR£S~;;"'::"=----l_J-----~_+-----------------------___-i
3-34
3:
l:
typical applications
o
o
N
m
......
DC Coupled MOS Clock Driver
3:
o
"IV
l:
o
N
,,-'-1--1""--,om -"'T........,
.1 OUTPUT
,,-.!.I-....---
INPUT
m
n
~OUTPUT
-.,...-1....../
-uv
Transistor Coupled MOS Clock Driver
TTL INPUTS
{o--.....--,
TO SHIFT
} REGISTERS
':>o-+-+
_12 V
Logically Controlled AC Coupled Clock Driver
nLClOCKA
.PUT 0-....-.....:,
zo.
"----1
~
•
b
CLOCK INPUT - 2 to
ONE SKOT OUTPUT - AOJPULSE MOTH
PHASE ONE OUTPUT
PHAU TWO OUTPUT
3-35
(,)
co
N
o
o
application information
::I:
1.0 Introduction
:i!
.......
CO
The MH0026 is capable of dellvenng 30 watts
peak power (1.5 amps ~t 20Y needed to rapidly
charge large capacitative loads) while its package is
limited to the watt range. This section describes
the operation of the circuit and how to obtain
optimum system performance. I f additional design
information is required, please contact your local
National field application engineer.
N
o
o
::I:
:i!
a simplified diagram, D1 (Figure 3) provides 0.7Y
dead zone so that 0 3 IS turned ON for a rising
Input pulse and O 2 OFF prior to 0 1 turning ON a
few nanoseconds later. D2 prevents zenenng of the
emitter·base junction of O 2 and provides an initial
discharge path for the load via 0 3 , During a falling
input, the stored charge In 0 3 is used beneficially'
to keep 0 3 ON thus preventing O 2 from conduct·
ing until 0 1 IS OFF. 0 1 stored charge is quickly
discharged by means of common·base transistor
04 .
2.0 Theory of Operation
Conventional MOS clock drivers like the MH0013
and similar devices have relied on the circuit
configuration in Figure 1. The AC coupling of an
input pulse allows the device to work over a wide
range of supplies while the output pulse width
may be controlled by the time constant - R 1 X C1.
The complete circuit of the MH0026 (see sche·
matic on page 1) basically makes Darllngtons out
of each of the transistors in Figure 3.
",----",<>v'
",--",-ov'
EXTERNAL
INo-JC1~
OUT
",~"",--oOUT
C1
INo-J ~
EXTERNAL
H ..........- ....ovFIGURE 1. Conventional MOS Clock Drive
D2 provides 0.7Y of dead·zone thus preventing 0 1
and O 2 from conducting at the same time. In
order to drive large capacitive loads, 0 1 and O 2
are large geometry devices but Cob now limits
useful output rise time. A high voltage TTL output
stage (Figure 2) could be used; however, during
switching until the stored charge is removed from
0 1, both output devices conduct at the same time.
This is familiar in TTL with supply line glitches in
the order of 60 to 100 mAo A clock driver built
this way would introduce 1.5 amp spikes into the
supply lines.
",---",-ov'
C1
INo-J ~
EXTERNAL
OUT
01
L.......- _.........--ov-
FIGURE 2.
When the output of the TTL input element (not
shown) goes to the logic "1" state, current is
supplied through C 'N to the base of O[ and O 2
turning them ON, and 0 3 and 0 4 OF F when the
input voltages reaches 0.7Y. Initial discharge of
the load as well as E·B protection for 0 3 and
are provided by D 1 and D 2 . When the input
voltage reaches about 1.5Y, 0 6 and 0 7 begin to
conduct and the load is rapidly discharged by 0 7 ,
As the input goes low, the input side of C, N goes
negative with respect to Y- causing 0 8 and 0 9 to
conduct momentarily to assure rapid turn·off of
O 2 and 0 7 respectively. When 0 1 and O 2 turn
OF F, Darl ington connected 0 3 and
rapidly
charge the load toward y+ volts. R6 assures that
the output will reach to within one VB E of the
y+ supply.
a.
a.
The real secret of the device's performance is
proper selection of transistor geometries and resis·
tor values so that 0 4 and 0 7 do not conduct at
the same time while minimizing delay from input
to output.
3.0 Power Dissipation Considerations
Alternate MOS Clock Drive
Unique circuit design and advanced semiconductor
processing overcome these clasic problems allow·
ing the high volume manufacture of a device, the
MH0026, that delivers 1.5A peak output currents
with 20ns rise and fall times into 1000pF loads. In
3·36
FIGURE 3. Simplified MH0026
There are four considerations in determining
power dissipations.
1. Average DC power
2. Average AC power
3. Package and heat sink selection
4. Remember-2 drivers per package
s:
:I:
application information (cont.)
The total average power dissipated by the MH0026
is the sum of the DC power and AC transient
power. The total must be less than given package
power ratings.
o
o
N
Thus for RAM address line applications, package
type and heat sink technique Will limit drive
capability rather than AC power.
"-
3.2 AC Transient Power (per driver)
:I:
en
s:
o
o
AC Transient power is given by:
Since the device dissipates only 2mW with output
voltage high (MOS logic "0"). the dominating
factor in average DC power is duty cycle or the
percent of time in output voltage low state (MOS
logiC "1 "). Percent of total power contributed by
Poc is usually neglible in shift register applications
where duty cycle is less than 25%. Po c dominates
in RAM address line driver applications where
duty cycle can exceed 50%.
3.1 DC Power (per driver)
N
en
n
where: f
CL
= frequency of operation
= Load capacitance (including all
strays and wiring)
Example 3: W+
PAC
Poc = (V+ - V-I X (lS(Lowl) X
(
ON time
)
OFF time-ON time
where:
= (Output Low Power) X (Duty Cycle)
IS(Low) = Is
@
(V+ - V-I
Example I: W+ = +5V, Va) Duty cycle
=
-12V)
= 25%, therefore
Poc
= 17V X 40mA X 17/20 X 25%
Poc
= 145mW worst·case, each side
Po 'c
= 109mW typically
b) Duty cycle = 5%
Poc
= 21mW
c) See graph on page 3
The above illustrates that for shift register applica·
tions, the minimum clock width allowable for the
given type of shift register should be used in order
to drive the largest number of registers per clock
driver.
Example2: W+=+17V, 'V=GND):
a) Duty cycle
= 50%
Po C = 290mW worst·case
POC
= 218mW typically
b) Duty cycle
Poc
'V
= -12V)
= 17 X 17 X f(MHz) X 10 6 X
C L (nF) X 10- 9
DC Power is given by:
or Poc
= +5V,
= 100%
= 580mW
PAC
= 290mW per MHz per 1000pF
Thus at 5MHz, a 1000pF load will cause any driver
to dissipate one and one half watts. For long shift
registers, a driver with the highest package power
rating will drive the largest number of bits for the
lowest cost per bit.
3.3 Package Selection
Power ratings are based on a maximum junction
rating of 175°C. The following guidelines are
suggested for package selection. Graphs on page 3
illustrate derating for various operating tempera·
tures.
3.31 TO-5 ("H") Package: Rated at 600mW still
air (derate at 4.0mW/oC above 25°C) and 900mW
with clip on heat sink (derate at 6.0mW/oC above
25°C). This popular hermetic package is recom·
mended for small systems. Low cost (about 10¢)
clip·on·heat sink increases driving capability by
50%.
3.32 8,PIn ("N") Molded MInI·DIP: Rated at
600mW still air (derate at 4.0mWtC above 25°C)
and 1.0 watt soldered to PC board (derate at
6.6mWtC). Constructed with a special copper
lead frame, this package is recommended for
medium size commercial systems particularly
where automatic insertion is used. (Please note for
prototype work, that this package is only rated at
600mW when mounted in a socket and not one
watt until it is soldered down.)
3.33 TO-8 ("G") Package: Rated at 1.5 watts
still air (derate 'at 10mWtC above 25°C) and 2.3
watts with clip on heat Sink (Wakefield type
215-1.9 or equivalent-derate at 15mWtC).
Selected for Its power handling capability and
moderate cost, this hermetic package will drive
very large systems at the lowest cost per bit.
3·37
(.)
CD
N
application information (cont.)
o
o
3.4 Summary-Package Power Considerations
:t
~
Dc
The maximum capacitative load that the MH0026
can drive is thus determined by package type, heat
sink technique, ambient temperature, AC power
(which is proportional to frequency and capacitive
load) and DC power (which is principally deter·
mined by duty cycle). Combining equations previously given, the following formula is valid for ,
any clock driver with negligible input power and '
negligible power in output high state:
......
CD
N
o
o
:t
~
CL (max
pF)
In
0
(V'" - V-I' X Roq X f(MHz)
C L (max in pF)
= .5 X
Time in output low state
Time in output low + Time in output high state
Table I illustrates MH0026 drive capability under
various system conditions.
4.0 Pulse Width Control
Two external input coupl ing capacitors are required to perform the level translation between
TTLlDTL and MOS logic levels. Selection of the
capacitor size is determined by the desired output
pulse width. Minimum delay and optimum performance is attained when the voltage at the input
of the MH0026 discharges to just above the
devices threshold (about 1.5Vl. If the input is
allowed to discharge below the threshold, to F F
and tf will be degraded. The graph on page 3
shows optimum values for C'N vs desired output
pulse width. The value for C'N may be roughly
predicted by:
V s ' X 500 X f(MHz)
Where: n ~ number of drivers per pkg. (2 for
the MH00261
PmaxlmW)(T A' pkg) ~ Package power
rating in milliwatts for given package,
heat sink, and max, ambient temperature (See graphs)
~
~
10-3 X
Pmax(mW)X 500-Vs' X DcX 10'
R.q
Duty Cycle
The MH0026 is intended for applications in which
the input pulse width sets the output pulse width;
i.e., the output pulse width is logically controlled
by the input pulse. The output pulse width is given
by:
)
_
t, +tf _
(PW OUT- (PW1 ,N+ 2- - PW ,N +25ns
10-'
n
X
PmoxlmWI(TA,pkg) X ROq - (V+ - V-I' X (Dc) X 10'
or:
~
equivalent internal resistance
C'N ~ (2X 10-3 ) (PWl oUT
Req ~ (V+ - V-)/lsILow) ~ 500 ohms (worst
case over temperature for the MH0026 or
660 ohms typically)
For an output pulse width of 500ns, the optimum
value for C, N is:
Vs = (V+ - V-) = total supply voltage across
device
C, N ~ (2 X 10- 3 )(500 X 10- 9 1 == 1000pF
TABLE 1. Worst Case Maximum Drive Capability for MH0026*
TO·8WITH
HEAT SINK
PACKAGE TYPE
TO-8
FREE AIR
MINI·DIP
SOLDERED DOWN
TO·5 AND MINI·DIP
FREE AIR
Max.
Max.
Operating
Frequency
~
I
Temp.
....
60°C
85°C
60°C
85°C
60°C
85'C
60'C
85'C
Duty Cycle
100kHz
5%
30 k
24 k
19 k
15 k
13 k
10k
7.5k
500kHz
10%
6.5k
5.1k
4.1k
3.2k
2.7k
2k
1.5k
lMHz
20%
2.9k
2.2k
1.8k
1.4k
1.1k
l.4k
1.1k
1.1k
840
600
430
2MHz
25%
850
650
550
400
280
190
5MHz
25%
620
470
380
290
240
170
120
80
10MHz
25%
280
220
170
130
110
79
-
-
*Note' Values In pF and assume both Sides In use as non-overlapmg 2 phase driver, each Side operating
at same frequency and duty cycle with (V+ - V-) == 17V For loads greater than 1200 pF,
rise and fall times Will be limited by output current, see Section 5 0
3-38
5.8k
3:
o
.~
application information (cont.)
5.0 Rise & Fall Time Considerations(Note 3)
The MH0026's peak output current is limited to
1.5A. The peak current limitation restricts the
maximum load capacitance which the device is
capable of driving and is given by:
1= C L
The rise time,
predicted by:
t"
dv
at.';; 1.5A
for various loads may be
t, = (LW) (250 X 10- 12 + C L )
== V+ - VC L = The load capacitance
For V+ - V- = 20V, C L = 1OOOpF, t, is:
==
=
(20V) (250 X 10- 12
25ns
+ 10- 12 )
For small values of C L , equation above predicts
optimistic values for t,. The graph on page 3
shows typical rISe times for various load capaci·
tances.
The output fall time (see Graph) may be predicted
by:
t f == 2.2R(C s +~)
hFE
........
3:
~
o
o
N
en
7.0 Clock Line Cross Talk
Where: /:,V = The change in voltage across C L
t,
o
en
N
practice, determination of a value for L is rather
difficult. However,R s is readily determined emper·
ically, and values typically range between 10 and
51 ohms. Rs does reduce rise and fall times as
given by:
+1
6.0 Clock Overshoot
The output waveform of the MH0026 can over·
shoot. The overshoot is due to finite inductance of
the clock lines. It occurs on the negative going
edge when 0 7 saturates, and on the positive edge
when 0 3 turns OFF as the output goes through
V+ - V be' The problem can be eliminated by
placing a small series resistor In the ouput of the
MH0026. The critical valve for Rs= 2yLlCQ where
L is the self·inductance of the clock line. In
(")
At the system level,voltage spikes from -......H-;)oc>--t':::.'0 TTL 9,
14 Vss
WIDTH
CONTROL
):>-+-I---;)oc..-;-t'-o TTl "2
L-:-.....-rOOGND
.....--"vv-r-l"-O MOS DAMPED "1
IJ UST
2
12 FREOUfNCY
CONTROL
Mas DAMPED 91
MOS2
nL¢,
TTl ¢>z
MOS¢2
Ro
""--"",,""""-+''-<> MOS DAMPED 92
'-----t'-oM08<:>1
MH1B03
' - - - - - - + 0 0 MOS¢2
v"
TOPVIEW
Order Number MH7803J or MH8803J
See Package 16
Order Number MH8803N
v~
3-40
TEST
See Package 22
Note 1: These specifications apply for the MH7B03 at VSS - VOO ~ 17V ±10% and over-55°C to +125°C; for the MH8803
at VSS - VOO = 17V ±5% and over O°C to +70°C unless otherwise specified.
Note 2: The duty cycle can not physically exceed 50% at any output. At high frequencies the frequency adjust pin will affect
the pulse width by limiting the duty cycle to slightly less than 50%. Under thiS condition the pulse width spec does not apply.
typical performance characteristics
Frequency and Pulse Width
Pulse Wi
~
..
300
PIN 12 OPEN -
:>
~
200 I-++++~'I-I++-++++J..-l-j
100
]
10
~
PIN 2 OPEN
...,-r+f-Hf-H
iii
~
f-J.-Hf...l..lH-HH-H-HH-J..-l-j
0.5
f-J.-HH-+-+-H-"Ioo.J.-+-HH-J..-l-j
FREnUENCY CONTROL VOLTAGE MINUS Voo (VI
~
~
;i
>
10
H+H"k-H-H+1A+f-H
~ -10
H+H,If-+-++++N+l-H
.
!!l"
~
::i
H-++4-l+H-+-+++-HH-+-l
0'-'-J....I...J....1...J....L...I..J....I...J....1...wu...w
103.0507.090 11 13 15 17
vs Temperature
OLLLLLLLL.LJ...LJ...LJ...LJ.....1...1
10 30 50 70 90 11 13 15 17
PULSE WIDTH CONTROL VOLTAGE MINUS Voo (VI
~
-20
H~HP.W-i·++-f+H-H+'N
~II
-30 W...L..L..l...l-l...L..L..l...l-l...L..L..l..J.J
-75 -50 -25
0
25
50
75 100 125
AMBIENT TEMPERATURE lOCI
3·41
('I)
o
CIO
CIO
typical performance characteristics (con't)
:r::
Total Transient Power
vs Frequency vs Total CL
Frequency and Pulse
~
.......
Maximum Package Dissipation
Width vs VSS-VDD
15
('I)
o
CIO
:r::
"""
10
oH-+++b);=i"t+t+H-t-H
~
I
FREQUENcvH++-+++-+-j
05
~
~
I
-20
-30
I .......
13
14
"
\ ~,..L
~r(
15
16
17
23
24
0
25
25
~u;
200
"....'"
"........
100
50
75
z
~
Q
125
100
150
0
£V
V
L
~
LV ~
~~ t:::: I--::L
£
100
200
300
400
500
600
ICC vs Duty Cycle
,-r--r---,--,--,
6.0
4.0
30~0/"
I
FREQUENCV 1kHz)
ISS vs Duty Cycl.
8.0
I
TEMPERATURE 1°C)
VSS-VOD
".s.li
300
:r
, ~,\
,
L ~oo~~
Vss-Voo :: 11V
.s
'"~
..L..I...J-.... ,.....I-'-'-.J..J
L-J....J-'--..L..I
12
r-
400
~
0.9
-
.....-
08
".sJl
2.0
" 1"'---
07
.......
0.6
"
r-....
05
0
10
20
30
40
0
50
10
20
30
40
50
DUTV CYCLE (%)
DUTV CYCLE 1%)
applications information
TTL MONITOR OUTPUTS
16~OS
~1
80=
0=
The TTL outputs are extra functions provided for
monitor or synchronization applications. In some
systems these outputs may not be required. For
these cases the Vee pin may be left open and the
TTL circuitry power consumption will be virtually
zero.
_'"-wi
20-
12-
MOS
-::Jllf~
I;' :~:ESHOlO
-12-
50-
\
JO10=
The TTL outputs are slaved to the MaS outputs.
Thus the TTL outputs start to switch when the
MaS outputs cross the TTL threshold voltage
(about 1.5V above ground). Figure 1 depicts the
effect of different supply voltages on the TTL
waveform when the MaS outputs are driving
capacitive loads.
15VTHRESHOLD
TTL
¢,
::==
10
r
10
T¢:L \ .
OUTPUT WAVEFORMS
OUTPUT WAVEFORMS
WITH +11V, +5 OV, DV SUPPLIES
WITH +5ilV, -12V,OV SUPPLIES
(A)
(6)
FIGURE 1.
DAMPED MOS OUTPUTS
Typically they perform as follows:
An extra set of MaS outputs provides a 10 ohm
resistor in series with each output line. These
resistors give the output pulses an R-C rolloff
which tends to minimize ringing or peaking
problems associated with board layout.
INHIBIT AND TEST INPUTS
The INHIBIT and TEST inputs are deSigned to
facilitate testing of the device. They were not
included in the IC for system use.
3-42
INHIBIT Input: in the low state pr~vents pulses
. from being initiated on either phase output.
High Level Input:
V ,H ~ V DD
+ 2.0V
Low Level Input:
V DD
+ O.2V ~ V ,L
~
V DD - O.5V
3:
::I:
....00
applications information (con't)
o
TEST Input: in the low state forces a ONE state
on all outputs. The test input should only be used
with the INHIBIT input also in the low state.
2
.......
3:
::I:
PAC ~ [(Vcc - GND)2 X f x
High Level:
V1H
w
Where
Cd TTL
Cd MaS
o
+ [(Vss - V OO )2 X f x
voo + B.OV
Low Level:
00
00
w
And
Poc
~
(lcd x (V cc - GND)
+ (Iss)
x (Vss-V oo )
A pull-up resistor is connected from the TEST
pin to Vss internally.
for Icc and Iss selected at the appropriate duty
cycle.
POWER CONSIDERATIONS
For practical cases the PAC TTL can be neglected
as being very small compared to PAC MOS,
Internal power dissipation is affected by three
factors:
• dc power
• ac power
• package dissipation capability
The total average power dissipation is the summation of the dc power and ac power. This sum
must be less than the maximum package dissipation capability at the particular operating temperature to insure safe operation, i.e.:
P01SS ~ PAC + POC .:; PMAX
Thus P01SS is the sum of the MaS transient
power (total for both sides of the MH7B03) and
the standby power of the TIL and MaS sections
of the MH7B03.
DECOUPLING
It is recommended that each device be decoupled
with a O.l!lF capacitor from Vss to Voo. If there
is noise on the supply lines, better frequency and
pulse width stability can be obtained by connecting
a O.OOl!l F capacitor from the frequency control
pin to V 00 and another O.OOl!lF capacitor from
the pulse width control pin to Voo.
3-43
00
o
00
00
Memory/Clock Drivers
:::t
:E
MH8808 dual high speed MOS clock driver
general description
features
The MH8808 IS a high speed dual MOS clock
driver intended to drive the two phases of a
memory array of 500 pF per phase at rates up to
4 MHz. The design Includes output current limit·
Ing for controlled rise and fall times, and thermal
shutdown which protects the chip against excessive power dissipation or accidental output shorts.
Two DTL!TTL compatible status outputs monitor
clock outputs and provide a corresponding TTL
logic level for status indication. Both direct and
internally damped outputs are available for each
phase to suit the particular application. It is ideally
suited for driving MM5262 2k RAMs.
•
High Speed: 18 ns typ delay and 20 ns typ rise
and fall times with 500 pF load
•
Current limited outputs ±450 mA typ
•
Direct and damped outputs available
•
Thermal shutdown protection
•
TTL compatible status outputs
•
1W dissipation capability at 25°C T A
•
16 pin cavity dual-in-Ilne package
•
Output high level clamped to +5V
connection diagram
Dual-I n-Line Package
Vss
16
DAMPED
OUT
15
Voo
OUT
14
OUT
12
11
'DO NOT CONNECT TO THIS PIN
TOP VIEW
Order Number MH8808J
See Package 17
Order Number MH8808N
See Package :?3
3·44
DAMPED
OUT
10
NC
s:
~
absolute maximum ratings
00
00
V.
+N
Vss - V OD
Total Power DISSipation (Note 1)
26V
lW
o
00
O°C to + 700 e
Operatmg Temperature Range
electrica I characteristics
The following apply for Ves '" +7V, Vss
-=
+5V, Voo;= -15V, TA "" 25°C unless otherWise stated
PARAMETER
CONDITIONS
V'N = -9V (Note 21
Output Low Voltage
lOUT = +1 rnA, VIN -= -lOV
(Note 21
Output High Voltage
lOUT = -1 mA, VIN
Status" 1 " Voltage
lOUT
Status "0" Voltage
lOUT =
-14V
=;;
= -250IlA, V'N = -14V
20 rnA, VIN
MIN
MAX
10
Input Current
=
53
3
v
V
05
-10V
mA
v
-14
45
UNITS
V
(Note 21
Output Leakage Current
V BB = +8 5V, Vss = 5V
V OD = -17 5V, V OUT = +8 5V
VIN =
100
open
4
Damping Resistor
V'N = -11 5V
Vss = +6 5V, V DD = -17 5V
V BB = +8 5V (Note 21
IlA
11
32
mA
23
mA
-55
mA
V'N = -11 5V
Vss = +6 5V, V DD = -17 5V
Iss
Vss
=
+8 5V (Note 2)
100
V'N=-115V
Vss = +6 5V, V DD = -17 5V
V BB = +8 5V (Note 21
Output Rise Time
C L = 500pF
26
ns
Output Fall T ,me
C L = 500 pF
26
ns
Delay to Negatlve-Gomg Output
CL
= 500 pF
7
22
ns
Delay to Positive-GOIng Output
C L = 500 pF
10
25
ns
Note 1: Maximum junction temperature is +12SoC. For operation above +25°C derate at +80°C/W ()JA for still air.
Note 2: Test only one input high (more positive) at a time.
3-45
c
3:
~
Line 0 rivers/Receivers
N
o
......
c
3:
OM7820/0M8820 dual line receiver
00
00
general description
o
N
The DM7820, specified from ·55°e to 125°e, and
the DM8820, specified from oOe to 70 o e, are
digital line receivers with two completely indepen'
dent units fabricated on a single silicon chip.
Intended for use with digital systems connected
by twisted pair lines, they have a differential input
designed to reject large common mode signals while
responding to small differential signals. The output
is directly compatible with RTL, DTL or TTL
integrated circuits.
• Each channel can be strobed independently
• High input resistance
• Fanout of two with either DTL or TTL
integrated circuits
The response time can be controlled with an ex·
ternal capacitor to eliminate noise spikes, and the
output state is determined for open inputs. Ter·
mination resistors for the twisted pair line are
also included in the circuit. Both the DM7820 and
the DM8820 are specified, worst case, over their
full operating temperature range, for ±10·percent
supply voltage variations and over the entire input
voltage range.
features
• Operation from a single +5V logic supply
• Input voltage range of ± 15V
, schematic and connection diagrams
Dual-ln·Line and Flat Package
R(SPONSETIME
CONTROl
"
'"
",
RI'
~
."
IlION.IIVERTING
''''UT
~:
.... .
AI
TERMINATIOIiI
..
'.PUT
IS'
'""
""
IN'UT
..
~MN~Q1 . ~
...'n
.
RESPONSE TIME
RI.
'"~
.....
""
RI
INVERTING
3K
"'-"110
"
n."
RI,
'"
5K
'"
INPUT-"--.f---iURC.!lNATiQN
""
DUtf'UT
-=--1----1
AESPOIliSETIME
L--+-'_OUTPUT
GROUND
TO' VIEW
RI.
n.
Order Number DM7820J Dr DM8820J
See Package 16
'""
Order, Number DM8820N
See Package 22
Order Number DM7820W or DM8820W
See Package 27
STROlE
typical application
LINE DRIVER AND RECEIVER:::
1/2DM7830
TWISTED PAIR LINE
OUTPUT
tVee IS 4 5V to 5 5V for both the
DM78201ndDM783D.
tExactvaluadepandsonlmelength
*OpbonaltoGontrol response time
STADBE
4·1
0
N
CO
CO
absolute maximum ratings
:eC
8.0V
±20V
±20V
Supply Voltage
.......
0
Input Voltage
Differential Input Voltage
N
CO
....
8.0V
25mA
Strobe Voltage
Output Sink Current
Power Dissipation (Note 1)
Operating Temperature Range
DM7820
DM8820
Storage Temperature Range
Lead Temperature (Soldering. 10 sec)
:e
C
600mW
-55°C to +125°C
O°C to +70°C
-65°C to +150°C
300°C
electrical characteristics
PARAMETER
(Notes 2 & 3)
CONDITIONS
Input Threshold Voltage
VIN ~ 0
-15V::;V II,::; 15V
High Output Level
lOUT::; 0.2 mA
Low Output Level
I'ink ::; 3.5 mA
MIN
-0.5
-1.0
0
0
MAX
UNITS
0.5
1.0
V
V
2.5
5.5
V
0
0.4
V
Inverting Input Resistance
3.6
5.0
kQ
Non-inverting I nput Resistance
1.8
2.5
kQ
Line Termination Resistance
T A ~ 25°C
Response Ti me
Cdelay ~ 0
Cdelay ~ 100 pF
Strobe Current
V strobe
~O.4V
V strobe
~
Power Supply Current
120
Non-inverting Input Current
Inverting Input Current
170
ns
ns
1.4
-5.0
mA
J1A
3.2
5.8
8.3
6.0
10.2
15.0
mA
mA
mA
5.0
-1.0
-7.0
7.0
-1.6
-9.8
mA
mA
mA
4.2
-0.5
-4.2
3.0
0
-3.0
mA
mA
mA
VIN ~ 15V
VIN ~ 0
VIN ~ 15V
VIN ~ 0
VIN = -15V
Q
1.0
5.5V
VIN ~ 15V
VIN ~ 0
VIN ~ -15V
250
40
150
VIN~-15V
Note 1: For operating at elevated temperatures, the device must be derated based on a
thermal resistance of 1000 C/W and a maximum JunctIon temperature of 160°C for the
DM7820 or 105°e for the DM8820.
Note 2: These specifications apply for 4.5V::;: Vee::;: 5 5V. -15V::;: V CM ::;: 15V and
_55°e::;: T A ::;: 125°e for the DM7820 of oOe::;: T A ::;: 70 De for the DM8820 unless
otherwise specified; tYPical values given are for Vee:;; 5.0V, TA = 2SoC and V CM = 0
unless stated differently.
Note 3: The specifications and curves gIven are for one Side only Therefore, the total
package dissipation and supply currents will be double the values given when both
receivers are operated under identical conditions.
4-2
TYP
c
typical performance characteristics
3:
(Note 3)
"""
00
N
o
......
Supply Voltage Sensitivity
Common Mode Rejection
3:
0.3
~
.'"
..
w
TA =,25°C
..'"
.
~ 0.4
w
0.2
~
>
....
~
'"~ -0.1 1--+--+-+--+-I--=f".....0;;;;::1
~
ffi
~ -0.2
-0.3
1--+--+-+--+-1--+--+---1
L----L--'-_'--"--'-_'--'--'
4.5
4
5
....
~ ~
I'" -0.2
i
~
1
..
-
~"k
.ll
I
-20
-10
10
-0.4
20
-0.2
0.2
0.4
OIFFERENTIAL INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Termination Resistance
2111
Vee'" 5V
TA '" 25°C
~
-4
.
..'"
..~
w
\" Cd• ltv '" 100 pF
w
/'
....
~
.
""\
II
~
>
\
o
0.2
3
..'"
w
In
0.2
- r-OUTPUTLOW0.1
ico1i
-75 -50 -25
TIME ("')
0
/.
190
r--...
170
r-
160
I
I
o
o.B
0.6
0.4
190
g
u
~
....=>
o
Vee" S.OV
>
\
Cd.l.y=O,
~
OUTPUT H i G t t
~
-
> -2
~
,
25°e
III
Output Voltage Levels
w
~
o
1
5.5
~
N
t:;. i-"'"
125°C-
I~r-
I
!:!:-O.4
Response Time
=>
~
55°C,
r- :::::
3.5;:;:~
I
,
.L.
~.
~·O.2"A
. v. 'OOT •
SUPPLY VOLTAGE (V)
..'"
.
....
'n+- -
Voo~
00
00
Vee" 5V
I-FANOUT'2
I
I
t;: -JOlJl'''''Z.5V I
~ 0.2
> 0.1
c;
c
Transfer Function
150
25
50
75 100 125
-75 -50 -25
Positive Supply Current
0
25 ·50
75 100 125
TEMPERATURE (OC)
TEMPERATURE (OC)
Internal Povver Dissipation
Maximum Power DiSSipation
300
10
-
,/
700
Vcc=50V
='"
.......
OUTPUTLOW
Vee'" 5V
~(O~ r- l"".
......
......
OUl"PUl"
#1(;,#
r-;;. I -
200
;::
::
..:--.
,..... ,.....
~
cc: 100
~
.,
\~
j~
'\
~
-10
10
INPUT VOLTAGE (V)
20
-20
-10
25°C
-j
I'=f'
f
10
INPUT VOLTAGE (V)
~ 500
::
~ 400
co
~
125°C
o
-2
-20
~ 600
i§: ~
~Ul"A
~
1\
\
r- r-.O!
i'
r- ~ fa,\
I
I 1\
f 300
\;
\
BOTH SIDES
1
200
20
\\~ -
25
45
65
85
105
125
AMBIENT TEMPERATURE (OC)
4-3
c(
o
N
00
00
Line Drivers/Receivers
::!E
Q
......
c(
o
DM7820A/DM8820A dual line receiver
N
fe
::!E
general description
Q
The DM7820A and the DM8820A are improved
performance digital line receivers with two completely Independent units fabncated on a single
silicon chip. Intended for use with digital systems
connected by twisted pair lines, they have a differential Input designed to reject large common mode
signals while responding to small differential SIgnals. The output is directly compatible with RTL,
DTL or TTL integrated circuits. Some Important
design features include:
•
• Outputs can be wire OR'ed
• Series 54174 compatible
The response time can be controlled with an ex·
ternal capacitor to reject Input noise spikes. The
output state is a logic "," for both inputs open.
Termination resistors for the twisted pair lille are
also included in the circuit. Both the DM7820A
and the DM8820A are specified, worst case, over
their full operating temperature range (_55°C
to '25°e and oOe to 70°C respectively). over the
entire input voltage range, for ±'O% supply voltage variations.
• Operation from a single +5V logic supply
Input voltage range of ±'5V
•
• Strobe low forces output to "," state
•
Fanout of ten with either DTL or TTL integrated circuits
High input resjstance
schematic and connection diagrams
. Dual-In-Llne Package
"Vcc
RESPONSE TIME
CONTROL
TERMINATION
'"'"
...'"
~
'"
""
NON INVERTING
,.,
INPUT
...... r -
-
'""
.
""
~
'"~
'"
'"
"
_ ..... 0'0
~ n~" . ~
""
AESPOIIISETlM£
..
..,"
'"'"
'"
'"
..
""
R3
.
""
Note Pm 'l connactadtobottomofclYltVlNckaga.
Order Number DM7820AJ Dr DM8820AJ
See Package 16
'"
15'
Order Number DM8820AN
See Package 22
'"
INVERTING
INPUT
H
""
,
"'"
Note. Schematic shOWI one-half of Unit
typical applications
Order Number DM7820AW Dr DM88Z0AW
See Package 27
Single Ended (EIA-RS232C) Receiver with Hysteresis
Differential' Line Driver and Receiver
Cl
01
~F
OUTI'IlT
IDUTPUT· '"fOR
O'UINPUT)
*Opttonal to control response time
4-4
o
s:....
absolute maximum ratings
electrical characteristics
PARAMETER
Differential Threshold Voltage
CO
N
o
8.0V
±20V
±20V
8.0V
50mA
600mW
Supply Voltage
Common-Mode Voltage
Differential Input Voltage
Strobe Voltage
Output Sink Current
Power Dissipation (Note 1)
Operating Temperature Range
DM7820A
DM8820A
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
l>
........
o
s:CO
CO
N
o
_55°C to 125°C
O°C to 70°C
_65°C to 150°C
300°C
l>
(Notes 2,3 & 4)
VCM
<; V CM <; +3V
<; V CM <; +15V
-3V <; V CM <; +3V
-15V <; V CM <; +15V
CONDITIONS
OUTPUT
MIN
OTHER
2: 2 5V
2: 2 5V
V OUT <; O.4V
V OUT <; O.4V
UNITS
-4001lA
V OUT
+0.06
+0.5
V
-15V
-4001lA
V OUT
+006
+1.0
V
-0.08
-0.5
V
-0.08
-10
Inverting Input Resistance
-15V
<; VCM <; +15V
-15V
<; V CM <; +15V
+16 mA
+16mA
36
18
TA
Lme Termmatlon Resistance
25°C
"
120
5
25
170
250
V
kn
kn
n
+3.0
+42
0
-0.5
mA
-15V
-3.0
-4.2
mA
+15V
+5.0
+7.0
mA
OV
-10
-16
mA
-15V
-7.0
-9.8
mA
+6.0
+10.2
mA
mA
+15V
OV
Non-Inverting Input Current
MAX
-3V
Non-Inverting Input Resistance
Inverting Input Current
TYP
V D1FF
OV
Logic "0"
Logic "0"
V DIFF "-05V
+3.9
+65
-15V
Logic "0"
Vo1FF=-lV
+92
+14.0
Logical "1" Output Voltage
-4001lA
V D1FF
25
4.0
55
V
Logical "0" Output Voltage
+16mA
VD1FF
0
022
0.4
V
Logical "1" Strobe Input Voltage
+16mA
V OUT
<; O.4V,
V DIFF " -3V
Logical "0" Strobe Input Voltage
-4001lA
V OUT
2: 2 5V,
V OIFF " -3V
+15V
Power Supply Current
Logical "1" Strobe Input Current
Logical "0" Strobe Input Current
Output Short Circuit Current
OV
DifferentIal Input to "1" Output
Strobe Input to
"a"
Output
Strobe Input to "1" Output
= +lV
=;
-lV
5
VSTROBE =
a 4V, V D1FF = -3V
= 5 5V,
5V, V D1FF
21
VSTROBE = OV
mA
V
0.9
V
50
IlA
-10
-1.4
mA
-2.8 -45
-6.7
mA
= +3V
VSTROBE =
Vee
PropagatIon Delays (see waveforms)
DIfferentIal Input to "a" Output
0=
-lV
mA
001
V cc "5V, T A "25°C
30
45
Vce" 5V. T A
25°C
35
55
ns
Vcc" 5V, T A "25°C
16
25
ns
Vcc" 5V. T A
18
30
ns
"
"
25°C
ns
Note 1: For operating at elevated temperatures, the deVIce must be derated based on a thermal
resIstance of 1000 C/W and a maxImum JunctIon temperature of 160°C for the DM7820A, or
1500 C/W and 115°C maxImum junction temperature' for the DM8820A.
Note 2: These specifications apply for 4.5V ~ VCC ~ 55V, -15V ~ VCM ~ 15V and -55°C ~
T A ~ 125°C for the DM7820A or aoc ~ T A ~ 70°C for the DM8820A unless otherwise specified.
TypIcal values gIven are for Vee = 5.0V, TA = 25°C and VCM
OV unless stated differently
0:
Note 3: The specifIcatIons and curves gIven are for one side only. Therefore, the total package
dissipatIon and supply currents will be double the values given when both receivers are operated
under IdentIcal conditions.
Note 4: Min and max limIts apply to absolute values.
4-5
r- -1-.l.'iN.lou'
~ou'
~
I
IO~T '" 161mA
VOUT =- O.4V,
-0.1
I-
.... -0.2
i
~
'"
TA;: 25°C
'"
~
c
I
~
~
~ 0.4
Q
F;;;::
c
I VCM1"OV
....
~
'"
-0.2
4.5
E
5.0
5.5
6.0
S
:;..0:
:£
u
+10
-10
~
·(1 -~5"C- -
z
c
~
z
,..~
1 1
----"'..!:t...
-0.2
0.2
./
./
l"- I - ......
170
t-I--
1!l
....... at/I:
,ot/,/'
-..,.;: (0",
1-"";'
r--...
1
-S-IO-S-_I--~
-,...,.
I
I
o
-20
,g
200
~
0
\l:
r-........
-20
'"
~
C
;::
15
30
26
22
......
~
c
./
0
25
50
I
i
1
,..
-INPUT.;>
-2
75 100 125
A
-6
f'-+INPUT
-10
-20
1
10
26
.
::0::'1
I
Vee = SV
~
A
-10
~.
;'"
- r-
=
>
10
3~
~
O. 3
c
O. 2
1
J.-I-
~~OU1;~
I~ "'~
IO( I I
tOGlc~t
r-
0
50
75 100 125
Noise Rejection
/
STRDBE TD "1" OUTPUT
\'L
~-
-
./
0
25
TA I"C}
,..'"c
1/
i
w
"w
100
~
i.--"
"\
50
Vee'" SV
TA = 2SoC
VOrFF - +2.SV PULSe
g
~
- !---c :;;ZSTR08E TD "0" DUTPUT
10
-75 -50 -25
25
TA rC}
1000
22
14
r-
I
O. 1
-75 -50 -25
20
I
LOGICAL "1" DUTPUT,
lOUT =-400 ~A -
!;
Vee = sv
18
20
Output Voltage Levels
W
I
~
1
-10
5
~'c
.
.....-:
...... ...... 1
-4
w
~
,... ......
,,~
INPUT VDLTAGE IWITH RESPECT TD GRDUND} IV}
~
c
a:
DIFFERENTIAL
TD "1" DUTPUT
TA I"C)
4-6
>
t;
i"""
18
-75 -50 -25
25
I
i
CC • , Ov
DUTPUT LDW
100
Differential Input Delays
38
~
J
~
~
c
a:
COMMDN-MDDE VDLTAGE IV)
42
-100
-8
1<
I'...
+10
-10
~
ct
I nternal Power Dissipation
§
Ot/J;ot/,/'
-50
TA I"C}
I I Vcc"5V~HTA"25OC_
- ~~
'"
i
160
-75 -50 -25
0.4
./
300
-........
~
E
180
Power Supply Current
.......
c
c
r- ~:c: =2:~C
190
DIFFERENTIAL INPUT VDLTAGE IV)
-........
>
Input Characteristics
;:
If
I I I
10
+20
1--+-+-',
50
~
,..'"
z
-55"C_
-0.4
~
c
Termination Resistance
~~
I I
I I
~
_ '6"'~~
.G.4~~~;;-
COMMON·MDDE VDLTAGE IV}
~\25JC",," ..
1 1
• -4~G"~L
~ffi
-20
Transfer Function
FANOUT "10
-
"oIJ1'
,g
-0.4
SUPPLY VOLTAGE IV}
Vee'" s.nv
VCM = OV
Temperature Sensitivity
100 , -......:::0-,-"'1"'-,-,:,---.;:::-1
S
75 100 125
~
~
x
"'"
10
10
100
1000
CRESPONSE TIME CONTROL (pF)
10,000
c
3:
ac test circuit and waveforms
'-I
00
N
o
l>
.....
c
r----------------t~~V~·5V
PULSE
GEN.
400"
15 pF"
3:
00
00
N
FD10D (4)
o
l>
PULSE
GEN.
*lncludesJlgandProba
tr =tf= 10ns
PRR=1MHz
OIFF +2.5V---~r--...
ov
INPUT
-2.5V
STRDBE
INPUT
ov
DUTPUT
A '" Differential Input to "0" Output
B = Dltferentlallnput to "1" Output
e = Strobe Input to "0" Output
o = Strobe Input to "1" Output
4·7
N
N
co
co
::E
Q
......
Line Drivers IReceivers
N
N
~
::E
DM7822/DM8822 dual line receiver
Q
general description
The DM7822/DM8822 is a dual Inverting Ime
receiver which meets the requirements of EIA
specification RS232 Revision B. The device con·
tams both receivers on a smgle monolithic silicon
chip. The receivers share common power supply
and ground connections, otherwise their operation
IS fully mdependent.
high state Independent of the Information being
received at tl;1e mput.
The output of the DM7822/DM8822 IS completely
compatible with five volt DTL and TTL logic
families
The DM7822 is specified for operation over the
-55°C to +125°e military temperature range. The
DM8822 is specified for operation over the oOe
to + 70°C temperature range.
I n addition to meetmg the requirements of RS232,
the DM7822/DM8822 also has Independent strobe
mputs which allow the receiver to be placed In the
connection diagram
Vee
INPUT
INPUT
D~TPUT
STROBE
STROBE
OUTPUT
*MllkenoconnlC1lontotheseplns
HFor o,.m.on requiring ''MIrk Hold" With the Input open connect a 470n
I1ISIstonfrom ..... ofthmpmstoground
Ord ... Number DM7822J
See Package 16
Order Number DM8822N
See Package 22
typical connection
TWISTED PAIR LINE
Rl'
*For Mark Hold R1 ;; 4700, otherwlS1lconnect Pin 3 to ground
4·8
GNO
c
3:
.....
absolute maximum ratings
CO
N
N
.....
Supply Voltage
Input Voltage
Strobe Voltage
Output Sink Current
Power DISsipation (Note 1)
Operating Temperature Range
DM7822
DM8822
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
electrical characteristics
PARAMETER
Negative I nput Threshold
Voltage
PARAGRAPH IN
RS-232
4.8 (B)
CONDITIONS
MIN
TYP
4.5 and 4 B (5)
4.5 and 4.B (4)
3.0
Y'N
Y'N
Y'N
= 25V
= OV
= -25V
Y'N
= OV
3.57
-B.33
Logical "1" Output Vol.tage
lOUT:": -0.2 mA
Logical "0" Output Voltage
lOUT
Strobe Current
VSTROBE
VSTROBE
5.0
5
0
-5
Power Supply Current
(Both Receivers)
-25V:": V ,N :": 25V
Response Time. t, or t2
T A = 25°C
Vee = 5.0V
Input Ramp Rate:": 10 ns
2.0
V
70
kSl
B.33
-3.57
mA
mA
mA
0.5
V
2.5
V
= 3.5 mA
0.4
=0.4V
= 5.5V
1.0
-5.0!-,A
In
UNITS
V
.03
Note 1. For operating at elevated temperatures, the deVice must be derated
MAX
-2.0
V OUT :::: 2.5V
V ouT :":04V
I nput Current
Open Circuit Input Voltage
CO
CO
N
N
(Note 2)
POSItive I nput Threshold
Voltage (Note 3)
Input Resistance
c
3:
8.0V
±30V
8.0V
25 mA
600 mW
_55 D C to +125°C
O°C to 70°C
-65°C to +150°C
300°C
65
V
1.4
-1.0 rnA
mA
24.0
mA
125
ns
accordance with
the "MaXimum Power DISSipation" curve
Note 2. Mm/Max limits apply across the guaranteed temperature range of _55°C to +125°C for
the DM7822 and OoC to 700 e for the DM8822 unless otherWise specified LikeWise the limits
apply across the guaranteed Vee range of 4.5V to 5.5V for the DM7822 and 475V to 5.25V
for the DM8822 unless otherWise specifIed. TYPical values are given for Vee = S.OV and
TA = 25°C
Note -3. Stnce the EIA RS-232 specification requires the threshold to be between -3V and +3V,
the Immunity limits shown here guarantee 1 volt additIOnal noise Immunity
4-9
N
N
co
co
::E
typical performance
char~cteristics
c
.......
N
N
Threshold Voltage vs Supply Voltage
co
....
::E
650
Response Time
V'i
Input Ramp Time
I nternal Power DISSipatIOn
10,000
VC C ' 5 0 v _ j ±
600
c
;;
E 550
"
450
"
400
~
z
"
''""
'"
iii
:.'!
tl
z
~
a:
350
Q
a:
100
~
~
300
350
300
250
200
150
100
50
250
40
45
55
50
10
60
100
1.000
~~~~~~::'N 11
\
'\.
"
,.... i--'
0 +5 +10 +15 +20 +25
Output Voltage Level.
Vee;; 5V
r-FANOUT'2
~
..
01
~
OUTPUT HIGH
~
"....>
~
~
I_TJ
rr.
-01
-02
45
5.5
-04
I
OM7822
60n
E
z
~
400
~
300
'"
,
\
OM8822
:.'!
,
\
a:
+25V
INPUT
,
OUTPUT
45
65
85
105
125
AMBIENT TEMPERATURE I'CI
ac test circuit
"
OUTPUT
INPUT
50pF
4-10
5
~
Vee'" 5.0V
0.2
OUTPUT LOW-
-
'--
0.1
o
-75
-25
0
25
75
TEMPERATURE lOCI
switching time waveforms
200
25
0.4
DIFFERENTIAL INPUT VOLTAGE IVI
Maximum Power Dissipation
700
I
-t±
~
"~
">
"
I
0.2
-0.2
~
::>
. j'
SUPPLY VOLTAGE IVI
500
125'C25'C -
I
4
"
::::.-
l·r, V
-03
•
,
,,~
IJI •
55'C,
/
INPUT VOLTAGE IVI
Transfer Function
I
I
7
~
r-....
-25 -20 -15 -10 -5
10.000
INPUT RAMP TIME (ns)
SUPPl V VOL TAGE (V)
Threshold Voltage vs Supply Voltage
470n RESISTOR ,_
CONNECTED FROM
PINHO GROUND -
E 400
~ 1.000
500
~
>
TA "25 C
~
125
c
:s:.....
Line Drivers/Receivers
CO
W
o
......
c
:s:CO
DM7830/DM8830 dual differential line driver
g~neral
CO
W
description
o
The DM7830/DM8830 is a dual differential line
driver that also performs the dual four-input NAND
or dual four-input AND function.
normally associated with single-wire transmissions.
features
TTL (Transistor-Transistor-Logic) multiple emitter
inputs allow this line driver to interface with standard TTL or DTL systems. The differential outputs
are balanced and are designed to drive long lengths
of coaxial cable, strip line, or twisted pair transmission lines with characteristic impedances of
50n to 500n. The differential feature of the
output eliminates troublesome ground-loop errors
•
Single 5 volt power supply
•
Diode protected outputs for termination of
positive and negative voltage transients
•
Diode protected inputs to prevent line ringing
•
High Speed
•
Short Circuit Protection
schematic*and connection diagrams
Dual-In-Line and Flat Package
AND
NAND
OUTPUT
OUTPUT
AND
NAND
GND
OUTPUT
OUTPUT
TOPVIEW
Order Number DM7830J or DM8830J
See Package 16
"'-+--t--VUTPUT
Order Number DM8830N
See Package 22
Order Number DM7830W or DM8830W
See Package 27
*2 PER PACKAGE.
typical application
Digital Data Transmission
LINE DRIVER AND RECEIVER
TWISTED PAIR LINE
OUTPUT
tVee IS 4 5V to 5 5V for both the
DM182D and OM7830
tEKactvalue depends on Imelength
*OptlOnal to control response time
STROBE
4-11
o
CW)
absolute maximum ratings
CO
CO
:E
c
.......
7.0V
Vee
) I nput Voltage
5.5V
_55°C to +125°C
o
CW)
Operating Temperature
CO
Storage Temperature
c
Lead Temperature (Soldering, 10 sec)
Output Short Circuit Duration (125°C)
.....
:E
DM7830
DM8830
O°C to 70°C
_65°C to +150 o C
electrical characteristics
300°C
1 second
(Note 1)
PARAMETER
CONDITIONS
Logical "1" Input Voltage
Logical
"a"
MIN
TYP
MAX
UNITS
2.0
V
Input Voltage
V
0.8
Logical "1" Output Voltage
V IN = 0.8V lOUT = -0.8 mA
2.4
Logical "l"Output Voltage
V IN = 0.8V lOUT = 40 mA
1.8
V
3.3
V
Logical
"a" Output Voltage
V IN = 2.0V lOUT = +32 mA
0.2
0.4
V
Logical
"a" Output Voltage
V IN = 2.0V lOUT = +40 mA
0.22
0.5
V
Logical "1" Input Current
V IN = +2.4V
120
I1A
Logical "1" Input Current
V IN = 5.5V
2
mA
V IN = O.4V
4.8
mA
Logical
"a"
Input Current
Vee = 5.0V
T A :: 125°C
Output Short Circuit Current
mA
11
18
mA
TA = 25°C
8
12
ns
Vee = 5.0V
11
18
ns
C L =15pF
8
12
ns
See Figure 1
5
8
ns
12
16
ns
12
16
ns
(Each Driver)
Propagation Delay AN D Gate
tpdl
tpdO
Propagation Delay NAND Gate tpdl
tpdO
Differential Delay tl
}
} Load, lOOn and 5000 pF
Differential Delay t2
See Figure 2
=
:s.
T A ~ +125 0C, Vee"'" +5V ±10%, DM8830 aOc
+5V ±5% unless otherwise stated. TYPical values given are for T A Z 2SoC,
Note 1: Specifications apply for OM7830 -55°C
S
120
V IN = 5.0V
Supply Current
~ TA
?oOe, Vee
Vee = 5.0V.
100
40
"PUTS{:~V'
4
1DOu
&"'pF
V,
.v
v,.
~
'
.
~'v
VA
FIGURE 1.
4-12
FIGURE 2.
-v.
c
3:
typical performance characteristics
o
.......
Output High Voltage (Logical ",")
Vs Output Current
40
~
30
w
"
~
...... r--... I
-.....; t'- ~125C
....... '-
20
>
~
g
g
.......
>
,
10
I
o
o
20
40
60
80
GU~R1NTIEO I LobcAL 1.1" f-
20
?:
2.0
"'~
I.B
w
..
15
11;
10
i-""
.......
;:::
-55 C
Threshold Voltage Vs Temperature
Differential Delay Vs Temperature
]
-..l2n
"W00
i-""
~
'">
~
'"'"
~
c;
j
1.6
INPUT VOLTAGE
...... ~
,...~
12
AN
1,0
B
I-
100 120 140
OUTPUT SOURCE CURRENT (rnA)
GATE ~
~NANOr-GATE
~
Tt
LOG1C~Tt
NTEED
INPUT VOLTAGE
-50 -25 0 25 50 75 100 125
·50 ·25 0 25 50 75 100 125
TEMPERATURE I'CI
TEMPERATURE rCI
Differential Output Voltage
(iVANO - VNANOi)
Vs Differential Output Cur.rent
Output ,Low Voltage
(Logical "0") Vs Output Current
Maximum Power Dissipation
~
800
~
700
J
'"....
~
.,
'"~
- - \~MB~30 r--r-- NM7~30
,
600
500
Q
1\
,
1\
ill
400
~
OUTPUT CURRENT (mAl
300
25
45
65
105
" I'"
=>
-,
85
-55"C ,
'"....>
l\
'"
If
."....
,
~
25'1/'
!;
'"
~
125
20
40
60
125'
80 100 120 140
OUTPUT SINK CURRENT ImAI
AMBIENT TEMPERATURE rCI
Power Dissipation (No Load)
Vs Data Input Frequency
~
.5
;;;
200
'"....
:;
160
z
140
Q
'"
;:::
;;0
ill
c;
'"
ac test circuit
lBO
/
120
100
"'-"l"'--'
80
~
012
511.02
'.
571002005710
DATA INPUT FREOUENCY (MHz)
switching time waveforms
~
"
'-
'5V
'"
'5Y
~"---I
00
00
W
o
~
1.4
c
3:
,,~
v,,_v.-./~"
L
u
•
4-13
N
M
00
00
Line 0 rivers/Receivers
:!
,c
N
M
DM7831/DM8831.DM7832/DM8832 TRI-STATETM line driver
1!2
:!
c
general description
• High impedance output state which allows
many outputs to be connected to a common
bus line.
Through simple logic control, the DM7831/
DM8831, DM7832/DM8832 can be used as either
a quad single-ended line driver or a dual differential
line driver. They are specifically designed for
party line (bus-organized) systems. The DM7832/
DM8832 does not have the Vee clamp diodes
found on the DM7831/DM8831.
mode of operation
To operate as a quad single-ended line driver apply
logical "O"s to the Output Disable pins (to keep
the outputs in the normal low impedance mode)
and apply logical "O'''s to both Differential/
Single·ended Mode Control inputs. All four
channels will then operate independently and no
signal inversion will occur between inputs and
outputs.
The DM7831 & DM7832 are specified for operation over the -55°C to +125°C military temperature range. The DM8831 & DM8832 are specified
for operation over the O°C to +70°C temperature
range.
To operate as a dual differential line driver apply
logical "O"s to the Output Disable pins and apply
at least one logical "1" to the Differential/Singleended Mode Control inputs. The inputs to the A
channels should be connected together and the
inputs to the B channels should be connected toIn this mode the signals applied to the resulting
inputs will pass non·inverted on the A2 and B2 outputs and inverted on the A, and B, outputs.
features
• Series 54174 compatible
• 17 ns propagation delay
low output impedance-high dril,
• Very
capability
• 40 mA sink and source currents
• Gating control to allow either single-ended or
differential operation
When operating in a bus-organized system with
outputs tied directly to outputs of other
(continued I
connection and logic diagram
"A" OUTPUT
ENABLE
OUTPUT
A2
INPUT
A2
OUTPUT
A,
DIFFERENTIALI
INPUT SINGLE ENDED <
A,
MODE CONTROL
Order Number DM7831J, OM8831J,
OM7832J or DM8832J
See Package 17
Order Number OM8831N or DM8832N
S.. Package 23
Order Number DM7831W, OM8831W,
DM7832W or DM8832W
See Package 28
"8" OUTPUT
OUTPUT
INPUT
82
82
ENABLE
OUTl'UT INPUT DIFFERENTIAL! GNO
8,
8,
SINGLE ENDfO
MODE CONTROL
TOP VIEW
truth table
(Shown for A Channels Only)
"A" OUTPUT DISABLE
INPUT A,
OUTPUT A,
INPUT A2
OUTPUT A2
0
0
0
0
Loglca! "1" or
Logical "0"
Same as
Logical" 1" or
Logical "0"
Same as
Input At
0
0
X
1
1
X
Logical" 1" or
Logical "0"
OpPosite of
Input At
LogIcal' 1 0'
Logical "0"
Same as
1
X
X
1
X
x - Don t Care
4-14
DIFFERENTIAL!
SINGLE·ENDED
MODE CONTROL
High
X
X
Impedance
state
X
Input A2
Input A2
High
Impedance
state
c
s::
.....
absolute maxi.mum ratings
CO
Co.)
~
......
7V
55V
55V
-65'C to +150'C
-5SoC to +12SoC
aOc to +70°C
300'C
Supply Voltage
I nput Voltage
Output Voltage
Storage Temperature Range
Operatmg Temperature Range DM7831, OM7832
DM8831, DM8832
Lead Temperature (Soldering, 10 sec )
Time that 2 bus-connected devIces may
be In oPPosite low Impedance states
C
s::CO
CO
Co.)
~
C
s::
.....
lOms
S1multaneously
CO
electrical characteristics
Co.)
(Note 1)
N
......
PARAMETER
CONDITIONS
LogICal "1" Input Voltage
DM7831,DM7832 Vee = 4 5V
DM8831,DM8832 Vee - 4 75V
Logical "0" Input Voltage
DM7831,DM7832 Vee = 4 5V
DM8831,DM8832 Vee - 475V
Logical "T" Output Voltage
DM7831,DM7832 Vee = 4.5V
10=-40mA
10 = -2 mA
DM7831,DM7832 Vee = 5 5V V ,N = 5 5V
DM8831,DM8832 Vee 525V V ,N 24V
Logical "0" Input Current
DM7831,DM7832 Vee = 5 5V
DM8831,DM8832 Vee 525V V ,N = 0.4V
Output Disable Current
DM7831,DM7832 Vee = 55V Vo = 2AV or 0 4V
DM8831,DM8832 Vee - 5.25V
Output Short CirCUit Current DM7831,DM7832 Vee =55V
DM8831,DM8832 Vee 5.25V
18
24
18
24
23
27
25
29
029
029
050
AD
-40
-40
(Note 2)
DM7831,DM7832 Vee = 5,5V
DMS831,DM8832 Vee - 525V
050
-100
65
T A =25°C
liN =-12mA
mA
IlA
-16
mA
40
Il A
120
(Note 2)
mA
90
mA
-15
V
-15
Vcc +l 5
V
V
Vee=50V,
T A = 25'C
13
25
ns
Vee = 5,OV,
TA = 25'C
13
25
ns
Delay from Disable Inputs to High
Impedance State (from Logical "1"
Level), t, H
Vee=50V,
TA = 25'C
6
12
ns
Delay from Disable Inputs to HIgh
Impedance State (from LogIcal "0"
Levell, tOH
Vee=50V,
T A = 25'C
14
22
ns
PropagatIOn Delay from Disable Inputs
to Logical "1" Level (from High
Impedance State), tH 1
Vee = 5.0V,
T A = 25'C
14
22
ns
Propagation Delay from Disable Inputs
to Logical "0" Level (from High
Impedance State), tHO
Vee=50V,
TA = 25'C
18
27
ns
tlal Smgle-ended Mode Control to
N
V
V
V
V
40
1
-1.0
Co.)
V
V
V
V
V
AD
DM7831, DM8831
Output Diode Clamp Voltage DM7832,DM8832 lOUT = -12 mA,Vee = 5 OV,!A = 25°C
DM7831,DM8831 lOUT +12mA,vee 50V,T A 25 C
Outputs,
s::CO
V
10=40mA
10=32mA
10 40 mA
10 = 32 mA
Logical "1" Input Current
Propagation Delay to a Logical "0"
from Inputs A" A 2 , 8,,8 2 Differen-
C
UNITS
CO
DM7831,DM7832
DM8831,DM8832
Vee=50V,
MAX
08
Logical "0" Output Voltage
Input Diode Clamp Voltage
TYP
20
DM8831,DM8832 Vee = 4.75V 10
40 mA
10=-52mA
Supply Current
MIN
tpdQ
Propagation Delay to a Logical "1"
from Inputs A 1 , A 2 , 8,. 8 2 Dlfferen-
tlal Smgle-ended Mode Control to
Outputs, tpd 1
Note 1: Unless otherwise speCified minImax limits apply across the _55°C to +125°C temperature
range for the DM7831, DM7832 and across the
to 70°C temperature range for the DM8831,
DM8832 All tYPleals are given for VCC = 5.0V anq T A = 25'C.
oOe
Note 2: Applies for TA = 125°C only Ohly one output should be shorted at a time
4-15
N
('I)
co
co
::!
mode of operation (cont.)
DM7831/DM8831's, DM7832/DM8832's (Figure
1). all devices except one must be placed in the
"high impedance" state. This is accomplished by
ensuring that a logical "1" is applied to at least
one of the Output Disable pins of each device
which is to be in the "high impedance" state. A
NOR gate was purposely chosen for this function
since it is possible with only two DM5442/
DM7442, 8CD-to-decimal decoders, to decode as
many as 100 DM}831/DM8831's, DM7832/
DM8832's (Figure 2).
The unique device whose Disable inputs receive
two logical "0" levels assumes the normal low
Q
.......
N
('I)
co
,...
::!
Q
"""
('I)
co
co
::!
Q
.......
impedance output state, providing good capacitive
drive capability and waveform Integrity especially
during the transition from the logical "0" to
logical "1" state. The other outputs-in the high
Impedance state-take only a small amount· of
leakage current from the low Impedance outputs.
Smce the logical "1" output current from tne
selected device is 100 times that of a conventional
Series 54174. device (40 mA vs. 400 MA), the
output is easily able to supply that leakage current
for several hundred other DM7831/DM8831's,
DM7832/DM8832's and still have available drive
for the bus line (F igure 3).
"""
('I)
Je
::!
Q
BUS LINES
~
SELECTED AS
DRIVING - - .
DEVICE
GATED INTO
THIRD STATE -
Figure 1
F,gure 2
FOR DRIVING OTHER TTL INPUTS
SELECTED AS
DRIVING DEVICE
GATED INTO
HI IMPEDANCE
STATE
~~t---.
8
8
3
1
8
8
3
2
GATED INTO
HIIMPEOANCE
STATE
Figure 3
4-16
c
3:
~
typical performance characteristics
Propagation Delay from Input
Propagation Delay from Input
to Output (Channell)
25
>
"z
";::
~
~
30
Vee' 5.0V
DIFFERENTIAL/SINGLE.ENDED MODE
CONTROL INPUTS AT LOGICAL "0"
.!
~
to Output (Channell)
J. J.. J J .I.
30
20
tpdO
tpr-
10
25
>
20
~
z
I
15
g
- """'
r--"
~
"
5
~
CONTROL INPUTS AT LOGICAL "1"
I
'Pd,.!.... ~ ~
"
10
o
-75 -50 -25
0
25
....
tpdQ
75 100 125
0
25
50
20
~
10
i'
..... V
-25
50
TEMPERATURE
V
50
J
-
r-tHO
-
15
75 100 125
->--
~~
-75 -50 -25
re)
3:
CO
CO
W
N
Propagation Delay vs Load
Capacitance
~
'Ht
0
25
50
Vec:: SOV
TA::25°C
--
!
>
~
"z
"
75
50
40
5
20
"IE
10
~
J
'I
30
I,.d.
In
IIIII
o
100 125
10
100
1000
re)
TEMPERATURE
10,000
e,I,F)
Total Supply Current vs
Logical "1" Output Voltage ••
Logical "0" Output Voltage ••
Frequency
Source Current
Sink Current
70
Vee'~'5:0V
60
TA '25°C
-j
ALL CHANNELS SWITCHING ,/
"'"
0.5
"""-
......
:--.; ::::.
...... ~
Vrc =tOV
i'
\
l°tBDlBlEI
<40
Veel ,
5.~V
25
25°C~
-55'C
/1
.P
-"-."l
I
i:i,..-;- -55'C
-20
120
[6
~
160
20
40
I
'1}
20
15
DM7832
!-II
100
OM11l11
OMlln
,-...-
§OOCIpF
1--.....-0"
i-
tpd1
.N.UT:
50
1
~1"'14-
I
-50
OUTPUT A,
~
-
10
I I
VOUT (V)
80
ImAI
/ - -.....-0"
~125°C
-2
60
lOUT
INPUT A,
I. I
o;.o.......:...2nl
-40
1/ ~
I\,
80
tial Mode
DM7831
1 1 1
.!
0.2
~
/
Propagation Delay in Differen30
12SoC --.-...
+20
~
-7 ~E~ ~
125'&_/ V
/ l....: 1""_-55'e
lOUT (mA)
lOUT" VOUT High Impedance
Output State
I
0.3
0.1
\
\
40
100
'IMHz)
Vee" 5V
.,
,
~_55°C
~
\
H-tttWlt-H-ttttHt-H++HIII-+tffiHH
10
Vie?Oi0.4
I
~25oe
125°e_
.01
c
75 100 125
60
20 C--
50
...
,
25
Vee'" 5 OV
10
0
0
TEMPERATURE rC)
o
-75 -50 -25
20
-75 -50 -25
Impedance State
'tH
o
W
N
Delay from Disable to Low
Vee" 5.0V
i-
tpd1
75 100 125
30
15
c
3:
~
IE
25
"
10
TEMPERATURE I'C)
30
>
5
=
t=- tpdO
.......
-75 -50 -25
Delay from Disable to High
Impedance State
_tOH
...
20
15 f---=
o
50
TEMPERATURE I'C)
!
>
~
z
~
I
CO
CO
W
25
!
"
I"-
~
I
.......
3:
Ve~'510V
Vee' 5 OV
DifFERENTIAL/SINGLE-ENDED MOUE
15
c
to Output (Channel 2)
30
J J JJ J
...w
.......
Propagation Delay from Input
100
....,j
.."
t---
I:
ov
ov
v, -V2
~
TEMPERATURE ee)
4-17
N
('I)
co
co
switching time waveforms
N
tpdl & tpdO
~
C
.......
('I)
,---------'v
co
,...
~
C
INPUT
INPUT
...
OV----J
DV---.J
('I)
I
I
I
I
.......,.J
co
co
I
tOHI4--
I
n
I
I
~
c
...
INVERTED
.......
D"TI'"'
ACTUAL
OUTPUT
I,.OGICAl ''0''
1
\fOLTAGE
('I)
_ - - - - - " ' " 15V
~
,-----------'V
~
C
INPUT
OV
Inputcharactenstlc
Amplitude = 3 OV
Frequency'" 1.0 MHz, 50% duty cycle
t, '" t1:::; 10 ns (10% to 90%)
tHl
INPUT
~~5V
\-
INPUT
_ _ _ _ _ _ _ _ _ .V
~
I
I
I
-1
__________ .V
'.,
I
OUTPUT
I
I
IS.
OUTPUT
ov
I
ac load circuit
s,
0,
DM7832!
OM8832
l
Swttch 5,
Switch 52
C,
Ipdt
,,-
closed
50 pF
tpdO
closed
closed
50 pF
closed
closed
• 5 pf
"....
,,"""
• 5 pf
'0.
".
'.0
'.'
1K
C
'
closed
0""
*Jjg capacitance.
All dIOdes are FOlo0
4-18
l
s,
50 pF
closed
50 pF
c
Line Drivers/Receivers
:!:
"-oJ
CO
W
en
.......
C
:!:
DM7836/DM8836 quad NOR unified bus receiver
CO
CO
w
en
features
general description
The DM7836/DM8836 are quad 2-lnput receivers
designed for use In bus organized data transmission
systems interconnected by terminated 120Q impedance lines_ The external termination IS intended to be 180Q reSIStor from the bus to the +5V
logic supply together with a 390Q resistor from
the bus to ground_ The design employs a built-in
input hysteresIs providing substantial noise Immunity. Low Input current allows up to 27 drlver/
receiver pairs to utilize a common bus. This receiver has been specifically configured to replace
the SP380 gate pln-for-pln to provide the distinct
advantages of the DM7837 receiver design in eXistIng systems. Performance IS optimized for systems
with bus rISe and fall times ~ lOps.
•
Plug-i n replacement for SP380 gate
•
Low I n put current
Vee = OV (15 pA typ)
•
Built-in input hysteresIs (1 V typ)
with
normal
Vee
or
•
High nOise Immunity (2V typ)
•
Temperature-insensitive input thresholds track
bus logiC levels
•
DTLITTL compatible output
•
Matched, optimized nOise Immunity for "I"
and "0" levels
•
High speed (18 ns typ)
typical application
.5V
'5V
180
IBO
120n Unified Data Bus
--,
390
I
1'14
~7~6
I
I
I
_.J
390
.,..
connection diagram
Dual·ln·line and Flat Package
OUT 3
OUT 4
IN 4A
OU12
OUTl
IN 48
IN JA
IN lB
IN1A
IN 18
IN 2A
14
GND
IN 28
TOP VIEW
Order Number DM7836J
or DM8836J
See Package 16
Order Number DM8836N
See Package 22
Order Number DM7836W
or DM8836W
See Package 27
4-19
absolute maximum ratings
(Note 1)
7.0V
5.5V
600mW
Supply Voltage
Input Voltage
Power Dissipation
Operating temperature range:
DM7836
DM8836
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
_55°C to +125°C
O°C to +70°C
_65°C to +150°C
300°C
electrical characteristics
The following apply for V L 'S Vee'S V H. T L 'S T A 'S T H. unless otherwISe specified INote
PARAMETER
INPUT
OUTPUT
COMMENTS
MIN
21
TYP
MAX
UNIT
High Level Input Threshold
DM7836
DM8836
V TH
V TH
16 mA
16 mA
< 04V
< 04V
1.65
1.80
225
2.25
265
250
V
V
Output> 24V
Output> 24V
0.97
1.05
130
1.30
163
1.55
V
V
Output
Output
Low Level I nput Threshold
DM7836
DM8836
-400~A
V TH
V TH
-400~A
Maximum Input Current
4V
Vee
VH
15
50
~A
Maximum Input Current
4V
Vee" OV
1
50
J.lA
Logic "1" Output Voltage
o 5V
-400 ~A
Logic "0" Output Voltage
4V
16mA
Output Short Circuit Current
o 5V
OV
=
24
Vee - V H
Power Supply Current
4V
Per Package
Input Clamp Diode Voltage
-12 mA
TA
The following apply for Vee
=
V
025
o
25'C
-18
04
V
·55
mA
mA
25
40
-1
-1.5
V
20
18
30
30
ns
ns
5V, T A-= 25 'C unless otherwise speCified
Propagation Delays
Input to Logic "1" Output
Input to Logic "0" Output
I
I
I
Note 3
Note 4
Nota 1: Voltage values are With respect to network ground terminal. Positive current
IS defined as current into the reference pin.
Note 2: For DM7836: V L = 4.5V, VH = 5.5V, TL = _55°C, T H = +125°C.
For DM8836: V L = 4.75V, V H = 5.25V, TL = O°C, TH = +70°C.
Note 3: Fan·out of 10 load, CLOAD = 15 pF total, measured from VIN = 1.3V to VOUT = 1.5V, VIN = OV to 3V pulse.
Nota 4: Fan-out of 10 load, CLOAD
4-20
= 15 pF
total, measured from VIN
= 2.3V to V OUT = 1.5V, VIN = OV to 3V pulse.
c
Line Drivers/Receivers
s:
"COW
"C
......
s:CO
DM7837/DM8837 hex unified bus receiver
00
W
"
general description
features
The DM7837/DM8837 are high speed receivers designed for use in bus organized data transmission
systems Interconnected by terminated 120n Impedance lines. The external termination is intended to be 180[2 reSIStor from the bus to the +5V
logic supply together with a 390[2 resistor from
the bus to ground. The receiver design employs a
built-in Input hysteresIs providing substantial nOise
Immunity. Low input current allows up to 27 driver/receiver pairs to utilize a common bus. Disable
Inputs provide time discriminatIOn. Disable Inputs
and receiver outputs are DTL/TTL compatible.
Performance is optimized for systems with bus
rISe and fall times::::: lOllS.
•
Low receiver Input current for normal V cc or
Vee = OV (1511A typ)
•
Six separate receivers per package
•
Built-in receiver input hysteresis (lV typ)
•
High receiver nOise immunity (2V typ)
•
Temperature insensitive receiver Input thresholds track bus logic levels
•
DTLlTTL compatible disable and output
•
Molded or cavity dual-in-Ilne or flat package
•
High speed
typical application
.5V
'5V
180!1
120n Unified Data Bus
--, r- --,
390!1
3901]
I
I
I
I
_...J
I I
I I
I I
I
_...1
connection diagram
Dual·ln·Line and Flat Package
Vee
IN 1
OUT 1
IN 2
OUT 2
IN 3
IN 4
OUT 4
IN 5
OUT 5
IN 6
OU16
OUT 3
DISABLE A
DISABLE 8
GNO
TOP VIEW
Order Number DM7837J
or DM8837J
See Packago 17
Order Number DM8837N
So. Package 23
Order Number DM7837W
or DM8837W
See Package 28
4-21
absolute maximum ratings
Supply Voltage
Input Voltage
Power Dissipation
Operating Temperature Range
DM7837
DM8837
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
(Note 1)
7V
5.5V
600mW ....
_55.°C; to +125°C
O°C to +70°C
_65°C to +150°C .....
300°C i .
electrical characteristics
The following apply for V L ~ V cc ~ V H, T L ~ T A ~ T H, unless otherwise specified (Note 2)
RECEIVER
INPUT
PARAMETER
DISABLE
INPUT
OUTPUT
COMMENTS
MIN
TYP
MAX
UNIT
165
225
265
V
16 mA
< 0 4V
Output < 0 4V
180
225
250
V
08V
-400 rnA
Output> 2 4V
0.97
130
163
V
08V
-400 mA
Output> 2 4V
1.05
130
155
V
High Level Receiver Threshold
DM7837
V'H
08V
l6mA
High Level Receiver Threshold
DM8837
V'H
08V
Low Level Receiver Threshold
DM7837
V'H
low Level Receiver Threshold
DM8837
V'H
Output
Maximum Receiver Input Current
4V
Vee· V H
150
500
"A
Maximum Receiver Input Current
4V
Vee
OV
10
500
"A
Logic "1" Input Voltage
Disable
o 5V
V"
16 mA
Output
Logic "0" Input Voltage
Disable
05V
V"
-400 pA
Output> 24V
08
V
Logic "1" Output Voltage
o 5V
4V
o 8V
o 8V
-400 IJA
Logic "0" Output Voltage
04
V
Logic "1" Input Current
Logic "1" Input Current
Disable
Disable
< 0 4V
V
025
24V
800
"A
55V
20
mA
4V
04V
o 5V
OV
Power Supply Current
4V
OV
Per Package
Input Clamp Diode
-12 mA
-t2 mA
TA '" 2S"C
Disable
V
24
l6mA
Output Short CircUit Current
Logic "0" Input Current
20
OV
Vee'" V H
-32
mA
-550
mA
45.0
600
mA
-10
-15
V
ns
-180
The follOWing apply for Vee = 5V, T A" 25"C unless otherWise specified
Propagation Delays
Receiver Input to Logic "1" Output
OV
Note 3
20
30
"0" Output
OV
Note 4
18
30
ns
Receiver Input to Logic
Olsable Input to Logic "1" Output
OV
Note S
9
15
ns
Olsable Input to LogIc "0" Output
OV
Note 5
4
10
ns
Note 1: Voltage values are with respect to network ground terminal. Positive current is defined as current into the referenced pin.
Note 2: For DM7837: V L = 4.5V, V H = 5.5V, TL = _55°C, TH = +125°C
For DM8837: VL = 4.75V, VH = 5.25V, TL = O°C, TH = +70°C
Note 3: Fan·out of 10 load, CLOAD = 15 pF total. Measured from V,N = 1.3V to VOUT = 1.5V, V,N = OV to 3V pulse.
Note 4: Fan-out of 10 load, CLOAD = 15 pF total. Measured from V,N = 2.3V to VOUT = 1.5V, V,N = OV to 3V pulse.
Not. 5: Fan-out of 10 load, CLO AD = 15 pF total. Measured from V1N = 1.5V to VOUT = 1.5V, V,N = OV to 3V pulse.
4-22
o
3:
Line Drivers IReceivers
CO
""'"
to)
CO
........
o
DM7838/DM8838 quad unified"bus transceiver
3:
CO
CO
~·features
general description
to)
The DM7838/DM8838 are quad high speed drivers!'
receivers designed for use in bus organized datatransmission systems interconnected by termi·
nated 120n Impedance lines. The external termi·
nation is intended to be a 180n resistor from the
bus to the +5V logic supply together with a 390n
resistor from the bus to ground. The bus can be
terminated at one or both ends. Low bus pin cur·
rent allows up to 27 driver/receiver pairs to utilize
a common bus. The bus loading is unchanged
when Vee = OV. The receivers Incorporate hystere·
SIS to greatly enhance bus nOise immunity. One
two·lnput NOR gate is included tq disable all
drivers In a package simultaneously. Receiver per·
formance IS optimized for systems with bus rISe
and fall times::; 10}.1s.
•
4 totally separate driver/receiver
package
pairs per
•
•
1 V typical receiver Input hysteresIs
Receiver hysteresis independent of receiver
output load
•
Guaranteed minimum bus noise Immunity of
1.3V, 2V typo
• Temperature·insensitive receiver thresholds
track bus logic levels
•
•
•
•
20}.1A typical bus terminal current with normal
V cc or with Vee = OV
Open collector driver output allows wlre·OR
connection
High speed
Series 74 TTL compatible driver and disable
Inputs and receiver outputs
typical application
'5V
'5V
IBO!!
120S! Unified Data Bus
-, r-
390~,
I I
I I
I I
I
_.J
-,
390i,
I
I
I
I
_...1
connection diagram
Dual' In-Une and Flat Package
Vee
BUS1
IN I
~Ull
BUS2
IN2
BUS 3
IN J
OU13
BUS 4
IN 4
OUT 4
OU12 DISABLE A
DISABLE B GND
TOP VIEW
Order Number DM7838J
or DM8838J
See Package 17
Order Number DM7838W
or DM8838W
See Package 28
Order Number DM8838N
See Package 23
4-23
CO
co
co
co
:E
('t)
absolute maximum ratings
Supply Voltage
Input and Output Voltage
Operating Temperature Range
DM7B3B
DMBB3B
7V
55V
600mW
c
Power
co
co
":E
electrical characteristics
DISSipation
-:55 C to +125 C
OCto+70C
-65'C to +150'C
300 C
Storage Temperature Range
Lead Tpmperature (Soldering, 10 sec]
"'('t)
DM7838/DM8838
c
The following apply for V L ~ Vee S V H' T L S:r A S T H unless otherWise specified {Note 21
PARAMETER
DISABLE
INPUT
BUS
PIN
RECEIVER
OUTPUT
COMMENTS
2V
Logic "1" Input
Voltage
DRIVER
INPUT
MIN
TYP
MAX
20
UNIT
V
Disable
Logic "0" Input
Voltage
Disable
2V
50 mA
Logic "1" Input
Voltage
Driver
o SV
50mA
Logic "0" Input
o SV
4V
Voltage
'" 'sus <'
Bus"":: 0 7V
Bu~
os
0 7V
<
20
V
V
100!J.A
OB
V
Driver
High Level RecelvPI
Thlf".hold OM7838
o BV
V TH
16 mA
High Level Recelvel
Thte<;hold DM8838
OSV
V TH
1611lA
Low Level Receiver
o BV
Tht e~hold
165
2 25
265
v
Recelvel output
1 BO
2 25
250
V
097
1 30
163
V
105
1 30
155
V
< 0 4V
R('c{'IVCI output
OM 7838
'>
o BV
Low Level Receive.
Threshold DM8838
Logic "1" Input
output
RpC~IVE'1
< 04V
-400 "A
2 4V
Recelvel output
>24V
55V
55V
24V
24V
40
"A
Logic "0" Input
Current
Disable
and Driver
04V
04V
-16
Il1A
Maximum Bus
Cunent
o SV
o SV
4V
Maximum Bus
Current
o BV
o SV
4V
Low Level Bus
Voltage
o BV
2V
Logic ''1'' Output
Voltage
Receiver
o SV
o SV
o 5V
Logic "0" Output
Voltage
Receiver
OBV
o SV
4V
16mA
Output Short Circuit
Current
Receiver
o BV
o SV
o 5V
OV
Current
InA
Disable
and Driver
Logic "1" Input
Current Disable
and Driver
20
Vee =- V H
04
50mA
100
"A
100
"A
07
24
-400"A
V
04
025
-lB
mA
mA
50
70
TA
25°C
-1
-15
Propagation Delays
Disable to Bus" 1"
Note 3
19
30
Disable to Bus "0"
Note 3
15
23
Driver Input to Bus "1"
Note 3
17
25
Driver Input to Bus "0"
Note 3
Bus to Lagle "1"
Receiver Output
Note 4
20
30
Bus to LogiC "a"
Receiver Output
Note
5
lS
30
Input Diode Clamp
Voltage
OV
2V
-12mA
-12 mA
-12 mA
=
The follOWing apply for Vee'" 5V, T A'" 25°C unless otherwise speCified
Voltage values are With respect to network ground terminal POSitive current 15 defined as current Into the referenced
Note 2:
For DM783S. VL = 4.5V, VH = 5.5V, TL = -55 c C, TH = +125'C
For OM8838' VL = 4.75V, VH = 5.25V, TL = O°C, TH = +70' C
91H from bus pin to VCC and 20an from bus pin to ground, CLOAD:= 15 pF total Measured from VIN '" 1.5V to
1.5V, VIN = OV to 3.0V pulse.
Fan-out of 10 load, CLOAD '" 15 pF total Measured from VI N == 1.3V to VOUT '" 1 5V, VIN '" OV to 3.0V pulse
Fan-out of 10 load, CLOAD '" 15 pF total Measured from VIN '" 2.3V to VOUT '" 1 5V, VIN =- OV to 3 OV pulse.
Note 4:
Note 5:
4-24
15
Note 1:
pin.
Note 3:
VBUS'"
V
-55
Per Package
Supply Current
V
V
r-
...3:
Line 0 rivers/Receivers
~
00
00
LM1488 quad line driver
general description
features
The LM 1488 is a quad line driver which converts
standard DTUTTL input logic levels through: one
stage of inversion to output levels which meet·EIA
Standard No. RS-232C and CCITT Recommendation V. 24.
• Current limited output
± 10 mA typ
• Power-off source impedance
300n min
• Simple slew rate control with external capacitor
• Flexible operating supply·range
• Inputs are DTUTTL compatible
schematic and connection diagrams
r-------~--------~--~----~,.
Dual-In-Line Package
V'
V-
GN.
"
TQPVIEW
Order Number LM1488J
See Package 16
1/4CIRtUIT
typical applications
RS232C Data Transmission
T2L/DTL
-..... -,k)o---t
1/4LM1489/
1/4 LM1488
--""L._~
LM1480A
T2L/DTL
_... .",.-,
P----I-------r-----t--·D'O--:::L_ .p- --
T2L/DTL
T2l/0TL
,-~--
-_.:(-1:==
",_.J--INTERFACE DATA
TERMINAL EOUIPMENT
--<~
.. - ,_.J---
SIGNAL GROUND
MODEM
"OPTIONAL fOR NOISE FILTERING
4-25
00
00
~
~
~
....
absolute maximum ratings
(Note 1)
Supply Voltage
v+
v-
(,
Input Voltage (V IN )
Output Voltage
Power Derating (Note 2)
(Package Limitation, J Package)
Derating above T A = +25°C (1/0 JA )
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
-15V :S:;,V IN
Input Current
LogiC "1"
I "put Current
High Level
Output Voltage
(Note 3)
CONDITIONS
PARAMETER
h
1000 mW"o, II. '
6.7mwfc,,,., '
O°C to +75°C .
_65°C to +175°C
300°C
electrical characteristics
LogiC "0"
+15V
-15V, ;':
:S 7 .ov., ,
±15V!"'i' (
MIN
V ,N = OV
TYP
MAX
-1.0
-1.3
O1A
10.0
fJA
.005
V,N = +5.0V
RL = 30kH
V,N = 0 SV
lV'=9OV
V- = -9.0V
V' = 13.2V
V- = -13.2V
{ V' = 9.0V
V- = -9.0V
UNITS
6.0
7.0
V
9.0
10.5
V
-6.0
-6.S
V
-9.0
-10.5
V
Low Level
Output Voltage
RL = 3.0kH
V ,N = 1.9V
High Level Output
V OUT = OV
V,N=OSV
-6.0
-100
-12.0
rnA
V OUT = OV
V,N = 1.9V
6.0
10.0
12.0
rnA
Short-Circuit Current
Low Level Output
Short-ClrcUlt Current
Output ReSistance
V' = V- = OV
V OUT = ±2V
V ,N = 1.9V
Positive Supply
Current
IOutput Open)
V,N = O.SV
V,N = 1.9V
Negative Supply
Current
IOutput Open)
V ,N = O.BV
V' = 13.2V
V- = -13 2V
I
I
I
V' = 9.0V. V- = -9.0V
V' = 12V, V- = -12V
V' = 15V. V- = -15V
15.0
19.0
25.0
20.0
25.0
34.0
rnA
rnA
rnA
V' = 9.0V, V- = -9.0V
V' = 12V, V- = -12V
V' = 15V, V- = -15V
4.5
5.5
S.O
6.0
7.0
12.0
rnA
rnA
rnA
V' = 9.0V, V- = -9.0V
V+ = 12V, V- = -12V
V+ = 15V, V- = -15V
-13.0
-IS.0
-25.0
-17.0
-23.0
-34.0
rnA
rnA
rnA
-1.0
-1.0
-2.5
rnA
rnA
rnA
\ V+ = 9.0V, V- = -9.0V
V+= 12V, V-=-12V
V+= 15V, V-=-15V
;
-.001
-.001
-.01
252
444
333
576
rnW
rnW
CL =15pF,T,,=25°C
230
350
ns
Power Dissipation
V+ = 9.0V, V- = -9.0V
V+ = 12V, V- = -12V
Propagation Delay
to "1" It pd ,)
RL =3.0kn
Propagation Delay
H
300
RL = 3.0 kn
CL = 15pF, T" = 25°C
70
175
ns
Rise Time (t r)
RL =3.0kn
CL = 15 pF, T" = 25°C
75
100
ns
Fall Time It,)
RL =3.0kn
CL = 15 pF , T" = 25°C
40
75
ns
to "0" ItpdO)
Note 1: Voltage values shown are with respect to network ground terminal. Positive current is defined as current into the
referenced pin.
Note 2: The maX1mum junction temperature of the LM14SS is 150°C. For operating at elevated temperatures the cavity
Dual-In-Line Package (J) must be derated based on a thermal resistance of 85°C/W, junction to ambient.
Note 3: These specifications apply for V+ = +9.0V ± 1%, V- = -9.0V ± 1%, TA = O°C to +75°C unless otherwISe noted. All
typicals are for V+ = 9.0V, V- = -9.0V, and T A = 25°C.
applications
RS232C specifies that the output slew rate must
not exceed 30V per microsecond. Using the worst
case output short circuit current of 12 mA in the
above equation, calculations result In a required
capacitor of 400 pF connected to each output.
By connecting a capacitor to each driver output
the slew rate can be controlled utilIZing ,the output
current limiting characteristics of the LM1488.
For a set slew rate the appropriate capacitor value
may be calculated uSing the following relationship,
C = Isc (llT/llV)
where C IS the required capacitor, Isc IS the short
CirCU It cu rrent value, and II VIII T IS the slew rate.
typical applications (con't)
DTL/TTL·to·HTL Translator
DTLlTTL·to·MOS Translator
+12V
+12V
OTlfTTL
OIl/TTL
INPUT
INPUT
-12V
DTLlTTL·to·RTL Translator
t12V
OH/TTL
Rll OUTPUT
INPUT
-0 1VTO+3'1V
-12V
ac load circuit
+30V
switching time waveforms
V'"iT
r-----"\-------
30V
_____ ,v
vo
-::-" 1"15,"
",
t,andtt are measured between
10%and 90% of the output
waveform
·CLmcludesprobeandllgcapacltance
typical performance characteristics
Output Voltage and
15
;< 12
.§
...
~
~
:0
~
~
t-~
Current~Limiting
V+=12V
V-=-12V
"'-!_
V+::9V
V-=-9V
9
0
-3
41
-9
2-12
-15
\
1\
\1\
..l
Characteristics
'\~~
\
\
,~,
-16 -12
-8
-4
\
8
12
16
V o . OUTPUT VOLTAGE (V)
4-27
«en
...::Ecooe:t
Line Drivers/Receivers
-'
"enco
LM1489/LM1489A quad line receiver
...oe:t
::E
-'
general description
features
The LM1489/LM1489A are quad line receivers
designed to interface data terminal equ ipment with
data communications equipment. They are constructed on a single monolithic silicon chip. These
devices satisfy the specifications of EIA standard
No. RS232C. The LM1489/LM1489A meet and
exceed the specifications of MC 1489/MC 1489A
and are pin-for-pin replacements. The LM 1489/
LM 1489Aare available in 14 lead ceramic dualin-line package.
• -Four totally separate receivers per package
•
Programmable threshold
•
Built-in input threshold hysteresis
•
"Fail safe" operating mode
•
I nputs withstand ±30V
schematic and connection diagrams
Dual-In-line Package
,
ResPO~SE
,
,
INPUT CONTROlOUTPUl
IIESf'ONSE
IN~IH CON~ROL OUT~UT
(1/4 Of UNIT SHOWN!
"
2K
OUTPUT
INPUT
D---""V'Y--t---.....- - ;
LM1489:
LM1489A:
AF '" 10K
RF '" 2K
Order Number LM1489J or LMI489AJ
See Package 16
ac test circuit and voltage waveforms
RESPONSE CONTROL
~ OPEN
, ._ _ _ _- . . - -_ _ _ _ _ ]V
OUTPUT
Vee
INPUT
--/
Jt-----f.J'
'-----ov
--~'"""r
J
lS"f
INI:LUOINfl
JIG AND PROBE
OUTPUT
~
typical applications
T"L10Tt
:=t=)..·
T'LlOTL
»--t---r--i---C~-=:~=)~-INTERCONNECTING
TtL/OlL
CABLE
T'l/on
--·~(=~::-O
en
MAX
Supply Voltage Vee +
Supply Voltage Vee
o
LM75107A, LM75207
LM7510BA, LM7520B
LM363, LM363A
LM5510BA,
CD
::::!.
CD
III
typical applications
Line Receiver Used in a
,Party-Line or Data-Sus System
lWllfED,AlR
TRA_ON
""
"'.
LlIERECEMRSARE
OOlll7fLMmli
OALllla
LlNEDRIVERlARE
1.Mi/ii11ll/LMN'ti
OROMIDI
DRIVERS
Line Receiver Used in MOS Memory System
nLT8M011
WlnU_IlEMaRYARRAV
MltlTOnLRECEIVIRSllJIPUII).
ORIVERI
4·31
schematic diagrams
LM55107Afl:M75107A. LM75207
LM5510SA:/LM7510BA.
LM7520B
•
"~'f"-~'
vcc+O--...__<.....- -....-
....-
~
. . .--<~-----1
.....- -.....---.-- --- --,
, I
~
9"
12D~
16K
,
.l',-----t
900
OK
~~
as,
j.. .... -~
t'~.. -.
I
I
,
~4K
I
INPUTB
INPUT A
I
:
'
I
OUTPUT
o---....-...J
....-~--oG'O
t---~_++----1~
3K
JK
...'----+-""---0
-'---....-----0
STROBE G
STROBE S
vcc-o--_"'___"'_~--""-----....J
Nota 1: 1/2 01 the dual cm:ult IS shown.
Note 2: *Indtcates connections common to second half of dual ClfeLlit.
Note 3' Componenn shown With dash hnesere apphcable to the LM55101A, LM75101A, and LM15201 only.
LM 163/LM363. LM363A
cc o--...--<.....- -....- ....- ...--<.....-----1~---<.....- -....---__,
V +
120
900
180
--....,H
9Oo ...
OK
INPUT B
OUTPUT
INPUT A 0---1---'
...--~-oG'O
t---~~+-----1~
JK
L . . . . - - -...- - - -....OSTR08E
JK
G
85K
OK
DISABLE 0
-----...J
vcc-o---....- - -...-~--....
Note 1 t/2 of the dual CIrCUit IS shown.
Note 2 *Indlcates connectlons common to second half of dual CIrCUit
1K
4-32
...3C
LM55107A/LM75107A. LM 5 5108A/LM75108A
dc electrical characteristics (T MIN ~TA ~TMAX)
.
PARAMETER
CONDITIONS '.. c''''
'~';.!
~'O",/LM75107A
MIN
Into lA, lB. 2Aor2B (lIH)
Vee +;:. MaM, Vee - '" Max,
VIC'" 0 5V. VIC" -3V to 3V
i
Low Level Input Current
Into lA.1B.2Aor2B (I,Ll
Vee + '" Max. Vee - '" Max.
VIC =-2V, VIC =-3Vto3V
i
High Level Input Current
Into 1Gor2G (lIH)
Vee +;:. Max. Vee -
High Level Input Current
Vee T = Max. Vee -,. Max,
Into 1Gor2G (lIH)
VIH(S) '" Max Vee:-
Low Level Input Current
Vee + = Max, V cc - '" Max,
Into 1G or 2G (IlL)
VILIS) '" Q4V
High Level Input Current
V IHts) = 24V
.....
LIMITS
/ '
\'~}~
U1
U1
....
0
LM55108A/LM75108A
TVP
MAX
30
75
=Max.,. .~
)0
MIN
TVP
MAX
30
75
U1
~A
-10
-10
~A
40
40
~A
I
I
mA
-16
-16
mA
U1
....
0
CD
)0
en
CD
~.
CD
VI
High Level Input Current
Into S IIIH)
Vee + '" Max, Vee -;:. Max,
V IHts) '" 2 4V
80
SO
~A
High Level Input Current
IntoStl'H)
Vee + '" Max. Vee - = Max,
V IH1S) = Max Vcc+
2
2
mA
Low Level Input Current
IntoS (lId
Vee +:: Max, Vee - '" Max,
VILIS) '" 04V
-32
-32
mA
High Level Output
Voltage (V OH )
Vee + '" Mm, V ee - '" Mm,
ILOAO ""-4~A, VIO =25mV,
Vie'"' -3V to 3V
Low LevtN Output
Voltage IVo L)
Vee +::: Min, V ee -" Min,
ISINK '" 16 mA, VIC'" -25 mV,
Vie = -3V to 3V
High Level Output
Current UOH )
Vee +,.. Min, Vee - '" Min
VOH = Max Vee +
Short CirCUit Output
Current 1I0si
Vee + = Max, Vee - = Max
High Logie Level Supply
Current from Vee (teeH +1
Vee + '" Max, Vee - = Max,
VIC =25 mV, TA = 25°C
18
High LogiC Level Supply
Current from Vee (lceH-)
V ee +'" Max, V ee -= Max,
VIC::: 25 mV, TA '" 25°C
--84
Input Clamp Voltage on
GorS(VII
Vee + '" Min, Vc;e - '" Min,
liN =-12mA, T A ::: 25°C
-1
ac switching characteristics
...
......
3C
UNITS
24
V
04
04
250
-18
-70
(Vee + = 5V.
18
-15
--84
-1
-15
=
~A
mA
30
vec -
V
-5V.
TA
=
30
mA
-15
mA
-15
V
25°C)
LIMITS
PARAMETER
CONDITIONS
LM55107A/LM15107A
MIN
Propagation Delay Time, Low to High
Level, From Differential Inputs A and
BtoOutput (Note 1) (tPLHtCjl
RL '" 3900., CL '" 50 pF
Propagation Delay Time, Low to High
Level, From Differential Inputs A and
Bto Output (Note 1) (tPLHtO)i
AL '" 3900., CL '" 15 pF
Propagation Delay Time, High to Low
Level, From Differential Inputs A and
B to Output (Note 1) (tpHL(od
RL '" 390n, CL = 50 pF
Propagation Delay Time, High to Low
Level, From Differential Inputs A and
B to OutPUt (Note 11 (tpHLtOli
RL ::: 390n, CL = 15 pF
Propagation Delay Time, Low to High
Level. From Strobe Input G or S to
Output (tpI.Hts)1
RL = 390n, Cl. = 50 pF
Propagation Delay Time, Low to High
Level, From Strobe Input G or S to
Output (tPLH (5) I
R ... = 390n, Cl. = 15 pF
Propagation Delay Time, High to Low
Level, From Strobe Input G or S to
Output (tpHLtS}i
RL = 390n, CL = 50 pF
Propagation Delay Time, High to Low
Level. From Stlobe Input G or 5 to
Output (tPHl.tsd
AI. "390n, Cl. = 15 pF
TVP
MAX
17
25
LM55108A/LM7510BA
MIN
TVP
ns
19
17
ns
ns
25
ns
ns
15
13
8
25
25
19
10
UNITS
MAX
20
ns
ns
15
13
20
ns
Note 1: Different,al input is +100 mV to -100 mV pulse. Delays read from 0 mV on input to 1.5V on output.
4·33
LM75207, LM75208
dc electrical characteristics
(O°C::;TA ::;+70°C)
LIMITS
PARAMETER
CONDITIONS
. ._._. i
High Level Input Current
IntolA,lB.2Aor2B litH)
Vee + = Max. Vee -"' Max,
VIO "0 5V, VIC'" -3V to 3V
Low Level Input Current
Vee t
Into lA, lB,2Aor2B (IlL)
Max. V ee - =Max,
V to '" -2V. VIC" -3V to 3V
High Level Input Current
Vee + '" Max, V ee - =Max.
Into lG or 2G (I,H)
VIHISI "2 4V
High Level Input Current
Vee + '" Max, Vee ~ '" Max,
V 1H1S ) '" Max Vee
Into lG or 2G (I tH
)
Vee + '" Max, Vee - '" Max,
Into lG or 2G
VILISI '"
(IlL)
Into S
MIN
0
TYP
,::)2
"
Low Level Input Current
High Level I nput CUI rent
lM76207
E~I\I
~,j
•
"
(lIH)
4V
V cc + '" Max, V cc - '" Max,
V 1H1S) '" Max Vc c +
Low Level Input Current
Into S (IlL)
Vee + '" Max, V cc -" Max,
High Level Output
Voltage (V OH )
Low Level Output
Voltage (VOL)
Vec + = Mm, Vee - = Min,
ISINK '" 16 mA, Vm =-10 mV,
Vie'" -3V to 3V
High Level Output
Current (lOH)
Vee + = Mm, Ve~- = Min
V OH '" Max Vee
Short Circuit Output
Current (los)
Vee + = Max, V ee - '" Max
High logic Level Supply
Current From Vce (lecH +)
Input Clamp Voltage on
GorS(V.!
Vee + '" Mm, Vee - '" Mm,
liN'" -12 mA, T A '" 25°C
75
"A
-'0
-'0
"A
40
40
"A
mA
-'6
-, 6
mA
80
80
"A
-32
mA
V
04
04
250
-70
-'8
,8
Vce + = Max, Vee - '" Max,
ac switching characteristics
30
75
24
VIO '" 10 mV, TA = 25°C
V IO '" 10 mV, TA '" 25°C
MAX
-32
Vce + '" Max, V ee - '" Max,
High logic level Supply
Current From Vee (l eeH -)
UNITS
TYP
mA
VILIS> = 04V
V ec +'" Mm,Vcc-"'Mm,
I LOAD = -400J.lA, V ID = 10 mV,
VIC = -3V t<;>, 3V
MIN
",\~
Vee + '" Max. Vee - '" Max,
V 1H1S) '" 2 4V
High Level Input Current
Into S OIH)
lM7520B
MAX
-84
-,
V
"A
mA
30
'8
-84
-'5
-,
-15
30
mA
-'5
mA
-15
V
(Vcc+=5V,Vcc-=-5V,TA=25°C)
LIMITS
PARAMETER
CONDITIONS
lM75207
MIN
Propagation Delay Time, Low to High
Level, From Differential Inputs A and
B to Output (Note 1) (tPLH (0))
RL '" 470n, CL '" 15 pF
Propagation Delay Time, low to High
level, From D'tfferentlallnputs A and
B to Output (Note 1) (tPLH (0»)
RL = 470n, CL '" 15 pF
Propagation Delay Time, High to low
level, From Differential Inputs A and
RL '" 470n, CL = 15 pF
TYP
lM7520B
MAX
MIN
TYP
UNITS
MAX
35
35
20
B to output (Note 1) (tPHLIOd
Propagation Delay Time, High to low
level, From Differential Inputs A and
B to Output (Note 1) (tpHL(D)1
RL '" 4700, CL '" 15 pF
PropagatIOn Delay Time, Low to High
Level, From Strobe Input G or S to
Output (tPLH (S))
RL = 4700, CL '" 15 pF
Propagation Delay Time, low to High
level, From Strobe Input G or S to
Output (tPLH (S»)
RL = 470n, CL = 15 pF
Propagation Delay Time, High to low
level. From Strobe Input G or S to
Output (tPH L (S))
RL = 470n, C L = 15 pF
Propagation Delay Time, High to low
level, From Strobe Input G or S to
Output (tPH L (S))
RL = 470n, C L = 15 pF
20
17
17
'7
Note 1: Differential input is +10 mV to -30 mV pulse. Delays read from 0 mV on input to 1.5V on output.
4-34
17
ns
r-
3:
U1
U1
LM163/LM363
dc electrical characteristics
...
(TMIN :STA :STMAX )
0
....,
LlMITS~
CONDITIONS
PARAMETER
LM1631LM363
,
MIN
Vee + '" Max, V cc - '" Max.
VIO '" 0 5V. VIC'" -3V to JV
High Level Input Current
Into lA.1B,2Aor2B (lIH)
l>
"r-
UNITS
TVP
MAX
30
75
pA
U1
U1
-10
pA
0
3:
...
I
Vee + '" Max, V cc - '" Max;'
VIO '" -2V, VIC'" -3V to 3V
Low Level Input Current
Into lA, lB,2Aor28 (IlL)
High Level I nput Current
Vee + '" Max, V cc - '" MaxI
Into 1G, 2G or 0
V1HIS 1 -=
(lIH)
2 4V
Into lG, 2G or 0 (1 1H I
V cc + '" Max, Vcc~ '" Max,
V 1H1S ):= Max Vee
Low level Input Current
Vee + '" Max, V cc - '" Max.
Into 0
V 1L1m '" 0 4V
High Level Input Current
(IILI
00
pA
l>
1
mA
en
-16
mA
CD
CD
~
Vee + '" Max, V cc - '" Max.
Low Level Input Current
Into lG or 2G (IlL)
40
-40
en
pA
V1H{OI '" 2V, VILIGI '" 0 4V
Low Level Input Current
Vee + '" Max, V cc - '" Max,
Into lG or 2G (IlL)
V 1L10l = 0 8V, VILIGI '" 0 4V
-16
mA
Vee + '" Min, Vec - '" Mm.
High Level Output
Voltage (V OH )
I LOAD
:=
-2 mA, V 10 = 25 mV.,
V I LID) '" a
av, VIC
24
V
-3V to 3V
:=
Vee + '" Min, Vee - '" Min,
Low Level Output
04
ISINK '" 16mA. V 10 =-25mV,
Voltage (Vod
V 1L10) '" 0
(100 ~
Vee + = Max, V cc -"" MaK,
VIH10I '" 2V, V OUT '" 2 4V
Output Disable Current
Vee +:= Max, V ec - = Max,
(100)
V IH10 ) = 2V, V OUT
Short CirCUit Output
Current (los)
Vec+"'Max,V1L(D)
Vcc-=Max
High Logic Level Supply
Vee +:= Max, V cc - '" Max,
Current From Vee + (lceH +)
VIO =25mV, TA : 25"C
High Logic Level Supply
Vee + = Max, V ec - : Max,
Current From V ee - (tCCH-)
VIO
Input Clamp Voltage on
Gor 0 (VI)
Vcc+=Mln,Vcc-=Mm,
Output Olsable Current
:=
V
av, Vie =-3V to 3V
:=
a 4V
",oav,
-18
28
-84
25 mY, T A = 25"C
-1
liN'" -12 mA, T A'" 25"C
40
pA
-40
pA
-70
mA
40
mA
-15
mA
-15
V
(Vcc+~5V. Vcc-~-5V. TA ~25°C)
ac switching characteristics
LIMITS
PARAMETER
LM1631LM363
CONDITIONS
MIN
UNITS
TVP
MAX
Propagation Delay Time, Low to High
Level, Flom Differential Inputs A and
RL
:=
390n, C L
:=
50 pF
17
25
"'
RL
:=
39an, C L
:=
50 pF
17
25
ns
RL "390n, C L
:=
50 pF
10
15
ns
= 390£1, C L
~
50 pF
8
15
ns
RL " 39m~, C L "5 pF
20
ns
RL '" 39an, C L " 5 pF
30
ns
R t '" 1k to OV, C L " 50 pF
25
ns
RL " 390n C t " 50 pF
25
ns
B to Output (Note 1) (tpLHIO))
PIOp
5
S
",
~
3.6
J)5.~V
3.0
NO LOAD
TA =+25 C
Q
2.5
2.0
VT _
VT •
1.5
1.0
0.5
0.2 0.40.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
V, - INPUT VOLTAGE (VI
typical applications
75
Single·Ended Party Line Circuits
INPU~
V'H~
VT+
,VT_
v"
OUTPUT
vaHYL
V"
THE HIGH GAIN AND BUILTIN HYSTERESIS OF THE LM55122!
LM75122 LINE RECEIVERS ENABLE THEM TO BE USED AS
SCHMITT TRIGGERS IN SQUARING UP PULSES
Pulse Squaring
4·44
r-
s::
....
Line 0 rivers/Receivers
~
N
W
LM75123 dual line driver
general description
features
The LM75123 is a monolithic dual line driver
designed specifically to meet the I/O interface
specifications for IBM System 360. It is compatible with standard TIL logic and supply voltage
levels.
• Meet IBM System 360 I/O interface specifications for digital data transmission over 500 to
500n coaxial cable, strip line, or terminated
pair transmission lines
• TIL compatible with single 5.0V supply
The low-impedance emitter-follower outputs of
the LM75123 enable driving terminated low impedance lines. In addition the outputs are uncommited allowing two or more drivers to drive
the same line.
• 3.11V output at IOH = -59.3 mA
• Open emitter-follower output structure for
party-line operation
• Short circuit protection
• AND-OR logic configuration
Output short-circuit protection is incorporated
to tum off the output when, the output voltage
drops below approximately 1.5V.
• Plug-in replacement for the SN75123 and the
8T23
connection diagram
typical performance
characteristics
Dual-In-Line Package
Vee
16
2F
2E
1.
2D
2C
28
2>
2V
Output Current VI Output Volt_
14
-300
Vee·
oS
.
S
..
-150
.s
-50
~
§
u
-2DD
'\
!;
-100
I
1.
lC
lD
IE
TOP VIEW
IF
tV
,
I
\
f--
o
18
5,~V
VIH "'2.0V
TA "'25°C
;( -250
051 D 1,5 2.0253,03.54,04550
Vo - OUTPUT VOLTAGE IV)
GND
truth table
Order Number LM75123J
Sao Package 17
INPUTS
Order Number LM75123N
Sao Package 23
E
F
OUTPUT
V
A
B
C
0
H
H
H
H
X
X
H
X
X
X
X
H
H
H
L
All Other Input Comblnatlon~
-H =high level, L =low level, X = irrelevant
ac test circuit' and switching time waveforms
3J1V
~50ns
>--+-....- .....-0 OUTPUT
3 QV
---'I-Jr=-=i
VOH
---+r----,.
INPUT
C,
(NOTE 8J
OUTPUT
NOTE A. THE PULSE GENERATORS HAVE THI;: FOLLOWING CHARACTERISTICS louT"" 5On.
tv. = 200 lIS, DUTY CYCLE = 6p%
NOTE B CL INCLUDES PROBE AND JIG CAPACITANCE
4-45
absolute maximum ratings
operating conditions
(Notes 1 and 2)
7.0V
Supply Voltage, VCC
Input Voltage
5.5V
7.0V
Output Voltage
Continuous Total Power Dissipation at (or
below) 25~C Free-Air Temperature (Note 5) 800 mW
Operating Free-Air Temperature Range
etc to +75·C
Storage Temperature Range
-65·C to +150·C
Lead Temperature (Solden ng, 10 seconds)
300·C
electrical characteristics
Supply Voltage, VCC
High Level Output Current,
IOH
Temperature, T A
MIN
MAX
UNITS
4.75
5.25
-100
V
mA
0
+75
·C
(Note 3)
PARAMETER
CONDITIONS
High Level Input Voltage (V,H )
MIN
TYP
MAX
UNITS
V
2.0
Low Level Input Voltage (V,d
0.8
V
-1.5
V
Input Clamp Voltage (V,)
Vee = 5.0V, 1,=-12mA
Input Breakdown Voltage (V (BR) 1)
Vee = 5.0V, I, = 10mA
5.5
V
High Level Output Voltage (V OH )
Vee = 5.0V, V,H = 2.0V,
10H = -59.3 mA, (Note 4)
TA = 25·C
TA = O°C to +75°C
3.11
2.9
V
V
High Level Output Current (lOH)
Vee = 5.0V, VIH = 4.5V, TA = 25'C, (Note 4)
VOH = 2.0V
Low Level Output Voltage (Vod
V,L = 0.8V, 10L = -240I'A, (Note 4)
Off State Output Current (10 OFF)
Vee = 0, Vo
High Level Input Current (I,H)
=4.5V
=0.4V
Vee = 5.0V, TA = 25'C
Vee = 5.25V, All Inputs at 2.0V, Outputs Open
Vee = 5.25V, All Inputs atO.8V, Outputs Open
Low Level Input Current (l,d
Short
CirCUIt
Output Current (los)
Supply Current, Outputs High (lceH)
Supply Current, Outputs Low (Iced
V,
PARAMETER
Propagation Delay Time, High to Low
Level Output (tPH d
Propagation Delay Time, Low to HIgh
Level Output (tPLH)
Propagation Oelay Time, Hlt'tl to Low
level Output (tPHd
0.15
=3.0V
40
V,
switching characteristics
Propagation Delay Time, Low to High
Level Output (tPLH)
-250
-100
40
!lA
-1.6
mA
-30
mA
28
mA
60
mA
TYP
MAX
UNITS
12
20
ns
12
20
ns
20
35
ns
15
25
ns
-{)1
MIN
=50n,C L = 15pF
(See AC Test CirCUit and SWitching
TIme Waveforms)
RL
V
I'A
Vee = 5.0V, TA = 25°C
CONDITIONS
RL
mA
=50n, CL = 100 pF
(See AC Test Circuit and SWitching
Time Waveforms)
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The
table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: All currents into device pins are shown as positive, currents out of device pins shown as negative, all voltage values are
referenced with respect to network ground terminal, unless otherwise noted. All values shown as max or min on absolute
value basis.
Note 3: Minimax limits apply across the guaranteed operating temperature range of O'C to +75'C for LM75123, unless
otherwise specified. Typicals are for VCC = 5.0V, T A = 25·C. POSItive current IS defined as current into the referenced pin.
Note 4: The output voltage and current limits Bre guaranteed for any appropriate combination of high and low inputs
specified by the truth table for the desired output.
Note 5: For operating at elevated temperatures, the cavity DIP package (J) hes a maximum junction temperature of +lSetC
and must be derated based on a thermal resistance of +85·C/W, junction to ambient. The molded DIP package (N) hes a maximum junction temperature of +150°C and must be derated based on a thermal resistance of +150'C/W, junction to ambient.
4·46
Line Drivers/Receivers
LM75124 triple line receivers
general description
features
The LM75124 is designed to meet the input/
output interface specifications for I BM System
360. It has built-in hysteresis on one input on
each of the three receivers to provide large noise
margin. The other inputs on each receiver are in
a standard TTL configuration. The LM75124 is
compatible with standard TTL logic and supply
voltage levels.
•
•
•
•
•
•
Built-in input threshold hysteresis
High speed .. typ propagation delay time 20 ns
Independent channel strobes
Input gating i'ncreases application flexibility
Single 5.0V supply operation
Plug-in replacement for the SN75124 and the
8T24
connection diagram and truth table
Dual-In-Line Package
vee
IS
IR
IV
3A
3S
3R
3V
A
S
Y
H
H
X
X
L
X
X
X
X
L
H
L
H
X
H
X
L
H
L
H
X
H
L
X
L
H
L
L
X
X
H
OUTPUT
INPUTS
Bt
R
=
high level, L '" low level, X = Irrelevant
tB Input and last two lines of the truth table
are applicable to receivers 1 and 2 only
TOP VIEW
Order Number LM75124J
Order Number LM75124N
See Package 17
See Package 23
typical application
A
8
C
o
r - - - - - - -,I
95n COAXIAL CABLE
r+~-rr=====~+-~~
95
8---"_J
L __ 1~M~4
__
-.J
4-47
'It
...
N
~
operating conditions
absolute maximum ratings
:E
(Notes 1 and 2)
....I
Supply Voltage, VCC
7.0V
Input Voltage
R I nput with V CC Applied
7.0V
R Input with VCC not Applied
6.0V
A, B, or S Input
5.5V
Output Voltage
7.0V
Output Current
±100 mA
Continuous Total Power Dissipation at (or below)
25°C Free-Air Temperature (Note 5)
800 mW
MIN
MAX
4.75
5.25
-800
UNITS
V
I'A
16
mA
a
+75
°c
TYP
MAX
UNITS
IOH
Low Level Output Current,
IOL
Operating Temperature, T A
O°C to +7So C
Operating Temperature Range
Storage Temperature Range
Supply Voltage, VCC
High Level Output Current,
--6S o C to +150°C
Lead Temperature (Soldering, 10 seconds)
300°C
electrical characteristics
(Note 3)
PARAMETER
CONDITIONS
MIN
High Level Input Voltage (V ,H 1
A, B, orS
R
V
V
2.0
1.7
Low Level Input Voltage (V'L)
A, B, orS
R
O.S
0.7
HysteresIs (V T+
-
(Note 7)
VT-)
R
Vee"" 5.0V, TA
Input Clamp Voltage (V,)
A, B, orS
Input Breakdown Voltage
A, B,arS
V
V
=
25°C
0.2
0.4
V
-1.5
Vee = 5 OV, I, = -12 mA
V
(V(BR) I)
High Level Output Voltage (V OH )
Vee = 5 OV, I, = 10 mA
V
,H
10H
Low Level Output Voltage (VoLl
=V,HMIN,V,L =V,LMAX,
5.5
V
2.6
V
= -SOOI1A (Note 4)
V'H =V,NMIN,V'L=V,LMAX,
0.4
V
5.0
5.0
mA
mA
40
170
I1A
Jl.A
10L = 16 mA (Note 4)
Input Current at Maximum Input Voltage
R
(I,)
V, = 7.0V
V, = 6.0V, Vee =
a
High Level I nput Current (I'H 1
A, B, orS
R
V, = 4.5V
V, =3.11V
Low Level Input Current (lId
A, B,or S
V,=O.4V
-0.1
-1.6
mA
Short Circuit Output Current (los)
Vee = 5 OV, TA = 25°C. (Note 6)
-50
-100
mA
Supply Current (Ieel
Vee = 5.25V
72
mA
TYP
MAX
UNITS
20
30
ns
20
30
ns
switching characteristics
PARAMETER
Propagation Delay Time, Low to High Level
Output from R Input (tPLH)
Propagation Delay Time, High to Low Level
Output from R Input (tPH cl
Vee = 5.0V, T A = 25°C
CONDITIONS
(See AC Test CircUit and SWitching
Time Waveforms)
MIN
Note 1: "Absolute MaXimum Ratings" are those values beydnd which the safety of the deVice cannot be guaranteed. Except for "Operatmg
Temperature Range" they are not meant to Imply that the deVices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual deVice operation.
Note 2: All currents Into device PinS are shown as positive, currents out of deVice pins shown as negative, all voltage values are referenced
with respect to network ground termmal, unless otherwise noted All values shown as max or min on absolute value baSIS.
Note 3: Mm/max limits apply across the guaranteed operatmg temperature range of O°C to +7SoC for LM75124, unless otherwise specified.
TYPlcals are for Vec '" S.OV, TA '" 2SoC. POSitive current IS defmed as current into the referE!nced pin.
Note 4: The output voltage and current limits are guaranteed for any appropnate combmatl'on of high and low inputs specified by the truth
table for the deSired output.
Note 5: For operatmg at elevated temperatures, the cavity 01 P package (J) must be derated based on a thermal resistance of +8SoC/W,
Junction to ambient. The molded DIP package (N) must be derated based on a thermal resistance of +150°C/W, junction to ambient.
Note 6: Note more than one output should be shorted at a time.
Note 7: HysteresIs IS the difference between the POSitive gOing Input threshold voltage, VT+' and the negative gOing Input threshold
voltage, VT_'
4-48
ac test circuit and switching time waveforms
2.6V
845
lN3064
)o-+-..:........-~~ OUTPUT
L __
=
*___
I
..J
50k
NOTE A. THE PULSE GENERATOR HAS THE FOLLOWING CHARACTERISTICS: ZoUT ~ sOn. tw =200 11$.
OUTV CYCLE =50%.
NOTE B CL INCLUDES PROBE AND JIG CAPACITANCE.
';50 ..
26V-H=~",,==~
INPIIT
VOH---~r---~
OUTPUT
typical performance characteristics
Output Voltage ys
Receiver Input Voltage
a
w
~
..
..5
~
>
4.0
3.6 I- vee· 5.0V '
NO LOAD
TA ' 26°C
3.0
2.6
2.0
~
1.6
I
1.0
oj
0.5
VT_
V"
I-+-+-+-+-+-+-+-+-+-l
OI:=:!:::::!:::t::"I,=""*",,,,-..L..LJ
o
0.2 0.4 0.6 0.8 1.0 1.2 1A 1.6 1.8 2.0
V, -INPUT VOLTAGE (V)
4·49
C
:E:
o
o
o
Peripheral/Power Drivers
en
.......
DHOOO~/D H0006C
C
:E:
*current driver
o
o
o
en
general description
n
there is less likelihood of false turn-on due to an
inadvertent short in the drive line.
The DH0006/DH0006C IS an Integrated high
voltage, high current driver designed to accept
standard DTL or TTL logic levels and drive
a load of up to 400 mA at 28 volts. AND inputs
are provided along with an Expander connection,
should additional gating be required. The addition
of an external capacitor provides control of
the rise and fall times of the output in order to
decrease cold lamp surges or to minimize electro·
magnetic interference if long lines are driven.
features
• Operation from a Single + 1OV to +45V Power
Supply.
• Low Standby Power Dissipation of only 35 mW
for 28V Power Supply.
• 1.5A, 50 ms, Pulse Current Capability.
Since one side of the load is normally grounded,
'Previously called NH0006/NH0006C
Metal Can Package
schematic and 'connection diagrams
OUTPUT
RESPONSE
TIME
CONTROL
INPUT
- ...---4I----~...-~...- .._Ov"
NC
TOP VIEW
"-"-0
Order Number DH0006H or DH0006CH
See Package 13
OUTPUT
Dual-In-Line Package
INPUT
10
INPUT
OUTPUT
EXPANOER
INPUT
INPUT
INPUT
INPUT
---"t--,
C ) RESPONSE
TIME
CONTROL
B
·.,......--4I--..- - - - - - o G R O U N O
GROUND
+ __
INPUT_"";'f---' ' -_ _
INPUT
Order Number DH0006CN
See Package 21
typical applications
Lamp Driver with Expanded I"puts
Relay Driver
V"
+28V
OUTPUT
OTL/TTL {
LOGIC
INPUTS
J27
LAMPS
onnn
EXPANDER INPUT
RELAY
COIL
LOGIC
INPUTS
\-
~USH TO
.l.TEST
5·1
(.)
U)
o
absolute maximum ratings
o
o
Peak Power Supply Voltage (for 0.1 sec)
Continuous Supply Voltage
Input Voltage
Input Extender Current
Peak Output Current (50 ms Onll sec Off)
Operating Temperature
DH0006
DH0006C, DH0006CN
Storage Temperature
J:
o
.......
U)
o
o
o
J:
o
electrical characteristics
PARAMETER
60V
45V
5.5V
5.0mA
1.5A
_55°C to +125°C
O°C to +70°C
_65°C to +150°C
(Note 1)
CONDITIONS
MIN
Logical "1" Input Voltage
Vee = 45V to 10V
Logical "0" Input Voltage
Vee = 45V to 10V
Logical "1" Output Voltage
Vee = 28V, V 1N = 2.0V, lOUT = 400 mA
Vee =45V, V 1N =0.8V, RL = lK
Vee = 10V, V 1N = 2.0V, lOUT = 150 mA
Logical "0" Input Current
Vee = 45V, V 1N = .4V
Logical "1" Input Current
Vee = 45V, V 1N = 2.4V
26.5
27.0
8.8
9.2
Vee = 45V, V 1N = 0.8V
V
V
.01
.001
V
V
-0.8
-1.0
mA
0.5
5.0
/1A
5.5V
"Off" Power Supply Current
UNITS
V
0.8
Logical "0" Output Voltage
~
MAX
2.0
Logical "1" Output Voltage
Vee = 45V, V 1N
TYP
(Note 2)
100
1.6
/1A
2.0
mA
8
mA
"On" Power Supply Current
Vee = 45V, V 1N = 2.0V, lOUT = 0 mA
Rise Time
Vee = 28V, RL = 82n
0.10
Fall Time
Vee = 28V, RL = 82n
0.8
/1S
Ton
Vee = 28V, RL = 82n
0.26
/1S
Toll
Vee = 28V, RL = 82n
2.2
/1S
Note 1: Unless otherWise specified, limits shown apply from -5SoC to 12SoC for DH0006 and O°C to
70° C for DH0006C.
Note 2: TYPical values are for 2SoC ambient.
Note 3: Power ratmgs for the TO·5 based on a maximum junction temperature of +17SoC and a f/>JA
of 210 0 C/W
Note 4: Power ratmg for the DH0006CN Molded DIP based on a maximum Junction temperature of
+150o C and a thermal resistance of 17SoC/W when mounted
In
a standard DIP socket
Note 5: Power ratmg for the DH0006CN Molded DIP based on a maximum Junetlo!" temperature of
+150°C and a thermal resistance of 150oC/W when mounted on a 1/16 Inch thick, epoxy-glass board
wtth ten 0 03 Inch Wide 2 ounce copper conductors.
switching time waveforms
--"~"I~%---+T---~-r----
A PULSE
,
.~ __~~'I~I=N'=U,~lItr____
:....:J" I-
.0%----t-+-J'+~q.--1f_--
.'. -f 1-'0..'-
PULSE OUTP;T\
10'
5·2
/1S
C
::t
«:)
typical performance
I:)
I:)
0)
Maxuhum ContinUOUS Output
Current For TO~5
.....
Inpu, Threshold Voltage
Maximum Contmuous Output
~
vs Temperature
Current For Molded 01 P
2.2
~
.'"
40
~
..
>
30
~
>
~
~
.
'"
::;
~
t
~
~
'"~
40
~
::;
20
>
~
30
1.2
~
200
400
600
-50 -25
BOO
MAXIMUM CONTINUOUS OUTPUT CURRENT ImAI
Logical "0" I nput Current
1200
I-
~
B 1000
f
P
600
~
200
+25°C
800
_55°~,>
!!!
5 400
.s<
,
£
~
+12S"C
~
l& ~
~ po +25°C
Ie ......
10
>
~
~
..... Ill!!! F""'"
0.5
+25°~
~
30
20
40
50
,
300 f--
20
Vee
,.
30
0
~
20
;::
SO
lS 100 125
_.l
o
~ ~ r1
-lS -50 -25
0
25
~
1.6
.;
..;
14
1.5
.'"~
...
f5
>
z
;::
I
'"
SO
15 100 125
I-
:!i
!;
.~
13
Available Output Current
I-
~
1.2
1.0
.8
m
.6
A
>
.2
.
:<
o
-o
10
f--
1 ms"ON"
1.0
09
O.B
0.1
06
~
Tc::: 25"C
!;
y+s'i
20
~
30
40
50
20
10
-
~
os
2.0
~
Vee'" 2av
\
'"
~ E:::; ......
~ I': ~LSE CONDITION.
~ ~ TON'" LOsee:
I"'J
I"
l~
<
TOFF=10sec:
I("
..l..l
TA • 12SoC
o
200
400
""
SO
100
r
~
C,'
!;
150
200
r--
BOO
600
'10 6.
1000
{mAl
"'j"'
30
TA "'25°C
pF
opF \C,. 300 .KjBO pF
Cf
... r-:: Ii:::l
'
\ 1'1 loA""'
C:. 300 pF
RL ::: fian
~
Vee = 2aV
Turn On Control
!!!
30
100 ms "OFF"
SO
4.0
, .PULSE CONDITION
V;~
Ii'
- ",,J
tl-+
-OUTPUT CURRENT,
!!!
\>"W
~
S
2.0
~
T~' i25'b
1.4
t- _~TA'O'C
TA =25°C
tTA 7UOC
11
Turn Off Control
4.0
r-trH=T~' -;s,d-
12
TEMPERATURE rCI
20
I.B
16
40
30
Output Saturation Voltage
!/r
[...;' ......
10
2S
20
SUPPLY VOLTAGE IVI
",'I-~
t, ::::;10 ns
I
-15 -50 -25
10
50
~!.~~~
\)~FVIN = 3.0V PULSE
1
o
40
,-
=2RV
RL = 6an
CL = 10pF
]
CL :: 10pF
VIN '" 3.DV PULSE
t, ~10 ns
RISE TIME
100
30
Turn Off and Fall Time
Vee:: 2aV
Rl :: 6an
I
I
200
~
~~
SUPPLY VOLTAGE IVI
4.0
Tu!NO~TlJ~ t-t""
;::
~
~
~~ V
~
10
Turn On And Rise Time
400
~
~
V
~ ~'"
+125'C-
+125°C
IP
SUPPl Y VOLTAGE IVI
l-
~
Jsoc
I
~
o
10
5
15 100 125
"ON" Supply Current Drain
o
~
50
25
V.
_55°~
1.5
I-
t:::: ~ ~
...::~ ~ ro-:
0
AMBIENT TEMPERATURE I'CI
"Of F" Supply Current Drain
2.0
1600
1400
DB
0.6
MAXIMUM CONTINUOUS OUTPUT CURRENT ImAI
f5
14
1.0
!!!
0)
()
16
j!:
'"
20
I.B
~
10
i
80
20
250
~
C,·Q
20
10
JI'.
~ V2.0
4.0
CF = 680 pF
~L8V
RL ::: 6an
TA = 25°C
CL "'10pF
6.0
1.0
10
SUPPLY VOLTAGE, Vee.IVI
5-3
(,)
i
Peripheral/Power 'Drivers
o
o
:::c
Q
.......
OQ
OH0008/0H 0008C*
high voltage, high current driver
o
o
o
:::c
c
general description
The DHOOOS/DHOOOSC is an integrated high voltage, high current driver, designed to accept standard DTl or Tel Input levels and provide a pulsed
load of up to 3A from a continuous supply voltage
up to 45V. AND Inputs are provided with an EXPANDER connectIOn, should additional gating be
required.
.circuit also requires only one power supply for
.circuit functional operation.
The DHOOOS is available in a lO-pln TO-5 package;
the DHOOOSC IS also available In a lO-pln TO-5, In
addition to a 10-lead molded dual-In-line package.
features
Since one side of the load is normally grounded,
there is less likelihood of false turn-on due to an
inadvertent short in the drive line.
The high pulse current capability makes the
DHOOOS/DHOOOSC ideal for driving nonlinear
resistive loads such as incandescent lamps. The
'Previously called NHOOOS/NHOOOSC
• Operation from a Single +10V to +45V Power
Supply.
• Low Standby Power Dissipation of only 35 mW
for 2SV POwer Supply.
• 3.0A, 50 ms, Pulse Current Capability.
Metal Can Package
schematic and connection diagrams
OUTPUT
Rf
RISE AND
FALL
TIME
CONTROL
RESPONSE CONTROL
r - - -...- - I - -...- ....- ...."'-O v"
TOP VIEW
Order Number DH0008H or DH0008CH
See Package 13
INPUT
Dual-In-Line Package
L............-oOUTPUT
INPUT
EXPANDER
"
v"
INPUT
-----Cl GROUND
1 L - - + -. .
Nt
INPUT
RESPONSE CONTROL
EXPANDER
GROUND
INP,Uf
typical application
Controller for Closed Loop Stepper Motor
...--+-...-+-...-+---,
:~~+-
DTf~---r~--It~====:!~::::~~~~
DR
m
CLOCK
5-4
OUTPUT
INPUT
INPUT
Order Number DHOOO8CN
See Package 21
Switching Sequence
Step
1
2
3
4
1
A
1
B
0
C
0
1
1
0
0
1
0
0
1
1
0
0
1
0
1
1
1
0
0
To reverse the direction use a 4, 3, 2, 1
sequence
C
:J:
absolute maximum ratings
Peak Power Supply Voltage (for 0.1 sec)
Continuous Supply Voltage
Input Voltage
Input Extender Current
Peak Output Current
(50 msec Onll sec Off)
Continuous Output Current
(See continuous operating curves.)
Operating Temperature
DHOOOS
DHOOOSC
Storage Temperature
electrical characteristics
PARAMETER
o
o
o
60V
45V
5.5V
5.0mA
CO
.......
o
:J:
o
o
3.0 Amp
o
CO
n
-55°C to +125°C
O°C to +70°C
_65°C to +150°C
(Note 1)
CONDITIONS
MIN
= 45V to 10V
TYP
(Note 2)
MAX
UNITS
V
Logical "1" Input Voltage
Vee
Logical "0" Input Voltage
Vee = 45V to 10V
Logical "1" Output Voltage
Vee = 45V, V ,N = 2.0V, lOUT
50 ms Onll sec Off
Logical "0" Output Voltage
Vee
Logical "1" Output Voltage
Vee = 2SV, V ,N = 2.0V, lOUT
50 ms Onll sec Off
Logical "0" I nput Current
Vee = 45V, V ,N = O.4V
-O.S
-1.0
mA
Logical" 1" I nput Current
Vee = 45V, V ,N = 2.4V
0.5
5.0
!i A
2.0
O.S
= 1.6A
43
= 45V, V ,N = O.SV, RL = 1 K
26.5
V
43.5
0.02
= O.SA
0.1
V
V
27.1
Vee = 45V, V ,N = 5.5V
V
100
!i A
"Off" Power Supply Current
Vee
= 45V, V ,N = OV
1.6
Rise Time
Vee
= 2SV, RL = 39Q, V ,N = 5.0V
0.2
!is
Fall Time
= 2SV, RL = 39Q, V ,N = 5.0V
Vee = 2SV, RL = 39Q, V ,N = 5.0V
Vee = 2SV, RL = 39[2, V ,N = 5.0V
3.0
!is
TON
TOFF
Vee
2.0
mA
0.4
!is
7.0
!is
Note 1: Un"less otherWise specified limits shown apply from -55°C to 12SoC for DH0008 and O°C to
70°C for DH0008C.
Note 2: Typical values are 25°C ambient
Note 3: Power ratings for the TO·5 based on a maximum Junction temperature of + 175°C and a 1> JA
of 21OoC/w
Note 4: Power ratmgs for the DH0008CN Molded DIP based on a maximum Junction temperature of
150°C and a thermal resistance of 150°C/w when mounted
In
a standard DIP socket
Note 5: Power ratings for the DH0008CN Molded DIP based on a maximum Junction temperature of
150°C and a thermal resistance of 115°C/w when mounted on a 1/16 Inch thick, epoxy-glass board
with ten 0.03 Inch Wide 2 ounce copper conductors.
switching time waveforms
-"·'U·'-
9O%--+-F=----'H-A PULSE
rl INPUT
.D%--+f----it-~
....., l.::j"
000-
90%--1-+-1+--\--1--
f.'o
10%
f.Ulr::.:~;;\
5·5
CJ
00
o
o
o
typical performance
:t:
Q
.......
Maximum Continuous Output
Current for Molded DIP
Maximum Continuous Output
Current for TO-S Package
Available Output Current
50
00
o
o
o
~
Q
'"'"
!;;
~
40
~
36
'"
~
c
40
'"
w
w
:t:
....
::i
c
>
~....
30
>
>
>
t
t
iil
400
200
20
1.0
.9
c
>
z
c
:;
a:
":ll....
....
~
"c
~
:;:
O.B
>
'"
0.4
.8
.7
~
2.0
'"~
1.6
c
>
1.6
9c
1.4
tl
a:
'"....
.5
.4
~
.3
.2
!!
j
....
::i
a:
~
:
!!
1.2
F
..
~
1.0
::l
9
0.8
-50 -25
0
25
50
V
~
~
./
+12S 0 C-
'"a:
20
30
t
iil 0.5
40
P
~~
~ ~ +2So C
1.0
~
~
~
30
~
~
'"c
TIME ... )
j
+125°C
w
!
200
250
10
I
f-Vee -2BV
1--1; '7.1'
IIX
RL '" 30n
Cl "'10pF
TA =25°e
RF =51kn
IJ
2
4
6
40
50
10pF
0
8.0
-"",I'
. / !-""
6.0
V
TjRN
./
..".
iFF jlME
~
f-
' '\ FALL TIME
-25
+25
+75
+125
TEMPERATURE rC)
Vee
700
l
o
30
TUrn ON and Rise Time
I I
.~~.#
+12S o C
VIN " 3.0V PULSE
tf ::;10 ns
10.0
-75
50
I
20 r-~
....
150
20
CL
12.0
1/
40
---
Vee = 2aV
RL '" JOn
14.0
T.= aprrOXim'j'Y 1,0 nS - - f -
H
30
100
~ P""
i<
~~~
o
2.0
30
50
200
~
4.0
20
I
....
10
~ ;;.--
400
Turn OFF Control
~
"e:
"c
600
SUPPLY VOLTAGE IV)
....
20
-55°~~
o
10
~
~
+25°C
800
Turn OFF and Fall Times
e"
'P
SUPPLY VOLTAGE IV)
Turn ON Control
50
16.0
o
50
40
SUPPLY VOLTAGE IV)
V. .
....
::i
o
10
1000
10
~
-55°~ ""J.
:;: 1.5
.!
B
30
1200
75 100 125
2.0
t--
20
1400
OFF Supply Current Drain
ON Supply Current Drain
A ~. /
~
~
I I
AMBIENT TEMPERATURE lOCI
I lY'
+25°~~
PULSE COND~T~
1 MS"ON"
100 MS "OFF"
It
Logical "0" I nput Current
0.6
~/
I If
Tc '" -55"C
1600
w
J5°C
Tc o 25°Cj
SUPPLY VOLTAGE. Vee, IVI
2.2
OUTPUT CURRENT IAI
5·6
1.2
1.6
Input Threshold Voltage
vs Temperature
.2 .3 .4 .5 .6 .7 .8 .9 1.0
....
;;
10
1.1
w
2.0
W
11/
MAXIMUM CONTINUOUS OUTPUT CURRENT ImAI
Output Saturation Voltage
~
2.B TCi12rC
2.4
600
600
MAXIMUM CONTINUOUS OUTPUT CURRENT ImAI
'"'"!;;
I I
I I
3.2
!;c"
w
iil
20
4.0
3.6
8 10 12 14 16 18
TIME I",)
600
!
!
500
=2aV
RL ' 3911
CL 10pF
VIN ::t l,OV PULSE
0
tr -:;::10 AS
I
400
300
I
TURN ON TIME /"
I
200
-
RISE TIME / '
100
I
-50 -25
0 +25 +50 +15 +100 +125
TEMPERATURE 1°C)
c
::z:
o
o
Peripheral/Power Drivers
~
~
.......
c
::z:
o
o
~
~
(')
DH0011*(SH2001)
DH0011C*(SH2002)
DH 0011CN*(SH2002P)
.......
high voltage high current drivers
(')
c
::z:
o
o
~
~
Z
general description
Applications include driving lamps, relays, cores,
and other devices requiring several hundred milliamp currents at voltages up to 40V. Logic flexibility is provided through a 4-input NAND gate, a
NOR input and an input which bypasses the geting
and connects the base of the output transistor.
The DH0011 high voltage, high current driver
tamily consists of hybrid integrated circuits which
provide a wide range of variations in temperature
range, package, and output current drive capability. A summary of the variations is listed below.
'PrevlOusly called NH0011, NH0011C, NH0011CN
logic diagram
Dual-In-Line Package*
GND
TOP VIEW
ordering information
NSC
DESIGNATION
SH
DESIGNATION
SEE
PACKAGE
TEMPERATURE
RANGE
OUTPUT CURRENT
CAPABILITY
DHOO11H
DHOO11CH
DHOO11CN
SH2001
SH2002
SH2002 P
12
12
22
-55'C to +125'C
O'C to +70'C
O°C to +70°C
250mA
150mA
150mA
*Metal can pin numbers are the same as the dual-In-line pin numbers.
5·7
z
(,;)
:=
absolute maximum ratings
o
o
:x:
8V
VCC
40V
Collector Voltage (Output)
1.0mA
Input Reverse Current
800mW
Power Dissipation
_55°C to +125°C
Operating Temperature Range DH0011H
DH0011CH/DH0011CN O°C to +70°C
_65°C to 150°C
Storage Temperature
Q
"(J
......
o
o
:x:
Q
......
"-
o
o
:x:
electrical characteristics
PIN 6
PIN 1
PIN 2
PIN 3
PIN 4
PIN 5
PIN 7
PIN 8
1
V 1H
V 1H
V 1H
V 1H
GND
GND
IOL1
2
V 1L
GND
GND
IOL1
3
V 1L
GND
TEST NO.
Q
4
V 1L
5
V 1L
PIN 9
PIN 10
SENSE
V CCL
Vs
VOL
V CCL
Vs
IOL2
V CCL
V6
VOL
V OL2
V 1L
MIN
GND
IOL2
V CCL
V6
V OL2
GND
IOL2
V CCL
V6
V OL2
V CCL
V6
V OL2
V CCL
V6
V OL2
6
V 1L
GND
IOL2
7
GND
GND
IOL2
V 1H
8
VR
GND
GND
GND
GND
V CCH
11
IR
9
GND
VR
GND
GND
GND
V CCH
12
IR
10
GND
GND
VR
GND
GND
V CCH
13
IR
11
GND
GND
GND
VR
GND
V CCH
14
IR
V CCH
19
IR
12
GND
VR
13
VF
VR
VR
VR
GND
V CCH
11
-IF
14
VR
VF
VR
V CCH
12
-IF
VR
VR
VF
VR
VR
GND
15
GND
V CCH
13
-IF
16
VR
VR
VR
VF
GND
V CCH
14
-IF
GND
GND
V CCH
19
-IF
V CCL
V6
V CCL
Is
lox
V PD
110
IpDH
110
17
18
19
GND
20
VF
GND
GND
GND
GND
GND
GND
Vox
V OH
GND
V MAX
22'
GND
V PD
tON
23'
GND
V PD
tOFF
21
GND
I MAX
*See Test Circuits and Waveforms on Page 4.
forcing functions
(Note 1) DH0011
-55°C
+25°C
+125°C
UNITS
V CCL
4.5
4.5
4.5
V
V CCH
5.5
5.5
5.5
V
PARAMETER
V PD
5.0
V
V MAX
8.0
V
V 1L
1.4
1.1
0.8
V
V 1H
2.1
1.9
1.7
V
VR
4.0
4.0
4.0
V
VF
0.0
0.0
0.0
lou
250
250
V
mA
250
IOL2
8.0
8.0
7.5
mA
Vox
40.0
40.0
40.0
V
Note 1: Temperature Range -5SoC to +12SoC
5·8
MAX
*
.0
:l:
forcing functions
O°C
5.00
5.00
PARAMETER
VCCL
VCCH
Vpo
VMAX
V1L
V1H
VR
+25°C
5.0
5.0
5.0
8.0
1.1
1.9
4.0
0.45
150
8.0
40.0
1.20
2.00
4.00
0.45
150
8.0
40.00
VF
lOll
IOL2
Vox
test limits
-55°C
MIN
MIN
.......
V
V
V
V
V
V
V
o
::I:
o
o....
....
(")
.......
C
::I:
o
o....
V
mA
mA
....
(")
z
V
+125°C
MAX
MIN
0.45
0.45
2.00
lox
IPOH
IMAX
tON
tOFF
V
V
V
1.80
2.0
1.6
5.0
30.6
29.6
160
220
1.60
UNITS
MAX
0.4
0.4
2.20
IR
-IF
J1A
mA
J1A
mA
mA
5.0
1.5
200
ns
ns
(Note 2) DHOOllC, DHOOllCN
O°C
+25°C
MAX
MIN
MIN
+70°C
MAX
0.45
0.45
VaLl
VOL2
VOH
....
UNITS
.95
1.8
4.0
0.5
150
7.5
40.0
+25°C
MAX
0.45
0.45
VOLl
VOL2
VOH
PARAMETER
+70°C
5.0
5.0
(Note 1) DHOOll
PARAMETER
test limits
o
o....
(Note 2) DHOOllC, DHOOllCN
1.95
UNITS
MAX
0.45
0.45
2.05
IR
-IF
MIN
0.5
0.5
V
V
V
10.0
1.35
200
J1A
mA
J1A
mA
mA
1.85
5.0
1.4
5.0
30.6
34.0
1.40
lox
IpOH
IMAX
Note 1: Temperature Range -5SoC to +125°C
Note 2: Temperature Range OoC to +70O C
switching time test circuit
(
50V
AI
PIN10=V cc "'SV
PULSE
GEN.
~
FREQ = 100 kHz
DUTY CYCLE = 50%
Typical Switching Times
1
OUTPUT
'.1O,f-WI.,.G
CAP.
-
PIN 5, PIN 7 GNO
200
A
!II
;:
switching time wavefo-rms
150
'!.ott
100
",-
50
'r
'GV
"':'~,\.i
4V
ov
2V
4V
'o~
\2V
1.:" . -i
"
...,.,
25°C
125°&
TEMPfRATURE (°1:)
5·9
z
u
...
ClO
Peripheral/Power Drivers
o
o
J:
Q
Z
U
...o,...
DH0016CN*
DH0017CN*(SH2200P)
DH0018CN*
o
J:
Q
z
u
...o
high voltage high current drivers
CD
o
J:
Q
general description
withstanding voltages up to 100V. Logic flexibility is provided through a 4-input NAND gate, a
NOR input and an input which bypasses the gating
and connects to the base of the output transistor.
This high-voltage, high-current driver family consists of hybrid integrated circuits which provide a
wide range of output currents and output voltages.
Applications include driving lamps, relays, cores,
and other devices requiring up to 500 mA and
*Previously called NH0016CN, NH0017CN, NH0018CN
logic diagram
Dual-In-Line Package
GNO
TOP VIEW
ordering information
5·10
NSC
DESIGNATION
SH
DESIGNATION
SEE
PACKAGE
DHOO16CN
DHOO17CN
DHOO18CN
N/A
SH2200P
N/A
21
21
21
OUTPUT CHARACTERISTICS
Maximum Standoff
Voltage
70V
50V
100V
Current
250mA
500mA
500mA
o
:t
o
absolute maximum ratings
...o
SV
SV
70V
50V
100V
1.0A
2.0A
455mW
O°C to +70°C
_65°C to +150"C
Vee
I nput Voltage
Collector Voltage
DHOO16CN
DHOO17CN
DH001SCN
DHOO16CN
Output Surge Current
DH0017CN & DH001SCN
Power Dissipation
Operating Temperature Range
Storage Temperature
Ol
(')
Z
o
:t
o
o
.......,
(')
Z
o
electrical characteristics
TEST
PIN 1
NO.
2
V 1H
3
V'L
PIN 2
V'H
4
PIN 3
PIN 4
V'H
V'H
V'L
5
V'L
6
7
V'L
11
PIN 9
GND
GND
IOL1
GND
GND
IOL1
V'L
GND
GND
IOL1
V'L
GND
GND
IOL1
GND
GND
IOL1
PIN 10
SENSE
MIN
V OL1
Vee
Va
V OL1
Vee
Va
V OL1
V'L
Vee
Va
V OL1
V'L
Vee
Va
V OL1
V6
V OL2
GND
IOL2
Vee
V6
V OL2
GND
IOL2
Vee
V6
V OL2
V'L
GND
GND
IOL2
Vee
V6
V OL2
GND
IOL2
Vee
V6
V OL2
V'H
12
VR
GND
GND
GND
GND
Vee
11
IR
13
GND
VR
GND
GND
GND
Vee
12
IR
14
GND
GND
GND
Vee
13
IR
GND
GND
VR
GND
GND
15
VR
GND
Vee
14
IR
Vee
19
IR
17
VF
VR
VR
VR
GND
Vee
11
-IF
16
VR
GND
IS
VR
VR
VF
VR
VR
Vee
12
-IF
VR
VF
VR
GND
19
GND
Vee
13
-IF
20
VR
VR
VR
VF
GND
Vee
14
-IF
GND
GND
Vee
19
Vee
V6
Vee
V PD
18
110
IpD
V MAX
110
I MAX
21
GND
GND
IOL3
GND
Vox
GND
24
25
GND
GND
22
23
VF
GND
GND
GND
...
MAX
Va
Vee
o
o
LIMITS
Vee
V'L
10
PIN 8
IOL2
V'L
9
PIN 7
GND
V'L
S
:t
PIN 5 PIN 6
00
(')
Z
-IF
V OH1
lox
forcing functions
O°C
+25°C
Vee
V PD
V MAX
5.0
V'L
V 1H
VR
VF
Vox
Vox
Vox
IOL1
IOL 1
IOL2
IOL3
0.S5
19
4.5
0.45
50
5.0
8.0
0.S5
1.S
4.5
0.45
70
50
100
500
250
16
8.0
SYMBOL
(DHOO16CN)
(DHOO17CN)
(DHOO18CN)
(DH0017CN, DHOO18CN)
(DHOO16CN)
500
250
16
+70°C
5.0
0.85
1.6
4.5
0.45
70
50
100
500
250
16
UNITS
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
5-11
z
(J
...
ClO
test limits
o
o
J:
o
z
O°C
0.6
0.45
1.95
SYMBOL
V OL1
V OL2
...,...
V OH1
CJ
IR
o
o
:::t
o
1.6
-IF
lox
Ipo
I MAX
Z
+70°C
0.6
0.45
1.65
60
1.6
200
+25°C
0.6
0.45
1.85
60
1.6
5.0
12.2
10
UNITS
V
V
V
J1A
rnA
J1A
rnA
rnA
(J
...
CD
o
o
J:
o
Typi~al
Output Voltages vs Temperature
Typical Switching Time. IC = 250 mA
Typical Switching Time. IC = 500 mA
DHOOl6CN
DHOO17CN,DHOO18CN
~ 04
is
>
~
'"
< OJ
!:;
"
">=<
...g;
:Ii
...
>
z
DHOOt1CN, DH0018CN Ie;; 500 mA
~
0.2
!
600
"'"
500
>=
r- I - -DHOOI6CN 'c ·250mA-
z 400
;;
tO~F
~~
.... ...... .....
]
!
'"
Z
JO
2.0
~
~ JOO
!
0.1
~
"
- -
i
200
100
1.0
tON
f-"""
.... i-"'"
...... ~
tON
0
0
25
50
75
0
TEMPERATURE I CI
25
50
75
0
TEMPERATURE I CI
.,
50•
Pm 10= Vee =5.0V
PULSE
GEN.
~
Frequency=100kHz
Duty Cycle "'50%
t
OUTPUT
C.1O,'-W,.,
CAP. ••
Pm 5,Pm 7 GND
":'
R1 ;; 200n lDHOO16CN!
R1" lOOn (DHOD17CN, DHD018CN)
switching time waveform
INPUT
D.
-r-,
1
\
2V
"V
\
10,.-----
OTT
\
.V
25
SO
TEMPERATURE
switching time test circuit
5·12
-
tOFF
2V
-,<>,,-.
.V
7.
rei
o
:::t
o
o
Peripheral/Power 0 rivers
N
CO
n
o
......
DH0028C/DH0028CN*hammer driver
:::t
o
o
N
CO
general description
features
The DH0028C/DH0028CN is a high current
hammer driver designed for utilization in a wide
variety of printer applications. The device is
capable of driving 6 amp pulsed loads at duty
cycles up to 10% (1 ms ON/10 ms OFF). The
input is DTL/TTL compatible and requires only a
single voltage supply in the range of 10V to 45V.
• Low standby power: 45 mW at Vee = 36V.
35 mW at Vee = 28V.
• AND input
flexibility.
n
with
expander
affords
Z
logic
• Fast turn-on, typically 200 ns_
'Previously called NH0028C/NH0028CN
connection diagrams
Metal Can Package
Molded Dual·lnwLine Package
OUTPUT
V"
1
10
INPUT
2
,
INPUT
EXPANDER
Ne
INPUT
OUTPUT
Nt
INTERNAL
CONNECTION
3
•
7
GROUND
5
•
INPUT
TOPVIEW
Order Number OH0028CH
See Package 13
Order Number DH0028CN
See Package 21
typical application
COLUMN ONE
INPUT
COLUMN TWO
INPUT
r-----+----....---~~?+36V
',*""
r-+----+-----H~---+-----~~g~~Rcci~LE
r--DH002SC;;---,
I
I
L--l;--.J
INHIBIT
..--------+~
>-------4~--------t-
m
m
3W
3W
HAMMER #1
lOV
HAMMER #2
lOV
*Use one decouphngcapacltor per SIX hammer dnvers for
ImprovedllC nOise Irnmumty
**Zener IS used to contral the dynamiCS of the hammer
5-13
z
(,)
co
.absolute maximum ratings
N
o
Continuous Supply Voltage
Instantaneous Peak Supply Voltage
(Pin 1 to Ground for 0.1 sec)
Input Voltage
Expander Input Current
Peak Otuput Current (1 ms ON/l0 ms OFF)
Continuous Output Current DH0028C at 25°C
DH0028CN at 25°C
Operating Temperature
Storage Temperature
Lead Soldering Temperature (10 sec)
o
::z::
c
......
(,)
CO
N
o
o
::z::
c
electrical characteristics
PARAMETER
45V
60V
5.5V
5.0mA
6.5A
750mA
1000mA
O°C to 70°C
_65°C to +175°C
300°C
(Note 1)
CONOITIONS
TYP
MIN
MAX
UNITS
(Natoli
Logical ''1'' Input Voltage
Vee = lOV to 45V
Logical "0" Input Voltage
Vee'" lOV to 45V
V
20
Logical "0" Input Current
Vee = 45V. V IN
04V
08
Logical "1" Input Current
Vee:: 45V. VIN = 24V
Vee:: 45V. V IN = 5 5V
05
Logical "," Output Voltage
Vee:: 45V, V IN ::: 20V,
::
lOUT = l6A
Vee = J6V, VIN = 2
0.8
V
10
mA
5.0
1000
430
435
V
335
340
V
av.
lOUT =
SA
(Note 2)
Logical "0" Output Voltage
Vee'" 45V. RL = lk, V 1N
OFF Power Supply Current
Vee" 45V. VIN = DOV
Rise Time (10% to 90%)
Vee· 45V. R, • 391!
VIN = 50V peak, PRF
Fall TIme (90% to 10%)
TOFF
'"
020
0 8V
. 16
V
mA
02
ps
Vee = 45V, R L ::: 39U
VIN = 5 OV peak, PRF ~ 1 kHz
30
ps
Vee = 45V. R L :: 39U
VIN = 5 OV peak, PRF
04
ps
70
ps
=
=
1 kHz
1 kHz
Vee'" 45V, RL = 39U
VIN = 5 OV peak, PRf ::: 1 kHz
Note 1. These specifications apply for ambient temperatures from
speCified All tYPical values are for 25°e ambient
oOe
to 700e unless otherwise
Note 2' Measurement made at 1 ms ON and 10 ms OFF
Not. 3: Power ratings for the DHOO28C are based on a maximum Junction temperature of 17Soe and
a thermal resistance of 2100C/W
Not.4: Power ratings for the OH0028CN are based on a ma)omum Junction temperature of 17Soe
and a thermal reSistance of 1500 e/W
typical performance characteristics
Waveforms for Typical
Drum Printer Hammer
., 4°CIf::f::J=ErIJ]
a
30
:f
101--
201--
Vcc" 3ev
TON =1 ms
TOFF "10ms
TA IE 25"C
0
~
~~AJMEJ
6 I-t-tELiA~
..9
2
-10 I--
.,
4
0
IA I
VI I I
V,
I
V(
R,
~
I\"
D 02040608 1.0 12 14 16
TIME (ms)
5·14
100
20
C
::t
o
o
Peripheral/Power Drivers
w
UI
"C
::t
o
o
OH0035/0H0035C PIN diode switch driver
w
UI
(")
general description
The DH0035/DH0035C is a high speed digital
driver designed to drive PI N diodes in R F modulators and sWitches. The device is used in conjunction
with an input buffer such as the DM7830/DM8830
or DM5440/DM7440.
features
•
•
Large output voltage swing - 30V
Peak output current In excess of 1 Amp
•
Inputs TTLlDTL compatible
•
•
Short propogatlon delay - IOns
High repetition rate - 5 MHz
The DH0035/DH0035C is capable of driving a
variety of PIN diode types including parallel,
serial, anode grounded and cathode grounded. For
additional Information, see AN-49 PIN Diode
Drivers.
The DH0035 is guaranteed over the temperature
range _55°C to +125°C whereas the DH0035C is
guaranteed from O°C to 85°C.
schematic and connection diagrams
Metal Can Package
'""
y
~OUl1'UT
""
TOP VIEW
Order Number OH0035G or DH0035CG
See Package 6
typical applications
Grounded Cathode Design
Note Cathode nrounded Pin dIOde Rp = 62n hmlts diode
forward current to 100 rnA TYPical sWitching for HP33604A,
RF tum-on 25 os, turn-off 5 ns CZ'" 250 pF, Rp '" on,
e1 '" 0 1F
V"--10V
5-15
(.)
It)
M
o
o
absolute maximum ratings
Q
V- Supply Voltage Differential (Pin 5 to Pm 1 or 2)
40V
V· Supply Voltage Differential (Pin 1 or 2 to Pin 8 or 9)
30V
Input Current (Pltl 3 or 7)
:!::.75 rnA
Peak Output Current
± 1 0 Amps
Storage Temperature Range
Power DISSipation (Note 3)
Lead Temperature (Soldering, 10 sec)
::t
"It)
M
o
o
::t
PARAMETER
O"C to +85"C
300°C
(Notes 1,2)
CONDITIONS
MIN
LIMITS
TYP
MAX
UNITS
Input Logic "1" Threshold
V OUT " -8V, RL " lOOn
Input Logic "0" Threshold
VOUT " +8V, RL " lOOS!
POSItive Output SWing
louT" 100 mA
Negative Output SWing
louT" 100 mA
POSitive Short CircUIt Current
V ,N
c OV, RL" on
(Pulse Test; Duty Cycle ~ 3%)
400
800
mA
Negative Short Circuit Current
V ,N
800
-1000
mA
Turn-On Delay
V ,N " 1.5V, V OUT " -3V
10
15
Turn-Off Delay
V ,N " 1 5V, V OUT " +3V
15
30
ns
On Supply Current
V ,N " 1 5V
45
60
mA
15
V
70
V
-7.0
V
+8.0
V
-8.0
c 1.5V, liN" 50 mA, RL " on
(Pulse Test, Duty Cycle ~ 3%)
04
Note 1: Unless otherwise specified, these specifications apply for V+ = 10.0V, V- = -10.0V, pin 5
grounded, over the temperature range _55°C to +125°C for the DH0035. and O°C to 85°C for the
DH0035C.
Note 2: All typical values are for T A
=
25°C.
Note 3: Derate linearly at 10 mW/oC for ambient temperatures above 25°C.
typical applications (cont.)
Grounded Anode Design
V'" IOV
--!r----~'~
SOV
r--...!'!----,
LOGIC
INPUT
I
I
I
I.
I
I
I
I
I
:
I
L
.J...
2DOpF
i
1-
71
111
I
I"
I.
Ir
1/2 OM7831l/0M88l0
120'F~
4
I
---J---~
-- ..,
I I Di~~E
I
I SWITCH
1'__ ....J
>O~I~--~~~
OHOll35
-~---
,-1
-=-
ch
120pF
Note. Anode grounded pm dIOde. RM = 56n hmlts dIOde
forward current to 100 rnA. TYPical sWitchmg for HP33622A.
RF tutn·on 5 ns, turn off 4 ns C2'" 0 l>JF,
RF turn-on 5 ns, turn off4 ns Cl = 470 pF, C2 '" 0 lJiF,
RM "on.
Alternate Current Limiting
V·
5-16
-55°C to +125"C
DH0035C
1 5W
electrical characteristics
Q
-65-'C to +150~'C
Operating Temperature Range DH0035
V-"-10DV
":"
ns
r-
s:w
...
Peripheral/Power Drivers
0)
LM3611, LM3612, LM3613, LM3614 dual peripheral drivers
general description
features
The LM3611 series of dual peripheral drivers was
designed for those applications where a higher
breakdown voltage is required than that provided
by the LM75451 series. The pin outs for the
circuits are identical to those of the LM75451 to
LM75454. The LM3611 series parts feature high
voltage outputs (80V breakdown in the "off" state)
as well as high current (300 mA in the "on" state).
Typical applications include power drivers, relay
drivers, lamp drivers, MOS drivers, and memory
drivers.
• 300 mA output current capability per driver
80V
• Hlgh·voltage outputs
• TTL or DTL compatible
• Input clamping diodes
• Choice of logic function
connection diagrams and truth .tables
LM3612
LM3611
TOP VIEW
Positive logic
TOP VIEW
Order Number LM3611 N
or LM3612N
See Package 20
AS= X
A
B
0
0
0
1
0
Q
0
1
1
1
Positive logic
OUTPUT X'
OUTPUT X'
0
0
1
1
a
1
0
·0
1
1
1
1
1
0
'''0'' Output S;; 0.7V
"1" Output S;; 100MA
*"0" Output S;; 0.7V
"1 " Output S;; 100MA
LM3613
"
LM3614
.NO
Order Number LM3613N
or LM3614N
See Package 20
TOPVI£W
Positive logic
AS= X
B
A
A+B
==
TOP VIEW
POSitive logic
X
A +8
==
X
OUTPUT X'
A
B
OUTPUT X'
A
0
0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1
0
*"0" Output S;; 0.7V
"1" Output S;; 100MA
B
'NO
"
*"0" Output S;; 0,7V
"1" Output S;; 100MA
5-17
absolute maximum ratings
Supply Voltage, Vee
Input Voltage
Output Voltage (Note 3)
Continuous Output Current
Continuous Total Power Dissipation (Note 2)
Operating Free Air Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
(Note 1)
7.0V
5.5V
80V
300mA
800mW
O°C to +70°C
-65°C to +l50°C
300°C
electrical characteristics
.
....
....
CD
(LM3611 Dual AND Peripheral Driver)
The following apply at O°C ~ T A ~ +70°C, Vee = 3.0V +5% unless otherwise specified .
LOGIC
INPUT
PARAMETER
(If)
~
OUTPUT
SUPPLY
VOLTAGE
COMMENTS
MIN
TYP
MAX
UNITS
Logical "1" Input Voltage
V ,N
475V
FIgure
t
Logical "0" Input Voltage
Y,N
475V
Figure
t
OS
V
Logical "1" Input Current
24V
5.5V
5.25V
5.25V
Figure 2
Figure 2
40
10
I'A
rnA
Logical "0" Input Current
04V
525V
Figure 3
-16
rnA
Output Low Voltage
OSV
OSV
100mA
300 rnA
475V
4.75V
Figure 1
figure 1
04
07
V
V
Output Leakage Current
20V
20V
100!lA
100!lA
4.75V
OV
Figure 1
80
Figure 1
80
Su~ply
20
V
-1.0
025
05
V
V
Currents
Output Low
OV
525V
Per Package
69
rnA
Output High
50V
525V
Per Package
Figure 4
11
mA
-12mA
50V
TA .. +25°C
-15
Figure 4
Input Clamp Diode Voltage
V
Figure 3
Propagation Delay Times. The following apply for Vee = 5 OV, TA = 25°C
Propagation to "1" (t pd1 )
INote 4)
Figure 6
130
ns
Propagation to "0" (t pdO )
INote 4)
Figure 6
125
ns
electrical characteristics
(LM3612 Dual NAND Peripheral Driver)
The following apply at O°C ~ T A ~ +70°C, Vee =5.0V +5% unless otherwise specified.
LOGIC
INPUT
PARAMETER
OUTPUT
SUPPLY
VOLTAGE
COMMENTS
MIN
TYP
MAX
UNITS
Logical "'" Input Voltage
Y,N
475V
Figure 1
Logical "0" Input Voltage
Y'N
475V
Figure 1
O.S
V
Logical "1" Input Current
24V
5.5V
5.25V
525V
Figure 2
Figure 2
40
1.0
pA
rnA
-16
mA
04
07
V
V
Logical "0" Input Current
04V
525V
Figure 3
Output Low Voltage
20V
20V
100mA
300mA
475V
475V
Figure 1
Figure 1
Output Leakage Current
OSV
lOO!lA
100!lA
475V
OV
Figure 1
Figure 1
50V
5.25V
OV
525V
Per Package
Figure 4
Per Package
oav
Supply Currents
Output Low
Output HIgh
V
20
-1.0
0.25
05
V
V
SO
SO
71
mA
14
rnA
-1.5
V
Figure 4
Input Clamp Diode Voltage
Propagation Delay Times
5-1B
-12mA
50V
TA '" +2SoC
Figure 3
The follOWing apply for Vee:::: 5 OV. T A :::: +2Soc
Propagation to "1" (t pd1 )
(Note 4)
FIgure 6
110
ns
Propagation to "0" (tpdO)
INote 41
FIgure 6
110
ns
r-
s:
electrical characteristics
(LM3613 Dual OR Peripheral Driver)
The following 'apply at O°C ~ T A ~ + 70°C, Vcc
PARAMETER
LOGIC
INPUT
Col)
Q)
SUPPLY
VOLTAGE
OUTPUT
....
....
= 5.0V +5% unless otherwise specified.
COMMENTS
MIN
TYP
MAX
V"
475V
Figure 1
Logical "0" Input Voltage
Y'N
4.75V
Figure 1
OB
V
Logical "1" Input Current
24V
5.5V
5.25V
525V
Figure 2
40
10
rnA
Logical "0" 1nput Current
O,4V
5.25V
Figure 3
-16
rnA
Output Low Voltage
o 8V
100 rnA
300 rnA
475V
475V
Figure 1
04
07
V
V
l~A
475V
OV
Figure 1
Figure 1
OV
525V
Per Package
5.0V
525V
Per Package
Logical "1" Input Voltage
0.8V
Output Leakage Current
Supply Currents
Output Low
20V
20V
100~A
20
r-
s:
UNITS
Col)
V
Figure 2
-1.0
025
05
Figure 1
Q)
....
N
~A
r-
s:
Col)
Q)
....
Col)
80
BO
V
V
73
rnA
14
rnA
-15
V
r-
s:
Col)
Q)
Figure 5
Output High
....
~
Figure 5
Input Clamp Diode Voltage
-12 mA
50V
TA == +25°C
Propagation Delay TImes The following apply for Vee = 5 OV, TA '" +25°C
Propagation to "1" (tpd1 )
(Note 4)
Figure 6
125
Propagation to "0" (tpdO)
(Note 4)
Figure 6
125
electrical characteristics
(LM3614 Dual NOR Peripheral Driver)
The following apply at O°C ~ T A ~ + 70°C, Vee
PARAMETER
LOGIC
INPUT
n'
n,
OUTPUT
= 5.0V +5% unless otherwise specified.
SUPPLY
VOLTAGE
COMMENTS
MIN
TYP
MAX
UNITS
V·
V
Logic "1" Input Voltage
Y'N
4.75V
Figure 1
Logical "0" Input Voltage
Y'N
475V
Figure 1
OB
Logical "1" Input Current
2 4V
55V
525V
5.25V
Figure 2
Figure 2
40
1.0
rnA
-16
rnA
04
0.7
V
V
Logical "0" Input Current
o 4V
525V
Figure 3
Output Low Voltage
20V
2.0V
100mA
300mA
475V
475V
Figure 1
Figure 1
Output Leakage Current
08V
08V
100pA
100pA
475V
OV
Figure 1
Figure 1
50V
5.25V
OV
525V
Per Package
Figure 5
Per Package
Supply Currents
Output Low
Output High
20
-1.0
0.25
05
~A
V
V
80
80
79
rnA
17
rnA
-15
V
Figure 5
Input Clamp Diode Voltage
-12mA
5.0V
Propagation Delay Times The follOWing apply for Vee'" S.OV, T A
'"
TA '" +25°C
Figure 3
+25°C
Propagation to "1" (tpd1)
(Note 4)
Figure 6
220
Propagation to "0" (tpdO)
(Note 4)
Figure 6
150
n,
n'
Note 1: All voltage values are with respect to ground. Positive current is defined to be current into referenced pin.
Note 2: Maximum junction temperature is 150°C. For operating at elevated temperatures, the package must be derated
based on a thermal resistance, 6JA, of 11 0° C/W.
Note 3: Maximum voltage to be applied to either output in the off state.
Note 4: Delay is measured wIth a 50n load to
1OV, 15
pF load capacitance, measured from
1.5V
input to
50%
point on output.
5-19
~
:;,
schematic diagrams
(V)
:E
"'"
(each dnver)
LM311"
J,
Duar AND Peripheral Driver
.-+_...___....---------<> v"
L---t-------~----~--~~--~--t---8
P.~kag.
20
5·27
absolute maximum ratings
INote 11
7V
5.5V
30V
300mA
820mW
O°C to +70°C
-65°C to +150°C
300°C
Supply Voltage, Vee
Input Voltage
Output Voltage (Note 4)
Continuous Output Current
Continuous Total Power Dissipation (Note 2)
Operating Free Air Temperature Range
Storage Temperature Range
Lead Temperature (soldering, 10 sec)
e lectrica I cha racteristics
PARAMETER
LOGIC
INPUT
The following apply at
OUTPU-r
ooe:s :s
SUPPl Y
VOLTAGE
TA
+70°C. Vee
= 5V + 5% unless otherwISe noted.
COMMENTS
MIN
a 7V
20
Logical "1" Input Voltage
V IN
3DOmA
475V
Output S;
Logical "0" Input Voltage
V IN
30V
475V
Output:; 100.uA
Logical "1" Input Current
2.4V
525V
TYP
MAX
UNITS
V
08
40
V
1
#A
rnA
-16
rnA
04
07
V
V
5.5V
525V
Logical "0" Input Current
0.4V
525V
Output Low Voltage
2.0V
20V
lOOmA
475V
025
300mA
475V
05
08V
30V
475V
100
#A
0.8V
30V
OV
100
#A
Per Package
61
79
rnA
525V
Per Package
13
17
rnA
5V
T A =25°C
Output Leakage Current
-1.0
Supply Currents:
Output Low
Output High
Input Clamp Diode Voltage
A, '" 5V
B, "'OV
A1 "" B, :: OV
~12mA
525V
-15
V
Propagation Delay Times. The following Apply for Vee = 5V, T A'" 25°C
t pd1 ' Input "0" to Output "1"
(Note 3)
13
35
t pd1, Input "'" to Output "0"
(Note 3)
19
35
Output Risetime
Output Falltlme
Note 1:
n,
n,
"'n,
All voltage values are with respect to ground. Positive current IS defined to be current mto referenced pm.
Note 2: Maximum Junction temperature IS 150°C. For operating at elevated temperatures, the package must be derated
based on a thermal resistance, 0JA, of 110°C/W.
Note 3: Delay IS measured with a 50ft load to lOV, 15pF load capacitance, measured from 1.5V input to 50% pOint on
output. Unused Inputs should be grounded for thiS test.
Note 4: MaXimum voltage to be applied to either output In the off state.
5·28
Display Drivers
DM5441A/DM7441A
BCD to decimal decoder/nixie* driver
general description
The DM5441AIDM7441A is monolithic blnarycoded-decimal to decimal decoder. The BCD
number to be decoded IS applied to the four
input lines; and the unique output correspond Ing
to the decimal equivalent of the input number
falls to a logical 0 level. Outputs are designed to
drive gas-filled-readout (Nixle*) tubes but are also
able to operate with other low current lamps
and re·lays.
An over-range feature provides that if binary numbers between 10 and 15 are applied to the input
the least significant bit of these numbers (0
through 5) will be decoded on the output.
logic table
connection diagram
0
INPUT
C
0
•
A
0
0
0
0
0
0
1
1
0
1
0
2
Order Number DM5441AJ
or DM7441AJ
0
0
0
See Package 17
0
1
Order Number DM7441N
0
Se. Package 23
0
1
1
0
1
1
0
0
0
8
1
0
0
1
9
0
0
Dual-I n-Line and Flat Package
.N.
Order Number DM5441AW
See Package 28
LOW OUTPUT
0
0
1
1
1
0
0
0
4
1
5
1
1
3
•
7
lOVER RANGEl
0
0
1
1
1
1
1
1
0
0
2
1
1
0
1
3
1
1
1
0
4
1
1
1
1
5
1
typical applications
Nixie* Readout
1
s'
Over-Range Decoding
INDICATOR TU8E
OVER RANGE
INDICATOR
-e-+--~c
--"-~B DMS441A/DM7441A
BCD INPUT
Note: Values for B+ and RL are as specified by the
tube manufacturer.
*Trademark of Burroughs Corporation
6-1
absolute maximum ratings
Supply Voltage (Vee!
Output Voltage
I nput Voltage
Operating Temperature Range
7.0V
70V
5.5V
_55°C to +125°C
OoC to +70°C
DM5441A
DM7441A
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
electrical characteristics
-65°C to +150°C
300°C
(Note 1)
PARAMETER
Logical 1 Input Voltage
Logical 0 Input Voltage
Logical 1 Input Current
(all inputs)
MIN
CONDITIONS
DM5441A
DM7441A
DM5441A
DM7441A
DM5441A
DM7441A
DM5441A
DM7441A
DM5441A
Logical 0 I nput Current
DM7441A
DM5441A
Supply Current
DM7441A
DM5441A
Logical 1 Output Breakdown DM7441A
Logical 1 I nput Current
Vee
Vee
Vee
Vee
Vee
Vee
Vee
= 4.5V
= 4.75V
= 4.5V
= 4.75V
= 5.5V
= 5.25V
= 5.5V
Vee - 5.25V
Vee = 5.5V
Vee - 5.25V
Vee = 5.5V
Vee
Vee
Vee
= 5.25V
= 5.5V
= 5.25V
Logical 1 Output Current
DM5441A
DM7441A
Vee
= 5.5V
= 5.25V
Logical 0 Output Voltage
DM5441A
DM7441A
Vee
Vee
= 4.5V
= 4.75V
Vee
TYP
(Note 2)
MAX UNITS
2.0
V
0.8
V IN
= 2.4V
V IN
= 5.5V
V IN
= 0.4V
V IN
= O.OV
lOUT
3
= 1.0 mA
70
40
IJA
1
mA
-1.0
-1.6
mA
21
36
mA
85
V
= 50V
125°
70°
25°
0°
_55°
60
40
1.8
1.8
1.8
IJA
lOUT = 7 mA
125°
70°
25°
0°
_55°
3.0
2.5
2.5
2.5
2.5
V
V OUT
1.4
Note 1: Unless otherwise specified 'minImax limits apply across the -5SoC to +12SoC temperature range for the DM5441A,
and the
oOe to +70o e temperature range for the DM7441A.
25°e for Vee = 5V.
Note 2: All typical, apply at
6·2
V
Display Drivers
DM5445/DM7445
DM54145/DM74145
BCD-to-decimal decoder/drivers
o
general description
The DM5442/DM7442 and DM54145/DM74145
BCD-to-decimal decoder/drivers are fully compatible for use with TTL or DTL logic circuits_ Each
circuit features full decoding of all valid BCD
input conditions (0 to 9) ensuring that all outputs
will be off for any invalid input condition_ Each
output transistor is capable of sinking 80 mAo
In the off condition each transistor can withstand
3:
c.n
...
high breakdown voltages (DM5445/DM7445 = 30V
and DM54145/DM74145 = 15V).
.j:Io
.j:Io
c.n
features
.......
o
• 210 mW typical power dissipation
• 30 ns maximum propagation delay
• Series 54/74 compatible
3:
-..I
...
.j:Io
.j:Io
c.n
logic and connection diagrams
Dual-'In-Line and Flat Package
OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPIIT
o
1
2
3
4
5
I
Order Number DM5445J, DM7445J, DM54145J or DM74145J
See Package 17
Order Number DM7445N or DM74145N
See Package 23
Order Number DM5445W, DM7445W, DM54145W
or DM74145W
See Package 28
truth table
INPUTS
DeB
o 0 0
o0 0
o 0 1
o 0 1
o 1 o
o 1 0
o 1 1
o 1 1
1 o 0
1 o 0
1 o 1
1 0 1
1 1 o
1 1 o
1 1 1
1 1 1
A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
OUTPUTS
o
o
1
1
1 0
11
11
11
11
11
1 1
11
11
11
11
11
11
11
11
2 3
4 5
11
11
o1
1 0
11
11
11
11
11
11
11
11
1 1
11
11
11
11
11
11
11
o1
1 0
1 1
1 1
11
11
11
11
11
11
1 1
11
6 7
11
1 1
1 1
11
11
11
o1
1 0
11
11
11
11
11
1 1
1 1
11
8 9
1 1
1 1
11
1 1
1 1
1 1
1 1
1 1
o1
1 0
11
1 1
11
11
1 1
11
6-3
absolute maximum ratingS(Note
operating conditions
1)
Supply Voltage
Input Voltage
Output Voltage
7V
55V
DM5445/DM7445
30V
DM54145/DM74145
15V
Operatl n9 Temperature Range
DM5445.DM54145 _55°e to +125°e
oOe to +70 o e
DM7445.DM74145
Storage Temperature Range
_65°e to +150 o e
Lead Temperature (Soldenng, 10 sec)
300 0 e
Supply Voltage (Veel
DM5445.DM54145
DM7445.DM74145
MIN
MAX
UNITS
4.5
475
5.5
5.25
V
V
electrical characteristics (Note 2)
CONDITIONS
PARAMETER
TYP
MIN
MAX
UNITS
V
Logic "1" I nput Voltage
08
LogIc "0" Input Voltage
Output Breakdown Voltage
Vee = Max. 10FF = 250pA
Vee = Max. 10FF = 250pA
Logical "0" Output Voltage
Vee::: Min, lOUT = 80 rnA
Vee::: Min, lOUT = 20 mA
Logical "1" Input Current
Vee::: Max, VIN = 24V
Vee -=- Max, V IN ::: 5 5V
Logical "0" Input Current
Vee = Max, Y'N
Supply Current
Vee = Max
Vcc=Max
=
30
15
V
V
05
02
09
04
a 4V
tpdO
Propagation Delay to a Logical "1"
Vee = 50
TA=25°C
e L = 15pF
pA
1
rnA
~
62
70
Input Clamp Voltage
Propagation Delay to a Logical "0",
40
-1
42
42
DM5445/DM54145
DM7445/DM74145
rnA
rnA
rnA
-1 5
V
RL = lOOn
17
30
ns
Vee = 5 0
T A = 25°C CL = 15 pF RL = lOOn
18
30
ns
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the deVice cannot be guaranteed Except
far "Operating Temperature Range"·they are not meant to Imply that the deVices should be operated at these limits The table
of "Electrical Characteristics" prOVides conditions for actual deVice operation.
Note 2: Unless otherWise speCified mm/max limits apply across the -5SoC to +125°e temperature range for the DM5445,
DM54145 and across the oOe to 70 0e range for the DM7445,DM74145 All tYPlcals are given for Vee'" 5 OV and T A '" 2SoC
ac test circuit and switching time waveforms
90%
INPUT
ov~
I._I
J
'%
3."
15V
15V
f-
OUTPUT -
~
f--
,----
\'5V
A
15V
,,,,,_~'_,~,
OUTPUT
_~c:-~
I~,- - -I ~
15V
FREnUENCY = 1 MHz
DUTVCYCLE=50%
t, =tf '" 10 n$
6-4
V
V
Display Drivers
DM5446A/DM7446A
DM5447A/DM7447A
DM5448/DM7448
BCD-to-7-segment decoder/drivers
general description
This versatile series of 7-segment display drivers
fulfills a wide variety of requirements for most
active high (common cathode) and active low
(common anode) Light Emitting Diodes (LED)
or lamp displays. Each device fully decodes a
4-bit BCD input into a number from 0 through 9
in the standard 7-segment display format, and
BCD numbers above 9 Into unique patterns that
verify operation. All circuits operate from a
single 5.0V supply.
The DM5446A/DM7446A has active-low, opencollector outputs that will drive segments requiring
up to 40 mA of current. The outputs are capable
of withstanding 30V at a maximum leakage current
of 2501lA. This configuration is particularly well
suited for common anode LED displays or higher
voltage lamp displays. The high sink current
capability also allows this circuit to be used in
the multiplex or nonmultiplex mode of display
drive. In addition, the device may be used to
drive logic circuits since its normalized fanout
is 25.
The DM5447 A/DM7447 A has tne same output
characteristics as the DM5446A/DM7446A except
that the outputs withstand 15V at a maximum
leakage current ot2501lA. Since its output configuration IS the same as the DM5446AIDM7446A
ItS applications will also be the same, the only
restriction is that a lower voltage type display be
used because of the reduced output voltage limit
of 15V.
The DM5448/DM7448 has active-high, passivepull up outputs with a fanout of 4. Typical source
current is 2.0 mA at an output voltage of 0.85V.
The sink capability is 6.4 mA at a maximum
voltage of O.4V. It is normally used to drive logic
circuits, operate high-voltage loads such as electroluminescent displays through buffer transistors or
SCR switches, and in low current common cathode
Non-Multiplex LED applications.
features
•
•
Lamp-test input
Leading/trailing zero suppression (RBI and
•
Blanking iriput, that may be used to modulate
lamp intensity or inhibit output
RBO)
• TTL and DTL c~mpatible
• Input clamping diodes
connection diagrams
Dual-in-Line and Flat Package
Dual-I n-Line and Flat Package
DM5446A!DM7446A,
DM5447AIDM7447A
DM5448/DM7448
~
INPUTS
~~~i OU~~UT IN~~T
~
~
INPUTS
INPUTS
TOP VIEW
~~~i OU~:UT IN~~T
~
UNO
INPUTS
TOP VIEW
Order Number DM5446AJ, DM7446AJ,
DM5447AJ, DM7447AJ, DM5448J,
or DM7448J
Order Number DM5446AN, DM7446AN,
DM5447AN, DM7447AN, DM5448N,
or DM7448N
Order Number DM5446AW, DM7446AW,
DM5447AW, DM7447AW,
DM5448W or DM7448W
See Package 17
See Package 23
See Package 28
6·5
absolute maximum ratings
(Note 1)
operating conditions
MIN
Supply Voltage
I nput Voltage
7.0V
5.5V
-65°e to +150o e
Storage Temperature Range
300°C
Lead Temperature (Soldering, 10 seconds)
MAX
Supply Voltage (Vee)
DM5446A, DM5447 A, }
DM5448
4.5
DM7446A,DM7447, }
DM7448
4.75
Temperature (T A)
DM5446A, DM5447 A,} -55
DM5448
DM7446A, PM7447A,} 0
DM7448
Output Voltage
DM5446A,DM7446A
OM5447A,DM7447A
DM5448, DM7448
UNITS
5.5
V
5.25
V
+125
°c
+70
°e
30
15
5.5
V
V
V
40
6.4
mA
mA
mA
MAX
UNITS
Output Sink Current (per segment)
DM5446A,DM7446A,
DM5447A,DM7447A
DM5448, DM7448
electrical characteristics
40
(Note 2) The following is applicable to all parts.
PARAMETER
CONDITIONS
MIN
Logical "1" Input Voltage
TYP
2.0
V
Logical "0" Input Votlage
0.8
Logical "1" Output Voltage
BI/RBO Node
Vee = Mm, lOUT = -200JJA
Logical "0" Output Voltage at
BI/RBO Node
Vee = Min, liN = 8.0 mA
2.4
V
37
V
0.4
V
Vee = Max, V IN = 2.4V
Vee = Max, V ,N = 5.5V
40
1.0
JJA
mA
Logical "0" Input Current
(Except BI/RBO Node)
Vee = Max, V ,N = OAV
-1.6
mA
Logical "0" Input Current
BI/RBO Node
Vee = Max, V IN = OAV
-4.2
mA
Output Short CirCUit Current at
BI/RBO Node
Vee = Max
-4.0
mA
Input Clamp Voltage
Vee = 5.0V, T A = 25°C, liN = -12 mA
-1.5
V
Logical "1" Input Current at any
Input Except BI/RBO Node
0.3
output characteristics and supply current
DM5446AiDM7446A, DM5447A/DM7447A (Note 2)
PARAMETER
Logical "1" Output Voltage
Outputs a through g
DM5446A, DM7446A
DM5447A, DM7447A
Logical "0" Output Voltage
Outputs a through g
Supply Current
DM5446A, DM5447A
DM7446A, DM7447A
6·6
CONDITIONS
Vee = Max, lOUT = 250JJA
MIN
TYP
MAX
UNITS
V
V
30
15
Vee = Min, lOUT = 40 mA
03
04
Vee = Max
60
60
85
103
V
mA
mA
output characteristics and supply current
DM5448/DM7448 (Note 2)
PARAMETER
Logical "1" Output Voltage
Outputs a through g
DM5448, DM7448
CONDITIONS
MIN
TYP
2.4
3.2
Vee = Min, lOUT =-400/JA
MAX
UNITS
V
Logical "0" Output Voltage
Outputs a through g
Vee = Min, lOUT = 6.4 mA
Logical ''1'' Load Current
Available, Outputs a through g
Vee = Min, V OUT = 0.85V
Output Short Circuit Current
Outputs a through g (Note 3)
Vee = Max
-3.0
-4.0
mA
Vee = Max
50
50
76
90
mA
mA
Supply Current
DM5448
DM7448
0.25
-1.3
V
0.4
-2.0
mA
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed.
They are not meant to Imply that the deVices should be operated at these limits. The table of "Electrical Characteristics"
provides condlttOns for actual dev'lce operation.
Note 2: Unless otherWise specified minImax limits apply across the -55°C to +12SoC temperature range for DM5446A,
DM5447A, and DM5448, and across the O°C to +70°C range for DM7446A, DM7447A, and DM7448. All typicals are given
for VCC = 5.0V and TA = 25°C.
switching characteristics
DM5446A/DM7446A, DM5447A/DM7447A, DM5448/DM7448 (VCC
CONDITIONS
PARAMETER
Propagation Delay to a Logical "0"
from A Input to any Output (tpdO)
DM5446A/DM7446A
DM5447A/DM7447A
DM5448
DM7448
= 5.0V,
MIN
TA
= 25°C)
TYP
MAX
UNITS
{ CL
RL
CL
CL
= 15 pF
= 120n
= 15pF, RL = lkn
= 15 pF, RL = 667n
100
100
100
100
ns
ns
ns
ns
{ CL
RL
CL
CL
= 15 pF
= 120n
= 15pF, RL = lkn
= 15 pF, RL = 667n
100
100
100
100
ns
ns
ns
ns
{CL
RL
CL
CL
= 15 pF
= 120n
= 15 pF, RL = 1kn
= 15 pF, RL = 667n
100
100
100
100
ns
ns
ns
ns
{ CL = 15 pF
RL = 120n
CL = 15pF, RL = lkn
CL = 15 pF, RL = 667n
100
100
100
100
ns
ns
ns
ns
Propagation Delay to a Logical "0"
from RBI to any Output (t pdO )
DM5446A/DM7446A
DM5447A/DM7447A
DM5448
DM7448
Propagation Delay to a Logical "1"·
'from A Input to any Output (t pd1 )
DM5446A/DM7446A
DM5447A/DM7447A
DM5448
DM7448
Propagation Delay to a Logical "1"
from RBI to any Output (t pd1 )
DM5446A/DM7446A
DM5447 A/DM7447 A
DM5448
DM7448
6·7
truth tables
DM5446A/DM7446A. DM5447A/DM7447A
I
INPUTS
OUTPUTS
DECIMAL
OR
FUNCTION
LT
RBI
D
C
B
A
ai/Reo
I
1
X
2
3
4
5
6
1
X
1
X
7
1
8
1
X
X
9
10
11
1
1
X
12
1
X
13
1
X
0
0
1
1
0
0
1
L
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
1
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
0
X
X
0
X
0
X
X
0
1
1
X
i
x
1
X
14
1
X
15
1
X
BI
X
RBI
1
0
X
0
X
LT
1
,
0
1
0
0
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
0
0
0
1
1
0
1
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
X
0
X
1
b
0
0
0
0
0
1
1
0
0
0
1
1
0
1
1
1
1
1
0
,
0
0
1
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
0
d
.
f
0
1
1
1
0
0
0
1
0
0
1
1
1
0
1
0
1
1
1
0
1
0
1
0
1
1
1
0
1
1
1
0
1
0
"
1
1
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
0
0
0
1
,
NOTE
1
,1
1
0
0
0
0
0
1
0
0
,0
1
0
0
0
0
1
1
1
0
2
3
4
Note 1: SI/RBO IS wire-AND logiC serving as blanking Input (BI) and/or ripple-blanking output (RBO), The blanking Input (BI)
must be ·open or held at a logical 1 when output functions' 0 through 15 are deSired, and the ripple-blanking Input (RBIl
must be open or at a logical 1 if blanking of a deCimal 0 IS not deSired. X'" input may be high or low.
Note 2: When a logical 0
IS
applied directly to the blanking mput (forced condition) all segmen] outputs go to a logical 1
regardless of the state of any other input conditIOn
Note 3: When the ripple-blankIng mput (RBI) and inputs A,
an
a,
C, and 0 are at logical 0, with the lamp test input at loglcall,
segment outputs go to a logical 1 and the npple-blanklng output (RBO) goes to a logical 0 (response condition).
Note 4: When the blanking Input/npple-blanklng output (BI/RBO) IS open or held at a logical 1, and a logical 0 is applied to
the lamp-test input, all segment outputs go to a logical O.
DM5448/DM7448
I
INPUTS
DECIMAL
OR
FUNCTION
OUTPUTS
.
LT
R81
D
C
B
A
BI/RBO
,
b
,
d
f
9 NOTE
0
1
1
0
0
1
1
1
1
1
1
1
1
1
X
1
X
X
1
0
1
0
1
0
1
1
2
3
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
0
0
0
1
1
1
0
1
0
0
1
1
1
1
5
6
7
1
X
X
1
X
1
X
8
1
X
9
1
X
0
0
0
0
0
0
0
0
1
1
10
11
1
X
I
1
1
X
X
1
1
X
X
1
14
1
1
15
1
81
X
1
0
X
X
4
12
13
RBI
LT
1
1
0
X
1
1
X
0
X
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
0
X
0
1
1
0
0
1
1
X
0
X
1
1
1
1
1
1
0
1
0
1
1
1
1
1
0
1
1
0
0
0
0
1
0
1
X
0
X
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
1
1
1
0
1
1
0
0
1
1
1
0
0
1
0
0
0
0
0
1
1
1
1
1
1
0
1
1
0
1
0
0
0
0
0
0
1
0
1
1
0
1
1
0
0
0
1
0
1
0
0
0
1
0
0
0
1
1
0
0
1
1
1
0
0
0
1
1
1
1
0
1
1
1
1
1
1
1
0
0
0
1
2
3
4
Note 1: BI/RBO IS wire-AND logiC serving as blanking input (Bt) and/or ripple-blanking output (RBO). The blanking input (BI)
must be open or held at a logical 1 when output functions 0 through 15 are deSired, and the ripple-blanking input (RBI)
must be open or at a logical 1 If blanking of a deCimal 0 IS not deSired. X::: Input may be high or low.
Note 2: When a logical 0 IS applied directly to the blanking Input (forced condition) all segment outputs go to a logical 0
regardless of the state of any other Input condition.
Note 3: When the npple-blanking input (RBI) and Inputs A, S, C, and D are at logical 0, with the lamp test at logical 1 all
segment outputs go to the logical 0 and the npple blanking output (RBO) goes to a logical 0 (response condition).
Note 4: When the blanking mput/npple-blankmg output (RI/RBO)
the lamp-test mput, all segment outputs go to a logical 1.
IS
open or held at a logical 1, and a logical 0 is applied to
output display
,l-:-*!b
'1 7'
d
SEGMENT IDENTIFICATION
NUMERICAL DESIGNATIONS - RESULTANT DISPLAYS
6-8
output stage schematics
OUTPUTS
a THROUGH g
DM5448/DM7448
DM5446A/DM7446A
DM5447A/DM7447A
ac test circuit
Ii ,---
INPUT
VccO--.------------1>-------,
OUTPUT
-1
I
R,
I
<>+---+
r----- --------1
II
I I
I I
I I
Te'll
I
.". II
I LOAD CIRCUIT fOR I 1
U~j;~;~.u L
INJOS4
R,
lNJ064 lN3064 lN3064
T.".e,
I
I
I
I
I
I
I
____ ~~a~:~ ____ J
LOAD CIRCUIT FOR
switching time waveforms
TYPiCALINPur
WA~~~!~:
(--:::--------~){..,~v
~"NOTE"
VOLTAGE
WAVEFORMS
:,~:
-----------"',
~v
INPUTS B, C, OR 0
"PlCAlO'T'UT
______________
~~:-------------VINIIl
~(SEENOTE21
I
~':~-------------.::'"
[----+--'1'__
'~V
-+_-..
_ _ _ _ _ _ _ _ _ _ _ v""m
________
__________
-VOUTlll
15V
..
~--------V""'
r-tpclO
A Input to Outputs
-----------------
~==:~~=:;:;~=~:::-------""'''
INPUTS A, B, C AND 0
"
~--------------Vl'-l(el
~=:::~g~:~~~==------------~",
..
--------VINIII
15V
~
R811NPUT
~--------VINrol
I
[
OUTPUTi
DM5446A/DM7446A _ _ _ _ _ _ _ _
_
DM::::::::___________
'~"'~
/ -"15V
v,,""
+_-'
____
IL
~~-----~~::::,~:
t.,dlOl--l
VouT!Cn
RBI Input to Outputs
Note 1 The tfutb table generator and pul,e generator have the followmg charactenstlcs·
VOUT(1 ) 2: 24V, VO~T(o) :::;; 04V, t, and tt s;; 10 ns, and PRR '" 1 0 MHz
Note 2 Inputs B, C, and 0 transItIOns Occur simultaneousiv With or prIOr to mput A
tranSItIOns RBI" 4.SV.
Note 3 CL Includes probe and JIg capacItance.
6·9
Display Drivers
DM54141/DM74141
BCD to decimal decoder/driver
general description
The DM54141/DM74141 is a second-generation
BCD to decimal decoder designed specifically to
drive cold cathode indicator tubes. This decoder
demonstrates an improved capability to minimize
switching tra'nsients in order to maintain a stable
display.
Full decoding is provided for all possible input
states. For binary inputs 10 through 15, all the
outputs are off. Therefore the DM54141/DM74141,
combined with a minimum of external circuitry,
can use these invalid codes in blanking leadingand/or trailing-edge zeros in a display as shown in
the typical application data. The ten high-performance NPN output transistors have a maximum
reverse current of 50MA at 55V.
Low-forward-impedance diodes are also provided
for each input to clamp negative-voltage transitions
logic diagram
in order to minimize transmission-line effects.
Power dissipation is typically 55 mW, which is
about one-half the power requirement of earlier
designs.
features
•
Drives cold cathode numeric indicator tubes
directly
•
Low leakage current at 55V
•
Low power dissipation of 55 mW typ
•
Fully decoded inputs ensure all outputs off
for invalid codes
•
Input clamp diodes for minimizing transmission
line effects
50MA max
connection diagram
Dual-In-Line and Flat Packag.
OUTPUTS
OUTPUTS
A (3)
B (8)
C (7)
o (4)
6-10
~~
OUTPUTS
Vee
INPUTS
TOP VIEW
B
C
2
~ OUTPUT
Order Number DM54141J or DM74141J
See Package 17
Order Number DM74141N
See Package 23
Order Number DM54141Wor DM74141W
See Package 28
c
absolute maximum ratings
Supply Voltage
Input Voltage
Output Voltage
7.0V
5.5V
60V
Storage Temperature Range
-B5°e ta +150oe
300°C
Lead Temperature (Soldering, 10 seconds)
electrical characteristics
3:
......
......
operating conditions
(Note 1)
Supply Voltage, Vee
DM74141
DM54141
U1
~
MIN
MAX
UNITS
4.75
4.5
5.25
5.5
V
V
~
C
3:
.....
......
Temperature, T A
DM74141
DM54141
0
-55
~
°e
°e
+70
+125
~
(Notes 2 and 3)
PARAMETER
CONDITIONS
MAX
UNITS
0.1
40
80
mA
08
V
-16
-3.2
mA
mA
-15
V
~A
Vee = Max, Vo = 30Y Input States 10-15
50
50
= 7.0 rnA
25
V
25
mA
Loglcal "1" Input Voltage (V tH )
Vee = Mm
Logical "1" Input Current (t IH 1
A Input
S, C, or 0 Input
Vee = Max, V 1H
Vee"" Max, V 1H
Vee'" Max, V 1H
Logical "0" Input Voltage (V1d
Vee
MIN
TYP
20
Y
5 5V
'" 2.4V
= 24V
""
= Min
~A
~A
Logical "0" Input Current (11Ll
A Input
8, C, or 0 Input
= DAV
= D.4V
Vee"'" Max, V 1L
Vee = Max, V 1L
Input Clamp Voltage (V CD)
Vee'" Mm, leo = -12 rnA
Logical "1" Output Voltage (V OH )
Vee = Max, IOH
Logical "1" Output Current
Vee
(lOH
1
= 0 5 rnA
= Max. Vo
Logical "0" Output Voltage (VoLl
Vee
=
Supply Current (Ieel
Vee
= Max, All
=
Mm, IOL
60
V
55V
Inputs GND, All Outputs Open
11
~A
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to Imply that the devices should be operated at these limits. The table
of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified minimax limits apply across the -55°C to +125°C temperature range for the DM54141 and
acrass the DoC ta +70oe range for the DM74141. All typicalsare given far Vee = 5.0V and T A = +25°e.
Note 3: All currents into device pins shown as positive, out of device pins as negative, alt voltages referenced to ground unless
otherwise noted. All values shown as max or min on absolute value basis.
truth table
INPUT
A
OUTPUT
ONt
L
L
0
L
H
1
L
2
L
H
H
H
3
L
H
L
L
4
L
H
L
H
L
L
H
H
L
5
6
H
H
H
7
H
L
L
L
8
H
L
L
H
9
H
L
H
L
NONE
H
L
H
H
NONE
H
H
L
L
NONE
H
H
L
H
NONE
H
H
H
L
NONE
H
H
H
H
NONE
0
C
B
L
L
L
L
L
L
L
H - high level, L - low level
t All other outputs are off
6·11
Display Drivers
p-
en
o:t
It)
~
DM75491 MOS-to-LED quad segment driver
C
DM75492 MOS-to-LED h~x digit driver
features
general description
•
The OM75491 and OM75492 are interface circuits
designed to be used in conjunction with MOS
integrated circuits and common-cathode LED's in
serially addressed multi-digit displays_ The number of drivers required for this time-multiplexed
system is minimized as a result of the segmentaddress-and-digit-scan method of LED drive_
Source or sink capability
per driver (DM75491)
50 mA
• Sink capability per
driver (DM75492)
250 mA
•
MOS compatability (low input current)
•
Low standby power,
• High-gain Darlington circuits
schematic and connection diagrams
DM75491 (each driver)
DM75492 (each driver)
(14,3,5,8,10,12)
(1,7,8,14)
..._---t(1,2,6, 7,9, 13)
• -'-'V+ollr-+-t
(11)
TO OTHER
DRIVERS
v"
/41
TO OTHER
DRIVERS
141
GNO
GNO
DM75491 Dual-In-Line Package
4.
4E
4C
IE
lC
DM75492 Dual-In-Line Package
V"
3.
3E
3.
,.
,v
6A
GN.
2.
"
2A
IV
2V
2A
v"
5A
5V
4.
GN.
3.
3V
4V
14
,.
TOPVIEW
Order Number DM75491J or DM75492J
See Package 16
Order Number DM75491N or DM75492N
See Package 22
6-12
TOP VIEW
absolute maximum ratings
Input Voltage Range (Note 1)
Collector Output Voltage (Note 2)
Collector Output to Input Voltage
Emitter to Ground Voltage (VI ~ 5V)
Emitter to Input Voltage
Voltage at Vss Terminal With Respect to
Any Other Device Terminal
Collector Output Current
Each Collector Output
All Collector Outputs
Continuous Total Dissipation
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
DM75491
DM75492
-5V to Vss
10V
10V
10V
5V
-5V to Vss
10V
10V
10V
10V
50mA
200mA
800mW
O°C to +70°C
-65°C to +150°C
300°C
250mA
600mA
OOOmW
O°C to +70°C
-65°C to +150°C
300°C
dc electrical characteristics
DM75491 (Vss = lOY, TA = O°c to +70°C unless otherwise noted)
PARAMETER
CONDITIONS
On State-Collector Emitter Voltage (V CE
ON)
TVP
MIN
Input'" 8 5V through 1 kn, V E
Ie SOmA. TA "" 2SoC
'"
5V,
MAX
UNITS
12
.9
V
0:;
On State Collector Emitter Voltage (V CE ON)
Input"" 8.5V through 1 kn, V E '" 5V,
Ie "'50mA
Off State Collector Current (I C OFF)
VC '" lOV, V E ,"" D, liN'" 4O.uA
Off State Collector Current (Ie
Vc'" lOV, V E
OFF)
""
VIN '" lOV, VE =: D, Ie = 20 rnA
Emitter Reverse Current (IE)
V IN
""
V
~A
~A
100
0, VIN '" .7V
Input Cunent at MaXimum Input Voltage (I,)
=0. V E
1.5
100
2.2
mA
3.3
5V, Ie ""0
100
~A
1
mA
Current Into Vss Terminal (Iss)
DM75492 (VSS = lOY, TA = O°C to +70°C unless otherwise noted)
CONDITIONS
PARAMETER
Low Level Output Voltage (VOL)
MIN
TVP
Input"" 6 5V through 1 kn., lOUT"" 250 rnA
MAX
.9
TA "" 2SoC
1.2
V
1.5
V
Low Level Output Voltage (VOL)
Input:::: 6 5V through 1 kn, lOUT:::: 250 mA
High Level Output Current (loHl
V OH :::: lOY, liN:::: 40.uA
200
High Level Output Current (tOH)
V OH '" lOY, VIN :::: .5V
200
Input Current at MaXimum Input Voltage (II)
VIN :::: 10V, IOL = 20 mA
2.2
UNITS
~A
~A
mA
mA
3.3
1
Current Into Vss Terminal (Iss)
ac switching characteristics
DM75491 (Vss = 7.5V, T A = 25°C)
PARAMETER
CONDITIONS
Propagation Delay Time, Low to High Level Output (Collectod (tPLH)
V IH =45V,V E =0,
Propagation Delay Time, High to Low Level Output (Collecto'd (tPHLl
RL :::: 2000, C L :::: 15 pF
DM75492 (VSS
MIN
TVP
MAX
UNITS
100
ns
20
ns
= 7.5V, TA = 25°C)
PARAMETER
CONDITIONS
Propagation Delay Time, Low to High Level Output (tPLH)
Propagation Delay Time, High to Low Level Output (tPH L)
MIN
VIH '" 7.5V, RL :::: 39n,
.!
CL :::: 15pF
TVP
MAX
UNITS
300
ns
30
ns
Note 1: The input is the only device terminal which may be negative with respe~t to ground.
Nota 2: Voltage values are with respect to network ground terminal unless otherwise noted.
6-13
N
Q)
~
,....
ac test circuits and switching time waveforms
:E
o
75V
75V
Rt =39.2
........O""--....-OUT'UT
:x>-"....._OUTPUT
J
DM75492
DM75491
1--$
---I
i
1
~"",--:;=I:--I--
10 AS
- - - - - - - - V1H
1
1
INPUT
I
~"'------'V
r----Vo,
OUTPUT
!
'-__-+_....L_ -}------1
1
I
I
1
I
VOL
~tPLH-I
NOTE 1 THE PULSE GENERATOR HAS THE fOLLOWING CHARACTERISTICS
PRR'" 100 KHz,tw =l,us.
NOTE 2· CL INCLUDES PROSE AND JIG CAPACITANCE
6-14
lOUT
= SOn.
CI,.=15pF
(NOTE21
Display Drivers
DM75493 quad LED segment driver
general description
features
The OM75493 is a quad LED segment driver. It
is designed to interface between MOS IC's and
LED's. An external resistor is required for each
segment to drive the output current which is
approximately equal to O.7V/RL and is relatively
con.tant, independent ot supply variations. Blank·
ing can be achievecj by taking the chip enable
(CE) to a logical "1" level.
•
Low voltage operation
•
Low input current for MOS compatibility
•
Low standby power
•
Display blahking capability
•
Output current regulation
•
Quad high gain circuits
logic and connection diagram
Dual-In-Line Package
Vss
OUT,
REF,
IN,
IN2
REF:!
OUT2
GND
TOP VIEW
Order Number DM75493J
Order Number DM75493N
See Package 17
See Package 23
switching time waveforms
truth table
v"
V'N
-2.IV---=:-"0---0-+-0
,%
~~c,
Vou ,
""'T'20pF
.L ±10%
6·18
o
3:
Display Drivers
Oil
U1
0)
.......
o
3:
00
00
U1
DM7856/DM8856. DM8857. DM7858/DM8858
BCD-to-7-segment LED drivers
0)
general description
o
This series of 7-segment display drivers fulfills a
wide variety of requirements for most active high
(common cathode) Light Emitting Diodes (LEDs).
Each device fully decodes a 4-bit BCD input into
a number from 0 through 9 in the standard 7segment display format, and BCD numbers above
9 into unique patterns that verify operation. All
circuits operate off of a single 5.0V supply.
3:
In addition, with the use of an external current
limit resistor per segment, this circuit can be used
in higher current nonmultiplex LED applications.
00
00
~
The DM7858/DM8858 has active high outputs
with source current adjustable with the use of
external current limit resistors, one per segment.
This feature allows extreme flexibility in source
current value selection for either multiplex or
non-multiplex common cathode LED drive applications. It allows the system designer freedom to tailor
the drive current for his particular applications.
The DM7856/DM8856 has active-high, passive
pull-up outputs which provide a typical source
current of 6.0 mA at an output voltage of 1. 7V.
The applications are the same as for the DM5448/
DM7448 except that more design freedom is
allowed with higher source current levels. This
circuit was designed to drive the MAN-4 or equivalent type display directly without the use of
external current limit resistors.
o
3:
Oil
U1
00
.......
o
3:
00
00
U1
00
features
•
•
Lamp-test input
Leading/trailing zero suppression (RBI and
RBO)
• Blanking Input that may be used to modulate
lamp intensity or inhibit output
• TTL and DTL compatible
• Input clamping diodes
The DM8857 has active-high outputs and is designed to be used with common cathode LED's
in the multiplex mode. It provides a typical source
current of 50 mA at an output voltage of 2.3V.
connection diagram
Dual-In-Line and Flat Package
OUTPUTS
VI
11
1 J iii I
-
II II I I
B
RI
r
OUTPUT
IIIIPUT
· l' -'-' J.'
CLAMP
TEST
~
INPUTS
t' !' J.'
RI
0
A
GND
------INPUTS
TOP VIEW
Order Number DM7856J, DM8856J,
DM8857J, DM7858J, DM8858J
Order Numbar DM7856N, DM8856N,
DM7858N or DM8858N
Ordar Number DM7856W, DM8856W,
DM7858Wor DM8858W
See Package 17
Sea Package 23
See Package 28
output display
,C1.
'0'
•
SEGMENT IDENTifiCATION
101 /12131'-{/sJs/7/BlqJ::/~/L1~/t:1 1
•
I
Z
3
4
Ii
B
1
•
8
10
11
12
13
'4
Ii
IIUMERICAL DESIGNATIONS - RESULTANT DIIPlAYS
6-19
00
Ln
00
00
absolute maximum ratings
.......
Supply Voltage
I nput Voltage
~
C
(Note 1)
7.0V
5.5V
Storage Temperature Range
-65°C to +150o e
Lead Temperature (Soldenng, 10 seconds)
300°C
00
Ln
~
operating conditions
Supply Voltage (Vee)
DM7856, DM7858
DM8856, DM8857, }
DM8858
~
C
Temperature (TA)
DM7856, DM7858
DM8856, DM8857, }
DM8858
"
Ln
00
00
~
C
MIN
MAX
4.5
5.5
V
4.75
5.25
V
-55
+125
°e
0
+70
°e
Output Voltage
All CircUits
5.5
V
Output Sink Current (per Segment)
DM7856, DM8856
6.4
mA
60
mA
mA
Output Source Curre!')t (per Segment)
DM8857
DM7858, DM8858
(£)
UNIT!!
50
Ln
00
00
~
c
.......
electrical characteristics
(£)
(Note 2) The following is applicable to all parts.
Ln
~
PARAMETER
~
C
CONDITIONS
MIN
Logical "1" Input Voltage
TYP
MAX
UNITS
2.0
V
Logical "0" Input Votlage
0.8
Logical "1" Output Voltage
BI/RBO Node
Vee = Min, lOUT = -2001lA
Logical "0" Output Voltage at
BI/RBO Node
Vee = Min, liN = 8.0 mA
V
37
24
V
0.3
0.4
V
"
Logical "1" Input Current at any
Input Except BI/RBO Node
Vee = Max, V ,N = 2.4V
Vee = Max, V ,N = 5.5V
40
1.0
IlA
mA
Logical "0" Input Current
(Except BI/RBO Node)
Vee = Max, V ,N = O.4V
-1.6
mA
Logical "0" Input Current
BI/RBO Node
Vee = Max, V ,N = O.4V
-4.2
mA
Vee = Max
-4.0
mA
Vee = 5.0V, TA = 25°C, liN =-12mA
-1.5
V
Output Short Circuit Current at
BI/RBO Node
Input Clamp Voltage
output characteristics and supply current
DM7856/DM8856 (Note 2)
PARAMETER
Vee
Logical "1" Load Current
Available, Outputs a through g
Vee = 5 OV, V OUT = 1.7V
Output Short CirCUit Current
Outputs a through g (Note 3)
Supply Current
DM7856
DM8856
6·20
CONDITIONS
Logical "0" Output Voltage
Outputs a through g
= Mm,
MIN
TYP
MAX
UNITS
0.4
V
-u0
-7.5
mA
Vee = Max
-12
-15
mA
Vee = Max
90
90
lOUT
0.25
= 6.4 rnA
-4.7
120
130
mA
mA
c
s:
output characteristics and supply current (con't)
~
U'I
DM8857, DM7858/DM8858 (Notes 2 and 3)
0)
.......
MIN
CONDITIONS
PARAMETER
Logical "1" Load Current
Available, Outputs a through g
DM8857
DM7858 (Note 4)
DM8858 (Note 4)
Vee ~ 5.0V, V OUT ~ 23V
Vee ~ 5 OV, lOUT ~ -50 rnA
Vee ~ 5 OV, lOUT ~ -50 rnA
Supply Current
Vee;::: Max
TYP
UNITS
MAX
-40
-60
2.9
s:
00
00
rnA
V
32
32
27
C
U'I
0)
V
60
c
s:
00
rnA
00
U'I
"'-I
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed.
They are not meant to imply that the devices' should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
c
Note 2: Unless otherwise specified mmlmax limits apply across the -5SoC to +12SoC temperature range for DM7856,
and OM7858 and across the O°C to +70°C range for OM8856, DM8857, and OM8858. All tYPlcalsare given for VCC ~ S.OV
and TA ~ 2SOC.
s:
Note 3: Care must be taken in not shorting the outputs to ground while they are In the "1" state because excessive current
flow would result from the Darlington upper stages.
U'I
~
00
Note 4: Special care must be taken In the use of the DM7858 ceramic (J) and the DM88~8 plastic (N) DIP'swith regard to
not exceeding the maximum operating junction temperature of the devices. The maximum junction temperature of the
DM7858J IS 150°C and must be derated based on a thermal resistance of 80°C/watt, junction to ambient. The maximum
junctlor) temperature for the DM8858N IS 150°C and must be derated based on a thermal resistance of 140°C/watt junction
to ambient.
.......
C
s:00
00
U'I
00
truth table
I
INPUTS
OUTPUTS
DECIMAL
OR
C
X
o
o
o
o
o
0
X
o
1
X
o
1
RBI
FUNCTION
LT
o
1
1
1
1
X
2
1
X
3
1
4
1
5
1
B
A
Bl/RBO
0
o
0
1
1
1
1
1
1
0
o
1
1
0
1
1
o
o
0
1
0
1
1
1
o
1
1
o
1
1
1
1
1
1
1
1
o
o
1
o
0
1
0
1
1
o
o
1
1
o
1
1
1
o
1
1
o
1
1
a
b
d
9
NOTE
1
o
1
o
o
1
6
1
X
o
1
1
0
1
0
o
1
1
1
1
1
7
1
X
o
1
1
1
1
1
1
1
o
o
o
o
8
9
1
X
o
o
1
1
1
1
1
1
1
1
X
1
1
1
1
1
o
o
1
1
10
1
X
0
0
0
0
0
1·
1
0
1
0
o
o
1
1
1
1
1
1
0
o
1
1
1
0
1
0
1
o
1
1
1
1
1
o
o
o
1
o
o
o
o
o
1
1
o
o
1
1
1
1
o
o
o
o
o
o
o
o
o
o
o
o
o
1
1
1
1
1
11
1
X
1
1
1
1
12
1
X
1
1
13
1
X
1
1
o
o
14
1
X
1
1
1
0
1
0
15
1
X
1
1
1
1
1
0
X
0
X
X
X
0
0
o
0
0
0
o
o
o
o
X
X
1
1
1
BI
X
X
X
RBI
1
o
o
LT
o
X
X
o
2
3
4
Note 1: BI/ABO IS wlre~AND logic serving as blanking Input (Btl and/or rlppJe~blanking output (RBO). The blanking Input (BI)
must be open or held at a logical 1 when output functions 0 through 15 are desired, and the npple~blanklng Input (RBI)
must be open or at a logical 1 If blanking of a decimal 0 IS not desired. X = Input may be high or low.
Note 2: When a logical 0 IS applied directly to the blanking Input (forced condition) all segment outputs go to a logical 1
regardless of the state of any other mput condition
Note 3: When the npple~blanking Input (RBI) and Inputs A, B, C, and D are at logical 0, with the lamp test Input at logical 1,
all segment outputs go to a logical 1 and the npple~blanking output (RBO) goes to a logical 0 (response condition).
Note 4: When the blanking Input/npple~blanklng output (BIIRBO) IS open or held at a logical 1, and a logical 0 is applied to
the lamp~test Input, all segment outputs go to a logical O.
6-21
co
It)
co
co
:?!
output stage schematics
c
,------.--0 v"
.......
,---"",--.--0 v"
co
It)
co
:?!
"
c
"co
It)
co
:?!
c
DM7856/DM8856
CD
It)
CO
CO
:?!
c
.......
CD
It)
~
:?!
c
6-22
DM8857
DM7858/DM8858
o
3:
Display Drivers
00
00
U1
CD
o
3:
00
00
DM8859, DM8869 TTL compatible hex LED drivers
en
CD
general description
The DM8859, DM8869 are TTL compatible hex
LED drivers with programmable current source
outputs. The current sources are nominally set
at 20 mA but may be adjusted by external
resistors for any value between 0-50 mA. Each
device contains six latches which may be set by
input data terminals. A strobe common to all six
latches enables the data input terminals. The
DM8859 current source outputs are switched on
by entering a high level into the latches and the
DM8869 current source outputs are switched on
by entering a low level into the latches.
The devices are available in either a molded or
cavity package. In order not to damage the devices
there is a limit placed on the power dissipation
allowable for each package type. This information
is shown in the graph on the back page.
schematic diagram
DM8859
INPUT
DATA 1
OUTPUT t
COMMON
CURRENT
CONTROL
COMMON
STROBE
TO OTHER
LATCHES
TO OTHER
CURRENT
SOURCES
connection diagram
truth table
Dual·1 n·Lin. Package
Vee
I"
IADJ
"
DATA lIP,
14
DIP,
DATA 11P2
12
"
0/P2
11
DATA 1/P3
10
0/P3
9
,.......
1
2
STROBE DATA lIPs
J
4
OIP6 DATA 11P5
5
DIPs
6
DATA lIP.
J
DIP.
COMMON
STROBE
lIP
DM8859
DM8869
OIP (t+1)
OIP (t+1)
0
a
OFF
ON
a
1
ON
OFF
1
X
OIP (t)
OIP (t)
I'
GNU
TOP VIEW
Order Number DM8859J or DM8869J
See Package 17
Order Number DMB859N or DM8869N
See Package 23
6·23
~
co
absol,,!\e
QO
:i
ma~imum
ratings
(Note 1)
operating conditions
>
Supply Voltage
Input Voltage
Output Voltage
+7.0V
+5.5V
+5.5V
Storage Temperature Range
--£5°e to +150o e
Lead Temperature (Soldering, 10 secondsl
3000 e
Q
en
It)
OQ
OQ
elec;trical characteristics
:i
Q
MIN
MAX
UNITS
Supply Voltage (Veel
DM8859, DM8869
4.75
5.25
V
T emperatu re (TAl
DM8859, DM8869
0
PARAMETER
CONDITIONS
Vee = 4.75V
Logical "0" Input Voltage
. Vee ~ 435V
MIN
MAX
TYP
20
Vee'" 5.25V, VIN = DAV
Vee
Supply Current (each deVIce)
Vee ::: 5.25V •.~urrent Sources "Off"
Input Clamp Voltage
=:
-10
5.0V, IA~J Pin Open, 25°C
~A
-16
mA
·20
.'
'~w~
mA
-1.1
,liN =-:12mA
V
40
Vee'" 5.25V, VIN '" 2.4V
Logical "0" Input Current
UNITS
V
08
TYPical Output Current
°e
,. ,
:(Note 2)
Logical "1" Input Voltage
Logical "1" Input Current
+70
50
mA
-1.5
V
"
Nota 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the deVice cannot be,guaranteed. Except
for "Operating Temperature Range" they are not meant to Imply that the deVices should be operated at these limits. The
table of "Electrical Characteristics" provides conditions for actual deVice operation.
Note 2: Unless otherWise speCified minimax limits apply across the ooe to +70°C temperature range for the DM8859 and the
DM8869. All tYPleals are given for Vee = 5.OV and TA = 25°e.
typical performance characteristics
test circuit
Max Power Dissipation Curves
r+
50r-~r--'~-'--~---'
"
gw
§
5l
i
I-
B
45
40
f-----I11\O---+\.""'\.'--+CAVIT~PACKAGE (J)
\
I\.
35r--+-~\.-r--~,,~r--1
30 1---t-4rt--+-""i;:----1
25 f-PACKAGE (N)
MOLDED*_+'----+'--"~
1 '
20
15
10
5.0
o
I"
Vcc=5V
..........
CURVE ASSUMES ALL OUTPUT~
BEING USED AT70'C ~MBIEN~ TEMPERATURE
I
I
o
1.0
2.0
3.0
4.0
VOLTS ACROSS OUTPUT
6·24
5.0
v"
I
I
27'
)
IAOJ
I
I
I
.....
L+
56'
~
-=-
IADJ may be programmed by a
voltage source or by resistors.
o
~
Display Drivers
00
00
en
....
DM8861
MOS-to-LED 5-segment driver
general description
features
The OM8861 is designed to be used in conjunction
with MOS integrated circuits and common-cathode
LED's in serially addressed mUlti-digit displays.
• Source or sink capability
per driver
• MOS compatibility (low input current)
• Low standby power
• High gain Darlington circuits
The OM8861 is a 5-segment driver capable of
sinking or sourcing up to 50 mA from each driver.
50 mA
schematic and connection diagrams
DM8861
(4,6,12, 13.16)
A
-.-.y,f---+-OUTPUT
CL "lSpF
I'NOTE2I
DM8861
~$10ns
--l
:
I
:"'~-"""="'--I--
- - - - - - - - V1H
I
I
INPUT
I
~~-------'V
r---Vo,
OUTPUT
!
"-__--'_....1.:"--+ - -- ---- VOL
I
I
I
I
I
I-",,-j
NOTE 1 THE PULSE GENERATOR HAS THE FOLLOWING CHARACTERISTICS ZOUT"
son,
PRR=100KHl,t'IV =1/.15
NOTE 2 C,- INCLUDES PROBE AND JIG CAPACITANCE
6-27
(I)
(I)
co
co
Display Drivers
:!:
c
DM8864, DM8865, DM8866 LED cathode drivers
features
general description
The DM8864, DM8865 and DM8866 are cathode
drivers for 9, 8, and 7 digit LED displays respectively. They are designed to interface between
MOS calculator or clock circuits supplying 2.0 mA,
and LED displays operating up to 50 mA in a
multiplex mode. The DM8864 and DM8866 feature
a "low battery" indicator driver which will light
a decimal point whenever a 9.0V battery drops
below 6.5V typical.
connection diagrams
•
Used with 50 mA LED displays
•
"Low battery voltage" indicator
•
Directly interfaced from MOS
•
Inputs and outputs clustered for easy wiring
•
Drivers consume no standby power
(Dual-In-Line Packages)
OUTPUTS
OUTPUTS
INPUTS
INPUTS
TOPVIEW
TOPVIEW
Order Number DM8864N
Order Number DM8865N
See Package 29
See Package 25
OUTPUTS
INPUTS
TOPVIEW
Order Number DM8866N
See Package 25
typical application
. -_ _ _ _ _ _ _...._-o+90V
d,
LAST DIGIT
LAST OlGlT
OMaS66 OR
DM8864OR
OM886S
MM6736DR
MM5738
MOS
CALCULATOR
CIRCUIT
LED
DISPLAY
FIRST DIGIT
~VCC2
6-28
III$N66AOA
NSN9SA
fiRST DIGIT
AND PIN 1 CONNECTION APPLICABLE ONL Y TO DM8864 AND OMISS6
(NSN9BM
o
absolute maximum ratings
(Note 1)
Supply Voltage
11 V
I nput Voltage
11 V
Output Voltage
8.0V
Storage Temperature Range
~5°C to +125°C
Lead Temperature (Soldering, 10 seconds)
300°C
3:
CO
CO
operating conditions
Supply Voltage, V CC
MIN
5.0
Temperature, T A O
en
MAX
UNITS
9.5
V
01:0
+70
°c
o
3:
CO
CO
en
electrical characteristics
U'1
(Note 2)
PARAMETER
CONDITIONS
MIN
= Max
Logical "1" Input Voltage (V ,H )
Vee
logical "I" Input Current (I,H)
Vee = Max, Y'N = 6.5V
Logical "0" Input Voltage (V,L )
Vee
Logical "0" I nput Current (I t L)
Vee = Max, Y'N = D.4V
Decimal Pomt Output Current (pm 1)
Vee = 6.25V, V DP = 3.3V, V'N9 = 4.5V
MAX
4.5
o
UNITS
3:
CO
CO
V
= Max
(lDPON) (Note 3)
Decimal Pomt Output Current (Pm 1)
TYP
2.0
mA
04
V
60
en
en
IlA
60
mA
-10
IlA
..
Vee = l.OV, V DP = 1 OV, V ,Ns =45V
(lop OFF) (Note 3)
Output Leakage Current (lCEX)
Vee = Max, VOH = 6.0V, liN = 40llA
40
Logical "0" Output Voltage (VOL)
Vee = Min, Y'N = 4 5V, 10L = 50 mA
15
V
Supply Current (I CC1 or led
Vee = Max,
01
mA
Supply Current (Icc,)
Vee = Max, V ,N9 = 4.5V
13
mA
VIN
=0
0
IlA
Note 1: "Absolute MaXimum Ratings" are those values beyond which the ~afety of the deVice cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to Imply that the deVices should be operated at these limits. The
table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Apply over O°C to +70°C operating temperature range.
'
Note 3: Note applicable to DM8865.
6·29
o
CO
CO
CO
Display Drivers
:E
Q
"-
o
CO
CO
DM7880/DM8880 high voltage 7-segment decoder/driver
(for driving Sperry and Panaplex IITM displays)
I"-
:E
Q
general description
Output currents may be varied over the 0.2 to 1 5
mA range for driVing various tube types or
multiplex operation. The' output current IS ad·
justed by connecting an external program reSistor
(Rpl from Vee to the Program Input In accor
dance With the programming curve The CirCUit
design prOVides a one·to-one correlation between
program Input current and b-segment output
The DM7880/DM8880 is custom designed to decode four lines of BCD and drive a gas-filled
seven-segment display tube.
The design employs a 112-bit read-only memory
which provides BCD Input to full hexadecimal output decoding In the standard DM7880/DM8880
product. For applications desiring other fonts, or
not using standard BCD coding, the ROM contents
can be custom modified to produce any 16 output
displays for the 16 binary Input combinations.
current.
The Blanking Input prOVides unconditional blank·
Ing of any output dISplay, while the Ripple Blanking pinS allow simple leadlng- or tralllng·zero
blanking.
Each output constitutes a sWltchable, adjustable
current
sink
which
prOVides
constant current
to the tube segment, even with high tube anode
supply tolerance or fluctuation. These current
sinks have a voltage compliance from 3V to
at least 80V; tYPically the output current vanes
1% for output voltage changes of 3 to 50V. Each
bit line of the ROM switches a current Sink on
or off as prescribed by the input code. Each
current Sink is ratloed to the b-output current
as required for even illumination of all segments.
features
•
•
Current sink outputs
Adjustable output current - 0.2 to 1.5 mA
•
High output breakdown voltage - 110V typ
•
Suitable for mUltiplex operation
•
Blanking and Ripple Blanking prOVISions
•
Low fan-in and low power
logic and connection diagrams
,-----------------,
I
I
I
Dual·ln·Llne Package
OUTPUTS
aDUlPUT
+
r-+---l,- b OUTPUT
116
15
14
AINflUT
12
"
11
9
10
... :1_+-_-1- cOUTPUT
B INPUT
r-+--!""
CINPUl
o INPUT
RIPPLE
BLANKING
INPUT
dOUTPUT
-
... :r-+---t-eOUTPUT
+----1
....:r,..-I---l- 'OUTPUT
... 1'-+---1- gOU1PUT
,'.
1
2
C
3
,
4
PRDGRAM. BI/RBO
INPUTS
BLANKING
INPUT!
RIPPLE
BLANKING
OUTPUT
6-30
+--""-1
,
7
RBI
INPUTS
TOPVIEW
CURRENT
PROGRAMMING
INPUT
I'
GND
Order Number DM7880J or DM8880J
See Package 17
Order Number DM8880N
See Package 23
c
absolute maximum ratings
PARAMETER
MAX
UNITS
45
475
55
525
V
-55
0
+125
+70
o
......
V
c
Temperature (T AI
DM7880
DM8880
3:
e
e
00
00
00
o
(Note 3)
MIN
CONDITIONS
Logic "I" Input Voltage
Vee = Min
Lagle "0" Input Voltage
Vee = Min
Logic "I" Output Voltage (RBO)
Vee = Min,
lOUT = -200 pA
Logic "0" Output Voltage IRBO)
Vee = Min, lOUT = 8 mA
Logic "I" Input Current (Except BI)
Vee = Max, V, ... = 24V
Vee = Max, V, ... = S SV
Logic "0" Input Current (Except BI)
Vee = Max, V, ... = 04V
Logic "0" Input Current (BI)
Vee = Max, V, ...
Powel Supply Current
Input Diode Clamp Voltage
Segrnent Outputs
Outputs a, f, g ON Cunent Ratio
MIN
00
Supply Voltage IVee)
DM7880
DM8880
7V
6V
Vee
80V
600mW
Power DISSipation (Note 1)
50mA
TranSIent Segment Output Current (Note 2)
-65"e to 150"e
Storage temperature Range
300"e
Lead Temperature (Soldering, 10 sec)
Vee
Input Voltage IExcept 81)
Input Voltage (81)
Segment Output Voltage
electrical characteristics
....3:00
operating conditions
TYP
MAX
20
V
08
24
-~
".
37
013
, ,
UNITS
V
V
04
2
4
IS
400
-300
-600
V
/-IA
/-IA
/-IA
-12
-20
mA
V ee - Max, Rp= 22k
All Inputs = OV
27
43
mA
Vee = Max, T A = 25°C
I, ... = -12 mA
-09
-15
04V
V
All Outputs = SOV
Output b Curr = Ref
084
093
102
Output c ON Current Ratio
All Outputs = SOV,
Output b Curr = Ref
1.12
12S
138
Output d ON Current Ratio
All Outputs ~ SOV
Output b Curr = Ref
090
100
110
Output e ON Current Ratio
All Outputs = SOV
Output b Curr = Ref
099
110
1,21
Output b ON Current
Vee = SV, V OUT b = SOV
T A = 2SoC, Rp= 181k
Vee = SV, V OUT b = SOV
TA = 2SoC, Rp = 7.03k
Vee = SV, V OUT b = SOV
T A = 2Soc, Rp = 340k
018
020
022
mA
04S
o SO
o SS
mA
090
1.00
110
mA
Vee = SV, VOUT b = SOV
T A = 25°C, Rp = 2 20k
135
1. SO
165
mA
Output Saturation Voltage
Vee = Min, Rp = lk±5%
lOUT b = 2 mA (Note 4)
Output Leakage Current
V OUT = 75V, BI = OV
Output Breakdown Voltage
lOUT = 250 pA, BI = OV
0.8
.003
80
2.5
3
V
pA
V
110
Propagation Delays
BCD Input to S~gment Output
BI to Segment Output
RBi to Segment Output
RBI to RBO
V ce =5V,T A =25°C
Vee= SV, T A = 25°C
V Ge =5V,T A =25°C
V ee =5V,T A =25°C
04
04
0.7
04
10
10
10
10
ps
/-IS
PS
ps
Note 1: MaXimum Junction temperature for DM7880 IS +150° C whereas that for OM8880 IS +130u C. For operating at elevated temperatures
t"e deVice must be derated based on a thermal resistance of 8Sc C/W ElJA for DM8880.
Note 2: In all applications transient segment output current must be limited to SO mAo Th~s may be accomplished In dc applications by
connecting a 2.2k resistor from the anode-supply filter capacitor to the display anode, or by current limiting the anode driver In multiplex
applications.
Note 3. MinImax limits apply across the guaranteed operating temperature range of -5SoC to +125°C for DM7880 and oOe to +70oe for
DM8880, unless otherwise speCified TYPlcals are for Vee = 5 OV, T A = +2S oC. Positive current IS defined as current IOta the referenced pin.
Note 4: For saturation mode the segment output currents are externally limited and ratloed
6-31
o
CO
:
typical performance characteristics
~
Q
......
o
co
co
....
~
Q
Output Current Programming
Vcc· 5V
1
>-
..
"
3.0
i5
~
1.08
ON CURRENTS
1.06
..
~
\ /
1.00
~
z 0.98
0.3
'" ,
0.1
10
/
0.96
0.94
I I I
Vee" 5V
TA =25"C
.
::"
."
1 1 1
>-
IOUT~~
ill
I 1
1\ 1 I I
B 1 mA
>-
TYPICAL OPERATiNG POINTS
Rp = oTEMP COEFF
OUTPUT OFF
O.2mA S;; lOUTS;; 1.5mA
z 0.90
30
"..
Vee" 5V
VOUT " 50V
V
0.92
Output Characteristic
'"
\
1.02
.
..~
I.
.,r
ON CURRENT RATIOS
~k.l.04
"
1.0
'"~
co
VOUT '" 50V
TA "25"C
,
On Currents vs Temperature
.fi
.
10.0
5nA
-50
100
50
Rp(k!l)
100
30
'
.,
60
90
110
OUTPUT VOL TAGE IVI
TA rCI
typical application
Ii----L
I I I
..
(116-200VDC)
""r
R-Z2K
(NOrEZI
SPERRY
SP-7300R
SP-1S0
~999999
,,
'"
DISPLAY
TU~E
5Vl0%
DECODEA/ORrvER
'.
-1,1,101
DM5475
QUAotATCIt
cl
AI BI
I
D+-~~~JT
PM549G
OECADE
COUNT
INPUT
COUNTER
truth table
DECIMAL
OR
FUNCTION
RBI
D
0
X
0
0
1
6-32
C
B
A
0
0
0
0
0
2
X
0
0
3
x
0
0
4
X
0
0
0
BI/RBO
0
0
5
X
0
6
X
0
7
X
0
8
X
0
0
9
X
0
0
0
0
10
X
0
11
X
0
12
X
0
13
X
0
14
X
15
X
BI
X
X
X
X
X
0
RBI
0
0
0
0
0
0
0
0
0
0
0
0
I-I
I_I
0
,
I
0
0
0
0
0
0
0
=1
_I
0
0
'-'I
5
5-I
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I:!
1
0
0
0
0
0
0
0
0
0
0
0
0
DISPLAY
d
b
I
0
C!
0
0
I_I
0
0
_I
II
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
C!
n
L
1-1
I-
i-1
1-1
E
,-
I-
a
'/-;/b
_/ /e
d
SEGMENT
IDENTIFICATION
Display Drivers
DM8884A high voltage cathode decod~r/driver
(for driving Panaplex IITM and Sperry displays)
general description
The DM8884A is designed to decode four lines of
BCD input and drive seven-segment digits of gasfilled readout displays. Two separate Inputs are
provided for driving the decimal point and comma
cathodes.
program Input In accordance with the programming
curve.
All outputs conSISt of switchable and programable current sinks which provide constant current
to the tube cathodes, even with high tube anode
supply tolerance. Output currents may be varied
over the 0.2 to 1.2 mA range for mUltiplex operation. The output current IS adjusted by connecting
an external program resistor (Rp) from Vee to the
•
Usable with AC or DC Input coupling
•
Current sink outputs.
•
High output breakdown voltage
features
•
Low Input load current
•
Intended for multiplex operation.
•
Input pullups increase noise immunity
logic and connection diagrams
v~
r-------------t----------I
OUTPUTS
t"->-~--o
Dual-In-Line Package
dO'
OUTPUT
"
INPUTS
1$(6MENT
DECOOER
PROG
D PT
INPUT
tOlnIllil
00III1IlII
GND
INPUT OUTPUT
TOP VIEW
Order Number DM8884AN
See Package 25
......
PROGRAMMA.8LE
~~:::~~---!-------------1
~------------J-----------~
GN,
6-33
II(
~
00
00
00
absolute maximum ratings
Vee
Input Voltage (Note 1)
Segment Output Voltage
Power Dissipation (Note 2)
Transient Segment Output Current (Note 3)
Operating Temperature Range
d
Storage Temperature Range
:E
Q
7V
Vee
BOV
600mW
50 rnA
O°C to +70°C
-65°C to +150°C
electrical characteristics
(O°c
~ T A :-;:; 70 0 e - Unless otherwl~e noted), Vee = 5V ± 5%.
PARAMETER
CONDITIONS
LogiC "1" Input Voltage
Vee
= 4.7SV
LogiC "0" Input Voltage
Vee
= 4.7SV
LogiC "1" Input Current
Vee = S.2SV, Y'N = 2.4V
Positive Input Clamp Voltage
Vee = 4.7S, liN = 1 mA
LogiC "0" Input Current
Vee = S.2SV, V ,N = 0.4V
V
1.0
-250
).IA
40
rnA
-1 S
Vee = SV, VOUT b = SOY,
TA = 2SoC, Rp= lB.lk
Rp = 7.03k
Rp = 3.40k
Rp = 2.BOk
V OUT
lOUT = 2S0).lA
Vee
11
O.lB
045
0.90
lOB
0.22
O.SS
1.10
1.32
rnA
mA
mA
mA
S
).IA
BO
V
= SV, T A = 2SoC
10
Note 1: This I,mlt can be hIgher for a current Ilmltmg voltage source
V
09
= 75V
Output Leakage Current
Output Breakdown Voltage
Propagation Delay:
Any Input to Segment Output
).I A
V
Rp= 2.Bk,
All Outputs = SOV
Output b Current = Ref
Output b ON Current
V
IS
S.O
Vee = SV, liN = -12 rnA, T A = 2SoC
Segment Outputs'
All Outputs ON Current RatiO
UNITS
lrii'i~js = SV
All
Negative Input Clamp Voltage
MAX
20
ve b"'5i::Z5V,
Power Supply Current
MIN
).Is,
\
IS 1400 C For operation at elevated temperatures, the deVice must be derated
based on 8 thermal resistance of 140°C/W (J JA
Nota 3: In all applIcations tranSient segment output current must be limited to 50 rnA This may be accomplished In DC appll.
cations by connecting a 2.2k resistor from the anode-supply filter capacitor to the display anode, or by current limiting
the anode driver In multiplex applications
Note 2: The maximum junction temperature
truth table
FUNCTION
,
0
2
3
··,
5
·,
ID
"
"
""
"
'OPT
'Com_
,,
OPT
,
,,
,,
,
,
,
,
,
,,
,
,
0
0
,,,
,,
,
,,,
,, ,,
COOWA
,
0
C
B
0
0
0
0
0
0
0
0
0
0
0
0
0
0
,
,
,,, ,,
,
,
,
0
,
, , ,
, ,
0
,
, ,
,, ,, ,
,
,
, ,
,,
, o·, ,
, , ,
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
. ..
,
A
0
0
0
0
,
0
0
0
0
0
0
0
0
0
0
,
,
0
0
0
, ,
, ,
,
, ,
, ,
0
0
0
°, , , ,,
, ,
, ,
,
°, , ,
,
,
,
, , ,
,
, , , ,
, , , ,
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
,
,
O'8f'LAY
0
0
0
0
0
'"
,
I
I
0
0
0
0
'"'"E
,
I "
I
l"'OG
I
c,
-
I
I
I w"
I
I
I
7
0
0
,
I
'-I
EI
:3
x x x x x x x x x x x
x x x x x x x x x x x
r--ve<,.----,I
3
5
G
0
0
,
.f" PANII.Pl'XIIIII'PLII.~
~'il'~
L7
0
0
0
0
0
typical application
/";7'
I
I
I
I
.C/,
d
a
.p
BlANKING
1,1" I, I-I' ,I, 1:.1"·"
'.
I
I
I
I
I
l2!!'!!.4G,!, ___ ::J
OeclmalPo,nl
Comma
*Oeclmal pomt and comma can be displayed with or without any numeral.
typical performance characteristics
6·34
(see DM78BO data sheet)
OM888"
+
~ ~ ~
t=:"
,-,
."
~
o
~
Display Drivers
00
00
00
en
DM8885 MOS to high voltage cathode buffer
general discription
The DM8885 mterfaces MOS calculator or counterlatch-decoder-drlver CirCUits directly to sevensegment high-voltage gas-filled dlsplays_ The SIX
inputs A, B, D, E, F, G are decoded to drive the
seven segments of the tube.
multiplex operation The output current IS adjusted
by connecting a program resistor (Rp) from Vee to
the program Input-
Each output constitutes a sWltchable, adjustable
current source which prOVides constant current to
the tube segment, even With high tube anode supply
tolerance or fluctuation. These current sources have
a voltage compliance from 3V to at least 80V. Each
current source is ratloed to the b-output current
as required for even Illumination of all segments.
Output currents may be varied over the 0.2 to
1.5 mA range for drivmg various tube types or
•
Current source outputs
•
Adjustable output currents 0.2 to 1.5 mA
connection diagram
features
•
•
•
.•
•
High output breakdown voltage 80V min
Slelltijble for multiplex operatl9n
L9)N'fan-in and low power
Blankmg via program input
Also drives overrange, polarity, deCimal POlilt
cathodes
truth tables
Dual-In-Line Package
A
B
D
E
F
G
DISPLAY
1
1
1
1
1
1
1
1
1
u
0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
GNO
1
1
1
1
1
0
1
0
1
INPUT'
,-,
I
,~
3
OUTPUT'
0
110FF)
1
o ION)
• POSitive LogiC
Lj
5
S-,
,
EI
'3
,
CI
q
,q
r~l
'Cr
ILl
"
u
SI
d
C=jABO·Eif
TOPVIEW
Order Number DM8885J
See Package 17
Order Number DM8885N
See Package 23
typical applications
'sv
'sv
v" o-...--!--<~-i--"""I---o
-I
-I
v" o-"'--t--o
____ -I
-12V
Open·Drain MOS Output
Push-Pull MOS Output
6-35
In
eo
co
eo
:I
absolute maximum ratingsl,
Q
7V
6V
BOV
600mW
50mA
O°C to +70°C
-ti5°C to +150°C
300°C
Vee
Input Voltage
Segment Output Voltage
Power Dissipation (Note 1)
Transient Segment Output Current (Note.2)
Operating Temperature Range
Storage Temperature Range
Lead T,emperature (Soldering. 10 sec)
electrical characteristics
(Note 3)
PARAMETER
MIN
CONDITIONS
=4 7?~
LogiC:: "'" Input VOltage
Vee
Logic "0" Input Voltage
Vee" 4 75V
Logic "'" Input Current
Vee
, "
TVP
MAX
20
'-:!'
UNITS
V
,
08
=5 25V, VIN '" 2 4V
2
V
15
"A
5 5V
4
400
"A
=5 25V, VIN '" 0 4V
-300
-600
"A
22
31
mA
-09
-15
Vee" 5 25V, V IN
'"
logic "0" Input Current
Vee
Power Supply Current
Vee'" 5 25V. All Inputs '"
Input Diode Clamp Voltage
Vee'" 5V, liN'" -12 rnA. TA '" 2S'C
av. Rp '" 2 2k
V
Segment Outputs
Outputs a, f, 9 On Current Ratio
All Outputs '" 5OV. Output b Curr :: Ref
084
093
102
Output c On Current Ratio
All Outputs '" SOV, Output b Curr '" Ref
1 12
1 25
1 38
Output d On CUrrent Ratio
All Outputs'" SOV. Output b Curf :: Ref
090
100
110
Output e On Current Ratio
All Outputs :: SOV. Output b Curr ::: Ref
099
1 10
121
Output b On Current
Vee = 5V, V OUT b '" SOV, TA '" 2S"C, Rp '" 18 lk
018
020
022
mA
Vee'" SV, V OUT b == SOV, T A'" 2S"C, Rp '" 7 03k
045
050
055
mA
Vee'" SV, VOUT b:= 50V, T A"" 2S OUTPUT
VilAS
Q
I
I
I
I
I
I
VBtAS
:E
I
I
I
I
00
~
OUTPUT
,.--------------------,I
I
S~nse
c
aIo
:s::
Amplifiers
N
......
C
OM7802/0M8802. OM7806/0M8806
,
high speed MOS to TTL level converters
:s::
general description*
o
N
00
00
features
C
The DM7802/DM8802, DM7806/DM8806 are high
speed MOS to TTL level converters. These circuits
act as an interface level converter between MOS
-and TTL logic devices. It consists of two 1-input
converters with common strobe input to inhibit
"0" entry when strobe is high. It allows parallel
entry when strobe is low and the internal latch
is preset by the common preset input. TR 1STATE@ output logic is implemented in this
circuit to facilitate high speed time sharing of
decoder-drivers, fast random-access (or sequential)
memory arrays, etc .
• Very low output impedance ability
:s::
high drive
aIo
en
• High impedance output state which allows
many outputs to be connected to a common
bus line
......
c
:s::
00
00
• Average power dissipation 110' mW per converter
o
en
• Also see LM3625.
logic and connection diagrams
IN.
(CURRENT INPun
OUTPUT A
IN,
(CURRENTINPUn
OUTPUT B
sriiOiE
PRESET
Dual-In-Line Package
16
mnrar
15
Ne
14
OUTPUT A
13
PRESET
OM1802/DM8802
Ne
12
11
GND
lD
INPUT A
Dual-In-Line and Flat Package
v"
smrn
V"
Ne
13
OUTPUT A
OUTPUTB
12
PRESET
DISABLE
Ne
DM1806/DM8806
NC
11
lD
GND
OUTPUT B
DISABLE
Ne
GND
GND
INPUTB
INPUTA
INPUTB
GND
GND
GND
GND
TOPVIEW
TOP VIEW
Order Number DM7802J or DM8802J
Order Number DM7806J or DM8806J
See Package 17
See Package 16
Order Number DM8802N
See Package 23
Order Number DM8806N
See Package 22
Order Number DM7806W or DM6806W
See Package 27
7-1
8
co
co
::E
Q
......
CD
o
absolute maximum ratings
,
operating conditions
(Note 1)
MIN
Supply Voltage
fe
Input Voltage
7.0V
55V
Output Voltage
5.5V
Storage Temperature Range
::E
.
Lead Temperature (Soldering, 10 .econd.1
Q
Supply Voltage (Veel
DM7802, DM7806
DM8802, DM8806
Temperature (T A)
DM7802, DM7806
DM8802, DM8806
--£5° e to 150° e
JOooe
4.5
4.75
-55
0
MAX
UNITS
55
5.25
V
V
+125
+70
°e
"e
N
o
co
co
::E
Q
......
N
o
electrical characteristics
(Note 2)
CONDITIONS
PARAMETER
i
Logical "1" Input Current
(lINA, IINB
I
Logical "O"lnp,ut Current
(lINA. IINS)
Logical "1" Input Voltage, Strobe,
Q
Vee
= Min
MIN
TYP
MAX
200
Vee = Min
~A
V
20
Vee = Min
UNITS
~A
500
Preset, Disable
Logical "0" Input Voltage, Strobe,
Preset, Disable
Vee = Min
08
V
logical "1" Output Voltage
Vee = Min, lOUT =
Logical "0" Output Voltage
Vee = Min, lOUT = 16 rnA
04
Third State Output Current
Vee = Max, Vo =24V
Vee =Max, Vo =04V
40
~A
-40
~A
Loglca' "1" Input Current
Vee = Max, VIN =24V
Vee = Max, VIN = 5 5V~
40
10
j;.A
rnA
logical "0" Input Current
Vee = Max, VIN = 04V
-16
rnA
40
rnA
Supply Current
15rnA
V
24
Vee = Max, V'NIDISABLEl "" 2
V
Other Inputs = ¢V
Input Clamp Voltage
Vee = Min, liN =
Output Short CirCUit Current (Note 3)
Vee
= Max, Vo
12 rnA
OV
DM7802. DM7806
DM8802,DM8806
'15
V
70
-70
rnA
rnA
=
20
-18
Propagation Delay to a Logical "0" From
STROBE to Output (t",1
Vcc = 5 OV (See waveforms)
T A = 25°C
17
25
n,
Propagation Delay to a Logical "1" From
Preset to Output Itdpl
Vce = 50V (See waveforms)
TA = 25°C
22
32
n,
Delay From Disable Input to High Impedance
State (From Logical "1" Level)(t,H I
Vec=50V (See ac test cirCUIt)
TA = 25°C
70
11
n,
Delay From Disable Input to High Impedance
State (From Logical "0" Level)(toH I
Vcc=50V (See ac test circuit)
TA = 25°C
17
25
n,
Delay From Disable Input to L!,9lcal "1"
Level (From High Impedance Stale)(tH,1
Vcc =50V (See ac test CirCUit)
TA = 25°C
90
14
n,
Delay From DISable Input to Loglcai "0"
Level (From High Impedance State)(tHol
Vcc = 50V (See ac test circuit)
TA = 25°C
135
16
n,
Note 1: "Absolute Maximum Rating." are tho.e value. beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to Imply that the devIces should be operated at these limits. The
table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise speCified minimax limits apply across the -55°C to +125°e temperature range for the DM7802,
DM7806 and across. the oOe to +70o e range for the DM8802, DM8806. All tYPical. are given fJr Vee = 5.0V, TA = 25°C.
Note 3: Only one output at a time should be shorted.
7-2
c
typical input circuit
3:
.....
CO
o
truth table
IN AOR B
ST
P
0
1
1
1
0
0
1
1
SDk
0
1
X
X
N
0
0
0
0
0
1
1
1
X
.......
QA OR Oa
c
1
3:
1
0
CO
CO
1
o
H,-Z
N
x = Don't care
C
3:
.....
CO
ac test circuits
o
en
.......
C
3:
SWITCH S,
SWITCH S2
CL
tdp
Closed
Closed
50 pF
t d•
Closed
Closed
50 pF
*5 pF
tOH
Closed
Closed
t'H
Closed
Closed
*5 pF
tHO
Closed
Open
50 pF
tHl
Open
Closed
50 pF
CO
CO
o
en
""Jig capacitance
(a)
+50V
+3nV
PULSE GEN NO 2
STROBE
o-----c~
h~---""""~"o:'::"-I
PRESET
f=1 MHz
DISABLE
t,=t,<5ns
Ro '" 51 forPG 1 & 2
tpw "'tsw =20 Rsmax
ls=20ns.max
(e)
(b)
+511V
lNPUTA,B
OPEN
o-----c>-l
DISABLE
t,"'t,<5ns
Ro '" 51
tow =200ns,max
(d)
Test Circuit 20
7-3
CD
0
CO
switching time waveforms
co
~
c
.......
CD
toH
0
t1H
co
.....
~'"
i
~
C
30V
15V
INPUT
INPUT
N
0
OV
I
I
----'((lH~
co
co
I
I
I
ArTUAt
n
I
~
C
OUTPUT
ACTUAL
lOGICAL "0"
VOLTAGE
~
0
'>
I",~
:_1
OUTPUT
LOGICAL "1"
VOLTAGE
15V
'\1.
--1
",15V
(b)
(a)
CO
.....
~
C
tH1
tHO
INPUT
15V
I
I
I
I
~ '"'
I
I
I
OUTPUT
I
I
I
I
I
OUTf'UT
(d)
(e)
+ 1 5 m A - - - - - -___
."'-------
[t
"W
" ••,
+30V-
PRESET
+14V-
OV
--------t--------
"'!-r--------~
-;)
'30VOUTPUT
+14V--
OV
7-4
(el
.v
r~
(11
(11
Sense Amplifiers
N
o
.......
r~,
LM5520/LM7520 series
dual core memory sense amplifiers
general description
The devices in this series of dual core sense
amplifiers convert bipolar millivolt-level memory
sense signals to saturated logic levels. The design
employs a common reference input which allows
the input threshold voltage level of both amplifiers
to be adjusted. Separate strobe inputs provide time
discrimination for each channel. Logic inputs and
outputs are DTUTTL compatible. All devices of
the series have identical preamplifier configurations, while various logic connections are provided
to suit the specific application.
The LM5520/LM7520 has output latch capability
and provides sense, strobe, and memory function
for two sense lines. The LM5522/LM7522 contains a single open collector output which may be
used to expand the number of inputs of the
LM5520/LM7520, or to drive an external Memory
Data Register (MDR). Intended for small memories, the two channels of the LM5524/LM7524 are
independent with two separate outputs. The
LM5534/LM7534 is similar to the LM55241
LM7524 but has uncommitted, wire-aRable outputs. The LM5528/LM7528 has the same logic
configuration of the LM5524/LM7524 and in
addition provides separate low impedance Test
Points at each preamplifier output. A similar
device having uncommitted, wire-aRable outputs
is the LM5538/LM7538.
features
.....
(11
N
o
en
• Adjustable input threshold voltage
CD
• Fast overload recovery times
CD
en
• Two amplifiers per package
• Molded or cavity dual-in-line package
• Six logic configurations
The part number ending with an even number
(e.g., LM5520) designates a tighter guaranteed
input threshold uncertainty than the subsequent
odd number ending (e.g., LM5521). The remaining
specifications for the two are identical. All devices
meet or exceed the specifications for the corresponding device (where appl icable) in the
SN5520/SN7520 series and are pin-for-pin repl'acements.
absolute maximum ratings
Supply Voltage
Differential or Reference Input
Voltage
Logic Input Voltage
Operating Temperature Range
LM55XX
LM75XX
Storage Temperature Range
±7V
±5V
+5.5\(
-55°C to +125°C
O°C to +70°C
-65°C to +150°C
• High speed
• Guaranteed narrow threshold uncertainty over
temperature
typical application
WIRE OR
CONN~TlONS
MEMOIIYDATA
REGISTER
Expanded Small Memory System
7-5
LM5520/LM7520 and LM55211LM7521
electrical characteristics
LM5520/LM5521 : The following apply for -55°C ~ T A ~ 125°C
TEST CONOITIONS lEACH AMPLIFIER)
PARAMETER
Differential Input
Threshold Voltage
(VTH I INote 21
MIN
1018)
35(33)
Differential & Reference
Input Bias Current
TYP
15
15
40
40
MAX
20122)
45(47)
100
30
DIFF.
INPUT
REF.
INPUT
mV
mV
mV
mV
±VTH
±VTH
tV TH
±VTH
15mV
15mV
40mV
40mV
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
~A
OV
OV
+525V
+525V
UNIT
STROBE
INPUT
GATEQ
INPUT
GATEQ
INPUT
LOGIC
OUTPUT
INOTE 3)
SUPPLY
VOLT.
+16 mA(Or ±5V
±5V
+16 mAIO) ±5V
-400~AIQ)
±5V
-400~AIQ)
+525V
COMMENTS
logic Output <0 4V
Logic Output >2.4V
LQglc Output <0 4V
Logic Output >2 4V
!S.2SV
LM7520/LM7521: Thfi following apply for O°C$;TA $;70°C
Differential Input
Threshold Voltage
(V TH ) (Note 4)
1118)
36133)
Differential & Reference
Input Bias Current
15
15
40
40
30
tV TH
±VTH
±5V
44(47)
mV
mV
mV
mV
±VTH
±V nt
15mV
15mV
40mV
40mV
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
75
~A
OV
OV
+525V
+525V
+625V
±S 25V
±525V
19(22)
+16 mAtO)
-400~AIQ)
+16 mAIO)
-400~AIQ)
±5V
±5V
±5V
Logic Output <0 4V
Logic Output >2 4V
Logic Output 2 4V
LM5520/LM5521: The following apply for -55°C$; T A $; 125°C
LM7520/LM7521: The following apply for O°C $; T A $; 70°C
Differential Input Offset
Current
Logic "1" Input Voltage
(Strobes)
(Gate a)
(Gate a)
Logic "0" Input Current
-1
Logic "1" Input Current
(Strobe & Gate Q)
(Gate OJ
5
02
5
02
24
24
24
Logic "0" Output Voltage
(Strobe)
(Gate aJ
(Gate
Circuit Current
Q Output Short
OV
+525V
+525V
+525V
V
V
V
40mV
40mV
40mV
20mV
20mV
20mV
+2V
OV
OV
+475V
+2V
OV
+2V
08
08
08
V
V
V
40 mV
40 mV
40 mV
20mV
20mV
20mV
+OSV
OV
OV
+4.7&V
+O.SV
OV
-16
mA
40mV
20mV
+04V
+04V
+04V
±S 25V
Each Input
40
1
40
1
"A
mA
20mV
20mV
20mV
2QmV
+24V
+525V
+52&V
+525V
+525V
+525V
+24V
+525V
+24V
+525V
±S 25V
±52&V
±& 2&V
±525V
Each Input
Each Input
"A
mA
OV
OV
40mV
40mV
V
V
V
4QmV
40mV
40 mV
2QmV
20mV
2QmV
+20V
OV
+4.75V
+525V
+0 BV
OV
+0 BV
V
V
V
40mV
OV
OV
20mV
20mV
20mV
~.8V
+475V
+2V
OV
+2V
mA
OV
20mV
OV
OV
39
39
39
025
025
025
a)
a Output Short
OV
2
2
2
Logic "0" Input Voltage
(Strobes)
(Gate a)
(Galea)
Logic "1" Output Voltage
(Strobe)
(Gate Q)
(Gate a)
~A
05
040
040
040
-3
-4
-5
-21
OV
OV
:!:5V
:!:5V
!5V
Logic Output >2 4V
Logic Qutput <0.4V
Logic Output <0 4V
+16 mAIO) ±5V
±5V
-400~AIO) ±5V
Logic Output <0.4V
Logic Output >2 4V
Logic Output >2 4V
-400jJAIQ)
+16 mAIO)
+16 mAIO)
-400~IQ)
+0 BV
-400~AIQ)
-400~AIQ)
-400~AIQ)
+16 mAIO)
+16 mAIO)
+16mA(Q)
±475V
±475V
±475V
OVIQ)
±525V
-28
-35
mA
OV
20mV
OV
OV
OV
V+ Supply Current
21
35
mA
OV
20mV
OV
OV
OV
±525V
V- Supply CurreQt
13
-18
mA
OV
20mV
OV
OV
OV
±S 2SV
CirCUit Current
OVIO)
Note 1: For O"C $; TA $; 70°C operation, electrical. characteristics for LM5520 and LM5521 are
guaranteed the same as LM7520 and LM7521, respectively.
Note 2: Limits in parentheses pertain to LM5521, other limits pertain to LM5520.
Note 3: Q or Q in parentheses indicate Q or Q logic output, respectively.
Note 4: Limits in parentheses pertain to LM7521, other limits pertain to LM7520.
Note 5: Positive current is defined as current Into the referenced pan.
Note 6: Pin 1 to have ~1 00 pF capacitor connected to ground.
7-6
±475V
±475V
±475V
±S 25V
r-
3:
c.n
c.n
N
o
.......
r-
3:
LM5520/LM7520 and LM55211LM7521
electrical characteristics
LM5520/LM5521 and LM7520/LM7521: The following apply for T A
-..I
c.n
N
= 25°C, V+ = 5V, V- = -5V
o
f/)
TEST CONOITIONS
PARAMETER
AC Common-Mode
Input FIring Voltage
MIN
TVP
MAX
UNIT
V
'25
DIFF.
INPUT
REF.
INPUT
STROBE
AND
GATE
INPUTS
PULSE
20mV
+5V
Q
LOGIC
OUTPUT
CD
ACTEST
CIRCUIT
SCOPE
Propagation Delays
D,fferent,al Input to
Logical "1" a Output
20
DifferentIal Input to
Logical "0" a Output
Differential Input to
Logical "1"
a OutPUt
ns
20mV
t
28
ns
20mV
I
36
ns
20mV
I
40
Differential Input to
logical "0" Q Output
28
55
ns
20mV
I
Strobe Input to
Logical "1" Q Output
10
30
ns
20mV
1
Strobe Input to
Logical "0" Q Output
20
ns
20mV
1
Strobe Input to
logical "1" Q Output
33
ns
20mV
1
Strobe Input to
Logical "0" Q Output
16
55
ns
20mV
1
12
20
ns
20mV
2
6
ns
20mV
2
17
ns
20mV
2
ns
20mV
2
ns
20mV
2
ns
20mV
2
a
Gate Input to
Logical "1:' Q Output
a Input to
a Output
Gate a Input to
Gate
Logical "0"
Logical "," Q Output
Gate a Input to
a Output
19
Gate Input to
Logical "1" 5. Output
12
Gate Q Input to
Logical "0" Output
6
Logical "0"
a
a
Dlff Input Overload
Recovery Time
Common-Mode Input
Overload Recovery
Time
Min Cycle Time
30
20
10
ns
5
ns
200
ns
7·7
~.
CD
en
en
Q)
.~
LM5520/LM7520 and LM55211LM7521
Q)
Ul
o
It)
,....
N
schematic diagram
~
...J
........
o
N
"
It)
It)
O------1~--..
_____,
~
...J
GAlA
o--+--+l--===t~==!:::~=t-------,
OUTPUT
•
connection diagram
v·
COT
STIIOB£
GATE
A
Q
OUTPlITOlmUTSTAOBf
Ii
Q
L.....--'
DIFFERENTIAL
INPtJTA
~
A£FUENtE
INPUT
B
GATE
II.
GND
'-..---'
DifFERENTIAL
INPUT 8
TOP VIEW
Order Number LM5520J or LM7520J
Sea Package 17
Order Number LM7520N
See Package 23
Order Number LM5521J or LM7521J
See Package 17
Order Number LM7521N
See Package 23
7·8
r-
s:
U1
U1
LM5520/LM7520 and LM55211LM7521
AC test circuit (1)
N
o
........
r-
ST~OB£
DiffERENTIAL
111'111
s:
INPUT
o,.,j
U1
"---..,I
»--::::1~)o--'-
N
o
__!~"'-+_+-oo .. ~ ~"'
I
, 511 1
ST,. ." ..
---------t
I
A~
:
I
I
I---~ :--,
1511
I
£~
__ - "
15",
I
I--~
~f
I
"~."
~
I
OUTPU10
___
1511
I I
I
OUT'UTn~
lW
15\1
I I
1511
I
I
I
151/
I
I
~~.L
:
: \:i.....t15V
c~ ~I
I
I
\
\.-0
-.:
:
G~
C-
~15V
~:
I
1--11
--l
1 Pulse generator characreflstlcs
ZOUT '"
!lon, t, "I, =15±5ns,PRR= 1 MHz
2 Propagation delays
A= Dtfferentlal mputto logtcal "1" output 0
n
B'" DifferentIal mput to logical "0" output
C" Differential mput to logical "0" output 0.
0= Differential mput to logical "1" output
E" Strobe IIlput to logical "1" output
n
n
F '" Strobe mput to logU:31 "0" Olltput n
G " Strobe Input to logical "0" output 0:
H " Strobe Input to logical "1" output
0:
voltage waveforms (2)
AC test circuit (2)
-------"
~
GATE II
INPUT
1SV
15V,
~IOO"~
, , ----"
£!iE
GATE Ii
INPUT
I
15V
OV
I
I
I
15V
1--+3OCI,,"~
"----,
»--::::~~)o-...__~:'3'--<~_-I---o :UT'UT
I
I
I
A...-j
I
I
I
I
I
I
I
.....-
I
I ~
I
i
t---r a
I 15V
I 15V :
r
t-I
p..'p"__I-_....-ogUT'UT
E-.!
.....-:
~
ounUTli
OV
:
~o~
Q~,,~
••..I
~'5V~15V
1 Pulse generator characteristiCS
ZOUT : bOn, t,:4 =15±5 nS,PAR '" 1 MHz
2 Propagation delays.
A" Gate n Input to logical "0" output
"Includmll Ilg and probe
B " Gate n IIIput to logical "1" output
C = Gate Q Input to luglcal "1" output
D = Gate n Input to logical "0" output
E = Gate 0: Input to logical "0" output
F " Gate 0: mput to logical "1" output
7·9
.
LM5522/LM7522 and LM5523/LM7523
electrical characteristics
Q)
o
o
LM5522/LM5523: The following apply for -55°C::; T A
::;
N
125°C (Note 1)
TEST CONDITIONS (EACH AMPLIFIER)
It)
,....
PARAMETER
~
..J
MIN
10181
o
Differential Input
Threshold Voltage
(Vnl) (Note 2)
It)
It)
Differential & Reference
Input BIas Current
"N
~'
351331
TV.
15
15
40
40
30
MAX
201221
451471
100
UNIT
mV
mV
mV
mV
"A
DIFF.
INPUT
REF.
INPUT
tV TH
tSmV
±VTH
15mV
tV TH
±VTH
40mV
40mV
OV
LM7522/LM7523: The following apply for O°C::; T A
..J
11181
DifferentIal Input
Threshold Voltage
361331
(V TH ) INote31
Differential & Reterence
Input Bias Current
15
15
40
40
30
iV TH
44(47)
mV
mV
mV
mV
75
"A
OV
191221
iVTH
iV TH
iV TH
OV
::;
STROBE
INPUT
GATE
INPUT
lOGIC
OUTPUT
SUPPLY
VOLT.
+5V
+5V
+5V
+5V
+5V
-I'5V
+5V
+5V
-400J.l,A
+16mA
-400IJ,A
+16mA
±5V
±5V
±5V
±5V
+525V
+525V
COMMENTS
Logic
Logic
Logic
Logic
Output
Output
Output
Output
>2
<0
>2
<0
4V
4V
4V
4V
t5.2SV
70°C
15mV
15mV
40mV
40mV
OV
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
-400 p.A
+525V
+5.25V
tS 2SV
+5.25V
+525V
±52SV
+16mA
-400J.l.A
+16mA
±5V
±5V
±5V
±6V
Logic Output >2.4V
Logic Output 2.4V
logic Output <0 4V
LM5522/LM5523: The following apply for -55°C::; T A::; 125°C
LM7522/LM7523: The following apply for O°C::; T A
Dlff Input Offset Current
Logic "1" Input VOltage
(Strobes)
(Gate)
05
2
2
Logic "0" Input Voltage
(Strobes)
(Gate)
Logic
"a.. Input Current
-1
Logic "1" Input Current
(Strobes)
2.4
Logic "0" Output Voltage
(Strobes)
(Gatel
Output Short CircUit
Current
-21
Output Leakage Current
-28
0.01
::;
70°C
OV
40mV
40mV
20mV
20mV
+2V
OV
+475V
+2V
+16mA
-400v.A
±5V
±5V
Logic Output <0 4V
Logic Output >2 4V
08
0,8
V
V
40mV
40mV
20mV
20mV
>{l8V
OV
+4.75V
+O.SV
-400 "A
±5V
±5V
Logic Output >2.4V
Logic Output <0.4V
-16
mA
40mV
20mV
>{l4V
>{l4V
±5.2SV
Each Input
"A
mA
"A
mA
OV
OV
40mV
40mV
20mV
20mV
20mV
20mV
+2.4V
+52SV
+525V
+52SV
+S.2SV
+525V
+2.4V
+S.2SV
±5.25V
±S.25V
±5.25V
±S 2SV
V
40mV
20mV
>{l8V
+2V
V
V
40mV
40mV
20mV
20mV
+2V
OV
+4.75V
>{l.8V
mA
40mV
20mV
OV
+S.25V
3.
025
025
OV
V
V
40
1
40
1
(Gate)
Logic "'" Output Voltage
"A
0.40
0.40
-3.5
250
+16mA
-400 JJ.A
±4.75V
+16mA
+16mA
±4.75V
±4.75V
rle PinS 10 and 12
Tie PinS 10 and 12
OV
±5.25V
Tie PinS 10 and 12
+5.25V
±475V
"A
OV
20mV
V+ Supply Current
23
36
mA
OV
20mV
OV
OV
±5.25V
V- Supply Current
-13
-18
mA
OV
20mV
OV
OV
±5.25V
OV
+2V
LM5522/LM5523 and LM7522/LM7523: The following apply for T A = 25°C, V+ = 5V, V- = -5V
AC Common Mode Input
Flrmg Voltage
PropagatIon Delays
Differential Input to
logical" 1" Output
DifferentIal Input to
LogIcal "0" Output
±25
V
26
os
20mV
AC Test CirCUit
"S
20m"
AC Test CirCUit
"S
20mV
AC Test Circuit
"S
20mV
AC Test CirCUIt
"S
20mV
AC Test Circuit
"S
20mV
AC Test CIrcuit
21
Strobe Input to
45
22
Logical "'" Output
Strobe Input to
Logical "0" Output
12
Gate Input to
40
4
Logical "'" Output
Gate Input to
Logical "0" Output
15
Differential Input Over·
load Recovery Time
10
"S
5
"S
200
"S
Common Mode Input
Overload Recovery
Time
Min Cycle Time
e
25
PULSE
20mV
+5V
+5V
SCOPE
Note 1. For 0° C ~ T A ~ 70 0 operation, electrical characteristics for LM5522 and LM5523 are guaranteed th~ same as LM7522 and LM7523,
respectively
Note 2: Limits In parentheses pertaIn to LM5523, other limits pertain to LM5522
Note 3. Limits In parentheses pertain to LM7523, other limits pertain to LM7522
No-te.4· Positive current IS defined as current mto the referenced pin
Note 5: Pin 1 to have:? 100 pF capacitor connected to ground
7·10
r-
s:
U1
U1
LM5522/LM7522 and LM5523/LM7523
N
o
.....
rschematic diagram
s:.....
connection diagram
U1
N
o
}--+---_+OCE~T
IIEFERENCE
•N'UT
en
...CD
f<
,-
CD
(I)
r
"---,...----'
glffllll."A~ i
OIFFEIIENThU
111'1111
IIIPUT,t,l
TOP VIEW
Order Number LM5522J or LM7522J
Se. Packag. 17
Order Number LM7522N
See Package 23
Order Number LM5523J or LM7523J
See Package 17
Order Number LM7523N
See Package 23
"
OUTPUT
AC test circuit
DtfFEflEMTlAl
STROlE
IN'IIT
IN'UT
T
li,FINCLUDING
A
. ." "..'
...
voltage waveforms
------
~~
I
!DIIIV
OIFfElIlNTIAL
ZOm.
20 "'v
I
I"'UT
--..j
100..
1
tGmll
I
...'
I
~3IB"'-----I
II
01/
_________ 3\1
~15V
£::'i~;-----:
~~.-I C - OV
STRDBEINI'UT----'!'··:
,---+--3ID"'~
' ' ' ' ' £---1-f
15V
.-
LOGIC
DUWUT
-----l
~:
I
I
I
--I
I--A--t
i
I
a
1--'
I
.....
I---
~--3V
I
1511
--i
C
laDnI
~:
I
~"
r-' i~
I
I
I
f-F
'I~"
~
'5V
1511
'511
1511
1511
1. One strobe IS grounded when the other stdo IS bemgtested
2. Pulse generator characteristics.
ZOUT = 50n, t, = tt" 15 ±5ns, PRR = 1 MHz
3.Propag&tlondelays:
A =,D,tferantlal mputto logical "0" output
B=DtfferentlalmplittololPcal"'''output
C =Stl1lbe mputto logical "0" output
D=Strobemputtologlcal"1"output
E= Gatemputto logical "1" output
F = Gate mputto logical "0" output
'511
7-11
...
II)
,O2 4V
LogiC Output <0 4V
LogiC Output >2 4V
t525V
LM7524/LM7525: The following apply for oOe ~ TA ~ 70 0 e
Differential Input
Threshold Voltage
NTH) (Note 3)
15
11181
15
361331 40
40
D,fferentlal & Reference
30
Input 81as Current
±VTt-i
tV TH
441471
mVmV
mV
mV
75
~A
OV
191221
tV TH
±VTH
15mV
15mV
40mV
40mV
+5V
+5V
+5V
+5V
OV
+16mA
-400~A
+16mA
-400~A
±5V:!:S%
LogiC Output <0 4V
t5V ±5%
LogiC Output >2 4 V
LogiC Output <0 4 V
±5V ±S%
±5V ±S%
LogiC Output >2 4 V
±525V
+525V
LM5524/LM5525: The following apply for -55°e ~ TA ~ 125°e
LM7524/LM7525: The following apply for oOe ~ T A ~ 70 0 e
0lt1 Input Offset Current
LogiC "'" Input Voltage
logiC
"0" Input Voltage
-1
LogiC "0" Input Current
5
0.02
logiC "'" Input
Current
logiC "'" Output Voltage
2.4
OV
OV
+525V
±525V
-400~A
±5V
LogiC Output >2 4V
±5V
LogiC Output 2
<0
>2
4V
4V
4V
4V
±S 25V
oOe::; T A ::; 70°C
±VTH
44147)
mV
mV
mV
mV
75
"A
OV
191221
STROBE
INPUT
±VTH
tV TH
tV TH
15mV
15mV
40mV
40mV
OV
+5V
+5V
+5V
+5V
+16mA
-400 "A
+t6mA
-400 "A
+525V
±5V
±5V
±5V
±5V
Logic Output <0 4V
Logic Output >2 4V
logic Output <0 4V
Logic Output >2 4 V
±S 25V
LM5528/LM5529: The following apply for -55°C::; T A::; 125°C
LM7528/LM7529 : The following apply for oOe::; T A ::; 70°C
Dlff I nput Offset Current
Logic "1" Input Voltage
05
Logic "0" Input Voltage
Logic "0" Input Current
-1
Logic "1" Input
Current
Logic "1" Output Voltage
5
0.02
2.4
0.25
OV
OV
±525V
+525V
±5V
Logic Output >14V
:t5V
Logic Output <0 4V
V
40mV
20mV
+2V
08
V
40mV
20mV
+D8V
-1.6
mA
40mV
20mV
+D4V
±525V
40
1
"A
mA
OV
OV
20mV
20mV
+24V
+5.25V
±5_25V
±525V
V
40mV
20mV
+20V
V
40mV
20mV
+0 av
+16mA
±475V
+525V
OV
±525V
3.9
Logic "0" Output Voltage
Output Short CirCUit
Current
"A
2
040
-400 "A
+16mA
-400 "A
±475V
-28
-35
mA
40mV
20mV
V'" Supply Current
29
40
mA
OV
20mV
OV
±525V
V- Supply Current
-13
-18
mA
OV
20mV
OV
±5.25V
-21
LM5528/LM5529 and LM7528/LM7529: The following apply for T A
AC Common-Mode Input
FIring Voltage
±25
V
PULSE
20mV
+5V
= 25°C. V+ = 5V. V- = -5V
SCOPE
Propagation Delays
Differential Input to
Logical "1" Output
20
Differential Input to
Logical "0" Output
28
Strobe Input to
Logical "1" Output
10
Strobe Input to
Logical "0" Output
Differential Input Over·
load Recovery Time
ns
20mV
AC Test CirCUit
ns
20mV
AC Test CirCUit
ns
20mV
AC Test CircUit
20
ns
20mV
AC Test CirCUit
10
ns
5
ns
200
ns
Common-Mode Input
Overload Recovery
Time
Min. Cycle Time
Note 1: For
oOe ::;; T A
::;;
700e
40
30
operation, electrical characteristics for lM5528 and
guaranteed the same as LM7528 and LM7529 respectively.
Note 2: Limits In parentheses pertain to LM5529, other limIts pertain
Note 3: limits In parentheses pertain to LM7529, other ltmlts pertain
Note 4: Positive current is defined as current Into the referenced pin.
Note 5: Pin 1 to have 2:100 pF capacitor connected to ground.
Note 6: Each test POint to have::;; 15 pF capacitive load to ground.
7·14
to LM5528.
to LM7528.
LM5529 are
r-
:s:
U1
U1
LM5528/LM7528 and LM5529/LM7529
N
o
.........
r-
schematic diagram
:s:...,
connection diagram
U1
N
,.<>------..---....-----,
TEST
POINT
J---1r-----+-o<..,
"
STROlE OUrnJT DunUT STROlE
A
A
A
I
o
TEST
,olin
•
.
C/)
•
CD
CD
en
r
DifFERENTIAL
C. XT
I
IN'UT A ~
\..............
DIFFERElfTiAl
IN'UTA
l
STROBE A
~
DifFERENTIAL
IN'UTI
1,.,IIT
TOP VIEW
Order Number LM5528J or LM7528J
See Package 17
<>---+---I+--++--J
Order Number LM7528N
See Package 23
Order Number LM5529J or LM7529J
See Package 17
Order Number LM7529N
See Package 23
r
DIffERENTIAL
INPUTB
~
I
l
L
STROBEIo---+-------+---J
voltage waveforms
AC test circuit
OIHEREIiTlAl
INPUT
~~
I
.:
i
:
---
~-_-O\l+-5V
DIffERENTIAL
20m\!
tomV
za",\1
28",Y
IN'UT
-----1'OO"'~
,
I
~
...'
OV
r--------lOOn.--------.,
~1~~----JV
STRO.EIN~~lDD.~~~ ··I~nI ~ov
.~ r-- i'
~<-i:-----<:'
~
lOGIC
15V
lSV
1 SV
15V
OUnUT
1 Pulse generator characteristics
ZOUT = 50n, t.- :If =15±5 os, PRR" 1 MHz
2 Propagation delays
A '" Differential mput to logical "1" output
B '" Differential mput to logical "0" output
C '" Strobe Input to logical "1" output
0'" Strobe mput to logIcal "0" output
7-15
en
Q)
...
LM5534/LM7534 and LM5535/LM7535
electrical characteristics
Q)
en
o
LM5534(LM5535 : The following apply for -55°C:S; T A :S; 125°C (Note 1)
N
TEST CONDITIONS (EACH AMPLIFIERI
,...
It)
PARAMETER
~
...I
Olfferentlal Input
Threshold Voltage
......
o
(VTH ! (Note 21
MIN
10181
35133)
N
Differential & Reference
Input Bias Current
It)
It)
~
TYP
15
15
40
40
30
MAX
201221
451471
100
LM7534(LM7535: The following apply
...I
Differential Input
Threshold Voltage
(V TH I (Note 3)
1118)
361331
Differential & Reference
Input Bias Current
15
15
40
40
30
DIFF.
INPUT
REF.
INPUT
mV
mV
mV
mV
!.VTH
15 mV
15mV
40mV
40mV
"A
OV
UNIT
tV TH
±VTH
tV TH
OV
STROBE
INPUT
+5V
+5V
+5V
+5V
LOGIC
OUTPUT
+525V
+20 rnA
+525V
+20mA
SUPPLY
VOLT.
15V
±5V
±5V
±5V
COMMENTS
Logic Output <250 IJ.A
LogIC Output <0 4 V
LogiC Output <250 IJ.A
logiC OutPUt <0 4V
±525V
+525V
f~r O°C:S; T A :S; 70°C
±VTH
±VTH
441471
mV
mV
mV
mV
75
"A
OV
191221
±VTH
±VTH
15 rT'V
15mV
40mV
40mV
OV
+5V
+5V
+5V
+5V
+5.25V
+20mA
+525V
+20mA
±5V
±SV
±5V
±5V
LogiC Output <250 IJA
LogiC Output <0 4V
LogiC Output <250 JJA
logiC Output <0 4V
±525V
+525V
LM5534(LM5535: The following apply for -55°C:S; T A :S; 125°C
LM7534(LM7535: The following apply for O°C:S; T A :S; 70°C
Dlff Input Offset Current
05
LogiC "0" Input Voltage
LogiC "1" Input Voltage
LogiC "0" Input Current
"A
0.8
2.0
-1
LogIC "1" Input
Current
5
0.02
LogiC "0" Output Voltage
0.25
Output Leakage Current
0.01
OV
OV
+525V
1525V
V
40mV 20mV
+08V
+5.25V
±5V
LogiC Output <250 IJ.A
V
40mV
20mV
+2.0V
+20 mA
:t5V
LogiC Output <0.4V
-1.6
mA
40mV
20mV
+O.4V
±5.25V
40
1
"A
mA
OV
OV
20mV
20mV
+2.4V
+525V
±525V
±525V
V
40mV
20mV
+2V
+20 mA
±4.75V
250
"A
40mV
20mV
+O.8V
+525V
±475V
0.40
_V+ Supply Current
28
38
mA
OV
20mV
OV
±525V
V- Supply Current
-13
-18
mA
OV
20mV
OV
±525V
LM5534(LM5535 and LM7534(LM7535: The following apply for T A = 25°C, V+ = 5V, V- = -5V
AC Common-Mode Input
FIring Voltage
PULSE
20mV
+5V
SCOPE
12.5
V
Differential Input to
Logical"'" Output
24
ns
20mV
AC Test Circuit
Differential Input to
Logical "0" Output
20
ns
20mV
AC Test CircuIt
Strobe Input to
Logical"'" Output
16
ns
20mV
AC Test CirCUit
Strobe Input to
Logical "0" Output
10
ns
20mV
AC Test Circuit
Differential Input Over·
load Recovery Time
10
ns
5
ns
200
ns
Propagation Delays
Common-Mode Input
Overload Recovery
Time
Min. Cycle Time
40
30
Note 1: For OOC :S;TA :S;70oC operation, electrical characteristics for LM5534 and LM5535 are
guaranteed the same as LM7534 and LM7535 respectively
Note 2: Limits In parentheses pertain to LM5535, other limits pertain to LM5534.
Note 3: Limits In parentheses pertain to LM7535, other limits pertain to LM7534.
Note 4: Positive current is defined as current into the referenced pin.
Note 5: Pin 1 to have 2: 100 pF capacitor connected to ground.
7·16
r-
3:
C1I
C1I
LM5534/LM7534 and LM5535/LM7535
N
o
.......
r-
schematic diagram
3:
.....
connection diagram
C1I
N
,.o------.---t------,
J-----i-----t-o,...
y.
STAOBE DunUT
A
OUTPUT
8
A
STROBE
I
o
en
NO
CONN
...CD
""",,,,{.
CD
III
INPUT
'--....,,--I
CEXT
OlffERENTIAl
'N'UTA
DlffERENTJAL{
limIT A
-
+
~
'-...---'
OIFf[REIITlAl
Ile~:~:u
INPUTB
TOP VIEW
Order Number LM5534J or LM7534J
See Package 17
Order Number LM7534N
See Package 23
Order Number LM5535J or LM7535J
See Package 17
Order Number LM7535N
See Package 23
AC test circuit
voltage waveforms
DlfF£IIENTIA~
STROle
"""
INPUT
.----.- <",
v·
TUT
'OINT
STROlE
II
II
OUTPUTOUTPUTSTR08E
II
8
TEST
POINT
•
C/)
•
...CD
CD
REfUENCE{
IIiPUT
(II
COXT
"-----...---'
DIFFERENTIAL
INPUT A
OlfUAENTIAL{
INPUT A
~
INPUT
'--.---'
DIFFERENTIAL
INPUT I
TOP VIEW
Order Number LM5538J or LM5538J
See Package 17
Order Number LM7538N
See Package 23
Order Number LM5539J or LM7539J
See Package 17
Order Number LM7539N
See Package 23
voltage waveforms
AC test circuit
DiffERENTIAL
STROle
INPUT
INPUT
r - -.....-OV·~5\1
~~
I
:
1
--
DIffERENTIAL
20mV
'NPUT
20,.V
HmY
21 ..11
:
----l
110 M
I
t----
...'
DV
to--- 30001$-----1
I
~
~1-:V---l\l
STAO'EI"~M3DDnl~~~·~~ .. ~DV
OUTPUT
r-----i 1--1
t--.l I----l \--0
.-J
~-.
r::----'~
~'~
....
r.:::-
~IW
1 Pulse generator charactenst,cs
ZOUT" 50,11, I, = 4" 15±5 liS, PRR" 1 MHz
2 Propagation delays
A= D,fferent,al mputto logical "0" output
B= Differential mpulto logical "1" output
C;Strobe mput to logical "D"output
D = Strobe ,nputto log,cal "1" output
7·19
.
UI
Q)
guaranteed performance characteristics
Q)
CJ)
o
N
It)
,...,
:!
...J
Differential Input Threshold
Voltage
.......
o
N
48
It)
It)
40
~
...J
lM55ZOllMnt2i
lM55241lMUZII
lMSS34ILMSUI
$TRO.[ IN~IJT -fV -
",,,.,MUM
,%
;;
:!
-55 C '- TA " IU C _
",<05\1'5%
_
'1-'-511
'"
~>
32
~
24
"~
a:
....
'"
Differential Input Threshold
Voltage
48
~
lMSS2lllMS511!
lMS52Slllil!SSlli
lM55JSIlMSUt
STRQIEIIIII'UP-2V
40
~
"""'~I"'UM
lM5Sl4IlM~11
lMUM/UIS!."-
16~ ~LM'5211lM5S231
32
">
~
"
~
....
'"
lMUlOIUIIH2lI
"""'MUM
r- t~~~~~:~~1
~lM'SWl~~
t--MAXIMUM
LM15211lM1UJI
lM1U5ILII!152"
UoII1U51lt,0539
MAXIMUM
W
'"
~
t= ~:;:!:;~::!!!;~
OC<.T.",,71It
'1·'511' 5%
Y-'-iV ".
;;
24
~
LM1UOllM1S12!
lM15241lM1S21'
LM15)41LM1~J'
""'fIMUM_
'·"""·"'f$
16
LMlUSllMIS211
lM1SnlUl1U9
MINIMUM
8
8
15
25
20
30
40
35
15
25
20
REFERENCE VOLTAGE (mV)
30
40
35
REFERENCE VOLTAGE (mVI
typical performance characteristics
Transfer Characteristics
5.0
lMSSzn lMS511 lMl!02B
U"~I
10 ounUT GIn VI
~=,:~~;~:::~~;~:~~;~:~m (0 OUTPUT DIn "
U""~l4 lM~5n LM1~' lMl~n
lM~521'lM5S19'LMnli
~
.
v' ·5V
V-'-$V
w
"....>
=>
SlAOIE
3.0
2.0
~
"
I
l.oue
to
!:;
l~AO''''~
lM1Slil
4.0
-
"
~
Am1Eic:1
VOlUGI
-u.,v
t--I-
IIEHAINel
VOLTAGE
_ • .,V
I
1.0
±5
~::::;t::~:;~:;::;t:~:: t n En
4.0
"·~·-r
w
'"
~
"....>
-
~
I
"
I
lOAO.,.1
0
~
I
AUEAENeE
VOtUGl
·lh.V
±10 ±15 ±20 ±25 ±30 ±35 ±40
3.0
l-
2.0
co
>
"e>
1ll
">
'"
"'"
III
RlflRE1tC1
VOLTAGE
·n_v
t--
:z:
....
..
~
c;
18
,....
~
....
19
~~E5~::CE
vri i
GE
2T i-
Vi' j5.0V1
-35
LOAO~._ t-
'j.+- I--
±15 ±20 ±25 ±30 ±l5 ±4O
45
rc)
85
125
_(1
;:: 14.6
ill
~
c;
1
4 75
.
REFERENCE VOLTAGE
14.4
-4.75
~
""
= 15 mV
-5.00
-5.25
V- (V)
Differential Input Bias Current
50
j
1.4
1.3
12
1.0
40
a:
~
~
35
;;
v+" 5V
V-· -5V
cc
a:
I,,~A' 25=C
45
....
ill
a:
J
11
t-
-5r C "I TA f'2fC
55
Z
5.0
14.8
-
y+ =5.25~
y+= 5.0V
16.2
~
~
TA
7·20
-n_v
'"!:;
..'"
.
~
1la:l
15.0
w
21
20
~
t---
_,,_v
">
~
1
1
15.6
15.4
.
22
~
....
w
!:;
Differential Input Frequency
Response
"'
'"
!:;
IImlEtcE
VOLTAGE
±5 ±10
..'"
-
15.8
DIFFERENTIAL INPUT VOLTAGE (mV)
T emperatu re Coefficient
..
1
V··SV
V-'-511
T,,'He
STROlE ?2V
0
'ULLU'
;;
oS
II
IIHEIIE""
VOUAGE
!
1.0
01FFERENTIAL INPUT VOLTAGE (mVI
;;
oS
Power Supply Rejection
Transfer Characteristics
50
DIFFERENTIAL INPUT VOLTAGE
v+" 5 25V
V- =-5.25V
=OV
"\
"
30
25
.............
I-
20
15
10K
lOOK
1M
10M
100M
SINUSOIOAL INPUT FREQUENCY (Hzl
-35
+5
+45
TA
rc)
+85
+125
r-
3:
U1
U1
typical performance characteristics (cont.)
N
o
.......
Differential Input Offset
23
27
DIFFERENTIAL INPUT VOL TAGE '" OV
09
07
"....E
06
B
.... 05
B
>-
1
....
~
08
~
"- ....... .......
w
~
0
04
0.3
~
~
g,
ill
21
".5....
19
V-'-525V
~
13
~
13
+85
+45
+125
+S
Power Supply Currents
"....£
I
>-
t
ill
26
lM5524/lMnn/lMJSZ4IlMJ525
28
r---
I I
! I
I
DIH~RENT'IALIN~T V~l2DmY
TAG~
I'"
v-·r
14
NEG1TlVESU"tjcuAR1uT
2SV,
"E....
24
~
OY
AEfEAEHCE VOLTAGE
STROlEINPUTS-OY
V'-5UY
18
+125
+'.5 '
I I
~J=::;~=::J:~:~::;t:;~;
+S
1
-
20
~
16
V··+525\'
v~ ~ -5 ZSV
I
~
I
-
.'"~
+45
+85
+125
f-I-
~
~
I I I
11 1
~
z
;::
~
26
0
I I I
:1
0
g:
J
22
I llA
L...I--1"I
20
18
-3S
+5
+45
~
0
.
0
V
IOHAJTO 11 OUTPUT
+85
+45
+S
-2
5
V
~
g:
30
34
]
SU:ACTEl,tn+1l
42
>
.~
..'"
,/
/'
OHAYTO 1 OUTPUT
0
,/
I I I I
+5
1 11
:1
0
.......
g:
I---
lMSS22/lM5523/lM7S22/lM7523
>-
.
30
g
-35
+125
DelAY TO "1" OUTPUT
30
0
;::
26
:1
24
~
~
lM5534/lM5535/lM1534/lM153S
lMS538/lM553S/lM1538/lM1539
~
~elAY
22
20
I I I
18
~
1
I -I.A"
l..-+'1 "~'~~~~:UOT-:::;
111~
-
-35
+5
24
]
22
>-
20
~
. ~·~~~~:~i
SEE AC TEST CIRCUIT
~ -/
"'"
TO "0" OUTPUT
22
+S
+45
+85
+125
11
....
~
;::
~
:1
0
g:
18
16
14
12
10
V
+85
+125
TA eC)
Strobe to Output Propagation
Delays
4B
lM5UDIl MS521Il M152t1/LM1521
IDEUVSTOnOUTPUTONlV)
tMS5Z4ItMU25ILM1S2'ILM1SZ5
tMS&211lMSS29ILM152I1LM1S2'
I I I
OHAYTO 0 OUTPUT
-"
I I I
I I I
-"':"":. +"
-3S
+45
+5
-35
Dolays
I I I
f- -
/
/'
26
24
~
/
28
Strobe to Output Propagation
26
28
I "1
-/
32
20
26
+85
36
32
+125
SUACTUTCIRCUIT
Differential Input to
Output Propagation Delays
34
-
+8S
SEj AYESl ClrU1i
TA rC)
!
+45
0
;::
I--t""
DHAYTD G ounUT
'=
Differential Input to Output
Propagation Delays
1/
46
34
NErTit E i'RI~G VOLT~GE
-3S
+125
36
38
I
-1
eel
lM5S20IlM5S21IlM1S20IlM1S21
(QElAYSlO!iOUTPUTOfilLYI
>-
REFE~EN~E ViOL T~GE I, 20lmv
y+ '" +5Y
-3
50
]
./
./
I I I
24
+125
=-+ PciSITI~E f"Rl~G V~l T~GE
'j
f - r-
Differential I nput to Output
Propagation Delays
OE~OUTPUT
0
r
til
+85
+5
-4
-35
V
lM5520/tM5521/UI1520llM1S21
IOElAVSTOQOU1PUTONlV)
lMSS241lMS5251lM1S241lM1525
lMr.s2'/tMS'2t1LM15t8llM1SH
30
28
I
I- r v l - ' t I I
>
I
TA
34
>-
~EGATIVE SUPPl Y CURRENT
w
-I-
12
Differential Input to Output
Propagation Delays
]
I
~
......
11 1
:::~::~;;u~~~lOAVGE za mV
TA lOCI
32
I
t:::::
'OSH!V[SllPPlVCURREN~
DIH1EAElillAliNPUTVOlTllitoOv
B
>-
I I I I
-35
I
...CD
CD
AC Common-Mode Firing
Voltage
'1EGATIVESUI'I'lYCUAR£NT
10
V-i-5r~ -L
-35
Power Supply Currents
~"M55H/lM152I1LM1SZ9
POSITIYESUP'LY
CURRENT
22
15
V+=525V
TA I'C)
T,4, (el
b..J.. 1
+45
N
o
o
......
RE!ERJNC~
VO!TAGE' 20 mV
DIFFERENTIAL INPUT VOL TAGE' OV
AlllOGIC INPUTS' OV
11
-35
U1
.......
19
>-
IS
3:
.....,
J LM5522/lM5523/lM7522/lM7523
Il'--i.......l
POSITIVE SUPPl Y.....
CURRENT
ill
17
11
+S
-3S
30
23
V+=525V
02
r-
Power Supply Currents
Power Supply Currents
Current
10
+5
44
V
!
>-
*..
~
SEEACTESTCIAUIT
",,"
_r'"
40
36
32
;::
28
~g:
24
20
16
12
+45
TA 1°C)
+85
+125
lM5520/lM5521/lM1520/lM7S21
10ErlAYISTO, iio,UTP~T ONLY) . / ~
DElAY
f-
~O ..\ .. O'UTP~T / '
-
Y
~EE ~C TEST CIRCUIT
DElAY TO "0" JUTPlT
1 1
-35
1 1
+S
+45
-i-
+8S
+125
TA 1°C)
7-21
..
I/)
G.l
G.l
typical performance characteristics (cont.)
en
o
N
~
31
..J
!
........
o
>
~
."
.."'"
N
LO
LO
27
~
i-"'"
19
Sf
co
19
5!
17
~
15
co
13
....
DELAY TO "1" OUTPUT
f
15
I'
21
..~
V
fC>
..J
23
>
;::
lM5534/LM5535/lM1534/LM7535
LM5538/LM5539/LM7538/LM7539
25
]
23
Delavs
22
27
~
LM5522/LM5523/LM7522/LM7523
SEE AC TEST CIRCUIT
Gate to Output Propagation
Strobe to Output
Propagation Delays
Strobe to Output Propagation
Delays
,...
LO
Sf
DELAY TO "0." OUTPUT
OILAJ TO
"1" OUTPUT
.V
V
11
20
1/
18
~I-
16 ~4-~-+-+--~~~~~
14
12
SEE AC
1-+-++-71'''-1--+-+-+-1
10 f-+-:~q-
TTilRCr IT
~
f'.
t?
r-~~~~~~~~~
OELAYTOT~
r""o ~'OUTPUT
11
-35
+85
+5
+125
+5
-35
+85
+45
+5
-35
+125
+45
TA ('CI
Gate to Output Propagation
Delavs
Gate to Output Propagation
Delavs
29
.
27
]
~
'"co
;::
~
f
Sf
co
LM5520/LM5521/LM7520/LM7521
(GATE 0 TO ft OUTPUT OELAYSI
SE~ ACITESTC1~CUIT
25
23
DELAY TO "0" OUTPUT
21
II
II
:!
>
g
5f
)
z
co
)
""",V ./
19
17
~
21
19
-j..-
I,;"
V
LM55221LM5523/LM7522/LM1523
SE~ AC IrES-: CI~CUI~
V
17
J..-
15
13 r;ELAY TO "0" JUTjUT
11
co
Sf
DELAY TO "1" OUTPUT
DELAY TO "1" OUTPUT
15
-35
+5
+45
+85
-35
+125
+5
+45
TA ('CI
TA ('CI
typical applications
)----1,-+.) ~~~:~TlON
I
I
I
,L _______________ -.JI
I
I
Large Memory System with Sectored COfe Planes
7-22
p...
+85
+125
+85
+125
r-
~
($I
typical applications (cant.)
U1
N
o
.......
r-
STROll
~
MEilIORYDATA
REGISTER
,----,
I
--l
-.J
U1
I
I
I
I
tlTI
I
I
N
o
'------I
:
I
~---;--..J
lIT I
.en
CD
:
:
I
1----1
I
I
r-----,---I
I
I
I
III 3
I
I
f----1
I
I
I ",. II
-...,
L __ .J
Small Memory System
£lInRNA~
IIIEMORYOATA
"RlGISTtR
r--l
I
I
I
I
I--OOATA
L __ J
t
WIRE OR
COfIIiECTION
La~ge Memory System
7-23
»
J:
o
o....
Analog Switches
~
......
»
J:
AH0014/AH0014C· DPDT, AH0015/AH0015C quad SPST,
AH0019/AH0019C· dual DPST-TTL/DTL compatible
o
o....
~
n
MOS analog switches
»
general description
This series of TTL/DTL compatible MOS analog
switches feature high speed with internal level
shifting and driving. The package contains two
monolithic integrated circu it chips: the MOS ana·
log chip is similar to the MM450 type which
consists of four MOS analog switch transistors;
the second chip is a bipolar I.C. gate and level
shifter. The series is available in both hermetic
dual·in·line package and flatpack.
features
• Large analog voltage switching
±10V
500 ns
• Fast switching speed
• Operation over wide range of power supplies
•
Low ON resistance
• High OFF resistance
•
J:
o
Fully compatible with DTL or TTL logic
o
....
UI
......
»
J:
• Ineludes gating and level shifting
These switches are particularly suited for use
in both military and industrial applications such
as commutators in data acquisition systems, multi·
plexers, AID and D/A converters, long time
constant integrators, sample and hold circu its,
modulators/demodulators, and other analog signal
switching applications. For information on other
National analog switches and analog Interface ele·
ments, see listing on last page.
o
o....
UI
n
»
J:
o
....o
The AH0014, AH0015 and AH0019 are specified
for operation over the -55°C to +125°C military
temperature range. The AH0014C, AH0015C and
AH0019C are specified for operation over the
_25°C to +85°C temperature range.
CD
......
»
J:
o
o....
CD
block and connection diagrams
A~AI~G
r--------..,
I
III
,,:::;~::::""
'.ll~1
I
I
I
I
AN~~~~I
I~
'~A\On
'NA'OG~~""TI
, " i ~' E::.
L__ , , ___ r-\0""
See Package 4
QuadSPST
r--------,
~~~~~OG
"1
ANA~~~~~~~iOG
""""~'""""
AN':::~ i i : II :~:~O"
" if!~:~:~: Ei~:'
L
_
_
eI
I
.~:::;~~~~;O"
'N"~I
I
I
_
...J
to:'~'\o:'tl ,~'G'Cll~",C'
Note All logic mputsshown at lOgiC "1"
Order Number AH0015D or AH0015CD
See Package 2
typical applications
Integrator
I
I
A·~~~~~I
I, A.AlOG
A.ALOo;~~OUT'
~
"":
:
GND
Order Number· AH0014F or AH0014CF
INI
A.A'"~
L __ "
Note AUlogtc Inputs
shown at logiC "1 "
,OGIC
n
r---------,
tJ
l;;-,
'ODIC
·\O~'C
fE:~'"
..J
Note Alilolllcmputs
shown at logiC "1"
___
Order Number AH0014D or AH0014CD
See Package 1
Dual DPST
::::::n:-Gl.
I
,~..
""oo
OUT,
'NA'Dc~lll:
'~A2
I
f
I
I
A.~~O~
•
I
I
I '"
~~~;OG
i~' ~ ~i::
L,
,-1i" __ .....J
'""IC
"l~~'C
,oG,c
A'l~~"
Note Pill COllnectlOnsare Identical for DIP
and flatpack Alllo~lcal mputs shown at "1 ..
Order Number AH0019F or AH0019CF
See Package 4
Order Number AH0019D or AH0019CD
See Package 1
Reset Stabilized Amplifier
'Previously called NHOO14/NHOO14C and NH0019/NHOO19C
8·1
(.)
en
po
0
0
absolute maximum ratings
~
en
po
Vee Supply Voltage
V- Supply Voltage
V+ Supply Voltage
V+IV- Voltage Differential
Logic Input Voltage
Storage Temperature Range
Operating Temperature Range
AHOO14, AH0015, AHOO19
AHOO14C, AHOO15C, AHOO19C
Lead Temperature (Soldering, 10 secl
:::E:
0
0
:::E:
.
c(
CJ
It)
po
0
0
electrical characteristics
:::E:
w
>
-5
:g
-10
~
-15
~
25'C
~
-50
Vee'" 5.0V
V- = -22V
y+ =B.DY
+5
..
...,.
.
f""o.~
-25
o
Driver Gate VIN v. VOUT
'"
~
~
»
::t
AMBIENT TEMPERATURE rc)
i'25
(")
~
_55
V- = NO EFFECT
w
ANALOG
IL
~
It:..
~
105'
v+ '" +10V
I"b-
o
o
I'
125
Leakage v. VIN (ChanneP'OFF")
VIN
::t
150
AMBIENT TEMPERATURE rc)
v+ '" 10V
~
W
_15'
VI~ = JouT'• _1'ov
115
100
-55'
50
z
z
~
,AMBIENTTEMPERATURE rC)
..'"
.."
.~
I"""
i;
200
Is
fo'
0
_15'
-55°C
..
225
/
IL
1..
0
20
_
......
w
-- r-
25
100
~
RON vs Temperature
~ou; = oJ
s
fo'
o
o
(Note 2)
(")
»
::t
-55'C
o
o
(D
.......
»
-20
l!!
::t
!!!
-15
o
o
-25
+10
-10
0
0
0.5
ANALOG VIN (V)
(V)
1.0
1.5
20
2.5
3.0
3.5
INPUT VOLTAGE (V)
(D
(")
Schematic (Single Driver Gate
and MOS Switch Shown)
d·
:::r:
Analog Switching Time Test Circuit
''''':=::Jf'~
',.-DI
ANALOG
...
'"
~.'
II.
r
tS-,.
...
RL
J
UK
...
"
"~
'"
II
I
I
I
'IV
I
~"
I
:
IV
II
I
I
.
I
:
I
I
~tOfl~
I
~IO"-~
selecting power supply voltage
The graph shows the boundary conditions which
must be used for proper operation of the unit.
The range of operation for power supply V- is
shown on the X axis. It must be between -25V
and -8V. The allowable range for power supply
V+ is governed by supply V-. With a value chosen
for V-, V+ may be selected as any value along a
vertical line passing through the V- value and
terminated by the boundaries of the operating
region. A voltage difference between power supplies of at least ~V should be maintained for
adequate signal swing.
v-
~
7
-i5
-15
V+
25
20
15
10
5
0
-5
-5
-10
-15
-20
-25
8-3
en
Q)
';:
Analog Switches
Q)
Ch
o
...
CD
o
::t
«
........
AH0120/ AH0130/AH0140 / AH0150/ AH0160
series analog switches
...
general description
o
Ln
o
::t
The AH0100 series represents a complete family
of junctIon FET analog switches. The Inherent
flexibility of the family allows the designer to
tailor the devIce selection to the particular application. Switch conf,gurat,ons avaIlable include dual
OPST, dual SPST, OPOT, and SPOT. r dsiON) ra~'ges
from 10 ohms through 100 ohms. The ser'ies IS
available In both 14 lead flat pack and 14 lead
cavity DIP. Important desIgn features Include:
«
........
o~
...o
::t
«
........
o
('t)
...
o
•
TTUOTL and RTL compatible logic inputs
•
Up to 20V p-p analog input signal
«
•
rds(ON) less than 10D (AH0140, AH0141,
AH0145, AH0146)
o
...o
•
Analog signals in excess of 1 MHz
•
"OFF" power less than 1 mW
«
schematic diagrams
::t
........
N
::t
•
Gate to drain bleed resIstors eliminated
•
Fast switching, tON IS typically .4 !,-S, tOFF is
1.0 !,-S
•
OperatIon from standard op amp supply voltages, ±15V, available (AH0150/AH0160 series)
•
Pin compatible with the popular OG 100 series.
The AH0100 series is designed to fulfill a wide
variety of analog switching applications including
commutators, multiplexers, 0/ A converters, sample
and hold circuits, and modulators/demodulators.
The AH01 00 series is guaranteed over the temperature range _55°C to +125°C; whereas, the
AH0100C series is guaranteed over the temperature
range _25°C to +85°C.
DUAL DPST and DUAL SPST
oPoT (dill.) and SPOT (diff.)
Nate Dotted line portions ate not applicable
to thedllal SPST.
Note Dottedhne portlonsalenotappi1cable
to the SPOT {differential}
logic and connection diagrams
Order any of the devices below using the part number with a 0 or F suffix. ,See Packages 1 and 4.
DUAL oPST
DUAL SPST
oPoT 10iff)
SPOT (oiff)
4----+-' "---+'0' -.
HIGH LEVEL li10V)
HIGH LEVEL (:tl0V)
HIGH LEVEL (tlaV)
HIGH LEVEL (±10Vt
AHOl40(10n)
AHOl29 130m
AH0126 (80n)
AH0141 110m
AH0145110n)
AH0133 (30n)
AHOl34 (80nl
AH0139130nl
AH0146110U)
AHOl44 (30n)
AH0143(80!I:I
MEDIUM LEVEL (±7SV)
MEDIUM LEVEL (±7,51
MEDIUM LEVEL (±7,5VI
AH0163 (15.11)
AHOl64 (60.11)
AHo\61 (15.11)
AH0162 (50.11)
MEDIUM lEVEL 1±1 5V)
AHOl53 (15n1
AHOl64 (60.11)
8-4
AH0151 (15m
AH0162 (60n)
AH0142 180n)
~
:x
...
o
N
o
absolute maximum ratings
High
Level
Medium
Level
........
~
:x
o
w
o
Total Supply Voltage (V+ - V-I
36V
34V
Analog Signal Voltage (V+ - V A or V A - V-I
30V
25V
Positive Supply Voltage to Reference (V+ - V R)
25V
25V
Negative Supply Voltage to Reference (V R - V-I
22V
22V
25V
Positive Supply Voltage to Input (V+ - Y,N)
25V
±6V
±6V
Input Voltage to Reference (V ,N - V R)
±6V
Differential Input VOltage (V ,N - V ,N2 )
±6V
Input Current, Any Terminal
30mA
30mA
Power Dissipation
See Curve
Operating Temperature Range AH01 00 Senes
-55°C to +125°C
AH0100C Series
-25°C to +85°C
Storage Temperature Range
-65°C to +150°C
Lead Temperature (Soldering, 10 sec)
jOQ~,C
...
........
~
:x
o
,flI.
o
);;
:x
...
...o
U'I
electrical characteristics
o
for "HIGH LEVEL" Switches (Note 1)
........
~
DEVICE TYPE
PARAMETER
SYMBOL
DUAL
DPST
DUAL
SPST
OPDl
(D1 FFI
SPOT
(DI FF)--'
Logic "1"
Input Current
'" -180V. VA
",oov
20
Note 2
POSItive Supply Current
SWitch ON
One OTive' ON Note 2
TA = 25°C
Over Temp Range
Negative Supply
Current SWitch ON
One Driver ON Note 2
All CirCUits
Reference Input
(Enable) ON Current
IRION)
Positive Supply
Current SWitch OFF
I\OFF)
One Driver ON Note 2
TA = 25°C
Over Temp Range
T A =25°C
Over Temp Range
All CircUits
TA = 25°C
Over Temp Range
Reference Input
(Enable) OFF Current
All CirCUits
AH0126
AH0134
AH0142
AH0143
SWitch ON Resistance
r dslON)
AH0129
AH0133
AH0139
AH0144
Switch ON Resistance
rdsiONj
AH0140
AH0141
AH0145
AH0146
Driver leakage Current
(10
SWitch Leakage
Current
IS10FFIOR
IO(QFF)
ISIOFF) OR
SWitch Turn-ON Time
tON
(ii'
22
(/)
30
33
mA
20
mA
-10
-14
16
mA
mA
1010
25
-10
-10
25
-10
rdslON)
10lOFFI
.1
20
25
Over Temp Range
SWitch ON Resistance
Current
.
60
120
",A
All CirCuits
SWitch Leakage
MAX
01
Over Temp Range
NegatIVe Supply
Current SWitch OFF
+ IsioN
TYP
Over Temp Rangp
TA = 25°C
Over Temp Range
IINIOFF)
o
a;
o
en
(11
UNITS
v+:= 120V, V-
Note 2
Logic "0"
Input Current
:x
LIMITS
CONDITIONS
All CirCUits
Vo = 10V
10 = 1 mA
T A = 25°C
Over Temp Range
80
45
150
Vo = 10V
10 -; 1 mA
Vo = 10V
IF = 1 mA
Vo = Vs -; -lOV
TA
•
25°C
20
n
n
n
1
100
nA
100
nA
nA
10
nA
60
Over Temp Range
8 ..
Over Temp Range
01
Over Temp Range
10
08
oA
AH0126
AH0129
AH0134
AH0133
AH0142
AH0139
AH0143
AH0144
Vos'" ±20V
T A =25°C
Over Temp Range
AH0140
AH0141
AH0145
AH0146
Vos'" ±20V
TA '" 25°C
Over Temp Range
AH0126
AH0129
AH0134
AH0133
AH0142
AH0139
AH0143
AH0144
See Test CirCUit
VA'" ±10V TA '" 25°C
05
08
"'
08
1.0
"'
"'
"'
10
SWitch Turn-ON Time
tON
AH0140
AH0141
AH0145
AH0146
See Test CircUit
VA =±10V TA =25°C
SWitch Turn-OFF Time
tOFF
AH0126
AH0129
AH0134
AH0133
AH0142
AH0139
AH0143
AH0144
See Test ClfCUIt
V A "'±10V T A ",2SoC
09
16
SWitch Turn-OFF Time
tOFF
AH0140
AH0141
AH014S
AH0146
See Test ClfCUlt
V A "':tl0V TA=2SoC
11
25
Note 1: Unless otherWise specified these limits apply for -55°C to +125°C for the AH0100 senes
and _25°C to +85°C' for the AH0100C series. All tYPical values are for T A = 25°C.
Note 2: For the DPST and Dual DPST, the ON condItIon IS for VIN = 2.SV; the OFF condItion
IS for VIN =
For the differential SWItches and SW1 and 2 ON, VIN2 = 2.5V, VIN1 = 3.0V.
For SW3 and 4 ON, VIN2 = 2.SV, VIN1 = 2.0V.
o.av.
8·5
III
G)
'i:
electrical characteristics
cZ
o
CD
o
for "MEDIUM LEVEL" Switches (Note 1)
DEVICE TYPE
PARAMETER
~
SYMBOL
::J:
c(
.......
o
an
~
o
SPST
OPDT
y+,. +15 OV. V':. -15V. VR = OV
Note 2
logiC "0"
Input Current
IIN!OFFI
All CircUits
Note 2
All CircUits
'+(ONI
Current SWitch ON
LIMITS
CONDITIONS
SPOT
IDIFFI
All Circuits
TA= 2SoC
UNITS
.TYP
20
120
TA= 2SoC
01
One Driver ON Note 2
.A
.A
01
2
.A
.A
22
30
33
mA
mA
-10
-18
-20
mA
mA
-14
-16
mA
mA
Over Temp Range
TA '" 2SoC
Over Temp Range
MAX
60
Over Temp Range
'-'ONI
All CircUits
One Driver ON Note 2
TA=2SoC
Over Temp Range
One Driver ON Note 2
TA '" 2SoC
Over Temp Range
-10
NegatIVe Supply
o
DUAL
'INION)
Current SWitch ON
~
DUAL
LoQIC ","
Input Current
PoSitive Supply
::J:
DUAL
OPST
:t
o
Reference Input
(Enable) ON Current
IfllONI
All CircUits
POSItive Supply
Current SWitch OFF
I+(OFFI
All Circuits
V IN1
V1N2 '" 0 BV
TA= 2SoC
Over Temp Range
10
10
25
.A
.A
c(
Negative Supply
Current SWitch OFF
'-(OFF)
All Circuits
VIN' = V1N2 = 0 BV
T,,=25°C
Over Temp Range
-10
-10
-25
.A
.A
oCW)
Reference Input
(Enabte) OFF Current
VIN1 = V IN2 '" 08V
T A =25°C
Over Temp Flange
-10
-10
-25
.A
.A
TA '" 25°C
Over Temp Range
10
15
45
100
n
n
n
n
2
500
nA
nA
::J:
.......
All Circuits
I"HOFI'I
~
'"
o
Switch ON Resistance
rdRON)
AHOl53
AHOl51
AH0163
AH016l
Vo = 7 5V
10 '" 1 mA
c(
Switch ON Resistance
rdllON)
AHOl54
AH0152
AHOl64
AHOl62
Vo = 7 5V
10 '" 1 mA
T A "'25°C
Over Temp Range
Va = Vs = -7 5V
T A '" 25°C
Over Temp Range
Vos = ±15V
T A =25°C
Over Temp Range
5
Vos = ±150V
TA=2SoC
Over Temp Range
10
::J:
.......
30
50
o('II
o
DrIVer Leakage Current
(10 + IS)ON
Switch Leakage
Current
IOIOFFIOR
IS(ol'''1
c(
SWitch Leakage
Current
IOCOFF)OR
ISCOFFI
AHOl54
AHOl52
AHOI64
AH0162
Switch Tum-ON Time
tON
AHOI53
AHOISI
AHOI53
AH0161
See Test Circuit
V A =±75V
T A =25°C
08
10
Switch Turn-ON Time
tON
AHOl64
AH0152
AHOl64
AH0162
See Test CircUit
VA =±75V
T A =25°C
05
08
Switch Turn-OFF Time
tOFF
AHOl53
AHOISI
AHOI63
AH016l
See Test Circuit
V A =±75V
TA = 25°C
II
25
SWitch Turn-OFF Time
tOFF
AHOI54
AHOl52
AHOl64
AH0162
See Test Circuit
V A "'±75V
TA = 25°C
09
15
~
::J:
All Circuits
AHOI53
AH0151
AHOI53
AH0161
Not. 1: Unless otherwise specified, these limits apply for -55°C to +125°C for the AH0100 senes
and -25°C to +a5~C for the AH0100C series. All typical values are for T A = 25°C.
Note 2: For the DPST and Dual DPST, the ON condition IS for V,N = 2.5V; the OFF condition
IS for VIN = o.av. For the differential SWitches and SWl and 2 ON, VIN2 = 2.5V, V,Nl = 3.0V.
For SW3 and 4 ON, VIN2 = 2.5V, VINl = 2.0V.
B·6
01
10
10
nA
20
nA
nA
200
~
.'
.'
.'
.'
typical performance characteristics
Power Dissipation
ON Supply CUrrent
vs Temperatu re
vs Temperature
rds(ONI vs Temperature
AH0120 thru AH0140 Se,i ..
100
2.•
500
""
z
"~ 400
~
300
~
~
200
100
~
AHOI43. AHOI42.
AHOI26. AHOI34
".
'"tz
I- I-IONI
~
"
'"
1
F
r-
~ONI
"..
10
.......
,
l3
'"~
I-- I- ~!ONI
vo'"
tov r-
AHOI29. AHOI33.
AHtj~
:=::::: :=::::..::
10 '" 1 rnA
Y+ • -t12V
I I I
V- • -18V
1.0
25
15
100
50
TEMPERATURE rCI
-15 -50 -25
125
0
25
50
~5-50~
15 100 125
Leakage Current vs Temperature
1000
V' ·12.0V
S
~ 100
AHOI54. AH0152
AHOI64. AHOl62
~
~
"z
"
!i;
~
g
~
10
z
"
~
v+
.E
"+15V
y-" -15V
Vo " 7.5V
Is :: 1 rnA
1.0
±10V
Vo OR Vs '" ±1.5V
EAHOI53. AHOI51.
f=AHOI63. AH~
..+-
~
==~CEPT AHOI40. AHOI.I.
-
AHOI45. AH0146
1.0
-15 -50 -25 0 25 50 15 100 125
TEMPERATURE I'CI
m
y+ = +15V
~ 100
~ :~::::: ~=:::~.
10
~
v-· -15V
V- • -IB.OV
s:
H
AH0150 8< AH0160
1000
Yo OR Vs
~
Leakage Current vs Temperature
AH0120. AH0130. 8< AH0140
100
~
TEMPERATURE rCI
TEMPERATURE I'CI
'ds(ON) vs Temperature
AH01501 AH0160 Series
0
" 10
0.1
r"'"
"'"
I--'
AHOI54. AHOI52.AHOI64. AH0162
0.1
25
45
85
65
lOS
125
25
45
TEMPERATURE rCI
85
105
65
TEMPERATURE I'CI
125
Differential Switch Input
Threshold vs Temperature
Single Ended Switch Input
Threshold vs Temperature
I
2.0
~ 2.0
PI:'
~
~L
~~
"
""
l3
"
SWITCHES ON-
~
,.
z
~
~ ~
1.0
I-- I-- ALL SWITCHES
O~ ~
~
-
~~L SWITCHES ON~
r- ALL SWITCHE~ ~ ~
-.. ~
1.0
~
'"
,."z
IVIN1-V1N21~03~
VR " OV
V·-V-·30V
~5~~5
"""
"ill
~
~
0255075100 125
-75 -SO -25
0
25
50
75 100 lZ5
TEMPERATURE I'CI
TEMPERATURE I'CI
switching time test circuits
"9,'-,'"
v",
..
rL
,~
2~Y
5Y
'.
ow
I
I
I
I.::'
I
I
I I
I
I
~
__
W
_
-
Differential Input
Single Ended Input
OUTPUT
"
I
-t,~~
I
I
~
~ ',,, fI
I
I
I
I
I
8-7
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CD
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applications information
CD
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o
co
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...
1. INPUT LOGIC COMPATIBILITY
A.
'
::J:
.......
Voltage Considerations
In general, the AH0100 series is compatible with
most DTL, TTL, and RTL logic families. The ON·
input threshold is determined by the V BE of the
input transistor plus the V f of the diode in the
emitter leg, plus I x R" plus VA' At room
temperature and VA = OV, the nominal ON thres·
hold is: O. 7V +0. 7V+0.2V, = 1.6V.Over temperature
and manufacturing tolerances, the threshold may
be as high as 2.5V and as low as 0,8V, The rules
for proper operation are:
«
oIt)
...
o
::J:
«
.......
o
...
~
o
terminal will open all switches. The VA (ENABLE)
signal must be capable of rising to within 0.8V of
V'NION) in the OFF state and of sinking I AION )
milliamps in the ON state (at V'N(ON) - VA
2.5V). The V A terminal can be driven from most
TTL and DTLgates.
>
3. DIFFERENTIAL INPUT CONSIDERATIONS
The differential switch driver is essentially a differential amplifier. The input requirements for proper
operation are:
IV,N , - V ,N2 1:::: 0.3V
V ,N - VA ~ 2,5V All switches ON
::J:
«
.......
V ,N - VA S; 0,8V All switches OFF
o
...o
M
::J:
«
o
N
....
o
::J:
«
.......
2.5 ~ (V ,N , or V ,N2) - v'A ~ 5V
The differential driver may be furnished by a DC
level' as shown below. The level may be derived
from a voltage divider to V+ or the 5V Vee of
the DTL logic. In order to assure proper operation,
the divider should be "stiff" with respect to I,N2'
Bypassing R 1 with a 0.1 IlF disc capacitor will
prevent degradation of tON and tOFF'
B. Input Current Considerations
I'NION), the current drawn by the driver with
V ,N = 2.5V is typically 20 IlA at 25°C and is guar·
anteed less than 120 IlA over temperature. DTL,
such as the DM930 series can supply 180 IlA at
logic "1" voltages in excess of 2,5V. TTL output
levels are comparable at 400 IlA. The DTL and
TTL can drive the AH0100 series directly. However, at low temperature, DC noise margin in the
logic "1" state is eroded with DTl. A pull-up resistor of 10 kQ is recommended when using DTL
over military temperature range.
If more than one driver is to be driven by a DM930
series (6K) gate, an external pull-up resistor should
be added. The value is given by:
11
Rp = N _ 1 for N
>2
where:
Rp = value of the pull-up resistor in kQ
N
C.
= number of drivers.
Input Slew Rate
The slew rate of the logic input must be in excess
of 0.3V Ills in order to assure proper operation of
the analog switch. DTL, TTL, and RTL output
rise times are far in excess of the minimum slew
rate requirements. Discrete logic designs, however,
should include consideration of input rise time.
2. ENABLE CONTROL
The application of a positive signal at the V A
8-8
Alternatively, the differential driver may be driven
from a TTL flip-flop or inverter.
.,".
~
'---
PM~l:
y,~,
-
---
v.
~
r
~.~.
'--v,~.
1160M~CIt
-
---
v.
~
r
Connection of almA current source between V A
and V- will allow operation over a ±1 OV common
mode range. Differential input voltage must be less
than the 6V breakdown, and input threshold of
2.5V and 300mV differential overdrive still. prevail.
4. ANALOG VOLTAGE CONSIDERATIONS
The rules for operating the AH0100 series at
supply voltages other than those specified essentially breakdown Into OFF and ON considerations.
The OFF considerations are dictated by the maximum negative sWing of the analog signal and the
pinch off of the JFET switch. In the OFF state,
the gate of the FET is at V- + VeE + VSAT or
about 1.0V above the V- potential. The maximum
Vp of the FET switches is 7V. The most negative
analog voltage, V A, sWing which can be accomodated for any given supply voltage IS:
IVAI:SIV-I-Vp - VeE - VSAT or
IV AI<:::;lv-I-8.0 or IV-I2':IV AI+8.0V
For the standard high level switches, VA <1- 181
+8 = -10V. The value for V+ is dictated-by the
maximum positive swing of the analog input voltage. Essentially the collector to base junction of
the turn-on PNP must remain reversed biased for
all positive value of analog input voltage. The base
of the PNP is at V+ - VSAT - VeE or V+ - 1.0V.
The PNP's collector base junction should have at
least 1.0V reverse bias. Hence, the most positive
analog voltage swing which may be accommodated
for a given value of V+ is:
VA
:s v+ - 2.0V or V+ ::: VA + 2.0V
For the standard high level sWitches, V A = 12 2.0V = +10V.
5. SWITCHING TRANSIENTS
Due to charge stored In the gate-to-source and
gate-to-drain capacitances of the FET switch, transients may appear in the output during switching.
This IS particularly true during the OFF to ON
transition. The magnitude and duration of the
transient may be minimized by making source
and load impedance levels as small as practical.
Furthermore, transients may be minimized by
operating the sWitches in the differential mode;
i.e., the charge delivered to the load during the
ON to OFF transition is, to a large extent, cancelled by the OFF to ON transition.
typical applications
Programmable One Amp Power Supply
.1
.. I
I
I
I
<1Iiv
4
I
I
_1SV~
ZEM\I
AOJUST
VOUT '" (±Polaflty) x (BCD Code) x VREF
lOUT - ZA peak. 1A contmuous
VOUT Range - t12V
Full Scale AcquISItIOn Time - 8jis
Four to Ten Bit 0 to A Converter (4 Bits Shown)
".-lOG
outrUT
'"'"
Settlngllme 1J1s
Accuracy 02%
*Note All resistors are 0 1%
8-9
en
Q)
'i:
typical applications (con't)
Q)
t/)
Four Channel Differential Transducer Commutator
o
CD
o"'"
(0
::I:
:
!
t
,····,,~:t!
.:;~.J11.
lIn,
*Note: Vas adlusted to zero
8-10
J.,..
r--rl
L ...'"
.~,\O"
..."""",--++--++--1+-'
IntegratIOn Internal = 10 sec
*Integratlon Error = TOOj.lV
ResetTlme 30j.ls
*Cs = Polystyrene DielectriC
Analog Signal Range 15 Vp·p
Sample Rate 1 MHz
AcquIsitIOn Time: 20j.ls
Drift Rate 0.5 mY/sec
Ana log Switches
AH2114/AH2114C DPST analog switch
general description
The AH2114 is a DPST analog switch circuit comprised of two junction FET switches and their
associated driver. The AH2114 is designed to fulfill
a wide variety of high level analog switching applications including multiplexers, A to D Converters,
integrators, and choppers_ Design features include:
•
Powered from standard op-amp supply voltages
of ±15V
•
Input signals in excess of 1 MHz
•
Low ON resistance, typically 75.(1
•
High OFF resistance, typically 1011 .(1
•
Large output voltage swing, typically ±1 OV
The AH2114 is guaranteed over the temperature
range _55°C to +125°C whereas the AH2114C is
guaranteed over 'the temperature range O°C to
+85°C_
• Turn-ON and turn-OFF
tim~s
typically 1 JJ.s
schematic and connection diagrams
Metal Can Package
"
CircUIt IS shown
with V sw logic" 1"
108K
"
l08K
Order Number AH2114G or AH2114CG
See Package 6A
ac test circuit and waveforms
IIOUT>
',.
v,~,
llou"
FIGURE 1,
FIGURE 2.
8-11
o
~,
absolute maximum ratings
N
:z:
+25V
-25V
40V
25V
136W
Vplus Supply Voltage
Vmmus Supply Voltage
Vplus-Vmlous Differential Voltage
Logic Inp.ut Voltage
Power DISSipation (Note 3)
Operatmg Temperature Range
AH2114
AH2114C
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
c:r:
......
:t
....
N
:z:
c:r:
-5SoC to +12SoC
aOc to +8So C
-6SoC to + 12SoC
300°C
electrical characteristics
(Notes 1 and 2)
AH2114
CONDITIONS
PARAMETER
MIN
"On" Resistance
10 " lOrnA, VGs " OV, TA " 25°C
10 " lOrnA, V GS " OV
Dram-Gate
Vos" 20V, VGs" -7V, TA " 25°C
Static Dram-Source
TYP
75
AH2114C
MAX
100
150
02
Leakage Current
FET Gate-Source
Breakdown Voltage
I G "10pA
Vos" OV
Drain-Gate
VOG "20V, Is" 0
f" 1.0 MHz, T A" 25'C
Source-Gate
Capacitance
VoG "20V,1 0 "0
f"'- 1 OMHz, TA = 2SoC
Input 1 Turn-ON Time
V IN1
=
lOV, T A
=
2SoC
TYP
75
10
60
35
Capacitance
MIN
0.2
MAX
125
160
50
60
35
UNITS
rl
rl
nA
nA
V
4.0
5.0
40
50
pF
40
50
40
~O
pF
35
35
60
60
ns
(See Figure 1)
Input 2 Turn-ON Time
ViN2
::
lOV, TA '" 2SoC
12
15
12
12
ps
06
0.75
06
0.75
ps
(See F,gure 1)
Input 1 Turn-OFF Time VIN1 = lOV, TA = 2SoC
(See Figure 1)
Input 2 Turn·OFF Time V ,N," lOV, TA " 25'C
(See Figure 1)
DC Voltage Range
TA "25'C
50
80
50
80
ns
±90
±1O 0
±9.0
±10 0
V
±90
±100
±90
±1O 0
V
(See Figure 2)
AC Voltage Range
TA " 25'C
(See Figure 2)
Note 1: Unless otherWise specified these specifications apply for pm 12 connected to +15V, pin 2
connected to -15V, _55°C to 125°C for the AH2114, and
Note 2: All
typical values are for T A = 25°C.
Note 3: Derate linearly at 10QoC/W above 25°C.
8-12
aOc to 85°C for the
AH2114C.
Analog Switches
AH5009 series low cost analog current switches
general description
features
The AH5009 series IS a versatile family of analog
SWitches designed to economically fulfill a wide
variety of multiplexing and analog switching applications.
•
Large analog signal range
•
Excellent Isolation
between channels
Even numbered switches (AH5010, AH5012,
AH5014, etc.') may be driven directly from
standard (5V) TTL; whereas the odd numbered
switches (AH5009, AH5011, AH5013, etc.,) are
intended for applications utilizing open-collector
(15V) structures.
• Very low leakage
•
±10V peak
80dB
at 1 kHz
50pA
150 ns
High switching speed
loon
•
Low on resistance
•
Interfaces With standard TTL
functional and schematic diagrams
(See additional types on page 6.)
MUX Switches
SPST Switches
MUX Switches
SPST Switches
(4 channel version shown)
(quad version shown~
(4 channel version shown)
(quad version shown)
::=1f"
6~
"
10- __ J
.~
I
8o- __ ..J
'~'
'~~I
I
r:~,
20---..1
.~-'--o,
I
10---'"
L--t
11~4---09
I
1IIo---_..J
'l~
14~~16
" 0-----1
15O---.J
I
5
!
,1
!"T¥'
,-'2 10
!"~"
.----t !
..L
':'
,
0
13
IS
UNCOMMITTED DRAINS
connection diagrams
Dual-I n-Line Package
,
,
.
Dual-tn-Line Package
Dual-I n-Line Package
,
,
,
Order Number AH5017CN,
AH5018CN, AH5019CN,
AH5020CN, AH5021CN,
AH5022CN, AH5023CN,
or AH5024CN
Order Number AH5009CN,
AH5010CN, AH5013C,N,
or AH5014CN
See Package 22
Order Number AH5011CN,
AH5012CN, AH5015CN,
or AH5016CN
See Package 23
See Package 20
8·13
en
o
oIt)
absolute maximum ratings
::J:
::I:
typical performance characteristics
0'1
o
o
Leakage Current, IO(ON)
Maximum Power Dissipation
~
600
t.
";:::
400
::
~
300
'"~
f
lOOk
1000
..!>
Is _
1.
500
........
f
I'....
.......
i'-.
200
~A.
~
I,:
~
~
10
50
10
0.5
1.0
1.5
150
10k
~
~
./
lk
rI-- 1-'5~111~
~
,.:
z
!l!
I-
./'
~
-- -r-
~
'"'"
'"~
o
10
45
55
65
75
85
35
45
55
65
75
85
TEMPERATURE I"CI
co
35
25
2.0
On Resistance, rOS(ON)
vs Temperature
Leakage Current,IO(OFF)
25
/
SOURCE CURRENT (mAl
vs Temperature
B 100
100
~
/
o
TEMPERATURE I"CI
j
..'"
co
1
100
75
lk
;
j
25
::::
~
V
~
100
./
10k
.!!
100
B
"'
VA'" ±10V
Is'" 1 mA
~
TA - 25°C
I
§
CD
vs Temperature
Leakage Current,IO(ON) vs IS
Cross Talk, CT vs Frequency
-120
-110
-100
-90
~
t; -80
~.
'"
l-
I
-10
-60
-50
-40
-30
-20
-10
25
35
TEMPERATURE I"C)
45
55
65
75
85
100
TEMPERATURE I"C)
lk
10k
lOOk
1M
FREQUENCY (Hz)
test circuits
AC SWitching Test Circuits
VA
±IOV
~
G
VIN
~
S
VO"'
(e l SlllpF)
(OUT)
D
":'
":"
Cross Talk Test Circuit
"~
10K
'D~
8·15
0)
o
o
applications information
J:
Theory of Operation
In
R1(MIN)
VA(MAX) AD
>
VA(MAX)
which ever is worse.
Where:
VA(MAX)
Peak ampl itude of the analog input signal
AD
Desired accuracy
IO(ON)
Leakage at a given Is
loss
Saturation current of the
FET switch
""
FIGURE 1. Use of Compensation FET
(2b)
1055 /10
=. __---~..:..-R, + rOS(ON)Q'
(2a)
IO(ON)
or:
20 mA
In a typical application, VA might = ±10V, AD
0.1 %, O°C < T A < 8SoC. The criterion of equation
(2b) predicts:
10V
R1(MIN)
Skn
- 20MA
>---=
10
For R, = R2, gain accuracy is determined by the
rOS(ON) match between 0, and O2, Standard
match between 0, and O2 is son resulting in a
gain accuracy of O.S% (for R, = R2 = 10k).
Tighter rOS(ON) match versions are available.
Noise Immunity
The switches with the source diodes grounded
exhibit improved noise immunity for positive
analog signals in the "OFF" state. With V 1N = lSV
and the VA = +10V, the source of 0, is clamped
to about 0.6V by the diode (V GS = 14.4V). The
"ON" impedance of the diode is about 26n
ensuring that AC signals imposed on the +10V
will not gate the FET "ON_"
For R, = Sk, Is:; 10V/Sk or 2 mAo The electrical
characteristics guarantee an IO(ON) < lilA at 8SoC
for the AHS010C_ Per the criterion of equation
(2a):
(1 OV) (10- 3 )
R1(MIN) 2::
10kn
1 x 10-6
>
Since equation (2a) predicts a higher value, the
10k resistor should be used_
'" o-"M.-<......- - ,
Selection of Gain Setting Resistors
Since the AHS009 series of analog switches are
operated current mode, it is generally advisable to
make the signal current as large as possible. However, current through the FET switch tends to forward bias the gate to channel (source) diode
resulting in leakage across the diode. This leakage,
IO(ON), increases exponentially with increasing Is.
As shown in Figure 2, IO(ON) represents a finite
error in the current reaching the summing junction
of the op amp.
8-16
FIGURE 3.
The "OFF" condition of the FET also effects gain
accuracy. As shown in Figure 3, the leakage across
O2 , IO(OFF) represents a finite error in the, current
arriving at the summing junction of the op amp.
»
:J:
applications information (con't)
(J1
o
o
(g
ANALOG
,--------,
I
'II'UTIVA)
+5V
I
I
I
I
I
ANALOG
OUTPUT
I
I
I
__ I
I.!::.T~~ __-_..:.j
I
I
I
FIGURE 4. Interfacing with +5V Logic
ANALOG
,-------,
I
I
I
I
I
INPUT
IV,~)
I
I
I
ANALOG
OUTPUT
I
I
...--t--<>--4-o------J
I
~T!!::~
I
I
I
__
I
____ -=..J
FIGURE 5. Interfacing with +15V Open Collector Logic
Accordingly:
R1IMAX)
Where:
<
and the odd numbered types from 15V open
collector TTL.
VAIM IN) Ao
(N) IOIOFF)
VAIM IN)
Minimum value for the ana·
log input signal
Ao
N
Desired accuracy
IOIOFF)
OF F leakage of a given F ET
switch
Number of chan nels
As an example, if N = 10, Ao = 0.1%, and IOIOFF)
10 nA at 85°C for the AH5009C, R lIMAX ) IS:
:S
R lIMAX )
:S
Standard TTL gates pull-up to about 3.5V (no
load). In order to ensure turn-off of the even
numbered switches such as AH5010, a pull-up
resistor, R EXT , of at least 10 kn should be placed
between the 5V Vee and the gate output as shown
in Figure 4.
Likewise, the open-collector, high voltage TTL
outputs should use a pull-up resistor as shown in
Figure 5. In both cases, tloFF) is improved for
lower values of REXT and the expense of power
dissipation in the' low state.
(lV)(10- 3 )
(10)(10 x 10- 9 ) = 10k
RDSlON,COMP£NSATING
HEMEN.!
Selection of R2 , of course, depends on the gain
desired and for unity gain R 1 = R2 .
Lastly, the foregoing discussion has ignored resis·
tor tolerances, input bias current and offset
voltage of the op amp - all of which should be
considered in setting the overall gain accuracy of
the circuit.
FIGURE 6. Oefinition of Terms
TTL Compatibility
Two input logic drive versions of AH5009 series
are available: the even numbered part types are
specified to be driven from standard 5V-TTL logic
Definition of Terms
The terms referred to in the electrical characteristics tables are as defined in Figure 6.
8-17
0')
o
oIt)
device schematics and pin connections
::J:
<
FOUR CHANNEL
AH5009CN (ROS(ON) ::; lOOn 15V· TTL)
AH5010CN (ROS(ON) ::; loon 5V· TTL)
14 PIN DIP
AH5011CN (ROS(ON) ::; loon 15V • TTL)
AH5012CN (ROS(ON) ::; 150n 5V . TTL)
16 PIN DIP
'~'
t L
'7J-..-L'"
t L
"7J-..-L"
t12 !IO
9
"~"
ts
113
THREE CHANNEL
AH5013CN (ROS(ONr::; loon 15V . TTL)
AH5014CN (ROS(ON) ::; 150n 5V· TTL)
14 PIN DIP
AH5015CN (ROS(ON)::; loon 15V· TTL)
AH5016CN (ROS(ON) ::; 150n 5V· TTL)
16 PIN DIP
'~"
t
L
t
1,
'~'.
"~.c
til 1,0
TWO CHANNEL
AH5017CN (ROS(ON)::; loon 15V· TTL)
AH5018CN (ROS(ON) :s; 150n 5V· TTL)
S PIN DIP
AH5019CN (ROS(ON) ::; loon 15V· TTL)
AH5020CN (ROS(ON) ::; loon 5V • TTL)
SPIN DIP
3~"
t L
.~.'
,
,
12
14
11
13
SINGLE CHANNEL
AH5021CN (ROS(ON) ::; loon 15V . TTL)
AH5022CN (ROS(ON) ::; 150n 5V· TTL)
S PIN DIP
'1YPff'
.
,
,
AH5023CN (ROS(ON) ::; loon 15V· TTL)
AH5024CN (ROS(ON) ::; lOOn 5V· TTL)
SPIN DIP
'7J-..-L'"
t. !,
Package Types - 8, 14, 16 pin epoxy "8"
8·18
»
:I:
typical applications
U1
o
o
16-Channel Multiplexer
Gain Programmable Amplifier
CD
EOUT
r
I
I
I
I
I
I
•
'M
I
I
I
I
L_
EOUT
Low Cost Demultiplexer
Note The analog sWltcn between the op amp
and the 16 mputSWItches redllcestheerrors
due to leakage
Characteristics Error" 0 4/-1V typical @ 25~C
10MVtyplcal@1UoC
All resistors are 10K
Low Cost Multiplexer/Mixer
v+-zov
100pf
"
lOOK 3
A""L·~·-1
VODe '"
(V~:fl3).
+IOV
8-19
N
o
o.:!:
Ana log Switches
OV
-:)OV
VORIVE (Note 1)
V S1AS
+40V
+4DV
-40V
+40V
+~lOV
(Note 11
Power DISSlpdtlon @ T A '" 25 C
Lmedf Derdtlng Factor
Power DISSipation @ T c 125'C
Linear Derating Fdctor
Mdxlmum JunctIOn Operating Temperdture
AM1000
AM 1002
Storage Temperature
Ledd Temperature (Soldering, 10 sec)
300mW
17 mWr'C
150mW
6 mWt'C
-55'C to +150"C
+200°C
+300°C
»
s:...
o
o
...
»
s:...
o
electrical characteristics
ON CHARACTERISTICS (Note 21
PARAMETER
MIN
TYP
AM1DOl
20
40
50
AM100D
AM1G02
20
20
25
50
30
100
CONDITION
VORIVE - + 15V, V S1AS - -15V
Rof'J
liN -
1
rnA.
VORIVE ~
RON
V OUT -
OV
+lOV V S1AS
1 mA, V OUT
I"
=
MAX
-lOV
-
OV
UNITS
"
o
U
N
~2
OFF CHARACTERISTICS
PARAMETER
AM1000
AM1001
CONDITION
MIN
VORIVE - -20V, V S1AS '-
IOLJT IOFF:
VIN '"
TYP
AM1002
MAX
MIN
UNITS
TYP
MAX
-lOV
- lOV, VOUT +lOV
TA = +25"C
T A - +125"C
05
025
25
25
05
02
;
1
"A
"A
05
05
25
25
05
02
1
1
nA
MA
TYP
MAX
UNITS
5
10
mA
-lOY
+lDV, V ouT "-10V
VDRIVE - -20V, V S1AS
lOUT (OFF)
VIN
-
T A "'+25C
T A =. +125 C
DRIVE CHARACTERISTICS (Note 3)
PARAMETER
CONDITION
-lOY
VIN = ±10V, V OUT = ±10V
VORIVE
'OAIVE.
(Switch OFF)
=.
-20V, V S1AS '"
MIN
AM 1000, 1001,1002
SWITCHING CHARACTERISTICS
PARAMETER
CONDITION
tON
AM1000
MAX
AM1001
MAX
AM1002
MAX
100
150
200
'"
100
100
100
"'
See SWitching Time
Test CircUit
tOFF
UNITS
Note 1: ~he maximum voltage ratings may be applied between any pm or pms Simultaneously. Power diSSipation may be
exceeded In some modes If the voltage pul~e exceeds 10 ms. Normal operation will not cause excessive power diSSipation
even In a de sWitching application.
Note 2: All parameters are measured with external silicon diodes. See electncal connection diagram for proper diode placement
Note 3: IBIAS (Switch OFF) is equal to IORIVE (Switch OFF). I(BIAS) (Switch ON), is equal to external diode leakage.
Nqte 4: Rise and fall times of VORIVE shall be 15 ns maximum for switching time testing.
switching time test circuit and waveforms
r----Duil
vOUT~DV
I
I
-r-w:
. :
fLIXT'""'
,
,
100
-=-
I
,,
,
I
I
L
____ ...JI
0:-
IN914
IN914
-10V
:
-VOUT
,
,
Jl""'
VORtVE
"
,
:
:
':
,
ION __ ,
:-
:
:
'
.
"
-20V
__ , .·-IOfF
VORIVJ1SL::::
8-21
Analog Switches
AM2009/AM2009C/MM4504/MM5504
six channel MOS multiplex switches
general description
The AM2009/ AM2009C/MM4504/MM5504 are six
channel multiplex sWitches constructed on a single
silicon chip uSing low threshold P-channel MOS
process. The gate of each MOS device IS protected
by a diode circuit.
The AM2009/ AM2009C/MM4504/MM5504 are designed for applications such as time divIsion multipleXing of analog or digital signals. SWitching
speeds are primarly determined by conditions
external to the device such as signal source Impedance, capacitive loading and the total number of
channels used In parallel.
features
•
•
•
•
•
150n
100 pA
±10V
TYPical low "on" resistance
TYPical low "off" leakage
TYPical large analog voltage range
Zero Inherent offset voltage
Normally off with zero gate voltage
The AM2009/MM4504 are specified for operation
over the -55°C to +125°C military temperature
range. The AM2009C/MM5504 are specified for
operation over the -25°C to +85°C temperature
range.
schematic diagram
,"
"
U
+
~~
~~
~~
Pm numbers 10 parenthesIs apply
tor the MM4504/MM5504 only
'!"r
~
"
..L,
r
~
"
,
+
fa
.L,
.
r--
..
-1:
~
,
,
,
.
,
l:
.
Order Number AM2009F, AM2009CF, MM4504F or MM5504F
See Package 4
Order Number AM2009D, AM2009CD, MM4504D or MM5504D
See Package 1
typical applications
ANALOGtNPUTS
ANALOG
OUTPUT
m
ANALOG
INPUTS
OUTPUT
TTL Compatible 6 Channel MUX
8-22
32 Channel MUX
»
absolute maximum ratings
(V BULK = OV)
Voltage on Any Source or Dram
Total Power DISSipation (at TA == 2SoC)
Power DISSipation - each gate Circuit
-30V
-3SV
+03V
SOmA
01 mA
Voltage on Any Ga~e
Positive Voltage on Any Pm
Source or Drain Current
Gate Current (forward direction of zener clamp)
electrical characteristics
s:N
Operating Temperature Range
o
o
900mW
lS0mW
_55°C to +12SoC
- 2SoC to +8SoC
-6SoC to +150°C
300°C
AM2009,
AM2009C
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
CD
.......
»
s:N
o
(Note 1)
o
CD
LIMITS
(')
TVP
.......
CONDITIONS
PARAMETER
MIN
V GS
DC ON Resistance
V GS = -20V,
TA= 2S oC
DC ON Resistance
V GS
IDS
==
IDS =
-100 pA,
lS0
-10V, Vss = -20V,
= -100pA, TA = 2SoC
V GS == -20V, los == ~100MA
V GS '" ~lOV, V SB == -20V,
los == -lOOMA
V GS ==
~20V,
V GS == ~20V,
Note 2
Note 2,
.......
s:
s:
25°C
100
Vos '" -20V, Note 2
Vos == -20V, Note 2, TA '" 25°C
100
TA ==
Output Leakage
V SD == ~20V, Note 2
V SD '" -20V, Note 2, T A'" 25"C
Gate-Bulk Breakdown
Voltage
1GB == -10 MA, Note 2
-35
Source-Dra,n Breakdown
Voltage
Iso == ~lOMA, V GO == 0,
Note 2
-30
Drain-Source Breakdown
los '" ~10 J1A, V GS == 0,
Note 2
-30
Voltage
o
.Jlio
500
DC ON Resistance
I nput Leakage
U'I
=
DC ON Resistance
Gate Leakage
s:
s:.Jlio
-10
V os , los '" ~1 MA
Threshold Voltage
U'I
U'I
o
.Jlio
500
v
v
4000
Transconductance
mhos
Gate Capacitance
Note 3, f "" 1 MHz
47
8
pF
Input Capacitance
Note 3, f '" 1 MHz
46
8
pF
Output Capacitance
Note 3, f
20
pF
=
16
1 MHz
Note 1: Ratings apply over the specified temperature range and VBULK == 0 unless otherwise specified.
Note 2: All other pins grounded.
Note 3: Capacitance measured on dual-in-line package between pin under measurement to all other pins. Capacitances are
guaranteed by design.
typical performance characteristics
"ON" Resistance vs Gate-to-
"ON" Resistance
Source Voltage
Temperature
700
r---,--,,---,--,--.--,
600
r--~:S~~2~1~0IJA+_t-.---l
_
400
r---
;
300""'-'-'
YS
T
Input Leakage Current vs
Temperature
1000=
10
100
-30
-25
-20
-15
YGs(Y}
-10
-5
0
-50 -25
0
25
511
15
TEMPERATURE! C}
loo
125
o
25
50
75
100
125
TEMPERATURE! C)
8-23
Analog Switches
AM3705/ AM3705C 8-channel MOS analog multiplexer
general description
The AM3705/AM3705C IS an eight-channel MOS
analog multiplex sWitch. TTL compatible logic
mputs that require no level shifting or mput
pull·up resistors and operation over a wide range
of supply voltages IS obtamed by constructmg the
device with low threshold P·channel enhancement
MOS technology. To simplify external logic reo
qUlrements, a one·of·elght decoder and an output
enable are mcluded In the device.
Important design features include:
• TTLlDTL compatible mput logic levels
•. Operation from standard +5V and -15V supplies
• Wide analog voltage range - ±5V
• One·of·elght decoder on chip
• Output enable control
•
•
•
Low ON resisfance - 150n
Input gate protection
Low leakage currents - 0.5 nA
The AM3705/AM3705C is designed as a low cost
analog multiplex switch to fulfill a wide variety of
data acquisition and data distribution applications
mcluding cross·point switching, MUX front ends
for AID converters, process controllers, automatic
test gear, programmable power supplies and other
military or mdustrial mstrumentation applications.
The AM3705 is speCified for operation over the
-55°C to +125°C military temperature range. The
AM3705C is specified for operation over the _25°C
to +85°C temperature range.
schematic and connection diagrams
'" z
" 2"
"
....
Z'
V.
...
..... '
V• •
S, •
Il
Voo
II
S,
II
S,
"• ..s,
TOPVIEW
Order Number
AM3706D Dr AM3705CD
Sea Package 2
------.,,".,._-----
block diagram
(MIL·STD·806B)
truth table
lOGIC INPUTS
DATA INPUT
CHANNElNOS
Lhhhhhhh
OOATADUTPut
CHANNEl
2'
2'
2'
DE
ON
L
H
L
H
L
H
L
L
H
H
L
L
H
H
H
H
H
H
H
H
H
H
S,
S,
S,
S.
S,
S,
S,
H
L
L
L
L
H
H
H
H
X
X
X
L
OFF
L
So
typical application
BuHered S'Channel Multiplex, Sample and Hold
LOGIC INPUT
-Botl! Vas IIRes.ra Internally connected.
IItilar ORa or bath may !teUl8d
·.0'
...... 1
AII.LOS
OUffUT
'"Polystyrene OleillCtfiC
Anal ... Signal FIIInp - +5V
Acqulllbon Tlml - 26 ns
OnftRl1e-05mV/rac
Aperature Time - 250 ns
8·24
»
3:
~
absolute maximum ratings
U'I
.......
»
3:
w
.....
o
_55°C to +12SoC
Operating Temperature Range AM3705
AM3705C
Storage Temperature Range
Lead Temperature (Sol~ermg, 10 sec)
_25°C to +85°C
_65°C to +15poC
300°C
electrical characteristics
PARAMETER
o
+03V
-35V
±30 mA
±O 1 mA
500mW
Positive Voltage on Any Pm (Note 1)
Negative Voltage on Any Pin (Note 1)
Source to Drain Current
Logic I nput Current
Power DISSipation (Note 2)
U'I
(")
(Note 3)
SYMBOL
CONDITIONS
MIN
ON Resistance
RON
VIN
ON ReSistance
RON
Y'N ~ -5V, lOUT ~ -100pA
ON ReSistance
RON
V,N ~ -5V, lOUT
T A =+125°C
T A = +70°C
AM3705
AM3705C
V ss ,
=
100 pA
IOUT;=
~
RON
VIN = +5V, Voo = -15V,
ON ReSistance
RON
V IN
ON ReSistance
RON
Y'N ~ -5V, Voo = -15V,
lOUT ~ -100 pA
OFF ReSistance
ROFF
Output Leakage Current
I LO
Vss - V OUT
~
~
lOUT
AM3705
AM3705C
Data Input Leakage Current
AM3705
AM3705C
100 pA
av,
:::;
-100pA
'"
Vss - V OUT ~ 15V, TA ~ 7Q°C
'LDI
'LOI
Vss - V IN := 15V
Vss - Y'N ~ 15V, TA = 125°C
'LOI
Vss - V IN
:;:
15V, T A
""
=
125°C
ILl
ILl
'Ll
Vss - VlOgrc In = 15V
Vss - Vlagrcln = 15V, TA = 125°C
Vss - Vlagrcln = 15V, TA;c.. 70°C
LogiC Input LOW Level
V,L
Vss
LogiC Input LOW Level
LogiC Input HIGH Level
LogiC Input HIGH Level
V ,L
Vss
n
l
~
n
150
n
250
n
05
Voo
3.0
Vss - 2.0
+5 OV
SWitching Time
~
Q
1 kHz
~
~
pA
}J.A
}J.A
1.0
V
V
V
V
ns
ns
62
dB
35
pF
Vss - VOIP ~ 0, f ~ 1 MHz
6,0
LogiC Input Capacitance
C",
Vss - Vlaglc In = 0, f;;:: 1 MHz
60
Power DISSipation
Po
Voo
OV
1
10
10
600
Co,
~
nA
nA
nA
300
Data Input Capac:tance
-31V, Vss
30
500
500
Vss + 0 3
Vss - V OUT
1 MHz
nA
nA
nA
3.5
Cdb
0, f
10
500
500
Vss - 4.0
Output Capacitance
~
Q
100
001
,05
05
+5 OV
ITest Circuit
f
Channel Separation
400
400
01
25
05
70°C
LogiC Input Leakage Current
AM3705
AM3705C
t-
n
n
05
150
35
15V
Vss - V OUT = 15V, TA
Channel SWitching Time-POSitive
400
-
'LO
Channel SWitching Time-Negative
160
10 10
0
UNITS
250
Voo:::; -15V,
I LO
V'H
V'H
t+
MAX
80
-100pA
ON ReSistance
lOUT
LIMITS
TYP
125
pF
pF
175
mW
Note 1: All voltages referenced to VSS.
Note 2: Rating applies for ambient temperatures to +25°C, derate linearly at 3 mW/oC for ambient
temperatures above +25°C.
Note 3: SpeCifications apply for T A ~ 25°C, -24V ~ VDD ~ -20V, and +5,OV ~ VSS ~ +7 ,OV; unless
otherWise specified (all voltages are referenced to ground).
8·25
typical performance characteristics
ON Resistance vs Analog
Input Voltage
300
~ITElT
~
400
T.=+2SoC
lOUT = -100IJA
350
150
t-
50
c:
-5
-3
-1 0
+,
+5
200
+7
.l
100
25
50
~
r '+5r
15 100 125
-10
"
~104
;:i
~
O.ov- t---
-20
-25
"
=frt-
""
V.. ,·IV
V
~ 103
Vour::
Voo SUPPLY IV)
TESTPOINTS
~
-""I.
~~
-15
VOUT - Vss '" 15V
'05
1
-S.ov-
o
10'
ffia:
Vour::
switching time test circuit
Output Leakage Current vs
Ambient Temperature
!
"' .......
TEMPERATURE rCI
INPUT (VI
~
~
1-VO
IIIII
0
~
50
VINPUT'" +7V
-15 -50 -25
Vss '" +5V
-1 00 J.lA
':;,50
-SV
II
100
TA =25°C
lOUT"
rtI
o
+3
TtMoiNtS
VINPUT::
-; 200
a: 150
50
o
2:.0
II
o
100
tUIU.k
_ 250
TESTPOINT~
r-
a:
Vss:: +lV
lOUT "'-100",A
300
I I I I
~
I IJ I I
Voo:: -20V
voo '" -20V
!oILT r-- Vss'+1V
200
ON Resistance vs VOO
Supply Voltago
ON Resistance vs
Ambient Temperature
V",,·IV
'",.
OUTPOT
!
,''-
'I
~
" 10'
o
25
50
100
15
125
TEMPERATURE I' CI
typical applications (con't.)
Differential Input MUX
16-Channel Commutator
'''''''"'/
...:::~: I
"'""'I
'UfCTITTLJ
' ' ' ''"'r
Vottage Gam =200
Differential Input ReSIstance = 10 10 n
CMRR=lDOdB
Input Current"05nA
S-Channel Demultiplexer with Sample and Hold
Wide Input Range Analog Switch
""""I
'!/PuTS
Analog Input Range-25V
Slew Rate - 5 VI/Js
8-26
I'"'
::!l
0)
Analog Switches
C1I
o
.......
I'"'
"T1
N
LF1650/LF2650/LF3650 quad JFET analog switch
0)
C1I
o
.......
general description
I'"'
"T1
The LF1650/LF2650/LF3650 is a monolithic combination of bipolar and JFET technology producing the
industry's first one chip quad FET switch_ A unique
circuit technique is employed to maintain a constant
RON over the analog voltage range. The input is designed
to operate from minimum TTL levels. and switch
operation also ensures a break before make action.
tOFF
•
Open switch isolation at 1.0 MHz
0)
-50 dB
• < 1.0 nA leakage in OFF state
•
TTL. DTL. RTL direct drive compatibility
•
Single disable pin turns all sWitches in package OFF
The LF1650/LF2650/LF3650 is designed to operate
from ±15V supplies and swing a ±1 OV analog signal. The
FET SWitches can be used wherever a dc to medium
frequency analog signal needs to be controlled .
features
•
W
< tON. break before make action
•
Constant ON resistance for signals ±10V and 100 kHz
connection diagram
DuaH n-Line Package
(LogiC "0" In).
S4
IN,
01
OISABLE
+Vcc
S1
53
OJ
D2
IN,
TOPVIEW
Order Number LF1650D, LF2650D or LF3650D
See Package 2
Order Number LF3650N
See Package 23
typical circuit and schematic diagrams
..--......,>---------.....- .....----c
~
IN:;:~~AG} 0
r--------,
Is
I
I
I
(lOGIC "1" > 2 OVI
+Vcc
I
L.
f-.:I~~
__ J~
,----;;--
~r15Vf"-: tfr"
.,:: -
IN
I
-J
V,o---4___
FIGURE 1.
~--~
' - -.....- - - < l - VEE
FIGURE 2.
8-27
C1I
o
o
LD
CD
(W)
U.
...l
........
o
LD
CD
N
u.
...l
........
o
LD
CD
....
U.
...l
absolute maximum ratings
Positive Supply - Negative Supply
36V
36V
Positive Supply - Reference Supply
Input Voltage
Vee - 2.5V
Reference Voltage
Vee - 5.0V::::: VR:::::- VEE
-4.0V
Input Voltage + Reference Voltage
Input Voltage - Reference Voltage
6.0V
Positive Analog Voltage
Vee
Negative Analog Voltage
VEE
Analog Current
II A I<20mA
Power Dissipation INote 1)
Molded DIP ILF3650N)
570mW
Cavity DIP (LF1650D, LF2650D, LF3650D)
800mW
Operating Temperature Range
-55°C to +125°C
LF1650
-25° C to +85° C
LF2650
O°C to +70°C
LF3650
--u5°C to +150°C
Storage Temperature
300°C
Lead Temperature (Soldering, 10 secon'!s)
electrical characteristics
I+Vee
= 15V, -VEE = -15V, T A = 25°C, unless otherwise noted)
CONDITIONS
PARAMETER
ON Resistance I RON)
VA
MIN
= OV, 10 = 1.0 mA
TYP
MAX
n
150
Maximum Analog Swing IV AMAX) I Figure 1)
UNITS
V
V
+11
-12
Analog Current Loss II SION ) + 1010N»)
SWitch ON, Source and Drain Connect to +10V
0.3
nA
Source Current OFF IlsIOFF»)
SWitch OFF, Source at +10V, Drain at -10V
0.4
nA
Drain Current OFF (IOIOFF»)
SWitch OFF, Source at +10V, Drain at -10V
0.1
nA
Logic Input Bias Current II,NH)
V ,N at +5.0V
3.6
fJ.A
Delay Time ON ItoN) IFigures 3 and 4)
Source at -10V
500
ns
Delay Time OFF It OFF ) (Figures 3 and 4)
Source at +1 OV
90
ns
Source Capacitance ICSIOFF»)
SWitch OFF Source at -10V
4.0
pF
Drain Capacitance ICOIOFF»)
SWitch OFF Drain at -10V
3.0
pF
Active Source and Drain Capacitance
ICSION ) and COlON»)
SWitch ON Source and Drain at OV
5.0
pF
OFF Isolation
SWitch OFF, 1 0 MHz Signal on Source
IF,gure 5)
-50
dB
Crosstalk
One SWitch OFF Another SWitch ON with
1.0 Vrms @ 1.0 MHz at Source I Figure 5)
-65
dB
Positive Supply Current Ilcel
All SWitches OFF
5.0
mA
Negative Supply Current II EE )
All SWitches OFF
-3.0
mA
Reference Supply Current II R)
All Switches OFF
-2.0
V ,N LogiC "0"
V ,N LogiC "1"
Signal Path Slew Rate
rnA
0.8
V
V
2.0
50
V/fJ.s
Note 1: For operating at high temperatures the molded DIP products must be derated based on a +12So C maximum junction temperature and a
thermal resistance of + 17SoC/W, devices in the cavity DIP are based on a +150°C maximum junction temperature and are derated at +100°C/W.
8-28
r-
~
cr>
est circuits
U1
o
.....
r-
."
N
cr>
U1
o
.....
r-
30V
50%
."
!i0%
W
OV ......'+-----+>--~~
cr>
Vo
U1
o
10pF
"*
VD=+10V
FIGURE 4. tON. tOFF Test Circuit
IOV
L.....-j---....L-t-=t--
BOV
-8 OV ,.....~.-+--r---~~
lDVlms'
10MHz
-10V
t OVrms
10MHz
OFF ISOLATION
IVe:
CROSSTALK=ZQlog IVAI
IVe l
=
201011 -
IVe l
-Yo
FIGURE 5. OFF Isolation and Crosstalk
FIGURE 3. tON. tOFF. Test
ypical performance characteristics
ON Resistance vs Analog Voltage
ON Resistance vs Temperature
Break Before Make Action
500
400
]:
300
;::::
200
.
100
P, r-- _
'K
OUTPUT PULSE
......
r-
200
+Vcc -15V, -VEE '" -15V
TIME MEASURED FROM
50% INPUT PULSE TO 90%
,
11
160
I
V"""
120
r--toN
I
,
J
V
j.+Vcc '" 15V
-Vee = -15V
IA = 1.0mA
80
40
tOFF
120
-10
-60
-2.0
2.0
60
-10
10
VA (VOLTS)
On Resistance vs Analog
Current
s;
160
120
--
20
60
,/'"
,/
Vee = 15V
Vee'" -15V
r---
Vs '" 0
Switch Capacitances vs
Temperature
Analog Voltage
8.0
800
-
600
;:
400
§
w
u
z
-20
20
40
60
60
>=
+ COlON)
~r - - ' j
CS(ON)
;:;
40
~(OFF)
-50
r
50
100
150
-10
Vee
_
0
15V
Vee "'-15V
o
TEMPERATURE rCI
../
CDIOFFI
20
o
ANALOG CURRENT (mA)
150
10
]:
.
100
SWitching Times vs
200
40
-40
50
TEMPERATURE (OCI
1000
80
-60
-50
10
1200
V
r--
-20
VA (VOLTS)
240
200
-60
-6.0
-2.0
20
60
10
VA (VOLTSI
8·29
o
aD
CD
tYPical performance characteristics (con't)
('I)
u.
.....
o
Logic 1" Input'Bias
Current vs Temperature
Supply Current vs
Supply Current vs Supply
Voltage
.......
16
Temperature
10
10
10
8.0
-B.O
80
aD
CD
N
u.
.....
.......
o
aD
$!
U.
.....
C
..s
....
..'"'"
6.0
>
4.0
~
i
1
~
~>
NEGATIVE ll EE ) _
2.0
o
..
~
t
ill
Vs '" VEE + 5.0V
ALL SWITCHES OFF
o
5.0
10
C
4.0 t-~'!-<;;:-+-+--+=-l
2.0
6.0
i:l
40
t--t=''''''''''j--+=;;t;;;;:--i
~
\
...........
!!
2.0
REFERENCE II.)
15
20
25
O'-----'_---'-_-'-_..l..----l
o
-100
-100
-50
50
100
50
100
150
-50
TEMPERATURE 1°C)
Switch Leakage Currents
vs Temperature
-50
....
is
~
SUPPL V VOLTAGE (±V)
-100
\
-3
6.0
Vee = t5V
VEE'" -15V
VIN :: +5.0V
VR " OV
Supply Current
10
150
100
YS
10k
100
150
Crosstalk and OF F Isolation
vs Frequency Using Test
CirCUit of Figure 5
Toggle Rate
1.0k
50
I-
TEMPERATURE (OC)
lOOk
1.0M
10k
lOOk
1.0M
FREQUENCY 1Hz)
FREQUENCY 1Hz)
TEMPERATURE I'C)
-
Slew Rate of Analog Voltage
Leakage Currents vs
Analog Voltage
0.6
~
....
is
a:
..
Above Which Signal Loading
Occurs
.--,--:-:---:::-:-r--,---,
20
I
>
80
0.4
Vee'" 15V
VEE'" -15V
~
0.2
.."
~
w
~
:2'"
-0.2
h,L-f-.c_"'F--+=:':""'==-J
60
I""'""""'-
40
C
16
....
is
12
..s
'"C!
i:l
~
·See Note
100
.~
r- ..........
:::'"
"z
"
20
-2.0
2.0
VA (VOLTS)
6.0
10
-100
8.0
-50
50
100
150
TEMPERATURE 1°C)
-100
~A)
"
40
o
o
-60
'\
-50
50
..........
100
150
TEMPERATURE (OC)
*Note: The above graph indicates the analog current at which 1% of the analog current is lost.
When the drain of the analog switch IS positive with respect to the source the drain gate junction tends to forward bias and the output
FET becomes a PNP transistor with base and substrate current losses. Operation In this mode allows much higher analog currents while
maintaining a minimum RON.
8-30
s:
s:
Analog Switches
~
CTI
o
.......
MM450/MM550, MM451/MM551
MM452/MM552, MM455/MM555 MOS analog switches
s:
s:CTI
general description
•
The MM450, and MM550 series each contain
four p channel MOS enhancement mode transistors built on a single monolithic chip. The four
transistors are arranged as follows:
MM450, MM550
MM451, MM551
MM452, MM552
MM455, MM555
•
Large Analog Input Swing
V BU LK
Low Supply Voltage
CTI
o
± 10 Volts
= +10 Volts
VGG = ~20 Volts
•
Dual Differential
Switch
Four Channel
Switch
Four MOS Transistor Package
Three MOS Transistor Package
•
Low ON Resistance
VIN = -10V
150>2
+10V
75>2
200 pA@25°C
Low Leakage Current
•
I nput Gate Protection
•
Zero Offset Voltage
Each gate input is protected from static charge
build-up by the incorporation of zener diode protective devices connected between the gate input
and device bulk.
These devices are useful in many airborne and
ground support systems requiring multiplexing,
analog transmission, and numerous signal routing
applications. The use of low threshold transistors
(VTH = 2 volts) permits operations with large analog input swings (± 10 volts) at low gate voltages
(~20 volts). Significant features, then, include:'
The MM450, MM451, MM452 and MM455 are
specified for operation over the _55°C to +125°C
military temperature range. The MM550, MM551,
MM552 and MM555 are specified for operation
over the -25°C to + 70°C temperature range.
schematic and connection diagrams
Note 1 Pms 1 and 8 connected to case and deVice bulk Dlam and
Source may be mterchanged MM452F. MM552F
Note 2 MM452D and MM552D (dual-m-Ime packl;lgesl have same
pm connections as MM452F and MM552F shown above
Note Pm 5 connected to case and
device bulk. MM450, MM550
Order Number MM450H or MM550H
See Package 12
Order Number MM452F or MM552F
See Package 4
Order Number MM452D or MM552D
See Package 1
TOPVIEW
GATE!
BULK
Note Pm 5 connected to case and
Note Pm 5 connected to tase and
deVice bulk MM451, MM551
device bulk Drain and Source may
be tIlterchanged MM455, MM555
Order Number MM455H or MM555H
See Package 12
Order Number MM451H or MM551H
See Package 12
typical applications
EnUIVAlENl
fr
0-++--+....--11-+--+-1
TOGGLE
INPUT o--+-"-+---~.J
IL ______ _
SWITCH #1
OUTPUT
SWITCH:fb.
OUTPUT
DPDT Analog Switch
8-31
absolute maximum ratings
MM450, MM451, MM452, MM455
MM550, MM551, MM552, MM555
Gate Voltage IVGG)
Bulk Voltage IV BULK)
Analog Input IV IN )
+lOV to -30V
+10V
+10V to -20V
+10V to -30V
+10V
+10V to ··20V
Power Dissipation
Operating Temperature
Storage Temperature
200 mW
-SS·C to +12S·C
-6S·C to +150·C
200 mW
-2S·C to 70·C
-65·C to +150·C
electrical characteristics
STATIC CHARACTERISTICS (Note li
CONDITION
PARAMETER
MIN
TYP
V
V
150
600
n
200
n
VOG=O,lo=ltJA
ON Resistance
V IN = -10V
ON Resistance
V IN = Vss
75
V GS = -25V, VBS = 0, T A = 25°C
10 10
20
Input (Drami Leakage Current
MM450, MM451, MM452, MM455
UNITS
±10
3.0
Analog Input Voltage
Threshold Voltage (V GstT)i
OFF Resistance
Gate Leakage Current (I GSBi
MAX
1.0
2.2
n
pA
nA
.025
.002
.025
100
1.0
1.0
tJ A
tJA
T A =25°C
TA = 70°C
0.1
.030
100
1.0
nA
tJA
Output (Sourcei Leakage Current
MM450, MM451, MM452, MM455
TA = 25°C
.040
100
nA
Output (Sourcei Leakage Current
MM450
MM451
MM452, MM455
MM450, MM451, MM452, MM455
TA = 85°C
T;" = 85°C
T A =85°C
T A =125°C
1.0
1.0
1.0
1,0
tJA
tJA
tJA
tJA
Output (Sourcei Leakage Current
MM550
MM551
MM552, MM555
TA = 70°C
T A = 70°C
TA = 70°C
1.0
1.0
1,0
tJA
tJA
tJA
Input (Drami Leakage Current
MM550, MM551, MM552, MM555
T A =25°C
TA = 85°C
T A =125°C
DYNAMIC CHARACTERISTICS
Large Signal Transconductance
Vos = -10V, 10 = 10 mA
4000
f = 1 kHz
tJmhos
CAPACITANCE CHARACTERISTICS (Note 2i
DEVICE TYPE
PARAMETER
Analog Input (Draini Capacitance (CoBi
MIN
TYP
"ALL
MAX
UNITS
8
10
pF
Output (Sourcei Capacitance (CsBi
MM450,
MM451,
MM452,
MM455,
MM550
MM551
MM552
MM555
11
20
7.5
7.5
14
24
11
11
pF
pF
pF
pF
Gate Input Capacitance (CGBi
MM450,
MM451,
MM452,
MM455,
MM550
MM551
M,,IYI552
MM555
10
5.5
5.5
5.5
13
8
9
9
pF
pF
pF
pF
Gate to Output Capacitance (CGsi
ALL
3.0
5
pF
Note 1: The reSistance specifications apply for -55°C::::: TA::::: + 8SoC, VGG = -20V, VBULK =
+10V, and a test current of 1 rnA. Leakage current IS measured with all pins held at ground except
the Pin being measured which IS biased at -25V.
Note 2: All capacitance measurements are made at 0 volts bias at 1 MHz.
8·32
typical dynamic input characteristics
ITA = 25°C Unless Otherwise Notedl
CONDITION 1
ANALOG INPUT VOL lAGE
AT +10 VOLTS
Dynamic Ron
Ron vs VGG
Ves '" +lOV
1
LU
T
VON·
+10V
V
O U'
-8
+8
-22
-16
VGG (V)
CONDITION 2
ANALOG INPUT VOLTAGE
AT 0 VOLTS
Dynamic Ron
Vss+l0V
1
ovLUvou,
T
VON
o
-4
-8
-12
-16
-20
VGG (V)
CONDITION 3,
ANALOG INPUT VOLTAGE
AT -10 VOLTS
Dynamic Ron
=
~~~:~*~~~~~
VSB +10V
VON
-10V
i
LU
T
VSB
V IN
100.000
::
+10Y
10V
V
OU '
~::: =~:~ r-r
VOG "-20V-f--f------
r-r--
VGG
8
10 L..JLJ-l-l--'-'--'--'--'-..J
-1.0
-!J 6
-02
-+il.2
+06
+1.0
L--'--!..--'_l-..J...~_'--'
100
-17
-16
-19
-18
-20
/:; VIN (V)
VGG (V)
-50
I
1000
/.1/
V•• '5~E
Vu =1.5V';-VaB :: 10V
=
1 == -
1
J
100
E
F
r-
I Jl"
Vas =OV
V•• -25V
"I" I
I I I
10
0
-4
Drain Current vs
Gate To Source Voltage
Typical Drain Characteristics
Ron vsVGG
10.000
-8
-
VGG (V)
-16
~
a
."
-35
I" -13.5 b"'"
-30
,e:P!2
-25
.E
-15
~
-10
6
--45
-5
0
Va,
-20
~
6.0
H-+-+-++--+-+-f-I/I+-(
~
4.0 f-H-+-+-+-++/~-t----l
..
z
0
.....
.E
.....
2.0
H-+-+-++--+/--A--+--4---j
o ,..........-'-"'-~V..l-L....I-.J....J
0
-20
V., • OV -f-f-f-f-+-tJ"H
~
-!,-f-
-1~ f-
80
I-
~~~
-20
~,;-2~V+-+-+-+-+-~
Vss:: OV
.-GF-
--40
z
;;;:
I I
-12
_'VG~'~'5Ve :::;,L
-45
l-
10 , - , - , - . , - - , - , - , - , - . , - , - "
-40
-60
-80
-100
DRAIN TO SOURCE VOLTAGE - VOLTS
o
-1.0
-2.0
-3.0
-4 O·
-50
VGS - GATE TO SOURCE VOLTAGE - VOL TS
8-33
typical input capacitance characteristics
MM450. MM550
C,NVSV,N
MM451. MM551
CINvSV,N
Va. =+1.
= V.~' ~ZOV
~
.a
J
F V•• --1OV
10
VOG
='1
-10
-6
50
40
30
....
30
ZO
/:F= F=
=oy
VaG
~
J
+2
_ ~.G ~
+10
-10
-6
ZO
-1,OV I
V,N IVI
J
,I
V•• ' -Z[r
~
VaG'"' OV
10
VOG =-1
VOG "
VGG
=+lOV
."
-2
VIN
l- e--
V. a " +10V
60
4D
30
.!:
-
=+10Y
+6
V•• • +1OV
10
II I
-2
C,NVSV ,N
Vao =-2
zo
i'"
MM452. MM552. MM455. MM555
+2
+6
+10
-10
FF f - -
OV If- f-.,"l-
,
r··I"+IIOV
-6
+8
+10
IV)
typical applications (con't)
IMM451-------"l
,...-----,1
1
,...---+1
VIDEO
INPUT =1
VIDEO
VIDEO
OUTPUT #f
INPUTa2
:~~3++~~
L
II OUTPUT
INTELLIGENCE
I
I
_J
DPST High-Frequency Switch
4-Channel Multiplexer'
*Explnuon In thl number of dlta mput hnn IS pusSlbll by
uSing mulbpl. level senes SWItches allowmg the same decode
gdes to be used for all lower rank dacodlRg.
8-34
Analog Switches
MM454/MM554 four-channel commutator
general description
• All Channel Blanking input provided
• Reset capability provided
• Low ON Resistance
The fIiIM454/MM554 IS a four-channel analog commutator capable of switching four analog input
channels sequentially onto an output line. The
device is constructed on a single silicon chip using
MaS P Channel enhancement transistors; it contains all the digital cirCUitry necessary to sequentially turn ON the four analog switch transistors
permitting multiplexing of the analog input data.
The device features:
In addition, the MM454/MM554 can easily be
applied where submultiplexing is required since a
4: 1 clock countdown signal is provided which can
drive the clock input of subsequent MM454/MM554
units.
±10V
500 kHz
200pA
50nA
The MM454 is specified for operation over the
-55°C to +125°C military temperature range. The
MM554 is specified for operation over the -25°C
to +70°C temperature range.
• High Analog Voltage Handling
• High Commutating Rate
• Low Leakage Current (T A = 25° C)
(T A = 85°C)
200n
schematic and connection diagrams
ANALOG
INPUTS
4
'ANALOG
OUTPUT
CLOCK
INPUT
OUTPUT
41
COUNTDOWN
-------.....J
RESET---....
"
"
NOCONIIIEeno ..
v••
IZ
CLOCKI.PUl
v••
OU11'UT41COUfilTDOWN
NO 1 Ali/lUG IIiIPUT
RESET
NO ZA,.ALOGIIiI'UT
ALL CHAIINELILANKING
NO 3ANALOIIINPUT
NOCOIIN£CTlOIil
NO 4ANALD61NPUT
ANALOBOUTPUT
V"
Note: Pin 1 connected to elSe and to deVIce bulk. Noflll\al Operabng VoltagBI
VOG =-24Y. VDD -OV;Vss s+12V,RESET BIAS=+12V (DVfor RESET)
ALL CHANNEL BLANKING BIAS" +12V (QV for BLANKING)
Order Number MM454F or MM654F
Se. Package 4
8-35
absolute maximum ratings
(Note 11
+lOV to -30V
+10V
+10V to -20V
200mW
_55°C to +125°C
_25°C to +70°C
_65°C to +150°C
Gate Voltage (V GG 1
Bulk Voltage (V ss 1
Analog Input (V IN 1
Power Dissipation
Operating Temperature MM454
MM554
Storage Temperature
static characteristics
(Note 2)
CONDITION
PARAMETER
Analog Input Voltage
ON ReSistance
ON ReSIStance
OFF Resistance
Analog Input Leakage Current
V'N
MIN
= -10V
TYP
170
90
V'N = Vss
MAX
± 10
600
200
T A = 25°C
T A = 85°C
TA = 25°C
T A = lO°C
T A = 25°C
T A = 85°C
T A = 25°C
T A = lO°C
Vss = +12V
VGG = -24V
V
12
12
12
10 10
MM454
MM454
MM554
MM554
Analog Output Leakage Current MM454
MM454
MM554
MM554
V 55 Supply Current Drdln
V GG Supply Current Drain
UNITS
5.5
3.5
nA
/1A
nA
/1A
nA
/1A
nA
/1A
mA
mA
TYP
MAX
UNIT
050
006
0001
.030
0100
30
000.1
.030
100
1.0
100
1.0
100
1.0
100
1.0
3.8
2.4
capacitance characteristics
PARAMETER
CONDITION
Analog Input Capacitance Channel OFF
liN
Analog Input Capacitance Channel ON
liN
MIN
=a
=0
4
6
pF
20
24
pF
20
24
pF
Analog Output Capacitance
liN = 0
Clock Input
V cL =+12V
2.0
pF
Reset Input
VAESET
=
+12V
20
pF
Blanking Input
VBLANK
=
+12V
20
pF
clock characteristics
(Note 3)
PARAMETER
CONDITION
Clock Input (HIGH)(')
Clock Input (LOW)
MIN
TYP
Vss - 2
-5
Clock Input Rise Time (POS GOING)
MAX
UNIT
Vss
V
+5
V
20
~sec
0
No requirement
Clock Input Fall Time (NEG GOING)
Countdown Output (POS) V OH
Vss -2
Countdown Output (NEG) VOL
Maximum Commutation Rate
Vss
Vss
0
05
+100
V
MHz
2.0
+12
+14
Note 1: Maximum ratings are limiting values above which the device may be damaged. All voltages
referenced to VOO "" O.
Note 2: These speCifications apply over the Indicated o~eratmg temperature range for V GG = -24V,
VDD = av. VSS = +12V, VRESET = +12V, V8LANK = +12V ON reSIStance measured at 1 mA,
OFF resistance and leakage measured With all analog Inputs and output common Capacitance measured
at 1 MHz.
Note 3: Operating conditions In Note 2 apply. VSS to VOO (OV) voltage IS applied to counting and
gating Circuits VGG IS required only for analog SWitch biasing' All logic Inputs are high resistance and
are essentially capaCitive.
Note 4: LogiC Input voltage must not be more positive than VSS.
8·36
V
V
typical performance characteristics
RON vs Analog Voltage
260
~
u
~
220
'"
~I"O
vss "+12V
L)
=";;
u 0
..i'" "
140
;
30
26
26
24
22
20
18
16
14
12
10
Voo = OV
VBULK :: +12V
vGG = -24V
-
z
c
100
~
~l
TA =+85 C
l"
~ ~
....TA~I'25 r-IC
~
= -55
C
I""- r-.
i"'-r-.
-10 -8 -6 -4 -2
CHANNEl "OFF;;;;'
4
2
r-
60
CHANNEL "ON"
I
6
i"'-
i""\...J""-o
T.
1
I
-
o
-10 -8 -6 -4
0 +2 +4 +& +8 +10
v," ANALOG INPUT VOLTAGE (VI
13
~
.,
12
~
,:
11
10
'9
L.(
V
10
'9
V
~
-2
0 +2 +4 +6 +8 +10
V," ANALOG INPUT VOLTAGE IVI
Plus V,N (max) ys VBULK
14
~
Minus V,N (max) ys VGG
v
-30
-28
-24
.
~
~
t- T.=+85C
-20
La
ftl'!
-16
.b.
IrL I!:=
I!Z
-12
TA "+25CTA~-55
C-
I!Z
I!!Ii
-8
-4
o
11
12
13
14
V," MAXIMUM POSITIVE GOING
ANALOG EXCURSION IV)
o
-2 -4 -6 -8 -10 -12-14 -16 -18 -20
V," MAXIMUM NEGATIVE
ANALOG EXCURSION IR o " ~ 1 Kl"!) IVI
timing diagram
CLOCK 0
IN 1
CHI
CH2
CH3
n"___...In"___...In..___
O~:--II,--_ _.......
ON
OFF
n,--__~n..___...n ..___....rt..
O~: _ _ _......
OFF _ _ _ _ _ _..I
~~
n
r
OUTPUT
"0"
COUNTDOWN "I"
NOTE "0" LEVEL =+llV
"1"LEVEl
=
OV IGNOI
8-37
New Products
DM7833/DM 8833, DM7834/DM8834, DM7835/DM8835,
DM7839/DM8839 quad TRI-STATE® transceivers
general description
This family of TRI·STATE® party line trans·
ceivers offer extreme versatility in bus organized
data transm ission systems. The data bus may be
unterminated, or terminated DC or AC at one or
both ends. Drivers in the third (high impedance)
state load the data bus with a negligible leakage
current. The receiver input current is low allowing
at least 100 driver/receiver pairs to utilize a single
bus. The bus loading is unchanged when Vee = OV.
The receiver incorporates hysteresis to provide
greater noise immunity. All devices utilize a high
current TRI·STATE output driver. The DM7833/
DM8833 and DM7835/DM8835 employ TR1·
STATE outputs on the receiver also, while on
the DM7834/DM8834 and DM7839/DM8839 the
receiver outputs are standard active pu II up T2 L.
The DM7833/DM8833 are non-inverting quad
transceivers With a common drtver disable can·
trol and a common receiver disable control.
The DM7839/DM8839 are non· inverting quad
transceivers with a common two-input driver
disable control.
The DM7834/DM8834 are inverting Quad trans·
ceivers with. a common two input driver disable
control.
The DM7835/DM8835 are inverting quad transceivers with a common driver disable control
and a common receiver disable control.
features
•
•
•
•
•
450 mV (typ)
Receiver hysteresIs
lAV (typ)
Receiver noise immunity
50/iA (max)
Receiver Input current
for norma I Vee or
Vee = OV
Receivers
Sink
16 mA at 0.4V (max)
Source
2.0 mA (mil)
2 4V ( .)
5.2 mA (com) at.
min
Drivers
Sink
50 rnA at 0.5V (max) or
32 rnA at 0.4V (max)
lOA mA at
2AV (min)
Source
•
•
•
Drivers have TRI-STATE outputs
DM78331DM8833 and DM7835/DM8835 reo
celvers have TRI·STATE outputs
Capable of driving lOOn DC terminated buses
•
74 series TTL compatible
connection diagrams
TOP VIEW
DM7833/DM8833
TOP VIEW
DM7835/DM8835
TOP VIEW
DM7834/DM8834
TOP VIEW
DM?839/DM8839
9·1
New Products
LM165/LM365. LM166/LM366. LM167/LM367.
LM168/LM368 MOS sense amplifiers (MOS to TTL converters)
general description
This is a new series of hex sense amplifiers. The LM 165/
LM365 and LM166/LM366 have TRI·STATE outputs.
The LM167/LM367 and LM168/LM363 have both
TRI·STATE inputs and outputs. High impedance states
are controlled by an enable input.
unconnected. It can be set from 100llA to 350llA by
connecting a resistor from the pin to ground, and set
,above 350llA by connecting a resistor from the pin to
the positive supply.
The outputs are high current drivers capable of sinking
50 mA in the low state and sourcing 5.0 mA in the
high state. The circuits feature high speed direct MOS
sense capability with high impedance states to allow
use of a common bus line.
The current threshold, at which the outputs change
state is determined by the current at the programming
pin. The current threshold is i OOIlA with the programming pin grounded and 350llA with the pin
connection diagram
Dual-In-Line Package
INPUT
14
2
INPUT
,
OUTPUT
OUTPUT
INPUT
"
12
4
INPUT
OUTPUT
11
INPUT
OUTPUT
10
5
OUTPUT
TOPVIEW
truth tables
LM165/LM365
LM166/LM366
liN
DIS
OUT
liN
DIS
OUT
X
H
Hi-z
X
H
Hi-z
>1,
L
L
H
L
>1,
L
1,
L
>1,
L
H
v'
--0 v-
FREQUENCY CONTROL
PULSE WIDTH CONTROL
--<> INHIBIT
--0 TEST
0--------.. .
r--'--Ovcc
.,
DAMPED MOS OUTPUTS
TTL OUTPUTS
10n
L - -....--oCNO
DIRECT MOS OUTPUTS
connection diagram
INHIBIT
v'
TEST
FREQ CONTROL
.9-8
zCD
~
New Products
...
"0
oQ.
C
(")
MH8804 quad MOS memory driver
MH8805 dual MOS memory driver
general description
1"+
1/1
features
The quad MH8804 and the dual MH8805 are
bipolar to MOS drivers specifically designed to
drive input address lines for MOS memory arrays
using MM1103 type RAMs. The MH8804 IS pin
compatible with the 13207 and the MH8805 with
the SN75361.
•
Current mode output drive
•
Rise and fall times
•
Delay times
•
High output voltage
±500 mA
20 ns
15 ns
•
Low output voltage
•
Input levels
Vss - 1.0V
0.3V
TTLlDTL
connection diagrams
16
v~
v"
15
0,
0,
0,
v"
14
0,
0,
13
E,
11
E,
11
0,
0,
E,
E,
0,
0,
0,
ID
0,
0,
GNO
GNO
v~
VM
TOPVIEW
TOP VIEW
MH8804
MH8805
g.g
~
I
Applications
N
N
...5"
~...
...
III
INTEGRATED CIRCUITS FOR
DIGITAL DATA TRANSMISSION
!.
n
n
c
;~:
(II
....
o...
o
cS'
INTRODUCTION
;:;:
III
c
It is frequently necessary to transmit digital data
in a high-noise environment where ordinary integrated logic circuits cannot be used because they
do not have sufficient noise immunity. One solu·
tion to this problem, of course, is to use highnoise·immunity logic. In many cases, this approach
would require worst case logic swings of 30V,
requiring high power-supply voltages. Further,
considerable power would be needed to transmit
these voltage levels at high speed. This is especially
true if the lines must be terminated to eliminate
reflections, since practical transmission lines have a
low characteristic impedance.
A much better solution is to convert the ground
referred digital data at the transmission end into a
differential signal and transmit this down a balanced, twisted-pair line. At the receiving end, any
induced noise, or voltage due to ground-loop currents, appears equally on both ends of the
twisted-pair line. Hence, a receiver which responds
only to the differential signal from the line will
reject the undesired signals even with moderate
voltage swings from the transmitter.
Figure 1 illustrates this situation more clearly.
When ground is used as a signal return as in Figure la, the voltage seen at the receiving end will be
the output voltage of the transmitter plus any
noise voltage induced in the signal line. Hence, the
noise immunity of the transmitter-receiver combination must be equal to the maximum expected
noise from both sources.
The differential transmission scheme diagrammed
in Figure 1b solves this problem. Any ground noise
or voltage induced on the transmission lines will
appear equally on both inputs of the receiver. The
receiver responds only to the differential signal
coming out of the twisted-pair line and delivers a
single·ended output signal referred to the ground
DATA
INPUT
!l.
III
DATA
OUTPUT
...
-t
III
:;:,
(II
3
iii'
(II
0'
GAOUND 8
GI'OUND A
a Smgle-Ended System
:;:,
INDUCED
NOISE
DATA
INPUT
DATA
OUTPUT
GROUND A
GROUND B
b Differential System
FIGURE 1. Comparing Differential
Data Transmission
and Single-Ended
at the receiving end. Therefore, extremely high
noise immunities are not needed; and the transmitter and receiver can be operated from the same
supplies as standard integrated logic circuits.
This article describes the operation and use of a
line driver and line receiver for transmission systems using twisted-pair lines. The transmitter provides a buffered differential output from a DTL or
TTL input signal. A four-input gate is included on
the input SO that the circuit can also perform logic.
The receiver detects a zero crossing in the differ·
ential input voltage and can directly drive DTL or
TTL integrated circuits at the receiving end. It also
has strobe capability to blank out unwanted input
signals. Both the transmitter and the receiver incorporate two independent units on a single silicon
chip.
10·1
c
.2
(II
(II
E
(II
c
~
l-
S
LINE DRIVER
CO
Q
16
;t::
Figure 2 shows a schematic diagram of the line
transmitter. The circuit has a marked resemblance
to a standard TTL buffer. In fact, it is possible to
use a standard dual buffer as a transmitter. However, the DM7830 incorporates additional features.
For one, the output is current limited to protect
the driver from accidental shorts in the transmission lines. Secondly, diodes on the output clamp
severe voltage transients that may be induced into
the transmission lines. Finally, the circuit has
internal inversion to produce a differential output
signal, reducing the skew between the outputs and
making the output state independent of loading.
.!2I
.
...
.
U
Q
....o
(II
·S
(J
"C
S
~
...
C)
CD
- ..........-,.
,-....;.--...........
C
N
N
I
Z
c:(
NAND
OUTPUT
,......--.-...........- ..........-,.
...
OUTPUT
FIGURE 2. Schematic Diagram of the DM7830 Line
Driver
As can be seen from the upper half of Figure 2, a
quadruple-emitter input transistor, Q9, provides
four logic inputs to the transmitter. This transistor
drives the inverter stage formed by Ql0 and Ql1
10-2
to give a NAND output. A low state logic input on
any of the emitters of Q9 will cause the base drive
to be removed from Ql0, since Q9 will be
saturated by current from R8, holding the base of
Ql0 near ground. Hence, Ql0 and Qll will be
turned off; and the output will be in a high state .
When all the emitters of Q9 are at a one logic level,
Ql0 receives base drive from R8 through the forward biased collector-base junction of Q9. This
saturates Ql0 and also Qll, giving a low output
state. The input voltage at which the transition
occurs is equal to the sum of the emitter-base turn
on voltages of Ql0 and Qll minus the saturation
voltage of Q9. This is about l.4V at 25°C.
A standard "totem-pole" arrangement is used on
the output stage. When the output is switched to
the high state, with Ql0 and Qll cut off, current
is supplied to the load by Q13 and Q14 which are
connected in a modified Darlington configuration.
Because of the high compound current gain of
these transistors, the output resistance is quite low
and a large load current can be supplied. Rl0 is
included across the emitter-base junction of Q13
both to drain 'off any collector-base leakage current in Q13 and to discharge the collector-base
capacitance of Q13 when the output is switched to
the low state. In the high state, the output level is
approximately two diode drops below the positive
supply, or roughly 3.6V at 25°C with a 5.0V
supply.
With the output switched into the low state, Q 10
saturates, holding the base of Q14 about one diode
drop above ground. This cuts off Q13. Further,
both the base current and the collector current of
Ql0 are driven into the base of Qll saturating it
and giving a low-state output of about O.lV. The
circuit is designed so that the base of Q 11 is
supplied 6 mA, so the collector can drive considerable load current before it is pulled out of
saturation.
The primary purpose of R 12 is to provide current
to remove the stored charge in Q 11 and charge its
collector-base capacitance when the ·circuit is
switched to the high state. Its value is also made
enough less than R9 to prevent supply current
transients which might otherwise occur' when the
power supply is coming up to voltage.
*J.
Kalb,
"Design Considerations for
"National Semiconductor TP-6, May. 1968.
a TTL Gate,
The lower half of the transmitter in Figure 2 is
identical to the upper, except that an inverter
stage has been added. This is needed so that an
input signal which drives the output of the upper
half positive will drive the lower half negative, and
vice versa, produci~g a differential output signal.
Transistors 02 and 03 produce the inversion. Even
though the current gain is not necessarily needed,
the modified Darlington connection is used to produce the proper logic transition voltage on the
input of the transmitter. Because of the low load
capacitance that the inverter sees when it is completely within the integrated circuit, it is extreme,
Iy fast, with a typical delay of 3 ns. This minimizes
the skew between the outputs.
One of the schemes used when dual buffers are
employed as a differential line driver is to obtain
the NAN D output in the normal fashion and provide the AND output by connecting the input of
the second buffer to the NAN D output. Using an
internal inverter has some distinct advantages over
this: for one, capacitive loads which slow down
the response of the NAND output will not introduce a time skew between the two outputs;
secondly, line transients on the NAND o~tPut will
not cause an unwanted change of state on the
AND output.
Clamp diodes, D 1 through D4, are added on all
inputs to clamp undershoot. This undershoot and
ringing can occur in TTL systems because the rise
and fall times are extremely short.
Output-current limiting is provided by adding a
resistor and transistor to each of the complementary outputs. Referring again to Figure 2, when
the current on the NAND output increases to a
value where the voltage drop across R11 is sufficient to turn on 012, the short circuit protection
comes into effect. This happens because further
increases in output current flow into the base of
012 causing it to remove base drive from 014 and,
therefore, 013. Any substantial increase in output
current will then cause the output voltage to collapse to zero. Since the magnitude of the short
circuit depends on the emitter base turn-on voltage
of 012, this current has a negative temperature
coefficient. As the chip temperature increases
from power dissipation, the available short circuit
current is reduced. The current limiting also serves
to control the current transient that occurs when
the output is going through a transition with both
011 and 013 turned on.
The AN D output is similarly protected by R6 and
05, which limit the maximum output current to
about 100 mA, preventing damage to the circuit
from shorts between the outputs and ground.
The current limiting transistors also serve to increase the low state output current capability
under severe transient conditions. For example,
when the current into the NAN D output becomes
so high as to pull 011 out of saturation, the output voltage will rise to two diode drops above
ground. At this voltage, the collector-base junction
of 012 becomes forward biased and supplies additional base drive to 011 through 010 which is
saturated. This minimizes any further increase in
output voltage.
When either of the outputs are. in the high state,
they can drive a large current towards ground
without a significant change in output voltage.
However, noise induced on the transmission line
which tries to drive the output positive will cut it
off since it cannot sink current in this state. For
this reason, D6 and D8 are included to clamp the
output and keep it from being driven much above
the supply voltage, as this could damage the
circuit.
When the output is in a low state, it can sink a lot
of current to clamp positive-going induced voltages
on the transmission line. However, it cannot
source enough current to eliminate negative-going
transients so D5 and D7 are included to clamp
those voltages to ground.
It is interesting to note that the voltage swing
produced on one of the outputs when the clamp
diodes go into conduction actually increases the
diffferential noise immunity. For example with
no induced common mode current, the low-state
output will be a saturation voltage above ground
while the high output will be two diode drops
below the positive supply voltage. With positivegoing common mode noise on the line, the low
output remains in saturation; and the high output
is clamped at a diode drop above the positive
supply. Hence, in this case, the common mode
noise increases the differential swing by three
diode drops.
10-3
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25
50
15
100
125
150
OUTPUT SOURCE CURRENT (mAl
FIGURE 3. High State Output Voltage as a Function of
Output Current
Having explained the operation of the line driver,
it is appropriate to look at the performance in
more detail. Figure 3 shows the high-state output
characteristics under load. Over the normal range
of output currents, the output resistance is about
lOn. With higher output currents, the short circuit
protection is activated, causing the output voltage
to drop to zero. As can be seen from the figure,
the short-circuit current decreases at higher
temperatures to minimize the possibility of overheating the integrated circuit.
v+ =5V
~
'"~
-S5!C
.. "
2
~
1
>
"
Y
T
125
150
OUTPUT SINK CURRENT (mAl
FIGURE 4. Low-State Output Current as a Function of
Output Current
Figure 4 is a similar graph of the low-state output
characteristics. Here, the output resistance is about
5n with normal values of output current. With
larger currents, the output transistor is pulled out
of saturation; and the output voltage increases.
This is most pronounced at _55°C where the transistor current gain is the lowest. However, when
the output voltage rises about two diode drops
above ground, the collector-base junction of the
current-limit transistor becomes forward biased,
10-4
LRL 0 son
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,
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2S"C
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moc
15
100
12S
lS0
OUTPUT CURRENT (mAl
.1
100
V+"'5V
~~'100~
25
~2S0Cso, 15
~RL0200n ,~
~
1.
....... 1"
2S
The curves in Figures 3 and 4 demonstrate the
performance of the line driver with large, capacitively-coupled common-mode transients, or under
IJIL
25°C
00
It is clear from the figure that the low state output
current is not effectively limited. Therefore, the
device can be damaged by shorts between the output and the 5V supply. However, protection
against shorts between outputs or from the outputs to ground is provided by limiting the highstate current.
tIL
I
II
~
providing additional base drive for the output transistor_ This roughly doubles the current available
for clamping positive common-mode transients on
the twisted-pair line_ It is interesting to note that
even though the output level increases to about
2V under this cdndition, the differential noise
immunity does not suffer" because the 'high-state
output also increases by about 3V with positive
going common-mode transients.
FIGURE 5. Differential Output Voltage as a Function of
Differential Output Current
gross overload conditions. Figure 5 shows the
ability of the circllit to drive a differential load:
that is, the transmission line_ It can be seen that
for output currents less than 35 mA, the output
resistance is approximately l5n_ At both temperature extremes, the output falls off at high currents,
At high temperatures, this is caused by current
limiting of the high output state_ At low temperatures, the falloff of current gain in the lowstate output transistor produces this result_
Load lines have been included on the figure to
show the differential output with various load
resistances, The output swing'can be read off from
the intersection of the output characteristic with
the load line, The figure shows that the driver can
easily handle load resistances greater than lOOn.
»
z
I
N
N
S'
This is more than adequate for practical, twistedpair lines.
Figure 6 shows the no load power dissipation, for
one-half of the dual line driver, as a function of
frequency. This information is important for two
reasons. First, the increase in power dissipation at
high frequencies must be added to the excess
power dissipation caused by the load to determi ne
the total package dissipation. Second, and more'
important, it is a measure of the "glitch" current
which flows from the positive supply to ground
through the output transistors when the circuit is
going through a transition. If the output stage is
II !
125
30
~
100
to:
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C
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-15 -50 -25
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15 100 125
TEMPERATURE (OC)
cO'
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FIGURE 7. 'Propagation Time as a Function of Temperature
r-
WJ,,-
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r-
ONE SIDE
{=[5111-
25
0,1
10
...
III
V
~
~
f
~
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C
150
.s
i;
25
10
100
SWITCHING FREQUENCY (MHz)
FIGURE 6. Power Dissipation as a Function of Switching
Frequency
not properly designed, the current spikes in the
power supplies can become quite large; and the
power dissipation can increase by as much as a
factor of five between 100 KHz and 10 MHz. The
figure shows that, with no capacitive loading, the
power increase with frequencies as high as 10 MHz
is almost negligible. However, with large capacitive
loads, more power is required.
The line receiver is designed to detect a zero crossing in the differential output of the line driver.
Therefore, the propagation time of the driver is
measured as the time difference between the application of a step input and the point where the
differential output voltage crosses zero. A plot of
the propagation time over temperature is shown in
Figure 7. This delay is added directly to the propagation time of the transmission line and the delay
of the line receiver to determine the total datapropagation time. However, in most cases, the
delay of the driver is small, even by comparison to
the uncertainties in the other delays.
III
.
-4
To summarize the characteristics of the DM7830
line driver, the input interfaces directly with standard DTL or TTL circuits. It presents a load which
is equivalent to a fan oyt of 3 to the circuit drivingit, and it operates from the 5.0V, ±10% logic
supplies. The output can drive low impedance lines
down to 50Q and capacitive loads up to 5000 pF.
The time skew between the outputs is minimized
to reduce radiation from the twisted-pair lines, and
the circuit is designed to clamp common mode
transients coupled into the line. Short circuit protection is also provided. The integrated circuit consists of two independent drivers fabricated on a
41 x 53 mil-square die using the standard TTL
process. A photomicrograph of the chip is shown
in Figure 8.
III
::::I
III
3
iii'
0'
III
::::I
FIGIJRE 8. Photomicrograph of the DM7830 Dual Line
Driver
10·5
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....
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LINE RECEIVER
C'D
Q
~CI
is
-v·
r----=
~
0:
~
v+ J5.0J
OUTPUT LOW
ONE SIDE
~\
I '~
100
f
I~
1-
II
~
o
-20
-
-10
25)f.
"125°C
~ ~ ~'I
10
T
20
The variation of the internal termination resistance
with temperature is illustrated in Figure lS.Taking
into account the initial tolerance as well as the
change with temperature, the termination resis·
tance is by no means precise. Fortunately, in most
cases, the term ination resistance can vary
appreciably without greatly affecting the charac'
teristics of the transmission line. If the resistor
tolerance is a problem, however, an external resis·
tor can be used in place of the one provided within
the integrated circuit.
INPUT VOLTAGE IV)
FIGU'RE 16. Internal Power Dissipation as a Function of
Common Mode Input Voltage
200
190
g
.....
180
!1i
170
z
or
Figure 17 shows that the power supply current
also changes with common mode input voltage due
to the current drawn out of or fed into the supply
through R9. The supply current reaches a
maximum with negative input voltages and can
actually reverse with large positive input voltages.
The figure also shows that the supply current with
the output switched into the low state is about
3 mA higher than with a high output.
10·10
tl
0:
160
,
/
--
150
-15 -50 -25
-
~
0
25
50
15 100 125
TEMPERATURE 1°C)
FIGURE 18. Variation of Termination Resistance With
Temperature
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DATA TRANSMISSION
;:;:
en.
....
10
The interconnection of the DM7830 line driver
with the DM7820 line receiver is shown in Figure 19. With the exception of the transmission
line, the design is rather straightforward. Connections on the input of the driver and the output or
strobe of the receiver follow standard design rules
for DTL or TTL integrated logic circuits. The load
presented by the driver inputs is equal to 3 standard digital loads, while the receiver can drive a
worst-case fanout of 2. The load presented by the
receiver strobe is equal to one standard load.
...o
UNTERMINATED
n..
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=
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300n
~
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t§:
...
15Dn
7m
2!..
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...
I(
II)
II)
-10
...
-I
II)
TIME (jls)
The purpose of Cl on the receiver is to provide dc
isolation of the termination resistor for the transmission line. This capacitor can both increase the
differential noise immunity, by reducing attenuation on the line, and reduce power dissipation in
both the transmitter and receiver. In some applications, C 1 can be replaced with a short between
Pins 1 and 2, which connects the internal termination resistor of the DM7820 directly across the
line. C2 may be included, if necessary, to control
the response time of the receiver, making it
immune to noise spikes that may be coupled differentially into the transmission lines.
:::I
FIGURE 20. Transmission Line Response With Various
Termination Resistances
en
The effect of termination mismatches on the transmission line is shown in Figure 20. The line was
constructed of a twisted pair of No. 22 copper
conductors with a characteristic impedance of
approximately 170n. The line length was about
150 ns and it was driven directly from a DM7830
line driver. The data shows that termination resistances which are a factor of two off the nominal
value do not cause significant reflections on the
line. The lower termination resistors do, however,
increase the attenuation.
en
en
CIt
0OO2~f
OUTPUT
t hact value depends on Imelength
+v+ IS 4 5V to 5 5V for both the DM7820 and DM7830
*OptlOnal to control response time
STROBE
FIGURE 19. Interconnection of the Line Driver and Line
Receiver
10-11
3
O·
:::I
The effect of different values of dc isolation
capacitors is illustrated in Figure 22. This shows
that the RC time constant of the termination resis·
tor/isolation capacitor combination should be 2 to
3 times the line delay. As before, this data was
taken for a 150 ns long line.
Figure 21 gives the line-transmission characteristics
with various termination resistances when a dc
isolation capacitor is used. The line is identical to
that used in the previous example. It can be seen
that the transient response is nearly the same as a
dc terminated line. The attenuation, on the other
hand, is considerably lower, being the same as an
unterminated line. An added advantage of using
the isolation capacitor is that the dc signal current
is blocked from the termination resistor which
reduces the average power drain of the driver and
the power dissipation in both the driver and
receiver.
10
15Dn+ZOO pF
./
ft.oo
IE ~
a
..
'"or
~
0
S
3I1On+211011 pF
11
...... 150n+4000 pF
>
0
or
10
15Dn+ll00pF
-!
-
PI
1'1
v
. / lson+ZOOOpF
a
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lli:fiI"O
or
~
0
>
0
or
S
-10
...... 75n+ZOOOpF
-5
-
TIME (psi
FIGURE 22. Response of Terminated Line With Different DC Isolation Capacitors
~::::
In Figure 23, the influence of a varying ground
voltage between the transmitter and the receiver is
shown. The difference in the characteristics arises
because the source resistance of the driver is not
constant under all conditions. The high Oljtput of
-10
TIME (...1
FIGURE 21. Line Response for Various Termination
Resistances With a DC Isolation Capacitor
10
10
10
VcM --15V
VCM""OV
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a
1,J,lf'\
co
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-5
-10
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2
4
TIME(",)
a. VCM=OV
"-
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I-5
U"
...,
lson
or
S
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lVi'lI"~
!-
-10
-1 0
TIME
I I
lson +ZGOO pF
0
lit.)
b. VCM--15V
FIGURE 23. Line Response With Different Terminations
and Common Mode Input Voltages
10·12
~UNTERMINATED
~~
0
lson
.L J ..l. J.YCM1--1--IIY
r-ra:;
a
\ ' IlIOn +2000 pF
150n
>
UNTERMINATED
1M
lson+2000 pF
0
~
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UNTERMINATED
4
TIME 1#<1)
c. VCM= 15V
»
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I
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N
the transmitter looks like an open circuit to voltages reflected from the receiving end of the transmission line which try to drive it higher than its
normal dc state_ This cQndition exists until the
voltage at the transmitting end becomes high
enough to forward bias the clamp diode on the 5V
supply. Much of the phenomena which does not
follow simple transmission-line theory is caused by
this. For example, with an unterminated line, the
overshoot comes from the reflected signal charging
the line capacitance to where the clamp diodes are
forward biased. The overshoot then decays at a
rate determined by the total line capacitance and
the input resistance of the receiver.
When the ground on the receiver is 15V more
negative than the ground at the transmitting end,
the decay with an unterminated line is faster, as
shown in Figure 23b. This occurs because there is
more current from the input resistor of the
receiver to discharge the line capacitance. With a
terminated line, however, the transmission characteristics are the same as for equal ground voltages because the terminating resistor keeps the line
from getting charged.
Figure 23c gives the transmission characteristics
when the receiver ground is 15V more positive
than the transmitter ground. When the line is not
terminated, the differential voltage swing is increased, because the high output of the driver will
be pulled against the clamp diodes by the common
mode input current of the receiver. With a dc isolation capacitOT, the differential swing will reach this
same value with a time constant determined by the
isolation capacitor and the input resistance cif the
receiver. With a dc coupled termination, the characteristics are unchanged because the differential
load current is large by comparison to the common mode current so that the output transistors
of the driver are always conducting.
The low output of the driver can also be pulled
below ground to where the lower clamp diode con-
ducts, giVing effects which are similar to those
described for the high output. However, a current
of about g rnA is required to do this, so it does not
happen under normal operating conditions.
To summarize, the best termination is an RC combinat~on with a time constant approximately equal
to 3 times the transmission-line delay. Even
though its value is not precisely determined, the
internal termination resistor of the integrated circuit can be used because the line characteristics are
not greatly affected by the termination resistor.
The only place that an RC termination can cause
problems is when the data transmission rate
approaches the line delay and the attenuation
down the line (terminated) is greater than 3 dB.
This would correspond to more than 1000 ft. of
twisted-pair cable with No. 22 copper conductors.
Under these conditions, the noise margin can disappear with low-duty-cycle signals. If this is the
case, it is best to operate the twisted-pair line without a termination to minimize transmission losses.
Reflections should not be a problem as they will
be absorbed by the line losses.
CONCLUSION
A method of transmitting digital information in
high-noise environments has been described. The
technique is a much more attractive solution than
high-noise-immunity logic as it has lower power
consumption, provides more noise rejection, operates from standard 5V supplies, and is fully compatible with almost all integrated logic circuits. An
additional advantage is that the circuits can be
fabricated with integrated circuit processes used
for standard logic circuits.
10-13
c
.2
II)
II)
E
~
~
I-
APPENDIX A
LINE RECEIVER
Design Analysis
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i....
CO
~
Cl
....
Q)
The purpose of this appendix is to derive mathematical expressions describing the operation of the
line receiver. It will be shown that the performance of the circuit is not greatly affected by the
absolute value of the components within the integrated circuit or by the supply voltage. Instead, it
depends mostly on how well the various parts
match.
, where V IN is the common mode input voltage and
R.IIR b denotes the parallel connection of the two
resistors. In Equation (A. 1), RS = R9, R3 = R 10,
Rl0« Rll, R9» Rl0, R3« Rll, RS»R3
and
R3
«3 so it can be reduced to
R4 +2R6 + R3
+
V+ - 3V BE - Rl0
R9 V
(A. 2)
IC1=
Rl0+Rll+R3
which shows that the collector current of 01 is
not affected by the common mode voltage.
The analysis wi" assume that all the resistors are
well matched in ratio and that the transistors are
likewise matched, since this is easily accomplished
over a broad temperature range with monolithic
construction. However, the effects of component
mismatching will be discussed where important .
Further, large transistor current gains will be
assumed, but it will be pointed out later that this
is valid for current gains greater than about 10 .
The output voltage on the collector of 02 is
A schematic diagram of the DM7S20 line receiver
is shown in Figure A-l. Referring to this circuit,
the collector current of the input transistor is
given by
+
VC2 =V -
.E
N
N
I
~
(A.3)
VC2 = V+ - IC2R12
For zero differential input voltage, the collector
currents of 01 and 02 will be equal so Equation
(A. 3) becomes
R12
(v+ - 3V BE - .B.:!Q
v+)
R9
Rl0+Rll+R3
.(A.4)
It is desired that this voltage be 3V BE so that the
output stage is just on the verge of switching with
zero input. Forcing this condition and solving for
R12 yields
V+ - 3V
R12= (Rl0+ Rll + R3) +
RB1EO +
V -3V BE - M V
V+ - V BEl - V BE3 - V BE4
ICl = R911 Rl0+ Rll + R311 RS
R3
R311 Rll
R4 + 2R6 + R3 VBE 1 - RS + R3 /1 R 1 VIN
R911 Rl0+ Rll + R311 RS
+
Rl01lRll
(VIN-V) R9+Rl011Rll
(A.l)
+
R911 Rl0+ Rll + R3// RS
(A. 5)
RESPONSE·TIME
CONTROL
AIO
16'
~
A12
A17
1.5K
A16
3K
5.OK
AI1
4.15K
~
A.
5K
NON-INVERTING
INPUT
...
....lD
4.5h~., ·,r
A15
., '-t
A'
170
'"
A13
1.5K
Q2
A8
5'
OUTPUT
......
A.
lK
I';
TERMINATION1 A.
lK
A5
1K
A14
'60
A'
16'
GROUND
Al
INVERTING
5K
A2
16'
INPUT
STROBE
DM7820duai Imoreceiver (one sIde)
FIGURE A-l. Schematic Diagram of the DM7820 Line
Receiver
10-14
This shows that the optimum value of R12 is
dependent on supply voltage. For a 5V supply it
has a value of 4.7 kD.. Substituting this and the
other component values into (A. 4).
V C2 = 2.a3V BE + O.Oal V+ ,
(A.6)
which shows that the voltage on the collector of
02 will vary by about ao mV for a lV change in
supply voltage.
The next step in the analysis is to obtain an
expression for the voltage gain of the input stage.
R1
f
5.
AV IN
I
~:, ~R~
R"
R1
RI
1K
1K
~3 0.'"
j.,"
R12
415K
LIOU'
Finally, the threshold error due to finite gain in
the output stage can be considered. The collector
current of 07 from the bleeder resistor R 14, is
large by comparison to the base current of oa, if
oa has a reasonable current gain. Hence, the collector current of 07 does not change appreciably
when the output switches from a logic one to a
logic zero. This is even more true for 06, an
emitter follower which drives 07. Therefore, it is
safe to presume that 06 does not load the output
of the first-stage amplifier, because or the compounded current gain of the three transistors, and
that oa is driven from a low resistance source.
It follows that the gain of the output stage can be
determined from the change in the ernitt~r-base
voltage of oa required to swing the output from a
logic one state to a logic zero state. The expression
kT
ICl
t.V SE = q log. I;;
FIGURE A-2. Equivalent Circuit Used to Calculate Input
Stage Gain
An equivalent circuit of the input stage is given in
Figure A·2. Noting that R6 = R7 = Ra and
R2 '=' 0.1 (R6 + R7 lIRa). the change in the emitter
current of 01 for a change in input voltage is
0.9 R2
t.I E2 = Rl (0.9 R2+ R E2 ) t.V IN ·
(A. 7)
Hence, the change in output voltage will be
t. V OUT = al E2R 12
0.9aR2R12
=Rl(0.9R2+Rd
t.V IN ·
Since a '=' 1, the voltage gain is
0.9 R2 R12
The emitter resistance of 02 is given by
kT
R E2 =qlc2 '
V+ - 3V BE
IC2=
R12
where
so
R
kTR12
_
E2 - q (V+ - 3V BE )
describes the change in emitter-base voltage required to vary the collector current from one
value, lel' to a second, Ic2 . With the output of
the receiver in the low state, the collector current
of oa is
IOL =
(A. a)
(A. 9)
(A. 10)
With a voltage gain of 0.75, the results of Equation (A. 6) show that the input referred threshold
voltage will change by 0.11V for a 1V change in
supply voltage. With the standard ±10-percent
supplies used for logic circuits, this means that the
threshold voltage will change by less than ±60 mV.
(A. 14)
where VOL. is the low state output voltage and
ISINK is the current load from the logic that the
receiver is driving. Noting that R13= 2R14 and
figuring that all the emitter·base voltages are the
same, this becomes
(A.ll)
670 mV and
Therefore, at 25°C where V BE
kT/q = 26 mV, the computed value for gain is
0.745. The gain is not greatly affected by tempera,
ture as the gain at -55°C where V ~E = al 0 mV
and kT/q = la mV is 0.774, and the gain at 125°C
where V BE =4aO mV and kT/q = 34 mV is 0.730.
V+ - VOL - V BE9 - V BE10
R17
VSE7
V BE9 V BE8
+ R15 - R14 + R13 + ISINK ,
IOL =
(A. 12)
(A. 13)
V+-V oL -2V SE V BE
R17
+ R15
V BE
-2R14 + ISINK '
(A. 15)
Similarly, with the output in the high state, the
collector current of,Oa is
IOH =
V+ - VOH - V SE9 - VSE10
R17
V BE7
+ RlJ - ISOURCE ,
(A. 16)
where V OH is the high-level output voltage and
ISOURCE I~ the current needed to supply the input
leakage of the digital circuits loading the
comparator.
10-15
ca
.t:
.21
Q
With the same conditions used in arriving at
(A. 15), this becomes
IOH
=
V+ - VOH - 2V SE
VSE
R17
+ RT5
V BE
- 2R14 -lsouRCE .
(A. 17)
From (A. 13) than +10V.
Secondly, when the analog signals on some channels are positive and those on other channels are
negative, the negative currents will subtract from
the positive currents, further reducing the total
leakage at the output. Also, when a switch is ON,
it would not be contributing to the leakage.
Assuming signal voltages vary randomly between
+10 and -10V, total leakage will run about half
that of worst case. Of course, leakage will be still
less if the analog signal limits are less tt-an ±10V.
CONCLUSION
Integrated MOSFET switching circuits make excellent low-level analog commutators.' Power dissipation is essentially zero, capacitance is reasonably low (typically 8 pF at the analog input), the
ROFF/RoN ratio is high, and the control signal is
isolated from the input. MOS IC's with four or
more switching channels are readily available in
production quantities.
Conventional bipolar drive circuitry can control
channel switching at rates in the megahertz range.
Hybrid integrated circuits containing monolithic
MOS multiplexers and bipolar drivers are being
manufactured for medium-speed applications
(NH0014 and NHOO19). Level-changing circuits in
these devices allow external TTL or DTL IC's to
control the commutator at analog signal levels to
±10V. MOS commutator systems can be built with
building-block circuits such as the MM454F in
Figure 12. This monolithic IC can commutate at
rates to 1 MHz, depending on the range of signal
voltages. The control logic on the chip includes a
clock-fiountdown c!1ain that facilitates submultiplextH~~' l . N,~";j;,
.~,
10-21
ANALOG
OUTPUT
ca
c
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en
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ci
CLOCK
INPUT
('I)
('I)
OUTPUT
.:1
COUNTDOWI
....T·--......------~
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FIGURE 12. Logic Diagram of MM454F Four-Channel
MOS Multiplexar. Switches and Control
Circuitry Are Fabricated In the Same Monolithic Chip.
MOSFET switches are generally used to commutate low-frequency analog signals. Today, the
preferred device for RF-signal multiplexing is the
N-channel junction FET, which can handle signal
frequencies in the VHF range. MOS IC's have operated successfully, however, in some RF application. The high-frequency capabilities of MOS IC's
are being investigated by the author and will be
the subject of a future report.
Although the most outstanding feature of
MOSFET's is the ease with which they can be fabricated as multichannel monolithic IC's, their electric81 characteristics compare quite favorably with
those of other switching components. An "order
of magnitude" comparison of MOSFET's and
other devices that could be used for lOW-level
analog switching is given by Table 1. Better characteristics might be obtained in each case, but
these values are typical.
Each type of analog switch has advantages and
limitations that must be considered for practical
use. No switch is perfect. If a switch were perfect,
it would have zero resistance when ON, infinite
resistance when OFF, and be 100% efficient-that
is, it would consume no power.
Electrically, the mechanical switch comes close to
this ideal. It has the highest ROFF/RoN ratio and
totally isolates the analog signal from the switching-control function. However, it has mechanical
drawbacks that make it noisy and unsuitable for
10-22
low-level commutation: contact bounce, contact
pitting, susceptibility to vibration, and the necessity to move a physical mass to turn the switch on
or off. It cannot commutate very fast and consumes more power than a solid-state switch, as a
rule_
Bipolar transistors make excellent digital switches,
the fastest ever developed, but they are usually a
poor choice for multiplexing low-level analog
signals. Their main disadvantages are an inherent
offset voltage and the impossibility of isolating the
switching control signal from the analog signal
being switched. Furthermore, analog switching
rates are slower than FET's. Their Ron is low,
though-typically 10 ohms in, analog switches
(versus milliohms in power transistors). Bipolar
transistors fare much better in high-level switching,
where DC offset is not a problem.
Photocells make fairly good analog switches.
Because light is used as the control signal, the control is completely isoillted from the analog electrical signal. However, Ro N is high and the
ROFF/R ON ratio is relatively poor. Even at
moderate RO~F/RoN ratios, photocells cannot
commutate much faster than 100 Hz. After exposure to intense light, a photocell made with a
semiconductor such as cadmium sulfide or cadmium selenide exhibi~ a long turn-off decay time.
Photocell turn-off time constants may stretch out
for many seconds before Ro F F reaches an acceptable level. Faster switches can be made with combinations of electroluminescent diodes and phototransistors, but these devices are still very
expensive.
Some N-channel junction FET's come close to
being ideal switches. Offset voltage is zero, and the
admittance-ta-input capacitance ratio Yh/C". is
the highest of any contemporary device. These
two parameters govern commutation rate, which
can be very high if the impedances of the signal
source and the load are made very low. Theoretically, the high majority-carrier mobility in an
N-channel J-F ET enables it to operate at a frequency higher than any other tyPe of FET. A
good example is the 2N4391: ROFF/RoN is
about 109 , Rd. (on) is a maximum of 30 ohms,
and maximum leakage at 2SoC is 100 pA. The orle
major disadvantage of N-channel J-FET's is that
they are extremely difficult to make in the form
of multichannel IC's. For high-frequency commutation, the P-channel type of J-FET is a !,loor
choice because its majoritv carrier mobilitY is
lower than N channel J-F ET' s.
»2
Applications
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APPLICATIONS OF MOS
ANALOG SWITCHES
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ABSTRACT
This discussion begins with some basic commutation circuits, then describes some uses in linear
amplifier applications such as reset fllnctions and
chopper applications. The use of MOS switches as
a suppressed carrier double-sideband modulator
and a double-sideband demodulator is then covered; followed by a circuit proposal for a phaselocked loop AM-FM detector without tuned
circuits.
THE MOS DIFFERENTIAL SWITCH-DC TO RF
The dual differential switch is a particular switch
connection scheme wh ich at first glahce prompts
one'to say-so what? It is, however, one of those
simple circuit configurations which can find a wide
variety of uses in electronic circuits. The dual differential switch could also be called a DPDT
switch or two SPDT switches-depending on how
they are toggled.
MOS switches have some unique features which
make them very useful for data switching' ,2,3: no
offset voltage, high Ro F F IRa N ratios, low leakage, fast operation, and matched "on" resistance.
Within definite bounds, MOS switches exhibit
good isolation between the switching drive and
signal path.
MOS switches do have somewhat unique driving
,requirements. In order to solve this problem,
National manufactures a hybrid integrated circuit
which' provides DTL-TTL drive compatibility with
the dual differential switch. These devices use the
DM7801 chip with an MM450 chip for the
NHOO14 and the DM7800 chip with an MM450
chip for the NH0019. The NH0014 is basically a
DPDT switch while the NH0019 is two SPDT
switches in the same package. Each connection has
its particular advantages and disadvantages.
COMMUTATION CIRCUITS
The NH0014 may be used as a two channel como'"~
mutator only, because two of its four channels are
always on. The NH0019 may be used for systems
with any number of channels since it can shut all
channels off on command.
Figure 3 shows a six channel commutator which
'may be easily expanded. Data sampling may be
done on any format wh ich the user chooses. Sampling format is easily controlled by DTL or TTL
logic design independent ,of the NH0019. Since
each bllffer-driver of the NH0019 has a dual input
gate, all channel blanking is readily achieved. If
desired, the format shown in Figure 3 may be
::~~
0--0
I
0--0
I
I
I
I
(a) MOS Configuration
(b) Schematic Configuration
FIGURE 1. MM4501MM550 MOS Dual Differential Switch
10-23
modified so as to use the NH0019 logic inputs as
binary gates which can'reduce the command logic
complexiW if the blanking function is not
required.
figuration. Demultiplexing may be accomplished
by using a circuit identical to the multiplexer
because the MOS device is a true bilateral switch.
In hard·wired systems where the multiplex "out·
puts" are electrically connected as in Figure 4, the
signal may be transmitted in either direction. For
non·hardwired systems, the modulation·demodula·
tion sequence is still bilateral, but provisions must
be made for transmit/receive function control.
Since the multiplexed information is in differential
form, common mode noise' is greatly reduced.
Also, the MOS gate drive spiking is drastically
reduced because of the differential channel con·
'S
III
c
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1U
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3Vee----~--~----------------------------------__,
Q.
Q.
c:(
OUTPUT INPUT INPUT ,. .1 IIII'UT OUTPUT
1
11
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AI
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L..--...-1Hf-....--~~'
'++-.--014
'.,."
'Icc
ANALOG OUTPUT I
lie
N.e v"' ....
GND
Note: Allinpub "HIGH,"
AIIALOOOUTPUT2
lal NH0014
OUTPUT IN"" IN'UT
Vee
0
B
Gil.
Y""~II'
Ypl~1
Z
AI
OUTPUT INPUT I..-tIT
1
AI
Note: All inputs "HIGH,"
(bl NHOO19
FIGURE 2. NH0014 and NH0019 DTL·TTL Compatible
MOS Analog Switches
10·24
II
II
»
2
ALLCHA .... n
ILANKING
I
rNH0QI1
-- -- -
-
-
-
-
-
-
-
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--------~},
tNANNH
SELEI:T
LIliES
o....
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________ J
--------1
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FIGURE 3. Differential Signal Commutatpr-NH0019
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I'"
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I'"
I,"'
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FIGURE 4. Commutation-Modulation and Demodulation
10·25
USAGE IN LINEAR AMPLIFIER CIRCUITS
The NH0014 and NH0019 devices are useful for
switching functions in linear circuit applications
because of high off/on resistance ratio and ease of
switching control using logic elements. Sample and
hold circuits, integrator reset switching, and reset
stabilized amplifiers are a few examples (Figure 5).
More detailed information on this type of circuitry
is available in National Semiconductor applications
notes AN-4, AN-5, AN-20, and AN_29 4 - 7 •
An obvious use of the NH0014 and NH0019 are in
chopper stabilized amplifiers (Figure 6). One of
the better forms of chopper stabilized amplifiers is
the series shunt chopper with sample and hold
type of output. The NH0014 does a good job at
this because it contains the complete set of
switches plus proper drive for the switches. The
NH0014 can greatly reduce component count for
chopper stabilized amplifiers.
DOUBLE SIDEBAND MODULATOR
The NH0019 can be used as a double sideband
mo.;ju lator. In modu lator applications, the
NH0019 functions as a DPDT switch which alternately reverses the polarity of the modulating
signal at the chopper frequency. MaS switches
work quite well at this application because of zero
offset voltage and large signal handling ability.
In order to build a double sideband balanced
modulator8 ,9, one of the two modulating inputs
must be applied as a balanced input. For the circuit shown in Figure 7, an LM102 and LM107
were used for an audio phase splitter.
(al Intogrator
(bl Reset Stabilized Amplifier
FIGURE 5. SWitching Applications With Linear Circuits
CHOPPER
DRIVE
r - - - - - - - - - - -Nii,Oi4]
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INPUT
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FIGURE 6_ Series-Shunt Chopper Stabilized Amplifier
10-26
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LS--~----_.--------------~----~---------
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FIGURE 7. Double Sideband Modulator·Demodulator
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CO
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Both point A and point B in Figure 7 are DSB
modulated outputs; so, technically, you could get
by with only one. The waveform at point A is
illustrated in Figure 8a for a carrier frequency of
100 kHz and an audio frequency of 12.5 kHz.
Point B is equal and out of phase.
One type of spurious response encountered with
MaS switching devices is output spikes caused by
a charge being dumped into the channel by the
gate drive through gate·channel capacitance. By
adding Cl, part of the charge can be absorbed,
the switching transients are an "in phase" or
"common mode" error.
To better illustrate th'e improvement by using a
balanced output, the audio signal was reduced to
zero volts and the points A, B, and AB were mea·
sured as shown in Figure 9. The improvement
operating in the differential mode is oDvious.
The circuit drive requirements for Figure 7 may be
simplified by using the NH0014 since it provides
an inverting function internally. Only one phase of
toggle drive to the NH0014 is required.
lOris/em
Vart lV/em
HOUI
(al Va
FIGURE 8. Double Sideband Signal
thus reducing the voltage ampl itude of the spikes.
The R1Cl combination has its 3 dB point at about
80 kc, so output from the phase splitter was not
attenuated in the audio range.
The astute observer will notice switching transients
on the waveform in Figure 8a. By taking the out·
put in differential form at points A and B, these
transients are greatly reduced because the desired
signals are equal but of opposite polarity, while
The modulation will be distorted more due to the
phase lag created by the internal inverter of the
NHOOI4. Figure lOa shows the switching perform·
ance of the NH0019 while Figure lOb shows the
switching performance of the NHOOI4. In applica·
tions which do not require high carrier fre·
quencies, the N H0014 is adequate, but for carrier
frequencies above 100 kHz, the NH0019 provides
improved performance because of its symmetrical
switching behavior.
10·27
~
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c.l
...
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(J)
ell
0
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Han! SOns/em
Vert 01V/cm
C
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FIGURE 9. MOS Switching Transients
C
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lal NH0019 50 nslem
Ibl NH0014 50 nslem
FIGURE 10. Channel Switehing-NH0019 vs NH0014
lal Single Ended Output
(b) Differential Output
FIGURE 11. Demodulator Recovered Output
DOUBLE SIDEBAND DEMODULATOR
The major requirement of double sideband signal
demodulation is proper carrier reinsertion. For
maximum output, the carrier must be reinserted
exactly in phase or exactly 1800 out of phase with
respect to the signal. Any departure from th is
optimum phase relationship will reduce the reo
covered signal amplitude. By applying the double
sideband signal to a second N HOOl g, as shown in
Figure 7, the original modulating waveform may
be recovered, along with some switching transients
(Figure 11).
10·28
These switching transients may be filtered out
quite easily. It is, however, instructive to compare
the recovered audio signal with the original. The
modulating signal had less than 0.1% distortion at
1 kHz. Figure 12 shows the distortion of the
recovered signal vs. signal amplitude.
Carrier frequency was 100 Hz for the upper curve
and 10k Hz for the lower. These curves indicate
that most of the distortion is due to switching
transients, especially at low modulation levels.
Output filtering will significantly reduce the reo
covered signal distortion.
Figure 13 emphasizes the affect that switching
transients have on harmonic distortion. At carrier
frequencies below 10 kHz, the RMS value of the
transients is reduced to a point where distortion of
the MOS switches themselves can be seen.
The NH0014 and NH0019 data sheet suggests a
V plus supply value of 10 volts and a V minus
supply value of -20 volts. However, switching
transients may be reduced by using different power
supply voltages. Figure 14 and Figure 15 show what
happens to harmonic distortion caused by spiking
versus power supply level. Figure 14 is plotted for
V minus with V plus at 10 volts. Figure 15 shows
what happens as V plus is varied. All of the pre·
vious data was taken at V plus at 14 volts and V
minus at -12 volts.
AM-FM DEMODULATOR
Although an AM·FM demodulator was not
physically constructed, the previously discussed
"double sideband demodulator" performance
implies that a very interesting phase detector can
be built. The interesting features of this type of a
detector are large dynamic range, recovery of both
12.0
.
1M
zQ
~
~
6J
~
'.D
1111
111111
1111
IIlIU
~ SIG FRED AT 1.0 kHz
Figure 16 shows the proposed circuit block diagram which uses a phase-locked loop for phase
reference signal. The voltage controlled oscillator
(VCO) is operated at 4 f o . Flip Flop #1 provides a
two phase output which is fed into FF #2 and
FF #3. The outputs of FF #2 and FF #3 are
exactly 900 out of phase regardless of the frequency of the VCO. This kind of performance is
awfully hard to achieve using tuned clrcu its. For a
455 kHz detector, the VCO would operate at
1820 kHz. TTL flip flops will operate quite nicely
at that frequency and shou Id hold phase sh ift
errors to practically zero. The LM 107 provides DC
gain to close the phase-locked loop, it forces the
VCO to a frequency and phase angle which causes
the "FM out" port to zero volts DC; this port is
then operating exactly in quadrature with the
applied signal. This part of the detector is then
insensitive to amplitude modulation and sensitive
to frequency modulation. Since the AM detector
portion is operating exactly 90 0 out of phase with
the FM portion, its output is insensitive to FM and
sensitive to AM.
"
11111
lUll
~
~
a
~
~
D.l
"
"
IM~INAL AT IdMl'Hl
30
!;;
'0 kHz
.ot
11111111
111111 U 1111~
Q
l00~
2.D
111111
5.D
2
C. RRIER AT 100 kHz AND 10 kHz
!;;
~
in·phase (amplitude modulated) and quadrature·
phase (frequency modulated) signals plus the
feasibility of not using any inductors for tuning.
"
"
V
"D
1D
10,000
1000
100,000
CARRIER FREQ (Hz)
RMS-VOL15 (VI
There was httle slgm'lcant difference In dlstortlDn
at Signal amplitudes of 3 OV, 1 OV, 0 lV, 0 IV RMS
FIGURE 12. Recovered Signal Harmonic Distortion vs
Audio Modulation Level
FIGURE 13. Recovered Signal Harmonic Distortion vs
Carrier Frequency
Z
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~
~
~~
POSITIVE SUPPLY AT+.DV
50
~
a
~
.D
30
"
"
I----~URVE 1 NEG SUPPLY AT -20V
~
CURVE 2 NEG SUPPLY AT -12V
1
50
4D
2
3D
"
1D
10 12 14 16 18 20 22
NEGATIVE SUPPLY VOLTAGE (V)
FIGURE 14. Harmonic Distortion vs Negative Power
Supply Voltage
20
60
100
140
180
POSITIVE SUPPL Y VOLTAGE (VI
FIGURE 15. Harmonic
Voltage
Distortion vs Positive Supply
10-29
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FIGURE 16. AM·FM Demodulator
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CONCLUSION
The most obvious use of the NH0014 and NH0019
is in commutator applications, and it indeed is a
very useful device for that purpose. The use of
these switches in linear circuit applications is also
very attractive because of DTL· TTL control com·
patibility. There are many more uses of these
switches possible than the few examples described
here.
The unusual application of these devices as sup'
pressed carrier double·sideband modulators and
demodulators suggests applications in servo systems
and even communications systems due to their
high speed operation. The final circuit suggestion,
a phase·locked loop AM·FM demodulator without
tuned circuits should be very useful in communica·
tions systems. The NH0019 will operate quite well
at an IF frequency of 455 kHz or less.
These basic capabilities of the MOS dual differen·
tial switch should encourage much greater usage
of this type of device in new product' designs.
2. D.L. Wollesen, "Analog Signal Commutation",
National Semiconductor AN·33, February
1970.
3. D.L. Wollesen, "Analog Switching-High Speed
With JFET's", EDN, January 15, 1970.
4. R.J. Widlar, "Monolithic Operational Ampli·
fiers", National Semiconductor AN·4, April
1968.
5. R.J. Widlar, "Integrated Voltage Follower",
National Semiconductor AN·5, May 1968.
6. W.S. Routh, "Applications Guide For Op
Amps", National Semiconductor AN·20,
February 1969.
7. R.J. Widlar, "I.C. Op Amp Beats FET's On In·
put Current", National Semiconductor AN·29,
December 1969.
8. F.E. 'Terman, Electronic and Radio Engineer·
ing, McGraw·Hill, New York, 1955.
REFERENCES
1. D. Mrazek, "High Speed MOS Commutators",
National Semiconductor AN·28, January 1970.
10-30
9. M. Schwartz, Information Transmission Modu·
lation and Noise, McGraw·Hill, New York,
1959.
»
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Applications
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ii1
PIN DIODE DRIVERS
INTRODUCTION
The DH0035/DH0035C is a TTL/DTL compatible,
DC coupled, high speed PIN diode driver. It is
capable of delivering peak currents in excess of
one ampere at speeds up to 10 MHz. This article
demonstrates how the DH0035 may be applied to
driving PI N diodes and comparable loads which
require high peak currents at high repetition rates.
The salient characteristics of the device are summarized in Table I.
There are essentially two considerations of interest
in the "ON" condition. First, the amount of
"ON" control current must be sufficient such that
R F signal current will not significantly modulate
the "ON" impedance of the diode. Secondly, the
time required to achieve the "ON" condition must
be minimized.
"flNC"..-)......--i)'H ~RFOUT
"FC ~
PARAMETER
CONDITIONS
Differential Supply
Voltage (V+ - V-,
30V Max.
Output Current
1000mA
Maximum Power'
~elay
~ .. C"'
I~(1--+-----'
t ~
VALUE
CONTROL NODE
1.5W
PRF
= 5.0 MHz
FIGURE 1. Simplified PIN Diode Switch
10 ns
V+-V-=20V
10% to 90%
15 ns
V+ - V- = 20V
90% to 10%
10 ns
The charge control model of a diode 1 ;2 leads to
the charge continuity equation given in equation (1).
Table I DH0035 Characteristics
i=
where:
Figure 1 shows a simplified schematic of a PI N
diode switch. Typically, the PIN diode is used in
RF through microwave frequency modulators and
switches. Since the diode is in shunt with the R F
path, the R F signal is attenuated when the diode
is forward biased ("ON"), and is passed unattenuated when the diode is reversed biased ("OFF").
Q
(1 )
Q = charge due excess minority carriers
T =
PIN DIODE SWITCHING REQUIREMENTS
dQ
Cit +-;;-
mean life time of the minority carriers
Equation (1) implies a circuit model shown in Fig..
dQ
ure 2. Under steady conditions !it = 0, hence:
(2)
where:
I = steady state "ON" current.
10·31
~
II)
>
The time response of the charge, hence the time
for the diode to achieve the "ON" state could be
shortened by applying a current spike, Ipk, to the
diode and then dropping the current to the steady
state value, IDC, as shown in Figure 3b. The
optimum response would be dictated by:
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I "Total current
loc '" SS control current
IRF '" RF sIgnal current
C
,5
(lpk) (t) = T'l oc
D..
(5)
Q)
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I
FIGURE 2. Circuit Model for PIN Switch
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DIDDE
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V-=-lDV
FIGURE 6. Cathode Grounded Design
where:
2V BE = forward drop of 0 4 base emitter
junction plus Vf of the PIN diode = 1.4V.
In terms of Rp, equation (15) becomes:
Rp =
(h fe + 1) (V+ - 2V BE ) - loc R3
(h fe + 1) loc
Again, the power dissipated by the DH0035 must
be considered. In the "OFF" state, the power
dissipation is given by:
(20)
(15a)
For the circuit of Figure 6, and IDC = 100 rnA,
Rp is 62 ohms (nearest standard value).
It now remains to select the value of C,. To do
this, the change in voltage across C, must be
evaluated. In the "ON" state, the voltage across
C" Vc, is given by:
(16)
where:
D.C. = duty cycle =
"OFF" time
"OFF" time + "ON" time
The "ON" power dissipation is given by:
2
PON -_ [ (VC)ON + loc X (VC)ON ] (1 R3
~,C.)
(21)
For the values indicated above, (Vc) ON = 3,BV,
where:
(VC)ON is defined by equation (16).
In the "OFF" state, Vc is given by:
( 17)
Total power dissipated by the DH0035 is simply
PON + POFF . For a 50% duty cycle and the circuit of Figure 6, P diss = 616 mW.
(lB)
The peak turn-off current is, as indicated earlier,
equal to 50 rnA x hfe which is about 1000 rnA,
Once the excess stored charge is removed, the
current through 0 5 drops to the diodes leakage
current. Reverse bias across the diode = V- - Vsat ~
-10V for the circuit of Figure 6.
= B.OV for the circuit of Figure 6.
Hence, the change in voltage across C, is:
V
(VC)OFF - (VC)ON
B.O - 3.B
REPETITION RATE CONSIDERATIONS
4.2V
The value of C4 is given, as before, by equation
(11) :
C, =
For a diode with
C, = 250 pF.
T
IOCT
\F
= 10
ns and loc
(19)
= 100
Although ignored until now, the PRF, in particular,
the "OFF" time of the PIN diode is important in
selection of C2 , RM , and C" Rp. The capacitors
must recharge completely during the diode "OFF"
time. In short:
(22a)
rnA,
4 RpC,
~
tOFF
(22b)
10-35
e
~
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c
.5
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en
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z
ct
FIGURE 7. RF Turn-On (10 ns/em)
FIGURE 8. RF Turn-Off (10 ns/em)
CONCLUSION
The circuit of Figure 6 was breadboarded and
tested in conjunction with a Hewlett-Packard
33622A PI N diode.
loc was set at 100 mA, V+ = 10.OV, V- = 10V.
Input signal to the DM8830 was a 5V peak,
100 kHz, 5 jJ.s wide pulse train. RF turn-on was
accomplished in 10-12 ns while turn-off took
approximately 5 ns, as shown in Figures 7 and 8.
has been demonstrated which enable the designer
to tailor the DH0035 driver to the PIN diode
application.
REFERENCES
1. "Pulse, Digital, & Switching Waveforms", Jacob
Millman & Herbert Taub, McGraw-Hili Book
Company, Inc., New York, N.Y.
In practice, adjustment C2 (C l ) may be required
to accommodate the particular PIN diode minority
carrier fife time.
2. "Models of Transistors and Diodes", John G.
Linvill, McGraw-Hili Book Company, Inc., New
York, N.Y.
SUMMARY
3. National Semiconductor AN-18, Bert Mitchell,
March 1969.
A unique circuit utilized in the driving of PI N
diodes has been presented. Further a technique
4. Hewlett-Packard Application Note314, January
1967.
1036
Appl ications
HIGH SPEED ANALOG SWITCHES
SUMMARY
In the past, many factors combined to make
precision, high speed analog switching circuits complex and expensive, if not impossible_ A unique
monolithic J-FET family opens new analog switching applications which require high toggle rates,
high frequency signal handling ability, and high
level analog signals with broad dynamic range_
Called the AM 1000, AM100l and AM1002 analog
switches, these devices were developed specifically
for high speed analog switching applications_ The
AM 1000 series overcomes the probl em of slow
switching speed normally associated with junction
FET analog switches_ While MOS analog switches
are noted for their high speed, they have the
peculiar problem of their ON resistance being
modulated by the analog signal leveL The AM1000
series eliminates this problem too_
National's AM1000 series analog switches are
simple N-channel monolithic integrated circuit
J-FETs. They are packaged in TO-72 (4-pin TO-1S)
headers to reduce circuit board space and yet
retain the advantages· of a hermetically sealed
package.
WHAT IS AN ANALOG SIGNAL?
An analog signal is an electrical voltage (or
current) whose level is an analog of certain information. This information can be an electrical
level itself, a voice signal, an electrical analog
of a pressure, temperature, position, etc., or any
other data source. The analog information may
also be preconditioned by logarithm ic compression or expansion, or other desired "distortion_"
If the analog information does not vary quickly
with time and if many analog signals have to
be handled in a system, the analog information
. may be sampled periodically rather than monitored
continuously_ Sampled data systems can dramatically reduce cost and weight by proper utilization
of available information channel bandwidth where
the cost of additional data channels becomes
expensive.
The telephone companies are probably the most
adept at signal multiplexing, but other applications
are beginning to appear. Modern aircraft are using
multiplexing to reduce weight in wire harnesses.
Any applications requiring long multiconductor
cable runs are prime targets for economic use of
analog signal mUltiplexing.
TIME DOMAIN MULTIPLEXING
There are two basic types of mUltiplexing: frequency domain multiplexing and time domain
multiplexing. Frequency domain multiplexing is
common in RF communications, it uses a number
of subcarriers on a data channel, each subcarrier
being modulated in some manner. An example
would be FM radio standard broadcast which has
home stereo mu Itiplex information (a suppressed
carrier double sideband subcarrier) and the SCA
commercial "background music" multiplex information (an FM modulated subcarrier). When
the number of data channels becomes great, frequency domain multiplexing becomes difficult to
implement.
In time domain multiplexing, a certain time slot
is allowed for sampling of a particular data line.
Thus, if you sample some analog information
during a 10 j.ts time slot at a 10kHz rate, you
have time "left over" to sample nine other signals
at 10 j.ts intervals at a 10 kHz rate. If you can
improve the analog switch device to execute a
suitable sample in only 1 j.tS, you have made a
tenfold improvement and you have th e choice of
increasing system channel capability to 100 channels (with no change in analog signal bandwidth),
increasing analog signal frequency bandwidth by
10 times (with no increase in channels), or a compromise between increasing signal bandwidth and
increasing the number of data channels. This is
what the AM 1000 family of analog switches is
all about; they allow shorter sampling times for a
given signal accuracy.
10-37
WHAT MAKES A GOOD ANALOG SWITCH?
There are five principle parameters wh ich determine how good an analog switch is:
There is at least -10V from gate to source of 0 1
so it is pinched off and leakage from .input to
output is in the pA range. O 2 has -10V from gate
to source so it is also pinched off and its current
which shunts the input signal is in the pA range_
ON resi sta nce
ON resistance modulation
OFF resistance
Offset voltage
Commutation rate
There are other considerations which may also be
significant for special cases, but these five will
almost always have significant bearing on a system
design. For most applications, there are two devices which are the most popular-MaS switches
and J-FET switches. Relays normally would be
a good choice but they won't toggle very fast.
In general, the MaS switches have had a speed advantage, and ease of fabrication advantage, whereas the J-FET switches have an advantage of lower
ON resistance, no ON resistance modulation, higher
voltage capability.4.5,6 The AM1000 family of
analog switches have all of the advantages of the
J-FET plus high speed which makes it superior to
any MaS switch in a precision system.
WHAT MAKES THE AM1000 FAST?
Figure 1 shows a typical J-FET circuit used in
analog switching. Diode 0, allows the gate drive
signal to drive the gate negative thus turning off
the J-FET switch. When the gate drive signal goes
positive, diode 0 1 decouples the drive from the
gate and resistor Rg discharges the gate-source
capacitance. Rg ml,lst be large so it doesn't load
the analog signal, typical values for Rg are 100 kn
and up; thus the gate capacitance:-Rg time constant is large which precludes high switching rates.
If Ciss of the J-FET is 15 pF nominal and Rg is
100 kn, the time constant is 1.5 p.s thus making
megacycle toggle rates impossible.
FIGURE 2_ AM1000 Circuit
FIGURE 3_ AM1000 Turned Off
0 3 is operated at OV gate-source so it draws saturation current, loss. The bias supply for 0 1 must be
10V more positive than the negative drive signal.
During turn-on, the drive signal ideally makes a
step function change from -20V to +10V thus
turning O2 off. The gates of 0" O2 and 0 3 are
then driven positive by the saturation current of
0 3 through diode 0,. The rate that this voltage
slews is dependent on gate capacitance and loss
of 0 3 . C;ss(off) of the AM 1000 is about 10 pF so
the voltage slews at:
loss
dv
dt =
c:-
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FIGURE 1. Typical J-FET Analog Switch
The AM 1000 consists of three J-FETs. One large
and two small ones. The large one acts as the
analog signal pass transistor. The two smaller
FETs act as a turn-on circuit which reduces
switching transients.
The pinchoff voltage of all these FETs are almost identical and are all less than 10V_ In Figure :3 (ignoring diode drops). the gates of all three
FETs are at -20V and the AM1000 is turned off.
10-38
5 X 10-3
10-'1
= 5 X lOB V/sec
Within 5V of rise (about 10 ns). O2 begins to turn
on and 0 1 turns off_ The remainder of the gate
capacitance charge is discharged into the input
(or source) of 0 1 via the ON resistance of O2 and
0 3 , During this time interval the average series
resistance of O2 and 0 3 is about 2 kn and the
gate capacitance is changing from about 10 pF
to about 25 pF. The approximate RC time constant is 20 pF and 2 kn, or 40 ns, depending on
the level cif the analog signal. Total turn on time
is therefore about 50 ns. For a +10V analog
signal, the correct analysis is a little more complex,
but the AM 1000 will turn on in about 70 ns for
this circuit'condition. The reason that the turn-on
transier)t at R L is drastically reduced is that the
discharge path . of gate capacitance does not flow
through R L. The small transient that may appear
at R L is due to the time that Dl is on during
turn-on.
Gate capacitance discharge path
FIGURE 4. AMI 000 Turning On
So, the AM 1000 achieves its high switching speed
because its Rg (see Figure 1) is very low during
turn on, yet its Rg during the OFF state is in the
G ohm range and thus doesn't load the signal.
The capacitance of the AM 1000 is about twice that
of the MOS switch but the system load resistance
is 25 times lower thus giving the AM 1000 a toggle
rate advantage of about 12 times over the MOS
"high speed" analog switch. In order to graphically
illustrate the superiority of the AM 1000, two
simple series switches were constructed; one with
the MOS switch and one with an AM 1000. The
MOS analog switch was set up to sample a +10V
DC signal, after being switched off, the output
returns to ground level. The AM 1000 was set up
to sample a portion of the turn off transient of
the MOS analog switch, each switch with a 0.5%
system accuracy! Figure 5 shows the circuit used
to obtain the oscillograph shown in Figure 6A.
TOGGLE RATE
The toggle rate (how fast the switch can be turned
on and off) of an analog switch is not a simple
straightforward parameter for a real system design.
The reason is that most analog switches are speci·
fied at a ridiculously low impedance level; this is
done in order to show the highest speed that the
device can possibly go. This speed is not normally
realistic for most systems designs. In order to
demonstrate a realistic comparison, the AM 1000
will be pitted against an MOS analog switch for a
system with a ±10V analog signal swing.
TABLE 1: AM1000 - MOS Parameter Comparison
PARAMETER
AMIDOD
ROS(on)
(Max)
30n
4000
ROS(on)
(Min)
20n
150n
ROS(on)
(Nom)
25n
275n
C,g
(Nom)
15 pF
Breakdown Volts
40V
FIGURE 5. Analog Switch Comparison Circuit
MOS
ANALOG SWITCH
7 pF
35V
ROSlon) and Ciss indicate the basic speed capability
of the devices assuming low source and load
impedance, here the AM 1000 has a speed advantage
of about 5: lover the MOS switch.
The parameter that affects toggle rate the most,
however is ROSlon) variation with analog signal
level. At an analog signal of +10V, the MOS
switch has an. ROSlon) of 150n and for a -10V
analog signal it has an on resistance of 400n. This
variation of ON resistance is caused by the bulk
gate to channel voltage modulating the ON reo
sistance of the MOS switch. 5 Thus, the MOS
switch has a design on resistance characteristic of
275n ±125n. The AM1000 has an ROSlon) of 25n
±5n and its resistance does not vary with analog
signal level.
For a system of a given accuracy, the load imped·
ance is determined by the variations expected in
channel resistance. Assuming a system accuracy of
±0.5%, the AM 1000 load resistance cou Id be as
low as 1 kn; the MOS switch load resistance would
have to be 25 kn (±125n being 0.5% of 25 kn).
A National LH0033 high speed buffer was used
to sense the analog voltage at the load resistor of
the MOS switch and drive the analog input of the
AM1000. Figure 6A shows the oscillogram; the
upp~r trace is the MOS switch turning off; its load
voltage heading toward ground; the lower trace
(oscilloscope vertical gain reduced slightly for
photo clarity) shows the AM 1000 sampling this
switching transient. Figure 68 shows the timing
pulses, the upper trace being the MOS drive timing
and the lower is the AM1000 drive timing (posi·
tive indicating off for both devices). It is interesting
to note that the turn·on delay or "aperture time"
of the AM 1000 is primarily caused by the DH0034
translator. Maximum specified turn on time is
100 ns and turn off time is specified at 100 ns for
the AM 1000. Figure 6 shows absolute superiority
of the AM 1000 in switching ability for a given
system accu racy.
AM1000 DRIVE CIRCUITS
Normally, analog switches will be selected by some
digital control means which will usually mean OV
add +5V power supply levels. The AM t 000 needs
a driver capable of handling the full analog voltage
swing, plus 10V. Therefore a circuit known as an
analog switch translator is normally requried. There
are several types available. All of the following
circuits feature "break before make" action which
is desirable for multiplexing.
10·39
III
.
CI)
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(,)
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Ul
til
0
c;
C
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FIGURE 6A. AM 1000 Sampling the Switching Transient of an MOS Analog Switch
«
Off
MOS
ANALOG
SWITCH
ON
OFF
AMI 000
ON
FIGURE
68. Analog Switch Drive Timing
Analog switch translator·drivers fall into two basic
categories. Those with pullups and those without.
If the translator-driver has a pullup, such as the
National DM7800, then a switching diode must be
used to decouple the driver from the AM 1000
when the driver goes positive.
which the AM1000 must charge. Usually this
additional capacitance is not excessive.
on
m
INPUTS
FIGURE 8. Translator-Driver without Pullup
on
m
INPUTS
FIGURE 7. Translator-Driver with Voltage Pullup
The AM 1000 does not requ ire a driver with a pu 11up. Figure 8 shows the circuit for this configuration. Note that the driver decoupling diode is not
required. This configuration eliminates one power
supply but adds the capacitance of the driver
10-40
In some systems, the cost of monolithic or hybrid
drivers is not worth the space they save. Figure 9
shows a four channel driver using low cost discrete
components. The ON channel is selected by binary
coding and is DTL-TTL compatible. If A and B
are "high" then drive is removed from Q 5 allowing
channell AM100l to pull up and turn on. Q6, Q 7
and Q s have drive applied which pull down on
CH2, 3 and 4 thus turning them off. The voltages
. and devices indicated in Figure 9 ,allow ±15V
analog signals to be handled.
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CC
All NPN Transistors - 2N3903
All PNP Transistors - 2N3905
All Diodes -1 N914
(f)
Digital Inputs High for Aand B
DlgltallnplIts Low for Aand B
~
~:
n
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FIGURE 9. Binary Controlled Four Channel Multiplexer
CD
1/1
CURRENT MODE MULTIPLEXING
So far, the discussion of multiplexing circuits has
been confined to sampling various analog input
voltages. Voltage mode analog switching allows
maximum toggle rates but limited voltage range
(±10V for AM 1000, AM1002 and ±15V for
AM100l).
If large analog voltages must be handled, current
mode multiplexing must be used; toggle rate is
reduced because accurate current-voltage converters are not as fast as non-inverting voltage amplifiers. Analog signal loading can also be a problem.
Nevertheless current mode multiplexing allows
sampling of very high analog voltages. This is
accomplished by using scaling resistors and bound
limit diodes at the input of the analog switch.
Also, in this case the current to voltage converter
should be the lowest impedance point in the
system, so the AM 1000 must be "turned around",
so its analog "output" is used for the signal input
and vice versa.
The 10 kSl feedback resistor shown results in 10V
output for 1 mA input. Thus the scal ing resistor at
the input is selected for 1 mA for 100V input, or
10 IlAN. A 1000V analog signal would use a
1 MSl scaling resi!;tor. For lower voltage signals,
the Ron of the AM1000 would have to be ~on·
sidered for precision systems. The bound limit
diodes connected to +10V and -10V prevents
excessive voltage from appearing at the AM1000.
Input impedance to the current to voltage converter is Rt divided by the open loop op amp gain
(5000 for the LH0032); the input impedance
would be 2Sl in Figure 10.
OTHER APPLICATIONS
Analog computer circuits can make good use of
analog switches. A few examples are sample and
hold circuits, reset stabilized circuits, integrator
reset switches, and chopper stabili~~ed amplifiers. 4
Video signal switching can be done with a minimum of switching transients. More unusual appli·
cations such as double sideband suppressed carrier
modulators can be constructed plus double sideband suppressed carrier demodulation and FM
quadrature demodulators. 5
CONCLUSION
Where precision, high speed analog switching is
required, the AM1000 series of analog switches
"rewrites the book."
FIGURE 10. Current Mode Multiplexing
The system sensitivity in Figure 10 is determined
by Rt in the current to voltage converter op amp.
The LH0032 J·FET input op amp is selected
because of its high slew rate and low input current.
Time domain multiplexing can be dramatically
improved in channel capability and/or analog signal
bandwidth capability. Sample and hold circuits can
be improved, chopper stabilized amplifiers can be
improved and virtually any other circuit which
requires precision, high level, high speed analog
switching can be improved.
10-41
BIBLIOGRAPHY
1. Mrazek, Dale "High Speed MaS Commutators"
National Semicondur.tor AN·28.
2. Wollesen, Donald L. "Analog Signal Commutation" National Semiconductor AN·33.
3. Wollesen, Donald L. "Analog Switching - High
Speed with J-FETS" EDN, January 15, 1970.
10·42
4. Cohen, Joel M. "Sample and Hold Circuits Using
FET Analog Gates" EEE, January 1971.
5. Stump, Ronald and Wollesen, Donald, "MaS
Analog Switches" National Semiconductor AN·
38.
6. Gordon, Bernard, "Digital Sampling and Re·
covery of Analog Signals" EEE, May 1970.
Applications
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APPLYING MODERN CLOCK
DRIVERS TO MOS MEMORIES
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0-
INTRODUCTION
CD
MOS memories present unique system and circuit
challenges to the engineer since they require precise timing of input wave forms. Since these inputs
present large capacitive loads to drive circuits, it is
often that timing problems are not discovered
until an entire system is constructed. This paper
covers the practical aspects of using modern clock
drivers in MOS memory systems. Information
includes selection of packages and heat sinks,
power dissipation, rise and fall time considerations,
power supply decoupling, system clock line ringing
and crosstalk, input coupling techniques, and
example calculations. Applications covered include
driving various types shift registers and RAM's
(Random Access Memories) using logical control
as well as other techniques to assure correct
non-overlap of timing waveforms.
The MH0026 is a high speed, low cost, monolithic clock driver intended for applications above
one megacycle. Table II illustrates Its performance
characteristics while its unique circuit design is
presented in Appendix II. Of course the above are
just examples of the many different types that
are commercially available. Other National Semiconductor MOS Interface circuits are listed in
Appendix III.
The following section will hopefully allow the
design engineer to select and apply the best circuit
to his particular application while avoiding common
system problems.
Of course each of us is careful of details but
reminders such as "turn on the power suppl ies"
or "don't reverse supply polarity" sometimes
solve a not-so·obvious problem. This section is
intended to review and answer deSign questions
like "how much should I decouple supplies?"
The MH0025 was the first monolithic clock driver.
It is intended for applications up to one megacycle
where low cost is of prime concern. Table I
illustrates its performance while Appendix I describes its circuit operation. Its monolithic, rather
than hybrid or module construction, was made
possible by a new high vOltage-gold doped process
utilizing a collector sinker to minimize V CE SAT.
Package and Heat Sink Selection
Package type should be selected on power handling
capability, standard size, ease of handling, availability of sockets, ease or type of heat sinking
TABLE I. MH0025 Characteristics
CONDITIONS (v+ - V-I '" l1V
PARAMETER
VALUE
UNIT,)
15
tON
on
30
C L = 000l,uF, Ro = 50n
25
CIN = 0022J.1F, RIN =
tOFF
t,
150
t,
Positive Output Voltage SWing
VIN - V- =
av,
lOUT'" -lmA
Negative Output Voltage SWing
liN = 10mA, lOUT = lmA
On Supply Current (v+)
liN = lOrnA
v+ - 0 7
V- + 1 0
v
17
mA
VALUE
UNITS
TABLE II. MH0026 Characteristics
PARAMETER
CONDITIONS (v+ -
V-I "" 17V
75
ION
tOFF
t,
t,
CIN
=
00lJ.1F, RIN =
on
Ro = 50n, CL = l000pF
Positive Output Voltage SWing
VIN - V- =OV,
Negative Output Voltage Swmg
liN'" lOrnA, lOUT'" lmA
On Supply Current (v+)
liN"" lOrnA
lOUT =
-lmA
75
25
25
V+ -0 7
v
v- + 0.5
28
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PRACTICAL ASPECTS OF USING
MOS CLOCK DRIVERS
Although the information given is generally applicable to any type of driver, two new monolithic
integrated circuit drivers, the MH0025 and MH0026
are selected as examples because of their low cost.
:::l
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mA
10-43
3
o
.
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III
TABLE III. Package Power Ratings
TO·8 Power Rating
MINI DIP Power Ratings
1.2
3.0
,J
- NWITH
iOloEkEO
2.5
2.0
1.5
1.0
=
STILL AIR WITH CLlP·ON
SINK (THERMAllOY
~EAT
TYPE 215 - 1.9 OR EDUIV)
t-....
STlLL~ r--... ~
f'-.,
0.5
25
50
75
0.8
~
0.6
0
iic;
100
125
~
STill;;;;;'"
25
150
z
t.o
0.8
i
06
'"
0'
c;
~
50
75
100
125
150
AMBIENT TEMPERATURE (OC)
TO-5 Power Ratings
0
"'
r-....
0.2
(~C)
Flatpack Power Rating
12
~
PC BolARO
8 CU. CONDUCTORS
20Z 031N WIDE
'" D.'
~
AMBIENT TEMPERATURE
10
~
z
3.0
r- I'-..
~
~Tlll
AIR WITH CLIP
ON HEAT SINK
STIll ;;;;;-
..........
i"-..........
02
25
50
15
100
125
20
~
~
15
~
10
0
'"
~
150
AMBIENT TEMPERATURE (
DM7820/DM8820, DM7820A/DM8820A
.~
DM7830/DM8830
AND
OUTPUT
NAND
OUTPUT
AND
NAND
GND
OUTPUT
OUTPUT
RESPONSE
Q)
a::
-INPUT TERMINATION +INPUT
Vco
14
"
TIME
STROBE
Vco
OUTPUT
12
13
14
12
13
C
IV
.
!II
Q)
>
.~
Q
Q)
c
::i
1ii
.~
-INPUT TERMINATION +INPUT
C
STROBE
GND
OUTPUT
RESPONSE
TIME
NOTE PIN 7 CONNECTED TO BOTTOM OF CAVITY PACKAGE
!Q)
TOP VIEW
TOP VIEW
;:
Q
"
C
IV
DM7833/DM8833
DM7831/DM8831, DM7832/DM8832
!II
::I
m
J9IV
Vo<
"A"OUTPUT
DISABLE
DIFFERENTIAL!
OUTPUT
A,
INPUT
OUTPUT
A,
A,
INPUT
A,
SINGlE·ENDED
MODE CONTROL
Vo<
BUS o
IN,
DUlo
BUSe
IN,
DUTe
DRIVER
DISABLE
BUS e
IN,
OUTe
RECEIVER
GND
Q
M
00
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z
«
"8"OU1'U1
DISABLE
OUTPUT
82
INPUT
82
IN,
OUTPUT INPUT DIFFERENTIAL! GND
8,
B,
SINGLE·ENDED
DISABLE
MODE CONTROL
TOP VIEW
TOPVIEW
DM7835/DM8835
DM7834/DM8834
DRIVER
Vee
BUSo
INo
DUTo
BUSe
INc
BUSA
INA
QUTA
BUS e
INe
DUTe
DRIVER
DUTe
DISABLE
Vee
BUSo
DRIVER
GND
BUS",
INA
DISABLE
TOP VIEW
OUTo
BUSe
OUTA
BUS a
INe
TDPV1EW
FIGURE 1.
10-56
INo
INc
OUTe
DUTe
DISABLE
RECEIVER
DISABLE
GND
z»
DM7836/DM8836
DUll
OUT 4
IN4A
INJA
IN 48
I
DM7837/DM8837
IN 3B
V"
V"
IN 1
OU12
IN2
OUT 1
IN'
00
W
.
OUT 1 DISABLE A
0
I»
I»
14
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0
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....
...
~
GNO
OU12
OUT 1
IN IA
IN 18
IN 2A
IN.
IN 28
OU14
OUTS
IN5
IN'
OUTS
.
DISABLE 8 GNO
~
:1
TOP VIEW
TOP VIEW
i
r-
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~
0...
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DM7839/DM8839
DM7838/DM8838
...III
~
DRIVER
V"
BUS 1
IN 1
OUT 1
BUS2
IN 2
OU12
DISABLE A
OUT
V"
DISABLE
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~
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~
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BUS 3
IN'
OUT J
BUS4
I••
OUH
DISABLE 8 GND
BUS A
IN,
IN,
BUSa
OUT A
OUTs
RECEIVER
GNO
DISABLE
TOP VIEW
TOP VIEW
LM1489/LM1489A
LMl488/LM1588
INPUT
o
V'
14
GNO
"
RESPONSE
CONTROL
OUTPUT
0
0
12
11
INPUT
C
RESPONSE
CONTROL
C
OUTPUT
C
GNO
10
INPUT
RESPONSE
OUTPUT
INPUT
RESPONSE
OUTPUT
A
CONTROL
A
A
B
CONTROL
B
TOP VIEW
,
TOP VIEW
FIGURE 1. (Con'd
10-57
Not much need be said about the EIA RS232C
designs. They meet or exceed a standard wh ich is
below today's attainable performance levels.
UNIFIED BUS
A typical unified bus is a flat, multiconductor
cable interconnecting the CPU and peripherals ot'
a minicomputer (Figure 2). The lines are single·
ended (non·differential), ground-referenced, bidirectional, and terminated at each end in 1200.
to 3.2V. The line level is high except when an
open-collector driver pulls the line low. Drivers
take turns transmitting, as controlled by "polling"
or other control sequences.
Single-ended communications are susceptible to
common mode voltage induced by ground currents
between chassis. In a computer room, the problem
is usually minimized by linking the chassis with
heavy-gauge grounding cables. Communications
with remote points go through differential transmission links, or modems coupled to phone lines.
In early unified bus designs, open-collector TTL
buffers were used as drivers, and standard gates
as receivers. However, the low threshold voltage of
the receiving gate (it can be as low as 1.0V) is too
close to ground potential, which can itself be
carrying transients of almost a volt. In addition,
the gate's input current can be as high as 1.6 mA,
severely limiting the number of receivers which
can be controlled by one driver. This is true
particularly if the driver has an open collector output, and must also be sinking the current from a
1200. termination at each end of the unified bus.
That problem was solved by the SP380 gate. Its
signal input is the base of an NPN emitter-follower,
giving a higher threshold and lower input current.
Unfortunately, the input transistor's collector-base
junction becomes forward-biased when Vcc goes
down. If a peripheral is shut off, the bus lines are
clamped near ground unless the bus cable is
disconnected manually.
The new unified bus designs in Table I have a
receiver that is self-isolating when power is down.
The main bus is still usable if peripherals are
turned off.
Other improvements incluc\e: very low input
current, typically 151.1A whether Vee is 5.0V or
zero; input hysteresis of 1.0V, providing 1.8V
noise immunity; thresholds of 1.3V and 2.3V; and
temperature compensation to keep thresholds and
noise immunity constant.
The DM7836/DM8836 is pin-compatible with the
SP380. Each receiver trio in the DM7837/DM8837
has an enable control, so the system can force
receiver outputs to zero whether the bus is pulled
down or not. The four drivers in the DM7838/
DM8838 transceiver are disabled by a NOR gate
control.
Each open-collector driver in the transceiver sinks
50 mA at 0.7V. It has the power to pull down
the double-terminated bus and drive 20 of the
low-current receivers.
TRI-STATE BUS
TR I-STATE logic (or TSL) outputs are active in
both the "I" and "0" state. This greatly improves
risetimes and allows many more driver/receiver
pairs to be connected to a bus since power is not
wasted in terminations. Switching delays can be
halved during certain data exchanges.
A disabled output switches into a third, highimpedance state. Only small leakage currents flow
in the output in this state, virtually disconnecting
the output from the bus. TSL outputs do not
"wire-O R" - the bus is operated by one set of
outputs at a time.
Figure 3 is a TSL bus line. Although there are no
terminations, reflections are less of a problem than
in a unified bus. The bus is tightly controlled
without terminations because the disabled driverS
actually clamp undershoots.
'lOV
'"
'10
FIGURE 2. Unified Open Collector Bus
10-58
T...
CPU
PERIPHERAL #1
PERIPHERAL #2
PERIPHERAL #N
!~ ~--i-'--~'---+~-~
IL
_ _ _ _ _ JI
1/4DM7833
FIGURE 3. TRI-5TATE Bus
+5IV
"DV
11.
'01
OlD
FIGURE 4. Open Collector Line With Stub
r
FIGURE 5. TRI-5TATE Line With Stub
Tests indicate the transceivers can drive bus lines
longer than 25 feet. They are guaranteed to source
10.4 mA at the minimum "one" level of 2.4V.
Small-signal source impedance is typically 50n
to '5.0V compared with 120n to 3.2V on the
unified bus. That' explains TSL's higher speed the active-pull-up output charges the line capaci·
tance much faster. If even greater source current
capability is needed, the DM7831/DM8831 and
DM7832/DM8832 are available. As quad singleended drivers they can source and sink at least
40 mA' (and have a source impedance of only
lln). They can drive lines with characteristic
impedance down to 40n.
When a peripheral equipped with a transceiver is
powered down or disabled, no current (apart from
microamps of leakage) will, flow in the input/
output while the data levels move between ground
and +5.0V. Other peripherals can still use the bus
without their signals being shunted or degraded.
The receivers are isolated like the unified bus
designs. (The DM7832/DM8832 has the same
degree of freedom. However, the DM7831/DM8831
has an output diode to Vcc to control transients
when used in its differential mode. It will clamp
the bus lines when powered-down, so it is not
recommended for use in a peripheral which might
be switched off in isolation from the rest of the
system).
In the TSL transceiver family, typical receiver
input characteristics are 17J.lA current, 400 mV
hysteresis, and 1.4V noise immunity. All types
are completely compatible with standard TTL.
Figure 4 shows a line with a stub (actually a
branch of equal length, to ease analysis). It is
terminated in the line's characteristic impedance
at all three ends.
Figure 5 shows an identical hook·up, this time
"terminated" only by a disabled TR I·STATE gate
at the receiving end and the stub end.
10·59
The result of driving the circuit of Figure 4 is
seen in Figure 6. The current pulled from the line
by the driver (top trace) was determined by the
effective impedance of the termination in parallel
with the 1200 line charged to 3.2V. When this
wavefront reached the fork, half the current was
drawn from each leg. So when the half-current
front arrives at the stub only half the voltage
pull-down results (Figure 6 lower trace).
A series of these timed halvings and quarterings
produces the bathtub effect shown. The duty
cycle distortion experienced by a receiver at the
stub termination is obvious. If we take off the
stub termination network, the situation gets no
better. Figure 7 shows it (time base and sensitivity
unchanged). The undershoot in the I~wer trace is
followed by an overshoot which reaches 1.0V above
ground: and the stub continues to ring (which
isn't surprising since its two ends have terminations
in 60n and infinity respectively). A receiver at
the end of the stub would have to be ignored
until the ringing had decayed, and its output
had become va lid.
Contrast this with Figure 8, demonstrating the
results of. the TRI-STATE driver of Figure 5. The
same rapid falling edge at the receiving end is
brought to a halt very sharply, and instead of
reflective overshoots, there is a shallow series of
level adjustments which never cross the maximum
zero level of O.4V above ground.
How is this achieved?
Figure 9 shows the schematic of the output' stage
of a TRI-STATE transceiver. Now if the output is
disabled, point A is held by the TRI-STATE control at VCEsat + VBE , or 1.0V at 25°C.
AT TRANSMITTING END
-GNU
-OND
-8ND
-OND
AT RECEIVING END
FIGURE 6. Open Collector Bus With Two Termineted
Stubs 2.0V/div 20 ns/div
FIGURE 7. Open Collector Bus at an Unterminatad Stub
AT TRANSMITTING END
-GND
AT RECEIVING END
-GND
HORIZONTAL: 20 ."DIV
VERTICAL: EXPANDED TO IV/DIV
FIGURE 8. TRI-5TATE@ Bus at a Stub - Oemonstration
of the TSL Non-Linear Termination
10·60
r - - -.....- - - - -..... voo
FIGURE 9. DC Levels in a Disabled TRI-IITATE Element
So to turn on the Darlington pull-up stage will take
an undershoot below ground on the bus line of
2 VBe lower than point A. Or at 25°C, 1.0·-1.6,
= --a.6V., Allowing for a chip temperature somewhat above ambient, the output will begin to
clamp at -O.4V. Figure 10 shows a typical result of
14
12
10
II
06
14
02
logic transmission lines. The ability of the disabled
TSL output to turn on very hard in a precisely
similar way in an otherwise uncontrollable situation
has been conclusively dempnstra~ed.
A further advantage for an unterminated line
appears under certain special conditions of architecture. Figures 11 and 12 compare two test
circuits, simulating two peripherals one on each
.
20
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BUS DRIVER
,
+50V
'"
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FIGURE 10. Current Available as a Function of Bus
Voltage at. Disabled TRI-IITATE Output
a test of pulling current out of a disabled TRISTATE output.
O. A. Horna* has pointed out the effectiveness
of a non-linear termination in emitter-coupled
FIGURE 11. Central Controller in an Open Collector
Environment
'0. A. Horna - "Non-Linear Termination of Transmission Lines" IEEE Transactions on Computers,
Sept. 1972, pp. 1011-1-15.
10-61
f!
CD
,~
side of a CPU, linked by, in the first case an
open collector terminated bus; in the second case
a TRI-STATE bus.
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delays. And the receiver, waiting for data from
the far end, must obviously be ignored until a
safe amount of time after the glitch seen in Figure
13 trace 3 has died down. Contrast this with the
TRI-STATE case shown in Figure 14. The relinquished bus, seeing only extremely low leakage
current, does not move. It may be safely assumed
that very shortly after the changeover, a change on
the line will be a signal being propagated on the
bus.
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TRUE DIFFERENTIAL TRANSMISISON
'i
FIGURE 12. Central Controller in a TRI-STATE
'+=l
c:::
Environment
!!!
In both cases, the bus drivers are holding the bus
in one state, and not switching data during the
experiment.
:!
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Looking at Figure 13, in the open collector case,
relinquishment by one driver and immediate taking
up by the other at the low state still leaves the
termination to pull the bus high for two line
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Often, a zero ground reference can't be establ ished
between remote subsystems. One can overwhelm
the ground difference with a high-amplitude, slngleended transmission. But a differential transmission
not referenced to ground is more efficient (Figure
15). The data is complemented at normal logic
levels, transmitted over a twisted-pair cable, and
received with a comparator sensitive enough to overcome signal degradations, yet rejecting common
mode voltages.
....COCO
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ill
GND
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ill
GND
FIGURE 13. Open Collector Bus Signals With Central
FIGURE 14. TRI-STATE Bus Signals With Central
Controller
Controller
:::~_>CJ(_
FIGURE 15. Differential Drive - Ideal
10-62
r-----------.--.----.--.-- v•
D.
NAND
OUTPUT
.9
07
":"
"::"
V·
06
AND
OUTPUT
0,
FIGURE 16. DM8830 Schematic
We implemented the differential concept several
years ago with the DM7830/DM8830 driver and
DM7820/DM8820 receiver. More recently, the
two TRI-STATE drivers have been used in such
applications. DM7831 output characteristics in the
differential driving mode are shown In Figure 17.
~
30
~~~~~~~~t-
~
20
~~~-p~~~~~
10
~~~~-F~r4~~~
~
~
~
Q
"
" "
'DO
OUTPUT CURRENT (rnA)
FIGURE 17. Differential Output Voltage as a FunctIon of
Differential Output Current in the DM7831
The DM7820 and DM7830 designs were explained
in AN-22. Rather than repeat the information in
that note, the following sections will answer
questions frequently asked by users.
First, how does the new DM7820A differ from the
DM7820? They both have the same schematic.
One of the two receivers on the chip is shown in
Figure 18. However, the "A" version's fanout is
10 TTL or DTL loads rather than 2, the strobe
input is specified fully and is guaranteed to be
driven by saturated logic, and the speeds are
guaranteed.
Second, what establishes the driver current requirement? The receiver's non-inverting input is at the
center of a voltage divider between Vee and
ground. This sets the voltage into the terminal at
1/2 Vee, or 2.5V in a 5.0V system. The smallsignal input impedance is the parallel combination
of the two 5.0 kQ +167Q paths, or about 2.5 kQ.
When the input swings from high to ground, the
current transient is about 1.0 mAo A similar
analysis shows the driver must source about 1/2 mA
to bring the inverting input up to 2.4V.
10-63
~
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RESPONSE-TIME
CONTROL
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170
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TERMINATION
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NOTE SCHEMATIC SHOWS ONE HALF OF UNIT
III
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FIGURE 18. DM7820 Schematic
o
(W)
00
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Point of Failure
To Invert
25 MHz
12MHz
3.2 MHz
0.275 MHz
~+INPUT
~-INPUT
2Ui
___X"-----_
FIGURE 21, Differential Drive Long Distanc.
10-65
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CROSSTALK IMMUNITY
One more question concerns crosstalk in multipair cables_ The tests reported in Table III indicate
that the individual pairs rarely, if ever, need
individual shielding. One shield over all the pairs
in the sheath should be adequate.
en
TABLE III •
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NOISE THRESHOLD AT POINT A
(VOLTS)
LOWER
UPPER
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1.22
1.22
124
1.24
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126
127
1.30
1.30
FREQUENCY
500 kHz
100 kHz
10kHz
1.0 kHz
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DRIVING 7-SEGMENT GAS DISCHARGE DISPLAY
TUBES WITH NATIONAL SEMICONDUCTOR CIRCUITS
CQ
INTRODUCTION
Circuitry for driving high voltage cold cathode
gas discharge 7 ·segment displays, such as Sperry
Information Displays and Burroughs Panaplex II,
is greatly simplified by a complete new line
of monolithic Integrated cirCUits from National
Semiconductor. The new products also make
possible reduced cost of system Implementation.
They are: DM7880/DM8880 high voltage cathode
decoder/driver; DM8884A high voltage cathode
decoder/driver; DM8885 MOS to high voltage
cathode buffer; DM8889 low power cathode
driver; and DM8887 8·digit anode driver.
In addition to satisfying all the displays' parameter
requirements, including high output breakdown
voltage, the new circuits have capability of pro·
grammlng segment current, and provid ing constant
current sinking for the display segments. This
feature alleviates the problem of achieving uni·
formity of brightness with unregulated display
anode voltage. The National circuits can drive the
displays directly.
Sperry Information Displays and Burroughs Pan·
aplex II are used principally in calculators and
digital instruments. These 7·segment, multi·d,git
displays form characters by passing controlled
currents through the appropriate anode/segment
combinations. The cathode in any digit will glow
when a voltage greater than the ionization voltage
is applied between it (the cathode) and the anode
for that digit. In the multiplexed mode of opera·
tion, a digit position is selected by driving the
anode for that digit with a positive voltage pulse.
At the same time, the selected cathode segments
are driven with a negative current pulse. This
causes the potential between the anode and the
selected cathodes to exceed the ionization level,
causing a visible glow discharge.
Generally, these displays exhibit the following
characteristics: low "on" current per segmentfrom 200llA (in DC mode) to 1.2 mA (in multiplex
mode); high tube anode supply voltage-180V to
200V; and moderate Ionization voltage-170V.
Once the element fires, operating voltage drops
to approximately 150V and light output becomes
a direct function of current, which is controlled
by current limiting or current regulating cathode
circuits. Current regulation therefore IS most
desirable since brightness will then be constant
for large anode voltage changes. Tube anode to
cathode "off" voltage is approximately 100V;
and maximum "off" cathode I~akage is 31lA to
51lA.
Correspondingly, specifications for the cathode
driver must be complimentary, approximately as
follows: A high "off" output breakdown voltage
80V minimum; typical "on" output voltage of
5OV; maximum "on" output current of 1.5 mA
per segment; and maximum "off" leakage current
of 31lA to 51lA.
To allow operation without anode voltage regu·
latlon, the cathode driver must be able to sink a
constant current In each output, with the output
1
V,,'5V
1
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90
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120
Z
OUTPUT VOL lAGE (VI
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(b) On Currents vs Temperature
2
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104 r--.--r-,--.--r-'-71
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1-:;<'7
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r--V ~ v:~ =sov
hoi' t---- Rp='D TEMP. COEF
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0.2 mA::; tOUT < 12mA
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20
30
40
50
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(a) Cathode Driver Output Characteristic
T.-25"C
3
CD
641
10
fA (OCI
FIGURE 1.
"on" voltage ranging from 5V to 50V Isee Figure
1). The following IS a brief description of the
Circuits now offered by National:
DM7880/DM8880 High Voltage
Cathode Decoder/Driver
The DM7880/DM8880 offers 7-segment
With high output breakdown voltage
minimum; constant current·sink outputs;
grammable output current from 0.2 mA to
outputs
of 80V
and pro·
1.5 mAo
10·67
power supply voltage IS 5V. The device can be
used for multiplexed or DC operation.
Application
The circuit has a built-in BCD decoder and can
interface directly to Sperry and Panaplex II
displays, minimizing external components (Figure
2). The inputs can be driven by TTL or MaS
outputs directly. It is optimized for use in systems
with 5V supplies.
Available in 16-pin cavity DIP packages, the
DM7880 is guaranteed over the full military
operating temperature range of -55°C to +125°C;
the DM8880 in molded DIP over the industrial
range of O°C to +70°C.
DM8884A High Voltage Cathode Decoder/Driver
'"
The DM8884A offers g·segment outputs with high
output breakdown voltage of 80V minimum;
constant current-sink outputs, programmable from
0.2 mA to 1.2 mAo It also offers input negative
and positive voltage clamp diodes for DC restoring,
and low input load current of -0.25 mA maximum.
(+110-200VDC)
Application
DECODER/DRIVER
...c
CD
E
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....I
FIGURE 2. DC Operation From TTL
The DM7880/DM8880 decoder/driver provides for
unconditiOnal as well as leading and trailing zero
blanking. It utilizes negative input voltage clamp
diodes. Typically, output current varies only 1%
for output voltage changes of 3V to 50V. Operating
DM8884A decodes four lines of BCD input and
drives 7 -segment digits of gas-filled displays. There
are two separate inputs and two additional outputs
for direct control of decimal POint and comma
cathodes. The inputs can be DC coupled to TTL
(Figure 3) or MaS outputs (Figure 4). or ACcoupled to TTL or MaS outputs (Figure 5) using
only a capacitor. This means the device is useful
in applications where level shifting is required. It
can be used In multiplexed operation, and is
available in an 18-pin molded DIP package.
Other advantages of the DM8884A are: typical
output current variation of 1% for output voltage
changes of 3V to 50V; and operating power supply
Cl
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FI GURE 7. Peak Detector
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BCD
R4
A:~~o-+-_--+---I~~---+---++-----1r----O
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FIGURE 8. High Speed 3·bit A to D Converter
10·75
-u
-11V
FIGURE 9. Direct Interfacing to EeL
R4
V~(~_
R2
VUT
(~) -
VOL
(ii)
V~ (~) -
VOM
(~)
= VOH
V" •
FIGURE 10. Level Detactorwith Hysterllis
10·76
Applications
DRIVING 7-SEGMENT LED DISPLAYS WITH
NATIONAL SEMICONDUCTOR CIRCUITS
INTRODUCTION
There are many different information display
technologies available today, including liquid
crystals, gas-discharge tubes, fluorescent tubes,
Incandescent lamps, and light emitting diodes
(LEDs)_ Each technology has its own particular
drive requirement_ This note will focus on 7segment LED display drive requirements and
demonstrate that National Semiconductor has
a full line of display drivers that meet the
requirements for most any 7-segment LED drive
appl ication_
2. Non-decoding, direct drive (MOS to 7-segment)
DM75491
DM8864
DM75492
DM8865
DM8861
DM8866
DM8863
Thus, Nationat,has circuits that will drive 7-segment
LEDs from either fully decoded circuits or from
non-decoded outputs.
CONFIGURATIONS AND CONSTRUCTION OF
7-SEGMENT LEDs
WHY ARE LED DRIVERS NEEDED?
The purpose of 7-segment LED drivers is to act
as an interface element between data input and'
the display. This interface is necessary when either
the input data format or circuitry current capabilIties do not allow direct connection between input
and display. To satisfy these needs, National's
7-segment LED drivers are divided into two basic
categories.
1. Internally decoded (BCD to 7-segment)
DM5446A/DM7446A
DM5447 A/DM7447 A
DM5448/DM7448
DM7856/DM8856
DM8857
DM 7858/DM 8858
LEDs are segregated into two groupings with
regard to construction, see Figure 1.
Common anode displays are constructed on a
common substrate which forms the anode of the
diodes, while each of the seven cathodes are
bonded out to separate pins. The second type,
common cathode, has the cathode fabricated on
a common substrate with the anodes bonded out
to individual pins_ Due to these radically different
'configurations, drive circuits are usually tailored
in their design for one or the other type, Tailoring
in this respect means either sinking current (active
low) or sourcing current (active high) when referenced to segment drive. I n addition, drive
requirements are quite variable because of LED
light intensity requirements as well as digit size
COMMON CATHODE
COMMON ANODE
SEPARATE
ANODES
(SEGMENT
ENABLE)
SOURCE
rttn=~
SINKDbt=-J
CURRENT
COMMON CATHODE
(DIGIT ENABLE)
COMMON ANOOE
·'Tlft
\
SEPARATE
CATHODES
I
I~SINKSEGMENT
CURRENT
(SEGMENT
ENABLE)
FIGURE 1. 7-Segment L,ED Construction
10-17
COWJIONSEGMENT
LIIilES
'y y •••
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-- - , r - - -- -,
...
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-
II ~ ~
I I ~,
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II
II
I I __
_ _ ":".JI IL _ _ _ _ _ .JL
DIGIT
DIGIT
1
2
_ _ _ .JI
DIGIT
3
FIGURE 2. Multi·Digit 7-Sagmant LED
,"
SEGMEfIIT ENABLE
LINES
BCD TO l.s£GMENT
DECODER DRIVER
STROBED
BCD
DATA
LOGIC
(INCLUDING
MULTIPLEXING
CIRCUITRYI
CLOCK>---....
COUNTER
DIGIT ENABLE
LINES
FIGURE 3. A Typical Multiplexing Scheme
and efficiency. Thus the system designer needs a
degree of latitude not only with respect to the
type of display used but also the drive current
available.
7·segment LEDs can be purchased in either single
or multi-digit display packages. Single digit displays
have individual segment and common pins while
multi-digits have paralleled segment pins and
separate digit pins equal to the number of digits
in the package, see Figure 2.
Multi·digit displays, due to their configuration,
must be driven in a multiplex mode of drive, where
segment drivers are time shared by all the digits.
This is contrasted to the single digit displays which
10·78
may be driven in either the multiplex or the nonmultiplex (direct drive) mode. The ,nonmultiplex
mode uses separate segment drivers for each digit
of the display. Multiplex operation has a decided
cost saving advantage over nonmultiplex operation
especially when the number of digits being driven
is large.
MODES OF 7-SEGMENT LED DRIVE
In the multiplex mode of drive the LED digits
in a multi-digit format are driven by a single set
of segment drivers while each digit is selected by
its own digit driver. Figure 3 shows the circuitry
needed to implement a typical six digit multiplexed
display.
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Each digit is selected individually by enabling its
digit driver whose control is determ ined by a
counter or equivalent circuitry operating at some
clock frequency. Strobed data, by way of the
counter and multiplex circuitry, is then displayed
on the selected digit by the single set of segment
drivers. If the strobe rate is high enough, from
about 250 to 1,000 .Hz depending on external
conditions, the display will appear flicker free to
the human eye. The BCD·to·7·segment decoder
converts BCD data to the desired 7·segment output
format.
In summary, LED driver requirements for multiplex or nonmultiplex drive operation require
either segment, digit or BCD to 7-segment drivers.
Analysis of the particular system needs with
regard to the number of digits and relative circuit
costs should be the determining factor for multiplex or nonmultiplex operation. Circuit requirements for multiplex operation will in general
require relatively high current capabilities.
In the multiplex mode each digit has a reduced
duty cycle and is operated at somewhat higher
than average or typical dc operating current levels.
The amount of current will be a function of the
number of digits, duty cycle, and the type
and efficiency of the display used. Since currents
are higher than average so also will be the LED
brightness due to the nearly linear brightness
versus current curve for most LEDs. The human
eye will detect the brightness peaks and through a
partially integrating and peak detecting action will
perceive a higher display brightness at some average
current level in the multiplex mode than the same
average current in the nonmultiplex (direct drive)
mode. The result is that a multiplexed display will
operate at a lower total power than the same
display operated in the nonmultiplex mode with
the same apparent brightness.
Table I lists the 7-segment LED drivers available
from National. Each circuits application is divided
into groupings with respect to common anode or
cathode, digit or segment, multiplex or nonmultiplex areas. Additionally, current capabilities are
also specified for each product.
In the nonmultiplex mode of 7·segment LED drive
each digit has its own set of segment drivers
thereby dropping the digit driver select require·
ment of multiplexed operation. In this case, the
common digit pin may be tied to the highest
potential if common anode or the lowest if
common cathode. It is evident that in a nonmultiplexed display the driver package count
would be high since each digit requires its own
set of segment and possibly decoder drivers.
If a large number of digits are used the segment
driver package count wou Id equal the number of
digits while in the multiplex mode this count
is equal to one. Granted, in the multiplex mode
additional control circuitry is required. Consideration of the relative cost of this circuitry in
comparison to the segment decoder driver circuitry
in the nonmultiplex mode results, in general, in
the fact that if the number of digits in the display
equals or is more than four, total package count
and/or cost is less in the multiplex mode of drive.
In most MOS circuits multiplex operation is ideal
since the counter, multiplexer, and BCD to 7segment decoders or equivalent circuitry can
usually be incorporated on the same chip along
with calculator, clock or other function. In this
case the only external interface components
required would be the digit and segment drivers
since MOS circuits are generally unable to sink
or source the higher current required for most
multiplex operations.
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NATIONAL'S 7-SEGMENT LED DRIVERS
3
From the table it is evident that some of the
circuits may be used in dual roles - both multiplex
or nonmultiplex; common cathode or anode. In
general, what will determine whether one drivers
application is multiplex or nonmultiplex is that
drivers current capability. The direction of current
flow through the driver (source or sink) is the
determining factor in dual application with regard
to common anode or cathode.
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Table II lists the operating temperature range and
package types for the 7-segment LED drivers.
In the following sections each circuit is described
in greater detail and typical applications are
given.
BCD TO 7·SEGMENT DECODER DRIVERS
DM5446A/DM7446A,DM5447A/DM7447A,
DM5448/DM7448
This family of BCD to 7-segment decoder drivers
was designed for the most general possible display drive appl ications including display technologies other than LEDs. The difference between
the circuits is in their output stage configurations.
These differences wi II be discussed separately later.
The circuits convert the standard 4-bit BCD input
to the popular 7-segment output format. All
input BCD codes above 9 are decoded into unique
patterns that verify operation. The circuits are
TTL-DTL compatible and operate off of a single
5.0V supply.
Added features included in all circuits are a ripple
blanking input pin as well as a lamp test pin for
display turn on. In addition the blanking input/
ripple blanking output pin may be used to modulate display intensity ..
10-79
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TABLE I. National7-Segment LED Driver.
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DEVICE
NUMBER
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COMMON CATHODE
Multiplex
COMMON ANODE
Nonmultlplex
DIGIT
SEGMENT
DRIVER
DRIVER
INTERNAL
DECODING
X
X
X
X-
X
X
Multlplex
Nonmultlplex
X
X'
OM 5446A1DM 7446A
X
1 3 rnA Source, Adjustable
Externally, TTL Input
C
Compatibility
C
DM7856/DM8856
...I
OM8857
X
DM7858/DM8858
X
X-
X-
X
X
60 rnA TYPical Source, TTL
Input ~ompatlbility
X
X
X
50 rnA TYPical Source, ExtE'rnally Adjustable, TTL Input
Compatibility
X
X
X
X
W
....
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Adjustable Source Current 0 to
50 rnA, TTL Input Compatibility
patlbility
en
OM75491
X
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OM75492
X
DM8861
X
DM8863
X
X
X
X
50 rnA Source/Sink, 4 Drivers
per Package, MOS Input Compatibility
X
X
X
X"
250 rnA Sink, 6 Drivers per
~ackage, MOS Input Compatibility
X
X
X
X
50 mA Source/Sink, 5 Drivers per
Package, MOS Input Compatibility
X
X
X
X
X"
500 mA Sink, 8 Drivers per Package,
MOS Input Compatibility
DM8864
X
X
X
X
X--
50 mA SlI1k, 9 'DrIVers per Package,
MaS Input Compatibility
DM8865
X
X
X
X
X--
50 rnA Sink, 8 DrIVers per Package,
MaS Input Compatibility
DM8866
X
X
X
X
X"
50 rnA Sink, 7 Dnvers per Package,
MaS Input Compatibility
X
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AND FEATURES
Up to 40 rnA Sink, Open Collector
High Breakdown (30/15V)
TTL Input Compatibility
DM5~47A/DM7447A
OM5448/0M7448
CURRENT CAPASI LlTY
X
*Wlth the use of an external transistor/segment
HFor common anode LED's
TABLE
II.
Operating Temperature Range and Package Type
OP~RATING
DEVICE
NUMBER OF PINS
Ti;MPERATURE RANGE
PACKAGE TYPE
NUMBER
O°C to +70°C
DM8857
X
DM8858
X
Flat Pack
DIP IJI
IWI
X
X
X
X
X
X
DM7858
Ceramic
DIP INI
X
X
X
X
Plastic Molded
X
X'
DM8856
18
X
X
DM7856
16
X
X
DM5448
DM7448
14
X
DM5446A,DM5447A
DM7446A, DM7447A
~55°C to +12SoC
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X,
X
X
X
X
X
DM75491
X
X
X
X
X
DM75492
X
X
X
X
X
D~8861
X
X
X
DM8863
X
X
X
OM8865
X
X
X
DM8866
X
X
X
DM8864
X
10-80
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X
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DM5446A1OM1446A
DM5447AlDNll447A
DM50\48/tlM7448
DM18SS/DM8856
FIGURE 4a. Output Stage
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FIGURE 4b. Output Stage
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BCD
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THE FOLLOWING EQUATION MAY BE USED TO DETERMINE THE APPROPRIATE VALUE OF
Rx (SEGMENT CURRENT liMIT RESISTOR) FOR SOME LED CURRENTISEGMENT Is (mAl.
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Rx" Vee: - 0;: - VlED (@ Is) kn
Os
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40 mAl
!II
WHERE VlED (@ lsi IS THE DIODE (LED) VOLTAGE DROP AT OPERATING CURRENT Is
EXAMPLE:
Is=20mA
VLED (@ lsi" 3.4V*
Vee" 5.0V
Rx " 65.11
*MAN-, OR EQUIVALENT
FIGURE 5. Nonmultiplex Application of the OM7447A
DM5446A/DM7446A, DM5447 A/DM7447 A
These circuits feature active-low, open collector
high current outputs (Figure 4a). Each output is
capable of sinking up to 40 mA at a maximum
internal drop of OAV. This high current capability
makes these circuits particularly well suited for
driving the large MAN-lor equivalent type displays
directly. The circuits are also applicable, with or
without the use of external current limit resistors,
to driving lower current displays in the multiplex
mode of drive.
The DM5446A and DM7446A outputs are capable
of withstanding 30V at a maximum leakage of
250MA over temperature. The DM5447A and
DM7447 A have a 15V output capability at a
maximum leakage over temperature of 250MA.
This standoff voltage ability makes the circuits
applicable for direct drive to indicator lamp type
displays. Figure 5 shows a typical application of
the circuits with LEDs.
Refer to Table II for the operating temperature
range and package types for the DM5446A/
DM7446A and DM5447A/DM7447A.
DM5448/DM7448
The DM5448/DM7448 has active high passive
pull-up outputs (Figure 4b) with a TTL fanout of
4. The typical output source current is 2.0 mA at
an output voltage of 0.85V. Each output is
capable of sinking 604 mA with a maximum'
internal drop of OAV. Since the output current
level is low the circuit can be used to drive low
current common cathode displays operating in the
nonmultipiex mode.
The major application of the DM5448/DM7448
is to drive logic circuits, operate high-voltage
loads such as electroluminescent displays through
buffer transistors or SCR switches. or high-current
10-81
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BCD { B
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't------t--1rt--t--f
6 DM1448101-----t--1r-t-i
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"I-----t-t
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"t-----t--1rt--t--+--+--t
SEGMENT
DESIGNATION
DECIMAL
INPUT
is
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Rx MAY BE CALCULATED USING THE FOLLOWING EOUATION
~
Rx'" 5.0-VLED kn
Is -l.6
E
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",.2:!....
kn
Is-1.6
[VL£D=1.7V@5,DmAj
~x :26500
WHERE:
Rx '" PULL·UP RESISTOR VALUE
I
Is'" CURRENT PER SEGMENT IN mA
.....
~
EXAMPLE:
Is '" 5.0 rnA
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Rx '"' 970,0
Q
FIGURE 6.
No~multiplex
Application of the DM74<18
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loads through buffer transistors. Figure 6 shows
the DM7448 in a low current direct drive LED
application.
The operating temperature range and package
types for the DM5448/DM7448 are given in
Table II.
BCD TO 7·SEGMENT LED DRIVERS
DM7856/DM8856, DM8857, DM7858/DM8858
This series of three circuits was designed'to pro·
vide a wide range of current capabilities'in driving
common cathode 7·segment LEOs operating in the
multiplex or nonmultiplex mode. The circuits,
discussed individually below, have output stages
with varying source current capability designed
for specific as well as general applications.
All circuits accept 4·bit BCD and decode this input
to the desired 7·segment output format for direct
drive to LEDs. In addition, the circu its feature a
lamp test pin for display turn·on check, ripple
blanking·input pin and blanking input/ripple
blanking output pin which may be used to
modulate display intensity.
The three circuits are TTL·DTL compatible and
provide full decoding of the 16 possible input
combinations. All parts operate off of a single
5.0V supply.
source current of 6.0 mA at an output voltage of
1.7V. This current level was designed for directly
driving, without the use of external current limit
resistors, the MAN·4 or equivalent type displays in
the nonmultiplex mode of operation.
j:ach output has a fan·out of 4 and is capable of
sinking 6.4 mA with a maximum internal drop of
O.4V making the circuit suitable for use with logic
circuits. With the use of an external buffer tran·
sistor per output the circuit may be used to drive
high current common anode LED displays as well
as high voltage electroluminescent displays. Figure
7 shows a typical application of the DM8856.
Vee sov
m
BI/RBO
DECIMAL
POINT
DM7856/DM8856
The DM7856/DM8856 output stages, passive·
pullup (active high, Figure 4b), provide a typical
10·82
FIGURE 7. Nonmultiplex Application of the DM8856
»2
Operating temperature range and package types
for the DM7856/DM8856 are given in Table II.
Table II gives the operating temperature range and
package type for the DM8857.
DM8857
DM7858/DM8858
The output stages of the DM8857, active pull-up
(active-high, Figure 4c), source a typical current
The DM7858/DM8858 output stages are active
pull-up (active-high, Figure 4d) like those of the
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FIGURE 4c_ Output Stage
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FIGURE 4d. Output Stage
~
of 50 mA at an output voltage of 2_3V _ The
circuit was designed to be used with MAN-4 or
equivalent type displays operating in the multiplex
mode of drive_ With this high current capability
the circuit can drive up to 16 such digits_
DM8857. The output stages are exactly the same
as the DM8857 except that the internal current
limit resistor per output has been removed.
External current limit resistors must then be used.
This allows the circuit to be customized for a
particular common cathode multiplex or nonmultiplex application. Each output stage, through
its own external resistor, can be programmed to
some current from 50 mA down to 0 mAo Care
must be taken in not shorting the outputs to
ground because of the excessive current flow that
would result from the Darlington upper stage. See
Figure 9 for a typical application of the DM8858.
The applications of this circuit obviously are not
limited to just the MAN-4 type of display. Common
cathode displays with high dc current requirements or lower multiplex current levels may be
driven by this circuit with the use of an external
current limit resistor per segment. A typical application of the DM8857 is given in Figure 8.
DM8857 Output Current
vs Voltage
60
DMB867
Vee '" 5.0V
TA = 2lre
VLT :O.8V
50
40
C-
oS
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30
2D
10
o
1.5
STROBE
20
2.5
3.0
35
4.0
VOUT (V)
INPUT
FOR MULTIPLEX OR NONMULTlPtEX APPLICATIONS WHERE AN EXTERNAL CURRENT
LIMIT RESISTOR PER SEGMENT IS REQUIRED SEE THE OUTPUT CURRENT VS VOLTAGE
CURVE FOR THE DM8857 AND USE THE EOUATION GIVEN IN FIGURE 9 TO CALCULATE
THE RESISTOR VALUE
FIGURE 8. DM8857 Typical Multiplexing Scheme
10·83
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Maximum output source current per segment for
the DM7858/DM8858 is 50 mAo Operating tem·
perature range and package types are given in
Table II.
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Special care must be taken in the use of the
DM7858 ceramic and the DM8858, plastic DIP's
with regard to not exceeding the maximum operating junction temperature of the devices, The maximum junction temperature of the DM7858J is
1500 e and must be derated based on a thermal
resistance of 80o e/Watt, junction to ambient. The
maximum junction temperature for the DM8858N
is 1500 e and must be derated based on a thermal
resistance of 140o e/Watt, junction to ambient.
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low input current, 3.3 mA maximum at 10V
input, making them suitable for direct drive from
MOS circuits. The circuits are used to drive the
paralleled segments in multi·digit displays. Since
both circuits feature accessable collectors and
emitters they may be used as either common
cathode or anode segment drivers. They feature a
source or sink current capability of up to 50 mA
with a maximum collector to emitter drop of
1.5V over the operating temperature ran'ge. In
addition, each output is specified to have a maximum leakage of 100llA at an output voltage of
10V over temperature. Both circuits operate from
a single supply that can have a maximum voltage
of 10V,
DM75491 FOUR SEGMENT DRIVER
DM75491, DM8861 MOS TO LED SEGMENT
DRIVERS
The DM75491 and DM8861 were designed for
MOS calculator applications. Both circuits feature
The DM75491 is a four segment driver whose main
application is with multi·digit LEDs operating in
the multiplex mode of drive. Each package con·
tains four separate segment drivers, each driver
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DM8858 Output Current
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vs Voltage
BCD
INPUTS
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MM5738
NSN98A
LED DISPLAY
DM8864
MO'
CALCULATOR
CIRCUIT
f!--
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FIRST DIGIT
FIRST DIGIT
r-
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FIGURE 13. A Typical Application of the DM8864, Showing a Complete 8-Digit,
5 Function Calculator with Memory.
10-88
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Appl ications
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TRANSMISSION LINE CHARACTERISTICS
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INTRODUCTION
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Digital systems generally require the transmission of
digital signals to and from other elements of the system.
The component wavelengths of the digital signals will
usually be shorter than the electrical length of the cable
used to connect the subsystems together and, therefore,
the cables should be treated as a transmissions line. In
addition, the digital signal is usually exposed to hostile
electrical noise source which will require more noise
immunity then required in the individual subsystems
environment.
The requirements for transmission line techniques and
noise immunity are recognized by the designers of subsystems and systems, but the solution used vary con·
siderably. Two widely used example methods of the
solution are shown in Figure 1. The two methods
UNBALANCED METHOD
5V
120
switching transients from actuating devices of neighboring control systems. Also external to a specific subsystem, another subsystem may have a·ground problem
which will induce noise on the system, as indicated in
Figure 2.
ELECTR:C~
MOTO~
"
INDUCED NOISE ALONG CABLE ROUTE
GROUND PROBLEMS IN ASSOCIATED EQUIPMENT
FIGURE 2. External Noise Source.
BALANCED METHOD
DM1830
The signals in adjacent wires inside a cable may induce
electromagnetic noise on other wires in the cable. The
induced electromagnetic noise is worse when a line terminated at one end of the cable is near to a driver at the
same end, as shown in Figure 3. Some noise may be
6~"ik>FIGURE 1.
illustrated use unbalanced and balanced circuit techniques. This application note will delineate the characteristics of digital signals in transmission lines and
characteristics of the line that effect the quality, and will
compare the unbalanced and balanced circuits performance in digital systems.
FIGURE 3. Internal Noise Sou ......
NOISE
The cables used to transmit digital signals external to a
subsystem and in route between the subsystem, are
exposed to external electromagnetic noise caused by
induced from relay circuits which have very large transient voltage swings compared to the digital signals in the
same cable. Another source of induced noise is current
in the common ground wire or wires in the cable.
10-89
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DISTORTION
The objective is the transmission and recovery of digital
intelligence between subsystems, and to this end, the
characteristics of the data recovered must resemble the
data transmitted. In Figure 4 there is a difference in the
pulse width of the data and timing signal transmitted,
and the corresponding signal received. In addition there
is a further difference in the signal when the data is
"ANO"ed with the timing signal. The distortion of the
signal occurred in the transmission line and in the line
driver and receiver.
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TRANSMITTED
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TIMING.J
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The rise time in a transmission line is not an exponential
function but' a complementary error function. The high
frequency components of the step input are attenuated
and delayed more than the low frequency components.
This attenuation is inversely proportional to the fre·
quency. Notice in Figure 6 particularly that the signal
takes much longer to reach its final dc value. This effect
is more significant for fast risetimes.
The Outy Cycle of the transmitted signal also causes
distortion. The effect is related to the signal rise time as
shown in Figure 7. The signal doesn't reach one logic
level before the signal changes to another level. If the
signal has a 112 (50%) Outy Cycle and the threshold of
the receiver is halfway between the logic levels, the distortion is small. But if the Outy Cycle is 1/8 as shown in
the second case the signal is considerably distorted. In
some cases, the signal may not reach the r~ceiver threshold at all.
RECEIVED-.1l
po
DATA
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RECEIVED
TIMING
RECDVERED
DATA
~----
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-1 LJ L-J L-J L-J L
•
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---.J
112 DUTY CYCLE
A. A-A.-~_.A. /
V
X V ---v-v- VTH
----
LINE RESPONSE'
FIGURE 4. Effect of Distortion
IIBOUTY
A primary cause of distortion is the effeCt the transm is·
sion line has on the rise time of the transmitted data.
Figure 5 shows what happens to a voltage step from the
driver as it travels down the line. The rise time of the
signal increases as the signal travels down the line. This
effect will tend to affect the timing of the recovered
signal.
h h h h h
U U U LJ L
112 DUTY
CYCLE DATA.J
nL-----JnL
CYCLE DATA..J
1/8 DUTY CYCLE
LINE RESPONSE
VTH
..... ____ _
FIGURE 7. Signal Distortion Due to Duty Cycle
In the previous example, it was assumed that the
threshold of the receiver was halfway between the ONE
and ZERO logic levels. If the receiver threshold isn't
halfway the receiver will contribute to the distortion of
the recovered signal. As shown in Figure 8, the pulse
time is lengthened or shortened, depending on the
polarity of the signal at the receiver. This is due to the
offset of the receiver threshold.
r-l~
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DRIVER
INPUT--.J
FIGURE 5. Signal Response at Receiver
'x U
=-.J'...I . . . . _.
r--l~
POSITIVE PULSE
RECEIVER
OUTPUT---.J
1_.-0:
I-"'~
RECEIVER
OUTPUT
THE STEP RESPONSE OF A TRANSMISSIDN
LINE RESEMBLES A COMPLIMENTARY
ERROR FUNCTION RATHER THAN AN
EXPONENTIAL FUNCTION
TIME
FIGURE 8. Signel Rise Tim.
10·90
Z
example that the losses reduce the signal below the
threshold of the receiver in the unbalanced method. Also
that part of the I R drop in the ground wire is common
to other circuits-this ground signal will appear as a
source of noise to the other unbalanced line receivers in
the system.
I
....
o
termination until it reaches its final dc value. In both the
rise and fall time diagrams, there are transient voltage
and current signals that subtract from the particular
signal and add to the system noise.
CO
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en
3
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120
LM75452
r----'
I
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30
I
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I
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C-,
o:r
.
.......
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40 mA
30
L.. ____......J;.....\JV"""--1:+----:-.....t-~-.....- ....-..J
":"
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n
FIGURE 11. Line Reflection Diagram of Rise Time
GR3Vl
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IR DROP SUBTRACTS
(ii'
FROM NOISE MARGIN
IR DROP GENERATES
GROUND lOOP NOISE
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FIGURE 9. Unbalanced Method
Transmission lines don't necessarily have to be perfectly
terminated at both ends, (as will be shown later) but the
termination used in the unbalanced method will cause
additional distortion. Figure 10 shows the signal on the
transmission line at the driver and at the receiver. In this
case the receiver was terminated in 120£2, but the char·
acteristic impedance of the line is much less. Notice that
the wave forms have significant steps due to the
incorrect termination of the line. The signal is subject to
misinterpretation by the line receiver during the period
of this signal transient because of the distortion caused
by Duty Cycle and attenuation. In addition, the noise
margin of the sighal is reduced.
-
AT DRIVER
-
BALANCED METHOD
I
r
I
PAIR SHIELDED
In the balanced method shown in Figure 13, the transient voltages and currents on the line are equal and
2V/DIV
AT RECEIVER
100 FT TWISTED
FIGURE 12. Line Reflection Diagram of Fall Time
OM7830
I
-
30
,---=:>
200 nsiDIV
170
FIGURE 10. LM75451. DM7400 Line Voltage Waveforms
30
The signal waveforms on the transmission line can be
estimated before hand by a reflection diagram. Figure 11
shows the reflection diagram of the rise time wave
forms. The voltage versus current plot on left is used to
predict the transient rise time of the signal shown on the
right. The initial condition on the transmission line is an
I R drop across the line termination. The first transient
on the line traverses from this initial point to zero cur·
rent. The path it follows corresponds to the characteristic impedance of the line. The second transient on the
diagram is at the line termination. As shown, the signal
reflects back and forth until it reaches its final dc value.
Figure 12 shows the reflection diagram of the fall time_
Again the signal reflects back and forth between the line
30
INPUT
BALANCED LINE SIGNAL
OUTPUT
THE GROUNO lOOP CURRENT IS MUCH LESS THAN SIGNAL CURRENT
FIGURE 13. Cross Talk of Signals
opposite and cancel each others noise. Also unlike the
unbalanced method, they generate very little ground
noise. As a result, the balanced circuit doesn't contribute
to the noise pollution of its environment.
10-91
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ca
ca
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The circuit used for a line receiver in the balanced
method is a differential amplifier. Figure 14 shows a noise
transient induced equally on line A and line B from line
C. Because the signals on line A and B are equal, the
signals are ignored by the differential line receiver.
Likewise for the same reason, the differential signals on
line A&B from the driver will not induce transients on
line C. Thus, the balanced method doesn't generate noise
and also isn't susceptible to noise. On the other hand
the unbalanced method is more sensitive to noise and
also generates more noise.
an unbalance reflection at the terminator. Therefore, the
lines should alsQ be terminated for unbalanced signals.
Figure 16 shows the perfect termination configuration
of a balanced transmission line. This termination method
is primarily required for accurate impedance measure·
ments.
UNBALANCED
III
BALANCED
E
III
C
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FIGURE 16. Impedance Measurement
SIGNAL ON LINE A
SIGNAL ON LINE 8
~
~
DIFFERENCE SIGNAL (A-Bi _ _ _ _~_...~
The unbalanced method circuit used in this application
note up to this point is the unbalanced circuit shown in
Figure 1. The termination of its transmission line was
greater than the characteristic impedance of the unbal·
anced line and the circuit had considerable threshold
offset. The measured performance of the unbalanced cir·
cuit wasn't comparable to the balanced method. There·
fore, for the following comparison of unbalanced and
balanced circuits, an improved termination shown in
Figure 17 will be used. This circuit terminates the line in
60n and minimized the receiver threshold offset.
FIGURE 14. Cross Talk of Signals
The characteristic impedance of the unbalanced trans·
mission line is less than the impedance of the balanced
transmission line. In the unbalanced method there is
more capacitance and less inductance than in the bal·
anced method. I n the balance method the Reactance to
adjacent wires is almost cancelled (see Figure 15). As a
result a transmission line may have a 60n unbalanced
impedance and a 90n balanced impedance. This means
that the unbalanced method, which is more susceptible
to I R drop, must use a smaller value termination, which
will further increase the I R drop in the line.
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000/\
0000
00000
0000
000
,~
Zo
FIGURE 15.
.COAX
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FIGURE 17. Improved Unbalanced Method
A plot of the Absolute Maximum Data Rate versus cable
type is shown in Figure 18. The graph shows the dif·
ferent performances of the DM7820A line receiver and
s.,
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100
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276
a
20=-logVI b
000
000.0
00000
0000
000
Zo Unbalanced < Zo Balanced
The impedance measurement of an unbalance and balance
line must be made differently. The balanced impedance
must be measured with a balanced signal. If there is any
unbalance in the signal on the balanced line, there will be
10·92
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SINGL~±H±t
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SINGLE TWISTED
PAIR SHIELDED
"'"x
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ALL WIRE #22
AWG STRANDED
DM7820AlDM7830
1'8 DUTY CYCLE
"'"
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1.0
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II
100
1000
LINE LENGTH (FTI
FIGURE 18. Oata Rate vs Cable Type
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PAIR SHIELDED
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DM1820AIDMlI30
NINE TWISTED PAIR
Zo BALANCED ,9,~?
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112 DUTY CYCLE
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LINE LENGTH (Fn
FIGURE 19. Data Rate .5 Duty Cvcle
O·
10
;::,
1000
100
10
LINE TERMINATION RESISTANCE (OHMS)
10
1000
!::
LINE LENGTH IFn
FIGURE 20. Data Rate.s Line Termination
the DM7830 line driver circuits with a worse case 1/8
Duty Cycle in no. 22 AWG stranded wire cables. In a
single twisted pair cable there is less reactance than
in a cable having nine twisted pairs and in turn this
cable has less reactance than shielded pairs. The line
length is reduced in proportion to the increased line
attenuation which is proportional to the line reactance.
The plot shows that the reactance and attenuation has a
significant effect on the cable length. Absolute Maxi·
mum Data Rate is defined as the Data Rate at which the
output of the line receiver is starting to be degraded. The
roll off of the performance above 20 mega baud is due
to the circuit switching response limitation.
100
FIGURE 21. Data Rate YS Distorion of
LM75452, DM7400
is the percentage difference in the pulse width of the
data sent versus the data received.
Data Rate versus the Line Length for various percentage
of timing distorition using the balanced DM7820A and
DM7830 circuit is shown in Figure 22. The distortion of
this method is improved over the unbalanced method, as
was previously theorized.
The Absolute Maximum Data Rate versus Line Lengths
shown in the previous two figures didn't include any
induced signal noise. Figure 23 shows the test configura·
tion of the unbalanced circuits which was used to
5V
Figure 19 shows the reduction in Data Rate caused by
Duty Cycle. It can be observed that the Absolute Maxi·
mum Duty Rate of 118 Duty Cycle is less than 112 Duty
Cycle. The following performance curves will use 1/8
Duty Cycle since it is the worst case.
Absolute Maximum Duty Rate versus the Line
Termination Resistance for two different lengths of
cable is shown in Figure 20. It can be seen from the
figure that the termination doesn't have to be perfect in
~he case of balanced circuits. It is better to have a termi·
nation resistor to minimize the extra transient signal
reflecting between the ends of the line. The reason the
Data Rate increases with increased Termination Resist·
ance is that there is less I R drop in the cable.
100
t---t:I------l11
100
5V
150
II
100
5V
'50
The graphs in Figure 21 shows the Data Rate versus the
Line Length for various percentage of timing distortion
using the unbalanced LM75452 and DM7400 circuits
shown in Figure 17. The definition of Timing Distortion
lDOffiER
NEAR
END RECEIVER
II
':"
CABLE WITH
NINE TWISTED PAIR
100
5.
150
II
10~.
~:::~~:r~~~:'R' -f-H-fH-tl1
1.0 L,..:;.11:.;8D:;,;U~T.:..Y...
CY;.:C..
LE,",,"_.L.l..l..L.J..l.UJ
10
100
LINE LENGTH
FIGURE 22. Data Rate
1l1li0
(FT)
'5 Distorion of
oM7820A, DM7830
':"
FIGURE 23. Signal CrOll Talk Experiment Using
DM75462, DM7400
measure near end cross tal k noise. In this configuration
there are eight line drivers and one receiver at one end of
the cable. The performance of the receiver measured in
the presence of the driver noise is shown in Figure 24.
10·93
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Figure 24 shows the Absolute Maximum Duty Rate of
the unbalanced method versus line length and versus the
number of line drivers corresponding to the test configuration delineated in Figure 23_ In the noise measurement set-up there was a ground return for each signal
wire_ If there is only one ground return in the cable the
performance is worse_ The graph shows that the effective
line length is drastically reduced as additional Near End
Drivers are added_ When this performance is compounded
by timing distortio~ the performance is further reduced.
..
B
...~
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100
===
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LM754521DM7400
TERMINATED 100 1150n
NINE TWISTED PAIR
~8 DUTY CYCLE
FDUR NOISE
10 GENERATDRS
TwO'Nf:lIS
~i;ENERAT
WS
noise similar to the unbalance performance shown in the
previous figure. Unlike the unbalanced case, there was
no measurable degradation of the circuits Data Rate or
distortion.
CONCLUSION
National has a full line of both Balanced and Unbalanced
l"ine Drivers and Receivers. Both circuit types work well
when used within their limitations. This application note
shows that the balanced method is perferable for long
lines in noisy electrical evironments. On the other hand
the unbalanced circuit works perfectly well with shorter
lines and reduced data rates. It should be kept in mind
that when you are spending $500,000 for a CPU and
$75,000 for peripherals, it pays to investigate the best
way to transmit data between them.
:Ii
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DEFINITION OF BAUD RATE
~S~~A\~=~
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1.0
100
10
T,
1__
~
I.
T,-I - - - -
IIIII
1000
LINE LENGTH 1FT)
BIT RATE =
FIGURE 24. Data Rata .. Signal Cross Talk of
LM75462, DM7400
INTERVAL PER BIT
8AUDRATE=
Figure 25 shows the test configuration of the balanced
circuit used to generate worst case Near End cross talk
1
'"
2T2
MINIMUM UNIT INTERVAL
=2.
T1
The data in this note was plotted versus Baud Rate.
The minimum unit interval reflected the worse case
conditions and also normal ized the diagrams so that
the diagrams were independent of duty cycle. If the
duty cycle is 50% then the Baud Rate is twice the
Bit Rate.
REFERENCES
t/2 DUTY CYCLE
170
IC's for Digital Data Transmission, Widlar and Kubinec,
National Semiconductor Application Note AN-22.
Data Bus and Differential Line Drivers and Receivers,
Richard Percival, National Semiconductor Application
NoteAN-83.
RADC TR73-309, Experimental Analysis of the Transmission of Digital Signals over Twisted Pair Cable,
Hendrickson and Evanowski, Digital Communication
Section Communications and Navigation Division, Rome
Air Development Center, Griffis Air Force Base, New
York.
CABLE WITH
NINE TWISTED PAIR
Fast Pulse Techniques, Thad Dreher, E-H Research
Laboratories, Inc., The Electronic Engineer, Aug. 1969.
\
Transient Analysis of Coaxial Cables, Considering Skin
Effects, Wigingtom and Nahmaj. Proceedings of the IRE,
Feb. 1957.
,'"
8 NEAR END GENERATORS
FIGURE 25_ Signal Cross Talk Experiment Using
DM7830,DM7B20A
10-94
Reflection and Crosstalk in Logic, Circuit Interconnections, John DeFalco, Honeywell, Inc., IEEE Spectrum,
July 1970.
M I L-STD -883/M I L-M -38510
r-o
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MIL-STO-883
Mil-Standard-883 is a Test Methods and Procedures
Document for Microelectronic Circuits. It was
derived from MIL-S-19500, MIL-STD-750, and
MIL-STD-202C for transistors and diodes at about
the time that National Semiconductor Corporation
was entering the military microelectronics market.
As a result, our standard quality control operations
are written around MI L-STO-883. The bonding
control, visual inspections, and post seal screening
requirements set forth by 883 (as well as added
control procedures beyond the requirements of
883) have been part of National's quality control
procedures almost from the start. Our Quality
Assurance Procedures Manual is available upon
request.
We offer a complete line of linear/883 (Class B)
products as standard, off-the-shelf items_ Special
Linear/883 data sheets have been prepared to
reflect this capability. They show process flow,
electrical parameters, end of test criteria, and test
circuits. We save you the problem of specifying test
and inspection procedures, and offer significant
cost savings by having an off-the-shelf, "to the
letter" 883 program. In addition, we will test any
of our integrated circuits to any class of MILSTD-883.
The detailed information concerning MI L-STD-883
screening is contained in National's specification
NSC10002_
MIL-M-38510
MIL-M-38510 specifies the general requirements
for supplying microcircuits. These are; product
assurance, which includes screening and quality
conformance inspection; design and construction;
marking; and workmanship. The screening and
quality conformance inspection are conducted in
accordance with MIL-STD-883.
The MIL-M-38510 specs for standard linear devices
require 100% DC testing at 25°C, _55°C and
+125°C. AC testing is performed at +25°C. The
electrical parameters specified are tighter than the
normal data sheet guaranteed limits. Additionally,
MIL-M-38510 requires device traceability, extensive documentation and closely matched maintenance.
SCREENING
All microcircuits delivered in accordance with MI LM-38510 must have been subjected to, and passed
all the screening tests detailed in Method 5004 of
MIL-STD-883 for the type of microcircuit and
product assurance level.
The device electrical and package requirements of
MIL-M-38510are detailed by a device specification
referred to as a slash sheet. Each slash sheet defines
the microcircuit electrical performance and mechanical requirements. Each device listed on a slash
sheet is referred to as a slash number and the group
of the microcircuits contained on a slash sheet is
defined as a family of devices. The device may be
Class B or C as defined by MIL-STD-883, Method
5004 and 5005. Three lead finishes are allowed
by the slash sheet, pot solder dip, bright tin plate,
and gold plate.
QUALITY CONFORMANCE
Quality conformance inspection is conducted in
accordance with the applicable requirements of
Group A, (electrical test), Group Band C, (environmental test) of Method 5005, M I L-STD·883. These
tests are conducted on a sample basis With GroupA
performed on each sublot, Group B on each lot,
and Group C as specified (usually every three
months).
To supply devices to MI L-M-38510, the IC manufacturer must quality the devices he plans to supply
to the detail specifications. Qualification consists
of notifying the qualifying activity of one's intent
to qualify to MIL-M-38510. After passing comprehensive audits of facilities and documentation
systems, the IC manufacturer will subject the
device to and demonstrate that they satisfy all of
11-1
MIL-M-38510 (con't)
the Group A, B, and C requirements of Method
5005 of MIL-STD-883 for the specified classes and
types of IC_ The qualification tests shall be monitored by the qualifying agency. Finally the IC
manufacturer shall prepare and submit qualification test data to the qualifying agency. Groups A,
B, and C inspections then shall be performed at
intervals no greater than three months.
I
....I
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.........
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00
00
I
Q
ICIJI
performed on a sample of devices which are chosen
at random from a lot of devices that has satisfactorily completed the screening of Method 5004
must be performed on each device, Le. on a 100%
basis as opposed to qualification testing (Method
5005) which occurs on a random sample basis.
In summary, the entire purpose of MIL-M-38510
and MIL-STD-883 is to provide the military,
through its contractors with standard devices.
The purpose of qualification testing is to assure
that the device and lot quality conform to certain
standard limits. In effect, lot qualification tests
tend to ensure that once a particular device type
is demonstrated to be acceptable, it's production,
including materials, processing, and testing will
continue to be acceptable. These limit$ are specified in MIL-STD-883 in terms of LTPD's (Lot
Tolerance Percent Defective) for the various qualification test sub-groups. Qualification testing is
....I
:!
MM38510/
I
Specifies the
General Requirements of
MIL-M-38510
11-2
XXX
T
Slash
Sheet
No.
We at National Semiconductor have supplied and
are supplying devices to the MIL-M-38510 specifications. To order a MIL-M-38510 microcircuit,
specify the following:
For example; to specify an LM741 in a DIP
processed to the requirements of MIL-M-38510,
Class B, with gold plated leads, specify M-38510/
10101BCC.
XX
T
Device
Type
X
T
Device
Class
X
T
Case
Outline
X
T
Lead
Finish
c
~
.
Definition of Terms
:::I
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-f
voltage comparators
Input Bias Current: The average of the two Input
currents.
Input Offset Current: The absolute value of the
difference between the two input currents for
which the output will be driven higher than or
lower than specified voltages.
Input Offset Voltage: The absolute value of the
voltage between the input term Inals requ Ired to
make the output voltage greater than or less than
specified voltages.
Input Voltage Range: The range of voltage on the
input terminals (common mode) over which the
offset specifications apply.
Logic Threshold Voltage: The voltage at the out·
put of the comparator at wh ich the loading logic
circuitry changes its digital state.
Negative Output Level: The negative DC output
voltage with the comparator saturated by a dlf·
ferential input equal to or greater than a specified
voltage.
Output Leakage Current: The current into the
output terminal with the output voltage within a
given range and the Input drive equal to or greater
than a given value.
Output Resistance: The resistance seen looking
into the output terminal with the DC output level
at the logic threshold voltage.
Output Sink Current: The maximum negative cur·
rent that can be delivered by the comparator.
Positive Output Level: The high output voltage
level with a given load and the Input drive equal to
or greater than a specified value.
Power Consumption: The power reqUired to oper·
ate the comparator With no output load. The power
will vary with signal level, but is specified as a
maximum for the entire range of Input signal
conditions.
...
(1)
3
Response Time: The interval between the applica·
tion of an input step function and the time when
the output crosses the logic threshold voltage. The
input step drives the comparator from some Initial,
saturated input voltage to an Input level just barely
in excess of that required to bring the output from
saturation to the logic threshold voltage. ThiS
excess is referred to as the voltage overdrive.
(II
Saturation Voltage: The low·output voltage level
With the input drive equal to or greater than a
specified value
Strobe Current: The current out of the strobe
terminal when it is at the zero logic level.
Strobed Output Level: The DC output voltage,
independent of input conditions, with the voltage
on the strobe terminal equal to or less than the
specified low state.
Strobe ON Voltage: The maximum voltage on
either strobe terminal required to force the output
to the specified high state Independent of the
input voltage.
Strobe OFF Voltage: The minimum voltage on the
strobe terminal that will guarantee that it does not
Intertere with the operation of the comparator
Strobe Release Time: The time reqUi red for the
output to rise to the logic threshold voltage after
the strobe terminal has been driven from zero to
the one logic level.
Supply Current: The current required from the
positive or negative supply to operate the com·
parator with no output load. The power will vary
With Input voltage, but IS specified as a maximum
for the entire range of Input voltage conditions.
Voltage Gain: The ratio of the change in output
voltage to the change In voltage between the Input
terminals prodUCing It
analog switches
Driver Leakage Current: The sum of the currents
into the source and drain sWitch terminals, With
both held at the same specified voltage.
Logic "0" Input Voltage: The voltage level which
is guaranteed to be Interpreted by the device as a
logical "false" Signal.
Logic "1" Input Voltage: The voltage level which
is guaranteed to be interpreted by the device as a
logical "true" Signal.
Logic Input Slew Rate: The voltage difference
between the logic "1" and logic "0" states divided
by the transition time.
11·3
II)
E
~
analog switches (con't)
c
Switch Leakage Current: The current seen when a
specified voltage is applied between drain and
source of a channel that is logically turned off.
...o
o
:Ec
Switch On Resistance: The equivalent resistance
from source to drain, tested by forcing a specified
current and measuring the resultant voltage drop.
It=
CD
C
Switch Turn-Off Time: The interval between the
time that the logic input passes through the threshold voltage and the time that the output goes to
a specified voltage level in the test circuit.
Switch Turn-On Time: The interval between the
time that the logic input passes through the threshold voltage and the time that the output goes to
90% of its final value in the specified test circuit.
interface circuits
Common Mode Voltage: Arithmetic mean of voltages at the differential inputs referenced to
ground pin at the receiver.
ferential voltage required to prodcue a given output level, against power supply voltage (V Pin 14V Pin 7).
Common Mode Sensitivity: Rate of change of
input differential voltage required to produce a
given output level, against common mode voltage.
Disabled Output Clamp Current: The current which
flows from the output of a disabled TRI-STATE
gate when it is dragged below ground (for instance
by a transmission-line-associated transient). It is
derived from the Vee power rail.
Supply Sensitivity: Rate of change of input dif-
sense amplifiers
AC Common-Mode Input Firing Voltage: The
peak level of a common-mode pulse which will
exceed the input dynamic range and cause the
logic output to switch. Pulse characteristics: t, = tl
~ 15 ns, PW = 50 ns.
11-4
Differential Input Threshold Voltage: The DC
input voltage which forces the logic output to the
logic threshold voltage (-1.5V) level.
Input Bias Current: The DC current which flows
Into each input pin with differential input of OV.
Common-Mode Input Overload Recovery Time:
The time necessary for the device to recover from
a ±2V common-mode pulse (t, = tl = 20 ns) prior
to the strobe enable signal.
Supply Current: The total DC cur'rent per package
drawn from the voltage supply.
Differential Input Offset Current: The absolute
difference in the two input bias currents of one
differential input.
Offset Voltage: Difference between the absolute
values of threshold voltage in positive- and negativegoing directions.
Differential Input Overload Recovery Time: The
time necessary for the device to recover from a 2V
differential pulse (tl = t, = 20 ns) prior to the
strobe enable signal.
Propagation Delay Time: Interval from switching
input through 1.5V to output traversing its 50%
voltage point. Measured with 50n load to.+10V
15 pF total capacitance.
Physical Dimensions
(All dimensions are in inches.)
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Package 1
14 Lead Cavity DIP (01
Package 2
16 Lead eavity DIP (01
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Package 9
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Package 11
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0.100
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254
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