1974_National_MOS_Integrated_Circuits 1974 National MOS Integrated Circuits
User Manual: 1974_National_MOS_Integrated_Circuits
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Edge Index
by Product Family
Dynamic Shift Registers
Static Shift Registers
PROMs/ROMs
RAMs
Clock Drivers
Analog Switches
ROM Character Generators
ROM Code Converters
Custom MOS/LSI
Complex Standards
Interface Circuits
Microprocessors
Application Notes/Briefs
Def. of Terms/Physical Dimensions
Manufactured under one or more of the following U.S. patents: 3083262, 3189758, 3231797, 3303356, 3317671, 3323071, 3381071, 3408542,3421025,3426423,3440498,3518750, 3519897, 3557431, 3560765,
3566218,3571630,3575609,3579059,3593069,3597640,3607469,3617859,3631312,3633052,3638131,3648071,3651565,3693248.
National does not assume any responsibility for use of any CIrCuitry described; no CIrCUit patent licenses are Implied; and National reserves tile nght, at any time Without notice, to change sail! circuitry.
© 1974 NatiOnal Semiconductor Corp.
I ntrod uction
Here is National's newest MOS handbook containing information on the largest standard MOS
product line in the industry. Extra copies of this handbook, plus those on our other major
product lines - digital, linear and transistors - are also available. To receive your handbooks,
contact a National sales office, representative or distributor.
TOTAL CAPABILITY
Note: Numbers in parentheses are device types presently available.
ii
Table of Contents
Edge I ndex by Product Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Product Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alpha-Numerical Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MOS Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DYNAMIC SHIFT REGISTERS -
i
ii
vii
xi
SECTION 1
MM400/MM500 Dual 25-Bit Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM401/MM501 Dual 25-Bit Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM402/MM502 Dual 50-Bit Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM403/MM503 Dual 50-Bit Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM406/MM506 Dual 1OO-Bit Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM407/MM507 Dual 100-Bit Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM1402A 1024-Bit Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM1403A 1024-Bit Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM1404A 1024·Bit Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4001A/MM5001A Dual 64-Bit Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4006A/MM5006A Dual 100-Bit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4007/MM5007 Dual 1OO-Bit Mask Programmable Shift Register . . . . . . . . . . . . . . . . . . . . . . . .
MM4010A/MM5010A Dual 64-Bit Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4013/MM5013 1024-Bit Dynamic Shift Register/Accumulator . . . . . . . . . . . . . . . . . . . . . . . .
MM4015A/MM5015A Triple 60 + 4-Bit Accumulator/Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4016/MM5016 512-Bit Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4017/MM5017 Dual 512-Bit Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4019/MM5019 Dual 256-Bit Mask Programmable Shift Register . . . . . . . . . . . . . . . . . . . . . . . .
MM5023 Quad 80-Bit Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5024A 1024-Bit Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4025/MM5025 Dual 1024-Bit Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4026/MM5026 Dual 1024-Bit Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4027 /MM5027 2048-Bit Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4104/MM5104 Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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1-1
1-1
1-1
1-1
1-1
1-1
1-5
1-5
1-5
1-9
1-12
1-12
1-9
1-15
1-19
1-22
1-25
1-12
1-28
1-5
1-31
1-31
1-31
1-36
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2-1
2-1
2-4
2-7
2-7
2-10
2-10
2-13
2-16
2-16
2-16
2-21
2-24
2-27
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3-1
3-3
3-8
3-13
3-18
3-21
3-24
3-26
3-28
STATIC SHIFT REGISTERS - SECTION 2
MM404/MM504 Dual 16-Bit Static Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM405/MM505 Dual 32-Bit Static Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4040/MM5040 Dual 16-Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4050A/MM5050A Dual 32-Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4051A/MM5051A Dual 32-Bit Static Shift Register-Split Clock . . . . . . . . . . . . . . . . . . . . . . . .
MM4052/MM5052 Dual 80·Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4053/MM5053 Dual 1OO-Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5054 Dual 64/72/80-Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4055/MM5055 Quad 128-Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4056/MM5056 Dual 256-Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4057/MM5057 512-Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5058 1024-Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5060 Dual 144·Bit Mask Programmable Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5061 Quad 100-Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PROMS/ROMS - SECTION 3
MM3501 1024·Bit Read-Only Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5202A Electrically Programmable 2048-Bit Read Only Memory (PROM) . . . . . . . . . . . . . . . . . .
MM4203/MM5203 2048-Bit Electrically Programmable Read-Only Memory (PROM) . . . . . . . . . . . .
MM5204 Electrically Programmable 4096-Bit Read Only Memory (PROM) . . . . . . . . . . . . . . . . . .
MM4210/MM5210 1024-Bit Read-Only Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4211/MM5211 1024-Bit Read-Only Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5212 12,288-Bit Read-Only Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4213/MM5213 2048-Bit Read-Only Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4214/MM5214 4096-Bit Read-Only Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iii
ROMs - SECTION 3 (Cont.)
MM521512,288-Bit Read-Only Memory. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-30
MM4220/MM5220 1024-Bit Read-Only Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
MM4221/MM5221 1024-Bit Read-Only Memory .... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36
MM4229/MM5229 3072-Bit Read-Only Memory (Open Drain) ............................. 3-40
MM4230/MM5230 2048-Bit Read-Only Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
MM4231/MM5231 2048-Bit Read-Only Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46
MM4232/MM5232 4096-Bit Static Read-Only Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50
MM4233/MM5233 4096-Bit Read-Only Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-53
MM4240/MM5240 2560-Bit Static Character Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-55
MM4241/MM5241 3072-Bit Static Read-Only Memory
3-59
RAMs - SECTION 4
MMll0l 256-Bit Fully Decoded Static Random Access Memory . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM 11 011 256-Bit Fully Decoded Static Random Access Memory . . . . . . . . . . . . . . . . . . . . . . . . .
MMll01A 256-Bit Fully Decoded Static Random Access Memory . . . . . . . . . . . . . . . . . . . . . . . . .
MMll01A 1 256-Bit Fully Decoded Static Random Access Memory . . . . . . . . . . . . . . . . . . . . . . . ..
MMll01A2 256-Bit Fully Decoded Static Random Access Memory . . . . . . . . . . . . . . . . . . . . . . . ..
MM2102 1024-Bit Fully Decoded Static Random Access Memory. . . . . . . . . . . . . . . . . . . . . . . . ..
MM4250 256-Bit Fully Decoded Static Random Access Memory . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4262/MM5262 2048-Bit Fully Decoded Dynamic Random Access ReadIWrite Memory .........
4-1
4-1
4-1
4-1
4-1
4-5
4-1
4-9
CLOCK DRIVERS - SECTION 5
MH0007/MH0007C DC Coupled MOS Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MH0009/MH0009C DC Coupled Two Phase MOS Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . .
MH0012/MH0012C High Speed MOS Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MH0013/MH0013C Two Phase MOS Clock Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MH0025/MH0025C Two Phase MOS Clock Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MH0026/MH0026C 5 MHz Two Phase MOS Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MH7803/MH8803 Two Phase Oscillator/Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MH8808 Dual High Speed MOS Clock Driver
5-1
5-3
5-5
5-7
5-11
5-14
5-23
5-27
ANALOG SWITCHES - SECTION 6
MM450/MM550 Dual Differential Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM451/MM551 Four-Channel Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM452/MM552 Four MOS Transistor Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM454/MM554 Four-Channel Commutator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM455/MM555 Three MOS Transistor Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0014/AH0014C DTLITTL Compatible DPDT Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . ..
AH0015/AH0015C Quad DTLlTTL Compatible SPST Analog Switch . . . . . . . . . . . . . . . . . . . . . . .
AH0019/AH0019C DTLlTTL Compatible Dual DPST Analog Switch . . . . . . . . . . . . . . . . . . . . . . .
AH0120 Series High Level Analog Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AH0130 Series High Level Analog Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AH0140Series High Level Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0150 Medium Level Analog Switches ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AH0160 Medium Level Analog Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AH2114/AH2114C DPST Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AM 1000 Silicon N-Channel High Speed Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AM1001 Silicon N-Channel High Speed Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AM1002 Silicon N-Channel High Speed Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AM2009/AM2009C Six-Channel MOS Multiplex Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AM3705/AM3705C Eight-Channel MOS Analog MUltiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-1
6-1
6-1
6-5
6-1
6-8
6-8
6-8
6-12
6-12
6-12
6-12
6-12
6-21
6-23
6-23
6-23
6-25
6-27
ROM CHARACTER GENERATORS - SECTION 7
MM4220NP/MM5220NP 7x9 Horizontal Scan Display Character Generator . . . . . . . . . . . . . . . . . . ..
MM4230NN/MM5230NN 7x9 Horizontal Scan Display Character Generator . . . . . . . . . . . . . . . . . . .
MM4230NO/MM5230NO 7x9 Horizontal Scan Display Character Generator . . . . . . . . . . . . . . . . . . .
MM4240AA/MM5240AA 7x5 Horizontal Scan ASCII-7 Character Generator . . . . . . . . . . . . . . . . 3-55,
MM4240AE/MM5240AE ASCII-7 and Lower Case Character Generator . . . . . . . . . . . . . . . . . . . . . .
iv
7-1
7-1
7-1
14-21
14-21
ROM CHARACTER GENERATORS - SECTION 7 (Cont.)
MM4240ABl)/MM5240ABU Hollerith Character Generator. . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-3,
MM4240ABZ/MM5240ABZ EBCDIC-8 Character Generator . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5,
MM4240ACA/MM5240ACA EBCDIC Character Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6,
MM4241ABLlMM5241ABL Vertical Scan ASCII-7 Character Generator. . . . . . . . . . . . . . .. . . . . ..
MM4241 ABV /MM5241 ABV Vertical Scan ECMA-7 (Scandinavian) Character Generator . . . . . . . . . . .
MM4241ABW/MM5241ABW Vertical Scan ECMA-7 (German) Character Generator . . . . . . . . . . . . . .
MM4241 ABX/MM5241 ABX Vertical Scan ECMA-7 (French, British, Italian) Character Generator. . . ..
MM4241ABY/MM5241ABY Vertical Scan ECMA-7 (Spanish) Character Generator. . . . . . . . . . . . . ..
14-21
14-21
14-21
14-21
14-21
14-21
14-21
14-21
For information on the following character generators contact National, Santa Clara:
MM4240AD/MM5240AD Katakana Alphabet Character Generator
MM4240AF/MM5240AF 5x7 ASCII·6 with Low True Outputs Character Generator
MM4240AH/MM5240AH 5x7 ASCII-6 with High True Outputs Character Generator
MM4240AK/MM5240AK 5x7 ECMA-6 (French, British, Italian) Character Generator
MM4241AAN/MM5241AAN ASCII Vertical Scan Character Generator
ROM CODE CONVERTERS - SECTION 8
SK0003 Sine/Cosine Look-Up Table Kit ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4220AE/MM5220AE ASCII-7 to Hollerith Code Converter . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4220AP/MM5220AP BCOIC to ASCII Code Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4220BLlMM5220BL Baudot to ASCII Code Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4220BM/MM5220BM Sine Look-Up Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4220BN/MM5220BN Arctangent Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4220DF/MM5220DF "Quick Brown Fox" Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4220EK/MM5220EK BCDIC-to-EBCDIC and ASCII-to·EBCDIC Code Converter. . . . . . . . . . . ..
MM4220LR/MM5220LR BCDIC to ASCII-7/ASCII-7 to BCDIC Code Converter . . . . . . . . . . . . . . .
MM4221 RQ/MM5221 RQ ASCII-7 to EIA RS244A/EIA RS244A to ASCII-7 Code Converter. . . . . ..
MM4221RR/MM5221RR ASCII-7 to EBCDIC Code Converter . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4230BO/MM5230BO Hollerith to ASCII Code Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4230FE/MM5230FE Selectric-to-EBCDIC/EBCDIC-to-Selectric Code Converter . . . . . . . . . . . . .
MM4230JT/MM5230JT BCOIC to EBCDIC/EBCDIC to BCDIC Code Converter . . . . . . . . . . . . . . .
MM4230KP/MM5230KP ASCII-7 to Selectric Code Converter . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4230QW/MM5230QW Hollerith to EBCDIC Code Converter. . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4230QX/MM5230QX EBCDIC-8-to-ASCII-8 Code Converter. . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4230QY/MM5230QY ASCII-8-to-EBCDIC-8 Code Converter. . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4230RS/MM5230RS Binary to Modulo-n Divider Code Converter . . . . . . . . . . . . . . . . . . . . . ..
MM4231RP/MM5231RP IBM 1130 EBCDIC to ASCII-7 Code Converter . . . . . . . . . . . . . . . . . . . . .
MM4232/MM5232 AEI, AEJ, AEK Sine Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
For information on the following code converters contact National, Santa Clara:
MM350lTL ASCII to Baudot, Baudot to ASCII Code Converter
MM4213UW/MM5213UW EBCDIC-8 to Hollerith Code Converter
MM422lTM/MM522lTM ASCII to Baudot, Baudot to ASCII Code Converter
MM4230JP/MM5230JP ASCII to MDS Code Converter
MM4230SQ/MM5230SQ ASCII-8 to Hollerith Code Converter
8-1
8-3
8-6
8-8
8-10
8-14
8-16
8-18
8-21
8-24
8-27
8·30
8-32
8-37
8·43
8-46
8-48
8-50
8-52
8-54
8-59
CUSTOM MOS/LSI - SECTION 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
9-1
COMPLEX STANDARDS - SECTION 10
MM5307 Baud Rate Generator/Programmable Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5309 Digital Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5311 Digital Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5312 Digital Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5313 Digital Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5314 Digital Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5315 Digital Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5316 Digital Alarm Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4320/MM5320 TV Camera Sync Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5370 Digital Alarm Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5371 Digital Alarm Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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10-1
10-4
10-10
10-10
10-10
10-10
10·4
10-15
10-20
10-26
10-26
v
COMPLEX STANDARDS - SECTION 10 (Cont.)
MM5375AA/AB/AC/AD/AE Digital Alarm Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5554 Frequency Divider. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5555 Chromatic Frequency Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5556 Chromatic Frequency Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5725 One Chip Calculator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5736 MaS/LSI Six-Digit Calculator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5738 MaS/LSI Eight-Digit Calculator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5739 MaS/LSI Eight-Digit Calculator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5740 90-Key Keyboard Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5740AAE 90-Key Keyboard Encoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5740AAF 90-Key Keyboard Encoder ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
10·33
10·38
10-40
10-40
10-42
10-54
10-59
10-71
10-76
10-76
10-76
INTERFACE CIRCUITS - SECTION 11
DM7800/DM8800 Dual Voltage Translator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7802/DM8802 High Speed MaS to TTL Level Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7806/DM8806 High Speed MaS to TTL Level Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7810/DM8810 Quad 2-lnput TTL-MaS Interface Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7811/DM8811 Quad 2-lnput TTL-MaS Interface Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7812/DM8812 TTL-MaS Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '" . . . . . . . . .
DM8861 MOS-to-LED 5-Segment Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8863 MOS-to-LED 8-Digit Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8885 MaS to High Voltage Cathode 8uffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM75491 MOS-to·LED Quad Segment Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM75492 MOS-to-LED Hex Digit Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM88l12 TTL-MaS Hex Inverter/Interface Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM139/LM239/LM339 Quad Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM163/LM363 Dual Line Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM363A Dual MaS Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM55107A/LM75107A Dual Line Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM55108A/LM75108A Dual Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM75207 Dual MaS Sense Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM75208 Dual MaS Sense Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
11-1
11-4
11-4
11-9
11-9
11·9
11-11
11-11
11-15
11-17
11-17
11-20
11-22
11-30
11-30
11-30
11-30
11-30
11-30
MICROPROCESSORS - SECTION 12
Microprocessor IMP-Series Product Description List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
*MM5750 MaS/LSI Register and Arithmetic Logic Unit (RALU). . . . . . . . . . . . . . . . . . . . . . . . . ..
**MM5751 MaS/LSI Control and Read Only Memory Unit (ROM) . . . . . . . . . . . . . . . . . . . . . . . . ..
12-1
12-6
12-14
APPLICATION NOTES/BRIEFS - SECTION 13
AN-40 The Systems Approach to Character Generators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AN-44 High Voltage Shift Registers Move Display. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AN-55 Low Frequency Operation with Dynamic Shift Registers. . . . . . . . . . . . . . . . . . . . . . . . . ..
AN-57 American and European Fonts in Standard Character Generators. . . . . . . . . . . . . . . . . . . ..
AN-76 Applying Modern Clock Drivers to MaS Memories. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AN-80 MaS Keyboard Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN·85 Saving ROMs in High-Resolution Dot·Matrix Displays and Printers . . . . . . . . . . . . . . . . . . .
AN-86 A Simple Power Saving Technique for the MM5262 2K RAM ...... . . . . . . . . . . . . . . . .
AN-lOa Custom ROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MaS 8rief 10 Trig Function Generators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MaS Brief 14 Mask Programming Specializes MaS Shift Register Designs . . . . . . . . . . . . . . . . . . . .
MaS Brief 16 Double-Clocking Cuts Standard Registers to Non-Standard Sizes. . . . . . . . . . . . . . . ..
DEFINITION OF TERMS/PHYSICAL DIMENSIONS - SECTION 14
*IMP-OOH/520
HIMP-16A/521. IMP-16A/522. IMP-8A/520
vi
13-1
13-13
13-17
13-21
13-27
13-39
13-51
13-59
13-63
13-71
13-73
13-75
Alpha-Numerical Index
AH0014/AH0014C DTL/TTL Compatible DPDT Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0015/AH0015C Quad DTL/TTL Compatible SPST Analog Switch . . . . . . . . . . . . . . . . . . . . . .
AH0019/AH0019C DTL/TTL Compatible Dual DPST Analog Switch . . . . . . . . . . . . . . . . . . . . . .
AH0120 Series High Level Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0130 Series High Level Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0140 Series High Level Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0150 Medium Level Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0160 Medium Level Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH2114/AH2114C DPST Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AM1000 Silicon N-Channel High Speed Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AM1001 Silicon N-Channel High Speed Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AM 1002 Silicon N-Channel High Speed Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AM2009/AM2009C Six-Channel MaS Multiplex Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AM3705/AM3705C Eight-Channel MaS Analog Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7800/DM8800 Dual Voltage Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7802/DM8802 High Speed MaS to TTL Level Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7806/DM8806 High Speed MaS to TTL Level Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM781 0/DM881 0 Quad 2-1 nput TTL-MaS I nterface Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7811/DM8811 Quad 2-lnput TTL-MaS Interface Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7812/DM8812 TTL-MaS Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM8861 MaS-to-LED 5-Segment Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM8863 MaS-to-LED 8-Digit Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM8885 MaS to High Voltage Cathode Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM75491 MaS-to-LED Quad Segment Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM75492 MaS·to-LED Hex Digit Driver
........................................
DM88L 12 TTL-MaS Hex Inverter/Interface Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM 139/LM239/LM339 Quad Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM163/LM363 Dual Line Receiver
............................................
LM363A Dual MOS Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM55107A/LM75107A Dual Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM55108A/LM75108A Dual Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM75207 Dual MOS Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM75208 Dual MOS Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MH0007/MH0007C DC Coupled MaS Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MH0009/MH0009C DC Coupled Two Phase MaS Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . .
MH0012/MH0012C High Speed MOS Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MH0013/MH0013C Two Phase MOS Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MH0025/MH0025C Two Phase MOS Clock Driver
MH0026/MH0026C 5 MHz Two Phase MOS Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MH7803/MH8803 Two Phase Oscillator/Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MH8808 Dual High Speed MOS Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .....
MM400/MM500 Dual 25-Bit Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM401/MM501 Dual 25-Bit Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM402/MM502 Dual 50-Bit Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM403/MM503 Dual 50-Bit Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM404/MM504 Dual 16-Bit Static Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM405/MM505 Dual 32-Bit Static Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM406/MM506 Dual 100-Bit Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM407/MM507 Dual 100-Bit Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM450/MM550 Dual Differential Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM451/MM551 Four-Channel Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM452/MM552 Four MOS Transistor Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM454/MM554 Four-Channel Commutator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM455/MM555 Three MOS Transistor Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM1101 256-Bit Fully Decoded Static Random Access Memory . . . . . . . . . . . . . . . . . . . . . . . . .
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6-8
6-8
6-8
6-12
6-12
6-12
6-12
6-12
6-21
6-23
6-23
6-23
6-25
6-27
11-1
11-4
11-4
11-9
11-9
11-9
11-11
11-11
11-15
11-17
11-17
11-20
11·22
11-30
11-30
11-30
11-30
11-30
11-30
5-1
5·3
5-5
5-7
5-11
5-14
5-23
5-27
1-1
1-1
1-1
1-1
2-1
2-1
1-1
1-1
6-1
6-1
6-1
6-5
6-1
4-1
vii
MM1101A 256-Bit Fully Decoded Static Random Access Memory . . . . . . . . . . . . . . . . . . . . . . . . ,
MM 11 01 A 1 256-Bit Fully Decoded Static Random Access Memory . . . . . . . . . . . . . . . . . . . . . . . ,
MMll01A2 256-Bit Fully Decoded Static Random Access Memory. . . . . . . . . . . . . . . . . . . . . . ..
MM1402A 1024-Bit Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM1403A 1024-Bit Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM1404A 1024-Bit Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM2102 1024-Bit Fully Decoded Static Random Access Memory . . . . . . . . . . . . . . . . . . . . . . . . .
MM3501 1024-Bit Read-Only Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,
MM4001A/MM5001A Dual 64-Bit Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4006A/MM5006A Dual 100-Bit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4007/MM5007 Dual 100-Bit Programmable Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4010A/MM5010A Dual 64-Bit Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4013/MM5013 1024-Bit Dynamic Shift Register/Accumulator . . . . . . . . . . . . . . . . . . . . . . . . .
MM4015A/MM5015A Triple 60+4-Bit Accumulator/Register . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4016/MM5016 512-Bit Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4017/MM5017 Dual 512-Bit Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4019/MM5019 Dual 256-Bit Mask Programmable Shift Register . . . . . . . . . . . . . . . . . . . . . . . .
MM4025/MM5025 Dual 1024-Bit Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4026/MM5026 Dual 1024-8it Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4027/MM5027 2048-Bit Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4040/MM5040 Dual 16-Bit Static Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4050A/MM5050A Dual 32-Bit Static Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4051A/MM5051A Dual 32-Bit Static Shift Register-Split Clock. . . . . . . . . . . . . . . . . . . . . . . ..
MM4052/MM5052 Dual 80-Bit Static Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4053/MM5053 Dual 100-Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4055/MM5055 Quad 128-Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4056/MM5056 Dual 256-Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4057/MM5057 512-Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4104/MM5104 Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4203/MM5203 2048-Bit Electrically Programmable 2048 Read-Only Memory (PROM) . . . . . . . ..
MM4210/MM5210 1024-Bit Read-Only Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4211/MM5211 1024-Bit Read-Only Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4213/MM5213 2048-Bit Read-Only Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4214/MM5214 4096-Bit Read-Only Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4220/MM5220 1024-Bit Read-Only Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4220AE/MM5220AE ASCII-7 to Hollerith Code Converter . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4220AP/MM4220AP BCDIC to ASCII Code Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4220BL/MM5220BL Baudot to ASCII Code Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4220BM/AM5220BM Sine Look-Up Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4220BN/MM5220BN Arctangent Look-Up Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4220DF/MM5220DF "Quick Brown Fox" Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4220EK/MM5220EK BCDIC-to-EBCDIC and ASCII-to-!:BCDIC Code Converter. . . . . . . . . . . . ..
MM4220LR/MM5220LR BCDIC to ASCII-7/ASCII-7 to BCDIC Code Converter . . . . . . . . . . . . . . .
MM4220NP/MM5220NP 7x9 Horizontal Scan Display Character Generator . . . . . . . . . . . . . . . . . . ,
MM4221/MM5221 1024-Bit Read-Only Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4221RQ/MM5221RQ ASCII-7 to EIA RS244A/EIA RS244A to ASCII-7 Code Converter .......
MM4221RR/MM5221RR ASCII-7 to EBCDIC Code Converter . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4229/MM5229 3072-Bit Read-Only Memory (Open Drain) . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4230/MM5230 2048-Bit Read-Only Memory.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4230BO/MM5230BO Hollerith to ASCII Code Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4230FE/MM5230FE Selectric-to-EBCDIC/EBCDIC-to-Selectric Code Converter .............
MM4230JT/MM5230JT BCDIC to EBCDIC/EBCDIC to BCDIC Code Converter . . . . . . . . . . . . . . .
MM4230KP/MM5230KP ASCII-7 to Selectric Code Converter
MM4230NN/MM5230NN 7x9 Horizontal Scan Display Character Generator. . . . . . . . . . . . . . . . . ..
MM4230NO/MM5230NO 7x9 Horizontal Scan Display Character Generator. . . . . . . . . . . . . . . . . ..
MM4230QW/MM5230QW Hollerith to EBCDIC Code Converter. . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4230QX/MM5230QX EBCDIC-8-to-ASCII-8 Code Converter. . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4230QY/MM5230QY ASCII-8-to-EBCDIC-8 Code Converter. . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4230RS/MM5230RS Binary to Modulo-n Divider Code Converter ..... ; . . . . . . . . . . . . . . . ..
MM4231/MM5231 2048-Bit Read-Only Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
viii
4-1
4-1
4-1
1-5
1-5
1-5
4-5
3-1
1-9
1-12
1-12
1-9
1-15
1-19
1-22
1-25
1-19
1-31
1-31
1-31
2-4
2-7
2-7
2-10
2-10
2-16
2-16
2-16
1-36
3-8
3-18
3-21
3-26
3-28
3-32
8-3
8-6
8-8
8-10
8-14
8-16
8-18
8-21
7-1
3-36
8-24
8-27
3-40
3-42
8-30
8-32
8-37
8-43
7-1
7-1
8-46
8-48
8-50
8-54
3-46
MM4231RP/MM5231RP EBCDIC to ASCII-7 Code Converter
MM4232/MM5232 4096-Bit Static Read-Only Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4233/MM5233 4096-Bit Read-Only Memory . . . . . . . . . .
MM4240/MM5240 2560-Bit Static Character Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM4240AA/MM5240AA 7x5 Horizontal Scan ASCII-7 Character Generator
. . . . . . . . . .. 3-53,
MM4240AE/MM5240AE ASCII-7 and Lower Case Character Generator . . . . . . . . . . . . . . . . . . . . .
7-3,
MM4240ABU/MM5240ABU Hollerith Character Generator
MM4240ABZ/MM5240ABZ EBCDIC-8 Character Generator . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5,
MM4240ACA/MM5240ACA EBCDIC Character Generator. . . . . . . . . . . .
. . . . . . . . . ..
7-6,
MM4241/MM5241 3072-Bit Static Read-Only Memory . . . . . . . . . . . . . . . . . . . . .
MM4241ABL/MM5241ABL Vertical Scan ASCII-7 Character Generator . . . . . . . . . . . . .
MM4241 ABV /MM5241 ABV Vertical Scan ECMA-7 (Scandinavian) Character Generator ... .
MM4241ABW/MM5241ABW Vertical Scan ECMA-7 (German) Character Generator ..... .
MM4241 ABX/MM5241 ABX Vertical Scan ECMA-7 (French, British, Italian) Character Generator ....
MM4241 ABY /MM5241ABY Vertical Scan ECMA-7 (Spanish) Character Generator
MM4262/MM5262 2048-Bit Fully Decoded Dynamic Random-Access Memory . . . . . . . . . . . . . . . . .
MM4320/MM5320 TV Camera Sync Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5023 Quad 80-Bit Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5024A 1024-Bit Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5054 Dual 64172/80-Bit Static Shift Register. . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5058 1024-Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5060 Dual 144-Bit Mask Programmable Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5061 Quad 100-Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5202A Electrically Programmable 2048-Bit Read-Only Memory (PROM) . . . . . . . . . . . . . . . . . .
MM5204 Electrically Programmable 2048-Bit Read-Only Memory (PROM). . . . . . . . . . . . . . . . . . ..
MM5212 12,288-Bit Read-Only Memory (Open Drain) . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5215 12,288-Bit Read-Only Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5307 Baud Rate Generator/Programmable Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5309 Digital Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5311 Digital Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5312 Digital Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . ..
MM5313 Digital Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '
MM5314 Digital Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5316 Digital Alarm Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5319 Digital Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5370 Digital Alarm Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5371 Digital Alarm Clock . . . . . . . . . . . . . . . . . . . . . . ..
. . . . . . . . . . . . . . . . .. . . .
MM5375AA/AB/AC/AD/AE Digital Alarm Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5554 Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5555 Chromatic Frequency Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5556 Chromatic Frequency Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5725 One Chip Calculator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5736 MOS/LSI Six-Digit Calculator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . ..
MM5738 MOS/LSI Eight-Digit Calculator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5739 MOS/LSI Eight-Digit Calculator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5740 90-Key Keyboard Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5740AAE 90-Key Keyboard Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5740AAF 90-Key Keyboard Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5750 MOS/LSI Register and Arithmetic Logic Unit (RALU). . . . . . . . . . . . . . . . . . . .
MM5751 MOS/LSI Control and Read Only Unit (CROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
SK0003 Sine/Cosine Look-Up Table Kit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-54
3-50
3-51
3-55
14-21
14-21
14-21
14-21
14-21
3-59
14-21
14-21
14-21
14-21
14-21
4-13
10-20
1-28
1-5
2-13
2-21
2-24
2-27
3-3
3-13
3-40
3-30
10-1
10-4
10-10
10-10
10-10
10-10
10-15
10-4
10-26
10-26
10-33
10-38
10-40
10-40
10-42
10-54
10-59
10-71
10-76
10-76
10-76
12-1
12-9
8-1
ix
~
~s
0
MOS Selection Guide
Max Freq
orM;n
Access Time
VDD2
VSS
VDD
VGG
(J)
(J)
CD
CD
Clock
....
Swing
(')
Dynamic Shift Registers
MM400/MM500
MM401/MM501
MM402/MM502
MM403/MM503
MM406/MM506
Dual
Dual
Dual
Dual
Dual
25-81t Dynamic Shift Register
25-8it Dynamic Shift Register
50-Bit Dynamic Shift Register
50-Bit Dynamic Shift Register
100-8it Dynamic Shift Register
1.0 MHz
1.0 MHz
1.0 MHz
1.0MHz
1.0MHz
+10
+10
+10
+10
+10
GNO
GNO
GNO
GNO
GNO
+10
+5.0
+5,0
None
None
None
None
None
16
16
16
16
16
GNO
None
16
5.0
5.0
5.0
NOlle
None
None
17
17
17
MM407/MM507 Dual laO-Bit Dynamic Shift Register
MM1402A 1024-8it Dynamic Shift Register
1.0 MHz
5.0 MHz
MM14Q3A 1024-81t Dynamic Shift Register
MM1404A 1024-81t Dynamic Shift Register
5.0 MHz
5.0 MHz
MM4001A/MM5001A Dual 64-Bit Dynamic Shift Register
2.5 MHz
+5.0
None
·12
17
MM4006A/MM5006A Dual laO-Bit Dynamic Shift Register
MM4007/MM5007 Dual 100-Bit Mask Programmable Shift Register
MM4010A/MM5010A Dual 64-Bit Accumulator
MM4013/MM5013 1024-Blt Register/Accumulator
MM4015A/MM5015A Triple 60 + 4-Blt Register/Accumulator
2.5
2.5
2.5
2.5
2.5
MHz
MHz
MHz
MHz
MHz
t5.0
+5.0
+5,0
+5.0
+5.0
None
None
None
None
None
12
-12
-12
12
-12
17
MM4016/MM5016 512-Blt Dynamic Shift Register
MM4017/MM5017 Dual 512-81t Dynamic Shift Register
MM4019/MM5019 Dual 256-Blt Mask Programmable Shift Register
MM5023 Quad 80-Blt Dynamic Shift Register
MM5024A 1024-Bit Dynamic Shift Register
2.5
2.5
2.5
2.5
5.0
MHz
MHz
MHz
MHz
MHz
+5.0
+5.0
+5.0
+5.0
+5.0
None
None
None
GND
12
12
12
12
·5.0
None
17
MM4025/MM5025
MM4026/MM5026
MM4027/MM5027
MM4104/MM5104
3.0 MHz
3.0 MHz
+5.0
+5.0
+5.0
+5.0
GND
GND
GNO
17
17
None
··12
12
12
-12
GNO
GND
GNO
GNO
GND
6.0
-D.O
- 12
12
12
16
16
+5.0
+5.0
+5.0
+5.0
+5.0
+5.0
+5.0
+5.0
GNO
GNO
GNO
GNO
GNO
12
12
12
-12
12
+5.0
+5.0
+5.0
+5.0
GNO
GNO
GNO
GNO
12
12
12
-12
TTL
TTL
TTL
TTL
TTL
TTL
TTL
+5.0
+5.0
+5.0
·-13
12
-12
-12
-12
-27
-12
·12
-12
-12
None
None
None
None
None
12
-12
-12
-·12
OV
-12
12
12
12
-12
None
None
None
None
None
-12
-·12
-12
-12
-12
12
·12
-12
12
12
None
None
None
None
None
-12
·12
-12
-12
None
None
None
None
Dual 1024-Bit Dynamic Shift Register
Dual 1024-Blt Dynamic Shift Register
2048-Bit DynamiC Shift Register
DynamiC Shift Register
3.0 MHz
2.5 MHz
+5.0
C)"
~
G)
c:
c..
CD
17
17
17
17
17
17
17
TTL
17
17
Static Shift Registers
MM404/MM504 Dual 16-Bit Static Register
MM405/MM505 Dual 32-8it Static Register
MM4040/MM5040 Dual 16-8it Static Shift Register
MM4050A/MM5050A Dual 32-Bit Static Shift Register
MM4051A/MM5051A Dual 32-8\t Static Shift Register-Split Clock
1.0 MHz
1.0 MHz
2.2 MHz
MM4052/MM5052 Dual 80-Bit Static Shift Register
MM4053/MM5053 Dual 1DO-Bit Static Shift Register
MM5054 Dual 64172/80-8it Static Shift Register
MM4055/MM5055 Quad 128-Bit Static Shift Register
MM4056/MM5056 Dual 256-Bit Static Shift Register
1.6 MHz
MM4057/MM5057 512-8it Static Shift Register
MM5058 1024-8it Static Shift Register
MM5060 Dual 144-81t Mask Programmable Static Shift Register
MM5061 Quad 100-Bit Static Shift Register
1.6 MHz
1.6 MHz
1.6
2.2
1.5
1.5
MHz
MHz
MHz
MHz
1.5 MHz
1.5 MHz
1.5 MHz
1.5 MHz
+10
+10
17
17
17
17
17
PRDMs/RDMs
4.0 }J.S
1.0 }J.S
1.O}.1s
MM3501 1024·8it Read-Only Memory
MM5202A Electrically Programmable 2048-8it PROM
MM4203/MM5203 2048-Bit Electrically Programmable PROM
MM5204 Electrically Programmable 4096-8it PROM
MM4210/MM5210 1024-Bit Read-Only Memory
650 ns
+12
MM42l1/MM5211 1024-8it Read-Only Memory
MM5212 12,288-Bit Read-Only Memory
MM42l3/MM5213 2048-81t Read-Only Memory
MM4214/MM5214 4096-Bit Read-Only Memory
MM5215 12,288-8it Read-Only Memory
950 ns
5.0 }J.S
750 ns
1.0}.1s
3.0 }J.S
+5.0
t5.0
MM4220/MM5220 1024-8it Read-Only Memory
MM422l/MM5221 1024-81t Read-Only Memory
MM4229/MM5229 3072-8it Read-Only Memory (Open Drain)
+12
MM4231/MM5231 2048-8it Read-Only Memory
650 ns
950 ns
1.4/1s
725 ns
950 ns
MM4232/MM5232
MM4233/MM5233
MM4240/MM5240
MM4241/MM5241
1.0}.1s
1.0}J.s
600 ns
900 ns
+5.0
+5.0
+5.0
-12
-12
-12
-12
MM1101 256-Bit Fully Decoded Static Random Access Memory
MM11011 256-Bit Fully Decoded Static Random Access Memory
MM 11 01 A 256-8it Fully Decoded Static Random Access Memory
MM 11 01 A 1 256~Bit Fully Decoded Static Random Access Memory
MMll01A2 256-Bit Fully Decoded Static Random Access Memory
1.5}J.s
1.0/1s
1.5 }.1S
1.0}.ls
500 ns
+5.0
+5.0
+5.0
+5.0
+5.0
-·7.0
-7.0
--9.0
·9.0
-9.0
-10
-10
--9.0
--9.0
--9.0
None
None
None
None
None
MM2l021024-Bit Fully Decoded Static Random Access Memory
MM4250 256-Bit Fully Decoded Static Random Access Memory
MM4'262/MM5262 2048-8it Fully Decoded Dynamic R/W Memory
1.0/15
650 ns
365 ns
+5.0
+5.0
+5.5
None
None
-5.0
-15
-9.0
None
None
+8.5*
19
MM4230/MM5230 2048-Blt Read-Only Memory
4096-8it
4096-8it
2560-8it
3072-8it
Static Read-Only Memory
Read-Only Memory
Static Character Generator
Static Read-Only Memory
~5.0
+5.0
+12
+5.0
+5.0
+12
+5.0
+12
RAMs
'VBB
xi
3:
3:
~
o
o
"3:
3:
Dynamic Shift Registers
* MM400/MM500 series dynamic shift registers
general description
U1
The National Semiconductor line of dynamic shift
registers are built on a single silicon chip utilizing
MOS P channel enhancement mode transistors.
Designed to operate over a wide frequency spec·
trum, these devices can be used in any sequential
digital system that employs a two phase clocking
system. The low threshold transistors used permit
operation with a V OD supply voltage of -1 OV and
a -16V clock amplitude to obtain these device
features:
•
Minimum Operating
Frequency Guarantee
o
o
•
Military and Commercial Temperature Ranges
-55°C to +125°C
MM400 Series
MM500 Series
O°C to + 70°C
en
CD
The power dissipation of the device decreases as
the operating frequency is decreased; at 10 kHz
typical dissipation is 6 I1W/bit. The minimum
operating frequency is also reduced substantially
at lower temperatures; typical minimum frequency
of operation at 25°C is 100 Hz.
•
Direct DTL or TTL compatibility
•
High Frequency
Operation
•
Low Power
Consumption
1 MHz guaranteed
0.8 mW/bit
@
1 MHz
1/1
500 ohms
•
Low Output Impedance (VoHI
•
Clock inputs directly compatible with MH0009,
two phase clock driver
schematic and connection diagrams
...
(ii'
Metal Can Package
-Voo
,~
Note: Pm 4 connected 10 case.
TOPVIEW
tLOCK¢, ONPIN 5
Order Number MM400H,
MM500H, MM401H, MM501H,
MM402H, MM502H, MM403H,
MM503H, MM406H, MM506H,
MM407H or MM507H
CLOCKtJ>, ONPINl
See Package 23
typical applications
FIGURE 1 - TTL/MaS Interface- Low Frequency
(see clock timing graph for detail)
CLOCK V"1,tl2 REnUIREMENTSWITH Vss =+5V
CLOCK REP. RATE 650 kHz TYP.
lOGIC "0" (V ss ) = +4.5V
lOGIC "1" (Vs.<; - V,:,d
=
-sv
,
ClOCKh
+lDV TYP.
Standard Register Configurations t
I
I
VSS-~~
,
CLOCK V()l. ')2 REnUIREMENTS WITH Vss
lOGIC "0" (Vssl ~ +9.SV
lOGIC "1" (V ss - V(Jd '" -S.OV
-10V
Waveforms for Applications
ClOCKrJj,
FIGURE 2 - TTL/MaS Interfaces
OPEN DRAIN OUTPUT
CONFIGURATION
I
vss-v:~
I
TYPICAlOATAIN (Vss-2.5VI=\
C~
(Vss-4·5V)
~
I'
~
20 Kn OUTPUT
-5SoC to
+12S"C
- 2SoC to
+70°C
-5SoC to
+12So C
- 2SoC to
+70°C
Dual 25 bit
MM400
MM500
MM401
MM501
Dual 50 bit
MM402
MM502
MM403
MM503
Dual 100 bit
MM406
MMS06
MM407
MM507
I
:::~~::::"'=B"'n="='A=,=~L--IF=='\L--
tFor other length registers consult your National representative.
*For New Designs, See MM4006A/MM5006A Data Sheet.
1·1
I/)
Q)
';:
absolute maximum ratings
Q)
U)
Drain Voltage (-V DD )
Clock Inputs (V, , V2)
Data Inputs
Power Dissipation (Note 1)
Operating Temperature
MM400 Series
MM500 Series
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
0
0
It)
~
~
.......
0
0
~
~
~
electrical characteristics
PARAMETER
Clock Repetition Rate
Clock Input Capacitance
(Pins 3 & 5)
Data Output Voltage Levels
MOS to MaS
Logic "0" (V 0 H)
+0.5V to -25V
+0.5V to -25V
+0.5V to -25V
500mW
-55°C to +125°C
-25°C to + 70°C
-65°C to +150°C
300°C
(Note 2)
CONDITIONS
See Fig. 2
See Fig. 1
f: 1.0 MHz, OV Bias
MM400, 401,500,501
MM402, 403, 502, 503
MM406, 407, 506, 507
-20V Bias
MM400, 401, 500, 501
MM402, 403, 502, 503
MM406, 407, 506, 507
V DD : GND, Vss : +10V
freq : 1 MHz max.
Input (d.c.)
Logic "0" (V OH )
Logic "1" (VOL)
I L : 2.5 rnA } S N
6
ee ote
I L : -1 .6 rnA
Breakdown Voltage
On Pin 1
On Pin 2 (Note 3)
On Pin 6 (Note 3)
On Pin 7
Leakage Current
Pin 1
Pin 2 (Note 4)
Pin 6 (Note 4)
Pin 7
Pin 8 (Note 4)
Power Supply Current Drain
1-2
MAX
1.0
0.5
V DD : -5V, Vss: +5V
(V ss : 4.75 min)
freq : 0.5 MHz max.
IL : 2.5 rnA }
IL : -1.6 rnA See Note 6
1.0 illS. Test Current
TA : 25°C
GND on Pins 2, 3, 4, 5, 6, 7
-8V on Pin 8
GND on Pins 1,4,6,7,8
-8V on Pins 3, 5
GND on Pins 1,2,4,7,8
-8V on Pins 3, 5
GND on Pins 1, 2, 3, 4, 5, 6
-8V on Pin 8
TA : 25°C
V, : -18V, Va: -8V
All Other Pins at GND
V 2 : -18V, Vo: V's: -8V
All Other Pins at GND
V6: -18V, V3: Vs : -8V
All Other Pins at GND
V 7 : -18V, Va: -8V
All Other Pins at GND
Va: -8V
All Other Pins at GND
Outputs at Logic "1"
1 MHz Operations, T A : 25°C
(, : 0.4 IlS, 2 : 0.2 IlS)
MM400,401,500,501
M M402 ,403,502 ,503
M M 406 ,407 ,506 ,507
UNITS
MHz
MHz
22
40
85
40
60
100
pF
pF
pF
18
32
55
25
40
65
pF
pF
pF
Vss -1.5
V
V
Vss -8.0V
Logic "1" {VoLl
Logic "0" (V OH )
Logic "1" (VOL)
TYP
V OD : -10V, Vss: GND
freq: 1 MHz max.
Input (d.c.)
MaS to TTL (Fig. 1)
MaS to TTL (Fig. 2)
MIN
See Note 5
See Note 5
0.4
V
V
0.4
V
V
2.5
2.5
-25
V
-25
V
-25
V
-25
V
4.5
9.0
18.0
0.5
IlA
0.5
IlA
0.5
IlA
0.5
IlA
0.5
IlA
9.0
14.0
30.0
rnA
(Average)
~
~
electrical drive requirements
CONDITIONS
PARAMETER
Clock Pulse Width
4>, Clock pw
Clock pw
Clock Delay, "'d
See Definition
TVP
MAX
UNITS
10.0
10.0
11 5
11 5
115
115
115
11 5
0.4
0.2
0.1
1 MHz, "'pw = 0.2115
100 kHz, "'pw = 0.2115
10 kHz, "'pw = 10 115
Clock I nput Level (V ¢)
Logic "0" (V~H I
Logic "1" (V¢L)
Data Pulse Width tdw
Data Setup Time tds
Data Input Voltage Levels
MaS to Mas
Logic "0" (V IH I
Logic "1" (V ,L I
TTL to MaS (Fig. 1)
Logic "0" (V IH I
Logic "1" (V,LI
TTL to MaS (Fig. 2)
Logic "0" (V ,H I
Logic "1" (V,LI
MIN
........
~
~
See Timing Diagram
"'2
Clock Pulse Transition trcP, tf, -Vlj>
lj>d......., J.-....
90%
10%
I
-Voo
turns ON allowing node F to be at --2-. When $2 returns to its zero state (ground level) T2 turns OFF allowing node F to discharge to zero volts. When tP1 goes negative (one state) the coupling unit T3 and the load resistor T5 are clocked ON allowing information at node F
to be transferred to node B. T4 is held OFF if node F was
at ground potential and is turned ON if node F had been
at -Voo potential. Continuing the example above, T4 is
held OFF and node G is at -Voo since T5 is ON during
<1>1 clock pulse. When (1'1 returns to its zero state, node G
maintains a -Voo voltage level. This voltage level is
IT!aintained at node G until the tP2 clock appears. The
bit delay demonstrated in this example is repeated
through each half of the dual register.
NOOE A
NODE 8
NOOE C
DATA
OUTPUT
I
I
N 81T DELAY
~
1·3
performance characteristics
Minimum Operating Frequency
Power Dissipation vs Maximum Frequency
10K
1000
.
~TA"2n
I-V oo ",-10V
.E 100 f-v." -16V
z
0::
'"
:l:
iii
c
10
~
MMJ06
'">
M~402
f-
2K
MM400=
or
~
l<
.,...
"
~
10
100
V
100
1/
50
1/
.
1.4
~
1.4
....
1.2
....
1.2
'!:
1.0
~
1.0
0::
0.8
~
0.8
iii
0.6
~
0.6
or
0.4
a:
0.4
C
~
0.2
~
~.
..,.
I-
FRED.
IMHz)
1.0
1.5
3.5 I- 2.0
3.0 I-- 2.5
4.0 I--
2.0
1.5
.,
•2
0.4
0.3
0.2
0.15
0.2
0.2
0.2
0.15
.......
-2
-3
-4
-5
-6
-1
-8
Clock Timing, Direct·Coupled TTL or OTl
1.·~~ .....
....
;::;
1~~
~
°t
i..-
~
4.0
~
3.0
"'"
2.0
~
Veo '" -lOY
""'"
~~
-14
-16
-18
••
UNITS
0.1
0.05
0.05
0.05 1 "~
"'
"'
"'
""'"
ons
-20
CLOCK AMPlITUDE IVOLTS)
..
.'" ...
-
.E
....;;;
c
I I
~U
V¢1' V¢2
(VOL TS)
~~
r--.....
..........
........
~~
lA
~
0.8
iii
0.6
'"
0.4
:l:
~
~
l<
1.0
'"0::
C
200
or
0.2
o
-25
1 ps
Power Dissipation/Bit vs. Temperature
1.8 r--r--r--r--,.-,--,.--r-......
.
:l:
iii
400 ns 0.6!Js 0.8 J15
.E 1.2
....
0::
nt
~~
.........
200 ns
CLOCK 1' V <1>2
vs. Maximum Frequency
~
oIt:±::±::±=t:d:=:b::b;;;l
140
~
'-- 1.1._S5ot - l
~ d'J0t
Veo (VOL TS)
4.5
I
100
o
-9
-8
~
I
60
0.1
0
5.0
20
-20
1.8
C
~
1/
Power Dissipation/Bit vs. Clock Amplitude
1.8
~
Voo '" -tOV
V"'l '" V1>:l '" -16V
TEMPERATURE (OC)
Power Dissipation/Bit vs. Supply Voltage
:l:
I....
/
OPERATING FREQUENCY (kHz)
.E
V
TYPICAL
200
10
-60
1000
V
boo
GUARANTEED
lK
500
20
0.1
Output Sink/Source Current
8
V
I
5K
j.lS;
f = 1 MHz; except as othervvise noted.
Dynamic Shift Registers
MM1402A/M M1403A/M M1404A/MM 5024A
1024-bit dynamic shift registers
general description
•
The MM1402A/MM1403A/MM1404A/MM5024A
1024-bit dynamic shift registers are MOS monolithic integrated circuits using silicon gate technology to achieve bipolar compatibility. 5 MHz
data rates are achieved by on-chip mUltiplexing.
The clock rate is one-half the data rate; i.e.,
one data bit is entered for each rjJ, and 4>2 clock
pulse.
All devices in the family can operate from +5V,
-5V, or +5V, -9V power supplies.
applications
features
•
Guaranteed 5 MHz operation
•
Low power dissipation
•
DTL/TTL compatible
•
Low clock capacitance
125 pF
•
Low clock leakage
~ 1 !J.A
.1 mW/bit at 1 MHz
•
Inputs protected against static charge
•
Operation from +5V, -5V or +5V, -9V power
supplies
Seven standard configurations
Quad 256-bit
MM1402AD
Quad 256-bit
MM1402AN
Dual 512-bit
MM1403AH
Dual 512-bit
MM1403AN
Single 1024-bit
MM1404AH
Single 1024-bit
MM1404AN
Single 1024-bit with
MM5024AH
internal pull-down resistor
•
Radar and sonar processors
•
CRT displays
•
•
Terminals
Desk top calculators
•
Disk and drum replacement
•
Computer peripherals
•
•
Buffer memory
Special purpose computers-signal processors,
digital filtering and correlators, receivers, spectral compressors and digital differential analyzers
•
Telephone equipment
•
Medical equipment
connection diagrams
Metal Can Package
Metal Can Package
Metal Can Package
Voo
V~
v~
TOP VIEW
TOP VIEW
Order Number MM1403AH
Order Number MM1404AH
Order Number MM5024AH
See Package 23
See Package 23
See Package 23
Dual-In·line Package
OUTPUTI
INPUT4
15
NC
INPUT1
Dual-I n-Line Package
Dual-I n-Line Package
NC
OUTPUT 4
"
NC
12VOD
V~
OUTPUT2
"
INPUTJ
NC
INPUT2
OUTPUT3
TOP VIEW
Order Number MM1402AD
Order Number MM1403AN
See Package 3
See Package 12
TQI'VIEW
Order Number MM1404AN
See Package 12
Order Number MM1402AN
See Package 15
1-5
absolute maximum ratings
Data and Clock Input Voltages and Supply
Voltages with Respect to V ss
+0.3V to -20V
600mWatTA = 25°C
oOe to +70°C
-65°C to +160o
300°C
Power Dissipation
Operating Temperature Range
Storage Temperature Range
e
Lead Temperature ISoldering, 10 sec)
electrical characteristics
= -25°C to +70°C, Vss = 5V ±5%, V DD = -5V ±5% or -9V ±5%, unless otherwise specified.
TA
PARAMETER
MIN
CONDITIONS
Data 1nput Levels
Logical Low Level {V1d
logical High Level (V 1H )
VIN
VIN=VSS
Clock Input Levels
Logical Low Level (Vq,d
Voo
=
v
Vss + 0.3
V
<10
500
nA
5
10
pF
Vss - 15
Vss + 0.3
Vss - 12.6
V
Min VrpL, TA
Vrp= Vss
Data Output Levels
Logical Low Level (Vod
logical High Level (V OH )
Logical Low Level (Vod
RL1 = 3k to V oo , IOL = 1.6 rnA, V OD = -5V ± 5%
RL1 = 3k to V oo , IOH = 100 pA
==
25"C
RL 1 = 4.7k to Vee, IOL = 1.6 rnA, Voo = -9V ± 5%
RL1 = 4.7k to V OD , IOH = 100pA
RL2 ': 4.7k to VOD' Voo "" -5V ± 5%
RL2 = 6.2k to V OD , V DO = -9V ± 5%
R L3 "" 3.9k to Vss
2.4
2.4
Vss -1.9
Vss - 1.9
TA = 25°C, V DO = -5V ± 5%
V
Vss + 0.3
V
V
10
1000
nA
90
125
pF
Vss - 14.7
Vss -1
Voo=-9V±5%
Clock Leakage Current
Power Supply Current (l oD )
Vss - 4.2
-5V ± 5%
Clock Capacitance
Logical High Level (V OH )
Logical High Level (V OH )
logical High Level (V OH )
UNITS
Vss-l.7
Vss - 17
Vss-l
Logical High Level (VIj.lH)
logical Low Level (V4>L)
logical High Level (VrpH)
MAX
Vss - TO.O
=-15V, TA =25°C, All Other Pins GND
Data Input Leakage Current
Input Capacitance
TYP
-0.3
3.5
-0.3
3.5
Vss -1
0.5
0.5
V
V
V
V
V
V
Vss -1
35
50
rnA
30
56
40
rnA
rnA
<10
1000
Output Logic "0", 5 MHz
Data Rate, 33% Duty Cycle,
Continuous Operation, Vq,L = Vss - 17V
TA=O°C
TA = 25°C, Voo = -9V ±5%
Output at Logic "0",3 MHz
Data Rate, 26% Duty Cycle,
Continuous Operation, VrpL = Vss - 14.7V
TA
=
45
QOC
Data Output Leakage Current
V OUT = O.OV, TA = 25°C, Vrpl = Vq,2 = Vss - lOV,
All Other Pins +5V
Internal Resistor (MM5024A)
T A =25°C
Output Capacitance
V OUT = Vss. f = 1 MHz
ac characteristics
3.7
TA = -DOC
to
Data Frequency
Clock Pulse Width (¢pw)
Clock Phase Delay Times (¢d. ¢)d)
Clock Transition Times (¢t n ¢tf)
Data Input Delay Time (tds)
Data Input Hold Time (t dH )
Data Output Propagation Delay
5.2
10
kfl
pF
+70°C, Vss = 5V ±5%
MIN
Clock Frequency (¢f)
5
Voo = -5V ± 5%
PARAMETER
4.7
rnA
nA
Note 1
MAX
2.5
Voo = -9V ± 5%
MIN
Note 1
5.0
0.130
10
10
Note 1
0.170
10
1000
UNITS
MAX
1.5
MHz
3.0
MHz
10
j.lS
Note 1
ns
1000
ns
30
60
ns
20
20
ns
90
110
ns
Note 1: Minimum clock frequency is a fUnction of temperature and clock phase delay times, ¢d and ,
time, it exists at <1>, time, (Beginning on <1>,', negative going edge and ending on the
succeeding 4>2'0 negative going edge.)
'·7
timing diagram
BIT1
.,
Tl
I
CLOCK
I
I
I•
I
I
I
---+1":rr----r-
.",-J_" I
----+I'i-=~'
Ii
CLOCK
I
I
I
I
I
I
"
:
BITN+2
BIT1
BIT2
9~-iwL--------vo,
II
II
II
II
.~---j:-- -I~.~
I
II
I
.... --r--I
9~
I
,L
I
--
I
CLOCK PERIOD-'
10%
"'---j
I
BITN+1
l~r--r~voH
I
1-
.,
alTN
BIT 2
I
I
10%
I
1- I
1
: - I ....
I--DATA PERIOD---j
I
1
I
:
I
r------------~~---------r4-----,-----.~
I
IN BIT 1
IN BIT 2
tpdH _ : : - -
;:;;;u;------------------u----------1
I
-1 J-
V
tpllL
- - - - - - - - - - - - - - - - I I I I f - - - - - - - . . . J \ - . U r B i T i - J DUTBITZ
1·8
It.
~ :~VABOVE GND (Voo )
v.,
Dynamic Shift Registers
MM4001A/MM5001A dual 64-bit dynamic shift register
MM4010A/MM5010A dual 64-bit accumulator
general description
features
The MM4001A/MM5001A dual 54-bit dynamic
shift register is a monolithic MOS integrated cir-
•
High frequency operation
•
Low power consumption 0.4 mW/bit at 1 MHz
threshold technology. The device consists of two
54-bit registers with independent two phase clocks
and is guaranteed to operate at a 2.5 MHz operating frequency for CRT display appl ications.
•
DTLlTTL compatibility
•
Minimum operating frequency
The MM401 OA/MM501 OA is a dual accumulator
function capable of operating at very high frequency. The device is also constructed on a single
silicon chip utilizing MOS P-channel enhancement
transistors. With the recirculate control line at an
MOS logic "0" state, the device functions as an
accumulator. A logic "1" state at the recirculate
control line allows external information to enter
the register serially. It is important to note that
recirculation of data is performed internally, independent of the output circuit thus making it
insensitive to output loading.
•
Application versatility
cuit utilizing P-channel enhancement mode low
connection diagrams
Metal Can Package
Metal Can Package
guaranteed
250 Hz at 25°C
"Split clock" operation, independent
control of each
register for
MM4001A/MM5001A
applications
•
Business machine
•
CRT refresh memory
•
Delay I ine memory
•
Arithmetic operations
MM4010A/MM5010A
LOGICAL HIGH LEVEL
LOAD
(V lCH )
LOGICAL LOW LEVEL
(VLcd
Recirculates "old" data
Loads "new" data
'.
Note: Pin 5 connected tncase.
TOP VIEW
Note: Pin5 conll€cted to case.
TOPVIEW
Order Number MM4001AH
Order Number MM4010AH
or MM5010AH
See Package 24
or MM5001Ah
See Package 24
+5V, -12V power
supplies, push-pull
output stage
load control truth table
r:Dr.lTROlA
'.
3.3 MHz typ
typical applications
MM4001A/MM5001A TTL/MaS Interface
MM401 OA/MM501 OA TTL/MaS I nt.rface
'-9
absolute maximum ratings
Voltage at Any Pin
Operating Temperature Range
MM40 1OA/MM4001 A
MM5010A/MM5001A
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Vss + 0.3V to Vss - 22V
_55°C to +125°C
O°C to +70°C
_65°C to +150°C
300°C
electrical characteristics
T A within operating temperature range, Vss = +5.0V ±5%, V GG = -12.0V ± 10%, unless otherwise stated.
PARAMETER
MIN
CONDITIONS
Data I nput Levels
Logical HIGH Level iV 1H }
Logical LOW Level iV 1L }
TVP
Vss - 2.0
Vss - 18.5
Data Input Leakage
VIN '" -20V. TA "" 25°C
Data Input Capacitance
VIN = O.OV. f = 1 MHz,
MAX
UNITS
Vss + 0.3
Vss - 4.2
V
V
0.01
0.5
"A
3.0
5.0
pF
All Other Pins GND
All Other Pins GND
Note 2
Load Control I nput Levels
Logical HIGH Level (V LCH )
Logical LOW Level (V LCLl
Load Control Input Leakage
V IN '" -20V, T A'" 25°C
All Other Pins GND
Load Control Input Capacitance
VIN = a.DV, f = 1 MHz,
All Other Pins GND
Note 2
Clock I nput Levels
Logical HIGH Level (V,pH)
Logical LOW Level (VrpL)
Vss + 0.3
Vss - 18.5
Vss - 4.2
V¢ = -20V, T A'" 25°C,
All Other Pins GND
Clock Input Capacitance
Vrp eo O,OV, f'" 1 MHz,
All Other Pins GND
~~:~~~:;~~~~~~:
0.5
"A
3.0
5.0
pF
Vss + 0.3
Vss - 14.5
0.05
17
Note 2
ISOURCE = -0.5 mA
ISINK = 1.6 mA
V
V
0.01
Vss - 1.5
Vss - 18.5
Clock Input Leakage
Data Output Levels
Logical HIGH Level (V OH )
Logical LOW Level (VOL)
Vss - 2.0
34
2.4
1.0
V
V
"A
20
40
pF
pF
Vss
V
0.4
V
3.0
4.5
7.0
rnA
rnA
rnA
2.5
MH,
Power Supply Current
IGG
TA = 25°C, V GG =-12V,
¢pw = 150 ns, Vss = 5.0V,
Vrj:JL "" -12V, Data=0-1-0-1
0.01 MHz ~ ¢f ~ 0.1 MHz
¢1 =
1 MHz
¢1 = 2.5 MHz
Clock Frequency (¢1)
¢tr = rptj = 20 ns, Note 1
Clock Pulsewidth (¢pw)
¢t f + ¢pw
+1>tr~
10.5/15
Clock Phase Delay Times {1>d'¢dl
Note 1
Clock Transition Times (1)t,, ¢t f )
1>t1 + ¢pw + ¢tr ~ 10.5/1$
Partial Bit Times (T)
Input Partial Bit Time (TIN)
Output Partial Bit Time (TOUT)
Note 1
2.0
3.0
5.0
0.01
3.3
0.15
10
10
I
0.20
100
100
0.20
Setup Time (t ds )
80
Data Input Hold Time (t dh )
20
0
Load Control Input Setup Time
(tLcs)
80
30
Load Control Input Hold Time
(t LCh )
20
0
Data
In~ut
30
"'n,
"'
"'
"'n,
n,
n,
"'
Data Output Propagation Delay
From 1>OUT
Delay to HIGH Level (tpdH)
Delay to LOW Level (tpdL)
See ac test circuit
150
150
200
200
Note 1: Minimum clock frequency is a function of temperature and partial bit times, TIN and TOUT,
as shown by the 1Jt versus temperature and TIN, TOUT versus temperature curves. The lowest guaranteed clock frequency for any temperature can be attained by making TIN equal to TOUT- The
minimum guaranteed clock frequency is:
Typical Power Supply Current
5
0
l-
:;l
..
.s
10
i
il:
::l
~
"
0.1
1!
"z
TIN-ToUT-
.=
- -
1!
"x
.
"
.111.0.~
1.0
4'pw=
0.3
;;
0.01
-60
-ZO
ZO
60
100
140
0.1
-60
-ZO
S!
Z.O
140
r
~ ~ -?"
i"jZ5"C
V
1.0
15
DATA = 11-1-0-1
0.01
0.10
1.0
10.0
CLOCK FREQUENCY, Of IMHz)
Typical Data Output Sink
Current vs Data Output
Voltage
Typical Data Output Source
Current vs Data Output
Voltage
..
-- -
I
I
1.5
~:~: ~,':..:~
lZ
4.0 H-5J"C
3.5 I- T.=25"C ' "
Z.5
100
I
4.5
~ 3.0
60
0.1
0.001
TEMPERATURE I"C)
Typical Power Supply Current
vs Voltage
..
ZO
150 nl
Vss '" 5.0V
H+t+H!!f--+1ftt111Hf--
.....
TEMPERATURE rC)
5.0
3.0
i
tIl,=1 MHz
9PW'" 150ns
Vss = 5.0V
'"z
;;
18
11
4
Vss = s.nv
VGG '" -12.0V
VrfJL '" -12.DV
VOL = -IZ.0V
DATA = 11-1-0-1
16
10
.§
L.-,,:
-1
-1
19
Vss - VGO IV)
VOUT
switching time waveforms
V OUT (V)
IV)
ac test circuit
-r'OPF
$oUT ClOCK
Vss-1.6V
=::.:..--~'
r-
UV~,-
,, I
---,y,:-
______
1-11
Dynamic Shift Registers
MM4006A/MM5006A dual 100-bit shift register
MM4007/MM5007 dual 100-bit mask programmable shift register
MM4019/MM5019 dual 256-bit mask programmable shift register
general description
The MM4007/MM5007 and MM4019/MM5019 are
monolithic dual 100-bit and dual 256-bit dynamic
shift registers utilizing P-channel enhancement
mode technology to achieve bipolar compatibility.
The length of the registers may be varied at manufacture by the altering of the metal mask providing
custom length of both registers. Additional connection between registers may be accomplished at the
metal mask to provide single shift register lengths
of up to 200 or 512-bits, with or without an
appropriate tap provided at the juncture. The
MM5006A is an MM5007 programmed as a dual
100-bit shift register.
For the MM4007/MM5007
N
For the MM4019/MM5019
N
= 20 to 100 bits
= 40 to 256 bits
are assigned by National upon initial order entry.
See MOS Brief 14 for a more detailed description
of the custom mask.
features
Standard +5V, -12V
power supplies
•
Bipolar compatibility
•
Mask programmable length
MM4007/MM5007
MM4019/MM5019
dual 20-100 bits
dual 40-256 bits
Low clock capacitance
MM4007/MM5007
MM4019/MM5019
65 pF max
125 pF max
•
STANDARD LENGTHS:
Dual 100-bit
Dual SO-bit
Dual 256-bit
MM4006A
MM4007/AA
MM4019
•
Standard clock frequency
250 Hz min typical at 25°C
2.5 MHz maxguaranteed over temp
•
Full temperature range
MM4007,MM4019
MM5007,MM5019
CUSTOM LENGTHS:
The programmed sh ift registers are assigned a letter
code for each option. These are designated by a
pair of letters after the number code but before
the package designation such as
MM5007/AA/H
which is a oOe to + 70°C dual SO-bit dynamic
shift register in the TO-99 package. Pattern codes
_55°C to +125°e
O°C to +70o e
applications
•
Custom shift registers
•
CRT recirculate display
connection diagrams
Dual-In-Line Package
Metal Can Packages
Note: Pin 4 connected to case.
Note: Pin 7 connected IDcase.
Nole: Pin 4 connected to case.
Standard Connection
Note: Pin 4 connected HI case.
Optional Connections
ordering information
1·12
DUAL
SO-BIT
DUAL
100-BIT
MM4007AAiO
MM4007AAiH
MM5007AAiD
MM5007AAiH
MM4006AD
MM4006AH
MM5006AD
MM5006AH
DUAL
100-BIT
MM4007D
MM4007H
MM5007D
MM5007H
DUAL
256-BIT
PROGRAMMABLE
20 to 100 Bits
PROGRAMMABLE
40 to 256 Bits
SEE
PACKAGE
MM4019D
MM4019H
MM5019D
MM5019H
MM4007XXiD
MM4007XXiH
MM5007XXiD
MM5007XXiH
MM4019XXiD
MM4019XXiH
MM5019XXiD
MM5019XXiH
2
23
2
23
absolute maximum ratings
Vss + O.3V to Vss - 22V
Voltage at Any Pin
Operating Temperature Range
-55"C to +125°C
O°C to +70"C
_65°C to +150°C
MM4006A,MM4007,MM4019
MM5006A,MM5007,MM5019
Storage Temperature Range
electrical characteristics
T A within operating temperature range, Vss = 5.0V ±5%, V GG = -12.0V ±10%, unless otherwise noted.
PARAMETER
MIN
CONDITIONS
TVP
MAX
UNITS
Vss + 0.3
V
V
Data Input Levels
Logical HIGH Level (V 1H )
Logical LOW Level {V1d
Data Input Leakage
Vss - 2.0
Vss - 18.5
VIN '" -20V, T A"" 25°C,
Vss - 4.2
0.01
0.5
MA
30
5.0
pF
All Other PinS GND
Data Input Capacitance
V1N"'O.DV,f oo 1 MHz,
All Other PinS GND
(Note 11
Clock Input Levels
Logical HIGH Level {V¢Hl
Logical LOW Level (VrpL)
Clock I nput Leakage
Vss - 1.5
Vss + 0.3
Vss -18.5
Vss - 14.5
VQ == -2.0V, T A'" 25°C,
0.05
1.0
V
V
MA
All Other PinS GND
Clock I nput Capacitance
Vrp = a.av, fool MHz,
All Other Pms GND
(Note 1)
MM4Q06A/MM5006A &
50
95
MM4007 iMM5007
MM4Q19/MM5019
Data Output Levels
Logical HIGH Level (VoHI
Logical LOW Level (VoLI
2.4
ISOURCE = -0.5 mA
ISINK = 1.6 mA
65
125
pF
pF
0.4
V
V
Vss
Power Supply Current
T A "" 2SoC. V GG "'" -12V.
rppw= lS0ns
Vss = 5.0V, V¢L == -12V.
Data == 0-1-0-1
IGG
MM4006A/MM5006A &
MM4007/MM5007
MM4019/MM5019
MM4006A!MM5006A &
MM4007/MM5007
MM4019/MM5019
s:: 0.1
MHz
2.0
2.5
3.0
3.5
mA
mA
r/!f= 1.0 MHz
4.0
5.0
6.0
7.0
mA
mA
6.0
9.0
9.0
12.0
mA
mA
2.5
MH,
0.01 MHz -:;; rpf
MM4006A/MM5006A &
MM4007/MM5007
MM4019/MM5019
Clock Frequency ((,bf)
¢t,
Clock Pulsewidth (4)pwl
¢It I + ¢pw + rt>t, s:: 10.5 /lS
Clock Phase Delay Times (4)d, ¢d)
(Note 2)
Clock Transition Times (rt>t" ¢ltf}
¢tf + ¢pw + ¢It,
Partial Bit Times (T)
Input Partial Bit Time (TIN}
Output Partial Bit Time (TOUT)
(Note 2)
.01
= rt>tf = 20 ns
3.3
10
0.15
10
M'
"'
s:: 10.5 /lS
1.0
100
100
0.20
0.20
M'
M'
M'
Data Input Setup Time (tds )
80
30
m
Data Input Hold Time ltdh)
20
0
n'
Data Output Propagation Delay
from rt>OUT
Delay to High Level (tpdH )
Delay to Low Level (tpdL )
(See ac test circuit)
150
150
200
200
m
n,
Note 1: Capacitance is guaranteed by periodic testing.
Note 2: Minimum clock frequency is a function of temperature and partial bit times (TIN and TOUT) as shown by the cPf
versus temperature and TIN. TOUT versus temperature curves. The lowest guaranteed clock frequency for any temperature
can be attained by making TIN equal to TOUT. The minimum guaranteed clock frequency is:
1
¢f(min):= TIN + TOUT' where TIN and TOUT do not exceed the guaranteed maximums.
Note 3: Minimum clock frequency and partial bit time curves are guaranteed by testing at a high temperature point.
1-13
performance characteristics
...
Guaranteed Minimum Clock
Guaranteed Maximum TIN
Frequency vs Temperature
and TOUT vs Temperature
(Note 2)
(Note 2)
10
100
~
-
~
~
TIN orTou ,== 200 ns
]
A
1.0
~
~
""
z"
;;;
JZ
~
-
10
>=
~
TIN "'TOUT- - -
"''''
0.1
.."x
"
1.0
"
I"
0.1
0.01
-60
-20
20
60
100
-20
140
20
Typical Data Output Sink
Current vs Voltage
12
'"z
0;
140
-1
VOUT (V)
Typical Power Supply Current
MM4007/MM5007
vs Voltage MM4019/MM5019
10
10
.1 L
B
-
-55'C
0:
....-tI
£
0
0
I.,or-
4
I.-
Vss' 5.0V
1"'1""'"
VGG '" -12.0V
V¢L =-12.0V
¢.-I.OMHz
9pl'l ~ 150 ns
9
1 1
1 1
I-
i
100
Typical Power Supply Current vs
Voltage MM4006A/MM5006A
10
£
60
TEMPERATURE ('C)
AMB'ENTTEMPERATURE ('C)
0:
Typical Data Output Source
Current vs Voltage
Vss ~ 5.DV
-
I
I
1 1
14
-1
15
16
17
18
14
19
r- _~5oJ -I-""
1 1
-
TA =25°C
---
~_-1" 1 ~~:J
TA=25°C
1 1
V,,'l ~ -12.0V
DATA D-l-D-t
-n
15
_f-
1
1..1--
125'C
1 1
1 1
16
17
VOUT (V)
Typical Power Supply Current
Typical Power Supply Current vs Clock
vs Clock Frequency MM40191
Frequency MM4006A1MM5006AI
MM5019
MM4007/MM5007
10.0
10.0
:1311
~55'~ ~ 1=
TA=25°C
-55'C
3.0
0:
£
0
1.0
.!<
~
lit!
I
3.0
~
[\1
F
TA=2SoC
0:
£
125'C
Jl
~
~
~
1.0
125'C
¢!ow=150n,
Vss~5.0V
0.3
0.3
[1
0.1
0.001
VGG=~12.0V
VOL ~-12.OV
DATA = 0-1-0-1
0.001
0.01
0.10
1.0
CLOCK FREQUENCY. q" (MHz)
switching waveforms
10.0
0.01
0.10
1.0
10.0
CLOCK FREQUENCY. q" (MHz)
ac test circuit
'5V
~INeLOCK
¢OUTCLOCK _ _ _V'-~__''''.5V'''
1-14
18
19
Dynamic Shift Registers
s:
s:
~
...o
w
"-
MM4013/MM5013 1024-bit dynamic shift register/accumulator
(J1
general description
The MM4013/MM5013 1024-bit dynamic shift
register/accumulator is an MOS monolithic integrated circuit using P-channel enhancement mode
low threshold technology to achieve direct bipolar
compatibility. There is on-chip logic to load and
recirculate data, and a read control for enabling the
bus-ORableTRI-STATETM push pull output stage.
features
•
Standard +5V, -12V
power supplies
No pull down or
pull up resistors
required
Bipolar compatibility
•
Package option
•
Low clock capacitance
¢f min ~ 400 Hz @
25°C typ
¢f max ~ 2.5 MHz
over temp. guaranteed
•
Wide frequency range
•
Built-in recirculate
•
TRI-STATE output
•
Full temperature operation
MM4013
MM5013
Exclusive-OR and
recirculate loop on-chip
Allows wire-OR bus
structure on output
-55°C to +125°C
O°C to +70°C
applications
•
"Silicon Store" replacement for drum and disc
memories
TO-99 or
molded 8-pin mini-DIP
•
File memories
160 pF max
•
CRT refresh
connection diagrams
Metal Can Package
WRITE
CONTR(lL
DATA
Order Number MM4013H
orMM5013H
"
See Package 24
:fj",,"''':;;;:,"
3
•
4
5
Order Number MM4013D
orMM5013D
See Package 1
Order Number MM5013N
See Package 12
Vs;s
typical applications
truth table
TTL/MaS Interface
(Positive Logic)
Logic "1" '" V!H '" Logical HIGH Level
Logic "0" '" V I L "" Logical LOW Level
I
L- - - -
s:
s:
-"'~I;:"':...
I
- - - - .J
•. - - - - - ,
, - - - - - -,1'-I
,
I
I
,
,
,-I
,
I
'-I
,.
,
L----~'~f"'2...----.J
-12V!1IN
I
I
WRITE
,
L~IT~.J
*
READ
FUNCTION
Recirculate
Output 0 isabled
Recirculate
Output Enabled
Write Mode
Output Disabled
WnteMode
Output Enabled
...o
w
absolute maximum ratings
Voltage at Any Pin
Operating Temperature Range MM4013
MM5013
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Vss + 0.3 to Vss - 22
-5S"C to +12S"C
O°C to +70"C
-6SoC to +150"C
300°C
electrical characteristics
TA within operating temperature range, Vss == +5.0V ±5%, VGG
= -12.0V ± 10%, unless otherwise noted.
CONDITIONS
PARAMETER
Data Input Levels
Logical HIGH Level (V 1H )
Logical LOW Level (V ILl
MIN
TYP
MAX
Vss + 0.3
Vss -4.2
Vss - 2.0
Vss -18.5
UNITS
V
V
Data Input Leakage
VIN '" -20.0V, TA = 2SoC,
All Other Pins GND
0.01
0.5
"A
Data Input Capacitance
VIN = a.DV, f -; 1 MHz,
All Other Pins GND
3.0
5.0
pF
Control Input Levels
Logical HIGH Level (V H )
Logical LOW Level (V L )
(Note 1)
Vss + 0.3
Vss - 2.0
Vss - 18.5
Vss - 4.2
V
V
Control Input Leakage
V IN '" -20.0V, T A '" 25°C,
All Other Pins GNO
0.01
0.5
"A
Control Input Capacitance
V IN '" O.OV, f '" 1 MHz,
All Other Pins GND
(Note 1)
3.0
5.0
pF
Clock Input Levels
Logical HIGH Level (VH)
Logical LOW Level (V\ilL)
V'" -20.0V, TA '" 25°C,
All Other Pins GND
Clock Input Capacitance
V '" a.ov, f '" 1 MHz
All Other Pins GND
(Note 1)
Data Output Levels
Logical HIGH Level (V OH )
Logical LOW Level (VOL)
'SOURCE'" -0.5 mA
ISINK '" 1.6 mA
Data Output Leakage
VOUT '" -5.0V, T A'" 25°C
Output in High Impedance State
Power Supply Curnmt
TA '" 25°C, VGG '" -12V,
Cppw'" 150 ns, Vss '" 5.0V,
VL'" -12V, Data'" 0-1-0-1
0.01 MHzSCPfSO.1 MHz
CPf'" 1.0MHz
CPf = 2.5 MHz
IGG
Vss +0.3
Vss - 14.5
Vss - 1.5
Vss - 18.5
Clock Input Leakage
Clock Frequency (CPf)
CPt, '" cpt f
Clock Pulsewidth (cppw)
CPtf
0.05
140
2.4
20 ns, (Note 2)
0.01
0.15
'"
Clock Phase Delay Times (CPd, ~d)
(Note 2)
Clock Transition Times (cpt" CPtf)
¢tf + ¢pw + cpt,::;';: 10.5 /J.$
Partial Bit Times (TJ
Input Partial Bit Time (TIN)
Output Partial Bit Time (TOUT)
(Note 2)
190
"A
5.3
3.0
8.0
10.3
15.0
rnA
rnA
rnA
2.5
MH,
3.3
10
0.2
0.2
80
20
Write Setup Time (t ds)
80
Write Hold TIme (tdhl
20
pF
10.0
1.0
Data Input Hold Time (toh)
"A
V
V
10.0
Data Input Setup Time (t ds )
V
V
V"
0.4
1.60
+ CPPW + CPt, S 10.5/J.s
1.0
100
100
30
"'
"'
"'
"'
30
Read Setup Time (t RS )
Read Hold Time (t Rh )
Data Output Propagation Delay
from CPOUT
Delay to HIGH Level (tpd1 )
Delay to LOW Level (tpdO)
(seeac test circuit)
150
150
200
200
150
150
200
200
150
150
200
200
Propagation Delay From
Read Control Disable to
HIGH Impedance State:
Delay From HIGH Level (tlH)
Delay From LOW Level (tOH)
Propagation Delay From
Read Control Enable to
LOW Impedance State:
Delay to HIGH Level (t Hl )
Delay to LOW Level (tHO)
Note 1: Capacitance is guaranteed by periodic testing.
Note 2: Minimum clock frequency is a function of temperature and partial bit times (TIN and TOUT) as shown by the CPf
versus temperature and TIN. TOUT versus temperature curves. The lowest guaranteed clock frequency for any temperature
can be attained by making TIN equal to TOUT. The minimum guaranteed clock frequency is:
1
f(min) = TIN + TOUT' where TIN and TOUT do not exceed the guaranteed maximums.
Note 3: Minimum clock frequency and partial bit time curves are guaranteed by testing at a high temperature paint.
1-16
s:
s:
perform ance characteristics
Guaranteed Minimum Clock
Frequency vs Temperature
(Note 2)
~
Guaranteed Maximum TIN
and TOUT YS T emperatu fa
(Note 2)
,00
!
,0 I '
-60
-20
CTI
...ow
r~I~11
V,,-'-'2.0V
~~
V¢H '" 3.5V
DATA' O·H)·' -55"C
If
.
~
iii
V
'0
,0
J 1.0
~~
s:
s:
.;.., ,50 ns
Vss = s.nv
VGG = -12.0V
J
TIN. TOUT
.......
Typical Power Supply Current
vs Clock Frequency
,ook
TINORToUT-200n
...wo
'.0
;;O.'~.
20
60
,00
'40
AMBIENT TEMPERATURE rCI
Typicel Power Supply Current
vs Voltage
EEEf
0.0'
-60
0., W..l.WIIIL.l..il
-20
20
60
'00
AM81ENT TEMPERATURE I"CI
,40
0.00,
0.0,
,.0
0.1
'0.0
CLOCK FREQUENCY ... IMHzl
Typical Data Output Source
Current vs Data Output
Voltage
Typical Data Output Sink
Current vs Data Output
Voltage
9.0
..
8.0
...
7.0
-55"C
...n
6.0
~
5.0
J1
4.0
_t-"I-'"
....
.'"
~
'25"C
.. ' , MHz·
~ ~'25"C~ -1/}pw=150ns
G
Vss' 5.OV
V=='-------'
140UTPUT2A
130UTPUT3A
LOAD CONTROL 2 5
12¢oUT
11 ~IN
INPUT37
Vss 8
::L>-{C~-'-(~d--lIl OUTPUllS
L======='--~_9
Note: Pin 8 connected to
LOAD CONTROL 3
~ase.
TOPVIEW
Order Number MM4015AD or MM5015AD
See Package 3
typical applications
Typical Arithmetic Configuration
TTL/MaS Interface
r -I~., , ______ 1______ -, r-;:;::-I,~"
TTliOTl
MM4015A!MM50t5A
I I
load Control
logical Low - Data IS loaded
logical High - Data
" L U'L
I I
I
IS
Recirculated
I
I
The above cirellll WIll generate the functlOll"
A + C 'B
B~C
A - A
119
absolute maximum ratings
Voltage at Any Pin
Operating Temperature Range MM4015A
MM5015A
Storage Temperature Range
Vss + 0.3V to Vss - 22.0V
_55°C to +125°C
O°C to +70 o C
_65°C to +150°C
electrical characteristics
T A within operating temperature range, Vss = 5.0V ±5%, VGG = -12.0V ±10%, unless otherwise stated
MIN
CONDITIONS
PARAMETER
TYP
MAX
UNITS
Vss + 0.3
Vss - 4.2
V
V
Data Input Levels
Logical HIGH Level (V JH )
Vss - 2.0
Vss - 18.5
Logical LOW Level (V1LJ
Data Input Leakage
VIN '" -20.aV, TA '" 2SoC,
All Other Pins GND
Data Input Capacitance
VIN '"
a.av, f '" 1 MHz,
0.Q1
0.5
pA
3.0
5.0
pF
All Other PinS GND
See Note 2
Load Control I nput levels
Logical HIGH Level (V1Hl
Logical LOW Level (V 1L)
Load Controllnpul Leakage
Load Control Input Capacitance
Vss + 0.3
Vss - 4.2
Vss - 2.0
Vss - 18.5
VIN '" -20.0V, T A"" 2SoC,
All Other Pins GND
VIN ""
a.ov, f '" 1 MHz,
V
V
0.01
0.5
pA
3.0
5.0
pF
All Other Pins GND
See Note 2
Clock Input Levels
Logical HIGH Level(V!fJH)
Logical LOW Level (Vq'.lL)
V¢=-20V,TA '" 25°C,
All Other Pins GND
Clock Input Capacitance
V¢ '" O.OV, f == 1 MHz,
All Other Pins GND
See Note 2
Data Output Levels
Logical HIGH Level (VOH )
Logical LOW Level (VOL)
Vss + 0.3
Vss - 14.5
Vss - 1.5
Vss - 18.5
Clock Input Leakage
0.05
45.0
2.4
ISOURCE '" -0.5 mA
ISINK == 1.6 mA
V
V
1.0
pA
60.0
pF
Vss
0.4
V
V
Power Supply Current
IGG
T A'" 25°C, VGG == -12V,
¢pw == 150 ns, Vss == +5.0V,
V¢L oo-12V,Data==0-1-0-1
0.01 MHz
s: ¢f s: 0.1 MHz
¢f ==
1 MHz
¢f == 2.5 MHz
Clock Frequency (¢f)
¢t, '" ¢tf == 20 ns, Note 1
Clock Pulsewidth (¢pw)
¢tf + ¢pw + ¢tr
Clock Phase Delay Times (¢d, ¢d)
Note 1
Clock Transition Times (¢tr, ¢tf)
¢tf + ¢pw 1- ¢tr S 10.5 j.1S
Partial Bit Times (T)
Input Partial Bit Time (TIN)
Output Partial Bit Time (T OUT)
Note 1
s: 10.5 j.1s
0.01
2.2
4.5
3.0
7.0
8.5
rnA
rnA
rnA
3.3
0.15
5.5
2.5
MH,
10.0
p,
1.0
ps
10
n'
0.20
0.20
100
100
P'
ps
80
30
ns
Data Input Hold Time (tdhl
20
0
ns
Load Input Setup Time (tis)
80
30
ns
Load Input Hold Time (tlh)
20
0
ns
Data Input Setup Time
(~s)
Data Output Propagation Delay
From ¢OUT
Delay to HIGH Level (tpdH)
Delay to LOW Level (tpdd
150
150
200
200
ns
ns
Note 1: Minimum clock frequency is a function of temperature and partial bit times (TIN and TOUT) as shown by the CPt
versus temperature and TIN, TOUT versus temperature curves. The lowest guaranteed clock frequency for any temperature
can be attained by making TIN equal to TOUT. The minimum guaranteed clock frequency is:
¢f(min)
1
:=
TIN
+ TOUT
, where TIN and TOUT do not exceed the guaranteed maximums.
Note 2: Capacitance is guaranteed by periodic testing.
1·20
s:
s:
performance characteristics
Typical Minimum Clock
Typical Maximum Partial
Frequency vs Temperature
(Note 1)
Bit Times vs Temperature
100
r-
u
TIN Of TOUT
=
~
,.
..Y
1.0
;::
"
~
3.0
10
0
l-
~
E
i
,:
o
0
~
~
10.0
i
200 ns
z
:,.r/
0.1
l-t-
TIN" To UT -
,.~
1l
"x
~
0.01
-20
20
60
100
140
-60
6.0
~
.s
0
0
4.0
»
-20
20
"
60
100
0.1
140
0.001
0.1
0.01
1.0
10.0
CLOCK FREOUENCY.,p, (MHz)
Data Output Sink
Current vs Voltage
12
iI'>f=l MHz
.j:::Io
o
.....
, /~
Vss" +S.DV
10 I---+_-+_+_VGG' -12.0V
......: ~
'"
V¢L" -12.0V
V-
I-- t-"' i--'"' ~k--;5"e ~ t:: I-- """ ~I TA'25"e
125"e -
3.0
125"e
2.0
15
16
17
18
19
1
OUTPUT VOLTAGE (VI
Vss - VGG (V)
switching time waveforms
='---------.,"0
r-
1.5V~
-1
-1
OUTPUT VOLTAGE (VI
ac test circuit
'" I
.Jy.;-
..._ _ _ _ _ _ _
1·21
Dynamic Shift Registers
MM4016/MM5016 512-bit dynamic shift register
general description
The MM4016/MM5016 512-bit dynamic shift register is a monolithic MOS integrated circuit utilizing P channel enhancement mode low threshold
technology to achieve bipolar compatibility_ An
input tap provides the option of using the device
as either a 500 or 512-bit register.
• Military and Commercial Temperature Ranges
MM4016
_55°C to +125°C
MM5016
O°C to +70°C
•
Low power dissipation
< 0.17 mW/bit
at 1 MHz max.
< 30/lW/bit
at 100 kHz typo
features
•
Bipolar compatibility
+5V, -12V operation
No pull-up or pull-down
resistors required.
TO-1 00 or choice of two
Dual-I n- Li ne Packages
•
Package option
•
Fewer clock drivers required
•
System flexibility
applications
• Glass and magnetostrictive delay line replacement.
• CRT refresh memory.
Clock line
capacitance of
100 pF typ
• Radar delay line.
300 Hz guaranteed min.
operating frequency at 25°C.
500 or 512-bit register length.
• Drum memory storage (silicon store)
• Long serial memory.
connection diagrams
Metal Can Package
Dual-I n- Line Package
Dual-In-Line Package
Ne
NC
SOO·81T
INPUT
NC
OUTPUT
Ne
Ne
v"
v"
Note: Pin 5 connected to case.
TOPVIEW
Note: Pin B connected to case.
TOPVIEW
TOP VIEW
Order Number MM4016H
orMM5016H
Order Number MM40160
orMM5016D
See Package 24
See Package 3
typical application
TTL/MOS Interface
'5V
Note: The unused input pin must be connected to vss.
1-22
Order Number MM5016N
See Package 12
s:
s:
.j::o
absolute maximum ratings
....
0
Voltage at Any Pin
Operating Temperature Range
Vss + 0.3V to Vss -22V
_55°C to +125°C
O°C to +70°C
_65°C to +150°C
300°C
MM4016
MM5016
Storage Temperature Range
Lead Temperature (Soldering, 10 secl
O'l
........
s:
s:
U1
....0
electrical characteristics
O'l
TA within operating temperature range, Vss::: +5.0V ±5%, VGG::= -12.0V ±10%, unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Vss + 0.3
Vss - 4.2
V
V
Data I nput Levels
Vss - 2.0
Vss - 18.5
Logical HIGH Level (V'HI
Logical LOW Level (V'LI
Data Input Leakage
V'N = - 20V, T A = 25°C,
All Other Pins GND
Data I nput Capacitance
V'N = O.OV, f = 1 MHz,
All Other Pins GND, (Note 2)
Clock Input Levels
Logical HIGH Level (V¢H)
Logical LOW Level (V¢L)
VIjJ = -20V, T A = 25°C,
All Other Pins GND
Clock Input Capacitance
VIjJ = O.OV, f = 1 MHz,
All Other Pins GND, (Note 2)
Power Supply Current
IGG
0.5
jlA
3.0
5.0
pF
Vss - 1.5
Vss - 18.5
Clock Input Leakage
Data Output Levels
Logical HIGH Level (V OH )
Logical LOW Level (VOL)
0.01
Vss + 0.3
Vss - 14.5
0.05
100
2.4
ISOURCE = -0.5 mA
ISINK = 1.6 mA
1.0
120
Vss
0.4
V
V
jlA
pF
V
V
TA = 25°C, VGG = -12V,
IjJpw = 150 ns
Vss = 5.0V, VIjJL = -12V,
Data = 0-1-0-1
0.01 MHz:::; 1jJ,:::; 0.1 MHz
1.0
2.0
mA
1jJ,
=
1 MHz
3.5
5.0
mA
1jJ,
= 2.5 MHz
7.0
10.0
mA
3.3
2.5
MHz
= IjJt, = 20 ns,
Clock Frequency (1jJ,)
IjJt,
(Note 1)
Clock Pulsewidth (ljJpw)
IjJt, = IjJpw + IjJt,:::; 10.5
Clock Phase Delay Times (ljJd, ;Pdl
(Note 11
Clock Transition Times (IjJt" IjJt,l
IjJt, + IjJpw + IjJt,:::; 10.5 jlS
Partial Bit Times (T)
(Note 1)
jlS
0.01
0.15
jlS
1
jls
100
100
jls
ns
0.20
0.20
Input Partial Bit Time (T,NI
Output Partial Bit Time (T ouTI
10
10
jlS
Data Input Setup Time (td,)
80
30
ns
Data Input Hold Time (toh)
20
0
ns
Data Output Propagation Delay
from IjJOUT
Delay to HIGH Level (tpdHI
Delay to LOW Level (tpdel
See ae test circuit.
150
150
200
200
ns
ns
Note 1: Minimum clock frequency is a function of temperature and partial bit times (TIN and TOUT) as shown by the CPf
versus temperature and T, N, TOUT versus temperature curves. The lowest guaranteed clock frequency for any temperature
can be attained by making TIN equal to TOUT. The minimum guaranteed clock frequency is:
¢f(min)
=
1
TIN + TOUT
, where TIN and TOUT do not exceed the guaranteed maximums.
Note 2: Capacitance is guaranteed by periodic testing.
1-23
performance characteristics
Typical Maximum TIN
and TOUT vs Temperature
(Note 1)
Typical Minimum Clock
Frequency vs Temperature
(Note 1)
Typical Power Supply
Current vs Clock Frequency
10.0
100
50
~ ZO
~ 10
.2
3.0
"-
5.0
C
'§1'0.~
j
Z
i
!
~
2.0
1'-
1.0
o.Z
ZO
60
100
140
-60
-20
TEMPERATURE ('C)
.. -I MHz
I/lpw=150m
Vss" 5.DV
4.5
VOL" -IZV
DATA
4.0
~
3.5
1 3.0
Jl
"1:::!?
T."25'C"..
......,.....
2.0
1.6
".... "....
16
15
0.1
0.001
140
0.10
1.0
Typical Data Output Sink
~
1...
~
or:
1l
~
~
;;
4 1--1--+-+-+'1""""0;::1
Vss' 5.0V
V•• ' -12.0V-+--I--1--I
VOL' -12.0V
-1
19
Vss - V•• (V)
Your (V)
Your (V)
ac test circuit
switching time waveforms
.,v
DATAIIlf'UT
4.
4tttoCLOCK
..
'
~CLOCK
----~,.-.:-:
...::Ii,
------
DATA OUTPUT
'·24
10.0
CLDCK FREOUENCY," (MHz)
CUrrent vs Voltage
,...,
16
0.01
Typical Data Output Source
."
17
100
Current vs Voltage
125'~ "...
~
1.0
DATA" 0-1-0-1
1'1..
60
-55'C
"..'
2.5
ZO
VOG .. -12.0V
H+HlIIII-+HttHII--I VOL' -12.0V
TEMPERATURE rCI
Typical Power Supply
Current vs Voltage
5.0
Vss' 5.0V
1
0.1
-zo
¢PW=150ns
0.3
MM5016~ MM4016
0.5
'''r
'---------'~
ou~:~~ O--...- ..........I-....-I*'.H~-,
Dynamic Shift Registers
MM4017/MM5017 dual 512-bit dynamic shift register
general description
The MM4017/MM5017 dual 512-bit dynamic shift
register is a monolithic MOS integrated circuit
utilizing P channel enhancement mode low threshold technology to achieve bipolar compatibility_
An input tap provides the option of using either
register in a 500-bit or 512-bit configuration_
• System flexibility
features
•
• Military and Commercial Temperature Ranges
_55°C to +125°C
MM4017
MM5017
O°C to +70°C
• Standard +5V, -12V supplies
Bipolar compatibility_ No pull-up
or pull-down
resistors requ ired_
•
Package option TO-l00 or Dual-I n-Line Package_
•
Fewer clock
drivers required
400 Hz guaranteed
min_ operating frequency
at 25° C_ 500 or
512-bit register length_
Low power dissipation
<0.17 mW/bit
at 1 MHz max.
< 30 jJ.W/bit at
100 kHz typo
applications
• Glass and magnetostrictive delay line replacement
• CRT refresh memory
• Radar delay line
• Drum memory storage (silicon store)
• Long serial memory
Clock line
capacitance of
140 pF typ_
connection diagrams
Dual-I n-Line Package
Metal Can Package
Order Number MM4017D
orMM5017D
Se. Package 3
Order Number MM5017N
See Package 15
Order Number MM4017H
orMM5017H
S•• Package 24
v.
TOP VIEW
typical applications
1000 or 1024 Bit Accumulator
-----t..J
REI:IIICUlATEIWR1TE---I....
--1_,.
D";:-1--__
TTL/MOS I ntarfa..
II
L_r_J
DTLffTl
":"
I I
1i1111M111/MMUIJ
I
L----l~i;;---_-l
-1ZVJ'0%
Not!: Unused inputb) should be tied to Vss.
1·25
.......
0
absolute maximum ratings
:E
:E.
Voltage at Any Pin
Vss + 0.3 to Vss - 22
Operating Temperature MM4017
_55°C to +125°C
O°C to +70~C
MM5017
-65°C to 150°C
Storage Temperature
300°C
Lead Temperature (Soldering, 10 sec)
LC')
...
"....
0
~
electrical characteristics
:E
:E
T A within operating temperature range, Vss = +5.0V ±5%, VOG = -12.0V ±lO%, unless otherwise specified.
PARAMETER
CONDITIONS
Data I nput Levels
Logical HIGtl Levei (V,H)
Logical LOW Level (V-,d
L
TYP
MIN
Vss - 2.0
Vss-18.5
MAX
UNITS
Vss + 0.3
Vss - 4.2
V
V
Data I nput Leakage
Y'N = -20V, T A = 25°C,
All Other Pins GND
0.01
0.5
/lA
Data I nput Capacitance
Y'N = OV, f= 1 MHz,
All Other Pins GND
3.0
5.0
pF
Clock Input Levels
Logical HIGH LeVel (V¢H)
Logical LOW Level (V",d
Clock Input Leakage
V",= -20V, TA = 25°C,
All Other Pins GND
Clock Input Capacitance
V",=OV,f=lMHz,
All Other Pins GND
Data Output Levels
Logical HIGH Level (V OH )
Logical LOW Level (Vod
Vss + 0.3
Vss - 14.5
Vss - 1.5
Vss -18.5
0.05
140
2.4
ISOURCE = -0.5 mA
ISINK = 1.6 mA
1.0
160
Vss
0.4
V
V
jJ.A
pF
V
V
Power Supply Current
TA = 25°C, VGG = -12V, \Opw = 150 ns
Vss = 5.0V, V",L = -12V,
Data = 0-1-0-1
0.01 MHz 5: \0, 5: 0.1 MHz
IGG
\0, =
\0, =
Clock Frequency
(\0,)
\Ot, = \Ot, = 20 ns, Note 1
Clock Pulsewidth (\Opw)
\Ott + \Op~ + \Ot, 5: 10.5 jJ.S
Clock Phase Delay Times (\Od, ibd)
Note 1
Clock Transition Times (\Ot" \Ot,)
\Ot, + \Opw + \Ot, 5: 10.5 jJ.S
Partial B it Times (T)
Input Partial Bit Time (T'N)
Output Partial Bit Time (TOUT)
2.1
3.2
mA
1 MHz
7.0
10.5
mA
2.5 MHz
10.0
14.0
mA
3.3
2.5
MHz
0.01
0.15
10
10
jJ.S
ns
0.20
0.20
1.0
jJ.S
Note 1
Note 1
jJ.S
jJ.S
Data Input Setup Time (td,)
80
30
ns
Data Input Hold Time (tdh )
20
0
ns
Data Output Propagation Delay
from4JouT
Delay to HIGH Level (tpdH)
Delay to LOW Level (~cl
See ae test circu it
150
150
200
200
ns
ns
Note 1: Minimum clock frequency is a function of temperature and'partial bit times (TIN and TOUT) as shown by the €f>t
versus temperature and TIN. TOUT versus temperature curves. The lowest guaranteed clock frequency for any temperature
can be attained by making TIN equal to TOUT- The minimum guaranteed clock frequency is:
tlmin) =
1
, where TIN and TOUT do not exceed the guaranteed maximums.
TIN + TOUT
Note 2: The curves are guaranteed by testing at a high temperature point.
Note 3: Capacitance is guaranteed by periodic testing.
1-26
performance characteristics
Guaranteed Maximum
Guaranteed Minimum Clock
Frequency vs Temperature
(Notes 1 and 2)
IOo~_
lOOk
~
>
~
10k
j lo~I'~~~~~~~~~
~TIN OR TOUT -200 n
~
~ l.ok
Eo Eo
TIN. TOUT
':1.
~
o
"
m_M
o.olEfE
-20
20
60
100
-60
140
-20
Typical Power Supply
Current YS Voltage
_55°C-,
7.0
6.0
~
..so 5.0
~
~
B
1.0
0.1 W.J.illlllL-Ll.LLUJiL.LllIJJJII...J..UllIW
20
60
100
140
0.001
0.01
0.1
1.0
10.0
CLOCK FREQUENCY,¢, (MHz)
Typical Data Output Source
Current vs Data Output Voltage
Typical Data Output Sink
Current vs Data Output Voltage
2.0
1.0
18
17
~-4-jLf.~~~4---+-~
w
Vss '" 5.0V
Vq,L = -12.0V
Vf)
tf
Clock Pulsewidth (pw. q.ip;,j)
cptr =, and 2 clock pulse.
•
Low power dissipation
1201lW/bit
at 1 MHz rate 0° C, gu aranteed
•
Low clock capacitance
•
Wide operating temperature range
MM4025,MM4026,MM4027 -55°C to +125°C
MM5025,MM5026,MM5027
The MM4025/MM5025 and MM4027/MM5027
have on-chip logic to load and recirculate data.
The MM4026/MM5026 has an individual logicselect line to load one of the two inputs on each
of the 1024-bit registers.
•
•
O°C to 70°C
applications
•
features
190pFmax
"Silicon store" replacement for drum and disc
memories
Bipolar compatibility
Standard +5V, -12V
power su pplies
6 MHz
High frequency of operation
guaranteed
•
CRT displays
•
Buffer memories
logic and connection diagrams
Military Temperature Range
Dual-In-Line Package
Dual-In-Line Package
Flat Package
Order Number MM40250
or MM50250
See Package 3
Order Number MM40260
or MM50260
Order Number MM4027F
or MM5027F
See Package 26
See Package 3
Commercial Temperature Range
Dual-In-Line Package
Dual-I n-Line Package
·
m
Dual-In-Line Package
~,
LOAD
[ONTROL
Order Number MM5026N
See Package 13
See Package 15
[JATA
I/TI~UT
~""
3
!lATA
4
OUTPUT
Order Number MM5025N
Voo
J
2
,
~
~
I
6
VGG
5
">
Order Number MM5027N
See Package 12
1·31
absolute maximum ratings
+0.3 to -20.0V
Voltage at Any Pin With Respect to Vss
Operating Ambient Temperature Range
-5SoC to +12SoC
O°C to +70°C
-6SoC to +150°C
300°C
MM4025,MM4026,MM4027
MM5025,MM5026,MM5027
Storage Temperature Range
lead Temperature (Soldering, 10 sec.)
electrical characteristics
Vss = +5.0V ± 5%, Vee = GND, VGG = -12.0V ±10%
TA within operating temperature range unless otherwise stated.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Vss + 0.3
V
V
Data Input Levels
Logical High Level (V"",)
Logical Low level IV ILl
Vss - 1.7
Vss -10
Data Input Leakage
Y'N = -10V, TA = 2SoC, All other pins GND
Data Input Capacitance
Y'N =
av, f = 1 MHz, All other pins GND
INote 1)
Vss - 4.2
0.01
0.5
~A
2.5
5.0
pF
V ss "-t versus
temperature and T1. T2 versus temperature curves. The lowest guaranteed clock frequency for any temperature can be
attained by making Tl equal to T2. The minimum guaranteed clock frequency: CPf (min) "" 1/(T 1 + T2) where T 1 and T2 do
not exceed the guaranteed maximum.
Note 3: Minimum clock frequency and partial bit time curves are guaranteed by testing at a high temperature point.
Note 4: For data pattern of 1111000011110000 etc.
Note 5: Maximum frequency limited by maximum package power dissipation for MM4025, MM4026 and MM4027.
1-32
guaranteed performance characteristics
Guaranteed Minimum Clock
Guaranteed Maximum T 1 and
Frequency vs Temperature
(Note 21
T2 vs Temperatura (Note 2)
100 _ _
,
]
~
i
..z>=
11
10 1
"-
~ 1.0
. . .
~E!E!§fE!!3
;;0.1~1!!I
0.01 L--'--'-...I.........J..................1.......1..-l................
-60
-20
20
60
100
140
AMBIENT TEMPERATURE I"C)
AMBIENT TEMPERATURE I"C)
typical performance characteristics
Power Supply Current
Power Supply Current vs
vs Data Rate
VOO
lo~g
~
i
~l'OM.~ffl
ffi
::::
t/Jpw=80ns
I
!C
~
_
-
~~~~~'~V"_lB'5V
"J
.!
===
~
.01
I'
o ro
TA"+25"C
,,=
VGG =-1B.5V
~
~
~
~
00
n
00
54
~
...
~,~
.
00
I-
DATt;:'~
~~
~::O"C
R "125"L..r-r-
Power Supply Current vs
~"~
Vss= GND 3.0 MHz _
t/Jpw= 80 ns
56
52 I-+-+-~++ VGG"-18.5V-
z
..
56
f--+--",,++-+.f"
j
~
a: 48
"'
44
DATA::: Note 4
54
1 52
J
~
50
C 40
a:
36
46
32
44
0
40
~F~~~~~~~~~T~A~-+~Z~5"~C
24
F7~~;ro<,,:,--+..J.::~j-~:: ::;;~C
16 ;;...-10
-12
-6.0
80
TEMPERATURE I"C)
120
/
-14
-18
-20
Maximum Clock Frequency
vs Temperature
/" ~
."
4.7
~
4.6
=
4.5
'-
VGG = -18.5V
y,p"-18.5V
VDD "' -5.3V
vss "' GRD
th"'3mHz
DATA'" Note 4
VOD '" -5.0V
-17.0V
VdI=-11.0V
Vss"GND-
VGG '"
......... ~
.....
4.4
V
80
-16
V.IV)
V
J
48
-40
32
Power Supply Current vs
Clock Pulse Width CPPW
f..:
i:l
,...
-5.5
58
68"
64 1-''i:~-t-t-''''r--t-~:::1~5~~ -
\
r-- r--
Voo (V)
Temperature
60
I....
r--r-- f-ITA~
..... 1-
100 (mA)
l'
T~"~55"~ ~
--
V¢"-1&'5V
V.. -GND
V:!
2.0
15
co
9.0
VaG =-lS.5V
Vss' GNO
V. . -14.5V
TA =+25°C
8.5
8.0
-4.5
I
'"in
1.6
2
1.4
I
TA =+12SoC
12
L
././
./ /
//
"'" "">
'"
VV
1.8
~
~:80ns
~-bl.+i5"C
!-- To· 85°C
1....
V
:l:
TVPical Data Output Source
Current .. Data Output
Voltage
V
!....
'"
V
VaG" Vss -14.5V
To·~25°:b
I-TA::+B~:~
~
~
§
VDO
51
GND
'"
~
~ P'"
V;=Vss-14.5V
VOUT
'"
~
f-To·+125°~
1l
VSS = +5V
::;.:
V~ '" Vss -t4.5V
"
15
V V V
V
V V V
/ V
V
Vss " S.OV
Voo'" Vss - S.OV
10
rd6
O.4V
.,
l?:: ~
~
~ P"
~oo· V~- 5.0VVGo=Vss-12.0V_
V.· Vss - 12.0V _
TA
;;;
125°&
1.2
-5.0
-5.5
14.0
12
-4.0
VOUT
Vss - VaG
Voo (VI
typical applications
Memory Expansion
14
't
,t----I
r----- ------
INPUT
~
41
'1'
tot'
r--- ---- ----- --I
14
I
I
I
1••UT1Ao--+_ _- - .
INPUllA
INDEPENDENT
INPUT SElECT A
I
I
I
I
I
OUTPUT A
4
INPUT 2A
0--!------1'-.)
•
INPUT 18 o - - t - - - ,
OUTPUT B
IZ
INPUT 28o--t-----IL..I
MM50"
I
I
MM50zs1
--,J--~.r--~[---1 .
L-----r--T---r----~
13
YGa
150
Yeo
a
5
Vss
INDEPENDENT
INPUT SELECT B
VeG
Voo
Vss
INPUT
INPUlZB
TTL/MOS Interfaca
+5V
I
5
5%
r----- -- - -
Vg
---------,
I
I
I
I
I
I
r- -,
I
I
9
I
INPUT
•
I
I
I
L-----86r -10
VeG -12V
1·34
I
I
J
--r--r---26
76
Voo
411
~2
truth tables
Positive Logic
Logic "1" '" V 1H
::
Logical High Level
Logic "0":= V 1L
:=
Logical Low Level
Input Select A
Function
Select Input 2A
Select Input 1A
1
0
Input Select B
Write/Recirculate
Function
Select Input 28
Select Input 1 B
1
0
switching time waveforms
BIT TIMES
!
Bill
I
I
RIT2
I
8113
81T4
I
"
"
"1"
DATAl,
"1"
--fF'l DA,~~,IN I DA~~,LN nl---+--+--!---+--+-.....,~--+--+--!--I ""
"I"
+ __+-_-I
DATAOUT:""+-_-I_ _
enters the register at ¢, time, it exits at ¢, time,
(beginning on ¢l's negative going edge and ending
on the succeeding ¢2's negative going edge).
Shown is a simplified illustration of the timing of
a 4-bit multiplexed register showing input output
relationships with respect to the clock. If data
timing diagram
BITI
BIT No.2
BITN+1
8ITN
81T2
BIT I
'~O"----VO"
"j -- ~---------vo,
"
CLOCK
11
II
lJTlI' VO"
II
1>1,
.,
CLOCK
BI12
'i
"
los-I:.!..-
10%
::
t.:J,---r- 1
:
;'r::;;X
~
II
---11-- <,Ill,
I
I
I
1-- I
i
---I
I
I
I
I
90%
--
:
90", - -
I
---VOL
I
'{---------___ ~~-_-_------:4-----:-----. v~
\N'm'-'
---I
w
IHBtH
I-DATA PERIOD---I
: :
1
tpdH_:
:__
_:
:_Iodl
v'c
;,:;:;.;u:;------------------~11!----------1------.E~~vABOvEGND(VDol
OUT BIT 1
OUTBIT2
1-35
Dynamic Shift Registers
MM4104/MM5104 dynamic shift register
general description
The MM4104/MM5104 360/359,228/287,40/32
bit dynamic shift register is a monolithic MOS
integrated circuit utilizing p-channel enhancement
mode low threshold technology to achieve bipolar
compatibility. The register lengths are lengthened
or shortened by hard wiring the length select line
to VGG or Vss. The lengths available are: 40,
288, 328, 360, 400, 560, 688; or 32, 287, 319,
359, 391, 446, 678.
•
Multiple length registers Electrically adjustable
360/359, 288/287, 40/32 bit
registers
•
Wide frequency range
features
•
250 Hz min. guar.
at 25°C
2.5 MHz max. guar.
over temp.
applications
+5V, -12V power
supply. No pull-up
or pull-down
resistors required
DTLiTTL compatibility
connection diagram
•
Data store
•
CRT displays
•
Business machine
Metal Can Package
DATA OUTPUT 2
(40!J20UT)
DATA INPUT lA
{360,2811IN)
v~
TOP VIEW
Order Number MM4104H
or MM5104H
See Package 24
typical applications
TTL/MOS Interface
,,.
r
I
1"
r - - - - - - - - - 1,1
L!I!...JI
I
L __ -
_t_
M04104IMM5704
-, -
ISHORT~G~
-
Y~~NG)
-
-
--
-''T';;; -12V
I
-q-'I--- - --'
91N
,,,
Note: VGG on pin] results in a 2aB·bit register between pm 7 and pin 4 and a 287·bit register between pins 6 and 4.
The unused mput fS or 7) must be returned ttl Vss. Also, there is a J2·bit register bet>wen pins 1 and 2.
Vss on pin 3 results in a 360 bit register between pin 7 and pin 4 and a JS9·bit register between pins 6 and 4. The
unused input (6 or 7J must be returned to Vss. Also, there
1-36
IS
a 40·bit register between pins 1 and 2.
absolute maximum ratings
Voltage at Any Pin
Operating Temperature Range MM4104
MM5104
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Vss + 0.3V to Vss - 22V
_55°e to 125°e
_25° e to 70° e
_65°e to 1500 e
300 0 e
electrical characteristics
(T A within operating temperature range, Vss = +5.0V, ±5%, VGG = -12.0V ±10%, unless otherwise specified.)
PARAMETER
CONOITIONS
MIN
TYP
MAX
UNITS
Vss + 0.3
Vss -4.2
V
V
Data Input Levels
Logical HIGH Level (V 1H )
Logical LOW Level (V,c!
Vss - 2.0
Vss - 18.5
Data Input Leakage
V'N = -20.0V, TA = 25°C,
All Other Pins GND
0.01
0.5
)J.A
Data I "put Capacitance
V'N = O.OV, , = 1 MHz,
All Other Pins GND, (Note 31
3.0
5.0
pF
Length Select Input Levels
Logical HIGH Level (VLsHI
Logical LOW Level (V LSd
Vss + 0.3
Vss
Vss - 18.5
VGG
V
V
Length Select I nput Leakage
V'N = -20V, T A = 25°C,
All Other Pins GN 0
0.01
0.5
)J.A
Length Select I nput Capacitance
V'N = O.OV, , = 1 MHz,
All Other Pins GND, (Note 31
6.0
9.0
pF
Clock Input Levels
Logical HIGH Level (V"HI
Logical LOW Level (V" d
Vss + 0.3
Vss - 14.5
Vss - 1.5
V ss -18.5
Clock I nput Leakage
V,,= -20V, TA = 25°C,
All Other Pins GND
Clock I"put Capacitance
V" = O.OV. , = 1 MHz,
All Other Pins GND. (Note 3)
0.05
85
1.0
V
V
)J.A
100
pF
Vss
0.4
V
V
Data Output Leveis
Logical HIGH Level (VoHI
Logical LOW Level (Vod
= -0.5 rnA
= 1.6 rnA
2.4
ISOURCE
ISINK
Power Supply Current
TA = 25°C, VGG = -12V, pw = 150 ns
Vss = 5.0V, V"L = -12V. Data = 0·1·0·1
IGG
0.01 MHz"; ,,,; 0.1 MHz
1.5
2.5
mA
1 MHz
3.5
5.0
mA
tf)
INote 11
0.01
0.15
)J.s
1
)J.S
100
100
)J.S
)J.S
ns
t, + pw + j-J~~h
....
Static Shift Registers
*MM404/MM504 dual16 bit static register
*MM405/MM505 dual 32 bit static register
general description
The National Semiconductor line of MOS static
shift registers are monolithic integrated circuits
utilizing P-channel enhancement mode transistors_
The use of a low threshold technology permits
operation with a Voo supply voltage of -10 volts
and a V GG supply and clock amplitude voltage of
less than -16 volts_ These registers require only a
single clock input to operate from DC to 1 MHz
in either synchronous or asynchronous systems_
Each register cell is designed specifically to avoid
race conditions during latching, thus insuring
operation under all conditions specified in the
electrical characteristics_
connection diagram
Additional features include:
•
•
•
•
•
•
Bipolar compatibility
Single phase clock input
High frequency operation
1.0 MHz
Low power consumption
1.7 mW/bit typ
Output impedancl~ (V OH )
soon typ
Military and commercial temperature ranges
MM404, MM40S
-SSoC to +12SoC
MMS04, MMSOS
O°C to +70°C
Metal Can Package
V.
Note: Pin 4connel:ted to case
TOPV1EW
Order Number MM404H, MM504H,
MM405H or MM505H
See Package 23
typical applications
2N Bit Johnson Counter
TTLiMOS Interface
DIVIDE BV
2N OUTPUT
CLOCK Wi 1• REQUIREMENTS WITH Vss " +10V
lOGIC "0" = Vss -1.5V
lOGIC "t" = Vss -16V
Note: Clear register to.n "0" before
counting by applying "'" to tlear input
and clockingthrOLlgh 2N clock cycles.
Waveforms for Applications
Single 2N Bit Register
I
Vn
CLOCK",
ov~~hr-1r"""'1r
-16V
U
Lf
U
U
U
I
DATAOUTPtlT
TY'ICALOATAIN
~::= ~~\
=--~:1----~~~~~~~
I
v~
Von VaG
TYPICAL DATA OUT -UV N liT DELAY
..I,IV
\~
-b-J
\
~
"For New Designs, 50e MM4040/MM5040, MM4050A/MM5050A_
2-1
absolute maximum ratings
+O.5V
+O.5V
+O.5V
+O.5V
to -25V
to -25V
to -25V
to -25V
300mW
_55°C to +125°C
O°C to +70°C
-65°C to +150°C
Drain Voltage (V DO)
Gate Voltage (V GG)
Clock Input (V4>I)
Data Inputs
Power 0 issipation (Note 1)
Operating Temperature MM404, MM405
MM504, MM505
Storage Temperature
electrical drive requirements
PARAMETER
(Note 1)
CONDITION
Clock pulse Width
4>, Clock. q,1pw
MIN
0.4
Clock Pulse Risetime, t r ¢
Falltime, tftll'
1 MHz with
Data Setup Time,
#'
#'
2.0
#'
-O.S
Vss -1.S
Vss -16.0
Vss -18.0
V
V
Vss
Vss -14.5
Vss -2.S
Vss -7.0
0.2
tdS
electrical characteristics
PARAMETER
Clock Repetition Rate
V
V
#'
#s
0.03
tdh
#'
0.6
tPpw '" 2 IJ.s
10 kHz with tP pw = 10 J,lS
Logic "V.L "
UNITS
0.05
100"kHz with
Oats Input Voltage Levels
Logic "V'H"
Logic "V'L"
MAX
10
tPpw '" O.4J,l5
Clock Input Level
Logic "V.H "
Data Hold Time,
TYP
(Note 2)
CONDITION
Fan-Out ","
MIN
TYP
de
MAX
1.0
UNITS
MHz
Data Output Voltage Levels
Logic "VOH "
Logic "VOL"
Vss -1.5
V
V
3.0
pF
Vss -8.0
Data Input Capacitance
(Each Inputl
f= 1 MHz
Clock line Capacitance
f
VI,.,
=
=
I.S
OV
1 MHz, -20V Bias MM404, MM504
MM405. MMS05
OV Bias
Output Impedance
Outputs at Logic "0"
Input Leakage Current
Pin 1
TA == 2SOC
V IN ::: -l8V
All Other Pins at GND
Power Supply Current Drain
IVoo )
Outputs at Logic "0"
1 MHz Operation
T A ::: 2SOC
MM404. MMS04
MM40S. MMSOS
MM404. MMS04
MM405. MMSOS
9.S
18
IS
30
pF
pF
IS.0
2S
20
40
pF
pF
O.S
S.S
10.0
1.0
Hl
O.S
#A
10.0
IS.0
rnA
rnA
Note 1: For operating at elevated temperatures, the device must be derated based on a +1S0°C maximum junction
temperature and a thermal resistance of +1S(fC/W junction to ambient. The full rating applies for case temperatures
to +125°C.
Note 2: These specifications apply over the specified temperature ranges for -IIV < VOO < -9.5V, and -18V < VGG
< -14.5V and clock repetition rate of 10 kHz with output measurement load of less than 10 pF in parallel with 10 Mn to
ground unless otherwise specified.
2-2
s:
s:-!lao
performance characteristics
Power Dissipation vs VOO
o
Power Dissipation vs Temp.
Power Dissipation vs VGG
-!lao
.......
s:
s:U'1
o
-!lao
s:
s:-!lao
Voo" -10V
I--t--t---t--t- v", '" VGG
FRED" 10 kHz
-9
I
-14
-11
-10
I
o
-18
-16
-55
25
U'1
125
.......
s:
s:U'1
TEMPERATURE 'c
V DD
Max. Frequency vs Supply Voltages
VOUT vs Load Current
16
14
12
10
t--+-t--+--t--+-
~~~
1-+-+-+---1-....'1-+-+---1
4
"
r-.L
o
~N;KI
-4 -5
1.8
::I
1.6
o
f--t--+---+-+---+-::;;;ool--I
V
U'1
/~
/
1.4 f-+~F---+-+-+--+-l
/
~
V¢=O.4/J- sec @1MHz
1.2 l-y-t-Vrp=O.3j.Lsec@1.5MHz
;:!;
1.0
~
4K EXTERNA
-1 -2 -3
~
1!i
V+--+----+---+-+--t--1
I-++
21-..0'
2.0
~-
6~-+~V4-+-~-+~
8
'"
~
V
VrjJ=O.2/-1sec@2.0MHz
Voo" -10V
[ I I I
-6 -7 -8 -9
-14
-18
-16
VGG
-20
& WdVolts)
operation
A diagram of a one-bit static register employing
two clock phases (,1') is shown in the schematic_
The register requires only one external clock phase
( turns T
"ON" generating the complement of , that is
and in turn l' is used to turn T 6 and T 7 "OFF".
This action allows the register's previous information to be temporarily stored on the gate to source
capacitance C 3 of T 8' The output at node E during this timing sequence remains unchanged. However, during t2 time, clock returns to ground;
concurrently l' goes to a logic "1"level turning T,
"OFF" allowing T6 and T7 to turn "ON". The
information which was previously stored on the
gate of T 8 discharges to a logic "0" level causing
the output at node E to switch to a logic "1" level
thereby obtaining the required one-bit of delay.
I.
Likewise the information at node C is fed back to
node A latching T 2 in the "ON" state.
When a logic "0" level is presented at the register
input, the sequence is once again repeated. The bit
delay demonstrated in this example is repeated for
each half of the dual static register.
timing diagram
I~
tll11t2
I
I
I I
~ i~~:~ I~!r'-f 90%~i~f:::::"-"'10%1~
!'-r
IP
I 90%
:I I
I
I
I
I I
I I
I
---" - ' . .
I
I
n.i~h !'-----{in~In!'--
"i
-J
I I
INPUT DATA
NODEA--+-----\'
I
I
I
:r+-----i.
I
I"+---;' ~
--r"1 t--'"
II
IT-
I I
I :
I I
I I
I I
I I
NODE 8
I
:
I 1rf----'1 :
:i"ti :T-
I
I I
I
I I
NOOEC~
NOOEO~
II
II
NODE E
----toNE BIT DELAy!------
I
NOOEG . . . . n·1DElAY ...
DATA DU1l'UT . . . . N81TOElAY
I
I
I
I
I
I I
I I
I I
I I
I I
I
~
.~
I
I I
2-3
Static Shift Registers
MM4040/MM5040 dual 16-bit static shift register
general description
The MM4040/MM5040 dual 16-bit static shift
register is a monolithic integrated circu it utilizing
P channel enhancement mode low threshold technology to achieve direct bipolar compatibility on
the inputs and outputs. The device requires only
a single phase clock.
•
• Static data buffer
• Serial memory storage
+5, -12V operation
No pull-up or pulldown resistors needed
• Printer memory
• Telemetry systems and data sampling
connection diagram
Metal Can Packaga
v""
v"
TOPYIEW
Order Number MM4040H or MM5040H
Saa Package 23
typical application
·,v
2-4
2.2 MHz guaranteed
applications
features
• Bipolar compatibility
High frequency operation
• Single phase clock
absolute maximum ratings
Voltage at Any Pin
Operating Temperature Range MM4040
MMS040
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Vss + 0.3V to Vss - 22
-SSoC to +12SoC
O°C to +70°C
-6SoC to +150°C
300°C
electrical characteristics
TA within operating temperature range, Vss = +5.0V ±5%, Vss - Voo = 9V to 18.SV, VGG = -12V ±10%, unless otherwise specified
PARAMETER
CONDITIONS
Data I nput Levels
Logical High Level (V ,H )
Logical Low Level (V,e!
TYP
V ,N = -20V, TA = 25°C.
All Other Pins GN 0
Data Input Capacitance
V ,N = O.OV, f = 1 MHz,
All Other Pins GNO (Note 1)
Clock Input Levels
Logical High Level (V t, = t, + ~ + PW ~ 10.5 ns
2.2
MHz
10.0
!J.s
1.0
!J.S
Data Input Setup Time (",)
120
60
ns
Data Input Hold Time ("h)
20
0
ns
Data Output Propagation Delay from
Delay to High Level (tpdH)
Delay to Low Level (tpde!
See test circuit
200
200
300
300
ns
ns
Note 1: Capacitance values are guaranteed by statistical lot sample testing.
2-5
guaranteed performance characteristics
Data Input Levels vs
Supply Voltage
2.0 MHz Operating Curve
1.0 MHz Operating Curve
500
1000 r-,-.,..-,--r--,r-,-.,..---,
9t, =41t, =20 "S
3.0
t;)f=
]: BOO
~
!:l
~
1=
i
Z.O
600
~
~ 1.0
"'"
13
14
15
16
11
18
13
19
Vss - V¢L = Vss - Voo '" Vss - VGG (VI
14 15
Vss" +5.0V
.,...
300
~~ 400 I
1.0
..
2.0
1.0
12
13
14
15
16
17
18
19
20
Vss - VaG'" Vss - Voo (V)
14
16
15
17
18
19
Vss - Vq,L '" Vss - VGG (V)
switching time waveforms
18
20
WllllL - II ~ (/
a~ 3.0
'.0
3.0
'"
16
11111111 IsVcl [ 1
.§ 4.0
...
..~
'.0
L::: -12.0V
IV"'· 3.SV
10
100
1000
10,000
OPERATING FREQUENCY (kHz)
ac test circuit
OATA
'''"',~
~lOCK
!
L
Vo;s-4.2V\
1_'--._'''___
~_:___I_,_,,'',~
________- J
Vss-l.5V
I
VSS-145V:
om
OUTPUT
I
I I
-I"'r'~-j"·I-I
\'"
!
F
-"j '----------,-L---',,,"~
2-9
Static Shift Registers
MM4052/MM5052 dual 80 bit static shift register
MM4053/MM5053 dual 100-bit static shift register
general description
The MM4052/MM5052 dual aO-bit and MM4053/
MM5053 dual 100-bit static shift registers are
monolithic integrated circuits utilizing P channel
enhancement mode low threshold technology to
achieve direct bipolar compatibility on the inputs
and outputs. The devices require only a single
phase clock.
• High frequency operation
• Improved drive capability
• Static data buffer
• Serial memory storage
+5, -12V operation
No pull-up or pulldown resistors needed
• Printer memory
• Telemetry systems and data sampling
connection diagram
Metal Can Package
NC
TOP VIEW
Order Number MM4052H, MM5052H,
MM4053H or MM5053H
See Package 24
typical application
'5V
Vre
r- - ,
I
I
1
I •
I
I
L_~_.J
-12V
ANY DTLITTl DEVICE
2-10
push-pull outputs
applications
features
• Bipolar compatibility
1.6 MHz guarantee
• Single phase clock
ANY DTLITTL DEVICE
absolute maximum ratings
Voltage @ Any Pin
Operating Temperature Range
MM4052/MM4053
Vss +O.3V to Vss -22V
_55°C to +85°C (Ambient)
_55°C to +125°C (Case)
O°C to + 70°C (Ambient)
-65°C to +150°C
MM5052/MM5053
Storage Temperature Range
300°C
Lead Temperature (Soldering, 10 sec)
electrical characteristics
TA within operating temperature range, Vss ~ +5.0V ±5% and VGG ~ -12V ±10%, unless otherwise specified.
Data Input Levels
Logical High Level (V ,H )
Logical Low Level (V I L)
V ,N ~ -20V. TA ~ 2SoC
All other pins GND
Data Input Capacitance
V ,N ~ O.OV, f ~ 1.0 MHz
All other pins GND
Clock I nput Levels
Logical High Level (V ¢H)
Logical Low Level (V ¢ L )
V ,N ~ -20V, TA ~ 2SoC
All other pins GND
Clock I nput Capacitance
V ,N ~ O.OV, f ~ 1.0 MHz
All other pins GND
Power Supply Current
.01
3.0
Vss-1.S
Vss-18.S
Clock I nput Leakage
(V OH)
(V 0 L )
(V OH)
(VOL)
TYP
Vss - 2.0
Vss - 18.S
Data I nput Leakage
Data Output Levels
Logical High Level
Logical Low Level
Logical High Level
Logical Low Level
MIN
CONDITIONS
PARAMETER
ISOUACE ~ -SOO IlA
ISINK ~ 1.6 rnA
ISOUACE ~ -10 IlA
ISINK ~ 10llA
MAX
UNITS
Vss - 4.2
V
V
O.S
IlA
S.O
pF
Vss
Vss - 14.!
V
V
1.0
Il A
22
28
pF
2.4V
4.8
-3.0
Vss
0.4
Vss-1.0
Vss
Vss - 12.0
Vss
Vss - 7.0
V
V
V
V
9.S
12.S
mA
12.0
16.0
mA
200
200
300
300
ns
ns
TA ~ 2SoC
~ 1.6 MHz
VGG ~ Vss - 17V
V¢L ~ Vss - 17V
cP,
(IGG) MM40S2/MMSOS2
(IGG) MM40S3/MMSOS3
Propagation Delays from Clock
Propagation Delay to a High (tpdH )
Propagation Delay to a Low (t pdL )
Clock Frequency
(CP,)
Clock Pulse Width (CPpw)
See waveform
See waveform
See operating curves
0
1.6
MHz
See operating curves
CPt, + CPpw + cpt, ~ 10.Slls
0.2S
10
Il s
S
S
IlS
Ils
Clock Transition Times
Risetime (CPt,)
Falltirne (CPt,)
CPt, + CPpw + cpt, ~ 10.SIlS
cpt, + CPpw + cpt, ~ 10.SIlS
Data Input Setup Time (t d,)
80
SO
ns
Data I nput Hold Time (t dh )
20
0
ns
2-11
guaranteed performance characteristics
Maximum Data Input Low
1.0 MHz Operating Curve
500
!
..
400
k-
...
%
i
o
~
300
......
......
0
~
~
><
u
400
><
u
"u
r-r--t-rT"-r-""'*""
200
18
16
14
Level vs Supply Voltage
1.6 MHz Operating Curve
"u
200
~~=1 ~60~HZ
J
I
I
;
MIN .....
~
-
12
14
Vss - VGG (V)
16
,.
~
[T.RANGE'-55'Cto+85'C· V1L "'D,BV
V1H '" 3.0V
tilt.:: ¢it, =20 n5
100
20
~AxL
~
...~
I-I-t--
18
20
Vss - VGG (V)
"...g
'"''i<""
"'"
2.2
2.0
1.8
1.6
1.4
1.2
1.0
.8
12
14
16
18
20
Vss - VOG (V)
typical performance characteristics
Data Output Sink Current
Data Output Source Current
vs Data Output Voltage
1
vs Data Output Voltage
5.r-~~~-'--'--;r-,
vGG '" -12V
~V"-4'_5._0V-+-_-+-_I--4-;;;o""
4.0
§
c-
o!
Power Supply Current
...--...--,--.,....-r--r--o
10.0
1;;;;::T"""'oj;;:~~iy::-::;;oo;;i
8.0
S
3.0 ~-4--+---+--7F-::>"'I-:"'"
~
:;:
...
2.0
~-4--+-F.,y:.-7'~"""'-,--i
!l
4.0 f--t-+-+-t-~"",,-"'f
1.0
f---l~"""-+-t--t--i
~"
2.0
i
5.0
4.0
3.0
2.0
1.0
0.0
><
...
;::
;;
Vss '" S.OV
tPPW = 250 m
TA
.08
~
"
&.0
o!
f--t--j--+--II--t--i
VGG:: -12V
Vss:: 5.0V
5.0
-1.0
4.0
3.0
VOUT (V)
2.0
VOUT
1.0
0.0
-1.0
II
"'"
ill
>
"
= +25°C
tPf '" 1.0MHz
DATA ·1-0-1-0
'"
a
~
.10
.06
./
.....
.04
o
12
14
11111111
'"
~
"
.08
I
- tl~I~~'cl
.06 -
/
TA -+25°C
o!
0
0
w
.04
'"
'"ill
>
11111111 I
_ TA=~85°C 1-
1-1111111/ LVGG - -12V
.02
1IIIilil I I ~rT~ ~'~~-l-O
"
11111111
o
10
100
11 ...... 250 ",
10,000
1000
OPERATING FREQUENCY (kHz)
switching time waveforms
DATA INPUT
2·12
16
Vss - VGG {VI
(VI
Power Supply Current
;;
'"
.02
.10
;::
V
V
ac test circuit
18
20
Static Shift Registers
MM5054 dual 64/72/80-bit static shift register
general description
The MM5054 dual SO-bit static shift register is a
monolithic MOS integrated circuit utilizing silicon
gate low threshold technology to achieve complete
bipolar compatibility. The device has input and
output taps that also provide register lengths of
64 or 72 bits.
The single phase bipolar compatible clock lines
may be driven by any conventional DTL or TTL
circuit. The registers may be operated as a dual
register by connecting the clock lines A and B
together, or as two independent registers. Two
clock control lines provide independent logical
control of the shift register clock lines.
Standard supplies
•
High freq. operation
• Single phase clock
+5.0V, -12V
DC to 3.0 MHz typ
DTLlTTL compatible
on·chip clock driver
•
Low clock line capacitance
•
System flexibility
•
Low power dissipation
S.O pF max
Split clock or common
clock operation. Logical
control of clock lines
<600 /lW/bit typ
applications
features
•
•
Complete bipolar compatibility
DTLlTTL
input/output and
clock line compatibility
without additional
components
• Teletype data buffers
• Printer memory - SO, 12S, 136, 144 bit lengths
• Telemetry and data sampling systems
• Serial memory storage
logic diagram
DATA
DATA
OUTPUT
INPUT
1,15
3,13
DATA
INPUT
1,140-------'
ClOCK
4,12
...r-,
1,9"-_ _
CLOCK
CONTROL
6,10
The unused data inputs and clock controls should be connected to Vss to ensure proper operation.
logic diagram shows 1/2 of the unit.
connection diagram
truth table
Dual-In-Line Package
INPUT-A-12/BO 1
16 VDD
INPUT-A-64172 2
15INPUT-8-72/BO
OUTPUT-A-12IBO 3
14 INPUT-B-64172
DUTPUT-A-64112 4
13 OUTPUT-B-12fBD
NC5
120UTPUT-8-64/12
CLOCK CONTROL A 6
CLOCK A 1
Positive Logic
CLOCK
CONTROL
CLOCK
Low
Inhibited
High
Active
10 ClOCKCDNTROL B
9
CLOCKS
rop VIEW
Order Number MM5054D
See Package 3
Order Number MM5054N
See Package 15
2-13
absolute maximum ratings
Voltage at Any Pin
Operating Ambient Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
Power Dissipation
Vss + 0.3V to Vss - 20V
O°C to +70°C
_65°C to +150°C
300°C
600 mW@ 25°C
dc electrical characteristics
TA within operating range, VGG =-12V ±10%, Voo = GND, Vss = 5.0V ±5%, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Data, Clock Control, and Clock Levels
Vss +0.3
Logical High Level (V 1H )
Logical Low Level (V I L)
Vss - 4.2
Input Leakages
VIN = -10V, TA
=
V
V
0.5
MA
4.5
6.0
pF
6.0
8.0
pF
Vss
0.15
0.4
V
V
7.0
5.0
10
8.0
mA
mA
25"C
Atl Other Pins GND
Data Input Capacitance
VIN =OV,f= 1.0 MHz
All Other Pins GND (Note 1)
av,
Clock and Clock Control
Capacitance
VIN
Data Output Levels
Logical High Level (V OH )
(Figure 1)
=
f = 1.0 MHz
(Note 1)
ISOURCE =
Logical Low Level (VOL)
ISINK =
2.4
-0.5 mA
1.6 rnA
Power Supply Current
¢, ~ 1.5 MHz, TA = 25°C
(lGG + IOD = Iss)
Vss = 5.0V, Vao = GND
VGG = -12V
IGG
100
ac electrical characteristics
TA within operating range, VGG = -12V ±10%, V OD = GND, Vss = 5.0V ±5%, unless otherwise noted.
PARAMETER
CONDITIONS
Clock Frequency (CPf)
9t" ¢lt f
:;
MIN
10 ns (Note 2)
MAX
UNITS
DC
3.0
TYP
1.5
MHz
0.180
10
Clock Pulsewidth (¢pw)
¢pw
¢t r = 1't1 ~ 10 ns
0.25
¢pw
¢tr=:¢tf~10ns
0.38
MS
MS
Clock Transition Times
Clock Risetime (4't.)
500
500
Clock Fatltime (tf = 10 ns
0
ns
)
=:
1>tf
=:
Data Input Setup Time (t ds )
(Figure 1)
I/>t,
=
1>t f
= 10 ns
60
30
ns
Data Input Hold Time (tdh )
(Figure 1)
(Ptr
=:
¢tf = 10 ns
40
20
ns
Data Output Propagation Delay
(Figures 1 and 2)
From Clock
Delay to Output High Level (tpdH
¢tr=¢tf = 10ns
)
Delay to Output Low Level (tpdd
Note 1: Capacitance is guaranteed by periodic testing.
Note 2: For static operation clock must remain at Vil.
2·14
ns
ns
200
200
300
300
ns
ns
s:
s:C1I
typical performance characteristics
5.0
:<
oS
4.0
~
~w
J.O
...
1\.1\.
I\.
I.....
DoC
I\.
+10°C
I....... ~
"
1.0
o
o
~
J.O
::::
in
~
I+I~" DoC
5.0
4.0
5.0
V- 1/
~
6.0
T,. =+25°C
I-
T,.= +70°C
~
~
1111
1.0
1111 III
IIII III
100k
0.6
O.B
::t
.§
0
0
5.0
-i~~~~:
+70°C
I-
111111
_I ~ III
4.0
!
3.0
Vss= +5.0V
Voo = GND
YGG = -12.0V
1.0M
Il"lml
O·C
6.0
DATA'" 1-0-1-0
Vss =+5.0V
VDD '" GNU
VGG " -12V
2.0
1.0
o
10M
10k
lOOk
Typical 1.0 MHz
Operating Curve
-
~
MAX¢f'W~
JOO
O"C
< T A < +70·'C
VIL = O,BV
VIH '" 3,OV
'Pt,=¢'tf=10ns
100
15.5
12
~~ =--
"
~'"
u
"
U
BOD
700
600
500
i'<;,
13
~'Vss=+5,OV
Vee" GNO
300
V1L
"
1B.5
Vss - VGG (V)
-
O.BV
--+4- 1
ZOO
~
~
t-
I I
I 11
13
14
15
,.w
...=>
"
Z.O
17
18
19
r- ~ t==::
~
I
=
~
~O°C-
DoC
~
1.0
'"inz
/
3.0
./
Z.O
L
16
17
18
,/'
~CAI
,/'
--- ~70jc_
/'
V
:<
1 __
Voo" GNU
YSS =+5.0V
VOUT"
O.4V
1.0
12
13
14
15
16
17
1B
19
Vss - VGG (V)
Vss - VGG (V)
switching time waveforms
16
1
MIN
:i:
B.O
YaG ::; -12V
I
-12V
Voo '" GND
Vss '" +5.0V
\IGG '"
9.0
r.... ~
Z.O
u
Voo'" GND
Vss=+5.0
+~5°C
~
Current vs Data Output Voltage
10
I
I
Typical Power Supply
Current vs VGG
Typical Data Output Sink
Typic.1 Data Output Sourc.
Current vs Data Output Voltage
ac test circuit
DATA
INPUT
I
T
I"
,',''',',s:o14
.'". . - ......-j.ot-~+H"""+lh
....."'I .."I .."I J,.
10PF
CLOCK
CONTROL
FIGURE 2
OU~~~~---------
Note; All times measured with respect to 50% points.
FIGURE 1
2-15
Static Shift Registers
MM4055/MM5055 quad 128-bit static shift register
MM4056/MM5056 dual 256-bit static shift register
MM40571MM5057 512-bit static shift register
general description
The MM40S5/MM50SS, MM40S6/MMSOS6,
MM40S7/MMS057 512-bit static shift registers are
MOS monolithic integrated circuits using silicon
gate technology to achieve bipolar compatibility.
They have a guaranteed operating frequency of
1.0 and 1.5 MHz respectively, and an on chip clock
generator allows TTL level clock driver for com·
plete TTL compatibility.
Low clock capacitance
10 pF (typ)
Operates from +5.0V, GND, and -12V
•
Three configurations
MM4055/MMSOS5
MM40S6/MMS056
MM40S7/MMSOS7
•
features
•
•
•
Quad 128 bit
Dual 256 bit
Single S12 bit
I nternal recirculate
applications
Guaranteed operation
1.5 MHz
1.0MHz
O°C to +70°C
-SSoC to +12SoC
• Single TTL compatible clock, on chip clock
generator
•
CRT displays
•
•
Terminals
Disk and drum replacements
•
Buffer memory
connection diagrams
Dual-In-Line Package
RECIRCULATE 1
Dual-In-Line Package
'"
"
15 111C
RECIRCULATE
'"
INPUTB
12
"
iNPUT 0
'"
'
'co
OUTPUTB
'
,~
.
..
Metal Can Package
Dual-In-Line Package
",',"'U""O"".
INPUT
OUTPUT
Vss
2
1
Nt
5
¢t"
,
VGG
4
TOP VIEW
TOPVIEW
Order Number MM4055D
orMM5055D
Order Number MM5056N
See Package 13
See Package 3
Order Number MM5055N
See Package 15
Order Number MM4057D
orMM5057D
See Package 1
Order Number MM5057N
See Package 12
logic diagram
.."..... :~
CONTROL
N·BITS
DATA
INPUT
2-16
~~i:UT
Order Number MM4056H
orMM5056H
See Package 24
absolute maximum ratings
(Note 1)
Data and Clock Input Voltages and
Supply Voltages with Respect to Vss
Power Dissipation
Operating Temperature Range
MM5055, MM5056, MM5057
MM4055, MM4056, MM4057
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
+0.3V to -20V
600 mW @ T A = 25°C
O°C to 70°C
_55° C to 125° C Case
-65°C to 160°C
300°C
electrical characteristics
TA
(MM4055, MM4056, MM4057)
= -55°C to +125°C, Vss = 5.0V ±5%,
VGG
PARAMETER
= -12V
±5%, V DD
= OV, unless otherwise
CONDITIONS
MIN
TYP
noted.
MAX
UNITS
Vss + 0.3
Vss - 4.2
V
V
Data, Recirculate and Clock Input Le\lels
Vss -l.0
Logical High Level (V 1H )
Logical Low Level (V1Ll
Vss - 15
Data, Recirculate and Clock Input
Leakage
VIN =: -lOV, T A == 25°C
All Other Pins GND
0.01
0.5
~A
Data I nput Capacitance
VIN =OV,f=l MHz
4.5
6.0
pF
3.0
6.0
pF
10
14
pF
All Other Pins GND (Note 2)
Recirculate Input Capacitance
VIN =OV,f=l MHz
All Other Pins GND (Note 2J
Clock Capacitance
VIN =: OV, f = 1 MHz
All Other Pins GND (Note 2)
Data Output Levels
Logical High Level (V OH )
'SOURCE'"
Logical Low Level (V o d
, SINK ::
Power Supply Current
-0.5 rnA
1.6 rnA
2.4
Vss
Voo
0.4
V
V
T A:: 25°C, VGG = -12V, Vss :: 5.DV
V OD =OV,ippw = 230 ns
Oata"'0·1·0-'·· .
IGG
1>f SO.1 MHz
¢,:5 1.6 MHz
6.5
10.5
9.0
15.5
rnA
rnA
' DO (Note 4)
¢,:50.1MHz
1>f S 1.6 MHz
13
15
18
20
rnA
rnA
2.2
1.0
MHz
0.280
0.160
10
~s
de
~s
Clock Frequency (¢if)
¢tr, 1>tf
S 10 ns (Note 5)
¢tr, 1>tf
S
S
Clock Pulse Width
i¢pwl
I¢pw)
¢t" 1>tf
10 ns (See ac Test Circuit)
-400
10 ns (See ae Test Circuit)
-400
Data Input Setup Time (tds )
260
ns
Data Input Hold Time (tdH 1
120
ns
260
ns
120
ns
Recirculate Setup Time (t ds )
Recirculate Hold Time (tdH)
Data Output Propagation Delay
Delay to High Level (tpdH)
Delay to Low Level (tpdd
S
10ns
For Load Conditions See ac Test Circuit
t"tf
350
350
700
700
ns
ns
2-17
electrical characteristics (con't)
(MM5055, MM5056, MM5057)
TA = O°C to +70°C, Vss =5.0V±5%, VGG =-12V±5%, V DD =OV,unlessotherwisenoted.
PARAMETER
CONDITIONS
Data, Recirculate and Clock Input Levels
Logical High Level (V'H)
MIN
TYP
Vss -1.5
Vss -15
Logical Low Level (V'L)
MAX
UNITS
Vss + 0.3
Vss - 4.2
v
v
Data, Recirculate and Clock Input
Leakage
Y'N =-10V, TA = 25°C
All Other Pins GND
0.01
0.5
Data Input Capacitance
Y'N =OV,f= 1 MHz,
4.5
6.0
pF
All Other Pins GND (Note 2)
Recirculate Input Capacitance
Y'N = OV, f = 1 MHz,
All Other Pins GND (Note 2)
3.0
6.0
pF
Clock Capacitance
V IN =OV,f= 1 MHz,
All Other Pins GNO (Note 2)
10
14
pF
Data Output Levels
Logical High level IV 0 H)
Logical Low Level (VoLl
Power Supply Current
100 (Note 4)
Clock Frequency (¢f)
'SOURCE =
'SINK
-0.5 mA
= 1.6 mA
Vss
v
0.4
V
=-12V, Vss=5.0V
V OD =OV,f/>pw =230m
Data=O-1-0-1·· •
TA =
25°C,
2.4
Voo
VGG
¢,$O.l MHz
¢, $2.2 MHz
6.5
13
9.0
19
mA
mA
¢,$O.lMHz
¢, $2.2 MHz
13
15
18
20
mA
mA
3.0
1.5
MHz
0.100
0.100
100
de
¢tr. f/>tf S 10 ns (Note 5)
Clock Pulse Width
~)
I¢pw)
¢tn ¢tf S 1() ns
¢tr. ¢tf S 10 ns
0.230
0.300
Data Input Setup Time (tdS )
110
Data Input Hold Time (tdH )
40
Recirculate Setup Time (tds)
Recirculate Hold Time (tdH)
Data Output Propagation Delay
Delay to High Level (tpdH )
Delay to Low Level (tpdd
t r , tf~ 10ns
For Load Conditions See Test Circuit
110
40
ns
250
250
345
345
ns
ns
Note 1: "Absolute MaXimum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The
table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Positive true logic notation is used:
Logic "1" = most positive voltage level
Logic "0" = most negative voltage level
Note 4: Outputs not loaded when measuring IDO. Add 1.6 rnA to '00 for each TTL load to compute worst case power.
Note 5: For static operation clock must remain at VIL.
2·18
typical performance characteristics
Typical I DO vs Clock
Typical IGG vs Clock
Frequency
Frequency
20
111111
18
16
14
~
.s
12
Ji
10
Typical Powe, Supply
Current vs V GG
21
I.ll
li'~<-~~
t-
18
~
1P.:;;~"t.
p..I--'
f.....
15
8.0
!
12
j
9.0
DATA < 1·0·1-0
6.0
6.0
Yss = 5.0V
4.0
Voo = OV
2.0
3.0
I~IGG::: -12V
lOOk
10k
Veo::: GNU
Vss'" +5.0V
DATA < 1·0·1·0 . /
1::- f..-
:::
lOOk
10k
1M
13
10M
;
i
V,,<+5.0V
{ .. < 1.0 MHz
Yoo = GNU
,pt. = ¢'It ::: 10 ns
TA =1+125"IC CLOCK
VII_ =O.BV
VIH =3.5V
900
~
:;
'"
2.0
15
~
~
~
1.0
14
700
600
15
17
16
18
500
400
1
i"~
II-
,
300
19
13
rJlt r =ljJ t f=10ns
I
I
I
I
14
15
3.0
~
~
ill
a:
i
2.0
......
B
1l
Yeo = GNU
Vss= +5.0V
VOUT= O.4V
15
16
IVss - VGGI IVI
300
17
16
=
17
D.BV
I I I
18
0j lM
IbllWMIN
2.0MHz
I,"'t,'" 10ns
Vss= +5.0V
Voo =OV
15
18
I--
--l.....
¢t'"
100
rr
MM5055f56/51 TA = DOC to +1rC
200
MIN.pPW
I
I
17
16
18
17
18
Typical Data Output Source
Current YS Data Output
Voltage
f~
,,(.,
II"
I.,."t"A.,."t"
4.0
.s
.s....
14
'"
~
I I I
~:v
13
I..
V'L
V,", < 3j5V
Typical Output Sink
Current vs Data Output
Voltage
5.0
12
16
IV" - VGGI IVI
Typical Data Output Sink
Current VS V GG
1.0
!
'"
:;
V1L ::: D.BV
VIH =3.5V
I'N..
200
IV" - VGGI IVI
....
'~A~l
io-'~ "~5'C"
...
~
'>
~~
j0
30
~~
tflt =-1.5MHz
!f/pw =333 PS
'"
;0:'"
-
w~~
...
",2
~~
~'"
>"
~
'>
Voo "'OV
OUTPUT LOAO = 1 TTL INPUT _
DATA = 1010 •..
tt-
10
r-tt'GIG 1
0
vs Supply Voltage
vs Temperature
~LI~Ti~~~~AO -1 TTL INf'UT
40
00 E
Vss=+5.0V.Voo=-12V'- t- t20
Guaranteed Power Consumption
50
1 1
\/00. 011
TA -2S"Ci""""
00
~~
j~
10
-
14
15
900
iO
BOO
~
700
w
!
~
600
500
.. =1.5MHz
]: 1000
1
I I
I-t- t-ljAi l
'":;
I
r-
iO
~.
r-
~
I I
~ 300
0:
> 200
1 1
...,
100
1
IMIN)
17
~
~
~
t-~
18
19
BOO
Vss '" 5.0V
VDD :: ov
TA '" 25°C
600
Vss" 5.25
600
Voo
500
""-
400
300
200
100
10 20 30 40 50 60 70 BO 90 100
1 1
10 20 30 40 50 60 70 BO 90 100
~
L1
1:;
200
J.l
~
ffi
4.0
t-b-
.
~
..'",
~
...., = 50%
VOD :: -12V
Vss" 5.0V
Voo = OV
OUTPUT LOAO = 1 TTL GATE
2.0
;(
IMIN)
1.0
"
0
-11.6
-11.8
-12
VOG
TA - AMBIENT TEMPERATURE I"C)
~b
3.0
:::
1 1
~
~,
1
vs Ambient Temperature
5.0
OUTPUT LOAD = 1 TTL GATE j - t -
~
....
Typical Maximum Frequency
g
~tj'
-12.2
=OV
VGG" -12.6V
TA - AMBIENT TEMPERATURE I"CI
1 1 1
400
tk=1.5MHz
¢?w::: 333 ns
DATA IN;; 1010 ...
0
I 1
tflt "'1.5MHz
OUTPUT LOAO = 1 TTL INPUT
700
Typical Clock Pulse Width
vsVGG
VDD=OV
Vss = 5.0V
1 1
1
VGG " -12V
OUTPUT LOAO = 1 TTL INPUT,_
400
0
1 1
'i"
"'"
-
t--
VSS - VGG IV)
Typical Clock Pulse Width
vs Ambient Temperature
1000
'"
1
16
ill
o;
r- c-
I
0
10 20 30 40 50 60 70 BO 90 100
~
:
1
SPECIFIED
OPERATING RANGE
20
~ 900
BOO
Z
E
TA - AMBIENT TEMPERATURE I"CI
!
:;'"
1000
I
,_'333
..
~
DATA'N .1010.
ss
30
...
1
o
Typical Power Supply Current
0
-12.4
t-r-
10 20 30 40 50 60 70 80 90 100
TA I"C)
(V)
switching time waveforms
,
0;;:
~l$Ipw- _ _ _
v,"
".
1/
v,"
\
DATA INPUT
\
v"
v,"
r---"'\
STREAM SELECT
v"
v""
-Ios-
\
\
V
1\
v"
.
J
1\
,
f--tos- -..tDH __
_tDH __
II
II
-""-
I~
\
I
I
r---"'-r-- tsw-
V
I
~~l
DATA OUTPUT
\
\
-~\
Voc
NOTE 1: TIMES MEASURED AT 50% POINTS WITH t., 1t ::: 10 ns.
NOTE 2: FOR DC STORAGE CLOCK MUST REMAIN AT VIPL'
2-23
~MfN
2.0MHz
t," t," 10 os
Vss" +5.DV
(if"
100
MIN'*;=r
0
V,',H ~ 3.0V
V.. ,L" O.SV
+lIrc
I
200
u
0
I I I I
100
V 1L " n.BV
V 1H " 3.0V
TA "DoC to
0
(,'.It,=9t,=1005
I'i--i
I
lOOk
""t (Hz)
'"
V1H = 3.5V
400
200
14
400
O'C
T ~<"" II I '1
Tlo,1 Inn
fE',!
c'J'-l
'=======r-1
T91t1(rJ
L __
3·16
Space
switching time waveforms
V," ___",""
ADDRESS
V,, _ _ _......I
v,"
POWEn SAVER
V,,----+--'"____________-+____
DATA out
FIGURE 1. Acce.. Time From Addre.. to Date Out
v,"
POWER SAVER
V"
v,"
CHIP SELECT
V"
Vo "
DATA OUTPUT
It :t
DATA OUT
VALID
vo•
FIGURE 2. Access Time From Power Saver or Chip Select to Output
programming waveforms
Vco
POWER
SAVER
ADDRESS
AND DATA
V"p~==='"
PROGRAM
FIGURE 3. Programming Waveforms
3-17
PROMs/ROMs
MM4210/MM5210 1024-bit read only memory
general description
no clocks required
output wire AND
capability
• Chip enable output control.
The MM4210/MM5210 is a 1024-bit static read
only memory. It is a P-channel enhancement mode
monolithic MOS integrated circuit utilizing low
threshold technology. The device is a non-volatile
memory organized as 256-4 bit words. Programming of the memory contents is accomplished by
changing one mask during device fabrication. Customer programs maybe supplied in a tape, card, or
pattern selection format.
• Static operation
• Common data busing
applications
•
•
•
•
•
features
• Bipolar compatibility
• High speed operation
500 ns typ
Code conversion
Random logic synthesis
Table look-up
Character generators
Microprogramming.
block and connection diagrams
Dual-In-Line Package
INPUT A3
16
voo
INPUT A2
15
INPUT A4
SENSE
INPUTS
OUTPUTS t
AMPLIFIERS
(LSBI A,
LSI INPUT A,
14
INPUT As
LSB OUTPUT 8,
13
INPUT As
INPUT A, Msa
S,ILSB)
A,
"
A,
A,
OUTPUT B2
•
12
OUTPUT 113
6
11
vG ,
10
CHIP
"
Msa OUTPUT 84
"
v"
,
,
ENABLE
INPUT As
9
TOP VIEW
CHIP ~
*The output is Enabled by applying
ENABLE
a logic"1"totlM Chip Enable line.
trhe outputs Bre connettad to
Order Number MM4210J or MM5210J
See Package 10
Order Number MM5210N
See Package 15
V eD through an internal MOS
resistor when Disabled.
typical application
256 x 4 Bit ROM Showing TTL Interf...
-12V _ _ _ _...._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...._
--<,..-.....
....
....- .....----------__,
+lZV _ _ _ _+--<~
.'v-....--+-~_t-~----------~r__t-+-~_t--_1~.,y
A• •
UK
3.0K
3.0K
CHIP
)O'-I_+_....._.....:E~.A:::':;:LE"l1O
'1":'"----I-+--t-~H
.....-;:-_ _ _ _v.;,;'""o 11
61"'"----1--+-...- - 1
UK
3.8K"
»r-_~
&.8K
_____~A'~12
F'~'----I:-~---~
MM421OJMM5210
8.8K
"
13
DTLml1061C
14
voo
*Resistorvalue can varvfrom 150H
to 30 kH depending on spaed requirements.
Note: For programming information see AN·100.
3-18
"
":"
}."'"
absolute maximum ratings
V G G Supply Voltage
V D D Supply Voltage
I nput Voltage
(V ss -20)V
Storage Temperature
Operating Temperature MM4210
MM5210
Lead Temperature (Soldering, 10 sec)
<
Vss-30V
V ss -15V
Y,N
(Vss +0.3)
_65°C to +150 o e
_55°C to +125°e
oOe to +70 o e
300°C
<
electrical characteristics
TA within operating temperature range, Vss ~ +12V ±5% and VGG ~ -12V ±5%, unless otherwise specified.
PARAMETER
Output Voltage Levels
MOSto MOS
Logical "1"
Logical "0"
MOSto TTL
Logical "1"
Logical "0"
CONDITION
MIN
1 Mfl to GND Load
TYP
MAX
UNITS
Vss -9.0
V
V
+0.4
V
V
Vss -8.0
V
V
Vss-1.0
6.8 kfl to V GG Plus One
Standard Series 54/74 Gate Input
+2.4
Input Voltage Levels
Logical "1"
Logical "0"
Power Supply Current
Vss -2.0
T A = 2Soc
19
Vss
VGG (Note 1)
I nput Leakage
Y'N = Vss -12V
Input Capacitance
f= 1.0MHz
Access Time (Notes 2,3)
TA = 25°C
(See Timing Diagram)
Vss = +12V VGG = -12V
T ACCESS
Output AND Connection
Note 1:
Y'N
~
25
1
Il A
1
IlA
pF
5
OV
150
500
MOS Load
TTL Load
mA
650
ns
3
8
The VGG supply may be clocked to reduce device power without affecting access time.
Note 2: Address time is measured from the change of data on any input or Chip Enable line to the output of a TTL gate.
See Timing Diagram.
Note 3: The access time in the TTL load configuration follows the equation: T ACCESS = the specified time + (N - 1) (50) ns
where N = number of AN D connections.
3-19
performance characteristics
Guaranteed Access Ti me vs
Supply Voltages
Typical Access Time vs
Supply Voltages
~
1000
800
]
1000
o25~
T,
J
800
]
~ 600
~ 600
~
400
I-
400
200
10,8
12.0
13.2.
10.8
12.0
Power Supply Current vs
Temperature
Vss = +12.0V
Tr1 25° C
GUARANTEED
..§
0
0
.A'
20
TYPICAL
~
22
18
Jl
16
14
:
"\
i'.!'UARANTEEO
I"
..§
I VGG=-12.0V
,
26
22
18
J'..
"
)-.....
t.....
TYPICAl'!'--
14
10.8
13.2
Vss & VGe (V)
Power Supply Current vs
Voltage
~
I~
25"C/
Vss & VGG (V)
24
+p+
125"C
t-'70"C I
200
12.0
13.2
-50 -25 0 25 50 75 100 125
Vss & VGG (V)
TEMPERATURE (Ce)
timing diagram/address time
+lv
I
"JL
ov
I
3.0K
'sv
INPUT AN
DM8810
OM8812
E"~IOPF
~
'5V
I
OUTPUT BM
MM4210/MM5210
I
EOUT
*"
10 PF:::!::
I
6.aK
ANY OHITTl
GATE
Jv
+12V
ov
E"
+12V
ov
"v
~
E'···- --Vss -9.0
~VW20
OA
1.5V
0
II
fOUl
.,v
ov
1.5V
time
3-20
*"
l,s
pF
PROMs/ROMs
MM42111MM52111024-bit read only memory
general description
The MM4211/MM5211 is a 1024-bit static read
only memory_ It is a P-channel enhancement mode
monolithic MOS integrated circuit utilizing low
threshold technology_The device is a non-volatile
memory organized as 256-4 bit words_ Programming of the memory contents is accomplished by
changing one mask during device fabrication_
Bipolar compatibility
•
High speed operation
•
Static operation
Common data busing
output wire AND
capability
•
Chip enable output control
applications
features
•
•
+5V. -12V operation
< 700 ns
typ
no clocks required
•
•
Code conversion
Random logic synthesis
•
•
Table look-up
Character generators
•
Microprogramming
Dual-ln~Line
block and connection diagrams
Package
" V"
"
INPUT A3
SENSE
AMPLIFIERS
INPUT A4
INPUT A2
OUTPUTS t
LSB INPUT A,
14
INPUT As
LSB OUTPUT 8,
13
tNPUT~
12
INPUT A7 MSB
B,(lSB)
B,
OUTPUT 82
DUTPUT 83
6
MSB DUTPUT 84
7
V"
B
B,
..
,
INPUT As
Order Number MM4211J
Dr MM5211J
See Package 10
Order Number MM5211 N
See Package 15
CHIP"
ENABLE
when Disabled.
"
V"
CHIP
ENABLE
TOPVIEW
'""The output is Enabled by applying a logic "1"to the Chip Enable lin e.
tThe outpuu ara connected to VDO through an internal MOS resistor
11
typical application
256 x 4 Bit ROM Showing TTL Interlace
-12V - - - -. .-----------------~.......-
. .---.
.5V-~----~----------------------------~~-+--+--i--~----~-
...
.~{
V"
6.BK
UK
6.BK
6.8K
CHIP
B.
ENABLE
"
Vue.;
B,
11
B,
A,
12
ANY DlL/TTL
I
MM4211!MM5211
LOGIC
13
B,
ANY DTlITTL
LOGIC
14
Voo
t
Note: For programming information see AN·100.
"
I"
I
1
3-21
absolute maximum ratings
VGG Supply Voltage
Voo Supply Voltage
Input Voltage
(Vss - 20)V
Storage Temperature
Operating Temperature MM4211
MM5211
Lead Temperature (Soldering, 10 sec)
<
Vss - 20Y
Vss - 20V
V 1N
(Vss +0.3)V
_65°C to +150°C
_55°C to +125°C
O°C to +70°C
300°C
<
electrical characteristics
T A within operating temperature range, Vss = +5V ±5%, V GG = Voo = -12V ±5%, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
6.8K ±5% to VGG Plus One
Standard Series 54/74 Gate
+2.4
TYP
MAX
UNITS
+0.4
V
V
Output Voltage Levels
MaS to TTL
Logical "1"
Logical "0"
Output Current Capability
Logical "0"
VouT=2.4V
I nput Voltage Levels
Logical "1"
Logical "0"
Power Supply Current
100
IGG (Note 1)
Vss - 4.2
Vss - 2.0
TA = 25°C
Vss = +5V
VGG = Voo = -12V
I nput Leakage
V 1N = Vss - 12V
Input Capacitance (Note 4)
V GG Capacitance (Note 4)
f = 1.0 MHz, V 1N = OV
f = 1.0 MHz, V 1N = OV
Address Time (Note 2)
See Timing Diagram
T A ~ 25°C,
Vss = 5V
VGG = Voo = -12V
TAccEsS
Output AND Connection
(Note 3)
mA
2.5
6.5
12.0
1
mA
IlA
1
IlA
5
15
25
pF
pF
700
950
ns
6.8K ±5% to V GG Plus One
Standard Series 54/74 Gate
Note 1: TtJe VGG supply may be clocked to reduce device power without affecting access time.
Note 2: Address time is measured from the change of data on any input or Chip Enable line to the
output of a TTL gate. (See Timing Diagram.) See curves for guaranteed limit over temperature.
Note 3: The address time in the TTL load configuration follows the equation:
T ACCESS = The specified limit + IN -1) (501 ns
Where N = Number of AND connections.
Note 4: Capacitance guaranteed by design.
3-22
V
V
8
s:
s:
performance characteristics
oIlIo
N
Power Supply Current vs
Power Supply Voltages
.....
.....
.......
Power Supply Current vs
Ambient Temperature
s:
s:
U'I
16
16
Voo:= VGG
TA=25°C
14
Vss " +5.0V
Voo '" VGG - 7.2V
14
12
N
12
MAXIMUM
.....
.....
I'S.
MAXIMUM
----+---'--f
5 - B7
r:c=>p-----~----~'-
OTLrrTLLOGIC
512 x 4 ROM connection
Mode Control - LogiC "1"
Ag
- Logic "0" Enables the odd
(B1, B3 ... Bg) outputs
- Logic "1" Enables the even
(82,84, .. Ss) outputs.
,
I
,
21
4 - 8,
,I
n
3 -At
NC_ 23
2 -A2
NC-
1 _A,
1
tSee operatill!! mode lIotes.
1
Operating Modes
256 x 8 ROM connection (shown)
Mode Control - Logic "0"
Ag
- LogiC "1"
\
l:C=>p----t--,/';""
OUT1'UlS
,
,
,
,
The outputs are "Enabled" when a logic "1"
applied to the Chip Enable line.
Logic levels are negative true MaS logic.
I
I
I
I
I
IS
1
Mode Control should be "hard wired' to V LL
(Logical "1 ") or VSS iLf)qical "O"}.
3-27
PROMs/ROMs
MM4214/MM5214 4096-bit static read only memory
general description
features
The MM4214/MM5214 4096-bit static read only
memory is a P-channel enhancement mode monolithic MaS integrated circuit utilizing a low threshold voltage technology to achieve bipolar compatibility_ TRI-STATE® outputs provide wire
ORed capability without loading common data
lines or reducing system access times. The ROM
is organized in a 512 word X 8-bit memory
organization.
•
•
Customer programs may be submitted for production in a paper tape or punched card format.
Pin compatible with MM5204 PROM
Bipolar compatibility
No external
components required
+5.0V,-12V
• Standard supplies
TRI-STATE outputs
• Bus aRable output
No clocks requ ired
• Static operation
applications
• Character generator
• Random logic synthesis
• Microprogramming
• Table look-up
logic and connection diagrams
Dual~ln·Line
Package
NC
CHIP SELECT
24
23
22
NC
21
NC
..
A,
A,
A,
A,
B,
B,
V
DeCODE
MEMORY
ARRAY
.
A,
CHIPSELECTo---------------------------------~
B,
B,
B,
B,
B,
6
,
20
A,
A,
7
"18
A,
B
17
A, 10
"
A,
.•
15
11
14
Vss t2
"
A6
TQPVIEW
NC
v__
....
B,
B,
B,
B,
B,
B,
..
A,
Order Number MM4214J
or MM5214J
See Package 11
Order Number MM5214N
See Package 18
timing diagram/address time
TIME
Note: For programming information see AN-100.
3-28
absolute maximum ratings
Voo Supply Voltage
Vss - 20V
Input Voltage
(Vss - 20) V
Storage Temperature Range
< V'N < (Vss + 0.03) V
-65°C to +150°C
Operating Temperature Range
MM4214
MM5214
Lead Temperature (Soldering, 10 seconds)
-55°C to +125°C
-25°C to + 70°C
300°C
electrical characteristics
T A within operating temperature range, Vss
=+5.0V ±5%, V DO =-12V ±5%, unless otherwise noted.
CONDITIONS
PARAMETER
Output Voltage Levels
Logical Low Level (V,e)
Logical High Level (V'H)
TYP
MIN
MAX
0.4
Ie = 1.6 mA Sink
IL
= 100MA Source
2.4
Input Voltage Levels
Logical Low Level (V cl
Logical High Level (V H)
V ss -4.0
V ss -2.0
Vss = 5.0V, Vee =-12V, TA = 25°C
Power Supply Current
(Iss) (Note 4)
UNITS
V
V
V
V
23
37
mA
Input Leakage
V'N = Vss - 10V
1.0
IlA
Input Capacitance (Note 2)
f= 1.0 MHz, V'N =OV
5.0
10
pF
Output Capacitance (Note 2)
f = 1.0 MHz, V'N = OV
4.0
10
pF
Address Time (T ACCESS) (Note 1)
Vee = -12V, Vss = 5.0V, TA = 25°C
1000
150
ns
20
Output AND Connections (Note 3)
Note 1: CapaCitances are measured periodically only.
Note 2: Address is measured from the change of data on any input or chip enable line to the output of a TTL gate. (See
Timing Diagram.)
Note 3: The address time follows the following equation: T ACCESS = The specified limit + (N-1) x 25 ns where N = Number
of AND connections.
Note 4: Outputs open.
Note 5: Positive true logic notation is used. Logic "',. = most positive voltage level. Logic "0" = most negative voltage level.
typical performance characteristics
Typical Access Time
vs Supply Voltage
Guaranteed Access Time
vs Supply Voltage
1600
1
600_
1400
-125°C
1200 TA=10°C
"" 1000
- 25°C
oS
~ 800
1400
1200
.
:!
I-
400
600 •
•
800
&00
400
200
200
o
-IZ5°C
1000 TA-l0°C
_25°C
0
16.2
11.0
Vss
16.2
I1.B
+ 1Vool (V)
Power Supply Current
VI Temperature
Vss - 5.0V
~
Voo - -12V
60
5°l J~l ~j !l l!l1l1l1
50
MAXIMUM
30
<
TYPICAL
1jI 40
MAXIMUM
30
TYPICAL
20
20
10
10
-50 -25
0
25
50
15 100 125
TEMPERATURE 1°C)
T.-25°C
10
60
40
11.8
Power Supply Current
vsVoltage
BO.~
10
11.0
Vss + IVool(V)
16.2
11.0
11.8
Vss + IVODI (V)
3·29
PROMs/ROMs
MM5215 12,288-bit read only memory
general description
features
The MM5215 12,288-bit static read only memory
is a P-channel enhancement mode monolithic
MOS integrated circuit utilizing low threshold
voltage technology and ion-implanted resistors.
TRI-STATE® outputs provide wire-OR capability
without loading common data lines or reducing
system access times. The ROM is organized in a
1024x 12 bit word configuration. The VGG supply
may be brought to OV to reduce internal power
dissipation in the non-enabled mode to 10JjW/bit.
•
•
•
•
•
Static operation
TRI-STATE outputs
No clocks required
+12V and -12V supplies
Pin compatible with E.A. 3800
applications
Customer programs may be submitted on Hollerith
coded punched cards.
• Character generator
• Random logic synthesis
• Microprogramming
• Ta!:IIe look-up
schematic diagram
M"
.,
..
0'2 Msa
0"
0"
0,
MEMORY
MATRIX
"
"
0,
0,
OUTPUT
DRIVER
10Z4X12
0,
0,
o.
0,
0,
UIA,
O,LSB
--The output is enabled by applving a Logic Hi!#! to tbe Chip Enable.
*CHIP ENABLE
cOi'mection diagram
Dual-In-Line Pack_
MSi
VlXl
O,~
v.Ne
Ne
Vao
0"
~
0",
0,
~
Ac
08
07
De
A3
A2
TOP VIEW
Note: For programming
information see AN-l00.
3-30
Order Number MM5215AD
See Package 7
CHIP
05 ENABLE 04
A,0
A,
MSS
LSB
As
03
O2
Aa
Order Number MM5215AN
See Package 19
absolute maximum ratings
V GG Supply Voltage
Input Voltage
Vss +0.5V to Vss -30V
Vss +0 5V to Vss -30V
800mW
O'C to +70'C
-65'C to +150'C
300'C
Power Dissipation at 25°C Ambient
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
electrical characteristics
T A within operating temperature range Vss
0::
+12V ± 1.OV, V DO
=:
OV, VGG = -12V
CONDITIONS
PARAMETER
MIN
Input Voltage Levels
Logical "1"
Logical "0"
(Note 11
(Note 11
Vss - 2.0
Output Voltage Levels
Logical "1"
Logical "0"
No Load
No Load
Output Current
Logical "1"
Va = Vss
Va = Vss - 6.0V
Logical "0"
Va = Vss - 12V
Va = Vss - 6.0V
±, .OV unless otherwise specified.
TYP
MAX
UNITS
Vss - 9.0
V
V
Vaa
Vss
V
V
2.5
0.7
-2.0
-1.5
mA
mA
mA
mA
Power Supply Current
Iss
Standby Power Dissipation
Vss = +13V, Vaa = OV,
VGG =-13V
30
mA
Vss = +13V, Vaa = OV,
V GG =-13V
15
mA
Vss = +12V, Vaa = OV
V GG = OV, T A = 25'C
150
mW
Vss = +12V, Vaa = OV
VGG = -12V, T A = 25'C
300
mW
TA =25'C
3.0
Address Ti me
T ACCESS
/1S
Note 1: Positive logic definition.
switching time waveforms
ADDRESS _ _ _
~X\._________. IX\.____
~.5V
CHIP ENABLE
-
DATA OUTPUT
DATA NDT VALID
r--
~I\
TRI·STATE@
I---- , _
TRI-STATE®
3-31
PROMs/ROMs
MM4220/MM5220 1024-bit read only memory
general description
The MM4220/MM5220 is a 1024-bit static read
only memory. It is a P-channel enhancement mode
monolithic MOS integrated circuit utilizing low
threshold voltage technology. The device is a nonvolatile memory organized as 128-8-bit words or
256-4-bit words. Programming of the memory contents is accomplished by changing one mask during
the device fabrication. Customer programs may be
supplied in a tape, card, or pattern selection format.
•
Static operation
•
Common data busing
•
Chip enable output control.
•
Random logic synthesis
features
•
Table look-up
•
Character generators
•
Microprogramming
•
Bipolar compatibility
•
High speed operation
500 ns typ
no clocks required
output wire AND
capability
applications
•
Code conversion
block and connection diagrams
SENSE AMPLIFIERS
INPUTS
OUTPUTS
B,LSD
lSB
A,
Dual-In-Line Package
A,
S,
S,
So
INPUT AJ
Voo
INPUT III
NO
LSB INPUT A,
NO
lSB OUTPUT 8,
INPUT A.
"
OUTPUT 82
A,
So
INPUTA 5
OUTPUT 83
INPUT As
OUTPUT 8.
INPUT A]
S,
S,
OUTPUT 85
Voo
OUTPUTBij
MODE
CONTROL
OUTPUT 8 7
CHIP
ENABLE
MSB OUTPUTB a
A, _ _ _
~_-'
INPUT As MSB
V"
TOP VIEW
MODe CONTROL-----L~
"
Order Number MM4220J
or MM5220J
See Package 11
Order Number MM5220N
See Package 18
Note: For programming information see AN-l00.
3·32
3:
3:
,f:o
N
N
absolute maximum ratings
o
........
VGG Supply Voltage
Voo Supply Voltage
Input Voltage
(V ss -20)V
Storage Temperature
Operating Temperature MM4220
MM5220
Lead Temperature (Soldering, 10 sec)
<
3:
3:
Vss-30V
V ss -15V
Y'N < (V ss +0.3)V
-65°C to +150°C
-55°C to +125°C
O°C to +70°C
300°C
U1
N
N
o
electrical characteristics
TA within operating temperature range, Vss = +12V ±5% and VGG = -12V ±5%, unless otherwise specified.
PARAMETER
Output Voltage Levels
MOSto MOS
Logical "1"
Logical "0"
MOSto TTL
Logical "1"
Logical "0"
CONDITION
1 MU to GND Load (Note 1)
6.8 kU to V GG Plus One
Standard Series 54/74 Gate Input
MIN
TVP
MAX
UNITS
Vss -9.0
V
V
+0.4
V
V
Vss -8.0
V
V
Vss -1.0
+2.4
Input Voltage Levels
Logical "1"
Logical "0"
Power Supply Current
Vss -2.0
TA = 25°C
19
Vss
VGG (Note 1)
I nput Leakage
Input Capacitance
f= 1.0MHz
T A = 25°C
(See Timing Diagram)
Vss = +12V VGG = -12V
Output AN 0 Connection
mA
IlA
1
IlA
Y'N = Vss -12V
Access Time (Notes 2, 3)
T ACCESS
25
1
pF
5
Y'N = OV
150
500
650
MOS Load
TTL Load
ns
3
8
Note 1: The VGG supply may be clocked to reduce device power without affecting access time.
Note 2: Address time is measured from the change of data on any input or Chip Enable line to the output of a TTL gate.
See Timing Diagram.
Note 3: The access time in the TTL load configuration follows the equation: TACCESS
where N = number of AND connections.
= the specified time +
(N - 1) (50) ns
3·33
performance characteristics
Typical Acc_ Time vs
Supply Voltages
Guaranteed Access Ti me VI
Supply Voltages
TA • 125'C
1000
:g
1000
TA • l/;"C
800
800
]
T•• 25'C
m600
hoo
400
.... 400
200
200
J
~
18.8
12.0
13.2
125'ciPt
1':7,·
'7~~
25'C
13.2
12.0
18.8
Vss & VGG (V)
Vssl V.G (VI
Power Supply Currant vs
Temperature
Power Supply Current vs
Voltage
fA = 25°C
24
26
.J;'
22
!j
Vss =+12.0V
VGG = -12.0V
GUARANTEED
.....
",
20
!
18
22
14
GUARANTEED
"-
.E 18
16
I
'\
.
TYPICAL
i'-
"
r-...
TYPICAL
14
10.8
13.2
12.0
r-...
!'....
-50 -25 0 25 50 75 100 125
TEMPERATURE ('CI
Vss & VGG(VI
timing diagram/address time
+lv
I
INPUT A:,i
.3TL
OV
I
UK
..v
EIN~::10PF
DM881D
T'
I
MM42201MM5Z2D
i
I
~
'6V
OUTPUTs,.
I
UK
10 ,F
±
±
-ANY DTL/TTL
GATE
-,lv
+12V
ov
~
~
r----
E"
+12V
~
TAccess ______
OR
ov
.3V
1.5V
0
EOUT
'3V
DV
3-34
UV
....
15 ,F
EOUT
typical application
128-8 Bit ROM Showing TTL Interface
'
.
..
B,
CHI~
ENABlE
.
t MOPE
CONTROL
V,.
A,
'~'l
u,
..
..
.
U,
}-
B,
"
B,
MPM22l1JMM5220
I,
..
"
I,
A,
O"110RD.IIll
TTL6ATES
Z3
V"
.
A,
tSae operating modenotils.
"="
*R values caR vary from 140 to 3D kn depending on speed requilllments.
OPERATING MODES
128x8 ROM connection
Mode Control - Logic "0"
As
- Logic "1"
256x4 ROM connection
Mode Control - Logic "1"
As
- Logic "0" Enables the odd
(8 1 ___ B7 ) outputs
- Logic "1" Enables the even
(B 2 ___ B8 ) outputs.
The outputs are "Enabled" when a logic "1" is
applied to the Chip Enable line.
The outputs are connected to V DO through an
internal MaS resistor when "Disabled."
The logic levels are in negative voltage logic notation.
3-35
PROMs/ROMs
MM4221/MM52211024-bit read only memory
general description
The MM4221/MM&221 is a 1024-bit static read
only memory. It is a P-channel enhancement mode
monolithic MOS integrated circuit utilizing low
threshold voltage technology. The device is a nonvolatile memory organized as 12B-B-bit words or
256-4-bit words. Programming of the memory
contents is accomplished by changing one mask
during the device fabrication.
•
Static operation
•
Common data busing
no clocks requ ired
•
Chip enable output control
output wire AND
capability
applications
•
features
Code conversion
•
Random logic synthesis
•
Table look-up
•
Bipolar compatibility
+5V. -12V operation
•
Character generators
•
High speed operation
<700 ns typ
•
Microprogramming.
block and connection diagrams
Dual-I n-Line Package
(LSB) A,
"
"
"
INPUT A,
"
'00
INPUT A,
lS81NPUTA,
"
"
MEMORV
ADDRESS
DECODER
"
"
.,.PUTA.
lSBOlJTPUT8,
"
OUTPUTS,
INPUTA, MSB
'"'
OUTPUTB.
MODE
CONTROL
OUTPUT 8,
CIIIP
'"
MSBounUTB.
'
.
ENABLE
INPUT A"
"
Order Number MM4221J
or MM5221J
See Package 11
Order Number MM5221N
See Package 18
Note: For programming information see AN-l00.
3-36
A"
INPUT
OUTPU11I,
OU1PU18 5
"---1----' ~""'-----~~~BlE
'''PUT A"
OUTPUTB J
absolute maximum ratings
V GG Supply Voltage
Voo Supply Voltage
Input Voltage
(V ss - 20)V
Storage Temperature
Operating Temperature MM4221
MM5221
Lead Temperature (Soldering, 10 sec)
Vss - 20V
Vss - 20V
< V'N < (V SS +0.3)V
_65°C to +150°C
-55°C to + 125°C
O°C to +70°C
300°C
electrical characteristics
T A within operating temperature range, Vss ~ +5V ±5%, VGG ~ Voo ~ -12V ±5%, unless otherwise specified.
PARAMETER
CONDITIONS
Output Voltage Levels
MOS to TTL
Logical "1"
Logical "0"
6.8 kSl ±5% to VGG Plus One
Standard Series 54/74 Gate
Output Current Capability
Logical "0"
V OUT
~
2.4V
Input Voltage Levels
Logical "1"
Logical "0"
Power Supply Current
100
IGG (Note 1)
+0.4
+2.4
V
V
2.5
mA
Vss - 4.2
T A ~ 25°C
Vss ~ +5V
VGG ~ Voo
6.5
~
Input Capacitance
V GG Capacitance (Note 4)
f
f
Address Time (Note 2)
See Timing Diagram
T A ~ 25°C,
Vss ~ 5V
VGG ~ Voo ~ -12V
~
~
1.0 MHz, V'N
1.0 MHz, V'N
~
~
OV
OV
V
V
12.0
1
mA
IlA
1
IlA
5
15
25
pF
pF
700
950
ns
-12V
V'N ~ Vss - 12V
Output AND Connections
(Note 3)
UNITS
TYP
Vss - 2.0
I nput Leakage
T ACCESS
MAX
MIN
6.8 kSl ±5% to V GG Plus One
Standard Series 54/7 4 Gate
8
Note 1: The VGG supply may be clocked to reduce device power without affecting access time.
Note 2: Address time is measured from the change of data on any input except mode control or Chip
Enable line to the output of a TTL gate. (See Timing Diagram). See curves for guaranteed limit
over temperature.
Note 3: The address time in the TTL load configuration follows the equation:
T ACCESS ~ The specified limit + (N - 11 (501 ns
Where N = Number of AND connections.
Note 4: Capacitance guaranteed by design.
3-37
performance characteristics
16Rm
16_
Power Supply Current vs
Power Supply Voltages
Power Supply Current vs
Ambient Temperature
Vee:: VGG
Vss':: +S.OV
~.::2rC
14
12
12
MAXIMUM
MAXIMUM
10
10
8
6
4
Vee VGG=-12V
14
8
tt::ttE~Bm
rn
~:::t:I::tt::tttttttj
17.0
~=t~~~~TV~P:ICfA~L;$_~~
~:::t:I::tt::ttttttt:l
4
: ffiE±±E:±Effi
: ffiE±±E:±Effi
16.0
~;d:tW;+t=tl=t=l=l
6 ~
TVPICAL
18.0
-50 -25
Vss - VGG (V)
Typical Access Time vs
Power Supply Voltages
]
1 1000
800
;::
600
~
~
'"
50
75
100
rr-.,-rr-r. ..,-,-,-,-.,
H-t-+t-l-t-t-+-t-Voo':: VGG
1200
tj~t~~;~~;~~~~~~~i"'+1-25+.o-lC
:~~:.~
1 '000 ~
+70°C
H-+-t-t-lH++-H-+ +25'C
J
800
~
600
H-++-HH++-H-+++-i
H-++-HH++-H-+++-l
400
~
400 H-+++-H++-H-+++-l
200
'"
200
o
0
16.0
18.0
17.0
H-++-HH++-H-+++-i
tttttttttttttJj
16.0
17.0
Vss - VGG (V)
18.0
Vss - VGG tV)
timing diagram/address time
'5'
+JV-rI
,•..J
L
t
INPUT
ANYTTl!OTl
GATE
.~ -
2
AN~
EIN~10Pf
T
L OUTPUT BM
-....--1
rru-..- -....-10Pf~
MM4221!MM5221
~
I1
68K
*"
GATE
'. ': _fr~:: '----1Ir---.,v ---.l
,
EOUT
.,v
'v
~
1.5V
1.5V
*"
ANVTTl!DTl J..15Pf
'v r----l
I EITHER
I
time
3·38
125
1400
H-t--t-t-l-t++-t-Voo':: VGG
1200
J
25
Guaranteed Access Time vs
Power Supply Voltages
1400
!
0
AM81ENT TEMPERATURE lOCI
EOUT
typical application
128-8 Bit ROM Showing TTL Interface
"
tCHIP
ENABlE
]--
"
"
MODE
CONTAOL
'
..
"
-!
tSee operating mode notes.
~
:
"
.
.
"
' .. ,
"
"
ANVl~~~£JTl
"
1
1
OPERATING MODES
'28x8 ROM connection
Control - Logic "0"
As
- Logic ","
256x4 ROM connection
Control - Logic ","
As
- Enables the odd (8 I
(8 2 ___ 8 s ) outputs.
___
87
)
or even
The outputs are "Enabled" when a logic "," is
applied to the Chip Enable line.
The outputs are connected to ground through an
internal MaS resistor when "Disabled."
Logic levels are negative true MaS logic.
Mode control should be "hard wired" to either
Voo (logical ",") or Vss (logical "0").
The logic levels are in negative voltage logic notation.
3-39
PROMs/ROMs
MM4229/MM5229 3072-bit read only memory (open drain)
general description
The MM4229/MM5229 is a 3072-bit static read
only memory_ It is a P-channel enhancement
mode monolithic MOS integrated circuit utilizing
low threshold technology_ The device is a nonvolatile memory organized in a 256 x 12 bit
word configuration_
•
Programmable chip select inputs
•
Typical 1.0,us access time
•
Open drain outputs allow wire-OR of up to
8 devices
applications
Customer programs may be supplied on Hollerith
coded punched cards.
•
Code conversion
features
•
Random logic synthesis
•
TTL compatible
•
Table look-up
•
Low standby power
•
Microprogramming
block diagram
10
connection diagram
Dual·ln·Line Package
28 NC
OUTPUT 12 I
OUTPUT 11 2
27 Ae
OUTPUT 10 :I
,. A,
OUTPUT 9 4
2S A,
OUTPUT. 5
OUTPUT 7 &
OUTPUT 6
7
OUTPUT 5
•
23 Vss
OUTPUT 4 9
20 A,
OUTPUT 3 10
19 As
OUTPUT 2 11
18 NC
OUTPUT 1 12
11 CE
I. CS,
Voo 13
15 CS 2
TOP VIEW
Note: For programming
information see AN-l00.
3-40
Order Number MM4229D
or MM5229D
See Package 7
Order Number MM5229N
See Package 19
11
12
absolute maximum ratings
All Inputs or Outputs with Respect to the
Most Positive Voltage Vss (Substrate)
Supply Voltage Voo and Vo with Respect
to Vss (Substrate)
Operating Temperature Range
MM4229
MM5229
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
+0.3V to -20V
+3.0V to -20V
-55°C to +125°C
-25°C to +70°C
-65°C to +125°C
300°C
electrical characteristics (Note 1)
TA within operating temperature range, Voo = -12V ±10%, Vss = +5V ±5%, unless otherwise specified.
PARAMETER
CONDITIONS
Data Input Levels
Logical High Level IV,H)
Logical Low Level (V ,L )
Data Output Levels
Logical High Level (V OH )
Logical Low Level (VOL)
MIN
Vss = +4.75V
Vss = +4.75V
+2.4
6.8 kn ±5% to V OD Plus One
+2.4
TYP
MAX
Standard Series 54/74 Gate
UNITS
+0.8
V
V
+0.4
V
V
Output Current Capability
V OUT = 2.4V
Logical "0"
2.5
rnA
Data Input Leakage (lAI)
Y'N - Vss = -5V
2.0
/.lA
Data Output Leakage (I AO )
V OUT - Vss = -5V (Note 1)
2.0
/.lA
Data Input Capacitance (C IN )
Y'N - Vss = OV
5.0
pF
Data Output Capacitance (C OUT )
V OUT -Vss =OV
8.0
pF
Access Ti me (T A)
Address Response (tAA)
C Inhibit Response (tAd
CL = 20 pF
CL = 20 pF
1.0
0.8
1.4
1.2
/.ls
/.ls
Vss = +5V, V, = OV
Voo = 12V, TA = 25°C
25
25
32
32
rnA
rnA
2.0
2.0
/.lA
/.lA
18
18
rnA
rnA
Active Power Supply
Voo Supply (1 00 )
Vss Supply IIss)
Data Input Currents
Logical High Level (I,H)
Logical Low Level (IlL)
Y'N - Vss = -2.4V
Y'N -Vss =5V
Standby Power Supply
Vss = +5V, V, = OV
Voo = -12V, TA = 25°C
100
Iss
12
12
Note 1: Chip inhibited or de-selected.
Note 2: The above logic levels are indicated in negative logic notation.
switching time waveforms
-,r----1.5V
-----.11
1 -----I
I
l.--IAA---l
I
I
-----I----~r__
I
I\,,'~ _ _ _
~I/----.,-----
----_.1*;:1.5V
1
I
I
I--- tAC----1
I
I
I I r----
____ J ____ ~..
'_.5_V_ _
Definitions:
Access Time: Represents the total propagatIOn delay through input translatiun decode for memory s~lection and output sense amplification of the
memory signal and is measured from the last input transition through 1.5V to the last output transitioll through 1.5V.
Chip Ellable: The output source and sink transistors are turned off In the chip inhibit and chip de·select mode to allow OR·tleing of output for easy
memory expansion.
Chip Select: The outputs are ellabled and data from the selected memory location will appear at the outputs. The chip select and chip enable inputs
are programmable for decoderlessword expansion.
3-41
PROMs/ROMs
MM4230/MM5230 2048-bit read only memory
general description
The MM4230/MM5230 is a 2048-bit static read
only memory. It is a P-channel enhancement mode
monolithic MOS integrated circu it utilizing low
threshold voltage technology. The device is a nonvolatile memory organized as 256-8 bit words or
512-4 bit words. Programming of the memory contents is accomplished by changing one mask during
the device fabrication. Customer programs may be
supplied in a tape, card, or pattern selection format.
features
•
Bipolar compatibility
•
High speed operation
500 ns typ
no clocks required
output wire AND
capability
•
Static operation
•
Common data busing
•
Chip enable output control.
applications
•
Code conversion
•
Random logic synthesis
•
Table look-up
•
Character generators
•
Microprogramming.
block and connection diagrams
SENSE AMPLIFIERS
Dual~ln~Line
OUTPUTSt
Package
8 1 {LSB}
B,
B,
B.
"
INPUTA3
24
INPUTA 2
"
LSB INPUTA 1
22
LSBOUTPUTB 1
21
lNPUT~
OU1PU182
"
"
INPUT As
OU1PU18 4
18
INPUTA1
OU1PU185
17
OU1PUT8 3
V"
INPUT As
B,
B,
OUTPU186
OUTPUT 87
INPUT As MSB
V"
MODE
10
C.ONTROL
B,
CHIP
MSB OU1PU188
ENABLE
V"
. ---..--.....
MODECONTROL-----L-.r
Note: For programming information see AN·100.
3-42
12
13
INPUTAg
TOP VIEW
CHIP
ENABLE-
Order Number MM4230J
orMM5230J
See Package 11
Order Number MM5230N
See Package 18
absolute maximum ratings
VG G Supply Voltage
Vo 0 Supply Voltage
Input Voltage
(V ss -20)V
Storage Temperature
Operating Temperature MM4230
MM5230
Lead Temperature (Soldering, 10 sec)
Vss-30V
Vss -15V
< V'N < (V ss +0.3)V
-65°C to +150°C
_55°C to +125°C
O°C to +70°C
300°C
electrical characteristics
T A within operating temperature range, Vss
PARAMETER
Output Voltage Levels
MOSto MOS
Logical "1"
Logical "0"
MOSto TTL
Logical "1"
Logical "0"
= + 12V
±5% and V GG
=
-12V ±5%, unless otherwise specified.
CONDITION
1 MS1 to GND Load (Note 1)
MIN
TYP
MAX
UNITS
Vss -9.0
V
V
+0.4
V
V
Vss -8.0
V
Vss -1.0
6.8 kS1 to V GG Plus One
Standard Series 54/74 Gate Input
+2.4
Input Voltage Levels
Logical "1"
Logical "0"
V
Vss -2.0
Power Supply Current
T A = 25°C
24
Vss
VGG (Note 1)
I nput Leakage
V'N = Vss -12V
I nput Capacitance
f = 1.0 MHz
Access Time (Notes 2, 3)
T A = 25°C
(See Timing Diagram)
Vss = +12V VGG=-12V
TACCESS
Output AND Connection
40
1
mA
1
IlA
pF
5
V'N = OV
150
500
MOS Load
TTL Load
IlA
725
ns
3
8
Note 1: The VGG supply may be clocked to reduce device power without affecting access time.
Note 2: Address time is measured from the change of data on any input or Chip Enable line to the output of a TTL gate.
See Timing Diagram.
Note 3: The access time in the TTL load configuration follows the equation: TACCESS
where N
= number
=
the specified time + (N -1) (50) ns
of AND connections.
Note 4: The above logic levels are indicated in negative logic notation.
3-43
performance characteristics
Guaranteed Access Time
vs Supply Voltages
1000
'" 800
Typical Access Time vs
Supply Voltages
I-H-++++-l-,-+-++-I-H-H
1'.." '" 12$OC
1000
I-t+H-+-j;T~,:.. 7';t':++-I-++1
I-t+-l-+-H T, • 2S"o"'C"i-+-i++-I
800
.5
.5
~ 600
~ 600 1-t-H-++1-++-++-H-H--H
J
400
H---H-++-t+H+H---H-+-I
.... 400
200
I-t+H++-+++-+++-+++1
200
10.8
12.0
rl
~
13.2
lr5;eFt{t
10°S:::!
iar-10.8
12.0
13.2
Vss & VGa (V)
Vss & VGG (V)
Power Supply Current
Power Supply Current
vs Temperature
vs Voltages
~ r-r-r-r-r-r-r-~~
50
36
H-++--H:.I"'I-l-++--H--=I--1
1 32
H-+++--H-+-hloo"l,++-H
g
H-++-l-:""", TYPICAL -
24
H.-1"+--H-++-I-++--H-H
20
r-t-t-t-t-t~-f~-+-+
10
r-t-+-+-+-++-t-t-+
132
12.0
10.8
1
o
o
28
t--++-+-+-r Vss = +12.0V
t---±M""A""Xf-+--+-+-VGG =-12.0V
-50 -25
0 25 50 15 100 125 150
TEMPERATURE rei
Vss & VaG (V)
timing diagram/address time
.,v
"v-rI
OV...J
L
I
l.OK
I
INPUT AN
.J
)O-~~---Il-lJ
OM8810
If
MM42JD/MM52JO
TL.- lOP ' '1 I
E,,/
.,v
I
L OUTPUT 8M
ILt~--""'--""--I
68K
,::I-:
--
~
0
EOUT
·,V
OV
1.5V
I
time
3-44
Eour
::I-:
10PF~ AN\DA~l~TTL ~
15pF
typical application
256 x 8 Bit ROM Showing TTL Interface
+12V----------...~r-------------------------_,
~V--~-------r~r---------------------------r--+--+--t-----.-- ,'v
V"
t A,
UK
1J
UABLE
B,
t MODE
B,
CONTROL
V"
..
A,
B,
A,
6.8K
6.81(
}..-
B,
.
MM42JIIIMM52JD
B,
A,
20
A,
DM8BIO
TTl GATES
V,,
B,
B,
22
A,
2J
A,
A,
tSee operating modl,l notes.
*R values&an vary from 740H tu 30 kSl.
OPERATING MODES
'28x8 ROM connection
Mode Control - Logic "0"
A9
- Logic "'"
256x4 ROM connectiqn
Mode Control - Logic "'"
Ag
- Logic "0" Enables the odd
(B, ' ' , B7 ) outputs
- Logic "'" Enables the even
(B, ' , , B8 ) outputs,
The outputs are "Enabled" when a logic "'" is
applied to the Chip Enable line,
The outputs are connected to V DO through an
internal MOS resistor when "Disabled,"
The logic levels are in negative voltage logic notation,
3·45
PROMs/ROMs
MM4231/MM5231 2048-bit read only memory
general description
The MM4231(MM5231 is a 2048-bit static read
only memory. It is a P-channel enhancement mode
monolithic MOS integrated circuit utilizing low
threshold voltage technology. The device is a nonvolatile memory organized as a 256-8 bit words or
512-4 bit words. Programming of the memory
contents is accomplished by changing one mask
during the device fabrication.
features
•
Static operation
•
Common data busing
No clocks required
•
Chip enable output control
Output wire AND
capability
applications
•
Code conversion
•
Random logic synthesis
•
Table look-up
•
Bipolar compatibility
+5V, -12V operation
•
Character generator
•
High speed operation
640 ns typo
•
Microprogramming
block and connection diagrams
Dual·ln·Line Package
SENSE AMPLIFIERS
INPuts
B,
INPUTA3
(lSB) A,
INPUT A,
B,
lSBINPUTA ,
B,
INPUT~
lSBOUTPUTB,
2D
B.
INPUTA.
A"
OUTPUT 83
INPUT
OUTI'1.I184
INPUT A,
OUTPUlB.
INPUTA. MSR
B,
B.
OUTPUT
B~
'"
B,
MODE
CONTROL
OUTPUT 8,
B.
CHIP
ENASH
MSB OUnUTB.
INPIJTA.
TOP VIEW
....
'.---
- - - ' y------~~~8LE·
MOOECONTROL-----L.J
tThe outputs are connected to Voo through an internal MOS resistor when Disabled.
*The output is enabled by applying a Logic "1" to the Chip Enable line.
Note: For programming information see AN·l00.
3·46
Order Number MM4231J
or MM5231J
See Package 11
Order Number MM5231N
S.e Package 18
absolute maximum ratings
V GG Supply Voltage
Voo Supply Voltage
Input Voltage
Storage Temperature
Operating Temperature
(V ss - 20)V
<
MM4231
MM5231
Lead Temperature (Soldering, 10 sec)
Vss - 20V
Vss - 20V
VIN
(V ss + 0.3)V
_65°C to +150°C
_55°C to +125°C
O°C to +70°C
300°C
<
electrical characteristics
PARAMETER
TYP
CONDITIONS
MIN
Output Voltage Levels
MOS to TTL
Logical "1"
Logical "a"
6.8 kn ±5% to V DO Plus One
Standard Series 54/74 Gate
2.4
V
V
Output Current Capability
Logical "a"
V OUT
2.5
mA
~
+0.4
2.4V
Input Voltage Levels
Logical "1"
Logical
"a"
Power Supply Current
100
I GG (Note 1)
I nput Leakage
MAX
Vss - 4.2
V
V
30
1
mA
1
fJ.A
Vss - 2.0
TA ~ 25°C
Vss ~ +5V
VGG ~ Voo
VIN
~
15
~
-12V
-12V
UNITS
fJ.A
I nput Capacitance
f
~
1.0 MHz, VIN
~
OV
5
pF
V GG Capacitance
f
~
1.0 MHz, VIN
~
OV
15
pF
Address Time (Note 2)
See Timing Diagram
T A ~ 25°C Vss ~ +5.0V
VGG ~ Voo ~ -12.0V
TAccEsS
Output AN 0 Connections
(Note 3)
640
6.8 kn ±5% to Voo Plus One
Standard Series 54/74 Gate
Note 1: These specifications apply for VSS ~ +5V ±5%, VGG = VOO = -12V, ±5%, and TA
to +125°C IMM4231), T A = -25°C to +70oC (MM5231) unless otherwise specified.
950
ns
8
= -55°C
Note 2: .1he VGG supply may be clocked to reduce device power without affecting access time.
Note 3: Address time is measured from the change of data on any input or Chip Enable line to the
output of a TTL gate. (See Timing Diagram.) See curves for guaranteed limit over temperature.
Note 4: The address time in the TTL load configuration follows the equation:
T ACCESS = The specified limit + (N - 1) (50) ns.
Where N = Number of AND connections.
Note 5: Capacitances are measured on a lot sample basis only.
3·47
performance characteristics
Typical Access Time (TAl
Guaranteed Access Time (T A)
vs Power Supply Voltage
vs Power Supply Voltage
1400
1400
Voo = VaG
1200
Voo '" VGG
1200
+125"C
+10 o 'C
1000
1000
+25°'C
800
]
600
~ 600
400
400
200
200
]
~
+1,25"C
800
+70"C
~25~C
0
0
16.0
18.0
17.0
16.0
Ambient Temperature
Power Supply Voltage
40
32
TA
24
;0
.!
~
",
25°C
Vss= +5.Dvt4
36
32
l-2u~~~I~TUE~D
20
;0
I--
Voo:: VaG:: -12V
111
28
24
MAXIMU'?;:
GUARANTEED
.! 20
~ 16
16
12
18.0
Power Supply Current vs
Power Supply Current vs
28
17.0
Vss - VGG (V)
Vss - VaG (V)
TYPICAL
8
12
8
4
4
0
0
16.0
iTn
IIII
-50 -25
18.0
11.0
lU
H-UJ..
Vss - VGG (V)
0 +25 +50 +15 +100 +125
TA rCI
timing diag rami add ress time
1::\
~'"---l
E"
~~
15V
fOUT
1.5V
I
time
'5V
'5V
+JYL
OV
I
ANY TTL/OlL
GATE
Iv"
INPUT AN
fiN
~ 11) pF
'f
MM42Jt/MM5231
vool
'5V
t'
III pF
I'D
6.aK
-,Tv
3-48
I
hOUTPUTBM
l
~
ANY TTL/On
GATE
~ 15 pF
'f
fOUT
typical application
256 x 8 Bit ROM Showing TTL Interface
'.
v"
t CHIP
ENABLE
}-"
B.
B,
MOllE
CONTROL
f
B.
v,"
'.
B.
"
...
~"I
B.
MM4231/MM5231
B,
'.
B,
'.
B,
v,,
"
"
TIL GATES
1
tSee operating mode notes.
"
I
"
1
1
Operating Modes
256 x 8 ROM connection (shown)
"a"
Mode Control - Logic
Ag
- Logic "1"
512 x 4 ROM connection
Mode Control - Logic "1"
Ag
- Logic "0" Enables the odd
(B" B3 ... B91 outputs
- Logic "1" Enables the even
(B2, B4 ... BSI outputs.
The outputs are "Enabled" when a logic "1" is
applied to the Chip Enable line.
Logic levels are negative true MOS logic.
Mode Control should be "hard wired" to VOO
(Logical "1"1 or VSS (Logical "0").
The logic levels are in negative voltage logic notation.
3-49
PROMs/ROMs
MM4232/MM5232 4096-bit static read-only memory
general description
features
The MM4232/MM5232 4096-bit static read-only
memory is a P-channel enhancement mode monolithic MaS integrated circuit utilizing a low threshold voltage technology to achieve bipolar compatibility. TRI-STATETM outputs provide wire ORed
capability without loading common data lines or
reducing system access times. The ROM is organized in a 512 word x 8-bit or 1024 word x 4-bit
memory organization that is controlled by the
mode control input. Programmable Chip Enables
(CE 1 and CE 2 ) provide logic control of up to 16K
bits without external logic. A separate output
supply lead is provided to reduce internal power
dissipation in the output stages.
• Bipolar compatibility
No external
components required
• Standard supplies
+5V, -12V
• Bus aRable output
TR I-STA TE outputs
• Static operation
No clocks required
• Multiple ROM control
Two-programmable
Chip Enable lines
applications
•
•
•
•
Character generator
Random logic synthesis
Microprogramming
Table look-up
logic and connection diagrams
Dual-In-Line Package
A.
B,
A,
B,
A,
B,
MEMORY
ARRAY
...
A,
A"
MODE
CONTROL
CE,
CE,
Note: For programming information see AN·100.
3·50
B.
s,
a.
s,
B.
MODE CONTROL
1
24
VioL
eE,
.2
23
VaG
CE2
3
22 Be MSI
21.,
.. .
..... ,,,
.. "
A"
LSI A,
A,
11
VIS
12
.. a.
" ..
11
..
17
83
" .,
15 ., LSI
14 "- Msa
13 ..
TOP VIEW
Order Number MM4232J
orMM5232J
Sao Package 11
Order NumberMM5232N
Se. Packag. 18
absolute maximum ratings
V GG Supply Voltage
V LL Supply Voltage
Input Voltage
(Vss - 20)
Storage Temperature Range
Operating Temperature Range MM4232
MM5232
Lead Temperature (Soldering, 10 sec)
electrical characteristics
Vss - 20V
V ss -20V
v < V'N < (VSS + .03)V
_65°C to +150°C
_55°C to +125"C
O°C to +70°C
300°C
POSITIVE LOGIC
T A within operating temperature range, VSS = +5.0V ±5%, V GG = Voo = -12V ±5%, unless otherwise noted.
PARAMETER
CONDITIONS
Output Voltage Levels
Logica' "0", VOL
logical "1", VOH
MIN
TYP
Vss-4.0
Vss + 0.3
V
V
23
12
37
mA
mA
5
15
pF
10
pF
1000
ns
VGG
Vss - 2.0
Logical "''', V LH
Vss
Vss
= 5, VaG = -12. VLL = -12. TA = 25°C
= 5, VGG = -12, V LL = -3, TA = 125°C
Input Leakage
VIN :::: Vss -l·QV
Input Capacitance (Note 1)
f
= 1.0 MHz, V'N = OV
Output Capacitance (Note 1)
f
= 1.0 MHz, V'N = OV
Address Time (Note 2)
TA = 2SOC, Vss
T ACcess
VGG
V
V
2.4
Input Voltage Levels
Logical "0". V IL
Iss INote 4)
UNITS
.4
IL = 1.6 rnA Sink
IL = 100 $.LA Source
Power Supply Current
Iss (Note 4)
MAX
20
1
4
=5
150
jlA
= V LL "" -12V
20
Output AND Connections (Note 3)
Note 1: Capacitances are measured periodically only.
Note 2: Address time is measured from the change of data on any input or Chip Enable line to the output of a TTL gate.
(See Timing Diagram.)
Note 3: The address time fOllOWS the following equation: T ACCESS = the specified limit + (N - 1) x 25 ns where N = Number
of AND connections.
Nota 4: Outputs open.
timing diagram/address time
\1lljv;:..,,-.;....=+-_
EIN
..v
E~
': ...f"L
54/1.
GATE
T'OPF
+iV
.,v
-~ T
"'74
--
,. of
-../'v_-.
EITHER OR ~
EOUT
GATE
r'I,F
....
TIME
3·51
performance cha racteristics
Typical Access Time VI
Supply Voltage
Guaranteed Access Time vs
Supply Voltage
1800
VLL • VaG
1400
,!':-
lZ00
125'C
IODD T.=711"C
!IOO
400
400
zoo
200
11.2
18.2
17.1
17.0
2r'C
c
.... 600
V.. +,VooIlVI
Power Supply Current vs
Voltage
Power Supply Current vs
Temperature
V.. -5.0V
Voo= VLL '"-12V
70
70
60
80
C
17.8
17.0
V.+IVoG I (V)
C 50
50
540
J
MAXIMUM
.!40
MAXIMUM
30
TYPICAL
J
30
TYPICAL
20
ZO
10
10
-50 -25
0
25
50
18.2
75 100 125
17.0
17.'
v.. +,v.a , (VI
TEMPERATURE rCI
typical applications
TTLIMOS Interface
v.
A,
B,
A.
A,
.
..
....
B.
MM4232/
MM5Z32
A,
B,
FIGURE ,. PowerSaverfor
Small Memory Arrays
rI
I
I
I
FIGU RE 2. Power Saver for
Large Mom Dry Arrays
--,
r----,
I
I
I
I
I
'::" I
I
I
I
I
I
I
L ___ ...J
L ___ ...J
ASSUME IIvl..l. IIMIN - 11-3V II
MODE
VOO-VLLMIN = R (1.& mAl (N)vm.-a N- 7tDr51t 11ont.
CONTROL
N.. lforh8font.
CE,o----.....J
CE,o-----~
512 x 8 ROM connection
Mode Control = VIH
A,0' V'L
Operating Modes
1024 x 4 ROM connection
Mode Control = VI L
A10 = VI L enables the odd (8, ... 87) outputs
VI H enables the even (82 ... 8S' outputs
Note: Both chip enab'es may be programmed to provide any of four combinations. Example if CE, • , and CE2 = 1
outputs (Positive Logic) would be enabled only when device pins 2 and 3 are Logic ",". The outputs will be in the
third state when disebled.
3·52
PROMs/ROMs
MM4233/MM5233 4096-bit read only memory
general description
The MM4233/MM5233 4096-bit static read only
memory is a monolithic MaS integrated circuit
utilizing P-channel ion-implanted enhancement
mode low threshold technology to achieve bipolar
compatibility. The ROM is organized in a 512
word x a-bit format.
•
No external components
required
Bipolar compatible
+5.0V, -12V
• Standard supplies
•
Bus aRable outputs
TRI-STATE outputs
No clocks required
• Static operation
Four programmable
chip select lines
Four programmable chip selects provide logic control of the TRI-STATE® outputs, allowing wire
OR capability of up to 16 ROM's without loading
common data lines or reducing systems access
times. A separate output supply lead V DO is provided to reduce internal power dissipation in the
output stages.
•
features
•
Microprogramming
•
•
Control logic
•
Table look-up
Multiple
ROM control
applications
•
Pin for pin compatible with the Fairchild
3514
Code conversion
logic and connection diagrams
.
.
---OVOG
VDD
. - - , •.r--~Oo LSI
Msa As
I"
D,
X
MEMORY
DECODE
ARRAY
D,
23
.
..
22
~
~
20
"
~
"
19
.. ..
11
16
..
15
USB
..
~
14
~
.--,.;e---.~D,
A,
D,
Ao
Do
1
LSB
~
13
D,
..
A,
~
Dual-In-Line Package
LSI
L _____J--t::<;-r-<101 MSB
cs,
cs,
cs,
cs,
~
-
..
2
, • , ,
~
~
~
1
~
LSI
• ,
~
~
10
~
11
~
112
~
MSB
TOP VIEW
Order Number MM4233J
or MM5233J
See Pack_II
Order Number MM5233N
See Package 18
Note: For programming information see AN-IOO.
3-53
absolute maximum ratings
Voltage at Any Pin
Power Dissipation at 25°C Ambient
Operating Temperature
MM4233
MM5233
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Vss + 0.5V to Vss - 20 V
O.BW
-:-55°C to .+125°C
O°C to +70°C
,,5°C to +150°C
300°C
electrical character.istics
Vss = +5.0V ±5%, V DD = OV, VGG = -12V ±5%, TA = -55°C to +125°C, uniess otherwise noted.
CONDITIONS
PARAMETER
Output Voltage Levels
Logical Low
Logical High
IL = 2.4 mA Sink
I L = 0.5 mA Source
Input Voltage Levels
Logical Low
Logical High
Power Supply Current
Iss
TYP
MIN
MAX
UNITS
V
V
0.4
2.4
Vss -4.0
V
V
21
30
mA
21
30
Vss -1.0
T A = 25°C
(Note 1)
IDD
mA
1.0
IGG
mA
I nput Leakage
V IN = Vss -10V
1.0
/lA
Input Capacitance
(Note 2)
f= 1 MHz, V IN = Vss
5.0
pF
Output Capacitance
(Note 2)
f = 1 MHz, V OUT = Vss
9.0
pF
Address Time
TACCESS
Select Time
TSELECT
TA = 25°C
(Note 3 and Note 4)
1000
ns
TA = 25°C
(Note 3 and Note 4)
BOO
ns
Note 1: Outputs open.
Note 2: Capacitances are measured periodically only.
Note 3: See timing diagram.
Note 4: 1.5 TTL load, CL = 20 pF.
switching time waveforms
ADDRESS INPUT
~~~5:-----------'
CHIPSElECTINPUT
---------"' ,'----:----
-------"
!--tACCESS-"
___ _
OUTPU;-------------~ E:-~'~v
3-54
,-------------
~~1.5V
OUTPUT
----------------'.
;
__ .
~
, .. __ ~.:v
PROMs/ROMs
MM4240/MM5240 2560-bit static character generator
general description
features
The MM4240/MM5240 2560-bit static character
generator is a P-channel enhancement mode
monolithic MaS integrated circuit utilizing a low
threshold voltage technology. Six character address and three row address input lines provide
access to 64-8 x 5 characters. Customer-generated
single or multiple package character fonts are easily
programmed by completing a pattern selection
form. A standard 7 x 5 raster scan font is available by
ordering the MM4240AA/MM5240AA.
•
•
•
•
•
Bipolar compatibility
High speed operation-500 ns max
±12 volt power supplies
Static operation-no clocks required
Multiple ROM logic application-chip enable
output control
• Standard fonts available-off-the-shelf delivery
applications
•
•
•
•
The MM4240/MM5240 may be used as a
512 x 5-bit read only memory for applications
other than character generation.
Character generation
Random logic synthesis
Microprogramming
Table look-up
connection diagram
Dual~1
n-Line Package
l'
ROW
ADDRESS ( L2
INPUTS
LSB
23
lo
NC
22
"
Order Number MM4240J
or MM5240J
'.
See Package 11
Order Number MM5240N
A,
"
B,
17
DATA
' 'IB'
OUTPUTS
"I
"
A,
Ao
B,
B.
6 LINE
INPUTS
See Package 18
LSB
15
CHIP
B,
ENABLE
TOP VIEW
typical application
'"
0,
B,
BO,
=___=-___
LOAD/REClflClIlATE
COln~~'_l_ _
LOADflI;EC1RCULATE
'_"J"'~Ol_ _ _ _ _ _ _~
'AGlREFRESH
MEMORY
LINE REFRESH
MEMORY
l, ,
Note: For additional information refer to AN·40.
Note: For programming information see AN-100.
3-55
absolute maximum ratings
VGG Supply Voltage
V DD Supply Voltage
Input Voltage
Storage Temperature
Operating Temperature
(Vss - 20)V
<
MM4240
MM5240
Lead Temperature (Soldering, lOsec)
electrical characteristics
PARAMETER
Output Voltage Levels
MOSto MOS
Logical "1"
Logical "0"
Vss - 30V
Vss - 15V
V 1N
(V ss +0.3)V
-65°C to +150°C
-55°C to +125°C
O°C to +70°C
300°C
<
(Note 1)
CONDITIONS
MIN
IMr2 to GND
6.8 kr2 to V GG Plus One
Standard Series 54/74 Gate
Output Current Capability
Logical "0"
V OUT = Vss - 6.0V
Input Voltage Levels
Logical "1"
Logical "0"
100
+0.4
+2.5
25
f = 1.0 MHz, V 1N =OV
f= 1.0 MHz, V 1N =OV
Address Time (Note 3)
See Timing Diagram
TA = 25°C
150
1
IlA
8
40
pF
pF
425
500
ns
4
10
d~vice
power without affecting access time.
Note 3: Address time is measured from the change of data on any input or Chip Enable line to the
output of a TTL gate. (See Timing Diagram). See curves for guaranteed limit over temperature.
Note 4: The address time in the TTL load configuration follows the
mA
IlA
5
Not. 1: These specif;catipns apply for VSS = +12V ±5%, VGG = -12V ±5%, and T A = _55°C to
+125°C (MM4240) T A = 0° C to +70° C (MM5240) unless otherwise specified.
equa,~ion;
T ACCESS = The specified limit + IN - 1) (50) ns
Where N = Number of AND connections.
The number of AND ties in the MOS load configuration can be increased at the expense of MOS "0"
3-56
40
1
V
V
25
MOS Load
TTL Load
Note 2: The V GG supply may be clocked to reduce
V
V
mA
2.5
TA = 25°C
MOS Load
Input Capacitance (Note 5)
V GG Capacitance (Note 5)
level.
V
Vss - 8.0
V 1N = Vss - 12V
Note 5: Guaranteed by design.
Vss - 9.0
Vss - 2.0
Input Leakage
Output AND Connection
(Note 4)
UNITS
V
IGG (Note 2)
T ACCESS
MAX
Vss - 1.0
MOSto TTL
Logical "1"
Logical "0"
Power Su ppl y Current
TYP
performance characteristics
Guaranteed Access Time (TAl
vs Supply Voltage
1000
800
",
600
]
~
",
'.
~ 400
t'-....
~
TA
+JO°C
~
1
Typical Access Time (TAl
Supply Voltage
1200
1000
f--
....
f--
j
TA "+25°C
ZOO
100
......
100
400
125°C
25°C
0
10
lZ
11
13
10.8
14
-VGG (V)
Temperature
60
I I
TA '" 25°C
Vss
50
50
...s
~
T~P:CAL
30
"
VOO Power Supply Current vs
Pawe.. Supply Current vs
Voltage
40
13.Z
12.0
Vss
Vss & - VGG (V)
e
e
WC
200
0
...s
YS
e
e
1""-
40
,TYPICAL
b-
30
20
ZO
10
10
=+12.0V
- - -.
Vo G
MAr
"
-12.0V
I--
0
lZ.0
10.8
-50 -25 0 25 50 15 100 125 150
13.2
TEMPERATURE lOCI
Vss & -VOG (V)
timing diagram/address time
+12V
~
EITHER
DV
E"
~
r----TACCESS~
+t2V
.,v ~
~
DV
1.SY
0
EOUf
'JV
1.SV
DV
,""
+l
V
3.0K
"V
j
INPUT ~
.JJL
DV
OMl810
E,,-!: _,
T
~
'OPf
,.I.
I
..V
I
. h OUTPUT 1M
~ MM4240/MM5240
Jl"
fOUT
10 pf
I
UK
l
:f
ANY OTL/TTl
.ATE
l'5 pF
:f
-,Iv
3-57
MM4240AA/MM5240AA character font
••••: ••••• -I··: :•••• ·1·· ..... r··· :....
..·.1.·:
:::...:I .a:...
: : I··· :.. !.:
••• ••••• .1••• I.... :
•••1
00
000000
01
000001
02
Don 010
1)3
ooaOl1
04
000100
10
001000
11
001001
12
001010
13
001011
14
001100
05
000101
06
000110
01
DOll III
...: : .:. .....:I:·::I ..e. ::i.... 1·:·11···1 rl
I: :i .:.
i
:
I I 16 :1•••
:
17
15
001101
001110
001111
:.... :e.-:i.····e•• e.
81 B283B485
010
••• ••
•• ••••
••• •••
••••
• •• •• •
• • •••• • •••••• ••e.••• •••••
••• ••• I• ••• ••• ••• •••
•• •• •• •I • I.·.:
:• I •• •• • •••
• ••• 26 • •
21
2J
24
"
"
"
•• •• •• •• •••••• •••• ••
•••• •••
•
••• ••• •• •• ••
•• • :••
•
•
•
•
•
:
•• ••• ••
•• •• •• ••••••• ••••
"
•• ••• .:• :• • ••
•• ••• : •I
I• •
••• • •
••
••••
: : ••:.- Ie :: :.:_:
•
010 noD
010001
010010
010011
010100
010101
3D
J1
32
J4
35
011 000
011001
011010
3J
011011
011100
0111[11
40
41
100000
100001
42
Ion DID
......
4J
100011
.-:-......
• • •••
••• •
•t • ••: .....
:
• •
•
50
• •
101 DOD
70
111000
3-58
45
100101
53
101011
54
lOt 100
101101
"
63
110011
64
110100
110101
71
111001
:•
•
37
011111
••
II
47
100111
.. ........:i···." ....
52
101010
...
46
100 110
....•
••
51
110001
011110
27
01D1T1
••
•• •••••
••
:: •••
••
101001
•••• •••
:•• :• :•
••• .:.
" "
•••••I I•••::
••••••• •
••• ••
110000
44
100100
0111110
55
57
1011'0
101111
"
110111
••• ••:
•••••• •••••• :• :
•••• ••.1••1.
I.••••••••
: •••••••••• I •
110010
72
••
••
••
••
••
111010
111011
II
••
••
13
65
110110
"
•
••
••••• •••• • I :
•• •••••
••
••
•••
"
111100
75
76
•
111101
111110
111111
"
PROMs/ROMs
MM4241/MM5241 3072-bit static read-only memory
general description
features
The MM4241/MM5241 30n-bit static read-only
memory is a P-channel enhancement mode monolithic MaS integrated circuit utilizing a low threshold voltage technology to achieve bipolar compatibility. TRI-STATETM outputs provide wire ORed
capability without loading common data lines or
reducing system access times. The ROM is organized in a 64 x 6 word by a-bit memory organization. Programmable Chip Enables ICE, and CE 2 )
provide logic control of mUltiple packages without
external logic. A separate output supply lead is
provided to reduce internal power dissipation in
the output stages.
•
Bipolar compatibility
•
Standard supplies
•
Bus aRable output
Static operation
No clocks requ ired
•
Multiple ROM control
Two programmable
Chip Enable lines
applications
•
Character generator
•
Random logic synthesis
•
Microprogramming
•
Table look-up
Dual-I n-Line Package
lSO
C
3.0
10 ,
Output Sink Current
VOUT
'"
+0.45V, T A" 70°C
2.0
Ic,
Output Clamp Current
VOUT "-l.OV, T A" O°C
ION
Output Source Current
VOUT
"
O.OV, TA '" +25"C
-3.0
-8.0
-3.0
-8.0
rnA
ION
Output Source Current
VOUT
'"
O.OV, TA " +70"C
-2.0
-7.0
-2.0
-7.0
rnA
'oH"-100/J.A
3.'
4.'
3.'
4.'
Vss - 2.0
VON
Output HIGH Voltage
C'N
Input Capacitance (Note 3)
(AU Input Pins)
'.-'. )
CO UT
Output Capacitance
VOUT
C,
Vo Power Supply
Capacitance
Vo" Vss
100
Power Supply Current, Voo
TA '2':C
'0
Power Supply Current, Vo
TA '" 25 C
"
Vss
I
8.0
7.0
Continuous
Operation
'OL" 0.0 mA
rnA
rnA
2.0
6.0
f" 1 MHz
Vss + 0.3
8.0
3.0
6.0
13.0
7.0
10.0
13.0
10.0
rnA
pF
7.0
10.0
7.0
10.0
pF
20.0
35.0
20.0
35.0
pF
14.0
18.0
rnA
17.0
20.0
rnA
ac characteristics
T A = O°C to +70°C for MM1101 Family, T A = _55°C to +125°C for MM4250;
Vss = +5V ±5%, Vo = Voo = -9V ±5% for MM4250, MMll01A, MMll01Al, MMll01A2;
Vss
= +5V ±5%, Vo = -10V ±5%, Voo
SYMBOL
,~
"" -7V ±5%, for MM1101, MM1101l (unless otherwise specified).
TEST
MIN
Read Cycle MMll0l, MMll01A
MMll0ll, MMll01Al
MMll01A2
MM4250
1.5
1.0
500.0
650.0
TYP
(Note 21
ns
ns
Address to Chip Select Delay
1.2 (Not. 41
0.7 (Note 41
0.2 (Note 41
0.35 (Note 41
Access Time MMll0l, MMll01A
MMll0ll, MMll01Al
MM1101A2
MM4250
Previous Read Data Valid
0.85
0.65
400.0
400.0
50.0
Note 1: All voltage measurements are referenced to ground,
Note 2: Typical values are at TA = +25°C and nominal supply voltages.
Note 3: Capacitances are measured periodically only.
Note 4: Maximum value for tac measured at minimum read cycle.
4-2
UNITS
IlS
IlS
MM1101, MMll01A,
MM11011, MMll01Al
MMll01A
MM4250
'.
MAX
1.5
1.0
500.0
650.0
Ils
IlS
J1S
IlS
IlS
IlS
ns
ns
ns
ac characteristics (con't)
WRITE CYCLE IMM1101, MMll0l1, MM1101A, MM1101Al, MMll01A2)
TEST
SYMBOL
TYP
INote 2)
MIN
MAX
UNITS
twe
Write Cycle
O.B
iJ.S
two
Address to Write Pulse Delay
0.3
iJ.S
twp
Write Pulse Width
0.4
iJ.s
tow
Data Set up Time
0.3
iJ.S
'OH
Data Hold Time
0.1
iJ.S
WRITE CYCLE IMM4250)
'wo
Write Cycle
1.0
iJ.s
'wd
Address to Write Pulse Delay
0.35
iJ.S
iJ.S
twp
Write Pulse Width
0.50
'dw
Data Set-up Time
0.35
iJ.S
'dh
Data Hold Time
0.15
iJ.s
CHIP SELECT AND DESELECT IMM1101, MMll011, MM1101A, MMll01Al, MM1101A2, MM4250)
0.4
'ew
Chip Select Pulse Width
'cs
Access Time Through Chip
Select Input
0.2
0.3
iJ.S
teo
Chip Deselect Time
0.1
0.3
iJ.S
iJ.S
Note 1: All voltage measurements are referenced to ground.
Note 2: Typical values are at T A ::= +25°C and nominal supply voltages.
Note 3: Capacitances are measured periodically only.
Note 4: Maximum value for tac measured at minimum read cycle.
typical performance characteristics
Typical Access Time vs
Typical Access Time vs
MM1101A, MM1101A1,
MM1101A2, MM4250
Voltage
Temperature
Operating Region
VDO-Jovr
t7yoo',-9V,C
MM1101A
1000
!
800
!i!
100
~..
600
;:
Q
.
MM1101Aj~
Vuo--IV
;Df>--UIV
~
~:~~~~ ~ ~
rs!-~"
.voo--g~_=t±
• Voo-1....v
400
r+~;ov
-6
..s
'"
"
-9
-10
1200
Cl =20 pF
1000
1 TTL LOAD
MM1101Ai
~
~
.
~
-t-
-30
MMll01A2,MM4250
-10
10
~C>
30
16
15
>
,
14
~
13
12
11
-l50
18
11
~
o
~
400
1--
-I-~
.....
600
200
-11
MM1101A,-:-
-
!i!
;: 800
l'
~VDD~-'V
-1
Vcc - 5.0V
"-
VDD --9V
200
TA -25"C
1400
10
-t
REGION
I
I
I
8
TEMPERATURE 1°C)
Vo (V)
TYPICAL OPERATING
- l - I REGION.l
17V1
- I - ,,"GUARANTEE
_ OPi~ATINGt: :.l
10
12
14
16
Vss- VOD (VI
ac test circuit
Test Setup for MM1101A and MM1101A Speed Measurement
'SV
+3:n
ADDRESS
INPUT
Iv~ IVD IVDD
MMll01/
MM1101A
..v
oATA
1
OUTPUT
,~
-=
C,
OUTPUT
ANY
tTL GAT.
CONDITIONS OF TEST
Input pulse amplitudes: OV to +5.0V.
Input pulse (lse and fall times:::; 10 liS.
Speed measuremelltsare referenced to the 1.SV level (unless otherwise noted);
at the OUt(:lllt of the TTL gate (t"" s; 10 ns) Cl So 20 pF.
4·3
....... 0
"'\,0
c(N
oo:t
;::E
switching time waveforms
:E:E
:E .
....... N
......
......
:E:E
C(C(
Chip Select and Deselect
Read Cvcle
00
I-----,,,---~.j
:E:E
.......
......o
...
:E
AODRESSES
ADDRESSES
.~~l
:E
...
...
.......
...
OUTPUTS
OUTPUTS
.
~
________'_':r-L
AEAO/WRITE
o
:E
:E
____________ ________
(r:r-
'-v-i(
'.---IJT-r-
---------------'
Power Switching For Reduced Power Applications
Write Cvcle
ADDRESSES
ADDR,SSES
:
--r
_____________________
---./~2:'Dns
v" ------------7.:~
Vo AND
CS LEAD
V.
',<,:;
REAOIWRITE
OUTPUTS
DATA IN
Voo :-9Vt5"
Note 1: All inputs of the MM1101 A accept standard TTL outputs with Vce = +5.0V ±5%.
Note 2: Maximum value for tAC measured at minimum read cycle.
4·4
lOOns
s:
s:
N
...o
RAMs
N
MM2102 1024-t;)it fully decodetJ static random access memory
general description
features
The MM2102 is a 1024 word by one 'bit static
random access read write memory manufactured
using N-channel enhancement mode silicon gate
technology, Static storage cells eliminate the need
for clocks and refresh. Data in and data out have
the same polarity and the read operation is
nondestructive.
• Single +5.0V supply
Low threshold silicon gate N-channel technology
allows complete DTLlTTL compatibility of all
inputs and outputs as well as a single +5V supply.
The separate chip enable input (CE) controlling
the TRI-STATE® output allows easy memory
expansion by OR-tying individual devices to a
data bus.
The simple interface and high performance make
the MM2102 ideally suited for those applications,
for large and small storage capacity, where cost is
an important design consideration.
• All inputs and
compatible
output directly DTLlTTL
• Static operation - no clocks or refreshing
required
•
Low power
150 mW typ
•
High speed
500 ns typ
• TR I-STATE output for bus interface
• Chip enable allows simple memory expansion
• On chip address decode
• All inputs protected against static discharge
•
Low cost 16-pin Epoxy B package
block and connection diagrams
Dual·1 n~Line Package
A,
A,
A.
,...!!...oVcc
A,
A,
CELL
A,
ARRAY
32 ROWS
32 COLUMNS
,..l..o GNO
1.
I ~'
15 As
~
14 Ag
.;
R/W
A,
A,
13
CE
12 DATA OUT
A,
A.
A,
R/W
COLUMN 1/0 CIRCUITS
COLUMN SelECTOR
DATA
OUT
11 DATA IN
't:'
10
A.
Ao
,"l
vee
GNU
TOP VIEW
Order Number MM2102D
See Package 3
Order Number MM2102N
See Package 15
4-5
N
...
o
N
::E
::E
absolute maximum ratings
(Note 1)
Voltage at Any Pin
-Q.SV to +7 .OV
oOe to+70oe
--6Soe to +150oe
Operating Temperature Range
Storage Temperature Range
Power Dissipation
1.OW
300°C
Lead Temperature (Soldering, 10 seconds)
dc electrical characteristics
(T A within operating temperature range, Vee = 5.0V ±5%, unless otherwise noted.)
PARAMETER
MIN
CONOITIONS
TVP
INote41
MAX
UNITS
IV 1H )
2.2
Vee
V
Logic "0" Input Voltage (V.d
-0.5
0.65
V
0.45
V
Logic "'" Input Voltage
Logic "'" Output Voltage (VoHI
Logic "0" Output Voltage
(Vod
IOH = -l00pA
2.2
V
IOL = 1.9 mA
Input Load Current (lL.d
VIN = 0 to S.25V
Output Leakage Current (I LOH)
ce· 2.2V. VOUT •
Output Leakage Current (lLod
~
Power Supply Current (I CC1 )
AU Inputs::l S.25V,
Data Out Open
4.0V
= 2.2V, VOUT = O.45V
30
10
pA
10
pA
-100
pA
60
mA
70
mA
TA = 25°C
Power Supply Current II CC2 )
All Inputs = 5.25V
Data Out Open
TA = O°C
ac electrical characteristics
(TA within operating temperature range, Vee = 5.0V ±5%, unless otherwise specified.)
See ac test circuit and switching time waveforms.
PARAMETER
CONOITIONS
MIN
TVP
(Note 4)
MAX
UNITS
READCVCLE
Read Cycle (tRC)
ns
1000
R/W::: VU-t
Access Time itA)
500
Chip Enable to Output Time
(teo)
1000
n.
500
n.
Previous Read Data Valid With
Respect to Address ItOH 1 )
50
n.
Previous Read Data Valid With
Respect to Chip, Enable (tOH 2)
0
n.
Write Cycle (twc)
1000
n.
Address to Write Set Up Time
200
n.
750
ns
Write Recovery Time (tWA)
50
n.
Data Set Up Time
800
ns
Hold Time (tOH)
100
n.
Chip Enable to Write Set Up
Time (tcwl
900
n.
WRITE CYCLE
(tAwl
Write Pulse Width (twpl
Data
(tDW I
CAPACITANCE
Input Capacitance (Allinputsl
V1N =OV,T A =2SoC,
(C'NI
f· 1.0 MHz, (Note 21
Output Capacitance (CoUT)
VOUT = av, TA .. 25°C,
3.0
pF
7.0
pF
f· 1.0 MHz, (Note 21
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The
table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Positive true logic notation is used; Logic "1"
= most
pOSitive voltage level; Logic "0" = most negative voltage level.
Note 4: Typical values are for T A = 25"e and nominal supply voltage.
4-6
typical performance characteristics
Power Supply Current vs
Temperature
C
,g
1l1li
~
00
Ie
~
10
~
It:
ii:
Ie
~
C
,g
.1l
10
30
5
20
~
10
~
-- . ..
1"""_
30
ZO
40
~
I
10 ZO 3D 40 50 60 10 80 SO 100
4.0
TA -AM8IENTTEMPERATURE ("C)
TA"OO~+
:
~ -10
~
I!:
.
..~
~
I-
e
!; -5.0
1.5
1.0
Va' - LDGIC "0" DUTPUT VDLTAGE (V)
Access Time
YS
Temperatura
100
BOD
!
100
>=
500
~
400
!II
..... '"""
600
TAo = 2S"C
Yee =4.15Y
1 TTL LOAD
IHIO
!!l
I
~
1l1li
Vee =4.'15V
2.0
Vee =4.1SV
0.5
6.0
1,000
SOD
~ 400
I
300
c
IZOO
a
1.0
5.0
I
TA = 25°C
Vee =4.75V
1 TTL LOAD
800
!
+70"C
"'
l;!
j
2
j
5.0
900
+25°C
Ie
+10°C
in
1,0l1li
C -15
!'+26"C;..r-
10
Access Time vs Load
Capacitance
Output Voltage
,g
I
1-+-
.
..
~
Vee - POWER SUPPLY VOLTAGE (V)
Output Source Currant
\IS
=O"C./'
~
Ie
I I I
J L
I
.1l
TA
I-
[,01-
RANGE
VB
15
,g
..... :.,n I
i-eGU~~D
DPERATING
Ie
..
c
TA =25"C
ALL INPUTS' 5.25V
DATA DUT OPEN
Ie
50
40
50
!
60
2
I
Supply Voltage
V~ "5.2~V
SO
I-
Output Sink Current
Output Voltage
Power Supply Current vs
5l1li
-r-
........
.......
300
200
100
3.0
80
v"" - LDGIC "I" OUTPUTYOLTAGE (V)
180
240
320
C, - LDAD CAPACITANCE (pF)
400
10 20 30 40 50 60 10 BO 8D 100
T. - AMBIENT TEMPERATURE ("C)
ac test circuit
ANY TTL GATE
MM2102
CL
~1DDPF
"DELAY TIMES MEASURED ATMM210! OUTPUT,
switching time waveforms
Write Cycle
Read Cycle
twe
V'H
V'H
ADDRESS
ADDRess
v"
V"
tow
V'H
V'H
CHIP
ENABLE
CHIP
ENABLE
V"
V"
t OH ,
t.,
VOH
~
WRITE
DATA
OUT
V'H
Va'
'ow
DATA STABLE
NOTE: ALL TIMES MEASURED WITH RESPECT
~ 20 ns.
TO 1.5V LEVEL WITH t, AND It
VA'
4-7
N
o....
;
typical application
:E
2k Word a·Bit Memory System
ADDRESS
INPUTS
I
A,
---&:-
Ao
~
A,
DI
p.o.
MM2102
CE
CE
R/W
R/W
(TTL)
DATA
INPUTS
[
~' (TTLI]O----t-t--l------H-I-t-------I
:
0,
~
~
A,
A,
MM2102
A,
CE
READ/WRITE
CONTROL
4·8
(TTL)
Jo._____..__..:R:::.'-::.t
W
MM21 02
A,
CE
R/iN
RAMs
MM4262/MM5262 2048-bit fully decoded
dynamic random access read/write memory
general description
The MM4262/MM5262 is a fully decoded 2048
word by 1 bit dynamic read/write random access
memory fabricated using National Semiconductor's
proprietary silicon gate low threshold technology.
All inputs except the clocks are TTL compatible.
The output p.rovides a current pulse allowing
a large number of devices to be bussed together
without compromising system performance due
to capacitive loading. The current pulse output
is converted to TTL levels by means of a sense
amplifier.
features
•
•
•
•
Low power
Operating
Standby
MM4262
MM5262
360 mW (max) 400 mW (max)
2.5 mW (max) 2.5 mW (max)
+5.0V, +8.5V, -15V
•
Power supplies
•
Low overhead
circuits
•
System oriented design
Bipolar compatible except for clocks
Current sense output
Chip Select for easy memory expansion
Fully decoded with internal
memory address register
•
Package
•
Device protection
22 pin DIP (Cavity and Molded)
All inputs and outputs
protected against static charge
Fast access time
MM4262
470 ns (max)
MM5262
365 ns (max)
Fast cycle time
Short Read
Read/Write
Write
565 ns (min)
750 ns (min)
750 ns (min)
475 ns (min)
635 ns (min)
635 ns (min)
•
Core memory replacement
•
Mainframe memory
•
Buffer storage
1.0 ms
2.0 ms
•
Non·volatile memory using battery back up
Refresh cycle
applications
block and connection diagrams
r----CLOCK 1.«>1 (19)
CLOCK 2,,,,,, (17)
CLOCK 3.1>:1 (18)
VOD (5)
A5
As
A1
As
(6)
(7)
(8)
(9)
Dual-In-Line Package
v" , ' - - - " " - ' - - ' "
21
6--.
¢--+
r--+
DATA IN
V~
READ!WRITE
;,
-CH-"-SE-LE-CT
(4) DATA OUT
CLOCK 1 (c"i
DATA OUT
c}--+
Voo
ClOCKJ ("3)
A,
CLOCK 2 k'zl
Vss(20)~
VBB (1)
b--+
(21) DATA IN
I
A,
)( ADDRESS
A,
A,
(COLUMN)
204B·BIT DVNAMIC
14
A,
RAM MATRIX
A;o
L ______ -
-
-
-
-
-
-
-
-
-
-
--I
)
V ADDRESS
(ROW)
A,
A,
Ao (12!
A
2
(3) R/W
A, (13)
"
12
11
A,
Order Number MM4262D
or MM5262D
See Package 5
Order Number MM5262N
See Package 17
recommended interface circuits
CLOCK DRIVERS:
MH0026
MH8808
SENSE AMPLIFIERS:
LM167
LM168
DM7806/DM8806
4·9
absolute maximum ratings
Voltage at Any Pin
Power Dissipation
Operating Temperature Range
V BB
+ 0.3V
(Note 1)
to V BB - 27V (Note 16)
1.0W
-55°C to +125°C
aOc to +70 0e
-65°C to +150°C
MM4262 (T CASE)
MM5262 (T AMBIENT)
Storage Temperature Range
300°C
Lead Temperature (Soldering, 10 seconds)
MM4262 (-55°C ~ T CASE ~ +125°C, VSS = 5.0V ±0.25V,
Vss = 3.5V ±0.5V, V OD = -15V ±1.0V, unless otherwise noted)
dc electrical cha racteristics
V BB
-
PARAMETER
CONDITIONS
Inputs
MIN
TYP
(Note 18)
MAX
UNITS
Vss + 1.0
Vss 4.2
V
V
(Notes 14, 15)
(Chip Select, Read/Write.
Addresses, Data In)
Voltage
Logical "1" (V 1H )
Vss - 1.5
Logical "0" (V 1L )
Vss - 10
Current
10
0::; VIN -:;: Vss
"A
Clock Inputs
Voltage
Logical" 1" {V !pH)
Logical "0" IV4>d
Current
V ss -l.0
Vss ... , ,0
Voo -1.0
Voo
VIN = -16V
Outputs
Current
+ 1.0
V
V
50
"A
100
6.0
"A
mA
"A
10
"A
18
rnA
150
100
"A
INote 15)
VOUT
Logical "0" (lOLl
Logical "1" (IOHI
::::
OV
V auT = 12V,
V OUT = 1.8V,
CS =
CS =
O.4V
O,4V
500
V OUT = OV, CS '" 3.5V
Leakage Current
IINote 17)
TA "" 25°C, V SB - Vss '" 3.5V, Vss '" 5.0V,
Voo = -15V, VOUT '" 1.2V, Reading l's at
T CYCLE'" 750 ns
Power Supply Current
(100)
12
Operating
Standby (No Clocks)
(lBB)
pA
ac electrica I characteristics MM4262 (All times measured from 50% points, t" tj ~ 20 ns.
see ac test circuit and timing diagram, conditions under dc electrical characteristics apply.)
MIN
TYP
(Note 18)
¢1 Clock Pulse Width (T 1 pw)
(Note 4)
115
70
¢z Clock Pulse Width (T 'lPW)
(Note 6)
275
160
PARAMETER
CONDITiONS
MAX
UNITS
ns
400
¢3 Clock Pulse Width (T3PW )
(Note 8)
110
60
¢1 Clock to ¢'l Clock Delay (T 12)
INote 5)
110
60
¢'l Clock to ¢3 Clock Delay (T 23)
(Note 7)
65
10
¢3 Clock to ¢1 Clock Delay (T31)
(Note 9)
75
40
Chip Select and Address Set
Up Time (T AS)
100
60
Chip Select and Address Hold
Time (T AH )
110
50
ns
R~ad/Write
85
30
ns
65
30
ns
95
30
ns
25
0
Read Set Up Time
(T RWS3)
Read/Write Read Hold Time
(T RWH3)
Read/Write Write Set Up Time
IT RWS1)
Read/Write Write Hold Time
(T RWD3)
Logical "1" Data In Set Up
Time (T OS1)
(Note 10)
180
60
ns
Logical "0" Data I n Set Up
Time (T OS2)
(Note 10)
75
30
ns
70
20
Data In Hold Time (T OH1)
Read Access Time (T AC C'l l
Read Access Time (T ACC1
4·10
)
T ACC1 = T AS
+ T1'l + T ACC'l
ns
150
260
ns
300
470
ns
ac electrical characteristics (con't)
PARAMETER
MM4262
CONDITIONS
Read Only Cycle (TSHORT IREAD)
(Note 111
Read, Write, Read Modify Write
Cycle (T CYCLE)
Refresh Time
(Note 12)
Output Hold Time (To H)
(Note 13)
Chip Select, Address, ReadIWrite,
Data In, Data Out Capacitance (ex)
rPl Clock Capacitance (C 1 1
¢2
Clock Capacitance (C 2 )
4>3
Clock Capacitance (C 3 1
Clock Rise/Fall Time
r"
MIN
TYP
INot.,8)
MAX
ns
750
ns
1.0
ms
7.0
pF
ns
1000
~""
~,,~ '"~, ~. ~ ',",
V TEST
:=
UNITS
565
5.0 Vae WIth
RMSat
f= 1 MHz
~15mV
Input Rise/Fall Time
50
pF
25
pF
25
pF
100
ns
50
ns
dc electrical characteristics
V BB
-
MM5262 o°c::; TA ::; +70°C, Vss = 5.0V ±0.25V,
Vss = 3.5V ±0.5V, Voo = -15V ±1.0V, unless otherwise noteO.
PARAMETER
CONDITIONS
Inputs
MIN
TYP
INot.18)
MAX
UNITS
Vss+l.0
V
V
(Notes 14 and 15)
(Chip Select, Read/Write,
Addresses, Data In)
Voltage
Logical "1" (V 1H )
Logical "0" (V 1L )
Vss -1.5
Vss -10
OV ~ VIN
Current
:s
Vss - 4.2
1.0
Vss
MA
Clock Inputs
Voltage
Logical "1" (V !pH)
Vss - 1.0
Logical "0" (V ¢Ll
V DD -1.0
Vss + 1.0
V DD + 1.0
VIN oo-16V
Current
V
V
50
MA
100
6.0
MA
mA
MA
10
pA
20
150
100
rnA
(Note 15)
Output
Current
Logical "0" (lOLl
Logical "1" (I OH )
Leakage Current
V OUT
= OV
VOUT
'"
V OUT
= 1.8V,
VOUT
= av,
1.2V,
es ~ OAV
es " OAV
CS
600
= 3.5V
IINot. 17)
TA '" 25°C, Vas - Vss '" 3.5V, Vss '" S.OV,
Voo "" -15V, VOUT '" 1.2V, Reading l's at
T CYCLE"" 635 ns
Power Supply Current
13
1100)
Operating
Standby (No Clocks)
II BB )
MA
MA
ac electrical characteristics MM5262 (All times measured from 50% points, t" tf ::; 20 ns,
see ac test circuit and timing Oiagram, conditions under dc electrical characteristics apply.)
PARAMETER
CONDITIONS
MIN
TYP
INot.131
MAX
UNITS
¢, Clock Pulse Width (T 1PW)
(Note 4)
95
70
¢2
Clock Pulse Width (T 2PW)
INote 6)
240
160
¢3
Clock Pulse Width (T 3PW)
(Note 8)
100
60
ns
¢,
Clock to
(Note 5)
90
60
ns
¢2
Clock Delay (T 12)
ns
400
ns
q,2 Clock to q,3 Clock Delay
(T 23)
INote 7)
50
10
ns
2
Clock Capac'itance (C 2 )
1>3
Clock Capacitance (C 3 )
f"
1.0 MHz
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The
table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Positive true logic notation is used: Logic "1" = most positive voltage level
Logic "0" = most negative voltage level
Note 4: T 1 PW. 4>1 clock - used to change input logic address and chip select.
Note 5: T 12. interval between clock 1 and 2 - for decode.
Note 6: T2PW. ¢2 clock - cell access.
Note 7: T23. interval between clock 2 and 3 - decision time.
Note 8: T3PW. 4>3 clock - write or refresh clock.
Note 9: T31. write recovery time.
Note 10: If a "1" is being written then data in must go high TDSl before the end of 4>2 and remain in that state until TDHl
after 4>3 goes low. If a "0" is being written. data in must go low at least TOS2 before ¢3. and remain in that state until TOHl
after ¢3 goes low.
Note 11: For a short read cycle, ¢3 may be inhibited and the next cycle may begin T23 after ¢2.
Note 12: Addresses AO through A4 are the row addresses. To accomplish a refresh, at least one location in each row must be
accessed during any 2 ms period for the MM5262 and 1 ms for the MM4262. The row will refresh when reading or writing with
the chip disabled or enabled as long as 4>3 is applied.
Note 13: During a read cycle the output will remain valid until the next 1'1 or TOH whichever is less. During a read modify
write or write cycle the output will remain valid until -.....
r--------4J~-OUTPUT
--OUTPUT
t an
3;;3Dns} C =200 F
m;
L
P,
t"fl~40
5-1
(,)
......
o
o
absolute maximum ratings
o
J:
8.0V
--40V
+28V
30V
5.5V
800mW
±500mA
-65°C to +150°C
-55°C to +125°C
OoC to +85°C
300°C
Vee Supply Voltage
V- Supply Voltage
V+ Supply Voltage
(V+ - V-I Voltage Differential
Input Voltage
Power Dissipation (T A = 25°C)
Peak Output Current
Storage Temperature Range
Operating Temperature Range MH0007
MH0007C
Lead Temperature (Soldering, 10 seconds)
:?!
r::o
o
o
J:
:?!
electrical characteristics
(Note 1)
PARAMETER
MIN
CONDITIONS
Logical "1" Input Voltage
Vee = 4.5V
Logical "0" Input Voltage
Vee = 4.5V
Logical "1" Input Current
Vee = 5.5V, VIN = 5.5V
Logical "0" Input Current
Vee = 5.5V, VIN = 0.4V
Logical "1" Output Voltage
Vee = 5.5V, lOUT = 30 mA, VIN = 0.8V
V+ - 4.0
Vee = 5.5V. lOUT = 1 mA, VIN = 0.8V
V+ - 2.0
TYP
(Note 2)
2.2
UNITS
V
0.8
100
1.0
1.5
V
IlA
mA
V
V
V- + 2.0
Logical "0" Output Voltage
Vee = 4.5V, lOUT = 30 mA, VIN = 2.2V
Transition Ti me to
Logical "0" Output
CL = 200 pF (Note 3)
50
ns
Transition Time to
Logical" 1" Output
C L = 200 pF (Note 3)
75
ns
Note 1: Minimax limits apply across the guaranteed range of -5SoC to +12SoC for the MHoo07, and from
the MH0007e, for all allowable values of V-and V.
Noto 2:' All typical values measured at TA = 25°e with Vee
Note 3: Transition time measured from time VIN
= 5.0V, V-= -25V. V = OV.
= 50% value
until VOUT has reduced 80% of final value.
Allowable Values fot V- and V+
Maximum Power Dissipation
"
VOLTS
1.2
~
0.8
'"
~
0.6
i'"
0.4
c;
I
1.0
a;
;::
c.L
C~SE
i'
AM~IENT
'"
T- I"- r-... i""-
0.2
I
0
0
25
50
75
..........
100
TEMPERATURE ("C)
125
'''''rr
"
OPERATING
REGION
150
."
.3D
·40
5·2
MAX
V
aOc to +8SoC for
3:
::t
o
Clock Drivers
o
o
CD
.......
3:
::t
o
o
MH0009/MH0009C dc coupled two phase MOS clock driver
o
CD
(")
general description
features
The MH0009/MH0009C is high speed, DC coupled,
dual MOS clock driver designed to operate in
conjunction with high speed line drivers such as
the DM8830, DM7440, or DM7093. The transition
from TTL/DTL to MOS logic level is accomplished
by PNP input transistors which also assure accurate
control of the output pulse width.
•
DC logically controlled operation
•
Output Swings - to 30V
•
Output Currents - in excess of ±500 nA
•
High rep rate - in excess of 2 MHz
•
Low standby power
schematic and connection diagrams
Metal Can Package
2
INPUT B 6
---1>--.....-[i
'---I4f-+-10
¢>2BIAS 1
¢~
TOPVIEW
OUTPUT
Order Number MH0009G
orMH0009CG
8
'"u
300
100
200
300
400
z
~
FOR TYPICAL APPLICATION
r-
eiN '"
4300 pF
-55 -35 -15 5
~ 1000
,
ll~ P
25 45 65 85 105125
100
200
300
400
PU LSE WI DTH (ns)
AMBIENT TEMPERATURE rCI
AVERAGE POWER (mW)
-,t.
/' /
, / /'
RIN '" 4H1
K / T ,./ ..,,h ~ ~ , / '-;.g1n
r-
et '" 1000pF
on y
R,"' 20n,--j
~ 2000
5....
"
RtN '" 10D:
u
Illy
~
R1N
~3000
1000 pF ----.....
...I-t:1-I- ~
r- OM7830/BBJO DRIVER ~
400
~
'IV'
"
DM8830 DRIVER
Vee = 5V
TEST CIRCUIT (FIG. 81
CIN " 2200 pF
w
M~
FIGURE 6. R'N vs C,N vs Pulse Width
FIGURE 7. Package Power Derating
1.5
~
1.0
'"
~
'"""-
pulse width
.5
25
50
Maximum output pulse width is a function of the
input driver characteristics and the coupling
capacitance and resistance. After being turned on,
the input current must fall from its initial value
'I N peak to below the input threshold current
II N min '" VB E /R 1 for the clock driver to turn
off. For example, referring to the test circuit of
Figure 8, the output pulse width, 50% to 50%, is
given by
['-"
15
f'...
100
125
150 115
AMBIENT TEMPERATURE rCI
circuit operation
Input current forced into the base of 01 through
the coupl ing capacitor C I N causes 01 to be driven
into saturation, swinging the output to
V- + VcE(SAT) + VOIOOE'
When the input current has decayed, or has been
switched, such that 01 turns off, 02 receives base
drive through R2, turning 02 on. This supplies
current to the load and the output swings positive
to V+ - VSE.
It may be noted that 01 always switches off
before 02 begins to supply current; hence, high
internal transient currents from V+ to V- cannot
occur.
liN peak
+ ROC IN In - - - '=' 400 ns.
'iN min
For operation with the input pulse shorter than
the above maximum pulse width, the output pulse
width will be directly determined by the input
pulse width.
Typical maximum pulse width for various C I Nand
RIN values are given in Figure 6.
timing diagram
ac test circuit
A.ln"ulpulsewHith
_> olact pulse
V'N
~
5V
w
8.tnputPUI"W1dt~.ft",I\~90%
=t~aek pulse ~::-
Clock "ul..
outpllt
V1N
=
0 to 5.0V pulse, f" 500 kHz, DC
~
50%, tr and t,
-s: 10
11S.
t" ON
10~QN
---1,.,.-----'-",tr'-'-H----
"JoOV
511%
-PW
PC-=H-----
Vl "-16V
Figure 8
5·9
(,)
M
....
o
o
fan-out calculation
J:
~
The drive capability of the MH0013 is a function
of system requirements, i.e., speed, ambient tem·
perature, voltage swing, drive circuitry, and stray
wiring capacity .
........
M
....
o
o
The followi ng equations cover the necessary calcu·
lations to enable the fan·out to be calculated for
any system condition. Some typical fan·outs for
conditions are given in Table 1.
J:
~
maintained for the full duration of the pulse
width .
4. Package Power Dissipation
Total Average Power
Internal
Power
Transient Current
The maximum peak output current of the MH0013
is given as 600 mAo Average transient current reo
quired from the driver can be calculated from:
C L (V+ - V-)
I =
TR
(1)
This can give a maximum limit to the load.
Figure
1 shows
maximum voltage swing and
capacitive load for various rise times.
1. Transient Output Power
The average transient power (PAC) dissipated is
equal to the energy needed to charge and discharge
the output capacitive load (C L ) multiplied by the
frequency of operation (F).
PAC = C L X (V+ - V-)2 X F
(2)
Figures 2 and 3 show transient power for two dif·
ferent values of (V+ - V-) versus output load and
frequency.
2. In ternal Power
"0" State
Negligible «3 mW)
"I" State
P'NT =
(V+ - V-)2
R2
x Duty Cycle.
(3)
Figure 4 gives various values of internal power
versus au ptut voltage and duty cycle.
3. Input Power
The average input power is a function of the input
current and duty cycle. Due to input voltage
clamping, this power contribution is small and can
therefore be neglected. At maximum duty cycle of
50%, at 25° C, the average input power is less than
10 mW per phase for R'NC'N controlled pulse
widths. For pulse widths much shorter than
R'NC'N, and maximum duty cycle of 50%, input
power could be as high as 30 mW, since I'N peak is
5·10
= Transient
Typical
Example
Calculation
Output Power +
Power + Input
for
One Half
MHOOl3C
How many MM506 shift registers can be driven by
an MH0013C driver at 1 MHz using a clock pulse
width of 400 ns, rise time 30-50 ns and 16 volts
amplitude over the temperature range 0-70°C7
Power Dissipation
From the graph of power dissi pation versus tem·
perature, Figure 7, it can be seen that an
MH0013C at 70°C can dissipate lW without a heat
sink; therefore, each half can dissipate 500 mW.
Transient Peak Current Limitation
From Figure 1 (equation 1), it can be seen that
at 16V and 30 ns, the maximum load that can be
driven is limited to 1140 pF.
Average I nternal Power
Figure 4 (equation 3) gives an average power of
102 mW at 16V 40% duty cycle.
Input power will be a maximum of 8 mW.
Transient Output Power
For one half of the MH0013C
500 mW = 102 mW + 8 mW
+ transient output power
390 mW = transient output power
Using Figure 2 (equation 2) at 16V, 1 MHz and
390 mW, each half of the MH0013C can drive a
1520 pF load. This is, however, in excess of the
load derived from the transient current limitation
(Figure 1, equation 1). and so a maximum load
of 1140 pF would prevail.
From the data sheet for the MM506, the average
clock pulse load is 80 pF. Therefore the number
.
. 1140
·
a f d eVlces driven IS
or 14 registers.
-so
For nonsymmetrical clock widths, drive capability
is improved.
s:
::t
o
Clock Drivers
o
N
(JI
"-
s:
::t
MH0025/MH0025C two phase MOS clock driver
o
o
N
(JI
(")
general description
features
The MH0025/MH0025C is monolithic, low cost,
two phase MOS clock driver that is designed to be
driven by TTLlDTL line drivers or buffers such as
the DM932, DMBB30, or DM7440. Two input
coupling capacitors are used to perform the level
shift from TTLlDTL to MOS logic levels. Optimum
performance in turn·off delay and fall time are
obtained when the output pulse is logically con·
trolled by the input. However, output pulse widths
may be set by selection of the input capacitors
eliminating the need for tight input pulse control.
• B-Iead TO-5 or B·lead dual·in·line package
• High Output Voltage Swings-up to 30V
• High Output Current Drive Capability-up to
1.5A
• Rep. Rate: 1.0 MHz into> 1000 pF
• Driven by DM932, DMB830, DM7440(SN74401
• "Zero" Quiescent Power
connection diagrams
Dual-In-Line Package
Metal Can Package
8 N.C.
INPUT A 2 - - 1 t - - t : > C - - + - 1 OUTPUT A
v~
y'
, v'
3
INPUTB 4 - - 1 t - - t : > C - - + - 5 OUTPUT8
Note; Pin 4 connected to case.
TOP VIEW
Order Number MH0025H
orMH0025CH
Order Number MH0025CN
See Package 12
See Package 23
typical application
~T~'
I
y~
I
I IN
I
L __ :.. ~D~83~R,!M7~ J<,)' CIN
ac test circuit
timing diagram
-
A.,np.tpuISllWldlh~IN5V
11._t-'-'
I'RR~II.!iMHz
v,,-s.ov
1,-I,SU'nl
""IMWldt1i:
A.l.Gl'i
J
B'lnpUlpulsewidlh~'"
WIdth
sa\sclockpulse
1.2.0011$
.
>clockpul.
~!~:~:Ulsa
10%
,;:DN
~
Yo.
_ _ _ __
,tJ"...O-"---- II 'OV
J
IIOUT
*Q1 is a selected high speed NPN switching transistor.
F:::........:::;~-+----V2·-1&V
5·11
(.)
Ln
N
o
o
absolute maximum ratings
(v+ - V-I Voltage Differential
Input Current
Peak Output Current
Power Dissipation
Storage Temperature
Operating Temperature MH0025
MH0025C
Lead Temperature (Soldering, 10 sec)
:t:
~
.........
Ln
N
o
o
:t:
~
30V
100 mA
1.5A
See Curves
-65°C to +150°C
-55°C to +125°C
O°C to +85°e
300 0 e
electrical characteristics
(Note 1) See test circuit.
MAX
UNITS
15
30
ns
e'N ~ .001 pF
25
50
ns
R'N ~ OQ
30
60
ns
PARAMETER
CONDITIONS
TYP
MIN
T dON
T rise
TdoFF INote 2)
>-
eL
T la " INote 2)
~
.001 pF
T la " INote 3)
P.W. 150% to 50%) INote 3)
-'
Positive Output Voltage Swing
V ,N
~
OV, lOUT
~
-1 mA
60
90
120
ns
100
150
250
ns
V+ - 1.0
500
ns
V+ - 0.7V
V
Note 1. MiniMax limits apply across the guaranteed operating temperature range of _55°C
for MH0025 and
aOc to 85°C for
V- + 1.5V
V- + 0.7V
Negative Output Voltage Swing liN ~ 10 mA, IOUT~ 1 mA
to
V
+125°C
MH0025C. Typical values are for +25°C.
Note 2. Parameter values apoly for clock pulse width determined by input pulse width.
Note 3. Parameter values apply for input pulse width greater than output dock pulse width.
performance characteristics
Package Power Derating
Transient Power vs Rep. Rate
400
~
~
>=
;:;
1.2
gj
1.0
'"
0.8
c
~
II
"x
""
cl
-- - MH0025H &MH0025CH STilL AIR
1.4 -
MH0025CN SOLDERED INTO PC
BOARD WITH 8 GlI CONDUCTORS
2 OZ, .03 IN. WIOE
~
I
I'\.
f-
I', :'\
0.6
"-
0.2
0
-25
0
50
15
75
300
"
~...
"
200
~
100
/ /
100 125 150
Cl
V
II / /
/'
II J /
rl- '/ / '
~
>= 100
0
.5
1.0
"
60
c
Cl =J50PF
f.d::'"
1.5
80
~
40
Q
20
/
/
1 1
21/>1;
3200
~
~- 2400
~ 2000
~ 1600
(5: 1200
Q
~
800
400
0
K
1\
\\
.\
k'
MHDD25C; V
0
10
""-
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
(PMAX )
CL '"
5·12
FREQUENCY {MHl)
(1k) - (v~ - V-)2 (DC)
fl pk ) ft,)
(f) (1 k) (V+ _ V-)2
900
::;: V+ _ V-
"
50
(v+ - v-r2 iDC)
INPUT PULSES
w
65.RoC,~ln~
I.. , ..
OUTPl/T PULSE wtOTH
=
INPUTPUtSE WIDTH
I-
OJ932
500
&RIV~A ~~l...rDRIVER
I>-
~
I-::::r;.-t"
~
300
100
rr-
I-
V
700
§;
"
60
--1k--
PLUg90n •.
]:
Q
I'...: "-
40
Dl/TPUTPUlS[WIDTHVS,C, .. FORlONG
FOR tNPUTPUlSE'
...'"
"- "'-
30
Output P .W. Controlled by C,N
1100
20V.T.,25C
'- .....
..... r--.
r:~~:~:~~:::: ~~~\:: ;;o~ """
'\~,
20
PDe
1
-,
/v·-)~ldv-
DUTY CYCLE (%)
MH0025!:N; V'_V =20V,lA,1,C
2800
/'
PULSE REPETITION RATE (MHz)
Maximum Load Capacitance
~
/
~
PAC" {v+ - V-)2f CL
D,C
/
///
u
2.0
V 1.9
%
/
/
;:;
gj
X
<. 1~-~6V
/
it
.§ 120
h~ / ' ~ ~ ~L-lDOpF
V'"-v-= 16V
~ ~P'
TEMPERATURE (C)
If' -V-~20V/
140
"J5O PF
4;?-
/
~
'~
0.4
.§
DC Power (POC) vs Duty Cycle
160
Cl o l1500plF ;L-1000 pF
201l0pF
sonpt/Ll UP
~--200
I
600
1000 1400
elN
IMAX
~
1800
2200
(pF)
Peak current delivered by driver
1M IN :::: (VsE !Rl) =- (O.6!lk)
70 85
~
J:
o
applications information
o
N
Circuit Operation
Input current forced into the base of 01 through the
coupling capacitor C'N causes 0 1 to be driven into
saturation, swinging the output to V- + VCE(sat) +
VOiode'
When the input current has decayed, or has been
switched, such that 0 1 turns off, O 2 receives base
drive through R2 , turning O 2 on. This supplies
current to the load and the output· swings positive
to V+ - V BE .
It may be noted that 0 1 must switch off before
O2 begins to supply current, hence high internal
transients currents form V- to V+ cannot occur.
~...
'"
1
'T'
I
"
INPUT
"
25"
"
fi
01
FIGURE 1. MH0025 Schematic (One·Half Circuit)
The following equations cover the necessary cal-
~
J:
Transient Current
o
o
The maximum peak output current of the MH0025
is given as 1.5A. Average transient current required
from the driver can be calculated from:
N
U'1
(")
(1)
Typical rise times into 1000 pF load is 25 ns
For V+ - V- ~ 20V, I ~ O.SA.
Transient Output Power
The average transient power (Pac) dissipated, is
equal to the energy needed to charge and discharge
the output capacitive load (Cd multiplied by the
frequency of operation (t).
PAC ~ C L
X
(V+ -
v-)2 X
f
(2)
For V+ - V-~ 20V, f ~ 1.0 MHz, C L ~ 1000 pF,
PAC ~ 400 mW.
Internal Power
"0" State
Negligible «3 mW)
"1" State
(3)
Fan-Out Calculation
The drive capability of the MH0025 is a function
of system requirements, i.e. speed, ambient temperature, voltage swing, drive circuitry, and stray
wiring capacity.
U'1
.......
culations to enable the fan-out to be calculated
for any system condition.
~
SO mW for V+ - V- ~ 20V, DC ~ 20%
Package Power Dissipation
Total average power
internal power
~
transient output power +
example calculation
How many MM506 shift registers can be driven by
an MH0025CN driver at 1 MHz using a clock pulse
width of 200 ns, rise time 30-50 ns and 16V amplitude over the temperature range 0-70°C?
Power Dissipation:
At 70°C the MH0025CN can dissipate 630 mW
when soldered into printed circuit board.
Transient Peak Current Limitation:
F rom equation (1), it can be seen that at 16V and
30 ns, the maximum load that can be driven is
limited to 2S00 pF.
Average Internal Power:
Equation (3), gives an average power of 50 mW at
16V and a 20% duty cycle.
For one half of the MH0025C, 630 mW
dissipated.
-i-
2 can be
315 mW
~
50 mW + transient output power
265 mW
~
transient output power
Using equation (2) at 16V, 1 MHz and 250 mW,
each half of the MH0025CN can drive a 975 pF
load. This is, less than the load imposed by the
transient current limitation of equation (1) and
so a maximum load of 975 pF would prevail.
From the data sheet for the MM506, the average
clock pulse load is SO pF. Therefore the number
975
of devices driven is 80 or 12 registers.
5·13
(J
CD
N
Clock Drivers
o
o
J:
:E
"CDN
MH0026/MH0026C 5 MHz two phase MOS clock driver
o
o
general description
J:
The MH0026/MH0026C is a low cost monolithic
high speed two phase MOS clock driver and interface circuit. Unique circuit design along with
advanced processing provide both very high speed
operation and the ability to drive large capacitive
loads. The device accepts standard TTLlDTL outputs and converts them to MOS logic levels. It may
be driven from standard 54/74 series gates and
flip-flops or from drivers such as the DM8830 or
DM7440. The MH0026 is intended for applications
in which the output pulse width is logically controlled: i.e., the output pulse width is equal to the
input pulse width.
:E
•
•
High rep rate-5 to 10 MHz depending on load
Low power consumption in MOS "0" state-
•
Drives to 0.4 V of G N 0 for RAM address drive
2 mW
features
The MH0026 is intended to fulfill a wide variety of
MOS interface requirements. As a MaS clock driver
for long silicon gate shift registers, a single device
can drive over 10k bits at 5 MHz. Six devices provide input address and precharge drive for a 8k by
16 bit MM1103 RAM memory system. Information
on the correct usage of the MH0026 in these as well
as other systems is included in the Application
Section. A thorough understanding of its usage
will insure optimum performance of the device.
•
•
•
•
The device is available in 8-lead TO-5, one watt
copper lead frame 8-pin mini-DIP, and one and a
half watt TO-8 packages.
Fast rise and fall times-20 ns with 1000 pF load
High output swing-20V
High output current drive-±1.5 amps
TTLlDTL compatible inputs
connection diagrams
Metal Can Package
,-
Dual-I n-Line Package
"'6""
INPUT A 2
Order Number MH0026H
or MH0026CH
See Package 23
Flat Packa_ge
7 OUTPUT A
V-
J
6 V'
II'IPUTB
4
50UTPUTB
Order Number MH0026J
or MH0026CJ
See Package 9
schematic diagram
11/2 of Circuit Shown)
EXTERNAL
0-1'"~."o-,-.-""",-1
5-14
Metal Can Package
"
Order Number MH0026G
or MH0026CG
See Package 25
Order Number MH0026F
or MH0026CF
See Package 25A
absolute maximum ratings
V+ -V- Differential Voltage
Input Current
Input Voltage (V IN - V-I
Peak Output Current
Power Dissipation
Operating Temperature Range
3:
o
o
:I:
(Notes 1 & 2)
MH0026
MH0026C
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
N
22V
100mA
5.5V
1.5A
See curves
-55°C to +125°C
O°C to 85°C
-65°C to +150°C
300°C
en
"-
3:
o
o
:I:
N
en
("')
dc electrical characteristics
~-----,-------,--------~ UNITS
V
rnA
V
J1A
V
V
V
V
rnA
J1A
ac electrical characteristics
(Notes 1 & 2, AC test circuit)
Turn·On Delay (tON)
5.0
Turn·Off Delay (tOFF)
5.0
Rise time (t,) - Note 3
Falltirne (t,) - Note 3
7.5
12
12
ns
15
ns
ns
V+ - V- = 17V, C L = 250 pF
12
V+ - V- = 17V, CL = 500 pF
15
18
ns
C L = 1000 pF
20
35
ns
V+ -V-= 17V,C L =250pF
10
V+ -V-= 17V,C L =500pF
12
16
ns
CL = 1000 pF
17
25
ns
ns
Note 1: These specifications apply for if" - V- "" 1OV to 20V, CL "" 1000 pF, over the temperature range -550 C to + 1250 C
for the MH0026 and O°C to +85°C for the MH0026C.
Note 2: All typical values for the T A
:=
25°C.
Note 3: Rise and fall times are given for MOS logic levels; i.e., rise time is transition from logic "0" to logic "1" which
is voltage fall. See waveforms.
5·15
u
W
N
typical performance characteristics
o
o
J:
~
TO·5 & DIP Power Ratings
......
W
N
o
o
~
~
illQ
J:
3.0
1.2
1.0
:s
~
~
~
:r
0.8
DC Power (POC) vo
Duty Cycle
TO-S Package Power Rating
I--
r-
~
MHOll26H' AND MH'OO26CH
"
INSTILL AtR WnH CLIP
~ONHEATSIN~
..........
0.4
r-.....
MHO!l26H 8. MHOO26CH
IN STILL AIR
2.0
illQ
1.5
~
0.2
25
50
~
~
")'
75
100
125
-
2.5
'">=
0
::
0.6
400
MH0026G AND MH0026CG IN
MH0026CN SOLDERED TO PC
~o,"" WIT"' CU. C",OUCTORS
_20Z,.03IN,WIQE
_
-
360
~~I!~ ~~RK~~THHEg~:'~lNOY
-
320
TYPE 215-1.9 OR EQUIV.I
"
i'..
E
~
~
'"
t ,>~
1.0
150
25
AMBIENT TEMPERATURE eel
50
75
100
0
'"
160
120
/.
V.
~
10
lY
V
IV· _ V-I'
PDc"'~(DC)
",
150
'/
'/
X /'
/
./
200
40
125
'/
./
~: =~::::~'>
240
80
MH0026G AND
MHOrOCG
STll( AIR
0.5
25~C
Cl
V· -V-'20V_
280
"i',. /
.........
TA =
20
30
40
50
60
70
80
DUTY CYCLE (%)
AM81ENT TEMPERATURE e"C)
Transient Power (PAC) vs
Supply Current vs Temperature
Frequency
900
800
"
E
~
~
'"
iii
400
~
I
600
500
>-
300
200
100
/
U,
I::
"
0-
500pF
i
I I
--
V-
C,
>
200p~_
H"J
~
I I
1.0
2.0
8.0
CL
7.5
7.0
6.5
6.0
3.0
4,0
5.0
0
'"
14
1
-
E
Y1
/
J
'"
TA=25'C
DUTY CYCLE'" 20%
f= 1 MHz
/
I I
CL
I
17V
Input Current vs Input Voltage
16
8.5
Vc, ' 1000 pF
1
700
:r
A v+ _v-",
CL =2000pF
~
v+ -v- '" 20V
"
E
0-
~
V- =OV
10
~
V
i
-,..;
0
25
50
0.5
75 100 125
TEMPERATURE rCI
Rise Time vs load Capacitance
Fall Time vs load Capacitance
>:
>=
V· -V-'20V
15
~
a;
10
~V
~V v+ -V-"'17V
>=
~
........
15
1/ V
:;:
."
5
400
600
800
1000 1200
o
200
Turn-On & Turn-Off Time
vs Temperature
~
>:
>=
11
0
"
."
~
~
>0
"
~
~
10
-~'-~-'2~4
/"
.,,/
i'
'0'
1'\. V
l/ r<--
./'
I
-75 -50 -25
0
25
50
--
75 100 125
TEMPERATURE ( C)
5-16
20
!
>:
~
>-
600
15
I
CL
800
500
~
400
w
/
300
,;'
!; 200
0
I-'"
100
1000
200
a;
10
'"
f- Vj-V;'20V
20
g
w
">=
I
~
0
L
c,~
15
c,~~
10
I
I
'"
0
I
I
0
25
50
75
TEMPERATURE ( C)
1000 1200
100 125
/'
- ----
/"
I
CL
-75 -50 -25
800
Fall Time vs Temperature
1000 pF
'"
600
25
V+-V-=2DV
L
CL
400
INPUT CAPACITANCE, CIN (pF)
c,n?F-
>=
............
tOFF
400
600
1:
Rise Time vs Temperature
25
I
CIN = CL '" 1000 pF
12 "-- Ro = 50S"'!
13
2.5
V+ -V-"'20V
CL '" 1000 pF
TA '" 25°C
700
LOAD CAPACITANCE IpFI
lOAD CAPACITANCE (pF)
14
Ro '" 50u
TA '" 25°C
1/
'"
:;
~
V-
10
R~' 150,1,
TA=25°C
~
200
:!
20
!
>:
2.0
800
V+-V-=15Vto20V
...-:;..-r-
1.5
Optimum Input Capacitance vs
Output Pulse Width
25
20
1.0
INPUT VOLTAGE (V)
FREOUENCY (MHz)
!
1/
~
v+ -v- '" 17V
-75 -50 -25
25
V+ '" 20V
12
-75 -50 -25
0
25
50.t 75 100 125
TEMPERATURE CCI
3:
o
:r:
typical applications
o
N
0)
.......
3:
DC Coupled RAM Memory Address or Precharge
Driver (Positive Supply Onlyl
AC Coupled MOS Clock Driver
:r:
o
o
N
','
0)
~Pf
j'"' ' '
n
j'''.'''~
tilES 0111
MMlIDlTYPE
MEMOAYSYSTEM
eLueNTO
SHfFTAEGISTERS
Transistor Coupled MOS Clock Driver
DC Coupled MOS Clock Driver
TTLIIPUTS
{~=::;:=;--tl
.
INPUT
}""'"
.
REGISTERS
INPUT
Logically Controlled AC Coupled Clock Driver
TTLCLOCK
INPUT
"0
JL
......,....._..!!.!
TOADDLTlOIiAL
} SIIIFTRE&ISTEIIS
V'
'O---l
..
~
CLOCKINPUT-2fo
DIE SIIOT DUTf'UT-ADJPULSEWIPTH
PHASE ONE OUTPUT
PHASETWOOIiTPUT
5·17
(,)
co
S
typical applications (con't)
oJ:
:!:
.......
Precharge Driver for MOS RAM Memories
CO
N
o
o
J:
:!:
,"o"'''~~~~~
f-o--+ __-+___= ..... 0-
---o00HTRO~
SHEeT
OHOHOo---LJ----------'"...-----------------------!
ac test circuit
switching time waveforms
100pF
V,,,,=5V
PRF.1MH>
pw.
o.s~.
t,.~lt';;10
n.
application information
1.0 Introduction
The MH0026 is capable of delivering 30 watts
peak power (1.5 amps at 20V needed to rapidly
charge large capacitative loads) while its package is
limited to the watt range. This section describes
the operation of the circuit and how to obtain
optimum system performance. If additional design
information is required, please contact your local
National field application engineer.
configuration in Figure 1. The AC coupling of an
input pulse allows the device to work over a wide
,..--.....-ov·
'2
!l2
EXTERNAL
C1
lNo-J~
...14.....-o 0U1
D2
2.0 Theory of Operation
......................-ov·
Conventional MOS clock drivers like the MH0013
and simi lar devices have relied on the circuit
5·18
FIGURE 1.
Conventional MOS Clock Drive
3:
:E:
o
o
application information (con't)
range of supplies while the output pulse width
may be controlled by the time constant - R, X C,.
O 2 provides 0.7V of dead-zone thus preventing 0,
and O2 from conducting at the same time. In
order to drive large capacitive loads, 0, and O2
are large geometry devices but COb now limits
useful output rise time. A high voltage TTL output
stage (Figure 2) could be used; however, during
switching until the stored charge is removed from
0, , both output devices conduct at the same time.
This is familiar in TTL with supply line glitches in
the order of 60 to 100 mAo A clock driver built
this way would introduce 1.5 amp spikes into the
supply lines.
.---+-ov·
ct
EXTERNAL
OUT
INo1~
N
When the output of the TTL input element (not
shown) goes to the logic "1" state, current is
supplied through C IN to the base of Ot and O 2
turning them ON, and 0 3 and 0 4 OF F when the
input voltages reaches O,7V. Initial discharge of
the load as well as E-B protection for 0 3 and 0.
are provided by 0, and O2 , When the input
voltage reaches about 1.5V, 06 and 0 7 begin to
conduct and the load is rapidly discharged by 0 7 ,
As the input goes low, the input side of C, N goes
negative with respect to V- causing 0 8 and 0 9 to
conduct momentarily to assure rapid turn-off of
O2 and 0 7 respectively. When 0, and O2 turn
OF F, Darl ington connected 0 3 and 0. rapidly
charge the load toward V+ volts. R6 assures that
the output will reach to within one VB E of the
V+ supply .
Q)
.......
3:
:E:
o
o
N
Q)
.n
The real secret of the device's performance is
proper selection of transistor geometries and resistor values so that 0 4 and 0 7 do not conduct at
the same time while minimizing delay from input
to output.
Ot
3.0 Power Dissipation Considerations
L...~--"'-4.-o v-
FIGURE 2. Alternate MOS Clock Drive
Unique circuit design and advanced semiconductor
processing overcome these clasic problems allow·
ing the high volume manufacture of a device, the
MH0026, that delivers 1.5A peak output currents
with 20ns rise and fall times into 1000pF loads. In
a simplified diagram, 0, (Figure 3) provides 0.7V
dead zone so that 0 3 is turned ON for a rising
input pulse and O2 OFF prior to 0, turning ON a
few nanoseconds later. O2 prevents zenering of the
emitter-base junction of O2 and provides an initial
discharge path for the load via 0 3, During a falling
input, the stored charge in 0 3 is used beneficially
to keep 0 3 ON thus preventing O2 from conducting until 0, is OFF. 0, stored charge is quickly
discharged by means of common-base transistor
0..
The complete circuit of the MH0026 (see schematic on page 130 basically makes Darlingtons out
of each of the transistors in Figure 3 .
There are four considerations in determining
power dissipations.
1. Average DC power
2. Average AC power
3. Package and heat sink selection
4. Remember-2 drivers per package
The total average power dissipated by the MH0026
is the sum of the DC power and AC transient
power. The total must be less than given package
power ratings.
Since the device dissipates only 2mW with output
voltage high (MOS logic "O"l. the dominating
factor in average DC power is duty cycle or the
percent of time in output voltage low state (MOS
logic "1"). Percent of total power contributed by
Poe is usually neglible in shift register applications
where duty cycle is less than 25%. Poe dominates
in RAM address line driver applications where
duty cycle can exceed 50%.
. - - -....-ov·
3.1 DC Power (per driver)
DC Power is given by:
EXTERNAL
lNo1ct~
OUT
Poe = (V+ - V-) X (lS(Low)) X
(
ON time
)
OFF time-ON time
or Poe = (Output Low Power) X (Duty Cycle)
FIGURE 3, Simplified MH0026
Vs
h
I S(Low) = Is @V + - V- = 20V
were:
5-19
(J
CD
N
application information (con't)
o
o
::t
Example 1: (V+ = +5V, V- = -12V)
:E
.......
a) Duty cycle = 25%, therefore
CD
N
POC = 17V X 40mA X 17(20 X 25%
o
o
::t
:E
3.3 Package Selection
Power ratings are based on a maximum junction
rating of 175°C. The following guidelines are
suggested for package selection. Graph's illustrate
derating for various operating temperatures.
Po C = 145mW worst·case, each side
POC = 109mW typically
b) Duty cycle = 5%
POC = 21mW
c) See graph.
The above illustrates that for shift register applica·
tions, the minimum clock width allowable for the
given type of shift register should be used in order
to drive the largest number of registers per clock
driver.
Example2: (V+=+17V, \r=GND):
a) Duty cycle = 50%
Po C = 290mW worst·case
POC = 218mW typically
b) Duty cycle = 100%
POC = 580mW
Thus for RAM address line applications, package
type and heat sink technique will limit drive
capability rather than AC power.
3.2 AC Transient Power (per driver)
AC Transient power is given by:
3.31 TO-5 ("H") Package: Rated at 600mW still
air (derate at 4.0mWtC above 25°C) and 900mW
with clip on heat sink (derate at 6.0mW(oC above
25°CI. This popular hermetic package is recom·
mended for small systems. Low cost (about 10¢1
clip·on·heat sink increases driving capability by
50%.
3.32 8·Pin ("N"I Molded Mini·DIP: Rated at
600mW still air (derate at 4.0mWtC above 25°C)
and 1.0 watt soldered to PC board (derate at
6.6mWtC). Constructed with a special copper
lead frame, this package is recommended for
medium size commercial systems particularly
where automatic insertion is used. (Please note for
prototype work, that this package is only rated at
600mW when mounted in a socket and not one
watt until it is soldered down. I
3.33 TO-8 ("G") Package: Rated at 1.5 watts
still air (derate at 10mWI"C above 25°CI and 2.3
watts with clip on heat sink (Thermalloy type
215-1.9 or equivalent-derate at 15mWI"CI.
Selected for its power handling capability and
moderate cost, this hermetic package will drive
very large systems at the lowest cost per bit.
3.4 Summary-Package Power Considerations
The maximum capacitative load that the MH0026
can drive is thus determined by package type, heat
sink technique, ambient temperature, AC power
(which is proportional to frequency and capacitive
load) and DC power (which is principally deter·
mined by duty cycle). Combining equations pre·
viously given, the following formula is valid for
any clock driver with negligible input power and
negligible power in output high state:
where: f = frequency of operation
CL = Load capacitance (including all
strays and wiring I
CL Imax in pF)
10-3
= --;;-- X
Pm,,)mw,IT A,pkg) X R,q - IV+ - V-)' X IDc) X 103
IV'" - V-)' X R,q X flMHz)
Example 3: (V+
= +5V,
\r
= -12V)
PAC = 17 X 17 X f(MHzl X 10· X
CL Imax in pF) = .5 X 10- 3 X
Pm"lmW) X 500 - V s ' X Dc X 103
C L (nF) X 10-9
PAC = 290mW per MHz per 1000pF
Thus at 5MHz, a 1000pF load will cause any driver
to dissipate one and one half watts. For long shift
registers, a driver with the highest package power
rating will drive the largest number of bits for the
lowest cost per bit.
5·20
Vs ' X 500 X flMHz)
Where: n = number of drivers per pkg. (2 for
the MH0026)
Pmax(mW)(T A , pkg) = Package power
rating in milliwatts for given package,
heat sink, and max, ambient tempera·
ture (See graphs)
s:
:::I:
o
o
application information (con't)
N
Req = equivalent internal resistance
0)
For an output pulse width of 500ns, the optimum
value for C, N is:
Req = (v+ - V-)/ls! Low) = 500 ohms (worst
case over temperature for the MH0026 or
660 ohms typically)
C'N = (2 X 10- 3 )(500 X 10-9 )
'"'
"-
s:
:::I:
1000pF
o
o
5.0 Rise & Fall Time Considerations(Note 3)
Vs = (V+ - V-I = total supply voltage across
device
N
0)
The MH0026's peak output current is limited to
1.5A. The peak current limitation restricts the
maximum load capacitance which the device is
capable of driving and is given by:
dv
I = CL at ,,;; 1.5A
Dc = Duty Cycle =
Time in output low state
Time in output low + Time in output high state
The rise time, t"
predicted by:
Table I illustrates MH0026 drive capability under
various system conditions.
(")
for various loads may be
t,= (6V)(250X 10- 12 +C L )
Where: 6V = The change in voltage across C L
'"' V+ - VC L = The load capacitance
For V+ - V- = 20V, C L = 1 OOOpF, t, is:
4.0 Pulse Width Control
t, '"' (20V)(250 X 10- 12 + 10- 12 )
= 25ns
The MH0026 is intended for applications in which
the input pulse width sets the output pulse width;
i.e., the output pulse width is logically controlled
by the input pulse. The output pulse width is given
by:
For small values of C L , equation above predicts
optimistic values for t,. The graph on page 132
shows typical rise times for various load capaci·
tances.
The output fall time (see Graph) may be predicted
by:
t f '"' 2.2R(C s + ~
Two external input coupling capacitors are reo
quired to perform the level translation between
TTLlDTL and MOS logic levels. Selection of the
capacitor size is determined by the desired output
pulse width. Minimum delay and optimum per·
formance is attained when the voltage at the input
of the MH0026 discharges to just above the
devices threshold (about 1.5V). If the input is
allowed to discharge below the threshold, to F F
and t f will be degraded. The graph on page 132
shows optimum values for C'N vs desired output
pulse width. The value for C'N may be roughly
pred icted by:
C, N = (2 X 10-3 ) (PW)o UT
hFE
+
1
6.0 Clock Overshoot
The output waveform of the MH0026 can over·
shoot. The overshoot is due to finite inductance of
the clock lines. It occurs on the negative going
edge when 0 7 saturates, and on the positive edge
when 0 3 turns OFF as the output goes through
V+ - Vbe' The problem can be eliminated by
placing a small series resistor in the ouput of the
MH0026. The critical valve for Rs = 2y'[C[ where
TAB LE 1. Worst Case Maximum Drive Capability for MHOO26*
TO·SWITH
HEAT SINK
PACKAGE TYPE
MINI· DIP
SOLDERED DOWN
TO·S
FREE AIR
TO·5 AND MINI·DIP
FREE AIR
Max.
Max.
Operating
Ambient
LS
60°C
85°C
60°C
85°C
60°C
Frequency j
85°C
60°C
85°C
4
Duty Cycle
100kHz
5%
30 k
24 k
19 k
15 k
13 k
10k
7.5k
500kHz
10%
6.5k
5.1k
4.1k
3.2k
2.7k
2k
1.5k
lMHz
20%
2.9k
2.2k
1.8k
l.4k
1.1k
1.1k
5.8k
1.1k
840
600
430
2MHz
25%
850
650
550
400
280
190
5MHz
25%
620
470
380
290
240
170
120
80
10MHz
25%
280
220
170
130
110
79
-
-
l.4k
*Values in pF and assume both sides in use as non·overlaping 2 phase driver;
each side operating at same frequency and duty cycle with (V+ - V-I
=
17V.
5·21
application information (con't)
L is the self-inductance of the clock line. In
practice, determination of a value for L is rather
difficult. However,R, is readily determined emperically, and values typically range between 10 and
51 ohms. R, does reduce rise and fall times as
given by:
7.0 Clock Line Cross Talk
At the system level,voltage spikes from q" may be
transmitted to q,2 (and vice-versa) during the
and 0 4 come on and pull the output back to V+
A simple method for eliminating or minimizing
this effect is to add bleed resistors between the
MH0026 outputs and ground causing a current of
a few milliamps to flow in 0 4 , When a spike is
coupled to the clock line 0 4 is already "ON" with
a finite hIe' The spike is quickly clamped by 0 4 ,
Values for R depend on layout and the number of
registers being driven and vary typically between
2k and 10k ohms.
8.0 Power Supply Decoupling
transition of q" to MOS logic "1 ". The spike is
due to mutual capacitance between clock lines and
is, in general, aggravated by long clock lines when
numerous registers are being driven. Transistors
0 3 and 0 4 on the q,2 side of the M H0026 are
essentially "OF F" when q,2 is in the MOS logic
"0" state since only micro-amperes are drawn
from the device. When the spike is coupled to q,2,
the output has to drop at least 2 VB E before 0 3
5-22
Power supply decoupling is a widespread and
accepted practice. Decoupling of V+ to V- supply
lines with at least 0.1 f.1F non inductive capacitors
as close as possible to each MH0026 is strongly
recommended. This decoupling is necessary
because otherwise 1.5 ampere currents flow during
logic transition in order to rapidly charge clock
lines.
Clock Drivers
MH7803/MH8803 two phase oscillator/clock driver
general description
features
The MH7803 is a self contained two phase
oscillator/clock driver. It requires no external
components to generate one of three primary
oscillator frequencies and pulse widths. Other
frequencies can easily be obtained by programming
input voltages. Three sets of outputs are provided:
damped and un-damped MOS outputs and TTL
monitor outputs. The MOS outputs easily drive
500 pF loads with less than 150 ns rise and fall
times. In addition the outputs have current limiting
to protect against momentary shorts to the supplies.
•
Two phase non-overlapping outputs
•
No external timing components required
•
Frequency adjustable from 100 kHz to 500 kHz
•
Pulse width adjustable from 260 ns to 1.4ps
•
Damped and un-damped MOS outputs
•
TTL monitor outputs
The MH7803 and MH8803 are available in a 14
lead cavity DIP. The MH8803 is also available in
a 14 pin molded DIP.
block and connection diagrams
Dual·1 "-Line Package
r"'--+-CV~
14 Vss
INHIBIT
WIDTH
2
13 TEST
CONTROL
):>-++-C:>O-+-r-oOTTl <;)2
12 fREQUENCY
MOS DAMPED 1'1
CONTROL
MOSo,
V"
10
MOSDAM1'ED 1'2
+---'lM......f'-o
Mas DAMI'ED "1
MOS¢2
t-1!--.....,.....-,t-'-O MOS DAMPED 1'2
V.,
'100
'-----+"-0 MOS¢l
MH7BOJ
Voo
TEST
'------1"-0 MOS¢l
INHIBIT
TILl',
TTL 1'2
'NO
TOP VIEW
Order Number MH7803J or MH8803J
See Package 9
Order Number MH7803N
See Package 14
5·23
absolute maximum ratings
Operating Temperature Range
-55°C to +125°c
MH7803
O°C to +70°c
MH8803
Storage Temperature Range
-6~C to +l50°c
3OQ°c
Lead Temperature (Soldering, 10 secondsl
22V
7.0V
Vss + 0.5V
Vss + 0.5V
14V
Vss
Vss - Voo
Vee - GNO
Pulse Width Adjust Voltage
Frequency Adjust Voltage
Vss - Voo Minimum
Test and Inhibit Input Voltages
electrical characteristics
PARAMETER
Frequency
Frequency Change from 25°C
MH7803
MH8803
(Note 1)
CONDITIONS
MIN
TYP
MAX
UNITS
Pin 12 at 17V, TA = 25°C
Pin 12 Open, T A = 25°C
Pin 12 at OV, TA = 25°C
300
175
60
500
300
100
600
350
150
kHz
kHz
kHz
Pin 12 at 17V
Pin 12 at 17V
Pulse Width (Note 21
±20
±10
Pin 2at 17V, TA = 25°C
Pin 2 Open, TA = 25°C
Pin 2 at OV, T A = 25°C
Pulse Width Change from 25°C
MH7803
MH8803
0.2
0.5
1.0
0.26
0.75
1.4
Pin 2 at 17V
Pin 2 at 17V
±20
±10
MOS V OH
10H =-100IlA
MOS VOL
10L = 2.0 mA
TTL V OH
10H = -2001lA
TTL VOL
MH7803
MH8803
10L = 2.0 mA
10L = 3.2 mA
Vss -1.1
%
%
0.4
1.3
2.6
IlS
IlS
IlS
±30
±15
%
%
Vss-0.8
Voo+0.15
V
V
Voo+0.5
3.7
2.4
TTL los
±30
±15
3.0
MOS Output Current Limit
V
0.17
0.2
0.3
0.4
8.0
15
70
V
V
mA
mA
Iss
Pins 2,12,13 at OV, and
Pin 1 at -0.3V
10
17
mA
Icc
Pins 2, 12, at OV, and
Pin 1 at -0.3V
0.75
1.1
mA
10
10
13
15
n
n
100
20
150
30
ns
ns
Ro
MH7803
MH8803
7.0
5.0
CL = 500 pF, T A = 25°C
CL =50pF, TA = 25°C
MOS tR,t,
Note 1: These specifications apply for the MH7803 at VSS - VOO = 17V ±10% and over -55°C to +125°C; for the MH8803
at VSS - VDD = 17V ±5% and over O°C to +70°C unless otherwise specified.
Note 2: The duty cycle can not physically exceed 50% at any output. At high frequencies the frequency adjust pin will affect
the pulse width by limiting the duty cycle to slightly less than 50%. Under this condition the pulse width spec does not apply.
typical performance characteristics
Frequency and Pulse Width
Puis. Width Control Voltage
Frequency Control Voltage
600
500
'"
400
I
~
300
1:;
ffi
ff:
20
1.5
I
~
VI Temperature
~ 1.0
i
...'"
"i
PIN 12 OP~N-
~
200
u
~
PIN 2 OPEN
..
0.5
100
ill
ff:
~
r-
5
1.0 3.0 5.0 1.0 9.0 11 13
15
11
FREQUENCY CONTROL VOLTAGE MINUS VOD (V)
5·24
1.0 3.0 5.0 1.0 9.0 11 13
H:+H,f-.I-++-I+-N:++-H
v,.w.
~ -H ~~+1~~r+i-rti-rt~
0
0
-10
15
11
PULSE WIDTH CONTROL VOLTAGE MINUS Voo (V)
II
-30 '-"'-'-l-L-'-'-'-...L...J'-'--'-'...J.....L...L.J
-15 -50 -25 0 25 50 15 100 125
AMBIENT TEMPERATURE I'C)
s:::I:
....a
typical performance characteristics (con't)
CO
Width
VSS-VDD
YS
20
~
I,
f:
1
j)
10
~
--L
>
:.
.
>
~
w
~
-20
z
~
-30
12
13
rlt
14
15
~
I
;:
Maximum Package Dissipation
...--,---r--,--.,--,--r
...~
f--+---+-
z
"'
f
,.~
~
"
17
23
24
25
25
50
75
100
TEMPERATURE
VSS-VOD
125
.5
4.0
2.0
150
lOU
200
JOO
400
500
600
FREQUENCY (kHz)
ICC vs Duty Cycle
ISS vs Duty Cycle
"Jl
100
re)
0.9 . - - - , - - - , - - - ; - - - , - - ,
8.0
6.0
oto)
200
iii
~
0.5
CO
CO
300
a:
1.0
..x
16
s:
::I:
jO
.5
o
-
........
400
z
iii
c
I I
-10
IT~!2U
:
1,I +
~FREQUENCY -
~
1.5
oto)
Total Transient Power
vs Frequency vs Total CL
Frequency and Pulse
--
0.8
VI""-
-----l------+-I
1
20
30
..§.
0.7
0.6
I
10
"
0.5
40
10
50
20
30
50
40
DUTY CYCLE (%)
DUTY CYCLE I%}
applications information
TTL MONITOR OUTPUTS
16_~OS
<..',
80-
0=
The TTL outputs are extra functions provided for
monitor or synchronization applications. In some
systems these outputs may not be required. For
these cases the V cc pin may be left open and the
TTL circuitry power consumption will be virtually
zero.
[Oi
20-
:
1
I
-+---it.
-40-
-:.~=
I
I
I
THRESHOLO
!
)
i
I
!
M
MOSOS
0
r
I
:: ~~o,Tt!r,;;\
I.
The TTL outputs are slaved to the MOS outputs.
Thus the TTL outputs start to switch when the
MOS outputs cross the TTL threshold voltage
(about 1.5V above ground). Figure 1 depicts the
effect of different supply voltages on the TTL
waveform when the MOS outputs are driving
capacitive loads.
tM~Sr-
15VTHRESilOLD
-80-
::~
[
~
OUTPUT WAVEFORMS
WITH+17V,+5.0V,OVSUPPLIES
OUTPUT WAVEFORMS
WtTH +5.0V.-12V,DV SUPPLIES
(AI
(BI
FIGURE 1.
DAMPED MOS OUTPUTS
Typically they perform as follows:
An extra set of MOS outputs provides a 10 ohm
resistor in series with each output line. These
resistors give the output pulses an R·C rolloff
which tends to minimize ringing or peaking
problems associated with board layout.
INHIBIT AND TEST INPUTS
The INHIBIT and TEST inputs are designed to
facilitate testing of the device. They were not
included in the IC for system use.
INHIBIT Input: in the low state prevents pulses
from being initiated on either phase output.
High Level Input:
V 1H
2
Voo + 2.0V
Low Level Input:
Voo + O.2V
2
V 1L
2 V DO
-
O.5V
5-25
M
o
CO
CO
applications information (con't)
:E
TEST Input: in the low state forces a ONE state
on all outputs. The test input should only be used
with the INHIBIT input also in the low state.
CO
High Level:
::t
......
M
o
......
::t
V1H ~ Voo + B.OV
:E
Low Level:
Where
PAC
= [(Vcc -
GND)2
X
f x Cd TTL
+ [(V ss - V OO )2 x f x CLl MOS
And
Poc = (lcd x (Vcc - GND) + (Iss)
x (Vss-Voo)
A pull-up resistor is connected from the TEST
pin to Vss internally.
for Icc and Iss selected at the appropriate duty
cycle.
POWER CONSIDERATIONS
For practical cases the PAC TTL can be neglected
as being very small compared to PAC MOS'
Internal power dissipation is affected by three
factors:
• dc power
• ac power
• package dissipation capability
The total average power dissipation is the summa·
tion of the dc power and ac power. This sum
must be less than the maximum package dissipa·
tion capability at the particular operating tempera·
ture to insure safe operation, i.e.:
P01SS = PAC + Poc :::; PMAX
5·26
Thus P01SS is the sum of the MOS transient
power (total for both sides of the MH7803) and
the standby power of the TTL and MOS sections
of the MH7803.
DECOUPLING
It is recommended that each device be decoupled
with a O.lIlF capacitor from Vss to Voo. If there
is noise on the supply lines, better frequency and
pulse width stability can be obtained by connecting
a O.OOlIlF capacitor from the frequency control
pin to Voo and another O.OOlIlF capacitor from
the pulse width control pin to Voo.
3:
:I:
Clock Drivers
00
00
o
00
MH8808 dual high speed MOS clock driver
general description
features
The MH8808 is a high speed dual MOS clock
driver intended to drive the two phases of a
memory array of 500 pF per phase at rates up to
4.0 MHz. The design includes output current
limiting for controlled rise and fall times. Two
DTLlTTL compatible status outputs monitor clock
outputs and provide a corresponding TTL logic
level for status indication. Both direct and inter·
nally damped outputs are available for each phase
to suite the particular application. It is ideally
suited for driving MM5262 2.0k RAMs.
•
High Speed: 18 ns typ delay and 20 ns typ rise
and fall times with 500 pF load
• Current limited outputs ±450 mA typ
• TTL compatible status outputs
•
Direct and damped outputs available
•
1W dissipation capability at 25°C T A
•
16 pin cavity dual·in·line package
• Output high level clamped to +5V
connection diagram
Dual·1 n-Line Package
DAMPED
Vss
OUT
16
15
voo
DAMPED
OUT
OUT
12
14
11
OUT
NC
10
6n
*00 NOT CONNECT TO THIS PIN.
TOP VIEW
Order Number MH8808J
See Package 10
5-27
00
o
00
00
absolute maximum ratings
~
Vss
V BB
J:
+7V
-
26V
lW
V DD
Total Power Dissipation (Note 1)
Operating Temperature Range
oDe to +700e
electrical characteristics
The following apply for Ves
= +B.OV, Vss = +5.0V. V OD = -15V. T A = 25°C unless otherwise stated.
PARAMETER
MIN
CONDITIONS
Input Current
Y,N = -9.0V (Note 2)
Output Low Voltage
lOUT
= +1.0 mA,
VIN
= -lOV
TYP
MAX
UNITS
10
mA
-14
V
(Note 2)
Output High Voltage
lOUT = -1.0 rnA, VIN = -14V
4.S
Status "1" Voltage
lOUT =-2S0ILA, Y'N =-14V
3.0
Status "0" Voltage
lOUT = 20 mA, Y'N = -10V
(Note 2)
O.S
V
Output Damping Resistor (Iss)
Y,N = -ll.SV, Vss = +S.8V,
Voo = -17.SV, V •• = +8.SV
(Note 2)
37
mA
Output Damping Resistor (Iss)
Y,N =-l1.SV, Vss =+S.8V,
Voo = -17.SV, V •• = +8.SV
(Note 2)
24
mA
Output Damping Resistor (100)
Y,N = -l1.SV, Vss = +S.8V,
Voo =-17.SV, V •• =+8.5V
(Note 2)
-S6
mA
Output Rise Time
CL = SOO pF
26
Output Fall Time
CL =
sao pF
26
Delay to Negative-Going Output
CL =
sao pF
7.0
22
Delay to Positive-Going Output
CL = 500 pF
10
30
n,
n,
n,
n,
S.S
Note 1: Maximum junction temperature is 110°C. For operation above 2SoC derate at 85°C/W 8JA for still air.
Note 2: Test only one input high (more positive) at a time.
5·28
V
V
s:s:
s:s:
Analog Switches
~~
U1U1
NO
................
MM450/MM550, MM4511MM551
MM452/MM552, MM455/MM555 MOS analog switches
s:s:
s:s:
U1U1
general description
U1U1
NO
The MM450, and MM550 series each contain
four p channel MOS enhancement mode transistors built on a single monolithic chip. The four
transistors are arranged as follows:
MM450, MM550
MM451, MM551
MM452, MM552
MM455, MM555
Dual Differential
Switch
Four Channel
Switch
Four MOS Transistor Package
Three MOS Transistor Package
These devices are useful in many airborne and
ground support systems requiring multiplexing,
analog transmission, and numerous signal routing
applications. The use of low threshold transistors
(V TH = 2 volts) permits operations with large analog input swings (± 10 volts) at low gate voltages
(-20 vOltsl. Significant features, then, include:
•
Large Analog Input Swing
•
Low Supply Voltage
±10 Volts
VSULK
VGG
•
Low ON Resistance
•
Low Leakage Current
•
I nput Gate Protection
•
Zero Offset Voltage
= +10
= -20
Volts
Volts
V 1N
-10V
150£1
V 1N
+10V
75£1
200 pA@25°C
Each gate input is protected from static charge
build-up by the incorporation of zener diode protective devices connected between the gate input
and device bulk.
schematic and connection diagrams
Metal Can Package
Note. Pill 5collnected to case and device bulk
Metal Can Package
Note: Pin 5 connected to case and device bulk.
Order Number MM450H
or MM550H
Order Number MM451H
orMM551H
See Package 24
See Package 24
Flat Package
Metal Can Package
Note1: Pins 1 and R connected to case and
device bulk. Dralll and Source may be
interchanged.MM452F,MM552F.
Note 2: MM4520 and MM552D (dual-in-line
packa~es) tJave same pm CUlmectlonsas
MM452F and MM552F shown above.
Note: PIO 5c[lnnected to case and device blilk
Dram and Source mav be mterchanged.
Order Number MM452D
orMM552D
Order Number MM455H
or MM555H
See Package 2
See Package 24
Order Number MM452F
orMM552F
See Package 26
6-1
absolute maximum ratings
MM450, MM451, MM452, MM455
Gat. Voltage (VGG)
Bulk Voltage (V BULK)
Analong Input (V IN )
MM550, MM551, MM552, MM555
+IOV to-JOV
+IOV
+IOV to-20V
200 mW
O°C to +70°C
-65°C to +150°C
+IOV to-JOV
+IOV
+IOV to-20V
200 mW
_55°C to +125°C
_65°C to +150o C
Power Dissipation
Operating Temperature
Storage Temperature
electrical characteristics
STATIC CHARACTERISTICS (Note 1)
CONDITION
PARAMETER
TYP
MAX
UNITS
V
V
150
600
n
VIN = Vss
75
200
n
V GS = -25V, VBS = 0, T A = 25°C
10 '0
20
VOG=O,lo=lJlA
ON Resistance
VIN = -10V
ON Resistance
OF F Resistance
Gate Leakage Current (I GSB)
I nput (Drain) Leakage Current
MM450, MM451, MM452, MM455
MIN
±10
3.0
Analog Input Voltage
Threshold Voltage (V GS(TI)
1.0
2.2
n
pA
TA = 25°C
TA = 85°C
TA = 125°C
0.025
0.002
0.025
100
1.0
1.0
nA
JlA
JlA
TA = 25°C
TA = 70°C
0.1
0.030
100
1.0
JlA
Output (Source) Leakage Current
MM450, MM451, MM452, MM455
T A = 25°C
0.040
100
nA
Output (Source) Leakage Current
MM450
MM451
MM452, MM455
MM450, MM451, MM452, MM455
TA
TA
TA
TA
Output (Source) Leakage Current
MM550
MM551
MM552, MM555
TA = 70°C
TA = 70°C
TA = 70°C
Input (Drain) Leakage Current
MM550, MM551, MM552, MM555
= 85°C
= 85°C
= 85°C
= 125°C
nA
1.0
1.0
1.0
1.0
JlA
JlA
p.A
JlA
1.0
1.0
1.0
JlA
JlA
JlA
DYNAMIC CHARACTERISTICS
Large Signal Transconductance
Vos = -10V, 10 = 10 mA
f = 1 kHz
4000
Jlmhos
CAPACITANCE CHARACTERISTICS (Note 2)
PARAMETER
----
Analog Input (Drain) Capacitance (COB)
ALL
Output (Source) Capacitance (CSB )
MM450,
MM451,
MM452,
MM455,
Gate Input Capacitance (C GB )
MM450,
MM451,
MM452,
MM455,
Gate to Output Capacitance (C Gs )
ALL
DEVICE TYPE
MIN
TYP
MAX
UNITS
8
10
pF
MM550
MM551
MM552
MM555
11
20
7.5
7.5
14
24
11
11
pF
pF
pF
pF
MM550
MM551
MM552
MM555
10
5.5
5.5
5.5
13
8
9
9
pF
pF
pF
pF
3.0
5
pF
Not. 1: The resistance specifications apply for -55°C ~ TA ~ +B5°C, VGG = -20V, VBULK = +10V, and a test current of
1 mAo Leakage current is measured with all pins held at ground except the pin being measured which is biased at -25V.
Note 2: All capacitance measurements are made at OV bias at 1 MHz.
6·2
typical dynamic input characteristics
(T A
2S0C Unless Otherwise Noted)
=
CONDITION 1:
ANALOG INPUT VOL lAGE
AT +10 VOL TS
8/'t+,;1!
Dynamic Ron
Ron vs VGG
. -Jr.
10,000
vas'" +lOV
+1~
E
1000
OUT
i
.e
100
T
2
E
0
-f-
-
0-..
VGG
-,
10
0
"
'~f'
-
;t
.:'-
F=
-16
=
. -Jr
OV
YS
E
f=
Vss '" +lOV
VV
-0.6
-02
6
:t.:--
~~: :~::~~
.-
4
;t
2
E
0
z
~",..
4
t-- --r----
VGG
,s
..l
10
0
-4
2
-8
-12
-16
-
+0.6
+1.0
IrVGG
eo
OV /
"
V
-4V
'/
V
...
'- ,,~ :I-r
-it,';::: IGr-Li; .;::
--
....f:::::V'
217'; ~
~"t
:::-;~
I'-
10
-1.0
-20
VOUT
Vas" +10V
VIN " DV
8
VIN "'OV
100
T
10
.'F=
'b~TA' 55-C
£
<02
IWIN (V)
VGG
I
VGG '" -5
VaG'" -10
VGG "'-20
Dynamic Ron
Ron
1000
VOUT
VGG'~f_
';;':'''V
1"-
8
10
-1.0
10,000
V8B +l0V
~V,'/
~-'
I'-'"
VGG (V)
CONDITION 2:
ANALOG INPUT VOL rAGE
AT 0 VOLTS
V/(I.'/
+6
VGG '" +4
I
'/'/
l7 ~'"
VGG '" +10J\-tz~
2
6
-22
. 'IOV/,
VaG'" +8
rI/
4
- - r--
V OlJT
~VGG
4
CC~ ~V" -"OV
-----=t VIN_~l~_
~ t;s- - -
Vas ~ +10V
8
~ -1 TA -25O
I\"!i rTA '850
-
~
10
VGG '" -5V J
VGG "'-BV- t-VGG '" -10V- i VGG '" -15V_
iVaG'" -20V
-02
-0.6
<0.6
'02
+1.0
6V," IV)
VaG (V)
CONDITION J:
ANALOG INPUT VOLTAGE
AT -10 VOLTS
Dynamic Ron
Ron vs VGG
. -Jr.
-tOY
10
100,000
Vee +10V
Vee'" +10V
VIN '" 10\1
8
-
f=-G r--
-
- -.. -10,000
OUT
-
)
£
T
VGG
4
TA '8n ~
_ TA '25"C
;t
55°C_
z
i/jrT.'
"
1000
6
=
E
0
2
4
.
-11
-18
-2~
-19
1
VIN '" -lOY
I
...::~
~~
-1.0
r+
-fi.6
-02
-50
-45
VeB:5~.E
'+ V•• -1.5V'- f= f=
Vee'" tOV ~ i - t-1000
~
~
i.e
'"
100
>z
E
f=
..
~
-30
-25
~
VeB=OV~
V•• ' 2.5V
0
~~
I.f'
-35
z
u
_lv G; , ~'5VI=
-40
-13.5
~ -12
~~
~
-20
-15
-10
:::;"-
-4
-8
-12
VGG (V)
-16
-20
-20
+0.6
+1.0
I
6.0
~,
.E
-60
-80
-100
VDS - DRAIN TO SOURCE Val TAGE - Val TS
J
!
z
......
-40
<0.2
8.0 t--Ves"'OV
4.0
/
2.0
./
0
0
VGG =- -20V- i - ' -
t-- Vps ~ -2~V
i
0
0
-18~_f--_
VGO =- -19V
Drain Current vs
Gate To Source Voltage
Vas '" OV
""'' ' '
6
-4.5
-5
10
I
VGG'
10
f=
:...;.;..- i--......
P""
k::~
:;;.
/'; V'N (V)
Typical Drain Characteristics
Ron vsVGG
~10V
iii
, V GG =- -16V
VOG (V)
10,000
VOUT -
l,41 ,
f--1f ~GG' -11'~ -
r--
6
8
10
100
-16
2
Vee =- +10V
0
-1.0
-2.0
V
-3.0
-4.0
-5.0
VGS - GATE TO SOURCE VOLTAGE - VOLTS
typical input capacitances
50
40
30
20
MM450, MM550
MM451,MM551
C 1N vs VIN
C1Nvs V 1N
H=t=l Vaa::: +10
VG~' ~20V
50
40
30
.A
FVGG =-10V
10
Lf= f=
20
B-
!::'''''''
-10
=
. ~GG ;-IIOV •
VGG
5
4
3
+10V
-2
'2
=
<10
-10
-6
OV
f== P-
'/-
i
'2
'6
-10
<10
f=: f=: F
.... ~
VGG '" -20V
.~
-2
Vaa '" +1DV
10
J
--'6
f== f=:
VaG::: +10V
IJ j
-6
50
40
30
20
10
U
VGG :: OV
VaG
z
CIN vs V 1N
==t==t==t=- Yaa '" +tOV
Vt"G' -20V
~
J
MM452, MM552 , MM455 , MM555
1 V
VGG =
VGG
=
~ f=: ~
OV li- i:;;;
r1-
,
jGGC't
-6
-2
+6
'2
+10
Y'N (V)
typical applications
EQUIVALENT
rr
1MM451--------i
.---_ _.......,1
TOGGLE
INPUT
o--i-i--+...>---1r-+--+......
o-'"t-'...-+----1r---'
1 ______ _
L
SWITCH #1
OUTPUT
SWITCH 'Ill
OUTPUT
1
1
"'---"1
~~~J~~~t;
L
I OUTPUT
I
DPDT Analog Switch
1
1
_J
VIDEO
VIDEO
INPU1.#1
OUTPUT #1
VIDEO
VIDEO
INPUT #2
OUTPUT #'l
4 Channei Multiplexer*
w
TOGGLE
INPUT
DPST High-Frequency Switch
6-4
*Expansioll in the number of data input lines
is possible by usillgmultiple level series
switchesaltowing the same decode gates to
be used for all lower rank decoding.
INTELLIGENCE
Analog Switches
MM454/MM554 four-channel commutator
general description
Low Leakage Current (T A ~ 25°C)
(T A ~ 85°C)
• All Channel Blanking input provided
• Reset capability provided
• Low ON Resistance
The MM454/MM554 is a four·channel analog com·
mutator capable of switching four analog input
channels sequentially onto an output line. The
•
device is constructed on a single silicon chip using
MaS P Channel enhancement transistors; it con·
tains all the digital circuitry necessary to sequen·
tially turn ON the four analog switch transistors
permitting multiplexing of the analog input data.
The device features:
• High Analog Voltage Handling
• High Commutating Rate
200 pA
50 nA
200Q
In addition, the MM454/MM554 can easily be
applied where submultiplexing is required since a
4:1 clock countdown signal is provided which can
drive the clock input of subsequent MM454/MM554
units.
±10V
500 kHz
logic and connection diagrams
ANALOG
INPUTS
4
ANALOG
OUTPUT
CLOCK
INPUT
OUTPUT
4:1
COUNTDOWN
RESET---....- - - - - - - - - - - '
Flat Package
I-------rCLOCK INPUT
fOUR Blr
COUNTER
I
AND
DECODER
OllTPUT4,1 COUNTDOWf,!
r--------f"- NO 1 ANALOG INPUT
.--___-+"-
NO.2 ANALOG INPUT
ALL CHANNEL BLANKING
NO.1 ANALOG INPUT
NO CONNECTION
NO.4 ANALOG INPUT
.,,-'------'
L-_ _...!._ANAlOG OUTPUT
Note: Pin 7 CORRected to case and to device bulk. Nominal Operating Voltage5: VGG = -24V; VOD "OV;
Vss = +12V, RESET BIAS" +12V (OV for RESET), ALL CHANNEL BLANKING BIAS'" +12V (OV for
BLANKING)
Order Number MM454F
orMM554F
See Package 26
6-5
absolute maximum ratings
(Note 1)
+10V to -30V
+10V
+10V to -20V
200mW
_55°e to +125°e
oOe to +70o e
_65°e to +150 O e
Gate Voltage (V GG)
Bulk Voltage (V ss )
Analog Input (V IN)
Power Dissipation
Operating Temperature MM454
MM554
Storage Temperature
static characteristics
(Note 2)
PARAMETER
CONDITION
Analog Input Voltage
ON Resistance
ON Resistance
OFF Resistance
Analog Input Leakage Current
MIN
170
90
10 '0
0.050
0.006
0.0001
0.030
0.100
30
0.0001
0.030
V'N = -10V
V ,N = Vss
MM454
MM454
MM554
MM554
Analog Output Leakage Current MM454
MM454
MM554
MM554
V ss Supply Current Drain
VGG Supply Current Drain
TYP
T A = 25'C
TA = 85'C
TA = 25°C
T A = 70°C
T A = 25°C
TA = 85°C
T A = 25°C
T A = 70°C
Vss = +12V
VGG=-24V
3.8
2.4
MAX
±10
600
200
100
1.0
100
1.0
100
1.0
100
1.0
5.5
3.5
UNITS
V
!1
!1
!1
nA
J,lA
nA
J,lA
nA
J,lA
nA
J,lA
mA
mA
capacitance characteristics
TYP
MAX
UNIT
Analog Input Capacitance Channel OFF
PARAMETER
liN
=
0
4
6
pF
Analog Input Capacitance Channel ON
'iN
=
0
20
24
pF
Analog Output Capacitance
liN
=
0
20
24
pF
Clock Input
Vel
Reset Input
VAESET
=
Blanking Input
VBlANK
=
clock characteristics
CONDITION
=
MIN
2.0
pF
+12V
2.0
pF
+12V
2.0
pF
+12V
(Note 3)
PARAMETER
CONDITION
Clock Input (HIGH)(')
Clock Input (LOW)
MIN
TYP
Vss - 2
-5
Clock Input Rise Time (POS GOING)
a
VSS -2
Vss
Vss
V
+5
V
20
J,lsec
Vss
a
Countdown Output (NEG) Val
Maximum Commutation Rate
UNIT
No requirement
Clock Input Fall Time (NEG GOING)
Countdown Output (POS) V OH
MAX
0.5
+10.0
V
MHz
2.0
+12
V
+14
V
Note 1: Maximum ratings are limiting values above which the device may be damaged. All voltages referenced to VOD
=
O.
Note 2: These specifications apply over the indicated operating temperature range for VGG = -24V. VOO = OV, VSS = +12V,
VRESET = +12V. ON resistance measured at 1 rnA, OFF resistance and leakage measured with all analog inputs and output
common. Capacitance measured at 1 MHz.
Note 3: Operating conditions in Note 2 apply. VSS to VDD (OV) voltage is applied to counting and gating circuits. VGG is
required only for analog switch biasing. All logic inputs are high resistance and are essentially capacitive.
Note 4: Logic input voltage must not be more positive than VSS.
6·6
typical performance characteristics
RON vs Analog Voltage
260
....z
VDO
'"~
220
~
~I
\
180
"'-;
.....
!:'"
140
'"~
100
~
'"
'"
I'.
.......
TA
"
+85
~
TA
z
"
-55')C
l
60
-10 -8 -6 -4 -2
_
VlsS 1>12V
-
;>:
U
:1:
+2S"C
~=>~
--
~-"
~ z
~u
t- t-
..... .... "
1jj
'"
-
0
l"- t-.
'"z
'"
0 +2 +4 +6 +8 +10
CHANNEL "ON"
11
;3
I
=
30
28
16
24
....z
-
OV
~:~L=K_;;~2V
'c
'i-. _ TA
1'k1.......
'"
10
18
16
14
11
10
8
6
4
1
CHANNEL "OFF:;';;'
o
-10 -8 -6 -4
Voo ANALOG INPUT VOLTAGE IVI
13
~
12
.,
~
11
>
10
+9
V
+9
V
V
V
0 +2 +4 +6 +8 +10
Minus VIN (max) vs VGG
v
-30
-18
-24
t-
TA
'"
11".0
~ -16
0
,:
10.
~
-11
-8
lUi
+85°C
-10
TA '" +25°C-
rt I!=o r-T.· -55'C-
~
~
~
-4
o
10
-2
Voo ANALOG INPUT VOLTAGE IVI
Plus VIN (max) vs VSULK
14
.,t!.
11
12
13
14
V,n MAXIMUM POSITIVE GOING
ANALOG EXCURSION IVI
o
-2 -4 -6 -8 -10 -12 -14 -16 -18 -10
V,n MAXIMUM NEGATIVE
ANALOG EXCURSION (Ron" 1.0 kill (V)
timing diagram
CLOCK 0
IN 1
CHI
CH2
ON
OFF
ON
,--,
CH3 OFF _ _ _--'I
~:
,....-.,
IL._ _ _--II
,........,
''--_ _........1
,.....-,
IL._ _ _---li
'-
r
OUTPUT
"0"
COUNTDOWN "I"
NOTE: "0" LEVEL '" +12V
","LEVEl" OV (GNU)
6·7
(.)
....
0)
o
o
Analog Switches
J:
«
......
AH0014/AH0014C* DPDT. AH0015/AH0015C quad SPST.
AH0019/AH0019C* dual DPST-TTL/DTL compatible
MOS analog switches
0)
....
o
o
J:
«
(.)
general description
....
o
It)
This series of TTLlDTL compatible MOS analog
switches feature high speed with internal level
shifting and driving. The package contains two
monolithic integrated circu it chips: the MOS analog chip is similar to the MM450 type which
consists of four MOS analog switch transistors;
the second chip is a bipolar I.C. gate and level
shifter. The series is available in both hermetic
dual·in-line package and flatpack.
o
J:
«
......
....
It)
o
o
J:
«
(.)
o::t
....
features
o
• Large analog voltage switching
±10V
500 ns
• Fast sw itch ing speed
• Operation over wide range of power supplies
o
J:
«
......
o::t
....
o
•
Low ON resistance
• High OFF resistance
•
Fully compatible with DTL or TTL logic
•
Includes gating and level shifting
These switches are particularly suited for use
in both military and industrial applications such
as commutators in data acquisition systems, multiplexers, AID and D/A converters, long time
constant integrators, sample and hold circu its,
modulators/demodulators, and other analog signal
switching applications. For information on other
National analog switches and analog interface elements, see listing on last page.
block and connection diagrams
o
J:
«
ANALOGINAI
ANALOGINBt
ANAlOGINA2
ANALOGINB2
r----------,I
r----------,I
"I
I
~
"I
,I
I
I
I
I
"11
I
~
"I
I"
I
I
I
I
19
ANAlOGOUTI
ANALOG INB1
ANALOGOUTZ
E:~
ij'l
I
ANALOG IN Al
,I
I
9
I
I
'I
I
ANALOGINB2
--r-.o
~'I
_ __ .J
Note: Aliloglcmputs
shown at logic "1."
LO~IC
LOGIC
B
Order Number AH0014F
or AH0014CF
Order Number AH0014D
orAH0014CO
See Package 26
See Package 2
Dual DPST
~ANAlOGOUTl
1'1
I
,
I
ANAlOGIN2~ANAlOGOUT2
I
"
~
7,
I
18
I
~'
J
:
~
l
I,
:
ANAlOGOUTJ
Ii'i'i'~' t=::,
IL
_
2
_
1
ANALOG OUT 4
-'f.!..-'.D
_
16
'4
15
LOGIC4LOGIC3LOGIC2LOGICI
Note: Atllogu;inputsshownatlogic "1."
Order Number AH0015D
orAH0015CD
See Package 2
'Previously called NH0014/NHOO14C and NH0019/NHOO19C
6-8
_ __ .J
12 13
QuadSPST
ANALOG IN 4
~V'
i2--GNO
L___
Note: All togicmputs
shown at loyic "1."
r--------,
ANALOGIN3
ANALOG OUT 2
J..!!--vcc
lOGIC
ANALOGIN,
ANALOG OUTI
~v-
I
I
12
lOGIC
A
I"
I
I
I
I
15
I
I
,I
'II
lL-GND
L___
~
,I
ANALOGINA1
6
r
--------l
'.AIOGINB1~
I
;::::::t--f-ANAIOGOUT'
I
I
I
ANALD"NA2~
I
l
ANAIO'''82~
~A.AIOGOUT2
I
I
:I
I
L
~I ~I tt::*
I.!2-- vcc
t1--GND
__
1 2
LOGIC
At
LOGIC
__-1
1312
lOGIC
N(lte: Pill c(lnnectionsare ide.ntlca!
A2
for DIPand Flatllack.AII Inglc
lOGIC inputsareshownatlngic"l."
82
Order 'Number AH00190
orAH0019CD
See Package 2
Order Number AH0019F
orAH0019CF
See Package 26
»
:::t
o
o....
absolute maximum ratings
Vee Supply Voltage
V~ Supply Voltage
V Supply Voltage
V+/V- Voltage Differential
~
7.0V
-30V
+30V
40V
5.5V
··65°C to +150°C
Logic Input Voltage
Storage Temperature Range
Operating Temperature Range
AH0014, AH0015, AH0019
AH0014C, AH0015C, AH0019C
Lead Temperature (Soldering, 10 sec)
electrical characteristics
.........
»
:::t
o
o....
~
(")
_55°C to +125°C
_25°C to +85°C
300°C
»
:::t
o
o....
(Notes 1 and 21
c.n
.........
PARAMETER
CONDITIONS
Logical "1" Input Voltage
Vee = 4.5V
MIN
TYP
MAX
2.0
UNITS
V
Logical "0" Input Voltage
Vec=45V
Logical "1" Input Current
Vee = 5.5V
V ,N = 2AV
5
Il A
Logical "1" Input Current
Vee = 5.5V
V ,N = 5.5V
1
mA
Logical "0" Input Current
V ee =5.5V
V ,N = OAV
0.2
0.4
mA
Power Supply Current Logical "1"
Vee = 5.5V
V ,N = 4.5V
0.85
1.6
mA
Vee = 5.5V
V ,N = OV
0.8
V
Input - each gate (Note 3)
Power Supply Current Logical "0"
Input - eaeh gate (Note 3)
AH0014, AHOO14C
AH0015, AHOO15C
AH0019, AHOO19C
V ,N (Analog) = +10V
V ,N (Analog) = -10V
Analog Switch I nput Leakage Current -
200
600
mA
mA
rnA
D.
D.
D.
10"
V ,N = -10V
AH0014, AH0015, AH0019
TA = 25°C
TA = 125°C
25
25
200
200
pA
nA
AH0014C, AH0015C, AHOO19C
T A = 25 Q C
T A = 70°C
0.1
30
10
100
nA
nA
40
40
400
400
pA
nA
10
50
nA
nA
V OUT = -10V
Current - each output (Note 4)
AH0014, AH0015, AHOO19
T A = 25°C
TA = 125°C
AH0014C, AH0015C, AHOO19C
T A = 25 Q C
TA = 70°C
0.05
4
Analog Input (Drain) Capacitance
1 MHz
@
Zero Bias
8
10
pF
Output Source Capacitance
1 MHz
@
Zero Bias
11
13
pF
Analog Turn·OFF Time -
See test circuit; T A;::;;: 25°C
400
500
ns
350
100
100
425
150
150
ns
ns
ns
Analog Turn·ON Time -
tOFF
tON
See test circuit; T A
0=
2SoC
AH0014, AHOO14C
AH0015, AHOO15C
AH0019, AHOO19C
Note 1: Min/max limits apply across the guaranteed temperature range of -55°e to +125°e for AH0014, AH0015, AH0019
and -25°C to +85°C for AH0014C, AH0015C, AH0019C. V- = -20V. V+ = +10V and an analog test current of 1.0 rnA unless
otherwise specified.
Note 2: All typical values are measured at T A = 25°e with Vee = 5.0V. V+ = +10V, V- = -22V.
Note 3: Current measured is drawn from Vee supply.
Note 4: All analog switch pins except measurement pin are tied to V+.
(")
»
:::t
o
o....
»
3.0
0.41
0.41
each input (Note 4)
Analog SWitch Output Leakage
c.n
CD
75
150
Analog Switch OFF ReSistance
o
o....
.........
1.5
0.22
0.22
Analog Switch ON Resistance - each gate
»
:::t
:::t
o
o
....
CD
(")
(.)
...
m
o
analog switch characteristics
o
J:
RON vs Temperature
«
RON vs Temperature
125
.......
...
o
m
125
V:N "
VIN '" VOUT '" +10V
I
o
.,u
J:
«
(.)
...
100
."
75
~
I50 ~
?
25
z
Il)
o
o
]
V
.,
u
..... i-"""
;:
~
.,
Q
-55°C
«
.......
25'
-15'"
65'
/
1/
~
..... 1-'
.,
175
~
150
~
125
~
50
25
-w
v,~"Jou,I"-110V
200
-"
w
u
~
AMBIENT TEMPERATURE (OC)
...
225
~
75
0
_55'
105'"
RON vs Temperature
~ou;" oJ
100
-"
0
J:
(Note 2)
25'
65'
V
V
V
100~
_55 0
1050
'L
25'
_15 0
AMBIENT TEMPERATURE (OC)
65'
105'
AMBIENT TEMPERATURE (OC)
Il)
o
o
Leakage vs V'N (Channe' "OFF",
C'N vsV'N
J:
«
v+:o IOV
50
"
20
(.)
!
CHANNEL "ON" - CHANNEl "ON"-V-"'-OV
V-"'-20V
~
...
o
~
z
U
~
~
;;:
75 1.....
50
~
V+" +10V
V- '" NO EFFECT
.,~
J:
I'
25
I'
10
;
0
5
z
z
-25
2
~
...
o
1
~
11
==';=':;NEL "ON"
v- '" -tOV
-10 -8-6 -4
-2 0
CHANNEl "OFF"
v- =-20V
f',
+10
ANALOG VIN (V)
o
0
>
-5
~
-10
Q
"
0
i
-10
Vee'" 5.0V
+5
~>
~
"
-50
-75
+2 +4 +6 +8 +10
~
~
Q
o
Driver Gate V,N vs VOUT
+10
V-"'-22V
V+ '" B.OV
125°C
t-
25°(;
_55°(;
-15
-20
-25
0 0.5 1.0 1.5 2.0 1.5 3.0 3.5
ANALOG VIN (V)
INPUT VOL TAGE (V)
J:
«
Schematic (Single Driver Gate
and MOS Switch Shown'
~
.~'"''''
'~f
Analog Switching Time Test Circuit
'''"'~'OO'
I
ANALOG
-=-
WJ-~'''"'
'"'_J
""'
6BK
-=-
w
,
,
".~
,
DV
~,
'"
AL
',.-0-...1
I
I
,
!
lDV
I
I
DV
:
~'"
:
I
I
I
I
I
, I
~10N-:
r--l0Ff~
selecting power supply voltage
The graph shows the boundary conditions which
must be used for proper operation of the unit.
The range of operation for power supply V- is
shown on the X axis. (t must be between -25V
and -8V. The allowable range for power supply
V+ is governed by supply V-. With a value chosen
for V-, V+ may be selected as any value along a
vertical line passing through the V- value and
terminated by the boundaries of the operating
region. A voltage difference between power supplies of at least 5V should be maintained for
adequate signal swing.
6-10
~
v- -;5
-15
p
V+
25
20
15
10
5
0
-5
-5
-10
-15
-20
-25
»~
o
o
...&
typical applications
Integrator
~
......
Reset Stabilized Amplifier
»~
r-----AKoiii41
I
o
I
RESET
9
I
~
I
(')
»
~
o
o
v,.o-'W~~..,
v"
...&
U1
......
»
~
">O------....-ov
o
o
oo,
...&
U1
(')
»~
o
o
...&
CD
analog switch data sheets
For additional applications information, see the
following:
AN·28 High·Speed MOS Commutators, Mrazek
AN·33 Analog-Signal Commutation, Wollesen
AN·38 MOS Analog Switches, Stump!Woliesen
For information on other National analog switches
and interface circuits, see the following data sheets:
MOS Analog Switches
Dual Differential - MM450/MM550
Triple - MM455/MM555
Quad - MM452/MM552
Four Channel - MM451/MM551
Four Channel with Commutator - MM454/MM554
Six Channel - AM2009/AM2009C
TTL/DTL Compatible MOS
Eight Channel MUX - AM3705/AM3705C
TTL/DTL Compatible J·FET
)
DualDPST
Dual SPST
Dual DPDT (Diff)
SPOT (Diff)
.
AH0100/AH0100c Senes
......
»
~
o
o
...&
High Level Compatible J·FET
DPST - AH2114/ AH2114C
CD
(')
Ultra High Speed J-FET
±10V; 30n - AM1000
±15V; 50n - AM 1001
±10V; lOon - AM1002
N·Channel Discrete J·FET Switches
5 Ohm - 2N5432·
7 Ohm - 2N5433
10 Ohm - 2N5434
Analog Switch Drivers
TTL Dual Level Translator - DM7800/DM8800
TTL Dual High Speed Translator - DH0034/
DH0034C
Analog Comparator/Level Translator - LM 111
Series
Sample and Hold Circuits
Low Drift Precision - LH0023/LHOO23C
High Speed - LH0043/LH0043C
Plus a complete line of amplifiers, comparators, and
voltage regulators.
6·11
/I)
Q)
'':
Analog Switches
Q)
en
o
o
AH0120/ AH0130/ AH0140/ AH0150/ AH0160
series analog switches
.......
«
general description
CD
::I:
o
LO
o
::I:
«
.......
o
'It
o
::I:
«
The AH0100 series represents a complete family
of junction FET analog switches. The inherent
flexibility of the family allows the designer to
tailor the device selection to the particular application. Switch configurations available include dual
DPST, dual SPST, DPDT, and SPDT. r d,(ON) ranges
from 10 ohms through 100 ohms. The series is
available in both 14 lead flat pack and 14 lead
cavity DIP.
features
.......
o
•
TTLlDTL and RTL compatible logic inputs
o
•
Up to 20V p-p analog input signal
•
«
rds(ON) less than 10n .(AH0140, AH0141,
AH0145, AH0146)
.......
•
Analog signals in excess of 1 MHz
N
logic and connection diagrams
....
M
::I:
o
5
::I:
•
"OFF" power less than 1 mW
•
Gate to drain bleed resistors eliminated
•
Fast switching, tON is typically .4/.ls, tOFF is
1.0/.ls
Operation from standard op amp supply voltages, ±15V, available (AH0150/AH0160 series)
•
•
Pin compatible with the popular DG 100 series.
The AH0100 series is designed to fulfill a wide
variety of analog switching applications including
commutators, multiplexers, D/A converters, sample
and hold circuits, and modulators/demodulators.
The AH0100 series is guaranteed over the temperature range _55°C to +125°C; whereas, the
AHOl OOC series is guaranteed over the temperature
range _25°C to +85°C.
DUAL SPST
DUAL DPST
«
"----+--+--'-o'w,
sw,
.w,
,,, ......----:~---'I-':O ••'
:
"
,
0-'-+-----0""";
"-----+--+-""<>.w,
I
,I
---------....11
HIGH LEVEL (flOVI
HIGH LEVEL (±lOV)
MEDIUM LEVEL (±7.5VI
AH0140 (l0n)
AH0129 (30.11)
AH0141 (lom
AH0133 (30.111
AH0153 (l5n)
AHOl54 (50n)
AH0126 (80nl
AH0134
·
·
",
"
.:....
,
I
)/
I
+
___ oJ
.A'.
,
,
/"
,
,
s
,
sw,
o-!-+------~~~-------r~~,
sw,
&"---+-'0'"
sw,
'
:
",0-+--1
:,
I
---------....1
SWlTCH STATES ARE FOR
V,N , - LOGIC "1"INPUT AND
II'N2" 2.S118IAS
bOO
V~(£NAaLE)
!"
HIGH LEVEL (±lOV)
MEDIUM LEVEL (±7.5)
HIGH LEVEL (±10V)
MEDIUM LEVEL (±7.5vl
AH0145 (10.11)
AH0163 (15.111
AH0139 (30m
AH0164 (son)
AH0146 (lom
AH0144 (30fl:)
AHQ143 (80ni
AH0162 (50n!
AH0142 (80m
Order Number AHOXXXD
See Package 2
6-12
AH0152 (50m
SPOT (Diff)
y"
,,...
AH01S1115m
(son)
DPDT (Diff)
·..
MEDIUM LEVEL (±7.6VI
Order Number AHOXXXF
See Package 26
AH0161 (15£1)
l>
...J:
o
absolute maximum ratings
N
High
Level
o
Medium
Level
"l>
J:
36V
34V
Total Supply Voltage (V+ - V-)
Analog Signal Voltage (V+ - V A or V A - V-)
30V
25V
25V
Positive Supply Voltage to Reference (V+ - V R)
25V
Negative Supply Voltage to Reference (V R - V-)
22V
22V
25V
Positive Supply Voltage to Input (V+ - V IN )
25V
±6V
±6V
Input Voltage to Reference (V IN - V R)
±6V
±6V
Differential Input Voltage (VIN - V IN2 )
Input Current, Any Terminal
30mA
30mA
Power Dissipation
See Curve
_55°C to +125°C
Operating Temperature Range AH0100 Series
O°C to +85°C
AH0100C Series
-65°C to +150°C
Storage Temperature Range.
Lead Temperature (Soldering, 10 sec)
300°C
g
Co.)
o
"l>
J:
g
~
o
"-
l>
J:
...
o
U1
o
electrical characteristics
DEVICE TYPE
PARAMETER
SYMBOL
"l>
J:
for "HIGH LEVEL" Switches (Note 1)
DUAL
DPDT
SPOT
OPST
SPST
10lFFI
10lFFI
UNITS
v+ = 12.0V, v- = -lS.0V. VR '" D.DV
Logic "1"
Input Current
'INION)
All Circuits
Note 2
TA = 2SoC
Over Temp. RangP
Logic "0"
Input Current
IINtOFFl
All Circuits
NotB 2
TA "" 2SoC
Over Temp. Range
'+(ONI
All Circuits
One Driver ON Note 2
TA "" 2SoC
Over Temp. Range
'-(ON I
All Circuits
One Driver ON Note 2
Positive SupplV Current
Switch ON
Negative Supply
Current Switch ON
Reference Input
(Enable) ON Current
All Circuits
IRION)
TA
ZSoC
TYP
MAX
2.0
60
120
.01
~A
~A
2.2
3.0
3.3
rnA
rnA
-1.0
-1.8
2.0
rnA
rnA
One Driver ON Note 2
-1.0
-1.4
rnA
rnA
1.0
10
25
~A
-1.6
'+(OFFI
All Circuits
V IN1 = V 1N2 '" O.BV
T A :: 25°C
Over Temp. Range
Negative Supply
Current Switch OFF
I-(OFF)
All Circuits
V IN1 '" V 1N2 = O.BV
T A '" 25°C
Over Temp. Range
-1.0
-10
~A
25
~A
Reference Input
(Enable) OFF Current
IR(OFF)
All Circuits
V IN1 '" V IN2 = O.BV
T.·2s"C
-1.0
-10
-25
~A
Switch ON Resistance
rd$(ON)
AH0126
AH0134
AH0142
AH0143
Vo'" 10V
10=1 mA
TA = 2SoC
Over Temp. Range
45
80
150
Switch ON Resistance
rds(ON)
AH0129
AH0133
AH0139
AH0144
Vo = 10V
10= 1 mA
TA = 25°C
Over Temp. Range
25
30
60
AH0146
Vo == l0V
IF = 1 mA
TA '" 2SoC
Over Temp. Range
8
10
20
n
n
n
n
n
n
Vo=Vs=-10V
TA = 25°C
Over Temp. Range
1
100
nA
nA
1
100
nA
nA
rdstON)
Driver Leakage Current
(10 + IsloN
Switch Leakage
Current
IStOFFIOR
IOtOFFI
Switch Leakage
Current
Switch TUrn·ON Time
AH0140
AH0141
AHQ145
All Circuits
Over Temp. Range
.01
AH0134
AH0133
AH0142
AH0139
AH0143
AH0144
Vos == ±20V
TA '" 2SoC
Over Temp. Range
0.8
AH0129
IStOFFIOR
IOIOFF)
AH0140
AH0141
AH014S
AHOl46
Vos'" ±20V
TA '" 2SoC
Over Temp. Range
4
tON
AH0126
AH0129
AH0134
AH0133
AH0142
AH0139
AHQ143
AH0144
See Test Circuit
VA:: ±10V
TA=2SoC
Switch Turn·ON Time
tON
AH0140
AH0141
AH014S
AH0146
See Test Circuit
TA=2SoC
VA = ±10V
Switch Turn·OFF Time
tOFF
AH0126
AH0129
AHOl34
AH0142
AH0133
AHQ139
AH0143
AH0144
Switch TUrn·OF F Time
tOFF
AH0126
AH0140
AH0141
AH0145
AH0146
See Test Circuit
VA = ±10V
TA= 2SoC
See Test Circuit
V A =±10V
TA '" 2SoC
i"
~A
T,6,= 2SOC
Over Temp. Range
=
.
en
CD
~A
.1
2.0
Over Temp. Range
0)
o
Positive Supply
Current Switch OFF
Switch ON Resistance
...
o
LIMITS
CONDITIONS
DUAL
III
~A
~A
10
1.0
"A
nA
0.5
0.8
~s
0.8
1.0
~s
0.9
1.6
~s
1.1
2.5
~s
Note 1: Unless otherwise specified these limits apply for -5SoC to +12SoC for the AH0100 series and -25°C to +8SoC for the
AH0100C series. All typical values are for T A = 25°C.
Note 2: For the OPST and Dual OPST, the ON condition is for VIN = 2.SV; the OFF condition is for VIN = O.8V. For the
differential switches and SWl and 2 ON, VIN2 = 2.5V, VINl = 3.0V. For SW3 and 4 ON, VIN2 = 2.SV, VINl = 2.0V.
6·13
III
G)
';:
electrical characteristics
G)
(JJ
o
CD
.o
for "MEDIUM LEVEL" Switches (Note 1)
DEVICE TYPE
PARAMETER
SYMBOL
J:
«
DUAL
DPST
DUAL
SPST
DUAL
DPOT
SPOT
(DIFF)
UNITS
y+ =+15.0V, V-=-15V, V R =OV
Logic "1"
Input Current
tIN(ON)
All Circuits
Note 2
TA = 25°C
Over Temp. Range
Logic "0"
Input Current
IINIOFFI
All Circuits
Note 2
T A "' 25°C
Over Temp. Range
J:
Positive Supply
Current Switch ON
I+(ONI
All Circuits
One Driver ON Note 2
T A '" 25°C
Over Temp. Range
........
Negative Supply
Current Switch ON
'-(oNI
All Circuits
One Driver ON Note 2
........
oIt)
.o
«
o
~
.o
Reference Input
(Enable) ON Current
-1.8
rnA
rnA
2.0
V IN1
V IN2 '" O.BV
T A '" 25°C
Over Temp. Range
-1.0
AH016l
Vo '" 7.5V
10 '" 1 mA
TA '" 25°C
Over Temp. Range
AH0162
Vo" 7.5V
10'" 1 mA
~e; ~!:~~Range
Reference Input
OF F Current
i RIOFF )
Switch ON Resistance
fdslaNI
AH0153
AH0151
AH0163
Switch ON Resistance
rdslaNI
AH0154
AH0152
AH0164
....
Driver Leakage Current
(10
J:
Switch Leakage
Current
10lOFFI OR
ISIOFFI
AH0153
AH0151
AH0163
AH0161
Vos '" ±15V
Switch Leakage
Current
iOIOFF) OR
is(OFFI
AH0154
AH0152
AH0164
AH0162
Vos '" ±15.0V
Switch Turn-ON Time
tON
AH0153
AH0151
AH0163
AH0161
«
-1.0
Over Temp. Range
All Circuits
!Enable)
+ IS)ON
rnA
rnA
-1.0
I-IOFF)
N
3.0
3.3
T A '" 25°C
Over Temp. Range
Negative Supply
Current Switch OFF
o
2.2
V IN1 '" V IN2 '" O.BV
........
o
pA
pA
All Circuits
V IN1
All Circuits
=
00.
Vo '" Vs '" -7.5V
-1.6
rnA
rnA
10
25
pA
-10
25
pA
-10
25
pA
pA
10
15
30
45
50
100
n
n
n
n
2
500
oA
oA
.01
TA '" 25°C
Over Temp. Range
TA~25°c
pA
pA
0.1
2
.01
V 1N2 = O.SV
All Circuits
J:
60
120
1.0
I+(OFFI
«
........
20
T A = 25°C
Over Temp. Range
J:
o
M
.o
MAX
T A'= 25°C
Over Temp. Range
One Driver ON Note 2
Positive Supply
Current Switch OFF
«
T A =25°C
TVP
-1.0
All Circuits
IA(ON)
LIMITS
CONDITIONS
5
-1.4
pA
pA
10
1.0
oA
pA
1.0
2.0
200
oA
oA
See Test Circuit
VA "'±7.5V
TA '" 25°C
OB
1.0
P'
0.5
O.B
"'
Over Temp. Range
T A "'25°C
Over Temp. Range
Switch Turn-ON Time
tON
AH0154
AH0152
AH0164
AH0162
See Test Circuit
VA "'±7.5V
TA = 25°C
Switch Turn-OFF Time
tOFF
AH0153
AH0151
AH0163
AH0161
See Test Circuit
VA "'±7.5V
T A =25°C
1.1
2.5
P'
AH0162
See Test Circuit
V A =±7.5V
TA '" 25°C
0.9
1.5
P'
Switch Turn-OFF Time
tOFF
AH0154
AH0152
AH0164
Note 1: Unless otherwise specified these limits apply for -55°C to +125°C for the AH0100 series and -25°C to +8SoC for the
AH0100C series. All typical values are for T A = 25° C.
Note 2: For the DPST and Dual DPST, the ON condition is for VIN = 2.5V; the OFF condition is for VIN = O.8V. For the
differential switches and SWI and 2 ON, VIN2 = 2.5V, VINI = 3.0V. For SW3 and 4 ON, VIN2 = 2.5V, VINI = 2.0V.
6·14
»
l:
9
typical performance characteristics
N
ON Supply Current
Power Di!i$ipation
vs Temperature
vs Temperature
100
Z.4
.
500
co
~ 400
~
""'-
JOO
.....
;;( 2.0
.§
~ 1.6
'"
~
I'-.
~
'"
~ 200
~ 0.8
~ 0.4
l:
~
10
~
- I- ~tON)
~
o
...&
Co)
Vo'" lOV
A~01J~
.......
AH0140, AHOI4~
I-AHOl45, AHOI46_
l:
10 ::;, rnA
V+ '" +12V
Z5
50
15
100
TEMPERATURE (OC)
e15 -50 -25
IZ5
0
Z5
50
15 100 IZ5
0
»
o
...&
~
111
I
o
I I I
v- '" -lav
1.0
-15 -50 -Z5
o
AHOIZ9, AH01JJ,
~
~
z
»
AHOl4J, AHOl4Z,
AHOIZ6, AHOIJ4
V
u
I-IONI
~
100
t==
-
1.2
.......
~
t- ~ON)
o
r dSION} vs Temperatur.
AH0120 thru AH0140 Series
Z5
50
.......
»
15 100 125
l:
TEMPERATURE ("C)
TEMPERATURE (OC)
o
...&
Leakage Current vs Temperature
'ds(ON) vs Temperature
AH0150/AH0160 Series
AH0120, AH0130, & AH0140
1000
100
1000
V' - IZ.OV
V- • -IB.OV
Yo OR vs" ±10V
f- ~ ~ AHDI .., AHDI5Z- l -
AHOl41,
CO- AHOI45, AHOl46
AHOl5J, AHDI5I,_
AHOl6J, AHDI6r=
~
g
y+ '" +15V
V-· -15V
=
.E 1.0
I I I
1.0
-15 -50 -Z5 0 Z5 50 15 100 IZ5
TEMPERATURE (OC)
=
.!!!!l!
.......
~r '"+15V
V- - -15V
l:
Vo OR Vs - ±1.5V
o
»
o
...&
~
100
0)
,:::AHOI5J, AHOl51,
=AHOI6J, AH~
......
I-
Vo 7.5V
Is =1 mA
"..s
~AHOI48,
I-- I-- _ A H T r t t--
U1
Leakage CUrrent vs Temperature
AH0150 & AH0160
o
~
C/)
if
§
EXCEPT AHOI48, AHOI'I,
AHDI", AHDI48
-
0.1
(1)
AHOI .., AHOI5Z,AHOI64, AHOI6Z
1.0
~
(D'
en
0.1
Z5
45
65
85
105
TEMPERATURE (OC)
IZ5
25
45
lZ5
65
85
105
TEMPERATURE (OC)
Differential Switch Input
Threshold vs Temperature
Single Ended Switch Input
Threshold vs Temperature
I
Z.O
\\')
~~
~L
~
~L SW1TCHES ON~~
SWITCHES DN;>6;~
- IV IN1
ALL
-
I- ALL SWITCHES OFF
SW1~CHE~ O~ ~
i""" ~
~ O.3~
V1N2 1
VA" OV
V+-V-::3DV
o
-15 -50 -Z5 0 Z5 50 15 100 IZ5
TEMPERATURE 1°C)
-15 -50 -Z5 0 Z5 50 15 100 IZ5
TEMPERATURE (OC)
switching time test circuits
Differential Input
Single Ended Input
rL
uv
"
V'N,~2.5Y
z.sv
'5V
'.
I
'" I
I
+V'"
~!t
I
I
I
I
I
SWl&2
OUTl'UT
V'N1
V'N.-2.5V
L,.,---4-4-'
... .,
OUTPUT
.....
v",
i'--t
I
I
I
I
I
I
I
ov
OUTPUT
.....
OUTl'UT
6·15
III
CD
'':;:
CD
applications information
en
1, INPUT LOGIC COMPATIBILITY
A.
Voltage Considerations
In general, the AH0100 series is compatible with
most DTL, TTL, and RTL logic families. The ON·
input threshold is determined by the V BE of the
input transistor plus the V f of the diode in the
emitter leg, plus I x R1, plus VR' At room
temperature and V R = OV, the nominal ON threshold is:0.7V+0.7V+0.2V,= 1.6V.Over temperature
and manufacturing tolerances, the threshold may
be as high as 2.5V and as low as 0.8V. The rules
for proper operation are:
V IN - V R 2: 2.5V All switches ON
V IN - V R :::; 0.8V All switches OFF
terminal will open all switches. The V R (ENABLE)
signal must be capable of rising to within 0.8Vof
VINION) in the OFF state and of sinking IRION)
milliamps in the ON state (at VINION) - V R
2.5V). The V R terminal can be driven from most
TTL and DTL gates.
>
3. DIFFERENTIAL INPUT CONSIDERATIONS
The differential switch driver is essentially a differential amplifier. The input requirements for proper
operation are:
IV IN1 - V IN2 1::::0.3V
2.5 <::: (V IN1 or V IN2) - V R <::: 5V
The differential driver may be furnished by a DC
level as shown below. The level may be derived
from a voltage divider to V+ or the 5V Vee of
the DTL logic. In order to assure proper operation,
the divider should be "stiff" with respect to IIN2'
Bypassing Rl with a 0.1 JlF disc capacitor will
prevent degradation of tON and tOFF'
'.
B. Input Current Considerations
IINION), the current drawn by the driver with
V IN = 2.5V is typically 20 JlA at 25°C and is guaranteed less than 120 JlA over temperature. DTL,
such as the DM930 series can supply 180 JlA at
logic "1" voltages in excess of 2.5V. TTL output
levels are comparable at 400 JlA. The DTL and
TTL can drive the AH0100 series directly. However, at low temperature, DC noise margin in the
logic "1" state is eroded with DTL. A pull-up resistor of 10 kn is recommended when using DTL
over military temperature range.
Alternatively, the differential driver may be driven
from a TTL flip·flop or inverter.
If more than one driver is to be driven by a DM930
series (6K) gate, an external pull-up resistor should
be added. The value is given by:
11
Rp = N _ 1 for N
>2
where:
Rp = value of the pull-up resistor in kn
Connection of almA current source between V R
and V- will allow operation over a ±1 OV common
mode range. Differential input voltage must be less
than the 6V breakdown, and input threshold of
2.5V and 300mV differential overdrive still prevail.
N = number of drivers.
C. Input Slew Rate
>lDVI
CMRAN6E
The slew rate of the logic input must be in excess
of 0.3V IJls in order to assure proper operation of
the analog switch. DTL, TTL, and RTL output
rise times are far in excess of the minimum slew
rate requirements. Discrete logic designs, however,
should include consideration of input rise time.
2. ENABLE CONTROL
The application of a positive signal at the V R
6-16
l>
::I:
The rules for operating the AH0100 series at
supply voltages other than those specified essen·
tially breakdown into OFF and ON considerations.
The OFF considerations are dictated by the maxi·
mum negative swing of the analog signal and the
pinch off of the JFET switch. In the OFF state,
the gate of the FET is at V- + V BE + VSAT or
about 1.0V above the V- potential. The maximum
V p of the FET switches is 7V. The most negative
analog voltage. V A, swing which can be accomodated for any given supply voltage is:
IV A I::; Iv-I- V p
-
V BE
-
VSAT or
....oN
V A::; V+ - 2.0V or V+ ~ VA + 2.0V
4. ANALOG VOLTAGE CONSIDERATIONS
o
For the standard high level switches, V A ~ 12 2.0V ~ +10V.
......
l>
::I:
o
....
w
5. SWITCHING TRANSIENTS
o
Due to charge stored in the gate-to-source and
gate-to-drain capacitances of the FET switch, transients may appear in the output during switching.
This is particularly true during the OFF to ON
transition. The magnitude and duration of the
transient may be minimized by making source
and load impedance levels as small as practical.
......
l>
::I:
o
....
~
o
......
l>
::I:
IV AI::;IV-I-S.O or IV-I:;:' IV AI+S.OV
For the standard high level switches, V A <1- lSi
+S ~ -10V. The value for V+ is dictated-by the
maximum positive swing of the analog input voltage. Essentially the collector to base junction of
the turn-on PNP must remain reversed biased for
all positive value of analog input voltage. The base
of the PNP is at V+ - VSAT - V BE or V+ - 1.0V.
The PNP's collector base junction should have at
least 1.0V reverse bias. Hence, the most positive
analog voltage swing which may be accommodated
for a given value of V+ is:
VA ::;v+ - VSAT - V BE
-
1.0V or
o....
o
......
U1
l>
::I:
....o
en
o
Furthermore, transients may be minimized by
operating the switches in the differential mode;
i.e., the charge delivered to the load during the
ON to OFF transition is, to a large extent, cancelled by the OF F to ON transition.
CJ)
CD
::::!.
CD
!fj
typical applications
Programmable One Amp Power Supply
r:: I
-;:HoWll
141:
I,
8
,.-_ _ _ _-=.:-a
+j!iV
24.9K
~7-----------~~--.-~
+-_____-.::8.:.1_+__+_..!~
...... - ----;;-H~,
49,9K 1%
141
I,
lOOK 1%
I
1
1
1
I
1
+15V
4
lOOK 1%
12.4K 1%
I
1
1
1
r
10K
11
"
12
-'5V~
ZERO
ADJUST
10K
1- - - l
I
~---------'
HUOTt BCD INPUTS
DISABLE
6-17
en
CD
';:
typical applications (con't)
CD
tn
o
Four to Ten Bit 0 to A Converter (4 Bits Shown I
U)
~
o
:t
c(
ANALOG
.......
o
II)
OUTPUT
RIDIC
"
5
20K
.---1f--.....- - f - -.....- - t - -......--o',..
:t
c(
.......
o
~
~
o
:t
c(
z·'
.......
SettingTime:1.DJ.ls
AccurllCv:O.2%
*Note: All resistorsare 0.1%
T'
o
(W)
~
o
:t
Four Channel Differential Transducer Commutator
c(
.......
o
N
TRAN"~~~: {:
o
o
~
:t
TRANSDUCER {
c(
NO.2
0
8~;-~--:-1,
~ I.
.1
,,1.,...(.
[,
I:
I
a-1':"--i-...;.:.'+....-..JVv.-.....:.j
.",;;';-~1:
I,
'RA"""'{OOS I
NO.3
z
: I
I
I,
I
~
TRANSDUCER'
NO.4
{ o-4-.a--r
I:
5
~:I
, - "I'
... o-!!l
'I
I
I
I
3
I"
~
~
I
I
4
X
Gain: 22
Commutation Rate: 500 kHz
I"
4 Cross Point Analog Switch
ALL CHANNEL
BLANKING
,-,
~r-+-~~'
I
I
o
1'''
I
"':..---,~
o-~4-.....-f-~-4-1~~-,
f--o ..
I,
,'L_
DM74154
I
4T016
,L __
,,1-+-:-..,'1
4
DECODER
I
I
1'''
I
I
I
L,-, - ,
Switching Time: BOOns
"ON" Resistance: 45n
"OFF" Resistance: 10· on
6-18
l>
::t:
o....
N
o
........
typical applications (con't)
Delta Measurement System for Automatic Linear Circuit Tester
l>
::t:
o....
w
o
........
,----------,
I
I
I
I
I
~~~I;~~~::~~E
I,
1
I
I
l>
I
.1
"
I
I
I
L
_ I
L _________ ~J"
-....
+
paramet~1
o
....
~
EOOT
1
____ J
_
1'1 "f
-15V
o
~
........
l>
::t:
t15V
o....
UI
o
........
Analog Itlpllt Rall!W -7,5V
EOUT = 10K (Analog Input 2 - AnaloQ Input 1)
Error Rate: 0.01% F.S./sec
Note: S1 must be open for SOps min to take first reading with IL = 50 rnA. Second reading is taken with S2 dosed.
With 51 and other set-lip lo[(:mg fUllctlons under computer control, svstem will measure lme and load regulation
(III voltage reglilatols, voltage galli, offset current, CMRR and PSRR on IJP amps as well as other clrt:uits requinng
meaSl.llement of the change of a
::t:
1
I
I
I
with the change of a forcing luncllol\
l>
::t:
o
....
0)
o
Precision Long Time Constant Integrator with Reset
c (tow LEAKAGE)
0.1
(J)
~F
(1)
~
CD'
1/1
,
lUOM
I
""""'q:t>- 'S
+..J
(TTL)
R(~;EL~
I
-
L
r
I _
..!1I01~
R
IHllll
""Nute: Vos adjusted to zero
1
-,.J -
v'
b
v-
ITTLI
Integration Internal: 111 sec
'"IntegratIOn Error: l[)IIIN
Reset Time: 30J-ls
Four Channel Commutator
ANALOG
INPUTS
rI_I-, rI-I-,
AH01,]
AH01S3
CHANNEL1~L---l-7-_ _ _-!""'"
CHANNEll 0
CHANNEL30
CHANNEl40
I
:
:
i
./ I
C)""'"":
I
:
I
I
i
''-11"1"--,-----+-+
I
I
I
I
L
"C s
CHANNEL
SELECT (TTl)
=
Polystyrene Dielectric
Analog Signal Range: 15 Vp·p
Sample Rate: 1.0 MHz
Acquisition Time: 25}.'s
Drift Rate: 0.5 mV/sec
6-19
(I)
Q)
.t:
~
schematic diagrams
o
...
CD
DUAL DPST and DUAL SPST
o
::t
«
.........
o
...
Ln
o
::t
«
'"
s,
.........
...oo
~
::t
«
.........
o
o
...
M
::t
«
""
.........
...oo
N
::t
«
'.
(ENABLE)
Note: Dotted line portions are not applicable
to the dual SPST.
DPDT (diff.l and SPOT (diff.)
'.. ""''----1----'
Note: Dotted line portions are not applicable
to the SPOT (differential).
6-20
Analog Switches
AH2114/AH2114C DPST analog switch
general description
The AH2ll4 is a DPST analog switch circuit comprised of two junction FET switches and their
associated driver. The AH2ll4 is designed to fulfill
a wide variety of high level analog switching applications including multiplexers, A to D Converters,
integrators, and choppers_
•
Large output voltage swing, typically ±10V
•
Powered from standard op-amp supply voltages
of ±15V
•
Input signals in excess of 1 MHz
features
The AH2ll4 is guaranteed over the temperature
range -55°C to +125°C whereas the AH2ll4C is
guaranteed over the temperature range O°C to
+85°C_
•
Low ON resistance, typically 750
• High OFF resistance, typically 1011 0
• Turn-ON and turn-OFF times typically 1 IlS
schematic and connection diagrams
Metal Can Package
C"C11I1I1S11oJln
WllhVs",LolI"''''''
"
10.8K
".
"
Order Number AH2114G
or AH2114CG
See Package 25
ac test circuit and waveforms
VOUT!
"
FIGURE 1_
FIGURE 2_
(.)
...
~
absolute maximum ratings
N
::t
«
Vplus Supply Voltage
Vminus Supply Voltage
Vplus-Vminus Differential Voltage
Logic Input Voltage
Power Dissipation
Operating Temperature Range
AH2114
AH2114C
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
"'-
......
~
N
::t
«
electrical characteristics
PARAMETER
Static Drain·Source
"On" Resistance
+25V
-25V
40V
25V
1.36W
-55°C to +125°C
O°C to +85°C
-65°C to +125°C
300°C
(Notes 1 and 2)
CONDITIONS
AH2114
MIN
TYP
75
10 = 1.0 mA, VGS = OV, TA = 25°C
10 = 1.0 mA, VGS = OV
0.2
AH2114C
MAX
MIN
TYP
75
100
150
MAX
UNITS
n
n
125
160
Drain·Gate
Leakage Current
VOS= 20V, VGs=-7V, TA =25°C
FET Gate·Source
Breakdown Voltage
IG =1.0 IlA
Vos = OV
Drain·Gate
Capacitance
VOG = 20V, Is = 0
f = 1.0 MHz, T A = 25°C
4.0
5.0
4.0
5.0
pF
Source·Gate
Capacitance
VOG = 20V, 10 = 0
f= 1.0 MHz, TA = 25°C
4.0
5.0
4.0
5.0
pF
Input 1 Turn-ON Time
V'N1 = 10V, T A = 25°C
(See Figure 1)
3.5
Input 2 Turn-ON Time V'N2 = 10V, TA = 25°C
(See Figure 1)
1.2
1.5
1.2
1.2
IlS
Input 1 Turn-OFF Time V'N1 = 10V, T A = 25°C
(See Figure 1)
0.6
0.75
0.6
0.75
IlS
1.0
60
35
Input 2 Turn·OFF Time V'N2 = 10V, TA = 25°C
(See Figure 1)
0.2
5.0
60
nA
nA
V
35
50
60
3.5
80
50
60
ns
80
ns
DC Voltage Range
TA =25°C
(See Figure 2)
±9.0
±10.0
±9.0
±10.0
V
AC Voltage Range
TA = 25°C
(See Figure 2)
±9.0
±10.0
±9.0
±10.0
V
Note 1: Unless otherwise specified these specifications apply for pin 12 connected to +15V pin 2 connected to -15V -55°C
I
to +125°C for the AH2114, and O°C to +85°C for the AH2114C.
Note 2: All typical values are for T A = 2/f C.
Note 3: Derate linearly at l00°C/W above +2/fC.
6·22
i
»
s:
Analog Switches
~
o
o
o
»
s:
AM1000,AM1001,AM1002 silicon N-channel
high speed analog switch
~
o
o
~
»
s:
~
o
o
general description
The AMl 000 series are junction FET integrated circuit analog switches. These devices commutate
faster and with less voltage spiking than any other
analog switch presently available. By comparison,
discrete JFET switches require elaborate drive circuits to obtain reasonable performance for high
toggle rates. Encapsulated in a four pin TO-72
package, these units require a minimum of circuit
board area. Switching transients are greatly reduced
by a monolithic integrated circuit process. The
resulting analog switch device provides the following features:
•
•
Low ON Resistance
High Analog Signal Frequency
•
•
•
•
N
4 MHz
250pA
±15V
High Toggle Rate
Low Leakage Cu rrent
Large Analog Signal Swing
Break Before Make Action
The AM 1000 series of analog switches are particularly suitable for the following applications:
• High Speed Commutators
• Multiplexers
• Sample and Hold Circuits
• Reset Switching
• Video Switching
30n
lOa MHz
schematic diagram
equivalent circuit
TO-72 Package
~NU~~~~~4
OII1V
V
£
AN~~~~
v.~
2
3
TDPVIEW
Order Number AM1000H,
AM1001H or AM1002H
See Package 22
typical applications
±10 Volt SWing Analog Switch 0.5% Accuracy
±15 Volt SWing Analog Switch
r--"'iiOo]
ANALOG
INPUTS
[o---:;o---<)--,+CI--o---o ~~~~:;
r--'M'Oail
ANI~~~; 2~ :~~g:
I
•
I
CHANNEL
.K
SELECT
INPUT
-10V
BIAS
6-23
N
o
o
....
absolute maximum ratings
~
«
....
AM100l
AM1000
AM1002
+50V
+50V
-50V
+50V
+40V
+40V
-40V
+40V
VIN (Note 1)
V OUT (Note 1)
VORIVE (Note 1)
o
o
....
V B1AS (Note 11
~
Power Dissipation @ T A = 2SoC
300mW
1.7mW/oC
150mW
6mWtC
_55°C to +150°C
Linear Derating Factor
Power Dissipation @Tc "" 12SoC
Linear Derating Factor
Maximum Junction Operating Temperature
Storage Temperature
lead Temperature (Solding, TO sec)
+200°C
+300°C
electrical characteristics
«
ON CHARACTERISTICS (Note 21
o
PARAMETER
o
o
....
~
«
MIN
TYP
MAX
UNITS
RON
VORIVE:: +15V, V B1AS =: -15V
liN = 1 rnA. VOUT "" OV
CONDITION
AM100l
20
40
50
!2
RON
VORIVE
+10V. VelAS = -lOV
AM 1000
20
20
25
50
30
100
!2
=:
liN'" 1 rnA, VOUT :::: OV
AM 1002
n
OFF CHARACTERISTICS
PARAMETER
AM1000
AM100l
CONDITION
MIN
VORIVE == -20V, V B1AS = -lOV
VIN = - lOV. VOUT :::: +10V
T A '" +2SoC
T A " +12SoC
IOUT(OFFJ
=: -20V. V S1AS :: -lOV
+10V, VOUT "" -lOV
TA = +2SoC
T A = +12SoC
AM1002
TYP
MAX
.05
.025
.05
UNITS
TYP
MAX
.25
.25
0.5
0.2
1
1
~A
.25
.25
0.5
0.2
1
1
~A
TYP
MAX
UNITS
5
10
mA
MIN
nA
VORIVE
lOUT (OFF)
VIN
=
.05
nA
DRIVE CHARACTERISTICS (Note 3)
PARAMETER
CONDITION
VORIVE '" -20V, VBIAS '" -10V
VIN = ±10V, V OUT '" ±lOV
'ORIVE
(Switch OFF)
MIN
AM1000, 1001, 1002
SWITCHING CHARACTERISTICS
PARAMETER
CONDITION
'ON
See Switching Time
Test Circuit
tOFF
AM1000
MAX
AM100l
MAX
AM1002
MAX
UNITS
100
150
200
ns
100
100
100
ns
Note 1: The maximum voltage ratings may be applied between any pin or pins simultaneously. Power dissipation may be
exceeded in some modes if the voltage pulse exceeds 10 ms. Normal operation will not cause excessive power dissipation even
in a "DC" switching application.
Note 2: All parameters are measured with external silicon diodes. See electrical connection diagram for proper diode placement.
Note 3: IBIAS (Switch OFF) is equal to IDRIVE (Switch OFF). I(BIAS) (Switch ON), is equal to external diode leakage.
Note 4: Rise and fall times of VDRIVE shall be 15 ns maximum for switching time testing.
switching time test circuit and waveforms
r----OU.T.i
I
r-
~ov
I
'lOUT
~
1
'Y
I
I
.
•
I
•
90% I
1M
I
,Nk----...J
:
,
VOUT
''
,
,,
:
VDRIVE
-'lOUT
'
''
,
_lOll
:,
111914
,
_.w
IIDRIVJ1fL:::
6-24
I""-i
-!
r-
-21V
Iof•
~
3i:
Analog Switches
N
o
o
CD
......
~
AM2009/AM2009C six channel MOS multiplex switch
3i:
N
general description
The AM2009/AM2009C is a six channel multiplex
switch constructed on a single silicon chip using low
threshold P-Channel MOS process. The gate of each
MOS device is protected by a diode circuit.
CD
n
The AM2009/AM2009C is designed for applications
such as time division multiplexing of analog or
digital signals. Switching speeds are primarly determined by conditions external to the device such
as signal source impedance, capacitive loading and
the total number of channels used in parallel.
features
•
•
o
o
• ±10V typical large analog voltage range
• Zero inherent offset voltage
• Normally off with zero gate voltage
150 ohms typical low "ON" resistance
100 pA typical low "OFF" leakage
schematic diagram
BULK
01
14
-r-
0'
03
o.
13
+
~~
~~
,
~~
~
~~
J"t--
1::,...
~
12
1:,...
~
~
11
p..o
SOURCE
1:.05
r-
10
1:.06
po--
9
.L.:
,
1
Gl
GZ
3
G3
•
5
G4
G5
6
G6
Order Number AM2009D or AM2009CD
Order Number AM2009F or AM2009CF
See Package 2
Sea Package 26
typical applications
32 Channal MUX
TTL Compatible 6 Channel MUX
INPUT
ANALOG INPUTS
CHANNELS
AMZ009!AM2009C
ANALOG
OUTPUT
ANALOG
INPUTS
OUTPUT
TTLl
ADDRESS SELECT
1-6
ADDRESS SELECT
1-12
6-25
(.)
en
o
o
absolute maximum ratings
N
(V BULK = OV)
Voltage on Any Source or Drain
Voltage on Any Gate
Positive Voltage on Any Pin
Source or Drain Current
Gate Current (forward direction of zener clamp)
:?!
«
.......
en
o
o
N
electrical characteristics
:?!
«
-30V
-35V
+0.3V
50mA
0.1 mA
Total Power Dissipation (at T A
'"
25°C)
Power Dissipation - each gate circuit
Operating Temperature Range AM2009
AM2009C
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
900mW
150mW
_55°C to +125°C
_25°C to +85°C
_65°C to +150°C
300'C
(Note 1)
LIMITS
PARAMETER
UNITS
CONDITIONS
MIN
TYP
-1.0
MAX
Threshold Voltage
V GS = Vos. los = -1/lA
DC ON Resistance
V Gs " -20V, los" -100 IlA,
T A = 25°C
150
250
II
DC ON Resistance
VGS '" -lOY, VSB = -20V.
los" -100IlA, T A " 25'C
500
1250
\I
DC ON Resistance
V GS " -20V, los" -100 IlA
325
\I
DC ON Resistance
VGS = -lOY, VSB = -20V,
los" -100 IlA
Gate Leakage
VGs "'" -20V, Note 2
VGS = -20V, Note 2, T A
"'"
25°C
100
Input Leakage
V DS = -20V, Note 2
VDS = -20V, Note 2, TA
=
25°C
100
VSD = -20V, Note 2
VSD = -20V, Note 2, TA = 25'-'C
500
Output Leakage
Gate-Bulk Breakdown
Voltage
' GB ::,
Source-Drain Breakdown
Voltage
Drain-Source Breakdown
Voltage
-3.0
V
n
1500
1.0
IlA
pA
1.0
IlA
pA
3.0
IlA
pA
-35
V
' sD ""-lOI1A,V GD =O,
Note 2
-30
V
IDs=-10I1A, VGs=O,
Note 2
-30
-10 /lA, Note 2
V
Transconductance
4000
mhos
Gate Capacitance
Note 3, f
1 MHz
4.7
8
pF
Input Capacitance
Note 3, f -'" 1 MHz
4.6
8
pF
Output Capacitance
Note 3, f
20
pF
=
=
1 MHz
16
Note 1: Ratings apply over the specified temperature range and VaULK = 0, unless otherwise
specified_
Note 2: All other pins grounded_
Note 3: Capacitance measured on dual-in-line package between pin under measurement to all other
pins. Capacitances are guaranteed by design.
typical performance characteristics
"ON" Resistance vs Gate-toSource Voltage
§ 400
"ON" Resistance vs T
Temperature
i'f 'DO
:2
,f 300
Input Leakage Current vs
Temperature
I ....
~
'" f--i-+.-+I-fI~+--+_---:l
10'
F--1f'~~''1-
,'--'-...J....-.J._'--'-....L-I
-20
-15
VGs(VI
6-26
-10
-5
-50 -25
0
25
50
75100
TEMPERATURE ( C)
12!1
25
50
75
100
TEMPERATURE ( Cl
125
»
3:
Analog Switches
~
o
U'I
AM370S/ AM370SC 8-channel MOS analog multiplexer
general description
.......
The AM3705/AM3705C is an eight-channel MOS
analog multiplex switch. TTL compatible logic
inputs that require no level shifting or input
pull-up resistors and operation over a wide range
of supply voltages is obtained by constructing the
device with low threshold P-channel enhancement
MOS technology. To simplify external logic requirements, a one-of-eight decoder and an output
enable are included in the device.
......
o
U'I
(')
The AM3705/AM3705C is designed as a low cost
analog mUltiplex switch to fulfill a wide variety of
data acquisition and data distribution applications
including cross-point switching, MUX front ends
for AID converters, process controllers, automatic
test gear, programmable power supplies and other
military or industrial instrumentation applications.
TTLlDTL compatible input logic levels
Operation from standard +5V and -15V supplies
Wide analog voltage range - ±5V
One-of-eight decoder on chip
block diagram
3:
w
• Output enable control
• Low ON resistance - 150£2
• I nput gate protection
• Low leakage currents - 0.5 nA
Important design features include:
•
•
•
•
»
For information on other National analog switches,
see listing on last page of this data sheet.
connection diagram
(MIL-STD-806B)
Dual-In-Line and Flat Package
CHANNEL NO.'S
Lhhhhhhh
"
Z2
'"
V~
2
o DATA OUTPUT
1&
~
15
2'
"
OUTPUT
ENABLE
~
v••
Vm '
13
S, •
12
S,
S, •
11
S,
S, ,
10
S,
S, •
9
~
Order Number AM3705D
orAM370SCD
See Package 3
"'80th Vss lines are Internally connected; eIther
one or both may be used.
truth table
CHANNEL
LOGIC INPUTS
2°
2'
2'
OE
L
H
L
H
L
H
L
H
L
L
H
H
L
L
H
H
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
S.
X
X
X
L
OFF
ON
S,
5,
53
S,
55
5,
S,
typical applications
Buffered 8-Channel Multiplex, Sample and Hold
ANALOG
OUTPUT
''''''
(
,OJ
INPUTS
Wide I nput Range Analog Switch
"'",
INPUTS (
-AITAlDG
OUTPUT
CHANin
Hun
ITTU
"'Polystyrene Dielectric
Analog Signal Range: i5.0V
Acquisition Tima: 25 os
Analog Input Range: '25V
Slew Rato: 5.0V/lJs
Dnft Rate: 0.5 mY/sec
Aperture Time: 250 ns
6-27
absolute maximum ratings
Positive Voltage on Any Pin (Note 1)
Negative Voltage on Any Pin (Note 11
+O.3V
-3SV
±30mA
±0.1 mA
SOOmW
-SS'C to +12S'C
-2S'C to +8S'C
-6S'C to +lS0'C
300'C
Source to Drain Current
Logic I nput Current
Power Dissipation (Note 2)
Operating Temperature Range AM3705
AM370SC
Storage Temperature Range
Lead Temperature (Soldering, 10 secl
electrical characteristics
PARAMETER
(Note 3)
SYMBOL
CONDITIONS
ON Resistance
RON
V ,N 0 Vss; lOUT 0 100 ilA
ON Resistance
RON
V ,N 0 -SV; lOUT 0 -100ilA
ON Resistance
RON
V ,N 0 -SV; lOUT 0 -100ilA
AM3705
AM370SC
MIN
LIMITS
TYP
MAX
UNITS
80
2S0
!l
160
400
!l
400
400
!l
!l
T A =+125°C
TA "" +70°C
ON Resistance
RON
V ,N 0 +SV; Voo 0 -lSV;
lOUT 0 100ilA
100
!l
ON Resistance
RON
V ,N 0 OV, Voo 0 -15V,
lOUT 0 -100ilA
lS0
!l
ON Resistance
RON
V ,N 0 -5V; Voo 0 -15V;
lOUT 0 -100 pA
250
!l
OFF Resistance
ROFF
Output Leakage Current
I LO
I LO
I LO
AM3705
AM370SC
Data Input Leakage Current
Vss - V OUT = 15V
Vss - V OUT = 15V; TA '" 125°C
Vss - V OUT :::: 15V; TA =: 70c e
'LOI
Vss - VIN =: 15V
VSS-V'N 0 15V;TA 0 125'C
Vss - VIN = 15V; T A :::: 70 0 e
III
III
III
Vss - VLogicln =: 15V
Vss - V Logic In = 15V; TA =: 125°C
Vss - VL091C In == 15V; T A == 70 D e
Logic Input LOW Level
V ,L
Vss 0 +5.0V
logic Input LOW Level
Logic Input HIGH level
Logic Input HIGH Level
V ,L
V ,H
V ,H
Channel Switching Time-Positive
t+
Channel Switching Time-Ne'gative
t
'LOI
AM370S
AM370SC
'LOt
Logic Input Leakage Current
AM3705
AM3705C
-
Channel Separation
!l
10 10
Vss 0 +5.0V
l
0.5
150
35
0.1
25
0.5
.001
.05
.05
0.5
Voo
3.0
Vss - 2.0
10
500
500
nA
nA
nA
3.0
500
500
nA
nA
nA
1
10
10
pA
1.0
Vss - 4.0
3.5
Vss + 0.3
300
Switching Time
Test Circuit
I
IlA
ilA
V
V
V
V
ns
600
ns
f 01 kHz
62
dB
35
pF
Output Capacitance
Cdb
Vss - V OUT 0 0; f 0 1 MHz
Data Input Capacitance
C'"
Vss - VOIP 0 0; f 0 1 MHz
6.0
logic Input Capacitance
Co,
VSS-VLogicln=O;f= 1 MHz
6.0
Power DiSSipation
Po
Voo 0 -31V, Vss 0 OV
125
pF
pF
175
mW
Note 1: All voltages referenced to VSS.
Note 2: Rating applies for ambient temperatures to +250 C, derate Iinearly at 3.0 mW C for ambient temperatures above +25 0 C.
r
Note 3: Specifications apply for TA = 25"C, -24V ::: VDD ::: -20V, and +S.OV ::: VSS ::: +7.0V; unless otherwise specified
(all voltages are referenced to ground).
6·28
l>
s:
w
typical performance characteristics
ON Resistance vs Analog
Input Voltage
300
~ITElT 10ilT
250
_
;
V oo " -20V
Vss=+7V
400
TA =+25"C
lOUT'" -100/J.A
100
350
I I I I
1"-1"-1-
100
lI-
50
'OUT ",-10D/J.A
t--
Tl;WoiN~S
0' 150
V. NPUT
150
-3
-1 0 +1
+3
+5
+7
100
-; 150
rt1
100
0
25
50
TEMPERATURE
75 100 125
C11
.......
l>
s:w
25°C
=+5V
lOUT"" -100J.'A
"-
--
'\
'\
'-.,
"-
I
VOUT
.....
o
I
=
-S.OV-
C11
("')
~
~
Var -+S_jV
V OUT =
7V
-75 -50 -25
Output Leakage Current vs
Ambient Temperature
50
l'TI"I+ I
50
INPUT (VI
10'
-5V
"
=
Vss
100
II
o
-5
TA
250
Ti
;200
o
ON Resistance vs V DO
Supply Voltage
I IJ I I
hLlllJl-
Voo - -20V
Vss" +7V
300
TEST POINT--<
150
.....
ON Resistance vs
Ambient Temperature
-10
I"CI
-15
o.ov- r--
-20
-25
Voo SUPPl Y (V)
switching time test circuit
~VOUT Vss - 15V
TES~
/
V
25
50
100
75
125
TEMPERATURE eel
typical applications (con't.)
Differential Input MUX
16-Channel Commutator
IIN£RTING(
INPUT
CHANNElS
'01
CHANNEll
SELEniTTLI
'"'
IN\lERTING
INPUT
CHANNEtS
(
Voltage Gain: 200
Differential In!Jut Resistam;e: 1111011
CMRR: 11111 dB
In!Jut Current: 0.5 nA
'01
CLOCK
I~PUT
8-Channel Demultiplexer with Sample and Hold
A~ALOG
INPUT
Drift Rate:-21l mY/sec
6-29
(.)
It)
o,....
schematic diagram
M
~
«
........
It)
o
,....
M
~
«
analog switch data sheets
For specifications
on
other
Nat i 0 na I analog
switches and analog interface circuits, see the
following data sheets:
TTl/DTl Compatible J-FET
ANALOG SWITCH DRIVERS
Dual DPST
Dual SPST
Dual OPDT (Ditt)
TTL Dual Level Translator - DM7800/DM8800
TTL Dual High Speed Translator - DH0034/
DH0034C
Analog Comparator/Level Translator - LM111
SPOT (Diffl
I
.
t AH0100/AH01DOC Series
)
Series
MOS Analog Switches
High level Compatible J-FET
Dual Differential - MM450/MM550
Triple - MM455/MM555
Quad - MM452/MM552
Four Channel - MM451/MM551
Four Channel with Commutator - MM454/MM554
Six Channel - AM2009/AM2009C
DPST - AH2114iAH2114C
SAMPLE AND HOLD CIRCUITS
Ultra High Speed J-FET
±10V; 30n - ANI100D
±15V; son - AM1001
±10V; lOon -- AM1002
Low Drift Precision -- LH0023/LH0023C
High Speed - LH0043/LH0043C
TTLlDTL Compatible MOS
N-Chanoel Discrete J-FET Switches
DPDT - AH0014/AHQ014C
Quad SPST - AH0015/AH0015C
DPST -- AH0019iAHOOl9C
5 Ohm - 2N5432
7 Ohm - 2N5433
10 Ohm - 2N5434
6·30
Plus a complete line of amplifiers comparators
and voltage regulators.
s:s:
s:s:
ROM Character Generators
~~
NN
WN
00
Zz
MM4220N P/MM5220NP. MM4230NN/MM5230NN.
0'"
..............
s:S:
s:S:
UlUl
MM4230NO/MM5230NO.7 x 9 horizontal scan
display character generator
NN
WN
general description
00
Zz
The MM4220NP/MM5220NP isa 1024-bit read-only
memory and the MM4230NN/MM5230NN and
MM4230NO/MM5230NO are 2048-bit read-only
memories programmed to generate a font of 64
7x9 dot-type raster or horizontal-scan characters.
The typical application shows the ASCII-address
system. The display refresh memory, built with
MOS dynamic shift registers, and the TTL control
techniques are similar to those described in Application Note AN-40. Designs for vertical-scan fonts,
printer character generators, and designs for fonts
larger than 7x9 are also outlined in AN-40.
O~
For full electrical, environmental and mechanical
details, refer to the M M 4 2 2 0 I M M 5 220 and
MM4230/MM5230 data sheets.
N
W
s:
s:
~
o
Z
z
.......
s:
s:
typical application
Ul
N
7x9 Character Generator System
W
o
Z
z
.
+: .. :
...
Note: For additiollal information refer to AN-40.
~.
MM52JO NN
I.
MM5230 NO
I
~.
~
I
• .:
Order Number MM4220NP/J, MM5220NP/J,
MM4230NN/J, MM5230NN/J, MM4230NO/J,
or MM5230NO/J
See Package 11
Order Number MM5220NP/N, MM5230NN/N,
or MM5230NO/N
See Package 18
7-1
'0
Zz
Zo
character font
OM
..... ... ..... ......: .......
..... . .'" . .·,......, .....f
: . . .. ..
...::-: ::.....
i.
..
I
-i
!
I.:_!.! :.....:: ......
r-:: ...... .:.... .i....: :: :.....: i ! ..i..
..
MN
Nit)
,
:
•o o.•
It)~
~~
~,
01
000000
'0
Zz
Zo
100000
"
010000
OJ
04
110000
00100(1
os
1010110
"
011000
"
111000
"
000100
.......
r···::.. ....... ......
.i·····
I :! .::...
· ·:
......
! .. ! I .... .:;::::
OM
MN
N..:t
..:t~
~~
"
000010
......
17
100010
11.
Z
"
0100HI
N
N
l2
OOUDOI
lJ
100001
It)
~
20
001010
,
i •••••
"
010001
"
21
101010
.: .: ......
..... .. ,
·· .. ....
......
· . ........!.·..: ·.,...
o
°
I
19
1111010
011010
"
111010
....
•
l5
110 !HI!
J6
001001
09
100100
n"
,
"
101001
111001
24
000110
11.
Z
51
4B
°
000011
N
N
1001111
010011
110011
"
100110
40
000101
101011
011011
111011
"
100101
..:t
~
~
Note: Input addresses are in six bit ASCII code ilnd are shown in the sequence Au. A, ... As.
7-2
57
000111
:
11
110100
12
001100
26
27
28
010110
110110
001110
. ., , , .
: ..:::
..:....
:.. ..:
55
001011
"
010100
:
13
101100
"
011100
15
111100
. ....::: ..... .,. ,..: ..::.. .
.: . :.....
..' . t. .... .J ! ·if!!::
,.:
... .........:.j ·.........., .o...,......,... ,.......,., ··........., ....,..............,
i.······i ...: .:.....:::: ........
..
....
: ::- .
:.....: .:.
·:...i! : ·...., .........., :, ·:......: ......
.. .......
..
"
"
"
"
,~
.....i
. ·.. .......
.:,
·o. •
.. i...... i:···:1 ·· ....... :..•.•..:
i.:···
: ..
HID ' "
42
010101
"
1119111
"
101110
"
011110
"
111110
....
..'
.. .. ..
..... '.:. ,........,.
.., .... ,.'
...
4l
47
110101
001101
HI1101
"
"
61
62
001111
101111
011111
110111
011101
111101
"
111111
ROM Character Generators
MM4240ABU/MM5240ABU hol.lerith character generator
general description
The MM4240ABU/MM5240ABU is a 64 x
read-only memory programmed to display
character subset of the Hollerith 12-line
normally used in punching 80 column cards.
pression from 12 Iines to the six needed to
8 x 5
a 64code,
Commake
up a 64-character set may be accompl ished as
shown in the typical appl ication.
For electrical, environmental and mechanical details, refer to the MM4240/MM5240 data sheet.
typical application
SEAIAl
DATA
'"'
'.
"
"
"
"
MM424UABUI
MM524DABU
""
PAGE
STORE
'"
"
(SHAN40)
"
1l0llERITH
CODE
"
'.
'.
'"
12" As . A,
11 " As
0 A,
A, . A"
,
8 '" A3
Note: Hold present gives closure to GND.
Order Number MM4240ABU/J or MM5240ABU/J
See Package 11
Order Number MM5240ABU/N
See Package 18
7·3
code table
character font
HOLLERITH
INPUT CODE
OCTAL
(NON-COMPRESSED)
8
8
8
8
2
3
4
5
8
8
6
7
00
(space)
01
02
03
04
05
06
07
1
10
11
12
13
14
15
16
17
20
21
22
23
24
25
26
27
28
o
8
6
30
31
32
33
34
35
36
8
7
37
9
8
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
7-4
2
8
3
8
8
4
5
8
2
8
8
8
3
4
5
8
6
8 7
GRAPHIC
SEOUENCE DISPLAY
40
41
42
43
44
45
46
47
50
51
52
53
54
55
56
57
60
61
62
63
64
65
66
67
70
71
8
8
2
3
72
73
8
4
8
5
8
6
8
7
74
75
76
77
MM4240ABU/MM5240ABU
........... ...: :•••••
•• ....:
....
: :..... ••.
... .. ..........
••
... ...::..: :••• .·1 ••••: ••••••i i.
:•••::••••••
...:: ....::
....
:
•
:.. .:.
.:. ::
•••
:..
•••• •••
•••••••••
•• !••.....•
. : • ••••:!
:•••:• ....
•• •• !• !• =••
•••••• :•• .....:
..... : :•••
..::••:
• ....
••• :: :•••••
•••••• ...:: .....
.....
..
•••..• .. ..
•• .........
• •
•
::
::
.••
·:i:·
:
• • ••
........ ....
.
:...::.. : ........
:::
..... : I·: I :::.::: :...
•...••. ••
. ......• •..• •.•.....• .•
..... :.... . :...: ..: ••• ..•:..
!·•.! .
!.:... :.
.! .! ::- •• :.: :
......
•• •••
•••••• • • •••••
·.:::... i......! .:5··:!
.........:... :.... .:.... !......
i··
.
·.:.. : : .:.........!!
:... :.... ·!.. ....
.!
00
T
U
v
W
x
y
000001
02
000010
03
000011
04
000100
05
000101
06
000110
000111
10
Dill 000
11
001001
12
001010
1J
001011
14
001100
Hi
001101
16
001110
17
001111
20
21
010001
22
010010
23
010011
24
010100
25
010101
26
010110
27
010111
31
011001
32
011010
33
011011
34
011100
40
100000
41
100001
42
100010
43
100011
44
100100
50
101000
51
101001
52
101010
53
101011
54
55
101100
101101
60
110000
&1
110001
62
110010
63
110011
1i4
110100
65
110101
3D
011000
K
L
M
N
o
P
Q
A
01
I••• ··1••••
• • •••
o
F
G
(period)
07
000000
010000
z
:• •.... •• : :.
••
••••• •••
•••
1···1
•• ••
70
111000
71
n
111001
111010
••
••
73
111011
35
011101
45
100101
36
011110
46
100110
.
74
111100
51
101111
66
67
110110
110111
:.
15
111101
47
1001t1
56
101110
••• ::::: ••
•
••
e.
37
011111
76
111110
!
;
.:
.1••
••:
77
111111
ROM Character Generators
MM4240ABZ/MM5240ABZ EBCDIC-8 character generator
general description
six needed for a 64-character subset is accomplished by simply ignoring the two most significant
EBCDIC bits, bit 0 and bit 1.
The MM4240ABZ/MM5240ABZ is a 64 x 8 x 5
read only memory that has been programmed to
display the 64 character graphic subset of EBCDIC8, an Extended Binary Coded Decimal Interchange
Code with character assignments and locations conforming to the American Standard x 3.26-1970
(see MM52300X data sheet for full EBCDIC-8
table).
The octal character address digits are then formed
as shown below.
For electrical, environmental and mechanical details, refer to the MM4240/MM5240 data sheet.
Compression of the eight bits of EBCDIC-8 to the
character font
.... ...... •..... •...
..····.....
•.
•..... ·
.·.. ••......·
·
....
•
·
··......
:.... :• ·
··.....·• .•.....·•....··· ....
"·
...
...
.
··.....·· ...·: ·...• .... ....· ···· .....··•
· ·· · ·
···.........·
·
··.. ··.. ··· ......·•
::::-.::
··........... ...···........ ····.·••......··......
·... ·.... ·...· . ·. · ......
• .. ··.
....
···...
..
.
·
..
...
: ·-:-.
.
....
.
·
-:::- ··
.
...... .. ..·: .-:- ·.. ··: .::· · .
.........
..............
.. . ··...
.··.····...··.. ..
..
. ..... ·· ......
.. ..
·_:e.....••_. ·: ...
..
...... .... ·....:
·
::
.. ...... : .. ::: ... ·•
... ......
. .....
.........
···...... ....·:: ·:....
....·.......
.... :.....
:. ....: .•.... ...
: .......... :
·
··...... •......·• ·· ..... ··..
··•.........·•• ·..........••• ••.... .........
• • ..:..
00
000000
01
000001
02
DOUOla
03
000011
04
000100
00(1101
06
000110
000111
10
00100(1
11
001001
12
001010
13
001011
14
001100
15
001101
16
001110
001111
05
27
(lID 111
010001
22
010010
23
010011
24
010100
25
010101
26
010110
31
011001
32
33
34
011100
35
36
011010
011101
41
100001
42
100010
43
100011
44
100100
45
100101
46
100110
47
100111
50
101000
51
101001
52
101010
53
101011
54
101100
•••••
55
101101
56
101110
101111
60
110000
61
110001
62
63
64
65
~
67
110010
110011
110100
110101
110110
110111
74
111100
75
76
77
111101
111110
11111/
20
010000
30
40
100 DO!!
21
70
11
72
1111)00
111001
111010
o •
73
111011
EBCDIC BITS
~
17
MSB
MSD
234
567
'-/
'-/
1
2
LSB
LSD
~
OCTAL DIGITS
37
011111
Order Number MM4240ABZ/J or MM5240ABZ/J
See Package 11
57
OUTPUTS
8,8 2 83 8 4 8 5
000.
•
001..
•
010 • • •
ROW
011.
••
ADDRESS 100.
•
101.
•
110.
•
111
Order Number MM5240ABZ/N
See Package 18
7-5
ROM Character Generators
MM4240ACA/MM5240ACA EBCDIC character generator
general description
The MM4240ACA/MM5240ACA is a 64 x 8 x 5
read only memory that has been programmed to
display the 64 character graphic subset of E8CDIC,
an Extended Binary Coded Decimal Interchange
code typically used in IBM systems.
The octal character address digits are then formed
as shown below.
Compression of the eight bits of EBCDIC to the
six needed for a 64·character subset is accom·
For electrical, environmental and mechanical de·
tails, refer to the MM4240/MM5240 data sheet.
plished by simply ignoring the two most significant
EBCDIC bits, bit zero and bit one.
character font
· ....
.
.... ...................
.. .. ••
:
00
000000
••• ••: ••:::
•• :•
:::
1···11•••: :••••
I
•••
:
I•••• I
©
01
1100001
...
~
000010
000011
M
05
0110100
000101
• • ••• •
i···! I :.1.
: : .:. • ::
00
000110
:••::
07
000111
·".•• ··1·· ·!:•
o
.:-o.
10
11
001001
12
13
001010
001011
14
001100
15
001101
16
17
001110
001111
'.'
: I.': : : : : '.:: : : ••••
••••••••••
: •• :•••. : :1 ::•••::
w
010000
~
o
... . ....
··.... .....
.. .... ..........
.. ..
... ......
.
...·• .•....•• •••• ..•••• ·.....
• ..
..
•...
•• ••• .. .....
·:.::.:.
.... • · .....·.. •· • ·
001000
EBCDIC BITS
o
21
22
23
M
25
26
27
010001
010010
010011
0111100
010101
010110
010111
MSB 234
MSD
'"1
567 LSB
'-/
2
LSD
"--.../
OCTAL DIGITS
••••
"
0
•
· · · · ...• ......
·
·
·
••'.'••
·• ·.• • •: ·• ••• ••• •·•• .:••....·:•• ....
••.·· ·...•• •• ••...•• ••• ·
• •• •
°
·
.. ··. .....:
:.. .. •• ••
.
"·..·
·•'.'•• ·• .....
.
••
·•
·.. ·..... .....· .••.. ·• ..•• .....
·
.....
..
•••·. • ..· ....
...·....••·• ·.....
·.•" • :• ••:e...••••·.....··.:
·••••..··•• .....·••• ··•.....
· • ••
..
•••• ...• •• .........
·
.
••...
.. ..•...·. · ·.
·•••·•• ·......··• ..•• ........
·
31
J2
JJ
011001
011010
011011
41
42
43
l(JOOOI
1(10010
100011
50
101000
51
101001
52
53
1010111
1011111
60
61
1111001
62
110010
63
64
110011
110100
30
011000
34
011100
"
40
10(lO(JO
44
100100
35
011101
36
011110
0
45
100101
46
100110
.0
47
100111
0.
0
110000
37
011111
0
64
101100
55
101101
••••
65
110101
0
56
101110
66
110110
57
101111
OUTPUTS
8, B2 B3 B4 B5
•
•••••
••
•
000.
001 • •
010 •
ROW
011.
ADDRESS 100.
101 •
110.
111
67
110111
•••••
o •
70
111000
7·6
71
111001
n
111(Jl0
• 730
111011
74
11110(J
75
76
77
1111(J1
111110
111111
Order Number MM4240ACA/J or MM5240ACA/J
Order Number MM5240ACA/N
See Package 11
See Package 18
(J)
"o
o
o
ROM Code Converters
eN
SK0003 sine/cosine look-up table kit
general description
The SK0003 Sine/Cosine Look-Up Table Kit consists offourMOS ROMs: three MM4210/MM5210's
and one MM4220/MM5220-1024 bit static read
only memories. They are P-channel enhancement
mode monolithic MaS integrated circuits utilizing
a low threshold technology.
THE SINE FUNCTION
The SK0003 implements the equation sine ~ sin
M cos L + cos M sin L. Cos L was assumed to be
1 in the equation. However, it is a variable between
1 and 0.99998 and is a function of round off error.
Worst case error is 1-5/8 bits in LSB at address
1415 (62.25°). The error increases from zero to
.002% every 8 bits, therefore, the MM42201
MM5220 provides the error correction factor
cos(M - 2.81°)sin L in the equation sine ~ sinM +
cos (M - 2.81°) sin L. The circuitry to perform this
function is shown in Figure 1. Additional information is available in MOS Brief 10_
THE COSINE FUNCTION
To generate the cosine function cose ~ sin (8 90°), the input must be complemented and a
logical "1" added. Figure 2A is a logic diagram
of the circuitry used to provide the cosine function, as well as providing both sine and cosine
functions in the same system. 11-bit resolution
and 12-bit accuracy ±1-5/8-bits is achieved in this
configuration.
A reduction in logic can be achieved as shown in
Figure 2B if a loss in resolution of 112-bit in an
11-bit input or 1/4-bit in a 10-bit input is acceptable.
ELECTRICAL CHARACTERISTICS
Refer to the appropriate data sheet for each
device shown in the figures. The devices noted are:
MM4210/MM5210, MM4220/MM5220, DM54831
DM7483, DM78121DM8812 and DM5486/DM7486.
logic diagram
DM8812,
o-[)oo---Qoo-[)oo-[)o-
1.
J;,
2'
B
2"
CARRY
OUTPUT
.,~---------t--I
"
.,~---------t--I
Order Number SK0003C
or
Order Number SKOOO3M
CARRY
OUT1'UT
{
{
Aa MM5210
"
"
A. MKOOll
II:!
"
,H
"
!:
A,
"
21
""MM5220
i A.
J "
"
MKOIO
..
~====~=~_J>---,,;:":':'~(T~O~"~CHOUTPun
~
-12V
FIGURE 1. SK0003 Logic Diagram (Kit Includes ROMs Only). This Circuit Provides l1-Bit Resolution and 12·Bit
Accuracy in a
eto Sin eConverter.
8-1
('I')
0
0
0
logic diagram
~
C/)
CARRY
DUT
2'
".{
MSB'S
2'
DM748J
2'
2·
2'
."
FOUR
MSB'S
.
{
I,
SKOOOJ
2"
ROMS
I,
A,
AND
OUTI'UT
I,
ADOERS
A,
2'
A,
t'
"'"
lSB'S
2,10
{
I,
A,
2- 11
I,
A,
2,12
I,
SINE/COSINE
ENABU
A,
I,
"
CARRY
"
FIGURE 2A. Sine/Cosine Conversion Provides 11-8it Resolution, 12-Bit ± 1-5/8 Bit Accuracy.
EX-I.IA GATES
MSO=tJDM74'"
2'
NEXT
2'
"SO
2'
2'
2'
SKBDD3
AOMS
2'
AND
OUTPUT
ADDERS
2'
2'
CS'3
SINE!
COSINE
"O"_Sme
2'
2.10
2"
2"
"1"-COl'ne
SIGNAL
FIGURE 2B. Sine/Cosine Conversion with Cosine Approximated. (Cosine Conversion has 10-Bits Input Resolution
and 12-Bit ±1-5/8-Bit Accuracy.)
8-2
s:
s:
ROM Code Converters
~
N
N
o
l>
m
........
s:
s:
C11
MM4220AE/MM5220AE ASCH-7 to hollerith code converter
N
N
o
l>
m
general description
The MM4220AE/MM5220AE 1024-bit read-only
memory has been programmed to convert the
128 entries of the American Standard Code for
Information Interchange in seven bits (ASCI 1-7) to
Hollerith code (compressed to eight bits). The
conversion performed follows the recommendation
of American National Standard ANSI x 3.261970, Hollerith punched card code.
The typical appl ication shows a recommended
circuit for re-expansion of the Hollerith code to
twelve lines.
For electrical, environmental and mechanical details, refer to the MM4220/MM5220 data sheet.
typical application
t o~~~:!~2
0,
,
0,
,
,,
liNCH
OW
i,}
"
17~
11
'"',
."
. '"
."
ASCII·7
INPUTS
MM4220lHI
-.
FAN OUT AVAILAOlE
1 TTL lOAD
r
"
*".
" "
~'" °
·, .
-
'"'+
·.
r
r --r---
,"
A'18
TYPICAL
7UNES
·.
10
MM5220AE
Bs
8,
,~ J
,I)
.~
,
·
_12V
,~
DM1442
.~
,~
,
)
FAN OUT AVAILABLE
10TTLLOADS
'0-, 0-'0-HOLLERITMPU NCHCOMMANDS
(ACTIVELEVE L lOW,PUNCHl
'CHIPENABLE
*Chlp Enable'" Logic "1" to obtain OlitputS.
logic levels:
OTL/TTl (ellceptat MOS/ROM Interface}. Logic "1," +5.0V, NOM, lllglC "0" ground, NOM.
MOS/ROM inputs and outputs. logic "1 ," more negative, logic "0," more positive.
Order Number MM4220AE/J or MM5220AE/J
See Package 11
Order Number MM5220AE/N
See Package 18
8-3
w
«
~
code conversion tables
N
It)
~
~
........
w
«
b7
bs
b5
o
N
N
o::t
b4 b3 b2 b,
~
~
0
0
0
~
RO
0
0
0
1
1
0
0
1
0
4
5
0
0
8-4
P
11-7
1
0
1
1
3
0
1
2
1
11-8
a
12-0-1
q
12-11-8
B
12-2
R
11-9
b
12-0-2
r
12-11-9
3
3
C
12-3
S
0-2
c
12-0-3
s
11-0-2
4
4
D
12-4
T
0-3
d
12-0-4
t
11-0-3
0-8-4
5
5
E
12-5
U
0-4
e
12-0-5
u
11-0-4
&
12
6
6
F
12-6
V
0-5
f
12-0-6
v
8-5
7
7
G
12-7
W
0-6
9
12-0-7
w
11-0-6
8
8
H
12-8
X
0-7
h
12-0-8
x
11-8-5
9
9
I
12-9
Y
0-8
i
12-0-9
Y
11-0-8
*
11-8-4
J
11-1
Z
0-9
j
z
8-2
12-11-1
11-0-9
+
;
I
11-8-6
[
12-8-2
k
12-8-6
K
11-2
12-11-2
12-0
L
11-3
\
1
12-11-3
12-11
M
11-4
1
m
12-11-4
11-0
DLE
12-11-9-8-1
SP
NOPCH
1
SCH
12-9-1
DCl
11-9-1
!
12-8-7
1
1
A
12-1
0
0001
2
STX
12-9-2
DC2
11-9-2
"
0010
8-7
2
2
0011
3
ETX
12-9-3
DC3
11-9-3
8-3
4
ECT
9-7
DC4
9-8-4
$
0100
5
ENO
0-9-8-5
NAK
9-8-5
%
0101
0110
6
ACK
0-9-8-6
SYN
9-2
7
BEL
0-9-8-7
ETB
0-9-6
CAN
11-9-8
I
8
BS
11-9-6
EM
11-9-8-1
I
9
HT
12-9-5
10
IF
0-9-5
SUB
9-8-7
1011
11
VT
12-9-8-3
ESC
0-9-7
1100
12
FF
12-9-8-4
FS
11-9-8-4
1101
13
CR
12-9-8-5
GS
11-9-8-5
1110
14
SO
12-9-8-6
RS
11-9-8-6
12-8-3
0-8-6
N
11-5
11-8-7
15
SI
12-9-8-7
US
11-9-8-7
/
0-1
?
0-8-7
0
11-6
0-8-5
1010
1111
@
0-8-2
11-8-2
!\
,
"
@
,
>
15
---r-
?
16
Blank
!
'7
18
/
/
19
20
S
S
T
T
u
u
V
V
W
W
23
24
X
X
y
y
25
Z
Z
26
t
LF
21
22
0
0
% or{
29
30
,
31
32
til
"
a
33
34
J
J
K
K
0
0
-
HT
0
35
L
L
0
36
37
M
M
a
N
N
0
38
0
0
39
40
P
P
Q
Q
R
R
a
a
a
a
a
a
a
a
a
4'
42
!
,
43
44
$
$
. .
45
I
I
46
47
4
I
0
48
& or +
&
a
49
A
A
0
50
B
C
B
D
D
E
E
a
a
a
a
54
F
F
0
55
G
G
0
56
H
H
57
I
I
?
+
a
a
a
a
a
a
5'
52
53
58
C
59
60
J:I or)
6'
62
63
I
<
(
<
0
*
CR
a
~
.0
a
a
0
%
0
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
27
28
v
BCDIC
A7
0
0
a
a
a
a
a
a
1
,
,
,
1
,
,
,
,
,
,
,
,
,
1
,
a
a
a
a
,
, ,
, ,
, ,
1
0
a
a
a
a
0
a
a
0
0
a
a
,
,
,
,
E
P
,
, ,
, a ,
, , a
a
a , a
, a a
, , ,
a ,
a , a
, a a
, ,
,
a
a , a
1
0
0
1
0
a
,
1
1
a
0
a
1
,
, ,
ASCII
b7
0
0
a
a
0
0
a
a
a
a
0
a
1
1
1
, a
,
, , aa
a a a
,
a , , ,
, a a , a
,
, a a
, ,
, ,
, aa a
,
,
,
a
a a a
a
,
a , , ,
,
,
, a
, ,
a
,
,
a
a
,
, a a
, a, a , ,
, a
, , ,
,
,
,
,
a a ,
, ,
,
,
, a , a , a a a
,
, ,
,
, a , ,
, a
, , aa
, a , ,
, a , , , a , a
, 0 , , , , , ,
, a
, ,
,
, ,
a ,
, a a ,
, , aa
, , , ,
, ,
, , a , a a a
, a , , ,
, ,
,
, ,
, ,
, , a, a ,
, ,
, , ,
,
, , ,
a , , ,
, , ,
, a, aa a
, ,
, , , a,
a , ,
,
, , , ,
, , , , a, a aa aa
, , , , , , , a
1
1
1
1
0
1
1
1
1
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
1
1
0
0
AS AS
A4 A3 A2 A,
B8
B7
0
0
, a,
,
, a
1
1
a
a
a
a
0
a
a
,
1
0
,
,
,
0
0
a
a
,
0
1
b,
N
N
0
o
»
."
1
1
1
0
a
a
0
1
1
a
a
a
1
, aa
, a
, ,
a
,
1
1
1
a
a
a
a
a
a
1
1
0
, a,
a
1
1
0
1
1
a
1
1
0
1
0
0
1
0
0
0
0
0
0
0
0
u
0
1
1
0
1
,
,
,
1
0
1
a
a
a
a
a
0
0
,
0
0
,
a
0
,
a
a
, a ,
,
,
, aa , ,
,
, ,
a , , a
,
a a
0
0
0
a
a
a
a
a
a
a
a
a
a
a
0
0
0
0
,
a
a
a
a
BS
BS
0
0
0
, a ,
,
, , a
,
, ,
,
, , a a a
, , a a ,
, , a
a
a , a , a
, a a
a , a ,
a
a , , ,
,
a
,
, a,
,
a ,
,
,
a ,
a a
,
a ,
,
a ,
, , a,
1
, aa
, a
,
, a
a ,
, a
a
a
a
a
a
b2
,
a , a
a , ,
, a a
,
, a a
,
0
0
a
a
a
a
a
a
a
a
1
a
a
a
1
0
0
0
0
0
b3
a
a
0
0
0
0
, , ,
, , ,
, , ,
,
a
, a
0
0
0
1
a
1
1
1
1
1
b4
0
1
1
1
1
a
a
a
bS
,
, ,
, ,
, ,
, ,
, ,
,
a
, a a
, , ,
a a a
a , a
, a , ,
, ,
a a a ,
a , a ,
0
bS
,
, ,
a
a ,
, a
, ,
0
a
a
,
,
,
,
0
0
,
,
,
a
a
a
a
,a
B4
B3
B2
B,
0
, ,
,
, , , a
,
,
,
,
a
, a , a a aa
, , , , a a
, , a ,
a
0
0
8·7
ROM Code Converters
MM4220BLlMM5220BL baudot-to-ASCII code converter
general description
The MM4220B L/MM 5220BL is used for conversion
of the Communications Set Baudot code to the
American Standard Code for Information Interchange (ASC II).
feedback and latch circuits can be deleted (as
shown with the X's).
The accompanying table is applicable for the code
conversion scheme as shown (or its alternate)
rather than for the device itself. The input and
output codes are defined at the TTL gates with the
logic trues high (Logic "1" = +5 volts, nominal;
Logic "0" = Ground, nominal).
The Baudot and ASCII codes have different formats. ASCII has a unique code combination for
each alphabetic, numerical, or control character.
The correct interpretation of a five bit Baudot is
dependent upon knowing its previous history;
whether upper or lower case was last selected. In
effect a sixth-bit, which can be called the Case Bit,
is required to uniquely identify the Baudot input.
The latch circuit shown in the typical application
can store this information and will generate the
Case Bit. If the bit is externally supplied, the
device characteristics
For full electrical, environmental, and mechanical
details, refer to the MM4220/MM5220 1024-bit
read only memory data sheet.
typical application and connection diagram
Baudot to ASCII
"
'"
"
A421
"
MM4220BL
DR
Ollll'UTGATES
-,
"
"
)\'20
DM8000SERIES
'.
iAll6.8K)
logic Levels of Input and Output Code,.
"1"" +5.0V Nominal
"0"= Ground, Nominal
Logic Levels
"1" More Negative Output
"0" More Positive Output
Dual-In-Line Package
'.
"
'.
"
'.
MODE
CONTROL
'.
8·8
See Package 11
Order Number MM5220BL/N
See Package 18
"
'n ..."_-===_..J
Order Number MM4220BLlJ or MM5220BLlJ
'.
code conversion tables
FUNCTION
INPUT
ROM
ADDRESS
BAUDOT
SYMBOL
CODE
OUTPUT
ASCII
SYMBOL
INPUT
OUTPUT
C
A
S
E
1
2
3
4
S
EP
b7
b6
bS
b4
b3
b2
0
0
0
0
0
0
0
0
0
0
0
0
0
BAUDOT
ASCII
bl
Blank
NULL
0
0
1
T
T
0
0
0
0
0
1
1
1
0
1
0
1
0
2
CR
CR
0
0
0
0
1
0
1
0
0
0
1
1
0
1
1
1
0
0
1
1
1
1
0
0
0
0
3
0
0
0
0
0
0
1
4
Space
Space
0
0
0
1
0
1
0
1
0
1
0
0
5
H
H
0
0
0
1
0
1
0
1
0
0
1
0
0
0
6
N
N
0
0
0
1
1
0
0
1
0
0
1
1
1
0
7
M
M
0
0
0
1
1
1
0
1
0
0
1
1
0
1
8
LF
LF
0
0
1
0
0
0
0
0
0
0
1
0
1
0
9
L
L
0
0
1
0
0
1
1
1
0
0
1
1
0
0
1
0
R
R
0
0
1
0
0
1
1
0
1
0
11
G
G
0
0
1
0
1
1
0
1
0
0
0
1
1
12
I
I
0
0
1
1
0
0
1
1
0
0
1
0
0
1
13
P
P
0
0
1
1
0
1
0
1
0
1
0
0
0
0
14
C
C
0
0
1
0
1
1
0
0
0
0
1
1
15
V
V
0
0
1
1
1
1
0
1
0
1
0
1
1
0
16
E
E
0
1
0
0
0
0
1
1
0
0
0
1
0
1
17
Z
Z
0
1
0
0
0
1
0
1
0
1
1
0
1
0
10
18
1
1
1
0
1
D
0
1
0
0
0
0
1
0
0
0
1
0
0
19
B
B
0
1
0
0
1
1
0
1
0
0
0
0
1
0
20
S
S
0
1
0
1
0
0
0
1
0
1
0
0
1
1
21
Y
Y
0
1
0
1
0
1
0
1
0
1
1
0
0
1
22
F
F
0
1
0
1
1
0
1
1
0
0
0
1
1
0
23
X
X
0
1
0
1
1
1
1
1
0
1
1
0
0
0
0
0
0
0
D
1
A
W
A
0
1
1
0
0
1
0
0
0
25
W
0
1
1
0
0
1
1
1
0
1
0
1
1
1
26
J
J
0
1
1
0
1
0
1
1
0
0
1
0
1
0
27
Upper
0
1
1
0
1
1
0
0
0
1
1
0
0
0
28
24
IS1/Can
1
U
U
0
1
1
1
0
0
0
1
0
1
0
1
0
1
29
Q
Q
0
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
1
0
0
1
1
K
1
1
0
K
0
1
1
30
31
Lower
Delete
1
1
1
1
1
1
1
1
1
1
1
1
1
32
Blank
NULL
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
33
5
5
1
0
0
0
0
1
0
0
1
1
0
1
0
1
34
CR
CR
1
0
0
0
1
0
1
0
0
0
1
1
0
1
35
9
9
1
0
0
0
1
1
0
0
1
1
1
0
0
36
Space
Space
1
0
0
1
0
0
1
0
1
0
0
0
0
0
37
#1£ SIS
BS/FE
1
0
0
1
0
1
1
0
0
0
1
0
0
0
1
1
1
1
0
0
0
1
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
40
LF
LF
1
0
1
0
0
0
0
0
0
0
1
0
1
0
41
}
}
1
0
1
0
0
1
1
0
1
0
1
0
0
1
42
4
4
1
0
1
0
1
0
1
0
1
1
0
1
0
0
38
39
1
0
1
0
1
0
43
&
&
1
0
1
0
1
1
1
0
1
0
0
1
1
0
44
S
8
1
1
a
a
1
a
1
1
1
0
1
1
1
0
1
a
0
1
1
0
a
1
0
0
0
1
1
1
a
a
a
0
0
a
a
a
;
1
a
a
a
a
1
45
1
1
1
1
1
0
1
1
1
0
1
48
3
3
1
1
0
0
a
0
0
0
1
1
0
1
1
49
"
"
1
1
a
a
a
0
1
0
0
1
0
1
1
a
a
a
1
1
a
a
a
a
a
a
a
1
a
a
1
1
0
1
1
a
a
a
46
1
47
1
$
$
1
1
51
?
1
Bell
?
Bell
1
52
1
1
a
a
a
a
53
6
6
1
1
0
50
1
0
61
1
1
1
1
1
1
a
a
1
1
62
I
I
1
1
1
1
1
0
0
a
a
a
a
a
a
a
a
a
a
a
a
63
Lower
Delete
1
1
1
1
1
1
1
1
54
I
I
1
1
0
55
I
I
1
1
0
1
1
1
1
56
-
-
1
1
1
a
a
a
0
2
1
1
57
1
1
0
0
1
1
1
1
1
a
0
1
1
1
a
a
1
Can
1
1
0
7
7
1
1
1
1
a
1
2
58
59
Upper
60
1
1
1
a
1
1
1
1
1
a
a
1
1
1
1
1
a
a
1
1
0
1
a
a
0
a
1
1
1
1
1
1
0
1
1
a
1
1
1
1
0
1
0
1
1
0
a
a
a
1
1
1
1
a
1
1
0
a
0
1
1
0
1
1
1
1
1
0
1
a
1
a
a
a
a
0
1
1
1
1
1
1
1
LEGEND:
EP'" Even Parity
LF "" Line Feed
CR '" Carriage Return
Can'" Cancel
IS1 '" Information Separator #1
S/S .. Stop/Start
BS == Back Space
8-9
ROM Code Converters
MM4220BM/MM5220BM sine look-up table
general description
The MM422bBM/MM5220BM is a 1024-monolithic MaS read only memory that has been
programmed to solve for the sine value x of a
known angle e; i.e., to obtain the solution of the
equation x = sin e.
"1" it carried into the LSB of the eight bit code,
where Ag was a binary "0" it was simply dropped.
EXAMPLE
Find the sine of 45~
Values of e are defined in the look up table for
0° <:::: e < 90° (quadrant I) which has corresponding solutions of 0 <:::: x < 1. For values of
90° < e < 180° (quadrant II), enter the complement 1180° - 8) to obtain the correct solution.
Solutions for quadrants III and IV differ in sign
with I and II. This is summarized in Table 1.
The input address is (45/90) 128 = 64 or
1000000, as expressed in binary. The converter
generates the output .10110101 whose decimal
equivalent is 0.707131. Thus, sin 45° = 0.707.
Find the sine of 21 O?
This value is in quadrant III; therefore 8 ' = 210° 180° = 30°. The input address is then (30/90)
128 '" 43 to the nearest whole integer. The binary
input to the ROM is then 0101011. The output
value is .10000001 or 0.503906. Thus, sin 210° =
-0.504, with the sign generated by the external
logic. The solution is within 1%; note that address
43 is actually equal to 30.23°.
This input is divided into 128 parts for 8 in each
quadrant. Thus, the appropriate input address is
(8' /90°)1128) to the nearest whole integer. The
actual input code to the ROM is the input address
expressed in binary, with A, being the least
significant bit.
The output is the value of X expressed in binary.
The output lines B B2 , . . . . . B8 are binary place
"
values 112, 1/4, . . . . . . 1/256. The sign for negative values of X is externally generated.
device characteristics
For full electrical, environmental and mechanical
details refer to the MM4220/MM5220 1024-bit read
only memory data sheet.
The 8 bit output code has been rounded off from
a larger word code, i.e., where Ag was a binary
connection diagram
Dual*ln-line Package
A,A,A,_
241-- Von
1
2
nt-- lII .c
]
221o-1II_C
81 - 4
21t-- A4
82
-
5
2DI-- A5
BJ
-
6
191--Afi
8._1
IB_A,
11 i-- VGG
85 - 8
8u -
16 ~~g~iROl
r- ~~~BLE
r--
9
87 - 1 0
15
8a - l 1
V ss -
14
TJ
12
As
t-- N.e
TOPVIEW
Order Number MM4220BM/J or MM5220BM/J
See Package 11
Order Number MM5220BM/N
See Package 18
8-10
pattern selection form
ADDRESS
REFERENCE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
FUNCTION
CODE
INPUT
OUTPUT
DEGREES
RADIANS
88
B7
B6
B5
B4
B3
B2
B,
,000
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
0
0
1
1
1
0
0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
0
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
1
0
1
0
1
1
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
0
0
1
1
1
0
0
1
1
1
0
0
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
1
1
1
0
0
0
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
.00
.70
1.41
.012
2.11
.037
2.81
3.52
4.22
4.92
5.63
.049
6,33
.110
7.03
7.73
8.44
.123
.135
,147
9.14
.160
9.84
10.55
11.25
11.95
12.66
13.36
14.06
14.77
.172
15.47
16.17
16.88
17.58
18.28
18.98
19.69
20.39
21.09
21.80
22.50
23.20
23.91
24.61
25.31
26.02
26.72
27.42
28.13
28.83
29.53
30.23
30.94
31.64
32.34
33.05
33.75
34.45
35.16
35.B6
36.56
37.27
37.97
38.67
39.37
40.08
40.78
41.48
42.19
42.89
43.59
44.30
.025
,061
.074
.086
.098
.184
.196
.209
.221
.233
.245
.258
.270
.282
.295
.307
.319
.331
.344
.356
.368
,380
.393
.405
.417
.430
.442
.454
.466
.479
.491
.503
.515
.528
.540
.552
.565
.577
.589
.601
.614
.626
,638
.650
.663
.675
.687
,699
.712
.724
.736
.749
.761
.773
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
0
1
0
0
1
0
1
1
0
1
1
0
0
1
1
0
0
1
1
1
0
0
0
1
0
1
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
1
1
0
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8-11
~
a:I
o
pattern selection form(con't)
N
N
Lt)
~
~
........
ADDRESS
REFERENCE
~
a:I
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
o
N
N
~
~
~
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
8-12
FUNCTION
CODE
INPUT
OUTPUT
DEGREES
RADIANS
B8
B7
B6
B5
B4
B3
B2
B,
45.00
.785
1
1
1
1
1
a
a
a
1
1
a
a
1
1
1
0
0
1
1
1
1
1
a
1
1
1
a
a
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
45.70
.798
46.41
47.81
.810
.822
.834
48.52
.847
49.22
.859
49.92
.871
47.11
50.62
.884
51.33
,896
52.03
52.73
.908
.920
53.44
.933
54.14
.945
54.84
.957
a
a
0
0
a
a
1
a
a
1
0
1
a
1
1
55.55
.969
56.25
.982
56.95
.994
1
1
1
1
1
1
0
57.66
1.006
a
a
58.36
59.06
1.019
0
1
1
0
0
1
1
0
1
1.031
59.77
1.043
60.47
1.055
61.17
1.068
61.87
62.58
1.080
63.28
1.104
0
1
0
63.98
1.117
a
64.69
1.129
1
65.39
1.141
66.09
1.154
a
a
1.092
a
1
0
1
0
1
a
a
a
1
a
a
a
a
a
a
a
a
1.190
1.203
1
1
1.215
a
70.31
1.227
1
71.02
1.239
a
71.72
1.252
1
1
1
72.42
1.264
a
a
73.12
1.276
1
73.83
1.289
74.53
1.301
a
a
75.23
1.313
0
1
1
1
75.94
1.325
76.64
1.338
77.34
1.350
1.399
a
1.411
81.56
1.424
82.27
1.436
0
1
1
0
0
1
1
1
1
1
1
82.97
1.448
83.67
1.460
84.38
1.473
85.08
1.485
85.78
1.497
86.48
1.509
87.19
1.522
87.89
1.534
88.59
1.546
89.30
1.559
1
1
a
0
1
1
1
69.61
1.387
0
1
1
1
1
1
1
68.91
79.45
1
1
0
1
1
1
1
1
0
0
0
0
0
0
0
68.20
80.86
a
a
0
1
1
1
1
80.16
1
1
0
a
a
a
a
a
a
a
a
1.362
a
a
0
1
1
1
1
1
a
1.166
1.374
0
1
1
a
a
1.178
78.75
a
a
67.50
78.05
1
1
0
1
1
0
1
1
0
1
1
66.80
1
0
1
0
0
1
1
0
1
a
a
a
a
1
1
1
1
0
a
0
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
0
a
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
a
a
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
a
a
a
a
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
a
0
a
a
0
0
0
a
0
a
0
0
a
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
s:
s:
typical application
~
N
N
o
Vt>;
GATESQMR81(10RDM8812
A,
~
s:
.......
s:
s:U1
68K,
24
V"
TYPICAL,
8UNES
nAUSDMJ400
A,
~,
A,
B,
A.
B,
A,
'"
MM42Z0BM/
MM5220BM
A.
A,
IB
o
"
s:
~
B
9
3.0K,
N
N
Bo
B,
B,
TYPICAL,
7UNES
S.
Vss
DTLITTLLOGIC
'A.
·CHIPENABLE _ _ _....J
tMODECONTROl-------l
tMode Control'" Logic "0," As '" Logic "1."
*Chip Enable" Logic "1"to obtain outputs.
logic Levels;
DTLITTl (except at MOS/ROM mterface), LogH: "1," +5.0V, NOM. Logic "0," ground, NOM.
MOS/ROM Inputs and outputs. logiC "1," more negative. logiC "0," more positive.
Table 1. SINE
Ouadrant
I
II
III
IV
INPUT
Entry to ROM (8' )
Range
> 00 <90
> 900 < 1800
> 1800 < 270 0
> 2700 ~ 3600
0
OUTPUT
Binary Value
Sign
+
+
Direct
1800 - X
Direct Reading
X - 1800
Direct Reading
-
3600 - X
Direct Reading
-
Direct Reading
+'
360'
-,
8-13
ROM Code Converters
MM4220BN/MM5220BN arctangent look-up table
general description
greater than unity, either complement the output
binary code and add a 1, or complement the
resultant angular value (Le., subtract from gOo).
The MM4220BN/MM5220BN is a 1024·bit mono·
lithic MaS read only memory that has been pro·
grammed to solve for the angle (J whose tangent
value x is known; Le., to obtain the sqlution to the
equation: (J = arctan x.
The 8·bit output code has been rounded off. That
is, if another bit of even lower significance had
been computed for the given arctangent value was
a binary "1", it would have carried over into the
LSB of the eight bit code. If it was a binary "0", it
would have been dropped.
Values of x are defined in the Look Up table for
o < x < 1 with angles corresponding from
0° ~ (J < 45°. For val ues x 2 1, the reci procal of x
(Le., 1Ix) must be entered and the output angle
must be complemented to obtain the actual value.
EXAMPLE
The input is divided into 128 equal parts for x.
Thus, the appropriate input address is (128)(x) to
the nearest whole integer for obtaining the appro·
priate ROM address. The input code is the ROM
address expressed in binary with Al being the least
significant bit. For input values greater than unity,
the decimal reciprocal is to be taken prior to entry
of the binary address.
Find the angle whose tangent is 0.258.
The input address is 128 x 0.258, or 33 to the
nearest integer. Expressed in binary, this is
0100001, and is the actual input code to the
converter. The converter will generate the binary
value .01010010, whose decimal equivalent is
0.3203125.
The output has been normalized for 45°. To ob·
tain the true angular reading, the output should be
multiplied by 45°, Le.: (J = ((Jou,pu,) x 45° where
(Jou,pu, is the decimal equivalent of the output.
The output code is the normalized value of the
angle (J expressed in binary. The output lines 6 1 ,
B2 , •••• B8 are binary place values 1/2,1/4, ....
1/256. To obtain angles between 45° and 89.6°
which occur when input values of x are equal to or
Thus, (J
= 0.320 x 45° = 14.4°
device characteristics
For full electrical, environmental, and mechanical
details, refer to the MM4220/MM5220 1024·bit
read only memory data sheet.
connection diagram
Dual-In-Line Package
A3 -
1
24_ VOD
A2 -
2
,,-
A,_
3
12-
1,_ 4
21-A.,
82- 5
2V_AD
,,- ..
83 - 1
II_A,
84 - 7
B,-.
17_Voo
~~g::RDL
8,-8
1&
8J _ID
15~~=~8LE
,,_11
Vss -
"1-"
"I-
12
TOP VIEW
Order Number MM4220BN/J or MM5220BN/J
See Package 11
Order Number MM5220BN/N
See Package 18
8·14
3:
3:
pattern selection form
~
OUTPUT CODE (90UTPUT)
ADDRESS
128lKI
8 87
0
0
0
0
1
1
0
1
2
3
4
5
6
7
•
9
10
0
0
0
1
1
0
1
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
3
14
1
16
17
1
1
1
0
0
1
1
1
0
0
0
0
0
1
1
0
0
1
1
I
0
0
0
0
1
1
1
1
0
1
0
0
0
1
0
0
1
1
0
1
1
0
1
1
0
0
0
0
1
1
1
0
0
0
0
0
1
"24
0
0
25
26
27
2.
29
30
31
32
33
1
1
34
1
1
0
0
84 83
0
0
1
11
12
18
19
20
21
22
1
86 85
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
I
0
1
0
1
1
I
1
1
1
1
1
1
1
0
0
0
0
1
0
0
0
1
I
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
0
1
1
0
1
1
1
1
1
0
0
0
40
0
0
41
42
1
1
0
0
0
0
0
0
0
0
0
35
36
37
38
39
1
1
1
1
I
0
0
0
0
0
0
0
0
0
0
0
0
0
1
82
81
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
I
1
1
1
1
1
1
1
ADDRESS
128 (x)
OUTPUT CODE WOUTPUT)
83 82 81
B8 B' B6 85 84
I
1
0
1
1
I
1
0
0
0
1
0
0
a
1
1
1
0
1
0
0
1
0
1
I
45
0
0
1
1
46
a a
0
43
44
ADDRESS
'281"
86
87
88
89
90
91
0
0
1 1 1 0
1 1
1 0 0 1 1 1 1 0
1 1 0 1 1 1 1 0
52
0 1 1 1 1 1 1 0
53
0 0 a 0 0 0 0 1
0 1 0 0 0 0 0 1
54
0 0 1 0 0 0 0 1
55
56
0 1 1 0 0 0 0 1
0 0 0 1 0 0 0 1
57
.R
0 1 0 1 0 0 0 1
1 0 1 1 0 0 0 1
59
1 1 1 1 0 0 0 1
60
1 0 0 0 1 0 0 1
61
1 1 0 0 1 0 0 1
62
1 0 1 0 1 0 0 1
63
1 1 1 0 1 0 0 1
64
65
1 0 0 1 1 0 0 1
1 1 0 1 1 0 0 1
66
1 0 1 1 1 0 0 I
67
1 1 1 1 1 0 0 1
'8
1 0 0 0 0 1 0 1
'9
1 1 0 0 0 1 0 1
70
1 0 1 0 0 1 0 1
71
1 1 1 0 0 1 0 1
72
1 0 0 1 0 1 0 1
73
1 1 0 1 0 1 0 1
7A
1 0 1 1 0 1 0 1
7<
0 1 1 1 0 1 0 1
76
0 0 0 0 1 1 0 1
77
0 1 0 0 1 1 0 1
78
79
0 0 1 0 1 1 0 1
80
0 1 1 0 1 1 0 1
0 0 0 1 1 1 0 1
81
1 0 a 1 1 1 0 1
82
1 1 0 1 1 1 0 1
83
1 0 1 1 1 1 0 1
84
1 1 1 1 1 1 0 1
85
Note: 1 more negative output.
o more positive output.
a a
0 0
0 0
1 0 0
0 1 0
0 1 0
0 1 0
0 1 0
0 I 0
0 1 0
0 1 0
0 I 0
0 1 0
0 1 0
0 1 0
0 1 0
0 1 0
1 1 0
1 1 0
1 1 0
I
1 0
I
A7
0
1
0
48
49
50
51
1
0
1
1
0
0
0
1
1
1
1
1
1
1
0
0
0
1
92
I
1
93
1
.,
0
0
94
95
I~
98
1
0 0
0 0
0 1 0 0
1 1 0 0
1 1 0 0
0 0 1 0
1 0 1 0
0 1 1 0
1 1 1 0
0 0 0 1
0 0 0 1
0 0 1
0 1 0 1
1 1 0 1
0 0 1 1
0 0 1 1
1 0 1 1
0 1 1 1
010
1 0
lr-!1
99
100
101
102
103
0
0
104
0
1
1
1
105
106
107
0
0
0
0
1
1
0
0
0
108
109
110
111
112
0
0
0
1
1
0
0
1 0
1 0
1 0
1
0
0
1
0
113
114
115
116
117
118
119
1
1
1
0
0
1
0
0
0
1
1
1
1
1
1
120
121
122
123
124
125
126
127
N
N
OUTPUT CODE WOUTPUT)
.8 87 86 BS B' B3 B2 81
1
1
1
1
1
1
0
0
1
1
0
0
0
0
0
1
1
1
0
1
1
0
0
0
1
1
0
0
a
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1 0
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
.1-
U1
N
N
o
IX!
Z
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3:
3:
1
1
1
1
Z
......
1
1
1
IX!
1
1
1
1
1
1
o
1
MM522BN
typical application
A,
17
A,
B,
A,
B,
A.
B,
"
"
"
"
!~
A,
•
.
ZO
MM4220BNI
1
B,
"
MM522l1BN
UK,
TYPICAL,
lUNES
.
B B,
.. J
• B.
.
IOI'B::..,- - - - I -.....
"
B.
tMode Control = logic "0," As = LogiC "1,"
*Chip Enable = logic "1" to obtain outpuh.
".
·CHIPENABLE
tMODE CONTROL----.....J
DlL/TTLLDGIC
logic Levels:
OTL/TIl (except at MOS/RDM Interface!. logiC "1," +5.DV, NOM. logIC "0," ground, NOM.
MOS/ROM mputs and outputs. LOUIc "1," more
lIeg~tlve.
logiC "0," more positive
8·15
u.
o
o
ROM Code Converters
N
N
In
:E
:E
.......
u.
MM4220DF/MM5220DF
o
o
"quick brown fox" generator
N
N
~
:E
:E
general description
along with an even parity bit for a binary count
input of 64 to 127.
The IIiIM4220DF/MM5220DF is designed for exercising and rapid testing of ASCII and Baudotcoded keyboards, typing mechanisms, and data
communic-ations links by generating the internationally accepted "Quick Brown Fox" message_
device characteristics
The input is a 7-bit binary sequential count. The
output of a 6 stage up-counter can be used; a
seventh bit selects the desired code. The message
is generated in the 5-bit Baudot Communications
Set code with a binary count input of a to 63. The
message is generated in the 7-bit American Standard Code for Information Interchange (ASCII)
The message generator is fully contained on a
monolithic MOS integrated circuit chip utilizing
low threshold voltage technology for increased
DTL/TTL compatibility. For complete electrical,
environmental, and mechanical details, refer to the
MM4220/MM5220 1024-bit read only memory
data sheet.
typical applications
connection diagram
Dual-I n-Line Package
"
"
"
"
"
"
.
.
MM4Z2(JOFI
MM52Z0DF
"
"
'
.
"
"
"
"
-,
"
"
"
"
"
~
'00
-,
MODE
CONTROl
"
-,
~
"
'..
tMODECONTRDL----....
tMode Control = Logic "0," As = Logic "1."
"Chip Eneble '" Logic ","10 obtllin outputs.
logic Levels:
OlL/TIL (eKeept at MOS/ROM interface). Logic "1," +5.DV, NOM. Logic "0," ground, NOM.
MaS/nOM inputs and outputs. Logic "1," more neglltive. logic "0," more positive.
Outputs for Circuit shown
Baudot: Logic"O" = "punch"
ASCII: loglctnversion
8-16
QUICK
QUICK
QUICK
QUICK
QUICK
QUICK
QUICK
QUICK
QUICK
QUICK
QUICK
QUICK
BR0WN
BReWN
BReWN
BR0WN
BR0WN
BHeWN
BReWN
BR0WN
BR0WN
BR0WN
BR0WN
BR0WN
F0X
Fex
F0X
F0X
Fex
F0X
F0X
F0X
F0X
F0X
F0X
FeX
JUMPS
JUMPS
JUMPS
JUMPS
JUMPS
JU,,",PS
JUMPS
JUMPS
JUMPS
JUMPS
JUMPS
JUMPS
eVER
eVER
eVER
0VER
0VER
0VER
0VER
0VER
eVER
eVER
eVER
0VER
THE
THE
THE
THE
THE
THE
THE
THE
THE
THE
THE
THE
LAZY
LAZY
LAZY
LAZY
LAZY
LAZY
LAZY
LAZY
LAZY
LAZY
LAZY
LAZY
D0G
DeG
DeG
D0G
00G
D0G
D0G
DeG
DeG
DeG
DIIIG
DeG
123<1567890
12304561890
12304561890
i2304561890
12304561890
12304561890
12341567890
12304567890
12304567890
12341567890
12304567890
12304567890
See Packago 11
Order Number MM5220DF/N
See Package 18
A typical application showing the ASCII-coded test
message as received at a computer terminal.
THE
THE
THE
THE
THE
THE
THE
THE
THE
THE
THE
THE
Order Number MM4220DF/J
or MM5220DF/J
DE
OE
UE
DE
DE
DE
DE
OE
DE
DE
DE
DE
3:
3:
code conversion table
.fa
N
N
OUTPUT CODE
o
o
OUTPUT CODE
."
P
........
A
3:
3:
R
Baudot
OUTPUT
-
-
ADDRESS
CHARACTER
0
1
2
3
CR
1
1
CR
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
5
6
7
8
9
LF
L"
T
H
E
SP
Q
U
I
10
11
12
13
K
SP
"
15
B
R
16
17
18
19
20
21
22
0
23
24
25
26
27
28
29
C
W
N
SP
F
0
X
SP
J
U
M
P
S
SP
0
-
55
56
57
58
59
Fig.
1
2
3
4
5
6
7
8
9
0
SP
60
61
Ltr.
62
63
E
D
SP
0
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0
1
0
1
1
0
1
1
1
1
1
1
1
0
1
0
0
1
1
0
0
1
0
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
87
86
85
84
1
1
1
1
88
0
1
1
1
1
1
SP
0
0
1
0
1
0
0
0
1
0
1
0
0
1
1
1
G
CR
1
1
1
1
1
1
0
1
0
0
0
1
1
1
1
0
1
1
1
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
0
0
0
0
1
1
1
0
0
1
0
1
1
1
1
1
1
0
0
66
67
68
69
70
71
0
0
1
0
0
1
0
1
1
1
1
1
Y
0
1
0
1
R
SP
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
0
1
0
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
1
0
SP
L
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
33
34
A
0
1
0
0
0
1
0
0
1
1
0
1
0
1
1
1
Z
0
CR
0
0
0
0
0
1
1
1
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
NULL
65
0
1
1
0
1
0
0
1
1
1
64
0
1
1
1
1
1
E
1
1
1
1
0
1
E
H
1
1
0
1
1
1
1
1
1
V
SP
b1
0
0
1
1
32
38
39
b2
1
1
1
T
b3
1
1
0
30
31
35
36
37
b4
0
1
0
1
1
1
1
b5
0
1
1
1
1
b6
1
1
1
1
1
1
b7
1
1
0
0
0
1
1
1
0
0
1
1
1
1
1
Y
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
1
1
1
0
1
1
1
1
0
1
1
0
1
0
1
0
1
1
1
0
0
1
1
1
0
1
0
1
1
1
1
0
0
0
1
0
0
0
1
2
=
LF
T
H
E
SP
72
Q
73
74
75
76
77
78
79
80
81
82
83
8.
85
U
I
C
K
SP
B
R
0
W
N
SP
F
0
X
86
87
88
SP
0
1
1
89
90
91
M
0
1
92
93
1
1
94
95
0
96
0
1
0
1
1
1
1
0
97
98
99
SP
1
1
1
1
1
1
0
0
0
1
1
0
1
0
0
1
1
1
1
1
0
1
0
0
0
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
0
0
1
1
0
0
1
1
1
1
0
1
1
0
1
0
0
1
83
82
81
J
0
1
0
0
0
1
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
1
1
0
1
1
1
0
1
1
0
1
0
1
1
0
0
1
0
1
0
1
V
E
0
0
0
0
R
0
0
0
0
1
0
0
0
1
1
1
1
0
1
1
0
0
0
0
1
1
1
1
1
1
1
0
1
0
1
0
0
1
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
0
T
1
E
0
0
0
1
1
1
107
108
109
110
111
112
113
11.
115
116
117
SP
L
A
Z
Y
D
0
G
0
1
0
1
0
0
0
1
0
1
1
0
0
1
1
0
1
1
1
1
0
1
0
0
0
1
0
0
1
0
1
1
1
0
1
H
126
127
1
1
1
1
1
1
1
0
1
0
1
1
1
1
0
1
1
1
1
1
1
0
S
SP
SP
12.
125
1
1
0
1
0
0
1
0
0
0
P
102
103
104
105
106
118
119
120
121
122
123
0
1
1
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
1
1
1
U
100
101
Baudot: Logic "0" :: "punch"
SP
ASCII
T
CHARACTER
1
1
0
1
I
OUTPUT
ADDRESS
4
1
1
1
1
1
1
1
1
3
1
5
0
1
0
1
1
1
1
0
1
1
0
1
0
1
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
SP
0
0
0
0
1
DEL
0
0
0
0
DEL
0
0
0
0
0
88
87
86
B5
SP
1
2
3
4
5
6
7
8
9
0
SP
D
E
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
0
1
0
1
1
0
1
1
1
1
1
1
0
0
0
1
0
0
1
1
1
1
1
1
1
0
0
1
0
0
0
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
1
1
1
0
1
0
0
0
0
1
1
1
0
1
1
0
1
0
1
0
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
1
0
1
1
0
0
1
0
1
0
1
0
1
0
1
1
1
0
1
0
1
1
1
1
1
0
1
0
0
0
0
0
B3
B2
81
1
0
0
1
0
0
84
."
0
1
0
1
1
1
0
0
1
1
0
0
1
1
0
1
1
o
o
0
1
1
1
0
1
1
0
1
N
N
1
1
0
1
1
1
0
0
1
0
C11
0
ASCII: Logic inversion
Space
Note: When chip enable input is at a logical 0, all outputs are at a logical 1.
8-17
ROM Code Converters
MM4220EK/MM5220EK
BCDIC-to-EBCDIC and ASCII-to-EBCDIC code converter
general description
TheMM4220EK/MM5220EK isa 1024-bitread only
memory that has been programmed to convert
both Binary Coded Decimal Interchange Code
(BCDIC) and the American Standard Code for
Information Interchange (ASCII) to Extended Binary Coded Decimal Interchange Code (EBCDIC).
The BCDIC-to-EBCDIC converter is located in the
first 64 8-bit bytes of the ROM. The unused parity
check bit (the most significant input BCDIC bit) is
a Iways a "0".
The ASCII-to-EBCDIC converter is located in the
second 64 8-bit bytes of the ROM. Thus, the input
ASCII code in addresses 64 through 127 has a "1"
in the most significant (A 7 ) bit which is used with
the selection logic. The resulting 6-bit ASCII input
is for display-only upper case and numerical
codes, since it will not accept the control commands or the lower case characters.
device characteristics
For full electrical, environmental and mechanical
details, refer to the MM4220/MM5220 1024-bit
only memory data sheet.
connection diagram
typical application
Dual-In-Line Package
A,
0,
I
0,
.
'00
A,
A,
A,
0,
0,
B
0,
A
0,
A,
2
B,
A,
B,
A,
B,
A,
'"
A,
B,
MM4220EKI
MM5220EK
A,
B
~ ~
B,
2
IB
3.0K,
TVPICAl,
B,
.
B
B,
A-
B,
A,
B,
A,
'"
B,
MODE
CONTROL
B,
CHIP
B,
B,
B,
B,
'"
ENABLE
"
7UNES
'"
tMODE C O N T A O l - - - - - - '
tMode Control
= logic "0," Aa "Luglc "1."
·Chip Enable = logic "1" to obtall1 outputs.
logic Levels:
Oll/TTL (except at MOS/ROM II1terface~. Logic "1," +5.0V, NOM. Logic "0," grolJlld, NOM.
MOS/ROM inputs and OtltputS. logic "1," more negative. Logic "0," more positive.
8-18
~
A,
B,
Order Number MM4220EK/J
or MM5220E KI J
See Package 11
Order Number MM5220E KIN
See Package 18
s:
s:
code conversion tables
~
N
N
o
m
FUNCTION
s:"
s:
.......
COOE
INPUT
OUTPUT
acOic
EBCOIC
SYMBOL
INPUT
OUTPUT
C
ROM
AODRESS
SYMBOL
BCOIC
B A B 4
0
,
Space
,
Space
0
0
0
0
2
2
3
4
0
0
0
0
0
0
0
0
0
0
3
4
2
3
4
0
0
0
0
5
5
5
0
0
0
6
7
6
7
6
7
0
0
0
0
8
9
,0
8
8
9
0
0
9
0
,
0
0
E
0
11
#or-
#
'2
@or'
@
>
'5
'6
17
0
0
0
0
0
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I
I
0
0
S
T
S
T
0
0
0
U
U
0
0
0
V
V
0
0
W
W
0
0
X
y
X
y
0
0
0
0
0
0
0
25
Z
Z
26
tIRM)
RM
0
0
27
28
% or (
%
0
29
30
\
+
q
0
0
3'
32
33
#I
-
0
0
J
J
0
34
K
K
35
36
L
L
0
0
M
M
0
37
38
N
N
0
0
0
39
40
P
P
0
0
Q
Q
0
4'
42
,
R
0
!
0
43
$
$
0
0
0
R
44
45
I
)
6
& or +
A
"
0
&
0
0
46
49
0
A
50
B
B
5'
52
C
C
0
0
0
D
0
53
E
E
0
54
F
F
55
G
G
0
0
56
57
H
H
0
I
58
59
60
6'
62
63
,
I
0
?
0
or )
0
[
I
<
<
0
I:l
*
,
>
0
,
0
0
0
TM
24
0
0
0
Space
23
,
0
JITM)
Space
2'
22
0
0
0
0
0
0
0
'8
48
0
0
,
,
,
,
,
,
,
,
,
,
,
0
0
0
'9
20
47
0
0
0
0
0
0
'3
'4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
0
0
0
0
0
0
0
0
0
0
0
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
0
,
1
0
,
,
, ,
,
,
, ,
,
,
, ,
0
,
,
,
,
,
,
,
,
,
,
0
0
0
2
0
0
0
0
0
0
0
0
0
0
0
0
,
, ,
, , ,
0
0
,
0
0
0
0
0
0
0
0
0
0
,
, ,
, ,
, , ,
0
0
,
,
,
,
,
,
,
,
0
0
0
0
0
0
0
,
,
,
,
0
,
,
,
,
0
0
0
0
0
0
0
0
0
0
,
,
,
,
,
, ,
, ,
, ,
,
,
, ,
, ,
, ,
, , ,
,
, ,
, ,
, , ,
,
, ,
,
, ,
,
,
, ,
, ,
, ,
, , ,
,
, ,
, ,
, , ,
,
, ,
,
, ,
,
,
, ,
0
0
0
0
0
,
,
,
,
0
,
,
,
,
, ,
, ,
, ,
, ,
0
0
0
0
0
0
0
0
, ,
, , ,
0
,
,
,
,
, ,
, ,
, ,
,,
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
0
2
,
,
,
,
,
,
,
,
,
,
,
,
,
,
0
0
,
,
EBCOIC
3 4 5
,
,
,
,
,
,
,
,
,
,
,
,
,
,
0
0
0
0
0
0
0
0
0
0
0
0
0
,
,
,
,
,
,
,
, ,
,
, ,
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
,
,
,
,
,
,
0
0
0
0
,
,
,
,
,
0
0
0
0
0
0
0
0
0
0
0
0
0
,
0
0
0
0
0
0
0
0
0
,
,
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
,
0
0
,
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
,
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
"
0
0
,
,
, ,
, ,
, , ,
, ,
, , , ,
,
,
,
,
,
, ,
, ,
, , ,
, , ,
, ,
, ,
, , ,
, , ,
, , ,
, , ,
, , , ,
, , , ,
,
,
,
,
,
, ,
, ,
,
,
, , ,
, ,
, ,
, ,
, ,
, , ,
0
o
0
0
,
m
0
0
0
0
0
0
,
0
0
0
0
0
0
0
0
0
0
N
N
7
,
,
, ,
,
,
, ,
,
, ,
,
,
, ,
,
,
, ,
,
,
, ,
,
0
0
,
U'I
6
0
0
0
,
0
0
0
0
0
0
,
,
0
,
,
,
,
,
,
,
,
,
,
,
,
,
0
0
0
0
0
0
0
0
0
0
0
0
0
,
0
0
0
,
8-19
code conversion tables(con't)
FUNCTION
INPUT
COOE
INPUT
OUTPUT
OUTPUT
C
1
2
3
4
5
6
7
@
1
0
0
0
0
1
1
1
1
1
0
A
B
C
A
B
C
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
68
69
70
D
D
E
F
E
F
1
1
1
0
0
0
0
0
0
0
0
0
1
1
71
G
G
72
73
7.
75
H
H
1
1
0
0
0
0
I
I
1
0
0
J
J
1
1
0
0
0
1
0
0
0
0
0
1
1
0
1
ASCII
SYMBOL
EBCDIC
SYMBOL
64
@
65
66
67
0
0
0
1
0
0
0
0
0
1
1
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
0
1
0
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
0
1
1
1
1
0
1
0
1
0
1
EBCDIC
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
1
1
1
a
1
1
1
1
1
1
1
1
1
a
1
1
a a a
1
1
1
a 0
a 0
a a
1
a
a
a
a
a
1
1
1
1
1
1
1
1
0
1
1
1
0
1
a a a
1
0
1
0
0
0
1
1
0
1
1
1
1
0
0
1
1
a
1
1
1
1
1
1
0
0
1
0
0
0
1
a
0
a
a
0
1
1
1
1
0
0
1
1
1
0
1
1
0
1
1
a
0
a a
0
1
0
1
0
1
1
1
0
1
1
1
0
1
1
0
1
1
0
1
0
0
1
1
1
0
0
a
0
1
0
0
0
0
0
1
0
0
0
0
1
0
0
P
P
1
0
1
1
0
0
0
1
1
1
0
1
1
81
Q
Q
1
0
1
0
0
0
1
1
1
0
1
1
0
0
82
R
R
1
0
1
0
0
1
1
1
0
1
1
0
0
83
S
T
S
T
1
0
1
0
1
1
1
1
0
0
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
1
0
0
1
U
0
0
1
U
1
1
0
1
0
1
1
0
87
V
W
88
x
89
y
V
W
X
y
90
91
z
L
L
77
M
M
1
1
78
79
N
N
1
0
85
86
1
1
0
Z
1
[
(
1
0
92
\
\
a
93
9.
95
I
"'or"
I
,
1
1
1
1
0
96
Space
Space
97
,
0
0
1
1
1
1
1
1
a
a
1
1
0
1
0
1
a
a
0
1
a
0
1
1
101
102
103
%
%
&
&
1
1
1
1
0
0
0
0
a
104
(
(
1
1
1
1
a
a
0
1
105
106
I
)
1
1
1
1
0
a
1
1
107
108
+
1
1
1
1
0
3
a
a a
1 a
a a
1 a
0
0
1
1
1
115
0
0
0
1
#
1
1
0
"
2
1
1
1
$
0
1
1
#
114
1
0
0
"
113
1
1
$
112
1
0
0
98
/
0
1
99
100
111
1
1
1
a
,
109
110
1
a
1
0
1
1
0
1
+
0
0
1
1
0
1
1
1
0
0
0
1
1
0
0
1
1
1
a
1
1
0
1
1
0
1
0
1
0
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
1
1
0
1
0
1
0
1
0
0
1
1
1
1
a
1
0
1
0
1
1
0
1
1
a
1
0
1
0
1
0
0
1
1
0
1
1
a
0
1
0
0
1
0
0
1
1
1
1
0
1
1
0
1
a
0
1
1
0
1
1
1
1
1
0
0
1
1
1
1
5
1
1
1
1
1
0
1
0
1
1
1
1
1
1
1
0
0
a
1
1
0
1
1
a
0
1
0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
1
0
0
1
1
0
0
0
0
0
1
1
1
1
1
1
1
a
0
0
1
a
0
1
0
1
1
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
0
a
a
1
1
0
1
0
a
1
1
1
1
0
1
a
1
0
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
1
a
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
0
a
0
1
1
1
1
1
1
1
0
1
0
0
1
0
1
1
1
1
0
1
1
1
0
8
8
1
1
1
121
9
9
1
1
1
1
1
1
1
1
a 0
a a
a 1
1
1
1
0
1
1
0
1
a
1
1
1
1
1
1
0
a
0
1
0
0
1
0
1
1
0
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
0
127
1
1
1
1
1
120
126
0
1
1
1
1
125
a
a
1
1
1
1
1
6
7
123
124
1
0
0
1
1
1
6
7
122
1
1
1
1
118
119
5
1
0
0
•
117
0
0
1
0
0
•
116
0
0
0
1
1
/
0
1
2
3
0
1
1
0
1
0
0
1
,
0
1
1
1
80
K
76
0
0
0
1
1
1
1
0
1
0
0
1
1
0
K
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
0
0
0
0
0
0
0
84
8-20
0
ASCII
D
E bS b5 b4 b3 b2 bl 0
ROM
ADDRESS
1
1
;
;
<
>
<
>
1
1
1
1
1
1
1
?
?
1
1
1
a
1
1
1
0
1
1
1
1
1
1
1
1
a
0
0
0
0
0
1
illS
3:
3:
ROM Code Converters
~
N
N
o
MM4220LR/MM5220LR ecolc to ASCII-7/
ASCII-7 to ecOic code converter
r::lJ
........
general description
3:
3:
The MM4220LR/MM5220LR is a 128 x 8 read
only memory which has been programmed to convert the 64 characters of the Binary Coded Decimal
Interchange Code (BCDIC) to the American Standard code for Information Interchange in seven
bits (ASCII-7).
U1
N
N
address 63, converts the 64 character ASCII
graphic subset to BCDIC. The tables show the
character assignments and their binary equivalents.
o
r-
::lJ
For electrical, environmental and mechanical details, refer to the MM4220/MM5220 data sheet.
The first half of the ROM, from address 0 to
typical applications and connection diagram
BCDIC to ASCII
Dual-In-Line Package
Z4
"
"
VOD
"
"
"
"
"
"
'"
1BIT
ASCII
OUTPUT
MIIDE
"
CONTROL
CHIP
EJtABLE
"
'. "
"
Order Number MM4220LR/J
or MM5220LR/J
",
See Package 11
tMODECONTROl _ _ _ _....
Order Number MM5220LR/N
tMode Control" logic "D," As '" LogiC "1."
"Chip Enable = Logic "'''to obtam outpuu.
See Package 18
Logic Levels:
Oll/TTl (except at MOS/ROM mtertace).loOIc "1," +5.0V, NOM. logic "0," ground, NOM.
MOS/ROM inputs and outputs. Logic "1," more negative. logiC "0," mOl"! positive.
ASCII to BCDIC
QATESDM8lI1DORDM,B12
"
"
"
0,
""
0,
ttt.ltDTUSEO)
0,
ASCII
INPUT
.,"
S81T
BCDICOUTPUT
"
"
."
,"
3DK,
T~~r:E~
"
"
tModeControl '" Logic"O," As = LoglI:"1."
"Chip Enable = Logic "'" to obtain outputs.
logic levels:
OTL/TTl (except at MOS/ROM mterface). Logic "1," +5.OV, NOM. Logic "0," Braund, NOM.
MOS/ROM inputs and outputs. Logic "1," more negative. LogiC "0," more positive.
8-21
a::
....
o
code conversion tables
N
N
an
::E
::E
......
ASCII to BCOIC
....a::
o
FUNCTION
INPUT
N
N
q-
::E
::E
ROM
ADDRESS
ASCII
SYMBOL
SCOIC
SYMBOL
0
1
2
3
4
5
6
7
8
9
10
SP
SP
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
..
I
I
#
+++
#
$
$
%
%
&
&
I
Blank
)
~
VT
I
V
CR
I
0
1
2
3
4
5
6
7
8
9
I
0
1
2
3
4
5
6
7
8
9
<
>
<
;
,
@
A
V
>
?
@
A
3'
35
36
37
38
39
40
41
42
43
B
B
C
C
L
L
46
M
M
'6
47
••
4B
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
8-22
COOE
OUTPUT
D
D
E
E
F
F
G
H
G
H
I
I
J
J
K
K
N
N
0
P
P
Q
Q
0
R
R
S
S
T
T
U
U
V
V
W
X
W
X
y
y
Z
Z
I
I
\
\
)
)
~
"
-
-
C
INPUT
OUTPUT
0
MCI
ASCII
D
E
b7
bS
1>4
bJ
b2
bl
DATA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A7
As
As
Aa
A2
AI
B8
a
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A.
d
E
P
B
SCDIC
A
8
0
0
1
0
0
1
1
1
1
0
0
1
1
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
0
0
1
0
1
1
0
0
1
0
1
0
1
1
0
0
1
1
0
0
0
1
0
1
0
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
1
0
0
1
1
1
1
1
0
1
0
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
B7
Bs
BS
B.
0
1
1
1
0
1
0
0
1
1
1
0
0
1
1
0
0
1
1
0
1
0
0
1
1
0
1
0
'I
1
4
2
1
0
0
1
0
0
1
0
1
0
1
1
0
0
1
0
0
0
0
0
0
1
1
1
1
0
0
' 1
1
1
1
1
0
1
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
0
1
1
1
1
0
1
0
1
1
0
0
1
1
0
0
0
0
1
1
B3
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
0
0
0
0
1
0
1
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
B2
B,
o,
s:
s:
code conversion tables(con't)
~
N
N
o
r-
:0
BCOIC to ASCII
"CODE
P
A
R
FUNCTION
INPUT
OUTPUT
C
BCOIe,
SYMBOL
ASCII
SYMBOL
E
8
A
64
SP
SP
1
0
0
65
1
1
1
0
0
66
2
2
1
0
0
67
3
3
1
0
0
ROM
ADDRESS
INPUT
0
ecole
0
4
2
1
T
Y
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
1
0
0
U1
b7
b6
bS
b4
b3
b2
b1
0
0
1
0
0
0
0
0
1
0
1
1
0
0
0
1
1
0
1
1
0
0
1
0
0
1
1
0
0
1
1
0
4
4
1
0
0
0
1
0
0
1
1
0
1
0
69
5
5
1
0
0
0
1
0
1
0
0
1
1
0
1
0
1
70
6
6
1
0
0
0
1
1
0
0
0
1
1
0
1
1
0
71
7
7
1
0
0
0
1
1
1
1
0
1
1
0
1
1
1
72
8
8
1
0
0
1
0
0
0
1
0
1
1
1
0
0
0
73
9
9
1
0
0
1
0
0
1
0
0
1
1
1
0
0
1
74
0
0
1
0
0
1
0
1
0
0
0
1
1
0
0
0
0
75
#
#
1
0
0
1
0
1
1
1
0
1
0
0
0
1
1
76
@
@
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
1
0
0
1
1
0
1
0
0
1
1
1
0
1
0
78
>
>
1
0
0
1
1
1
0
1
0
1
1
1
1
1
0
79
V
-
1
0
0
1
1
1
1
1
0
1
1
1
1
0
1
80
Blank
(
1
0
1
0
0
0
0
0
0
1
0
1
0
0
0
81
I
1
0
1
0
0
0
1
1
0
1
0
1
1
1
82
5
I
S
1
0
1
0
0
1
0
0
1
0
1
0
0
1
1
83
T
T
1
0
1
0
0
1
1
1
1
0
1
0
1
0
0
84
U
U
1
0
1
0
1
0
0
0
1
0
1
0
1
0
1
0
68
77
1
85
V
V
1
0
1
0
1
0
1
0
1
0
1
0
1
1
W
W
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
87
X
X
1
0
1
0
1
1
1
1
1
0
1
1
0
0
0
88
Y
Y
1
0
1
1
0
0
0
0
1
0
1
1
0
0
1
89
Z
Z
1
0
1
1
0
0
1
0
1
0
1
1
0
1
0
90
1
VT
1
0
1
1
0
1
0
1
0
0
0
1
0
1
1
1
0
1
1
0
1
1
1
0
1
0
1
1
0
0
92
%
%
1
0
1
1
1
0
0
1
0
1
0
0
1
0
93
V
1
0
1
1
1
0
1
0
0
1
0
0
1
1
1
94
\
1
0
1
1
1
1
0
0
1
0
1
1
1
0
0
95
+I +
"
1
0
1
1
1
1
1
0
0
1
0
0
0
1
0
0
\
-
-
1
1
0
0
0
0
1
0
1
1
1
1
1
97
J
J
1
1
0
0
0
0
1
1
1
0
0
1
0
1
0
98
K
K
1
1
0
0
0
1
0
0
1
0
0
1
0
1
1
0
99
L
L
1
1
0
0
0
1
1
1
1
0
0
1
1
0
100
M
M
1
1
0
1
0
0
0
1
0
0
1
1
0
1
0
101
N
N
1
1
0,
0
0
1
0
1
0
1
0
0
1
1
1
102
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
1
1
103
P
P
1
1
0
0
1
1
1
0
1
0
1
0
0
0
0
104
Q
Q
1
1
0
1
0
0
0
1
0
1
0
0
0
1
105
R
1
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
1
0
1
0
1
0
0
0
1
0
0
0
0
1
,
R
106
107
$
$
,
108
109
1
1
1
0
1
0
1
1
0
0
1
0
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
0
1
I
I
1
0
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
0
1
1
1
0
1
1
111
6
I
1
1
0
1
1
1
1
1
0
1
0
1
0
0
1
0
110
112
&
&
1
1
1
0
0
0
0
1
0
1
0
0
1
1
113
A
A
1
1
1
0
0
0
1
0
1
0
0
0
0
0
1
114
B
B
1
1
1
0
0
1
0
0
1
0
0
0
0
1
0
C
C
115
1
1
0
0
1
1
1
1
0
0
0
0
1
1
116
0
0
1
1
1
0
1
0
0
0
1
0
0
0
1
0
0
117
E
E
1
1
1
0
1
0
1
1
1
0
0
0
1
0
1
0
1
118
F
F
1
1
1
0
1
1
0
1
1
0
0
0
1
1
119
G
G
1
1
1
0
1
1
1
0
1
0
0
0
1
1
1
120
H
H
1
1
1
1
0
0
0
0
1
0
0
1
0
0
0
121
I
I
1
1
1
1
0
0
1
1
1
0
0
1
0
0
1
122
?
?
1
1
1
1
0
1
0
0
0
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
1
0
1
1
1
0
1
1
1
1
1
0
0
1
1
0
1
1
1
1
0
125
"[
n
[
1
1
1
1
1
0
1
1
1
0
1
1
0
1
1
126
<
<
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
1
CR
1
1
1
1
1
1
1
1
0
0
0
1
1
0
1
A7
Ao
AS
A4
A3
A2
A,
88
87
86
85
84
83
82
8,
123
124
127
r-
1
96
0
o
:0
1
86
91
N
N
ASCII
I
8
s:
s:
OUTPUT
8-23
o
...a:
ROM Code Converters
N
N
It)
~
~
........
o
...a:
N
N
MM4221RO/MM5221RO ASCII-7 to EIA RS244AI
EIA RS244A to ASCII-7
~
~
general description
~
The MM4221RO/MM5221RO is a 1024-bit read
only memory that has been programmed to convert between the American Standard Code for
Information Interchange, compressed to six bits,
and the Electronic Industries Association numerical control standard code, RS244A. The second
group of addresses, from 64 to 127, effects the
revers~,
conversion.
applications information
In the first 64 entries, compression of ASCII-7 to
six bits has been accomplished by dropping bit b6 ,
and substituting the control codes listed for certain
unused ASCII graphic symbols.
In the second 64 entries, the RS244A parity check
bit, C5 is ignored. The bit Ce , used only for the
end of block code (EOB) is used externally to de·
tect existence ofthis symbol, and to insert a redundant code, C4 . C2 (ROM address 74). This code
will be translated arbitrarily as an ASCII EXT.
typical application
LGWTRUE
LOW TRUE
~
I1S244A
ASCII
.----------,
I
'"
I
I
I
"
I
I
'.
I
'.
~o-if-----1
"
"
"
"
"
"
"
0,
"
0,
0,
0,
'"
6.8K
CODE
SELECT
Order Number MM4221RQ{J or MM5221RQfJ
See Package 11
8-24
""lOW" Graphic
HIGH = Contrul
0 - AS744A 10 ASCII
l ' ASCII 10 RSZ44A
Order Number MM5221 RQfN
See Package 18
code conversion tables
ASCII to RS244A
FUNCTION
ROM
AOORESS
0
1
2
3
•
5
6
7
8
9
10
11
12
13
I.
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
3'
35
36
37
38
39
40
41
'2
.3
44
45
46
'7
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
INPUT
OUTPUT
ASCII
SYMBOL
EIA
SYMBOL
SP
SP
ETX
EaT
EOB
EaR
%
%
&
&
BS
HT
BS
TA8
,
,
-
-
I
0
1
2
3
I
0
1
4
5
6
7
8
9
FS
GS
2
3
4
5
6
7
8
9
UC
LC
COOE
C
INPUT
OUTPUT
0
0
E
b7
b5
b,
b3
b2
b,
e8
e7
e6
e5
e,
e3
e2
e,
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
1
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
0
0
1
0
1
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
.0
1
1
0
1
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
1
0
0
0
1
0
1
1
0
0
1
1
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
0
1
0
0
0
1
1
0
0
1
1
0
0
0
0
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0
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0
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0
0
0
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.JL
,
,
b
b
c
c
d
d
e
e
f
f
a
a
h
h
;
;
i
i
k
k
I
m
I
m
n
n
0
0
p
p
q
,
,
t
q
,
,
t
u
u
v
v
w
w
x
x
y
,
,
y
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
~
~
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DEL
DEL
0
0
A7
IncreaSing Binary
Sequence
I
I
I
I
I
I
I
I
I
,
As
•
As
A4
A3
A2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
,
0
1
1
1
1
1
1
1
A,
B8
B7
Bs
B5
B,
B3
B2
B,
8-25
CJ
a:
N
code conversion tables(con't)
N
ID
:E
:E
.......
RS244A to ASCII
FUNCTION
d
a:
....
N
N
'I:t
OUTPUT
ROM
ADDRESS
EIA
SYMBOL
ASCII
SYMBOL
64
Space
,
Space
65
66
:E
:E
CODE
INPUT
,
2
2
3
4
3
4
5
5
6
7
6
7
8
9
8
75
EOB
EOR
ETX
EOT
76
71
78
&
&
,
67
68
69
70
7'
72
73
74
9
79
,
80
0
0
8'
82
,
,
83
84
t
t
u
u
85
v
v
86
87
w
w
x
x
88
y
89
,
,
90
BS
BS
9'
92
93
94
y
TAB
HT
96
97
j
98
k
95
99
I
J
k
I
'00
m
m
'0'
'02
'03
n
n
0
0
p
0
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q
,
q
%
%
'05
'06
'07
'08
'09
110
11'
112
113
,
+
a
a
b
b
c
.
c
f
f
9
h
;
9
h
LC
GS
UC
FS
119
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d
d
e
;
'23
'24
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'27
8-26
,
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,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
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,
,
DEL
DEL
OUTPUT
"7
"6
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0
0
0
0
0
0
0
0
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0
0
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,
+
115
118
,
,
INPUT
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114
116
117
C
0
0
E
,
I
As
•
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A41 A3
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B7
B6
B5
B4
B3
BZ
Bl
ROM Code Converters
MM4221RR/MM5221RR ASCII-7 to EBCDIC code converter
general description
Certain arbitrary assignments have also been made
for maximum usefulness, and in these two areas
the part differs from the MM4230QY /MM5230QY,
which follows American National Standard ANSI
X3.26 recommendations for character assignments.
The MM4221 RR/MM5221 RR is a 1024-bit readonly memory that has been programmed to convert between the 128 characters of ASCII-7, the
American Standard Code for I nformation I nterchange in seven bits, and EBCDIC, an extended
binary coded decimal interchange code. This conversion follows the EBCDIC character assignments
used in the IBM 1130 computer.
For electrical, environmental and mechanical details, refer to the MM4221/MM5221 data sheet.
typical application
ASCII-7 to EBCDIC
'5V
ASCIt.1
ESCDIC
BINARY
HIGH TRUE
12,16
MSB
b,
b,
b,
b,
18
19
20
21
A,
B.
B,
A,
11
II
MSB
10
B,
A,
B,
II,
MM42l1RRI
MM5221RR
B,
b,
A,
B,
lSB
b,
A,
b,
A,
B,
lSB
15J7.24
6.8K
6.8K
6.8K
6.8K
6.8K
6.8K
6.8K
6.8K
lOW
TRUE
-12V
Order Number MM4221RR/J or MM5221 RR/J
See Package 11
Order Number MM5221RR/N
See Package 18
8-27
Ct:
Ct:
~
N
N
In
code conversion tables
:?i
:?i
.......
Ct:
Ct:
FUNCTION
OUTPUT
ASCII
EBCDIC
SYMBOL
SYMBOL
MSB
0
1
NULL
NULL
0
a
SOH
SOH
0
2
STX
STX
0
ROM
ADDRESS
~
N
N
o::t
:?i
:?i
CODE
INPUT
3
ETX
INPUT
0
0
0
0
0
0
0
0
0
0
0
MSB
0
0
0
1
0
0
0
0
0
1
,
0
1
0
0
0
0
0
0
0
0
0
, ,
0
0
0
0
0
1
1
0
0
ETX
0
0
0
0
0
4
EDT
EDT
0
0
0
0
5
ENQ
6
ENQ
ACK
0
0
0
0
0
0
0
0
0
1
,
,
, ,
ACK
BEL
7
BEL
8
BS
9
10
HT
LF
11
VT
12
13
14
15
16
17
OLE
OLE
DCl
0
0
0
0
0
0
0
0
0
0
0
VT
0
FF
FF
0
0
0
0
0
,
,
0
1
CA
SO
CA
SO
a
a
a
a
1
0
51
a
a
a
a
a
51
a
1
1
1
0
0
0
1
0
BS
HT
LF
lB
19
DC2
DC3
DC'
DC2
DC3
20
DC4
AS
21
NAK
SYN
ETB
NAK
SYN
CAN
EM
CAN
EM
26
27
SUB
SUB
BYP
28
FS
29
GS
AS
22
23
24
25
30
31
ESC
32
33
SP
SP
!
!
34
"
"
#
#
36
$
$
37
%
%
38
39
&
&
I
I
I
I
41
+
a
/
0
49
1
1
2
50
2
51
3
4
5
5
55
,
1
0
0
0
0
0
0
0
a
a
a
a
a
a
a
0
0
0
0
0
a
a
a
a
a
a
a
a
a
0
0
0
0
1
1
1
a
,
1
a
1
1
1
a
0
0
a
0
1
0
a
0
a
a
a
a
0
0
a
a
a
a
a
a
a
a
0
I
I
j
4
6
7
6
7
8
8
9
9
j
I
I
<
<
61
-
-
62
63
>
>
,
I
,
,
A7
IAs I A5 IA4 I Aa I A2 I A1
1
1
0
1
1
0
0
1
1
1
0
1
0
,
,
,
,
0
0
1
0
1
1
0
a
1
1
1
a
1
1
a
1
0
0
0
a
a
,
1
1
a
1
1
a
a
a
a
1
1
0
1
1
1
1
a
1
a
1
1
0
0
0
1
1
a
1
1
1
1
0
0
0
Ba
B7
1
1
1
0
0
0
0
1
1
a
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
B6
1
1
0
1
1
0
,
1
a
,
0
a
a
a
0
0
0
0
0
0
1
1
1
0
1
1
1
,
1
1
a
1
1
a
a
a
a
a
a
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
a
0
a
, ,
,
, , ,
,
0
0
1
1
1
1
1
1
,
,
,
0
1
1
1
0
0
,
,
0
0
0
1
0
0
0
0
1
1
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
a
a
a
0
a
0
0
0
0
0
a
a
a
a
a
a
0
I
3
0
0
1
a
0
I
0
0
,
0
j
58
59
60
0
0
0
j
/
0
56
57
1
I
I
a
,
0
0
0
,
LSB
0
0
1
0
0
0
,
,
+
48
52
53
54
0
1
CONTINUING BINARY
SEOUENCE
45
46
47
0
I
42
43
44
1
1
j
FLS
GS
us
40
,
EOB
ADS
US
35
8-28
OUTPUT
LSB
,
1
1
0
1
1
0
1
1
1
1
,
0
1
a
,
1
1
a
a
0
1
1
0
0
a
1
1
1
a
1
1
1
0
1
a
0
a
a
1
a
1
1
1
1
,
,
0
1
1
,
1
1
1
1
1
0
0
1
a
a
,
,
a
a
a
1
0
1
1
1
0
,
a
a
,
,
1
1
0
1
1
1
0
0
a
a
1
1
1
0
1
1
0
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
a
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
a
1
0
1
0
0
1
0
1
0
1
a
1
1
0
1
1
0
0
0
0
1
1
,
a
1
0
0
1
1
a
1
1
1
1
0
0
1
1
1
1
B5
B.
B3
1
1
1
.0
1
0
1
0
1
a
1
0
1
0
1
B2
B1
code conversion tables(con't)
FUNCTION
INPUT
OUTPUT
ASCII
SYMBOL
EBCDIC
SYMBOL
64
@
@
65
66
A
A
8
8
67
C
C
68
D
D
69
E
E
ROM
ADDRESS
70
F
F
71
72
73
74
G
G
75
76
77
78
79
80
81
82
83
84
85
86
87
88
B9
90
91
92
93
94
95
96
97
98
H
I
J
K
K
L
i-
M
M
N
N
0
0
P
P
Q
Q
R
R
S
S
T
T
U
U
V
V
W
W
X
X
Y
Y
Z
Z
[
[
\
NL
I
,
,
b
,
c
,
100
101
d
d
f
f
103
104
9
h
9
h
,
I
k
I
I
en
en
n
0
p
p
q
q
,
t
t
u
u
118
119
v
v
w
w
120
121
x
x
y
,
115
116
117
122
123
124
125
126
127
,
I,
,
~
DEL
o
I
o
I
o
I
MSB
0
0
1
1
1
1
1
0
1
1
1
0
0
0
0
0
0
1
1
0
0
0
1
0
1
1
1
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
1
1
1
0
0
1
0
0
1
1
0
0
1
1
1
0
0
1
1
1
0
0
0
1
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
CONTINUING BINARY
SEQUENCE
1
1
0
n
0
I
lSB
I
I
I
I
I
k
,
,
114
o
J
108
109
110
111
I
o
,
107
112
113
I
e
102
105
106
1
b
99
e
,
I
RES
OUTPUT
MSB
H
I
J
1\
CODE
INPUT
,
y
I,
,
,I
DEL
A7
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
0
AS
A4
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
1
0
0
'0
0
0
0
1
1
0
0
1
0
1
1
0
1
0
1
1
0
1
0
1
1
1
1
0
1
1
0
0
0
1
0
0
1
0
0
0
0
0
0
1
1
1
0
1
0
0
0
0
0
1
1
1
0
0
1
)
0
1
1
0
1
1
1
0
0
0
0
0
1
1
0
1
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
0
0
1
1
0
0
1
1
1
1
1
1
0
1
1
0
0
1
1
0
1
0
0
0
0
1
0
1
0
0
1
1
1
1
a
0
1
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
a
a
a
a
a
a
0
0
1
0
a
1
0
0
1
1
1
0
1
1
1
a
0
1
0
0
1
1
1
a
a
a
1
1
a
a
a
a
a
a
a
a
1
a
1
1
1
a
1
1
0
0
0
0
0
0
0
0
0
0
a
0
0
a
a
a
a
a
a
1
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A1
1
1
1
1
0
1
1
A2
1
0
0
0
1
1
1
A3
1
1
1
1
0
1
0
1
,
1
1
0
0
0
1
1
1
1 I I I I I
A6
1
1
1
1
1
0
lSB
1
1
1
1
1
1
1
1
1
a
a
a
1
a
a
a
a
a
a
B8
B7
B6
0
1
1
a
a
a
a
0
0
0
a
1
1
1
1
0
1
1
a
a
a
a
1
1
1
1
a
a
a
a
a
a
a
a
a
0
1
a
a
a
a
1
1
1
1
a
a
a
a
1
1
1
0
1
a
a
a
1
1
a
0
1
1
1
a
0
1
0
BS
B4
0
1
a
a
1
1
1
1
1
1
1
1
1
1
1
a
1
1
1
1
B3
B2
B,
1
8-29
ROM Code Converters
MM4230BO/MM5230BO hollerith to ASCII code converter
general description
The MM4230BO/MM5230BO 2048-bit MOS readonly memory has been programmed to convert the
12 line Hollerith punched card code to eight level
ASCII. This conversion conforms to the American
National Standard (ANSI x 3.26 - 1970). Three
TTL 4-input NAND gates, and three inverters are
used to compress the 12 Hollerith lines to eightline binary encoded form suitable for use by the
read-only memory. This application is shown
below.
For electrical, environmental and mechanical details, refer to the MM4230/MM5230 data sheet.
typical application
MODE
4 INPUT NAND GATES AAE
DM143QTYPES
CONTROL
OUTPUT,
ASCII-$
",
'.
PUNCHED
CARD
DATA
INPUT
ZDNE(,:, _________________
,"""n
~
,,--.-----------------"'i
Note t: Vss" +12V ±10%, VDO " GNO, VGG "-12V -,-10%.
Note 2: The Hollerith mput data (lines 1 through 12) is considered to be from
normally open switches returned, in the case of a punched hole, to GND as shown.
connection diagram
Dual~1
n-Line Package
"
"
"
...
'.
'.
"
"
'.
"
"
'.
~
'00
MIIDE
"
"
'
.
CONTROL
CHIP
ENABLE
"
...
Order Number MM4230BO-1/J or MM5230BO-1/J
See Package 11
Order Number MM5230BO-1/N
See Package 18
8-30
'.
ANYIlTl/TTl
HIGH
DEVICE
TRUE
code conversion table
Hollerith to ASCII
12
12
12
11
11
0
11
0
0
12
11
0
12
11/10
10/8
1111
11/9
12
11
0
&
-
¢
SP
I
1
A
J
I
1
a
j
-
13/9
SOH
DCl
811
2
B
K
S
2
b
k
s
13110
STX
DC2
8/2
\
12
11
0
11
0
12
11
0
8-1
12/3
12/10
13/1
1318
9/1
10/0
10/9
9/15
11/11
9
-1
SYN
1011
10/10
11/2
11/12
9
-2
3
C
L
T
3
c
I
t
13/11
ETX
DC3
8/3
9/3
10/2
10111
11/3
11113
9
-3
4
D
M
U
4
d
m
u
13112
9112
9/13
8/4
9/4
10/3
10/12
11/4
11/14
9
-4
5
E
N
V
5
e
n
v
13113
HT
8/5
LF
9/5
10/4
10113
11/5
11/15
9
-5
6
F
a
w
6
f
0
w
13/14
8/6
BS
ETB
9/6
10/5
10114
11/6
12/0
9
-6
7
G
P
X
7
9
P
x
13115
DEL
8/7
ESC
EaT
10/6
10115
11/7
12/1
9
-7
8
H
Q
Y
8
h
q
y
14/0
917
CAN
8/8
9/8
10/7
1110
11/8
12/2
9
-8
9
I
R
Z
9
[
I
\
8-4
<
.
%
8-5
(
I
8-6
+
8-7
,0)
8-2
8-3
$
CD may be "I"
® may be "-)I'
r
z
1411
8/13
EM
8/9
9/9
NUL
DLE
8/0
9/0
9-8-1
12/11
13/2
14/2
8/14
9/2
8110
9/10
14/8
14/14
15/4
15/10
9-8-2
12/5
12/12
13/3
14/3
VT
8115
8/11
9/11
14/9
14115
15/5
15/11
9-8-3
12/6
12/13 13/4
14/4
FF
FS
8/12
DC4
14/10
15/0
15/6
15/12
9-8-4
12/7
12/14 13/5
14/5
CR
GS
ENQ
NAK
14/11
1511
15/7
15/13
9-8-5
-
12/8
12/15
13/6
14/6
SO
RS
ACK
9/14
14/12
15/2
15/8
15/14
9-8-6
"
12/9
13/0
13/7
14/7
SI
US
BEL
SUB
14/13
15/3
15/9
15/15
9-8-7
"
@
-
>
~(JJ
I
12/4
,
Note: The entries of Form AlB refer to the unassigned locations in the right hand side of the ASII table
(bit ES = 1) deSignated for specialist use. {See National Bureau of Standards Technical Note No. 478.
Note: For the full ASCII-8 Code Table, see MM42300Y /MM5230QY data sheet,
8-31
W
LL
o
ROM Code Converters
M
N
It)
~
~
.......
W
LL
o
M
N
"lit
MM4230FE/MM5230FE selectric-to-EBCDIC/
EBCDIC-to-selectric code converter
~
~
general description
The MM4230FE/MM5230FE provides for the conversion of IBM Selectric Correspondence Code to
Extended Binary Coded Decimal Interchange Code
(EBCDIC) in both directions. These two decoders
are contained on a monolithic MOS device.
counterparts, it is not necessary to encode bit
position 0 (A8), which is used instead as the code
converter selection bit. In addition to the Selectric
Correspondence output code bits there is a bit to
indicate upper or lower case. The odd parity bit
generated does not account for the case bit.
The Selectric-to-EBCDIC converter is located in
binary addresses 0 through 127. Input bit A7 is
used as a single line command to determine
whether upper (denoted by a "1 ") or a lower
(denoted by a "0") case has been selected.
device characteristics
The EBCDIC-to-Selectric converter is located in
binary addresses 128 through 255. Since not all
EBCDIC control commands have Selectric code
For full electrical, environmental, and mechanical
details refer to the MM4230/MM5230 2048-bit read
only memory data sheet.
typical application
connection diagram
Dual*1 n·Line Package
A,
Vco
A,
'"
A,
,
JO-_ _ _I-_..,A. 21
"
A,
A,
IlM8812
TTL GATES
"
~~:~~~~~f
03
71";;:"----I---i
"
"
""
A,
"
A,
"
"
"
"
A,
A,
Vc ,
MODE
"
CONTROL
"
ENABLE
CHIP
"
V"
DM7400SERIES
-12V de
*Chip Enable: logic "1' to obtain outputs.
Logic Levels:
DTL/TTl (elt~ept at MOS/ROM interface), Logic "1," +5.DV, NOM, logiC "0" ground. NOM.
MOS/ROM inputs and outputs. Logic "1," more negative, LogIC "0," more positive.
8-32
n
A,
"
"
A,
A,
6.81<,
TYPICAL
8 LINES
"
',.
A,
A,
Vee
TTL GATES
Order Number MM4230FE/J
or MM5230FE/J
See Package 11
Order Number MM5230FE/N
See Package 18
3:
3:
code conversion table-selectric-to-EBCDIC
~
N
W
FUNCTION
INPUT
OUTPUT
D
E
C
A
S
E
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
0
0
0
0
0
a
a
a
a
a
0
0
1
0
SELECTRIC
SYMBOL
EBCDIC
SYMBOL
a
-
-
1
b
b
2
w
w
3
9
9
4
q
q
5
k
k
6
;
;
7
6
6
8
y
y
9
h
10
,
,
11
a
a
12
p
p
13
e
e
h
14
15
5
5
NULL
NULL
NULL
NULL
16
17
18
."
R5
a
a
a
a
a
a
a
a
a
SELECTRIC
R, R2A
R2
a
a
a
a
a
a
a
a
a
Tl
T2
0
a
a
a
a
a
a
a
a
1
1
1
1
a
1
a
1
a
a
1
1
1
1
1
a
a
a
1
1
1
1
1
1
a
1
1
1
1
a
a
a
1
1
0
0
1
1
1
0
1
0
1
0
a
1
1
1
a
a
a
a
a
a
a
a
......
OUTPUT
INPUT
C
ROM
ADDRESS
o
m
CODE
1
2
EBCDIC
4
3
5
6
7
a
a
a
a
a
a
a
a
a
1
a
a
a
1
1
1
1
1
a
a
a
1
1
a
a
1
a
1
a
a
a
a
1
a
a
a
a
a
1
1
1
1
1
a
1
1
a
1
a
1
a
0
0
0
1
a
a
a
a
0
0
1
0
0
1
1
1
1
a
a
0
a
a
a
1
1
1
a
1
0
0
1
0
1
1
0
a
0
1
1
0
1
1
0
0
a
0
1
0
1
0
0
0
1
1
1
a
0
1
1
1
1
1
1
0
a
0
1
1
1
1
1
1
1
0
1
a
a
0
0
a
a
a
a
a
a
1
a
a
0
0
a
0
a
a
a
a
a
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
a
a
0
0
0
0
0
0
0
a
0
0
a
0
1
1
1
1
1
1
0
1
1
1
1
0
1
0
0
0
0
a
0
0
1
0
0
1
1
0
-
-
0
0
0
1
0
1
0
0
21
n
n
0
0
0
1
0
1
0
1
0
1
a
0
1
0
1
0
0
0
0
1
0
1
1
0
0
1
0
0
1
a
1
1
22
23
2
2
NULL
NULL
NULL
NULL
24
25
26
0
0
0
1
a
1
1
1
1
1
1
1
0
0
1
a
0
0
0
1
1
0
0
a
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
a
a
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
a
0
0
0
0
a
0
a
28
j
j
0
0
1
1
1
0
a
1
0
0
1
0
0
0
1
29
t
t
0
0
a
a
1
1
1
0
t
1
a
1
0
0
a
1
1
a
27
30
31
,
NULL
,
NULL
NULL
NULL
NULL
32
0
1
1
1
1
0
0
0
0
0
0
0
0
a
1
1
1
1
1
1
0
1
1
a
0
1
1
a
a
0
a
a
0
0
0
0
1
0
0
0
1
0
0
a
a
a
0
a
a
a
a
0
a
a
1
0
a
0
1
a
a
0
0
1
0
0
0
1
1
0
a
a
1
0
0
1
0
0
1
0
1
1
a
1
1
0
0
a
a
0
1
0
1
1
0
1
0
a
0
0
a
1
a
a
a
0
1
1
0
a
a
0
0
a
1
1
1
1
1
1
1
1
0
1
0
1
a
a
a
a
1
a
a
0
1
0
0
1
1
0
0
1
0
a
1
a
a
1
0
1
0
1
a
1
a
a
1
0
4
4
0
0
1
0
1
0
1
1
1
1
1
1
0
;
0
0
1
0
1
1
0
1
1
a
0
1
a
1
1
1
1
0
a
0
0
0
1
0
1
1
1
0
1
0
a
a
a
1
d
a
a
0
d
1
1
0
a
1
a
1
1
1
1
1
1
1
1
0
1
1
1
0
0
a
a
0
0
0
0
1
0
(}
a
a
0
0
0
0
0
0
0
36
38
c
a
c
a
39
8
8
40
41
/
I
/
I
42
0
43
44
45
0
a
a
a
a
a
a
a
35
37
0
a
a
a
a
a
a
a
a
a
a
a
33
34 .
46
,
..7
7
,
7
1
0
0
0
0
a
0
0
0
0
0
a
a
1
1
1
1
a
0
a
a
a
0
1
1
1
1
0
1
0
0
1
1
1
0
a
a
a
0
1
1
NULL
0
0
1
1
0
49
NULL
0
0
1
1
0
50
NULL
NULL
0
1
1
a
1
0
a
0
0
a
0
a
a
0
a
a
a
a
a
a
a
a
a
a
1
1
0
0
1
1
0
0
0
0
0
0
1
1
1
1
0
1
1
1
0
1
1
a
1
a
a
1
1
1
a
a
1
1
0
1
1
1
1
1
1
1
a
a
0
a
a
a
a
0
0
a
a
1
a
a
a
a
a
a
a
a
0
1
a
0
1
1
1
1
1
a
a
a
a
a
a
a
a
a
a
a
a
1
1
a
a
a
1
a
a
a
1
1
a
a
a
1
a
a
a
a
(Ba
B7
B6
B5
B4
52
f
f
0
53
u
u
54
v
v
a
a
55
3
3
0
a
a
58
NULL
NULL
NULL
59
NULL
56
57
60
61
9
x
9
x
62
m
m
63
1
1
0
1
1
1
0
a
1
1
1
a
0
0
1
1
1
0
a
0
a
1
1
1
1
1
a
1
1
a
1
1
0
a
1
1
1
1
1
a
1
1
1
1
1
1
I
a
1
0
a
a
a
a
a
1
1
1
1
1
1
128
64
32
16
a
4
2
1
(Aa
A7
A2
A,)
0
a
a
1
0
0
1
m
1
48
51
."
1
20
19
1
0
o
1
0
0
C1I
N
W
a
a
a
0
3:
3:
1
a
1
1
0
a
a
a
a
a
a
a
a
a
1
1
1
1
1
1
1
0
a
a
0
1
B3
B2
B,)
0
0
(ROM ADDRESS IN BINARY)
As
As
A4
A3
8·33
W
LL
g
code conversion table-selectric-to-EBCDIC(con't)
N
It)
:!
:!
FUNCTION
INPUT
.......
CODE
OUTPUT
C
W
LL
D
E
C
A
S
E
RS
-
0
1
0
0
ROM
SELECTRIC EBCDIC
ADDRESS
SYMBOL
SYMBOL
o
M
N
~
:!
:!
0
6'
65
B
B
0
1
0
66
W
W
0
1
0
SELECTRIC
R2
Rl R2A
Tl
T2
0
1
2
0
0
1
1
EBCDIC
4
3
S
6
7
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
0
0
0
1
0
1
1
1
0
0
1
1
0
1
(
(
0
1
0
0
0
0
1
1
1
0
0
1
1
0
1
68
a
a
0
1
0
0
0
1
0
0
1
1
0
1
1
0
0
0
69
K
0
0
0
1
0
1
1
1
0
1
0
0
1
0
1
0
1
71
<
72
Y
,
•
1
70
,
0
67
K
Y
.,
0
0
0
1
1
0
0
1
0
0
1
0
0
0
0
1
1
1
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
0
1
1
1
0
1
0
0
0
0
1
73
H
H
0
1
0
0
1
0
0
1
1
1
0
0
1
0
0
0
7'
75
S
S
0
1
0
0
1
0
1
0
1
1
1
0
0
0
1
0
I
I
0
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
76
P
P
0
1
0
0
1
1
0
0
1
1
0
1
0
1
1
1
77
E
0
1
0
0
1
1
0
1
1
1
0
0
0
1
0
1
78
E
"
"
0
1
0
0
1
1
1
0
0
1
1
1
1
1
1
1
79
%
%
0
1
0
0
1
1
1
1
0
1
1
0
1
1
0
0
80
NULL
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
81
NULL
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
82
NULL
0
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
+
NULL
+
0
8.
0
1
0
1
0
1
0
0
0
1
0
0
1
1
1
0
85
N
N
0
1
0
1
0
1
0
1
1
1
0
1
0
1
0
0
1
0
1
0
1
1
0
0
1
0
0
1
0
1
1
@
@
0
1
0
1
1
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
83
86
1
0
1
88
NULL
0
1
0
1
1
0
0
89
NULL
0
1
0
1
1
0
0
1
0
0
0
0
0
0
0
0
90
NULL
0
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
91
NULL
0
1
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
87
92
J
J
0
1
0
1
1
1
0
0
1
1
93
T
T
0
1
0
1
1
1
0
1
1
1
1
0
0
NULL
9'
95
Z
Z
1
0
0
1
0
1
1
1
1
1
1
1
1
0
1
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
1
1
0
1
1
1
0
0
0
0
1
1
1
0
1
1
0
0
0
0
0
1
0
97
98
NULL
0
99
NULL
0
0
1
100
0
1
1
1
101
C
C
0
1
1
0
0
1
102
A
A
0
1
1
0
0
1
1
1
0
NULL
NULL
96
0
0
103
*
*
0
1
1
0
0
1
1
1
0
1
0
1
1
0
10.
?
?
0
1
1
0
1
0
0
0
0
1
1
0
1
1
1
105
L
L
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
106
0
0
0
1
1
0
1
0
,
1
0
1
1
0
1
0
1
1
0
107
$
$
0
1
1
0
1
0
1
1
0
1
0
1
0
1
1
0
1
1
0
1
1
0
0
0
1
1
1
1
0
1
0
D
D
0
1
1
0
1
1
0
1
1
1
0
0
0
1
0
0
108
109
1
1
1
110
R
R
0
1
1
0
1
1
1
0
1
1
0
1
1
0
0
1
111
&
&
0
1
1
0
1
1
1
1
0
1
0
1
0
0
0
0
0
0
0
112
NULL
0
1
1
1
0
0
0
0
0
0
0
0
0
113
NULL
0
1
1
1
0
0
0
1
0
0
0
0
0
0
0
"'
NULL
0
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
NULL
0
1
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
1
0
0
115
0
116
F
F
0
1
1
1
0
1
0
0
1
1
117
U
U
0
1
1
1
0
1
1
1
1
V
0
0
1
#
1
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
1
1
1
1
0
1
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
121
NULL
NULL
0
1
1
1
1
0
0
1
0
0
0
0
0
0
0
0
122
NULL
0
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
118
V
119
#
120
1
0
1
1
1
0
0
NULL
0
1
1
1
0
1
1
0
0
0
0
0
0
0
0
12.
G
G
0
1
1
1
1
1
0
0
1
1
0
0
0
1
1
1
125
X
X
0
1
1
1
1
1
1
1
1
1
0
0
1
1
1
126
M
M
0
1
1
1
1
1
0
1
0
1
1
0
1
0
1
0
0
127
+
NULL
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
128
4
2
64
32
16
a
(ROM ADDRESS IN BINARY)
1
IAa
A7
IBa
B7
B6
BS
84
B3
B2
123
8-34
OUTPUT
INPUT
A6
1
As
A4
A3
A2
AI)
Bl)
~
~
~
code conversion table-EBCDIC-to-selectric
FUNCTION
INPUT
ROM
ADDRESS
EBCOIC
SYMBOL
OUTPUT
E
,
2
5
6
7
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
1
0
0
d
1
0
0
0
0
1
0
0
1
1
0
0
0
0
1
0
1
0
f
1
0
0
0
0
1
1
0
0
9
1
0
0
0
0
1
1
1
1
0
1
1
h
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
0
1
0
0
0
1
0
1
0
0
0
0
0
129
SOH
,
,
130
STX
b
b
131
ETX
c
c
132
PF
d
133
HT
,
,
134
LC
f
135
DEL
9
h
138
139
-
,
,
SMM
VT
o
m
........
C
0
0
."
OUTPUT
EBCOIC
3
4
SELECTRIC
SYMBOL
NUL
137
INPUT
P
A
R
I
T
Y
128
136
N
W
COOE
C
A
S
E
0
SELECTRIC
Rl R2A
R5
R2
~
~
T,
T2
0
0
1
1
0
0
0
1
1
0
1
1
1
0
1
1
0
1
0
1
0
0
1
1
0
0
1
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
1
0
1
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
FF
-
1
0
0
0
1
1
0
0
0
a
0
0
0
0
0
0
141
CR
-
1
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
142
SO
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
143
SI
-
1
0
a
0
1
1
1
1
0
0
0
0
0
0
0
0
144
OLE
-
1
0
0
1
a
0
0
0
0
0
0
0
0
0
0
0
145
DCl
J
J
1
0
0
1
0
0
0
1
0
0
0
1
1
1
0
0
k
1
0
0
1
0
0
1
0
1
0
0
0
0
1
0
146
DC2
k
147
TM
I
I
1
0
0
1
0
0
1
1
0
0
1
0
1
0
0
1
148
RES
m
m
1
a
0
1
a
1
0
0
0
0
1
1
1
1
1
0
149
NL
n
n
1
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
150
8S
0
0
1
0
0
1
0
1
1
0
0
0
1
0
1
0
1
0
151
IL
p
0
0
1
0
1
1
1
1
0
0
0
1
1
0
0
CAN
q
P
q
1
152
1
0
0
1
1
0
0
0
0
0
0
0
0
1
0
0
153
EM
1
0
0
1
1
0
0
1
1
0
1
0
1
1
1
0
154
CC
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
155
CUl
1
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
156
I FS
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
157
IGS
-
1
0
0
1
1
1
0
1
0
0
a
0
0
0
0
0
158
IRS
-
1
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
159
IUS
-
1
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
160
OS
-
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
161
50S
1
0
1
0
0
0
0
1
0
0
·0
0
0
0
0
0
162
FS
0
0
1
0
1
0
1
163
164
BYP
165
LF
166
ETB
167
ESC
168
,
1
,
,
1
0
1
0
0
0
1
0
1
0
t
t
1
0
1
0
0
0
1
1
1
0
0
1
1
1
0
u
u
1
0
1
0
0
1
0
0
1
0
1
1
0
1
0
1
"
w
"w
1
0
1
0
0
1
0
1
1
0
1
1
0
1
1
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
1
0
x
1
0
1
0
0
1
1
1
0
0
1
1
1
1
0
1
y
1
0
1
0
1
0
0
0
0
0
0
0
1
0
0
0
x
y
,
,
0
1
0
1
0
0
1
0
0
0
1
1
1
1
1
170
SM
1
0
1
0
1
0
1
0
0
0
0
0
1
1
0
1
a
1
1
0
0
0
0
0
0
1
a
c0
a
a
0
CU2
0
0
0
a
a
a
0
171
169
1
1
0
1
1
a
0
0
0
0
0
173
ENQ
1
0
1
0
1
1
0
1
0
0
0
0
0
0
0
0
174
ACK
-
1
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
175
BEL
-
1
0
1
0
1
1
1
1
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
a
a
0
0
0
172
176
1
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
-
1
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
-
1
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
1
177
178
SYN
179
180
PN
181
RS
182
UC
183
EOT
-
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
1
0
0
0
0
a
0
0
1
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
1
1
0
0
0
0
0
0
0
0
0
184
-
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
185
-
1
0
1
1
1
0
0
1
0
0
0
0
0
0
0
0
186
-
1
0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
187
CU3
-
1
0
1
1
1
0
1
1
0
0
0
0
0
0
0
0
188
DC4
-
1
0
1
1
1
1
0
0
0
0
0
0
0
a
0
0
189
NAK
1
0
1
1
1
1
0
1
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
B4
B3
B2
190
191
SUB
-
1
0
1
1
1
1
1
1
12S
64
32
16
S
4
2
1
(AS
A7
A2
Al)
0
0
0
0
(BS
B7
B6
B5
o
m
."
1
140
,
U1
N
W
(ROM ADDRESS IN BINARY)
A6
A5
A4
A3
B,)
835
W
LL
o
code conversion table-EBCDIC-to-selectric(con't)
M
N
Lt)
FUNCTION
~
~
.......
INPUT
COOE
OUTPUT
W
LL
o
ROM
ADDRESS
M
N
'It
~
~
192
193
Space
-
A
A
194
195
196
197
198
B
B
C
C
D
D
E
E
199
200
201
202
203
204
205
206
207
208
209
210
211
212
F
F
G
G
H
H
I
I
i
i
<
-
(
(
t
,
t
&
&
J
J
K
L
K
L
M
M
213
N
N
214
215
216
217
218
219
220
221
222
223
224
225
226
227
0
P
0
P
Q
Q
R
!
$
$
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
8-36
EBCDIC SELECTRIC
SYMBOL
SYMBOL
• or
R
*
.
)
)
;
-
;
I
S
T
I
S
T
U
V
U
W
V
W
X
y
X
y
Z
Z
%
-or-
%
-
>
?
?
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
#
#
@
@
"
"
INPUT
OUTPUT
P
A
R
I
C
0
D
E
1
2
EBCDIC
3
4
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
0
0
0
1
0
0
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
0
1
1
1
0
0
1
1
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
7
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
6
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
S
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
128
64
32
16
8
4
2
(ROM ADDRESS IN BINARYI
(AS
A7
A6
AS
A4
A3
A2
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
E
RS
0
0
0
0
1
0
0
0
1
1
0
1
0
0
0
1
1
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
0
1
0
0
0
0
1
0
1
0
1
1
0
0
0
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
0
0
1
1
0
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
B7
B6
0
1
0
1
1
0
1
1
0
0
,
SELECTRIC
R2
Rl R2A
Y
1
1
A
S
0
1
0
1
0
1
0
0
1
C
T
1
1
0
0
1
0
All (B8
0
0
1
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
0
1
0
1
1
0
0
0
0
0
0
0
1
U
1
0
1
1
1
0
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
1
1
1
1
0
1
1
1
0
0
1
0
1
1
1
0
1
1
0
1
1
1
0
0
1
Tl
T2
0
1
0
0
1
0
0
0
0
0
0
0
1
1
1
0
1
0
0
1
0
0
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
0
0
1
1
1
0
1
0
1
0
1
1
0
0
0
0
1
0
0
0
1
0
0
1
1
0
0
1
0
0
1
0
0
0
1
1
1
1
1
0
0
1
0
1
0
0
1
0
0
1
0
1
1
0
1
0
0
0
0
0
1
1
1
u
0
0
0
0
1
1
0
0
1
0
1
0
0
1
0
0
0
1
1
1
1
1
1
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
1
1
1
0
1
1
1
1
1
0
0
1
0
0
1
0
1
0
0
0
BS
B4
B3
B2
B,I
1
1
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
1
1
0
1
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
0
0
1
1
0
1
1
1
1
1
1
1
0
1
ROM Code Converters
MM4230JT/MM5230JT BCDIC to EBCDIC/
EBCDIC to BCDIC code converter
general description
The MM4230JT IMM5230JT is a 2048-bit read-only
memory that has been programmed to convert from
the 64-entry, 6-bit Binary Coded Decimal Inter-
Character assignments for the EBCDIC are given
to IBM 1130 specifications. AI! the non-alphanumeric assignments in BCDIC are subject to specialist usage, and care should be taken over them.
change Code (BCDIC) to the eight-bit extended
BCD interchange code (EBCDIC) and back again.
The tables show the two translations in binary.
connection diag ram
For electrical, environmental and mechanical details, refer to the MM4230/MM5230 data sheet.
Dual -I n- Li ne Package
INPUT A,
"
'00
INPUT A,
INPUT A,
OUTPUTB,
INPUTA.
OUTPUTB,
INPlITA,
OUTPUTB3
INPUTA.
OUTPUTB,
INPUIA,
OUTPUTB,
IHPIITA.
DUfPUTD,;
'"
MODE
OUTPUTS,
CONTROL
CHIP
OUTPUTB"
ENABLE
'" "
INPUTA.
Order Number MM4230JT/J
or MM5230JT I J
See Package 11
Order Number MM5230JT/N
See Package 18
typical applications
BCDIC to EBCDIC
I
tAg
13
tel/IP
ENA8LE
"~t,,
1\
ao_l.
608K:
I
I OM1404
tMOOE
CONTROL
~16
AoIIIGH
"
A,IIIGII
:I
I
(EBCDIC
HIGH
410UTl'UTS TRUE
I
[}M881D
a,IIM8812
"
"
I
I
:J
".
"''' BCDIC
''''
TRUE
INPUT
jl
I"
I
I
l
co.
tSee opmtiny mode notes. (MM4230 data sheet.)
-oR values ~~!l vary from 581Hl. to 30 kH.
8-37
..,
I-
o
typical applications (con't)
M
N
It)
~
~
........
..,o
I-
EBCDIC to BCDIC
M
N
'"
~
+12V
~
~
'2~
I
...
I:
HIGH
TAUE
o,DM8812
6.8K
UK
"r~
.. r"
:
l.DK3.0k3.0K3.0K3.0K3.0K3.0K·~11
"
"
"
f
:
+tv
6.lK
tMODE
~18
DM8Btn
6.8K
I
I
CONTROL
Aa LOW
6.11(
lUI(
tCHIP
ENABLE
'">OM
~'L'~-+--+--+--t--+--r1
'.
DTLmLlOG1C
lICDle
OUTPUT
.,
HIGH
TRUE
H~-~:~ j
INPUT
~24
I
tSee operating mode notes. (MM4230 data sheet.)
"R values can vary from 6801l to 30 kr!.
8-38
s:
s:
code conversion tables
~
N
W
o
c..
BCDIC to EBCDIC
-I
.......
FUNCTION
ROM
ADDRESS
s:
s:U1
CODE
INPUT
OUTPUT
BCDIC
SYMBOL
EBCDIC
SYMBOL
NULL
NULL
OUTPUT
EBCDIC
Bs
B4
B3
B2
B,
0
0
Ba
B7
B6
0
0
0
0
0
0
I
I
I
I
I
I
I
0
0
0
I
2
2
2
I
I
I
I
0
I
0
3
3
3
I
I
I
1
0
0
4
4
4
I
I
I
I
0
0
I
I
0
0
I
0
0
I
0
I
I
I
0
5
5
5
I
I
1
I
6
6
6
I
I
I
I
7
7
7
I
I
I
I
0
0
I
I
I
8
8
8
I
I
I
I
I
0
0
0
9
9
9
I
I
I
I
I
0
0
I
10
0
0
I
I
I
I
0
0
"
I
I
1
I
0
0
0
0
I
I
@
0
I
I
I
I
I
0
0
0
I
I
I
I
I
0
I
..
0
I
I
I
I
I
1
0
0
I
I
I
I
I
I
I
Space
0
I
0
0
0
0
0
0
0
"
12
"
@
13
14
15
16
Space
17
/
/
0
I
I
0
0
0
I
18
S
S
I
I
I
0
I
0
T
T
I
I
I
0
0
0
19
0
0
I
I
20
U
U
I
I
I
0
0
I
0
21
V
V
I
I
I
0
0
I
0
I
22
W
W
I
I
I
0
0
I
I
0
23
X
X
I
I
I
0
0
I
I
I
24
Y
Y
I
I
I
0
I
0
0
0
Z
Z
I
I
I
0
I
0
0
I
26
NULL
NULL
0
I
0
0
0
0
0
0
0
I
I
0
I
0
I
I
0
0
%
%
I
I
0
I
I
0
0
I
I
0
I
1
0
I
30
>
>
0
I
I
0
I
I
I
0
31
?
?
0
I
I
0
I
I
I
I
0
I
I
0
0
0
0
0
33
J
J
I
I
0
I
0
0
0
I
34
K
K
I
I
0
I
0
0
I
0
28
29
32
L
I
I
0
I
0
0
I
I
36
M
M
I
I
0
I
0
I
0
0
37
N
N
I
I
0
I
0
I
0
I
38
I
I
0
35
L
I
0
0
I
0
I
0
39
P
P
I
I
0
I
I
I
I
I
40
Q
Q
I
I
0
I
I
0
0
41
R
R
I
0
I
I
0
I
42
!
,
1
0
0
0
I
0
I
I
0
I
0
43
44
$
$
0
I
0
45
)
)
47
-,
-,
48
&
49
A
46
I
I
I
I
0
I
I
0
I
I
0
0
0
0
I
0
I
I
I
0
I
0
I
0
I
I
I
I
0
0
I
0
I
I
1
I
I
&
0
I
0
1
0
0
0
0
A
I
I
0
0
0
0
0
I
0
50
B
B
I
I
0
0
0
0
1
51
C
C
I
I
0
0
0
0
I
I
52
0
0
I
I
0
0
0
I
0
0
53
E
E
I
I
0
0
0
I
0
I
54
F
F
I
I
0
0
0
I
1
0
55
G
G
I
I
0
0
0
I
I
1
56
H
H
I
I
0
0
I
0
0
0
57
I
I
I
I
0
0
I
0
0
I
I
0
I
0
•
0
0
0
59
•
I
0
I
0
0
I
0
I
I
60
<
<
0
1
0
0
I
1
0
0
I
58
oc..
-I
0
25
27
N
W
61
(
(
0
1
0
0
1
0
I
62
+
+
0
I
0
0
I
I
1
0
63
I
I
0
I
0
0
I
I
I
I
8-39
code conversion tables(con't)
BCDIC to EBCDIC lcon't)
FUNCTION
ROM
ADDRESS
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
OUTPUT
BCDIC
SYMBOL
EBCDIC
SYMBOL
0
1
0
1
2
2
3
4
5
6
3
4
5
6
NULL
NULL
7
8
9
7
8
9
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
83
84
85
86
87
88
NULL
NULL
NULL
NULL
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
12.
125
126
127
8·40
CODE
INPUT
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NUL.L
NULL
NULL.
NULL
NULL
NULl.
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL.
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL.
NULL
NULL
NULL
OUTPUT
EBCDIC
Ba
B7
B6
B5
B.
B3
B2
B1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NULL
NULL
NULL
NULL
NULL
0
0
0
0
0
NULL
a
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
a
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
a
a
0
0
0
0
a
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
a
a
0
0
0
0
0
a
0
1
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
a
a
0
0
3:
3:
code conversion tables(con't)
-'="
N
W
o
c..
EBCDIC to BCDIC
-I
.......
FUNCTION
OUTPUT
ROM
ADDRESS
EBCDIC
SYMBOL
BCDIC
SYMBOL
128
NULL
NULL
129
NULL
NULL
0
0
130
NULL
0
0
NULL
0
0
0
132
NULL
NULL
NULL
NULL
0
0
0
0
0
133
-
-
0
0
0
I
0
0
0
0
I
0
0
0
0
0
0
0
0
0
0
0
0
131
134
135
NULL
136
NULL
137
NULL
NULL
139
•
•
140
<
<
141
138
3:
3:
CODE
INPUT
OUTPUT
BCOIC
B5
B.
U'1
B2
B,
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I
0
0
0
0
I
I
I
0
I
0
0
I
I
I
0
I
1
0
0
I
I
I
I
0
0
B8
B7
B6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B3
I
I
0
0
I
I
I
0
I
0
0
1
1
I
I
I
0
143
I
I
0
0
I
I
I
I
1
I
144
&
&
0
0
I
I
0
0
0
0
145
NULL
NULL
147
NULL
NULL
NULL
NULL
0
146
148
NULL
NULL
142
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
,
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
$
0
0
I
0
I
0
I
0
0
0
I
0
I
0
I
I
0
0
149
150
151
NULL
152
NULL
153
,
154
$
NULL
NULL
155
156
}
157
158
}
-,
"
I
0
0
I
0
I
I
0
0
I
0
I
1
0
I
0
0
I
0
I
I
1
0
I
0
I
1
I
160
I
I
0
0
I
0
0
0
0
0
161
.J
.J
0
0
0
I
0
0
0
1
159
0
0
I
162
NULL
NULL
0
0
0
0
0
0
NULL
NULL
0
0
0
0
0
0
0
0
0
163
164
NULL
NULL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
166
NULL
NULL
NULL
NULL
0
0
0
0
0
0
0
167
NULL
NULL
0
0
0
0
0
0
0
0
168
NULL
NULL
0
0
0
0
0
0
0
0
169
NULL
NULL
0
0
0
0
0
0
0
0
170
NULL
NULL
0
0
0
0
0
0
0
0
0
0
0
I
I
0
I
1
0
0
0
I
1
I
0
0
165
171
172
%
%
>
0
0
0
0
I
I
I
0
I
,
>
,
0
0
0
I
1
1
1
0
0
0
0
I
1
1
I
1
176
NULL
NULL
0
0
0
0
0
0
0
0
177
NULL
NULL
0
0
0
0
0
0
0
0
178
NULL
NULL
0
0
0
0
0
0
0
0
179
NULL
NULL
0
0
0
0
0
0
0
180
NULL
NULL
0
0
0
0
0
0
0
0
181
-
-
0
0
0
I
0
0
0
0
182
-
0
0
0
I
0
0
0
0
183
NULL
0
0
0
0
0
0
0
0
184
NULL
NULL
NULL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
185
NULL
NULL
186
0
0
187
#
#
0
0
0
I
0
I
1
188
@
@
0
0
0
0
I
1
0
0
0
0
0
0
1
1
0
I
189
c..
-I
0
175
173
174
N
W
o
190
"
0
0
0
0
1
1
I
0
191
"
0
0
0
0
1
1
1
1
8-41
..,o
I-
code conversion tables(con't)
M
N
it)
:i!
:i!
EBCDIC to BCDIC (con't!
.......
..,
I-
FUNCTION
o
M
N
-.:t
:i!
:i!
8-42
INPUT
OUl1'UT
ROM
ADDRESS
EBCDIC
SYMBOL
BCDiC
SYMBOL
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
-
-
A
B
A
C
B
C
D
D
E
E
F
F
G
H
G
H
I
I
NULL
NULL
NULL
CODE
OUl1'UT
BS
B7
as
BCDIC
B5
B4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
B3
B2
Bl
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
1
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
NULL
0
0
0
0
0
0
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
J
J
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
NULL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
K
K
L
M
L
M
N
N
a
a
P
P
Q
Q
R
R
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
S
T
NULL
S
T
NULL
U
U
V
V
W
W
X
X
V
Z
V
Z
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
NULL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
ROM Code Converters
MM4230KP/MM5230KP ASCII-7 to selectric code converter
general description
The MM4230KP/MM5230KP MOS read-only memory has been programmed to perform the conversion between the American Standard Code for
Information Interchange in seven bits (ASCII)
and the Selectric correspondence bail code transmitted and received by the IBM Series 7 inputl
output printers.
application hints
The ASC II field and Selectric bail code field as
defined do not map exactly: for instance "space"
is handled as a normal 7-bit code in ASCII, but is
handled as a unique switch and solenoid pair in the
Selectric printer. And even among the graphic
characters, ± and ri exist only for Selectric, and>
and
only for ASCII. The former problem is
handled in the MM4230KP/MM5230KP by exploiting the inherent redundancy of the bail code
(see Table 2). The latter inconsistency is resolved
by making arbitrary equivalences between the
unique characters. The two tables show the treatment of both the characters which have equivalents
in both codes, and those characters, and the functions, which do not. Encoding and decoding the
Selectric functions that the user requires is a
matter of conventional Boolean logic. A typical
example is shown below.
<
For electrical, environmental and mechanical details, refer to the MM4230/MM5230 data sheet.
typical applications
" HI---<{>---.J
.-+-I-l-U-..--
"H-------R5 ii~:~iH,~tE'NPUTS
"[_...:.:.::;;/..,;,)0----,,
ABOVE
n--~--4-----ff
I
BAIL CODE FRIlM
CONVERTER
lOW TRUE
iff
"
"
L
I
I
I
_ _ _ _ ...l
tM351 PERIPKERAL
IIRIVER
Order Number MM4230KP-2/J or MM5230KP-2/J
Order Number MM5230KP-2/N
See Package 11
See Package 18
8-43
code conversion tables
Table 1. ASCII·7 to Selectric
~h'
s
,
b4
b3
b2
+
+
+
~
~n
Row+ -
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
1
0
1
0
A
1
0
1
1
B
1
1
0
0
C
1
8-44
bl
1
0
1
D
1
1
1
0
E
1
1
1
1
F
0
0
0
0
0
0
0
1
1
02
12
STX
22
ETX
DB
NAK
1B
ACK
SYN
23
33
BS
42
HT
A
0
a
q
"
2
B
R
b
r
""
3
C
S
c
s
$
4
D
T
d
t
%
5
E
U
e
u
&
6
F
V
f
v
7
G
W
9
w
I
8
H
X
h
x
)
9
I
Y
i
y
.
J
Z
j
z
+
K
2B
3B
CAN
4A
25
EM
52
LF
53
VT
72
FF
72
CR
5A
SUB
6A
ESC
7A
FS
4B
GS
53
SO
58
<
40
-
SI
6B
US
73
=
>
RS
63
7B
1
0
1
ETB
BEL
1
!
3A
03
ENO
13
1
1
1
P
DC3
DC4
0
@
62
IA
DC2
2A
EOT
1
0
0
OA
32
0
5
SP
DCI
SOH
1
1
4
2
DLE
1
3
1
NUL
0
0
50
/
?
L
M
N
0
[
7F
\
60
J
77
6
7
25
P
k
I
I
:
m
I
1\
70
-
n
0
7F
48
77
- 58
DEL
00
1
code conversion tables (con't)
Table 2. Selectric to ASCII-7
Rs
,
T,
0
R2A
R2
R,
j j
j j
0
0
0
0
TS
Row
-
0
0
1
1
0
1
2
b
w
0
0
T2
S
0
0
0
0
-
2/0
h
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
Q
k
0
1
0
1
5
P
e
0
1
1
0
6
y
1
3
4
5
6
7
0
3/0
I
I
6/C
4
6/F
~ ~A;( W; ~ W r1~;« ~ ~~
~ ~ ~ ~ ~ ~ ~ ~~
"
3/D
i
6
n
2/C
5
2/7
2/E
Y21
a
8
d
r
7
f
u
v
3
z
9
x
m
1
7
J
t
1
0
0
0
8
-
6
W
(
1
0
0
1
9
y
H
S
)
1
0
1
0
A
1
0
1
1
6
1
1
0
0
C
1
1
0
1
1
1
1
0
2/1
3/6
c
2
1
~* ~ ~ ~
L
?
0
$
4/F
~ ~ ~ ~ ~ ~ ~~ ~
~ ~~~~~~ ~
.
Q
K
0
P
E
E
+
N
F
~~ ~ ~/~ ~
9
1
1
1
0
1
1
1
1
1
0
1
1
0
0
0
s
1
1
I
0
1
1
0
1
ri
I
4/9
"
6/3
2/C
%
2/E
@
F
C
A
D
R
U
V
%.0
J
T
F/F
Z
G
X
M
&
#
±[
5/B
ASCII shown thus. Column No.!Row No.
8-45
ROM Code Converters
MM4230QW/MM5230QW hollerith to EBCDIC code converter
general description
The MM42300W/MM52300W 2048-bit MaS read
only memory has been programmed to convert the
12 line Hollerith Code to the 8 line EBCDIC Code.
Three TTL 4-input NAND gates and three TTL
inverters are used to compress the 12 Hollerith
lines to eight line binary encoded form suitable
for use by the ROM.
For electrical, environmental and mechanical details, refer to the MM4230/MM5230 data sheet.
typical application
Hollerith to EBCDIC
MODE
CUNTRDL
41NPlITNAND GATES ARE
IlM14JDTYPES
OllTl'UT.
ASCI/_S
",
PUNCHED
CARD
DATA
INPUT
A5 20
'"'~~~;
1\6 ,9
(
,: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~A1
18
,,------------------"'-1
= GNO, VGG '" -12V ±10%.
Note 2: The Hollerith input data (lines 1 through 12) is cOllsidered to be from
normallv open switches returned, in the case of a punched hole, to GND as shown.
Note 1: Vss '" +12V ±10%, VDO
ANY DTl!lTl
HIGH
DEVICE
TRUE
~j'." ~ju,
"::"
lINES1T01
":"
lINESBT012
connection diagram
Dual-In-Line Package
"
'.
"
"
"
"
"
"
"
Vss
8-46
"
'.
Order Number MM4230QW/J or MM5230QW/J
See Package 11
Order Number MM5230QW/N
See Package 18
MODE
CONTROL
CHIP
ENABLE
12
'---------'
'.
code conversion table
Hollerith to EBCDIC
12
12
12
11
11
0
0
8-2
11
0
&
-
SP
I
,,
1
A
J
/
1
a
j
2
B
K
S
2
b
k
I
12
11
0
12
12
11
0
0
11
0
12
11
0
80
90
AO
BO
31
41
51
El
71
9
-1
22
SYN
42
52
62
72
9
-2
70
49
59
69
Bl
SOH
DCl
21
s
B2
STX
DC2
~
12
11
8-1
3
C
L
T
3
c
I
t
B3
ETX
DC3
23
33
43
53
63
73
9
-3
4
D
M
U
4
d
m
u
B4
04
14
24
34
44
54
64
74
9
-4
5
E
N
V
5
e
n
v
B5
HT
15
LF
35
45
55
65
75
9
-5
6
F
a
w
6
f
0
w
B6
06
BS
ETB
36
46
56
66
76
9
-6
7
G
P
X
7
9
P
x
B7
DEL
17
ESC
EaT
47
57
67
77
9
-7
8
H
0
Y
8
h
q
Y
B8
08
CAN
28
38
48
58
68
78
9
-8
9
I
R
Z
9
i
r
z
B9
09
EM
29
39
NUL
OLE
20
30
9-8-1
1
\
[
8-3
$
8-4
<
*
%
8-5
(
)
-
8-6
+
>
8-7
!CD A@
?
8A
9A
AA
BA
OA
1A
2A
3A
CA
OA
EA
FA
9-8-2
#
8B
9B
AB
BB
VT
lB
2B
3B
CB
DB
EB
FB
9-8-3
@
8C
9C
AC
BC
FF
FS
2C
DC4
CC
OC
EC
FC
9-8-4
8D
90
AD
BD
CR
GS
ENO
NAK
CO
DD
ED
FD
9-8-5
~
8E
9E
AE
BE
SO
RS
ACK
3E
CE
DE
EE
FE
9-8-6
"
8F
9F
AF
BF
SI
US
BEL
SUB
CF
DF
EF
FF
9-8-7
CD may be "I"
@ may be ","
Note: Unassigned entries e.g. AF refer to the EBCDIC code as a 16 x 16 table, column then row, in hexidecimal notation.
Note: The relationship between Hollerith as 256 valid punch combinations and EBCDIC as eight binary digits is well
established. This converter conforms to this practice. The assignments shown in the table above are the recommendations
of the American National Standards Institute. For details on alternate non-alphanumeric graphic and control codes, see
ANSI x 3.26 - 1970.
8·47
ROM Code Converters
MM4230QX/MM5230QX
EBCDIC-8 -to- ASCII-8 code converter
general description
The MM42300X/MM52300X is a 2048·bit read
only memory that has been programmed to con·
vert Extended Binary Coded Decimal Interchange
Code (EBCDIC) to the American Standard Code
for Information Interchange extended to eight bits
(ASCII·8).
lished by the American National Standard ANSlx
3.26-1970. Exact details are shown in the code
table.
For electrical, environmental and mechanical de·
tails, refer to the MM4230/MM5230 2048·bit read
only memory data sheet.
The conversion conforms to the practice estab·
typical application
connection diagram
Dual-I n-line Package
-12V----------------....-._,
.,,--..-------------+--+-+-~.---
It/PUlA.
'00
It/PUlA,
,so
'0'
UK,
TYPICAL,
INPUlA,
8 LINES
GATES DM7400
B,
ounUTB,
E,
B,
E,
B,
I)\.ITPU182
INPUT As
OUr9\.118 3
INPUlA.
OUTPUT 8.
tNPUTA,
OUTPUTB.
INPUTA.
E,
B.
E.
B,
OUTPUTS6
'00
OUTPUT8,
MODE
CIlNTROL
E.
OUTPUT 8.
B.
M..
"
E.
B,
B,
OlL/TTl LOGIC
8·48
CHIP
ENABLE
INPUlA.
E,
+12V-----..-.........tv;;t~\_---'~j'''----+__I
*Chip Enable'" Logic "'" to obtain outputs.
logic Levels:
DTL/TTl (except at MOS/ROM interface). logic "1," +5.0V. NOM, Logic "0" ground, NOM.
MOS/ROM inputs and outputs. logic "1," more negative, logic "0," more positive.
'"
E.
Order Number MM4230QX/J
or MM5230QX/J
See Package 11
Order Number MM5230QX/N
See Package 18
3:
3:
code conversion table
~
N
W
o
0---0
0
0
1---0
0
0
2---0
5
0
7
I 0I 0I 0I
0
~
Row t
0
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
1
0
0
4
0
1
0
1
5
0
1
1
1
1
0
1
7
0
0
0
0
0
1
1
0
1
0
A
1
0
1
1
B
1
1
1
1
0
1
C
0
1
1
1
0
E
1
1
1
1
F
10
DC'
"
01
STX
OC2
02
12
OC3
13
03
9C
90
HT
3
80
90
81
97
80
18
AO
A9
A'
AA
92
VT
DB
FF
8F
DC
CA
lC
A2
AB
B3
Bo
A3
AC
54
BE
95
A4
AD
BS
BF
17
96
AS
EDT
A6
04
AE
AF
DO
SO
88
98
A7
BO
BB
98
A8
B'
B9
8A
9A
8B
9B
SB
06
BEL
IF
2E
24
C2
60
28
I
23
40
29
SF
27
3E
3D
>
9E
,
2B
·3B
A
21
'A
5E
o ""', t
r;----'
OA
k
b
02
,
63
O.
A
B
01
08
-
64
00
7E
,
73
,
74
OC
m
d
"
75
0
,
65
w
0
66
" 07
,
70
OE
17
OF
P
7B
10
58
71
69
72
09
oA
DB
DC
DO
DE
OF
,
79
3F
22
I
42
7A
4B
M
F
W
40
47
X
50
Y
0
48
49
36
7
SA
5
6
7
38
39
B
9
CB
02
E2
E8
EE
F4
FA
A
C5
CC
03
E3
E9
EF
F5
F8
B
E4
EA
FO
F6
FC
C
Fo
0
FE
E
CO
04
C7
CE
05
ES
EB
F1
F7
C8
CF
06
E6
EC
F2
F8
C9
DO
07
E7
ED
F3
F9
X
3
4
C4
C6
o
p
2
37
8
9
Z
52
35
0
59
51
A
I
34
5
51
4F
P
G
..
..
55
4E
0
33
4
V
N
45
32
54
U
40
44
1
3
4C
43
U'I
N
W
0
31
53
T
l
:lO
1
2
5
K
E
9F
4A
4'
0
0
5C
70
3:
3:
1
F
E
\
I
C
1
0
J
B
1
1
D
7.
A
EO
E1
1
1
C
p
X
......
1
0
0
H
y
0
@
25
2A
3C
3A
2C
%
I
SUB
07
,
1
#
<
15
05
C'
7C
50
$
14
CO
I
I
NAK
ACK
US
OF
8C
lE
DE
51
B7
89
'0
AS
B6
CA
C3
,
0'
BC
93
ENO
GS
BB
B2
94
DC4
FS
8A
20
I
2F
'9
8E
26
84
,B
EM
•
0
1
0
•
•
7
0
1
1
1
0
1
0
0
1
1
1
1
1
0
0
0
1
0
1
1
0
1
1
83
ESC
CAN
20
9'
ETB
B7
1F
1
1
5
SP
1
0
0
4
'6
08
DEL
1
0
SYN
82
OA
BS
96
2
0
0
1
lF
85
09
•
•
1
0
OLE
00
0
1
0
NUL
ETX
0
0
1
SOH
1
1
0
1
0
0
0
1
0
3---0
4
0
0
EO
FF
F
Hexadecimal EBCDIC
C5 "Character Address
,
lj'___ ~,~---':0
Location in ASCII-8 (ROM ContI
Character Assignment
IIf Any)
8-49
ROM Code Converters
MM4230QYIMM5230QY
ASCII-8 -to- EBCDIC-8 code converter
general description
The MM42300Y/MM52300Y is a 204S-bit read
only memory that has been program med to convert the American Standard Code for Information
Interchange extended to eight bits, (ASCII-S) to
Extended Binary Coded Decimal Interchange Code
(EBCDIC-S)_ The conversion conforms to the practice established by the American National Standard
ANSlx3_26 1970_ Exact details are shown in the
code table.
For electrical, environmental and mechanical details, refer to the MM4230/MM5230 204S-bit read
only memory data sheet.
connection diagram
typical application
....__,
-"v----------------~I-
....
~v--
LS.
GATES OMBII, OR DMII812
E,
E,
E,
E.
E,
E,
E,
...
E,
Dual~ln·Line
Package
----------_=~-_i-_r-t_-~I---
" '
INPllT~
Ag
6.8K,
TyptCAL,
"
..
INPIITA L
aLINES
GATESOM7400
INPUT A,
"
.,
OUTPUTS,
INPLITA.
OUTPUT 8,
INPUT As
"
OUTPUT I.
IIilPUTAe
DUTPlITI4
tNPUTA,
...
...
OUTPUT Is
INPlITAg
..
3
~
i:
'00
OUTPUT'"
Ollll'UTB,
MODE
"
CONTROL
CHIP
ENABLE
OIlTPUTS.
101"'':'"----1--1
..2V-----..~t-t_;;j~~-4_-'j'..
OTL/TTL LOGIC
'n
"
tNPUTAo
TOP VIEW
Order Number MM42300Y IJ
or MM52300Y IJ
Se. Packag. 11
Order Number MM52300Y/N
tMode Control = Logic "0," A8 = LOllic"1."
oIfChip Enable = Logic "1" to obtain outputs.
logic Levels:
DTLITTL (except at MOS/ROM interface). Logic "I," +5.0V. NOM. Logic "0," ground, NOM.
MUS/ROM inputs and outputs. LogiC "1," more negative. Logic "0," more positive.
S-50
See Package 18
s:
s:
code conversion table
,J:o
N
W
o
o
0
,,&-0
b7_0
"a-O
0
~
••• •
0
0
0
0
0
0
0
0
1
0
1
0
0
1
2
0
0
1
1
3
0
1
0
0
4
1
0
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
1
0
1
0
A
1
0
1
1
B
1
1
0
0
C
1
1
0
1
0
1
1
1
1
1
1
0
1
E
F
0
1
NUL
SP
' (j)
11
01
STX
OC2
02
ETX
DC4
37
5
SYN
2F
7
26
CAN
BS
18
16
HT
EM
SUB
3F
25
VT
ESC
9
.
5C
4E
lC
OC
6B
60
AS
IE
DE
SI
US
4B
I
04
6E
A7
A8
A9
I
CO
93
SA
05
94
06
00
-
n
SF
-
6A
I
m
,,0
0
6F
,
92
EO
I
N
61
IF
OF
,
,
91
k
4A
03
7E
/
A6
I
M
10
00
B9
E9
I
02
4C
88
I
L
-
GS
SO
5E
<
AS
w
87
E8
01
A4
h
Z
K
FS
CR
7A
,
86
E7
C9
A3
u
Y
J
99
A2
B4
85
E6
C8
,
98
t
9
X
I
F9
50
27
aB
FF
C7
H
,
E5
W
,
83
I
C6
F8
40
I
19
05
IF
8
82
E4
V
G
F7
70
(
E3
U
C5
F6
50
ETB
,
d
C4
F
81
E2
T
E
6
32
2E
BEL
C3
F5
6C
&
D9
97
q
b
S
0
F4
5B
3D
20
ACK
4
%
C2
p
79
,
08
R
C
F3
7B
3C
NAK
ENa
Cl
7
6
\
07
a
B
3
$
7C
A
F2
7F
#
13
03
ECT
.,
2
12
DC3
1
4F
..
5
0
Al
95
DEL
0
60
, maybe"'"
2 may be "--,"
96
07
1
0
1
0
1
0
1
1
1
0
0
1
0
1
1
0
1
1
P
@
40 o FO
1
1
4
1
0
1
0
0
3
0
10
DCl
0
1
0
1
2
OLE
00
SOH
0
1
1
1
1
0
0
0
0
bS_O
b4 b3 b2 bl Row.-
0
0
0
1
0
1
0
s:
s:
1
1
0
0
1
-<
........
1
1
1
1
0
1
8
9
A
B
C
0
E
20
30
41
58
76
9F
88
21
31
42
59
77
AD
22
lA
43
62
7B
23
33
44
63
24
34
45
64
15
35
46
65
os
36
47
17
OB
48
28
38
1
W
DC
0
o
89
00
1
AA
BA
DE
2
80
AB
BB
OF
3
BA
AC
BC
EA
4
8B
AD
BD
E8
5
66
8C
AE
BE
EC
6
67
80
AF
BF
ED
7
49
68
8E
BO
CA
EE
8
69
8F
Bl
CB
EF
9
B2
CC
FA
10
29
39
2A
3A
52
70
90
2B
3B
53
71
9A
B3
CD
FB
11
12
13
2C
04
54
72
9B
B4
CE
FC
09
14
55
73
9C
B5
CF
FO
OA
3E
56
74
90
B6
DA
El
N
tRow
51
lB
U'I
7.E
F
57
75
9E
DB
B7
o
-<
14
FE
EO
15
FF
The Hexadecimal EBCDIC entry is formed thus:
3 The top line in each entry to the table represents an
assigned character (Columns 0 to 7). The bottom
line in each entry is the corresponding EBCDIC Code,
in hexadecimal notation.
Eight EBCDIC bits
MSB 0 1 2 3
4 5 6 7
1st Digit
2nd Digit
Example: 0 1 0 1
5
1 1 0 0
LSB
or •
C
To convert ASCII·8 asterisk (*) to EBCDIC-S
E8
E,
• in ASCII is a 2A or binary 00101010
applying this as an address to the MM5230QY /MM4230QY
bit-O bit-7
gives the output 0101 1100, which is an EBCDIC-S asterisk.
8-51
ROM Code Converters
MM4230RS/MM5230RS binary to
modulo-n divider code converter
general description
Applying the required division ratio, in binary, to
the inputs of the ROM as shown, generates two
sets of four program inputs, one for each of the
2 DM7520/DM8520 dividers_
The MM4230RS/MM5230RS binary to modulo-n
divider code converter is set up to generate the
program input settings for a pair of DM7520/
DM8520 modulo-n dividers, in order to divide by
any binary number from one to 255. Detailed
instructions for use of the DM7520/DM8520 are
given in its data sheet.
For electrical, environmental and mechanical details, refer to the MM4230/MM5230 data sheet.
connection diagram
Dual~ln-Line
Package
INPllTA,_ 1
INPUTA,- 2
INPUTA,_ 3
Uf--NC
00TI'UT8,-4
21~INPUTA.
OUTPUTB,_5
20 r--INPUTA.
OUTPOT8 3 - 6
19~INPUTA6
See Package 11
OUTI'UT8._1
18!--INPUTA,
Order Number MM5230RS/N
See Package 18
Order Number MM4230RS/J or MM5230RS/J
OU11'UT8 5 - 8
OUTPUTB.-9
16r-VG!;
0IlTI'UT8,_10
00TI'UT8._11
14
f-~~~BLE
VSS-L."_--:,::::"c:,,::::,w,-_'...J3r-- INPUT A9
typical application
Binary to Modulo-n Divider
CONNECT
DIRECT Til
MS'
"
~
BINARY
DIVISDfI
"
"
1
...
"
~
...
I"
'. '"
"
"'.
'.
"
A
"o--D<>----------4--+-I 1
.s. o--j)<>-----------~-IAI
HIGH
TRUE
1"
MODE
CONTROL
~
MM523(1RS
"
".,
-v
."..
--:::
-v
-v
02f-----o-+-~+___If_+--+-of>--o
."..
CHIP
INPUTS
DM1404
0"
~
"1
., I
"
"
J'' ' ' ,
"" f
DIVIDERI
"
o,f-......-Tl-+-l-+---if-+--+---o " J
~lF· f'''~
!
8-52
DM:!~~=~520
J-l
UK
s:
s:
code conversion table
: BY
SETTING
I
DIVIDER 1
DIVIDER 2
~
.
: BY
SETTING
I
..,
165
164
163
162
161
160
159
158
157
156
1
1
1
0
0
0
0
0
1
0
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
1
1
0
1
1
155
154
153
152
151
150
149
148
147
146
1
0
0
0
0
1
0
0
0
0
0
1
0
0
0
1
1
0
1
1
1
0
1
0
0
0
1
1
0
1
145
144
143
142
141
140
139
138
137
136
0
1
1
1
0
0
1
0
1
1
0
0
1
1
1
0
0
1
0
1
1
0
0
1
1
1
0
0
1
0
1
0
1
0
0
1
0
1
1
1
0
1
0
1
0
0
1
0
1
1
1
0
1
0
1
0
0
1
0
1
1
1
1
1
1
0
1
1
1
0
0
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
0
1
1
0
1
1
0
0
0
0
1
1
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
1
1
1
1
1
0
0
0
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
1
1
1
1
1
1
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
1
1
1
1
B.
85
184
B3
B,
B,
1
0
0
1
1
1
1
0
1
1
0
1
0
0
1
1
1
1
0
1
1
0
1
0
0
1
1
1
1
0
1
1
0
1
0
0
1
1
1
1
0
1
1
0
1
0
0
1
1
1
1
0
1
1
0
1
0
0
1
1
1
1
0
1
1
0
1
0
0
1
0
1
1
0
1
1
0
1
0
0
245
244
243
242
241
240
239
238
237
236
0
1
1
1
0
1
0
0
0
1
1
0
1
1
1
0
1
0
0
0
1
1
0
1
1
1
0
1
0
0
0
1
1
0
1
1
1
0
1
0
1
0
1
1
0
1
1
1
0
1
1
1
0
1
1
0
1
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
0
1
1
0
0
0
0
0
235
234
233
232
231
230
229
228
227
226
1
0
1
1
0
0
1
1
1
0
1
1
0
1
1
0
0
1
1
1
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
1
0
0
0
1
1
0
1
1
0
0
1
0
0
0
1
1
0
1
1
0
225
224
223
222
221
220
219
218
217
216
215
214
213
212
211
210
209
208
207
206
0
1
0
1
1
0
1
0
1
0
0
0
1
0
1
1
0
1
0
1
1
0
0
1
0
1
1
0
1
0
1
1
0
0
1
0
1
1
0
1
1
1
1
0
0
1
0
L
1
0
1
0
1
1
1
0
1
0
0
1
1
0
1
0
0
0
0
0
1
1
0
1
0
1
1
0
1
0
1
1
1
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
1
0
1
1
1
0
1
0
1
0
0
1
0
11
1
0
0
0
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
1
0
1
1
1
205
20'
203
202
201
200
199
198
197
196
1
1
0
1
1
1
0
0
1
1
1
1
1
0
1
1
1
0
0
1
1
1
1
1
0
1
1
1
0
0
1
0
0
0
1
1
1
0
0
0
0
1
0
0
0
1
1
1
0
0
0
0
1
0
0
0
1
1
1
0
1
0
0
1
0
0
0
1
1
1
195
19'
193
192
191
190
189
188
187
186
1
0
0
0
0
1
1
0
0
1
1
0
1
1
0
0
1
0
0
1
0
0
1
1
1
0
1
0
1
1
0
1
0
1
1
0
0
1
0
0
1
0
0
1
1
1
0
1
0
1
0
0
1
0
1
1
0
0
1
0
0
1
0
0
1
1
1
0
1
0
0
0
0
1
0
1
1
0
0
1
0
0
1
0
0
1
1
1
0
1
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
0
0
0
0
1
1
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
1
1
1
1
1
0
0
B,
B.
B" B,
B3
B,
B,
0
1
0
0
1
0
0
0
0
0
1
0
1
0
0
1
0
0
0
0
1
1
0
1
0
0
1
0
0
0
1
1
1
0
1
0
0
1
0
0
1
1
1
1
0
1
0
0
1
0
1
1
1
1
1
0
1
0
0
1
1
1
1
1
1
1
0
1
0
0
1
1
1
1
1
1
1
0
1
0
255
254
253
252
251
250
249
248
247
246
0
0
1
1
1
0
1
1
0
0
0
0
0
1
1
1
0
1
1
0
0
0
0
0
1
1
1
0
1
1
0
0
0
0
0
1
1
1
0
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
1
0
1
1
1
0
0
0
0
1
0
0
1
0
0
0
0
0
1
1
0
1
0
1
1
1
0
0
0
0
1
1
0
1
0
0
0
0
0
1
1
0
1
0
1
1
1
0
0
0
0
1
1
0
1
0
0
0
0
0
1
1
0
1
0
1
1
1
0
0
0
0
1
1
0
1
0
0
0
0
0
1
1
0
1
0
1
1
1
0
0
0
0
1
1
0
1
0
0
0
0
0
1
1
0
1
0
1
1
1
0
1
0
0
1
1
0
1
0
0
0
0
0
1
1
1
1
1
1
0
0
1
0
0
0
0
1
1
1
1
0
0
1
0
0
1
0
1
1
1
1
0
0
1
0
0
1
0
1
1
1
1
0
0
1
0
0
1
0
1
1
1
1
0
0
1
1
1
0
0
0
1
0
1
1
0
1
1
1
0
0
0
1
0
1
0
0
1
1
1
0
0
0
1
0
0
0
0
1
1
1
0
0
0
1
0
0
1
0
0
1
0
0
1
1
1
0
1
0
1
1
0
1
1
0
1
0
0
1
0
0
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
0
0
1
0
0
1
0
0
1
1
1
0
1
0
1
1
0
1
0
1
1
0
0
1
0
0
1
0
0
1
1
1
0
1
0
1
1
0
Q
0
1
0
1
0
0
0
1
0
1
0
1
1
1
1
1
1
0
0
1
I
DIVIDER 1
DIVIDER 2
B,
Ba
: BY
SETTING
Ba
DIVIDER 1
:ll
85
184
B3
B,
B,
0
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
0
0
0
1
0
0
1
1
1
1
1
0
0
0
1
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
1
0
1
0
0
0
0
1
1
0
0
1
1
1
1
1
0
0
0
0
0
1
0
1
0
0
0
1
1
1
0
0
1
1
1
1
1
0
1
0
0
0
0
1
0
0
0
1
1
1
1
1
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
0
0
0
0
0
1
0
1
0
0
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
1
1
1
1
0
0
0
1
1
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
1
0
0
0
0
1
1
1
1
0
0
1
0
0
0
0
1
1
1
1
0
0
1
0
0
0
0
1
1
1
55
54
53
52
51
50
49
48
47
46
135
134
133
132
131
130
129
128
127
126
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
1
1
0
0
0
1
0
1
0
0
0
1
1
0
0
0
1
45
44
43
42
41
40
39
38
37
36
1
1
0
1
0
1
0
0
1
0
125
12'
123
122
121
120
119
118
117
116
0
1
0
0
1
1
0
0
1
1
1
0
1
0
0
1
1
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
1
0
1
0
0
0
0
0
1
0
0
1
0
1
0
35
3.
33
32
31
30
29
28
27
26
1
1
0
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
0
115
11.
113
112
111
110
109
108
107
106
0
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
0
1
0
1
1
1
0
1
1
1
1
0
1
0
0
1
1
0
1
1
1
1
0
1
0
0
1
1
0
1
1
1
1
0
1
0
0
1
1
0
1
1
1
1
1
1
0
0
1
1
0
1
1
1
0
1
1
0
0
1
1
0
1
1
25
24
23
22
21
20
19
18
17
16
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
1
1
1
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
1
0
105
104
103
102
101
100
99
1
0
1
1
0
0
0
1
1
1
0
1
0
1
1
0
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
0
1
0
1
1
0
0
0
1
0
1
0
1
0
1
1
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
1
1
1
0
1
0
1
0
1
0
1
15
14
13
12
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
0
1
1
0
0
0
1
1
0
0
0
5
4
3
2
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
o
DIVIDER 2
B.
98
N
W
1
en
.......
s:
s:C1I
N
W
o
:ll
en
11
10
9
8
7
6
8-53
Q.
a::
0-
ROM Code Converters
M
N
an
:;
:;
.......
Q.
a::
0-
M
N
-.;t
MM4231RP/MM5231RP EBCDIC to ASCII-7 code converter
:;
general description
:;
The MM4231RP/MM5231RP is a 2048-bit readonly memory that has been programmed to convert from E 8CDIC, an extended binary coded
decimal interchange code used in the IBM 1130
computer, to ASCII-7, the American Standard
Code for I nformation I nterchange in seven bits_
conversion of the MM4230QX/MM5230QX in that
it follows certain earlier IBM 1130 character assignments_ Also certain EBCDIC control codes are
arbitrarily preserved and translated (see translation chart on truth table)_
For electrical, environmental and mechanical details, refer to the MM4231/MM5231 data sheet_
This conversion differs from the ANSI x 3_26
typical application
EBCDIC TO ASCII-7
...
-
EBCDIC
ASCII
LOW TRUE
LII
BIT
12,15
.
" .,
.
.." .
".
..
.
HIGH TRUE
17
~.~ID
________________________~~~r-~I:>
__
"'~-------------------1~-r--~~~
..~--------------~~-+--~--+-~r.>
MMiZ3tAP
.. ~------------.-~~-+--~--+-~r.>
~b,
.
.
.
b,
A,
8,
11,24,13
r--~~~r-----1r-----1:------1------1---1---t-------Ob,
UK
UK
UK
UK
UK
UK
UK
UK
OM'' '
-12V
Order Number MM4231 RP-2/J or MM5231 RP-2/J
See Package 11
8-54
Order Number MM5231 RP-2/N
See Package 18
3:
.,.3:
code conversion tables
N
W
....
::D
""CI
.......
FUNCTION
INPUT
ROM
EBCDIC
ASCII
SYMBOL
SYMBOL
MSB
0
NULL
NUL
0
0
0
0
0
1
SDH
SDH
0
0
0
0
2
STX
STX
0
0
0
0
•
ETX
ETX
PF
5
HT
6
7
DEL
HT
0
0
0
0
0
0
0
0
•
DEL
I
I
I
SMM
VT
VT
FF
FF
CR
CR
"
15
SO
so
Sl
Sl
16
OLE
OLE
17
DCl
DCl
18
DC2
DC2
DC3
DC3
I.
20
21
RES
NL
8S
23
IDL
2'
25
CAN
CAN
EM
EM
26
CC
BS
27
CUI
28
FLS
FS
2.
30
GS
RDS
GS
RS
31
US
US
32
OS
33
SDS
3.
36
BVP
37
38
LF
EDB
ET8
3.
PRE
ESC
.,
SM
CU2
44
45
END
END
46
ACK
47
BEL
ACK
BEL
SVN
SVN
48
4.
50
51
52
PN
53
RS
54
UC
55
EDT
DC4
EDT
56
57
58
59
CU3
60
DCA
61
NAK
NAK
.2
•3
SUB
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
1
0
1
1
1
1
1
1
1
0
0
0
0
1
0
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
I
CI'I
N
LSB
0
1
0
1
I
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
0
0
I
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
1
1
1
1
0
0
0
0
1
0
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
1
0
0
0
1
1
1
0
0
0
0
1
0
1
0
1
1
1
1
0
0
0
1
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
1
0
1
1
1
0
....
0
1
1
I
I
I
I
I
I
I
I
I
I
.......
LF
.0
43
0
W
::D
""CI
1
CONTINUING BINARY
SEOUENCE
FS
35
42
MSB
0
I
I
I
I
I
\
22
CC/G
0
0
.......
\
8
11
12
13
LSB
0
0
0
LC
10
OUTPUT
INPUT
OUTPUT
ADDRESS
3
3:
3:
CODE
SUB
,
As
A7
As
As
I A4
,
A3
A2
A,
1
0
0
a
a
a
a
a
a
a
1
a
a
a
a
a
1
a
a
1
1
a
1
1
1
a
a
a
1
a
1
1
a
a
a
a
1
a
1
a
a
a
a
a
a
a
1
a
a
a
a
a
1
a
1
a
1
a
a
a
1
1
a
1
a
B7
B6
So
B3
B2
B,
sa
as
8-55
L
!E
cwt
code conversion tables(con't)
N
ID
I
Ii::
FUNCTION
~
N
.
~
~
OUTPUT
ROM
ADDRESS
EBCDIC
SYMBOL
ASCII
SYMBOL
64
65
66
67
68
89
70
71
72
73
74
75
76
SP
SP
MSB
\
...,.
OUTPUT
LS8
CC/G
MSB
I
1
0
1
0
0
0
0
LSB
0
1
1
1
1
1
1
1
1
0
0
0
0
1
0
1
1
1
1
1
1
1
1
0
1
0
0
1
0
1
1
1
1
1
1
0
1
1
1
0
0
1
1
1
1
0
0
1
0
1
0
0
0
0
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
0
0
1
1
1
1
1
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
1
1
1
1
0
1
0
0
0
1
1
1
0
0
1
0
1
1
0
1
1
0
0
1
1
0
1
1
1
1
1
1
1
0
0
1
0
0
1
1
0
1
1
0
0
1
1
1
1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
0
1
1
0
1
1
1
1
1
1
1
0
0
1
0
0
0
1
1
0
1
1
1
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
1
1
0
1
1
0
1
0
1
0
1
0
1
1
0
Sa
87
86
85
84
B3
82
8,
I
•
-
<
<
(
(
78
79
80
81
82
83
84
85
8G
87
88
89
90
91
92
93
+
+
&
&
9G
97
9B
99
100
101
102
103
104
105
105
107
100
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
INPUT
I
77
94
95
8-56
COOE
INPUT
,,
,
I
I
I
I
I
I
I
I
$
$
I
I
;
;
--,
1\
I
I
I
I
CONTINUING BINARY
SEQUENCE
I
I
I
%
-
%
-
>
>
?
7
I
I
I
I
I
,
,
..
..
..
..
#
#
I
I
I
-.
~ I A7 I A6 I As I A4 I A3 I A2 I A~
code conversion tables(con't)
FUNCTION
ROM
ADDRESS
128
129
130
131
132
133
134
135
136
137
CODE
INPUT
OUTPUT
EBCDIC
SYMBOL
ASCII
SYMBOL
.
b
,
.
d
e
f
f
9
9
h
h
I
I
;
I
I
,
143
144
145
146
J
k
k
147
148
I
I
m
m
J
149
150
n
0
0
151
152
153
p
p
q
q
,
154
155
n
J
172
173
174
175
176
177
,
,
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
1
0
1
0
0
1
1
0
0
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
u
,
u
,
w
x
w
x
,
Y
,
[
[
,
,
I
I
Y
1
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
0
1
0
1
0
1
1
1
1
0
1
1
0
0
0
1
0
0
0
1
1
0
0
1
1
1
1
,0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
1
1
0
1
1
1
1
0
1
1
1
0
1
lis
B7
BS
B5
B.
B3
B2
B,
0
0
1
0
0
0
1
0
1
0
0
1
0
1
0
,
I
I
I
I
181
182
183
18'
185
I
186
187
191
LSB
CONTINUING BINARY
SEQUENCE
178
179
180
188
189
190
MSB
1
1
I
I
,
,
156
157
158
159
160
165
166
167
168
169
170
171
'"
CC/G
I
I
138
139
140
141
142
161
162
163
164
LSB
I
b
d
,
MSB
\
,
e
OUTPUT
INPUT
[
I
J
I
As
-"-
\
I A7 I AS I A5 I A.4 I A3 I A2 I Al
8-57
0..
ex:
~
code conversion tables(con't)
M
N
It)
::E
::E
......
CODE
FUNCTION
0..
ex:
~
ROM
ADDRESS
Old'
192
193
194
195
196
197
198
199
200
201
202
N
::E
::E
INPUT
OUTPUT
EBCDIC
ASCII
SYMBOL
SYMBOL
INPUT
MSB
LSB
l
+ ZERO
A
A
B
B
e
e
D
D
E
F
E
G
G
H
H
I
208
209
ZERO
210
211
K
J
K
L
L
212
213
214
215
216
M
M
N
N
0
P
0
P
Q
Q
217
218
219
R
R
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
LSB
MSB
1
1
I
I
1
1
1
I
1
1
1
1
I
I
I
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
0
0
1
1
0
0
0
1
0
1
0
1
0
0
1
1
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
1
1
0
0
1
1
0
1
0
0
0
0
1
0
1
0
0
0
0
0
0
1
1
1
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0
0
1
0
0
1
1
1
0
1
0
1
0
0
0
1
B5
B.
B3
B2
B,
CONTINUING BINARY
SEQUENCE
S
T
U
V
W
S
T
U
V
X
X
I
I
W
Y
Y
Z
Z
238
239
240
241
242
243
244
245
0
1
2
3
4
5
246
247
6
7
5
6
7
248
249
8
9
8
9
250
251
252
253
254
255
8-58
J
1
1
1
1
1
1
1
I
I
I
I
203
204
205
206
207
CC/G
I
"
F
I
OUlPUT
I
I
I
I
I
I
0
1
2
3
4
I
,
.A.
I
1
1
1
1
1
1
1
1
1
1
1
1
1
1
As
A7
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
AS
A5
A.
A3
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
B7
B6
1
0
1
0
1
1
A2
AI
Sa
ROM Code Converters
s:
s:
~
II-)
Co)
II-)
.......
s:
s:U1
MM4232/MM5232 AEI, AEJ, AEK sine look up table
general description
II-)
Co)
II-)
The MM4232/MM5232 AEI, AEJ and AEK are all
P-channel enhancement mode MaS read-only memories, each storing 4096 bits. They are programmed
to generate the sine function of any angle expressed as a binary fraction of a right-angle. They
may be combined and arranged to provide a lookup table of varying resolution and accuracy, to
meet almost any system requ irement for generation of the sine function.
»
m
application information
»m
Figures 1 through 4 show the four ways that these
parts may be combined. The table shows the performance of all combinations.
(..
»
m
"
perfo rmance specifications
FIGURE
ROM NO. USED
RESOLUTION
1= INPUT
WORD
LENGTH I
OUTPUT WORD
LENGTH
ACCURACY
ADDER PACKAGES
REQUIRED
+0
1
AEI
9 bits
8 bits
2
AEI + AEJ
9 bits
16 bits
i. 1/2 bit in
16
0
3
AEI + AEJ +
AEK
12 bits
16 bits
± 3/4 bit in 14
4
4
AEI+AEJ+
2 AEK's
15 bits
16 bits
±1 bit in 14
6
e
SINE LOOK-UP TABLE WITH HIGH
RESOLUTION AND ACCURACY
sine of an angle
resolved into 2'5 increments
in the range 0 <;: e < 71/2.
Theoretical Background
The table is based upon the equation:
sin (M + L) = sin M cos L + cos M sin L
0
-1 bit in 8
(1)
By splitting M and L each into two parts MM,
M L, and LM, LL, and (assuming M
L) the following equation is obtained.
»
sin (M + L) "" sin (MM + ML)
(2)
+ cos (MM + 1/2 LSB of MM) sin LM
+ cos (MM + 1/2 LSB of MM) sin LL
"" sin (MM +M LI
+ cos (MM + 1/2 LSB of MM) (sin LM + sin LL)
This error, due to the mathematical approximation,
is ±3.2x 10-5 maximum, corresponding to ±1 bit in
15 bits. I n addition to the mathematical error, an
inevitable round-off error in the 16th bit is introduced. As there are 3 LSB outputs to be added
(Figure 4), the maximum round-off error will be
±1-112 bit in 16 bits or ±2.3 x 10-5 . The theoretical
maximum total error will then be ± (3.2 + 2.31
.x 10-5 = ±5.5 x 10-5 , which is slightly less than ±1
bit in 14 bits.
A computer analysis shows that the actual errors
in the table as implemented are as follows:
+4.4 x 10-. 5 (at 61.872°1
The following approximations have been used:
cos(LM+LLI""1
sin (LM + LL) ~ sin (LM) + sin (LL)
cos (MM + ML) "" cos (MM + 1/2 LSB of MM)
By taking MM = 6 bits, ML = 3 bits, LM = 3 bits,
and LL = 3 bits, 15 bits resolution is obtained. The
accuracy has been computed by comparing the
values of Equation 2 with the ideal value of the
Order Number MM4232J or MM5232J
See Package 11
-4.7 x 10.- 5 (at 83.142°)
As the sine function is very linear in the LM-LL
range, the third term of Equation 2 can be considered as being 11(21 3 of the second term without
significant error. Therefore, the same pattern can
be used for the two lower ROMs in Figure 4, and a
total of three different masks are needed. In addition, six 4-bit adders are used.
Order Number MM5232N
See Package 18
8-59
~
w
«
(0 = rr/2 RADIANS)
SINe
~
«
A,
(8" n/2 RADIANS)
r'-
2-2 _
W
«
N
M
N
It)
:l!
:l!
.......
A,
SINO
ANGLE
8a
87
A,
A,
Bs
A,
,~-
A,
,~-
II,;
,~-
A,
,-,-
,~-
A,
,~-
A,
2"_
A,
t-- 2"
A,
B7 1--Z2
MM42321
MM5232
AEI
&El=O
CE2=0
A,
.--
80 1--2.3
B5
t- Z
84
1-- 2-5
83
1-- z./l
B2
B,
MM42J2/
MM5232
A,
AEI
CE1=O
CE2=0
A,
r - - A,
-'l
r--
,-,
FIGURE 1
N
M
N
'It
:l!
:l!
A,
,~
A,
88t-- 2-9
Blt-- 2,\0
MM4232/
MM52J2
,~
II,;
"
,-,"
A,
AEJ
C£I=O
A,
eE2=1
,..
A,
A,
CE1CE2
ALL
OM54831
DM1483
B,
B,
B,
B,
A,
B,
A,
B,
A,
A,
B,
A,
B,
A,
MM4232/
MMS232
1:2
co
t-z-3
2:,1- 2-4
-[
A,
AEI
.--..--
A,
&£1"0
CE2=0
B,
B,
A,
B,
'"
,--
A,
B,
A,
SINo
" "
2:Jj-2z
'"
A,
B,
A,
B,
A,
B,
A,
B,
CE1CE2
c,
:::4
t- 2-5
:::3~2-6
:::2
r- 27
~,
t- Z
-8
CO
I
ANGLE
B,
A,
B,
B,
A,
B,
,~
A,
,~
A,
B,
A,
r---
MM423Z/
MM5Z32
A,
"
A,
B,
A,
B,
,~
-9
CE2=1
B,
. - - - A,
B,
. . - - A,
B,
B,
:::Zt-2'1
co
c,
B,
A,
B,
eEl eEl
:::4r Z'3
1;3
1:,
CO
-#
B,
A,
B,
A,
B,f--
A,
t--
A,
L - A,
°' _______
2-1
2-1 '
I---
A,
B,~
MM42321
MM5232
AEK
eEl=1
tE2=1
A,
B,I--B,
_ _ _ _ _ __
A,
2-12' _ _ _ _ _ __
B,
A,
B,
CEttE2
FIGURE 3.
Note: Angles are expressed as binary fractions of a right-angle.
8-60
J-- 2"12
t--
2"'4
:::21- 2,'5
~A,
A,
l:,
-[
AEJ
&El=O
,~
,.
B,
A,
B,
A,
:::4r- Z
:::31-- 2·'0
A,
B,
A,
C,
1-- 2"'2
B4t-- 2",3
83
1-- 2"'4
8,1--
A,
(e=rri2RADfANS)
~1--2·11
85
821--2"'5
Z-,6
FIGURE 2
,.
i--.t5
1-- 26
B,t-Zoll
II,;
,~
,~
,~
83
ANGLE
CElt;f2
,-,
"I->'
B4
CE1CE2
t-- 2"7
.--
1-- Z-2
1-- 2-3
Bzl--F
A,
A,
t-- 241
86
l-- 2-'
t-
2,11;
w= - pI RADIANS)
ANG LE
,~
,~
''-
'
,-
,~
MM
,~
-
f-~
,
B,
-
A,
B,
A,
B,
-
A,
-
A,
B,
r
"_
-
I-
A,
1-
A,
MM5232
B,
II,
B,
A,
B,
A,
B,
A,
DM748J
B,
C,
B,
B,
-
A,
B,
A,
B,
A,
B,
CE1CE2
B,
A,
B,
1_
A,
B,
-
A,
B,
1_
A,
_
A,
r----
r'
-
B,
A,
B,
A,
B,
A,
B,
A,
C,
ML
'-)
2--8 - f -
: -
A,
1-
A,
A,
_
A,
B,
. - - - - - II,
B,
B,
B,
~A,
B,
_A,
B,
A,
B,
B,
CE1CE2
B,
A,
B,
A,
B,
A,
B,
A,
B,
B,
-
~
A,
B,
-
A,
11_
A,
-
U1
N
W
N
"
'"
»
m
"-"
" ,.... "
»
m
c..
" f- "
L3
f-
»
OM1483
m
" fCO
" f-
;Ii;
2- 12
C,
::::4
t-
" f- 22:2 f- 2-15
L, f14
OM1483
CO
*
"
::::3 i--
DM7483
::::2~
CO
',-
MM5232
AEK
~
A,
B,
A,
B,
A,
B,
A,
B,
CE1CE2
11-
s:
s:
I
B,
-
.......
I
MM5232
A,
" "
" ,.
"
C, ' DM7483
"
AEJ
,~
N
W
N
l'
" f-
CO
~
_
CO
"B,
B,
A
A2
'
"
I
~
AEI
Ii -
s:
s:.J:Io
SIN X
B,
. - - - - - A,
B,
_A,
B,
-A,
B,
A,
C,
2: 4
DM7483
CO
-
"
"
"
s,
A,
B,A,
B,-
l-
A,
-1-
A,
1-
A,
1-
A,
B,MM5232
AEK
B,-
A,
B,
A,
B,
B,
A,
CE1CE2
FIGURE 4
Note: Angles are expressed as binary fractions of a right angle.
8-61
(")
r:::
...
o
III
Custom M OS/LS I
3
:!:
o
en
........
r-
en
Custom MOS/LSI Product Flow
I nterface between
Product Definition
Customer and
Design/Production
Engineers
Time Sharing Computer
Simulates
Static and Dynamic
Partitioning
Simulation
Performance and
Worst Case Parameters
Calma Digitizing System
Drafting
Digitizing
David Mann
lOX Reticle Generation
Reticle Generator
David Mann
6-Barrel Step & Repeat
Mask Making
Camera
Wafer Fabrication
Volume Wafer Production
Santa Clara Facility
Teradyne JV7. J283
Macrodata MD200
100% Waver Probe Test
Fairchild Sentry 600
Assembly
Volume Assembly.
Worldwide
Teradyne J277. J283
Macrodata MD200
100% Finished Product
Test
Fairchild Sentry 600
Qual ity Assu ranee
Internal Spec to MIL-STD 883
Reliability
High Rei Processing
Available on all Products
Shipping
9-1
U)
....
o
INTRODUCTION
"U)
While custom and standard MOS have advantages
over each other for specific applications, there is a
high demand for both in today's electronics industry. In most cases, the true test of whether a sys·
tem can most economically be implemented with
standard, custom, or both, can only be determined
after partitioning. If the quantities in question do
not exceed a few hundred units per year, the stan·
dard product approach is probably the best solu·
tion. However, if the total number of units is
many thousand per year, then customizing is
usually the best approach.
::E
..=
E
o
en
(,)
Custom MOS circuits are designed to do a specific
job. You are not buying capability that is not
needed. The entire chip is devoted to performing
your specific function. Advantages are:
1)
2)
3)
4)
F ewer Packages
Lower Power Dissipation
Smaller P.C. Boards
Proprietary Design
These advantages result in lower system costs and
protection of your system design.
RESOURCES
National has brought together a group of experi·
enced circuit and system designers, separate from
the standard product group, to offer a custom
MOS/LSI design service to the industry. This group
is prepared to aid in the logic design of a system,
partition the system into feasible LSI circuits if
the design requires more than one chip, develop
the chips, assist the customer in prototype system
checkout, and put the design into production.
National has one of the most advanced IC manu·
facturing facilities in the industry. Your custom
design will go through the same production facili·
ties where National's standard MOS products are
manufactured, and thus benefit from our long
experience in MOS processing.
As with its bipolar circuits, the key to National's
MOS program is volume production. We are a
leading producer of shift registers, read·only memo
ories, and random access memories. I n the latter
category, National is supplying many second source
and proprietary static and dynamic RAMs as well
as several advanced large-capacity RAMs.
National was the first company to offer MOS cir·
cuits that operate at voltage levels directly com·
patible with TTL. (Previously, level-shifters were
needed if high·voltage MOS and low·voltage TTL
were to work together). To achieve this so·called
low· level MOS operation, National pioneered in
the fabrication of circuits made from silicon cut
along the (1-0·0) axis of the crystal. Subsequently,
other companies developed bipolar compatible
MOS circuits also.
1·0-0 P-channel metal gate and 1-1-1 silicon gate
technologies are presently utilized by National
in our standard MOS products. These processes
9·2
have become industry standards. All of the
P-channel MaS process devices offer bipolar
compatibility.
Metal gate devices operate to 1.5 MHz. This technology is well·suited to random logic and ROM
applications. Higher logic densities and operating
frequencies approaching 5 MHz can be achieved
by using silicon gate technology. This process
lends itself to RAMs, registers, and random logic
appl ications.
Static and dynamic logic is available in both metal
and silicon gate devices. In general, less power is
dissipated if dynamic logic is employed, wh ich
also offers the advantage of synchronous opera·
tion and eliminates hazards due to race conditions.
In any event, power dissipation of typical LSI
functions (up to 1000 gate functions) approach
500 mW in devices fabricated with either metal
gate or silicon gate technology.
Complementary MaS (CMOS) technology is pre·
sently being used on many custom products.
Structured logic, ROMs, RAMs, and registers,
designed with CMOS cannot achieve the density
of P·channel MOS. However, quiescent power and
dissipations are less than one microwatt per gate.
Operation to 10 MHz can be achieved. One of the
advantages of CMOS is that power dissipation is
a function of frequency, with the DC (quiescent)
state consuming the least power.
The N·channel process is also undergoing develop·
ment at National. This process allows higher den·
sity and high frequency operation than P·channel.
Ion implantation is a technique that can be applied
to any of the previously mentioned processes. It
allows threshold voltages to be adjusted to a desired
level by implanting ions in the gate region. Deple·
tion load devices and large value ohmic resistors are
also being made with ion implantation, which
greatly improves packing density on LSI chips.
DESIGN
Your custom design will benefit from National's
longtime experience in the MaS business. Exten·
sive use of computer·aided design (CAD) and
computer simulation programs assure proper opera·
tion of your circu it before it goes into production.
All designs are verified with a circuit analysis pro·
gram to assure proper operation. Worst case signal
paths are checked to see that no signal race condi·
tions ex ist.
Circuit layouts are performed using advanced
CAD techniques. CAD system bypasses manual
artwork generation entirely and goes directly from
a digitized layout to lOX reciticles eliminating
the need for rubylith and intermediate reduction
steps. National's photomask generation laboratory
is one of the best equipped in the industry including
the Calma Digitizing System, the David Mann
Pattern Generator, and 6·barrel Step and Repeat
camera.
(")
C
TESTING
National has a nu mber of LS I testers that allow
complete checkout of structured logic (ROMs,
RAMs, shift registers, etc.) and random combina·
tional logic. The random logic testers are computer
programmed to test to the customer's input/output
logic specifications. On·line testers include Tera·
dyne J283, J277, Macrodata 230·2 LSI tester
and Fairchild Sentry 600.
After fabrication, each wafer is checked for thres·
hold voltage, breakdown voltage, oxide rupture
and sheet resistivity. The wafer then goes into
functional test. The logic on each die is thoroughly
exercised. This 100% test of each wafer eliminates
any fu nctional defective die from being packaged.
After packaging, all devices are stressed to environ·
mental extremes. The packaged devices are then
returned for another functional test. Depending
on the customer's requirement, packages can be
tested under a variety of environmental conditions
and can be subjected to a burn·in cycle. Full MIL·
STD 883 processing is offered on all National
custom and standard MaS devices.
QUALITY ASSURANCE
National's quality assurance department has a com·
plete and comprehensive qual ity control program
which effectively controls component parts and
vendors at a qual ity level of fu nctional, workman·
ship and dimensional criteria. The QA program also
covers in·process controls of assembled devices,
final electrical test, marking and final shipment of
approved product. All procedures are documented
at specification control and at respective quality
inspection stations. Weekly and monthly reports
are generated for quick feedback of information
for corrective action pu rposes.
All inspections are performed to specified internal
AQL inspection levels which meet or exceed MI L·
STD 883.
RELIABI LlTY
The reliability evaluation program in effect at
National is a continuous monitor on the process
...
(II
stability of assembled devices on extended life
test. Tests which are performed on a continuous
basis on each process are:
o
3
3:
(a) High Temperature Operating Life Test (ex·
tended life)
(b) High Temperature Storage Test (extended
life)
orJ)
"rrJ)
MIL·STD 883, which specifies testing procedures
for integrated circuits, was innovatively handled by
National. The company adopted 883 specs as its
own, rather than to set up one procedure for
military orders and another for industrial cus·
tomers. Therefore, there are no dual standards at
National. All devices are given the same quality
control treatment and the company inventories
devices with guaranteed 883 specs.
All standard devices undergo MI L·STD 883 testing.
They are 100% subjected to a temperature cycle
per Method 1003 Condition D, fine leak test per
Method 1014 Condition A, Helium 5 x 10.7 , and
gross leak test per Method 1014 Condftion C.
The company has been informed by the National
Aeronautics and Space Administration that it has
received line certification under MIL·M·38510, the
new military standard defining acceptable pro·
cedures for producing devices.
A customer may request any special rei processing
per Document NSC/0002. The intent of th is docu·
ment is to provide the user with the ability to
procure any integrated circuit manufactured by
National to any class of M I L·STD 883 processing.
PACKAGES
National offers a variety of dual·in·line packages
(DIPs). metal cans, flat packs, and specialized
packages. Both ceramic and molded packages are
available.
All packages meet the standard JEDEC registered
outlines. Lead finishes are available in either gold
or tin. The ceramic packages meet a leakage of
5 x 10-7 std cc He/sec leak rate. National's molded
packages are the most advanced in the industry
and afford reliability which rivals the ceramic
packages.
9-3
3:
3:
c.n
w
o
.....
Complex Standards
MM5307 baud rate generator/programmable divider
general description
features
The National Semiconductor MM5307 baud rate
generator/programmable divider is an MaS/LSI
P-channel enhancement mode device. A master
clock for the device is generated externally. An
internal ROM controls a divider ci rcuit which
produces the output frequency. Logic levels on the
four control pins select between sixteen output
frequencies. The frequencies are chosen from the
following possible divisors: 2N, for 3 ~ N ~ 2048;
2N + 1 and 2N + 0.5 for 4 ~ N ~ 2048. Also one
of the sixteen frequencies may be gated from the
external frequency input. The MM5307 AA is
supplied with the divisors shown in Table I.
•
•
•
Choice of 16 output frequencies from 1 crystal
External frequency input pin
Internal ROM allows generation of other
frequencies on order
•
Bipolar compatibility
•
1.0 MHz master clock frequency
applications
• DAR/T clocks
• System clocks
• Electrically programmable counters
schematic and connection diagrams
Dual-In-Line Package
14 "OUT
EXTERNAL FRED.
13 RESET
NC
12 VGG
OUTPUT
RESET ) - - - . . . . . . ,
OUTPUT
v~
EXTERNAL
11 A
,
10
ClOCK
EXT
FAEO
,
NC
v~
TOP VIEW
CLOCK
EXT~~~~~ :>----+1 GENERATOR
'--------'
Order Number MM5307 AA/D
See Package 2
Order Number MM5307AA/N
See Package 14
10-1
absolute maximum ratings
Voltage at Any Pin With Respect to Vss
Power Dissipation
Storage Temperature Range
Operating Temperature
Lead Temperature (Soldering, 10 seconds)
+0.3V to Vss - 20V
700mW
-65°C to +150°C
O°C to +70°C
300°C
dc electrical characteristics
TA within operating range, Vss
=
+5.0V ±5%, VGG
PARAMETER
=
-12V ±5%, unless otherwise specified.
CONDITIONS
TYP
(NOTE 3)
MIN
All Inputs
Logical High Level (V'H)
Logical Low Level (V1d
Vss
Vss
~
~
1.5
18
MAX
Vss
Vss
+ 0.3
~4.2
UNITS
V
V
Leakage
V'N "~10V, TA " 25"C
All Other Pins GND
0.01
0.5
/-iA
Capacitance
V'N" OV, I" 1.0 MHz
All Other Pins GND (Note 1)
3.5
7.0
pF
Output Levels
Logical High Level (V aH )
Logical Low Level (VOL)
ISINK
Power Supply Current (IGG)
I" 1.0 MHz
= -0.5 mA
1.6 mA
Vss
ISOURCE
=
~
2.6
Vss
Vss -- 4.6
25
35
V
V
mA
ac electrical characteristics
TA within operating range, Vss = +5.0V ±5%, V GG = -12V ±5%, unless otherwise specified.
PARAMETER
CONDITIONS
Master Frequency
MIN
TYP
(NOTE 5)
MAX
UNITS
0.01
1.5
1.0
MHz
Access Ti me (T A)
CL
50 pF (Note 2)
16
Reset Delay Time (t R D)
f = Master Clock Frequency
500 + 4/1
"
500 + 4/1
Reset Pulse Width (R pw )
500 + 4/1
T
= Output Period
ns
ns
Output Delay From Reset (too)
Output Duty Cycle
/-is
ns
0.5T ±1/1
f = Master Frequency
Note 1: Capacitance is guaranteed by periodic measurement.
Note 2: Access time is defined as the time from a change in control inputs (A, B, C, OJ to a stable output frequency_
Access time is a function of frequency. The following formula may be used to calculate maximum access time for any
master frequency: T A"'" 2.8}.ts + 1/f x 13, f is in MHz.
Note 3: Typical values lor TA
10·2
= 25°C,
VSS
= 5.0V
and VGG
= -12V.
truth table
TABLE I. MM5307AA Output Ootails (921.6 kHz Master Clock Frequency)
CONTROL
PINS
AB C D
OUTPUT
FREO
kHz
DIVISOR
a a a 1
a a 1 a
a a 1 1
a 1 a a
a 1 a 1
a 1 1 a
a 1 1 1
1 a a a
1 a a 1
1 a 1 a
1 a 1 1
1 1 a a
1152
0.800
1.200
1.760
768
524
64
48
110
134.5
150
300
600
900
1200
19.200
32
28.800
24
38.400
16
12
8
57.600
1800
2400
3600
4800
76.800
115.200
6
-
a a a a
50
75
2.152
2.400
4.800
9.600
14.400
428.5
384
192
96
1 1 0 1
1 1 1 a
1 1 1 1
COMMON BAUD RATES
(OUTPUT FREO/16)
7200
9600
-
153.600
EXT
timing diagram
EXT.
elK, 1>ouT
A, B, Cor 0
OUTPUT
==x
+90%
+10%
r--x
Jt +90%
+10%
J
X
X
1ST PULSE
OF CORRECT
T,
'eo
LENGTH
:~~~ J::
O~~~~l:l~~l~IE~~
DURING THIS TIME
1O%ft90%
RESET
"\
10%
I----Rm---l
'00-
10·3
Complex Standards
MM5309, MM5315 digital clocks
general description
These digital clocks are monolithic MOS integrated
circuits utilizing P-channel low-threshold, enhancement mode and ion implanted depletion mode
devices_ The devices provide all the logic required
to build several types of clocks. Two display modes
(four or six digits) facilitate end-product designs of
varied sophistication. The circuits interface to LED
and gas discharge displays with minimal additional
components, and require only a single power
supply. The timekeeping function operates from
either a 50 or 60 Hz input, and the display format
may be either 12 hours (with leading-zero blanking)
or 24 hours. Outputs consist of multiplexed display drives (BCD and 7-segment) and digit enables.
The devices operate over a power supply range of
11V to 19V and do not require a regulated
supply. The MM5309 and MM5315 clocks are
packaged in a 28 lead dual·in-line package.
•
4 to 6 digit display mode
•
12 or 24 hour display format
•
Leadi ng·zero blanking (12-hour format)
•
BCD and 7-segment outputs
•
Single power supply
•
Fast and slow set controls
•
Output enable control
•
Internal multiplex oscillator
•
Hold count control
applications
•
Desk clocks
•
Automobile clocks
features
•
Industrial clocks
•
Reset
•
Military clocks
•
50 or 60 Hz operation
•
Interval timers
connection diagrams
Dual-I n-line Package
Veo
MULTIPLEXED
BCD OUTPUTS
(NEGATIVE
TRUE)
[-~
imf4
~MUXTlM1NG
-1
BCD2~
~Ml
iClJ1~
t-!i
b....!
10-4
MM5309
(NEGATIVE
TRUE)
t!!- HI
rE- lo
H
e..!!
~50/60Hz1NPUT
,...!!
,J!.
50/60 Hz SELECT
..!!
~4/6DJGITSELECT
-.!
~ ~I~~NG
r~
tll- M,
Benl...J
~MIO
BCD'....!
fiHl
DIGIT
ENABLE
OUTPUTS
~Sl
.!.!
MULTIPLEXED
BCD QUTPUTS
Ml0
,....!
,....!
12/24 HOUR SELECT
Voo
OUTPUT ENABLE
p!.. 4/6 DIGIT SELECT
• ...!
MULTIPLEXED
1SEGMENT
OUTPUTS
Dual-In-Line Package
~
.....2
8C04...1
• ....!
f,!.Hl0
h....!
pts,
MM531S
j'.
,....!
,....!
f2.
~...!.!!
!!.. FAST SET
~FASTSET
f...!.!
.!!.. SLOW SET
~SlDWSET
g~
~StO
~
RESET
t1!-Vss
MULTIPLEXED
7SEGMENT
OUTPUTS
~S,0
50/&0 Hz INPUT
.!.!..HDLD
.!!. RESET
12f24HRSElECT..12
50/60 Hz SELECT
ENABLE
OUTPUTS
.!.!..Vss
.!.2
TOP VIEW
TDPVIEW
Order Number 5309N
Se. Package 19
Order Number MM5315N
Sea Package 19
s:
s:
absolute maximum ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
(J1
w
o
Vss + 0.3 to Vss - 20V
-25°C to +70°C
-65°C to +150°C
300°C
CD
s:
s:
(J1
w
....
(J1
electrical characteristics
TA within operating range, Vss = +14V, V DD = OV, unless otherwise specified.
PARAMETER
CONDITIONS
Power Supply Voltage
Vss (V DD "OV)
Power Supply Current
Vss
0
MIN
TYP
MAX
11
14
19
v
2.0
10
mA
50 or 60
60k
Hz
V ss -1.0
0
Vss
4.0
v
1.0
60
+14V (No Output Loads)
50/60 Hz Input Frequency
de
UNITS
50/60 Hz Input Voltage
Logical High Level
Vss - 2.0
-2.0
Logical Low Level
Multiplex Frequency
Determined by External R & C
de
V
kHz
All Logic Inputs
Logical High Level
Logical Low Level
Internal 20
kn
ReSistor to V ss
Vss
--2.0
V
V
o
4.0
5.0
20
0.01
rnA source
rnA source
0.3
rnA source
25
mAsink
BCD and 7-Segment Outputs
Logical High Level
Loaded 2.0 k!.1 to V DD
2.0
Loaded 10m! to Vss
5.0
Logical Low Level
Digital Enable Outputs
Logical High Level
Logical Low Level
10
functional description
A blDck diagram Df the MM5309 and MM5315
digital clDcks is shown in Figure 1. CDnnection
diagrams fDr these devices are shown on the
front page. The fDllowing discussiDns are based
on Figure 1.
50 or 60 Hz Input: This input is applied to a
Schmitt trigger shaping circuit which provides
approximately five volts of hysteresis and allows
using a filtered sinewave input. A simple RC
filter such as shown in Figure 10 should be used
to remove possible line voltage transients that
could either cause the clock to gain time or
damage the device. The input should swing between
Vss and V DD . The shaper output drives a counter
chain which performs the time keeping function.
50 or 60 Hz Select Input: This input programs the
prescale counter to divide by either 50 or 60 to
obtain a 1-pps timebase. The counter is programmed
for 60 Hz operation by connecting this input to
V DD . An internal 20 kn pull-up resistor is common
to this pin; simply leavif'g this input unconnected
programs the clock for 50 Hz operation. As shown
in Figure 1, the prescale counter provides both
1-pps and 10-pps signals, which can be brought
out as bonding options.
Time Setting Inputs: Both fast and slow setting
inputs, as well as a hold input, are provided.
Internal 20 kn pull-up resistors provide the normal
timekeeping function. Switching any of these
inputs (one at a time) to V DD results in the
desired time setting function.
The three gates in the counter chain (Figure 1) are
used for setting time. During normal operation,
gate A connects the shaper output to a prescale
counter (750 or 7 60); gates Band C cascade the
remaining counters. Gate A is used to inhibit the
input to the counters for the duration of slow,
fast or hold time-setting input activity. Gate B is
used to connect the shaper output directly to a
seconds counter (7 60), the condition for slow
advance. Likewise, gate C connects the shaper
output directly to a minutes counter (7 60) for
fast advance.
Fast set then, advances hours information at one
hour per second and slow set advances minutes
information at one minute per second.
12 or 24 Hour Select Input: This input is used to
program the hours counter to divide by either 12
or 24, thereby providing the desired display format.
10-5
functional description (con't)
The 12-hour display format is selected by connecting this input to V DO; leaving the input unconnected (internal 20 kQ pull-up) selects the 24-hour
format_
Output Multiplexer Operation: The seconds, minutes, and hours counters continuously reflect the
time of day_ Outputs from each counter (indicative
of both units and tens of seconds, minutes, and
hours) are time-division multiplexed to provide
digit-sequential access to the time data_ Thus,
instead of requiring 42 leads to interconnect a
six-digit clock and its display (7 segments per
digit), only 13 output leads are required. The
multiplexer is addressed by a multiplex divider
decoder, which is driven by a multiplex oscillator.
The oscillator and external timing components
set the frequency of the multiplexing function
and, as controlled by the 4 or 6 digit select
input, the divider determines whether data will
be output for 4 or 6 digits. A zero-blanking
circuit suppresses the zero that would otherwise
sometimes appear in the tens-of-hours display;
blanking is effective only in the 12-hour format.
The multiplexer addresses also become the display
digit-enable outputs. The mUltiplexer outputs are
applied to a decoder which is used to address a
programmable (code converting) ROM. This ROM
generates the final output codes, i.e., BCD and
7-segment. The sequential output order is from
digit·6 (unit seconds) thru digit-1 (tens of hours).
Multiplex Timing Input; The multiplex oscillator
is shown in Figure 2. Adding an external resistor
and capacitor to this circuit via the multiplex
timing input (as shown in Figure 10) produces a
relaxation oscillator. The waveform at this input
is a quasi-sawtooth that is squared by the shaping
action of the Schmitt trigger in Figure 2. Figure 3
provides guidelines for selecting the external components relative to desired multiplex frequency.
Figure 4 illustrates two methods of synchronizing
the multiplex oscillator to an external timebase.
The external RC timing components may be
omitted and this input may be driven by an
external timebase; the required logic levels are the
same as the 50 or 60 Hz input.
Reset: Applying V DO to this input resets the
counters to 0:00:00_00 in 12 hour format and
00: 00: 00_00 in 24 hour formats leaving the input
unconnected (internal 20 kQ pull-up) selects
normal operation.
4 or 6 Digit Select Input: li ke the other control
inputs, this input is provided with an internal
20 kQ pull-up resistor. With no input connection
the clock outputs data for a 4 digit display. Applying Voo to this input provides a 6 digit display.
Output Enable Input: With this pin unconnected
the BCD and 7-segment outputs are enabled (via an
internal 20 kQ pull-up). Switching V DO to this
input inhibits these outputs. (Not applicable to
MM4315 clock.)
Output Circuits: Figure 5-A illustrates the circuit
used for the BCD and 7-segment outputs. Figure
5-B shows the digit enable output circuit. Figure 6
illustrates interfacing these outputs to standard
and low-power TTL. Figures 7 and 8 illustrate
methods of interfacing these outputs to commonanode and common-cathode LED displays, respectively. A method of interfacing these clocks to
gas-discharge display tubes is shown in Figure 9.
When driving gas-discharge displays which enclose
more than one digit in a common gas envelope, it
is necessary to inhibit the segment drive voltage(s)
during inter-digit transitions. Figure 9 also illustrates a method of generating a voltage for application to the output enable input to accomplish the
required inter-digit blanking.
50160H.
12124 HOUA
SHECT
INPUT
HOLlli~~~~~~~t~~~E~~~i~~~=~==~ b-------4:j
SLOW SET
FAST SET
RESET
v.<>-+)
'-{~--TI----;:=====~OOUTPUT
ASREQ'O
ENABLE
VooO--+-
MULTIPLEXED
RlIOUTJlU1S
MULTIPLEXED
f.SEGMENT
DUTflUTS
MULTIPLn
TIMING
INPUT
""===============--,===============::>OIGtTENABLE
t-
FIGURE 1. MM5309, MM5315 Digital Clock Block Diagram
10-6
OUTPUTS
functional description (con't)
5O!&DPI'S
OUTPUT DR
MULTIPLEX
OSCILLATOR
OUTPUT
SO/60Hz
INPUT OR
MULTIPLEX
TIMING
COMPONENTS
1.000.000
'" 100,000
E
I
I
~
I
I
I
I
I
L
-i,
I~
,~
___
-< ,. _____
~
ffi
ff:
10,000
~
;!
~
I
I
...JI
100
lOpF
.::'n'd "mp""u ,..,do.
r 11
Vss
100pf
10DOpF
O.Ot.uF O.lpF
CAPACITANCE C (WITH R' 100ki
shapingclr~ulttoform
multip'exoscillator
I
1000
:E
*Eftectively
FIGURE 2. 50/60 Hz Shaping Circuit/Multiplex Oscillator
FIGURE 3. Multiplex Timing Component.selection Guide
'
0--1 1-....==9
C2
EXTERNAL
TIME
BASE
EXTERNAL
CLOCK
SIGNAL
MULTIPLEX
TIMING INPUT
..
MM5309
(tN'UTOR OUTPUT)
R-
*R", IOOlen
'0'
Note: Free runmng frequencv should be set to lun sligtltly 'ower than
system frequency over temperature. External time base may be input or output.
'00
FIGURE 4. Synchronizing or Triggering Multiplex OScillator.
DIGIT ENABLE
OUTPUT
Q~~'
1-5EGMENT
OUTPUT
voo
iCii
OR 1m
(DPENORA'Nt
Voo
VOD
FIGURE 5. Output Circuits
10·7
functional description (con't)
MOS to TTL Interface
MOS to Low Power TTL Interface
Yss
~+5."V
ANYJ4lGATE
Vee ~ 5.0V
AHY1411tGATES
Yss=5.0V
iiCiii
FurVss =+5, Voo = 12. R= 10ku
For Vss" +10 to 17V, Veo = GND, R "3.0 kll
Note: DIgIt select WIll drIve TTL dIrectly when +5,
-12 supplies are used.
FIGURE 6. Interfacing TTL
Vss
--<1>---------.---
v~--~--------------~---
~~PICAt ~---------i
--rL
TYPICAL
SEGMENT
OUTPUT
EN~;~! "I..-r
vss -
OUTPUT
,
,-il
I
TYPICAL LED
SEGMENTS
(COMMON ANODE)
MM5J09
MM5J09
TYPICAL LED
SEGMENTS
(COMMON CATHODE)
SUCH AS NSN14A
OR EaUIV
SUCH AS
NSN71L,Ofl
EQUIY
TYPICAL
TYPICAL
2k
~~~;~~I-~---------I
SeGMENTI--~Wrl~.j
OUTPUT~
Voo
Voo
V __. . . ._ _ _ _ _ _ _ _ _. . . ._ _. . . ._ __
oo
AL = Vss
VD:(lF~F
Voo-......__-------------4~---
(V ss
n.sv
RL =
VF
1.5V
N(lF)
If = requited average LED current
WhereR L Ismk!!
And VF = forward drop of LED
O.9V = volt~gedrop of transistors
N = number of digits in displav
IF = required ilver~ge LED current
FIGURE 7. Interfacing Common-Anode
LED Displays
FIGURE 8. Interfacing Common-Cathode
LED Displays
WhereAt isink!.!
AndV F = forward drop of LED
O.6V'" voltage drop of transistors
N = number of digIts In display
(Ov)
fYPICAL
EN~I:~~f----------f2N5081IX6)
OUTPUT~
Stt~~~t
MULfl~l~l
-"} f----------..---1
J
\ + - - - - -....--,
~~Jml+~~-'
1)5~----~±:=.;::,::;,,~''';''::;'::;'M'~'';;';::,,~!;-4-T--jr-TINTER [JIGIT BLANKING
FI GUR E 9. Interface Panaplex 11* Neon Display Tube
*TM of Burroughs Corp.
10·8
V oo )/2
functional description (con't)
s:
s:
lOOk
(J'I
...
w
0224
(J'I
SEG
d
6
'"
189101112
IU
lUi
I
I
I
I
~
470
eL'lo
PM
AM
~PJilll
lN5086
,,.
(Xl)
(JfIlVERI
0.1 r,,120DV
(Xli
IXII
lN914
'"
I
I
~I~
(XII
....----_'0_-_'~--
-105V----------------------'~----
FIGURE 10. MM5309 Driving Gas-Discharge Display, Typical Applications
10-9
Complex Standards
MM5311,MM5312,MM5313,MM5314, digital clocks
general description
features
These digital clocks are monolithic MOS integrated
circuits utilizing P-channel low-threshold, enhancement mode devices_ The devices provide all the
logic required to build several types of clocks_
Two display modes (four or six digits) facilitate
end-product designs of varied sophistication_ The
circuits interface to LED and gas discharge displays
with minimal additional components, and require
only a single power supply_ The timekeeping function operates from either a 50 or 60 Hz input,
and the display format may be either 12 hours
(with leading-zero blanking) or 24 hours_ Outputs
consist of multiplexed display drives (BCD and
7-1;egment) and digit enables_ The devices operate
over a power supply range of 11 to 19V and do
not require a regulated supply_ The MM5311
through MM5314 clocks are packaged in 24 and
28 lead dual-in-line packages_
•
50 or 60 Hz operation
•
4 to 6 digit display mode
•
12 or 24 hour display format
•
Leading-zero blanking (12-hour format)
•
BCD and 7-segment outputs
•
Single power supply
•
Fast and slow set controls
•
Output enable control
•
Internal multiplex oscillator
•
Hold count control
applications
•
•
•
•
Desk clocks
Automobile clocks
Industrial clocks
Military clocks
connection diagrams
Dual-in-Line Package
Vo
"....!
om.".
( ••
,"
8CDOUTPUTS
Bfif4-l
(NEGATIVE
TRUE)
RD1~
RDI-.!!
MULTIPLEXED
1 SEGMENT
OUTPUTS
a
Dual-in-Line Package
OUTPUT ENABLE
~4I6DIIlITSELECT
~MUKTIMING
~'j
~H,
• .2
fB-HlO
,..!
f11-s,
• ..!
p!!..s,o
OUTPUTS
MUlTIPLEXED
1SEGMENT
OUTPUTS
r!!.SOI60H.INPUT
f1!-FASTSH
l..!l
f1!-SlIlWSET
~BCDe
~VDO
1
• ..!.
,..1.1
2
BCD22..
HCD1~
DIGIT
ENABU
• .Jll
5DlfiGIbSElEcr
{""-"
~M'o
• ..!
12124HDURSELECT..,!}
MULTIPLEXED
BCDUUTfUTS
(NEGATIVE
TRUE)
t£MUXTIMING
~'l
• ..!.
~Ml0
,..!.
~H,
DIGIT
ENABLE
OUTPUTS
.-"
~H,o
• ..!.
tlL
,.1
~SD/60HlINPUT
I..!!
..!! FA$TSET
1 PPSOUTPUT
rltllO lD
12124I1RSElECT.!!
..!!.SlDWSH
~v..
50/6GHISHECT.!l
,,-,'.
Order Number MM5311 D
Order Number MM5311 N
Order Number MM5312D
Order Number MM5312N
See Package 7
See Package 19
See Package 6
See Package 18
Dual-I n-Line Package
V",,--!.
MUlTIPLEX~l)
BCD OUTPUTS
(NEGATIVE
TRUE~
("""
BC04...1.
l!.M,o
l!.H,
MULTIPLEXEO
1SEGMENT
OUTPUTS
E..1I1O
..E. s,
.l.
v,,02.
.!..M,
B'CDl....l
• .2
OUTPUT ENABLE
~~~~NG
BCIi2....!
• ...!
Dual-I n-Line Package
~4I6oIGITSELECT
j-
E!WIlE
,,""'"
MULTIPLEXEO
JSEGMENT
OUTPUTS
2!.416oIGITSELECT
.E- MUX TIMING
.2-
.E.M,
.2.
,2-
,!1.,M,"
~II'
• ..!.
fl!.H,o
.2-
~S,
ulGIT
ENABLE
OUTPUTS
,..!
2.!.s,o
• ..!
.!!!..'PPSOUTPUT
,2.
• ..l2
~S,"
.!.!..S0160H"NPUT
f...!!
,2.
f2i 50!60H,INPUT
.!!..FASTSET
g2!
.!.!.. SLOW SET
12124HRSEL£CT..!.!!..
12124HRSElECT~
.!!..HOLO
511160H,SHECT..!.!.
5GI60H,SElECT..!!
..!!..V..
V..
.!!.
~FASTSET
p!.SlOWSET
~HOlD
Order Number MM5313D
Order Number MM5313N
Order Number MM5314D
Order Number MM5314N
See Package 7
See Package 19
See Package 6
See Package 18
10-10
s:
s:UI
W
....
....
s:
s:UI
W
....
absolute maximum ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Vss + 0.3 to Vss - 20V
-25°C to +70°C
-£5°C to +150°C
300°C
electrical characteristics
TA within operating range, Vss = +14V, Voo = OV, unless otherwise specified.
CONDITIONS
PARAMETER
Power Supply Voltage
Vss (Voo "OVI
Power Supply Current
Vss == +14V (No Output Loads)
50/60 Hz Input Frequency
MIN
11
TYP
MAX
~
UNITS
14
19
V
8.0
15
mA
de
50ar 60
60k
Hz
Vss - 2.0
-2.0
Vss -1.0
0
Vss
4.0
V
V
de
1.0
60
kHz
-2.0
Vss
0
4.0
V
V
2.0
5.0
s:
s:UI
....WW
50/60 Hz Input Voltage
Logical High Level
Log.ieal Low Level
Multiplex Frequency
Determined by External R & C
All Logic Inputs
Logical High Level
Logical Low Level
Internal20kU Resistor to Vss
BCD and 7·Segment Outputs
Logical High Level
Logical Low Level
Loaded 2kf! to V DO
Digital Enable Outputs
logical High Level
Logical Low Level
s:
s:UI
....W
~
Loaded lOOn to V ss
5.0
10.0
20
0.Q1
mAsQurce
0.3
25
mAsource
mAsink
mAsource
functional description
A block diagram of the MM5311 thru MM5314
digital clocks is shown in Figure 1. The various
functional capabilities of the clocks are listed in
Table 1. Connection diagrams for these devices are
shown on page 1. The following discussions are
based on Figure 1.
50 or 60 Hz Input: This input is applied to a
Schmitt trigger shaping circuit which provides
approximately five volts of hysteresis and allows
using a filtered sinewave input. A simple RC
filter such as shown in Figure 10 should be used
to remove possible line voltage transients that
could either cause the clock to gain time or
damage the device. The input should swing between
Vss and Voo. The shaper output drives a counter
chain which performs the time keeping function.
50 or 60 Hz Select Input: This input programs the
prescale counter to divide by either 50 or 60 to
obtain a l·pps timebase. The counter is programmed
for 60 Hz operation by connecting this input to
Voo. An internal 20 kf! pull·up resistor is common
to this pin; simply leaving this input unconnected
programs the clock for 50 Hz operation. As shown
in Figure 1, the prescale counter provides both
l·pps and 10·pps signals. As shown in Table 1,
the MM5312 and MM5313 clocks provide the
l·pps signal as an output. On these clocks, the
10·pps signal (in place of the l·pps signal) may be
selected as an output via a lead-bonding option.
Time Setting Inputs: Both fast and slow setting
inputs, as well as a hold input, are provided.
Internal 20 kf! pull-up resistors provide the normal
timekeeping function. Switching any of these
inputs (one at a time) to Voo results in the
desired time setting function.
The three gates in the counter chain (Figure 1) are
used for setting time. During normal operation,
gate A connects the shaper output to a prescale
counter (+ 50 or + 60); gates Band C cascade the
remaining counters. Gate A is used to inhibit the
input to the counters for the duration of slow,
fast or hold time·setting input activity. Gate B is
used to connect the shaper output directly to a
seconds counter (+ 60). the condition for slow
advance. Likewise, gate C connects the shaper
output directly to a minutes counter (+ 60) for
fast advance.
Fast set then, advances hours information at one
hour per second and slow set advances minutes
information at one minute per second.
12 or 24 Hour Select Input: This input is used to
program the hours counter to divide by either 12
or 24, thereby providing the desired display format.
The 12-hour display format is selected by connect·
ing this input to Voo; leaving the input unconnected (internal 20 kf! pull-up) selects the 24-hour
format.
Output Multiplexer Operation: The seconds, minutes, and hours counters continuously reflect the
time of day. Outputs from each counter (indicative
of both units and tens of seconds, minutes, and
hours) are time-division multiplexed to provide
digit·sequential access to the time data. Thus,
instead of requiring 42 leads to interconnect a
six-digit clock and its display (7 segments per
digit), only 13 output leads are required. The
multiplexer is addressed by a multiplex divider
decoder, which is driven by a multiplex oscillator.
The oscillator and external timing components
set the frequency of the multiplexing function
and, as controlled by the 4 or 6 digit select
10·11
functional description (con't)
input, the divider determines whether data will
be output for 4 or 6 digits. A zero·blanking
circuit suppresses the zero that would otherwise
sometimes appear in the tens-of-hours display;
blanking is effective only in the 12-hour format.
The multiplexer addresses also become the display
digit-enable outputs. The multiplexer outputs are
applied to a decoder which is used to address a
programmable (code converting) ROM. This ROM
generates the final output codes, i.e., BCD and
7 -segment. The sequential output order is from
digit-6 (unit seconds) thru digit-1 (tens of hours).
Multiplex Timing Input: The multiplex oscillator
is shown in Figure 2. Adding an external resistor
and capacitor to this circuit via the multiplex
timing input (as shown in Figure 10) produces a
relaxation oscillator. The waveform at this input
is a quasi-sawtooth that is squared by the shaping
action of the schmitt trigger in Figure 2. Figure 3
provides guidelines for selecting the external components relative to desired multiplex frequency.
Figure 4 illustrates two methods of synchronizing
the multiplex oscillator to an external timebase.
The external RC timing components may be
omitted and this input may be driven by an
external timebase; the required logic levels are the
same as the 50 or 60 Hz input.
....
....
M
It)
::E
::E
SELECT ..- -______
UDHI
4 or 6 Digit Select Input: Like the other control
inputs, this input is provided with an internal
20 kn pull-up resistor. With no input connection
the clock outputs data for a 4 digit display. Applying Vee to this input provides a 6 digit display
(not applicable to the MM5312 clock, see Table 1).
Output Enable Input: With this pin unconnected
the sa:i and 7-segment outputs are enabled (via an
internal 20 kn pull-up). Switching Vee to this
input inhibits these outputs.
Output Circuits: Figure 5-A illustrates the circuit
used for the BCD and 7-segment outputs. Figure
5-B shows the digit enable output circuit. Figure 6
illustrates interfacing these outputs to standard
and low-power TTL. Figures 7 and 8 illustrate
methods of interfacing these outputs to commonanode and common-cathode LED displays, respectively. A method of interfacing these clocks to
gas-discharge display tubes is shown in Figure 9.
When driving gas-discharge displays which enclose
more than one digit in a common gas envelope, it
is necessary to inhibit the segment drive voltage(s)
during inter-digit transitions. Figure 9 also illustrates a method of generating a voltage for application to the output enable input to accomplish the
required inter-digit blanking.
~::::::::::~~--r=======~::::;:::::::::::::~~
12114 "OUR
5l1li111:1
SELECT
I"'UT
'. <>-+
,~<>-+
I
L~~----lI~----~::::::::::::::=-~'mn
AS REa'o
ENAILE
MULTIPLEXED
RDomm
MULTIPUXED
HEGMEIilT
Du,",un
IDUlPUn
f-:==============-.':::::==============~>DlGITEII"IU:
MULTIPLEX
TlIIIINB
.N'UT
FIGURE 1. MM5311 thru MM5314 Digital Clocks, Block Diagram
.......
OUTPUT OR
MULTIPLEX
50110 Hz
OSCILLATOR
INPUTOfl
MULTIPLEX
TIMING
COMPONENTS
OU1'I'UT
1.000.000
I
VDO
I
I
I
I
I
I
'-I
-EFFECTIVELY
ffi
ff:
E
5
'"
DD~~~I~~M:I~~~~~~~~~~ TO
10,000
::I
I
y.
I
i:; 100,000
iii
I
I
L~,
....
I
11------0< 1- _ _ _ _ _ -1
ri
!
::I
1000
l00pF
1000pF
O.OI"F O.I"F
CAPACITANCE C {WITH R: 100kl
MULTIPLEX OSCILLATOR
Y.
FIGURE 2. 50/60 Hz Shaping CircuitlMultiplex Oscillator
10-12
FIGURE 3. Multiplex Timing Component.selection Guide
functional description (con't)
o-j I-.....==~
Cl
EXTERNAL
TIME
BASE
EXTERNAL
CLOCK
IISIAL
MULTIPLEX
TIMING IN'UT
(INPUT DR OUTPUTI
R'
Note: Free Tunningfrequency should beset to runslightlv
lower than system frequency OYer tempenrtuTe. External
Voo
time IIase RIiIY be input or output.
L-_ _ _..J ...
*R ;;-'110kn
FIGURE 4. Synchronizing ar Triggering Multiplex Oscillators
v..
v"
DIGIT ENABLE
OImUT
.~~v.
Vou
l.ft.GMENT BCD DR ,_
Ou....UY
(OPEN ORAIIII
(AI
(BI
FIGURE 5. Output Circuits
V.
Vas" +5V
ANV 74L GATE
ANY 1401 GATES
Vee "5V
Vcc "'5V
MM5311
For Vss" +5, Voo;; -12, R ;; 18 lin
VD•
FOT V. '" +10 ta nv, Voo '" GND, A = 3 lin
FOR Vss" +5, Voo=-12. R;; Uk
Vou =-1IV
Note: Digit select will drive TTL directlV when +5, -12
supplies are used.
MOS ta TTL Interface
MOS to Low Power TTL Interface
FIGURE 6. Interfacing TTL
~--~------------~---v.
TYPICAL
EN~:~~ L . . I
OUTPUT
RL =
""CAL LED
IEGMEII"
ItO_ON·MODE!
SUtMAS
IlAfl.IA.OR
EDUIV.
v~,
__- '__________
~~~
Vss -VOD -VF -O.6V
N (IF)
WHERE RL IS IN kn
AND VF = fORWARD DROP OF LED
O.6V "" VOLTAGE DROP OF TRANSISTORS
N = NUMBER OF DIGITS IN DISPLAY
IF = REQUIRED AVERAGE LED CURRENT
__
FIGURE 7. Interfacing Common-Anade LED Displays
10-13
functional description (con't)
'.--~------------~~-TVPICAl
lOV)
SEGMEIfT
OUTPUT~
TYPiCAL
~~~ml-"""'l....r------------------1
,<'Iss -1.5
!;;::~T~EO
(COMMON'CATHODE)
SUCH ASMAN·l.
DR Eomv.
TYPICAL
SEGMENT
MMun
TYPICAL
.....
~~~:t~I-----------I
'"
TYPICAL
SEGMENT
DUTJlUT
MUl i:~~~~
,,,--.....------------........> - -
I
1+__________.....__-,
f~r:~:
RL '" (Vss - V~D:::) - VF - 1.5V
1+--.---,
(1m
WHERE AL IS IN kn
AND VF
'"
FORWARD DROP OF LED
O.9V"" VOLTAGE DROP OF TRANSISTORS
N '" NUMBER OF DIGITS IN DISPLAY
IF = REOUIRED AVERAGE LED CURRENT
FIGURE 8. Interfacing Common-Cathode
LED Displays
FI GUR E 9. I ntertacing Panaplex 11* Neon Display Tube
.....~._--------~._--------_.------------------------_t_
,.----------------~------
....
AC IN..J\M:1~::_--;::=t------~_:~----",..._,
01 22
0221
D3201--+-----+---i
04 I.
2N51188
SE'
~
•
f
D
3 4 5 Ii
1
I
.'
"
...
,
c
I
I
-----
~
Tv~
CATHODE
DRIVER
-".----....--....--....--~~--.......
INTER-DIGIT BLANKING CIRCUIT
0.02
ZOOV
lN914
I
I
I
lNI14
41k
".
~!~
-...-----------------------------....--.....~--+-------_t------....--+---+--......
-.•• ----------------------------....--------4>---------....---..----FIGURE 10. MM5314AN Driving Gas·Discharge Display, Typical Application
*TM of Burroughs Corp.
10·14
Complex Standards
MM5316 digital alarm clock
general description
The MM5316 digital alarm clock is a monolithic
MOS integrated circuit utilizing p-channel lowthreshold, enhancement mode and ion-implanted
depletion mode devices_ It provides all the logic
required to build several types of clocks and
timers_ Four display modes (time, seconds, alarm
and sleep) are provided to optimize circuit utility.
The circuit interfaces directly with seven-segment
fluorescent tubes or liquid crystal displays, and
requires only a single power supply. The timekeeping function operates from either a 50 or 60
Hz input, and the display format may be either
12 hours (with leading-zero blanking and AM/PM
indication) or 24 hours_ Outputs consist of display
drives, sleep (e.g., timed radio turn-off), and alarm
enable. Power failure indication is provided to
inform the user that incorrect time is being displayed_ Setting the ti me cancels this indication_
The device operates over a power supply range of
B to 29 volts and does not require a regulated
supply. The MM5316 is packaged in a 40-lead dualin-line package.
features
•
•
•
•
50 or 60 Hz operation
Single power supply
Low power dissipation (32 mW at BV)
12 or 24 hour display format
• AM/PM outputs
}
• Leading-zero blanking
12-hour format
•
•
•
•
•
•
•
24-hour alarm setting
All counters are resettable
Fast and slow set controls
Power failure indication
Blanking/brightness control capability
Elimination of illegal time display at turn-on
Direct interface to fluorescent tubes or liquid
crystal displays
• 9-minute snooze alarm
• Presettable 59-minute sleep timer
applications
•
•
•
•
•
•
•
•
•
•
•
•
Alarm clocks
Desk clocks
Clock radios
Automobile clocks
Stopwatches
Industrial clocks
Military clocks
Portable clocks
Photography timers
Industrial timers
Appliance timers
Sequential controllers
block and connection diagrams
OUTPUT
~~~~------------------------------------------,
Dual-In-Line Package
41 PM OUTPUT
JIIH.OUTPIIT
31 alMHASELECT
"
HRS_I
!ilIIG H. SElECT
UiGJIIH •• IPUT
:M FAITSETIN,UT
: ::N~EST~::::YINPUT
ALA"IIIDISPLAYIII'UT
TOIIGDAS
0161T
:
Vgo
U
;~naUTfUT
: :~::: :~~;~UT
24 SNOOZE INPUT
MIItS-.
D~~~:~ O-::"--------------------------------------.j
"
"
;~
OUTPUT CO_Oil SOURCE
s:1~~::O-::·--------------------------------------.j
ILA~:~~~ O-::"--------------------------------------.j :~~~~t~~
SlO. SET
"
o-----tI>
FASTSET~
v.. ~
Order Number MM5316D
See Package 8
Order Number MM5316N
See Package 20
VDD~
FIGURE 1_ MM5316 Digital Alarm Clock, Block Diagram
FIGURE 2. Connection Diagram
10-15
CD
~
('I)
It)
:!:
:!:
absolute maximum ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 sec)
Vss +0.3 to Vss -29V
-25°C to +70°C
-65°C to +150°C
300°C
electrical characteristics
TA within operating range, Vss = +8 to +29V, VDD = OV, unless otherwise specified.
PARAMETER
CONDITIONS
=OVI
Power Supply Voltage:
Vss (Voo
Power Supply Current:
no output loads
Vss
Vss
MIN
TYP
+8
= +8V
= +29V
MAX
UNITS
+29
V
2
4
3
5
mA
mA
50 or 60
30k
Hz
50/60 Hz Input:
DC
Frequency
Voltage
Logical High Level
Vss -l
Vss
V
Logical Low Level
Voo
Voo +1
V
Blanking Input Voltage:
Logical High Level
Vss -2
Vss
V
logical Low Level
Voo
Vss-4
V
Vss
V
All Other Input Voltages:
Vss -l
Logical High Level
Logical Low Level
Internal 2.5 MO Resistor to Voo
Power Failure Detect Voltage:
(Vss Voltage)
Output Currents:
Vss
Voo
9
Voo
Voo +2
20
V
V
=+21 to +29V, Voo =OV
1 Hz Display
= Vss -2V
Logical High Level
VOH
Logical Low Level
VOL"" Voo
1
I'A
I'A
1
I'A
1
I'A
I'A
1500
10', of Hours (b&c), 10', of Minute, (a&d)
= Vss -
Logical High Level
VOH
logical Low Level
VOL:::: Voo
2V
p.A
.1000
All Other Display, Alarm and Sleep Outputs
10·16
logical High Level
VOH
= Vss
Logical Low Level
VOL
= VOD
- 2V
500
functional description
A block diagram of the MM5316 digital alarm
clock is shown in Figure 1. The various display
modes provided by this clock are listed in Table 1.
The functions of the setting controls are listed in
Table 2. Figure 2 is a connection diagram. The
following discussions are based on Figure 1.
50 or 60 Hz Input (pin 35); A shaping circuit
(Figure 3) is provided to square the 50 or 60 Hz
input. This circuit allows use of a filtered sinewave
input. The circuit is a Schmitt trigger that is
designed to provide about 6V of hysteresis. A
simple RC filter, such as shown in Figure 7, should
be used to remove possible line-voltage transients
that could either cause the clock to gain time or
damage the device. The input should swing between
Vss and Voo. The shaper output drives a counter
chain which performs the timekeeping function.
50 or 60 Hz Select Input (pin 36); A programmable
prescale counter divides the input line frequency by
either 50 or 60 to obtain a 1-pps time base. This
counter is programmed to divide by 60 simply by
leaving pin 38 unconnected; pull·down to V 00 is
provided by an internal 2.5 MQ resistor. Operation
at 50 Hz is programmed by connecting pin 38
to Vss.
Display Mode Select I nputs (pins 30 thru 32); I n the
absence of any of these three inputs, the display
drivers present time·of-day information to the
appropriate display digits. Internal 2.5 MQ pulldown resistors allow use of simple SPST switches
to select the display mode. If more than one
mode is selected, the priorities are as noted in
Table 1. Alternate display modes are selected by
applying Vss to the appropriate pin. As shown in
Figure 1 the code converters receive time, seconds,
alarm and sleep information from appropriate
points in the clock circuitry. The display mode
select inputs control the gating of the desired data
to the code converter inputs and ultimately (via
output drivers) to the display digits.
Time Setting Inputs (pins 33 and 34); Both fast
and slow setting inputs are provided. These inputs
are applied either singly or in combination to
obtain the control functions listed in Table 2.
Again, internal 2.5 MQ pull-down resistors are
provided; application of Vss to these pins effects
the control functions. Note that the control functions proper are dependent on the selected display
mode. For example, a hold·time control function
is obtained by selecting seconds display and actuating the slow set input. As another example, the
clock time may be reset to 12;00;00 AM, in the
12-hour format (00;00;00 in the 24-hour format),
by selecting seconds display and actuating both
slow and fast set inputs.
Blanking Control Input (pin 37); Connecting this
Schmitt trigger input to Voo places all display
drivers in a non-conducting, high·impedance state,
thereby inhibiting the display. See Figures 3 and 4.
Conversely, Vss applied to this input enables the
display.
Output Common Source Connection (pin 23); All
display output drivers are open-drain devices with
all sources common to pin 23 (Figure 4), When
using fluorescent tube displays, Vss or a display
brightness control voltage is permanently connected to this pin. Since the brightness of a fluores·
cent tube display is dependent on the anode
(segment) voltage, applying a variable voltage to
pin 23 results in a display brightness control. This
control is shown in Figure 7. However, when
using liquid crystal displays, the lifetime of the
display device is optimized when AC drive voltages
are provided. The common source connection of
the MM5316 output drivers facilitates generating
AC drive voltages. An interface circuit for driving
liquid crystal displays is shown in Figure 5.
12 or 24 Hour Select Input (pin 38): By leaving
this pin unconnected, the outputs for the mostsignificant display digit (1 O's of hours) are programmed to provide a 12-hour display format. An
internal 2.5 MQ pull·down resistor is again pro·
vided. Connecting this pin to Vss programs the
24·hour display format. Also, the output connections (pins 1, 2, 39 and 40) are different for each
format. Figure 6 illustrates these differences. In
addition to displaying 10's of hours, this digit
provides an AM/PM indication (12-hour format
only) and the power failure indication. In the
12·hour format, AM indication is provided by
segment "f"; PM indication by segment "e." The
power failure indication consists of a flashing of
the AM or PM indicator at a 1-Hz rate. A fast or
slow set input resets an internal power failure
latch and returns the display to normal. In the
24-hour format, the power failure indication consists of flashing segments "c" and "f" for times
less than 10 hours, and of a flashing segment "c"
for times equal to or greater than ,10 hours but
less than 20 hours; and a flashing segment "g" for
times equal to or greater than 20 hours.
Alarm Operation and Output (pin 25): The alarm
comparator (Figure 1) senses coincidence between
the alarm counters (the alarm setting) and the
time counters (real time). The comparator output
is used to set a latch in the alarm and sleep circuits.
The latch output enables the alarm output driver
(Figure 4), the MM5316 output that is used to
control the external alarm sound generator. The
alarm latch remains set for 59 minutes, during
which the alarm will therefore sound if the latch
output is not temporarily inhibited by another
latch set by the snooze alarm input (pin 24) or
reset by the alarm off input (pin 26).
Snooze Alarm Input (pin 24): Momentarily connecting pin 24 to Vss inhibits the alarm output for
between 8 and 9 minutes, after which the alarm
will again be sounded. This input is pulled-down
to Voo by an internal 2.5 MQ resistor. The
snooze alarm feature may be repeatedly used
during the 59 minutes in which the alarm latch
remains set.
10-17
functional description (con't)
Alarm Off Input (pin 26): Momentarily connecting
pin 26 to Vss resets the alarm latch and thereby
silences the alarm. This input is also returned to
Voo by an internal 2.5 M1l resistor. The momen·
tary alarm off input also readies the alarm latch
for the next comparator output, and the alarm
wi II automatically sound again in 24 hours (or at
a new alarm setting). If it is desired to silence the
alarm for a day or more, the alarm off input should
remain at Vss.
Sleep Timer and Output (pin 27): The sleep output
at pin 27 can be used to turn off a radio after a
desired time interval of up to 59 minutes. The
time interval is chosen by selecting the sleep dis·
play mode (Table 1) and setting the desired time
interval (Table 21. This automatically results in a
current·source output via pin 27, which can be
used to turn on a radio (or other appliance). When
the sleep counter, which counts downwards, reaches
00 minutes, a latch is reset and the sleep output
current drive is removed, thereby turning off the
radio. This turn-off may also be manually controlled (at any time in the countdown) by a mo·
memtary V ss connection to the snooze input
(pin 24). The output circuitry is the same as the
other outputs (Figure 4).
'"
·OUTPlITCOMMONSOURC(8USIPINZJ!
'''''AI~~
SO/iOPPS
OIlTf'UTOR
BtANKING
SIGNAL
BlANKING
tFROM--t
SHAPER)
OUTPUT
IOPENDRAIN)
'.
*Alarm and sleep output sources are connected to Vss;
blanking is not applied to these outputs.
'.
FIGURE 3. 50/60 Hz or Blanking Input Shaping Circuits
FIGURE 4. Output Circuits
(+2~~----'----'
....
l'V~MS
mtoVDD
..\
Ul -'·
SEGMENT "OH"
",V DD +4V
Note 1: At should be chosen for equal peak.to-peak swings at points "A" and "B," so
there is no de component placed on the segment.
Note 2: R2 mayor may not be required, depending on the display used and the parasitic
circuit capacitance associated with ttm segment output. This resistor should be just small
enough to assure that off segments are not visible.
FIGURE 5. Liquid Crystal Display Interface
PIN 1
AM
PlN4(I
PIN 1
"~"'~"...
.
"
"
FIGURE 6. Wiring Ten'..of·hours Digit
10·18
I'IN4t1
PM
functional description (con't)
TABLE 1.
'SELECTED
DISPLAY MODE
MM5316 Display Modas
DIGIT NO. 1
DIGIT NO. 2
DIGIT NO.4
DIGIT NO. 3
Time Display
10's of Hours & AM/PM
Hours
10's of Minutes
Minutes
Seconds Display
Blanked
Minutes
la's of Seconds
Seconds
Alarm Display
la's of Hours & AM/PM
Hours
10's of Minutes
Minutes
Sleep Display
Blanked
Blanked
10's of Minutes
Minutes
*If more than one display mode input is applied, the display priorities are in the order of Sleep
(overrides all others!, Alarm, Seconds, Time (no other mode selected).
TABLE 2.
SELECTED
DISPLAY MODE
*Tiine
CONTROL
INPUT
Slow
Fast
Both
Alarm
Seconds
Sleep
MM5316 Setting Control Functions
CONTROL FUNCTION
Minutes Advance at 2 Hz Rate
Minutes Advance at 60 Hz Rate
Minutes Advance at 60 Hz Rate
Slow
Alarm Minutes Advance at 2 Hz Rate
Fast
Both
Both
Alarm Minutes Advance at 60 Hz Rate
Slow
Fast
Both
Both
Input to Entire Time Counter is Inhibited (Hold)
Seconds and 10's of Seconds Reset to Zero Without
a Carry to Minutes
Time Resets to 12:00:00 AM (12-hour format)
Time Resets to 00:00:00 (24-hour format)
Slow
Fast
Both
Substracts Count at 2 Hz
Substracts Count at 60 Hz
Substracts Count at 60 Hz
Alarm Resets to 12:00 AM (12·hour format)
Alarm Resets to 00:00 (24-hour format)
*When setting time sleep minutes will decrement at rate of time counter, until the sleep counter
reaches 00 minutes (sleep counter will not recycle).
typical application
Figure 7 is a schematic diagram of a general purpose alarm clock using the MM5316 and a
fluorescent tube display.
I-
""~J
_MI
IIV 11k
.,,"
---"-- 1
'~"
-"
r
I
I
I
I
I
I
I
IL.___
'NY<
I
I
I
I
IIC
I
I'I'IOF
1 MOIIIIS
_ ___ JI:M~
MODE
FIGURE 7. Typical Application
10·19
Complex Standards
MM4320/MM5320 TV camera sync generator
general description
features
The MM43201MM5320 TV camera sync generator
is an MOS, P-channel enhancement mode, LSI
chip designed to supply the basic sync functions
for either color or monochrome 525 line/60 Hz
interlaced camera and video recorder applications.
Required power supplies are +5V and -12V, or
any other combination resulting in Vss - 17V.
All inputs and outputs are TTL compatible without the use of external··components. Military and
commercial temperature ranges are available.
•
Multi-function gen lock input provides flexible control of multiple camera installations
•
•
•
16 lead dual-in-line package
Conventional +5V, -12V power supplies
Uses 2.04545 MHz or 1.260 MHz input reference
Field indexing provided for VTR applications
Color burst gate and sync allow stable color
operation
•
•
logic and connection diagrams
HORIZ~~~~~ O------pw = 235 ns, Vss = +5.0V
Input Clock Frequency = 2.04545 MHz
ac electrical characteristics
T A within operating temperature range Vss = +5.0V ±5%, V GG = -12V ±5%, unless otherwise stated.
PARAMETER
Input Clock Pulse Width (¢pw)
CONOITIONS
Input Clock Frequency
=
MIN
TYP
MAX
210
190
235
235
260
280
ns
ns
530
520
545
545
560
570
ns
ns
500
600
800
ns
500
500
750
750
ns
ns
600
700
ns
UNITS
2.04545 MHz
t/>t r • tt "" 20 ns
MM4320
MM5320
Input Clock Pulse Width (--+
0-----.
0---------<>\
MULTiPlEX
OSCILLATOR
0-------------------------,
LINE
FREOUENCY
INPUT
10 HOURS
HOURS
1
DIGIT ANODE
DRIVE OUTPUTS
OA~T~~~
ALARM
OFF
+-____--,
0----..,
AM/PM
COLON
}
AUXILIARY
CATHODE DRIVE
OUTPUTS
SNOOZE
INPUT
SLEEP
+-___..J
MULTIPLEXEO
1·SEGMENT
1
CATHODE DRIVE
OUTPUTS
ALARM
DIS1'LAY
SLEEP
BRIGHTNESS
CO~!~~~
o-----____________________.J
0---------------------------'
0---------<>1
SHAPING
CIRCUIT
FIGURE 1. MM5370 and MM5371 Digital Alarm Clock, Block Diagram
10·29
.....
o
functional description (con't)
TABLE I. MM5370 and MM5371 Displav Modes
'SELECTED
DISPLAY MODE
DIGIT NO.1
DIGIT NO.2
DIGIT NO.3
Time
lO's of Hours
Unit Hours
10's of Minutes
Unit Minutes
Alarm
1O's of Hours
Unit Hours
10's of Minutes
Unit Minutes
Sleep
Blanked
Blanked
1O's of Minutes
Unit Minutes
DIGIT NO.4
*If more than one display mode input is applied, the display priorities are in the order of Sleep
(overrides aO others), Alarm, Seconds, Time (no other mode selected).
Table II. MM5370 and MM5371 Setting Control Functions
SELECTED
DISPLAY MODE
CONTROL
INPUT
Time*
Slow
Fast
B9th
Reset
Reset
Minutes Advance at 2 Hz Rate
Minutes Advance at 60 Hz Rate
Minutes Advance at 60 Hz Rate
Time Resets to 12:00 AM 112·hour format)
Time Resets to 00:00 124·hour format)
Alarm
Slow
Fast
Both
Both
Alarm
Alarm
Alarm
Alarm
Sleep
Slow
Fast
Both
Subtracts Count at 2 Hz Rate
Subtracts Count at 60 Hz Rate
Subtracts Count at 60 Hz Rate
CONTROL FUNCTION
Minutes Advance at 2 Hz Rate
Minutes Advance at 60 Hz Rate
Resets to 12:00 AM 112·hour format)
Resets to 00:00 124·hour format)
*When setting time sleep minutes will decrement at rate of time counter, until the sleep counter
reaches 00 minutes (sleep counter will not recycle).
LINE
FREQUENCY
INPUT OR
BRIGHTNESS
CONTROL
INPUT
SHAPED LINE
FREQUENCY
DR BRIGHTNESS
CONTROL SIGNAL
FIGURE 2. 60 Hz (or 50 Hz) Input (or Brightne.. Control Input) Shaping Circuit
10·30
s:
s:
U1
functional description (con't)
W
.....
o
MULTIPLEX~
TIMING
INPUT
I
I
I
II
I
II
s:
s:
U1
",::~'~:~": nii-----------~r 11'----___
w
::l
II
:n1'-_________
0I611NO.3:
10'SOF MINS. ~
I
~
-<
n
I
I
I
I
~~I------~
U~II~I~~~R; I
~------
I
::
n
~I:I~:~S~~
I
ANY
SEGMENT
_ -__IL
~
I
j
r--:;--,L--'r - - IL
L.::J
u------Lf
ON
urr
I
I
AM I I COLON ~
L.:...J
L:.:..J-- ~~~.;~'~;:~;
AM/PM - - ,
CATHODES
~l'HIBLINKING
COLON DRIVE
COLON
CATHODES
i
i
:eOlDN:
L _ _ ~'"
FIGURE 3. Output Timing Diagram
MULTIPLEX
-teTiiNGINPUT
EXTERNAL
TIMING
COMPONENTS
1,000,000
I
+--6-.....
--1
~
OSCILLATOR
OUTPUT
5100,000
~
:::
e:
10,000
~
~
~
1000
"
100
10 pF
100 pF
10DDpF
O.01/-1F
O.1/-1F
CAPACITANCE C (WITH R=100k)
FIGURE 5. Multiplex Timing ComponentSelection Gu ide
FIGURE 4. Multiplex Oscillator Circuit
V~
__- , _ - , _ , -_ _ _
~
_ _ ___
EXTERNAL
TlMUASE
Voo - - - - - -.....- - -...._ _ _ __
Note 1: For synchronizing, free running period should be set to ruii
slightly longer than external timebase over temperature.
Note 2: For driving, timing capacitor should be deleted.
FIGURE 6. Synchronizing or Driving Multiplex Oscillator
10·31
functional description (con't)
V.
Q (DATA)
ALARM OR
OIDATA'«V.
SLEEP OUTPUT
V
00
(OPEN DRAIN)
TYPICAL DIGIT
OR SEGMENT
OUTPUT
v••
FIGURE 7. Output Circuits
...j '"
V.
,""
h
BRIGHTNESS
ADIUST
CIRCUIT
I
V~
I
MUXTIMING
>----
V.
~()o
SLOWSEr
~()o
FAST SET
~()o
RESET
~()o
ALARM DiSPlAY
~()o
ALARM OFF
~()o
SLEEP DISPLAY
~()o
SNOOZE
BRIGHTNESSCONT.
ALARM
} CONTROLSTO
ALARM AND/OR
RADIO CIRCUITS
SLEEP
IDOk(X4)
M
10M
MM5370
~
H
IOH
12/24 HOURS
'''~*f''~
!.i
.• .
IOH
v••
60Hz
IN
-'f
d
H
I
,
AMI
PM COLON
b
II
I
10.
•
'OM
GAS DISCHARGE
DISPLAY
lINEFREQ.
1111k
I
I
d
. AMI
PM COLON
1Mldl
II
II I
V.
/I
II
II
II
II
II
..
-150
-190
Jl II
Vss: DV
VDD = -21V tD -29V
II
f--
4.n
II
--1:
-------I
~,
r
O.OSpf
'50V
''''
-4IIVTO-HV
2111«1111
v•
--4
10·32
~
1111914
(~10)
ZZk
~
'"
II
I~F/I50V
FIGURE 8. Typical Application
.,"
ZN
~, ~
s:
s:U'I
Complex Standards
W
-...I
U'I
»
»
.......
s:
s:U'I
MM5375AA/MM5375AB/MM5375AC/
MM5375AO/MM5375AE digital alarm clock
W
-...I
U'I
»
general description
tc
.......
The MM5375 digital alarm clock is a monolithic
MOS integrated circuit utilizing p-channel low
threshold, enhancement mode and ion-implanted
depletion mode devices. It provides all the logic to
give a four or six digit twelve or twenty-four hour
display from a 50 or 60 Hz input. Inputs include
time setting, 60 Hz input, display brightness control, alarm set, snooze, alarm off, and multiplex
oscillator frequency control. Outputs consist of
8-segment selects (eighth segment for AM/PM and
colon indications). digit enables, and alarm signal
consisting of a 500 Hz to 1,000 Hz, squarewave
(frequency externally adjustable) gated on and off
at a 2.0 Hz rate. Power failure indication is provided to inform the user that incorrect time is being
displayed. Setting the time cancels this indication.
•
Elapsed time register option
•
24-hour alarm setting
•
All counters resetable
•
Fast and slow set controls
•
Power failure indication
•
Brightness control capabil ity
•
No illegal time display at turn-on
•
•
Alarm tone output
Simple interface to gas-discharge displays and
LED's
•
6 to 8 minute snooze alarm
•
Internal digit multiplex oscillator
•
Leading zero blanking
•
Activity indicator
•
4 or 6 digit operation
s:
s:U'I
W
-...I
U'I
»
(')
.......
s:
s:U'I
W
-...I
U'I
»
C
.......
s:
s:U'I
features
•
•
applications
50/60 Hz operation
Single power supply
•
Alarm clocks
Desk cI ocks
Automobile clocks
•
Low power dissipation
•
12/24 hour display format
•
•
•
•
AM/PM indication
Calendar register option
•
Industrial clocks
•
Military clocks
W
-...I
U'I
»m
connection diagram
Dual-In-Line Package
DIGIT
OUTPUTS
{1O~~~:::: ~
2!.
OIGIT
OUTPUTS
- - 1 SECOND
J
1 HOUR ...;..
10 HOURS -
10 SECONDS }
23
4
Voo ....:..
..E.
8TH SEGMENT OUTPUT
2.!.
BRIGHTNESS CONTROL
2.!!.
MULTIPLEX OSCILLATOR
DtS~N~V S~~AO~~ ...!.
.!! •
ALARM OFF
..2..
.!!c
ALARM OUTPUT
.!.
..!l.
SLOW SET
...!.
.!!oo
FAST SET
.!!
.!!,
60 Hz INPUT
.!l.
.l!.F
A
SEGMENT
OUTPUTS
vss .!.!.. ......._ _ _ _.....1.!.!..G
TOP VIEW
Order Number MM5375XXN
See Package 18
10-33
w
Dr· nv
VGG f!--J5V
OSC'~VDO
MOST
L-;;'--;;'--rr"---ii"--ii"~-ii"~-;,"'-----;i'r''_"..:J,~voo
J
1
9
n
SIGHIF
OIliIT(B)
NINENSN-4t
1/4" DIGIT lED
LEAST
SIGNIFICANT
OIliITU)
~~-
1
1"'-----1r---.. DlGITIJ)
I"--I---.OIGIT(S)
r - - I - - - . DlGIT{4)
I-'--I---.OIGIT(J)
0.'\
+
,:-ENHR
I-'--I---.DIGIT(ZI
"'t
"The DM15491 IIId DMI16l are National Semiconduc:tor foor and five element Darlinlton selment
drivers. The DM8863 is an eight
IIlem~t
Darlington digit driver.
I'
."
tAitemativety use two NSN33 triple 1/1" ditits and one NSN133 double 1/8" dilit with seperate
minussign,lndchangerasistorvaiulSto 100n.
FIGURE 1, TVPical Application - LED Displav
10-45
--c
-t ns"fTV:ICAl
IN914
.
re:
-t
.
rl
-t
-t
,
rl
"
-t
41KTVPICAl.............,
IODV
i-
",
"
'.
21 S,
"'. "'.
"'.
"'.
""' '"~!n
"'.
MMS12S
VGG f!--l5V
I5 R2
~Rl
.f':-
>.2.
:>.2.
,"
,"
.
"
,'.
'.
"
." .
"
.
t
r
VOO~-2aV
I6 R,
'::-
"'
~I"
13KTVPICA~~
I
I
I
I
~\I
82pf Voo I .•
T.os(:,~vool.
PANAPlH
PAATNOBR09Z52
9
56K
L -
~I~~; -
-- - -
DIGIT
1':"I"
X
I
....
10
28
Typical Digit Current vs
Digit Voltage
2,0~~m
~~~=VOG-35V
50
26
Vss - Voo{VI
.-
il!
25
VSS-VGG (V)
Vss - voo - 2ay
'-
MIN
Typical Scan Period vs eX
~
,.,"
TVP
I
I
5.0
-
.,.. -.
i--
I
. .
-0
MAX
j....: ~ po
TVP- r - r-
I- """"MIN
1.0
MI'!..,
Vss - VGG:Z 35V:f=I=
TA :2SOC
~
~
-I-"
TVP
10.0
I
I
~
MAX
...,..
.§
2.0
b
1.0
o
110
"'"
Vss - voo '" 26Y
'~
o
I
2
C IpF)
3
4
5
6
1
8
9 10
VSS-VT (V)
-lll/l/l
I I I _I I_I
FIGURE 4, MM5725 Display Font
accounting machine notation
The MM5725 performs its arithmetic according to
a logic form known as Polish notation. In this
notation, as pointed out in the description on
page one, the new number keyed into the machine
operates on the previously accumulated result only
when the operator key (+, -, x, +) is struck. And
at that point, the result appears. There is no
separate equals (=) key, as all four operator keys
perform the function of generating the result of a
calculation, The use of an operator key after the
data entry is a very natural mode of operation in,
for instance, credit balance transactions. For calculator users without previous training, as one
might typically classify first-time low-cost calculator buyers, it is equally natural to extend the
Polish notation to the multiply and divide operations,
Users who have been exposed to electric accounting machines, however, may be confused by this
routine. Those machines usually use a hybrid
notation, Polish in addition and SUbtraction, but
10-48
algebraic in multiplication and division: for example A x B = . The MM5725 may be used in
such machines by adding a key, wired in parallel
to the +/Enter key, called (~) and by marking the
existing multiplication and division keys ~ and -;.
The operation of A x B = C may now be compared
Polish Entry
2
+/Enter
"Pseudo· Hybrid" Key Caps
2
x Actually causes entry
3
3
x 6 appears
~ 6 appears
and E + F = GT looks like this:
8
8
+/Enter
~
4
4
2 appears
-
2 appears
sample calculations
CALCULATION
KEY
PROCEDURE
DISPLAY
-
2
1
3
3
7.
4
O.
3.
7.
7.
4
8
1
3.
O.
3.
3.
1
+ (Enter)
3.
1
8
7
6
5
4
3
Entry
Initial setting after clear operation
Enter number 37.48
Result
3
7
4
8
3
3
7.
Addition
a) 3.1+4.11;7.21
3
4
Result
1
1
4.
4.
1
4.
4.
1
1
+
7.
2
1
b) 0 + 4.11 ; 4.11
1
1
4.
4.
1
O.
4.
4.
1
1
+
4.
1
1
7.
7.
0
7.
0
3
O.
7.
7.
0
3
2
7.
0
3
4
Result
c) -7.032 + 3; -4.032
7
0
3
2
-
-
3
Result
+
d) 4.0053114 + 8 ; 12.005311
Assume 4.0053114
result from previous calculation
-
4.
0
3
2
4.
0
0
5
3
1
1
4
8.
1
2.
0
0
5
3
1
1
8
Result
+
2
3.
Subtraction
a) 4 - 2.1; 1.9
Result
4
O.
4.
+ (Enter)
4.
2
1
2.
2.
2.
1
-
1.
9
10-49
sample calculations (con't)
CALCULATION
KEY
PROCEDURE
DISPLAY
-
8
7
5
6
4
2
1
3.
3.
9
O.
3.
3.
9
7
3.
9
7
3
b) 0 - 3.97 = -3.97
3
9
7
Result
-
-
4.
O.
4.
4.
6
4.
6
3.
3.
1
3.
3.
1
1
7.
7
1
. c) -4.6 - 3.11 = -7.71
4
6
3
1
1
Result
-
-
Multiplication
a) 4 x 5 = 20
4
O.
4.
+ (Enter)
4.
5.
5
Result
b) above result x 5 = 100
Result
2
o.
0
O.
4
4
4
9.
O.
4.
9.
9.
6
4
9.
6
O.
4
2
x
5.
5
x
1
c) -49.6 x 0.42 = -20.832
4
9
6
Result
d) 8765.432 x 100. = 876543.20
assume first digit result from
previous calculation
Result
-
-
4
2
-
x
8
7
O.
O.
4
2
O.
8
3
2
6
5.
4
3
1
1
0
2
1.
O.
O.
3
2
0
1
0
0
x
8
7
6
5
4
Division
a) 4 + 3 = 1.3333333
4
O.
4.
+ (Enter)
4.
3.
3
Result
10·50
1.
3
3
3
3
3
3
3
sample calculations (con't)
CALCULATION
KEY
PROCEDURE
b) 3074: 7.5
Since no remainder beyond 5
all trailing zeros suppressed
DISPLAY
-
8
7
6
5
4
3
2
3
0
+ (Enter)
3.
3
3
4
4
5
+ (Enter)
9
9
9
9
9
9
9
9
Result
o.
o.
4.
Result
c) 45 7 9.9999999
: 4.5000000
1
o.
7.
5
4
4.
5.
4
9.
4.
9.
9
5
9.
9
9
0
9.
9
9
9
0
9.
9
9
9
9
0
9.
9
9
9
9
9
0
9.
9
9
9
9
9
9
0
5.
9.
9.
9
9
9
9
9
9
9
0
(zeros are shown when remainder exists)
o.
d) 42.676: 7.1
4
2
6
4
4
4
2.
+ (Enter)
4
2.
6
4.
2.
2.
6
6
6.
Result
7.
1
o.
e) 52770.003: 175666.66
5
2
7
5
5
2
+ (Enter)
5
2
0
0
3
1
7
5
6
o.
o.
o.
0
0
0
6
6.
6
5
2
7
7
o.
0
0
3
6
10-51
sample calculations (con't)
CALCULATION
KEY
PROCEDURE
DISPLAY
-
2
1
7
3.
O.
3.
3.
7
+ (Enter)
3.
7
8
7
6
5
4
3
Chain Calculation
a) 3.7 + 4.85 - 3.49 = 5.06
3
8
5
4.
4.
8
4.
4.
8
5
+
8.
5
5
4
4
9
3.
3.
4
3.
3.
4
9
-
5.
0
6
O.
4.
7.
2.
3
Result
b) 472
x .018 + 3.1 = 11.596
4
7
2
4
4
7
+ (Enter)
4
7
O.
O.
0
0
1
8.
4
9
6
3.
9
3.
3.
1
6
2
2
2
4
4
O.
2.
4.
6.
6.
3
3
3
7.
3.
7.
7.
8
0
8.
2
o.
0
1
8
2.
O.
0
1
8
x
=
3
1
+
Result
c)
(246 - 37.8) x 4.5
9
1
1.
5
= 104.1
2
4
6
+ (Enter)
3
7
8
-
2
4.
4.
4.
5
9
3
6.
9
1
0
4.
4
5
x
9.
9
Result
10·52
1
sample calculations (con't)
CALCULATION
d) 266475 x 8624
187.9
KEY
PROCEDURE
DISPLAY
-
8
7
= 12230337.
Assume first number from previous
result
6
5
4
3
2
1
2
6
6
4
7
8
5.
8.
6.
2.
8
6
4
Note that decimal point capacity of
display has been exceeded, but is
stored in memory.
x
2
2
9
8
6
0
8
0
4
1
1
1
8
1
8
8
7.
8.
7.
7.
9
0
3
3
7.
4.
1.
1
8
7
9
Result
8
8
6
2
2
1
2
2
3
Decimal point appears
10·53
Complex Standards
MM5736 MOS/LSI 6 digit calculator
features
general description
The MM5736 employs three working registers
to provide add, subtract, multiply and divide
functions. It includes on-chip key debounce and
interfaces directly with the keyboard matrix as
shown in, Figure 2 and 3. A one-of-six output
provides the strobe signals necessary to enable the
appropriate digit for display; segment data for each
digit appears during the appropriate strobe. See
Figure 1 for digit and segment timing. Leading
zero blanking has been incorporated to conserve
battery life. Average battery life is estimated to be
between 10 and 20 hours depending upon battery
quality, operating schedule and the average number
of digits displayed.
• Six digit display
•
Four functions (+, -, X, +)
• Chain operations
• Auto summing, convenient counting by any
radix, and auto squaring
•
Floating negative sign indicator for true credit
balance
• Three different error indications
• Leading zero blanking
• On-chip oscillator uses no external components
With the addition of a single-pole slide switch, a
decimal point may be lit at an appropriate digit
in the display; e.g., the third digit will present a
dollars and cents format for users who generally use
the calculator to balance checkbooks or keep track
of supermarket expenditures. (Figures 2 and 3
indicate this feature using the NSN66A LED
display, which has a decimal point between the
second and third digits.)
• Effective keyboard bounce protection
•
Interfaces with keyboard directly
• 9.0V battery operation with a typical power
dissipation less than 30 mW-resulting in a
battery life in excess of 15 operating hours with
normal use
connection diagram
Dual-In-Line Package
I
DIGIT4-
(
18
roVOD
.!
r-17 DlGIT2
K,-
r!! DIGIT J
DIGIT I
KEYBOARD
SCAN
INPUTS
U
,
r!!
4
K,-'
5
K2 -
DIGIT 5
r-I. Dl G1T6
..!
~SEGMENTe
SEGMENTI2
f1!. SEGMENT,
SEGMENT,
SEGMENT,
~SEGMENTd
SEGMENT
~vss·
..!
b..!
TOP VIEW
*V ss always most positive supply.
Order Number MM5736N
See Package 16
10-54
absolute maximum ratings
Operating Temperature
Storage Temperature
Voltage on Any Pin Relative to Vss
Lead Temperature (Soldering, 10 seconds)
oOe to + 70°C Ambient
-55°C to +150o e Ambient
+0.3V to -12V
300°C
dc electrical characteristics
Vss - 6.5V
~
VDD
~
Vss - 9.5V (Vss is always the most positive potential)
PARAMETER
Supply Current
Keyboard Scan Input Levels
(Kl, K2, K3)
Logical High Level
Logical Low Level
CONDITIONS
MIN
Voo '" Vss ~ 9.5V,
TA = 25°C
Vss
~
TYP
MAX
3.7
6.0
2.5
Voo "" Vss - 6,5V
Voo = Vss - 9.5V
Vss - 5.0
Vss - 6.0
UNITS
rnA
V
V
V
Digit Buffer Output Levels
(01 Through 06)
Logical High Level
Logical Low Level
lOUT == -1.2 mA
Voo "" Vss - 6.5V
Voo
Segment Output Current
(Sa Through Sg)
Source Current
=
Vss -1.5
Voo
Voo
Vss - 9.5V
T A =25°C
V OUT '" Vss - 3.8V, Voo
V OUT = Vss - 4.2V, Voo
V OUT = Vss -7.8V, Voo
=
=
=:
Vss - o.5V
Vss - 7.25V
Vss - 9.5V
Vss
Vss - 6.0
Vss -7.0
-3.0
-7.3
-15
V
V
V
rnA
rnA
rnA
ac electrical characteristics
PARAMETER
MAX
UNITS
Word Time (Figure 1)
CONDITIONS
0.42
MIN
1.60
rns
Digit Time (Figure 1)
70
267
MS
Interdigit Blanking Time
(Figure 1)
Digit Output Transition Rise
and Fall Times
C LOAD
Keyboard Sensing Inputs
(Kl, K2, K3)
High to Low Transition
Time After Key Release
C LOAD = 100 pF
Key Bounce - Output
Stability Time
=
100pF
2.8
TYP
4.0
MS
2.0
~S
4.0
MS
7.0
11.4
ID
rns
(The time a keyboard sensing input must be continuously
higher than the minimum
logical high level to be accepted
as a key closure, or lower
than the maximum logical
low level to be accepted
as a key release.)
10-55
I-----------WORDTIME
!--INTERDIGIT BLANKING TIME
DIGITI
DIGIT TIME
OrGIl2
DIGIT
OUTPUTS
-4
DIGIT3_+_ _ _~_ _
DIGIT&
s,
SEGMENT
DESIGNATION
ACTUAL DISPLAY:
D6~---------Ol
FIGURE 1. Timing Diagram
ill
7X410n
DM15491
M~~i~:~: --~ 9.0V
'---
EDUIV.
-
DMl5491
K,
-f
S,
"
s.
,.
~
S.
VM
~
~'4
,
•
'-
'-
~
I'o-!-
~....
f'o.!-"-
j'-o2- ~
"
"
~
,"
"
"-
,
"
S.
41011
Dr
MM5736
uP
K,
DI
-~
I
Sb
02
D3
D4
D5
Dti
I
Voo
SWITCH
(OPTIONAL)
,.---
~
Sb
M
05
"
Sg
~
03
00
1
'S","
01
POWER
DM75492
'-
......
'-rFIGURE 2. Recommended Calculator Configuration with MM5736
10-56
S.
I
C
KEYBOARD
so
CI rl CI C] CI CI
UCIC/UCIC/
SWITCH
~~~~~~:--~
EQUIV
K,
if
5,
Sf
5.
Sd
&
~
~
.....
I
5.
V"
470!!
MMS736
K,
f'o.!-.....
i'o-!-.....
50
D1
D2
OJ
D4
os
Dfi
v,,
I
I
or
or
SWITCH
I
I
"
SO
r---
'I
50
Sd
5.
Sf
5,
C/ C/ C/ C/ C/ C/ ",,,.
CI CI C.l Ct. C/ C/
06
(OPTIONAL)
-
05
~
OJ
02
01
I
~.....
f'o.!-..... "-o-L..... r--o..:-.....
POWER
'"'-02-..... "-0.2-..... "-0-:-....
~.....
,
SWITCH
DM7S492
,
......
,
......
--.-
KEYBOARD
FIGURE 3. Optional Calculator Configuration with MM5736
keyboard bounce and noise
rejection characteristics
The MM5736 calculator is designed to interface
with low cost keyboards. These keyboards are
usually the least desirable from a noise and false
entry standpoint. When a key closure is sensed by
the calculator, an internal timeout is started. Any
peturbations which occur during the timeout will
reset the timer to zero so that a key is only accepted
as vaild after a noise·free time out period. Noise
that persists indefinitely will inhibit key entry.
Key releases are checked in the same manner.
Low cost conductor loaded elastomeric keyboards
often have key-pressure versus contact resistance
characteristics that can create almost continuous
noise during "teasing" or low pressure key depressions. The MM5736 keyboard scanning circuitry
can accept a series switch resistance up to 50 kn
as a valid_closure, which combined with the internal
resettable debounce timer, insures reliable key
operations under a variety of conditions and
keyboards.
range of the calculator
The MM5736 is capable of displaying six significant
positive digits and five negative digits:
-99999 ~ Display
~
+999999
The display scans from right (LSD) to left (MSD).
Digit 1 time (Figure 1) corresponds to LSD.
error conditions
The following is a list of error conditions which
are displayed by the MM5736. If any of these
conditions occur, the machine automatically locks
out all key entries except CLEAR.
(1)
(2)
(3)
(4)
Error
Display
Too many numbers entered
Negative solution too large
Positive Solution too large
Divide by 0
EXXXXX
EEXXXX
EXXXXX
EEEEEE
10-57
CD
M
"
key description
examples (con't)
~
Clear Key:
MULTIPLICATION
Lt)
~
a. Operation during number entry
Key
1. First depression functions as a clear entry
when followed by a number reentry.
C
1000
2. Second depression functions as a clear all.
+
b. Operation after function key will clear all
registers.
x
c. Power on: Two depressions are required at
power on to clear the machine.
o Through
4
C
a. First entry clears the display register and enters
the digit into the least significant digit.
b. Second through sixth entry shifts the display
register left one digit and enters the digit into
the least significant digit.
c. Seventh entry shifts the display register right
one digit and displays an E in the most signifi·
cant digit of the display register.
1000
+
3
Subtraction Key: Depression of this key will
subtract the number entered from the accumulator
and display the results. Further depressions without
number entry will result in repeated subtractions
of the entry from the accumulator.
Multiplication Key: Depression of this key will
result in a multiplication of the number entered
by the accumulator with the results being displayed.
If no entry is made, the number being displayed will
be squared.
Divide Key: Depression of this key will result
in a division of the accumulator by the number
entered, with the results being displayed.
Key
C
+
400
2
x
7
C
35323
+
10018
9595
16000
35000
+
10·58
Display
0
1500
1500
400
1100
2
2200
7
314
Key
Display
C
0
3
3
9
81
3
+
x
x
REPETITIVE ADD/SUBTRACT
(AUTO SUMMING)
Key
Display
C
0
3
3
6
9
6
+
+
+
3
BALANCING A CHECK BOOK
Key
0
1000
1000
3
333
AUTO SQUARING
3
examples
Display
CHAIN OPERATIONS
1500
Add Key: Depression of this key will add the
number entered to the accumulator and display
the results. Further depressions without number
entry will result in a repeated addition of the entry
to the accumulator.
0
1000
1000
4
4000
DIVISION
Key
9 Keys:
Display
Display
0
35323
35323
10018
25305
9595
15710
16000
- 290
35000
34710
CLEAR ENTRY
Key
Display
C
0
3
3
4
3
+
4
C
a
5
5
8
0
9
9
+
C
9
+
Complex Standards
MM5738 calculator
general description
The MM5738 calculator was designed with "low
system cost" as a major criterion. Through advanced design techniques National Semiconductor
has been able to incorporate many desirable features
into the MM5738 and still offer significant overall cost effectiveness, probably best emphasized
by evaluating the additional components required
to fabricate a competitors complete hand-held
calculator.
The READY pin from the MM5738 is an output
signal used to indicate when the calculator is
performing an operation. This signal may be help·
ful if the device is used in a system other than a
calculator or for optimizing testing. It is possible
to defeat the key debounce circuit for faster key
entries.
Other than a single DM8864 digit driver, there are
NO external components necessary to interface
the MM5738 to the LED display, keyboard and
9.0V battery of a finished calculator. Figure 1
shows the keyboard matrix and interconnections
of these elements.
• Full 8·digit capacity
• 5·functions (+, -, x,
The MM5738 uses the familiar algebraic notation
performing addition, subtraction, multiplication
division and percentage operations on positive or
negative eight digit, floating point numbers_ It
is capable of doing chain or constant problems
while retaining another number in an independent
memory register. The contents of the memory
register are only altered upon the depression of
the Memory Store key and are unaffected by any
clear or recall memory operations.
The MM5738 provides an on-chip key debounce
circuit that interfaces directly with the appropriate
keyboard matrix (Figure 1). While a digit driver is
required, the MM5738 can drive the segments of
most common cathode LED displays directly. The
one-of-nine digit outputs provide the strobe signals
necessary to enable the proper digit for display;
segment data for each digit appears during the
appropriate strobe (Figure 2)_ The ninth 'digit is
used as a sign or error indicator, and in conjunction
with the DM8864 digit driver, as a low voltage
indicator. (The decimal point of the ninth digit
is usually used as the low voltage indication
alerting the user to the need for battery replace·
ment in the near future, without interfering with
his normal use of the calculator.) The negative sign
always resides one position to the left of the most
significant digit of negative numbers and therefore
only appears in the ninth position when an eight
digit negative number is being displayed.
Leading zero blanking and a display turnoff circuit
have been incorporated into the MM5738 to con·
serve battery life. Battery life is estimated to be
between 10 and 15 hours, depending upon battery
quality, operating schedule and the average number
of digits displayed.
features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
7, %)
Chain operations
2-key memory
Constant operations independent of memory
Auto squaring
Percent discount and tax operations
Floating decimal point for ease of operation
Floating negative sign indicator. Tracks most
significant digit.
Convenient algebraic key entry notation
Leading zero blanking
On·chip oscillator uses no external components
Display turnoff (after 16 seconds) with no
external components
Requires only a digit driver to interface with
an LED display
Key debounce uses no external components
Direct 9.0V battery compatibility
connection diagram
Dual-In-Line Package
READY..!..
fl!.OIGIT4
OIGIT9.2...
~OIGIT5
OIGIT'.2..
~DIGIT6
DIGIT2..!..
~OLGIT1
01GIT1.!.
~DIGIT8
iJ.!. KE Y INPUT 1 ~ Kli
J2! KEY INPUT2 (K21
voo2.
SEGMENTd.2.
SEGMENTg..!.
~KEYINPUT1(Kl)
SEGMENTb2.
~SEGMENTe
SEGMENTf.!.2.
~SEGMENTa
DEC1MALPT.!!.
¢SEGMENTc
v..2.!.
t-£.OISPLAYAESET
TOP VIEW
Order Number MM5738N
See Package 18
10-59
absolute maximum ratings
operating voltage range
Voltage at Any Pin Relative to Vss
(All other pins connected to Vss)
+0.3V to -12.0V
Ambient Operating Temperature
aOc to +70°C
Ambient Storage Temperature
-55°C to +150°C
Lead Temperature (Soldering, 10 seconds)
300°C
6.5V ::; Vss - Voo ::; 9.5V
dc electrical cha racteristics
Keyboard Scan Input Levels
(K1 through K3)
Logical High Level
Logical Low Level
(Tentative)
CONDITIONS
PARAMETER
Operating Supply Current (1001
(Vss always defined as most positive supply voltage)
MIN
TYP
Voo ~ Vss - 9.5V
TA "25°C
MAX
UNITS
10.5
rnA
V ss -2.5
Vss-u·O
V
V
V
Voo = Vss - 6.5V
V ss -3.5
V
Vaa "Vss - 9.5V
V ss -4.5
V
V ss -6.0
V ss -7.0
V
V
V
V ss -5.0
Vaa " Vss - 6.5V
Vaa " Vss - 9.5V
Display Reset Input Levels
V ss -l.5
Logical High Level
Logical Low Level
Digit Buffer Output Levels
(01 through 09)
Logical High Leve!
Logical Low Level
Source Current, T A = 25° C
lOUT == -1.2 mA, V DO == Vss -_6.5V
Voo == Vss - 6.5V
Voo = Vss - 9.5V
V OUT == Vss - 3.6V,
Voo == Vss - 6.5V
V
Vss -l.5
-5.0
V OUT = Vss - 5.0V,
rnA
-10
Vaa " Vss - S.OV
V OUT = Vss -6.5V,
V DD Vss - 9.5V
'-15
=0
ac electrical characte ristics
rnA
rnA
(Tentative)
MAl<
UNITS
Word Time (Figure 2)
0.64
2.4
rns
Digit Time (Figure 2)
70
267
ilS
CONDITIONS
PARAMETER
MIN
Interdigit Blanking Time (Figure 2)
Digit Output Transition Times
Rise
Fall
Keyboard Scan Inputs High to
Low Transition Time After Key
Release
100 pF
100 pF
2.0
5.0
ils
ils
C LOAD
'"
100 pF
4.0
ilS
'"
Display Cutoff Time
(The Time After the Last Valid
Key Closure at Which the 7
Most-Significant Bits Wilt
be Blanked.)
9.0
Calculation Time (Worse Case
0.093
10·60
ilS
=
4.5
99999999.1
4.0
CLOAD
CLOAD
Key Bounce-out Stability Time
(The Time a Keyboard Scan
Input Must be Continuously
Higher than the Minimum Logical
High Level to be Accepted as a
Key Closure, or Lower than the
Maximum Logical Low Level to
be Accepted as a Key Release.)
For: 99999999'" 1 "
TYP
16
17
ms
37
seconds
0.35
seconds
s::
s::CJ1
.....
MAllORY
MNt61l40R
EOUIV
.
II
1J
K1V",
~:
K2
~K301
~
{OPTIDNA.Lil
~
~
~
f"o2-
~
~
"u.!-
~
~
~
~
~
"'. " '.
'"
.
02
03
5
"'
,
.
" '. '",
S"
D5
n
""''''':~
o
D.
08
D'
12
"
2D
I'
09
.
--=-
ND
V
O~
~
J
r----
"-
POWER
~"-
D
~
.~
~ ~
'-o-!..
SWITCH
OM8864
~
....
D
C
-.0 00
DISPLAY
FIGURE 1. MM5738 Calculator with Low Voltage Indicator and Display
-------1
1
I
D9
I
•
-+______~------;_----~----------------~--~------~----~
i~_+-~rL-.-J
SEGMENTS~
S,
I
I
I
1
i
I
I
I
I
'.
I
s,
I
LJ
I
ACTUAL
DISPLAY
I
i
I
I
O/CCLI::;::; I
CI 1C1_1
I
I
I
I _1.'-
I
~
l-r
I
SEGMENT
DESIGNATION
I
Sa
I
I
~
I
s./:::/8.:
..
St
St.
FIGURE 2. Display Timing Diagram
10-61
BOUNCE AND NOISE REJECTION
B. Operation after a function key wi II clear all
registers except the memory register.
The MM5738 calculator can successfully interface
with low cost keyboards. These keyboards are
usually the least desirable from a noise and false
entry standpoint. When a key closure is sensed
by the calculator, an internal timeout is started.
Any voltage perturbations of significant magnitude
which occur on the Key Input Lines (Kl, K2 or
K3) during the timeout will reset the timer to
zero. A key is only accepted as val id after a noisefree timeout period; noise that persists indefinitely
will inhibit key entry. Key releases are checked in
the same manner.
C. Operation following Power On: Two depressions
are required.
Low cost conductor loaded elastomeric keyboards
often have a key-pressure versus contact resistance
characteristic that can generate continuous noise
during "teasing" or low pressure key depressions.
The MM5738 defines a series switch resistance up
to 50 kn to be a valid key closure which combined
with the resettable debounce timer insures reliable
operation under a variety of such conditions.
DISPLAY TURNOFF
The MM5738 has an internal timer which will
turn off the seven most significant LEOs when
no key cI osures have been made for a peri ad of
sixteen seconds. The previous display will reappear
when the DISPLA Y RESET pin is momentarily
connected to V ss. Any other key depressed after a
display turnoff reactivates the display, modifying
it appropriately. This circuit requires no external
components, other than a DISPLA Y RESET switch
(which could be physically part of the keyboard).
The option can be disabled by hardwiring the DISPLA Y RESET pin to Vss.
II. Display Key (Momentarily connecting Vss to
DISPLA Y RESET pin.)
A. Depressed before display turn-off wi II reset the
internal timer, and extend the time before
turn-off occurs.
B. Depressed after display turn-off will reset the
internal timer and return the display without
altering the information.
C. Any key depression will also reset the internal
timer and activate an updated display.
III. Number Entries
A. First Entry clears the display register and enters
the number into the LSD of the register.
B. Second through eighth Entry shifts the display
register left one digit and enters the number
into the LSD of the register.
C. Subsequent Entries are ignored. Also, only
seven positions are allowed to follow the
decimal point. Therefore, the eighth number
entry after a decimal point would be ignored.
IV. Decimal Point Key
A. First depression of this key will enter a decimal
point in the least significant position of the
display register. If there have not been previous
number entries, the display will show a zero
and a decimal point in the LSD.
B. Subsequent depressions of this key before a
function key entry will be ignored.
V. Percent Key
ERROR CONDITIONS
In the event of an overflow, the MM5738 will
display an E and at least the seven most significant
digits of the answer, except in the case of division
by O.
An E will also appear if the action of the percent
key results in underflow of the decimal point.
Once in an error condition, all keys except the
CLEAR key are ignored. The contents of the
memory register are never altered by an error
condition or the subsequent clear operation.
Each depression of this key will shift the decimal
point two places to the left. If the display has no
decimal point, one is inserted in the second
position. If shifting results in loss of the decimal
point, an E will appear in the ninth LED and the
machine will lock out further entries until CLEAR
is depressed.
A. Depression after a function key will perform the
operation described above on the result being
displayed and the machine will go to the
number entry mode.
B. Depression while in the number entry mode
will perform the operation described above.
KEY OPERATIONS
I. Clear Key
A. Operation during number entry (acts as a clear
entry key).
VI. Memory Store Key
Depression of this key will store the display
register information in the memory register. The
memory will only retain magnitude information;
i.e., it does not store sign data.
1. First depression clears the entry and displays
a previous result.
2. Second depression clears all registers except
memory register and displays a zero without
decimal point in the least significant digit
(LSD).
10-62
VII. Memory Recall Key
Depression of this key will recall the number
stored in the memory register and insert it into the
display register just as if it had been keyed in as
an entry.
VIII. Add Key
1. Indicate the end of the entry.
A. Depression of this key after an equal key will
re-enter the results from the equal operation
and record the fact that an addition is the
next function to be executed.
2. Perform the previously recorded function.
3. Record the fact that an equal key has been
depressed.
B. Depression of this key after the add, subtract
B. Depression of this key while in the number
or divide key, without an interceding number
entry, will be ignored.
entry mode will:
1. I ndicate the end of the entry.
C. Depression of this key after a multiplication
key, without an interceding number entry, will
result in an auto squaring of the number being
displayed. Subsequent equal key depressions
will continue to auto square.
2. Perform the previously recorded function,
if any.
3. Record the fact that an addition is the next
function to be executed.
C. Depression of this key after the subtraction,
multiplication, division or an earlier add key,
without an interceding number entry, will
record the fact that an addition is next function
to be executed.
XIII. Constant Key
The number entry following each multiplication
or division key is automatically stored in a constant register. (This register is not the memory
register.)
IX. Subtraction Key
Same action as the add key except that subtract
will be recorded instead of addition.
A. Depression of the constant key while in the
multiplication mode will result in multiplying
the display by the constant register. The value
of the constant remains unchanged.
X. Multiplication Key
B. Depression of the constant key while in the
division mode will result in dividing the display
by the constant register. The value of the constant remains unchanged.
Same action as the add key except that multiplication will be recorded instead of addition.
XI. Division Key
C. Multiple depressions of the constant key is a
technique for raising a number to an integer
power. The integer may be positive or negative.
See the examples.
Same action as the add key except that division
will be recorded instead of addition.
XII. Equal Key
D. Operation of the constant key in the proper
sequence is used for percent discount and tax
add on problems. See the examples.
A. Depression of this key while in the number
entry mode will:
sample problems
I.
Addition and Subtraction
A. 23.37 + 243.00 - 489.16 = -222.79
KEY
DISPLAY
COMMENTS
c
C
o
2
2
23
3
First C is clear entry.
23.
3
23.3
23.37
+
23.37
243
266.37
489.17
243
489.17
C
489.16
266.37
489.16
-222.79
Perform addition.
Wrong entry.
Clear entry; return previous total.
Floating negative indicator.
10-63
sample problems (con't)
II. Multiplication
=
A.5 x 3.14
15.7
KEY
DISPLAY
COMMENTS
c
C
a
5
5
5,
x
3.14
1 5.7
3.14
Second entry stored as constant.
B. Continue with a constant operation:
7 x 3.14 = 21.98
.003 x 3.14 = 0.00942
KEY
21.98
15
.0 a 3
15
COMMENTS
DISPLAY
0.0
0.0 a 3
a 942
{
K is a dynamic key that is decoded with the
~thers in the keyboard matrix. (Figure 11
III. Auto Squaring and Raising a Number to a Positive
Power (See V for Negative Powers)
A. 5.25 2 = 27.5625
KEY
COMMENTS
DISPLAY
c
a
C
5.25
x
5.25
5.25
27.5625
5.25 is stored as a constant.
B. 6.37 3 = 258.47485,
6.37 4
6.37 8
=
=
1646.4847 and
2710911.8
KEY
COMMENTS
DISPLAY
c
C
6.37
a
X
6.37
6.37
K
4 0.5 7 6 9
258.4 7 4 8 5
~
1 646.4 847
27 1 09 1 1.8
6.37 2
6.37 3
6.37 4
{ ""while in X mode always squares the display
and also stores a new constant.
IV. Division
A. .4 '" .3
=
1.3333333
KEY
DISPLAY
COMMENTS
c
C
.4
a
0.4
0.4
.3
10·64
0.3
1.3333333
Second entry stored as constant.
sample problems (con't)
B. Continue, with constant calculations:
.0005 "'" .3 " 0.0016666
3"," .3 " 10.
KEY
0.0005
.0005
15
3
K
COMMENTS
DISPLAY
0.0001 6666
3
10.
V. Raising a Number to a Negative Power
A. 4.3176
3
"
0.0124243
KEY
c
c
4.3176
15
~
B.. 7356- 5
COMMENTS
DISPLAY
o
4.3176
Constant is stored.
0.23 1 6 1 0 1
0.0536432
0.0 1 2424 3
4.6429217
KEY
COMMENTS
DISPLAY
C
0
C
.7356
C.
.7356- 9
0.7 356
1.359434
K
1.84806 1
15
15
2.5 1 23 1 7
~
4.64291 7
3.4 1 533
15.85708 using auto square and memory
KEY
COMMENTS
DISPLAY
C
C
.7356
0
0.7356
S
0.7356
.7356- 1
X
1.359434
1.359434
1.8480608
. 7356- 2
3.4 1 53287
.7356- 4
.7356- 8
R
1 1.66447
1 1.66447
0.7 356
1 5.85708
Store to memory .
Re-enter results .
Re-enter results.
Recall memory .
.7356- 9
10-65
sample problems (con't)
VI. Chain Operations Using Memory and %
-(131/19.6) + (0.045 - 26.31) x 1001.2 x 87%
37.65
=
607.8030
DISPLAY
KEY
C
COMMENTS
a
C
131
131
131
19.6
19.6
6.683673
6.683673
S
.0 45
Store to memory .
0.0 4 5
0.0 4 5
26.31
-26.265
26.31
X
1 a a 1.2
- 2 6 2 9 6.51 8
1 a a 1.2
6.683673
- 2 6 3 a 3.2 01
37.65
- 6 9 8.6 241
R
37.65
X
87
0.87
- 6 a 7.8 a 2 9 6
87
%
Recall from memory.
% can be used with +, -,
X,
or ...;-.
VII. Evaluating an Expense Account Using Memory
Mon
Breakfast
Lunch
Dinner
Lodging
Telephone
Transportation
Totals
KEY
C
C
Wed
Thurs
Fri
1.25
1.97
1.37
2.35
8.32
21.50
1.75
3.15
1.37
2.98
13.10
3.75
29.92
86.00
4.47
10.75
8.10
149.98
6.85
21.50
1. 75
3.75
21.50
.75
37.15
32.32
.00
3.25
36.79
DISPLAY
7.25
21.50
1.97
35.62
COMMENTS
a
1.25
1.25
+
1.37
1.25
1.37
+
2.62
1.75
1.75
4.37
+
Find weekly totals:
1.37
1.37
5.74
Breakfast total.
S
5.74
Store to memory.
2.65
2.65
2.65
1.97
4.62
2.35
6.97
+
1.97
+
2.35
+
3.15
+
2.98
10·66
2.65
7.50
Tues
3.15
10.12
2.98
Total
5.74
sample problems (con't)
VII. Continued
KEY
+
R
S
DISPLAY
COMMENTS
13.1
5.74
18.84
Calculate and store,
1 8.84
New subtotal.
7.5
7.50
+
6.85
Lunch total.
7.5
6.85
14.35
8.32
+
7.25
8.32
22.67
7.25
+
29.92
R
1 8.84
S
21.50
X
48.76
Calculate and store.
48.76
New subtotal.
21.50
21.50
4
4
+
86.
R
48.76
S
1.75
Calculate and store.
134.76
New subtotal.
1.7 5
+
1.75
0.75
+
1.97
1.97
S
3.75
Lodging total.
134.76
0.75
+
R
Dinner total.
2.5
4.4 7
Phone total.
1 34.76
139.23
Calculate and store,
139.23
New subtotal.
3.75
3.75
3.25
3.25
+
3.75
3.75
+
R
7.
1 0.75
Cab total.
139.23
149.98
Calculate total.
The same technique is used to find the daily subtotals and the double-check of the accumulative total.
VIII. Evaluate a Polynomial Using Constant and Memory
Find: 3x3+2x2+3.1x-16~?,forx~5.1
KEY
COMMENTS
DISPLAY
C
C
3
o
3
3
5.1
15.3
7 8.03
397.953
Calculate 3x 3
s
397.953
Store 3x 3
2
2
X
5.1
K
'5
10·67
sample problems (con't)
VIII. Continued
KEY
DISPLAY
COMMENTS
10.2
IS
IS
52.02
+
R
Re-enter 2x2
449.973
Calculate 3x 3 + 2x2
Store 3x 3 + 2x2
S
449.973
3.1
3.1
X
3.1
~
15.81
15.81
+
R
Calculate 2x2
52.02
397.953
449.973
465.783
16
Recall 3x 3
Calculate 3.1 x
Re-enter 3.1 x
Recall 3x 3 + 2X2
Calculate 3x 3 + 2X2 + 3.1x
16
449.783
Calculate 3x 3 + 2X2 + 3.1 x - 16
IX. Evaluate a Polynomial after Factoring. (Note the Convenience of Algebraic Notation.)
Find: 23.4x 3
-
5.3x 2 + .6x - 178:?, for x: 2.7
Factoring: . [(23.4x - 5.31x + .6J x - 178: ?
KEY
DISPLAY
COMMENTS
C
C
0
23.4
23.4
X
23.4
2.76
2,76
S
2.76
64.584
5.3
5.3
X
R
+
.6
X
{ Store X to memory for further
use and to save key entry.
59.284
2.76
163,62384
0.6
164.22384
R
2.76
453.25779
178
178
275.2 5779
X, Adding and Subtracting Percentages
3.5% + 2.7% - 12.6% + 3.1%
KEY
=
-0.033
DISPLAY
COMMENTS
C
C
3.5
%
+
2.7
%
12.6
%
+
3.1
%
0
3.5
0.035
0.035
2.7
0.027
0.062
12.6
0.126
- 0.0 6 4
3.1
0.031
0.033
10-68
% key moves decimal point 2 positions to left.
sample problems (con't)
XI. Multiplication and Division Using % Key
A. Find the 5.5% tax on the following Items:
KEY
$135.63.5127.35.5189.79.
COMMENTS
DISPLAY
C
0
C
135.63
135.63
X
1 35.63
5.5
%
127.35
~
189.79
~
5.5
0.055
7,4 5 9 6 5
5.5% is stored as constant.
5.5% of $135.63
IS
$7,46.
1 2 7.3 5
7.00425
5.5% of $127.35 is $7.80.
189.79
1 0,4 3845
5.5% of $189.79 is $10,44.
8. Mark·up Problem
Find the retail price of the following items if they are to be marked-up 33% over these wholesale prices:
$89.50. $127.29. $149.95.
KEY
COMMENTS
DISPLAY
C
C
0
89.50
89.50
77
89.50
77
%
1 27.29
~
149.95
~
Items are at 77% of retail.
0.77
1 16.23376
127.29
165.31 16
149.95
1 94.7402
C. Find 5% tax on a $129.99 item and then add it on to find total cost to customer.
KEY
COMMENTS
DISPLAY
C
C
0
5
%
5
0.05
X
0.05
+
129.99
6,4 995
IS
136,4 895
129.99
On this type of problem the percentage must be entered first.
Tax is calculated, then added on.
Total cost is calculated.
D. A salesman, whose commission on a $975.37 sale is 18%, wants to know what his profit is and how much to
send to the company.
KEY
COMMENTS
DISPLAY
C
C
18
%
X
975.37
IS
0
18
0.18
0.18
975.37
1 75.5666
799.8034
On this type of problem the percentage must be entered first.
Profit is calculated then discounted.
Difference is calculated
10·69
00
(V)
:;;
sample problems (con't)
:?!
:?!
XII. Problem Using % and Memory
A color TV which is normally priced at $599.99 is marked down 20%. When purchased, the following figures are
required:
1. Amount of savings to customer.
2. Sales price
3. 6% sales tax
4. Total amount of transaction
KEY
COMMENTS
DISPLAY
C
C
0
20
20
%
0.20
X
0.20
599.99
599.99
1 19.998
Savings to customer.
1$
479.992
Sales price.
S
479.992
Store sales price.
6
10-70
Enter percentage first.
6
%
0.06
X
0.06
R
479.992
+
28.79952
1$
508.7 9 1 52
Enter percentage first.
Recall sales price.
Tax due.
Amount of transaction.
Complex Standards
MM5739 calculator
general description
features
The MM5739 employs three working registers to
provide add, subtract, multiply and divide functions_ It includes on-chip key debounce and interfaces directly with the keyboard matrix as shown
in Figure 2_ While a digit driver is required, the
MM5739 can drive the segments of most LED
displays directly. A one-of-nine output provides
the strobe signals necessary to enable the appropriate digit for display; segment data for each
digit appears during the appropriate strobe. See
Figure 1 for digit and segment timing. Leading
zero blanking and a 16 second display turnoff
circuit have been incorporated to conserve battery
life. Battery life is estimated to be between 10 and
20 hours, depending upon battery quality, operating schedule and the average number of digits
displayed.
• 9-digit display
•
4-functions (+, -, x, -0-)
• Chain operations
• Auto summing, convenient counting by any
radix, and auto squaring
•
Floating negative sign indicator for true credit
balance
•
3-different error indications
•
Leading zero blanking
• On-chip oscillator uses no external components
For the additional cost of a single pole slide switch,
a decimal point may be lit at any convenient
point in the display; i.e., zero decimal point or
two decimal point position. (Figure 2 indicates
the wiring for a decimal point in the dollars/cents
position.) This would be helpful for users who
are generally operating in an "adding machine"
mode; e.g. housewives when balancing their
checkbooks or keeping track of supermarket
expenditures.
•
Display turnoff after
external components
16 seconds with no
•
Effective keyboard bounce protection
•
Requires only a digit driver to interface with
a LED display
•
Interfaces with keyboard directly
• 9.0V battery operation with a typical power
dissipation less than 35 mW-resulting in a
battery life in excess of 15 hours with normal
use.
connection diagram
Dual-I "-Line Package
01GIT7....!..
r!!.OIGIT8
.2.
f!!.OIGIT9
DISPLAY RESET
0161T4...l
~VDD
DIG!Tl...i
rll-
DIGIT 2
KJ..l.
~DIGITJ
Kl...!.
~OIG1T5
K2...!.
~OIGIT6
-!
~SEGMENT~
SEGMENT
,...!
r!!-SEGMENT c
SEGMENT
Q.2i
HGMENT a
~SEGMENTd
rl!.V ss
SEGMENT b..ll.
TOP VIEW
Order Number MM5739N
See Package 17
10-71
absolute maximum ratings
oOe to +70o e
-55°C to +150 o e
Operating Temperature (Ambient)
Storage Temperature (Ambient)
Voltage on Any Pin Relative to Vss
(All others V ss )
Lead Temperature (Soldering, 10 seconds)
+0.3V to -12V
300°C
operating voltage range
Vss -6.5V ~ V DD ~ Vss -9.5V (V ss is always the most positive supply)
dc electrical characteristics
PARAMETER
Supply Current
CONDITIONS
MIN
Voo '" Vss -9.5V, TA = 25°C
TYP
MAX
3.7
7.5
UNITS
mA
Keyboard Scan Input Levels (Kl, K2, K3)
Vss -2.5
Logical High Level
Logical Low Level
Vss -6.5V
Vss -5.0
Voo = Vss -9,5V
Vss -6.0
Voo
=
V
V
V
Digit Buffer Output Levels (01 through D9)
Logical High Level
Logical Low Level
lOUT == -1.2 rnA
Voo = Vss -6.5V
Vss -1.5V
Vss
V ss -6.0
Vss -7.0
Voo :::: Vss -9.5V
Segment Output Current (Sa through 59)
Source Current
TA
=
V
V
V
25°C
V OUT :::: Vss -3.8V, Voo = Vss -6.5V
V OUT = Vss -4.2V, Voo = Vss -7.25V
-4.2
-7.5
-10
-20
VOUT = Vss -l.8V, Voo = Vss -9.5V
mA
mA
mA
ac electrical characteristics
MIN
TYP
MAX
UNITS
Word Time (Figure 1)
PARAMETER
0.64
1.50
2.40
ms
Digit Time (Figure 1)
70
267
MS
CONDITIONS
4.0
Interdigit Blanking Time (Figure 1)
C LOAD = 100 pF
2.0
MS
Keyboard Sensing Inputs (K1, K2, K3) High
to Low Transition Time, after Key Release
C LOAD = 100 pF
4.0
MS
Key Bounce-Out Stability Time
(The time a keyboard serving input must be
continuously higher than the minimum Logical
High Level to be accepted as a key closure, or
lower than the maximum Logical Low Level to
be accepted as a key release.)
4.5
Display Cutoff Time
9.0
10-72
MS
Digit Output Transition Times (Rise and Fall)
20
17
ms
37
seconds
,
BOUNCE AND NOISE REJECTION
reappear when the DISPLA Y RESET pin is
momentarily connected to Vss. In addition, any
key depressed after a display turnoff reactivates
the display, modifying it appropriately. This circuit
requires no external components and can be disabled by hardwiring the DISPLA Y RESET input
to Vss.
The MM5739 calculator is designed to interface
with low cost keyboards. These keyboards are
usually the least desirable from a noise and false
entry standpoint. When a key closure is sensed
by the calculator, an internal timeout is started.
Any perturbations which occur during the time·
out will reset the timer to zero. A key is only
accepted as valid after a noise·free Key Bounce·out
Stability Time as defined in the electrical charac·
teristics section. Noise that persists indefinitely
will inhibit key entry. Key releases are checked
in the same manner.
RANGE OF THE CALCULATOR
The MM5739 is capable of displaying nine significant positive digits and eight negative digits:
-99 999 999
Low cost conductor loaded elastomeric keyboards
often have a key-pressure versus contact resistance
characteristic that can generate continuous noise
during "teasing" or low pressure key depressions
when interfaced with some keyboard scanning
techniques. The MM5739 senses a series switch
resistance up to 50 krl. as a valid key closure, pro·
viding a reliable interface under these conditions.
Error
(1) Too many numbers entered
r,--------
r
-
t--ij
~
999 999 999
ERROR CONDITIONS
The MM5739 has an internal timer which will
turn off the 8 most significant digits of the display
when no key closures are made for a period of
20 seconds (typically); The previous display will
--j
Display
The following is a list of error conditions which
are displayed by the MM5739. If any of these
conditions occur the machine automatically locks
out all key entries except clear.
DISPLAY TURNOFF CIRCUIT
DIGIT
OUTPUTS
~
The display scans from right (LSD) to left (MSD).
Digit 1 time (Figure 1) corresponds to LSD.
(2) Negative solution too large
(3) Positive Solution too large
(4) Divide by 0
-------WOAOTIME
Display
EXXXXX
EEXXXX
EXXXXX
EEEEEE
r----t'1
INTERIlIGIT BLANKING TIME
DIGITTtME
r----,
I---
;-----
,--,
OJ
II
~
DO
SEGMENTS
'.
I
!----
;-----
I
~
I
~I
~
r--r
LI
s,
'.
r---i
r---J
r
s,
1-,
ACTUAL
DISPLAV;
I
'-I
5
~I
I
I
I
I
I
I
I
,
,
I
7 801
j---
j-
f.I---
,
SEGMENT
DESIGNATION
D1-'~----------------------------------------~.
FIGURE 1. Display Timing Diagram
10·73
MALLORY _ +
11M OR "':"I.OV
EQUIV.-
DPSW.
IDPTID.ALI~n
1---;:=l:=:f:K~l~va;;-.t.ss"t-t~-=..~-;s.;-i':S.to'~l"~LA~i~~ DP
I
Ii::"
::::hl ~ ?f!?f!?????....
S.
D2
OJ
"--;',"',,
D1
•
s.
..
s.
S.
1
"
J
"-".!.
~
'-o!- f'.,!..
~
~
POWER
SWITCH
ON
DM8864
~ ~
.,
'o.!... ~, ~
~
,
•
.,o
.,c
FIGURE 2a. Recommended MM5739 Calculator Schematic with Display Cutoff Feature
till
8X24011
DM8110
r---- _
MALLORY
y~DPSWtTCH
16040R
(OPTIONAL)
,~
" •
6 K1Vss
S.
..
11
14
S.
rl
L......
K3 01
~
DI ..
RESET
MMS13!1
7 "
D2
OJ
D4
O. O.
07
08
h
BBBBBBBBB
OgVnD
I
L
_
.....o
1011.....-".. ".. . s. LA:
9
+
-= ••v
EDUIV. --:
DO
-.;-J
DI
07
O.
0'
D4
03
D2
J
01 NSN69
-
~
~
"-".!., ~
~
~ j'-o.!. "-0.:.
~
~
.
......
POWER
SWITCH
~ ~
•
,•
C
KEYBOARD
--T-
FIGURE 2b. Optional Calculator Schematic (with optional fixed decimal point and display cutoff feature)
10·74
ON
s:
s:
examples (con't)
key operations
~
W
Clear Key:
a. Operation during number entry.
1. First depression functions as a clear entry.
2. Second depression functions as a clear all.
b. Operation after function key wi II clear all
registers.
c. Power On: Two depressions are required at
power on to clear the machine.
Multiplication:
o Through 9 Keys
a. First Entry clears the display register and enters
the digit into the least significant digit.
b. Second through Ninth Entry shifts tlie display
register left one digit and enters the digit into
the least significant digit.
c. Tenth Entry shifts the display register right
one digit and displays an E in the most signifi·
cant digit of the display register.
Division:
Add Key: Depression of this key will add the
number entered to the accumulator and display the
results. Further depressions without number entry
will result in a repeated addition of the entry to
the accumulator.
CD
Key
Display
4
x
0
1000
1000
4
4000
Key
Display
C
1000
+
C
1000
+
3
0
1000
1000
3
333
Chain Operations:
Key
C
1500
+
400
Subtraction Key: Depression of this key will
subtract the number entered from the accumulator
and display the result. Further depressions without
number entry will result in repeated subtractions
of the entry from the accumulator.
2
x
7
Display
0
1500
1500
400
1100
2
2200
7
314
Auto Squaring:
Multiplication Key: Depression of this key will
result in a multiplication of the number entered
by the accumulator with the results being displayed.
If no entry is made, the number being displayed
will be squared.
Divide Key: Depression of this key will result in a
division of the accumulator by the number entered,
with the results being displayed.
Key
Display
C
0
3
3
9
81
3
+
x
x
Repetitive Add/Subtract Auto Summing:
examples
Key
Display
C
3
0
3
+
+
+
3
6
9
6
3
Balancing a Checkbook:
Key
C
987635323
+
10018
9595
987616000
35000
+
Display
0
987635323
987635323
10018
987625305
9595
987615710
987616000
-290
35000
34710
Clear Entry:
Key
Display
C
o
3
3
3
4
3
+
4
C
5
5
+
C
8
9
9
+
9
o
10-75.
Complex Standards
MM5740 gO-key keyboard encoder
general description
The MM5740 MaS/LSI keyboard encoder is a
complete keyboard interface system capable of
encoding 90 single pole single throw switch closures
into a usable 9-bit code. It is organized as a bit
paired system and is capable of N key or two key
rollover. The MM5740 is fabricated with silicon
gate technology and provides for direct TTUDTL
compatibility on Data and Strobe outputs without
the use of any special interface components.
• Only one TTL level clock required
features
• Shift lock with indicator capabi lity
• N key/two key rollover (mask programmable)
•
90 key:quad mode capabil ity
• One character data storage
• Repeat function (selectable)
• Key bounce masking by single external capacitor
• TRI·STATE@ data outputs directly compatible with TTUDTL or MaS logic
• Level or pulse data strobe output
•
Function inputs directly compatible with TTU
DTL logic
• Data strobe pulse width control
block and connection diagrams
Dual-In-Line Package
m
80UNCE
MASK
"
38
ClOC~~
"
"
'L:J
B6
X6
"
Xl
::::; o-----~
lOC~IIO +-----~
:
CDNT~Ol
:
I
I
I
I
I
I
I
I
I
I
Cg~~ATOl
"
DATA STROBE OUTPUT
DATA STROBE CONTROL
KEY,BOUNCEMASK
17
VGG
18
SHIFT LOCK I/O
TOPVII:W
Order Number MM5740AAA/O,
MM5740AAB/O or MM5740XXX/O
v,. 0----+-
See Package 8
Order Number MM5740AAA/N,
MM5740AAB/N or MM5740XXX/N
See Package 20
TR I-ST ATE is a registered trademark of National Semiconductor Corp.
10-76
absolute maximum ratings
Data and Clock Input Voltages and Supply
Voltages with Respect to Vss
+ O. 3V to -20V
600 mW at T A = +25°C
-25°C to + 70°C ambient
-65°C to +160°C
300°C
Power Dissipation
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
electrical characteristics
(Note 1,5)
PARAMETER
CONDITIONS
Clock Repetition Rate
Rep. Rate = 200 kHz
Clock Pulse Width
Rep, Rate = 10 kHz
Clock Amplitude
Logic Level "0"
Logic Level "1"
MIN
MAX
UNITS
10
TYP
200
kHz
2.4
20
2.6
80
)1,
+2.4
V
V
+0.4
Clock Transition Times
Risetime
Falltime
Rep. Rate = 200 kHz
Rep. Rate = 200 kHz
100
100
Clock Input Capacitance
5.0
)1'
n,
n,
pF
Data Input Levels, Yl thru Yl0
Logic Level "0"
Logic Level "1"
Logic Level "0"
-3.0
Logic Level "'"
+0.4
Vss -1.5
+2.4
Data Strobe Control
Logic Level "0"
+3.5
+0.4
Logic Level "'"
V
V
V
V
V
V
Data Output Levels, Xl thru X9
Logic Level "0"
When Connected to Yl thru Yl0
Logic Level "'"
via Switch Matrix, (C L
= 75 pF)
Vss - 0.75
V
V
Vss -1.0
V
V
-3.0
B 1 thru 89 and Data Strobe
"a"
I = 100)1A (Note 2)
I = 1.6 mA (Note 2)
Logic Level
Logic Level "1"
Shift Lock Voltage Open
Before Closure
Shift Lock Voltage Closed
Switch Closed
Shift Lock Voltage Lockeo
After Release, (I = 1.0 rnA)
(Figure 2)
Transition Times
Data Strobe (T DS1 )
Data Strobe (T DSO)
+0.4
V
VGG - 2.0
V
Vss
Vss - 8.0
V
Cc = 100 pF, I = 1.6 mA
CC = 100 pF, I = 100)1A
2.5
1.0
)1'
)1,
CL = 100pF,1 = 1.6mA
CL = 100 pF.1 = 100)1A
2.5
1.0
)1'
)1'
Vss - 5.0
rnJII
Data Output Levels
(T DO,)
(Tooo)
Output Enable Setup Time IT OES)
Output Enable Release Time (T OER)
Repeat Input Pulse Width (T RPW)
)1'
2.5
)1'
10
0.5
m,
m,
(Note 3)
fCLOCK
= 10 kHz
200 kHz
fCLOCK =
Power Supply Current
2.5
20
IGG, Iss
Note 1: These specifications apply for VSS = +5.0
35
mA
vee ±5%, VGG = -12.0 VDC ±5%, VLL ::: GND and TA::: ODC to +70°C.
Note 2: When outputs 81 thru B9 and Data Strobe are driving TTL/DTL Vss - VLL ~ 5.25V. When driving MOS, VSS VLL'; 10.0V.
1
Note 3: Trpw min. '" 100 x f clock
Not. 4: If shift and control inputs are derived from a single pole, single throw switch closure to VSS, a 100 OHM resistor
returned to VLL (GNO) is required on these inputs.
Note 5: The following inputs have internal pull-up resistors to VSS: clock, output enable, repeat, shift, control.
10-77
0
'lilt
.....
In
description of pin functions
~
~
NAME
PIN NO.
FUNCTION
Xl·X9
4·12
These pins are chip outputs which are used to
drive the key switch matrix. When activated (at
the appropriate scan time) they are driven high.
Yl·Yl0
22·31
Pins 22·31 are the Y sense inputs which are con·
nected to the X drive lines via the key switch
matrix. They are internally precharged to a low
state and are pulled high upon switch closure.
Bl·B9
1,33·40
These are the data outputs which represent the
code for each keyswitch. They are TRI·STATE
outputs with direct TTL compatibility. When the
output enable input (Pin 15) is high, these outputs
are in the third state.
Data Strobe Output
13
The function of this pin is to indicate that valid
data ·has been entered by the keyboard and is
ready for acceptance. An active data strobe is
indicated by a high level. The data strobe may be
operated in the pulse or level mode as indicated by
the timing diagram.
Data Strobe Control
14
The basic purpose of this input is to provide
data strobe output pulse width control. When con·
nected to the data strobe output (P in 13), the
data strobe will exhibit a one bit wide pulse width.
The pulse width may be varied by interposing an
RC network between the data strobe output and
the strobe control input. For level mode of operation the data strobe control input may be ,tied to
Vss or to the data strobe output.
Output Enable
15
Repeat
16
This input serves to TRI·STATE the data output
(Bl·B9) lines. In addition, it controls the return
of the data strobe to the idle condition (low state)
which is needed in the level strobe mode of
operation.
The repeat input is designed to accept a repeat
signal via the repeat key. One data strobe will be
issued for each positive interval of the repeat
signai. Thus, if a 10Hz signal is applied to the
repeat input via the repeat switch, a 10 charact,er
per second data strobe will be issued when a data
key and the repeat key are held depressed.
Key·Bounce Mask
17
This pin is intended as a timing node to mask
switch key-bounce. The mask time interval is
generated by connecting a capacitor to this pin.
Shift
21
When this input is brought to a logic "0" (V,.,)
level, the encoder will assume the shifted char·
Control
19
A logic "0" places the encoder in the control
character mode.
Shift Lock I/O
20
acter mode.
This pin is intended to serve as an input when the
shift lock key is depressed. It places the encoder
in the shift mode. Upon release of the key, the
shift mode will be maintained and this pin will
serve as an output to drive an indicator. This function is reset by depressing the shift key.
Clock
3
A TTL compatible clock signal is applied to this
pin. A bit time is defined as the time from one
negative going transition to the succeeding negative going transition of the clock.
10·78
Vss
32
+5.0V supply
VLL
2
Ground
VGG
18
-12V supply
timing diagram
CLOCK
KEY-BOUNCE MASK TIME
~
DETECT
SWITCH
(DETERMINATED BY EXTERNAL C)
CLOSURE
CHARACTER
STORED
PULSE
STROBE
MODE
1
~~~:UTS
DATA
STROBE
_--"11"---,
-----------f
\
+0.4
T"",
DATA
STROBE
Vss -1.D
------f
TO"---j
r
LJ
I
lEVEL
STROBE
MODE
OUTPUT
ENABLE
DATA~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _(
OUTPUTS 1_..
__- - - - - - -
r-
TOER
Tooo
HIGH IMPEDANCE STATE --------~
TD01
applications information
+6V
-12V
OUTPUT
ENAILE
II WIDER DATA STROBE PULSE WIDTH
CONTROLLED BY AC
Al DATA STROBE PULSE WIOTH =
ONE CLOCK PERIOD
Pulse Data Strobe Mode
Le.el Data Strobe Mode
key bounce capacitor values
500
400
...
"
.s
~
5
:i!
50% OUTY CYCLE CLO./-'
300
200
V
::l
100
/
/
/
/
NOMINAL POWER SUPPLIES
TA = 2fioC
1.0
2.0
3.0
4.0
TIME (msl
FIGURE 1. KeV-Bounce Mask Time
10-79
application
+&V
-llV
GilD
+5V ~>-_SH
....
"T~":-O''"1·r'/O-I
&NDOR +5Y
[
.
_,,5h
I I'
+
v.- SV L - - - - - - I
I
ImA
OPEN
I
CLOSED
,
zo.
FIGURE 2. Shift Logic 1/0 Interface
repeat switch function
Lom
,-_"'_'_"'_...iSTROIE
Repeat Switch Connections
CLoC'~~~
REPEAT
INPUT
!
I
~I
_____""I-__--'
·1
Note: Both Repeat Switch and a Data Key must be depressed to enable repeat function. For N-Key Rollover, the data
outputs will represent the current valid data key (N Key Roll during Repead.
Repeat Function
typical applications
INSERTDlflDES
FDR N·KEY ROLLOVER
KEY SWITCH MATRIX
19IMAX)
SINGLE'DlE,SINGLE
~_~t-+_THROW.MOMENTARV
,-------11"".-1211
, - - - - - - - - 1 1.. ·.511
, - -_ _ _ _ _ Vu·GND
REPEAT
CLOCK
i
~.
10-80
CODE ASSIGNMENT CHART
Customer:
Date:
MATRIX
ADDRESS
y
X
{Note 3)
COMMON
B,
B2
II:!
B.
UNSHIFT
IIg
B.
B6
B7
SHIFT
B8
B.
a.
B7
SHIFT
CONTROL
CONTROL
a.
Bs
a.
B7
B8
B.
B6
B7
CHARACTER
B8
US
S
C
SC
1
2
3
4
5
6
7
B
9
10
1
2
3
4
5
6
7
B
9
10
1
2
3
4
5
6
7
8
9
10
0
0
N-Key Rollover
2 Key Rollover
Page 0'of3 (Note 1)
Note: Use 88 if parity bit is desired
Note 1: 3 code assignment charts ate required for each keyboard encoder pattern. Fill in a "1" or "0" in each output box
(B1 thru Bgl. Indicate page number.
Note 2: The matrix is 9 "X" locations by 10 "V" locations.
Note 3: Write in 10 one's, 10 two's, etc. in successive X address locations up to 9. This will fill 3 charts. The first page will have
address matrix location 1,1; 1,2: 1,3... 1,10; 2,1; 2,2 ... 2,10; 3,1, etc. up to 3,10. Page 2 has 4,1 to 6,10. Page 3 has 7,1 to 9,10.
Note 4: A contact closure at the address matrix location will cause the appropriate bit pattern to appear at the output in negative true logic. VOH = "0"; VOL = "1."
Note 5: See application note AN-80 for coding example:
10-81
AM
&t&
MM5740~MM5740~ODE ASSIGNMENT CHARTS
., ·2 ., ., .,
MATRIX
ADDRESS
COMMON
y
X
Sg
s.
,
SHIFT
CONTROL
CONTROL
CHA~ACTER
US
S
C
SC
1
2
0
0
1
0
0
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
3
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
5
5
5
1
,
1
0
0
0
0
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
1
5
0
1
0
0
0
1
1
0
1
1
1
0
1
1
0
1
1
1
0
1
2
2
2
2
1
1
0
0
0
1
1
0
0
1
1
0
0
1
,
,
0
0
1
1
0
0
3
3
3
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
,.
3
•.>
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
6
6
1
0
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
9
9
10
1
1
1
0
0
1
1
0
1
1
1
0
1
1
1
0
1
,
1
0
1
7
7
"6
9
,
"6
9
1
1
1
1
1
1
0
•
•
7
0
0
1
0
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
5
1
9
7
2
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FF
FF
FF
FF
2
2
1
0
1
1
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
CR
CR
CR
CR
2
3
,
0
0
1
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
FS
FS
FS
FS
2
1
0
1
1
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
GS
GS
GS
GS
2
5
1
1
0
1
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
VT
VT
VT
VT
2
6
0
1
1
1
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
SO
SO
SO
SO
2
7
0
0
2
•
2
9
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HT
HT
HT
HT
0
0
0
1
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
.5
.5
.5
.5
"
"
'.'
<:>
LF
LF
LF
LF
OLE
NUL
DEL
DEL
SP
SP
SP
2
10
1
0
1
1
1
0
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
3
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
3
2
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
0
0
0
0
1
0
1
0
0
0
1
1
0
0
1
0
0
0
P
3
,
@
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DEL
DEL
3
5
1
1
0
1
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
0
0
3
3
3
3
3
3
0
1
0
SP
•
0
1
1
1
1
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
7
1
1
1
1
0
0
1
0
1
1
1
0
0
0
1
0
1
1
1
0
0
,
,
•
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
P
P
OLE
OLE
9
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
SI
S1
10
0
1
0
1
1
1
1
0
0
0
1
0
1
1
1
0
0
0
1
0
1
., ·2 ., ., ., s. ., •• ., s. ., •• . s. ., ., ., ., ••
MATRIX
UNSHIFT
COMMON
ADDRESS
SHIFT
SHIFT
CONTROL
CONTROL
,
CHARACTER
,
Y
1
0
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
0
1
0
1
9
I
9
I
4
2
1
0
0
1
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
I
I
HT
HT
4
3
, ,
1
1
1
1
1
0
0
1
1
1
0
1
0
0
0
0
0
1
0
0
1
0
S1
US
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
0
1
1
0
0
0
K
VT
ESC
4
5
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
0
1
0
0
1
L
FF
FS
4
6
0
0
1
1
0
0
1
0
1
1
1
0
0
0
1
0
1
1
1
0
0
4
7
0
1
1
1
1
0
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
4
•
0
0
1
1
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
L
L
FF
FF
1
0
Os
Sg
1
US
S
I
C
<
>
SC
<
>
9
1
1
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
1
K
K
VT
VT
10
0
0
0
1
0
1
1 '0
,
0
4
0
1
0
0
1
1
0
1
0
1
0
0
5
0
1
1
0
0
1
1
0
0
0
1
0
1
1
1
0
0
0
1
0
1
1
0
1
0
0
0
1
0
1
0
1
0
0
0
1
U
•
• ,
U
NAK
•
NAK
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
Y
Y
EM
EM
5
,
,
•
0
1
0
1
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
J
J
LF
LF
5
5
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
1
H
H
.5
.5
5
6
1
0
1
1
0
0
0
1
0
1
0
1
1
0
0
0
1
1
0
0
0
M
J
CR
GS
5
7
0
1
1
1
1
0
0
1
0
1
0
1
1
0
0
0
1
1
0
0
0
N
1\
SO
RS
1
0
1
1
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
1
M
M
CR
CR
0
0
N
SO
4
1
5
5
3
•
5
1
{
0
0
0
1
1
1
0
0
0
1
0
1
0
0
0
0
0
0
0
1
N
SO
1
1
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
0
0
7
1
1
0
1
0
0
1
1
0
0
0
1
0
1
1
1
0
0
0
1
0
1
5
%
5
•
•
1
7
'"
2
0
1
0
0
0
1
0
1
1
1
0
1
1
1
0
0
0
1
0
0
0
R
R
DC'
DC'
0
0
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
1
0
0
0
T
T
DC'
DC'
4
0
1
0
0
ACK
ACK
5
7
1
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
F
F
1
1
1
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
1
G
G
BEL
.EL
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
0
0
V
V
SYN
SYN
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
CAN
• •
EM
,
9
1
0
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
10
0
0
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
0
0
Negative True Logic
B, - B7 = ASCII Code
Ba ::: Even parity (on B" 8 2 • 8 3 • 84. 8 5• 8 6 • B7, Bs)
=
{
3
•
• •
•
• •
•
89
1
10
•
•
•
1
6
I
9
5
5
Selective Repeat Bit
Note: Use Ba if parity bit is desired.
10-82
., •• ., ., ., .. ., ., ., ..
SHIFT
s.
,• ,• ,• ,•
1
X
. .. .,
UNSHIFT
STX
STX
CAN
CAN
CAN
EM
EM
,
EM
5
5
s:
s:
en
MM5740AAE, MM5740AAF CODE ASSIGNMENT CHARTS (CONTINUED)
MATRIX
COMMON
ADDRESS
Y
X
7
7
7
B,
Og
B,
B,
B,
B,
B,
, ,
, ,
0
0
0
1
0
0
0
1
1
0
0
0
,
0
0
,
0
0
0
0
0
0
0
1
0
7
0
0
7
5
0
0
3
6
7
7
1
8
0
7
7
8
8
2
8
8
8
8
8
8
8
9
9
9
9
9
9
9
9
3
7
1
8
0
9
'0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
1
0
D
0
0
1
0
0
, ,
,
,
0
S
C
SC
OC2
DC'
DC2
DC2
E
E
ENG
ENG
DC3
DC3
DC3
DC3
0
,
,
0
0
EaT
EDT
0
0
0
DC'
DC'
DC'
DC'
0
0
0
C
C
E1X
ETX
,
1
0
0
1
I)
I)
1
1
0
0
0
NAK
NAK
NAK
1
0
0
1
1
0
0
0
0
,
,
NAK
0
, ,
0
0
SYN
SYN
SYN
SYN
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
0
ET8
ET8
ET.
ElO
0
1
0
0
0
1
0
1
1
1
0
0
0
,
0
0
,
0
1
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
END
0
, ,
0
0
1
I)
1
1
1
0
0
0
1
0
0
0
W
0
0
0
ACK
ACK
ACK
ACK
S
5
OC3
DC3
8EL
,
I)
1
"
3
/I
ENO
ENO
ENO
W
ETB
ETB
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
0
1
,
0
0
,
0
0
,
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
,
,
BEL
BEL
BEL
1
0
0
1
1
1
0
1
1
1
0
0
0
1
0
0
0
x
X
CAN
CAN
51
51
51
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I)
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
OLE
OLE
OLE
OLE
1
0
0
0
DC'
DC'
,
DC'
0
,
DC'
0
0
NUL
NUL
NUL
I'oJUl
a
DC'
ESC
ESC
ESC
A
SOH
SOH
SOH
SOH
SOH
SOH
2
2
SUB
SU8
1
0
0
0
1
0
,
0
0
0
0
0
0
0
0
0
0
1
0
0
0
a
0
1
0
0
0
0
0
0
,
ESC
A
0
0
0
1
0
0
,
0
0
0
STX
STX
STX
STX
0
0
0
0
ETX
ETX
ETX
ETX
0
0
0
,
,
EaT
EaT
EaT
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
0
0
,
,
, ,
,
,
0
0
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
,
51
0
0
0
0
0
,
,
,
,
0
,
0
0
0
0
0
0
0
, ,
,
,
,
,
,
, , ,
,
,
,
,
,
,
,
,
,
,
,
0
,
1
0
0
0
0
0
7
9
0
0
0
0
10
0
US
0
0
0
9
1
0
0
6
9
0
, ,
,
0
0
B,
1
0
8
0
8,
0
0
5
8,
0
0
3
8,
0
0
0
8,
0
,
,
,
0
B,
0
0
0
B,
0
5
6
B,
1
0
0
0
CHARACTER
B,
0
9
'0
1
8
0
, ,
, ,
,
,
,
,
SHIFT
CONTROL
CONTROL
B,
,
, ,
, ,
, , ,
, ,
, ,
, , ,
,
, , ,
, , ,
, ,
,
,
,
, ,
, , ,
, ,
,
,
,
,
, ,
7
0
.
SHIFT
B3
,
7
UNSHIFT
B,
1
B,
.....
~
o
0
0
0
,
0
0
0
0
0
0
,
0
0
0
0
0
0
0
0
0
0
0
,
EaT
I
I
DC1
,
Negative True Logic
81
-
B7 = ASCII Code
Bs "" Even panty (on 8 1 • 8 2 • 8 3 • 8 4 • 8 5 • 8 6 • 8 7 • Ba)
8 9 = Selective Repeat Bit
Note: Use Ba if parity bit is desired.
ASR
ASR 33
MM5740AAE IN-KEY ROLLOVER)
MM5740AAF 12-KEY ROLLOVER)
Typical Keyborad Arrangement
10-83
c
...,~
Interface Circuits
00
o
o
......
c
~
DM7800/DM8800 dual voltage translator
00
00
general description
features
The DM7800/DM8800 are dual voltage translators
designed for interfacing between conventional TTL
or DTL voltage levels and those levels associated
with high impedance junction or MOS FET-type
devices_ The design allows the user a wide latitude
in his selection of power supply voltages, thus providing custom control of the output swing_ The
translator is especially useful in analog switching;
and since low power dissipation occurs in the "off"
state, minimum system power is required_
•
o
o
31 volt (max) output swing
•
1 mW power dissipation in normal state
•
Standard 5V power supply
• Temperature range:
DM7800
DM8800
•
_55°C to +125°C
O°C to +70°C
Compatible with all MOS devices
schematic and connection diagrams
'u
"
R2
4.SK
R1
,OK
0'
Metal Can Package
.3
'6K
03
0'
D.
+-__
..
-.l.-+_OUTPU1X
OUTPUll
TOP VIEW
Order Number DM7800H
or OM8800H
See Package 24
4.SK
.....----1>__.,
typical applications
Bipolar to MOS Intarfacing
4-Channel Analog Switch
T
T
r-----~I
rlal---~...,I
I
SWITCH 1 _ - ' - - ' ' - '
MM41i1
I
ANALOG INPUT ,.
I
ANALOG IN'U12
SWITCH 2 _ - ' - L . . I ' - '
OTL
D'
OTl
OR
TTl
rJ---0
~MOSSHIFT
REGISTER
DM780D
I
INPUT~~
LEVELS~
TTL
INPUT
LEVELS
SWITCH 3--1-1-1-"
ANALOG IN'U13
SWITCH 4_-1-1-1-"
ANALOG IN'U14
3-
-=
-
-
r
II
.J I
-22V
LI---T~
-=
-tOY
A'ALOG OUTPUT
L _____ --l
"An.lol signals within the ranUI of +8.DV to -B.DV.
11-1
o
o
CO
CO
::E
absolute maximum ratings
"-
Vee Supply Voltage
7.0V
V 2 Supply Voltage
-30V
V3 Supply Voltage
+30V
40V
V 3·V 2 Voltage Differential
Input Voltage
5.5V
_65°C to +150°C
Storage Temperature Range
Operating Temperature Range
_55°C to +125°C
DM7S00
O°C to 70°C
DMSSOO
Lead Temperature (Soldering, 10 sec)
3OQ°C
o
o
o
CO
.....
::E
o
electrical characteristics
PARAMETER
(Note 1)
CONDITIONS
MIN
TYP
(Note 4)
MAX
UNITS
Logical "I" I nput Voltage
DM7S00
DMSSOO
Vee = 4.5V
Vee - 4.75V
Logical "0" Input Voltage
DM7S00
DMSSOO
Vee = 4.5V
Vee - 4.75V
Logical "I" Input Current
DM7S00
DMSSOO
Vee = 5.5V
Vee - 5.25V
VIN = 2.4V
5
I/-A
Logical "I" Input Current
DM7S00
DMSSOO
Vee= 5.5V
Vee = 5.25V
VIN = 5.5V
1
rnA
Logical "0" I nput Current
DM7S00
DMSSOO
Vee = 5.5V
Vee - 5.25V
VIN = 0.4V
-0.4
rnA
Output Leakage Current (Note 2)
DM7S00
DMSSOO
Vee= 5.5V
Vee - 5.25V
VIN = O.SV (Note 5)
10
I/-A
20.0
kn
V 2 + 2.0
V
Output Collector Resistor
2.0
V
O.S
TA = 25°C
-0.2
11.5
16.0
V
Logical "0" Output Voltage
DM7S00
DMSSOO
Vee = 4.5V
Vee - 4.75V
VIN = 2.0V (Note 5)
Power Supply Current
Logical "0" (Note 3)
(Each Gate)
DM7S00
DMS800
Vee = 5.5V
Vee - 5.25V
VIN = 4.5V
0.S5
1.6
rnA
Power Supply Current
Logical "I" (Note 3)
(Each Gate)
DM7S00
DMSSOO
Vee = 5.5V
Vee - 5.25V
VIN = OV
0.22
0.41
rnA
Transition Time to Logical "0" Output
TA = 25°C
C = 15 pF (Note 6)
25
70
125
ns
Transition Time to Logical "I" Output
T A =25°C
C = 15 pF (Note 7)
25
62
125
ns
Note 1: MinImax limits apply across the guaranteed temperature range of -SSoC to +12SoC for the DM7800 and ODC to +7rf'C
for the DM8800 unless otherwise specified.
Note 2: Current measured is drawn from V3 supply.
Note 3: Current measured is drawn from Vee supply.
Nota 4: All typical values are measured at TA = 25°e with Vee = 5.0V, V2 " -22V, V3
Nota 5: Specification applies for all allowable values of V2 and V3.
Note 6: Measured from 1.SV on input to 50% level on output.
Note 7: Measured from 1.5V on input to logic "0" voltage, plus 1V.
11·2
= +8V.
c
3:
......
00
o
o
theory of operation
........
c
3:
The two input diodes perform the AND function
on TTL or DTL input voltage levels. When at least
one input voltage is a logical "0", current from Vee
(nominally 5.0VI passes through R, and out the
input(sl which is at the low voltage. Other than
small leakage currents, this current drawn from Vee
through the 20 k~2 resistor is the only source of
power dissipation in the logical" 1" output state.
When both inputs are at logical "1" levels, current
passes through R, and diverts to transistor 0" turn·
ing it on and thus pulling current through R 2 . Cur·
rent is then supplied to the PNP transistor, 02. The
voltage losses caused by current through 0" D3 ,
and 02 necessitate that node P reach a voltage suf·
ficient to overcome these losses before current be·
gins to flow. To achieve this voltage at node P, the
inputs must be raised to a voltage level which is one
diode potential lower than node P. Since these levels
are exactly the same as those experienced with conventional TT Land DT L, the interfacing with these
types of circuits is achieved.
Transistor 0, provides "constant current switch·
ing" to the output due to the common base connection of 0,. When at least one input is at the
logical "0" level, no current is delivered to 02: so
that its collector supplies essentially zero current
to the output stage. But when both inputs are raised
to a logical "1" level current is supplied to 02.
00
00
Since this current is relatively constant, the collector of 02 acts as a constant current source for the
output stage. Logic inversion is performed since
logical" 1" input voltages cause current to be sup·
plied to 02 and to 03. And when 0 3 turns on the
output voltage drops to the logical "0" level.
o
o
°
The reason for the PNP current source, 2 , is so
that the output stage can be driven from a high
impedance. This allows voltage V 2 to be adjusted
in accordance with the application. Negative volt·
ages to -25V can be applied to V 2. Since the out·
put will neither source nor sink large amounts of
current, the output voltage range is almost exclusively dependent upon the values selected for V 2
and V 3 .
Maximum leakage current through the output transistor 0 3 is specified at 10 I1A under worst-case
voltage between V, and V 3 . This will result in a
logical "1" output voltage which is 0.2V below V 3 .
Likewise the clamping action of diodes D 4, D s, and
D6 , prevents the logical "0" output voltage from
falling lower than 2V above V" thus establishing
the output voltage swing at typically 2 volts less
than the voltage separation between V 2 and V 3.
selecting power supply voltage
The graph shows the boundary conditions which
must be used for proper operation of the unit. The
range of operation for power supply V 2 is shown
on the X axis. It must be between -25V and -BV.
The allowable range for power supply V 3 is governed by supply V 2. With a value chosen for V 2, V 3
ma", be selected as any value along a vertical line
passing through the V 2 value and terminated by
the boundaries of the operating region. A voltage
difference between power supplies of at least 5V
should be maintained for adequate signal swing.
~.'
OPERATING
25
"
"
,
10
0
V,
17~
REGION
-,
-10
-15
-20
-25
11-3
co
o
00
00
Interface Circuits
~
o
........
CO
o
~
~
OM7802/0M8802. DM7806/DM8806
high speed MOS to TTL level converters
o
N
o
00
00
~
o
........
N
o
00
.....
~
o
general description
features
The DM7802/DM8802, DM7806/DM8806 are high
speed MOS to TTL level converters. These circuits
act as an interface level converter between MOS
and TTL logic devices. It consists of two 1·input
converters with common strobe input to inhibit
"0" entry when strobe is high. It allows parallel
entry when strobe is low and the internal latch
is preset by the common preset input. TRISTATE@ output logic is implemented in this
circuit to facilitate high speed time sharing of
decoder-drivers, fast random-access (or sequential)
memory arrays, etc.
• Very low output impedance ability
• High impedance output state which allows
many outputs to be connected to a common
bus line
• Average power dissipation 110 mW per converter
logic and connection diagrams
'N,
lCURRENT INPUTI
ourpUTA
IN,
(CURRENTINPUTj
OUTPUT B
sfFioBE
PRESET
Dual-In-Line Package
"
mmr
15
Ne
14
OUTPUT A
13
PRESET
11
Ne
11
GNO
"
INPUT A
Flat Package
v"
14
V"
Ne
13
OUTPUT A
OUTPUTB
11
PRESET
OUTPUTB
DISABlE
DISABLE
Ne
Ne
Ne
"
GNO
GNO
GNO
INPUTB
INPUT A
INPUTB
GNO
GNO
GNO
GNO
TOPVIEW
TOP VIEW
11-4
Order Number DM7802J, DM8802J,
DM7806J or DM8806J
Order Number DM8802N or
DM8806N
See Package 10
See Package 15
high drive
Order Number DM7806W or
DM8806W
See Package 27
c
absolute maximum ratings
MIN
Supply Voltage
7.0V
Input Voltage
5.5V
Output Voltage
5.5V
Storage Temperature Range
Supply Voltage (Veel
DM7802, DM7806
DM8802, DM8806
4.5
4.75
MAX
UNITS
5.5
5.25
V
V
N
.......
c
3:
CO
CO
Temperature (TAl
-6SoC to 150°C
Lead Temperature (Soldering, 10 seconds)
3:
.....
CO
o
operating conditions
(Note 1)
DM7802, DM7806
DM8802, DM8806
300°C
-55
0
+125
+70
°e
°e
o
N
c
electrical characteristics
3:
.....
CO
o
(Note 2)
PARAMETER
CONDITIONS
logical "1" Input Current
Vee = Min
Logical "0" Input Current
Vee = Min
Logical "1" Input Voltage
Vee
Logical "0" Input Voltage
Vee = Min
Logical "1" Output Voltage
Vee = Min,
lOUT =
-1.5 mA
lOUT =
16 mA
MIN
TYP
MAX
500
2.0
2.4
Vee = Min,
Logical "'" Input Current
Vee = Max, V 1N = 2.4V
Vee = Max. V 1N = 5.5V
40
1.0
JJ.A
rnA
-1.6
rnA
40
rnA
-1.5
V
Input Clamp Voltage
Vee = Min,
Output Short Circuit Current (Note 3)
Vee = Max, Va = OV
DM7802, DM7806
DM8802, DM8806
liN
'=
o
~
V
Vee = Max, Va = 2.4V
Vee = Max. Va = O.4V
Vee = Max, V1N(DISABLEI = 2
Other Inputs = 1JV
CO
CO
V
Logical "0" Output Voltage
Vee = Max, V iN = OAV
3:
/iA
Third State Output Current
Logical "0" I "put Current
c
V
0.8
Supply Current
.......
/iA
200
=Min
~
UNITS
-12 mA
-20
-18
0.4
V
40
-40
/iA
/iA
-70
-70
rnA
rnA
Propagation Delay to a Logical "0" From
STROBE to Output (td,1
Vee o5.0V
T A o 25°e
(See Figure 1)
17
25
ns
Propagation Delay to a Logical "1" From
Preset to Output (tdp)
Vee o5.0V
TA o 25°C
(See Figure 1)
22
32
ns
Delay From Disable Input to High Impedance
State (From Logical "1" Level)(tlH)
Vee o5.0V
(See Figure 2)
7.0
11
ns
TA = 2S OC
Delay From Disable Input to High Impedance
State (From Logical "0" Level)(toH )
Vee o5.0V
TA o 25°C
(See Figure 3)
17
25
ns
Delay From Disable Input to Logical "1"
Level (From High Impedance State)(tHl)
Vee o5.0V
(See Figure 2)
9.0
14
ns
TA = 25°C
Delay From Disable Input to Logical "0"
Level (From High Impedance State)(tHO)
Vee o5.0V
TA o 25°C
(See Figure 3)
13.5
16
ns
Note 1; "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The
table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the -55°C to +125°C temperature range for the DM7802,
DM7806 and across the oOe to +70o e range for the DM8802, DM8806. All typicals are given for Vee = 5.0V, T A = 25°C.
Note 3: Only one output at a time should be shorted.
11-5
CQ
o
CO
CO
typical performance characteristics
:E
c
........
tds vs Temperature
CQ
o
tOH vs Temperature
tdp vs Temperature
40
40
30
30
40
CO
"c
:E
N
o
WORST CASE PATH
!
WORST CASE PATH
20
J
"-
:!
.;
10
c
o
:E
N
J.
10
0
25
50
-75 -50 -25 0
75 100 125
8.0
.
/
WORST CASE PATH.......
7.0
~
6.0
~
50
75 100 125
-75 -50 -25 0
V
V
"/
16
17
14
12
r-....
14
I"--
13
12 I--I--
!
_...!ORST CASE PATH-
.r ::r:
TYr'CA , CAiE PyH
8.0
j
TYPICAL CASE PATH
6.0
-
4.0
2.0
11
5.0
-75 -50 -25 0
25
50
o
10
75 100 125
-75 -50 -25 0
TEMPERATURE rc)
25
50
TEMPERATURE
n)
0.4
!;
0
>
OJ
VOUT vs lOUT Logical "I"
4.0
+I~~
,/
......
0.2
0.1
~~p
~~~
~
~
~
55
J
~
3.0
2.0
+125
+25
-55
,
~
1.0
~
~5-55
+f5
o
20
40
60
80
-10
100
10
truth table
0
INAOR B
ST
P
0
1
0
1
1
1
1
1
1
0
0
0
0
X
1
1
X
x
20
IOUT(mA)
lOUT (mA)
11·6
0
= Don't cafe
0
0
X
25
50
75 100 125
TEMPERATURE 1°C)
5.0
0.6
~
-75 -50 -25
75 100 125
VOUT vs lOUT Logical "0"
0.7
0.5
1::::=
WORST CASE PATH
10
15
J
..... ~
..... TYPICAL CASE PATH
75 100 125
tH1 vs Temperature
18
16
!
25 50
TEMPERATURE rC)
tHO vs Temperature
t1H vs Temperature
!
25
TEMPERATURE 1°C)
9.0
c
e: ~
10 I-TYf'CA, CAiE TH I--I--
TEMPERATURE 1°C)
o
~
:E
WIRSTt~
o
-75 -50 -25
........
I--
TYPICAL CASE PATH
TYPICAL CASE PATH
CO
CO
I:.--'
20
30
~ :/
OAOR Os
1
1
0
1
Hi·Z
30
40
50
o
3!:
.....
ac load circuit
00
o
N
"'-
o
3!:
00
00
SWITCH S.
SWITCH 52
Cl
'dP
'd.
Closed
Closed
50 pF
Closed
Closed
50 pF
'OH
Closed
Closed
'5 pF
DM11116!
DM8806
o
N
o
3!:
.....
00
"H
Closed
Closed
'5pF
'HO
Closed
Open
50 pF
o
'H.
Open
Closed
50pF
"'-
0)
o
3!:
* Jig capacitance
00
00
o0)
switching time waveforms
'OH
r-------INPUT
0'
I
I
I
I
---.JtOH
I
l-4-
I
I
-'nI
ACTUAL
~~~~~AGLE"O"
l.GV
__
OU_"_U1_ _
--
_ - - - - "'1.5V
t
INPUT
'---------ov
~
....
OUTPUT
-
__________ .v
: r------I
I
I
1.5V
11-7
CD
o
ex)
ex)
ac test circuits and switching time waveforms
:E
"of
q
Q
.......
CD
o
INPUTA,B
PULS£ GEN. NO. l
jCURR£NTI
~
:E
+S.OV
......
PUlSEGEN.NO.2
Q
OUT
DM7ID6!
PRESET
DM8106
PUU£GEN.NO.1
N
o
"
f= 1.0MHz
1,.=1,<5.00$
Ro =51 f(lrPG 1 &2
tpw "'tsw "'20 "sMax
ts=20nsMaK
ex)
ex)
:E
Q
"
DISABLE
.......
N
o
~
:E
+l~A-------\---------1
Q
~.-------I
'---,---,----'
"ff----
:::~-,,'
----I'"'.
+UV
_ _ _ _ _ _ _ _ _•
<-I4V-
IV
FIGURE 1. DM7802/DM8802, DM7806/DM8806 AC Test
+5.0V
+3.0V
o-----c>-\
OPEN
0-----<>-1
DISABLE
"
t,=t f <5.0ns
OUT
OM7806f
DM8806
PRESET
Ro =51
tow = 200 IlS Max
3.GV
+5.UV
rNPU1A,B
OPEN
0-----<>-1
DISABLE
OUT
DM7806{
"
t,=t,<5.0115
Ro =51
tow =20Dn~Max
DM8806
":"
FIGURE 3. (For tOH, tHoI
11-8
~s
o
3:
....
...o
I nterface Circuits
CD
......
DM7810/DM8810 quad 2-input TTL-MOS interface gate
DM7811/DM8811 quad 2-input TTL-MOS interface gate
DM7812/DM8812 TTL-MOS hex inverter
general description
o
3:
CD
CD
...o
In addition the devices may be used in applications
where it is desirable to drive low current relays or
lamps that require up to 14 volts.
These Series 54/74 compatible gates are high output voltage versions of the DM5401/DM7401
(SN5401/SN7401), DM5403/DM7403
(SN5403/SN7403), and DM5405/DM7405
(SN5405/SN7405). Their open·collector outputs
may be "pulled·up" to +14 volts in the logical "1"
state thus providing guaranteed interface between
TTL and MOS logic levels.
o
....3:
...
CD
......
o
3:
CD
CD
......
schematic and connection diagrams
,-----"'----0 v"
4K
------O v"
r - - - -....
3:
....
...
CD
N
OUTPUT
INPUT
INPUTS
o
1.&K
OUTPUT
0-::-1-......
......
o
3:
1K
DM7810/DM8810, DM7811/DM8811
DM7812/DM8812
Dual-tn-Line Package
Dual-In-Line and Flat Package
G.D
TOP VIEW
CD
CD
N
...
L-_ _ _...._--oG.D
'---_-oOND
lOPVIEW
Drder Number DM7810J or DM8810J
See Package 9
Order Number DM7811J or DM8811J
See Package 9
Order Number DM7810N or DM8810N
Order Number DM7811N or DM8811N
See Package 14
See Package 14
Order Number DM7811W or DM8811W
See Package 27
Dual-I n-Line and Flat Package
"
13
"
11
1D
Order Number DM7812J or DM8812J
See Package 9
Order Number DM7812N or DM8812N
See Package 14
Order Number DM7812W or DM8812W
See Package 27
TOP VIEW
G.D
11·9
...
N
00
00,
~
C
absolute maximum ratings
operating conditions
7V
5.5V
Output Voltage
14V
Storage Temperature Range
_65°e to +150o e
Lead Temperature (Soldering, 10 seconds)
3000 e
Supply Voltage (Vee)
DM78XX
DM88XX
Temperature (TA)
DM78XX
DM88XX
.......
...
N
00
....
~
C
...
Vee
I nput Voltage
MIN
MAX
UNITS
4.75
4.75
5.25
5.25
V
V
-55
0
+125
70
°e
°e
00
00
~
C
.......
...
electrical characteristics
~
PARAMETER
(Note 1)
MIN
CONDITIONS
TYP
MAX
UNITS
~
C
Input Diode Clamp Voltage
...
Vee = 5.0V, T A = 25°c
liN =-12mA
Logical "1" Input Voltage
Vee = Min
Logical "0" Input Voltage
Vee = Min
Logical" 1" Output Current
Vee = Min
V OUT = 10V
Logical "1" Output Breakdown
Voltage
Vee = Min, V ,N = OV
lOUT = 1 mA
Logical "0" Output Voltage
Vee = Min, V ,N = 2.0V
lOUT = 16 mA
Logical" I" I nput Current
Vee = Max, V ,N = 2.4V
40
Logical "I" Input Current
Vee = Max, V ,N = 5.5V
1
mA
Vee = Max, V ,N = O.4V
-1.6
mA
o
00
00
~
C
.......
...
o
~
~
C
Logical
"a"
Input Current
-1.5
V
V
2.0
0.8
V ,N = 0.8V
V ,N = O.OV
250
40
V
IlA
/lA
14
V
0.4
V
/lA
Supply Current - Logical "0"
(Each Gate)
Supply Current - Logical "1"
(Each Gate)
Propagation Delay Time to a
Logical "0", tpdQ
Vee = 5.0V, T A = 25°C
COUT = 15 pF, RL = lk
4
12
18
ns
Propagation Delay Time to a
Logical "I", tpdl
Vee = 5.0V, T A = 25°C
COUT = 15 pF, RL = lk
18
29
45
ns
Vee = Max, V ,N = 5.0V
3.0
5.1
mA
Vee = Max, V ,N = OV
1.0
1.8
mA
Note 1: Unless otherwise specified minImax limits apply across the _55°C to +125°C temperature range for the DM78XX and
across the O°C to 700 e range for the DM88XX. All typicals are given for Vee = 5.0V and TA = 25°C.
typical applications
+10V
3K
+12V
I.
7.SK
GROUND
L...Jo--....--!INPUT
DMlll0,OMllll,DM8812
I
CLOCK
+10V-,
1
Yo--....--lIINPUT
VDO
"*" ~ESx~:p~; ~h~~~~rster
L--6v
11·10
Note: Normal voltages applied to
MOS shift registers have been shifted
by +10V for this application.
OM8810,OM8811,DM8B12
'::
I
NSC MOS ROM
(ExampleMM521)
c
Interface Circuits
3:
00
00
...
0)
c
3:
00
00
0)
W
DM8861 MOS-to-LED 5-segment driver
DM8863 MOS-to-LED 8-digit driver
general description
features
The DM8861 and DM8863 are designed to be
used in conjunction with MOS integrated circuits
and common-cathode LED's in serially addressed
multi-digit displays.
•
Source or sink capability
per driver, DM8861
•
Sink capability per
driver, DM8863
The DM8861 is a 5-segment driver capable of
sinking or sourcing up to 50 rnA from each driver.
•
MOS compatibility (low input current)
The DM8863 is an 8-digit driver. Each driver is
capable of sinking up to 500 rnA.
50 rnA
500 rnA
•
Low standby power
•
High gain Darlington circuits
schematic and connection diagrams
OM8861
OM8863
(4,6,12,13,16)
A
(18)
TO OTHER
DRIVERS
v~
IN5
co
C5
Cl
El
IN1
(18)
TO OTHER
DRIVERS
191
TO OTHER
DRIVERS
v"
Dual~ln~Line
E5
11.4,5,7,10,12,14,16)
v"
(9I
TO OTHER
DRIVERS
v~
...
.~-(2,3,6,8,11,13,15,17)
-.-"V'oIV-.....--l
v"
Dual-In-Line Package
Package
E4
IN4
1N3
E3
C3
v~
IN.
OUT8
INJ
NC
IH2
E2
C2
Voo
Dun
IN1
IN2
DUl2
OUT7
DUT3
IN6
OUT6
IN5
OUT5
IN3
OUT4
IN4
Voo
TOP VIEW
TOP VIEW
Order Number OM8861N
See Package 16
Order Number OM8863N
See Package 16
11-11
(W)
CD
CO
CO
absolute maximum ratings
~
DM8861
.....
C
Input Voltage Range (Note 1)
Collector (Output) Voltage (Note 2)
CD
Collector (Output)-to-Input Voltage
Emitter-to-Ground Voltage (V, 2: 5V)
Emitter-to-Input Voltage
CO
CO
~
C
DM8863
-5V to Vss
10V
-5V to Vss
10V
10V
10V
5V
Voltage at Vss Terminal With Respect to
Any Other Device Terminal
Collector (Output) Current
Each Collector (Output)
All Collectors (Output)
Continuous Total Dissipation
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
lOV
10V
10V
50mA
200 mA
800 mW
O°C to +70°C
-65°C to +150°C
300°C
500mA
600 mA
800 mW
O°C to + 70°C
-65°C to +150°C
300°C
dc electrical characteristics
DM8861 (V ss
= 10V,
= O°C to
TA
+70°C unless otherwise noted)
PARAMETER
CONDITIONS
On State Collector Emitter Voltage (V CE
On State Collector Emitter Voltage (V CE
Off State Collector Current (Ie
Off Set Collector CUrrent (Ie
ON)
ON)
OFF)
OFF)
TVP
MIN
Input = B.5V through 1 kfl. VE = 5V,
MAX
.9
Ie = 50 rnA. T A = 25°C
Input = B.5V through 1 kfl, VE = 5V.
Ie = 50 rnA
!LA
!LA
2.2
3.3
Current Into Vss Terminal (Iss)
rnA
100
!LA
1
rnA
MAX
UNIT
+70°C unless otherwise noted)
PARAMETER
CONDITIONS
MIN
Low Level Output Voltage (VOL)
Y'N = 7V. lOUT = 500 rnA. T A = 25°C
Low Level Output Voltage (VOL)
VIN "" 7V, lOUT'" 500 rnA
High Level Output Current (I OH
V
100
Y'N = lOY, VE =O.le = 20 rnA
= O°C to
1.5
100
Y'N =O.VE =5V.le =0
TA
V
Ve = lOY, VE = 0, liN = 40!LA
Input Current at Maximum Input Voltage (II)
= 10V,
1.2
Ve = lOY, VE = O. Y'N = .7V
Emitter Reverse Current (Ie)
DM8863 (V SS
UNIT
1.5
V
1.6
250
)
V OH
=
lOV, liN
High Level Output Current (lOH)
VOH
=
lOV, VIN :::: .5V
Input Current at Maximum Input Voltage (II)
VIN :::: lOV, tOl == 20 rnA
=
TVP
40,uA
Current Into Vss Terminal (Iss)
V
!LA
250
!LA
2
mA
1
mA
ac switching characteristics
DM8861 (V ss
= 7.5V,
TA
= 25°C)
PARAMETER
CONDITIONS
Propagation Delay Time, Low to High Level Output (Collector) (tPLH)
V 1H '" 4.5V. VE '" 0
Propagation Delay Time, High to Low Level Output (Collector) (tPHL)
RL '" 200n. CL
DM8863 (V SS
= 7.5V,
TA
==
15 pF
TYP
MAX
UNIT
100
ns
20
ns
= 25°C)
PARAMETER
CONDITIONS
Propagation Delay Time, Low to High Level Output (t PLH )
V 1H
Propagation Delay Time, High to Low Level Output (tPHL )
CL
=
=
av, RL
=
2H2.
15pF
Note 1: The input is the only device terminal which may be negative with respect to ground.
Note 2: Voltage values are with respect to network ground terminal unless otherwise noted.
11-12
MIN
MIN
TYP
MAX
UNIT
300
ns
30
'"
o
s:
Q)
Q)
..
typical application
0')
o
s:
a-Digit Calculator With LED Display
Q)
Q)
r-------,
1_1j
27 S,
0')
to)
I
* Ia! !! ",,'
I
~ _d-~ --; -
"
"
26 RJ
25 R,
~R,
CLEAR~
J'C-
.!..
I.!..
1'-'-
MOST
,'.
NINE NSI·j.4t
SIGNIF
OIGIT{BI
,"
1
1!4'OIGITLEO
SIGNIFICANT
OIGIT(11
~-+---+OIGIT!71
I'"
I~
I-.!.
1"-
f ' - - + - - - + 0I6IT(4)
.!..
I~
P--f---+ DlGIT(3)
f!--f---+
tAlternatively lise two NSNJ3 triple 1/8" digits and one NSN133 double 1/8"
digit with separate mml.lssign, and change resistor values to 100 n.
0IGI1(2)
~"
"
11-13
M
(g
co
co
ac test circuits and waveforms
~
C
....
(g
co
co
~
C
7.5V
7.5V
~r--"'-OUTPUT
'><>-'--'-OUTPUT
GNO
DM8861
DM8863
:---
---l
1---::; 10 ns
I
:
r.=--:=,,=--,--------- v,"
I
I
I
INPUT
I
'-""'-------DV
OUTPUT
I
I
IpHL
I
I
--1---1
I
I
Note 1: The pulse generator has the following tharacteristics:
loUT" 50n, PRR" 100 kHz, tw" 1.0IlS.
Note 2: CL includes probe and jig capacitance.
11-14
c
Interface Circuits
s:
00
00
00
C1I
DM8885 MOS to high voltage cathode buffer
general discription
The DM8885 interfaces MOS calculator or counterlatch-decoder-driver circuits directly to sevensegment high-voltage gas-fi11ed displays. The six
inputs A, B, D, E, F, G are decoded to drive the
seven segments of the tube.
multiplex operation_ The output current is adjusted
by connecting a program resistor (Rp) from Vee to
the program input.
Each output constitutes a switchable, adjustable
current source which provides constant current to
the tube segment, even with high tube anode supply
tolerance or fluctuation. These current sources have
a voltage compl iance from 3V to at least 80V. Each
•
•
Current source outputs
Adjustable output currents 0.2 to 1.5 mA
•
•
•
•
•
High output breakdown voltage 80V min
Suitable for mUltiplex operation
Low fan-in and low power
Blanking via program input
Also drives overrange, polarity, decimal point
cathodes
features
current source is ratioed to the b-output current
as required for even i11umination of all segments.
Output currents may be varied over the 0.2 to
1.5 mA range for driving various tube types or
connection diagram
truth tables
Dual-tn-Line Package
A
B
D
E
F
G
DISPLAY
INPUT'
1
1
1
1
1
1
1
1
1
',
1 (OFFI
0
'-'
0
0
1
1
1
0
0
0
0
0
1
o (ON)
0
1
1
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
/
I?
3
~Positlve
L/
OUTPUT'
Logic
5
,5
-,,
EI
'3
b
,-,
-,
/"1
/-/
',
'-'
SI
C=(iHf,O+E)F
TOP VIEW
Order Number DM8885N
See Package 15
typical applications
'5V
v" o-....--t--O
____ ..J
-12V
Open-Drain MOS Output
Push-Pull MOS Output
11-15
aD
GO
GO
GO
absolute maximum ratings
~
o
7V
6V
80V
600mW
50mA
OOC to +70°C
-65°C to +150°C
300°C
Vee
Input Voltage
Segment Output Voltage
Power Dissipation (Note 1)
Transient Segment Output Current (Note 2)
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
electrical characteristics
(Note 3)
PARAMETER
CONDITIONS
Logic "1" Input Voltage
Vee = 4.75V
logic "0" Input Voltage
Vee = 4.75V
logic "1"lnput Current
Vee=> 5.25V, V IN = 2.4V
MIN
TYP
MAX
2.0
UNITS
V
0.8
2
V
15
"A
Vee'" 5.2SV, V IN = 5.5V
4
400
"A
Logic "0" Input Current
Vee = 5.25V, VIN "" D.4V
-300
-600
"A
Power Supply Current
Vee'" 5.25V. All Inputs = OV, Rp '" 2.2k
22
31
rnA
Input Diode Clamp Voltage
Vee = 5V, I.N = -12 mA, TA = 2SoC
-09
-1.5
V
Segment Outputs.
Outputs a, f, 9 On Current Ratio
All Outputs = SOV. Output b Curro '" Ref.
0.84
q.93
1.02
Output c On Current RatIO
All Outputs'" SOV, Output b CUrr.
=
Ref.
1.12
1.25
1.38
Output d On Current Ratio
All Outputs"" SOY, Output b Curro
=
Ref.
0,90
1.00
1.10
Output e On Current Ratio
All Outputs::: SOY, Output b Curr.
=
Ref.
0.99
1.10
1.21
Output b On Current
Vee
2SoC, Rp '" lB.lk
0.18
0.20
0.22
rnA
SOY, T A = 2Soc, Rp:: 7 03k
0.45
0.50
0.55
rnA
3.40k
0.90
1.00
1.10
rnA
SOY, TA = 2SoC, Rp = 2.20k
1.35
1.50
1.65
rnA
0.8
2.5
0.003
3
"A
0.003
3
~A
=
SV, VOUT b '" SOy, TA
Vee:: SV, VOUT b
Vee
=
=
=
SV, VOUT b::: SOV, TA = 2SoC, Rp
Vee = SV, VOUT b
=
Output Saturation Voltage
Vee = 4.7SV, 'ouTb:: 2 rnA. Rp
Output Leakage Current
VOUT '" 7S\}, V IN
Output Breakdown Voltage
lOUT'" 2S0 ,uA, V IN
=
=
lk ± S% (Note 4J
=
,
O.BV, Rp> lk
VOUT= 75V, VPAOG= 0.4V
=
O.BV
80
110
V
V
Propagation Delays:
Input to Segment Output
Vee:: SV, TA = 2SoC
0.4
10
"'
Note 1: Maximum junction temperature is 13(fC. For operating at elevated temperatures, the device must be derated based
on a thermal resistance of 150°CIW 8 JA.
Nota 2: In all applications transient segment output current must be limited to 50 mAo This may be accomplished in DC applications by connecting a 2.2k resistor from the anode-supply filter capacitor to the display anode, or by.current limiting the
anode driver in multiplex applications.
Nota 3: MinImax limits apply across the guaranteed operating temperature range of O°C to +70o C, unless otherwise specified.
Typicals are for Vee = 5V, TA = 25°C. Positive current is defined as current into the referenced pin.
Note 4: For saturation mode the segment output currents are externally limited and ratioed.
typical performance characteristics
11-16
(see DM7880 data sheet)
Interface Circuits
DM75491 MOS-to-LED quad segment driver
DM75492 MOS-to-LED hex digit driver
features
general description
The DM75491 and DM75492 are interface circuits
designed to be used in conjunction with MOS
integrated circuits and common-cathode LED's in
serially addressed multi-digit displays_ The number of drivers required for this time-multiplexed
system is minimized as a result of the segmentaddress-and-digit-scan method of LED drive_
• Source or sink capability
per driver (DM75491)
50 mA
• Sink capability per
driver (DM75492)
250 mA
• MOS compatability (low input current)
•
Low standby power
• High-gain Darlington circuits
schematic and connection diagrams
DM75492 (each driver!
DM75491 (each driver!
_ /_ _ _.... 11.2,8.1,9.131
(14, l,5.B.l0, 121
A -'--'VV><--4I---i
(1,7,8,14\
(1')
v~ .::(1"-"+-_ _-!---+--OU1PUT
N
;><>-'-.....-OUTPUT
J
Cl = 15pF
I'NoTE21
DM75491
CL
~
15 pF
,NOTE2)
DM75492
:____
-----I
1 _ < 1(J ns
Ii:
~;;;;;----::=.lc--,-I
------ --- v'"
I
INPUT
I
...:.::";:.%------ov
OUTPUT
i
'----+-...L-f-------
VOL
I
I
I
I
I
r-- --1
tPLH
NOTE 1: THE PULSE GENERATOR HAS THE FOLLOWING CHARACTERISTICS:
PAR = 100 KHz, tw '" lj.ls.
NOTE 2: CL INCLUDES PROBE AND JIG CAPACITANCE.
lOUT
= SOn,
11-19
N
....
...I
Interface Circuits
OCI
OCI
:E
Q
DM88l12 TTl-MOS hex inverter/interface gate
general description
levels up to +14V without resistive pull·ups at the
outputs and still providing a guaranteed logical "1"
level of Vee - 2.2V with an output current of
-200 /lA.
The DM88L 12 is a low power TTL to MOS hex
inverter element. The outputs may be "pulled up"
to +14V in the logical "1" state, thus providing
guaranteed interface between TTL. and MOS logic
levels. The gate may also be operated with Vee
schematic and connection diagrams
Dual-In-line and Flat Package
'OK
20K
'"
GN'
TOP VIEW
Order Number DM88L 12J
See Package 9
Order Number DM88L 12N
See Package 14
Note: Shown is schematic for each inverter.
Order Number DM88L 12F
See Package 26
typical applications
TTL Interface to MOS ROM
With Resistive Pull-Up
TTL Interface to MOS ROM
Without Resistive Pull-Up
+1211
+1211
NSC MOS ROM
(EXAMPLE MM521!
-1211
ac test circuits
Vee" 14.011
~
Vcc-!iV
.
lilN
1
fORVcc~4V
T
":"
Figure 1
11·20
switching time waveforms
VOUT
.>o--+--<>
CL "'5 Pf
FOR Vcc"!i.OV
Figure 2
VOUT
~
, '"=-C'-I-~
.~. - I~it"
f-" 1.0 MHz
tr"'tf"'lllns
PW" lOOns
c
absolute maximum ratings
(Note
15V
5.5V
15V
~5"e to +150"e
300"e
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldering. 10 sec)
electrical characteristics
logical "0" Input Voltage
Logical "1" Output Voltage
Logical" 1" I nput Current
Logical "0" Input Current
Output Short Circuit Current (Note 3)
Supply Current - Logical "1"
(Each Inverter)
Logical "0"
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
DM78L12
DM88L12
-55
0
125.
70
"e
"e
MIN
CONDITIONS
TYP
2.0
2.0
1.3
1.3
Vee = 14.0V
Vee -'" Min
Vee = 14.0V V ,N = O.7V
V ,N = 0.7V
Vee = Min
= Min
VIN = OV
Vee = 14.0V V ,N = 2.0V
V ,N = 2.0V
Vee"" Min
lOUT = -200/lA
lOUT = +200 /lA
lOUT
= -5.0IJ. A
11.B
14.5
Vee = 1.1V
0.5
0.2
= 3.6 mA
UNITS
V
V
0.7
0.7
V
V
V
V
V
12.0
15.0
lOUT = 12 mA
lOUT
MAX
1.3
1.3
1.0
0.4
V
V
Vee = 14.0V
VIN
V ,N = 2.4V
<1
<1
20
Vee = Max
10
/lA
/lA
Vee = 14.0V V ,N = 5.5V
V ,N = 5.5V
Vee = Max
<1
<1
100
100
/lA
/lA
Vee = 14.0V V ,N = O.4V
Vee::; Max
V ,N = O.4V
-320
-100
-500
-lBO
/lA
/lA
-25
-B
-50
-15
mA
mA
== 2.4V
Vee = 14.0V VOUT = OV
V OUT
= OV
Vee = 14.0V
VIN =
ov
Vee = Max
VIN
Vee
=
Max
-10
-3
= OV
Vee = 14.0V V ,N = 5.25V
V ,N = 5.25V
Vee = Max
0.32
0.11
0.50
0.16
mA
mA
1.0
0.3
1.5
0.5
mA
mA
Propagation Delay to a Logical "0"
from Input to Output, tpdO
Vee = 5.0V
TA = 25"'C
See Figure 2
27
45
ns
Propagation Delay to a Logical "0"
from Input to Output, tpdO
Vee = 14.0V
See Figure 1
TA = 25"e
11
20
ns
Propagation Delay to a Logical "1"
from Input to Output, tpd1 (Note 4)
Vee = 5.0V
TA = 25"e
See Figure 2
79
100
ns
Propagation Delay to a Logical" 1"
from Input to Output, lpdt
Vee = 14.0V
See Figure 1
TA = 25"e
34
55
ns
...
rN
Temperature
Vee = 14.. 0V
Vee"" Min
Vee
Logical "0" Output Voltage
Supply Voltage
DM78L12
DM88L12
(Note 2)
PARAMETER
Logical "1" Input Voltage
3:
ao
ao
operating conditions
1)
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot
be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the
devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions
for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the -5SoC to +125°e temperature
range for the DM78L12 and across the o"e to +70"e range for the DM88L12. All typical. are
given for Vee = 5.0V and TA = 25"e, or for Vee = 14.0V and TA = 25"e.
Note 3: Only one output at a time should be shorted.
Note 4: t pd1 for Vee = 5.0V is dependent upon the resistance and capacitance used.
11-21
Interface Circuits
LM139/LM239/LM339 quad comparator
general description
The LM 139 series consists of four independent
voltage comparators which were designed specifically to operate from a single power supply over a
wide range of voltages_ Operation from split power
supplies is also possible and the low power supply
current drain is independent of the magnitude of
the power supply voltage_ These comparators also
have a unique characteristic in that the input
common-mode voltage range includes ground,
even though operated from a single power supply
voltage_
Application areas include limit comparators, simple
analog to digital converters; pulse, squarewave and
time delay generators; wide range VCO; MOS clock
timers; multivibrators and high voltage digital logic
gates_ The LM 139 series was designed to directly
interface with TTL and CMOS_ When operated
from both plus and minus power supplies, the
LM339 will directly interface with MOS logic where the low power drain of the LM339 is a
distinct advantage over standard comparators_
advantages
•
• Allows sensing near GND
• Compatible with all forms of logic
•
Power drain suitable for battery operation
features
• Wide single supply
Voltage range
2 V DC to 36 V DC
or dual supplies
±1 V DC to ±18 V DC
• Very low supply current drain' (0.8 mAl independent of supply voltage (1 mW/comparator at +5 V Del
35 nA
• Low input biasing current
3 nA
• Low input offset current
and offset voltage
3mV
• I nput common-mode voltage range includes
ground
• Differential input voltage range equal to the
power supply voltage
•
1 mV at 5~A
70 mV at 1 mA
Low output
saturaticn voltage
• Output voltage compatible with TTL (fanout of
2), DTL, ECL, MOS and CMOS logic systems
Eliminates need for dual supplies
schematic and connection diagrams
Dual-In-Line and Flat Package
OUTPUTl OUTPUT4
GNU
OUTPUT 2 OUTPUT I
v·
INI'UT4+
INPUT4-
INPUT 3-
v'
OUTPUT
INPUT 1-
INPUT 1+
INPUT 2-
INPUT2+
TOP VIEW
Order Number LMl39D, LM239D or LM339D
See Package 2
Order Number LM339N
See Package 14
Order Number LMl39F
See Package 26
typical applications
+5VDC
+5Voc
v,
'OM
Driving TTL
11-22
Driving CMOS
Comparator with Hysteresis
absolute maximum ratings
Supply Voltage, V+
36 Voc or ±18 Voc
Differential Input Voltage
36 V DC
Input Voltage
-0.3 Voc to +36 Voc
Power Dissipation (Note 1)
Molded DIP (LM339N)
570mW
Cavity DIP
(LM139D, LM239D & LM339D)
900mW
Flat Pack
(LM139F)
800mW
Output Short-Circuit to GND (Note 2)
Continuous
electrical characteristics
MIN
At Output Switch Point,
Vo:= 1.4 VaG, V REF '"
+1.4 Vee and Rs '" on,
:::
-25°C to +85°C
-55°C to +125°C
-65°C to +150°C
300°C
LM239, LM339
MAX
±5.0
MIN
TVP
-~2.0
MAX
UNITS
..!:S.O
niVoc
250
nAoe
+25°C
Linear Range, T A
'"
25
100
25
+2Soc
+2 Soc
Input Offset Current
IIN(+) -IINH. T A'"
Input Common-Mode Voltage
Range (Note 6)
TA
Supply Current
RL = 00 On All Comparators
TA =+25°C
~
TYP
±2.D
IINII) or IINH With Output in
'"
50mA
o°c to +70°C
(v+ = +5.0 Voc. see Note 4)
CONDITIONS
TA
Input Bias Current (Note 5)
< -0.3 Voc )(Note 3)
LM139
PARAMETER
Input Offset Voltage
Input Current (V IN
Operating Temperature Range
LM339
LM239
LM139
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
±3.0
±25
:±.5.0
V+-1.5
+2Soc
0.8
2.0
0.8
150
nAoe
V+-1.5
V DC
2.0
mAac
Voltage Gain
RL
+25°C
200
200
Large Signal Response Time
VIN := TTL Logic Swing,
VREF=+l.4Vac,VRL'"
5.0 Voe and Rt_ '" 5.1 kn
300
300
Response Time (Note 7)
VAL"" 5.0 Voe and RL
5.1 kn,T A =+25°C
1.3
1.3
"'
Output Sink Current
VIN (__ ) ~ +1.0 Vac , VIN (+) = 0
and Va ~+1.5 Voc, TA ': +2SoC
16
16
mAoc
Saturation Voltage
VIN (.) ~+1.0Vac, VIN (+) '" 0
and ISINK ~ 4.0 mA, TA = +25°c
250
Output Leakage Current
VIN (+) :2 +1.0 Vac , VIN (_) '" 0
and VOUT '" 5.0 Voc , TA'" +2SoC
Input Offset Voltage
At Output Switch Point, Vo ~
1.4 Voc; V AEF '" +1.4 Voc and
Rs =on
Input Offset Current
IIN(+) -IIN(_)
Input Bias Current
IINi+) or liN i-I With Output in
Linear Range
15 kn, TA
=:
=
Input Common-Mode Voltage
Range
500
mVoc
9.0
9.0
mVoc
±10D
±15D
nAoc
300
400
nAoc
V+-2.0
V+-2.0
V DC
500
250
V/mV
0.1
0.1
nAoc
Saturation Voltage
VIN (_} :2+1.0Vac , VIN (+} =0
and ISINK ::; 4.D mA
700
700
mVoc
Output Leakage Current
VIN (+} :2+1.0Voc , VINH =0
and VOUT ", 30 Voc
1.0
1.0
pAoc
Differential Input Voltage
(Note 8)
Keep All Y,N 's 2:" 0 Voc (or
V-, if used)
36
36
V DC
Note 1: For operating at high temperatures, the LM339 must be derated based on a +12SoC maximum junction temperature and a thermal
resistance of +175°C!W which applies for the device soldered in a printed circuit board, operating in a still air ambient. The LM239 and
LM139 must be derated based on a +150°C maximum junction temperature. The low bias dissipation on the ON-OFF characteristic of the
outputs keeps the chip dissipation very smalt (Pd ~ 100 mW), provided the output transistors are allowed to saturate.
Note 2: Short circuits from the output to V+ can cause excessive heating and eventual destruction. The maximum output current is approximately 20 rnA independent of the magnitude of V+.
Note 3: This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction
of the input PNP transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is
also lateral NPN parasitic transistor action on the IC chip. This transistor action can cause the output voltages of the comparators to go to
the V+ voltage level (or to ground for a large overdrive) for the time duration that an input is driven negative. This is not destructive and
normal output states will re-establish when the input voltage, which was negative, again returns to a value greater than -0.3 VOC.
Note 4: These specifications apply for V+ = +5.0 VOC and -55°C ~ TA s:: +12SoC, unless otherwise stated. With the LM239, all temperature specifications are limited to -25°C ~ TA ~ +8SoC and the LM339 temperature specifications are limited to O°C ~ T A ~ +70°C.
Note 5: The direction of the input current is out of the Ie due to the PNP input stage. This current is essentially constant, independent of
the state of the output so no loading change exists on the reference or input lines.
Note 6: The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than 0_3V. The upper
end of the common-mode voltage range is V+ - 1.5V, but either or both inputs can go to +30 VOC without damage.
Note 7: The response time specified is for a 100 mV input step with 5.0 mV overdrive. For larger overdrive signals 300 ns can be obtained,
see typical performance characteristics section.
Note 8: The positive excursions of the inputs can exceed the power supply voltage level, and if the other input voltage remains within the
common-mode voltage range, the comparator will provide a proper output state. The low input voltage state must not be less than -0.3 VOC
(or 0.3 VOC below the magnitude of the negative power supply voltage, if used).
11·23
typical performance characteristics
Supply Current
1.0
or
.!
0.8
Input Current
T.=-55'~ f-'
_I J.
.L. -T.~i'""
.. ;,
..i:. ...
Ii;
;
a:
>-
I
"'-
0.8
OA
BO
~ --t::'fC
~
-
...
!!
I
10
30
20
20
Tf '+:25'~
I I
0
10
y+ -SUPPLY VOLTAGE IVocl
f
30
6
co
is>
>~::
~
co
...co
c1->
~E
2Om~.~._
3
1
~.
100m
0
I I I
I I I
i.=~5,L
O
co_ -50
> z
5>
~1OD
~
>
0.001
0.5
1.0
1.6
1
....... T. =+25'C
~V
I
0.1
0.01
40
1.0
10
100
10 - OUTPUT SINK CURRENT (mAl
6
~
~
~~2!
~::
~
co
~'>
co.s
Z
~>
I
4
1
3
!L
2
u
0
50 t-
2.0
TIME I_I
5mV
20mV
I
100
0
,,
",INPUT OVERDRIVE = 100 mV
1
...co·
>
5
t-l·:tl
~J?'-.
H.
I I I
!!
0
~v
~V
I
0
Response Time for Various
Input Overdrives - Positive
Transition
J¥11111
4
2
/ f f TA = -55'C
y+ - SUPPLY VOLTAGE (Vocl
5 mV - INPUT OVERDRIVE
5
f WI--
IA
0.01
:i
I I
20
Response Time for Various
Input Overdrives - Negative
c
I-
I JUTI!F
-II)TURtTlOIN
TA=+125°~
I-
1'\ T.TA,=+2~C
=+70'C-
Transition
",'
0.1
I--
~
$
40
..
-
a:
E
I I I RL =_
1.0
..
I-
T... =+12&OC- I--
il
~
'"cco
!:;
co
>
co
T.· O"C
40
-I
0
V1NICMI" 0 VDC
RINfCMI S!!1tJ1n
T~' -J6'C
I-
I:
a:
TA " +70°C
0.2
I I
I I
il
c
.s ao
a:
Output Saturation Voltage
10
0
0.5
I I
1
1.5
2
TIME,,"",)
application hints
The LM139 is a high gain, wide bandwidth
device; which, like most comparators, can easily
oscillate if the output lead is inadvertently allowed
to capacitively couple to the inputs via stray
capacitance. This shows up only during the output
voltage transition intervals as the comparator chan·
ges states. Power supply bypassing is not reo
quired to solve this problem. Standard PC board
layout is helpful as it reduces stray input-output
coupling. Reducing the input resistors to <10 kn
reduces the feedback signal levels and finally,
adding even a small amount (1 to 10 mV) of posi·
tive feedback (hysteresis) causes such a rapid transition that oscillations due to stray feedback are
not possible. Simply socketing the IIC and attach·
ing resistors to the pins will cause input-output
oscillations during the small transition intervals
unless hysteresis is used. If the input signal is a
pulse waveform, with relatively fast rise and fall
times, hysteresis is not required.
All pins of any unused comparators should be
grounded.
The bias network of the LM139 establishes a
drain current' which is independent of the magnitude of the power supply voltage over the range of
from 2V DC to 30 VDC •
It is usually unnecessary to use a bypass capacitor
across the power supply line.
11·24
The differential input voltage may be larger than
V+ without damaging the device. Protection should
be provided to prevent the input voltages from
going negative more than -0.3 VDC (at 2SoC). An
input clamp diode and input resistor can be used
as shown in the applications section.
The output of the LM 139 is the uncommitted
collector of a grounded·emitter NPN output transistor. Many collectors can be tied together to provide an output OR"ing function. An output "pull·
up" resistor can be connected to any available
power supply voltage within the permitted supply
voltage range and there is no restriction on this
voltage due to the magnitude of the voltage which
is applied to the V+ terminal of the lM 139 package. The output can also be used as a simple SPST
switch to ground (when a "pull·up" resistor is not
used). The amou nt of current wh ich the output
device can sink is limited by the drive available
(which is independent of V·) and the {3 of this
device. When the maximum current limit is
reached (approximately 16 mAl, the output transistor will come out of saturation and the output
voltage will rise very rapidly. The output saturation voltage is limited by the approximately 600
rsat of the output transistor. The low offset voltage
of the output transistor (1 m V) allows the output
to clamp essentially to ground level for small load
currents.
typical applications (con't)
+5'o'oc
v'
lOOk
-12 Voc
TEMPERATURE
SENSUII6
THERMOCOUPLE
MOS to TTL Logic Translator
Ground Referenced Thermocouple
in Single Supply System
v'
(liVre)
51.
.... ,
+5V oc
'60
.00
\
I
IN!I.
P
4.3.
vo
200
I
,,/ +--+---1
1M
"V REF4
'00
Ramote Temperature Sensing
'60
+5 Voc
P
"VREF3
'00
+IiV oc
V"
'"
TTL to MOS Logic Converter
P
+15Vpe
+VREf2
10.
R1
I.
.2
'''''
'60
P
+VREF'
'01
"
lN914
D2
1NI14
lOp'
P,.
+15V oc
v'
,~~,
,"
o-""'.....H
1M
Visible Vo"_ Indicator
*Forlarge ratios of Rl/R2.
":"
D1canbeomitted.
Pulse Generator
11-25
typical applications (con't)
V·
V·
,...
"Ok
4.3.
Uk
V;n.r
~PF
f
~
V;n...n.
100kHl
Vo
Vo
.
"
,,..
,,,.
Crystal Controlled Oscillator
Squarewave Oscillator
V·
V·
,,..
''''
500pF
3.Ok
3.0k
s.a
'V,
FREDUENCY
>",,,,,-0
CONTROL
VOLTAGE
OUTPUT 1
INPUT
V'"
...
~-----------------+~
DUTPUTZ
50'
V+"+30Voc:
+250 mVoc S" Vc
s: +50 Voc
7DOHz'$fo$100kHz
Two-Decade High-Frequancy VCO
V·
V·
V·
.V",o-----I
Vo
Vo
Vo
10K
",.O-""'",,",H
Basic Comparator
,.
Non-Inverting Comparator with Hysteresis
Inverting Comparator with Hysteresis
v·
,,..
Vo
STROBE
INPUT
Vo
·ORlogicgltewithout
pull-apresistor.
Comparing I nput Voltages
of Opposite Polarity
11-26
Output Strobing
....
typical applications (con't) (v+ ~
3:
..&
15 Vod
W
V·
CD
.......
....
V·(12Vod
3:
lOOK
'"
.......
V OUT
:'::T
''0''
N
W
CD
....
C'D
3:
w
"1"
w
CD
,
ALL DIDOES
1,.914
Larg. Fan-in AND Gate
Limit Comparator
V'
V'
::r
"
200.
lk
C
''0''''1''
OR Gate
AND Got.
V'
V'
'00'
'1K
'"
'00'
'DO'
O.OOl"f
lOOK
Bi-Stabla Mu Itivibrator
One..shot Multivibrator
V'
,. ,.
..OK
'OM
""
-fE "V
,~
o
'"
'01'
1I0 Pf
T
V,
MI.
12k
':'
One-8hot Multivibrator with Input Lock Out
11-27
typical applications (con't)
II.
'"
(v+ = 15 Vocl
....
".
V'
'8M
,,.
Vo
v,
...
"0
~:rL
10
14
u•
C1
O••J1I1F~
-v.
v,
INPUT GATING SIGNAL
v+
-------- __""'___ --
...
".
3.1•
".
t
v"
I
v,
...
ORing the Outputs
Time Delay Generator
v·
V'
".
M"NE'IC
PICKUP
1.0.
"
Av ~ 1110
Low Frequency Op Amp
Av=110
Low Frequencv Op Amp
3.0k
II
Vo
,.
Transducer Amplifier
(VO = OV for VIN = OV)
v·
Vo
R2
"
Low Frequency Op Amp with Offeat Adjust
11·28
'"
Zero Crossing Detector (Single Power Supply)
split-supply applications
(v+ = +15 V DC and V-- =-15 V OC )
v-
v,
Zero Crossing Detector
v-
5DpF
v,
MOS Clock Driver
Comparator With a Negative Reference
11-29
Interface Circuits
LM55107A/LM75107A.LM55108A/LM75108A.
LM163/LM363 dual line receivers
LM75207.LM75208.LM363A dual MOS sense amplifiers
general description
features
The nine products described herein are TTL
compatible dual high speed circuits intended for
sensing in a broad range of system applications.
While the primary usage will be for line receivers
or MOS sensing, any of the products may effectively be used as voltage comparators, level trans·
lators, window detectors, transducer preamplifiers,
and in other sensing applications. As digital line
receivers the products are applicable with the
LM55109/LM75109 and LM55110/LM75110 com·
panion drivers, or may be used in other balanced
or unbalanced party-line data transmission systems.
The improved input sensitivity and delay specifi·
cations of the LM75207, LM75208 and LM363A
make them ideal for sensing high performance
MOS memories as well as high sensitivity line
receivers and voltage comparators. TR I-STATE®
products enhance bused organizations.
•
High speed
•
TTL compatible
•
Input sensitivity
•
Input common·mode range
•
High input impedance with normal Vee, or
Vee = OV
•
Strobes for channel selection
17 ns typ
±10 mV or ±25 mV
±3V
•
TRI·STATE outputs for high speed buses
•
Dual circuits
•
Sensitivity guaranteed over full common-mode
range
•
Logic input clamp diodes
•
14 pin cavity or molded dual·in·line package
•
Standard supply voltages
±5V
connection diagrams
Dual-In-Line Package
Dual-In-Line Package
Vee·
INPUT
1A
INPUT
18
INPUT
2A
Ne
INPUT
28
OUTPUT
IV
Ne
OUTPUT
2V
STROBE
2G
STROBE
lG
STROBE
S
GNO
v~'
INPUT
INPUT
Vee·
lA
28
Ne
INPUT
1A
INPUT
Ne
OUTPUT
STROlE
DISAILE
IV
lG
0
18
STROBE
2V
2G
GNO
TOP VIEW
TOP VIEW
Order Number LM55107AJ, LM75107AJ,
LM55108AJ, LM75108AJ, LM75207J or LM75208J
See Package 9
Order Number LM75207N or LM75208N
See Package 14
Order Number LM163J, LM363J or LM363AJ
See Package 9
Order Number LM163N, LM363N or LM363AN
See Package 14
product selection guide
TEMPERATURE ......
PACKAGE""
INPUT SENSITIVITY""
OUTPUT
~5°C
S; T A ~ +12Soc
CAVITY DIP
O°C:$TA ::;+70°C
CAVITY OR MOLDED DIP
!:25mV
!:25mV
lM55107A
LM5510SA
lM163
lM75107A
lM7510SA
lM363
±10mV
LOGIC~
TTL Active Pull-up
TTL Open Collector
TTL TRI-STATE
11-30
OUTPUT
lM75207
lM7520S
lM36JA
absolute maximum ratings
Strobe I nput Voltage
Storage Temperature Range
Power Dissipation
7V
-7V
±6V
±5V
Supply Voltage, Vee+
Supply Voltage, Vee-
Differential Input Voltage
Common Mode I nput Voltage
5.5V
~5°e to +150o e
600mW
3000 e
Lead Temperature (Soldering, 10 sec)
operating conditions
LM55107A,
LM55108A,
LM163
NOM
MAX
MIN
4.5V
5V
5.5V
4.75V
5V
5.25V
-4.5V
-5V
-5.5V
-4.7SV
-5V
-S.25V
-S5°e
to
+12Soe
oOe
to
+70 oe
MIN
Supply Voltage Vee +
-
Supply Voltage Vee
Operating Temperature Range
LM75107A, LM75207
LM75108A, LM75208
LM363, LM363A
NOM
MAX
typical applications
Line Receiver Used in a
Party-Line or Data-Bus System
TWISTEOPAIR
TRANSMISSION
LINE
lOll
-=
line receivers are lM75107/lM751 08 or LM16J.
line
driv~rs
are LM55109/LM55110 or DM7831.
Line Receiver Used in MOS Memory System
TTl TOIiIOS
MM1101 MOS MEMORY ARRAY
DRIVEAS
11-31
««
COM
Oco
schematic diagrams
'-M
~~
~...J
...J '
....... CO
«0
CON
OLn
LM55107A1LM75107A. LM75207
LM55108AiLM75108A. lM75208
.- .....
Vcc+o--"'~~--""-"'-"'_f-----~~--"'--'-----
...
Ln~
Ln...J
~....:
~
'"
'"
...JO
'N
Ln
«
..........
1.6K
4K
8.5K
...
-:,~----,
~ .. t.-..... -~
ttL ..
~~
,
Ln...J
.....
--,I
'2D~
,
~4K
'
~M
...JCO
I
INPUT 8
I
....... M
«~
I
I
:
OUTPUT
INPUT A0---+----'
..... ...J
0 .......
'-M
LnCO
Ln.-
'---r--+1---~~-,~~--oGN'
3K
JK
~~
'----+-~---OSTROBE
...J...J
G
.----~----_DSTR08f S
v~-o--_~----~-~--t-
_____
~
Note 1: 112 of the dual circuit is shown.
Note 2: '"Indicates connections common to second half of dual circuit.
Note 3: Components shown with dash lines ate applicable to the lM55107A, lM75107A, and lM75207 nnlv.
LM163iLM363. LM363A
Vcc + 0--f---1~--""-"'-"'~P-----~~--f----'----,
INPUT B
OUTPUT
INPUT A0---+----'
t--~~~+-----4~~--~-DGN'
3K
'-----+----t-o STROBE G
3K
8.5K
DISABLE 0
vcc-o--_~---~-~-_~-----~
Notel: 1/2 of the dual circuit is shown.
Note 2: *llIdieates connections common to
second half of dual circuit.
11-32
,...
...
~
LM55107A/LM75107A. LM55108A/LM75108A
dc electrical characteristics (T MIN "STA "STMAXI
a»
W
,...
MIN
Vee + =- Max, Vee - '" Max,
V 1D = Q.5V, VIC = --3V to 3V
High Level Input Current
Into lA, lB.2Aor2B (lIHl
Into lA,lB.2Aor28 (IlL)
Vee + '"' Max, V ee - = Max,
V ID = ~2V. VIC = 3V to 3V
High Level Input Current
Vee + = Max, V ee -
IntolGor2G (IIHI
V1H1S )
High Level I nput Current
Vee
Into lGor 2G (IIH]
V1H(S)"" Max Vee
Low Level Input Cunent
Into lG or 2G (IlL)
Vee + = Max, Vee - = Max,
High Level Input Current
Into S (lIH)
Vee + = Max, V cc - = Max,
V 1H1S) '" 2.4V
High Level Input Current
Into S litH)
Vee t
Low Level Input Current
Vee + = Max, Vec - "" Max,
Into S (I,LI
V'LIS) '" DAV
Low Level Input Current
=
=
LM55108A/lM75108A
LM55107AILM75107A
CONDITIONS
TYP
30
MAX
MIN
30
75
"A
-10
-10
"A
40
40
"A
-1.6
-1.6
...
~ 0
.....
.....
UI
0
.....
,...
~
.....
80
80
Max, VCC~ '" Max,
Vec t'" Min, Vcc -
<=
,... ,...~
~
-3.2
-3,2
a»
W CO
Min,
24
V
04
ISINK '" 16 mA, V ID = -25 mV,
0.4
l> l>
V
V'c == -3V to 3V
High Level Output
Vc;c + = Min, Vc~- '" Mm
Current (I OH )
V OH == Max Vcc
250
Vce + = Max, Vec - '" Max,
High Logic Level Supply
Current From Vec (ICCH+)
V ID == 25 mV, T A == 25°C
High Logic Level Supply
Vee + == Max, Vec - == Max,
Current From Vce UCCH-)
V'c =25mV,T A = 25°C
Input Clamp Voltage on
Vee + '" Min, Vee - = Min,
liN =-12mA,T A = 25°C
G or 5 (Vd
-70
-18
Vec + == Max, Vcc - = Max
Current (los I
18
-84
-1
ac switching characteristics
"A
rnA
30
18
-15
-8.4
-1
-1.5
(V cc + = 5V, V cc - = -5V,
TA
30
rnA
-15
mA
-1.5
V
= 25°cl
LIMITS
PARAlVETER
CONDITIONS
LM55107A/LM75107A
MIN
Propagation Delay Time, Low to High
Level, From Differential Inputs A and
RL = 390n, C L '" 50 pF
TYP
MAX
17
25
LM5S10BA/LM7S10BA
MIN
TYP
MAX
19
25
19
25
13
20
13
20
UNITS
B to Output (Note 1) (tpLHtnl)
Propagation Delay Time. Low to High
Level, From Differential Inputs A and
R L '" 390[2, CL == 15 pF
B to Output (Note 1) (tPLHID»)
Propagation Delay Time, High to Low
Level, From Differential InpulS A and
RL '" 390n, CL == 50 pF
17
25
B to Output (Note 1) (tpHL{Q) )
Propagation Delay Time, High to Low
Level. From Differential Inputs A and
RL == 390n, CL
=
15 pF
B to Output (Note 1) (tpHL{O) )
P,opagatlon Delay Time, Low to High
Level, From Strobe Input G
01
S to
RL = 390[2, CL == 50 pF
10
15
Output (tPLHISI)
PlOpagatlon Delay Time. Low to High
level, From Stlobe Input G 01 S 10
RL == 390n, C L == 15 pF
Output (tPLHISd
Propagation Delay Time, High to Low
Level, From Stlobe Input G or S to
RL = 390n, C L = 50 pF
15
Output (tPHLISd
Propagation Delay Time, High to Low
Level, F,om Sllobe Input G 01 S to
R,
390n, C L '" 15 pF
Output (tPHLISI)
Nota 1: Differential input is +100 mV to -100 mV pulse. Delays read from
.....
...
0
W UI
rnA
Vcc + '" Min, Vcc -" Min,
Short Circuit Output
...
N
0 l>
CO .......
"A
V'c = -3V to 3V
low Level Output
~
UI
UI
UI 0
rnA
rnA
I LOAD == -400j../A, V ,D '" 25 mV,
Voltage (VoLI
,...l>
CO
VIHISI '" Max Vee
Voltage (VoHI
,...
.....
i- UI
rnA
VIL(S) "" DAV
High Level Output
a»
W ~
MAX
- Max, Vee ~ =- Max,
'"
UNITS
TYP
75
.....
~ l>
W .......
N
Max,
2AV
...
....... 0
LIMITS
PARAMETER
~
UI
UI
a mV on input to 1.5V on output.
11·33
•
wg
0)'"
V
l>l>
Vcc + == Min, Vcc - '" Min,
0.4
ISINK " 16 rnA, V IO '" -25 mV,
V ILIO ) '" O.BV, VIC" -3V to 3V
Output Disable Current
Vcc+::o Max, V cc -= Max,
(100 1
VIHCOI '" 2V, V OUT = 2 4V
Output Disable Current
V cc + '" Max, Vcc-::O Max,
0 00 1
VIHIOl '" 2V, V OUT
Short Circuit Output
Current (los I
Vee + '" Max, VIL(o) = 0.8V,
V ce - = Max
High Logic Level Supply
Current From Vee + (lceH+1
V ee + '" Max, V ce - = Max,
V IO =25mV, TA = 25°C
28
High Logic Level Supply
Current From Vee - (leeH-)
Vee + = Max, V ee - '" Max,
V tD =25mV, TA =25°C
-8.4
!nput Clamp Voltage on
GorD IV,}
Vee + = Min, V ee - == Min,
liN = -12 mA, T A = 25°C
-1
'"
O.4V
-18
ac switching characteristics
V
40
"A
-40
"A
-70
mA
40
mA
-15
mA
-1.5
V
(Vcc+=5V,Vcc-=-5V,TA=25°C)
LIMITS
PARAMETER
CONDITIONS
LM163/LM363
MIN
UNITS
TVP
MAX
Propagation Delay Time, Low to High
Level, From Differential !nputs A and
B to Output (Note 1 I ttpLH{O) I
RL = 390n, CL = 50 pF
17
25
Propagation Delay Time, High to Low
level, From DifferentIal Inputs A and
B to OutPUt (Note 1) (tPHLlod
RL " 390n, C L = 50 pF
17
25
Propagation Delay Time, Low to High
level, From Strobe !nput G to
Output (tPLH (5) I
RL ::; 390n, C L = 50 pF
10
15
Propagation Delay Time, High to Low
Level, From Strobe Input G to
RL .. 390n. CL = 50 pF
15
Disable Low to High to Output High
to Off tt1Hl
RL = 390n,CL =5pF
20
Disable Low to High to Output Low
to Off ItOHI
RL = 390n, C L -=
5 pF
30
Disable High to Low to Output Off
to High (t H1 1
AL = 1k to OV, C L
Disable High to Low to Output Off
to Low (tHO)
RL = 390n, C L -" 50 pF
OutPUt (tPHLCS)i
::::.
50 pF
r-
s:r-S:....
W CII
mA
25
25
Note 1: Differential input is +100 mV to -100 mV pulse. Delays read from 0 mV on input to 1.5V on output.
11·35
LM363A
dc electrical characteristics
(O°C:STA
~+70°C)
LIMITS
PARAMETER
LM363A
CONDITIONS
MIN
High Level Input Current
Vee + "Mu. Vee - Ma)C,
Into lA, lB. 2Aor 28 (111-1)
VIO = O.5V, VIC = -3V to 3V
low Level Input Current
Into lA. 1 B, 2A or 28 Old
Vee + = Max, Vee -" Max,
VIC =-2V. VIC"" -3V"to3V
High Level Input Current
Vee + = Max, Vee - '" Max.
Into lG, 2G or 0
VIM IS) "2 4V
OIH)
High Level Input Cunent
Into lG, 2G or 0
(lIH)
UNITS
TVP
MAX
30
75
"A
-10
"A
40
"A
Vee ~ '" Max, Vee ~ " Max,
VIHISf "Max Vee
mA
low level Input CUrl en!
Vee + "Max, Vee - "Mal<,
Into D (IlL)
V ILID )" Q4V
Low level Input Current
Into 1G or 2G (IlL)
Vee +" Max. V cc - "" Max.
V1H(Q) '" 2V, V1L1G! "0 4V
Low Level Input Current
Into lG or 2G (IlL)
Vee + "Ma><, Vee -" Malo:,
High Level Output
Voltage (V OH )
Vee + "Mm, Vee -" Mm,
'LOAD = -2 rnA, VIO = 10 mV,
VIL(Ol -::. 0.8V, VIC'" ·-3V to 3V
Low Level Output
Voltage (VOL)
Vee + = Min, Vee - '" Min,
ISINK '" 16 mA, VIO = -10 mV,
VlllOI = 08V, Vie = -3V to 3V
Output DIsable Current
(1001
Vee + =: Max, Vee - = Max,
VIHIOl '" 2V, V OUT = 2.4V
Output DIsable Current
Vee +
(100)
VIHIOI :2V, V OUT =OAV
Short CirCUit Output
Current 1105 1
Vee+=Max,VllIOl
V ee - '" Max
HIgh LogiC Level Supply
Current From Vec + (leeH+)
Vee + ': Max, Vee - = Max,
VIO = 10mV, T", =2SoC
28
High LogIC Level Supply
Current From Vee - (leeH-J
Vee + = Max, Vee - = Max,
VIO = 10mV, TA, =2SoC
-8.4
Input Clamp Voltage on
GorD IVoi
V ce + = Min, V ee -= Min,
lIN = -12 mA, T A, = 2SoC
-1
VILIO) '"
oav,
VIL!GJ"
= Max, V ec -;'
-1.6
--40
-1.6
O.4V
24
ac switching characteristics
0.4
-18
(V cc +=5V. V
"A
mA
V
Max,
=oav,
mA
cc -=-5V.
V
40
"A
--40
"A
-70
mA
40
mA
-15
mA
-1.5
V
TA = 25°C)
LIMITS
PARAMETER
LM363A
CONDITIONS
MIN
TVP
UNITS
MAX
Propagation Delay TIme, Low to High
Level, From DIfferential Inputs A and
8 to Output (Note 1) (tpLHIOlJ
RL = 4700, C L '" 15 pF
35
Propagation Delay TIme, High to Low
Level, From Differential Inputs A and
B to Output (Note 1) (tPHLIO)J
Rl = 4700, Cl '" 15 pF
20
RL = 470n. CL :::: 15 pF
17
PropagatIon Delay Time, High to Low
Level, From Strobe Input G to
OutPUt (tPHLlSI J
RL = 470!t CL "'" 15 pF
17
Disable Low to High to Output High
to Off (t1H)
RL "'" 4700, CL '" 5 pF
20
Disable Low to HIgh to OutPUt Low
to Off (tOH)
RL = 470n. CL '" 5 pF
30
Disable' High to Low to Output Off
to High (tt-l1)
RL = lk to OV, CL = 15 pF
25
Disable High to Low to Output Off
to Low (tHO)
RL = 470n, C L = 15 pF
25
Propagation Delay Time. Low to HIgh
Level, From Strobe Input G to
Output (tPLH IS) I
Not. 1: Differential input is +10 mV to -30 mV pulse. Delays read from 0 mV on input to 1.5V on output.
11-36
Microprocessors
INTRODUCTION
National Semiconductor produces a family of Microprocessors built around the MM5750 and MM5751 LSI
processor building blocks described in this section. Because this family spans a range from chip sets thru
card assemblies to complete microcomputer systems, National can support the microprocessor user at any
desired level of building complexity.
The microprocessor assemblies and systems presently available are described below. Software support for
these products includes both resident and cross·assemblers; as well as debug programs, relocating loaders,
and diagnostics.
16·BIT PRODUCTS
IMp·16C/200,IMP·16C/300: These are complete microprocessors on B 1/2" x 11" PC cards. They include
those architectural features described in the MM5750 and MM5751 data sheets, as well as:
•
•
•
•
256 words of Read/Write Memory
Sockets for 512 words of PROM
Interrupt Capability
Conditional Jump and User Flag Logic
The IMP·16C/200 has a 43·instruction set, with one empty socket to accept a second CRaM which extends
the set to 60 instructions. The IMP·16C/300 includes both CRaM's for a full 60·instruction set. That is the
only difference between the two.
IMP·16L/300: This is a microprocessor card similar to the IMP·16C cards described above, but without any
on·card memory. Other differences include:
• Direct Memory Access Capability
• Vectored Priority Interrupt Logic
• Single·Bus I/O Structure
This card is supplied with two CRaM's, providing a 60·instruction set.
IMP·16P/304, IMP·16P/308: The IMp·16P's are prototyping systems to aid the IMp·16C card or chip set
user in the development of interfaces and applications software. They include a IMP·16C card, chassis, front
panel, power supply, 4k or 8k of Read/Write Memory, and interfaces for TTY and card reader. A resident
assembler and other system software are supplied with the IMp·16P.
IMP·16L/304, IMP·16L/308: These IMp·16L systems are prototyping tools to aid the IMp·16L card user in
the development of interfaces and applications software. They include a IMP· 16L card, 4k or 8k of Read/
Write Memory, and a TTY interface. A resident assembler and other system software are supplied with the
IMP·16L.
8·BIT PRODUCTS
IMP·8C/200: This is a complete microprocessor on an 8 1/2" x 11" PC card. It includes those architectual
features described in the MM5750 and MM5751 data sheets, as well as:
•
•
•
•
256 bytes of Read/Write Memory
Sockets for 2k bytes of PROM
Interrupt Capability
Conditional Jump and User Flag Logic
IMp·8P/208: This is a prototyping system to aid the IMp·8C card or chip set user in the development of
interfaces and applications software. It includes an IMP·8C card, a chassis, front panel, power supply, 8k
bytes of Read/Write Memory, and interfaces for TTY and card reader. System software is supplied with the
system.
For more detailed information on the above products, request a Product Description from your local sales
representative.
12·1
IMP-SERIES PRODUCT NUMBER SYSTEM
II'---v---''--,.--'
M P -Ixlxlal/lblcldlelfl
}-1
~'--r-'
FAMILY NAME
THIS DESIGNATOR IS THE SAME
FOR ALL MEMBERS OF THE
FAMILY
Y S U B - CODE EXPANSION
e IS EXPANSION FOR HOWR, REV
LEVEL FOR MANUALS. SEE NEXT
SHEET FOR SFTWR.
DEVICE SUB - CODE
NUMBER OF BITS
THE MEANING OF THIS FIELD IS
DEPENDENT UPON THE DEVICE
OR CLASS CODE.
4,8,16, ETC. FOR ITEMS NOT
ASSOCIATED WITH FIXED
WORD LENGTH, USE '00'.
MEMORIES
SIZE OF MEMORY ON WORDS
.1k FOR CARDS, .100 FOR CHIPS
CARDS / SYSTEMS
MAJOR DEVICE CODE
. ,HIS FIELD INDICATES THE
MAJOR DEVICE WITH WHICH
THE PARTICULAR ITEM IS
ASSOCIATED.
L-____~
C - IMP - 16C CARD
UP - SYSTEMS & ASSOCIATED
COMPONENTS
A - COMPONENTS THAT CUT
ACROSS CARD OR SYSTEM LINES.
S - SOFTWARE
H - MECHANICAL HDWR. THAT
CUTS ACROSS CARD/
SYSTEM LI N ES.
F - FIRMWARE
DEVICE CLA! CODE
AMOUNT OF MEMORY IN THE
SYSTEM, IN 1k INCREMENTS.
SYSTEMS WITH LESS THAN lk
OF MEMORY (LIKE IMP-16C) WILL
USE '00'.
SOFTWARE/MANUALS
NUMBER SEQUENTIALLY, START AT
00 IN ORDER OF RELEASE.
PERIPHERALS / HDWR
00-09
10-19
20-29
30-39
40-49
50-59
60-&9
70-79
80-89
90-99
or
-
8TC & GEN'L OPTIONS
TTY's & PRINTERS
CARD EQUIP.
MAG. TAPES
DISCS
PAPER TAPE
DATA COM
ADC/DAC, ETC.
POWER, CHASSIS, & MOUNTING
CABLES & MISC.
SOFTWARE CLASS CODE
FIELD INDICATES A
CLASS OF DEVICE
ASSOCIATED WITH SOME
MAJOR CATEGORY ABOVE.
O-MEMORY
1 - DEVICE/SYSTEM WITHOUT
SPACE FOR EXTENDED CROM.
2 - DEVICE/SYSTEM WITH SOCKET
FOR EXTENDED CROM.
3.- DEVICE/SYSTEM WITH EXTENDED CROM.
4,7 - UNUSED AT PRESENT,
8 - PERIPHERAL OR CHASSIS PART.
9 - HARDWARE MANUAL.
5 - CHIP SETS.
6- DICE.
FIELD INDICATES CLASS OF
SOFTWARE WITHIN AWORD
SIZE. USE THESE CODES IF
DEVICE CODE IS "S" ONLY.
0- UTILITY ROUTINES
1 - ASSEMBLERS
2 - COMPILERS & INTERPRETERS
3 - OPERATING SYSTEMS
4 - MATH ROUTINES
5 - DIAGNOSTICS
6 - APPLICATION PROGRAMS
9 - SFTWR PACKAGES INCLUDING
SFTWR. MANUALS.
SOFTWARE SUB-CODES
II
M P
-lxlxl.I/I+ldlelf I
'--,.--'
t
USE THIS SET OF SUB-CODES FOR SOFTWARE AND LISTINGS ONLY. (a
(f) - REVISION
LISTING
SOURCE P. TAPE
OBJ, P. TAPE
SOURCE 7TK M.T., 556BPI
OBJ. 7TK M.T., 556BPI
SOURCE 7TK M.T., BOO BPI
08J 7TK M.T., 800 BPI
SOURCE 9TK N.T., 800 BPI
08J 9TK M. T., 800 BPI
SOURCE 9TK M,T., 1600 BPI
OBJ 9TK M. T., 1600 BPI
SOURCE CASSETTE
OBJ CASSETTE
SOURCE ON DISC
o - OBJ ON DISC
R - V AVAILABLE
W- USER WRITE-UP
P - SOURCE CARDS
Q - OBJ CARDS
Y - MANUAL
REV. LEVELS ARE ASSIGNED
SEQUENTIALLY STARTING
WITH (A).
A - W NORMAL RELEASE
X - PRE-RELEASE
Z - OBSOLETE; AVAIL.
FOR REPLACEMENT ONLY
A B C 0E F G H I J K L MN -
12-2
= S)
(e)-MEDIUM
IMP-SERIES MICROPROCESSORS LIST
MODEL
PRODUCT DESCRIPTION
IMP·16L HARDWARE
IMP·16L1300
IMp·16L1304
16·bit microprocessor on 8·1/2 x 11" printed circuit card. Includes the following features:
•
Extended Instruction Set
(60 instructions)
•
Direct Memory Access Logic
•
•
Priority Interrupt Logic
Address Capability for 65k of Memory
16·bit, Microcomputer prototyping system to aid the system designer in working with the
IMP·16L microprocessor card. Includes:
•
•
•
•
IMp·16L1300 Microprocessor Card
Basic Software Package
Control Panel and Chassis
Power Supply with power for up to 8k
of memory
• 4k Read/Write Memory
• TTY Controller
• 8 Slots additional card mounting
capacity
IMP·16L1308
Same as IMp·16L1304 but includes 8k words of Read/Write memory
IMp·16L1004
4096 word, 16·bit Read/Write memory card for IMp·16L. Size is 8·1/2 x 11".
IMP·16L/825W
IMP·16L Card Reader Controller for DOCUMATION Card Reader (2 pc cards plus
software)
IMP·16P AND IMP·16C HARDWARE
IMp·16C/200
16·bit paraliel microprocessor system packaged on an 8·112 x 11 printed circuit card.
Includes the following features:
• 256 words of 16·bit RAM memory
• Sockets for 512 words of ROM
memory
•
Interrupt logic
•
Address capability for 65k of memory
(off card)
•
Socket for Extended Instruction Set
CROM
IMp·16C/300
Same as IMP·16C/200 above, but includes Extended Instruction Set CROM (IMP·16A1
522N).
IMp·16P/204
16·bit microcomputer prototyping system, to aid the system designer in working with the
IMP·16C microprocessor card. Includes:
• IMp·16C/200 Microprocessor Card
• Chassis, Front Panel, and Power Supply
• 4k Read/Write Memory
• TTY ICard Reader Interface
• Basic Software Package
• 7 slots additional card capacity
IMP·16P/208
Same as IMp·16P1204 but includes 8k words of Read/Write Memory
IMP·16P/304
Same as IMp·16P/204, but includes Extended Instruction Set CROM.
IMP·16P/308
Same as IMp·16P/208 but includes Extended Instruction Set CROM.
IMP·16P/004
4096 word, 16·bit ReadIWrite memory card (8·1/2" x 11 ") for use with IMp·16C/200
and IMP·16P/20x. Requires one IMp·16P/0042 Timing and Control Card for 1·8 memory
cards.
IMP·16P/004T
Timing and Control Card to support IMP·16P/004 RAM memory cards used with
IMP·16C/200 and IMP·16P/l0x. One card supports up to 8 RAM memory cards. Size
is 8·1/2" x 11".
IMP·16C/882
Control panel board for use with IMP·16C, provides programmer easy access to functional
areas of the card. Includes PC board, data switches, display lights, and controls.
IMp·16F/500
2·PROM set, including Memory Diagnostics, control panel service routine, and sample
programs for IMp·16C cards. (CMEMDI)
IMp·16F/501
4·ROM set including complete IMp·16 CPU Diagnostics, for IMP·16C card. (ROMDI)
IMp·16F/000
2·PROM set including service routines for TTY and Control Panel, for IMp·16C card.
(CUTIL)
16·BIT FIRMWARE AND SOFTWARE
12·3
IMP-SERIES MICROPROCESSORS LIST (Con't_)
MODEL
PRODUCT DESCRIPTION
IMP-16F/002
2-PROM set including software debug routines to be used with IMP-16F/OOO above, an
IMP-16C card and a TTY_ (DEBUGC)
IMP-16S/900A
IMP-16 Cross Assembler, for use on IBM System 360/370 or other large-scale computers
with at least lOOk bytes of available memory. Written in ANSI FORTRAN 4, accepts
IMP-16 machine language. Package includes:
FORTRAN Source Card Deck
(lMP-16S/100P)
• Assembler Manual (IMP-16S/102Y)
• Assembler Source Listing (IMP-16S/100A)
•
• 360/370 Assembler Installation
Manual (lMP-16S/114Y)
• Assembler Internal Description Manual
(IMP-16S/103Y)
Package includes all items, but each item is also available individually, at price shown in
parenthesis.
Note that a version of this Cross-Assembler is also available through the terminal network
of Tymshare Corp. Contact local Tymshare office.
MANUALS - l6-BIT EQUIPMENT
IMP-16C/92l
IMP-16C/935
IMP-16C/936
IMP-16C Application Manual
IMP-16C Interface Guide
IMP-16C/P Product Description
IMP-16L/924
IMP-16L1925
IMP-16L/92S
IMP-16L Product Description
IMP-16 Utility Reference Manual
IMP-16L User's Manual
IMP-16S/l02Y
IMP-16S/l03Y
IMP-16SI11SY
IMP-16 Programming and Assembler Manual
IMP-16 Assembler Internal Description Manual
IMP-16 Tymshare User's Manual
IMP-SC AND IMP-SP HARDWARE
IMP-SC PROCESSOR CARD
IMP-SC/200
8-bit parallel microprocessor system packaged on an 8-1/2" x 11" printed circuit card.
Includes:
256 words of 8-bit ReadlWrite
Memory
• Sockets for 2048 words of PROM
Memory
•
IMP-8P/20S
Interrupt logic
Address Capability for 65k of Memory
(off card)
8-bit microcomputer prototyping system to aid the system designer in working with the
IMP-8C microprocessor card. Includes:
•
•
•
IMP-SP/2l6
•
•
8k Bytes of ReadlWrite Memory
IMP-8C/200 Microprocessor Card
Chassis, Front Panel, and Power Supply
•
•
TTY/Card Reader Controller
6 Slots of Additional card mounting
capacity
• Basic Software Package
Same as IMP-8PI208, but includes 16k bytes of ReadlWrite Memory.
S-BIT FIRMWARE AND SOFTWARE
IMP-8F/50l
8-PROM package including CPU diagnostic routines
IMP-SS/900
IMP-8 Cross-Assembler for use on IBM System 360/370 or other large-scale computers
with at least lOOk bytes of available memory. Written in ANSI, FORTRAN 4, accepts
IMP-8 assembly language mnemonics and outputs IMP-8 machine language. Package
includes:
•
•
FORTRAN Source Card Deck
Assembler Manual
• Assembler Source Listing
• 360/370 Assembler Installation Manual
Note that a version of this Cross Assembler is also available through the terminal networks
of the Tymshare Corp. (Contact local Tymshare office), and General Electric Information
Services.
12-4
IMP-SERIES MICROPROCESSORS LIST (Con't_)
MODEL
PRODUCT DESCRIPTION
8-BIT EOUIPMENT MANUALS
IMP-8C/932
IMP-8C Application Manual
IMP-8P/930
IMP-8P/933
IMP-8C/P Product Description
IMP-8P User's Manual
IMP-8S/040Y
IMP-8S/134Y
IMP-8P Utility Reference Manual
IMP-8 Programming and Assembler Manual
IMP-OOH/880
6 Slot Card Cage with six l44-pin wire-wrap connectors for mounting IMP series microcomputers, memories, and 1/0 controllers. Mounts in IMP-16L, ·16P, or -8P chassis.
IMP-OOH/881
6 Slot Card Cage as above, but with three 144-in wire-wrap connectors, spaced for use
with IMP-00H/89x wire·wrap Prototyping Cards.
IMP-OOH/891
Prototyping Card, 8·1/2 x 11" with 144-pin connection on one edge, and pre-drilled to
hold 64 16-pin wire-wrap sockets or 58 16-pin and 4 24-pin wire-wrap sockets (not
included). Mounts in 6-slot Card Cage.
MECHANICAL ASSEMBLIES
IMP-OOH/882
144-Pin Single Card Connector for IMP-series cards.
IMP-OOH/892
Prototyping Card, 8-1/2 x 11 ", with 144-pin connection on one edge, and pre-drilled to
hold up to 90 wire-wrap sockets (not included) in any combination of 16-pin and 24-pin
configurations. (24-pin uses two socket positions.)
IMP-OOH/890
Extender Card for use with IMP Series cards and card cages. Includes 144-pin male and
female connectors, and will raise a logic card clear of the card cage for easy access to
components.
PERIPHERALS FOR USE WITH IMP-16L, -16P, -8P
IMP-OO/825
Documation 300 CPM Card Reader and Cable
IMP-OO/8l0
ASR-33 Teletype and Cable
MICROPROCESSOR CHIP SETS
IMP-16A/500D
16-bit Microprocessor Chip Set including four Register Arithmetic Logic Units (RALUs)
and one Control Read Only Memory (CRaM) with standard 43-instruction set.
IMP-16A/502D
16-bit Microprocessor Chip Set as above, but including a second CRaM with the extended
60- i nstructi on set.
IMP-8A/500D
8-bit Microprocessor Chip Set including 2 RALUs and one CRaM with the standard
38-instruction set.
IMP-OOA/520D
Register, Arithmetic and Logic Unit (RALU) used in the above mentioned Chip Sets.
This device is a 4-bit processor slice for use in 4 to 32-bit computers.
IMP-16A/521D
Control Read-Only Memory (CRaM) used to microprogram four RALUs for the standard
16-bit, 43-instruction set.
IMP-16A/522D
CRaM used to microprogram four RALUs for the extended l6-bit, l7-instruction set.
Intended for use with the IMP-16A/521D, above.
IMP-8A/520D
CRaM used to microprogram 2 RALUs for the standard 8-bit, 38-instruction set.
MM52030
MM5203D
Unprogrammed PROMs, 256 x 8 bit, for use with all IMP series microprocessors.
MM5203D may be electrically programmed once, while MM52030 may be erased with
UV light and re-programmed.
CHIP SET MANUALS
IMP-OOA/905
Microprocessor Chip Set Product Description.
12-5
Microprocessors
IMP MM5750 MOS/LSI register and arithmetic
logic unit (RALU)
general description
The MM5750 is a member of a new family of
microprocessor elements, and is a monolithic
MOS/LSI circuit utilizing standard P-channel, enhancement mode, silicon gate technology. It provides a 4-bit slice of the register and arithmetic
portion of a general purpose controller/processor.
RALU's may be stacked in parallel for longer
word lengths. The RALU is designed to be used
with other members of National's IMP family
(in particular the MM5751 CROM) to form a
complete processor. Each RALU provides 96
bits of storage in the form of 4 bits in each of 7
general registers, a status register and a 16-word
last in, first out (LI FO) stack. The arithmetic and
logic unit performs ADD, AND, OR and exclusive
OR operations on true and complemented data
from the registers at nearly 106 operations per
second. A shifter is provided for single bit left or
right shifts and an I/O data multiplexer for
communication with an external data bus. Control
is provided over a 4-bit, time multiplexed command
bus.
The RALU operates on +5V and -12V supplies
with 4-phase, non-overlapping clocks. Signals which
are intended for interface with the MM5751
CROM are MOS level, while those which are
intended for interface with the rest of the processor system are TTL levels.
features
• 4-bit slice of register
and arithmetic logic block
•
ADD, AND, OR,
Exclusive OR
Arithmetic and
logic operations
Functions not
pre-assigned
• 7 general purpose
registers
Overflow, Link, Carry,
general flag
• 4-bit status
register
•
Last in, first out
16 word stack
4-bit, bipolar
compatible
• Multiplexed
1/0 data bus
• Multiplexed command bus
•
-700 kHz
+5V,-12V
• Standard suppl ies
•
Drives TTL
Bipolar compatibility
Non-overlapping
• 4-phase clock
24-pin DIP
• Standard package
applications
•
General purpose processor
• Distributed and multiprocessors
• Process controllers
• Machine tool controllers
• Small business machines
• Term i nal controllers
Expandable to
32-bit word
• Test system and instrument control
• Traffic controller
block and connection diagrams
Dual~ln·Line
Package
24
DATAm
.
Voo (-12V)
"~
"
NeBID)
20 Ne8ll!
"
"
[IATA(31
NCB (1)
NCB(2l
(GND)V"'
SININ
CSH3
(+ 511IVss
.
IS
"
"
evov
13 SELECT
Order Number IMP-OOA/520D
See Package 6
Order Number IMP.QOA/520N
Se. Package 18
12-6
4-bit MOS levels
High speed operation
absolute maximum ratings
All Input or Output Voltages With Respect to
+0.3V to -20V
Most Positive Supply Voltage Vss
Operating Temperature Range
Storage Temperature
Power Dissipation
aOc to +70°C
--65°e to +150°C
1W Maximum at +25°C
Note: Maximum ratings indicate limits beyond which permanent damage may occur. Continuous operation at these limits
is not intended and should be limited to those conditions specified under de electrical characteristics.
dc electrical characteristics
(T A =
o·c to +70·C, Vss = +5V ±5%, VGG = -'2V ±5%, V LL = GND)
PARAMETER
CONDITIONS
Logic ","Input (MDS and TTL) (V ,NIO ) (Note')
MIN
(Note 2)
TYP
MAX
(Note 2)
Logic "O"lnput (MDS) (V ,NIO ))
Vss -7.0
Logic "O"lnput (TTL) (V'N(o))
Vss - 4.0
Logic "O"lnput Current (TTL) (I,NIOI)
Y'N = OV
Input Leakage Current (MaS) (Id
V 1N = +5.0V to -12V
UNITS
V
Vss - 0.8
V
V
-1.75
mA
±1.0
j.lA
Logic "'" Output (MOS) (V OUT ,,))
Vss - 0.4
V
Logic "0" Output (MOS) (VOUTIOI)
Vss - 8.0
V
Logic "'" Output (TTL) (VOU"O)
lOUT'"
0.2 rnA
Logic "0" Output (TTL) (VOUTIOI)
lOUT'"
-1.6 rnA
Pull-up Transistor "on" Resistance (PPUL.L_up)(Note 1)
V 1N
= Vss -1.0V
Signal Line Input Capacitance (Cs ) lor SELECT, SVRST,
SININ, OATA (0), (')' (2), (3)
Y'N = Vss , IT = 700 kHz
CSHO, CSH3 Input Capacitance (Cs )
Y'N = Vss , IT = 700 kHz
Clock Input Capacitance (C c )
Y'N = V ss , IT = 700 kHz
3.0
7.0
30
Clock "'" Leve) (V¢I") (Note 4)
Vss-'·O
Clock "0" Level (V ¢Io))
VGG -1.0
Load Capacitance lor DATA(O), ('), (2), (3),
CSHO, CSH3 (Cel
CYOV, FLAG
STFL, NREQO
V
2.4
"
40
0.4
V
5.0
k!1
'0
pF
'4
pF
55
pF
Vss
VGG
+ 1.0
25
20
30
Y'N = OV, IT = 700 kHz
V
V
pF
pF
pF
Current Sinking Resistors Required on CYOV,
STFL, NREQO (R SINK ) (Note 3)
From Pin to VaG
Power Dissipation (Po) (T I - T 8 Equal Width)
f= 700 kHz
4.6
550
5.8
k!1
750
mW
Note 1: Internal pull-up provided for TTL inputs. Refer to Figure 3 and text.
Note 2: Max = most positive; Min = most negative.
Note 3: Required to drive 74H loads. Larger resistance values may be used to drive standard or low power TTL.
Note 4: Clamp diodes and series damping resistors may be required to prevent clock overshoot.
FUNCTIONAL DESCRIPTION OF RALU
A diagram of the RALU is shown in Figure 1.
Seven general registers (labelled R1 -R 7 ) are provided. Any of the seven registers may be loaded
onto the A· or B·bus for processing by the
arithmetic and logic unit (ALU). The data on the
A·bus may be complemented before being loaded
on the lA-bus, which serves as the input to the
ALU. The operations which may be performed
by the ALU are ADD, AND, OR and exclusive
OR. The ADD operation adds IA and B and the
carry (CSHO) from pin 14. A carry output (CSH3)
is provided by pin 11. The result of the ALU
operation is available to the shifter via the S·bus.
The shifter provides a one bit left or right shift
(or no shift) and transfers the shift information
in and out of pins 11 and 14. Output data from
the shifter may be returned to any of the
registers over the R·bus.
A 16word last in, first out stack (LIFO) is provided
and may be accessed over the A· and R·buses.
When the bottom word of the stack becomes non·
zero a stack full signal (STFL) is provided at pin 3.
Status information is provided by a 4·bit status
register. Link, Overflow, Carry and Flag indicators
are provided in bit positions 3, 2, 1 and 0
respectively (where bit 3 is the most significant
bit). The Link flag may be included in shift
operations (under control of the Select input)
and the Overflow and Carry flags provide informa·
tion on the result of ADD operations. A general
purpose status flag (Flag) is also provided which
may be used for interrupt enable or other functions ~here it is desirable to save status bits on
the stack. Also, the Link, Overflow and Carry
functions may be disabled, allowing these flags to
be used for general purpose application. This is
12·7
V.,...VI[D--
VGG H2VJ
II:>-ffi:>--
MCl101
IE>----
Vu flUIDJ
NClmiD-NCI' 2J i D - NC8f3JID--
s,",N[!IO!>------==~:I::_-'
DATA(3J
(21
FIGURE 1. RALU Block Diagram
described in the section detailing control signals
for the RALU.
Communication between the RALU and the rest
of the system is provided by the 1/0 data multi·
plexer. This logic provides for loading the R-bus
from the external data bus, as well as sending
data from the A- and R-buses. Details of sigl"lal
functions and'timing are presented in the following
sections. Positive true logic signals are used ("1" =,
most positive voltage, "0" = most negative voltage).
Signal names beginning with N are complemented
signals.
FUNCTIONAL DESCRIPTION OF SIGNALS
Signal timing for the RALU is shown in Figure 2,
The timing diagram is divided into 8 time intervals
(T,-T8) based on the 4-phase non-overlapping
clocks. The clock inputs have MOS levels of +5V
and -12V and occur during the odd time intervals,
Thus phase 1 ciock is a logic "0" (-12V) during
T, and a logic "1" (+5V) during T 2 -T 8 •
Commands
The command inputs to the RALU occur on pins
21, 19, 18, and 20 which correspond to command
bits NCB(O)' (1)' (2), and (3) respectively. The
command inputs are complemented MOS signals
and are multiplexed over the 4 odd time intervals
in each RALU cycle (T" T 3 , T 5 , T 7 ). The
inputs must be driven negative to logic "0"
during the even time intervals. The command
functions for each bit are indicated in the diagram.
During T" the three least-significant command
bits specify the address of the register (R,-R 7 )
12-8
to be loaded on the A-bus. If NCB(O), (1), and
(2) are all logic "1" the A-bus is set equal to zero.
The fourth command bit NCB(3) is used to enable
stack operations. If NCB(3) is at a logic "1"
(most positive level) no stack operations occur. If
it is a logic "0" stack operations are enabled, but
will only occur if the A or R-bus address is zero.
If the A-bus address is zero the stack wi II be pulled
onto the A-bus. If the R-bus address is zero, the
R-bus will be pushed onto the stack.
During T 3 the three least-significant bits specify
the address of the register (R,-R7) to be loaded
on the B-bus. (Note that stack and flags cannot
be accessed over the B-bus. An address of zero always gives zero data, however, NCBX's = all 1's.)
The most-significant bit specifies that the A-bus
is to be complemented when it is transferred to
the lA-bus.
During T 5 , NCB(l) and NCB(O) specify the ALU
operation to be performed as follows: DO-AND,
01-XOR, 10-0R, ll-ADD. NCB(3) and NCB(2)
are used to specify control functions as follows:
OO-No-OP, Ol-R-bus control, 10-shift S-bus left
l-bit position during transfer to R-bus, ll-shift
S-bus right l-bit position during transfer to R-bus.
The R-bus control code is used in conjunction
with the 1/0 control bit (NCB(3) at T 7) and
the Byte input (SININ at T 5) to set the value
of the R-bus as shown below and in Table I
(RALU command code summary).
During T 7 the three least significant bits specify
the address of the register (R,-R 7 ) to be loaded
LOGIC
LEVELS
SIGNALS'
¢,
MOS
CLOCKS
¢,
MOS
¢,
MaS
¢,
MOS
TIME INTERVALS
T3
T2
T1
T'
~IN
T6
T'
T7
TO
FUNCTION
s:
s:
U'I
PIN
NO.
......
U'I
IN
J
0
IN
\...---1
"--.I
~
IN
23
IN
21
21
gQMMAND
NCB(Q)
MOS
AD
"0"
BO
"0"
AWci
"0"
Ro
"0"
IN
NCB(n
MaS
Ai
"0"
Bi
"0"
ALUl
"0"
Ai
"0"
IN
19
NCB(2)
MOS
Ai
"0"
B2
"0"
CTL6
"0"
R2
"0"
IN
I.
NCB(3)
MaS
STACK
"0"
caMP
"0"
eTll
"0"
DATA(0),(1},(2),(3}
TTL
i16
DATA
R BUS!OUT)
CONTROL
I - - - 000·' C." lOCI
=1
SELECT
TTL
SVRST
TTL
DC
CYQV
TTL
CARRY OR OVERFLOW
FLAG
TTL
r---
STFL
TTL
f-------STACK FULL
NREQO
Mise
SIN IN
CSHQ
CSH3
TTL
MOS·T5
TTL·T7
MaS
MOS
FLAG
I---RoO
OVCEN
ONl
SELECT
20
17,5,4,7
IN
13
..,..
_
"1"
~I-
• I-
"0"
~
OC
SIGN
"1"
r---- HIGH IMPEDANCE
HIGH
IMPEDANCE 2
IN
I/O
OC--
-I·
-I-
"0"
"'"
(OUT)
t=0C--
SVRST
I--- Don't Care ( D C ) - - - "1"
(OUT)
DATA
INPUT
"1" (GUT)3
A BUS(QUTj
I
BYTe
2 ___
"0"
(OUTI
I
IN
OUT
"
OUT
16
"'"
OUT
R =0
OUT
OC
IN
10
(IN)
(OUT)
"'"
SHIFT 110
I/O
I.
CARRY
(OUT)
"1"
(OUT)
SHIFT I/O
I/O
11
CARRY
Note 1: A positive true logic convention is used for all signals (I.e., "1" = more positive voltage, "0" "" more negative voltage).
Signal names beginning with N are complemented signals.
Note 2: CSHO and CSH3 high impedance state for intervals T2 through T 4 is the TRI-STATE mode for output drivers.
Note 3: "1" (OUT) means RALU is driving this node to the "1" logic level during the defined interval. For bidirectional I/O
lines the logic state is defined as "in" or "out."
FIGURE 2. RALU Timing Diagram
from the R-bus. The most-significant bit specifies
that the R-bus is to be set equal to the output of
the I/O multiplexer rather than the shifter (unless
R-bus control was specified at T 5). Reference
R-bus control states Table I.
Data
The data transfers between the RALU and memory
or peripheral devices occur on pins 17, 5, 4, and 7
which correspond to data bits DATA(O), (1), (2)
and (3) respectively. During T 1 and T 2 the data
lines are driven with the value of the R-bus which
occurred at the end of the previous timing cycle.
This output may be used by the CROM chip for
conditional branch inputs. During T 3 and T 4 the
data lines are driven with the value that was
loaded onto the A-bus during the current timing
cycle. This output is typically used for address
and data output to system memory or peripheral
devices. During T 5 and T 6 the data lines are driven
to a logic "1." During T 7 the data lines are used
for input to the RALU from system memory or
peripheral devices. The data receivers are "zeroes
catching" so the data lines must not be allowed
to go negative during T 7 unless the data input is
to be a logic zero. During T 8 the data lines are
again driven to a logic "1" by the RALU. As
with all TTL inputs on the RALU a 3K-5K
pull·up is provided on the chip to insure an
adequate logic "1" level (see Figure 3). The
pull-up is provided by an MOS transistor which
is turned on only during the data input interval.
At other times it is in the "off" or high impedance
state.
Control Signals
The RALU control lines provide a means of using
the RALU status flags. The SELECT line is used
as an input at T 5 ("zeroes catching") and is unused
at other times. If the SELECT line is a logic "1"
at T 5 the Overflow status flag will be selected as
the output on the Carry or Overflow (CYOV) line
(pin 15) during the following cycle. If the RALU
is in the most significant byte of a processor (as
specified by the Byte input on the SININ line)
the Link status flag will be included in any shift
that occurs in the current cycle. The shift will be
a five (5) bit shift with the Link in the most
significant bit position. If the Select input is a
logic "0" at T 5 the Carry status flag will be
selected at the CYOV output and shift operations
will not affect the link.
The Save/Restore (SVRST) line is used as an
input during T 5 ("zeroes catching") and provides
a means of modifying the status flags over the
data bus. If SVRST is a logic "1" during T 5 the
status flags will be loaded onto the A-bus during
the following cycle (at TIl, provided the A·bus
address bits NCB(2)' (1), and (0), at T 1 during
that cycle are a logic "1." If a pull stack operation
has been specified by NCB(3)' (2), (1), and (0) at
T 1, the SVRST input at T 7 will inhibit it and
instead the status flags will be loaded on the A-bus.
Table II specifies the control bits and the data that
occurs on the A-bus at T 1. The SVRST line also
causes the status flags to be loaded from the R-bus
at the end of the following cycle. (The statos of
12-9
r--------------------~
I
I
'.
I~'-;
I
I
~
1
-I
~
'.
I
I
}--4>-"W\,-+----i~---_; ~ ~mf;:i
SYRST
SElEI:T
SININ
- I r F: ' ·
'00
flAG
NtBIO)
NCBm
NC8(2)
NCB(1)
-I
I
I
'00
rJ.
DATAIO)
)-+--""IV-....-+----1 ~RECEIVER
DATA(1)
DATAm
DATAIJ)
O'S CATCHING"
-I
-I
'.
~~
'"
~~
-I
-I
-I
-I
IL ____________________
~
*\'5
&,~
J
fot SININ input. Note: Input protection on all inputs.
FIGURE 3. RALU Driver and Receiver Buffers
SVRST during one cycle only affects conditions
in the fol/owing cycle. I This will occur in parallel
with the loading of any other register specified
by the R·bus address. Table III specifies the
control bits and the results that occur on the
R·bus.
The CYOV line provides an output signal indicating
the state of the Carry or Overflow status flag as
determined by the Select input. The Flag output
indicates the state of the general purpose status
flag. The stack full (STFLI output goes true when
the bottom word of the stack is non-zero at the
start of the preceding cycle. The result bus equals
zero (NREOO) output goes to logic "0" level when
the R·bus contains all zeroes. The CYOV, STFL
and NREOO outputs require an external resistor
connected to V GG.
Miscellaneous Signals
The SININ line is used to input information as to
whether the RALU is in the most or least signifi·
cant byte of a processor word (at T 5) and also
the sign value wh ich is propagated to the most
significant byte (at T 7) when the R·bus control
function is specified. If SININ is a logic "1" at
T 5 the RALU will enable the functions of the
most significant byte. The functions enabled are
inclusion of the Link in shift operations and
setting the R-bus to zero or sign as specified by
12-10
the R-bus control code. If SI N I N at T 5 is a logic
"0" the functions are not enabled.
The carry input (CSHO) and carry output (CSH3)
lines are used primarily for transfer of carry and
shift information between RALU's or between
RALU and CROM. If an ADD operation is specified, the value of carry input (CSHO) at T 5 will
be added to the IA and B-bus inputs to the ALU.
The resulting carry output from the most significant
bit will occur on CSH3 at T 5' When a left shift is
specified, the shift output from the most significant bit occurs on CSH3 at T 7 and T 8 while the
shift input ("zeroes catching") to the least significant bit must be provided on CSHO during T 7
and Ta. The pins exchange roles for a right shift.
During T 1 the CSH3 input (if a logic "0" at T 1 )
is used to enable the Overflow and Carry flags to
be set to the result of an ADD operation, if an ADD
is specified for the current cycle. The Carry flag
is set equal to the value of the ripple carry out of
the most significant bit of the ALU. The Overflow
flag is set if there is a two's complement arithmetic
overflow (i.e. sign of both operands was the same
and the sign of the result is different). For systems
using multiple RALU's the Overflow and Carry
flags of all but the most significant RALU will be
disabled by the logic "1" output of CSHO generated
by the adjacent RALU at T l ' These flags may
therefore be used for general purpose functions.
TABLE I. RALU Commands
1.A Command I"puts
COMMAND BITS 1
TIME
INTERVAL
NC8(3)
T1
Sl ACK
A BUS
T3
COMP
B BUS
To
' - - - CTL
17
I/O
NCB(21
I
NCB('I
I
NCBIOI
ALU-
L
R BUS
1.B Command Codes3
ALU FUNCTIONS
CTL FUNCTIONS
NCBI1!. 101 @T5
FUNCTION
NCBI31, 121 @ T5
11
AND
11
FUNCTION
NONE
'a
XOR
10
R BUS CONTROL
01
OR
01
SHIFT LEFT
00
ADD
00
A, B & R BUS ADDRESSES
SHIFT RIGHT
R BUS CONTROL
NCBI2!. 1'1, 101
ADDRESS
111
ZEROES, FLAGS, STACK'
110
(NCB(31 @T71
BYTE
(SININ@T51
R BUS VALUE
,
110
R1
OUTPUT OF SHI FTER
R2
,
a
101
1
OUTPUT OF SHI FTER
100
R3
a
a
OUTPUT OF 110 MUX
all
R4
a
1
0'0
R5
VALUE OF SIGN INPUT
ON SININ@T7
001
R6
000
R7
Note 1: Commands are complemented signals.
Note 2: See text and Tables II and III for addressing flags and stack.
Note 3: Logic values shown are values which must be applied to NCB inputs to get indicated results.
TABLE II. Binary Table for A Bus Addressing
(Time Interval T,)
RESULTING DATA
ON A BUS
INPUTS
SVRST
@ PreVIOUS Cycle T 5
a
a
a
a
a
a
a
a
0
a
a
a
a
a
0
a
,,
,
,,
1
,
,,
,
1
1
1
1
1
,
NCB 131, (21, (11, (01
@
TABLE III. Binary Table for R Bus Addressing
(Time Interval T7)
SVAST
@Prevlous Cycle T 5
Current Cycle T 1
,,
,, ,
1 1 1 1
1 , a
, 0 ,
a a
, a ,
1
a
1
a
1
1
a
o
o
a
a
o
a
a
1
1
1
1
a
0
a
0
1
1
o
a
1
1
,
a
1
aa
o0
0
,
a
,
a
0 1
0 0
, , ,,
,,
1
1
1 1 a
o
1 a ,
1
0
1
a
1
1 0 1 0
1 0 0 1
a
1
1
a
a
,
,
1
a
a
a
a
a
a
,
1
,
1
a
a
o
o
0 1 0
0 0 1
0
1
a
,
a a a a
All Zero's
Contents of
Contents of
Contents of
Contents of
Contents of
Contents of
Contents of
Pull Stack
Contt:nt~ of
Contents of
Contents of
Contents of
Contents of
Contents of
Contents of
NCB (3) @CurrentCycie
Tl and NCB (2), (l),(O)
@Current Cycle T 7
0
Al
A2
A3
A4
R5
As
R7
R1
A2
R3
R4
R5
R6
R7
Status Flags
Contents of Rl
Contents of R2
Contents of R3
Contents of R4
Contents of R5
Contents of Rs
Contents of R 7
Status Flags
Contents of R,
Contents of R2
Contents of R3
Contents of R4
Contents of Rs
Contents of R6
Contents of R7
REGISTER LOADED
FROM R BUS
INPUTS
a
a
a
a
0
a
a
a
0
a
a
0
a
a
a
1
1
1
1
1
1
1
1
1
,
,,
,,
,
1
,111
,,
1
1 a
, a 1
1 1 0 a
1 a 1
,
1 0 1 0
1 0 0 1
1 0 a a
,,
a 1
o 1 1 0
a1a1
o1 aa
o a 1 1
o0 1 a
oaa 1
aaa0
,, ,, , ,
,
,
1 , a
1 a
1 0 1
a
,
a
1
1 0 1 a
1 0 0 1
1 0 0 a
,
a , 1
a , 1a
o1a1
o10 a
a a 1 1
aa1
oa0
0
1
a a a a
Not Stored
R,
R,
R3
R,
R5
R6
R,
Push Stack
R,
R,
R3
R,
R5
R6
R,
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Status
Flags
Flags and
Flags and
Flags and
Flags and
Flags and
Flags and
Flags and
Flags and
Flags and
Flags and
Flags and
Flags and
Flags and
Flags and
Flags and
At
A2
A3
R4
A5
Rs
A1
Push Stack
A1
A2
R3
A4
A5
Rs
R7
Note: LogiC values shown are what must be applied to NCB
(which is a complemented signal) to get desired results.
Note: Logic values shown are what must be applied to NCB inputs to get results shown.
12-11
Tl
10% 90%
140nsMIN
"
13
90% 10%
:;-
"
-\
.30mMIN
"
90% 10%
140nsMIN
"
-
10% 90%
I., I
",
V
-
f-
90% 10%
"
f\
MI~
MIN
ABUSOUT
1
I
~
~
MAX
MAX
140 ns MIIII
-
-
"
\
/
I
,
ilO ns MIN
"
"
/
10% 90%
-
T7
~-:;- ~~ ~- ~~ ~r-I
~ ~I
MIN
"IN
1l0rrsMIIII
90% 10%
T5
550s
450'
10% 90%
.,
140nsMIN
TJ
~~
DATA!O),(lJ.l21.(3I
.,1
"'","IN
I
\
T1
55ns
NCB((IUIl.(2).(l1
T8
10% 90%
55ns
450s
MIN
MIN
550s
45n5
MIN
"IN
A BUSOUT
_Iyss OUT
'"'
MIN
"1"OUT
~
I
l5n!
MAX
I
A
~
350s
~
MAX
DATA
INPUT
35n!
~ - 11MIN
NO FALSE
NEG TRANSJTlON
II
I
80 os
~
DATA
INPUT
SElECT.SVRST
~ C--
BOns
MIN
I
NO fALSE
NEG TRANSITIONS
I
1
i
I I "'m 1
CYOV
flAG
I
I
MAX
i
VALID
I
I
I
I
VALID
MAX
!
!
I
80"'1
I
I
I
I
I
I
80ns
f-~AX
I
I
1l00!_1
STFt"
MAX
._-
~
I
I
SININ
I
kfr
"'"
CSHJ
"IN
MIN
~
II I
1 81ln•
"0"
205mi
MAX
VALID
""'
~
SIGN
INPUT
VALID
.IN
35ns
MIN
NO FALSE
NEG TRANSITION
I
I
i
CARRY INPUT
I
I
I
I
I
MIN
""'
I
i
I
I Ii
I
50 os
(-
"0"
I
VALID
1
1
I
OUT
MAX
'~-,F
r B~"'''UT
~ p;J
I
I
I
CSHO
!
I
I
I
I
I
I
MAX
VALID
IIIREQO'
I
I
I
~An;
VALID
i 80"'1
i
"I" OUT
r'
I
I
~
80.
~
~r ~ ~
F
30ns
MIN
I
"0"
"."
80ns
~
I~:;
DHA~rTr---
MAX
CARRV
~:pOLJ~1
~
CSHO
OUT
I
SHIFT OUT
I,.,~I
INPUT
BOns
MIN
t-
J.FT 'UT
80.
~I I.,~
r
INPUT
~I
BO"'I
MAX
MIN
NO fALSE
NEG TRANSITION
I
330nsMIN
T ~ MICROCYClEPERIOD
~
lOpS MAX
*WIth external 5.8k resistor to VGG .
Note: t, and 1+ '" 250 ns max.
FIGURE 4. RALU Signal Timing Specifications
(TA = O°C to +70°C, Vss =+5.0V '5%, VGG = -12V ±5%. VLL = GND)
12·12
~~
NO FALSE
NEG TRANSITION
On
MI
Recommended Start-up Conditions
Power supplies must be within specification for
ten microseconds (lOllS) before clocks are started.
(Note: All internal nodes must be in a discharged
state before start-up.) When power supplies are
cycled on and off rapidly the nodes must be
discharged by running the clocks for one (1)
microcycle (T 1 - T 8) after power is removed from
the RALU.
is not valid at the start of T 5 then the CSH3
output will become valid a maximum of 50 ns
after the input becomes valid. In a typical 16·bit
application the carry input (CSHO) to the least
significant RALU will be valid at the start of T 5.
however. the carry input to the more significant
RALU's will be delayed, since it must first be
generated at the CSH3 output of the preceeding
less significant RALU.
It is recommended that STFL and CYOV be tied
to V55 if not used.
As indicated on the CSHO timing specification,
the latest the CSHO input can become valid for a
proper RALU ADD operation to occur is 30 ns
before the end of T5'
SIGNAL TIMING SPECIFICATIONS
The output from CSH3 is valid within 50 ns of a
valid input at CSHO. In a system with multiple
RALU's the carry must propagate through each
RALU and provide a valid input to the most
significant RALU at least 30 ns before the end of
T 5. For a system with N RALU's, the minimum
width of T 5 to allow for carry propagation is
approximately 40N + 1.5N2 ns (N ~ B). However,
this is strongly affected by the carry line capaci·
tance (this capacitance should be minimized as
much as possible, especially for the high order bits).
The timing specifications for all RALU signals
are shown in Figure 4. These specifications apply
over the complete range of recommended operating
conditions (T A = O°C to +70°C. V55 = +5V ±5%.
VGG = -12V ±5%). Time intervals are defined with
respect to the 10% and 90% points of the four
MOS clock inputs. The clocks have a maximum
rise and fall time of 250 ns. The command inputs
on the NCB lines must be valid a minimum of 55
ns prior to the end of the odd time intervals (see
Figure 3). Data inputs to the RALU over the data
lines must be valid for at least 35 ns during T 7 and
must never go falsely negative to a logic zero.
during T 7 , due to the "zeroes catching" nature of
the receiver. It will often simplify interface design
if input data to the RALU is gated onto the data
bus during parts of T 6 and T 8 as well as during
the required interval T 7 . The logic "1" outputs
of the RALU data lines at T 6 and T 8 may be
overridden by the data input drive; however. the
increased power dissipation will lower the maximum allowable ambient temperature for the chip.
(Note: The logic "1" output drive has a minimum
impedance of 300n to VS5 ')
The specification of the carry output (CSH3)
applies only when the carry input to CSHO is
valid prior to the start of T 5' If the CSHO input
For systems where N is large, T 5 should be
streched to provide the additional time. Alternatively the buffer circuit shown in the figure
below may be used between RALU's. A single
buffer between the center RALU's will typically
reduce the carry propagation time by more than
30%, however the noise margin is reduced
somewhat.
te
H
'IN4454
RAlU(I+ll
2N4215
c"O~_""_..J1N4454
_____
RAlum
CSH3
L -__
~
12-13
Microprocessors
IMP MM5751 MOS/LSI control and read only
memory unit (CROM)
general description
The MM5751 Control and Read Only Memory Unit
(CROM) is a member of a new family of microprocessor devices, and is a monolithic MOS/LSI
circuit utiiizing standard P-<:hannel, enhancement
mode, silicon gate technology_ It provides read
only microprogram storage and control logic and
is designed for use with the MM5750 R~ister and
Arithmetic Logic Unit (RALU)_ The CROM provides storage for one-hundred microinstructions
of 23 bits each. Circuitry is also provided for
program sequencing, subroutine execution, and
translation of microinstructions into RALU command·s. One CROM may be used with 1 to Ii
RALU's to implement systems with 4 to 32-bit
word lengths. Multiple CROM's may be used to
provide expanded capability. CROM's are available
with standard 8- and 16-bit i.nstruction sets. (Other
sets may be available in the future.)
The CROM operates on +5V and -12V supplies
with 4-phase, non-overlapping clocks. Signals which
are intended for interface with the MM5750 RALU
are MOS level, while those which are intended for
interfacing with the rest of the system are TTL
levels.
features
•
•
•
•
•
•
•
Standard supplies
Bipolar compatibility
Standard package
High speed
Microprogrammable
Subroutine capability
Expandable
+5V, -12V
Drives TTL
24 pin DIP
-700 kHz
100 words
Return address register
Up to 4 CROM's
applications
•
•
•
•
•
Standard I MP instruction sets
Expansion of standard instruction sets
Custom instruction sets
Custom application control programs
Control of 4 to 32-bit microprocessors when
used with MM5750-Register and Arithmetic
Logic Unit
block and connection diagrams
Dual-In-Line Package
r-------- ----,
I/O DATA BUS
I
I
I
I
I
I
Dun 2
01(6)
lDO WORDS MICROINSTRUCTION
(MICRO-IROGRAM STORAGE)
23 NFLEN
J
2Z HDeSH
21
01(6) 4
LOC.SH
01(41
5
211 NC8(0)
IGND)V LL
6
19 Nellz)
01(3)1
18 HClln
01(1)
17 NC8(3)
a
16 ~,
01/21'0
""
DUO)
READ ONLY MEMORY
24 VGG I-!2V!
ruCND
ENCTL 11
(+5V1 Vss 12
13 ¢1
'--~---'
TOP VIEW
Order Number IMP-16A1521D U6-bit std. CROMI.
IMP-16A/522D (16-bit extended CROMI. or
IMP-SA/521D (S-I>it std. CROMI
See Package 6
,,,....
CO,OITlONAl .IU .....
INTERRUPTI
12-14
AALU CONTROL
Order Number IMP-16A1521N (16-bit std. CROMI.
IMP-16A/522N U6-bit extended CROM). or
IMP-8A1521N (S-bit std. CROM)
See Package 1S
s:
s:
absolute maximum ratings
U1
.....
...
U1
All Input or Output Voltages With Respect
to Most Positive Supply Voltage (V ss )
Operating Temperature Range
Storage Temperature
Power Dissipation
+O.3V to -20V
O°C to +70°C
-65°C to +150°C
1W Maximum at +25°C
Note: Maximum ratings indicate limits beyond which permanent damage may occur. Continuous operation at these limits
is not intended and should be limited to those conditions specified under de electrical characteristics.
electrical characteristics
PARAMETER
CONDITIONS
Logic "1" Input (MOS and TTL) (V 1N (1d (Note 1)
MIN
INote 21
TYP
MAX
(Note 21
UNITS
V
Vss - 0.8
Logic "0" Input (MOS) (V1Nmd
V ss -7.0
V
Logic "0" Input (TTL)
vss - 4.0
V
(VIN(O))
Logic "0" Input Current (TTL) (1 IN
(O)l
Input Leakage Current (MOS) (I d
VIN
c::
OV
VIN "" +5.0 to -12V
Logic "1" Output (MOS) (V OUT (l))
-1.75
mA
±1.0
pA
V
Vss - 0.4
Vss - 8.0
Logic "0" Output (MOS) (V OUTW )}
Logic "1" Output (TTL) (V OUT (l))
lOUT'"
Logic "0" Output (TTL) (VouTwd
lOUT = -2.0 mA (Note 3)
Pull-up Transistor "on" Resistance (RpULL_UP) (Note 1)
V IN
:=;
0.2 mA
Vss -1.0V
2.4
V
V
3.0
0.4
V
5.0
kl1
01(01 - 01(71 Input Capacitance (Csi
VIN '" V ss , fT "" 700 kHz
5.0
10
pF
NJCNO, ENCTL, LOCSH, HOCSH Input Capacitance
VIN
11
14
pF
Clock Input Capacitance (C e )
VIN '" V ss , fT = 700 kHz
40
60
pF
=
Vss. fT = 700 kHz
30
Clock "1" Level (Vrp(1))(Note 4)
Vss - 1.0
Vss
V
Clock "0" Level (V rpWl)
VGG -1.0
VGG+l.0
V
25
22
20
50
pF
pF
pF
pF
850
mW
Load Capacitance For 01(01. (11, (21, (31 ICLI
HOCSH, LOCSH
ENCTL.NFLEN
NCB(OI. (11, (21. (31
Power Dissipation (PD) (T 1 - T 8 Equal Width)
Note 1:
Note 2:
Note 3:
Note 4:
f" 700 kHz
600
Internal pullup provided for TTL inputs. Refer to Figure 3 and text.
Max. = most positive; Min. = most negative.
lOUT = -1.6 mA for NFLEN (Pin 23),
Clamp diodes and series damping resistors may be required to prevent clock overshoot.
12-15
FUNCTIONAL DESCRIPTION
directly in microcode. In cases where larger programs are desired, up to four CRaM chips may
be used in a single processor. (CROM's which
implement 8- and 16-bit instruction sets are
available as standard products.)
A block diagram of the Control and Read Only
Memory (CRaM) chip is shown in Figure 1.
The ROM provides storage for one-hundred 23-bit
microinstructions. This is sufficient to implement a macroinstruction set comparable to many
mini-computers, or to provide a control program
V. (+&VI
,.---'==="'----<,
(]:>--
VLlIGIID)
£I:>-
VQG (-12VI
(!!)o--
.,[D--.. [D--.. [D--.. [D---
JUMPIFLAG
ADDRESS
FIGURE 1. CROM Block Diagram
TABLE I. IMP Microinstruction Word Formats
ARITHMETIC INSTRUCTIONS
CONTROL
•
A
R
ADP
SHIFT
CONTROL
110 INSTRUCTIONS
1'.,.2., · ,.. 1' .... 1"."."1"."."."1"1''1'.."."'' 1
CONTROL
JUMP INSTRUCTIONS
12-16
ROUT
RIN
FADDR
Sf RF
CONTROL
NJCNO
A simplified version of the ROM bit functions is
indicated in Table I. For explanation purposes
the functions have been divided into three classes.
The class is specified by the control fields, which
are also used for special functions. The arithmetic
class allows specification of the registers to be
loaded on the A and B·bus of the RALU, the
ALU operation to be performed (AOPI, a shift
operation and the register to be loaded from the
R-bus. The I/O class provides fields for addressing
a register for data output and a register for data
input as well as setting (SF I and/or resetting
(RFI one of 16 external control flags to indicate
the type of I/O transfer. The microinstruction
jump class provides a 9-bit address field, selection
of up to 16 jump conditions (JCONDI, an unconditional jump command (JUCI and specification of
a subroutine jump or return (JSR/RETI. (The
jump condition and flag logic is provided off
the chip to save pins. Standard product bipolar
MSI circuits are available which provide eight
control flags in a single addressable latch and 8 or
16 jump conditions with a single multiplexer. I
The ROM has 9 programmable address inputs
which come from the ROM address register (RARI.
The RAR is a 9-bit synchronous counter with
parallel load inputs which normally counts sequentially through ROM addresses. When a program
branch is desired the contents of the RAR may be
altered by parallel loading from one of several
sources. One possibility is to load an address
specified by the microcode stored in the ROM.
This may be either a conditional or unconditional
branch. Conditional branches are controlled by
the jump condition input (NJCNDI. An external
jump condition multiplexer drives NJCND and
may apply one of up to 16 conditions to the
input. The condition applied is selected by the
jump/flag address which is sent out over pins 01 (01,
(11, (21. and (31 at the beginning of each microinstruction cycle. The RAR may also be loaded
from the subroutine address register (SRAI. This
register is loaded from the RAR if a jump to
subroutine is specified by the microcode. The
SRA is loaded back into the RAR when a return
from subroutine is executed. There are two programmable addresses which may be loaded into
the RAR. These are the address of the instruction
fetch routine, which will be loaded into the RAR
when a new macroinstruction is to be "fetched"
from the system memory, and the address of the
initialize routine, which will be loaded when the
power is turned on. The final method of loading the
RAR is from the CRaM instruction register (CI RI.
This register is loaded from external memory,
or an I/O device, with a macroinstruction to be
executed. The CI R is loaded into the RAR as
commanded by the microprogrammed "fetch"
routine. The CI R bits are masked by the outputs
of the Address Control ROM (ACRI before being
loaded into the RAR. The masking is used to set
bits which are not part of the instruction opcode
to zero. There are 12 masks available; the one used
is selected by the current contents of the CI R
(Le., each instruction selects its own mask). The
selection code and masks are both programmable.
The HOCSH and LOCSH (High and Low Order
Carry/Shift) signals are used to implement carry
and shift operations. LOCSH is used to provide a
low order carry in for the ALU. This is useful for
incrementing, two's complementing a number or
emitting (serial) bit patterns to the ALU. During
circular shift operations HOCSH and LOCSH are
tied together by an internal transistor, allowing
shifts to propagate between the most and least
significant ALU bits. In the case of open shifts
the HOCSH and LOCSH pins provide trailing
zeroes to be shifted into the ALU.
Control information from the CRaM to the RALU
is sent over four time-multiplexed lines (NCB(OI,
(11, (2), and (3)). Four 4-bit commands are sent
each microinstruction cycle. These lines go to all
RALU chips in parallel. The enable control pin
(ENCTL) and the chip enable circuitry are used
for systems having more than one CRaM (for
microprograms with more than 100 wordsl.
Details of signal fu.nctions and timing are presented
in the following sections. Positive true logic signals
are used (" 1" = more positive Voltage, "0" = more
negative voltagel. Signal names beginning with N
are complemented signals.
FUNCTIONAL DESCRIPTION OF SIGNALS
The timing diagram (Figure 2) is divided into 8
time intervals (T, - Tal based on the 4-phase nonoverlapping clocks. The clock inputs have MaS
levels of +5V and -12V and occur during the odd
time intervals. Thus phase 1 is a logic "0" (-12VI
during T, and a logic "1" (+5VI during T2 - Ta.
Commands
The command outputs to the RALU occur on pins
20, 18, 19, and 17 which correspond to command
bits NCB(O), (11. (2), and (3). The command outputs are complemented MaS signals and are multiplexed over the 4 odd time intervals in each cycle
(T" T 3 , T 5 , T 7 ). Outputs are driven negative. to
logic "0" during the even time intervals. The
command functions for each bit are indicated in
the diagram. During T, , the three least significant
command bits specify the address of the register
to be loaded onto the A-bus. Registers R, - R7 are
addressed by binary values of 1 - 7 respectively, A
value of zero causes the A-bus to be set equal to
zero. The fourth command bit is used to enable
stack operations, If NCB(3) is at a logic" 1" (most
positive level) no stack operation occurs, If it is at
a logic "0" stack operations are enabled, but will
only occur if the A or R-bus address is zero. If
the A-bus address is zero the stack wi II be pulled
onto the A-bus. If the R-bus address is zero, the
R-bus will be pushed onto the stack.
12-17
SIGNALS
(Note 1)
s;LJl.C!§
.,
..
..
0,
LOGIC
LEVELS
MOS
MOS
'T3
T2
~
T4
~
T5
T6
~
T7
~
T8
~
"--./
MOS
PIN
FUNCTION
" ,----
PIN
NO,
INPUT
16
INPUT
I.
INPUT
~
MOS
~
JlAI8.
TIME INTERVALS
T1
"
INPUT
13
20
NCBIO)
MOS
Ali
"0"
D1l
"0"
Al:lJlj
"0"
~
"0"
OUTPUT
NCBIl)
MOS
Ai
"0"
iii
"0"
ALUl
"0"
AT
"0"
OUTPUT
18
NCB(2)
MOS
A'i
"0"
~
"0"
"0"
R!!
"0"
OUTPUT
19
NCB(3)
MOS
Si'ACK
"0"
COMP
"0"
"0"
OUTPUT
17
DI(0).11I.12).13)
TTL
J/FL
ADDR
lOUT)
DC
I/O
9,8,10,7
DC
INPUT
5,4,3.2
DI(4).15).16).(7)
TTL
ENCTL
MaS
NFLEN
TTL
NJCND
TTL
HOCSH
MaS
CONTROL
.M!§£
LOCSH
MaS
"0"
lOUT)
I---
I-;;
DC
I
i7B
"0"
==:j
DATA
IINPUT)
DON'T CARE
JFETCH liN/OUT)
I-- JCOND
OVCEN
lOUT)
DON'T CARE INPUTIDC)
Si'i:G I..
"'"
=
em
lOUT)
DATA
.. I ..
"I"
.. I(N~~~. 3)
I "'" I-
UNSPECIFIED OUTPUT ____
- - - l I!FTIr I - - "1" _ _ _
--l
DON'T CARE IDC)
liN)
I
INo"
HIGH2)
IMPEDANCE
---l
~"'" ( I N J - + LOlOUT)
. CARRY ..-1
"1"
lOUT)
"1"
lOUT)
11
OUTPUT
23
INPUT
1
SH'iFfO/O)
I/O
22
SHm'1I/0)
I/O
21
DATA
I
I
I/O
I
DC
._-Note 1: A positive true logic convention is used for all Signals except clocks. Signal names beginning With N are complemented
signals.
Note 2: HOCSH at T4 and T5 is in the TRI-STATE high impedance output mode of CRaM load drivers.
Note 3: "I" (OUT) means CROM is driving this node to the logic "1"level during the defined interval. For I/O lines the logic
state is defined as "in" or "out." I"put or output nodes are defined only as "1" or "0."
FIGURE 2. CROM Timing Diagram
During T 3 the three least significant, bits specify
the address of the register (R , - R7 ) to be loaded
on the B-bus. The most significant bit specifies
that the A-bus is to be complemented when it is
transferred to the lA-bus. During T 5 NCB(1) and
NCB(O) specify the ALU operation to be performed. while NCB(3) and NCB(2) are used to
specify control functions,
During T 7 the three least significant bits specify
the address of the register (R 1 - R7 ) to be loaded
from the R-bus. The most significant bit specifies
that the R-bus is to be set equal to the output of
the I/O multiplexer rather than the shifter.
Control Signals
The enable control (ENCTL) is a "wired-or" signal
line required for operation of multiple CROM's.
It provides a logic "1" output at T2 - T4 whenever
a branch to the instruction fetch routine occurs.
and responds to a logic" 1" input at T 2 - T 4 by
executing a branch to the instruction fetch routine
and disabling if the instruction has not been
implemented in that particular CROM. The flag
enable (N F LEN) control output is used to set or
reset flags addressed by DI (0) - DI(3) at Tl of the
current cycle. A logic "0" output at T 2 specifies
setting of the addressed flag while a logic "0"
output at T 6 specifies resetting.
Data
Miscellaneous Signals
Instructions to the CRaM are transferred over the
data input lines (DI(O) - DI(7)) into bits 0 - 7 of
the CI R. (Bit 8 of the CI R is loaded from the
NJCND input.) Data input occurs at T 7' As with
all TTL inputs on the CRaM a 3k - 5k pull-up is
provided on the chip to insure an adequate logic
"1" level (see Figure 3). The pull-up is provided
by' an MOS transistor which is turned on only
during the data input interval (T1)' At other times
it is in the "off" or high impedance state. Signal
lines DI (0) - DI (3) are also used to output a 4-bit
address to the control flags and jump conditions.
This address output becomes valid during T 1 and
must be stored in an external latch at the end of
T1 ·
12-18
The jump condition input line (NJCND) is used to
input conditional branch information at T 1 and
T2 as specified by the jump condition addressed by
DI (0) - DI (3) at T l' If the input is a logic "0"
and a conditional branch has been specified for
the current cycle, a branch will occur. The NJCND
input is also used to load data into CIR(8) at T 7 •
The high and low order carry/shift lines (HOCSH
and LOCSH) are used to provide shift and carry
information to the RALU chips. If a circular shift
has been specified, HOCSH and LOCSH are connected together on. the CROM during T 7 and T 8
by a low on-resistance MOS transistor switch. For
, - - - - - - - ----v-::--l
~ =>-~"J~",+---lv
-1~
-i
I
m
..' C::=I
.,
v"
NFLEN,
"'''I ill
I
I
I
I
OHO)·
~3)
ONLY
I
I
I
I
I
HOCSH
I
C=::J. . . .~W~r~
I
I
I
I
I
I
I
i
~
.~
~ _____ ~ ___ ~_~m~O~KJ
I
Note: Input protection on all inputs.
FIGURE 3. CRDM Driver and Receiver Buffer
the case of a circular left shift HOCSH serves as an
input driven by the most significant RALU and
LOCSH serves as an output to the least significant
RALU and follows the voltage input at HOCSH.
The direction of data transfer is reversed for circular
right shift. In the case of open ended shifts the
CROM output (LOSCH for left shift and HOCSH
for right shift) provides a logic "1" to the RALU
(since the shift data is complemented this will pro·
vide a trailing "0" for the shift operation) and
ignores the shift input data from the RALU. The
carry input to the least significant RALU is provided by LOCSH at T4 and T 5. The overflow and
carry flags on the RALU are enabled by the output
of HOCSH at T,. A logic "1" input is required to
HOCSHatT3 . Thisline is precharged to a logic "1"
at T 2. A logic" 1" input is requ ired for LOCSH at T 2
and T 3. The LOCSH input will be precharged to a
logic "1" at T, when connected to CSHO of an
RALU.
SIGNAL TIMING SPECIFICATIONS
The timing specifications for all CROM signals
are shown in Figure 4. These specifications apply
over the complete range of recommended operating conditions. Time intervals are defined with
respect to the 10% and 90% points of the four
MOS clock inputs. The command outputs on
the NCB bus become valid within the first
85 ns of the odd time intervals. These lines
are driven to a logic zero within the first 85 ns
of the even time intervals. The jump condition
and flag address outputs on DI(O) - D1(3)
become valid within the first 80 ns of T, and
remain valid for at least 10 ns after the 90%
point at the end of T,. Data inputs to all
DI lines must be valid for at least the last
35 ns of T 7 and must remain valid until the
10% point at the start of T8. Timing for the
remaining signals is similar. (Note that signals may
not change state during "valid" time intervals.)
12-19
T2
10% 80%
T5
T4
T3
90%10%
10%9Il'10
90%10%
T6
10%90%
T8
T1
10%90%
900/. UI%
90% 10%
I
"
'.
140nsMIN
-[\
130 ns MIN
/
"
~
85m
115ns
MAX
MAX
I
J/FL
AOOR
01(0),(1),(21.(3)
r\
~t
T1
IIIC8jO), 111, (2), (31
"
-
f-
~'l
'.
140 ns MHI
V
"
TJ
~D
85n.
MAX
130nsMIN
"
-
f-
'.
140 lIS MIN
[\
~
I
MAX
1\
/
"
I
T7
COMMAND
·r
f
~
8~
'.
140nsMIN
"
-
I-
I
~D
85n.
130nsMIN
V
"
T5
MAX
10%80%
I
n.
A
13DnsMIN
-
~
MAX
~~.
INPUT
VALJ~
80n.
MAX
35ns
MIN
IOns
MIN
I
I
I
I
DATA
INPUT
1
01(4)'(5),(6),(71
35n.
MIN
I
ENCTt
~
MAX
IJOns
MAX
OUT
I
I
I
I
OUTPUT DATA VALID
VALID INPUT REQUIRED1
~
.IN
I
flESETVALlD
SET VAllO
.~
-""'--
60ns
~
NFLEN
~
MAX
15nl
150s
~!"....
.~
fiOns
MAX
'5ns
'50S
r-"f'-
r-"f"--,
NJCND
3D.
MAX
~
35nl
HOCSH
~
I
Dvm
"1"
''1''
"1"
~ ~
105ns
MAX
~
~''-
IOns
MAX
80ns
35ns
MIN
MAX
,.
"'"
"I"
LOCSH
~
MIN
CARRY OUTPUT
~
MAX
~
lOnl
MAX
T ~ PERIOD z 10jJsMAX
Note 1: 1:, and If '" 250 ns max.
Note 2: Rotate inpot valid 130 ns max.
Note 3: Rotale output valid 80 ns min.
FIGURE 4. CROM Signal Timing Specifications
ITA =O°C to +70°C, Vss = +5V ±5%, VGG = -12V ±5%, VLL = GND)
12-20
DATA
INPUT
~~
JCOND VALID
~
45ns
-~
SHIFT
~
~
~~
~
MAX
OUTPUT
l>
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,,:.
Applicati,on Notes/Briefs
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CD
II)
o
til
The largest MOS ROMs mass produced last year
stored 1024 and 2048 bits-general purpose sizes
used for table lookup, microprogramming and
random-logic functions as well as character generation. A typical generator contained three 1024-bit
ROMs, such as National Semiconductor's SK0001
and SK0002 kits (see Table 1 and Figures 2 and
31. Generating the standard 64 ASCII-selected
characters in a 5 x 7 font requires a storage capac-
TUBE
""
3
MaS ROMS AND REGISTERS
!~Ap~-~~r~
{FlJTUAE)
VECTOR
DISPLAYS
TYPEWRITERS
&TELE·PRINTERS
{IIAMMEROR BALL)
TAPE PUNCHES
& PRINTERS
THERMAL,
~~~CTROSTATIC.
flUORESCENT
DISPLAY
LE_LlGllT_EMITTING
El-ELECTRilLUMINESCENT
Figure 1. Display Family Tree
13-1
ity of at least 5 x 7 x 64. Each logical "1" bit
stored in the ROM produces a black dot on a
printout or a bright spot on a CRT screen, and
each "a" bit a blank space.
.
..
...
II)
Table 1.
(,)
ca
ca
ROM Combinations for Various Fonts
PARTS REQUIRED
FONT
CHARACTERISTICS
(J
5x7
Raster Scan
SKOOOl
or MM5240
S
7x5
Vertical Scan
static ROM required
SKOOO2
or MM5241
.t:
7x9
Raster Scan
MM5241
9x7
Vertical Scan
static ROM required
MM5240
8)( 10
Raster Scan
MM5241
10 x 8
Vertical Scan
MM5240
.t:
(,)
(2 required)
.
ca
o
Q.
Q.
(2 required)
(2 required)
«
III
E
9
X
11
static ROM required
(2 required)
Raster Scan
MM5240
(3 required)
SIII
11 x 9
Vertical Scan
static ROM required
MM5241
(3 required)
tJ)
12 x 16
Raster Scan
MM523
>
(6 required)
II)
16 x 12
.t:
I-
Vertical Scan
static ROM required
MM5241
(4 required)
oq-
Two new soon-to-be-announced ROMs are the
MM5240, storing 64 x 8 x 5 bits, and the MM5241
storing 64 x 6 x 8 bits. Each chip also contains
decoding logic and sense amplifiers (as do the
1024 and 2048-bit chips). Thus, one ROM is
ample for a standard 5 x 7 or 7 x 5 font. The
added capacity can implement special needs, such
as dropping comma tails below the other characters and symbols. But its main purpose is in
providing the logic and programming flexibility
that enables ROMs to be operated in tandem to
generate the larger font sizes indicated in Table 1.
The additional capacity costs little in· terms of
silicon real estate because these devices are made
by low-threshold processes with p-channelenhancement mode MOSFETs as the storage
elements-the most LSI-able type of MOS.
In the past, when diode matrixes were used as
character generators, the 5 x 7 or 7 x 5 fonts gave
the best cost/legibility tradeoff. Because the new
ROMs lower the cost per function, the 8 x 10 font
will probably become the most attractive.
The input-output configurations of the MM5240
and MM5241 are outlined in Figure 4 for a standard ASCII-addressed font. The 6-bit ASCII code
words will address any of 64 characters (2 6 ). The
control logic generates the three additional address
8'~12J4S
I
B2,,:~gg:
Z
«
83 ---- • • 00.
B.~.O.O.
8s
--:gg::
8./.000.
o,/"
All GATES ARE
DM80000R OM8810
LINE RATE
CLOCK INPUT
UNESElECTCDUNTER
Figure 2a. Three-ROM Raster Scan Character Generators
13-2
Figure 2b. Character Generator For Tape Printers and
Other Vertical Scan Applications
»
z
~
CHARACTER SELECT
I,
0
0
·0
0
I,
0
0
0
0
I,
0
0
I,
0
,
CHAR.
0
8
ROW
15 16
,
0
•
0
0
0
0
0
,
,
,
0
2
'0
6
,.
,
,
,
0
'2
,
0
,
,
,
,
,
0
0
0
0
,
,
,
0
,
,
9
5
'3
0
,
0
,
0
,
,
,
0
0
0
3
,
,
"
,
,
,
o
,
-I
,
,
0
,
7
'5
:::T
CD
C/)
COLUMN ADDRESS
INPUTS
CD
CHIPENA8LE
LINE SELECT
Figure 5. Basic Digital Character Generator and CRT
Refresh Memory
.r:.
I-
Figure 4b. MM5241 Vertical Scan Character Generator
o
Element
•
I
5 x 7 x 64 dot matrix. The output bits forming
each dot line or column are presented in parallel.
The parallel outputs are serialized by a TTL regis·
ter and used to control the CRT beam or the
printer mechanism. To simplify the selection
process, the ROMs are programmed to generate
the lines or columns in the correct sequence when
addressed by the sequential outputs of a TTL
counter.
Z
control logic:-preferably TTL MSI devices such as
single-chip binary counters and B-bit parallelinput/serial-output shift registers-were not used,
the character generating process would be slowed
excessively_ This would limit the number of characters that could be displayed in a CRT refresh
cycle or printed out in a given time. The new
generation of MOS ROMs can deliver up to eight
bits in parallel in about 700 nanoseconds, compared with a microsecond or more for last year's
models. Logic speeds around 10 MHz are therefore
desirable (several times higher than the speed that
can be achieved by MOS gates. I Likewise, dynamic
registers can now easily be run at rates above
2 MHz-double the speed of early mass produced
registers-so the logic controlling refresh storages
must also be faster.
Z,
As before, coded data from a communications link
or the console keyboard passes through the registers and addresses the character generator. In these
examples, the 6-bit ASCII input and the 3-bit
control logic input generate raster scan character
formats that allow a conventional TV monitor to
be used as a display. Communications codes other
than ASCII can be used.
.
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The improved compatibility and higher speed are
largely due to better design and processing of the
input and output stages of the registers and the
sense amplifiers of the ROMs. They don't increase
the complexity of the MOS circuitry, unlike other
techniques for increasing MOS speed, and therefore they have permitted the capacity increases
cited.
'::f'
MlOOP
r+
o
N lOOP
DATA
INPUT
\6 BITS)
(")
'::f'
...
Q)
Q)
(')
r+
...
CD
The net benefit to the system designer of this
approach to MOS design is that it enables the
system designer to capitalize on the best features
of each technology-MOS storage for high density
and low cost, and TTL for high speed processing
of data and control signals. This is what produces
lowest cost per function in most digital systems.
CRT RASTER SCAN DISPLAYS
The basic refresh mode in Figure 5 limits the
number of characters that can be displayed. A
better way of generating and refreshing raster scan
displays, particularly those with many rows or
lines of characters, is outlined in Figure 6. Figure 7
illustrates the timing and logical implementation
for a multiple row system.
G')
LINE
SELECT
CD
:::J
CD
...
o...
Figure 6. (M-N)+N Technique for Large Page Displays
Q)
r+
The refresh memory registers are divided into M-N
and N sections to facilitate page displays. M is the
total number of characters displayed in several
rows (lines of the pagel and N is the number of
characters in each row. To form such a display
with single-loop registers, as in Figure 5, would
take seven recirculations of all M data words
during each refresh cycle of the CRT. The technique in Figures 6 and 7 only requires high speed
recirculation of N bits at a time, with advantages
that will be discussed shortly.
VI
PARALLEL
INPUl
INPUT
DATA
*Used only for multiple character line solutions.
Where: m character words is the total display field
n character words is line display requirement.
Figure 7. Multiple Row Raster Scan Display System
13-5
...
...
III
....ocu
Assume that on the first sweep of the CRT beam,
the ROM is being addressed by the six register
outputs representing characters N 1, N 2 , N J, etc.
The first horizontal, 5·dot line of each character in
the display row are displayed in sequence. Then
the line address inputs to the ROM from the can·
trol logic change to their second state at the time
that N 1 has completed its recirculation to the N
register's outputs. Thus, on the second CRT
sweep, the second series of 5·dot lines are displayed horizontally for all N characters. At the
end of seven recirculations, the complete row of N
characters is on the display.
(I)
r::::
(I)
e"
...
....Q
(I)
...
cu
cu
.s:
(,)
....o
.s:
Q
Now, the contents of the N register are not returned to the input of the N register. Instead, they
are fed back to the input of the M-N register and
this register is clocked to load the N register with
the second group of N characters. The M-N register
is then held still while the N register recirculates
seven times to generate the second row of characters on the display. After all M characters are on
the display, the first group of N characters is
reloaded into the N register and the entire process
is repeated to refresh the display.
cu
...oQ.
Q.
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III
E
(I)
....III
>
CI)
(I)
.s:
Human factors-chiefly the eye's response timedictate that the display be refreshed at least 30 to
35 times a second for good legibility. Most designers prefer to refresh at 60 Hz power line frequency because it is generally the most convenient
frequency.
~
o
-=t,
Z
«
Besides generating the line address inputs (that is,
the number of recirculations of the N register), the
control logic keeps track of the number of dots
and spaces in he output bit stream. The spaces
between characters in a display row are inserted as
"0" bits when the ROM outputs are serialized by
the TTL register. The counters also control the
loading and recirculations of the MaS registers in
the refresh memory subsystem.
A multiple row raster scan display could be generated with the M-Ioop technique in Figure 5 but,
the implementation is difficult and impractical.
This technique is more appropriate for single row
displays. Using this method of display, all M characters to be displayed must recirculate seven times
to generate a 5 x 7 horizontal scan, so all stages of
the registers must operate at the full character
rate. To form several rows with a single-loop
memory requires an interlaced scan rather than an
ordinary raster scan. The first series of 5-dot lines
are generated by the first N character outputs as
before, but the next set of N inputs to the ROM
will generate the first group of 5-dot lines in the
second row of characters on the display. Therefore, the beam must jump to the new line position.
To display four rows of 5 x 7 characters, for
instance, would require a staircase generator that
would step the beam by the height of nine scan
lines (seven dot lines, plus two blank spacing lines
between rows) three times after the initial scan.
13-6
Then, as the second of the seven recirculations
begins, the beam would have to be shifted an
additional line to start the second series of line
scans-and so forth.
The M-N-N technique does not require any more
register stages than the M-Ioop technique and
significantly reduces control and drive circuit
requirements-again producing a lower cost per
function.
REFRESH MEMORY MODULATION
The technique employed in the M-N-N refresh
memory is called "clock modulation". In other
applications, it has already been found to significantly reduce total storage costs.' It helps minimize power dissipation-in most terminals, the
amount of power consumed is unimportant in
itself since line power is used, but registers are
powered by clock drivers and the cost and complexity of the drive network is certainly important. Furthermore, the technique allows long, very
high-density MaS circuits, produced by relatively
inexpensive low threshold (bipolar compatible)
processes to operate at very high effective character rates.
As shown in Figure 7, the raster scan system uses
nine clock intervals to generate a row of characters
on the display. Seven are for the high-speed recirculations. During the other two intervals, the
first N characters are fed back from the output of
the N register to the input of the M-N register
while the N register is loaded from the M-N register with a new row's worth of characters. Since
two intervals are used for this operation, the registers operate at only half the character rate. The
rest of the time, the M-N register is chargequiescent. Its average clock frequency is only
about 11 % of the character rate.
I n other words, most of the refresh memory
(perhaps 90% in a large display system) operates at
only half the character rate (say 1 MHz instead of
2 MHz) only two-ninths of the time. The savings in
the drive network alone can be judged from the
power-frequency plot for a typical MaS dynamic
register (Figure 8)3. In addition, the designer can
i="
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15V
ftI
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ffio.o"~iimE
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0.0001
I
10
100
1,000
MAXIMUM OPERATING FREQUENCY (KHz)
Figure 8. Power
vs Frequency Plot of Typical
MOS
Dynamic Register
increase the number of characters generated per
refresh cycle, for a larger display, or increase the
number of dot lines, for a larger font, or both.
»
z
Remember, though, that dynamic registers must
be clocked to retain data. How long can the M·N
register be turned ofF Long enough for practical
applications. The guaranteed minimum frequency
is temperature dependent, since temperature
affects charge-storage time. The minimum for
National Semiconductor's MM-series registers is
500 Hz at 25°C, rising to 3 kHz at 70°C (maximum operating temperature is 125°C, but that is
not a display environment). At room temperature,
the registers can safely be quiescent for as long as
2 msec. (The typical MM register will actually hold
data for 10 msec.) Suppose the N register stores 40
characters and operates at 2 MHz. The quiescent
period can be as short as 40 x 7 x 0.5 = 140 /-IS. If
standard TV raster timing is maintained then the
quiescent period will be 7 x 63 /-IS = 441 /-IS.
Obviously, the designer has great leeway in character rates, operating temperatures, and register
capacities.
Other applications in displays for clock modulation include input-output buffering of data during
data reception and transmission,2 or during display editing and formatting through the console
keyboard. The register rates can be adjusted via
control logic to accommodate differences between
1/0 and recirculation rates. Note that the gating in
Figure 7 permits data entry under TTL control
into either register section.
CHARACTER GENERATION
The first generally available MOS character generators were kits such as those in Figure 2, using
three 1024-bit ROMs (MM521). Although singlechip generators were being developed in 1969,
they were in very short supply. The kits cost about
half as much as diode generators and thus allowed
terminal manufacturers to start the changeover to
MOS.
The kits are also a good place to begin describing
character generator operation in this appl ication
note, because they provide an "exploded view" of
multi-ROM generator operation. Similar techniques will be needed to build larger fonts with the
new devices. The external gating functions shown
in Figure 2 are not needed for these fonts when
the MM5240 and MM5241 are used. The "assembly" of the dot patterns is taken care of in the
programming of the ROMs. However, to generate a
large font, such as 8 x 10 or 12 x 16, with the new
ROMs will require operation of two to four ROMs.
The 6-bit ASCII code was devised to select 64 (2 6 )
characters. However, an 8-bit address is used to
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The MK003 is continuously enabled by grounding
the chip-enabled pin, CEo It must generate a 1-bit
output for each of the 7 x 64 dot lines in the
64-character set, which implies a 9-bit address.
Rather than produce a special ROM just for this
function-which would make it expensive-the
MM521 was programmed to generate 2562-bit
outputs from the 8-bit address. The counter's C
output simply gates out the unwanted bit.
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For a 5 x 7 font, the new single-chip character
generators are simply programmed to generate all
5 bits in each dot line, from a 9-bit address. Standard programming provides the 64-character
ASCII set, but special characters can be substituted by changing the stored dot patterns. The
reprogramming process consists of altering an
etching mask that controls gate insultation thickness in the MOS field effect transistors of the
storage array. If the oxide is left thick, the transistor will not switch when selected by the decoding
logic, generating a "0" output from that location.
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MM5240 is 5 x 8 x 64 rather than 5 x 7 x 64-each
ROM can generate half of the 8 x 10 x 64 character set. The ROMs can be addressed simultaneously, as before, and be commutated by the
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Each MM521 in the SK0001 raster scan kit can
store 256 4-bit dot patterns. As the inset letter
"N" in Figure 2a indicates, the MK001 ROM
stores the first four 4-dot line segments of each of
the 5 x 7 characters, the MK002 stores 4-bit
segments of the other three-dot lines, and MK003
supplies the fifth bit of each of the seven-dot lines.
All ROMs are addressed simultaneously.
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select the dot lines and the 6-bit ASCII code from
the 256 (2") word locations in each ROM. These
two additional bits dre supplied by the A and B
outputs of a TTL binary counter
DM8533 (SN7493) and the counter's C output is
used to commutate the MK001 and MK002. The
ROMs are enabled by an output at the TTL logical
"0" level. Thus, with the gating shown, the
MK001 is enabled during the first four of seven
line-rate clock inputs and the MK002 during the
remaining three inputs.
MM5241
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Figure 9. Multiple ROM Character Fonts
control logic to put out the 8-dot horizontal lines
in the correct sequence. For very high speed character generation, the addressing of the ROMs can
be skewed or overlapped so that the outputs from
one are generated while the inputs to the other are
being decoded. The only real limitations to the
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character generation rates achievable with such
techniques are the speed of the bit serializing logic
and the bandwidth of the video circuitry_
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the DM8533 TTL binary counter will reset on the
count of 16_ And with the gating and interconnections shown, the column select cycle is:
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ROMs Enabled
DCB
000
001
010
011
100
101
MK004
MK005
MK004
MK005
MK006
reset (instantaneous)
Starting with the dot/character or dot and space
counter in Figure 7, the counter moduli are set to
accomplish the following functions:
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• The dot and space counter determines the number of horizontal spacing bits between characters in the character row on the display_ Its
output is loaded into the parallel inputs of the
DM8590 serial-in/parallel-out shift register. For
a 5 x 7 font, for example, a modulus of six
inserts one spacing bit (logical "0" bit) between
each 5-dot group in the serialized stream_
During line recirculation periods, this counter
also drives the N counter at the character shift
rate of the N register.
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the three address bits that sequence dot·line
selection from the ROM.
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raster-scan displays to keep track of which page
line has just been generated. This time is signified by the C or D output of the line select
counter.
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which is apparent is that the sequencing of the
character generator is different in each of the two
basic techniques. In one case the character generator is sequenced at the character rate (raster scan)
while in the other case the generator element is
sequenced at the column rate (vertical scan) of the
font.
Since a display utilizing the vertical scan techniques has input address changes at some multiple
of the display character rate, a clocking system for
a dynamic ROM character generator must be
supplied. This requires the addition of a frequency
divider and Clock generator which results in a
higher system cost when dynamic ROMs are used.
A second consideration which should not be overlooked in systems cost is the compatibil ity of
ROMs in mUlti-package character fonts. Optimum
ROM usage and organization will result in lower
systems cost. ROMs will also find applications in
micro-programming and code conversion where
synchronous operation is preferred.
The 8 x 10 font is much better and 12 x 16 is
almost optimum for legibility. Small, lower case
characters can be sharply defined, too, and they
almost appear to be drawn with continuous
strokes.
System designers considering these fonts for lowcost displays run, at present, into CRT cost problems. The least expensive displays are televisiontype CRTs with limited video bandwidth. Bandwidth also limits the number of characters that can
be displayed simultaneously. Not counting the
times required for beam retrace and functions
other than character generation:which reduce the
time available in a refresh cycle for dot handling,
the necessary bandwidth is roughly:
The greatest portion of the discussion has dealt
with a 5 x 7 font. A full 64 character display can
be coded into a single MaS package. Now that LSI
has entered the scene, we see a different trend
towards larger, more stylized font. The economy
of MaS ROMs will provide the customer with a
more legible character font at the present cost of
"discrete" character generators. An analysis of the
most practical solutions to various fonts are tabu·
lated in Table 2. The part types which have been
used to generate a 64 x 7 x 5 raster scan font are
the SK0001·3 ROM kit or the MM5240 which is
under development. The vertical scan fontis satisfied by the SK0002-3 ROM bit or the MM5241
which is under development. If we examine the
other possible fonts, these same two monolithic
elements will satisfy the requirements if they were
64 x 8 x 5 and 64 x 6 x 8 respectively. Therefore,
the added memory storage is being incorporated
into the MM5240 and MM5241. In some of these
cases the font is scanned in the horizontal dimension while in others the font is scanned in the
vertical dimension. You find both the 8 x 5 and
6 x 8 elements capable of satisfying the font
matrix requirement. Since all the ROMs listed are
static by design, there are no special clocking hardships induced with the solution of any of these
larger fonts. This is not true for all dynamic ROM
solutions.
TV-type CRTs have a maximum bandwidth of
about 4 MHz, of which only about 2.5 MHz is
generally useful. If one uses a 5 x 7 font with one
spacing bit (6 x 7 total) at a 60-Hz refresh rate,
each displayed character needs 2.52 kHz of bandwidth, so the limit is about 1,000 characters. In
contrast, the new ROMs take as little as 700 nanoseconds to generate a dot line, or about 5 j.1S per
character. That's fast enough to generate 200,000
characters a second, or a display of more than
3,000 characters at the 60-Hz refresh rate. The
actual dot rate in the serial bit stream to the CRT
can approach 10 MHz. And if larger fonts are
generated in some multiplexed addressing mode,
the required bandwidth can be much higher.
As mentioned before and shown in the table, the
same ROM element is used in both raster scan or
vertical scan applications. If we recall the design
solutions showing the refresh memory and character generator for a 5 x 7 display, the first thing
Luckily, these problems are not insurmountable
and there are alternatives to using oscilloscopequal ity C RTs or storage tubes, wh ich are fi ne for
high performance applications but too rich for
low cost terminals.
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BW ~ (dots and spacing bits per character)
X (characters per display row or page)
X (refresh rate)
Obviously, the designer can drop the refresh rates.
New CRT, with longer persistence phosphors
facilitate this. Also, CRT manufacturers have been
responding to the new terminal market by working
on bandwidth improvements, and they are appar·
ently going to reach 10 MHz in moderately priced
video systems soon.
Finally, the designer is not obliged to display his
characters digitally just because he uses a MaS
ROM. Don't forget that the ROM is really working
as a code converter, generating a 35-bit machine
language code from a communications code. The
language translation can be whatever the situation
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The register stages can either shift the bits to the
serial output for recirculation or store the data
indefinitely. Hence, displayed characters can be
swept along a line of indicators, "frozen" on a
stationary display, or made to reappear periodically at any desired repetition rate.
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A code-converting/character-generating ROM can
be placed at the register input, to display numbers
and symbols or alphanumerics. A designer can get
almost as much flexibility from a lamp or panel
display as from a CRT display. In fact, the first
application of the MM5081 is controlling a matrix
of neon lamps in a moving billboard display.
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requires.
All that need be done is update methods used in
analog displays, which form characters with
strokes rather than dot lines or columns. The
ROMs can be programmed such that the bit outputs, when integrated, control X and Y ramp
generators. The slopes of the ramp functions are
determined by the number of bits in a sequence
and the lengths are determined by the locations
chosen for turn-off bits. As in the vertical scan
technique, the ROM is addressed at the character
rate.
Even though some characters can be formed with
one or two strokes (I, L, etc.). equal time should
be given to all characters in a page display to keep
the character rows aligned. A standard sized area
of the MOSFET array, such as 6 x 8 or 5 x 8
should be used for each character. Most patterns
would thus be a combination of stroke and nostroke outputs. The single-chip fonts have an
8-stroke capacity for each of 64 characters which
is more legible than the standard segmented type
of instrument readout, since slant lines could be
generated wherever needed.
APPENDIX
WHAT ABOUT INSTRUMENTS
AND CONTROLS?
While it is safe to predict that 1970 will be "the
year of the MaS" in alphanumeric terminals, MaS
applications in numeric readouts are just beginning
to emerge.
A new device with considerable promise in this
field is a high voltage, MaS static shift register, the
MM5081. Developed by National, it has a TTLcompatible serial input, 10 parallel outputs that
can stand off -55V, 10 latching-type storage
stages, and a serial output.
This novel combination of functions means that
the MM5081 can drive lamps, numeric indicator
tubes, filament tubes in segmented number and
symbols displays, electroluminescent panels, and
the new gas-cell arrays. In short, it provides MaS
with a good foothold on the numeric side of the
readout family tree in Figure 1.
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Some applications for character generators in instruments are also cropping up. Displaying range
scales on an oscilloscope is a good idea that can be
improved upon with the new ROMs. The display
frees the operator of the chores of mentally calculating scale factors and manually writing these on
scope photos. With an alphanumeric font, the
camera can also record information such as test
conditions, date and time of test, identification
numbers, etc. Photo sequences and the data
needed to analyze the curves can be coordinated
automatically.
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Similarly, a ROM can be programmed to display
standard curves for go-no-go equ ipment checkout
operations. For example, if a radar's pulse amplifier should have certain output characteristics, the
ROM generates the correct output curves through
a digital-to-analog converter and stroke generator.
When an actual operating characteristic and the
reference curve are displayed simultaneously, the
operator can tell at a glance whether the radar is
functioning properly. Many curves or general purpose curve segments can be programmed into a
ROM and picked out as needed with selector
switches or a ROM microprogrammer.
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ROMs can be programmed as lookup tables,
random-logic synthesizers,4 encoders, decoders,
and microprogrammers as well as character generators. A single ROM can perform limited combinations of these functions, virtually qualifying it as a
microcomputer. It has been suggested that this
capability be used in control panels to perform
functions like actuating an alarm when a transducer level goes out of range and initiating corrective action. ROM addresses can be derived from
digital meter circuitry. In multi-point measuring
systems, this would provide the solid state equivalent of a rack of meter relays.
DEFINITIONS OF DISPLAY TERMS
Font: A set of printing or display characters of a
particular style and size. A typical dot-character
font is 5 x 7, referring to the number of dot locations per character.
Dot Character: A character formed by a pattern of
bright dots on a CRT screen or dark spots on hard
copy, rather than by continuous strokes. The dot
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pattern corresponds to bit-storage patterns in a
digital memory.
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Column: In a dot character matrix for vertical
scanning, a column is a vertical series of dots. On a
page display, a column contains several vertically
aligned characters. In this article, a column refers
to a dot column.
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Row: A horizontally aligned group of characters
on a display .
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Line: In this report, line refers to the number of
dots displayed in a single scan when a raster scan
character is generated. In a 5 x 7 dot character,
there are seven lines of 5 dots each.
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Page: A display consisting of several rows of characters, corresponding to lines on a printed page.
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Raster Scan: See Figure 9.
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Vertical Scan: Two types of CRT vertical scans are
shown in Figure 10. In hard copy appl ications, the
dots in a column or character may be printed
simultaneously by the printing transducers rather
than being scanned.
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Sawtooth Scan: See Figure 10.
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Pedestal Scan: See Figure 10.
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Dynamic Element: A digital device that must be
clocked. A dynamic shift register must be clocked
to retain data. A dynamic ROM is clocked to
decode the address and generate an output.
Static Element: A device that does not have to be
clocked to retain data. A static ROM uses direct
coupled decoding for bit selection and static output buffers.
REFERENCES
1. A.D. Hughes, Desired Characteristics of Automated Display Consoles, Proc. Society for Information Display, Vol. 10, No.1, Winter, 1969 .
2. Dale Mrazek, MaS Delay Lines, Application
Note AN-25, National Semiconductor, April, 1969.
3. Dale Mrazek, Low Power MaS Clock-Modulated Memory Systems, Application Note AN-19,
National Semiconductor, April, 1969.
4. Floyd Kvamme, Standard Read Only Memories
Complex Logic Design, Electronics,
January 5, 1970.
Simplify
Application Notes/Briefs
HIGH VOLTAGE SHIFT REGISTERS
MOVE DISPLAYS
There was a time when one had to go to Times
Square or Picadilly Circus to see a moving lamp
display. But now they're going into stadium scoreboards, stock brokers' offices, waiting rooms and
many other places where an attention-getting manmachine interface is wanted.
REGISTER PLUS SWITCHES
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Figure 1 shows in simplified form how one
MM5081 would be connected to drive a bank of
10 neon lamps. A data bit stream is entered into
the serial input and shifted at the clock rate to the
serial output. Then, it can be routed back to the
input and recirculated to repeat the display motion.
Naturally, display designers would like to make
the control and drive circuitry more compact and
less expensive. What's needed to replace the banks
of discrete switching devices is storage and switching high-voltage circuits in monolithic form. That's
exactly why National developed the MM5081 highvoltage MaS shift register.
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The states of the data bits circu lating through the
register control the switching of the MaS output
transistors. When a bit in the true state (MaS
logical "1"1 is being stepped down the 10 register
stages, the lamps wili turn on and off in sequence
at the register clock rate_ In this mode, the clock
rate is the display rate. A typical display rate will
move the Iight along by no more than two or
three lamps per second, making any message displayed on parallel rows of lamps easy to follow and
read. A latch-type register cell that can shift at frequencies to DC and a single-phase clock input are
used in the MM5081 to achieve this effect_ However, the logic formatting the data for display will
have to run at some higher rate. If the control
system has other functions as well, it may be
desirable to load the register at a clock rate in the
hundreds of kilohertz_ At such a high rate, the
bit stream flashes by the 10 parallel output
switches too rapidly to see the lamps being turned
on. After loading, when the main system logic is
freed, the clock rate is dropped to the display
rate and the message is seen. The message simply
recirculates at the display rate until new data is
ready for loading.
This unusual IC is the first MaS device capable of
driving gas-discharge tubes and other high-voltage
display elements without going through a bipolar
buffer such as a transistor or SCR. Moreover, it can
"walk" the message around and around the display when operated in a recirculating mode. The
latter feature provides a clear-cut division between
system functions - the MM5081's take on the responsibility of display operation per se, while the
system logic need only format messages and control updating by invading the registers_ In other
words, the main system logic need pay only inter-'
mittent attention to display operation. If the main
system is a data-processing computer, for instance,
it can handle the display like any other peripheral.
Relieved of responsibilities for moving and refreshing the display, the main system can do more data
processing between display updates.
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The use of high-speed logic for control is facilitated by making the MM5081 with low-threshold,
p-channel, enhancement-mode MOS transistors. As
a rule, a low threshold device allows data to be
entered at bipolar logic levels.
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The output transistors do not need a large gate·
voltage change to turn on and off. They are also
low-threshold devices in this sense. But they have
to withstand transients up to 100 volts and stand
off steady state voltages up to 55V to operate
lamp-type displays reliably. Adequate gate logic
voltages for the output transistors must be ensured
to make the lamps glow brightly when they should
be on or to make them free of any residual glow
due to switch leakage when the switching tran·
sistors are turned off. That is, a low RON and high
ROFF must be ensured despite very high voltage
on the MOSFET drains. Because a pullup resistor
is used, the input gate should be a TTL or DTL
device with an uncommitted-collector output able
to withstand at least 10V. Among such devices are
the DM881 0, DM8811 or DM7426 (SN7426) quad
NOR.gates, or the DM8812 hex inverter. All these
TTL devices will stand off to 14V.
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The other two gates used in the input switch can
be any TTL or DTL types. The arrangement shown
brings the serial output back to the serial input
through the top gate when the "new data enable"
line is low (DTLlTTL logical "0") or permits the
registers to be reloaded with new data when the
enable line is high. A pull-down resistor is placed
on the register output to handle 1.6 mA the current sinking required for operation of the TTL or
DTL recirculation control gate.
TICKER-TAPE DISPLAY
A straightforward type of moving lamp display is
illustrated in Figures 2 and 3. Simple messages such
as CALLING DR. CASEY ... CALLING DR.
CASEY ... DR. CASEY, PLEASE REPORT TO
SURGERY ... or stock quotes, or a series of
instrument readings would be displayed as 7X5
characters by this system. That is, each character
would be a lighted lamp pattern selected from a
moving matrix seven lamps high by five lamps
with a moving column of lamps turned off between
characters. The off column is a space bit in each
lamp row.
Assume that the display is long enough for 33
characters. Each row requires 33X6 lamps and
198 register stages. Each row is a cascade of 20
MM5081's. The input of the first register and the
DATA IN
ROWS
DATA IN
ROW}
FIGURE 2. 7XN Bit Shift Register and Display
13-14
output of the last register are connected as in
Figure 1, and the registers in between are simply
daisy-chained by connecting each serial output to
the next serial input. All seven rows would use
140 register packages.
The character data for this type of system can be
formatted by a standard character generator. For
instance, the standard ASCII code can address a
bipolar compatible read-only memory such as
National's MM5241AA, which is programmed to
generate 5X7 dot-type characters for CRT display.
However, in the lamp display system, the display
refresh function is handled without an additional
memory. The column bits are entered in each
register chain, as before, through the input gating
at a rate determined by the clock rate supplied
the MH0025C clock driver. The MH0025C is a
two·phase driver. However, since the MM5081
takes a single-phase clock input (converted to a
two-phase clock inside the register package). only
one of the dual drivers in the MH0025C package
is shown (the other half can be used to share the
clock-drive load).
After the registers are loaded, the clock into the
driver is dropped to a frequency of 2 Hz, if the
register was loaded at a higher frequency. This rate
is stabilized by the coupling capacitor Ce . The
coupling capacitor on this type of driver deter·
mines the maximum pulse width, but the minimum pulse width is established by the clock
signal. So, at the lower frequency, the characters
sweep smoothly from right to left across the display lamps. They repeat the message every 100
seconds because 200 register stages are in each of
the seven parall el rows.
Both the clock driver and the registers operate off
the 10V and -6V power supplied.
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ON
OFF
switch. The purpose is to limit the current and
voltage across the lamps and the MaS output transistors to ensure that they operate reliably and
have long lives. Also, the method reduces power
consumption and allows lower power, inexpensive
high-voltage power supplies to be used.
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The high-voltage switch seen in Figure 3 and
detailed in Figure 4 switches at a rate of 50 Hz and
a duty cycle of 25%. Thus, when any of the MaS
output transistors is on, the lamp that is "on"
during that 250 msec display-rate interval (100%
duty cycle at 2 Hz) is actually on for only 5 msec
at a time. Then it turns off for 15 msec. This refresh rate was chosen because it provides a good
lamp intensity with no apparent flicker.
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FIGURE 4. High Voltage Switch
The -125V supply turns on the lamps, and the
-45V supply turns them off. But what is actually
being used is the voltage difference, or bias. Most
glow-discharge lamps require a 65V starting voltage
and a 60V holding Voltage. The switch keeps the
lamps alternating between these levels while the
MOS transistors are on, but imposes a max imum
voltage of only -65V on the MaS transistors (that
is, 125-60V) for the 5 msec "on" time_ The
MM5081 can easily take this - the spec allows
-100V at 60 Hz (or 16.66 msec) and they are
stress-tested to this level.
INDUSTRIAL DISPLAYS
FIGURE 3. System Block Diagram
DISPLAY DRIVE
The high voltage supply (shown in the block diagram in Figure 3) is generated from a high voltage
The characters displayed can be any kind of
symbol within the resolution of the lamp array from letters to cartoon characters - and within the
flexibility of the controls. Getting patterns to
move back and forth while changing shape is
technically feasible, but would require complex
clocking techniques to put the bits in the desired
location. Static pictorial displays wou Id be fairly
simple to implement, merely requiring loading of
the registers at a high rate followed by storage at
a DC display rate for the desired time. Although
the characters would appear static, the high-voltage
switch would keep the actual duty rate low.
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There are many potential new applications for
moving·lamp displays in industrial control systems.
Functions such as process flow rates through
several feeder pipelines or subassembly line rate
in an assembly plant, cannot easily be set up on a
CRT display. Complex computer graphic tech·
niques or very expensive multi·gun displays may
be needed.
The clock rates and lengths of a number of rows
of lamps can readily be adjusted by hand·operated
controls, such as voltage·controlled oscillators and
gating between registers chosen by selector switches. Any feeder-line display rate that can be repre·sented by the display rate could therefore be varied
at a compressed scale of time and distance until the
display operator arrived at the optimum balance
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Application Notes/Briefs
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LOW FREQUENCY OPERATION WITH DYNAMIC
SHIFT REGISTERS
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In many dynamic shift register applications, it is
advantageous to operate the circu it at low clock
frequencies or in clock burst modes where high
frequency clock rate periods are followed by long
intervals in which the clocks are absent. To insure
that his system will operate correctly under these
conditions, the designer should be aware of the
limitations of the type of shift register he is using.
There are two basic forms of dynamic shift register
cells: the ratioless and the ratio. The ratio less
circuit of Figure , a is based on a capacitor pre·
charge concept. During
C
...
..r:.
FIGURE lb. Ratio Type Dynamic Shift Register Cell
3:
c
o
.';:;
e
Q)
c.
o
>
CJ
C
Q)
~
c:r
...
LL
Q)
3:
o
...I
It)
It)
I
Z
c(
FIGURE 2. Timing Diagram For Two Phase Dynamic Shift Registers
The ratio dynamic shift register cell of Figure 1 b
has only one isolated node which limits minimum
frequency operation. It, like the ratioless cell, is
the gate node of the logic transistor. The ratio cell
does not rely on stored precharge to establish a
"1" level on a succeeding logic gate mode. If a
"0" level had been transferred to node A of the
ratio cell by Q, during
c:
IL = Total leakage current at critical node.
t.l
(I)
:::I
0-
.
(I)
LL
~
o
....I
.
It)
It)
z
Total capacitance at critical node
V,N,T,AL
...
The initial voltage can be optimized in two ways:
by using the highest clock amplitude possible and
by allowing something greater than minimum clock
pulsewidth to insure that the maximum amount of
charge is coupled to the node (and in the case of
the ratio less cell, that the maximum precharge
voltage is obtained before transfer). A high value
of VGG or Voo , the negative supply voltage, increases on-chip power and therefore junction temperature, as well as increasing the minimum required node voltage. It is a good idea, therefore,
«
13-20
to stay away from very high supply voltages. When
both the clock driver reference voltage and VGG
or Voo are the same supply, the best tradeoff is
toward the higher end of the specified range, however. One other consideration which applies during
operation at any frequency, but particularly at low
frequency, is excursions of the clock line more
positive than Vss. This forward biases internal
junctions which results in parasitic PNP transistors.
If the collector of the parasitic PNP happens to be
a critical node, the circuit will fail. Because critical
nodes are often closer to the minimum required
voltage during low frequency operation, registers
are usually more sensitive to positive clock spikes.
When calculating temperature effects of a system
operating in the clock burst mode, the designer
must remember that power dissipation in the shift
register is approximately double at 2.5 MHz what
it is at 100 kHz. High frequency bursts will heat
the chip, causing high junction temperatures which
reduce the time the clocks can be off.
SUMMARY
Dynamic shift registers can be operated at very
low clock rates if manufacturers data sheets are
consulted and the proper clock phasing is used_
Added margin can be designed into systems by
keeping clock amplitudes high, the clock pulsewidths 10 to 20% wider than specified minimums,
power supplies low and temperatures as low as
possible. Beware of circuit board hot spots which
increase the temperature of individual packages,
or extensive interlead coupling or ringing which
could result in positive clock spikes .
Application Notes/Briefs
»
z
u..
.....
»
.3
CD
5'
I»
~
AMERICAN AND EUROPEAN FONTS IN
STANDARD CHARACTER GENERATORS
I»
~
C.
Ten popular American and European 64-character
subsets for displays and printers are now available
from National as single-chip, standard character
generators. These parts, listed in Table 1, are sold
off-the-shelf without a ROM masking charge.
The ROMs are static, bipolar-compatible types,
operating without clocks on standard power supplies. Rowand column access times are typically
450 and 700 ns respectively. An MM4240/MM5240
2560-bit ROM is used for the 5 x 7 horizontal-scan
fonts and an MM4241/MM5241 30n-bit ROM for
the 7 x 5 vertical-scan fonts. The MM4240 and
MM4241 operate at -55°C to +125°C and the
MM5240 and MM5241 at _25°C to +70°C.
Input-output configurations and character formats
for the ROMs are shown in Figures 1 and 2. Application Note AN-40 The Systems Approach to
Character Generators gives examples of Iine and
column address-control logic, and CRT and printer
operating techniques.
m
c
a
'a
CD
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o
~
P+
en
:i"
en
P+
I»
~
C.
I»
a.
TYPE NUMBER
CODE
64-CHARACTER SUBSET
n
FIGURE
~
I»
;
Horizontal Scan (5 x 7)
MM4240AA!MM5240AA
ASCII
Upper-case alphanumeric
3
MM4240AE!MM5240AE
ASCII
Lower-case alpha and symbols
4
MM4240ABU!MM5240ABU
Hollerith
Upper-case alphanumenc
5
MM424QABZ/MM524QABZ
EBCDIC-B
Upper-case alphanumeric
6
MM4240ACA!MM5240ACA
EBCDIC
Uppet"case alphanumeric (IBM)
7
n
.
.g
;
C)
CD
~
CD
I»
Vertical Scan (7 x 5)
MM4241 ABL/MM5241 AB L
ASCII
Upper-case alphanumeric
B
MM4241ABV/MM5241ABV
ECMA
Upper-case A/N, Scandinavian
9
MM4241ABW!MM5241ABW
ECMA
Upper-case A/N, German
MM4241ABX!MM5241ABX
ECMA
Upper-case A/N, general
European (French, British. Italian)
11
MM4241ABY!MM5241ABY
ECMA
Upper-case A/N, Spanish
12
TABLE 1. Single-Chip, Standard
:
Horizontal~Scan
and Vertical-Scan Character Generators
"'
IN~~~
CODE
INPUTS
(CHARACTER
ADDRESS)
"'.
ADDRESS
INPUTS
f
MM4240/
MM5240
"
(CHARACTER
AOORUS)
(I:
"'.
•
OUTPUTS
MM4241J
MM5241
C,
000B,B,8, 8,8,
"
"
b,
It,
",
"
c,
001.
~~~:
•
ROW
•• :
AODRESS100 •
••
101.
110.
111.
(A) ROMCONFlGUAATION
FIGURE 1. Horizontal-Scan Character Generator ROM
Ul
10
COLUMN
AODRESS {
INPUTS
c,
C.
"
"
"
"
"
"
COLUMN
OUTPUTS
COLUMN
ADDRESS
8.. I•
:;s-_
g:6;;~§
OUTPUTS:::
•
•
•
8, •
8,.
"
_:
•
•
(AI ROM CONFIGURATION
FIGURE 2. Vertical-Scan Character Generator ROM
13-21
Note that each ROM has a chip-enable input to
permit multi-ROM operation with common control
logic_ For instance, two horizontal-scan ASCII
character generators may be operated in tandem to
obtain upper and lower-case characters_ In this
case, chip-enable would be controlled with bit b6
of the normal 7-bit ASCII code, and its complement, 1)6'
HORIZONTAL SCAN FONTS
'E
aI
~
C
aI
...
CJ)
C
...
1/1
C
o
LL
C
aI
CD
C.
e
::::I
W
~
C
aI
The subsets of 64 5 x 7 characters in the horizontal-scan fonts are the ones most commonly
used in low-cost TV and CRT raster-scan displays
and dot-matrix line printers.
characteristics of all the horizontal-scan character
generators).
MM4240AEIMM5240AE generates unique symbols
describing the ASCII-7 control codes, as well as
lower-case letters (Figure 4). The designer may not
wish to display or dot-print the symbols. Since the
symbols are generated only when the most significant address bit is logic "0", this bit line may be
used to disable the chip, and blank the screen when
control signals are transmitted. If not, the system
designer can use the symbols as he likes.
... ..... .l ....·....................: .·:..:
··"'·.. ··"' .....· .....: .....· .·.. . ...:..·
.....
..... ...... ·: ..
: :..: ..
::
.......·::
.......... .....
..... :.....
.....
......
. ..... ....
........ : :
...
.:.
.....: :........: :........: :.:....: : :.:.:
·:........·:..:...:..:.:..:.:.:....:. :...............
. . . . .....
:.......: .:.:.:
:.:.: :.:.: :...:..:....:
. . .:.:.:
. ..:...:........
·........................................
................................
I
• I•
'
MM4240AAlMM5240AA contains the ASCII-6 pre7erred graphic subset, formed from ASCII-7 by
ignoring bit b6 . The remaining six bits form two
octal address characters. One is formed by the
three more significant bits, b 7 , b 5 and b4 , and the
seco nd by b3 , b 2 and b,.
Also, characters 36 and 37 in ASCII (x3.4 1965)'
are respectively a carat (or circumflex), and an
underscore. These are awkward in a video display,
so they are replaced by the more useful arrows.
(The arrows are related to characters in an older
teletypewriter set.) This font, shown in Figure 3,
is also described on the MM4240/MM5240 data
sheet (which should be referred to for operating
... . .... ....................
.
• I II
I
I
• I.··. : II
.0:::
•••: :••• :
C
aI
: ::••
I ••
·.1.·: : .1••• ••.•• .1••• :.... :
to)
';:
Oil
01
112
OJ
04
05
06
DOQOOe
000001
000010
000011
0001110
000101
000110
:
0:
••••:
07
: ·......
··:...··:• ...··•• ·..." ···: .......: ..'···......
·....: .: ...:..:...··:
.... ... .... ... ...... .. .. .
CD
10
001000
.....
InI
I ••: I. II""
'1'
I
E
';::
=
STILL AlA WITH ClIP·ON
~EAT SINK (THERMALlOY
TYPE 215 - 1,9 OR fQUIV.'
"'-
STILL~ r-....
~
.........
0.'
Q
25
.:.I:
50
75
~
z
0
~
iii
1.0
~
~
100
125
l<
2
0.6
STllL~
0.'
cu. CONDUCTORS
oz.. OJ IN WIDE
"""
..........
0.2
150
25
50
75
100
125
150
AMBIENT TEMPERATURE (QCI
AMBIENT TEMPERATURE reI
CJ
~OLOE~EO Tri PC .dARD
~WITH 8
0.'
C
~
-
.2
(.)
TO-5 Power Ratings
...c
Flatpack Power Rating
1.2
'.0
G)
"C
o
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::!!
0
~
en
c
iii
1.0
0.8
~
3\:
l<
NTiLL
~
z
AIR WITH CUP
ON HEAT SINK
0.6
C
'>
Q.
Co
«
-I'...
0.'
STlll~ r--....
0.2
25
50
AMBIENT TEMPERATURE
,....
CD
125
~
~
..........
100
2.'
2.0
iii I.'
c
""" ~
15
0
~
150
reI
1.0
D.'
CASE TEMPERATURE
I"\.
F~EE AliA
25
50
15
-r100
125
150
AMBIENT TEMPERATURE (OC)
I
Z
«
required, reliability and cost. Power handling capability for various packages is illustrated in Table" I.
The following guidelines are recommended:
500mW rating under normal system conditions;
i.e., there is no practical way to conduct heat
away from the device other than air.
The TO·5 ("H") package is rated at 600mW still
air (derate at 4.0mW/oC above 25°C) and 900mW
with clip on heat sink (derate at 6.0mWtC above
25°C). This popular cavity package is recommended
for small systems. Low cost (about 10 cents) clip·
on-heat sink increases driving capability by 50%.
Other package types range in size and power handl·
ing capability. Most have the disadvantage of being
in non·standardsizes and are difficult to mount in
a system.
The 8 pin ("N") molded mini·DIP is rated at
600mW still air (derate at 4.0mWtC above 25°C)
and 1.0W soldered to P.C. board (derate at
6.6mW/oC). Constructed with a special copper
lead frame, this package is recommended for
medium size commercial systems particularly where
automatic insertion is used. (Please note for prototype work, that this package is only rated at
600mW when mounted in a socket and not one
watt until it is soldered down.)
The TO·8 ("G") package is rated at 1.5W still air
(derate at 10mWtC above 25°C) and 2.3W with
with clip on heat sink (Wakefield type 215·1.9 or
equivalent·derate at 15mWtC). Selected for its
power handling capability and moderate cost, this
hermetic package will drive very large systems at
the lowest cost per bit.
The 14 pin cavity DIP is rated at 600mW free air.
While some rate this package at 1W case tempera,
ture, National does not recommend its use for
clock drivers. This is because from a user point of
view, it is impossible to get more than 400 to
13-28
Power Dissipation Considerations
The amount of registers that can be driven by a
given clock driver is usually limited first by internal
power dissipation. There are four factors;
• Package and heat sink selection
• Average DC power, Poc
• Average AC power, PAC
• Numbers of drivers per package, n
From the package heat sink, and maximum ambient
temperature one can determine PMAX , wtlich is
the maximum internal power a device can handle
and sti II operate rei iabl y. The total average power
dissipated in a driver is the sum of DC power and
AC power in each driver times the number of
drivers. The total of which must be less than
the package power rating.
P01SS = n X (PAC + Pod:::: PMAX
(1)
Average DC power has three components: input
power, power in the "OFF" state (MOS logic
"0") and power in the "ON" state (MaS logic "1").
(2)
POC = PIN + POFF + PON
For most types of clock drivers, the first two terms
are neglible (less than 10mW) and may be ignored.
dissipate internally 290mW per MHz per thousand
pF of load. At 5MHz, this would be 1.5W for a
1000pF load. For long shift register applications,
the driver with the highest package power rating
will drive the largest number of bits.
Thus:
~PON
P OC
Combining equations (1), (2), (3), and (4) yields
a criterion for the maximum load capacitance
which can be driven by a given driver:
=
where:
v+ - V- = Total voltage across the driver
500
CL =2nF
= Equi'valent device resistance
Req
in the "ON" state
= V+ - V- / IS(ON)
Iz
400
~
300
.
(3)
~
'"
DC = Duty Cycle
~
"ON" Time
1-
-¥~'·It.'IF
III
II 1/ C,·IOIOOpr~
I
IA I
I
III /
zoo
100
VCL"'SOOpF
I I
./
IIJ.
~
~I='"
"ON" Time + "OFF" Time
j...
~50:'F
y+ -Y-=17V
0.5
1.0
2.0
1.5
2.5
PULSE REPETITION FREOUENCY (MHz)
For the MH0025, Req is typically 1kn while Req
is typically 600n for the MH0026. Graphical
solutions for Poc appear in Figure 1. For example
if V+ = +5V, V- = -12V, Req = 500n, and
DC = 25%, then Poc = 145rriW. However, if the
duty cycle was only 5%, Poc = 29mW. Thus to
maximize the number of registers that can be
driven by a given clock driver as well as minimizing
average system power, the minimum allowable
clock pulse width should be used for the particular
type of MOS register.
".
i" ...
2OV').1! 1/
..!. ) /
2ovl1~r----
!
I
100
15
3:
oC/)
PRF
1
CL
<- f
3:
CD
3
o
.
(5)
CD'
en
As an example, the MH0025CN can dissipate
630mW at T A = 70°C when soldered to a printed
circuit board. Req is approximately equal to 1k.
For V+ = 5V, V- = -12V, f= lMHz, and DC = 20%,
CL is:
CL
1'--"//
I~ V ./
10
20
v'
- 106
-rp
_I.,o!.oo
.'0'"
3tI
40
50
60
[(630 X 10""3)
(2)(17)2
0.2]
1 X 103
CL
YS
~
880pF (each driver)
10
DUTY CYCLE (%)
FIGURE 1. POC
< _1
~
'/.V
50 ;;'17 i,....-'
25 ~
o
YS
f-f-f7·17•
: :::
Em
FIGURE 2. PAC
Duty Cycle
In addition to Poc, the power driving a capacitive
load is given approximately by:
(4)
A typical application might involve driving an
MM5013 triple 64·bit shift register with the
MH0025. Using the conditions above and the clock
line capacitance of the MM5013 of 60pF, a single
MH0025 can drive 880pF/60pF, or 14 MM5013's.
Similarly, the MH0026CG can dissipate LOW at
75°C. For V+ = 5V, V- = -12V, f = 2MHz, and
DC = 20%, the maximum load capacitance which
may be driven is:
where:
f = Operating frequency
CL = Load capacitance'
Graphical solutions for PAC are illustrated in
Figure 2. Thus, any type of clock driver will
L
<
-
1 [(1.0)
2x106
(2)( 17)2 -
CL
~
700pF (each driver)
C
0.2]
600
13-29
TABLE IV. Worst Case Maximum Drive Capability for MH0026·
MINI· DIP
SOLDERED DOWN
TO-8
FREE AIR
TO-8WITH
HEAT SINK
PACKAGE TYPE
T0-5 AND MINI·DIP
FREE AIR
Max.
Max.
Operating
Frequency
Ambient
t:§
I
60°C
B5°C
60°C
8S c C
60"e
85°C
60°C
8SoC
~
Duty Cycle
100kHz
5%
30 k
24 k
19 k
15 k
13 k
10k
7.5k
500kHz
10%
6.5k
5.1k
4.1k
3.2k
2.7k
2k
1.5k
lMHz
20%
2.9k
2.2k
1.8k
1.4k
1.1k
S.ak
1.1k
840
600
430
2MHz
25%
850
650
550
400
280
190
5MHz
25%
620
470
380
290
240
170
120
80
10MHz
25%
280
220
170
130
110
79
-
-
1.4k
Uk
·Values in pF and assume both sides in use as non·overlapping 2 phase driver; each side
operating at same frequency and duty cycle with (v+ - V-I = 17V. For loads greater
than 1200 pF, rise and fall times will be limited by output current:
~
I
Z
, (to MOS
logic "1 "I is capacitively coupled via CM to <1>2'
Obviously, the larger CM is, the larger the spike.
Prior to <1>, 's transition, Q , is "OFF" since only
JlA are drawn from the device. A simple method
of minimizing cross-talk is shown in Figure 6.
til
~
o
s:o
rJ)
One last word of caution with regard to use of a
damping resistor should be mentioned. The power
dissipated in Rs can approach (V+ - V-ffC L and
accordingly the resistor wattage rating will generally be in excess of lW. There are, obviously,
applications where degradation of t, and t, by use
of damping resistors cannot be tolerated. Figure 4
s:
CD
3
o.,
;'
til
D2
lN914
1K
FIGURE 6. Use of Bleed Resistors to Minimize Clock-
Line Crosstalk
FIGURE 4. Use of High Speed Clamp to Limit Clock
Overshoot
shows a practical circuit which will limit overshoot
to a diode drop. The clamp network should
physically be located in the center of the distributed load in order to minimize inductance
between the clamp and registers.
Cross Talk: Voltage spikes from <1>, may be
transmitted to <1>2 (and vice versa) during the
transition of <1>, to MOS logic "1." The spike is
due to mutual capacitance between clock lines
and is, in general, aggravated by long clock lines
when numerous registers are being driven. Figure 5
illustrates the problem.
Bleed resistors are connected between the clock
driver and ground causing a current of a few mA
to flow. The output impedance of the clock driver
is reduced and the negative spike is thus minimized.
Values for Rb depend on layout and the number
of registers being driven. Typical values are between
1k and 10kD.
A major point should be emphasized with regard
to clock-line crosstalk, i.e., even if the output
impedance of the driver is zero ohms, self inductance between the clock driver and registers will
cause the clock lines to spike on the transitions.
Hence, the technique shown in Figure 6 works
reasonably well for small systems.
13-31
For large systems, the circuit of Figure 7 is
recommended. In this instance, 0 1 and O2 are
turned "ON" just prior to the clocks transition
to logic "1." The spike is therefore clamped by the
VCE (sat) of 0 1 and O2 , A key feature of the cir·
cuit is that the clamps are physically placed
adjacent the register thus minimizing the induct·
ance between the clamp and the load.
3. Dale Mrazek, "MaS Delay Lines," National
Semiconductor, AN·25, April 1969.
4. Dale Mrazek, "MaS Clock Savers," National
Semiconductor, MB·5.
5. Dale Mrazek, "Silicon Disc's Challenge Magnetic
Disc Memories," EDN/EEE Magazine, Sept.
1971.
6. Richard Percival, "Dynamic MaS Shift Registers
can also simulate Stack and Silo Memories,"
Electronics Magazine, Nov. B, 1971.
7. Bapat and Mrazek, "Dynamic MaS Random
Access Memory System Considerations," Na·
tional Semiconductor, AN·50, Aug. 1971.
FIGURE 7. Cross Talk Minimization Circuit
B. Don Femling, "Using the MM5704 Keyboard
Interfacein Keyboard Systems," National Semi·
conductor, AN·52.
Input Capacitive Coupling
Generally, MaS shift registers are powered from
+5V and -12V supplies. A level shift from the
TTL levels (+5V) to MaS levels (-12V) is there·
fore required. The level shift could be made utiliz·
ing a PNP transistor or zener diode. The disadvan·
tage to DC level shifting is the increased power
dissipation and propagation delay in the level
shifting device. Both the MH0025 and MH0026
utilize input capacitors when level shifting from
TTL to negative MaS capacitors. Not only do the
capacitors perform the level shift function without
inherent delay and power dissipation, but as will
be shown later, the capacitors also enhance the
performance of both the MH0025 and MH0026.
APPENDIX I
MH0025 Circuit Operation
The schematic diagram of the MH0025 is shown in
Figure AI·1. With the TTL driver in the logic "a"
state 0 1 is "OFF" and O 2 is "ON" and the output
is at approximately one VBE below the V+ supply.
CONCLUSION
The practical aspects of driving MOS memories
with new low cost clock drivers has been discussed
in detail. When the design guide lines set forth in
this paper are followed and reasonable care is
taken in circuit layout, the MH0025 and MH0026
provide superior performance for most MaS input
interface applications.
.......~~-oOtJTPUT
INPUT
CR2
Rl
"0
'---""'--4"""----0 v-
FIGURE AI·'. MH0026 Schomatic (Ono·Half Circuit)
REFERENCES
1. Bert Mitchell, "New MaS Clock Driver for
MaS Shift Registers," National Semiconductor,
AN-lB, March 1969.
2. John Vennard, "MaS Clock Drivers," National
Semiconductor, MB-9, December 1969.
13·32
When the output of the TTL driver goes high,
current is supplied to the base of 0 1 , through
C IN , turning it "ON." As the collector of 0 1 goes
negative, O2 turns OFF. Diode CR 2 assures turn·on
of 0 1 prior to 02'S turn·off minimizing current
spiking on the V+ line, as well as providing a low
impedance path around 02'S base emitter junction.
The negative voltage transition (to MOS logic "1 ")
will be quite linear since the capacitive load will
force 0, into its linear region until the load is
discharged and 0, saturates. Turn-off begins when
the input current decays to zero or the output of
the TTL driver goes low. 0, turns "OFF" and O2
turns "ON" charging the load to within a V BE of
the V+ supply.
Rise Time Considerations
The logic rise time (voltage fall) of the MH0025 is
primarily a function of the AC load, C L , the
available input current and total voltage swing. As
shown in Figure AI-2, the input current must
or
[C L + (hFEQ1+1)CTcl t.V
h FEQ,
(AI-5)
liN
Equation (AI-5) may be used to predict t, as a
function of C L and t.V. Values for GTC and hFE
are 10 pF and 25 respectively. For example, if a
DM7440 with peak output current of 50 mA were
used to drive a MH0025 loaded with 1000 pF, rise
times of:
(1000pF + 250pF) (17V)
...:::I
0-
or 21ns may be expected for V+=5.0V, V-=-12V.
Figure AI-3 gives rise time for various values of
CL •
R2
c.
(1)
(')
(50mA) (20)
lK
s:o
n
'?'
...
of
...
C
(1)
J
1/1
g
"'-C-R2--1~ 02
s:
o
rn
s:
(1)
3
o
200
400
600
800
o...
;'
1000
LOAD CAPACITANCE, CL (pF)
1/1
FIGURE AI·3. Rise Time vs CL for the MH0025
FIGURE AI·2. Rise Time Model for the MH0025
Fall Time Considerations
charge the Miller capacitance of 0" CTC, as well
as supply sufficient base drive to 0, to discharge
C L rapidly. By inspection:
(AI-l)
The MaS logic fall time (voltage rise) of the
MH0025 is dictated by the load, C L , and the
output capacitance of 0,. The fall time equivalent
circuit of MH0025 may be approximated with the
circuit of Figure AI-4. In actual practice, the base
v'
(AI-2)
If the current through R2 is ignored,
(AI-3)
A,
CTC01T T-10PF
':"
IiHQz +l
CTCal = OUTPUT CAPACITANCE OF 01
"" lDpF
hFEQ2 '" CURRENT GAIN OF 02
~
20
IAVG = AVG CURRENT THROUGH Rz
v+ -v2R2
":'"
where:
FIGURE AI-4. Fall Time Equivalent Circuit
Combining equations AI-l, AI-2, AI-3 yields:
drive to O 2 drops as the output voltage rises
toward V+. A rounding of the waveform occurs
as the output voltage reaches to within a volt of
V+. The result is that equation (AI-7) predicts
conservative values of t f for the output voltage
at the beginning of the voltage rise and optimistic
13-33
1/1
Q)
.~
o
values at the end. Figure AI-5 shows t f as function
of GL .
E
Q)
~
is the peak current delivered by the TTL driver into
a short circuit (typically 50 to 60 mAl. 0 1 will
begin to turn-off when liN decays below V BE /R 1
or about 2.5 mAo In general:
(J)
(AI-8)
o
~
160
I-l-H-l-+-+-I--I-+--l
Where:
...o
~
Ro
...
1/1
Q)
>
..
120
I""q.."++++-+-+-+-H
.
.~
Output impedance of the TTL driver
~
GIN
Input coupling capacitor
.
Substituting liN
yields:
o
200
~
400
600
BOO
~
IMIN
1000
.2
t1
u
= ROG IN In
...
I:
Q)
Assuming hFE2 is a constant of the total transition:
o
~
L!.V ~(V+ - V-)
Cl
L!.t
I:
>-
2R2
0..
«
(AI-6)
tpw
2<
t, + t f
-2- + t1
t, + t f
I MAX
+ ROG IN In
2
or
(AI-7)
CD
......
I
Z
«
(AI-g)
The total pulse width must include rise and fall
time considerations. Therefore, the total expression
for pulse width becomes:
GTC01 + GL /h FEo 1+1
Q.
I MAX
IMIN
FIGURE AI-5. MH0025 Fall Time vs CL
""C
and solving for t1
R1
LOAD CAPACITANCE, CL (pF)
CJ
VBE
~--
MH0025 Input Drive Requirements
Since the MH0025 is generally capacitively coupled
at the input, the device is sensitive to current not
input voltage. The current required by the input is
in the 50 to 60 mA region. It is therefore a good
idea to drive the MH0025 from TTL line drivers,
such as the DM7440 or DM8830. It is possible to
drive the MH0025 from standard 54/74 series gates
or flip-flops but tON and t, will be somewhat
degraded.
I nput Capacitor Selection
(AI-10)
IMIN
The logic "1" output impedance of the DM7440 is
approximately 65S1 and the peak current (I MAX )
is about 50 mAo The pulse width for GIN = 2,200pF
is:
25ns + 150ns
tpw
2<
+ (65S1) (2,200pF) In
2
50mA
517ns
2.5mA
A plot of pulse width for various types of drivers
is shown in Figure AI-7. For applications in which
The M H0025 may be operated in either the logically controlled mode (pulse width out 2< pulse
width in) or GIN may be used to set the output
1100
I,.
900
OIl(~p~;Pp~~~~~lOrH vs C'N fllR LONG
65'R.CINln~1!
~lU::~: :,UlSE WIDTH" INPUT PULSE WIDTH
]
~
700
i
1/
Hfb+-
f-- iOM9J2oJIVEJ-
500
i1
~
300
"rPiuur
100
200
600
1000
1400
1800
2200
CIN (pF)
FIGURE AI-S. MH0025 Input Current Waveform
pulse width. In the latter mode a long pulse is
supplied to the MH0025. The input current is of
the general shape as shown in Figure AI"6. I MAX
13-34
FIGURE AI-7. Output PW Controlled by CIN
the output pulse width is logically controlled, GIN
should be chosen 2 to 3 times larger than the
maximum pulse width dictated by equation (AI-l0).
APPENDIX Ii
DC Coupled Operation
The MH0025 may be direct-coupled in applications
when level shifting to a positive value only. For
example, the MMll03 RAM typically operates
between ground and plus 20V. The MH0025 is
shown in Figure AI-8 driving the address or precharge line in the logically controlled mode.
+5.0V
14U'~ ,U'~
r-I-', r-I-',
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MH0025CN
TO RAM
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MHD026 Circuit Operation
The schematic of the MHOD26 is shown in Figure
AIi-1. The device is typically AG coupled on the
input and responds to input current as does the
MHDD25. Internal current gain allows the device
to be driven by standard TTL gates and flip-flops.
With the TTL input in the low state 0 1 , O2 , 0 5 ,
Os, and 0 7 are "OF F" allowing 0 3 and 0 4 to
come "ON." R6 assures that the output will pull
up to within a V BE of V+ volts. When the TTL
input starts toward logic "1," current is supplied
via G'N to the bases of 0 1 and O2 turning them
"ON." Simultaneously, 0 3 and 0 4 are snapped
"OFF." As the input voltage rises Ito about 1.2Vl,
0 5 and 0 6 turn-on. Multiple emitter transistor 0 5
provides additional base drive to Q 1 and O 2 assuring their complete and rapid turn-on. Since 0 3 and
Q 4 were rapidly turned OF F minimal power supply
current spiking will occur when Q 7 comes "ON."
FIGURE AI-S. DC Coupled MH0025 Driving 1103 RAM.
If DC operation to a negative level is desired, a
level translator such as the DM78DD or DHDD34
may be employed as shown in Figure AI-g. Finally, the level shift may be accomplished using
PNP transistors are shown in Figure AI-1D.
L. ::r:::
MH0025CN
~
EXTERNAL
""
0-1 ~""O-,~NV--f
.J
O-12V
~O.lj.!f
FIGURE AII-l. MH0025 Schematic lOne-Half Circuit)
FIGURE AI-g. DC Coupled Clock Driver Using OH0034.
Os now provides sufficient base drive to 0 7 to
turn it "ON." The load capacitance is then rapidly
discharged toward V-. Diode 0 4 affords a low
impedance path to 0 6 's collector which provides
additional drive to the load through current gain
of 0 7 , Diodes 0 1 and O2 prevent avalanching
Q 3 's and 04'S base-emitter junction as the coilectors of 0 1 and O 2 go negative. The output of
the MHDD26 continues negative stopping about
D.5V more positive than V-.
'5V
6~'~
r--,
INPUTS
TTl {
¢,
"::"
L.~P'~
-12V
FIGURE AI-l0. Transistor Coupled MH0025 Clock Driver.
When the TTL input returns to logic "D," the input
voltage to the MHDD26 goes negative by an amount
proportional to the charge on G,N' Transistors Q 8
and 0 9 turn-on, pulling stored base charge out of
0 7 and O2 assuring their rapid turn-off. With 0 1 ,
O2 , 0 6 and 0 7 off, Darlington connected 0 3 and
0 4 turn-on ;nd rapidly charge the load to within
a V BE of V .
13-35
1/1
Q)
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Q)
:?!
CI)
o
Rise Time Considerations
25
Y+-V-=15Yto2DV
Predicting the MaS logic rise time (voltage fall)
of the MH0026 is considerably involved, but a
reasonable approximation may be made by utilizing equation (AI-51. which reduces to:
:?!
o
'"
(AII-1)
...
>
C
V
Ro '" SOn
TA '" 25°C
/
200
1/1
'':::
I--'
10
...
Q)
1; .....
15
400
600
800
tODD
LOAD CAPACITANCE (pF)
For CL = 1000pF, V+ = 5.0V, V- = -12V,
t, "" 21 ns. Figure AII-2 shows MH0026 rise times
vs. C L .
FIGURE AII·3. Fall Time vs Load Capacitance
..lIi:
(J
are shown in Figure AII-4. There is breakpoint at
V ,N "" 0.6V which corresponds to turn-on of 0 1
and O2 , The input current then rises with a slope
of about 600n (R 2 II R3 ) until a second breakpoint at approximately 1.2V is encountered, corresponding to the turn-on of 0 5 and 0 6 , The slope
at this point is about 150n (R 1 II R2 II R3 II R4 ).
.2
u
...c::
Q)
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o
:?!
!
20
!
15
I
1-V'+_+-V--1.-2OV+-j"*~\J'f·'--'_vl-::_+.-::"l:-:1
v
H-+-+::'~"++t-r-t-H
C'I
c::
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MH0013
Two phase, AC coupled clock driver.
o
MH0025
Low cost, two phase clock driver.
.::I.
MH0026
Low cost, two phase, high speed clock
driver.
MH8808
Dual clock driver for MM5262.2k RAM.
o
...o
...CIl
'i:
CJ
.2
u
c...
CIl
MOS Oscillator/Clock Drivers
o
MH7803/MH7807 - Complete two phase clock
system for MaS micro·processors and
calculators.
Cl
C
"C
~
MH0026
Dual high speed address and precharge
driver.
TT L to MOS Interface
DH0034
Dual high speed TTL to negative level
converter.
DM7800
Dual TTL to negative level converter .
DM7810/DM7812/DM7819 - Open collector TTL
to positive high level MOS converter
gates.
DM78L12 Active pull-up TTL to positive high
level MOS converter gates.
MOS to TTL Level Converters and Sense Amps
DM7802/DM7806* - Dual sense amp for MM5262
2k MaS RAM memory.
LM 165 Series * - Hex sense amp MaS to TTL.
LM163/LM75107/LM75207* - Dual sense amp
for MM1103 1k MaS RAM memory.
MOS RAM Memory Address and Precharge Drivers
Voltage Regulators for MOS Systems
':;'
MH8804
Quad TTL to 1103 address driver.
LM109/LM140 Series - Positive regulators.
Q.
MH8805
Dual TTL to 1103 address driver.
LM120 Series - Negative regulators.
«
MH0025
Dual address and precharge driver.
LM125 Series* - Dual +/- regulators.
Co
*To be announced.
13·38
Application Notes/Briefs
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13 j-.::'::.AT:.:A~S::;TO::.:'~BE:...._ _~
o
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14
c(
DATA STO'BE
CONTROL
JT
In most situations, the processor will readily accept
data presented by the keyboard at normal keyboard rates. If conditions are such that the processor will be busy for periods of time longer than
the time between keyboard entries, then a buffer
memory will be needed to store those entries.
These considerations pertain to total system design
and will vary in each particular situation.
For the purpose of further illustrating the use of
the data strobe, data strobe control and output
enable, let us consider the particular application
where it is desired to poll several keyboards in a
system. We will consider that the keyboards can
be either localized or at remote locations and that
a scanning interrogation technique will be used.
MM5748
00
such that additional data may be entered. Of
course the time periods of concern in such a design
are dictated by the keyboard activity rate and the
processor organization.
C
":"
FIGURE 9. Variable Width Pulse Data Strobe
In many applications, it is more convenient to
have a level strobe mode of operation. For example,
in bus structured systems where there are many
keyboards andlor other peripherals connected to
the main processing system a controlled level strobe
is desired. Such a configuration is illustrated in
Figure 10. In this situation many peripherals share
a TRI-STATE bus. When a peripheral such as the
FIGURE 11. Polling System for Localized Keyboards
FIGURE 10. Keyboard Usa in a Bus-Structured Interrupt
System
keyboard has data available, the Data Strobe goes
high. This signal interrupts the processor. At the
appropriate time, the processor will respond to
this interrupt by setting a flag. This flag can be
used to enter a read peripheral mode and send an
enable signal to the keyboard. When the output
enable of the MM5740 goes low the Data Outputs
are presented to the TR I-STATE bus for acceptance
by the processor. On the next negative edge of the
clock, the data strobe will be automatically reset.
At this point the keyboard and processor have
completed a data exchange and conditions are
I
13-44
In Figure 11 such a polling set up is shown for
localized keyboards and the associated timing
diagram is shown in Figure 12. Since the keyboards
are local, the wiring capacitance can be reasonable
enough to make use of the TR I-STA TE feature
of the MM5740 and allow all encoders to'share a
common data bus. When a character is entered
from any keyboard, the corresponding data strobe
line (pin 13) will go high. When the keyboard is
read, the output enable line will go low, taking the
data lines out of the high impedance state. One
bit time later, the data strobe will be automatically
reset which in turn will drive the output enable
high again. This removes that keyboard from the
data bus and allows the remaining keyboards to
be interrogated. The data strobes for each keyboard
are combined and gated with the clock to form a
single data strobe output to the receiving system.
When the receiving system sees the data strobe
pulse, the output data is stable and ready for
acceptance.
l>
Z
Use Two Encoders for 180 Key Capability
I\EADI~'I-\\-----READ2~1-1_ _ _ _ __
--------~v~
STI\~!I~~
Co
Some special applications may require an N-key
rollover encoder capable of handling a keyboard
with greater than 90 keyswitches. Such situations
are easily handled by using two MM5740 encoders
to provide a capability of up to 180 keyswitches.
Figure 14 illustrates how such a system is configured
and Figure 15 shows typical timing waveforms.
It should be noted that such a configuration is
achieved with a minimum of peripheral circuitry.
o
3:
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en
~
CD
G)
DATASTROBfl _ _ _ _ _ _ _- - ' ( \
...._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
~
OUTPUT _ _ _ _ _ _ _--,.
o
o
~
ENABLE1
~~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CODE
~
DATA 1 _
HIGH IMPEDANCE STATE
~~ _ _ _ _ HIGH IMPEDANCE STATE
CODE
DATA
TRANSITION
o
00
,
CODE
DATA
AVAILABLE
FROM THIRD STATE
DETECT
z
SWITCH~
«
CLOSURE
MATRIX 2
~
" ' -
DATA STROBE 2 - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--'
OUTPUT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..,
~
ENABLE2
COOE:::::::::::::::::::~~~;,:;.;~;,:::::::::::::::::::::~~
.1\~____I'l_!!f~H__
DATA 2
HIGH IMPEDANCE SlATE
---------------...J~
O A T A S T R O B E O U T - - - - - - - - - - - I I \....
FIGURE 15. Typical Timing Diagram - 2 Encoder Expansion Operations
The keyswitches (up to 1801 are wired in two
X-V matrices; one set for each MM5740 encoder.
Both encoders operate asynchronously with respect
to each other; at any time the scan position in one
matrix may not be the same scan position in the
second matrix. The essential point to remember is
that no two keys may be depressed at "exactly"
the same time and still result in a valid code output.
This assumption is quite valid in that there is
always some finite time period between the depression of a key and the depression of a succeeding key, even though that time may be as low as
5-10 ms. Anyone using a keyboard as an input
device to his system must know what the maximum
keyboard activity rate will be for his particular
application. This information tells the system
designer how much keybounce he can tolerate,
what the encoder frequency should be, the type
of rollover to specify, the width of the data strobe,
whether his system is fast enough to accept
asynchronous data from the keyboard without a
buffer store and many other vital design specifications.
strobe output pulse. Code data is valid during the
time that the output enable is low and the clock is
high. After the first data strobe is reset both
encoders are in the idle condition. If a valid
closure is now detected in the second switch
matrix, the second encoder performs exactly like
the first one did a short time earlier. During this
activity, the first encoder is in the high impedance
state. The data strobe outputs from each encoder
are combined in a 7400 gate to provide one data
strobe output line for the keyboard system.
Since both key switch matrices are physically
part of the same keyboard, two keys will not be
activated at exactly the same time. Therefore, each
encoder, operating asychronously with respect to
the other, perform as separate entities. However,
the receiving system which communicates with the
keyboard encoders cannot distinguish that there
are two encoders and two sub-matrices. Externally
this arrangement appears as a single encoder with
up to 180 key capability.
Complete ASR 33 Keyboard System
The above discussion' relates to the application
shown in Figure 14 in the following way. With no
activity on the keyboard the data outputs of both
encoders are in the third or high impedance state.
A valid key closure in one matrix activates the
data strobe and code data outputs of the corresponding encoder removing it from the high impedance state. The second encoder remains in the
high impedance state. Resetting of the data strobe
is automatically accomplished via the output
enable pin and results in a one bit time wide data
13-46
By using the MM5740AAE or MM5740AAF,
typical ASR 33 type communications keyboards
may be configured. These parts are available as
standard off the shelf units. While both versions
contain the same ROM encoding (all 90 key
positionsl, the AAE provides N-key rollover and
the AAF is programmed for 2-key rollover. It
should be noted that many variations of ASR 33
keyboards may be configured by connecting to
the appropriate matrix coordinates.
»z
MM5740 TTL inputs may be supplied from
standard TTL logic without any restrictions on
the TTL·TTL loading. For example, the MM5740
clock input may be supplied from a standard TTL
gate which also drives 10 other TTL loads. By
incorporating any of the techniques' discussed
previously many variations of this basic keyboard
system may be implemented with a minimum
of additional hardware.
One common keyboard system is shown in Figure
16. The associated keyboard layout is shown in
Figure 17 while the key codes are shown in
Figure 18. It is apparent that a minimum of
external hardware is needed to configure a total
keyboard. The ease with which the MM5740 is
able to interface with inexpensive TTL circuitry
eliminates the need for many external resistors
and level translators. It should also be noted that
,
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.,~.,
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, , , , ,
" "', , " " " ", '"
, "",
,
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" ,
,
,
,
, , , "
",
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" "" ""
m
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EDT ETXSTX
,
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"
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lM555'
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Notc 1: Matrix (;oordillates not showl! with 5witGh
""
'M""
, ,
~re
not lised for this particular
Note 2: N-key rollover - MM574DAAE, 2-kev rollover - MM5470AAF.
Note 7: Data strobe
=
10JJspliise
OE
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n
MM5740AAE
" I-"--
" ~:>o--+.,
0,
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Y~LOCK
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tt=:'
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29
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"
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14
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SHlfTLK
SHlflCONTAOL
o£J'"" " ~
,,~>\y "~n J.
SHIfT
r~Ll
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o-tI (OJ I
* L~".~
CONTROL
~
~ ."
,
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40mA
[MIllI1
EN2222
,
*To be introduced
configuration, These coordinates, however, are programmed fo rthecharacters
Note 4: Scan cycle "'900JJs
Note 5: Repeatrate'" 10 characters per second
Note 6: Key bounce mask time eo 4.0 ms
,
'----)4
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0
M
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5DOpf
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Del DCl
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m,,,,
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BREAK
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TYPICAL
KEYSWiTCH
WITHDIOllE
FIGURE 16. ASR·33 Keyboard
13·47
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ASRJ3
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MM5740AAE (N-key rollover)
MM574DAAF (2-keV rollover)
FIGURE 17. Typical Keyboard Arrangement
MATRIX
COMMON
ADDRESS
UNSHIFT
CHARACTER
CONTROL
sc
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
2
"
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FF
FF
GS
GS
GS
so
so
so
SP
SP
0
FS
6
0
0
0_
0
0
o'I-'-,
,
0
0
0
0
0
0
0
0
0
0
0
0
,
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2-f.-20
0
0
0
0
0
0
0
0
so
8S
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OEL
,5
6
3
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
"
OLE
0
0
0
0
0
0
0
0
Negative True Logic
Bl - B7 ~ ASCII Code
B8 ~ Even parity (on Bl. B2. B3. B4. B5. B6. B7. 88)
B9 = Selective Repeat Bit
Note: Use 8S if parity bit is desired.
FIGURE 18. Code Assignment Chart
13-48
0
OLE
l>
Z,
00
MATRIX
ADDRESS
UNSHIFT
COMMON
o
6
0
s:
0
0
0
o
0
o
CONTROL
o
0
0
0
0
0
o
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en
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It)
0
o
o
10
,0
0
-<
0
C-
O
...
I»
C.
m
:::I
n
o
o
°o °
0
5
:::I
0
0
(Q
W
o
6
c.
0
0
°
o
o
0
o
0
0
o
0
0
°
0
010
0
0
0
o
0
°
0
0
0
°
W
Negative True Logic
B1 - B7 = ASCII Code
B8 = Even parity Ion B1. B2. B3. B4. B5. B6. B7. B8)
B9 "" Selective Repeat Bit
Note: Use B8 if parity bit is desired.
MATRIX
ADDRESS
COMMON
UNSHIFT
1
,
0
0
0
o
,
1I0
0
0
;
,
0
I---'+---"'+'o,-!-,,-O+-'+-,,0
L---,t--,:-r+,-'o,+.o
,
0
=0 "
·o-;;-~
8
0
0
o
0
0
0
o
(J
I 1
o
0
0
OC4
o
0
,
1
0
D
,
°
o
0
o
°
; 0
00000000000000
9
0
0
o
0
0
0
0
°
0
0
0
Negative True Logic
B1 - B7 = ASCII Code
B8 = Even parity Ion B 1. B2. B3. B4. B5. B6. B7. B8)
89
=
Selective Repeat Bit
Note: Use B8 if parity bit is desired.
FIGURE 18. Code Assignment Chart (cont'd)
13-49
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"C
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CONCLUSION
The MM5740 keyboard encoder offers a wide
versatility of features not found in conventional
MSI designs. In addition, performance specifications of the MM5740 far exceed those of other
MOS encoders currently available. The wide range
of clock frequency, low power dissipation, variable
bounce masking, ease of interface, rollover capability and its many other notable features make the
MM5740 a logical choice for your keyboard
o
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13-50
encoding function. This encoder has been designed
not only as a powerful part of any keyboard
system but also with the intention of minimizing
the amount of additional keyboard electronics and
simplifying the interaction of the keyboard with
other system components with wh ich it must
communicate. As a result, the MM5740 should go
a long way toward improving the cost-performance
basis of keyboard oriented systems.
J>
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Application Notes/Briefs
00
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SAVING ROMs IN HIGH·RESOLUTION DOT·MATRIX DISPLAYS AND PRINTERS
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INTRODUCTION
Conventionally, the number of bits in a digital
character generator's read only memory is proportional to the number of dots in the character
matrix. That is, the ROM array ordinarily doubles
and redoubles in size as one scales up the resolu·
tion or changes from an upper·case to an upper·
case/lower·case font.
One version of this new technique automatically
proportions character widths as in letterpress
printing. This gives each character a more natural
shape and eliminates the irregular spacings usually
seen around "I" and other narrow characters. Yet
the control logic is simple and the ROM savings
approach 40% at typical font sizes.
Fortunately, such progressions may not be reo
quired. Reorganizing the ROMs to suit the specific
application often save thousands of bits and
allows the designer to use smaller, faster, more
economical monolithic ROMs. As a simple example,
expanding the array in 32·character subsets rather
than the more conventional 64·character subsets
will enhance performance and save up to 25% of
ROM capacity in typical UC/LC applications.
Such advantages are available immediately, without
development of special ROMs. The designs can
be implemented with standard MOS or bipolar
ROMs currently in production. In fact, inter·
mediate coding broadens the cost/performance
options by allowing a combination of MOS and
bipolar ROMs to be used.
Savings much greater than 25% are possible when
the matrix size reaches a point where several
monolithic ROMs are needed to store the font.
We have found a two·stage, column·generation
approach called "intermediate coding" to be much
more efficient than straightforward dot·matrix
generation. It exploits the fact that column
patterns tend to become highly redundant as the
matrix size increases.
Dot-character styles ranging in complexity from
5 x 7 to 12 x 24 or more dots per character have
been developed to meet the human-engineering
standard of various industries using digital displays
and printers. The more popular sizes are listed in
Table I.
TABLE I.
SIZE AND
SCANNING
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The 5 x 7 fonts, such as Figure 1, lead in applications volume due to their use in low-cost data
.
"'U
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Typical Dot-Matrix Character Fonts
DOTS PER
CHARACTER
THEORETICAL
CHARACTER ROM
DESIGN
EFFECTIVENESS
ill
PRACTICAL
DESIGNS
5x7
HOrizontal
35
64x7x5=2-1/2k
1.00
Fig.3
35
64 x 5 x 7
=
2,560
1.00
Fig.3
63
64 x 9 x 7
=
4,032
0.67
Fig. 6
63
64x7x9=4,032
1.00
Figs. 5 & 8
64 x 12 x 8 = 6,144 and
1.00
1.00
Figs. 6 & 7
1.00
1.00
Fig. Be
Fig. 88
7x5
Vertical
7x9
Horizontal
9x7
Vertical
7x12&8x12
Horizontal
96
96 x 12 x 8
12x7&12x8
64 Character Vertical
96 Character Vertical
12
x
96
96
=
8.216
64x8x12=6,144
96
x 8x 12.= 9,216
16
192
192
64 x 16 x 12'" 12.288
96x 16x 12= 18.432
1.50 for Fig. 9A
Fig.9A
1.50 Fig. 9
Fig. 98
192
192
64 x 12 x 16 = 12,288
96 x 12 x 16 = 18,432
1.50 for Fig. SA
1.50 for Fig. 98
Figs. 6. 7.&9
96 Character VertIcal
24 x 12
64 Character Vertical
288
64)( 12x24= 18,432
2.00 for Fig. 98
Figs. 6.7. & 9
208
64 x 13 x 16 = 13.312
3.06 for Fig. 10
Fig. 10
64 Character Horizontal
96 Character Horizontal
16 x 12
64 Character Vertical
64 x 13 x 10 to 64 x 13 x 16
64 Character Variable
Font Width
13-51
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c
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..... i"· I·..•
IJ
..
.·:.i...! ..... • il·· ...
...... • .1••• ..... .1••• I.... I
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D..
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011
01
02
113
04
05
0&
000000
000001
000010
000011
0001011
0011101
OUOll0
01
10
001000
11
001001
12
13
14
15
16
11
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~rn
rn~
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000111
I.•.
L.··I: :1·.-:
:-. 1I··,.
1:•••1:.Ler •••••••••••••
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,!
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•••••
20
010000
21
0111001
e. •••••
22
010010
23
010011
~:.:~ :y: :::::
1U
:!:
31!
011000
31
011801
J:l
011010
;:
..
:....
24
010100
"on "
25
0111101
:
26
1110110
21
0111111
.1.
•
"
011110
37
0111T1
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(. ) ·:if::.. ••1·•• ..:1 ...... ••..:
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a:
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I
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11111011
011101
i i J i••.:•• :: .: :·1 ii
i i· "I·· I· II =.:.:
i
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011
42
100001
"
1111 DOl
43
~m
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11111010
mm
&3
101011
44
4&
46
~~
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~m
41
mm
I.
54
101100
1111101
56
11111111
101111
••••1 ••~ .:••
I
1. :..•...11. . . : ,•••
.:. I .........
...
•• .... ••• ••••
.. •
:::: ·:~I : =
:1 .•.•• ......
••
::J:
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:!:
oa:
61
62
63
64
65
86
110000
ru~
mm
rum
m~
mm mm
10
111lI0II
11
111001
11
1I1UlO
73
111011
14
111100
15
1T111J1
&1
rum
I
16
111110
71
111111
..••:. ......
.' ,...
.
:.
.!
• • • • 1..1
interface terminals (although some terminal manufacturers are going to larger sizes in response to
complaints that 5 x 7 presentations cause eyestrain)_ In other applications, a standard is often
set by older printing techniques_ To cite a few
examples: business-machine users are accustomed
to typewriting; advertisers want characters with
"sales appeal" on their billboard displays; scoreboards and traffic-control signs must be read
easily at a distance; and electronic printing systems
may have to simulate several metal type fonts_
The matrix size is frequently enlarged to improve
lower-case character definition in UC/LC applications_ A 5 x 7 font typically grows to 7 x 9 for UC
and 7 x 12 for LC, as in Figure 2_ Likewise, 7 x 9
is expanded to 8 x 12 and 12 x 16 to 12 x 24 for
lower-cases_
o... . ·· ·.........·.........··....·. ....
.....
o.. ·•.. · ··· ·· ...· ..
...
.
...
..,.,...:....... .: ·...............
::- ..
.
..........
..
. ... .......·. ........
.
...
IIl4S
12346
1234$
1234S
12345
1234S
,
,
,
I ••••
12346117
I
,
~
,
12346&7
1234S17
1234S'7
1234517
•••••
:
: e.
: _.
•••
•
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FIGURE 2. UCILC Characters at 5 x 7 and 7 x 12
Matrix Sizes
(AI Upper-Case Font
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.. . .....• .....I .....·"1:·.·:... I:·:: ::.::.
..............: .:. ..:
••··1 I··....... : .:: • •••• •• :.:••
..::.. ..... I,. .:1:.•..• I I I .:.
... I.:.:·11·:.:.11-:...II...:·1 r.··1... I.:.I I I-I·!.:.
I···!
... ... ... .:. .:. ..: .:. .:.
c
'>ca
I I
oouoao
Ul
0000111
"
000010
M
000100
H
DUll 101
~
~
000011
000110
000111
10
001000
11
001001
12
001010
13
001011
14
001100
1&
1101101
18
001110
17
001111
m
21
01110111
00
(I)
an
00I
Z
c(
1110080
:•••: r:·:
~
un"
~
u
V
010101
11101111
010111
.·i·' :.... •...::·r: r"· ,•••:
010010
0111011
1110100
I:·:i
ii·i iii 1···11 :·i I·: i I, II i·1
........................................
.. .:... :":.• ...... .:.. ·: ... ·r·..··.......:
. ........
. • ·" ."... .".. .·..... ·•. ."..
r.·. :.........
··..• ..··• ·••.. .··.• ··:•....·. .··•• ....
·: ....•..
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•
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·· " · "
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1111000
31
011001
n
n
M
~
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011010
011011
011100
0111111
011110
31
011111
•
t:
11100011
100001
100010
100011
100100
so
51
101001
52
101010
101011
101100
101000
54
100101
I
61
110001
10
71
111101
moDO
62
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111010
110011
~
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110100
I
I
73
111011
111100
1001111
100111
II
101101
I : .......: •• I
"
1100110
•••1
.: I ••••
101110
II
~
101111
I:
:
110101
1101111
~
67
110111
75
111101
16
71
111111
111110
(81 Lower-Case Font
FIGURE 1. ASCII Full Set Font of 1285 x 7 Characters
13-52
At 5 x 7, it is most economical, as a rule, to program a "full set" of 128 UC/LC characters in
standard character-generator ROMs. The full set
in Figure 1 is stored in two 64-character MaS
ROMs. This provides a mass-production base and
equalizes access times. If the 32 special symbols
generated with the ASCII control codes are not
usable, they are simply blanked by disenabling
the lower-case ROM when the seventh ASCII bit
is "0." But if the font is scaled up to simulate
typewriting, for example, this practice becomes
wasteful since 96 characters would suffice.
Another compl ication is that many special ized font
sizes, such as 11 x 9, do not fit neatly into standard
ROMs made in building block sizes. In other
words, one cannot store the font in a minimumsized ROM array without paying the extra costs
of custom ROM development or specialized lowvolumn ROMs.
CHARACTER-GENERATOR ROMs
Consequently, character-generator ROMs have been
developed that adapt to a variety of font sizes.
They may not exactly fit the theoretical matrix
array at odd sizes. but that is easily offset by
the economy of parts standardization.
Two such MaS ROMs are outlined in Figure 3
with their addressing for 5 x 7 horizontal scanning
and 7 x 5 vertical scanning. The vertical-scan subsystem in Figure 4 shows the amount of support
logic typically required in a display.
»
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CHARACTER
CODE
rr'
A.
A,
"
ROW
ADDRESS
OUTPUTS
}""
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Aa
USE 2 ROMs AND
APPLVA,TOC£
FOR 128 CHARACTERS
R
Al
........
....:
:
"
.
CHARACTER
CODE
r
....:
AJ
A.
A,
ADDRESS
:...
A•
COLUMN
ADDRESS
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{''
CA2
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00
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COLUMN ADDRESS
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OUTPUTS
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use 2 ROMI AND
APPLY A, TO C[
FOR 12B CHARACTERS
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SCAN
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(AI 5 x 7 Horizontal-5can, 64-Characters
5'
(BI 7 x 5 Vertical-Scan, 64-Characters
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FIGURE 3. MM5,240 and MM5241 Standard Character·Generator ROMs
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CHARACTER
GENERATOR
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lAXtS
MOO
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INPUT
CHARACTER
DATA
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OUTPUT REGISTER
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PARAllEl
ENABlE
C
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DOT RATE
CLOCK
lINF
COUNTER
LINE
DIVIDER
COLUMN
COUNTER
'0
iii
<1/1
DOT/COLUMN
DIVIDER
III
FIGURE 4. Typical 7 x 5 Vertical-5can Display Generator Subsystem
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C.
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The MM5240 expands straightforwardly in 64·
character increments to larger fonts, such as the
9 x 7 or 10 x 8 arrays in Figure 5A. An expansion
such as Figure 58 would be used to provide a full
set UC/ LC font. These expansions keep the
character rate the same as at 5 x 7, whereas
doubling the size of each monolithic ROM would
not.
However, the chief attraction of this conversion is
in UC/LC applications. Figure 7 shows how to
use three ROMs to generate 96 7 x 9 to 8 x 12
horizontal·scan characters-a 25% savings compared
with a "full set" expansion. The chip·enable inputs
are programmed to sense the sixth and seventh
cnaracter·address bits. External decoders aren't
needed.
32-CHARACTER BLOCKS
If each ROM in Figure 7 is replaced with a parallel
assembly of three ROMs (24 outputs), the result
is a 24 x 12, 96-character vertical-scan generator
with the same character rate as at 8 x 12. In other
words, the 32-character approach maintains the
benefits of parts standardization and performance
up to a very high resolution.
A similar expansion of the MM5241, as in Figure
6A. would provide 7 x 9 to 8 x 12 horizontal-scan
fonts. However, the direct 64·character expansion
places a ROM-enabling operation in the middle of
the character. Such operations are common in
large-font generator designs.
A simple solution to this problem is to "steal"
a character-address input, use it as a row-address
input, and then use a chip·enable input as a
character input (Figure 68). This provides a 32·
character or 64-character block enabled during the
between·characters spacing interval. A 32·character
block would be the only ROM required in a
system using only numbers and symbols.
Other ROMs can be used in this fashion. In Figure
8, the MM5227 TRI·STATE@and MM5288 256 x
12 ROMs are shown in expansions that comple·
ment those of the MM5241. These ROMs provide
access times well under a microsecond. For rates
in the nanosecond range, general-purpose bipolar
ROMs with four or eight outputs, such as the
DM8597 256 x 4 and DM8596 512 x 8 can be
worked into similar organizations.
13-53
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- - - - - . COLUMN
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REGISTER
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ADDRESS
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OUTPUTS
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SPACE
(A) 9 x 7 or 10 x 8 Vertical-Scan, 64-Characters
II)
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(B) 9 x 7 or 10
X
8 Vertical-Scan, 12S-Characters
FIGURE 5. Expansion of MM5240 to Larger Fonts
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1/2
CHARACTER o-.-If-+--.J
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12345"78
•
•
•
•
••
eOl'N01
0 0 1
00,oADM
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•
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.010
ROM.
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(A) 7 x 9 to 8 x 12 Horizontal-5can, 64-Characters
(8) 7 x 9 to 8 x 12 Horizontal-Scan, 64-Characters
FIGURE 6. Conventional and Improved MM5241 Expansions to 8 x 12
13·54
ROW
ADDRESS
A, - As
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0 - -.......
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OUTPUTS (EACH ROM)
.......:i
o
0
o
:
......
.:
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ROW
ADDRESS
00
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CD
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CE PROGRAM FOR ASCII
ROM NO.1 Ae = D. AJ = 0 (CAPITAL LETTERS)
ROM NO.2 A6 = 1. AJ ~ 0 (NUMBERS. SYMBOLS)
ROM NO. J A6 ~ 1. AJ = 1 (LOWER·CASE LETIERS)
2"
r+
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c=
0
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FIGURE 7. USing 32-Character Expansions for 7 x 12 or 8 x 12. 96-Character Generator
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Theoretically, they could all have been unique,
since there is a possible pattern variation ranging
from 128 to 65,536 (2 7 to 2 16 ). UC/LC and
horizontal·scan fonts are more variable than upper·
case vertical·scan fonts, but they are still far from
worst-case.
This analysis led to the organization in Figure 9A.
Instead of doubling the 64 x 12 x 8 organization to
produce fonts up to 16 x 12, it adds only a 2k
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PARALLEL
TO SERIAL
CONVERTER
MM52l1
256_8
COLUMN
GENERATOR
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CHARACTER
INPU1DAIA
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113456769101112
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CLOCK-II
(AI 12 x 16 Vertical Scan (UCI
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This last word includes an EOe bit. When EOe
and the time-out state of the master counter
coincide, gate 1 clears the address counter. Now
address 0000 0000 generates the space pattern in
two spacing columns. When the master counter
reaches its second state, gate 2 enables the address
counter's parallel preset inputs. Finally, the input
ROM sets the counter to the star.ting address for
.I and the process continues through I, M and B.
Proportional spacing is inherent. So is high-speed
since the input ROM is a small bipolar array. The
main ROM can be either MaS or bipolar generalpurpose ROMs. This organization should also
expand efficiently since the repeat probability
tends to rise with matrix width.
In printing applications involving more complex
characters, the operational advantages might be of
more interest than ROM savings. For example, two
64 x 6 x 8 or 512 x 8 ROMs might be used as an
Ue/Le generator with the ninth address input a
direct shift control:
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Sl'ACE CODE
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0000
COUNTER OUTPUT
(4 LSB)
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12 • •
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COLUMNS
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1234 S 6 7 8 910
.. ......... ........
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...
.. ....
....
:: .... .... .. ..
:: !! -:,:- ii ::::::.
.... ......
..
..:: :::: :::: .........
......
.........
......
......
..
REPEAT CODE 1032103210
(13xl0i
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Eoe CODE 0000001 , 1 1
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(Repeat Pattern Character Quality and Coding Example)
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CHARACTER
DATA INPUT
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OM7488
(2 REDI
CHARACTER
MEMORYo---------++-----.J
CLOCK OUTPUT
CLOCK
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"0"';",.
I I cs~ .. CSM~5262
On
!/
L--
DATA
fOR MEMORY EXf,{NSHlN CONNECT OM74154
AS FOLLOWS'
/
11~13""~
REFRESH
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CSM.MSZfi2
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DATA ENABlE
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T2
-fg~tatatL _____________________ J
FIGURE 4. 8k x 16 Memory Module
USE OUTPUTS
OM1096
OM7098
I
DM1400
OM7402
OM1411
i
DM742n
DM7474
I
I
I
lM168
MHOO26
I
h--1
c~ .. ,",.,.M5262 /
I
~ _ _ _ J ~~"_~_____ J
IL ~Yor:~!::~8lE
____ ,
USE OUTPUTS
USE OUTPUTS
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41hBk USE OUTPUTS
-/
2n~8k
J,dBk
0"1741&4
OM75&4
OMllll02
MM5252
I
ENABLE,
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P=l,~rGURE~)~ 1>:1
IT 1" J 1+5.0v-tRIW
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DM7402
13-62
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8s -8"
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2
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Application Notes/Briefs
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CUSTOM ROM PROGRAMMING
IC
III
3
3
INTRODUCTION
entering ROM codes that it is clear which logic
level is used. National has programs to convert
NEGATIVE logic to POSITIVE or POSITIVE to
NEGATIVE so ROMs can be entered in either
logic bm the customer must specify which logic
it is.
Custom ROM programs are submitted to National
in three formats: paper tape, punched cards or
truth table with punched cards being the preferred.
These programs are converted into machine Ian·
guage and outputted on a magnetic tape. This
magnetic tape is used to make the programmable
gate mask and the test tape. Wafers are held in
inventory at gate mask. The wafers are then com·
pleted using the custom gate mask and tested at
the wafer level. The wafer is then scribed and the
good dice assembled. After assembly the units are
tested using the custom test tape to assure the
correct output pattern for every address.
DEFINITIONS
Logic Definitions
NEGATIVE Logic: "0" ; VH ; the more positive
voltage. "1" ; V L ; the more negative voltage.
When MOS was in its infancy the design engineers
called a logic ONE a low voltage because a p.
channel MOS transistor is turned on with a negative
bias applied. This became known as NEGATIVE
logic and was the opposite of TTL's POSITIVE
logic. As the MOS technology evolved and TTL
compatibility became a reality it became desirous
to use the same logic in MOS as in TTL. Therefore
the first ROMs to come out were specified in
NEGATIVE logic and the new ROMs are specified
in POSITIVE logic. Extra care must be taken in
POSITIVE Logic: "0" ; V L ; the more negative
voltage. "1" ; VH ; the more positive voltage.
Input Output Definitions
Address: A, is the least significant input address
on ROMs. Lo is the least significant input address
on character generators.
Outputs: 8, is the least significant output.
INFORMATION NEEDED
So that National can better serve its customers the following information must be submitted with each ROM
code.
NATIONAL PART NUMBER
National Semiconductor Corporation
2900 Semiconductor Dr., Santa Clara, CA 95051
Phone (408) 732·500
ROM LETTER CODE (NATIONAL USE ONLY)
TWX 910-339-9240
NAME
DATE
ADDRESS
CUSTOMER PRINT OR 1.0. NO,
I
CITY
TELEPHONE
STATE
I
NAME OF PERSON NATIONAL CAN CONTACT (PRINT)
I
ZIP
PURCHASE ORDER NO.
AUTHORIZED SIGNATURE
I
DATE
13·63
~
IC
C)
c
E
TRUTH TABLE FORMS
E
Use the appropriate form for submitting truth tables.
~
C)
...o
0..
Form I
MM3501
MM5201
MM5202
MM4203/MM5203
~
oa:
E
OUTPUT CODe NOTE: 1
ADD-
~
RESS
MM5204
MM4210/MM5210
MM4211/MM5211
MM4213/MM5213
B8
B7
B6
85
B4
83
82
MM4214/MM5214
MM4220/MM5220
MM4221/MM5221
MM4230/MM5230
LS8
B1 SUM
MM4231/MM5231
MM4232/MM5232
MM4233/MM5233
OUTPUT CODE
ADDRESS
88
87
86
85
84
83
82
LS8
81 SUM
_50
~
__ 1
_51
_
52
(,)
o
o
__ 3
~
_
53
_
54
_55
_
56
z
«
__ 7
57
_58
__ 9
59
_10
60
11
_61
_12
_62
_13
_63
_14
_64
_15
_65
16
_66
_18
_
67
68
_19
_
69
_20
_
70
_17
71
_21
72
_22
73
74
_23
_
_24
__ 25
_75
_76
_
77
26
27
28
78
_29
79
30
80
81
_82
_32
_83
_34
_84
_35
85
_36
_37
_86
_
87
_38
_88
_39
_89
40
90
41
91
_42
92
_43
_93
_44
_94
_45
_95
46
_96
_47
_97
_48
_98
49
_99
T8
T8
Note 1: The Appropriate Logic Level box must be checked or order will not be accepted.
o POSITIVE Logic on Addresses and Outputs
o NEGATIVE Logic on Addresses and Outputs
Note 2: The MM4232/MM5232 and MM4233/MM5233 have programmable chip selects and the logic level to enable the
chip must be specified. CS 1 ~ CS 2 _ CS 3 _ CS 4_
Note 3: TB is the total
"1" bits in a column expressed in Decimal.
Note 4: SUM is the total "1" bits in a row expressed in Decimal.
13·64
»
z
...
I
Form II
o
o
(')
c:
~
MM5212
MM5215
MM4229/MM5229 (Positive logic only)
o
3
::u
o
OUTPUT COOE NOTE: 1
ADD·
812 811 a10 B9
RESS
B8
B7
B6
B5 BO
B3
LSB
B2 B1 SUM
ADD·
RESS
0
1
50
51
2
52
53
3
4
_
5
55
56
_57
OUTPUT CODE NOTE: 1
812 B11 810 B9
B8
B7
B6
B5 BO
B3
LSB
B2 B1 SUM
a
cc
...
I»
3
3
64
6
7
8
s·
CC
58
._59
9
10
"
_12
_
60
61
62
_
64
13
63
14
15
65
16
66
67
68
17
_
18
19
69
20
70
21
71
22
_
23
24
25
73
74
_75
26
76
_77
27
28
72
29
78
_79
30
31
_81
80
32
82
_83
33
_34
84
35
85
36
86
87
37
38
41
88
89
90
_91
42
_92
39
40
43
93
44
_94
45
95
46
47
_96
97
_98
48
99
49
TB
TB
Note 1: The Appropriate Logic Level box must be checked or order will not be accepted.
o
o
POSITIVE Logic on Address and Outputs
NEGATIVE Logic on Address and Outputs
Note 2: The MM4229/MM5229 has programmable chip selects. Specify the Logic Level to enable the Chip (Positive Logicl
CSl
CS2
~
."
CS3
Not8 3: TB is the total "'" bits in a column expressed in Decimal.
Note 4: SUM is the total "1" bits in a row expressed in Decimal.
13·65
CD
c:
E
E
~
.
r-------------------------------------------------------------------------~
Form III
MM4240/MM5240
CD
o
Il.
:i!
o
CHARACTER
ADDRESS
(DECIMAL)
CHA.RACTER
-,
_0
a:
LINE
ADDRESS
(DECIMAL)
ADDRESS
(DECIMAL)
010
a~
:::I
·3
·2
SUM
CHARACTER
LINE
ADDRESS
(DECIMAll
ADDRESS
(DeCIMAL)
_8
0
,
'"'
2
S1/1
., .,
OUTPUT WORD
0
,
E
.,
1
(.)
o
o
7
2
3
3
,
,
,
_5
7
_9
0
0
,
2
,
\
1
100
,
,,0
I
I ,
~+ --l
5
6
,"
_2
o
6
7
7
- -
_6
0
\
\
I
,
i
I
3
,"0
,
001
2
\
2
3
3
----1---=--
7
BS SUM
6
I ,
a~
·3
,
7
",
«
·2
,
2
•
'7
Z
.,
OUTPUT WOAD
B,
I
\
T.
\
,
,
6
7
",
_3
0
'"'
,
'01
7
_7
0
,
2
3
01 ,
3
,
•
•
,"
7
7
TB
TB
Note 1: A logic "1" = most negative voltage. A logic "0" = most positive voltage.
Note 2: Line address (L o , L j , L 2 ) are the row or column select lines in a character generator application. I n a read only memory application, As shall be considered the MSB and La the LSB.
Note 3: TB is the total "1" bits in a column expressed in Decimal.
Note 4: SUM is the total "1" bits in a row expressed in Decimal.
13·66
l>
...
:2
I
Form IV
o
o
MM4241/MM5241
CHARACTER
ADDRESS
(DECIMAL)
_0
LINE
ADDRESS
DECIMAL
C')
OUTPUT CODE
LS8
81
82
83
84
85
86
87
88
SUM
CHARACTER
ADDRESS
ADDRESS
(DECIMAL)
DECIMAL
LINE
_5
0
LS8
81
c:::
OUTPUT CODE
82
83
84
B5
B6
B7
88
SUM
0
Ll LI La
o 0 0
:lJ
1
1
o
001
s:
...
o
to
...
I»
2
2
010
3
01 1
4
- f--
1--
3
--
"'0
4
100
5
5
-,
1 1 0
_6
2
4
100
to
-f---
010
01 1
s·
1
1
001
3
3
3
0
0
000
2
1
3
i
4
I
5
5
1 1 0
_2
_7
I
0
000
0
I
I
1
06,
o~o
3
01 1
4
100
2
I
I
I
I
3
i
5
5
,------0
_8
0
000
1
1
f---2
010
I
3
01 1
4
5
101
0
!
3
4
100
_4
I
I
c-------
001
2
,
4
I
1 1 0
_3
~
o
3
5
_9
1
2
3
4
5
T8
0
-+I
1
2
3
4
5
T8
Note 1: On the character address and output word negative logic is used:
A logic "1" most negative voltage
A logic "0" most positive voltage
on the line address positive logic is used:
A logic "a" most negative voltage
A logic "1" most positive voltage
Note 2: Line address (L o , L 1 , L 2 ) are the column select lines in a character generator application. In a read only memory
application A6 shall be considered the MSB and Lo the LSB.
Note 3: TB ;s the total "1" bits in a column expressed in Decimal.
Note 4: SUM is the total "1" bits in a row expressed in Decimal,
13-67
C)
c
E
TAPE ENTRY FORMAT
ca
Tape format for the following ROMs.
.
E
MM3501
MM4210/MM5210
MM4211/MM5211
MM4213/MM5213
C)
e
11.
MM4214/MM5214
MM4220/MM5220
MM4221/MM5221
MM4230/MM5230
"s. MSB
Note 5
~
MM4231/MM5231
MM4232/MM5232
MM4233/MM5233
Note 6
oa:
Note 8
2 Spaces-+-'==,
E
---',-Note3
SIII
OOf)'1nnnn
ni010lfJ I
0011111 I
:::I
(.)
Note 2
1 Space
nWlI llMl
o
o
0'lr)0f)r)fl'l
OfJ111IOO
4
~
00'H10I)O()
n
DIDI/HOI
4
l\(1f)
wo;"
A-'5~
z
c(
n
;.1')1)6
_'I'Jr)"l
TB~
14n _ _ _ _ _ _-j-_Note 4
fS7 I:,n
IS .... ?51l
HIS
40
r94 (lin
rA3 I no
1E<<:' 1">5
fBI 19·'
--'========j--l Space
L __
a·BIT TAPE FORMAT
Note 1: The code is a 7-bit ASCII code on 8 punch tape.
Note 2: The ROM input address is expressed in decimal form an,d is preceded by the letter A.
Note 3: The total number of "1" bits in the output word.
Note 4: The total number if "1" bits in each output column or bit position.
Note 5: Specify product type.
Note 6: Must type POS logic, or NEG logic depending on which is used.
Note 7: LOGIC ON ADDRESS AND OUTPUTSmust be the same (either
pas
or NEG).
Note 8: Specify the pattern necessary to enable the ROM on the ROMS that need chip selects.
Tape format for the MM5202, MM4203/MM5203 and MM4204/MM5204.
PROM TAPE P AND N FORMAT
Carnage returnhne feed
allowed betweeen F and B.
startCharacter-,stopCharacter, ( , Data FIeld"
t I
t
MSB{Pm11)
LSB{Pm4)
t
I
I
B PPPN P P N N FBN N P P N N PPF ... BNPNPNNNN F
Word 0
Word 1
All Address Inputs LOW
Word 255
-------------.
All Address Inputs HIGH
*Data Field: Must have only P's or N's typed between Band F. No nulls or rubouts. Must have exactly eight P and N
characters between Band F. Any characters except Band F may be typed between the F stop character and the B start
be rubbed out. Data for exactly 256 words must be entered, beginning with word O. P = "1" or the more positive voltage.
N = "0" or most negative voltage. When the MM4204/MM5204 is used the word length is 512.
PROM TAPE BINARY FORMAT
o
o
, - - - - - ; : - - - - - - - - -BIT 1
00
0
00
00
00
00
00
00
········fc·p·····
o
o
o
0
~
,
~WORDl
COMPLEMENT WORD 1
o
~
--BITS
COMPLEMENT WORD N
WORDN
COMPLEMENT WORD 0
WORD 0
START
Note 1: Tape must be all blank except for the 513 words punched.
Note 2: Tape must start with a START punch.
Note 3: Data is comprised of two words the first being the actual Data the second being the complement of the data.
Nota 4: A punch is equal to a "1" or most positive voltage and the omission of a punch is a "0" or the more negative voltage.
When programming the MM5202 or MM4203/MM5203 it should be remembered that the opposite logic from what is
programmed will appear on the output of the PROM. In otherwords a P on the tape will program a Logic "0" or YL in
the PROM.
13-68
»
z
CARD ENTRY FORMAT
MM3501
Card format for the:
MM4210/MM5210
MM4211/MM5211
~
MM4213/MM5213
MM4214/MM5214
MM4220/MM5220
MM4221/MM5221
MM4230/MM5230
MM4231/MM5231
MM4232/MM5232
MM4233/MM5233
o
o
(")
c
UI
S
3
12J4567891(l11121J14151611181920212223242526272829:JD313233343!i3637383940414243441546474849505152535455565750116960616263&166666768691071121374161677187980
:JJ
=-xL
l---------~----CS2
~~3
o
_______________~ ___________--j
----.~~
~
'x
"'tI
a
...
CQ
t-::-:~c__----------------------
------------~--~-----------1
I»
3
3
~-~:o·'~:~-------------------
:;,
CQ
~~~,=~~.-------------------~-------------------~
1 . . . - - - I l 1 0•• 4
Note 1;
Punch three input addresses per card with the first address in columns 1-25, the second in columns 26-50 and the third in columns 51-80.
Note 2:
The ROM input address is expressed in decimal form and is preceded by the letter A.
Note 3:
Note 4:
Note 5:
The total number of "1" bIts in the output word.
The total number if "'" bits in each output column or bit position.
Specify product type.
Note 6:
Note7:
Note 8:
Note 9:
Must type POS logic or NEG logic depending on which is used.
LOGIC ON ADDRESS, OUTPUTS AND CHIP ENABLE must be the same (eIther POS or NEG),
Leading zeros must be punched.
Specify the Chip Select Logic Levels that will enable the ROM where necessary.
Card format for the MM5212.
'234567891011121314151617181920.12223242526212B293031323334J536373B394041424344450464148496051 S253f>455565158596061 626364658667 68897011n73747576711819BO
"-,
Note
Note
Note
Note
Note
Note
1:
2:
3:
4:
6:
6:
Not. 7:
Note 8:
Note 9:
Punch three input addresses per card with the first address in columns 1-25, the second in columns 26-50 and the third in columns 51-80.
The ROM input address is expressed in decimal form and is preceded by the letter A.
The totsl number of "1" bits in the output word.
The total number if "'" bits in each output column or bit position.
Specify product type.
Must type POS logic.
POSITIVE LOGIC ON AODRESS AND OUTPUTS.
"'" more positive output. "0" more negative output.
Leading zeroes must be punched.
13-69
CI
c:
E
E
Card format for the MM5215.
r!!
CI
o...
Q.
12345678g101112131415TSll1S192U212223242526272829303132333435363738394Q414243444546474B495051 0253545556575859606 1626364656667f;86970711273747576771879BO
~'
No,.S
----------
::?!
oa:
ic=~c;:_------------
E
S
-----------------------------------------1
---------------------
ic=--:-c:--=-'-------------------- ------------------------j
I/)
:;,
TBO?
(,)
810
---------~------"-----".--------
~-
------------------------------_._--_._-._---------._----~~~-----~---------------------.. - - - , - - - - - - - - - . - - - - - - - - - - -
o
o
...
-'-""-'-'-"'-------------------------------- ---=~-==~:::~:::=---========---=
I
Z
«
---------------------------- ----------- -------_._-
- ------ -----
---------_._--._--
-
----------
~----------------
---------
-- - - - -- -
~ii7a91ii,1121314'51S17'8'92021n23,4252627282930313233;5435363138394041424344454<54'4849'50515253545556575859606162636465661i7686970717273747S76771B7980
Note 1:
Note 2:
Note 3:
Note 4:
Note
Note
Note
Note
Note
Punch three Input addresses per card with the first In columns 1--25,
the second in columns 26-50, and the third in columns 51-80.
The ROM input address is expressed in decimal form and IS preceded
by the letter A.
The total number of "1" bits in the output word
The total number If "1" bits m each output column or bit position.
5:
6:
7:
8:
9:
Specify product type.
Must type negative logic
NEGATIVE LOGIC ON ADDRESS AND OUTPUTS
"1" more negative output. "0" more positive output.
Leading zeroes must be punched
Card format for the MM4229/MM5229.
ic=~-----------------------------------
----------------- ------- -- -------- - - - - - - - - - - - - - - - - - 1
~:~::~:~:~:~;~;~:~;~;~;~;~:~;~;~;~"~'_ _ _ _ ~~~"~'~O
111111
1 0
1 0
\
0
1 01
0
I
-' -"---'11
I
11
- 12
.----.-.----~-
I
._--i c = - : - - : - - : - - - - - - - - - - - - - - --- ------- --------.F~"----------- - - "---.----~.--~
---------------------- -
-
-- ------ ----- -----.----.--..
-----~-
ic=~,_;_-------------------------------I=;-,~;c;__---~~----------------------
ic=~cC---------------
--
- -- - - - - - - - - - - - - - - - - - - - - - - - - - - - j
- - - - - - - - - - - - ---- - - - - - - - - - - - - - - - - - - ------------------------i
ic=c-:-:-:-------------------------- ic=~cc_-------------
I----~;__---------------.------.--.----------------.-----------I
I-+--~'------------------.--------------------------i
I--c:c:---'---------------------------------------------
Note
Note
Note
Note
Note
1:
2:
3:
4:
5:
Note 6:
13-70
The code is Hollerith as punched on IBM Model 029,
Corresponds to Pin 16
Corresponds to Pin 15
Corresponds to Pm 14
The ROM input address is expressed In decimal form and
preceded by the letter A
All 256 address (0-255) must be coded.
Note
Note
Note
Note
IS
7:
8:
9:
10:
The total number of "1 '5" in each Input word.
The total number of "1'5" in each output column.
Leading zeros must be punched.
The customer may use his own 10 designation if he does not
punch the first column.
Note 11: Positive logic on address and outputs "1" more positive
voltage "0" more negative voltage.
s:
o
CJ)
Application Notes/Briefs
...O:J
ai'
....
....
o
TRIG FUNCTION GENERATORS
Accuracy is the major design variable of trigonometric lookup tables built with MaS read-only
memories. Only a few ROMs are needed for most
practical applications, but accuracy can be made
to increase very rapidly with memory capacity if
interpolation techniques are used.
For instance, without interpolation a single
1024-bit ROM can store 128 angular increments
and generate an 8-bit output that will be better
than 99.9% of the handbook value (Table 1).
1"---;,1
I
I
I
I
I
I
I
I
I
I
...
-I
cS'
."
c:
n
WIIIEOOA
OUTPUT
::1
::.
o
::1
G)
CD
::1
BINARY
DECIMAL
ADDRESS
DEGREES
OUTPUT
SINE
0
1
2
3
0
0.1
2.1
.00000000
.00000011
00000110
00001001
0.000
0.012
0,023
0.035
127
89.3
",11111
0.996
1..
...
CD
...
II)
o...
III
(a)
TABLE ,_ MM422BM/MM522BM Sine Function Generator
1--+_---,-'
L~i;:'-',-,r'
If one simply cascaded ROMs to improve input
resolution and output accuracy for a high-accuracy
trig solution (X=sin e) as in Figure 1, large numbers of ROMs might be needed. This 24-ROM
system stores 2048 12-bit values of sin x (or other
trig functions). giving angular resolution of 1 part
in 2" (0.05%) and output accuracy of 1 part in
2' 2 (0.024%). The system in Figure 2 has the
same resolution and is accurate to the limit of its
12 output bits (0.024%), which makes it just as
good. But it only requires four 1024-bit ROMs and
three 4-bit TTL full adders, so it only costs about
one-fifth as much as the more obvious solution of
Figure 1.
Instead of producing x = sin 0, the Figure 2 system
divides the angle into two parts and implements
the equation
x = sin 0 = sin (M
+ L)
= sin M cos L
+ cos M sin L
It can be programmed for any angular range.
Assume the range is 0 to 90 degrees and let M be
the 8 most significant bits of and L be the 3 least
significant bits of 0 (0 being the 11-bit input
angular increments, equal to 90°12048, or
0.044 deg.) as in Table 2.
e
With an 8-bit address, the three 256x4 ROMs will
give the 12-bit value of sin M at increments of
M = 90° 12 8 , or 0.352 deg. The cos L can only vary
between 1 and 0.99998. So we assume cos L=l
and store values of sin M at 0.352 deg. resolution
(bl
FIGURE 1. Conventional 2048·lncrement Sine Table Uses
24 ROMs
13-71
....
I/)
o
in the top three ROMs, reducing the equation to
III
Q)
sin () = sin M + cos M sin L
Q)
Values of the second term are stored in the fourth
ROM. The maximum value of the second term in
the above equation can only be cos Msin L
= 0.00539 where cos Mmax = 1, sin Lmax
= 0.00539. This is the maximum value to be added
to sin M above. Only the five least significant bits
of a 12-bit output are needed to form the maximum output, so an MM522 is used in its 128x8
configuration.
c
CI
c
o
'.j:i
u
C
::I
U.
C)
'L:
I-
~UT
o
....
,-.
,.,
DMB283
ADDER
4NEXT
,-.
MDSTS.GHITS
Q)
'L:
m
~OUT
o
,.,
Since we are using an approximation, accuracy is
not quite as good as the Figure 1 system. The
additional error term is cos L, assumed 1 but
actually is a variable between 1 and 0.99998. At
every eighth increment, L is zero, making cos M
M
ADDRESS
M.
L
0
1
2
3
0
1
I 0
I 1
1 o 0
1 0 I
1 1 0
1 1 1
1 o 0 0 M '" 0.352°
1 o 0 I
,
5
6
7
•
~g
"--,6
32
64
128
256
512
102'
2048-1
I
1
I
1
I 0
1 o 0
1 1 1
1
o
o
0
0
0
0
0 o
0 o
0 o
1 1
o
0
0
0
0
0
I 1
o
0
0 o
0 o
0 o
0 o
0 o
0 o
1 1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
,;
o
TABLE 2. Programming of 2048-lncrement Sine Table
:E
r'
,-,
~DUT
,..
sin L=O, and sin x=sin M to 12-bit accuracy. Then
the error rises to a limit of near 0.002% at every
eighth increment where L is 0.352-0.044. This
error can be halved by adjusting the fourth ROM's
output so that
Z~ID
0,..283
ADDER
roo
sin () = sin M + cos (M-2.81°) sin L
2-12
3LEAITSIG8ITS-1
(1Z8x8MDDE)
MM522 in 128 X 8 MODE generates CDS (M4 - 2.81
sinl3MM5211BneratesinM
sinO "sin M+cos (M4 -2.BI sin l
FIGURE 2. Four-ROM LoolH
levels.
Output Source Current: The current which flows
out of the output terminal of the register when the
output is a logical High level. Conventional current
flow is assumed.
Clock Pulse Falltime, tt: The time delay between
the 10% to 90% voltage points on the clock pulse
as it traverses between its logic Vq,H and logic VL
levels.
Clock Pulse Width,
c..
n
~
1--0,310--1
I,
2
l
II--0125+0.025~I
1
-T
-T
0.280
MAX
0.270
MAX
GLASS
- .---
I I
0046
1--
~O.005 -I
MAX
.
1
0.730
MAX
GLASS
'-
I
°Ml:~
0,045
PlN'~~N:-,,~-r.,0.
r
~:~~~
--'r~
'0I.5
I
I~
-0.015
---L
i IIII
I
0.030 ___
:to.OID!
i
0.115 MIN
I
'----j~_O.015
!:~:~~~_I
C
0.019
Package 2
l4-Lead Cavity DIP (D)
Package 1
8-Lead Cavity 01 P (D)
r- _.
i
0.730
MAX-'
GLASS
-·~I
!
02110
PIN NO.l __
IDENT --
MAX
t
o.llD
_I
MAXi
--j
I,
PINNO.,.
I
IDENT ~
Fi
0.008
,
0.012,
---
L
i
I
0325 +0.025__
.
-0.015:
r-
0.037
I
0.050 -,
G.02D
to.OID
k
0.165
d _+~t
. - " . ,
--.-,
I
0.100
I
±O,OlO---"
1
I
0.015_1___
0.019'
__
-
O.OOB
t--
~ ~
0.115
MIN
ill'~
O.050---j I
O.11l0.-..J
0.300
REF
r--
:to.oIU·
Package 3
:to.ol0 -I
Package 4
l8·Lead Cavity DIP (D)
l6·Lead Cavity DIP (D)
[----.,'00._-_------1
i
22
21
211
19
18
M:X
16
15
14
13
Ii2II
-,
I
0.365
MAX
1
~r,'TT"+r..rr..rr.'rr"rr..~.'"''"~,, ~
I--- 0.410----1
A'
I
MAX
If-- 0.425+0.025
-0.015
~:::'-
I
_J
'
~~
' "O.OlD
0.008
0.012
0.025.
±O.010
JL
._1
.1
'
~fll00
__ It-.. 0018
, ' "
~0.002
Package 5
22·Le.d Cavity DIP (D)
14-4
''l'l
~
~ +0.012 ~!I
-+~~O,15
0125
MIN
II
IL
0.015
0.020 ----j I
0125
MIN
MAX
1.290
14
D
PIN NO.1
IOENT~
~6A_·:l
:~:~~~ "'-
c
0.5JO 0.550
MAX MAX
3'
CD
::::s
1/1
1
S'
::::s
MAX
:
1/1
0.200
MAX 0.050
,
'-'T tOrO
mmrmm=-fl
0.008
0.012
-0.625
~Tr
0.610
1-
r'-----
~
131
I
±~:~!~ ·-1 ~ -
---j
I
-j
I
~ t~:~~~
:1
-1 ~ t~:~~~
0.125
MIN
Package 6
24-Lead Cavity DIP (D)
MAX
1.400
-T
I
0.5JO
Mr
T.r-n'T""TITT7T"Tii::;:m;:r:::r.rTITiion;;n;;n;;r"TiiT' _1
0.475
r;-OM·6~XO_--·I'
1r
I
f--
.. -0.625
1--...
I
~
SOUARE·TVP
-! ...
1.l-I
0,045
TVP
0.200
.~~iT
+TYP!V VVVVVVVVVVVVtO~5
0.010
00"55~- _-j
+O_0 .
1
O.05o.J
to.Ol0
I
r--
__I
1
11.100
to.Ol0
__ I
L
0.018
I . !.0.002
MIN
Package 7
28-Lead Cavity DIP (D)
RAO
0.032
Package 8
40-Lead Cavity DIP (D)
14-5
VI
I:
.2
VI
I:
Q)
E
c
0.025
0.025
RAD
RAD
ca
.2
VI
>
..r:.
D..
0.200
I
I
O.100~ f--
I
0.385
!----- ±0.1I25---l
10.010
Package 10
16-Lead Cavity DIP (J)
Package 9
14-Lead Cavity DIP (J)
i----~-~~~---·-------1_f ~6:~
i5l Ii4l rm I
I
24
23
22
21
20
19
18
17
16
GLASS
0.025
I
RAD-~
0.515
0.525
I
I
~~rr,~~r.nr,n~~~~~-L
0.200
I
If-----tD.025----1
""
I
0.100
l--~O.010
II 0.018
---0--+ 0.002
a~D
~~
0.125
MIN
Package 11
24-Lead Cavity DI P (J)
~
'------1.490MAX--~"---::l
"""""""" '""""" " -f
0.600
MAX
GLASS
I
0.025
RAD
0.515
0.525
I
i
0.060
O.100--l
i
I--
0.100
'O,010
--iI
>---I
PackagellA
28 Lead Cavity DIP (J)
14-6
".. JIf--
'0002
I
~'h
----jf-- O.OlB
iO.D02
0.125 0.070
MIN
"'tI
:::r
.r:;
~=rr
Il..
~O.130
---r ~~~O
±O.OOS
Of-I
Ir---.(1425+0.025
I
-D.01S------j
0.050---i
±O.DIS - I
~
-
I
I __
r-
0.100
I I
±o, 010 --l
f--
Il-
0.018
±D.OOJ--J
O.l~
MIN
Package 17
22-Lead Molded DIP IN)
1
0.063
'AD
0.540
J'
~~~rrrTrr~~.fT.,~~.=rr.~,"~,~,,~~,,~I
.,.270MAX------4
rr D6ODH~
~O.'60
-0620--
r
Ii~~~; J'
I
_ - 0 6 2 5 +0.025 _ _ 11
1
.
0.075
-0.015
:to.015
I
f--
----1
1--0.100
TYP
I~
~
__L
JJ.s
0.018
±HOro
~11~!i
MIN
Package 18
24-Lead Molded DIP IN)
1
11.062
'AD
PINNO.lINDENT
0.550
~~~J'
".1
1--------1.470MAX------~_.j.
Package 19
28-Lead Molded DIP IN)
14-8
1
0062
RAD·
PINND.lINDENT
0.550
c
br.r~r=r.r;~=r;r'i~=;;n;;rr.;r~;;rr.;r=r.:rr.~"f.':Ff.:;A]5
3'
~
::s
(/I
1------------Z.070MAX-----------I1
0'
::s
(/I
Package 20
4O-Lead Molded DIP (NI
r
'L'-r, - r.'1"-=-,-,'r" "- r.r-r;n-;rl. ,- r, ", ;n; ~
I
----r
I~~
0.180
MAX
----.-t
0.020
r-
---r
0.100--1
I--
----11--0.019
---+
0.125
Package 21
24-Lead Quartz Lid Cavity DIP (QI
0.100
Package 22
4-Lead TO-72 Metal Can Package (HI
Package 23
S-Lead TO-5 Metal Can Package (H I
14-9
1/1
s::
,2
1/1
s::
r~:~~: DlA----I
Ii~:~~: I
ofLlcj ~:5,0
DIA
Q)
E
c
tr~
0~~1~
~ ~l
~ i~ ~:~~~
It!
to)
'in
I
0.016 DIA10LEADS'
>
..r:.
0.019
DtA
~
0..
Package 24
lO-Lead TO-5 Metal Can Package (H)
Package 25
l2-Lead TO-S Metal Can Package (G)
0.050
:to.005
PINNOl
IDENT~
II 0.D1~
--H-- O,019
I 0.020
f--. O.040
--i1~0."5
0.019
Package 25A
Package 26
lO-Lead Flat Package (F)
l4-Lead Flat Package (F)
Lo,02D
0.04(1
Package 27
14-Lead Flat Package (W)
INCHES TO MILLIMETERS CONVERSION TABLE
14-10
INCHES
MM
INCHES
MM
INCHES
0.001
0.0254
0.010
0.254
0.100
2.54
0.002
0.003
0.0508
0.0762
0.020
0.508
0.1016
0.762
1.016
5.08
7.62
0.004
0.030
0.040
0.200
0.300
0.400
10.16
0.005
0.006
0.007
0.008
0.1270
0.1524
0.1778
0.2032
0.050
0.060
0.070
0.500
0.600
0.700
12.70
15.24
17.78
0.009
0.2286
1.270
1.524
1.778
2.032
2.286
0.800
0.900
20.32
22.86
0.080
0.090
0."5
II
0.019--1[-
MM
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