1975_Fairchild_34000_Isoplanar_CMOS_Data_Book 1975 Fairchild 34000 Isoplanar CMOS Data Book

User Manual: 1975_Fairchild_34000_Isoplanar_CMOS_Data_Book

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•

FAIRCHILD SEMICONDUCTOR

34000lS0PLANAR
CMOS DATA BOOK

I=AIRCHILO
SEMICONDUCTOR

464 Ellis Street, Mountain View, California 94042
©1975 Semiconductor Components Group, Fairchild Camera and Instrument CorporatlOn/464 Ellis Street Mountain View, California 94042/(415) 962-5011 /TWX 910-379-6435

TABLE OF CONTENTS

SECTION

SUBJECT

1.

34000 Series CMOS General Description

2.

Design Considerations With 34000 Series CMOS

3.

PAGE
1-3

Introduction

2-3

Power Consumption

2·3

Supply Voltage Range

2-4

Propagation Delay

2·5

Noise Immunity

2·7

Interface to TTL

2·7

Input/Output Capacity

2·8

Output Impedance

2·8

Input Protection

2·8

Handling Precautions

2·8

A Word to the TTL Designer

2·8

Technical Data
Numerical Index of Devices
Selector Guide by Function
TTL to CMOS Comparison Guide
Cross Reference Guide
34000 Series CMOS Family Characteristics
Definition of Symbols and Terms
Data Sheets

3·3
3··5
3·7
3·15
3-17
3·21
3-23

(See numerical index of devices for page numbers)
4.

Products Planned for 1975
Numerical Index of New Products

4-3

Preliminary Data Sheets

4-5

(See numerical index of new products for page numbers)
5.

Bipolar Interface Circuits for CMOS

6.

Fairchild Ordering Information and Package Outlines
Packaging Information

6-3

Matrix VI Program

6-5

Unique 38510 Program
Package Physical Dimensions
7.

5·3

Fairchild Field Sales Offices and Distributor Outlets

6-8
6-13
7-1

34000 SERIES CMOS GENERAL DESCRIPTION

1-1

34000
SERIES CMOS

•
ISOPLANAR C
The Fairchild CMOS logic family uses Isoplanar C for high perform-

GENERAL DESCRIPTION - Fairchild CMOS logic combines the
popular 4000 series functions with the advanced Isoplanar C process.
The result is a logic family with a superior combination of noise

ance. This technology combines local oxidation isolation techniques
with silicon gate technOlogy to achieve an approximate 35% savings in

immunity and standardized drive characteristics. At static conditions,
these devices dissipate very low power, tYpically 10 nW per gate. The
low power combined with the wide (3 to 15 V) recommended
operating supply voltage requirement greatly minimizes power supply
costs. The CMOS family is designed with standardized output drive
characteristics which, combined with relative insensitivity to output

area as shown in Figure 1-1a. Operating speeds are increased due to the
self-alignment of the silicon gate and reduced sidewall capacitance.
Conventional CMOS circuits are fabricated on an n-type substrate as
shown in Figure 1-1b. The p-type substrate required for complementary
n-channel MOS is obtained by diffusing a lightly doped p-region into
the n-type substrate. Conventional CMOS fabrication requires more
chip area and has slower circuit speeds than Isoplanar C CMOS. This is a
result of the n+ or p+ channel stop which surrounds the p- or
n-channels respectively in CMOS, Silicon gate CMOS (Figure l-1cl has a
negligible reduction in area, though transient performance is improved.

capacitance loading, simplify system design.

•
•

•
•

•

•

LOW POWER - TYPICALLY 10 nW PER GATE STATIC
WIDE OPERATING SUPPLY VOLTAGE RANGE 3 TO 15 V RECOMMENDED
18 V ABSOLUTE MAXIMUM
HIGH NOISE IMMUNITY
BUFFERED OUTPUTS STANDARDIZE OUTPUT DRIVE
AND REDUCE VARIATION OF PROPAGATION DELAY
WITH OUTPUT CAPACITANCE
WIDE OPERATING TEMPERATURE RANGE
COMMERCIAL
_40°C TO +85°C
MILITARY
_55°C TO +125°C
HIGH DC FAN OUT - GREATER THAN 50

Fig. 1-1 •.

ISOPLANAR C CMOS STRUCTURE
REDUCES AREA 35%

N·SUBSTRATE

Fig.l-1b.

N-SUBSTRATE

CONVENTIONAL METAL GATE CMOS STRUCTURE

Fig.l-lc.

1-3

CONVENTIONAL SILICON GATE CMOS STRUCTURE
REDUCES AREA 8%

34000 SERIES CMOS
FULLY BUFFERED CONFIGURATION DESCRIPTION

Fairchild CMOS logic is designed with the system user in mind. Output buffering is used on all devices to achieve high performance,
standardized output drive, highest noise immunity and decreased ae sensitivity to output loading. Figure 1-2 illustrates a conventional
unbuffered 2-lnput NOR Gate_ Either n-channel transistor connected to VSS (ground) conducts when either input is HIGH, causing the output
to go LOW through the ON resistance of the device_ If both inputs are HIGH, both n-channel devices are on; effectively halving the ON
resistance, thereby making the output impedance (and hence fall time) a function of input variables. Similarly the p-channel devices are

switched on by LOW signals; Le. when both inputs are LOW, conduction from VOD to the output will occur.
Since the p-channel devices are in series, their ON resistance must be decreased (larger chip area) to hold output HIGH impedance within
specification. As the number of gate inputs increases, even larger p-channel devices are required, and the output impedance to VSS becomes
even more pattern sensitive.
A conventional unbuffered CMOS 2-lnput NAND Gate interchanges the parallel and serial transistor gating to achieve the NAND function
(Figure 1-3). The changes in output resistance then move to the p-channel transistors connected to VDD, while the n-channel devices must be
increased in size due to their serial connection.
Fairchild CMOS uses small geometry logic transistors to generate the required function which drive standard low impedance output buffers
(Figures 1-4 and 5). This technique reduces chip size, since only two large output transistors are required and rise and fall times are independent
of input pattern. Buffered outputs also increase system speeds and make propagation delay less sensitive to output capacitance. Figure 1-6
illustrates typical propagation delay vs. output capacitance for conventional and buffered CMOS Gates.
Another advantage of the Fairchild approach is improved noise immunity. Because of the increased voltage gain, nearly ideal transfer
characteristics are realized as shown in Figure 1-7. The high gain (greater than 10,000) also provides significant pulse shaping; the waveforms of
Figures 1-8 and 9 compare the output waveforms of conventional and buffered CMOS gates. For input transition times of 100 ns or less, the
outputs of both gate types are similar. When the input transitions are stretched to one microsecond, the conventional gate exhibits increased
transition times while the buffered gate has unchanged output transition times. This feature eliminates progressive deterioration of pulse
characteristics in a system. The combination of Isoplanar C a~ buffered outputs results in new standards of CMOS logic performance.

1---,--0 OUTPUT

1--+--0 OUTPUT

~:::D-o-- OUTPUT

:=Do--OUTPUT

Vss
Fig_ 1-2_

Fig_ 1-3_

CONVENTIONAL NON-BUFFERED
2-INPUT NOR GATE

CONVENTIONAL NON-BUFFERED
2-INPUT NAND GATE

Ao--+----f----'

Fig_ 1-5_

Fig_ 1-4_, FAIRCHILD 34001 FULLY BUFFERED NOR GATE

1-4

FAIRCHILD 34011 FULLY BUFFERED NAND GATE

34000 SERIES CMOS

Fig. 1-6
COMPARISON OF PROPAGATION
DELAY VS LOAD CAPACITANCE FOR
CONVENTIONAL AND FULLY
BUFFERED NAND GATES

..

Fig. 1·7
TYPICAL VOLTAGE TRANSFER
CHARACTERISTICS FOR
CONVENTIONAL AND FULLY
BUFFERED DEVICES

c:

~DDl15J

>

I 16

I 250 1--+--j----"1--t----'t--,.f--+---l

S

~

g

z
o

(!J

orx: 100~-+-'~~~~~+-~~4-~

:

10

1\

I 6.0

""

VDD =6

!5

1

6.0

15

~

W

~

....J

!:1

2.0

(!l

o....J

\

I~

~CONVENTlO~
\
"
..J.
If'
~ CMOS~ATE

0.1

o
o

1.0

L

1\ V " 1'-

W

>
W

....J

,

11" ~ V

4.0

....J

>
W

FULLY BUFFERED CMOS

,

1.0J'NPl/

>
4.0

o

10

INPUT VOLTAGE - V

Fig.1·9
NEGATIVE-GOING INPUT RAMPS OF
0.1 !,5 AND 1.0 1'5 APPLI ED TO
CONVENTIONAL AND FULLY
BUFFERED GATES

>
I

~EVlr

I--

V,N -

6.0 ~++-+-t-+-+-+-1I-+-""

U)
....J

~

FULLY
\j....----BUFFERED

6.0

pF

Fig. 1-8
POSITIVE-GOING INPUT RAMPS OF
0.1 !,5 AND 1.0!,5 APPLIED TO
CONVENTIONAL AND FULLY
BUFFERED GATES

1""--

I

~

o
o

l~

JlL

I;<'

~
CL - LOAD CAPACITANCE -

.1

VD~ = 1J~ ~DEVICE

!5
~
o

~ 150 1--+--j----"1r-,..r-::>oF--t-:;oo~=-r

tA = ~5°C

~

l ' lONV~NTIJNAL

w

(!J

~ 200 1--+--j----"1--'<--t-++--+--:¥'---I

I

tS

0.2

V

1-5

II
i"""I'

IINPYT'>

0.4

0.6

TIME -I's

TIME -I's

V

0.8

1.0

~~~I~~ cf~~~'DERAT'ONS WITH 34000

2-1

DESIGN CONSIDERATIONS
WITH 34000 SERIES CMOS

INTRODUCTION

Complementary MOS digital logic building blocks of SSI and
MSI complexity have been hailed as the ideal. logic family.
They are rapidly gaining popularity as more and more
manufacturers introduce increasing numbers of parts at
reasonable prices.
Originally designed for aerospace applications, CMOS now
finds its way into portable instruments, industrial and medical
electronics, automotive applications and computer peripherals,
besides dominating the electronic watch market.
In late 1973, Fairchild introduced the 34000 CMOS family,
using Isoplanar technology to achieve superior electrical per·
formance. Most of these devices are functional equivalents and
pin-for-pin replacements of the well-known 4000 series; some
are equivalent to TTL circuits and some are proprietary logic
designs.
A few CMOS devices, such as bidirectional analog switches,
exploit the unique features of CMOS technology; some take
advantage of the smaller device size and higher potential
packing density to achieve true LSI complexity; but most of
the available CMOS elements today are of SSI and MSI complexity and perform logic functions that have been available in
DTL or TTL for many years. Therefore, it is both helpful and
practical to compare the performance of CMOS with that of

the more familiar DTL/TTL (Figure 2-1). The TTL to CMOS
Comparison Guide in Section 3 lists numerous CMOS circuits
that are pinout identical to their TTL counterparts, others that
are functionally identical only, still others that are similar and,
in most cases, offer added features.
CMOS speed is comparable to 74L-TTL and DTL, and about
three to six times slower than TTL or Low Power Schottky
(LS-TTL). Voltage noise immunity and fan out are almost
ideal, supply voltage is noncritical, and the quiescent power
consumption is close to zero-several orders of magnitude lower
than for any competing technology.
POWER CONSUMPTION

Under static conditions, the p-channel (top) and the n-channel
(bottom) transistors are not conducting simultaneously, thus
only leakage current flows from the positive (VDD) to the
negative (VSS) supply connection. This leakage current is
typically 0.5 nA per gate, resulting in very attractive low
power consumption of 2.5 nW per gate (at 5 V).
Whenever a CMOS circuit is exercised, when data or clock
inputs change, additional power is consumed to charge and
discharge capacitances (on-chip parasitic capacitances as well
as load capacitances). Moreover, there is a short time during
the transition when both the top and the bottom transistors
are partially conducting. This dynamic power consumption is
74LS
LOW POWER
SCHOTTKY

34000

34000

DTL

9LS
LOW POWER
SCHOTTKY

CMOS
5 V SUPPLY

CMOS
10 V SUPPLY

33 ns

30 ns

5 ns

10 ns

35 ns

25 ns

35 MHz

3 MHz

5 MHz

80 MHz

40 MHz

5 MHz

10 MHz

10 mW

1mW

8.5 mW

2mW

2mW

10 nW

10 nW

NOISE IMMUNITY

1 V

1 V

1 V

0.8 V

0.8 V

2V

4V

FAN OUT

10

10

8

20

20

50'

50'

STANDARD
TTL

74L

10 ns

FLIP-FLOP TOGGLE
FREQUENCY
QUIESCENT POWER

PROPAGATION DELAY

'OR AS DETERMINED BY ALLOWABLE PROPAGATION DELAY
Fig. 2·1 CMOS COMPARED TO OTHER LOGIC FAMILIES

2-3

obviously proportional to the frequency at which the circuit is
exercised, to the load capacitance and to the square of the
supply voltage. As shown in Figure 2·2, the power
consumption of a CMOS gate exceeds that of a Low Power
Schottky gate somewhere between 500 kHz and 2 MHz of
actual output frequency.

SUPPLY VOLTAGE RANGE
CMOS is guaranteed to function over the unprecedented range
of 3 to 18 V supply voltage. Characteristics are guaranteed for
5, 10 and 15 V operation and can be extrapolated for any
voltage in between. Operation below 4.5 V is not very meaningful because of the increase in delay (loss of speed), the
increase in output impedance and the loss of noise immunity.
Operation above 15 V is not recommended because of high
dynamic power consumption and risk of noise spikes on the
power supply exceeding the breakdown voltage (typ>20 V),
causing SCR-Iatch-up and destroying the device unless the
current is externally limited.

At 100 transitions per second, the dynamic power
consumption is far greater than the static dissipation; at one
million transitions per second, it exceeds the power
consumption of LS·TTL. Comparing the power consumption
of more complex devices (MSI) in various technologies may
show a different result. In any complex design, only a small
fraction of the gates actually switch at the full clock
frequency, most gates operate at a much lower average rate
and consume, therefore, much less power.

The lower limit of power supply voltage, including ripple, is
determined by the required noise immunity, propagation delay
or interface to TTL. The upper limit of supply voltage, including ripple and transients, is determined by power dissipation or
direct interface to TTL. The 34049, 34050 and 34104 provide
level translation between TTL and CMOS when CMOS supply
voltages over 5 V are used. While devices are usable to 18 V,
operation above 12 V is discouraged for reasons of power
dissipation.

A realistic comparison of power consumption between
different technologies involves a thorough analysis of the
average switching speed of each gate in the circuit. The small
static supply current, IDD is specified on individual data sheets
for 5,10 and 15 V. The dynamic power dissipation for 5,10
and 15 V, 15 and 50 pF may be found in graph form for
frequencies of 100 Hz to 10 MHz. The total power may be
calculated, PT ~ (I DD X V DD) + dynamic power dissipation.

Low static power consumption combined with wide supply
voltage range make CMOS the ideal logic family for battery
operated equipment.

Fig. 2-2
TYPICAL POWER OISSIPATION
VERSUS INPUT FREQUENCY FOR
SEVERAL POPULAR LOGIC FAMILIES

103

104

105

106

INPUT FREQUENCY -

107

108

Hz

______----'_J
2-4

Capacitive Loading Effect

PROPAGATION DELAY

Compared to TTL and LS-TTL, all CMOS devices are slow and
very sensitive to capacitive loading. See Figure 2-3. The Fair·
child 34000 family uses both advanced processing (lsoplanar)
and improved circuit design (buffered gates) to achieve propagation delays and output rise times that are superior to any
other junction-isolated CMOS design. (Silicon-on-sapphire,
50S, can achieve similar performance but at a substantial cost
penalty).

Historically, semiconductor manufacturers have always specified the propagation delay at an output load of 15 pF, not
because anybody considers this a representative systems
environment, but rather because it was the lowest practical
test-jig capacitance. It also generated the most impressive
specifications. TTL with an output impedance less than 100 Q
is little affected by an increase in capacitive loading; a 100 pF
load increases the delay by only about 4 ns. CMOS, however,
with an output impedance of 1 kQ (worst case at 5 V) is 10
times more sensitive to capacitive loading. Figure 2-4 shows
the positive- and negative-going delays as a function of load
capacitance. It should be noted that the older, unbuffered
gates have an even higher output impedance, a larger dependence on output loading, and do not show the same symmetry.

Isoplanar processing achieves lower parasitic capacitances
which reduce the on-chip delay and increase the maximum
toggle frequency of flip-flops, registers and counters. Buffering
all outputs, even on gates, results in lower output impedance
and thus reduces the effect of capacitive loading.
Propagation delay is affected by three parameters: capacitive
loading, supply voltage, and temperature.

Fig. 2·3
NORMALIZED PROPAGATION
DELAY VERSUS LOAD
CAPACITANCE FOR TTL AND CMOS

5.0

~L+J5OC

4.5

J

S

4.0

w

C 3.5
C

CD4001A
r-- VDD
=5V/

~ 3.0
:::;
- 140 I---+-t--

o

12

1_......."""",

~

VCl~15pF

tx ..........,

20

00

~ 160

VCl~ 1~0I PJI

\

(5 ~ 140

;5;;:

180 I-- +--+---+

TA

""I 160

~~

200r--,-,--,--,--,-·-,--,--,-,

I J
~ 25°C'1 1

180

;;:
oa:

-

14

VOlTAG~

-

Il.

16
V

TA -

AMBIENT TEMPERATURE -

125
°c

Fig.2·Gb
PROPAGATION DELAY
VERSUS AMBIENT TEMPERATURE
WITH VOD = 10 V

Fig.2·5b
NEGATIVE-GOING PROPAGATION
DELAY VERSUS POWER SUPPLY VOLTAGE

200
2 180

~ 8160

g~140

\

w 1l.120

\

~g
!;( 1l.100

S~
21

>~:3
Il.w
1

100

I~ 251c'I

TA

Cl

cll~50r-

/'

"'-.

00

-'
w
60
0

I

\ ~ VCl
'\ ~ ><..
..........

40
.... C 20

>«

~ lob pF r-

/'

\ 1\\

60

80

1

\\

80

'c"

~

2
0

~
Cl
«
Il.

15 pF

0

a: 20

r-- ::- t-

2.0 4.0 6.0 8.0 10

12

14

VOD _. POWER SUPPLY VOLTAGE -

40

Il.

16
TA -

V

2-6

AMBIENT TEMPERATURE -

°C

CMOS delays increase with temperature. They are very
sensitive to capacitive loading but can be reduced by increasing
the supply voltage to 10 or even 15 V.

Unfortunately these impressive noise margin specifications
disregard one important fact: the output impedance of CMOS
is 10 to 100 times higher than that of TTL. CMOS interconnections are therfore less "stiff" and much more susceptible to capacitively coupled noise. In terms of such current
injected crosstalk from high noise voltages through small
coupling capacitances, CMOS has about six times less noise
margin than TTL. It takes more than 20 mA to pull a TTL
output into the threshold region, but it takes only 3 mA to
pull a CMOS output into the threshold of a 5 V system.

To determine propagation delays, the effects of capacitive
loading, supply voltage, manufacturing tolerances and ambient
temperature must be considered. Start with the values of tpLI-i
(propagation delay, a LOW-to-HIGH output transition) and
tPHL (propagation delay, a HIGH-to-LOW output transition)
given in the individual data sheets. Delay values for VDD at 5,
10 and 15 V and output capacity of 15 and 50 pF are provided. Manufacturing tolerances account for the differences
between MIN, TYP and MAX. Starting with the nearest
applicable delay value, correct for effects of capacitive loading,
ambient temperature and supply voltage using the general
family characteristics of Section 3.

The nearly ideal transfer characteristic and the slow response
of CMOS circuits make them insensitive to low voltage,
magnetically coupled noise. The high output impedance,
however, results in a poor rejection of capacitively coupled
noise.
INTERFACE TO TTL
When CMOS is operated with a 5 V power supply, interface to
TTL is straightforward. The input impedance of CMOS is very
high, so that any form of TTL will drive CMOS without loss of
fan out in the LOW state. Unfortunately, most TTL has
insufficient HIGH state voltage (typically 3.5 V) to drive
CMOS reliably. A pull up resistor (1 kQ to 10 kQ) from the
output of the TTL device to the 5 V power supply will effectively pull the HIGH state level to 4.5 V or above. Alternately,
DTL Hex inverters may be used between the TTL and CMOS.
9LS Low Power Schottky and 93LOO Low Power TTL/MSI
utilize the unique output configuration shown in Figure 2-8 to
pull its output to VCC-VBC or approximately 4.3 V when
lightly loaded.

Fig. 2-7
TYPICAL TRANSFER
CHARACTERISTICS FOR TTL AND CMOS
6
TA = +25°C
SUPPLY VOLTAGE = 5 V

~

1\

o
o

34000
CMOS
7400
TTL

2

4

All 34000 logic elements will drive a single 9LS Low Power
Schottky input fan in directly. A 9LS Hex inverter such as the
9LS04 makes an excellent low cost TTL buffer with a fan out
of 20 into 9LS or 5 into standard TTL. Alternately, the 34049
and 34050 Hex buffers may be used to drive a fan out of 8
into 9LS or 2 into standard TTL.

6

INPUT VOLTAGE - V

NOISE IMMUNITY
When operating CMOS at voltages higher than 5 'If direct
interface to TTL cannot be used. The 34104 Quad Level
Translator converts TTL levels to high voltage CMOS up to
15 V. The 34049 and 34050 Hex Buffers will accept high
voltage CMOS levels up to 15 V and drive 2 standard
TTL loads.

One of the most advertised and also misunderstood CMOS
features is noise immunity. The input threshold of a CMOS
gate is approximately 50% of the supply voltage and the
voltage transfer curve is almost ideal. As a result, CMOS can
claim very good voltage noise immunity, typically 40% of the
supply voltage, i.e., 2 V in a 5 V system, 4 V in a 10 V system.
Compare this with the TTL transfer curve in Figure 2-7 and its
resultant 1 V noise immunity in a lightly loaded system and
only 0.4 V worst case.
Since CMOS output impedance, output voltage and input
threshold are symmetrical with respect to the supply voltage,
the LOW and HIGH level noise immunities are practically
equal. Therefore, a CMOS system can tolerate ground or VDD
drops and noise on these supply lines of more than 1 V, even
in a 5 V system. Moreover, the inherent CMOS delays act as a
noise filter; 10 ns spikes tend to disappear in a chain of CMOS
gates, but are amplified in a chain of TTL gates. Because of
these features, CMOS is very popular with designers of industrial control equipment that must operate in an electrically
and electromagnetically "polluted" environment.

KEY TO OUTPUT HIGH LEVEL
IS THE RESISTOR RETURNED
TO THE OUTPUT RATHER
THAN GROUND

Fig. 2·8
THE 93LOO AND 9LSOO TTL FAMILIES
WILL DRIVE CMOS DIRECTLY WITHOUT RESISTORS AS LONG AS
THERE ARE ONLY CMOS DEVICES
BEING DRIVEN FROM THE OUTPUT.
2-7

INPUT/OUTPUT CAPACITY

HANDLING PRECAUTIONS

CMOS devices exhibit input capacities in the 1.5 to 5 pF range
and output capacity in the 3 to 7 pF range.

All MOS devices are subject to damage by large electrostatic
charges. All 34000 devices employ the input protection
described in Figure 2.~ however, electrostatic damage can still
occur. The following handling precautions should be observed.

OUTPUT IMPEDANCE
All 34000 logic devices employ standardized output buffers.
Section 3 details output characteristics. It should be noted
that these impedances do not change with input pattern as do
conventional CMOS gates. Buffers, analog switches and analog
multiplexers employ special output configurations which are
detailed in individual data sheets.

1. All 34000 devices are shipped in conducting foam or
tubes. They should be removed for inspection or assembly
using proper precautions.
2. Ionized air blowers are recommended when automatic
incoming inspection is performed.
3. 34000 devices, after removal from their shipping material,
should be placed leads down on a grounded surface. Conventional cookie tins work well. Under no circumstances
should they be placed in polystyrene foam or plastic trays
used for shipment and handling of conventional ICs.
4. Individuals and tools should be grounded before coming in
contact with 34000 devices.

INPUT PROTECTION
The gate input to any MOS transistor appears like a small
«1 pF) very low leakage «10- 12 A) capacitor. Without
special precautions, these inputs could be electrostatically
charged to a high voltage, causing a destructive breakdown of
the dielectric and permanently damaging the device. There·
fore, all CMOS inputs are protected by a combination of series
resistor and shunt diodes. Various manufacturers have used
different approaches; some use a single diode, others use two
diodes, and some use a resistor with a parasitic substrate diode.

5. Do not insert or remove devices in sockets with power
applied. Ensure power supply transients, such as occur
during power turn-on or off; do not exceed maximum
ratings.
6. In the system, all unused inputs must be connected to
either a logic HIGH or logic LOW level such as VSS, VDD
or the output of a logic element.
7. After assembly on PC boards, ensure that static discharge
cannot occur during storage or maintenance. Boards may
be stored with their connectors surrounded with conductive foam. Board input/output pins may be protected with
large value resistors (10 Mn) to ground.
8. In extremely hostile environments, an additional series
input resistor (10 to 100 kn) provides even better protection at a slight speed penalty.

Each member of the 34000 family utilizes a series resistor,
nominally 200 n, and two diodes, one to VDD, and the other
to VSS (Figure 2-9). The resistor is a poly-silicon "true
resistor" without a parasitic substrate diode. This ensures that
the input impedance is always. at least 200 n under all biasing
conditions, even when VDD is short circuited to VSS (selective
power-down). A parasitic substrate diode would represent a
poorly defined shunt to VSS in this particular case.
The diodes exhibit typical forward voltage drops of 0.9 V at
1 mA and reverse breakdowns of 20 V for Dl and 26 V for
D2. For certain special applications such as oscillators, the
diodes actually conduct during normal operation. However,
currents must be limited to 10 mA.

A WORD TO THE TTL DESIGNER
Designing with CMOS is generally an easy transition and allows
the designer to discard many of the old design inhibitions for
new found freedoms. A few of these are:
Fan out-It is practically unlimited from a dc point of view
and is restricted only by delay and rise time considerations.
Power Supply Regulation-Anything between 3 V and 15 V
goes, as long as all communicating circuits are fed from the
same voltage.

2000
NOMINAL.

INPUT

O--~M,----0--6

Voo = Pin 14
VSS 0 Pin 7

13~ 12

2p- 9P10
1 11
12

,

34049

10

3---£>0--29---£>0--10
5---£>0--411 -{.>o-12
7---£>0--614 ---£>0--15

Voo ~ Pin 14
VSS ~ Pin 7

8

3
4
5

~:l--t>o---4 11~10

6

'=D-13~
9

2

Pin 14

34023
1211~

b

0

VSS ~ Pin 7

6~13~

34012
13

VOOoPin 14
VSS ~ Pin 7
NC : : : Pins 6, 8

Voo = Pin 1
VSS = Pin 8
NC 0, PIOS 13, 16

34050

--------

3-{>-' 9--{:>--10

34068

~P-'3

9 10
11
12

VOO~Pin

14

5-t>-4

11--{:>--12

7--{:>--6

14---1::;>-10

VOO

34081

5=0-412 =0-"

VSS ~ Pin 7

10

34001

VOO~Pin

VSS

3=f.>"=D>'==Do-

= Pin

Voo
VSS

14
7

5

2

8

12

10

-9 13

VOO~Pin

14

4

11

5

12

Pin 16
Pin 8

340098

11

15

VSS ~ Pin 7

10

34002

;~1'~~13

°
0

,"§"

34025

6

12

11

15

Voo ~ Pin 14

13

340097

"§"
12-

4

Pin 1

VSS ~ Pin 7
NC 0 Pins 1, 6, 8

-3

6

0

VSS ° Pin 8
NC ° Pins 13, 16

VOO 0 Pin 16
VSS ~ Pin 8

Voo = Pin 14
VSS ~ Pin 7
NC ~ Pins 6,8

34030

;:jD-3 :jD-10
34078

:~D-4~~:}D-"
Voo ~ Pin 14

=D-38=D-'o
5=D- 412 =D- '1
9

6

'13

:~[)o-4 ~~~I>--"

34071

V OD

VOO ~ Pin 14
VSS ~Pin 7

34077

;::::}1>-3 :~I>--'0

VSS ~ Pin 7
NC ~ Pins 1, 6, 8

21

AND

34070

Pin 14

VSS ~ Pin 7

3-8

VOO ° Pin 14
VSS ~Pin 7

TTL TO CMOS FUNCTION SELECTOR GUIDE

TTL

FUNCTION

CMOS

FUNCTIONAL DIFFERENCES BETWEEN CMOS AND TTL

PAGE
NO.

COMPLEX GATES (Cont'd)
7453

4-Wide, 2-lnput AND-ORINVERT Gate

34086

Different Pinout. The 34086 has two additional inputs which can be used as
either expander inputs or inhibit inputs by connecting them to any standard CMOS
output. The 7453 can be expanded only by connecting it to a special expander
circuit. The 7453 does not have an inhibit capability.

3-95

7474

Dual D Flip-Flop

34013

Different Pinout. The 7474 has active LOW SD and CD inputs; the 34013 has
active HIGH SD and CD inputs.

3-27

74109
9024

Dual JK Flip-Flop,
Edge-Triggered

34027

Different Pinout. The 7474 has active LOW SD and CD inputs; the 34013 has
the 34027 has active HIGH SD' CD and K inputs.

3-53

FLIP-FLOPS

74175

Ouad D Flip-Flop

340175

Same Pinout, Functionally Identical

3-148

74174

Hex D Flip-Flop

340174

Same Pinout, Functionally Identical

3-145

93510
9310
74160

Synchronous, BCD Up
Counter, Asynchronous
Master Reset

340160

Same Pinout. The 340160 and 93510 are fully edge-triggered. The 74160
and 9310 are "opposite state catching" on the Count Enable and Parallel Enable
inputs. The Terminal Count is fully decoded on the 340160,9310 and 93510
(TC = CET.00 .O,.0z.03) but is not fully decoded on the 74160
(TC = CET.00.03)' For the count sequence above 9, the 340160 is the same
as the 74160, different than the 9310 and 93510.

3-139

93516
9316
74161

Synchronous, Binary Up
Counter, Asynchronous
Master Reset

340161

Same Pinout. The 340161 is fully edge-triggered; the 74161 and 9316 are
"opposite state catching" on the Count Enable and Parallel Enable inputs. The
340161 is functionally identical to the 93516.

3-139

74162

Synchronous, BCD Up
Counter, Synchronous
Reset

340162

Same Pinout. The 340162 is fuIlY'edge-triggered and the Terminal Count is
fully decoded (TC = CET. 00.01."02.03); the 74162 is "opposite state
catching" on the Count Enable, Parallel Enable and Synchronous Reset inputs and
the Terminal Count is not fully decoded (TC = CET.00.03 ).

3-139

74163

Synchronous Binary Up
Counter, Synchronous
Reset

340163

Same Pinout. The 340163 is fully edge-triggered; the 74163 is "opposite state
catching" on the Count Enable, Parallel Enable and Synchronous Reset inputs.

3-139

74490

Dual BCD Up Counter

34518

Different Pinout. The 34518 has two clock inputs per counter and is fully
synchronous internally. The 74490 has a single clock input per counter, has a
"set to nine" input and is a ripple counter internally.

3-107

74393

Dual Binary Up Counter

34520

Different Pinout. The 34520 has two clock inputs per counter and is fully
synchronous internally. The 74393 has a single clock input per counter and is
internally organized as a ripple counter.

3-107

Synchronous, Binary/
Decade, Up/Down Counter

34029

No TTL Equivalent

74192

BCD, Up/Down Counter

340192

Same Pinout. Thei1f~ fully decoded on the 340192 (TC u = ~01. 02.03.
CP u); on the 74192 T u is not fully decoded (TC u = °0.°3. u).

3-150

74193

Binary, Up/Down Counter

340193

Same Pinout, Functionally Identical

3-150

74142

Divide-by-10 Counter
with Decoded Outputs

34017

Different Pinout. The 74142 is a BCD Counter/Latch/Decoder. The decoded
outputs are active LOW and can have decoding spikes. The 34017 is a 5-stage
Johnson decade counter with active HIGH, glitchless decoded outputs.

3-38

74393

7-Stage Binary Counter

34024

Different Pinout. The 74393, a dual 4-bit counter, can be connected as a
7-stage counter.

3-49

COUNTERS

3-9
.-~---

3-58

TTL TO CMOS FUNCTION SELECTOR GUlbE

TTL TO CMOS FUNCTION SELECTOR GUIDE
34040

10

7

34040

CP

6

5

4

13 14

15

1

2

12

3

34021

11
34021

10

V DD = Pin 16
11

9

7

6

5

3

2

4

13 12 14 15

1

CP

VSS = Pin 8

V DD = Pin 16
VSS = Pin 8

34020
1
OR
15

10

34555

2
3
OR OR
14 13

34020

CP

1/20F 34555

V DD = Pin 16
11

9

7

5

4

6

13 12

14 15

1

2

VSS = Pin 8

3

V DD = Pin 16
ORQROROA

340195
4

5

6

12

11 10

7
1

10

CP

3-0 K

VSS = Pin 8

9

2

34556

3

OR

OR OR

15

14

13

340195
1/20F 34556

MR

V DD = Pin 16
VSS = Pin 8

15 14 13 12 11

4

5

6'

V DD = Pin 16
VSS =Pin 8

7

OR OR OR OR

10

9

340194
3

°SR
So
10

S,

11

CP

4

5

6

10

13

12

34028

11

Po
340194

34028

MR

V DD = Pin 16
15

V DD = Pin 16

VSS = Pin 8

14 13 12

3

14

2

15

1

6

7

4

9

VSS = Pin 8

5

34035
9

10 11

34019

12

34019

1

S.

14

34035

CP

V DD = Pin 16
VSS = Pin 8

V DD = .Pin 16
VSS =Pin 8

15 14 13

34539
6

5

4

3

15

10

11

12

13

34015
14

So

15

34539

S,

V DD = Pin 16

V DD = Pin 16
5

4

3

10

14

13 12 11

2

VSS = Pin 8

VSS = Pin 8
15 10

1

2

3

4

5

6

7

9

34512

34014
7

6

5

4

13 14 15

1

11

11

So

12

S,

13

S2

34512

34014

10

CP

2

12

3

V DD = Pin 16
VSS = Pin 8

14

3-12

V DD = Pin 16
V SS =Pin8

TTL TO CMOS FUNCTION SELECTOR GUIDE

PAGE
NO.

FUNCTION

CMOS

74157
9322

Quad AND-OR Select Gate
(Quad 2-lnput Multiplexer)

34019

Different Pinout. The 34019 has two Select inputs which allow the choice of
four possible outputs: 0, A. B, A+B. The 74157 and 9322 have a single Select
input which allows the selection of either A or B inputs, and an active LOW
Enable input.

74153

Dual 4-lnput Multiplexer

34539

Same Pinout, Functionally Identical

3-110

74251

B-Input Multiplexer
3-State Outputs

34512

Different Pinout. The 34512 has an Enable input which forces all outputs LOW,
but it does not have a Z output. The 74251 does not have an Enable input, but has
both Z and Z ou~puts.

3-103

TTL

FUNCTIONAL DIFFERENCES BETWEEN CMOS AND TTL
MULTIPLEXERS

(74151
9312)

3-41

The 74151 and 9312 do not have 3-state outputs; they provide the Z output in
lieu of the Output Enable input. The 34512 can perform the same function as the
74151 and 9312.
ANALOG SWITCHES AND MULTIPLEXERS/DEMULTIPLEXERS
3-35,3-82

Quad Bilateral
Switch

34016/
34066

No TTL Equivalent. The 34016 and 34066 are "analog" switches.

(74151
9312)

8-Channel Analog
Multiplexer/Demultiplexer

34051

No TTL Equivalent. The 34051 can be used as a digital circuit to perform the
same function as the 74151 and 9312. The 34051 in an "analog" multiplexer/
demultiplexer.

3-76

(9309)

Dual 4-Channel Analog
Multiplexer/Demultiplexer

34052

No TTL Equivalent. The 34052 can be used as a digital circuit to perform the
same function as the 9309. The 34052 is an "analog" multiplexer/demultiplexer.

3-79

7475

4-Bit Latch

34042

Different Pinout. The 7475 has separate Enable inputs for bits, Oland 2,3. The
34042 has a Common Enable input for all four bits; but with the Exclusive-NOR
Enable inputs, it is possible to have either an active HIGH or an active LOW
Enable input.

3-70

9334
74259

8-Bit Addressable
Latch

34099

Same Pinout. The 9334 and 74259 have active LOW Clear inputs, the 34099 has
an active HIGH Clear input.

3-97

Dual 4-Bit Addressable
Latch

34723

No TTL Equivalent

75367

Quad TTL-to-CMOS
Converter, 3-State Outputs

34104

Different Pinout. The 34104 'has true and complement outputs and a common
active HIGH Output Enable input. The 75367 has only the inverted outputs
available and has individual active LOW Output Enable inputs.

74L85

4-Bit Magniiude
Comparator

340085

Same Pinout, Functionally Identical

Programmable Bit
Rate Generator

34702

No TTL Equivalent

74S189
7489

16 x 4-Bit RAM with
3-State Outputs

34725

Same Pinout, Functionally Identical. The 34725 is also similar to the 7489. The
3-130
7489 has open collector outputs which are HIGH impedance when Chip Select and
Write Enable are HIGH. Outputs are the complement of data inputs when
Write Enable is LOW irrespective of Chip Select. Outputs are the complement
of the selected word when Write Enable is HIGH and Chip Select is LOW.

74200

256 x l-Bit RAM with
3-State Outputs

34720

Different Pinout. The 74200 has three Chip Select inputs but does not have a
Q output. Write Enable is active LOW. The 34720 has only one Chip Select
input but has both Q and ~ outputs. Write Enable is active HIGH. The 37420
is transparent in the Write mode.

LATCHES

3-127

TRANSLATORS
3-100

ARITHMETIC OPERATORS, ADDERS, COMPARATORS

LSI -

3-133

SPECIAL FUNCTION
3-114

RAMs

3-13

3-124

TTL TO CMOS FUNCTION SELECTOR GUIDE
34099
14

13

1

2

3

34099

15

"

'3

'

,

13 14 15 12

A,

'0

5

6

7

9

10

11

Voo = Pin 16
VSS = Pin 8

12

VOO = Pin 14
VSS = Pin 8

340086

34051

,

5

10

7

2

15

11

9

1

14

4

'3

Y,

A(jYo Y, Y2 V3 Y4 Ys Va

11

"

4

12

3405'

Voo = Pin 16
VSS = Pin 8

VOO = Pin 16
VSS = Pin 8
Vee = Pin 7

34702
15

14

,

14

13 12

11

34723
3 '3

2

ECp
34702

'x
°xeD

Voo = Pin 16
VSS = Pin 8

34723
CL

'5

CD

,

5

4

6

,

9

12

®

'0

4

6

10

12

3

®
EO

'3

"

3

34725

34104

@

CD

'0

10 11

2

VOO = Pin 16
VSS = Pin 8

"

34725

5

7

Voo = Pin 16
VSS = Pin 8

9 ,11

34720

'5

16

12

Voo = Pin 16
VSS = Pin 8
Vee = Pin 7

'3

34042
4

7

13 14

,0

5~ 0

6"

34042

2

3

10

9

11

11

12

1

15

13

Voo = Pin 16
VSS = Pin 8

3·14

14

Voo = Pin 5
VSS = Pin 8
NC =Pin 4

CROSS REFERENCE GUIDE

Fairchild

RCA

RCA'

Series A

Series B

340098
340160
340161
340162
340163
340174
340175
340192
340193
340194
340195

National

MC14160
MC14161
MC14162
MC14163

MM80C98
MM74C160
MM74C161
MM74C162
MM74C163

MC14174
MC14175
CD40192B
CD40193B
CD40194B

Solid State

Motorola

Scientific

Salitron

Harris

Texas
Instruments

HD74C160
HD74C161
HD74C162
HD74C163

MM74C174
MM74C175
MM74C192
MM74C193

HD74C174

MM74C195

HD74C195

TP4360
TP4361
TP4362
TP4363

I

HD74C192
HD74C193

MC14194

PACKAGE CODE CROSS REFERENCE

Package

Fairchild

RCA

Motorola

National

Solid State

Scientific

Salitron

Harris

Texas
Instruments

Plastic DIP

P

E

P

N

E

E

1

Ceramic DIP

D

D or F

L

D

D

D

1

J

Ceramic Flatpak

F

K

-

F

F

-

9

-

Solid State
Scientific

Solitron

Harris

Texas
Instruments

2

TF

4

TP

5

TL

N

TEMPERATURE CODE CROSS REFERENCE
Temperature
Range
Military
(-55'C to +125'C)

Commercial

(-40' C to +85' C)

Commercial

(O'C to +70'C)

Fairchild

RCA

Motorola

National

M

D, K, F
Packages

A

70CXX

D,F
Packages

D
Package

46XX

Only

Only

E

E

56XX

Package

Package

Only

Only

-

-

54CXX

Only

E
C

Package

C

Only

-

-

-

74CXX

80CXX

*These devices are members of the new RCA Series B CMOS. Specifications include: Maximum operating voltage range of 3 to 18 volts;
recommended operating voltage range of 4 to 15 volts; symmetrical rise and fall times of 50 ns; output source and sink capability of 1.8 rnA
typical at V OD = 10 volts and TA = 25°C; and worst case noise immunity of 1.4 volts. All Fairchild 34000 Series CMOS devices are direct
pin-for-pin replacements for RCA's Series A and Series B CMOS.
'" "'This device is a functional equivalent only.
'" '" "'This device is pin-far-pin compatible if leads 4 and 8 are tied together.

3-15

CROSS REFERENCE GUIDE

Fairchild

RCA

RCA*

Series A

Series B

Motorola

National

Solid State
Scientific

Texas

Solitron

Harris

HD4001A
HD4002A
HD4011A
HD4012A
HD4013A

TP4001A
TP4002A
TP4011A
TP4012A
TP4013A

HD4019A

TP4014A
TP4015A
TP4016A
TP4017A
TP4019A

I nstru ments

-

34001
34002
34011
34012
34013

CD4001A
CD4002A
CD4011A
CD4012A
CD4013A

MC14001A
MC14002A
MC14011A
MC14012A
MC14013A

MM4601A
MM4602A
MM4611A
MM4612A
MM4613A

SCL4001A
SCL4002A
SCL4011A
SCL4012A
SCL4013A

CM4001A
CM4002A
CM4011A
CM4012A
CM4013A

34014
34015
34016
34017
34019

CD4014A
CD4015A
CD4016A
CD4017A
CD4019A

MC14014A
MC14015A
MC14016A
MC14017A

MM4614A
MM4615A
MM4616A
MM4617A
MM4619A

SCL4014A
SCL4015A
SCL4016A
SCL4017A
SCL4019A

CM4014A

34020
34021
34023
34024
34025

CD4020A
CD4021A
CD4023A
CD4024A
CD4025A

MC14020A
MC14021A
MC14023A
MC14024A
MC14025A

MM4620A
MM4621A
MM4623A
MM4624A
MM4625A

SCL4020A
SCL4021A
SCL4023A
SCL4024A
SCL4025A

CM4020A
CM4021A
CM4023A
CM4024A
CM4025A

34027
34028
34029
34030
34035

CD4027A
CD4028A
CD4029A
CD4030A
CD4035A

MC14027A
MC14028A

MM4627A
MM4628A
MM4629A
MM4630A
MM4635A

SCL4027A
SCL4028A
SCL4029A
SCL4030A
SCL4035A

34040
34042
34049
34050
34051

CD4040A
CD4042A
CD4049A
CD4050A
CD4051A

MC14040A
MC14042A
MC14049A
MC14050A

MM4640A
MM4642A
MM4649A
MM4650A
MM4651A

SCL4040A
SCL4042A
SCL4049A
SCL4050A

34052
34066
34068
34069
34070

CD4052A
CD4066A

MC14035A

HD4023A
HD4025A
HD4027A

HD4030A

CD4068B
CD4069B
CD4070B
CD4071B
CD4077B
CD4078B
CD4081 B
CD4085B

34086
34099
34104
34512
34518

CD4086B
CD4099B

34520
34539
34555
34556
34702

CD4520B

TP4020A
TP4021A
TP4023A
TP4024A
TP4025A
TP4027A
TP4028A
TP4029A
TP4030A
TP4035A
TP4040A
TP4042A
TP4049A
TP4050A
TP4051A

MM4652A
MM4666A

34071
34077
34078
34081
34085

34720
34723
34725
340085
340097

CM4016A
CM4017A
CM4019A

TP4052A

MM74C04

HD4811

CM4104
CD4518B

CD4555B
CD4556B

MC14512
MC14518

SCL4518

MC14520
MC14539
MC14555
MC14556

SCL4520

*'*CD4061A

**MC14585

MM74C85
MM80C97

3-16

TP4512A
TP4518A
TP4520A
TP4539A

34000
SERIES CMOS FAMILY CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS (Non-operating) above which useful life may be impaired. All voltages are referenced to VSS.
Supply Voltage VDD
Voltage on any Input
Current into any Input
Maximum Power Dissipation

-0.5 to 18 V
-0.5 to VDD +0.5 V
. . . . ±10mA
400mW
-65°C to 150°C
300°C

Storage Tempt:!rature

Lead Temperature (Soldering, 10 s)

RECOMMENDED OPERATING CONDITIONS
Fairchild CMOS will operate over a recommended VDD power supply range of 3 to 15 V, as referenced to VSS (usually ground). Parametri~
limits are guaranteed for VDD equal to 5, 10 and 15 V. Where low power dissipation is required, the lowest power supply voltage. consistent
with required speed, should be used. For larger noise immunity, higher power supply voltages should be specified. Because of its wide operating
range, power supply regulation and filtering are less critical than with other types of logic. The lower limit of supply regulation is 3 V ,or as
determined by required system speed and/or noise immunity or interface to other logic. The recommended upper limit is 15 V or as determined
by power dissipation constraints or interface to other logic.

Unused inputs must be connected to VDD, VSS or another input.
Care should be used in handling CMOS devices; large static charges may damage the device.
Operating temperature ranges are -40°C to +85°C for Commercial and _55°C to +125°C for Military.

PARAMETER

34000XC
MIN

Supply Voltage, VDD
Operating Free Air

Temperature Range

34000XM

TYP

3
-40

+25

MAX

MIN

TYP

15

3

+85

-55

+25

MAX

UNITS

15

V

+125

°c

x = Package

Type; F for Flatpak, 0 for Ceramic DIP, P for plastic DIP. See Section 6 for Ordering
Information.

DC CHARACTERISTICS FOR THE 34000 SERIES CMOS FAMILY - Parametric Limits listed below are guaranteed for the entire Fairchild
CMOS Family unless otherwise specified on the individual data sheets.

DC CHARACTERISTICS: VDD = 5 V, VSS = 0 V
SYMBOL

PARAMETER

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

LIMITS
MIN

TYP

MAX

UNITS

TEMP

V

All

Guaranteed Input HIGH Voltage

V

All

Guaranteed I nput LOW Voltage

3.5
1.5
4.99

VOH

Output HIGH Voltage

4.95

V

4.0

V
0.01

>VOL

liN

Output LOW Voltage

Input Current

I
I

XC
XM

Output HIGH Current

All

IOH = 0 mA, Inputs at 1.5 or 3.S V

MIN,2SoC

IOL ~ 0 mA,lnputs at 0 or S V per
the Logic Function or Truth Table

MAX

V

All

J.lA

25°C

0.01

mA

-1.0
-0.7

mA

1.0
Output LOW Current

the Logic 'Func'tian or Truth Table

V

-0.4
IOL

IOH - 0 mA, Inputs at 0 or 5 V per

MAX

0.5

-1.5
IOH

MIN,25°C

0.05
0.1

TEST CONDITIONS

MIN,25°C
MAX
MIN,25°C
MAX

IOL = 0 mA,lriputs at 1.5 or 3.5 V
Lead under test at 0 Or 5 V
All other Inputs simultaneously at 0 or 5 V
VOUT=
2.5 V
VOUT=
4.5V

MIN

0.8

mA

0.4

25°C
MAX

3·17

Inputs at 0 or 5 V per
the Logic Function or
Truth Table

VOUT=
0.4 V

34000 SERIES CMOS FAMILY CHARACTERISTICS
DC CHARACTERISTICS: VDD ~ 10 V, VSS ~ 0 V
SYMBOL

LIMITS

PARAMETER

VIH

Input HIGH Voltage

VIL

I nput LOW Voltage

MIN

TYP

MAX

UNITS

TEMP

V

All

Guaranteed Input HIGH Voltage

V

All

Guaranteed Input LOW Voltage

7.0
3.0
9.99

Output HIGH Voltage

VOH

V

9.95

0.01
Output LOW Voltage

0.05

I nput Current

I

XC

All

0.1

XM

MAX
MIN

2.6
Output LOW Current

IOL

2.0

the Logic Function or Truth Table
~

0 rnA, Inputs at 3 or 7 V

Lead under test at 0 or 10 V
All other Inputs Simultaneously at 0 or 10 V

MIN,25°C

mA

-0.8

IOL -Oar 10V per

IOL

25°C

fJ.A

0.01
-1.4

Output HIGH Current

IOH

MAX

V

IOH ~ 0 rnA, Inputs at 0 or 10 V per
the Logic Function or Truth Table
IOH ~ 0 rnA, Inputs at 3 or 7 V

All
MIN,25°C

V

1.0
liN

MAX

V

9.0

VOL

MIN,25°C

TEST CONDITIONS

25°C

mA

1.2

MAX

VOUT~

9.5 V

Inputs at 0 or 10 V per

VOUT~

0.5 V

the Logic Function or
Truth Table

DC CHARACTERISTICS: VDD ~ 15 V, VSS ~ 0 V
SYMBOL

LIMITS

PARAMETER

VIH

Input HIGH Voltage

VIL

I nput LOW Voltage

MIN

TYP

MAX

UNITS

TEMP

V

All

Guaranteed Input HIGH Voltage

V

All

Guaranteed Input LOW Voltage

10.5
4.5
14.99

Output HIGH Voltage

VOH

V

14.95
13.0

Output LOW Voltage

V

0.05
2.0

XC

I

liN

Input Current

IOH

Output HIGH Current

1.0

XM

1.0
-2.2

3.6

All

IOH - 0 mA, Inputs at 4.5 or 10.5 V
IOL - 0 mA, Inputs at 0 or 15 V per

MAX
All

fJ.A

25°C

the Logic Function or Truth Table
IOL

MIN,25°C
MAX
MIN, 25°C

mA

2.0

IOH ~ 0 mA, Inputs at 0 or 15 V per
the Logic Function or Truth Table

MIN,25°C

V

mA

-1.4

Output LOW Current

IOL

MAX

V
0.01

VOL

MIN,25°C

TEST CONDITIONS

MAX

~

0 mA, Inputs at 4.5 or 10.5 V

Lead under test at 0 or 15 V
All other Inputs Simultaneously at 0 or 15 V
VOUT~

14.5 V
VOUT~

0.5 V

Inputs at

a or 15 V per

the Logic Function or
Truth Table

TYPICAL 34000 SERIES CHARACTERISTICS

Fig. 3-1
POSITIVE·GOING
PROPAGATION DELAY
VERSUS SUPPLY VOLTAGE
200

7160

/cl

g;140
~ ~120

\ ...

E Z100
"'0
~~ 80
I'"
3:
.. 0

~g:

\
"y-

60

z

1~OP~II

VCl-50PF

-"

VC~ ,~ pF
0

20

a

2.0 4.0

Voo -

12

14

\

~ ~'20

\

~

POWER SUPPLY VOLTAGE ,- V

I

\1\

80

Cl

0

1

I

oh PF~t:-

/ ' .ClIO"O!",

...-Cl 15pF
.\ K
_'\ I~ ~ 1 1
I......... ...... --::;::::±:
I::t:::.
0

I I 60
40

'" 20
16

1 1

1\

g:,oo

~w

-

6.08.0 10

g~140
'~" ~

251c_

TA 10

180

~ ~160

3;

i'-..-< "'.......
t-..... .......... t-- r- -

40

0

o

Fig. 3-3
POSITIVE-GOING
PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

200

2~oC
"I 1

TAl 0

180

~

Fig. 3-2
NEGATIVE·GOING
PROPAGATION DELAY
VERSUS SUPPLY VOLTAGE

00

2.0 4.0 6.0 8.0 10

Voo -

12

"

POWER SUPPLY VOLTAGE -

3-18

16
V

CL - LOAD CAPACITANCE -

pF

34000 SERIES CMOS FAMILY CHARACTERISTICS

Fig. 3·4
NEGATIVE·GOING
PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

200

VD~

T1 c 1J C

~ 180

~

O

g5

140

~

2100 -VDD;5
",0
80

~~

60

g~

40

20
00

CL -

100

VDDlo 10

'""
0

I

>
>-

.....v
l--

~

v

IV

0

150

LOAD CAPACITANCE -

pF

200r--r-r-r-'--r-'~'--r~

100

/'

;~j550C

80

> 140

,.

z 100

"

~

>= 40

~

60

".'" --"
." -

':.o"

0

Ii:

i

i

1

i

I

I

I-- 1--

25

iii

ffi

_-1_-

-I = -'---±::""
J- -t-

~

'5

t

i

'"

f

VGS -

20

125
°C

GATE TO SOURCE

~ 60 ~_f-------j,-----,~--,VC;Ol TAGE - V

107

Hz

1

T
I-- --tI

--

CL =

CL::: 100

pF-~-t~Hl-

'J

-1--'111--

50 pF

- I---

~5 --

-55

--.. . -

ji::

II
tpLH

I

TCL=15pF

25

TA - AMBIENT TEMPERATURE -

Fig. 3·12
p·CHANNEL DRAIN CHARACTERISTICS
70

106

VOO:::15V

--

J
40

tpLH

25
TA - AMBIENT TEMPERATURE -

=+=

60

;t

'if!

I

I CL I

80

~

i

105

Fig. 3·9
PROPAGATION DELAY
VERSUS AMBIENT
TEMPERATURE @ VDD ~ 15 V

~_
"
o

I

p::t.

CL::: 50 pF

104

Z

-,- 'IT

--

Cl- 15

--

[

V~~5~
II

.- .-

10 0

1

If
Voo::; 10V

INPUT FREQUENCY -

I

1-- i

~

.
"I(-

k:

102 103

2

V

tPH~_

)(1 L

I

'"

.-

J

~

10-4

~

15

~-V~D;10~-

-55

DC

Fig. 3·11
n·CHANNEL DRAIN CHARACTERISTICS
o~~~~~r--r--'--.

10-2

~ 10-3

_tCL=50 pF

20

o

AMBIENT TEMPERATURE -

Z 10- 1

o

10

Cl=100pF

Z
0

o

1.0

o

! !

180

"g,20 ~-T---+-Hf+--+-

10

Fig. 3-8
PROPAGATION DELAY
VERSUS AMBIENT
TEMPERATURE @ VDD ~ 10 V

Fig. 3·7
PROPAGATION DELAY
VERSUS AMBIENT
TEMPERATURE @ VDD ~ 5.0 V

TA -

~.

INPUT VOLTAGE -

7160~4--+-~+-~-4-+-4-~

-rr 11
,1111111
VOO=15V

~

5.0

200

100

..ffi
~.

I~ V

I--I--

1000

~
U

~+125°C

VDD lo 5V

>::>

~

"''""

~

10

!:;

-~TV
50

15 1V

I

I
w

V

y

~DDlo1~

7

>

V

V

~ ~120

0

Fig. 3·6
GATE POWER DISSIPATION
VERSUS FREQUENCY

15

1 160

~~

Fig. 3·5
VOLTAGE TRANSFER
CHARACTERISTICS OVER
_55°C TO +125°C RANGE

125
DC

OUTPUT TRANSITION TIME
VERSUS LOAD CAPACITANCE

1'40r--r~--'--'--.-__--'---'

~

TA-,,25°C

~120-~

f--~--~--+--~--+-~~

Z

g100~-~~--.~.~--+-~~+---1

I
~ -20

>-

~-30~-~~~~~~--+-~

""::>

:J
CJ

~-40~-r--~-4---4--+-~

~

i

~-50

iii
z

~

:

.

I

I

5
5o

""

VGS :15V

E-60~-I--~I-·~~~~~~~

i

10

-70 o~-'-----c'----l--_.J.,-0-.L-_J'5
Vos -

DRAIN TO SOURCE VOLTAGE -

80

V

--

>-

"z<1

10

60

40
20 ~+--..I"""'*"""

15

Vos - DRAIN TO SOURCE VOLTAGE - V

CL -

LOAD CAPACITANCE -

pF

INPUT CIRCUITRY

Fig. 3-13
INPUT PROTECTION CIRCUIT

All inputs are protected by the network of Figure 3-13; a series
input resistor plus diodes D1 and D2 clamp input voltages

between VSS and VOD. Forward conduction of these diodes is
typically 0.9 V at 1 rnA. When VSS or VOD is not connected,

avalanche breakdown of the diodes limit input voltage; D1
typically breaks down at 20 V, D2 at 26 V. In normal logic

200 n

operation the diodes never conduct, but for certain special
applications such as oscillators, circuit operation may actually
depend on diode conduction. Operation in this mode is
permissible so long as input currents do not exceed lOrnA.

INPUTo--_N_O~M""I\N_A_L_+-_--..._ i~i~~~~ORS
D1

I nput capacitance is typically 5 pF across temperature for any
input.

Vss

3-19

DEFINITION OF SYMBOLS AND TERMS USED IN DATA SHEETS

CURRENTS - Positive current is defined as conventional current flow into a device. Negative current is defined as conventional current flow out of a device.
liN -

(Input Current) -

The current flowing into a device at specified input voltage and VD D '

IOH -

(Output HIGH Current) -

IOL -

(Output LOW Current) -

The drive current flowing out of the device at specified HIGH output voltage and VDD'

IDD -

(Quiescent Power Supply Current) -

The drive current flowing into the device at specified LOW output voltage and VDD'
The current flowing into the VDD lead at specified input and VDD conditions.

IOZH - (Output OFF Current HIGH) - The leakage current flowing into the output of a 3-state device in the "OFF" state at
a specified HIGH output voltage and VDD'
IOZL - (Output OFF Current LOW) HIGH output voltage and VDD'
IlL -

The leakage current flowing out of a 3-state device in the "OFF" state at a specified

(Input Current LOW) - The current flowing into a device at a specified LOW level input voltage and a specified VDD'

IIH - (Input Current HIGH) VDD'

The current flowing into a device at a specified HIGH level input voltage and a specified

IDDL - (Quiescent Power Supply Current LOW) - The current flowing into the VDD lead with a specified LOW level input
voltage on all inputs and specified V DD conditions.
IDDH - (Quiescent Power Supply Current HIGH) - The current flowing into the VDD lead with a specified HIGH level input voltage on all inputs and specified VDD conditions.
IZ - (OFF State Leakage Current) - The leakage current flowing into the output of a 3-state device in the "OFF" state at
a specified output voltage and VDD'

VOLTAGES VDD -

All voltages are referenced to V SS which is the most negative potential applied to the device.

(Drain Voltage) -

The most positive potential on the device.

VIH -

(Input HIGH Voltage) -

VIL -

(Input LOW Voltage) -

The range of input voltages that represents a logic HIGH level in the system.
The range of input voltages that represents a logic LOW level in the system.

VIH (min) -

(Minimum Input HIGH Voltage) -

The minimum allowed input HIGH level in a logic system.

VIL (max) -

(Maximum Input LOW Voltage) -

The maximum allowed input LOW level in a system.

VOH - (Output HIGH Voltage) - The range of voltages at an output terminal with specified output loading and supply
voltage. Device inputs are conditioned to establish a HIGH level at the output.
VOL - (Output LOW Voltage) - The range of voltages at an output terminal with specified output loading and supply voltage. Device inputs are conditioned to establish a LOW level at the output.
VSS - (Source Voltage) - For a device with a single negative power supply, the most negative power supply, used as the
reference level for other voltages. Typically ground.
VEE - (Source Voltage) - One of two (VSS and VEE) negative power supplies. For a device with dual negative power supplies, the most negative power supply used as a reference level for other voltages.

ANALOG TERMS
RON - (ON Resistance) output load and VDD'

The effective "ON" state resistance of an analog transmission gate, at specified input voltage,

RON - ("tJ. "ON Resistance) - The difference in effective "ON" resistance between any two transmission gates of an
analog device at specified input voltage, output load and VDD'

3-21

I

DEFINITION OF SYMBOLS AND TERMS USED IN DATA SHEETS
AC SWITCHING PARAMETERS
fMAX - (Toggle Frequency/Operating Frequency) - The maximum rate at which clock pulses may be applied to a sequential circuit with the output of the circuit changing between 30% of VDD and 70% of VDD. Above this frequency the device
may cease to function. See Figure 3-15.
tplH - (propagation Delay Time) - The time between the specified reference points, normally 50% points on the input
and output voltage waveforms, with the output changing from the defined LOW level to the defined HIGH level. See Figure 3-14.
tpHL - (Propagation Delay Time) - The time between the specified reference points, normally 50% points on the input
and output voltage waveforms, with the output changing from the defined HIGH level to the defined LOW level. See Figure 3-14.
tTLH - (Transition Time, LOW to HIGH) - The time between two specified reference points on a waveform, normally 10%
and 90% points, which is changing from LOW to HIGH. See Figure 3-14.
tTHL - (Transition Time, HIGH to LOW) - The time between two specified reference points on a waveform, normally 90%
to 10% points, which is changing from HIGH to LOW. See Figure 3-14.
tw -

(Pulse Width) -

The time between 50% amplitude points on the leading and trailing edges of pulse.

th - (Hold Time) - The interval immediately following the active transition of the timing pulse (usually the clock pulse) or
following the transition of the control input to its latching level, during which interval the data to be recognized must be
maintained at the input to ensure its continued recognition. A negative hold time indicates that the correct logic level may
be released prior to the active transition of the timing pulse and still be recognized.
ts - (Set-up Time) - The interval immediately preceding the active transition of the timing pulse (usually the clock pulse)
or preceding the transition of the control input to its latching level, during which interval the data to be recognized must be
maintained at the input to ensure its recognition. A negative set-up time indicates that the correct logic level may be initiated sometime after the active transition of the timing pulse and still be recognized.
tpHZ - (3-State Output Disable Time, HIGH to Z) - The time between the specified reference points, normally the 50%
point on the Output Enable input voltage waveform and a point representing a 0.1 VDD drop on the Output voltage waveform of a 3-state device, with the output changing from the defined HIGH level to a high impedance OFF state.
tpLZ - (3-State Output Disable Time, LOW to Z) - The time between the specified reference points, normally the 50%
point on the Output Enable input voltage waveform and a point representing a 0.1 VDD rise on the Output voltage waveform of a 3-state device, with the output changing from the defined LOW level to a high impedance OFF state.
tpZH - (3-State Output Enable Time, Z to HIGH) - The time between the specified reference points, normally the 50%
point on the Output Enable input voltage waveform and a point representing 0.5 VDD on the Output voltage waveform of
a 3-state device, with the output changing from a high impedance OFF state to the defined HIGH level.
tpZL - (3-State Output Enable Time, Z to LOW) - The time between the specified reference points, normally the 50%
point on the Output Enable input voltage waveform and a point representing 0.5 VDD on the Output voltage waveform of
a 3-state device, with the output changing from a high impedance OFF state to the defined LOW level.
trec - (Recovery Time) - The time between the end of an overriding asynchronous input. typically a Clear or Reset input,
and the earliest allowable beginning of a synchronous control input, typically a Clock input, normally measured at 50%
points on both input voltage waveforms.

'TLH---~

1-

~I

-

'THL

I~--...J\- - - - - - - - 9 0 %
INPUT

------

____-'IV -------1\

Fig. 3-14.

----- -

-

50%

-------10%

_Vss

Propagation Delay, Transition Time

Fig. 3-15.

3-22

Maximum Operating Frequency

FAIRCHILD CMOS • 34001 • 34002
34001 QUAD 2-INPUT NOR GATE. 34002 DUAL 4-INPUT NOR GATE
DESCRIPTION - These CMOS logic elements provide the positive input NOR function. The outputs are fully buffered for highest noise
immunity and pattern insensitivity of output impedance.

34002
LOGIC AND CONNECTION DIAGRAM
DIP (TOP VIEW)

34001
LOGIC AND CONNECTION DIAGRAM
DIP (TOP VIEW)

~~~NGlIolIol

~J

LdJ
r f=>r:Jr-8--H-ft-1

w

0.

~10-1~+H-+,H~~~~~~~~~
~

~10-2~~~~~~TH~~Tff-+-H~
(jj

~

1 0-3 t;.lg..f14-+1-++-+++l+
104

105

106

107

INPUT FREQUENCY - Hz

34002
PROPAGATION DELAY
VERSUS TEMPERATURE

34001
PROPAGATION DELAY
VERSUS TEMPERATURE
80

80
CL = 15 pF

CL = 15 pF

.

70

c

I 60

>

:5w

50 :-- r--

Z

40

~
(!l

30

~
a:

20

0

0

0

0.

-

ntPlt~

~
"lPLJ

.. 70
c
I 60

~

I-

o

"1 1

30

~

20

0.

10

o
a:

'\
trLHi tP~L VIDD 11 ~ V

o

o
~

~PH~ V6D =15 Vi
\ II..---'

~~

--

tPLH. IpHL VDD = 10 V

(!l

I-

10

-

50

Z 40

t~HL tDJ = 110 V l -

T f\1

tplH.

>

tpLH. tPHL V?D ~ 15,V

o

-60-40-20 0 20 406080100120140
TA - AMBIENT TEMPERATURE - °C

-60 -40-20 0 20 40 60 80100120140
TA - AM81ENT TEMPERATURE - °C

34001
PROPAGATION DELAY
VERSUS LOAD CAPACITANCE
100r--r--~~--.-~--'-~--,

.
7
5

90~~--r--+--+--+--+--4~

80

70 ~-t---~-+-Jlr--b...-
VERSUS FREQUENCY
E1000rT~'-~rT~Tr~-MT-r~~

I
w 100 H+t+-+-H-t+-+-++++
CJ

~ 10r+rrr+1~~~-r~~~~
~

~ 1.0Httt--t'lcH-tt--f-:;f:;PJjf'7'7f*fHttt-l

~

~ 10- 1 H-!+H,J.'IJ:!<:,o.1001--+-+~~-+~+--~-+---{

o
z
o

o
z

801--+--+~r--+--+-r--+---{

o

~

~

:

~

o

IE

__~-+---{

oa:

101--+--l-tPLH. tPHL VDD
OL-~~

o 20

0

0.

15 V

__~~__L-~~~.

20 ....."9:=--+"'C.'

__
00 ~

O~~--~_~

o w

CL - LOAD CAPACITANCE - pF

~

~~

__

~

__

~~

l001W1~100

CL - LOAD CAPACITANCE - pF

3-26

34013
DUAL D FLIP-FLOP

DESCRIPTION - The 34013 is a CMOS Dual 0 Flip-Flop which is edge-triggered and features independent Set Direct, Clear Direct, and Clock inputs. Data is accepted when the Clock is LOW and

LOGIC SYMBOL

transferred to the output on the positive-going edge of the Clock. The active HIGH asynchronous
Clear Direct (Col and Set Direct (Sol are independent and override the 0 or Clock inputs. The
outputs are buffered for best system performance.

34013

I

PIN NAMES

o
CP
So
CD

°
Q

Data Input
Clock Input

(L~H

Edge-Triggeredl

13

I
I

Asynchronous Set Direct Input (Active HIGHI
Asynchronous Clear Direct Input (Active HIGH)
True Output
Complement Output

CD

Q

o-f-

12

I
____ -.J
VOD = Pin 14
VSS

34013

TRUTH TABLE
OUTPUTS

INPUTS
So

CD

CP

H
L
H
L
L

L
H
H
L
L

X
X
X

...r
...r

L

= LOW Level

1-1

= HIGH Level

X

7

CONNECTION DIAGRAM
DIP (TOP VIEW)

34013

I

= Pin

0

°n+1

°n+1

X
X
X
L

H

L
H
H
H
L

H

L
H
L
H

14

13

"
10

= Positive-Going Transition
=

Don't Care

0n+1 = State After Clock Positive Transition

!
I

NOTE:

The

Flatpak version has the same

pinouts (Connection Diagram) as the

Dual In-Line Package.

3-27

I
I

~

FAIRCHILD CMOS • 34013
DC CHARACTERISTICS: V DD as shown, VSS = 0 V
LIMITS
SYMBOL

PARAMETER

VOO - 5 V
MIN

Quiescent

Power
100

Supply
Current

TYP

XC
XM

VOO=10V
MAX

MIN

TYP

VOO = 15 V

MAX

MIN

TYP

UNITS

TEMP

TEST CONDITIONS

MAX

10

20

4

140

280

56

1

2

OA

60

120

24

pA
~A

MIN,25°C
MAX

All inputs common

MIN,25°C

and at 0 V or VOO

MAX

NOTE: Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Characteristics.

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VOO as shown, VSS = 0 V, TA = 25°C
LIMITS
SYMBOL

PARAMETER

VOO = 5 V
MIN

VOO = 10V

TYP

MAX

MIN

MAX

150
150

35
35

66
66

tpLH
tpHL

Propagation Delay,
CP to Q, 0:

80
80

tpLH

95

171

40

tpHL

Propagation Delay,
So or Co to Q

60

110

30

tpLH
tpHL

Propagation Delay,
So or Co to 0:

100
100

170
170

45
45

tTLH
tTHL

Output Transition
Time

34
34

75
75

tpLH
tpHL

Propagation Delay,
CP to Q, 0:

95
95

lpLH

Propagation Delay,

tpHL

So or Co to 0

tpLH
tpHL

Propagation Delay,
SD or Co to 0:

tTLH
tTHL

Output Transition
Time

ts
th

Set-Up Time, Data to CP
Hold Time, Data to CP

80
0

VOO = 15 V

TYP

MIN

TYP

UNITS

25
25

ns
ns

72

30

ns

55

20

ns

80
80

30
30

ns
ns

20
20

40
40

10
10

170
170

38
38

72
72

29
29

ns
ns

130

220

45

90

32

ns

75

135

35

65

20

ns

115
115

190
190

50
50

90
90

35
35

ns
ns

60
60

135
135

30
30

70
70

20
20

30
-25

25
25

45
45

8
-6

ns
ns

lwCP(L)

Minimum Clock Pulse Width

100

55

55

30

18

ns

lwSD(H)

Minimum So Pulse Width

60

30

30

15

10

ns

lw CO(H)

Minimum CD Pulse Width

60

30

30

15

10

ns
ns

Recovery Time for So

-20

-9

-10

-4

-2

Recovery Time for CD

0

11

0

6

6

fMAX

Maximum CP Frequency
(Note 2)

5

8

8

16

CL = 50 pF
Input Transition
Times'; 20 ns

ns
ns

15
-12

tree So

CL = 15 pF
Input Transition
Times ~ 20 ns

ns
ns

40
0

tree Co

TEST CONDITIONS

MAX

CL = 15 pF
Input Transition
Times ~ 20 ns

ns
MHz

NOTES:
1. Propagation Delavs (tPLH and tPHL) and Output Transition Times (tTLH and tTHL) will change with Output Load CaPacitance (eLL
Set-up Times (ts), Hold Times (th), Recovery Times (tree), and Minimum Pulse Widths (tw) do not vary with load capacitance.
2. For fMAX input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.
3. Propagation Delays and Output Transition Times are graphically described in this section under 34000 Series CMOS Family Characteristics.
4. It is recommended that input rise and fall times to the Clock Input be less than 15 Ms.

3-28

FAIRCHILD CMOS • 34013
TYPICAL ELECTRICAL CHARACTERISTICS
POWER DISSIPATION
VERSUS FREQUENCY
El000~~~-rnT-r"rr'-rn,,~~-'

~

CLOCK FREQUENCY
VERSUS
POWER SUPPL Y VOLTAGE

25

I

u

~

~

TA = 250C
CL = 15 pF
1

~ 100

N

:t

«
:.:

~

>
()
=>

15

0
w

010-lH~1~~~~~·~~t-H+-H-t-H-i

----

~10-2

()
..J

15 1 0-3 ~'HJ..q-+t+t++tt\-

()

!

IX:

w

~10-4~~~~~-Ull-~--~--~
~
102
105
106
107

S
w

90

o
2:
o
f=
<3

70

~

50

f

40

I

30

o

80

60

10
IX:

CL

= 15 pF
VOo=~ ! -

t-±-I

~

0..

o

.,c

/

5

10

15

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

140~~---r--~--r--,---r--'--'

so

-

TA = 25°~

w 120

2: 100 1----+-+_-:,:;'"

o
f=

<3 80I----,joL--j--+---I--+-+~j--___l

I

~

~

hbo l10V

-~

I

10

a:

o

o

I

-60-40-20 0

~

2040 60 80100120140

TA -- AMBIENT TEMPERATURE -

60 I----+--j---'---I---+-+-=!-___l

0..

20

0

[

VDD - POWER SUPPLY VOLTAGE - V

I

o
o 10

U

Hz

PROPAGATION DELAY
VERSUS TEMPERATURE

WI

" 100

5

---~

/

10

0

/V

/

II:

III

CLOCK FREQUENCY -

e--- '---- --

...
:.:

f=

«

1---- - - --~

--~

Z
w

1.01'

-----

20

I

1 0 H-t-H--t-t-t+t++ttHrt7'ft1M.n-i>l1'71

---_.

0..

401----+--j-~~~~-~~~-j--___l

20
°0~-2~0--..J4~0--6·~0--~80---L--l~2-0-1-4~0--J160

U

CL - LOAD CAPACITANCE - pF

°C

WAVEFORMS

-'1
So

twSO{H)

1"-

~_______________________

CP

\~\\\\\\\
SET-UP TIMES, HOLD TIMES,
AND MINIMUM CLOCK PULSE WIDTH

-

RECOVERY TIME FOR SO, RECOVERY TIME FOR CD,
MINIMUM So PULSE WIDTH, AND MINIMUM CD PULSE WIDTH

NOTE: Set-up Times and Hold Times are shown as positive values but may be specified as negative values.

3-29

34014
8-81T SHIFT REGISTER

DESCRIPTION - The 34014 is a fully synchronous edge-triggered 8-Bit Shift Register with eight

LOGIC SYMBOL

synchronous Parallel Inputs (PO-P7), a synchronous Serial Data Input (OS), a synchronous Parallel

Enable Input (PE), a LOW-to-HIGH edge-triggered Clock Input (CP) and Buffered Parallel Outputs
from the last three stages (05-071.
Operation is synchronous and the device is edge-triggered on the LOW-to-HIGH transition of the Clock
Input (CPI. When the Parallel Enable Input (PE) is HIGH, data is loaded into the register from the
Parallel Inputs (PO-P7) on the LOW-to-HIGH transition of the Clock Input (CPI. When the Parallel
Enable Input (PE) is LOW, data is shifted into the first register position from the Serial Data Input
(OS) and all the data in the register is shifted one position to the right on the LOW-to-HIGH transition
of the Clock Input (CPI.

•
•
•
•

7

11

6

1314,151

DS

34014
10

2123

Voo

=

VSS

= Pin 8

Pin 16

CONNECTION DIAGRAM
DIP (TOP VIEW)

TYPICAL SHIFT FREQUENCY OF 14_7 MHz AT VDD = 10 V
PARALLEL OR SERIAL TO SERIAL DATA TRANSFER
AVAILABLE OUTPUTS FROM THE LAST THREE STAGES
FULLY SYNCHRONOUS

16
15
14

13
12
11

10

PIN NAMES
PE
PO-P7

Os
CP
05, 06, 07

Parallel Enable Input

NOTE:

Parallel Data Inputs

Serial Data Input
Clock Input (L-+H Edge-Triggered)
Buffered Parallel Outputs from the Last Three Stages

The F latpak version has the same
pinouts (Connection Diagram) as the
Dual In-Line Package

LOGIC DIAGRAM

@

°7

Voo = Pin 16

VSS

o

=

Pin 8

= Pin Number

3-30

FAIRCHILD CMOS • 34014
DC CHARACTERISTICS: V DD as shown, VSS = 0 V
LIMITS
SYMBOL

MIN
Quiescent
Power

IDD

Supply
Current

VDD = 10 V

VDD = 5 V

PARAMETER

TYP

XC
XM

MAX

MIN

TYP

VDD = 15 V

MAX

MIN

TYP

50

100

20

600

1200

240

5

10

2

300

600

120

UNITS

TEMP

TEST CONDITIONS

MAX
~A
~A

MIN,25°C

All inputs common

MAX

and at 0 V or V DD

MIN,25°C
MAX

NOTE: Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Characteristics.

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: V DD as shown, VSS = 0 V, TA = 25°C
LIMITS
SYM80L

V DD = 5 V

PARAMETER

MIN

TYP

tpHL
tpHL

Propagation Delay,
CP to any Q

tTLH
tTHL

Output Transition
Time

tpLH
tpHL

Propagation Delay,
CP to any Q

tTLH
tTHL

Output Transition
Time

twCP

CP Minimum Pulse Width

ts
th

Set -Up Time PE to CP
Hold Time PE to CP

ts
th

Set-Up Time DS to CP
Hold Time DS to CP

80

ts
th
f MAX

MAX

V DD = 10V
MIN

TYP

MAX

V DD =15V
MIN

TYP

UNITS

109
139

47
57

33
38

ns
ns

33
37

19
19

13
15

ns
ns

129
165

57
68

41
47

ns
ns

70

37
34

21
21

ns
ns

93

33

22

ns

118
117

44
43

29
27

ns
ns

77

28
27

17
16

ns
ns

Set-Up Time Pn to CP
Hold Time Pn to CP

108
107

37
36

23
22

ns
ns

Max. Input Clock Frequency
(Note 3)

5.8

14.7

77

TEST CONDITIONS

MAX
CL = 15pF
Input Transition
Times';; 20 ns

CL = 50pF
Input Transition
Times';; 20 ns

CL = 15pF
Input Transition
Times';; 20 ns

MHz

NOTES:

1. Propagation Delays and Output Transition Times are graphically described in this section under 34000 Series CMOS Family Characteristics.
2. Propagation Delays (tPLH and tPH L) and Output Transition Times (tTLH and tTH L) will change with Output Load Capacitance (eL).
3.
4.

Set-up Times (t s). Hold Times (th), and Minimum Pulse Widths (tw) do not vary with load capacitance.
For fMAX input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.
It is recommended that input rise and fall times to the Clock Input be less than 15 J..Ls.

SWITCHING WAVEFORMS

P"

D' _ _ _
MINIMUM CLOCK PULSE WIDTH
AND SET-UP AND HOLD TIMES, PE TO CP, Os TO CP, AND Pn TO CP
NOTE: Set-up and Hold Times are shown as positive values but may be specified as negative values.

3-31

34015
DUAL 4-81T STATIC SHIFT REGISTER

DESCRIPTION - The 34015 is a DU81 Edge·Triggered 4·8it Static Shift Register (Serial·to-Parallel
Converter). Each Shift Register has a Serial Data Input (D)" a Clock Input (CP), four fuJly buffered
parallel Outputs (GO-Q3) and an overriding asynchronous Master Resot Inpu.t (MRl.

-----------------,
LOGIC SYMBOL
34015

Information present on the serial Data Input (D) is Bhifted into the first register position, and all the
data in the register is shifted one position to the right on the LOW~to~HIGH transition of the Clock
Input lep).

A HIGH on the Master Reset Input (MR) clears the register and forces the Outputs (00-031 LOW,
independent of the Clock and Data Inputs (e? and DI.

..
..
•
..

TYPICAL SHIFT FREQUENCY OF 14 MHz AT VDD = 10 V
ASYNCHRONOUS MASTER RESET
SERIAL-TO-PARALLEL DATA TRANSfER
FUI.L Y BUFFERED OUTPUTS FROM EACH STAGE

15

PIN NAMES

DA,DB
MRA,MRS
CPA,CPB
°OA,01A,Q2A,Q3A
ODS, 0, B, Q2B, 038

5

4

3

10

13

12

11

2

Os

Serial Data Input
Master Reset Input (Active HIGH)

Clock I nput (L-~ H Edge·Triggeredi
Parane! Outputs
Parallel Outputs

14

--------------------- - " - - - - - - - "---------_.
LOGIC DIAGRAM

VDD
VSS

0=

Pin 16
Pin 8

CONNECTION DIAGRAM
DIP ITOP VIEWI

(i) "_"8_ _
@M.~O--O!>__---"+-_--+----_-O------:..J
VDD
VSS

NOTE:

The

Pin 16

F latpak version has the same

pinouts (Connection Diagram) as the
Dual 1t1,Line Package.

Pin 8

( ) = Pin Number

3-32

FAIRCHILD CMOS • 34015
DC CHARACTERISTICS: VDD as shown, VSS = 0 V
LIMITS
SYMBOL

V DD = 5 V

PARAMETER

MIN
Quiescent

Power
IDD

Supply
Current

TYP

XC
XM

V DD =15V

V DD =10V
MAX

MIN

TYP

MAX

MIN

TYP

10

20

4

100

200

40

1

2

0.4

30

60

12

TEMP

UNITS

TEST CONDITIONS

MAX
~A

~A

MIN,25°C

All inputs common

MAX

and at 0 V or V DD

MIN,25°C
MAX

NOTE: Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Characteristics.

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: V DD as shown, VSS = OV, TA = 25°C
LIMITS
SYMBOL

PARAMETER

V DD = 5 V
MIN

V DD =10V

TYP

MAX

TYP

MAX

tpLH
tpHL

140
140

250
250

75
75

135
135

45
45

ns
ns

tpHL

Propagation Delay, MR to Q

150

300

B5

150

60

ns

tTLH
tTHL

Output Transition
Time

50
50

100
100

25
25

60
60

20
20

tpLH
tpHL

Propagation Delay,
CP to Q

165
165

300
300

85
85

150
150

50
50

ns
ns

tpHL

Propagation Delay, MR to Q

180

325

90

160

60

ns

tTLH
tTHL

Output Transition
Time

85
85

150
150

45
45

85
85

30
30

ts
th

Set-Up Time, D to CP
Hold Time, D to CP

150
0

twCP(L)

Minimum Clock Pulse Width

twMR(H)

Minimum MR Pulse Width
MR Recovery Time

fMAX

Maximum CP Frequency
(Note 3)

70
-5

50
0

30
-20

120

60

70

75

40

45

300

160

4

8

MIN

TYP

UNITS

Propagation Delay,
CP to Q

tree

MIN

V DD = 15 V

TEST CONDITIONS

MAX

40
40

50
50

ns
ns

ns
ns

25
-10

ns
ns

35

25

ns

25

20

ns

120

60

45

7

14

ns

CL = 15 pF
I nput Transition
Times';; 20 ns

CL = 50 pF
Input Transition

Times.;; 20 ns

CL = 15 pF
Input Transition
Times.;; 20 ns

MHz

NOTES:
1. Propagation Delays and Output Transition Times are graphically described in this section under 34000 Series CMOS Family Characteristics.

2. Propagation Delays (tPLH and tPHLl and Output Transition Times (tTLH and tTHLl will change with Output Load Capacitance (el)'
Set-up Times (t s ), Hold Times (th), Recovery Times (tree), and Minimum Pulse Widths (twl do not vary with toad capacitance.
3. For fMAX, input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.
4. It is recommended that input rise and fait times to the Clock Input be tess than 15 j.ls.

3-33

I

FAIRCHILD CMOS • 34015
TYPICAL ELECTRICAL CHARACTERISTICS

POWER DISSIPATION
VERSUS FREQUENCY
1000
TA; 25°
100
10

I

VDD;W~r-

!;(I

w 1.0

iiiel
(1)0(

is

TII

I

>

V?81; 15V '\

~~
11.

11

~~

~~

S

V~~

Z

~¢ ~~~ -"- VDD; 5
~~
~ [/-:/ I~Dp 1111~ ~ I I ~ II
10- 3

ffiii!

II

11

III

CL - 15 pF
--Cl;50pF

~

80

ii!
o

60

~

20

11.

o

I

--

I--

,--

I
20 40 60 80 100120140

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

300r---,---.----r---r--~--~

~

300

TA; 25°C

I

5

250

2501--1--'.--1--+--+--+___--1

w

VDD = 5 V
f-"""

C

Z 200

200r--~~~-~-~--+-_4

o

i=

ii!

ii!
1 00 r---+----+------""' and Minimum Pulse Widths (tw>' do not vary with load capacitance.
3. For fMAX, input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.
4. It is recommended that input rise and fall times to either Clock Input (CPO or Cl5 1 ) be less than 15 p.s.

3-39

FAIRCHILD CMOS • 34017
SWITCHING WAVEFORMS

CPo

CPl

{~

.'}
\

\

/

-/

50%

HOLD TIMES, CPO TO CPl AND CPl TO CPO
Hold Times are shown as positive values, but may be specified as negative values.

CPo

MR

MINIMUM PULSE WIDTHS FOR
CP AND MR AND RECOVERY TIME FOR MR
CONDITIONS: CPl ~ LOW while CPO is triggered on a LOW-to-HIGH
transition. twCP and tree also apply when CPO ~ HIGH and CPl is
triggered on a HIGH-to-LOW transition.

3-40

34019
QUAD 2-INPUT MULTIPLEXER
OI:SCRIPTION - The 34019 provides four multiplexing circuits with common selection inputs; each
circuit contains two inputs and one output. It may be used to select four bits of information from one

of two
SA and
and SB
cannot

sources. The A inputs are selected when SA is HIGH, the B inputs when Sa IS HIGH. When
SB are HIGH, output IZ n ) is the logical OR of the An and Bn inputs IZ n ~ An + Bnl. When SA
are LOW, output IZ n ) is LOW independent of the multiplexer inputs IAn and Bnl. The 34019
be used to multiplex analog signals. The outputs utilize standard buffers for best performance.

1---------------I
LOGIC SYMBOL

I
I
6

PIN NAMES
SA,SB
AO - A3, 80 - B3

Select Inputs IActive HIGHi

Zo - Z3

Multiplexer Outputs

7

4

5

Multiplexer Inputs

2

3

15

1

34019

14

SB

11

10

12

13

TRUTH TABLE

VOD =-" Pin 16
VSS

=

Pin 8

'---------------CONNECTION DIAGRAM
DIP ITOP VIEW)

H

L
X

HJGH Level
=

LOW L.eve!
Don't Care

--------------------------,

lOGIC DIAGRAM

16

'1
15

0@(1)

14

13
12
11

10

VDD

0:":.

Pin 16

VSS

_--0

Pin 8

~

NOTEF latpak verSion has the same
Tne
pinouts (ConnectIon Diagram) as the
Dual In Lme Package

() -:: Pin Number

3-41

FAIRCHILD CMOS • 34019
DC CHARACTERISTICS: V DD as shown, VSS = 0 V
LIMITS
SYMBOL

V DD = 5 V

PARAMETER

TYP

MIN
Quiescent

Power
IDD

Supply
Current

XC
XM

VDD- 1O V
MAX

MIN

VDD - 15 V

MAX

TYP

MIN

TYP

30

60

12

600

1200

24

5

10

2

100

200

40

UNITS

TEST CONDITIONS

TEMP

MAX
~A
~A

MIN,25°C
MAX
MIN,25°C

All inputs common
and at 0 V or V DD

MAX

NOTE: Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Characteristics.

AC CHARACTERISTICS: VDD as shown, VSS = 0 V, TA = 25°C
LIMITS
SYMBOL

V DD = 5 V

PARAMETER

MIN

V DD =10V

TYP

MAX

MIN

VDD = 15 V

TYP

MAX

MIN

TYP

UNITS

TEST CONDITIONS

MAX

tpLH

Propagation Delay,

50

100

20

45

16

ns

tpHL

SA,SB' An or Bn to Zn

50

110

25

55

20

ns

CL = 15 pF
Input Transition Times';; 20 ns

tTLH

Output Transition

40

75

20

40

15

25

ns

tTHL

Time

45

75

22

40

15

25

ns

tpLH

Propagation Delay,

75

150

35

70

24

ns

tpHL

SA,SB' An or Bn to Zn

85

160

37

75

29

ns

CL = 50 pF
Input Transition Times.;; 20 ns

tTLH

Output Transition

80

135

42

70

32

45

ns

tTHL

Time

90

135

40

70

30

45

ns

NOTE:

1.

Propagation Delays and Output Transition Times are graphically described in this section under'34000 Series CMOS Family Characteristics.

TYPICAL ELECTRICAL CHARACTERISTICS

PROPAGATION DELAY
VERSUS TEMPERATURE

POWER DISSIPATION
VERSUS FREQUENCY

z

o

~

OJ

it
o
if

INPUT FREQUENCY -

Hz

TA - AMBIENT TEMPERATURE -

3-42

°C

CL - LOAD CAPACITANCE - pF

34020
14-STAGE BINARY COUNTER

DESCRIPTION - The 34020 is a 14-5tage Binary Ripple Counter with a Clock Input (CP). an
overriding asynchronous Master Reset Input (MR) and twelve fully buffered Outputs (00. 03-0131.
The counter advances on the HIGH-to-LOW transition of the Clock Input (CPI. A HIGH on the Master
Reset Input (MR) clears all counter stages and forces all Outputs (00. °3-°13) LOW. independent
of the Clock Input (CP).

LOGIC SYMBOL

VOD = Pin 16
VSS

Pin 8

CONNECTION DIAGRAM
DIP (TOP VIEW)

25 MHz TYPICAL COUNT FREQUENCY AT VDD = 10 V
COMMON ASYNCHRONOUS MASTER RESET
FULLY BUFFERED OUTPUTS FROM THE FIRST STAGE
AND THE LAST ELEVEN STAGES

•
•
•

=:

16
15
14
13
12

11
10

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual In-Line Package.

PIN NAMES

CP

Clock Input (H-> L Triggered)
Master Reset Input (Active HIGH)
Parallel Outputs

MR
°0.°3-°13
LOGIC DIAGRAM

VOD = Pin 16
VSS = Pin 8

() =Pin Number

~------~~--------~~----------*-----------~----------~-----------4----------~
3-43

FAIRCHILD CMOS • 34020

-------------------------------------------DC CHARACTERISTICS: V DD as shown, VSS = 0 V
---------

--

~--~-~-------l=

SYMBOL

PARAMETER

LIMITS
VDD = 5 V

---

M IN

;-.Power
",,;;.,"' f XC
Supply

Current

-,
.-

XM

_

--t-

VDD = 15 V

VDD = 10V

TYP! MAX

MIN

TYP
_._-_.-

50

MAX

MIN

TYP

20

1400
700
..
,
15
25
c---- f - - - - - - - -

280

'-____ ~

TEMP

TE ST CONDITIONS

r-100

r--~

UNITS

MAX

_-

_____~!i,Q2

5

_

300

~A
~A

'---

MIN,25°C All i nputs common
MAX __ and at OVor V DD
MIN,25°C
MAX

NOTE; Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Characteristics,

AC CHARACTERISTICS AND SET -UP REQUIREMENTS: VDD as shown, VSS

3-44

=0

V, TA = 25°C

FAIRCHILD CMOS • 34020
TYPICAL ELECTRICAL CHARACTERISTICS
CLOCK FREQUENCY
VERSUS
POWER SUPPLY VOLTAGE

POWER DISSIPATION
VERSUS CLOCK FREQUENCY

:=

35

E 1000

T~I;12$od
I
"I
~ 100

~
~

10

iii...

1.0

~

10- 1

VDD = 16V '::::
VDD =10V

~~

?
~'"

~p

~~ ~~

j:

~

I/)
I/)

10-2

C 10-3

~

W

V

~

102

II:

:= 10-4

,..~

IIII I
P,

~~
104

30

I

26

TA - 25°C
CL = 15 pF

::!

'"

/

>
C)

"'~

Z

w

20

:::I

aw

15

VD~ =I~j~

.....:
C)

10

I III

....0C)

5

105

CLOCK FREQUENCY -

106

o

107

Hz

/'

-

/

/

II:

CL= 15pF-CL=50 pF - - 103

:z:

N

/
o

/
5

10

15

VDD - POWER SUPPLY VOLTAGE - V

PROPAGATION DELAY
VERSUS TEMPERATURE

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

II!
I

;
w
C
Z

o

~

o

...II:
I

8

e

If;

o
CL - LOAD CAPACITANCE - pF

TA - AMBIENT TEMPERATURE - °C

SWITCHING WAVEFORMS

PROPAGATION DELAY MASTER
RESET TO OUTPUT. MINIMUM MASTER RESET
PULSE WIDTH AND RECOVERY TIME FOR MASTER RESET

PROPAGATION DELAY CLOCK TO
OUTPUT 00. OUTPUT TRANSITION
TIMES AND MINIMUM CLOCK PULSE WIDTH

3-45

34021
8-81T SHIFT REGISTER
DESCRIPTION - The 34021 is an edge-triggered S-Sit Shift Register (Parallel-to-Serial Converted
with a synchronous Serial Data Input (OS), a Clock Input (CP), an asynchronous active HIGH Parallel
Load Input (PL), eight asynchronous Parallel Data Inputs (PO-P7) and Buffered Parallel Outputs from
the last three stages (05-07).
Information on the Parallel Data Inputs (PO-P7) is asynchronously loaded into the register while the
Parallel Load Input (PL) is HIGH, independent of the Clock (CP) and Serial Data (OS) inputs. Data
present in the register is stored on the H IGH-to-LOW transition of the Parallel Load I nput.(PL).
When the Parallel Load'input is LOW, data on the Serial Data Input (OS) is shifted into the first
register position and all the data in the register is shifted one position to the right on the LOW-toHIGH transition of the Clock Input (CP).

LOGIC SYMBOL

7

6

5

4

13 14 15

1

2

3

11

34021

10

CP

12

Voo = Pin 16
VSS = Pin 8

•
•
•
•

CONNECTION DIAGRAM
DIP (TOP VIEW)

TYPICAL SHIFT FREQUENCY OF 18.1 MHz AT VDD = 10 V
PARALLEL·TO·SERIAL DATA TRANSFER
BUFFERED OUTPUTS AVAILABLE LAST THREE STAGES
CLOCK INPUT IS L .... HEDGE-TRIGGERED

,.
15
14

13
12

11

10

PIN NAMES
PL
PO-P7

Os
CP
°5-°7

Parallel Load Input
Parallel Data Inputs
Serial Data Input
Clock Input (L .... H Edge·Triggered)
Suffered Parallel Outputs from the Last Three Stages

NOTE:

The F latpak version has the same
pinouts"(Connection Diagram) as the
Dual In-Line Package.

LOGIC DIAGRAM

°7

Voo = Pin 16
VSS = Pin 8
= Pin Number

o

3-46

@

FAIRCHILD CMOS • 34021
DC CHARACTERISTICS: VDD as shown, VSS = 0 V

SYMBOL

MIN

IDD

Quiescent
Power

XC

Supply
Current

XM

LIMITS
V DD = 10V

VDD = 5 V

PARAMETER

TYP

MIN

MAX

TYP

50
600
5
300

VDD = 15 V

MAX

MIN

TYP

UNITS

TEMP

TEST CONDITIONS

MAX

100
1200

20
240

pA

MIN,25°C
MAX

10
600

2
120

~A

MIN,25°C
MAX

All inputs common
and at 0 V or V DD

NOTE: Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Characteristics.

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VDD as shown, VSS

=0 V, TA =25°C

LIMITS
SYMBOL

PARAMETER

VDD = 10V

VDD = 5 V
MIN

TYP

MAX

MIN

TYP

MAX

VDD = 15 V
MIN

TYP

UNITS

tpLH
tpHL

Propagation Delay,
CP to Q n

119
161

51
64

43

tpLH
tpHL

Propagation Delay,
PL to Q n

172
150

70
96

66

ns
ns

tTLH
tTHL

Output Transition
Time

28
32

15
14

10
9

ns
ns

tpLH
tpHL

Propagation Delay,
CP to Q n

134
184

59
74

40
49

ns
ns

tpLH
tpHL

Propagation Delay,
PL to Q n

188
274

78
105

54
72

ns
ns

tTLH
tTHL

Output Transition
Time

58
69

31
27

22
22

ns
ns

twC P

CP Minimum Pulse Width

61

21

14

ns

twPL

PL Minimum Pulse Width

67

24

16

ns

tree

PL Recovery Time

71

28

21

ns

ts
th

Set-Up Time DS to CP
Hold Time DS to CP

51
49

16
15

12
11

ns
ns

ts
th

Set-Up Time Pn to PL
Hold Time, Pn to PL

78
72

28
26

18
16

ns
ns

fMAX

Shift Frequency (Note 3)

7.8

18.1

34
4B

TEST CONDITIONS

MAX
ns
ns
CL = 15 pF
Input Transition
Times';; 20 ns

CL = 50 pF
Input Transition
Times';; 20 ns

CL = 15 pF
Input Transition
Times .. 20 ns

MHz

NOTES.
1. Propagation Delays and Output Transition Times are graphically described in this section under 34000 Series CMOS Family Characteristics.
2. Propagation Delays (tPLH and tpHL) and Output Transition Times (tTLH and tTHL) will chang"e with Output Load Capacitance (eL)'
Set-up Times (ts), Hold Times (th), Recovery Times (tree), and Minimum Pulse Widths (t w ), do not vary with load capacitance.
3. For fMAX input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.
4. It is recommended that input rise and fall times to the Clock Input be less than 15 J..I,s.

SWITCHING WAVEFORMS

DS

MINIMUM CLOCK PULSE WIDTH
AND SET-UP AND HOLD TIMES, Os TO CP

MINIMUM PL PULSE WIDTH, RECOVERY
TIME FOR PL, AND SET-UP AND HOLD TIMES, Pn TO PL

NOTE: Set-up and Hold Times are shown as positive values but may be specified as negative values.

3-47

FAIRCHILD CMOS. 34023
TRIPLE 3·INPUT NAND GATE

DESCRIPTION - This CMOS logic element provides a 3·input positive NAND function. The outputs are fully buffered for highest noise·
immunity and pettern insensitivity of output impedance.
LOGIC AND CONNECTION DIAGRAM
DIP (TOP VIEW)

NOTE:
The Flatpak version has the same pinouts
(Connection Diagram) as the Dual

In~Line

Package.

OC CHARACTERISTICS: VOO as ahown, VSS = 0 V
LIMITS
SYMBOL

TYP

MIN
Quiescent
Power
Supply
Current

IDD

VD D = 10V

VDD = 5 V

PARAMETER

MAX

MIN

TYP

MAX

0.5
15.0
0.05
3.0

XC
XM

VD D = 15 V
MIN

5.0
30.0
0.1
6.0

TEMP

UNITS

TEST CONDITIONS

MAX

TYP

1.0
6.0
0.02
1.2

MIN,25°C
MAX
MIN,25°C
MAX

~A
~A

All inputs common
and at 0 V or VOD

NOTE: Additional DC Characteristics are listed in this saction under 34000 Series CMOS Family Characteristics.

AC CHARACTERISTICS: VDD as shown, VSS = 0 V, TA = 25°C
LIMITS
V DD = 10V

VDD = 5 V

PARAMETER

SYMBOL

MIN

TYP

MAX

35
35

MIN

VDO=15V

TYP

MAX

75
75

20
20

40
40

15
9

MIN

TYP

tpLH
tpHL

Propagation Delay

tTLH
tTHL

Output Transition
Time

19
19

75
75

9
7

40
40

6
5

tpLH
tpHL

Propagation Delay

45
51

110
110

25
25

60
60

19

tTLH
tTHL

Output Transition
Time

45
45

135
135

18
18

70
70

17
12

..

NOTE: Propagation delays and output tranSition times are graphically deSCribed

UNITS

ns
ns
ns
ns

25
25

ns
ns

12

In

TEST CONDITIONS

MAX

ns
ns

45
45

CL =15pF
Input Transition Times .. 20 ns

CL = 50 pF
Input Transition Times .. 20 ns

this section under 34000 Series CMOS Family Characteristics.

TYPICAL ELECTRICAL CHARACTERISTICS

~ '000

POWER DISSIPATION
VERSUS FREQUENCY

II U~J =1~~lv

I
TA=26°C
w '00

1,0
~

~

1,0
10-

,

~

!: 10-2
III
!!l
Q

a:

~
i

10-3

10-4
102

VOD-&V

I

I

!i

...

~f

/.

CL=1SpF_

c~ i r~ prl~'
'07

TA=25'C

Q,oo~~-+--r-~-+--r-~-i
~
~ BOI--t--t--t-"<:-t--:;..t"'-t--::I.....--I

Z

o

J>:: ...

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE
!140r-~~--r-~~--r-'--'

~'20~.~-+--r-~-+--r-~-i

Q

...

103
104
10&
10&
INPUT FREQUENCY - Hz

PROPAGATION DELAY
VERSUS TEMPERATURE

~

I ~~~~,I.j~
VDD-51(~

"
~

!

f

Q

f

I

1 40

i

i20~±:~~~-+~~~
.l
i 0o~~~~~~~~~~~

.l

i

TA - AMBIENT TEMPERATURE -

3-48

oc

CL - LOAD CAPACITANCE - pF

34024
7-STAGE BI NARY COUNTER

DESCRIPTION - The 34024 is a 7-Stage Binary Ripple Counter with a Clock Input (CP), an
overriding asynchronous Master Reset Input (MR) and seven fully Buffere~arallel Outputs (QO-Q6).
The counter advences on the HIGH-to-LOW transition of the Clock Input (CP). A HIGH on the Master
Reset Input (MR) clears all counter stages and forces all Outputs (QO-Os) LOW, independent of the
Clock Input (CP).

LOGIC SYMBOL

CP

34024

12

VOO

~

11

9

B

5

4

3

Pin 14

VSS = Pin 7
NC = Pins 8,10 and 13

•
•
•
•

CONNECTION DIAGRAM
DIP (TOP VIEW)

TYPICAL COUNT FREQUENCY OF 30 MHz AT VDD = 10 V
CLOCK TRIGGERED ON THE HIGH-TO-LOW TRANSITION
ASYNCHRONOUS ACTIVE HIGH MASTER RESET
OUTPUTS AVAILABLE FROM ALL SEVEN STAGES

14

13

PIN NAMES

CP

Clock Input (H->L Triggered)

MR
00-Q6

Buffered Parallel Outputs

NOTE:
The F latpak version has the same
pinouts (Connection Diagram) as the

Master Reset Input

Dual I n-Line Package.

_0

cp--OI:>--I

®

MR~-[)o---~------~-----~~-----~--------+------~------~

Voo

= Pin

VSS

= Pin

o

NC

14

7
= Pin Number
= Pins 8,10 and 13

3-49

fAIRCHilD CMOS • 34024
DC CHARACTERISTICS: VDD as shown, VSS = 0 V
LIMITS
SYMBOL

MIN
Quiescent

Power

100

Supply

TYP

XC
XM

Current

V DD = 15 V

VDD = 10V

VDD = 5 V

PARAMETER

MAX

MIN

TYP

MAX

MIN

TYP

50

100

20

700

1400

280

5

10

2

300

600

120

UNITS

TEMP

TEST CONDITIONS

MAX
~A

MIN,25°C

All inputs common

MAX

and at 0 Vor V DD

MIN,25°C

~A

MAX

NOTE: Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Characteristics.

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: V DD as shown, VSS = 0 V, TA = 25°C
LIMITS
SYMBOL

V DD = 5 V

PARAMETER

MIN

TYP

V DD =10V
MAX

MIN

VDD = 15 V

TYP

MAX

MIN

TYP

UNITS

TEST CONDITIONS

MAX

82

165

37

75

23

ns

75

150

35

70

20

ns

CL = 15 pF

105

210

42

85

30

ns

Input Transition

25
25

75
75

13
13

40
40

10
10

Propagation Delay,
CP to

100
97

200
195

45
40

90
80

30
25

ns
ns

tpHL

Propagation Delay, MR to On

130

260

50

100

35

ns

tTLH
tTHL

Output Transition
Time

60
60

130
130

30
30

70
70

25
25

twCP

CP Minimum Pulse Width

90

45

35

17

13

ns

tw MR

MR Minimum Pulse Width

80

40

30

15

12

ns

tree

MR Recovery Ti me

60

30

25

12

9

fMAX

Input Count Frequency
(Note 3)

6

12

15

30

tpLH
tpHL

Propagation Delay,
CP to

tpHL

Propagation Delay, MR to On

tTLH
tTHL

Output Transition
Time

tpLH
tpHL

00

00

-

25
25

45
45

ns
ns

ns
ns

ns

Times,,;; 20 ns

CL = 50 pF
Input Transition
Times,,;; 20 ns

CL = 15 pF
Input Transition
Times.;;;; 20 ns

MHz

NOTES:
1. Propagation Delays and Output Transition Times are graphically described in this section under 34000 Series CMOS Family Characteristics.
2. Propagation Delays (tPLH and tPHL) and Output Transition Times (tTLH and tTHL) wiil change with Output Load Capacitance (eLL
Recovery Times (tree) and Minimum Pulse Widths (tw) do not vary with load capacitance.
3. For fMAX, input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.
4. It is recommended that input rise and fall times to the Clock Input be less than 15 jJS.

3-50

FAIRCHILD CMOS • 34024
TYPICAL ELECTRICAL CHARACTERISTICS
CLOCK FREQUENCY
VERSUS
POWER SUPPLY VOLTAGE

POWER DISSIPATION
VERSUS FREQUENCY
35
N

x

TA
CL

30

=25°C
=15 pF

::;
I

>
CJ
Z

w

25

/

20

w

a:

15

LL

:.:
CJ

10

L

0

...J

5

CJ

/

/
V

;;;)

0

L

I'

o

o

5
10
15
VDD - POWER SUPPLY VOLTAGE - V

PROPAGATION DELAY

PROPAGATION DELAY
VERSUS TEMPERATURE

~ 180.-_V.,E_R_S,U_S_L,O_A_D,-C_A_PrA_C_IT,A_N_C.,E---,

>

160~-r--r--r--r-

:sw

140~-+--+--+--~--~~~+--1

~

120~-t--t--+--~~

~

100

o

if
o

~ 160
CL = 15 pF
I
;

140

w
o 120
Z

~
t:I

ifo

80

a:

60

II.

I

I

40

a:

a

20~~~~-+~~~~~--~~

tPLH "...... I-"

80

II.

a

VDO = 5 V

o 100

20

o

°O~~~~~~~~~~~~

f-:k::f-

-::: ~ ~
tPLH

-----

1'~

10
h-- VOID =

.\1::"

IL tP~~ r-ro~ = 1 5V
1

-60 -40 -20 0 20 40 60 80100120140
TA - AMBIENT TEMPERATURE - °C

CL - LOAD CAPACITANCE - pF

SWITCHING WAVEFORMS

FOR

-

.l>

tPHL

t;:; a 5 V

MINIMUM PULSE WIDTH
RECOVERY TIME

CP AND MR AND MR

3-51

FAIRCHILD CMOS • 34025
TRIPLE 3-INPUT NOR GATE

DESCRIPTION - This CMOS logic element provides a 3-input positive NOR function. The outputs are fully buffered for highest noise immu·
nity and pattern insensitivity of output impedance.

LOGIC AND CONNECTION DIAGRAM
DIP (TOP VIEW)

NOTE:
The Flatpak version has the same pinouts
(Connection Diagram) as the Dual In-Line

Package.

DC CHARACTERISTICS: VDD as shown. VSS = 0 V
LIMITS
SYMBOL

PARAMETER

MIN

IDD

Quiescent
Power
Supply
Current

=5 V

V DD

TYP

=10V

V DD
MAX

MIN

TYP

0.5
15.0
0.05
3.0

XC
XM

=15 V

V DD

MAX

MIN

TYP

5.0
30.0
0.1
6.0

UNITS

TEMP

TEST CONDITIONS

MAX

1.0
6.0
0.02
1.2

~A

~A

MIN. 25°C
MAX
MIN. 25°C
MAX

All inputs common
and at 0 V or V DD

NOTE: Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Characteristics.

AC CHARACTERISTICS: VDD as shown. VSS

= 0 V. TA = 25°C
LIMITS

SYMBOL

PARAMETER

VDD
MIN

=5V

VDD

TYP

MAX

30
35

75
75

tpLH
tpHL

Propagation Delay

tTLH

Output Transition
Time

15
16

75
75

tpLH
tpHL

Propagation Delay

45
47

110
110

tTLH
tTHL

Output Transition
Time

38
38

135
135

tTHL

..

MIN

=lOV

V DD

TYP

UNITS

MAX

13
20

40

12

40

16

8
6

40
40

6
4

20
25

60
60

15
21

ns
ns

20
15

70
70

15

ns
ns

NOTE: Propagation delays and output transition times are graphically described

MIN

=15 V

TYP

11
In

TEST CONDITIONS

MAX

25
25

ns
ns

CL = 15pF

ns

Input Transition Times.;; 20 ns

ns

45
45

CL

=50 pF

Input Transition Times.;; 20 ns

this section under 34000 Senes CMOS Family Characteristics.

TYPICAL ELECTRICAL CHARACTERISTICS
PROPAGATION DELAY
VERSUS TEMPERATURE
40
35

Q

30

z
2

26

~
f
I

~

~

~

INPUT FREQUENCY -

Hz

CL=15pF

~

I I Jrl-

I

;

,.- f.-t;;;L Vee = 5 v I1.

16
10 1_

tPLH tpHL Voo

=10 V

1

f- f-' -t:t:T 1
tPL

6

w

tpHL Voo

=15 V

o~

--

0:
0-

I

:s

II-

l JJ I

..l

0
-60-40-200 20408080100120140
TA -

AMBIENT TEMPERATURE -

3·52

TA=250C

120r-~-+--t-~-1--+--t~

~100r--r~--~~--+--+--t-.,
o
~ 80

..-ht1

l- I- tPLHVOD = 6 V

20

PROPAGATION DELAY
~ 14¥ERSUS LOAD ~APACITANCE

oc

j

60r--r~--~~--+-~~~.,
40~~~~~~--~~~T-"

20 k

J:::::t:=t:=¥t:"111

°0~~2~0~40~~60~~B=0~1~0~0~1~2~0~1~40~160
CL - LOAD CAPACITANCE -

pF

34027
DUAL JK FLIP-FLOP

DESCRIPTION - The 34027 is a Dual JK Flip·Flop which is edge·triggered and features independent

I----L-OG;~ SYMBOL

Direct Set, Direct Clear, and Clock inputs. Data is accepted when the Clock is LOW and transferred to
the output on the positive-going edge of the Clock. The active HIGH asynchronous Clear Direct (CD)
and Set Direct (SO) are independent and override the J, K, or Clock inputs. The outputs are buffered

for best system performance.

CD

PIN NAMES

J, K

a

Q

Complement Output

CP

o---r--

14

I
I

1)--+--

Synchronous Inputs
Clock Input (L -. HEdge-Triggered)
Asynchronous Direct Set Input (Active HIGH)
Asynchronous Direct Clear Input (Active HIGH)
True Output

SD
CD

0

!

I

i

'DO~'

I
_______ J

TRUTH TABLE
INPUTS

So

J

K

On+1

H

L

X

X

X

H

L

L

H

X

X

X

L

H

H

H

X

X

X

H

H

L

L

.s
.s
.s
.s

L

L

L
L

L
L
H

.s

L

~

16

Pin 8

--

CP

L

= Pin

OUTPUTS

CD

L

Voo

VSS

CONNECTiON DIAGRAMS
DIP (TOP VIEW)

°n+1

NO CHANGE

H

L

H

L

L

H

H

H

H

L
On

On

= LOW Level
= HIGH Level

10

= Positive ·Going TranSition

X

= Don't

0n+1

=.

Care
State After Clock Positive Transition

NOTE:
The F latpak version has the same
pinouts (Connection Diagram! as the
Dual I n~Line Package.

3-53

FAIRCHILD CMOS • 34027
DC CHARACTERISTICS: VOO as shown, VSS = 0 V
LIMITS
SYMBOL

VOO = 5 V

PARAMETER

MIN

'00

Quiescent
Power
Supply
Current

TYP

VOO = 15 V

VOO = 10V
MAX

MIN

TYP

MAX

XC

10
140

20
280

XM

1
60

2
120

MIN

TYP

UNITS

TEMP

TEST CONDITIONS

MAX

4
56
0.4
24

~A
~A

MIN,25°C
MAX
MIN,25°C
MAX

All inputs common
and at 0 Vor VOO

NOTE: Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Characteristics.

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VOO as shown, VSS = OV, TA = 25°C
LIMITS
SYMBOL

PARAMETER

VOO= 10V

VOO = 5 V
MIN

TYP

MAX

75
75

MIN

VOO = 15V
MIN

TYP

UNITS

TEST CONDITIONS

TYP

MAX

MAX

150
150

35
35

75
75

25
25

ns
ns

CL =15pF

80

150

60

ns

Input Transition

ns

Times.;;; 20 ns

tpLH
tpHL

Propagation Delay,
CPtoQ,O

tpLH

Propagation Delay, So to Q

160

300

tpHL

Propagation Delay, Co to Q

160

300

80

150

60

tTLH
tTHL

Output Transition
Time

50
50

100
100

30
30

60
60

20
20

tpLH
tpHL

Propagation Delay,
CPtoQ,O

100
100

200
200

45
45

85
85

30
30

ns
ns

CL =50pF

tpLH

Propagation Delay, So to Q

180

350

90

175

75

ns

Input Transition

tpHL

Propagation Delay, Co to Q

180

350

90

175

75

ns

Times " 20 ns

tTLH
tTHL

Output Transition
Time

85
85

150
150

45
45

85
85

30
30

ts
th

Set-Up Time, J, K to CP
Hold Time, J, K to CP

100
0

45
-25

40
0

20
-10

15
-5

ns
ns

twCP(L)

Minimum Clock Pulse Width

150

75

70

35

25

ns

CL =15pF

tw So(H)

Minimum So Pulse Width

150

75

60

30

25

ns

Input Transition

twCo(H)

Minimum Co Pulse Width

150

75

60

30

25

ns

Times" 20 ns

trec So

Recovery Time for So

0

-5

0

-4

-3

ns

tree Co

Recovery Time for Co

0

-5

0

-4

-3

fMAX

Maximum CP Frequency (Note 2)

4

8

8

16

40

40

50
50

ns
ns

ns
ns

ns
MHz

NOTES:
1. Propagation Delays (tPLH and tpHL) and Output Transition Times {tTLH and tTHL} will change with Output Load Capacitance (eL)'
Set-up Times (t 5), Hold Times (th), Recovery Times (tree), and Minimum Pulse Widths (tw) do not vary with load capacitance.
2. For fMAX, input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.
3. Propagation Delays and Output Transition Times are graphically described in this section under 34000 Series CMOS Family Characteristics.
4. It is recommended that input rise and fall times to the Clock I nput be less than 15 }Js.

3-54

FAIRCHILD CMOS • 34027
TYPICAL ELECTRICAL CHARACTERISTICS
POWER DISSIPATION
VERSUS FREQUENCY

PROPAGATION DELAY
VERSUS TEMPERATURE

~100

«
...J

-

CL 015 pF

I 90

>

VDO - 5 V

80

f-"'""

W

0
2
0

i=

«
Cl
«
Q.

0

0:
Q.

o

70

...... V

60

I-'"

---

50
VOD 0 10V

40
i-- I -

30

l - i--

20

--

r-I - VDO

-

0 15V

~ 10

o

Q.

U

-60 -40 -20 0

INPUT FREQUENCY - Hz
PROPAGATiON DELAY
VERSUS POWER SUPPLY VOLTAGE

~

300 TA::: 250C

S

~200

I

1180

z

o

2501---J\---+---+- - 1 - - 1 - - - 1

TA 0 25°C

~

:3160

w
°140

2001---+-~-+--+--1--+--~

VDD

Z

g120

i=

~ 1501--~--+~

~100

if
~ 100r---P~~~~~~+---1-­

o

I

o

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

>

w

o

20 40 60 80 100120140

TA- AM81ENT TEMPERATURE - °C

50

~

if
8:

80

oI

40

y

/"

/ 'V

Jooo~ ~

:/

- -'1+

60

~

V

~

~ 20

Q.

~ °0

U

O

20

VDO - POWER SUPPLY VOLTAGE - V

CL -

40

60

80 100120 140 160

LOAD CAPACITANCE -

pF

SWITCHING WAVEFORMS

----"1
SD

CP

twSD(H)

1""--

~_______________________

-

NOTE:
ts & th are shown as positive values but may be
specified as negative values.

SET-UP TIMES, HOLD TIMES,
AND MINIMUM CLOCK PULSE WIDTH

RECOVERY TIME FOR SO, RECOVERY TIME FOR CD,
MINIMUM So PULSE WIDTH, AND MINIMUM CD PULSE WIDTH

3-55

34028
I-OF -10 DECODER
DESCRIPTION - The 34028 is a CMOS 4-bit BCD to 1-of-10 active HIGH decoder. A 1-2-4-8 BCD

.-------------LOGIC SYMBOL

code applied to input'S AO through A3 causes the selected output to be HIGH, the other nine will be
LOW_ If desired, the 34028 may be used as a 1-ofB decoder with enable; 3-bit octal inputs are applied
to inputs AO. A1, and A2 selecting an output 0 through 7. Input A3 then becomes an active LOW
enable, forcing the selected output LOW when A3 is HIGH. The 34028 may also be used as an g··input

demultiplexer with an act1ve LOW data input. The outputs are fully buffered for best performance.

•

•
•

BCD TO 1-0F-l0 DECODER
1-0F-8 DECODER WITH ACTIVE lOW ENABLE
a-INPUT DEMULTIPLEXER WITH ACTIVE LOW DATA INPUT

PIN NAMES
AO -- A3

:340:-8

Add,ess Inputs, 1-2-4-8 BCD
Outputs (Active HIGH)

00-- 09

TRUTH TABLE
OUTPUTS

INPUTS
A3

A2

VDO =- Pin 16

VSS

01 02 0 3 0 4 0 5

A1

l

L

L

L

L

L

L

L

L

L

H

L

L

L

L

L

L.

L

L

L

L

H

L

L

L

L

L

L

L

H

L

L

L

H

L

L

L

L

L

L

L

1-

l

L

L

H

L

L

l

L

L

L

H

L

L

L

L

L

H

L

L

L

L

H

H

L

L

L

L

L

L

L

H

L

L

L

H

H

H

L

L

L

L

L

L

L

H

L

L

L

L.

L

l

L

L

L

H

L

L

H

L

H

L

L

H

L
L

H

H

L

L

L

L

L

L

L

L

H

L

L

H

L

L

L

L

L

H

L

H

L

L

L

L

L

L

H

L

H

H

L

L

L

L

l

L

H

1-1

l

L

L

L

L

L

L

L

L

L

H

L

H

H

L

H

L

L

L

L.

L

L

L

L

L

H

H

H

H

L

L

L.

L

L

L

L

L

H

L

H

H

H

H

L

L

L

L

l

l

L

L

H

L

L

L.

L

H

L

L.

H

L.

L

H

L

L

L

L

1
2

:<
4
5

H

=

HIGH Level

Pin 16
Pin 8

o "" Pin Numher

vOLl

16

03

15

OLJ

U,

14

07

,\,

13

Og

A2

12

"

Dual I n line Package
----~--------

00

VSS

04

OJ

NOTE
The F latpak verSIOn has the same
(
ponouts (Connection D,agram) as theJ

0)

VDD

fl
r

~

DIAGRAM

C>-

Pin 8

CONNECTION DIAGRAM
DiP (TOP VIEW)

L= LOW Level

@

::=

------_._-_.,_. __.__._._-"--------

FAIRCHILD CMOS • 34028
DC CHARACTERISTICS: VDD as shown, VSS = 0 V

MIN
Quiescent
Power
Supply
Current

IDD

LIMITS
V DD =10V

V DD = 5 V

PARAMETER

SYMBOL

TYP

MAX

MIN

TYP

30
600
5
100

XC
XM

V DD = 15 V

MAX

MIN

60
1200
10

TYP

UNITS

12
240
2
40

200

TEMP

TEST CONDITIONS

MAX
MIN,25°C
MAX
MIN,25°C
MAX

~A

~A

All inputs common
and at 0 V or VDD

NOTE: Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Characteristics.

AC CHARACTERISTICS: VDD as shown, VSS = 0 V, TA = 25°C

SYMBOL

LIMITS
V DD = 10V

V DD = 5 V

PARAMETER

MIN

TYP

MAX

MIN

VD D = 15V

TYP

MAX

MIN

TYP

tpLH

Propagation Delay,

145

290

An to On

125

290

60
45

130

tpHL

130

37
30

tTLH
tTHL

Output Transition
Time

40
40

100
100

20
20

60
60

15
15

tpLH
tpHL

167
157

325
325

66
57

145
145

45

An to On

tTLH
tTHL

Output Transition
Time

85
110

20C
200

40
37

100
100

31
25

Propagation Delay,

UNITS

TEST CONDITIONS

MAX
ns
ns

CL = 15 pF
Input Transition Times .. 20 ns

ns
ns

40
40

ns
ns

40
70
70

CL = 50 pF
Input Transition Times .. 20 ns

ns
ns

NOTE:
Propagation Delays and Output Transition Times are graphically described in this section under 34000 Series CMOS Family Characteristics.

1.

TYPICAL ELECTRICAL CHARACTERISTICS

POWER DISSIPATION
VERSUS FREQUENCY

~

E'0oorrm-"nT'-~-rrm~TnTO

~

S
'~:
if
ffi

TA::: 25oc

lll

~

111111111

Voo

1.0

1SV

o
~
~

•.,

VOO=10V

••'

~ 10-1 t-tttt-+-1+-ft';,j)~\'
~
.....:: ... :::

r.? ...

'",:::r"'++tH-ttfH

:1:1'.'Ii'

",

~1~2~~B:·~::~;~·'~~~I~'D~rIU~I~·5IV~~
~ 10-3 i:>t"+--t+tt+tttI+'Cf"L'"'="1=-5-I:pF=,*-i
1:'::'.1':

~ 10_4'::"-cu...."'"::".LLl.-'-:-!.J.U-'-:C"'L~~_50"'"'""PF~.~
...

..J.

II.

102

103

2
I
>-

104

106

INPUT FREQUENCY -

106
Hz

107

PROPAGATION DELAY
VERSUS TEMPERATURE
200

CL-15pF

180
160
"0 -

120 _

I
I

<&~ _
V
r-+- ~1];0!i'0'""l':-:-'--t--+--+r-\--I
Vr-'

100f---+-+-++-r-r-+-+-+--+
~ 80 f---+-+-++-r-+-+-+=Io--+
IE 50 -f---f--- "Oo<'O~-

o

I

tS
g
~

40_~f::~~\5V
-

20 f-+-+-+-+-1f-+-+-+-+--i

~

~
z

~.

f

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE
300
2&0

;25~C
I

i-l .v~
.2*b~

200f-~-+--+-~~--+--r--i
160

~~

1~ tP~L V\,D =J'0 V\

100f---~rf-+I_t-I~l~+--+~~-i

t'LII~'n='O"

I

d

TA

::':::

50

~6~0~--~20~~20~~6~O-L~1~00~~1~'0
TA - AMBIENT TEMPERATURE - °C

3-57

Cl - LOAD CAPACITANCE - pF

34029
SYNCHRONOUS UP jDOWN COUNTER
DESCRIPTION - The 34029 is a Synchronous Edge-Triggered Up/Down 4-Bit Binary/BCD Decade
Counter with a Clock Input (CPl.an active LOW Count Enable Input (CE),an Up/Down Control Input
(UP/DN), a Binary/Decade Control Input (BIN/DEC), an overriding asynchronous active HIGH
Parallel Load Input (PL), four Parallel Data..!!!?uts (PO-P3), four Parallel Buffered Outputs (QO-Q3)
and an active LOW Terminal Count Output (TC).

LOGIC SYMBOL
4

Information on the Parallel Inputs (PO-P3) is loaded into the counter while the Parallel Load Input
(PL) is HIGH, independent of all other input conditions. With the Parallel Load Input (PL) LOW,
operation is synchronous and is edge-triggered on the LOW-to-H IGH transition of the Clock Input
(CP)' Operation is determined by the three synchronous Mode Control Inputs; UP/ON, BINIDEC and
CE (see the Mode Selection Table), These inputs must be stable only during the set-up time prior to
the LOW-to-HIGH transition of the Clock Input (CP) and the hold time after this clock transition.
The Terminal Count Output (TC) is LOW when the counter is at its terminal count, as determined by
the counting mode, and the Count Enable Input (CE) is LOW (see Logic Equation for TCI.

12

13

3

UP/DN

10

34029

TC

CE

CP

15

6

11

14

2

VOD = Pin 16

•
•
•
•
•
•

BINARY OR DECADE UP/DOWN COUNTER
ASYNCHRONOUS PARALLEL LOAD
ACTIVE LOW COUNT ENABLE
CLOCK EDGE·TRIGGERED ON THE LOW·TO·HIGH TRANSITION
ACTIVE LOW TERMINAL COUNT FOR CASCADING
TYPICAL COUNT FREQUENCY OF 12 MHz AT VDD = 10 V

PIN NAMES
PL
PO-P3
BINIDEC
UP/DN
CE
CP
QO-Q3
TC

= Pin 8

VSS

CONNECTION DIAGRAM
DIP (TOP VIEW)

Parallel Load Input
Parallel Data Inputs
Binary/Decade Control Input
Up/Down Control Input
Count Enable Input (Active LOW)
Clock Input (L .... H Edge-Triggered)
Buffered Parallel Outputs
Terminal Count Output (Active LOW)

16

15
14

13
12
11

10

MODE SELECTION TABLE
PL
H
L
L

UP/DN

CE

CP

MODE

X

X

X

X

Parallel Load (P n .... Qn)

X

X

H

X

L

L

L

..r
..r
..r
..r

BIN/DEC

L

L

H

L

L

H

L

L

L

H

H

L

No Change
Count Down, Decade

NOTE:

Count Up, Decade

H=HIGHLevel

The F latpak version has the same

Count Down, Binary

L = LOW Level

Count Up, Binary

X = Don't Care
I = Positive-Going Transition

pinouts (Connection Diagram) as the
Dual In-Line Package.

34029 STATE DIAGRAM, BIN/DEC = HIGH

34029 STATE DIAGRAM, BIN/DEC = LOW

~-E}:GEt=:

4

~

~

~-13....,'-..--...--'r-"'--

.....

CDUNTUP---

COUNTUP--COUNT DDWN- -

COUNT DDWN- -

-

-

LOGIC EQUATION FOR TERMINAL COUNT
TC

= CE.

[((UP/ON).

00. Q3.

((Ql • Q2)

+ (BINi5EC))) + ((UP/DN)

3-58

• QO· Ql • Q2· Q3

FAIRCHILD CMOS • 34029
LOGIC DIAGRAM

CD

"~~--~----------------~--------1-----------~~--+---------~~--~---------+1-~-+-+---------'

®

(j)

®

VDD

~

Pin 16

VSS

=

Pin 8

o=

fi
T

"

e'

Q

Q

Pin Number

j5'[ (Parallel Load Input) - Asynchronously L.oads P into a, Overriding all Other Inputs
P (Parallel Input) - Data on this Pin is Asynchronously Loaded into Q, when PL is LOW Overriding all Other Inputs
T (Toggle Input) - Forces the Q Output to Synchronously Toggle when a LOW is Placed on this Input.
CP (Clock Pulse Input)
a, (True and Complimentary Outputs)

a

DC CHARACTERISTICS: VDD as shown, VSS = 0 V

LIMITS
SYMBOL

PARAMETER

VD D = 5 V
MIN

c

IDD

Quiescent
Power
Supply
Current

XC
XM

TYP

VD D =15V

VDD = 10V
MAX
50
700
5
300

MIN

TYP

MAX
100
1400
10
600

MIN

TYP
20
280
2
120

UNITS

TEMP

~A
~A

MIN,25°C
MAX
MIN,25°C
MAX

NOTE: Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Characteristics.

3-59

TEST CONDITIONS

MAX
All inputs common
and at a V or VDD

FAIRCHILD CMOS • 34029
AC CHARACTERISTICS AND SET-UP REOUIREMENTS: VDD as shown, VSS = 0 V, TA = 25°C
LIMITS
V DD =10V

VDD = 5 V

PARAMETER

SYMBOL

MIN

TYP

MAX

MIN

TYP

V DD = 15 V

MAX

MIN

TYP

UNITS

TEST CONDITIONS

MAX

tpLH
tpHL

Propagation Delay,
CP to On

135
135

54
50

35
33

ns
ns

tpLH
tpHL

Propagation Delay,
CP to TC

150
228

62
90

42
60

ns
ns

tpLH
tpHL

Propagation Delay,
PL to On

152
194

59
80

38
56

ns
ns

tTLH
tTHL

Output Transition
Time

25
25

13
13

10
10

ns
ns

tpLH
tpHL

Propagation Delay,
CP to On

150
150

62
59

41
39

ns
ns

tpLH
tpHL

Propagation Delay,
CP to TC

167
252

71
100

48
66

ns
ns

tpLH
tpHL

Propagation Delay,
PL to On

170
220

70
90

45
62

ns
ns

tTLH
tTHL

Output Transition
Time

60
65

31
25

23
18

ns
ns

twCP

CP Minimum Pulse Width

50

21

14

ns

twPL

PL Minimum Pulse Width

60

21

16

ns

tree

PL Recovery Time

62

24

17

ns

ts
th

Set-Up Time, BIN/DEC to CP
Hold Time, BIN/~ to CP

106
104

41
40

29
28

ns
ns

ts
th

Set-Up Time, UP/ON to CP
Hold Time, UP/ON to CP

145
101

55
38

38
25

ns
ns

ts
th

Set-Up Time, CE to CP
Hold Time, IT to CP

118
101

49
38

33
25

ns

ts
th

Set-Up Time, Pn to PL
Hold Time, Pn to PL

29
26

11
7

8
4

ns
ns

fMAX

Input Clock Frequency

5

12

CL = 15 pF
Input Transition
Times';;; 20 ns

CL = 50 pF
Input Transition
Times';;; 20 ns

CL = 15 pF
Input Transition
Times.;;; 20 ns

MHz

NOTES:
1. Propagation Delays and Output Transition Times are graphically described in this section under 34000 Series CMOS Family Characteristics.
2. Propagation Delays (tPLH and tpHL) and Output Transition Times (tTLH and tTHL) will change with Output Load Capacitance (eL)'
Set~up Times (t s ), Hold Times (th), Recovery Times (tree), and Minimum Pulse Widths (tw) do not vary with load capacitance.

rb

3. For fMAX, input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.
4. It is recommended that input rise and fall times to the Clock I nput be less than 15 p,s.

SW'TC"'NG WAVEFORMS

....-'twcp ---..

--I

CP

50%

50%

FGM-

---- 's ----

~\
CE

cp~FL
1--'wPl ......

...--th~

50%

1\50%

/

V

Pl

~V;;;:\ ~50%
,

....... ts(H)~ -+-th(H) ...... ....... t s( L)--+- -'hlll--

-

BIN/DEC

1.(50%

\

50%

~

/

~

. / 50%

Pn

~~O%

.....-ts(H)--+- --'hI HI ...... - 4 - ts ( L) ---. _'hl ll __

-

UP/DN

1/50%

\

1\50%

I....... trec ....

)-

'n-

JV:::-

MINIMUM CP WIDTH, SET-UP AND HOLD
TIMES, CE TO CP, BIN/DEC TO CP AND UP/ON TO CP

MINIMUM P.L PULSE WIDTH, RECOVERY
TIME FOR PL, AND SET-UP AND HOLD TIMES, Pn TO PL

NOTE: Set-up and Hold Times are shown as positive. values but may be specified as negative values.

3-60

FAIRCHILD CMOS • 34029
TYPICAL ELECTRICAL CHARACTERISTICS

"c

POWER DISSIPATION
VERSUS FREQUENCY

3:

E 1000r"

S
w

220

140
120

~

Cl

BO

~

40

a::
-"

:t:

ei
....
e-

~

-

-

tPLH

I

~ ;:-...,.~ p-

......",:~ F

~

~D~=15VT

r-

20
0
O

20
CL -

f--

J\

I--VDD = 10 V"

60

r---

~
.c:. :::- tPLH-

~

100

--+--------,.---+--------......---1--------.ri--+-------..-+---+-------......+---I-------

CLOCK

Fig. 1 RIPPLE CLOCK EXPANSION

PARALLEL LOAD
BIN/DEC
UP'DOWN

I I I I

I I I I

L..-I

IBIN/mPQP1P2P3

' - - UP'DN
---0

CLOCK

f

C-

P2

BIN/DEC Po

7° ~2 l~3
1'

UP

')4029

TC

ep

'---

up'oN

34029
CE

I I I I

'- '" P,,-

P3

P,

CE

[eP

TC

00 0,

02 03

I I I I

r

Po

P1

P2

DN
34029

CE

00 01

cp

P3

rep--

02 Cl3

I I I I

Fig. 2 PARALLEL CLOCK EXPANSION (FULLY SYNCHRONOUS)

-------------1r--------.--+--------..---+--------.....---tl--------......-1---+-------...-+---+-------.....-+--+-------

PARALLEL LOAD - - - - . . . - - - - - - - - - - -.....
!OlIN/DEC
UP/DOWN

Fig. 3 SEMI·SYNCHRONOUS EXPANSION

------------.-----------t-------

PARALLEL LOAD - - - -.....

----1r--+--------.......--+---------..--+------UP/DOWN -,rll---+-------.......+---+--------..+--+------BIN!DEC

UP/ON

UP/DN

34029

- 0 eE

cr

CLOCK

Fig. 4 HIGH SPEED SEMI·SYNCHRONOUS EXPANSION

3·62

FAIRCHILD CMOS • 34030
QUAD EXCLUSIVE-OR GATE

DESCRIPTION - The 34030 CMOS logic element provides the Exclusive-OR function. The outputs are fully buffered for best performance.
34030 QUAD EXCLUSIVE-OR GATE

NOTE:

The F latpak version has the same pinouts
(Connection Diagram) as the Dual In-Line
Package.

x ~ AB

+

AS

I

DC CHARACTERISTICS: V DD as shown, VSS = 0 V
LIMITS
V DD = 5 V

PARAMETER

SYMBOL

MIN
Quiescent
Power
Supply

IDD

TYP

MAX

MIN

XM

VDD = 15 V

MAX

TYP

5.0
70.0
0.5

XC

Current

VDD=10V

MIN

10.0
140.0
1.0
60.0

30.0

UNITS

TEST CONDITIONS

TEMP

MAX

TYP
2
28

~A

0.2
12

~A

MIN,25°C
MAX
MIN,25°C
MAX

All inputs common
and at 0 Vor VDD

NOTE: Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Characteristics.

AC CHARACTERISTICS: VDD as shown, VSS = 0 V, TA = 25°C
LIMITS
VDD = 10V

V DD = 5 V

PARAMETER

SYMBOL

MIN

TYP

MAX

MIN

V DD=15V

TYP

MAX

MIN

TYP

33
33

65
65

23
23

UNITS

Propagation Delay,
AorBtoX

65

130

65

130

Output Transition
Time

23
23

45

tTHL

45

10
10

25
25

8
8

tpLH
tpHL

Propagation Delay,

85

45
45

27

85

170
170

90

AorBtoX

90

27

tTLH
tTHL

Output Transition
Time

50
50

100
100

23
23

50
50

17

35

17

35

tpLH
tpHL
tTLH

TEST CONDITIONS

MAX
ns
ns

CL = 15 pF

20

ns

Input Transition Times .. 20 ns

20

ns
ns
ns

CL = 50 pF

ns
ns

I nput Transition Times .. 20 ns

NOTE:' Propagation delays and output transition times are graphically described in this section under 34000 Series CMOS Family Characteristics.

TYPICAL ELECTRICAL CHARACTERISTICS
~
E 1000

I

~

100

~

10

~

1,0

2

52

10-

PROPAGATION DELAY
VERSUS TEMPERATURE

POWER DISSIPATION
VERSUS FREQUENCY

TflilT1iI111111111

II

I1I1

VOO=10V'

Jb~ .,6V

1

!

~~

!!!

~

ffi 10-3

~ 'O-~02

'~

,

V

/

~
a

10- 2

/~

I 100 CL = 15 pF
0

103

~
"

80
70

~

60

:

50

If

40

o

/

~

Voo· 5 V I

111111~L~15PFCL = 60 pF __

104

106

108

INPUT FREQUENCY - Hz

107

~
I

!

l~oo<6~

-

0

TA = 26°C

9

~

PROPAGATION DELAY
LOAD CAPACITANCE

14 VERSUS

;:::: ;-

--

120

I.l>-I~ ,/'"

Q

~ 10 0

~

Vee = 16 V I-

20

w

~

F=

Voo =,0 v

30

;

10

:

80

f

6


0

15

w

a::

LL

"U

I IIII
104

105

CLOCK FREQUENCY -

106

,I

5

o

Hz

'/

-

-

'.

I

II

..J

107

V'

/

I

10

0

U

/

I
I

20

Z

CL-15pF-CL = 50 pF - - 103

ii

25

>
U

~P9 =I~ I~

TA - 25°C
CL= 15 pF

30

N

o

Y

5

--

10

15

VDD - POWER SUPPLY VOLTAGE - V

PROPAGATION DELAY
VERSUS TEMPERATURE

.

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

c

180

>

160

CL = 15 pF

>

:3

140~+-~-+~~+-4-

~ 120 ~+-~-+--'

Z

o
i=
«
o
~
o

:3w

140

Z

120

Cl

100~4--+~~+-~.

0

i= 100

«
0
«
11.

80~~-+~~~~-+--~4--+-1

a::

11.

11.

I

I

o

0

o

0
0

o

I-

I~

80

0

a::

60
40
20

I-

iQ.
.U

20

40
TA - AMBIENT TEMPERATURE - °C

40

100120140160

CL - LOAD CAPACITANCE - pF

SWITCHING WAVEFORMS

MR

CP

l~tTHL
PROPAGATION DELAY MASTER
RESET TO OUTPUT. MINIMUM MASTER RESET
PULSE WIDTH AND RECOVERY TIME FOR MASTER RESET

PROPAGATION DELAY CLOCK TO
OUTPUT QO. OUTPUT TRANSITION
TIMES AND MINIMUM CLOCK PULSE WIDTH

3-69

I

34042
QUAD D LATCH

DESCRIPTION - The 34042 is a 4-Bit Latch with four Data Inputs (00-03), four buffered Latch
Outputs (00-03), four buffered Complementary Latch Outputs (00-03) and two Common Enable
Inputs (EO and El). Information on the Data Inputs (00-03) is transferred to the Outputs (°0-03)
while both Enable Inputs (EO, El) are in the same state, either HIGH or LOW. The Outputs (00-03)
follow the Data Inputs (00-03) as long as both Enable Inputs (EO, El) remain in the same state. When
the two Enable Inputs (EO, El) are different, the Data Inputs (00-03) do not affect the Outputs
(00-03) and the information in the latch is stored. The
3 Outputs are always the complement
of the 00-03 Outputs. The Exclusive-OR input structure allows the choice of either polarity for the
Enable Input. With one Eaable Input HIGH, the other Enable Input is active HIGH; with one Enable
Input LOW, the other Enable Input is active LOW.

LOGIC SYMBOL

00-15

The last moment prior to the trailing end of the enable condition that the Latch Outputs can still be
affected by the inputs is specified as a set'up time. A negative set-up time, as typically exhibited by
this device, means that the latches respond to input changes after the end of the enable condition.
Following established industry practice, a hold time is specified, defining the time after the end of the
enable condition, that the inputs must be held stable, so that they do not affect the state of the
latches. It follows from this definition, that the hold time is identical with the negative set-up time.
Set-up and hold times have a tolerance, due to manufacturing process variations, temperature and
supply voltage changes. For predictable operation the data input levels must be held stable over the
full spread of this timing window starting with the earliest set-up time (largest positive or smallest
negative value) to the latest hold time.

4

! :::}[)

ACTIVE HIGH OR ACTIVE LOW ENABLE
TRUE AND COMPLEMENTARY OUTPUTS (Q & 0)

EO
L
L

PIN NAMES
00-0 3
EO, El
00-0 3

00--03

Data Inputs
Enable Inputs
Parallel Latch Outputs
Complementary Parallel Latch Outputs

H
H

El
L
H

13 14

34042

2

3

10

9

11

12

1

15

Voo = Pin 16
VSS = Pin 8

TRUTH TABLE
•
•

E

7

LATCH CONDITION
Enabled
Not Enabled

L

Not Enabled

H

Enabled

CONNECTION DIAGRAM
DIP (TOP VIEW)

L = LOW Level
H ::: HIGH Level

LOGIC DIAGRAM
16
D,

CD

D2

@

D3

15

@

14
13
12
11

10

NOTE:
VOD::: Pin 16

The

VSS

pinouts (Connection Diagram) as the

o

=

Pin 8

=

Pin Numbers

Flatpak version has the same

Dual In-Line Package.

3-70

FAIRCHILD CMOS • 34042
DC CHARACTERISTICS: VOO as shown, VSS = 0 V
LIMITS
SYMBOL

MIN
Quiescent

Power
100

Supply
Current

VOO = 10V

VOO = 5 V

PARAMETER

TYP

XC
XM

MAX

MIN

TYP

VOO=15V
MIN

MAX

TYP

10

20

4

140

280

56

1

2

60

120

0.4
24

UNITS

TEMP

TEST CONDITIONS

MAX
~A

~A

MIN,25°C

All inputs common

MAX

and at 0 V or VOO

MIN,25°C
MAX

NOTE: Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Characteristics.

I
AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VOO as shown, VSS = 0 V, TA = 25°C
LIMITS
SYMBOL

PARAMETER

VOO = 5 V
MIN

VOO=10V

TYP

MAX

MIN

VOO=15V

TYP

MAX

MIN

TYP

UNITS

TEST CONDITIONS

MAX

tpLH
tpHL

Propagation Delay,
Data to Output

85
80

170
160

36
35

72
70

26

ns
ns

CL = 15 pF

tpLH
tpHL

Propagation Delay,
Enable to Output

135
115

270
230

55
45

110
90

41
35

ns
ns

Input Transition
Times < 20 ns

tTLH
tTHL

Output Transition
Time

29
27

75
75

15
15

40
40

11
10

tpLH
tpHL

Propagation Delay,
Data to Output

101
99

200
200

45
44

90
88

33
33

ns
ns

CL = 50 pF

tpLH
tpHL

Propagation Delay,
Enable to Output

156
137

310
275

66
58

132
116

47
41

ns
ns

Input Transition
Times ~ 20 ns

tTLH
tTHL

Output Transition
Time

65
60

135
135

31
26

70
70

25
20

ts
th

Set-Up Time, On to EO or El
Hold Time, On to EO or El

10
50

-12
25

10
25

-6
13

-4
7

ns
ns

Input Transition

twEn

Minimum Enable Pulse Width

80

40

32

16

12

ns

Times

27

25
25

45
45

ns
ns

ns
ns
CL

= 15 pF
<

20 ns

NOTE:
1. Propagation Delays (tPLH and tPHL) and Output Transition Times (tTLH and tTHL) will change with Output Load Capacitance
Set-up Times (t s )' Hold Times (th), and Minimum Pulse Widths (tw) do not vary with load capacitance.

3-71

(eLl.

FAIRCHILD CMOS • 34042
TYPICAL ELECTRICAL CHARACTERISTICS

~
TYPICAL POWER DISSIPATION
~ 1000
VERSUS FREQUENCY

"~

100

~

..ffi

TA='25'C 1111
t ttU~f'!1-,15V
VOD"'15V

10

Z

/~

1.0

o

~

/
/

10- 1

0:

/

~

10-3

~
C3

10- 4
10 2

o

Q

~~

104

105

~~

60

g

20

Q.::

...o

106

~

INPUT FREQUENCY - Hz

~

80

0::>

I I ICL~1~pF
---CL= 50 pF

103

...1120

g~ 100

40

•

V

I- tt

--;1#

~~

~

~ f..- ......

I'-

l~

~-I

I

I

I

I

I

I

L tpLH. tpHl. DATA TO OUTPUT

40

5

20

~

0

-60-40-200 20406080100120140
TA - AMBIENT TEMPERATURE -

~

140

TA - 25°C
CL=15pF

1

:I:

120

l:i
jE

100

~

80

~

~

60

"~

40

:;

:>

:;

\

",,""

\
\

o

180 f--i--t--+-I----j~l~+_++-I

~~

160

;~

1"'--

20

PROPAGATION DELAY
VERSUS TEMPERATURE
200

~

w"
i=~

40

~ < 20
~

o

80

O~ 60~~~~~~~~~~~~
~~

..........

15

10

Voo - POWER SUPPLY VOLTAGE - V

~

I
I

tpLH. ENABLE TO OUTPUT

I

I

20 40 60 80 100 120 140 160
CL - LOAD CAPACITANCE - pF

C

~5100

\

V

1"-- tpHt.. ENABLE TO OUTPUT
Lt- tPLH. tPHL. DATA TO OUTPUT
0

°C

;~140~+-++-+~---jr-+-~~~
~ ~ 120 f--+--+_+-

Z

:i1

~

rrr

60

If~

"
MINIMUM ENABLE PULSE
WIDTH VERSUS
POWER SUPPLY VOLTAGE

r

)..-

lrh

80

~~

I I I

o

f...1"""
l--~OO
.AFt" /~

~~140
Ww
~: 120
C3~

OU~PUT
I

>5 160

9z 100

....LH. ENA8LJ T0 1

~~ A-" J....

~OO==~
-.100

... w

1"- tPHL. ENABLE TO OUTPUT

:1

TA:O: 25°C

...~180

.l=~

I.--- V

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

i

~200

I I I

Cl= 15 pF

~5 160
5~ 140

"'w

/

Y. Thp. 34049 provides six inverting buffers, the 34050 six non-inverting buffers. Their guaranteed fan out into common bipolar logic
elements is shown in Table 1.

34049
LOGIC AND CONNECTION DIAGRAM
DIP (TOP VIEW)

34050
LOGIC AND CONNECTION DIAGRAM
DIP (TOP VIEW)

NOTE,
The Flatpak version has the same
pinouts (Connection Diagram) as the

Dual In-Line Package.

TABLE 1
Guaranteed fan out of 34049, 34050 into common logic families
INPUT PROTECTION
DRIVEN ELEMENT

INPUT 200 II
NOMINAL

GUARANTEED

TO LOGIC

INPUT~

FAN OUT

TRANSISTORS

t"

TO Vss

Standard TTL, OTL

2

9LS, 93L, 74LS

9

74L

NOTE: Typical Breakdown Voltage
of Diode 01 is 20 V.

16

Conditions: VDD

= VCC = 5.0

± 0.25 V

VOL':::;;:0.6V,TA=Ot075°C

DC CHARACTERISTICS: VOO as shown, VSS = 0 V, 34049XM and 34050XM
LIMITS
SYMBOL I PARAM·
ETER

I

VOO - 5 V
MIN

TYP

VOO=10V
MAX

MIN

TYP

VOO=15V

MAX

MIN

TYP

-1.85
-1.25
Output
IOH

UNITS

TEMP

mA

MIN

mA

25°C

VOUT = 2.5 V for VOO = 5 V
Inputs at 0 or VOO

mA

MAX

per Function

-5.2

mA

MIN

V OUT = 9.5 V for VOO = 10 V

-4.7

mA

25°C

V OUT = 14.5 V for VOO = 15 V
Inputs at 0 or VOO
per Function

-2.5

-0.9

HIGH
Current

V OUT = 4.5 V for VOO = 5 V
-0.62
-0.5

-1.85
-1.0

-1.25

-2.5

-0.35

-0.9

-3.5

mA

MAX

3.75

10.0

24.5

mA

MIN

22.0

mA

25°C

VO UT = 0.4 V for VOO = 5 V
V OUT = 0.5 V for V DO = 10 V
V OUT = 0.5 V for V DO = 15 V

16.8

mA

MAX

Inputs at 0 or VOD

3.0
Output
IOl

TEST CONDITIONS

MAX

6.0

8.0

2.1

16.0

5.6

LOW

per Function

Current
3.3
2.6

5.2

1.8

mA

MIN

mA

25°C

Inputs at 0 V or VOO

mA

MAX

per Function

V OUT = 0.4 V for V OD = 4.5 V

Quiescent
100

Power

0.3

0.5

0.1

Supply

20.0

30.0

6.0

MIN,25°C
~A

MAX

Current
NOTE: Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Characteristics.

3·74

All inputs common
and at 0 V or V DO

FAIRCHILD CMOS • 34049 • 34050
TYPICAL ELECTRICAL CHARACTERISTICS

TYPICAL POWER DISSIPATION
VERSUS FREQUENCY

:!:

,

E 1000

II III

~ 100

«
""o

10

ffi

1.0

~

t'66 ='l'~'V
VDD = 10~

l\

Do

i5

10- 1

~

10- 2

>=

iii
Ul

i5

10-3

II:

w

:!: 10-4
~

...~

~" ~V
~~ V

" ~~
V
~r:

V

103

105

10 4

I~JD~J1Y

Cl-15 pF _ _
Cl =50 pF---

;..:

10 2

~
V

III III

INPUT FREQUENCY -

3-75

106
Hz

107

34051
8-CHANNELANALOG MULTIPLEXER/DEMULTIPLEXER
DESCRIPTION - The 34051 is an S-Channel Analog Multiplexer/Demultiplexer with three Address
Inputs (AO-A2), an active LOW Enable Input (E), eight Independent Inputs/Outputs (YO-Y7) and a
Common Input/Output (Z).

LOGIC SYMBOL

The 34051 contains eight bidirectional analog switches, each with one side connected to an Independent Input/Output (YO-Y7) and the other side connected to a Common Input/Output (Z). With the
Enable Input (E) LOW, one of the eight switches is selected (low impedance, ON state) by the three
Address Inputs (AO-A21. With the Enable Input (E) HIGH, all switches are in the high impedance OFF
state, independent of the Address Inputs.
Vaa and VSS are the two supply voltage connections for the digital control inputs (AO-A2, EO). Their
voltage limits are the same as for all other digital CMOS. The analog inputs/outputs (YO-Y7, Z) can
swing between VOO as a positive limit and VEE as a negative limit. VOO-VEE may notexceed 15 V.
For operation as a digital multiplexer/demultiplexer, VEE is connected to VSS (typically ground).

•
•

ANALOG OR DIGITAL MULTIPLEXER/DEMULTIPLEXER
COMMON ENABLE INPUT (ACTIVE LOW)

13 14 15 '12

1

5

2

4

11
10

FUNCTION
Independent Inputs/Outputs
Address Inputs
Enable Input (Active LOW)
Common Input/Output

PIN NAMES
YO-Y7
AO-A2

E
Z

Voo:= Pin 16

TRUTH TABLE
INPUTS
E A2

VSS

CHANNELS

:= Pin 8

VEE=Pin7

Y2- Z Y3- Z Y4- Z Y5- Z Y6-Z

Y7- Z

AI

AO

YO-Z

Yl-Z

L

L

L

L

ON

OFF

OFF

OFF

OFF

OFF

OFF

OFF

L

L

L

H

OFF

ON

OFF

OFF

OFF

OFF

OFF

OFF
OFF

L

L

H

L

OFF

OFF

ON

OFF

OFF

OFF

OFF

L

L

H

H

OFF

OFF

OFF

ON

OFF

OFF

OFF

OFF

L

L

L

OFF

OFF

OFF

OFF

ON

OFF

OFF

OFF

L

H
H

L

H

OFF

OFF

OFF

OFF

OFF

ON

OFF

OFF

L

H

H

L

OFF

OFF

OFF

OFF

OFF

OFF

ON

OFF

L

H

H

H

OFF

OFF

OFF

OFF

OFF

OFF

OFF

ON

H

X

X

X

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

CONNECTION DIAGRAM
DIP (TOP VIEW)

L = LOW Level
H = HIGH Level
X"'" Don't Care

34051 FUNCTIONAL LOGIC DIAGRAM

Y,
0

Y6

0)

16

Y5

Y4

®

Y,

Y3

(2)

@

@

Y,

@

Yo

@

TG

@-

AO

~
~
~E

J

00

A,

0,

A,

0,
03
°4
06
°6-10,-

l

TG

I

TG

TG

I

TG

TG

E

E

E

TG

VDO = Pin 16
"" Pin 8

VEE

=

0=

14

~

13

lI-

12

11
10

0) Z

E

E

~

E

J-

E

~

1-0F·8 DEWDER AND
LEV E L CONVE RTE R

VSS

15

81 DI RECTIONAL
ANALOG SWITCHES

NOTE:
The

Pin 7
Pin Numbers

TG

3-76

E

-~

F latpak version has the same
pinouts (Connection Diagram) as the
Dual I n~Line Package.

FAIRCHILD CMOS • 34051

I

NOTES:
1. Additional DC Characteristics for the Address ann Enable Inputs are listed in this section under 34000 Series CMOS Family Characteristics.
2.

E~.= VSS, R L

3,

V is =8.6VforVDO=15V
Vis'=' 5.1 V for VDO "" 1 0 V
V ls = 1.9 V for VOO = 5 V

4.

V is is the voltage signal at an I nput/Output Terminal (Y n/Zn)'

::0

10 kSl, any channel selected and VSS

=

VEE or V DO / 2 .

3-77

FAIRCHILD CMOS • 34051
AC CHARACTERISTICS AND SET-UP REQUIREMENTS: V DD as shown, VEE ~ 0 V, TA ~ 25°C
LIMITS
SYMBOL

PARAMETER

~-~5V
MIN

TYP

VDD ~ 10 V
MAX

MIN

TYP

MAX

V DD
MIN

~

15 V

TYP

UNITS

TEST CONDITIONS

CL ~ 15 pF, E ~ VSS ~ VEE'
An or Vis ~ V DD or VEE
Note 3

MAX

tpLH
tpHL

Propagation Oelay,
Input to Output

20
B

7
4

4
3

ns
ns

tpLH
tpHL

Propagation Delay,
Address to Output

160
200

90
120

75
90

ns
ns

tpZL
tpZH

Output Enable Time

180
200

90
100

70
80

ns
ns

~L ~

tpLZ
tpHZ

Dutput Disable Time

1000
1000

900
900

860
850

ns

Vis ~ V DD or VEE
Note 3

tpLH
tpHL

Propagation Delay,
Input to Output

25
10

10
6

6
4

ns
ns

~L ~ 50 pF
E ~ VSS ~ VEE'

tpLH
tpHL

Propagation Delay,
Address to 0 utput

170
210

95
125

80
95

ns
ns

An or Vis = VOD or VEE
Note 3

tpZL
tpZH

Output Enable Time

185
205

95
105

75
85

ns
ns

<:L ~ 50 pF
E or An ~ VSS ~ VEE

tpLZ
tpHZ

Output Disable Time

1250
1240

1130
1120

1080
1070

ns
ns

Vis ~ V OD or VEE
Note 3

0.2

0.2

0.2

%

CL

Distortion, Sine
Wave Response

15 pF
E or An ~ VSS ~ VEE

~

15 pF

~L ~ 10k f! ,VSS ~VDD/2

E ~ VEE'
Vis ~ V OD /2 (sine wave)
f is ~ 1 kHz

f MAX

Crosstalk Between
Any Two Channels

1

MHz

RL 1 kf!, E'> VEE
Vis ~ V OD /2 (sine wave)
at -40 dB
VSS ~ V OD /2, 20 Log 10
(V oslV is ) ~ -40 dB

OFF State
Feedthrough

1

MHz

~L ~ 1 k f! ,VSS ~ VOOI2
E ~ V DD
Vis ~ V DD /2 (p-p),
20 L09l 0 (V oslV is ) ~ -40 dB

MHz

RL ~ 1 kr!
Vis ~ V OD /2 (sine wave)
VSS ~ V DO /2
20 L09l 0 (V oslV is ) ~ -3 dB

ON State
Frequency Response

13

40

70

I

NOTES:
1. Propagation Delays and Output Transition Times are graphically described in this section under 34000 Series CMOS Family Characteristics.
2. Vis/Ves is the voltage signal at an Input/Output terminal (Y n/Zn).
3,

V IN = V DD (Square Wave). Input transition times

< 20 ns,

RL

=

10

kn.

3-78

34052
DUAL 4-CHANNEL ANALOG MULTIPLEXER/DEMULTIPLEXER
DESCRIPTION - The 34052 is a Dual 4-Channel Analog Multiplexer/Demultiplexer with common
channel select logic. Each Multiplexer/Demultiplexer has four Independent Inputs/Outputs (YO-Y3)
and a Common Input/Output (Zl. The common channel select logic includes two Address Inputs
(AO, A1) and an active LOW Enable Input (E).

LOGIC SYMBOL

Both multiplexer/demultiplexers contain four bidirectional analog switches, each with one side
connected to an Independent Input/Output (YO-Y3) and the other side connected to a Common
Input/Output (Z). With the Enable Input LOW, one of the four switches is selected (low impedance,
ON state) by the two Address Inputs. With the Enable Input HIGH, all switches are in the high
impedance OFF state, independent of the Address Inputs.
VDD and VSS are the two supply voltage connections for the digital control inputs (AO, A1, El. Their
voltage limits are the same as for all other digital CMOS. The analog inputs/outputs (YO-Y3, Z) can
swing between VDD as a positive limit and VeE as a negative limit. VOD-VEE may not exceed 15 V.
For operation as a digital multiplexer/demultiplexer, VEE is connected to VSS (typically ground).
•
•

12 14

15

11

1

2

4

10
At

34052

DIGITAL OR ANALOG MUL TIPLEXER/DEMUL TIPLEXER
COMMON ENABLE INPUT (ACTIVE LOW)

PIN NAMES
YOa-Y3a
YOb-Y 3b
AO,A1

E
Za,Zb

FUNCTION
Independent Inputs/Outputs
I ndependent Inputs/Outputs
Address Inputs
Enable Input (Active LOW)
Common Input/Output

13

\tDO = Pin 16

TRUTH TABLE
INPUTS

VSS

= Pin 8

VEE

=

Pin 7

CHANNELS

E

A1

AO

Y1-Z

Y2-Z

L

L

L

ON

OFF

OFF

OFF

L

L

H

OFF

ON

OFF

OFF

L

H

L

OFF

OFF

ON

OFF

L

H

H

OFF

OFF

OFF

ON

H

X

X

OFF

OFF

OFF

OFF

YO-Z

Y3-Z

CONNECTION DIAGRAM
DIP (TOP VIEW)

L"" LOW Level, H = HIGH Level, X = Don't care.

34052 FUNCTIONAL LOGIC DIAGRAM

4

5

2
Y3.

Y2.

1
Y, •

11
Yo.

15
Y3b

14
Y2b

Y,b

12
YOb

BIDIRECTIONAL
ANALOG SWITCHES
TG

®--

AO

00

®-

A,

0,

®-c

E

0,

~TG
LTG

TG

E

E

E

E

03
TG

1-0F-4 DECODER
AND LEVEL CONVERTER

TG

TG

E

E

E

VOO = Pin 16

VSS = Pin 8
V EE = Pin 7

o

TG

E

16

JJ- ~

15
14

13

JlII-~
lI-

12
11

10

NOTE:

The

= Pin Number

Flatpak version has the same

pinouts (Connection Diagram) as the

Dual In-Line Package.

3-79

I

FAIRCHILD CMOS • 34052
DC CHARACTERISTICS: VDD as shown, VEE = 0 V
LIMITS
PARAMETER

SYMBOL

V DD - 5 V
MIN

TYP

VD D
MAX

RON

ON
Resistance

XM

=10V

TYP

V DD -15V

MAX

MIN

TYP
35

125

55
65
100

95
100
125

55
65
100

35
40

1600

110
125

55

95
100

XC

MIN

40
65

TEST CONDITIONS

UNITS

TEMP

n

25°C
MAX

12

25°C
MAX

n

25°C
MAX

Note 3

MIN

n

25°C
MAX

Vis =VDD
Note 2

n

25°C
MAX

MAX
Vis =V DD
Note 2

MIN

Vis =VEE
Note 2

MIN

65

MIN

1000
850

200

60
95

90
100
150

50
65
110

30
40
70

90
100

30
40

150

50
65
110

1750
1000

100
125

n

220

25°C
MAX

Note 3

700

50
60
100

10

5

n

25°C

Note 2

Vis =VEE
Note 2

MIN

70

•

MIN

"

!iRON

"ON Resistanee Between Any
Two Channels
OFF State
XC
Leakage
Current, All
Channels OF F XM

IZ

Any
Channel
OFF

IDO

Quiescent
Power
Supply
Dissipation

80
nA

XC
XM

XC
XM

E=V DD ,
VSS =VO DI2
Vis =VD D or VEE

800

25°C

E = VSS =VOO/2

100
10
20
700
2
70

40
1400

4
140

Vis

8
2801
0,8
28

~A
~A

MIN,25°C
MAX
MIN,25°C
MAX

=V DD or VEE

VSS =VEE
All Inputs Common
and at 0 V or VDD

NOTES:
1, Additional DC Characteristics for the Address and Enable 1nputs are listed in this section under 34000 Series CMOS Family Characteristics.
2. E = VSS. RL "" 10 kil, any channel selected and VSS "" VEE or VOD/2.
3. V
V
V

4. V

= 8.6V for VDD = 15V
=5.1VforVDD=10V
= 1.9V for VDO

= 5V

is the voltage signal at an Input/Output Terminal (Y n/Zn).

3-80

FAIRCHILD CMOS • 34052
AC CHARACTERISTICS AND SET-UP REQUIREMENTS: V DD as shown, VEE = 0 V, TA = 25°C
LIMITS
PARAMETER

SYMBOL

V DD = 5 V
MIN

TYP

V DD =10V
MAX

MIN

TYP

MAX

V DD = 15 V
MIN

TYP

UNITS

TEST CONDITIONS

CL = 15 pF, E = VSS = VEE'
An or Vis = V DD or VEE
Note 3

MAX

tpLH
tpHL

Propagation Delay,
Input to Output

20
8

7
4

4
3

ns
ns

tpLH
tpHL

Propagation Delay,
Address to Output

160
200

90
120

75
90

ns
ns

tpZL
tpZH

Output Enable Time

180
200

90
100

70
80

ns
ns

~L = 15 pF

tpLZ
tpHZ

Output Disable Time

1000
1000

900
900

860
850

ns

Vis = V DD or VEE
Note 3

tpLH
tpHL

Propagation Delay,
Input to Output

25
10

10
6

6
4

ns
ns

~L = 50 pF
E = VSS = VEE'

tpLH
tpHL

Propagation Delay,
Address to Output

170
210

95
125

80
95

ns
ns

An or Vis = V DD or VEE
Note 3

tpZL
tpZH

Output Enable Time

185
205

95
105

75
85

ns
ns

~L = 50 pF
E or An = V SS = VEE

tpLZ
tpHZ

Output Disable Time

1250
1240

1130
1120

1080
1070

ns
ns

Vis = V DD or VEE
Note 3

0.2

0.2

0.2

%

CL = 15 pF

Distortion, Sine
Wave Response

E or An = V SS = VEE

~L=10kn ,VSS = V DD I2

E = VEE'
Vis = V DD I2 (sine wave)
lis = 1 kHz

-

Crosstalk Between
Any Two Channels

1

MHz

RL = 1 k n , E = VEE
Vis = V DD /2 (sine wave)
at -40 dB
VSS = VDD12, 20 LoglO
(Vos/V is ) = -40 dB

OFF State
Feedthrough

1

MHz

~L = 1 k n , VSS = VD DI2
E = V DD
Vis = VDD12 (sine wave)
20 Log 10 (Vos/V is ) = -40 dB

MHz

RL = 1 kn . E = VSS
Vis = V DD I2 (sine wave)
VSS = V DD I2
20 Log lO (VDslVis) = -3 dB

ON State
Frequency Response

f MAX

13

40

I

70

NOTES:
1.

Propagation Delays and Output Transition Times are graphically described in this section under 34000 Series CMOS Family Characteristics.

2. Vis/Vas is the voltage signal at an Input/Output Terminal (V n/Zn).
3.

VI N

=

VOD (Square Wave), Input Transition Times <20 ns and R L = 10 Ul.

3-81

-

34066
QUAD BILATERAL SWITCHES

DESCRIPTION - The 34066 has four independent bilateral analog switches (transmission gates). Each
switch has two Input/Output Terminals (Y n • Zn) and an active HIGH Enable Input (En). A HIGH on
the Enable Input establishes a low impedance bidirectional path between Y nand Zn (ON condition)'
A LOW on the Enable Input disables the switch; high impedance between Y nand Zn (OFF condition),

•
•

LOGIC SYMBOL

DIGITAL OR ANALOG SIGNAL SWITCHING
INDIVIDUAL ENABLE INPUTS (ACTIVE HIGH)

PIN NAMES

EO - E3
YO-Y3
ZO- Z3

Voo "" Pin 14
VSS = Pin 7

Enable Inputs
Input/Output Termin,als
Input/Output Terminals

o

LOGIC DIAGRAM (1/4 OF A 34066)

= Pin Numbers

CONNECTION DIAGRAM
DIP (TOP VIEW)

y"----------;-------~~-----,
14

13
12
11

10

Note: The Flatpak version has the
same pinouts (Connection Diagram)

as the Dual In-Line Package.

3-82

FAIRCHILD CMOS • 34066

DC CHARACTERISTICS: V DD as shown, VSS ~ 0 V
LIMITS
SYMBOL

PARAMETER

VDD ~ 5 V
MIN

RON

ON
XC

Resistance

XM

TYP

VDD~15V

VDD~10V

MAX

MIN

TYP

MAX

MIN

TYP

MAX

190

900

100

450

80

270

1000

120

500

80

250
280

330

1090

170

520

130

300

160

850

85

400

60

220

270

1000
1150

120
190

500
550

80
145

280

360

UNITS

TEMP

MIN

RL~10kn

n

25°C
MAX

En ~ VDD'
Vis ~ V DD to VSS

MIN

RL

n

25°C
MAX

En ~ VD D'
Vis ~ V DD to VSS

n

25°C

320

"6. " ON Resist6. RON

10

5

OFF State Leak-

100

100

age Current,
Any Y to Z

200

200

Quiescent

IDD

Power
Supply
Current

XC
XM

~

10kn

Vis ~ V DD to VS S'

ance Between Any
Two Switches

IZ

TEST CONDITIONS

0.25
25

0.5
30

0.1
6

0.25

0.5

25

30

0.1
6

En

~ VDD

RL

~

10kn

Vis ~ VDD or VSS'

nA

MIN,25°C
MAX

~A

MIN,25°C
MAX

All inputs common

MIN,25°C

and at V DD or VSS

~A

En ~ VSS

MAX

NOTES: 1. Additional DC Characteristics for the Enable I nputs are listed in this section under 34000 Series CMOS Family Characteristics.
2. Vis is the input voltage to Input/Output Terminal (Y n/Zn).

3-83

FAIRCHILD CMOS • 34066
AC CHARACTERISTICS AND SET-UP REQUIREMENTS: V DD as shown, VSS = 0 V, TA = 25°C
LIMITS
SYMBOL

PARAMETER

V DD = 5 V
MIN

TYP

V DD = 10V
MAX

MIN

TYP

MAX

VDD = 15 V
MIN

TYP

UNITS

TEST CONDITIONS

MAX

tpLH
tpHL

Propagation Delay,
Y n to Zn or Zn to Y n

4
3

1.5
1.5

1
1

ns

CL = 15pF, RL = 10kn
Input Transition Times'; 20 ns
En = V DD
Vis = V DD (square wave)

tpZL

Output Enable Time

24
24

14
14

10
10

ns
ns

CL = 15 pF, RL = 300n
(square wave)
E =V
n
DD

tpLZ
tpHZ

Output Disable Time

160
160

170
170

182
182

ns
ns

Input Transition Times.; 20 ns
Vis =V DD

tpLH
tpHL

Propagation Delay,
Y n to Zn or Zn to Y n

8
8

3
4

2
2.5

ns
ns

CL = 50 pF, RL = 10 kn
Input Transition Times.; 20 ns
En = V DD
Vis = V DD (square wave)

tpZL

Output Enable Time

32
32

16
16

13
13

ns
ns

CL = 50 pF, RL = 300n
(square wave)
E ~V
n
DD

Output Disable Time

380
380

380
380

400
400

ns
ns

Input Transition Times.; 20 ns
Vis =V DD

0.31

0.31

0.31

%

CL ~ 15 pF, RL = 10kn
Input Frequency ~ 1 kHz
En = VDD
Vis = V DD !2 (sine wave)

tpZH

tpZH
tpLZ
tpHZ

Distortion, Sine
Wave Response

Crosstalk Between
Any Two Switches

0.9

MHz

Crosstalk, Enable
Input to Output

50

mV

1.25

MHz

ON State
Frequency Response

90

MHz

Enable Input
Frequency (Note 2)

10

MHz

OFF State
Feedthrough

f MAX

RL ~ 1 kn
EA = V DD , EB = VSS
Vis = V DD /2 (sine wave)
at -50 dB, 20 Log 10
[Vos (B)lV is (A)] = -50 dB
Input Transition Times.; 20 ns
RL(OUT) = 10 kn ,RL(IN) = 1 kn
En = V DD (square wave)
RL = 1 kn
En ~ V SS '
Vis ~ V DD !2(sine wave)
20 Log 10 (V os/V is) = -50 dB

RL = 1 kn
Vis = V DD !2 (sine wave)
En = V DD ,
20 Log 10 (Vas/Vis) ~ -3 dB
CL =15pF,R L =1 kn
Input Transition Times.; 20 ns
En = V DD (square wave)
Vis ~ V DD

NOTES:
1, Propagation Delays and Output Transition Times are graphically described in this section under 34000 Series CMOS Family Characteristics.
2, For f MAX , input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.
3, Vis/Vas is the voltage signal at an I nput/Output Terminal (Y n/Zn).

3-84

FAIRCHILD CMOS • 34068
a-INPUT NAND GATE

DESCRIPTION - This CMOS logic element provides the positive 8-lnput NAND function. The outputs are fully buffered for highest noise
immunity and pattern insensitivity of output impedance.

34068 LOGIC SYMBOL

CONNECTION DIAGRAM
DIP (TOP VIEW)

~,--

0-'2.

1 [NC

0~

0~

®2

®~
@)~
®~

~(

@

Z

VOD

P

14

Z P13

iJ

Voo = Pin 14

3 [ I,

17

Vss

= Pin 7

4 [ 12

16Ull

NC

= Pins 1, 6, 8
6

c:

7

C VSS

NC

14

NC

NOTE:
The F latpak version

NAND Gate Inputs
Output (Active LOW)

12

I

15U'O
iJ

5[13

@...2

PIN NAMES
10- 17

-

2 [ 10

9

;::J

8

has the same

pinouts (Connection Diagram) as the

Dual I n-Line Package.

=0 V

DC CHARACTERISTICS: VDD as shown. VSS

LIMITS
SYMBOL

PARAMETER

V DD
MIN

Quiescent
Power

IDD

Supply
Current

=5 V

TYP

XC
XM

V DD
MAX

MIN

= 10 V

TYP

V DD
MIN

MAX

= 15 V

TYP

0.5

5.0

1.0

15.0

30.0

6.0

0.05

0.1

0.02

3.0

6.0

1.2

UNITS

TEMP

TEST CONDITIONS

MAX

IlA
~A

MIN,25°C
MAX
MIN,25°C

All inputs common
and at 0 V or VDD

MAX

NOTE: Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Characteristics.

AC CHARACTERISTICS: V DD as shown, VSS

=0 V,

TA

=25°C
LIMITS

SYMBOL

PARAMETER

MIN
tpLH

Propagation Delay

tpHL

VD D -10V

VDD - 5 V
TYP

MAX

MIN

TYP

MAX

V DD - 15 V
MIN

TYP

UNITS

TEST CONDITIONS

MAX

65

30

22

ns

70

32

22

ns

CL

Input Transition Times .. 20 ns

= 15 pF

tTLH

Output Transition

25

13

10

ns

tTHL

Time

25

10

8

ns

tpLH

Propagation Delay

82

40

29

ns

88

40

28

ns

CL

tTLH

Output Transition

64

32

24

ns

Input Transition Times .. 20 ns

tTHL

Time

55

23 I

16

ns

tpHL

= 50 pF

NOTE:

Propagation delays and output transition times are graphically described in this section under 34000 Series CMOS Family Characteristics.

3-85

FAIRCHILD CMOS • 34069

HEX INVERTER

DESCRIPTION - The 34069 is a general purpose Hex Inverter which has standard Fairchild input and output characteristics. A single-stage

design has been used since the output impedance of a single-input gate is not pattern sensitive.

LOGIC AND CONNECTION DIAGRAM
DIP (TOP VIEW)

NOTE:
The F latpak version has the same pinouts
(Connection Diagram) as the Dual In-Line
Package.

DC CHARACTERISTICS: VOO as shown, VSS ~ 0 V
LIMITS
SYMBOL

PARAMETER

MIN
Quiescent
Power
100

Supply
Current

VOO~10V

VOO ~ 5 V
TYP

XC
XM

MAX

MIN

VOO-15V

MAX

TYP

MIN

TYP

3.0

5.0

1.0

42.0

70.0

14.0

0.3

0.5

0.1

20.0

30.0

6.0

TEST CONDITIONS

TEMP

UNITS

MAX
~A

~A

MIN,25°C
MAX

All inputs common

MIN,25°C

and at 0 V or V DO

MAX

NOTE: Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Characteristics.

AC CHARACTERISTICS: VOO as shown, VSS ~ 0 V, TA

=25°C
LIMITS

SYMBOL

PARAMETER

VOO ~ 5 V
MIN

tpLH

Propagation Delay

tpHL

VOO ~ 15 V

VOO ~ 10V

TYP

MAX

20
20

MIN

MIN

TYP

UNITS

TEST CONDITIONS

MAX

TYP

MAX

36

10

20

7

ns

36

10

20

7

ns

CL

Input Transition Times";; 20 ns

=15pF

tTLH

Output Transition

20

45

12

25

11

20

ns

tTHL

Time

20

45

12

25

11

20

ns

tpLH

Propagation Delay

32

64

16

32

13

ns

32

64

16

3.2

13

ns

CL

Input Transition Times:O; 20 ns

tpHL
tTLH

Output Transition

45

135

23

70

18

45

ns

tTHL

Time

45

135

23

70

18

45

ns

~

50 pF

NOTE:
Propagation Delays and Output Transition Times are graphically described in this section under 34000 Series CMOS Family Characteristics.

1.

3-86

FAIRCHILD CMOS· 34069
TYPICAL ELECTRICAL CHARACTERISTICS

E 1000
I

w

Cl

100

U

10

~

:

..IE
Z

o

~

'III I I

VDD -15 V
liOD" 10\1

~

:~ ~"

--' "';:.:-, ,
"-:::"

'~-"

~:::"

",

".

a:
w

>-

:5w
o
Z
o

~

Cl

:o

..

VDD

=5 V

104

105

20

0

~

15

Cl

10 tPHLVDD-l0V

..
a:

-

tpHL VOO =5 V
1--1--~rVOO - ::..:-1 tPLH VDD -10V

r:~

'.Ii

I

1

tPLH VDD" 15 V
5

I\P~L ~Dri = ,15 V

o

-60

107

106

0
Z

0

CL" 15 pFCL =50 pF-----103

25

:

l JI

III

15 10- 3

I

".

"

,,-

~ 10-~02

I

CL~l~PF

30

>-

:5w

V

",

,

", "

c

--~
--- --- --

.... J~'-

::::., 'VV'

.

--

III I

10-1

III

35

T~llI2~od

1.0

ii.i 10- 2

~

PROPAGATION DELAY
VERSUS TEMPERATURE

POWER DISSIPATION
VERSUS FREQUENCY

~

-20

i

I II

20

60

100

TA - AMBIENT TEMPERATURE - °C

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

OUTPUT TRANSITION TIME
VERSUS LOAD CAPACITANCE

120~1--r~--+-~-+--~1--r~
100r-~-r~--+--r-+--r-~-r.79
80r-~-r~--+--r-+

60

140

INPUT FREQUENCY - Hz

r-+--+--+--I-

40 1-+--+-7is..-'f'-

a:

CL - LOAD CAPACITANCE - pF

CL - LOAD CAPACITANCE - pF

TYPICAL VOLTAGE TRANSFER
CHARACTERISTICS FOR THE
UNBUFFERED 34069
HEX INVERTER

>
I

15

w
Cl

«
...

-'
0

>

........

10

~

...........

\
"
"\

~

0

...I

5.0

~

0

>

o
o

\..
5.0

\"
10

15

VIN - INPUT VOLTAGE - V

3-87

FAIRCHILD CMOS • 34070
QUAD EXCLUSIVE-OR GATE

DESCRIPTION - The 34070 CMOS logic element provides the Exclusive-OR function. The outputs are fully buffered for best performance.
LOGIC AND CONNECTION DIAGRAM
DIP (TOP VIEW)

NOTE:
The Flatpak version has the same pinout

(Connection Diagram) as the Dual In-Line
Package.

x=

AS + AS

DC CHARACTERISTICS: VOO as shown, VSS = 0 V
LIMITS
SYMBOL

PARAMETER

MIN
Quiescent

Power
IDD

Supply
Current

VOO = 10V

VOO = 5 V
TYP

XC
XM

MAX

MIN

TYP

VOO=15V

MAX

MIN

5.0

10.0

2.0

70.0

140.0

18.0

0.5

1.0

0.2

30.0

60.0

12.0

TEMP

UNITS

TEST CONDITIO NS

MAX

TYP

~A

MIN,25°C

All inputs common

MAX

and at 0 V or V DD

MIN,25°C

~A

MAX

NOTE: Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Characteristics.

AC CHARACTERISTICS: VOO as shown, VSS = 0 V, TA = 25°C
LIMITS
SYMBOL

V OD = 5 V

PARAMETER

MIN

VOO=10V

TYP

MAX

MIN

VOO=15V

TYP

MAX

MIN

TYP

UNITS

TEST CONOITIONS

MAX

tpLH

Propagation Oelay,

65

130

33

65

23

ns

tpHL

A or B to X

65

130

33

65

23

ns

CL = 15 pF

tTLH

Output Transition

23

45

10

25

8

20

ns

Input Transition Times';; 20 ns

tTHL

Time

23

45

10

25

8

20

ns

tpLH

Propagation Delay,

85

170

45

90

27

ns

tpHL

A or B taX

85

170

45

90

27

ns

CL = 50 pF

tTLH

Output Transition

50

100

23

50

17

35

ns

Input Transition Times';; 20 ns

tTHL

Time

50

100

23

50

17

35

ns

NOTE: Propagation delays and output transition times are graphically described in this section under 34000 Series CMOS Family Characteristics.

TYPICAL ELECTRICAL CHARACTERISTICS

'DO
;

90

~

80

z
o

~
;t

C!J

o

Hl.

Cl= 15 pF

50

C~oo-"'::-' e=-1-"""--

40

;l
o

30

20

---

I

Voo - ,sVi

-1

0

~

l?60-40-20 0

I
TA -

2040 6080100120140

AMBIENT TEMPERATURE -

~-88

TA '" 25°C

120

~ 100
'"

~
;t

80

~

60

°C

<
o
0:
/:
I

~
,/

I

I
i

_,o'i

"00-

40

20

I

1)/V

o

a.

Voo:= 10 V

/:

140

~

I

O

60

:::

0:

INPUT FREQUENCY -

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

PROPAGATION DELAY
VERSUS TEMPERATURE

POWER DISSIPATION
VERSUS FREQUENCY

~

~

t:: ~

IT

~ m ~ ~ OO'M'm'~'~
CL -

LOAD CAPACITANCE -- pF

FAIRCHILD CMOS • 34071
QUAD 2-INPUT OR GATE

DESCRIPTION - The 34071 is a positive logic Quad 2-lnput OR Gate. The outputs are fully buffered for highest noise immunity and pattern
insensitivity of output impedance.

NOTE:
The F latpak version has the same
pinouts (Connection Diagram) as the
Dual In-Line Package.

LOGIC AND CONNECTION DIAGRAM
DIP (TOP VIEW)

DC CHARACTERISTICS: V DD as shown, VSS = 0 V
LIMITS
SYMBOL

PARAMETER

V DD - 5 V
MIN

Quiescent
Power
Supply
Current

IDD

NOTE:

TYP

VDD -lOV
MAX

MIN

TYP

MAX

0.5
15.0
0.05
3.0

XC
XM

VDD - 15 V
MIN

UNITS

TEMP

5.0
30.0
0.1
6.0

TEST CONDITIONS

1.0
6.0

~A

MIN,25°C
MAX

0.02
1.2

~A

MIN,25°C
MAX

MAX

TYP

All inputs common
and at 0 V or VDD

Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Characteristics.

AC CHARACTERISTICS: VDD as shown, VSS = 0 V, TA = 25°C

SYMBOL

LIMITS
VDD =10V

V DD = 5 V

PARAMETER

MIN

TYP

15
14

30
30

11
11

19
24

75
75

10
10

40
40

8
7

43
52

85
100

22

40
40

17

ns

23

15

ns

CL = 50 pF

ns

Input Transition Times .. 20 ns

tpLH
tpHL

Propagation Delay

tTLH
tTHL

Output Transition

tpLH
tpHL

Propagation Delay

tTLH

Output Transition

45

135

24

70

18

tTHL

Time

54

135

21

70

15

Time

TEST CONDITIONS

60
60

30
35

MIN

UNITS

MAX

MAX

MIN

VDD =15V

TYP

TYP

MAX
ns
ns
25
25

45
45

CL = 15 pF
Input Transition Times .. 20 ns

ns
ns

ns

NOTE:
1. Propagation Delays and Output Transition Times are graphically described in this section under 34000 Series CMOS Family Characteristics.

TYPICAL ELECTRICAL CHARACTERISTICS
~1000rTTIT-rTnrT-nTr"Trr-rTTI"

140

80
Cl=15pF

I

70

w

"~
f

~o

60

120
100~+~--~-~---~

50

~

40

j::

30

13'0- 1 H+!i-bffi9<;[.-!J,P.i· "t1'ii"--t--Tt'tH
-: 1 0- 2 H~;¥.:ru+-"-tii+-t-t*++++H

iii

B10-3 f..f':Plf+tttH--H+t'w" 10-4 '-;:"-W.-,"-:;'-'"'-'--;'-'''--L"-=,-'.ll-'-;:'-'-''--' 7
~

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

PROPAGATION DELAY
VERSUS TEMPERATURE

POWER DISSIPATION
VERSUS FREQUENCY

102

106
INPUT FREQUENCY - Hz

10

VDD~5"
-

tPL~l

1---

20

tPLH. tpHL

10
t;PLHj

o

-60

-40

-20

I

r--

J=J

VOO

10 V f- f--

lor 'rl- c--

tP~L
20

t:::;

40

60

80

100

140
120

TA - AMBIENT TEMPERATURE - °C

3-89

OL-~-L

o

20

__L-J-~__L-J--J

40

60

80 100 120140 160

CL -LOAD CAPACITANCE - pF

FAIRCHILD CMOS. 34077
QUAD EXCLUSIVE-NOR GATE

DESCRIPTION - The 34077 CMOS logic element provides the Exclusive-NOR function. The outputs are fully buffered for best performance.
The 34077 may be used interchangeably for the 4811.
LOGIC AND CONNECTION DIAGRAM
DIP (TOP VIEW)

"

"

Voo

"

"

"

"

RRRRGl[71[7l

La~

lSoJ

NOTE:
The F latpak version has the same pinouts
(Connection Diagram) as the Dual In-Line
Package.

Ia~ ra$l

~~~~~~~
AS + AS

X ~

DC CHARACTERISTICS: VDD as shown, VSS = 0 V
LIMITS
SYMBOL

V DD = 5 V

PARAMETER

MIN
Quiescent

MAX

XC

Power

IDD

TYP

Supply

XM

Current

V DD = 10V
MIN

TYP

V DD = 15 V
MIN

MAX

TYP

UNITS

TEMP

TEST CONDITIONS

MAX

5.0

10.0

2.0

70.0

140.0

28.0

0.5

1.0

0.2

30.0

60.0

12.0

~A

MIN,25°C

All inputs common

MAX

and at 0 Vor VDD

MIN,25°C

~A

MAX

NOTE: Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Characteristics.

AC CHARACTERISTICS: V DD as shown, VSS = 0 V, TA = 25°C
LIMITS
V DD = 10V

V DD = 5 V

PARAMETER

SYMBOL

MIN

TYP

MIN

MAX

V DD = 15 V

TYP

MAX

MIN

TYP

TEST CONDITIONS

UNITS

MAX

Propagation Delay,

45

90

20

40

15

ns

A or B toX

55

110

20

40

17

ns

CL = 15 pF

tTLH

Output Transition

23

45

10

25

7

20

ns

Input Transition Times.:; 20 ns

tTHL

Time

23

45

10

25

7

20

ns

tpLH

Propagation Delay,

55

110

27

55

17

ns

tpHL

A or B toX

65

130

27

55

20

ns

CL = 50 pF

tTLH

Output Transition

53

100

20

50

15

35

ns

Input Transition Times':; 20 ns

tTHL

Time

53

100

20

50

15

35

ns

ipLH
tpHL

NOTE: Propagation delays and output transition times are graphically described in this section under 34000 Series CMOS Family Characteristics.

TYPICAL ELECTRICAL CHARACTERISTICS
POWER DISSIPATION
VERSUS FREQUENCY

s:E 1000

J IllJ

TA-2S o C

I

~

'00

1111 LI

I

~llliLi VDD='~V
~

'0

~

'.0

z
2:
~

10-1

!!:: 10-2

ill

l'I'

s:fZ '0-4102

/

VOO'=5V

I Ii II
103

'00

0

I

I,

,I

a:

I ill II I

l~l='5PFCl=50pF __
'OS

..""'"
.
0

I

'0·

INPUT FREQUENCY - Hz

~

0

;::

~

,

I
>

z

"

~

~ 10-3~

w
a:

/

~

:', ,~
~:;.-

~
/

/

VOD:: 1S'V i

PROPAGATION DELAY
VERSUS TEMPERATURE

~

'07

~

""~
I

~

~

100 CL"'15pF

90
80
70
60
50
40
30
20
'0
0

I~oo=~:' f:::;

;-

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE
I '40
TA '" 25°C
>
c

~

'20

I.~,J"/,, V

0

z
0 '00

;JY'

;::

V"""

'"~"

V

Voo -15V

60

;i

40

"0:~

-

80

0

IE

Voo '" 10 V

1-

.

20

V
~oo='O" _ -

I--

-::: ~

I

~

-60-40-20

o

20 40 60 80100120140

TA - AMBIENT TEMPERATURE __

3-90

°c

l:

l!-

00
20 40 60

T

80 100 120140 160

CL - LOAD CAPACITANCE -

pF

FAIRCHILD CMOS • 34078
8-INPUT NOR GATE

DESCRIPTION - This CMOS logic element provides the positive 8-lnput NOR function. The outputs are fully buffered for highest noise
immunity and pattern insensitivity of output impedance.

34078 LOGIC SYMBOL

CONNECTION DIAGRAM
DIP (TOP VIEW)

lC~P14
01o~

0 "

1

2

34078

Z

®'4~ ~

3

Voo = Pin 14
VSS = Pin 7

@

@16~

NC

@'7-

= Pins 1, 6, 8

PIN NAMES
NOR Gate Inputs
10-17
Z
Output (Active LOW)

OC CHARACTERISTICS: VOO as shown, VSS

Z~13

C 10
C I,

17 pt2

4 [

I,

16 J11

s[

13

15 J10

6 [

NC

14

7[

V55

NC

J
J

9

8

NOTE:
The F latpak version has the same
pinouts (Connection Diagram) as the
Dual In~Line Package.

=0 V
LIMITS

SYMBOL

PARAMETER

VOO
MIN

100

Quiescent
Power
Supply
Current

=5 V

TYP

VOO
MAX

MIN

=10 V

TYP

MAX

0.5
15.0

XC

=15 V

TYP

UNITS

TEMP

TEST CONOITIONS

MAX

5.0
30.0

1.0
6.0

~A

MIN,25°C
MAX

0.1
6.0

0.02
1.2

I'A

MIN,25°C
MAX

0.05
3.0

XM

VOO
MIN

All inputs common
and at 0 V or VOD

NOTE: Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Characteristics.

AC CHARACTERISTICS: VOO as shown, VSS

=0 V, TA =25°C
LIMITS

SYMBOL

PARAMETER

VOO
MIN

tpLH
tpHL

Propagation Oelay

tTLH
tTHL
tpLH

TYP

VOO
MAX

MIN

=10V

TYP

87
102

36

Output Transition
Time

35

20

37

Propagation Oelay

tpHL
tTLH
tTHL

=5 V

Output Transition
Time

MAX

VOO - 15 V
MIN

TYP

UNITS

TEST CONOITIONS

MAX

27
29

ns
ns

CL

16
15

ns

Input Transition Times" 20 ns

17

108
129

46

34

50

35

ns
ns

76
80

39
32

30
24

ns
ns

40

=15 pF

ns

CL

=50 pF

Input Transition Times "20ns

NOTE:
Propagation delays and output transition times are graphically described in this section under 34000 Series CMOS Family Characteristics.

3-91

FAIRCHILD CMOS • 34081
QUAD 2-INPUT AND GATE
DESCRIPTION - The 34081 is a positive logic Quad 2-lnput AND Gate. The outputs are fully buffered for highest noise immunity and pattern
insensitivity of output impedance.
LOGIC AND CONNECTION DIAGRAM
DIP ( TOP VIEW)

NOTE:
The F latpak version has the same
pinouts (Connection Diagram) as the
Dual In~Line Package.

DC CHARACTERISTICS: VDD as shown, VSS = a V

SYMBOL

PARAMETER

MIN
Quiescent
Power
Supply

100

Current

LIMITS
VDD =10V

V DD = 5 V
MAX

TYP

MIN

TYP

0.5
15.0
0.05

XC
XM

V DD = 15 V

MAX

MIN

UNITS

TEMP

~A

MIN,25°C
MAX

6.0
0.02
1.2

6.0

TEST CONDITIONS

MAX

1.0

5.0
30.0
0.1

3.0

TYP

All inputs common
and at V or V DD

a

MIN,25°C

~

MAX

NOTE: Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Characteristics.

AC CHARACTERISTICS: VDD as shown, VSS =

SYMBOL

I'y1IN
Propagation Delay

tn.H
tTHL

Output Transition
Time

tpLH

Propagation Delay

TYP

MAX

35
35

tpHL
tTLH

Output Transition

tTHL

Time

LIMITS
VDD = 10V

V DD = 5V

PARAMETER

tpLH
tpHL

a V, TA = 25°C
VDD = 15V

UNITS

TEST CONDITIONS

TYP

MAX

60
60

16
18

33

27
25

75
75

13
10

40
40

10

55
60

95
95

23
25

50
50

17

ns

19

ns

CL = 50 pF

135
135

30
23

70

23
16

ns
ns

Input Transition Times"; 20 ns

70
57

MIN

MIN

TYP

33

MAX

11
13

7

70

ns
ns
25
25

45
45

ns
ns

CL = 15pF
Input Transition Times"; 20 ns

NOTE:

1.

Propagation Delays and Output Transition Times are graphically described in this section under 34000 Series CMOS Family Characteristics.

TYPICAL ELECTRICAL CHARACTERISTICS
POWER DISSIPATION
VERSUS FREQUENCY
~'OOOrTnr~~'-nTrr~~-n~

I
I I I

~

a:
~

40

,0~Hr~+#4=~f+~~~~

>

, .0~ttt-=t\lrttt-ttJ;f.~,*I!fI-tl-tH

Q

~,o-'~Hr~~~~P+~~~1t1
>=
~ ,o-2b1il!ffi>i7lM+tftf-t--ttIH-tt-tH

illo , 0-3WIoIf't-t+++-t-ttlt-

~

.."'"
a:

'10

~ 1 o-~O'-:2:"-"J....J.-:f-L",-'-:-'-Lll.,.l..0-:f5.llI.,-'o-=al.J..U....J,0 7
INPUT FREQUENCY -

Z
0

0

a:

Q..

5w

Hz

- -JDDI~.lv

......r-

30

./

20 ~ '0

o

'40

CL~,.pFI

I '00 H-fH-H-I*-II-+lH

~

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

PROPAGATION DELAY
VERSUS TEMPERATURE
50

-

I .....

-60

VJD~'OV

- - -I-f
vr o ;

-20

20

60

.....
'51v r-100

140

TA - AMBIENT TEMPERATURE - °C

3-92

CL - LOAD CAPACITANCE - pF

FAIRCHILD CMOS • 34085

-------------------------------------------------------------------------------------,
DUAL 2-WIDE 2-INPUT AND-OR-INVERT GATE

DESCRIPTION - The 340S5 is a Dual 2-Wide 2-lnput AND-OR-Invert (AOI) Gate, each with an additional input (l4A or 14S) which can be
used as either an Expander Input or an Inhibit Input by connecting it to any standard CMOS output. A HIGH on this Input (14) forces the
Output (F) LOW independent of the other four inputs (10-13). The Outputs
and FS) are fully buffered for highest noise immunity and
pattern insensitivity of output impedance.

(FA

PIN NAMES
IOA- 14A,IOs-14S

Gate Inputs
Outputs (Active LOW)

FA, FS

CONNECTION DIAGRAM
DIP (TOP VI EW)
LOGIC DIAGRAM

VDD

~

VSS

= Pin

Pin 14
7
NOTE:

The F latpak version has the same
pinouts (Connection Diagram) as the
Dual In~Line Package

DC CHARACTERISTICS: V DD as shown. VSS = 0 V

SYMBOL

PARAMETER

MIN
Quiescent
Power
Supply
Current
NOTE:

LIMITS
V DD =10V

V DD = 5 V
TYP

MAX

MIN

TYP

0.5

XC

TYP

30.0
0.1

6.0
0.02
1.2

6.0

UNITS

TEMP

TEST CONDITIONS

~A

MIN,25°C
MAX

~A

MIN,25°C
MAX

MAX

1.0

5.0

15.0
0.05
3.0

XM

V DD = 15 V
MIN

MAX

All inputs common
and at 0 V or V DD

Additional DC Characteristics are listed in this'section under 34000 Series CMOS Family Characteristics.

AC CHARACTERISTICS: V DD as shown, VSS = 0 V, TA = 25°C
LIMITS
SYMBOL

PARAMETER

V DD -l0V

VD D - 5 V
MIN

TYP

MAX

MIN

V DD = 15V

TYP

MAX

MIN

TYP

UNITS

TEST CONDITIONS

MAX

tpLH

Propagation Delay,

40

SO

lB

40

tpHL

AnyltoF

54

100

2B

50

12
15

ns

CL = 15 pF

tTLH

Output Transition

20

45

12

25

10

20

ns

Input Transition Times <20 ns

tTHL

Time

20

45

12

25

10

20

ns

ns

tpLH

Propagation Delay,

56

115

25

55

17

tpHL

AnyltoF

74

135

30

65

20

ns

CL = 50 pF

tTLH

Output Transition

45

100

22

50

15

35

ns

Input Transition Times < 20 ns

tTHL

Time

45

100

22

50

15

35

ns

ns

NOTE:
1. Propagation Delays and Output Transition Times are graphically described in this section under 34000 Series CMOS Family Characteristics.

3-93

FAIRCHILD CMOS • 34085
TYPICAL ELECTRICAL CHARACTERISTICS

~1000
I

T~I~12Jod

w 100

~

U

10

f
iii

1.0

II:

~

2

.~

103

104

105

f

20

o

~f>"

V-

Q.

-'

~

Ii:

,

10

~

CL = 15 pF
CL = 50 pF······

V

10- 4
102

30

II:

1i>1~ 1I 5 1V

..'

z
o

~

~

....
.... ..,/

CL = 15 pF

o

~

iii
~.
III
is 10-3

40

w

... ~.
~
~ 1 ~,'(,'"
.. ~.' . ... ~
VDD = 10V"
.
~ ..'
..... ~.- ....
;;.. ..'
.... ~ ...

~ 10- 1
i=
10-2

;

IIII I
'(r;w

Q.

f

PROPAGATION DELAY
VERSUSTEMEPRATURE

POWER DISSIPATION
VERSUS FREQUENCY

......

I-

t::::

~

~

INPUT FREQUENCY - Hz

o

-60

-20

120

I

;

w

~

BO 1--+-1---'.
601-...,...c...j-

f

~
I
II.

~
~

40

~

~ f:.- IVDD=115~

1--,j,.""-I-+-I-+---1~..I---I

201-~~~~~~~-~~--4

O~~_~~~L-~_~-L~

o

CL - LOAD CAPACITANCE - pF

3-94

20

60

100

140

TA - AMBIENT TEMPERATURE - °C

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

~
o

~

I
II.

106

~

V

VV

FAIRCHILD CMOS • 34086
4-WIDE 2-INPUT AND-OR-INVERT GATE

DESCRIPTION - The 34086 is a 4-Wide 2-lnput AND-OR-Invert (AO!) Gate with two additional inputs (18 and!9} which can be used ~ either
expander inputs or inhibit inputs by connecting them to any standard CMOS output. A HIGH on 18 or a LOWon Ig forces the Output (F} LOW
independent of the other eight inputs (10-171. The Output (I'} is fully buffered for highest noise immunity and pattern insensitivity of output
impedance.
PIN NAMES
10-18

Gate Inputs
Gate Input (Active LOW}
Output (Active LOW}

Tg

I'

CONNECTION DIAGRAM
DIP (TOP VIEW}

LOGIC DIAGRAM

0)

'0

1[~J1'

0

'1
G) '2
@ '3
@"

'-----'

@'5

~
13

~

'6

~

17

@) '.
@Tg
F

F0

VOO
VSS

~

~

Pin 14
Pin 7

NC

='

Pin 4

DC CHARACTERISTICS: VDD as shown. VSS

PARAMETER

VDD
MIN

IDD

I,

17

3 [

i'

16

4[

NC

19] 11

5 [

12

18] 10

6 [

13

15

7[

Vss

14;J 8

J

13

12

9

'0· '1 + '2· 13 + '4· 15 + IS ·'7 + '8 + '9
NOT":
The F latpak version has the same
pinouts (Connection Diagram) 85 the
Dual I n-Line Package.

NOTE:
A HIGH on IS or a LOW on 19 forces the output (F) LOW.

SYMBOL

J
J

2 [

Quiescent
Power
Supply
Current

=0 V
LIMITS
V DD =10V

=5V

TYP

MAX

MIN

TYP

0.5
15.0
0.05
3.0

XC
XM

VOD
MIN

MAX

=15 V

TYP
1.0
6.0
0.02
1.2

15.0
30.0
0.1
6.0

TEST CONDITIONS

UNITS

TEMP

"A

MIN. 25°C
MAX

~A

MIN. 25°C
MAX

MAX
All inputs common
and at 0 V or VDD

NOTE: Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Charactaristics.

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VD D as shown. VSS

=0 V. TA =25°C

LIMITS
SYMBOL

PARAMETER

V DD
MIN

=5 V

VDD

TYP

MAX

MIN

=10V

VDD
MIN

=15V

TYP

UNITS

TYP

MAX

150
150

35
35

70
70

20
20

ns
ns
ns
ns

tpLH
tpHL

Propagation Delay.
10 through 18 to ]!

80

tpLH
tpHL

Propagation Delay.

40

Ig to

40

60
60

20
20

30
30

10
10

tTLH
tTHL

Output Transition
Time

25
25

45
45

12
12

25
25

8
8

tpLH
tpHL

Propagation Delay.
10 through 18 to F

100
100

180
180

40
40

80
80

25
25

ns
ns

tpLH
tpHL

froPl!l!ation Delay.
19 to F

65
65

100
100

35
35

50
50

20
20

ns
ns

tTLH
tTHL

Output Transition
Time

55
55

100
100

25
25

50
50

18
18

r

80

TEST CONDITIONS

MAX

20
20

35
35

CL = 15 pF
InputTransitionTimes .. 20ns

ns
ns

CL =50 pF
Input Transition Times .. 20 ns

ns
ns

NOTE:
Propagation I;)elays and Output Transition Times are graphically described in this section under 34000 Series CMOS Family Characteristics.

1.

3-95

FAIRCHILD CMOS • 34086
TYPICAL ELECTRICAL CHARACTERISTICS

POWER DISSIPATION
VERSUS FREQUENCY

PROPAGATION DELAY
VERSUS TEMPERATURE

l!!
I

w

;

U

o
z
o

~
~

ffi
Il~ 10-1 H+t+-I---H-rY'btHl---' ,-H.I-1'-"''9-+1t--l

i

40

I
20

II:

w
;: 10- 4

~

l!!

>

z

o

~

~

106

140

\

60

1"-

40

!!}

20

E

o

,

;

I\~

w

z
o

~

"8.oA'

~

\

-60
-20
20
60
100
140
-40
0
40
80
120

6

180

TAI=

25~C

150

"I)" /
"~""",,

120

g:

10

60

VOO=~~-

I

e

30

,

0

E

15

VDD - POWER SUPPLY VOLTAGE - V

~

,'"
I-- ~

1"-

~

V

.......-

90

o

~ "-..... ...........
'~

o

----

o

~~

Il-

e

!
I

TA = 25°C

"<"

oII:

VO~- ...VOO~ f-- f--

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

0.

80

./

PROPAGATION DELAY
VERSUS
POWER SUPPLY VOLTAGE

\'\?"~
-~ ~~

100

0

?

TA - AMBIENT TEMPERATURE - °C

'\

120

E

107

V

INPUT FREQUENCY - Hz

160

::5

:!l

,

"
102

"

"00

60 / '

en
"
C10-3~~-I-~~~

."..,

I_,,~ "",

80

g:

~10-2H-J.I'1i""'b~1'f---l

CL= 15 pF

w

o

~

100

VOO:15 V

I-

0

~

~

~

~

1001~1~1~

CL - LOAD CAPACITANCE - pF

3-96

34099
8-BIT ADDRESSABLE LATCH
DESCRIPTION - The 34099 is an 8-Bit Addressable latch with three Address Inputs (AO-A2), a
Data Input (D), an active lOW Enable Input (E"), an active HIGH Clear Input (Cl) and eight Parallel
latch Outputs (00-°7).

lOGIC SYMBOL
14

13

1

2

3

When the Enable (E! and the Clear (Cl) Inputs are HIGH, all Outputs (°0-°7) are lOW. Eightchannel demultiplexing or active HIGH 1-of-8 decoding with output enable operation occurs when

the Clear Input (Cl) is HIGH and the Enable Input (E! is lOW.
34099

When the Clear (Cl) and Enable (E) Inputs are lOW, the selected Output (00-07ljdetermined by the
address Inputs AO-A2) follows the Data Input (OJ. When the Enable Input (E) goes HIGH, the
contents of the latch are stored. When operating in the addressable latch mode (E ~ Cl ~ lOW),
changing more than one bit of the address (AO·A2) could impose a transient wrong address. Therefore,
this should only be done while in the memory mode (E ~ HIGH, Cl ~ lOW).

15

4

5

6

Voo
VSS

•
•
•
•
•
•

SERIAl-TO-PARAllEL CAPABILITY
EIGHT BITS OF STORAGE WITH THE OUTPUT OF EACH BIT AVAILABLE
RANDOM (ADDRESSABLE! DATA ENTRY
ACTIVE HIGH DEMULTIPLEXING OR DECODING CAPABILITY
EASI LY EXPANDABLE
COMMON ACTIVE HIGH CLEAR

7
=

9

10 11

12

Pin 16

= Pin 8

CONNECTION DIAGRAM
DIP (TOP VIEW)
16
15
14
13
12

11
10

PIN NAMES
AO-A2

o
E
Cl

°0-°7

Address Inputs
Data Input
Enable Input (Active lOW)
Clear Input (Active HIGH)
Parallel latch Outputs

NOTE:
The F latpak version has the same
pinouts (Connection Diagram) as the
Dual 1n-Line Package.

LOGIC DIAGRAM
CL

~@

3-97

Voo
VSS

o

= Pin 16
= Pin 8
= Pin Numbers

FAIRCHILD CMOS • 34099

MODE SELECTION
E

L

CL

MODE

L

L

Addressable Latch

H

L

Memory

L

H

Active HIGH 8-Channel Demultiplexer

H

H

Clear

"" LOW Level

H
= HIGH Level
QN-1 = State Before the Positive Transition of the Enable Input

TRUTH TABLE
PRESENT OUTPUT STATES
CL

E

0

AO

Al

A2

QO

Ql

Q2

Q3

Q4

Q5

Q6

Q7

H

H

X

X

X

X

L

L

L

L

L

L

L

L

CLEAR

H

L

L

L

L

L

L

L

L

L

L

L

L

L

DEMULTIPLEX

H

L

H

L

L

L

H

L

L

L

L

L

L

L

H

L

L

H

L

L

L

L

L

L

L

L

L

L

H

L

H

H

L

L

L

H

L

L

L

L

L

L

H

L

H

H

H

H

L

L

L

L

L

L

L

H

L

H

X

X

X

X

L

L

L

L

L

L

QN-l
L

QN-l

QN-l

QN-l

L

L

H

L

L

L

H

L

L

H

L

L

QN-l

QN-l
L

QN-l

L
L

L

H

H

L

L

QN-l

H

QN-l

L

L

L

H

H

H

QN-l

•

QN-l

L

L

L

H

H

H

H

QN-l

.. QN-l

H

MODE

..•.

MEMORY
ADDRESSABLE

...

QN-l

LATCH

DC CHARACTERISTICS: V DD as shown. VSS = 0 V
LIMITS
SYMBOL

PARAMETER

VDD
MIN

Quiescent

Power
100

Supply
Current

XC
XM

=5 V

TYP

VDD
MAX

MIN

= 10V

TYP

VDD

MAX

MIN

= 15 V

TYP

10

20

4

100

200

40

1

2

0.4

15

30

6

UNITS

TEMP

~A

~A

MIN. 25°C
MAX
MIN. 25°C
MAX

NOTE: Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Characteristics.

3-98

TEST CONDITIONS

MAX
All inputs common
and at 0 V or V DD

FAIRCHILD CMOS • 34099
AC CHARACTERISTICS AND SET-UP REQUIREMENTS: V DD as shown, VSS = 0 V, TA = 25°C

SYMBOL

LIMITS
V DD = 10V

V DD = 5 V

PARAMETER

MIN

TYP

MAX

MIN

TYP

MAX

V DD = 15 V
MIN

TYP

UNITS

tpLH
tpHL

Propagation Delay,
Eto Qn

90
90

40

40

30
30

ns
ns

tpLH
tpHL

Propagation Delay,
D to Qn

75
75

35
35

25
25

ns
ns

tpLH
tpHL

Propagation Delay,
Address to On

100
100

45
45

35
35

ns
ns

tpHL

Propagation Delay, CL to On

75

35

25

ns

40
40

20
20

15
15

ns
ns

110
110

50
50

35
35

ns
ns

tTLH
tTHL

Output Transition
Time

tpLH
tpHL

E to On

tpLH
tpHL

Propagation Delay,
D to On

96
95

45
45

30
30

ns
ns

tpLH
tpHL

Propagation Delay,
Address to On

120
120

55
55

40
40

ns
ns

Propagation Delay,

tpHL

Propagation Delay, CL to On

95

45

30

ns

tTLH
tTHL

Output Transition
Time

75
75

40
40

25
25

ns
ns

ts
th

Set-Up Time, D to E
Hold Time, D to E

30

40

10
20

5
20

ns
ns

ts
th

Set-Up Time, Address to
Hold Time, Address to E

30
40

10
20

5
20

ns
ns

50

20

15

ns

50

20

15

ns

E

E Pulse Width

twE

Minimum

twCL

Minimum CL Pulse Width

TEST CONDITIONS

MAX

CL = 15 pF
Input Transition
Times';; 20 ns

CL = 50 pF
Input Transition
Times';; 20 ns

CL = 15 pF
Input Transition
Times .. 20 ns

NOTES:
1. Propagation Delays and Output Transition Times are graphically described in this section under 34000 Series CMOS Family Characteristics.
2. Propagation Delays (tPLH and tPHL) and Output Transition Times (tTLH and tTHl) will change with Output Load Capacitance (el)'
Set-up Times (t 5 ), Hold Times (th), and Minimum Pulse Widths (tw) do not vary with load capacitance.

SWITCHING WAVEFORMS

MINIMUM PULSE WIDTH FOR E AND CL
AND SET-UP AND HOLD TIMES, D TO E AND An TO E
NOTES:
1. Sat-up and Hold Times are shown as positive values but may

be specified as negative values.
2. The Address to Enable Set-up Time is the time before the HIGH-

to-LOW Enable transition that the Address must be stable so
that the correct latch is addressed and the other latches are
not affected.

3-99

34104
QUAD LOW VOLTAGE TO HIGH VOLTAGE
TRANSLATER .WITH 3-STATE OUTPUTS

DESCRIPTION - The 34104 Quad Low Voltage to High Voltage Translator with 3-State Outputs
provides the capability of interfacing low voltage circuits to high voltage circuits, such as low voltage

CMOS and TTL to high voltage CMOS. It has four Data Inputs (10-13), an active HIGH Output Enable
input (EO), four Data Outputs (ZO-Z3) and their Complements (Zo-Z3). With the Output Enable
input HIGH, the Outputs (ZO-Z3, 20-23) are in the low impedance "ON" state, either HIGH or LOW
as determined by the Data Inputs; with the Output Enable input LOW, the Outputs are in the high
impedance "OFF" state.

CONNECTION DIAGRAM
DIP (TOP VIEW)

The device uses a common negative supply (VSS) and separate positive supplies for inputs (VDDI) and
outputs (VDDO)' VDDI must always be less than or equal to VDDO, even during power turn-on and
turn-off. For the allowable operating range of VDDI and VDDO see Figure 1. Each input protection
circuit is terminated between VDDO and VSS. This allows the input signals to be driven from any
potential between VDDO and VSS, without regard to current limiting. When driving from potentials
greater than VDDO or less than VSS, the current at each input must be limited to 10 rnA.
When used in a bus organized system, all 34104 devices on the same bus line should be connected to
the same VDDO and VSS supplies. Otherwise, parasitic diodes from the output to VDDO and VSS can
become forward biased, even while the device is in the OFF state, causing catastrophic failure if the
current is not limited to 10 rnA.

•
•
•

11
10

3-STATE FULLY BUFFERED OUTPUTS
OUTPUT ENABLE INPUT (ACTIVE HIGH)
DUAL POWER SUPPLY

PIN NAMES
10-13
EO
ZO-Z3
ZO-Z3

FUNCTION
Data Inputs
Output Enable Input
Data Outputs
Complimentary Data Outputs

NOTE:
The F latpak version has the same
pinouts (Connection Diagram) as the
Dual In-Line Package.

LOGIC SYMBOL

®

@
EO

@
Vooo

=

Pin

1

VOOI

~

Pin 16

VSS

~

Pin 8

a = Pin NUmber

3-100

FAIRCHILD CMOS • 34104
DC CHARACTERISTICS: VDDO

=VDDI

as shown, VSS

=0 V
LIMITS

SYMBOL

PARAMETER

VDDO/ I - 10 V

VDDO/ I - 5 V
MIN

TYP

MAX

MIN

V IH

Input HIGH
Voltage

3.5

*

7.0

V1L

Input LOW
Voltage

**

1.5

**

VOH

Output HIGH
Voltage

VOL

II

4.99
4.95
4.0

Output LOW
Voltage

Input Current -

XC
XM

TYP

VDDO/I- 15 V

MAX

MIN

TYP

UNITS

TEMP

TEST CONDITIONS

MAX

* 10.5

*

V

All

Guaranteed Input
HIGH Voltage

**

4.5

V

All

Guaranteed Input
LOW Voltage

V

MIN,25°C
MAX
All

3.0

14.99
14.95
13.0

9.99
9.95
9.0
0.01

0.01

0.01

0.05

0.05

0.05

0.5

1.0

2.0

0.1
0.01

0.1
0.01

1.0
1.0

V

~A

IOH = 0 rnA
Note 1
IOH - 0 rnA
Note 2

MIN,25°C
MAX

IOL = 0 rnA
Note 1

All

IOL - 0 rnA
Note 2

25°C

Lead Under Test at 0 V
or VDDO ' All Other
Inputs Simultaneously
at 0 V or VDDO

IOH

IOL

-1.5
-1.0

Output HIGH
Current

MIN,25°C
rnA

MAX

VOUT = 2.5 V for
VDDO = 5 V
Note 1

Output LOW
Current

-0.7
-0.4

-1.4
-0.8

-2.2

MIN,25°C

-1.4

MAX

1.0
0.8

2.6
2.0

3.6

3.6

0.4

1.2

2.0

rnA

MIN
25°C
MAX

VOUT = VDDO -0.5 V
Note 1
V OUT = 0.4 V for
VDDO = 5 V
VO UT = 0.5 V for
VDDO = 10V
V OUT = 0.5 V for
V DD O=15V
Note 1

IOZH
Note 3

Output OFF

IOZL
NOle 3

Output OFF

Current HIGH,XM
Current LOW,XM
Quiescent

IDD

I Power

XC

, Supply

I Current

0.05
3.0
-0.05
-3.0
50
700
5

XM

10

-

0.1
6.0

0.02
1.2

~A

MIN,25°C
MAX

to VDDO' EO = Vss

-0.1
-6.0

-0.02
-1.2

~A

MIN,25°C
MAX

to VSS' EO = VSS

100
1400

20
280

pA

300
600

60
120

pA

MIN,25°C
MAX
MIN,25°C

Output Returned
Output Returned
All Inputs
Common and at

o V or

MAX

* v1H mllst be less than or equal to VODO' If VIH is greater than VDDO. current at each input must be limited to 10 rnA.
* *VIL must be greater than or equal to VSS, If VI L is less than VSS. current at each input must be limited to 10 rnA.
Notes:
1. Inputs at 0 V or VOOO per function.
2. Inputs at 0.3 VOOO or 0.7 VDO per function.
3. For IOZH and IOZL commercial product limits, multiply the above military product limits by 10.

3-101

VDDI

FAIRCHILD CMOS. 34104
AC CHARACTERISTICS AND SET·UP REQUIREMENTS: V DDI = 5 V, VDDO as shown, VSS = 0 V, TA = 25°C
LIMITS
SYMBOL

V DDO = 5 V

PARAMETER

MIN

TYP

V DDO =10V
MIN

MAX

TYP

MAX

V DDO =15V
MIN

TYP

UNITS

TEST CONDITIONS

MAX

tpLH
tpHL

Propagation Delay,
In to Zn or Zn

135
135

75
75

65
65

ns
ns

CL = 15 pF
Input Transition Times.;; 20 ns

tpZH
tpZL

Output Enable
Time

190
lB5

95
90

75
75

ns
ns

RL = 1 k n to VSS
RL = 1 kntoV DDO

tpHZ
tpLZ

Output Disable
Time

100
100

75
70

70
60

ns
ns

RL = 1 kn to VSS
RL = 1 k n to V DDO

tTLH
tTHL

Output Transition
Time

30
30

18
18

16
16

ns
ns

tpLH
tpHL

Propagation Delay,
In to Zn or Zn

160
160

85
85

75
75

ns
ns

CL = 50 pF
Input Transition Times';; 20 ns

tpZH
tpZL

Output Enable
Time

200
200

100
100

80
80

ns
ns

RL = 1 kntoVsS
RL = 1 kn to V DDO

tpHZ
tpLZ

Output Disable
Time

115
110

80
80

75
70

ns
ns

RL = 1 kntoVsS
RL = 1 kU to V DDO

tTLH
tTHL

Output Transition
Time

60
60

30
30

25
25

ns
ns

NOTE:

1. Propagation Delays and Output Transition Times are graphically described in this section under 34000 Series CMOS Family Characteristics.

Fig. 1 TYPICAL ELECTRICAL CHARACTERISTICS
VDDO VERSUS VDDI

>

15

I
w

12 r-

Cl

«

~~~~~~~~~~~~W~
~~~~~r __

--

!:;
0

>
>
-'

~~'\~~V

9

""::;)

~~ f\~ V

(I)

!

6

II:

w

!

:=

0
"-

-

i

Vi

3

I

..

~\\\~ V,
~W I

!

0
C

!--

c
>

0

i

0
VDDI

3

12
15
6
9
POWER SUPPLY VOLTAGE - V

SWITCHING WAVEFORMS
EO

~~50%
I-

50%.1 '-

-

tPHZ

OUTPUT
90%

EO

/

HIGH Z
"OFF" STATE

" ..... ....... -

...

;;

"

50%

\0%

tpZH

-

J

0.5 V ODO

-.,.,..!:... - - ---o.v

10%

OUTPUT

OUTPUT ENABLE TIME
(tPZH) AND OUTPUT DISABLE TIME (tPHZ)

t."
,

-

tPLZ
;-

...

l
tpZL

---;;;;--- - -

HIGH Z
"OFF" STATE

"
"

~
" 0.5 VODO

OUTPUT ENABLE TIME
(tPZL) AND OUTPUT DISABLE TIME (tPLZ)

3·102

Vooo

34512
8-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS
DESCRIPTION - The 34512 is an 8-lnput Multiplexer with Active LOW logic and output enables (E,
EO). One of eight binary inputs is selected by Select Inputs SO, 51 and 52 and is routed to the output
F.A HIGH on the Output Enable (EO) causes the F output to assume a high impedance or "OFF"
state, regardless of other input conditions. This allows the output to interface directly with bus
oriented systems (3-state). When the active LOW Enable (E) is HIGH, it forces the output LOW
provided the Output Enable (EO) is LOW. By proper manipulation of the inputs, the 34512 can
provide any logic functions of four variables. The 34512 cannot be used to multiplex analog signals.

LOGIC SYMBOL
7

15101

9

So
S,

34512

5,

Voo = Pin 16
VSS = Pin 8
•
•
•
•

CONNECTION DIAGRAM
DIP (TOP VIEW)

SELECTS ONE·Of-EIGHT DATA SOURCES
PERFORMS PARALLEL-TO-SERIAL CONVERSION
3-STATE OUTPUTS WITH ACTIVE LOW OUTPUT ENABLE
ACTIVE LOW LOGIC ENABLE

PIN NAMES
5elect Inputs
Output Enable (Active LOW)
Enable (Active LOW)
Multiplexer Inputs
Multiplexer Output

SO,51,52

EO
E
10 to 17
F

NOTE:
The F latpak version

has the same
pinouts (Connection Diagram) as the

Dual I n-Line Package.

LOGIC DIAGRAM

TRUTH TABLE
INPUTS

EO E
H

52

5,

So

X

X

X

H

VDO

=

Pin 16

VSS :::: Pin

o

8

= Pin Number

@
"'~------~

15

16

17

X
X

X

X

X

X

X

X

X

X

L

X

X

X

X

X

H

X

X

X

X

X

X

L

X

H

X

H

X

X

X

X

X

X

L

X

X

X

X

X

X

X

L

X

X

X

X

X

X

X

H

X

X

X

X

L

H

X

X

X

X

H

H

H

X

X

H

X

X

H

H

X

X

X

X

L

X

X

X

H

X

X

X

X

H

X

X

X

H

X

X

X

X

L

X

X

L

H

X

X

X

X

H

X

X

H

H

H

L

H

H

X

X

X

X

X

X

H

H

X

X

X

X

X

X

H

X

H

H

H

X

X

X

X

X

X

L

H

H

H

X

X

X

X

X

X
X

X

H

H

X

X

X

X

X

X

X

X

X

X

X

Z

Don't Care
High I mpedance State

3-103

X
X

14

H

HIGH Level
X

X

13

X

LOW Leve!

@

O~'

OUTPUT
12

X

H

H

X

X

I,

H

H

H

10

X
H

FAIRCHILD CMOS • 34512
DC CHARACTERISTICS: VDD as shown, VSS = 0 V

"MOO'

I

IOlH
(Note 2)
lOlL
(Note 2)

LIMITS

""'Mme

Output OFF

MIN

TYP

MIN

MAX

TYP

UNITS

TEMP

0.02
1.2

uA

MIN,25°C
MAX

Output returned to
VDD , EO = VDD

-0.05
-3.0

-0.1
-6.0

-0.02
-1.2

uA

MIN,25°C
MAX

Output returned to

30
600
5
100

60
1200
10

12
240

uA

-- ~--------

1--.

Current LOW,XM
XC
XM

I

TEST CONDITIONS

MAX

6.0

0.1

0.05
3.0

Current HIGH,XM
---- I--Output OFF

V DD = 15 V

V DD = 10V
MAX

TYP

MIN

Quiescent
Power
Supply
Current

IDD

V DD = 5 V

2

MIN,25°C
MAX
MIN,25°C
MAX

uA

200 L---~ 40

VSS ' EO =V DD
All inputs common
and at 0 V or VDD

NOTES:

1. Additional DC Characteristics are listed in this section under 34000 Series CMOS Family characteristics.
For IOZH and 10ZL commercia! product limits, multiply the above military product limits by 10.

2.

AC CHARACTERISTICS: V DD as shown, VSS = 0 V, J A = 25°C

SYMBOL

MIN

TYP

MAX

Data to Output

130
130

tpLH
tpHL

Propagation Delay,
Select to Output

tpLH
tpHL

V DD = 15 V

UNITS

TEST CONDITIONS

TYP

MAX

260
260

65
65

130
130

45
45

ns
ns

150
150

300
300

75
75

150
150

55
55

ns
ns

Propagation Delay,
E to OutPUt

70
70

140
140

35
35

70
70

25
25

ns
ns

tplH
tplL

Output Enable
Time

26
28

70
70

11
11

35
35

10
10

ns
ns

(R L = 1 k n to VSS)
(R L = 1 kn to VDO)

tpHZ
lPLZ

Output Disable
Time

34
39

90
90

20
20

45
45

15
15

ns
ns

(R L = 1 k n to VSS)
(R L = 1 k n to VOO)

tTLH
tTHL

Output Transition
Time

45
45

100
100

20
20

60
60

15
15

tpLH
tpHL

Propagation Delay,
Data to Output

150
150

300
300

75
75

150
150

52

52

ns
ns

IpLH
tpHL

Propagation Delay,
Select to Output

175

175

350
350

85
85

170
170

60
65

ns
ns

tpLH
tpHL

Propagation Delay,
E to Output

90
90

175
175

45
45

90
90

30
32

ns
ns

Output Enable

33
30

85
85

20
22

45
45

18
20

ns
ns

(RL = 1 kn toVSS)
(RL = 1 k!l to VDD)

39
40

100
100

20
20

50
50

15
15

ns
ns

(R L = 1 kn to VSS)
(R L = 1 kn toV DD )

90
100

200
200

40
40

100
100

33
30

tpLH

I Propagation Delay,

tpHL
---_.

,

LIMITS
VDD = lOV

V DD = 5 V

PARAMETER

tpZH
tpZL

I Time

tpHZ
tpLZ

Oulput Disable
Time

tTLH
tTHL

Output Transition
Time

I

MIN

-

MIN

TYP

MAX

40
40

65

65

CL = 15 pF
Input Transition Times.; 20 ns

I

ns
ns
CL = 50 pF
Input Transition Times.; 20 ns

ns
ns

NOTE:

1.

Propagation Delays and Output Transition Times are graphically described in this section under 34000 Series CMOS Family Characteristics.

3-104

FAIRCHILD CMOS • 34512
TYPICAL ELECTRICAL CHARACTERISTICS

TYPICAL POWER DISSIPATION
VERSUS FREQUENCY

~

1000

I

~~ I~ 2~ob: II

w 100

~
U

10

i1:

1.0

II:

...
w

~~

Z 10-1

o
~
i1:

.... ~
10- 2

iii

I;.:::

5 10-3 ~

~~

~

10-102

~

~

....

,... ~

~

~I;.:::

(-

~5V
VDD = 10 V

':''?,I?

(-~

IIII

CL = 15 pF--CL=50 p F - -

II:

...

~
,...

IIII

~~DI= 111Jl
i ~;

C!J

PROPAGATION DELAY
VERSUS TEMPERATURE

103

104

106

105

INPUT FREQUENCY -

107
TA - AMBIENT TEMPERATURE -

Hz

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

00 20 40
CL - LOAD CAPACITANCE -

pF

SWITCHING WAVEFORMS

EO

J50%

tpHZ

--.II~

~
F

50%\

--.1

""'1-+---tP-ZH

f

HIGH Z
0.5 VOO
,""OFF" STATE /
....... ---.-:::...----OV

OUTPUT ENABLE TIME
hpZH) AND OUTPUT DISABLE TIME (tpHZ)

OUTPUT ENABLE TIME
(tPZL) AND OUTPUT DISABLE TIME (tPLZ)

3-105

°C

FAIRCHILD CMOS • 34512
APPLICATIONS
MULTIPLEXER AS A FUNCTION GENERATOR - In most digital systems there are areas, usually in the control section, where a number of
inputs generate an output in a highly irregular way. In other words, an unusual function must be generated which is apparently not available as
an MSI building block. In such cases, many designers tend to return to classical methods of logic design with NAND and NOR gates using
Boolean Algebra, Karnaugh maps and Veitch diagrams for logic minimization. Surprisingly enough, multiplExers can simplify these designs.
The 34512 8-lnput multiplexer can generate anyone of the 65,536 different functions of four variables. An example will illustrate the
technique. Assume four binary inputs are A, B, C and D and F is the desired function (See Fig. 1). If C is connected to SO, B to S1 and A to S2,
any combination of A, Band C will select an input (assuming the output is enabled). For each combination of A, Band C, the required output,
as a function of the fourth variable D, is either H or L the same as D or the opposite of D. Therefore, the truth table may be examined and each
input of the 34512 is connected to VDD, VSS, 0 or 0 as required and in such fashion the function is generated.
In the example shown, (Fig. 1) the first two outputs are the opposite of D, so 10 is connected to D. The second two are HIGH, so 11 is
connected to VDD, etc.
32·INPUT MULTIPLEXER - The 3-State Output Enable can be used to expand the 34512. A 32·lnput Multiplexer utilizing four 34512s and
a 34011 is shown in Fig. 2.

INPUT VARIABLES

F

L

L

H

L

H

L

H

L

H

H

H

H

H

L

L

L

L

H

L

H

H

L

H

H

L

L

L

H

H

H

L

H

L

L

L

L

B

C

L

L

L

L

L

L

L
L

L

'''UTD~

REQUIRED FUNCTION

0

A

/
H

-"~

I-----""""t- OUTPUT

--

= HIGH

L.evel

L = LOW Level

D--------+---.----"'
VDD--------+-~+---__1

Vss ----...,..~_t_+_+_,-_(

~

"
"
INPUT 30
INPUT31

Fig. 1

'D
"

'"3
"
"IS

17

32·INPUT MULTIPLEXER,
THE INPUTISSELECTED
BY 5·81T ADDRESS A4 - AO
AND PRESENTED AT
THE OUTPUT

Fig. 2

3-106

34518 • 34520
DUAL 4-BIT DECADE/BINARY COUNTERS
DESCRIPTION - The 34518 is a Dual 4·Bit Internally Synchronous BCD Counter and the 34520 is
a Dual 4·Bit Internally Synchronous Binary Counter. Both have the same operation except for the
count sequence. Each counter has both an active HIGH Clock Input (CPO) and an active LOW Clock
Input (CP1). buffered OutPUtS from all four bit positions (00-03) and an active HIGH overriding
asynchronous Master Reset Input (M A).

LOGIC SYMBOLS

The counter advances on either!!!!' LOW·to·HIGH transition of the CPO Input if CPl is HIGH or the
HIGH·to·LOW transition of the CPl Input if CPO is LOW (see the Truth Table). Either Clock Input
(CPO. CP1) may be used as the Clock Input to the counter and the other Clock Input may be used
as a Clock Inhibit Input.
A HIGH on the Master Reset Input (MR) resets the counter (00-0 3
Inputs (CPO. GIll).

= LOW)

independent of the Clock
112 OF 34518iJ4520
10

•
•
•
•
•

TYPICAL COUNT FREQUENCY OF 10 MHz AT VDD = 10 V
TRIGGERED ON EITHER A LOW·TO·HIGH OR A HIGH·TO·LOW TRANSITION
ASYNCHRONOUS ACTIVE HIGH MASTER RESET
BUFFERED OUTPUTS FROM ALL FOUR BIT POSITIONS
FULLY SYNCHRONOUS COUNTING

PIN NAMES
CPO a• CPOb
CPla. CPlb
MRa. MAb
Ooa-0 3a
Oob-03b

CPb

15

Clock Input (L ... H Triggered)
Clock Input (H'" L Triggered)
Master Reset Inputs
Outputs
Outputs

11121314

Voo

= Pin

VSS

=

16

Pin 8

CONNECTION DIAGRAM
DIP (TOP VIEW)
16

TRUTH TABLE
13

CPo

J

CPl
H

L

Counter Advances
Counter Advances

X

L

No Change

L

No Change

L

L

No Change

"-

L

No Change

H

Aeset (Asynchronous)

""- J
X

H
X

MODE

L

L

.J

MR

X

"
x

=

L

10

Don't Care
LOW Level

H = HIGH Level
~= Positive-Going Transition

""""'-=

Negative-Going Transition

1/2 OF A 34518 LOGIC DIAGRAM
0,

(!)OR@

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) a$ the
Dual I n~Line Package.

0,@OR@

MR--~~~()~-+----~------+---+---~~---t---+----~-r------+---~

Q)OR@

Voo = Pin 16
VSS = Pin 8
= Pin Number

o

3·107

FAIRCHILD CMOS • 34518 • 34520
1/2 OF A 34520 LOGIC DIAGRAM
Q,

Q,

Q3

~5-

..;~

·9

Qo

(VOR@

!®OR@

-~J
r-<

(VOR@)

+
MR--J>o-o"..
CP c

r - - J.~

~i>

-

0-

,--- 0

@lOR@

~O

, - - ' J.~
-0

QI-

r -+- r '-f-

Q~

CP c

Qo-

CP C

@lOR@

aI-

r+~

Qf>-

,.l.

~i>

0)oR0
@OR@

CPo

Voo

~

VSS

= Pin

o

Ci',

Pin 16
8

= Pin Number

DC CHARACTERISTICS: VD D as shown, VSS = 0 V
LIMITS
SYMBOL

VDD - 5 V

PARAMETER

MIN

100

\

Ouiescent
Power
Supply
Current

TYP

XC
XM

VD D -10V
MAX

MIN

TYP

50
700
15
900

VDD - 15 V

MAX

MIN

TYP

100
1400

UNITS

20
2BO
5
300

25
1500

TEMP

TEST CONDITIONS

MAX
~A
~A

MIN,25°C
MAX
MIN,25°C
MAX

All inputs common
and at 0 V or V DD

NOTE: Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Characteristics.

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VDD as shown, VSS = OV, TA = 25°C
LIMITS
SYMBOL

PARAMETER

V DD = 5 V
MIN

TYP

VDD = 10V

MA~

MIN

\

TYP

MAX

V DD = 15 V
MIN

TYP

UNITS

85
85

55
55

ns
ns

200

80

55

ns

35
35

18
18

12
12

ns
ns

Propagation Delay,
CPO or CP, to On

220
220

95
95

60
60

ns
ns

tpHL

Propagation Delay,
MR to On

220

90

60

ns

tTLH
tTHL

Output Transition
Time

65
65

35
35

25
25

ns
ns

70

30

20

ns

120

50

35

ns

tpLH
tpHL

Propagation Delay,
CPO or CP 1 to On

200
200

tpHL

Propagation Delay,
MR to On

tTLH
tTHL

Output Transition
Time

tpLH
tpHL

TEST CONDITIONS

MAX

IwMR

MR Minimum Pulse Width

twCP

CPO or CPl Minimum
Pulse Width

tree

MR Recovery Time

15

5

0

ns

ts

Set-Up Time, CPO to CP 1

130

57

40

ns

ts

Set-Up Time, CP 1 to CPO

130

57

40

fMAX

Input Count Frequency
(Note 3)

4

10

CL=15pF
Input Transition
Times .. 20 ns

CL=50pF
Input Transition
Times .. 20 ns

CL J 15pF
Input Transition
Times .. 20 ns

ns
MHz

NOTES:
1. ProPegation Delays and Output Transition Times are graphically described In this section under 34000 Series CMOS Family Characteristics.
2. Propagation Delays (tPLH and tpHL) and Output Transition Times (tTLH and tTHL) will change with Output Load Capacitance (eL)'
Set~up Times (t 5 ). Hold Times (th). Recovery Times (tree), and Minimum Pulse Widths (tw) do not vary with load capacitance.
3. For fMAX, input rise and fall times are greater than or equal to 5 ns and less th~ or equal to 20 ns.
4. It is recom!",ended that input rise and fall times to either Clock I nput (CPO or CP1) be less than 15 J.i.s.

3-108

FAIRCHILD CMOS • 34518 • 34520
SWITCHING WAVEFORMS

CPo

MR

Conditions: CP1 = HIGH and the device triggers on a LOW-to-HIGH

transition at CPO. The timing also applies when CPO
device triggers on a HIGH-to-LOW transition at CPl.

~

LOW and the

MINIMUM PULSE WIDTHS FOR
CPO, CP, AND MR AND MR RECOVERY TIME

CPo

CI',

NOTE:
Set-up and Hold Times are shown as positive values but may be

specified as negative values.

SET-UP AND HOLD TIMES, CPO TO CP, AND CP, TO CPO

3-109

34539
DUAL 4-INPUT MULTIPLEXER

DESCRIPTION - The 34539 is a Dual 4-lnput Digital Multiplexer with common select logic. Each
multiplexer has four Multiplexer Inputs (10-13), an active LOW Enable Input (E) and a Multiplexer
Output (Zl. When HIGH, the Enable Input (E) forces the Multiplexer Output (Z) of the respective
multiplexer LOW, independent of the Select (SO, S,) and Multiplexer (10.13) Inputs. With the Enable
Input (E) LOW, the common Select Inputs (SO, S,) determine which Multiplexer Input (10.13) on
each of the multiplexers is routed to the respective Multiplexer Output (Z).
•
•

COMMON SELECT LOGIC
ACTIVE LOW ENABLES

LOGIC SYMBOL

6

3

15

10

11

12

13

34539

s,

Za, Zb

4

14

PIN NAMES
10e, I'a, 12a, 13a
lab, 11b, 12b, 13b
SO,S,
Ea , Eb

5

z,

Multiplexer Inputs
Select Inputs
Enable Inputs (Active LOW)
Multiplexer Outputs

VDO = Pin 16

VSS = Pin 8

TRUTH TABLE

E

Z

X

X

H

L

L

L

L

10

H

L

L

11

So S,

CONNECTION DIAGRAM
DIP (TOP VIEW)

OUTPUT

INPUTS

L

H

L

12

H

H

L

13

H = HIGH Level
L =- LOW Level
X = Don't Care

'6
'5

LOGIC DIAGRAM

14

13
12
11
10

VDD
VSS

o

= Fin
= Pin

NOTE:
The F latpak version

16
8

has the same

pinouts (Connection Diagram) as the

= Pin Number

Dual In-Line Package.

3·'10

FAIRCHILD CMOS • 34539
DC CHARACTERISTICS: V DD as shown, VSS = 0 V
LIMITS
SYMBOL

PARAMETER

MIN
Quiescent

Power
IDD

Supply
Current

V DO =10V

V DD = 5 V

TYP

MIN

MAX

TYP

VOD = 15 V

MIN

MAX

TYP
12

XC

30
600

60
1200

240

XM

5
100

10

2

200

40

TEST CONDITIONS

UNITS

TEMP

~A

MIN,25°C
MAX

MAX

~A

All inputs common
and at 0 V or V OD

MIN,25°C
MAX

NOTE: Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Characteristics.

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VDO as shown, VSS = 0 V, TA = 25°C
LIMITS
SYMBOL

PARAMETER

V DO = 5 V

MIN

TYP

V OD =10V

MAX

MIN

TYP

MAX

V DO =15V

MIN

TYP

UNITS

TEST CONDITIONS

MAX

tpLH
tpHL

Propagation Delay,
IX tol

145
120

61
50

43
33

ns
ns

tpLH
tpHL

Propagation Oelay,
Select to l

190
192

78
78

55
55

ns
ns

CL =15pF
Input Transition

tpLH
tpHL

Propagation Delay,

100
96

42
42

29
32

ns
ns

Times.;; 20 ns

1: tol

tTLH
tTHL

Output Transition
Time

38
31

19
15

12
12

ns
ns

tpLH
tpHL

Propagation Delay,
IX tol

166
140

71
58

51
40

ns
ns

tpLH
tpHL

Propagation Delay,
Select to l

210
210

88
88

62
62

ns
ns

CL = 50 pF
Input Transition

tpLH
tpHL

Propagation Delay,
Etol

120
118

53
51

37
38

ns
ns

Times.;; 20 ns

tTLH
tTHL

Output Transition
Time

76
66

39
30

29
22

ns
ns

NOTE:
Propagation Delays and Output Transition Times are graphically described in this section under 34000 Series CMOS Family Characteristics.

3-111

34555 · 34556
DUAL 1-0F-4 DECODERS/DEMULTIPLEXERS
DESCRIPTION The 34555 and 34556 are Dual 1-of-4 Decoders/Demultiplexers. Each
decoder/demultiplexer has two Address Inputs (AO, A1), an active LOW Enable Input (EO) and four
mutually exclusive Outputs which are active HIGH for the 34555 (00-03) and active LOW for the
34556 (00-03).

LOGIC SYMBOLS

When the 34555 is used as a decoder, the Enable Input (E) when HIGH, forces all Outputs (°0-°3)

LOW. When used as a demultiplexer, the appropriate Output is selected by the data on the Address
Inputs (AO, A1) and follows as the inverse of the Enable Input (E). All unselected Outputs are LOW.

34556

When the 34556 is used as a decoder, the Enable Input (E) when HIGH forces all Outputs (00-°3)
HIGH. When used as a demultiplexer, the appropriate Output is selected by the data on the Address
Inputs (AO, A1) and follows the state of the Enable Input (E). All unselected Outputs are HIGH.

•

ACTIVE HIGH OUTPUTS FOR THE 34555 AND
ACTIVE LOW OUTPUTS FOR THE 34556
OVERRIDING ACTIVE LOW ENABLE

•

G) CVG)
OR

OR OR

1/2 Of- 345b6

1,2 OF 34555

PIN NAMES

E

OR OR OR OR

Enable Input (Active LOW)
Address Inputs
Outputs (Active HIGH - 34555 Only)
Outputs (Active LOW - 34556 Only)

AO,A1
00-0 3
00-°3

@@@®
VDO = Pin 16
VSS

o

=

Pin

= Pin

8
Number

LOGIC DIAGRAMS

1/2 OF A 34555
1/2 OF A34555

0 @
r--~==Ft:=Jo-ot>- 00
0R

CONNECTION DIAGRAMS
DIP (TOP VIEW)
34555

Q)OR@

16

A, ~0-4--t>o---+-,

15

(i)OR@

14

E--oI~~---------+

(i)OR(9)

13

Voo"'" Pin 16
VSS = Pin 8
= Pin Number

12

o

11
10

1/2 OF A 34556
1/2 OF A 34556

0 @
0R

34556

14
13

12

(i)OR@)

11

10

Voo

=

Pin 16

VSS = Pin 8
== Pin Number

o

Note: The Flatpak version has the
same pinouts (Connection Diagram)
as the Dual 1n-Line Package.

3-112

FAIRCHILD CMOS • 34555 • 34556
34555 TRUTH TABLE

34556 TRUTH TABLE

E

AO

A,

0,

02

03

04

E

AO

A,

00

0,

02

03

L

L

L

H

L

L

L

L

L

L

L

H

H

H

L

H

L

H
L

L
L

L
H

H
H

L
H

H

L

L
L

H
L

H

L

L
H

L
H

H

L

L
H
H

L

L

L

H

L

H

H

H

H

H

H

X

X

L

L

L

L

H

X

X

H

H

H

L
H

H
L
X

HIGH Level
LOW Level
Don't Care

~

~

~

L

DC CHARACTERISTICS: VDD as shown, VSS = 0 V

SYMBOL

PARAMETER

MIN

IDD

Quiescent
Power
Supply
Current

LIMITS
VDD = 10V

VDD = 5 V
TYP

MAX

XC

20
200

XM

2
100

MIN

TYP

V DD ='5 V

MAX

MIN

40
400
4
200

UNITS

TEMP

8
80

~A

MIN,25°C
MAX

0.8
40

~A

MIN,25°C
MAX

TYP

TEST CONDITIONS

MAX
All inputs common
and at 0 V or VDD

Note: Additional DC Characteristics are listed in this section under 34000 Series CMOS FamilY Characteristics.

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VDD as shown, VSS = 0 V, TA = 25°C, 34555 only

SYMBOL

PARAMETER

LIMITS
V DD -10V

V DD - 5 V
MIN

TYP

MAX

MIN

TYP

MAX

VDD - 15 V
MIN

TYP

UNITS

TEST CONDITIONS

MAX

tpLH
tpHL

Propagation Delay,
Address to 0 utput

130
105

54
45

33
40

ns
ns

tpLH
tpHL

Propagation Delay,

E to Output

130
105

51
45

32
32

ns
ns

tTLH
tTHL

Output Transition
Time

35
33

15
13

12
10

ns
ns

tpLH
tpHL

Propagation Delay,
Address to 0 utput

148
127

60
54

40
45

ns
ns

tpLH
tpHL

Propagation Delay,
~ to Output

148
127

60
53

40
40

ns
ns

tTLH
tTHL

Output Transition
Time

65
66

20
25

25
20

ns
ns

CL = 15 pF
Input Tnin~ition
Times .; 20 ns

CL = 50 pF
Input Transition
Times'; 20 ns

AC CHARACTERISTICS AND SET -UP REQUIREMENTS: VDD as shown, VSS = 0 V, TA = 25°C, 34556 only

SYMBOL

PARAMETER

LIMITS
V DD =10V

VDD = 5 V
MIN

TYP

MAX

MIN

TYP

MAX

VDD = 15 V
MIN

TYP

UNITS

TEST CONDITIONS

MAX

tpLH
tpHL

Propagation Delay,
Add ress to 0 utput

120
160

48
58

33
40

ns
ns

tpLH
tpHL

Propagation Delay,

E to Output

114
125

45
50

32
32

ns

tTLH
tTHL

Output Transition
Time

37
35

18
15

12
10

ns
ns

tpLH
tpHL

Propagation Delay,
Address to Output

140
185

57
68

40
45

ns
ns

tpLH
tpHL

Propagation Delay,

E to Output

134
145

55
58

40
40

ns
ns

tTLH
tTHL

Output Transition
Time

75
77

37
29

25
20

ns
ns

CL =15pF
Input Transition
Times'; 20 ns

CL = 50 pF
Input Transition
Times'; 20 ns

NOTE:
Propagation Delays and Output Transition Times are graphically described in this section under 34000 Series CMOS Family Characteristics.

1.

3-113

34702

PROGRAMMABLE BIT RATE GENERATOR
FAIRCHILD CMOS LSI
DESCRIPTION - The 34702 Bit Rate Generator provides the necessary clock signals for digital data

LOGIC SYMBOL

transmission systems, such as Universal Asynchronous Receiver and Transmitter circuits (UARTs). It
generates any of the 13 commonly used bit rates using an on-chip crystal oscillator, but it's design also
provides for easy and economical multichannel operation, where any of the possible frequencies must
be made available on any output channel.

ECp

One 34702 can control up to eight output channels. When more than one bit rate generator is
required, they can still be operated from one crystal.

•
•
•
•
•
•
•
•
•

PROVIDES ALL 13 COMMONLY USED BIT RATES
ONE 34702 CONTROLS UP TO EIGHT TRANSMISSION CHANNELS
USES 2.4576 MHz INPUT FOR STANDARD FREQUENCY OUTPUTS
(16 TIMES BIT RATE)
CONFORMS TO EIA RS·404
ON·CHIP INPUT PULL UP CIRCUITS
TTL COMPATIBLE-OUTPUTS WILL DRIVE 1.6 rnA
INITIALIZATION CIRCUIT FACILITATES DIAGNOSTIC FAULT ISOLATION
LOW POWER DISSIPATION-1.35 rnA POWER DISSIPATION AT 5 V AND 2.4576 MHz
16·PIN DUAL IN·LlNE PACKAGE

1

2

3

10

Voo = Pin 16
VSS = Pin 8

CONNECTION DIAGRAM
DIP (TOP VIEW)
16
15

14

13

PIN NAMES
CP

Ox

External Clock Input
External Clock Enable Input (Active LOW)
Crystal Input
Multiplexed Input
Rate Select Inputs
Clock Output
Crystal Drive Output

00-0 2

Scan Counter Outputs

Z

Bit Rate Output

ECp
IX

1M
SO-S3

Co

12

11
10

NOTE:

The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual In-Line Package.

BLOCK DIAGRAM

o
o

'x
Ox

Q0 ~--~--------------~~

o

cP~4-------------r-"\

,---------------,
I
I
I

I
I
I

I

I

I
:
I
I

Q

I
I
IMR

FF

I

INITIALIZATION
TO ALL
I
L __C.!.!!.C~!- _ _ _ ~~~R~~.J

Voo = Pin 16

VSS = Pin

o

=

8

CO

Pin Number

3-114

FAIRCHILD CMOS • LSI • 34702
TABLE 1

TABLE 2

CLOCK MODES AND INITIALIZATION

TRUTH TABLE FOR RATE SELECT INPUTS

IX

ECp

CP

J1Jl.Il.J"

H

L

X

L

X

H

X

L

OPERATION

S3

....n..n...I"1I Clocked from CP
H

--1L

H
L
X

-Il. =

S2

Sl

So

Output Rate (Z)
Note 1

Clocked from IX

Continuous Reset
Reset During First CP = HIGH Time

L

L

L

L

Multiplexed Input (1M)

L

L

L

H

Multiplexed Input (1M)

L

L

H

L

L

L

H

H

75 Baud

L

H

L

L

134.5 Baud

L

H

L

H

200 Baud

L

H

H

L

600 Baud

50 Baud

L

H

H

H

2400 Baud

LOW Level

H

L

L

L

9600 Baud

Don't Care

H

L

L

H

4800 Baud

1st HIGH Level Clock Pulse

H

L

H

L

1800 Baud

H

L

H

H

1200 Baud

H

H

L

L

2400 Baud

H

H

L

H

300 Baud

H

H

H

L

150 Baud

H

H

H

H

110 Baud

HIGH Level

After ECp Goes LOW
Clock Pulses

Note 1.
Actual output frequency is 16 times the indicated Output Rate,
assuming a clock frequency of 2.4576 MHz.

FUNCTIONAL DESCRIPTION - Digital data transmission systems employ a wide range of standardized bit rates, ranging from 50 baud
interfacing with electromechanical devices, to 9600 baud for high speed modems. Modern electronic systems commonly use Universal

Asynchronous Receiver and Transmitter circuits (UARTs) to convert parallel data inputs into a serial bit stream (transmitter) and to reconvert
the serial bit stream into parallel outputs (receiver). In order to resynchronize the incoming serial data, the receiver requires a clock rate that is
a multiple of the incoming bit r.ate. Popular MOS~LSI UART circuits use a clock that is 16 times the transmitted bit rate. The 34702 can
generate 13 standardized clock rates from one common high frequency input.
The 34702 contains the follo\{\ling five functional subsystems which are discussed in detail below:
1. An Oscillator Circuit with associated gating.
2. A Prescaler used as scan counter for multichannel operation (described in the applications section).
3. A network of Counter Chains to generate the required standardized frequencies.
4.

An Output Multiplexer (frequency selector) with resynchronizing output flip·flop.

5. An Initializing (reset) Circuit.
OSCILLATOR
For conventional operation generating 16 output clock pulses per bit period, the input clock frequency must be 2.4576 MHz (i.e. 9600

baud x 16 x 16, since the scan counter and the first flip·flop of the counter chain act as an internal -;- 16 prescaler). A lower input frequency
will obviously result in a proportionally lower output frequency.
The 34702 can be driven from tWQ..!!!.ternate clock sources: (1) When the ECp (active LOW External Clock Enable) input is LOW, the CP input
is the clock source. (2) When the ECp input is HIGH, crystal connected between IX and OX, or a signal applied to the IX input is the clock

a

source.
PRESCALER (SCAN COUNTER)
The clock frequency is made available on the CO (Clock Output) pin and is applied to the"'" 8 prescaler with buffered Outputs QO, Ql, and Q2.

This prescaler is of no particular advantage in single frequency applications, but it is essential for the simple and economical multichannel
scheme described in the Applications section of this data sheet.
COUNTER NETWORK

The prescaler Output 02 is a square wave of 1/8 the input frequency and is used to drive the frequency counter network generating the 13
standardized frequencies. Note that the frequencies are labeled in the Block Diagram and described here in terms of the transmission bit rate. In
a conventional system using a 2.4576 MHz clock input, the actual output frequencies are 16 times higher.
The output from the first frequency divider flip·flop is thus labeled 9600, since it is used to transmit or receive 9600 baud (bits per second).

The actual frequency at this node is 16 x 9.6 kHz = 153.6 kHz. Seven more cascaded binaries generate the appropriate frequencies for bit rates
4800, 2400, 1200,600, 300, 150, and 75.

The other five bit rates are generated by individual counters:
bit
bit
bit
bit
bit

rate
rate
rate
rate
rate

1200 is divided by 6 to generate bit rate 200,
200 is divided by 4 to generate bit rate 50,
2400 is divided by 18 to generate bit rate 134.5 with a frequency error of -0.87%,
2400 is also divided by 22 to generate bit rate 110 with a frequency error of -0.83%, and
9600 is divided by 16/3 to generate bit rate 1800.

The 16/3 division is accomplished by alternating the divide ratio between 5 (twice) and 6 (once). The result is an exact average output
frequency with some frequency modulation. Taking advantage of the -;- 16 feature of the UART, the resulting distortion is less than 0.78%,
irrespective of the number of elements in a character, and therefore well within the timing accuracy specified for high speed communications
equipment. All signals except 1800, have a 50% duty cycle.

3-115

FAIRCHILD CMOS • LSI • 34102
OUTPUT MULTIPLEXER
The outputs of the counter network are fed to a 16-input multiplexer, which is controlled by the Rate Select Inputs (SO-S3). The multiplexer
output is then resynchronized with the incoming clock in order to cancel all cumulative delays and to present an output signal at the buffered
Output (ZI that is synchronous with the prescaler Outputs (00-°21. Table 2 lists the correspondence between select code and output bit rate.
Two of the 16 codes do not select an internally generated frequency, but select an input into which the user can feed either a different,
nonMstandardized frequency, or a static level (HIGH or LOW) to generate "zero baud".
The bit rates most commonly used in modern data terminals (110. 150, 300, 1200, 2400 baud) require that not more than one input be
grounded, easily achieved with a single pole, 5-position switch. 2400 baud is selected by two different codes, so that the whole spectrum of
modern digital communication rates has a common HIGH on the S3 input.

INITIALIZATION (RESETI
The initialization circuit generates a common master reset signal for all flip-flops in the 34702. This signal is derived from a digital differentiator
that senses the first HIGH level on the CP input after the ECp input goes LOW. When ECp is HIGH, selecting the Crystal Input, CP must be
LOW. A HIGH level on CP would apply a continuous reset.
All inputs to the 34702, except IX have on-chip pull up circuits which improve TTL compatibility and eliminate the need to tie a permanently
HIGH input to VDD.

DC CHARACTERISTICS: VDD = 5 V, VSS = 0 V
SYMBOL

LIMITS

PARAMETER

V IH

Input HIGH Voltage

VIL

Input LOW Voltage

VO H

Output HIGH Voltage

MIN

TYP

MAX

3.5
1.5
4.99
4.95

UNITS

TEMP

V

All

Guaranteed Input HIGH Voltage

V

All

Guaranteed Input LOW Voltage

V

MIN,25°C
MAX

4.0

All
0.01

VOL

Output LOW Voltage

0.05

V

0.5
Input LOW Cu rrent
IlL'

for Input IX
Input LOW Current
for all Other Inputs
Input HIGH Current

IIH

IOH

IOL

for Input IX
Input HIGH Current
for all Other Inputs

-0.1
-0.01

XC
XM
XC
XM

-30
-30

XC
XM

0.1
0.01

XC
XM

0.1
0.01

Output HIGH Current

Output LOW Current

-1.5
-1.0
-0.7

-3.0
-2.0
-1.4

-0.4

-0.8

3.5

5.5

3.5

5.5
3.2

1.6

IDDL*

IDDH

Quiescent
Power
Supply
Current, LOW
Quiescent
Power
Supply
Current, HIGH

XC
XM

XC
XM

10

IOL = 0 mA, Inputs at 1.5 or 3.5 V

Lead Under Test at 5 V
All Other Inputs Simultaneously at 0 V

rnA

MIN,25°C
MAX

~A

pA

30

IOL =0 mA, Inputs at 0 or 5 V per the
Logic Function or Truth Table

25°C

I

5

rnA, Inputs at 1.5 or 3.5 V

pA

pA

60

=0

Lead Under Test at 0 V
All Other Inputs Simultaneously at 5 V

~A

400

IOH

25°C

mA

200

IOH = 0 rnA, Inputs at 0 or 5 V per the
Logic Function or Truth Table

~A

mA

200
400

MIN,25°C
MAX
All

TEST CONDITIONS

MIN,25°C
MAX
MIN
25°C
MAX

VOUT = 2.5 V
V OUT = 4.5 V

V OUT

Inputs at 0 or 5 V per
the Logic Function or
Truth Table

=0.4 V

MIN,25°C
MAX
MIN,25°C
MAX
MIN,25°C
MAX
MIN,25°C
MAX

All Inputs at 0 V

All Inputs at 5 V

* Input Current and Quiescent Power Supply Current are relatively higher for this device because of active pull up circuits on all inputs except
IX. This is done for TTL compatibility.

3-116

FAIRCHILD CMOS· LSI • 34702

DC CHARACTERISTICS: V OD
SYMBOL

=15 V, VSS =0 V
LIMITS

PARAMETER

MIN

V IH
Input HIGH Voltage
---V IL
Input LOW Voltage

TYP

MAX

10.5
4.5

UNITS

TEMP

V

All

Guaranteed Input HIGH Voltage

All

Guaranteed Input LOW Voltage

V

14.99
V OH

Output HIGH Voltage

MIN,25°C
V

14.95
13.0
0.01

VOL

Output LOW Voltage

0.05

V

2.0

IlL'

IIH

IOH

Input LOW Current

XC

for Input IX

XM

Input LOW Current

XC

for all Other Inputs

XM

-0.02
-100
-100

Input HIGH Current

XC
XM

0.02

Input HIGH Current

XC

0.2

for all Other Inputs

XM

0.02

Outpul LOW Current

Quiescent
IDOL'

Supply
Current, LOW
Quiescent
Power

'DOH

Supply
Current, HIGH

XM

XC
XM

=0 rnA,

MIN,25°C

IOL

=0

MAX

Inputs at 0 or 15 V per the
Inputs at 4.5 or 10.5 V

rnA, Inputs at 0 or 15 V per the

Logic Function or Truth Table
IOL

= 0 rnA,

Inputs at 4.5 or 10.5 V

25°C

~A

25°C

Lead Under Test at 0 V
All Other Inputs Simultaneously at 15 V

0.2

-2.2

-4.4

-1.4

-2.8

mA

rnA

Lead Under Test at 15 V
All Other Inputs Simultaneously at 0 V

MIN,25°C
MAX
MIN

18.0

XC

IOH

~A

10.0

Power

= 0 rnA,

Logic Function or Truth Table

All

All

18.0
IOL

IOH

-0.2

for Input IX

Output HIGH Current

MAX

TEST CONDITIONS

VO UT
VO UT

= 14.5 V
= 0.5 V

Inputs at 0 or 15 V per
the Logic Function or
Truth Table

25°C
MAX

500

~A

1000
500

~A

1000
40

~A

240
40

~A

120

MIN,25°C
MAX
MIN,25°C

All Inputs at 0 V

MAX
MIN,25°C
MAX
MIN,25°C

All Inputs at 15 V

MAX

* Input Current and Quiescent Power Supply Current are relatively higher for this device because of active pull up circuits on all inputs except
IX. This is done for TTL compatibility.

3-117

FAIRCHILD CMOS • LSI • 34702

DC CHARACTERISTICS: V DD
SYMBOL

=10 V, VSS =0 V

PARAMETER

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

MIN

LIMITS
TYP

MAX

7.0
3.0

UNITS

TEMP

V

All

V

All

V

MIN,25°C
MAX
All

9.99
VO H

VOL

Output HIGH Voltage

Input LOW Current
IlL'

IIH

for Input IX
Input HIGH Current

Input HIGH Current

for all Other Inputs

10L

0.01
0.05
1.0

Output LOW Voltage

for Input IX
Input LOW Current
for all Other Inputs

10H

9.95
9.0

-0.1
-0.01

XC
XM
-60
-60

XC
XM
XC
XM

0.1
0.Q1
0.1

XC
XM

Output HIGH Current

Output LOW Current

V

All

~A

25°C

~A

25°C

mA

MIN,25°C
MAX

IDDL'

XC

Supply
Current, LOW

XM

Quiescent
Power

IDDH

Supply
Current, HIGH

XC
XM

Guaranteed Input HIGH Voltage
Guaranteed Input LOW Voltage

=

10H 0 mA, Inputs at 0 or 10 V per the
Logic Function or Truth Table

=0 mA. Inputs at 3 or 7 V
10L =0 mA. Inputs at 0 or 10 V per the
10H

Logic Function or Truth Table
10L

=0 mA, Inputs at 3 or 7 V

Lead Under Test at 0 V
All Other Inputs Simultaneously at 10 V

Lead Under Test at 10 V
All Other Inputs Simultaneously at 0 V

0.01
-1.4
-0.8

-2.8
-1.6

10.0

14.0
14.0

mA

7.0
Quiescent
Power

MIN,25°C
MAX

TEST CONDITIONS

MIN
25°C

VOUT
V OUT

=9.5 V
=0.5 V

Inputs at 0 or 10 V per
the Logic Function or
Truth Table

MAX

400
800
400
800
20
120
10
60

~A

MIN,25°C
MAX

~A

MIN,25°C
MAX

~A

~A

MIN,25°C
MAX
MIN,25°C
MAX

All Inputs at 0 V

All Inputs at 10 V

* Input Current and Quiescent Power Supply Current are relatively higher for this device because of active pull up circuits on all inputs except
lX- This is done for TTL compatibility.

3-118

FAIRCHILD CMOS • LSI • 34702

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VDD as shown, VSS

=0 V, TA =25°C

LIMITS
SYMBOL

PARAMETER

VDD
MIN

=5 V

TYP

VDD
MAX

MIN

= 10V

TYP

MAX

V D D- 15V
MIN

TYP

UNITS

TEST CONDITIONS

MAX

tpLH
tpHL

Propagation Delay,
IX to CO

105
105

55
55

35
35

ns
ns

tpLH
tpHL

Propagation Delay,
CP to CO

80
80

40
40

30
30

ns
ns

tpLH
tpHL

Propagation Delay,
CO to On

40
40

20
20

15
15

ns
ns

tpLH
tpHL

Propagation Delay,
CO TO Z

50
50

25
25

20
20

ns

tTLH
tTHL

Output Transition
Time

50
35

25
20

15
10

ns
ns

tpLH
tpHL

Propagation Delay,
IX to CO

150
150

75
75

55
55

ns
ns

tpLH
tpHL

Propagation Delay,
CP to CO

100
100

50
50

35
35

ns
ns

tpLH
tpHL

Propagation Delay,
CO to On

60
60

30
30

25
25

ns
ns

tpLH
tpHL

Propagation Delay,
COTOZ

70
70

35
35

25
25

ns
ns

tTLH
tTHL

Output Transition
Time

70
40

35
25

25
15

ns
ns

ts
th

Set-Up Time, Select to CO
Hold Time, Select to CO

150
-10

100
-7

75
-5

ns
ns

ts
th

Set-Up Time, 1M to CO
Hold Time, 1M to CO

150
-10

70
-7

50
-5

ns
ns

twCP(L)
twCP(H)

Minimum Clock Pulse Width,
LOW and HIGH

150
150

75
75

50
50

ns
ns

twiX(L)
twIX(H)

Minimum IX Pulse Width,
LOW and HIGH

150
150

75
75

50
50

ns
ns

CL = 15 pF
Input Transition
Times <; 20 ns

CL = 50 pF
Input Transition
Times <; 20 ns

CL = 15 pF
Input Transition
Times <; 20 ns

NOTES:

1.
2.

Propagation Delays and Output Transition Times are graphically described in this section under 34000 Series CMOS Family Characteristics.
Propagation Delays (tPLH and tPHL) and Output Transition Times (tTLH and tTHL) will change with Output Load Capacitance (eLL
Set-up Times (ts ), Hold Times (th), and Minimum Pulse Widths (tw) do not vary with load capacitance.

3.
4.

The first H IG H Level Clock Pulse after ECp goes LOW must be at least 350 ns long to guarantee reset of all Counters.
It is recommended that input rise and fall times to the Clock Inputs (CP, IX) be less than 15 fJ.s.

3-119

FAIRCHILD CMOS • LSI • 34702
SWITCHING WAVEFORMS

CP/I X

MINIMUM CP AND IX PULSE WIDTHS AND SET-UP AND HOLD TIMES,
SELECT INPUT (Sn) TO CLOCK OUTPUT (CO) AND 1M INPUT TO CLOCK OUTPUT (CO)
Note: Set-up and Hold Times are shown as positive values but may be specified as negative values.

APPLICATION
SINGLE CHANNEL BIT RATE GENERATOR

Figure 1 shows the simplest application of the 34702. This circuit generates one of five possible bit rates as determined by the setting of a single
pole, 5-position switch. The Bit Rate Output (Z) drives one standard TTL load or four low power Schottky loads over the full temperature
range_ The possible output frequencies correspond to 110, 150,300, 1200, and 2400 Baud. For many low cost terminals these five bit rates are

adequate.
SIMULTANEOUS GENERATION OF SEVERAL BIT RATES
Fixed Programmed Multichannel Operation
Figure 2 shows a simple scheme that generates eight bit rates on eight output lines, using one 34702 and one 93L34 8-Bit Addressable Latch.

This and the following applications take advantage of the built-in scan counter (prescaler) outputs. As shown in the block diagram, these
outputs (00 to 02) go through a complete sequence of eight states for every half-period of the highest output frequency (9600 Baudl. Feeding

these Scan Counter Outputs back to the Select Inputs of the multiplexer causes the 34702 to interrogate sequentially the state of eight
different frequency signals. The 93L34 8~Bit Addressable Latch, addressed by the same Scan Counter Outputs, reconverts the multiplexed
single Output (Z) of the 34702 into eight parallel output frequency signals. In the simple scheme of Figure 2, input S3 is left open (HIGH) and

the following bit rates are generated:
00:

110 Baud,

01:

9600 Baud,

02:

4800 Baud,

03:

1800 Baud,

04:

1200 Baud,

05:

2400 Baud,

06:

300 Baud,

07:

150 Baud.

Other bit rate combinations can be generated by changing the Scan Counter to Selector interconnection or by inserting logic gates into
this path.

Fully Programmable Multichannel Operation
Figure 3 shows a fully programmable 8~channel bit rate generator system that, under computer control, generates arbitrarily assigned bit rates
on all eight outputs simultaneously. The basic operation is similar to the previously described fixed programmed system, but two 9LS170 4 x 4
Register File MSI packages are connected as programmable look-up tables between the Scan Counter Outputs (00 to 02) and the multiplexer
Select Inputs (SO to S3). The content of this B-word by 4-bit memory determines which frequency appears at what output.
19200 Baud Operation
Though a 19200 Baud signal is not internally routed to the multiplexer, the 34702 can be used to generate this bit rate by connecting the 02

output to the 1M input and applying select code 0 or 1. An additional 2~input NAND gate can be used to retain the "Zero Baud" feature on
select code O. Any multichannel operation that involves 19200 Baud must be limited to four outputs as shown in Figure 4. Only the two least
significant Scan Counter Outputs are used, so that the scan is completed within one half period of the 19200 output frequency.
CLOCK EXPANSION

One 34702 can control up to eight output channels. For more than eight channels, additional Bit Rate Generators are required. These Bit Rate
Generators can all be run from the same crystal or clack input. Figure 5 shows one possible expansion scheme. One 34702 is provided with a
crystal. All other devices derive their clock from this master. Figure 6 shows a different scheme where the master clock output feeds into the I X
input of all slaves and all ECp inputs are normally held HIGH. This scheme retains the reset feature and the selection between two different
clock sources of the basic 34702 circuit.

During normal operation, the common ECp line is HIGH and the common clock line (CP) is LOW. For diagnostic purposes the common ECp is
forced LOW. This deselects the crystal frequency and initiates the diagnostic mode. When CP goes HIGH for the first time, all 34702s are reset

through their individual on~chip initialization circuitry. Subsequent
counter, causing all 34702s to operate synchronously.

LOW~to-HIGH

3-120

clock transitions on the common CP line advance the scan

FAIRCHILD CMOS • LSI • 34702
TYPICAL APPLICATIONS (Cant'd)

'a

56 pF

~f-PF_~~

........_ - ,

SWITCH POSITION

BIT RATE
110 Baud

1
2

150 Baud

3

300 Baud

4

1200 Baud

5

2400 Baud

Fig. 1 SWITCH SELECTABLE BIT RATE GENERATOR
CONFIGURATION PROVIDING FIVE BIT RATES

Fig. 2 BIT RATE GENERATOR CONFIGURATION
WITH EIGHT SIMULTANEOUS FREOUENCIES

I
56pF

~PF

~
~r'0

-L

Mn~

L

CP 1M

So 5, 8 2

53

ECp

34702
'x

, . Ox
CO

00

Q,

02

Z

2.4576 MHz

CRYSTAL

RE

LAO
-

A,

9LS170

°0

Q1

°2 °3

II

~'"
9LSOO

L-

D

93L34
E

°7
°6
°5
°4
°3
°2
0,

CHANNEL 6
CHANNEL 5

CHANNEL 4
CHANNEL 3
CHANNEL 2
CHANNEL 1
CHANNEL 0

CHANNEL 7

°0
0-A2
CL

RE

LAO

AO A,

9LS170

-

A,

°0

I

Q, °2 °3

II

II

L-

Fig. 3 A FULLY PROGRAMMABLE g·CHANNEL BIT RATE GENERATOR SYSTEM

3·121

FAIRCHILD CMOS • LSI • 34702
TYPICAL APPLICATIONS

J

1/40F A
9LSOO

0,M
CP

So 5, 52 S3

2.4576 MHz

56 pF

CRYSTAL

--0 ECp

fiM1l.TI
~L-

~PF

O

34702

'X

Ox
CO

00 0, 02

Os , . . -

a

°41--

RE

LAO
A,

0, , . . -

°6 ,..-

l

I
'--

Z

L L

93L34 03

°2

E
9LS170

00 0,

0,

02 03

II

°0
eLp-

L-

AO A, A2

I J

1

Fig. 4 FULLY PROGRAMMABLE 4·CHANNEL BIT RATE GENERATOR SYSTEM WITH THE 19.2 k BAUD FEATURE.

I I I 11
CP 1M

56pF

1=

-1
56pF

It

So 5, 52 53

Eep

r10

Mn

~
~

34702

rl

'x

Q,

Ox co 00

02

Z

I I I I I

2.4576 MHz

CRYSTAL

I I I I I
t-----Icp

CP 1M

1M

'x

So 5, 52 53

Eep

,......-~OIEep

34702

34702

'x

-

Ox co

Ox

CO 00

Q,

02

Z

I II I I

I I I I I
CP 1M

So

5, 52 53

Eep
34702

-

'x
Ox

CO 0 0 0, 02

Z

I I I I I
I I I LI
CP 1M

So. 5,

52 53

Eep

r - -.......DlEcp

34702

34702

'x

'x

-

Ox co
TERNAL

(EXCLoCK

Fig. 5 CASCADE CLOCK EXPANSION SCHEME

MODE

)

(CONTROL)

Ox CO °0

Q,

02

Z

I I I I I

Fig. 6 TANDEM CLOCK EXPANSION SCHEME

3·122

FAIRCHILD CMOS • LSI • 34702
CRYSTAL SPECIFICATION RECOMMENDATIONS - Table 3 is a convenient listing of recommended crystal specifications.
Crystal manufacturers are also listed below.

TABLE 3 CRYSTAL SPECIFICATIONS
PARAMETERS

COMMERCIAL CRYSTAL SPEC

Frequency

2.4576 MHz "AT" Cut
250

Series Resistance (MaxI

n

-6.0 dB (Min)

Unwanted Modes
Type of Operation

Parallel

Load Capacitance

32 pF ±0.5

CRYSTAL MANUFACTURERS
CTS Knights, Inc.
Sandwich, III. 60548
(815) 786·8411

x - Tron Electronics
1869 National Ave.
Hayward, Calif.
(415) 783·2145
Erie Frequency Control
499 Lincoln St.
Carlisle, Pa. 17013
(717) 249-2232
International Crystal Mfg. Company
10No. Lee
Oklahoma City, Okla. 73102
(405) 236-3741

3·123

34720
256~B!T

RANDOM ACCESS MEMORY WITH 3-STATE OUTPUTS
FAIRCHILD CMOS. LSI

DESCRIPTION - The 34720 is a 256-8it Random Access Memory with 3-State Outputs. It has a Data
Input (D), eight Address Inputs (AO-A?), an active HIGH Write Enable Input (WE), an active LC)W
Chip Select Input (CS), an active HIGH 3-State Output (Q) and an active LOW 3-State Output (Q).
Information on the Data Input (D) is written into the memory location selected by the Address Inputs
(AO-A7) when the Chip Select Input (CS) is LOW and the Write Enable Input (WE) is HIGH. Under

LOGIC SYMBOL

these conditions, the device is transparent, i.e. the data input is reflected at the True and
Complementary Outputs (0, Q). Information is read from the memory location selected by the
Address Inputs (AO-A7) while the Chip Select (Cs) and the Write Enable (WE) Inputs are LOW. The Q

Output is the information written into the memory, Q is its complement. When the Chip Select Input
(CS) is HIGH, both Outputs (Q, Qj are held in the high impedance OFF state. This allows other

16

15

"

3-State outputs to be wired together in a bus arrangement. The 34720 offers fully static operation.
o
•
•
~

o
•
•

3-STATE OUTPUTS
ORG,l'.NI2ATlON - 256 WORDS Xl-BIT
ON-CHIP OECODING
TRUE AND COMPLEMENT OUTPUTS AVAILABLE
FULLY STATIC
LOW POWER DISSIPATION
HIGH SPEED

10

PIN NAMES
CS
Chip Select Input (Active LOW)
Write Enable Input
WE
o
Data Input
Address Inputs
AO-A7
3-State Output (Active HIGH)
Q
3-State Output (Active LOW)
Q

11

13

V OD =Pin5
VSS = Pin 8
NC

MODE SELECTION
WE

CS
L

H

L

L

X

H

14

Q

MODE

Complement of
Data Written
into Memory

Write

Q

Data Written
Into Memory

Data Written

Data Written

4

CONNECTION DIAGRAM
DIP (TOP VIEW)

Complement Clf

Into Memory

= Pin

Read

Into Memory

High

High
Impedance

Impedance

Inhibit

BLOCK DIAGRAM
16
'0

A,
"A,

~
,

,~m" ~
INPUT

VOD""Pin5

,
DECODFR

~

16x16
MATRIX

VSS

=

NC

Pin'4

=

15

Pin 8
14

0= Pin Number

13

"
11

~1C/~~

10

'---r--'

OUTPUT

BUFFER

Note:

The Flatpak version has the

same pinouts (Connection Diagram)
as the Dual I n-Line Package.

3-124

FAIRCHILD CMOS • LSI • 34720
DC CHARACTERISTICS: V DD as shown, VSS = 0 V
LIMITS
SYMBOL

PARAMETER

=5 V

V DD

MIN

TYP

VDD~15V

V DD =10V

MAX

MIN

TYP

MAX

MIN

TYP

Output OFF
Current, HIGH

0.05
3.0

0.1
6.0

0.2
12

IOZL

Output OFF
Current, LOW

-0.05
-3.0

-0.1
--6.0

-0.2
-12

0.5
30
0.5

2
60

IDD

Quiescent
Power
Supply
Current

4
120
4
120

IOZH

XC
XM

2
60

30

UNITS

TEMP

TEST CONDITIONS

IJA

MIN,25°C
MAX

Output Returned

~A

MIN,25°C
MAX

Output Returned

MIN,25°C
MAX
MIN,25°C
MAX

All inputs common
and at 0 Vor V DD

MAX

~A
~A

to V DD ,

ES =V DD

to V SS ' CS

=V DD

Note: Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Characteristics.

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VDD as shown, VSS = 0 V, TA = 25°C
LIMITS
SYMBOL

PARAMETER

VDD

MIN

=5 V

TYP

V DD

MAX

MIN

=10 V

TYP

MAX

VDD

MIN

=15 V

TYP

UNITS

TEST CONDITIONS

MAX

tpLH
tpHL

READ MODE
Propagation Delay,
Address to Output

200
200

100
100

75
75

ns
ns

CL =15 pF
Input Transition
Times,;; 20 ns

tpZH
tpZL

Enable Time,
CS to Output

125
125

60
60

40
40

ns
ns

RL
RL

tpHZ
IpLZ

Disable Time,
CS to Output

125
125

60
60

40
40

ns
ns

tTLH
tTHL

Output Transition
Time

40
40

20
20

15
15

nS
ns

tpLH
tpHL

WRITE MODE
Propagation Delay,
WE to Output

125
125

60
60

40
40

ns
ns

tpLH
tpHL

READ MODE
Propagation Delay,
Address to Output

250
250

125
125

100
100

ns
ns

CL =50 pF
Input Transition
Times,;; 20 ns

tpZH
tpZL

CS

Enable Time,
to Output

150
150

70
70

50
50

ns
ns

RL
RL

tpHZ
tpLZ

Disable Time,
CS to Output

150
150

70
70

50
50

ns
ns

tTLH
tTHL

Output Transition
Time

75
75

35
35

25
25

ns
ns

tpLH
tpHL

WRITE MODE
Propagation Delay,
WE 10 Output

150
150

70
70

50
50

ns
ns

twWE

WRITE MODE
Minimum WE Pulse Width

100

80

60

ns

ts
th

Set-Up Time, D to WE
Hold Time, D to WE

50
40

20
20

15
15

ns
ns

Is
th

Set-Up Time, Address to WE
Hold Time, Address to WE

50
40

20
20

15
15

ns
ns

Is
Ih

Set-Up Time, CS to WE
Hold Time, CS to WE

50
40

20
20

15
15

ns
ns

=1 kn to VSS
=1 kn to V DD
RL =1 kn to VSS
RL =1 kn toV DD

=1 kn toVS S
=1 kn to VDD
RL =1 kn to VSS
RL =1 kn to V DD

CL = 15 pF
Input Transition
Times';; - 20 ns

NOTES:

1.
2.

Propagation delays and output transition times are graphically described in this section under 34000 Series CMOS Family Characteristics.
Propagation Delays (tPLH and tPHLl and Output Transition Times (tTLH and tTHLl will change with output load capacitance (eL). Set-up
Times (t s ), Hold Times (th), Minimum Pulse Widths (tw) do not vary with toad capacitance.

3-125

FAIRCHILD CMOS • LSI • 34720
SWITCHING WAVEFORMS

READ MODE

50%

50%

90%
~

_tpHZ

OUTPUT

--

,

J~

HIGH Z
"

Q"'F

..... -

-

-

o
OUTPUT

05 VOO

STATE /

-

--{~~""

"OFF" STATE

10%

~-------------O V

CS TO OUTPUT ENABLE AND DISABLE TIMES

WRITE MODE
......-twWE~

~ 50%

v,0%

WE

-

~

J
t,

~V50%

.

r

th

50%\~

]~

J~
.......--t

~th~ .....

5_ _ _ . .

)V50%

50,K

jr\,.

_----i}~
~th~

_~ts~

{,----50%

MINIMUM PULSE WIDTH FOR WE AND SET-UP AND HOLD TIMES,
o TO WE, An TO WE, AND CS TO WE

Note: Set-up and Hold Times are shown as positive values but may be specified as negative values.

3-126

\i'"

/,. - :-G;; - ",- --------VOD

/

0.5 VOO

'-----

34723
DUAL 4-BIT ADDRESSABLE LATCH
DESCRIPTION - The 34723 is a Dual 4-Bit Addressable Latch with common control inputs; these
include two Address Inputs (AO, Al), an active LOW Enable Input (E) and an active HIGH Clear Input
(CL). Each latch has a Data Input (D) and four Outputs (00-031.

LOGIC SYMBOL

When the Enable (E) and Clear (CLl Inputs are HIGH, al.l Outputs (00-03) are .hOW. Dual 4-channel
demultiplexing occurs when the Clear Input (CLl is HIGH and the Enable Input (E) is LOW.
When the Clear (CLl and Enable (E) inputs are LOW, the selected Output (00-03),~etermined by the
Address Inputs (AO, Al), follows the Data Input (D)' When the Enable Input (E) goes HIGH, the
contents of the latch are stored. When operating in the addressable latch mode (1' = CL = LOW),
changing more than one bit of the address (AO, A1) could_ impose a transient wrong address.
Therefore, this should only be done while in the memory mode (E = HIGH, CL = LOW).

I
VOD :=: Pin 16
VSS = Pin 8

•
•
•
•
•
•

CONNECTION DIAGRAM
DIP (TOP VIEW)

SERIAL· TO-PARALLEL CAPABI LlTY
OUTPUT FROM EACH STORAGE BIT IS AVAILABLE
RANDOM (ADDRESSABLE) DATA ENTRY
ACTIVE HIGH DECODING OR DEMULTIPLEXING CAPABILITY
EASILY EXPANDABLE
ACTIVE HIGH COMMON CLEAR

PIN NAMES
AO,Al
D a , Db

E
CL
00a- 0 3a, °Ob- 0 3b

Address Inputs
Data Inputs
Enable Input (Active LOW)
Clear Input (Active HIGH)
Parallel Latch Outputs

Note: The Flatpak version has the
same pinouts (Connection Diagram)
as the Dual In-Line Package,

LOGIC DIAGRAM

Voo = Pin 16
VSS = Pin 8

0= Pin Numbers
3-127

FAIRCHILD CMOS • 34723
MODE SELECTION

E

CL

L

L

Addressable Latch

H

L

Memory

L

H

Dual 4-Channel Demultiplexer

H

H

Clear

MODE

H = HIGH Level
L = LOW Level

TRUTH TABLE
CL

E

D

AO

Al

00

H

H

X

X

X

H

L

L

L

L

H

L

H

L

L

H

L

L

H

L

H

L

H

H

H

L

L

H

L

H

MODE

01

°2

03

L

L

L

L

Clear

L

L

L

L

Demultiplex

H

L

L

L

L

L

L

L

L

L

H

L

L

L

H

L

L

L

L

H

L

H

L

L

H

L

L

L

H

H

L

L

L

L

H

L

H

H

H

L

L

L

H

ON-I

ON-I

ON-I

Memory

L

H

X

X

X

°N-1

L

L

L

L

L

L

ON-I

ON-I

ON-I

Addressable

L

L

H

L

L

H

ON_1

ON-I

Latch

L

L

L

H

L

ON-I

ON-I
L

ON-I

ON-I

ON-I
L

ON-I

L

L

H

H

L

ON-I

H

L

L

L

L

H

ON-I

ON-1

L

L

H

L

H

ON-I

ON-I

H

L

L

L

H

H

ON-I

ON-I

ON-I

ON-I
L

L

L

H

H

H

ON-I

ON-I

ON-I

H

ON-I

L
LOW Level
H
HIGH Level
X
Don't Care
ON-I ~ State before the positive
transition of the Enable Input

DC CHARACTERISTICS: VD D as shown, VSS

=0

V

-LIMITS

SYMBOL

PARAMETER

V DD - 5 V
MIN

Ouiescent
Power
IDD

Supply
Current

XC
XM

TYP

VD D - 1OV
MAX

MIN

TYP

VD D - 15V

MAX

MIN

TYP

10

20

4

100

200

40

1

2

0.4

15

30

6

UNITS

TEMP

~A

~A

MIN,25°C
MAX

~25OCj

Note: Additional DC Characteristics are listed in this section under 34000 Serles CMOS Family Characteristics.

3-128

TEST CONDITIONS

MAX

MAX

All inputs common
and at 0 V or VOO

FAIRCHILD CMOS· 34723
AC CHARACTERISTICS AND SET-UP REQUIREMENTS: V DD as shown, VSS = 0 V, TA = 25°C
LIMITS
SYMBOL

V DD

PARAMETER

MIN

=5 V

TYP

Propagation Delay,

V DD
MAX

MIN

= 10V

TYP

MAX

V DD
MIN

= 15 V

TYP

UNITS

tpLH
tpHL

E to On

90
90

40
40

30
30

ns
ns

tpLH
tpHL

Propagation Delay,
D toOn

75
75

35
35

25
25

ns
ns

tpLH
tpHL

Propagation Delay,
Address to On

100
100

45
45

35
35

ns
ns

tpHL

Propagation Delay, CL to On

75

35

25

ns

tTLH
tTHL

Output Transition
Time

40
40

20
20

15
15

ns
ns

tpLH
tpHL

E toOn

110
100

50
50

35
35

ns
ns

tpLH
tpHL

Propagation Delay,
D to On

95
95

45
45

30
30

ns
ns

tpLH
tpHL

Propagation Delay,
Address to On

120
120

55
55

40
40

ns
ns

Propagation Delay,

TEST CONDITIONS

MAX

tpHL

Propagation Delay, CL to On

95

45

30

ns

tTLH
tTHL

Output Transition
Time

75
75

40
40

25
25

ns
ns

ts
th

Set-Up Time, D to E
Hold Time, D to E

30
40

10
20

5
20

ns
ns

ts
th

Set-Up Time, Address to E
Hold Time, Address to E

30
40

10
20

5
20

ns
ns

twE

Minimum E Pulse Width

50

20

15

ns

twCL

Minimum CL Pulse Width

50

20

15

ns

CL = 15 pF
Input Transition
Times" 20 ns

CL = 50 pF
Input Transition
Times" 20 ns

CL = 15 pF
Input Transition
Times" 20 ns

NOTES:

1.

Propagation delays and output transition times are graphically described in this section under 34000 Series CMOS Family Characteristics.

2.

Propagation Delays (tPLH and tPHL) and Output Transition Times (tTLH and tTHLJ will change with output load capacitance (eL)' Set-up
Times (ts ), Hold Times (th), and Minimum Pulse Widths (twl do not vary with load caPacitance.

SWITCHING WAVEFORMS

#..,..

'h

J

/17777?

50

'----_-J

~

/50%

CL _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

'L

MINIMUM PULSE WIDTH FOR E AND CL AND SET-UP
AND HOLD TIMES, D TO E AND An TO E

3-129

NOTES:
1. Set-up and Hold Times are shown as positive values but may
be specified as negative values.

2.

The Address to Enable Set-up Time is the time before the
HIGH-to-LOW Enable transition that the Address must be
stable so that the correct latch is addressed and the other
latches are not affected.

34725
64-81T (16 x 4) RANDOM ACCESS MEMORY
WITH 3-STATE OUTPUTS
DESCRIPTION - The 34725 is a 64-Bit Random Access Memory with 3-State Outputs organized as
16 words by four bi~ith four Data Inputs (00-03), fourl~ddress Inputs (AO-A3), an active LOW
Write Enable Input (WE), an active LOW Chip Select Input (CS) and four active LOW 3-State Outputs

LOGIC SYMBOL

(00-0 31.
Information on the four Data Inputs (DO-D3) is written into the memory location selectec!..EY the
Address Inputs (AO-A3) when both the Chip Sel~ct!nput (CS) and the Write Enable Input (WE) are
LOW. Under these conditions, the Outputs (QO-Q3) are held in a high impedance OFF state.
Information is~ad from the memory location selected bY..!!'e Address Inputs (AO-A3l_while the Chip
Select Input (CS) is LOW and the Write Enable Input (WE) is HIGH. The Outputs (Q0:93) are the
complement of the information written into the memory. When the Chip Select Input (CS) is HIGH,
all Outputs (00-03) are held in the high impedance OFF state. This allows other 3-State outputs to be

4

6

10

12

3

wired together in a bus arrangement. The 34725 offers fully static operation.
34725

•
•
•
•
•

3-STATE OUTPUTS
ORGANIZATION - 16 WORDS X 4 BITS
ON-CHIP DECODING
INVERTED DATA OUTPUT
FULLY STATIC OPERATION

PIN NAMES
CS
WE

00- 0 3
AO-A3

00-0 3

CS
Chip Select Input (Active LOW)
Write Enable Input (Active LOW)
Data Inputs
Address Inputs
3-State Outputs (Active LOW)

5

MODE SELECTION
OUTPUTS

WE

9

11

MODE

L

High Impedance

Write

L

H

Outputs are Complement of
Data Written into Location

Read

H

X

High Impedance

L

7

Voo = Pin 16
Vss = Pin 8

Inhibit

CONNECTION DIAGRAM
DIP (TOP VIEW)

LOGIC DIAGRAM

16
15
14

""CD
A1 @

A2 @I
A3

@

···•••......

13
16 X 4

12

ARRAY

MEMORY
CELL

11
10

Voo = Pin 16
Vss = Pin 8
= Pin Number

Note:

The Flatpak version has the

same pinouts (Connection Diagram)

o

as the Dual In-Line Package.

3-130

FAIRCHILD CMOS • 34725
DC CHARACTERISTICS: VDD as shown, VSS = 0 V
LIMITS
SYMBOL

V DD = 5 V

PARAMETER

MIN

TYP

V DD =15V

V DD=10V
MAX

TYP

MIN

MIN

MAX

TYP

UNITS

TEMP

TEST CONDITIONS

MAX

'OZH

Output OFF
Current HIGH

0.05
3.0

0.1
6.0

0.2
12.0

~A

MIN,25°C
MAX

Output Returned
to VDD ' CS = VDD

'OZl

Output OFF
Current LOW

-0.05
-3.0

-0.1
-6.0

-0.2
-12.0

~A

MIN,25°C
MAX

Output Returned
to V SS ' CS = V DD

Quiescent
Power
Supply
Current

2.5
15
2.5
15

5
30
5
30

10
60
10
60

MIN,25°C
MAX
MIN,25°C
MAX

All inputs common
and at 0 Vor VOO

'00

XC
XM

~A
~A

Note: Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Characteristics.

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VDD as shown, VSS = 0 V, TA = 25°C

SYMBOL

PARAMETER

LIMITS
V DD = 10V

VDD = 5 V
MIN

TYP

MAX

MIN

TYP

MAX

VDD=15V
MIN

TYP

UNITS

TEST CONDITIONS

MAX

tplH
tpHL

READ MODE
Propagation Delay,
Address to Output

180
180

70
70

50
50

ns
ns

Cl = 15 pF
Input Transition
Times..;; 20 ns

tpZH
tpZl

CS

Enable Time,
to Output

135
135

60
60

45
45

ns
ns

Rl =lkntoVsS
RL = 1 k n to VDO

tpHZ
tpLZ

Disable Time,
CS to Output

135
135

60
60

45
45

ns
ns

RL = 1 kntoVsS
RL = 1 k n to V OD

tTLH
tTHL

Output Transition
Time

40
40

20
20

15
15

ns
ns

tpZH
tpZL

WRITE MODE
Enable Time
WE to Output

135
135

60
60

45
45

ns
ns

RL = 1 kn to VSS
RL = 1 kn toV DD

tpHZ
tpLZ

Disable Time,
WE to Output

135
135

60
60

45
45

ns
ns

RL = 1 kn to VSS
RL = 1 kn toV DD

tpLH
tpHL

READ MODE
Propagation Delay,
Address to Output

200
200

95
95

70
70

ns
ns

CL - 50 pF
Input Transition
Times";; 20 ns

tpZH
tpZL

Enable Time,
CS to Output

150
150

70
70

50
50

ns
ns

RL = 1 kn VSS
RL = 1 kn V DD

tpHZ
tpLZ

Disable Time,
CS to Output

150
150

70
70

50
50

ns
ns

RL = 1 UHo VSS
RL = 1 k n to VDD

tTLH
tTHL

Output Transition
Time

75
75

35
35

25
25

ns
ns

tpZH
tpZL

WRITE MODE
Enable Time,
WE to Output

150
150

70
70

50
50

ns
ns

RL = 1 kn to VSS
RL = 1 kn to V DD

tpHZ
tpLZ

Disable Time,
WE to Output

150
150

70
70

50
50

ns
ns

RL = 1 kn to VSS
RL = 1 kn to VDD

twWE

WRITE MODE
Minimum WE Pulse Width

180

100

80

ns

ts
th

Set-Up Time, On to WE
Hold Time, On to WE

150
40

120
20

115
15

ns
ns

ts
th

Set-Up Time, Address to WE
Hold Time, Address to WE

150
40

120
20

115
15

ns
ns

ts
th

Set-Up Time, CS to WE
Hold Time, CS to WE

150
40

120
20

115
15

ns
ns

CL = 15 pF
Input Transition
Times";; 20 ns

NOTES:
Propagation Delays and Output Transition Times are graphically described in this section under 34000 Series CMOS FamilY Characteristics.
Propagation Delays (tPLH and tpHL) and Output Transition Times (tTLH and tTHL) will change with Output Load Capacitance (eL).
Set-up Times (ts ), Hold Times (th), and Minimum Pulse Widths (tw) do not vary with load capacitance.

1.
2.

3-131

FAIRCHILD CMOS • 34725
SWITCHING WAVEFORMS

READ MODE
50%

50%

~

~
OUTPUT

90%

~
PZL

HIGH Z
"OFF" STATE

--- -HIGH Z
"OFF" STATE

0.5 V DD

~---_..J-OV

-VOD
V
0.5 DO

'--

CS TO OUTPUT ENABLE AND DISABLE TIMES

WRITE MODE
50%

~

~
OUTPUT

90%

50%

50%

I~,­

HIGH Z
"OFF" STATE

0.5 V DD

~ ----..J-OV

~

PZL

WE TO OUTPUT ENABLE AND DISABLE TIMES

MINIMUM WE PULSE WIDTH AND SET-UP AND HOLD TIMES,
On TO WE, An TO WE, AND CS TO WE
Note: Set-up and Hold Times are shown as positive values but

may be specified as negative values,

3-132

~

----HIGH Z
"OFF" STATE

-V OD
V
0.5 DO

'---

340085
4-81T MAGNITUDE COMPARATOR
DESCRIPTION - The 340085 is a 4-8it Magnitude Comparator which compares two 4-bit words
(A, 8), each word having four Parallel Inputs (AO-A3,80-83); A3,83 being the most significant inputs.
Operation is not restricted to binary codes, the device will work with any monotonic code. Three
Outputs are provided: "A greater than 8" (OA>8), "A less than 8" (OA<8), "A equal to 8"
(OA=8). Three Expander Inputs, IA>8, IA<8, IA=8, allow cascading without external gates. For
proper compare operation the Expander Inputs to the least significant position must be connected as
follows: IA<8 = IA>8 = L, IA=8 = H. For serial (ripple) expansion, the 0A>8, 0A<8 and 0A=8
Outputs are connected respectively to the IA>8, IA<8, and IA=8 inputs of the next most significant
comparator, as shown in Figure 1. Refer to Applications section of data sheet for high speed method
of comparing large words.

The Truth Table on the following page describes the operation of the 340085 under all possible logic

LOGIC SYMBOL

10

7

2

15

11

9

1

14

conditions. The upper 11 lines describe the normal operation under all conditions that will occur in a
single device or in a series expansion scheme. The lower five lines describe the operation under
abnormal conditions on the cascading inputs. These conditions occur when the parallel expansion
technique is used.

•
•

EASILY EXPANDABLE
BINARY OR BCD COMPARISON

•

0A>B, 0A8, IA<8, IA=8
°A>B
°A<8
°A=8

Word A Parallel Inputs
Word 8 Parallel Inputs
Expander Inputs
A Greater than 8 Output
A Less than 8 Output
A Equal to 8 Output

VDD

::=:

VSS

= Pin

Pin 16
8

LOGIC DIAGRAM

CONNECTION DIAGRAM
DIP (TOP VIEW)

A,

~o----,-t;:>o-P-r,

@

o----o~

8, CD",l'-{>o-J-r.::>o-h-LJ

0AB

13
12

11

AO~·o----,-D~~~~------t1-r~

10

VOO = Pin 16
BO

IA>B

VSS = Pin 8
= Pin Number

@

0~'.4>~-c~

-=

o

____________~~~~r-----~

'A~-C~____________f=l:*~~r--------'
Note: The Flatpak version has the
same pinouts (Connection Diagram)
as the Dual 1n-Line Package.

3-133

•

FAIRCHILD CMOS • 340085
TRUTH TABLE
CASCADING
INPUTS

COMPARING INPUTS

OUTPUTS

Aa,Ba

A2,B2

AO,BO

IA>B

IAB

°AB3

X

X

X

X

X

X

H

L

L

A3B2

X

X

X

X

X

H

L

L

A3=B3

A2B1

X

X

X

X

H

L

L

A3=B3

A2=B2

AlBO

X

X

X

H

L

L
L

Al,Bl

A3=B3

A2=B2

Al=Bl

AOB

A>8

°AS

L - IAS

I---

A 19 -

AO A, A2 A3 BO
IA>S

°AB

340085

°AB

' 4 - iAB
°AB

',-

IAB OA<'l
0A=B -NC

A 14 -

IA>S

8 14 -

IAB
340085

#2

°A=B i-NC

IA=a

J
I
AO A,

J
A2 A3 80

IA>B

IA8

OUTPUTS

340097 • 340098
3-STATE HEX NON-INVERTING AND INVERTING BUFFERS

DESCRIPTION - These two CMOS buffers provide high current output capability suitable for driving
high capacitance loads. The 340097 is a Non~lnverting CMOS Buffer with 3~state outputs and the
340098 is an Inverti ng CMOS Buffer with 3-5tate outputs. The 3-5tate outputs of each device are
controlled by two Enable Inputs (E04, E02). A HIGH on Enable Input E04 causes the Outputs of
four of the six buffer elements to assume a high impedance or OF F state, regardless of other input

CONNECTION DIAGRAM
OIP (TOP VIEW)

16

conditions and a HIGH on Enable Input E02 causes the Outputs of the remaining two buffer elements
to assume a high impedance or OFF state, regardless of other input conditions.

15
14

•
•
•

13

3-STATE OUTPUTS
TTL COMPATIBLE - FAN OUT OF ONE TTL LOAD
ACTIVE LOW ENABLE INPUTS

12
11

10

NOTE:

PIN NAMES
1A-6A
E04, E02
1X-6X

The

Buffer Inputs
Enable Inputs (Active LOW)
Buffer Outputs (Active HIGH for the 340097 and Active LOW for the 340098)

340097 LOGIC DIAGRAM

2

4

6

has the same

340098 LOGIC OIAGRAM

lA

2

2A

4

3A

6

o

F latpak version

pinouts (Connection Diagram) as the
Dual 1n" Line Package.

= Pin

lA

2A

3A

o

Numbers

3-136

=

Pin Numbers

FAIRCHILD CMOS • 340097 • 340098
DC CHARACTERISTICS: VDD as shown, VSS = 0 V
LIMITS
SYMBOL

V DD = 10 V

VDD = 5 V

PARAMETER

MIN

TYP

MAX

MIN

TYP

VDD = 15 V
MIN

MAX

TYP

UNITS

TEMP

TEST CONDITIONS

MAX

ISc(HI

Output Short
Circuit Current

-4.35

-20

mA

All

VIN = VDD or VSS per
Function, VO UT = VSS

ISc(LI

Output Short
Circuit Current

4.35

20

mA

All

VIN = VDD or VSS per
Function, VO UT = VDD

IOH

Output HIGH
Current

-1.6
Note
2

mA

All

VO UT = 2.4 V,
Inputs at 0 V or V DD
per Function

IOL

Output LOW
Current

1.6
Note
2

mA

All

VOUT= 0.4 V,
Inputs at 0 V or VDD
per Function

IOZH

Output OFF
XC
Current HIGH

0.5
7

0.5
7

0.05
3

0.05
3

~A

MIN,25°C
MAX
MIN,25°C
MAX

Output Returned
to VDD , EOn = VDD

XM

0.5
7
0.05
3

Output OFF
XC
Current LOW

-0.5
-7

-0.5
-7

MIN,25°C
MAX

Output R~urned
to VSS' EOn = VD D

-0.05
-3

-0.05
-3

~A

XM

-0.5
-7
-0.05
-3

3
42
0.3
20

5
70
0.5

IOZL

Quiescent
IDD

Power
Supply
Current

XC
XM

30

MIN,25°C
MAX

1
14

~A

MIN,25°C
MAX

0.1
6

~A

MIN,25°C
MAX

All inputs common
and at 0 V or VDD

NOTES:
1. Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Characteristics.
2.

For IOH and IOL tests, VOO = 4.5 V for military grade product and VDO = 4.75 V for commercial grade product.

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: V DD as shown, VSS = 0 V, TA = 25°C, 340097 only
LIMITS
SYMBOL

PARAMETER

VDD = 5 V
MIN

TYP

VDD = 10 V
MAX

MIN

TYP

MAX

VD D = 15 V
MIN

TYP

UNITS

TEST CONDITIONS

MAX

tpLH
tpHL

Propagation Delay,
Data to Output

45
45

22
22

18
18

ns
ns

CL = 15 pF
Input Transition Times.;; 20 ns

tpZH
tpZL

Output Enable
Time

60
85

30
35

25
28

ns
ns

RL = 1 kn to VSS
RL = 1 kn to VDD

tpHZ
tpLZ

Output Disable
Time

35
55

28
33

25
27

ns
ns

RL = 1 kn to VSS
RL = 1 kn to VD D

tTLH
tTHL

Output Transition
Time

25
25

15
15

10
10

ns
ns

tpLH
tpHl

Propagation Delay,
Data to Output

65
65

28
28

20
20

ns
ns

CL = 50 pF
Input Transition Times';; 20 ns

tpZH
tpZL

Output Enable
Time

70
95

35
40

29
30

ns
ns

RL = 1 kn to VSS
RL = 1 k n to V DD

IpHZ
tpLZ

Output Disable
Time

40
60

31
35

29
30

ns
ns

Rl = 1 kn to VSS
RL = 1 kn to V DD

tTLH
tTHL

Output Transition
Time

40
40

20
20

15
15

ns
ns

NOTE:
1. Propagation Delays and Output Transition Times are graphically described in this section under 34000 Series CMOS Family Characteristics.

3-137

FAIRCHILD CMOS • 340097 • 340098
AC CHARACTERISTICS AND SET-UP REQUIREMENTS: V DD as shown, VSS = 0 V, TA = 25°C, 340098 only
LIMITS
SYMBOL

V DD = 5 V

PARAMETER

MIN

TYP

V DD =10V
MAX

MIN

TYP

MAX

VDD =15V
MIN

TYP

UNITS

TEST CONDITIONS

MAX

tpLH
tpHL

Propagation Delay,
Data to Output

45
45

30
30

25
25

ns
ns

CL = 15pF
Input Transition Times.;; 20 ns

tpZH
tpZL

Output Enable
Time

60
85

30
35

25
28

ns
ns

RL =1kntoV sS
RL = 1 kntoV DD

tpHZ
tpLZ

Output Disable
Time

35
55

28
33

25
27

ns
ns

RL = 1 kn to VSS
RL = 1 k n to V DD

tTLH
tTHL

Output Transition
Time

25
25

15
15

10
10

ns
ns

tpLH
tpHL

Propagation Delay,
Data to Output

75
75

35
35

30
30

ns
ns

CL = 50 pF
Input Transition Times';; 20 ns

tpZH
tpZL

Output Enable
Time

70
95

35
40

29
30

ns
ns

RL = 1 kn toVSS
RL = 1 kn to VDD

tpHZ
tpLZ

Output Disable
Time

40
60

31
35

29
30

ns
ns

RL = 1 kn toV SS
RL = 1 kn to V DD

tTLH
tTHL

Output Transition
Time

40

40

20
20

15
15

ns
ns

SWITCHING WAVEFORMS

50%

~
90%

,

tPHZ

--

HIGH Z
"OFF"STATE

r-tPZH

~t:Z_
/'

jO.5V OO
.I

10%

..... - - - - " " - - O V

OUTPUT

OUTPUT ENABLE TIME
ItPZH) AND OUTPUT DISABLE TIME (tpHzi

~r

-=:i ~:~
r-...

EOn

OUTPUT

50%

50%

-

HIGHZ
"OFF" STATE

,

05V OO
~

OUTPUT ENABLE TIME
(tpZLi AND OUTPUT DISABLE TIME (tpLzi

3-138

340160 · 340161 · 340162 · 340163
4-81T SYNCHRONOUS COUNTERS
DESCRIPTION - The 340160 and the 340162 are fully synchronous edge-triggered 4-Bit Decade
Counters. The 340161 and the 340163 are fully synchronous edge-triggered 4-Bit Binary Counters.
Each device has a Clock Input (CP); four synchronous Parallel Data Inputs (PO-P3); three synchronous
Mode Control Inputs, Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable trickle
(CET); Buffered Outputs from all four bit positions (QO-Q3); and a Terminal Count Output (TC). The
340162 and 340163 have an additional synchronous Mode Control Input, Synchronous Reset (SR).
Alternately, the 340160 and 340161 have an overriding asynchronous Master Reset (MRI.
Operation is fully synchronous (except for Master Reset on the 340160 and 340161) and occurs on
the LOW-to-HIGH transition of the Clock Input (CP). When the Parallel Enable ·Input (PE) is LOW,
the next LOW-to-HIGH transition of the Clock Input (CP) loads data into the counter from Parallel
Inputs (PO-P3)' When the Parallel Enable Input (PE) is HIGH, the next LOW-to-HIGH transition of the
Clock Input (CP) advances the counter to its next state only if both Count Enable Inputs (CEP and
CET) are HIGH; otherwise, no change occurs in the state of the counter. The Terminal Count Output
(TC) is HIGH when the state of the counter is nine (QO = Q3 = HIGH, Q1 = Q2 = LOW) for the
340160 and 340162/fifteen (Qo = 01 = 02 = Q3 = HIGH) for the 340161 and 340163 and the Count
Enable Trickle Input (CET) is HIGH. For the 340162 and 340163, a LOW on the Synchronous Reset
Input (SR) sets all Outputs (00-03 and TC) LOW on the next LOW-to-HIGH transition of the Clock
Input (CP), independent of the state of all other synchronous Mode Control Inputs (CEP, CET, PEl.
For the 340160 and 340161, a LOW on the overriding asynchronous Master Reset (MR) sets all
outputs (Qo-Q3 and TC) LOW, independent of the state of all other inputs.

LOGIC SYMBOL
3

•
•
•
•
•
•

12 MHz TYPICAL COUNT FREQUENCY AT VDD = 10 V
DECODED TERMINAL COUNT
FULLY SYNCHRONOUS COUNTING AN'D PARALLEL ENTRY
SYNCHRONOUS (340162/340163) OR ASYNCHRONOUS (3401601340161) RESET
BUILT-IN CARRY CIRCUITRY
FULLY EDGE-TRIGGERED

5

6

10

10

14 13 12

11

3

6

4

5

eET

CP

TC

15

TC

15

SR

These devices perform multistage synchronous counting without additional components by using a
carry look-ahead counting technique.

The 340160, 340161, 340162, and 340163 are edge-triggered; therefore, the synchronous Mode
Control Input (CEP, CET, PE for the 340160/340161 and CEP, CET, PE, SR for the 340162/340163)
must be stable only during the set-up time before the LOW-to-HIGH transition of the Clock
Input (CPl.

4

14 13 12

11

VDD

=

Pin 16

Vss

=

Pin

8

340160/340161
CONNECTION DIAGRAM
DIP (TOP VIEW)
16
15

14
13

12

PIN NAMES
PE
PO-P3
CEP
CET
CP
MR
SR

00-0 3
TC

11

Parallel Enable I nput (Active LOW)
Parallel Inputs

10

Count Enable Parallel Input

Count Enable Trickle Input
Clock Input (L-+H Edge-Triggered)
Master Reset Input (Active LOW) for the 340160/340161 Orily
Synchronous Reset Input (Active LOW) for the 340162/340163 Only
Parallel Outputs
Terminal Count Output

340162/340163
CONNECTION DIAGRAM
DIP (TOP VIEW)
16
15

14

SELECTOR GUIDE
RESET

13

MODULUS
DECADE

BINARY

Asynchronous

340160

340161

Synchronous

340162

340163

12
11

10

NOTE:
The F latpak version has the same
pinouts (Connection Diagram) as the
Dual In-Line Package.

3-139

FAIRCHILD CMOS • 340160 • 340161 • 340162 • 340163
SYNCHRONOUS MODE SELECTION
340160/340161

SYNCHRONOUS MODE SELECTION
340162/340163

PE

CEP

CET

MODE

SR

PE

CEP

CET

L

X

X

Preset

H

L

X

X

Preset

H

L

X

No Change

H

H

L

X

No Change

H

X

L

No Change

H

H

X

L

No Change

H

H

H

Count

H

H

H

H

Count

L

X

X

X

Reset

MR

~

HIGH

MODE

TERMINAL COUNT GENERATION
340160/340162
(QO • 0,

CET

. Q2 .

340161/340163

Q3)

(00 • Q1 • Q2 • Q3)

TC

L

L

L

L

L

H

H

L

H

L

L

L

H

H

H

H

TG ~ GET' 00 • 01 • 02 • 03 (340160/340162)

H '" HIGH Level
L"" LOW Level
X = Don't Care

TG ~ GET' 00' 01 • 02 • 03 (340161/340163)

STATE DIAGRAM
340160 • 340162

STATE DIAGRAM
340161 . 340163

NOTE:
The 340160 or 340162 can be preset to any state, but will not count beyond 9. If preset to state 10, 11, 12, 13, 14 or 15, they will return to
thei r normal sequence within two clock pulses.

3·140

FAIRCHILD CMOS • 340160 • 340161 • 340162 • 340163
340161/340163 LOGIC DIAGRAM
The 340161 and 340163 binary synchronous counters are similar. However, the 340161 has an asynchronous master reset circuit as shown on
the 340160/340162 Logic Diagram.

Voo

Pin 16

VSS

Pin

o

8

Pin Numbers

340160/340162 LOGIC DIAGRAM

The 340160 and 340162 BCD synchronous counters are similar. However, the 340162 has a synchronous reset circuit as shown on the 340161/
340163 Logic Diagram.

VOD

Pin 16

VSS

Pin

o
3·141

8

Pin Numbers

FAIRCHILD CMOS • 340160 • 340161 • 340162 • 340163
DC CHARACTERISTICS: VDD as shown, VSS = 0 V

SYMBOL

MIN
Quiescent

IDD

Power
Supply
Current

LIMITS
VDD = 10V

V DD = 5 V

PARAMETER

TYP

MAX

MIN

TYP

V DD = 15 V

MAX

MIN

TYP
40

XC

100
700

200
1400

280

XM

20
300

40
600

8
120

UNITS

TEMP

~A

MIN,25°C
MAX

~A

MIN,25°C
MAX

TEST CONDITIONS

MAX
All inputs common
and at 0 V or VDD

NOTE: Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Characteristics.

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VDD as shown, VSS = 0 V, TA = 25°C

SYMBOL

PARAMETER

LIMITS
V DD =10V

V DD = 5 V
MIN

TYP

MAX

MIN

V DD - 15 V

TYP

MAX

MIN

TYP

UNITS

TEST CONDITIONS

MAX

tpLH
tpHL

Propagation Delay,
CP to Q

95
95

185
185

50
50

90
90

33
35

ns
ns

tpLH
tpHL

Propagation Delay,
CP to TC

130
130

250
250

60
60

115
115

37
37

ns
ns

tpLH
tpHL

Propagation Delay,
CET to TC

70
75

130
130

32
45

65
80

20
30

ns
ns

tpHL

Propagation Delay, MR to Q

128

250

55

110

37

ns

(340160/340161 )

tpHL

Propagation Delay, MR to TC

153

300

65

130

45

ns

(340160/340161 )

tTLH
tTHL

Output Transition
Time

35
40

75
75

20
20

40
40

15
15

tpLH
tpHL

Propagation Delay,
CP to Q

120
120

220
220

55
55

105
105

40
38

ns
ns

tpLH
tpHL

Propagation Delay,
CP to TC

155
155

285
285

70
70

130
130

45
40

ns
ns

tpLH
tpHL

Propagation Delay,
CET to TC

95
95

165
165

40
55

80
95

27
36

ns
ns

25
25

CL = 15 pF
I nput Transition
Times.; 20 ns

ns
ns

CL = 50 pF
Input Transition
Times.; 20 ns

tpHL

Propagation Delay, MR to Q

150

285

65

125

44

ns

(340160/340161 )

tpHL

Propagation Delay, MR to TC

175

335

75

145

52

ns

(340160/340161 )

tTLH
tTHL

Output Transition
Time

60
70

135
135

35
30

70
70

25
23

tree

MR Recovery Time

twMR(L)

MR Minimum Pulse Width

45
45

ns
ns

3

1

20

1

1

ns

(340160/340161 )

110

60

55

27

17

ns

(340160/340161 )

twCP

CP Minimum Pulse Width

90

50

40

20

15

ns

ts
th

Set-Up Time, Data to CP
Hold Time, Data to CP

70
0

35
-30

35
0

18
-15

13
-10

ns
ns

ts
th

Set-Up Time, PE to CP
Hold Time, PE to CP

110
-10

60
-57

60
-5

30
-28

20
-18

ns
ns

ts
th

Set-Up Time, CEP, CET to CP
Hold Time, CEP, CET to CP

200 115
-20 -110

95
-10

50
-48

35
-32

ns
ns

ts
th

Set-Up Time, SR to CP
Hold Time, SR to CP

40
0

15
-5

18
0

15
-2

4
0

ns
ns

'MAX

Input Count Frequency
(Note 3)

3

6

7

12

CL = 15 pF
I nput Transition
Times'; 20 ns

(3401621340163)
(340162/340163)

MHz

NOTES:
1. Propagation Delays and Output Transition Times are graphically described in this section under 34000 Series CMOS Family Characteristics.
2. Propagation Delays (tPLH and tPHL) and Output Transition Times (tTLH and tTHL) will change with Output Load Capacitance (eLL
Set-up Times (ts ), Hold Times (th), Recovery Times (tree), and Minimum Pulse Widths (tw ), do not vary with load capacitance.
3. For fMAX inpu.t rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.
4. It is recommended that input rise and fall times to the Clock Input be less than 15 J,Ls.

3-142

FAIRCHILD CMOS • 340160 • 340161 • 340162 • 340163
TYPICAL ELECTRICAL CHARACTERISTICS

POWER DI~SIPATION
VERSUS FREQUENCY

:::El000
I

Tr

~100

2

1

~

(Jl0

:

Voo
Voo
VOO
VOO

I

...ffi 1.0

ri II 1
0 15 V
015 V
0 10 V0 10V

I

: 10- 2
(jj

V>

is 10-3
a:

~ ~~

50

:%!

:5w
0

~ ~?

Z

0

>$.-

;=

...
... ~

...
...

0

a:

I

80 r--70

..-

/

CL-15 pF_
CL 050 pF ___

u

107

INPUT COUNT FREQUENCY
VERSUS TEMPERATURE

!

-

-"""

TA

I

o

tz

z

.... 10

~

..-

100

V

o

~30

z
:::l
o
(J

-

1-

VOO 0 15V

~

I~,.-/

250C

~ 120

...... 1""r-- t-- I--

i--

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

w

t--....

I -10~

~~I

-60 -40 -20 0 20 40 60 80 100120 140
TA - AMBIENT TEMPERATURE - °C

~ 140

CL 015 pF

I .......

V

~ 10
... 0

Q

CI

V

/ 'V

40

<520

140

w
a:
u.
.... 20

l-.J
-.JQq;;:.---

90

I 30

IIII

:;

~

CL 0 15 pF



.-% V

~

!'b:~ ~~

~ 10- 4 ~

!r

~

..~

I

~ 10-1
;=

~ 110

L

V

,..

"DO

V

80

(!)

VDO 0 15 V
VOO

:

r---

o

...a:

o;:;:t-

--r-r-=-

VDD 05 V

VOO 0 10V

60

VOO - 15 V

40

<5 20

~

...(J

o

-60 -40 -20 0 20 40 60 80 100120140
TA - AMBIENT TEMPERATURE - °C

o

o w

~
M
M l001Wl~lM
CL - LOAD CAPACITANCE - pF

SWITCHING DIAGRAMS
CLOCK (CPI TO OUTPUT (QI
PROPAGATION DELAYS AND MINIMUM
CLOCK PULSE WIDTH

CLOCK (CPI TO TERMINAL COUNT (TCI
PROPAGATION DELAYS

COUNT ENABLE TRICKLE INPUT (CET!
TO TERMINAL COUNT OUTPUT (TCI
PROPAGATION DELAYS

CET
CP

t::::i r-

o

tPLH~

t=-

~50%

CONDITIONS: l'E = MR = CEP = CET = H
for 340160/340161 and PE = SR = CEP =
CET = H for 340162/340163.

t

PLH

-1

t:=...-.=i r--

tPHL

~

TC---"O%

CONDITIONS: See the Terminal Count
Generation Table, fiE = CEP = CET = MR =

H for 340160/340161 andPE= CEP = CET
for 340162/340163.

= SR = H

3-143

F\50%

t~rd~
TC-'50%

CONDITIONS:

~

See the Terminal Count
Generation Table. CP = PE = CEP = M R = H
for 340160/340161 and CP = PE = CEP =
SR = H for 340162/340163.

FAIRCHILD CMOS • 340160 • 340161 • 340162 • 340163
SWITCHING DIAGRAMS (Cont'd)

340162/340163
SET-UP TIMES (t s ) AND HOLD TIMES
(th) FOR SYNCHRONOUS RESET (SR)

SET-UP TIMES (ts ) AND HOLD TIMES
(th) FOR PARALLEL DATA INPUTS
(PO,P3)'

o_~

----II
CONDITIONS:

PE

~ L, PO,P3 ~ H.

CONDITIONS:
340160/340161

PE ~ L,
and PE =

SET-UP TIMES (ts) AND HOLD TIMES
(th) FOR PARALLEL ENABLE INPUTPE

MR

~

H

for

L, SR = H for

CONDITIONS: MR ~ H for 340160/340161
and SA = H for 340162/340163.

340162/340163,

340160/340161
MASTER RESET (MR) TO OUTPUT (0)
DELAY, MASTER RESET PULSE WIDTH,
MASTER RESET RECOVERY TIME, AND
MASTER RESET TO TERMINAL COUNT
(TC) DELAY

SET-UP TIMES (ts ) AND HOLD TIMES
(th) FOR COUNT ENABLE INPUTS (CEP
AND CET)

CP

Q

o=x___

TC

CONDITIONS:
P 3 ~ H,

PE

~ L and Po ~ PI ~ P2 ~

CONDITIONS:
PE
340160/340161 and
340162/340163,

H

PE

NOTE:
1. Set-up Times (ts ) and Hold Times (th) are shown as positive values, but may be specified as negative values.

3-144

~

SR

~

H

for
for

340174
HEX D FLIP-FLOP

DESCRIPTION - The 340174 is a Hex Edge-Triggered D Flip-Flop with six Data Inputs (00-D5), a
Clock Input (CP) an overriding asynchronous Master Reset (MR), and six Buffered Outputs (00-05l.

LOGIC SYMBOL
3

4

Information on the Data Inputs (DO-D5) is transferred to the Buffered Outputs (00-05) on the
LOW-to-HIGH transition of the Clock Input (CP) if the Master Reset Input (MR) is HIGH. When
LOW, the Master Reset Input (MR) resets all flip-flops (00-05 ~ LOW) independent of the Clock
(CP) and Data Inputs (DO-D5).

6

11

13 14

340174

2

5

7

10

12 15

Voo = Pin 16
VSS = Pin 8

•
•
•
•

CONNECTION DIAGRAM
DIP (TOP VIEW)

TYPICAL CLOCK FREOUENCY OF 16 MHz AT VDD ~ 10 V
COMMON CLOCK TRIGGERED ON LOW-TO-HIGH TRANSITION
COMMON ACTIVE LOW MASTER RESET
FULLY EDGE-TRIGGERED CLOCK INPUT

16

15
14

13
12

10

PIN NAMES
NOTE:

Data Inputs
Clock Input (L-+H Edge-Triggered)
Master Reset I nput (Active LOW)
Buffered Outputs from the Flip-Flops

00- 0 5
CP
MR

00-0 5

The

F latpak version has the same

pinouts (Connection Diagram) as the
Dual I n-Line Package.

LOGIC DIAGRAM

M\D
CP

G0-g--i~~~---------+-4----------+-+----------+~----------~~--------~~

@
°5

Voo = Pin 16

VSS = Pin 8

o

= Pin Number

3-145

FAIRCHILD CMOS • 340174
DC CHARACTERISTICS: VDD as shown, VSS = 0 V
LIMITS
SYMBOL

VDD = 5 V

PARAMETER

MIN
Ouiescent
Power
Supply
Current

IDD

TYP

XC
XM

VDD - 15 V

V DD - 10V
MAX

MIN

TYP

MIN

MAX

20
200
2
100

TYP

40
400
4
200

UNITS

TEMP

TEST CONDITIONS

MAX

8
80
0.8

MIN,25°C
MAX
MIN,25°C
MAX

~A

pA

40

All inputs common
and at 0 V or VDD

NOTE: Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Characteristics.

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VDD as shown, VSS = OV, TA = 25°C
LIMITS
SYMBOL

PARAMETER

VDD = 5 V
MIN

V DD = 15V

VD D - 10V

TYP

MAX

MIN

TYP

MAX

MIN

TYP

UNITS

TEST CONDITIONS

MAX

tpLH
tpHL

Propagation Delay,
CP to On

60
60

100
100

25
25

45
45

18
18

ns
ns

tpHL

Propagation Delay,
MR to On

65

105

30

50

20

ns

tTLH
tTHL

Output Transition
Time

35
35

75
75

20
20

40

40

10
10

tpLH
tpHL

Propagation Delay,
CP to On

70
70

115
115

35
35

60
60

25
25

ns
ns

tpHL

Propagation Delay,
MR to On

80

125

40

65

25

ns

tTLH
tTHL

Output Transition
Time

65
65

135
135

35
35

70
70

15
15

25
25

45
45

CL =15pF
Input Transition
Times" 20 ns

ns
ns

CL =50pF
I nput Transition
Times" 20 ns

ns
ns

twCP(L)

Minimum Clock Pulse Width

45

25

20

10

8

ns

twMR(L)

Minimum MR Pulse Width

55

35

35

20

15

ns

tree

MR Recovery Time

25

6

13

5

2

ns

ts
th

Set-Up Time, Dn to CP
Hold Time, Dn to CP

5
20

1
10

5
10

1
2

0
1

ns
ns

fMAX

Maximum Clock Frequency
(Note 3)

5

9

8

16

CL = 15 pF
Input Transition
Ti mes" 20 ns

MHz

NOTES:

1.

Propagation Delays and Output Transition Times. are graphically described in this section under 34000 Series CMOS Family Characteristics.

2.

Propagation Delays (tPLH and tPHL) and Output Transition Times (tTLH and t-rHL) will change with Output Load Capacitance (eL)'
Set-up Times (ts), Hold Time~ (th), Recovery Times (tree), and Minimum Pulse Widths (tw) do not vary with load capacitance.
For fMAX, input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.
It is recommended that input rise and fall times to the Clock I nput be less than 15 /J.s.

3,
4.

3-146

FAIRCHILD CMOS·

340174

lYPICAL ELECTRICAL CHARACTERISTICS

El000

I

i'lll

;;:-~

IJ66 ~ lJI~"

10

ffi
0-

1.0

20

J
..

J:

::!!

I
Z

w
:::>
cJ
w

.' ..'

Z

•• -;?
..' ..' ~: .~~
~
'" 1 0-3 ~. ..;;:~
15
V
w
g10-41~ 1~ 1~

>::

(J

100

>-

90

:3w

80

z

70

f=

60

o

-1

...."'/

~
o

0::

0-

40

./
./

30

a

20

E?

10

0(J

o

~ t--

-60

/'

-20

>-

100

~

~

90

z

80

f=

70

(!J

60

~
o

I--

60

100

15

10

140

V
./
.... .,~

~

_ ~O\l

50

\l0~

40

a

30

E?

20

0(J

10

V

~

---...,..,....

I

\l010~1'~

20

/
5

0::

0-

l - I-'" ~\I
!-

/

TA; 25°C

c(

-- --

-

110

o

/'
\100

/'

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

"c:
o

V

50

~

VDD - POWER SUPPLY VOLTAGE - V

-1~

c(

(!J

Hz

CL; 15 pF

/

o
o

1~

PROPAGATION DELAY
VERSUS TEMPERATURE

"c:

5

(J

1~

CLOCK FREQUENCY -

o

0

...J

CL - 15 pF
CL; 50 pF ......
1~

/

...

5 V

III I

0-

10

0::

f' VDD;

Cii 10- 2
0::

/'

15

>(J

1

o 10-1

TA ;1 25oC
CL; 15 pF

N

,

..,;:,.- .
..'
v.
.~
..
IJ6 D ~ lIJI~,t~
..' P , /
.;;:- ~. "'V..'
l

(J

~

I I II

T~I ~I 2~ot

~ 100

~

CLOCK FREQUENCY
VERSUS
POWER SUPPLY VOLTAGE

TYPICAL POWER DISSIPATION
VERSUS CLOCK FREQUENCY

~

\l00~

~S\l- I--

_ - f-

,/

o

TA - AMBIENT TEMPERATURE - °C

20

40

60

80 100 120 140160

CL - LOAD CAPACITANCE - pF

SWITCHING WAVEFORM

CP

D,

MR

MINIMUM PULSE WIDTHS FOR CP AND MR, MR
RECOVERY TIME, AND SET-UP AND HOLD TIMES, On TO CP
NOTE: Set-up and Hold Times are shown as positive values but may be specified as negative values

3-147

340175
QUAD D FLIP-FLOP

DESCRIPTION - The 340175 is a Ouad Edge-Triggered 0 Flip-Flop with four Data Inputs (00-03), a
Clock Input (CP) an overriding asynchr~o~ Master Reset (MR), four Buffered Outputs (00-03) and
four Complementary Buffered Outputs (00-03!.

LOGIC SYMBOL

Information on the Data Inputs (00-03) is transferred to Outputs (00-03) on the LOW-to-HIGH
Transition of the Clock Input (CP) if the Master Reset Input (MR) is HIGH. When LOW, the Master
Reset Input (MR) resets all flip-flops (00-03 ~ LOW, 00-03 ~ HIGH), independent of the Clock (CP)
and Data (00-03) Inputs.

4

5

12 13

6

7

11

CP

3

;!

10 14 15

Voo::= Pin 16
VSS = Pin 8

TYPICAL CLOCK FREOUENCY OF 16 MHz AT VOD = 10 V
COMMON CLOCK TRIGGERED ON LOW-TO-HIGH TRANSITION
COMMON ACTIVE LOW MASTER RESET
TRUE AND COMPLEMENTARY OUTPUTS AVAILABLE
FULLY EDGE-TRIGGERED CLOCK INPUT

•
•
•
•
•

CONNECTION DIAGRAM
DIP (TOP VIEW)
16
15
14
13

10

PIN NAMES

00- 0 3

Data Inputs

CP
MR

Clock Input (L-+H Edge-Triggered)
Master Reset I nput (Active LOW)
Buffered Outputs from the Flip-Flops
Complimentary Buffered Outputs from the Flip-Flops

00-0 3
00-0 3

Note:

as the Dual In-Line Package.

LOGIC DIAGRAM

00

Go
VDO
VSS

o

=

Pin 16

=

Pin 8

The Flatpak version has the

same pinouts (Connection Diagram)

00

= Pin Number

3·148

FAIRCHILD CMOS • 340175
DC CHARACTERISTICS: VOO as shown, VSS = 0 V
LIMITS
SYMBOL

MIN

100

Ouiescent
Power

XC

Supply
Current

XM

VOO = 10V

VOO = 5 V

PARAMETER

TYP

MAX

MIN

TYP

2
20
0.2
10

VOO=15V

MAX

MIN

TYP

4

8

40

80
0.8
40

0.4
20

UNITS

TEMP

TEST CONDITIONS

MAX
MIN,25°C
MAX
MIN,25°C
MAX

~A
~A

All inputs common
and at 0 V or VOO

NOTE: Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Characteristics.

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VOO as shown, VSS = 0 V, TA = 25°C
LIMITS
SYMBOL

VOO = 10V

VOD = 5 V

PARAMETER

MIN

TYP

MAX

MIN

TYP

MAX

V OD=15V
MIN

TYP

UNITS

tpLH
tpHL

Propagation Delay,
CP to an or an

60
60

25
25

18
18

ns
ns

tpLH
tpHL

Propagation Delay,

iiiiR to an or an

65
65

30
30

20
20

ns
ns

tTLH
tTHL

Output Transition
Time

35
35

20
20

10
10

ns
ns

tpLH
tpHL

Propagation Delay,
CP to an or an

70
70

35
35

25
25

ns
ns

tpLH
tpHL

Propagation Delay,
MR to an or an

80
80

40
40

25
25

ns
ns

tTLH
tTHL

Output Transition
Time

65
65

35
35

15
15

ns
ns

twCP(L)

Minimum Clock Pulse Width

25

10

8

ns

lwiiiIR(L)

Minimum MR Pulse Width

35

20

15

ns

6

5

2

ns

1
10

1
2

0
1

ns
ns

9

16

tree

MR Recovery Time

ts
th

Set·Up Time, On to CP
Hold Time, On to CP

f MAX

Maximum Clock Frequency
(Note 3)

TEST CONDITIONS

MAX

CL =15pF
Input Transition
Times':; 20 ns

CL = 50 pF
Input Transition
Times':; 20 ns

CL =15pF
Input Transition
Times':; 20 ns

MHz

NOTES:
1. Propagation Delays and Output Transition Times are graphically described in this section under 34000 Series CMOS Family Characteristics.
2.

3.
4.

Propagation Delays (tpLH and tpHL) and Output Transition Times (tTLH and tTHL) will change with Output Load Capacitance (eL)'
Set-up Times {ts>' Hold Times (th), Recovery Times (tree>' and Minimum Pulse Widths (tw), do not vary with load capacitance.
For fMAX input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.
It is recommended that input rise and fall times to the Clock Input be less than 15 }J.S.

SWITCHING WAVEFORMS
'w'

ep

J

FL

~50%
"---J
.,,-

D"

-

MR

I~O%

\.

~

./
-.-twm-..
o~~
50%

50%

MINIMUM PULSE WIDTHS FOR CP AND MR.
MR RECOVERY TIME, AND SET·UP AND HOLD TIMES. On TO CP
Note: Set-up and Hold Times are shown as positive values but may be specified as negative values.

3-149

340192 · 340193
4-BIT UP/DOWN DECADE AND BINARY COUNTER
DESCRIPTION - The 340192 is a 4-Bit Synchronous Up/Down BCD Decade Counter and the 340193
is a 4-Bit Synchronous Up/Down Binary Counter. Both operate the same except for the count
sequence. Both counters have a Count Up Clock Input (CPU), a Count Down Clock Input (CPO!. an
asynchronous Parallel Load Input (i'L), four Parallel Data Inputs (PO-P3), an overriding asynchronous
Master Reset (MR), four Counter OutputSjQQ-03), a Terminal Count Up (Carry) Output (TCU) and a
Terminal Count Down (Borrow) Output (TCD).

LOGIC SYMBOL

11

When the Master Reset Input (MR) is LOW and the Parallel Load Input (PL.) is HIGH, the Counter
Outputs change state on the LOW-to-HIGH transition of either Clock Input. However, for correct
counting, both Clock Inputs cannot be LOW simultaneously. With the Master Reset Input (MR) LOW,
information on the Parallel Data Inputs (PO-P3) is loaded into the counter when the Parallel Load
Input (PL) is LOW and stored in the counter when the Parallel Load Input (PL.) goes HIGH, independent of Clock Inputs (CPU, CPO). When HIGH, the Master Reset (MR) resets the counter independent
of all other input conditions. See equations below for Terminal Count Outputs (TCU, TCD)'

15

14

3

TYPICAL COUNT FREQUENCY OF 8 MHz AT VDD = 10 V

Voo

•
•
•
•

SYNCHRONOUS OPERATION
INTERNAL CASCADING CIRCUITRY PROVIDED
ACTIVE LOW PARALLEL LOAD
ACTIVE HIGH ASYNCHRONOUS MASTER RESET

VSS

9

2

6

= Pin
= Pin

7

16
8

CONNECTION DIAGRAM
DIP (TOP VIEW)

Parallel Load Input (Active LOW)
Parallel Data Inputs
Count Up Clock Pulse Input (L .... H Edge-Triggered)
Count Down Clock Pulse Input (L .... H Edge-Triggered)
Master Reset Input (Asynchronous)
Buffered Counter Outputs
Buffered Terminal Count Up (Carry) Output (Active LOW)
Buffered Terminal Count Down (Borrow) Output (Active LOW)

Go-Q3
TCU
TCD

10

12

•

PIN NAMES
PL
PO-P3
CPU
CPO
MR

1

16
15
14
13
12
11

MODE SELECTION
(Both Counters)

10

MR

PL

CPU

CPO

MODE

H

X

X

X

Reset (Asyn.)

L

L

X

X

Preset (Asyn.)

L

H

H

H

No Change

L

H

..r

H

Count Up

L

H

H

..r

Count Down

NOTE:
L = LOW Level
H = HIGH Level
X

S

The F latpak version has the same
pinouts (Connection Diagram) as the
Dual I n-Line Package.

= Don't Care

= Positive~Going

Clock Pulse Edge

340192 STATE DIAGRAM

340193 STATE DIAGRAM

Count Up _ _ _ __
Count Down __________ _

340192 LOGIC EQUATIONS FOR TERMINAL COUNT
TCU
TCD

= Go. Q3 •
= Go. Q1 •

340193 LOGIC EQUATIONS FOR TERMINAL COUNT

CPU
Q2 • Q3 • CPO

3-150

FAIRCHILD CMOS • 340192 • 340193
LOGIC DIAGRAMS

340192

MR

~~~

______~__~~~________~~__~~__________~____-+~

CD

@

(CLEARI@

00
Voo

=

Pin 16

VSS

=

Pin 8

o

01

0

__________

~

02

= Pin Number

340193

(DOWN

CPD~-4~~~

COUNTI~

-l____Jl~::::::::::d:::::~!E::::::::::i:::::~~~~~~~~~~~~~~

____

MR ~DM~------~---1~----------~~--~~-----------4-----+~----------~

@

(CLEARI@

00
VDD

VSS

o

Teo

(BORROW
OUTPUTI

CD

01

= Pin 16
= Pin 8
= Pin Number

3-151

0

02

FAIRCHILD CMOS • 340192 • 340193
DC CHARACTERISTICS: VOO as shown, VSS = 0 V
LIMITS
SYMBOL

VOO

PARAMETER

MIN

100

Quiescent
Power
Supply
Current

=5 V

TYP

VOO
MAX

MIN

= 10V

TYP

XM

900

= 15 V

TYP

MIN

100
1400
25
1500

50
700
15

XC

VOO

MAX

UNITS

TEMP

TEST CONOITIONS

MAX

20
280

~A

5
3000

~A

MIN,25°C
MAX
MIN,25°C
MAX

All inputs common
and at 0 V or VOO

NOTE: Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Characteristics.

AC CHARACTERISTICS AND SWITCHING REQUIREMENTS:
LIMITS
SYMBOL

VOO -10V

VOO - 5 V

PARAMETER

MIN

TYP

MAX

MIN

TYP

MAX

VOO - 15 V
MIN

TYP

UNITS

tpLH
tpHL

Propagation Oelay,
CPU to Qn

225
225

95
95

65
65

ns
ns

tpLH
IpHL

Propagation Oelay,
CPO to Qn

225
225

95
95

65
65

ns
ns

tpLH
tpHL

Propagation Oelay,
CPU toTCU

110
110

50
50

35
35

ns
ns

tpLH
tpHL

Propaga~

CPO toTC O

125
125

50
50

35
35

ns
ns

tpHL

Propagation Oelay, MR to On

250

110

75

ns

tpLH

Propagation Oelay, MR
toTCU orTCO

350

150

100

ns

tpLH
tpHL

t!:0pagation Oelay,
PL to On

250
250

100
100

65
65

ns
ns

tTLH
tTHL

Output Transition
Time

35
35

20
20

15
15

ns
ns

tpLH
tpHL

Propagation Oelay,
CPU to On

245
245

105
105

70
70

ns
ns

tpLH
tpHL

Propagation Oelay,
CPO to Qn

245
245

105
105

70
70

ns
ns

IpLH
tpHL

Propagation Oelay,
CPU to TCU

130
130

60
60

40
40

ns
ns

tpLH
tpHL

Propagation Oelay,
CPO 10 TCO

145
145

60
60

40
40

ns
ns

tpHL

Propagation Oelay, MR to On

270

120

80

ns

tpLH

Pr~ati0!!..Q.elay,

370

170

105

ns

270
270

110
110

70
70

ns
ns

Oelay,

MR

TEST CONOITIONS

MAX

CL = 15 pF
Input Transition
Times" 20 ns

I

CL = 50 pF
Input Transition
Times .. 20 ns

toTC U orTC O
tpLH
tpHL

!:!.opagation Oelay,
PL to On

tTLH
tTHL

Output Transition
Time

55
55

30
30

20
20

ns
ns

twCP

Min. CPU or CPO Pulse Width

85

30

20

ns

IwMR

Minimum MR Pulse Width

60

30

20

ns

IwPL

Minimum PL Pulse Width

75

25

20

ns

tree

MR Recovery Time

75

30

20

ns

75

30

20

ns

85
-83

30
-28

20
-19

ns
ns

4

8

tree

PL Recovery Time

Is
th

Set-Up Time, Pn ~ PL
Hold Time, Pn to PL

fMAX

Input Count Frequency (Note 3)

See note on following page.

3-152

MHz

CL = 15 pF
Input Transition
Times .. 20 ns

FAIRCHILD CMOS • 340192 • 340193
NOTES:

1.

Propagation Delays and Output Transition Times are graphically described in this section under 34000 Series CMOS Family Characteristics.

2.

Propagation Delays (tPLH and tPHL) and Output Transition Times (tTLH and tTHL) will change with Output Load Capacitance
Set-up Times (t s ), Hold Times (th), Recovery Times (tree), and Minimum Pulse Widths (t w ), do not vary with load capacitance.
For fMAX. input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.
It is recommended that input rise and fall times to the Clock Inputs (CPU or CPO) be less than 15 MS.

3.
4.

SWITCHING WAVEFORMS

RECOVERY TIMES FOR PI. AND MR.
MINIMUM PULSE WIDTHS FOR CPU. CPD.
HOLD TIMES Pn TO Pi:

Pi: AND MR AND SET-UP AND

NOTE: Set-up and Hold Times are shown as positive values but may be specified as negative values.

3-153

(eLl.

340194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER

DESCRIPTION - The 340194 is a 4-Bit Bidirectional Shift Register with two Mode Control Inputs
(SO, S1), a Clock Input (CP), a Serial Data Shift Left Input (DSL), a Serial Data Shift Rig.!!!..lnput
(DSR), four Parallel Data Inputs (PO-P3), an overriding asynchronous Master Reset Input IMR) and
four Buffered Parallel Outputs (OO-ojl.
When LOW, the Master Reset Input (MR) resets all stages and forces all Outputs (00-03) LOW,
overriding all other input conditions. When the Master Reset Input (MR) is HIGH, the operating mode
is controlled by the two Mode Control Inputs (SO, 51) as shown in the Truth Table. Serial and parallel
operation is edge-triggered on the LOW-to-HIGH transition of the Clock Input (CPI. The inputs at
which the data is to be entered and the Mode Control I nputs (SO. 51) must be stable for a set·up time
before the LOW-to-HIGH transition of the Clock Input CPI.

LOGIC SYMBOL
3

10

S,

11

CP

4

5

7

340194

15 14 13

Voo
VSS

•
•
•
•
•

6

12

Pin 16
Pin 8

CONNECTION DIAGRAM
DIP (TOP VIEW)

TYPICAL SHIFT FREQUENCY OF 14 MHz AT VDD = 10 V
ASYNCHRONOUS MASTER RESET
HOLD (DO NOTHING) MODE
FULLY SYNCHRONOUS SERIAL OR PARALLEL DATA TRANSFERS
POSITIVE EDGE-TRIGGERED CLOCK

16
15
14

13
12
11

PIN NAMES
10

Mode Control Inputs
Parallel Data Inputs
Serial (Shift Right) Data Input
Serial (Shift Left) Data Input
Clock Input (L-+H Edge-Triggered)
Master Reset I nput (Active LOW)
Parallel Outputs

50,51
PO-P3
DSR
DSL
CP
MR
00-0 3

NOTE:

The

FlatPak version has the same

pinouts (Connection Diagram) as the

Dual In-Une Package.

LOGIC DIAGRAM
~

~

(2)

~

~

~

0 0 0

S1~·o-,-----,----r=---~~----~--~~----.------.----r=~--~----~~--~~---,

sO~'~~---+---H-1+-~------r--+r-~-1+-----+-~H-~--~-----r--Tr4H--'
(2)

DSR :::::.'------------,

Voo

Pin 16

VSS

Pin

8

o

cp~o-----------4---~--~------~---r---t-------+--~--~r-----~
MR~------_Q[>~--------------~~----------~--_i~----------------~

CD

3-154

__--------~

FAIRCHILD CMOS • 340194
TRUTH TABLE
OPERATING
MODE
Hold
Shift Left
Shift Right
Parallel Load

INPUTS (MR

L
H
L

OUTPUTS AT tn+1

DSR

DSL

PO,P"P2,P3

L

X

X

X

L

X

IL

X

L
H

X
X

L

X

X

I

H

= H)

So

Sl

H

QO

°1

°2

03

00

°1

°1

°2

°2
03

03
L

°1
L

°2
00

03

H

°1

°2

00
L
H

°1
L
H

°2
L
H

L
H

H

H

X

X

H

H

X

X

L

H

H

X

X

L
H

H

H

HI G H Voltage Level

x ""

L

LOW Voltage Level

(t n +1) = Indicates state after next LOW-to-HIGH clock transition.

Don't Care

DC CHARACTERISTICS: VDD as shown, VSS = 0 V

SYMBOL

MIN

IDD

Quiescent
Power
Supply
Current

LIMITS
VDD = 10V

V DD = 5 V

PARAMETER

TYP

MAX

MIN

TYP

V DD =15V

MAX

MIN

XC

50
500

1000

100

20
200

XM

5
40

10
80

2
16

UNITS

TEMP

TEST CONDITIONS

~A

MIN,25°C
MAX

~A

MIN,25°C
MAX

MAX

TYP

All inputs common
and at 0 Vor V aD

~

NOTE: Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Characteristics.

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VDD as shown, VSS = 0 V, TA = 25°C
LIMITS
SYMBOL

V DD = 5 V

PARAMETER

MIN

VDD=15V

VDD = 10 V

TYP

MAX

80
80

MIN

MIN

TYP

UNITS

TEST CONDITIONS

TYP

MAX

MAX

150
150

35
35

65
65

25
25

ns
ns

CL = 15 pF

80

150

35

65

25

ns

Input Transition

40
40

75
75

20
20

40
40

15
15

ns
ns

Times'; 20 ns

tpLH
tpHL

Propagation Delay,
CP to Q

tpHL

Propagation Delay,

tTHL
tTLH

Output Transition
Time

tpLH
tpHL

Propagation Delay,
CP to Q

100
100

180
180

45
45

80
80

35
35

ns
ns

tpHL

Propagation Delay, MR to Q

100

180

45

80

35

ns

Input Transition

tTHL
tTLH

Output Transition
Time

75
75

135
135

40
40

70
70

25
25

ns
ns

Times.; 20 ns

ts

Set-Up Time,
Po - P3 , DSL ' DSR to CP
Hold Time,
Po - P3' DSL' DSR to CP

th

MR to Q

25
25

45
45

CL = 50 pF

80

40

40

20

15

ns

0

-10

0

-5

-5

ns

30

-0

20
-5

ns
ns

CL = 15 pF

35

25

ns

Input Transition
Times'; 20 ns

ts
th

Set-Up Time, S to CP
Hold Time, S to CP

100
0

60
-10

50

twCP(L)

Minimum Clock Pulse Width

100

60

60

a

twMR(L)

Minimum MR Pulse Width

75

40

45

25

15

ns

tree

Recovery Time for MR

180

100

90

50

35

ns

f MAX

Maximum CP Frequency
(Note 3)

4,5

9

9

14

I

MHz

NOTES,
1. Propagation Delays and Output Transition' Times are graphically described in this section under 34000 Series CMOS Family Characteristics.
2. Propagation Delays (tPLH and tPHIJ and Output Transition Times (tTLH and tTHL) will change with Output l.oad Capacitance (eL)·
Set·up Times (t s), Hold Times (th), Recovery Times (tree), and Minimum Pulse Widths (tw) do not vary with load cClpacitance.
3. For fMAX input rise and fal/ times are greater than or equal to 5 ns and Jess than or equal to 20 ns.
4. It is recommended that input rise and fall times to the Clock I nput be less than 15 j.Ls.

3-155

FAIRCHILD CMOS • 340194
TYPICAL ELECTRICAL CHARACTERISTICS

POWER DISSIPATION
VERSUS FREQUENCY

s:

E 1000

~

10

w

1.0

a:
Il.

Z

o

~
iii

TIII'II

100

::2
(..)

II

T~'~'2~od

I
w
C!l

IIII

ITW -

~66UdU"

10-3

a:
w

~

,.~

~

~~...

!if' .r;::. . . .

5

90

w
C

80

Z

70

~

50

if
I

ao

III

~

10- 4
~
10 2

100

~
o

'

CL-15 pF-CL=50pF· ...... ·

lll.

(..)

104

10 3

10 5

10 6

PROPAGATION DELAY
VERSUS TEMPERATURE

c

o

.... ... ~
..
....V P.VDD = 5 V

~

10- 2

(J)

,"t--- .It if ....'
~. :.... ;
~

VDD-15V

10-1

15

1111

.

--

,-

20

o

w

c
z
o

TA = 25°C

~

~
o

if
I

a
~
Il.

(J

5I

140

\

120

\'CL = 50 pF
100

\ '\

80

'\

CL = 15 PF"-.,

o

o

5

120

if

"'-....
1'<

20

140

~
o
.......

10

60

140

100

--

TA = 25°C

160

z

C!l

'\

180

~

o
~

60

40

20

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

:r!

160

I

-20

TA - AMBIENT TEMPERATURE - °C

PROPAGATION DELAY
VERSUS POWER SUPPLY VOLTAGE

5

"00 = 10"

~V

10

INPUT FREQUENCY - Hz

:r!

--

40

-60

107

"0,2. :.,;-

~

60

30

15~

CL = 15 pF

100

VDD - POWER SUPPLY VOLTAGE - V

=6"

"00

=10 V

60

I

15

"00

I-

80

a

40

~

20

~

0

Voo - 16 V

o

ro

~

00

11

~

l00lrol~l00

CL - LOAD CAPACITANCE - pF

3-156

FAIRCHILD CMOS • 340194
SWITCHING TIME WAVEFORMS
The shaded areas indicate when the input is permitted to change for predictable output performance.

MASTER RESET PULSE WIDTH.
MASTER RESET TO OUTPUT DELAY AND
MASTER RESET TO CLOCK RECOVERY TIME

CLOCK TO OUTPUT DELAYS
CLOCK PULSE WIDTH

OTHER CONDITIONS:

S,: L, MR : H, SO: H

OTHER CONDITIONS:

SO. S, : H

PO: p , : P2: P3: H

\

\-----------

5,

OUTPUT'

---155HIFT LEFT

'-----------

I

~..._ _ _ _

'\.-_--Ir

SET-UP Its) AND HOLD (th) TIME FOR SERIAL
DATA (DSR. DSL) AND PARALLEL DATA (PO. Pl. P2. P3)

SET-UP (ts ) AND HOLD (th) TIME FOR S INPUT

,

OTHER CONDITIONS:

MR: H

OTHER CONDITIONS:

* DSR Set-up Time Affects 00 Only
DSL Set-up Time Affects 03 Only

3-157

MR : H

340195
4-81T UNIVERSAL SHIFT REGISTER
DESCRIPTION - The 340195 is a fully synchronous edge-triggered 4-Bit Shift Register with a Clock
Input (CP), four synchronous Parallel Q~ta Inputs (PO-P3), two synchronous Serial Data Inputs (J, K),
a synchronous Mode Control Input (PE), Buffered Outputs from all four bit positions (QO-Q3), a
Buffere~nverted Output from the last bit position (03) and an overriding asynchronous Master Reset
Input (MRl.

LOGIC SYMBOL

Operation is synchronous (except for Master Reset! and is ed~triggered on the LOW-to-HIGH
transition of the Clock Input (CP). When the Mode Control Input (PE) is LOW, a LOW-to-HIGH clock
transition loads data into the register from Parallel Data Inputs (PO-P3l. When the Mode Control Input
(PE) is HIGH, a LOW-to-HIGH clock transition shifts data into the first register position from the

9

4

6

5

7

6

Serial Data Inputs (J, K), and shifts all the data in the register one position to the right. D-type entry is
obtained by tying the two Serial Data Inputs (J, K) together. A LOW on the Master Reset Input (MR)

PE

resets all four bit positions (QO-Q3 = LOW, 03 = HIGH) independent of all other input conditions.
10

CP

° 0--

340195

3

3~ K __

•
•

•
•
•
•

TYPICAL SHIFT FREQUENCY OF 12 MHz AT VDD = 10 V
ASYNCHRONOUS MASTER RESET
J, K INPUTS TO THE FIRST STAGE
FULLY SYNCHRONOUS SERIAL OR PARALLEL DATA TRANSFERS
COMPLEMENTARY OUTPUT FROM THE LAST STAGE
POSITIVE EDGE-TRIGGERED CLOCK

PIN NAMES
PE

11

MR

f
VDD
VSS

15 14

13 12

Pin 16
Pin 8

Parallel Enable Input (Active LOW)
Parallel Data Inputs
First Stage J Input (Active HIGH)
First Stage K I nput (Active LOW)
Clock Input (L ~ HEdge-Triggered)
Master Reset I nput (Active LOW)
Parallel Outputs

PO-P3
J

K
CP
MR
QO-Q3
03

Complementary Last Stage Output

LOGIC DIAGRAM

CONNECTION DIAGRAM
DIP (TOP VIEW)

000
CD
PE
K Po
J

16
15
14
13
12
11
10

VOD

""

VSS

=

o

=

Pin 16

NOTE:

The

Pin 8
Pin Numbers

Flatpak version has the same

pinouts (Connection Diagram) as the

Dual 1n~Line Package.

3-158

FAIRCHILD CMOS • 340195
TRUTH TABLE
OPERATING MODE

INPUTS (MR

OUTPUTS AT tn+l

J

K

Po

Pl

P2

P3

QO

Ql

Q2

H

L

L

X

X

X

X

L

00

Ql

Q2

H

L

H

X

X

X

X

QO

QO

Ql

H

H

L

X

X

X

X

QO

Ql

H

H

H

X

X

X

X

00
H

°2
Q2

Ql
L

Q2
L

02
Q2
H

H

H

L

Shift Mode

Parallel Entry Mode
H

= HI

PE

L

X

X

L

L

L

L

L

QO
L

L

X

X

H

H

H

H

H

H

Q3

Q3
Q2
Q2

HIGH Voltage Level

L

LOW Voltage Level

X

Don't Care

(t n +1) = Indicates state after next LOW to HIGH clock transition.

DC CHARACTERISTICS: VD D as shown, VSS = a v

SYMBOL

MIN
Quiescent
IDD

Power
Supply
Current

LIMITS
V DD = 10 V

V DD = 5 V

PARAMETER

TYP

MIN

MAX

XC
XM

TYP

V DD =15V

MAX

MIN

TYP

50

100

20

500

1000

200

5
40

10
80

2
16

UNITS

TEMP

TEST CONDITIONS

MAX
~A

pA

MIN,25°C
MAX

Inputs at 0 V or V DD
per the Logic Function

MIN,25°C
MAX

or Truth Table

NOTE: Additional DC Characteristics are listed in this section under 34000 Series CMOS Family Characteristics.

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VD D as shown, VSS = 0 V, TA = 25°C
LIMITS
SYMBOL

PARAMETER

VD D - 10V

VDD - 5 V
MIN

TYP

MAX

MIN

VD D - 15 V

TYP

MAX

MIN

TYP

UNITS

TEST CONDITIONS

MAX

tpLH
tpHL

Propagation Delay,
CP to Qn

80
80

150
150

35
35

65
65

ns
ns

CL = 15 pF

tpHL

Propagation Delay, MR to Q3

80

150

35

65

ns

Input Transition

ns

Times'" 20 ns

tpHL

Propagation Delay, MR to Q n

80

150

35

65

tTHL
tTLH

Output Transition
Time

40
40

70
70

20
20

35
35

tpLH
tpHL

Propagation Delay,
CP to Qn or Q3

100
100

180
180

45
45

80
80

ns
ns

CL = 50 pF

tpHL

Propagation Delay, MR to Q3

100

180

45

80

ns

Input Transition

tpHL

Propagation Delay, MR to Q n

100

180

45

80

ns

Times", 20 ns

tTHL
tTLH

Output Transition
Time

75
75

135
135

40
40

70
70

ts

Set-Up Time,

25
25

45
45

ns
ns

ns
ns

80

40

40

20

25

ns

0

-10

0

-5

0

ns

J, K, Po - P3 to CP
th

Hold Time,
J, K, Po - P3 to CP

ts
th

Set-Up Time, PE to CP
Hold Time, PE to CP

100

60
0

50

30
0

35

20
0

ns
ns

CL = 15 pF

twCp(L)

Minimum Clock Pulse Width

100

60

60

35

40

25

ns

Input Transition
Times", 20 ns

twMR(L)

Minimum MR Pulse Width

75

40

45

25

25

15

ns

trec

Recovery Time for MR

180

100

90

50

60

35

ns

fMAX

Maxi mum CP Frequency (Note 3)

4.5

9

9

14

MHz

NOTES:
1. Propagation Delays and Output Transition Times are graphically described in this section under 34000 Series CMOScFamily Characteristics.
2. Propagation Delays (tPLH and tPHL) and Output Transition Times (tTLH and tTHL) will change with Output Load Capacitance (CL)'
Set-up Times (t s), Hold Times (th), Recovery Times (tree), and Minimum Pulse Widths (tw), do not vary with load capacitance.
3. For fMAX inpLit rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.
4. It is recommended that input rise and fall times be less than 15 /-Ls.

3-159

FAIRCHILD CMOS· 340195
TYPICAL ELECTRICAL CHARACTERISTICS

S;E

I

w

(!)

POWER DISSIPATION
VERSUS FREQUENCY
1000
T'

o

a:

...w
Z

o

~
iii
a:
w

I111

10

~PI?= ?VI"r---

~
~~
.'
."
~'

..

'

····v

VDD = 5 V

.···v

II11

~

o
z

~ :7.

.. :.... ;

~.

10- 1

10- 3

~

~
w

~.'

.f}K- :f..·V
.'

I

10- 2

III

~ci6l"d~ " J k

1.0

Vl

15

II

I

~

«
0.

1~12~od

fill I I

100

..c:
o

i

II i
Ii
III

10 3

10 4

50

o
a:

c..

a
o
I0.

o

c:

180

>

160

~

140

:s

~

120

Z

TA = 25°C

«

100

~

80

(!l

o
a:

0.

I

a

e...
o

20

VOD - S v

o

-60

....

160
140

~

120

~
I

ao

40

o w

~

~

~

i

5V

I0.

o

l00lWl~l~

CL - LOAD CAPACITANCE -

60

20

100

140

TA = 2SoC

\

i

100

pF

60

'\

",.I

'"

CL = 15 pF"-..,

40

i

20

o

o
VDD -

3-160

\CL = 50, pF

\

80

0.

VDD = 10V

Vr

-20

PROPAGATION DEALY
VERSUS POWER SUPPLY VOLTAGE

~

~

20

\100= 10\1

~I\I

10

>

oj::
«
(!l

60

0

--

30

TA - AMBIENT TEMPERATURE - °C

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

j::

-

\I~;:":-

I

40

Hz

.
:s

I -~

70

60

106

INPUT FREQUENCY -

80

«
0.

lsL

CL = 15 pF

90

~

(!l

CL= 15 pF-CL = 50 pF ........

O
...
S; 10- 4
10 2

PROPAGATION DELAY
VERSUS TEMPERATURE
100

,"'."...1'--I

i
5

10

15

POWER SUPPLY VOLTAGE - V

FAIRCHILD CMOS • 340195
SWITCHING TIME WAVEFORMS
The shaded areas indicate when the input is permitted to change for predictable output performance.

CLOCK TO OUTPUT DELAYS
AND CLOCK PULSE WIDTH

MASTER RESET PULSE WIDTH.
MASTER RESET TO OUTPUT DELAY AND
MASTER RESET TO CLOCK RECOVERY TIME

r

50%

'WMRILI--j--I",-I

-%---------

__________JjCr50

CLOCK
CLOCK

•

t

I- 'PHL-I

OUTPUT

5~'

OUTPUT - - - - -......

J

OTHER CONOITIONS:

~

PE

~

MR

~

H

OTHER CONDITIONS:

K~L

SET-UP (.!.II AND HOLD (thl TIME FOR SERIAL
DATA (J & KI AND PARALLEL DATA (PO. Pl. P2. P31

PE
Po

/

~
~

L
P,

~

P2

~

P3

~

H

SET-UP H EDGE-TRIGGERED
ASYNCHRONOUS PARALLEL LOAD INPUT (ACTIVE HIGH)

PIN NAMES
PL
PIN NAMES

PO-P4

AO-A3, BO-B3
Co
SO-S3
C4

Data Inputs
Carry Input
Sum Outputs
Carry Output

D
CP
MR
00-0 4

Parallel Load Input
Parallel Inputs
Data Input
Clock Input (L->H Edge-Triggered)
Master Reset Input
Buffered Outputs (Active LOW)
LOGIC SYMBOL

LOGIC SYMBOL

10
7

6

5

4

3

2

1

12

7

9

12

11

13

34018
14

11

3

14

34008

10

2

15

CP

15

13

5

Voo
VSS

VO D = Pin 16

VSS = Pin 8

CONNECTION DIAGRAM
DIP(TOP VIEW)

CONNECTION DIAGRAM
DIP (TOP VIEW)

4

6

Pin 16
=

Pin

8

DIVIDE-BY-N MODE
SELECTION
DIVIDE BY

16

2

DINPUT

-

00

-

15

15

3

14

14

4

°0'°1
01

13

13

5

01'02

12

12
11

11

10

10

6

02

7

02- 0 3

8
9
10

NOTE: The Flatpak version has
the same pinouts (Conn-

NOTE: The Flatpak version has the-same pinouts(Connection

ction Diagram) as the

Dual I n-Line Package,

Diagram) as the Dual I n-Line Package.

4-6

-

03

-

°3'°4
04

=

34022
4-STAGE DIVIDE-8Y-8 JOHNSON COUNTER

DESCRIPTION - The 34022 is a 4-Stage Divide-by-8 Johnson Counter with eight glitch free active
HIGH Decoded Outputs (00-07). an active LOW Output from t ' ost significant flip-flop (Q4-7).
an active HIGH and an active LOW Clock Input (CPO. CP1)
'overriding asynchronous Master
Reset Input (MRI.

LOGIC SYMBOL

The counter is advanced by either a
Po while CP1 is LOW or a HIGH-toLOW transition at CP1 while CPO is HIGH (see Functi'
Table)' When cascading the counters.
the Q4-7 Output (which is LOW while the cou ' ',
tes 4. 5. 6 and 7) can be used to drive the
CPO Input of the next 34022. A HIGH on
' Reset Input (MR) resets the counter to Zero
(00 = Q4-7 = HIGH. 01- 07 = LOW),i~!!!~,p~i~~i~n! of the Clock Inputs (CPO. Ci'1).

'II

,~"

","":',

,,"'_,'

•
•
•

CLOCK EDGE·TRIGG
HIGH·TO-LOW TR

12

,

,,,,,,,,,,1,,"

'I'~'I~&"t:i~HER A

15

2

1

3

711

4

510

LOW-TO·HIGH TRANSITION OR A

,/(1)111':';"

BUFFERED CAR", li~,!,UT (Q4-7) AVAILABLE FOR CASCADING
BUFFERED FULL'i!!"OECODED
OUTPUTS
""'IT

Voo

Pin 16

VSS

Pin

NC

Pin 6, 9

8

PIN NAMES
CPO
CP1
MR

Clock Input (L-+H Edge-Triggered)
Clock Input (H-+L Edge-Triggered)

00-0 7
Q4-7

Decoded Outputs
Carry Output (Active LOW)

CONNECTION DIAGRAM
DIP(TOP VIEW)

Master Reset Input

FUNCTIONAL TRUTH TABLE
MR

CPO

CP1

H

X

X

L

H

H-+L

Counter Advances

L

L-+H

L

Counter Advances

L

L

X

No Change

L

X

H

No Change

L

H

L-+H

No Change

L

H-+L

L

No Change

00

13

= Q4-7 = H; 01-07 = L

H

HIGH Level

L
L~H

LOW Level
LOW-to-HIGH Transition

H-+L

H IGH-to-LOW Transition

X

14

OPERATION

12

10

NOTE:

Don't Care

The F latPak version has the same
pinouts (Connection Diagram) as the
Dual In-Line Package.

4-7

•

34031

34041

54-STAGE STATIC SHIFT REGISTER

QUAD TRU E/COMPLEMENT BUFFER

DESCRIPTION - The 34031 is an edge-triggered 64-Stage Static Shift
Register with two Serial Data Inputs 100, 01) a Data Select Input IS), a
Clock Input IC?), a buffered Clock Output ICO) and buffered Outputs
from the 64th bit position IQ63, 063).

DESCRIPTION - The 34041 is a Quad True/Complement Buffer
which provides both an inverted active LOW Output (Z) and a
HIGH Output IZ) for each Input (I).

Data from the selected Data Inputs 100 or 01), as determined by the
state of the Select Input IS), is shifted into the first shift register
position and all the data in the register is shifted one position to the
right on the LOW-to-HIGH transition of the Clock Input ICP), DO is
selected by a LOW on the Select Input IS) and 01 is selected by a
HIGH on the Select Input IS).
Registers can be cascaded either by connecting all the Clock Inp,uts~ "'':'-,11.'''_
ICP) together or by driving the Clock Input ICP) of the right;ni'~;i~.<:··:',"::',::··
register with the system clock and connecting the Clock Output"j!I::.O)'".:·· ,t
to the Clock Input ICP) of the preceding register. When t~,~.. sec6~!'l·'··:·
technique is used in the recirculating mode, a flip-flop"'

store the Output IQ63) of the right-most register un~iI·c,.
register is clocked.
,~,",• CLOCK INPUT IS L-+H EDGE-TRIGGERED .".",.'·.:::;',,:,::'""."·,. i.:,.
•
•
•

DATA SELECT INPUT IS) ALLOWS
DO OR 01 INPUTS

DAT~·'!:1"~~Ct

EASI LY CASCADED
TRUE
AND
COMPLEMENTARY
AVAILABLE FROM 64TH STAGE

'to

PIN NAMES

AT EITHER

...
BUFFERED

OUTPUTS

la, Ib, Ic, Id

Buffer Input

Za,Zb,Zc,Zd

Buffered True Output

Za, Zb, Zc, Zd

Buffered Complementary Output

PIN NAMES
00,01
S
CP
CO
Q63

G:63

Data Inputs
Data Select Input
Clock Input IL-+H Edge-Triggered)
Buffered Clock Output
Buffered Output from the 64th Stage
Complementary Buffered Output from the 64th Stage
LOGIC DIAGRAM

LOGIC SYMBOL
151

10
34031
CP

063

CO

Voo = Pin 16 VSS = Pin 8
NC = Pins 3,4,5,11,12,13,14

CONNECTION DIAGRAM
DIP ITOP VIEW)

VDD

Pin 14

Vss

Pin

7

CONNECTION DIAGRAM
DIP (TOP VIEW)

16
15

14

14

13

13

12

12

11

11

10

10

NOTE: The Flatpak version has the same pinouts (Connection
Diagram) as the Dual In-Line Package.

NOTE: The Flatpak version has the same pinouts (Connection
Diagram) as the Dual In-Line Package.

4-8

34043

34044

QUAD R/S LATCH WITH 3-STATE OUTPUTS

QUAD R/S LATCH WITH 3-STATE OUTPUTS

DESCR IPTION - The 34043 is a Quad R/S Latch with 3-State Outputs
with a common Output Enable Input (EOl. Each latch has an active
HIGH Set Input (Sn), an active HIGH Reset Input (Rn) and an active
HIGH 3-State Output (Qnl.

DESCRIPTION - The 34044 is a Quad R/S Latch with 3-State Outputs
with a common Output Enable Input (EOl. Each latch has an active
LOW Set Input (Sn), an active LOW Reset Input (Rn) and an active
HIGH 3-State ()~tPut (Qnl.

When the Output Enable Input (EO) is HIGH, the state of the Latch
Outputs (Qn) can be determined from the Truth Table (see below).
When the Output Enable Input (EO) is LOW, the Latch Outputs are in
the high impedance OFF state. The Output Enable Input (EO) does not
affect the state of the latch.
•
•
•
•

When

th""'0,~;~'~,t, Enable

Input (EO) is HIGH, the state of the Latch
be determined from the Truth Table (see belowl.
When:::tl!~,"'e:jJtput Enable Input (EO) is LOW, the Latch Outputs are in
fh:~ ~,j\l~"'i'inpedance OFF state. The Output Enable Input (EO) does
<:Ii<>¥i:::~jl'kct the state of the latch.

Output~':':,,::(,q'~'l"\ca~

:,":~ ~:STATE BUFFERED OUTPUTS (ACTIVE HIGH)

3-STATE BUFFERED OUTPUTS (ACTIVE HIGH)
COMMON OUTPUT ENABLE
SET INPUTS TO EACH LATCH (ACTIVE HIGH)
RESET INPUTS TO EACH LATCH (ACTIVE HIGH)

'.
•
•

PIN NAMES

COMMON OUTPUT ENABLE
SET INPUTS TO EACH LATCH (ACTIVE LOW)
RESET INPUTS TO EACH LATCH (ACTIVE LOW)

SO-S3
RO-R3
QO-Q3

Common Output Enable Input
Set Inputs

EO

Output Enable Input

SO-53

Set Inputs (Active LOW)

Reset Inputs

RO-R3

Reset I nputs (Active LOW)

QO-Q3

3-State Buffered Latch Outputs

3-State Buffered Latch Outputs
TRUTH TABLE

EO

TRUTH TABLE
OUTPUT (Qn)

INPUTS
Sn

INPUTS

OUTPUT (Qn)

Sn

Rn

X

X

High Impedance

L

X

X

High Impedance

H

H

L

H

H

L

H

H

H

L

H

L

H

H

L

L

H

H

H

H

H

L

L

L

L

L

H

H

= HI G H

Rn

EO

L

H
H

I

PIN NAMES

EO

Level, L = LOW Level, X

No Change

= Don't Care

H

H = HIGH Level, L

=

LOGIC SYMBOL
3

6

7

12

11

34043

2

9

10

No Change

= Don't

Care

LOGIC SYMBOL
3

4

LOW Level, X

4

7

6

11

12

15

14

14 15

Voo

Pin 16

VSS

Pin

NC

Pin 13

8

34044

1

13

CONNECTION DIAGRAM
DIP (TOP VIEW)

9

10

Voo

Pin 16

VSS

Pin

NC

Pin

8

1

CONNECTION DIAGRAM
DIP (TOP VIEW)

16

16

15

15

14

14

13

13

12

12

11

11

10

10

NOTE: The Flatpak version has the same pinouts (Connection
Diagram) as the Dual In-Line Package.

NOTE: The Flatpak version has the same pinouts (Connection
Diagram) as the Dual In-Une Package.

4-9

34046
MICROPOWER PHASE-LOCKED LOOP
DESCRIPTION - The 34046 is a Micropower Phase-Locked Loop consisting of a low power linear

LOGIC SYMBOL

Voltage~Contro!led Oscillator, a Source Follower Circuit, two different Phase Comparators, and a
Zener diode. The Voltage-Controlled Oscillator has two External Capacitor connections (C exta , Cextb).
two External R~sistor connections (R exta • Rextb), a Voltage-Controlled Oscillator Input Uvea) and

a Voltage-Controlled Oscillator Output (OVCOl. The Source Follower Circuit provides a Demodulated
Output (OD) from the Voltage-Controlled Oscillator. An active LOW Enable Input (E) common to

both the Voltage-Controlled Oscillator and the Source Follower Circuit is also provided. Phase
Comparator I and Phase Comparator II have common Signal liS) and Comparator IIc) Inputs and
separate outputs; Phase Comparator I Output (OPCI), Phase Comparator II Output (OPCII), and Phase
Pulse Output (OPIIl. An input to the Zener diode liz) is also provided.

The Voltage-Controlled Oscillator requires one external capacitor ({;1) and one external resistor (R,)
to determine operational frequency range. A second externa(,,'f~s~$tor (R2) may be used to allow
frequency offset. External resistor R3 and external capacito("':'~:2"\~ofnbined serve as a low pass filter
to the Voltage-Controlled Oscillator Input IivCO)' Outpu{"<;l,j):' \ji pr6vided to avoid loading the low
pass filter. External resistor R4 is required if this outpu'~,:"i,,~.,U'i:i'Fzed. 00 must be left open when not
utilized. The output from the Voltage-Controlled Qiicilla,l,r::",(OVCO) may be connected directly or
indirectly through CMOS frequency dividers (i.e,,:':,tI:1(1,:(3,4018, 34020, 34022, 34024, 34029, 34040,
34518,34520, 340160, 3~0161, 340162, 340169,;3i!O'!ilQ, or 340193) to the Comparator Input (ICl.
With the Enable Input (E) HIGH both the"~:!litage"eontrolled Oscillator and the Source Follower
Circuit are OFF to minimize power cons~ptlan~".Whh E LOW, both are enabled.

For direct-coupling between OVCO an':~:~,,1:b~:,)'~'e voltage swing at the Voltage-Controlled Oscillator
Output (OVCO) must be within",~til~dar'CF:;CMOS logic levels NOH? 0.7 x VDO and VOL';; 0.3
x V DO); otherwise the signal fr!IDl' @
CD

0

~

i-

Ec22- --0[>

_J

SOURCE

FOLLOWER

-

Von'" Pin 16
Vss "'Pin8

00

Rexta

Rextb

@( @ @
R4

R,

R,

VDD

~

VSS

~

0

~

Pin 16

Pin

8

Pin Numbe

VSS

L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ._ _ _ _ _ _ _ _ _ _ _ _ _ _~

4-11

34047
MONOSTABLEjASTABLE MULTIVIBRATOR

DESCRIPTION - The 34047 is a Monostable/Astable Multivibrator,.capable of operating in either the
monostable or astable mode. Operation in either mode require~,;",ac- ternal capacitor (ex) between
pins 1 and 3 (Cext,Rext/Cext) and an external resistor (Rx)
'"
ins 2 and 3 (Rext,Rext/Cextl.
These external timing components (Rx,C x ) determine the
width in the monostable mode
and the output frequency in the astable mode. The
active HIGH and active LOW
astable mode Enable Inputs (EAO,EA1), active HIGH
've LOW Trigger Inputs (TO,1'1) for
operation in the monostable mode, a Retrigger I
), an Oscillator Output (0), active HIGH
and active LOW flip-flop Outputs (Q,G)' and a '
synchronous Master Reset Input (MRI.

LOGIC SYMBOL

ASTABLE OPERATION. Astable oper
on the EA 1 input. The frequency

tained by either a HIGH on t!>e EAO input or a LOW
cycle output at the Q and Q outputs is determined
A frequency twice that of the Q and Q outputs is
, a 50% duty cycle is not guaranteed. The 34047 can be
, the EAO and EA 1 inputs.

by the external timing compo

available at the Oscillator a
used as a gated oscillator

MONOSTABLE OPE
N. Monostable operation is obtained by connecting the EAO input LOW
and the EA1 in~t HIG . The device can be triggered by either a LO~-to-HIGH transition at the TO
input while the T1 input is LOW 0--' a HIGH-to-LOW transition at the T1 input while the TO is HIGH.
The output pulse width at 0 and 0 is determined by the external timing components (Rx,Cxl. The
device can be retriggered by applying a simultaneous LOWato~HIGH transition to both the Retrigger

Input (IRT) and the TO input while the 1'1 input is LOW.

13

10

MR

:~T

Q

0--11

L-----~T-----~

Voo

Pin 14

VSS

Pin

7

A HIGH on the Master Reset Input (MR) resets the output flip-flop (0 = LOW,G =HIGH) independent
of all other input conditions.

•
•
•
•
•

MONOSTABLE OR ASTABLE OPERATION
TRUE AND COMPLEMENTARY BUFFERED OUTPUTS
ENABLED WITH EITHER A LOW OR A HIGH LEVEL IN THE ASTABLE MODE
TRIGGERED ON EITHER A LOW-TO-HIGH OR A HIGH-TO-LOW TRANSITION
IN THE MONOSTABLE MODE
ASYNCHRONOUS MASTER RESET

CONNECTION DIAGRAM
DIP (TOP VIEW)

14

PIN NAMES
Cext

External Capacitor Connection

R ext

External Resistor Connection

Rext/Cext

Common External Capacitor and Resistor Connection

IRT

Retrigger Input

TO

Trigger Input (L ~ H Triggered)

1'1

Trigger Input (H

EAO

Enable Input (Active HIGH)

EA1
MR

Master Reset

~

L Triggered)

Enable I nput (Active LOW)

a

asci lIator Output

O,Q

True and Complementary Buffered Outputs

NOTE: The Flatpak version has the same
pinouts (Connection Diagram) as
the Dua! I n-Line Package.

4-12

34053
TRIPLE 2-CHANNEL ANALOG MULTIPLEXER/DEMULTIPLEXER

DESCRIPTION - The 34053 is a Triple 2-Channel Analog Multiple er!Demultiplexer with a common
ent Inputs/Outputs (YO,Y1), a
Enable Input (E). Each Multiplexer/Demultiplexer has two In
Common Input/Output (Z), and a Select Input (S). Each
er/demultiplexer contains two
bidirectional analog switches, each with one side connect
endent Input/Qutput (YO.Y1)
he Enable Input (E) LOW, one of
and the other side connected to a Common I nputlOutPLI
ect Input (S). With the Enable Input
the two switches is selected {low impedance, ON sta
(l~) HIGH, all switches are in the high impedance
, independent of the Select Inputs (Sa-Sc).

LOGIC SYMBOL

12 13

2

1

5

•

3

the Digital Control Inputs (Sa-Sc,E). Their
S. The analog Inputs/Outputs (YO,Y1,Z) can

VDD and VSS are the two supply voltage
voltage limits are the same as for all

swing between VDO as a positive limi
For operation as a digital multiplexerl

a negativ!=! limit. VOD-VEE may not exceed 15 V.

er, VEE is connected to VSS (typically ground).

11

10

6-0 E

•

COMMON
14

PIN NAMES
YOa-YOc, Y1a' Y 1c
Sa-Sc

E
Za-Zc

15

4

Pin 16

I ndependent Input/Outputs
Select Inputs
Enable Input (Active LOW)
Common Input/Outputs

Pin

8

Pin

7

CONNECTION DIAGRAM
DIP (TOP VIEW)
TRUTH TABLE
INPUTS

CHANNELS
16

E

S

YO-Z

L

L

ON

L

H

OFF

ON

14

H

X

OFF

OFF

13

H

HIGH Level

L

LOW Level
Don't Care

Y1- Z
OFF

15

12

X

11
10

NOTE: The FJatpak version has the same
pino!-lts (Connection Diagram) as the Dual

In-Une Package.

4-13

34067
16-CHANNEL ANALOG MULTIPLEXER/DEMULTIPLEXER

DESCRIPTION - The 34067 is a 16-Channel Analog Multiplexer/Demultiplexer with four Address
Inputs (AO-A3), 1SIndependent Inputs/Outputs (YO-Y15), an active LOW Output Enable input (EO),
and a Common Input/Output (Z). The 340S7 contains 16 bidirectional analog switches, each with one
side connected to an Independent Input/Output (YO-Y15) and the other side connected to a Common
Input/Output (Z). One of the 16 switches is selected (low impedance, ON state) by the four Address
Inputs (AO-A3) when the Output Enable input (EO) is LOW. All unselected switches are in the high
impedance OFF state. With the Output Enable input (EO) HIGH, all 16 switches are in the high
impedance OFF state. The Analog Input/Outputs (YO-Y15,Z) can swing between VDD and VSS.
VDD-VSS may not exceed 15 V.
•
•
•

CONNECTION DIAGRAM
DIP (TOP VIEW)

ANALOG OR DIGITAL MULTIPLEXER/DEMUL TlPLE
24-PIN PACKAGE
SINGLE POWER SUPPL Y

PIN NAMES
YO-Y15
Address Inputs

AO-A3
Z

10
11

12

34067

Voo

Pin 24

VSS

Pin 12

NOTE: The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual I n-Line Package,

TRUTH TABLE
CHANNEL

INPUTS
A3 A2 A1

AO

YO-Z

Y1-Z

Y2-Z

Y3-Z

Y4- Z

Y5-Z

YS-Z

Y7-Z

YS-Z

Yg-Z

Y1O-Z Y11-Z Y12-Z Y13-Z Y14-Z Y15-Z

L

L

L

L

ON

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

L

L

L

H

OFF

ON

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFf

OFF

OFF

OFF

OFF

OFF

OFF

L

L

H

L

OFF

OFF

ON

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

L

L

H

H

OFF

OFF

OFF

ON

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

L

H

L

L

OFF

OFF

OFF

ON

OFF

OFF

OFF

OFF

OFF

OFF

OFF

H

OFF

OFF

ON

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

H

OFF

OFF

OFF

OFF

H

OFF

OFF

OFF

OFF

OFF

ON
OFF

OFF

H

OFF
OFF

OFF

L

L
H

OFF
OFF

OFF

L

L
H

OFF
OFF

OFF

H

OFF
OFF

OFF

L

OFF
OFF

ON

OFF

OFF
OFF

H

L

L

OFF

OFF

OFF

OFF

OFF

OFF

OFF

ON

L

OFF
OFF

OFF
OFF

OFF

OFF
OFF

OFF
OFF

OFF

OFF

OFF
OFF

OFF

L

OFF
OFF

OFF

H

L
H

L
H

OFF

H
H
H

L
H

OFF

OFF

OFF

OFF

OFF

OFF

OFF

H
H

H
H

H

H

L

L

H

H

L
L

L

OFF
OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

H

OFF

OFF

OFF

OFF
OFF

OFF

OFF

OFF

OFF

OFF
OFF
OFF

OFF

L
H

OFF
OFF
OFF

OFF

H

OFF
OFF
OFF

OFF
OFF

OFF
OFF

H

LOW Level

H

HIGH Level

EO

= LOW Level

4-14

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF
ON

OFF
OFF

OFF
OFF

OFF

OFF

OFF

OFF

ON
OFF
OFF

OFF

ON

OFF

OFF
OFF

OFF

OFF

OFF
OFF

OFF
OFF

OFF
OFF

OFF

OFF

OFF

OFF

OFF

OFF

ON
OFF
OFF
OFF

OFF
OFF

OFF

tlFF
OFF
OFF

OFF

OFF
OFF

ON
OFF
OFF

OFF

ON
OFF

OFF
OFF
OFF
ON

34072

34075

DUAL 4-INPUT OR GATE

TRIPLE 3-INPUT OR GATE

DESCRIPTION - This CMOS logic element provides the positive Dual
4-lnput OR function. The outputs are fully buffered for highest noise
immunity and pattern insensitivity of output impedance.

DESCRIPTION - This CMOS logic element provides the positive Triple
3-lnput OR function. The outputs are fully buffered for highest noise
immunity and p,attern insensitivity of output impedance .

NOTE: The Flatpak version has the same
Diagram) as the Dual tn-Line Package.

NOTE: The FlatPak version has the same pinouts (Connection
Diagram) as the Dual I n-Line Package.

34073

34082

TRIPLE 3-INPUT AND GATE

DUAL 4-INPUT AND GATE

DESCRIPTION - This CMOS logic element provides the positive Triple
3-lnput AND function. The outputs are fully buffered for highest noise

DESCRIPTION - This CMOS logic element provides the positive Dual
4-lnput AND function. The outputs are fully buffered for highest noise
immunity and pattern insensitivity of output impedance.

immunity and pattern insensitivity of output impedance.

NOTE: The Flatpak version has the same pinouts (Connection
Diagram) as the Dual In-Line Package.

NOTE: The Flatpak version has the same pinouts (Connection
Diagram) as the Dual In-Line Package.

4-15

•

34510
UP jDOWN DECADE COUNTER

[)ESCRIPTION - The 34510 is an Edge-Triggered Synchronous Up Down BCD Counter with a Clock
Input (CP), an active HIGH Up/Down Count Control Input (U
), an active LOW Count Enable
Input (CE), an asynchronous active HIGH Parallel Load Inpu
ur Par3'.!!.e1 Inputs (PO-P3), four
Parallel Outputs (00-Q3!. an active LOW Terminal
ut (TC) and an overriding
asynchronous Master Reset Input (MRI.

LOGIC SYMBOL

Information on the Parallel Inputs (PO-P3) is loa
(PL) is HIGH, independent of all other input c
must be LOW. With the Parallel Load Inpu

'''counter while the Parallel Load Input
cept the Master Reset Input (MR) which
he counter changes on the LOW-to-HIGH
transition of the Clock Input (CP) if the
Ie Input (CE) is LOW. The Up/Down Count
Control Input (Up/Dn) determines th~
of the count, HIGH for counting up, LOW for
counting down. When counting up,
I Count Output (TC) is LOW when the Parallel
Outputs (00-03~re HIGH and t
able (CE) is LOW. When counting down, the Terminal
Count Output (TC) is LOW w,
rallel Outputs (00-03) and the Count Enable Input (CE)
are LOW. A HIGH on the
Input resets the counter (00-03 ~ LOW) independent of all

4

15

CP

10

UP/ON

13

3

34510

TC

MR

6

other input conditions.

•
•
•
•
•

12

11

14

2

Voo

Pin 16

VSS

Pin

8

UP/DOWN COUNT CONTROL
SINGLE CLOCK IIliPUT (L~H EDGE-TRIGGERED)
ASYNCHRONOUS PARALLEL LOAD INPUT
ASYNCHRONOUS MASTER RESET
EASILY CASCADABLE
CONNECTION DIAGRAM
DIP (TOP VIEW)

16

PIN NAMES

15

PL

Parallel Load Input (Active HIGH)

PO-P3

Parallel Inputs

14

CE

Count Enable I nput (Active LOW)

13

CP

Clock Pulse Input (L~H Edge-Triggered)

Up/Dn

Up/Down Count Control Input

TC

Terminal Count Output (Active LOW)

12
11

00-Q3

Parallel Outputs

MR

Master Reset Input

10

NOTE,
The F latpak version has the same
pinouts (Connection Diagram) as the

Dual In· Une Package.

4-16

34511
BCD-TO-7 SEGMENT LATCH/DECODER/DRIVER

DESCRIPTION - The 34511 is a BCD-to-7-Segment Latch/Decoder/Driver with four Address Inputs
(AO-A3), an active LOW Latc.!!....Enable Input (ELI, an active LOW Ripple Blanking Input (IB), an
active LOW Lamp Test Input (I LT) and seven active HIGH NPN bipolar segment outputs (a-g).

LOGIC SYMBOL

When the Latch Enable Input (ELI is LOW, the state of the Segment Outputs (a-g) is determined by
the data on the Address Inputs (AO-A31. When the Latch Enable Input (EL) goes HIGH, the last data
present at the Address Inputs (AO-A3) is stored in the latches and the Segment Outputs (a-g) remain
stable.

7

When the Lamp Test Input (ILT) is LOW, all the Segment Outputs (a-g) are HIGH independent of all
o.!!>er input conditions. With the Lamp Test Input (lLT) I::!!Q.H, a
on the Ripple Blanking...!!'put
(lB) forces all Outputs (a-g) LOW. The Lamp Test Input (lLT
Ripple Blanking Input (IB) do
not affect the latch circuit.

abc

HIGH CURRENT SOURCING OUTPUTS (U
BLANKING INPUT (ACTIVE LOW)
LAMP TEST INPUT (ACTIVE LOW)
LAMP INTENSITY MODULATION,

11

d

e

10

9

f

9

15 14

VSS = Pin 8

CONNECTION DIAGRAM
DIP (TOP VIEW)

AO-A3

Add··

IT

Latch
Ie I n put (Active LOW)
Ripple Blanking Input (Active LOW)
Lamp Test Input (Active LOW)
Segment Outputs

ILT
a-g

6

Voo == Pin 16

PIN NAMES

TB

2

34511

13 12

•
•
•
•

1

Inputs

16
15
14

13

TRUTH TABLE
OUTPUTS

INPUTS
EL

IB

X

X

ILT
L

12

A3

A2

A1

AO

a

b

c

d

e

f

9

DISPLAY

X

X

X

X

H

H

H

H

H

H

H

8

X

L

H

X

X

X

X

L

L

L

L

L

L

L

BLANK

L

H

H

L

L

L

L

H

H

H

H

H

H

L

0

L

H

H

L

L

L

H

L

H

H

L

L

L

L

1

L

H

H

L

L

H

L

H

H

L

H

H

L

H

2

L

H

H

L

L

H

H

H

H

H

H

L

L

H

3

L

H

H

L

H

L

L

L

H

H

L

H

H

4

L

H

H

L

H

L

H

H

L

H

H

L
L

H

H

L

H

H

L

H

H

L

L

L

H

H

H

H

H

5
6

L

H

H

L

H

H

H

H

H

H

L

L

L

L

7

L

H

H

H

L

L

L

H

H

H

H

H

H

H

L

H

H

H

L

L

H

H

H

H

L

L

H

H

8
9

L

H

H

H

L

H

L

L

L

L

L

L

L

L

BLANK

L

H

H

H

L

H

H

L

L

L

L

L

L

L

BLANK

L

H

H

H

H

L

L

L

L

L

L

L

L

L

BLANK

L

H

H

H

H

L

H

L

L

L

L

L

L

L

BLANK

L

H

H

H

H

H

L

L

L

L

L

L

L

L

BLANK

L

L

L

L

.

L

L

L

BLANK

L

H

H

H

H

H

H

H

H

H

X

X

X

X

H == HIGH Level
L = LOW Level
X = Don't Care
== Depends upon the BCD code applied during the LOW-to-H I G H transition of E L.

4-17

.

11

10

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual I n-Line Package.

NUMERICAL DESIGNATIONS

•

34514
1-OF-16 DECODER/DEMULTIPLEXER WITH INPUT LATCH

DESCRIPTION - The 34514 is a 1·of·16 Decoder/Demultiplexer with four binary weighted Address
Inputs (AO-A3), a Latch Enable Input (EU, an active LOW Enable Input (E) and sixteen mutually
exclusive active HIGH Outputs (00-015).

CONNECTION DIAGRAM
DIP (TOP VIEW)

When the Latch Enable Input (EL) is HIGH, the selected Output (00-015) is determined by the data
on the Address Inputs (AO-A3). When the Latch Enable Input (EL) goes LOW, the last data present
at the Address inp~ts (AO-A3) is stored in the latches and the Outputs (00-015) remain stable. When
the Enable Input (E) is LOW, the selected Output (°0-°15), determined by the contents of the latch,
is HIGH. When the Enable Input (E) is HIGH, all Outputs (00-015) are LOW. The Enable Input (E)
does not affect the state of the latch.
With the Latch Enable Input (EL) HIGH, 16·channel demultip
the Enable Input (E) and the desired output is selected by
follow as the inverse of the data. All unselected outputs (0
•
•
•

24
23

resu Its when data is applied to

22

selected output (00-015) will
OW.

21

LATCH ENABLE INPUT (ACTIVE HIGH)
ENABLE INPUT (ACTIVE LOW)
SELECTED BUFFERED OUTPUTS
(ACTIVE HIGH) COMPLEMENT OF TH

20

19
18

PIN NAMES
17

AO-A3

E

16

EL
00-°15

VDD
VSS

34514

11

9

10

8

7

6

5

4

18

=
=

Pin 24
Pin 12

10

15

11

14

12

13

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.

17 20 19 14 13 16 15

TRUTH TABLE
INPUTS

OUTPUTS

E

AO

A1

A2

A3

00

H

X

X

X

X

L

L

L

L

L

H

L

L

L

H

L

H

H

L

L

L

L

H

L

L

H

L

H

L

L

L

H

H

L

L

H

H

H

L

L

L

L

H

L

L

L

H

L

L

°2
L

03

04

°5

06

°7

08

09

010

011

012

013

°14

L

°1
L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

H

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

H

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

H

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

H

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

H

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

H

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

H

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

H

L

L

L

L

L

L

L

L

L

H

L

L

L

L

L

L

L

L

H

L

L

L

L

L

L

L

L

L

H

L

L

L

L

L

L

L

L

L

H

L

L

L

L

L

L

H

L

H

L

L

L

L

L

L

L

L

L

L

H

L

L

L

L

L

H

L

H

L

L

L

L

L

L

L

L

L

L

L

H

L

L

L

L

L

H

H

L

L

L

L

L

L

L

L

L

L

L

L

H

L

L

L
L

°15

L

H

L

H

H

L

L

L

L

L

L

L

L

L

L

L

L

L

H

L

L

L

H

H

H

L

L

L

L

L

L

L

L

L

L

L

L

L

L

H

L

L

H

H

H

H

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

H

H = HIGH Level
L
= LOW Level
EL = HIGH

4·18

34515
1-0F-16 DECODER/DEMULTIPLEXER WITH INPUT LATCH

DESCRIPTION - The 34515 is a 1-of-16 Decoder/Demultiplexer with four binary weighted Address
Inputs (AO-A3), a Latch Enable Input (Ell, an active LOW Enable Input (E) and sixteen mutually
exclusive active LOW Outputs (00-0151.

CONNECTION DIAGRAM
DIP (TOP VIEW)

When the Latch Enable Input (EL) is HIGH, the selected Output (00-015) is determined by the data
on the Address Inputs (AO-A31. When the Latch Enable Input (Ell goes LOW, the last data present
at the Address Inputs (AO-A3) is stored in the latches and the Outputs (00-015) remain stable_ When
the Enable I nput (E) is LOW, the selected Output (5(j-015), determined by the contents of the latch,
is LOW. When the Enable Input (E) is HIGH, all Outputs (00-015) are HIGH. The Enable Input (E)
does not affect the state of the latch.
With the Latch Enable Input (EL) HIGH, 16-channel demultipl
the Enable Input (E) and the desired output is selected by A
follow the data at the Enable Input (E). All unselected a
•
•
•

24
23

results when data is applied to
lected Output (00-015) will
15) are HIGH.

22
21

20

LATCH ENABLE INPUT (ACTIVE HIGH)
ENABLE INPUT (ACTIVE LOW)
BUFFERED OUTPUTS (ACTIVE LOW)

19
18

PIN NAMES
AO-A3

17

E

16

EL

E

10

15

11

14

12

13

EL AO A, A2 A3

VDD

34515

= Pin

24

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as

VSS = Pin 12

the Dual In-Line Package.
11

9

10

,8

7

6

5

4

18

17 20 19 14 13 16 15

TRUTH TABLE
INPUTS

OUTPUTS

E

AO

Al

A2

A3

00

01

02

03

04

05

06

07

Os

09

010

011

012

013

014

015

H

X

X

X

X

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

L

L

L

L

'L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

L

L

L

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

L

H

L

L

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

L

L

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

L

L

L

H

L

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

L

H

L

H

L

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

L

L

H

H

L

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

L

H

H

H

L

H

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

L

L

L

L

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

H

L

H

L

L

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

L

L

H

L

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

L

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

L

L

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

L

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

L

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H = HIGH Level
L = LOW Level
EL = HIGH

4-19

•

34516

34519

UP/DOWN COUNTER

QUAD 2-INPUT MULTIPLEXER

DESCRIPTION - The 34516 is an edge-triggered synchronous Up/
Down 4-Bit Binary Counter with a Clock Input (CPl. an active HIGH
Count Up/Down Control Input (Up/On). an active LOW Count Enable
Input (CE), an asynchronous active HIGH Parallel Load Input (PL),
four Parallel Inputs (PO-P3), four Parallel Outputs (QO-Q3), an active
LOW Terminal Count Output (TC) and an overriding asynchronous
Master Reset Input (MR).

DESCRIPTION - The 34519 provides four multiplexing circuits with

common selection inputs; each circuit contains two inputs and one
output. It rna

be used to select four bits of information from one of
A inputs are selected when SA is HIGH, the B inputs
H. When SA and SB are HIGH, the output (2a)
sive-NOR of the An and Bn inputs (2n = An 0Bn).
are LOW, the output (2n) is LOW, independent
iplexer inputs (An and Bn). The 34519 cannot be used
x analog signals. The outputs utilize standard buffers for

Information on the Parallel Inputs (PO-P3) is loaded into the counter
while the Parallel Load Input (PL) is HIGH, independent of all other
input conditions except the Master Reset Input (MR) which must be
LOW. When the Parallel Load Input (PU and the Count Enable Input
(CE) are LOW, the counter changes on the LOW-to-HIGH transition·
the Clock Input (CP). The Count Up/Down Control Input (
determines the direction of the count, HIGH for counting
for counting down. When counting up, the Terminal C
(TC) is LOW when QO = Q1 = Q2 = Q3 = HIGH

formance.

•

FUllY BUFFERED OUTPUTS
FUNCTION
Select I nputs (Active HI G H)
Mu Itiplexer Inputs
Multiplexer Outputs

PIN NAMES
SA,SB
AO-A3, BO-B3

When counting down the Terminal Count Output (

00 = Q1 = Q2 = Q3 = LOW and the CE = LOW. A
Reset Input (MR) resets the counter (QO = q, '

20-Z3

independent of all other input conditions.
lOGIC SYMBOL
•
•
•
•

UP/DOWN COUNT CONTROL
SINGLE CLOCK INPUT (L->H EDGE-TRIGGERED)
ASYNCHRONOUS PARALLEL lOAD INPUT
ASYNCHRONOUS MASTER RESET

PIN NAMES
PL

00-Q3

FUNCTION
Parallel Load Input (Active HIGH)
Parallel Inputs
Count Enable Input (Active LOW)
Clock Pulse Input (L->H Edge-Triggered)
Up/Down Count Control Input
Terminal Count Output (Active LOW)
Parallel Outputs

MR

Master Reset Input

PO-P3
CE
CP
Up/On
TC

23151

V OO =Pin16

VSS = Pin 8

10111213

CONNECTION DIAGRAM
DIP (TOP VIEW)

LOGIC SYMBOL

34516

TC

NOTE: The Flatpak version has the same pinouts (Connection
Diagram) as the Dual I n-Line Package.

VOO=Pin16
~

11

14

VSS = Pin 8

2

TRUTH TABLE
CONNECTION DIAGRAM
DIP (TOP VIEW)

13

11

NOTE:

SELECT

INPUTS

SA

SB

An

Bn

2n

L

L

X

X

L

H

L

L

X

L

H

L

H

X

H

L

H

X

L

L

L

H

X

H

H

H

H

L

L

H

H

H

L

H

l

H

H

H

L

L

H

H

H

H

H

H = HIGH Level
L = LOW Level
X = Don't Care

The F latpak version has the same
pinouts (Connection Diagram) as the
Dual In-Line Package.

4-20

OUTPUT

34522

34526

PROGRAMMABLE 4-BIT BINARY
DOWN COUNTER

PROGRAMMABLE 4-BIT BCD DOWN COUNTER

DESCRIPTION - The 34522 is a synchronous Programmable 4-Bit
BCD Down Counter with an active HIGH and an active LOW Clock
Input (CPO, <:P,), an asynchronous Parallel Load Input (PL), four
Parallel Inputs (PO-P3), a Carry Forward Input (CF), four buffered
Parallel Outputs (QO-Q3), a Terminal Count Output (TC) and an
overriding asynchronous Master Reset Input (MR).

DESCRIPTION - The 34526 is a synchronous Programmable 4-Bit
Binary Down Counter with an active HIGH and an active LOW Clock
Input (CPO, <:P,)' an asynchronous Parallel Load Input (PL), four
Parallel Inpu
PO-P3), a Carry Forward Input (CF), four buffered
Parallel
(QO-Q3), a Terminal Count Output (TC) and an
nous Master Reset Input (MR).

Information on the Parallel Inputs (PO-P3) is loaded into the counter
while the Parallel Load Input (PL) is HIGH, independent of all other
input conditions except Master Reset Input (MR) which must be LOW.
When the Parallel Load Input (PL) and the active LOW Clock Input
(CP,) are LOW, the counter advances on a LOW-to-HIGH transition of
the active HIGH Clock Input (CPO). When the Parallel Load Input (
is LOW and the active HIGH Clock Input (CPO) is HIGH, the c
advances on a HIGH-to-LOW transition of the CP, Input. The Ter
Count Output (TC) is HIGH when the counter is in the zero .
Q, = Q2 = Q3 = LOW) and the Carry Forward Input (
,
HIGH on the Master Reset Input (MR) resets t
LOW) independent of other input conditions.

the Parallel Inputs (PO-P3) is loaded into the counter
allel Load Input (PL) is HIGH, independent of all other
nditions except Master Reset Input (MR) which must be LOW.
he Parallel Load Input (PL) and the active LOW Clock Input
e active HIGH Clock Input (CPO). When the Parallel Load Input (PL)
is LOW and the active HIGH Clock Input (CP.l!!..is HIGH, the counter
advances on a HIGH-to-LOW transition of the CP, Input. The Terminal
Count Output (TC) is HIGH when the counter is in the zero state
(QO = Q, = Q2 = 03 = LOW) and the Carry Forward Input (CF) is
HIGH. A HIGH on the Master Reset Input (MR) resets the counter
(Oo- Q3 = LOW) independent of other input conditions.

•

•

•
•
•
•

1) are LOW, the counter advances on a LOW~to·HIGH transition of

FULLY SYNCHRONOUS PROGRAMMAB
COUNTER
CLOCK INPUT EITHER HIGH-TO-LOW OR LOW-TO-HIGH
EDGE-TRIGGERED
ASYNCHRONOUS MASTER RESET
CASCADABLE
ASYNCHRONOUS PARALLEL LOAD

PIN NAMES
PL
PO-P3
CF
CPO

<:P,
MR
TC
QO-03

FULLY SYNCHRONOUS PROGRAMMABLE BCD DOWN
COUNTER
• CLOCK INPUT EITHER HIGH-TO-LOW OR LOW-TD-HIGH
EDGE-TRIGGERED
• ASYNCHRONOUS MASTER RESET
• CASCADABLE
• ASYNCHRONOUS PARALLEL LOAD
FUNCTION
PIN NAMES
Parallel Load Input
PL
Parallel Inputs
PO-P3
Carry Forward Input
CF
Clock Input (L-+H Edge-Triggered)
CPO
Clock Input (H-+L Edge-Triggered)
<:P,
Asynchronous Master Reset Input
MR
Terminal Count Output
TC
Buffered Outputs
00-Q3

FUNCTION
Parallel Load Input
Parallel Inputs
Carry Forward Input
Clock Input (L-+H Edge-Triggered)
Clock Input (H-+L Edge-Triggered)
Asynchronous Master Reset Input
TC Terminal Count Output
Buffered Outputs
LOGIC SYMBOL

LOGIC SYMBOL

511142

13

13
34522

V DD = Pin 16
10

7

VSS

9151

=

VDO = Pin 16

Pin 8

10

CONNECTION DIAGRAM
DIP (TOP VIEW)

7

9

15

VSS

1

CONNECTION DIAGRAM
DIP (TOP VIEW)
16
15
14

13
12
11

NOTE:
The F latpak version has the same
pinouts (Connection Diagram) as the
Dual I n~Line Package.

NOTE:
The F latpak version has the same
pinouts (Connection Diagram) as the
Dual I n-Line Package.

4-21

= Pin

8

34528
DUAL RETRIGGERABLE RESETIABLE
MONOSTABLE MULTIVIBRATOR

DESCRIPTION - The 34528 is a Dual Retriggerable Resetta
Multivibrator has an active LOW Input (iQ). an active HIGH In
Input (Co). an Output (0). its Complement (Q) and t
.
components (Cext • Cext/Rext). An external timing
Cext/Rext and an external resistor must be connected
A HIGH-to-LOW transition_on the iQ Input when t
on the '1 Input when the 10 Input is HIGH p
a negative pulse (H .... L....H) on tlTe Q Output'
Clear Direct Input (CO) forces the a Outp
until the Clear Direct Input (CO) is HI

•
•
•

RESETTABLE
TRIGGER ON EITH
TRANSITION ON
COMPLEMENTA

Monostable Multivibrator. Each
(11). an active LOW Clear Direct

34528 LOGIC SYMBOL

onnecting the external timing
connected between Cext and
ext and VDD·

is LOW or a LOW-to-HIGH transition
tive pulse (L....H.... L) on the Output and
irect Inp_ut (Co) is HIGH. A LOW on the
Output HIGH and inhibits any further pulses

a

-TO-LOW TRANSITION ON

10

a,
I

OR A LOW-TO-HIGH

1/2 OF 34528

Ct

Cext/Rextb

10

ab

PIN NAMES

iiia. iiib
11a. 11 b
Cl)a. CDb
0". 0b

0;;. Qb

Cexta. Cextb
Cext/Rexta. Cext/Rextb

FUNCTION
Input (H .... L Triggered)
Input (L.... H Triggered)
Clear Direct Input (Active LOW)
Output
Complimentary Output (Active LOW)
External Capacitor Connections
External Capacitor/Resistor Connections

vDD

At

@

®
Cextb
1/20F 34528

13

Voo = Pin 16
VSS = Pin 8

CONNECTION DIAGRAM
DIP (TOP VIEW)

TRUTH TABLE

10

11

Co

H.... L

L

H

Trigger

H

L....H

H

Trigger

X

X

L

Reset

OPERATION

16
15
14
13

H
L
H-+L
L-+-H
X

12

= HIGH Level
= LOW Level
= HIGH-to-LOW Transition
== LOW-to-HIGH Transition
= Don't Care

11

10

NOTE:
The F latpak version has the same
pinouts (Connection Diagram) as the
Dual"tn-Line Package.

4-22

34531
13-INPUT PARITY CHECKER GENERATOR

DESCRIPTION - The 34531 is a 13-lnput Parity Checker/Generatllr with 13 Parity Inputs (10-112)
and a Parity Output (Z). When the number of Parity Inputs that, a~ , HIGH is even, the Output (Z) is
LOW_ When the number of Parity Inputs that are HIGH is a
tput (Z) is HIGH_ For words of
12 bits or less, the Output (Z) can be used to generate
r even parity by appropriate
termination of the unused Parity Input (s). For words a
bits, the devices can be cascaded
by connecting the output (Z) of one device to
Input (10-112) of another device_
When cascading devices, it is recommended that t
of one device be connected to the 112
input of the other device since there is less del'
tput (Z) from the 112 input than from any
other Input (10-111).

•
•
•

LOGIC SYMBOL

76

5

10-112
Z

3

2

1

151413121110

34531

VARIABLE WORD LENG
FULLY BUFFERED OUT
PARITY INPUTS (A

PIN NAMES

4

FUNCTION
Parity Inputs
Buffered Output

VDD=Pin16
VSS = Pin 8

CONNECTION DIAGRAM
DIP (TOP VIEW)

TRUTH TABLE
INPUTS

OUTPUT

10 11 12 13 14 15 16 17 18 19 110 111 112
All Thirteen
Inputs LOW

Z
L

Any One

Input HIGH

H

Any Two

Inputs HIGH

L

Any Three

Inputs HIGH

H

15

Any Four

Inputs HIGH

L

14

Any Five

Inputs HIGH

H

Any Six

Inputs HIGH

L

Any Seven

Inputs HIGH

H

Any Eight

Inputs HIGH

L

11

Any Nine

Inputs HIGH

H

10

Any Ten

Inputs HIGH

L

Any Eleven

Inputs HIGH

H

Any Twelve

Inputs HIGH

L

All Thirteen

Inputs HIGH

H

L

=

H

=

LOW Level
HIGH Level

16

13
12

NOTE:

The

Flatpak version has the same

pinouts (Connection Diagram) as the

Dual In-Line Package.

4-23

34532
a-INPUT PRIORITY ENCODER

DESCRIPTION - The 34532 is an 8-lnput Priority Encoder with
(10-17), three active HIGH Address Outputs (AO-A2), an active
HIGH Enable Output (EO ut ) and an active HIGH Group Selec

ht active HIGH Priority Inputs
H Enable Input (Eln), an active
(GS)'

Data is accepted On the eight Priority Inputs (10-17). T
de corresponding to the highest
Priority Input (10-17) which is HIGH is generated on the
utputs (AO-A2) if the Enable Input
(Eln) is HIGH. Priority Input 17 is assigned the hi
. The Group Select output (GS) is
HIGH when one Or more Priority Inputs (10-1
able Input (Eln) are HIGH. The Enable
Output (EO ut ) is HIGH when all the Priori
7) are LOW and the Enable Input (Eln) is
HIGH. The Enable Input (Eln) when LO
tputs (AO-A2, GS, EO ut ) LOW.

LOGIC SYMBOL

10

11

12

13

1

2

3

4

34532

15

9

7

6

14

VDO = Pin 16

PIN NAMES

VSS

FUNCTION
Priority Inputs
Enable Input
Enable Output
Group Select Output
Address Outputs

10-17
Eln
EOut
GS
AO-A2

= Pin

8

CONNECTION DIAGRAM
DIP (TOP VIEW)

16

TRUTH TABLE
15

INPUTS

OUTPUTS
14

Eln

17

15
X

14
X

13
X

12
X

10

GS

A2

A1

AO

X

16
X

I,

L

X

X

L

L

L

L

L

H

L

L

L

L

L

L

L

L

L

L

L

L

H

12

H

H

X

X

X

X

X

X

X

H

H

H

H

L

11

EOut

H

L

H

X

X

X

X

X

X

H

H

H

L

L

H

L

L

H

X

X

X

X

X

H

H

L

H

L

H

L

L

L

H

X

X

X

X

H

H

L

L

L

H

L

L

L

L

H

X

X

X

H

L

H

H

L

H

L

L

L

L

L

H

X

X

H

L

H

L

L

H

L

L

L

L

L

L

H

X

H

L

L

H

L

H

L

L

L

L

L

L

L

H

H

L

L

L

L

13

10

NOTE:

The Flatpak version has the same

x ""

pinouts (Connection Diagram) as the

Don't Care

Dual In-Line Package.

L = LOW Level
H = HIGH Level

4-24

34582
CARRY LOOKAHEAD GENERATOR

DESCRIPTION - The 34582 is a Carry Lookahead Generator which provides high speed lookahead
over word lengths of more than four bits. The device has a Carry

Generate Inputs 1<3 0 -(3 3 ), four active LOW Carry Propagate
(Cn+x,Cn+y,Cn+z), an active LOW Carry Propagate Out"

LOGIC SYMBOL

put (en), four active LOW Carry

iPO-P3), three Carry Outputs
n active LOW Carry Generate

Output (GL The logic equations for all outputs are shown
4

3

2

1

15 14

6

I

- 5;'

LENGTHS OF MORE THAN FOUR

10
13

PIN NAMES

Cn
11

12

<3 0 -<3 3

1'0-1'3
~n+x/Cn+y,Cn+z

G
P

ry

utputs
ry Generate Output IActive LOW)
Carry Propagate Output IActive LOW)

VOD = Pin 16

VSS

=

Pin 8

LOGIC EQUATIONS
C n + x = GO + Po ' C n

Cn +y

= G1

C n+ z

=

+ P1 • GO + P1 • Po • C n

G2 + P2 • G 1 + P2 '. P1 ' GO + P2 ' P, • Po • C n

CONNECTION DIAGRAM
DIP ITOP VIEW)

<3 - G3 + P3 ' G2 + P3 • P2 • G, + P3 • P2 ' P, , GO

l' = P3

• P2 • P, • Po

16
15
14
13

12
11
10

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual In-Line Package.

4-25

340283
4-BIT BINARY FULL ADDER

DESCRIPTION - The 340283 is a 4-Bit Binary Full Adder with two 4-bit Data Inputs (AO-A3.
BO-B3). a Carry Input (CO). four Sum Outputs (SO-S3) and a Carry'
tput (C4).
The 340283 uses full lookahead across 4-bits to generate th~,,,",,

LOGIC SYMBOL

tput (C4)' This minimizes the

necessity for extensive "Iookahead" and carry-cascading cir
5

•
•

6

3

2

14

15

12 11

FULL CARRY LOOKAHEAD ACROSS
EASILY CASCADED
340283

PIN NAMES
AO. BO. A1. 81
A2. B2. A3. B3
1

Co

13

10

SO-S3
C4

LOGIC DIAGRAM
Voo = Pin 16

Vss

~

Pin

8

CONNECTION DIAGRAM
DIP (TOP VIEW)

16
15
14
13

12
11

",,-0l:2?-ii==Ii=o--1
__.......-,,

10

" ",

""~0

LCQ----t:=:t:::v

"O~
""--0

NOTE:
The F latpak version has the same
pinouts (Connection Diagram) as the
Dual In-Line Package.

"o~0~_--.........
Voo

= Pin

16

Vss

=

Pin

8

4-26

34703
16 x 4 PARALLEL/SER IAL FI FO
FAIRCHILD CMOS MACROLOGIC*

DESCRIPTION - The 34703 is an expandable high speed First-In First Out (FIFO) buffer memory
with totally asynchronous and independent data inputs and outpu '," in either serial or 4~bit parallel
form. It can be extended to any number of words and to
mber of parallel bits without
additional circuitry and without compromising any featu.
3-state output buffers which

LOGIC SYMBOL

I

I

I

provide added versatility and make the 34703 compati

•

ther circuits of the bus-oriented

CMOS Macrologic family.

7

---<>
---<>
8 ---<>

6

5

4

3

10

•
•
•
•
•

SERIAL OR PARALLEL INPUT
SERIAL OR PARALLEL OUTPUT,
EXPANDABLE WITHOUT EXTER
3-STATE FULLY BUFFERE
24-PIN PACKAGE

9

13

IES

IRF

CPSI
TOP

---<>

14
15

34703

TOS
DES

1 6 - 0 CPSO

ORE

23

1 7 - 0 EO

PIN NAMES

MR

00-0 3

Os
PL
CPSI
CPSO
IES
TTS
TOS
TOP
OES
OE
MR

iRF
ORE

00-0 3

Os

11

Parallel Load Input
Serial Input Clock Input (HIGH-to-LOW Triggered)
Serial Output Clock Input (HIGH-to-LOW Triggered)
Serial Input Enable (Active LOW)
Transfer to Stack I nput (Active LOW)
Transfer Out Serial I nput (Active LOW)
Transfer Out Parallel Input
Serial Output Enable Input (Active LOW)
Output Enable Input (Active LOW)
Master Reset Input (Active LOW)
Input Register Full Output (Active LOW)
Output Register Empty Output (Active LOW)
Parallel Data Outputs
Serial Data Output

1819202122

VOD == Pin 24

VSS = Pin 12

CONNECTION DIAGRAM
DIP (TOP VIEW)

24

23
22
21

20
19

18
17
16

10

15

11

14

12

13

NOTE:

The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual In-Line Package.

* A Trademark of Fairchild Camera and Instrument Corporation.
4-27

FAIRCHILD CMOS • MACROLOGIC • 34703
BLOCK DIAGRAM

G) DS------------------------------~

CD

CD

PL

CPSI~
®IES~

@

INPUT

CONTROL

TTS--Q

STACK

14 X 14 STACK

CONTROL

D
@OES--o

@

TOP

OUTPUT
CONTROL

@TOS--o
@ Cpso--o

Voo

=

Pin 24

VSS

=

Pin 12

o

== Pin Numbers

FUNCTIONAL DESCRIPTION - As shown in the block diagram, the 34703 consists of three parts: 1! an input register with parallel and serial
data inputs as weH as control inputs and outputs for input handshaking and expansion. 2) a 4~bit wide, 14-word deep fall-through stack with
self-contained control logic. 3} an output register with parallel and serial data outputs as well as control inputs and outputs for output
handshaking and expansion. Since these three sections operate asynchronously and almost independently, they will be described separately
below:

INPUT REGISTER (DATA ENTRY!:
The input register can receive data in either bit-serial or in 4-bit parallel form, store it until it is sent to the fall-through stack, and generate and
accept the necessary status and control signals.
Figure 1 is a conceptual logic diagram of the input section. As described later, this 5-bit register is initialized by setting the F3 flip-flop and

resetting the other flip-flops. The Q output of the last flip-flop (FC! is brought out as the "Input Register Full" output (IRF!. After
initialization this output is HIGH.

PARALLEL ENTRY:
A HIGH level on the PL input loads the DO-D3 data inputs into the FO-F3 flip-flops and sets the FC..f!ip-flop, which forces IRF LOW,
indicating "input register full". The 0 inputs must be stable while PL is HIGH. During parallel entry the IES input should be LOW; the CPSI
input may be either HIGH or LOW.

*A Trademark of Fairchild Camera and Instrument Corporation.

4-28

FAIRCHILD CMOS • MACROLOGIC • 34703
r-------------------OUTPUTFROMSTACK-----------------.
LOAD FROM 8T ACK

INITIALIZE

cpso-----I--~--------------~----------~----~--------------+-------------_+~

OES----~L-.J~~--t---------t-~~

MR------...

TOP----~~~--_t--~~
EO----~.~-------t-

Fig. 2
CONCEPTUAL OUTPUT SECTION
SERIAL ENTRY:
Data on ~DS input is serially entered into the F3, F2, Fl, FO, FC shift register on each HIGH-to-LDW transition of the CPSI clock input,
provided I ES and PL are LDW.
After the fourth clock transition the four serial data bits are aligned in the four data flip-flops and the FCflip-flop is set, forcing

TRF

LOW

(input register full) and internally inhibiting further CPSI clock pulses.

Figure 3 illustrates the final positions in a 34703 resulting from a 64·bit serial bit train. BO is the first bit, 863 the last bit.

TRANSFER TD THE FALL-THROUGH STACK:
The outputs of the flip-flops FO-F3 feed the stack. A LOW level on the TTS input attempts to initiate a "fall-through" action. If the top
location of the stack is empty, data is loaded into the stack and the input register is re-initialized. Note that this initialization is postponed until
PL is LOW again. Thus automatic FIFO action is achieved by connecting the iRF output to the TTS input.
Data falls through the stack automatically, pausing only when it is necessary for an empty next location. In the 34703, like in most modern
FIFO designs, the MR input initializes the stack control section only and does not clear the data.

INPUT

Rl'QljilJ'!3. ____________ _

34703

OUTPUT
REGISTER

Fig. 3
FINAL POSITIONS IN A 34703 RESULTING
FROM A 64-BIT SERIAL TRAIN

4-29

FAIRCHILD CMOS • MACROLOGIC • 34703
OUTPUT REGISTER (DATA EXTRACTION):
The output register receives a 4·bit data word from the bottom stack location, stores it and puts it on a 3-state 4-bit parallel data bus or on a
3-state serial data bus. The output section generates and receives the necessary status and control signals. Figure 2 is a conceptual logic diagram
of the output section.
PARALLEL DATA EXTRACTION:
When the FIFO is empty (after a LOW pulse is applied to MR), the Output Register Empty (ORE) output is LOW, After data has been entered
into the FIFO and has fallen through to the bottom stack location, it is transferred into the output register. provided the "Transfer Out
Parallel" (TOP) input is HIGH, arid the OES input is LOW, As a result of the data transfer ORE goes HIGH, indicating valid data on the data
outputs (provided the 3-state buffer is enabled).
TOP can now be used to clock out the next word, When TOP goes LOW, ORE will go LOW indicating that the output data has been extracted,
but the data itself remains on the output bus until the next LOW-to-HIGH transition of TOP transfers the next word (if available) into the
output register as explained above, During parallel data extraction TOS, CPSO and OES should be LOW,
SERIAL DATA EXTRACTION:
When the FIFO is empty (after a LOW pulse is applied to MR), the Output Register Empty (ORE) output is LOW, After data has been entered
into the FIFO and has fallen through to the bottom stack location, it is transferred into the output shift register provided the "Transfer Out
Serial" (TOS) input is LOW, TOP must be HIGH, and OES and CPSO must be LOW,

As a result of the data transfer ORE goes HIGH indicating valid data in the shift register. The 3~state serial data output aS is automatically
enabled and puts the first data bit on the output bus, Data is serially shifted out on the HIGH,to-LOW transition of CPW, The fourth
transition empties the shift register, forces ORE LOW and disables the serial output OS, For serial operation the ORE output is tied to the TOS
input, requesting a new word from the stack as soon as the previ
one has been shifted out.

~-------------INPUTDATA------------------------.

~

INITIALIZE

D,

~I

--+----""1""----,

°5 ---1---1

iES

CPS I

----+--Qjr'"}--+------------4-------4-------4~

INPUTREG~STAGK~==----------""1""-r----------~_+-------~_+----------_,
(PULSE DERIVED FROM TTS)

' - - - - - - - - - - - D A T A INPUTS TO S T A G K - - - - - - - -

Fig, 1
CQNCl'9Tl)AI,. llll!'IJT SECTION

4-30

FAIRCHILD CMOS • MACROLOGIC • 34703
EXPANSION
VERTICAL EXPANSION

The 34703 can be vertically expanded to store more words without any external parts. The interconnections

necessary to form a 46~word by 4-bit FIFO are shown in Figure 4. Using the same technique, any FIFO of 15n + 1 words by four bits can be
constructed. Note that expansion does not sacrifice any of the FIFO's flexibility for Serial/Parallel input and output.
HORIZONTAL EXPANSION - The 34703 can also be horizontally expanded to store long words (in multiples of four bits) without any
external logic. The inter-connections necessary to form a 16-word by 12-bit FIFO are shown in Figure 5. Using the same technique. any FI FO
of 16 words by 4 x n bits can be constructed. When expanding in the horizontal direction, it is necessary to connect the IRF and ORE outputs
of the right most device (most significant device) to the TTS and TOS inputs respectively of all devices to the left (less significant devices).

As in the vertical expansion scheme, horizontal expansion does not require sacrificing any of the FI FO's flexibility for Serial/Parallel input
and output.
HORIZONTAL AND VERTICAL EXPANSION - The 34703 can be expanded in both the horizontal and vertical direction without any

external parts and without sacrificing any of the F.IFO's flexibility for Serial/Parallel input and output. The interconnections necessary to form
a 31-word by 16-bit FIFO are shown in

Fi~ure

6.

Figures 7 and 8 show the timing diagrams for serial data entry and extraction for the 31-word by 16-bit FIFO shown in Figure 6. The final
position of data after serial insertion of 496 bits into the FIFO array of Figure 6 is shown in Figure 9.

PARALLEl DATA IN

PARALLE\J,,~,':t!L

MASTER
RESET

LOAg".

':.~'

I O
2
03

0,

I
DO

"/:/::':"I~";;:

SERIAL oATA!N

,,:~

.;;;:::;;:;l::
SERIAL INPUT CLOCK

•

I"i:;:l'.
~
'"

::'e

\;,;:li:;;t~ ,---c
.-::'.:)'.::./::: .

PL
TTS
IES
CPS!

Os

0 3 02 01

DES

DO

0--

ORE

0--

34703

TOS
TOP

epso
ED
MR

Q3 Q2 Q 1

°0

1

L--c

IRF

Os

Nle

PL
TTS
IES
CPS!

Os

D3 O2 0 1 DO
IRF

po--

ORE

0-

DES

,---c

.--

34703

TOS
TOP
CPSO

ED
Q 3 °2 Q,

MR

°0

1

L--c

Je

PL Os 03 02
TTS
IES
epsI

a,s

r-<

UMP
ERIAL OUTPUT CLOCK
UTPUT ENABLE

Os

0, DO
IRF

p-

34703

TOS
TOP

ORE
epso
EO
MR °3 °2 Q, 00 Os

a

r

°3 °2

-=-

0,

I
I

SER IAL
DATA OUT

°0

I

PARALLEL DATA OUT

Fig. 4
A VERTICAL EXPANSION SCHEME FOR THE 34703

4-31

DATA VALID

FAIRCHILD CMOS • MACROLOGIC • 34703

Jrl'

r - - - - - - - - - - - - - P A R A l L E L DATA INPUT _ _ _ _ _ _ _ _ _ _ _ _- ,

CP:: _ _ _

f--""""1l~-+I-to3-Dt-2-+0,_01-0_ _ _-+-_~++-+07-to6- 0t--+04_ _ _-+---,1
5

• __+-olrisL
.-+--_i-<>JIES
'-<> ~:~

Ds

DO

IRFlo-+----I--<'I"ES
-<> CPS I
34703

,-oTOS
r - - TOP
---0 CPSG

rO EO~R

D3 02 D1

ORE 1003

0,

0,

J

,----<>lOES
,-oTOS
r--TOP

34703

,--0 CPSO

r<' E~R 03 Q, 0,

DUMP--t;-+4-~r--+--r-+-i-r-t_--r-~-r+---+_+~r_t_+--r-+__i.-J

O'sO--ti-t-~r--+--r-t-+-r-t---r-r-~+---t-+-ir-t-+--r-+--i-~

EO-rt-r---4---1--r-t-+-+-+---~--r---~--+--r~-+-+-1---+--t-~

DATA
READY

MR--t;-+----~-r-+-i-r----r-r----~_+~r_t_+_--+__i----~

I

I

1

I

1

~~~~~~---irt----~-----+-t1-+--+-~~-----r+-t1-----r+-~------+-r+-t----+-+~
~~~C~T--r-rt--~~-----+-t;-+---+-~-------r+-~---r~--------i-r+-t_---i~
DUMP---i~-----------+-~-+---+------------++-t1---~----------+-++-t---~
4_o,,'3'-0-'12'-"
1L0--,3,--°-,,2_°-,-'°--'0'--_ _ _ _ _ _ _ _
°'-7°--,6,--°--,5,-°24 PARALLEL DATA OUTPUTQ-",-,o--""-0_09'--0-'8'---_ _ _ _ _ _ _0-"5'--o--"c:

Fig.6

A 31 X 16 FIFO ARRAY

4·32

SERIAL
DATA
OUTPUT

FAIRCHILD CMOS • MACROLOGIC • 34703

I
I

to ---...

DEVICE 1

I
I

k-----

~----------------~I,
I

I I
tD----+-I

DEVICE 2

~

IRF

__

__________________________________~:--~r----I I
I I

tD+---l

DEVICE 3

__

: Ir_____

IRF

I

I

•

DEVICE 4/TTS ALL DEVICES
IRF

INPUTS
BITS

STORED IN
DEVICE 3

STORED IN
DEVICE 4

Fig. 7
SERIAL DATA ENTRY FOR ARRAY OF FIG. 6

I

I

I

I

to--"

DEVICE 5

k----

~----------------~I,
I I
I I
tD----+-I

DEVICE 6

I
I
__

L-________________~__________________~:~:~r-----

I

I I
I I

tD+---l

DEVICE 7

__

~________~~Ir----~D~E~V~IC~E~8~,T~0~S~A~L~L~D~E~V~I~C~ES~

I
I
I
____________________________________________________________~ltD~

I
I
__

I

~--I....

SERIAL DATA OUTPUT

01

DEVICE 5

DEVICE 6

DEVICE 7

Fig. 8
SERIAL DATA EXTRACTION FOR ARRAY OF FIG. 6

4-33

DEVICE 8

FAIRCHILD CMOS • MACROLOGIC • 34703

SERIAL
INPUT

8483 8482 8481 8480
34703

8487 8486 8485 8484

8491 8490 8489 8488

34703

34703

34703

34703

34703

Fig. 9
FINAL POSITION OF A 496·BIT SERIAL INPUT

4·34

8495 8494 8493 8492

34703

34704
DATA PATH SWITCH
FAIRCHILD CMOS MACRO LOG IC*
DESCRIPTION - The 34704 Data Path Switch (DPS) is a combinatorial array for closing data path

LOGIC SYMBOL

loops around arithmetic/logic networks such as the 34705 (Arithmetic Logic Register Stack). A total
of 32 instructions (see Table 1) facilitate logic shifting, byte swapping, masking, sign extension,
introduction of common constants and other operations.

1167891517192123

The 5-bit Ins!!:uc.!ion_w0-.e.d (10-14) selects one ~ the 32 instructions operating on two sets ~ 4-bit
Data Inputs (DO-D3. KO-K3)' Shift Left Input (LI) and Output (LO) and Shift Right Input (R I) and
Output (RO) are available for expansion in 4-bit increments. An active LOW Output Enable Input
(EO) provides for 3-state control of the Data Outputs (00-03) for bus oriented applications.

34704

b

22

The 34704 is packaged in the new slim 24-pin Dual In-Line package.
13 1416182010

VOO

VSS

•
•

EXPANDABLE IN MULTIPLES OF FOUR BITS
TWO 4·BIT DATA INPUT BUSES

•

4-BIT DATA OUTPUT BUS WITH 3-STATE OUl'PJ!":iia:lhERS

•
•
•

USEFUL FOR BYTE MASKING AND SWAP~,:~~1'!i:: c,,::"
PROVIDES ARITHMETIC OR LOGIC SIjI.~iIC':'·' '"
PROVIDES FOR SIGN EXTENSION
....... .

•

NEW SLIM 24-PIN DIP

. . ,..

-'·:.'i,:::"

"'' ,:'

Pin 24
=

Pin 12

CONNECTION DIAGRAM
DIP (TOP VIEW)

,'1"11

PIN NAMES

fl!~'~~::'1 ~~~,ts(Active

DO-D3. KO-K3
10-14

LOW)

In:ij:r:~ction Word Input

[I

Shiii"'''Left Input (Active LOW)
Shift Left Output (Active LOW)
Shift Right Input (Active LOW)
Shift Right Output (Active LOW)
Output Enable I nput (Active LOW)
Data Output (Active LOW)

LO
RI
RO
EO
00-0 3

NOTE:

The

Flatpak version has the same

pinouts (Connection Diagram) as the
Dual In-Line Package.

TABLE'
INSTRUCTION SET FOR THE 34704
INPUTS

OUTPUTS

INPUTS
14 13 12 11

OUTPUTS
10 LO 03 02 01 00 RO

Byte Mask

H

L

L

L

L

H

Byte Mask

H

L

L

L

H K31<3 K2 K, KO

Minus "2" in 2s CompO)

H

L

L

H

L

-RI FiT FiT FiT

K-Bus Sign Extend

H

D-Bus Sign Extend

L

Minus "'" in 2s CompO)

H

L

L

H

H 03 03 02 D, DO

D-Bus Sign Extend

H

L

H

L

L

FUNCTION

14 13 12 11

10 03 02 0,

L

L

L

L

L

L

L

L

L

L

L

L

L

H

H

H

H

L

L

L

H

L

L

L

L

L

L

L

H

H

L

L

H

L

L

00

L

L

H

L

H

L
L
L
D3 02 0,
H
H
H

Byte Mask D-Bus

H

L

H

L

L

L

H

H

L

03 D2 D,. DO Byte Mask D-Bus

H

L

H

H

00 Byte Mask D-Bus

-RI -RI AI FiT FiT

-RI

-

03 02

5,

DO

FiT

FUNCTION
K-Bus Sign Extend

D-Bus Sh ift Left

L

L

H

H

H

L

L

L

L

Byte Mask D-Bus

H

L

H

H

L

H

L

L

L

L

H

H

H

Negative Byte Sign Mask

H

H

L

L

H K3 K2 K, KO Ri
LI 03 02 0, DO
L
H
03 53 02 0, DO
iJ K3 -K2 Kl KO
L

L

H

L

L

H

H

H

H

H

Positive Byte Sign Mask

H

H

L

L

H

KO Byte Mask K-Bus
L Byte Mask K-Bus

H

H

L

H

L

H

H

L

H

H

DO Load Byte

H

H

H

L

L

D3 D2 Dl DO

Complement D-Bus

H

H

H

L

H

K3 K2 K, KO

Complement K-Bus

H

H

H

H

L

Undefined

H

H

H

H

H

Undefined

-

-

L

H

L

H

L

K3 K2 K,

L

H

L

H

H

L

H

H

L

L

L

H

H

L

H

L

H

H

H

L

L
L
L
D3 02 0,
K3 K2 K,
H
H
H

L

H

H

H

H

H

H

H

-

H

KO Load Byte
L Plus "'"
H Zero
H

=

HIGH Level

L "" LOW Level

H

(2) Arith "'" Arithmetic

4-35

D-Bus Shift Right Arith(2)
K-Bus Shift Right

K3 K3 K2 K, KO K-Bus Shift Right Arith(2)
Byte Mask K-Bus
K3 K2 K, KO
H

(1) Comp "'" Complement

*A Trademark of Fairchild Camera and Instrument Corporation.

K-Bus Shift Left
D-Bus Shift Right

H

H

Byte Mask K-Bus

•

34705
ARITHMETIC LOGIC REGISTER STACK
FAIRCHILD CMOS MACROLOGIC*
DESCRIPTION -

The Arithmetic Logic Register Stack (ALRS) is designed to implement general

LOGIC SYMBOL

registers in programmable digital systems. The device contains a 4·bit arithmetic logic unit (ALU), an
8-word by 4-bit RAM and associated control logic. The ALU implements eight arithmetic and logic

functions where one 4-bit operand is supplied from an external source (input data bus) and the second
4-bit operand is supplied internally from one of the eight RAM words selected by the Address Inputs

{AO-A21. The result of the operation performed on the operands is loaded into the same RAM location
and simultaneously loaded into the output register. making it available at the 3-state output data bus.
2 3 4 23 5 6

The 34705 operates on four bits of data but features are provided for expansion to longer word lengths.

21 19 1715

Carry Propagate and Carry Generate outputs are provided for an external carry lookahead where
maximum operating speed is required. In applications where high speed arithmetic is not needed, ripple
expansion may also be implemented. The. 34705 provides three status Signals - Zero, Negative and
Overflow - to qualify the result of an operation.

The 34705 is a member of Fairchild's 34000 CMOS
24-pin Dual In-Line package.

aCrOIC)g,l~':,,,taml,I~~

and is available in the new slim

13
10
11

22

REGISTERS/ACCUMULA]:O~!~:;~';'"~INGLE

•
•
•
•
•
•
•
•

EIGHT GENERAL
PACKAGE
2 MHz MICROINSTUCTION RATE,"':',f"'iil"
VERY LOW POWER - IDEAL FOR ElATfi;,:fi~"OPERATION
EXPANDABLE IN MULTIPLES OF,F
,61~:ill;~
PROVIDES FOR RIPPLE OR CAR
AHEAD
IMPLEMENTS 64 MICROINSTII:LfCTS
PROVIDES THREE STATU$:'S,l~i:;!\i;JjiS- ZERO, NEGATIVE AND OVERFLOW
3-ST A TE OUTPUTS'''' ", l:'" ., ,

•

NEW SLIM 24-PIN

20 18 16 14

9

= Pin

24
8

VDO

VSS "" Pin

PIN NAMES

Y

Data Inputs (Active LOW)
Address Instruction Inputs
ALU I nstruction Inputs
Most Significant Slice Input
Clock Input
Output Enable Input (Active LOW)
Execute I nput (Active LOW)
Data Outputs (Active LOW)
Ripple Carry Output (Active LOW, Note a)
Carry Propagate Output (Active LOW, Note b)
Carry Generate Output (Active LOW, Note cl

Z

Zero Status Output (Active HIGH, Open Drain)

00-0 3
AO-A2
10-12
MSS
CP
EO

EX
00-0 3
W
X

CONNECTION DIAGRAM
DIP (TOP VIEW)

24

23
22
21

NOTES:

a.
b.

20

Vi output also carries instruction information.
X output provides negative status on most significant slice.
Y output provides overflow status on most significant slice.

19
18
17

TABLE 1
INSTRUCTION F!ELD ASSIGNMENT

16
10

12 11 10
L

L L
L H

NOTES:

L

1. Rx is the RAM location addressed bV AO-A2'
2. The result of any operation is always loaded into
the Output Register.

L H H
L H H
H L L

H

INTERNAL OPERATION
Rx plus D-8us plus 1

+

Rx

Rx plus D-Bus + Rx
Rx' D-Bus + Rx (Logic AND)
QwBus

~

H L H
H H L

Rx ® O-Bus

H H H

D·Bus

+

Logic HIGH Level

*A Trademark of Fairchild Camera and Instrument Corporation.

4-36

11

14

12

13

Rx

Rx + F!x
Rx + D-Bus

~

15

NOTE:
+

Rx (Logic OR)

+

Rx

~

Logic LOW Level

Rx

L

The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual I n~Line Package.

FAIRCHILD CMOS MACROLOGIC • 34705
34705 BLOCK DIAGRAM

MSS

®

@
Vi
@
X
@

CONTROL

Y

®

or-"\

~
': "I! "'!I!~i~!,

@

,®

DECODER

I, ®

...

~:~9.~~

'"'"""'"'

'0

OUTPUT
REGISTER

R~
... @

F3

t:
AO

r-

'@
'@

r+-

I1I1

00

.---

D,

r-

D3

Q,
LATCH

0,

Q,

A,

0,

~

WE DO D1 02 03

@
@

0,

@ 0,

~

J

.---I'I'~~!I'!

@ 00

8 X 4 RAM

A,
00 Q, 02 03

.,.,
·0

·3

'i'

(%)

®

'0

~~
CD - Voo = Pin 24
VSS=Pin12
Pin Numbers

0=

4-37

•

FAIRCHILD CMOS MACROLOGIC • 34705
FUNCTIONAL DESCRIPTION - As shown in the Block Diagram, the 34705 Arithmetic Logic Register Stack (ALRS) consists of a 4-bit ALU,
an 8-word by 4-bit RAM with output latches, an instruction'decode network, control logic, and a 4-bit output register.
The ALU receives the active LOW input data (DO-D3) as one operand while the RAM provides the second operand through latches. The ALU
output is stored in both the RAM and output register. The active LOW output data bus (00-03) is obtained from the output register through
3-state buffers. An active LOW Output Enable (EO) input controls these buffers; a HIGH level on EO disables them (high impedance statel.
The instruction bus for the 34705 consists of two fields, A and I; AO, A" A2 specify the desired location on the RAM and 10, I" 12 specify the
desired function to be performed. Table 1 lists Instruction Field Code assignments. Thus, the 34705 provides eight registers (RO-R7) and eight
different operations may be performed on any of these registers. The 10. 11, '2 inputs are decoded by the instruction decode network to generate

necessary control signals for the ALU. The ALU also generates and transmits to the control logic the following signals: carry out, carry
propagate, carry generate, negative status and overflow status. The control logic manipulates the status Signals as a function of 10, 11,12 and a
control input MSS. A HIGH level on the MSS (Most Significant Slice Input) declares the most significant slice in a 34705 array. All devices,
except the most significant 34705, should have a LOW level (ground) on the MSS input. The control logic generates three device outputs, W,
X and Y for arrayed operation of 34705 arrays. An all zero result from the ALU is decoded and presented at the open drain Zero Status (Z)
Output.
The 10 input serves a dual purpose: for arithmetic instructions, it is used as the carry input and for non~arithmetic instructions it serves as an
instruction input. This is possible because only two arithmetic instructions require carry. The dual purpose use of 10 plays an important role
in 34705 expansion schemes.

OPERATION - The 34705 operates on a single clock. CP an' EX are inputs to a 2~input active LOW AN D gate. A microcycle starts as the
clock goes HIGH. For normal operation the Execute (EX)
W. Data is read from the RAM through enabled latches and applied as one
U as the other operand and the operation as determined by instruction lines
operand to the ALU. Data inputs (00-031 are applied
and the result of the operation is written back into the RAM provided that EX
10, I" 12 is executed. When CP is LOW, the latches are'
is LOW. Then A lines must obviously be held stabl
is time. On the LOW~to~HIGH CP transition, the result of the operation is I,oaded
is held HIGH, the operation selected by the I and A inputs is performed, but the
into the output register and a new microcycle c
result is not written back into the RAM a
into the output register.

34705 ARRAYS
The 34705 is organized,
lesser significant slic
Appropriate Carr
for every four 34

n a 4~bit wide data bus but can easily be expanded for longer words. Expansion requires that carries from
ed towards the most significant slice. The 34705 provides full lookahead capability for high speed arithmetic.
) and Carry Propagate (5() outputs are provided so that only one external carry lookahead generator is needed
speed is not a prime consideration, it is possible to implement ripple carry expansion.

In arrayed operatio
t is common to bus EX, CP and EO inputs of ,all devices. The Z output is open drain and is normally
other devices and to an external load resistor so that a HIGH level indicates a zero result from an operation in the array.

OR~tied

with the

Figure 2 sh()ws a ripple carry '6-bit wide array using four 34705s. The MSS input is tied to VDD on the most significant slice (ALRS 4). The
MSS input of the other devices are tied to ground (VSS). The instruction bus of this array consists of A~Field and I~Field. A-Field is obtained by
connecting corresponding A inputs of all 4 devices. The 10 input of device 1 (i.e., least significant slice) in conjunction with the bussed 11,12
inputs forms the I~Field for the array. The 10 inputs of devices 2, 3 and 4 are connected to the Woutputs of devices 1,2 and 3 respectively. The
ALU network generates the carry propagate output. The control logic operates on this signal a~ a function of 11 and 12 to generate the W
output. If both 11 and 12 are LOW O.e., an arithmetic instruction), the Vii output is the carry output of that slice. In case of non~arithmetic
I.Q.structions, it will assume the state of the 10 input. Thus, in Figure 1, if an arithmetic instruction is specified, carry will propagate through the
W output to 10 input of the next higher Significant slice. On the other hand, non-arithmetic instructions will effectively connect all 10 inputs
together to form the I~Field for the array. The Vii output of device 4 is the carry output from the array. The control logic also generates X and
Y outputs which participate in e~pansion when full carry lookahead is required. These outputs are normally ignored in ripple expansion except
for the most significant slice. If a'device is the most significant slice, X and Y correspond to negative and overflow status signals. Thus X output
of Device 4 will be LOW, if the 'reSUlt of an operation has its most significant bit as "1" (i.e., negative result). Similarly a LOW level on Y
output of device 4 indicates that arithmetic overflow has occurred. If the two operands have the same sign and the result has opposite sign,
then it is assumed that an overflow has occurred. It should be noted that W, X and Yare not controlled by EX or CPo Figure 2 shows a 16~bit
array with full carry iookahead expansion. Implementation of the lookahead scheme requires the use of an external 34582 in addition to the
four 34705s in the array. Since device 1 is the least significant and device 4 is the most significant slice, the MSS inputs of the first three devices
are connected to ground while device 4 has a HIGH level at this input. The A-Field for the array instruction bus is obtained by connecting
corresponding A inputs of all four devices. Bussed 11 and 12 inputs together with the 10 input of device 1 form the I-Field for the array. The
10 inputs for devices 2, 3 and 4 are obtained from the 34582 carry outputs (Cn+x, Cn+y and Cn+z respectively). Also the P and G inputs of
34582 are connected to X and Y outputs of the 34705s as shown. The control logiC in the 34705 (see Block Diagraml generates X and Y
outputs as a function of 11, 12 and MSS inputs as well~s the carry generate and carry propagate ~utputs of the ALU. If the MSS input of a slice
is LOW and an arithmetic instruction is specified, its X output will reflect carry propagate and Y will reflect carry generate outputs from that
slice. For an arithmetic instruction the 10 input will be treated as carry~in into a slice irrespective of MSS. Thus, whenever 11 and 12 are LOW,
the array behaves as an adder with full carry lookahead. The VIi outputs still reflect carry output, which is ignored for devices 1,2 and 3. The Vii
carry input to the array so the 10 input of device 1 must be connected to the appropriate 34582 input as shown.
When a non~arithmetic instruction is specified to the array, the control logic of the 34705 forces a LOW level on X and a HIGH level on Y
outputs on all except the most significant slice. An examination of the 34582 logic reveals that whenever P is LOW and G is HIGH, the
associated carry output is the same as the carry input. Thus, in Figure 2, devices 2 3 and 4 will assume the logic level as that presented to the
10 input of device 1 during non~arithmetic instructions effectively bussing 10 through all four d'1vices. As in the case of ripple expanSion, X and
Y outputs of device 4 represent negative and overflow from the array.
'

4-38

FAIRCHILD CMOS MACROLOGIC •

,

0

--r--.

--

-

.--..

,

4

34705

8

~.-.~-------

IT Dl3[) °15
12

10

--

1,;XAOA1A"

DOD1D,D'/,

ALRS 1 34705
MSS

CP EO 00010203 ?

X
Y

~

CLOCK

14

-

ALRS 2 34705

MSS
CP EO
~

II I
J
J 0,
00

01

03

° °,° °
0

2

ALRS3 34705

X
Y

MSS

3 Z

y

~

~

Y

07

MSS

CP EO 0 0 0 1 2 3 Z

y y

09

II

'2 0 0 0 , °2 0 3

ALRS 4 34705

X

CP EO 00010203 Z

all

X
Y

1

VOD

o~ 0;0

d,

65

°°

tl

1,~XAOAh'

,~XAOA""1'2 DOD1D2D!N

(AOA1A"1"DOD 1D,D'/,

JJ f

CARRY OUT
NEGATIVE
OVERFLOW

ZERO

012 0 , 4

013 015

VOO

~----------------DATAOUTPUT----------------

~------------------

DATA IN P U T - - - - - - - -

CARRY OUT
NEGATIVE
O\/ERFLCW

FIG. 2

l _ _ _ .__._
4·39

34706
PROGRAM STACK
FAIRCHILD CMOS MACROLOGIC*

DESCRIPTION -

The 34706 is a 16-word by 4-bit "Push-Down Pop-Up" Program Stack. It is

LOGIC SYMBOL

designed to implement Program Counter (PC) and return address storage for nested subroutines
in programmable digital systems. The 34706 executes four instruc;tions: Return, Branch, Call and

Fetch as specified by a 2-bit instruction. When the device is
is in the top location of the stack. As a new PC value is "

to the stack (Call Operation),
Ion of the stack is the current

all previous PC values effectively _move down one level. T
PC. Up to 16 PC values can be stored, which gives the

the stack (Return Operation) brings the most recent
at the two output buses. The remaining two i
In the Branch Operation a new PC value is I
inputs. In the Fetch Operation, the cont
on the Xo -

ized, the program counter (PC)

evel nesting capability. "Popping"
op of the stack and makes it available
ftect only the top location of the stack.

2 3

23

-<>

CI

7

13

CP

X3 bus and the current
620181614

891011

Voo "" Pin 24
VSS = Pin 12

are provided. The 34

in the new slim 24-

•
•
•
•
•
•
•
•
•

16·WORD BY 4-BIT LIFO
15·LEVEL NESTING CAPABILITY
VERY LOW POWER -IDEAL FOR BATTERY OPERATION
RELATIVE ADDRESSING CAPABILITY
2 MHz MICROINSTRUCTION RATE
PROGRAM COUNTER LOADABLE FROM DATA BUS
OPTIONAL AUTOMATIC INCREMENT OF PROGRAM COUNTER
STACK LIMIT STATUS INDICATORS
NEW SLIM 24-PIN DIP

CONNECTION DIAGRAM
DIP (TOP VIEW)

PIN NAMES
DO-D3

Data I nputs (Active LOW)

10,11

Instruction Inputs

EX

Execute I nput (Active LOW)

CP

Clock Input

MR

Master Reset Input (Active LOW)

Ci

Carry Input (Active LOW)

EQo

Output Enable Input (Active LOW)

00-0 3
)(0-)(3

Output Data Outputs (Active LOW)

11

Address Outputs

12

CO

Carry Output (Active LOW)

SF

Stack Full Output (Active LOW)

SE

Stack Empty Output (Active LOW)

10

* A Trademark of Fairchild Camera and Instrument Corporation

4-40

FAIRCHILD CMOS MACROLOGIC

•

34706

FUNCTIONAL DESCRIPTION - As shown in the Block Diagram, the 34706 consists of an input multiplexer, a 16 x 4 RAM with output
latches addressed by the Stack Pointer (SP), an incrementor, control logic, and output buffers. The 34706 is organized around three 4·bit
buses; the Input Data (D) Bus (00, 01, 02, 03), Output Data (0) Bus (DO, 01, 02, (3) and the Address (X) Bus (XO, Xl, X2, X3). The 34706
implements four instructions as determined by inputs 10 and 11. (See Table I). ThE! O-bus is derived from the RAM output latches and enabled
by the active LOW Output Enable (EOO) input. The X-bus is also derived from the output latches; it is enabled internally during the Fetch
Instruction. Execution of instructions is controlled by the Execute (EX) and Clock (CP) inputs.
FETCH OPERATION - The Fetch Operation places the content of the current Program Counter (PC) on the X-bus. If the carry In (ci) is LOW,
the current PC is incremented in preparation for the next Fetch. If
is HIGH, the value of the current program is unchanged, (Iterative Fetch).

a

The instruction code is set up on the I lines when CP is HIGH. The active level LOW Execute (EX) is normally set up at this time as well. The
control logic interprets 10 and 11 and selects the incrementor output as the data source to the RAM via the input multiplexer. The current PC
value is loaded into the latches and is available on the O-bus if EOO is LOW. When CP is LOW (assuming EX is also LOW) the output latches
are disabled from following the RAM output and the X-bus Output buffers are enabled, applying the current PC to the X-bus. The output of
the incrementor is written into the RAM during the period when CP and EX are LOW. If
is LOW, the value stored in the current PC, plus
one, is written into the RAM. If
is HIGH, the current PC is not incremented. Carry Out (CO) is LOW when the contents of the current PC
is at its maximum, i.e., all ones. When CP or EX goes HIGH, writing into the RAM is inhibited and the Address buffers (XO - X3) are disabled.

a

a

BRANCH OPERATION - During a Branch Operation, the Data Inputs (DO - 03) are loaded into the current program counter.
The instruction code and the EX input are set up when CP is HIGH. The stack poiriter remains unchanged. When CP goes LOW (assuming EX
is LOW), the D-bus inputs are written into the current PC. The X-bus drivers are not enabled during a Branch Operation.
CALL OPERATION - During a Call Operation the conte

he data bus is loaded into the top location of the stack and all previous PC

values are effectively moved down one level.

HIGH. When EX is LOW, a ·'one" is added to the stack pointer value thus
The instruction code and the EX input are set up
is LOW), the D-bus inputs are written into this new RAM location. On the
incrementing the RAM address. When CP is L
LOW-to-HIGH CP transition, the increm"ented
ter value is loaded-into the stack pointer register. When the RAM address is "1111"
further Call Operations should be initiated. If an additional Call Operation is performed
the Stack Full output (SF) is LOW, indi
tion will be written over, SF will go HIGH and the Stack Empty (SE) will go LOW.
SP is incremented to "0000". the conten

is "popped" to become the current PC.

RETURN OPERATION - 0
The instruction is set up
address, presenting t
disabled, thereby
into the stack po

IGH. When EX is LOW, a "one" is subtracted from the stack pointer value, thus decrementing the RAM
PC value through the enabled latches to the three-state O-bus drivers. When CP is LOW, the latches are
current value of the PC. On the LOW-to-HIGH CP transition the decremented stack pointer value is loaded

When the RAM address is "0000", the Stack Empty output (SE) is LOW, indicating that no further return-operations should be initiated. If
an additional Return Operation is performed, SP is decremented to "1111", the SE will go HIGH and the Stack Full output (SF) will go LOW.
Operation oftheactive LOW Master Reset (MR) causes the SP to be reset and the contents of that RAM location (0000) to be cleared. The Stack
Empty (SE) output goes LOW. This operation overrides all other inputs.
MULTIPLE 34706 OPERATION - The 34706 may be expanded to any word length in mUltiples of four without external logic. The connection
for expanded operation is shown in Figure 1. Carry In (a) and carry Out (CO) are connected to provide automatic increment of the current
program counter during the Fetch Operation. The
input of the least significant 34706 is tied LOW to ground; the CO input of the least
significant 34706 is connected to the
input of the next significant 34706.

a

a

MSB

LSB

Da Os 0'100'11
'0

EX

CO

CARRY OUT

CP

SF

STACK FULL

SE

STACK EMPTY

MR---+-+--~~4-4-4-4--+-+-+-+------4--+----~-+-+-+-+--~--~~-----+-+----~
LSB

50

01

MSB
02 03

Xo X1 X2 X3

I

I
ADDAE"SS BUS

DATA BUS

FIGURE 1.34706 EXPANSION A 16 BY 12 PROGRAM STACK
·Tie to

Voo to disable automatic increment.
4-41

FAIRCHILD CMOS MACROLOGIC • 34706

INSTRUCTION

10

L

L

Return (Pop)

L

H

Branch
(Load PC)

THE

INTERNAL
OPERATION

INSTRUCTION

11

TABLE I
SET FOR

34706
O-BUS (WITH
EOO LOW)

X-BUS

Decrement
Stack Pointer

Disabled

New ("popped")
Program Counter
value when EX
goes LOW

Load D-Bus

Disabled

Current Program
Counter until CP
goes HIGH again.
then updated with
newly entered PC
value

Disabled

Current Program
Counter until CP
goes HIGH again.
then updated with
newly entered PC
value

Current Program
Counter while
both CP I¥ EX
are LOW. disabled while CP
or EX is HIGH

Current Program
Counter until CP
goes HIGH again.
then updated with
incremented PC
value

into current

Program
Counter location

H

L

H

H

Call (Push)

gram Counter
ifC! is LOW

H = HIGH Level

L = LOW Level

34706 BLOCK DIAGRAM

DO 5, 52 53
CI

2illC'9~FJI('5J1

®

I

SELECT

~

TTT1
INPUT MUX

I
I
• t t t

WE

I

@

INCREMENTOR
LOGIC

DATA INPUT

'0

~

-~
EX -~

,

CP

Mi'i

CONTROL
LOGIC

COUNT 1
UP/DOWN

-¥-

CP

-~

STACK
POINTER

MR

r--r--- ~
r--- """
r---

16

x 4 STATIC
RAM

DATA OUTPUT

t t t t

ENABLE

LATCHES

•

MR

@
Voo
VSS

o

=Pin 24
= Pin

12

OUTPUT
DRIVERS

II II

0 KV
SF SE

DO 51

°

2 03

@@@@

= Pin Number

4-42

I

I

OUTPUT
DRIVERS

+ ++ t

Xo X,

X2 X3

®G)@@

I

34107
DATA ACCESS REGISTER
FAIRCHILD CMOS MACROLOGIC·

DESCRIPTION - The 34707 Data Access Register (DAR) perform,s memory address arithmetic for
RAM resident stack applications. It contains three 4-bit registers i ' ded for program counter (RO),
stack pointer (R1) and operand address (R2)_ The 34707 i
ts 16 instructions (see Table 1)
which allow either pre or post decrement/increment and
er transfer in a single clock
cycle. It is expandable in 4-bit increments and can op
MHz microinstruction rate on a
16-bit word. The 3-state outputs are provided for bus 0
plications. The 34707 is packaged in
the new slim 24-pin Dual In-Line package.

•
•
•
•

LOGIC SYMBOL

2

3

4

5

21 19

17 15

EXPANDABLE IN 4-BIT INCREMEN.
OPTIONAL PRE OR POST INCR
3-STATE OUTPUTS
2 MHz MICROINSTRUCTI

13

PIN NAMES
8

Word Inputs
puts (Active LOW)
nput (L .... H Edge-Triggered)
Carry Input (Active LOW)
Carry Output (Active LOW)
Execute I nput (Active LOW)
Address Output Enable Input (Active LOW)
Data Output Enable Input (Active LOW)
Address Outputs
Data Outputs (Active LOW)

!!l-13
00-0 3
CP

CT
CO
EX
EO x
EO o
XO-X3

00-0 3

INSTRUCTION

VDD

ON THE NEXT RISING CP EDGE

L

L

L

L

RO

L

L

L

H

RO plus 0 plus CI

L

L

H

L

RO

L

L

H

H

RO plus 0 plus CI

L

H

L

L

RO

L

H

L

H

RO plus 0 plus CI

L

H

H

L

Rl
Rl plus 0 plus CI

Pin 24

23

SEQUENTIAL FUNCTION OCCURRING

10

14

24

AVAILABLE ON THE X-BUS

11

~

20 15 16

CONNECTION DIAGRAM
DIP (TOP VIEW)

COMBINATORIAL FUNCTION

12

10 l'

VSS = Pin 12

TABLE 1
INSTRUCTION SET FOR THE 34707

13

9

22

21

RO plus 0 plus CI .... RO and O-register

20

RO plus 0 plus CI .... Rl and O-register

,.

RO plus 0 plus CI ... R2 and O-register

17

19

16

R1 plus 0 plus CI -+ Rl and O-register

L

H

H

H

H

L

L

L

R2

H

L

L

H

o plus CI

H

L

H

L

RO

H

L

H

H

o plus CI

H

H

L

L

H

H

L

H

R2
R2 plus 0 plus CI

R2 plus 0 plus CI ... R2 and O-register

H

H

H

L

H

H

H

H

Rl
o plus CI

o plus

o pi us. C I .... R 2. and O-register

15
14
13

o plus CI .... RO and O-register

CI .... Rl and O-register

L LOW Level
H = HIGH Level
• A Trademark of Fairchild Camera and I nstrument Corporation.

4-43

NOTE:
The Flatpak version has the same
pinouts (COnnection Diagram) as the
Dual In·Line Package.

FAIRCHILD CMOS. 34707
BLOCK DIAGRAM

0

G) 8)

@

CD

INSTRUCTION
DECDDE

I

@@ @

@
r-

l-1

r

OPERAND ENABLE

.,<01

"~J

SOURCE

,I.'"

~

.~."l.1·

.~

EX
CP

C0

0

J

l: ,.

,

,,:.

REGISTER
ARRAY
3X4

iI"
MULTIPLEXER

REGI TER

Jr ~
f@ J~
00
01

.:'"

1lIIt.,

~.

~~:

I

)

,"~,,..

~
~~

J

P~I ~

4

REG. SELECT
DESTINATION
REG. SELECT

@

I-

ARITHMETIC
UNIT (AU I

J,

J,

-*-l@~
-*-1@ -*l@
l0
1® ~@ 1°
'7

02

Xl

X2

X3

CD

VDD
VSS
0

=
=

PIN 24
PIN 12

• PIN NUMBER

FUNCTIONAL DESCRIPTION - The 34707 contains a 4-bit sl.!!:e £f three registers (RO, R1, R21, a 4-bit adder, a 3-state address output buffer
(XO-X31, and a separate output register with 3-state buffers (00-031, that can put the register contents on the data bus (refer to the Block
Diagraml. The DAR can perform 16 instructions, selected by 10-13, as listed in Table 1.
OPERATION - The 34707 operates en a single clock. CP and E~ a!!l inputs to a two input, active LOW AND gate. For normal operation EX is
LOW. A microcyle starts as the clock goes HIGH. Data inputs 00-03 are applied to the Adder as one of the operands. Three 01, 12, 131 of the
four instruction lines select which of the three registers, if any, is to be used as the other operand. The next LOW-to-HIGH CP transition writes
the result from the Adder into one register (RO, R1, R21 and into the output register provided EX is LOW. If the 10 instruction input is HIGH,
the multiplexer routes the result from the Adder to the 3-state buffer controlling the address bus (XO-X3) independent of EX and CPo If 10 is
LOW, the multiplexer routes the output of the selected register directly into the 3-state buffer controlling the address bus (XO-X31,
independent of EX and CPo
34707 ARRAYS - The 34707 is organized as a 4-bit register slice. The active LOW CI and CO lines allow ripple-carry expansion over longer
word lengths.
APPLICATIONS - In a typical application, the register utilization in the DAR may be as follows: RO is the program counter (PC), R1 is the
stack pointer (SP) for memory resident stacks and R2 contains the operand address. For an instruction fetch, PC can be gated on the X-bus
while it is being incremented !i.e., D-bus = 11. If the instruction fetched calls for an effecti"e address for execution, which is displaced from the
PC, the displacement can be added to the PC and loaded into R2 during the next microcycle.

4-44

34710
16 x 4 BIT CLOCKED RAM WITH 3-STATE OUTPUT REGISTER
FAIRCHILD CMOS MACROLOGIC"
DESCRIPTION - The 34710 is a register-oriented 64-Bit Read/Write Memory organized as 16 words
by four bits. An edge-triggered 4-bit output register allows new data to be written while the previous
data is held. The 3-state data outputs provide flexibility and make the 34710 compatible with the
other bus oriented circuits in the CMOS Macrologic family.

LOGIC SYMBOL

The 34710 consists of a 16 x 4·bit RAM selected by the four Address Inputs (AO-A3) and an
edge-triggered 4·bit output register with 3·state output buffers.
WRITE OPERATION - When the three control inputs; Write Enable (WE), Chip Select (CS), and
Clock (CP), are LOW the information on the Data Inputs (i)0-03) is written into the memory location
selected by the Address Inputs (AO·A3). If the input data changes while WE, CS, and CP are LOW, the
contents of the selected memory location follows these changes, p
ided set-up time criteria are met.

CP

-to-HIGH, the contents of the
d into the Output Register.

Al

READ OPERATION - Whenever CS is LOW and CP goes
memory location selected by the Address Inputs (AO-A3) .

EO is HIGH the four Outputs
, the Outputs are determined by the

A 3-State Output Enable (EO) controls the output
(00-03) are in a high impedance or OFF state; whe
state of the output register.

WE

CS

DO 0, 02 03

AD

34710

A2
A3
EO

00 0, 02 03

•
•

Y Y

EDGE·TRIGGERED OUTPUT REGIS
3-STATE OUTPUTS

I.

14 12 10

Voo = Pin 18
VSS ~ Pin 9

PIN NAMES
Ao-A3
00-0 3

ts Active LOW)
t (Active LOW) Input
Output Enable (Active LOW) Input
Write Enable (Active LOW) Input
Clock Input (L .... H Edge·Triggered)
Buffered Outputs (Active LOW)

CS"
EO
WE
CP

50-0 3

CONNECTION DIAGRAM
DIP (TOP VIEW)

BLOCK DIAGRAM

o WE-r:;::=:(:~
Q)ep

8

18

~~--~~--~--~

0s

I.
17

15
16 X4

14

MI:::MQRY CELL
ARRAY

13

12
11
10

Voo

~

Pin 18

VSS ~ Pin

o

= Pin

9

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual In-Line Package.

@@@)@

Numbers

* A Trademark of Fairchild Camera and Instrument Corporation.

4-45

34731
QUAD 64-BIT STATIC SHIFT REGISTER
FAIRCHILD CMOS LSI

DESCRIPTION - The 34731 is a Quad 64-Bit Shift Register eac
(DA-DD), Clock Inputs (CPA-CPO) and Data Outputs (Q63A-

with separate Serial Data Inputs
from the 64th register pOsition.

CONNECTION DIAGRAM
DIP (TOP VIEW)

gister position and all the data
transition of the Clock Inputs

Information present on the Serial Data Inputs is shifted int
in the register is shifted one position to the right on e
(CPA-CPO).
Low impedance outputs are provided for direct

14

13

•
•
•
•
•

FREQUENCIES UP TO 4 MH
SERIAL-TO-SERIAL OAT
SEPARATE CLOCK IN
FULLY BUFFERED
DIRECT INTERF
14-PIN PACKAGE

12
11
10

PIN NAMES

NOTE:
The F latpak version has the same
pinouts (Connection Diagram) as the
Dual I n-Line Package.

DA-DD

Serial Data Inputs

CPA-CPO

Clock Input (H-+L Edge-Triggered)

0s3A-Q 63D

Buffered Outputs from the 64th Register Position

LOGIC SYMBOL

'0
"s3A

10

CPA

'0 '0

1 2 - D.
Q S3B

11

"s3c

-8

13--<= CPs

5

Voo =
VSS =

Pin 14
Pin 7

4-46

CP

c

"s3D

1

3

CPo

2

BIPOLAR INTERFACE CIRCUITS FOR CMOS

5-1

BIPOLAR INTERFACE CIRCUITS FOR CMOS

CMOS TO TTL DRIVER

CMOS TO 7-SEGMENT LED DISPLAY

9LS04 Hex Inverter
(Reference: Fairchild Low Power TTL Data Book)

9374 7-Segment Decoder/Driver/Latch
(Reference: Fairchild 9374 Data Sheet)

When multi-TTL drive capability is required, the CMOS 34049 and
34050 Hex Buffers can be used to drive two standard TTL loads with
typical delays of 45 ns (V DO = 5 V). However, the 9LS04 drives five
standard TTL loads with typical delays of 5 ns. The 9LS04 must be
operated from a 5 V TTL supply, but it can accept input voltage to
11 V, allowing its use with CMOS operated up to 10 V.

This bipolar device contains latches for storage, a 7-segment decoder

•
•
•
•
•

and 15 mA constant current drivers. The 9374 must operate at 5 V; its
inputs are also limited to 5 V.

•
•
•
•

34000 COMPATIBLE INPUTS
DRIVES FIVE TTL LOADS
5 ns DELAY
ACCEPTS 11 V INPUTS
2 mW PER INVERTER

•

HIGH SPEED INPUT LATCHES FOR DATA STORAGE
15 rnA CONSTANT CURRENT SINK CAPABILITY TO
DIRECTLY DRIVE COMMON ANODE LED DISPLAYS
INCREASES INCANDESCENT DISPLAY LIFE
DATA INPUT LOADING ESSENTIALLY ZERO
WHEN LATCH DISABLED
AUTOMATIC RIPPLE BLANKING FOR SUPPRESSION OF
LEADING EDGE ZEROS AND/OR TRAILING EDGE ZEROS
9374
LOGIC SYMBOL

9LS04 LOGIC AND CONNECTION DIAGRAM
DIP (TOP VIEW)

vee
712635

4 13 12 11 10 9 15 14

MOS TO LED DIGIT DRIVER

Vcc
GND

9664 MOS to LED Digit Driver
(Reference: Fairchild 9664 Data Sheet)
This driver is ideal for driving high current devices such as LEOs, relays
and lamps. High input impedance allows direct drive from 34000 CMOS
devices: however, there is some degradation in logic level at the CMOS
output. The 9664 is specified to 10 V operation, the 9664A to 20 V.
•
•
•
•
•

Pin 16
Pin 8

9374
CONNECTION DIAGRAM

150 mA SINK CAPABILITY
CMOS COMPATIBLE INPUTS
VERY LOW STANDBY POWER
SIX HIGH GAIN DARLINGTON CIRCUITS
10 AND 20 V OPERATION
16

9664/9664A LOGIC AND CONNECTION DIAGRAM
DIP (TOP VIEW)

15
14
13

12

OUTPUT 1

INPUT 1

OUTPUT 2

OUTPUT 6

11

INPUT 6

10

INPUT 2
Vao (GND)
INPUT 3

vee
INPUT5

OUTPUT 3

OUTPUT 5

OUTPUT 4

INPUT 4

5-3

BIPOLAR INTERFACE CIRCUITS FOR CMOS (Cant/d)

ONE-SHOT MULTIVIBRATOR

VOLTAGE COMPARATOR

96L02 Low Power Dual
Retriggerable Resettable Monostable Multivibrator
(Reference: Fairchild Low Power TTL Book)

J.LA775-Quad Comparator
(Reference: Fairchild J.LA775 Data Sheet)
I n a CMOS system it may be necessary to detect differences between
two voltage levels and convert to logic levels. The p.A 775 Quad
Comparator is capable of operating over the CMOS power supply range.
These comparators have a unique characteristic in that the input
common mode voltage range includes ground, even though operated
from a single power supply voltage. Applications include limit
comparators, simple analog to digitai converters; pulse, squarewave and
time delay generators and wide rang. VC,O.

The 96L02 is pin and function compatible with the 34528 Dual
Monostable and exhibits improved stability and speed. It is usable in
5 V CMOS systems.
•
•
•
•
•
•
•

TYPICAL POWER DISSIPATION OF 25 mW/ONE SHOT
50 ns TYPICAL PROPAGATION DELAY
RETRIGGERABLE 0 TO 100% DUTY CYCLE
34000 COMPATIBLE lIiIPU-rS
OPTIONAL RETRIGGER LOCK·OUT CAPABILITY
PULSE WIDTH COMPENSATED FOR VCC AND
TEMPERATURE VARIATioNS
RESETTABLE

•
•
•
•
•
•
•

96L02 LOGIC AND CONNECTION DIAGRAM
DIP (-rOP VIEW)

SINGLE SUPPLY OPERATIPN-+2.0 V TO +36 V
COMPARES VOLTAGES NEAR GROUND POTENTIAL
LOW CURRENT DRAIN-700 p.A TYPICAL
COMPATIBLE WITH ALL FORMS OF CMOS
LOW INPUT BIAS CURRENT -~5 nA TYPICAL
LOW INPUT OFFSET CURRENT -25 nA
LOW OFFSET VOL TAGE-S mV MAX
LOGIC AND CONNECTIQN DIAGRAM
DIP (TOP VIEW)
OUTPUT 2

OUTPUT 3

OUTPUT 1

OUTPUT 4

v+

1"

16

2'

,.'

GND

INPUT 1-

INPUT 4+

INPUT 1+

INPUT 4-

INPUT 2-

INPUT 3+

INPUT 2+

INPUT 3-

14'
13

12

POWER SUPPLY REGULATOR

11

J.LA78MG 4-Terrriinal ~egulator
(Reference: Fairchild J.LA78 MG. J.LA79 MG Data Sheet)

10

This single compact regulator with its 500 mA capability is sufficient
for all but the very largest CMOS systems. The adjustable output
voltage feature allows fine tuning of system speed product.
•
•
•
•
•
•

* Leads for external timing

OUTPUT CURRENT IN EXCESS OF 0.5 A
POSITIVE OUTPUT VOLTAGE 5 TO 30 V
INTERNAL THERMAL OVERLOAD PROTECTION
INTERNAL SHORT CIRCUIT CURRENT PROTECTION
OUTPUT SAFE AREA PROTECTION
POWER MINI DUAL IN·LINE PACKAGE
p.A78 MGCONNECTION DIAGRAM
DIP (TOP VIEW)

1NPUOT4

COMMON

OUTPUT

2

3

C~NTROL

NOTE: Heat sink tabs connected to common

5·4

FAIRCHILD ORDERING INFORMATION
AND PACKAGE OUTLINES

6-1

ORDER AND PACKAGE INFORMATION

Fairchild CMOS circuits may be ordered using a simplified purchasing code where the package style and temperature
range are defined as follows:

PACKAGE STYLE
D = Dual In-line - Ceramic (hermetic)
P = Dual In-line - Plastic
F = Flatpak

T
D

C

T

Temperature
Range Code
Package
Code

L -_ _ _ _ _ _

~---------

Device
Type
Fairchild

In order to accommodate varying die siz!ls and numbers of leads (14, 16, 24, etc.), a number of different package forms
are required. The Package Information list on the following pages indicates the specific package codes currently used for
each device type. The detailed package outline corresponding to each package code is shown at the end of this section.
Temperature Range
Two Basic temperature grades are in common use: C = Commercial-Industrial, 40°C to +85°C; M
+125 'C. Exact values and conditions are indicated on the data sheets.

=Military, -55°C to

Examples
(a)

34014FM
This number code indicates a 34014 Register in a Flatpak with military temperature rating.

(b)

34720DC
This number code indicates a 34720 256 x 1 RAM in a ceramic Dual In-line package with commercial temperature
rating.

Device Identification/Marking
All Fairchild standard catalog CMOS circuits will be marked as follows:

MILITARY (M)
-55°C to +125°C
DEVICE

CERAMIC
DIP (D)

FLATPAK (F)

34001
34002
34011
34012
34013
34014
34015
34016
34017
34019
34020
34021
34023

6A
6A
6A
6A
6A
6B
6B
6A
6B
6B
6B
6B
6A

31
31
31
31
31
4L
4L
31
4L
4L
4L
4L
31

I

~ F Device Type XX
['

Date Code

J

COMMERCIAL (C)/INDUSTRIAL
-40°C to +85°C
CERAMIC
DIP(D)
6A
6A
6A
6A
6A
6B
6B
6A
6B
6B
6B
6B
6A

6-3

PLASTIC
DIP (P)
9A
9A
9A
9A
9A
9B
9B
9A
9B
9B
9B
9B
9A

FLATPAK (F)
31
31
31
31
31
4L
4L
31
4L
4L
4L
4L
31

•

ORDER AND PACKAGE INFORMATION

DEVICE

CERAMIC
DIP(D)

34024
34025
34027
34028
34029
34030
34035
34040
34042
34049
34050
34051
34052
34066
34068
34069
34070
34071
34077
34078
34081
34085
34086
34099
34104
34512
34518
34520
34539
34555
34556
34702
34720
34723
34725

6A
6A
68
68
68
6A
68
68
68
68
68
68
68
6A
6A
6A
6A
6A
6A
6A
6A
6A
68
68
68
68
68
68
68
68
68
68
68
68

340085
340097
340098
340160
340161
340182
340163
340174
340175
340192
340193
340194
340195

68
68
68
68
68
68
68
68
68
6B
68
68
68

MILITARY (M)
-55°C to +125°C
FLATPAK (F)

+:.
---.-

I

SA

I

31
31
4L
4L
4L
31
4L
4L
4L
4L
4L
4L
4L
31
31
31
31
31
31
31
31
31
31
4L
4L
4L
4L
4L
4L
4L
4L
4L
4L
4L
4L

COMMERCIAL (C)/INDUSTRIAL
-40°C to +85°C
PLASTIC
FLATPAK (F)
DIP (P)

-------

,CERAMIC
DIP (D)

c--------- ---_..

4L
4L
4L
4L
4L
4L
4L
4L
4L
4L
4L
4L
4L

6A
6A
68
68
68
6A
68
68
68
68
68
68
68
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
68
68
68
68
68
68
68
68
68
68
68
68

9A
9A
98
98
98
9A
98
98
98
98
98
98
98
9A
9A
9A
9A
9A
9A
9A
9A
9A
9A
98
98
98
98
98
98
98
98
98
98
98
98

68
68
68
68
68
68
6B
68
68
68
68
68
68

98
98
98
98
98
98
9B
98
98
98
98
98
9B

I

31
31
4L
4L
4L
31
4L
4L
4L
4L
4L
4L
4L
31
31
31
31
31
31
31
31
31
31
4L
4L
4L
4L
4L
4L
4L
4L
4L
4L
4L
4L
4L
4L
4L
4L
4L
4L
4L
4L
4L
4L
4L
4L
4L

~---------------------------------------------------------------------~

6-4

MATRIX VI PROGRAM ORDERING INFORMATION

Matrix VI is a full spectrum/cost effective reliability and quality program for commercial/industrial ICs only. It features
six levels of screening/package flows, each tailored to a user's field application/environment and his incoming quality/
equipment reliability requirements.
A Matrix VI part number consists of the device type followed by the package code letter, the temperature range code letter,
and the Matrix VI code letter (as applicable, see flow chart).

o

C X X

~

Designates additional Matrix VI Processing (Levels, 2,4,5,6)
Temperature Range Code ("C" for -40°C to +85°C operation)
Package Code ("0" for ceramic DIP, "P" for plastic molded DIP, and "F" for Flatpak)
Device Type

EXAMPLES
(a)

34001 PC

Device type 34001, packaged in plastic Dual In-Line (P), in commercial temperature range (C)
and processed to Matrix VI Level 1.

(b)

34oo1PCQM

Device type 34001, packaged in plastic Dual In-Line (P), in commercial temperature range (C(
with supplemental Matrix VI Level 2 testing including 100% thermal shock, "hot rail" test and
0.15% AQL functional testing.

(c)

34001 DC

Device type 34001, packaged in ceramic Dual In-Line (D), in commercial temperature range
and processed to Matrix VI Level 3.

(d)

34001 DCQM

Device type 34001, packaged in ceramic Dual In-Line, in commercial temperature range (C)
with supplemental Matrix VI Level 4 screening including second 100% DC/functional testing
and 0.15% AQL functional testing.

(e)

34001PCQR

Device type 34001, packaged in Dual In-Line, in commercial temperature range (C) with suP"
plemental Matrix VI Level 5 screening including 100% thermal shock, "hot rail" test, 168 hours
125°C burn-in and 0.15% AQL functional testing.

(f)

34001 DCQR

Device type 34001, packated in ceramic Dual In-Line, in commercial temperature range with
supplemental Matrix VI Level 6 screening including burn-in, three 100% DC/functional tests
and 0.15% AQL functional testing.

6-5

•

6 MATRIX VI PROCESS FLOW OPTIONS & COST EFFECTIVENESS

KEY
100% OPERATION

I~H" <~SA~P~E ?@%I

C»

m

CERAMIC PACKAGED DEVICES

PLASTIC MOLDED DEVICES

FUNCTIONAL. +25°C. 0.28% AOL
DC. +25°C. 1.0% AOL
DC. +85°C. 2.2% AOL
DC. -4Q°C. 2.2% AOL
AC. +2.5.°(;,.1.:6% A~~
·.z.:::;·;·::::::·::::·;·;·;·

(PC)

1.

.

...;:::':;::::':':

;::::;:.:.-

-.::::::':':'

LEVEL 2.
(PCOM)

LEVEL 3.
(DC)

LEVEL 4.
(DCOM)

LEVEL 5.
(PCOR)

1

LEVEL 6.
(DCOR)

THERMAL SHOCK
LlQUID-TO-L1QUID

THERMAL SHOCK
L1QUID-TO-L1QUID

ooe TO +100°C

OOC TO +100°C

883/1011/A

883/1011/A

BURN-IN 883/1015/C
168 HRS, +125'C

DC & FUNCTIONAL
+25°C

1% PDA LOT REJECTION
CRITERIA APPLIED TO
LOTS EXHIBITING MORE
THAN 1% !NTERMITIENTS
THROUGH HOT RAIL TEST

'".:.,

COST EFFECTIVENESS ANALYSIS
RELIABILITY FACTOR
=lX
QUALITY GUARANTEE
ON FUNCTIONALITY
= O.28%AQL
COST SEQUENCE 1

RELIABILITY FACTOR

" 1.4X
QUALITY GUARANTEE
ON FUNCTIONALITY
=O.15%AQL
COST SEQUENCE 2

RELIABILITY FACTOR

=2X
QUALITY GUARANTEE
ON FUNCTIONALITY
= 0.2% AOL
COST SEQUENCE 3

RELIABILITY FACTOR
=2.3X
QUALITY GUARANTEE
ON FUNCTIONALITY
=0.15%AQL
COST SEQUENCE 4

RELIABILITY FACTOR
"7.SX - 9X (1)
QUALllY' GUARANTEE
ON FUNCTIONALITY
=0.15%AQL
COST SEQUENCE 5

NOTE:

1.

Burn-in has the same relative effectiveness for plastic molded devices as for ceramic/hermetic packaged devices. Assuming a controlled (air conditioned and constant power)
application/environment, the reliability factor would be approximately 9X. But should the field application be in a less controlled and power onloff application, the reliability
would be approximately 7.Sx'

UNIQUE 38510
-T
CLASS

S

CLASS
OA

CLASS

CLASS

OB

OB'

CLASS
OC

CLASS
OP

PRESEAL VISUAL
FAIRCHILD STD
FICF·ST·2011

SEAL

~
00

TEMP CYCLE
CONDo C

TEMP CYCLE
COND.C

TEMP CYCLE
COND.C

TEMP CYCLE
CONDo C

HERMETICITY
SPECIFY

HERMETICITY
COND.A/B
CONO. C1·2

HERMETICITY
COND.A/B
CONDo C2

HERMETICITY
CQND.NB
CQND.C1·2

HERMETICITY
CONO. AlB
CONDo C2

HERMETICITY
SAMPLE
1.0AQL FINE
0.4 AQL GROSS

POST B/I ELECT
SPECIFY

POST B/I ELECT
25°C DC
125°C DC
_55°C DC
25°C AC
25°C FUNCTIONAL

POST B/I ELECT
25°C DC
25°C FUNCTIONAL

POST B/I ELECT
25°C DC
125°C DC
_55°C DC
25°CAC
25°C FUNCTIONAL

ELECTRICAL
25°C DC
25°C FUNCTIONAL

POST BII ELECT
25°C DC

I

'"cD

EXTERNAL VISUAL
100%

EXTERNAL VISUAL
100%

QUALITY
CONFORMANCE
GPA,B & C

QUALITY
CONFORMANCE
GPA,B&C

QUALITY
CONFORMANCE
GPA,B & C

EXTERNAL VISUAL

EXTERNAL VISUAL
100%

EXTERNAL VISUAL

100%

100%

• Upon customer request only. Class B processing in this case includes adding post burn-in testing; de testing at +125°C and _550 C and ae testing.
at 25°C.

•

i

PROCESS SCREENING REQUIREMENTS
MI L-STD-883 TEST METHODS

DESCRIPTION

Preseal Visual MTD. 2010.1 :

Condo A Maximum Visual Criteria
Condo B Optimum Visual Criteria
FICF-ST-02011 Fairchild Standard

Bond Strength:

Bond strength is monitored on a sample basis three times per shift per mach.

Seal:

Devices are
requirements

High Temperature Storage:

Condo B Tstg ~ 125°C Specify Time
Condo C Tstg ~ 150°C
Condo D Tstg ~ 200°C

Thermal Shock MTD 1011:

Condo A 0° /100° C 15 cycles
Condo B _55° /125° C

Temperature Cycle MTD 1010:

Condo B _55° /125° C
Condo C _65° /1500 C 10 cycles
Condo D _65° /200°C

Mechanical Shock MTD 2002:

Condo A 500 Gs 5 Shocks in Xl, X2
Condo B 1500 Gs Yl, Y2, Zl & Z2

Constant Acceleration MTD 2001:

Condo D 20000 Gs 2 minute in each
Condo E 30000 Gs Xl X2 Yl Y2
Condo F 50000 Gs Zl Z2

Hermetic Seal MTD 1014:

Condo
Condo
Condo
Condo

Pre Burn-in Electrical (5004.1):

25°C DC electrical testing to remove rejects prior to submission to burn-in
screen

Burn-in Screen MTD 1015:

Cond.A,Cond. B,Cond.C
Condo D and Condo E

Post Burn-in Electrical (5004.1):

Post Burn-in electrical screening to cull out devices which failed as a result
of burn-in. Test Parameters may include: 25°C DC, 125°C ~C,
-55°COC, 25°C AC and 25°C Functional tests.

Radiography MTD 2012:

6X,

Quality Conformance Inspection MTD 5005: 1:

Group A:
Group B:
Group C:

External Visual MTD 2009:

3X, 20X magnification: Verify dimensions, configuration, lead structure,
marking and workmanship

hermetically

sealed

for

compliance to

MI L-STD-883

A Fine-Helium 5xl0-8 cc/sec
B Fine-Radiflo 5xlO- 8 cc/sec
Cl Gross-FC43/Hot 10- 3 cc/sec
C2 Gross-FC78/Vacuum 1O- 5 cc/sec

ax magnification and criteria specify number of views
Electrical Characteristics
Package oriented Tests
Environmental and Life Tests

6-11

I

UNIQUE 38510 PROGRAM ORDERING INFORMATION

The Fairchild Unique 38510 Program is written in accordance with MIL-M-38510 and MIL-STD-883
To meet the need of improved reliability in the military market, CMOS Integrated Circuits are available with special
processing. Devices ordered to this program are subjected to the 100% screening as outlined in the Process. Devices will be
marked in accordance with MI L-M-3851 0 unless otherwise specified under number OPtion 6.
UNIQUE 38510 devices are not normally stocked by distributors.
Customer procurement documents should specify the following:
(a)
(b)
(e)
(d)

Fairchild Product Code indicating the basic device type and package combination.
The Unique 38510 Device Class. (A, B, C, S, P)
Number and/or Letter Options required.
Special Marking requiremen1S.

The order code number consists of (a) and (b) as shown above. The order code detailed format is shown below.
D

34000

t

t

t

TEMPERATURE RANGE
C = _40°C TO +85°C(59X)
M = -55°C TO +125°C(51X)

DESIGNATES UNIQUE 38510 PROCESSING IF
REQUIRED. SEE DESCRIPTION OF SCREENING
REQUIREMENTS

t

DEVICE
TYPE

QX

M

PACKAGE TYPE
CERAMIC DIP
D
P
PLASTIC DIP
F
CERAMIC FLAT

Order code examples are:
34029FMQB
Class QB Unique 38510

34001DMQC
Class QC Unique 38510

Number Options: These options apply to operations performed on each unit delivered:
OPTION 1

Lead form to dimensions in detail specifications, followed by hermetic seal tests.

OPTION 2

Hot solder dip finish.

OPTION 3

Read and record critical parameters before and after burn-in.

OPTION 4

Initial'qualification, Group B & C quality conformance not required.

OPTION 5

Radiographic inspection shall be performed on all devices.

OPTION 6

Special marking required.

OPTION

.7

Non-conforming variation - refer to procurement documents for details (must be negotiated with factory).

Letter Options: These options apply once per Purchase Order or line item and are considered Test Charges:
OPTION A

Group B testing shall be performed on customer's parts.

OPTION B

Group C testing shall be performed on customer's parts.

OPTION C

Generic data to be supplied from the latest completed lot.

OPTION D

Unique 38510 program plan, pertinent to the device family being purchased, shall be supplied.

6-1.2

PACKAGE OUTLINES
CERAMIC FLATPAKS -

USED ON ALL FM DEVICES

4L

31

In Accordance with
JEDEC TO-86 Outline
14-Lead Cerpak

16-Lead Cerpak

16 -

=-~---=---I
-

----

.050
TYP .
.4{)9

T
.006
260
1.-_.240-----j
I

t=~~___
i---~~i -- .. -j

!.065

I

..J _ _-----,

.055

NOTES:

All dimensions in inches
Leads are gold-plated kovar
Package weight is 0.26 gram
Hermetically sealed alumina package
Lead 1 orientation may be either tab or dot

NOTES:

All dimensions in inches
Leads are gold-plated kovar
Package weight is 0.4 gram
Hermetically sealed beyyllia package

4M
24- Lead BeO Cerpak

~~-fI

1.
2
3
4
5
6
7
8
9
10
11

L
-,-.019
.015
TYP.

I

.350

22
21
20

19~~~~

T
:~~j
:!~

.620

KT

112

1----.250---1

.090
.065

j

I

.006

.004

NOTES:

I

I--- ---I
.395
.365

All dimensions in inches
Leeds ere gold-plated kovar
Package weight is 0.8 gram
Hermetically sealed beryilia package

6-13

•

PACKAGE OUTLINES
CERAMIC PACKAGES -

USED ON ALL DC AND OM DEVICES

68

6A
14-Lead Ceramic Dual In-Line

16-Lead Ceramic Dual In-Line

r-

k--

;~-----I

8
.025 R
NOM .

.271

.245

_I Yr-,-.,..,...,...,...,..,-,-,-...,.-,--fT'

~~:

I-rJ.......rt.-

,

020~1-016

015
MIN

~Seatlng

IT
i

~~~-~

I Plan.-

011_
O~

095
065

I--NOM-----1
375
I

riP.
NOTES:

All dimensions in inches
Leads are intended for insertion in hole
rows on .300" centers
They are purposely shipped with "'positive"
misalignment to facilitate insertion
Board·drilling dimensions should equal your
practice for .020 inch diameter lead
Leads are tin·plated kovar
Package weight is 2.0 grams

NOTES:

All dimensions in inches
Leads are intended for insertion in
hole rows on .300" centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board·drilling dimensions should equal your
practice for .020 inch diameter lead
Leads are tin·plated kovar
Package weight is 2.0 grams
'The .037/.027 dimension does not apply
to the corner leads

24-Lead Ceramic MSI Dual In-Line

r::::~::j
112111098

6

4 32 1

.030 R
.020

.575
.515

L

1415 61718192021222324

.:j I.'=-.~

--i

L~g
Ir=N~~

.210

~~:g;~
L
'J
~

.200
.100

-I

t

~1l0
.090
TYP.

NOTES:

.037
.027
ST~o'NF

~~.020
.016

.

Sea,;..

~.n.

I~
U~+
1-- -----I
750
MAX.

All dimensions in inches
Leads are intended for insertion in hole
rows on .700" centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Leads are tin-plated kovar
Package weight is 6.5 grams
Package material is alumina

6-14

6N

PACKAGE OUTLINES
CERAMIC PACKAGES -

USED ON ALL DC AND OM DEVICES

60
24-Lead Ceramic Dual In-Line

I'

1.200----1
MAX. IV\I\IV\ 1

{·• I:::::::::::{·~L "
~~II'~

i

.065
.045

-+j

.025

NOM.

1-- 1
1/°\1
~
~a~~ng -F~\

.190

400

'l"WtNtiitWf
~ ~~
.

.135
.115

t

i i

---I

.110
1-090

.037
.027
STANDOFF
WIDTH

TIP.

NOTES:

II .020
--11-- .016

~500~
MAX.

All dimensions in inches
leads are intended for insertion in hole
rows on .50Q" centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal your
practice for .020 inch diameter lead
leads are tin-plated kovar

70
18-Lead Ceramic Dual In-Line

025R

,170
219

I-~-J8Z -~'I

r-~3f-~1'~i'f ~
+_.
1

. . _..:

011
OOg-

I"

.135
115

II

.037
..... ~.027

I'

.020
---ro-016

STANDOFF

-

-- ~;i. ------1

WIDTH

NOTES:

All dimensions in inches
Leads are intended for insertion in
hole rows on .300" centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal your
practice for .020 inch diameter lead
leads are tin-plated kovar

6-15

PACKAGE OUTLINES
PLASTIC PACKAGES -

USED ON ALL PC DEVICES

98

9A
14-Lead Plastic Dual In-line

16-Lead Plastic Dual In-line

,rrn A~~
020

f-

%T:~j~-bu::(J=m1
.-t _____

~ ~ ~ I~i

. 150
100

1....

,

I .110

·--1- ,090
TYP.

NOTES:

All dimensions in inches
Leads are intended for insertion in hole
rows on .300" centers.
They are purposely sh ipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal your
practice for .020 inch diameter lead
Leads are tin-plated kovar
Package weight is 0.9 gram
Package material is silicone

NOTES:

~;; II

__ i I
.020
i f- .027 -, I - ,016
STANDOFF
WIDTH

1!-5°TYP

. ,i

149
139

,-

-!---.-,
I

I

NOTES:

I

~ ~,060
All dimensions in inches
Leads are intended for insertion in hole
rows on .300" centers.
They are purposely sh ipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal your
practice for .020 inch diameter lead
Leads are tin-plt;tted kovar

6-16

L-

375 NOM.-

.-1

All dimensions in inches
Leads are intended for insertion in hole
rows on .300" centers.
They are purposely sh ipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal your
practice for .020 inch diameter lead
Leads are tin-plated kava,
Package weight is 0.9 gram
'The .037/.027 dimension does not apply
to the corner leads

r~

050---...i

ni

l

18-Lead Plastic Dual In-line

'~7~. !

---' 010

9M

PACKAGE OUTLINES
PLASTIC PACKAGES -

USED ON ALL PC DEVICES

9N
24-Lead Plastic MSI Dual In-Line

r-

1.260

T--1 ~~~~~~~N\I\I\~
(

.560
.540

~

I

J3

V

045
035 R

24

L~-~~VIW'V!,"I\V'WW~~''VJ!11I
-I I-g~~
-.-1 L090
.065
165
.145

.~j
rI'
'~=""
+-I
::L_~

!I

I I

135
:1l5

-----j

110
037
r-",090 -j f-'-:027

TYP

...-

Seating

~- -I-Plane-

[I

020

-d--.'016

ST~rD~FF

NOTES: All dimensions in inches
Leads are intended for insertion in
hole rows on .700" centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal your
practice for .020 inch diameter lead
Leads are tin-plated kovar

•
9U

24-Lead Plastic Dual In-Line

165
145

t-~'020MiN
-~ Seating
'I
~-

+=1
-

135
.115

I I .110
----j f-.090
TYP.

II~.

L037
.027

J!

.020
,r--.016

ST~~&WF

NOTES: All dimensions in inches
Leads are intended for insertion in hole

rows on .500" centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal your
practice for .020 inch diameter lead
Leads are tin-plated kovar

6-17

FAIRCHILD FIELD SALES OFFICES
AND DISTRIBUTOR OUTLETS

7-1

FAIRCHILD FRANCHISED DISTRIBUTORS
ALABAMA
HALLMARK ELECTRONICS
4739 Commercial Drive
Huntsville, Alabama 35805
Tel: 205-837-8700 TWX: 810-726-2187
HAMILTON/AVNET ELECTRONICS
805 Oster Drive, N.W.
Huntsville, Alabama 35805
Tel: 205-533-1170
Telex: None - use HAMAVLEC8 DAL 73-0511
(Regional Hq. in Dallas, Texas)
ARIZONA
HAMILTON/AVNET ELECTRONICS
2615 S. 21st Street
Phoenix, Arizona 85034
Tel: 602-275-7851 TWX: 910-951-1535

G.S. MARSHALL COMPANY
5633 Kendall Court
Arvada, Colorado 80002
Tel: 303-423-9670 TWX: 910-938-2902
HAMILTON/AVNET ELECTRONICS
5921 N. Broadway
Denver, Colorado 80216
Tel: 303-534-1212 TWX: 910-931-0510
CONNECTICUT
HAMILTON/AVNET ELECTRONICS
643 Danbury Road
Georgetown, Conaecticut 06829
Tel: 203-762-0361
TWX: None - use 710-897-1405
(Regional Hq. in Mt. Laurel. N.J.)
SCHWEBER ELECTRONICS

(shipping address)
195 Spangler Avenue
Elmhurst Industrial Park

Elmhurst, Illinois 60126
Tel: 312-279-1000 TWX: 910-254-0169
INDIANA
PIONEER INDIANA ELECTRONICS, INC.
6408 Castleplace Drive
Indianapolis, Indiana 46250

Tel: 317-849-7300 TWX: 810-260-1794
SEMICONDUCTOR SPECIALISTS, INC.
(mailing address)
Weir Cook Airport

P.O. Box 41630
Indianapolis, Indiana 46241

LIBERTY ELECTRONICS/ARIZONA
3130 N. 27th Avenue
Phoenix, Arizona 85016
Tel: 602-257-1272 TWX: 910-951-4282

Danbury, Connecticut 06810
Tel: 203-792-3500

(shippmg address)
1885 8anner Ave.
Indianapolis, Indiana 46241
Tel: 317-243-8271 TWX: 810-341-3126

CALIFORNIA
AVNET ELECTRONICS
10916 W. Washington Blvd.
Culver City, California 90230
Tel: 213-558-2345 TWX: 910-340-6364

FLORIDA
HALLMARK ELECTRONICS
1302 W. McNab Road
Ft. Lauderdale, Florida 33309
Tel: 305-971-9280 TWX: 510-956-3092

IOWA
SCHWEBER ELECTRONICS
Suite 302, Executive Plaza
4403 First Avenue S.E.
Cedar Rapids. Iowa 52402
Tel: 319-393-9125

ELMAR ELECTRONICS
2288 Charleston Rd.
Mountain View, California 94042
Tel: 415-961-3611 TWX: 910-379-6437

HALLMARK. ELECTRONICS
7233 Lake Ellenor Drive
Orlando, Florida 32809
Tel: 305-855-4020 TWX: 810-850-0183

HAMILTON ELECTRO SALES
10912 W. Washington Blvd.
Culver City, California 90230
Tel: 213-55B-2121 TWX: 910-340-6364

HAMILTON/AVNET ELECTRONICS
4020 North 29th Avenue
Hollywood, Florida 33021
Tel: 305-925-5401 TWX: 510-954-9808

HAMILTON/AVNET ELECTRONICS
575 E. Middlefield Road

SCHWEBER ELECTRONICS
2830 North 28th Terrace
Hollywood, Florida 33020
Tel: 305-927-0511 TWX: 510-954-0304

Mountain View, California 94040

Tel: 415-961-8600 TWX: 910-379-6486
HAMILTON/AVNET ELECTRONICS
8917 Complex Drive
San Diego, California 92123
Tel: 714-279-2421
Telex: HAMAVELEC SDG 69-5415
G.S. MARSHALL COMPANY
9674 Telstar Avenue
EI Monte, California 91731
Tel: 213-686-0141 TWX: 910-587-1565

Finance Drive
Commerce Industrial Park

GEORGIA
HAMILTON/AVNET ELECTRONICS
6700 Interstate 85 Access Road, Suite 1E
Norcross, Ga. 30071
Tel: 404-448-0800
Telex: None - use HAMAVL6CB DAL 73-0511
(Regional Hq. in Dallas, Texas)

KANSAS
HAMILTON/AVNET ELECTRONICS
37 Lenexa Industrial Center

9900 Pflumm Road
Lenexa. Kansas 66215
Tel: 913-888-8900
Telex: None - use HAMAVLECB DAL 73-0511
(Regional Hq. in Dallas, Texas)
LOUISIANA
STERLING ELECTRONICS CORP.
5029 Veterans Memorial Highway
Metairie. Louisiana 70002

Tel: 504-887-7610
Telex: STERLE LEC MRIE 58-328
MARYLAND
HAMILTON/AVNET ELECTRONICS
(mailing address)
Friendship International Airport

P.O. Box 8647
Baltimore, Maryland 21240

SCHWEBER ELECTRONICS
4126 Pleasantdale Rd., Suite 14
Atlanta, Ga. 30340
Tel:. 404-449-9170

(shipping address)
7255 Standard Drive
Hanover. Maryland 21076
Tel: 301-796-5000 TWX: 710-862-1861
Telex: HAMAVLECA HNVE 87-968

G.S. MARSHALL COMPANY
8057 Raytheon Rd" Suite 1
San Diego, California 92111
Tel: 714-278-6350 TWX: 910-335-1191

ILLINOIS
ALLIED ELECTRONICS
1355 Sleepy Hollow Road
Elgin, Illinois 60120
Tel: 312-697-8200
Telex: 72-2465 or 72-2466

SCHWEBER ELECTRONICS
5640 Fisher Lane
Rockville. Maryland 20852
Tel: 301-881-2970 TWX: 710-828-0536

G.S. MARSHALL COMPANY
788 'Palomar Avenue
Sunnyvale, California 94086
Tel: 408-732-1100 TWX: 910-339-9263

KIERULFF ELECTRONICS
9340 Williams Street
Rosemont, Illinois 60018
Tel: 312-678-8560 TWX: 910-227 -3166

LIBERTY ELECTRONICS
124 Maryland Street
EI Segundo, California 90245
Tel: 213-322-8100 TWX: 910-348-7111

HAMILTON/AVNET ELECTRONICS
3901 N. 25th Avenue
Schiller Park, Illinois 60176
Tel: 312-678-6310 TWX: 910-227-0060

LIBERTY ELECTRONICS/SAN DIEGO
8248 Mercury Court
San Diego, California 92111
Tel: 714-565-9171 TWX: 910-335-1590

SCHWEBER ELECTRONICS, INC.
1380 Jarvis Ave.
Elk Grove Village, III. 60007
Tel: 312-593-2740 TWX: 910-222-3453

COLORADO
ELMAR ELECTRONICS
6777 E. 50th Avenue
Commerce City, Colorado 80022
Tel: 303-287-9611 TWX: 910-936-0770

SEMICONDUCTOR SPECIALISTS, INC.
(mailing address)

G.S. MARSHALL COMPANY
17975 Skypark Blvd.
Irvine, California 92707
Tel: 714-556-6400

O'Hare International Airport

P.O. Box 66125
Chicago, Illinois 60666

7-3

PIONEER WASHINGTON ELECTRONICS. INC.
9100 Gaither Road
Gaithersburg, Maryland 20760
Tel: 301-948-0710 TWX: 710-828-9784
MASSACHUSETTS
HAMILTON/AVNET ELECTRONICS
185 Cambridge Street
Burlington. Massachusetts 01803
Tel: 617-273-2120 TWX: 710-332-1201
KIERULFF ELECTRONICS
13 Fortune Drive
Billerica, Massachusetts 01865
Tel: 617-667-8331 (Local)
617-935-5134 (from Boston Area)
TWX: 710-390-1449
SCHWEBER ELECTRONICS
213 Third Avenue
Waltham. Massachusetts 02154
Tel: 617-890-8484

I

FAIRCHILD FRANCHISED DISTRIBUTORS (cont.)
MICHIGAN
HAMILTONI AVNET ELECTRONICS
12870 Farmington Rd.
Livonia, Michigan 48150
Tel: 313-522-4700 TWX: 810-242-8775

NEW MEXICO
CENTURY ELECTRONICS
121 Elizabeth, N.E.
Albuquerque, New Mexico 87123
Tel: 505-292-2700 TWX: 910-989-0625

PIONEER/DETROIT
13485 Stamford

HAMILTON/AVENT ELECTRONICS
2450 Baylor Dr. S.E.

Livonia, Michigan 48150

Albuquerque, New Mexico 87119

Tel: 313-525-1800

Tel: 505-765-1500
TWX' None - use 910-379-6486
(Regional Hq. in Mt. View, Ca.)

SCHWEBER ELECTRONICS
86 Executive Drive

Troy, Michigan 48084
Tel: 313-583-9242
SHERIDAN SALES CO.
24543 Indoplex Drive (P.O. Box 529)
Farmington, Mich. 48024
Tel: 313-477-3800
MINNESOTA
HAMILTON/AVNET ELECTRONICS
7683 Washington Ave. South
Edina, Minnesota 55435
Tel: 612-941-3801
TWX: None - use 910-227 -0060
(Regional Hq. in Chicago, III.)
SCHWEBER ELECTRONICS
7015 Washington Ave. South
Edina, Minnesota 55435
Tel: 612-941-5280

NEW YORK
HAMILTON/AVNET ELECTRONICS
167 Clay Road
Rochester, New York 14623
Tel: 716-442-7820
TWX: None - use 710-332-1201
(Regional Hq. in Burlington, Mass.)
HAMILTON/AVNET ELECTRONICS
6500 Joy ROad
E. Syracuse, New York 13057
Tel: 315-437-2642 TWX: 710-541-0959

Westbury, L.I., New York 11590
Tel: 516-334-7474 TWX: 510-222-3660
SCHWEBER ELECTRONICS, INC.
Rochester, New York 14623
Tel: 716-461-4000

Tel: 314-731-.1144
Telex: HAMAVLECA HAZW 44-2348
SEMICONDUCTOR SPECIALISTS, INC.
3805 N. Oak Trafficway
Kansas City, Mo. 64116
Tel: 816-452-3900 TWX: 910-771-2114

SUMMIT DISTRIBUTORS, INC.
916 Main Street
Buffalo, New York 14202
Tel: 716-884-3450 TWX: 710-522-1692

SEMICONDUCTOR SPECIALISTS, INC.
1020 Anglum Road
Hazelwood, Missouri 63042
Tel: 314-731-2400 TWX: 910-762-0645

NORTH CAROLINA
HALLMARK ELECTRONICS
3000 Industrial Drive
Raleigh, North Carolina 27609
Tel: 919-832-4465 TWX: 510-928-1831

NEW JERSEY
HAMILTON/AVNET ELECTRONICS
113 Gaither Drive

PIONEER/CAROLINA ELECTRONICS
2906 Baltic Avenue
Greensboro, North Carolina 27406
Tel: 919-273-4441

Lakeview Square

East Gate Industrial Park

Mt. Laurel, N.J. 08057
Tel: 609-234-2133 TWX: 710-897-1405
HAMILTON/AVNET ELECTRONICS
218 Little Falls Road
Cedar Grove, New Jersey 07009
Tel: 201-239-0800 TWX: 710-994-5787

OKLAHOMA
HALLMARK ELECTRONICS
4846 South 83rd East Avenue
Tulsa, Oklahoma 74145
Tel: 918-835-8458 TWX: 910-845-2290

Tel: 215-674-5710 (from Pennsylvania phones)
Tel: 609-541-1120 (from New Jersey phones)

SEMICONDUCTOR CONCEPTS
195 Engineers Rd.
Hauppauge, New York 11787
Tel: 516-273-1234 TWX: 510-227-6232

Hazelwood. Missouri 63042

10 Knollcrest Drive

Reading, Ohio 45237
Tel: 513-761-5432 TWX: 810-461-2670

SCHWE8ER ELECTRONICS

2 Town Line Circle

MISSOURI
HAMILTON/AVNET ELECTRONICS
364 Brookes Lane

SHERIDAN SALES CO.
(mailing address)
P.O_ Box 37826
Cincinnati, Ohio 45222
(shipping address)

PENNSYLVANIA
PIONEER/DELWARE VALLEY, INC.
203 Witmer Rd.

Minneapolis, Minnesota 55420

Tel: 612-854-8841 TWX: 910-576-2812

SHERIDAN SALES COMPANY
23224 Commerce Park Road
Beachwood Ohio 44122
Tel: 216-831-0130TWX: 810-427-2957

HAMILTON/AVNET ELECTRONICS
70 State Street
Westbury, L.I .. New York 11590
Tel: 516-333-5800 TWX: 510-222-8237
Jericho Turnpike

SEMICONDUCTOR SPECIALISTS, INC.
8030 Cedar Avenue South

SCHWEBER ELECTRONICS
23880 Commerce Park Road
Beachwood, Ohio 44122
Tel: 216-464-2970 TWX: 810-427-9441

OHIO
ARROW ELECTRONICS, INC.
3100 Plainfield Road
Kettering, Ohio 45429
Tel: 513-253-9176 TWX: 810-459-1611

Horsham, Pennsylvania 19044

HALLMARK ELECTRONICS, INC.
458 Pike Road
Huntington Valley, Pennsylvania 19006
Tel: 215-355-7300 TWX: 510-667-1727
PIONEER ELECTRONICS, INC.
560 Alpha Drive
Pittsburgh, Pennsylvania 15238
Tel: 412-782-2300 TWX: 710-795-3122
SHERIDAN SALES COMPANY
1717 Penn Ave.
Suite 5009
Pittsburgh, Pennsylvania 15221
Tel: 412-244-1640
TEXAS
.
HAMILTON/AVNET ELECTRONICS
4445 Sigma Road
Dallas, Texas 75240
Tel: 214-661-8661
Telex: HAMAVLEC8 DAL 73-0511
HAMILTON/AVNET ELECTRONICS
1216 West Clay
Houston, Texas 77019

Tel: 713-526-4661
Telex: HAMAVLECB HOU 76-2589
NORVELL ELECTRONICS, INC.
10210 Monroe Drive
IP.O. Box 20279)
Dallas, Texas 75220
Tel: 214-350-6771 TWX: 910-861-4512

Rutherford, New Jersey 07070
Tel: 201-935-2120TWX: 710-989-0225

HAMILTON/AVNET ELECTRONICS
761 Beta Drive, Suite "E"
Cleveland, Ohio 44143
Tel: 216-461-1400
TWX: None - use 910-227 -0060
(Regional Hq. in Chicago, III.)

STERLING ELECTRONICS
774 Pfeiffer Blvd.
Perth Amboy, N.J. 08861
Tel: 201-442-8oooTolex: 138-679

HAMILTON/AVNET ELECTRONICS
118 Westpark Road
Dayton, Ohio 45459
Tel: 513-433-0610 TWX: 810-450-2531

SCHWEBER ELECTRONICS, INC.
2628 Longhorn Blvd.
Austin, Texas 78758
Tel: 512-837-2890 TWX: 910-874-1359

SCHWEBER ELECTRONICS
43 Belmont Drive
Somerset, N.J. 08873
Tel: 201-469-6008 TWX: 710-480-4733

PIONEER/CLEVELAND
4800 East 131 st Street
Cleveland, Ohio 44105
Tel: 216-587-3600

SCHWEBER ELECTRONICS, INC.
141 77 Proton Road
Dallas, Texas 75240
Tel: 214-661-5010 TWX: 910-860-5493

RiERULF~-ELECTRONICS

#5 Industrial Drive

7-4

NORVELL ELECTRONICS, INC.
6440 Hillcrolt Avenue
Houston, Texas 77036
Tel: 713-774-2568 TWX: 910-881-2560

FAIRCHILD FRANCHISED DISTRIBUTORS (cont.)
SCHWEBER ELECTRONICS. INC.
7420 Harwln Drive
Houston, Texas 77036
Tel: 713·784·3600 TWX 910·881·1109
STERLING ELECTRONICS
4201 Southwest Freeway
Houston, Texas 77027
Tel: 713·627·9800 TWX 910·881·5042
Telex STELECO HOUA 77·5299
UTAH
HAMILTON/AVNET ELECTRONICS
647 W Billlnis Rd
Salt Lake City. Utah 84119
Tel. 801·262.·8451
TWX None - use 910·379·6486
(Regional HQ. in Mt View, Ca )
WASHINGTON
HAMILTON/AVNET ELECTRONICS
13407 Northrup Way
Bellevue, Washington 98005
Tel. 206·746·8750 TWX 910-443·2449
LIBERTY ELECTRONICS
5305 2nd Ave. South
Seattle. Washington 98108
Tel: 206·763·8200 TWX 910-444·1379

CANADA
CAM GARD SUPPLY LTD
640 42nd Avenue S.E.
Calgary, Alberta, T2G 1Y6, Canada
Tel: 403·287·0520 Telex: 03·822811

CAM GARD SUPPLY LTD
1303 Scarth Street
Regina, Saskatchewan, S4R 27, Canada
Tel: 306·525·1317 Telex: 07·12667

CAM GARD SUPPLY LTO.
10505 111 th Street

CAM GARD SUPPLY LTD
1501 Ontario Avenue
Saskatoon, Saskatchewan, S7K 17, Canada
Tel 306·652·6424 Telex: 07 -42825

Edmonton, Alberta, T5H 3E8, Canada

Tel: 403·426·1805 Telex: 03·72960
CAM GARD SUPPLY LTD.
4910 52nd Street
Red Deer. Alberta, T4N 2C8, Canada
Tel. 403·346·2088

ELECTRO SONIC INDUSTRIAL SALES
(TORONTO) LTD
1100 Gordon Baker Rd
Willowdale, Ontario, M2H 3B3, Canada
Tel: 416-494·1666
Telex. ESSCO TOR 06·22030

CAM GARD SUPPLY LTD.
825 Notre Dame Drive

Kamloops, British Columbia, V2C 5N8, Canada
Tel: 604·372·3338
CAM GARD SUPPLY LTD.
1777 Ellice Avenue
Winnepeg, Manitoba, R3H OW5, Canada
Tel. 204·786·8401 Telex: 07·57622
CAM GARD SUPPLY LTD.
Rookwood Avenue
Fredericton, New Brunswick, E3B 4Y9, Canada
Tel: 506-455·B891

HAMILTON/AVNET INTERNATIONAL
(CANADA) LTD.
6291 Dorman Rd , Unit #16
Mississauga, Ontario, L4V 1 H2, Canada
Tel: 416·677·7432 TWX. 610·492·8867
HAMILTONI AVNET INTERNATIONAL
(CANADA) LTD.
1735 Courtwood Crescent
Ottawa, Ontario, K1Z 5L9, Canada
Tel: 613·226·1700
HAMILTON/AVNET INTERNATIONAL
(CANADA)L TD
2570Paulus Street
SI. Laurent, Quebec. H4S 1G2, Canada
Tel: 514·331·6443 TWX: 610-421·3731

WISCONSIN
HAMILTON/AVNET ELECTRONICS
6055 N. Santa Monica Blvd.
Whitefish Bay. Wisconsin 53717
Tel: 414·964·3482

CAM GARD SUPPLY.L TD.
15 Mount Royal Blvd.
Moncton, New Brunswick, E1C aN6, Canada
Tel: 506·855·2200

MARSH ELECTRONICS, INC.
6047 Beloit Road
Milwaukee, Wisconsin 53219
Tel: 414·545·6500 TWX: 910·262·3321

CAM GARD SUPPLY LTD.
Courtenay Center
Saint John, New Brunswick, E2L 2X6, Canada
Tel: 506·657-4666 Telex: 01 -447489

RAE. INDUSTRIAL ELECTRONICS, LTD.
1629 Main Street
Vancouver, British Columbia, V6A 2W5, Canada
Tel: 604·687·2621 TWX: 610·929·3065
Telex' RAE·VCR 04·54550

SEMICONDUCTOR SPECIALISTS, INC.
10855 W. Potter Road
Wauwatosa, Wisconsin 53226
Tel: 414·257·1330 TWX: 910·262·3022

CAM GARD SUPPLY LTD.
3065 Robie Street
Halifax. Nova Scotia, B3K 4P6, Canada
Tel: 902·454·8581 Telex: 01·921528

SCHWEBER ELECTRONICS
2724 Rena Road
M,ssissauga, Ontario. L4T 3J9, Canada
Tel: 416·678·9050

I

7-5

FAIRCHILD SALES REPRESENTATIVES
CALIFORNIA
CELTEC COMPANY
7380 Clairemont Mesa 8Ivd., Suite 109
San Diego, California 92111
Tel: 714-279-7961 TWX: 910-335-1512

KANSAS
B.C. ELECTRONICS
1015 West Santa Fe
Olathe, Kansas 66061
Tel: 913-782-6696 TWX: 910-749-6414

NEW YORK
LORAC SALES, INC.
275 Broadhollow Road
Melville. New York 11746
Tel: 516-293-2970 TWX: 510-224-6480

CELTEC COMPANY
2041 Business Center Drive, Suite 211
Irvine, California 92664
Tel: 714-752-6111

B.C. ELECTRONICS
1229 South Paige
Wichita, Kansas 67207
Tel: 316-686-3394

OHIO
COMPONENTS, INC.

COLORADO
SIMPSON ASSOCIATES, INC.
2552 Ridge Road
Littleton, Colorado 80120
Tel: 303-794-8381 TWX: 910-935-0719

MASSACHUSETTS
SPECTRUM ASSOCIATES, INC.
888 Worcester Street
Wellesley, Massachusetts 02181
Tel: 617-237-2796 TWX: 710-348-0424

CONNECTICUT
LORAC SALES, INC.
2777 Summer Street
Stamford, Connecticut 06905
Tel: 203-348-7701 TWX: 710-474-1763

MICHIGAN
RATHSBURG ASSOCIATES
16621 E. Warren Ave.
Detroit, Michigan 48224
Tel: 313-882-1717 Telex: 23-5229

FLORIDA
WMM ASSOCIATES, INC.
101 Wymore Road, Suite 300
Altamonte Springs, Florida 32701
Tel: 305-862-4700

MISSISSIPPI
CARTWRIGHT & BEAN, INC.
P.O. Box 3730
5250 Galaxy Drive, Suite J
Jackson, Mississippi 39207
Tel: 601-981-1368

TEXAS
TECHNICAL MARKETING
4445 Alpha Road
Dallas, Texas 75240
Tel: 214-387-3601

MISSOURI
B.C. ELECTRONICS
348 Brookes Drive
Hazelwood, Missouri 63042
Tel: 314-731-1255 TWX: 910-762-0651

UTAH
SIMPSON ASSOCIATES, INC.
2480 So. Main Street, Suite 105
Salt Lake City, Utah 84115
Tel: 801-486-3731 TWX: 910-925-5253

NEW JERSEY
LORAC SALES, INC.
580 Valley Road
Wayne, New Jersey 07470
Tel: 201-696-7070 TWX: 710-988-5846

WASHINGTON
QUADRA
1621 - 114th Avenue S.E.
Suite 212
Bellevue, Washington 98004
Tel: 206-264-4948 TWX: 910-951-1544

WMM ASSOCIATES, INC.
1822 Drew Street
Clearwater, Florida 33519
Tel: 813-447-2533 TWX: 810-866-4108
WMM ASSOCIATES, INC.
1628 e. Atlantic Blvd.
Pompano Beach, Florida 33060
Tel: 305-943-3091
GEORGIA
CARTWRIGHT & BEAN, INC.
P.O. Box 52846
90 W. Wieuca Square, Suite 155
Atlanta, Georgia 30342
Tel: 404-255-5262
INDIANA
LESLIE M. DEVOe COMPANY
7172 North Keystone Ave., Suite C
Indianapolis, Indiana 46240
Tel: 317-257-1227 TWX: 810-341-3284

NORTH CAROLINA
CARTWRIGHT & BEAN, INC.
625 Hafwyn Drive'
Charlotte, North Carolina 28215
Tel: 704-333-6457
CARTWRIGHT & BEAN, INC.
P.O. Box 11209
2415-G Crabtree Blvd.
Raleigh, North Carolina 27604
Tel: 919-832-7128

7-6

7461 N. linden Lane

Cleveland, Ohio
Tel: 216-842-2737
TENNESSEE
CARTWRIGHT & BEAN, INC.
P.O. Box 4760
560 S. Cooper Street
Memphis, Tennessee 38104
Tel: 901-276-4442
CARTWRIGHT & BEAN. INC.
8501 Kingston Pike
Knoxville, Tennessee 37919
Tel: 615-693-7450

CANADA
AVOTRONICS LIMITED
200 Consumers Road, Suite 200
Willowdale, Ontario, M2J 1P8, Canada
Tel: 416-493-9711
AVOTRONICS LIMITED
6600 Trans Canada Highway, Suite 750
Pointe Claire, Quebec, H9R 452, Canada
Tel: 514-697·2135 TWX: 610-422-3908
Telex: 05-821-762

FAIRCHILD SALES OFFICES
'HUNTSVILLE. ALABAMA
3322 So. Memorial Parkway 35801
Suite 92

Tel 205-883-7020 TWX: 810-726-2214
PHOENIX. ARIZONA
4414 N 19th Avenue 85015
Suite G
Tel 602-264-4948 TWX 910-951-1544
'LOS AN GELES, CALI FOR NIA
6922 Hollywood Blvd. 90028
Suite 818
Tel. 213-466-8393 TWX 910-3213009

FORT WAYNE, INDIANA
2118 InlM)od Drrve 46805
SUite 111
Tel 219·483·6453 TWX 810·332·1507
'INDIANAPOLIS, INDIANA
7202 N Shadeland 46250
Tel 317·849·5412 TWX. 810·260·1793
BLADENSBURG, MARYLAND
5801 Annapolrs Road 20710
Suite 500
Tel 301·779·0954 TWX 710·826·9654
'BOSTON, MASSACHUSETTS

SAN DIEGO, CALIFORNIA
8333 Clalremont Mesa Blvd. 92111
Suite 109
Tel 714279-6021
'SANTA ANA, CALIFORNIA
2101 East Fourth S1. 92705
Bldg. B. SUite 185
Tel 714-558-1881 TWX 910-595-1109
'SANTA CLARA, CALIFORNIA
3080 Olcott Street 95050
SUite 210A
Tel 408-244-1400 TWX 910-338-0241
'DENVER, COLORADO
7475 W 5th Ave .. Suite 100
Lakewood. Colo. 80226
Tel 303-234-9292
'STAMFORD, CONNECTICUT
2nd Floor
2777 Summers Street 06905
Tel 203-348-7701 TWX: 710-474-1763
ORLANDO, FLORIDA
Crane's Roost Office Park
303 Whooping Loop
Altamonte Springs, Fla. 32701
Tel 305-834-7000 TWX 810-850-0152
TAMPA, FLORIDA
12945 Seminole 81vd
Florida Twin Towers Bldg 2, Room 6
Largo. Fla. 33540
Tel: 813-585-3892

888 Worcester Street
Wellesley Hills. Mass. 02181
Tel 617237-3400 TWX 710·348·0424
DETROIT, MICHIGAN
Westland Office Plaza
33300 Warren Avenue SUite 101
Westland. Mich. 48185
Tel 313-425·3250 TWX 810·2422973
M1NNEAPOllS, MINNESOTA
7600 Parklawn Avenue
Room 251
Edina. Minn. 55435
Tel: 612-835-3322 TWX:910-576-2944

POUGHKEEPSIE, NEW YORK
15 College View Ave_ 12603
Tet 914-452-4200 TWX 510-248-0030
'ROCHESTER, NEW YORK
600 Kreag Rd
Pittsford. NY 14534
Tel 7163851130
SYRACUSE. NEW YORK
333 E Onondaga Street 13202
ret 315-471-3391 TWX- 710-541-0499
CLEVELAND, OHIO
6151 Wilson Mills Rd_
SUite 101
Highland Heights. OhiO 44143
Tel 216-461-8288 TWX 810-427-9271
DAYTON, OHIO
4812 Frederick Road 45414

Suite 101
Tel: 513-278-8278 TWX 810-459-1803
TULSA, OKLAHOMA
5321 S. Sheridan Road 74145
SUite 15
Tel 918-663-7131

WAYNE, NEW JERSEY
580 Valley Road 07490
Suite 1
Tel 201-696-7070

'PHfLADEPHIA, pEN NSYLVANIA
Fort Washington Industrial Park
500 Office Center
Fort Washington, Pa. 19034
Tel: 215-886·6623 TWX: 510-665-1654

ALBUQUERQUE, NEW MEXICO
2403 San Mateo N.E. 87110
Plaza #2
Tel 505-265-5601 TWX 910-989-1186

'DALLAS, TEXAS
13771 N_ Central Expressway 75231
SUite 809
Tel: 214-234-3391 TWX' 910-867-4757

BINGHAMTON, NEW YORK
3215 E. Main St. Suite 7
Endwell. NY 13760
Tel607-7541094

'H OUSTO N, TEXAS
6430 Hi IIcroft 77036
Suite 102
Tel: 713-771-3547 TWX: 910-881-6278

'MELVILLE, NEW YORK
275 Broadhollow Road 11746
rei: 516-293·2900 TWX 510-224-6480

'CHICAGO, IlliNOIS
9950 W lawrence Avenue
Room 311
Schiller Park. III 60176
Tet 312·671·4660 TWX: 910-227·0051

MILWAUKEE, WISCONSIN
4642 76th Street
Suite 101
Greenfield. Wisconsin 53220
rei 414·282·5260
*FieJd Applications Engineer available.

*Fleld Applications Engineer available.

7-7

INTERNATIONAL FIELD SALES OFFICES
AUSTRALIA
Fairchild Australia Pty. Ltd.
420 Mount Oandenong Road
Croydon. Victoria. 3136
Australia
Tel: 723-4131 TWX: 30846
AUSTRIA
Fairchild Electronics
Schwedenplatz 2
1010 Vienna
Tel: 0043 222635821
Telex: 0047 75096
BRAZIL
Fairchild Electronica Ltd
Caixa Postal 30407
Rua de Consola Cao. 3542
Sao Paulo, S.P. Brazil
Tel: 81·6168 Telex' 021·261
Cable: FAIRLEC

Fairchild Halbleiter GmbH

Fairchild Semiconduttori S.pA

8 Munchen 80
Truderinger Str. 13
Tel: 089 4701091·3 Telex: 05 24831

Via Rosselini, 12
20124 Milano. Italy
Tel: 00392 6887451·5

Fairchild Halbleiter GmbH
8500 Nurnberg
Waldluststr. 1
Tel: 0911 407005 Telex 06·23665

JAPAN
TDKFairchild
Sanyo Kokusaku Pulp Bldg. 2nd FI.
7·8 Shibuya 1 ·Chome

Fairchild Halbleiter GmbH
725 Leonberg -Eltingen

Tokyo 150. Japan
Tel: 03·400·8351 Telex' 2424173

Poststr. 37
Tel: 07152·41026 Telex: 07·22644

MEXICO

Shibuya-ku

Fairchild Mexicana S.A.

HONG KONG
Fairchild Semiconductor (HK) Ltd

135 HOI 8un Road
Kwun Tong
Kowloon, Hong Kong
Tel: K·890271 Telex: HKG·531

Blvd. Adolfo Lopez Mateos No. 163
Mexico 19. D.F
Tel: 905·563·5411 Telex: 017· 71·038
SCOTLAND

Toronto Regional Office

ITALY

FSC
1590 Matheson Blvd. Unit 26
Mississauga, Ontario L4W lJl, Canada
Tel: 416·625·7070 TWX: 610-492·4311

Fairchild Semiconduttori, S.p.A
Viale Cortina d'Ampezzo, 152

Fairchild Semiconductor Ltd
Shiel House
Crai9shil!
Livingston
West Lothian, Scotland

00135 Rome. Italy
Tel 00396 3274006

Tel: 00445 8932891
Telex 0051 72629

CANADA

SWEDEN

Fairchild Semiconductor
1385 Mazurette Suite 3

Fairchild Semiconductor AB
Svartensgatan 6,

Montreal. Quebec. H4N lG8. Canada
Tel 514·382·2552 TWX: 610·421·3178

S ·11620 Stockh olm
Tel 00468-449255 Telex: 0054·17759

FRANCE

TAIWAN

Fairchild Semiconducteurs, S.A.
121 Avenue d'italien

Fairchild Semiconductor (Taiwan) Ltd.
Hsietsu Building, Room 502

750310. Paris. France
Tel 00331 5805566
Telex: 0042 20614

47 Chung Shan North Road
Sec. 3, Taipei, Taiwan

Tel: 573205 thru 573207
GERMANY

THE NETHERLANDS

Fairchild Halbleiter GmbH
European Headquarters

Fairchild Semiconductor
Paradijslaan 39
Emdhoven, Holland

6202 Wiesbaden·Biebrich
Postfach 4559

Tel: 003140-446909 Telex: 0044·51024

Hagenauer Strasse 38

Tel: 061212051 Telex: 841·4186588

UNITED KINGDOM
Fairchild Semiconductor· Ltd.
Kingmaker House
Station Road
New Barnet/Hertfordshire

Tel 00441 4407311 Telex: 0051 262835

7-8



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