1975_National_Interface_Integrated_Circuits 1975 National Interface Integrated Circuits
User Manual: 1975_National_Interface_Integrated_Circuits
Open the PDF directly: View PDF 
.
Page Count: 460
| Download | |
| Open PDF In Browser | View PDF |
Edge Index
by Product Family
~
NAnONAL
Here is the new INTERFACE catalog from National Semiconductor Corporation. It contains complete information on all of National's INTERFACE products and we hope it becomes your most important INTERFACE
guide. For your convenience, two different Tables of Contents are provided. One lists the products by
type-Line Driver, Sense Amplifier, etc.-and the other lists the products alphanumerically by part number.
Product selection guides and a complete product applications section are also included. For information on
products that become available after this catalog goes to print, contact your local National office. The addresses are listed on the back cover.
Peripheral/Power Drivers
level Translators/Buffers
line Drivers/Receivers
g
D
Memory/Clock Drivers
(I
Sense Amplifiers
iii
Display Drivers
[tI
Opto-Couplers
fI
A"pplications
[#)
Physical Dimensions/Def. of Terms
Manufactured un~er one 'or more of tile following U.S. patents: 3083262, 3189758, 3231797, 3303356, 3317671. 3323071, 3381071, 3408542,3421025,3426423,3440498,3518750,3519897, 3557431, 3560755,
3566218,3571630,3575609,3579059,3593069,3597640,3607469,3617859,3631312,3633052,3638131,3648071,3651565,3693248.
National does not assume any re5Ponsj~illty lor use 01 any circuitry described; no circuit patent licenses are implied: and National reserves the right, at any tim~ with(wt notice, to change said cirCUitry,
© 1975 National Semiconductor Corp.
o
m
~
Ordering Information
NAll0NAL
Ordering information for National devices covered in this catalog is as follows:
OS
--
3611
-r-
L -_ _ _ _ _ _ _ _ _
OEVICE NUMBER
' - - - - - - - - - - - - - OEVICE FAMILY
OEVICE FAMILY
OM - Digital Monolithic
OS - Digital Special
NCT - Opto Couplers
DEVICE NUMBER
3, 4 or 5 digit number
Suffix Indicators:
A - Improved Electrical Specification
PACKAGE
o ~ Glass/Metal Dual-In-Line Package
F - Flat Package (0.25" wide)
G - TO-8 (12 lead) Metal Can
H - TO·5 (multi-lead) Metal Can
J - Glass/Glass Du.al-In-Line Package
N - Molded Dual-In-Line Package
W - Flat Package (0.275" wide)
National's interface products use a 16/36 prefix. The 16 is used to denote the military temperature range
(-55°C to +125°C) and the 36 denotes the commercial temperature range (O°C to +70°C), i.e. OS1630/
OS3630. Display drivers and line drivers and receivers employ a 76/86 or a 78/88 prefix. The 76 or 78 applies
to the military part, and the 86 or 88 to the commercial part, i.e. OS7830/0S8830. Some interface circuits
and sense amplifiers employ a 55 as the first two digits for the military temperature range part, and a 75 for
the commercial part, i.e. DS5520/DS7520. Digital products employ a 54 as the first two digits for the
military temperature range part, and a 74 for the commercial part, i.e. DM5446/DM7446.
ii
~
Table of Contents
NAnONAL
Edge Index by Product Family . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
Alpha-Numerical Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x
PRODUCT GUIDES
Thermal Ratings for Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interface Cross Reference Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmission Line Driver and Receiver Product Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . _ ... .
Peripheral Driver Guide . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LED Driver 5election Guide ...............•.........•........•..•...' •........•......••....
Opto-Coupler Cross Reference Guide . • . . . . . . . . • . • . . . . . . . • . . . . . . . • . . . • . . • . . . . . . . . . . . . . . . . . . . . .
xvi
xvii
xviii
xix
xx
xxi
PERIPHERAL/POWER DRIVERS - SECTION 1
051611 Dual Peripheral Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
051612 Dual Peripheral Driver
051613 Dual Peripheral Driver
051614 Dual Peripheral Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
051631 CM05 Dual Peripheral Driver . . . . . . . . . . . . . • . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . .
051632 CM05 Dual Peripheral Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
051633 CM05 Dual Peripheral Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
051634 CM05 Dual Peripheral Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
051686 Positive Voltage Relay Driver . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
051687 Negative Voltage Relay Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
053611 Dual Peipheral Driver . '.' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
053612 Dual Peripheral Driver
053613 Dual Peripheral Driver ...........•... , .......•........ , . . . . . . . . . . . . . . . . . . . . . . . . . . .
053614 Dual Peripheral Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
053631 CM05 Dual Peripheral Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . .
053632 CMOS Dual Peripheral Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . . . .
053633 CM05 Dual Peripheral Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . .
053634 CM05 Dual Peripheral Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
053686 Positive Voltage Relay Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . .
053687 Negative Voltage Relay Driver . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0555450 Dual Peripheral Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS55451 Dual Peripheral Driver
0555452 Dual Peripheral Driver
0555453 Dual Peripheral Driver
0555454 Dual Peripheral Driver
0555460 Dual Peripheral Driver
0555461 Dual Peripheral Driver
0555462 Dual Peripheral Driver
0555463 Dual Peripheral Driver
0555464 Dual Peripheral Driver
0575450 Dual Peripheral Driver
0575451 DuaL Peripheral Driver
0575452 Dual Peripheral Driver
0575453 Dual Peripheral Driver
0575454 Dual Peripheral Driver
0575460 Dual Peripheral Driver
0575461 Dual Peripheral Driver
DS75462 Dual Peripheral Driver
0575463 Dual Peripheral Driver
DS75464 Dual Peripheral Driver
1-1
1-1
1-1
1-1
1-7
1-7
1-7
1-7
1-13
,.,5
,.,
1-1
1-1
1-1
'-7
1-7
1-7
1-7
1-13
,.,5
1-17
,.,7
1-17
1-17
1-17
1-28
1-28
1-28
1-28
1-28
1-17
1-17
1-17
1-17
1-17
1-28
'-28
1-28
1-28
1-28
iii
LEVEL TRANSLATORS/BUFFERS - SECTION 2
DS1630 Hex CMOS Compatible Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . • . . . .
D53630 Hex CMOS Compatible Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS7800 Dual Voltage Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS7802 High Speed MOS to TTL Level Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . ' .....................
DS7806 High Speed MOS to TTL Level Converter . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . .
DS7810 Quad 2-lnput TTL·MOS Interface Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS7811 Quad 2-lnput TTL-MOS Interface Gate, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS7812 TTL-MOS Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS78L12 TTL-MOS Hex Inverter/Interface Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS7819 Quad 2-lnput TTL-MOS AND Gate . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . ,' . . . . . . . . . . . . . . . _ ..
DS8800 Dual Voltage Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,' . . . . . . . . . . . . . . . . , .........
DS8802 High Speed MOS to TTL Level Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8806 High Speed MOS to TTL Level Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8810 Quad 2-lnput TTL-MOS Interface Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ; ... _ .....
DS8811 Quad 2-lnput TTL-MOS Interface Gate ...................................................
DS8812 TTL-MOS Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . .' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS88L 12 TTL-MOS Hex Inverter/lnterface Gate . . . . . . . . • . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . o' . '• • • •
DS8819 Quad 2-lnput TTL-MOS AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . o' • • • • • • •
2-1
2-1
24
5·32
5·32
2-7
2-7
2-7
2-10
2-12
2-4
5-32
5-32
2-7
2-7
2-7
2-10
2-12
LINE DRIVERS/RECEIVERS - SECTION 3
DS1488 Quad Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ; ....." . . . . . . . . . . . . . . . . • . . . . . . 3-1
D51489 Quad Line Receiver . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , ............ 3-4
DS1489A Quad Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
D51603 Dual Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ' . . . . . . . . . . . . . . . . . . . . . . . . 3-56
DS1688 Quad TRI-STATE® Differential Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
DS1689 Quad Differential Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ; .... ' ................. . 3-8
DS1690 Quad Differential Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • .' ......... " .. . 3-8
DS3603 Dual Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . :r56
DS3604' Dual Line Receiver
3-56
DS3650 Quad Line Receiver
3-10
D53652 Quad Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . _ ......................................3-10
053660 Optically Isolated Line Receiver ....................................................... '. 7·1
DS3661 Optically Isolated Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . •' ....... 7·1
DS3688 Quad TRI-STATE® Differential Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
DS3689 Quad Differential Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .' ......•. 3-8
DS3690 Quad Differential Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
DS7640 Quad NOR Unified Bus Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
DS7641 Quad Unified Bus Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . o' • • • • • • • • • • • • ': • • • • • • . . . 3-17
.DS7820 Dual Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .; .... ;....... 3-22
DS7820A Dual Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
DS78LS20 Dual Differential Line Receiver .....................................................'. 3-29
DS7822 Dual Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31
DS7830 Dual Differential Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '.' , .............. .' ... 3-34
DS7831 TRI-STATE® Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37
DS7832 TRI-STATE® Line Driver ............................................. : . . . . . . . . . . . . . . 3-37
OS7833 Quad TRI-STATE® Party Line Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
DS7834 Quad TRI-STATE® Party Line Transceiver .................................................. 3-46
DS7835 Quad TRI-STATE® Party Line Transceiver ................................................. 342
DS7836 Quad NOR Unified Bus Receiver ........................................................ 3-50
DS7837 Hex Unified Bus Receiver . . . . . . . . . . . . . " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52
DS7838 Quad Unified Bus Transceiver ........................................' ................... 3-54
DS7839 Quad TR I-STA TE® Pa'rty Line Transceiver ................................' .......: ........ 3-46
DS8640 Quad NOR Unified Bus Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : ............. 3-15
DS8641 Quad Unified 8us Transceiver ...................................................... o' • • 3-17
DS8642 Quad Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1.9
DS8820 Dual Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-22
DS8820A Dual Line Receiver ..................................... '..........•. ; .............. 3-25
DS88LS20 Dual Differential Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . o' • • ; • • • • • • ' • • • • • • o' 3-29
DS8822 Dual Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,' .... ; ........... 3·31
DS8830 Dual Differential Line Driver ............... , . . . . . . . . . . . . . . . . . . . . . . . . . .' . . . . . . . . . . . . . . . 3-34
DS8831 TRI·STATE® Line Driver .... _ .. '" . . . . . . . . . . . . . . . . . . . . . , ........ _ . . . . . . . . . . . . . . . . . . '3-37
iv
LINE DRIVERS/RECEIVERS - SECTION 3 (CONTINUED)
DS8832 TRI-STATE® Line Driver __________________________________________________________ 3-:31
DS8833 Quad TR I-ST ATE® Party Line Transceiver
______ . ___________________________ '____
DS8834 Quad TRI-STATE® Party Line Transceiver
DS8835 Quad TRI-STATE® Party Line Transceiver
DS8836 Quad NOR Unified Bus Receiver
DS8837 Hex Unified Bus Receiver
DS8838 Quad Unified Bus Transceiver
D58839 Quad TRI-STATE® Party Line Transceiver
DS55107 Dual Line Receiver
DS55108 Dual Line Receiver
DS55109 Dual Line Driver
DS55110 Dual Line Driver
DS55121 Dual Line Driver
DS55122 Triple Line Receiver
o·
DS75107 Dual Line Receiver
DS75108 Dual Line Receiver
DS75109 Dual Line Driver
DS75110 Dual Line Driver
DS75121 Dual Line Drive~
DS75~ 22 Triple Line Receiver
DS75123 Dual Line Driver
DS75124 Triple Line Receiver
DS75150 Dual Line Driver
DS75154 Quad Line Receiver
DS75207 Dual Line Receiver
DS75208 Dual Line Receiver
0
0
0
0
0
0
0
0
0
0
0000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
000
0,000000000:
0
0
0
0
_
0
0
000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0'0
0
0
0
0
,
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
_
0
0
0
0
0
0
0
0
0
0
0
_
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
o.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
0
0
00
0
0
0
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0'0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0.0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
_
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
_
0
0
0
0'0
0
0
0
0
0
_
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
0:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
_
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
~
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
_
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
'0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0000000
0
0
0
0
0
0
0
0
0
0
0
0
000000000,000'000000
00000000000000000000000000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
0
00
0
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
_
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
o.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3-42
3-46
3-42
3-50
3-52
3-54
3-46
3-56
3-56
3-63
3-63
3-66
3-68
3-56
3-56
3-63
3-63
3-66
3-68
3-71
3-73
3-76
3-79
3-56
3-56
MEMORY/CLOCK DRIVERS -SECTION 4
DS0025 2 Phase MOS Clock Driver
DS0025C 2 Phase MOS Clock Driver
D50026 5 MHz 2 Phase MOS Clock Driver
D50056 5 MHz 2 Phase MOS Clock Driver
DS1640 Quad MOS TRI-SHARETM Driver
DS1642 Dual Bootstrapped MOS Clock Driver
DS1645 Hex TRI-STATE® MOS Latch/Driver
DS1646 6-Bit TRI-STATE® MOS Refresh Counter/Driver
DS1,647 Quad TRI-STATE® Memory I/O Register
DS1648 TRI-STATE® MOS Mult.iplexer/Driver
DS1649 Hex TRI-STATE® MOS Driver
DS1670 Quad MOS TRI-SHARETM Driver
DS1671 Bootstrapped 2 Phase MOS Clock Driver
DS16n Dual Bootstrapped MOS Clock Driver
DS1675 Hex TRI-STATE® MOS Latch/Driver
DS1676 6-Bit TRI-STATE® MOS Refresh Counter/Driver
DS1677 Quad TRI-STATE® MOS Memory I/O Register _
DS1678 TRI-STATE® MOSMultiplexer/Driver
DS1679 Hex TRI-STATE® MOS Driver
DS3629 Memory Driver with Decode Inputs
DS3640 Quad MOSTRI-SHARE™ Driver
o. o. o.
DS3642 Dual Bootstrapped MOS Clock Driver
D53643 Decoded Quad MOS Clock Driver
DS3644 Quad MOS Clock Driver
o.
o.
D53645 Hex TRI-STATE® MOS Latch/Driver
DS3646 6-Bit TRI-STATE® MOS Refresh Counter/Driver • _
DS3647 Quad TRI-STATE® MOS Memory I/O Register ...... _
DS3648' TR I-STATE® MOS Multiplexer/Driver
D53649 Hex TRI-STATE® MOS Driver
DS3670 Quad MOSTRI-SHARE™ Driver. o.
DS3671 Bootstrapped 2 Phase MOS Clock Driver .
0
0
0
0
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
'0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
'0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
000000000000000000000000000000000000000000000000000
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0'
0
0
0
0
0
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
,
0
0
0
0
0
0
0
0
0
0
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
0
0
0
0
0
00000000000000000000000000
o.
,
0
000000000000
000
_
0
0
0
0
0
_
0
0
0
0
0
0
0
0
0
_
0
_
0
0
_Co
00
0
0
0
0
0
0
0
0
0
0
0
00
0
0
0
0
0
0
0
0
0
0
0
0
0
00
0
0
0
_
0
0
0
0
0
0
0
0
0
0_
0
0
0
0
0
0
0
_
0
000
_
0
0
0
000000000000000000
0000000000000000000000000000000
0
0
0
0
0
0
0
0
0000
0
00
0
_
0
0
_
0
0
0
_
0
0
0
_
0
0
0
0
0
0
0
0
0
0
0
0
0
_
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
_
0
_
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
_
0
0
0
0
0
0
0
_
0
0
0
0
00000000000000000000000000000000
_
0
0
0
0
0
0'
0
0
0
0
0
0
.0
0
0
0
0
0
_
0
0
0
0
0
0
0
0
_
0
0
0
_
00
0
0
0
0
0
0
0
0
0
0
0
_
0
_
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
_
0
0
0
0
0
0
0
0
0
0
0
0
00000000'
00000000000
_
0
0
0
0
O.
0
0
0
0"
0
0
0
0
0
0
_
0
0
0
0
0
0
0:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
_
0
0
0
0
0
0
_
0
0
0
__
0
0
0
0
••••
000
0
0
0
0
0
0
0
0
0
0
0
0
0"
0
00
0
0
00
0
0
0
0
0
0
0
0
0
0
0
_
0
0
0
0
_
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
_
0
0
0
0
0
0
0
0
_
0
0
0
0
0
0
•
0
0
•
0
••
0
0
0
0
0
0
0
0
•
0
0
0"
0
0
•
0
0
0
•
_
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00000000.00'000.00.000000
_.
0
0
0
0
••••
0
••••
0
0
••
0
0
0
0
••••••••
0
00
0
000000000000000
0
0
••••
0
0000000
0
0
0
0
0
0
0
0"
0
0
0
0
0
00
0
0
0
••
0
0
__
0
0
0
0
0
0
0
•
0
••
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
•
0
0
0
•
0
0
•
0
0
•
0
0
0
0
0
0
0
0
0
0
0
0
•
0
•••
0
0
0
•
0
0
0
•
0
0
0
0
0
0
0
0
0'
0
."
•
••
0
0
0
•
0
•
0
0
0
0
••
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
••••
0
0
0
•
0
0
0
0
0
0
0
0
0
0
0
00
0
0
..
0
0
0
0
0
0
0
0
0
00
0
0
0
•••••
0
0
0
0
_
0
0
0
0
•
0
••••••••••••
0
•••••••••••••••
_
••
0
••••••••••••••••••••••••
0
••••
•••••
0
0.0
0
•
••••
0
0
0
•••••
•••••
••••••••
0
•••
••••••••••••••
00.
0
•
0
o.
0
0
o
o.
•••
0
0
_
•••••••••••
••••••••
0
••••••
••••••••••••••••
0
0.0.
••••••
0"
__
••••••••
0
•• '
••••
••
0
_
••••••••
...........
0'0
4-1
4-1
4-4
4-4
4-17
4-20
4-29
4-33
4-36
4-41
4-46
4-17
4-49
4-20
4-29
4-33
4-36
4-41
4-46
4-11
4-17
4-20
4-23
.4-26
4-29
4-33
4-36
4-41
4-46
4-"
.
(
~,
MEMORY/CLOCK DRIVERS -SECTION 4 (CONTINUED)
DS3672 Dual Bootstrapped MOS Clock Driver ..•............................•.......•.......•...
DS3673 Decoded Quad MOS Clock Driver . . . . . . . . . . . . . . . . . . . . . . . ; ..•••.....•..................
DS3674 Quad MOS Clock Driver . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . • • . . . . . . . , ..
DS3675 Hex TRI·STATE® MOS Latch/Driver ...... ; ......••....•.......... , .......••....•.•...
DS3676 6·Bit TRI-STATE® MOS Refresh Counter/Driver . . . . . . . . . . . . • . . . . . . • . . . . • . . . . . . . . . . . . . . . . .
DS3677 Quad TRI-STATE® MOS Memory I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . .
DS3678 TRI-STATE® MOS Multiplexer/Driver . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . • • . . . . . . . . . . . . . . . .
DS3679 Hex TRI-STATE® MOS Driver . . . . . . . . . . . . . . . . . . • . . . . . . . • . . . . . . . • . . . . . . . . . . . . . . . . . . .
DS7803 2 Phase Oscillator/Clock Driver . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . • . . . . . . . . • . . . . .
DS7807 2 Phase Oscillator/Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . • . • . . .
DS8803 2 Phase Oscillator/Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . • . . . . • . . . . . . • . . . . . . . . . , ..•....
DS8807 2 Phase Oscillator/Clock Driver
DS8813 2 Phase Oscillator/Clock Driver . . . . . . • . . . . . . . . . . . . . . . • . . . • . . . . . . . . . . . . . . . . . . . . . . • • . . .
DS8817 2 Phase Oscillator/Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . • . . . . . . . . • . . . . . .
DS16147 Quad TRI-STATE® MOS Memory I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . • . . . •
DS16149 Hex MaS Driver . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . • . . . . • . . . . . , ......•...•....
DS16177 Quad TRI-STATE® MOS Memory I/O Register . . . . . . . . . • . . . . . • . . . . . • . . . . . . . . . . . • . . . . • . . . .
DS16179 Hex MaS Driver . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . • . . . . . . . . . . . • . . . . . . . _ ...
DS36147 Quad TRI-STATE® MaS Memory I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . .
DS36149 Hex MOS Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . • . . . . . • . . . . . . . . . . . . • . . • • . . .
DS36177 Quad TRI-STATE® MOS Memory I/O Register . . . . . . . . . . • . . . . . . . . . . . . • . . . . . • • . . . . . . . . • . . •
DS36179 Hex MOS Driver . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS55325 Memory Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS75324 Memory Driver with Decode Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . .
DS75325 Memory Driver . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . • • . . • . . . . . . . . . . . . . . . . . . . • . • . . . .
DS75361 Dual TTL to MOS Driver .............................••........•.........•.•••...•
DS75362 Dual TTL to MOS Driver . • . . . . . . . . . . . . . . . . . . . . . . • . • . . . • . . . . . . . . • . . . . . . . . . . . . . . . . .
DS75364 Dual MOS Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . • . . .
DS75365 Quad TTL to MaS Driver ..............•.........••....•.........•.................
4·20
4-23
4·26
4-29
4·33
4-36
4-41
4-46
4-56
4-60
4-56
4-60
4-56
4-60
4-36
4-53
4-36
4-53
4·36
4-53
4-36
4-53
4-70
4-64
4-70
4-77
4-82
4-87
4-91
SENSE AMPLIFIERS - SECTION 5
DS1603 Dual MaS Sense Amplifier . . . . . . . . . . . . . . . . . . . . ., .....•.....•......•....•.......••..•
DS160~ High Speed Hex MaS Sense Amplifier ...........•...•...........•....••...•..••••...••.
DS1606 High Speed Hex MOS Sense Amplifier . . . . . . . . . . . . . . . . • . . . • . . . . . • . . . . . . . • . . . . . . . . . . • . . . .
DS1607 High Speed Hex MOS Sense Amplifier • . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . • • . . . .
DS1608 High Speed Hex MOS Sense Amplifier •.........•......•.......•..•..............•.•••..
DS3603 Dual MOS Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . • • • . . . . . . . . . . . . . . . . . . . . . • . . . . . • . .
DS3604 Dual MOS Sense Amplifier ....................•.....•...........•....•........ _ .....
DS3605 High Speed Hex MOS Sense Amplifier . . . . . . . . . . . . . . , •.••.•..•..... _ . . . . . . . . . • . . . . . . . . . .
DS3606 High Speed Hex MOS Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . • . . . • . • . . • . . . . . . . . . . . . . ..
DS3607 High Speed Hex MOS Sense Amplifier ......•......•..••....•...•...•••......•.•.•.•.•..
DS3608 High Speed Hex MOS Sense Amplifier . . . . . . . . . . . . . . . . . . • . . . . . . • • . . . . . . . . . . • . • . . . . . . . . • •
DS3625 Dual High Speed MOS Sense Amplifier . . • . . . . . . . . • . . . . . • . • . . . . . . . . . . . . . . . . . . . . . . . • . . . . .
DS3651 Quad High Speed MOS Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . • • . . . . . . . • .
DS3653 Quad High Speed MOS Sense Amplifier . • . . . . . . . . . . . . . . . . . . . . . • • . . . • . . . . . . . . . . . . . . . . . . ..
DS5520 Dual Core Memory Sense Amplifier ....•...•.............•.•..•.••..••................•
DS5520A Dual Core Memory Sense Amplifier .............•..•.••..•..••.•...•.........•.•...••
DS5521 Dual Core Memory Sense Amplifier .. _ . . . . . . . . . . . • . . . . . . . . • . . . . . • . . • . . . . . • . . . . . . . . . . . •
DS5522 Dual Core Memory Sense Amplifier ...............•.•....•..•...••..•...•.••..•.•••....
DS5522A Dual Core Memory Sense Amplifier . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . • . • . • . . . . . . . • . . . .
DS5523· Dual Core Memory Sense Amplifier ...................•.........•.•..........••.••.•.•
DS5524 Dual Core Memory Sense Amplifier ...........•.....•.•.....•.•••.•.•.•.............•.
DS5524A Dual Core Memory Sense Amplifier ..•..............••. '••..•.....•.•...•........ , ..•.
DS5525 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . • . . . . . . . . . . . . . • . .
DS5528 Dual Core Memory Sense Amplifier .................•••.....•.......•.•...........••...
DS5528A Dual Core Memory Sense Amplifier ..................•..•.•.•...••....................
DS5529 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . • • . . . . . . . . . . . . . . .
DS5534 Dual Core Memory Sense Amplifier ........•....•.....•••.....•............•.......•..
DS5534A Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . • . . . • . • . • . • . • . .
3-56
5-1
5-1
5-1
5-1
3-56
3-56
5-1
5-1
5-1
5-1
5-6
5-8
5-8
5-13
5-13
5-13
5-13
5-13
5-13
5-13
5-13
5-13
5-13
5-13
5-13
5-13
5-13
SENSE AMPLIFIERS - SECTION 5 (CONTINUED)
DS5535 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS5538 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS5538A Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS5539 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS7520 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS7520A Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS7521 Dual Core Memory Sense Amplifier ..... _ . . . . . . . . . . . . . . . . . _........ _ . . . . . . . . . . . . . . . _ ..
DS7522 Dual Core Memory Sense Amplifier ... _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS7522A Dual Core Memory Sense Amplifier ......... _ ..... _ .. _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS7523 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ .
DS7524 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS7524A Dual Core Memory Sense Amplifier . _ . . . . . . . . . . . _ ..... _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS7525 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ ..... _ ....... .
DS7528 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS7528A Dual Core Memory Sense Amplifier . . . . . . . . . . . . __ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS7529 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS7534 Dual Core Memory Sense Amplifer ...... _ . . . . . . . . . . . . . . . . . '. . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS7534A Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS7535 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS7538 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ ..... .
DS7538A Dual Core Memory Sense Amplifier . . . . . . . . . . . . _ .... _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS7539 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . _ .. _ . . . . . . . . . . . . . . . . . . . . . , ..
DS7802 Dual High Speed MOS Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS7806 Dual High Speed MOS Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8802 Dual High Speed MOS Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8806 Dual High Speed MOS Sense Amplifier .... _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS55107 Dual MOS Sense Amplifier ............ _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS55108 Dual MOS Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS75107 Dual MOS Sense Amplifier
DS75108 Dual MOS Sense Amplifier
DS75207 Dual MOS Sense Amplifier
DS75208 Dual MOS Sense Amplifier
5-13
5-13
5-13
5-13
5-13
5-13
5-13
5-13
5-13
5-13
5-13
5-13
5-13
5-13
5-13
5-13
5-13
5-13
5-13
5-13
5-13
5-13
5-32
5-32
5-32
5-32
3-56
3-56
3-56
3-56
3-56
3-56
DISPLAY DRIVERS -SECTION 6
DM5441A 8CD to Decimal Decoder/Nixie™ Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
DM5446A 8CD to 7-Segment Decoder/Driver .. _ .....1 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • _ • • • • • • • 6-3
DM5447A 8CD to 7-Segment Decoder/Driver ... _ ....... _ ....... _ ...... _ .. _ ...... _ . . . . . . . . . . . . . 6-3
DM5448 8CD to 7-Segment Decoder/Driver ... _ .... _ .. _ ............. _....... _ . . . . . . . . . . . . . . . . . 6-3
DM7441A 8CD to Decimal Decoder/Nixie ™ Driver .. _ . _ ............ _ .. _ ... _ . . . . . . . . . . . . . . . . . . . . . 6-1
DM7446A 8CD to 7-Segment Decoder/Driver . . . . . . . . . . . . . . . . . . . . . _ ... _ . . . . . . . . . . . . . . . . . . . . . . . . 6-3
DM7447A BCD to 7-Segment Decoder/Driver _. _ .... __ ... _ .. _ .. _ .. ___ . _ ....... _ . _ . . . . . . . . . . . . . . 6-3
DM7448 BCD to 7-Segment Decoder/Driver .......... _ .... _ .... _ . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . _ 6-3
DM54141 BCD to ,Decimal Decoder/Driver .... _ .. _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
DM74141 BCD to Decimal Decoder/Driver . . . . . . . . . . . . . . . . __ ... _ . _ .. _ ........ __ ...... _ .. _ .... . 6-8
DS7856 BCD to 7 ·Segment LED Driver . . . . . . . . . . . . . . . . . _ . _ ..... _ ..... _ ......... _ . . . . . . . . . . . . 6-37
DS7858 BCD t07-Segment LED Driver . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . . . . . . . . . _ .... _ .... . 6-37
DS7880 High Voltage7-Segment Decoder/Driver . . . . . . . . . . . . _ . _ .... _ ...... _ ........... _ ... _ .. _ .. 6-59
DS7885 MOS to High Voltage Cathode Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ ..... . 6-64
DS7887 8-Digit High Voltage Anode Driver . . . . . . . . . . . . . . __ .... _ ....... _ ...... _ .. _ . _ . _ .. _ . _ . __ . 6-66
DS7889 8-Digit High Voltage Cathode Driver . . . . . . . . . . . . . . . _ ...... _ . . . . . . . . . . . . . . . . . . . . _ ...... . 6-66
DS7891 High Voltage Anode Driver (Active Low Inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . 6-70
DS7895 Ouad LED Segment Driver ............. _ ... __ .. _ ............... _ . . . . . . . . . . . . . . . . . . . 6-74
DS7897 8-Digit High Voltage Anode Driver ......... _ ......... _ .. _ ......... _ ....... _ . _ .. __ .... . 6-66
DS8650 Low Voltage 4-Digit LED Driver ....... _ ......... _ .... _ ......... _ . . . . . . . . . . . . . . . . . . . . 6-10
DS8651 Low Voltage 7-Segment LED Driver ., _ ......... _ ......... _ ....... ______ . _ . _ . __ . _ ..... . 6-12
DS8654 8-0utput Buffer . . . . . . . . . . • . . . . . . . . . " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ ... . 6-14
DS8655 12-0utput Decoder/Driver and Oscillator .......... " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
DS8656 Diode Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ .. _ . 6-14
QS8658 Low Voltage 4-Digit LED Driver .... _ ...... _ .. _ . _ .. _ .... _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20
DS8659 Low Voltage 7-Segment LED Driver . . . . . . . . . . . . . . . . . . . . . . ; . . . . . . . . . . . . . . . . . . . . _ ..... _ . 6-12
D58673 7-Segment Decoder/Driver/Latch .... _ ....... _ ... _ .. _ ... ___ .. _ . _____ . . . . . . . . . . . . . . . . . . 6-22
vii
DISPl-AY DRIVERS - SECTION 6 (CONTINUED)
DS8674 7-Segment Decoder/Driver/Latch ..........••... , ...... , .........•• , ... , ..•. ; ...•..• ,. 8-22
DS8692 Printing Calculator Interface Set ..........•....., ...................................... 6·28
DS8693 Printing calculator Interface Set .....•... , •... : .........•.....•.......•....•... ; .. : .. 6-28
DS8694 Printing Calculator Interface Set ; ............•.' .••....... , ....••..•..... : .••..• ~ .•. " 6-28
DS8844 LED Cathode Driver •.•.................. , .• , .................•.•...' ....••....••.•..8-35
DS8855 LED Cathode Drive,r ......•.............•....•.........•..•.. ; •... '..............•.6·35
DS81;!56 BCD to 7-Segment LED Driver ..•......•...................•.•.... ; .. ; .... , ... ', ..... 6·37
DS8857 BCD to 7-Segment LED Driver .............' ...••..•.......•.......•...•.... : .•. ~ ... ,. 6-37
DS8858 BCD to 7 ·Segment LED Driver ..........••...............•....•.•..........•. '. ; .•... 6-37
DS8859 Open Collector Hex Latch LED Driver ..................................................... 6·41
.oS8861 MOS to LED 5-Segment Driver ••.................... : ...•.......••.......: •....•..••.. 6-44
DS8863 MOS to LED 8·Digit Driver ............•....... , ............•...•................... 6-44
OS8864 LED Cathode Driver ...................................•.•...•••..•...•..•....... 6-35
DS8865 LED Cathode Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . • . . . . . . . . • . . . . . . . . . , .• ; ..• ~ . 6·35
DS8866 LED Cathode Dri~er .....•.. , ............ , •............•......••...... '.....•..•.•. 6-35
DS8867 8·Segment Driver ..............•.... I • ' , ' • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • ' • • • • • • • • • • 6·47
DS8868 12·Digit Decoder/Driver .................................. .' ...• '................... '. . . . • 6-49
OS8869 Open Collector Hex Latch LED Driver ..•..........•.....• ~ ........... , ...... ~' •..... '. :. 6-41
DS8870 Hex LED Digit Driver ....•.............•.................. ~ .......................... 6-51
DS8871 Saturating LED Cathode Driver .........•...........•..•....••... , ....... ; ..•....•... 6-53
DS8872 Saturating LED Cathode Driver .. '.......................•.... ; ~' ..•........••... , •..•. ,6-53
DS8873 .Saturating LED Cathode Driver ........... ~ .............. ,' ...... '..................... 6~53
DS8874 9-Digit Shift Input LED Driver ..•......................•.•....• ' ..•.....•..• ~; •..•... 6-55
DS8876 9-Digit Shift Input LED Driver .•...•................•..• ; ...... '.......... ; ..•.....•. 6-55
DS8a77 6-Digit LED Driver ...•......•........•.••....•..••.. .' , .. ; •. " .................... ,. 6-57
058879 9-Digit Shift input LED Driver ...........•...............•....•...... : ......•.. " . " 6-55
0"58880 High Voltage 7-Segment Decoder/Driver ........•........•..••..•..........•.........••.. ·.6-59
DS8884A High Voltage Cathode Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , ..... : ..•....•. 6-62
DS8885 MOS to High Voltage Cathode Buffer ...........•..•..•...........•.......•.....•....•. 6-64
DS8887 8·Digit High Voltage Anode Driver ......•.....•...•.•.•......•..•.............. '...•.•. 6-56
DS8889 8-Digit High Voltage Cathode Driver ......•..•.....•.....• ; ..••....••..•..•...•...... '.. ,6-66
DS8891 High Voltage Anode Driver (Active Low Inputs) . . . . . . . . . . . . . . . . . . . . . . . ' .•......•... ; ....... 6·70
DS8892 Programmable Hex LED Digit Driver ........................•.......• .- .......•.........6-72
DS8895 Quad LED Segment Driver ...... ; . . . . . . . . . • . . . . . . . . . . . . . . . . . . ; .......•....•........ ,6·74
DS8897 8-Digitliigh Voltage Anode Driver ..................•.•. , ..........•............., ....• ,6-66
DSa963 MOS to LED 8'Oigit Driver .......•..................•....... ; '...••..............•.. 6-44
DS8973 LED 9·Digit Driver . _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '6-77
DS8974 LED 9-Digit Driver . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . ; ..........•..•................• 6-77
DS8976 LED 9-Digit Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . • . . • . . . . . ' •........ _ •.. 6'77
DS8977 Saturating LED Cathode Driver ....................................................... 6-53
DS75491 MOS to LED Quad Segment Driver •.. ' .....•....•.•....... : ........•............•' ..... 6-79
DS75492 MOS to LED Hex Digit Driver ...•....................•....•.....•...•..•....•...... 6-79
DS75493 Quad LED Segment Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6'82
DS75494 Hex Digit Driver ........•..•.................•..............•.....•.•..... ',' ... 6-84
OPTO-COUPLERS - SECTION 7
053660 Optically Isolated Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . • . . • . . . . .
DS3661 Optically Isolated Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NCT200 Phototransistor Opto-Coupler ............ _ . . . . . . . . . . . . . . . . . . . . . . . . . " ...... '........ ' ..
NCT260 Phototransistor Opto-Coupler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '............ : .'...
4N25 Phototransistor Opto-Coupler . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . • . . •' ..
4N26 Phototransistor Opto-Coupler
4N27 Phototransistor Opto-Coupler
4N28 Photo transistor Opto-Coupler .................................... ;, .................... .
7-1
7-1
7-4
7-4
7·6
7-6
7-5
7-6
APPLICATIONS/BRIEFS -SECTION 8
AN-22
AN-76
AN-83
AN-84
AN-99'
viii
Integrated Circuits for Digital Data Transmission .• , ........•...•..............•" ...... , .....
Applying Modern Glock Drivers to MOS Memories .......................• :... " .... ' .......... "
Data Bus and Differential Line Drivers and Receivers .......•.............••.......•.• , .. ' ...•. '
Driving 7-Segment Gas Discharge Display Tubes with NS Circuits ..................•...........•..
Driving 7 -Segment LED Displays with NS Circuits •. .o........................................
8-1
8-17
8-27
8·39
8-43
APPLICATIONS/BRIEFS - SECTION 8 (CONTINUED)
AN-lOB Transmission Line Characteristics ___ ... '. . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . . _ ..
AN148 Driver Update-New Drivers'for LED Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OB-l Switching Time Testing of Opto-Couplers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ ..
OB-2 The Odd Coupler _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ .. _ .... '.......
8-55
8-61
8-71
8-72
MIL-STD-883, MIL-M-38510/ DEFINITION OF TERMS/ PHYSICAL DIMENSIONS - SECTION 9
/
ix
~
Alpha~Numei'ical
Index
NA'I1ONAL
DM5441A BCD to Decimal Decoder/Nixie™ Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM5446A BCD to 7-Segment Decoder/Driver .. : . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM5441A BCD to 7-Segment Decoder/Driver ................ \.....•.................•..........
DM544B BCD to 7-Segment Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7441A BCD to Decimal Decoder/Nixie™ Driver ....... ' ................. '.......................
DM7446A BCD to 7-Segment Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '...................
DM7447A BCD to 7-Segment Decoder/Driver ........ ; . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . , .....
DM7448 BCD to 7-Segment Decoder/Driver . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54141 BCD to Decimal Decoder/Driver . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . ; ....
DM74141 BCD to Decimal Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . .
DS0025 2 Phase MOS Clock Driver, . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . : ..........•............. ,
DS0025C 2 Phase MOS Clock Driver . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . • . . . . . . . . . . . . • . . . . . . . . . .
DS0026' 5 MHz 2 Phase MOS Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . .
DS0056 5 MHz 2 Phase MOS Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . .
OS 1488 Quad Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS1489 Quad Line Receiver ... , ............. '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS1489A Quad Line Receiver
DS1603 Dual Line Receiver . . . . . . . . . . . . . . . . . . . . . ., . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS1605 High Speed Hex MOS Sense Amplifier ....................... ' . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS1606 High Speed Hex MOS Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '..... ; ......
DS1607 High Speed Hex MOS Sense Amplifier ...................................................
DS1608 High Speed Hex MOS Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS1611 Dual Peripheral Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • '..•. ' ....•............... "
DS1612 Dual Peripheral Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . '............
DS1613 Dual Peripheral Driver ............. ,.................................................
DS1614 Dual Peripheral Driver .........................•.•............•......•....•....•..
DS1630 Hex CMOS Compatible Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . .
DS1631, CMOS Dual Peripheral Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '..................•
DS1632 CMOS Dual Peripheral Driver" . . . . . . . . . . . . . . . . . . . . . .
DS1633 CMOS Dual Peripheral Driver . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . .
DS1634 CMOS Dual Peripheral Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS1640 Quad Mb~ TRI-SHARETM Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . •
DS1642 Dual Bootstrapped MOS Clock Driver ............ '............ '. . . . . . . . . . . . . . . . . . . . . . . . . .
DS1645 Hex TRI·STATE® MOS Latch/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . .
DS1646 6-BitTRI-STATE® MOS Refresh Counter/Driver ..........•....
DS1647 Quad TRI-STATE® Memory I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '............
DS1648 TRI·STATE® MOSMultiplexer/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . •, ....•
®
.
'
DS1649 Hex TRI-STATE MOS Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ., ............•.........
DS1670 Quad MOS TRI-SHARETM Driver .....•.......•..........•...
DS1671 Bootstrapped 2 Phase MOS Clock Driver ........ " ........................................
DS1672 Dual Bootstrapped MOS Clock Driver .........•....•................
,DS1675 'HexTRI·STATE® MOS Latch/Driver .....
DS1676 6-Bit TRI-STATE® MOS Refresh Counter/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS1677 Ouad TRI·STATE® MOS Memory I/O Register .....•...................................•..
,
®
'
DS1678 TRI-STATE MOS Multiplexer/Driver' .............. : . . . . . . . . . . . . . . . . . . .
DS1679 Hex TRI-STATE® MOS Driver . . . . . . . . . . . . . . . . . . . . .
DS1686 Positive Voltage Relay Dri~er . . . . . . . . . . . . . . . . . .
DS1687 Negative Voltage Relay Driver
DS1688 Quad TR I-ST ATE® Differential Line Driver
DS1689 Ouad Differential Line Receiver
OS1.690 Quad Differential Line Receiver
DS3603 Dual Line Receiver
DS3604 Dual Line Receiver
DS3605 High Speed Hex MOS Sense Amplifier .
0
••••••••••••••••••••••••••••••••
0
0
••••••••••••••••••••
••••••••••••••••••••••••••
0
•••••••••••••••••••••••
0
0
•••••••••••••
:
• • • • • • • • • • • • • • • • • '.
••••••••••••••••••••••••••••••
0
0
0
0
0
0
0
0
•••••••••
0
0
0
0
•
'0
0
0
0
0
•
0
•••••
0
••
••••
0
0
••
0
••
0
0
0
•••
0
0
0
0
0
•
0
0
0
0
••
0
0
•••
o.
0
••••••
0
0"
0
•
0
00
0
0
•••
0
0
0
0
0
o.
0
0
0
0
0
0
0
••
0
•••••••••
0
•••••
••••••
0
0
•
••••
•
0
•
0
0
0
•
0
0
0
0
•
0
•••
0
___
_
•
0
0
0
0
0
••
0
0
0
:
0
••
......
0
0
0
0
0
0
0
0
0
•••
0
0
0
0
••
••
0
•••••
0
••
•••••
••••
0
0
•
0
0
••
0
•••••••••••
•••••••••
"
0
••
••••••
•
_
•
______
0
•
0
_
0
0'
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
_
••••
0
0
0
0
0
0
0
0
•
0
0
0
•
0
0
0
0
0
0
•••••••
0
0
0
0
0
•••
0
•
0
0
••
0
•••••
0
0
•
0
0
0
••
0
0
•
0
0
0
0
0
0
0
0
0
0
•
0
0
••
0
••
0
••••
0
•••
0
0
0
0
0
••
0
•
0
0
0
0
0
0
0
0
0
••••••
0
0
0
0
•
0
••
0
•
0
••
0
•
0
••••••
0
0
••
0
•
0
•
0
0
•
0
0
•
0
0
0
0
•
••
0
0
0
0
•••
0
•
0
0
0
0.'
•
0
0
• • '0
•
6-1
,6-3
6-3
6-3
6-1
6-3
6-3
6-3
6-8
6-8
4-1
4-1
4-4
4-4
3-1
34
3-4
3-56
5-1
5-1
5-1
5-1
1-1
1-1
1-1
1-1
2-1
1-7
,1-7
1-7
1-7
4-17
4-20
4-29
4-33
4-36
4-41
4-46
4-17
4-49'
4-20
4-29
4-33
4-36
4-41
446
1-13
1-15
3·6
3·8
3·8
3·56
3-56
5·1
D53606 High Speed Hex MOS Sense Amplifier . . . . . . . . . • . . . . . . . . . . . . • . . . . . . . . . . : . . . . . . . . . . . . . . . . 5-1
D53607 High Speed Hex MOS Sense Amplifier ... " . . . . . . . . . . . . . • • . . . . . . . • . . . . . _ . . • . . . . . . . . . . . . . . 5-1
DS3608 High Speed Hex MOS Sense Amplifier . . . . . . . . . . . . . . . _ . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
DS3611 Dual Peripheral Driver _ ...•........ _ . . . . • • . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . 1-1
DS3612 Dual Peripheral Driver . . . . . . . . . . . . . _ . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . _ .... 1-1
DS3613 Dual Peripheral Driver . . . . . . . . . . . . . _ . . • . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . 1-1
DS3614 Dual Peripheral Driver . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1'1
DS3625 Dual High Speed MOS Sense Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . 5-6
DS3629 Memory Driver with Decode Inputs . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ 4-11
D53630 Hex CMOS Compatible Buffer . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
D53631 CMOS Dual Peripheral Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
D53632 CMOS Dual Peripheral Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
D53633 CMOS Dual Peripheral Driver . . • . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
D53634 CMOS Dual Peripheral Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ •... 1-7
D53640 Quad MOSTRI-SHARE™ Driver _ . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
DS3642 Dual Bootstrapped MOS Clock Driver . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
DS3643 Decoded Quad MOS Clock Driver . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . 4-23
DS3644 Quad MOS Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . _ .......... : . . . . . . • . . . . . . • . . . . • .. 4-26
DS3645 Hex TRI-STATE® MOS Latch/Driver .. _ . . . . . . . . . . . . . • . . . . . . . . . . . . . • . . . . • . . . • . . . . . • . . . . 4-29
DS3646 6-Bit TRI-STATE® MOS Refresh Counter/Driver ..... ~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33
DS3647 Quad TRI-STATE® MOS Memory I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36
DS3648 TR I-STATE® MOS Multiplexer/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41
DS3649 Hex TRI-STATE® MOS Driver • • . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-46
DS3650 Quad Line Receiver . • . . . . . . . . • • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
DS3651 Quad High Speed MOS Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . 5-8
DS3652 Quad Line Receiver •....•..•..... _ . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
DS3653 Quad High Speed MOS Sense Amplifier . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . • . . . . . . . . . . . . . . . .. 5-8
D53660 Optically Isolated Line Receiver . . . . . . . . . . . . • • . . . . . . . . . . • . . • . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
D53661 Optically Isolated Line Receiver . . . . . . . . . . . . . • . . . . . • . . , . . . • . . . . . . . . . • . . • . . . . . . . . . . .-•.. 7-1
DS3670 Quad MOS TRI-SHARETM Driver . . . . . . . . . . . . . . . . . . . . . • . . . . • . . . . . . . . . • . • . . . . . . ' ....... 4-17
DS3671 Bootstrapped 2 Phase MOS Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-49
D53672 Dual Bootstrapped MOS Clock Driver . . . . . . . . . . . • . • . . . . . . . . • • . . . . . . . . . . . . • .' ..•..... ,... 4-20
DS3673 Decoded Quad MOS Clock Driver . . • . . . • . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
D53674 Quad MOS Clock Driver .......... _ .•....•.....•....... ' . . . . . . . . . . . . . . . • . . . . . . . . . . . 4-26
DS3675 Hex TRI-STATE® MOS Latch/Driver .... _ . . . . . . . . . . . • . . . • . . . . . . . . . . . . . . . . . . . . • . . . . . . . . 4-29
DS3676 6-Bit TR I-STATE® MOS Refresh Counter/Driver . . . . . • . • . . . . . . . . . . . • . • . . . . . . . . . . . . . • . . . . • . 4-33
D53677 Quad TRI-STATE® MOS Memory I/O Register . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . • • . . . . . . . . . . . 4-36
D53678 TRI-STATE® MOS Multiplexer/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41
D53679 Hex TRI-STATE® MOS Driver . . . . . . . . . . . . . . . . . . . . . . . • . . . '. . . . . . • . . . . . . . . . . . . . . • . . _ .. 4-46
D53686 Positive Voltage Relay Driver . . . . . . . . . . . . • . . . . . . " . . . . . . • . . . . . . . . . . . . . . ' ........ _ ..•.. 1-13
DS3687 'Negative Voltage Relay Driver . . . . . . . . . . . . . . . . . . . • • . . . . • . . . . . . . . . . . . . . . . . . . • . . . . . . • . . 1-15
D53688 Quad TRI-STATE® Differential Line Driver ..........•.••.•....•••....... '.•.•............ 3-6
D53689 Quad Differential Line Receiver ....•...• _ . . . . . . . . • . . . . . . . . . . . . . . . . • • . . . . • . • . . '..... _ .. 3-8
D53690 Quad Differential Line Receiver .....•...........•......••..•.....' •.....•............. 3-8
DS5520 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . • . . . . . . . • . . . . . . . . • . • . . . . . . . . • . . 5-13
DS5520A Dual Core Memory Sense Amplifier . . . . . . . . . • . • . . . . . . • . . . . . . . . . . . . . . . . . . . . . . • • . . . . . • . 5-13
DS5521 Dual Core Memory Sense Amplifier •........••..•......•..........•....... '.•....•.. , .. 5-13.
DS5522 Dual Core Memory Sense Amplifier .......•...,. ...... : .....••.......•........... _ .••.. 5-13
DS5522A Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • • . . . . . . • . . . 5-13
DS5523 Dual Core Memory Sense Amplifier . . . . . . . . . . . . • . . . . • . . • . . • . . . . . . . • . . . . . . . .- ..•....., ... 5·13
DS5524 Dual Core Memory Sense Amplifier •..................•..•. ; . . . . . . . . . . . . ,..•• _ •....•... 5-13,
DS5524A Dual Core Memory Sense Amplifier ................•..••.•.......••......••. __ •••..•. 5.13
DS5525 Dual Core Memory Sense Amplifier ...•.....•........•.•.....•. ; ..........••.•... _ .. _ . 5-13
DS5528 Dual Core Memory Sense Amplifier •...•....•..........•..........•. ".... _ .......•..... 5-13
DS5528A Dual Core Memory Sense Amplifier . . . • . . . . . . . . . . . . . . . . • . . . . . . . • . . . . . . • . . . . . . . • • . . . . _ 5-13
DS5529 Dual Core Memory Sense Amplifier ...•.....•.......... , . . . . . . . . . . . . . • . . . . . _ ..•.......• 5-13
DS5534 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . • . • . . . . . . . . . . • . 5-13
DS5534A Dual Core Memory Sense Amplifier . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13,
DS5535 Dual Core Memory Sense Amplifier ..•.....••........... _ ........•.•.......•...••..... 5-13
DS5538 Dual Core Memory Sense Amplifier . . . . . . • . • . . . . . . . . . . . . . . . . . • . . . . . . . . . . ., ....•.•...... 5-13
xi
DS5538A Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.13
DS5539 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " 5-1(1
DS7520 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . ;0 • • • • • • • 0', 0' • • • • • • • • • • • • • 5.13
DS7520A Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , ...... - ••• 5.13
DS7521 Dual Core Memory Sense Amplifier .. - . . . . . . . . . . . . . . . . . .
5.13
DS7522 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . '0' • • • • • • • • • • • • • • • • • • • • • • • , • • • • • • • • • 5.13
DS7522A Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . - ........... - . . . . . . . . . . . . • . . . . . . . . . . 5.13
DS7523 Dual Core Memory Sense Amplifier .: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - ..• - ., . - ...... 5.13
DS7524 Dual Core Memory Sense Amplifier ................•..........•.
5.13
DS7524A Dual Core Memory Sense Amplifier ............................•...•...•..... , ........ 5.13
DS7525 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • ; ..•........ 5.13
DS7528 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . ; ... 5-13
DS7528A Dual Core Memory Sense Amplifier .... '0' • • • • • • • • • • • • • • • • • • • • • • • • , ; " 0 ' • • • '0 • • • • • • • • • • • • 5-13
DS7529 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . _ ... _ . . .. .• 5-13
DS7534 Dual Core Memory Se(1se Amplifier
5-13
DS7534A Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . '.. 00' • • • • • • • • • • • • • • • • • • • • • , • 0• • • • • • • • • 5-13
DS7535 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . '.. . •... • .. • . . . .. 5-13
DS7538 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-13
DS7538A Dual Core Memory Sense Amplifier . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . • . 5.13
DS7539 Dual Core Memory Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . • ; .... ',' .. ' ........ _ . _ .. 5-13
DS7640 Quad NO R Unified Bus Receiver . . . . . . . . . . . . . . . . . . . . . . . • . . . . . • ' .....•.......•...... ,;.. 3-15
DS7641 Quad Unified Bus Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . • . . . . . . . . . . . . . . '. . . . . .. 3-17
DS7BOO Dual Voltage Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ; .•................. 2-4
DS7802 Dual High Speed MOS Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .' .... '...•.... 5-32
- DS7803 2 Phase Oscillator/Clock Driver . . . . . . . .. . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-56
DS7806 Dual High Speed MOS Sense Amplifier . . . . . . . . . . . . . . ,. . . . . . . . . . . . . ; . . . . • . . . . . . . . . . . . . . . _ 5-32
DS7807 2 Phase Oscillator/Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . ,' ......... ; ............. 4-56
DS7810 Quad 2-lnput TTL·MOS Interface Gate . . . . . . . . . . . . . . . . . . . . . . . • . • , .........•..... "" . , .. 2-7
D$7811 Quad 2-lnput TTL-MOS Interface 'Gate . . . . . . . . . . . ' . . . . . . . . . . . . . . . . . . . . . . . . . '" ........ " 2-7
DS7812 TTL·MOS Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2'7
,DS78L 12 TTL·MOS Hex Inverter/Interface Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . 2,10
DS7819 Quad 2-lnput TTL·MOS AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . 2-12
DS7820 Dual Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .' . . . . . . . . . . . . . ., ....• 3-22
DS7820A Dual Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,. . . . . . . . . . . . . . , . . . . . . . . . . . . . . 3'25
DS78LS20 Dual Differential Line Receiver . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . • . . . . . . . . • . 3-.29
DS7822 Dual Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . ,." .... : .....- ...•......•... 3-31
DS7830 Dual Differential Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . 3-34
DS7831 TRI·STATE® Line Driver . . . . . . . . . . . . . . . . . . . ; ...•... -. . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . 3-37
DS7832 TRI·STATE® Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • • . . . . . . . . . . . . 3-37
DS7833 Quad TRI-STATE® Party Line Transceiver ...... ,. . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . • '; ...... 3-42
DS7834 Quad TR I·ST ATE® Party Line Transceiver . . . . . . . . . . . . . . . . . . . . . . .' ......•.•....' •......... 3-46
DS7835 Quad TRI·STATE® Party Line Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . .'. 3-42
DS7836 Quad NOR Unified Bus Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '. . . . . . . . . . . . . . . . . . . . 3'15
DS7837 Hex Unified Bus Receiver .. '. . . . . . . . . . . . . . . . . ',' . . . . . . . . . . . . . . . . . . '......•....•.. ",' ... 3-52
DS7838 Quad Unified Bus Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '; .. " ....•............ 3,54
DS7839 Quad TR I·STATE® Party Line Transceiver . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . ,.........•...... 3·46
DS7856 BCD to 7-Segment LED Driver ... ,. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : .. 6-37
DS7858 BCD to 7 ·Segment LED Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ", ...... " •. . . . . . . . 6-37
DS7880 High Voltage 7-Segment Decoder Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '..... , ....... 6-59
DS7885 MOS to High Voltage Cathode Buffer . . . . . . . . . . . . . . . . ' . . . . . . . . . • . . . . . . . . . . . . . . . . . . . '•.... 6-64
DS7887 8-Digit High Voltage Anode Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ', ... '. . . . . . . . . . . . . . . . . • 6.66
DS7889 8-Digit High Voltage Cathode Driver . . . • . . . . . . . . . . . . . . . . . . . . . . . . . ; ..... ' . . . . . . . . . . . . . . . . 6·66
DS7891 High Voltage Anode Driver (Active Low Inputs) . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . ; ... '.. ,6·70
DS7895 Quad LED Segment Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .' . . . . . . . . . . . . . . . . . . . . . . . . 6-74
DS7897 8-Digit High Voltage Anode Driver . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . '•............ ; ... 6-66
DS8640 Quad NOR Unified Bus Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . 3·15
DS8641 Quad Unified Bus Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . . . . ; . ; ... '....... 3-17
DS8642 Quad Transceiver . . . . . . . . . . . . . . . . . .' ......., . . . . . . . . . . . . . . ;'" ......... .' ............ 3-19
DS8650 Low Voltage 4-Digit LED Driver ..........................•...•.. ; ................•.• :. 6-10
DS8651 Low Voltage 7-Segment LED Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . , ... : ....... 6-12
DS8654 8-0utput Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,' . . . . . . . . . . . . . . . . • ', .......
6-14
DS8655 12-0utput Decoder/Driver and Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
0'
•••••••••••••••••••••••••••••
0
°
• • • • • • • • • • • • • • • • • • • • • • •
•••••••••••••••••••••••••••••••••••••••••••••••••••
0• • • • • • • • • • • • • • •
"
' ••••••
0• • •
xiJ
DS8656 Diode Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8658 Low Voltage 4-Digit LED Driver ......... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8659 Low Voltage 7-Segment LED Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • .
DS8673 7·Segment Decoder/Driver/Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8674 7 ·Segment Decoder/Driver/Latch . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . • . . . .
DS8692 Printing Calculator Interface Set . . . . . . . . . . . . . . . . . . '................................... .
DS8693 Printing Calculator Interface Set .............................•.....•...... , .... , ..... .
DS8694 Printing Calculator Interface Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . .
DS8800 Dual Voltage Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8802 Dual High Speed MOS Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . .
DS8803 2 Phase Oscillator/Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8806 Dual High Speed MOS Sense Amplifier . . . . . . . . . . . . . . . . . ., . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8807 2 Phase Oscillator/Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8810 Quad 2-lnput TTL-MOS Interface Gate . _ ............... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8811 Quad 2-lnput TTL-MOS Interface Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , .. .
DS8812 TTL-MOS Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS88L 12 TTL-MOS Hex Inverter/Interface Gate . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . . _ .. .
DS8813 2 Phase Oscillator/Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -. . . . . . . . . . . . . . . . . . . . .'.
DS8817 2 Phase Oscillator/Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8819 Quad 2-lnput TTL-MOS AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8820 Dual Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : .. .
DS8820A Dual Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS88LS20 Dual Differential Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8822 Dual Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8830 Dual Differential Line Driver . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . •
DS8831 TRI-STATE® Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . .
DS8832 TRI-STATE® Line Driver . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .' ........•..
DS8833 Quad TRI-STATE® Party Line Transceiver . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8834 Quad TRI-STATE® Party Line Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8835 Quad TRI-STATE® Party Line Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8836 Quad NOR Unified Bus Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8837 Hex Unified Bus Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8838 Quad Unified Bus Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . .
DS8839 Quad TR I-ST ATE® Party Line Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . .
DS8844. LED Cathode Driver .......... : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ., ...•.......
DS8855 LED Cathode Driver .. " ..................................................... , .... .
DS8856 BCD to 7-5egment LED Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . .
DS8857 BCD to 7-Segment LED Driv,er' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '........... .
DS8858 BCD to 7·Segment LED Driver ...................... " ............. , .......... _ .. ' ...•..
DS8859 Open Collector Hex Latch LED Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . .
DS8861 MOS to LED 5-Segment Driver .....................................•..........•......
DS8863 MOS to LED 8-Digit Driver ...... ,. . . . . . . . . . . . . . . . . . .' ..... " . . . . . . . . • . . . . . . . . . . . . . . . . . .
DS8864 LED Cathode Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . .
DS8865 LED Cathode Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . ; ... .
DS8866 LED Cathode Driver . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . • . . . . . . . . '.............. .
DS8867 8,Segment Driver ..... " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8868 12-Digit Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . • '.... ' •..•. ;' .....•..........
DS8869 Open Collector Hex Latch LED Driver . . . . . . . . . . . . . . . . . . . . • . . . . • . . . . . . . . . . . . . . . . . . . . . . .
DS8870 Hex LED Digit Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8871 Saturating LED Cathode Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . • . . . . . . . . . .
DS8872 Saturating LED Cathode Driver . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . . . . . . . • . . . . . . . . . . . . .
DS8873 Saturating LED Cathode Driver ......•...............•................................
DS8874 9-Digit Shift Input LED Driver • . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8S76 9-Digit Shift Input LED Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8877 6-Digit LED Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8879 9-Digit Shift Input LED Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . . . . .
DS8880 High Voltage 7-Segment Decoder/Driver . . . . . . . . . . . . . . . . . . '.................. _ . _ ......... .
OS8884A High Voltage Cathode Decoder/Driver ............ '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .' .. ,
DS8885 MOS to High Voltage Cathode 8uffer ............ '..... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . .
DS8887 8-Digit High Voltage Anode Driver ..... -. " . " . '. . . . • . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . .'....
DS8889 a-Digit High Voltage Cathode Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . • . .
DS8891 High Voltage Anode Driver (Active Low Inputs) . . . . . . . . . . . . . . . . . . . . . • . , ................•...
6-14
6-20
6-12
6-22
6-22
6·28
6-28
6-28
2-4
5-32
4-56
5-32
4-60
2-7
2-7
2-7
2·10
4-56
4-60
2-12
3-22
3-25
3-29
3-31
3-34
3-37
3-37
3-42
3-46
3-42
3-50
3-52
3-54
3-46
6-35
6-35
6-37
6-37
6-37
6-41
6-44
,6-44
6-35
6-35
6-35
6-47
6-49
6-41
6-51
6-53
.6-53
6-53
6-55
6-55
6-57
6-55
6-59
6-62
6.64
6-66
6-66
6-70
xiii
0$8892 Programmable Hex LED Digit Driver ••• ; •.•...••.•.••••••.••••.•••.••......••..••.•.•.•• 6-72
DS8895 Quad LED Segment Driver ....•••.•.•.•.•••••••••••••.••..••••.•••.•••••• '.' ; •••••• " 6-74
DS8897 8-Digit High Voltage Anode Driver .•••....••..•••..••••.•••••••••••...•.••••.• ' .••••••• 6-66
DS8963 MOS to LED 8-Digit Driv,er .•.•••.•• " .•••.•••••.••••••••••••••••• ',' •••.• , •.•••••••• 6-44
058973 LED 9-Djgit.Driver .•....•.•..•••.•...•.••••••.•••.•••..••• ' •••••••.••••.••••••••• 6-77
DS8974 LED 9-Digit Driver •.••....••.......•.••...•••..•••••••••••••••••.••..•• ; .••••.••• 6-77
DS8976 LED 9-Digit Driver ...........•....••.•••..••••.••..••.•••••.• ; •••••••...•••.••• , 6-77 ,
DS8977 Satutating LED Cathode Driver •..•..•••.•••..•••••••••.•••••••••.••...•...•••.•••••. 6-53
DS16147 Quad TRI-5TATE® MOS Memory I/O Register •.•.•••.•.•••••.••••••••.•••..•••.• ; ••••••• 4-36
DS16149 Hex MOS Driver ••.....•...••.•••••••.••..•••••..••••••••.•••••.••••••.•..••••. 4-53
DS16177 Quad TRI-STATE® MOS Memory I/O Register •.••.••••••••••••••••••••••...•.••.•••••••• 4-36
DS16179 Hex MOS Driver ..........•••...••...••.••••.•••.•••.•••.••••••••.•.•.•••.•••••. 4-53
DS36147 Quad TRI-STATE® MOS Memory I/O Register •.••.••.••••..•••• : .•...•••••••.•••..••• ;; . 4-36
0536149 Hex MOS' Driver .••.••.••.•.••...•...•••..••.•••.••••.••••.•••••.••••.••••••••. 4-53
0536177 Quad TRI-STATE® MOS Memory I/O Register •••••.•.••••••...••••••••••.••••.•.•...••••• 4-36
0536179 Hex MOS Driver .......••...•.••.• _ •.••..•.•••.•••••.••.•.. ',' .............. ,.•••• 4-53
DS55107 Dual Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-56
DS55108 Dual Line Receiver ..•...••.•.•••...•.•..•..•••.....•.••••.•••••••.•••••••••• '•.• 3-56
DS55109 Dual Line Driver ................................................................. 3-63
DS55110 Dual Line Driver ••.•.•...•...••...•....••...•..•.•••.•.•••••..••..•••.••.•.••.. 3-63
DS55121 Dual Line Driver ..•..•....•..••.••.••..•••••.•.••.••.••••••.•..•••..•••.•••• ; .• 3-66
DS55122 Triple Line Receiver .....•...•••.••..••.••.....•••.•••...•.••••.•••.•.• ; •••.••••. 3-68
DS55325 Memory Driver • _ ... _ ....•• _ ••.•.••• ' .•••••••..•••••••••••.•••••..•••••••••.•••• 4-7,0
DS55450 Dual Peripheral Driver ...••..•.....• , •••••••••••••••..•••.••.•.•..••••.••••• ; ••••. 1·17
DS55451 Dual Peripheral Driver ..•....•....•..••...•..••••.•..•..•••...••.••.••...••••••.• 1-17
DS55452 Dual Peripheral Driver •.•....•..•••..•.••.....•.....•••..•••.•••.•..•••••..•..••• 1-17
DS55453 Dual Peripheral Driver ..•• _ ...•..•.•••.•••••.••••••••.•.•.•••.••••••.•••••••••..• 1-17
DS55454 Dual Peripheral Driver .•.••.•••.•••• " ............................................. 1-17
DS55460 Dual Peripheral Driver ..••.•..••••.••.•••...••••..•••••••••••••••.•••••••.•..•.•• 1-28
DS55461 Dual Peripheral Driver ..•...•.....•..••.•.••.••••.•••••••••..•.•..•••.••••••••••• 1·28
DS55462 Dual Peripheral Driver ...•.•..•..•. .. • . . . • • . • • • • . • . • • • • • • • • . • . • . • • • • . • • • • . • • . • • . •• 1-28
DS55463 Dual Peripheral Driver ...•.••.•...••.••••••••.••••••.••••••••.••••••••••••••••••• 1-28
DS55464 Dual Peripheral Driver ...•.•...•••..•• .. • • . . . • • • . • • . • . . • • • • • . • • • • • • • . • • • . • • • . • . • •. 1-28
DS75107 Dual Line Receiver ..•..••••.•.•.••.....•..••.••••.••••••..•••..•.•.•••.••.••••• 3-56
DS75108 Dual Line Receiver .••....•••••••.•••.•.•••••.•••.••••.••••••.•••••••.•.••• ; •••• 3-56
DS75109 Dual Line Driver .........••........•..•.•...••........••••.. '. . . . . . . . • . . . • • • . • •. 3-63
DS75110 Dual Line Driver ... _ ...•...•.••.•..•..••...•••••...•.•.•....•••.•••..••••••••.. 3-63
DS75121 Dual Line Driver •.. _ ................................................... ; •.•••.••• 3-66
DS75122 Triple Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-68
DS75123 Dual Une Driver •....•..•.•...•...•..••••••••••.•••••••.••••••••••••.•••••••.•• 3-71
DS75124 Triple Line Receiver .................... '",' •...•.•.•••••.•.•..••.•••• '........... ; •.• 3-73
DS75150 Dual Line Driver .••..•.••••.•••••••••••••.••••, ........................... '..••••• 3-76
DS75154 Quad Line Receiver ....•...••..•.•••••..•••....•..•..•.•.•••.....••••.••.•.••.••• 3-79
OS75207' Dual Line Receiver, '" _ •.... _ . __ .•••.••••.. '•••..•.••.•.••••.••..••.•.•••...••••• 3-56
DS75208 Dual Line Receiver .....••..•.••••...•.•••...•••.•••.•.•..•.•••••.••.•...•••.•.• 3-56
DS75324 Memory Driver with Decode Inputs .. ,.•...•.•.•••••••••••.••••••••.••••.•• '.•••••...•• '4-64
DS75325 Memory Driver .•••. _ .••.•.•••.....••. ; .••..••.•.•••.••...•••..•.•••••••.•••••• 4-70
DS75361 Dual TTL to MOS Driver •• _ ••.•••..•.•.••••..•..•••..••.••.•••..••••••••••• '••.•.. 4'77
0575362 Dual TTL to MOS Driver .••.. " .•..•.••••..•••••.••••.••••.•••••••••••.•••• ; ••••.• 4-62
DS75364 Dual MOS Clock Driver .•.•.•....•. __ .. _ .....................' •••• : •.••••••••.•••.• 4-87
DS75365 Quad TTL to MOS Driver ••...•.•.•.••.•••....•.•••••••••.••.••••• '••.••••.•.•••••• 4-91
DS75450 Dual Peripheral Driver ..•.••.•.•••••.•..•••.....•.•.•.....•' ..•••• : ..••.•..•••..•• , 1-17
DS75451 Dual Peripheral Driver .•..•.•.••..•.•••••.••...•.•••••••••••.•••••.••.•.•.•..•••• 1-17
DS75452 Dual Peripheral Driver ••..•..•....•....•.• ' .••......••••.•••..•••.••..••..•••...•. 1-17
DS75453 Dual Peripheral Driver ....••...••.••.••••••••.•••••.•••••••' •••..•••.•••••••.•••.•• 1-17
DS75454 Dual Peripheral Driver
1-17
0$75460 Dual Peripheral Driver
. :................................
", 1·28
OS75461 Dual Peripheral Driver
1-28
e '• • • • . • • • • . • ,• • . • • • • •
DS75462 Dual Peripheral Driver
1-26
1:28
DS75463 Dual Peripheral Driver
~
......................
••••
0"0
••••••••••••
••••••••••••
xiv
".0
. ...
"
•••••••••••••••••'
"•••••••••••••••••••••••
,0
• • • • '0
••
••
••• ' •••••••••••••••••
" .•
DS75464 Dual Peripheral Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS75491 MOS to LED Quad Segment Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS75492 MOS to LED Hex Digit Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS75493 Quad LED Segment Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS75494 Hex Digit Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NCT200 Phototransistor Opto-Coupler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NCT260 Phototransistor Opto-Coupler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4N25 Photo transistor Opto-Coupler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4N26 Phototransistor Opto-Coupler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4N27 Phototransistor Opto-Coupler
4N28 Phototransistor Opto-Coupler
1-28
6-79
6·79
6-82
6-84
7-4
7-4
7-6
7-6
7-6
7-6
xv
Thermal Ratings For
leis
MAXIMUM POWER DISSIPATION
To insure reliable long term operation of its Interface
Integrated Circuits, National Semiconductor has spec·
ified maximum junction temperature I"T"J) limits. These
limits are at 150°C for circuits packaged in a molded
dual·in·line package (Epoxy B);and 175°C for all other
package types.
ponding to the package thermal resistance (1/ 0 J-x),
Below this line is' the safe operating area of the device.
Additional constraints are Maximum Power DI~sip~tio'n
and Maximum Operating Temperature (TA)' These
parameters may be determined from device data sheets.
For this example, PO(MAX) = 300 mW and TA(MAX) =
70or;.
Maximum power dissipation (Po) of an integrated
circuit is limited by maximum allowable,junction tem·
perature of the silicone die, and thermal resistance
(0 J-x) of the package. Figure 1 illustrates the relation·
ship between power dissipation and junction tempera·
ture.
,Point "A" in Figure 1 is an operating point corresponding to TA = 50°C ~nd Po = 100 mIN. Determine
device junction temperature by projecting a line from
point" A," parallel to the Maximum Power Rating curve,
until it intersects the horizontal axis. TJ is determined
from the point of intersection with the horizontal axis.
For this example, Tj is 45°C.
The line indicating "Maximum Power Rating of Pack·
age" is projected from the maximum jl)nction tempera'
ture limit (150°C in this example) at a slope corres·
Figure 2 illustrates thermal resistance characteristics
THERMAL INFORMATION
for Interface Integrated Circuit packages.
0.7
~
0.6
'"
0.5
:1:
0.4
Q
"'-...
;::
;;;
'"
is
a:
'-.....
"'4.t,
~IIt,oOill"'II
0.3
I~l<
I
f'-..-..
w
;=
Q
,"-
0.2
A
0.1
o
I"-J.
o
25
50
75
100
TEMPERATURE
"-
125
rc)
FIGURE 1. Power Dissipation vs Temperatur.
1.8
~
THERMAL RESISTANCE
1.4
G (TO-B)
H (TO·5)
J (C·DIP)
N (Molded)
12
8
14,16
14,16
1.2
N (Molded, Copper Frame)
14,16
8
'"
;:: 1.0
:1:
is
,---1'-"":~"""'~~--
0.8
a:,
w
;=
!2
100
200
80
120
140
80
90
~~~~~-~---- =~!i~~d Jr~: a:~~:ec~e::~~~:te~::
Q
ill
LEADS
PACKAGE
1.6
devices, and reflect a 90% confidence
level. Refer to data sheets for specific
deyice information. Measurements were
made in still air with pacJlage soldered
into a printed circuit board.
0.6
0.4
0.2
25
50
75
100
125 '
150
TEMPERATURE (OC)
FIGURE 2. Maximum BJ_X Values for Ie Packages
xvi
175
200
~
Interface Cross Reference Guide
NAnONAL
NATIONAL
EXACT
REPLACEMENT
DEVICE
NUMBER
DEVICE
NUMBER
Texas Instruments (can't)
Fairchild
9374
OS8674
Motorola
MC1488
MC1489
MC1489A
MC3437
MC3438
MC3441
MC3443
MC3450
MC3452
MC3460
MC3483
jIolC3484
MC3485
MC3489
"
OS1488
OS1489
OS1489A
OS8837
OS8838
OS3651
OS3653
OS3650
OS3652
083674
OS8833
OS8834
OS8835
OS8839
Signetics
SP380
8T13
8T14
8T23
8T24
8T25
8T26
8T34
8T37
8T38
8T51
8T59
8T74 '
8T380
NATIONAL
EXACT
REPLACEMENT
:
OS8640
OS75121
OS75122
OS75123
OS75124
OS3625
OS8826
OS8834
OS8837
OS8838
OS8856
OS8857
OS8672
OS8836
Texas Instruments
SN5520
SN5521
SN5522
SN5523
SN5524
SN5525
, SN5528
SN5529
SN5534
SN5535
SN5'538
SN5539
SN7520
SN7521
SN7522
SN7523
SN7524
SN7525
SN7528
SN7529
SN7534
SN7535
SN7538
S!'I7539
SN55107
SN55108
SN55109
OS5520
OS5521
OS5522
OS5523
OS5524
OS5525
OS5528
OS5529
OS5534
OS5535
OS5538
0S5539
OS7520
OS7521
OS7522
OS7523
OS7524
OS7525
OS7528'
OS7529
OS7534
OS7535
OS7538
OS7539
, OS55107
OS55108
OS55109
\
SN55110
SN55121
SN55122
SN551!;0
SN55154
SN55180
SN55182
SN55183
SN55207
SN55208
SN55325
SN55361
SN55365
SN55369
SN55450
SN55451
SN55452
SN55453
SN55454
SN55460
SN55461
SN55462
SN55463
SN55464
SN55480
SN55493
SN55494
SN75107
SN75108
SN75109
SN75110
SN751:l1
SN75122
SN75123
SN75124
SN75150
SN75154
SN75180
SN75182
SN75183
SN75188
SN7!i189
SN75189A
SN75207
SN75208
SN75324
SN75325
SN75361
SN75362
SN75365,
SN75369
SN75450
SN75451
SN75452
SN75453
SN75454
SN75460
SN75461
SN75462
SN75463
SN75464
SN75480
SN75491
SN75492
SN75493
SN75494
OS5511O
OS55121
OS55122
OS55150
OS55154
OS7800
OS7820A
OS7830A
OS55207
OS55208
OS55325
OS55361
OS55365
OS0026
OS55450
OS55451
OS55452
OS55453
OS55454
OS55460
OS55461
OS55462
OS55463
OS55464
OS7880
OS55493
OS55494
OS75107
OS75108
OS75109
OS7511O
OS75121
OS75122
OS75123
OS75124
OS75150
OS75154
OS8800
OS8820A
OS8830
OS1488
OS1489
OS1489A
OS75207
OS75208
OS75324
OS75325
OS75361
OS75362
OS?5365
OS0026C
OS75450
OS75451
OS75452
OS75453
OS75454
OS75460
OS75461
OS75462
OS75463
OS~
OS88
OS7549
OS75492
OS75493
OS75494
xvii
Transmission Line Driver and ,
Receiver Product Guide
~
NA110NAL
DEVICE
OS7820/0S8820
DRIVER OR
RECEIVER
R~i,ver
COMMON MODE
OR DIFFERENTIAL
Differential
INPUT
THRESHOLD
OUTPUT
LEVELS
200mV
TTL
POWER
SUPPLY
DESCRIPTION
ANO'COMMENTS
+5.0
Oual ±15V Common Mode
'+5.0
OS7820 EIA Standards
RS422,a(l,d R5423
+5.0
Quad EIA Standards
RS422 and RS423
Range
"
OS78L820
Receiver
Differential
±200mV
TTL
OSl689/053689
Receiver
Differential
±2oo mV
TTL
'.
Driver
Diffe':~ntial
TTL
TTL
+5.0
Quad EIA Standard RS422
057820A/058820A
Receiver
Differential
200mV
TTL
+5.0
High Performance 087820
0578221058822
Receiver
Differentiall
-2.0 to +20
TTL
+5.0
O'ual EIA 5tandard R5232
051688/053688
Common MOde
057830/058830
Driver
Difte'rentiat
TTL
TTL
+5.0
Dual
057831/0S8831
Driver
Differential!
TTL
TTL
+5.0
TRI'5TATE@057830
057832/058832
Driver
Differential!
Common Mode
TTL
TTL
+5.0
25mV
Common Mode
10 mV Threshold
OS55107 Dual
TTL
±5.0
10mV
TTL
±5.0
10 mV Threshold 0555107
25mV
TTL
±5.0
Open Collector 0555107
10mV
TTL
±5.0
10 mV Threshold 0555108
±25 mV
TTL
±5.0
Quad 0575107
±7mV
TTL
±5.0
Quad 0575107
±25mV
TTL
±5.0
Quad OS75108
±7 mV
TTL
±5.0
Quad 0575108
Differential
25mV
TTL
±5.0
TRI·STATE@ 0555107
Receiver
D ifferen tial
10mV
TTL.
±5.0
10 mV Threshold OS1603
Driver
Differential
TTL
6.0mA
±5.0'
Dual
0555107/0575107
Receiver
Differential
0555207/0575207
Receiver
Differential
0555108/0575108
Receiver
Differential
0555208/0575208
Receiver
Differential
053650
Receiver
Differential
053651
Receiver
Differential
053652
Receiver
Differential
053653
Receiver
Differential
051603/053603
Receiver
OS3604
OS55109/0575109
057831 Without Vee
Clamp Diodes
0555110/0S75110
Driver
Differential
TTL
12mA
±5.0
12 mA 0555109
0555121/0575121
Driver
Common Mode
TTL
TTL
+5.0
Dual 50n or Coax Driver
0555122/0875122
Receiver
Common Mode
0.8 to 2.0
TTL
+5.0
Triple with Hvsteresis
0855123/0575123
Driver
Common Mod;e
TTL
TTL
+5.0
0855121 for IBM
0555124/0575124
Receiver
CommonMooe
0.7 to 1.7
TTL
+5.!l
OS55123 for IBM
087834/058834
Transceiver
Comm<;m Mode
TTL
TTL
+5.0
Quad TRI-5TATE@
057835/0S8835
Transceiver
Common Mode
TTL
TTL
+5.0
OS7834 with 8trobed
Receiver
057839/058939
Transceiver
Transceiver
Common Mode
TTL
TTL
+5.0
Non~lnverting
ComMQnMode
TTL
TTL
+5.0
057839 with Strobed
Receiver
Common Mode
TTL
TTL
+5.0
Quad NOR with
057640/05S640
Receiver
Co~mon Mode
TTL
TTL
+5.0
057836 with No
OS7641 1058641
Transceiver
Common Mode
TTL
TTL
+5.0
OS7838 with No
Hysteresis,
OS8642
Trans~eiver
Common Mode
TTL
TTL
+5.0
Quad Open,Collector
with 100 mA Sink
OS7837/058937
Receiver
Common Mode
TTL
TTL
+5.0
Hex w,ith Hvsteresis
DS7838/058838
Receiver
Common Mode
TTL
TTL
+5.0
Quad Open Collector
with Hystttresis
OS14S6
Driver
Common Mode
TTL
±7.0V
±9.0 to 15
Quad EIA 5tandard RS232
051489
Receiver
Common Mode
0.75 to 1.5
TTL
+5.0
Quad EIA 5tandard R5232
OS 1489A
Receiver
CommonMoqe
0.75 to 2.25
TTL
+5.0
OS75150
Driver
Common Mode'
TTL
±8V
±12
Oual EIA Standard RS232
~eceiver
Common Mode
0.8t03
TTL
+5.0
Quad EIA Standard RS232
Interface
Interface
~vsteresjs
057833/088833
057834
Receiver
OS7836
Hysteresis
,
'
Hysteresis
"
with Hvster~sis
Higher Ncrise Immunity
OSI489
OS75154 A'
with Hysteresis
xviii
~
Peripheral Driver Guide
NA110NAL
c
~.
GENERAL DESCRIPTION
~
....
Nominal
Vee
(Voltsl
Series or Device Number
Output
Breakdown
Voltage
(Voltsl
Maximum
Maximum
Output
Leakage
(1lA1
Output
On
Current
(mAl
VOL (MaxI
At
Maximum
Output Current
(Voltsl
Typical
Propagation
Delay
(nsl
Current
0575450 5eries (0575450,
05350,0575451,0575452,
0575453, 05754541
5.0
30
100
300
0.7
15
053611 5eries (053611,
053612,053613,0536141
5.0
80
100
300
0.7
130
0575460 Series
5.0
35
100
300
0.7
40
CONNECTION DIAGRAMS
.,
B1
Xl
C1
E1
TOP VIEW
GNO
"
Xl
82
C2
E2
SUB
B1
C1
E1
GNO
TOP VIEW
08350
Vee
B2
0875450
0875460
A2
X2
TOPVIEW
TOP VIEW
0875451,083611,
0875461
0875452,083612,
0875462
Vee
82
A2
X2
0875453 (LM35l1,
083613,0875463
Vee
82
X,
0875454,083614,
0875464
C)
c
is:
~
.
.~
Q
Q
w
,
~
'
LED Driver Guide
'.'
','
NAT10NAL
'
NSC#
STATUS
OESCRIPTION
...I
lOUT
(Note 1)
TXP
mA
VOUT
MAX
V
#
PINS,
",
14 Digit LED Dr
14 Digit LED Dr
14 Digit LED Dr
F
P
P
F
F
'F
17 Digit LED Dr
P
9
8
9
8
P
P
P
P
P
P
P
6 Digit L EO Or
4 Digit LED Watch Dr
4 Digit LED Watch Dr
Digit
Digit
Digit
Digit
LED
LED
LED
LED
Dr
Dr
Dr
Dr
7 Digit LED Dr
12 Digit LED Dr
6 Digit LED Dr ,
9 Digit LED Dr
9 Digit LED Or
6 Digit LED Dr
9 Digit
LED Dr
6 Digit LED Dr
Digit
Digit
Digit
Digit
LED
LED
LED
LED
84
80
-15
.
50
50
500
50
50
50
110
350
40
40
40
50
50
40
50
250
Max
40
250
500
P
F
F
P
F
P
9 Digit LED Dr
9 Digit LED Dr
9
6
8
7
84
50
P
p
8 Digit LED Dr
058920
058962
058963
058972
058973
058974
D5B975
058976
058977
0575492
0575494
Or
Dr
Dr
Dr
F
P
P
ioo
5
5
5
10
10
10
10
10
10
10
10
10
5
10
,10
10
10
10
10
10
10
10
Dice
- 24
14
24
16
22
18
22
18
18
18
14
18
22
22
14
14
14
14
16
10
10
10
10
10
10
10
10
10
10
10
20
18
18
18
22
22
22
22
18
14
16
9 Digit LED Dr
9 Digit LED Or·
F
F
F
F
9 Digit LED Dr
F
7 Digit LED Dr
6 Digit LED Dr
6 Digit LED Dr
P
P
P.
100
100
,100
100
40
250
180
P
40
30
16
p~
40
.15
16
9 Digit LED Dr
.
Dice
Dice
·•
·
·
··
·
SEGMENT DRIVERS
DM7446A
BCD to 7Seg.
DM7447A
BCD to 7 Seg.
Decoder/Driver
Decoder/Driver
DM7448
BCD to 7 Seg.
058647
058648
058649
058651
058659
058672
9 Seg. LED Watch Dr
9 Seg. LE~ Watch
8 Seg, LED Watch Dr
7 Seg. LED Watch Dr
75eg. LED Watch Dr
BCD to 7 Seg. LED .'
P
058673
058674
BCD to 7 5eg. LED
Decoder/Latch/Dr
BCD to 7 5eg. LED
058675
BCD to 7 Seg. LED
058876
BCD to 7 5eg. LED
,
-2
N/A
16
Decoder/Driver
F
F
Dr
F
-10
'. -10
-10
-£.5
-10
20
5
16
F
15
5.5
16
F
15
5.5
16
F
40
Max
25
Max
-£
-50
-50
±50
-14
-14
15
5.5
16
5.5
16
5.5
5,5
5.5
10
8
10
5.5
16
16
16
18
18
16
16
±50
±50
±50
-30
18
18
10
10
14
18
14
16
F
P
P
-4
-4
-4
-4
-4
Oice
Dice
Dice
Dice
Dice
Decoder/Latch/Dr
..
Decoder/Latch/Or
Decoder/latch/Dr
F
Decoder/Latch/Dr
DS8858
058857
058858
058861
058867
058895
056910
BCD to 7 Seg. LED Dr
BCD to 7 Seg. LED Dr
8CD to 7 Seg. LED Dr
5 5eg. LED Dr
8Seg. LED Dr
4Seg. LED Dr
058960
058961
0575491
0575493
45eg.
5Seg.
45eg.
4589.
Note 1:
1 Decade Counter/Latch
7 Seg. Decoder/Driv~r
Positiv~
INV.
,
INPUTS
.
"
COMMEN1'S .. ;
,.,
DIG'IT DRIVERS"
058646
DSa650
058658
058664
bS8665
058666
058844
058855
058863
058864
058865
058866
058868
058870
058871
058872
058873
058874
058876
058877
058879
058892
OEC.
....
LED
LED
LED
LED
Dr
Dr
Dr
Dr
'
-
p"
P
p
P
P
P
F
F
F
P
p,
current is going into' device'. ,
·
·
··
·
··
·
·
··
··
·•
··
··
·
·
·
·
··
··
··
··
·
·.'
·
··
MOS
MOS
MOS
MOS
MOS
MOS
MOS
MOS
MOS
MOS
MOS
MOS
MOS
MqS
MOS
MOS ,
MOS
MOS
MOS
MOS
MOS
, Mas
MaS
MOS
Mas
Mas,
MOS
MOS
MOS
MOS
9V LBI
Serial Input, 9V LBI
,Serial Input, 6V I:-BI
0575492 Pin.()u't'
Serial Input, 4.5V LBI
Programm~b,le
'"
I
9V,LBI
4,5V LBI
ElV LBI ;
;
,"-
9V LBI
9V LBI
TTL
TTL
TTL
Requires External Transistor
M05
MOS
MOS
MOS:
MOS
TTL
For CM05 Watch Ckts
Fo, CMOS Watch Ckts
For CMOS Watch Ckts
TTL
Alpha-Numeric Output
;
TTl'
-:
TTL
'HL
TTL
M05
M05
Ma5
TTL
·
",,")
9V LSI
4.5V LBI
0575492 Pin~Out
0575492 Pin-Out
TTL
•
9V LSI
MOS
TTL
,,*
For CMOS WatehC!<.ts '
For,CMOS Watch Ckts
For CMOS Watch Ckts
On Chip Clock, 9V LBI
' On Chip Clock'
'POS Circoit,On Chip Clock
,
MOS
M05
MOS
MOS
For CMOS Watch Ckts
For CMOS Watch Ckts
Decodes 0-9, A, E, H, L, P
Decodes 0-9, -, E, H, L, P
Alpha-Numeric Output, lOUT
Externally Set
Alpha-Numeric Output, lOUT
, Programmable
R~quires External Transistor
lOUT Internally Set
lOUT Externally Set
* Inverting with Em itter Grounded
Preset lOUT
lOUT Internally Set
'*Inverting,with Emitter Grounded
*Invertingwith Emitter Grounded
* Inverting wi,th Emitter Grou nded
lOUT Set by External Res.
o
~
Opto-Coupler Cross Reference Guide
S
oo
c:
CD
...
'C
NATIONAL
(")
DEVICE
TYPE
NATIONAL
NUMBER
COMMENTS
NCT200
4N25
NCT200
Direct Replacement
NCT200
4N25
NCT260
Direct Replacement
Direct Replacement
Direct Replacement
Direct Replacement
Direct Replacement
Litronics
ILl
IL5
IL12
IL15
IL16
IL74
IL 100
4N25
4N25
NCT260
NCT260
NCT260
NCT200
OS3661
Direct Replacement
Selection Required For 50% C.T.R.
NCT200
NCT260
4N25
4N25
NCT260
Direct Replacement
Direct Replacement
Direct Replacement
Selection Required For Maximum 14% C.T.R.
Direct Replacement
Direct Replacement
Texas Instrument
TIL-lll
TIL-112
TIL-114
TIL-l17
TIL-118
Direct Replacement
Direct Replacement
Selection Required For 50% C,T.R.
Direct Replacement
Genera I Electric
HllAl
HllA2
Hl1A3
Hl1A4
HllA5
4N25
NCT200
4N25
NCT200
NCT260
Selection Required For 50% C.T.R.
CLl-2
NCT200
Selection Required For Minimum 30% And
Maximum 100% C.T.A.
CLl-3
NCT200
Selection Required For Minimum 100% And
Maximum 200% C.T.R.
CL1-5
CLl-20
NCT200
NCT200
Direct Replacement
Selection Required For Maximum 100% C.T.R.
NCT260
NCT200
NCT200
NCT200
Direct Replacement
Selection Required For Minimum 100% C.T.R.
Selection Required For Minimum 25% C.T.R.
Selection Required For Minimum 25% C.T.R.
4N25
4N26
4N27
4N28
4N35
4N25
4N26
4N27
4N28
NCT200
4N36
NCT200
4N37
NCT200
Direct Replacement
Direct Replacement
Direct Replacement
Direct Replacement
Selection Required For 3.5 kV Isolation And
Minimum 100% C.T.R.
Selection Required For 2.5 kV Isolation And
Minimum 100% C.T.A.
Selection Required For Minimum 100% C.T.R.
4N25
4N26
4N27
4N28
Direct
Direct
Direct
Direct
D53660
Direct Replacement
Direct Replacement
Direct Replacement
Direct Replacement
Direct Replacement
Clairex
Optron
OP1022
OP1032
OP1062
OP1064
JEDEC Registered
Opto-Couplers
Motorola
MOC1001
MOC1000
MOC1002
MOC1003
Replacement
Replacement
Replacement
Replacement
Hewlett Packard
HP 4360
;....
CD
::::I
~
Monsanto
MCT2
MCT2E
MCT26
(/)
(/)
:::tI
Fairchild
FC0810
FC0811
FC0820
a
G')
c:
s::
CD
~
Peripheral/Power Drivers
NAll0NAL
OS161110S36ff, OS1612/0S3612, OS1613/0S3613,
OS1614/0S3614 dual peripheral drivers
general description
features
The DS1611 series of dual peripheral drivers was designed for those applications where a higher breakdown
voltage is required than that provided by the DS75451
series_ The pin outs for the circuits are identical to those
of the DS75451 through DS75454_ The DS1611 series
parts feature high voltage outputs (80" breakdown in
the "OFF" state) as well as high current (300 mA in
the "ON" state). Typical applications include power
drivers, relay drivers; lamp drivers, MaS drivers, and
memory d rivers_
• 300 mA output current capability per driver
connection diagrams
Vee
.,
82
Ai
V2.
81
VI
TOP VIEW
GNU
Order Number DS3611N
• High voltage outputs (BOV)
• TTL or DTL compatible
• Input clamping diodes
• Choice of logic function
(Dual-In-Line and Metal Can Packages)
Vee
82
AZ
Y2
TOPVIEW
Order Number DS3612N
0n!er Number DS3613N
Order Number DS3614N
GND
TOP VIEW
TOP'VI£W
TOP VIEW
PiII4i1inIllKtrialcontlctWltblhecase.
Pin4blnelectricalcoll1ectllriththtClSe.
Pin4isineleC1rialcantllC1Wit/1IbBC8III.
Pin4il;nalewicaltunbctwilhtfla .....
Order Number
DS1612H or DS3612H
Order Number
DS1613H or DS3613H
Order Number
DS1614H or DS3614H
Order Number
DS1611H or DS3611H
TOP VIEW
o
absolute maximum. ratings
(Not!'! 1)
'.
operating conditions
~AX
MIN
Supply Voltage, Vee
Input Voltage
Output Voltage (Note 5)
Continuous Output CUrrent
Continuous Total Power Dissipation (Note 4)
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
Supply Voltage (Vee)
OS161X
OS361X
7.0V
5.5V
BOV
300mA
BOOmW
-65°C to +150o e,
3000 e
Temperature (T A)
OS161X
'OS361X
4.5
4.75
-55
0
..
UNITS
5.5
. '.5.25
V
V
+125
+70
°e
°e
"
electrical characteristics
081611/083611,081612/083612, 081613/083613, 081614/083614 (Notes 2 and 3)
PARAMETER
CONDITIONS
V ,H
High Level Input Voltage
(Figure 1)
V'L
low Level Input Voltage
(Figure 2)
V,
Input Clamp Voltage
Vee
VOL
low Level Output Voltage
= Min',
I, =:-12 mA.(Figure3)
OS1611. V'L = O.BV·
OS1613, V,L =O.BV
Vee = Min,(Figure 1)
OS1614, V,H =2V
0S3611, V'L =O.BV
OS3612, V,H =2V
OS3613, V'L =O.BV
OS3614,V H=2V
'
Input Current at Maximum
Vee
= Max,
"
'. leiL
= 100 mA
MAX
~
.
UNITS
V
O.B
V
,-1.2
-1.5
V
0.2
0.5
V
O.B
V
"
10L = 300 m'A
0.45
16L = 100 mA
0.2
0.5
V
10L = 300 mA
0.45
O.B
V
10L = 100 mA
0.2
0.5
V
10L = 300 mA
0.45
O.B
V
10L - 100 mA
0.2
0.5
V
10L = 300 mA
0.45
O.B
V
10L = 100 mA
0.2
0.4
V
IOL == 300 mA
0.45
0.7
V
10L = 100mA
0.2
0.4
V
10L = 300 mA
0.45
0.7
V
10L = 100 mA
0.2
0.4
V
10L = 300mA
0.45
0.7
V
10L ~ 100 mA
0.2
0.4
V
IOL=300 rnA
0.45.
0.7
V
= 2V,
OSI61T,
10f! = 300 J.lA
OSi613
V ,H - 2V,
053611,
V ,H
Output Breakdown Voltage
Vee = Min.lFigure 1)
I,
TYP
2
OS1612, V,H =2V
V OH
MIN
10H = 100J.lA
0S3613
V'L - O.BV,
OS1612,
10H = 300 J.lA
OS1614
V'L - O.BV,
0S3612,
10H = 100J.lA
0S3614
BO
V
BO
V
BO
V
BO
V
1
V I = 5.5V, (Figure 2)
mA
Input Voltage
I'H
High Level Input Current
Vee = l\I)ax, V, = 2.4V, (Figure 2)
I'L
Low Level Input Current
Vee = Max, V, = O.4V, (Figure 3)
ICCH
Supply Current
-1
OSI.611/
V, = 5V
OS3611
OS1613/
0S3613
Vee = Max, Outputs
OS1612/
. High, (Figures 4 and 5)
V, = OV
OS3612
OS1614/
OS3614
leeL
Sl:Ipply Cur~ent
0S3611
11
mA
14
mA
14
rnA
~7
mA
69
mA
73
mA
71
mA
79
mA
OS1613/
Vee == Max, Outputs
0S3613
Low, (figures 4 and 5)
OS1612/
OS3612
V, = 5V
OS1614/
OS3614
1·2
J.lA
mA
OS1611/
V, = OV
\
40
-1,6
C
switching characteristics
en
....
Vee ~ 5.0V, T A ~ 25°c
.......
CJ')
OS1611/0S3611, OS1612/0S3612, OS1613/0S3613, OS1614/0S3614
........
C
PARAMETER
tpD1
CONOITIONS
Propagation Delay Time,
Low~To-High
MIN
TYP
MAX
UNITS
053611
CJ')
130
ns
110
ns
en
CD
125
ns
(II
220
ns
125
ns
110
ns
125
ns
150
ns
051612/
10
~
200mA. C L = 15 pF. RL
= 50n,
053612
...
OS1613/
(Figure 6)
OS3613
W
...
051611/
Level Output
(f)
CD'
OS1614/
OS3614
tpDO
Propagation Delay Time,
OS1611/
High-To-Low Level Output
OS3611
OS1612/
10
~
200 mAo CL
= 15 pF,
RL
= 50n.
(Figure 6)
OS3612
OS1613/
OS3613
OS1614/
OS3614
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless othelWise specified minimax limits apply across the O°C to +70°C temperature range for the DS3611, 083612, 083613, 083614,
and _55°C to +125°C temperature range for the 051611, D51612, 051613 and 051614. All typical values are for TA ~ 25°e and Vce = 5V.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
Note 4: Maximum junction temperature is 150°C. For operating at elevated temperatures, the package must be derated based on a thermal res istance,8JA, of 110°C/W.
D
Note 5: Maximum voltage to be applied to either output in the "OFF" state.
Note 6: Delay is measured with a son load to 1 av, 15 pF load capacitance, measured from 1.SV input to 50% point on output.
1-3
CIl
.S!
...
~
schematic diagrams
~
M
(each driver)
0536,11 Dual AN 0 Peripheral Drive'
en
---------o v"
C
r - - -...- - _ 4...
.......
~
U;
C
Note: 1/2 of unit shown.
OS3612 Dual ,,!AND Peripheral Driver
r---_4.---_4...- -...-------------0v,'
~_4t_-----_4t_----_4t_----~---t_--~---.--~GND
Note: 1/2 of unit shown.
083613 Dual OR Peripheral Driver
...
r - - - - - _ 4...--~--4
-------~)V"
L---~----------------~--_4~_4~~~~~~OGND
Note: 11Z of unit shown.
'·4
c
C/)
~
en
schematic diagrams (con't)
::::
........
DS3614 Dual NOR Peripheral Driver
c
C/)
~-----e------~-----------e--~~------~---------o~,
w
~.
C/)
CD
...
til'
1/1
L---~~---'------------~-----'
__
~~
__-4__
~~--~---oGNO
Note: 1/2 of unit shown.
test circuits
INPUT
UNDER
TEST
OTHER
INPUT
053611
V'H
V"
OS3612
D53613
CIRCUIT
SEE
V'H
TEST
8ff
TA.LE,
-4---
VOH
'OH
. ~Ioe
Vee
D53614
OUTPUT
APPLY
MEASURE
V'H
Vee
'OH
'oe
V OH
V'H
V"
V'H
Vee
10L
10H
VOL
V OH
V'H
V"
GND
10H
V"
'oe
V OH
Voe
GND
10L
10H
Voe
V OH
V'H
V"
V"
VOL
D
NOTE: Each input is tested separately .
•.• ..-....L_.,
4.5V
CIRCUIT
UNDER
TEST
OPEN
OPEN
Eath input is tested separately.
FIGURE 2.11.IIH
v,
Both gamsare tested simultaneously,
FIGURE 4. ICCH. ICCL for AND. NAND Circuits
Note 1: Each input is tested separately.
Note 2: When testing D83613 and 083614 input not under test is grounded. For. all
othar circuits it is at4.5V.
FIGURE 3. VI. IlL
V,
Both gates are tested simultaneous!y.
FIGURE 5. ICCH. ICCL for OR. NOR Circuits
1·5
.~...
~
test circuit and switching time waveforms
:::CD
INPUT
2.4V
('I)
,L,
Q
OS3611
053612
en
Vee n5V
OUTPUT
~
....enCD
c
INPUT
g~:~~
I
~~:r"'"'
1.5V!,
I
~.'~"~
I ) ~.:1O"'
k(H.
__________________
s; S.O n~
1.5V
-2'~'%
,v
---O.5J.JS'-~----~
---j
J.OV
'''' I
INPUT
OSl612
0$3614
,-,,",,-'-----,v
DUTPUT
Nutu I: The pwlse genelator hIlS the lollowina th.r.o:ttrinies: PRR = 1.0 MHz, ZOUT "" son.
Nota2;C L im:Jlldesprobe8ndjigl3pacitnncu.
FIGURE 6. Switching Times of Complete Drivers
~
Peripheral/Power Drivers
...cenen
w
...
"cen
NAll0NAL
w
en
DS16311DS3631, DS1632/DS3632, DS1633/DS3633, DS1634/DS3634
CMOS dual peripheral drivers
...
w
en
CD
general description
~.
The OS1631 series of dual peripheral drivers was
designed to be a universal set of interface components
for CMOS circuits.
high impedance OFF state with the same breakdown
levels as when Vee was applied.
Pin-outs are the same as the respective logic functions
found in the following popular series of circuits·;
OS75451, OS75461, OS3611. This feature allows direct
conversion of present systems to the OM74C CMOS
family and OS1631 series circuits with great power
savings.
Each circuit has CMOS compatible inputs with thresholds
that track as a function of Vcc (approximately 1/2 Vee).
The inputs are PNPs providing the high impedance
necessary for interfacing with CMOS.
Outputs have high voltage capability, minimum breakdown voltage is 56V at 250,uA.
The OS1631 series is also TTL/OTL compatible at
Vee = 5V.
The outputs are Oarlington connected transistors. This
allows high current operation (300 mA max) at low
internal Vee current levels since base drive for the
output transistor is obtained from the load in proportion to the required loading conditions. This is essential
in order to minimize loading on the CMOS logic supply.
features
• CMOS compatible inputs
• TTL/OTL compatible inputs
PNP's
• High impedance inputs
56V min
• High output voltage breakdown
300 mA max
• High output current capability
• Same pin-outs and logic functions as OS75451,
OS75461 and OS3611 series circuits
Typical Vee = 5V power is 28 mW with both outputs
ON. Vee operating range is 4.5V to 15V.
The circuit also features output transistor protection if
the Vee supply is lost by forcing the output into the
schematic diagram
•
Low Vee power dissipation (28 mW both outputs
"ON" at5V)
(Equivalent Circuit)
r - -....- - - - - - - - 4 r - -....~ v"
INPUT
OUTPUT
lOGIC
'I
AND LEVEL
TRANSLATION
ELEMENTS
CD
IJI
I
L __ -'
1/2 of circuit shown
GND
SEE CONNECTION DIAGRAMS FOR ORDERING INFORMATION
1-7
II
-absolute maximum ratings
operating conditions
(Note 1)
MIN
Supply Voltage
Voltage at Inputs
Output Voltage
16V
-{).3V to V CC +0_3V
56V
-6SoC to +150°C
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
300°C
Supply Voltage, Vcc
OS163110S16321
OS163310S1634
OS363110S36321
OS363310S3634
Temperature, T A
OS 1631/0S 16321
OS1633/0S1634
053631/0536321
t
MAX
UNITS
4.5
15
V
4.75
15
V
-55
+·125
°C
0
+70
°c
053633/053634
electrical characteristics
(Notes 2 and 3)
PARAMETER
CONOITIONS
MIN
TYP
MAX
UNITS
All Circuits
V IH
Logical "I" Input Voltage
(Figure 1)
VIL
Logical "0" Input Voltage
(Figure 1)
IIH
Logical "1" Input Current
IlL
Logical "0" Input Current
Vee = 5V
3-5
2.5
V
Vee = 10V
8.0
Vee = 15V
12.5
5
7_5
V
V
Vee = 5V
2.5
1.5
Vee = 10V
5.5
2.0
V
Vee = 15V
7.5
2.5
V
Vee = lSV, VIN = lSV, (Figure2)
VIN = O.4V, (Figure 3) Vee = 6V
Vee = 15V
V OH
Output Breakdown Voltage
Vee = 15V, 10H = 250p.A, (Figure 7)
VOL
Output Low Voltage
.110L = 100 rnA
Vee = Min, (Figure 1)
10L = 300 rnA
0.1
p.A
-50
p.A
200
56
V
65
p.A
V
0.9
V
1.1
V
051631/053631
'cc(a)
Supply Currents
lee(l)
Vee = 5V
Output Low
7
rnA
Vee = 15V
Both Drivers
14
rnA
Vee = 5V, VIN = 5V
OutPut High
2
rnA
7_5
rnA
Vee = 5.0V, TA = 25°C, CL = 15 pF, RL =.50n, V L = lOV.
(Figure 5)
200
ns
Vee = 5.0V, T A = 2Soc, CL = 15pF, RL = son, V L = 10V,
150
ns
VIN = OV, (Figure 4)
(Figure 4)
tpd1
Propagation to "1"
tpdO
Propagation to "0"
Vee = 15V, VIN = 15V 80th Drivers
(Figure 5)
OS 1632/053632
'CC(O)
Supply Currents
'cem
tpdl
(Figure 4)
VIN = OV, (Figure 4)
Propagation to "1"
Vee = 5V, VIN = 5V
Vee ~ _15V, VIN = 15V
Vee = 5V
Vee - 15V
Output Low
Output High
Vee = 5.DV, TA = 25°C, CL = 15 pF, RL = son, V L = 10V,
8
mA
18
mA
2.5
mA
9
rnA
150
ns
150
ns
(Figure 5)
tpdO
Propagation to "0"
Vee = S.OV, TA = 25°C, CL = 15 pF, RL = 50n, V L = 10V,
(Figure 5)
051633/053633
'CC(C)
Supply Currents
leCfl)
VIN = OV, (Figure 4)
(Figure 4)
tpdl
Propagation to "1"
tpdO
Propagatioh to "0"
Vee =5V, VIN = 5V
V ce =15V,V IN =15V
Output Low
Output High
7_5
mA
16
rnA
2
rnA
7.2
rnA
Vee = S.OV, TA = 2SoC, CL = 15 pF, RL = son, V L = 10V,
(Figure5)
200
ns
Vee = S.OV, TA = 2SoC, CL = 15 pF, RL = 50n, V L = 10V,
150
ns
(Figure5)
1·8
Vee = 5V
Vee = 15V
c
en
.en
electrical characteristics (con't)
PARAMETER
CONOITIONS
MIN
TYP
MAX
UNITS
IcC(o)
Supply Currents
I CC (1)
tpd1
Vee = 5V, V ,N ~ 5V
(Figure 4)
Vee = 15V, V ,N = 15V
V ,N = OV, (Figure 4)
Propagation to "1"
w
~
c
OS1634/0S3634
Vee = 5V
Output Low
Output High
Vee - 15V
Vee = 5.0V, TA = 25°C, CL = 15pF, RL = 50Q, V L =10V,
7.5
rnA
18
rnA
3
rnA
11
rnA
150
ns
150
ns
en
w
en
w
.-
(Figure 5)
tpdO
Propagati on to "0"
Vee = 5.0V, T A = 25°C, C L = 15 pF, RL = 50Q, V L = 10V,
(Figure 5)
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified minimax limits apply across the -55°C
to
+125°C temperature range for the D51631, D51632, DS1633 and
051634 and across the O°C to +70°C range for the 053631, 053632, 053633 and D53634. All typical values are for T A = 25°C,
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
test circuits
S.
v~
V
I
IH
Lr -r-.---'--- r
0--
SEE
TEST
TABLE
V1Lo--
~
CIRCUIT
UNDER
TEST
y
~
VOH
SEE
TEST
TABLE
D
~IOL
L-
Vo,
INPUT
UNOER
TEST
CIRCUIT
LM3611
APPLY
MEASURE
V,H
Vee
10H
10L
V OH
VOL
V'L
V ,H
Vee
10L
10H
VOL
V OH
V ,H
GND
V'L
V'L
10H
10L
V OH
VOL
V,H
GND
V'L
V'L
10L
10H
VOL
V OH
V,H
LM3612
V,H
LM3613
LM3614
IS
OUTPUT
OTHER
INPUT
V'L
Note: Each input
!f
':'
':'
tested separately.
FIGURE 1. VIH, VIL, VOH, VOL
-
I,"
V,"
vee
A, •
.,A
~
CIRCUIT
UNDER
TEST
V
r- OPEN
':'
Each input is tested separatelv.
FIGURE 2. IIH
,
1-9
m
'r:;
CI)
test circuits (con't) and switching time waveforms
CI)
M
CD
M
, Vee
CI)
C
~
A,B . - - ' - - ,
Vee
M
OPEN
(j)
....
en
c
Both gates a;e tested simultaneously.
Note A: Each rnput is tested separlltely.
Note 8: When testing 081633 and 081634 input not under test is grounded. For all
other circuits it is at Vee.
FIGURE 3.lll
FIGURE 4. ICC
INPUT
S.OV
10V
.1.
051631
001632
Vee =5V
",-"",-0 OUTPUT
PULSE
GENERATOR
(NOTE 1)
GND
DS16JJ
081634
~
OV
s.nv
INPUT
OS1631
031633
1 - - - - - - - - 0..,..----·----___o-1
::;;5.005
5.ov--H,.-:;;:::;-------------=~
INPUT
081632
081634
BV
VOH
----....,.,'"
OUTPUT
VO,------~_f~~-----------------~
Note 1: The pulse generator has the following characteristics: PRR '" 500 kHz, lOUT"'" 50n.
Note2: Cl inciudes probe and jig capacitance.
F:GURE 5. Switching Times.
1·10
g
connection diagrams. truth tables and ordering information
OS1~31
-"
en
w
OS1632
Metal Can Package
Metal Can Package
-"
.......
c
en
w
Vee
Vee
en
w
-"
en
CD
...
A1
GNO
GNO
TOP VIEW
TOPVIEW
(Pm4is electrically connected to the case.)
(Pin4iselectricallvconnect1ldtothecase.!
Order Number OS1631H/OS3631H
Order Number OS1632H/OS3632H
DualRln-Line Package
B1
Vee
ii'
Dual-tn-Line Package
X1
A1
B1
A1
X1
o
TOPVIEW
TOPVIEW
Order Number 3631N
Order Number OS3632N
Dual-I n-line Package
Vee
B1
NC
A1
B1
NC
NC
NC
Nt
NC
Dual-I n-Line Package
A1
X1
Vee
B1
NC
X1
GNO
A1
B1
NC
TOPVIEW
NC
NC
A1
X1
NC
NC
X1
GNO
TOP VIEW
Order Number OS1631J/OS3631J
Order Number OSI632J/OS3632J
Positive logic' AB=X
Positive logic' AB=X
A
>8
OUTPUT X
A
B
0
0
0
0
0
i
1
0
0
1
0
1
0
1
0
0
1
1
1
1
1
1
1
0
OUTPUT X
1-11
connection diagrams. truth tables and ordering information
OS1633
051634
Metal Can Package
Metal Can Package
Vee
Vee
GND
TOPVIEW
TOP VIEW
GND
(Pin 4 is electrically connected to the CilSe.)
(Pin4iselectricaUyconnettedtothecase.l
Order NumberOS·1633H/OS3633H
Dual~1 n~line
Order Number OS 1634H/053634H
Dual-I n-Line Package
Package
Vee
BZ
AZ
XZ
Vee
B2
.2
XZ
Al
B1
Xl
GND
Al
B1
Xl
GND
TOP VIEW
TOPVIEW
Order Number OS3633N
Order Number DS3634N .
DuaHn-Line' Package
Al
Ne
B1
Dual-In-line Package
Ne
Ne
Xl
GND'
Vee
B2
Ne
Al
B1
NO
TOP VJ~W
Ne
AZ
X2
Ne
Ne
Xl
GND
TOP VIEW
Order Number OSI633J/OS3633J
Order Number OS1634J/OS3634J
Positive logic:
"A+S:=; X
A
B
OUTPUT X
A
B
OUTPUT X
0
0
0
0
0
1
1
0
1
1
0
a
0
1
1
0
1
0
1
1
1
1
1
D
Positive logic' A + B :=
1·12
Ne
X
~
Peripheral/Power Drivers
NAll0NAL
DS1686/DS3686 positive voltage relay driver
Jleneral description
The DS1686/DS3686 is a high voltage/current positive
voltage relay driver having many features not available
in present relay drivers.
PNP inputs provide both TTL/DTL compatibility and
high input impedance for low input loading.
Output leakage is specified over temperature at an out·
put voltage of 54V. Minimum output breakdown (ac/
latch breakdown) is specified over temperature at 5 mAo
This clearly defines the actual breakdown of the device
since the circuit has incorporated in it an internal
reference which does not allow output breakdown
latching found in existing relay drivers. Additionally,
this internal reference circuit feature will eliminate the
need in most cases of an external clamping (inductive
transient voltage protection) diode. When the output is
turned "OFF" by input logic conditions the resulting
inductive voltage transient seen at the output is detected
by an internal zener reference. The reference then
momentarily activates the output transistor long enough
so that the relay energy is discharged. This feature
eliminates the need of external circuit protection components and insures output transistor protection.
The outputs are Darlington connected transistors, which
allow high current operation at low internal Vee
current levels-base drive for the output transistor is
obtained from the load in proportion to the required
loading conditions. Typical Vee power with both
outputs ON is 90 mW.
The circuit also features output transistor protection if
the Vee supply is lost by forcing the output into the
high impedance OFF state with the same breakdown
levels as when Vee was applied.
features
• TTL/DTL/CMOS compatible inputs
• High impedance inputs (PNP's)
• High output voltage breakdown (65V typ)
• High output current capability (300 mA max)
• Internal protection circuit eliminates need for output
protection diode in most applications
• Output breakdown protection if Vee supply is lost
• Low Vee power dissipation (90 mW (typ) both
-outputs "ON")
•
Voltage and current levels compatible for use in
telephone relay applications
connection diagrams
Metal Can Package
Dual-I n-Line Package
TOP VIEW
Pill4isinele~trical
Dual-In-Line Package
A1
COlltact with the case
Order Number DS1686H or DS3686H
B1
NC
TOP VIEW
Order Number DS3686N
schematic diagram
Order Number DSl686J or DS3686J
truth table
Positive logic: AB
r--,-~~-oDUTPUT
INPUT A
ZENER
INPUT 8 0 - - + - - I
EQUIVALENT
L-_'--.....- .....- - -.....-oGND
~
X
A
B
OUTPUT X
a
a
a
1
1
a
1
1
1
1
a
1
Logic "0" output "ON"
Logic "1" output "OFF"
1·13
o
CD
CO
CD
absolute maximum ratings
operating conditions
(Note 1)
('t)
C/)
Q
......
CD
CO
....C/)
CD
Q
Supply Voltage
7V
15V
56V
-65°C to +150°C
300°C
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
electrical \cha racteristics
Supply Voltage, V CC
DSl686
DS3686
4.5
4.75
5.5
5.25
V
V
-55
0
DS1686
DS3686
MIN
CONDITIONS
°c
°c
+125
+70
TYP
MAX
UNITS
2.0
Logical "1" Input Curre~t
'CC(O)
UNITS
(Notes 2 and 3)
PARAMETER
Veo
MAX
Temperature, T A
Logical "1" Input Voltage
V'L
MIN
Vee = Max, V ,N = 5.5V
V
1
Logical "0" Input Voltage
/.LA
0.8
Logical "0" Input Current
Vee:= Max, V!N
=:
-150
DAV
Input Clamp Voltage
Vee
= SV,
Output Breakdown
Vee
= Max,
V ,N
= OV,
lOUT
= 5 rnA
Output Leakage
Vee
= Max,
V ,N
= OV,
V OUT
= 54V
Output "ON" Voltage
.lloUT = 100mA
.
Vee = Min, V ,N = 2V IloUT _ 300 mA
0.9
1.1
V
Supply Current (Both Dri,vers)
Vee == Max, VIN = OV, Outputs Open
2.0
mA
Supply Current (Both Drivers)
Vee"" Max,
18.0
mA
Propagation Delay to a Logical "0"
C L ~ 15 pF, V L
(Output Turn "ON")
T A = 2SoC, Vee
Propagation Delay to a Logical "1"
CL
=
(Out1'ut Turn "OFF")
TA
= 25°C,
leLAMP
VIN ==
15 pF, V L
Vee
= -12 mA, T A = 25°C
V
/lA
-1.0
V
65
V
2
3V, Out'puts Open
/lA
V
= 10V,
= 5.0V
RL
= 50n,
100
ns
= 10V,
RL
= 50n,
500
ns
= 5.0V
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot ·be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. Th~ table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the -55°C to +125°C temperature range for the 081686 and across the oDe to
+70°C range for the DS3686. All typicals are given for VCC = 5.0V and T A = 25°C.
Note 3: All currents into device pins shown as positive, out of device pins'as
values shown as max or min on absolute value basis.
n~gative,_
all voltages referenced to grou'nd u,nless otherwise noted. All
ac test circuit and switching time waveforms
.""~:oo
JV
INPUT
GIRGUlT
UNDER
TEST
- ' - C,015,F
TINOTE21
Notel: The pulse generator has the following characteristics:
PR R '" 1 MHz, 50% duty cycle, ZOUT ::: 50n, t, '" tf ~ 10 ns.
Note 2: GL includes probe and jig capacitance.
Vo,
1-14
~1.5V
~~r
\
1'----f
~
Peripheral/Power Drivers
NAnONAL
051687/053687 negative voltage relay driver
general description
The D51687/D53687 is a high voltage/current negative
voltage relay driver having many features not available
in present relay drivers.
allow high current operation at low internal Vee
current levels-base drive for the output transistor is
obtained from the load in proportion to the required
loading conditions. Typical Vee power with both
outputs ON is 90 mW.
PNP inputs provide both TTL/DTL compatibility and
high input impedance for low input loading.
The circuit also features output transistor protection if
the Vee supply is lost by forcing the output into the
high impedance OFF state with the same breakdown
levels as when Vee was applied.
Output leakage is specified over temperature at an out·
put voltage of --54V. Minimum output breakdown (ac/
latch breakdown) is specified over temperature at -5 mAo
This clearly define~ the actual breakdown of the device
since the circuit has incorporated in it an internal
reference which does not allow output breakdown
latching found in existing relay drivers. Additionally,
this internal reference circuit feature will el iminate the
need in most cases of an external clamping (inductive
transient voltage protection) diode. When the output is
turned "OFF" by input logic conditions the reSUlting
inductive voltage transient seen at the output is detected
by an internal zener reference. The reference then
momentarily activates the output transistor long enough
so that the relay energy is disCharged. This feature
eliminates the need of external circuit protection components and insures output transistor protection.
features
• TTL/DTL/CM05 compatible inputs
• High impedance inputs (PNP's)
• High output voltage breakdown (-65V typ)
• High output current capability (300 mA max)
• Internal protection circuit eliminates need for output
protection diode in most applications
• Output breakdown protection if Vee supply is lost
• Low Vee power dissipation (90 mW (typ) both
outputs "ON")
• Voltage and current levels compatible for use in
telephone relay applications
The outputs are Darlington connected transistors, which
connection diagrams
Dual-In-Line Package
Dual-In-Line Package
Metal Can Package
GND
TOP VIEW
Pin 4 is in electrical contact with th~ case
Order Number DS1687H
or DS3687H
Vee
B2
A2.
xz
A1
Bt
Xl
GND
A1
NC
B1
NC
Nt
TOP VIEW
TOP VIEW
Order Number DS3687N
Order Number DS1687J
or DS3687J
schematic diagram
"
GND
truth table
r---~------------~V~
Positive logic' AB = X
INPUT A
INPUTS
'--4----"1---+--..--..-<> GND
A
B
OUTPUT X
0
1
1
0
0
0
1
1
1
1
0
1
Logic "0" output "ON"
Logic "1" output l'OFF"
' -__......______~.., OUTPUT
1·15
o
r--
00
CD
(W)
(f)
C
r:::
00
...
CD
absolute maximum ratings
Supply Voltage
Inpl:lt Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
,
(f)
operating conditions
(Note ;1)
7V
15V
-56V
-65°C to+150°C
300°C
Supply Voltage, VCC
DS1687
DS3687
MIN
MAX
UNITS
4,5
4.75
5.5
5.25
V
V
Temperature, T A
electrical characteristics
+125
+70
°c
°c
MAX
UNITS
-55
0
DS1687
DS3687
C
(Notes2 and 3)
CONDITIONS
PARAMETER
MIN
TYP
V ,H
Logical "1" Input Voltage
l,tH
Logical "1" Input Curr~nt
2.0
V'L
Logical "0" Input Voltage
I'L
Logical "0" Input Current
Vee = Max, \I,'N = OAV
-150
V eD
Input Clamp Voltage
Vee = 5V, leLAMP = -12 rnA, TA = 25°C
-1.0
V
V OH
Output.Breakdown
Vee
-£5
V
IOH
Output Leakage
Vee = Max, Y'N ~ OV, V OUT =-54V
VOL
Output "ON" Voltage
Vee
=
!J.A
0.8
= Max,
Y'N = OV,
Vee = Min, Y'N = 2V
=-5 rnA
lOUT
I
I
'ee(1)
Supply Current (Both Drivers)
lee(o)
Supply Current (Both Drivers)
Vee
tpd(ONJ
Propagation Delay 'to a Logical "0"
CL
(Output TUm "ON")
TA = 25°C, Vee = 5.0V
Propagation Delay to a Logical "1"
CL
(Output Turn "OFF")
TA = 25°C, Vee = 5.0V
tpd(OFFJ
V
1.0
Max, Y'N = 5.5V
!J.A
-2
!J.A
lOUT = -100 rnA
-{J.g
aoo rnA
1.1
V
2.0
mA
18.0
mA
lOUT =
Vee = Max, Y'N = OV, OutPuts Open
= Max,
V
Y'N = 3V, Outputs Open
= 15 pF, V L = -10V, RL
= 50n,
= 15 pF, V L = -10V, RL = 50n,
V
100
ns
500
ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for 'actual d,evice operation:
NOJe 2: Unless otherwise specified minimax Ii~its apply across the -55°C to+125°C'temperature range for the DS1687 and acr,oss the O°C to
+70°C range for the DS3687. All typicals are given for VCC
= 5.0V and TA = 25°C.
.
Note 3: All_currents into device pins shown as positive, out of device pins'as negative,
values shown as max or min on absolute value basis.
an voltages referenced to ground unless otherwise noted. All
ac test circuit and switching time waveforms
'v
INPUT
CIRCUIT
UNDER
TEST
Note t: The pulse generator has the following charac~ristics:
PRR" 1 MHz, 50% dUly cyele, ZOUT '" son, I," tl <;; 10 ns.
Note 2: CL includes prnbe and jig capacilance.
1-.16
r------------~
~5V
-L"r~t
15V\......_ _ __
c
~
Peripheral/Power Drivers
CJ)
(J'I
(J'I
~
(J'I
o
"c
NATlONAL
CJ)
0555450/0575450 series dual peripheral drivers
'oJ
(J'I
general description
~
(J'I
The OS55450lOS75450 series of dual peripheral drivers
are a family of versatile devices designed for use in
systems that use TTL or OTL logic. Typical applications
include high speed logic buffers, power drivers, relay
drivers, lamp drivers, MOS drivers, bus drivers and
memory drivers.
The OS55450/0S75450series are unique general purpose
devices each featuring two standard Series 54/74 TTL
gates and two uncommitted, high current, high voltage
NPN transistors. These devices offer the system designer
the flexibility of tailoring the circuit to the application.
The OS55451 /OS75451, OS55452/0S75452, DS55453/
DS75453 and DS55454/0S75454 are dual peripheral
connection diagrams
AND, NAND, OR and NOR drivers, respectively, (positive logic) with the output of the logic gates internally
connected to the bases ot the I~PN output transistors.
o
features
III
•
300 mA output current capability
•
High voltage outputs
•
•
•
•
No o~tPut latch-up at 20V
High speed switch i ng
Choice of logic function
TTL or DTL compatible diode-clamped inputs
•
Standard supply voltages
•
Replaces TI "A" and "B" series
CJ)
CD
::I.
CD
(Dual In-Line and Metal Can Packages)
D
TOPVIEW
Order Number
DS55450J, DS75450J, or DS75450N
V~C
Vee
Bl
VI
TOPVIEW
Order Number·DS75451N
Order Number DS75452N
Order Number DS75453N
Gruo
GNO
T!H'VIEW
Pln4i,inelectricafcorrtactwLthtne<:ase.
Order Number
OS55451H or DS75451H
Order Number DS75454N
TOP VIEW
TOPVIEW
Pin41,ineleGtricalconnctwithlhecal".
Order Number
DS55452H or DS75452H
Pin41SHIelectricai Cijntai:twithtnec,se.
Pin41!mel€ctricalr.ontactwiththecDSIl
Order Number
Order Number
DS55453H or DS75453H
DS55454H or DS75454H
1-17
absolute maximum ratings
Collector~to-Substrate-
operating conditions
(Note 1)
Supply Voltage, (Vee) (Note 2)
Input Voltage
Inter-emitter Voltage (Note 3)
VCC·to-Substrate Voltage
0555450/0575450
7.0V
5.5V
5.5V
Supply Voltage,(Vccl
055545X
057545X
35V
Voltage
05511450/0575450
Temperature, (T A)
055545X
057545X
35V
Collector-Base Voltage
0555450/0575450
Voltage (Note 4)
0555450/0575450
.
(Note 7),
MIN
MAx
4.5
4.75
5.5
5.25
V
V
+125
+70
°c
°c
--55
0
. UNITS
35V
ColI'~etor·Emitter
30V
Emitter-Base Voltage
5.0V
0555450/0575450
Output Voltage (Note 5)
,
0555451/0$75451, 0555452/0575452,
0555453/0$75453, 0555454/0575454
Coil ector Current (Note 6)
0555450/0575450
Output Current (Note 6)
0555451/0575451, 0555452/0575452,
0555453/0575453, 0555454/0575454
Continuous Total Dissipation
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
30V
300mA
300mA
800mW
--55°C to +150°C
260°C
dc electrical characteristics
DS55450/DS75450 (Notes 8 and 9)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
TTL GATES
V'H
High Level Input Voltage
(Figure 1)
V'L
Low Level Input Voltage
(Figure 2)
V,
Input Clamp Voltage
Vee = Min, I, = -12 mA, (Figure 3)
V OH
High Level Output Voltage
Vee = Min, V'L=O.8V, IOH=-400MA, (Figure2J
VOL
Low Level Output Voltage
Vee = Min,
I,
Input ClIrrent at Maximum Input
High Level Input Current
2.4
0.8
V
-1.5
V
0.5
0.4
V
V
3.3
(Figure 1)
Vee = Max, VI = 5.5V, (Figure4)
Input A
1
Input G
2
rnA
rnA
Input A
40
IlA
Input G
80
IlA
Input A
-1.6
3.2
rnA
rnA
2V, IOl = 16 rnA
Vee = Max, VI"" 2.4V, (Figure 4)
0.22
0.22
V
0555450
0575450
V!H =
Voltage
I'H
V
2
'.
I'L
Low Level Input Current
Vee = Max, VI = O.4V, (Figure 3)
los
Short Circuit Output Current
Vee = Max, (Figure 5), (Note 101
-,55
rnA
lecH
Supply Current
V cc = Max" V! = OV, Outputs High, (Figure 6)
2
4
rnA
IceL
Supply Current
Vee:= Max, VI = 5V, Outputs Low, (Figure6)
6
11
rnA
Input G
-18
OUTPUT TRANSISTORS
V(BA)CBO
Collector-Base Breakdown Voltage
I," 1001lA. IE"" 0
35
V
V(BR)CER
Collector-Emitter Breakdown
Ie'" 1001lA, R8E =500n
30
V
Voltage
V(BRlEBO
Emitter-Base Breakdown Voltage
hF •
Static Forward Current Transfer
0555450, T A = +25°C
Ratio
OS55450, T A = -55°C
VeE =3V. (Note 111
0575450, T A = +25°C
0575450, T A = DoC
V 8E
Base-Emitter Voltage
0555450
(Note 111
0575450
VCE(SAT)
Collector·Emitter Saturation
Voltage
OS55450
(Note 111
OS75450
1-18
5
V
Ie = 100 mA
Ie = 3pO mA
25
30
V
V
le=l00mA
Ie = 300 mA
Ie - 100 mA
Ie = 300 mA
10
15
25
30
le=100mA
Ie = 300 mA
20
25
V
V
V
V
V
V
IE" 1001lA, Ie = 0
= 100 mAo
= 300 mA
= 100mA
- 300 mA
0.85
1.05
0.85
1.05
1.2
1.4
1
1.2
V
V
V
V
18 = 10mA, I, = 100mA
0.25
0.5
0.25
0.5
0.5
0.8
V
V
0.4
0.7
V
V
I. = 10 mAo
18 = 30 mA,
18 = 10mA,
18 30 mA,
I,
Ie
Ie
Ie
18 =30mA, Ie -300mA
18 - 10 rnA, Ie = 100 mA
18 =30mA, Ie = 300 mA
\
c
en
U1
dc electrical characteristics (con't)
U1
0555451/0875451,0855452/0875452, 0855453/0875453, 0855454/0875454 (Notes 8 and 9)
~
U1
PARAMETER
V ,H
High-Level Input Voltage
V'L
Low-Level Input Voltage
V,
Input Clamp Voltage
VOL
Low-Level Output Voltage
MIN
CONDITIONS
TYP
MAX
2
UNITS
V
(Figure 7)
V'L = 0.8V
10L = 300 mA
Vee = Min,
(Figure 7)
10L = 100 rnA
V 1H
:=
2V
10L = 300 rnA
10H
High-Level Output Current
Vee
V OH = 30V
V'L = 0.8V
I,
Input Current at Maximum Input Voltage
Vee
= Max,
V
0.5
V
0575451, D575453
0.25
0.4
V
I'H
High- Level I nput Current
Vee:= Max, V, =2.4V, (Figure 9)
Low-Level Input Current
Vee
= Max,
ICCH
Supply Current, Outputs High
Vee
= Max,
(Figure 10)
Supply Current, Outputs Low
Vee
= Max,
(Figure 10)
0555451, 0555453
0.5
0.8
V
0575451, 0575453
0.5
0.7
V
D555452, 0555454
0.25
0.5
V
0575452, 0575454
0.25
0.4
V
0555452, D555454
0.5
0.8
V
0575452, D575454
0.5
0.7
V
300
IlA
0575451, 0575453
100
IlA
0555452, 0555454
300
IlA
0575452, 0575454
100
IlA
1
rnA
V, = 5.5V, (Figure 9)
I'L
leeL
-1.5
0.25
0555451, D555453
V 1H = 2V
= Min,
(Figure 7)
V
0555451. 0555453
Vee"" Min, 1,=-12mA
IOL = 100 rnA
0.8
-1
V, = O.4V, (Figure 8)
40
IlA
-1.6
rnA
V, = 5V
D555451i0575451
7
11
rnA
V, -OV
D555452iOS75452
11
14
rnA
V, = 5V
D555453iOS75453
8
11
rnA
V,=OV
D555454iOS75454
13
17
rnA
V, = OV
DS55451iDS75451
52
65
mA
V, - 5V
D555452iOS75452
56
71
mA
V, - OV
D555453i0575453
54
68
rnA
V, - 5V
0555454iDS75454
61
79
mA
TYP
MAX
UNITS
12
22
ns
RL 50n, Ie;:::;; 200 rnA, Gates and Transistors
Combined, (Figure 14)
20
30
ns
RL = 400n, TTL Gates, (Figure 12)
8
15
ns
n,
ac switching characteristics
0855450/0875450 (Vee = 5V, T A = 25°C)
PARAMETER
t pLH
Low-To-High Level Output
tpHL
tTLH
V OH
MIN
RL '" 4000, TTL Gates, (Figure 12)
CL = 15pF
Propagation Delay Time,
High-To-Low Level Output
CL = 15 pF
20
30
Transition Time, Low-To-High
CL = 15pF, RL = 50n, Ie ::>::: 200 mA, Gates and Transistors Combined,
(Figure 14J
7
'12
ns
CL =15pF, RL =50n, Ie ::::: 200 rnA, Gates and Transistors Combined,
(Figure 14)
9
15
ns
Level Output
High-Level Output Voltage After
Vs
Level Output
tTHL
CONDITIONS
Propagation Delay Time,
Transition Time, High-To-Low
=
RL - 50n, Ie::>::: 200 mA, Gates and Transistors
Combined, (Figure 14)
20V, Ie::::: 300 mA, RBE
=
500n, (Figure 15)
mV
Vs-6_5
Switching
to
Delay Time
Ie = 200 rnA, I B (1}
= 20 rnA,
Is
= -40 rnA,
VSE(OFF) - -lV,
8
15
n,
12
20
ns
7
15
ns
6
15
ns
CL = 15 pF, RL = 50n, (Figure 13), INote 12)
tR
Rise Time
ts
Storage Time
Ie = 200 rnA, I S(1) = 20 mA, IB = -40 rnA, VBE(OFF)
CL = 15 pF, RL = 50n, (Figure 13), INote 12)
Fall Time
-lV,
ic =200mA, I BI1 }oo20mA, i B "'-40mA, VBE(OFF}=-lV,
e L = 15 pF,
tF
=
HL = 50n, (Figure 13), INote 12)
Ie = 200 rnA, I B(l) = 20 rnA, Is = -40 rnA, VSE(OFF) = -1V,
CL = 15 pF, RL = 50n; (Figure 13), INote 12)
1-19
~
C
~
U1
~
U1
o
en
CD
:::I.
Il
D
ac switching characteristics (con't)
OS55451/0S75451,OS55452/0S75452,OS55453/0S75453,OS55454/0S75454 (Vee
PARAMETER
Propagation Delay Time, Low-To-High
tPLH
C l . " 15 pF, RL" son,
10 '" 200 mA, (Figure 14)
Level Outpu.,
Propagation Delay Time, High-To-Low
t pHL
CL " 15pF, RL "50n,
Level Output
10
-
Transition Time, Low-To-High Level
tTLH
~
5V,
CONDITIONS
~
200 mA, (Figure 14)
TA ~
25°C)
TYP
MIN
MAX
UNITS
DS55451/DS75451
18
25
ns
OS55452/DS75452
DS55453/DS75453
DS55454/DS15454
26
18
27
35
25
35
ns,
DS55451/DS75451
DS55452/DS75452
DS55453/DS75453
DS55454/DS75454
18
24
16
24
25
35
25
35
ns
ns
os
ns
ns
os
C L =15pF, RL o50n, 10
~
200 mA, (Figure 14)
5
8
os
C L " 15 pF, RL " 50n, 10
~
200 mA, (Figure 14)
7
12
ns
Output
Transition Time, High-To-Low level
tTHL
Output
VOH
Vs -6.5
Vs" 20V, 10 '" 300 mA, (Figure 15)
High-Level Output Voltage After
mV
Switching
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
pr:ovides conditions for actual device operation.
Note 2: Voltage values are with respect to network ground terminal unless otherwise specified.
Note 3: The voltage between two emitters of a multiple-emitter transistor.
Note 4: Value applies when t~e base~emitter resistance (RBE) is equal to or less than 500n.
Note 5: The maximum voltage which should be applied to any output when it is in the "OFF" state.
Not. 6: Both halves of these dual circuits may conduct rated current simultaneously; however, power dissipation averaged over a short time
interval must fall within the continuous dissipation rating.
Note 7: For the 0555450/0575450 only, the substrate (pin 81 must always be at the most~negative device voltage for proper operation.
NoteS: Unless otherwise specified minimax limits apply across the -55°C to +125°C temperature range for the OS55450 series and across the
oOe to +70':C range for the .oS75450 series. All typicals are given for Vee -= +5V and TA = 25°C.
Note 9:. All currents into device pins shown as positive, out of device pins as negative, ail voltages referenced to"ground unless otherwise noted. All
values shown" as max or min on absolute value basis.
Note 10: Only one output at a time should be shorted.
Note 11: These parameters must be measured using pulse techniques. tw = 300MS, duty cycle < 2%.
Note 12: Appl ies to output transistors on Iy.
schematic diagrams
OS55451 10575451
.
v"
~,.
'"
~
--
4k
. tl
Uk
,,.
~~y
Ao---<~7
.r.I'
A'
GO-
1.6k
,
y,
F1
E1
.4~
B1
>--001
AI>
Re~j,Jlor
.... A ..
... ~"
'30
Uk
4k
B2
.....-
E2
~
~
..
~r
,0~
"
GNO
Resistor values shown are nominal.
~
-
.. .
~
u
~ ~.
lk
ResistnrvaluesslluwnarennmlAal.
1·20
~t
V"
.-.r: . . ~Y
.A
!;
~
2.0
~
'"
"
1\
w
~
1.0
'"
-10
~
«
\
100
---
~
...z~
60
«
«
40
~
-20
"
T~C
TA~-
~
TA "O°C-
I--'
u
"«
I
VeE" 3V
(NOTE 81
80
z
w
1\
5
-"
20
~
-30
-40
HIGH·LEVEl OUTPUT CURRENT (mAl
FIGURE 16. OS55450/0S75450 TTL Gate
High-Level Output Voltage vs High-Level
Output Current
;::
"
In
10
20
40
70 100
200
400
COLLECTOR CURRENT (mAl
_FIGURE 17. OS55450/0S75450 Transistor Static
Forward Current Transfer Ratio vs Collector
Current
'-23
1/1
.~
en
o
typical performance characteristics (con't)
~
Il)
1.2
o:t
Ie
Il)
.....
~
en
1.0
(NOTE 8)
w
"~
c
(:)
0.6
~
o:t
Il)
Il)
0.5
....
1!i
F:::::= i\TA =+2SoC
"'
~
D••
;;
~
IB
'" 10
(NOTE 8)
D••
0.3
0.2
"!
~
en
0.6
:>
"z
";::
§
TA-+70°C
0.8
:>
a:
Il)
TA.~
i;"10
'""
:;
:5
0.2
c
10
20
40
70 100
200
0.1
~
o
400
COLLECTOR CURRENT (mAl
FIGURE 18.0555450/0575450 Transistor
Base-Emitter Voltage vs Collector Cur~ent
10
20
40
70 100
200
'00
COLLECTOR CURRENT (mA)
FIGURE 19. Transistor Collector-Emitter
Saturation Voltage vs Collector Current
typical applications
'sv
'sv
11
11
10
SUB
10
,v
'v
OUTPUT
0554450
0554450
GNO
GNO
INPUTG
INPUT A
V'" if + Al • A2 + At·
<>--+-----'
Ai
FIGURE 21. 500 mA Sink
FIGURE 20. Gated Comparator
'Vl
0-------..,...-....,."""""'-------0
our.QF-PHASE OUTPUT
5Vo-~~-----------~--~------2k
__
82'
B.2k
~
8.2k
r - - " t - - O IN·PHASE OUTPUT
INPUT
0-----,
,---+---+----------1-+-0 OUTPUT
Q
-V2
't5V
14
13
12
11
10
0575450
GNO
STROBE
Tbis side can perform the same 01 another fllnction.
FIGURE 22. Floating Switch
'-24
L--t=t=~=====t~LooUTPUTo.
FIGURE 23. Square-Wave Generator
o
en
<.TI
typical applications (con't)
<.TI
~
• V1 0-......- - - - -.....-
U1
.....- - ,
o
......
o
en
.....
<.TI
'5V
~
<.TI
o
en
(1)
DIODE ARRAY
r---------.,
I
I
I
I
:I.
(1)
1/1
I
J
I
SOURCE
... CURRENT
STRUBE
TO MEMORY DRIVE LINES
'-_+-_ _ _-0 -V2
Sour~e
and sink controls ~re aGtlvateri by
~Igh-Igvel
inpm volt.lges {V IH .:.: 2Vl
FIGURE 24. Core Memory Driver
.5V
0--._------------+---,
lN759
4.7k
,--+---4---+-.ND
Resislor Wlluas shawn II. nominal
C1
0555462/0575462
L..,14....._-osu,
......-.---------<>vt.:c
,....,----~-------'l
C2
E2
t---r----------oV2
A2
o---+---t--+
'-...............------...- ' -.....~---------o.ND
o
Risistorvaluesshown Ire nomioal.
Resistorvalul shown are oomilUll
0555463/0575463
0555464/0575464
......
r---_-.------~--~.--------Ov~
r------.------~--~.--'l
' -...........----.....---------....._ ........~-o.ND
,Resistor valuel shown are nominal.
truth ta bles
-.--------<>v~
'-...........----....----------.....~~--...............~--O.ND
Resirtor YlIluesshown are nominll.
(H = high level, L = low level)
0555461/0575461
0555462/0575462
0555463/0575463
A
B
A
B
V
A
B
L
L
L (ON State)
L
L
H (OFF State)
L
L
L (ON State)
L
H
L (ON State)
L
H
H (OFF St.te)
L
H
H
L
L (ON' State)
H
L
H
H
H
H (OFF State)
H
H
H ~OFF State)
L (ON Stat,e)
H
V
055546410575464
A
B
V
L
L
H (OF F State)
H (OFF State)
L
H
L (ON State)
L
H (OFF State)
H
L
L{ON State)
H
H (OFF State)
H
H'
L (ON State)
V
1-33
dc test circuits
Vco
Each ~put Is 1IItIId 8llplmely.
Bodt inputs Ire UltldtimultllnlOusiv.
Each input is testlld 8IIplraltllv.
FIGURE 1. VIH •. VOL
FIGURE 2. Vil. VOH
FIGURE 3. VI. IlL
v'"
V,o;::.=~-,
v,
Each gate is ttosted seplrataly.
EICII input is tlsttd.,.rltlly.
FIGURE 4. II.IIH
FIGURE 5.
BotfIga1ISareteStlldsimulllnlousty
ios
FIGURE 6. ICCH. ICCl
g
'oM
SEE
TEST
VOH
~IOL
TABLE
V'"
~~
,-~--,.-
CIRCUIT
INPUT
UNDER
TEST
0555461
,
0555463
0555464
• APPLY
VOH
V'L
10L
VOL
V,H
V1H
10L
V'L
Vee
VOH
V.oc·
fOH
V,H
V'L
Gnd
V,IL,
VOH
IOL
10H
VOL
V,H
Gnd
IO'L
V'L
V'L
VOH
VOL
10H
·
'M
."!fT" .
NOT£S
4.5V
MEASURE
,V'H
Vee
V,H
·0555462
OTHER
INPUT
OUTPUT
v'"
"OH
v~o"
;,.
I.
OPEN
}a.A
~~
Ne181: Elchinputilbstad8ll...rately.
Nohl!: WbM ftltill{l OS5548310175413 Ind OS75484,
lnputnat' ..nd.rtestislfOu~.
Forlllo1bBrcircttfhitilat4.5V,
FIGURE 8. VI. IlL
Each input is bIbd .....tely.
FIGURE 1. VIH. Vil. IOH. VOL
v""
OPE.
v,.o----"'-I
o'm
v,
Each input is tqted stpIrately.
FIGURE 9. II. IIH
'·34·
FIGURE 10. ICCH. ICCl for
AND. NAN 0 Circuits
FIGURE 11. ICCH.ICCl for
OR. NOR Circuits
switching characteristics
INPUT
2.4V
Vee
OUTPUT
~~r'Ct:::---:""' 'V
".~ 10%°1""
+1 /""
F""'
~15V
5V
INPUT
'v
O
"---VOL
OUTPUT _ _ _ _'_"_"___/ -
V
Notel: TIle poise §eneratol ha~ the following characteristics: PAR" 1 MHz, louT'"
"
son.
Note2:C L includeprobeandjigcapacitmce.
FIGURE 12. Propagation Delay Times, Each Gate (OS55460 and OS75460 Only)
"V
-tV
INPUT
R~
r-"'''
I~--"9O"'"""'+---------'V
"50
'&".
INPUT'
....-4~.....'-OUTPUT
1
tL"15pF
(NDTE21
8-,,'"'
'v
ouTPur-----::,,"'"'%1'-___I_-'-'11!"",,,"'%---Notel: Tile pulse generator has the followmg characteristics: duty cycle::; 1%, ZOUT '" 50n.
Nale2: CL !ntludesprobeandjigcapacltance
FIGURE 13. Switching Times, Each Transistor (OS55460 and OS75460 Only)
INPUT
1,1,,1
o
~~-----,.,v
"V
2.4V
INPUT
0555460
0555461
OS55463
Rt =50
1--------,-.,,--------1
S;5.0ns
....-
. . .-<>OUTPUT
INPUT
0555462
0555464
"-!!"'------,v
90%
911%
OUTPUT
~"-------------'1_'.::+--VOI
Note 1: The pube generator has the following charactel;!!ic!: PRR ~ 1 MHz, ZOUT"" SOn.
Nnte 2: When te,ting DS5S460 or DS75460, connect output Y In IlamistDf base and ground the sullstrate termin~l.
Nofll3: CLincludesprobe and jig clpacitnnte.
tTHl
FIGURE 14. Switching Times of Complete Drivers
Vs"
~OV
INPUT
INPUT
2.4V
~~~~:~
5V
l
0555463
r""'
---j
~D%
1,5V
L..~~-""'OOUTPUT
r"""'
--i
90":\11
_____ ,v
$10115
1.5~~,-_ _ _ _ _
1.5V
,,%
,v
1{90%
1.5V
I :_:"%====:;;,:===:':D%=~
I40,.5
INPlJTl~;;5ns
OS55462
0555464
l
'v
,v
OUTPUT
'-----------J·--- VOI
Note 1: Tile pulse ~enerator has the follOWing characteristics: PRR ,. 12.5 kHz, ZOUT " 50n.
Note 2: When tening OS5546 01 DS15460, connect output Y to transistor bsse wilh a 500n resistor from there to" ground,
and ground the substrate termiJl1lI.
Note 3: CL mcludesIJrobeandjigcapacitance.
FIGURE 15. Latch·Up Test of Complete Drivers
'·35
c
~
~
Level Translators/Buffers
en
w
Advance Information*
o
........
c
en
NAll0NAL
w
en
w
o
OS1630/0S3630 hex CMOS compatible buffer
general description
features
The OS1630/0S3630 is a high current buffer intended
for use with CMOS circuits interfacing with peripherals
requiring high drive currents. The OS1630/0S3630
features low quiescent power consumption (typically
50,uW) as well as high·speed driving of capacitive loads
such as large MOS memories. The design of the OS1630/
OS3630 is such that V cc current
spikes
commonly
found in standard CMOS circuits cannot occur, thereby,
reducing the total transient and average power when
operating at high frequencies.
•
H igh·speed capacitive driver
•
Wide supply voltage range
•
Input/output TTL compatibility
•
Input/output CMOS compatibility
•
No internal transient Vee current spikes
•
50,uW typical standby power
•
Fan out of 10 standard TTL loads
equivalent schematic and connection diagrams
Dual-In-Line Package
OUT 6
14
13
IN 6
12
OUT 5
IN'
11
10
IN 2
OUT J
OUT 4
IN 4
IN 3
GND
-o OUTPUT
INPUT o--'VVII"'~VVIt-....
OUT 1
IN'
OUT 2
TOP VIEW
Order Number DS163OJ, DS3630J
or DS3630N
typical applications
.,v
.,v
.,v
74C
CMOS
FAMILY
74C
CMOS
FAMILY
OS363D
~~
LINE
CMOS to TTL Interlace
CMOS To Transmission Line Interface
v'
740
CMOS
FAMILY
CMOS To CMOS Interlace
LED Driver
*Specifications may change.
2·1
o
M
CD
M
absolute maximum ratings
operating conditions
(Note 1)
(/)
o
"oCD
Supply Voltage
Input Voltage
Output Voltage
Lead Temperature (Soldering, 10 seconds)
M
U;
o
l6V
l6V
16V
300°C
dc electrical cha racteristics
Temperature (T A)
051630
053630
=
Vee, lOUT = -400/lA
V ,N = Vee - 2.0V, lOUT = 16 mA
IINL
Logical "0" Input Current
V OH Logical "1" Output Voltage
V IN = O.4V, louT = 16 mA
V IN = Vee, lOUT =-400/lA
V ,N = Vee - O.4V, lOUT = 16 mA
VOL Logical "0" Output Voltage
V IN = OV, lOUT = 400/lA
V,N = OV,
lOUT = 16mA
V IN = O.4V, lOUT = 16 mA
ac electrical.characteristics
t"dl
Propagation Oelay to a Logical "0"
Propagation Oelay to a Logical "1"
V
--!i5
+125
+70
°c
°c
0
UNITS
MIN
TYP
MAX
UNITS
90
200
/lA
053630
90
200
/lA
051630
0.5
3.2
mA
1.5
mA
053630
0.5
OS1630
-0.15
053630
V ee -150
-1
mA
-800
/lA
051630
V ee -l
V ee -o· 75
V
053630
V ee -0.9
V
OS1630
V ee -2.5
V ee -o· 75
V ee -2.0
053630
V ee -2.5
V ee -2.0
V
V
0.75
1
V
053630
0.75
0.9
V
OS1630
0.95
1.3
V
OS3630
0.95
1.3
V
OS1630
1.2
1.6
V
053630
1.2
1.5
V
051630'
Vee = 5.0V, TA = 25°C u'1(ess otherwise specified
TYP
MAX
C L = 50 pF
30
45
ns
C L : 250 pF
40
60
ns
GL = 500 pF
50
75
ns
GL = 50 pF
15
25
ns
GL = 250 pF
35
50
ns
GL ~ 500 pF
50
75
ns
CONDITIONS
PARAMETER
tpdO
.15
051630
CONDITIONS
Logical "1" Input Current
V tN
MAX
3
(Notes 2 and 3)
PARAMETER
IINH
MIN
Supply Voltage (V CC)
MIN
UNITS
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed" Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified min/max limits·apply acmss the -5SoC to +125°C temperature range for the OS1630 and across the O°C to
+70°C range for the 053630. All typicals are given for VCG
= 5.0V and T A = 25°C.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to,ground unless' otherwise noted. All
values shown as max or min on absolute value basis.
2·2
o
CJ)
typical performance cha racteristics
VOH VI Temperature,
VIN
0.3
0.4
Ii
".
~
~
2!
".
'"
= Vee
~
m
VOH Active vs Temperature
~ lOUT - -40011A
1.6
Ii
".
0.5
g'"
0.6
.,.
0.7
0.8
0.9
1.0
0.4
o
=
.......
oCJ)
=
lOUT'" --400pA840
_
V,"
OV
0
w
800
en
w
o
1.8
~
2!
'"
2.2
760
S
.s
1.9
2.0
".
Y'N - Vee
louT-16mA
1.1
w
VOL vs Temperature
880
720
"0
0
680
".
2.1
640
L"
600
85 105 125
560
-55 -35 -15 5
2.3
1.1
-55 -35 -15 5
25 45
85 105 125
65
-55 -35-15
TEMPERATURE rCI
5
25 45
65
TEMPERATURE ('CI
VOL vs Temperature
45 65 85 105 125
25
TEMPERATURE rCI
tpdo vs load Capacitance
Propagation Delay vs
70
1.6
1.5
45
Vee'" S.OV
VIN '" OV
IOUT- 16mA
TA '" 25°C
]:
60
>-
1.4
~
1.3
]:
15"
1.2
J.
>-
1.1
1.0
Vee
CL '" 250 pFTA"'25°C -
g
V
50
......
k'
40
~
./
./
........
i
./
30
40
........
I"",
"">=
35
........
.....
I"",
0.9
20
-55 -35 -15 5
25 45 65 85 105 125
30
0
100
200
300
400
7
9
13
11
15
Vee (V)
Propagation Delay
vs Temperature
tpd1 vs Load Capacitance
Vee'"
5
LOAD CAPACITANCE (,FI
TEMPERATURE rCI
60
3
500
f- Vee -
s.nv
I- CL
TA =2S C
Q
'"
5V
250 pF
50
50
]:
40
g
30
"">=
>
]
j.
/
10
V
V
0
i
1/
100
200
f-
~
/
20
40
300
400
500
-
I"",
J.-J.--
I"",
30
-55-35-155
LOAD CAPACITANCE (,FI
25
45
65
85 105 125
TEMPERATURE rCI
ac test circuit and switching time waveforms
INPUT
PULSE
GENERATOR
L
1k
v·
~ %"'"'
~"'''"'
Ce
INPUT
-I"r- -It
soil
V'N:~t90%
50%
OV
10%
_-PW_
Vo "
OUTPUT
Voe
tpd1-
Cl Includes probe and 1'9 capacitance
':'
t%
511%
-
I"",
Pulse Generator characteristics: PRR" 1.0 MHz, PW" 500 os, t," tf
< 10 os,
V1N"OtoVcc
2-3
o
o
00
00
o
o
~
"
DS7800/DS8800 dual voltage translator
o
c
......
Level Translators/Buffers
NAll0NAL
00
(/J
C
general description
features
The DS7800/DS8800 are dual voltage translators
designed for interfacing between conventional TTL
or OTL voltage levels and those levels associated
with high impedance junction or MOS FET-type
devices. The c;lesign allows the user a wide latitude
in his selection of power supply voltages, thus providing custom control of the output swing. The
translator is especially useful in analog switching;
and since low power dissipation occurs in the "off"
state, minimum system power is required.
•
31 volt (max) output swing
•
1, mW power dissipation in normal state
•
Standard 5V power supply
•
Tem perature range:
OS7800
OS8800
•
Compatible with all MOS devices
schematic and connection diagrams
v,
Rt
R2
20K
4.51(
...
Metal Can p'ackage
+-__
*+_OUTPUTX
Order Number DS7800H
or DS8800H
' - - - -.....-v,
typical applications
Bipolar to MOS Interfacing
4-Channel Analog Switch
'r
T
r--~5~--1
r"l-- _<1., I
I
SWITCH t - . l . -....---...
I
1
~
I
I
I
I
SWTTCH2-J.....L..r-...
r-, .......--rn
OTl
OR
TTl
I
INPUT
LEVELS
ANALOG INPUT 3
.I
I
ANALOG INPUT"
SWITCH 4_l-.I..,r-.,.
'---r.J
~
II
I
.ztv
*Allalog signals within the range of +8V to -8V.
2-4
.n=
r,J" __ ~!l.,
I
ANALOG INPUT I'
I
I
ANALOG OUTPUT
L _____
II
-.J
OR
_55°C to +125°C
O°C to +70°C
~V-!~
I::~T~
LEV£lS~
LI---T~
-=
·UI\i
c
absolute maximum ratings
V CC Supply Voltage
V2 Supply Voltage
V3 Supply Voltage
V3-V2 Voltage Differential
Input Voltage
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
electrical characteristics
Supply Voltage (V CCI
057800
058800
7.0V
-30V
30V
40V
5.5V
-65°C to +150°C
300°C
Temperature (T A)
057800
058800
CONOITIONS
V ,H
Logical "1" Input Voltage
Vee = Min
V ,L
Logical "0" Input Voltage
Vee = Min
I'H
Logical "1" Input Current
MIN
Vee = Max
5.5
5.25
V
V
+125
+70
-55
0
TVP
(NOTE 61
MAX
cCJ)
CO
CO
o
o
UNITS
V
V
5
i1A
1
mA
--D.4
mA
1N ==
Vee = Max, Y'N
Vee = Max, Y'N = O.BV (Notes 4 and 7)
Ro
Output .collector Resistor
TA =25°C
VOL
Logical "0" Output Voltage
Vee = Min, Y'N = 2.0V (Note 7)
ICC(MAX)
Power Supply Current
-0.2
= OAV
11.5
16.0
10
i1A
20.0
kQ
V 2 + 2.0
V
Vee = Max, Y'N = 4.5V (Note 5)
0.85
1.6
mA
Vee = Max, Y'N = OV (Note 5)
0.22
0.41
mA
MIN
TVP
MAX
= 15 pF (Note 8)
25
70
125
ns
T A = 25°e, e = 15 pF (Note 9)
25
62
125
ns
switching characte ristics
PARAMETER
tpdO
Transition Time to Logical
"0" Output
'-pdl
Transition Time to Logical
"1" Output
CONDITIONS
TA = 25°e, e
.....
o
o
CO
"-
°c
°c
5.5V
IV
Logical "0" I nput Current
Curr~nt
4.5
4.75
I Y'N = 2.4V
Output Leakage Current
Power Supply
UNITS
0.8
I'L
Output "0 F F"
MAX
2.0
10H
ICC(MIN)
MIN
(Notes 2 and 3)
PARAMETER
Output "ON"
CJ)
operating conditions
(Note 1)
UNITS
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified minimax limits apply across the -55°C to +125°C temperature range for the 057800 and across the aOc to
+70°C range for the 058800.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
Note 4: Current measured is drawn from V3 supply,
Note 5: Current measured is drawn from Vec supply.
Note 6: All typical values are measured at TA = 25°e with Vee = 5.0V, V2 = -ny, V3 = +8V.
Note 7: Sp~cification applies for all allowable values of V2 and V3'
Note 8: Measured from 1.5V on input to 50% level on output.
Note 9: Measured from 1.5V on input to logic "0" voltage, plus 1V.
2-5
o
o
CO
CO
theory of operation
tn
C
The two input diodes perform the AND function
on TTL or DTL inp.ut voltage levels. When at least
one input voltage is a logical "0", current from Vee
(nominally 5.0V) passes through R, and out the
input(s) which is at the low voltage. Other than
small leakage currents, this current drawn from Vee
through ,the io krl resistor is the on Iy source of
power dissipation in the logical" 1" output state.
C>
o
~
c
When both inputS are at logical" 1" levels, current
passes through R, and diverts to transistor 0" turn·
ing it on and thus pulling current through R2 . Cur·
rent is then supplied to the PNP transistor, 0;. The
voltage losses caused by current through a" D3 ,
and O2 necessitate that node P reach a voltage suf·
f.icient to overcome these losses before current be·
gins to flow. To achieve this voltage at node P, the
inputs must be raised to a voltage level which is one
diode potential lower than node P. Since these levels
are exactly the same as those experienced with con·
ventional TTL and DTL, the interfacing with these
types of circu its is achieved.
Transistor O 2 provides "constant current switch·
ing" to the output due to the common base con·
nection of O 2 , When at least one input is at the
logical "0" level, rio current is delivered to O 2 : so
that its collector supplies essentially zero. current
to the output stage. But when both inputs a~e r~ised
to a logical "1" level current is supplied to O2 ,
Since this current is relatively constant, the collec·
tor of O 2 acts as a constant current source for the
output stage. Logic inversion is performed since
logical" 1" input voltages cause current to be sup·
plied to O 2 and to 03' And when 0 3 turns on the
output voltage drops to the logical "0" level.
The reason for the PNP current source, O 2 , is so
that the output stage can be driven from a high
impedance. This allows voltage V2 to be adjusted
in accordance with the application. Negative volt·
ages to -25V can be applied to V2. Since the out·
put wiH neither sO,urce nor sink large amounts of
current, the output voltage range is almost exclu·
sively dependent upon the values selected for V2
and V3 .
Maximum leakage current through the output min·
sistor 0 3 is specified at 10 /lA under worst· case
voltage between V 2 and V3• This will result in a
logical "1" output voltage whith is 0.2V below V3'
Likewise the clamping action of diodes D4 , Ds, and
D6 , prevents the logical "0" output voltage from
falling lower than 2V above V 2, thus establishing
the output voltage swing at typically 2 volts less
than the voltage separation between V2 and V3.
selecting power supply voltage
The graph shows the boundary conditions which
must be used for proper operation of the unit. the
range of operation for power supply V 2 is shown
on the X axis. It must be between -25V and -8V.
The allowable range for power supply V3 is gov·
erned by supply V 2. With a value chosen for V 2, V 3
may be selected as any value along a vertical line
passing through the V2 value and terminated by
the boundaries of the operating region. A voltage
difference between power supplies of at least 5V
should be maintained for adequate signal swing.
20
15
10
-5
-10
-15
-20
-:25
switching time waveforms
INPUT
I-""\
OUTPUT~_ _
'=---i
___---'+_--'.1_
1.0V
T~,-~
2-6
~
o
~
00
o
"o
...
Level Translators/Buffers
CJ)
NAnONAL
00
00
...o
057810/058810 quad 2-input TTl-M05 interface gate
057811/058811 quad 2-input TTl-M05 interface gate
057812/058812 TIl-M05 hex inverter
general description
oCJ)
.....
......
00
These Series 54/74 compatible gates are high output voltage versions of the OM5401/0M7401
(SN540 1 /SN 7401), OM 5403/0M7403
(SN 5403/SN 7403), and OM 5405/0M7405
(SN5405/SN7405). Their open-collector outputs
may be "pulled-up" to +14 volts in the logical "1"
state thus providing guaranteed interface between
TTL and MOS logic levels_
In addition the devices may be used in applications
where it is desirable to drive low current relays or
lamps that require up to 14 volts.
"-
o
CJ)
00
00
......
o
~
...
00
schematic and connection diagrams
N
,----.----0 v"
"-
.----.........------0 v"
o
CJ)
4k
00
00
N
OUTPUT
INPUT
INPUTS
...
Uk
OUTPUT
0-:=-+-.-'
1k
L...---4~-OGNO
L . . . -.....-oGNO
087810/088810,087811/088811
OS7812/0S8812
Dual-In-line Package
Dual-I n-Line and Flat Package
GNO
TOP VIEW
TOPVIEW
OS7810/0S8810
OS7811/0S8811
Dual-In-Line and Flat Package
"
13
12
11
10
Order Number
OS7810J
OS7811J
OS7812J
OS8810J
OS8811 J
OS8812J
TOP VIEW
OS8810N
OS8811N
OS8812N
OS7810W
OS7811W
OS7812W
GNO
OS7812/0S8812
2-7
...co
N
co
absolute maximum ratings
operating conditions
(Note 1)
en
Q
.......
...,...
N
CO
Input Voltage
Output Voltage
Storage Temperature Range
en
Lead Temperature (Soldering, 10 seconds)
Supply Voltage (Vee)
D578XX
DS88XX
7V
5.5V
14V
_65°C to +150o e
300°C
Vee
Temperature (T A)
DS78XX
DS88XX
Q
...
CO
CO
en
electrical characteristics
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
-55
0
+125
+70
°e
°e
(Notes 2 and 3)
Q
...
,...
.......
PARAMETER
CONDITIONS
MIN
Input Diode Clamp Voltage
Vee
en
V ,H
Logical "1" Input Voltage
Vcc = Min
V'L
Logical "0" Input Voltage
Vee == Min
IOH
Logical" 1" Output Current
Vce
en
IOL
Logical "0" Output Current
Vee
= Min, Y'N = 2.0V, V OUT = O.4V
16
.......
V OH
Logical" 1" Output Breakdown Voltage
Vee
= Min, Y'N = OV, 100JT = 1 rnA
14
VOL
Logical "0" Output Voltage
Vee
= Min, Y'N = 2.0V,
I'H
Logical "1" Input Current
I'L
Logical "0" Input Current
ICC(MAx)
Logical "0" Supply Current
...
0
CO
CO
Q
...,...
0
V OUT
CO
en
=
Min,
(Each Gate)
lee(MIN)
Max
= O.OV
lOUT
=
Vee
= Max,
Y'N
= O.4V
Vee
= Max,
Y'N
= S.OV
Vee
= Max, Y'N = OV
V
0.8
V
250
J1A
40
J1A
rnA
V
= 16 rnA
I Y'N = 2.4V
Vee
Logical" 1" Supply Current
(Each Gate)
I Y'N = 0.8V
Y'N
UNITS
V
2.0
= 10V .1
Q
MAX
-1.5
VCLAMP
Q
TYP
= 5.0V, TA = 25°C, 'iN = -12 rnA
CO
I Y'N = 5.5V
0.4
V
40
J1A
1
rnA
--1.6
rnA
3.0
5.1
rnA
1.0
1.8
mA
TYP
MAX
UNITS
4
12
18
ns
18
29
45
ns
switching characteristics
PARAMETER
tpdO
CONDITIONS
Propagation Delay Time to
COUT = 15 pF, RL = 1k
Logical "0"
tpd1
MIN
Vee = S.OV, TA = 25°C,
a
= 25°C,
= 15 pF, RL = 1k
Propagation ,Delay Time to a
Vee = 5.0V, TA
Logical "1"
COUT
Note 1: "Absolute Ma'ximum Rati'ngs" are those 'values beyond which the safety_ of the device cannot be -guaranteed. Except for "Operating
Temperature Range" they are not meant to imp,ly that the devices should be operated at, these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified mi~/max limits apply across the '-55°C to +125°C temperature range for the DS781 0, DS7811 and OS7812 and
across the '(Joe to +70°C range for the DS7810, DS7811 and D57812.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
'
typical applications
+10V
+12V
3k
_ I,
GROUND
'--I~-""---iIINPUT
ClOCK
I I
INPUT
-v,
058810, DS8811, OS8812
MOSshiftregBter
(ExampleMM506)
2-8
+
>V,
V"
058810, OS88", OS8812
Note: Normal voltages applied to MOS shift
registers have been shifted by +10V for this
application.
7.5k
I
+10V--,
L--6V
1
MOSROM
(ExampteMM5221)
c
~
....oco
.......
ac test circuit and switching time waveforms
c
en
+5V
~
: .
:
9
~
co
co
....
o
--3.0V
--15V--
R,
INPUT
I
I
:
c
I
I
I
OUTPUTi\ij'
I
I
I
I
tpdo~1
I
.
I
I
en
-..J
co
....
....
I
---50%--.
I
I
I
i~l
I
I
I
.......
C
I
I
l__
\
en
tpdl
co
co
....
i= 1 MHz
....
t," tf '" 10 ns
PW '" 100 ns
c
~
co
....
N
.......
C
en
co
...co
N
2-9
~
Level Translators/Buffers
NAll0NAL
DS78L12/DS88L12 TTL-MOS hex inverter/interface gate
general description
The DS78L12/DS88L12 is a low power TTL to
MOS hex inverter element. The outputs may be
"pulled up" to +14V in the logical "1" state, thus
providing guaranteed interface between TTL and
MOS logic levels, The gate may also be operated
schematic and connection diagrams
zo.
40.
with Vee I~\iels up to +14V without resistive
pull-ups at the outputs and still providing a guaranteed logical "1" level of Vee - 2.2V with an
output current of -200J1A.
Dual-I n-line and Flat Package
'00
v"
GND
TOP VIEW
Order Number DS78L 12J, DS88L 12J
Order Number DS88L 12N
Order Number DS78L 12W
Note: Shovrn IS schematIC lor eac/l inverter
typical applications
TTL I nterface to MOS ROM
TTL Interface to MOS ROM
Without Resi~tive Pull-Up
With Resistive Pull-Up
N.tiu...1MOS ROM
_lhaIllPIIMM5UI)
'--':.,::;--'
switching time waveforms
ac test circuits
Vcc "140V
',,- r-t - - -'00.
~""
hrVec
p--3.0V
Vcc=5V
~
,4V
---.I!--"V.--~
INPUT
r"-""
foIVcx:" 5.0V
I
I
::
1"",,~
"
Figure 1
2-10
Figure 2
I
::
(lUTPUT~i~
- - - 50%"--,
::
I~_I
I
~t ... \
I
~:~~~~".
absolute maximum ratings
crJ)
operating conditions
(Note 1)
~
CO
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldering. 10 sec)
MIN
MAX
UNITS
4.5
4.15
5.5
5.25
V
V
125
70
°c
°c
!:
N
Supply Voltage (VCC)
DS78L12
DS88L12
Temperature (T A)
DS78L12
DS88L12
15V
5.5V
15V
,-65°C to +150°C
300°C
.......
C
rJ)
-55
0
CO
CO
!:
N
electrical characteristics
(Notes 2 and 3)
MIN
TYP
Vee = 14.0V
CONDITIONS
2.0
Vee:= Min
2.0
1.3
1.3
PARAMETER
V ,H
Logical "1" Input Voltage
V ,L
Logical "0" Input Voltage
V OH
Logical" 1" Output Voltage
Vee = 14.0V
Vee - Min
V ,N = 0.7V
Vee = 14.0V, lOUT = -20011A
I Vee"" Min,
lOUT = 200l1A
MAX
V
V
1.3
0.7
V
1.3
0.7
V
11.8
12.0
V
14.5
15.0
V
V
V ,N = OV, Vee = Min, lOUT = -5.0I1A (Note 6)
VOL
Logical "0" Output Voltage
I'H
Logicat "1" Input Current
V ,N =2.0V
V ,N = 2AV
V ,N = 5.5V
I'L
Logical "0" Input Current
Ise
Output Short Circuit Current
lecH
Supply Current - Logical "1"
(Each Inverter)
'eeL
Supply Current - Logical "0"
(Each Inverter)
V ,N = OAV
VOUT "" OV
(Note 4)
V ,N = OV
V ,N = 5.25V
UNITS
Vee = 14.0V, lOUT = 12 rnA
Vee;::: Min,
lOUT;::: 3.6 rnA
Vee = 14.0V
0.5
1.0
0.2
V
OA
V
<1
20
I1A
<1
10
I1A
Vee = 14.0V
<1
100
I1A
Vee
<1
Vee
=
Max
100
I1A
Vee = 14.0V
-320
-500
I1A
Vee
-100
-180
I1A
-25
-50
rnA
-8
-15
rnA
=
=
Max
Max
Vee = 14.0V
-10
Vee = Max
-3
,
Vee = 14.0V
0.32
0.50
rnA
Vee = Max
0.11
0.16
rnA
Vee = 14.0V
1.0
1.5
rnA
Vee = Max
0.3
0.5
mA
switching characteristics
tpdO
tpd1
UNITS
TYP
MAX
(Figure 21
27
45
ns
from Input to Output
Vee 5.0V
Vee = 14.0V
(Figure 11
11
20
ns
Propagation Delay to a Logical "1"
Vee = 5.0V
(Figure 21,(Note 5)
79
100
ns
Vee = 14.0V
(Figure 11
34
55
ns
CONDITIONS
PARAMETER
Propagation Delay to a Logical "0"
TA = 25°C
TA = 25°C
from Input to Output
MIN
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions tor actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the -5SoC to +12SoC temperature range for the DS78L 12 and across the aOe to
+70°C range for the DS88L 12.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: tpd1 for Vee"" S.OV is dependent upon the resistance and capacitance used.
Note 6: VOL
= VCC -1.1V for the DS88L12 and VCC -l.4V for the DS78L 12.
2-11
...
0)
00
00
~
VJ
C
........
...
0)
00
,....
Level· Translators/ Buffers
NAnONAL
VJ
C
057819/058819 quad 2-input TTL-MOS AN 0 gate
general description
The DS7819/DS8819 is the high output voltage
version of the SN5409. Its open-collector outputs
may be "pulled-up" to 14V in the logical "1"
state thus providing guaranteed interface between
TTL and MOS logic levels.
schematic and connection diagrams
4.
1.6K
2'
Dualwl n-Line and Flat Package
TOP VIEW
Order Number'oS7819J or DS8819J
Order Number DS8819N
Order Number DS7819W
2-12
o
absolute maximum ratings
MIN
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
7.0V
5.5V
5.5V
-B5°e to 1500 e
3000 e
Lead Temperature (Soldering, 10 sec)
electrical characteristics
Temperature IT AI
DS7819
DS8819
PARAMETER
CONDITIONS
Vcc~Min
V ,L
Logical "0" I nput Voltage
Vec
IOH
Logical" 1" Output Current
I'H
Logical "1" Input Current
UNITS
~
o
5.5
5.25
V
V
en
-55
0
+125
70
°e
°e
....00C.D
MIN
TYP
00
0.8
1V ,N ~ 2.0V, V OUT ~ 10V
1V ,N ~ 4.5V, V OUT ~ 14V
=:
Min
Vcc
~
Min, V ,N
~
0.8V, lOUT
~
UNITS
V
Min
Vce~Max
MAX
2.0
Vee
fJ.A
1.0
mA
004
16 mA
II V ,N ~ 204V
V ,N
5.5V
~
V
40.0
V
40.0
fJ.A
1.0
mA
-1.6
mA
I'L
Logical "0" I nput Current
Vce
~
Max, V ,N
~
Oo4V
ICCH
Logical "1" Supply Current
Vec
~
Max, V ,N
~
5V
11.0
21.0
mA
Iccl
Logical "0" Supply Current
Vcc
~
Max, V ,N
~
OV
20.0
33.0
mA
VCl
Input Clamp Voltage
Vce ~ 5.0V, TA ~ 25°C, liN ~-12 mA
-1.5
V
switching characteristics
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
tpdO
Propagation Delay to a Logical "0"
Vec ~ 5.DV, TA ~ 25°C
16.0
24.0
ns
tpdl
Propagation Delay to a Logical "1"
Vce ~ 5.DV, T A ~ 25°c
16.0
32.0
ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the -55°C to +125°C temperature range for the DS7819 and across the aOc to
+700 C range for the DS8819.
Note 3: All currents into device pins shown as positive, out of device pins as negatjve, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
ac test circuit and switching time waveforms
1.!iV
'5V
~.T
/.
/
/
.
INPUT
I
--I
/
,'/
:[//
/j../ ...~-:
+24,..,:·
COWT
OUTPUT
f~l
....
00
CD
4.5
4.75
(Notes 2 and 3)
Logical "1" Input Voltage
Logical "0" Output Voltage
MAX
.......
Supply Voltage IV eel
DS7819
DS8819
V ,H
VOL
en
-..J
operating conditions
(Note 1)
\
1.5VK
- --- '." 1j,%
50~
tpd'
MHz
t, ~ If" 10",
PW=100n,
2-13
~
Line Drivers/Receivers
NAT10NAL
D51488 quad line driver
general description
features
The OS1488 is a quad line driver which converts
standard OTLITTL input logic levels through one
stage of inversion to output levels which meet EIA
Standard No. RS·232C and CCITT Recommenda·
tion V. 24.
•
•
•
•
•
Current limited output
± 10 mA typ
Power·off source impedance
300ft min
Simple slew rate control with external capacitor
Flexible operating supply range
Inputs are OTL/TTL compatible
schematic and connection diagrams
Dual-In-Line Package
TOPVIEW
Order Number DS1488J
1/4Clrcu,\
typical applications
RS232C Data Transmission
1/40S14B9/
TTL/Oil
---t"-,
--..
--"1-_'")::.>--
DS1489A
1/4051488
TTL/Oll
__ .r-,
p.-......I---.---+---I~o--:::t_ ...r.>- --
TTL/OTL
TTL/OTl
--·:{-1:::-<><>--==:t_
.,.1:.1- - -~-
TTLfDTL
-,,~(=}::=-oo(\--"""--....L--+--c(
tNTERfACEOA1A
TERMINAL EnUIPMENT
*Optionalfotnoisefilterillg.
RS232C Data Transmission
3·4
MaS to TTL/DTL Translator
absolute maximum ratings
...o
en
(Note 1)
~
CO
CD
The following apply for T A = 25°C unless otherwise specified.
Power Supply Voltage
I nput Voltage Range
Output Load Current
Power Dissipation (Note 2)
Operating Temperature Range
Storage Temperature Range
electrical characteristics
.......
...oen
10V
±30V
20mA
1W
O°C to + 75°C
-65°C to +150°C
~
CO
CD
l>
(Notes 2, 3 and 4)
DS14S9/DS14S9A: The following apply for Vee = 5.0V ±l%,O°C:S: T A
PARAMETER
V TH
Input High Threshold Voltage
:s: +75°C unless otherwise specified.
CONDITIONS
TA = 25°C, V OUT ::; 0.45V,
lOUT = 10 rnA
MIN
ID51489
IDS1489A
V TL
Input Low Threshold Voltage
T A = 25°C, V OUT ~ 2.5V, lOUT = -0.5 rnA
I'N
Input Current
V'N = +25V
V OH
TYP
MAX
UNITS
1.0
1.5
V
1.75
2.25
V
0.75
+3.6
1.25
V
+5.6
+8.3
rnA
-8.3
rnA
V'N = -25V
-3.6
-5.6
V'N = +3V
+0.43
+0.53
V'N =-3V
-0.43
-0.53
2.6
3.8
5.0
V
2.6
3.8
5.0
V
0.45
Output High Voltage
lOUT = -0.5 rnA
II V'N = 0.75V
Input = Open
rnA
rnA
VOL
Output Low Voltage
V'N = 3.0V, lOUT = 10 rnA
0.33
Isc
Output Short Circuit Current
V'N = 0.75V
3.0
Icc
Supply Current
V'N = 5.0V
14
26
rnA
Pd
Power Dissipation
V'N = 5.0V
70
130
mW
UNITS
V
rnA
switching characteristics
PARAMETER
tpd1
Input to Output "High"
CONDITIONS
TYP
MAX
RL = 3.9k, (Figure 1) (ac Test Circuit)
MIN
28
85
ns
RL = 390n, (Figure 1) (ac Test Circuit)
20
50
ns
Propagation Delay
tpdO
Input to Output "Low"
Propagation Delay
t,
Output Rise Time
RL = 3.9k, (Figure 1) (ac Test Circuit)
110
175
ns
tf
Output Fall Time
RL = 390n, (Figure 1) (ac Test Circuit)
9
20
ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the devJce cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant'to imply that'the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2; Unless otherwise specified minImax limits apply across the O°C to +75°C temperature range for the D51489 and DS1489A.
Note 3': All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or m in on abso lute value basis.
Note 4: These specifications apply for resp~nse control pin =: open.
3-5
co
~~
~. ~
.
en
~~
""~
NAll0NAL
Line Drivers/Receivers
Advance Information*
Q
oCD
Q
051688/053688 quad TRI-5TATE® differential line driver
general description
The OS1688/0S3688 are high-performance quad differantial line drivers, optimized for digital data transmission over balanced lines. The outputs are compatible
with EIA Standards RS-422. The circuit uses Schottkyclamped transistor logic for minimum propagation delay
and the inputs are fully compatible with 54LS/74LS
series low power logic.
The OS1688/0S3688 provide a strobe and TRI-STATE
control common to all four drivers. The OS1688 is
specified over -55°C to +125°C and the OS3688 is
specified.over O°C to +70°C temperature range.
features
•
•
•
•
Compatible with RS-422
Single 5V ±10% supply
Series 54LS/74LS compatible
Oual versi on of OS8830
connection diagram and truth table
Dual-I n-line Package
Vee
A4
.4
IN 4
DIS
IN 3
B3
'3
STROBE
1
1
0
X
DISABLE
0
0
0
1
OUTPUTS
A
B
INPUT
0
0
1
1
1
0
X
X
0
Hi·Z
1
Hi-Z
x "" Don't Care
.,
B1
IN1
STS
IN2
.2
A2
GNO
TOP VIEW
Order Number OS1688J, DS3688J
or DS3688N
test circuits
Open Circuit Measurement
Short Circuit Measurement
-0.25 TO +6.0V
y-<>
':- -0.25 TO +6.0V
Test Termination Measurement
Power uOF F" Measurement
*Specifications may change
3-6
absolute maximum ratings
Supply Voltage
Input Voltage
Supply Voltage (Vee)
7V
20V
100mA
600mW
-55°C to +1500 e
3000 e
Output Sink Current
Power Dissipation
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
electrical characteristics
c
operating conditions
(Note 1)
Temperature (TA)
D51688
D53688
~
,UNITS
MIN
MAX
4.5
5.5
V
+125
+70
°e
°e
-55
0
cen
w
en
CO
CO
CONDITIONS
V IN (1)
Logical "1" Input Voltage
Vee = 4.5V
V INIO)
Logical "0" Input Voltage
Vee = 5.5V
MIN
TVP
MAX
2
UNITS
V
0,8
V
IIN(1)
Logical "1" Input Current
IINIO)
Logical ·'0" Input Current
Vee =5.5V. V IN = OV
VeLAMP
Input Clamp Voltage
I'N=-12mA
1.5
V
VOA.VOs
Logical "1" Output Voltage
Vee = 5.5V. Output Open
5.5
V
V OA • Vee
Logical "0" Output Voltage
Vo
Open Circuit Differential
"
V IN = 20V
100
J1A
-0,36
mA
Circuit
Vee = 4,5V. 450n to Vee
1
V
Vee = 5.5V
5.5
V
Voltage
VT
Output Terminated Differential
Vee = 4.5V.
Voltage
Terminated lOOn
2
V
AV T
Difference in Differential Voltage
Vee = 5.5V
0.4
V
Vos
Driver Offset Voltage
Terminated lOOn
3
V
AVos
Difference in Offset Voltage
Vee = 5.5V. lOOn
ISA.ls8
Output Short Circuit Current
Vee = 5.5V. (Note 4)
IXA.lx8
Output Power "OF F" Current
Icc
t p d1,
tpdO
Vee = OV
0.4
IV OUT = -0.25V
IV OUT = 6V
V
-150
rnA
-100
J1A
100
J1A
Supply Current
Vee = 5.5V
13
rnA
Propagation Delay Differential
Terminated 100n, 25°C
20
ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the -55°C to +125°e temperature range for the 051688 and acr·oss the oOe to
+70° e range for the D53688. All typical values are for T A = 25° e and Vee = 5V.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on .absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: Refer to EIA·R5-422 for exact conditions.
typical application
~'
lINJ." DRIVER
1/4083&88
CO
CO
.......
(Notes 2 and 3)
PARAMETER
en
~
4000FT
TWISTED PAIR OR
FLAT CABLE PAIR
~
LINE RECEIVER
1/4 D83689 0 R
112 088BL8Z0 OR
D88820A
Multiple drivers and receivers m.y be bussed on common transmission line.
3·7
~
Line Drivers/Receivers
Advance Information*
NAll0NAL
a)
co
CD
(¥)
Ul
.e.en
051689/053689, 051690/053690 quad differential line receivers
co
~,
general description
features
The OS1689/053689 and OS1690/0S3690 are highperfon:nance quad differential line receivers, optimized
for digital data transmission over balanced and unbalanced
lines. The inputs are compatible with EIA and Federal
standards, and the Schottky-clamped outputs are fully
compatible with 54LS!74LS series low power logic.
.' Full compatibility with EIA standards RS-232-C,
RS-422 and RS-423, and Federal standards 1020 and
1030
The OS1689/0S3689 provide a TTL strobe input, for
each pair of receivers, in a 16-lead package, while the
OS1690/0S369() include a separate strobe for each of
the four receivers in an 18-lead package, The OS1689
and' OS1690 are specified over a -55°C to +125°C
operating temperature range, the 053689 and OS3690
over a O°C to +70°C range.
•
Input voltage range of ±15V (differential or commonmodel
• 5k input impedance
• 50 mV input hysteresis
• 200 mV input threshold
Four receivers in single '16-lead or 18-lead package
•
• Sirigle 5V, ±10% supply
connection diagrams
Dual-I n-Line Package
0".1-1 n-Line Package
IN
IN
IN
OUT
STROBE
IN
OUT
STROBE
OUT
OUT
I.
IN,
IN
TOP VIEW
Order Number OSI689J, DS3689J
or OS3689N
IN
vee
IN
IN
our
GNO
IN
IN
OUT
STB
SlB
STB
STB
OUT·
TOP VIEW
OUT
IN
IN
IN
IN
GND
Order Number OS1690J, OS389OJ
or OS3690N
*Specifications may change
3-8
c
absolute maximum ratings
Supply Voltage
Common·Mode Voltage
Differential I nput Voltage
Strobe Voltage
Output Sink Current
Power Dissipation
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
en
operating conditions
(Note 1)
8.0V
±25V
±25V
8.0V
50 rnA
6DOmW
-65'C to +150°C
300'C
Supply Voltage (V CC)
~
CJ)
MAX
4.5
5.5
V
"-
+125
+70
'c
'c
en
w
CJ)
+15
V
::;6
V
00
CD
Temperature (T A)
DS1689, DS1690
DS3689, DS3690
~55
Common-Mode Voltage (VCM)
-15
0
Voltage Differential (VDIFF)
UNITS
00
CD
MIN
c
C
~
CJ)
CD
o
c
.......
CJ)
w
CJ)
electrical characteristics
Differentia! Threshold Voltage
o
(Notes 2 and 3)
PARAMETER
V TH
CD
CONDITIONS
-10V:O: V CM
< +10V
R'N
Input Resistance
IIN(D)
Data Input Current (Unterminated)
Input Balance
:0: +15V
0.06
0.2
V
-0.2
V
?> 2.5V
0.06
0.3
V
V OUT S°.4V
-{I. OS
-0.3
4 mA,
400pA, V OUT
V CM
~
15V
3.0
V CM
~
OV
0
V CM
-
. 3.0
15V
~400.uA.
lOUT
-7V S V CM S +7V
lOUT - 4 mA,
~
0:=
V DIFF ::::. DAV
V OH
Logical "1" Output Voltage
lOUT
VOL
Logical "0" Output Voltage
lOUT ""- 4
V1N(1 )
Logical "1" Strobe Input Voltage
lOUT
=
4 rnA, VOUT ::; DAV, V01FF "" -3V
V1NW)
Logical "0" Strobe Input Voltage
lOUT
~
-400pA, V OUT
IIN(1)
Logical "1" Strobe Input Current
VSTROBE
IIN{Q)
Logical "0" Strobe Input Current
VSTROBE "" OV, V01FF
lOUT': OV, VSTROBE "" OV, Vee'" 5.5V, INote 4)
0::
=:
-lV
?> 2.5V,
mA
V
2.5
35
0
0.25
V
fl'A
V
0.4
V
0.8
V
2.0
V
V01FF '" -3V
,5.5V, VDIFF '" 3V
=::
4.2
4.5
-400,uA, V D1FF '" 1V
="
rnA
mA
0.4
··-0.5V, (Note 5)
rnA, V01FF
4.2
-0.5
2.5
V 01FF ---G.4V
VOlFe
V
kn
5
-15V:O: V CM S+15V
INote 6)
UNITS
-0.08
-400pA, V OUT
".0;
Power Supply Current
Icc
MAX
> 2.5V
0
lOUT
lOUT -- 4 rnA.
TYP
V OUT -t-+i-+-C
500
ADO lo-+o-i-lY
lo--+""'-'>N1r--'----~'i
R > - - - < > +4.15V
V2<>-----0,,'i
.,.'V<>-+---<>-='i
v,
-4.15V
V3 <>-+..---0-:-1
V4o--+-+....--o-:..f
n
053652
525v
+
0--0Icex
11!
V
053650
V aH
V2
083652
083650
+2.97SV
+2.975V
+3.0V
-2.975V
D83660
+2.975V
+2.975V
-3.0V
-3.0V
083652
+0.4 rnA
+3.0V
:
GND
-3.0V
GND
GND
GND
+3.0V
+3.0V
-3.0V
-3.0V
GND
GND
VOH OR VOL
Channel A shown under test. Other channels are tested similarly.
053650
FIGURE 1.ICEX. VOH. and VOL
3V<>-..-_________--,
R>--_O+5.25V
+525V
R>-~P-O'3V
R>-hhD-5.25V
-5.25V
FIGURE 2. ICCH and IEEH
r-()---<>+5.25V
+25 mV <>-----1-0.,
'- FIGURE 3.IIH(S) and IIL(S)
~-o---D+5.25V
V,
Vl-2.0V
<>-+--.--<>''-1
+J.DV
Q-,t--+--o-,"!
1-"'-525V
Note; Channel A shown
~o-Ht-D'-5.25V
Note: Channel A{-) shown under test, other channels
are tested similarly. Devices are tested with VI from
underte~t,lItherGhannelsare
+J.OVlo-J.DV.
teltedsilllilarly. Only one output shorted ata time.
FIGL!RE 4. lOS
~o---o +5.Z5V
VI-Z.OV
VI
0-+-.....-<>-''"1
+J.OV
o-+--t--o-'i
FIGURE 5.IIH
+l.DV <>--..---o-'i
+2.DV
Note: Channel A(-J shown und~r test, other channels
are tested similarly. Devices BIO tOired with VI from
+J.oVto-3,OV.
FIGURE 6. IlL
3·12
8 > - - - 0 +S.25V
o-l--l++-<>''i
8>-1",,-0
R:>-t""-<>-525V
Note: Output cif Channul A shown uoder test:, ut"er
outputs are tested similBrlv for V1 ;;; DAV and +2.4V.
FIGURE 7. 10FF
I,
+0.4 rnA
-3.0V
GND
-2.975V
+3.0V
-2.975V
V4
083652
GND
+3.0V
-3.0V
Va,
OS3650
+3.0V
+3.0Y
-2.975V
-3.0V
, CEX
V3
083652
-525V
-16 rnA
-16mA
ct/)
ac test circuits and switching time waveforms (con't)
+IODmV
w
en
"'V
o----....
U'I
--o...:.j
2..
'ON
.co
mv~
'0%
v~H~1
t/)
w
en
trHL1D1
U'I
15V
'"
N
Yo,
E1Nwavelanncharlr:teriltia:
tTLHandtTHL=:;;'DnsmeesuredID%lollO%
PAR=1.QMHz
DlityCyd.=SOOns
No.: O~t of Chpnll B
"'own IIndor t81t, 11th. Gh....s an testM limn.rly.
S'at A"'orDS3662
S,.t"B"f1HDS3Ii5D
t L=t5pFtotalforDS3662
CL -50pFtotalforDS3660
H
FIGURE 8. Roceiver Propagation Delay tpLHIDI and tPHLIDI
+5.GV
Vlo---~~-~~
-o-~
V2o---+....
':'"
':'"
VI
V2
51
52
CL
tpLO{SI
100mV
GNO
Closed
Closed
15pF
tpOL(S)
l00mV
GNO
Closed
Open
50pF
tPHOtsl
GNO
100mV
Closed
Closed
15 pF
tpOH(SI
GNO
l00mV
Open
Closed
50pF
Ci... includes jig and probe capacitance.
EIN waveform characteristics: tTLH and tTHL S""O ns
measured 10% to 90%.
'0
PRR = 1.0 MHz
Note: Datput of ChMneI Bshown uMet test,
ot/uIr chuneb ~n tided Jimiltrty.
Duty Cycle ::: 50%
tPLolSI
'0"
'0
:~j;:.VOL +O.5Y
tPHolSI
3"~""
'V~o",
V. .
""'.6V
'0
vOH-a.5v
Yo,
~t.5V
tPOLISI
E"
3'~v=14:"" 100,.
tPOHISI
Eo.
5.DV-VD,
Eo
V~
________
1.IiV
~
_ _ __
.
'0
,.V\""
v::~--=t~
1.5Y
_IV
FIGURE 9. Strobe Propagation Delay Times tpLOISI. tpOLISI. tpHOISI and tPOHISI
3·13
N
Ln
CD
ac test circuits and switching time waveforms (con't)
(V)
+5.0V
CIJ
C
oLn
'_ov~
+100mVo----....--o-~
50"
ov
'90
CD
(V)
CIJ
C
Eo
EON
.
':5 C·
1.5V
Voc
15pF
1'(TOTAll
Note: EIN waveform char8l;teristics:
tTLH and tTHl $ 10 IlS ml:!asllr~d 10%1090%
PRR=1.0MHz
Duty Cycle = 500 os
Not&: Output !If Channel 8 shown IInder test,
other channelsare tested similady,
FIGURE 10. Strobe Propagation Delay tplH(S) and tpHL(S)
schematic diagrams
OS3650
OUTPUT
INPUT
Co---t---'
t--o GND
t - - - + -.....
v" o--~>-----+--~--~----'
"-1----<> STROBE
1/4 OF CIRCUIT SHOWN
OS3652
V--t--oOOUTPUT
t---+--t---<>GND
STROBE
3·14
c
~
Line Drivers/Receivers
!!i
en
.r:a
o
......
crJ)
NAnONAL
CO
en
.r:a
057640/058640 quad NOR unified bus receiver
general description
features
The OS7640 and OS8640 are quad 2-input receivers
designed for use in bus organ ized data transmission
systems interconnected by terminated 120[2 impedance
lines_ The external termination is intended to be 180[2
resistor from the bus to the +5V logic supply together
with a 390[2 resistor from the bus to ground. The design
employs a built-in input threshold providing substantial
noise immunity. Low input current allows up to 27
driver/receiver pairs to utilize a common bus. This
receiver has been specifically configured to replace the
SP380 gate pin-for-pin.
•
•
•
•
•
•
•
o
Plug-in replacement for SP380 gate
Low input current with normal Vee or Vee ~ OV
(301lA typ)
High noise immunity (l.lV typ)
Temperature-insensitive input thresholds track bus
logic levels
OTL/TTL compatible output
Matched, optimized noise immunity for "1" and "0"
levels
High speed (19 ns typ)
connection diagram
Dual·1 n-Line Package
14
GND
OUT 2
OUT 1
IN lA
IN 18
IN 2A
IN 26
TOPVIEW
Order Number DS7640J, DS8640J
DS8640N or DS7640W
typical application
120n Unified Data Bus
+5V
+5V
~: h'>- /4- '- - - I
I OS8838
-=
I
I
I
L_
18.
>---...-----1
>-----.--
-"I
>----<11>-----1
I
I
I
39.
-=
I
_.J
3·15
absolu.te maximum ratings
Supply Voltage
Input Voltage
operating conditio,ns
(Note 1)
Supply Voltage (VCC)
DS7640
DS8640
7.0V
5.5V
600mW
-65°C to +150°C
300°C
Power Dissipation
Storage Temperature Range
l.ead Temperature (Soldering, 10 seconds)
Temperature (T A)
DS7640
DS8640
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
-55
0
+125
+70
°c
°c
electrical characteristics
The following apply for V MIN
<:; Vee <:; V MAX , T MIN <:; T A <:; T;"'AX, unless otherwise specified
PARAMETER
V'H
V'l
CONDITIONS
High Level Input Threshold
DS7640
VOUT=VOL
OS8640
Low Level Input Threshold
VOUT=VOH
ItHMaximum Input Current
V'N = 4V
-
MIN
-
TVP
MAX
UNITS
1.80
1.50
V
1.70
1.50
V
DS7640
1.50
1.20
V
OS8640
1.50
1.30
V
Vee::::: V MAX
30
80
Vee = OV
1.0
50
IlA
1.0
50
IlA
0.25
0.4
V
-55
mA
40
rnA
MAX
UNITS
= V MAX
Maximum Input Current
V'N = O.4V, Vee
V OH
Output Voltage
IOH = -400IlA, V'N = V'l
Val
Output Voltage
10L = 16 mA, V'N - V'H
los
Output Short Circuit Current
V'N = 0.5V, Vas = OV, Vee = V MAX , (Note 4)
Icc
Power Supply Current
V'N = 4V, (Per Package)
I'L
(Notes 2 and 3)
IlA
V
2.4
-18
25
switching characteristics
PARAMETER
tpd
Propagation Delays
MIN
TVP
Input to Logie "1" Output
10
23
35
ns
Input to Logic "0" Output
10
15
30
ns
CONDITIONS
(Notes 5 and 6)
Note1: "Absolute Maximum Ratings" are those values beyond which the safety of tl)e device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides cqnditions for actual device operation.
Not. 2: Unless otherwise specified minImax limits apply across the -55°C to +125°C temperature range for the 057646 and across the QOCte
+70°C range for the OS8640. All typical values are for TA = 25°C and VCC = 5V.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: Fan-out of 10 load, CLOAD = 15 pF total, measured from VIN = 1.5V to VOUT = 1.5V, VIN = OV to 3V pulse.
Note 6: Apply for VCC = 5V, TA = 25°C.
3·16
~
Line Drivers/Receivers
NAnONAL
057641/058641 quad unified bus transceiver
general description
features
The DS7641 and DS8641 are quad high speed drivers/
receivers designed for use in bus organized data transmission systems interconnected by terminated 120n
impedance lines. The external termination is intended to
be a 180n resistor from the bus to the +5V logic supply
together with a 390n resistor from the bus to ground.
The bus can be terminated at one or both ends. Low bus
pin turrent allows up to 27 driver/receiver pairs to
utilize a common bus. The bus loading is unchanged
when Vee = OV. The receivers incorporate tight thresholds for better bus noise immunity. One two·input NOR
gate is included to disable all drivers in a package
simultaneously.
• 4 separate driver/receiver pairs per package
• Guaranteed minimum bus noise immunity of O.6V,
1.1Vtyp
• Temperature insensitive receiver thresholds track bus
logic levels
• 30llA typical bus terminal current with normal Vee
or with Vee = OV
• Open collector driver output allows wire-OR
connection
• High speed
• Series 74 TTL compatible driver and disable inputs
and receiver outputs
connection diagram
Dual-in-line and Flat Package
BUS1
IN 1
OUT 1
BUS2
IN2
OUT 2 DISABLE A
10
11
BUS 3
IN J
OUT 3
BUS 4
IN 4
OUT 4
I.
DISABLE B GNO
TOP VIEW
Order Number DS7641J, DS8641J
or DS8641N
typical application
+5V
1.s~-f
0
':"
120n Unified Data Bus
"V
1I Irii'--1I
0'"'41
.
I
I
111,
n
I I
I I
I I
I
I
I
IiM2E!...f-J L ____ J
3·17
absolute maximum ratings
operating conditions
(Note 1)
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
\
7V
5.5V
600mW
-£5°C to +150°C
300°C
Supply Voltage
Input and Output Voltage
Power Dissipation
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
Supply Voltage, (VCC)
D87641
DS8641
Temperature Range, (TA)
DS7641
DS8641
-55
°c
°c
+125
+70
a
electrical characteristics
The following apply for V MIN ::: Vee::: V MAX , T MIN::: T A::: T MAX unless otherwise specified (Notes 2 and 3)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DRIVER AND DISABLE INPUTS
V'H
Logical "1" Input Voltage
V'l
Logical "0" Input Voltage
2.0
V
0.8
V
I,
Logical "1" Input Current
V'N o5.5V
1
I'H
Logical 1/1" Input Current
V'N o2.4V
40
I'A
I'l
Logical "0" Input Current
V'N""OAV
-1.6
mA
VeL.
Input Diode Clamp Voltage
-1.5
V
I DIS =-12mA, liN
=-~12
-1
mA, teus """ -12 rnA,
mA
TA =- 25°C
DRIVER OUTPUT/RECEIVER INPUT
VOLB
Low Level Bus Voltage
VD'S oO.8V, V'N °2V, Isus =-50mA
0.4
0.7
V
I'HB
Maximum Bus Current
Y'N =O.8V, Vsus =4V,
30
100
I'A
I'LS
Maximum Bus Current
Y'N = O.SV, Vsus == 4V, Vee"" OV
2
100
I'A
V'H
High Level Receiver Threshold
V'l
V ,NO
Low Level Receiver Threshold
VCC=VMAX
O.8V, VOL 016 mA
:=
V'ND oO.8V, V OH 0 -4001'A
DS7641
1.80
1.50
V
DS8641
1.70
1.50
V
DS7641
1.50
1.20
V
DS8641
1.50
1.30
V
0.25
0.4
V
-55
mA
50
70
mA
TYP
MAX
UNITS
19
30
ns
15
23
ns
17
25
ns
9
15
ns
20
30
ns
18
30
ns
RECEIVER OUTPUT
V OH
Logical "1" Output Voltage
V'N oO.8V, V BUS oO.5V, 10H o-4001'A
VOL
Logical "0" Output Voltage
V'N oO.8V, VB US = 4V,
los
Output Short Circuit Current
V 01S
Icc
Supply Current
V 01S
""
O.8V, V ,N
;;;:.
tOL ""
O.8V, V BUS
;;;:'
O.5V, V.os == OV,
V
2.4
16mA
-18
Vee:= V MAX , (Note 4)
:::
OV, V JN == 2V. (Per Package)
switching ch aracteristics
PARAMETER
tpd
CONDITIONS
MIN
Propagation Delays (Note 7)
Disable to Bus "1"
Disable to Bus "0"
Driver Input to Bus 1/1"
(Note 5)
Driver Input to Bus "0"
Bus to Logical "1" Receiver
Output
Bus to Logical "0" Receiver
Output
(Note 6)
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply
that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the --55Q C to +125°C temperature range for the D87641 and across the oOe to
+ 70°C range for the OS8641. All typical values are for TAo 25°C and V CC = 5V.
Note 3: All currents into device pins shown as positive, out o(device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: 911"1 from bus pin to VCC and 20051 from bus pin to ground. CLOAO ~ 15 pF total. Measured from VIN 0 1.5V to VSUS= 1.5V,
VI N = OV to 3V pulse.
Note 6: Fan·out Df 10 load, CLOAD 0 15 pF total. Me.asured from VIlli = 1.5V to VOUT 0 1.5V, VIN 0 OV to 3V pulse.
Note 7: The following apply for
3·18
Vee
=:0
5V, TA
=
25Q C unless otherwise spe'cified.
~
Line Drivers/Receivers
NAll0NAL
058642 quad transceiver
general description
features
The DS8642 is a quad transceiver designed for bus
organized data transmission systems terminated by 50n
impedance. The bus can be terminated at one or both
ends. It has four bus drivers with a common strobe
gate and four bus receivers. Bus driver outputs can be
"OR-tied" with up to 19 other drivers and with up to
20 bus receiver loads. The bus loading is 2k when
• 100 mA Drive Capability
• Four separate driver/receiver pairs
• Open collector driver output allows wire-OR connection
• 50n line termination
• Completely TTL compatible on driver and disable
inputs, and receiver outputs
Vee = OV.
connection diagram
Vee
STROBE
OUTo
1No
OUTe
INc
BUSe
BUSo
DUl A
INA
OUTe
INa
BUSe
BUSA
GND
GND
TOP VIEW
Order Number DS8642J
or DS8642N
3-19
abs.olute·· maximum ratings
operating conditions
(Note 1)
MIN
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Power Dissipation
Lead Temperature (Soldering, 10 seconds)
electrical characteristics
7V
5.5V
5.5V
-65°e to +150o e
600mW
3000 e
Supply Voltage, Vee
4.75
Temperature, T A
0
MAX
f"
UNITS
5.25
V
+70
°e
MAX
UNITS
(Notes 2 and 3)
PARAMETER
MIN·
CONDITIONS
TYP
DISABLE/DRIVER INPUT
Logical "I" Input Voltage
Vce = Min
V IL
Logical "0" Input Voltage
Vee = Min·
I'L
Logical "0" Input Current
Vee = Max, V'N = O.4V
I'H
Logical "I" I nput Current
V'H
V eD
Vee = Max
Input Clamp Voltage
2
V
-0.9
l V'N = 2.4V
I V'N = 5.5V
-0.8
I'N =-12 mA
0.8
V
-1.6
mA
40
/lA
1
mA
-1.5
V
1.4
V
-1.5
V
RECEIVER INPUT/BUS OUtPUT
V'HB
Logical "I" Input Voltage
Vee = Max
3.1
V'LB
Logical "0" Input Voltage
Vee = Min
VeDB
Input Clamp Diode
liN = -50 mA
I'HB
Logical "I" Input Current
Vee = Max, V'NB = Vee
I'LB
Logical "0" I nput Current
Vee = Max, V'N = O.4V
VOLB
Logical "0" Output Voltage
Vee = Min, lOUT = 100 mA
10L
Logical "0" Output Current
Vee = Min, VOL = 0.8V
10HB
Power "OFF" Bus Current
Vee = OV, V'NB = 5.25V
V
-1.0
180
450
/lA
-40
0.4
0.8
1.7
2.65
/lA
V
100
mA
mA
RECEIVER OUTPUT
Logical "I" Output Voltage
Vee = Min, lOUT = -1 mA
10H
Logical "I" Output Current
Vee = Min, V OUT = 5.5V
los
Output Short Circuit Current
Vee = Min, V OUT = OV, (Note 4
VOL
Logical "0" Output Voltage
Vee = Min, lOUT
Ice
Supply Current
V OH
I
Vee = Max
2.4
3.2
-10
-28
V
100
= 16 mA
0.3
I
l-
49
/lA
-55
mA
0.45
I
64
V
I
mA
Note.1: .,Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits aPl?ly across "the O°C to +70°C range for the OS8642. All typicals are given for Vee == 5V and
TA=25°e.
Note 3: All currents into device pins shown as positive, out of device pins as negative. all voltages referenced to ground unless otherwise noted.
All values shown as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.
3·20
C
en
switching characteristics
co
0)
.j::o
CONDITIONS
TYP
MAX
(Figure 1)
34
50
ns
(Figure 1)
25
50
ns
(Figure 1)
38
55
ns
(Figure 1)
25
55
ns
PARAMETER
tpdO
Propagation Delay to a Logical "0"
MIN
UNITS
From Data I nput to Receiver Output
tpd1
Propagation Delay to a Logical" 1"
From Data I nput to Receiver Output
tpdO
Propagation Delay to a Logical "0"
From Strobe I nput to Receiver
Output
tpd1
Propagation Delay to a Logical "1"
From Strobe Input to Receiver
Output
typical performance characteristics
Receiver ON Impedance
400
Receiver OFF l mpedance
Vee'" 5V
TA
=
I
I
300
;;;
1.5
;;;
.sz
.3
2
200
-
100
_
vee'" OV
TA "'25"C
2.0
25"C
f2
3
i/
1.0
V~
V
0.5
4
2
VBUS (V)
3
4
Vsus (V)
ac test circuit and switching time waveforms
3V
1.. 5V -'
DATA INPUT
+5V
(
STROBEC>--1~O ~O_lO/'-I"
*
,
OATA INPUTo-....- - - - - '
)---4....
OV
\
- 1.5f
tpd1
VaH
1
">o-_..._ORECEIVER
OUTPUT
1"'" r"
RECEIVER
OUTPUT
1.5V
OV
K:-
-~~
1.5V
FIGURE 1.
f = 5 MHz
Pulse Width'" 100 ns
3-21
N
o
N
CO
CO
UJ
~
o
.......
o
N
Line Drivers/Receivers
NAll0NAL
~o
057820/058820 dual line receiver
general description
The DS7820, specified from -55°Cto+125°C, and
the DS8820, specified from O°C to +70°C, are
digital line receivers with two completely independent units fabricated on a single silicon chip.
Intended for use with digital systems connected
by twisted pair lines, they have a differential input
designed to reject large common mode signals while
responding to small differential signals. The output
is directly compatible with RTL, OTL or TTL
integrated circuits.
• Each channel can be strobed independently
• High input resistance
• Fanout of two with either OTL or TTL
integrated circuits
The response time can be controlled with an external capacitor to eliminate noise spikes, and the
output state is determined for open inputs. Termination resistors for the twisted pair line are
also included in the circuit. Both the OS7820 and
the OS8B20 are specified, worst case, over their
full operating temperature range, for ±10-percent
supply voltage variations and over the entire input
voltage range.
features
• Operation from a single +5V logic supply
• Input voltage range of ±15V
schematic and connection diagrams
Dual·1 n-line and Flat Package
RU'ONUTIME
CONTROL
"
'"~
'"
~
"'"
AU
.,
~
.,
R9
"
NON·INVERTING
INPUT
-~
'"~
~.,
R1
-
'"
"
RfSl'OHSETtM(
An
'"
'"
Q2
ourpUT-=-~-l
RESPONSE TIME
OUTPUT
'---l---''- ouTPUT
...
"
....0
AS
'"
'"
TOP VIEW
Order Number DS7820J or DS8820J
Order Number DS8820N
Order Number DS7820W or DS8820W
AU
"
R1
'"
STRon
typical application
mSTfD PAIR LINE
OUTPUT
tExactvaluedependsonlinelength.
*Optionaltotontrol response time,
STROBE
3-22
TERMINATION
STROBE
.'::1-
""'
"'
""
~"
"
INPUT
.... 010
GROUND
RJ
INVERTING
INP'UT
UK
AU
RI
nRMINATrON
'"
"
absolute maximum ratings
Supply Voltage
B.OV
±20V
±20V
B.OV
25 rnA
600 mW
Input Voltage
Differential Input Voltage
Strobe Voltage
Output Sink Current
Power Dissipation
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
Temperature ITAI
DS7820
DS8820
-<55
0
+125
+70
Input Threshold Voltage
CONDITIONS
MIN
TYP
MAX
UNITS
V'N = 0
-0.5
0
0.5
V
-15V ~ V'N ~ 15V
-1.0
0
1.0
V
5.5
V
High Output Level
lOUT ~ 0.2 mA
2.5
VOL
Low Output Level
IS'NK ~ 3.5 mA
0
R,-
I nverting I nput Resistance
R,+
Non·1 nverting I nput Resistance
RT
Line Termination Resistance
T A = 25°C
tr
Response Time
CaE LAY =0
40
ns
CDELAY = 100 pF
150
ns
VSTROBE = O.4V
1.0
V OH
1sT
Strobe Current
0.4
3.6
5.0
1.8
2.5
120
170
Icc
I'N+
Power Supply Current
Non·1 nverting I nput Current
I'N-
~
1.4
rnA
-5.0
pA
V'N = 15V
3.2
6.0
rnA
V'N =0
5.8
10.2
mA
V'N = -15V
8.3
15.0
mA
5.0
7.0
mA
V ,N = 15V
V'N = 0
V ,N =-15V
I nverting I nput Current
V
k~
VSTROBE = 5.5V
-1.6
-1.0
mA
-9.8
-7.0
rnA
V'N = 15V
3.0
V'N =0
0
-4.2
V'N =-15V
-3.0
4.2
mA
-0.5
mA
mA
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: These specifications apply for 4.5V ~ Vee ~ 5.5V, -15V ~ VeM ~ 15V and -<55"C ~ T A ~ +125"e for the DS7820 or O°C ~ T A ~
~70°C for the OS8820 unless otherwise specified; typical values given are for VCJ::.
=
5.0V, TA ::: 25°C and VCNI
=0
o
en
o
k~
250
........
CO
CO
N
"e
"e
(Notes 2 and 3)
PARAMETER
CO
N
o
Supply Voltage IV eel
DS7820
DS8820
300"e
Lead Temperature (Soldering, 10 sec)
V TH
MIN
-65°C to +150°C
Storage Temperature Range
electrical characteristics
o
en
-..J
operating conditions
(Note 1)
unless stated differently.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
Note 4: The specifications and curves given are for one side only. Therefore, the total package dissipation and supply currents will be double the
values given when both receivers are operated under identical conditions.
3·23
o
N
CO
typical performance characteristics
QO
tJ)
(Note 3)
C
.......
o
~
tJ)
0.3
I
~
C
~
..'"'"
0.2
!:.;
:>
0.1
,I
..
'"
~ 0.2
C
•$~ I
~
~
~ -0.1
TA ::: 2S"C
0.4
I J
....::u,·o
.•"1
-....:.;ou'·35
r:--r-:.."'~
00"6.2.,
<4
ffi
::: -0.2
:>
........
~
~
- i-
I
'
n
+1·~'·0.l"4
;::: 1-111OlJ"''''1.5V
-
~
'"
.
-0.3
4
4.5
5
5.5
-20
-10
SUPPLY VOLTAGE IV)
~
VCC~
w
TA = 25°C
co
f
-2
!!t -4
\
Cd,ll.,. -100 pF
/'
I
.....
;'"
~
"\
-0.4
±
180
w
ili
180
"- :- i-"'"" . /
170
'"
160
I
I
0
25
50
75 100 125
150
-75 -50 -25
TEMPERATURE I·C)
300
........
Vcc' 5.0V
OUTPUT LOW
I I vee'" 5V
I
!
\\
01l1"1>1/}-
........
..,....;; lOll-r_
["...
011""11,.
-
_~'
r-.;,oI""'oI'r_ ~
K
-2
-20
h
:\
.........
["...
125"C
\
......
o
-10
10
INPUT VOLTAGE IV)
20
0
25
50
75 100 125
TEMPERATURE (·C)
Internal Power Dissipation
Positive Supply Current
10
0.4
L
:g
'"'z
-75 -50 -25
0.2
200
0.2
0.8
-0.2
Termination Resistance
OUTPUTLOW- !--!--
0.6
r-
DIFFERENTIAL INPUT VOLTAGE (V)
'"
o
0.4
25°C
'Ii
20
Vcc - 5.0V
0.1
"'""
l·'.. ,·
In
I
I
~
.If
10
f--
TIME ("s)
3-24
jo4
I
I
.
125·C-
,7/ r-
~
:>
\
Cd"I"'=O,
o -=~
0.2
o
0
OUTPUT HI1GH
...
II
55·C,
Output Voltage Levels
;'"
:>
,..--.
1·5
,
~
I~'
INPUT VOLTAGE IV)
Response Time
..
• loU7 "'3
I
I
I I
O2
.
I
~
-r- ;.:::::
Vo~
~-O.4
5
Vee::: 5Y
-FAN OUT-2
I
w
II
~
z:
TA ",2S"C
........ ~>.Il
Transfer Function
Common Mode Rejection
SupplV Voltage Sensitivity
N
-20
-10
, ~-i f
~
25"C
10
INPUT VOLTAGE IV)
20
c
~
en
OJ
Line Drivers/Receivers
N
o
~
c
en
NATlONAL
00
00
N
DS7820A/DS8820A dual line receiver
o
»
general description
The DS7820A and the DS8820A are improved
performance digital line receivers with two completely independent units fabricated on a single
silicon chip. Intended for use with digital systems
connected by twisted pair lines, they have a differ·
ential input designed to reject large common mode
signals while responding to small differential signals. The output is directly compatible with RTL,
DTL or TTL integrated circuits_ Some important
design features include:
•
•
Input voltage range of ± 15V
•
Strobe low forces output to "1" state
•
High input resistance
•
Outputs can be wire OR'ed
•
Series 54174 compatible
The response time can be controlled with an external capacitor to reject input noise spikes. The
output state is a logic "1" for both inputs open.
Termination resistors for the twisted pair line are
also included in the circuit. Both the DS7820A
and the DS8820A are specified, worst case, over
their full operating temperature range (_55°C
to 125°e and oDe to 70°C respectively), over the
entire input voltage range, for ±10% supply volt-
Operation from a single +5V logic supply
•
Fanout of ten with either DTL or TTL integrated circuits
age variations.
schematic and connection diagrams
Dual-in-Line Package
RESPONSE TIME
CONTROL
.-----...- ....- - t -.....----..,-......r--"·
'"""
...'n
'"
,n
n
'"
. ~"
I~'
AD
'""
"..
.."
TERMINATION_
'""
INVERTING
INPUT
".
,.,"
"f"
."'
\2 TERMiNATiON
1.5k
""""
....,u
OUTPUT
Note: Pin 7 connected to bottom of cavity package.
',.," '"
.."
"''"'
Order Number OS7820AJ or DS8820AJ
Order Number DS8820AN
Order Number DS7820AW or DS8820AW
Note: Schematic shows one·halfofunit.
H
typical applications
Single Ended (EIA-RS232C) Receiver with Hysteresis
Differential Line Driver and Receiver
*Optionlll to control response time.
3-25
«o
N
00
00
en
c
.......
«o
N
~
C
absolute maximum ratings
(Note 1)
operating conditions
Supply Voltage
Common·Mode Voltage
B.OV
±20V
±20V
8.0V
50 rnA
600rilW
-65°C to 150°C
300°C
Supply Voltage (V CC)
DS7820A
DS8820A
Differential Input Voltage
Strobe Voltage
Output Sink Current
Power Dissipation
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
electrical characteristics
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
-55
0
+125
+70
°c
°c
UNITS
(Notes 2, 3, 4 and 5)
PARAMETER
V TH
Temperature (T A)
DS7820A
DS8820A
MIN
CONDITIONS
Differential Threshold Voltage
louT = -400I'A.
2: 2.5V
V OUT
TYP
MAX
-3V < V eM < +3V
MIN
0.06
0.5
-15V
c
~
c
gi='"
;;;;;;;:: r--
0.1
VOUT
-
i
TA = 25°C
IJ
0.2
I Ve\OV
2.5V, lOUT'" -400;;A
'"
;;;
0.2
>
VOUT
:::
;
IO~T ::: 16 rnA
1
DAV,
-0.1
~
-0.2
~
'"
-0.2
is
;
5.0
4.5
6.0
5.5
c
-0.4
--
FANOUT·l0
'"
--..
:;.. ;...-
"'"
:;;
180
~
~soc- -
LI
1 L
190
u
";::c
'"z
;;;
-5SOC_
I I
I I I
~
.
--~
-0.2
0.4
0.2
~ffi
+10
",,)-
~ (0/1- r--r-I 'X
I- ~
~O")-"" I I'.
~
'11" -r--,--'
""
1'-...
I
J
o
-20
>
~
;::
'"
38
34
i
C
30
26
I'.
r- TO "0" OUTPUT
.... :>IL
22
"
~
0:
3:
I'-.,
.......
A
V
18
-15 -50 -25
0
--
TA rC)
~
;;
-INPUT.> i""':
-2
-4
0
25
50
L
200
~~
"
~
f--+INPUT
~
.~
~OC
~
1/.'
'/
.~
10
::-
c
>
>-
"
"
r- Vee' 5V
I- --
;:::,;
I
I
1_
0.3
~
c
0.2
20
10
I 10(1
-15 -50 -25
22
'"c
18
w
15 100 125
/
30
~
STROBE TO 1"1" JUTPLT
\/
-/- -
-
1/
/
......
"\
14 f - r-- ~STR08E TO "0'.' OUTPUT
10
-15 -50 -25
0
25
I
50
15 100 125
Noise Rejection
1000
Vee:< 5V
26
~
TA I'C)
34
>
;::
i.-:"~. OU1 ?U1 ,
~oG't~
,~ "'~- I--
;;;;;<"
0.1
-10
1 l
I
LOGICAL "1" OUTPUT,
I-lOUT" -400 $.LA -
>-
~.
.
'"'"~
Strobe Delays
~
20
Output Voltage Levels
5
w
12rC
I
-10
INPUT VOLTAGE IWITH RESPECT TO GROUND) IV)
OUTPUT LOW
100
1-""'"1
A
-6
-10
-20
15 100 125
...... i"'"
...,~
COMMON·MODE VOLTAGE IV)
DIFFERENTIAL
TO ''1'' 0 UTPUT
50
0:
0:
J
-20
:;;
25
"
"u
./
o
+20
/
I
I
.s
I
ee .15.0V
.s
"c
~
~
./
;"
W
./
300
g
I-dIFFE~ENtIAL
Input Characteristics
TA I'C)
,
Vee = 5V
....-
TA rC)
>-
~
+10
-10
~
-150 L-...l--'-_'-....L..---'_.l--'---I
-75 -50 -25 0 25 50 75 100 125
-8
Differential Input Delays
]
~
C
./
160
COMMON·MODE VOLTAGE IV)
42
+20
Internal Power Dissipation
0""
I"
-50
;;i -1001-+--+-+-
-15 -50 -25
I I Vee' 5~ _
~~TA'25OC_
.......
~
TA=25°C
110
Power Supply Current
l""-
~
c
~
DIFFERENTIAL INPUT VOLTAGE IV)
10
o
»
Vee'" 5V
-w
N
1-+--+-',
50
>
0:
COMMON·MOOE VOLTAGE IV)
~
I I
-0.4
~
100 '--~"""-r--'---.-~~-'-'
Termination Resistance
-\)C
OV
• a.'V~il-;;-
-10
-20
Transfer Function
Vee::: 5.nV
'Jou'-
.,,\()({I~~
f-
SUPPLY VOLTAGE IV)
VCM
.s
_..4~a"~L
~
!
- r-- _2.~V. Iou' 'Jo\.l'1-
c
~
;
'"~
CJ)
00
00
Temperature Sensitivity
TA '" 25°C
Vee'" 5V
0.4
c
I
<:c
Common-Mode Voltage
Sensitivity
25
50
TA I'C)
75 100 125
:~ee· 5V
:~~
]
'">-c
·F':.;2:.5VPI ...
/
lO
w
~w
100
~
C
x"
''""
10
10
100
1000
10,000
CRESPONSE TIME CONTROL (pF)
3-27
2.5V.
V 01FF
""
-il.36
=OV,
V
-il.5
2.5
lOUT"" 4 rnA,
V
kn
n
5
Input Balance
UNITS
-40
(Note 4)
V
/lA
rnA
mA
switching characteristics
CONDITIONS
PARAMETER
tpdO(O)
tpd1(OJ
tpdO 5l
t pd 1(S)
Differential Input to "0"
Output
Differential Input to "1"
Output
Strobe Input to "0" Output
Strobe Input to "1" Output
MIN
TYP
MAX
UNITS
Vce - 5V. T A = 25·C
30
ns
Vcc = 5V. TA = 25·A
20
n,
Vcc = 5V. T A = 25·C
11
ns
Vcc=5V. T A =25·C
10
ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the -55°'C to +12~C temperature range for the DS78LS20 and across the O°C to
+70·C range for the DS88LS20. All typical values are for TA = 25·C, VCC = 5V and VCM = OV.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: The specifications given are for one side only. Therefore, the total package dissipation and supply currents will be double the values given
when both receivers are operated under identical conditions.
Note 6: Refer to EIA·RS·422 for exact condition·s.
3·30
c
~
~
Line Drivers /Receivers
N
N
.......
C
CJ)
NA110NAL
CO
CO
N
N
OS7822/0S8822 dual line receiver
general description
high state independent of the information being
received at 'he input.
The OS7822/0S8822 is a dual inverting line
receiver which meets the requirements of EIA
specification RS232 Revision B. The device con·
tains both receivers on a single monolithic silicon
chip. The receivers share common power supply
and ground connections, otherwise their operation
is fully independent.
The output of the OS7822/0S8822 is completely
compatible with 5V OTL and TTL logic families.
The OS7822 is specified for operation over the
-55°C to +125°C military temperature range. The
OS80822 is specified for operation over the O°C to
+70 C temperature range.
In addition to meeting the requirements of RS232,
the OS7822/0S8822 also has independent strobe
inputs which allow the receiver to be placed in the
connection diagram
Dual-In-line Package
vee
INPUT
STROBE
INPUT
STROBE
OUTPUT
OUTPUT
GNO
*Make no connection to thest pins.
-For operation requiring "Muk Hmd" with the input open connect a 470n
resistors from each oftbese pins to ground.
Order Number OS7822J
orOS8822N
typical connection
TWISTED PAIR LINE
*For Mark Hold R1
=
470n. otherwise connect pin 3 to ground.
3-31
N
N
co
co
absolute maximum ratings
operating conditions
(Note 1)
en
Q
.......
N
N
~
Q
Supply Voltage
Input Voltage
Stmbe Voltage
Output Sink Current
8,OV
±30V
8.0V
Supply Voltage (Vee)
OS7822
058822
25 mA
600 mW
057822 _55°C to +125°e
aOe to 70°C
058822
Storage Temperature Range
_65°C to +150 o e
Lead Temperature (Soldering, 10 sec)
300°C
Temperature (TA)
OS7822
058822
Power Dissipation
Operating Temperature Range
electrical characteristics
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
-55
0
+125
+70
°e
°e
(Notes 2 and 3)
,
PARAMETER
CONDITIONS
V TH -
Negative Input Threshold Voltage
VOUT:O: 2.5V
V TH +
Positive Input Threshold Voltage
V OUT ::;: O.4V, (Note 41
R'N
Input Resistance
liN
Input Current
MIN
3.0
V ,N = 25V
3.57
V ,N =OV
V ,N = -25V
Via
Open Circuit Input Voltage
V ,N = OV
V OH
Logical "1" Output Voltage
lOUT::;: -0.2 rnA
VOL
Logical "0" Output Voltage
lOUT = 3.5 rnA
1ST
Strobe Current
VSTROBE = O.4V
lee
Power Supply Current (Both Receivers)
-25V::;: V ,N ::;: 25V
t,
Response Time, t, or t2
T A = 25°C, Vee = 5.DV,
V STROBE = 5.5V
TYP
MAX
-2.0
V
2.0
V
5.0
7.0
kn
5
8.33
rnA
0
-8.33
UNITS
-5
0.03
rnA
-3.57
0.5
rnA
V
V
2.5
1.0
-5.0IlA
65
0.4
V
1.4
rnA
-1.0 mA
24.0
mA
125
ns
Input Ramp Rate::;: 10 ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be'guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated a1 these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Not. 2: MinImax limits apply across the guaranteed temperature range of--55°C to +125°e for the OS7822 and oOe to +70o e for the OS8822
unless otherwise specified. Likewise the limits apply across the guaranteed Vec range of 4.5V to 5.5V for the 057822 and 4.75V to 5.25V for
the 058822 unless otherwise specified. Typical values are given for Vee = 5.0V and TA = 25°C.
.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
Note 4: Since the EIA RS-232 specification requires the threshold to be between "'-3V and +3V, the immunity limits shown here guarantee 1V
additional noise immunity.
3-32
c
~
typical performance characteristics
00
N
N
.......
C
Threshold Voltage vs Supplv Voltage
650
;;
5SO
'"
500
=
450
~i=
400
C>
>
~
10.000
Vee
600
.§
~
;::
~
lOO
;S
200
150
100
,.
~
l50
::l 250
.
100
~
lOO
SO
4.5
5.0
5.5
10
6.0
Threshold Vol'tage vs Supply Voltage
0.1
I-
10.000
I-+--f"""''':
-0.2
f-+--+---1f--t--+--t-+---I
,.
~
,'"
"j
-0.4
125°C-
25 & r-
rn
0
0.2
-0.2
0.4
OIFFERENTIAL INPUT VOLTAGE IV)
SUPPl V VOLTAGE IV)
II'
I"
0 +5 +10 +15 +20 +25
~
..
~
-t±
Vee - S.DV
!:;
II
-O.l '-----'-----'-_1-.-"----'-_'----'---'
4
5.5
4.5
V
OUTPUT HiGH
I~
1-+-t-+--+-I-=J"""'Id
r.-....
J
Output Voltage Lavels
.... 10-"_ l -
55°C
-0.1
"
t'..
11
INPUT VOLTAGE IV)
Transfer Function
-~~~~~~.2
I
I
~
'"
~
'"
~
1.000
'\
-25 -20 -15 -10 -5
INPUT RAMP TIME (ns)
SUPPl V VOL TAGE IV)
~
100
~~~:~~:;'N
I\.
250
4.0
~ 50V~i±=
410n RESISTOR , _
CONNECTEO FROM
PIN3TO GROUNO -
z
C> l50
;::
~
00
00
N
N
TA = 25 C
~
.§ 400
:- 1,000
f/)
Internal Power Dissipation
Response Time vs Input Ramp Time
C>
'"
0.2
"
0.1
I-
I;'"
OUTPUT LOW- f-
o
-15
-
I
-25
0
25
TEMPERATURE
15
125
rc)
switching time waveforms
~2
5V
INPUT
OUTPUT
ac test circuit
5V
"
OUTPUT
INPUT
."
3·33
o
M
co
CO
tn
~
C
........
o
M
Line Drivers/Receivers
NAnONAL
re
tn
087830/088830 dual differential line driver
C
general description
The DS7830/DS8830 is a dual differential line
driver that also performs the dual four-input NAND
or dual four-input AND function.
normally associated with single-wire transmissions.
features
TTL (Transistor·Trans;"stor-Logic) mUltiple emitter
inputs allow this line driver to interface with standard TTL or DTL systems. The differential outputs
are balanced and are designed to drive long lengths
of coaxial cable, strip line, or twisted pair transmission lines with characteristic impedances of
50~ to 500~. The differential feature 'of the
output eliminates troublesome ground·loop errors
•
Single 5 volt power supply
•
Diode protected outputs for termination of
positive and negative voltage transients
•
Diode protected inputs to prevent line ringing
•
High Speed
•
Short Circuit Protection
schematic*and connection diagrams
Dual·' n-Line and Flat Package
"'-+-~-~~~PUT
AND
OUTPUT
NAND
OUTPUT
AND
NAND
GND
OUTPUT
OUTPUT
TOPV1EW
Order Number DS7830J or DS8830J
Order Num_ber DS8830N
Order Number DS7830W or DS88300
*2 PER PACKAGE.
typical application
Digital
Dat~
Transmission
TWISTEO PAIR LINE
OUTPUT
*Optionaltocontrolresponsetime.
STROBE
3-34
o
absolute maximum ratings
7.0V
5.5V
-6SoC to +150°C
3000 e
Vee
Input Voltage
Storage Temperature
Lead Temperature (Soldering, 10 sec)
Output Short Circuit Duration (125°C)
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
+125
+70
°e
°c
PARAMETER
Temperature (TAl
DS7830
DS8830
CONDITIONS
Logical "1" Input Voltage
V IL
Logical "0" I nput Voltage
V OH
Logical "1" Output Voltage
--55
0
VOL
Logical "0" Output Voltage
IIH
Logical" 1" I nput Current
MIN
TYP
MAX
00
00
W
o
V
0.8
= 0.8V
V IN
= 2.0V
V IN
lOUT
lOUT
lOUT
= --0.8 mA
= 40 mA
= 32 mA
= 40 mA
= 2.4V
V IN = 5.5V
V IN = O.4V
Vcc = 5.0V, T A = 125°C, (Note 4)
V IN = 5.0V, (Each Driver)
Isc
Output Short Circuit Current
Icc
Supply Current
V
2.4
V
1.8
3.3
V
0.2
0.4
V
0.22
0.5
V
V IN
Logical "0" I nput Current
120
IJ.A
2
mA
4.8
mA
100
120
mA
11
18
mA
TYP
MAX
UNITS
= 25°C, Vee = 5.0V,
= 15 pF, (Figure 1)
8
12
ns
11
18
ns
= 25°C, Vee = 5.0V,
= 15 pF, (Figure 11
8
12
ns
5
8
ns
12
16
ns
12
16
ns
40
switching characteristics
PARAMETER
CONDITIONS
Propagation Delay AN D Gate
tpdl
TA
CL
tpdO
Propagation Delay NAND Gate
tpd1
TA
CL
tpdO
Differential Delay
t,
MIN
Load, lOOn and 5000 pF,
(Figure 2)
Differential Delay
t2
Load, lOOn and 5000 pF,
(Figure 2)
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified minimax limits apply across the -55°C to +125°C temperature range for the 057830 and across the aoc to
+70oe range for the OS8830. Typical values are for TA = 25°e and Vee = 5.0V.
Note 3; All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.
l . ..
400
l
1NPUnO
_
$CI~
g
...
--'to
... ~
-l:lSr ~"
4
100
5000pF
V,
.V
VA -Va
SAME LOAD
FIGURE 1.
o
en
UNITS
2.0
lOUT
00
W
o
(Notes 2 and 3)
V IH
IlL
MIN
.......
Supply Voltage (Veel
DS7830
DS8830
1 second
electrica I cha racte ristics
~
operating conditions
(Note 1)
FIGURE 2.
3·35
typical performance. characteristics
Output High Voltage (Logical "'''I
VS Output Current
4.0
.......
..
~
'"
I
3.0
...... :---.
!:;
co
>
..J25"C
2.0
5
~
'"co
o
o
,
20
40
60
"c
15
ill
10
.",.
~
25
..
..
=
:;
..
i.."
~
I-
z
~
2
Output Low Voltage
ILogical "0"1 v. Output Current
160 1&0 140 120 100
10 -
-
-
J
IIII-
-
2l1li
1/
,
-55'cl
1,..0-
~
"
-
25'V"
J
II-
~ ~25'
I'-
100
0.1 2
511.0 2
5110.020.05110
20
40 60
10 lDO 12. 140
OUTPUT SINK CURRENT (mAl'
DATA INPUT FREQUENCY (MHzl
ac test circuit
,,
I"'"-----_-~-=.~':""----,
,
,,
Vee I
lIZ OIlUIIDIIUD
v.
.. I
v._~--,
"
switching time waveforms
. ;r... .
u\: ..
~
tv
3·36
~I
~tTEED
LDGI~4+
INPUT VOLTAGE
r-
OUTPUT CURRENT (mAl
....
~NANDIGATE
I I
TEMPERATURE rCI
Power DiSSipation (No Loadl
VI Data Input Frequency
~
"
,
15
·AN GATE~
TEMPERATURE (OCI
55'C +125'C '~
25'C
50
.... 1I::i!.
1.2
,t.o
-60 -25 025 60 15 101 US
·60 ·25 0 25 50 15 100 125
l1'-- ~ ......
200~"" I ' ~
LOAD .1.
I')c
......
\
\
9
_
~
"1,-!/Ot
.
=
I-
Differential Output Voltage
(IVAND - VNANDII
VS Differeritlal Output Current
son
~
~is
80· 100 120 140
GU~R~N!~~D
I Loblc!L i." r
INIUT VOLTAGE
;! 1.6 .I!!
S
~1I::i!.
> 1.4
.",.
OUTPUT SOURCE.. CURRUlT (mAl
LOAD I '
0m
..
~ 2.0
1.8
,
;::
'-55 C
1.0
20
J
~
Threshold Voltage V. Temparature
Delay V. Temperature
-
.
~
!
~ to-- ~12S-C
~
Diffe~ntial
V,,-v.
'
.
...,
.
~
Line Drivers/Receivers
NAnONAL
OS783110S8831, OS7832/0S8832 TRI-STATE® line driver
c
general description
~
• High impedance output state which allows
many outputs to be connected to a common
bus line_
Through simple logic control, the 057831/
058831, 057832/058832 can be used as either
a quad single-ended line driver or a dual differential
line driver_ They are specifically designed for
party line (bus-organized) systems_ The 057832/
058832 does not have the Vee clamp diodes
found on the 057831/058831.
CO
W
N'
.......
C
mode of operation
en
To operate as a quad single-ended line driver apply
logical "O"s to the Output Disable pins (to keep
the outputs in the normal low irnpedance mode)
and apply logical "0'" s to both Differential/
5ingle-ended Mode Control inputs. All four
channels will then operate independently and no
signal inversion will occur between inputs and
outputs.
To operate as a dual differential line driver apply
logical "O"s to the Output Disable pins and apply
at least one logical "1" to the Oifferential/5ingleended Mode Control inputs. The inputs to the A
channels should be connected together and the
inputs to the 8 channels should be connected toIn this mode the signals applied to the resulting
inputs will pass non-inverted on the A2, and 8 2 outputs and inverted on the Al and 8 I outputs_
The 057831 and 057832 are specified for operation over the -55°e to +125°e military temperature range_ The 058831 and 058832 are specified
for operation over the oOe to +70o e temperature
range_
features
• Series 54/74 compatible
• 17 ns propagation delay
.. Very low output impedance-high drive
capability
• 40 mA sink and source currents
• Gating control to allow either single-ended or
differential operation
CO
CO
W
N
When operating in a bus-organized system with
outputs tied directly to outputs of other
(continued)
connection and logic diagram
Dual-In-Line Package
"."QUTfUT
ENABU
OUTPUT
A2
INPUT
AI
OIJT1lUT
AI
INPUT
AI
DlfFERENTIAU
II.OLE·ENDED
MDOECOIITROL
Order Number DS7B31J, DSBB31J,
DS7B32J, DS8B32J, DSBB31N,
DSBB32N,DS7B31W,
orDS7832W
. roum;,
OUTPUT
B2
ENABLE
INPUT
12
OUTPUT IIII'UT DIFFEREITIALf GIIO
81
81
&eNGLE-EIOEo
MODE CONTROL
TOP VIEW
truth table
(5hown for A Channels Only)
"A" OUTPUT OISABLE
OIFFERENTIALI
SINGLE-ENOEO
MODE CONTROL
0
0
X
j
0
I
X
X
X
X
X
INPUT Al
OUTPUT Al
INPUTA2
Logical "," or
Logical "0"
Same as
InputAl
logical "1'· or
Logical "0"
Same as
Logical "," or
Logical "0"
Opposite of
InputA1
Logical "," or
Logical "0"
Same as
X
High
impedance
state
°VTPUTA2
InputA2
Input A2
High
X
impedance
state
X - Don't Care
3-31
N
('I)
absolute maximum ratings
,(Note 1)
operating conditions
en
Supply Volt8ge
I~put Voltage
Output Voltage
Storage Temperature Range
Lead Temperature ISoldering. 10 sec.1
Time that 2 bus-connected devices may
be in opposite low impedance states
simultaneously
7V
S.SV
S.SV
-6S·C to +150·C
300·C
Supply Voltage (V
OS7831, OS7832
088831.0S8832
co
co
Q
.......
~
~Q
.
M
cd
MIN
MAX
UNITS
4.5
5.5
5.25
V
V
+125
+70
·C
·C
4.75
Temperature (T A)
057831,OS7832
088831,058832
-05
0
co
('
electrica I characteristics
JNotes 2 and 3)
PARAMETER
CO
CO
en
Q
.......
M
MIN'
CONDITIONS
V'H
Logical "I" Input Voltage
Vee
II:
V,L
Logical "0" Input Voltage
Vee
= Min
VOH
Logical "1" Output Voltage
,10 =-40mA
057831.0S7832
10 =-2 mA
058831. 058832
VOL
Logical "0" Output Voltage
057831. 057832
Vee = Max
10 =, 40mA
lB
10 =-6.2 mA
2.4
0.29
1057831.057832. Y'N = 6.5V
1058831.058832. V'N = 2.4V
-1.0
I'L
Logical "0" Input Current
Vee = Max. Y'N = 0.4V
Output Disable Current
Vee = Max. Vo = 2.4V or 0.4V
-40
Ise
Output Short Circuit Current
Vee = Max. (Note 4)
-40
Icc
Supply Current
Vee = Max
Vell
Input Diode Clamp Voltage
Vee =S.OV. TA =2S·C.I ,N =-12mA
VelO
Output Diode Clamp Voltage
-100
65
I
lOUT = -12 mA
I'IOUT
a
12 mA
I
0578311058831
057832/058832
O.SO
0.40
0.50
0.40
V
V
V
V
1
40
mA
p.A
-1.6
mA
40
pA'
-120
mA
90
mA
-1.S
V
-1.S
V
Vee +1.5
I 057831{058831
V
V
V
V
V
2.9
10 = 32 mA
100
Vee = S~OV.
TA = 25'C
2.3
2.7
2.6
0.29
10 =40mA
UNITS
V
10 =32mA
058831. 058832
Logical "1" Input Current
1.8
2.4
10 =40mA
Vee = Min
I'H
MAX
0.8
Vee = Min
~
Q
TYP
2.0
Min
V
switching characteristics
PARAMETER
tpdO
CONDITIONS
MIN
TVP
MAX
UNITS
13
25
ns
Vee = 5.0V. TA = 25·C
13
25
ns
·Delay from Disable Inputs to High
Impedance State (from Logical "1"
Level)
Vee = S.OV. TA = 25·C
6
12
ns
Delay from Disable Inputs to High
Impedance State (from Logical "0"
level)
Vee = 5.0V. T A = 25·C
14
22
ns
Vce ~ S.OV. TA = 2S·C
14
22
ns
Vee =S.OV. TA =2S·C
18
27
ns
Propagation Delay to a Logical "0"
from InputsAl.A2.61.62
Differential Single-ended Mode
Vee = 5.0V. TA = 2S·C
Control to Outputs
tpd'
Propagation Delay to a Logical "1"
from IAput, AI. A2. 61. 62
Differential Si"gle~ended Mode
Control to Outputs
I
t'H
toH
tH'
,
Propagation Delay from Disable Inputs
to Logical "I" Level (from High
Impedance State)
tHO
Propagation Delay from Disable Inputs
to LogiC'a!, "0" Level (from High
I mpedance State)
'.
Note 1: "Absolute Maximum Ratin9s" are those values beyond which the safety of the device cannot be guarantaed. Except for "Operating
Tamperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified min/max limits apply across the'-o5"C to +125·C temperature range for the OS7831 and 057832 and across
the O·C to +70·Crange for the 088831 and 0S8832. All typical value. are for TA = 25"C and VCC = 5V.
Note 3: All currents i~to device pins shown as positive, out of device pins as negative, all voltages referencecf to ground unless otherwise noted. All
values shown as max or min!Dn absolute value basis.
Note 4: Applies for TA = 125"C·only. Only one output should be shorted at a time.
3·38
c
(J)
.....
CO
mode of operation (cont.)
OS7831/0S8831 's,
OS7832/0S8832's (Figure
1), all devices except one must be placed in the
"high impedance" state. This is accomplished by
ensuring that a logical "1" is applied to at least
one of the Output Disable pins of each device
which is to be in the "high impedance" state. A
NOR gate was purposely chosen for this function
since it is possible with only two OM5442/
OM7442, BCO-to-decimal decoders, to decode as
many as 100 OS7831/0S8831's, OS7832/
OS8832's (Figure 2).
The unique device whose Disable inputs receive
two logical "0" levels assumes the normal low
~
......
impedance output state, providing good capacitive
drive capability and waveform integrity especially
during the transition from the logical "0" to
logical "1" state. The other outputs-in the high
impedance state-take only a small amount of
leakage current from the low impedance outputs.
Since the logical "1" output current from the
selected device is 100 times that of a conventional
Series 54/74 device 140 mA vs. 400/1A), the
output is easily able to supply that leakage current
for several hundred other OS7831 /OS8831 's,
OS7832/0S8832's and still have available drive
for the bus line (Figure 3).
C
(J)
CO
CO
W
~
c
~
CO
W
N
......
C
(J)
CO
CO
W
N
BUS LINES
~
o0
SElECTED AS
DRIVING ___
DEVICE
s
S
8 8
8 8
3 3
1 2
o0
S S
8 8
8 8
3 3
1 2
o0
sS
GATED INTO
THIRD STATE ----..
8
8
3
1
8
8
3
2
Figure 1
Figure 2
FOR DRIVING OTHER TTL INPUTS
SElECTED AS
DRIVING OEVICE
GATED INTO
HI IMPEDANCE
STATE
40,IJA
LEAKAGE
CURRENT
PER CONN.
GATED INTO
HI IMPEDANCE
STATE
40jJA
Figure 3
3-39
N
M
ex)
ex)
typical performance characteristics
en
c
.......
Propagation Delay from Input
to Output (Channel 11
N
M
30
112
25
en
c
.s>
M
z
...
~
co
co
ex)
ex)
J JJJ J
en
20
'r-r--
tpdO
co
c
...
-15 -50 -25
Ieen
0
25
50
>
20
z
15
~
~
co
J JII J
~ r-
10
I
-15 -so -25
0
25
lO
I'
.... j...--'
tOH
""'"
.I
- -
15
10
t-- tHO
25
50
-15 -50 -25
15 100 125
T 01al Supply CUrrent vs
Frequency
""'"
""'''-
10
Vee:: 5.0V
60
TA=25°C
ALL CHANNELS SWITCHING
J
i--'" i--'"
tH1
""
lO
25
50
0
:!
>
~
z
0
~
20
if
10
100
40
OS18l1
Vee' =
.
.s
,
_55°C~
ii
,g
j
'~_55°C
-20
lii---2nl
125°C
,J:1+-7-
-40
'II I
Vie ·15.0~_
.,
O.l
>
0.2
~
lJ5 0 C_.I'
,
\
0·1
10,000
~
v.;
r-t7 7.z~ ~
V
~
""
I/. V--55°C
f&
1\
80
160
20
60
40
(mAl
lOUT
80
(mAl
20
15
DS18:.2
10
DS1il3l1
DS8831
-
500DpF
tpdZ
~
".,
--
* t f- tpd1
INPUT
i
1
---ll,.4.1--
--l
"'42
t--
'i
50
100
VI-V2
3-40
V
1/
I I
-50
VOUT (V)
1000
0.4
I
-2
100
5.~V
25
25°C ______
lllJ
'Propagation Delay in Differential Mode
30
12SoC ...............
C
10
0
lOUT
lOUT vs VOUT High Impedance
Output State
+20
t,.d.
11
o
I I
I (MHzI
I
t,.dO
0.5
\
j
'I
I
Vee'" 5.0V
10
Vee'" 5V
1
lO
Logical "0" Output Voltage vs
Sink Current
1\
...0
40
Logical "1" Output Voltage vs
Source CUrrent
20
10
TA "'25°C
50
>=
100 125
125°C_
>
,01
15
r--- ~ r--...!-2n
t-- --'--_55°C
.,
15 100 125
CL (pFI
t'" ~
~
50
TEMPERATURE reI
r-..
50
.su
0
25
Vee'" 5.0V
~
co
TEMPERATURE reI
0
60
o
0
40
-15 -50 -25
Propagation Delay vs Load
Capacitance
- ~
"......
! - i--'" ~
10
0
t,.d.
TEMPERATURE rCI
I. H
-15 -50 -25
10
15 100 125
vde = 510V
20
1--'- i"""
C
~
co
20
if
50
Vee'" 5.0V
25
15 I-- f--
>=
~
5.DV
15
Delay from Disable to Low
Impedance State
Impedance S~ate
~
co
~
TEMPERATURE (OC)
lO
>
.s>
:0
1---+--+-I---+-+---1r--+--I
25
o
15 100 125
20
Vee
co
z
co
r-r-
tpdO
if
Delay from Disable to High
!
......
t,.!,:.. ~ ~
TEMPERATURE ('C)
o
Propagation Delay from Input
to Output (Channel 21
lO ,-..,-...,-,-..,-,--;,-,-..,
Vee = 50V '
OIFFERENTlAL/SINGLE·ENOED MODE
CONTROL INPUTS AT LOGICAL 'T'
1
>=
I
o
M
]
co
-
10
25
~
co
I
15
if
.......
30
Vee = 5.0V
DIFfERENTIAL/SINGLE-ENDED MODE
CONTROL INPUTS AT LOGICAL "0"
>=
'"~'"
Propagation Delay from Input
to Output (Channel 11
TEMPERATURE eCI
~
"
'"
100
c
en
.....
switching time waveforms
(XI
....
W
........
c
tpd1 & tpdO
tOH
en
'v
(XI
(XI
....
W
INPUT
,,
,I
INPUT
w------
DV
J
C
en
.....
(XI
~tOH~
n
I
I
I
I
,JlYERHD
OUTPUT
ACTUAL
LOGICAL "0"
VOLTAGE
I
OUT'UT
I
I
I
I
I
I
I
I
I
I
I
........
c
---1
en
(XI
(XI
~~"'~
I
I
NONINVERTED
OUTPUT
W
N
"'" 1.5V
W
N
'v
t1H
I
,N.Ul
I
,V
ACTUAL
LOGICAl",N
Inputcharacte,istic:
OUTPUT
VOLTAGE
Amplitude=3.0V
Frequencv'" 1.0 MHz, 50% duty evcle
=t, 'S 10ns (10% to 90%)
t,
tH1
\-
INPUT
II'UT
~----------------DV
~
I
-l
_________________ w
'.,
I
OUTPUT
I
I
OUTPUT
,v
I
ac load circuit
s,
.,
....321
,SII"
l
SwitchS1
I"dl
,,"""
tpdO
"oud
10 •
,'''''''
',.
It
C
'.0
'
'.,
l
..
closed
"....
....
.......
".....
""""
,""'"
...."....
,,",,,,
C,
500'
50pF
"50'
-SpF
50 pF
500'
* Jig capacitance .
3-41
U')
C")
co
co
~
VJ
C
........
U')
C")
Line 0 rivers/Receivers
NAnONAL
~
c
057833/058833. 0578351058835 quad
TRI-5TATE® party line transceivers
C")
C")
co
co
VJ
C
........
C")
C")
~c
general description
features
This family of TRI-STATE Party Line Transceivers
offer extreme versatility in bus organized data
transmission systems. The data bus may be unterminated, or terminated dc or ac, at one or both
ends. Orivers in the third (high impedance) state
load the data bus with a negligible leakage current.
The receiver input current is low allowing at least
100 driver/receiver pairs to utilize a single bus.
The bus loading is unchanged when Vee = OV.
The receiver incorporates hysteresis to provide
greater noise immunity. All devices utilize a high
current TRI-STATE output driver. The OS7833/
OS8833 and OS7835/0S8835 employ TRI-STATE
outputs on the receiver also.
•
Receiver hysteresis'
•
Receiver noise immunity
1.4V typ
•
Bus terminal current for
normal Vee or Vee = OV
80llA max
•
Receivers
Sink
Source
•
400 mV typ
16 mA at 0.4V max
2.0. mA (Mil) at 2.4V min
5.2 mA (Com) at 2AV min
Orivers
Sink
50 mA at 0.5V max
32 mA at OAV max
lOA mA (Com) at 2.4V min
5_2 mA (Mil) at 2.4V min
Source
The OS7833/0S8833 are non-inverting quad
transceivers with a common inverter driver disable
control and a common inverter receiver disable
control.
•
Orivers have TRI-STATE outputs
•
The OS7835/0S8835 are inverting quad transceivers with a common inverter driver disable
control and a common inverter receiver disable
control.
OS7833/0S8833, OS7835/058835 receivers
have TRI-STATE outputs
• Capable of driving lOOn dc-terminated buses
• Compatible with Series 54/74
connection diagrams
Dual-in-line and Flat Package
Dual-I n-Line and Flat Package
DFlIVfR
Vee
BUSD
IND
OUTo
BUSe
INc
DUTe
8U8/\
INA
OUT",
BUSB
INa
IlUTB RECEIVER
DRIVER
DISABLE
V~C
BUS o
INo
OUTo
BUSe
JN e
GNO
8US"
INA
OUT",
BUSs
INs
OUTB RECEIVER
DUTe
DISABLE
DISABLE
DISABLE
TOP VIEW
Order Number DS7833J, DS8833J,
DS8833N or DS7833W
3-42
Order Number DS7835J, DS8835J,
DS8835N or DS7835W
GNO
c
absolute maximum ratings
~
operating conditions
(Note 1)
Supply Voltage (Vee)
057833, 057835
058833, 058835
Supply Voltage
7.0V
5.5V
Input Voltage
5.5V
Output Voltage
455°C to +150"e
Storage Temperature
3OQoe
Lead Temperature (Soldering, 10 seconds)
Temperature (TA)
057833, 057835
058833, 058835
W
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
+125
+70
°e
°e
--55
0
~
C
f/)
CO
CO
W
W
c
!!lCO
w
electrical characteristics
~
(Notes 2 and 3)
C
PARAMETER
DISABLE/DRIVER INPUT
I
I
CONDITIONS
V ,H
High Level Input Voltage
Vee = Min
V ,L
Low Level Input Voltage
Vee
I'H
High Level Input Current
,
MIN
I
TVP
I
MAX
I
f/)
UNITS
2.0
V
= Min
O.B
I
I
Vee:: Max
40
pA
1.0
mA
-1.0
-1.6
mA
-o.B
-1.5
V
-40
pA
Y'N = 2.4V
Y'N - 5.5V
I'L
Low Level Input Current
Vee =- Max, V IN = O.4V
VeL
Input Clamp Diode
Vcc=S.OV. i IN =-12mA,
lIT
Driver Low Level Disabled
Driver Disable Input"" 2.0V, V IN
TA=
=
2SoC
V
O.4V
Input Current
RECEIVER INPUT/BUS OUTPUT
V TH
V TL
18
High level Threshold Voltage
Low Level Threshold Voltage
Bus Current. Output Disabled
or High
DS7B33, DS7B35
1.4
1.75
2.1
V
DS6833, DS6B35
1.5
1.75
2.0
V
DS7833, DS7835
0.8
1.35
1.6
V
DS8833, DSBB35
0.8
1.35
1.5
25
BO
pA
5.0
BO
pA
-2.0
-40
pA
I Vee = Max
Vaus = 4.0V
I
Vee=OV
Vee = Max, Vaus = O.4V
V OH
Logic "1" Output Voltage
VOL
Logic "0" Output Voltage
los
Output Sh~rt C~rcuit Current
Vee:: Min
= Max,
DS7833, DS7835
2.4
lOUT = -10.,4 rnA
DS8B33, OSB835
2.4
V
2.1 5
2.75
0.2B
lOUT'" SOmA
Vee:: Min
Vee
lOUT"" -5.2 rnA
V
V
V
0.5
0.4
lOUT· 32mA
'-40
(Note.41
--62
-120
V
mA
RECEIVER OUTPUT
V OH
Logic "1" Output Voltage
lOUT = -2.0 mA
Vee"" Min
lOUT. = -5.2 mA
I DS7B33, DS7835
I DS8833, DSB835
2.4
3.0
2.4
2.9
0.22
V
V
0.4
V
VOL
Logic "0" Output Voltage
Vee'" Min.
lOT
Output Disabled Current
Vee'" Max. Disable
V OUT
'"
2.4V
40
~A
Inpu't5 '" 2.0V
V OUT
=
O.4V
-40
pA
los
Icc
Output Short Circuit Current
Supply Current
lOUT""
l6mA
Vee = Max. (Note 4)
Vee
=
Max
I DS7833, DS7835
I DS8833, DS8835
-28
. -40
-30
75
-70
mA
-70
mA
95
mA
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" th~y are not meant to imply that the devices sho,uld be operated at these limits. The
table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified minimax limits apply across the --55°e to +125°e temperature range for the 057833,
057835 and across the O°C to +70oe range for the 058833, 058835. All typicals are given for Vee = 5.0V and TA = 25°C.
Nots 3: All currents into device pins shown as positive, c;>ut of device pins as negative, all voltages referenced to ground unless
otherwise noted. All values shown as max or min on absolute value basis.
Note 4:. Only one output at a time should be shorted.
3·43
CO
CO
W
UI
switching characteristics
Vee = 5.0V, TA = 2SoC
PARAMETER
'pdO
CONDITIONS
- Propagation ,Delay to a
Logic "0" From Input
to Bus
Propagation Delay to a
'pd,
Logic "1" From Input
MIN
TYP
MAX'
UNITS
(Figure 1)
OS7833/0S8833
OS7835/0S8835
14
10
30
20
ns
ns
(Figurf11)
OS7833/0S8833
,087835/0S8835
14
30
11
30
ns
ns
(Figure 2)
OS7833/0S8833
OS7835/0S8835
24
16
45
35
ns
ns
(Figure 2)
0S7833/0S8833
OS7835/0S8835
12
18
30
30
ns
ns
CL = 5.0 pF, (Figures 1 and 2)
Driver
Receiver
8.0
20
ns
6.0
15
ns
C L == 5.0 pF, (Figures 1 and 2)
Driver
Receiver
20
13
35
25
ns
ns
CL
Driver
Receiver
24
16
40
35
ns
ns
Driver
19
15
33
·35
30
50
ns
ns
ns
to Bus
Propagation Delay to a
'pdO
Logic "0" From Bus
to Output
Propagation Delay to a
Logic "1" From Bus
to Output
'pd,
Delay From Disable
"H
Input to High Impedance
State (From Logic "1" Level)
Delay From Disable Input to
'OH
High Impedance State (From
Logic "0" level)
Delay From Disable Input to
'H'
I
I
Logic "1" Level (From High
;;;;
50 pF, (Figures 1 and 2)
Impedance State)
'HO
Delay From Disable Input to
Logic "0" Level (From High
CL = 50 pF, (Figures 1 and 2)
Impedance State)
f MAX
Receiver 0$7833
Receiver 057835
Maximum Clock Frequency
ac test circuits
Voe
,
Voe
...... .....
10'
.
-:-Lf
"'1
""T",,""
"
':J...1'..... ..... ......
400
OUTPUT
""T -=1.0.
FIGURE 1. Drivar Output Load
/
..
"''1
FIGURE·2. Racaiver Output Load
switching time waveforms
"
tpd1 8. tpdO
tOH
3.UV
'
I.';TJ . ' v .
,
\.,v
I [
ov:
--ifpdOr--
----ttpdtr--
OUTPUT~
:
1.5V
I I.SV
(lNVERTEDI
I
:
'''IMHz
t,=1t:5:1Dns(1I1"tellO%)
OUTVCvCLE-m
3·44
·OV
.
'pdt : - -
--I \odo :--
OUTPUT~
.
1.5V
, 1.SV
(NDNINVERTEO)
JBV'~
INPUT'
OUTPUT
ACTUAL LOGICAL "D"
VOLTAGE
I 1.5V
I
---lI
tClH
I---
I
Y-1
--r
D.SV
...,.&V
c
~
switching time waveforms (con't)
w
~
..JI.V
INPUT
INPUT _______
OV
ACTUAL LOGICAL "'"
VOLTAGE
OUTPUT
c
en
Jv------.
JV----------,__- - - - - - - - - - - - - -
~,UV
00
00
w
w
c
Ov------------~·- ' - - - - - - - -
I
O.5V
---------+I--......---.t
:
~----.
:!'l
I
I
t--tlH--J
t " ,.v
:
..
-----~, .•V
OUTPUT
\
o.v
~ tHO---j~ ACTUAL LOGICAL "0"
[
l
VOLTAGE
~
w
~
c
en
00
00
JV~.
INPUT
w
1\:5V
U'I
OV~
I
~,
I
I
OUTPUT
I
r-:-----------
J__
T - O••V
_ _________.....J
" .•v
I
I
V,
__
ACTUAL LOGICAL "1"
VOLTAGE
r
3-45
~
Line 0 rivers/ Receivers
NAnONAL
057834/058834, 057839/058839 quad
TRI-5TATE®party line transceivers
general description
features
This family of TRI-STATE party line transceivers offer
extreme versatility in bus organized data transmission
systems_ The data bus may be unterminated, or terminated de or ac, at one or both ends_ Drivers in the third
(high impedance) state load the data bus with a negligible
leakage current_ The receiver input current is low allowing at least 100 driver/receiver pairs to utilize a single
bus_ The bus loading is unchanged when Vee = OV. The
receiver incorporates hysteresis to provide greater noise
immunity. Both devices utilize a high current TRI·
STATE output driver. The DS7834/DS8834 and DS7839/
DS8839 employ TTL outputs on the receiver.
•
•
•
Receiver hysteresis
Receiver noise immunity
Bus terminal current for
normal Vee or Vee = OV
•
Receivers
Sink
Source
The DS7834/DS8834 are inverting quad transceivers
with two common inverter driver disable controls.
80llA max
16 rnA at O.4V max
2.0 rnA (Mil) at 2.4V min
5.2 rnA (Com) at 2.4V min
• Drivers
Sink
50 rnA at 0.5V max
32 rnA at 0.4V max
10.4 rnA (Com) at 2.4V min
5.2 rnA (Mil) at 2.4V min
Source
The DS7839/DS8839 are non-inverting quad transceivers
with two common inverter driver disable controls.
400 mV typ
1.4V typ
• Drivers have TRI-STATE outputs
• Receivers have TR I-STATE outputs
• Capable of driving lOOn dc-terminated buses
• Compatible with Series 54/74
connection diagrams
Dual-In-Line and Flat Package
Vee
BUSo '
INo
OUT 0
BUSe
Dual-In-Line and Flat Package
INc
DUTe
OUT B
DRIVER
DISABLE
TOP VIEW
Order Number DS7834J, DS8834J
DS8843N or DS7834W
3-46
DRIVER
DISABLE
GNO
DRIVER
Vee
BUSo
BUSA
INA
INo
DUTA
OUTo
BUSe
INc
DUTe
DISABLE
BUSe
INa
OUTs
DRIVER
GNO
DlSABtE
TOP VIEW
Order Number DS7839J, DS8839J,
DS8839N or DS7839W
absolute maximum ratings
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature
Lead Temperature (Soldering, 10 Seconds)
c
operating conditions
(Note 1)
Temperature (T A)
057834, 057839
OS8834, OS8839
MAX
4.5
4.75
5.5
5.25
V
V
.......
C
+125
+70
"C
"e
CO
CO
W
-fj5
0
UNITS
~
MIN
5upply Voltage (Vee)
OS7834, 057839
OS8834, 058839
7.0V
5.5V
5.5V
-fj5"e to +150"C
300"e
~
CJ)
~
C
CJ)
dc electrical characteristics
~
W
CD
(Notes 2 and 3)
.......
PARAMETER
MIN
CONDITIONS
TYP
MAX
UNITS
V ,H
High Level Input Voltage
Vee"" Min
V ,L
Low Level Input Voltage
Vee"" Min
I'H
High Level I nput Current
Vee == Max
2.0
V
0.8
IV
IV
V
,N =
2.4V
40
~A
,N =
5.5V
1.0
rnA
-1.0
I'L
Low Level Input Current
Vee == Max, V ,N = O.4V
liND
Driver Disabled Input Low
Driver Disable Input == 2.0V, V ,N = OAV
-1.6
rnA
-40
I1A.
-1.5
V
Current
VeL
Input Clamp Diode
Vee = 5.0V, liN =-12mA, T A = 25"C
-D.8
RECEIVER INPUT/BUS OUTPUT
V TH
V TL
IBH
High Level Threshold Voltage
Low Level Threshold Voltage
Bus Current, Output Disabled or
High
DS7834, DS7839
1.4
1.75
2.1
V
DS8834, DS8839
1.5
1.75
2.0
V
OS7834, DS7839
0.8
1.35
1.6
V
DS8834, DS8839
0.8
1.35
1.5
V
25
80
5.0
80
~A
-40
I1A
Vee - Max,
V BUS = 4.0V
Disable Input
=
2.0V
I Vee -OV
Vee
V OH
VOL
los
Logic "1" Output Voltage
Logic "0" Output Voltage
Output Short Circuit CUrrent
=
Max. V BUS = OAV, Disable Input = 2.0V
Vee = Min
Vee
= Min
Vee
::::0
lOUT
=
-5.2 rnA
lOUT = -10.4 rnA
DS7834, DS7839
2.4
2.75
DS7834, I;)S8839
2.4
2.75
0.28
lOUT:: 50 rnA
V
V
0.5
0.4
lOUT - 32 rnA
-40
Max, (Note 4)
-62
~A
-120
V
V
rnA
RECEIVER OUTPUT
V OH
Logic "1" Output Voltage
VOL
Logic "0" Output Voltage
los
Output Short Circuit Current
lee
Supply Current
C
CJ)
DISABLE/DRIVER INPUT
Vee:: Min
I lOUT:: -2.0 rnA
I lOUT -
Vee:::; Min, lOUT
=
J DS7834, DS7839
I DS8834, DS8839
2.4
3.0
V
2.4
2.9
V
0.22
16 mA
Vee:::: Max, (Note 4)
Vee = Max
5.2 rnA
I DS7834, D.S7839
I DS8834, DS8839
-28
-40
-30
75
0.4
V
-70
rnA
--70
rnA
95
rnA
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the -55°C to +125°C temperature range for the OS7834, OS7839 and across
the o"e to +70o e range for the 088834, 088839. All typicals are given for Vec = 5.0V and TA ~ 25"C,
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted.
All values shown as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.
3-47
00
CO
W
CD
en
(I)
co
co
ae electrical characteristics vcc=·s.ov, TA =2S0c
tn
PARAMETER
Q
......
en
(II)
tpdO
from Input to
Ie
en
tpd,
(Figure I)
~us
Propagation Delay to a Logic "1"
(Figure I)
from Input to Bus
.
'lit
Q
tpdO
tpd,
(II)
CO
CO
en
t1H
Q
TYP
MAX
087839/058839
MIN
14
30
ns
OS7834/058834
10
20
ns
057839/058839
14
30
0578341058834
11
30
ns
ns
057839/058839
24
45
ns
087834/058834
16
35
ns
057839/058839
12
30
ns
057834/058834
18
30
ns
CONDITIONS
Pr,?pagation Delay to a Logic "0"
UNITS
Propagation Delay to a Logic "0"
from Bus to Output
(Figure2)
Propagation Delay to a Logic "1"
from Bus to Output
(Figure2)
Delay from Oisal)le Input to High
CL
= 5.0 pF.
(Figures 1 and 2)
Driver Only
8
20
ns
CL
= 5.0 pF.
(Figures 1 and 2)
Driver Only
20
35
ns
CL
= 50 pF.
(Figures 1 and 2)
Driver Only
24
.40
ns
CL
= 50 pF.
(Figures 1 and 2)
Driver pnly
19
35
·ns
Impedance State (from Logic "I"
Level)
......
~
to+<
~Q
Delay from
~isable
Input to High
Impedance State (from Logic "0"
Level)
tHl
Delay from Disable Input to Logic
"I" Level (from High Impedance
State)
tHO
Delay from Disable Input to Logic
"0" Level (from High Impedance
State)
ac· test circuits
vee
-.:-15O.FT
r
vee
....
100
...
I.OIe
-= ":" .
....
400
'-L
OUTPUT
1
c,
50
FIGURE 1. Driver Output Load
0F
T
... ...
... .........
.
~
"'1
FIGURE 2. Receiver Output Load
switching time wavefprms
tpdt and tpdQ
~------r------~
{.»v
ov--I: .
INPUT
3.0V--,-----r--------.,....
'xSV
---it.dO~
i \..'",- - - -
INPUT
~tpd1r--
--r-\:
....
! v.-:::-! ~'.5V
I
---i tpdt 14-
,
- . ; tpdO ' - -
"
~
OUTPUT
(NO.,NVERTEDI
I
f=1MHz
1.- .. t,:s; 10 ns (UI%1O 9Q%J .
Duty eyda" 58%
3·48
I
I
1.5V
1.5V
11(,·5V
OV-_ _-J· I
OUTPUT
ClNVERTEDI
OUTPUT
ACTUAL
LO~8t~~:~
ito"lt.
,.--------"".5V
.y-.t
-----------r
D.SV
c
~
co
to)
switching time waveforms (con't)
~
tlH
3V
INPUT
OV
ACTUAL LOGICAL "1"
VOL lAGE
OUTPUT
i
3V
INPUT
5V
OV
,
O.SV
1
1
---.-i
1
1
1
N-
.......
\:V
C
CJ)
1
:
OUTPUT
""1.5V
co
co
to)
-----+, '-------
~tIH.......-.I
~
""t.5V
\
0.5V
~ 4to--..~ ACTUAL LOGICAL "0"
I
\
VOLTAGE
C
CJ)
CXl
to)
to
.......
C
CJ)
co
co
to)
'NP::---.. . .\\'"
to
OV---------TI-~-------------1
~,
I
1
OUTPUT
,'.5V
1
1 ~.,....------- ACTUAL LOGICAL ''1''
'/,__
__________T-
1__
VOLTAGE
0.5V
--r
3-49
Line Drivers/R~ceivers
~
~
NATIONAL
057836/058836 quad NOR unified bus receiver
general description
features
The DS7836/DS883£ are quad 2-input receivers
designed for use in bus organized data transmission
systems interconnected by terminated 120n impedance lines. The external termination is intended to be 180n resistor from the bus to the +5V
logic supply together with a 390n resistor from
the bus to ground. The design employs a built-in
input hysteresis providing substantial noise immunity. Low input current allows up to 27 driver/
receiver pairs to utilize a common bus. This receiver has been specifically configured to replace
the SP380 gate pin-far-pin to provide the distinct
advantages of the DS7837 receiver with built-in
hysteresis in existing systems. Performance is
optimized for systems with bus rise and fall times
::; 1.0p.s/V.
•
Low input current
Vee ~ OV (15 p.A typ)
•
Built-in input hysteresis (lV typ)
•
High noise immunity (2V typ)
•
Temperature-insensitive input thresholds track
bus logic levels
•
DTLITTL compatible output
•
Matched, optimized noise immunity for "1"
and "0" levels
•
High speed (18 ns typ)
with
normal
typical application
·5V
'5V
180
180
---,
390
,-
I I
I I
I I
---,
I
I
I
I
I
_...J
_...J
connection diagram
Dual·ln·Line and Flat Package
OUT3
OUT4
IN 4A
IN48
IN JA
IN 38
Vee
IN lA
IN 18
IN 2A
IN 28
,4
GNO
OUT 2
OUT 1
TOP VIEW
Order Number DS7836J
or DS8836J
3-50
Order Number DS8836N
Order Number DS7836W
J90
":"
Vee
or
absolute maximum ratings
operating conditions
Supply Voltage
Current Voltage
Power Dissipation
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
~5'e
7.0V
5.5V
600mW
to +150'e
300'e
5upply Voltage (V CC)
057836
058836
Temperature (T A)
057836
058836
MIN
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
-£5
0
'e
+125
+70
'c
UNITS
electrical characteristics
The following apply for V MIN ~ Vee ~ V MAX , T MIN ~ TA ~ T MAX, unless otherwise specified (Notes 2 and 3)
PARAMETER
V TH
Vil
CONDITIONS
High Level I nput Threshold
Low Level I nput Threshold
TYP
MAX
OS7836
1.65
2.25
2.65
V
058836
1.80
2.25
2.50
V
OS7836
0.97
1.30
1.63
V
OS8836
1.05
1.30
1.55
15
50
I1A
1
50
I1A
0.25
0.4
V
IVee ~ Max
liN
Maximum Input Current
V OH
Logical "1" Output Voltage
Y'N = 0.5V, lOUT = -40011A
Val
Logical "0" Output Voltage
Y'N ~ 4V, lOUT ~ 16 mA
Ise
Output Short Circuit Current
Y'N = 0.5V, V OUT
lee
Power Supply Current
Y,N
Vel
Input Clamp Oiode Voltage
liN ~ -12 mA, T A ~ 25'C
Y'N ~4V
~
MIN
IVee~OV
~
2.4
OV, Vee = Max, (Note 4)
V
-18
4V, (Per Package)
V
25
-1
-55
mA
40
mA
-1.5
V
UNITS
switching characteristics
Vee = 5V, T A = 25°C unless otherwise specified.
PARAMETER
tpd
CONDITIONS
Propagation Oelays
(Notes 4 and 5)
TYP
MAX
I Input to Logical" 1" Output
20
30
ns
I Input to Logical "0" Output
18
30
ns
MIN
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for" "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the -55°C to +125c C temperature range for the OS7836 and across the O°C to
+70'C range for the OS8836. All typical values are for TA ~ 25'C and Vce ~ 5V.
Note 3: All currents into device pins shown as positive, out of device pins as negative, alJ voltages referenced to ground unless otherwise noted. All
/
values shown as max or min on absolute value basis.
Note 4: Fan·out of 10 load, CLOAO ~ 15 pF total, measured from VIN ~ 1.3V to VOUT = 1.5V, VIN ~ OV to 3V pulse.
Note 5: Fan·out of 10 load, eLOAO
~
15 pF total, measured from VIN
~
2.3V to VOUT
~
1.5V, VIN
~
OV to 3V pulse.
~
Line Drivers/Receivers
NAnONAL
OS7837/0S8837 hex unified bus receiver
general description
features
The DS7837/DS8837 are high speed receivers designed for use in bus organized data transmission
systems interconnected by terminated 12m2 impedance Iines_ The external termination is intended to be 180n resisior from the bus to the +5V
logic supply together with a 390n resistor from
the bus to ground_ The receiver design employs a
built-in input hysteresis providing substantial noise
immunity. Low input current allows up to ,27 driver/receiver pairs to utilize a common bus.- Disable
inputs provide time discrimination. Disable inputs
and receiver outputs are DTL/TTL compatible.
Performance is optimized for systems with bus
rise and fall times:::; 1.0J.ls/V.
•
Low receiver input current for normal Vee or
Vee = OV (15 J.lA typ)
•
Six separate receivers per package
•
Built-in receiver input hysteresis (lV typ)
•
High receiver noise immunity (2V typ)
•
Temperature insensitive receiver input thresholds track bus logic levels
•
DTLITTL compatible disable and output
•
Molded or cavity dual-in-line or flat package
•
High speed
typical application
.5V
.5V
180
120n Unified Data Bus
---, r- ---,
390
I
I
I
I I
I I
I I
I
_...J
I
_..J
connection diagram
Dual-ln.:Line and Flat Package
Vee
IN 4
IN lOUT 1
OUT 4
IN 5
IN 2
OUT 2
OUT 5
IN 6
IN 3
OUT 3
DISABLE A
"OUT 6 DISABLE B GND
TOP VIEW
Order Number DS7837J
or DS8837J
3-52
Order Number DS8837N
Order Number DS7837W
390
absolute maximum ratings
c
CJ)
operating conditions
-..I
00
7V
5.5V
600mW
Supply Voltage
Input Voltage
Power Dissipation
Operating Temperature Range
OS7837
OS8837
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
MAX
UNITS
4.5
4.75
5.5
5.25
V
V
+125
+70
°e
°e
Temperature (TAl
OS7837
OS8837
-55
0
"C
CJ)
electrical characteristics
The following apply for V MIN
<::: Vee <::: V MAX, T MIN <::: T A<::: T MAX, unless otherwise specified
CONOITIONS
PARAMETER
V TH
V TL
Low Level Receiver Threshold
I'H
Maximum Receiver Input Current
V ,N
~
(Notes 2 and 3)
MIN
High Level Receiver Threshold
TYP
MAX
057837
1.65
2.25
2.65
V
058837
1.80
2.25
2.50
V
057837
0.97
1.30
1.63
V
058837
1.05
1.30
1.55
V
15.0
50.0
I1A
1.0
50.0
I1A
1.0
50.0
I1A
Vee = V MAX
4V
Vee
~
OV
I'l
Logical "0" Receiver Input Current
V ,H
Logical "1" Input Voltage
Disable
V'l
Logical "0" Input Voltage
Disable
I'H
Logical" 1" I nput Current
V ,ND
~
2.4V
V ,ND
~
5.5V
I'l
Logical "0" I nput Current
VIN = 4V. V 1ND = O.4V, Disable Input
V OH
Logical "1" Output Voltage
V ,N
~
0.5V, V ,ND
Val
Logical "0" Output Voltage
V ,N
~
4V, V ,ND
los
Output Short Circuit Current
V ,N
~
0.5V, V ,ND
V IN = D.4V, Vee = V MAX
Disable Input
~
~
0.8V, 10l
~
~
0.8V, 10H
OV, Vas
~
2.0
~
OV, Vee
I1A
2.0
rnA
-3.2
rnA
0.4
V
V
0.25
~
V MAX ,
V
80.0
2.4
16 rnA
UNITS
V
0.8
-40011A
-18.0
-55.0
rnA
60.0
rnA
(Note 41
~
Icc
Power Supply Current
V ,N
Vel
Input Clamp Diode
V 1N = -12 rnA, V 1ND = -12 rnA,
4V, V ,ND = OV, (Per Packagel
TA
45.0
-1.0
= 25°C
-1.5
V
switching characteristics
PARAMETER
tpd
Propagation Delays
CONDITIONS
W
-..I
Supply Voltage (Veel
OS7837
OS8837
--55°e to +125°e
O°C to +70°C
-i;5°e to +150o e
3000 e
MIN
TYP
MAX
UNITS
V 1ND =OV, Input to Logical "1" Output, (Note 5)
MIN
20
30
ns
Receiver
V ,N ~ OV,
Input to Logical "0" Output, (Note 61
18
30
ns
Input to Logical "1" Output
9
15
ns
Disable,
(Note 71
Input to Logical "0" Output
4
10
ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the -55°C to +125°C temperature range for the DS7837 and across the aOc to
+70o e range for the OS8837. All typieals values are for T A = 25°C and Vee ~ 5V.
Note 3: All currents into device pins shown as positve, out of device pins as negative, all voltages,referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: Fan-out of 10 load, eLOAO ~ 15 pF total. Measured from VIN ~ 1.3V to VOUT ~ 1.5V, VIN ~ OV to 3V pulse.
Note 6: Fan-out of 10 load, eLOAO ~15 pF total. Measured from VIN ~ 2.3V to VOUT = 1.5V, VIN ~ OV to 3V pulse.
Note 7: Fan-out of 10 load, CLOAO ~ 15 pF total. Measured from VIN ~ 1.5V to VOUT ~ 1.5V, VIN ~ OV to 3V pulse.
3·53
00
00
W
-..I
co
co
co
M
.~
C/)
Line Drivers IReceivers
~
C
........
M
co
co
,....
NAll0NAL
C/)
057838/058838 quad unified bus transceiver
C
general description
features
The DS7838/DS8838 are quad high speed drivers/
receivers designed for use in bus organized data
transmission systems interconnected by terminated 120[1 impedance lines_ The external termination is intended to be a 180[1 resistor from the
bus to the +5V logic supply together with a 390[1
resistor from the bus to ground. The bus can be
terminated at one or both ends. Low bus pin current allows up to 27 driver/receiver pairs to utilize
a common bus. The bus loading is unchanged
• when V cc ~ OV. The receivers incorporate hysteresis to greatly enhance bus noise immunity. One
two-input NOR gate is included to disable all
drivers in a package simultaneously. Receiver performance is optimized for systems with bus rise
and fall times S 1.0ILsN.
•
4 totally
package
separate driver/receiver
•
1 V typical receiver input hysteresis
•
Receiver hystereSis
output load
•
Guaranteed minimum bus noise immunity of
1.3V, 2V typo
•
Temperature-insensitive receiver thresholds
track bus logic levels
•
20ILA typical bus terminal current with normal
V cc or with V cc ~ OV
•
Open collector driver output allows wire-OR
connection
•
•
High speed
Series 74 TTL compatible driver and disable
inputs and receiver outputs
independent of receiver
typical application
.5V
'5V
180
390
120!! Unified Data
rQ:jl'r::;;.
Q
I
I
.
18'
Bus
--, r-
I I
I I
I I
I I
I I
II
1'16
I I
I.!M!E';,... __ .J L _
I
I
_...l
connection diagram
Dual I "-Line and Flat' Package
Vee
BUS3
8US
t
INJ
IN lOUT 1 , BUS 2
DUTl
BUS4
IN4
IN 2
OUT4
OUT 2 DISABLE A
DISABLED
GND
TOP VIEW
Order Number DS7838J
or DS8838J
3-54
Order Number DS8838N
pairs per
'Order Number DS7838W
39'
absolute maximum ratings
o
en
(Note 1)
Supply Voltage
Input and Output Voltage
7V
5.5V
600mW
Power Dissipation
Operating Temperature Range
OS7838
OS8838
Storage Temperature Range
Lead Temperature, (Soldering, 10 sec)
-...I
00
W
00
_55°C to +125°C
O°C to +70°C
-65°C to +150°C
300°C
........
o
en
00
00
W
00
electrical characteristics
057838/0S8838:
(Notes 2 and 3)
The following apply for V MIN
:0:: Vee :0:: V MAX , T MIN :0:: T A :0:: T MAX
PARAMETER
CONDITIONS
unless otherwise specified
MIN
TYP
MAX
UNITS
DRIVER AND DISABLE INPUTS
V ,H
Logical "1" Input Voltage
V'l
Logical
I,
Logical "1" Input Current
V ,N = 5.5V
1
I'H
Logical "1" Input Current
V ,N = 2.4V
40
JJA
I'l
Logical "0" Input Current
V ,N = O.4V
-1.6
mA
Vel
Input Diode Clamp Voltage
-1.5
V
0.7
V
"a"
2.0
V
I nput Voltage
0.8
-1
lOIS =-12mA,I'N =-12mA,I BUS =-12 mA,
V
mA
T A = 25°C
DRIVER OUTPUT/RECEIVER INPUT
VOLB
Low Level Bus Voltage
V OIS = 0.8V, V ,N = 2V, I BUS = 50 mA
I'HB
Maximum Bus Current
V ,N = 0.8V, V BUS = 4V, Vee = V MAX
20
100
JJA
I'LS
Maximum Bus Current
V ,N = 0.8V, V BUS = 4V, Vee = OV
2
100
JJA
V ,H
High Level Receiver Threshold
V'l
V'NO = 0.8V, VOL = 16 mA
Low Level Receiver Threshold
V,NO = 0.8V, V OH = -400/lA
0.4
057838
1.65
2.25
2.65
V
058838
1.80
2.25
2.50
V
057838
0.97
1.30
1.63
V
D58838
1.05
1.30
1.55
V
0.25
0.4
RECEIVER OUTPUT
V OH
Logical "1" Output Voltage
VOL
Logical
los
Output Short Circuit Current
Icc
5upply Cu rrent
tpd
Propagation Delays (Note 8)
"a"
Output Voltage
V ,N = 0.8V, V BUS = 0.5V, 10H = -400JJA
2.4
V ,N = 0.8V, V BUS = 4V. 10L = 16 mA
VDlS = 0.8V. V ,N = 0.8V, V BUS = 0.5V,
V
-18
V
-55
mA
70
mA
Vos = OV. Vee = V MAX • INote 4)
V OIS = OV. V ,N = 2V. (Per Package)
50
Disable to Bus "1"
INote 5)
19
30
ns
"a"
(Note 5)
15
23
ns
Driver Input to Bus "1"
INote 5)
17
25
ns
Driver Input to Bus 110"
(Note 5)
9
15
ns
Bus to Logical "'" Reciever Output
INote 6)
20
30
ns
Bus to Logical "0" Receiver Output
(Note 7)
18
30
ns
Disable to Bus
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the -55°e to +125° e temperature range for the OS7838 and across the O°C to
+70°C range for the OS8838. All typical values are for TA = 25°C and Vee = 5V.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
Note 4: Only one output at a ti~e should be shorted.
Not. 5: 9H1 from bus pin to VCC and 200n from bus pin to ground, C LOAO = 15 pF total. Measured from VIN = 1.5V to VBUS = 1.5V, VIN =
OV to 3.0V pulse.
Note 6: Fan-out of 10 load, CLOAO = 15 pF total. Measured from VIN = 1.3V to VOUT ~ 1.5V, VIN = OV to 3.0V pulse.
Note 7: Fan-out of 10 load, CLOAO = 15 pF total. Measured from VIN = 2.3V to VOUT = 1.5V VIN = OV to 3.0V pulse.
Note 8: These apply for Vce = 5V, TA = 25"C unless otherwise specified.
3-55
-
~
Line Drivers/Receivers
NAll0NAL
0555107/0575107, 0555108/0575108,
051603/053603,0575207, 0575208,
053604 dual line receivers
general description
features
The nine products described herein are TTL
compatible dual high speed circuits intended for
sensing in a broad range of system applications.
While the primary usage will be for line receivers
or MOS sensing, any of the products may effec·
tively be used as voltage comparators, level trans·
lators, window detectors, transducer preamplifiers,
and in other sensing applications. As digital line
receivers the products are applicable with the
OS55109/0S75109 and OS55110(OS75110 companion drivers, or may be used in other balanced
or unbalanced party-line data transmission systems.
The improved input sensitivity and delay specifications of the OS75207, OS75208 and OS3604
make them ideal for sensing high performance
MOS memories as well as high sensitivity line
receivers and voltage comparators. TR I-STATE@
products enhance bused organizations..
•
Oiode protected input stage for power "OFF"
condition
•
17 ns typ high speed
•
TTL c9mpatible
•
±10 mV or ±25 mV input sensitivity
•
±3V input common-mode range
•
High input impedance with normal Vee, 9r
Vee = OV
•
Strobes for channel selection
•
TRI-STATE outputs for high speed buses
•
Oual circuits
•
Sensitivity gntd. over full common-mode range
•
LOgic input clamp diodes-meets both "A" and
"8" version specifications
•
±5V standard supply voltages
connection diagrams
Dual-I n-l ine Package
Dual-I n-L ine Package
INPUT
INPUT
OUTPUT
STROBE
INPUT
"
2'(
20
"
NO
OUTPUT
STROBE
DISABlE
IV
lG
0
Vec"
Vee·
2A
INPUT
INPUT
Ne
IA
18
OUTPUT
STROBE
STROBE
IV
IG
S
GND
INPUT
lA
INPUT
18
Ne
STROBE
20
TOP VIEW
TOP VIEW
Order Number OS55107J, 0875107J,
OS55108J, OS75108J, OS75207J
or OS75208J
Order Number OS1603J, OS3603J
OS3604J or OS1603W
Order Number OS3603N or OS3604N
Order Number OS75107N, OS75108N·,
OS75207N or OS75208N
Order Number OS55107W or OS55108W
product selection guide
TEMPERATURE .....
PACKAGE-.+
INPUT SENSITIVITY-+
-55°C ~TA·'S +12SoC
O°C:S T A $ +70°C
CAVITY DIP
CAVITY OR MOLDED DIP
.t25mV
±25-mV
±10mV
OS55107
0555108
OS1603
0$75107
OS75108.
0S3603
0575207
OS75208
053604
OUTPUT LOGIC!
TTL ActIve Pull-up
TTL Open Collector
TTL TAl-STATE
3-56
OUTPUT
2Y
GND'
absolute maximum ratings
Supply Voltage, Vee +
Supply Voltage, VeeDifferential I nput Voltage
(Notes 1, 2 and 3)
Strobe I nput Voltage
7V
-7V
±6V
±SV
Common Mode Input Voltage
Storage Temperature Range
Power-Dissipation
Lead Temperature (Soldering. 10 sec)
S.SV
-6s·e to +1S0·e
600mW
300·e
operating conditions
OS751 07, OS75207
OS75108,0875208
083603, 083604
OS551 07,
0855108,
081603
NOM
MAX
MIN
Supply Voltage Vee +
MIN
4.SV
SV
5.SV
4.7SV
NOM
SV
MAX
S.2SV
Supply Voltage Vee -
--4.SV
-5V
-S.SV
-4.7SV
-SV
-S.25V
Operating Temperature Range
-ssoe
to
. +12Soe
o·e
to
+70·e
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except fOr "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteri:itics"
provides conditions for actual device operation.
Nota 2: Unless otherwise specified minImax limits apply across the -55°C to +1:i6°C temperature range for the 051603, 0555107 and 0555108
and across the
r:fc to +10°C range for the OS3603, 053604, 0516101, 0575108. All typical values are for T A::: 2s<»e and Vee = 5V.
Note 3: All currents into device pins shown as positive, out of deviCe pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
typical applications
Line Receiver Used in a
Party-Line or Data-Bus System
RECEIVEAS
1WI5TE0-,AlR
llIAldIiIIlSSION
LINE
10'
......,
LinII ......
1IS151l1/lmillO
Lina Receiver Used in MOS Memory System
nLTOMOS
DRIVERS
MMI2JZMOSMEMOAY ARAAY
MOSTOTnRECEIVEASIDS3ll1MI
3-57
II)
Q)
.;:
Q)
schematic diagrams
CI)
s....
~
Q
OS5.5107/0S75107,OS75207
0855108/0S75108,0875208
vcc+o--.....---f-.....--+-o OUTPUT
C,
(NOTE B)
Note 1: The pulse gefleriltors have the foUowinD characreristics:
3-66
n~.
y
B
C
0
E
F
H
H
H
H
X
X
H
X
X
X
X
H
H
All Other Input Combinations
H
= high level,
, L
ac test circuit and switching time waveforms
lOUT "'" 50~~. tw " 200 liS, duty cvcle '" 50%, t, " If = 5.0
Note 2: Cl IIlcludesprobe and jig capacitance.
OUTPUT
INPUTS
A
INPUT
=
L
low level, X = Irrelevant
absolute maximum ratings
Supply Voltage. V CC
I nput Vol tage
Output Voltage
Output Current
_Power Dissipation
electrical characteristics
Supply Voltage. VCC
Temperature, T A
DS55121
DS75121
6.0V
6.0V
6.0V
-75mA
600mW
300°C
Lead Temperature (Soldering, 10 seconds)
cCJ)
operating conditions
(Note 1)
U1
U1
MAX
UNITS
4.75
5.25
V
~
........
+125
+75
°c
°c
U1
MAX
UNITS
-55
0
C
~
ii:S
...
Vee; 4.75V to 5.25V (unless otherwise noted) (Notes 2 and 3)
PARAMETER
CONDITIONS
MIN
TYP
V ,H
High Level Input Voltage
V ,L
Low Level Input Voltage
V,
Input Clamp Voltage
Vcc = 5.0V, I, = -12 mA
-1.5
I,
Input Current at Max Input Voltage
Vcc = 5.25V, Y'N = 5.5V
1
mA
V OH
High Level Output Voltage
V'H = 2.0V, 10H = -75 mA (Note 4)
10H
High Level Output Current
Vee = 5.0V, V'H = 4.75V, V OH = 2.0V,
T A = 25°C (Note 4)
-250
mA
2.0
V
O.S
IOL
Low Level Output Current
V ,L = O.SV. VOL = OAV (Note 4)
10(OFFI
Off State Output Current
Vec = OV, Va = 3.0V
I'H
High Level Input Current
V, = 4.5V
I'L
Low Level I nput Current
V,=OAV
los
Short Circuit Output Current
Vcc = 5.0V, TA = 25°C
IccH
Supply Current. Outputs High
Vec = 5.25V, All Inputs at 2.0V,
V
V
V
204
-100
-0.1
-SOO
I1A
500
I1A
40
I1A
-1.6
mA
-30
mA
2S
mA
60
mA
Outputs Open
ICCL
Supply Current. Outputs Low
Vcc = 5.25V, All Inputs at O.SV.
Outputs Open
switching characteristics
tpLH
tpHL
Vee; 5.DV, T A ; 25°C
TYP
MAX
UNITS
Propagation Delay Time, Low-
RL = 37.11, (See ac Test Circuit
CL = 15pF
11
20
ns
to-High Level Output
and Switching Time Waveforms)
CL = 1000 pF
22
50
ns
Propagation Delay Time, High-
RL = 37.11, (See ac Test Circuit
S.O
20
ns
to-Low Level Output
and Switching Time Waveforms)
CL = 15 pF
CL = 1000 pF
20
50
ns
PARAMETER
CONDITIONS
MIN
...
MIN
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2; Unless otherwise specified minImax limits apply across the --55°C to +125°C temperature range for the 0555121 and across the aOc to
+70° C range for the DS75121. All typical values are for T A = 25° C and V CC = 5V.
Note 3: All currents into device pins shown as positive. out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
Note 4: The output voltage and current limits are guaranteed for any appropriate combination of high and low inputs specified by· the truth table
for the desired output.
3-67
N
N
....
Line Drivers/Receivers
U)
~
C
........
N
N
....
U)
U)
0555122/0575122 triple line receivers
en
c
general description
features
The DS55122/DS75122 are triple line receivers
designed for digital data transmission with line
impedances from 50n to 500n. Each receiver has
one input with built·in hysteresis which provides a
large noise margin. The other inputs on each
receiver are in a standard TTL configuration. The
DS55122/DS75122 are compatible with stanllard
TTL logic and supply voltage levels.
• Built·in input threshold hysteresis
• High speed ... typical propagation delay time
20 ns
• Independent channel strobes
• Input gating increases application flexibility
• Single 5.0V supply operation
• Fanout to 10 series 54/74 standard loads
• Plug-in replacement forlhe SN55122/SN75122
and the 8T14
connection diagram
truth table
Dual·ln-Line Package
INPUTS
R
A
8t
S
OUTPUT
V
L
H
H
X
X
X
X
L
H
L
L
X
H
X
H
L
X
X
L
H
x
L
H
X
H
X
L
X
L
H
H '" high level. L '" low level, X'" irrelevant
ta inpu~ and last two lines of the truth tabee
are applicable to receive" 1 and 2 only.
At
at
RZ
5Z
AZ
az
TOP VIEW
Order Number DS55122J,
DS75122J, DS75122N or
DS55122W
ac test circuit and switching time waveforms
Vee
z.&V
$5.0 ..
,.6v---l-Jr=-=i
1NlD64
INPUT
>O--!-_+--.-OUTPUT
v... ---l-r--""""'\
OUTPUT
v.,
'::'
Note I: The pidst,eneratorhastftefoUowingcilaracteristics:
ZoUT ~ son, tw '" 200 ns, duty cycl~ .. 50%, t, ,. tt '" 5.0 ns.
Not.2: CL includes probe and jig taplcitance.
3·68
absolute maximum ratings
Supply Voltage, Vee
Input Voltage
R Input
A, S, or S Input
Output Voltage
operating conditions
(Note 1)
6.0V
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
electrical characteristics vcc
MIN
MAX
4.75
5.25
UNITS
V
Operating Temperature, T A
6.0V
5.5V
6.0V
±l00rnA
600rnW
-£5°e to +150o e
3000 e
Output Current
Power Di~sipation
-55
0
D555122
D575122
High Level Output Current,
+125
+75
°e
°e
-500
I'A
16
rnA
IOH
Low Level Output Current,
IOL
= 4.75V to 5.25V (unless otherwise noted) (Notes 2 and 3)
PARAMETER
V,H
Supply Voltage, Vee
CONDITIONS
MIN
TVP
MAX
UNITS
High Level Input Voltage
A, B, R, or 5
Low Level I nput Voltage
A, B, R, or 5
Hysteresis
Vee = 5.0V, T A = 25°C, R,(Note 61
V,
Input Clamp Voltage
Vee = 5.0V, I, = -12 rnA, A, B, or S
-1.5
V
I,
Input Current at Max Input Voltage
Vee = 5.25V, V ,N = 5.5V, A, B, or 5
1.0
mA
V OH
High Level Output Voltage
V,L
~
VT+-V T _
2.0
V ,H = 2V, V ,L
10H = -500MA
0.3
= o.av, (Note 4)
VI{A} - OV, VUB} -
av.
V"A) = 1.45V, V"S) = 2.0V, (Note 71
Low Level Output Voltage
VOL
=
16 rnA
2.6
V
2.6
V
VI(Al = OV, V HS );::;: OV,
V'(A)
V,
High Level I nput Current
V
V
0.6
V ,H = 2.0V, V ,L = o.av, (Note 41
IOL
I'H
V
o.a
= 1.45V, V"S) = 2.0V, (Note a)
= 4.5V, A, B, or S
V, = 3.aV, R
0.4
V
0.4
V
40
I'A
170
MA
I'L
Low Level I nput Current
V, = O.4V, A, B, or S
-{),1
-1.6
los
Short Circuit Output Current
Vee
= 5.0V, T A
-50
-100
mA
Icc
Supply Current
Vee
= 5.25V
72
mA
switching characteristics
= 25°C, INote 51
mA
Vcc = 5.0V, T A = 25°C
PARAMETER
CONDITIONS
MIN
TVP
MAX
UNITS
tpLH
Propagation Delay Time, Low-to-H igh
Level Output from R Input
(See ac Test Circuit and Switching
Time Waveforms)
20
30
ns
tpHl
Propagation Delay Time, High·to-Low
Level Output from R Input
(See ac Test Circuit and Switching
Time Waveforms)
20
30
ns
Note 1: Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: All currents into device pins are shown as positive, currents out of device pins shown as negative, all voltage values are referenced with
respect to network ground terminal, unless otherwise noted. All values shown as·max or min on absolute value basis.
Note 3: Min/max limits apply across the guaranteed operating temperature range of -5SoC to +125 °c for 0555122 and O°C to +75°C for
0575122, unless otherwise specified. Typicals are for Vec = 5.0V, TA = 25°C. Positive current is defined as current into the referenced pin.
Note 4: The output voltage and current limits are guaranteed for any appropriate combination of high and low inputs specified by the truth table
for the desired output.
Note 5: Not more than one output should be shorted at a time.
Note 6: Hysteresis is the difference between the positive going input threshold voltage, VT+, and the negative going input threshold voltage, VT-·.
Note 7: Receiver input was at a high level immediately before being reduced to 1.45V.
Note 8: Receiver input was at a low level immediately before being raised to'1.4SV.
II
3·69
N
N
....
It)
typical performance characteristics
Ci
c
.......
N
N
Output
It)
~
....
It)
4.0
CIl
C
3.0
~
2.5
;::
2.0
vs Receiver Input Voltage
Jcc !s.dv
3.S
~
Volta~.
NO LOAD
TA ;:+25"C
Q
=
~ 1.5
I
VT_
Vp
1.0
o.s
o
o 0.2
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
V, -INPUT VOLTAGE IV}
typical applications
L __ '!!!S~2_ _ ..J
15
75 COAXIAl.~§LE
15 COAXIAL CABLE
L __ '~S~2 _ _ .J
15
-= L __
Single-Ended Party Line C,ircuits
INPU~
V,"~
v"
.'
VT+
VT._ .
VOH-r-I
OUTPUT
.. ~
Voe
L-
The high gain and built-in hysteresis of the OS55122/D815122
lilll! receivers enable them to be used as Schmit! triygers in
squaring up pulses.
Pulse ,squaring
3·70
'~S7!::2
__ ..J
~
Line 0 rivers/Receivers
NATIONAL
0575123 dual line driver
general description
features
The DS75123 is a monolithic dual line driver
designed specifically to meet the 1/0 interface
specifications for IBM System 360. It is com·
patible with standard TTL logic and supply voltage
levels.
• Meet IBM System 360 1/0 interface specifica·
tions for digital data transmission over 50n to
500n coaxial cable, strip line, or terminated
pair transmission lines
The low·impedance emitter·follower outputs of
the DS75123 enable driving terminated low im·
pedance lines. In addition the outputs are un·
commited allowing two or more drivers to drive
the same line.
• 3.11V output at IOH ; -59.3 mA
• TTL compatible with single 5.0V supply
• Open emitter-follower output structure for
party·line operation
• Short ci rcu it protection
• AND·OR logic configuration
Output short·circuit protection is incorporated
to turn off the output when the output voltage
drops below approximately 1.5V.
• Plug·in replacement for the SN75123 and the
8T23
typical performance
characteristics
connection diagram
DuaHn-Line Package
f2
16
E2
D2
C2
B2
.2
Y2
Output Current, vs Output Voltage
-300
14
15
Vee'" 5.0V
C( ~250
...
~ ~200
g;
u
-150
g~
-101)
~
01
E1
F1
Y1
I
-
I)tti-
1\
I
-.
o
C1
I
I
.2 -50
B1
"\.
!
I··+-t-
--
.
I
I
"
V1H '" 2.0V
TA"'25"C
I
.§
\1 1 I
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Vo - 0 UTPUT VOLTAGE (V)
GNO
TOP VIEW
truth table
Order Number OS75123J
Order Number OS75123N
OUTPUT
INPUTS
A
B
C
D
E
F
H
H
H
H
X
X
X
X
X
X
H
H
All Other Input Combinations
H = high level, L
=
y
H
H
L
low level, X = irrelevant
ac test circuit and switching time waveforms
l.OV
:;;!i.Ons
3.0V -1~.k-=-="INPUT
>--+-....- -....-0 OUTPUT
C,
(NOTE 2)
OUTPUT
Note 1:
THE PULSE GENERATORS HAVE THE FOLLOWING CHARACTERISTICS:
lQUT ""
son,
tw '" 200 ns, DUTY CYCLE'" 50%.
Note 2: CL INCLUDES PAD BE AND JIG CAPACITANCE.
3·71
absolute maximum ratings
operating conditions
(Note 1)
.,
Supply Voltage, VCC
Input Voltage
Output Voltage
Power Dissipation
Opereting Free·Air Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
7.0V
5.5V
7.0V
600mW
to +75°C
-65°C to +150°C
300°C
electrical characteristics
(Notes 2 and 3)
Supply Voltage, VCC
High Level Output Current,
10H
Temperature, T A
etc
PARAMETER
CONDITIONS
"
MIN
MIN
MAX
4.75
5.25
-100
0
+75
TYP
MAX
V'H
High Level Input Voltage
V'L
Low Levell ~put Voltage
V,
Input Clamp yoltage
Vee =5.0V,I, =-12mA
-1.5
I,
Input Current at Max Input Voltage
Vee = 5.25V, V'N = 5.5V
1
VOH
High Level Output Voltage
Vee = 5.0V, V'H= 2.0V,
10 ,:, = -59.3 mA, (Note 4)
10H
2.0
=
High Level' Output Current
Vee = 5.0V, V'H = 4.5V, TA = 25°C, •
VOH = 2.0V, (Note4)
3.11
-250
Low Level Output VoltalJll
V'L = 0.8V, 10L = -2401'A, (Note 4)
0.15
Off State Output Current
Vee = 0, Vo = 3.0V
40
High Level Input Current'
V, =4.5V
Low Level Input Current
V, =0.4V'
los
Short Circuit Output Current
Vee = 5.0V, TA = 25°C
ICCH
Supply"Current, Outputs High
Vee = 5.25V, All, Inputs at 2.0V, Outputs Open
leeL
Supply Current, Outputs Low
Vee = 5.26V, All Inputs at 0.8V, Outputs Open
switching characteristics
Propagation Delay Time, Highto-Low Level Output
-0.1
CONDITIONS
Propagation Delay Time, Lowto-High Level Output
IFHL
V
V
mA
mA
V
I1A
40
I1A
-1.6
mA
-30
mA
28
mA
60
mA
Vee =5.0V, TA = 25°C
PARAMETER
tpLH
UNITS
V
-100
VOL
I'H
°c
V
2.9
1010FF)
I'L
V
mA
V
0.8
ITA 25°C
ITA = O°C to +75°C
UNITS'
,
TYP
MAX
UNITS
RL ~ 500, (See ac Test Cireu,it
and Switching Time Waveforms
C L = 15 pF
12
CL = 100 pF
20
20
35
ns
ns
RL = 500, (See ae Test Circuit
C L = 15 pF
C L = 100 pF
12
15
20
25
ns
'and Switching Time Waveforms
MIN
ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device ,cannot be guaranteed. Except for "Operating
Temperature Range" they are not meaot to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
! p,rovides conditions 'for actual device operation.
Note 2: All eurrents,into device pins are shown as positive, currents out of device pins shown as negative, ali voltage values are referenced with
respect to network ground terminal, unless otherwise noted. All values sho",," as max or min on absolute value basis.
Note 3: Minimax limits apply across the guaranteed operating temperature range of etc to +75"C'for DS75123, unless otherwise specified. Typicals are for VCC = 5.0V, T A = 25° C. Positive current is defined as, current into the referenced pin.
'
Nota' 4: The output \fOltage and current limits are guaranteed for any appropriate combination of high' and low inputs specified by the truth table
for the desired output.
"
3-72
.~
Line Drivers/Receivers
NAllONAL
0875124 triple line receivers
general description
features
The OS75124 is designed to meet the input/
output interface specifications for IBM System
360. It has built·in hysteresis on one input on
each of the three receivers to provide large noise
margin. The other inputs on each receiver are in
a standard TTl,. configuration. The OS75124 is
compatible with standard TTL logic and supply
voltage levels.
•
•
•
•
•
•
Built·in input threshold hysteresis
High speed .. typ propagation delay time 20 ns
Independent channel strobes
Input gating increases application flexibility
Single 5.0V supply operation
Plug·in replacement for the SN75124 and the
8T24
connection diagram and truth table.
Dual·ln·Line Package
OUTPUT
INPUTS
A
at
R
S
Y
H
H
X
X
L
X
X
X
X
L
H
H
X
X
L
L
H
X
L
X
L
L
H
H
H
H
L
L
X
X
H" high level, L = low level, X = irrelevant
fa input and last two lines of the truth table
are applicable to receivers 1 and 2 only.
TOP VIEW
Order Number DS75124J
Order Number DS75124N
typical application
A
B
C
o
95 COAXIAL CABLE
r - - - - - - -,I
r+~-r~~~~~~~
B---"_J
":" L __ '~7~ _ _ .J
3·73
absoh,lte maximum ratings
"
operating conditions
(Note 1)
,
,
,
'.,
MIN
Supply Voltage, V CC
Input Voltage
R" Input with VCC Applied
R Input with VCC not Applied
A, B, or S Input
Output Voltage
Output Current
Power Oissipation
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
electrical characteristics
7.0V
7.0V
6.0V
.5.5V
7.0V
±100mA
600mW
etc to +75°C
-:66°C to +150°C
300°C
V'H
V'L
Low Level Input Voltage·
A,B,orS
0
Hysteresis
Vee
V,
Input Clamp Voltage
Vee
I,
Input Currentlat Maximum
Vee
Input Voltage
R
"
V OH
,-800
,
V
p.A
16
mA
+75
°c
"
MIN
TYP
MAX'
= 5.01i. TA = 25°C. R, (Note 6)
= 5.0V.I, =-12 mA, A. B. or S
= 5.25V. V'N = 5.5V. A, B. or S
I V, = 7.0V
I V, = 6.0V;Vee = 0
High level Output Voltage
V'H = V'HM'N, V'L
(Note 4)
VOL
L;;'w Level Output Voltage
V'H
I'H
High level Input Current
V,
I'L
Low Level Input Current
V,
los
Short Circuit Output Current
Vee
Icc
Supply Current
0.2
= V'LMAX' IOH =-BOOp.A,
= V'NM'N. V'L = V,lMAX. IOL = f6 rnA,
= 4.5V·. A. B. or S
V
0.8
0.7
V
-1.5
V
1
5.0
5.0
rnA
rnA
0.4
V
V
rnA
V
2.6
0.4
V
40
170
p.A
p.A
-{J.l
-1.6
rnA
~O
-100
rnA
72
rnA
(Note 4)
V,=3.11V,R
= 0.4V. A. B. or S
= 5.0V. TA = 25°C. (Note 5)
Vee = 5.25V
UNITS
V
2.0
1.7
R
VT+-VT-
UNITS'
,
CONDITIONS
A,B.orS
R
,.r"
MAX
,5.25
-
(Notes 2' and 3)
PARAMETER
High Level Input Voltage
',4.75
Supply Voltage, VCC
High Level Output current,
IOH
Low Level Output Current,
,IOL
pperatihg Temperatur,,; TA
"
.switching characteristics
"
tpLH
tpHL
PARAMETER
CONDITIONS
Propagation Delay Time. low·to-High
level Output from R Inpu~
Time Waveforms)
Propagation Delay Time. High-to·low
Level Output from R Input
Time Waveforms)
(See ac Test Circuit and Switching
(See ae Test Circuit and Switching
MIN
TYP
MAX
UNITS
20
30
ns
20
30
ns
Note 1: "Absolute, Maximum Ratings" are those values beyond which the safety of the device cannot, b.e guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at th~se limits. The table of "Electrical Charct?teristics"
provides conditions for actual device operation.
Note 2: All currents into device pins are shown as positive, currents out of device pins shown as negative, all voltage 'Values are referenced with
re$ipect to network gro,un"d' termin~l. unless otherwise noted. All values shown' as max or min on absolute value basis.
Note 3: Minimax. iimits apply across the guaranteed operating temperature range of 0° C to +7~C for DS75'124, unlesS otherwise specified. Typicals are ,for VCC : 5.0V, T A: 25°C. Positive current is defined as current into t~e referen~d pin.
Note 4: The output voltage and current limits are guara."teed for any appropriate c0lT!bination of high and low inputs specified by the truth table
for the desired output.
Note 5: Not more than one output should be shorted at a time_
Note 6: Hysteresis is the difference between the positive going input threshold voltage, VT+, and the negative going input threshold voltage, VT--
3-74
ac test circuit and switching time waveforms
Vee
2.6V
r-------,
84.5
I
lN3064
)O-+--....- -...-OUTPUT
5.0k
(NOTE 2)
Note1: THE PULSE GENERATOR HAS THE FOllOWING CHARACTERISTICS:
DUTY CYCLE' 50%.
Note 2: CL INCLUDES PROBE AND JIG CAPACITANCE.
louT"" SOH. tw = 200 ns,
:::; 5.0 115
2.6V
INPUT
VOH
OUTPUT
VOL
typical performance characteristics
Output Voltage Y'
Receiver Input Voltage
4.0
2
~
~
~
"
!;
~
I
0
>
Sec ~ 5.riV
3.5
NO LOAD
TA = 25"C
3.0
2.5
2.0
VT _
Vp
1.5
1.0
0.5
o
o
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
V, - INPUT VOLTAGE (V)
3-75
~
Line Drivers/Receivers
NA110NAL
0575150 dual line driver
general description
·features
The 0575150 is a dual monolithic line driver designed
to satisfy the requirements of the standard interface
between data terminal equipment and data communication equipment as defined by EIA Standard RS-232-C"
A rate of 20,000 bits per second can be transmitted with
a full 2500 pF load. Other applications are in datatransmission systems using relatively short single lines,
in level translators, and for driving MOS devices. The
logic input is compatible with most TTL and OTL
families. Operation is from -12V ancf +12V power
supplies.
• Withstands sustained output short-circuit to any
low impedance volta.ge· between -25V and +25V
• 2J.lS max transition time through the -3V to +3V
transition region under full 2500 pF load
• Inputs compatible with most TTL and OTL families
• Common strpbe input
• Inverting output
• Slew rate can be cpntrolled with an external capacitor
at the output
• Standard supply' voltages
±12V
schematic and connection diagrams
....,o-or---Hl
vQH
B
-31i
~"H'
10%
-10
VI = 2.4V
-Vee" -12V
TA =25°C
---
~
1-'-,-
Of
I
3-78
=7k
rr
V, 'OAV
'3V
-3V
tTLM
-20
-25
-15
-5
0 5
15
25
Vo -APPLIED OUTPUT VOLTAGE IV)
Note 1: The pulse generator bas the foHowing eharaetlUistics: duty eyele S; 50%, ZOUT '" 50n.
Note 2: Cl ineludn probe 80d jig capacitance.
FIGURE 6.
RL
.E -15
tplH
--l
0
-5
+Vcc -12V
FIGURE 7.
,
~
Line Drivers/Receivers
NAnONAL
OS75154 quadruple line receiver
general description
The DS75154 is a quad monolithic line receiver
designed to satisfy the requirements of the standard
interface between data terminal equipment and data
communication equipment as defined by EIA Standard
RS-232C_ Other applications are in relatively short,
single-line, point-to-point data transmission systems and
for level translators_ Operation is normally from a single
5V supply; however, a built-in option allows operation
from a 12V supply Without the use of additional components_ The output is compatible with most TTL and
DTL circuits when either supply voltage is used_
the negative-going threshold voltage to be above zero_
The positive-going threshold voltage remains above zero
as it is unaffected by the disposition of the threshold
terminals_ In the fail-safe mode,if the input voltage goes
to zero or an open-circuit condition, the output will go
to the high level regardless of the previous input condi'
tion_
features
In normal operation, the threshold-control terminals are
connected to the VCC1 terminal, pin 15, even if power is
being supplied via the alternate VCC2 terminal, pin 16_
This provides a wide hysteresis loop which is the difference between the positive-going and negative-going
threshold voltages_ In this mode, if the input voltage
goes to zero, the output voltage will remain at the low or
high level as determined by the previous input_
•
•
•
•
•
For fail-safe operation, the threshofd-control terminals
are open_ This reduces the hysteresis loop by causing
•
Input resistance, 3 kn to 7 kn over full RS-232C
voltage range
Input threshold adjustable to meet "fail-safe" requirements without using external components
Inverting o~tput compatible with DTL or TTL
Built-in hysteresis for increased noise immunity
Output witp active pull-up for symmetrical switching
speeds
Standard supply voltage-5V or 12V
schematic and connection diagrams
------,
COMMON TO 4 CIRCUITS
V~,
(NQTE)
I
I
I
I
I
V~'o-4-------+
., 0--'-.,---.....""'.....
GNOo-T"------t--4
Dual~ln~Line
THRESHOLD
I
AlT
NORM
v=
Vee!
CONT
4T
Package
OUTPUTS
,.---~~--ZY
3Y
1Y
4'
.,
I
-------,
. . : :- '
Uk
1 Of 4 RECEIVERS
I
I
1.6k
I
I
I
OUTPUT
GND
THRESHOLD
CONTROLS
4.2k
INPUT
o--I-MIV--I-"4H
TOP VIEW
I
1k
I
IL
_______ -
Order Number DS75154J
or DS75154N
_ _ _ _ .J
Note: When using Vee1 (pin 15), VCC2 (pin 16) may be left open or shorted to Vee1 .
When using VCC2 • Vee1 must be left open or connected to the thre$hold control pins.
3-79
absolute maximum ratings
Normal Supply Voltage (Pin 15l.(VCC1)
Alternate Supply Voltage (Pin 16),(VCC2)
Input Voltage
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
operating conditions
(Note 1)
7V
14V
±25V
-6SoC to +150°C
300°C
Alternate Supply Voltage (Pin 16)
(VCC2)
electrical characteristics (Notes
(Figure 1)
V'L
Low·Level Input Voltage
(Figure 1)
VT+
Positive·Going Threshold Voltage
V
"c
(Figure 1)
V
-3
V
3
V
2.2
3
V
-1.1
0
V
-3
Fail·Safe Operation
0.8
1.4
3
V
Normal Operation
0.8
3.3
6
V
Fail·Safe Operation
0
0.8
2.2
V
2:4
3.5
Low·Level Output Voltage
10L = 16 rnA, (Figure 1)
Input Resistance
V
0.23
0.4
AV, =-25Vto-14V
3
5
7
kQ
AV, - 14V to 3V
AV, - -3V to +3V
3
5
7
3
6
kQ
kQ
AV, - 3V to 14V
3
5
7
k'2
AV, - 14V to 25V
3
5
7
k'2
(Figure 2)
.
V'(OPEN)
Open·Circuit Input Voltage
I, = 0, (Figure 3)
los
Short·Circuit Output Current
(Note 5)
Vcc , = 5.5V, V, =-5V, (Figure 4)
ICCl
Supply Current From Vcel
VCCl = 5.5V, T A = 25° C, (Figure 5)
Icc2
Supply Current From VCC2
VCC2
= 13.2V,
0
-10
T A = 25°C, (Figure 5)
0.2
2
V
V
-20
-40
mA
20
35
mA
23
40
mA
TYP
MAX
UNITS
= 5V, TA = 25°C)
CONDITIONS
Propagation Delay Time, Low·to·High
UNITS
2.2
r,
PARAMETER
MAX
0.8
VOL
(V CC1
TYP
0.8
10H =-400pA, (Figure 1)
tpLH,
±15
+70
Fail·Safe Operation
Normal Operation
(Figure 1)
Hysteresis
switching characteristics
V
Normal Operation
High· Level Qutput,Voltage
VOH
13.2
3
(Figure 1)
Negative·Going Th,,;shold Voltage
VT+-V T _
V
10.8
0
MIN
' CONDITIONS
PARAMETER
VT _
5.5
2,3 and 4)
High·Levellnput Voltage
V'H
MAX
4.5
Input Voltage
Temperature, (TA)
UNITS
MIN
Supply Voltage (Pin 15),(VCC1)
MIN
C L = 50 pF, RL
=390'2,
(Figure 6)
22
ns
CL = 50 pF, RL
=390'2, (Figure 6)
20
ns
CL = 50 pF, RL
= 390'2. (Figure 6)
9
ns
C L = 50pF, R L " 390'2, (Figure 6)
6
ns
Level Output
tpHL
Propagation Delay Time, High·to·Low
Level Output
tTLH
Transition Time, Low·to·High Level
Output
tTHL
Transition Time, High·to·Low Level
Output
"AbSOI~ie
val~es
devic~ canno~
Exce~t
Not. 1:
Maximum Ratings" are 'those
beyond which the safety of the
be guaranteed'.
for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these' limits. The table of "Electrical Characteristics','
provides conditions for actual device ·operation.
.
.
Note 2: Unless otherwise specified minImax limits apply across the aOc to +70°C range for the OS75154. All typical values are for T A = 2SoC and
VCC! =5V.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
Note 4: The algebraic convention where the most~positive (least-negative) limit is designated as maximum is ,used in this data sheet for logic and
threshold feve1s only. e.g., when -3V is the maximum, the minimum Hmit is a more-neg~tive voltage.
Not. 5: Only one output at a time should be shorted.
3-80
dc test circuits and truth tables
5.5V
o 13.ZV
0
Vee,
IPIN 151
y
VCC2
MEASURE
Open·Circuit 1nput
(fail-safe)
V OH
V OH
Open
Open
Open
10H
10H
Open
Open
lO.BY
VT+ min,
V T _ (fail-safe)
V OH
O.BV
Open
10H
5.5V
Open
V OH
O.BV
Open
10H
Open
13.2V
V OH
Note 1
Pin 15
10H
5.5V and T
Open
V T + min (Normal)
A
T
TEST
Open
IPIN 161
4.5V
V OH
Note 1
Pin 15
10H
T
13.2V
V It• max,
V T _ min (Normal)
V OH
-3V
Pin 15
10H
5.5V and T
Open
V OH
-3V
Pin 15
10H
T
13.2V
V 1H min, V T + max,
VOL
3V
Open
10L
4.5V
Open
VT_ max (fail-safe)
VOL
3V
Open
10L
Open
10.BV
V 1H min, V T + max
VOL
3V
Pin 15
10L
4.5V and T
Open
(Normal)
VOL
3V
Pin 15
10L
T
10.BV
VOL
Note 2
Pin 15
10L
5.5V and T
Open
VOL
Note 2
Pin 15
10L
T
13.2V
V T - max (Normal)
Note 1: Momentaroly apply -5V. then O.BV.
Note 2: Momentarily apply 5V. then ground .
.'~JO l~"
(Pin 15)
OPEN
-
15
16
-V ee1 VCC2 -
"'.>-----1
v,
'Vee',
T
.1Rl-,
~><>---!.I-OOPEN
VCC2
IPin 161
Open
5V
Open
Open
Gnd
Open
Open
Open
Open
Pin 15
T and 5V
Open
Gnd
Gnd
Open
Open
Open
12V
Open
Open
Gnd
Pin 15
T
12V
Pin 15
T
Gnd
Pin 15
T
Open
FIGURE 2. rl
T
Open
Pin 15
>-----1 "':>o---!.I-o OPEN
~
VI(OPENI
L
Open
Pin 15
I
---~-----'
FIGURE 3. VI(OPEN} .
Veel
VeC2
(Pin 15)
IPin 161
5.5V
S.5V
Open
Open
T
13.2V
13.2V
Open
dc test circuits (con't)
5.5VJt<:.
Iccl
9
5 V,
OPEN
-
OPEN
I.!.L
-VCC1
OPEN
..J16
L
Vcc:-- R'"fl
-
OPEN
.r
y
"'V
~
__
T
15
Vee1
_
-J
0--013.2V
Icct
~ OPEN
16_L
V
All
CC2
>-.,...---1 ';>o---'-t-OOPE'
5V
Ea~h output is tested separate lV,
All four line receiVllrs are tested simultaneously_
FIGURE 5. ICC
FIGURE 4. lOS
ac test circuit and switching time waveforms
5V
INPUT
OUTPUT
OPEN
_
15_
Vee1
PULSE
GENERATOR
(NOTE 11
OPEN
...l!6_...l .
VCC2
Rl - ,
y
L---r----.J
,
T
.
~
Cl =: 50 pF
(NOTE 2)
~
5V----~~~~~-~~
INPUT
OV
------j:fi
-5V
VOH
----="-
OUTPUT
Note 1: The pulse generator has the following characteristics:
Note 2: CL includes probe and jig capacitance
ZOUT "'
son, tw '" 200 ns, duty cvcle:<;; 20%.
FIGURE 6.
typical performance characteristics
Output Voltage v.
Input Voltage
I
-
-
FAlllsAFE
OPERATION
I
vT -
(NOTE 3)
1
vT •
-VT
NORMA~J.
i-oPEIRATlI"
~
o
-3
-2
-1
INPUT VOLTAGE (V)
J,82
-
o
(/)
o
o
Memory/Clock Drivers
~
N
C1I
......
C
NAT10NAL
(/)
OS0025/0S0025C two phase MOS clock driver
N
C1I
o
o
(")
general description
features
The DS0025/DS0025C is monolithic, low cost,
two phase MOS clock driver that is designed to be
driven by TTL/DTL line drivers or buffers such as
the DM932, DS8830 or DM7440. Two .input
coupling capacitors are used to perform the leVel
shift from TTL/DTL to MOS logic levels. Optimum
performance in turn-off delay and fall time are
obtained when the output pulse is logically. con·
trolled by the input. However, output pulse widths
may be set by selection of the input capacitors
eliminating the need for tight input pulse control.
•
8·lead TO·5 or 8·lead dual·in·line package
•
High Output Voltage Swings-up to 30V
• High Output Current Drive Capability-up to
1.5A
•
Rep. Rate: 1.0 MHz into> 1000 pF
•
Driven by DM932, DS8830, DM7440 (SN7440)
• "Zero" Quiescent Power
connection diagrams
D~al-In-line
M,etal Can Package
v'
Package
8 NC
NC I
INPUT A 2
-+---1'>:---1-- 7
v- 3
v-
INPUT 8 4
OUTPUT A
6 v'
-+--..1:::>0---.....-5
OUTPUT B
Note: Pi" 4 connected to case.
TOP VIEW
TOPVIEW
Order Number DS0025H or DS0025CH
Order Number DS0025CN
typical application
timing diagram
L.___,.
.
~
-
5V
~
ac test circui1;
'ctockpulse
8. JnputpulseWldth
se.tsdockpulse
width
•
Ctoc~pLllse
output
£J
~gO% -
10%
~
-----.v
Y'N
_______
\tON
111%
50%
itdOFF
10%
5(1%
'v
V3 MOV
VOUT
Input waveform:
PRR"'O.5MHz
"""'"';;........;.;."-1--+----~.- v~
-16V
Vp.p= 5.0V
t,"'t,::O;10n5
"Ql is selected high speed NPNswitchingtransistor.
Pullewidth:
A. 1.0/15
B.2DOns
4-1
(J
It)
absolute maximum ratings
N
o
o
(Note 1)
(V+ - V ) Voltage Differential
Input Current
Peak Output Current
Storage Temperature
Operating Temperature DS0025
DS0025C
Lead Temperature (Soldering, 10 sec)
til
o
.......
It)
N
o
o
q)
o
electrical cha racteristi~s
30V
100mA
1.5A
_65°C to H50°C
-55°C to +125°C
O°C to +85°C
300°C
INotes 2 and
PARAMETER
:n ~ee test circuit.
CONDITIONS
TYP
MAX
UNITS
tdON
Turn·On Delay Time
C 'N
= O.OO1/lF, R'N = on, CL = O.OO1/lF
15
30
ns
t R1SE
Rise Time
C 'N
= O.OOlI'F, R'N = on, CL = O.OO1/lF
25
50
ns
t"OFF
Turn·Off Delay Time
C 'N = O.OO1/lF, RON =
(Note 4)
on, CL = 0.0011'F,
30
60
ns
tFALL
Fall Time
C 'N = O.OOlI'F, R'N
CL = O.OO1/lF
90
150
120
250
ns
ns
= on,
PW
Pulse Width (50% to 50%)
C'N = O.OO1/lF, R'N = on,
CL = 0.0011'F (Note 5)
Vo+
Positive Output Voltage Swing
V,N
= OV, lOUT = -1 mA
Vo_
Negative Output Voltage Swing
l'N
= 10 mA, lOUT = 1 mA
MIN
I
I
(Note 4)
(Note 5)
60
100
ns
500
V+-1.0
V+-o.7V
V
V- +0.7V
V-+1.5V
V
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except ~for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified min/max limits apply across the -55°C to +125°C temperature rang. for the 050025 and across the O°C to
+70°C range for the D50025C.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
Note 4: Parameter values apply for clock pulse width determined by input pulse width.
Note 5: Parameter values for input pulse wroth greater than output clock pulse width.
typical perfmmance
Transient Power vs Rep. Rate
400
Cl
ji
DC Power (POC)
110
Cl'IOOOpf
c~
Iz
_"JSfJ pF
II / 1/ 4~
V
0:
~...
Cl .15DOpf
1-'
300
.!
-2000';1
ZOO
i
Cl ,J50PF
:...
100
0
•
...2co
40
~
v· - V' ~ l&V
.5
Z.o
1.5
1.0
I /
I /
I
/
10
60
zo
L~
~
0
10
ZO
PULSE REPETITION RATE (MHz;
PAC;: (V+ ~ V-)2f Ci..
~ 2100
~ 2400
"~
2000
U 1600
:f
.
..'"
;312~
!:l
100
400
0
~
1\
\\
~,
K.
V
...uc:,v·_\/
"'.......-
·n c
=/~~~:;:~l:;~~Y
F"""
....
4-2
Y' _ V-
=
OUTPUT 'UlS£ WlOTM "''''UT'UlSE .G'"
nus .....
I
700
i
.~ IDO
i<
r--...
l"- .....;
V-), (OC) ,; ~
II) '!lI'Y' _ V-)'
I
..
fREQUENCY (MHz)
L
900
...:z:
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.1 2.0
C ,; (P.... ) (1k) - (V' -
70 IS
OUlPUnULSE WlOlK VI. c... FOR LONG;
I/IIPUT'ULSlS.
FOFlIUU'PUU.J.\
30
X
/Y'-)'IJV-
DUTY CYCLE (%1
Maximum Load Capacitance
3200
-cpb
V
I
100
0:
..Ie
I
120
Q
./J. ~ / ' ,,:::. ~ ~l'200pF
.....
140
Q
/ / / V
'II Y ./
~
~
z
in
.5 Duty Cycle
v' - V-· ZOvl
V
.J...!...~• ..... ":!"'t--
t--
t-t--
I-
GIUVfR
I:;;
~r::::
~
300
5IO'UUU,
,.
1
f"
100
200
IDO
1000 1400
lIDO 2280
CIN (pF)
'MAX" Peak cunent tIeIivlU'e. by driver
IMIN~~a~
c
applications information
en
o
Circuit Operation
.......
o
N
U1
Input current forced into the base of Q1 through the
coupling capacitor CIN causes Q 1 to be driven into
saturation, swinging the output to V- + VCE(sat) +
VOiodeo
When the input current has decayed, or has been
switched, such that Q 1 turns off, Q 2 receives base
drive through R2, turning Q 2 on. This supplies
current to the load and the output swings positive
to V+ - VSE'
It may be noted that Q 1 must switch off before
Q 2 begins to supply current, hence high internal
transients currents form V- to V+ cannot occur.
J
. - -.....-0,.
1...,....c,.
I
r~;
l:)'
+-~""'-oOUTPUT
culations to enable the fan-out to be calculated
for any system condition.
C
en
o
o
Transient Current
N
U1
The maximum peak output current of the OS0025
is given as 1.5A. Average transient current required
from the driver can be calculated from:
o
(1)
Typical rise times into 1000 pF load is 25 ns
For V+ - V- = 20V, I = 0.8A.
Transient Output Power
The average transient power (Pac) dissipated, is
equal to the energy needed to charge and discharge
the output capacitive load (C L ) multiplied by the
frequency of operation (f).
PAC = C L
X
(V+ - V-)2
X
f
(2)
For V+ - V- = 20V, f = 1.0 MHz, C L = 1000 pF,
PAC = 400 mW.
Internal Power
"0" State
FIGURE 1. OS0025 Schematic lOne-Half Circuit)
Negligible «3 mW)
"1" State
(3)
Fan-Out Calculation
The drive capabil ity of the OS0025 is a function
of system requirements, i.e. speed, ambient temperature, voltage swing, drive circuitry, and stray
wiring capacity.
The following equations cover the necessary cal-
= 80 mW for V+ - V- = 20V, DC = 20%
Package Power Dissipation
Total average. power
internal power
=
transient output power +
example calculation
How many MM506 shift registers can be driven by
a OS0025CN driver at 1 MHz using a clock pulse
width of 200 ns, rise time 30-50 ns and 16V amplitude over the temperature range 0-70°C?
For one-half of the OS0025C, 870 mW
dissipated.
Power 0 issi pation:
385 mW = transient output power
At 70°C the OS0025CN can dissipate 870 mW
when soldered into printed circuit board.
Transient Peak Current Limitation:
From equation (1), it can be seen that at 16V and
30 ns, the maximum load that can be driven is
limited to 2800 pF.
Average Internal Power:
Equation (3), g.ives an average power of 50 mW at
16V and a 20% duty cycle.
7 2
can be
435 mW = 50 mW + transient output power
Using equation (2) at 16V, 1 MHz and 350 mW,
each half of the OS0025CN can drive a 1-367 pF
load. This is less than the load imposed by the
transient current limitation of equation (1) and
so a maximum load of 1367 pF would prevail.
From the data sheet for the MM506, the average
clock pulse load is 80 pF. Therefore the number
of devices driven is 1367/80 or 17 registers.
4-3
z
=
'"Iz-
....
1"
1"
.J'
~
'ON
l""
-I'"
tOFF
Vee :20V
CIN '" CL =: fOOD pF
54S00 ON INPUT
(FIGURE 21
Z
P'
§
I-
1
0
25
50
-50 -25
75 100 125
TEMPERATURE ('CI
INPUT VOLTAGE (VI
0
Fall Time vs Load
Capacitance
40
40
30
30
1w
:g
">=
20
~
~
~
a:
20
~
10
10
0
200
400
600
800
200
0
1000 1200
LOAD CAPACITANCE (pF)
J2400
2200
5~ '800
161'10
51400
~ 1280
1000
~ 800
:: &00
"1Z
p4---
O~~;:Z~-
i2
1/
/
.....r-
.....TRANSISTO~_
WITH 50 OHMS
.. ZOO I--- f..:...- ~
TO +5V DRIVING OS00260
8'
0 100 zoo 300 400 500 600 700 800
~ 400
I
:I!
4-6
OUTPUT PU I.SE WIDTH (n,1
1000
800
1200
Duty Cycle
400
v+ -V-=20V
T.=25"C
I--CL = 1000pF
LOGICALLY CONTROL~F---+PULSE (FIGURE 21, OM74S00-
600
DC Power (POC) vs
Recommended 'nput Coupling
~ 2000
400
LOAD CAPACITANCE (,FI
CajlaCitance
~
25
50
TEMPERATURE
Rise Time vs Load
Capacitance
!
~
~
v· -V-= ZOV
v+ -v- '" 17V
-75 -SO -25
0.5 1.0 1.5 2.0 2.5
>
Q
6.0
-1.0 -0.5
Z4
ZZ
ZO
18
16
14
IZ
10
8
]
I
c.. =0
8.0
a:
{
-2
DUTY CYCLE = 211%
f=1MHz
I- /
a
Turn-On and Turn-Off Delay
vs Temperature
Supply Current YS Temperature
Input Current vs Input Voltage
360
320
ia:
I
T.=25'C
CL =0
1
280
.. -V-=2OV_
"-V-'I7V"
240
"-V-=12~)(
200
~
1<. 160
V
1/
"Y
./
V
120
V
/.
80
40
1/
J
~
~
10
l>"
(.. - V-I' (DCI
Poc '" ~
20
30 40
SO
DUTY CYCLE (%1
60
70
80
75 100 125
rc)
c
en
schematic diagrams
o
o
N
en
v'
.6
c
en
.,
"
o
o
U1
.,
~
0'
....
en
.....
D':"
....
1-,.07
~O, ~
D9
D6
....
H+
.2
~O.
p~
1/20S0026
~
....
•J
~
~0Jl
~DU TPUT
1"\02
~
:"
....
••
~O.
_II- D1O
~
....
I
.,
10k
i
.7
~
v"
v'
.,
.6
.,
D1
....
1";"
~
I... 07
....
~n'
~
....
H+
.2
EXTERNAL
~O,
~"~ ~
~O,
D':'
1I20S0056
~
....
.
OJ
.....
~06
~ ~OU TPUT
j\q2
:"
OJ
~
••
....
~n4
"~D1D
D4
~
••
10k
I
.7
1
v-
4-7
co
~
ac test circuits and switching time waveforms
o
en
c'
co
.
N
o
o
+20V
en
c
+5V
INPUT
50
C'N
fOOpF
10dOpF
(
VIN =5V
PRF = 1 MHz
PW=O.5J.!s
f,. = It:::;; 10ns
),
:1:
-
5J.!F~
I [>0 I
I
::L
~O.'J.!F
o OUTPUT
Yl~"
':"
":'
INPUT
OUTPUT
'0.
":'"
FIGURE 1.
+2DV
+5V
V'N
!
PULSEGEN
INPUT
)o--~--II---+-i ~>O-+-'VVIt....._-fO)VOUT
C,
10DOpf
FIGURE 2.
typical applications
DC Coupled RAM Memory Address or Precharge
Driver (Positive Supply Only)
AC Coupled MOS Clock Driver
+l1Y
+5V
100pf
C1
~O'F
1
10DpF
TWO PHASE elK
cz
Dstl026CN
1000pF
~
54/74SERIES
GATES AND FLOPS
REGISTERS OR RAMS
1120M740D
-f2yl
4·8
DSOD26CN
TO SHIFT
l
TD ADDRESS
LINES ON '
MEMORY SYSTEM
c
en
application hints
o
o
DRIVING THE MM5262 WITH THE
DS0056 CLOCK DRIVER
N
en
The clock signals for the MM5262 have three requirements which have the potential of generating problems
for the user. These requirements, high speed, large
voltage swing and large capacitive loads, combine to
provide ample opportunity for inductive ringing on clock
lines, coupling clock signals to other clocks and/or
inputs and outputs and generating noise on the power
supplies. All of these problems have the potential of
causing the memory system to malfunction. Recognizing
the source and potential of these problems early in the
design of a memory system is the most critical step.
The object here is to point out the source of these
problems and give a quantitative feel for their magnitude.
Line ringing comes from the fact that at a high enough
frequency any line must be considered as a transmission
line with distributed inductance and capacitance. To
see how much ringing can be tolerated we must examine
the clock voltage specification. Figure 6 shows the clock
V~+l
Vos
__________________________
VDD +l
Voo
_____
/
.~~. ~':\.
VDo-l
~
/\.fo'---"
~
-\/\
•
'
·VTlMINI "Minimum threshold ,ologe.
FIGURE 6. Clock Waveform
specification, in diagram form, with idealized' ringing
sketched in. The ringing of the clock about the Vss level
is particularly critical. If the VSs - 1 VOH is not main·
tained, at all times, the information stored in the memory
could be altered. Referring to Figure 1, if the threshold
voltage of a transistor were -1.3V, the clock going to
Vss - 1 would mean that all the devices, whose gates
are tied to that clock, would be only 300 mV from
turning on. The internal circuitry needs this noise
margin and from the functional description of the RAM
it is easy to see that turning a clock on at the wrong
time can have disastrous results.
Limiting the inductance of the clock lines can be
accomplished by minimizing their length and by laying
out the lines such that the return current is Closely
coupled to the clock lines. When minimizing the length
of clock lines it is important to minimize the distance
from the clock driver output to the furthest point
being driven. Because of this, memory boards are
usually ~esigned with clock drivers in the center of
the memory array, rather than on one side, reducing the
maximum distance by a factor of 2.
en
Using multilayer printed circuit boards with clock lines
sandwiched between the V DO and Vss power plains
minimizes the inductance of the clock lines. It also
serves the function of preventing the clocks from coupling
noise into input and outpiJt lines. Unfortunately multilayer printed circuit boards are more expensive than
two sided boards. The user must make the decision as
to the necessity of multilayer boards. Suffice it to say
here, that reliable memory boards can be designed using
two sided printed circuit boards.
The recommended clock driver forme with the MM4262/
MM5262 is the DS0056/DS0056C dual clock driver.
This device is designed specifically for use with dynamic
circuits using a substrate, V BB , supply. Typically it will
drive a 1000 pF load with 20 ns rise and fall times.
Figure 7 shows a schematic of a single driver.
r---+-+OV"
EXTERNAL
C"
0:1
.6
hN,"0T....J>iVY--I
Controlling the clock ringing is particulary difficult
because of the relative magnitude of the allowable
ringing, compared to the magnitude of the transition.
In this case it is lV out of 20V or only 5%. Ringing
can be controlled by damping the clock driver and
minimizing the .line inductance.
Damping the clock driver by placing a resistance in
series with . its oUtput is effective, but there is a limit
since it also slows down the rise .andfall time of the
clock signal; B.ecause the typical clock· driver can be
much faster than the worst case driver, the damping
resistor serves the useful function of limiting the
minimum rise and fall time.' This is very important
because the faster the rise and fall times, 'the worse thb
ringing problem becomes. The size of the damping
resistor varies because.it is dependent on the details of
the actual application. It must be determined empirically.
In practice a resistance ofl0 ohms to 20 ohms is usually
optimum.
C
en
o
oU'1
.5
FIG U RE 7.
Sch.m.~ic
of 1/2 OS0056
In the case of the MM5262, V+ is a +5V and V BB is
+B.5V. V BB should be connected. to the V BB pin
shown in Figure 7 through a 1 kS1 resistor. This allows
transistor 04 to saturate, pulling the output to within a
V CE (SAT) of the V+ supply. This is critical because as
was shown before, the Vss - 1.0V clock level must not
be exceeded at any time. Without the V BB pull up on
the base of 04 the output at best will be 0.6V below
the V+ supply and can be 1V below the V+ supply
reducing the noise margin or this line to zero.
4·9
CD
an
g
application hints (cont')
en
c
Because. of the amount of current that the clock driver
must supply to its capacitive load, the distribution of
power to the clock driver must be considered. Figu~ 8
gives the idealized voltage and current waveforms for a
clock driver driving a 1000 pF capacitor with 20 ns
rise and fall time .
CD
N
8en
c
• 6Y
inductance, L, is also shown. Let us assume, for the sake
of argument, that Cc is 1 pF and that the rise time of
the clock'is high enough to completely isolate the·clock
tranisent from the 7404 because ot· the inductance, L.
-~---r---"""\
20"
FIGURE 9. Clock" Coupling
I,
---''---'-----+-oj---
-1 AMP _ _ _ _--,_ _ _ _
L~
+8.5V
1k
Cl X,;lV
Il=~
Io-'F· ZDV
" 20 lC 10-9~1!C '" lJ+.
FIGURE 8. Clock Waveforms (Voltage and Currant!
As can be seen the current is significant. This current
flows in theV oo and Vss power lines. Any significant
inductance in the lines will produce large voltage
transients on the power supplies, A bypass capacitor,
as close as possible to the clock .driver, is helpful in
minimizing this problem. This bypass is most effective
when connected between the Vss and Voo supplies. A
bypass capacitor for each DS0056 is recommended.
The size of the bypass capacitor depends on the amount
of capacitance being driven. Using a low inductance
capacitor, such as a ceramic or silver mica, is most
effective. Another helpful technique is to run the Voo
and Vss lines, to the clock driver, adjacent to each
other. This tends to. reduce. ~he li.nes inductance and
therefore the magnitude of the voltage transients.
While discussing the clock driver, it should be pointed
out that the DS0056 is a relatively low input impedance
device. It is possible to couple current noise into the
input without seeing a significant voltage. Since this
noise is difficult to detect with an oscilloscope it is
often overlooked.
Lastly, ·the clock
generators. Figure
parasitic coupling
lines being driven
4·10
lines must be considered as noi'se
9 shows a clock coupled through a
capacitor, Ct, to eight data input
by a 7404. A parasitic lumped line
With a clock transition of 20V the magnitude of the
voltage generated across CL is: .
Cc
V=20Vx--= 20Vx ( -1-)
CL +C c
56+1
0.35V
This has been a hypothetical example to emphasize
that with 20V low rise/fall time transitions, parasitic
elements can not be neglected. In this example, 1 pF
of parasitic capacitance could cause system malfunction,
because a 7404 without a pull up resistor has typically
only 0.3V of noise margin in the"l" state at 25°C.
Of courSe it is stretching things to assume that the
indwctance, L, completely isolates the clock transient
from the 7404. However, it does point out the need
to minimize inductance in input/output as· well as
cI ock lines.
The output is current, so it ,is more meaningful to
examine the current that is coupled through a 1 pF
parasitic capacitance. The current would be:
1 X 10- 12
X
20
20 X 10-9
= 1 mA
This exceeds the total output current swing so it is
obviously significant.
Clock coupling to inputs and outputs can be minimized
by using multilayer printed circuit boards, as mentioned
previously, physically isolating clock lines and/or running clock lines at right angles to input/output lines.
All of these techniques tend to minimize parasitic
coupling capacitance from the Clocks to the signals in
question.
In considering clock coupling it is also important to
have a detailed knowledge of the functional characteristics
of the device being used. As an example, for the MM5262,
coupling noise from the 2 clock to thellddress lines
is of no particular consequence. On the other hand the
address inputs will be sensitive to noise coupled from
1 clock.
c
w
Memory/Clock Drivers en
en
~
N
CD
NAnoNAL
053629 memory driver with decode inputs
general description
The OS3629 is a monolithic memory driver which
features two 400 rnA (source/sink) switch pairs along
with decoding capability from four address lines. Inputs
Band C function as mode selection lines (source or
sink) while lines A and 0 are used for switch-pair
selection (output pair Y/Z or W/X). The OS3629 has
the same pin-out and function as the OS75324 except
that the source emitter voltage capability has been
raised from 3V to 7V _ This allows the OS3629 to drive
larger memory systems at the same current levels of the
OS75324.
•
Identical pin-out and function as OS75324
• 400 rnA output capability
• High voltage outputs
• Dual sink/source outputs
•
Internal decoding and timing circuitry
•
Fast switching times
features
• OTLITTL compatible
• Source emitter voltage of 7V (max) at 400 rnA source
•
Input clamping diodes
schematic and connection diagrams
r-~~~----------~~--------------~~----------~Vtt
TIMING
INPUTS
OUTPUT
x
'---++-~(SOU"CEI
+-""'I.-.--;---;4--""'I'v---;--+-O COLLECTORS
SOURCE
ADDRESS
INPUT1
SWITCH·PAIR
SllEL.,. 00-...,..+--1-'
0/'------.....-0 ~~~~~Tl
Dual-In-Line Package
GNO"
OUTPUT
Z
2
(SINK)
Dual-In-Line Package
OuTPUT SOURCE OUTPUT OUTPUT
V
COLLEt
X
W
Vee
(SOURCE)
TORS
\SOURCE)
(SINKI
1
II
ADDRESS
~_~_~.
TIMING INPUTS
ADDRESS INPUTS
GNO'
TOPYIEW
OUTPUT
Z
(SINK)
OUTPUT
Vee
V
SOURCE
COLLEe-
OUTPUT
x
OUTPUT
W
(SOURCEI
TORS
(SOURCE)
{SINK]
GNU
INPUT 0
ADDRESS INPUTS
TIMING INPUlS
rOPYIEW
*GND land GND 2 art to be und in p.rallel.
Order Number DS3629J
Order Number DS3629N
4-11
absolute maximum ratings,
(Note 1)
Supply Voltage Vcc (Note 4)
Input Voltage (Note 5)
Operating Case Temperature Range
Power Dissipation
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
'""
17V
5.5V
O°C to +70°C
600mW
-6SoC to +150°C
300°C
dc electrical characteristics
(Notes 2 and 3)
PARAMETER
V'N(H
Input Voltage Required to Insure
,
(Vcc= 14V, Tc = O°C to+70°C'unless otherwise noted)
MIN,
CONDITIONS
TYP
MAX
3,5
(Figure 1)
UNITS
V
Logical "1" At Any Input
VIN(C)
Input Voltage Required to Insure
(Figure 1)
0,8
V
200
100
IlA
Logical "0" At Any Input
IIN(l)
Logical "1" Level Input Current
"NIO)
Logical "0" Level Input Current
VSAT
Saturation Voltage
Address Input
V IN =5V, (Figure 1)
Timing Input
ViN = OV, (Figure 1)
ISINK :::::.:
(Figure 2)
RL =5311
420 rnA,
RL = 39.011
'OFF
Output Reverse Current
12
Timing Input
420 mA,
'SOURCE':::::.:
-6
Address Input
IlA
rnA
rnA
Sink
0.75
0,85
V
Source
0.75
0,85
V
125
200
IlA
12.5
15
rnA
Either Sink Selected
30
25
40
35
rnA
Either Source Selected
-1.5
V
V ,N = OV, (Figure 1)
("OFF" State)
Icc
Supply Current
All Sources and
V ,N = OV, (Figure 3)
Sinks "OFF"
(Figure 4)
Input Clamp Voltage
V,
liN
= -12 rnA, T A = 25°C
ac electrical cha racteristics
(V cc
=
14V, Tc = 25°C)
PARAMETER
tpd1
CONDITIONS
, Propagation Delay Time to Logical il 1"
Level
MAX
UNITS
90
ns
110
ns
50
ns
40
ns
70
ns
(Figure 5)
RL =5311,
Propagation Delay Time to Logical "a"
Level
Sink Output
RL1 = 5311,
RL2 = 50011, Source Output
CL = 20 pF
(Figure 5)
RL - 5311,
(Figure' 6)
Sin.k Storage Time
TYP
RL1 = 5311,
(Figure 6)
t,
MIN
RL2 = 50011, Source' Output
C L = 20 pF
tpdO
rnA
Sink Output
RL = 53n, CL = 20pF, (Figure 6)
<
!,
Note 1: "Absolute Maximum Ratings" are those, values beyond which the safety of the'device cannot be guaranteed. Except for '"Operating
Temperature Range" they are not meant, to imply that the devices should be operated at these Iil1:lits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless 'otherwise specified minImax limits apply across the O°C to +70°C teroperatJre range for the D53629. All typical values are for
TA = 25°C and VCC ~ 14V.
Note 3: All currents into device pins shown as positive, out of device pins as ~e9ative, all vO.ltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
Note 4: Voltage values are with respect to network ground terminal.
Note 5: Input signals must be zero or positive with respect to network ground terminal.
4·12
c
Cf)
truth table
W
0')
N
e.g
INPUTS
ADDRESS
OUTPUTS
TIMING
SOURCES
SINK
SINK
A B C D E F G
W
X
Y
Z
0 0
ON
OFF
OFF
OFF
,
, ,
1
0
0
1 1 0 0
1 0 1 0
1
1
,
1 1 1
OFF
ON
OFF
OFF
1 1 1
1 1 1
X X X X 0 X X
X X X X X 0 X
OFF
OFF
ON
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
X X X X X X 0
OFF
OFF
OFF
OFF
test circuits and switching time waveforms
fT,MiNGiNPuTS - - - - - - - ---,
v" ¢f-------O +t4V
E
I
I
53n
+13V
TEST
v,.
~
PEA
TRUTH
AND
TEST
TABLES
(SEE NOTES)
JV
-=
Notel: Check V'N(1f and V1N(O) per truth table.
Note 2: Measure IIN!Ol per test table.
Note 3: When measuring I'N(1!< all other inputs are at ground. Each input is testtld separately.
TEST TABLE FOR IINIO)
GROUND
TEST
IINIO)
B, C, E, F, and G
Aand D
A
B, C, E, F, and G
Aand D
D
A, D, E, F,and G
Band C
B
A, D, E, F, and G
Band C
C
A, B, C, D, F, and G
E
E
A, B, C, D, E, and G
F
F
A, B, C, 0, E, and F
G
G
APPLY 3.5V
FIGURE 1. VIN(O). VIN(l). IIN(a). IIN(l) and IOFF
c:n
~
test circuits and switching time waveforms (con't)
M
CJ)
C
.,y
r;MjNGI;UTS~-,--------,¢
·f--------O +14V
Vee
J
J
+13V
.,y
SEE
TRUTH
TABLE
~
.....--I""-lJ-.....-+-'----o. 7V
Note: This parameter must be measured using pulse techniques.
500 ns, duty cycle:::;; 1%.
tp "
FIGURE 2. V(SATI
fTiM,NGiNPu-;----.------¢' ~
Vee
' - ' - - - - - - 0 +f4V
J
I
530
15W
(NON·INDUCTlVE)
' -......._D+llV
}-~+-----D7y
FIGURE 3.
4·14
Tee (All Outputs OFF)
test circuits and switching time waveforms (con',t)
+15V
¢f-------O
I~--------------,
TIMING INPUTS
I
V",
I
~
+14V
I
I
....----'Ll~
1-....- - - - - 0 0 7V
SEE
NOTES
Note 1: Ground A.nd B,apply+3.SV. to CaRd 0,
and mulure Icc (outputW is Oft).
Not. 2: Ground Band D,.pply+3.5V to A and C,
and musura Icc (outputZiionl.
Note 3: Ground A and C. apply +3.SV to Band D.
and musure Icc (autput X is on).
Note 4: Ground CInd D•• pply.+3.5V to A and B.
lind measure Icc (output V is on).
FIGURE 4. ICC (One Output ON)
.,V
1, "'1, '" 1~1lS.
~M~n--~-------'
I'
Note 1: The input waveform is IUIIPlitd by a
generator witb tbe following characteristics:
Voo9------.. .0.I4V
duty cycleS;1%..nd louT'" son.
I
Note 2: Whln mtlSUring delay timn at output X,
apply +5V to input D. and grouml A. WheR meaauring
.....y times at output V,apply +5V to input A, and
groundD.
I
I
Note 3: CL includBsprobelndjigcapacitam::l.
Note 4: Unless othHwise noted all resistors are D.SW.
'--1*-00 +13V
• ....----'Ll-".J
..v
>-+_...._ ....-<>
OUTPUT
J-+-....- ....-<>
OUTPUT V
x
SEE
NOTE
2
1------ 50'''----_
...
·'V - - - - - j - - r - - - - - - - " \.
INPUT
OV-----'I
'0%
OUTPUT-----;....../')XORV
FIGURE 5. Sour..-Ou~put Switching Times
4·15
en
('II
CD
('t)
test circuits and switching time waveforms (con't)
UJ
Q
.,v fMiNGiNPUTs---------.-A
Vee
y-------o
I
I
+14V
R,
""'w
(NON-INDUCTIVE)
1-.....- .....""""""-0 +23V
'-"''1--0 +13V
..v
.~~~~
}1~r------C7V
0/"--,--,.
}-_~-----oDUTPUT
SEE
NOTE
2
C,
~20PF
Note1: The input waveform is supplied by a generator with the following characteristics: 4 = t, = 10 os,
duty cycle::;: 1%, ZOUT "" 50n.
Note 2: When measuring delay times at output W, apply +5V to input 0, snd ground A. When measuring
delay times at output Z, applv +5V to input A. and ground D.
,Note 3: Cl includes probe and jig capacitance.
6000s---_
.,v-----i--r------,
ov _ _ _-.J·
OUTPUT - - - - - . . . . . ,
FIGURE 6. Sink-Output Switching Times
4-16
~
Memory/Clock Drivers
Advance Information*
NAll0NAL
051640/053640, 051670/053670 quad M05 TRI-5HARE™port drivers
generai description
The DS1640/DS3640 and DS1670/DS3670 are quad
MaS TR I-SHARE port drivers with outputs designed to
drive large capacitive loads up to 500 pF associated
with MaS memory systems. PNP input transistors are
employed to reduce input current, allowing the large
fan-out to these drivers needed in memory systems.
The circuit has Schottky-clamped transistor logic for
minimum propagation delay_
for address expansion. For example, two packages may
be used to implement a three-input, eight-output decoder.
Also included is a refresh control, read/write, and strobe
input. These functions are required by the MM5270
4k TRI-SHARE MaS RAM.
.
features
The DS1640/DS3640 has a 15 ohm resistor in series
with the outputs to dampen transients caused by the
fast switching output circuit. The DS1670/DS3670 has
a direct, low impedance output source for use with or
without an external resistor.
•
•
•
•
•
The DS1640/DS1670 has two address inputs which
decode to one-of-four-high outputs. Provisions are made
TRI-SHARE port driver for MM5270 RAM
TTL/DTL compatible inputs
PNP inputs minimize loading
Capacitance-driving outputs
Built-in damping resistor (DS1640/DS3640)
logic and connection diagrams
Dual-In-line Package
AOORESSA:~~::~lrr~~~~~~~b
OUTPUT
ADDRESS
A"
DISABLE
ADDRESS B
EXPANSION
Vee
114
EXPN
ADOA
13
11
OUT
A'S
11
1D
ST8
OUT
A·8
9
8
o--H_L../
o-fF====~~t~~~~~t)
OUTPUT
A-S
l-
r-..
OUTPUT
A'S
REFRESHo-~=~~~=~!i~~~~~t)
A'S
READMRITEo-------------------*-r;~
STROBE
3
4
,
ADD
ADD BOUT
EXPN
REfSH
OIS
A-S
1
OUTPUT
2
•
OUT
I'
GNO
A'S
TOP VIEW
Order Number DS1640J, DS1670J, DS3640J,
DS3670J or DS3640N, DS3670N
o----------------------o-oAI>h.....-t--o OUTPUT
Noll t: TIt, puln ",...ator has till 'ullowin. cfI.~: PAR .. , MHz, 50" Duty Cycle, louT ..
6On.~"t,S;lans.
Nom2: CL
inclu"prolleandjigCllp.~itlnllll.
Nota3: n.higllcurrenttransilnt(llhi'-'111.DAltllrolll!tth.ruisbinceoftb8extarDilintarconnectillfl
lroundls" during tnl output tnlllltionfrom the lJigh stlta to the low stam can appur IS n_VI fd~back
to the lnlllft. If the Ixtemal ilt18rconnectil1fllOld from tile ~rMag circuit to ground il electrically lana. or
... tigniflclfttdcruistalM:8.itcensubtnctfromthelWifl:hinlrespOJlle.
FIGURE 1
switching time waveforms
l10de voltage waveforms
40001_
.::~...
OV
'.
,
vo_
_
INPUT
\c_';
~t~,
v+---t-~----------+"
OUTPUT
v-===j:!
OUTPUT
+2V
Vo, _ _ _ _ _
-..!'-_ _ _ _ _ _.1
BOOmRAPPIN
--~
Neta 1: 1M ",I.. ..,.fI1or has til, following characteristics:
PRR-, MHz.tR S fO .... "S 10 .... Z0UT =500.
Nell 2: CL indullalptobeandjigcapacitance.
Nob 1: TheliN lim......n IXPOMntlal deay ..tII th.fOIlowing1ilnlCOllStllItt: la" Co. R.
lh_ ren.. of VlIues for Aa (ruistor tmanDeI, and t.ml'8fltU" codficilllt im:IlIIItdI C8II be
foumljnlhalllll!ofelal:IriCildalncteristia.
typical applications
053672 Operating with Extra Supply·
to Enhance Output Voltage Level
vt
IN
053672 in Non-Bootstrap Application
with Single Supply-When Qutput
High Level is Nori.critical_
053672 Bootstrap Mode of Application
, witt; Capecitively Coupled I nput end
... Negetive Supply.
v;
><>-""''''''-<1,"""00 OUTPUT
IN
>:>-"111,.........,...-0
OUTPUT
100.--1
'..
Y-CDR1IND)
4-22
~
Memory/Clock Drivers
Advance Information*
NA110NAL
OS3643, OS3673 decoded quad MOS clock drivers
general description
The DS3643 and DS3673 are quad bipolar-to-MOS
decoder/clock drivers with TTL/DTL compatible inputs_
They are designed to provide high output current and
voltage capabilities necessary for optimum driving of
high capacitance N-channel MOS memory systems_
The device features full decoding of input address lines
from two inputs to one of four outputs_ Also featured is
the capability of expanding to three inputs to one of
eight outputs with the use of the Expansion and
Expansion inputs_ Also included are clock and refresh
inputs_
The circuit was designed for driving large capacitive
loads at high speeds and uses Schottky-clamped transistors_ PNP transistors are used on all inputs, thereby
minimizing input loading_
The DS3643 has a 10 ohm damping resistor in series
with each output to dampen transients caused by the
fast switching output, while the DS3673 has a direct,
low impedance output, for use with or without an
external resistor_
features
• TTL/DTL compatible inputs
• Operates from standard bipolar and MOS supplies
• PNP inputs minimize input loading
• Full logic decoding for either two inputs to one of
four outputs or three inputs to one of eight outputs
• High voltage/current outputs
• Input and output clamping diodes
• Control logic optimized for use with MOS memory
systems
• Built-in damping resistors (DS3643)
logic and connection diagrams
AI
Dual-In-Line Package
Vee1
14
OUT 4
eLK
13
RFSH
EXPN
11
10
12
,
r-
I
,
rr-
'--
Vee2
VCC~
OUT 3
,
4
3
OUTl
A'
AI
5
-EXPN
6
OUT 2
7
GND
TOP VIEW
Order Number DS3643J
or DS3643N
Order Number DS3673J
or DS3673N
truth table
INPUTS
OUTPUTS
CLOCK
REFRESH
EXPANSION
EXPANSION
A2
A,
1
X
X
X
X
X
0
0
0
0
1
X
X
X
X
0
0
0
1
1
1
1
0
0
0
1
1
0
1
o!
0
0
0
0
1
0
0
0
0
x = Don't ,Care State.
0
0
0
1
0
1
0
OUT,
OUT 2
OUT 3
OUT4
,
0
1
0
0
1
0
0
,
0
1
0
0
0
1
0
X
0
1
X
X
X
0
0
0
0
0
0
X
X
0
0
0
0
0
0
1
0
0
0
1
0
0
0
·Specifications may change.
4-23
operating conditions
.. abs9Iu~e maximum ratin9s '(Note 1)
Supply Voltage
vcel
VCC2
VCC3
Input Voltage
Output Voltage
Siorage Temperature Range
Lead Temperature (Soldering, 10 seconds)
Po~er Dissipation (PO)
C~ram ic Package,
Mo Ided Package
7V
13V
16V
-1.0V to 7V
, -1.0V to 16V
-£5°C to +150"C
300"C
MIN'
MAX
UNITS
Supply voltage
VCCI
VCC2'
VCC3
4.75
11.4
5.25
12.6
V
V
V
Temperature, T A
0
. ..
°c
+70
'VCC2 + (3V - 5%),"VCC2 + (3V + 5%)
1160mW
1000 mW
• Derate ceramic package at QO°CIW above 70"e; derate molded
package at 90°CIW above 70°C.
electrical characteristics
TA = o°c to +70°C, VeC1 = 5.0V ±5%, V CC2 = 12V ±5%, VCC3 = V CC2 + (3V ±5%) unless otherwiseno.ted. (Notes 2 and 3)
.'
PARAMETER
,V 1H
Logical "I" Input V61tage
V,L
Logical·'·O" Input Voltage
I'H
Logical "1"
Inp~t
CONDITIONS
TVP
MAX
UNITS
V
2
O.B
V
10
40
IlA
IlA
-250
-1.0
IlA
rnA
-1.5
V
Current
Refresh. Exp .• Exp,
AI. A2, Clock
Y'N = 5.5V
I'L
MIN
Logical "0" Input C~rrE!nt
Y'N
Refresh, Exp.
AI. A2, Clock, Exp.
=0.4V
-40
1.6
Vco
Input Clamp Voltage
I, =:-'2mA
VOH
Logical "I" Output Voltage
10H = -1 rnA, VIL = O.BV
Vee2-o·2
V
VOL
Logical "0" Output Voltage
10L·= 5 rnA, V,H = 2,OV
0,3
V
Voe
Output Clamp Voltage
loe = 5 rnA. V'L = O,BV
Icc
Supply Current Outputs High
Icc1
Refresh = 5V.
All Other Inputs = OV
ICC2
ICC3
leLO
All Inputs = 5V
ICC2
lee3
switching characteristics
V CC1
PARAMETER
tpd~
tpdO
V
rnA
inA
Vee, = 5.25V
Vee. ':' 12.6V
Vee3 = 15,75V
20
2
2
'1'A
. Vee, = 5.25V
Vee2 = 12.6V
Vee3 = 15.75V
30
0.1
15
rnA
rnA
rnA
Supply Currents Outputs Low
ICCl
..
.V ee2 +1.5
Propagation Delay to if LoQical
"O"·from Ai, A2 • Clock. Exp.
to Out 1
Propa~ation Delay to a Logical
"0" from Refresh, Exp. to
= 5V, V CC2 = 12V, VCC3 = 15V(Note 4)
CONDITIONS
MIN
TYP
MAX
UNITS
Ro = Ion
CL =400pF
CL = 100 pF
20
12
ns
ns
CL = 400pF
CL = 100 pF
25
Ro = Ion
17
ns
ns
Ro = Ion
CL = 400 pF
CL = 100pF
20
12
ns
ns
CL = 4QOpF
.C L = 1.00. pF
25
Ro = Ion.
ns
ns
Out 1
t,."
Propagation Delay to a Logical
"I" from A,. A., Clock, Exp:
toOut 1
tpd1
~ropagati~n
Delay to a Logic'al
, "I" from Refresh, EXp. to
Out 1
1.7
Note 1: "Absolute Maximum Ratings" are those values beyond :Which the safety of the device can'not be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditio'ns for act~al device operation.
'
Note 2: Unless oth';rwi~;' specified min/max limits apply across the O°C to +70°C range for the 053673. All typieals are given for VCC1 = 5.0V,
VCC2 = 12V, VCC3= 15V, and TJ>. = 25°C:
Note 3: AI" currents into device pins stlown as positive, Qut of device pins as negative, 'all voltages referenced to ground unless ~therwise noted.
All values 'Shown as max or ,min'bn,.absolut~ value'basis.
Note 4: For &c. measurements, a 10 oHm resistor must be placed in series with the output of t~e 053673. This resistor is internal to the 053643,
ho'!V~ve~, and need. not be.. added.
4-24
schematic diagram
EOUIVALENT INPUT
I
I
I
I
INPUT
....---..- ......,.,,"".-0
10
INTERNAL
lOGIC
CIRCUITRY
OUTPUT
(OS3643 ONLY)
I
I
I
L ___ _
L - _....- - - - - - - - - -. .-----~-------~....--__oGNO
ac test circuit and switching time waveforms
INP::V-l.5~_tr----,\:_.5V
+5V
:j t~o
+12V +15V
VOH--------~
INPUT
_
~t~,
10
UN 0 ER OS3673
TEST
C,
IINOTE4)
OUTPUT
+2V
VOL--------~-----'-----------------~
Note 1: The pulse generator has the following characteristics:
PRR '" 1 MHz, tR '510 ns,l{::::; 10 ns, ZOUT = SOn.
Note 2: CL includes probe and jig capacitance.
typical application
OS3673
ADDRESS 1
A, .
OUT 1 f- CE 1
ADDRESS 2
A,
OUT2 f- CE 2
EXPANSION
OUT3 f- CE 3
EXPANSION
OUT4
ADDRESS 3
LOGIC "1"
-- r
-- -'
f-
I-
OS3673
LOGIC "0"
-A,
OUT 1
-A,
OUT2
EXPANSION
OUT3
EXPANSION
OUT4
---
CE4
MM5270 DR
MM52BO
MOS RAM
ARRAY
CE 5
CE 6
CE 7
CEB
4-25
~
Memory/Clock Drivers
Advance Information*
NAnONAL
OS3644, OS3674 quad MOS clock drivers
general 'description
The OS3644 and OS3674 are quad bipolar-ta-MOS
clock drivers with TTL/OTL compatible inputs. They
are designed to provide high output current and voltage
capabilities necessary for optimum driving of high
capacitance N-channel MOS memory systems.
low impedance output for use with or without an
external damping resistor..
features
•
•
•
•
•
•
The device features two common enable inputs; a
refresh input, and a clock control input for simplified
system designs. The circuit was designed for driving
highly capacitive loads at high speeds and uses SChottkyclamped transistors. PNP transistors are used on all
inputs thereby minimizing input loading.
TTL/OTL compatible inputs
Operates from standard bipolar and MOS supplies
PNP inputs minimize loading
High voltage/current outputs
Input and output clamping diodes
Control logic optimized for use with MOS memory
systems
• Pin and function compatible with MC3460 and
3235
• Built-in damping resistors (OS3644)
The OS3644 contains a 10 ohm resistor in series with
each output to dampen the transients caused by the
fast-switching output, while the OS3674 has a direct,
schematic and connection diagrams
EQUIVALENT INPUT
EQUIVALENT OUTPUT
I
INPUT
I
I
I
I
1---+....-'11""'-0
INTERNAL
PUTfUl
10
(OS3644 ONLY)
lOGIC
CIRCUITRY
I
IL ____ _
1-~_-~---_---4------4-------4-----oGND
VCC1
16
OUT 0
15
SEL U
14
EN t
13
EN 2
12
1
2
3
4
5
VCC2
OUT A
SEl A
elK
RFSH
IN
IN
BEL C
11
OUT C
10
6
7
SEL BOUT 8
VCC3
9
8
GNU
TOP VIEW
Order Number OS3644J,
OS3674J, DS3644N or
OS3674N
4-26
·Speciflcatlons may change.
absolute maximum ratings
Supply Voltage
VCCI
VCC2
VCC3
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
Power Oissipetion (PO)
ceramic Package
Molded Package
c
w
en
operating conditions
(Note 1)
MIN
7V
13V
16V
-1.0V to +7V
-1.0V to +16V
~5·C to +150·C -'.
300·C
Supply Voltage
4.75
VCCI
11.4
VCC2
VCC2
+
(3V-5%)
VCC3
Temperature, TA
0
1160mW
1000mW
MAX
UNITS
5.25
12.6
VCC2 + (3V + 5%)
+70
V
V
V
·C
• Oerete ceramic package at BO·C/Wabov8 70"C; derete molded
package at 90"CIW above 70"C.
electrical characteristics
TA = O°c to +70°C, VCC , = 5.0V ±5%, VCC2 = 12V ±5%, VCC3 = VCC2 + (3V ±5%) unless otherwise noted. (Notes 2,3 and 4)
PARAMETER
V'H
Logical "I" Input Voltage
V'L
Logical "0" Input Voltage
I'H
Logical "1" Input Current
CONDITIONS
TVP
MAX
UNITS
V
2
Select Inputs
All Other Inputs
V'N = 5.0V
I'L
MIN
0.8
V
10
40
p.A
p.A
-250
-1.0
p.A
mA
-1.5
V
Logical "0" Input Current
VIN = 0.4V Select Inputs
All Other Inputs
-40
Vco
Input Clamp Voltage
I, =-12mA
VOH
Logical "1" Output Voltage
10H = -1 mA, V'L = 0.8V
VOL
Logical "0" Output Voltage
10L = 5 mA, V'H = 2.0V
0.5
V
Voc
Output Clamp Voltage
loc = 5 mA, V'L = 0.8V
Vcc2+1.5
V
ICCH
Suppiy Current Outputs High
27
4
mA
mA
mA
40
3
25
mA
mA
mA
Icc.
Icc2
ICC3
ICCL
V
Vcc2-D·5
All Inputs V'N = OV
Outputs Open
VCC' = 5.25V
VCC2 = 1Z;6V
VCC3 - 15.75V
18
2
2
All Inputs V'N = 5V
Outputs Open
VCC' = 5.25V
VCC2 = 12.6V
VCC3 = 15.75V
26.8
--4
Supply Currents Outputs Low
Icc.
IC02
ICC3
switching characteristics
Vcc , = 5V, VCC2 = 12V, VCC3 = 15V, TA = 25°C unless otherwise noted
PARAMETER
t"dO
Propagation Delay to a
Logical "0"
t"..
Propagation Delay to a
Logical"1"
15
CONDITIONS
MIN
TVP
MAX
UNITS
Ro = 10n
CL = 400 pF
C L = 100pF
20
12
ns
n.
Ro = 10n
C L = 400pF
C L =100pF
20
12
n.
ns
Nota 1: "Absolute Maximum Ratings" are those )lalues beyond which the' safety of the device cannot be guarantead. Except for "Operating
Temperature Range" they are not maent to imply that the devices should be operatad at theSe limits. The table of "Electricel Characteristics"
provides conditions for actuel device operation.
Nota 2: All typicals are given for VCC1 = 5V, VCC2 = 12V, VCC3 = 15V and TA "25·C.
Not. 3: All currents into device pins shown as positive, out of device pins es negative, all'voltegas referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
Nota 4: For ac measurements, a 10 ohm resistor must be placad in series with the output of the 053674. This resistor is internal to the 053644,
however, and need not be addad.
4·27
E
rt
u>
(I')
ac test circuit
~
+5V
+12V +15V
(INTERNAL ON
10
DS3644)
I
c,
(NOTE 41
REFRESH INPUT" 2.4V
ALL OTHER INPUTS = OV
switching time wavefonns
INPUT
t
_ _ _ _"-_ _--,
. £~
+3V---~-,,....
VOH - - - - -....
OUTPUT
VO,-------~
+2V
___
,~
______
~
Note 1! The pulse generator has the following ~halacteristi&s;
PRR =1 MHz, tR ~ 10 nS,t, S 10 ns, ZOUT.;'" son.
Note 2: CL includes probe and jig capacitance.
truth table
INPUT
4·28
ENABLE
ENABLE
1
REFRESH
INPUT
OUTPUT
2
SELECT
INPUT
CLOCK
INPUT
1
···X.
X
X
X
X
1
X
X
X
0
X
X
X
1
X
1.
X
1
'0
0
0
X
X
0
0
0
()
X
0
0
X"
0
1.
0
1
~
~
Memory/Clock Drivers
Advance Information*
...eno
C/)
~
U1
.......
oC/)
NAnONAL
w
~
OS1645/0S3645. OS1675/0S3675 hex TRI-STATE® MOS latch/drivers
U1
general description
The OS1645/0S3645 and OS1675/0S3675 are hex
MOS latch/drivers with outputs designed to drive large
capacitive loads up to 500 pF associated with MOS
memory systems. PNP input transistors are used to
reduce input currents, allowing the large fan-out to
these drivers needed in memory systems. The circuit
has Schottky-clamped transistor logic for minimum
propagation delay, and TRI-STATE® outputs which
allow bus operation.
The circuit employs a fall-through-Iatch which captures
the data in parallel with the output, thereby eliminating
the delay normally encountered in other latch circuits.
The OS1645/0S3645 and OS1675/0S3675 may be
'used for input address lines or input/output data lines
of a MOS memory system.
features
•
•
•
•
•
The OS1645/0S3645 has a 15 ohm resistor in series
with the outputs to dampen transients caused by the
fast switching output circuit. The OS1675/0S3675
has a direct, low impedance output for use with or
without an external resistor.
TTUOTL compatible inputs
PNP inputs minimize· loading
Capacitance-driving outputs
TRI-STATE outputs
Built-in damping resistor (OS1645/0S3645)
logic and connection diagrams
OAT . .
o--lr,......___-_-_ _-__--r-,- --,
I
I
I
I
I
I
IL ___ '-- __ _
o-C
o-C==
DATAD
o-C
DATAE
o-C
DATAF
~~!:~~
o-C
Vee
I"
===
=
==
=
=
==
==
======= ===
=
==
==
= =====::1-0°,
=-: =::1-0
==
====
==
OATAC
DATA B
Dual~ln.Line Package
OUT
DSBL
15
DATA F
GF
DATA E
12
13
14
tiE
OATA 0
11
10
00
,
r-
=::J--oGo
1
IN
a,
ENBl
,
DATA A
3
QA
5
4
DATA B
iia
•
DATA C
7
Ilc
I'
GNO
TOP VIEW
Order Number DS1645J, DS1675J
DS3645J, DS3675J, DS3645N
or DS3675N
0------1>0-------------'
truth table
INPUT
ENABLE
OUTPUT
DISABLE
1
a
a
a
a
X
1
X
1
x
DATA
OUTPUT
OPERATION
1
a
Data Feed-Through
a
x
1
Data Feed-Through
Q
Latched to Data Present
when Enable Went Low
Hi-z
High Impedance Output
= Don't care.
·Specifications may change.
4-29
"
absolute maximum ratings
operating conditions
(Note 1)
MIN
Supply
Logical
Logical
Logical
Voltage, Vee
"1" Input Voltage, V,N(lI
"0" Input Voltage, VIN(Q)
"1" Output Current, '05( 1)'
Logical "0" Output Current, 'OS(O)
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
Power Dissipation (PO)
Ceramic Package
Molded Package
Temperature (T A)
OS1645,051675
OS3645, OS3675
-lA
lA
-55'e to 150'e
300'e
MAX
UNITS
,5.5
V
-55
0
+125
'e
TYP
MAX
UNITS
0.8
V
4.5
Supply Voltage (Vee)
7V
7V
-1.5V
;'
ho
'c
1160mW
1000mW
* Derate ceramic package at 80°C/W above 70o e; derate molded
package at 90'e/W above 70'e.
electrical characteristics
(Notes 2 and 3)
PARAMETER
V ,NI ,)
Logical "1" Input I/oltage
V 'NIO)
Logical "0" Input Voltage
liN (1)'
Logical "1" I nput Current
I'NIO)
Logical "0" I nput Current
lIeLAMP
Input Clamp Voltage
VOHINL)
Logical "1" Output Voltage
CONDITIONS
MIN
2.0
Y'N = 5.5V
Enable Inputs
Vee = 5.5V
Data Inputs
Y'N = 0.5V
Enable Inputs
Vee = 5.5V
Data Inputs
V
0.1
40
I1A
80
I1A
-90
-250
I1A
-180
-500
I1A
-1.2
V
Vee = 4.5V, liN = -18 rnA
Vec= 4.5V, 10H =
a mA
3.4
4.25
V
(No Load)
VOLINL)
Logical "0" Output Voltage
0.25
Vee = 4.5V, 10L = 0 mA
0.45
V
(No Load)
VOHIWL)
Logical "1" Output Voltage
(With Load)
VOLIWL)
Logical "0" Output Voltage
(With Load)
Vee = 4.5V, 10H = -1.0 mA
Vee = 4.5V, IOL=20mA
DS1645/DS3645
2.4
3.5
V
DS1675/DS3675
2.5
3.5
V
DS 164;;/DS3645
0.6
1.1
V
DS1675IDS3675
0.3
0.5
V
liD
Logical" 1" Drive Current
Vee = 4.5V, V OUT = OV (Note 4)
170
10D
Logical "0" Drive Current
Vee = 4.5V, V OUT = 4.5V (Note 4)
170
mA
leeiMAX)
Maximum Power Supply
Vee = 5.5V
60
mA
Vee = 5':5V
40
mA
mA
Current
leelMIN)
Minimum Power Supply
Current
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant ,to imply tha~ the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified niin/max limits apply' across the -55°C to +125°C'temperature .range for the OS1645 and OS1675 and
across the O'C to +70'e range for the OS3645 and 053675. All typical values are for T A = 25'e and Vee = 5V.
Note 3: All currents into device pins shown as positiv6', out of device pins as negative, all voltages referenced to ground unless otherwise noted.
All values shown as max or min on absolute value basis.
Note 4: When measuring outP~t drive curr~rit and 'switching response for the 051675 and OS3675 a 15 ohm resistor should be placed in series
with each output. This resistor is internal to the OS1645/053645, and need not be added.
4-30
switch in g ch aracteristics
(Note 4) Vee
= 5V, T A = 25°C unless otherwise noted.
PARAMETER
tpdlOI
tpdlll
tSET -UP
CONDITIONS
MIN
TYP
MAX
UNITS
Propagation Delay to Logical
CL = 50 pF
7
ns
"0," Data Input to Output
CL = 250 pF
15
ns
CL = 500 pF
25
ns
Propagation Delay to Logical
CL = 50 pF
7
ns
"1," Data Input to Output
C L = 25.0 pF
15
ns
CL =500 pF
25
ns
0
ns
10
ns
Set·up Time on Data Input
before I nput Enable goes
Low
t HOLD
Hold Time on Data Input
after I nput Enable goes
Low
tHO
Delay from Disable Input to
CL = 50 pF,
RL
= 2 Ul to Vee
15
ns
CL = 50 pF,
RL
= 2 kD. to Ground
15
ns
CL =50pF,
RL
= 400n to Vee
15
ns
CL = 50 pF,
RL
= 400n to Ground
15
ns
Logical "0" Level (from High
Impedance Statel
tHl
Delay from Disable Input to
Logical" 1" Level (from High
Impedance State)
tOH
Delay from Disable Input to
High Impedance State (from
Logical "0" Level)
t'H
Delay from Disable Input to
High Impedance State (from
Logical "1" Level)
schematic diagram
EQUIVAlEN,T INPUT
EQUIVALENT OUTPUT
r------- ---,
I
.
I
I
15 (OS1645/0S3645 ONLY)
L-.--~~W'lr--o OUTPUT
INPUT
INTERNAL
lOGIC
CIRCUITRY
L ___ _
L-~~--------~~-----~-~~--_t---OGNO
OS3645/0S3675
4·31
tn
r--.
CD
M
ac test circuits and switching time waveforms (con't)
r./)
,Ctn
tpdO and tpd1
r;
Vee
15n
tn
~
V,"
15n
(NOTE 4)
15n
(NOTE 4)
(NOTE 4)
083675
VOUT
083675
V,"
O.1iJF
1:
1:
~
C
Vee
Vee· 1l.11JF
O.1J.!F
lii
t1H
tH1
VOUT
V,"
083615
VOUT
CD
M
ICC
r./)
,ctn
':"
~
""J
':"
2k
':"
':"
5·"1
ODD
':"
CD
.r./)
tOH
tHO
C
Vee
Vee
~"'1
~
-~
OUTPUT
O£V
2.2V
O.l/-1F
2k
15n
(NOTE 4)
~
.
V,"
J""
':"
40.
15n
(NOTE 4)
VOUT
083675
V,.
O.1IJ F
083675
':"
1VOUT
J""
DISABlE*
"'nputSign.1 Characteristics;
INPUT
Freq = t MHz
Duty cycle'" 50%
Amplitude'" O.4V to J.IlV
t, =tf = 2.5 os
OUTPUT
--=LitHO
-~
typical applications
The DS3645 and DS3675 latch/driver has T R I-STATE
outputs, which allows the outputs to be tied with those
of another TRI-STATE driver, such as the DS364tl and
DS3676 refresh counter. The DS3645 and DS3675 can
be disabled wh ile the alternate driver controls the address
lines into the memory system.
j'
MOS MEMORY
DATAl
1-1-1-1-....._ _
I-f-+-+-...............I-f-+-+--I-HI-
INPUTS
REFRESH
CONTROL
OUTPUT
[USABLE
OS3646/
083676
OUTPUT
REFRESH
t----'
ENABLE COUNTERt-_ _ _-'
4-32
SYSTEM
~
Memory/Clock Drivers
Advance Information*
NAnONAL
OS1646/0S3646, OS1676/0S3676 6-bit TRI-STATE®
MOS refreshcounter/driver
general description
The OS1646/0S3646 and OS1676/0S3676 are 6-bit
refresh counters with outputs designed to drive large
capacitive loads up to 500 pF associated with MOS
memory systems_ PNP input transistors are employed
to reduce input currents_ The circuit has Schottkyclamped transistor logic for minimum propagation delay,
and TRI-STATE® outputs allow it to be used on
common data buses_
The OS1646/0S3646 has a 15 ohm resistor in series
with the outputs to dampen transients caused by the
fast switching output circuit_ The OS1676/0S3676 has
a direct, low impedance output, for use with or without
an external resistor_
The counter uses as its input the RAM clock signal, and
with each clock input, it advances the count by one,
thus generating a new refresh address_
Extra pins in the package are used for a two input
NANO gate and a two input NOR gate; both of which
have capacitive drive outputs_
features
•
•
•
•
•
•
•
Circuit counts when clock goes high
TTL/OTL compatible inputs
PNP inputs minimize loading
Capacitance-driver outputs
TRI-STATE outputs
Extra gates on unused pins
Built-in damping resistor (OS1646/0S3646)
logic diagram
OUTPUT
ABC
0
ENABLE
connection diagram
Dual~1 n·Line
OUT
ENBl
Vee
1"
15
OUT 6
14
OUT 5
typical application
Package
OUT 4
12
"
11
10
9
The OS1646/0S3646 and OS1676/0S3676 have TRISTATE outputs which can be tied to the outputs of
another TRI-STATE driver_ The refresh counter can
control the address lines into a memory array during
a short refresh cycle, and then return to the highimpedance state .to allow the primary driver to .control
the address lines_
ADDRESsl
INPUTS
REFRE'SH
1
2
eLK
OUT1
J
OU12
5
4
OUT3
A
6
7
-A.B
CONTROL
18
OUTPUT
DISABLE
GNO
TOP,VIEW
Order Number DS1646J, DS1676J, DS3646J
DS3676J or DS3646N, DS3676N
OUTPUT
ENABLE
CLOCK
"Specifications may change.
4-33
\
absolute
~aximum
ratiogs
Supply Voltage, VCC
Logical "1" Input Voltage, VIN(1)
Logical "0" Input Voltage, VIN(O)
Logical "I" Output Current, 10S(1)
Logical "0" Output Current, 105(0)
Storage Temperature Range
.7V
7V
-1.5V
lA
lA
-65·C to 150·C
300·C
Lead Temperature (Soldering, 10 seconds)
Power Dissipation (PO)
Ceramic Package
Molded Package
dc
electric~1
operating conditions
(Note 1)
Temperature (TA)
051646,051676
OS3646,OS3676
Logical "I" Input Voltage
VINIOI
Logical "0" Input Voltage
IIN(lI
Logical "I" Input Current
CONDITIONS
Vee = 5.5V,
Enable Input
VIN = 5.5V
Clock Input
Vee = 5.5V
VIN = 0.5V
Logical "0" Input Current
VeLAMP
Input Clamp Voltage
Vee = 4.5V
lIN =-lBmA
VOH(NLI
Logical "I" Output Voltage (No Load)
Vee = 4.5V
10H = OmA
VOL(NLI
Logical
Vee = 4.5V
10L =OmA
VOH(WLI
Logical "I" Output Voltage (With
"a" Output Voltage
MIN
(No Load)
UNITS
V
·C
·C
3.4
p.A
80
p.A
-250
p.A
-1.2
V
V
0.45
V
V
DS1676/DS3676
2.5
3.5
V
V OUT = OV, (Note 4)
10D
Logical "0" Drive Current
Vee = 4.5V
V OUT = 4.5V
lee (MAXi
Maximum Power Supply Current
lee(MINI
Minimum Power Supply Current
DS1646/DS3646
0.6
1.1
DS1676/DS3676
0.3
0.5
V
V
-170
mA
170
mA
Vee.= 5.5V
60
mA
Vee = 5.5V
40
mA
(Vee = 5V, TA
=25°C)
PARAMETER
(Note 4)
CONDITIONS
CL = 50pF
Settling Time Delay from Clock
40
3.5
Vee = 4.5V
Propagation Delay to Logical "I"
V
2.4
Logical "I" Drive Current
Propagation Delay to Logical "0"
O.B
OS1646/0S3646
10L =20mA
ac electrical characteristics
UNITS
4.25
0.25
Vee = 4.5V
Load)
MAX
V
-90
10H =-1.0mA
Logical "0" Output Voltage (With
TYP
0.1
Vee = 4.5V
Load)
t pd (1)
+125
+70
2.0
.'
IIN(OI
tpd(OI
MAX
5,5
characteristics (Notes 2 and 3)
V IN (11
lID
-55
0
\
* Derate ceramic package at 80·C/W ~bove 70·C; derate molded
package at 90· C/W above 70·C,
1160mW
1000 mW
PARAMETER
VOLCWLI
MIN
4,5
Supply Voltage (VCC)
..
C L = 250 pF
MIN
TYP
MAX
UNITS
7
ns
15
ns
C L = 500 pF
25
ns
CL = 50 pF
CL - 250 pF
7
ns
15
ns
CL =,500 pF
25
ns
65
ns
CL
= 50 pF
Input to Output 06
tHO
Delay from Enable Input to Logical
CL =50 pF
RL = 2 k.l1 to Vee
10
ns
CL =.50 pF
RL
= 2 k.l1 to Gnd
10
ns
RL = 390.11 to Vee
10
ns
RL ~ 390.11 to Gnd
10
ns
"0" Level (from High Impedance State)
tH1
Delay from Enable I nput to Logical
"I" Level (from High Impedance State)
tOH
Delay from Enable Input to High Imped· CL = 50 pF
ance Staie (from Logical "0" Level)
t'H
Delay from Enable Input to High Imped· C L = 50 pF
ance State (from Logical "'" Level)
Note 1: "Absolute Maximum Ratings" are those values beyond which the saf~ty of the device cannot be guaranteed. Except for "O~rating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual ,device operation.
Note 2: Unless otherwise specified min/max limits apply across the -55·e to +125·C temperature range for the 051646 and 051676 and
across the O·C to +70·C range for the OS3646 and 053676. All typical values are for TA = 25·C and Vec = 5V.
Note 3: All currents into device pins shown as 'positive, out of device pins as negative, all voltages referenced to g·roUlid unless otherwise noted.
All values shown as max 01' min 'on absolute· value basis.
Note 4: When measuring output drive current and switching response for the D51676 and OS3676 a '5 ohm resistor should be placed in series
with each output. This resistor is internal to the 051646/053646, and need not be added.
4·34
C
en
ac test. circuits and switching time waveforms
Vee
O.lj.1F
t5n
C
en
w
en
~
en
(NOTE 4)
VOUT
I
.".
en
.......
O.lJ.1F
1.
1512
(NOTE 4)
OS3676
V'N
Vee
D.1iJ F
~
~
~
t1H
tH1
tpdO & tpd1
v"
~
en
V"
083676
Your
V'N
DS3676
VOUT
C
2k
5O"J
C
'
5O"J
.".
.".
.".
en
~
'"
en
en
"
.......
.".
C
en
tOH
tHO
Vee
W
en
O.lJ.1F
~
15n
(NOTE 4)
V'N
083616
VOUT
I
----f
--j
1:
~_1._5V_ __
1.5V
--i ~t~o ~2V r-t~,
OUTPUT~
V'N
DS3676
.".
VOUT
J
SD
.'
5D
.,
.".
ENABLE'"
INPUT
ENABLE"
INPUT
OUTPUT
OUTPUT
~rtHo
*Input Signal Characteristics:
Freq'" 1 MHz
Duty cycle = 50%
Amplitude'" O.4V to 3.0V
t. =tf =2.5 os
~
39'
15n
(NOTE 4)
.".
GATE'
INPUT
"en
Vee
O.1J.lF
-j
r-~H
~
schematic diagram
EQUIVAlEN;.:T:,:IN::;'.:U;.T_ _ _ _ _ _ _ _. -_ _ _ _ _ _ _ _
'"_U_'V,A_L,...EN_T_O_UT_'_UT""_ _ _
OVee
1------,
I
I
I
15 (DS1646/DS~46 ONLY)
L - - - -...."'VVV-o OUTPUT
INPUT
INTERNAL
LOGIC
CIRCUITRY
I
L _____ _
L-~~--------~~-------~~---~~--2 to Gnd
= 390>2 to Vee
Delay from Disable Input to Logical "1"
C L = 50 pF
Level (from High Impedance State)
R L = 2 k>2 to Gnd
Level (from High Impedance State)
C L = 50 pF
R L =2k>2toV ee
Setup Time of Data Input Before
LATCH Goes Low
tHOLD
Hold Time of Data Input After
LATCH Goes Low
schematic diagram
E~UIVALENT
EQUIVALENT INPUT
r
I
I
I
INPUT~r<
1~
L
Vee
In
I
I
INTERNAL
lOGIC
CIRCUITRY
-
-
-1- -
I
I
I
-~
Note: Data pins Al-A4 and Bl-84 consi$t of an input and an output tied tollether.
4-38
OUTPUT
-~
...... I
I
I
I
I
I
I
I
UNITS
ns
C L = 50 pF
. Delay from Disable I nput to Logical "0"
MAX
7
Delay from Disable Input to High
"0" Level)
TYP
CL =50pF
Impedance State (from Logical "1" Level)
Impedance State (from Logical
MIN
OUTPut
V
j'A
GNO
logic table
INPUT ENABLES
A
B
---
LATCH
OUTPUT DISABLES
B
A
EXPANSION
A1-4
B1-4
1
0
1
0
0
0
Hi-Z
0
1
1
0
0
0
B
Hi-Z
1
0
0
0
0
0
Hi-Z
Q
-
COMMENTS
-
O~ta
A
In on At Output to B
Data In on B, Output to A
-
Data Stored Which is Present When
LATCH Goes Low
0
1
0
0
0
0
Q
Hi-Z
Same as Above
1
0
X
0
1
0
Hi-Z
Hi-Z
Both A and B In Hi-Z State; Data
I nput on A, May Be Latched
0
1
X
1
0
0
Hi-Z
Hi-Z
Both A and B In Hi-Z State; Data
X
X
X
X
X
1
Hi-Z
Hi-Z
Both A and B In Hi-Z State
Input on 8, May Be Latched
x
=
Don't Care
Note: Data may be latched into the register independent of the output disables or expansion.
ac test circuits and switching time waveforms
tpdO & tpd1
V'N
t-........-........-OV OUT
V'N
\-........-_.....OV OUT
V'N
;;t' 390
'O'~ '::"
2k
tOH
INPUT'
IBORA)
OUTPUT
--f
--l
-1 ~
1:
~_I'_'V_ __
1.'V
'¢'
~2V ~'¢'
V'N
IAORB)~
*lnputSignaICharacteristics:
Freq=l MHz
Dutvcycle=51l%
Amplitude=O.4Vto3.0V
t,=t,=2.5ns
I'O'F
DISA8LEOR~
EXPANSION
LSV
INPUT*
,
DISABLE OR
EXPANSION
INPUT*
tHl
OUTPUT
(A OR B)
---=1i'"'
~
4-39
1/1
Q)
';:
Q)
operating waveforms
en
.....
::::-:-:x:: ---- 'X
'I:.t
<0
M
DATA _ _
INPUT
C
lATCH----------~\
INPUT
.
_
..
\. _ _ _ _ _ _ _ _ _ _ _ _
x.:
en
~
~
DI~~:~~
en
c
~
.
1..._ _ _ _ __
___________JI
OUTPUT-"'"
\1..____
-y,- _ _____ :>---- ____ {"- --DATA
-FEED·THROUGH
-+--
DATA
.-J
-I
DATA
I--lATCHEO--
LATCHEO-
-----~~~r~~----
I
OUTPUT _ _ _
OUTPUT
HI-Z ~- ACTIVE--
typical application
The diagram below shows how the DS1677 can be used as a register capable of multiplexing data lines .
Al
4
.,--
A2 081677 82
AJ
83
DATA LINES
(MULTIPLEXED)
A4
84
EXPANSION
~
fI-
-
10F4
OECODER
DM75155
dJ
11
~
f-
-~
'-~
-
lllI-
IIff-
f-
rf-
ITO DS1677 INPUT ENABLES
~
DATA
TD/FROM-------<
ARRAY
TO 081677 LATCH INPUTS
co~~~g~----------------~t
4-40
16
DATA LINES
TO MOS
MEMORY
ARRAY
~
Memory/Clock Drivers
Advance Information*
NAnONAL
OS1648/0S3648, OS1678/0S3678 TRI-STATE® MOS multiplexer/drivers
general description
The OS1648/0S3648 and OS1678/0S3678 are quad
2-input multiplexers with TR I-STATE outputs designed
to drive the large capacitive loads (up to 500 pF)
associated with MOS memory systems_ A PNP input
structure is employed to minimize input currents so that
driver loading in large memory systems is reduced_ The
circuit employs Schottky-clamped transistors for high
speed and TR I-STATE outputs for bus operation_
OS3678 has a direct, low impedance output for use
with or without an external resistor.
features
• TRI-STATE outputs interface directly with system
bus
• Schottky-clamped for better ac performance
• PNP inputs to minimize input loading
• OTL and TTL compatible
• High-speed capacitive load drivers
• Built-in damping resistor (D51648/0S3648 only)
The OS1648/0S3648 has a 15 ohm resistor in series
with the outputs which dampens the transients caused
by the fast-switching output circuit, while the OS1678/
logic and connection diagrams
OUTPUT
Dual-I "-line Package
(15)
CONTROL
Al~(2~1
________________r-~
INPUTS
OUTPUT
Vee
I..
B1~(3~1------t---------r-~
A2
(51
82
(61
A3
(111
63
(101
CONTROL
15
~
A4
84
INPUTS
OUTPUT
13
14
~
Y4
A3
12
83
Y3
--
1
AA~I"~I------~------~r-~
SELECT
'4 <>'ll.;;31______t-______t-r-~
OUTPUT
10
11
9
0-
2
4
3
At
B1
~
INPUTS
Y4
Yl
OUTPUT
,
5
A2
7
82
"--,-..J
INPUTS
V2
I'
GNU
OUTPUT
TOP VIEW
Order Number 051648J, 051678J
053648J, 053678 or
053648N, D53678N
SELECT
schematic diagram
EQUIVALENT OUTPUT
EOUIVALENT INPUT
r-----------------~--------------~~----_.------Ov~
r
I
I
I
15 (051648/053648 ONl VI
'-------.-"'''''''__0 OUTPUT
INPuT
INTERNAL
lOGIC
CIRCUITRY
~~~----------------__--------------_4------~----_oGND
·Specifications may change.
4-41
absolute maximum ratings
,
operating conditions
(Note 1)
Supply Voltage
Logical "1" Input Voltage
Logical "a" Input Voltage
Logical "1" Output Current
DS1648/0S1678
OS3648/0S3678
Logical "0" Output Current
OS1648/0S1678
OS3648/0S3678
Supply Voltage (Vee)
7V
7V
-1.5V
Temperature (T A)
D81648, D81678
D83648, DS3678
<0.7A
v"
EOUIVALENTINPUT
15 (DSl649!DS36490NlV)
L--_~"""-()OUTPUT
INPUT
connection diagram
typical application
Dual-In-Line Package
Vee
DlSZ
IN6
OUT6
INS
OUT5
IN4
OU14
0536149
OR
0836119
SDITRAM
MOS
DRIVER
ADDRESS
DISABLE
053649
OR
05367&
6 BIT RAM
ADDRESS
DlSt
OUT!
1N2
DUn
IN3
OUT3
MOS
DRiVER
GNO
DISABlE
TOP VIEW
Order Number DS1649J, DS1679J, DS3649J,
DS3679J or DS3649N, DS3679N
truth table
r----'
I
ADDRESS
LINES
MM5270
OR
MM528[}
MOSRAM
ARRAY
REFRESH &
ADDRESS
LINES
I
I
I
I
I
I
I
I
I
L. _ _ _ _ .J
DS3646
OR
DS3li16
CLOCK
MOS
COUNTER
DRIVER
DISABLE INPUT
DIS 1
DIS 2
INPUT
OUTPUT
ENABLE
x
4-46
'"
Don't care
Hi-Z '" TR!-$TATE mode
x
Hj·Z
X
Hi-Z
Hi-Z
ADDRESSOR
CDUNTSELeCT
No-'ADDRESS
"l"COUNTER
"'Specifications may change.
absolute maximum ratings
Supply Voltage
Power Dissipation
Logical "1" Input Voltage
Logical "0" Input Voltage
operating conditions
(Note 1)
7.0V
600mW
7.0V
-1.5V
A
_65°C to +150oC
300°C
MIN
(lOS(OII
<1.0
Logical "1" Output Current
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
MAX
UNITS
<1
A
+125
+70
°c
°c
Logical "0" Output Current,
Operating Temperature Range,
DM1649
DM3649
-55
0
Power Dissipation (POl
Ceramic Package
Mo Ided Package
1160mW
1000 mW
electrical characteristics
* Derate ceramic package at 80°C/W above 70° C; derate molded
package at 90°CIW above 70°C.
en
-..I
Over recommended operating temperature range (unless otherwise noted) (Note 1)
PARAMETER
!
CONDITIONS
MIN
TYP
Logical "0" Input Voltage
I'N(1)
Logical "1" Input Current
Vee = 5.5V
Y'N = 5.5V
0.1
"~NtO)
Logical "0" Input Current
Vee = 5.5V
Y'N = 0.5V
-90
VCLAMP
Input Clamp Voltage
V OH
Logical "1" Output Voltage
VOL
(No Loadl
a rnA
Vee = 4.5V
IOL=OmA
Vee = 4.5V
IOH
Logical "1" Output Voltage
V OH
(With Loadl
VOL
Ji.A
Ji.A
DS 1649/DS 1679
3.4
4.25
V
DS3649/DS3679
3.5
4.25
V
V
DS 1649/DS 1679
0.25
0.45
V
DS3649/DS3679
0.25
0.40
V
DS1649
2.5
3.5
V
DS1679
2.4
3.5
V
DS3649
2.7
3.5
V
DS3679
2.6
3.5
V
0.6
1.1
V
(With Loadl
D51679
0.3
0.5
V
,
ICC(MAX)
-1.0 rnA
40
-250
DS1649
Logical "0" Drive Current
100
:=:
V
Logical "0" Output Voltage
Logical"'" Drive Current
'10
Maximum Power Supply
Current
ICC1MIN)
IOH =
0.8
-1.2
liN:; -18 rnA
Vee = 4.5V
UNITS
,
V
Logical "1" Input Voltage
V 1NW)
Logical "0" Output Voltage
MAX
2.0
V 1N (1l
(No Loadl
Minimum Power Supply
Current
Vee = 4.5V
Vee = 4.5V
Vee = 4.5V
IOL==20mA
DS3649
0.6
1.0
V
DS3679
0.3
0.5
V
VOUT = OV
DS1649/DS1679
-170
mA
(Note 21
DS3649/D53679
-170
mA
V OUT =4.5V
DS1649/D51679
170
mA
(Note 21
DS3649/DS3679
170
mA
DS 1649/DS 1679
42
rnA
DS3649/DS3679
42
rnA
DS1649/DS1679
11
rnA
DS3649/DS3679
11
rnA
Vee = 5.5V
Vee = 5.5V
switching characteristics
= 5V, T A = 25°C) (Note 4)
(V CC
PARAMETER
tpd(O)
CONDITIONS
Propagation Delay to Logical "0"
(Figure 1)
t pd(l}
Propagation Delay to Logical "1"
(Figure 1)
tHO
Delay from Disable Inp~t to Logical "0"
i Level (from High Impedance State)
• tH1
tOH
t'H
..c
en
(Note 2 and 3)
MIN
TYP
MAX
UNITS
CL = 50 pF
7
n,
CL - 250 pF
CL - 500 pF
15
ns
25
ns
CL = 50 pF
7
ns
CL - 250 pF
15
ns
CL - 500 pF
25
ns
14
ns
14
ns
14
ns
14
ns
CL = 50 pF
RL =2kntoV ee
to Gnd
(Figure 2)
Delay from Disable Input to Logical "1"
CL = 50 pF
RL =2kntoGnd
Level (from High Impedance State)
to Gnd
(Figure 2)
Delay from Disable Input to High Impedance
CL = 50 pF
RL = 400n to Vee
State (from Logical "0" Level)
to Gnd
(Figure 3)
Delay from Disable Input to High Impedance
CL = 50 pF
RL = 40pn to Gnd
State (from Logical "'" Levell
to God
(Figure 3)
4-47
CD
.......
C
en
w
en
~
notes
Note 1:
II
Absolute Max'imum Ratings", are those values beyond which the safety of the device cannot be guaranteed. Except' for UOperating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
.
Note 2: Unless otherwise specified 'minimax limits apply across the -55 0 e to +125°e temperature range for the OS1649 and OS1679 and across
th'e oOe to +70o e range for the OS3649 and OS3679. All typical values are for TA = 25°e and Vee = 5V,
. '
Note 3: All currents intoidevice pins shown as positive~ but of device pins as negative, all voltages refereru:ed to ground unless' otherwise noted.
All values shown as max or min on absolute value basis.
Note 4: When measuring output drive current and switching response for the OS1679 and 083679 a 15 ohm resistor should be placed in Series
with each output. This resistor i~ internal to the'OSI649IDS3649 and need not be added.
ac test circuits and switching time'waveforms
, tpdO and tpd'
;-.w....._-o
v"
VOUT
I-'w...............t-O
'Villi
.00
toH
tHO
V~
O.I,1lF
INPUT"
11.5V '~"'V
.. . . . . .
~
,
OUTPUT
O.IV
,
'
22V
~
V,.
VOUT
,
,-
v,.
lSD"
lSD"
"lnputSiaJIIICharactlllnics:
Freq "'1 MHz
Dutycyde- 50%
AmpJitude = DAV to l.DV
~. =t, "'2.5ns
INPUT*
INPUT"
OUTPUT
OUTPUT
~ltH'
~
FIGURE-'
4·48
FIGURE 2
1~
~1.tiV
FIGURE 3
VOUl
Memory/Clock Drivers
~
Advance Information*
NAnONAL
OS1671/0S3671 bootstrapped two phase MOS clock driver
general description
The OS1671/0S3671 is a high speed dual MaS clock
driver and interface circuit. Unique circuit design provides both very high speed operation and the ability
to ,drive large capacitive loads. The device accepts
standard TTL/OTL outputs and converts them to MaS
logic levels. It may be driven from standard 54n4
and 54Sn4S series gates and flip·flops or from drivers
such as the OS8830 or OM7440. The circuit can be used
in both P-channel and N-channel MaS memory system
drive applications.
Each driver uses output bootstrapping to provide a
higher voltage to the output stage, thus eliminating the
need for an additional Voo supply. The bootstrapping
function is accomplished by connecting a small value
capacitor (typically 200 pF) from each output to each
drivers bootstrap node.
features
•
•
•
•
•
Fast rise and fall times-20 ns with 1000 pF load
High output swing-20V
High output current drive-±1.5A
TTL/OTL compatible inputs
High rep rate-5 to 10 MHz depending on power
dissipation
• Low, power consumption in MOS "0" state-2 mW
• Swings to O.4V of GNO for RAM address drive
The OS1671/0S3671 is intended to fulfill a wide
variety of MaS interface requirements. As a MaS clock
driver for long silicon gate shift registers, a single device
can drive over 10k bits at' 5 MHz. Six devices provide
input address imd precha,rge drive for an 8k by 16-bit
1103 RAM memory system.
connection diagrams
Dual~1 n-Line
Metal Can Package
v+
OUTl
Dual-I n-Line Package
Package
B2
QU12
"
v'
v'
14
"
OU12
13
12
vTOPYIEW
IN 1
B1
Order Number OS1671H
or DS3611H
V-
TOP VIEW
Order Number
OS3671N
IN2
Ne
BI
Dun
NO
INI
Ne
v'
TOP VIEW
Order Number OS1671J
or OS3671J
typical applications
v,·
>c>-'w.......-o OUTPUT
IN
"
v·SEE GRAPH FOR VALUE
0S3671 Operating with Extra Supply
to Inhance Output Voltage Le.el
Bootstrap Clock Driver Driven from a TTL 'Gate
*Specifications may change.
4·49
absolute maximum ratings
Input Current
Pea k Output Current
Storage Temperature Range
lead Temperature (Soldering, 10 seconds!
Power Dissipation" (PO)
Ceramic Package
Molded Package
Metal Can
L~gi~al "1" fnput'V'oltage
V
I'H
Logical "1" Input Current
Y'N - V- = 2.4V
V'L
logical "0" Input Voltage
V- =·OV
'IL-
logical "0" Input Current
V,N-V-e.OV
VOH
Logical
Logical "0" Output Volt~
Bootstrap Control Resistor
ICC(OFFI
=OV
1.5
10
I 053671
I
051671
V+-1.0
V -1.2
Supply Current "OFF"
V+ - V- = 20V, Y'N - V-
= ov
mA
°A'
V
-10
p.A
V
V
V-+1.0
V
2.0
3.3'
kn
30
40
mA
I OS3671
lQ
OSI671
50
100
500
p.A
p.A
I
T A = 25°C,
15
V-+0.6
1.1
V+ - V- = 20V. Y'N - V- = 2.411.
VB = V+ .lOne Side Only)
UNITS
V+--o.75
V --0.75
= 0 mA
"ON"
MAX
V
0.6
PARAMETER
tpd1
:rVP
2.0
-3
Y'N - V- = 2.4V,
switching characteristics
tpdO
MIN
10
VB ~ v+ + 1.0V, Y,N - V- '" Q.4V,
10 = OmA
Supply Current One Side.
Icc ION)
" Derate ceramic package at SOO C/W above 70° C; derate molded
package at 90'C/W above 70°C; derate matal can package at
200°C/W above 70"C.
CONOITIONS
V,H
RB
'c
°c
(Notes 2 and 3)
PARAMETER'
VOL
V
V
V
+70
+125
0
~5
D~1671
1160mW
890mW
525mW
UNITS
20
·40
20
Operating Temperature Range
053671
300"C
Output VoJtage
..
Supply Voltage
V+ - V- Differential
VB:'" V- Differential
VB - V+ Differential
~5"Cto+150"C
electrical characteristics
.t
MAX
Mli\I
22V
40V
20V
5.5V
l00mA
1.5A
VB ::. V- Differential
VB - V+ Differential
Input Voltage (VIN - V-I
~'1"
operating conditions
(Note 1)
v+'~ v- Differential
v+ = 20V, V-= OV
CONOITIONS
MIN
TVP
MAX
UNITS
Propagation Delay to a
Logical ~·O"
Ro = Ion. CL = 1000 pF
7.5
ns
Propagation Delay to a
Ro = lOn, CL = '1000 pF
12
ns
C L = 500 pF
C L = 1000 pF
25
31
ns
C L = 500pF
30
38
ns
ns
Logical "1"
t,
Rise Time
tt
Fall Time
Ro = Ion
Ro = Ion
C L = 1000pF
ns
Not. 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cennot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the -55"C to +125"C temperature r~~ge for the 051671 and across the
OoC to. +70'C range for the 053671. All typicals at 25'C.
Note 3: All currents into device pins shown as positive, out of device pins as negative .. all voltages referenced to ground unless otherwise noted.
All values shown as max or min on absolute value basis.
typical performance characteristics
Turn-On and Turn-Off Time
VI Temperature
Input Current vs
Input Voltage
1&
J
8
C
S
...
..
ifl
1:l
J
4
2
...
0
!!
-2
i£
V
S
-4
-S
-
V
(
I
0.5 1.0 1.5 2.0 2.5
(V ,N - Y-) - INPUT VO~ lAGE (V) •.
4-50
~
w
~
~
..
.....
~
9
Z
....'"
Z
9
'"
II
-1.0-0.5 0
]
24
22
20
18
16
14
12
10
8
6
4
2
0
Fall Time vs load Capacitance
40
IN
[',
toFF
L
.- I-"'"
V
30
1
./
!II
;:
J
20
10
!i4SIIO ON INPUT·
V
I{
~
~
::;
Vee = 20V
CIN = CL :: 100pF
J
V
0
-50 -25
0
25
50
75 100 125
TEMPERATURE ("CI
..-
0
200
400
l~AD
680
.tio
1000 1280
CAPACITANCE (pf)
typical performance characteristics (con't)
Output Pul ... Width When
Controlled Only by Input
Coupling Capacitor
Rise Time vs load Capacitance
800
40
700
30
-.
.s
~
;::
20
/
w
~
"'
10
V
-
I-""
]
.,..."
x
~
~
600
500
V
...=>
~
200
100
200
400
600
800
1000
1200
/
/
INPOT~
OUTPUT~
200
LOAD CAPACITANCE (pF)
/
/
/
400
=>
300
V
Cl ~ 1000 pF
Vee" ZOV
TA"25"C
400
600
800
1000 1200
CIN ~ INPUT CAPACITANCE (pF)
ac test circuit and switching time waveforms
.,v
t
+20V
1-""-1
v,"
V'"~I'V
J
'.'V\
~I '--~-<,-"-
I~ <,"
90%
90%
10%
0-3V
-<,
1,"11"51"
tpw ""
400 ns
fREQUENCV = 1 MHz
node voltage waveforms
typical applications (con"t)
400n5-------00'm
INPUT
o---j
v·---1-·~-----------4,
x,......W\o--Q
OUTPUT
"
C,"
OUTPUT
OS3671 Connected as OS0026
with Equivalent Characteristics
--Note 1: The faU time has an exponential dec", with the fallowing time constant: til = til Ra·
The lange of values for flu (resistor tolerance, and temperature coefficient induded) can be
found in the table of electrical tharacteristics.
Nnte 2: The high tllnent transient (as high IS 1.SA) through th! fWsunce of the extern.'
interconnecting V-lead during the output trlnsition from the high state tn the low staw can
appelr as negative feedback to the input. It the external intllrconmn:ting lead from the driving .
cireuit til V- is electric:llly IlIng, or has significant DC resistanc~. it can subtraet from tile
Mitchingl!s\lollu.
+ZOV
~
L:S1
IN
1000 pF
Typical Bootstrap
4·51
schematic diagram
(One Driver)
EXTERNAL
BOOTSTRAP
BOOTSTRAP
PIN
CAPACITOR
C,
. . ----U-- ---,
I
v·
I
I
I
I
'011
,,-
R9
R8
I
2k
I
D5
"
~
1""01
t:;-
~'
...
1..,;'
os
...
....
R2
EXTERNAL
0-H-~ I~
~
....
R3
"'t"'
"I
I
I
I
*
..;'
c"
J
I
1
1
1
....,.06
OUTPUT
:"
0.;.
R4
....,.0'
~
....
R5
10.
4-52
J!l- DlO
.
l'
.,
1/2053671
0'
I
v-
Memory/Clock Drivers
~
Advance Information*
NAnONAL
OS16149/0S36149, OS16179/0S36179 hex MOS drivers
general description
The 0516149/0536149 and 0516179/0536179 are
Hex M05 drivers with outputs designed to drive
large capacitive loads up to 500 pF associated with M05
memory systems. PNP input transistors are employed to
reduce input currents allowing the large fan-out to these
drivers needed in memory systems. The circuit has
5chottky-clamped transistor logic for minimum propagation delay, and a disable control that places the outputs in
the logical "1" state (see truth table). This is especially
useful in M05 RAM applications where a set of address
lines has to be in the logical "1" state during refresh.
The 0516149/0536149 has a 15 ohm resistor in series
with the outputs to dampen transients caused by the
schematic diagram
fast-switching output. The 0516179/0536179 has a
direct low impedance output for use with or without
an external resistor.
features
•
High speed capabilities
• Typ 7 ns driving 50 pF
• Typ 25 ns driving 500 pF
•
Built-in 15 ohm damping resistor (0516149/0536149)
• 5ame pin-out as 058096 and 0574366
EQUIVALENT INPUT
r-----'--::::-,=-::=-=-:::f--=--.....- -...---O,,,
15 (DS16149/DS36149 ON~V)
'---+-""....
_0 OUTPUT
INPUT
L ___ _
L--'-----~=-==~==~=-==~=-_~
connection diagram
Dual~1
__ __
~
_oGND
typical application
n-Line Package
08]6149
OR
0536119
r----'
1------,
1------1
681T RAM
1-____,
ADDRESS
LINES
MM5210
OR
MM5280
MOS RAM
053649
OR
053679
MOS
6BIT RAM
ADDRESS
olSI
IN2
OUT 1
GND
DISABLE
TOP VIEW
Order Number DS16149J, DS16179J, DS36149J,
DS3617J, DS36149N or DS36179N
I
I
I
I
I
I
I
I
I
053646
OR
OS3676
truth table
CLOCK
DISABLE INPUT
DIS 1
DIS 2
0
0
0
1
0
0
1
1
x
-
0
1
Don t care
MDS
COUNTER
DRIVER
INPUT
0
1
X
X
X
OUTPUT
1
0
1
1
1
ADDRESSOR
COUNT SELECT
"0" ADDRESS
·Specifications may change.
4-53
absolute maximum ratings
operating conditions
(Note 1)
MIN
Supply Voltage
Power Dissipation
7.0V
Logical "0" Output Current,
600mW
Logical "1" Input Voltage
1I0S(011
7.0V
-1.5V
l:-ogical "0" I nput Voltage
Logical "1" Output Current
Storage Temperature Range
Le~d Temperature (Soldering, '10 seconds)
0
(TMAXI
1160mW.
1000 mW
electrical characteristics
UNITS
<,.
A
+70.
°c
Operating Temperature Range,
<1.0 A
_65°e to +150°C
3000 e
Power Dissipation (PO)
Ceram ic Package
Molded Package
MAX
* Derate ceramic package at 80°C!W above 70°C; derate molded
package at 90° e/W above ioo c.
(Note 2 and 3)
Over recommended operating temperature range (unless otherwise noted) (Note 1)
PARAMETER
CONOITIONS
V1N(O)
Logical "0" Input Voltage
IIN(l)
Logical "1" Input Current
Vee
S.SV
V 1N
'"
S.5V
IIN{Q)
Logical "0" Input Current
Vee" 5.5V
V'N
c
0.5V
VCLAMP
Input Clamp' Voltage
VOH
Logical"1" Output Voltage
(No Loadl
IOH=OrnA
OS16149/0S16179
3A
4.25
OS36149/0S36179
3.5
4.25
-250
)1A
-1.2
V
V
V
0.25
OAO
V
Logical "1" Output Voltage
OS16149
2.5
3.5
V
(With Loadl
OS16179
OS36149
2A
3.5
V
2.7
3.5
V
OS36179
2.6
3.5
Vee" 4.5V
Vee" 4.5V
IOL
=
0 mA
IOH = -:-1.0 rnA
V
Logical "0" Output Voltage
OS16149
0.6
1.1
V
(With Loadl
OS16179
0.3
0.5
V
OS36149
0.6
1.0
V
OS36179
0.3
0.5
V
Vee" 4.5V
Current
Minimum Power Supply
ICC(MINl
-90
-18 mA
)1A
OS36149/0S36179
Maximum ~ower Supply
ICC(MAXl
Vee· 4 .5V
r
V
40
V
Logical "0" Drive Current
100
tiN'"
0.1
0.45
Logical ,"l" Drive Current
I'D
V
'0.8
==
UNITS
0.25
(No Loadl
VOL
MAX
OS16149IDS16179
Logj'cal "0" Output Voltage
V OH
TYP
2.0
Logical "1" Input
VOL
MIN
Volt~ge
V IN (l)
Current
Vee" 4.5V
V ec '" 4.5V
IOL = 20 rnA
=OV
OS16149/0S16179
-170
mA
OS36149/0S36179
-170
mA
V OUT = 4.5V
OS16149/0S16179
17.0
mA
(Note 21
OS36149/0S36179
170
mA
OS16149/0S16179
42
mA
OS36149/0S36179
42
mA
OS16149/0S16179
11
mA
OS36149/0S36179
11
mA
'Ji OUT
(Note 21
Vec "5.5V
Vee" 5.5V
switching characteristics
(Vee
= 5V,
,
TA
= 25°C)
(Note 4)
PARAMETER
tpd(Ol
Cl "50 pF
(Figure 1)
tpd(1l
Propagation Delay to Logical "1"
(Figure 1)
tH1
Delay from Disable Input to Logical "1"
CL = 500 pF
, to Gnd
4-54
MIN
CONDITIONS
Propagation Delay to Logical ';0"
TYP
'7
MAX
UNITS
ns
Cl "250 pF
15
ns
Cl "500 pF
25
ns
Cl
7.
ns
Cl "250 pF
15
ns
Cl "500 pF
25
ns
25
ns
"
50 pF
Rl "2kntoGnd
(Figure2J
notes
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for ~'Operatin9
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified minimax limits apply across the -5Soe to +12Soe temperature range for the 0816149 and 0816179 and across
the oOe to +70o e range for the 0836149 and 0836179. All typical values are for TA = 2Soe and Vee = 5V.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted.
All values shown as max or min on absolute value basis. '
.
Note 4: When measuring output drive current and switching response for the 0816179 and 0536179 a 15 ohm resistor should be placed in series
with each output. This resistor is internal to the 0816149/0836149 and 'need not be added.
ac test circuits and switching time waveforms
tpdO and tpd 1
tH1
v"
vee
O.1JJF
~
~
15£!
(NOTE 41
V'N
D836179
VOUT
V'N
D836179
ICC
,00"J
-=
·"1
-=
~.
INPUT"~1.6V
OUTPUT
V OUT
......1.6V
2k
-=
INPUT*
t .. ,
4'nputSignaIC"'I8r:teri51.ics;
Freq= 1 MHz
2.2V
O~V
FIGURE 1
Duty cycle;. 50%
Amplitude'" O.4V to 3.DV
t,=tl "'2.5ns
OUTPUT
FIGURE 2
4·55
M
~
Memory/Clock Drivers
o
NAnONAL
o
......
CJ)
057803/058803, 058813 two phase oscillator/clock driver
M
o
genera' description
00
00
~
Q
DIP. The DS8813 comes in an 8·pin molded DIP,
providing damped MOS outputs only.
The DS7803 is a self contained two phase oscillator/
clock driver. It requires no external components to
generate one of three primary oscillator frequencies
~n'd pulse widths. Other frequencies can easily be
obtained by programming input voltages. Three sets of
outputs are provided: damped and undamped MOS
outputs and TTL monitor outputs. The MOS outputs
easily drive 500 pF loads with less than 150 ns rise and
fall times. In addition the outputs have ClJrrent limiting
to protect against momentary shorts to the supplies.
features
•
•
•
•
•
•
The DS7803 and DS/3803 are available in a 14-lead cavity
DIP. The DS8803 is also available in a 14-pin molded
Two phase non-overlapping outputs
No external timing components required
Frequency adjustable from 100 kHz to 500 kHz
Pulse width adjustable from 260 ns to l.4ils
Damped and undamped MOS outputs
TTL monitor outputs
block and connection diagrams
057803/058803
Dual~ln-line
11
"
Package
v"
14 Vss
,
.0' ,
INHIBIT
TTL 1>1
WIOTH
CONTROL
13 rEST
12 FRED
CONTROL
DAMPEI)iii,
rTL"'i
MDSof>,
v"
R.
"
, '0'
MOS2
OND
TTL 1>,
TTL 4>2
v••
OND
MOS
DAMPED .:>,
Mas",
MOS92
TOP VIEW
Order Number OS7803J, D58803J
or OS8803N
058813
FR~~~~:~r
PUlse WIDTH
CONTROL
Dual-ln-LinQ Package
0..:'+-____-,
PULSE
5
I
INHIBIT
WIDTH
,.,]
"
~"
MO'
DA""D
TEST
"
OUTPUTS
5
P--.....IYv----ir<>
"
"
FREQ
CONTROL
TOP VIEW
Order Number 058813N
TEST
4-56
INHI81T
c
absolute maximum ratings
22V
7.0V
Vss- Voo
VCC - Gnd
Pulse Width Adjust Voltage
VSS - VOO. Minimum
VSS
VSS
14V
Test and Inhibit Input Voltages
VSS
Frequency Adjust Voltage
Operating Temperature Range
-55°C ta +125°C
O°C to +70°C
-65°C ta +150°C
300°C
OS7803
OS8803.0S8813
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
~
00
o
w
........
c
en
00
00
o
electrical cha racteristics
w
(Notes 1, 3)
c
PARAMETER
F
Frequency
PW
TVP
MAX
UNITS
en
300
500
600
kHz
Pin 12 Open
175
300
350
kHz
00
....
W
Pin 12 at OV
60
100
150
kHz
Pin 12 at 17V
TA = 25°C
L::.F
MIN
CONDITIONS
Frequency Change from 25°C
Pin 12 at 17V
Pulse Width
CL = 15 pF, TA = 25°C.
(Note 2)
L::.PW Pulse Width Change from 25°C
VOL Logical "0" Output Voltage
±30
%
±10
±15
%
0.2
0.26
0.4
I1S
Pin 2 Open
0.5
0.75
1.3
ps
Pin 2 at OV
1.0
I OS7803
I OS8803
1.4
2.6
ps
±20
±30
%
±10
±15
%
10H = -1 DOpA
MOS
V ss-1.1
Vss-0.8
V
10H = -200pA
TTL
2.4
3.7
V
MOS Outputs
10L = 2.0 mA
10L - 2.0 mA
TTL Outputs
Output Short Circuit Current
±20
Pin 2 at 17V
Pin 2 at 17V
V OH Logical "1" Output Valtage
los
I OS7803
I OS8803
OS7803
10L = 3.2 mA
V
Voo+0.15 Voo+0.5
I OS7803
I OS8803
TTL Outputs
3.0
V
0.17
0.3
0.2
0.4
V
8.0
15
mA
±70
mA
los
Output Current Limit
MOS Outputs
Iss
Supply Current
Pins 2, 12, 13 at OV. and Pin 1 at -0.3V
10
17
mA
Icc
Supply Current
Pins 2 and 12 at OV, and Pin 1 at -0.3V
0.75
1.1
mA
Ro
Damping Resistor
7.0
10
13
5.0
10
15
0.
0.
100
150
ns
20
30
ns
tr,tf
I OS7803
.LOS8803
Rise and Fall Times
CL =500pF
C L = 50 pF
T A "25°C, MOS
Note 1: These specificatians apply far the OS7803 at VSS - VOO = 17V ±10% and over -55°C ta +125°C; for the OS8803, OS8813 at VSSVOD = 17V ±5% and over O°C to +7.0°C unless otherwise specified.
Note 2: The duty cycle can not physically exceed 50% at any output. At high frequencies the frequency adjust pin will affect the pulse width by
limiting the duty cycle to slightly less than 50%. Under this condition the pulse width spec does not apply.
Note 3: The above specs apply to the DS8813 only where applicable, and approriate pin ':lumbers should be substituted.
typical performance cha racteristics
Frequency Control Voltage
Frequency and,Pulse Width
vs Temperature
Pulse Width Control Voltage
600
1.5
20
g
500
w
=>
~>
400
~
300
u
~
]:
...'"c
PIN Z 0 PEN
;:
PIN 12 OPEN-
~
200
,."
u
1.0
I
1.0 3.0 5.0 7.0 9.0 11
0.5
0
13
15
17
FREQUENCY CONTROL VOLTAGE MINUS Voo (V)
1.0 3.0 5.0 7.0 9.0
11
F~EIQJE~C~
13
15
17
PULSE WIDTH CONTROL VOLTAGE MINUS Voo (V)
V'
10"
0
N
100
0
1\
10
~
-10
'"z
~
-20
II
1I
'" I'
N.
P.W.
II
-30
-75 -50 -25
I
0
25
50
75 100 125
AMBIENT TEMPERATURE (OC)
4-57
00
typical performance characteristics (con't)
Frequency and Pulse
Width
g
M
~
o
"
00
00
~
o
.......
.
..
o
'=
ff:"
2iI
1\
80
IT~J2~oJ
;wf
10
Total Transient Power
vs Frequency
j....
"'"
j;
~
~
~
....
(/)
=>
~
> -10
M
~o
..
w
'"z
1
CL "500 1
'Y
60
V
40
~
;;!
-20
20
~
~ -30
12
14 . 15
13
16
17
20
21
V
/
. /V
C, :5b,F_ 0 =
100
22
VSS-VOD
ISS
v. Duty Cycle
4.0
jl
300
400
500
600
ICCv, Duty Cycle
0.'
6.0
~
200
FREQUENCY (kHz)
8.0
;;;
CL = 250 pF
I. . . . .
V1
1/
~
FREQUENCY
A
. . .V -----
.....-
0.8
......
;;;
~
0.7
f'."
.......
Jl
.............
0.6
2.0
0.5
10
20
30
40
50
o
10
DUTY CYCLE (%) ,
20
30
t--....
40
50
DUTY CYCLE (%)
applications information
TTL MONITOR OUTPUTS
MOS
~
0=
The TTL outputs are extra functions provided for
monitor or synchronization applications. In some systems these outputs may not be required. For these
cases, the Vee pin may be left open and the TTL
circuitry power consumption will be virtually zero.
For small space requirements, the OS8813 8-pin DIP
is available, which has the TTL outputs deleted.
1.0=
,t.5VTHRESHDlD
~
TIL
TTL,
¢,
¢'1
l.O=~l
10
~~l~
Outputwaveformi
with +17V,OV,+5V supplies
Outputwavefolms
with +5V, -12V, +5V supplies
(A)
(8)
FIGURE 1.
DAMPED MOS OUTPUTS
the following functional description:
An extra set of MOS outputs provides a 10 ohm resistor in
series with each output line. These resistors give the output pulses an RC roll off which tends to minimize ringing
or peaking problems associated with board layout.
INHIBIT Input: in the low state prevents pulses from
being initiated on either phase output.
INHIBIT AND TEST INPUTS
The INHIBIT and TEST inputs are designed to facilitate
testing of the device. They were not included in the IC
for system use. The truth table of Figure 2 supplements
4·58
IfiA
:;=
The TTL outputs are slaved to the MOS outputs. Thus
the TTL outputs start to switch when the MOS outputs
cross the TTL threshold voltage (about 1.5V above
ground). Figure 1 depicts the effect of different supply
voltages on the TTL waveform when the MOS outputs
are driving capacitive loads.
High Level Input:
V 1H
::::
V DD + 2.0V
Low level Input:
V DD + O.2V:::: V 1L
::::
VDD -O.5V
o
en
applications information (cont.)
TEST
INPUT
Open
Open
Normal Operation
Low
Low
Open
High
Low
Low
OUTPUT
P01SS = PAC + Poc
o
en
s: PMAX
co
co
o
w
o
PAC = PAC TTL + PAC MOS
TEST Input: in the low state forces a "1" state on all
outputs. The test input should only be used with the
INHIBIT input also in the low state.
en
co
PAC = [(V cc -Gnd)2 xfxCLl TTL
~
+[(Vss-Voo)2xfxCLl MaS
w
And
High Level:
2
w
.......
Where:
FIGURE 2. Truth Table
V 1H
~
o
particular operating temperature to insure safe opera·
tion, i.e.:
INHIBIT
INPUT
POC = (Icc! x (Vce - Gnd) + (Iss) x (Vss -V oo )
Voo + 8.0V
Low Level:
for Icc and Iss at the appropriate duty cycle.
For practical cases the PAC TTL can be neglected as
being very small compared to PAC MOS'
A pull·up resistor is connected from the TEST pin to
Vss internally.
POWER CONSIDERATIONS
Internal power dissipation is affected by three factors:
1. dc power
2. ac power
3. package dissipation capability
The total average power dissipation is the summation
of the dc power and ac power. This sum must be less
than the maximum package dissipation capability at the
ac test circuit
Thus P01SS is the sum of the MaS transient power
(total for both sides of the DS7803) and the standby
power of the TTL and MaS sections of the OS7803.
DECOUPLING
It is recommended that each device be decoupled with
a O.lf.lF capacitor from Vss to VDO. If there is noise
on the supply lines, better frequency and pulse width
stability can be obtained by connecting a O.OOlf.lF
capacitor from the frequency control pin to V 00 and
another O.OOlf.lF capacitor from the pulse width control
pintoV oo '
timing diagram
11\1
5\1
PULSE
WIDTHO
SELECT
MOS{"
DAMPED
OUTPUTS
o
FREQUENCY
SELECT
920--+---.--""1
"
4·59
g
Memory/Clock Drivers
co
(/J
Q
S
co
co
(/J
Q
.......
"o~
(/J
Q
057807/058807, 058817 two phase oscillator/clock driver
general description
The 057807 is a self contained two phase oscillatorl
clock driver. It requires no external components to
generate one of three primary oscillator frequencies and
pulse widths. Other frequencies can easily be obtained
by programming input voltages. Three sets of outputs
are provided: damped and un-damped MaS outputs and
TTL monitor outputs. The MaS outputs easily drive
500 pF loads with less than 75 ns rise and fall times.
In addition the outputs have current limiting to protect.
against momentary shorts to the supplies.
The 058817 comes in an 8-pin molded DIP, providing
damped MaS outputs only.
features
•
•
•
•
•
•
The 057807 and 058807 are available in a 14·lead
cavity DIP. The 058807 is also available in a 14-pin
molded DIP.
Two phase non-overlapping outputs
No external timing components required
Frequency adjustable from 400 kHz to 2 MHz
Pulse width adjustable from 130 ns to 700 ns
Damped and un-damped MaS outputs
TTL monitor outputs
block and connection diagrams
OS7807/0S8807
co:.:~~~ O-;T--------,
FREQUENCY
CONTROL
Dual-'In-Line Package
11
Vee
"
14
INHIBIT
TTL
ell
WIDTH
CONTROL
MOS
DAMPED \'1
V"
2
13 TEST
3
12 FRED
CONTROL
11
MOS,,),
TTl '"2
V"
10
DAMPED \l2
GNO
RD
"
"
RD
TTL 92
MOS92
MOS
DAMPED
v,
TTl'?l
'!DD
GNO
MOS
DAMPED "2
TOP VIEW
MOSy,
Order Number OS7807J,
OS8807 J or OS8807N
MOS('2
OS8817
Dual-I n-line Package
PUlSE
1
INHIBIT
WroTH
PULSE WIOTH
CONTROL
10
TEST
Q'l'MDAMPED
OS
OUTPUTS
FRED
VDO
CONTROL
10
P---'VI.fIr---+'-O Q,
L---!r-"---'
TOP VIEW
Order Number OS8817N
V"
4·60
VDD
TEST
INHIBIT
absolute maximum ratings
22V
7.0V
Vss
Vss
14V
Vss
Vss-Voo
Vcc-GND
Pulse Width Adjust Voltage
Frequency Adjust Voltage
Vss-Voo, Minimum
Test and Inhibit Input Voltages
Operating Temperature Range
DS7807
DS8807, DS8817
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
electrical characteristics
-55°C to +125°C
O°C to +70°C
-65°C to +150°C
300°C
(Notes 1 and 3)
PARAMETER
F
CONDITIONS
Frequency
MIN
Pin 12at 17V
Pin 12 Open
T A = 25°C
Frequency Change from 25°C
DS7807
Pin i2 at 17V
OSS807
PW
Pulse Width
C L =15pF,
T A = 25°C,
(Note 2)
Pin 2 at 17V
Pin 2 Open
Pin 2 at OV
Pin 2 at 17V
OS7807
OS8807
Ll.PW
Pulse Width Change from 25°C
VOH
Logical "1" Output Voltage
MOS, 10H = -1OOIlA
TTL, 10H = -2OO!J.A
VOL
Logical "0" Output Voltage
MOS, t OL = 2.0 mA
los
Output Short Circuit Current
los
MOS Output Current Limit
Iss
Supply Current
Icc
Supply Current
Ro
Damping Resistor
t" tf
Rise Time and Fall Time
TTL
kHz
%
%
0.13
0.38
!J.s
0.70
!J.s
!J.s
%
%
±20
±10
Vss -1.1
2.4
3.0
UNITS
MHz
MHz
±20
±10
10L= 2.0 mA,
OS7807
IOL=3.2mA,
OS8807
TTL
MAX
2.0
1.2
400
Pin 12 at OV
Ll.F
TVP
Vss -0.8
3.7
V
V
Voo+0.15
0.17
Voo+0.5
0.3
V
V
0.2
0.4
V
8.0
15
mA
±140
mA
Pins 2,12,13 at OV, and
Pin 1. at -0.3V
13
mA
Pins 2,12 at OV, and
Pin 1 at -0.3V
0.75
1.1
mA
10
10
13
15
n
n
OS7807
OS8707
T A =25°C,
7.0
5.0
C L = 500 pF
C L =50pF
MOS
50
10
ns
ns
'.
Note 1: These specifications apply for the 0571;107 at V55 - VOO = 17V ±10% and over -55°C to +125°C; for the 058807, OSSB17 at
V5S - VOO = 17V ±5% and over O°C to +70°C unless otherwise specified.
Not. 2: The duty cycle can not physically exceed 50% at any output. At high frequencies the frequency adjust pin will affect the pulse width by
limiting the duty cycle to approximately 40«J6. Under this condition the pulse width spec does not apply.
Note 3: The above specs apply to the 058817 only where appl icable, and appropriate pin numbers should be substituted.
4·61
ac test circuit
l1V
SV
PULSE
WIDTH 0
o
SELECT
MOS{.'
DAMPED
OUTPUTS
..
0-,--....----''"1
FREOUENCY
SElECT
timing diagram
applications information
TTL MONITOR OUTPUTS
DAMPED MOS OUTPUTS
The TTL outputs are extra functions provided for
monitor-or synchronization applications. In some systems
these outputs may not be required. For these cases the
Vcc pin may be left open and the TTL circuitry power
consumption will be virtually zero. For small space
requirements, the. 058817 8-pin OJP is available which
has the TTL outputs deleted.
An extra set of MOS outputs provides a 10 ohm resistor
in series' with each output line. These resistors give the
output pul~es an RC roll off which ten'ds to' minimize
ringing or peaking problems associated with board layout.
The TTL. outputs are slaved to the MOS outputs. Thus
the TTL outputs start to switch when the MOS outputs
cross the TTL threshold voltage (about 1.5V above
ground). Figu~ 1 d~pici:~ the effect of different supply
voltages on the TTL waveform when the MOS outputs
.
are ~riving capacitive loads.
,.
.,
MOS
8.11-
l-~~Sr
0-8.0-
:-=-+-+"\
~;.'; ~. V0\ II. }·~.~£SHOLD
4.0-:-
1.0=
':,L
:::= . . .
-
.'
1.0-
.
!fA
TTL
.¢2
.
•
Olltputwavefollll5
with +11V. av, +5V supplies
FIGURE 1.
4-62
rDr
INHIBIT AND TEST INPUTS
The INHIBIT and TEST inputs are designed to facilitate
testing of the device. They were not included in the IC
for system use.
INHIBIT
INPUT
TEST
INPUT
Open
Open
Normal Operation
Low
Open
High
Low
Low
Low
OUTPUT
FIGURE 2. Truth Table .
MOS
~
Outplltwaveforms
with +5V. -12V, +5V supplils
The' truth table of Figure 2 supplements the following
functional description: .
INHIBIT Input: in the low state prevents pulses from
being initiated on either phase output.
High Level· Input:
V ,H ~ Voo + 2.0V
Low Level Input:
,voo + O.2V ~ V,L ~ Voo - O.5V
c
en
applications information (con't)
~
§
Where
TEST Input: in the low state forces a ONE state on all
outputs. The test input should only be used with the
INHIBIT input also in the low state.
PAC = PAC TTL + PAC
PAC
High Level:
V IH
(f)
CO
CO
= [(Vcc -GNO)2 xfxCll TTL.
+ [(Vss -VDO )2
V DD + 8.0V
:;:::
C
MaS
X
~
c
f x Cll MOS
And
Low Level:
en
CO
CO
PDC = (Icel x (Vcc - GND) + (Iss)
V DD + 0.5V:;::: V ll :;::: V OD
::::l
x(VSS-V DD )
A pull·up resistor is connected from the TEST pin to
Vss internally.
for Icc and Iss selected at the apporpriate duty cycle.
POWER CONSIDERATIONS
For practical cases the PACTTl can be neglected as
being very small compared to PAC MOS'
Internal power dissipation is affected by three factors:
Thus PDISS is the sum of the MOS transient power
(total for both sides of the OS7807) and the standby
power of the TTL and MOS sections of the OS7807.
1. dc power
2. ac power
OECOUPLING
3. Package dissipation capability
It is recommended that each device be decoupled with a
O.l/lF capacitor from Vss to V DO ' If there is noise on
the supply lines, better frequency and pulse width
stability can be obtained by connecting a O.OOl/lF
capacitor from the frequency control pin to V DO and
another O.OOl/lF capacitor from the pulse width control
pin to V DD .
The total average power dissipation is the summation of
the dc power and ac power. This sum must be less than
the maximum package dissipation capability at the
particular operating temperature to insure safe operation,
i.e.:
typical performance characteristics
ICC
Transient Power vs Frequency
300
(VSS-VDD " 17Vj
~
~
'"
"50~PY
A'
200
/
100
/
'"
~
£.-
0
0
/
ISS
Duty Cvcle
8.0
......
'i'
~
"-....
0.7
'i'
~
Jl
....... ~
0.6
6.0
_I---'"
.lI
...........
--- -
91
4.0
2.0
0.5
0.8
Y5
10.0
CC JOPF-
/
0.4
Duty Cycle
0.8
/ ' ~l~
~
~
CC
YS
0.9
1.2
FREQUENCY IMH')
1.6
2.0
0
10
20
30
DUTY CYCLE (%j
40
50
0
10
20
30
40
50
DUTY CYCLE (%)
4·63
~.
Memory/Clock Drivers
NATIONAL
0575324 memory driver with decode inputs
general description
features,
The OS75324 is a monolithic memory driver
which features two 400 mA (source/sink) switch
pairs along with decoding capability from four
address lines. Inputs Band C function as mode
selection lines (source or sink) while lines A and
are used for switch·pair· selection (output ·pair
VIZ or W/X).
•
•
•
High voltage outputs
Dual sink/source outputs
Internal decoding and timing circuitry
•
•
•
400 mA output capability
OTLITTl compatible
Input clamping diodes
o
schematic and connection diagrams
r---.__.----------~.__.----------------~._------------O~
......
''''''
:~~::;:~...--_4.--~;:=:::;t::l~&U1PUTX
lSGURCEI
SUURCE
COLUCTGRS
~------------~-o:~:J
Dual-In-line Package
Dual·ln·Line Package
OUTPUT
Z
ISlMXI
AOORES$INI'uTS
Va;
OUTPUT
SOURCE
OUTPUT
OuT~UT
IsauYAtE)
~~~c.
ISO:RCF.)
15I:'CI
TIMlNGIIlf'UTS
GND 1 and GND 2 are to b,,,$8din parallel.
TO'VI£W
Order Number DS75324J
4·64
Order Number DS75324N
G~D
absolute maximum ratings
c
!!l
c.n
(Note 1) •
17V
W
5.5V
~
Supply Voltage Vee (Note 4)
Input Voltage (Note 5)
Operating Case Temperature Range
Power Dissipation
800mW
Storage Temperature Range
-1l5°C to +150°C
Lead Temperature (Soldering, 10 seconds)
300°C
dc electrical characteristics
(Vee = 14V, Te = O°C to +70°C unless otherwise noted) (Notes 2 and 3)
PARAMETER
V 1N (1)
N
O°C to +70°C
CONDITIONS
MIN
TYP
MAX
3.5
(Figure 1)
Input Voltage Required to Insure
UNITS
V
Logical "1" At Any Input
V,N(O)
(Figure 1)
Input Voltage Required to Insure
0.8
V
Logical "0" At Any Input
'INO)
'IN{OI
VSAT
Logical "'" Level Input Current
Logical "0" Level Input Current
Saturation Voltage
Y,N = 5V,
Address Input
200
(Figure 1)
Timing Input
100
Y'N = OV,
Address Input
(Figure 1)
Timing Input
Sink, ISINK - 420 mA, RL = 53n
(Figure 2)
Source,
IOFF
Output Reverse Current ("OFF" State)
Icc
Supply Current
ISOURCE ~
420 mA, RL -47.5n
Y'N = OV, (Figure 1)
All Sources and Sinks OFF, Y'N = OV, (Figure 3)
(Figure 4)
V,
-6
-12
I
mA
mA
0.75
0.85
0.75
0.86
V
125
200
IlA
V
12.5
15
mA
Either Sink Selected
30
40
mA
Either Source Selected
25
35
mA
-1.5
V
liN ~ -12 mA, T A = 25°C
I nput Clamp Voltage
IlA
IlA
i
ac switching characteristics
(Vee = 14V, T e ,=25°C)
PARAMETER
t,..1
CONDITIONS
Logical "1" Level
.MIN
Sink Output, RL = 53n,
Propagation Delay Time to
CL =20pF
(Figure 6)
Source Output, RL 1 = 53R
RL2 = 50on, (Figure 5)
tpdO
Sink Output, RL = 53n,
Propagation Delay Time to
Logical "0" Level
CL =20pF
(Figure 6)
Source Output, Ru = 53n,
RL2 = 500n, (Figure 5)
t.
Sink Storage Time
TYP
, MAX
UNITS
110
ns
90
ns
40
ns
50
n,
70
ns
Note 1: "Absolute Maximum Ratings" afe those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise ,pecililld minimax limits apply across the o"C to +70°C temperature range lor the Ds75324.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
Note 4: Voltage values are 'With respect to network ground terminal.
Note 5: Input signals must be zero or positive with respect to network ground terminal.
4·65
o:t
N
truth table
('i)
~
tn
C
INPUTS
OUTPUTS
ADDRESS
TIMING
A B C 0
E F G
W
a a 1 1
a 1 a 1
1 1 a a
1 a 1 a
1
1
1
X X X X
SINK
SOURCES
SINK
X
Y
Z
ON
OFF
OFF
OFF
OFF
OFF
OFF
1
1
1
OFF
1
1
1
OFF
ON
OFF
1
1
1
OFF
OFF
ON
OFF
a
X
x
a x
X a
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
X X X X X
X X X X X
ON
test circuits and switching time waveforms
rlMiNGjN;;rs --- --- - - - ,
E
',,9------
01 --"-'~-----O
I
I
14V
"
'5W
,"ON-INDUCTIVE) .
)-...t-----o 3V
FIGURE 3. ICC IAII Outputs "OFF"t
4,67
test circuits and switching time waveforms (can't),
l.6V
¢
..---------------...,
I TIMING INPUTS
I
v"
I
-------<0
~
14V
I
I
I
Note 1: GNO Aand B,apply+J.5Vto C 81ld 0,
and measure Icc (output W is on),
Note 2: GNO Band 0, apply +3.5V to A and C,
and measure ~cc (output Z is on).
3V
3.5V
Note J: GND A and C, apply +J.SV to Band 0,
and measure tcc (output X is on).
Note 4: GND C and D, apply +3.5V to A and B,
and measure Icc (output V is on).
SEE
NOTES
FIGURE 4. ICC (One Output "ON")
5V
FTiMiNG'iNPliTS----------,
I
Vee
9-------<0
t4V
I
I
I
}-.........~w.....-o
23V
'--I*"-013V
Note 1: The input waveform is supplied by a
}-+----1~.....p_-o OUTPUT X
5V
SEE
NOTE
2
}-+---1~""'P--O OUTPUT. V
f------
500ns---_-I
."
INPUT
ov----'I
o""UT~)X ORY
FIGURE 5. Source·Output Switching Times
4-68
generator with the following characteristics:
t, '" t, '" 10 ns, duty cycle:S; 1%, and lOUT"" 50ft
Note 2: When measuring delay times at output X,
apply +5V to input D, and GND A. When me!lSuring
delay times at output Y, apply +5V to input A,
and GND O.
Note J: CL includes probe and jig capacitance.
Note 4: Unless otherwise noted aU resistors are O.5W.
test circuits and switching time waveforms (con't)
rTiMiNGiNPijTs----------,
Y"9------
I
0
I
I
14V
R,
5311
OW
INON·INDUCTlVI;)
'--. .f--<>
13Y
Note 1: TIle input waveform issupplied by 11
generotorwiththefollowingchatatteristics:
t, "'It'" lDns,dutycytle:::; 1%, loUT '" 5D~:.
Note 2: When meRsuringdelBY times at output
W, applv +5V to mput 0, Bnd GNO A. When
meBsuringdelay time; at output Z,apply +5V
to input A, and GNO O.
".,
Note 3: CL includes probe and jig capacitance.
NOTE
}--i------IV
""1
(SEE
TEST
HilLEl
.IV
OPEN
' '1
OHN
(SEE
TEST
TABLE!
4.5'11
1k
L.!cel
_ _ _ _ GND
.J
Note1: Figures:) and 4 parameters must be measured using rmlse techniques. tw ~ 20D).Is, duty cycle s; 2%.
TEST TABLE
TEST TABLE
A
B
S1
W
X
C
D
S2
Y
Z
0.8V
4.SV
0.8V
GND
OPEN
O.BV
4.SV
O.BV
OPEN
4.SV
0.8V
0.8V
OPEN
GND
4,SV
O.BV
O.BV
RL
OPEN
RL
FIGURE 4. VIL and Sink VSAT
FIGURE 3. VIL and Source VSAT
5,SV
I'L
(SEE
TEST
TA8tE!
OPEN
r----- ,.
L'IICCl
GND
.J
6.5'11
(4.5'11 FDA
TESTING'll,)
TEST TABLES
APPLY V, = S.SV
MEASURE 'j,
APPLY V,
GROUND
APPLY S.SV
A
51
B. C. 52. D
51
B
A. B
51
C
52
52
C,D
A,SI, B
D
52
A, 51, B, C
APPL Y V,
= 2.4V
= O.4V,
MEASURE I'L
APPLY I,
= -10 rnA,
APPLY 5.SV
MEASURE V,
MEASURE I'H
C. S2. D
A
51
51, B,C,S2, D
A, B, C, 52, D
A. C, 52, D
A,SI, B, D
B
C
A, 51, C, 52, D
A, 51, B, S2, D
52
D
A, 51, B, C, S2
A,SI,B,C,D
FIGURE 5. VI, II, IIH, and IlL
4-73
&0
N
('I)
it)
de test eireuits(eon't)
Iii
C
.......
~
('I)
&0
&0
CIJ
C
OPEN
OPEN
FIGURE 6. ICClIOFF) and ICC2(OFF)
24V
OPEN
4.5'10-+--.;.;;......
'VI
-=
'Vl
~
(SEE
TEST
.~"
(SeE
TEST
TABLE)
L!'CCl
5.5'1
.J
5.5'1
TEST TABLE
TEST TABLE
C
0
S2
Y
Z
A
B
Sl
GND
5V
i(SINKI
OPEN
GND
5V
5V
GND
GND
GND
OPEN
i{SINK)
5V
GND
GND
GND
FIGURE 7. ICC1. Either Sink On
4·74
_ _ _ _ GND
FIGURE 8. ICC2. Either Source On
o
en
en
en
de test eireuits(eon't)
C/o)
N
en
.......
]50
o
OPEN
~
en
INPUT
C/o)
VOLTAGE WAVEFORMS
N
en
---......--....--f----l'""""'COllfCTORS
o,"------lf::::::'"
OUTPut
./-~---~~+-oOUTPUT v
C,
25 pF
"J"
./-+o,---....::.-+-<>our.. uT l
_ _ _ _ GNO
Note 1: The pulse generator has the following characteristics:
Nole 2: CL includes probe and jig capacitance.
"J"
..J
lOUT
c,
2~,F
= SOU, duty cycle S 1%.
TeST TABLE
OUTPUT UNDER TEST
PARAMETER
INPUT
CONNECT TO 5V
A and 51
B, C, 0 and S2
Band 51
A, C, 0 and S2
Sink output Y
C and S2
A,B,DandS1
Sink output Z
o and 52
A,B,CandS1
Source collectors
tPLH' and tPHL
tPLH. tPHL.
tTLH. tTHL,
and t5
FIGURE 9, Switching Times
20V
INPUT
VOL TAGE WAVEFORMS
.
R,
_ _ _ _GND
.J
,v
Notel: The puiS! generator has the followingcharatleristics:
Note 2: Cl includes probe ilnd ii!l capacitance.
ZOUT
"50!!, duty cycle S 1%.
TEST TABLE
CONNECT TO 5V
PARAMETER
OUTPUT UNDER TEST
INPUT
tTLH and tTHL
Source output W
Source output X
A and 51
B, C, D. and 52
Band 51
A, C. 0, and 52
FIGURE 10. Transition Times of Source Outputs
4·75
applications
External Resistor Calculation
A typical magnetic-memory word drive requiremel1t
is shown in Figure 11. A source-output transistor
of one OS75325 delivers load current (lL)' The
sink-output transistor of another OS75325 sinks
this current.
After solving for Rex" the magnitude of the source
collector current (lcs) ,is determined from Equation 3.
The value of the external pull-up resistor (Rex,)
for a particular. memory application may be determined using the following equation:
where:
16
Rex' ;
where:
[V CC2 (min)
VS
'L - 1.6 [V CC2 (min) Rex' is in
(3)
Ics "" 0.94 IL
Ics is in mAo
As an example, let V CC2 (min) ; 20V and V L
while I L of 500 mA flows. Using Equation 1:
;
3V
2.2J
(1)
16
Vs - 2.9J
Rex' ;
(20-3-2.2)
500 - 1.6 (20 - 3 - 2.9)
; 0.5
kn
kn,
and from Equation 2:
V CC2 (min) is the lowest expected value of
V CC2 in volts, V s is the source output volt-
500
PRex , ""
age in volts with respect to ground, I L is in
mAo
The power dissipated in resistor Rex< during the
load current pulse duration is calculated using
Equation 2.
IL
P Rex , '" 16
where:
(2)
[V CC2 (minl - Vs - 2J
P Rex , is in mW.
16
Ics '" 0.94 (500) '" 470 mA
In this example the regulated source-output transistor base current through the external pull-up
resistor (Rex,) and the source gate is approximately
30 mAo This current and Ics comprise ' L .
r---- R
I DS~~3E251
I D575325
SINK
r-----ON'
I 055&325/
OS15325
SOURCE
GNO
_ _ .J
Note1: For clarity, partialloyic diagrams of two DS55325's arl! shown.
-Note 2: Source and sink showililre in different pac:kages.
FIGURE 11. Typical Application Data
4-76
2J ""470mW
The amount of the memory system current source
(lcs) from Equation 3 is:
VCC2
I
[20 - 3
c
~
Memory/Clock Drivers
CJ)
-...I
U1
W
0)
-"
NAll0NAL
OS75361 dual TTL-to-MOS driver
general description
features
The DS75361 is a monolithic integrated dual TTL-toMOS driver interface circuit. The device accepts standard
TTL and DTL input signals and provides high-current
and high-voltage output levels for driving MOS circuits.
It is used to drive address, control, and timing inputs
for several types of MOS RAMs including the 1103 and
MM5270 and MM5280.
The DS75361 operates from standard TTL 5V suppl ies
and the MOS Vss supply in many applications. The
device has been optimized for operation with V CC2
supply voltage from 16V to 20V; however, it is designed
for use over a much wider range of V CC2'
•
Capable of driving high-capacitance loads
•
Compatible with many popular MOS RAMs
•
V CC2 supply voltage variable over wide range to 24V
•
Diode-clamped inputs
•
TTL and DTL compatible
•
Operates from standard bipolar and MOS supplies
•
High-speed switching
•
Transient overdrive minimizes power dissipation
•
Low standby power dissipation
connection diagrams
Dual~ln-Line
Vee1
"
Yl
Dual-In-Line Package
Package
V2
'2
GNo
Ne
Ne
.,
.2
TOP VIEW
TOP VIEW
Order Number DS75361N
Order Number DS75361J
Ne
GNo
4-77
absolute maximum ratings
Supply Voltage Range of VCCI (Note 11
Supply Voltage Range of VCC2
Input Voltage
Inter-Input Voltage (Note 41
Storage Temperature Range
operating conditions
(Note 1)
-0.5V to 7V
-O.5V to 25V
5.5V
5.5V
~5°C to +150°C
Lead Temperature 1/16 Inch from Case for
60 Seconds: J Package
Lead Temperature 1/16 Inch from Case for
10 Seconds: N or P Package
VIL
Low-Level Input Voltage
UNITS
5.25
24
V
V
Operating Temperature (T A)
0
V OH
High-Level Output Voltage
VIL = 0.8V. IOH = -50pA
VIL - 0.8V, IOH = lOrnA
VOL
Low-Level Output Voltage
V IH = 2V, IOL = 10 mA
V CC2 = 15V to 24V, V IH
IOL = 40 mA
Output Clamp Voltage
VI = OV, IOH
II
Input Current at Maximum Input Voltage
VI
IIH
High-Level Input Current
IlL
Low-Level Input Current
ICCllHI
Supply Current from V CC1, Both
Outputs High
ICC11L1
Supply Current from V CC1, Both
Outputs Low
ICC21 LI
Supply Current from V CC2 , Both
Outputs Low
Icc21S)
Supply Current from V ee2 ,
Stand· by Condition
switching characteristics
MAX
= 2.4V
VI = 0.4V
A Inputs
E Input
VI
V
-1.5
V
V
V
0.15
0.3
V
0.25
0.5
V
V cc2 +1.5
V.
= 20 rnA
A Inputs
E Input
0.8
V cc2 -1 V cc2 -O.7
V CC2 2.3 V CC2 1.8
2V,
1
mA
40
ao
pA
pA
-1.6
-3.2
mA
rnA
4
rnA
0.5
rnA
16
24
rnA
7
11
mA
0.5
rnA
TYP
MAX
UNITS
11
20
ns
-1
-2
2
V CC2 = 24V,
V CCl = 5.25V,
All I nputs at OV, No Load
V cc , = 5.25V,
V CC2 = 24V,
All Inputs at 5V, No Load
UNITS
V
= 5.5V
V eel = OV,
V Ce2 = 24V,
All Inputs at 5V, No Load
(V ecI = 5V, V CC2 = 20V, T A = 25°C)
PARAMETER
tOLH
TYP
'2
11=-12mA
Supply Current from V CC2, Both
Outputs High
MIN
CONDITIONS
Input Clamp Voltage
ICC21HI
°c
(Notes 2 and 3)
VI
Vo
+70
200°C
PARAMETER
High-Level Input Voltage
MAX
4.75
4.75
300°C
dc electrical characteristics
V IH
MIN
Supply Voltage (VCCI 1
Supply Voltage (VCC21
CONDITIONS
MIN
Delay Time, Low-to·High Level Output
tOHL
Delay Time, High·to-Low Level Output
tTLH
Transition Time, Low-to-High Level Output
tTHL
Transition Time, High-to-Low Level OutP4t
tpLH
Propagation Delay Time, Low·to·High Level Output
tpHL
Propagation Delay Time, High-to-Low Level Output
10
18
ns
25
40
ns
21
35
ns
10
36
55
ns
10
31
47
ns
CL = 390 pF,
R o = 10n
(Figure 1)
Note 1: ,. Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified min/max limits apply across the
andVCC1
oOe
to +700e range for the OS75361. All typical values are for ~A = 25 0e
= 5V and VCC2 = 20V.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
Note 4: This rating applies between the A input of either driver and the common E input.
4-78
typical performance characteristics
High·Level Output Voltage vs
Output CUrrent
Low-Level Output Voltage vs
Voltage Transfer Characteristics
Output Current
0.5
~
..:;'"
W
..'"~
W
0
> -1.0
5
~
0
Vee, :: 5V
~
-0.5
>
24
0.4
r VCC2 '" 20V
0.3
l-
=>
-1.5
~
VCC1 :: 5V
VCC2 :: 20V
v. = D.BV
"
;
+l+1lIIl-+l-lfHII-++IilHII
~
-3.0 Ll..UJ;UlIL.Ll.J1JjJIl--'-lillIlILU.JJ.lUlI
-0.01
-0.1
-1
-10
-100
~
0.2
0.1
1000
900
100
~
600
:<:
is
3:'"
~
~
I-
1,1.1,,,5.
35
~E
>1-
30
.. =>
g~
500
z>
.."'o~
~:i::
400
",
300
~6
or>:"
~"
g
200
100
!~
I-~
~~
w.c>W
2(;:
.. '"
30
25
20
~5j:
~o
~I-;-
o.~
15
10
80
-
~
X
g
~~
I-~
..--- i-""'"
~
>1.. =>
g~
40
~~
I-~
CL =20DpF
C~' 50lpf
>1e<=>
I-- I--
25
20
.!i~
",0
20V
RD '" 10n
~o
(FIGURE 1)
;;
..,.
VCC2 ::
f~
30
40
50
60
10
C: " 5J of
VCC1 '" 5V
VCC2 '" 20V
Ro'= lOn
10
BO
~~
",0
15
~o
10
..,.
01-
60
CL "'390PF.,V
...--t"" .J.
C~~
o
20
24
!~
50
~
~
~
M ro m
~~
~~
40
~~
30
.. 0;
20
VCC1 = 5V
VCC2 = 20V
TA =:25°C
I-~
(fiGURE 1)
C W
.."'-'"
/' . /f-""
/'
'j;::i:
~o
01-
g:~
g:~
;;
TA =25°C
(fiGURE 1)
W
10
Propagation Delay Time,
Low-to-High Level Output
vs Load Capacitance
~-]:
/'
I I
I I
(fiGURE 11
o
I--
AMBIENT TEMPERATURE ("C)
VCCl = 5V
35 ~RD=:10n
30 f- TA "25"C
(fiGURE 1)
25
=
c~ =20~ pF r-
15
o
20
CL
30
~~
OW
I 390I pF
35
z>
cw
v ee1 :: 5V
10
2.5
1.5
Propagation Delay Time,
High-to-low level Output
vs Ambient Temperature
w']
10
20
.
Ro '" 10n
lB
15°C
INPUT VOLTAGE (V)
15
,,>
OW
vee1 :: 5V
12
=
0.5
Propagation Delay Time,
High-to-Law Level Output
vs VCC2 Supply Voltage
w
CL =200pF
NO LOAD
100
40
CL =390pF
Vee1 :: 5V
VCC2 '" 20V
AMBIENT TEMPERATURE rC)
0.-
i=:i::
60
CL -390pF
20
Low·to-High level Output
vs VCC2 Supply Voltage
40
12
=>
40
25
Propagation Delay Time,
35
>
l-
Propagation Delay Time,
Low-to-High Level Output
vs Ambient Temperature
o
'"
"\
16
~
20
fREQUENCY (MH,)
-oS
'"
~"O°C
40
BOO
i=
.~
W
LOW·LEVEL OUTPUT CURRENT (rnA)
vs Frequency
2
0
20
~
TA
Total Dissipation (Both Drivers)
\0
A
~
'/
HIGH-lEVEL OUTPUT CURRENT (rnA)
.s
TA=W
VI:: 2V
10
0
o
12
SUPPL Y VOLTAGE (V)
16
20
24
0
100
2do
300
400
500
600
LOAD CAPACITANCE (Of)
SUPPLY VOLTAGE (V)
Propagation Delay Time,
High-to-Law Level Output
vs load Capacitance
60
11
~.~
50
1-1>=>
"0
40
2w
30
~g
0.-
VCC1
~~
"'''';;
~'"
5V
(fiGURE 11
RD;2~
RD"10n~
V
[::::
.6. G:; ~O
lIP"
~
~~
~g
=
VCC2 "" 20V
TA '" 2Soc
20
10
o
o
100
200
300
400
500
600
LOAO CAPACITANCE (of)
4-79
....
~
schematic diagram
(1/2 shown)
Lf)
~
C
Vee1
TO OTHER {
DRIVER
+-_______•
OUTPUT Y
INPUT A
ENABLE E
TO OTHER {
DRIVERS
GND
':"
ac test circuit and switching time waveforms
INPUT
5V
2DV
tj
rVCC1 VCC21
L
I
I
OUTPUT
--!-- .J
GND
2.4V
$11101;
3V---\---::l=,-----;;d
INPUT
DV
OUTPUT
Voc------"-A.-------"
Note 1: The pulse generator has the foUowingcharacteiistics: PRR = 1 MHz, louT"" son.
Note2: CL includes probe and jig capacitance.
FIGURE 1. Switching rimes, Each Driver
4-80
c
en
CiI
w
typical applications
The fast switching speeds of this device may produce
undesirable output transient overshoot because of load
or wiring inductance. A small series damping resistor
may be used to reduce or eliminate this output transient
1UV
5V
...
en
5V
16.1V
~,f- SILICON
DIODE
1
overshoot. The optimum value of the damping resister
to use depends on the specific load characteristics and
switching speed. A typical value would be between lOn
and 30n (Figure 3).
I
..... ,..,.,x=.L-..-,V".....,,-.y--+,....,OAV~T-:.,-.--~..".v~-.+--~:r'-cc.-~vcc....,~_}
~
E
i_- A., ""---.
Y
TTL (
DS75311
V ~ PRECHARG
~
0515361
TTL
INPUTS
12 PACKAGES}
i...-.-.IIo. CHIP
1113 RAM §
ISPACKAGES)
INPUTS
v r-- ENABLE
_
..... E
GND
Y
READ/wRI~;, ! A."""':- v GND E f'+-
r-----
=.:
I
L
Note: Ro ... 10n to lOn (Optionll).
FIGURE 3. Use of Oamping ROSistor to Roduce
or Eliminate Output Transient Overshoot in
Cortain 0575361 Applications
FIGURE 2. Interconnection of 0575361 Oevicelwith 1103 RAM
thermal information
POWER DISSIPATION PRECAUTIONS
Significant power may be dissipated in the Ds75361
driver When charging and discharging high-capacitance
loads over a wide voltage range at high frequencies.
The total dissipation curve shows the pdWer dissipated in
a typical DS75361 as a function of load capacitance and
frequency. Average power dissipated by this driver can
be broken into three componenU:
PT(AV) = POC(AV) + PC(AV) + PS(AV)
where POC(AV) is the steady-state power dissipation with
the output high or low, PC(AV) is the power level during
charging or discharging of the load capacitance, and
PS(AV) is the power dissipation during switching between
the low and high levels. None of these include energy
transferred to the load and all are averaged over a full
cycle.
neglected. The total dissipation curve for no load demonstrates this point. The power dissipation contributions
from both channels are then added together to obtain
total device power.
The following example illustrates this power calculation
technique. Assume both .channels are operating identically with C = 200 pF, f = 2 MHz, VCC1 = 5V, VCC2 =
20V, and duty cycle = 60% outputs high (tH/T = 0.6).
Also,assume VOH = 19.3V, VOL = O.lV, Ps is negligible,
and that the current from VCC2 is negligible when the
output is high.
On a per-channel basis using data sheet values:
POC(AV) = [(5V)
[(5V)
The power componenU per driver channel are:
PLtL +PHt H
POC(AV) =
T
e
;A) + (20V) (0 ;A))(O.6) +
C
6;A) + (20V)
C
;A))(0.4)
POC(AV) =·47 mW per channel
PC(AV) '" C VC2 f
PS(AV) =
PLHtLH+PHLtHL
T
PC(AV) '" (200 pF) (19.2V)2 (2 MHz)
where. the times are as defined in Figure 4.
PC(AV) '" 148 mW per channel.
PL, PH, P'LH, and PH L are the respective instantaneous
levels of power dissipation and C is load capacitance.
The OS75361 is so designed that Ps is a negligible portion of PT in most applications. Except at very high
frequencies, tL + tH »tLH + tHL so that Ps can be
For the total device dissipation of the two channels:
PT(AV) '" 2 (47 + 148)
PT(A V)
""
390 mW typical for total package.
FIGURE 4. Output Voltage Waveform
4-81
N
CD
.....CI)m
Q
~.
Memoryle.lock DriverS
NAlIONAL
0575362 dual TTL-to-M05 driver
general description
features.
The OS75362 is a dual monolithic integrated TTL-toMOS driver and interface circuit. that accepts standard
TTL and OTL input signals and provides high-current
and high-voltage output levels suitable for driving MOS
circuits. It is used to drive add~ess. control, and timing
inputs for several types of MOS RAMs including the
1103.
• Dual positive-Ic;lgic NAND TTL-to-MOS driver
• Versatile interface circuit for use 'betwe~n' TtL and
..
high'current, high-voltage systems'
• Cap.abie of driving high-capacitance loads
• ·Compatible with many popular MOSRAMs'
• VCC2 supply voltagl1 variable over wide range to 24V
maximum
.
.. VCC3 supply voltage .pin available
• VCC3 pin can be connected to VCC2 pin in some
applications'
,
• TTL and OTL compatible diode-clamped inputs
• Operatl!s fmm standard bipolar andMOS~'~ppIY
voltages
.
• High-speed switching
• Transient overdrive minimizes power dissipation
• Low standby power dissipation
The OS75362 operates from the TTL 5V' supply and the
MOS Vss and Vee supplies in many applications. This
device has been optimized for operation with VCC2
supply voltage from 16V to 20V, and with nominal
VCC3 supply voltage from 3V to 4V higher than VCC2 '
However; it is designed so as to be usable over a much
wider range of VCC2 and VCC3 ' In some applications the
VCC3 power supply can be eliminated by connl!cting the
VCC3 pin to the VCC2 pin.
schematic and connection diagrams
Dual-In-Line Package
Veet
Vee,
VI
,V2
V0C2'
v...
+ ___..
TO OTHER {""-_ _ _ _ _ _
DRIVERS ~
INPUTA
o-----........HH
AI
...H~.+-o<) ~UTPUT
~
Order
YCC3
TOPVI£W
Numb~r
DS75362N
Dual-In-Line Package
TO OTHER
DRIVERS
Vee,
Ne
-.'Vl
Ne
Ne
AI
Ne
Y2
VCC3
A2
.-----~~-~---~----_6-_oGND
TOP VIEW
Order Number DS75362J
4-82
Nt
•• 0
absolute maximum ratings
-0.5V to 7V
-0.5V to :!5V
-0.5V to 30V
5.5V
5.5V
_65°C to 150°C
300°C
Supply Voltage Range of VCC1
Supply Voltage Range of VCC2
Supply Voltage Range of V CC3
Input Voltage
I nter·1nput Voltage (Note 4)
Storage Temperature Range
Lead Temperature (Soldering 10 seconds)
electrical characteristics
V'H
V'L
Low·Level Input Voltage
Supply Voltage (VCC1)
Supply Voltage (VCC2)
Supply Voltage (V CC3)
MIN
4.75
4.75
VCC2
MAX
5.25
24
28
UNITS
V
V
V
Voltage Difference Between
0
10
V
0
70
°c
Supply Voltages: VCC3-VCC2
Operating Ambient Temperature
Range (TA)
(Notes 2 and 3)
CONDITIONS
PARAMETER
High·Level Input Voltage
o
operating conditions
(Note 1)
MIN
TVP
MAX
UNITS
V
2
O.B
V
-1.5
V
V,
Input Clamp Voltage
1,=-12mA
V OH
High·Level Output Voltage
VCC3 = V cc2 +3V, V'L = O.BV, 10H = -100f.lA
V cc2 -O.3 V cc2 -O.1
V
VCC3 = V cc2 +3V, V'L = O.BV, 10H = -10 mA
Vcc2-1.2 V cc2 -O.9
V
V cc2 -1
V
VCC3
VCC3
Low·Level Output Voltage
VOL
= V CC2 ' V'L = 0.8V,
= V CC2 , V'L = 0.8V,
= 2V, 10L = 10 mA
VCC3 = 15V to 28V, V'H
Output Clamp Voltage
V,
= OV,
I,
Input Current at Maximum
I nput Voltage
V,
= 5.5V
I'H
High·Levellnput Current
V,
= 2.4V
I'L
Low·Level Input Current
V,=O.4V
Icc1(H)
Supply Current from V cc"
All Outputs High
ICC2(H!
Supply Current from V CC2 ,
All Outputs High
ICC3(H!
Supply Current from V CC3 ,
All Outputs High
ICS',L!
Supply Current from V CC1.
All Outputs Low
ICC2IL!
Supply Current from V CC2,
All Outputs Low
Supply Current from V CC3,
All Outputs Low
ICC2IH!
Supply Current from V CC2 ,
All Outputs High
ICC3IH!
Supply Current from V CC3,
All Outputs High
Icc2ls!
Supply Current from V CC2,
Stand-by Condition
Supply Current from V CC3,
Stand·by Condition
ICC3IS)
Note 1:
II
10H
= -5O/.tA
= -10 mA
V'H
Vo
ICC31L1
10H
10H
= 2V,I oL
= 40 mA
Vcc2-0.7
0.15
0.3
V
0.25
0.5
V
V cc2 +1.5
V
= 20 mA
1
-1
2
V cc , = 5.25V, V CC2 = 24V,
VCC3 = 28V, All Inputs at OV, No Load
V cc ,
V CC3
= 5.25V, V CC2 = 24V,
= 28V, All I nputs at 5V, No
-1.1
1.1
= 5.25V, V CC2 = 24V,
= 24V, All Inputs at OV, No
mA
40
f.lA
-1.6
mA
4
mA
+0.25
1.6
mA
mA
1.1
1.8
mA
15
23.5
mA
1.5
mA
12.5
mA
Load
8
V cc ,
VCC3
V
V cc2 -2.3 V cc2 -1.8
0.25
mA
0.5
mA
0.25
mA
0.5
mA
Load
V cc , = OV, V CC2 = 24V,
VCC3 = 24V, All Inputs at 5V, No Load
Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the O°C to +70°C range for the 0$75362. All typical values are for T A = 25°C
and VCCl = 5V and VCC2 = 20V and VCC3 = 24V.
Nota 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
Note 4: This rating applies between any two inputs of anyone of the gates.
4·83
~
U1
W
0')
N
switching characteristics
(V CC1 = 5V, V CC2 = 20V, VCC3 = 24V, TA = 25°C)
CONDITIONS
PARAMETER
MIN
TYP
MAX
11
20
10
18
ns
20
33
ns
20
33
ns
31
48
ns
46
ns
tOLH
Delay Time, Low-to-High Level Output
tOHl.
Delay Time, High-to-Low
tTLH
Transition Time, Low-to-High Level Output
C L = 200 pF,
Ro = 24>2,
tTHL
Transition Time, High-to-Low Level Output
(Figure 1)
tpLH
Propagation Delay Time, Low-to-High Level Output
10
tpHL
Propagation Delay Time, High-to-Low Level Output
10
30
Lev~1
Output
UNITS
ns
ac test circuit and switching time waveforms
<;10n5_
INPUT
I
5V
24V
lOV
rvL7V!;vL71
'UlSE.
GENERATOR
I
I
I
INOTE 11
I
I
L
GND
--:1::-
.J
V
INPUT
...
I
I'
JV
'V~
7
-S1Dns
90%_\
90%
1.5V
1.5V
-'.s..- \
-t'H'-
'-L,OUT.UT
-
t[»jl.-
C,
I1NoTE21
r-tTHl
VOH
10%
-t"H-
VCC2
tOl,H--
2V\
OUTPUT
!-tTLI-.j
~V
2V
Yo,
Nota I: The pulse generator has the following characteristics: PHR '" 1 MHz, ZOUT
Notel: CL includes probe and jig capacitance.
'"
2V
SOH.
FIGURE 1. Switching Time., Each Driver
typical performanc'e characteristics
High-level Output Voltage VI
Output Current
High·level Output Voltage vs
Output Current
....
0
~
w
'"!::;'"
,."
...
~
-0.5
III
-..1.!
~
+10°C
TA~
-1.0
-1.5
" -Z.O
1:;
± -Z.5
:c'"
-3.0
~
w
VCC1 - SV
VCC2 '" 20V
Vec3 :; 24V
VI =O.8V
"...'"~,.
...=>
-0.1
-1.5
"
w
-Z.O
~
-Z.5
:c
-I
-10
-100
~
w
--.
~
-1.0
~
~
HIGH-LEVEL OUTPUT CURRENT {mAl
4-84
w -0.5
~
-0.01
0.5
0
~ll
A"
low-level Output Voltage
Output Current
'"'"
!::;
TA :;; +Z5°C
TA"'+70<>C~
Veel '"'5V
1111
VCC2oVCC30Z0VI
VI:;: O.8V
-3.0
-0.01
-0.1
-I
1I111
-10
0.3
~
O.Z
~
w
1:;
'i'ii"OC"
~
I
-100
HIGH-LEVEL OUTPUT CURRENT ImAI
'"
20V
VCC3 '" 24V
ITAo+~ ~
VI =ZV
,."
5
VCC1 '" 5V
VCC2
0.4
0.1
0
~
~=O°C
l/
20
,
40
60
80
LOW-lEVEL OUTPUT CURRENT {mAl
100
c
~
en
w
en
typical performance characteristics (can't)
Voltage
Tr~nsfer
Characteristics
vs Frequency
24 .--.,......-.,--,--.,.---,
W
"'"~
"15
16
>
~
~~:: ::v-f--lt--+---l
~
I 11111111 I
350
>=
300
iliQ
250
r- c, 1= 1!0 ~J
f--c~ '" 50 ~F'
I~
200
...
Vee3 = 24V "-f--tf--'-+---I
TA,=2S"C -
150
Veel
100
2.5
5V
V~,·24V
~~~:;~~ SQiAii
o
1.5
~
0.1
0.2
Propagation Delay Time,
High-to-Low Level Output vs
Ambient Temperature '
...
g~
... L
~!;
~~
zi::
C~
CW
~~
".
"'~
LC
C ...
L",
;::~
30
w~
zi::
20
>==
15
LO
10
C~
Ni [oil
"'"
~5j:
III
c ...
.Lt.!!.
40
im' '50. JUTi '1'ii'
7 10
.
C,=200pF
w ...
30
",
;::==
25
>'"
"c
Ic, -~o.J
20
~uj
c>
zw
35
30 I--25
10
Vee1
==
5V
VCC2
==
20V
"
10
20
30
40
50
&0
-
H'bl~
I'
.]
!~
S~
w~
20
15
vee,
LC
C ...
10
I
OW
I
12,
60
w";:
50
>'"
"c
~~
40
i=1=
"''''
Ww
c>
zw
Vee1 '" 5V
VCC2 = 20V
~~
~~
20
lf~
10
O'
."
~
50 100 150 201l 250 300 350 400
LOAD CAPACITANCE (.F)
70
BO
20
>=;:
15
~~
",=
10
./
I'
.,- ~
12
24
-
----
-C,-~
= 100pFI I
Vee1 ;; 5V
VCC3 = VCC2 + 4V
Ro =24U'
TA =25°~
(FIGURE 1)
16
20
24
Propagation Dalay Time,
High-to-Low Laval Output vs
load Capacitance
.. '"
w ...
~
60
SUPPLY VOLTAGE (VI
.]
I--' :::::
~~~~=O
30 t-- Ro = IOU
c~
LC
C ...
l l
50
CL=200~
"
20
60
VCC3" 24V
TA=25°C
~
(F,GURE,U t--Ro = ~
40
L",
Propagation Delay Time,
Low-to-High Leval Output vs
Load Capacitance
'2
311
25
O~
=
16
30
SUPPL Y VOLTAGE (V)
AMBIENT TEMPERATURE (OC)
20
35
zi::
"c
"'~
='SV .
VCC3 VCC2 + 4V
HD = 25H
TA"'ZS"C
(FIGURE 1)
70 BO
VCC3 = 24V
Ro '" 2412
(FIGURE 1)
Propagation Delay Time,
High-to-Low Laval Output vs
VCC2 Supply Voltage
>==
g:~
RD '" 24n
(FIGURE 1)
Vee1 '" 5V
AMBIENT TEMPERATURE (OC)
CL =100pF-
"'"
~:;;:
VCC3 = 24V
"''''
~ 50 ~F
40
c~
15
C,
VCC2 '" ZOV
10
40
.]
- -
f~
Propagation Delay Time,
Low-to-High Laval Output vs
VCC2 Supply Voltage
35
C,=200pF
25
C W
0.4 0.7 1
FREnUENCY (MHz)
INPUT VOLTAGE (VI
35
S~
~I
IV
Vc;cz=26V
50
NO LOAD
0.5
If
~
:0C
"i
.....
"'-
I
1 1c, = 200 pF!
400
oS
:::
12
C
40
500
450
20
?;
N
Propagation Delay Time,
Low-to-High Laval Output vs
Ambient Temperature
Total Dissipation (Two Drivers)
i=~
50
>'"
"c
Ww
40
;zw
30
~~
Q>
C!~
r-
>=5:
"c
20
L'"
10
"'~
~~
",=
"
Vcc, - 5V
VCC2 ::; 20V
VCC3 ';" 24V
TA ::; 2Soc
(FIGURE"U r I
Ro = lOu
0,
:~ ~
~ ~ P'"
~
RD =0
60 100 150 200 250 300 350 400
LOAD CAPACITANCE (pF)
4-85
typical applications
The {ast switching speeds of this device may produce
undesirable output transient overshoot because of load
or wiring inductance. A small series damping resistor
may be used to reduce or eliminate this output transient
overshoot. The' optimum value of the damping resistor
depends on the specific load characteristics and switching
speed. A typical value would be between Ion and 30n
tHL-
1------1" 1!f---~-I
(Fig(Jre 2).
FIGURE 3. Output Voltage Waveform
PL, PH, PLH, and PHL are the respective instantaneous
levels of power dissipation and C is load capacitance.
The DS75362 is so designed that Ps is a negligible portion of PT in most applications. Except at very high
tLH + tHL so that Ps can be
frequencies, tL + tH
neglected. The total dissipation curve for no load
demonstrates this point. The power dissipation contributions from two channels are then added together
to obtain total device power.
»
Note; RD '" lOU 10 30u (Optional).
FIGURE 2. Use of Damping Resistor to Reduce or
Eliminate Output Transient Overshoot In Certain
OS75362 Applications.
The following example illustrates this power calculation
technique. Assume two channels are operating iden.tically with C = 100 pF, f = 2 MHz, VCC1 = 51i, VCC2 =
20V, Vcc:i = 24V and duty cycle = 60% outputs high
(tHiT = 0.6). Also, assume VOH = 20V, VOL = 0.1 V,
Ps is negligible, and that the current from VCC2 is
negligible when the output is low.
thermal information
On a per-channel basis using
~ata
sheet values:
POWER DISSIPATION PRECAUTIONS
Significant power may be dissipated in the DS75362
driver when charging and discharging high-capacitance
loads over a wide voltage range at high frequencies.
The total dissipation curve shows the power dissipated in
a typical DS75362 as a function of load capacitance and
frequency. Average power dissipation by this driver
can be broken into three components:
PT(AV) = POC(AV) + PC(AV) + PS(AV)
where POC(AV) is the steady-state power dissipation with
the output high or low, PC(AV) is the power level during
charging or discharging of the load capacitance, and
PS(AV) is the power dissipation during switching between
the low and high levels. None of these include energy
transferred to the load and all are averaged over a full
cycle.
(20V) (0 ;A) + (24V)
t
6 4mA )] (0.4)
POC(AV) = 58 mW per channel
PC(AV) ""(100 pF) (19.9V)2 (2 MHz)
The power components per driver channel are:
PC(AV) "" 79 mWper channel.
PLtL +PHt H
POC(AV) =
T
PC(AV) "" C Vc 2f
P
_ PLHtLH+PHLtHL.
S(AV) T
'where the times are as defined in Figure 3.
4-86
For the total device dissipation of the two channels
PT(AV) "" 2 (58 + 79)
PT(AV) "" 274 mW typical for total package.
~
Memory/Clock Drivers
NAll0NAL
0575364 dual MOS clock driver
general description
The OS75364 is a dual MOS driver and interface circuit
that operates with either current source or voltage
source input signals. The device accepts signals from
TTL levels or other logic systems and provides high
current and high voltage output levels suitable for
driving MOS circuits. It may be used to drive address,
control and/or tim ing inputs for several types of MOS
RAMs and MOS shift registers.
The OS75364 operates from standard MOS and bipolar
supplies, and has been optimized for operation with V CC1
supply voltage from 12-20V positive with respect to
VEE, and with nominal V CC2 supply voltage from 3-4V
more positive than V CC1 ' However, it is designed so as to
be useable over a much wider range of V CC1 and VCC2'
In some applications the V CC2 power supply can be
eliminated by connecting the V CC2 pin to the V CC1 pin.
shifting may be done with an external PNP transistor current source or by use of capacitive coupling and
appropriate input voltage pulse characteristics.
The OS75364 is characterized for operation over the
O°C to +70°C temperature range.
features
•
•
•
•
•
Inputs of the OS75364 are referenced to the VEE ter·
minal and contain a series current limiting resistor. The
device will operate with either positive input current sig·
nals or input voltage signals which are positive with res·
pect to VEE' In many applications the VEE terminal is
connected to the MOS V DD supply of -12V to -15V
with the inputs to be driven from TTL levels or other
positive voltage levels. The required negative level
•
•
•
•
•
Versatile interface circuit for use between TTL levels
and level shifted high current, high voltage systems
Inputs may be level shifted by use of a current source
or capacitive coupling or driven directly by a voltage
source
Capable of driving high capacitance loads
Compatible with many popular MOS RAMs and MOS
shift registers
VCC1 supply voltage variable over wide range to 22V
maximum with respect to VEE
V CC2 pull-up supply voltage pin available
Operates from standard bipolar and/or MOS supply
voltages
High-speed switching
Transient overdrive minimizes power dissipation
Low standby power dissipation
connection diagrams
Dual-in-Line Package
Dual-I n-Line Package
NC
VI
NC
AI
TOP VIEW
TOP VIEW
Order Number DS75364N
Order Number DS75364J
NC
4-87
absolute maximum ra,tings
Supply Voltage Range of VCCl
Supply Voltage Ran~e of VCC2
Input Voltage
Tempera~ure
--65°C to +150°C
300°C
(Soldering, 10 seconds)
electrical characteristics
PARAMETER
V
V
Voltage Difference Between
Supply Voltages
Input Voltage
0
10
V
Temperature (T A)
0
Voltage Mode Input Logic Levels
V1L
Low Level Input Voltage
Voltage Mode Input Logic Levels
I'H
High Level lnpyt Current
Current Mode Input Logic Levels
I'L
low Level Input Current
Current Mode Input Logic Levels
V OH
High Level Output Voltage
V CC2
""
V CC1
(Note 41
V CC2. = V CC1 '
(Note 41
+ 3V.
10H = -100j./A
IOH
=
-10 rnA
10H = -50j./A
10H "-10 rnA
IOL
VCC2
= 10 mA
°c
70
,
MIN
CONDITIONS
High Level Input Voltage
Low Level Output Voltage
VCCl
22
28
(Notes 2, 3, 4 and 5)
V'H
VOL
MAX
4.75
VCCl
VCC2
~.
at
UNIT
MIN
Supply Voltage
-o.5V to 22V
-o.5V to 30V
15V
0.5V
Most positive Voltage Any Input
with Respect to VCC2
Storage Temperature Range
Lead
operating conditions
(N,?te 1)
TVP
MAX
10
5
1
8
UNITS
V
V
15
rnA
0.7
rnA
V
V'L = 1V
Vcc2-0·3
Vcc2-0·1
I'L = 0.7 mA
V cc2-0·3
Vcc2-0·1
V
V'L = 1V
V cc2 -1.2
V cc2-o·9
V
I'L "0.7mA
V cc2 -1.2
V cc2-0·9
V cc2 -1
Vcc2-0·7
V cc2-0·7
V cc2-1.8
V cc2-1.8
V
V
V'L = 1V
I'L - 0.7 rnA
V cc2-1
V'L = lV
V cc2-2.3
I'L "Q,7rnA
V cc2 -2.3
V
V
V
V'H "5V
0.15
0.3
V
I'H = 8 mA
0.15
0.3
V
V CC2 " 15 to 28V, V'H = 5V
0.25
0.5
V
10L =40 rnA
0.25
0.5
I'H "8mA
V cc1 +1.5
Va
Output Clamp Voltage
V, " OV, 10H " 20 mA
I,
Input Current at Maximum
V CC2 " 10V to 28V. V," 10V
17
26
V CC2 = 13.5V to 28V, I, = 15 mA
9
13.5
V
V
mA
Input Voltage
V,
I nput Voltage at Maximum
V
I~put Current
I'H
High'Level Input, Current
V," 5V
7
11
V'H
High Level Input Voltage
1,= 8mA
5.5
8
I'L
Low Level Input Current
V," 1V
1.1
1.6
V'L
L~w Lev~1
ICC1 (H)
Supply Current From V,CC1'
Both Outputs High
80th Inputs at OV, No "Load
ICC2 (H}
~upply
V CC, = 22V. V CC2 = 26V.
80th Outputs High
80th I nputs at OV, No Load
iCC1 (L)
Supply Current From V CC1 ,
V Ce1 e nv, V CC2 " 28V,
~oth
Both Inputs at 7V, No Load
ICC2 (U
'CC1(Hl
ICC2 (H)
Input Voltage
Current From V CC2 ,
Outputs Low
1,=0.7mA
V cc , = 22V, V CC2 = 26V,
Supply Current From V CC2 ,
V cc , " 22V. V CC2 " 28V,
80th Outputs Low
Both Inputs at 7V. No Load
Supply Current From V CC1,
V CC, " 22V. V CC2 " 22V.
80th Outputs High
Both Inputs at OV, No Load
Supply Current From V CC2 .
V cc , "nV, V CC2 =22V,
Both Outputs High
~oth
0.7
-1.1
1
-1·6
rnA
V
mA
V
mA
0.25
mA
1.1
2
mA
0.5
1
mA
8
14
mA
0.25
mA
0.5
mA
Inputs at OV, No Load
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they ,are not meant to imply that the devices should be operated at these limits; The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified min/max limits apply across the O°C to +70°C range for the OS75364. All typical values are for TA = 25°C,
VCC1" 20V, VCC2 = 24V and VEE = OV.
Note 3: All currents lnto device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
Note 4: Many of these parameters are specified independently for either voltage source or current source external forcing functions at the inputs.
Use the appropriate set of specifications for each application.
Note 5: All parameters are specified with VEE::: OV and for input voltage no more positive than "CC2.
I
4·88
switching ch aracte ristics
c
PARAMETER
MIN
CONDITIONS
TVP
MAX
UNITS
C L = 390 pF, Ro = 1(){l,
V CC2 = 24V
13
Level Output
(Figure 1)
V CC2 =·20V
14
ns
tOHL
Delay Time, High-to-Low
Level Output
C L = 390 pF, Ro = 100,
(Figure 1)
VCC2= 24V
9
VCC2 = 20V
10
ns
ns
tTLH
Transition Time, Low-ta-High
Level Output
C L = 390 pF, Ro = lOn,
(Figure 1)
V cc2 =24V
21
V CC2 = 20V
21
Transition Time, High-ta-Low
Level Output
CL = 390 pF, Ro = lOn,
V ec2 = 24V
19
(Figure 1)
V CC2 = 20V
18
Propagation Delay Time,
Low-ta.High Level Output
C L = 390 pF, Ro = 100,
V cc2 =24V
34
(Figure 1)
V CC2 = 20V
35
Propagation Delay Time,
C L = 390 pF, Ro = lOn,
V CC2 = 24V
28
High-to-Low Level Output
(Figure 1)
V CC2 = 20V
28
tTHL.
tpLH
tpHL
schematic diagram
m
.,...
ns
Delay Time, Low-to-High
tOLH
~W
V CC1 = 20V, Vee = OV, TA = 25°C
ns
ns
ns
ns
ns
ns
ns
ns
(1/2 shown)
vcc,
INPUT
~
J
~
r
vco,
.....
....
~
'-II
~
OUTPUT
*
I
L--~~---""--~VEE
ac test circuit and switching time waveforms
,;5NS-
I"
$ 5NS
!.:rr.
INPUT
I
I!LV
18%\
3V
3V
--l!!l!..V l---o....-I\"""'OII;...___ oV
IOV
VCC2
I
I
J
....L-
I
PULSE
RD
GENERATOR H~--I ;:1Qoo-J\I\,.,.....- OUTPUT
PRR"MH,
ZouT '" 58
CL (INCLUDES PROBE AND
L V'-'.J
JIG CAPACITANCE)
INPUT
I-I-
I
I--....~-
I- ....L-
rv~-t..,
T":,
OUTPUT
(Veez .. Vee,)
":'
Vco,
-3V
-l
1I-'THL
r\
toLH-
2V
I-'THL
2V
VOL
- ~VOH
I--t-rLH
'DHL-1--t-2V
VCC~\
V'~VDH
i-3V
-tpLH-
I-"HL-
OUTPUT .
IVCC2 .. VCC1 +4V)
I-'TLH
toLH-
I-
-2V
2V
VOL
FIGURE 1, Switching Tim••, Each Driver
4-89
:
typical applications
t")
It)
Iii
e
+5V
+IV
Vee1
v'"
CLOCK1
m(
MOSRAM
INPUT:S
CLOCK 2
GNo
VDD
V"
,
-
-15V
FIGURE 2. M05 RAM Clock Driver System with pl\lp Ttaosistor Current
Source used to Level-5hift to Inputs of DS75364
+BV
+5V
V,.
CLOCK 1
MOSSHIFT
R~~I~ER
CLOCK2
GNo
v"
VGG
-12V
FIGURE 3. M05 Shift Register Clock Driver System with Capacitive
Coupling used to Level-:Shift to Inputs of 0575364
application hints
Applications of the OS75364 used as an interface device
in systems converting TTL signals to negative polarity
MOS clock signals are shown in Figures 2 and 3. In both
applications the OS75364 Vee ,pin is connected to a
negative MOS supply voltage. The VCC2 supply pin may
be, connected to the V CCI pin as"s!lOwn in Figure 3 or
connected to a separate voltage more-positive than V CCI
as shown in Figure 2. The OS75364 m,ay be used over a
wide range of VCCI and VCC2 supply voltages which are
, positive with respect to Vee. However, for proper operation the voltage at the inputs of the OS75364 should not
be more positive than the voltage at VCC2 '
Both applications shown require negative level shifting
from positive voltage levels to the inputs' of the
OS75364 which are referenced to the Vee term'inal. A
PNP transistor' current source is used to level shift in
r--,
Figure 2. Resistor R sets the current and an open-
collector TTL gate is used to switch the PNP transistor:
Figure' j shows capacitive' coupling befng us~d to level
shift with the OS75361 TTL-to-MOS driver used as a
low impedance voltage source driver. The value of
coupling capacitor C depends on ,the frequency and
characteristics of the signal applied to the capacitor.
The fast switching of the OS75364 may produce undesirable output transient overshoot because of load or
wiring inductance. A small series damping resistor may
be used to reduce or eliminate this output transient overshoot. The optimum value of the damping resistor depends on the ,specific. load characteristics and, switching
speed. A typical vallie would be between 10 and 30
ohms (Figure4).
r;,;;;;-,
~I
I
I . I Teel
oS153&4
I
I
I
I
L_.J
L::.J
Note: Ro'" ton to 3Dn
(OJItionll).
FIGURE 4. Use of Damping Resistor to Reduco or Eliminate Output
Transient Overshoot in Certain DS75364 Applications
4·90
o
~
Memory/Clock Drivers
U'I
OS75365 quad TTL-to-MOS driver
general description
The DS75365 is a quad monolithic integrated TTL-toMOS driver and interface circuit that accepts standard
TTL and DTL input signals and provides high-current
and high-voltage output levels suitable for driving MOS
circuits. It is used to drive address, control, and timing
inputs for several types of MOS RAMs including the
1103.
• Capable of driving high-capacitance loads
The DS75365 operates from the TTL 5V supply and the
MOS Vss and Vee supplies in many applications. This
device has been optimized for operation with VCC2
supply voltage from 16V to 20V, and with nominal
VCC3 supply voltage from 3V to 4V higher than VCC2 '
However, it is designed so as to be usable over a much
wider range of VCC2 and VCC3 ' In some applications the
VCC3 power supply can be eliminated by connecting the
VCC3 pin to the VCC2 pin.
• VCC3 supply voltage pin available
• Compatible with many popular MOS RAMs
• Interchangeable with Intel 3207
• VCC2 supply voltage variable over wide range to 24 V
maximum
• VCC3 pin can be connected to VCC2 pin in some
appl ications
• TTL and DTL compatible diode·clamped inputs
• Operates from standard bipolar and MOS supply
voltages
• Two common enable inputs per gate-pair
features
•
High·speed switching
• Quad positive·logic NAND TTL-to·MOS driver
• Transient overdrive minimizes power dissipation
• Versatile interface circuit for use between TTL and
high-current, high-voltage systems
•
Low standby power dissipation
schematic and connection diagrams
Dual-in-Line Package
{+-------I------1
2EZ
....
2E1
4 ......--1
I.PUT A 0 - - - - -...
AJ
VJ
VCCl
A2
V2
GND
12
"
ENABLE E1
"""
U'I
Co)
0')
NAll0NAL
TO
OTHER
DRIVERS
en
........t-<--...H ......-O ~UTPUT
0 - - -....-+-+-11-.
-+-+-1<1......
ENABLE E2 0--<11......
VI
AI
lEI
1E2
TOP VIEW
TO OTHER {
DRIVERS
Positive logic: V = A',El'E~
~~~~
__------__
--------~--~G.O
Order Number DS75365J
or DS75365N
ONE OF 4 SHOWN
4-91
absolute maximum ratipgs
operating conditions
(Note 1)
'."
Supply Voltage Range of VCCl
Supply Voltage Range of VCC2
Supply Voltage Range of V CC3
Input Voltage
Inter-Input Voltage (Not. 4)
Storage Temperature Range
Lead Temperature (Soldering 10 seconds)
-0.5V to 7V
-0.5V to 25V
-0.5V t030V
5.5V
5.5V
-65°C to 150°C
300°C
electrical characteristics
V'H
V'L
Low-Level Input Voltage
V,
Input Clamp Voltage
V OH
VOL
High·Level Output Voltage
Low·Level Output Voltage
MIN
4.75
4.75
VCC2
Voltage Difference Between
0
10
V
0
70
°c
Operating Ambient- Temperature
Range (TA)
CONDITIONS
MIN
-1.5
V
VCC3 = Vcc2 +3V. V'L = O.BV. IOH = -10 mA
V cc2 -O.3 V cc2 -O.1
V cc2 -1.2 Vcc2~0.9
VCC3 = VCC2 • V'L = O.BV. IOH = -50/lA
V cc2 -1
V cc2 -O.7
V
VCC3 = V CC2 • V'L = O.BV, IOH = -10 mA
V cc2 -2.3 V cc2 -1.B
VCC3 = Vcc2 +3V. V'L = O.BV. IOH = -100/lA
V'H = 2V, IOL = 10 mA
Input Current at Maximum
Input Voltage
V, = 5.5V
"H
High·Level Input Current
Supply Current from V CC2.
All Outputs High
V
V
I,
ICC2(HI
UNITS
V
1,=-12mA
Vo
Supply Current from V cc"
All Outputs High
MAX
O.B
V, =OV, IOH = 20mA
' CC 1(HI
TYP
2
Output Clamp Voltage
"L
UNITS
V
V
V
Supply Voltages: VCC3-VCC2
. VCC3 = 15Vto2BV. V'H =2V, IOL.=40mA
Low·Level Input Current
M.AX.
5.25
24
28
(Notes 2 and 3)
PARAMETER
High-Level Input Voltage
Supply Voltage (V CCl )
Supply Voltage (VCC2)
Supply Voltage (VCC3)
V, = 2AV
V,=O.4V
V
V
0.15
0.3
V
0.25
0.5
V
V cc2 +1.5
V
1
mA
A Inputs
40
/lA
Eland E2 Inputs
80
/lA
A Inputs
-1
-1.6
mA
Eland E2 Inputs
-2
-3.2
mA
8
mA
4
-2.2
V cc , = 5.25V, V CC2 = 24V,
V CC3 = 28V, All Inputs at OV, No Load
-2.2
+0.25
-3.2
mA
mA
' CC3(HI
Supply Current from V CC3,
All Outputs High
2.2
3.5
mA
ICC1(LI
Supply Current from V cc,.
All Outputs Low
31
47
mA
' CC2 (LI
Supply Current from V CC2'
All Outputs Low
3
mA
ICC3(LI
Supply Current from V CC3.
All Outputs Low
25
mA
ICC2(HI
Supply Current from V ee2 ,
All Outputs High
0.25
mA
0.5
mA
0.25
mA
0.5
mA
' CC3 (HI
Supply Current from V ec3 ,
All Outputs Hig~
' CC2 (SI
Supply Current from V ec2 •
Stand·by Condition
' CC3 (SI
Supply Current from V CC3,
Stand· by Condition
V cc , = 5.25V. V CC2 = 24V,
VCC3 = 28V, All Inputs at 5V. No Load
16
V ce , = 5.25V, V CC2 = 24V,
V ec3 " 24V, All Inputs at OV. No Load
Vce; = OV, V CC2 = 24V,
Vec3 '" 24V, All Inputs at 5V. No Load
...
Note 1: "Absolute Maxj'mum Ratings" are those values beyond which the safety of the device cannot be' guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified min/max limits apply across the O°C to +70°c range for the OS75365. All typical values are for TA = 25°C
and VCCI = 5V and VCC2 = 20V and VCC3 = 24V.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
Note 4: This rating applies between any two inputs of anyone of the gates.
4-92
switching ch aracteristics
(V CC1 = 5V, V C'C2 = 20V, VCC3 = 24V; TA = 25°C)
TYP
MAX
tOLH
Delay Time, Low·to·High Level Output
PARAMETER
11
20
ns
tOHL
Delay Time, High·to·Low Level Output
10
18
ns
tTLH
Transition Time, Low·to·High Level Output
20
33
ns
tTHL
Transition Time, High·to·Low Level Output
20
33
ns
tpLH
Propagation Delay Time, Low·to·High Level Output
10
31
48
ns
tpHL
Propagation Delay Time, High·to·Low Level Output
10
30
46
ns
CONDITIONS
MIN
C L = 200 pF,'
Rc = 24n,
(Figure 1)
UNITS
ac test circuit and switching time .. waveforms
~ID",_
INfT
I
,
PUlSE
GENERATOR
(NOTE 1)
.V 24V 20V
-~I_I_I71
ee1
V
INPUT
VCC3 VCC2
I
I
I .d::::j
L ...2N~.JI
II
~
2.4V
I
I
1.18%
JV
9D~~
/1.5V
OV~
-~10ns
I.'VI\
1---0.",,-
Ro
1-',.,_
• ...b.,OUTPUT
~-~
1-
tDHL--
C,
IINoTE21
10%
-ITHL
Vo•
'0'._
Vm 2 V \
tTLH
-;
V"', -2V
OUTPUT
2V
Vo,
2V
Nott:1: The puhe pnerator hu the following chlrKtlristics: PR,R =- 1 MHz, louT"" SOn.
Note 2: CL includes probe MId Jig ClpKitance.
FIGURE 1. Switching Timas, Each Driver
typical performance c/laracteristics
0
2
"''"'"
l""'-
-0.5
....
~
'"
~
;±
~
"'s:
0
II
2
I III
~A=+10°C
!:;
co -1.0
>
TA·O°C'"'
~
-0.5
'"~
-'1.0
>
S
-1.5
== -1.5
-
0.5
-Z.5
iZ -2.0
VCC1 =5V
V= = ZOV
VCC3' 24V
V, = O.BV
-3.0
-0.01
..
-0.1
-10
-100
~
>
~
TA=+70°C~
III1 -rliJiOo~
VCC1 '" 5V
s:
V==VCc3 =ZOVI
VI =D.BV
S
TA - +2&°C
~
~ -2.5
-1
2
'"~
~
=>
co
-2.0
Low' Level Output Voltage
Output Current
High·Leval Output Voltage vs
Output Current
High·Level Output Voltage vs
Output Current
11111
-3.0
-0.01
0.2
'"
t
:i,
.1
.......:
VCC3 =24V
ITA=+7~ ~
0.3
~.
'I
VCC1- 5V
VCC2 " 20V
VI" 2V
~
.-100
-0.1
-1
-10
HIGH·LEVEL OUTPUT CURRENT (;"Al
HIGH·LEVEL OUTPUT CURRENT (mAl
0.4
0.1
0
~
~'O°C
/'"
ZO
40
50
BO
100
LOW·LEVEL OUTPUT CURRENT ImAI
I
,
.
4·93
typical performance :cha.racteristics (con't)'
Propagation Delay Time,
Low·to·High Level Output vs
Ambient Tem"",.ture
Total Dissipation (All Four
Voltage Transfer Charaetarilli..
...
~
w
~
c
Driven)
24
1000
20
900
li 800
.§
700
.
16
c
i
12
"5
~...
"...
Vee," 5V
VCC2 ·20V
J:
'"c
..
vcc•• 24V,
TA " ZSoC
NO LOAD
I-
VI
Frequency
40
~~!
I!",
..~~.
t=~
36
CL ~200pF
30
>",
600
25
CL~50!F
- .....
;:::
....
....
500
400
''''w
.....
~~-
300
200
100
20
15
VCC1 = IV
Vccz =20V
VCC3 = 24V
RD = 2411
(FIGURE H
10
lI:~
0
0.5
2.6
1.5
1
0.1
0,2
0:4 0.7 1
FRmUENCY (MHz)
INPUT VOLTAGE (V)
Propagation Delay Time,
High·to·Low
Lev~1
Sg
:r;:iil
;~
25
:s~
10
......
35
~~
g~
30
25
I!",
< ..
I~L'~OpJ
20
15
~~
CL =ZOOpF
30
ti~
40
.'=
'"
'"
.....
...
-",
~~
'(feci'a, 5V
VeC2 = ZOV
VCC3" 24V
fto =24n
U
li!
fa
i~
(FIGURE 1)
10
20
30
40
60
60
-
-c
,.
.....
LZOOjF
L........:"i"""
Zo
CL =I00pF-
15
VCC1 =5V
I
!~
.
.....
~~
....",
ii
>'"
"......
......
c"
;
...
50
40
;::;0
15
/
~~
0::
10
....=
....!...
j l
z,:;:.."..,e. ~
,/"."""
30 I-- RD! lOll
, "6;;;;~::;""'iio=O
20
70
:::
'""
I!",
50
.;::J:
" ..
......
.....
z ..
>'"
.....
....
f6
.. >
40
30
;::;0
....=
..,:,
",,,,
"
CL=200~
...-
'""C~O;:
VCC1I• 5V
I
VCC3 = Vea +4V
Ro = 241l
TA = 25'C
(FIGURE'I)
12
16
20
SUPPLY VOLTAGE (V)
20
VCC1 = 5V
VCC2 =20V
VCC3 '" 24V
TA = 25'C
(FIGURE 11
I
_
Ro o l01l'
r:-
:d;::::
~
~~ ~"'Rj,=0
10
50 100 150 200 250 300 350' 400
50 100 150 200 250 300' 350 400 ;
LOA,O CAI'ACITI\,NCE (pF)
UlAO'CAPI\CITANCE (pFI
typical applications
The fast switching speeds, of this device may produce
undesirable output transient overshoot because of load
or wiring inductance. A small series damping resistor
may be used to reduce or eliminate this output transient
4·94
BO
-
r-
Propagation Del~y Time,
High-to-Low Level OutPut vs
~Olid Capacitance
60
VCC2" IOV
VCC3 '24V
TA,zn
(fIGURE I) I--RD•
",
20
,
./
25
4812162024
SUPPLY VOLTAGE (V)
VCC1 =5V
10
....
~~
Zw
T. =25'C
(FIGURE 1)
70 80
35
,3D
.....
....
.....
I
VCC3 =V CC2 +4V
'Ro '" 25n'
10
.J
If,
......
>",
Propagation Delay Time,
Low-to-High Level Output VI
Load Capacitance
60
60
40
AMBIENT TEMPERATURE ('C)
.J
......
60
Propagation Delay Tima,
High-to-Low Level Output va
VCC2 Supply Voltage
Low4o-High Level Output vs
VCC2 Supply'Voltage
I
35
30 40
20
AMBIENT TEMPERATURE rC)
.-
40
!~
10
Propagation Delav Time,
Output va
Ambient Temperature
.... J
7 10
overshoot. The optimum value of the damping resistor
depends on the specific load characte~istics and switching
speed. A typical value would be between 10.11 and 30.11
(Figure 3).
~
o
(J)
typical applications (con't)
5V
19.sV
16V
Of
w
en
5V
U1
INPUTS
TTL
I
nl
J
INPUTS
Note: Ro "" lOU to 30n (Optional).
FIGURE 2. Interconnection of OS75365 Devices
With 1103-Type Silicon-Gate MOS RAM
FIGURE 3. Use of Damping Resistor to Reduce or
Eliminate Output Transient Overshoot In Certain
OS75365 Applications
thermal information
POWER DISSIPATION PRECAUTIONS
Significant power may be dissipated in the OS75365
driver when charging and discharging high-capacitance
loads over a wide voltage range at high frequencies.
The total dissipation curve shows the power dissipated in
a typical OS75365 as a function of load capacitance and
frequency. Average power dissipation by this driver
can be broken into three components:
PT(AV) ; POC(AV) + PC(AV) + PS(AV)
where POC(AV) is the steady-state power dissipation with
the output high or low, PC(AV) is the power level during
charging or discharging of the load capacitance, and
PS(AV) is the power dissipation during switching between
the low and high levels. None of these include energy
transferred to the load and all are averaged over a full
cycle.
neglected. The total dissipation curve for no load
demonstrates this point. The power dissipation contributions from all four channels are then added together
to obtain total device power.
The following example illustrates this power calculation
technique. Assume all four channels are operating identically with C; 100 pF, f; 2 MHz, VCC1 ; 5V, V CC2 ;
20V, VCC3 ; 24V and duty cycle; 60% outputs high
(tH(f; 0.6). Also, assume V OH ; 20V, VOL; 0.1V,
Ps is negligible, and that the current from VCC2 is
negligible when the output is low.
On a per-channel basis using data sheet values:
m~\ (24V)
X--4-t
(-2.2
4 mA)
POC(AV); [(5V ( - 4 - + (20V)
(2.24mA)] (0.6) + [(5V) (31 ;A) +
The power components per driver channel are:
POC(AV);
PLtL +PHtH
T
(20V) (0 ;A) + (24V) (16 4mA)] (0.4)
PC(AV) "" C VC2 f
POC(AV) ; 58 mW per channel
PC(AV) "" (100 pF) (19.9V)2 (2 MHz)
where the times are as defined in Figure 4.
PC(AV) "" 79 mW per chanl7!el.
PL, PH, PLH, and PHL are the respective instantaneous
levels of power dissipation and C is load capacitance.
The OS75365 is so designed that Ps is a negligible portion of PT in most applications. Except at very high
tLH + tHL so that Ps can be
frequencies, tL + tH
»
For the total device dissipation of the four channels:
PT(AV) "" 4 (58 + 79)
PT(AV) "" 548 mW typical for total package.
1-----T·1"-----I
FIGURE 4. Output Voltage Wavaform
4-95
c
~
Sense Amplifiers
~
0')
o
(11
.......
C
NAnONAL
(J)
W
OS1605/0S3605, OS1606/0S3606, OS1607/0S3607,
OS1608/0S3608 hex MOS sense amplifiers (MOS to TTL converters)
0')
o(11
general description
..c
(J)
The DS3605 series is a new series of programmable
hex MOS sense amplifiers featuring high speed direct
MOS sense capability with high impedance states to
allow use of a common bus line. The DS1605/DS3605
and the DS1606/DS3606 have TRI-STATE® outputs.
The DS1607/DS3607 and DS1608/DS3608 have both
TRI-STATE inputs and outputs. High impedance states
are controlled by an enable input.
Input current threshold (the level at which the output
changes state) is determined by the current at the
programming pin. The current threshold is 100pA with
the programming pin grounded and 250pA with the pin
unconnected. The threshold can be set from 100pA to
300pA by connecting a resistor from the pin to ground,
and set above 300pA by connecting a resistor from the
pin to the positive supply.
Outputs are high current drivers capable of sinking
50 mA in the low state and sourcing 5 mA in the high
state,
features
•
•
•
•
•
•
•
•
•
Non-inverting inputs (DS1605/DS3605, DS1607/
DS3607)
Inverting inputs (DS1606/DS3606, DS1608/DS3608)
No external components required (direct MOS sensing)
Programmable input thresholds
Current sensing-100pA minimum
50 mA drive capability
TRI-STATE control
Single 5V supply
15 ns typical propagation delay (DS3605)
0')
o
0')
.......
C
(J)
w
0')
o
0')
c(J)
a;
o
~
c(J)
w
0')
o
:oJ
:connection diagram
..c
typical application
(J)
0')
o
PACE Interface
Dual-I n-Line Package
00
.......
C
(J)
W
0')
, OM8!iJl
o
BUFFERS
00
AOM
ADORESS
LATCH
3053601
--t>-- 1----,1
HEX SENSE
AMPS
TOP VIEW
DATA AND ADDRESS
OUTPUT
JOMB097
ordering information
PACE
--- t - - - - v '
ORDER NUMBERS
DS1605J, DS1606J, DS1607J, DS1608J
PACKAGE
HEX SENSE
STROBE AND flAG
AMPS
OUTPUT
Cavity DIP (J)
DS3605J, DS3606J, DS3607J, DS3608J
Cavity DIP (J)
DS3605N, DS3606N, DS360lN, DS3608N
Molded DIP (N)
INTERRUPT AND JUMP CONDITION INPUTS
n33608 shown as an interface between the PACE
micropmcessor and TTl data bus and I/O bus,
5-1
CIO
oCD
abs.olute maximum ratings
operating conditions
(Note 1)
C")
(/)
o
CD
Supply Voltage
I nput Voltage
Output Voltage
I nput Drive Current per Input
Storage Temperature Range
rJ)
Lead Temperature ,(S.oldering, 10 se'conds)
"CIO
...o
o
7V
5.5V
5.5V
25mA
-65° e 10150° e
300°<:;,
MIN
MAX
UNITS
4.75
5.25
V
4.5
5.5
V
0
+70
°e
-55
+125
°e
Supply Voltage, Vee
DS3605/DS3606,
DS3607/DS3608
DS1605/DS1606,
DS 1607/DS 1608
Temperature, TA
roo;
DS3605/DS3606,
DS3607/DS3608
CD
DS 1605/DS 1606,
DS1607/DS1608
o
C")
rJ)
I
o
S
...
CD
rJ)
dc electrical characteristics
(Notes 2 and 3)
Q
CONDITIONS
PARAMETER
MIN
TYP
MAX
UNITS
CD
o
CD
C")
rJ)
Di~able
V IH
Logical "1" In!lut VOltage
Vee = Max, VIN = 2.4V
IIH
o
V IL
Logical "0" Input Voltage Disable
Vee = Min
8
IlL
Logical "0" Input Current Disable
VIN = O.4V
"-
~
o
Veo Inpllt Clamp Voltage Disable
'V OH Logical "1" Output Voltage
los
In
o
Output Short Circuit Current
VOL Logical "0'.' Output Voltage
CD
C")
rJ)
10L
o
o
Logical "0" Output Current
In
...
CD
Vee = Min, lOUT = -5 mA
liN
Vee = Max, O.4V ~ VIN ~ 5V
-40
ITH
Input Threshold Current
Vee = 5V, T A = 25°C,.l p = OpA
Vee - 5V, TA - 25°C, Ip -1 mA
lee
Vee", Max
V
mA
-1.5V
-50
-90
V
V
mA
0.4
V
50
-40
IMAX Maximum Input Driver Per Input
0.8
-1.6
-1
0.3
Vee = Min, lOUT = 50 mA
Vee = Min, VOL = 0.4
pA
2.4
-20
Vee = Max, O.4V:S: V OUT ~ 2.4V
rJ)
o
Vee = Min, liN = -12 mA
• Vee=.Max, V OUT = OV (Note 4)
V
40
TRI·STATE Inpllt Current
lOUT Tfll·STATE Output Current
......
2
Vee = Min
Logical "1 "Input Current Disable
100
1000
mA
40
pA
40
pA
250
1250
400
1500
pA
pA
15
8
mA
80
90
90
80
115
115
130
115
mA
mA
mA
rnA
Supply Current
Vee = Max
DS 1605/DS3605
DS1606/DS1607
DS3606/DS3607
DS 1608/DS3608
Note 1: "Absolute Maximum Ratings'~ are those values beyond which the safety o·f the device cannot be guaranteed. -Except for "Operating
Temperature Range" they ~re not meant to imply That the,devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for "actual dey-ice' operation.
Note 2: Unless otherwise specified minimax limits apply across the -55°C to +12SoC temperature range for the 081605. OS1606, DS1607and
DS1608, and across the ooe to +700 e range for the DS3605, DS3606, DS3607 and DS3608. All typicals are given for Vee = 5.0V, and TA
=
2Soe.
Note 3: All currents into device pins shown as posi'tive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as .max or min on absolute value basJs.
Note 4: Only one output at a time should be shorted.
5-2
c
5!l
en
ac electrical characteristics Unless otherwise specified, T A -= 25°C, Vee = 5V
o
U1
........
C
CJ)
PARAMETER
CONDITIONS
TYP
MAX
OS1605(OS3605
15
22
C L = 50 pF, RL = 8011,
OS1606(053606
26
39
ns
Ip = 7501lA, liN = 2 rnA
D51607(OS3607
24
35
ns
OS1608(OS3608
20
30
ns
OS 1605(DS3605
15
22
ns
C L = 50 pF, RL = 8011,
OS1606(D53606
19
29
ns
Ip = 750!1A, liN = 2 rnA
DS1607(053607
19
29
ns
DS1608(053608
14
21
ns
CJ)
051605(053605
18
32
ns
en
o
en
t pDO Propagation Delay
t po1 Propagation Delay
tOH
TRI-STATE Oelays (lnput(Output)
MIN
w
UNITS
C L =5pF,R L =80n,
OS1606(DS3606
18
32
ns
Ip = 750!1A, liN = 2 rnA
DS 1607(DS3607
20
35
ns
en
o
ns
U1
c
CJ)
~
en
o
en
C
........
w
c
OS1608(DS3608
20
35
ns
DS1605(oS3605
8
14
ns
CL = 5 pF, RL = 8011,
OS 1606(DS3606
8
14
ns
Ip = 750!1A, liN = 2 rnA
DS1607(D53607
10
18
ns
DS 1608(D53608
10
18
ns
051605(053605
22
40
ns
w
o
CJ)
t'H
tHO·
TRI-STATE Oelays (Input(Output)
TRI-5TATE Oelays (Input(Output)
C L = 50 pF, RL = 8011,
051606(D53606
20
35
ns
Ip = 750!1A, liN = 2 rnA
D51607(OS3607
45
80
ns
OS1608(OS3608
45
80
ns
t H1 • TRI-STATE Oelays (Input(Outputl
~
en
~C
CJ)
en
~
c
DS 1605(DS3605
25
45
ns
CJ)
C L = 50 pF, RL = 80n,
OS1606(OS3606
26
45
ns
Ip = 750!1A, liN = 2 rnA
OS1607(OS3607
35
60
ns
en
o
OS1608(OS3608
35
60
ns
........
~
00
C
"Data valid only after this delay.
CJ)
w
en
o
00
truth tables
051605/053605 (Note 1)
051606/053606 (Note 2)
liN
. DIS
OUT
liN
OIS
OUT
X
H
Hi-Z
X
H
Hi-Z
>IT
L
H
>IT
L
L
IT
L
L
>IT
L
H
~....
~
CD
~
5
BOO
Q
:z:
!ll:z:
600
....
400
~
EQUIVALENT TO PIN:
BEING ~PEN 1
200
VJ
-5
/
O!
-10
o
/
I
Q
;:
30
IVee l• 5J
20
"
5
[2
r'\
Q
'":z:....
-10
~
-20
....
'\
-30
-15 -50 -25 0
5.5
[\
",
POWER SUPPl V (V)
CD
I"OPEN-
\.
10
:>
4.5
VOLTAGE AT PROGRAMMING PIN (V)
..
..~
g
/
;:
:z:
VJ
T.· zk.·c
Ip "'OPEN
Q
~ 1200
CD
M
10
~
25 50 15 100 125 150'
T. - AMBIENT TEMPERATURE rC)
o
CD
M
VJ
o
......
Typical Input Threshold Current vs
Program Resistor OS3605 Series
CD
o
1600
~
1400
VJ
o
~ 1200
it)
5
1000
§l
o
co
fa 800
VJ
~
'"
....
x
M
o
......
O!
o
\
~
30
600
..'"
Capacitance OS 1606/0S3606
50
I
I
I
g:
20
~
30
~
;:
~
.... 1"'"
i
Q
~
:!
40
I
I
t"",
>-
t .... .d
.... "..t"',
Q
;:
~
:;!
IN~rr
~
r- I•• 115o"A
_ ~~d1!;~mA
>-
~RESISTOR TO VC~
10
I.--
.....
r- ......;'''''
15
20
25
......
V
20
Ip = 750pA
;11NW=2mA
'Vee = 5V
10
I
30
50
100
150
200
Typical Propagation Delay ys Input
Capacitance OS 1607/0S3607
50
:!
40
~,
30
>-
'"
Z
Q
;:
~ 20
:;!
~
50
250
f-
I,' 750"A
r-
IINm"'2mA
Vee = 5V
-
"",,1i'"
I
-r-";"~ e""'" t..,
r--
Typical Propagation Delay vs Input
Capacitance OS1608/DS3608
50
:!
>-
~
'"z
....... [;.;'
..'"
I
I
40
30
.....
Q
;:
;'
:;!
~
10
100
20
k--'
.......
V
t~.!-- .......
.......
.......... -e-c-
I
Ip = 750tlA
IINt1I=2mA
Vee =5V
10
rf-
I
50
100
150
200
INPUT CAPACITANCE (,F)
250
150
200
INPUT CAPACITANCE (,F)
INPUT CAPACITANCE (,F)
PROGRAM RESISTOR (kn)
5·4
?'-
RESISTOR TO GROUND
10
~o
!
40
I
I
\
Typical Propagation Delay vs I"put
Capacitance OS1605/0S3605
50
.I. .1.
~~e:2:YC-
400 TYPICAL
200
it)
I
\
Typical Propagation Delay vs Input
50
100
150
200
INPUT CAPACITANCE (,F)
250
250
c
!!l
en
ac test circuit
o
- - - -.....- 0 vee"
0'1
5V
.......
C
so
CJ)
w
en
o
0'1
All 010 DES ARE lNJ064
...enc
CJ)
o
en
-~~-~~-~~-OGND
.......
C
CJ)
switching time waveforms
w
en
o
en
, rnA
INPUT
WAVEFORM
C
...en
DmA
CJ)
~C
OUTPUT
081605/081608
CJ)
w
en
o
:-J
OUTPUT
0$1606/081607
3V
1.5V
DISABLE
cCJ)
...en
1.5V
DV
o
00
.......
cCJ)
OUTPUT
w
en
o
00
equivalent circuit
-----,
I
1k
INPUT
o-------1r-----1r---''-'""'1r-to........
4.5k
PROGRAMMI~~ o--,\,.,',.,k.,-............_ - \
I
I
I
TO TTL
OUTPUT
STAGE
I
I
I
I
I
DISABLE
(NOTE 1)
I
GNDo------4~---4~-_,--__
~-__
--_-~_~~
TYPICAL CIRCUIT;
ONE OF SIX SHOWN
Note 1: On tile DSJ6D5 and 0$3606, the disable is Dilly connected to the output stage. On' the
DS36D7and DSJ60B,it IS connected tn both the input and output,
Note 2: Diode 03 is used in lhe OS3607 and 053608 only. In the 083605 and 083606, the
emitter of Q4 IS connected directly to ground.
5-5
~
Sense Amplifiers
NAll0NAL
OS3625 dual high speed MOS sense amp
general description
features
The 0S3625 is a dual high speed MOS to TTL level
converter. It acts as an interface level converter between
MOS and TTL logic devices. It consists of two 1-input
converters with common strobe input to inhibit "0"
entry when strobe is high. It allows parallel entry when
strobe is low and the internal latch is preset by the com·
mon preset input. TRI·STATE® output logic is imple·
mented in this circuit to facilitate high speed time sharing of decoder-drivers, fast random-access (or sequential)
memory arrays, etc.
•
EasilV interfaces with most popular 1k and 2k
dynamic MOS RAMs
• Pin-for-pin replacement for the 8T25
• Very low output impedance - high drive ability
•
High impedance output state whicb allows many out·
puts to be connected to a common bus tine
• Average power dissipation 110 mW per converter
logic and connection diagrams
rNA
(CURRENT INPUT)
OUTPUT A
rN,
(CURRENT INPUT)
OUTPUT B
PRESET
DISABLE
DuaHn-Line Package
OUTPUT A
OUTPUT B
INPUT A
DlSABLEIPRESET
GND
INPUTS
TOP VIEW
Order Number DS3625N
5-6
absolute maximum ratings
Su ppl y Vol tage
Input Voltage
Output Voltage
7.0V
5.5V
5.5V
-65°C to 150°C
300"C
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
electrical cha racteristics
operating conditions
(Note 1)
MIN
MAX
Supply Voltage (VCC)
4.75
5.25
Temperature (T A)
0
+70
°c
TYP
MAX
UNITS
V
(Note 2)
PARAMETER
CONDITIONS
IINA,IINS
Logical "1" Input Current
Vee = Min
!INA,IINS
Logical "0" Input Current
Vee
V ,H
Logical" 1" I nput Voltage
Strobe, Preset/Disable, Vee = Min
V ,l
Logical "0" Input Voltage
Strobe, Preset/Disable, Vee
V OH
Logical" 1" Output Voltage
Vee
Val
Logical "0" Output Voltage
Vee = Min,
10
TR I-STATE Output Current
I'H
UNITS
:=
:=
Vee
:=
400
J.!A
200
Min
Min,
Vee = Max
Logical "1" Input Current
MIN
Max
lOUT
:=
lOUT =
:=
Min
-1.5 rnA
J.!A
V
2.0
0.8
V
0.4
V
2.8
V
16 mA
Va =3.9V
100
J.!A
Va - O.OV
-100
J.!A
V ,N = 2.4V
40
J.!A
V ,N - 5.5V
1.0
rnA
-1.6
rnA
40
rnA
I,l
Logical "0" I nput Current
Vee = Max, V ,N = O.4V
Icc
Supply Current
Vee = Max,
V eD
Input Clamp Voltage
Vee = Min, liN = -12 rnA
Ise
Output Short Circuit Current
Vee = Max, Va = OV, (Note 3)
V1N(PRE/DIS) =
2.0V, Other Inputs:= OV
1.5
-20
-70
V
rnA
switching characteristics
PARAMETER
td'
Propagation Delay to a Logical "0" from
CONDITIONS
MIN
MAX
UNITS
Vee = 5.0V, T A = 25°C
TYP
17
25
ns
Vee = 5.0V, T A = 25°c
7.0
11
ns
Vee = S.OV, T A = 2SoC
17
25
ns
Vee = S.OV, T A = 25°c
9.0
14
ns
Vee = 5.0V,
13.5
16
ns
Strobe to Output
t'H
Delay from Disable Input to High Impedance
State (from Logical "1" Level)
toH
Delay from Disable Input to High Impedance
State (from Logical "0" Level)
t H,
Delay from Disable Input to Logical "1"
Level (from High Impedance State)
tHO
Delay from Disable Input to Logical "0"
TA
= 25°C
Level (from High Impedance State)
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless othelWise specified minImax limits. apply across the OC e to +70°C range. All typicals are given for Vec =5.0V, T A = 25°C.
Note 3: Only one output at a time should be shorted.
5-7
....
It)
CO
M
en
C
'
~
~
Sen'se Amplifiers
Advance Information*
NAnONAL
DS3651. DS3653 quad high speed MOS sense amplifiers
general description
features
The OS3651 and OS3653 are TTL compatible high speed
circuits intended for sensing in a broad range of MOS
memory system applications. Switching speeds have been
enhanced over conventional sense amplifiers by application of Schottky technology, and TR I-STATE® strobing
is incorporated offering a high impedance output state
for bused organization.
•
High speed
15 ns (typ)
• TTL compatible
•
Input sensitivity
±( mV
• TRI-STATE outputs for high speed buses
±5V
• Standard supply voltages
The OS3651 ,has active puil-up outputs, and the OS3653
offers open collector outputs providing implied" ANO"
operations.
•
Pin and function compatible with MC3430 and
MC3432
truth table
connection diagram
Dual-In-Line, Package
Vee
-IN B
+IN 8
OUT B
VEE
OUT 0
+IN 0
-IN a
ST~OBE
INPUT
OUTPUT
OS3651
OS3653
V 10 ;::- +7.0 mV
L
H
Open
TA "" bOe to +70°C
H
Open
Open
L
X
Open
X
Open
L
Open
-7.0 mV::::; V ID
:::;
+7.0 mV
TA ==
aOc to +70°C
V ID ,5 -7.0 mV
H
L
L
T A = QOeta +70°C
H
Open
L = Low logic state
-IN A
+IN A
OUT A
SIB
OUT C
+fN C
-IN C
GNO
TGPVIEW
H = High logic state
Open = TRI-STATE
X = Indeterminate State
Order Number DS3651J, DS3651N,
DS3653J or DS3653N
typical applications
A Typical MOS Memory Sensing ApplicatiQn for a 4k word by 4..flit
memory arrangement. employing 1103 type memory devices
10---4--0 DATA BlT4,
200
200
DATA BIT 3
p.-+--r--o DATA BIT 3
200
DATA BIT 2
P.-+-+-oDATA BIT 2
200
DATA BIT 1
'svo-....'V\.IIr-.....- - - - - - - -....-->-~_tt;..
18k
Note: Only four devices are required for a 4k
word by 16·bit memory system.
200
STROBE
Jo-+-;-<:>DA'TA BIT 1
0------<>--t--l
*Specifications may change
5-8
absolute maximum ratings
operating conditions
(Note 1)
(T A = O°C to +70°C unless otherwise noted.)
Power Supply Voltages
Power Supply Voltages
±7.0 Vac
±7.0 Vac
VCC
VEE
VCC
VEE
Output Load Current, IOL
Differential-Mode Inpu't Signal Voltage
Range, VIDR
Common-Mode Input Voltage Range, VieR
Strobe Input Voltage, VI(S)
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
Differential~Mode
±6.0 Vac
±5.0 Vac
5.5 Vae
-55"C to +150"C
300"C
MIN
MAX
UNITS
+4.75
-4.75
+5.25
-5.25
16
Vac
Vac
mA
o
-5.0
+5.0
Vac
U'I
-3.0
+3.0
Vac
-5.0
0
+3.0
+70
vac
"C
MAX
UNITS
±7.0
mV
en
w
en
w
Input
Voltage Range, VIDR
Common¥Mode Input
Voltage Range, VICR
Input Voltage Range (any
input to GNa), VIR
Operating Temperature Range
electrical characteristics
(V cc = +5.0 V oc , \lEE = -5.0 V oc , TA = O°C to +70oC unless otherwis.e noted.) (Notes 2 and 3)
PARAMETER
V's
CONDITIONS
MIN
I nput Sensitivity , (Note 5)
(Common·Mode Voltage Range =
4.75::; Vee::; 5.25V
-3.0V::; V'N ::; 3.0V)
-4.75 ~ VEE
~
-5.25V
V,o
I nput Offset Voltage
liB
Input Bias Current
1'0
Input Offset Current
VIL(S)
Strobe Input Voltage (Low State)
V1H(S)
Strobe Input Voltage (High State I
'ILlS)
Strobe Current (Low State)
Vee = 5.25V. VEE = -5.25V. V'N = O.4V
'IH(S)
Strobe Current (High State)
Vee = 5.25V.
VEE = -5.25V
V OH
Output Voltage (High State)
2
Output Voltage (Low State I
1
Vee =4.75V
Output Leakage Current
Vee = 4.75V.
VEE = -4.75V
los
Output Current Short Circuit
V
V
2
Vee = 4.75V.
/iA
/i A
0.8
VEE = -4.75V
'CEX
mV
20
Vee = 5.25V, VEE = -5,25V
VEE = -4.75V
VOL
TVP
-1.6
mA
V ,N =2.4V
40
V'N = 5.25V
1
/iA
mA
10 = -400/iA
OS3651
V
2.4
10 = 16mA
Vo = 5.25V
Vee = 5.25V. VEE = -5.25V
(Note 41
OS3652
OS3651
-18
0.4
V
250
/iA
-70
mA
IOFF
Output Disable Leakage Current
Vee = 5.25V. VEE = -5.25V
40
/iA
lee
High Logic Level Supply Current
Vee = 5.25V. VEE = -5.25V
45
60
mA
lEE
High LogiC Level Supply Current
Vee = 5.25V. VEE = -5.25V
-17
-30
mA
switching characteristics
(V cc =+5.0V oc • VEE =-5.0V oC • T A = +25°C unless otherwise noted,)
PARAMETER
tpH L(D)
High-to-Low Logic Level Propagation
Oelay Time (Oifferential Inputs)
tpLH(D)
Low-to-High Logic Level Propagation
Delay Time (Differential Inputs)
tpOH(SI
TRI·5TATE to High Logic Level
Propagation Delay Time (Strobe)
tpHO(S)
High Logic Level to TRI·STATE
Propagation Delay Time (Strobe)
tpOL(S)
TRI·5TATE to Low Logic Level
Propagation Delay Time (Strobe)
tpLO(S)
Low Logic Level to TRI·5TATE
Propagation Delay Time (Strobe)
tpHL(S)
H igh-to- Low Logic Level
Propagation Delay Time (Strobe)
tpLH(S)
Low-to-High Logic Level
Propagation Delay Time (Strobe)
053651
CONDITIONS
MIN
TVP
MAX
UNITS
OS3651
10
ns
OS3653
12
ns
OS3651
15
ns
OS3653
18
ns
(Figure 1)
053651
8
ns
(Figure 1)
OS3651
8
ns
(Figure 1)
053651
10
ns
(Figure 1)
053651
10
ns
ns
5.0 mV + V's. (Figure 3)
5.0 mV + V's. (Figure 3)
(Figure 2)
(Figure 2)
OS3651
7
053653
8
ns
OS3651
7
ns
OS3653
8
ns
5·9
notes
Note 1: "Absolute Maximum Ratings" are thos,e values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
.
,
,
Note 2: Unless otherwis~ specified min/~ax limits appiy across the O°C to +70°C range for the OS3651 and 083653. All typical values are for
T A = 25°e, Vee = 5V, and VEE = -5V.
Note 3: All currents into device pins shown as positive. out of device pins as negative. all voltages referenced to grou'1d unless otherwise noted.
All values shown as max or min on absolute value 'basis.
Note 4: Only one output at a time should be 'sho~ted.
Note 5: A parameter which is of primary concern.when designing with sense amplifiers is, what is the minimum differential input voltage required
at the sense amplifier input termi,nals to guarantee a given output logic state. This Parameter is commonly referred to as thresholdvoitage. It is
well known that design considerations of threshold voltage are plagued by input ,qHset currents, bias currents, network source resistances, and
voltage gain. As a design convenience, the 053651 and 053653 are specified to a Parameter called input sensitivity (VIS). This parameter takes
into consideration input offset currents and bias 'currents, and guarantees a minimum input differential voltage to cause a given output logic state
with respect to a maximum source impedance of 200 ohms at each input.
ac test circuits and switching time waveforms
+5.0V
Vlo----t---o-.:.j
Vl
V2
Sl
82
CL
tPLO(Sl
100mV
GND
Closed
Closed
15 pF
tpOLfS)
100mV
GND
Closed
Open
50pF
tpHO(S)
GND
100 mV
dosed
Closed
15 pF
tpOH(S)
GND
100mV
Open
Closed
50 pF
V20----t-.--o-~
E,"
CL includes jig and probe capacitance.
E I N waveform characteristics: tTLH and tTH L
measured 10% to 90%.
PRR " 1.0 MHz
Eo
Duty
Cycle
=
50%
Note: Output of Channel 8 mown under test,' other channels are tested similarly.
tpLO(S)
tpHO(S)
3.DV~
E,"
E,"
DV~~
r"HO$'
DV
~
_ _ _ _ "-'1.5V
VOH
Eo
Eo
.
,
VOH - n.5V
. - - - - - , 1.5V
tPOL(S)
E,"
E'N
OV
5.0V-VO t
Eo
tPOH(S)
3'DV~0%
~
",.
I
OV
tpouS)
tpOH(S)
OH
V
,\1.5V
Eo
DV
VO, - - - - - '.....- - - -
FIGURE 1. Strobe Propagation Delay Times tpLO(S), tpOL(S). tPHL(S) and tpOH(S)
+5.0V
-0.:.-1
+100 mV 0 - - - - -....
390
E,"
\o:.:::-l
Level Detector with Hysteresis
270
270
270
270
_ _ _--,
Transfer Characteristics and Equations
for level Detector with Hysteresis
1/4053651
VOUT
VH1GH
VlOW
-
At R2
As "" R1+R2
- VH
VIN (VOLTS)
R2 [V01MAXI- VR6FI
V HIGH '" V REF
Vww " VREF
+
HYSTERESIS LOOP (VHI
5-12
R1 + R2
R2 [VOIMINI- VREF l
+
R1 + R2
~
Sense Amplifiers
NAnONAL
OS5520/0S7520,OS5520AlOS7520A series,
dual core memory· sense amplifiers
general description
The devices in this series of dual core sense
amplifiers convert bipolar millivolt-level memory
sense signals to saturated logic levels. The design
employs a common reference input which allows
the input threshold voltage level of both ampl ifiers
to be adjusted. Separate strobe inputs provide time
discrimination for each channel. Logic inputs and
outputs are OTLITTL compatible. All devices of
the series have identical preamplifier configurations, while various logic connections are provided
to suit the specific application.
The OS5520/0S7520 has output latch capability
and provides sense, strobe, and memory function
for two sense lines. The OS5522/0S7522 contains a single open collector output which may be
used to expand the number of inputs of the
OS5520/0S7520, or to drive an external Memory
Oata Register (MOR). Intended for small memories, the two channels of the OS5524/057524 are
independent, with two separate outputs. The
OS5534/0S7534 is similar to the OS5524/
OS7524 but' has uncommitted, wire-ORable outputs. The OS5528/0S7528 has the same logic
configuration of the OS5524/057524 and in
addition provides separate low impedance Test
Points at each preamplifier output. A similar
device having uncommitte,d, wire-O Rabie outputs
is the OS5538/0S7538.
features
• Highspeed
• Guaranteed narrow threshold uncertainty over
temperature
• Adjustable input threshold voltage
• Fast overload recovery times
• Two amplifiers per package
• Molded or cavity dual-in-line package
• Six logic configurations
Part numbers ending with an even number followed by an "A" (e.g., OS5520A) correspond to
a very tight input threshold of ±2 mY. Part numbers ending with an even number (OS5520)
correspond to an input threshold of ±4 mY. Part
numbers ending with an odd number (e.g.,
OS5521) correspond to an input threshold of
±8 mY. The remaining specifications for the three
are identical. All devices meet or exceed the specifications for the corresponding device (where
applicable) in the SN5520/SN7520 series and are
pin-f.or.-pin replacements.
Because these devices are duals that contain an
internal regulator, care must be exercised in testing
to insure that while one half is being tested, the
other inputs must be grounded or connected to
a signal that is within the input range of the device.
absolute maximum ratings
Supply Voltage
Differential or Reference Input Voltage'
Logic Input Voltage
Operating Temperature Range
DS55XX
DS75XX
Storage Temperature Range
±7V
±5V
5.5V
--55°C to +125°C
O°C to +70°C
--65°C to +150°C
typical application
MEMOA't'DA'A
REGISTER
[,"--,
~-+-__...;....j/ ~"1:r:Io--+H+-~1
:
I
I
L __ J
Expanded Small Memory System
5-13
II)
CD
'C
CD
055520/087520, 055520Al057520A and 0555211057521
II)
«o
N
In
~
C
~
o
N
In
In
electrical characteristics
OS5520IDS5520A, OS5521 :
OS7520/0S7520A, OS7521:
en
PARAMETER
Q
o
V TH
V AEF "" 15 mV
Vee ~,..±5.0V
~
Q
INote 41
V REF ""40mV
'BIAS
In
In
en
Q
CONDITIONS
Differential Input Threshold
Voltage
N
C3
N
The following apply for -55°C s::: TA s::: +125°C
The following apply for O°C s::: TAS::: +70°C
Differential and Reference
Input Bias Current
los
Differential Input Offset
Vee" ±5.25V,
Y'N "OV
Vee" ±5.25V
V 01FF
= OV,
MIN
TYP
OS5520/0S7520
11
15
19
mV
OS5520A/OS7520A
13
15
17
mV
OS5521/0S7521
OS5520/0S7520
8
15
22
mV
36
40
44
mV
OS5520A/OS,520A
38
40
42
mV
OS5521/oS7521
33
40
47
mV
OS5520/0S5520A, OS5521
30
100
/iA
OS7520/0S7520A.OS7521
30
75
/iA
Y'N ~ OV
MAX
0.5
UNITS
/iA
Current
V ,H
Logical "1" Input Voltage
I'H
Logical "l"-lnput Current
Strobe, Gate Inputs
VIL
Logical "0" Input Voltage
I'L
Logical "0" I nput Current,
2
Vee" ±5.25V
V cc " ±5.25V.
V 1N
= 2.4V
V
5
40
/i A
mA
1
Y'N " 5.5V
-1
V ,N "O.4V
0.8
V
-1.6
mA
-1.5
V
Strobe, Gate Inputs
Veo
Input Clamp Voltage
liN = -12 rnA
V OH
Logical "1" Output Voltage
Vee" ±4.75V. 10" -400/iA
Isc
Output Short Circuit Current
VOL
Logical "0" Output Voltage
Vee" ±4.75V. 10" 16 mA
'CEX
Output Leakage Current
Vo "5.25V
Icc+
V+ Supply Current
Vee" ±5.25V
'cc-
V
Vee" ±5.25V
Supply Current
Vee" ±5.25V. Vo" OV
2.4
3.9
V
Q Output
-3
.-4
-5
mA
Q Output
-2.1
-2.8
-3.5
mA
0.25
0.4
V
250
/iA
21
35
mA
-13
-18
mA
Note 1: For O°C:::: TA:O; +70°C operation, electrical characteristics for DS5520/0S5520A and OS5521 are guaranteed the same as OS75201
OS7520A. and OS7521, respectively.
Note 2: Positive current is defined as current into the referenced pin.
Note 3: Pin 1 to have 2 100 pF ca'pacitor connected to ground.
Note 4: For minimum VTH. logic output is
< O.4V at 16 rnA. For maximum VTH logic output is > 2.4V at -400J.tA.
\
5-14
o
fA
OS5520/0S7520, OS5520A/OS7520A and OS552110S7521
U1
U1
N
o
.......
o
~
U1
N
o
sw itch ing cha racteristics
v+ = 5.0V, v- = -5.0V,
TA
o
= 25°C
fA
PARAMETER
tpdt
CONDITIONS
Differential Input to
Logical "1"
tpdO
Differential Input to
Logical "0"
tpdl
Strobe Input to
Logical "1"
tpdO
Strobe Input to
Logical "0"
tpdl
Gate
Q
Input to
Gate
Q
1nput to
Gate Q Input to
Logical "1"
tpdO
Gate Q Input to
Logical "0"
tOR
Differential Input Overload
Recovery Time
tCMA
Common·Mode Input Overload
Recovery Time
tCY
Minimum Cycle Time
VCM
AC Common-Mode Input
Firing Voltage
20 mY, Be Test Circuit 1
""
V REF
= 20 rnA,
V REF
=:
V REF
'Logical "0"
tpd1
=
V REF
V REF
Logical "1"
tpdO
V REF
==
:=
MIN
20 rnA, ae Test Circuit 1
ae Test Circuit 1
20 rnA, ae Test Circuit 1
20
20 mV, ae Test Circuit 2
MAX
40
Q Output
36
o Output
28
Q Output
28
55
Q Output
10
30
Q
Output
33
Q
Output
Q Output
20
16
Output
12
Q
20 mY, ae Test Circuit 2
TYP
Q Output
Q Output
17
Q Output
6
o Output
19
Output
12
UNITS
20
ns
ns
30
ns
ns
V REF ==
V REF
=:
20 mY, ae Test Circuit 2, Q Output
6
V REF
=
20 mV, ac Test Circuit 2
10
ns
V REF == 20 mV, ac Test Circuit 2
5
ns
V AEF == 20 mV, ac Test Circuit 2
200
ns
±2.5
V
Pulse
o
~
U1
ns
ns
20 mY, ae Test Circuit 2, Q
-
~
ns
ns
ns
ns
N
o
»
en
CD
::::S.
CD
en
ns
20
ns
Note 1: For O°C:s TA:S +70°C operation, electrical characteristics for D55520/0S5520A and 055521 are guaranteed the same as D575201
DS7520A, and DS7521, respectively.
Note 2: Positive current is defined as current into the referenced pin.
Note 3: Pin 1 to have
2.
100 pF capacitor connected to ground.
Note 4: For minimum VTH, logic output is
< O.4V
at 16 rnA. For maximum VTH logic output is
N
o
ns
ns
55
U1
U1
> 2.4V at -400J.lA.
5-15
!
'S:
CI)
OS5520/0S7520, OS5520A/OS7520A and OS5521/0S7521
VI
«
o
N
Il)
"enc
schematic diagram
<
o
N
Il)
Il)
J-~-t------,---+--o
o
c
<,,,
REfERENCE}
INPUT 1
o
l
N
~
C
GAT~ o--+--+~==t::!:==:!::~:::.t--------,
~
N
I
Il)
Il)
OIFHflHHlAL}
INPUT A
en
c
OUTPUT
+ __
GAT~o-_+_ _ _ _ _ _
-'-!~l+--'
connection diagram
DUal·1 n-Line Package
"
C.~r
STROBE
A
(iAn
II
~
DiffERENTIAL
INPUT A
OUTPUT OUTPUT STROBE
II
Q
a
-
+
~
AEFERENt!
INPUT
GATE
Q
~
IlIfFEAENTlAL
INPUTS
TOPVIEW
Order Number DS55~OJ. DS5520AJ. DS5521J.
DS7520J. DS7520AJ. DS7521J. DS7520N
DS7520AN
DS7521N
or
5-16
•
o
Cf)
U'I
055520/057520, 055520A/057520A and 055521/057521
AC test circuit (1)
o
.......
o
STROlE
INPUT
DlffEAENTIAl
INPUT
U'I
N
v'.
~
~v
U'I
N
o
o
Cf)
"---""1
P---::.::1~Io--,....--~f!:"'-""_+-o~UTPUT
1
1
1
1
U'I
U'I
N
"'-+_-+-ogUT,uT
):>-,-,'
o
~
o
~
U'I
*Including jig and probe.
N
o
»
III
CD
voltage waveforms (1)
:::!.
CD
rod
~~
.-j
---
m~
IlIHERENTIAL
~~
N~
~10l
'''''~'
.:
'''''''''''~'''''-~
1.W I
\
I
I
A----i
I
t---~ ~I
...'
IV
'---~---"
~"
Uv.$V'
I
E-----;
I
~.....,j
r--f
I
!J.v
"~"
~
I!
I I
I
I
OtJT,ijTO
1.5\1
14---3000.- _~
III
ISV
1.5V
I
1.5\1
I
I
I
1
1
I
I
r--
1
1
OUTPUT0----r\
i ~~_l
:~I.sv
:~uv
c~ ~I
I
----1
:
~D
G~
~:
I
~H
--l
1. Pulse generator cbaracteristics:
ZOUT =50H, t, '"11 =15 2.4 V at --400"A. For max VTH, logic output is < OAV at 16 rnA.
5-18
c
CJ)
UI
UI
055522/057522, 055522A/057522A and 055523/057523
N
~
C
schematic diagram
~
connection diagram
UI
N
o
Dual·1 n-Line Package
C
CJ)
UI
UI
N
o
~
c
~
UI
N
c•• ,~~"t;~
OIHfREILTIAt
IN'UTA
AfffRENCE
DlfHRENTlAt
INPUT
IN'UT.
o
l>
TOP VIEW
Order Number OS5522J, OS5522AJ, OS5523J,
OS7522J, OS7522AJ, OS7523J, OS7522N,
OS7522AN or OS7523N
AC test circuit
DiffERENTIAL
I'~T
. - - - - - -....-e V"SII
I"... . . .""
n,f •• nUIIING
voltage waveforms
at ..v
2O.-v
20 no'"
~~
I
------~
14_
DlfHIIUITtAl'
IN'UT
...-.j
IOh,
1
I
j
t--
t----lllCl~l_____1
...'
I
I
0\1
_ _ _ _ _ _ _ _ _ 311
~uv
L:::\-~;-----~
: - ~~ .. - ~ov
STIlO.fl.'UT--.J! ....
I-rHO"';~
--1
f:
' . . . -.;;::;-~ . . "-
1011..
to--
l, Propa9lltion delaVs:
~~"
~
,~---J ~":
r'--.J ;'
..""",..J.
!
all
j
r'-' :- ':
UV
11
UV
Ult
_
:
:I
I
--i
_
,I
UII
1. One strobe is grounded when the other side is being tested.
2. Pulse generator characteristics:
ZOUT" SOn, I," 1," 15 ±5 ns, PRR" 1 MHz
Hit
"
ISII
A'" Ditferelltial input to logical "0" output
B" Differential input to logical "1" output
C " Strobe input to logical "0" ')utput
0" Strobe input to logical "1" output
£ '" Gate input to logical "t" output
F '" Gate input to Ingical. "0" output
lfiV
LOGIC
OUTPUT
5~ 19
g;
~.
~
III.
OS5524/0S7524. OS5524AiOS7524A and OS5525/0S7525
electrical characteristics
DS5524/DS5524A, DS5525:
DS7524/DS7524A, DS7525:
Thefollowingapplyfor-55°C~TA ~ +125°C
The following apply for O°C ~ T A ~ +70°C
PARAMETER
V TH
CONDITIONS
Differential Input Threshold
Voltage
VREF=15mV
Vee = ±5.0V
(Note 4)
V AEF = 40""V
'SIAS
Differential and Reference
Input Bias Current
los
Differential Input Offset
V ee
~
±5.25V,
Vee = ±5.25V
V'N = OV
MIN
TYP
055524/057524
11
15
19
mV
055524A/OS7524A
13
15
17
mV
MAX
UNITS
OS5525/0S7525
8
15
22
mV
OS5524/0S7524
36
40
44
mV
OS5524A/OS7524A
38
40
42
mV
OS5525/0S7525
33
40
47
mV
OS5524/0S5524A, OS5525
30
100
!J.A
OS7524/0S7524A,OS7525
30
75
!J.A
0.5
VO'FF = OV, V'N = OV
!J.A
Current
V'H
Logical "1" Input Voltage
I'H
logical "1" Input Current
Strobe, Gate Inputs
V'L
Logical "0" Input Voltage
I'L
Logical "0" Input Current,
2
Vee = ±5.25V
V'N - 5.5V
Vee = ±5.25V,
V
5
V'N = 2AV
.
40
1
-1
V'N = OAV
!J.A
mA
0.8
V
-1.6
rnA
-1.5
V
3.5
mA
St,robe, Gate Inputs
Veo
Input Clamp Voltage
I'N = -12 mA
V OH
Logical "1" Output Voltage
Vee = ±4.75V, 10 =-400iJ.A
2.4
3.9
Ise
Output Short Circuit Current
Vee = ±5.25V, Vo =OV
2.1
2.8
= 16mA
V
VOL
Logical "0" Output Voltage
Vee = ±4.75V, 10
0.25
0.4
V
Icc+
v,+ Supply Current
Vee = ±5.25V
29
40
mA
lee-
V
Supply Current
Vee = ±5.25V
-13
-18
mA
TYP
MAX
switching characteristics
The following apply for T A = 2SoC, V+ = 5.0V, V-=-5.0V
PARAMETER
tPdl
Differential Input to
CONDITIONS
MIN
UNITS
AC Test Circuit
20
40
ns
AC Test Circuit
10
30
ns
logical "1" Output
tPdl
Strobe Input to
logical "1" Output
tPdO
Differential Input to
Vee
= ±5.0V,
AC Test Circuit
28
ns
20
ns
10
ns
5
ns
200
ns
Logical "0" Output
'PdO
Strobe Input to
AC Test Circuit
Logical "0" Output
tDR
Differential Input Overload
Recovery Time
teMA
Common-Mode Input Overload
Recovery Time
tey
Minimum Cycle Time
V eM
AC Common-Mode Input
±2.5
Pulse
V
Firing Voltage
Note 1: For O°C ::; TA :::; +70°C operation, electrical characteristics for OS5524/0S5524A and OS5525 are guaranteed the same as OS7524/
OS7524A and OS7525 respectively.
Note 2: Positive current' is defined as current into the referenced pin.
Note 3: Pin 1 to have;::: 100 pF capacitor connected to ground.
Note 4: For min VTH, logic output is < 0.4V at 16 rnA. For max VTH, logic output is
5-20
> 2.4V at -400!J.A.
c
CJ)
UI
UI
N
055524/057524, 055524A/057524A and 055525/057525
~
schematic diagram
C
~
connection diagram
UI
N
o
Dual-In-Line Package
v·
STROlE
ouTPUT
A
A
OUTPUT STROle
B
I
1110
CONN
C
CJ)
UI
UI
N
o
~
c
.~
-
~
Ct"T
+
~
DIFF£AUHlAl
IIEHREIIIC[
INPUT"
IIIPut
UI
N
o
:t>
'----"'
DiffERENTIAL
IN.UTI
TOPVIEW
III
(1)
::l.
Order Number DS5524J, DS5524AJ, DS5525J,
DS7524J, DS7524AJ, DS7525J, DS7524N,
DS7524AN or DS7525N
AC test circuit
(1)
III
voltage waveforms
DiffERENTIAL
INPUT
STRODE
INPUT
DlffEflEIIITIAL
r--o ~~~~~T
1..0-..---=='+-11"' ,::>---L..1- "C;"'1'
["1
I
I
I
1
1
1
J
L-I-G'
-r
,oo"r 1
...
-
v-- -sv
l$pFINtlIJDING
JJIGAN(lPIHlBE
~2amv
I~
--..j
,
100 ...
~--- .. "'v
i'- ov
f'-----u-..Ji
~
~JlDn.---l
I
""""'''~~''
~~300"~~
A--J
I--~
--I
100 ...
f4-
GV
t--D
'
~~
lOGIC
OUTPUT
U.V
Ii-a
c-J f--- I
1.5V
1. Pulse generator characteristics:
ZOUT '" 50n, t, '" tl '" 15 ±5 liS, PRR
ISV
1.5Y
1 MHz
2. Propagation delays:
A'" Differential input to logical "1" output
B'" Differential input to logical "D"output
C=Strobeinputtological"l"otltput
D=Strobeinputtological "0" output
5-21
(I)
Q)
'C
i
«
o
N
Ln
055528/057528. 055528A/057528A and 055529/057529·
electrical characteristics
DS5528/DS5528A, DS5529:
DS75281DS7528A, DS7529:
~
Q
<
o
The following apply for -55°C::; T A ::; +125°e
The following apply for oOe::; T A::; +70o e
PARAMETER
V TH
V AEF
Voltage
Vee
N
Ln
Ln
o•
N
~
Q
~
N
Ln
Ln
Ul
Q
= 15 mV
= ±5.0V
(Note 5)
V REF =40mV
Ul
Q
ISlAS
Differential and Reference
Input BiasCurrent
los
MIN
TYP
DS5528/DS7528
11
15
19
mV
DS5528A1DS7528A
13
15
17
mV
CONDITIONS
Differential Input Threshold
Differential Input Offset
V ce
= ±5.25V,
V'N
Vee
= ±5.25V
V01FF
= ±5.25V
V'N = 2.4V
V'N - 5.5V
= OV
;::
MAX
UNITS
DS5529/DS7529
8
15
22
mV
DS5528/DS7528
36
40
44
mV
DS5528A/DS7528A
38
40
42
mV
DS5529/DS7529
33
40
47
mV
DS5528/DS5528A; DS5529
30
100
p.A
DS7528/DS7528A, DS7529
30
75
p.A
0.5
OV. V'N = OV
p.A
Current
V'H
Logical "1" Input Voltage
I'H
Logical "1" Input Cur~ent
Strobe, Gate Inputs
V'L
Logical "0" Input Voltage
I'L
Logical "0" Input Current,
V
2
Vee
Vee
I
= ±5.25V,
V'N
5
-1
= O.4V
p.A
40
1
mA
0.8
V
-1.6
mA
Strobe, Gate Inputs
-1.5
= -12 mA
Veo
Input Clamp Voltage
I'N
V OH
Logical "1" Output Voltage
Vee
= ±4.75V,
10
Ise
Output Short Circuit Current
Vee
= ±5.25V,
Va
VOL
logical "0" Output Voltage
Vee
= ±4.75V,
10
Icc+
V+ Supply Current
Vee
Icc-
V
Vee
Supply Current
= -400p.A
= OV
2.4
3.9
-2.1
-2.8
= 16mA
V
V
-3.5
mA
V
0.25
0.4
= ±5.25V
29
40
mA
= ±5.25V
-13
-18
mA
switching characteristics
The following apply for T A
= 25°C,
V+
= 5.0V,
PARAMETER
tpd1
Differential Input to
V-
= -5.0V
TYP
MIN
CONDITIONS
AC Test Circuit
MAX
UNITS
20
40
n,
10
30
n,
Logical "1" Output
tpd,
Strobe Input to
AC Test Circuit
\
Logical "1" Output
tpdO
Differential Input to
Vee
-= ±5.0V, AC Test Circuit
28
n,
20
n,
10
n,
5
n,
200
ns
Logical "0" Output
tpdO
,Strobe Input to
AC Test Circuit
Logical "0" Output
tOA
Differential Input Overload
Recovery Time
teMA
Common-Mode Input Overload
Recovery "Time
tey
Minimum Cycle Time
V eM
AC Common-Mode Input
±2.5
Pulse
Firing Voltage
Not. 1: For O°C :s; TA <;;;'+70°C operation, electrical characteristics for DS5528/0S5528A and DS5529 are guaranteed the same as DS75281
DS7528A and OS7529 respectively.
Note 2: Positive current is defined as current into the referenced pin.
Note 3: Pin 1 to have ~ 100 pF capacitor connectedto ground.
Note 4: Each test point to have $. 15 pF capacitive load to ground.
Not. 5: For min VTH, logic output is < 0.4V at 16 rnA. For max VTH, logic output is
5-22
> 2.4V at -400I'A.
V
o
f/)
U1
U1
055528/057528, 055528A/057528A and 055529/0S7529
N
~
o
~N
connection diagram
schematic diagram
o
Dual-In-Line Package
,.o-----------.-----.---------~
.1----+-----+-0,,,'
v+
rEST
'0116'
STR08E
II.
A
OUTPUT OUTPUT STROlE
A
B
o
f/)
TEST
PDIIIIT
•
B
U1
U1
N
l
o
~
IIHERfNCE{
'~PUT
o
f/)
TEST :IlINT
-.J
U1
. . .I
o-----+------++-==:j::~-----
N
o
t.~,
DlffUIEUIAl I
INPUT A ~
~
~
~
DtFFERENTI"L
(K'UTA
IIEHRENC£
tHPUT
DiffERENTIAL
'M.utl
»
(/I
...
CD
TOPVIEW
CD'
(/I
Order Number DS5528J, DS5528AJ, DS5529J,
DS7528J,DS7528AJ,DS7529J,DS7528N,
DS7528AN or DS7529N
DIffERENTIAL
INPUT8
r
I
1
AC test circuit
voltage waveforms
~11lmv
t~
IllFHA{NTIAl
~
,
100 ...
~--~"'v
f'-------..tr--1i
~,-.
I
STRDIE'' 'UT ~
i'- ov
f---300n'----1
~,-~:::--------l\l
~~lOO"'~~~···
I
I
.. ~ I--~ f-- B
...............
c--l
~ov
'OO"'~
~--I
r---
0
I~'
~
lOGIC
OUTPUT
I§V
'.511
I.W
UV
1. Pulse generator characteristics;
ZOUT '" 50U, t, '" 1, '" lS i51ls. PRR" 1 MHz
2. Propagation delays:
A '" Differential input to logical "1" output
B '" Differential input to loyical"O" lJUlput
C '" Strobe input 1a logical "1" output
0" Strobe input to logical "0" output
5-23
OS5534/0S7534, OS5534A/OS7534A and OS5535/0S7535
electrical characteristics
OS5534/0S5534A, OS5535:
OS75341DS7534A, OS7535:
The
The
following
following
apply
apply
for
for
PARAMETER
V TH
-55°C::::: T A ::::: +125°C
O°C::::: T A::::: +70°C
CONDITIONS
MIN
TYP
DS5534/DS7534
11
15
19
mV
DS5534A/DS7534A
13
15
17
mV
Vee = ±5.0V
DS5535/DS7535
8
15
22
mV
INote 4)
DS5534/DS7534
36
40
44
mV
DS5534A/DS7534A
38
40
42
mV
DS5535/DS7535
33
40
47
mV
Differential Input Thre,shold
Voltage
V REF
= 15 mV
V REF =40mV
'SIAS
Differential and Reference
I [lput Bias Current
los
Differential Input Offset
UN1TS
DS5534/DS5534A. DS5535
30
100
pA
DS7534/DS7534A. DS7535
30
75
JJ.A
Vee = ±5_25V,
VIN
Vec =.±5.25V
V 01FF =OV, Y'N = OV
= OV
,.MAX
0.5
JJ.A
Current
V ,H
Logi,~a,1
J1H
Logical "1" Input Current
Strobe, Gate Inputs
Logical "0" Input Voltage
I'L
Logical "0',' Input Current,
Strobe, Gate
Vee = ±5.25V
5
Y'N = 2.4V
VIN -
V ,L
V
2
"1" Input Voltage
40
1
5.5V
0.8.
Vee = ±5.25V.
-1
Y'N = OAV
JJ.A
rnA
V
-1.6
rnA
-1.5
V
Inp~ts
Veo
Input Clamp Voltage
'iN =-12rnA
VOL
Log1cal"O" Output Voltage
Vee = ±4.75V. 10 = 16 rnA
I CEX
Output Leakage Current
Va = 5.25V
Icc+
v+ 'Supply Current
Vee = ±5.25V
Icc-
V
Vee = ±5.25V
TYP
MAX
Supply Current
..
0.25
0.4
V
250
JJ.A
28
38
mA
-13
-18
mA
switching characteristics
The
following
apply
for
TA ~ 25° C, V+ ~ 5.0V, V-
PARAMETER
tpdl
~
-5.0V
CONDITIONS
Differential Input to
MIN
UNITS
AC Test Circuit
24
ns
AC Test Circwit
16
ns
Vee
20
40
ns
10
30
ns
Logical "1" Output
tpd1
Strobe Input to
Logic'al "1" Output
tpdO
Differential Input to
=:
±5.0V, AC Test Circuit
Logical "0" Output
tpdO
Strobe Input to
AC Test Circuit
Logical "0" Output
tOR
Differential Input Overload
10
ns
5
ns
200
ns
±2.5
V
Recovery, Time
tCMA
Common-Mode Input Overload
Recovery Time
tey
Minimum Cycle Time
VCM
AC Common-Mode Input
Pulse
Firing Voltage
s:
s:
Note 1: For DoC
TA
+70°C operation. electrical characteristics for 085534/085534A and 085535 are guaranteed the same as 0575341
D87534A and 087535. respectively.
Note 2: Positive current is defined as current into the referenced pin.
Note 3: Pin 1 to have?::: 100 pF capacitor connected to ground.
Note 4: For min VTH, logie output is
5·24
< 250pA at 5.25V. For max
VTH, logic output is
< 0.4V at 20 rnA.
c
C/)
U1
U1
OS5534/0S7534, OS5534A/OS7534A and OS5535/0S7535
N
o
.......
c
schematic diagram
~
connection diagram
o
" <>------.,-.--,-----,
..:I--,-----t""" <.n
N
Dual-In-Line Package
v'
STROlE OUTPUT
A
A
OUTPUT STROlE
•
I
C
C/)
110
COIIIIII
U1
U1
(
N
o
~
AHERENUj
IN'UT]
l-
cC/)
......
U1
N
-
CII~.6.L
IN'UTA
stROlE A
+
~
IIE~::::Cf
IIilPUfA
OlfflllUlTIAllf
o
~
~
OIFHRlNTIA~
INPUT.
l£::!.
TOP VIEW
CD
Order Number DS5534J, DS5534AJ, DS5535J,
DS7534J, DS7534AJ, DS7535J, DS7534N,
DS7534AN or DS7535N
o----+---t+--+-+_'
AC test circuit
1/1
voltage waveforms
ST"OIl
tH'Ul
lhflNCLIlOHIIG
IJ'GAND.AII'E
1. Pulse geneTatorcharacteristics:
ZOUT" 50!l, t,::: tl '" 15'5 us, PAR" 1 MHz
2. Propagation delays;
A" Differential input to logical "0" output
B" Differential input to logical "1" output
C = Strobe input to logical "0" output
o " Strobe input to logical "1" output
5-25
055538/057538. 055538A/057538A.,. and 055539/057539
',,,.
electrical characteristics
Differential Input Threshold
Voltage
V REF == 15 mV
Vee = ±5.0V
. (Note 5)
V REF =40mV
Differential and Reference
Input Bias Current
los
Differential Input 9ffset
MAX
UNITS
MIt-!
TVP
OS5538/0S7538
11
15
19
mV
OS5538A/OS7538A
13
15
17
mV
CONDITIONS
PA!lAI\IIETER
'BIAS
' t ,.
"
The following apply for -55°C -:; T A -:; +125°C
The following apply for O°C -:; T A -:; +70or;
OS5538/0S5538A,OS5539:
OS7538/0S7538A, OS7539:
V TH
".
OS5539/0S7539
8
15
22
mV
DS5538/0S7538
36
40
44
mV
OS5538A10S7538A
38
40
42
mV
OS5539/0S7539
33
40
47
mV
OS5538/0S5538A, OS5539
30
100
/lA
DS7538jOS7538A, OS7539
30
75
/lA
Vee = ±5,25V,
V ,N = OV
Vee = ±5,25V
V 01FF = av, Y'N = OV
Vee = ±5.25V
Y'N = 2AV
Y,N - 5,5V
Vee = ±5.25V,
Y'N = OAV
0,5
/lA
Curre~t
V ,H
~ogical "1" Input Voltage
I'H
Logical "1" Input Current
Strobe, Gate Inputs
V ,L
I'L
5
40
1
0.8
V
-1
-1.6
mA
-1.5
V
.
Logical "0" Input Voltage
Logic~1
V
2
',:0" Inpu,l Current,
/lA
mA
Strobe: Gate 'Inputs
Veo
Input Clamp Voltage
VOL
logical "0" Output Voltage
Vee = ±4.75V, 10 = 16 mA
'CEX
Output leakage Current(
Vo
Icc+
. V+ Supply Current
Icc-
V- Supply Current
'I'N =-12mA
0,25
= 5,25V
Vee = ±5,25V
Vee = ±5,25V
0.4
V
250
/lA
28
38
mA
-13
18
mA
,
switching characteristics
The following apply for T A = 25°C, V+ = 5,QV, V- =-5.0V
PARAMETER
tpd1
CONDITIONS
Differerytial Input to
MIN
TVP
MAX
UNITS
AC Test Circuit
24
ns
AC'Test Circuit
16
ns
Vcc = ±5.0V, AC Test Circuit
20
40.
ns
10
30
ns
Logical "I" Output
tpd,
Strobe Input to
Logical "I" Output
tpdO
Differential Input to
Logical "0" Output
tpdO
Strobe Input to
AC Test Circuit
:
Logical "0" Outpu't
tOR
Differential Input Overload
10
ns
5
ns
200
ns
±2,5
V
Recovery Time
tCMR
Comrnpn-Mode Input Overload
I
Recovery Ti me; ,
tey
Minimum Cycle Time
V CM
AC Common-Mode Input'
Pulse
Firing Voltage
Note 1: For O°C·~ TA ~+70°C oPeration, electrical characteristics for DS5538/0S5538A arid DS5539 are guaranteed the same as OS75381
OS7538A and OS7539 respectively,
Note 2: Positive current is defined as current into the referenced pin.
Note 3: Pin 1 to have;::: 100 pF capacitor connected to ground.
Note 4: Each test point to have
~
15 pF capacitive load to ground,
. Note 5: For min VTH, logic output is < 250/lA at 5.25V, For max VTH, logic output is < 0,4V at 20 mAo
5·26
cC/)
c.n
c.n
OS5538/0S7538, OS5538A10S7538A and OS5539/0S7539
N
g
C
~
c.n
connection diagram
schematic diagram
Dual~ln-line
"~----------.---~~--------,
J-----f--------~~"
v·
..
TUT
POUlT
STR08E
A
A
OUTPUT OUTPUT STROlE
A
~
Package
•
•
C
IUT
'OIlU
C/)
I
c.n
c.n
N
o
('
R!fERUln)
I"""T
1
~
l'
c
~
r
c.~.
INPUT A
'-. . . . . . .
OIH~R(NTIAl
INPUT A
OlfHRElITlAtJ
1
c.n
N
o
~
1>
TOP VIEW
(1j
INPUT
C/I
::::!,
l
(1j
Order Number DS5538J, DS5538AJ, DS5539J,
DS7538J, DS7538AJ, DS7539J, DS7538N,
DS7538AN or DS7539N
voltage waveforms
AC test circuit
OlffUltNTIAt
IN,uT
STROlE
INPUT
, - - -....--0 V<·sv
OlffERENTIAl
~20"'V
IN~
-...j
,.f"
C/I
~ _ _ 4D"\1
l'-----n--I: .
.
loa ...
t----
.SVIII
~
1\,.511
STRI.II(I"'"T
~3Do...----t-----'1
I
----1 1'-1
f\-
av
I----JlIILn.----------.j
~:\I---JV
~ .~~~
~
---i1DGn.f.oe=-
ou~ .. ~~ ..
~1~\1
av
---I f--o
r.-:--
~15\1
1. Pulse generator chalactemtics:
lOUT'" 50U,I, '" II eo 15 '5ns, PRR eo 1 MHz
2.Propagallondelays:
Aeo Differential input to logical "0" outpul
BeoOifferentialinputtoloyical''l''olltput
CeoStrobetnpultological"O"olltput
o = Strobe inpul to logical"," oUIPut
5-27
:B
.;:
Q)
en
«o
guaranteed performance characteristics
N
~
Q
<
o
Differential I nput Threshold
Voltage
N
&I)
>"
40
~
!
~
32
o
'">-
24
~
~
N
'"
DS5521,US552l,
OS5525,055529
OS$515,OS5539
=
g~:~:: g~::~~:
D55»4.055538
...~
Q
()
15
N
20
25
30
35
40
Rj;FERENCE VOLTAGE (mV)
In
In
o
Q
typical performance characteristics
Transfer Characteristics
Transfer Characteristics
5.0
:~~:: g~:~~: ~:~~ g~;~~ I Q OUTPUT ONLY'
1I$&528,OS5529, 051528.081529
..'"
~
V··5V
V-··5V
W
~
eo'"
'"'"
STROBE;:.:r
-!-
r- REFE~E'CE - -
~2S",V
2.0
VOlTAGE
REFERENCE
VOLTAGE
~l5mV
-limV
1.0
I
'"~
....'">-
-
~
g
I
3.0
REFf;REIliCE
v~~li5A!;t--+-?~I--l
"jfi",V
Q'
..'"
~
...~
'">=~
-'
~
C
..'"
.s
'"
I I I
I I I
'"g 15.2
v'= 5.0V
±5 ±10 ±15 ±20 ±25 ±30 ±3S ±40
±10 ±15 :!lO ±25 ±30 ±35 ±40
'">
~
...-'
'">=~
::
C
~
>~
::
'"ro
14.6
14A
.
~~E5~::CE VriGE
V- = -".OV
6.0
i
2T
l-
I
45
TA ('CI
85
125
"y+ f
-5.00
1.4
1.3
N
1.0
::;
!...
45
~
35
::::
1.2
II
~
;;;
V+= 5V
V-"'-5V
<
.
~
Q
1i,~A =2~~~,
10K
lOOK
1M
10M
-5.25
Differential Input Bias Current
50
1.1
~
19
REFERENCE VOLTAGE =ISmV
12 C
-sr'C ';I T
-4.75
55
i=
---- .:::
-(I4.7Sj
V- (VI
'"
-35
14.8
DIFFERENTIAL INPUT VOLTAGE (mY)
w
-
\r·=~.25~
15.0
Differential Input Frequency
Response
21
18
15.6
:t"
22
20
1~.8
~ 15A
:li
>-
-'
-35mV
1.0
Temperature Coefficient
.sw
'"'"
!:I
Rf:~b~~ r-- RE:~r~:~~ r -
2.0 -
DIFFERENTIAL INPUT VOLTAGE (mVI
;;:
2kUTPUltUP-
F:f.~~f:jt=f=!j
~,,,,·-
I""- .....
,....
Q.
0.3
t
ii:
V+"'Ii.2SV
N
21
"
!
19
+5
+45
15
fi
13
+125
+85
+5
-35
!"
26
i5
3'"
~
~
I ......
I
22
OlFF1ERfNJIALIN'UTVOLTAG!'OV
18
lI'oU511
1I-· 5·25V
1
.....
f
1
I I
1
~
t
1
ii:
I
+45
+45
26
]:
>
~
"z
;::
"
~
:f
"IE
DS552G,DSS6Z1,DS152D,DSl521
tOELAYSTO o OUTPUT ONLY)
OS5U4,DS5525,DS1524,OS7S2S
D5S52B,DS652B,DSJ528.DS752D
30
I I I
2B
,/
22
20
IL
I
I
22
~
5:f"
3B
.."
"IE
j I ]A
...-kt"'l
lB
-35
+5
!
>
~
"z
..
"~
~
IE
I I I
-
-
24
JO
--
22
20
18
26
rt
j
'l-iA'"
l,..1' I
24
!
22
..""~
..
20
>
;::
i1ELA YTO
.L I "O·O~'"
"1'
SEE AC rEST CIRCUIT I
-35
-3
45
TA (OC)
125
85
-35
36
34
!
1;1"
>
~
1/
L I
,/
--r
DELAY TO
"
"";::
V
~
:f
"IE
V
i--""
"a" OLiTPUr l
+45
+85
+125
OS5522, OS5523. OS7522, OS7523
SEj ATTliCUI,
32
30
DELAY TO "I" OUTPUT
+85
V
./
26
24
~
I
+--V
V
2B
~......
V
y
DELAY TO "0" OUTPU¥
22
~
20
+5
+45
Differential Input to Output
Propagation Delays
1/
sHIAtnhcIR~UIT
-'
+5
TA'(OC)
+125
-35
+5
Strobe to Output Propagation
Delays
'
Strobe to Output Propagation
Delays
,,~,~~~~;Ji
26
-1
-2
TA (OC)
I I I
28
>
-4
-35
DS5538, OS5539, OS7538, OS7539
30
!:;
I I I
34
+126
+85
en
Q
26
+45
OS5534, OS5535, OS7534, D57535
32
-,
- -
NEAIIIESUPLYCURRENT
OHAY TO "'" OUTPUT
Differential Input to
Output Propagation ~elays
34
-
.
.
~
w
I I I
TA IOe)
36
I
- -
08&520. 055521,DSl5211, D!J]5Z1
(OEtAY$TOQOUTPUTDNlV!
42
o
:z:-
~
50
>
U1
N
CD
:::So
CD
P'ropagation Dalays
!
o
~
+125
en
......
11-'_&'2511
16
46
+85
UPPlYCURREN~
-35
V
+45
rc)
AC Common-Mode Firing
Voltage
Differential Input to Output
DHAyITO.'·'" DUTPiJT
20
+5
TA
DIffERENTIAL INPUT 1I0LTAGE 'DV
REf ERENCE VOLTAGE· ZDmV STRDBEINPUTS-OV
1I··+5.l511
lB
+125
+85
I I I
24
-35
12
OHAYTO "O"OtlTPUT
26
+125
+85
I I I
24
Differential I nput to Output
Propagation Delays
32
(:
Supply Currents
TA (OC)
34
II;)
o
~:::::~~~:;~~::;::
I'{)SITIVE
14
I I
+5
-35
!"
>
NEGlTIVEluPPLJCURR1ENT
10
28
'"3
;::~::~~:u~~:TaAvGE, 20 mil
14
30
~•• DS55Z9,DS763'DSJ529
I I
I-
Po~er
oSS524,OS56U,oS1524.DS7525
r-
U1
15
TA lOCI
Power Supply Currents
POSITIVE SUPPLY
CURRENT
19
11
TA rC)
)....
o
en
U1
i5
a'"'">
17
11
-35
o
23
I-
V-=-5.25V
0.2
30
~
27
DIFFERENTIAL INPUT VOLTAGE' OV
0.1
!
Power Supply Currents
125
~
IE
lB
16
14
12
10
4B
OS552D,DS552I,DS15Z0,DS1521
(DElAYJTOQOUTPUTONLYl
DS5524,DS5626.D57&24,OS1525
05552I,05!i519.DSJ5ZI,DS1bZll
I I I
44
./
+"l'~""
~
36
"
~
32
IE
20
zQ
S~E
ACTEST CIRCUltT
~
...... 1'
~
28
24
16
~
• -35
40
>
1.---.....
DELAY TO "0" OUTPUT
I I I
I I I
!
12
+5
+85
+125
OS5520, DS5521, OS7520, OS7521
(O~LAYIS T~ Ii 0IUTPYT ONLY)
OE(AY ~O "\" O~TPUT
A
-
I-
-
tEE
Ac TEST CIRCVIT
DELAYTO "0" JUTP T
-35
I I
+5
V
./
+45
--
l-
+85
+125
TA (OC)
5-29
typical performance characteristics (cont.)
31
:!
>-
....
..::'"
.
~
Q
N
·
IE
l7
~~~~'T~~R~~~22, 087523 _ ~
23
:5
21
..
~..
::
V
~
19
15
:!
>-
23
I""-
085534, 085535, 087534, DS7535
085539, 085539, 087538, 087539
25
27
;:;
ill
OELAY TO "I" OUTPUT
I
I
'"
IE
OELAY TO "0" OUTPUT
O~LAJ
TO
"I" OUTPUT
19
',/
17
15
13
I'..
11
-35
rn
o
+6
+45
+85
t-
+125
-35
TA 'OC)
C>
N
-
29
.,..e
o
>-
..~
27
25
23
DELAY TO "0" OUTPUT
z
.'"
;::
21
::
19
c
"IE
OS5520, OS5521, OS7520, 087521
(GATE Q TO ii OUTPUT OELAY8'
SE~ AC rE8T C'R,CU'T
17
,
I---' V
V
V
18 ~+-~~_+~--hJ~+_~
14 !-=,:.;::.:.:..,:.::...,:...::;:.c:::;0t£f-+-+~
12 ~+-+-~~~-+-+~~
10
45
85
125
-35
+5
+45
TA ,OC)
TA 'OC)
Gate to Output Propagation
Delays
21
19
t7
:!
17
....~
..::
'15
>-
j
j
~
'" ./
,/
'"
IE
13
085222, 085523, 087522, DS7523
SE~ AC ,TESf C',CUlf '
V
p.-
..;....OELAY TO "0" JUTJUT
11
OELAVTO "I" OUTPUT
OELAY TO "I" OUTPUT
15
+5
+45
+95
-35
+125
+5
TA 'OC)
typical applications
I
1
1
~~f--t~,-L~
:
L _______________ -'
I
I
MDRIIIun
Large Memory Systam with Sectored Cora Planas
p-30
I--l-......"+-
OELAYTOT~
"O"OUTPUT'
Delays
U)
r-----------------__~
18
1/IL f-
Gate to Output Propagation
if)
if)
22
20
1/
SEEAC
T~ST ~IRCrIT
i-""
11
if)
Gate to Output Propagation
Delays
Strobe to Output
Propagation Delays
Strobe to Output Propagation
Delays
+95
+125'
+15
+125
o
en
U1
U1
typical applications (cont.)
II.)
o
"-
o
!!l
U1
,--,
I
I
__--,------1
I
II.)
o
I
I
8111
I
I
o
1-----1
:
I
--4
en
U'I
I
6111
I
U'I
I
I
I
r------1
I
I
I
1
BI11
I
I
I
I
I
__---:-----1
II.)
o
~
oen
f---..,
1
"""
U'I
1
BIl4
N
o
-....,
I
L __ -.l
»
III
CD
:::l.
CD
Small Memory System
III
HHIINAL
MEMORY DATA
IIEGISHII
r--l
I
I
!--OIlUA
I
I
L __ J
Large Memory System
5-31
<0
o
00
00
~
CJ)
c
........
<0
o
Sense Amplifiers
NAll0NAL
00
~
OS7802/0S8802, OS7806/0S8806
C
high speed MOS to TTL level converters
N
o
~
CJ)
C
........
N
o
00
.....
(IJ
C
general descriptron
features
The OS7802/0S8802, OS78061OS8806 are high
speed MOS to TTL level converters. These circuits
act as an interface level converter between MOS
and TTL logic devices. It consists of two 1-input
converters with common strobe input to i~hibit
"0" entry when strobe is high. It allows parallel
entry when strobe is low _and the internal latch
is preset by the common preset input. TR 1STATE® output logic is implemented in this
circuit to facilitate high speed time sharing of
decoder-drivers, fast random-access (or sequential)
memory arrays, etc.
•
Very low output impedance ability
•
High impedance output state which allows
marw outputs -to be connected lOa common
bus -line
•
Average power dissipation 110 mW per converter
logic and connection diagrams
",
jCUARENT INPUT)
OUTPUT A
IN,
(CURRENT INPUT)
OUTPUT B
STROiH:
PRESET
Dual-In-Line Package
Dual-Incline and Flat Package
15
S'fi'fOBf
Vee
15
NC
ITFm1fE
Vee
NO
13
OUTPUT A
OUTPUT B
q>UTPUT A
13
087802/0S8802
11
NC
12
PRESET
NC
GND -
"
,
NC.
"
j
GND
INPUT B
INPUT A
INPUT S
NC
081806/D88806
GND
GNO
DISABLE
OISABlE
GND
INPUT A
OUTPUT B
OND
OND
GNO
TOP VIEW
TOP VIEW
Order Number DS7802J, DS8802J
- Or DS8802N
5-32
Order Number DS780GJ, DS8806J,
DS8806N or DS7806W
high drive
absolute maximum ratings
(Note
o
~o
operating conditions
11
N
MIN
Supply Voltage
Input Voltage
7.0V
5.5V
Output Voltage
5.5V
Storage Temperature Range
Supply Voltage (VCCI
OS7802, 057806
058802, 058806
Temperature IT A)
057802, 057806
058802, 058806
-B5"C to 150'C
300"C
Lead Temperature (Soldering, 10 seconds)
electrical characteristics
(Notes 2 and
Logical "'" I nput Current
V
V
o
(f)
4.5
4.75
-55
0
CO
CO
o
·'c
+125
+70
N
C
o
CO
o0)
CONDITIONS
MIN
TYP
MAX
500
IINA,IINB
Logical "0" I nput Current
Vee
V ,H
Logical "1" Input Voltage
Strobe, Preset, Disable, Vee = Min
V,L
Logical "0" Input Voltage
Strobe, Preset, Disable, Vee
V OH
Logical "1" Output Voltage
Vee = Min, lOUT = -1.5 mA
VbL
Logical "0" Output Voltage
Vee = Min, lOUT = 16 mA
10
TRI-STATE Output Current
I'H
Logical "1" Input Current
Min
Vee = Max
0.8
V
o0)
204
V
V
/lA
Va = OAV
--40
/lA
2_4V
I,L
Logical "0" I nput Current
Vee ~ Max, Y'N = OAV
Supply Current
Vee = Max, V'NID'SABLE) ~ 2V, Other Inputs ~ t/iV
V eD
Input Clamp Voltage
Vee
Ise
Output Short Circuit Current
Vee = Max, Vo = OV,
(Note 4)
/lA
40
lee
~
200
Va = 2AV
~
I 057802, 057806
I 058802, DS8806
40
/lA
1.0
mA
-1.6
mA
40
mA
-1.5
V
-20
-70
rnA
-18
-70
mA
-12 mA
switching characteristics
MAX
UNITS
5.0V (See Waveforms). T A ~ 25'C
CONDITIONS
17
25
ns
V ee ~ 5.0V (See Waveforms). T A ~ 25'C
22
32
ns
5.0V (See·ae Test Circuit), TA = 25°C
7.0
11
ns
V ee ~ 5.0V (See ac Test Circuit). T A ~ 25'C
17
25
ns
Vee = 5.0V (See ac Test Circuit). T A ~ 25'C
9.0
14
ns
Vee = 5.0V (See ac Test Circuit). TA ~ 25'C
13.5
16
ns
PARAMETER
t",
Propagation Delay to a Logical "0" From
Vee
~
MIN
TYP
Strobe to Output
t dP
Propagation Delay to a Logical "1" From
Preset to Output
t'H
Delay From Disable Input to High Impedance
Vee
~
State (From Logical "1" Level)
IoH
Oelay From Disable Input to, High Impedance
State (From Logical "0" Level)
t H,
Delay From Disable Input to Logical "1"
Level (From High Impedance State)
tHO
Delay From Disable Input to Logical "0"
Level (From High Impedance State)
o
(f)
CO
CO
V
= Min
.......
/lA
2.0
Y'N - 5_5V
Min, liN
UNITS
004
V ,N
Vee = Max
~
5.5
5.25
.......
31
Vee = Min
=
UNITS
~
PARAMETER
'INA.IINB
MAX
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified min/max limits apply across the -5SoC to +12SoC temperature range for the OS7802, OS7806 and across the
O'C to +70'C range for the 058802, OS8806. All typicals are given for V CC = S.OV, T A = 25'C.
Note 3: All currents into device pins shown as positive. out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.
5-33
w=t sw =20nsmax
ts"'20ns,ma1l.
t,=t,-+--i
II
T"II
I
I
.".
I I'
WAVE'ORMS
[
ISEEIHIT£1)
I
I
I
I
I
I
l ____ ~:I~:'_ ____ J
LOAD CIRCUIT FOR
;-____ _________________ v_.
------------..,
TYPtCAL INPUT
VOLTADE
R,
lNJD&4 '.311&41.3084
T."."
I I
LOAD CIRCUIT FOR
U;;;~;~!J
switching time waveforms
lN3014
~
••rUTA
-----------""',
IM'UlSl,C,OAQ
1r-----------------------ylJlIfn
U\/
-------------·v..
...'~..---------v."""
mtCALO."ur (
VOLTAGE
WAVEfORMS
'~v __.---------v.....
--------------------t--...... ------______ v""""
c"
__
Uv
~
I
_______________
t.,.
.
v~.
,
A Input to Outputs
:=z~~;z:~:-------------~,
INPUTS A,', C, AND 0
------------.------
V'MIlI
""'-
'-----------------------------VINIDI
----
=~:=;:=-----------------------~
.......T.
~v
--:--
I
OUTPUT,
V'NIDI
r
I
-----\1.m
'''''--'t
r----------~OI,lTI1I
I.5V
:=~:;::::---------------------+--./.----------VOU1'1IN
DMI44IIDM1441---------------------t---,,----------VOUTI11
-1.5¥
OUTPUT,
' -_ _ _ _ _ v_..
'....
RBI Input to Outputs
Nota 1: The trulll tabh glnll'ltor and pul. pnll'ltar IIpI the taUowinl c....nchristics:
VOUTtll :2;2AY. YOUTIOI ::;;O.4V. 'l,lmlt,S10ns,andPRR = 1.0 MHz.
No1l2: ...11 B, C. and D tnnsftions occur simultaneously witb or pfior to input A
tranliticmL RBI "'UV.
Note 3: ~ ildudesprobtlnd jig .,..a.I.
6·7
~
Display Drivers
NAnONAL
DM541411DM74141
BCD to decimal decoder/driver
general description
The DM54141/DM74141 is a second-generation
BCD to de9imal decoder designed specifically to
drive cold cathode indicator, tubes. This decoder
demonstrates an improved capability 'to minimize
switching transients in order to maintain a stable
display.
Full decoding is provided for all possible input
states. For binary inputs 10 through 15, all the
outputs are off. Therefore the DM 5414 110M 74141,
combined with a minimum of external circuitry,
can use these invalid codes in blanking leadingandlor trailing-edge zeros in a display as shown in
the typical application data. The. ten high-performance NPN output transistors have a maximum
reverse current of 50IlA, at 55V.
Low-forward-impedance diodes are also provided
for each input to clamp negative-voltage transitions
logic diagram
in order to minimize transmission-line effects_
Power dissipation is typically 55 mW, which is
about one-half the power requirement of earlier
designs.
features
• Drives cold cathode numeric indicator tubes
directly
• 50llA maxdeakage current at 55V
•
Low power dissipation of 55 mW typ
•
Fully decoded inputs ensure all outputs off
for invalid codes
• Input clamp diodes for minimizing transmission
line effects
connection diagram
Dual-I n-Line and Flat Package
A (]I
ounuTS
OUTPUTS
15
B (6)
,
~~Vcc8CZ
OUTpUTS
INPUTS
~ OUTPUT
TOP VIEW
c
(7)
O.der Number DM54141J o. DM74141J
Order Number. DM74141N
Order Number DM54141W or DM74141W
D~~~I--~--------~==~jP-----4-----t-i
6-8
absolute maximum ratings
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
-65°e
Lead Temperature (Soldering, 10 seconds)
electrical characteristics
to
Supply Voltage. Vee
DM74141
DM54141
7.0V
5.5V
60V
+150o e
3000 e
Temperature, T A
DM74141
DM54141
Logical "1" Input Voltage
I'H
Logical "1" Input Current
MIN
MAX
UNITS
4.75
4.5
5.25
5.5
V
V
+70
+125
°e
°e
MAX
UNITS
0
-55
(Notes 2 and 3)
CONDITIONS
PARAMETER
V ,H
operating conditions
(Note 1)
MIN
TYP
V
2.0
Vee = Min
V ,H = 5.5V
Vee = Max
V ,H = 2.4V
V ,L
Logical "0" Input Voltage
I,L
Logical "0" I nput Current
V eD
Input Clamp Voltage
Vee = Min, leo = -12 mA
V OH
Logical "1" Output Voltage
Vee = Max, 10H = 0.5 mA
10H
Logical "1" Output Current
It AB. Input
C. or D Input
Vee = Min
I A Input
Vee = Max, V ,L = O.4V
Vee = Max
I B, C, or D Input
0.1
mA
40
/lA
80
/lA
0.8
V
-1.6
mA
-3.2
mA
-.1.5
V
V
60
Vo = 55V
50
/lA
Vo = 30V Input States 10-15
5.0
/lA
VOL
Logical "0" Output Voltage
Vee = Min, 10L = 7.0 mA
lee
Supply Current
Vee = M.x. All Inputs Gnd, All Outputs Open
11
2.5
V
25
mA
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Exc~pt for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified minimax limits apply across the -55°C to +125°C temperature range for the DM54141 and across the aOc
to +70o e range for the DM74141. All typicals are given for Vee = 5.0V and TA = +25°e.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
truth table
INPUT
A
OUTPUT
ONt
L
L
a
L
H
1
L
H
L
2
L
L
H
H
3
L
H
L
L
4
L
H
L
H
5
L
H
H
L
6
L
H
H
H
7
H
L
L
L
8
H
L
L
H
g
H
H
L
H
L
L
H
H
H
H
L
L
H
H
L
H
H
H
H
L
1-1
H.
H
H
NONE
NONE
NONE
NONE
NONE
NONE
0
C
B
L
L
L
L
L
H" high level, L" low level
t All other outputs are off
6-9
o
It)
CD
QO
CIJ
o
~
D-isplay Drivers
NAnONAL
OS8650 low voltage 4-digit LED driver
general description
features
The DS8650 is a 4-digit LED display driver designed
specifically for electronic watches. Its inputs interface
directly with CMOS watch circuits such as the MM5829,
and its outputs sink tVpically75 mA from a common
cathode LED watch display.
• Direct interface with CMOS watch circuits
• Grouped inputs and outputs
• Low voltage operation
The DS8650 is supplied in dice form. Plastic DIP parts
are available for device evaluation.
• Packaged devices available for evaluation
schematic diagram
50
INPUT PAD 11. 2. 3.')
OUTPUT
~
PAD 18. 7.6. 51
.
PAD9
connection diagram and chip pad layout
Dual-ln·Line Package
IN.
10
IN3
9
,.2
8
'"
NC
D:
-
1
2
OUT4
QUT3
3
DUl2
4
5
OUTt
GNO
Order Number DS8650N
or 058650 Dice
6·10
Is
7
Note 1: All dimensions in miflim:hes.
Note 2: Die sRe 33 mils x 36 mils.
Note 3: Pads 4.0 mils stfuarulear area.
absolute maximum ratings
V ,N = 1.5V
V OUT = 5V
Applied Voltage
electrical characteristics
(Note 1)
2.7V ~ Vee ~ 2.9V; -5°C ~ TA ~ +70°C, unless otherwise specified.
PARAMETER
CONDITION
I'H
Input "ON" Current
V,N = 1.1V. lOUT = 42 rnA
I'L
Input "OFF" Current
V,N = 0.2V. VOUT
VOL
Output "ON" Voltage
IOL =42 rnA. liN
IOL - 63 rnA. liN
ICEX
Output Leakage Current
(4 Outputs Tied Together)
V,N
= 0.2V.
IOL
Output Sink Current
VOL
=0.55V.
0.84
= 5.0V
=8401JA"
TYP
IJA
0.55
0.07
63
UNITS
rnA
-20
0040
= 5.0V
= 1.3 rnA
MAX
1.4
-{l.01
VCC = 2AV
1.3 rnA. Vec = 2.7V
VOUT
liN
MIN
1.0
V
V
IJA
75
rnA
Noto 1: All references to Vce apply on a system basis since the OS8650 has no Vec connection.
,
6·11
en
It)
CQ
00
en
c
~
Display DriverS
NAllONAL
058651. 058659 low voltage seven-segment LED drivers
general descripti'on
features
The OS8651 and OS8659 are seven segment LED display
drivers spedfically designed for electronic watches. Their
inputs interface directly with CMOS watch circuits such
as the MM5829. and their outputs provide a constant
current drive for common cathode LED watch displays.
Output current drive fr·om the OS8651 is 6.5 mA
typical per segment and the OS8~59 provides 10 mA
typically. thus no external resIstors are needed.
• Oi.rect interface with CMOS watch circuit
Both circuits .are supplied in dice form. Plastic DIP
parts are available for device evaluation.
• Internally set constant current drive
• Grouped inputs and outputs
• Packaged devices available for evaluation
•
Low voltage operation
schematic diagram
r - -......--o Vee PA016
OUTPUT PAD US, 14. 13, 12, II, 10, g)
.,
INPUT PAD (1:2.3.4.5.6.710-.....,.,......,
R2
OS8&51 81 "'3k,R2-1.8k
DSlJas9 R1 =Jk,RZ"D.75Jt
PADB
connection diagram and, chip pad layout
Dual-In-Line Package
"
1,1'
16
15
14
"
12
10
)'-
I-'-
,.--
I-'-
1
2
IN1
1M2
, •
INJ
lN4
5
INS
,
INB
7
IN1
TOP VIEW
Order Numb8r DS8651N
or DS8659N
.
6·12
11
"-
Ne
•
GND
Note 1: Alidimension.inllliWnches.
Note 2: Di,siza61 mJls ,,69 mill.
Note3: Pads 4.5 mils sqUire cfllllf typicallV.
absolute
maxi~~m
ratings
(Note 1)
Maximum Applied Voltage
Minimum Applied Voltage
Vee = 5V
Vee =-Q.3V
electrical characteristics
2.4V ~ Vee ~ 2.9V;
(Notes 2 and 3)
-SoC ~ TA ~ +70°C. unless otherwise specified.
I'H
I..
Input "OFF" Current
V,N
Icex
Ou,tput "OFF" Current
V,N
10H
Output "ON" Current
V,N
=0.8V,
Vee
=Vee -
0.2V
Supply Current
058651
058659
=2.7V
= 1.3V
I
Vee = 2.9.
V'N = 0.8
J Vee =2.7.
V,N = a.5: Vee =2.4. 'V OUT = 2.15
_
_
I Vee =2.7
•
2.9V, Vee
=3.5V.
V1N -O.5. VouT -2.15.
lee
MIN
CONOITIONS
PARAMETER
Input Current
Vee = 2.7V. V,N
MAX
UNITS
-300
-300
IlA
IlA
0.06
VOUT
1
TYP
-150
-15Q
VOUT
VOUT
Vcc=2.4
=0.5V. VOUT = 2.15V,
=2.3
=2.2
058651
058659
058659
5
-3.5
-ii.5
?
10
-200
nA
2
IlA
-10
rnA
rnA
-S
rnA
rnA
IT)A
-4 ..5
12
15
rnA
One Input-Output Pair "ON" at a Time
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless othelWise specified minImax limits apply across the -SOC to +7Cfc range for the 0586511058659. All typical values are for
TA = 25°e.
Note 3: All currents into device pins shown as positive, out of device pins as ne;gative, all voltages referenced to ground unless otherwise noted.
All values shown as max or min on absolute value basis.
'
6-13
~.
"Display Drive,rs
NATIONAL
088654 8 output buffer
088655 12 output decoder/driver and oscillator
088656, diode ,matrix
system description
The 088654, 058655 and 088656 are specifically
designed to operate a thermal printing head for calculator or other uses. :In this application the same segment in
each digit is selected at the same time, redueing the
overall time for, a complete print cycle. The 058654
is an 8·digit driver. Wi,th a 15-digit print head, two of the
058654, are required. The 058655 is an, 8-segment
driver. It drives 15 mA to the base of an external power'
transistor, which in turn may have to sink up to 800 mA
if all segments happen to be selected.' The segment drive
is,' sequential and is decodEld from inputs 'A, 8' and C.
These inputs with an enable input and an Indicator
5tatus input operate four status drive outputs, which are
also selected sequentially. These outputs,designated
, LV, AOO, MEM and CALC ate designed to drive LEO
status lamps through a single external limiting resistor
to ground. The, 088655 also provides the clock for the'
calculator circuit (MM5786) with an external resistor
and capacitor for accuracy.
The 058656 diode arrays are used to prevent "sneak"
currents in the resistive print head. In a 15-digit print
head with one alphanumeric digit there are 119 resistor
segments requiring 119 diodes. For ease of assembly, the
088656 is configured in four groups' of three common
cathode diOdes in each group. In the system, ten parts
of 058656 are required.
The whole system, F ;gure 1, is designed to operate
from a +19V supply for the print head and an 8-cell
nickle-cadmium battery supplying -BV to -11.6V for
the rest of the electronics. The 8-segment drive trans-
iSlors require LVCER'S of33Y min, ,B of> 100 'at
Ie = 500 mA, and VSAT < 1.0V at 800 mA with 16'mA
- , '
,"
"drive.
general description
058654 is an 8-digit driver with emitter/follower out,
puts. It can source up to 50 mA at a IQw impedance"alld
operates with a constant internal drive current over a '
wide range of power supply-from 5V to 33V. The
058654 can be' used to drive, ehictrical or meChanical,
multiplexed or unm'ultiplexed display systems., It can be
used as a segment driver for common dathode, displays
with external current limiting, 'resistors or can ,drive
incandescent or fluorescent displays directly; both digits
(anodes) and segments (grids); It will be necessary to run
the device at a lo~er duty cycle,to keep' the maximum
package dc power dissipation less than 600 mW while
operating all 8 outputs at' high supply voltage and large
source current. The inputs are M05 compatible and
elim inate the need for level shifting since inputs
referenced to the most negative supply of system.
are
The 088655 is a 1-out-of-8 segment decoder/driver; also
has 1-out-of-4 decoded status outputs and on-chip clock
generator. The segment outputs and status outputs are
controlled by enable and indicator status inputs respectively. The segment outputs can source 15 mA min. The
status outputs are capable of sinking up to 40 mA at a
low impedance. The device has a low-voltaga battery
indicator.
The clock frequency of the oscillator can be controlled
by external timing components, Rand C.
connection diagrams
Dual-ln·Line Package
Dual·1 n·Line Package
Dual-ln·Line Package
III C 'N. EN 'N A SlG SEG 1£0 lEG SEG tEG
Vcc(83)
(SZ)(SG)(S11
.0
FOP
A
G
,
II
" "
13
1,2
11
j
*
I"
•
~P'
I
OU14 DUT3 OUT.2 OUTl Vee
IN1
IN,
TOPYIEW
Order Number DS8654N
6-14
1M3
'''4
Ole Ole osc IND LV ADD MlM CALC SED lEG GND
CROUT IT OUT OUT OUT OUT C
E
TQPVIN
Order Number DS8656N
2
•
.* • * •
"
TO,VJEW
Order Number DS8656N
"
absolute maximum ratings
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Maximum Package Power
Lead Temperature (Soldering, 10 seconds)
electrical characteristics
OS8654 (Note 1)
Temperature (TA)
057654
058654
I'L
Logical
10H
Logical "1" Output
VOL
Logical "0" Output Voltage
MIN'
MAX
22
33
V
+125
+70
°c
°c
-55
0
UNITS
C~rrent
MINI
cCJ)
MA
00
13
40
MA
U1
0.01
-100
MA
Vee-loS
V ee -2.5
390
= Max,
= 6.5V
V ,N = O.4V
V OUT = Gnd
= 500MA,
Vee = Max, liN
~
~
V
IOH = -50mA
ICC(OFF)
Supply Current
Vee:::: Max, V IN
ICC(ON)
Supply Current
Vee
(All Outputs "ON")
lOUT = OmA
V,N
::::
V OUT = Gnd
= 6.5V,
0.01
1.0
mA
7.5
10
mA
Note 1: "Absolu'te Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limitS. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the -55°C to +125°C temperature range for the OS7654 and across the O°c. to
+70° C range for the DSB654. All typicals are given for V CC = 30V and T A = 25 ° C.
Note 3: All currents into devjce pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.
absolute maximum ratings
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Power Dissipation
Lead Temperature (Soldering, 10 seconds)
electrical characteristics
OS8655 (Note 1)
13.5V
lL6V
6V
-55°C to +150°C
600mW
300°C
operating conditions
OS8655
MIN
MAX
Supply Voltage (V CC)
B.O
11.6
Temperature (T A)
0
+70
UNITS
V
°c
OS8655 (Notes 2 and 3)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SEGMENT DECODER
= 6.5V
I'L
Logical "0" Input Current
Vee
I'H
Logical "1" Input Current
Vee = Max, V ,N = O.4V
lou
Logical "0" Output Current
Vou
IOH1
Logical "1" Output Current
V OH , = 1.0V, V ,N = 6.5V
Max, V ,N
:=
~
OV, V ,N = O.4V
-15
500
MA
40
MA
-10
MA
-25
mA
0.5
V
STATUS OUTPUTS
V OL2
Logical "0" Output Voltage
Vee = Min, V ,N = 6.5V, IOL2 = 40 mA
I
(Except LV)
IOH
Logical "1" Output Current
V OH
~
10V
LV "1" Output Current
V OL2
LV "0" Output Voltage
I Vee = Max
I Vee = 9.0V
Vee = 8.6V, IOL2 = 40 rnA
500
MA
500
/lA
0.5
V
OSCILLATOR SECTION
fose
Oscillator Frequency
Vee = Max, (Note 5)
VOL
Logical "0" Output Voltage
Vee = Min, IOUT=2mA
V OH
Logical "1" Output Voltage
Vee
d
Duty Cycle
lec
Supply Current
Ice(SS) Stand-By Supply Current
= Max,
CJ)
500
Vee == Max, V ,N
= Max,
~
C
UNITS
MAX
Vee:::: Max,
U1
U1
U1
TYP
Vee
~
00
OS8654 (Notes 2 and 3)
"a" Input Current
00
~
CONDITIONS
Logical "'" Input Current
CJ)
OS8654
Supply Voltage (V CC)
36V
36V
OV
-55°C to +150°C
600mW
300°C
PARAMETER
I'H
c
operating conditions
lOUT = -100MA,
kHz
100
0.5
V ee -2.5
V
V
60
%
Vee = Max, One Output Seleeted (Note 4)
56
rnA
Vee =- Max, Vso ~ 6.5V
28
mA
40
6-15
switching characteristics.
DS8655
vee = lOV, TA = 25°C unless otherwise specified.
CONDITIONS
PARAMETER
tpdO
From Input to Segment/Status
Output
tpdO
MIN
TYP
Propagation Delay to a Logical "0"
MAX
UNITS
100
ns
100
ns
100
ns
100
ns
See ac Test Circuits
Propagation Del ay to a Logical "0"
From Enable Indicator Status to
See ac Test Circuits
Segment/Status Output
tpdl
Propagation Delay to a Logical "1"
From Input to Segment/Status
See ac Test Circuits
Output
tpd1
Propagation Delay to a Logical "1"
From Enable/Indicator Status to
See ac
Test Circuits
- -
Segment/Status Output
fose
Oscillator Frequency
R = 18k, C = 1500 pF
d
Duty Cycle
R= 18k, C= 1500pF
kHz
100
40
60
%
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not mean,t to imply that the devi.ces should be operated at these limits. The table of "Efectrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwis~ specified min/max limits apply across the O°C to +7rfC range for the DS8655. All typicals are given for VCC = 10V
and TA = 25°C.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max ~r min on ab~olute vaiue basis.
No'te 4: Only one output at a time should be turned "ON."
Note 5: Oscillat~r frequency controlled by external timing components, resistor (2k to 20k) and capaci~c;tr~
electrical characteristics
088656 (TA = O°C to +70°C)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VR
Peak Inverse Voltage
IR = 0.1 mA
VF
Forward Vallago
IF = 50mA
1.5
V
t,
Reverse Recov. Time
IF =50mAto IR =0.1 mAatV R =30V
1.0
/1S
35
schematic diagram
OS8654
,.~
H.
u~
....
15k
IN
.
~~
~
6-16
v",
K
1
OUT
V
logic diagram
c
en
co
058655
0)
osc R
OSC C
U1
~
C
lOUT
SEG A
en
co
0)
SEG C
U1
U1
C
SEG E
en
co
EN
0)
SEG G
U1
0)
SEG B
IN A
SEG 0
SEG F
IN B
SEG OP
IN C
ADD OUT
CALC OUT
INO
ST
MEM OUT
LV OUT
BV
v" 0 - -.....1-....-1
schematic diagrams
(Input and Outputs)
058655 Tvpicallnput (Except Oscillator)
INPUT
058655 Segment Output
058655 Status Output
O--'VI.,..,.....-I
1..----+--0 OUT
truth tables
058655
Segment Decoder
SELECTED
OUTPUT
a
INC
INS
INA
0
0
0
1
0
Seg. d
0
0
0
0
1
1
Seg. e
1
Seg. f
1
0
0
Seg. 9
1
1
Seg. D.P.
1
None
X
1
X
0
1
0
1
X
Seg.
Seg. b
Seg. c
I
Status'Outputs
EN
0
0
0
0
0
0
0
0
1
OUTPUT STATE
CALC
MEM
0
1
1
0
1
1
1
1
1
0
1
1
ADD
1
1
1
INC
INS
INDIC
STATUS
0
1
1
1
1
0
0
1
1
0
1
0
1
1
1
0
0
LV
1
1
1
Vee
X
X
X
9.0-11.6V
S.O-S.6V
x = Don't Care
x = Don't Care
6-17
(D
LO
cg
ac test circuits and switching time waveforms
co
en
Vee "'lOV
Q
058655
Vee" lOV
250
250
LO
it)
cg
CO
en
STATUS
088655
OUTPUT
Q
SEGMENT
OUTPUT
~
LO
cg
.".
CO
en
.".
FIGURE 1.
FIGURE 2.
Q
6.5V
/
ENABLE
1
\:0%
\
0%
5
6.5V---r----~
INPUT
(SEE TRUTH TABLE)
50%
'~nJ~~
+~
1::________~r---:I~
1:: _________
*-
OUTPUT
,,\50%
FIGURE 3.
typical application
8 DIGITS
1
r--o
088654
LI
VDD
1
r-
~
r--
r--
~
r-
"--
f
~
'--
~
MOS CALCULATOR
~
~~
~ ~ ~
,
~
~
CHIP
MM5786
088656
f
7 SEGMENTS
,
!
v••
6·18
088655
!
~
system diagram·
II
I
11
I I
01501401301201101009 DB 01 0605 04 III 0201
PAPER
ADVA~~~
0 - ReADY
OUT 1-+++++++++++++--,
MM518&
OSC
K2
KI
I
.--4+++-t--I1-I4-.....+-<> +t9.0V
I
DS81iS4
DSB654
OIGIT DRIVER
~
STATUS
S352 51
~
I
DIGIT DRIVER
L.--r--.--r-r-,,-,---,-J
0102 0304050607 DB
09010011012013014015
SO
THERMAL PRINTER HEAD
~
I'-:- I'-:I'-:- I'-:-
~
I
I
~ I'-:~ I'-:I'-:-
~
":-
r--,.
~
~
Sg
MOTOR
CLUTCH
COIL
~
15
1'5
15
15
DIODES
DIODES
DIDOES
DIODES
~
-VSAT
I'-:-
":-
r--,.
~
I":-
~
I'-:-
"=
~
2X 13
KEYED
MATRIX
Sd
I'-:-
":~
•
'~~E~OI~~ES ~~d;f~l~
I'-:- I'-:-
PAPER
ADVANCE
CAM
SWITCH
Sb
l
lEO'S
INOS.. Sb St Sd
51 IN
L-_ _ _ _ _ _ _ _ _ _-\S2
Se
058655
SEGMENT DAiVER
usc
Sf Sg
SopW ..
210n
{c~~~~
INO
-&6.
~8;s MEM~
lvh
~
~--------------------S-J~OIT OS~R:rGNO , ~
*c
6-19
Display
Drivers
,
,
OS8658 low voltage four~d,git LED driver
general description
features
The 058658 is a 4-digit LED display driver designed
specifically for electronic wiltches. Iq inputs interface
dirtlctly with CMOS watch circuits such as the MM5829,
and its outputs sink tYpically, 100 rnA from a common
cathode LED watch display;
• Direct interface with CMOS watch circuits
• Grouped inputs and OUtputs
!" Low voltage operation
The 058658 is supplied in dice form. Plastic DIP parts
are available for device' evaluation.
• Packaged devices available fbr evaluation
schematic diagram
,
4pOO
II. 1.6.6)
OUTPUT
50!!
INPUTPOOU.2.3.4) . '
..
.
PAD!
connection diagram and chip pad layout
~C
N,C
1'4
1'3
OUT!
OU12
OUT'3
t2
11
to
24,6,
i- 8A
Dual·ln·Lina Pac~age
OU14
-ric
•
~
-.lb.
T
6;a
GNO
OUTt
ht
Lr"Nt
h2
r-0 'N2
a;a
rti3
r-0 'N3
J.
1
1'"14
INO
5~
t
2
IN!
3
4
5
IH2
IN3
IN.
TOP VIEW
Ord~r
6·20
Number pS8658N
Jca
Nt7
-I
1
hI
1;'
OUT ZLr'
1:18
OU13
"U
DUT4L ..
i
711
a's
-----L
+--G,1l
r-o
..rl:t8
u' ~
~
5'2~
• Note 1: All dimensiolll in miUin_.
Note2: ~siie331'1111s~31.
No~ 3:
Plds 4.0 mUs"SIIU'" clllr area.
,
absolute maximum ratings
Applied Voltage
Y'N
=1.SV
=sv
Vout
electrical characteristics
2.7V ::; Vee::; 2.9V;
-soe ::; T A
PARAMETER
I'H
Input "ON" Current
I'L
Input "OFF" Current
VOL
Output "ON" Voltage
leEx
Output Leakage Current
10L
Output Sink Current
(Note 1)
::; +70 oe, unless otherwise specified.
CONDITION
= 1.1V,
V,N =0.2V,
= 56 rnA
VciUT = 5V
' 10L - 56 rnA, liN =840p.A, Vee- 2.4V
10L =84 rnA, liN = 1.3 rnA, Vee =2.7V
V,N = 0.2V; V OUT = 5V
V,N
lOUT
MIN
0.84
TYP
MAX
-G.01
-20
0040
0.55
0.07
UNITS
rnA
6
1.0
p.A
V
V
p.A
(4 Outputs Tied Together)
VOL
=0.55V,
liN
= 1.3 rnA
84
100
rnA
Note 1: All references to VCC apply on a system basis since the 058658 has no Vee connection.
6·21
.
~
Display'Orivers
Advance Information*
~
co
058673, 058674 7-segment decoder/driver/latch
C
general description
tn
NATIONAL
plexed display system,s are el,iminated. it also allows low
strobing rates 'to be used w'ithout display flicker.' '
The 058673, 058674 is a 7-segment decoder/driver
with latches on the address inputs and active low constant current outputs to drive LEOs directly.
Another feature of the 01)8673, 058674 is the reduced
loading on the data inputs' wh~n the latch enable 'is
high' (on'ly 10pA typ). This allows many 058673,
058674's to. be driven from a MOS'dellice in multiplex
n;iode ~ithout the need for drivers on the pata lines.
The, 058673, OS8674 accepts' a 4'bit binary code and
piodlices output' drille to the apprdpriate segments of
the 7-segment display. It has ,a decode format which
produces numeric ~odes "0" through "9" and other
codes as shown" on subsequent' pages (see truth table).
,Lat~hes on the four data inputs are cpntrolled by an
The 058673, 058674 also provides alJtomatic blanking
of the leading and/or trailing edge zeros in a multidfgit
decimal number, resulting in an easily readable decimal
display conforming to normal
, writing practice.,
acti~e low, Latch Enable E~ When ~ is low; the state
of the outputs is determined b.y':the input data. When ~
goes high, the last data present at· the inputs is stored in
the latches and the outputs remain stable. The E( pulse,
width necessary to accept and store' data is typically
50 ns, which allows data to be stiobedin-io the bS86i{
058674 at normal TTL speeds. This feature means that
data can be routed directly from hi9h speed counters
and frequency dividers into the display without slowing
down the system clock or providing intermediate data
storage.
features
• High speed input latches for data storage
• 15 mA cons,tant, current ~ink capabili,ty ):0 directly
drive common anode LEO displays .. ; man 1 type
• Active low latch enable for easy interface with M51
circuits
• Oata input loading essentiaily zero when latch disabled '
The latch/decoder combination is a simple system which
drives LEO displays with multiplel(ed data inputs from
M05 time clocks, OVMs, calculator chips, etc. Oata
inputs are multiplexed while the displays are i~ static
mode. This lowers component and insertion costs, since
several circuits-seven resistors per display, strobe
drivers, a separate' display voltage source, and .clock
failure detect circuits-traditionally found in multi-
connection diagram
• .Automatic ripple blanking for suppression of leading
edge zeros and/or trailing edge zeros
• Pin out compatible with other standard M51 decoders
such as OM7446, OM7447 and OM7448
• Replaces Fairchild 9374 and 5ignetics aTI4 pin
for pin
Dual-In-Line Package
I"
A1
A2
lL
A3
AD
GNO,
TOP VIEW
Order Number oS8673J,
DS8674J or DS8673N, DS8674N
DS8673 Digit Display
rl
I_I
•
6-22
1
-, LI S
I -,
I l- _1
,
2
IOl-IRllIl-C
IC] -, lCJ/_ l'JC I '
"
"
DS8674 Digit Display
ll-' r-, - lI l-'
lIl
1
I
CI
I
I, • ,
• •
•
11
11
10
.11
-,
13
I-I"
13
15
14
15
·Specifications may change.
absolute maximum ratings
operating conditions
(Note 1)
~5·C to +150·C
Storage Temperature
Temperature (Ambient) Under Bies
-£5·C to +125·C
-{) .5V to +7 .OV
VCC Lead Potential to Ground Lead
"Input Voltage (dcl
-{).5V to +5.5V
'Input Current (dcl
-30 mA to +5.0 mA
Output Voltage (dc) Output "OFF"
10V
Output Voltage (dc) Output "ON"
8.0V
300·C
Lead Temperature (Soldering, 10 seconds I
MIN.
MAX
Supply Voltage (Vccl
4.75
5.25
Temperature (TAl
0
UNITS
V
+75
'C
MAX
UNITS
-Either Input Voltage limit or Input Current limit is sufficient
to protect the inputs;
electrical characteristics
(Notes 2 and 3)
PARAMETER
V IH
Input High Voltage
CONDITIONS
MIN
Guaranteed Input High Voltage
TYP
2.0
V
for All Inputs
V IL
Input Low Voltage
Guaranteed Input Low Voltage for
0.8
V
-1.5
V
0.25
004
V
15
18
All Inputs
Veo
Input Clamp Diode Voltage
= Min, liN =~12 mA,
= 25°C
Vee = Min, IOH =-4O!LA
Vee = Min, IOL = 0.8 mA
Vee = 5'.OV, VOL = 3.0V
Vee
TA
VOH
Output High Voltage RBO
VOL
Output Low Voltage RBO
IOL
Output Low Current a through g
2.4
12
IIH
Vee
Input High Current
Vee
Data
V IN
RBI and EL
IIH
Input High Current
IlL
Input Low Current
= Max,
= 2AV
Vee = Max,
Vee
V IN
Icc
= Max, VOl,JT = 5.5V
Output High Leakage Current
athrough 9
Power Supply Current
V IN
= Max,
=OAV
Vee = Max, V IN
V
14
Vee - 5.0V, VOL - 0.5V
leEx
3.5
mA
mA
250
!LA
10
40
!LA
5
20
!LA
1.0
mA
=5.5V
EL and "RBI
Data (Latch Enable Low)
~.25
~A
mA
~.25
~A
mA
Data (Latch Enable High)
±O.Ol
~.06
mA
RBO (Used as an Input)
~.7
-1.2
mA
35·
50
mA
=O.OV,
VOUT
=3.0V
Note 1: "Absolute Maximum Ratings" are those values beyond which the sefety of the device cannot be guaranteed. Except for "Operating
Temperature Rang." they are not meant to imply that the devices should be operated at these limits. The table of '~Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unle.s otherwise specified minimax limits' apply across the O·C to +75· range for' the DS8673 and DS8674. All typical values are for
TA· 25·C and VCC = 5V.
Nota 3: All currents into device pins shown as pOSitive, out of device pins as negative, all voltages referenced to ground un,less otherwise noted.
All values shown as max or min on absolute value basis.
6·23
switcl1ing characteristics
,
tPH~
TA
=25°C,
Vee = 5.0V
PARAMETER
"
CONDITIONS
MIN
Turn On [le/ay Data Input to
RL = 1 kSl,C L = 15pF,
OutPut
(Figure 3)
tpLH
Turn Off Delay Data Input to
Output
RL 1 kn, CL
(Figure 3)
tpHL
Turn On Delay EL Input to
Output
(Figure 2)
=
TVP
=15 pF, ,
RL = 1 kn,C L =15pF,
,
=1 kn,C L ": 15pF,
MAX
UNITS
140
ns,
140
ns
,140,1
.ns
140
ns
Turn Off Delay EL Input to
RL
Output
(Figure 2)
t.(H)
Set·Up Time High Data to
Latch Enable
(Figure 4)
75
ns
th(H)
Hold Time High Data to
Latch Enable
(Figure 4)
0
ns
t.(L)
Set·Up Time Low Data to
Latch Enable
(Figure 4)
30
th(L)
Hold Time Low Data to
(Figure 4)
0
(Figure 5)
85
tpLH
"
,.
ns
ns
"
Latch Enable
tw(Ed Latch E"able Pulse Width
50
ns
Set·Up Time: ts is defined as the time required for the logic level to be present at the Data' Input prior to the Enable transltl'on from Low to
High In order for the latch to recog~lze and store the new data.
Hold Time: th I. defined as the minimum time following the Enable transition from Low to High that the logic level must be maintained at the
data input In ordar to ensure continued recognition. A negative Hold Tim. indlcat.. that tha logic level may be released' prior to tha Enabla
trensltlon from Low to High and still be recognized.
typical performance characteristics
30
1
..
ii'l
a:
...
a:
;::
•!II
i!;
S
C>
I I I I
I I I I
I I I I
27
24
21
12
9
I,.-~
Vee - 6.25V,"",
18
16
TA -15'C_
~ee,'5,~~r
Vee =4.76V
6
3
I I I I
I I I I
0
0 1
3 4
2
5
8
7
•
9 10
OUTPUT YOUAGE (V)
FIGURE 1. Typical Const,ant Segment Current VI Output Voltage
switching time waveforms
OATA
'NPUT
=-=x ' X-----'-_";"_..J
'D~TA~
' IiT" 1.5V
<~2t{
OU11'UT
~UTPUT
1,iV
DATA~~
6·24
DATA
,NPUT
~
~~~~
FIGURE 4.
'
.
uv
'
r~-
,
FIGURE 3.
FIGURE 2.
INPUT
-: t
=~
--------x: .
,
\... _ _ _ _ _
"~
...
...
FIGURE 5.
o
en
block diagram
00
r-----------------,
AD
I
I
I
IL
en
C:i
o
I
I
en
00
~
__________ .J
_____ _
SEGMENT
ENCODER
A'o---------~~------------------~L:AT;.C:H-----------------~~
A2o-------~~~------------------~L;AT~C:H------~----------lr~
2
,.
A3O-------~~~------------------~L;AT~C:H------------------lr~
,
~------------------~---oMO/"
•
truth table
BINARY
STATE
-
EL
-RBI
A3
INPUTS
A2
Al
AO
-a
-b
-c
O~TPUTS_
d
e
f
-9
RBO
DISPLAY
-
H
.
X
X
L
L
X
L
X
0
L
L
L
H
H
H
H
H
H
a
L
H
L
L
L
L
L
L
L
L
L
L
H
H
1
2
3
4
5
6
L
X
L
L
L
L
H
H
L
L
H
H
H
H
f
H
L
L
L
H
L
L
H
L
2
3
'-I
5
6
STABLE
L
L
L
L
L
H
H
L
L
L
L
H
H
L
L
L
H
L
L
H
L
L
H
H
L
L
L
L
H
L
H
L
H
L
L
H
L
L
L
L
H
H
L
L
H
L
L
L
L
L
• H
STABLE
L
H
BLANK
0
7
L
L
H
H
H
L
L
L
H
H
H
H
7
8
9
10
11
12
13
14
15
L
H
L
L
L
L
L
L
L
L
L
L
B
CJ
L
X
X
X
X
L
H
L
L
H
L
H
H
L
L
H
L
H
L
L
H
L
L
H
H
H
H
H
L
-
L
H
L
H
H
L
H
H
L
L
L
L
E
H
L
H
H
L
L
H
L
L
H
L
L
L
L
H
H
L
H
H
H
H
L
L
L
H
L
L
H
H
H
L
L
L
H
H
L
L
L
P
H
H
H
H
H
H
H
H
H
H
H
H
BLANK
X
X
X
X
H
H
H
H
H
H
H
L"
BLANK
*The RBI will blank the display only if a binary zero is stored in the latches.
**RBO used as an input overrides all other input conditions.
DEFINITION
INPUTS
OUTPUTS
H
High Voltage Level
Output is "OFF"
L
Low Voltage Level
Sinking Current
X
Don't Care
Segment Identification
application hints
It is possible with common anode 7-segment LED
displays and constant current sink decoder drivers to
save substantial amounts of power by carefully
choosing operating points on display supply voltage_
First, examine the power used in the normal display
driving method where the display and decod~r driver are
both operated from a 5V regulated supply (Vee = VslThe power dissipated by the LED and the driver outputs
is (V cc X ISEG x n Segments)_ The total power dissi-
pated with a 15 mA LED displaying an eight (8) would
be:
P TOT = 5_0V x 15 mA x 7
'= 525mW
Of this 525 mW, the power actually required to drive
the LED is dependent on the V F drop of each segment.
Most GaAsP LEDs exhibit either a 1.7V or a 3.4V
6-25
application hints (con't)
forward voltage drop.' Therefore, the required total
power for seven segments wO\lld be:
P O .7 ) '" 1.7V
x 15mAx 7
a. Reduced transformer rating
b. lVIuch small smoothing capacitor
c. Jncreased LED light output due to pulsed operation
'" 178.5 mW
P(3A)'=
frequency of 120 Hz is high enough to .avoid display
flicker problems. The main advantages of this system
are:
3.4V x 15 mAx
7
'" 357mW
The remaining power is dissipated by the driver outputs
which are maintaining the 15 mA constant current
required by the. LEOs. Most of this power is wasted,
since the driver can maintain approximately 15 mA with
as little as 0.5V across the output device. By using a
separate power source (V s) f
1'1
'8
19
17
16
~
~
a
m
~
M
~
~
_
1
,
3
IN 1
IN 2
IN 3
IN 4
5
,
IN 5
IN 6
\
TOP VIEW
'
'181'
IN
TQPVIEW
Order Number DS8693N
Dual-In-Line Package
ctlLUMN
,TIMING
Vee OUT10UT20UT30UT40U150UT60UT70ur-8 IN
L4
-123
22
21
20
19
18
17
16
OSCCOSCA
15
14
13
.~l'
""7
.l'
.l'
.,,;>- ~
D
V
1
2
,3
4
INZ IN 3
IN4
5
• ,
IN 5 INS
8
~
"7
fr~
IN 1
I'
10
11
IN 7 INS eLK TIMING OSC
OUT OUT
COLUMN
TOP VIEW
Order Number DS8694N
6·28
10
J~'
1'2
GNO
l
IN 7 COLOR eLK PRINT GND
COLUMN
,
12
trf>
I
Order Number DS8692N
,
13
~-t(rG>-tr--
~
14
15
absolute maximum ratings
OS8692-Transistor Array (Note 1)
Collector to Base Voltage
Collector to Emitter Voltage
Collector to Emitter Voltage (Note 4)
Emitter to Base Voltage
Collector Current (Continuous)
35V
35V
15V
6V
0.4A
electrical cha racteristics
Power Di..ipation (TA = 2S·C)
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
OS8692 (Each Transistor, T A = 25° C unless specified)
PARAMETER
VCEO
CONDITIONS
Collector to Emitter Breakdown
650mW
1SOOC max
O"Cto +70"C
-65·C to +150"C
3WC
Operating Junction Temperature
MIN
2 and 3)
(Notes
TYP
UNITS
MAX
Ie = 101l/lA. la = 0
15
V
Ie = 1001lA, Vse = 0
35
V
Ie = 101l/lA, Ie = 0
35
V
Ie = 165 mA@V ee = 5V
Ic =350mA@V ee ·=5V
80
V
70
V
Voltage
V CES
Collector to Emitter Breakdown
Voltage
Veao
Collector to Base Breakdown
Voltage
hFe
de Current Gain
VCE(SATI
Collector to Emitter Saturation Voltage
Ie = 350mA, la = 7.0mA
VBE(SATI
Base to Emitter Saturation Voltage
Ie
absolute maximum ratings
Supply Voltage
Input Voltage
Output Voltage
All Pins Except Pin 13
Pin 13
= 350 rnA.
Is =7.0mA
OS8693 (Note 1)
12V
12V
Storage Temperature Range
Lead Temperature (Soldering. 10 seconds)
12V
19V
-65·C to +150°C
300°C
electrical characteristics
PARAMETER
1.0
V
0.95
V
operating conditions OS8693
MIN
MAX
Supply Voltage (VCC)
8.5
11.0
Temperature (TA)
0
UNITS
V
·C
+70
OS8693 (Notes 2 and 3)
I
I
CONDITIONS
MIN
I
TVP
I
MAX
I
UNITS
COLUMN DRIVERS.
liN
Input Current
VIN = Vee -1.5V
VOL
Output "OFF" Voltage
Vee = Min, liN = 50.0IlA, ICLOCK
= 301l/lA.
250
IlA
0.4
V
-17
mA
-1.2
mA
lOUT =, mA
10H
Output "ON" Current
Vee = Min. VIN = 7.0V. ICLoeK = 30D/lA.
V OUT = 1.0V
los
Output Short Circuit Current
Vce = Max. liN = SOIlA. ICLOCK = 300IlA.
V OUT =O.OV
CLOCK INPUT
VIN
"-
-7
..
InPut Voltage
liN = 300IlA
4.1
liN = 50llA
IIH
Logical" 1" Input High Current
IlL
Logical "0" Input Low Current
V
1.5
300
V
IlA
50
Il A
MOTOR DRIVER
11N(PflINT)
Input Current
VIN = Vee -1.5V
IIL(STOP)
Input Low Current (Stop)
Vee = Min, VINISTOP) ~ O.OV.
(Stop Switch Closed)
V'H(STOP)
Input.High Voltage (Stop)
Vee = Max. IINISTOP) = OIlA,.
(Stop Switch Open)
VOL
Output Low Voltage
Vee
lox
Output Leakage Current
Vee = Max, IpRINT = 51l/lA, VSTOP. = O.OV.
V OUT = 15V
= Min. VPRINT = 7V.loUT = 15mA
250
-270
IlA
Il A
1.35
V
0.5
V
100
IlA
,
6·29
electrical characteristics (con't)
OS8693
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
COLOR DRIVER
V ,N
Input Voltage
liN
= 250pA
4.55
V
liN = 50pA
VOL
Output "OFF" Voltage
Vee
= Min, liN = 50pA, lOUT = 1 rnA
= Min, liN = 250pA,V OUT = 1.0V
10H
Output "ON" Current
Vee
ICC(PEAKI
Peak Supply Current
Vee = Max,
fCC{SB)
Stand·by Supply Current
Vee = Max,
VCOLUMN IN/VPRINT "'"
ICLoeK IleoLoA
'COLOR
ICC(AVE)
Average Supply Current
= 300pA,
'CLOCK""
absolute maximum ratings
rnA
180
rnA
= OV,
55
mA
68
mA
300pA
operating conditions
OS8694 (Note 1)
12V
MIN
12V
19V
12V
~5'C to +150'C
300'C
dc electrical characteristics
V
-18
lV,
Vee = Max, Continuous Operation
Supply Voltage
Input Voltage
All Pins Except Pin 15
Pin 15
Output Voltage
Storage Temperature Range
Lead Temperature (Soldering 10 seconds I
V
0.4
(Note 61
VCOLUMN'tN/VPAINT"
= OpA,
-8
1.65
Supply Voltage (V CCI
8.5
Temperature (TAl
0
MAX
11.0
+70
UNITS
V
'c
OS8694 (Notes 2 and 3)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
COLUMN DRIVER
,liN
Input Current
V ,N
VOL
Output "OFF" Voltage
Vee
= Vce -1.5V
= Min, liN = 50pA,
ICLOCK
= 300pA,
250
pA
0.4
V
;-17
mA
-1.2
mA
lOUT =:: 1 rnA
= Min, V ,N = 7.0V, ICLOCK = 300pA,
= 1.0V
Vec = Max, liN' 50pA, ICLOCK = 300;'A,
V OUT = O.OV
Output "ON" Current
10H
Vee
-7
V OUT
Output Short Circuit Current
los
CLOCK INPUT
V ,N
Input Voltage
liN
liN
I'H
Logical "1" Input High Current
I'L
Logical "0" Input,Low Current
= 300pA
= 50pA
4.1
V
1.5
V
pA
300
50
pA
880
pA
0.5
V
TIMING BUFFER
= 17V
liN
Input Current
V ,N
VOL
Output Low Voltage
lOUT" 50pA, V ,N = 10V
V OH
Output High Voltage
lOUT
380
=-50pA, V;N
V
Vee-T.O
" 7V
OSCILLATOR
fosc
Freque';"1cy
.
Vee = Max, R = 18k, C = O.OO15IlFd,
85
100
115
kHz
(Note 51
VOL
Output Low Voltage
Vee =- Min, lOUT
VOH
Output High Voltage
lOUT
d
Duty Cycle
Vee = Max
Vase
Osc. Vee Turn·On Voltage
iCC{PEAK)
. Peak Supply Current
Vee = Max,
ICLOCK
iCC(SB)
Stand·by Supply Current
= 50llA
0.5
= -501lA
VCOLUMN 1N/Vp'RfNT
= 300pA,
' Vee = Max,
V ee -l.0
=
7V,
V
.V
40
50
60
7.2
7.7
8.2
%
V
200
mA
55
mA
62
mA
(Note 61
VCOLUMN
1NNpRiNT::= OV,
leLOeK ~ 300pA~
ICC(AVE)
6·30
Average Supply Current
Vee"" Max, Continuous Operation
c
en
ac electrical characteristics
OS8694
Vee = 5.0V. TA = 25°C (unless otherWise specified)
CO
CD
(£)
N
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
CO
CD
COLUMN DRIVERS (DSIl69J. DS8694) (Figure 3)
PWCOLUMN
Column In Pulse Width
1.1
360.0
/1s
PWCLOCK
Clock Pulse Width
1.0
150.0
/1S
Delay of Column In Pulse After
0.1
160.0
/1S
td
(£)
W
c
en
CO
CD
Clock Transitiol')s to Low State
for Output to Latch
tpdO
Propagation Delay to a Logical
(£)
Column In
= OV
10.0
/1S
Column In
= 7V
1300
/1S
,~
"0" From Clock to Column Out
Output
tpdl
Propagation Delay to a Logical
"1" From Clock to Column
Output
tpdO
Propagation Delay to a Logical
Clock
= 7V
10
/1s
Clock
= 7V
1300
/1S
"0" From Column In to Column
Out
tpdl
Propagation Delay to. a Logical
"1" From Column In to Column
Out
COLOR DRIVER (DS8693) (Figure 4)
tpdO
I
Propagation Delay to a Logical
10:0
/1s
10.0
/1S
"0" From Color In to Color Out
tpd1
Propagation Delay to a Logical
"1" From Color In to Color Out
MOTOR DRIVER (OS8693) (Figure 6).
PWPAINT
Print Signal Pulse Width
1
2400
/1S
PWSTOP
Stop Signal Pulse Width
1,
3000
/1s
PWCLOCK
Clock Pulse Width
1
150
tpdO
Propagation Delay to a Logical
..
"
,
/1S
100
/1S
10
/1S
"0" From Print to Motor Drive
Out
tpd1
Propagation Delay to a Logical
Print
= O.OV. Clock = 7.0V
"1" From Motor Stop (High·to·
-
Low Transition) to Motor Drive
Out
TIMING SIGNAL BUFFER (OS8694) (Figure 5)
PWTIMING
Timing Signal Pulse Width
t,
Rise Time
CLOAD
t,
Fall Time
' C LOAD
todO
Propagation Oelay to a Logical
ms
1
= 35 pF
500
~
500
ns
10
/1'
10
/1'
35 pF
ns
"0" From Timing In to Timing
Out
tpd'
Propagation Delay to a Logical
ul" From Timing In to Timing
Out
CLOCK OSCILLATOR (I;>S8694) (Figure 7)
(Note 5)
85
100
115
40
50
60
%
pF
,500
ns
CLOAD = 35 pF
500
ns
fosc
Oscillator Frequency
d
Duty Cycle
t,
Rise Time
CLOAD
t,
Fall Time
I
c
en
~35
kHz
6-31
.~
,,0)
CD
CICI
f/J
o
.
N
m
U)
Nota 1: "Absolute Maximum Ratings" are those values beyond which the safety of the \leYice cannot be guarantwd. Excelwfor.'~'Operating
Temperature Range" thay are not meant to imply that the devices should be operated at these limits. The teble of "Electrical Characteristics"
provides conditions for actua'i device o p e r a t i o n '
.'
.
No,. 2: Unl... otherwise specified minimax limit!'· apply _oss the o"C to +7rfC range for the 058692, 088693, 058694. All typicals are given
for VCC - S.OV and TA = 2S·C.
Note 3: All currents into device pins shown as positive, out of device. pins as negative, all voltageS raferenced to ground unla" otherwise noted. All
values hsown as max or min on absolute basis.
Note 4: Ratings refer to a high current pOint whera collector...mitter voltege is lowest.
Note 5, Oscillator frequency ii determined by external R between "Osc R" and "Osc C" and external CIrom "0'" C" to ground. 2k > R > 20k.
Note 6: Column outputs operate on approximately 1/16 duty cycle in normal operation.,
system connection diagram
Va.,
CICI
en
"
o
MOTOAsrn,~ I
V. .
lit PRINT
MOTOR BANS 13
• eLK IN
J COlOAIN
1 1111
....
SIn
COLOR OUT 14
DUH 11
ouu "
2 112
'"
B3
..
.. ."
"
""
DUT2 20
DUTI
•••
"
: : 13
,.,
,.,
~ ,.,
ovrl Iii
OS16111
,.,
.I, I" I" ..I"
.
..
,. "
""
"
••
•,
""
14
OUT5"
OUTt 21
DUT3 21
4 114
.,.!.
OUT'1 11
OIlTII f8
E2
B5
E3
OS118Z
83
OUT2 zz
OUTI U
ST.'
. ('+I
.!!...o v,
'f-1
.!....o,v••
MOTOR
'
,.
COLOR
"]
13
Cli~
Cl~
CI~
MOTOR
COLUMN
1Z
11
SELECT AND
10
COLOR MAGNET
~,v,
1+)
T.OET
v..
",
TIMING
SIGNAL
1ft
TIMING IN 15
~
MOTOR DRIV£
:~
C5~ "
14
11 OROUT
10 TIMING OUT
• INI
'1 INl
& Iftl
5
Q
"
• tLKIN
" " ..
I' 1" 1" I"
v..
V$$~24
II
EI
"
OS7119~
(RE£D~t")
24
C2~
12
,.
OUTS "
3 10 ,
,
•, "
OUT1 15
. DUll 18
.....,
4 IN4
,
"
"
" +--;;
v..
H
T.OEl
(+)
f!-o.
f!-o v,
V••
CI~
C1~
C&~
C5~
C4
.
T-+-;
C3~
~
}...
CI~
SElKE 311MINTER
v,,, fN fYoo REfERENCE'
~Df
K1
..
.• 0'
.,
~O2
~O3
,
,
•
0,
•,
O.
O'
•
•
10
DID
Oil
-'"
012
,,)//J~~I / )' /~'~/~I j'~1 J'~'
.
vss~v..
v..
READY
~NC
v,
'co
VDU
r---....... " ... l I
11 01:1
ADD
13 01&
I. USCIN
CALC
11 COLOft
12 TI"'''GSIGNAl
PRINT
I"
"
L.
v._
_ _ _ 5;!!!,L!!JI
' '0·'1
'Va :1flVITypiull
v, "'l1Vl1'ypiclll
VDI)
FIGURE 1.
6-32
-+-
20
12 014
.
ujl / pi ~I )';1 }';1 )';1 )1 ~'• ~~I )1 ~';1 / ~I•
~Grtulld
ACtoC
CONVERTER
-
f+-:AIJtS
c
rn
00
en
Logic and Timing Diagrams
COLUMN IN
(COLUMNSI-1&) :
COLUMN OUT
CD
N
(COLUMNS I-I,)
CLOCK
CLOCK
KEVB~LSES
COLUMN IN
n
---J t--t.J
JLJl
' -_ _ _ _ _~
~
t
OIGITTIME
WORD TIME
---1t
COLUMN
~r::L~:MATION
I-
PWCOLUMN
I
COLUMN OUT
Switching Time Waveforms
1V-----,__""'\
COLUMN IN
oy _ _ _.J)
COLUMN OUTPUT
CLOCK
FIGURE 3. DS8693/DS8694 Column Driver
COLOR IN
7V
0----(::>----0'
COLOR OUT
----r------,
}
COLOR IN
COLOR IN, V
ov-----'
8mA
. COLOR OUT, 1
r------,
Jl-,
.. -
OmA----..1
FIGURE 4. DS8693 Color Driver
[>
TIMING IN 0
17V
TIMING IN, V
OV
tOY
TIMING OUT, V
0.
--J
n
SW""...
U
o TIMING OUT
r--
IL
LJ
TIMING IN
f-1
{~.
"}-~'
TiMING OUT
FIGURE ,5. DS8694 Timing Signal Buffer
6·33
Logic and Timing Diagrams
PRINT~-Z-"""
CLOCK
___
'RI.T~
..!:.r)~~---L/O"'---
c::
..-,.,--------
~F--pw-
II
DRIVE
OUT
t~430m'---------~·"11
TL
------~----------------------------------~
I
I
I
I
CLOCK
MOTORSTO.
MOTOR
mm
1'!! I 1! Ii
I
I
II; I.
I
II
I
I
I
I
I
MOTOR DRIVE OUT
~L_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--'
Switching Time Waveforms
.RI.T'I\ _
__
---:3PW,=T~
MOTORORIV'
OUT1'UT
...
,r-\1..____________{
l,
CLOCK
~,
D tJ,.......,.--.--
MOTOR STOP
FIGURE 6, DS7693 Motor Drive Circuit
oseR
R
9
r-----"IIIIV--+
I
oSc C
........
-.-
I
OSC OUT.
.
~
B5I1HZ$IItoac$ 115kHz
OSCILLATOR
OUT
d"'Irty eyde"
40%$d$f}B%
FIGURE 7.DS8694 Oscillator Diagram
6·34
DSC:C:;.~cPWL
c
~
Display Drivers
Cf)
00
00
~
~
NAnONAL
C
058844. 058855. 058864. 058865. 058866 LED cathode drivers
00
00
general description
features
CJ1
CJ1
The D58844, D58855, D58864, D58865 and D58866
are cathode drivers for 7, 8 and 9 digit LE D displays.
They are designed to interface between M05 calculator
or clock circuits supplying 2.0 mA, and LED displays
operating up to 50 mA in a multiplex mode. The
D58864 and D58866 feature a "low battery" indicator
driver which will light a decimal point whenever a 9.0V
battery drops below 6.5V typical.
•
Used with 50 mA LED displays
•
"Low battery voltage" indicator
•
Directly interfaced from M05
•
Inputs and outputs clustered for easy wiring
•
Drivers consume no standby power
Cf)
connection diagrams
c
Cf)
00
00
0)
~
C
Cf)
00
00
(Dual-In-Line Packages)
0)
CJ1
cCf)
00
00
0)
0)
TOP VIEW
DS8855N
DS8844N
DS8864N
TOP VIEW
TOPVIEW
DS8865N
DS8866N
typical applications
Typical Output
a.p.
'Ok
DS8855OR
MMS7JliOR
MM5738
OS8H64OR
NSAll66OR
OS8865OR
NSA1198
058866
"OS
CALCULATOR
lED
DISPLAY
CIRCUIT
FIRSTDlGrr
"
~NSAlg8)
FIRSTOIGIT
6,7,ORRDIGITCALl:UtATOR
'VCC2 ilndpm I connectoon apvhcabl" oilly 10 OS8864 and OS8866
6-35
co
co
00
00
~
IJ')
CO
00
00
absolute maximum rati ng s
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
operating conditions
(Note 1)
llV
l1V
8.0V
~5"C to +125"C
300"C
MIN
MAX
Supply Voltage, VCC
5.0
9.5
Temperature, T A
0
+70
UNITS
V
"C'
fA
o
'It
electrical characteristics
CO
00
(Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
2.0
rnA
00
V ,H
logical "1" Input Voltage
o
I'H
Logical "l"lnput Current
Vee
= Max
IJ')
IJ')
V ,L
logical "0" Input Voltage
Vee
=
00
00
I,L
Logical "0" I nput Current
Vee = Max, Y,N = OAV
'OPON
Decimal Point Output Current
Vee = 6.00V, VOP = 3.3V, V ,N9 =4.5V, (pin 1), (Note 3)
IOPOFF
Decimal Point Output Current
Vee = 7.0V, VOP = 1.0V, V ,N9 = 4.5V, (Pin 11, (Note 3)
lOUT
Output Current
Vee = Min, Y'N = 4.5V, VOL = 1.5V
ICEX
Output Leakage Current
Vee = Max, V OH = 6.0V, liN = 40!J.A
1.0
40
VOL
Logical "0" Output Voltage
Vee = Min, Y,N = 4.5V, 10L = 50 rnA
1.0
1.5
V
ICC1
Supply Current
Vee:;;: Max,
0.001
0.1
rnA
~CC2
Decimal Point Supply Current
Vee =- M~x, VIN = 4.5V, V CC2 = Max
1.0
1.3
rnA
fA
fA
o
'It
'It
00
00
fA
o
Vee = Max, 10L = 50 rnA
I
I
4.5
Y,N = 6.5V
Y,N - 4.5V
4.0
V
1.3
0.50
0.65
rnA
Max
VIN :;;:
a
40
-4.0
004
V
60
!J.A
-6.0
rnA
-1.0
-50
-50
!J.A
rnA
!J.A
Note 1: "Absolute Maximum' Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for-actual device operation.
-Note 2: Unless otherwise specified, min!r'!lax limits apply across ,the aOc to +70°C temperature range. All typical values applyf or T A =: 25°C.
Note 3: Not applicable to DS8844, DS8855 or DS8865.
-
6-36
c
~
Display 0 rivers
........
C
~.
NA110NAL
00
CJI
057856/058856.058857. 057858/058858
BCO-to-7-segment LED drivers
0)
c
general description
This series of 7-segment display drivers fulfills a
wide variety of requirements for most active high
(common cathode) Light Emitting Diodes (LEOs).
Each device fully decodes a 4-bit BCD input into
a number from 0 through 9 in the standard 7segment display format, and BCD numbers above
9 into unique patterns that verify operation. All
circuits operate off of a single 5.0V supply.
en
00
In addition, with the use of an external current
limit rhistor per segment, this circuit can be used
in higher current non-multiplex LED applications.
It replaces the M50102.
CD
CJI
~
C
~
The 057858/058858 has active high outputs
with source current adjustable with the use of
external current limit resistors, one per segment.
This feature allows extreme flexibility in source
current value selection for either multiplex or
non-multiplex common cathode LED drive applications.lt allows the system designer freedom to tailor
the drive current for his particular applications.
The 057856/058856 has active-high, passive pullup outputs which provide a typical source current
of 6.0 mA at an output voltage of 1. 7V. The
applications are the same as for the OM5448/
OM7448 except that more design freedom is
allowed with higher source current levels. This
circuit was designed to drive the MAN-4 or equivalent type display directly without the use of
external current limit resistors, and replaces the
M50101.
CJI
00
........
c
en
00
00
CJI
00
features
• Lamp-test input
• Leadingltrailing zero suppression (RBI and
RBO)
• Blanking input that may be used to modulate
lamp intensity or inhibit output
• TTL and OTL compatible
• Input clamping diodes
The 058857 has active-h igh outputs and is designed to be used with common cathode LED's
in the multiplex mode. It provides a typical source
current of 50 mA at an output voltage of 2.3V.
connection diagram
Dual-I n-Line and Flat Package
I I I I I I
II I I I I
.' r L!: JB4 ),5 r r J:
------
.NPUTS
I
Order Number DS7B56J, DSBB56J,
DSBB57 J, ·DS7B5BJ, DS8B5BJ
~
CJI
0)
TEST
OUTPUT
IN'UT
------
INPUTS
TOI'VIEW
Order Number DS7B56W
or DS7858W
Order Number DSBB56N
or DSBB5BN
output display
IQ.
'I:::J'
•
SEOMENT IDENTIFICATION
10
IIUMlRltAL DESIGfilATIONS - REIUL TAfIT DISPlAYS
"
"
"
"
6-37
co
co
co
absolute maximum ratings
Q
Supply Voltage
It)
Ch
~
It)
~
operating conditions
(Note 1)
\
Input Voltage
Storage Temperature Range
Lead Temperature (Soldering, 10
~econdsl
Power Dissipation
Supply Voltage (Vee)
DS7856, DS7858
DS8856, DS8857
DS8858
Temperature (TA)
Dsn156,057858
DS8856, DS8857.
DS8858
Output Voltage
7.0V
5.5V
-65"e to +150"e
300"e
600mW
Q
....:
It)
}
}
MIN
MAX
4.5
5.5
V
4.75
5.25
V
-55
+125
"e
0
+70
"e
5.5
V
6.4
mA
60
50
mA
mA
All Circuits
~
Output Sink Current (per Segment)
Q
Output Source Current (per Segment)
DS7856, DS8856
(/)
DS8857
DS7858, DS8858
U)
It)
UNITS
co
co
(/)
Q
.......
electrical character.istics
U)
It)
~Q
(Note 2) The following is applicable to all parts.
PARAMETER
CONDITIONS
MIN
V ,H
Logical "1" Input Voltage
V ,L
Logical "0" Input Voltage
V OH
Logical "1" Output Voltage
Vcc = Min, lOUT = -200!-,A, 81/RBO Node
VOL
Logical "0" Output Voltage
Vee = Min, liN = 8.0 mA, 81/RBO Node
I'H
Logical" 1" Input Cu rrent
I'L
Logical "0" I nput Current
TYP
MAX
2.0
V
0.8
Vee = Max,
I
Except BI/RBO Node I
Vee = Max, V ,N = Oo4V
II
2.4
UNITS
3.7
0.3
V ,N = 204V
V ,N = 5.5V
V
V
0.4
V
40
!-'A
1.0
mA
ExceptBI/RBO Node
-1.6
mA
BI/RBO Node
--4.2
mA
Ise
Output Short Circuit Current
Vee = Max, BI/RBO Node
-4.0
mA
Veo
I nput Clamp Voltage
Vee = 5.0V, T A = 25°C, liN = -12 mA
-1.5
V
output characteristics and supply current
DS7856/DS8856 (Note 2)
PARAMETER
VOL
CONDITIONS
Logical "0" Output Voltage
MIN
Vee = Min, lOUT = 6.4 mA
TYP
MAX
0.25
004
UNITS
V
-6.0
-7.5
mA
-12
-15
mA
Outputs a through g
IOL
Ise
,
Logical "1" Load Current Available,
Outputs a through g
Output Short Circuit Current
Vee = 5.0V, V OUT = 1.7V
Vec = Max, (Note 3)
-4.7
Outputs a through g
Icc
Supply Current
Vee = Max
6-38
1-
DS7856
90
120
mA
058856
.90
130
mA
output characteristics and supply current (con't)
OS8857, OS7858/0S8858
(Notes 2 and 3)
PARAMETER
IOL
CONDITIONS
logical "1" load Current Available,
Vee
= 5.0V,
Vee
= 5.0V,
Vee
= Max
V OUT
MIN
= 2.3V,
TYP
-40
OS8857
MAX
UNITS
-60
rnA
Outputs a through g
V OH
logical "1" Output Voltage,
Outputs a through g
lee
Supply Current
lOUT
= -50
rnA, (Note 4)
I OS7858
I OS8858
2.7
3.2
2.9
3.2
V
V
60
c
en
rnA
CO
CO
U1
:oJ
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the ·-55()C to +12S0C temperature range for 057856, and 057858 and acrosS the
DoC to +70°C range for 058856, 058857 and 058858. All typicals are, given for VCC
= 5.0V and TA = 25°C.
Note 3: Care must be taken in not shorting the outputs to ground while they are in the "1" state because excessive current flow would result from
the Darlington upper stages.
Note 4: Special care must be tken in the use of the OS7858 ceramic (J) and the OS8858 plastic (N) DIP's with regard to not exceeding the maxi·
mum operating junction temperature of the devices. The maximum junction temperature of the DS7858J is 1750 C and must be derated based on
a thermal resistance of 90°C/watt, junction to ambient. The maximum junction temperature for the DS8858N is 150°C and must be derated based
on a thermal resistance of 120°C/watt junction to ambient.
truth table
I
INPUTS
DECIMAL
OR
FUNCTION
LT
RBI
0
1
1
1
1
X
2
1
X
3
1
X
4
1
X
5
1
6
7
8
D
0
0
C
8
0
0
0
0
A
BI/RBO
a
b
c
d
e
f
9
NOTE
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
0
0
1
0
1
1
0
0
0
0
1
1
0
0
1
1
0
1
1
1
1
1
0
0
0
1
1
1
1
1
0
0
1
1
1
0
0
1
X
0
·0
1
0
1
1
X
0
1
1
1
X
0
1
1
X
1
0
9
1
X
1
0
10
11
1
X
1
0
1
1
X
1
0
1
12
1
X
1
1
0
13
1
X
1
1
14
1
X
1
15
1
X
0
0
OUTPUTS
0
1
1
0
1
0
1
1
0
1
1
0
1
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
0
1
0
0
1
1
·0
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
0
0
1
1
1
1
0
0
1
0
1
1
1
0
1
0
1
0
1
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
BI
X
X
1
X
X
X
X
1
0
0
0
0
0
0
0
RBI
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
LT
0
X
X
X
X
X
1
1
1
1
1
1
1
1
4
2
Note 1: BI/RBO i. wire-AND logic serving as blanking input (BO and/or ripple-blanking output (R80). The blanking input (BI) must be open or
held at a logical "1 when output functions 0-15 are desired, and the ripple-blanking input (RBI) must be open or at a logical "1" if blanking of a
decimal 0 is not desired. X = input may be high or low.
Note 2: When a logical "0" is applied directly to the blanking input (forced condition) all segment outputs go to a logical "1" regardless of the
state of any other input condition.
Note 3: When the ripple-blanking input (RBO and inputs A, B. C and D are at logical "0." with the lamp test input at logical "1," all segment output. go to a logical "1" and the ripple-blanking output (R80) goes to a logical "0" (response condition).
If
Note 4: When the blanking input/ripple-blanking output (BI/R80) is open or held at a logical "1," and a logical "0" is applied to the lamp-test
input, all segment outputs go to a logical "0."
6-39
c
en
~
U1
CO
.......
c
en
CO
CO
U1
CO
co
an
co
co
en
output stage schematics
Q
,..-----..--0,,,
.......
co
an
~
en
Q
...:
Ien
an
Q,
CD
057856/058856
an
CO
CO
en
Q
.......
CD
an
~
Q
6·40
058857/
057858/058858
c
~
Display Drivers
en
CO
CO
U'1
CD
c
NAnONAL
en
CO
CO
058859. 058869 open collector hex latch LED drivers
en
CD
general description
The DS8859, DS8869 are TTL compatible open collector
hex latch LED drivers with programmable current sink
outputs. The current sinks are nominally set at 20 mA
but may be adjusted by external resistors for any value
between 0-40 mAo Each device contains six latches
which may be set by input data terminals. An active
low strobe common to all six latches enables the data
input terminals. The DS8859 current sink outputs are
switched on by entering a high level into the latches and
the DS8869 current sink outputs are switched on by
entering a low level into the latches.
The devices are available in either a molded or cavity
package. In order not to damage the devices there is a
limit placed on the power dissipation allowable for each
package type. This information is shown in the graph
included in this data sheet.
features
• Built-in latch
• Programmable output current
• TTL compatible inputs
• 40 mA output sink
logic diagram
output ci rcu it
058859
lOUT.
IAOJ
COMMON 15
CURRENT
CONTROL
STROBE
TO OTHER
CURRENT
SOURCES
TO OTHER
LATCHES
connection diagram
truth table
Dual-In-Line Package
IADJ
I"
15
INPUT 1 OUTPUT 1 INPUT 2 OUTPUT 2 INPUT 3 OUTPUT 3
14
13
12
11
I-
r-
1
9
10
1
3
4
5
6
7
STROBE INPUT 6 OUTPUT 6 INPUT 5 OUTPUT 5 INPUT 4 OUTPUT 4
COMMON
STROBE
INPUT
DATA
058859
OUTPUT
(t + 1)
OS8869
OUTPUT
(t + 1)
0
0
OFF
ON
0
1
ON
OFF
1
X
OUTPUT (t)
OUTPUT (t)
I'
GND
TOP VIEW
Order Number 058859J, 058869J
or 058859N, 058869N
6-41
absolute maximum ratings
Supply Voltage
Input Voltage
Output Voltage
operating conditions
(Note 1)
7V
5.5V
5.5V
-65°C to +150°C
300°C
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
electrical characteristics
MIN
MAX
Supply Voltage, V CC
4.75
5.25
Temperature, T A
0
PARAMETER
CONDITIONS
MIN
Logical "1" Input Voltage
Vee
=:
I'H
Logical "l"'nput Current
Vce
=Max, V'N =2.4V
V'L
Logical "0" Input Voltage
Vee = Min
liL
logical "0" I nput Current
Vee
Veo
Input Clamp Voltage
liN'" -12 rnA
10H
Log~cal
"1" Output Current
Vee
VOL
Logical "0" Output Voltage
Vee
=Min, V'L =O.8V, VOH =5.5V, V'H =2.0V
=Min,V'L = O.BV, 10L = 16 mA,
V'H
=
Supply Current
V
°c
(Notes 2 and 3)
V'H
Icc
+70
UNITS
Min
TYP
MAX
UNITS
40
/J.A
2.0
=Max, V ,N
2V, V ,ADJ
V
= D.4V
O.B
V
-1.0
-1.6
mA
-1.1
-1.5
250
0.4
V
/J.A
V
=VCCMIN
Vee = Max, Current Sources "OFF,"
50
mA
26
rnA
(See Truth Tablel. (Note 4)
'SINK
Output Current
Vee
TA
= S.OV, V OUT = 2.0V,
=25°C, (Note 4)
I
1
V 1ADJ
'"
'ADJ -
Open
Vee
40
MIN
switching characteristics
tpd1
Propagation Delay to a Logi.cal "0"
Propagation Delay to a Logical "1"
20
,
PARAMETER
tpdO
rnA
12
CONDITIONS
Vee = 5.0V, T A = 25°C, COUT
RL = 390fl, (Note 5)
Vee
RL
= 5.0V,
TA
= 15 pF,
= 25'C, COUT = 15 pF,
=390Sl., (Note 5)
MIN
TYP
MAX
UNITS
Data to Output
Strobe to Output
36
ns
50
ns
Data to Output
Strobe to Output
150
ns
150
ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Not. 2: Unless otherwise specified minImax limits apply across the (fC to +70°C temperature range. All typicals are given for Vee e S.OV and
TA=25°C.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted.
All values shown as max or min on absolute value basis.
Not. 4: See graphs for changes in 'SINK versus changes in temperature and Vec.
Note 5: COUT includes device output capacitance of approximately 8.5 pF and wiring capacitance.
-
642
,
typical performance characteristics
ISINK
Max Power Dissipation Curves
50r-~r_-,~_r---r--,
46
1
40
f--I\--+--"."\.".-tCAVIT~I\
"
~
3D
...
25 I-::-:-::MOLOE0-l.---+---f--I'......"."",
20 PACKAGE (N)
-
15
Vee:: 5V
10
CURVE ASSUMES ALL
Oi'
f---t--Tt--f---"'I.---t
~
j
I'
........
OUTPUT~
5 BEINGINAT~A=W~
30
f------+-----,oLf----1
20
f-------b~--t---l
2.0
3.0
4.0
~
10
/
oV
1--
0'---'--'--'--'---'
1.0
V,ADJ (S•• Figur.l)
40r---~----~V'~~
PACKAGE (J)
35~-+~\~\---+~,,~--~
i
YS
r----T-A,.'r2-5-0C----,---~--~
00
5.0
2.0
4.0
3.0
VOLTS ACROSS OUTPUT
5.0
V1ADJ (VOLTS)
.6. ISINK vs Temperature
30
25
20
15
10
g 5
<
0
-5
5 rnA.)
II:
Don't Care
OUTPUT
1
0
1
Hi-Z
x = Don't Care
"Specification. may change
7-1
absohJ,te
,
,
~ ~
"
.",>
m~xip1um
,
ratings
(Note
operating conditions,.
11
,,"',
';',1,
MIN
',.
,.t,
Supply Voltaga
Input Voltage (gate)
Input Pi ode Forward Current
.
.
~,'
"
Input Diode Reverse Voltage
Output Voltage
053660
053661
:Storage 'Temperature Range
Lead Temperature (Soldering, 10 seconds)
7V
5.5V
20mA'
5V
MAX
UNITS
Supply Voltage, VCC
4.5
5.5
,V
.T,mperature, TA
0, '
+70"
°c
-71t
5.5V
-55°C'to +125°C
300°C
~:
electrical chaJacteristics (ooe _70°CI
(Note
21
"
PARAMETER
..
CONDITiONS
< 0.4V, lOUT (Sink) = 16 mA
> 2.4V, lOUT (source) ':' -400f.tA
IINI!)
Logical" 1" I nput Current
V OUT
liN CO)
Logical "0" I nput Current
V OUT
V INI!)
Logical "1" Input Voltage
(See Truth Table for Output State)
Logical "0" Input Voltage
MAX
5
2.0
!..ogieal "1" Input Curr~nt '
/.tA,
V
..
(See Truth Table for Output State) ,
0.8
'I
V
VIN =+2.4V
40
p.A
VIN = O.4V
-1.6
mA
liN = -12 rnA, TA = 25°C
-1.2
V
(Strobe, Disable)
IIH
UNITS
mA
250
(Strobe, Disable)
VINCO)
TYP
MIN
(Strobe, Disable)
IlL
Logical "0" I nput Current
(Strobe, Disable)
V CL
Input Clamp Voltage
(Strobe, Disable)
V OH
Logical "1" Output Voltage
lOUT (Spuree) = -400p.A
VOL
Logical "0" Output Voltage
lOUT (Sink) = 16 rnA
100
Output Disable Current
Va =2.4V
Vo =0.4V
Icc
~
Supply Current
IIN'=5mA
,V
0.4
V
053661
40
p.A
053661
-40
p.A
VSTROBE'" 2V
053660
10
15
rnA
VOISABLE =2V
053661
12
18
rnA
VF
Input Diode Forward Vol'tage , :
;rA = 25°C,
V BR
Input Diode Reverse Breakdown
TA = 25°C, liN =-100J.lA
VIsa
DC Isolation (lnput·Output)
TA = 25°C
CM Rv
AC Common Mode Rejection
V
1.75
liN = lOrnA
5
V
1500
V
V AC,
p.p
200
' ·f = 1 MHz" OutPUt lVIeets Worst·Case VOL
(lnput·Output)
and V OH Levels (above)
"
7·2
2.4
,
,
switching characteris,tics
c
C/)
(Note 3)
w
en
en
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
o
.......
tpdO
Propagation Delay to Logical "0"
from LED Input
liN = 7.5 mA, Strobe High, Disable Low,
(Note 4)
70
ns
cC/)
tpd1
Propagation Delay to Logical "1"
70
ns
from LED Input
liN = 7.5 mA, Strobe High, Disable Low,
(Note 4)
..
Propagation Delay to Logical "0"
liN = 7.5mA, Disable Low
15
ns
15
ns
6
ns
tso
w
en
en
from Strobe Input
tS1
Propagation Delay to Logical "1"
from Strobe Input
liN
= 7.5 mA, Disable Low
t1H
Delay from Disable Input to High
Impedance State, from Logical
"1" Level
liN
= 0 mA, Strobe High
toH
Delay from Disable Input to High
Impedance State, from Logical
"0" Level
liN
= 7.5 mA, Strobe High
12
ns
tH1
Delay from Disable Input to
Logical "1" Level, from High
liN
= 0 mA, Strobe High
14
ns
tHO
Delay from Disable Input to
liN
= 7.5 mA, Strobe High
10
ns
Impedance State
Logical "0" Level, from High
Impedance State
Note 1: "Absolute Maximum Ratings" are th~e values beyond which the safety of the device cannot be guaranteed: Except for '''Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: These apply !'IIer. Vee range 4,5V to 5,5V. unless otherwise noted. Typicals given for T A = 25°e, Vee
value in all cases.
= 5.0V. Max refers to abSOlute
.
Note 3: All switching response characteristics given for output Pull-up resistor RL = 3900, shunt capacitance eL = 15 pF.
delays are independent of LED drive configuration, e.g., the same performance will be obtained with either test circuit
shown below:
Note 4: These'propagation
.'
ac test circuits
I
..v
I+
5V
PULSE
GEWER~TOR
1I
~~
r-430
L
430
I
PULSE
GENERATOR
':'
Positive Input Pulse
~,
+5V
~
o
L
1"1:
I
Nogative Input. Pulse
7-3
oCD
N
I-
(,)
Z
Q
Q
e
z,
NCT200, NCT260 phototransistor opto-coupler
general description
absolute maximum ratings
The NCT200 and NCT260 are Gallium Arsenide diodes
coupled with an NPN Silicon phototransistor in a'six
lead Epoxy duaf.in~line package. These devices feature
isolation voltage in excess of 2 kV. A GaAs light
emitting diode radiates infrared light into a photo·
sensitive transistor providing electrical isolation equiva·
lent to a relay.
-55°C to +150°C
Storage Temperature
-55°C to +100°C
Operating Temperature
Total Power Dissipation at 25°C
250mW
3.3 mW('C
Derate Li nearly
LeadTemperature (Soldering, 10 seconds)
260°C
These devices are ideally suited where coupling is
needed between two circuits but electrical isolation
must be maintained. These devices find a wide range
of application in data transmission as well as linear
coupling.
output transistor
applications
input diode
2000V isolation
High direct-current transfer ratio
0.5 pF coupling cap.
Standard dual-in-line package
"Dictated by maximum power disSipation.
connection diagram
Dual·ln-Line Package
1.......r---t"8
ANODE -"I--
'~
. . . . ....! r--
NC..l.
~
BAS,
LC ....._.,
l.!..
EMITTER
TOP VIEW
Order Number
NCT200 or NCT260
7·4
(TA = 25°C)
Power Dissipation
Derate Lin~arlY from 25°C
Forward DC Current Continuous
Forward DC Current Intermittent Duty~,
Reverse Voltage
Peak' Forward Current (1 pulse; 300 pps)
features
200mW
2.6mWtC
30V
70V
7V
VeEo ,
VeER (1 Mn)
V Eeo
• Phase control
• Feedback control
• T~lephone line receiver
• Line to digital logic isolation
• Solid state relays
•
•
•
•
(TA = 25~C, IF = 0)
Power Dissipation
Derate Linearly from 25°C
200mW
.2.6 mW('C
60mA
150mA
3V
3A
z
electro-optical characteristics
a
(T A = 25°C, unless otherwise specified)
CONDITIONS
PARAMETER
MIN
o
o
UNITS
TYP
MAX
1.2
1.5
V
10
/J.A
z
INPl!TDIODE
Forward Voltage
IF =60mA
IR
Reverse Leakage Current
V R = 3.0V
C
Capacitance
V = 0, f = 1 MHz
VF
150
n
~
Q')
o
pF
OUTPUT TRANSISTOR, IF = 0
HFE
de Forward Current Gain
leER
Collector-Emitter Current
VCE = 10V, Ic = 1 mA, NCT200
500
I NCT200
I NCT260
VCE = 10V, R = lMn
50
nA
100
nA
LV CEO
Collector-Emitter Sustaining Voltage
Ic = 1.0mA
30
60
V
BV cER
Collector-Emitter Breakdown Voltage
Ic = 100/J.A, R = 1 Mn
70
110
V
BV CBO
Collector-Base Breakdown Voltage
Ic = 10/J.A
70
110
V
BV Eco
Emitter-Collector Breakdown Voltage
Ic = 100/J.A
7
8.2
V
20
60
%
%
COUPLED CHARACTERISTICS
IcllF
de Current Transfer Ratio
IF = 10 mA, VCE = 10V,
RBE = 1 Mn
VCE(sATl
Collector-Emitter Saturation Voltage
I NCT200
I NCT260
6
0.2
IF = 15.0 mA, Ic = 1.6 mA, NCT200
IF = 50 mA
Ilc = 6.4 mA Pulsed NCT200
0.4
V
0.4
V
0.5
Ilc - 1.6 mA, NCT260
V
Vise
Isolation Voltage
Rlso
Isolation Resistance
V,so = 500V
10 11
elsa
I solation Capacitance
t= 1 MHz
0.5
pF
kHz
V
2000
n
BW
Bandwidth (Note)
IF = 10 mA, Vcc = 5.0V. RL = lOOn
150
tON
Output "ON" Time
IF = 10 mA, VCE = 4.0V, RL = 22n
2.0
/J.s
tOFF
Output "OFF" Time
IF = 10 mA, VCE = 4.0V, RL = 22n
3.0
/J.s
Note: Bandwidth is specified as the point where the collector current transfer ratio is 1/2 that of the low frequency current transfer ratio
(100 Hz!.
switching time waveforms
,
"PUT""'~
'.::::~
Ic"'O
lo~ ~
PULSE WIDTH = 8jJs
DUTY CYCLE" 10%
VCE
>:<4.DV
ltoFF
7-5
~
~
NATIONAL
4N25, 4N26, 4N27, 4N28 phototransistor
opto-coupler
general description
absolute maximum ratings*
(TA~ 2SoC, unless otherwise specified)
Gallium Arsenide LED optically coupled to a Silicon
Photo Transistor designed for applications requiring
electrical isolation, high-current transfer ratios, small
package size and low cost; such as interfacing and
coupling systems, phase and feedback controls, solidstate relays and general~PtJrpose switching circuits_
-55°C to +150°C
Storage Temperature
Operating Temperature
-5SoC to +100°C
Total Power Dissipation at 2SoC
250 mW
Derate Linearly
3_3 mW;oC
Lead Temperature (Soldering, 10 seconds)
260°C
applications
•
•
•
•
•
phototransistor*
Phase control
Feedback control
Telephone line receiver
Line to digital logic isolation
Solid state relays
(T A ~ 25°C)
Power Dissipation
Derate Linearly from 2SoC
VCEO
VECO
VCBO
150mW
2 mW;oC
30V
7V
70V
features
•
•
High isolation voltage
VISO ~ 2S00V (min) 1500V (min) SOOV (min) High Collector Output
4N25
4N26, 4N27
4N2S
Current
infrared emitting diode*
, Power Dissipation
Derate Linearly from 25°C
Forward DC Current Continuous
Reverse Voltage
Peak Forward Current (1 pulse; 300J,ls)
atlF~10mA
Ie ~ 10 mA (typ) 4N2S, 4N26
• 0_5 pF coupling cap_
• Standard dual-in-line package
*JEDEC Registered Data,
connection diagram
Dual-I n-Line Package
ANODE....!..r-!-,
CATHODE.2. -
~r-_--I.::.6_ BASE
~
LC fLl
NC.2
COllECTOR
rL-EMITTER
TOP VIEW
Order Number
4N25, 4N26, 4N27 Dr 4N28
7-6
(TA ~ 25°C)
150mW
2 mW;oC
SOmA
3V
3A
electro-optical characteristics
(T A = 25°C, unless otherwise specified)
CONDITIONS
PARAMETER
MIN
TYP
MAX
UNITS
100
ilA
1.5
LED CHARACTERISTICS
IR
Reverse Leakage Current
V R = 3.0V. (Note 41
VF
Forward Voltage
IF - 50 rnA. (Note 41
1.2
C
Capacitance
V R =OV, f= 1.0 MHz
150
V
pF
PHOTOTRANSISTORS, IF = 0
= 500ilA
SOO
HFE
de Current Gain
VeE = 5.0V.le
leBo
Collector-Base Dark Current
Ves
BV CBO
Collector-Base Breakdown Voltage
Ie
= 100ilA.
BVCEO
Collector-Emitter Breakdown Voltage
Ie
= 1.0 rnA,
BVepo
Emitter-Collector Breakdown Voltage
IE = 100ilA, 18
I CEO
Collector-Emitter Dark Current
VeE = lOV, Base Open, 14N2S, 4N26, 4N27
SO
nA
(Note 41
100
nA
= 10V, Emitter
= 0,
IE
= 0,
nA
70
V
(Note 41
30
V
(Note 41
7.0
(Note 41
= 0,
18
20
Open, (Note 4)
V
14N2B
COUPLED CHARACTERISTICS
Ie
Collector Output Current
VeE = 10V, IF
I.
VIsa
= 0,
= 10 rnA,
(Note 41
14N2S,4N26
2.0
14N27 ,4N2B
1.0
14N2S
I 4N26,4N27
I 4N2B
Isolation Voltage
(Note 41
= 2.0 rnA,
VeE (SAT)
Collector-Emitter Saturation
Ie
GISO
Isolation Capacitance
V = 0, f
BW
Bandwidth
IF
= lOrnA, VeE
tON
Output "ON" Time
IF
=
IF
= SO rnA,
rnA
V
lS00
V
SOO
= lOOn,
(Note 31
Fixed P.W. 8J1s
Fixed ~ 10% dc, VeE "'- 4V Fixed, RL
V
0.2
(Note 41
= S.OV, RL
=
rnA
2500
= 1.0 MHz
10 rnA, pK
10
=
O.S
V
O.S
pF
150
kHz
1
ils
4
ilS
1011
n
22H,
(Notes 1 and 2)
tOFF
Output "OFF" Time
= 10 mA, pK "" Fixed P.W. 8}1s Fixed
== 10% dc, VeE'" 4V Fixed, RL "" 22r2,
Rlso
Isolation Resistance
V
IF
(Notes 1 and 2)
Note 1: Test conditions: from t
= 0 of
= SOOV
IF until Ie exceeds 1.0 mAo
Note 2: Test condition: from end of 1F until Ie decreases below 1.0 rnA.
Note 3: Specified as the point where the collector current transfer ratio is one~half that of the low frequency C.T.R. (100 Hz).
Note 4: JEDEC Registered Data.
switching time waveforms
'NPUT""O~
':'::~
PULSE WIDTH "B/Js
DUTY CYCLE ",10%
VCE "4.0V
Ic"O
.
1o,
'0"
7-7
~
~
I
Applications
N
N
...5'
....
NAnoNAL
CD
C
I»
INTEGRATED CIRCUITS FOR
DIGITAL DATA TRANSMISSION
~
~'
n
c
;=j.'
(II
.0INTRODUCTION
c
It is frequently necessary to transmit digital data
in a high-noise environment where ordinary integrated logic circuits cannot be used because they
do not have sufficient noise immunity. One solution to this problem, of course, is to use highnoise-immunity logic. In many cases, this approach
would require worst case logic swings of 30V,
requiring' high power-supply voltages. Further,
considerable power would be needed to transmit
these voltage levels at high speed. This is especially
true if the lines must be terminated to eliminate
reflections, since practical transmission lines have a
low characteristic impedance.
A much better solution is to convert the ground
referred digital data at the transmission end into a
differential signal and transmit this down a balanced, twisted-pair line. At the receiving end, any
induced noise, or voltage due to ground-loop currents, appears equally on both ends of the
twisted-pair line. Hence, a receiver which responds
only to the differential signal from the line will
reject the undesired signals even with moderate
voltage swi ngs from the transmitter.
Figure 1 illustrates this situation more clearly.
When ground is used as a 'signal return as in Figure la, the voltage seen at the receiving end will be
the output voltagE: of the transmitter plus any
noise voltage induced in the signal line. Hence, the
noise immunity ·of the transmitter-receiver combination must be equal to the maximum expected
noise from both sources.
The differential transmission scheme diagrammed
in Figure 1b solves this problem. Any ground noise
or voltage induced on the transmission lines will
appear equally on both. inputs of the receiver. The
receiver responds only to the differential signal
coming out of the twisted-pair line and delivers a
single-ended output signal referred to the ground
DATA
a
I»
.
DATA
OUTPUT
INPUT
-t
I»
~
(II
3
GROUND
I.
GROUND A
Single-Ended System
NOISE
iii'
(II
GROUNa.
O·
~
INDUCEO
NOISE
DATA
DATA
OUTPUT
INPUT
GROUND
GROUND A
NOISE
GROUND B
h.DifterentialSvltem
FIGURE 1. Comparing Differential
and Single-Ended
Data Transmission
at the reCeiving end. Therefore, extremely high
noise immunities are not needed; and the transmitter and receiver can be operated from the same
supplies as standard integrated logic circuits.
Th is article describes the operation and use of a
line driver and line receiver for transmission systems using twisted-pair lines_ The transmitter provides a buffered differential output from a DTL or
TTL input. signal. A four-input gate is included on
the input so that the circuit can also perform logic.
The receiver detects a zero crossing in the differential input voltage and can directly drive DTL C?r
TTL integrated circuits at the receivin!l end. It also
has strobe capability to blank out unwanted input
signals. Both the transmitter .and .the receiver incorporate two independent units on a single silicon
chip.
8-1
r:::
.2III
.!!!
E
III
r:::
e
~
!!!
LINE DRIVER
'!'II
C
i6
....
Figure 2 shows a schematic diagram of the line
transmitter. The circuit has a marked resemblance
to a standard TTL buffer. In fact, it is possible to
. use a standard dual buffer as a transmitter. How·
ever, the DS7830 incorporates additional features .
For one, the output is current limited to protect
the driver from accidental shorts in the transmis·
sion lines. Secondly, diodes on the output clamp
severe voltage transients that may be induced into
the transmission lines. Finally, the circuit has
internal inversion to produce a differential output
signal, reducing the skew between the outputs and
making the output state independent of loading.
:§1
c
...
.2
....III
'5
~
U
"C
$
e
....~
.5
N
N
I
Z
«
NAND
• OUTPUT
...---..-..........- ..........-,.
to give a NAN D output. A low state logic input on
any of the emitters of 09 will cause the base drive
to be removed from 010, since 09 will be
saturated by current from R8, holding the base of
010 near ground. Hence, 010 and all will be
turned off; and the output will be in a high state.
When all the emitters of 09 are at a one logic level,
010 receives base drive from R8 through the for·
ward biased collector-base junction of 09. This
saturates 010 and also all, giving a low output
state. The input voltage at which the transition
occurs is equal to the sum of the emitter-base turn
on voltages of 010 and 01 i minus the saturation
voltage of 09. This is about 1.4V at 25°C.
A standard "totem-pole" arrangement is used on
the output stage. When the output is switched to
the high state, with 010 and all cut off, current
is supplied to the load by 013 and 014 which are
connected in a· modified Darlington configuration.
Because of the high compound current gain of
these transistors, the output resistance is qu ite low
and a large load current can be supplied. Rl0 is
included across the emitter-base junction of 013
both to drain off any collector-base leakage current in 013 and to discharge the. collector-base
capacitance of a 13 when the output is switched to
the low state. In the high state, the output level is
approximately two diode drops below the positive
supply, or roughly 3.6V at 25°C with a 5.0V
supply .
With the output switched into the low state, 010
saturates, holding the base of 014 about one diode
drop above ground. This cuts off .013. Further,
both the base current and the collector current of
010 are driven into the base of all saturating it
and giving a low-state output of about 0.1 V'. The
circuit is designed so that the base of all is
supplied 6 mA, so the collector can drive considerable load current before it is pulled out of
saturation.
FIGURE 2. Schematic Diagram of the DS7830 Line
Driver
As can be seen from the upper half of Figure 2, a
quadruple·emitter input transistor, Og, provides
four logic inputs to the transmitter. This transistor
drives the inverter stag~ formed by O~O and all
8-2
The primary purpose of R 12 is to provide current
to remove the stored charge in a 11 and charge its
collector-base capacitance when the circuit is
switched to the high state. Its'value is also made
enough less than R9 to prevent supply current
transients which might otherwise occur" when the
power supply is coming up to voltage.
*J. Kalb, "Design Considerations for a TTL Gate,
"Nationa/Semiconductor TP-6, May, 1968.
»
z
I
N
N
S'
;
CQ
iil
The lower half of the transmitter in Figure 2 is
identical to the upper, except that an inverter
stage has been added. This is needed so that an
input signal which drives the output of the upper
half positive will drive the lower half negative, and
vice versa, producing a differential output signal.
Transistors Q2 and Q3 produce the inversion. Even
though the current gain is not necessarily needed,
the modified Darlington connection is used to pro:
duce the proper logic transition voltage on the
input of the transmitter. Because of the low load
capacitance that the inverter sees when it is com·
pletely within the integrated circuit, it is extreme·
Iy fast, with a typical delay of 3 ns. This minimizes
the skew between the outputs.
One of the schemes used when dual buffers are
employed as a differential line driver is to obtain
the NAN D output in the normal fashion and pro·
vide the AND output by connecting the input of
the second buffer to the NAND output. Using an
internal inverter has some distinct advantages over
this: for one, capacitive loads which slow down
the response of the NAND output will not intro·
duce a time skew between the two outputs;
secondly, line transients on the NAND output will
not cause an unwanted change of state on the
AND output.
Clamp diodes, D1 through D4, are added on all
inputs to clamp undershoot. This undershoot and
ringing can occur in TTL systems because the rise
and fall times are extremely short.
Output-current limiting is provided by adding a
resistor and transistor to each of the complementary outputs. Referring again to Figure 2, when
the current on the NAND output increases to a
value where the voltage drop across R 11 is sufficient to turn on Q12, the short circuit protection
comes into effect. This happens because further
increases in output current flow into the base of
Q12 causing it.to remove base drive from Q14 and,
therefore, Q13. Any substantial increase in output
current will then cause the output voltage to collapse to zero. Since the magnitude of the short
circuit depends on the emitter base turn:on voltage
of Q12, this current has a negative temperature
coefficient. As the chip temperature increases
from power dissipation, the available short circuit
current is reduced. The current limiting also serves
to control the current transient that occurs when
;
the output is going through a transition with both
Q11 and Q13 turned on.
Co
(')
n
The AND output is similarly protected by R6 and
Q5, which limit the maximum output current to
about 100 mA, preventing damage to the circuit
from shorts between the outputs and grou nd.
c:
;j.'
III
.
0-
The current limiting transistors also serve to increase the low state output current capability
under severe transient conditions. For example,
when the current into the NAND output becomes
so high as to pull Q 11 out of saturation, the output voltage will rise to two diode drops above
ground. At this voltage, the collector-base junction
of Q12 becomes forward biased and supplies additional base drive to Q11 through Q10 which is
saturated. This minimizes any further increase in
output voltage.
c
~
II)
-I
iil
::s
III
3
When either of the outputs are in the high state,
they can drive a large current towards ground
without a significant change in output voltage.
However, noise induced on the transmission line
which tries to drive the output positive will cut it
off since it cannot sink current in this state. For
this reason, D6 and D8 are included to clamp the
output and keep it from being driven much above
the supply voltage, as this could damage the
circuit.
iii'
III
S'
::s
When the output is in a low state, it can sink a lot
of current to clamp positive-going induced voltages
on the transmission line. However, it cannot
source enough current to eliminate negative-going
transients so D5 and D7 are included to clamp
those voltages to ground.
It is interesting to note that the voltage swing
produced on one of the outputs when the clamp
diodes go into conduction actually increases the
diffferential noise immunity. For example with
no induced common mode current, the low-state
output will be a saturation voltage above ground
while the high output will be two diode drops
below the positive supply voltage. With positivegoing common mode noise on the line, the low
output remains in saturation; and the high output
is clamped at a diode drop above the positive
supply. Hence, in this case, the common mode
noise increases the differential swing by three
diode drops.
8·3
I:
o
'iii
,~
E
I/)
c
~
I-
"'-
~
ca
'
Q
....... .......::
...........
ca
,~
,2'
,t:t+
.l'~5°C
~
,
""",l5 0 C
..
Q
....o
o
I/)
,~
I
o
25
50
75
100
125
150
OUTPUT SOURCE CURRENT {mAl
:::J
~
FIGURE 3. High State Output Voltage as a Function of
(J
Output Current
i
..en
Having explained the operation of the line driver,
it is appropriate to look at the performance in
more detail. Figure 3 shows the high·state output
characteristics under load. Over the normal range
of output currents, the output resistance is about
lOn. With higher output currents, the short circuit
protection .is activated, causing the output voltage
to drop to zero. As can be seen from the figure,
the short-circuit current decreases at higher
temperatures to minimize the possibility of overheating the integrated circuit.
.
~
..
Q)
.E
N
N
I
~
50
15
100
iI"'"
125
150
OUTPUT SINK CURRENT {mAl
FIGURE 4. Low.-State Output Current as a Function-of
Output Current
Figure 4 is a similar graph of the low-state output
characteristics. Here, the output resistance is about
5n with normal values of output current. With
larger currents, the output transistor is pulled out
of saturation; and the output voltage increases.
This is most pronounced at _55°C where the transistor current gain is the lowest. However, when
the output voltage rises about two diode drops
above ground, the collector-base junction of the
current-limit transistor becomes forward biased,
8-4
V+=!iV
,,'"
ll. . . . ~
~
,
,I
0
50n
,
\,
25°C
-55°C
25
50
125°C
15
100
125
150
OUTPUT CURRENT {mAl
I
~25'CT
25
IRL
00
25'C
o
.1
1RL-200n
-... ~o100~
,
I
,.../
o
The curves in Figures 3 and 4 demonstrate the
performance of the line driver with large, capacitively-coupled common-mode transients, or under
I,ll
II
_551c
It is clear from the figure that the low state output
current is not effectively limited. Therefore, the
device can be damaged by shorts between the output and the 5V supply. However, protection
against shorts between outputs or from the outputs to ground is provided by limiting the highstate current.
1,1
I
V+:II 5V
providing additional base drive for the output transistor. This roughly doubles the current available
for clamping positive common-mode transients on
the twisted-pair line. It is interesting to note that
even though the output level· increases to about
2V under this condition, the differential noise
immunity does not suffer because the high-state
output also increases by about 3V· with positive
going common-mode transients .
FIGURE 5. Differential Output Voltage as a Function of
Differential Output Current
gross overload conditions. Figure 5 shows the
ability of the circuit to drive a differential load:
that is, the transmission line. It can be seen that
for output currents less than 35 mA, the output
resistance is approximately l5n. At both temperature extremes, the output falls off at high currents.
At high temperatures, this is caused by current
limiting of the high output state. At low temperatures, the falloff of current gain in the lowstate output transistor produces this result.
Load lines have been· inCluded on the figure to
show the differential output with various load
resistances_ The output swing can be read off from
the intersection of the output characteristic with
the load line. The figure shows that the driver can
easily handle load resistances greater than lOOn.
z>
I
N
N
:;
r+
(1)
(Q
This is more than adequate for practical, twisted·
pair lines.
25
:!
Figure 6 shows the no load power dissipation, for
one·half of the dual line driver, as a function of
frequency. This information is important for two
reasons. First, the increase in power dissipation at
high frequencies must be added to the excess
power dissipation caused by the load to determine
the total package dissipation. Second, and more
important, it is a measure of the "glitch" current
which flows from the positive supply to ground
through the output transistors when the circuit is
going through a transition. If the output stage is
15~
~
~
~
125
~l:l.
100
e-
75
iii
Q
rW)·
r-t~-rl
,:;f '->~
a:
50
f
25
1/
~
1.1
V
rn,,-
~
ONE SlOE
0.1
1.0
'"'"
10
z
I--'"
I
Q
.,
n
c
"....
c
i=
"....
;:+
en
.,o
o
-75 -50 -25
0
25
50
75 100 125
o
TEMPERATURE 1°C)
c.Q'
::.:
2!.
FIGURE 7. Propagation Time as a function of Temperature
o
Q)
r+
"'~
~
15
i=
S'
c.
Q)
-
'/
"'~
"
iil
v+ =5V
20
10
100
SWITCHING FREOUENCY IMHz)
FIGURE 6. Power Dissipation as a Function of Switching
frequency
not properly designed, the current spikes in the
power supplies can become quite large; and the
power dissipation can increase by as much as a
factor of five between 100 KHz and 10 MHz. The
figure shows that, with no capacitive loading, the
power increase with frequencies as high as 10 MHz
is almost negligible. However, with large capacitive
loads, more power is required.
The line receiver is designed to dp.tect a zero cross·
ing. in the differential output of the line driver.
Therefore, the propagation time of the driver is
measured as the time difference between the appli·
cation of a step input and the point where the
differential output voltage crosses zero. A plot of
the propagation time over temperature is shown in
Figure 7. This delay is added directly to the propa·
gation time of the transmission line and the delay
of the line receiver to determine the total data·
propagation time. However, in most cases, the
delay of the driver is small, even by comparison to
the uncertainties in the other delays.
To summarize the characteristics of the DS7830
line driver, the input interfaces directly with stan·
dard DTL or TTL circuits. It presents a load which
is equivalent to a fan out of 3 to the circuit driving
it, and it operates from the 5.0V, ±10% logic
supplies. The output can drive low impedance lines
down to 50n and capacitive loads up to 5000 pF.
The time skew between the outputs is minimized
to reduce radiation from the twisted'pair lines, and
the circuit is designed to clamp common mode
transients coupled into the line. Short circuit pro·
tection is also provided. The integrated circuit con·
sists of two independent drivers fabricated on a
41 x 53 mil·square die using the standard TTL
process. A photomicrograph of the chip is shown
in Figure 8.
...
-I
Q)
~
en
3
en
en
0'
~
FIGURE 8. Photomicrograph of the DS78300ual Line
Driver
8·5
c:
o
'0
,!!!
.~
c:
....E
...eaea
LINE RECEIVER
o
,---
>
0.2
0.1
I'- r-!4:.•ksv 1
::i
;: -11.1
~
~
-11.2
2i
-0.3
4
4.1
5
5.5
8
SUPPLY VOLTAGE (VI
FIGURE 12. Differential I"put Voltage Required for
Hi~ or Low Output as a Function of Supply Voltage
c
~
"
>
Figure 13 is a similar plot for varying common
mode input voltage. Again the differential input
voltages are given for high and low states on the
output with a worst case fanout of 2. With
precisely matched components within the
integrated circuit, the threshold voltage will not
">....
E
..
i
C/
;:
2i
I
..
0
I I I
1 1 1
-10
0
10
is!!
.
~
~
~
....
t-
-20
~
tt:£
~
("15V 1-
-11.4
Li~
~>
....
:0
I .1 .oL.::I-~ t,••,,'OU'=2.5V
~·O.2 ..",
J rI - ~u;~
, oU'-35
_
-11.2
I I' j'" 0.2
'11'
-0.4
-0.2
~'
IZ5'C
1
•
0.2
0.4
The transfer function of the circuit is given in
Figure 14. The loading is for a worst case fanout
of 2. The digital load is not linear, and this is
reflected as a non-linearity in the transfer function
which occurs with the outP~t around 1.5V. These
transfer characteristics show that the only
significant effect of temperature is a reduction in
the positive swing at -55°C. However, the voltage
available remains well above the 2.5V required by
digital logic.
~
ITA .125,cl-
t-.
,
-I£''r'-
25'C
DIFFERENTIAL INPUT VOLTAGE (VI
~
0.4
cS'
[11'---
I
~
..~
c
If
C>
~
~
~
II'C ......,~J
:0
•
. "'"
j. ;'"
I
I
3
5 z
~
Cc
~
I I
4 - Y+'5V
FAN OUT· 2
FIGURE 14. Voltage Transfer Function
.I .
""":'
~
..
~
T.125,J
Vci'O - -
c
ill
5
0.3
I
0""0-2
"'4
0 ~~"O.4VI
-~~~",""'I'-
5
change with common mode voltage. The
mismatches typically encountered give a threshold
voltage change of ±100 mV over a ±20V common
mode range. This change can have either a
positive slope or a negative slope.
2D
INPUT VOLTAGE (VI
FIGURE 13. Differential Input Voltage Required for
High or Low Output as a Function of Common Mode Voltage
:0
C>
4
2
0
-2
I
J-
1 I
1
-4
4
3
Z
I
0
0
~
Vee - 5V
TA'21'C-
-,
_J cdl'IY - 100 pF
"
I
(Cd.IIY· O
0.2
0.4
0.6
o.a
TIME 1;1.1
FIGURE 15. Response Time With and Without an External Delay Capacitor
Figure 15 gives the response time, or propagation
delay, of the receiver. Normally, the delay through
the circuit is about 40 ns. As shown, the delay can
be ,i ncreased, by the addition of a capacitor'
between the response-time terminal and ground, to
make the device immune to fast noise spikes on
the input. The delay will generally be longer for
negative going outputs than for positive gciing
outputs.
8-9
S
'iii
.!!!
E
II)
c
I!
I-
ea
;
Q
.~
.21Q
10
Under normal conditions, the power dissipated in
the receiver is relatively low. However, with large
common mode input voltages, dissipation increases
markedly, as shown in Figure 16. This is of little
consequence with common mode transients, but
the increased dissipation must be taken into
account when there is a dc difference between the
grounds of the transmitter and the receiver. It is
important to note that Figure 16 gives the
dissipation for one half the dual receiver. The total
package dissipation will be twice the values given
when both sides are operated under identical
conditions.
.....
0.
Y+'5V ' -
1
ONESIOE-
~~,l
..... ......
~o.._
r.....
Ofl",.
'lI~
~q"
r-...
-2
-20
-10
1"'0.
I",
1"'0.
10
r--.
ZO
INPUT VOLTAGE (V)
FIGURE 17. Power SupplV Current as a Function of
Common Mode Input Voltage
30a
y+
I..
. zoa 1\'~
l5.0J r-
OUTPUT LOW
ONE SIDE
;::
i
CI
co
~
L
'~
100
2
1/1
~
o
-zo
-10
Z5~
r~
"IZ5°C
=-= ~' -j
10
zo
The variation of the internal termination resistance
with temperature is illustrated in Figure 18.Taking
into accoUnt the initial tolerance as well as the
change with temperature, the termination resis-..
tance is by no means precise. Fortunately, iii most
cases, the termination resistance can vary
appreciably without' greatly affecting the characteristics of the transmission line. If the resistor
tolerance is a problem, however, an external resistor
be used iI, plilce of the one provided within
the integrated circuit.
can
zoo
INPUT VOLTAGE (V)
FIGURE 16. Internal Power Dissipation as. Function of
Common Mode Input Voltage
190
~
§
..
~ 110
Figure 17 shows that the power supply current
also changes with common mode input voltage due
to the current drawn out of or fed into the supply
th rou gh R 9. The supply current reaches a
maximum, with negative input voltages and can
actually reverse with large positive input voltages.
The figure also shows that the supply current with
the output switched into the low state is about
3 mA higher than with a high output..
8-10
i
110
co
160
,I'...
--
1&0
-75 -50 -Z5
0
~
Z&
50
TEMPERATURE
7& 100 lZ&
rc)
FIGURE 18. Variation' of Termination Resistan•• With
Temperature
l>
Z
I
N
N
5'
;
...
(Q
III
;
Co
Q
...
DATA TRANSMISSION
(')
c
;:+
The interconnection of the OS7830 line driver
with the OS7820 line receiver is shown in Figure 19. With the exception of the transmission
line, the design is rather straightforward. Connec·
tions on the input of the driver and the output or
strobe of the receiver follow standard design rules
for OTL or TTL integrated logic circuits. The load
presented by the driver inputs is equal to 3 stan·
dard digital loads, while the receiver can drive a
worst-case fanout of 2. The load presented by the
receiver strobe is equal to one standard load.
en
10
0...
c
UNTERMINATEO
~
I\.
V...--
~
r-.
Joon
~~
w
'"
~
>
IS"
;:;:
150n
15n
!!!.
Q
::"
~
C
~
-5
...
~
III
III
-10
...
"""
III
:::I
TIME I",)
The purpose of C 1 on the receiver is to provide dc
isolation of the termination resistor for the trans·
mission line. This capacitor can both increase the
differential noise immunity, by reducing attenua·
tion on the line, and reduce power dissipation in
both the transmitter and receiver. In some applications, C 1 can be replaced with a short between
Pins 1 and 2, which connects the internal termination resistor of the OS7820 directly across the
line. C2 may be included, if necessary, to control
the response time of the receiver, making it
immune to noise spikes that may be coupled differentially into the transmission lines.
FIGURE 20. Transmission Line Response With Various
en
Termination Resistances
3
The effect of termination mismatches on the transmission line is shown in Figure 20. The line was
constructed of a twisted pair of No. 22 copper
conductors with a characteristic impedance of
approximately 1700.. The line length was about
150 ns and it was driven directly from a OS7830
line driver. The· data shows that termination resis·
tances which are a factor of two off the nominal
value do not cause significant reflections on the
line. The lower termination resistors do, however,
increase the attenuation.
g:
S"
:::I
C1 t
O.002j.1F
OUTPUT
tExact value depends on line length.
W+ is 4.5V to 5.5V for both the OS78Z0 and 087830.
*Optionalto control response time.
STROBE
FIGURE 19. Interconnection of the Line Driver and Line
Receiver
8·11
Figure 21 gives the line·transmission characteristics
with various termination resistances when a dc
isolation capacitor is used. The Iine is identical to
that used in the previous example. It can be seen
that the transient response is nearly the same as a
dc terminated line. The attenuation, on the other
hand, is considerably lower, being the same as an
unterminated line. An added advantage of using
the isolation capacitor is that the dc signal current
is blocked from the termination resistor which
reduces the average power drain of the driver and
the power dissipation in both the driver and
receiver.
The effect of different values of dc isolati'on
capacitors is illustrated in Figure 22. This shows
that the RC time constant of the termination resis·
tor/isolation capacitor combination should be 2 to
3 times the line delay. As before, this data was
taken for a 150 ns long line.
10
1501l +200 pF
..."
.."" ~
r-..
=
~
">
""
~
>
-10
~
FIGURE 22. Response of Terminated Line With Dif-
~~
ferent DC Isolation Capacitors
In Figure 23, the influence of a varying ground
voltage between the transmitter and the receiver is
shown. The difference in the characteristics arises
because the source resistance of the driver is not
constant under all conditions. The high output of
4
TIME 'jAI)
.
FIGURE 21. Lin. Response for Various Termination
Resistances With a DC Isolation .Capacitor
10
10
10
VCM=OV
.
~
..
~
"~
UNTERMINATED
1501l +2000 pF
...
~
..""
l ....
I'r:~
II'
UNTERMINATED
r\' 1501l +2000 pF
~
-5
-
TIME ,.,1
a. VCM= OV
~
1\iI~
~
~I'-
-5
Wi""'"
-10
TIME ""I
b. VCM = -15V
FIGURE 23. Line Response With Different Terminations
and Common Mode Input Voltage.
8-12
1501l+2000pF
1'1501l
>
II
~-
"<' T
~
1501l
-10
-10
.."
...."
..1. _l . l. J,VCM -15V
f-- ~::;: FUNTERMINATED
~
:N!
>
1501l
-5
V:CM = -15V
~
1.:.1rl\
1\
!Ii~
"
7m +2000 pF
-5
flt.p.-
,.... 150n +4000 pF
1501l +2000 pF
-10
~
IJII:~
~. -&
3001l +2000 pF
... "'"/1/
150n +1100 pF
~
10
~
"../
TIME ,.,1
c. VCM = 15V
»
z
I
N
N
S"
i
IQ
;
ic.
the transmitter looks like an open circuit to voltages reflected from the receiving end of the transmission line which try to drive it higher than its
normal dc state. This condition exists until the
voltage at the transmitting end becomes high
enough to forward bias the clamp diode on the 5V
supply. Much of the phenomena which does not
follow simple transmission-line theory is caused by
this. For example, with an unterminated line, the
overshoot comes from the reflected signal charging
the line capacitance to where the clamp diodes are
forward biased. The overshoot then decays at a
rate determined by the total line capacitance and
the input resistance of the receiver.
When the ground on the receiver is 15V more
negative than the ground at the transmitting end,
the decay with an unterminated line is faster, as
shown in Figure 23b. This occurs because there is
more current from the input resistor of the
receiver to discharge the line capacitance. With a
terminated line, however, the transmission characteristics are the same as for equal ground voltages because the terminating resistor keeps the line
from getting charged.
Figure 23c gives the transmission characteristics
when the receiver ground is 15V more positive
than the transmitter ground. When the line is not
terminated, the differential voltage swing is increased because the high output of the driver will
be pulled against the clamp diodes by the common
mode input current of the receiver. With a dc isolation capacitor, the differential swing will reach this
same value with a time constant determined ·by the
isolation capacitor and the input resistance of the
receiver. With a dc coupled -termination, the characteristics are unchanged because the differential
load current is large by comparison to the common mode current so that the output transistors
of the driver are alway~ conducting.
The low output of ,the driver can also be pu lied
below ground to where the lower clamp diode con-
.
Q
n
c
ducts, giVing effects which are similar to those
described for the high output. However, a current
of about 9 mA is required to do this, so it does not
happen under normal operating conditions.
;:+"
en
.
0c
To summarize, the best termination is an RC combination with a time constant approximately equal
to 3 times the transmission-line delay. Even
though its value is not precisely determined, the
internal termination resistor of the integrated circuit can be used because the line characteristics are
not greatly affected by the termi nation resistor.
cO"
:::;:
!!.
...C
I»
The only place that an RC termination can cause
problems is when the data transmission rate
approaches the line delay and the attenuation
down the line (terminated) is greater than 3 dB_
This would correspond to more than 1000 ft. of
twisted-pair cable with No. 22 copper conductors.
Under these conditions, the noise margin can disappear with low-duty-cycle signals. If this is the
case, it is best to operate the twisted-pair line without a termination to minimize transmission losses.
Reflections should not be a problem as they will
be absorbed by the line losses.
I»
-f
;
::;,
en
3
en
en
0"
::;,
CONCLUSION
A method of transmitting digital information in
high-noise environments has been described. The
technique is a much more attractive solution than
high-noise-immunity logic as it has lower power
consumption, provides more noise rejection, operates from standard 5V supplies, and is fully compatible with almost all integrated logic circuits. An
additional advantage is, that the circuits can be
fabricated with integrated circuit processes used
for standard logic circuits.
8-13
c
o
'iii
.!!!
E
~
APPENDIX A
e
I-
LINE RECEIVER
Design Analysis
The purpose of this appendix is to derive mathematical expressions describing the operation of the.
line receiver. It will be shown that the performance of the circuit is not greatly affected by the
absolute value of the components within the integrated circuit or by the supply voltage. Instead, it
depends mostly on how well the various parts
match.
.~
.!2l
Q
...
....o
en
,t::
:::s
~
CJ
The analysis will assUme that all the resistors are
well matched in ratio and that the tranSistilrs are
likewise matched, since this is easily accomplished
over a broad temperature range with monolithic
construction; However, the effects of component
mismatching will be discussed where important.
Further, large transistor current gains will be
assumed. but it will be pointed out later that this
is Valid for current gains greater than about 10.
"0
CD
~C)
..
CD
.5
A schematic diagram :of the 087S20 line receiver
is shown in Figure A-1. Referring to this circuit,
the collector current of the input transistor is
given by
N
N
I
~
, V+ - VBE1 - VBE3 - V BE4
IC1 = RS// R10+ R1l +,R311 RS
R3
R3//R11
R4+ 2R6+ R3 VBE1 - RS+ R311 R1 V 1N
RS//R10+Rll +R3I1RS
+
R'10llRll
(V1N-V ) RS+R10//R1l
(A.1)
+
RSII R 10 + R1l + R3 II RS
where V1N is the common mode input voltage and
Ra//R\> denotes the parallel connection of the two
resistors. In Equation (A. 1). RS = R9, R3" R10;
R10« R11, R9» R10, R3« R1l, RS»R3
R3
'
«3. so it can be reduced to
R4+2R6+ R3
,
+
V+ - 3V BE - Rl0
RS V
IC1=
R10+R11+R3
(A. 2)
which shows that the collector current of 01 is
not affected by the common mode voltage.
and
The output voltage on the collector of 02 is
VC2 = V+ - IC2R12
(A. 3)
For zero differential input voltage, the collector
currents of 01 and 02 will be equal so Equation
(A. 3) becomes
~
+ R12 (v+ - 3V BE VC2 =V Rl0+R11+R3
v+)
. (A. 4)
It is desired that this voltage be 3V BE so that the
output stage is just on the verge of switching with
zero input. Forcing this condition and, solving for
R12 yields
'
V+ -3V
R12=(Rl0+Rl1+R3)
RB1~
,
+'
+
V -3VBE -Fi9 V
(A. 5)
RESPONSE·TIME
CUNTROl
r-------e---e-----+-~~----
."10'
__--~~-------~
."
3ZO
...- ...._____ 0.11'.'
.,
17.
TERMINATION
., ...____.....__+___....."".
A'
Ik
AS
1k
'17
_-4~-----....;.
.z
"'
STROBE
FIGURE A-1. Schematic Diagram of On. Half
of tho DS7820 Lin. R.ceiver
S-14
••0 •• 0
~
I
N
N
This shows that the optimum value of R 12 is
dependent on supply voltage. For a 5V supply it
has a value of 4.7 k.ll.. Substituting this and the
other component values into. (A. 4).
V C2 = 2.83V BE + 0.081V+,
(A.6)
which shows that the voltage on the collector of
02 will vary by about 80 mV for a 1 V change in
supply voltage.
The next step in the analysis is to obtain an
expression for the voltage gain of the input stage.
01
"
012
4.1Sk
I
AV OUT
I
LW SE =
Stage Gain
Since a
(A. 8)
~
1, the voltage gain is
0.9 R2 R12
AVI = Rl (0.9 R2 + R E2 )
(A. 9)
The em itter resistance of 02 is given by
~
where
so
RE2=·~'
qlc2
v+ 'C2=
3V SE
R12
iil
[
Q
c:;
c:
;:j:
1/1
0...
qkT
ICI
log. Tc;
(A. 10)
iil
::s
1/1
3
iii·
1/1
o·
IOL =
(A. 12)
Therefore, at 25°C where V SE = 670 mV and
kT/q = 26 mV, the computed value for gain is
0.745. The gain is not greatly affecteq by tempera·
ture as the gain at _55°C where V sE =810mV
and kT/q = 18 mV is 0.774, and the gain at 125°C
where VSE =480mV and kT/q = 34mV is 0.730.
With a voltage gain of 0.75, the results of Equa·
tion (A. 6) show that the input referred threshold
voltage will change by 0.11 V for a 1V change in
supply voltage. With the standard ±10·percent
supplies used for logic circuits, this means that the
threshold voltage will change by less than ±60 m V.
::s
(A. 14)
where VOL is the low state output voltage and
ISINK is the current load from the logic that the
receiver is driving. Noting that R 13 = 2R 14 and
figuring that all the emitter·base voltages are the
same, this becomes
(A.ll)
V+ - VOL - 2V SE VSE
R17
+ RT5
VSE
-2R14 + ISINK ·
(A. 15)
Similarly, with the output in the high state, the
collector current of 08 is
IOH =
V+ -VOH-VSE9-VSE10
R17
V SE9
V SE8
+ R15 - R14
V SE7
+ R13 - ISOURCE ,
I»
I»
-t
describes the change in emitter·base voltage reo
quired to vary the collector current from one
value, IC1' to a second, Ic2 . With the output of
the receiver in the low state, the collector current
of 08 is
V SE9 V SE8
VSE7
+ R15-RT4+ R13+lsINK,
.
C
(A. 13)
V+ - VOL - V SE9 - V SE10
IOL =
R17
Hence, the change in output voltage will be
AV OUT = alE2R12
0.9aR2R12
= Rl (0.9 R2+ R E2 ) AV ,N .
CD
CD
It follows that the gain of the output stage can be
determined from the change in the emitter·base
voltage of 08 required to swing the output from a
logic one state to a logic zero state. The expression
FIGURE A·2. Equivalent Circuit Used to Calculate Input
An equivalent circuit of the input .stage is given in
FigureA·2. Noting that R6=R7=R8 and
R2 ~ 0.1 (R6 + R7//R8), the change in the emitter
current of 01 for a change in input voltage is
0.9 R2
AI E2 = Rl (0.9 R2+ R E2 ) AV ,N ·
(A.7)
..
:;
Finally, the threshold error due to finite gain in
the output stage can be considered. The collector
cu rrent of 07 from the bleeder resistor R 14, is
large by comparison to the base current of 08, if
08 has a reasonable current gain. Hence, the col·
lector current of 07 does not change appreciably
when the output switches from a logic one to a
logic zero. This is even more true for 06, an
emitter follower which drives 07. Therefore, it is
safe to presume that 06 does not load the output
of the first·stage amplifier, because of the com·
pounded current gain of the three transistors, and
that 08 is driven from a low resistance source.
(A. 16)
where V OH is the high·level output voltage and
ISOURCE is the current needed to supply the input
leakage of the digital circuits loading the
comparator.
8·15
r:
'iii
o
.!!?
E
II)
r:
e
~
as
~
o
,~
,21
o
With the same conditions used in arriving at
(A. 15), this becomes
o
.....
IOH =
.
V+ - VOH - 2V SE
VBE
R17
+ ill
II)
+"
VSE
- 2R14 - ISOURCE .
::s
~
U
(A. 17)
+"
From (A. 13) the change in the emitter-base voltage of 08 in going from the high output level to
the low output level is
en
Q)
kT
IOL
AV SE = q loge IOH
'C
.
Q)
as
+"
(A_ 18)
providing that 08 is not quite in saturation, although it may be on the verge of saturation.
.E
N
N
I
z
The change of input threshold voltage is then
«
kT
IOL
(A. 19)
AV TH = qA v-; loge ~
where AV1 is the input stage gain, With a worst
case fanout of 2, where VOH = 2.5V, VOL = 0.4V,
ISOURCE = 40/.lA and ISINK = 3.2 mA, the calculated change in threshold is 37 mV at 25°C,
24 mV at _55°C and 52 mV at 125°C.
The measured values of overall gain differ by
about a factor of two from the calculated gain.
This is not too surprising because a number of
ass4mptions were made which introduce small
errors, and all these errors lower the gain. It is also
not too important because the gain is high enough
where another factor of two reduction wou Id not
cause the circuit to stop working.
The main contributors to this discrepancy are the
non-ideal behavior of the emitter-base, voltage of
08 due to current crowding under the emitter and
the variation in the emitter base voltage of 07 and
08 with changes in collector-emitter voltage (h RE ).
8-T6
Although these parameters can vary considerably
with different manufacturing metnods, they are
relatively fixed for a given process. The AV BE
errors introduced by these quantities, if known,
can be added directly into Equation (A. 18) to
give a more accurate gain expression.
The most stringent matching requirement in the
receiver is the matching of the input stage divider
resistors: 'R 1 with R8 and R2 with R3. As little as
1% mismatch in one of these pairs can cause a
threshold shift of 150 mV at the extremes of the
± 15V common mode range. Because of this, it is
necessary to make the resistors absolutely identical
and locate them close together. In addition, since
R1 and R8 do dissipate a, reasonable amount of
power, they have to be located to minimize the
thermal gradient between them. To do this, R9
was located between Rl and R8 so that it would
heat both of these resistors equally. There are not
seri.ous heating problems with R2 and R3; however, because of their low resistance value, it was
necessary even to match the lengths of the
aluminum interconnects, as the resistance of the
aluminum is high enough to cause intolerable mismatches. Of secondary importance is the matching
of 01 and 02 and the matching of ratios between
R 11 and R12. A 1 mV difference in the emitterbase voltages of 01 and 02 causes a 30 mV input
offset voltage as does a 1% mismatch in the ratio
of Rll to R12_
The circuit is indeed, insensitive to transistor
current gains as long as they are above 10. The
collector currents of 04 and 06 are made equal so
that their base currents load the collectors of 01
and 02 equally. Hence, the input threshold voltage
is affected only by how well the current gains
match_ Low current gain in the output transistor,
08, can cause a reduction in gain. But even with a
current gain of 10, the error produced in the input
threshold voltage is less than 50 mV.
~
Applications
NAnONAL
APPLYING MODERN CLOCK
DRIVERS TO MOS MEMORIES
3:
o
c.
.
CD
INTRODUCTION
:::I
The OS0026 is a high speed, low cost, monolithic clock
driver intended for applications above one megacycle.
Table II illustrates its performance characteristics while
its unique circuit design is presented in Appendix II.
The OS0056 is a variation of the OS0026 circuit which
allows the system designer to modify the output performance of the circuit. The OS0056 can be connected
(using a second power supply) to increase the positive
output voltage level and reduce the effect of cross
coupling capacitance between the clock lines in the
system. Of course the above are just examples of the
many different types that are commercially available.
Other National Semiconductor MOS interface circuits
are listed in Appendix III.
MOS memories present unique system and circuit
challenges to the engineer since they require precise
timing of input wave forms. Since these inputs present
large capacitive loads to drive circuits, it is often that
timing problems are not discovered until an entire
system is constructed. This paper covers the practical
aspects of using modern clock drivers in MOS memory
systems. I~formation includes selection of packages and
heat sinks, power dissipation, rise and fall time consid·
erations, power supply decoupling, system clock line
ringing and crosstalk, input coupling techniques, and
example calculations. Applications covered include
driving various types shift registers and RAM's (Random
Access Memories) using logical control as well as other
techniques to assure correct non·overlap of timing waveforms.
The following section will hopefully allow the design
engineer to select and apply the best circuit to his particular application while avoiding common system pro·
blems.
Although the information given is generally applica·
ble to any type of monolithic integrated circuit, the
DS0025, OS0026 and OS0056 are selected as examples
because of their low cost.
PRACTICAL ASPECTS OF USING
MOS CLOCK DRIVERS
The OS0025 was the first monolithic clock driver.
It is intended for applications up to one megacycle
where low cost is of prime concern. Table I illustrates
its performance while Appendix I describes its circuit
operation. Its monolithic, rather than hybrid or module
construction, was made possible by a new high voltage·
gold doped process utilizing a collector sinker to minimize VCESAT.
Package and Heat Sink Selection
Package type should be selected on power handling
capability, standard size, ease of handling, availability
of sockets, ease or type of heat sinking required, relia·
bility and cost. Power handling capability for various
packages is illustrated in Table III. The following guide·
lines are recommended:
TABLE I. OS0025 Characteristics
PARAMETER
CONDITIONS (V+ - V'I
= 17V
tON
tOFF
C 'N
t,
CL
= 0.0022~F,
= 0.0001~F,
RIN ""
on
= 50(1
RO
t,
Positive Output Voltage Swing
VIN - V-
Negative Output Voltage Swing
liN == lOrnA,
On Supply Current (v+)
liN = 10mA
='
OV, lOUT
lOUT =
=
-lmA
lmA
VALUE
UNITS
15
ns
30
ns
25
ns
150
os
V+ • 0.7
V
V· + 1.0
V
17
rnA
TABLE II. OS0026 Characteristics
PARAMETER
CONDITIONS (v+ . V-I
= 17V
tON
t,
t,
= 0.001~F,
C'N
tOFF
RO
=
son,
CL
R'N
=
= on
1000 pF
I
Positive Output Voltage Swing
VIN - V- "" OV,
Negative Output Voltage Swing
liN'" lOrnA,
On Supply Current (v+)
'iN""
10 rnA
lOUT ==
lOUT
-1 rnA
= lmA
VALUE
UNITS
7.5
ns
7.5
ns
25
25
ns
n,
V+ - 0.7
V
V· + 0.5
V
28
rnA
8-17
(')
0"
n
;r;-
...
C
<'
CD
Cil
S
3:
o
C/)
3:
CD
3
o:::l,
CD
1/1
The TO·5 ("H") package is rated at 750 mW still air
(derate at 200°C/W above 25 C) soldered to PC board.
This popular cavity package is recommended for small
systems. Low cost (about 10 cents) clip·on heat sink
increases driving capability by !)O%.
where:
Q
v+ - V- = Total voltage across the driver
To TO·S ("G"). package is rated at 1.5W still ai( (derate
at 100°C/W above 25°C) and 2.3W with clip·on heat
sink (Wakefield type 215·1.9 or equivalent·derate at
15 mWfC). Selected for its power handling capability
and moderate cost, this hermetic package will drive very
large systems at the lowest cost per bit.
Additional information is given in the section of this
data book on Maximum Power Dissipation (page 2).
= Equivalent device resistance in the
Req
"ON" state
The S·pin ("N") molded mini·DIP is rated at 600 mW
still air (derate at 9O°C/W above 25°C) soldered to PC
board (derate at 1.39W). Constructed with a special cop·
per lead frame, this package is recommended for
medium size commercial systems particularly where
automatic insertion is used. (Please note for prototype
work, that this package, is only rated at 600 mW when
mounted in a socket and not one watt until it is soldered
down.)
(3)
DC
= Duty Cycle
"ON" Time
=-----------------"ON" Time + "OFF" Time
For the DS0025, Req is typically. 1 kn while Req is
typically 600n for the DS0026. Graphical solutions for
Poc appear in Figure 1. For example if V+ = +5V,
V- = -12V, Req = 500 n, and DC = 25%, then Poc' =
145 mW. However, if the duty cycle was only 5%,
Poc = 29 ,mW. Thus to maximize the number of regis·
ters that can be driven by a given clock driver as well as
minimizing average system power, the minimum allow·
able clock pulse width should be used for the particular
type of MaS register.
Power Dissipation Considerations
The amount of registers that can be driven by a given
clock driver is usually limited first by internal power
dissipation. There are four factors:
1.
2.
3.
4.
225
!z
Package and heat sink selection
Average dc power, Poc
Average ac power, PAC
Numbers of drivers per package, n
~
ili
c
~
I
'I
100
PMAX
15
0
I
V
/
/
20~17
~ I---
f/T
i; V V
_ _ IREQ'1500
~
0
10
V
/ v'iVP
'/y
50
25
.II
YJ J
17
J:.' L L
125
a;
From the package heat sink, and maximum ambient
temperature one can determine PMAX , which is the
maximum. internal power a device can handle and still'
operate reliably. The total aver-
~
V
~
"n'1
~
200
8l1li
1000 1400
CON
_
19l1li
L
2200
IpFI
I
•
"0
-
-I
TO RAM
FIGURE AI-8. DC Coupled 080025 Driving 1103 RAM
+'v
.~I~
O.I~
r--,
r--,-=-
2
.,
71/11
F
MOS SHIFT
'1l5I 'hT O& REGISTERS
12
13
I
V -
OSOO25.0 .J
,L -.1;-
OMl440
-~
+5V
D.1"f
.0
r--'
~
.J
j-
LlU
FIGURE AI·'. Output PW Controlled bV CIN
.rl
-=-r----'
~'~
6
~
~~9JZDJIVEJ- ~!..
300
+zov
+5.0'11
OUTPUT PULSE WIDTH vs. C1N FOR LONG
INPUT PULSES.
5l1li
1l1li
(AHO)
IMIN
FORINPUTPULSE"':65.j.ROCIt..
!
IMAX
+ ROC IN In
2
A plot of pulse width for various types of drivers is
shown in Figure AI-l. For applications in which the
output pulse width is logically controlled, CIN should
be chosen 2 to 3 times larger than the maximum pulse
width dictated by equation (AI-l0).
TTl[
INPUTS
.,
».....,r=-<>
L
MH0026CN
'"if"
::r:
.J
1'LI"
0-12V
FIGURE AI-9. DC Coupled Clock Driver Using 080034
-=-
cp,~
-(2V
-
FIGURE AI-1,0. Transistor Coupled 080025 Clock Driver
8-23
APPENDIX"
Rise Time Considerations
080026 Circuit Operation
Predicting the MOS logic rise time '(voltage fall) of the
DS0026 is' considerably involved, but a reasonable
approximation may be made by utilizing equation
(AI·5), which reduces to:
j
The schematic of the DS0026 is shown in Figure AII-T.
The device is typically ac coupled on the' input and
responds to inptlt current as does the DS0025. Inter·
nal current gain allows the device to be driven by standard TTL gates and flip·flops.
With the TTL input in the low state 01, 02, 05, 06 and
07 are "OFF" allowing 03 and 04 to come "ON." R6
assures that the output will pull up to within a VBE of
V+ volts. When the TTL input starts toward logic ".1,"
current is supplied via C 1N to the bases of 01 and 02
turning them "ON." Simultaneously, 03 and 04 are
snapped "OFF." As the input voltage ri"ses (to about
1.2V), 05 and 06 turn·on. Multiple emitter transistor
05 provides additional base drive to 01 and 02 assur·
ing their complete and rapid turn·on. Since Q3 and
04 were rapidly turned "OFF" minimal 'power supply
current spiking will occur when 07 c'omes "ON .."
(AII·l)
For CL = 1000 pF, V+ = 5.0V, V- = -12V, tr ~ 21 ns.
Figure AII·2 shows DS0026 rise times vs C L •
25
i.
20
!...
15
~
~
v+
1
1
...
~~
V'-v--zoy ~~ v+-V-.i7V
o
10
5
~;;'
R~= IsoJ
~
o
T.· 26"C
200
401
&00
100
1000 1200
LOAD CAPACITANCE {pFI
EXTERNAL
R6
R8
R9
co.
;NPU;
05
Rl
I"":
FIGURE AII·2. Rise Time vs Load Capacitance
1'(;,
~
"L... ~8 :.
~tf1
;;
06
I
Fall Time Considerations
09
The MOS logic fall time of the DS0026 is determined
primarily by the capacitance Miller capacitance of 05
and 01 and R5. The fall time may be predicted by:
~
1"'.5
";
02
R3
(AII·2)
>--oou TPU:r
~":t
08
03
..:
••
'"""'
...
..
R'
0'
~
R5
10k
rr
I . . .,
where:
I'lfi
, .~010
Cs = Capacitance to ground seen at the base of Q3
= 2pF
1"":••
R'
"1
hFE2 = (h FEQ3
V·
FIGURE AII·l. 050025 Schematic (One·Half Circuit)
06 now provides sufficient base drive to 07 to turn it
"ON." The load capacitance is then rapidly discharged
toward V-. Diode D4 affords a low impedance path to
06's cOllectqr which provides additional drive to the
load through current gain of 07. Diodes Dl and D2 pre·
vent avalanching Q3'S and 04's base-emitter junction as
the collectors of 01 and 02 go negative. The output of
the DS0026 continues negative stopping about 0.5V
more positive than V-,.
When the TTL input returns to logic "0," the input
voltage to the DS0026 goes negative by an amount
proportional to the, charge on CIN • Transistors 08 and
09 turn·on, pulling stored base charge out of 07 and 02
assuring their rapid turn·off. With 01, 02, 06 and Q7
"OFF," Darlington connected 03 and 04 turn-on and
rapidly charge the load ,towithin a VBE of V+
8·24
+ 1)
(h FEQ4
+ 1)
~500
For the values given and CL = 1000 pF, tf ~ 17.5 ns.
Figure AII·3 gives tf for various values of CL •
25
~
ii
v+ -v-~ 15Vto20V
20
z
.... ~
0
~
...~
........
~
15
:.,..- :.,..,;'
10
5
I
V-
son
Ro =
fA = 2S"C
/
o
200
400
600
&00
1000
LUAU CAPACITANCE (pFI
FIGURE AII·3. Fall Tima vs Load Capacitance
DS0026 Input Drive Requirements
u
The 050026 was designed to be driven by standard
54/74 elements. The device's input characteristics are
shown in Figure AII-4. There is breakpoint at V IN ~
0.6V which corresponds to turn-on of 01 and 02. The
input current then rises with a slope of about 600n
(R2 II R3) until a second breakpoint at approximately'
1_2V is encountered, corresponding to the turn-on of 05
and 06. The slope at this point is about 150n (R1 II
R2 II R3 II R4).
4.0
16
vc~' 5~OV
~
3.0
J
2.0
~~'+125OC
I\~
TA'-55~
1.0
'~ rt,r
0
0
.--.,-=_....-....-....-..-..-.,--,
T.-Z5°C
'~
10
20
lOUT
14
1
v+ • 20V -+-+--+--+--+--+--1
v-·ov
12 I-~F-r-j-j-j-+-+-+-l
40
30
(mAl
FIGURE AII-5. Logical "'" Output Voltage
vs Source Current
10 I-t-t-t-t-t-t-t-t-+-l
In actual practice it's a good idea to use values of about
twice those predicted by equation (AII-4) in order to
account for manufacturing tolerances in the gate, 050026
and temperature variations.
a H-t--t-+-1I-+-t--t--..,.I/-j
6
/
H-t-l-++-+-+CV':o"F--t--J
4 I-t-t-t-t-t-~t-t-~
2HH-t-t..,..q-+++-l
O~--~~~~~~~~~
o
0.5
1.0
1.5
2.0
A plot of optimum value for CIN vs desired output pulse
width is shown in Figure AII-6.
2.5
INPUT VOLTAGE IV)
FIGURE AII-4. Input Current vs Input Voltage
The current demanded by the input is in the 5-10 mA
region. A standard 54/74 gate can source currents in
excess of 20 mA into 1.2V. Obviously, the minimum
"1" output voltage of 2.5V under these conditions cannot be maintained. This means that a 54/74 element
must be dedicated to driving 1/2 of a 050026. As far as
the 050026 is concerned, the current is the determining
turn-on mechanism not the voltage output level of the
54/74 gate.
Input Capacitor Selection
A major difference between the 050025 and 050026 is
that the 050026 requires that the output pulse width
be logically controlled. In short, the input pulse width ~
output pulse width. 5election of CIN boils down to
choosing a capao;:itor small enough to assure the capacitor
takes on nearly full charge, but large enough so that the
input current does not drop below a minimum level to
keep the 050026 "ON." As before:
t1
IMAX
= ROC IN In - IMIN
(AII·3)
J
w-
2400 r7""~~~-r--,--,--,.-,
2200 y+ - V- • 20V -i-t--t--t--;;i
TA = 2 5 ° c L .
~ 2000
5 1800
~
1600
;:\1400
~
CL
""
1000 pF
1--t--+--j-t--¥/gMl4S0~-
1200
D~~~~~~_
~ 1000
IL
L.
gaoo
/
__
" 600 1--t-..".y-t-:::;..........
'9---..,1---I
:il 400
J.-,-RANS1STD~_
!i
I ~~
WITH50DHMS
!:E 200 t-- r - TO +5V DRIVING OS0026'"
0
~
0 100 200 300 400 500 600 100 aDo
'"
DUTPUT PULSE WIDTH In.)
FIGURE AII-5. Suggested Input Capacitanca
vs Output Pulse Width
DC Coupled Applications
The 050026 may be applied in direct coupled applications. Figure AII-7 shows the device driving address or
pre-charge lines on an MM 11 03 RAM.
or
t1
C IN = - - - ' - - - -
(AII-4)
iIfJ
ROln IMAX
1M IN
In this case RO equals the sum of the TTL gate output
impedance plus the input impedan'ce of the 050026
(about 150n). IMIN from Figure AII-5 is about 1 mA.
A standard 54/74 series gate has a high state output
impedance of. about 150n in the logic "1" state and an
output (short circuit) current of about 20 mA into 1.2V.
For an output pulse width of 500 ns,
20mA
(150n + 150n)ln - 1 mA
= 560pF
+y:
2
I.
2~
DS1J026CN
~}
TO ADDRESS
LINES ON
MEMORY
SYSTEM
5'
4
~
I.
[3
1120M1410
£
FIGURE AII·7. DC Coupled RAM Memory Address or
Precharge Drivar (Positi.. Supply Onlyt
8-25
For applications requiring a dc level shift, the circuit of
Figure AII-8 or AII-9 are recommended ..
+5.0V
OS1673
Quad decoded MOS clock driver.
OS1674
OS75.361
Ouad MOS clock driver.
OS75365
Quad TTl-to-MOS driver.
Dual TTl-to-MOS driver.
MOS Oscillator/Clock Drivers
OS7803/0S7807,
oS7813/oS7817
Complete two phase clock system
for MOS microprocessors and calculators.
MOS RAM Memory Address and Precharge Drivers
-12V'
OS0025
Dual address and precharge driver_
OS0026
Dual high speed address and precharge driver.
TTL to MOS Interface
FIGURE AII-8. Transistor Coupled MOS Clock Driver
~~UT5{o-_"""",
T05HIOT
) REGISTERS
OH0034
Dual high speed TTL to negative.
level converter.
OS7800
Dual TTL to negative level converter.
OS7810/0S7812/
OS7819
Open collector tTL to positive
high level MOS converter gates.
OS78l12
Active pull-up TTL. to positive high
hivel MOS converter gates.
OS1640/0S1670
Quad MOS TRI-SHARETM driver.
OS1645/0S1675
Hex TRI-STATE® MOS driver.
OS1646/0S1676
6-bit TRI-STATE MOS driverrefresh counter.
OS1647/0S1677
Quad TRI-STATE MOS driver I/O
register.
OSl648/0S1678
TRI-STATE
plexer.
OS1649/0S1679'
Hex TRI-STATE MOSdriver.
-12 V
FIGURE All-B. DC Coupled MOS Clock Driver
APPENDIX III
MOS driver
multi-
OS16149/OS16179 Hex TRI-STATE MOS driver.
MOS Interface Circuits
MOS to TTL Converters and Sense Amps
MOS Clock Drivers
MH0007
Direct coupled, single phase, TTL
compatible clock' driver. . .
MH0009
Two phase,' direct or ac coupled
clock driver.
PS7802, OS7806* Dual sense amp for MM5262 2k
MOS RAM memory.
Hex sense amp MOS to TTL.
OS165 Series *
OS163,OS75107, Dual sense amp for MM1103 lk
MOS RAM memory.
OS75207*
MH0012
10 MHz, single phase direct coupled
clock driver.
Voltage Regulators for MOS Systems
MH0013
Two phase, ac coupled clock driver.
OS0025
low' cost, two phase clock
oS0026
lM120 Series
Negative regulators.
OS1671
low cost, two phase, high speed
clock driver.
Dual bootstrapped MOS driver.
lM125 Series*
Dual +/- regulators.
OS1672
Dual TTL bootstrapped MOS driver.
·To be announced
d~iver.
lMl09, lM140
Series.
Positive regulators.
~
Applications
NAll0NAL
DATA BUS AND DIFFERENTIAL LINE DRIVERS AND RECEIVERS
INTRODUCTION
Monolithic circuits designed specifically to transmit and receive digital data via bu'ses and differential cables have been available for two or three
. years. But important changes in transmission concepts and Ie designs have been made recently.
This note will bring designers up to data on
circuits developed at National Semiconductor.
Table I and Figure 1 outline the devices to be
discussed.
In general, the new bus circuits offer these advances: self-isolation of powered·down receivers;
much lower input currents, permitting more driver/
receivers pairs per bus line; input hysteresis to raise
noise immunity; higher speed with better control
of bus levels; and e'liminating of terminating
pull-up resistors by the TR I-STATE® designs.
The OS7820/0S8820 and OS7830/0S8830 were
described in Application Note AN-22. This note
adds to the previous discussion of termination
techniques and reports on new tests of their long·
lines drive capability and crosstalk immunity.
TABLE I. Tabl. of Devices Discussed
LINE DRIVERS
DEVICE NO.
LINE RECEIVERS
DEVICE NO.
DESCRIPTION
POWER
SUPPLY
±12V
OS1489A +5.0V
COMMENTS
Twisted pair single ended.
Unidirectional.
OSl488
OS1489/0S1489A
Communication to EIA
standard RS 232C.
OS7830/0S8830
bS7820AlOS8820A
Dual differential line driver
and receiver.
+5.0V
True differential. ±15V common
mode rejection. Unidirectional.
Use of internal receiver termination recommended up to 100 feet.
057831/058831
OS782eA/OS8820A
Dual differential line driver
and receiver.
+5.0V
True differential, bidirectional.
Driver includes upper and lower
!evel clamps to combat transients.
Use of internal receiver termination
optional.
OS7.832/058832
OS78~OAlOS8820A
Dual differential line driver
and receiver.
+5.0V
As above. but without upper level
clamping, so party line busses may
be used, even with some peripherals
powered down.
'
OS7831/0S8831
OS7837/0S8837
(hex) or OS7836/
OS8836 (quad)
Quad single-ended line driver
and hex receiver, or a quad
2 input NOR receiver.
+5.0V
If used unidirectionally. receiver
should be terminated. In party line
applications disabled driver clamps
line. Receiver input current is 15ILA
typical. has 1.0V hysteresis.
TRANSCEIVER
DEVICE NO.
DESCRIPTION
POWER
SUPPLY
COMMENTS
057838/058838
Quad open collectOf transceiver.
+5.0V
Receiver has typicall5J.tA input
current 1.0V hysteresis. Driver will
pull down double terminated 120n
line.
OS7839/058839
Quad TRI·STATE@transceiver.
Four transmitters all disabled by
control NOR gate.
+5.0V
Drivers have 10.4 rnA for~ard drive
at 2.4V~ sink 32 mA at O.4V. Receivers
have 1.0V hysteresis, input current is
15JJ.A typical. Disabled driver clamps
undershoots. A transceiver on the bus
may be powered down without affect·
ing bus logic levels.
OS7833/058833
Quad TRI·STATE transceiver.
One control disables all transmitters; one control disables all
receiver outputs.
+5.0V
OS7834/[)58834
Quad TRI·STATE transceiver.
Controls same as DM7839 but
driver and receiver are inverting.
+5.0V
OS7835/0S8835
Quad TRI-STATE transceiver.
Controls same as DM7833 but
di-iver and receiver are inverting.
+5.0V
8-27
087830/0S8830
OS7820/0S8820, OS7820AlOS8820A
RESPONSE
Vee
-INPUT TERMINATION +INPUT
TIME
OUTPUT
14
12
13
14
STROBE
-INPUT TERMINATION +INPUT
STROBE
RESPONSE
OUTPUT
AND
OUTPUT
NAND
OUTPUT
NAND
OUTPUT
GNO
12
13
AND
OUTPUT
GND
TIME
NOTE: PfN 7 CONNECTED TO BOTTOM OF CAVITY PACKAGE.
TOPVIEW
TOP VIEW
OS7831/088831, OS7832/0S8832
"B" OUTPUT
DISABLE
087833/0S8833
DIFFERENTIAL/
"A" OUTPUT
DISABLE
OUTPUT
82
OUTPUT
INPUT
OUTPUT
INPUT
A2
A2
A1
A1.
INPUT
112
SINGLE·ENDED
MODE CONTROL
DRIVER
Vee
OUTPUT INPUT DlFfERENTIAlI GNU
81
81
SINGlHNDEO
MODE CONTROL
BUS o
IND
OUTo
INA
BUSe
IN,
INc
OUTe
OUT B RECEIVER
DISABLE
OS7834/088834
OS7835/DS8835
DRIVER
8USo
iNo
OUTo
BUSe
INc
DUTe
DISABLE
DUIA
BUSs
INs
OUTa
DRIVER
OISABLE
OND
DRIVER
Vee
BUS p
1No
DUTo
BUSe
INc
DUTe
DISABLE
OUTII
RECEIVER
GND
DISABLE
TOP VIEW
TOPVIEW
FIGURE 1.
is·28
GNO
TOP VIEW
TOP VIEW
Vtc
DISABLE
087837/0S8837
087836/0S8836
IN lOUT 1
IN 2
OUT 2
IN J
OUT 5
IN 6
OUT 6
OUT 3
DISABLE A
14
GNO
OUT2
OUTl
IN1A
IN1B
IN 2A
IN 4
IN 28
OUT 4
IN 5
OISABlE B GNO
TOP VIEW
TOP VIEW
087839/088839
087838/088838
I
DRIVER
BUSI
BUS 3
IN 3
INI
OUTI
BUSZ
lNZ
OUT J
BUS 4
IN 4
OUT 4
OUT 2
DISABLE A
8US o
IN,
OUT D
INc
OUT
DISABLE
OUTa
RECEIVER
GNO
BUS e
DISABLE B GNO
DISABLE
TOPVIEW
TOP VIEW
081489/081489A
081488
INPUT
o
14
GNO
lOP VIEW
INPUT
A
13
RESPONSE
CONTROL
A
RESPONSE
CONTROL
0
12
OUTPUT
A
RESPONSE
OUTPUT
0
11
INPUT
B
INPUT
C
CONTROL
C
OUTPUT
C
OUTPUT
II
GNO
10
RESPONSE
CQN1ROL
B
TOPVI£W
FIGURE 1. (Con't)
8·29
Not much need tie,. said about the EIA RS232C
designs. They meet or exceed a standard which is
below today's attainable performance levels.
UNIFIED BUS
A typical unified bus is a flat, multiconductor
cable interconnecting the CPU and peripherals of
minicomputer (Figure 2). The lines are single·
ended (non-differer)tial), ground-referenced, bidirectional, and terminated at each end in 120n
to 3.2V. The line level is high except when an
open-collector driver pulls the line low. Drivers
take turns transmitting, as controlled by "polling"
or other control sequences.
a
Single-ended communications are susceptible to
common mode voltage induced by ground currents
between chassis. In a computer room, the problem
is. usually minimized by linking the chassis with
heavy-gauge grounding cables. Communications
with remote points go through differential transmission links, or modems coupled to phone lines.
In early unified bus designs, open-collector TTL
buffers were used. as drivers, and standard gates
as receivers. However, the low threshold voltage of
the receiving gate (it can be as low as 1.0V) is too
close to ground potential, which can itself be
carrying, transients of almost a volt. In addition,
the gate's input 'current can be as high as, 1.6 mA,
severely limiting the number of receivers which
can be controlled by one driver. This IS true'
particu,larly if the driver has an open collector output, and must also be sinking the current from a
120n termination at each lind of the unified pus.
That problem was solved by the SP380 gate. Its
signal input is the base of an NPN emitter-follower,
giving a higher threshold and lower, input current.
Unfortunately, the input transistor's collector-base
junction becomes forward-biased when Vee goes
down. If a peripheral is shut off, the bus lines are
clamped near ground unless the bus cable is
disconnected manually.
The new unified bus designs in Table I have a
receiver that is self-isolating when power is down.
The main. bus is still usable if peripherals are
turned off.
Other improvements include: very low input
current, typically 15J.!A whether Vee is 5.0V or
zero; input hysteresis of 1.0V, providing 1.8V
noise immunity; thresholds of 1.3V and 2.3V; and
temperature compensation to keep thresholds and
noise immunity constant.'
The OS7836/058836 is pin·compatible with the
SP380 and adds the advantages of hystersis. The
058640 is an exact repl acement for the SP380.
Each receiver trio in the OS7837/0S8837 has an
enable control, so the system can force receiver
outputs to zero whether the bus is pulled down o,r
not. The four drivers in the OS7838/0S8838
transceiver are disabled by a NOR gate control.
Each open-collector driver in the transceiver sinks
50 mA at 0.7V. It has the power to pull down
the double·terminated bus and drive 20 of the'
low-current receivers.
TRI-STATE 'BUS
TRI-STATE logic (or TSL) outputs are active in
both the "1" and "0" state. This greatly improves
risetimes and allows many more driver/receiver
pairs to be connected to a bus since power is not
wasted in terminations. Switching delays can be
hah(ed during certain. data exchanges.
A disabled output switches into a third, high·
impedance state. Only small leakage currents flow
in the output in this state, virtually disconnecting
the output from the bus. TSL outputs do not
"wire·OR" - the bus is operated by one set of
outputs at a time.
Figure 3 is a TSL bus line. Although there are no
terminations, reflections are less of a problem than
in a unified bus. The bus is tightly controlled
without terminations because the disabled drivers
actually clamp undershoots.
+UV
'80
3111
FIGURE, 2. Unified Open Collector Bus
8-30
l>
Z
CPU
PERIPHERAL #1
PERIPHERAL #2
I
PERIPHERAL #N
CO
w
--~~----~~----~--~~
@
i ----I
IL
C
ell
or
________ JI
1140S7833
FIGURE 3. TRI·STATE Bus
+5,OV
+5.0V
'"
1403}>--t----~-"?""--::_--_+_
';::
Q
015
320
II)
...----<1..-----
c
:::;
OUTPUT
01
170
TERMINATION
R4
1.Ok
O'
014
160
1.Ok
03
161
t---------~----~~~----~--~~~----~-GND
01
OZ
161
INI~~~~I~~ _ - " ".'Yk'lr-____
.
. . .________~
STROBE
Note: Schematic shows one-half of unit,
FIGURE 18. DS7820 Schematic
FIGURE 19. DS7830 Driving Daisy·Chained DS7820',
The DS7830 and DS7831 output curves are
similar .. Either can. drive up to 12 DS7820
receivers strung along a cable, as in Figure 19, and
have ample overdrive at the last receiver.
TERMINATING THE DIFFERENTIAL LINE
There are three modes of operation of the differ·
ential line, each of which demands a different
answer to the commonly asked question of how
to terminate the line. AN-22 only went into one
case, namely, terminating a short line where data
period exceeds two line lengths. The second case
covers those lines where the period is less than
two line lengths, and the third the case where the
fine is long.
Why is two line deJay times significant? It's a
question of power dissipation only. When the line
8-36
is short, so that effectively no voltage is lost in
the copper of the cable, running without a termina·
tion, where the differential capability of the driver
exceeds 3.5V will produce reflections of 7.0V
magnitude in the !'ine.
This situation is best avoided, so a termination in
the characteristic impedance of the line is advisable.
When data rates are slow, this means that the
driver, if the termination is dc, will continue
to dissipate the power plotted on the load line of
Figure 17, quite unnecessarily. If instead a capaci·
tor is included in series with the dc. termination,
at the leading edge the termination appears dc,
so Radio Frequency Interference (RFJ) doesn't
get generated. But as the capacitor charges, the
voltage on the higher line rises, and the current in
the driver drops, until at one VSE below Vee,
line power ceases to be dissipated.
~
I
w
MAXIMUM LINE LENGTHS
So long as the rise is controlled, RFI won't be a
problem. And the rule of thumb of R1 C = 3
line lengths works very well. Where the driver is
running so fast as never to be waiting for the
reflection, it will be continuously dissipating the
power indicated by the load line continuously.
00
The tests in Table II were made with a OS7820
and OS7830 to settle questions about maximum
line lengths and frequencies. Characteristics of the
test cable were: 24 AWG gauge; 11O£G impedance;
5.6£G/100 ft loop resistance; and 14 pF/ft capaci·
tance.
As the line gets longer, the loop resistance gets
up to the same order as the terminating resistor.
That translates into an attenuation of the differ·
ential drive voltage at the receiver. Once the lead·
ing edge of the received voltage gets below 2.5V,
the reflection ceases to have RFI significance, and
a progressively worse mismatch is acceptable as
the line gets longer, since the higher the termina·
tion resistor value, the more signal is available.
For a typical cable, 1000 feet marks the point
where any termination serves only to weaken the
signal and narrow the channel bandwidth.
C
Q)
S'
Receiver inputs were complementary pulses with
25/75% duty cycles. These simulate a string of
alternating ones and zeros in an RZ (return to
zero) format. The first results column indicates
safe maximum data rates. The second column
shows the rates at which attenuation reached a
point where the signal could not switch the line
receiver. These are typical, not maximum or safe
rates.
Figure 21 illustrates the weaker signals which
will switch the receiver. There is obviously no
noise margin. For maximum performance, a single
twisted·pair line should meet all three of these
criteria:
The bandwidth of the OS7820 receiver may be
reduced by use of a shunt capacitor. The response
curve is shown in Figure 20.
1000
Vee'" 5V
TA " 25"C
VOtFF = ±2.5VPUlSE
""
~
1. High characteristic impedance (to maXimIZe
initial voltage step and voltage across the term in·
at ion at the receiver)
;;
~
100
2. Low capacitance (minimizes the "line charging"
effect, which attenuates the signal's high·
frequency components and makes dc loss worse
by degrading the response to fast transients)
~
:i
~
10
100
10
1000
CRESPONSE TIME CONTROL
10,000
(pf)
3. Low resistance to dc (use heavier·gauge cable
for long runs driven at high frequency)
FIGURE 20. Noise Rejection in the DS7820A
TABLE II. DS7830/DS7820A 24 Gauge 110n
Line Length
25'
200'
1000'
5000'
Point of Duty
Cycle Distortion
1G MHz
5.0MHz
1.25 MHz
0.125MHz
Point of Failure
To Invert
25
12
3.2
0.275
MHz
MHz
MHz
MHz
---u-Lr
+
INPUT
~-INPUT
25:15
:::=x______x ___
FIGURE 21. Differential Drive Long Distance
8·37
l!.!
CD
'Q>)
CROSSTALK IMMUNITY
CJ
CD
I'a
One more question concerns crosstalk in multipair cables. The tests reported in Table III indicate
that the individual pairs rarely, if ever, need
individual shielding_ One shield over all the pairs
in the sheath should be adequate.
...
TABLE III.
a:
"C
c
I/)
~
'~
NOISE THRESHOLD AT POINT A
(VOLTS)
LOWER
UPPER
c
CD
c
1.22
1.22
1.24
1.24
:::i
CO
c
'+l
...CD
1.26
1.27
1.30
1.30
FREOUENCY
500 kHz
100 kHz
10 kHz
1.0 kHz
Two side-by-side runs of twisted pairs in the
cable were selected to provide two 800-foot
lengths adjacent to each other in the blJndle for
their whole length. A 057830 driver and a
057820 receiver were connected to each pair. One
driver's input was a pulse train and the other
driver's input was a dc voltage. Tests were made
to determine the susceptibility of the receiver on
the dc' line to signals cross-coupled into it from
the pulsed line .
£
is
"C
C
I'a
I/)
=
m
...
I'a
I'a
C
This driver/cable/receiver combination is susceptible in a transition region about 60 mV wide
between the "1" and "0" states, indicated by the
tabulated thresholds for the dc line. 5ignals from
the ac side coupled-in sufficiently to, trip the
de pair's receiver.
M
00
I
Z
«
However, ina real, system both driver outputs
will swing through this region rapidly_ The minimum swing is 2.0V. Therefore, the sensitive region
is 60 mV/2,000 mY, or 3% of the swing and of
the logic switching time. The minimum risetime
of a non-damped 057820 receiver output is 50 ns.
Assuming this is the result of a straight voltage/
time ramp input, the receiver is susceptible to
crossta,lk only if it is being driven with transition
times greater than 50 ns/3%, or 1.6 ms.
In fact, the longest driver risetimes observed
when the 057830 was driving the longest cable
in the previous test (Table II) were always less
than 10 ns. We can conclude that a twisted pair
with the driver and, receiver is immune to crosstalk from another 057830-057820 combination
operating with any adjacent twisted pair.
EIA STANDARD CIRCUITS
The drivers and receivers listed as EIA R5232C
circuits in Table I meet the specifications of that
standard_ It might be noted, however, that the
standard's provisions antedate the availability of
integrated circuits for such communications. Thus,
it tends to restrict further development.
Compare the results in Table II, for example,
with paragraph 1.3 of the standard. The standard
indicates 20 kilobits/second is a nominal data
transfer rate. And paragraph 1.4 requires singleended, ground-referenced links even though true
differential communications are demonstratedly
more efficient in data exchanges between chassis.
+S.OV
FIGURE 22. Crosstalk Between Close Twisted Pairs
8-38
»
2
~
I
Applications
00
~
C
::::!,
NA110NAL
S,
::::I
CCI
-r
DRIVING 7-8EGMENT GAS DISCHARGE DISPLAY
TUBES WITH NATIONAL SEMICONDUCTOR CIRCUITS
(I)
CD
CCI
INTRODUCTION
Circuitry for driving high voltage cold cathode
gas discharge 7-segment displays, such as Sperry
Information Displays' and Burroughs Panaplex II,
is greatly simplified by a complete new line
of monolithic integrated circuits from National
Semiconductor, The new products also make
possible reduced cost of system implementation.
They are: DS8880 high voltage cathode decoder/
driver; DS8884A high voltage cathode decoder/
driver; DS8885 MaS to high voltage cathode
buffer; DS8889 low power cathode driver; and
DS8887 8-digit anode driver_
In addition to satisfying all the displays' parameter
requirements, including high output breakdown
voltage, the new circuits have capability of programming segment current, and providing constant
current sinking for the display segments. This
feature alleviates the problem of achieving uniformity of brightness with unregulated display
anode voltage. The National circuits can drive the
displays directly.
Sperry Information Displays' and 8urroughs Panaplex II are used principally in calculators and
digital instruments. These 7 -segment, multi-digit
displays form characters by passing controlled
currents through the appropriate anode/segment
combinations. The cathode in any digit will glow
when a voltage greater thaI) the ionization voltage
is applied between it (the cathode) and the anode
for that digit. In the multiplexed mode of operation, a digit position is selected by driving the
anode for that digit with a positive voltage pulse.
At the same time, the selected cathode segments
are driven with a nl'gative current pulse. This
causes the potential between the anode and the
selected cathodes to exceed the ionization level,
causing a visible glow discharge.
Generally, these displays exhibit the following
characteristics: low "on" current per segmentfrom 200J.lA (in DC mode) to 1.2 mA (in multiplex
mode); high tube anode supply voltage-180V to
200V; and moderate ionization voltage-170V.
Once the element fires, operating voltage drops
to approximately 150V and light outPlit becomes
a direct function of current, which is controlled
by current limiting or current regulating cathode
circuits. Current regulation therefore is most
desirable since brightness will then be constant
for large anode voltage changes. Tube anode to
cathode "off" voltage is approximately 100V;
and maximum "off" cathode leakage is 3J.1A· to
5J.1A.
3
Correspondingly, specifications for the cathode
driver must be complimentary, approximately as
follows: A high "off" output breakdown voltage
80V minimum; typical "on" output voltage of
5OV; maximum "on" output current of 1.5 mA
per segment; and maximum "off" leakage current
of 3J.1A to 5J.1A_
CD
::::I
...
Ci)
III
UI
C
~'
To allow operation without anode voltage regulation, the cathode driver must be able to sink a
constant current in each output, with the output
::::I'
III
caCD
C
(a) Cathode Driver Output Characteristic
iii'
'ts
f
-4
c
iUI
1\111
O.5mA
TYPICAL OPERATING POINTS
:e
;:to'
30
::::I'
.0
90
120
2
OUTPUT VOLTAGE IV)
(I)
(')
~'
(b) On Currents vs Temperatura
o
1.04
r--,----..,.-..--,----..,.-..-""
S'.031---1c-f-+_+-I~I--.I'f-/--l
.L~..¥
1.02 I----l--l--l-~.~~. T
;+
i..
~
_
1.01
v
X.
CURRENT RATIOS
~ 1.00
1-+-+."c.F':;::::';;'::":"':::;':':;=l
~
0.99
-V-- vC;JT =50V
;
0.98
"
UI
1./ vi. Jv
-T'r----;-
I
I
Rp=OTEMP.COEF.
~ 8.97 L...J....-L_O,;".2,;"mA_<='o::.:uT~~'-'.:.::.2.:.:m~A
o
10
20
38
TA
40
50
60
10
rei
FIGURE ,_
"on" voltage ranging from 5V to 50V (see Figure
1). The following is a brief description of the
circuits now offered by National:
058880 High Voltage Cathode
DecOder/Driver
The DS8880 offers 7-segment outputs with high
output breakdown voltage of 80V minimum;
constant current-sink outputs; and programmable
output current from 0.2 mA to 1_5 mAo
*Now called Beckman Displays
8-39
power su pply voltage is 5V. The device" can be
used for multiplexed or DC operation.
Application
a
The circuit has
built-in BCD decoder and can
interface directly to Sperry and Panaplex II
displays, minimizing external components (Figure
2). The inputs can be driven by TTL or MaS
outputs directly. It is optimized for use in systems
with 5V supplies.
Available in 16-pin cavity DIP packages, the
DS7880 is guaranteed over the full military
operating temperature range of -55°C to +12SoC;
the DS8880 in molded DIP over the industrial
range of O°C to +70°C.
DS8884A High Voltage Cathode Decoder/Driver
Vu
The DS8884A offers 9-segment outputs with high
output breakdown voltage of 80V minimum;
constant current-sink outputs, programmable from
0.2 mA to 1.2 mAo It also offers input negative
and positive voltage clamp diodes for DC restoring,
and low input load current of -0.25 mA maximum.
(+17l1-200VOC:)
''''T
DISPLAY
Application
DS8884,/\ decodes four lines of BCD input and
drives 7-segment digits of gas-filled displays. There
are two separate" inputs and two additional outputs
for direct control of decimal point and comma
cathodes. The inputs can be DC coupled to TTL
(Figure 3) or MaS "outputs (Figure 4). or ACcoupled to TTL or MaS outputs (Figure 5) using
only a capacitor. This means the device is useful
in applications where level shifting is required. It
can be used in multiplexed operation, and is
available in an 18-pin molded DIP package.
MEMORY
...c
FIGURE 2. DC Operation From TTL
The DS8880 decoder/driver "provides for unconditional as well as I~ading and trailing zero blanking.
It utilizes negative input voltage clamp diodes.
Typically, output" current varies only 1% for
output voltage changes of 3V to 50V. Operating
G)
E
Cl
G)
(I)
I
Other advantages of the DS8884;A are: typical
output current variation of 1% for output voltage
changes of 3V to 50V; and operating power supply
"
Cl
C
'S;
'C
C
~
co
I
z
«
..~~ {
,
FIGURE 3. Intorfacing Directly With TTL Output
•g
e:
SPERRY
DISPLAY
5
8ANODECDNTFlOlliNES
TV •. COUPLING
CAPACITOR
FIGURE 4. BCD Data Interfacing Directly With MOS Output
8-40
»
z
I
When the OS8885 is used to drive minus and
plus (polarity) cathodes, overrange, and decimal
points, output c should be tied to Vee so it does
not saturate (Figure 7). This leaves 6 inputs and
6 outputs related one·to·one. The inputs can be
driven directly from TTL or MOS outputs.
-IIIV
CD
olio
C
:::!,
<
:i'
CQ
......
I
CJ)
CD
CQ
3
CD
...
IAIiIOOELINES
::s
lMTVP(IPlI
Ci)
I»
FIGURE 5. Cathode BCD Data AC Coupled
From MOS Output
en
-IZV
(fORMOS!
C
~'
*Outputmavbeparalleledforcathodesrequiringmore current,providingtbe
correspondinginpuhare also paralleled.
voltage of 5V. Inputs have pull·up resistors to
increase noise immunity in AC coupled applications.
I»
OS8885 MOS to High Voltage Cathode Buffer
C
(ii'
'0
OS8889 Low Power Cathode Driver
The OS8885 features seven constant current·sink
outputs; programmable output current of 0.2 mA
to 1.5 mA; high output breakdown voltage of 80V
minimum; and capability for blanking through
program current input. It operates from a +5V
supply.
.f
The 0S8889 requires no power supply since
power is derived from program current. It offers
extremely low standby power-only 1 mW internally. Features include programmable output currents 0.3 mA to 1.7 mA; 8 constant current-sink
outputs; and input negative voltage clamp diodes
for DC restoring. Outputs have 80V minimum
breakdown, voltage.
Application
OS8885 is best suited for interfacing 7·segment
fully decoded MOS chips to digit displays. It is
also useful for driving polarity, overrange, and
decimal point segments.
The device is suitable for multiplexed operation
from fully decoded chips and is capable of driving
decimal point segments simultaneously with numeric segments.
OS8885 has 6 inputs and 7 outputs. Output c is
decoded internally; the other 6 outputs are directly
controlled by the 6 corresponding inputs. A typical
application of this device is interfacing between an
MOS calculator chip with 7·segment decoded
outputs (open·drain or push·pull) and Sperry(
Panaplex II displays (Figure 6).
Application
~
caCD
The OS8885 is available in l6·pin molded DIP
package, and is guaranteed over the operating
temperature range of DoC to +70°C.
The OS8884A is guaranteed over the DoC to
+70°C operating temperature range.
~
::r
FIGURE 7. Polarity. Ovarranga. Decimal Point Driving
-I
c
c::r
m
~
::+
::r
Z
t/)
(")
~'
a
;:+'
en
The 0S8889 has 8 inputs and 8 outputs, and
interfaces directly between 7-segment decoded
MOS outputs and numeric display tubes (Figures
8 and 9). It is optimized for use in systems with a
limited number of power supplies.
SPERRY
OISPlAY
IANOOE
CONTROlUNES
Ii!:
!
TY'.COUPlING
CAPACITOR
FIGURE 6. Fully Oe.oded MOS Cathode Outputs
8-41
The program input is characterized in terms of
input current,therefore any supply (greater than
5V) can provide proper operation by connecting a
single resistor to the program pin from th€ supply.
The OS8889, guaranteed for the O°C to +70°C
operating temperature range, is offered in the 18pin molded OIP.
DS8887 8-Digit Anode Driver
The OS8887 interfaces directly to MOS chips
and operates from a -40V to -80V power supply .
The OS8887 can operate virtually any multiplex
display system requiring more output performance
from the MOS chip than is available (Figures 4, 6,
8 and 9). It has low input current and voltage
swing requirements but can drive up to 16 mA,
and exhibits -55V minimum output breakdown
voltage.
The OS8887 is available in the 18-pin molded
OIP package; and is guaranteed over the operating
temperature range of O°C to +70°C.
.""
.
COUNTER
DSlI887
CALCULATOR
ANODE
DRIVER
CHIP
cQ)
E
en
Q)
C/)
,...I
FiGURE 8. Decoded Cathode Data AC Coupled From MOS Output
en
c
'>
'C
Q
'I;f'
00
I
Z
«
0$11887
ANODE
DRIVER
8 ANODE CONTROL LINES
TVP,CDUPLING
CAPACITOR
TO OTHER
DISPLAYS
FIGURE 9. Decoded Cathode Data Direct Coupled From MOS Output
8-42
»
z
~
I
Applications
CD
CD
C
~
.;:-
NATIONAL
S'
IC
.....
I
oCD
DRIVING 7-SEGMENT LED DISPLAYS WITH
NATIONAL SEMICONDUCTOR CIRCUITS
IC
3
CD
INTRODUCTION
There are many different information display
technologies available today, including liquid
crystals, gas-discharge tubes, fluorescent tubes,
incandescent lamps, and light emitting diodes
(LEOs). Each technology has its own particular
drive requirement. This note will focus on 7segment LEO display drive requirements and
demonstrate that National Semiconductor has
a full line of display drivers that meet the
requirements for most any 7-segment LEO drive
appl ication.
...:=
2. Non-decoding, direct drive (MOS to LEO)
r-
m
OS8864
OS8865
OS8866
OS75491
OS75492
OS8861
OS8863
C
C
iii'
'C
iii"
~
Thus, National has circuits that will drive 7-segment
LEOs from either fully decoded circuits or from
non-decoded outputs.
~
;=4:
;:r
CON-FIGURATIONS AND CONSTRUCTION OF
7-SEGMENT LEOs
Z
o
WHY ARE LED DRIVERS NEEDED?
The purpose of 7-segment LEO driver.s is to act
as an interface element between data input and
the display. This interface is necessary when either
the input data format or circuitry current capabilities do not allow direct connection between input
and display. To satisfy these needs, National's
7-segment LEO drivers are divided into two basic
categories.
1. Internally decoded (BCO to 7-segment)
OS5446A/OS7446A
OS5447A/OS7447A
OS5448/0S7448
OS7856/0S8856
OS8857
OS7858/0S8858
Q
n
LEOs are segregated into two groupings with
regard to construction, see Figure 1.
c
;:.:
CII
Common anode displays are constructed on a
common substrate which forms the anode of the
diodes, while each of the seven cathodes are
bonded out to separate pins. The second type,
common cathode, has the cathode fabricated on
a common substrate with the anodes bonded out
to individual pins. Due to these radically different
configurations, drive circuits are usually tailored
in their design for one or the other type. Tailoring
in this respect means either sinking current (active
low) or sourcing current (active high) when referenced to segment drive. In addition, drive
requirements are quite variable because of LED
light intensity requirements as well as digit size
COMMON CATHODE
COMMON ANODE
SEPARATE
ANODES
(SEGMENT
ENABLE)
SOURCE
rttfr~
""ob+J
CURRENT
COMMON CATHODE
(DIGIT ENABLE)
COMMON ANOOE
·"Ttft
,
I
SEPARATE
I
\...
SINK SEGMENT
CURRENT
CATHODES
(SEGMENT
ENABL'E)
FIGURE 1. 7-Segment LED Construction
8-43
!II
.~
:J
~
COMMON SEGMENT
LINES
(.)
'y y .•.
en
z
....
.l:
'i
!II
>
ca
Q.
-
-,
I I
~
I I
_ _ 1- _ _ ..1I IL
r~
I
I
IL
1--
"...
r~
-- -,
-
,. ...
__
r~
-
1--
.....
~,
I I t' ~
I
~
I
I I
I I
I
_ _ _ .JL _ _ 1- _ _ ..1
.!!!
Q
,
DIGIT
Q
DIGIT
DIGIT
2
3
w
....I
....s::
FIGURE 2. Multi·Digit 7-Segment LED
Q)
E
2'
en
,....I
SEGMENT ENABLE
LINES
en
.::;c
BCD TO 7·SEGMENT
DECODER DRIVER
·c
STROBED
Q
BCD
DATA
0')
0')
I
z
LOGIC
c:t:
(INCLUDING
MULTIPLEXING
CIRCUITRY)
CLOCK
>----+
COUNTER
DIGIT ENABLE
LINES
FIGURE 3. A Typical Multiplexing Scheme
and efficiency. Thus the system designer needs a
degree of latitude not only with respect to the
type of display used but also the drive current
available.
7·segment LEDs can be purchased in either single
or multi·digit display packages. Single digit displays
have individual segment and common pins while
multi·digits have paralleled segment pins and
separate digit pins equal to the number of digits
in the package, see Figure 2.
Multi-digit displays, due to their configuration,
must be driven in a multiplex mode of drive, where
segment drivers are time shared by all the digits.
This is contrasted to the single digit displays which
8-44
may be driven in either the multiplex or the non·
multiplex (direct drive) mode. The nonmultiplex
mode uses separate segment drivers for each digit
of the display. Multiplex operation has a decided
cost saving advantage over nonmultiplex operation
especially when the number of digits being driven
is large.
MODES OF 7-SEGMENT LED DRIVE
In the multiplex mode of drive the LED digits
in a mUlti-digit format are driven by a single set
of segment drivers while each digit is selected by
its own digit driver. Figure 3 shows the circuitry
needed to implement a typical six digit multiplexed
display.
l>
2
Each digit is selected individually by enabling its
digit driver whose control is determ ined by a
counter or equivalent circuitry operating at some
clock frequency. Strobed data, by way of the
counter and multiplex circuitry, is then displayed
on the selected digit by the single set of segment
drivers. If the strobe rate is high enough, from
about 250 to 1,000 Hz depending on external
conditions, the display will appear flicker free to
the human eye. The BCD-to·7-segment decoder
converts BCD data to the desired 7-segment output
format.
In summary, LED driver requirements for multiplex or nonmultiplex drive operation require
either segment, digit or BCD to 7-segment drivers.
Analysis of the particular system needs with
regard to the number of digits and relative circuit
costs should be the determining factor for multiplex or nonmultiplex operation. Circuit require·
ments for multiplex operation will in general
require relatively high current capabilities.
In the multiplex mode each digit has a reduced
duty cycle and is operated at somewhat higher
than average or typical dc operating current levels.
The amount of current will be a function of the
number of digits, duty cycle, and the type
and efficiency of the display used. Since currents
are higher than average so also will be the LED
brightness due to the nearly linear brightness
versus current curve for most LEDs. The human
eye will detect the brightness peaks and through a
partially integrating and peak detecting action will
perceive a higher display brightness at some average
current level in the multiplex mode than the same
average current in the nonmultiplex (direct drive)
mode. The result is that a multiplexed display will
operate at a lower total power than the same
display operated in the nonmultiplex mode with
the same apparent brightness.
Table I lists the 7·segment LED drivers available
from National. Each circuits application is divided
into groupings with respect to common anode or
cathode, digit or segment, multiplex or nonmulti·
plex areas. Additionally, current capabilities are
al so specified for each product.
In the nonmultiplex mode of 7-segment LED drive
each digit has its own set of segment drivers
thereby dropping the digit driver select requirement of multiplexed operation. In this case, the
common digit pin may be tied to the highest
potential if common anode or the lowest if
common cathode. It is evident that in a nonmultiplexed display the driver package count
would be high since each digit requires its own
set of segment and possibly decoder drivers.
If a large number of digits are used the segment
driver package count wou Id equal the number of
digits while in the multiplex mode this count
is equal to one. Granted, in the multiplex mode
additional control circuitry is required. Consideration of the relative cost of this circuitry in
comparison to the segment decoder driver circuitry
in the nonmultiplex mode results, in general, in
the fact that if the number of digits in the display
equals or is more than four, total package count
and/or cost is less in the multiplex mode of drive.
I
CD
CD
C
::I.
S.
::I
CC
.....
I
fA
c!
NATIONAL'S 7·SEGMENT LED DRIVERS
3
GI
::I
....
r0-
m
C
C
(II
'0
iii
~
From the table it is evident that some of the
circuits may be used in dual roles - both multiplex
or nonmultiplex; common cathode or anode. In
general, what will determine whether one drivers
application is multiplex or nonmultiplex is that
drivers current capability. The direction of current
flow through the driver (source or sink) is the
determining factor in dual application with regard
to common anode or cathode.
:E::4:
::r
2
fA
o
~r
c
Table 1/ lists the operating temperature range and
package types for the 7·segment LED drivers.
S·
In the following sections each circuit is described
in greater detail and typical applications are
given.
BCD TO 7·SEGMENT DECODER DRIVERS
DM5446A/DM7446A,DM5447A!DM7447A,
DM5448!DM7448
This family of BCD to 7·segment decoder drivers
was designed for the most general possible dis·
play drive applications including display techno·
logies other than LEDs. The difference between
the circuits is in their output stage configurations.
These differences will be discussed separately later.
<
In most MOS circuits multiplex operation is ideal
since the counter, mUltiplexer, and BCD to 7segment decod~rs or equivalent circuitry can
usually be incorporated on the same chip along
with calculator, clock or other function. In this
case the only external interface components
required would be the digit and segment drivers
since MOS circuits are generally unable to sink
or source the higher current required for most
multiplex operations.
The circuits convert the standard 4·bit BCD input
to the popular 7·segment output format. All
input BCD codes above 9 are decoded into unique
patterns that verify operation. The circuits are
TTL·DTL compatible and operate off of a single
5.0V supply.
Added features included in all circuits are a ripple
blanking input pin as well as a lamp test pin for
display turn on. In addition the blanking input!
ripple blanking output pin may be used to modu·
late display intensity.
B-45
,~
;:,
U
a-
U
TABLE I. National7·Segment LED Drivers
U)
Z
Refer to LED Dr.iver Guide in Front of Catalog
.t:
+"
'i
DEVICE
NUMBER
III
DM5446A/DM7446A
DM5447A/OM7447A
>
«I
Q.
,!!
C
C
....
COMMON CATHODE
Multiplex
COMMON ANODE
Nonmultiplex
SEGMENT
DRIVER
INTERNAL
DECODING
X
X
X
Up to 40 rnA Sink, Open Collector
High Breakdown (30/15V)
TTL Input Compatibility
Multiplex
NonmultipJex
X
DIGIT
DRIVER
OM5448/0M7448
X
x·
X·
X
X
1.3 rnA Source, Adjustable
Externally, TTL Input
Compatibility
OS785.6/0S8856
X
X·
X·
X
X
6,0 rnA Typical Source, TTL
Inp,ut Compatib'j'tity
X.
X
W
OS8857
X
X
50 rnA TYPIcal Source, Externally Adjustable, TTL Input
+"
C
Compatibi I i~y
G)
OS7858/0S8858
X
X
OS75491
X
X
E
C)
X
Adjustable Source Current 0 to
50 rnA, TTL Input
Compatibility
X
G)
U)
X
X
X
50 rnA Source/Sink, 4 Drivers
X
,...I
per Package, MOS Input Compatibility
X
X
X
X"
250 rnA Sink, 6 Drivers per
Package, M9S Input Compatibility
X
X
X
X
50 rnA Source/Sink, 5 Drivers per
Packag,e. MOS Input Compatibility
X
X
X
X
X"
500 mA Sink, 8 Drivers per Package,
MaS Input Compatibility
OS8864
X
X
X
X
X"
50'mA Smk, 9 Drivers per Package,
MaS Input Compatibility
OSS865
X
X
X·
X
X"
50 mA Sink, 8 Driv.ers per Package,
MaS Input Compatibility
OS8866
X
X
X
X
X"
50 mA Sink, 7 Drivers per Package,
MaS Input Compatibility
OS75492
X
OSS861
X
C
OS8863
en
en
Z
C)
C
:i!a-
CURRENT CAPABI LlTY
AND FEATURES
I
X
c(
·With the use of an external transistor/segment.
·*For common anode LED's.
TA~.LE
DEViCE
NUMBER
OPERATING
TEMPERATURE RANGE
OoC to +10~C·
16·
X
X
Plastic Molded
DIP(N)
X
X
OSS857
X
X
X
(W)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
OS8858
X
OS75491
X
X
OS75492
X
X
OSS861
X
X
X
OS8863
X
X
X
OSS865
X
X
X
OS8866
X
X
X
OS8864
X
.X
22
Flat Pac!.
X
X
X
Ceramic
DIP (J)
X
X
X
OS8856
OS7858
18
X
X
DS7856
8-46
14
X
DM5448
DM74¢8
-SSoC to +12SoC
PACKAGE TYPE
NUMBER OF PINS
X
OM5446A,OM5447A
OM7446A,OM7447A
II. Operating Temperature Range and Package Type
X
X
z~
I
CD
CD
SEGMENT
OUTPUT
C
~'
S'
ea
-..I
I
OMM46A/DM744IA
DMSM1AlDM'I441A
en
DM544B/DM7448
DS716B/DS8868
FIGURE 48. Output Stage
"3
":s
ea
.
FIGURE 4b. Output Stage
rm
C
C
iii'
DECIMAL
POINT
"2-
II/RBD
I»
~
~
g:
Z
BCD
en
INPUTS
The following equation I1IIY be used to dfleJmin. the appropriate valu. of Rx
(sagment current limit resistor) for some LED curnnt/segmam Is (rnA).
Q
~
Rx = Vee - 0.3 - VLED (il lsi kn
(Is $ 40 mAl
whara VLED
(@lis)
c
it'
"
is the diode (LED) voltage drop at operating current Is.
Example:
Is" 2D rnA
VLEO (@ Is) = 3AV"
Vee .. 5.0V
Rx = B5n
lOMAN·' or equivalent
FIGURE 5. Nonmultiplex Application of the OM7447A
DM5446A/DM7446A,DM5447A/DM7447A
These circuits feature active·low, open collector
high current outputs (Figure 4a). Each output is
capable of sinking up to 40 mA at a maximum
internal drop of O.4V. This high current capability
makes these circuits particularly well suited for
driving the large NSN71 or equivalent type displays
directly. The circuits are also applicable, with or
without the use of external current limit resistors,
to driving lower current displays in the multiplex
mode of drive.
The DM5446A and DM7446A outputs are capable
of withstanding 30V at 'a maximum leakage of
250ILA over temperature. The DM5447A and
DM7447A have a 15V output capability at a
maximum leakage over temperature of 250ILA.
This standoff voltage ability makes the circuits
applicable ,for direct drive to indicator lamp type
displays. Figure 5 shows a typical application of
the circuits with LEOs.
Refer to Table II for the operating temperature
range and package types for the OM5446A/
DM7446A and DM5447A/DM7447A.
DM!?448/DM7448
The DM5448/DM7448 has active high passive
pull·up outputs (Figure 4b) with a TTL fanout of
4. The typical output source current is 2.0 mA at
an output voltage of 0.85V. Each output is
capable of sinking 6.4 rnA with a maximum
internal drop of 0.4 V. Since the output current
level is low the circuit can be used to drive low
current common cathode displays operating in the
non multiplex mode.
The major application of the OM5448/0M7448
is to drive logic circuits, operate high·voltage
loads such as electroluminescent displays through
buffer transistors or SeR switches, or high·current
8·47
t5.0V
R,
" "I-----t-+-+-II-+-+.....
BCD { :
INPUTS
~
LT
RBI
BI/RBO
"I-----+-+-+-II-+-...
9~------~-+~~r-+
6 DMl44B 101-----+-+-+.......
111-----+-+-.
121-----t--+
131---"'--.
SEGMENT
DESIGNATION
DECIMAL
INPUT
-=
Rx rnay be taltulatad using the following equatioll
Rx",5.0-VlEOkn"~ kn
Is-1.6
Is-1.6
[ VlEO O:1.7V@5.0rnAj
Ax :?650n
where:
Rx = PULL· UP RESISTOR VALUE
Is
0:
CURRENT PER SEGMENT IN rnA
Example:'
Is
=
5.0 rnA
Rx = 970.11
FIGURE 6. Nonmultiplox Application of tho OM7448
loads through buffer transistors. Figure 6 shows
the OM7448 in a low current direct drive LED
application.
The operating temperature range and package
types for the OM5448/0M7448 are given in
Table II.
BCD TO 7-SEGMENT LED DRIVERS
OS7856/0S8856, 088857, OS7858/088858
This series of three ci rcuits was designed to provide a wide range of current capabilities in driving
common cathode 7-segment LEOs operating in the
multiplex or non multiplex mode. The circuits,
discussed individually below, have output stages
with varying source current capability designed
for specific as well as general applications.
All circuits accept 4-bit BCD and decode this input
to the desired 7-segment output format for direct
drive to LEOs. In addition, the circuits feature a
lamp test pin for display turn-on check, ripple
blanking-input pin and blanking input/ripple
blanking output pin which may be used to
modulate display intensity.
source current of 6.0 mA at an output"voltage of
1.7V. This current level was designed for directly
driving, without the use of external current limit
resistors, the NSN74 or equivalent type displays in
the nonmultiplex mode of operation.
Each output has a fan-out of 4 and is capable of
sinking 6.4 mA with a maximum internal drop of
O.4V making the circuit suitable for use with logic
circuits. With the use of an external buffer transistor per output the circuit may be used to drive
high current common anode LED displays as well
as high voltage electroluminescent displays. Figure
7 shows a typical application of the OS8856.
Vee
~
5.0V
HI/RBO
D~CIMAl
The three circuits are TTL-OTL compatible and
provide full decoding of the 16 possible input
combinations. All parts operate off of a single
5.0V supply.
POINT
OS7856/0S8856
The OS78561OS8856 output stages, passivepullup (active high, Figure 4b), provide a typical
FIGURE 7. Nonmultiplex Application of the OS8856
»
z
Operating temperature range and package types
for the DS7856/DS8856 are given in Table 11.
Table II gives the operating temperature range and
package type for the DS8857.
D88857
087858/088858
The output stages of the DS8857, active pull-up
(active-high, Figure 4c), source a typical current
The OS7858/0S8858 output stages are active
pull-up (active-high, Figure 4d) like those of the
C
~
,--..,.----..,.-0
r---------~-ov~
I
CD
CD
:C'
5'
CQ
"rnI
v"
CD
CQ
..
3CD
:;,
'-----........
-+_.0.
1---______
DS8851
DS7B5B/DSBB58
FIGURE 4c. Output Stage
FIGURE 4d. Output Stage
of 50 mA at an output voltage of 2.3V. The
circuit was· designed to be used with NSN74 or
equivalent type displays operating in the mUltiplex
mode of drive. With this high current capability
the circuit Can drive up to 16 such digits.
OS8857. The output stages are exactly the same
as the OS8857 except that the internal current
limit resistor per output has been removed.
External current limit resistors must then be used.
This allows the circuit to be customized for a
particular common cathode multiplex or nonmultiplex application. Each output stage, through
its own external resistor, can be programmed to
some current from 50 mA down to a mAo Care
must be taken in not shorting the outputs to
ground because of the excessive current flow that
would result from the Oarlington upper stage. See
Figure 9 for a typical application of the 058858.
The applications of this circuit obviously are not
limited tojustthe NSN74 type of display. Common
cathode displays with high dc current requirements or lower multiplex current levels may be
driven by this circuit with the use of an external
current limit resistor per segment. A typical application of the DS8857 is given in Figure 8.
OS8857 Output Current
v. Voltage
~ r-~r-~~-'~~-r~
58
40
!
j
30
1-+--f'I<:+--+--+--+ DS8857 I
I-+--+-,'k--+--+--+ v", • 5.0V
1-t-t-.p.II-t-+ TA • ,"C
1-+--+--+--f'I<:+--+ V UV
I-+--+--+--+---Pot-+--+--t---C
LT '"
20 t-H-+-++-+-fI<~+-+-;
'0
t-t-t-t-t-t-t-t-~t-1
O'-'-'-'--'-'~~~~
1.6
STROBE
2.0
2.5
YOUT
3.0
3.&
4.0
IV)
INPUT
For multiplex or nonmultiplex appUcations where an external current limit resistor
per sagment is requited,see the output current VI voltage curve for the OS8857 and
use the equation given in Figure 9 to calcullltur the resistor value.
FIGURE 8. OS8857 Tvpical Multiplexing,Sche""
8-49
, Maximum ,output source current per· segment for
t~e 057858/058858 is 50 mAo Operating tem·
perature range and package types are given in
Table II.
low input current, 3.3 mA maximum at 10V
input, makihg th.em suitable .for direct drive from
MOS circuits. The circuits are used to drive the
paralleled segments in multi-digit Ijisplays. Since
both circuits feature accessable collectors and
emitters they may be used' as either common
cathode or anode segment drivers. They feature a'
source or sink current 'capability of up to 50 mA
with a maximum collector to emitter drop of
1.5V over th~ operating temperature range. In
addition, each output i's specified to have a maximum leakage of 100ilA at an output voltage of
10V over temperature. Both circuits oper.ate from
a single supply that can have a maximum voltage
of 10V.
5pecial care must be taken in the use of the
057858 ceramic and the 058858 plastic OIP's.
with regard to not excee,ding the maximum operat·
ing junction temperature of the devices. The maximum junction temperature of the 057858J, is
150°C and must be derated based on a thermal
resistance of 80°C/Watt, junction to ambient. The
maximum junction temperature for the. 0S8858N
is 150°C and must be derated based on a thermal
resistance of 140°C/Watt, junction to ambient.
OS75491 FOUR SEGMENT DRIVER
OS75491, OS8861 MOS TO LED SEGMENT
DRIVERS
The OS75491 is a four-segment driver whose main
application is with multi-digit LEOs operating in
the multiplex' mode of drive. Each package contains four separate segment drivers, each driver
The QS75491 and OS8861 were designed for
MOS calculator applications. 80th circuits feature
DS8858 Output Current
vs Voltage
BCD
INPUTS
y, ~yl
'j -tyy'
,
7
vee ~+5.ov
II/RIO
DECIMAL
POINT
1
." "
"
•
60
DS885S
I
50
•
•
""58
" •
11
15
'::"
14
j:'
A,
,.
1*~,.~,.~,.
~
.§
j
\.
3D
20
I"
,.
•
:1
3,2
~
1'0
3,3
3A
3.5
VOUT {VI
VOi.JT - Vo
,---1,
A
Is=SepnentQl'nat
Vo = LEDdiadtdfopltcumatls
VOUT = DS885hlltplltvoHagltlltc.rrentlsfRt .... phi
Example:
Is" 5.0 mA
Vo '" 1.1V (AT 6.0 mAl
FhlmglllphlYCI;:" i.BV, r.,
"2~GC!
VOUT '" 3.5JV fAT 5.0 mAl
R ,,3.53V -1.1V
)(
5.0 mA
Rx = 36Dn
The.mleqllltfoA IIIIYb,allll ""an !itlHlr 1111 DS71U 01 I•• DSl8U.,.'OPlfltilg
in'thamu!tipIPlJlod'afdrlva.lfth,"ditionll¥Ofutellrop'aetotflrllilhclrlnril
tlke~ intolllDnsiderltilln,thanawtqullllonwollh'lIII'Ittll.fa/Jollilllfonn:
Rx '= VOUT -I:tl - VDR
~D" • D.itIfrMlrdro~lII:,*mlm I.
FIGURE 9. OSS858 Applications
8-50
Vee = 5.0V
TA .. 25°C
VLT = O.BV
\.
40
3.6
3,7
CD
CD
The 058861 is a five segment driver which like the
0575491 is used with multi·digit LEOs operating
in the multiplex mode of drive. Each package
contains five separate drivers, each driver with
free collector and emitter points, Figure 4e.
lNo-....-'\II/\r....- - {
C
~
S:
::l
CC
-.J
I
A typical application of the 058861 is given in
Figure 11 where the 058861 is combined with
the OS75491 to provide a total of nine inde·
pendent sources of LEO segment current from an
M05 calculator. This allows control of the 7·
segments plus decimal point and minus sign. This
combination of circuits is not solely applicable to
just the 8 digit calculator configuration shown but
can be used with a display having as many digits
as desired as long as the multiplexed segment
current requirement does not exceed 50 mAo
SUB (GNO)
TO OTHER
DRIVERS
DRIVERS
I
DM8861 FIVE SEGMENT DRIVER
with free collector and emitter points, see Figure
4e.
TO OTHER
z>
OS75491 (4 per package)
OS8861 (5 per package)
FIGURE 4e. Circuit Schematic
In the multiplex mode of drive, a six digit calculator
needs only two 0575491's to drive the segments
in the display, see Figure 10. The total of eight
segment drivers allows drive to each of the indio
vidual seven segments plus logic control for the
decimal point. Figure 11 shows the 0575491
used in an 8 digit calculator application.
C/)
~
3
CD
...
::l
r-
m
C
C
CII
"0
iii"
ARRA'
SIX
NSN 74
-III: CI. 0. C/. C/.O.
01
D6
Voo
I
• " "
-=-
1
FIGURE 10. 6·Digit Calculator
8·51
:J
'S
~
Refer to Table" for operating temperature range
and package type for the OS8861.
en
z
0875492, OS8S63MOS TO LED
DIGIT bRtVERS
CJ
...
J:.
displays operating in the multiplex mode of drive.
The circuit features six high gain Darlington
connected transistors, with collectors open and
emitters tied to ground (Figure4f), capable of
The OS75492 and OS8863 are digit drivers
designed to drive multi·digit common cathode
LEOs directly from MOS circuits. Since digit
currents are quite high in multiplex operation
MOS circuits usually cannot sink the required
digit select current, therefore these circuits pro·
vide the required CUHent buffering. The two
circuits have differerit current handling capability
as well as different numbers of drivers per package,
each will be discussed individually later.
'i
~
'CU
Q.
,!
Q
Q
w
....
...c
SUIIGND}
v.~~_"""I-_""'_~""'TOOTHER
DRIVERS
0515492 (6 per peckllfla)
DS8B6318p8TplC~ge)
I
The circuits are totally compatible for use with
both the OS75491 and the OS8861. The most
common usage cif the circuits is in MOS calculator
applications where the OS75491 or the OS8861
source the segment current and either the
OS75492 or the OS8863 sink the digit current.
m
OS75492 SIX DIGIT DR IVER
G)
em
G)
(/)
,...
c
:~
.
9
FIGUaE 4f. Circuit Schematic
sinking up to 250 mA with a maximum collector
to ground drop of 1.5V over the operating
temperature range. Low input current of 3.3 mA
maximum at 10V makes the drivers suitable for
direct connection to MOS circuits. Output leakage
is 200llA maximum at 10V over temperature .
Maximum Vec is 10V.
The OS75492 is a ~ix digit LED driver designed
to be used with common cathode multi·digit
en
en
I
z
I'Y_-fl~.....;1__,,,
I
I
I (-,
I '-----I
I
I
I
:::I
.-:;'
I
I
I
I
CD
I
I
I
I
I
iii'
UI
S'
I
5.ov-=.1
I
I
n
.
.
:r
I
I
I
I»
30
L.. ____....J+-.,""".Yv~t-J---..;.L..--'_!......_-_+-_-_+_-_...._---I_ J
":"
I»
nr+
FIGURE 11. Line Reflection Diagram of Rise Time
''\0.83V/
t
CD
'1ft DROP SUBTRACTS
iii'
FROM NOISE MARGIN
IR DROP GENERATES
GROUND lOOP NOISE
r+
c:;"
FIGURE 9. Unbalanced Method
UI
Transmission lines don't necessarily have to be perfectly
terminated at both ends, (as will be shown later) but the
termination used in the unbalanced method will cause
additional distortion. Figure 10 shows the signal on the
transmission line at the driver and at the receiver. In this
case the receiver was terminated in 120n., but the char·
acteristic impedance of the line is much less. Notice that
the wave forms have significant steps due to the
incorrect termination of the line. The signal is subject to
misinterpretation by the line receiver during the period
of this signal transient because of the distortion caused
by Duty Cycle and attenuation. In addition, the noise
margin of the signal is reduced.
---
-
TIME
FIGURE 12. Line Reflection Diagram of Fall Time
BALANCED METHOD
AT DRIVER
fZV/DIV
AT RECEIVER
100 FT TWISTED
PAIR SHielDED
SIGNAL AT DRIVER
_ _ SIGNAL AT RECEIVER
In the balanced method shown in Figure 13, the tran·
sient voltages and currents on the Iine are equal and'
D57830
--
30
'~170
200.slDIV
FIGURE 10. DS75451, DM7400 Line Voltage Waveforms
30
The -signal waveforms on the transmission line can be
estimated before hand by a reflection diagram. Figure 11
shows the reflection diagram of the rise time wave
forms. The voltage versus current plot on left is used to
predict the transient rise time of the signal shown on the
right. The initial condition on the transmission line is an
IR drop across the line termination. The first transient
on the line traverses from this initial point to zero cur·
rent. The path it follows corresponds to the character·
istic impedance of the line. The second transient on the
diagram is at the line termination. As shown, the signal
reflects back and forth until it reaches its final dc value.
Figure 12 shows the reflection diagram of the fall time.
Again the signal reflects back and forth between the line
t~
INPUT
30
BALANCED LINE SIGNAL
OUTPUT
Tite ground loop cummt is much less thin sioml! current
FIGURE 13. Cross Talk of Signal.
opposite and cancel each others noise. Also unlike the
unbalanced method, they generate very little ground
noise. As a result, the balanced circuit doesn't contribute
to the noise poJ.lutiOn of its environment.
8·57
1/1
CJ
~
.;:
...
~
..
CJ
co
co
J:
(J
~
c
::;
c
o
.~
The circuit used for a line receiver in the balanced
method is a differential· amplifier. Figure 14 shows a noise
transient induced equally on line A and line B from line
C. Because the signals on line A and B are equal, the
signals are ignored by the differential line receiver.
Likewise for the same. reason, the differential signals on
line A&B from the driver will not induce transients on
line C. Thus, the balanced method doesn't generate noise
and also isn't susceptible to noise. On the other hand
the unbalanced method is more sensitive to noise and
also generates more noise .
'e
an. unbalance reflection at the terminator. Therefore, the
lines should also be terminated for unbalanced signals .
Figure 16 shows the perfect termination configuration
of a balanced transmission line. This termination method
is primarily required for accurate impedance measurements.
UNBALANCED
BALANCED
1/1
......c
CO
CO
o....
I
ROB'"
z
c(
Rxl/2 Rou" 90
FIGURE 16. Impedance Measurement
SIGNAL ON LINE A
SIGNAL ON LINE.
~
~
DIFFERENCE SIGNAL (A-B) _ _ _ _....._
....
~
The unbalanced method circuit used in this application
note up to this point is the unbalanced circuit shown in
Figure 1. The termination of its transmission line was
greater than the characteristic impedance of the unbalanced line and the circuit had considerable threshold
offset. The measured performance of the unbalanced circuit wasn't comparable to the balanced method. Therefore, for the following comparison of unbalanced and
balanced circuits, an improved termination shown in
Figure 17 will be used. This circuit terminates the line in
60n and minimized the receiver threshold offset.
FIGURE 14. Cross Talk of Signals
5V
The characteristic impedance of the unbalanced transmission line is less than the impedance of the balanc~d
transmission line. In the unbalanced method there is
more capacitance and less inductance than in the balanced method. In the balance method the Reactance to
adjacent wir,es is almost cancelled (see Figure 15). As a
result 'a transmission line may have a 60n unbal.anced
impedance and a 90£2 balanced impedance. This means
that the unbalanced method, which is more susceptible
to I R drop, must use a smaller value termination, which
will further increase the I R drop in the line.
-j .
r-- '>
OOOA
0000
00000
0000
000
13K
ZOCOAX "'
.Jk
b
:;
~
Zo ~
~76
Y'k
a
10g b
000
000..0
00000
0000
000
FIGURE 15. Zo Unbalanced < Zo Balanced
The impedance measurement of an unbalance and .balance
line must be made differently. The balanced impedance
must be measured with a balanced signal. If there is any
unbalance in the signal on the balanced line, there will be
8-58
A plot of the Absolute Maximum Data Rate versus cable
type is shown in Figqre 18. The graph shows the different performances of the DS7820A line receiver and
g
a
log
FIGURE 11. Improved Unbalanced Method
100
~
...
'"
...'"
:5
SINGl~;:ttttt
~TWISTED
w
10
.
SINGLE TWISTED
PAIR SHIELDED
!l
..
x
All WIRE #22
...'"w
:l
~
'"
PAIR
NINEnr'STE?rAIR~
<
"...w
::
OS75452/0M7400'
TERMINATED 100f150n
I
10
~
co
o....
E=::=
f==
noise similar to the unbalance performance shown in the
previous figure. Unlike the unbalanced case, there was
no measurable degradation of the circuits Data Rate or
distortion,
~I
T,
I~
IIII
1.0
1000
100
10
LINE LENGTH (FT)
BIT RATE "
FIGURE 24. Data Rate vs Signal Cross Talk of
OS75452,OM7400
Figure 25 shows the test configuration of the balanced
circuit used to generate worst case Near End cross talk
. ~'~ ~ ,·I c>=
NEAR END
112 OUTV CYCLE
170
INTERVAL PER BIT
BAUD RATE'" ,
,,2
T2
MINIMUM UNIT INTERVAL
,,~
T1
The data in this note was plotted versus Baud Rate.
The minimum unit interval reflected the worse case
conditions and also normalized the diagrams so that
the diagrams were independent of duty cycle. If the
duty cycle is 50% then the Baud Rate is twice the
Bit Rate.
REFERENCES
IC's for Digital Data Transmission, Widlar and Kubinec,
National Semiconductor Application Note AN-22.
Data Bus and Differential Line Drivers and Receivers,
Richard Percival, National Semiconductor Application
NoteAN-83.
RADC TR73,309, Experimental Analysis of the Trans'
mission of Digital Signals over Twisted Pair Cable,
Hendrickson and Evanowski, Digital Communication
Section Communications and Navigation Division, Rome
Air Development Center, Griffis Air Force Base, New
York.
170
CABLE WITH
NINE TWISTED PAIR
Fast Pulse Techniques, Thad Dreher, E-H Research
Laboratories, Inc., The Electronic Engineer, Aug. 1969.
\
8 NEAR END GENERATORS
FIGURE 25. Signal Cross Talk Experiment Using
057830, OS7820A
8-60
Transient Analysis of Coaxial Cables, Considering Skin
Effects, Wigingtom and Nahmaj, Proceedings of the IRE,
Feb. 1957.
Reflection and Crosstalk in Logic, Circuit Interconnections, John DeFalco, Honeywell, Inc" IEEE Spectrum,
July 1970.
l>
~
Applications
Z
.!.o
&
c
::2.
NAnONAL
<
...
(1)
c:
'0
Q.
;
I
z
DRIVER UPDATE-NEW DRIVERS FOR LED
DISPLAYS
I
INTRODUCTION
CATEGORIZING DRIVERS
<
(1)
iii
Many new LED drivers have been introduced in the past
year. This application note picks up where AN·99 left
off and expands into recent developments in LED
displays. If the particular display requirements are
known, inspection of Table I will narrow down the
selection of drivers to the most appropriate few, or
the one that will do the job. Reading the description
provided in this note, or on the data sheet for a parti·
cular driver should help complete the design project.
If more information on drivers in general is desired,
then read on. Since this is im application note, as many
circuit applications as possible for each driver are
included.
Drivers may be categorized by various functions and
conditions. Some of these are:
r-
c::2,
a)
b)
c)
d)
el
f)
g)
h)
Segment drivers or digit drivers
Anode drivers or cathode drivers
MOS compatible or TTL compatible inputs
Inverting or non·inverting outputs
Decoded or straight through drivers
Number of outputs
Current handling capability
Design supply voltage, particularly if an integral low
battery indicator is included
GENERAL CONSIDERATIONS
To multiplex or not to multiplex is an important consid·
eration. Some of the reasoning and arguments, pro and
con, are covered very well in AN·99 and reading of that
application note is recommended. An important factor
affecting display operation is that most I'liulti-digit
displays' presently available are interconnected for
multiplexing only, removing any choice by the systems
des!gner.
The mathemati~s of mUltiplexing is fairly straightfor·
ward. The drive requirement for most LED displays is
stated. in the form of an average segment current. Peak
segment current-the current a driver has to supply-is
derived by dividing the average segment current by the
duty cycle. For instance, it may be desirable to drive a
9-digit LED display, like National's NSA1298, with an
average segment current of 0.7 mAo If the duty cycle
were 10%, derived by driving the 9 digits for equal
periods plus a 10% of period interdigit blanking time,
then the peak segment current would be 7 mA (0.7 mA
+10%). Digit current is then the peak segment current
multiplied by the number of segments that are "ON."
Including the decimal point, the maximum digit current
would be 66 mA (7 mA x 8 segments). In addition to
this rather simple example, the designer needs to account
for the specified variation in segment currents due to
resistor tolerance, etc. and its effect on the digit driver
specifi~ation. However, the example serves to show the
basic mathematics involved.
The design guide in Table I should help in locating
devices in most of these categories.
FEATURES
There are many features available on the newer segment
and digit drivers which help make the overall cost of
production lower or make the end product more appealing or both.
One of these features is pinout. The newer segment and
digit drivers have all the inputs grouped together and all
the outputs grouped together, usually on opposite sides
of the package. This vastly simplifies circuit board layout
often eliminating costly jumper wires and very tight circuit board traces that lead to troublesome solder
bridging.
Another feature is that some of the newer segment
drivers incorporate the current setting resistors internally, saving the cost of purchasing, stocking, forming,
inserting and board layout for discrete resistors.
On many of the newer digit driverS, a new feature is the
self-contained low battery indicator. These indicators are
generally set for 9V battery systems or 6V (4-<:ell) or
4 1/2V (3'cell) battery systems. They are an appealing
sales featu re that warns the purchaser when to recharge
the batteries (if ni-cads) or replace them if they are
throw-aways.
8-61
0...
m
~
C
/ii'
'0
.f
UI
TABLE I.
Refer to LED Dri~er Guide in Front of Catalog
..
Nation"
,
Stu....
OUtput
Current
CNote1l
OH-SbIttI
Output
Vol....
M"
Mo.
Ivl
Number
.
.e
t!G)
>
·c
Q
~
Z
I
!
'&.
.
:::>
G)
>
·c
Q
~
.-;-
z
«
'mAl
DM7446A Production
DM7447A Production
DM7448 Production
D.....
Development
D....7
DS6648
DSB650
088661
DS6658
DS6659
=
DSB856
DSB657
058858
D5BB5B
D.... ,
DSB663
D.....
D58",
DSB856
DSS867
058868
D.....
088870
058871
DSBB72
058873
OS8874
OSS87S
058877
DSBB79
D.....
DS6673
058974
058976
0575491
0575492
DS75493
057''''
40
40
-2
••
Production
Dice
Die,
Dice
D..,
D'"
5
-S
mo<
--50. mal(
-50 mo<
.... 40
Production
Production
Production
Production
'50
Production
500
Production
50
Production
50
Production
-10
Production
Production
110
Production
0--40
Production
350
Production
50
PrGduc:tlon
50
Production
50
Development
50
O....!lIopment
50
Production
'0
Development
5~
Production
-I'
,.
~~
:~
5.'
5,'
5,'
5.5
10
10
10
10
10
1.
1.
1.
1.
,.,.
,.
,.,.
22
••
100
Development
100
Olllelopmel1\
100
,.0
Production
Production
250
-3,
180
Number
of
O....n
7
7
7
•
22
22
I.
I.
4
7
7
9
7
7
7
••
,.
Inverting
Anode
X
7
X
X
9
9
9
X
X
9
X
X
X
X'
' X
X
X
X
X
X
X
X
X'
X
X
X
X
X'
X
6
X
X
X"
X
X
X
X
X
X
X
X
·X
X
X
X
X
X
X
X
X
X
X
X
~
x
X
Comn.nta:
fThrougn ElI:tlfnalTranslmr
For CMOS Watch Circuits
For CMOS Watch Circuits
FQf CMOS Watch Circuits
For CMOS Walch Circuits
For CMOS Watcfl Circuits
For CMOS Watch Circuits
For CMOS Watch Circuits
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
TTL
MOS
Inputs Input.
X
X·
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X'
X'
X
X'
X
X
Xl
X
X
X
X
X
X
'X
9
9
9
•
••
X
X
X
X
X
X
X
X
X
X
9
X
X
X
Xl
X
X
6
X
X
"'......
X
X
Xl
X
X
X
Fo,
eommo•
X
X
X
X
Fo,
Common
Anode
X
X
X
X
X'
X
X
X
X
SlIgment
X
.X
X
X
X
X
X
X
X
•
•
C ....... Digit
X
X
Xl
X
X
X
X
X
X
X
9
""_
"',-
No&
'n_rting
X
X'
7
,.,. •
•
22
22
22
I •.
I.
16
X
X
X
•
•
12
1.
I.
..-
""""
9
9
,. •
,. ••
5.5 .
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
Development
Production
Production
D""
-4
:::
• Production
Dice
...
B4
-7
~roduction
,.,.,.
30
15
NA
5
-4
-4
5
Devalo menl -7
Development -7
Production
50
Production
-S
Production
Production
....
Pa• . (Number
of
Pinll
X
X
X
Lamp Driver With Latch
"With E'mitter Grounded
For 9V Battery With Low Battery
or 9V 8attary With Low Battery
X
~
tThrough External Tran~istOr
PreHt lOUT
For 4.5V Battery With Low Battery
Lamp Driver With Latch
For 9V Battery With Low Battary
For 9V Battery; Shift Input
For 6" BlJltery: Shift Input
0876492 Pin Out
For 4.5V Battery; Shift Input
Internal Set lOUT
For 4.5V BatteIY With Low Batterv
For 6V Battery With Low Bettery
or.vV_DatteryWith UJ~Battefy
"With Emitter GrQl,mded
lOUT Set By ReXT
Note l:Positive current is into the device (sinking).
, Watch Circuits Using LED's
Two new drivers designed to drive LEO displays in
watches are the 058658 and 058659: The 058658 is a
4·digit driver which is basically 4 NPN transistors on a
chip with their emitters tiecj together. The 4 bases are
brought out on one side of the chip and the 4 collectors
on the opposite side to ma~e assembly easier. The
058659 is a constant cl!rrent segment driver designed
to supply 10 ±3 mA. To accomplish this with only a
2.4-2.7V battery, the circuit uses a PNP current mirror
driven by a PNP emitter-follower. This is believed to be
the first all PNP integrated circuit in large scale production. Figure 1 shows a typical watch circuit using these
drivers. If, for reasons of battery life or for a smaller
CAS'
BACK
-i,I~~
-Ij-l i .
SET
DISPLAY
~
ADJUST
I
8-62
-[§Bi
CMO'
TIMING
CHIP
I
SEGMENT
DRIVER
....
DSIB6B
DIGIT
dRIVER
FIGURE 1. Typical Watch Circuit
"D'G'T
7~EGMENT
LED DISPLAY
NSC0101
I
ladies type watch. a smaller display is used, then lower
segment currents can be generated. The watch circuit in
Figure 2 shows just such a circuit. The 058651 will
supply 6.5 ±1.5 mA per segment.
The N5C01.75 are 75% the height of. the N5C0101 used
in Figure rand Gan be spaced closer togethl!r. An even
smaller, brighter display can be made using the N5C0155
which are .55% the height,of the N5C0101.
If the CM05 watch chip is deSigned to drive non·invert·
ing segment drivers, then the 058649 8-segment driver
can be used. The output current of the 058649 has a
much higher battery voltage dependence than the
058651 or 058659, but is more efficient since all display driver current goes through" the display. Figure 3
shows how the 058649 would be connect.ed in a Watch
circuit. With a fresh set of batteries, the 058649
delivers typically 10-12 mA per segment, dropping to
5 mil.. typically at 1/2 battery life.
As might be expected, digital watches are being designed
with more and more features. One of these features
includes the provision for an alpha-numeric representa·
tion for day of the week. This requires a 9·segment
driver, such as the 058647 (inverting) or 058648
(non-inverting). Also some 'designs show a third pair of
digits to show se,gonds or date at the same time hours
,and minutes are being displayed. For these applications,
a 6·digit drivllr such as the 058646 (inverting) can be
used. An example of t~e, application of these circuits
is shown in Figure 4.
,
}>
;----<
Z
.!..
H~+
it
It
::;7 : CRVSTAL T
3Z168Hz
os!:
TIME
voo -
1
~~:tCASE
<
...
~
-::- 1.5V
OSC OUT
IN
c::3.
V DD
VssO~ Voo
MM5829
V~_
SET
c:
"'C
Q.
...
III
t'·5V
f-o
~
I
V",
v'" -
z
~
c
~.
VDD
SEGMENT DRIVER
DIGIT DRIVER
DSIl65D
0$8651
~
ii1
~I
jJ
A l,
'---+ C
'--V~
0...
.l
-' II B B E/ZIC
rm
C
C
iir
A
F/~B
~D
,
NSC0175
LEO
DISPLAY
"'C
F
iii
G
-<
III
FIGURE 2. Low Power Watch Circuit
-::;H~+
1132168Hz
7
~CRYSTALI
V
DD
1
Vssot VOD
-=-1.5V
OsC OUT
OSC IN
TIME
voo-
f-o...LICASE
-L-
V~_
SET
_
t'·5V
f-o
V~
,-
VDD
V"
-
SEGMENT DRIVER
058649
DIGIT DRIVER
DSI!65D
l,
A
~:
,
"---- 0
F
G
COLON
r-- V"
dJ~
,='
I
I CI
I
I
,-,
0 'C/c
.l A
,,~.
NSCD175
LED
DISPLAY
FIGURE 3. Watch Circuit Using OS8649
8·63
.,
Vo ORVOO '
Voo
OSCIN
oseOUT
Voo
WATCH CHIP
v"
-
....L. 1
....L.ft·.
. . L. _~ I.,~
-
T
CASE
I.IV
V..
.
CD
>
·c
VDO
SEGMENT DRIVER
0 ....'
Q
......
DIGIT'DRIVER
V"
V..
~
I
~
!lBIBB.9'BB
FIGURE 4. Alpha·Numeric Data Watch
Clock Applications of LED Drivers
8-64
Clocks are generally viewed at some distance, and there·
fore require larger displays. Larger displays in turn require:
higher operating segment currents. Figure 5 shows a
typical clock circuit-in this case a clock for automobiles.
In this circuit, the segment currents are' set 'to approxi·
mately 45 rnA by the 4 resistors connected to each
OS75491. The OS8870 hex digit driver will sink the
360 rnA maximum digit current.
I,f .a high brightness, large display is desired, then the
application shown in Figure 7 can be used. In this circuit,
2·segment drivers rated at 50 mA each are paralleled to
~upply 100 rnA of segment ·current to the large 0.6 inch
NSN64R display. The digit drivers are also paralleled
to sink the required 700 mAo
Clocks for home use don't require. the. high degree of.'
light output that an ~ulO clock' re,quires. For these
applications it become~ more cost-effective to use two
0S8867's ~n parallel to produce a.. typical segment
current of 28 rnA. The digit driver in this case can be a
OS75492 and each digit driver will sink typically
208 mA with a figure 8 displayed and the colon dis·
played. This application is illustrated in Figure 6.
Calculator Applications of D.isplay Drivers
The key to low cost calculators has been to reduce the
number of components required to an absolute mini·
mum. An. example of. an extremely simple, low 'cost
calculator is shown in Figure 8. The DS8877 driver will
sink 35 rnA min and consists of 6 drivers per package.
-~
Z.087162 MHz
~
~DI--
CO
22M
&-i'~
BATTERY
5
OSC 1
+
~
.-11?
I
·•
10kj
,
"
3
'.l :-'"v
+
'
'"
7
GND
f
0-
•
";"
M,
M,o
H,
H10
• •" "
SWCOLON
141"
17
,
18
7
15
~DS7""
•
lOOk
,r---
~
c:>- '
• 14
7 ,RIGHTN'SS
(4) NSN14R - tC0rM10N CATHODE)
51012
3
·
Voo
•
V
!"
•
•
"
~
A
•....
IN914 ~
II- ..'"
3
.."
J'..
5
"
+
'---
~'
iil
'--,.--
0...
!"
C
C
Iii'
't:I
iii
-<
(II
7
•
"
"~
,.
A
I~ I~
,
•
, '"
V
IG. ITloN
~
...c
°l-I l-I
,~J
-
10
~
,....--
m
•
+
'-,.-- -,.--
,....--
a
1
z
r-
OS8810
VO.TAGE
-
~ ~ l-I - l-I
JfflD D.
35
"
c:
'&.
,. -~"
V
, !"
'50
'/2W
" ,
,
OS15491
',
MM6J18
MOSCLOCK
"~=~
10
5
,
V
d 18
V"
<
...
'/tW-
•
A
i
:::!,
CD
1,)1511
OSC 2 3
IN4003
C
,
2;'~
SET
HOURS
I:U4
~
..
-1.y -1'?
SET
MINUTES
FIGURE 5. Automobile Clock
7V
'4V
1.sEGMENT LINES
V';'
'0'ov
0,,'
(I)fIsio"R
COMMON·CATHODE
LED DISPLAYS
MM5J14
6-0IGIT
LINES
III\I"CO'
+-__-'Voo
~~L___
J
:DS":'' _ _ _
OV
NOIe: SeI "6311 dob sIaHt I.r rezaaioing I1Iquirtd circuitry fpr synch••net MUX osc.
FIGURE 6. Clock For ac Power
8·65
,v
••v
......
7-1EGMEMTLlIes
DlI88t
DSI.t
MM5311-MIt&314
+
+
.
.~
Q
~,
ov
~
.DtI: ... MM53lll11'ilsd........ ftf ..... .....,circuitry.
FIGURE 7. High Brightn.... Large Digit Clock
MALLOR!-::
+'
MNI81140R":" LOY
EOUtV.
-
.,
--1-~
~.....
f'o.i-......
'0-:-
......
~
......
It
Sf
.. .
So
. ..I
_,73&
D.
D2
D3
D4
D6
D.
1
I
v•
VDD
I
',an
DP
DP
" SWITCH
(OPTIONAl)
-'--
~
~.....
•.....
......
1
I
~
.....
~..... ~. ~
~......
. ???'???w. .
"0.:-
OS,877
......
•.....
•......
K£YBOARD
---rFIGURE 8. &-Digit Calculator Configuration.
......
SWlT"
»
z
except for the absence of any specification regarding a
low battery indicator.
Just because the calculator gets more complicated
doesn't mean that the component count has.to increase.
In Figure 9, the calculator circuit has 2 less components
than the circuit in Figure 8 (one switch and one resistor).
~
&
Rechargeable Battery and 3 or 4 Cell Systems
Yet this calculator provides an 8·digit floating point dis·
play with memory and constant. In addition the OS8864
display driver supplies a low battery indication besides
driving 9 digits. This low battery indicator supplies cur·
rent to turn on the decimal point segment in the digit 9
position whenever the battery voltage drops into the
6-7V region. It is specified to be "ON" if the Vec is
6V or less and to be "OF F" for any voltage over 7V.
All of the previous discussion and applications have
applied to a single 9V throw·away battery system.
Rechargeable cells are expensive, and it would require
6 cells to work in the previously described circuits.
It is even cost effective to replace an expensive recharge·
able cell with a less expensive segment driver. Also dc-todc converters can be obtained for less than the cost of
two cells. The following applications apply to just such
systems.
Even a sophisticated circuit as the Programmable Financial Computer shown in Figure 10 doesn't require any
driver circuitry more complicated than a single OS8864.
But first let us consider the question of just how many
cells to use. Any calculator system using less than 6 cells
will supply less than 6.6V end of life (assuming 1.1 V per
cell to be end of useful life for a nickel-cadmium
rechargeable cell.) Most calculator chips require at least
6.5V to work. Therefore any system of fewer than
6 cells will require a dc-to-dc converter to raise the
voltage for the MOS calculator chip.
If for some reason, such as ac operation, or different
battery voltage, etc., a low battery indicator is not
desired or needed, then the OS8855 can be used. It is
identical in specification and pin out to the OS8864,
o::::!.
<
..,
CD
C
"0
c..
II)
;
I
z
~
o::::!.
<
CD
CiI
0..,
r-
m
o
o
iii'
"0
or
<1/1
r!~~~~~ --+ 9.0V
EDUIV.
12
!!
K1 VSs
~~2
K3 01
'--.
(OPTIONAL) 3
"'-o.!-....
1"02-....
~
'-02-.....
~
.......
"'-o.!-
.....
~
.......
~
~
,
15
S.
14
s"
1
16
s..
S,
10
S.
MM!i138
0'
4
,
03
04
24
11
8
~
06
01
0'
23
22
21
II
DP
s" O"PLAt
RESET
08
20
,
OSVOD 6
S, ~ S, S. S. s" S.
NSAI'"
c/c/Gc/·
C/G--'-I
C/ C/ EI
oP
c/ c/ CI CI
M
M
~
M
EI
M
M
~
~
tS
.....
I
rn
V0V
INo
-
POWER
SWITCH
~
......
4
-
0
OS8864
r'ol-.... ~
..... ~
. ....
~
~.... ~
f"ol-
,
"-
:
, , ~
c
......
~
KEYBOARD
CALCULATOR CHIP
DIGIT DRIVER
DISPLAY
FIGURE 9. Memory Calculator
8-67
LED'
DISPLAY
,---
..::..
9V"'::"
~,
I
j-
D~FJ~.
UD
DATA
KEYBOARD
AND
\
1 X4
CONTRQL
KEYBOARD,
POWE.
SWITCH
LED
ALARM
PROGRAMMER
INDICATOR
~------~~------~--~~--~
ON
,FIGURE 10. Low Cost Hand'Held Programmable Financial Computer Using the MM5762 Calculator and MM5765 Programmer ,
...
Q)
>
·c
Q
co
:t
~
I
- VaAT
-=-4 CELLS
_
@1.5VEACH
\
f.OIGITLINES
FIGURE 11. 4-Cell Calculator System
8·68
Next, a GAAs LEO display requires a 1.7-2.0V drop to
operate. If we could get segment and digit drivers that
dropped less than O.3V each, the required supply for the
display would be 2.6V min. This eliminates the use of
1 or 2 cells to operate the display directly. The most
efficieht, least power wasting system would use 3 cells
to operate the display directly (since 'it takes 3/4 or
more of the power in a calculator) aniJ use 'a 3V to 8V
converter to run the MOSchip.
A compromise system using 4 cells can be constructed.
In, this system the calculator chip's Vss terminal is
connected to 'the positive batterY terminal,so that the
MOS calculator chip supplies direct segment drive, yet
all of this current flows from the battery, not the dc·toclc converter. Such a system is shown in Figure 11. The
reason 4 cells are required is that the MOS chip requires
at least 2V across its segment drivers in order to generate the required segment current.
Any 3-cell system also requires the use of a segment
driver, otherwise all of the segment current, e.g" display
current, would have to be generated by the MOS 'chip
off of the dc-to-dc converted 8V supply and all of the
efficiency we hoped to gain from using 3 cells would be
lo,st; Battery current drain would at least double and
typically triple with the resultant drastic decrease in
battery life;'
This system does require a digit driver with a lower output drop than the OS8864's Oarlington outputs. The
OS8864 'is specified to be less than1.5V which is adequate in 9V systems. Therefore a satura,ting output
driver like the OS8872 or 058873 is required. Their
outputs are specified at less than' O.5V. Their Ilinouts
'Ire identical to the 0S8864 and the OS8872 has no low
battery indicator, while the OS8873 does.
In a 3 cell system, one cell of the 4 cell system above is
traded for a segment driver (Figure 12).
The OS8867 segment driver has 8 drivers, each designed
to supply 14 mA segment current, independent of supply voltage. The 058973 9-digit driver will sink 100 mA
typically and has a low battery indicator set to turn on
the decimal point segment at the digit 9 time if the battery voltage drops bel'ow 3.1 V. It will be off for any
battery voltage greater than 3.5V.
Some ,other drivers that have particular uses, are the
OS8844, OS8865 and OS8871. The OS8844 is a 7-digit
driver with Oarlington outputs which are specified
like the 058864. The OS8865 is an 8-digit driver which
just adds one driver to the OS8844 and is in an 18-pin
package instead of the 0S8844's 16-pin package. The
058871 has a saturating output similar to the OS8872
and OS8873 (specified at 0.5V) and has 8 drivers in an
l8-pin package_ These drivers are useful for smaller
6-digit calculators (Figure 6). They are also useful for
the newer scientific calculators that have 1-2 or more
digits_ One example of this application is shown in
Figure 13_
Some Newer Driver Circuits
One scheme to reduce the numbe( of drivers or the
number of pins on a driver resulted in the 0S8868 which
is a 12-digit driver with low battery indicator all in an
18-pin package. This bit of magic is accomplished by
incorporating a 4 input' decoder on chip 'wi~h the drivers
and by feeding the low battery condition information
back into the MOS calculator circuit through one of the
input pins. Of course this requires a special calculator
chip to drive the OS8868. One such calculator circuit is
the MM5758 Scientific Calculator shown i'n the application bl,ock diagram in Figure 14_
...
o
...
,...
m
C
C
iii'
MU5760
SCIENTIFIC
CALCULATOR
I')
-B.B.B.B.B.B.B.B.
-=-
'tJ
!
4.5V
v,,
FIGURE 12. Typical 3-Cell Mathematical Calculator Circuit
r;,
I!J
FIGURE 13. 14-Digit Calculator'
8-69
~
Anbtherinterestingscheme to reduce package size and
number of interconnections is shown in Figure 15.
Q.
.!!2
mentary MOS calculator chip. One of these is the
MM5784. The interconnection diagram is shown in
Figure 16.
o
ow
The digit driver in this application, the OS8874, is a
shift register that only requires a SET input to set the
first digit driver and clock to step the "ON" signal from
the first to the second and on down to ,the 9th driver.
The SET signal also resets the 9th driver. One added pin
is used for a low battery output. This allows a 9-digit
driver to be put in a 14·pin package. In the OS8874, the
low battery indicator is set for a 6-cell (9V) battery
system. The OS8876 is a 0S8874 with a 4-cell low
battery system and a 3·cell version is the OS8879. Th is
driver also requires a special compatible and comple·
....
CONCLUSION
In this application note we have tried to stay away from
a cookbook approach. Rather, we have tried to stir the
interest and ingenuity of the reader in applying various
LEO drivers to the system design problem that may be
facing the reader. You are invited to inspect the specific
data sheets of any devices that seem to apply to your
application to enable you to complete your design calculations. May your new design be a winner!
.
-=-
Q)
.~
4.5V
o
~
'7'
Z
os}
TJ:""""
11,531
f8~~ MAXREF~I----j
I
-If-Il---rt
a.018iO.00Z
(0.46 to,OS}
0.009--1
(O,Z3)
"" '.03'
R"
IrO.
3ZO
-----r
0(190
0.050 TVP 12291 MIN
(1,21)
•
11100
(2,54} TVP
0.009
0,015
! 0325';'0,025
r
1-.
_0.016-1
6-Lead Molded Mini-DIP (N)
DIANOM
0.09201ANOM
PIN NO, I IDENT
~.'" ~
,f...,'-0.130
±0.OO5
'J
~:::
....~
, ~~
'J
0.130
to.otIS
rl,::~,
~:~.
,~~; J L
-:..!
PIN NO.1 IDENT
TVP
'04'
TVP
M'N
0.100
TY'
S Lead Molded Mini DIP (N)
0.092
1·~.032S -0.015
+tJ.OZ5J
MAX
~,
~ c~,::~ ':;I,~' M'.
1"'''1 ~r
Ir""'\t4'
K:::JF....
f~.::-J'.01'
1-0.325 -8.016
0.100
TV'
10 Lead Molded DIP (N)
14 Lead Molded DIP (N)
9-5
0.092
F!1F~~~~~!
OIANUM
0.250
:to.ODS
PIN NO. IIOENT
'+.F;~'F.F'i'::1=r:;'i"T;r-r.;d--1
r'.1801
~r
Id~
--\-lDt5
I IlJ2S -O.81S-i
-10.025 I
I-
pc ""J~.~.~.D.13O
..
~.mmm
:.V' . .=:11.
D
.. "
--
Ir D. "D.
D
MIN
"
D,~J
±0.011i
I .1 ..,,1
\--
:to.ODS
O.0Ij5
n."
0.015
II:I'
---1 f-- to.003
~TVP I--
D.MAX
03D
D.'20
to.005
I'
t-o.
325 +0.025
:1
0.025
to.015
-0.015--1
16 Lead Molded DIP (Nf
=tJ
--
l
j
l
0.100
TYP
~~ O.OIB
tll.Do3
18 Lead Molded DIP (N)
-~~:::::
1-----1.120MAX----~_I
0,004
0.006
0.002
RAD
PIN NO.1
!DENT
0.010
0.025
II 1
tl:~~~
~~~-y
PIN NO.1
IDENT
r,::::~:::~=~=D=i"i:"
0.009
O.DHi
I 0425 +0.025
\
1--.
-0.015--1
±::!~~
.
-t~
'04D
TV' .
•
~
,DT--J
0.050
±0.015
.'
I
f--
I l;'
0.100
:to,010--1
~
\1
0.018
:!:O.OfIl--lf.--
t~
°M~~O
~
=+'
O~I~5
D.'"
22 Lead Molded DIP IN)
Il-
0.010--1
0.040
.14 Lead Flat Package (W)
0.050
:to.oOs
INCHES TO MILLIMETERS CONVERSION TABLE
PIN NO.1
!DENT
1~
D.'"
16 Lead Flat Package (W)
9-6
INCHES
MM
INCHES
MM
INCHES
MM
0.001
0.0254
0.010
0.254
0.002
0.003
0.0508
0.0762
0.1016
0.020
0.508
0.762
0.100
0.200
2.54
5.08
0.300
0.400
0.500
7.62
10.16
12.70
0.600
0.700
0.800
0.900
15.24
17.78
20.32
22.86
0.004
0.005
0.006
0.007
0.008
0.009
0.1270
0.1524
0.1778
0.2032
0.2286
0.030
0.040
0.050
0.060
0.070
0.080
0.090
1.016
1.270
1.524
1.778
2.032
2.286
:-TJ,D
-t-~~~
O~I~5
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19 Create Date : 2016:08:11 13:27:30-08:00 Modify Date : 2016:08:11 14:13:55-07:00 Metadata Date : 2016:08:11 14:13:55-07:00 Producer : Adobe Acrobat 9.0 Paper Capture Plug-in Format : application/pdf Document ID : uuid:f4b3581c-695b-5640-9e64-f800476d8c71 Instance ID : uuid:ca35497a-94e1-584d-8a13-ccdb321cb39f Page Layout : SinglePage Page Mode : UseNone Page Count : 460EXIF Metadata provided by EXIF.tools