1975_RCA_High_Reliability 1975 RCA High Reliability
User Manual: 1975_RCA_High_Reliability
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High-Reliability Devices
- - -,
Power Transistors / RF/Microwave Devices /Integrated Circuits
A New Approach To Data Service
1975 RCA Solid State DATABOOKS
Seven textbook-size volumes covering all current commercial
RCA solid-state devices (through January 1, 1975)
Linear Integrated Circuits and DMOS Devices
(Data only) .............................. SSD-201 C
Linear Integrated Circuits and DMOS Devices
(Application Notes only) .................... SSD-202C
COS/MOS Digital Integrated Circuits ........... SSD-203C
Power Transistors .......................... SSD-204C
RF/Microwave Devices ......................SSD-205C
Thyristors, Rectifiers, and Diacs ..............SSD·206C
High-Reliability Devices ..................... SSD-207C
Announcement Newsletter: "What's New in Solid State"
Availabe FREE to all DATABOOK users.
"Bingo-type Response-Card Service" included with Newsletter Available FREE to all DATABOOK users.
Update Mailing Service available by subscription.
Indexed Binder available for Update Filing.
NOTE: See pages 3 and 4 for additional information on this
total data service. To qualify for Newsletter mailing,
use the form on page 4 (unless you received your
DATABOOK directly from RCA). You must qualify
annually since a new mailing list is started for each
edition of the DATABOOKS.
nell
High-Reliability Devices
This DAT ABOOK contains. descriptive text, data,
and related application notes on high-reliability
power transistors, rf power transistors, thyristors,
and integrated circuits presently available from
RCA Solid State Division as either standard or
custom products. For ease of type selection, a
complete index to these high-reliability devices is
given on pages 6-1 O. Text material and data are then
grouped according to type of devices: (a) power
transistors, (b) rf power transistors, (c) thyristors,
(d) linear and COS/MOS integrated circuits.
For ease of reference, data sheets in each category
are arranged as nearly as possible in order of typenumber sequence. Because some data, sheets
include more than one type number, however,
some types may be out of sequence. If you don't
find the number you're looking for where you
expect it to be, please refer to the Index to Devices
on pages 6-10.
Trade Mark(s) Registered ®
Marca(s) Registrada(s)
Copyright 1974 by RCA Corporation
(All rights reserved under Pan-American Copyright Convention)
Printed in USA111-74
Information furnished by RCA is believed to be accurate and reliable. However, no responsibility is assumed
by RCA for its use; nor for any infringements of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of RCA.
RCA Solid State I Box 3200 I Somerville, N.J., U.S_A. 08B76
RCA Limited I Sunbury-on-Thames I Middlesex TW16 7HW, England
RCA s.a. I 4400 Herstal I Liege, Belgium
2
RCA Solid State
Total Data Service System
The RCA Solid State DATABOOKS are supplemented throughout
the year by a comprehensive data service system that keeps you
aware of all new device announcements and lets you obtain as much
or as little product information as you need - when you need it.
New solid-state devices and related publications announced during
the year are described in a newsletter entitled "What's New in Solid
State". If you obtained your DATABOOK(s) directly from RCA,
your name is already on the mailing list for this newsletter. If you
obtained your book(s) from a source other than RCA and wish to
receive the newsletter, please fill out the form on page 4; detach it,
and mail it to RCA.
Each newsletter issue contains a "bingo"-type fast-response form for
your use in requesting information on new devices of interest to you.
If you wish to receive all new product information published
throughout the year, without having to use the newsletter response
form, you may subscribe to a mailing service which will bring you all
new data sheets and application notes in a package every other
month. You can also obtain a binder for easy filing of all your
supplementary material. Provisions for obtaining information on the
update mailing service and the binder are included in the order form
on page 4.
Because we are interested in your reaction to this approach to data
service, we invite you to add your comments to the form when you
return it, or to send your remarks to one of the addresses listed at
the top of the form. We solicit your constructive criticism to help us
improve our service to you.
3
Order Form for ''What's New in Solid State"
and for further information on Update Mailings and Binders
Please fill out just one copy of this form, and mail it to:
(a) from U.S.A. and Canada:
RCA Solid State Division
Box 3200,
Somerville, N. J., U.S.A. 08876
(b) from Latin America and Far East:
RCA Solid State
I nternational Sales
Somerville, N. J., U.S.A. 08876
(c) from United Kingdom, Europe, Middle East, and Africa:
RCA Limited
RCA s.a.
Sunbury·on·Thames
or 4400 Herstal
Liege, Belgium
Middlesex TW16 7HW, England
o Please add my name to the mailing list for "What's New in Solid State"
OPle~se send me details on obtaining update mailings for my DATABOOKS
and a binder for filing of supplementary material.
1 1 1 1 1 1 1 1 1 1 1 1 1 1 I
Name
I 1 I I
(Initials)
(Last)
Company
Address
Home
Busoness
1I
II
81
II
III
III
I II
III
II
II
II
II
(Number)
(City)
I
I
I
I
II
II
II
II
II
II
II
II
III
III
III
III
IIIIIIIII
II I I I I I I I
'--1'--1"-'11"-'10-1'-""1I
IIIIII I II
(Street, RFD, P.O. Box)
'--1
(State or Prov.)
(Country)
Function: (Check On••
A0
B0
C0
Do
E0
F0
GO
H0
I 0
J 0
K 0
4
Activity: {Check Onel
A 0 Broadcast
Executive/Administration
B 0 Communication
Purchasing/Procurement
C 0 Instrumentation/Control
Research/Development
o 0 Computer/Data Processing
Design Engineer
E 0 Computer, Peripheral
Application/Components
F 0 Automotive
Engineer
G 0 Industrial
Production/Manufacturing
H 0 Medical
Documentation/Library
I 0 Research
Reliability/QA
J 0 Transportation
EducationlTrairiing
K 0 Consumer, Electronic
ProgramlProject Management L 0 Consumer, Appliance
Marketing
M 0 Space
N 0 Ordnance
0 0 Avionics
p 0 Electronic Warfare
(Zip or Pstl. Zone)
Product Interest:
(Indicate order of interest if
more than one is marked)
AD Linear IC's
BDOigitallC's,COS/MOS
cD Digital IC's, Bipolar
oDThyristors/Rectifiers
eDUqUid Crystals
FDSemiconductor Diodes
GO RF Power Semiconductors
HDMOSFETS
I DPower Transistors
J OPower Hybrid Circuits
Table of Contents
Pages
Index to High-Reliability Solid-State Devices. . . • . . . . . . . . . . . . . . . . . . . . . . ..
6
Index to Application Notes .......................•................• 10
Introduction to High-Reliability Solid-State Devices ...................... 11
High-Reliability Power Transistors ....................................
JAN, JANTX, and JANTXV Types .........................•.....
Custom (Non-JAN) Types ......................•...............
Radiation-Hardened Types ......................................
Application Notes ............................................
15
30
38
49
51
High-Reliability R F Power Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 67
JAN, JANTX, and JANTXV Types ..............................• 79
HR-Series Types .............................................. 85
Premium and Ultra-High-Reliability Types .........................•135
Application Note •............................................179
High-Reliability Power Hybrid Circuit
(Multi-Purpose 7-Ampere Operational Amplifier) ..................... 183
High-Reliability Thyristors .....•.......................•........••.•193
Triacs ...........................................•..........200
Silicon Controlled Rectifiers .............•......................212
High-Reliability Integrated Circuits ...................................225
Linear Types ...........................................•....241
DMOS Devices ...............................................403
Linear IC Application Notes .....................................415
COS/MaS Types .............................................427
COS/MaS Application Notes ...............................•....706
Appendix - Test Circuits (COS/MaS) and Dimensional Outlines ........ 726
Operating Considerations for RCA Solid-State Devices .................... 740
5
Index to High-Reliability Solid-State Devices
Type
Page
Product
Line
Description
2N681 *
2N682*
2N683*
2N684*
2N685*
2N686*
2N687*
2N688*
2N689*
2N690*
2N2102*
2N3054*
212
212
212
212
212
212
212
212
212
212
38
38
PWR
PWR
25-A silicon controlled rectifier
25-A silicon controlled rectifier
25-A silicon controlled rectifier
25-A silicon controlled rectifier
25-A silicon controlled rectifier
25-A silicon controlled rectifier
25-A silicon controlled rectifier
25-A silicon controlled rectifier
25-A silicon controlled rectifier
25-A silicon controlled rectifier
Medium-power "-PAn transistor
Hometaxial-base medium-
2N322S*
2N3263*
213
39
SCR
PWR
5-A silicon controlled rectifier
High-speed n-p-n power
SCR
SCR
SCR
SCR
SCR
SCR
SCR
SCR
SCR
SCR
Product
Line
Type
Page
2N5572*
2N5573*
2N5574*
2N5578*
202
202
202
43
Triac
Triac
Triac
2N5754*
2N5755*
2N5756*
2N5757*
2N5781*
203
204
204
204
Triac
Triac
Triac
Triac
44
PWR
2N5784*
44
PWR
2N5954*
2N6033*
45
45
PWR
PWR
2N6056*
46
PWR
2N6079*
46
PWR
2N6248*
2N6251 *
47
47
PWR
PWR
2N6385*
48
PWR
2N8479*
49
PWR
2N8480*
49
PWR
49
PWR
49
PWR
PWR
power n-p-n transistor
transistor
2N3265*
39
PWR
2N3525*
2N3528*
2N3529*
2N3650*
2N3651*
2N3652*
2N3653*
2N3654*
2N3655*
2N3656*
2N3657*
2N365S*
2N3688*
2N3669*
2N3670*
2N3773*
213
213
213
214
214
214
214
215
215
215
215
215
216
216
216
40
SCR
SCR
SCR
SCR
SCR
SCR
'SCR
SCR
SCR
SCR
SCR
SCR
SCR
SCR
SCR
PWR
2N3870*
2N3871*
2N3872*
2N3873*
2N3S79*
217
217
217
217
40
SCR
SCR
SCR
SCR
PWR
2N3896*
2N3897*
2N3898*
2N3899*
2N4036*
2N4102*
2N5240*
217
217
217
217
41
213
213
41
SCR
SCR
SCR
SCR
PWR
SCR
SCR
PWR
2N5262*
42
PWR
High-speed n-p-n power
transistor
2N410,4
PWR
2N5320*
42
2N5322*
43
PWR
2N5441 *
2N5442*
2N5443*
2N5444*
2N5445*
2N5446*
2N5567*
2N5568*
2N5569*
2N5570*
2N5571*
200
200
200
200
200
200
201
201
201
201
202
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
5-A silicon controlled redifier
2-A silicon controlled rectifier
2-A silicon controlled rectifier
35-A silicon controlled rectifier
35-A silicon controlled rectifier
35-A silicon controlled rectifier
35-A silicon controlled rectifier
35-A silicon controlled rectifier
35-A silicon controlled rectifier
35-A silicon controlled rectifier
35-A silicon controlled rectifier
35-A silicon controlled rectifier
12.5-A silicon controlled rectifier
12.5-A silicon controlled rectifier
12.5-A silicon controlled rectifier
Hometaxial-base n-p-n
power transistor
35-A silicon controlled rectifier
35-A silicon controlled rectifier
35-A silicon controlled rectifier
35-A silicon controlled rectifier
High-speed n-p-n power
transistor
35-A silicon controlled rectifier
35-A silicon controlled rectifier
35-A silicon controlled rectifier
35-A silicon controlled rectifier
Medium-power p-n-p transistor
5-A silicon controlled rectifier
2-A silicon controlled rectifier
High-voltage n-p-n power
transistor
High-voltage, high-speed n-p-n
transistor
General-purpose n-p-n power
transistor
General-purpose p-n-p power
transistor
40-A silicon triac
40-A silicon triac
40-A silicon triac
40-A silicon triac
40-A silicon triac
40-A silicon triac
1O-A silicon triac
1a-A silicon triac
10-A silicon triac
1a-A silicon triac
15-A silicon triac
*High-reliability versions of these types are available on a custom basis.
6
2N6381 *
Description
15-A silicon triac
15-A silicon triac
15-A silicon triac
Hometaxial-base n-p-n power
transistor
2.S-A silicqn triac
2.S-A silicon triac
2.5-A silicon triac
2.5-A silicon triac
General-purpose p-n-p power
transistor
General-purpose p-n-p power
transistor
Medium-power p-n-p transistor
High-speed n-p-n power
transistor
8-A n-p-n Darlington power
transistor
.High-voltage n-p-n power
transistor
High-power p-n-p transistor
High-voltage n-p-n power
transistor
10-A n-p-n Darlington power
transistor
Radiation-hardened n-p-n
power transistor
Radiation-hardened n-p-n.
power transistor
Radiation-hardened n-p-n
power transistor
Radiation-hardened n-p-n
power transistor
VHF/UHF n-p-n power
transistor
UHF n-p-n power transistor
UHF n-p-n power transistor
VHF/UHF n-p-n power
transistor
VHF/UHF n-p-n power
transistor
VHF/UHF "-p-n power
transistor
UHF n-p-" power transistor
VHF n-p-n power transistor
VHF/UHF n-p-n power
transistor
VHF/UHF n-p-n power
transistor
40279
135
RF
40294
40296
40305
139
144
150
RF
RF
RF
40306
150
RF
40307
150
RF
40414
40571
40578
154
158
163
RF
RF
RF
40605
173
RF
40606
173
RF
VHF/UHF n-p-n power
CA101!...
CA101A!...
CA107!...
CA108!...
CA10SA!...
CAllI!...
CA723!...
CA741!...
CA747!...
CA748!...
CAI558!...
CA3000!...
CA3001!...
CA3002!...
CA3004!...
CA3006!...
CA3015A!...
241
241
249
254
254
259
284
270
270
270
270
276
282
288
293
298
302
LlC
LlC
LlC
LlC
LlC
LlC
LlC
LlC
LlC
LlC
LlC
LlC
LlC
LlC
LlC
LlC
LlC
transistor
Operational amplifier
Operational amplifier
Operational amplifier
Operational amplifier
Operational amplifier
Comparator
Operational amplifier
Operational amplifier
Operational amplifier
Operational amplifier
Operational amplifier
DC amplifier
Video amplifier
IF amplifier
RF amplifier
RF amplifier
Operational amplifier
Index to High-Reliability Solid-State Devices (Cont'd)
Type
Pago
Product
Lina
CA3018/•.•
CA3019/•••
CA3020A/ ...
CA3026/•.•
CA30288/ .•.
CA3039/•.•
CA3045/•••
CA3049/•••
CA3058/ •••
CA3078A/ ...
CA3080/•••
308
316
320
325
331
336
·340
345
350
356
363
LIC
LlC
LlC
LIC
LIC
LIC
LlC
LlC
LlC
LlC
LlC
CA3080A/•••
363
LlC
Description
Type
Pago
Product
Line
Description
Transistor array
CD4030A/ .••
C04031A1.••
C04032A/•••
539
543
548
COS/MaS
COS/MaS
COS/MaS
Quad exclusive-OR gate
64-stage static shift register
Triple serial adder (positive
C04033A/•••
C04034A/•.•
C04035A1•..
517
552
557
COS/MaS
COS/MaS
COS/MaS
MSI 8-stage static bus register
C04036A1.•.
Diode array
Wide-band power amplifier
Dual differential amplifier
Differential/cascode amplifier
Diode array
Transistor array
logic)
Dual differential amplifier
Zero-voltage switch
Micropower operational amplifier
Operational transconductance
amplifier
Operational transconductance
370
370
370
375
CA3094A/ .•.
375
CA3094B/ .•.
375
CA31 00/ ••.
.cA3118/ .••
CA3118A/ ...
383
389
389
CA3130A/ .••
397
CA3130B/ .••
397
C04000A/.••
427
C04001A/ •••
CD4002A/ .•.
CD4006A/•.•
CD4007A/••.
427
427
433
438
C04008A/ .•.
444
Positive voltage regulator
Positive voltage regulator
Positive voltage regulator
Programmable power..switch/
amplifier
Programmable power-switch/
LlC
amplifier
Programmable power-switch/
LlC
amplifier
Wide.tJand
operational amplifier
LIC
High-voltage n-p-n transistor array
LlC
High-voltage n-p-n transistor array
LlC
amplifier
COS/MOS-bipolar operational
LlC
amplifier
COS/MOS-bipolar operational
LlC
amplifier
COS/MaS
Dual 3-input NOR gate plus
inverter
COS/MaS
Quad 2-input NOR gate
Dual4-input
NOR gate
COS/MaS
18-stage static shift register
COS/MaS
COS/MaS
Dual complementary pair plus
inverter
4-bit full adder with parallel
COS/MaS
LlC
LIC
LlC
LlC
carry
:04009A/ ..•
450
COS/MaS
:0401 OAf•..
450
COS/MaS
:04011A/ •••
:04012A/ .•.
:D4013A/ ..•
456
456
463
COS/MaS
COS/MaS
COS/MaS
:D4014A/•..
:04015A/ ...
468
473
COS/MaS
COS/MaS
:D4016A/ .•.
:D4017A/ ...
:D4018A/•.•
478
484
489
COS/MaS
COS/MaS
COS/MaS
494
497
502
507
456
512
427
517
524
529
533
COS/MaS
COS/MaS
COS/MaS
COS/MaS
COS/MaS
COS/MaS
COS/MaS
COS/MaS
COS/MaS
COS/MaS
COS/MaS
:04019A/ •••
04020A/.••
D4021A/ .••
04022A/•.•
04023A/•••
04024A/ •.•
D4025A1 .•.
04026A/ ..•
D4027A1•.•
D4028A/ •••
D4029A/ •••
Hex buffer/converter
(inverting)
Hex buffer/converter
(non-inverting)
Quad 2-input NAND gate
Dual4-input NAND gate
Dual "0" flip-flop with
set/reset
8o$tage static shift register
Dual4-stage static shift
register
Quad bilateral switch
Decade counter/divider
Presettable divide-by-"N"
counter
Quad AND-OR select gates
14-stage binary counter/divider
8o$tage static shift register
Divide-by-8 counter/divider
Triple 3-input NAND gate
7-stage binary counter
Triple 3-input NOR gate
Decade counter/divider
Dual J-K master..slave flip-flop
BCD-to-decimal decoder
Presettable up/down counter
4-stage parallel in/out shift
register
561
COS/MaS
4-word-x-8-bit RAM (binary
C04038A/•..
548
COS/MaS
addressing)
Triple serial adder (negative
C04039A/•..
561
COS/MaS
4-word·x-B-bit RAM (word·
C04040A/...
CD4041A/...
CD4042A1••.
CD4043A/ .••
CD4044A1 ..•
CD4045A/..•
CD4046A/•••
C04047A/ •••
566
571
576
580
580
584
12-stage binary counter/divider
Quad true/complement buffer
Quad clocked "0" latch
696
COS/MaS
COS/MaS
COS/MaS
COS/MaS
COS/MaS
COS/MaS
COS/MaS
COS/MaS
CD4048A/ ..•
CD4049A/•••
605
610
COS/MaS
COS/MaS
logic)
line addressing)
amplifier
CA3085/ •••
CA3085A/ ...
CA3085B/•••
CA3094/ •••
Decade counter/divider
589
C04050A/ ••.
610
COS/MaS
C04057A/•••
C04060A/•..
616
624
COS/MaS
COS/MaS
C04061A/ ..•
C04062A1•..
C04063B/ ..•
C04066A/ .••
C04068B/•..
CD4069B/ ...
CD40718/ ...
C040728/ ...
C04073B/ ...
C040758/ •••
C04078B/ ..•
C040818/ ...
C04082B/ ..•
C040858/ ••.
C04086B/ ..•
630
637
665
665
671
665
677
671
671
682
688
COS/MaS
COS/MaS
COS/MaS
COS/MaS
COS/MaS
COS/MOS
COS/MaS
COS/MaS
COS/MaS
COS/MaS
COS/MaS
COS/MaS
COS/MaS
COS/MaS
COS/MaS
C045148/ •••
C04515B/ ...
C045188/ .••
C04520B/ ..•
HC2000H/ ...
694
694
700
700
183
COS/MaS
COS/MaS
COS/MaS
COS/MaS
HYB
644
649
655
660
Quad 3..tate NOR R/S latch
Quad 3..tato NANO R/S latch
21..stage counter
Micropower phase-locked loop
Monostable/estable
multivibrator
Expandable 8--input gate
Hex buffer/converter
(inverting)
Hex buffer/converter
(non-inverting)
LSI 4.tJit arithmetic logic unit
Binary counter/divider and
oscillator
Static random-access memory
Dynamic shift register
Magriitude comparator
Quad bilateral switch
NAND gate
Hex inverter
OR gate
OR gate
AND gate
OR gate
8-input NOR gate
AND gate
AND gate
AND.QR·INVERT gate
Expandable ANO·OR·INVERT
gate
Latch/line decoder
Latch/line decoder
Dual up counter
Dual up counter
Multipurpose 7-A operational
amplifier
UHF n-p-n power transistor
VHF/UHF n·p·n power
transistor
HR2N2857
HR2N3375
85
87
RF
RF
HF2N3553
89
RF
VHF/UHF n-p"" power
HR2N3632
91
RF
VHF/UHF n-p"" power
HR2N3866
HR2N5071
93
95
RF
RF
transistor
N-P#N rf power transistor
VHF n-p-" power
transistor
HR2N5090
97
RF
transistor
VHF/UHF "-p-n power
transistor
7
Index to High-Reliability Solid-State Devices (Cont'd)
Product
Type
HR2N5470
Page
Line
Description
99
RF
UHF/microwave
Type
"-PAn power
Page
Product
Line
JAN2N 1486
30
PWR
JAN2N1487
31
PWR
JAN2N1488
31
PWR
JAN2N1490
31
PWR
JAN2N1493
JAN2N2015
71
31
RF
PWR
transistor
VHF/UHF n-p-n power
transistor
VHF/UHF n-p-n power
transistor
JAN2N2016
31
PWR
JAN2N2857
JAN2N3055
80
32
RF
PWR
RF
transistor
HR2N5916
101
RF
HR2N5918
103
RF
HR2N5919A
105
RF
VHF/UHF n-p-n power
transistor
VHF/UHF n-p-n power
transistor
VHF/UHF n-p-n power
HR2N5920
107
RF
UHF/microwave n-p-n power
HR2N5921
109
RF
UHF/microwave n-p-n power
HR2N6105
111
RF
transistor
transistor
HR2N6265
113
RF
HR2N6266
115
RF
Microwave n-p-n power
JAN2N3375
81
HR2N6267
117
RF
transistor
Microwave n-p-n power
transistor
JAN2N3439
32
PWR
HR2N6268
119
RF
Microwave n-p-n power
JAN2N3440
32
PWR
HR2N6269
121
RF
Microwave n-p-n power
JAN2N3441
33
PWR
HR2N6390
123
RF
Microwave n-p-n power
HR2N6391
125
RF
Microwave n-p-n power
HR2N6392
127
RF
Microwave n-p-n power
transistor
transistor
JAN2N3442
33
PWR
JAN2N3553
81
RF
JAN2N3584
34
PWR
JAN2N3585
34
PWR
transistor
transistor
transistor
HR2N6393
129
RF
Microwave n-p-n power
HR3N187
HR3N200
HR2001
403
409
121
DMDS
DMDS
RF
Dualij8te rf MOS transistor
HR2003
123
RF
HR2005
125
RF
HR2010
127
RF
HE3001
129
RF
HF3003
129
RF
HR3005
129
RF
HR40915
131
RF
HR41039
JAN2N918
133
78
RF
RF
JAN2N1479
30
PWR
JAN2N1480
30
PWR
JAN2N1481
30
PWR
JAN2N1482
30
PWR
JAN2N1483
30
PWR
JAN2N1484
30
PWR
JAN2N1485
30
PWR
transistor
DualiJate rf MOS transistor
Microwave n-p-n power
transistor
Microwave n-p-n power
transistor
Microwave n-p-n power
transistor
Microwave n-p-n power
transistor
Microwave n-p-n power
transistor
Microwave n-p-n power
transistor
Microwave n-p-n power
transistor
Microwave n-p-n power
transistor
VHF n-p-n power transistor
VHF/UHF low-power n-p-n
transistor
Hometaxial-base n-p-n power
transistor
Hometaxial-base n-p-o power
transistor
Hometaxial-base o-p-n power
transistor
Hometaxial-base n-p-n power
transistor
Hometaxial-base n..p-o power
transistor
Hometaxial-base n-p-n power
transistor
Hometaxial-base n-p-n power
transistor
8
JAN2N3771
34
PWR
JAN2N3772
34
PWR
JAN2N3866
82
RF
JAN2N4440
81
RF
JAN2N5038
35
PWR
JAN2N5039
35
PWR
JAN2N5071
JAN2N5109
82
83
RF
RF
JAN2N5415
35
PWR
JAN2N5416
35
PWR
JAN2N5671
34
PWR
JAN2N5672
34
PWR
JAN2N5838
36
PWR
JAN2N5839
36
PWR
JAN2N5840
37
PWR
JAN2N5918
83
RF
JAN2N5919A
84
RF
JAN2N6211
37
PWR
Description
Hometaxial-base n..p-n power
transistor
Hometaxial-base n-p-n power
transistor
Hometaxial-base n-p-o power
transistor
Hometaxial-base n-p-n power
transistor
VHF "-p-n power transistor
Hometaxial-base "-p-" power
transistor
Hometaxial-base n-p-n power
transistor
UHF n-p-n power transistor
Hometaxial-base n-p-n power
transistor
VHF/UHF n-p-" power
transistor
High-voltage n-p-n power
transistor
High-voltage "-p·n power
transistor
~igh-voltage n·p·n power
transistor
High-voltage n-p-n power
transistor
VHF/UHF n-p-n power
transistor
High-voltage n-p-n power
transistor
High-voltage n·p·n power
transistor
High.-current n-p-n power
transistor
High-current n-p-n power
transistor
VHF/UHF n..p-n power
transistor
VHF/UHF n-p-n power
transistor
High-speed n-p-n power
transistor
High-speed n-p-n power
transistor
VHF n..p-n power transistor
VHF/UHF n-p-n power
transistor
High-voltage n..p·n power
transistor
High-voltage n-p-n power
transistor
High-speed n-p-n power
transistor
High-speed n-p-n power
transistor
High-speed n-p-n power
transistor
High-voltage n-p·n power
transistor
High-voltage n..p-n power
transistor
VHF/UHF n-p-n power
transistor
VHF/UHF n-p-n power
transistor
High-voltage p-n-p power
transistor
Index to High-Reliability Solid-State Devices (Cont'd)
Product
Type
Product
Line
Page
Line
Description
Type
JAN2N6212
37
PWR
High-voltage p-n-p power
JANTXV2N3585
34
PWR
JAN2N6213
37
PWR
High-voltage p-n-p power
JANTXV2N4440
81
RF
JANTX2N1479
30
PWR
Hometaxial-base o-p-o
218
218
218
218
219
219
219
219
219
219
219
219
219
220
220
220
221
222
222
222
222
222
222
222
222
222
222
217
217
217
217
217
217
217
224
214
215
SeR
SeR
seR
SeR
SeR
seR
SeR
seR
seR
seR
seR
SeR
seR
SeR
seR
SeR
SeR
SeR
seR
SeR
SeR
SeR
SeR
SeR
SeR
SeR
seR
SeR
SeR
seR
SeR
SeR
SeR
SeR
seR
SeR
seR
204
204
204
204
204
Triac
Triac
Triac
Triac
Triac
205
205
205
205
204
204
204
204
204
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
204
204
204
204
203
206
206
206
206
201
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Page
transistor
transistor
power transistor
JANTX2NI460
30
PWR
Hometaxial-base n-p-n
power transistor
JANTX2N1481
30
PWR
Hometaxial-base o-p-o
JANTX2N1486
30
PWR
JANTX2N2857
JANTX2N3055
80
80
RF
PWR
JANTX2N3375
81
RF
VHF/UHF n-p-n power
JANTX2N3439
32
PWR
High-voltage n-p-n power
JANTX2N3440
32
PWR
transistor
High-voltage n-p-n power
transistor
JANTX2N3441
33
PWR
JANTX2N3442
33
PWR
High-voltage n-p-n power
JANTX2N3553
81
RF
transistor
VHF/UHF n-p-n power
JANTX2N3585
34
PWR
High-voltage n-p-n power
JANTX2N3771
34
PWR
High-current n-p-n power
JANTX2N3772
34
PWR
JANTX2N4440
81
RF
High-current n-p-n power
transistor
VHF/UHF n~p-n power
JANTX2N5038
35
PWR
High~speed
JANTX2N5039
35
PWR
JANTX2N5071
JANTX2N5109
82
83
RF
RF
JANTX2N5415
31
PWR
JANTX2N5416
31
PWR
JANTX2N5671
36
PWR
JANTX2N5672
36
PWR
JANTX2N5840
36
PWR
JANTX2N5919A
84
RF
JANTX2N6211
37
PWR
VHF/UHF n-p-n power
transistor
High-voltage p-n-p power
IANTX2N6212
37
PWR
transistor
High-voltage p-n-p power
power transistor
Hometaxial-base o-p-o power
transistor
UHF n-p-n power transistor
Hometaxial-base o-p-n power
transistor
transistor
High-voltage n-p-n power
transistor
transistor
transistor
transistor
IANTX2N6213
37
PWR
IANTXV2N3375
81
RF
ANTXV2N3553
81
RF
ANTXV2N3584
34
PWR
transistor
n-p-n power
transistor
High-speed n-p-n power
transistor
VHF n-p-n power transistor
VHF/UHF n-p-n power
transistor
High-voltage n-p~n power
transistor
High-voltage p-n-p power
transistor
High~speed n-p-n power
transistor
High-speed n~p-n power
transistor
High-voltage n-p-n power
transistor
transistor
High-voltage p-n-p power
transistor
VHF/UHF n-p-n power
transistor
VHF/UHF n-p-n power
transistor
High-voltage n-p-n power
transistor
S2400A'
S2400B'
S24000'
S2400M'
S2600B'
S26000'
S2600M'
S2610B*
S26100*
S2610M*
S2620B'
S26200*
S2620M*
S3700B*
S37000*
S3700M'
S3701MI
S3704A"
S3704B'
S37040*
S3704M*
S3704S'
S3714A*
S3714B*
S37140*
S3714M*
S3714S*
S8400N*
S8410N*
S6420A*
S8420B'
S64200'
S6420M'
S8420N'
S8431M*
S7430M*
S7432M*
T2300A'
T2300B*
T23000'
T2302A*
T2302B'
T2304B*
T23040'
T2305B*
T23050*
T2310A'
T2310B*
T23100'
T2312A*
T2312B'
T23120*
T2313A'
T2313B*
T23130'
T2313M*
T2700B*
T27000*
T2710B*
T27100*
T4100M'
Description
High-voltage n-p-n power
transistor
VHF/UHF n-p-n power
transistor
4_5-A silicon controlled rectifier
4_5-A silicon controlled rectifier
4.5-A silicon controlled rectifier
4.5-A silicon controlled rectifier
7-A silicon controlled rectifier
7-A silicon controlled rectifier
7-A silicon controlled rectifier
3.3-A silicon controlled rectifier
3.3-A silicon controlled rectifier
3.3-A silicon controlled rectifier
7-A silicon controlled rectifier
7-A silicon controlled rectifier
7-A silicon controlled rectifier
5-A silicon controlled rectifier
5-A silicon controlled rectifier
5-A silicon controlled rectifier
5·A silicon controlled rectifier
5-A silicon controlled rectifier
5-A silicon controlled rectifier
5-A silicon controlled rectifier
5-A silicon controlled rectifier
5-A silicon controlled rectifier
5-A silicon controlled rectifier
5-A silicon controlled rectifier
5-A silicon controlled rectifier
5-A silicon controlled rectifier
5-A silicon controlled rectifier
35-A silicon controlled rectifier
35-A silicon controlled rectifier
35-A silcion controlled rectifier
35-A silicon controlled rectifier
35·A silicon controlled rectifier
35-A silicon controlled rectifier
35-A silicon controlled rectifier
35-A silicon controlled rectifier
35-A silicon controlled rectifier
35-A silicon controlled rectifier
2.5-A silicon triac
2.5-A silicon triac
2.5-A silicon triac
2.5-A silicon triac
2.5-A silicon triac
O.5-A silicon triac
O.5-A silicon triac
0.5-A silicon triac
0.5-A silicon triac
1.6-A silicon triac
1.6-A silicon triac
1.6-A silicon triac
1.9-A silicon triac
l.9-A silicon triac
1.9-A silicon triac
1.9-A silicon triac
1.9·A silicon triac
1.9-A silicon triac
1.9-A silicon triac
6-A silicon triac
6-A silicon triac
3.3·A silicon triac
3.3·A silicon triac
15·A silicon triac
High-reliability versions of these types are available on a custom basis_
9
Index to High-Reliability Solid-State Devices (Cont'd)
Typo
T4101M'
T4103S'
T41030'
T4104S'
T41040'
T4105S'
T41050'
T4110M'
T4111M'
T4113B'
T41130'
T4114S
T41140'
T4115S'
T41150'
T412OS'
T41200'
T412OM'
T4121S'
T41210'
T4121M'
T6401S'
T64010'
T6401M'
T6404S'
T64040'
T6405S'
T64050'
Page
201
207
Product
Line
Triac
Triac
207
Triac
207
Triac
207
207
207
202
202
207
207
207
207
207
207
202
202
202
201
201
201
208
20S
20S
209
209
209
209
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Product
Description
10-A silicon triac
15-A silicon triac
15·A silicon triac
10-A silicon triac
10-A silicon triac
6-A silicon triac
6-A silicon triac
15-A silicon triac
10-A silicon triac
15-A silicon triac
15-A silicon triac
10-A silicon triac
10-A silicon triac
6-A silicon triac
6-A silicon triac
15·A silicon triac
15·A silicon triac
15·A silicon triac
10·A silicon triac
10·A silicon triac
10·A silicon triac
30·A silicon triac
30·A silicon triac
30·A silicon triac
40·A silicon triac
40·A silicon triac
25·A silicon traic
25·A silicon triac
Typo
Pago
Line
Description
T6411S'
T64110'
T6411M'
T6414S'
T64140'
T6415B'
T64150'
T6421S'
T64210'
T6421M'
T8401S'
T84010'
T8401M'
20S
208
208
Triac
Triac
Triac
3O-A silicon triac
3O-A silicon triac
3O-A silicon triac
209
209
209
209
20S
20S
20S
210
210
210
210
210
210
210
210
210
211
211
211
211
211
211
211
211
211
Triac
4O-A silicon triac
Triac
4O-A silicon triac
2!)"A silicon triac
25-A silicon triac
TB411B*
T84110'
T8411M'
T8421B'
T64210'
T6421M'
T8430S'
T84300'
T8430M'
T8440S'
T84400'
T8440M'
T8450S'
T84500'
T8450M'
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
Triac
3O-A silicon triac
30-A silicon triac
30-A silicon triac
GO-A silicon triac
6O-A silicon triac
SO-A silicon triac
SO-A silicon triac
6O·A silicon triac
6O·A silicon triac
6O·A silicon traic
6O·A silicon triac
6O·A silicon triac
aO·A silicon tralc
aO·A silicon traic
8O·A silicon triac
8O·A silicon triac
8O~A silicon triac
SO·A silicon triac
SO·A silicon triac
8O·A silicon triac
8O·A silicon triac
*High·relaibillty versions of these types are available on a custom basis.
Index to Application Notes
Number
Title
Page
AN-6071 .......... Evaluation of Hermeticity of Aluminum TO-3 Packages
Under Thermal-Cycling Conditions (Reliability Report) •.........•...•• 51
AN-6229 .......... Microwave Power-Transistor Reliability as a Function
of Current Density and Junction Temperature .............i .••••••••.179
AN-6249 .......... Real-Time Controls of Silicon Power-Transistor Reliability .............. 53
AN-6320 .......... Radiation Hardness Capability of RCA Silicon Power
Transistors • . . . . . • . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 58
ICAN-6000 ......... Handling Considerations for MOS Integrated Circuits ........•.•.•...• 706
ICAN-6224 ......... Radiation Resistance of COS/MOS CD4000A Series .•....•......•...• 716
RIC-102C ......••.. High-Reliability COS/MOS CD4000A Slash (f) Series
Types Screened to MIL-8TD-883 .......•......................... 714
RIC-104A .......... High-Reliability COS/MOS MIL-M-38510 CD4000A-Series Types ...•...•
RIC-202A .......... High-Reliability CA3000 Slash (I) Series Types Screened
to MIL-STD-883 .•...........•...•••.••..........•...........
RIC-204 .......•.•. High-Reliability MIL-M-38510 CA3000-Series Types .................
1CE-402 ........... Operating Considerations for RCA Solid-State Devices .•.•....•.•.....
10
720
415
421
740
Introduction to High-Reliability Solid-State Devices
The advent of the transistor in 1948 marked a dramatic
step forward in the potential reliability of electronic
equipment. Much of this solid-state reliability potential
has been realized and, without doubt, has played a key
role in the phenomenal growth and diversification of
electronics over the past two decades. In spite of this
achievement, however, the demand and need for greater
reliability assurance in solid-state devices continues to
grow.
Electronic systems continue to grow more complex
as more comprehensive functions are provided. In the
process, greater quantities, or more sophisticated and
complex devices are used. The development cycle for
systems continues to decrease so that less and less time
is available for component reliability testing in operating
systems. Electronics systems are becoming interlocked
with huge dollar investments, with the social and political fabric of society, and with vital national security
to such a degree that a system failure may have
immediate and visible impact. Consumers are demanding better warranties at a time when service costs are
rising rapidly. Further, a dynamic solid-state technology
rapidly generates new devices that offer even greater
functional and reliability pot"ntial.
Solid-state devices classified as high-reliability types
have come to be primarily associated with military and
aerospace applications. In many ways, this association
is misleading because the commercial equipment market
is probably the largest user of high-reliability products,
but not necessarily by that label. Military and aerospace
agencies, however, have been largely responsible for
establishment of comprehensive published reliability
specifications and standards which have been accepted
by the solid-state industry. MIL standards dominate
the procedures used to specify high-reliability solid-state
devices and represent a common reference point frequently used by commercial users to define their requirements.
Commercial High-Reliability Requirements
The dominant market for solid-state devices today
is commercial. The bulk of the parts produced are initially designed, developed, and manufactured to meet
specific functional, quality, and reliability needs of a
class of commercial electronic equipment. Commercial
equipment tends to be evolutionary and to be produced
continuously over longer periods and in larger quantities
than is the case with equipment for mifitary and aerospace systems. At the outset, the commercial user is
more likely, than is the military and aerospace user,
to be involved in influencing the solid-state device manufacturer to his particular functional and economic
requirements. His opportunity to evaluate early devices
and influence corrective measures for his application
is greater. All these factors enhance the ability of both
the solid-state manufacturer and the user to reach a
balance between reliability and economics which matches
a particular need.
One of the most important factors, which brings lower
cost to the commercial user without sacrifice in reliability, is his ability, together with that of the manufacturer,
to identify accurately over a period of time a few relatively simple controls and/or screens which can be used
to effectively eliminate potential failures in his particular
application. This ability is possible because his application is specific and continuous, and device volumes
are considerable. The commercial user generally
achieves the reliability he requires without elaborate
specifications and with a minimum of administrative
procedures.
Military and Aerospace High-Reliability
Requirements
Military and aerospace requirements for highreliability solid-state devices are extremely large and
diverse, not only in terms of performance, operating
conditions, and reliability, but also in terms of logistics
and procurement. As a result of these requirements,
the military services have jointly developed specifications and standards under which most military end-use
solid-state devices are procured. To simplify procurement, logistics, and the development of reliability data,
MIL specs are not issued for the full spectrum of devices
manufactured; rather, they are restricted to those devices
for which significant need is demonstrated and are
specified so that the device can have as wide applicability
as possible. Although the limits for operating conditions
may exceed those required for some applications, they
simplify procurement and assure a supply of devices
for the majority of military equipment. These standards
also cover a wide range of requirements for the manufacturer on such things as:
(a) The procedure and requirements for a manufacturer to become certified to manufacture MIL-spec
parts.
(b) The requirements for qualifying parts.
(c) Product-assurance provisions in· such areas as
quality control, inspection procedures, personnel
training, cleanliness, failure analysis, and documentation.
(d) Test methods and procedures.
(e) Marking and identification of product.
(t) Preservation and packing.
A large number of transistor types are covered by
published military specifications. Specifications for microcircuits (integrated circuits) are relatively new, and
only a limited number of military specifications have
been approved and issued. Many types of devices, both
transistors and integrated circuits, are not covered by
military specifications, either because they are too new
11
or are not used in sufficient quantities. Many of these
devices offer the most recent technological advances
or have special performance characteristics which offer
advantages to the designer of high-reliability equipment.
RCA cooperates with the users of such devices in establishment of high-reliability specifications, patterned
after MIL standards, which allow these devices to be
approved for use in military and aerospace systems,
as well as commercial equipment. If the use warrants,
these specifications may be submitted by RCA, or the
user, to the cognizant military specification agency as
candidates for MIL approval as a standard type.
Most procurements of solid-state devices for military
systems are made by the equipment contractor from
the MlL-STD parts list as awards are received for
electronic equipment. Some military and aerospace
programs, because of their size, duration, or special
requirements (Minuteman and Apollo are two examples), require that special specifications and process
methods, or even special production lines, be established
and tailored to the particular functional, reliability, and
economic needs of the program. RCA Solid State Division has frequently used the resources of its laboratories,
production facilities, and expert technical staff to contribute to the success of such programs.
Military SpeCifications
There are two major military specifications used for
the procurement of standard solid-state devices by the
military. These specifications are MlL-S-19500, which
covers devices such as discrete transistors, thyristors,
and diodes, and MlL-M-38510, which covers microcircuits, both hybrid and monolithic.
MIL-S-19500 is the specification for the familiar
"JAN" transistors. Detailed electrical specifications are
prepared as needed by the three military services and
coordinated by the Defense Electronic Supply Center.
At present, approximately five hundred detailed electrical specifications are included in the MlL-S-19500 system.
Three levels of reliability, JAN, TX, and TXV, are
defined by MlL-S-19500. Devices designated as JAN
types receive lot screening only and are the least expensive. Devices designated as TX receive some lOOper-cent screening (primarily burn-in) and a tight lotsampling plan. Not all detailed specifications include
TX requirements. Devices designated as TXV are tested
the same as TX devices; however, they receive an additional visual inspection prior to sealing the package.
Only a few detailed specifications include TXV testing.
The Defense Electronic Supply Center maintains a
"Qualified Products List" of all vendors qualified to
produce devices in accordance with MlL-S-19500. This
list is published periodically and is available to manufacturers of military equipment. NASA, to date, has not
been a heavy user of MlL-S-19500, preferring instead
to procure devices to their own specifications.
MIL-M-38510 is the relatively new military specification for microcircuits. This specification is far more
12
demanding than MlL-S-195oo and presently only a few
vendors have parts on the Qualified Products List. MlLM-38510 also defines three levels (classes A, B, and
C) of reliability testing. These levels, however, are
markedly different from those defined by MlL-S-19500.
Class A, the highest level, is intended primarily for
flight and other highly critical applications. Class A
devices undergo a lengthy list of 100-per-cent screens,
plus a tight lot-sampling plan. Class B devices are·
intended for general military usage and undergo less
(but still extensive) 100-per-cent testing than Class A
units. Class C devices undergo the least amount of
100-per-cent testing and are, of course, the least expensive.
Approximately 40 detailed specifications are currently
included in the MlL-M-3851O system. A Qualified
Products List for these devices is maintained by the Defense Electronic Supply Center. NASA is now starting to use MlL-M-38510 specifications.
Both MlL-M-3851O and MlL-S-19500 attempt to
make available to the designer of military equipment
a list of standard, qualified, g~neral-purpose parts which
are acceptable to the military. Although MlL-S-19500
and MlL-M-38510 do not cover every solid-state device
available on the market, and do not attempt to do so,
enough devices are available to build the majority of
military equipment. Use of these devices makes the
job of spare-parts inventory far simpler for the military
and the job of specification negotiations far easier for
the equipment manufacturer.
Special Terms and Definitions
Acceptable Quality Level (AQL) is the maximum
percent defective (or the maximum number of defects
per hundred units) that for purposes of sampling inspection, can be considered satisfactory as a process average.
Acceptable Reliability Level (ARL) is a nominal
value expressed in terms of percent failures per 1000
operating hours specified for acceptance of parts or
equipment. It is the level of reliability that will be accepted at some confidence level by a reliability sampling
plan.
Acceptance/Rejection Criteria is the extent 9f defectiveness allowed in a sample of tested product which will
assure the quality level specified.
Assignable Causes of Variation are other-thanchance causes, such as unexpected and abnormal variations in material and machines, lack of skill or carelessness in manual operations, abnormal changes in power
supply, rough handling, etc. These causes normally can
be identified and eliminated economically.
Average is the arithmetic mean of a set of n numbers.
The average is obtained by dividing the sum of the
numbers by n.
Average Outgoing Quality (AOQ) is the average
outgoing quality of product after 100 percent inspection
of rejected lots, with replacement by good units of all
defective units found in inspection.
Average Outgoing Quality Limit (AOQL) (in outgoing product after inspection) is the maximum value of
the AOQ that a sampling plan will assure over a long
period of time, no matter how defective the product may
be when submitted for inspection.
Indifference Quality Level (IQL) is the product
quality which will be accepted as often as it is rejected. It
has a 0.50 probability of acceptance.
Burn-in is a process of "shakedown" operation of
each item of finished product that is performed prior to
placing the item in use.
Catastrophic Failure is a sudden change in the
operating characteristics of the product which would
cause the item to be inoperative (e.g., circuit opens or
shorts, structural failure, etc.).
Chance or Random Failure is a failure that occurs at
random within the operational time of the product after
all efforts have been made to eliminate design and before
wear-out becomes the predominant cause of failure.
Characteristi!= is a trait, property, or feature of a
specified item, type of item, or group of items.
Confidence Level is the degree of desired trust or
assurance in a given result. A confidence level, which
always is associated with some assertion, measures the
probability that a given assertion is true.
Confidence Interval is a range of values that is believed to include, with a preassigned degree of confidence (confidence level), the true value of a characteristic of the lot or universe for a given percentage of the
time. For example, 95% confidence limits for a sample
of 10 with a ratio of successes to total number tested of
0.9 (9 successes and 1 failure) would be 0.54 and 1.0;
that is, even with an observed success ratio of 0.9 (90%),
the best that can be said is that the true ratio lies between
0.54 (54%) and 1.0 (100%) as estimated 95% of the
time.
tion) of the characteristic measured, such as defects per
unit, defectives, percent defective, averages, etc., about
the expected level. Values fluctuating within the control
limits are considered comparable to the expected quality
level. Value falling outside these limits indicate a significant change in the measured characteristic.
Defect is the occurrence, in an individual element or
part, of a characteristic which fails to meet the specified
standard.
Defective is the status of an individual article that
contains one or more defects.
Degradation Failure is a failure that results from a
gradual change in performance characteristics with time
to a value outside the specified limits of the product but
would not cause the item to be inoperative.
Environment is the aggregate of all the conditions
and influences that can affect the operation of the product
(e.g., temperature, humidity, acceleration", shock, vibration, radiation, etc.).
Failure Mechanism is the basic physical or chemical
cause for failure.
Failure Mode is the characteristic which was observed to fail.
Failure Rate is defined as the number of failures
within a time interval. In the case of exponentially distri·
buted times-to-failure, the failure rate is defined as the
reciprocal of mean-time-to-failure (i.e., failure rate
equals lim, where m is the mean time between failures).
Heterogeneity is a state or conditions of dissimilarity
of nature, kind, or degree.
Homogeneity is a state or condition of similarity of
nature, kind, or degree.
Inherent Reliability is maximum reliability attainable with an item of a particular design.
Consumer's (Beta, (3) Risk is the probability that a
sampling plan will accept unsatisfactory material.
Consumer's risk normally is associated with the lot tolerance percent defective (LTPD) having a probability
of acceptance of 0.10.
Inspection (Final) is the application of an inspection
act, just prior to shipment of the product. Shipment in
this case may be to the customer, to a storage area, or to
assembly shops within RCA, where the product in question becomes a component of a larger unit of product.
Control Chart (Quality) is a chart identifying the
expected level of a characteristic and statistical control
limits placed above and/or below this level. Successive
values of some quality measure (e.g., defects-per-unit,
defectives, percent defective, averages, etc.) are plotted
on this chart for judging pattems and significant variations in the characteristic.
Inspection (Process) is the application of an inspec.
tion act at various stages in the manufacturing process
prior to the final stage.
Inspection Act is the determination of conformance
to specified requirements and general standards of acceptable workmanship.
Control Limits (Quality) are the statistical limits
(usually designated in multiples of the standard devia-
Inspection Item is any specific requirement, characteristic, or feature for which inspection is made.
13
Inspection Lot, for purposes ofacceptartce-sampling
inspection, is defined as an aggregation of articles submitted for inspection at one time that has been produced,
as far as practicable, under what are judged to be essentially the same conditions.
Random Selection is the selection of items from a
population in a manner such that each item has an equal
and independent chance of beinl! elected.
Inspection Point is a designaied position within the
manufacturing process at which inspection effort is applied.
Real Time Control is a continuous acceptance and
interpolation of data against established criteria.
Inspection by Attributes is the determination of conformance of a·particular inspection item without reference to degree or magnitude. For example, go/no-go
testing,
Inspection by Variables consists of a determination
of the magnitude of the characteristic covered by the
inspection item and use of approved statistical quality
control techniques to determine conformance to specifications.
Lambda, A (Life Test Failure Rate) is defined as the
lot tolerance percent defective (LTPD) per 1000 hours.
Lot Tolerance Percent Defective (LTPD) is the percent defective of a sampling plan for which the probability of acceptance is low (commonly 10% probability of
acceptance unless otherwise stated).
Mean Time .Between Failures (MTBF) is the average time between failures.
Operating Time is the time during which power is
applied to an item.
Parameter is a quantity or value that remains constant
within a given set of conditions (i .e., is subject to change
only if the conditions change).
Population (Universe) is the total collection of units
from a common source.
Precision is the degree to which repeated observations
of a class of measurements conform to themselves.
Process Average is the average percent defective or
average number of defects per hundred units of product
found during initial inspection. Initial inspection is the
first inspectiori ofproduct.(as distinguished from inspection of product resubmitted after prior rejections) and
includes only first sample results where multiple sampling plans are used.
.
Producer's (Alpha, a) Risk is the probability that a
sampling plan will reject satisfactory material. Producers risk normally is associated with a percent defective
which has a probability of rejection of 0.05.
14
Range is the difference between the greatest and the
least of a set of variate values.
Redundancy.js the existence of more than one means
for accomplishing a given task in which more than one
means must fail before there is an overall failure of th·e
system.
Reliability (Mathematical) is the probability of an
item performing its intended purpose for a specified
period of time under given conditions.
Sample is a group of items chosen by random selection.
·Sampling Inspection is a random and representative
selection of a portion of the units from a lot in accordance
with the specified sampling plan. Each unit in the
selected sample is inspected to determine whether or not
each unit conforms to specification requirements.
Sampling Plan is· an inspection plan that specifies
sample sizes and criteria for accepting or rejecting an
inspection lot based on the results of inspecting the
sample.
Shelf Life is the length of time an item can be stored
under specified conditions and still meet specified requirements with a specified level of assurance.
Specification is a detailed description of the characteristics of a product and of the criteria that must be used
for determining whether the product conforms to the
description.
State of the Art is the level at which technology has
been developed at any period of time.
Stratified Sample is a group of items selected from
sublots so that the number of items included in the
sample from each sublot is proportional to the size of the
sublo!. Random selection of items from within each
sublot is required.
Tolerance is the allowable variation in measurements
within which an item is judged acceptable.
Useful Life is the total operating time between burn-in
and wear-out.
Variables Testing is a test procedure in which the
items under test are classified according to quantitative,
rather than qualitative, measure of characteristics.
High-Reliability
Power Transistors
15
High-Reliability Power Transistors
A number of factors such as second breakdown,
power dissipation, current and voltage ratings, maximum operating areas, temperature, and thermal-fatigue
considerations affect the performance and reliability of
power transistors in various circuit applications. These
factors define the maximum limits of reliable transistor
operation for both steady-state and pulsed conditions.
Each of these factors must be given careful consideration
in the development and production of power transistors
for military, aerospace, and critical industrial applications for which high reliability is a prime objective.
In such applications, replacement of defective parts is
often difficult or impossible or may result in considerable
expense. Care must be taken to assure that field failure
rates are held to an absolute minimum. The following
guidelines should be followed in an effort to achieve
this objective.
Second Breakdown
Second breakdown IS a potentially destructive
phenomenon that can occur in all power transistors
within the maximum current and voltage ratings of the
device. A simplified explanation is that localized ihermal regeneration occurs, and the transistor exhibits· a
lower value of breakdown voltage, referred to as the
"second breakdown". The lower value of voltage
results from thermal generation of charge-carrier pairs
(holes and electrons) at high localized temperatures
which alter the conductivity of the semiconductor in
that vicinity. This localized effect reduces the ability
of the transistor to support the applied voltage. Fig.
2-1 shows qualitatively what happens under primary
or second breakdown.
Electrical Considerations:
Voltage
Breakdowns
Device voltages should be limited to 70
per-cent of the maximum rates values.
Current
Gain
A margin of 15 to 20 per cent above the
required values should be provided to
allow for degradation.
Sufficient Jslb protection must be providSecondBreakdown ed for forward-bias conditions and suffi~i1ergy Tests cient £Sib protection must be provided
for inductive circuits.
Reliability Considerations:
HighSuch tests are required to guarantee highTemperature temperature performance.
Tests
Low-Level
Leakage
Tests
Test for stability.
Delta
Adequate heat sinks must be provided
Temperature so that case temperature is held to a
Tests
minimum.
Operating
Device operating temperatures should be
Temperature limited to 50 to 75 per cent of maximum
rated values.
Transistor
Protection
16
Circuits should include provisions to protect power transistors against electrical
transients.
U
H
!z
~
B
~
8k:::::::::===:::::::=====~~=--COLLECTOR VOLTAGE (VeE)
Fig. 2-1- Primary and secondary breakdown voltages.
Reverse-Bias Second Breakdown-Reversebias second breakdown is a phenomenon that may occur
when the collector current continues to flow under
reverse-bias conditions and causes the injected current
to be concentrated in the central portions of the emitter,
in contrast to the normal edge injection of the current.
If the injected current is severely restricted to a very
small central area by a large reverse emitter-base bias,
the current density can rise to very large levels-in
the order of thousands of amperes per square centimeter.
If the collector of the transistor is of high-resistivity
Silicon, me Dlgn current density may inject a density
of charge carriers that is equal to or greater than the
collector impurity density. In this local region, the base
widens and the collector depletion layer expands until
the injected current density is smaller than the collector
impurity density. If the current density is sufficiently
high, the collector depletion layer expands to a more
heavily doped colleetor region, such as an epitaxial substate. When the collector depletion layer expands,
the collector breakdown voltage is governed by the
impurity gradient related to the base doping and the
heavily doped collector. The collector breakdown voltage normally supports only a fraction of the original
voltage, and the second-breakdown voltage results. The
thermal effects from the large current densities also contribute to the regeneration process. Fig. 2-2 shows the
process of reverse-bias second breakdown.
i
B+
o
PRIMARY
BREAKDOWN
HIGH CURRENT
'N'T'AL COLLECTOR
DOPING LEVEL
DENSITY
2.:
w
\oI:t..,J
~~~
g~8
111=
SECOND BREAKDOWN
REPRESENTATIVE
COLLECTOR SUBSTRATE
_
(LOG SCALE)
Fig. 2-2- Reverse-bias second breakdown.
In an inductive circuit, a situation exists such that
collector current flows in the forward direction while
the transistor is being turned off, and a high voltage
is induced across the device. As a result, the transistor
enters the sustaining region. The hot spot that forms
during reverse-bias second breakdown may then be
generated by current crowding in the depletion region,
as shown in Fig. 2-3.
LEAKAGE
. Fig, 2-4- Examples of (a) unclamped inductive loads
and (b) uncommutated leakage inductance.
COLLECTOR
DOPING IMPURITY
COLLECTOR SUBSTRATE
Ib)
INDUCTANCE
--r
COLLAPSE OF COLlECTORDEPLETION LAYER TO
NONCOMMUTATED
I,)
DO~~o~~V:iE:~DOWN
:
ity, as shown in Fig. 2-5. This figure shows the effect
of variations in the external base-to-emitter resistance
RIlE, the reverse base-to-emitter voltage VBE, and the
load inductance L.
B+
ES/bl~
RBE
.
~
Eslbl
ESlbl
BASE FIELD IN
n~p-n
~
1
E
I
~ (dfU£:~~
/
DEPLETION REGION
Fig. 2-3- Cross section showing current crowding that
occurs during reverse-bias second
breakdown.
The reverse base current that flows laterally through
the base region creates an electric field. For an n-p-n
transistor, electrons flow from the emitter to the collector
across the base region. The field causes these carriers
to flow mainly from the center of the emitter, because
the emitter-base forward bias is greatest at this point.
Because the device is in the sustaining region as a result
of circuit conditions, a depletion region is present. Carriers (electrons) that flow across this region, which
resembles two plates of a capacitor, decrease in potential. Therefore, energy is transformed to heat and causes
a hot spot and possibly reverse-bias second breakdown
(Es/b). Typical examples of this situation are circuits,
such as those shown in Fig. 2-4, in which an unclamped
inductive load or a non-commutated leakage inductance
is present.
Anything that increases the transverse base field aggravates hot-spot formation. Therefore, higher reverse
base currents that result from decreased base-drive resistance or higher reverse voltages diminish Esib capabil-
-----VBE
DIRECTION OF TRANSVERSE
TRANS1STORl=:
'---
I,)
Ibl
Fig. 2-5- (a) Typical inductive-load circuit and (b) variation
of second-breakdown capability as a function of
circuit parameters.
A test set which makes the measurement of reversebias second breakdown possible and aiso protects the
transistor being tested is shown in Fig. 2-6. A test
cycle includes the following steps:
I. The transistor is driven to the desired collectorcurrent level in saturation.
2. The transistor is reverse-biased.
3. The transistor enters the sustaining region,
VCEX(sus).
4. Energy is absorbed by the transistor.
If failure occurs, high-frequency noise is sensed at
the base of the transistor. A "crowbar" (transistor)
in parallel with the transistor being tested is then turned
on, and energy is shunted through this "crowbar" to
protect the transistor undergoing the test. 'Fig. 2-1 shows
the voltage-current relationship during the reverse-bias
second-breakdown (Esib) test.
Forltard-Bias Second Breakdown-Forwardbias second breakdown is somewhat different from
reverse-bias second breakdown. As shown in Fig. 2-8,
the localized heating results because the current density
J crosses the depletion region (collector field) Vc to
yield a power density P. As P increases, more current
17
The forward-bias second-breakdown current, Js/b,
is defined as the current at the onset of second breakdown, and is closely related to the collector field Vc,
the current density J, and other properties of tIle transistor. Forward-bias second breakdown is also related to
charge-carrier transit time across the base region, and
is controlled by base width and any accelerating fields
that exist in the base. The longer the transit time required
for the charge carrier to cross the base, the more lateral
diffusion of the charge and thus the greater the reduction
in the current density at the edge of the collector depletion layer. This diffusion effect, referred to as "fanout," is enhanced by wide base widths and homogeneously doped bases. Because the forward-bias second
breakdown is related to the base width, it is also related
to frequency response. For a given structure, this frequency relationship is expressed by the following empirical equation:
-BE
-veE
REVERSE-8IASSECOND BREAKOO~ IESJbI TEST SET
Fig. 2-6- Reverse-bias second-breakdown (Eslb) test set.
WAVEFORMS DURING SECOND-BREAKDOWN IESJbl TEST
FJg.
.....
P."
2-7- WavefOrms during second-breakdown (Eslb) test.
Pi- - FACTO~~~E
IS/b-
Operation in the forward-bias region subjects the
transistor to simultaneous current and voltage. This condition causes current concentrations as previously discussed. This type of rating must be considered for all
linear applications of transistors ..
The block diagram of a nondestructive secondbreakdown test set is shown in Fig. 2-9: The transistor
under test is in series with a pass transistor and is driven
by a differential amplifier at a current level selected
by the operator. The level selected is independent of
trimsistor current-transfer ratfo. The pass transistor is
operated out of saturation, so' that fast turn-off is possible. A second differential amplifier senses the voltage
across the pass transistor and the I-ohm resistor in series
with it. This voltage is held constant throughout the
test to improve the accuracy of the secondbreakdown voltage reading. The circuii is arranged so
that only the collector current of the transistor under
test passes through the I-ohm resistor. The voltage
across this resistor, therefore, provides an accurate indication of collector current.
WIDTH
DRIfT FIELD
CURRENT DENSITY
VOLTAGE
Fig. 2-8- Forward-bias second breakdown.
"is injected into the localized area. The increase in current
is caused by a decrease in the localized VOE, at an
approximate rate of2 millivolts per·C. The local system
becomes regenerative as more heat from the increased
power density reduces VUE and thereby increases the
current injection.
18
Fig. 2-9- Block diagram of test set 'tor forward-bias secondbreakdown current (lslb).
The onset of second breakdown is detected by use
of the primary of a pulse transformer connected in series
with the collector of the transistor under test. Under
second-breakdown conditions, the rapid rate of rise of
collector current induces a voltage L( di/dt) in the transformer secondary which is coupled to the input circuit
of the series pass transistor. This voltage turns off the
series pass transistor in one microsecond. Simultaneously, a voltage is developed across the transformer
primary of a polarity that immediately reduces the voltage across the transistor under test. The inductance
of the transformer also aids in limiting immediate current
rise in the transistor being tested.
The test-set characteristics, together with the protective cutout circuit, prevent damage to the transistor during the second-breakdown test. The complete cutout
time of the actual test set is approximately one microsecond; this value is sufficient to prevent destruction
of any transistor currently available.
The pulse width of the voltage and current applied
to the transistor under test can be varied from 0.5 millisecond to several seconds. For dc second-breakdown
tests, a pulse width of 0.5 to 2 seconds is required
because the thermal time constant of the power-transistor
pellet and mounting block may be several tenths of
a second.
A comparison of energy-handling capability for
several transistor structures is shown in Table 2-1 .
Table 2-1-Comparlson 01 Energy-Handling Capability
Ie
x VCEO
(I-Second pulse)
2N5240
2N5840
2N5038
2N5672
2N6032
2N3879
Forward Bias
Energy Handling Reverse-Bias
at VCEO Limit Energy ES/b
mJ
J
Doped
0.08 x 300
0.02 x 350
Double-diffused. double-epitaxial
0.25 x 90
22.5
0.12 x 120
14.4
0.05 x 120
6
0.09 x 75
6.85
VOL lAGE OPERATION
1.6
0.45
Vee
SUSTAINING
REGION
~
R
:
~
--.J
RELAY
-=-
TYPICAL
LVCEQ (sus)
TEST
SET
COLLECTOR-TO -EMITTER
VOLTAGE (VeE)
Fig. 2-10-lnductive voltage-breakdown testing of a
transistor: (a) load line; (b) test circuit.
high-current, high-voltage measuring point is
approached 'from the other direction with the collector
current Ie lagging the collector' to-emitter voltage VeE,
as shown in Fig. 2-11. Unless sufficient current is
supplied to the place the transistor in the sustaining
region, the breakdown voltage measured is artificially
high. If this high current is passed through a transistor
with a high breakdown voltage, a high dissipation
results. This dissipation is not uniformly distributed over
the whole junction, but tends to concentrate in the spots
with the lowest breakdown. This concentration is further
aggravated when the base-to-emitter junction is reversebiased. The small areas that break down first form hot
spots. These hot spots result in further current concentration with time, and possible device destruction. Fig.
2-12 shows the test circuit used in the curve-tracer test.
~
~
z
~
a
~
is
-l£V
24
7.0
HIGH-CURRENT LOW-
TEST POINT
S~fJ~~ING
U
ARTIFICIALLY HIGH
...J
AT lS)W CURRENTS
VOLTAGE READINGS
: : b=======~1
COLLECTOR-TO- EMlnER VOLTAGE (VeE)
13
20
40
1.0
Fig. 2-11-Load line for curve-tracer voltage-breakdown
testing.
Hometaxial- Base
2N5578
2N3055
2N3773
1.5 x 70
1.9 x 60
0.6 x 140
105
115
84
800
170
310
Inductive Voltage-Breakdown Testing
In most practical applications of transistors, the highest voltage that appears across the transistor results from
the turn-off of the transistor, because the transistor
switches from a high-current "on" state to a "cut-off"
state. Inductive testing simulates this condition very
closely, as shown in Fig. 2-10. Curve-tracer testing,
on the other hand, subjects the transistor to an increasing
voltage until the required current is achieved; i.e., the
Fig. 2-12- Test setup for curve-tracer voltage-breakdown
testing.
The 8-mlllisecond sweep of a curve tracer is relatively
slow compared to inductive sweeping. This sweep
allows time for the current to concentrate and to deliver
an,appreciable and variable amount of energy. Inductive
testing, on the other hand, delivers a relatively fixed
amount of energy in a short time (0.6 millisecond maximum for the 2N4348 transistor). Less concentration
of current is allowed, and the test is potentially less
destructive and provides a more realistic rating. Curve19
tracer testing may reject transistors that will operate
satisfactorily in any practical application because the
opportunity for the occurrence of hot spots is increased,
and lower values of VeEO are measured.
Effect of Temperature on Silicon Transistors
The characteristics of transistors vary with changes
in temperature. In view of the fact that most circuits
operate over a wide range of environments, a good
circuit design should compensate for such changes so
that operation is not adversely affected by the temperature dependence of the transistors.
Current Gain-The effect of temperature on the gain
of a silicon transistor is dependent upon the level of
the collector current, as shown in Fig. 2-13. At the lower
current levels, the current-gain parameter WE increases
with temperature. At higher currents, however, WE
may increase or decrease with a rise in temperature
because it is a complex function of many components.
z
;g
...z
w
'"'"u
Fig. 2-14- Collector current as a function of base-to-emitter
voltage at different temperatures.
amount by wnich the natural gain of the device (WE)
exceeds the gain with which the circuit drives the device
into saturation. This latter gain is known as the forced
gain (WEf).
At lower collector currents, the natural WE of a
transistor increases with temperature, and the lIt drop
in the transistor is small. The collector-to-emitter saturation voltage, therefore, diminishes with increasing temperature if the circuit continues to maintain the same
forced gain. At higher collector currents, however, the
IR drop increases, and gain may decrease. This decrease
in gain causes the collector-to-emitter saturation voltage
to increase and possibly to exceed the room-temperature
(25°C) value. Fig. 2-15 shows the effect ofiemperaiure
on the collector-to-emitter saturation voltage .
~
~--------------
COLLECTOR CURRENT tIcl
·Flg. 2-13- Current gain as a function of collector current
at different temperatures.
Base-to-Emitter Voltage-Fig. 2-14 shows the
effect of changes in temperature on the base-to-emitter
voltage (VSE) of silicon transistors. Two factors, the
-base resistance (lbb') and the height of the potential
barrier at the base-emitter junction (VBE'), influence
and behavior ofthe base-to-emitter voltage. As the temperature rises, material resistivity increases; as a result,
the value of the. base resistance Thb' becomes greater.
The barrier potential VBE' of the base-emitter junction,
however, decreases with temperature. The following
equation shows the relationship between the baseto-emitter voltage and the two temperature-dependent
factors:
COLLECTOR CURRENT (Ie)
Fig. 2-15- Collector current as a function of collector-toemitter saturation voltage at different temperatures.
Collector Leakall.e Currents-Reverse collector
current is a resultant of three components, as shown
by the following equation:
IR=ID+IG+IS
Fig. 2-16 shows the variations of these components
with temperature.
As indicated by this equation, the base-to-emitter voltage diminishes with a rise in temoerature for low values
of collector current, but tends to increase with a rise
in temperature for higher values of collector current.
Collector-to-Emitter Saturation Voltage-The
collecior-to-emitter saturation voltage VCE(sat) is
affected primarily by collector resistivity (Pc) and the
20
Fig. 2-16- Reverse collector current as a function of
temperature.
The diffusion or saturation current In is a result of
carriers that diffuse to the collector·base junction and
are accelerated across the depletion region. This compo·
nent is small until temperatures near 175°C are reached.
The component IG results from charge. generated car·
riers that are created by the flow of diffusion carriers
across the depletion region. This component increases
rapidly with temperature. In and IG are referred to
as bulk leakages. The term Is represents surface leakage
which is caused by local inversion, channeling, ions,
and moisture. This leakage component is dependent
on many factors, and its variations with changes in
temperature are difficult to predict.
At low temperatures, either surface or bulk leakage
can be the dominant leakage factor, particularly in tran·
sistors that employ a mesa structure. At high tempera·
tures, charge·generated carriers and diffusion current
are the major causes of leakage in both mesa and planar
transistor structures; the current Ia, therefore, is the
dominant leakage component. Because ofthe dominance
of surface leakage Is at low temperatures and the fact
that this leakage may vary either directly or inversely
with temperature, it is not possible to define a constant
ratio of the leakage current at low temperatures to that
at high temperatures. In view of the fact that power
transistors are norinally operated at high junction tem·
peratures, it is more meaningful to compare the leakage
characteristics of both mesa and planar transistors at
high temperatures. The relative reliability of different
types of power transistors, which is in no way related
to the magnitude of low·temperature leakage current,
is also best compared at high temperatures.
Pulsed Safe-Area
Sy~tems
On the basis of the heat storage in the thermal rriass
of the silicon chip and its mounting system, the peak
power· handling capability of transistors increases with
decreases in pulse duration. Fig. 2·17 shows normalized
thermal resistance NR as a function of time for a specific
transistor and indicates that power substantially higher
than rated steady· state values may be applied for short
periods of time without exceeding the maximum rated
junction temperature. These values of increased power
correspond to (I/NR) pede), where I!NR is the nor·
malized power multiplier and P(d,) is the steady· state
power rating at the case temperature of interest.
....
PM·ao
P.52
~a:
fi3 ~
Pdiss= [TJ(max)· TCl/OJ.C4-+-1
~ ~ 0.4+-+:::1==1--+++-1
I~ Q~
V
0
0
"f::;:.
DIS~
~"IQ
j"~
IO'~·~,I~~~4~IO~·'~IO~·'~IO~·'~I~I~O~'OO
TIME-SECONDS
NORMALIZED THERMAL RESISTANCE
Fig. 2·17-Normalized thermal resistance.
l=S/b LlMITEO
50
100
150
200
CASE TEMPERATURE-DC
Fig. 2·19- Derating curve for case temperatures above 25°C.
21
oscilloscope traces, an alternative approach· may be
used. The marked load line is sketched on the derated
curves. If the transistor is being operated in the safe
area, the trace time of the portion of the load line that
extends outside a given pulsed safe area should not
be greater than the specified pulsed width for that safe
area. For example, the load line should not spend more
than I millisecond outside the I-millisecond safe area.
For pulsed operation, the derating factor shown in
Fig. 2-19 must be applieil to the appropriate curve (m
the safe-area rating chart. For the derating, the effective
case temperature Tc(eft) may be approximaied by the
average junction temperature Ti(av). The average junction temperature is determined as follows:
Tj(av) = TC + PAV (e J-C)
This approach results in a conservative rating for the
pulsed capability of the transistor. A more accurate
determination can be made by computation of actual
instanianeous junction temperatures.
Depending upon whether time markers can be placed
along the load line, two methods are available to determine whether a transistor will be operated within its
safe-area limits in a given circuit.
I. Without Time Markers: The energy of the load
line is concentrated at a single point (II\', Vw) at which
the greatest load-line penetration outside the safe area
occurs. Multiplication of the waveforms of collector
current Ie and the collector-to-emitter voltage Vel'
yields a waveform of instantaneous power as a function
of time. Integration of one cycle of this instantaneouspower waveform results in an energy E. The width
(Ip) of an equivalent pulse may be determined as follows:
Thermal Fatigue
Significant temperature vanal10ns occur in power
transistors because of changes in ambient temperature
and in the power dissipation during operation. These
variations in temperature result in cyclic mechanical
stresses at the interface of the semiconductor pellet and
the metal header to which the pellet is bonded because
of the difference in the thermal expansions of these
parts. These stresses are a function of the difference
in the coefficients of thermal expansion of the semiconductor and metallic materials, of the change in temperature at ,the interface, and of the dimensions of the interface.
Power transistors are subjected to thermal-cycling
stresses in all practical applications. Table 2-2 lists
examples of the thermal cycling that a power transistor
may be required to withstand in several typical applications. These data show that the thermal-cycling requirements may be very severe even in some of the more
common types of applications. The cyclic stresses produced by the continuous thermal cycling may result
in dislocation "pile-ups" at points of discontinuity such
as may be produced by voids and impurities. Such dislocations cause localized hardening and cracks that may
eventually lead to transistorfailures. This type offailure
The voltage VI\', the current Iw, and the pulse width
Ip are compared to the corresponding values of the pulsed
safe area on the derated curves.
2. With Time Markers: If time-marked load lines
are available, either through the use of dual-trace
waveforms of collector-to-emitter voltage and collector
current as a function of time or Z-axis modulation of
Table 2-2 - Thermal-Cycling Requirements, for Typical Applications of Power Transistors.
PT
toTC
(WI
(OCI
Life Required
(yearsl
Typical Thermal·
Cycling Rating
Required
(cyclesl
8
2
75
45
5
5
5,000
5,000
lator
Switching
regulator
50
65
5
5,000
15
65
5
5,000
Hi·Fi audio
amplifier
Class AB
35
50
5
5,000
Computer power
supply
Series
regulator
50
65
10
10,000
Computer peripheral equip.
Solenoid
driver
5
5
10
1.3 x 108
Television
Vertical
output
Audio output
10
8
75
75
5
5
5,000
5,000
Unear
amplifier
100
55
10
144 x 103
Application
Auto radio
audio output
Power supply
Sonar
modulator
22
Circuit
Class A
Class AB
Minimum Equipment
Series regu-
may be considered simply as fatigue wearout that results
from continuous flexing of materials during thermal cycling.
Effect of Assembly Methods and Package
Material on Thermal-Cycling Capability-The
thermal-cycling stresses set up at the interface of two
dissimilar materials because of the difference. in the
coefficients of thermal expansion of the materials can
be reduced by insertion of a material that has an intermediate expansion coefficient between them. Fig. 220(a) illustrates the use of a molybdenum slab as an
expansion matcher in a silicon power transistor to reduce
the cyclic thermal stresses between the silicon pellet
and the copper header. Use of this technique can result
in significant improvement in the thermal-cycling capability of power transistors.
the lead solder. Use of this proprietary "controlled solder process" (CSP) makes it possible to avoid microcracks that propagate to cause fatigue failures in power
transistors and, therefore, greatly increases the thermalcycling capability of these devices.
Thermal-Cycling Rating Chart-An equipment
manufacturer should make certain that power-transistor
circuits are designed so that cyclic thermal stresses are
mild enough to assure that no transistor fatigue failures
occur during the required operating life of this equipment. Experimental results indicate that the thermalcycling capability of a power transistor can be predicted
by use of the following mechanical-activation energy
equation:
N= AeY.. /IlT
where N is the number of cycles to failure, A is a
system constant, y.J>. is a constant proportional to the
mechanical-activation energy required to produce a
failure, and LlT is proportional to the energy supplied
as a result of the change in temperature at the mounting
interface.
THERMAL COEFFICIENT
The above equation, together with empirical data,
OF EXPANSION
MATERIAL
X 10-' PER ·C
forms the basis for a new thermal-cycling rating system
SiLiCoN
4.2
developed by RCA. This rating system, which is the
MOLYBDENLIM
4.9
COPPER
17.0
first of this type in the industry, shows the relationship
STEEL
11.0
(o(
?etween total transistor power dissipation, the change
In case temperature, and the number of thermal cycles
SILICON DIE
that the transistor is rated to withstand.
Fig. 2-21 shows a typical thermal-cycling rating chart.
Thi~ chart is provided in the form of a log-log presentation in which total transistor power dissipation is denoted
by the ordinate and the thermal-cycling capability
(OJ
(number of cycles to failure) is indicated by the abscissa.
Fig. 2-20- Cross section of a transistor that uses a molyb- Rating curves are shown for various magnitudes of
denum expansion matcher between pellet and change in case temperature. Use of this chart makes
header; (b) cross section of a transistor in which it possible for a circuit designer to avoid transistor
thermal-fatigue failures during the operating life of this
pellet is soldered directly to copper.
Use of silicon-gold eutectic bonding to attach the equipment. In general, power dissipation is a fixed syssemiconductor pellet to the header results in a pellet- tem requirement. The designer also knows the number
to-header joint that can withstand a very large number of thermal cycles that a power transistor will be sub.iected
of number of thermal cycles. When this type of hard100a
solder bonding is used, however, the stress generated
0
because of a thermal mismatch is transmitted to the
,
pellet, which in most power transistors is made of sili~
1...
con. Because silicon is relatively weak in tensile strength
0.
and is highly "notched sensitive," the cyclic thermal
'f-z
stresses may result in the propagation of cracks in the
0
~ 10 fsilicon pellet unless either the pellet is very small or
~ a fan expansion matcher is used.
of;;
In most silicon power transistors, lead solder is used
'fto bond the pellet to the header. The cyclic thermal
~
"'
il
stresses produced at the mounting interface are then
,
absorbed by non-elastic deformation of the soft solder
material, and very little stress is transmitted to the pellet.
I
The continuous flexing of the solder, however, may
, 4 68105 2 4 6 8106 2 4 6 a107 2 4 6 a108
10'
eventually lead to fatigue failure in this material. Any
NuMBER OF THERMAL CYCLES
92CS'22828
impurities in the solder results in dislocation pile-ups
that accelerate the failure. RCA has developed a process Fig. 2-21-Thermal-cycling rating chart for an RCA hermetic
that significantly reduces the impurities introduced into power transistor.
MOLYBDENUM
~
23
to during the minimum required life of the equipment.
For these conditions, the chart indicates the maximum
allowable change in case temperature. (If the rating
point does not lie exactly on one of the rating curves,
the allowable change in case temperature can be approximated by linear interpolation.) The designer can then
determine the minimum size of heat sink required to
restrict the change in case temperature within this maximum value.
Thermal-cycling ratings are included in the technical
data for all RCA silicon power transistor announced
since January I, 1971. Similar ratings are being added
for earlier power transistors as sufficient date are accumulated.
RCA experience in determining thermal-cycling rating has shown that package material is also a very important consideration in relation to thermal fatigue. Comparison data on the RCA steel packages and aluminum
packages are given in the RCA Reliability Report,
"Evaluation of Aluminum TO-3 Packages Under
Thermal-Cycling Conditions" (AN-6071), shown later
in the section Applicatioll Notes all Power Transistors.
These data show that the thermal-cycling capability of
RCA's steel package with its glass-to-stem seal, welded
cap, and controlled solder process is far superior (more
than an order of magnitude better) to that of a similar type
aluminum package and hard-solder mounting system.
Thermal-Fatigue Testing-The RCA thermalcycling ratings allow a circuit designer to use power
transistors with assurance that fatigue failures of these
devices will not occur during the minimum required life
of his equipment. These ratings provide valid indications
of the thermal-cycling capability of power transistors for
all types of operating condi tions. On the basis of these
ratings, limiting conditions can be established during
circuit design so that the possibility of transistor
thermal-fatigue failures are avoided.
Obviously, all individual power transistors cannot be
tested to determine their thermal-cycling capability because such tests are expensive, time consuming, and
destructive. The validity of the RCA thermal-cycling
ratings results from the application of stringent process
controls at each step in the manufacture of power transistors and from the testing of a statistically significant
nUl!lber of samples. Thermal-cycling ratings for power
transistors provide the same type of assurance that a
device will not fail when operated within ratings as that
provided by the more familiar voltage, current, and
second-breakdown ratings.
During thermal-fatigue testing of power transistors,
the operating power for the device is usually equivalent
to that expected to be applied during normal operation.
The transistor is operated until the rise in case temperature is equal to the maximum value anticipated in the
intended application. The case temperature is then reduced to the initial value by use of forced-air or water
cooling. The cycle is repeated until failure occurs, as
indicated by a significant increase in the transistor thermal resistance. The transistor heat sink and the timing of
the temperature-cycling are selected to simulate as
closely as possible the actual conditions that the transistor
will be subjected to in the actual application. Table 2-3
shows the results of thermal-fatigue tests on several
RCA transistors.
Effect of Radiation on RCA Power Transistors
There has been an increasing requirement for modern
military systems to be "radiation hard", i.e., resistantto
the effects of nuclear radiation. The electronic equipment in these systems must be carefully designed to
achieve the required hardness. Solid-state devices have
been the subject of particularly close attention.
Nuclear radiation has two major effects on power
transistors. First, photocurrents generated by highintensity irradiation can cause transistor saturation and
possible circuit malfunction during the exposure. Second, prolonged exposure to bombardment by heavy particles such as neutrons can cause permanent changes in
the transistor characteristics. These changes, which are
caused by displacement damage to the semiconductor
crystal, are primarily manifested as a decrease in transistor gain and an increase in .aturation voltages. Table 2-4
summarizes the basic considerations relative to both
displacement damage and photocurrents.
Power transistors must be opti mally designed to
minimize these radiation effects and maintain the required power-handling capability. The key design
parameters are a thin low resistivity, low volume base,
and a collector as thin and as low in resistivity as possible
consistent with voltage breakdown requirements. Trans-
Table 2-3 - Thermal-Fatigue Performance of some Typical RCA Power Transistors
TVpe
Pellet Size
Mils x Mils
2N3773*
2N3773
2N3772
2N3055
2N3055
2N6032
2N5298
2N5240
2N5039
250
250
250
180
180
230
250
250
250
180
180
230
130
130
145
130
130
183
Early c..;sigll.
24
Mounting
Material
Le,d
Le,d
Lead
Lead
Lead
Silicun
Gold
Lead
Le,d
Le,d
**
Case Temp.
Power
Dissipation
No. of
Cycles
to 10% Failure
Change in
Material to
which Die is
CSP
aC
Watts
Copper
Molybdcum
No
No
Yes
No
Yes
No
42
42
90
65
90
53
85
85
16
50
6.7
105
Copper
Copper
Copper
No
Yes
Yes
50
42
73
18
51
59
Attached
Copper
Mnlybdcum
Cupper
Copper
Test still operating.
1.000
9.600
34.500"
3.500
40,000"'**
12.793***
10.000
8,500***
10,000***
*** Test terminated-fess than ICYA. failure.
Table 2-4 - Effect 01 Nuclear Radlallon on Power Transistors
Displacement Damage
Cause
Result
Radiation
Parameter
Heavy particles, such as neutrons,
bombarding the transistor and creating
defects in the semiconductor material.
Decreases lifetime in the base and increases collector resistivity.
Semipermanent gain degradation and
Increase in VCE("lj, leakage, and
VCE. These changes are referred
to as semipermanent because annealing at several hundred degrees centigrade for a few hours recovers most of
the degradation.
Particles per square centimeter,
called fluence, designated by the
symbol 1 2 2 J J .2
) 6J 7•8 516O
7
~
I
2
2
]
12233,
]
"
56
5
Usc first IlllIptinB plan bela_ arm_. If umplt' SLlI' equals, or
=-
Ust. fin-I nmpling pl.n .bove
• Derived from Table II-A of MIL-STD-l0SD
7
8
to
II
14
"'1",0,
,'5'
IT'"0_"_'
v"" [
l'i 21 'l2
7810"14"21221]
".
.fn)W
6
elc~ds.
10\ or bitch SlU', do 100
IM'rc~n!
InspectIon
Ac
=
Acc~pt.nc~
Re
:::0
R~iection
nllmber,
I". mber.
29
Hometaxial-Base
Silicon N-P-N Power Transistors
JAN2N1.479JAN2N1482
JAN Electrical Specification: MI L·S·19500/207
Structure: Hometaxial·base
Applications: Power·switching. amplifiers
System Usage: Military
Package: JEDEC TO·5
Maximum Aatings: PT = 1 W; VCEO = 40 V (2N1479. 2N1481)
= 55 V (2N1480. 2N1482)
ELECTRICAL CHARACTERISTICS. At Case Temperature (TC) = 2SOC Unless Otherwise Specified
CHARACTERISTIC
Gain·Bandwidth Product
DC Forward·Current Transfer Ratio
SYMBOL
IT
hFE
TEST CONDITIONS
IC = 5 rnA. VCE = 28 V
MIN.
LIMITS
MAX.
-
600
35
100
20
60
IC=200mA.VCE=4V
UNITS
kHz
2N1489
2N1490
2N1479
2N1480
Saturated Switching Time:
Turn-on
tON
IC = 200 mA
-
25
/lS
Turn·off
tOFF
IC = 200 mA
-
25
/lS
For characteristics curves and test conditions. refer to published data for basic type in File No. 135.
Hometaxial-Base
JAN2N1483- JAN2N1486
JANTX2N1.483-JANTX2N1486 Silicon N-P-N Power Transistors
JAN Electrical Specification: MIL-5·19500/180
Structure: Hometaxial·base
Applications: Power-switching. amplifiers
System Usage: Military
Package: JEDEC TO·8
Maximum Ratings: PT = 1.75 W; VCEO = 40 V (2N1483. 2N1485)
= 55 V (2N1484. 2N1486)
ELECTRICAL CHARACTERISTICS. At Case Temperature (TCi = 2SOC Unless Otherwise Specified
CHARACTERISTIC
Gain·Bandwidth Product
DC Forward·Current Transfer Ratio
Saturated Switching Time:
Turn·on
Turn·off
SYMBOL
fT
hFE
TEST CONDITIONS
IC = 5 mAo VCE = 28 V
600
LIMITS
MAX.
-
tON
IC = 750 mA
tOFF
IC = 750 mA
UNITS
kHz
2N1485
2N14B6
2N1483
2N1484
35
100 .
20
60
-
25
/lS
25
/lS
IC = 750 mAo VCE = 4 V
For characteristics curves and test conditions, refer to published data for basic type in File No. 137.
30
MIN.
JAN2N1487-JAN2N1490
Hometaxial-Base
Silicon N-P-N Power Transistors
JAN Electrical Specification: MIL-8-19500/208
Structure: Hometaxial-base
Applications: Power-switching. amplifiers
System Usage: Military
Package: JEDEC TO-3
Maximum Ratings: PT = 75 W; VCEO = 40 V (2Nl487, 2N1489)
= 55 V (2Nl488, 2N1490)
ELECTRICAL CHARACTERISTICS, At Case Temperature (TC) = 25"C Unless Otherwise Specified
CHARACTERISTIC
Gain-Bandwidth Product
SYMBOL
fT
DC Forward-Current Transfer Ratio
Saturated Switching Time:
Turn-on
Turn-off
hFE
tON
tOFF
TEST CONDITIONS
MIN_
IC= 100 mA, VCE = 12 V
LIMITS
MAX_
25
75
15
45
-
25
25
IC = 1.5 A, VCE = 4 V
IC= 1.5A
IC-l.5A
UNITS
-
500
-
kHz
2N1489
2N1490
2N1487
2N1488
/-IS
/-Is
For characteristics curves and test conditions, refer to published data for basic type in Fila No. 139.
Hometaxial-Base
Silicon N-P-N Power Transistors
JAN2N2015
JAN2N2016
JAN Electrical Specification: MI L-S-19500/248
Structuer: Hometaxial-base
Applications: Power-switching, amplifiers
System Usage: Military
Package: JEDEC TOol6
Maximum Ratings: PT =150 W; VCEO =50 V (2N2015)
= 65 V (2N2016)
ELECTRICAL CHARACTERISTICS, At Case Temperature (TC) = 25"C Unless Otherwise Specified
CHARACTERISTIC
Gain-Bandwidth Product
DC Forward-Current Transfer Ratio
SYMBOL
fT
hFE
Collector-to-Emitter Saturation Voltage VCE(sat)
TEST CONDITIONS
LIMITS
UNITS
MIN.
MAX.
IC = 5 A, VCE = 4 V
800
-
kHz
= 5 A, VCE = 4 V
15
50
1.25
V
IC
IC = 5 A, IB = 0.5 A
-
For characteristics curves and test conditions, refer to published data for basiC type In Fde No. 12.
31
Hometaxial-Base
Silicon N-P-N Power Transistors
JAN2N3055
JANTX2N3055
JAN Electrical Specification: MIL-S·19500/407
Structure: Hometaxial·base
Applications: Power·switching, amplifiers
System Usage: Military
Package: JEDEC TO-3
Maximum Ratings: PT = 117 W; VCEO = 70 V
ELECTRICAL CHARACTERISTICS, At Case Temperature (TC) = 25"C Unless Otherwise Specified
CHARACTERISTIC
SYMBOL
Gain·Bandwidth Product
fT
DC Forward·Current Transfer Ratio
hFE
Coliector·to·Emitter Saturation Voltage VCE(sat)
Second·Breakdown Collector Current:
With base forward·biased
Isib
Saturated Switching Time:
Turn·on
tON
Turn·off
toFF
Thermal·Cycling Rating
. .
TEST CONDITIONS
LIMITS
MIN.
MAX.
IC = 1 A, VCE = 4 V
SOO
IC = 4 A, VCE = 4 V
20
-
UNITS
kHz
IC - 4A,IB = 0.4 A
-
0.75
V
VCE = 70 V, t = 1 s
1.67
-
A
IC=4A
IC=4A
-
PT = 20W,flTC= 50°C
3x 105
6
12
-
-
..
jJS
I.IS
Thermal
Cycles
For characteristiCS curves and test conditIOns, refer to published data for basic type in File No. 524 .
JAN2N3439 , JAN2N3440
High-Voltage
.
JANTX2N3439, JANTX2N3440 Silicon N-P-N Power Transistors
JAN Electrical Specification: MI L-S·19500/368
Structure: Double-diffused epitaxial
Applications: High-voltage amplifiers, inverters, regulators
System Usage: Military
Package: JEDEC TO·39 (2N3439S) or JEDEC TO·5 (2N3439L)
Maximum Ratings: PT =0.8 W; VCEO =350 V (2N3439)
= 250 V (2N3440)
ELECTRICAL CHARACTERISTICS, At Case Temperature (TC) = 25"C Unless Otherwise Specified
CHARACTERISTIC
Gain·Bandwidth Product
DC Forward·Current Transfer Ratio
Coliector·to·Emitter Saturation Voltage
Second·Breakdown Collector Current:
With base forward·biased
Saturated Switching Time:
Turn·on
Turn·off
. .
SYMBOL
fT
TEST CONDITIONS
hFE
VCE(sat)
Ic=10mA,VCE=10V
Ic-20mA,VCE-l0V
Ic-50mA,IB-4mA
-
ISlb
VCE=200V,t=ls
50
toN
tOFF
IC = 20 mA
Ic=20mA
-
For characteristiCS curves and test conditions, refer to published data for basic type in File No. 64.
32
LIMITS
MIN.
15
40
-
MAX.
160
0.5
1
10
UNiTs
MHz
V
mA
/.IS
/.IS
High-Voltage
Silicon N-P-N Power Transistors
JAN2N3441
JANTX2N3441
JAN Electrical Specification: MIL-S-19S00/369
Structure: Hometaxial-base
Applications: High-voltage power switching, amplifiers
System Usage: Military
Package: JEDEC TO-66
Maximum Ratings: PT = 25 W; VCEO = 140 V
ELECTRICAL CHARACTERISTICS, At Case Temperature (TC) = 25"C Unless Otherwise Specified
CHARACTERISTIC
SYMBOL
Gain-Bandwidth Product
fT
DC Forward-Current Transfer Ratio
hFE
Collector-to-Emitter Saturation Voltage VCE(sat)
TEST CONDITIONS
LIMITS
MIN_
MAX_
IC = 0.5 A, VCE = 4 V
400
-
IC = 0.5 A, VCE = 4 V
25
100
IC - 0.5 A, IB = O.OSA
-
UNITS
kHz
1
V
Second-Breakdown Collector Current:
With base forward-biased
IS/b
VCE = 30 V, t = 1 s
833
-
mA
Saturated Switching Time:
Turn-on
Turn-off
tON
tOFF
IC=O.SA
IC-O.SA
-
8
15
PT = 4 W,~TC = SO"C
Sx 105
I1S
I1S
Thermal
Cycles
Thermal-Cycling Rating
-
-
For characteristics curves and test conditions, refer to published data for basic type in File No. 529.
High-Voltage
Silicon N-P-N Power Transistors
JAN2N3442
JAN Electrical Specification: MIL-S-19S00/370
Structure: Hometaxial-base
Applications: High-voltage power switching, amplifiers
System Usage: Military
Package: JEDEC TO-3
Maximum Ratings: PT = 117 W; VCEO = 140 V
ELECTRICAL CHARACTERISTICS, At Case Temperature (TC) = 25"C Unless Otherwise Specified
CHARACTERISTIC
SYMBOL
Gain-Bandwidth Product
fT
DC Forward-Current Transfer Ratio
hFE
Collector-to-Emitter Saturation Voltage VCE(sat)
Second-Breakdown Collector Current:
With base forward-biased
ISlb
Thermal-Cycling Rating
.
.
..
TEST CONDITIONS
LIMITS
MIN.
MAX.
-
IC = 3 A, VCE = 4 V
100
IC = 3 A, VCE = 4 V
20
IC - 3 A, 18 = 0.3 A
-
VCE;;'8 V, t = 1 s
PT=20W,~TC=SO°C
1.5
3xl0S
UNITS
kHz
70
1
-
V
A
Thermal
Cycles
For characteristics curves and test conditions, refer to published data for baSIC type 10 File No. 528 .
33
JAN2N3584, JAN2N3585
JANTX2N3584, ,JANTX2N3585
JANTXV2N3584, JANTXV2N3585
JAN Electrical Specification: MIL-8-19500/384
Structure: Double-diffused epitaxial collector
Applications: High-voltage amplifiers, inverters, regulators
System Usage: Military
High-Voltage
Silicon N-P-N
Power Transistors
Package: JEDEC TO-66
Maximum Ratings: PT = 35 W; VCEO = 250 V (2N3584)
= 300 V (2N3585)
ELECTRICAL CHARACTERISTICS, At Case Temperature (TCI = 25"C Unless Otherwise Specified
CHARACTERISTIC
Gain-Bandwidth Product
SYMBOL
fT
DC Forward-Current Transfer Ratio
hFE
Collector-to-Emitter Saturation Voltage VCE(sat)
TEST CONDITIONS
LIMITS
MIN_
MAX_
Ie = 0.2 A, VCE = 10 V
15
-
IC=lA,VCE=10V
25
100
UNITS
MHz
IC= 1 A,IB =0.125A
-
0.75
V
ES/b
IC=2A,L=100pH
RBE =20in
200
-
pJ
Second-Breakdown Collector Current:
With base forward-biased
IS/b
VCE = 100 V, t = 1 s
350
-
mA
Saturated Switching Time:
Turn-on
Turn-off
tON
toFF
IC= 1 A
IC= 1 A
Second-Breakdown Energy:
With base reverse-biased
-
3
7
-
ps
po
For characteristics curves and test conditions, refer to published data for basic type in File No. 138.
JAN2N3771, JAN2N3772
High-Current
JANTX2N3771, JANTX2N3772Sillcon N-P-N Power Transistors
JAN Electrical Specification: MIL-8-19500/413
Structure: Hometaxial-base
Applications: Power-switching, amplifiers, inverters
System Usage: Military
Package: JEDEC TO-3
Maximum Ratings: PT = 150 W; VCEO = 40 V (2N3771)
,;, 60 V (2N3772)
ELECTRICAL CHARACTERISTICS, At Case Temperature (TCI = 25"C Unless Otherwise Specified
CHARACTERISTIC
LIMITS
SYMBOL
TEST CONDITIONS
fT
Ie = 1 A, VCE = 4 V
600
-
kHz
DC Forward-Current Transfer Ratio
hFE
Ie = 10 A, VCE = 4 V
le= 15A;VeE=4V
15
15
60
60
2N3772
2N3771
Second-Breakdown Energy:
With base reverse-biased
ES/b
Ie = 5 A, L = 40 mH,
RBE= 100n
500
-
mJ
Second-Breakdown Collector Current:
With base forward-biased
ISlb
VCE=60V,t= 1 s
2.5
-
A
Turn-on
tON
Turn-off
tOFF
2N3772
2N3771
le= lOA IC= 15A
le=10A le= 15A
Gain-Bandwidth Product
Saturated Switching Time:
Thermal-Cycling Rating
PT= 20W,6TC= 50"C
For characteristics curves and test conditions, refer to published data for basic type in File No. 525.
34
MIN.
4x 105
MAX.
2N3771 2N3772
10
8
12
10
-
UNITS
ps
ps
Thermal
Cycles
JAN2N5038, JA N2N5039
High-Speed
JANTX2N5038., JANTX2N5039 Silicon N-P-N Power Transistors
JAN Electrical Specification: MIL-S-19500/439
Structure: Multiple-emitter sites, double-diffused
epitaxial collector
Applications: Switching regulators, inverters, amplifiers
System Usage: Military
Package: JEDEC TO-3
Maximum Ratings: PT = 140 W; VCEO = 90 V (2N50381
= 75 V (2N50391
ELECTRICAL CHARACTERISTICS, At Case Temperature (TC) =25"C Unless Otherwise Specified
CHARACTERISTIC
Gain-Bandwidth Product
I
DC Forward-Current Transfer Ratio
SYMBOL
fT
hFE
TEST CONDITIONS
LIMITS
MIN_
MAX_
UNiTS
2NS03B
IC=2A, VCE= 10V
60
IC=12A,VCE=SV
20
IC=10A,VCE=SV
20
-
13
-
mJ
MHz
2NS039
Second-Breakdown Energy:
With base reverse-biased
ESlb
IC",12A,L= 1BO IIH,
RBE = 20n
Second Breakdown Collector Current:
With base forward-biased
ISlb
VCE=4SV,t= 1 s
0.9
-
A
tON
tOFF
IC= 12A
IC=12A
-
-
O.S
2
liS
PT = 20 W, lITC = SO°C
4x lOS
-
Saturated Switching Time:
Turn-on
Turn-off
Thermal-Cycling Rating
liS
Thermal
Cycles
For characteristics curves and test conditions. refer to published data for basic type in File No. 367.
JAN2N5415, JAN2N5416
!High-Voltage
JANTX2N5415, JANTX2N5416 Silicon P-N-P Power Transistors
JAN Electrical Specification: MIL-S-19S00/4BS
Structure: Double-diffused epitaxial
Applications: High-voltage amplifiers, inverters, regulators
System Usage: Military
Package: JEDEC TO-S
Maximum Ratings: PT = 0.7S W; VCEO = -200 V (2NS41SI
= -300 V (2NS4161
ELECTRICAL CHARACTERISTICS, At Case Temperature (TC) = 25"C Unless Otherwise Specified
CHARACTERISTIC
Gain-Bandwidth Product
DC Forward-Current Transfer Ratio
SYMBOL
fT
hFE
Collector·to-Emitter Saturation Voltage VCE(satl
Second-Breakdown Collector Current:
With base forward-biased
ISlb
Saturated Switching Time:
Turn-on
tON
Turn-off
tOFF
TEST CONDITIONS
LIMITS
MIN.
MAX.
IC = -10 rnA, VCE= -10 V
1S
-
IC= -SO rnA, VCE = -10 V
30
120
IC - -SO rnA, IB - -S rnA
-
VCE=-100V,t= 15
-100
IC= -SO rnA
IC- -SOmA
-
UNITS
MHz
-2
V
-
rnA
1
10
liS
liS
For characteristics curves and test conditions, refer to published data for basic type in File No. 336.
35
High-Speed
JAN2N5671, JAN2N5672
JANTX2N5671, JANTX2N5672 Silicon N-P-N Power Transistors
JAN Electrical Specification: MIL-S-19500/488
Structure: Double-diffused epitaxial collector
Applications: Switching regulators. amplifiers
System Usage: Military
Package: JEDEC TD-3
Maximum Ratings: PT = 140 W; VCEO = 90 V (2N5671)
= 120 V (2N5672)
ELECTRICAL CHARACTERISTICS. At Case Temperature (TC) = 25"C Unless Otherwise Specified
CHARACTERISTIC
Gain-Bandwidth Product
SYMBOL
fT
DC Forward-Curr.ent Transfer Ratio
hFE
Collector-to-Emitter Saturation Voltage VCE(sat)
TEST CONDITIONS
LIMITS
MIN_
MAX_·
UNITS
IC=2A.VCE=10V
50
-
MHz
IC = 15 A. VCE = 2 V
20
IC= 15A.IB = 1.2A
-
100
0.75
V
20
-
mJ
Second-Breakdown Energy:
With base reverse-biased
ES/b
IC= 15A. L = 18O!.tH
RBE = 20n
Second-Breakdown Collector Current:
With base forward-biased
IS/b
VCE = 45 V. t = 1 s
0.9
-
A
tON
tOFF
IC=15A
IC-15A
-
0.5
2
!.ts
!.ts
Saturated Switching Time:
Turn~on
Turn-off
For characteristics curves and test conditions, refer to published data for basic type in File No. 383.
JAN2N5838-JAN2N5840
High-Voltage
JANTX2N5838-JANTX2N5840 Silicon N-P-N Power Transistors
JAN Electrical Specification: MIL-S-19500/487
Structure: Double-diffused. epitaxial-base
Applications: High-voltage switching regulators. inverters
System Usage: Military
Package: JEDEC TO-3
Maximum Ratings: PT = 100 W; VCEO = 250 V (2N5838)
= 275 V (2N5839)
= 350 V (2N5840)
ELECTRICAL CHARACTERISTICS. At Case Temperature (Tc! = 25"C Unless Otherwise Specified
CHARACTERISTIC
Gain-Bandwidth Procuct
DC Forward-Current Transfer Ratio
SYMBOL
fT
hFE
TEST CONDITIONS
MIN.
IC = 0.2 A. VCE = 10 V
5
LIMITS
MAX.
-
10
50
IC - 3 A. VCE - 2 V
8
40
IC=2A.VCE=3V
UNITS
MHz
2N5840
2N5839
2N5838
Second-Breakdown Energy:
With base reverse-biased
ESlb
IC = 3 A. L = 100!.tH
RBE = 50n
0.45
-
mJ
Second-Breakdown Collector Current:
With base forward·biased
ISlb
VCE=40V.t=ls
2.5
-
A
tON
tOFF
IC= 2 A
IC = 2 A
-
1.75
4.5
!.ts
!.ts
Saturated Switching Time:
Turn-on
Turn-off
For characteristics curves and test conditions. refer to published data for basic type in File No. 410.
36
JAN2N6211-JAN2N6213
JANTX2N6211- JANTX2N6213
High-Voltage
Silicon P-N-P Power Transistors
JAN Electrical Specification: MIL-S-19500/461
Structure: Double-diffused epitaxial collector
Applications: High-voltage amplifiers, inverters, regulators
System Usage: Military
Package: JEDEC TD-66
Maximum Ratings: PT = 35 W;VCEO = 225 V (2N6211)
= 300 V (2N6212)
= 350 V (2N6213)
ELECTRICAL CHARACTERISTICS, At Case Temperature (TC) = 25"C Unless Otherwise Specified
CHARACTE RISTIC
Gain-Bandwidth Product
SYMBOL
D-
TEST CONDITIONS
IC
I~
DC Forward-Current Transfer Ratio
Second-Breakdown Collector Current:
With base forward-biased
hFE
= -0_2 A, VCE = -10 V
= -I A V~~ = -4 V
= -I A, VCE = -3_2 V
IC
IC - -I A, VCE - -2_8 V
= -40
IStb
VCE
Turn-on
tON
Turn-off
tOFF
= -I
= -I
PT = 2
V, t
=I
s
MIN_
LIMITS
MAX_
UNITS
20
-
MHz
10
10
10
lOa
lOa
2N6213
2N6212
2N6211
-0_875
-
A
-
0_6
3_1
JJ-S
JJ-S
7x 105
-
Thermal
Cycles
100
Saturated Switching Time:
Thermal-Cycling Rating
IC
IC
A
A
W, "'TC
= 50a C
For characteristics cUlVes and test conditions, refer to published data for basic type in File No. 507.
37
High-Speed, Medium-Power
Silicon N-P-N Power Transistor
2N2102
Structure: Planar, Double-diffused epitaxial collector
Applications: Small-signal and medium-power general usage
System Usage: NASA SATURN
Package: JEDEC TO-39 12N2102S1 or JEDEC TO-5 12N2102LI
Maximum Ratings: VCEO - 65 V. PT = 1 W
ELECTRICAL CHARACTERISTICS, At Case Temperature (Tci = 2SOC Unless Otherwise. Specified
SYMBOL
CHARACTERISTIC
f,-
Gain-Bandwidth Product
DC Forward-Current Transfer Ratio
hFE
Collector-to-Emitter Saturation Voltage VCE(sat)
TEST CONDITIONS
LI~
ITS
MIN_
MAX.
)20
UNITS
40
-
MHz
IC - 150 mA, VCE - 10 V
Ic-150mA,IB-15mA
-
1.5
V
IC= 50 mA, VCE = 10V
For characteristics curves and test conditions. refer to published data for basic type In File No. 106.
Hometaxial-Base
Silicon N-P-N Power Transistor
2N3054
Structure: Hometaxial-base
Applications: Power-switching, amplifiers
System Usage: Military
Package: JEDEC TO-66
Maximum Ratings: VCEO = 65 V. PT
= 25 W
ELECTRICAL CHARACTERISTICS, At Case Temperature (TCi = 2SOC Unless Otherwise Specified
CHARACTERISTIC
Gain-Bandwidth Product
SYMBOL
f,-
DC Forward-Current Transfer Ratio
hFE
Collector-to-Emitter Saturation Voltage VCE(sat)
Second-Breakdown Collector Current:.
With base forward-biased
Thermal-Cycling Rating
ISlb
TEST CONDITIONS
IC = 0.2 A, VCE = 4 V
BOO
IC = 0.5 A, VCE = 4 V
25
IC = 0.5 A, IB = 0_05 A
-
MAX.
-
ulinTS
kHz
1
V
VCE=55V,t= 1 s
0.455
-
A
PT=4W,LlTC-50"C
5x 105
-
Thermal
Cycles
For characteristics curves and test conditions, refer to published data for basic type in File No, 527.
38
LIMITS
MIN_
High-Power, High-Speed, High-Current
Silicon N-P-N Power Transistor
2N3263
Structure! Double-diffused epitaxial collector
Applications: High-speed switching, amplifiers. inverters
System Usage: Minuteman. SRAM
Package:" Radial, hermetic
Maximum Ratings: VCEO
= 90 V. PT = 84 W
ELECTRICAL CHARACTERISTICS, At Case Temperature (TC) = 2SOC Unless Otherwise Specified
CHARACTERISTIC
SYMBOL
TEST CONDITIONS
LIMITS
MAX.
MIN.
Gain·Bandwidth Product
t,-
IC= 3 A, VCE
= 10V
20
-
DC Forward·Current Transfer Ratio
hFE
IC - 15 A, VCE - 3 V
25
-
Coliector·to·Emitter Saturation Voltage
VCE(sat)
IC - 15 A, IB - 1.2 A
Second·Breakdown Energy:
With base reverse-biased
ESlb
IC= 10A, L=40j.LH
RBE = 20n
Second·Breakdown Collector Current:
With base forward·biased
I SIb
VCE = 75 V, t= 250j.Ls
tON
tOFF
IC= 15A
IC-15A
Saturated Switching Time:
Turn-on
Turn·off
. .
..
For characteristics curves and test conditions, refer to published data for baSIC type
-
MHz
0.75
V
2
-
mJ
350
-
A
0.5
2
j.LS
j.LS
-
In
UNITS
File No. 54 .
High-Power, High-Speed, High-Current
Silicon N-P-N Power Transistor
2N3265
Structure: Double-diffused epitaxial collector
Applications: High-speed switching, amplifiers, inverters
System Usage: Minuteman. SRAM
Package: JEDEC TO·S3
Maximum Ratings: VCEO = 90 V. PT = 125 W
ELECTRICAL CHARACTER ISTICS, At Case Temperature (TC) = 25°C Unless Otherwise Specified
CHARACTERISTIC
SYMBOL
TEST CONDITIONS
LIMITS
MIN.
Gain-Bandwidth Product
t,-
IC=3A,VCE=10V
20
DC Forward-Current Transfer Ratio
hFE
IC= 15A, VCE = 3 V
25
Coliector·to·Emitter Saturation Voltage
VCE(sat)
IC-15A,IB-1.2A
Second·Breakdown Energy:
With base reverse-biased
ESlb
IC= 10A, L=40j.LH
RBE = 20n
Second Breakdown Collector Current:
With base forward-biased
ISlb
VCE = 75 V, t =250 j.Ls
Saturated Switching Time:
Turn-on
Turn-off
tON
tOFF
IC= 15A
IC= 15A
. .
..
-
MAX.
-
UNITS
MHz
0.75
V
2
-
mJ
350
-
mA
0.5
2
j.LS
-
j.LS
For characteristics curves and test conditions, refer to published data for baSIC tYpe to File No. 54 .
39
High-Voltage
Silicon N-P-N Power Transistor
2N3773
Structure: Hometaxial-ba58
Applications: High-voltage inverters. amplifiers, hammer drivers
System Usage: VIKING
Package: JEDEC TO-3
Maximum Ratings: VCEO a 140 V. PT = 150 W
ELECTRICAL CHARACTERISTICS. At Case Temperature (TCi = 25"C Unless Otherwise Specified
CHARACTERISTIC
SYMBOL
TEST CONDITIONS
LIMITS
MAX_
-
kHz
Gain-Bandwidth Product
fT
IC = 1 A. VCE = 4 V
200
DC Forward-Current Transfer Ratio
hFE
IC = 8 A. VCE = 4 V
15
IC = 8 A. IB - 0_8 A
-
1.4
V
ESlb
IC=2_5A. L=40mH
RBE= lOOn
0_125
-
J
ISIb
VCE= 100V.t= 1 s
1_5
-
PT = 20 W. 6TC = 50°C
4x 105
-
Collector-to-Emitter Saturation Voltage VCE(sat)
Second-Breakdown Energy:
With base reverse-biased
Second-Breakdown Collector Current:
With base forward-biased
UNITS
MIN_
Thermal-Cycling Rating
A
Thermal
Cycles
·For characteristics curves and test conditions, refer to published data for basic type in File No. 526.
High-Current, High-Speed
Silicon N-P-N Power Transistor
2N3879
Structure: Double-diffused epitaxial collector
Applications: High-current, high-speed switching
System Usage: Military
Package: JEDEC TO-66
Maximum Ratings: VCEO = 75 V. PT = 35 W
ELECTRICAL CHARACTERISTICS. At Case Temperature (Tci = 25"C Unless Otherwise Specified
CHARACTERISTIC
Gain-Bandwidth Product
SYMBOL
fT
DC Forward-Current Transfer Ratio
hFE
Collector-to-Emitter Saturation Voltage VCE(sat)
TEST CONDITIONS
60
-
IC = 4 A. VCE = 5 V
20
-
IC=4A.IB=0.4A
ESlb
IC=4A. L= 1251lH
RBE = 50n
Second-Breakdown Collector Current:
With base forward-biased
ISlb
VCE = 40 V. t
tnM
1,..=4A
IC=4A
tOFF
=1 s
For characteristics curves and test conditions, refer to published data for basic type in File No, 299.
40
MAX_
IC=0_5A. VCE= 10V
Second-Breakdown Energy:
With base reverse-biased
Saturated Switching Time:
Turn-on
Turn-off
LIMITS
MIN_
-
UNITS
MHz
1.2
V
1
-
mJ
500
-
mA
-
440
1200
ns
ns
Medium-Power
Silicon P-N-P Power Transistor
2N4036
Structure: Planar, double-diffused epitaxial collector
Applications: Small-signal. medium-power amplifiers
System Usage: Military
Packaga: JEOEC TO·39 (2N4036S) or JEOEC TO·5 (2N4036L)
Maximum Ratings: VCEO = -65 V. PT = 1 W
ELECTRICAL CHARACTERISTICS, At Case Temperature (TCi = 2[;oC Unless Otherwise Specified
CHARACTER ISTIC
SYMBOL
TEST CONDITIONS
LIMITS
MAX.
MIN.
Gain·Bandwidth Product
fT
IC = -50 rnA, VCE = -10 V
60
-
DC Forward·Current Transfer Ratio
hFE
IC = -150 rnA, VCE - -10 V
40
-
Collector·to·Emitter Saturation Voltage
VCE!sat)
IC
Saturated Switching Time:
Turn·on
Turn·off
toN
tOFF
Ic=-150mA
Ic--150mA
-150 rnA, IB - -15 rnA
-
-
UNITS
MHz
-0.65
V
110
700
ns
ns
For characteristics curves and test conditions. refer to published data for basic type in File No. 216.
High-Voltage, High-Power
Silicon N-P-~ Power Transistor
2N5240
Structure: Double-diffused epitaxial collector
Applications: Series regulators, power amplifiers
System Usage: Military
Package: JEOEC T0-3
Maximum Ratings: VCEO'" 300 V. PT "" 100 W
ELECTRICAL CHARACTERISTICS, At Case Temperature (TCi = 2[;oC Unless Otherwise Specified
CHARACTERISTIC
SYMBOL
TEST CONDITIONS
Gain·Bandwidth Product
f,-
IC = 0.2 A, VCE = 10 V
DC Forward·Current Transfer Ratio
hFE
IC= 2 A, VCE = 10V
Second·Breakdown Collector Current:
With base forward·biased
. .
..
5
20
MAX.
-
UNITS
MHz
IC=2A,IB=0.25A
-
2.5
V
ESlb
IC = 4 A, L = 0.2 mH
RBE = 50n
1.6
-
mJ
ISlb
VCE= 150V,t= 1 s
0.67
-
A
Collector-ta-Emitter Saturation Voltage VCE!sat)
Second·Breakdown Energy:
With base reverse·biased
LIMITS
MIN.
For charactenstlcs curves and test conditions, refer to published data for basic type in File No. 321 .
41
High-Speed
Silicon N-P-N Power Transistor
2N5262
Structure: Double-diffused epitaxial
Applications: Core drivers, high-speed amplifiers
System Usage: AEGIS
Package: Low~profile TO·39
Maximum Ratings: VCEO "" 50 V. PT
=1 W
ELECTRICAL CHARACTERISTICS, At Case Temperature (TCl = 25"C Unless Otherwise Specified
CHARACTERISTIC
SYMBOL
TEST CONDITIONS
LIMITS
MAX.
250
-
MHz
0.8
V
Gain·Bandwidth Product
fT
Ic=50mA,VCE=10V
DC Forward·Current Transfer Ratio
hFE
IC - 1 A, VCE - 1 V
25
Collector-to-Emitter Saturation Voltage
VCE(sat)
IC - 1 A, IB - 0.1 A
-
Saturated Switching Time:
Turn-on
Turn-off
tON
tOFF
IC= 1 A
IC= 1 A
.
.
..
For characteristics curves and test conditions. refer to publrshed data for
baSIC
-
30
60
-
type
In
UNITS
MIN.
ns
ns
File No. 313.
High-Speed
Silicon N-P-N Power Transistor
2N5320
Structure: Double-diffused epitaxial collector
Applications: Small-signal and medium-power amplifiers
System Usage: Military
Package: JEDEC TO-39 12N5320S1 or JEDEC TO-S 12N5320LI
Maximum Ratings: VCEO = 75 V, PT = 1 W
ELECTRICAL CHARACTERISTICS, At Case Temperature (TCl = 25"C Unless Otherwise Specified
CHARACTERISTIC
SYMBOL
TEST CONDITIONS
LIMITS
MIN.
MHz
-
0.5
V
-
80
800
ns
ns
fT
IC = 50 mA, VCE = 4 V
50
DC Forward-Current Transfer Ratio
hFE
Ic=500mA,VCE=4V
30
Collector-to-Emitter Saturation Voltage
VCE(sat)
IC = 500 mA, IB = 50 mA
Saturated Switching Time:
Turn-on
Turn-off
tON
tOFF
Ic=500mA
IC= 500mA
.
.
..
42
In
File No. 325.
UNITS
-
Gain-Bandwidth Product
For characteristiCS curves and test conditions, refer to published data for basIc type
MAX.
-
High-Speed
Silicon P-N-P Power Transistor
2N5322
Structure: Double-diffused epitaxial collector
Applications: Small-signal. medium-power amplifiers
System Usage: Military
Package: JEDEC TO-39 (2N5322S1 or JEDEC TQ.5 (2N5322LI
Maximum Ratings: VCEO = -75 V. PT A 1 W
ELECTRICAL CHARACTERISTICS, At Case Temperature (TC) = 25"C Unless Otherwise Specified
CHARACTERISTIC
SYMBOL
h-
Gain·Bandwidth Product
DC Forward·Current Transfer Ratio
hFE
Collector·to·Emitter Saturation Voltage VCE(sat)
TEST CONDITIONS
Turn-on
. .
..
tON
tOFF
MAX.
UNITS
IC = -50 rnA, VCE = -4 V
50
-
IC = -500 rnA, VCE = -4 V
30
-
IC - -500 rnA, IB - -50 rnA
-
-0.7
V
IC= -500 rnA
IC=-500 rnA
-
100
1000
ns
ns
Saturated Switching Time:
Turn·off
LIMITS
MIN.
MHz
For characteristics curves and test conditions, refer to published data for baSIC type In File No. 325.
High-Current, High-Power
Silicon N-P-N Power Transistor
2N5578
Structure: Multiple-emitter sites, homDtaxial-base
Applications: High-current. high-power amplifiers and switching
System Usage: TOW, Sonobuoy
Padcage: JEOEC TQ.3 with O.060-inch-diameter pins
Maximum Ratings: VCEO = 70 V, PT = 300 W
ELECTRICAL CHARACTERISTICS, At Case Temperature (TC) = 25"C Unless Otherwise Specified
CHARACTERISTIC
SYMBOL
Gain·Bandwidth Product
h-
DC Forward·Current Transfer Ratio
hFE
Collector·to·Emitter Saturation Voltage VCE(sat)
Second·Breakdown Energv:
With base reverse·biased
Second·Breakdown Collector Current:
With base forward·biased
..
..
TEST CONDITIONS
LIMITS
MIN.
MAX.
IC=10A,VCE=4V
400
-
IC=40A,VCE=4V
10
-
IC=40A,IB=4A
UNITS
kHz
-
1.5
V
ESlb
IC=7A, L=33mH
RBE= 100
0.8
-
J
ISlb
VCE = 25 V, t = 1 s
12
-
A
For characteristics curves and test conditions, refer to published data for baSIC type In File No. 359 .
43
High-Speed
Silicon P-N-P Power Transistor
2N5781
Structure: Epitaxial·base
Applications: Medium-power switching and amplifiers
System Usage: Military
Package: JEDEC TO-S
Maximum Ratings: VCEO = -65 V, PT = 1 W
ELECTRICAL CHARACTERISTICS, At Case Temperature (TC)
CHARACTERISTIC
Gain·Bandwidth Product
SYMBOL
fT
DC Forward·Current Transfer Ratio
hFE
Coliector·to·Emitter Saturation Voltage VCE(sat)
= 25"C Unless Otherwise Specified
TEST CONDITIONS
LIMITS
MIN.
8
IC=-O.l A, VCE=-2V
IC=-l A, VCE=-2V
MAX.
20
UNITS
-
MHz
IC=-l A, IB--O.l A
-
-0.5
V
IC=-l A
IC - -1 A
-
0.5
2.5
/1s
/1S
Saturated Switching Time:
Turn-on
Turn·off
For characteristics curves and
tON
tOFF
..
test conditions, refer to published data for basIc type
In
File No. 413 .
Hometaxial-Base
Silicon N-P-N Power Transistor
2N5784
Structure: Hometaxial-base
Applications: Medium-power switching, amplifiers
System Usage: Military
Package: JEDEC TO-S
Maximum Ratings: VCEO = 65 V, PT = 1 W
ELECTRICAL CHARACTERISTICS, At Case Temperature (TC)
CHARACTERISTIC
SYMBOL
= 25"C Unless Otherwise Specified
TEST CONDITIONS
LIMITS
MIN.
MAX.
UNITS
Gain·Bandwidth Product
fT
IC = 0.1 A, VCE = 2 V
1
-
DC Forward-Current Transfer Ratio
hFE
IC = 1 A, VCE = 2 V
20
-
IC= 1 A, IB=O.l A
-
0.5
V
IC= lA
-
5
/1S
IC= lA
-
15
/1S
Collector·to·Emitter Saturation Voltage VCE(sat)
MHz
Saturated Switching Time:
Turn-on
Turn·off
tON
tOFF
for characteristics curves and test conditions, refer to published data for basic type in File No. 413.
44
High-Speed, Medium-Power
2N5954
Silicon P-N-P Power Transistor
Structure: Epitaxial-base
Applications: Power-switching. amplifiers
System Usage: Military
Package: JEDEC TO-56
Maximum Ratings: VCEO
= -80 V. PT = 40 W
ELECTRICAL CHARACTERISTICS, At Case Temperature (Tci = 25"C Unless Otherwise Specified
CHARACTERISTIC
SYMBOL
TEST CONDITIONS
LIMITS
MAX.
MIN.
Gain-Bandwidth Product
fT
IC=-l A, VCE=-4V
5
DC Forward-Current Transfer Ratio
hFE
IC = -2 A, VCE = -4 V
20
Collector-to-Emitter Saturation Voltage
VCE(sa!)
IC=-2A,IB=-0.2A
-
-
UNITS
MHz
-1
V
For characteristics curves and test conditions refer to published data for basic type in File No. 675.
iii igh-Current, High-Speed, IH iglh-Power
2N6033
Silicon INI-P-INI Power Transistor
Structure: Double-diffused epitaxial collector
Applications: High-current, fast switching
System Usage: SAFEGUARD
Package: JEDEC TO-3 with O.06D-inch-diameter pins
Maximu"m Ratings: VCEO
= 120 V, PT =
140 W
ELECTRICAL CHARACTERISTICS, At Case Temperature (TCi = 25"C Unless Otherwise Specified
CHARACTERISTIC
SYMBOL
TEST CONDITIONS
Gain-Bandwidth Product
fT
IC = 2 A, VCE = 10 V
LIMITS
MIN.
50
MAX.
-
UNITS
-
MHz
DC Forward-Current Transfer Ratio
hFE
IC = 40 A, VCE = 2 V
Collector-to-Emitter Saturation Voltage
VCE(sat)
IC = 40 A, IB = 4 A
-
Second-Breakdown Energy:
With base reverse-biased
ESlb
IC=20A,L=310IlH
RBE = 5Q
62
-
mJ
Second-Breakdown Collector Current:
With base forward-biased
ISlb
VCE = 40 V, t = 1 s
0.9
-
A
tON
tOFF
Ic=40A
IC = 40A
-
10
1
V
Saturated Switching Time:
Turn-on
Turn-off
1
2
liS
liS
For characteristics curves and test conditions, refer to published data for basic type in File No. 462.
45
Darlington
Silicon N-P-N Power Transistor
2N6056
Structure: Monolithic, epitaxial-base
Applications: Power-switching. amplifiers, hammer drivers
System Usage: Military
Package: JEDEC TO·3
Maximum Ratings: VCEO = 80 V. PT -100 W
ELECTRICAL CHARACTERISTICS, At Case Temperature (TC) = 2fiOC Unless Otherwise Specified
CHARACTERISTIC
Gain·Bandwidth Product
SYMBOL
for
DC Forward·Current Transfer Ratio
hFE
Collector·to·Emitter Saturation Voltage VCE/sat)
Second·Breakdown Energy:
With base reverse·biased
ESlb
Second·Breakdown Collector Current:
With base forward·biased
ISlb
Thermal·Cycling Rating
TEST CONDITIONS
LIMITS
MAX.
MIN.
IC = 3 A, VCE = 3 V
4
-
IC = 4 A, VCE = 3 V
750
-
IC=4A,IB=16mA
-
IC = 5 A, L = 12 mH
RBE = lOOn
150
MHz
2
-
V
mJ
2
-
A
8x 105
-
Thermal
Cycles
VCE=40V,t= 1 s
P,.= 10W,t.TC= 50°C
UNITS
For characteristics curves and test conditions, refer to published data for basic type in File No. 563.
High-Voltage, High-Power
Silicon N-P-N Power Transistor
2N6079
Structure: Multiple-emitter sites. double-diffused epitaxial
Applications: High-voltage inverters
System Usage: SAFEGUARD
Package: JEDEC TO·66
Maximum Ratings: VCEO = 350 V, PT = 45 W
ELECTRICAL CHARACTERISTICS, At Case Temperature (TC)=2fiOC Unless Otherwise Specified
CHARACTERISTIC
Gain·Bandwidth Product
SYMBOL
for
DC Forward·Current Transfer Ratio
hFE
Collector·to·Emitter Saturation Voltage VCE/sat)
Second·Breakdown Energy:
With base reverse-biased
ESlb
Second·Breakdown Collector Current:
With base forward·biased
..
ISlb
TEST CONDITIONS
IC = 0.2 A, VCE = 10 V
1
IC = 1.2 A, VCE = 1 V
12
MAX.
UNITS
-
MHz
IC = 1.2 A, IB = 0.2 A
-
0.5
V
IC= 3 A, L = 100IIH
RBE = 50n
0.45
-
mJ
VCE = 50 V, t = 1 s
0.9
-
A
For characteristics curves and test conditions, refer to pUblished data for basIc type in File No. 492.
46
LIMITS
MIN.
High-Speed, High-Power
Silicon P-N-P Power Transistor
2N62A8
Structure: Epitaxial-base
Applications: Power--switching
System Usage: Military
Package: JEDEC TO-3
Maximum Ratings: VCEO = -100 V. PT= 125W
ELECTRICAL CHARACTERISTICS, At Case Temperature (TC) = 2!JOC Unless Otherwise Specified
CHARACTERISTIC
SYMBOL
TEST CONDITIONS
LIMITS
MAX.
MIN.
-
Gain·Bandwidth Product
fT
IC= -1 A, VCE = -4 V
10
DC Forward·Current Transfer Ratio
hFE
IC - -S A, VCE - -4 V
20
Coliector·to·Emitter Saturation Voltage
VCE(sat)
IC - -S A, IB - -O.S A
-
-1.3
Second·Breakdown Collector Current:
With base forward·biased
ISlb
VCE=-42V,t= 1 s
-1.2S
PT=10W,L'1TC=SO"
I.S x 106
-
Thermal-Cycling Rating
UNITS
MHz
V
A
Thermal
Cycles
For characteristics curves and test conditions, refer to published data for basic type in File No. 541.
!High-Voltage
Silicon N-P-N Power Transistor
2N6251
Structure: Multiple-epitaxial
Applications: High-voltage inverters
System Usage: MARK-48, P-3-C
Package: JEDEC TO-3
Maximum Ratings: VCEO::::l 350 V, PT = 175 W
ELECTRICAL CHARACTERISTICS, At Case Temperature (TC) = 2!JOC Unless Otherwise Specified
CHARACTERISTIC
SYMBOL
TEST CONDITIONS
LIMITS
UNITS
MIN.
MAX.
-
MHz
Gain-Bandwidth Product
fT
IC = 1 A, VCE = 10 V
2.S
DC Forward·Current Transfer Ratio
IC= lOA, VCE=3V
6
Collector-to-Emitter Saturation Voltage
hFE
VCE(sat)
IC - 10 A, IB - 1.67 A
-
1.5
V
Second-Breakdown Energy:
With base reverse-biased
ESlb
IC= lOA, L = SOIlH
RBE = lOOn
2.S
-
mJ
Second-Breakdown Collector Current:
With base forward-biased
ISlb
VCE=30V,t= 1 s
S.B
-
A
PT = 20 W, L'1TC = SO·C
2x lOS
-
Thermal
Cycles
Thermal-Cycling Rating
For characteristics curves and test conditions. refer to published data for basic type in File No. 523.
47
Darlington
Silicon N-P-N Power Transistor
2N6385
Structure: Monolithic. epitaxial-base
Applications: Power-switching, amplifiers, hammer drivers
System Usage: Military
Package: JEDEC To-3
Maximum Ratings: VCED - 80 V. PT ~ 100W
ELECTRICAL CHARACTERISTICS, At Case Temperature (TC) = 25"C Unless Otherwise Specified
CHARACTER ISTIC
SYMBOL
TEST CONDITIONS
MIN.
Gain-Bandwidth Product
fT
IC = 1 A. VCE = 5 V
20
DC Forward-Current Transfer Ratio
hFE
IC = 5 A. VCE = 3 V
1000
Collector-to-Emitter Saturation Voltage
VCE(sat)
IC = 5 A. IB = 0_0.1 A
-
Second-Breakdown Energy:
With base reverse-biased
ESlb
IC=4_5A. L= 12mH
RBE = lOon
Second-Breakdown Collector Current:
With base forward-biased
I SIb
Thermal-Cycling Rating
-
VCE = 75 V. t = 1 s
0_22
-
8x 105
-
UNITS
MHz
2
PT = 10 W. t.TC = 50"C
For characteristics curves and test conditions, refer,to published data for basic type in File No. 609.
48
120
MAX.
V
mJ
A
Thermal
Cvcles
Radiation-Hardened
Silicon N-P-N Power Transistor
2N6479 2N6481
2N6480 2N6482
Epitaxial-Planar Types for Aerospace and Military Applications
Rated for Operation in Radiation Environments with" Neutron Fluence Levels to 1 x 1014 Neutrons/cm2
and Gamma Exposure up to 1x108 Rad (Sills
ELECTRICAL CHARACTERISTICS, At Case Temperature (TCl = 2iPC
PRE-RADIATION
CHARACTERISTIC
TEST CONDITIONS
VOLTAGE
CURRENT
A de
V de
SYMBOL
VCB
Collector Cutoff Current:
With emitter open
*
With base.emitter junction
*
*
At TC·1Oo"C
reverse-biased
ICBO
ICEV
Emitter Cutoff Current
lEBO
Emitter-ta-Base Voltage
VEBO
VCE
VEB
IE
IB
LIMITS
2N64B0
2N64B2
2N6479
2N6481
IC
100
MAX.
MIN.
MAX.
-
1
-
1
1
1
1
-
2
2
mA
6
-
6
-
V
60
-
BO
-
0
60
0
0.002
mA
-
100
-
6
UNITS
MIN.
mA
1
Collector-ta-Emitter
*
Sustaining Voltage:
With base open
0.2 8
VCEO(SUS)
With external base-toemitter resistance
V
0.2 b
BO
-
100
-
*
Collector-to-Emitter
Saturation Voltage
VCEIs8tl
1.2
128
-
0.75
-
0.75
V
*
*
Base-ta-Emitter
Saturation Voltage
VSE(sat}
1.2
128
-
1.5
-
1.5
V
12"
20
300
20
300
7.3
-
7.3
-
(RBEI·l00 n
*
*
VCER(suS)
DC Forward Current
Transfer Ratio
hFE
2
Second Breakdown
Collector Current:
With base forwardbiased, t '" 1 s
ISlb
12
A
Saturated Switching Time
Rise
t,
VCC·
1.2 c
12
.-
400
-
400
Storage
t,
30
1.2c
12
-
BOO
BOO
Fall
tf
1.2 c
12
.-
200
-
1
10
.-
10
-
Magnitude of Common
Emitter Small·Signal
Short Circuit Forward
Current Transfer
Ratio (f c 10 MHz)
Thermal Resistance
tJunctio(l&to·Case)
Ihfel
ROJC
5
10
5
"'
200
2N6479
2N64Bl
0
:Nj 2
2NjB2
-
1.5
°e/W
*
In accordance with JEDEC registration data format JS-6 RDF-1.
a Pulsed; pulse duration ~ 350 ps, duty factor ~ 2%.
e IB1· IB2
49
POST-NEUTRON-RADIATION ELECTRICAL CHARACTERISTICS
AFTER EXPOSURE TO 5 x 1013 NEUTRONS/cm 2 (1 MeV equiv_l. At Case Temperature (TC) = 2~C
TEST CONOITIONS
CHARACTERISTIC
VOLTAGE
V de
SYMBOL
VCE
VBE
100
0
LIMITS
For all
TVpes
CURRENT
A de
IC
VEB
IB
UNITS
MIN.
MAX.
-
1.2
rnA
-
2.2
rnA
* Collector Cutoff Current:
With base-emitter
junction reverse-biased
ICEV
* Emitter Cutoff Current
5
lEBO
* Collector-ta-Emitter
Sustaining Voltage:
With base open
* Collector-ta-Emitter
Saturation Voltage
* Base-ta-Emitter
Saturation Voltage
0.2
0.2
0.05
0.05
BOb
VCEolsus)
60~
-
V
VCElsa')
7a
1.4
-
1.5
V
VBElsa')
7a
1.4
-
1.5
V
-
* DC Forward Current
Transfer Ratio
hFE
5
7a
12
Ihlel
5
1
10
-
-
9 x 10.16
Magnitude of Common
Emitter, Small-Signal
Short Circuit Forward
Current Transfer
Ratio (f - 10 MHz)
* Damage Constant
K"
* In accordance with JEDEC registration data format
Where hFE 1
=
Beta prior to exposure
hFE2
=
Beta after exposure
JS-6 RDF-l.
<
< 2%.
a Pulsed; pulse duration
350 1J5, duty factor
b For types 2N6480, 2N6482.
C For types 2N6479, 2N6481.
¢ = Neutron fluence 11 MeVequiv.1
Knowing K. "FE 2 may be calculated for other
fluences using the relationship:
1
h FE2 = - - - 1 K.,+--
·Damage constant K =
hFE1
TYPICAL CHARACTERISTIC DURING GAMMA EXPOSURE FOR DOSE
RATES OF lESS THAN 1 X 108 RAD(SiI/sec
CHARACTERISTIC
Collector·to·Base
Charge Generation
Constant
SYMBOL
ICI
TEST CONDITIONS
LIMITS
VOLTAGE - V de
For all
Types
VCB
V BE
TYPICAL
20
0
5x10 -8
UNITS
Coulomb
~
The charge generated in the depletion region of a transistor is proportional to the
volume of the depletion region, the total dose, and the energy of the gamma radiation.
The primary base-collector photo current [Ipp(basel] "" (C)i, where i is the gamma dose rate in Rad(SO/s.
50
Power Transistors
Application Notes
OOcr8LJD
Solid State
Division
AN-6071
Evaluation of Hermeticity of
Aluminum TO-3 Packages
Under Thermal-Cycling
Conditions (Reliability Report)
A program that continually upgrades product and
develops meaningful rating systems is a requirement in the
power-semiconductor business. RCA's program has played a
major role in the development of products and has led to the
specification of ISIb, ESIb, and thermal·cycling ratings.
RCA's experience in determining the thermal·cycling ratings
of power transistors has shown that package material and
assembly systems muSt be looked at very carefully from a
thermal-fatigue viewpoint. This report evaluates the thermal
capabilities of our qompetitors' aluminum TO-3 package with
soldered· in leads against the RCA steel TO·3 package with
glass-sealed leads.
Failure Data
In conjunction with its ongoing thermal·cycling rating
program, RCA continually evaluates product from its major
competitors. The results of this evaluation are quite
significant in the case of the aluminum TO·3 package. Type
2N3055 product in the aluminum TO-3 package from three
major competitors has been evaluated and the results
compared to those achieved with RCA's steel TO-3 package.
None of the competitors' product tested passed RCA's
thermal'cycling criteria, and, in addition, all of the product
demonstrated early failures in thermal-fatigue tests for
hermeticily. It is RCA's opinion that the aluminum package
as it is now manufactured is unacceptable, and that, in
addition, it has some fundamental engineering problems that
indicate that it may never be a viable hermetic-package
system. Tables I and II show tYPIcal examples of the data
gathered during tests of Type 2N3055 devices in aluminum
TO-3 packages. Tables III and IV show additional data on a
second, recently announced transistor type housed in the
aluminum TO-3 package. Note that most failures occurred
before 5000 cycles.
Failure Analysis
Helium Leak Test - Before and after each test, all units were
checked by submitting them to a four·hour helium bomb and
then to a helium-leak detector.
Freon Bubble - The freon·bubble test is a gross·leak test
in which the units are freon·bombed overnight (in FC-78
helium) and then submerged in hot freon (FC·43) and
checked for bubble exodus. Analysis of the leakers showed
that the devices lost hermeticity at the glass eyelet assemblies
(emitter and base leads) tho' are soldered into the aluminum
header after the number of thermal cycles indicated.
Note that no RCA devices failed the thermal-cycling test.
RCA steel TO·3 devices were included in these tests only
as controls; the life of the RCA steel-packaged 2N3055
on the 16·W thermal-cycling test is typically well beyond
100,000 cycles before first failures.
Table I - Results of 16·W Thermal·Cycling
Test of 2N3055 - 10,000 Cycles
(TC "" 40 to 130°C, No. of Units = 10
Table II - Results of Temperature-Cycling
NO. OF FAILURES ALUM. TO·3
Mfr.C
Mfr. A
Mfr.B
TEST
Test of 2N3055 - 75 Cycles
STEEL TO.l RCA
ITC = -65 to +150o C. No. of units = 151
Helium Leak-
NO. OF FAILURES ALUM. TO·3
Mfr. A
Mfr.B
Mrf.C
TEST
Fine
Freon Bubble Gross
Total
Cumulative Electrical
Failures for 10,000
Cycles
...1...
2-
J!.
..Q..
10
9
3
0
5 Short
10 jc
1 Open
4 Short
7 Short
Helium Leak Fine
STEEL TO·3 RCA
14
5
0
-L
..L
....Q....
Freon Bubble -
Gross
Total
....Q...
9
15
6
0
.. 0jc increased more than 25 percent
11·73
51
AN-6071 _____________________________________________________________
Table III - Results of 16-W Thermal-Cycling Test on Second
Device - 3000 Cycles
(TC=40to 1300C, No. of units = 12)
(TC = -65 to +1500C, No. of units = 12)
NO. OF FAILURES
ALUM. TO-3
MANUFACTURER A
TEST
Table IV - Results of Temperature Cycling Test on Second
Device - 25 Cycles
NO. OF FAILURES
ALUM_ TO-3
MANUFACTURER A
TEST
Helium LeakFine
0
Helium LeakFine
0
Freon Bubble Gross
9
Freon Bubble Gross
3
Total
9
Engineering Problem
Fig. 1 shows an exploded view of the aluminum TO-3
package; all three competitors use lead eyelet assemblies that
are soldered into the aluminum flange. The cyclic heating
and coolil)g of the aluminum package cause expansion and
contraction of the flange with respect to the eyelet assembly
and propagate microcracks that ultimately cause I.-aks.
Contamination of the solder holding the eyelet assembly
probably initiates the problem.
Total
3
header because the melting point of aluminum is below that
of the glass used in the seal. Consequently. manufacturers
who use aluminum packages are forced to use a soldered-in
assembly.
"_~ ~
CA
r
STEELSHEl.L
WELDED TO FLANGE
~
NICKEL-PLATED
VW---PtruSPHOR-SRONZE CLIPS
SOlDEREDTD LEADS
ALUMINUM SHELL COLD-WELDED
G-~'
*
~
~
GLASS-TO-fLANGE
SEAl
SOLoER PREFORMS
NICKEL-PLATED COPPER
O@
NICKEL-PLATED ALUMINUM FLANGE
Aluminum TO-3 package.
Fig. 2 shows the RCA steel TO-3 package. Note the
glass-to-stem seal with no solder interface. This configuration
is possible witll the steel package because the melting
point of steel is far higher than the melting point of glass. It
is not possible to use the same system with the aluminum
52
'< ....
G
I
Fig.l-
'
I" . .
FLANGE
~
o
1. .
~
GOLD-PLATED GLASSED-IN
LEAD-EYELET ASSEMBLIES
DUAL-METAL PELLET
~----HEAT SINK SOLDERED TO
ALUMINUM TOPIEBal8 SOLDER
ALUMINUM FLANGE
ON BOTTOM (COLLECTOR)
SOLDER-COAT£D PELLET----re,
Fig.2-
RCA steel TO-3 package.
Conclusion
RCA's competitors have proclaimed the attributes of
aluminum packages and hard - solder power (the power
available from a package in which the pellet has been
mounted by the use of a hard-solder method!. We believe that
the soldered-in eyelet associated with the aluminum package
has serious reliability and fundamental engineering problems.
This is also true of their so-called "hard-solder" packages,
which use the same type of soldered-in eyelet assemblies.
RCA's steel package with its glass-to-stem seal, welded cap,
and controlled solder process, is far superior to the
aluminum package and hard-solder mounting system-over an
order of magnitude better. The aluminum package has a long
way to go to compete. The customer who buys a device in a
'1'0-3 package may think he is buying long-term hermeticity;
he may have a serious problem if it's aluminum.
OOCIT5LJIJ
Power Transistors
Solid State
Application Note
AN-6249
Division
Real-Time Controls of
Silicon Power-Transistor Reliability
L. J. Gallace and V. J. Lukach
This Note compares the traditional, classical approach to
the reliability-assurance testing of power transistors with a
newer classification of testing: Real-Time Control, RTC. The
classical approach is commonly referred to as Group B, and involves a series of mechanical, environmental, and life stress
tests. RTC is a continuous, systematic evaluation and control
in "real time" of basic, potential failure mechanisms. It is an
important supplement to a total program intended to assure
the reliable performance of power transistors.
Classical Method of Determining Reliability
When examining semiconductor reliability. the term "reliability" itself must first be defined and understood. Because
"reliability" means different things to different people, it becomes necessary to define the degree or level of reliability required in the classical and universal language of statistics. The
procedure of accumulating life-test data under conditions which
may be application-oriented to obtain MTF (mean·time·tofailure) data is an oversimplified way of demonstrating reliability when one desires millions of device hours with a small
number of failures. Unless one is interested in demonstrating
only modest levels of reliability, this procedure will be totally
inadequate for determining how well the manufacturing
process produces devices that meet the intended design
criteria.
Table I indicates the enormous sample sizes required to
demonstrate very low failure rates by the classical method.
The equally enormous expenditures in facilities and time
required to test samples of the sizes shown is obvious.
Table I - Sample Size Required for 1000-Hour life Test
With Zero
at 90%
Confidence
With One
failure
at 90%
Confidence
With Thr••
failures
at 90%
Confidence
231
2,303
23,026
230,000
390
3,891
38,980
389,000
668
6,681
66,808
668,000
Failure
Rat. %/
1000 Hrs.
Failures
1.0
0.1
0.01
0.001
Fig. I(a) shows the "bathtub curve" used in the classical
method to characterize the random failure region; this curve is
an oversimplification of the three curves shown in Fig. I (b)
representing various failure modes. Clearly, the bathtubcurve method of de terming a region which by its very
definition is random and largely unpredictable is unsatisfactory.
INFANT
'
I
MORTALlTY:
RANDOM FAILURES:
I
I
I
I
WEAROUT
~
FAILURES
TIME
101
92C5-23374
TIME
101
92'::S-23465
Fig. 1 - (a) Generalized "bathtub" failure-rate curve, (bJ family of
curves from which the "bathtub" curve in (a) is derived.
Comparison of Group Band RTC
The classical approach was developed years ago because
some over-all protection in the form of reliability assurance was
needed by customers. TIlese Group B tests, performed
under standardized MIL-STD·7S0 conditions, were necessary
and useful. However, times have changed. Reliability engineers
have overstress-tested devices to destruction; in addition, a
wealth of customer field information is available. Failure analysis performed on a routine basis has added even more knowledge. The net result is a greater understanding and appreciation
of categories of potential failure mechanisms associated with
different product designs than was previously possible; RTC
is a reliability-assurance testing system that takes advantage of
all this information.
'2·74
53
AN-6249 ________________________________________________________
Reliability-assurance data published per specific customers'
requests has traditionally consisted of Group-B test results. In
general, the summation of data shows large sample sizes with
near zero total failures. RTC, with its accelerated test conditions, may not show zero failures. Therefore, when RTC data
is published externally, customers must be educated in its
interpretation. This education usually consists of personal can·
tact and a qualitative explanation of each report.
The foundation of RTC is accelerated testing, tests performed
at higher than normal stress levels to increase the failure rate
and shorten the time to wearout. There is almost no me·
chanical, environmental, life, or combined stress test for which
accelerated test conditions cannot be achieved. Table Illists
the various tests with recommended directions for acceleration.
The reliability tests of the future will use accelerated testing
techniques that are associated with real-time-control theory to
provide meaningful, quick appraisals and predictions of the reo
liability of solid·state components.
Table III describes some of the most important differences
that exist between the classical form of testing and RTC. The
power and advantages of RTC are clearly visible.
Real·Time Controls
Real-time controls are accelerated tests used to control reo
liability - a design and process parameter. In the real·time
method of determining reliability, a continuous flow of data
is interpolated into established criteria to provide an indication of how well the manufacturing process is producing
Table III -
Table II - Tests and Acceleration Directions
Test
Direction of Stress Acceleration
Mechanical
Lead fatigue
Lead pull
Lead torque
Centrifuge
Impact shock
Vibration
Solderability
Increase bends to package destruction
Increase weight to package destruction
Increase torque to package destruction
Increase G·force
Increase G·force
Equipment limited
Increase preconditioning stress, e.g.,
3 hrs. in steam
Environmental
Moisture resistance/
relative humidity
Salta tmosphere
Temperature cycling
Thermal shock
Life
Operating life
Storage life
Thermal fatigue
Reverse bias
Increase time; use pressure cooker!
autoclave; use moisture with bias
Increase time
Increase cycles; increase I'.T ambient
Increase cycles; increase llT liquid
Increase T junction
Increase T ambient
Increase I'.Tcase; increase cycles
Increase T ambient; increase voltage
product that meets the criteria. By comparing actual to
historical data, changes required in the manufacturing process
to improve the reliability of the product can be made on a day·
to·day basis.
The tests used as real·time controls are selected on the basis
of extensive reliability-engineering work done during the design
Differences Between Classical Group-B Tests and Real·Time Controls
APPROACH
GROUp·B TESTS
REAL·TIME CONTROLS
1. Test Considerations
At maximum device ratings or less
Overstress many times to destruction
2. Overall
General, multi·subgroups,
"shotgun" approach
Specific, predetermined reliability engineering
experimentation necessary, "rifle" approach.
3. Types of Failure
Non-predictable multi· failure modes;
read 6 to 15 electrical parameters
Visually one failure mode; i.e., look for evidence
of one specific failure mechanism. Many times
electrical readings not required.
4. Frequency
Usually once per month
Weekly - Daily - Hourly
5. Product Stage
Completed, electrically tested product
All stages of product
6. Sample Size
Large (approximately 150 per each
subgroups)
Small (approximately 40), taken more
frequently
1. Decisions
Very poor, after the fact
Immediate and Direct
2. Reliability Predictability
Poor, conSidering current low level
Excellent, considering protection from
accelerated conditions
EFFECTIVENESS
failure rates
3. Problem Detection, Feedback,
Corrective Action
Poor
Excellent, qUick response on today's product
with measurable quick evaluation of
corrective action
4. Efficiency of One Test Rack
8 tests/rack/year (1000 hr. test
and down period)
90 tests/rack/year (3 day max.
and 1 day for changing product)
5. Test Duration
Approximately 6 weeks
Minutes to three days maximum
54
_____________________________________________________________ AN-6249
of a new product. Reliability, design, and applications engineers
work together to develop an integrated matrix of mechanical,
electrical, thermal, and environmental stress tests that will
provide information concerning allowable margins of materials,
process, and structure in the manufacturing process. Failure
mechanisms detected during the manufacturing process can
then be continually controlled even though they occur under
accelerated conditions, and the product reliability margin, as
shown in Fig. 2, can be maintained. Very often a two- or
three-day accelerated life test can be used to predict the performance of a product in an actual application over a five-to
~
~
in
,"
It
'
Xl
lC
It
./'
Xx
-
'>
"Xl
ACCELERATED
160
It
'60
0
0
0
X
6.75 W-FAEE AIFc
'40
0
/'
V
/\
",
ACCELERATED
-3"srD:'oEV.
0
r---- r--
i
STANDARD
IBW- HEAT
SINK
r---
, 4.75j- FR EAr
RELIABILITY BOUNDARY
0
~
g t----------:."::P"'PL""""C.:-:T""O"N:-7"l-EVEL
1t
o
and test conditions for real-time control of thermal-cycling
capability of VERSAW ATT transistors. Fig. 3 shows the
"----:N,-'-.-:-OF:-:-U""N'-=T"'5- - - - -
0
10
TIME-MINUTES
23464
Fig. 2 - Curve demonstrating product-reliabUity margin.
seven-year period. For this reason, a major effort is made to
correlate accelerated-test data to use conditions.
Information generated by the RTC method has unquestionable validity because tests are well controlled, and all ambiguties have been removed. Not only is the stress application and
duration known for acceptable product, but, in most cases,
RTC may be used to evaluate and control individual failure
mechanisms. Current as well as historical and projected
operating information is generated for analysis.
12
92CS-2'Z046RI
Fig. 3 - Difference in therma/-cycling tests for the standard-
quality. Group-S method and the accelerated RTC
method.
differences in the thermal-cycling tests for the standardquality, group-B method and the accelerated RTC methodThe thermal·cycling test circuit, Fig. 4, includes an indicator
COMMON
2.
FUSE
TRANSISTOR
UNDER
TEST
Real-Time Control Programs
Thermal Cycling
The first real-time control was developed by RCA to
control the thermal-cycling capability of silicon power transistors in plastic packages. I ,2,3 The thermal-cycling capability
is determined from a system of rating curves which defines
cycle life in terms of power and changes in case temperature.
RTC tests are designed to produce information in three days
for use in process·control. Table IV shows the sampling plan
LAMP
COMMON
92CS-22048
Fig. 4 - The thermal cycle test circuit used to obtain the data in Table IV.
Table IV - Sampling Plan and Test for Real-Time-Control of
VERSAWATT TO-220 Thermal-Cycling Capability
OBJECTIVES
.
I. Provide a Meaningful Control for Critical Thermal-Cycling Capability.
2. Detect Lot·to-Lot Differences.
3. Initiate Corrective Actions and/or Holding Actions.
TEST CONDITIONS AND ACCEPTANCE CRITERIA
Accelerated Thermal Cycling - Free Air, 4.75 W,I'.Tc = 125 0 C, tON = 50 Sec.,
tOFF = 100 Sec., n = 40:
c = 0 @ 1700 cycles, or
c = I @ 3000 cycles
FAI LURES - Check for Opens on Rack, in Addition to Group B Tests End Points
Including Top-Contact and Bottom-Contact Electrical Paramelers.
NOTE: In No Way Does This Real-Time-Control De-Emphasize An Existing
Disciplined And Total In-Process Qu!.Iity-Control Program-From
Incoming Inspection Through Warehousing.
55
AN-6249 ___________________________________________________________
circuit for open-emitter or open-base contacts. The failure-rate
data for VERSAWATT product tested under the RTC accelerated conditions is shown in Table V.
Table V - Failure-Rate Data for 1972 for
VERSAWATT Product Tested Under RTC
No_ of No. of No. Lots No. of Units Per cent Failed
Lots
Units
Failed
Failed
4,150
104
6
0.144
Pull Strength
RTC may be practiced either on a lot-by-lot or shift basis.
For example, each day, 30 samples per shift of power transistors are subjected to the following sequence of tests immediateiy after the soldering of the emitter, base, and collector contacts, Le.,just before the units are plastic encapsulated:
I. Autoclave (121°C, 30 psia, 4 hours)
2. Pull test on emitter-base contacts
The purpose of the autoclave is to age the unprotected
soldered joint so that poor solder contacts are more easily
detected. A typical distribution for the pull-strength test is
shown in Fig. 5. A contact that cannot withstand at least
:!~
J!! 5.
z4B
=>40
~ 32
ci 24
z
I.
e
o
~
~
~
~
~
W
M
The test proceeds as follows:
I. Perform end-point test for hot intermittent opens.
2. Make curve-tracer measurement with power applied; allow
device to heat to 125°C.
3. Criticize data for stability criteria ("jitter").
4. Reject all unstable product and confirm rejects by
failure analysis.
U
~
%
PULL STRENGTH-OUNCES
S2 .5,
::~C.50
Aluminum-Gold Bonding
The aluminum-gold bonding RTC was developed to detect
the failure mechanism of bond lifts in gold bonds caused by
the presence of impurities in the gold. The failure mechanism
occurs after life testing at high temperatures (200°C) without
any apparent force being applied. The test is performed on a
lot basis according to the following sampling plan, test conditions, and procedures:
.
I. Sample size is 15 devices with at least 30 wire bonds, pulltest one half of the wire bonds on each unit.
2. Bake I hour at 390°C.
3. Perform pull-test on remaining wires.
4. Observe number of bond-lift failures.
Fig. 6 is a graphical representation of the results of the
aluminum-gold bonding test is performed on gold-plated parts
for four different lots.
~: .of: ,:~'. ~'u:: ~
.111,
...
20
:
12
14
16
12
56
Conditions
_65°C to 150°C
Cvcles
100
2'
4
6
8
14
16
18?; 20
0
2
4
6
8
(GRAMS)
!z
40
0
LOT A
LOT B
10 ounces of pull is a failure. The autoclave-plus-pull-test
RTC checks only the mechanical strength of the solder joint,
and provides a direct measure of the success of the soldering
process on a real-time basis. Deficiencies discovered as a result
of the pull-strength test are corrected in subsequent shifts.
Sample Size
~20
_BREAK
(GRAMSl
Fig. 5 - A tvpical pull-strength distribution after autoclave at
30psia, T= 121°C. 4 hours.
Wire-Bond Test
A thermal shock test of plastic product using wire bonds
for emitter-base connections is performed weekly, and is very
effective in monitoring a major failure mechanism which
manifests itself as intermittent opens under thermal operation.
The sampling plan and test conditions for the thermal-shock
RTC are as follows:
'8
c:::::JLlFT
~:.O['~I~- ~1l..." ". L'IE~U~n.
J~" J,l.UJ,Ll J,Lu. .,.~12
14
16
18?; 20
a
2
4
6
LOT C
e
(GRAMS)
~ 'or
: : ,"~.,I,.I ."o~~n~.,
g
20
12
14
16
IS?; 20 0
2
(GRAMS)
4
6
LOT 0
8
Dwell Time
30 sec. at each
extreme
Fig. 6 - Bond-pull test results before and after 3900 C bake.
AN-6249
Conclusion
Additional Tests
Additional real-time controls for maintaining the thermalcycling capability of both hermetic- and plastic.packaged
power transistors are shown in Table VI. These tests were
developed because of the success of earlier RTC tests on the
The accelerated tests of the real·time -control method of
realiability determination are invaluable tools in attaining the
most reliable silicon power transistors. These tests, used in
conjunction with or as substitutes for the tests of the Group B
Table VI - Real·Time Thermal·Cycling Test Conditipns
PACKAGE
POWER
(WATTS)
18
TO·220VERSAWATT
4.75
16
TO·3 Hermetic
56
8.5
TO·66 Hermetic
RCA "TOS' Plastic
1.5
1.5
TO·5 Hermetic
Tc(OC)
55
35
40
70
35
35
30
to
to
to
to
to
to
to
TO·220 plastic.packaged silicon power devices. RTC tests have
developed for all silicon power transistors because of demands
for increased reliability by automotive and consumer·product
manufacturers.
RTC Used to Achieve a Higher Reliability Level
Real·time controls not only maintain an acceptable reo
liability level as intended by the design of the product, but,
because they are most often highly accelerated tests that show
the difference in lot capability or margin of acceptability of
the product manufactured, they tend to force the level of
reliability higher. Fig. 7 shows how reliability levels are distri·
buted with and without RTC.
1!1""d
i!
RELIABILITY LEVEL _
RELIABILITY LEVEL_
Fig. 7 - Dis.tribution of reliability levels with and without RTC.
I'.Tc(OC)
110
155
130
120
155
135
lIS
55
125
90
50
120
100
85
ton
toft
HEATSINK
3 min. 3 min.
50s
100s
100s
50s
ISs
25s
50s
100s
60s
90s
60s
90s
30 C/W
Free Air
Free Air
6.3°CfW
Free Air
Free Air
Free Air
or classical method, have been proven more effective than
previous tests or applications·oriented derated conditions in
predicting and assuring reliability levels. The success of the
RTC method is directly related to a complete understanding
of device and manufacturing·process capability.
REFERENCES AND BIBLIOGRAPHY
I. G. A. Lang, B. J. Fehder, W. D. Williams, "Thermal
Fatigue in Silicon Power Transistors", IEEE Trans·
actions on Electron Devices, September, 1970.
2. V. J. Lukach, L. Gallace, and W. D. Williams, "Thermal
Cycling Ratings of Power Transistors", RCA Application
Note AN-4783.
3. L. Gallace, "Quantitative Measurement of Thermal
Cycling Capability of Silicon Power Transistors", RCA
Application Note, AN·6163.
4. L. J. Gallace and J. S. 'lara, "Evaluating Reliability of
Plastic Packaged Power Transistors in Consumer Appli-
cations", IEEE Transactions on Broadcast and Tele·
vision, Vol. BTR·19, No.3, August 1973.
5. D. M. Baugher and L. J. Gallace, "Methods and Test
Procedures for Achieving Various Levels of Power Tran·
sistor Reliability", Proceedings of "Improving Produci·
bility" Workshop, WESCON, September 1973.
6. C. W. Horsting, "Purple Plague and Gold Purity" 10th
Annual Proceedings IEEE Reliability Physics Symposium
April 5·7,1972.
57
OO(]5LJ[]
Power Transistors
Solid State
Application Note
AN-6320
Division
Radiation-Hardness Capability of
RCA Silicon Power Transistors
R. B. Jarl
Because all military systems and weaponry may at one
time be exposed to nuclear radiation, the effects of this
radiation on the electronic system components must be
determined and allowed for in the design. This Note
describes the types of radiation damage that might be
experienced by a power device and the tests used to
determine the design most effective in preventing this
damage.
"RADIATION HARDNESS"
In reality there is no such thing as a "radiation hard"
transistor. A circuit or a device is considered "radiation
hard" for a given application; the criteria is whether the
entire circuit will perform its intended function after being
exposed to a given radiation condition. There are several
levels of nuclear radiation for which equipment is designed.
For example, a hand·carried transceiver is designed for a
radiation level of possibly one thousand times less than the
gnidance electronics in an ICBM warhead because, in its
environment, the transceiver would be destroyed by a
nuclear.weapon blast effect while the radiation level was still
very low. An ICBM, on the other hand, flies outside the
earth's atmosphere; hence, the destructive mechanism might
not be blast effect but, more likely, neutron, gamma, and
X·ray effects from the defensive missile burst. The levels of
radiation from which manned aircraft, weapons stores,
missile launch systems and the like have to be protected lie
somewhere between the levels for the transceiver and the
ICBM.
All transistors suffer degradation in gain, saturation, and
leakage when exposed to nuclear radiation. The problem is to
acquire sufficient knowledge of the transistor behavior after
such exposure to allow the circuit designer to adjust the
design for any undesirable changes that may occur in the
device characteristics. The transistor designer may optimize a
power device for radiation characteristics, but usually at the
expense of its dc operating capability.
DAMAGE CLASSIFICATION
The types of radiation damage that may be inflicted upon
a power device are classified as follows:
I. Physical Damage
2. Displacemen t Damage
3. Transient Radiation Energy Effect (TREE)
4. Ionizing Electromagnetic Pulse Effects (IEMP)
Physical Damage is inflicted on a device by "flash X.rays"
from a nearby nuclear explosion. The X·rays produce a
thermo·mechanical shock·wave in the dense material to
which the transistor die is attached, usually molybdenum,
copper, or gold. This shockwave then propagates into the
transistor die and, if strong enough, will cause visible
fracturing of the device.
Displacement Damage refers to changes in the atomic
structure of the silicon crystal caused primarily by the
disruption of the crystal lattice by impacting neutrons. The
result of this damage is an increased recombination rate in
the base and increased collector·body series resistance. The
combined effect is manifest by a decrease in current gain and
an increase in collector-emitter saturation voltage.
Transient Radiation Energy Effects (TREE) are caused
mainly by gamma rays which produce large numbers of
whole electron pairs in the collector·base and emitter·base
junctions and cause large photo-currents to flow in the
associated circuits. Intense gamma radiation may also cause
current·gain degradation similar to that caused by neutron
exposure, but the effect is modest compared to neutron
effects.
Ionizing Electromagnetic Pulse (IEMP) Effects are the
result of an intense ionization of the surroundings of an
aircraft or space vehicle that produces a voltage gradient over
the hull of several hundred thousand volts. Wherever there is
a gap in the metal skin, such as access doors, windows, or
antenna feedthroughs, the field will redistribute itself and
follow the path of least resistance, possibly down into the
vehicle electronics. Should the IEMP suppression be insuffi·
9·74
58
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ AN-6320
cient, high-current pulses may be induced in the system
electronics. In most cases, the protection of the small signal
and logic circuits will dictate IEMP suppression well below
the capabilities of the power devices. Where a power device
will be exposed to an !EMP condition, a pulsed safe-area test
may be applied to simulate the situation and verify the
device durability.
This Note is confined to the discussion of displacement
damage (neutron effects) and transient-radiation effects
(photocurrents), the main cause of failure of power devices
exposed to nuclear radiation.
r--- SCREEN- - - - '
rEX~1
I
I
I
:
Vcc
I
I
10K
SCOPE
DEVICES TESTED
L. _____ ..::: ___ -1
TABLE I
IRRADIATED POWER-TRANSISTOR SWITCHES
Oescription
Size
(mils)
VCEO
(volts)
fT
(MHz)
2N6479
15A pwr sw.
n-p-n
ISS x ISS
""'60-80
100-140
2N5671
30A pwr sw.
n-p-n
210 x 220
100-140
60-90
2N5038
20A pwr sw.
n-p-n
143 x 182 100-140
70-100
2N3878
7A pwr sw.
n-p-n
103 x 103
60·90
SCOPE
50
Recently, six different RCA power-transistor structures,
as detailed in Table I, were subjected to fission spectrum
Transistor
lOt
ROOM
TRANSISTOR TYPE
Vee (VOLTS)
2N5038-9
55
55
-45
50
50
2N5671-2
2N6247-B
2N5320
2N3878-9
2N6479
VEE (VOLTS)
4
-3
10
92CS-25129
Fig. 1. Circuit and biasing arrangement for measuring photocurrent.
VCEO increased, as did fT (current gain bandwidth
product), while switching times decreased. VBE(sat) increased somewhat but was still very manageable.
It is possible to predict HFE after neutron exposure as a
function of an empirically determined damage coefficient,
KO:
empirically determined damage coefficient, KO:
2N5320
2N6247
KO
IA amp!. & sw. 42 x 42
n-p-n
lOA amp!.
p·n-p
75-110
ISO x 150
70-120
120-180
4-10
neutron exposure and gamma radiation to determine their
tolerance to nuclear and space radiation. Each sample
consisted of 20 units. Except for the 2N6479, which was
designed as a radiation tolerant device, these are standard
commercial power transistors. The devices were evaluated for
tolerance to neutron exposure and primary and secondary
photocurrent generation as a function of gamma·ray intensity. Fig. I shows the circuit configuration and biasing used
in measuring photocurrent.
Neutron Testing
Each unit tested for neutron tolerance received five
fission-spectrum neu tron exposures; the total fluence was
sufficient to produce almost a total degradation in current
gain (HFE>. Before and after each exposure, S·volt, HFE ,
appropriate VCE(sat), VBE(sat), ICBO ' lEBO and switching
speed data were taken. Only HFE and VCE(sat) degradation
showed themselves to be of primary concern. ICBO and
lEBO increased by only small and relatively manageable
amounts.
(I)
or
HFE~
60-80
I
HFE - HFEo
KO+_I_
HFEo
(2)
Where:
Current gain after neutron exposure
HF~
Current gain before neutron exposure
HFEo
Cumulative neutron flue nee
Recombination·rate damage coefficient
KO
(The derivation of Equations I and 2 is given in the
Appendix.) The more common form of this relationship is:
K~_I-)=_I_ _ _
IHFEo
2.. fT HFE~
(3)
The factor 2..1fT ,the gain·bandwidth product, is an
approximation of the base transit time. Eq. 3 works well
with small signal-devices, where fT may be easily and
repeatedly measured at the same collector current and
voltage levels as the other parameters of concern. The
measurement of fT at currents greater than I ampere is
extremely difficult owing to junction-temperature problems.
Furthermore, because of the low output impedances which
exist, and the difficulty of obtaining a load impedance which
must be even lower, the fT results are only qualitative in
59
AN-6320 _____________________________________________________________
nature. The gain-bandwidth product within members of a
given device design are generally uniform; therefore, for this
I
study, 2" fT was merged with K (the recombination-rate
damage coefficient) such that:
-K2" fT
= composite HFE damage cQ€;fficient.
2N6419
5
t6~-H~\~H+~_~I~-H~
1\
I I
b4,J;6-J+-H/-H-tl
i, x~I 5f-+-+++I-+--'<-+++--l2,"N"62
Q~ 4f-+-+++I-+-+~+-1--b~tr+-+~
!;i!!!
1'-,/
~~ 3~~~~~++'2N~5~iI~1/~~~/~~",5~T6~'~~
§o
2N5038~
II
I I
~i ~~=;~2~:3-~f~f:"::~:::;;~:~~~~~~:~/~:2N:i~7;19~
oL-t-~j~,~,IL~=+~~.=+,t,t:i,==.~,+,~~,~l~,~,
0.1
I
COLLECTOR CURRENT (Ie) -
10
AMPERES
100
""-Ff-A.
I
~
."
,
>
.
It).
I
II
*-e
2
5
0
240
1~;4
I'-
3
260
III
I
6
4~~
Figs.2, 3(a) through 3(m),and 4(0) through 4(1) present the
following typical information on the devices tested:
VCE(sat) vs cumulative neutron fluence (41) at a forced
gain of 4 (lclIB=4).
VCE(sat)vs cumulative neutron fluence (41) at a forced
gain of 8 (lclIB=8).
HFE vs IC prior to radiation
Recombination·rate damage coefficient (KO> vs IC.
0.01
7
,,
~
~
I
,
.
"
~
CUMULATIVE NEUTRON FLUENCE (~)- NEUTRONS/cm2
(I MeV EaUIVALENT)
Ib) 2N6479 (lOA)
:~u
:
-
--6 1
'6
'
I
I
~E
4
'"
I
92CM-25130
I
1/
"-
5
4
t
f--j
- - - ---
3~ f----
~
I
-~
'e
2N5672
5~ I---
I 40
! I
613
~
~:4
"'"
-~
,
~
13
CUMULATIVE NEUTRON FLUENCE (cZI)- NEUTRONS/cm 2
II MeV EaUIVALENT)
Fig. 2. Composite graph of recombination-fate damage coefficient as a
~
Ie) 2N5672 13A)
function of collector current for the power transistors
discussed in this Note.
7
260
-.--- - - - -
6
2N6479
""
10'2
"
,
2
-
--
.,
,
10'3
" <--'i
!l<. •• _
.
6 81014
4
NEUTRONS/cm2
o
4
1012
6
8
1013
/
/
., ,
10'4
,
Id) 2N5672110A)
for the power
60
=-Z
"i5
40~
.,,
la) 2N6479 13A)
of cumulative neutron fluence
...
1
""-
~
~
!
CUMULATIVE 'NEUTRON FLUENCE (cZI)- NEUTRONS/cm2
(I MaV EQUIVALENT)
transistolS discussed in this Note.
60
N
..
I 00 Q
60 ..
(I MeV EQUIVALENT)
Fig. 3. Collector-emitter saturation voltage and current gain as a
I 20
-i
/
I
6 8 10'5 0
!£"24
/
~.6/
~FE
"i',
/)
I,
r
16
I
}f-:a
's
CUMULATIVE NEUTRON FLUENCE (cZI) -
function
,,
--- ---
I 40
I
,
I
2
0
_L
HFE
3
I
5
-
2N5612
5
4
>
240 "
2082
a
10'5
Fig. 3. Collector-emitter saturation voltage and current gain as a
function
of cumulative neutron fluence for the power
transistors discussed in this Note.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ AN-6320
,40
2N5038
,
,
20
~:4
:
"
i'
r-- r--
10lZ
~
--
~/
. ""
-
.
.?
,
10"
10
-"-
40
I-
2-
a
,
"
20
~
!
'"
I
CUMULATIVE NEUTRON FLUENCE (~l - NEUTRONS/cm2
(I MeV EQUIVALENT)
~
6
I
I
:'
2N5038
5
I
~=8/
IS ,
3~
............
I
2
5
~
,
.,.
~
60~
.
OJ
I
5 Q.Q
t:i
40-
I
~
30;;
" 1/~=4I
IS
t><
,
>
I
,
,,
4
........... HFE
,
,
--
.
,
20
., ,
~
I-
, a~
0'"
~
~
CUMULATIVE NEUTRON FLUENCE (~)-NEUTRONS/cm2
5-~
HFE
4
'I---, , ,.
_5
0
1012
>
6r--+-~+,H_-+--t-t-H--+---+_H240~
2N3878
:
200~
5r--r------- -
i ::."'==:==:=::::=~+--_--_+-_+_H-r-------t_-----+-_+-_t_lT:::!
~
~
~
2
"""
HFE
80
I-
40
a
Is 41---
1012
4
6
~013
~
I
ri=8
~~Ic
I
g O_~
4
6
810'4
CUMULATIVE NEUTRON FLUENCE (~) -
4
0
6
~
BI015
NEUTRONS/cm 2
(I MaV EQUIVALENT)
(g) 2N3878 (0.3Ai
Fig. 3. Collector-emitter saturation voltage and current gain as a
function
of cumulative neutron fluence for the power
transistors discussed in this Note.
10'3
~~ .
,--
--
, , ,
,
I
,
,
10'4
."
o
IdS
(;) 2N3878 (2Ai
!
a
!~
--l.?
-
6 O~
I
rq
Ie
--
2r---~
>
i
CUMULATIVE NEUTRON FLUENCE (!lII- NEUTRONS/cm2
(I MeV EQUIVALENT)
r--r-,-,-rr-'--'-'-"---'-'-TO,2S0
I
in
, "
70
IS
1\
3-
(I MeV EQUIVALENT)
~
I
~
~
(~l- NEUTRONS/cm 2
:", """1 ,.l/
(f) 2N5038 (lOA)
~
s
,
(hi 2N3878 (IAi
7
,,
!
CUMULATIVE NEUTRON FLUENCE
(I MeV EQUIVALENT)
(e) 2N5038 (3A)
7
~=4
I "- Yl
L
?f
5
0
I
I----~
~=8
~
ldo:,
,'
I
4r-- ~3
g
-
2N3B7B
5
60 ;;
I
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:-- ' - -
, ---
:.
so _
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!£'Slt
IS
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6
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00 :
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5
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5
0
46
-/~I--- -
Bld3
4
6
'it- --
B,o' 4
CUMULATIVE NEUTRON FLUENCE (~l (I MeV EaUIVALENT)
(il
~
I-
~ r--- -/~~,~+
---
>
OJ
:!£;B
IS
4
Id 2
,20
,000:.
80 ;
,t
60;;
;;
40
20
~
a~
4 6 BI01:;0
NEUTRONS/cm 2
2N5320 (0. I A)
Fig. 3. CoJ/ector-emitter saWration voltage and current gain as a
function of cumulative neutron fluence for the power
transistor.; discussed in this Note.
61
AN-6320 __________________________________________________________
:__ ~l
! __ 1-1' ...
-!
I40
2eo
14
>
- - t---
2N6479
20 ..
2N5320
;--. -I'OOa...
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2V
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4
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(ml 2N6248 (SA.
z
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80
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"0
·"
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,
10
AMPERES
ffi
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40 "
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100
280
240 >
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2N503B
200 !;;:
Ii
80
---
t-'
60 -;
~
40
~d4
"
6
W
:I'"
1
8,0'5
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a
a
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.1\
of cumulative neutron f1ue!'ce for the power
160
I--
j
r--..
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"" ----,
· , ·" , ·
.,..'-.
0.01
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f'.- ~Ei
T
i
" 0.1
COLLECTOR CURRENT (Iel -
80
"0
2~ 0
'"
~
z
120 ~
Veli 4A. H FEI
transistors discussed in this Note.
"'
I 6O~
l-
I00 :
Fig. 3. Collector-emitter saturation voltage and current gain as a
function
.---
1
'"
--_. - -- ---
J
14
>
/~=4
IB
Bld 3
-\
"xV
· , , ·"
I 20 ..
-
20
6
2
200 ~
"FE
COLLECTOR CURRENT Uel -
CUMULATIVE NEUTRON FLUENCE (~)-NEUTRONS/cm2
II MeV EQUIVALENT)
62
~
(b12N5672
I
I
I
~
I20 ~
/'
:---0.01
NEUTRONS/cm 2
---
I
~
a
I40
•
.....
frl-:'
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I
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g
7
5
e~
10
AMPERES
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~
2 80
(t) 2N6248 (IAI
g
ffi~
·"
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(I MeV EQUIVALENT)
!:;
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_- t----
~014
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:I'"
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CUMULATIVE NEUTRON FLUENCE (41) -
.,
·
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... !::..,
!:;
i
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,
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COLLECTOR CURRENT (IC' -
,
!:;
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120
~
z
(al 2N6479
.,
~~
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\
2r- l -
!ci
"FE
160
(kl 2N5320 (O.3AI
~:!.
200
1
CUMULATIVE NEUTRON FLUENCE (~l - NEUTRONS/cm2
(I MeV EaUIVALENT)
",
..
240 >
40 "
/
i'--v
.
,
~
~
-
-
V
eo ..
I
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31-- t--
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10
AMPERES
·"
i...
40 "
1
100
(el 2N5038
Fig. 4. Recombination-rate damage coefficient and current gain as a
function
of collector current for the power transistors
discussed in this Note.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ AN-6320
14
I
ffi
8
~
6
~
~ 4
~
~
200
"!:i
w
z
1- - - -
f\
........ ........
,
240>
I 6O~
........
2
0.01
--_ .._.-
1
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-- --
a
2 80
.~- 11
-4
2N3878
"~I 2
"~IO
4
I 20 ~
I){'
Kr
80
---
40 u
.111 ."
,r--
V,
" 10 ,
I
"
COLLECTOR CURRENT lIe) AMPERES
"
0.1
i
>-
4
a
100
(d) 2N3878
Photocurrent Testing
The effect on power transistors of high-intensity radiation, such as high-energy electrons, gamma rays, and X-rays,
is ionization in the collector-base and emitter-base depletion
layers that produces primary photocurrents proportional to
the electrical volumes of the junctions. When these photocurrents flow through the biasing networks and are sufficient
to produce the appropriate IR drops in the circuit extrinsic
to the base-emitter circuit, the device may become forward
biased, producing what is known as "secondary photocurrent" by means of conventional HFE amplification.
Primary photocurrent production is predictable and can be
stated as a coefficient of 6.4 JlA/rad(Si)/cm 3. The expression
for the collector-base photocurrent, Ippc ' may be written as
Ippc = 6.4xlo-6 x A x W
4
I
"'21 2
2N5320
"
~IO
I
J
i
;
I
,
u
I*214
.
0.001
I
1
--r T
-t
,
,
0.01
8
.
240 >
"
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,
I
I
I
280
. iT 200 t:iw
,
j
6
: ! I~
1
>- 8
i5
;;;
,
<
~E
1
160
120 ~
>-
.I!
BO
IKD I I
I
COLLECTOR CURRENT tIcl -
2
ffi
~
40 u
if "- II
0.1
!
z
-.--+
where A is the area of the base in cm 2 and W is the width of
the collector-base depletion layer in centimeters. Note that W
is to some degree voltage dependent; therefore, Ippc will also
be voltage dependent to the extent that me collector
depletion layer widens according to the collector voltage and
the impurity ratio between the base and collector layers.
Fig. 1 shows the circuit used for obtaining the photocurrent data in this Note; it is not entirely satisfactory for
the levels of photocurrent that may occur in large power
devices. Because the photocurrent is measured by monitoring
the voltage across a 50-ohm termination resistor, the
arrangement saturates at a photocurrent of
468
Vii?
thus, the
amount of current measured is not a true indication of Ippc
at the higher exposure levels. The curves of Figs. 5{a)
through 5(1) should be evaluated with this fact in mind;
10
AMPERES
(e) 2N5320
,
4
\
"~I 2
6
280
2N6248
2N6479
4
240 >
1\
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2
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4
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68
0.1
2
468
I
COLLECTOR CURRENT lIe} -
120
468
10
eo
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z
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,
!Z
6-
!5
4
VEE~2
100
AMPERES
(f) 2N6248
/
V
)/
40 u
468
/
VCC~IOV
~
2
/
2
4
6
,
10'
2
4
6
, 10'
DOSE AATE-rnd/Sl/s
92CS-25150
(a) 2N6479
Fig. 4. Recombination-rate damage coefficient and current gain as a
function of col/ector current for the power transistors
discussed in this Note.
Fig. 5. Collector-base photocurrent as a function of dose rate for the
power transistors discussed in this Note.
63
AN-6320 __________________________________________________________
~
:!
:J;;;
I
f3
1000
•
·
••
3'"
4
I
•
I
V
J
/
VEE" 4V
i5
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2
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•
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i
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4
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g;
il
2
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••
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)/
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2
1
I
4
2N5320
4
;;;
/'
2
·
100
~
2N5671
8
107
DOSE RATE - rod/S!./,
/
/
4
/
0.1
4
••
107
DOSE RATE-rod/Sils
92CS-25154
(bl 2N5671
~
;;;
4
••
10·
92CS-25151
fa
ffi
VCC "50 V
VEE'" 4 V
2
(el 2N5320
1000
•
•
S •
•
2N5038
1000
:!
4
I
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4
lJ
2
2N6248
;;;
8:
t:!
2
/
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•
/
/
.5
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4
~~
~V
Vee =55V
VEE =-4V
~
2
I
/
6
8,07
8 loB
6
8
DOSE RATE-rod/Si./a
92CS-25t52
(el 2N5038
••
V
10
••
4
/
Vcc·- 45V
VEE'" -3V
2
•
4
DOSE RATE -
radlSi/s
92CS-25155
Fig. 5. Collector-base photocurrent as a function of dose rate for the
2N3878
power transistof'$ discussed in this Note.
I
••
/
2
:v
/
Vee &50\_
VEE'" 4 V
2
4
• •107
4
••108
2
4
••
DOSE RATE-rodl Sl/s
92CS-25153
(dI2N3B78
Fig. 5. ColltICtor-base photocufTf!fJt as B function of dose rate for the
power transiston discussed in this Nore.
64
/
4
2
(fJ 2N6248
2
••
~
:J
V
••
100
Characterization of the devices tested consisted of
measuring the primary photocurrents in the transistors and
plotting these as functions of radiation dose rate. Tests were
performed at the 25 MeV linear-accelerator facility at the
White Sands Missile Range, New Mexico. Radiation pulse
widths of 5 to 6 microseconds were used to attain
equilibrium photocurrent. All testing was performed with the
accelerator in the electron-beam mode of operation. Variations in dose rate were obtained by positioning the test
device at different distances from the beam port. Dose rates
ranged from about 5 x 105 to 2 x 108 rad(Si)/s and were
determined from the responses of a calibrated diode. The
radiation response of the diode was, in turn, calibrated
against lithium fluoride, Tiny Thermoluminescent DoSimetry
Discs '(TTDD's), and calcil!m fluoride impregnated Teflon
chips, both of which were positioned in the area normally
occupied by the device under test.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ AN-6320
APPENDIX
DERIVATION OF THE
NEUTRON-DAMAGE COEFFICIENT
The photocurrent characteristics of the various devices
evaluated are shown in Table II and described below.
TABLE II
DEVICE PHOTOCURRENT CHARACTERISTICS
Test
No.
2N6479
2N567 I
2N5038
2N3878
2N5320
2N6247
.93
1.2
1.5
.93
.85
.83
....!....
R
HFE
TOTAL GAMMA DOSE
(rads-silicon x 103)
Transistor Type
The common-emitter current gain at a constant voltage
may be expressed as:
2
3
4
5
2.2
2.3
2.7
2.13
2.0
1.68
4.2
3.7
4.1
3.63
3.4
2.68
33.2
26.7
25.1
24.6
32
6.1
79.2
58
38
49.6
73
26.3
2N6479. Relatively linear collector-base photocurrents
were observed. The emitter-base plot was non-linear. Secondary photocurrent began at 3 x 107 radls. The primary
photocurrent generation rates in amperes per rad per second
are:
collector-base
5 x 10-9 Alradls
I x 10- 11 Alradls (approx.) non-linear
emilter-base
2NS671-2. Both the collector-base and emitter-base
junctions exhibit a linear relationship between the photocurrent and the dose rate. However, this transistor type
switched into the secondary-photocurrent mode from 5 x
106 to 2 x 107 radls, so that the points of the emitter plot
are accordingly reduced in quantity. The plot in Fig. 5(b)
yields a primary photocurrent generation rate of:
4.8 x 10-9 Alradls
collector-base
emilter-base
2 x 10-10 Alradls
2NS038-9. Linear relationships between the photocurrent
and dose rate for both collector-base and emitter-base
junctions were obtained. The onset of secondary photocurrent was observed at dose rates of 2 x 107 to 2 x 10 8
radls. The primary photocurrent generation rates taken from
Fig. 5(c) are:
collector-base
3.1 x 10-9 Alradls
emilter-base
6.5 x 10- 11 Alradls
2N3878-9. The collector-base junction shows a linear
relationship between photocurrent and dose rate, whereas
the emitter base is very non-linear. The non-linearity holds
even though data is plotted from 5 x 105 to 108 radls, and
secondary photocurrent did not begin until the dose rate was
3 x 107 rad/s. The primary photocurrent-generation rates
are:
collector-base
2.4 x 10-9 Alradls
emitter-base
I x 10- 11 Alradls (approx.) non-linear
2NS320. Linear results. Secondary photocurrent is not
)bserved for this device for dose rates as high as 3 x 107
·adls. The collector-base photocurrent generation rate is 4 x
10-10 Alradls.
2N6247-8.Linear relationship between pl\Otocurrent and
lose rate for both junctions were seen. Secondary photourrent was observed at about 3 x 107 radls. PrimaryIhotocurrent generation rates are:
collector-base
2.9 x 10-9 Alradls
2.1 x 10- 10 Alradls
emitter-base
I
tb
where:
tb
(A-I)
base transit time
R
base recombination rate
The recombination rate (R) is proportional to the number of
defects produced in the base by neutron radiation. The
number of defects is proportional to the total exposure.
Therefore, R may be expressed as:
R
Ro + K
(A-2)
where:
K
a damage coefficient
total neutron fluenee
The base transit time, (tb), may be approximated by the
relationship:
I
(A-3)
271 fT
Manipulation of Eqs. A-I and A-2 yields the expression:
K
.!.. (_1_ _ _1_)
(A-4)
tb HFEq,+1
HFEo+1
HFE prior to neutron exposure I
HFE after neutron exposure 2
Simplifying,
HFEo + I = HFEo
Eq. A-4 now becomes
K
=1. (_1_ _ _1_)
tb HFEq,+1 HFEo
A reorganization yields:
I +H
(A-5)
(A-6)
= ---,c=-I,-,,-(A-7)
tbK1'+_I_
HFEo
If Eq. A-3 is then substituted in Eq. A-7, the expression
becomes:
(A-8)
FE
As described in the main text, fT and K may be merged as:
271KfT = KD
(A-9)
I + HFEq, is usually expressed as HFEq,' and the expression
becomes:
I
(A-IO)
REFERENCES
I. Larin, Radiation Effects in Semiconductors, pp. 17, eq.
2.19,2.20, John Wiley, New York, 1968
2. Same asref. I, pp. 14, eq. 2.11
3. Rockwell International, Internal letter 73-551-012-79,
October 15, 1973
65
66
High-Reliability
RF Power Transistors
67
High-Reliability RF Power- Transistors
During the past several years, the RCA Solid State
Division has conducted intensive programs to improve
the quality and reliability of rf power transistors. The
significant technological improvements that have resulted from these programs have advanced rf power
transistors to the point that such devices are now used
with confidence in numerous equipments in which high
reliability is a prime requisite.
Design Features
The recent technological advances in RCA rf power
transistors are extensions of the RCA overlay-transistor
concept. Table 3-1 summarizes some of the major design
features of RCA rf power transistors.
Overlay Transistor Structure-The RCA overlay
design, * the basic type of structure used for RCA highreliability rf power transistors, employs a unique emitter
construction that makes possible exceptional powerfrequency capabilities. The emitter is separated into
many discrete sites that are connected in parallel to
provide the increased current-handling capability required at high power levels. This type of emitter structure provides the high ratio of emitter periphery to base
area that is essential to the generation of high power
levels at high frequencies. In addition, the overlay construction makes possible current densities in the emitter mentallizing fingers that are significantly less than
those in other high-frequency transistor structures. The
adverse effect of high current density on transistor reliability, particularly with respect to failures caused by
aluminum migration, is discussed subsequently.
The reduced emitter current density in overlay transistors can be attributed primarily to the relatively broad
metal fingers used to interconnect the discrete emitter
sites. These fingers are typically an order of magnitude
wider than the ones used in interdigitated or mesh types
of transistor structures. In addition, the separation between the emitter and base metallized fingers is 3 to 4
times greater than that in other types of high-frequency
transistor structures. This increased separation permits
the deposition of thicker metallizing layers and, therefore, results in a further reduction in current densities.
Emitter-Site Ballasting-A major technological development in the evolution of rf power transistors is a
unique process in which an integral series resistor is
introduced directly above each emitter site of an overlay
transistor structure. RCA uses this process, which is
referred to as emitter-site ballasting, to achieve rugged
and reliable fine-line precise-geometry rf power transis. tors without sacrifice in high-frequency performance.
In overlay transistors, additional conducting and insulating layers can be readily introduced between the
aluminum metallization and the shallow diffused emitter
sites (shallow emitter diffusion is a requirement for good
microwave performance). RCA has developed a technique in which a polycrystalline silicon layer (PSL) is
interspersed between these regions. This interlayer, the
resistivity of which can be accurately controlled by impurity doping, is used as the medium for the emitter-site
ballasting of RCA microwave power transistors. Fig.
3-1 shows top and cross-sectional views of the emitterfinger structure of an overlay transistor that includes the
polycrystalline silicon layer.
The resistivity of the polycrystalline silicon layer and
the geometry of the contacting aluminum are controlled
to form a ballast resistor in series with each emitter site.
This ballasting has proved very effective in the reduction
of hot spots, i.e., localized heated areas that result when
the emitter-to-collector current is allowed to concentrate
within small regions of the transistor pellet. Such current
concentrations may occur when a large number of transistorelements are interconnected electrically, but are not
coupled thermally. The formation of such hot spots can
result in a regenerative condition that leads to localized
thermal runaway and the consequent destruction of the
transistor .
• U.S. Patent No. 3,434,019, March 18, 1969
Table 3-1 - Design Features
Feature
Overlay structure
Advantages
Reduces current density
Minimizes aluminum migration
68
Emitter-site ballasting
Reduces formation of isolated hot spots
I mproves safe operating area
Improves transistor resistance to failure under high VSWR conditions
Polycrvstalline silicon layer (PSLI
Minimizes "alloy spike" failures
Minimizes dielectric failures
Glass-passivated aluminum metallizing
Minimizes aluminum migration
Hermetic package
Improves resistance to moisture
Re$ults in rugged mechanical construction
Features low inductances and low parasitic capacitances
Provided in both stripline and coaxial configurations
----------------------------
p+ GRID
CROSS SECTION TAKEN THROUGH A
Fig. 3-t-Emitter-finger structure of an overlay transistor that
contains the polycrystalline silicon layer (PSL).
The ballast resistors connected in series with each
emitter site provide internal biasing control to prevent
excessive current in any portion of the transistor. The
formation of hot spots is thereby significantly reduced.
Because the overlay construction results in an emitter
that is segmented into many separate sites connected in
parallel, each hot spot may be isolated and controlled so
that the injection of charge carriers across the transistor
chip is made more uniform.
The emitter-site ballasting results in a more uniform
current distribution and, therefore, makes possible more
effective utilization of emitter periphery. Consequently,
transistor power-output and overdrive capabilities are
increased, and the forward-bias safe-operating area (determined by infrared measurements) is enlarged. This
latter factor is important for linear applications of
high-frequency power transistors.
The formation of transistor hot spots unde( rf conditions increases as the output VSWR increases. Transistor failures caused by high VSWR conditions are often
related to forward-bias second breakdown, which is
characterized by extremely high localized currents.
Emitter-site-ballasted transistors, therefore, have a substantially greater immunity to failure produced by high
VSWR conditions such as those encountered in some
broadband amplifiers. This immunity is particularly demonstrated by the RCA 2-GHz series of microwave
power transistors. For example, the RCA-2N6265,
2N6266, RCA2003, and RCA2005 2-GHz transistors
are characterized to withstand an infinite VSWR at rated
power levels and the specified frequency. Higher-power
types included in the 2-GHz series, such as the 2N6267
and the RCA201Q, are characterized to withstan.d a
VSWR of 10 to I at rated power levels and the specified
frequency.
Polycrystalline Silicon Layer-In addition to its use
as a medium for emitter-site ballasting, the polycrystalline silicon layer (PSL) also helps to minimize two other
thermally induced failure modes that occur in highfrequency power transistors. As shown in Fig. 3-1, this
layer forms a barrier between the aluminum metallization and the shallow diffused emitter region and, therefore, substantially reduces the possibility of "alloy
spike" failures, i.e., emitter-to-base shorts caused by
intermetallic formations of silicon and aluminum that
may occur under severe hot-spot conditions.
The polycrystalline silicon layer also provides a barrier between the aluminum emitter finger and the
silicon-dioxide insulating layer over the base. This barrier minimizes the possibility of emitter-to-base shorts
caused by dielectric failures that result from an interaction between the aluminum and the silicon dioxide.
Recent reliability studies of high-frequency transistors operated under overstress conditions (i.e., at junction temperatures greater than 200°C) demonstrated an
order of magnitude improvement in the mean time between failures for types that contain the polycrystalline
silicon layer over that of similar types in which this layer
is not used. These results verify that the PSL technique
contributes substantially to over-all device reliability and
therefore is an important feature in the construction of
high-frequency power transistors.
Glass-Passivated Aluminum-In RCA rf power
transistors, a silicon dioxide layer is deposited over the
aluminum metallization. This deposition results in an
increase of 40 per cent in the activation energy required
for the initiation of aluminum migration. The mean time
between failure of large crystalline aluminum passivated
in this way is increased by approximately four times at a
current density of I x 10· amperes/centimeter". The silicon dioxide layer also protects the aluminum from contamination and from dam~ge that may result because
of scratches or smears during device assembly.
RC A has recently concluded a study on electronmigration failure mechanisms in rf power transistors.
The RC A-2N6267, a 10-watt, 2-GHz transistor that has
the highest current density of any RCA microwave
power type, was used as the test device in this study. The
median time to failure (MTF) was determined for more
than one-hundred 2N6267 transistors that were dcbiased to simulate high-current-density and highjunction-temperature operating conditions. The effects
of hot-spot junction temperatures over the range from
230°C to 300°C, as determined from infrared scanning,
69
and of current densities in the metallization of I x 10"
amperes/centimeter" to 3 x 105 amperes/centimeter"
were observed. On the basis of the results obtained, the
MTF of the transistors at the typical operating current
density of I x 10' amperes/centimeter and the typical
operating junction temperature of 150°C was predicted
to be 100 years. Even at an operating junction temperature equal to twice the typical value (Le., at 2 x 10'
amperes/centimeter"), an MTF of 12 years is predicted
for operation of the transistors at a junction temperature
of ISO'C. These results indicate that, under normal
conditions, migration failures should not be a factor for
RCA rf power transistors.
Gold Metallization-In some RCA microwave
power transistors, particularly those intended for military phased-array-radar applications, gold metallization
is employed to meet government specifications. These
transistors use a metallization system that was developed
by RCA for a high-volume, high-reliability military
application. In this system, the contacting layer is a
noble-metal, silicide upon which successive layers of
titanium, platinum, and gold are superimposed. Tests of
transistors operated under extreme overstress conditions
(i .e., at current densities equal to twice the typical value
and a hot-spot junction temperature of 285°C) showed
that transistors that use the gold metallization have a
median time to failure 11 times that of transistors with
the same geometry that use glass-passivated aluminum
metallization. The MTF data given in the preceding
paragraph for overlay transistor structures that use
glass-passivated aluminum metallization, however,
show that this type of metallization is more than adequate
for most applications.
Hermetic Transistor Packages-The package of a
power transistor used in microwave applications becomes an integral circuit element that has a critical
bearing on over-all circuit performance. A suitable package for a microwave power transistor should have good
thermal properties and low parasitic reactances. Package
parasitic reactances and resistive losses significantly affect circuit performance characteristics such as power
gain, bandwidth, and stability. The most critical parasitics are the inductances of the emitter and base leads. The
higher the power capabilities of the transistor, the lower
the device impedances, particularly at the input. For
high-power high-frequency transistors, the input impedance is determined primarily by the package, rather
than by the transistor pellet. Consequently, such transistors should be encased in well-designed and wellconstructed packages.
All RCA high-reliability of power transistors are supplied in metal-ceramic or laminated-ceramic packages.
These packages, which are sealed with metallized
ceramic interfaces, provide a true hermetic enclosure
that can withstand thermal cycling from 65°C to
+ 200°C and power cycling such as may be encountered
in transmitter service. In addition, these packages are
mechanically rugged and are essentially impervious to
moisture and other external contaminants.
70
Fig. 3-2 shows photographs of packages used for
RCA high-reliability rf power transistors. These RCA
hermetic transistor packages are specially designed to
have extremely good thermal properties. For example,
in the metal-ceramic packages, such as the HF-II,
HF-21, and HF-28, the transistor pellet is mounted on a
silver block or stud which is connected to the collector
terminal. In the HF-46, a laminated-ceramic package,
the pellet is mounted directly on a beryllium-oxide substrate. In each case, the initial heat spreader, Le., the
silver block or beryllium-oxide substrate, is a material
that has a high thermal conductivity.
The RCA microwave-transistor packages, in addition
to being mechanically rugged hermetic designs with
excellent thermal properties, also have very low values
of parasitic reactances and excellent isolation between
input and output.
·'x
H·13BO
~
I
I
TO·216AA
(HF-191
i
~ II
H1301
,~
I
TO-60
(Ceramic-
TO-S
I
H·1299
Metan
;~.~
T0-39 with Flange
TO-39
TO-72
c'~f
',,.'7.'
HF-28
HF-46
TO-215AA
(HF·lll
H.162~
(j_.
~
,
...
TO-201AA
(HF-211
Fig. 3-2- Packages used for RCA high-reliability rf
power transistors
Special Rating Concepts
Unlike low-frequency high-power transistors, many
rf devices can fail within the dissipation limits set by the
classical junction-to-case thermal resistance during 'operation under conditions of high load VSWR, high collector supply voltage, or linear (Class A or AB) operation. Failure can be caused by hotspotting, which'results
from local current concentration in the acti ve areas of the
device, and may appear as a long-term parameter degradation. Localized hotspotting can also lead to catastrophic thermal runaway.
The presence of hotspots can make virtually useless
the present method of calculating junction temperature
by measurements of average thermal resistance, case
temperature, and power dissipation. However, by use of
an infrared microscope, the spot temperature of a small
portion of an rf transistor pellet can be determined accurately under actual or simulated device operating conditions. The resultant peak-temperature information is
used to characterize the device thermally in terms of
junction-to-case hotspot thermal resistance, IJIs·c.
The use of hotspot thermal resistance improves the
accuracy of junction temperature and related reliability
predictions, particularly for devices involved in linear or
mismatch service.
DC Safe Area-The safe area determined by infrared
techniques represents the locus of all current and voltage
combinations within the maximum ratings of a device
that produce a specified spot temperature (usually
200°C) at a fixed case temperature. The shape of this
safe area is very similar to the conventional safe area in
that there are four regions, as shown in Fig. 3-3: constant
I. MAXIMUM COLLECTOR
CURRENT IIC MAXI
\
1l.OISSIPATION-LiMITEO
\
REGION (POISS'CONSTANTI
\
value. The hotspot thermal resistance (lJIs.c) may be
calculated from the infrared safe area by use of the
following definition:
A
'OJ,g_c' -:-:-:
where TJS is highest spot temperature [TJ(m"l for the safe
area] and P is the dissipated power (= I x V product in
Region II).
The collector voltage at which regions II and III intersect, called the knee voltage VK, indicates the collector
voltage at which power constriction and resulting hotspot formation begins. For voltage levels above YK, the
allowable power decreases. Region III is very similar to
the second-breakdown region in the classical safe area
curve except for magnitude. For many rf power transistors, the hotspot-limited region can be significantly
lower than the second-breakdown locus. Generally VK
decreases as the size of the device is increased.
Fig. 3-4 shows the temperature profiles of two transistors with identical junction geometrics that operate at the
same dc power level. If devices are operated on the
.dissipation-limited line of their classical safe areas, the
profiles sh'ow that the temperature of the unballasted
device rises to values l30°C in excess of the 200°C
rating. Temperatur~s of t~is magnitude, although not
necessanly destructive, senously reduce the lifetime of
the device.
34 5
u
\
If
... 323
...
It:
~
296
0::"
~
...'"
I-
z
6
B
10
Figure 3-3. Safe-area curve for an rf power transistor determined
by infrared techniques.
current, constant power, derating power, and constant
voltage.
Regions I and IV, the constant-current and constantvoltage regions, respectively, are determined by the
maximum collector current and VCEO ratings of the device. Region II is dissipation-limited; in the classical
safe area curve, this region is determined by the following relationship:
where Tc is the case temperature.
This relationship holds true for the infrared safe area;
Pm" may be slightly lower because the reference temperature TJ(m"l is a peak value rather than an average
~
Vee =6.5 VOLTS
P OISS "13 WATTS l - I-TC=IOO"C
UN BALLASTED
26 21r1 I\¥
I
\
205
~AL~ASTEO
180
o
COLLECTOR-TO-BASE VOLTAGE (Vcal-V
T.IS - To
--1-'--
t
10
20
30 40
50 60
(MILSI
t
70
DISTANCE ACROSS PELLET
80
LEFT EDGE
RIGHT EDGE
OF PELLET
OF PELLET
Figure 3-4. Thermal profiles of a ballasted and an unballasted
power transistor during dc operation.
Effect of Emitter Ballasting-The profiles shown in
Fig. 3-4 also demonstrate the effectiveness of emitter
ballasting in the reduction of power (current) constriction. In the ballasted device, a biasing resistor is introduced in series with each emitter or small groups of
. emitters. If one region draws too much current, it will be
biased towards cutoff, allowing a redistribution of current to other areas of the device.
The amount of ballasting affects the knee voltage, VK,
as shown in Fig. 3-5. A point of diminishing returns is
reached as VK approaches VCEO.
RF Operation-In normal class C rf operation, the
hotspot thermal resistance is approximately equal to the
classical average thermal resistance. If the proper collector loading (match) is maintained, IJIs.c is independent of
output power at values below the saturated- or
71
30r----,-----r----,-----,
o ..
0.1,
0.2
0.3 .
0.4
produce maximum collector current. Power level does,
however, influence the temperature rise and probability
of failure.
Device' failure can also occ~r at a load' angle that
produces minimum collector current. Under this condition, collector voltage swing is near its maximum, and
an avalanche breakdown' can result. This mechanism is
sensitive to frequency and power level, and becomes
predominant at lower frequencies because of the decreasing rf-breakdown capability of the device.
TOTAL BALLASTING RESISTANCE-OHMS
Figure 3-5. Safe-area voltage for an rf power transistor as
a function of total ballasting resistance.
'"o
zev
./ . vcc· 26V
~
~
.....- 24V
slumping-power level, and is independent of collector
"';0
"',
supply voltage at values within + 30 per cent of the
~~ 4
/
recommended operating level.
3
Power constriction in rf service normally occurs only
~~
for collector load VSWR's greater than 1.0. A transistor
tIO~.C
that has a mismatched load experiences temperatures far
~
in excess of device ratings, as shown in Fig. 3-6(a) for
0
VSWR = 3.0. Forcoml'arison, the temperature profile
I
3
4
5
for the matched condition is shown in Fig. 3-6(b).
LOAD VSWR
Fig. 3-7 is a typical family of thermal-resistance Figure 3-7. Mismatch-stress thermal characteristics for the
curves that indicate the response of 'a device to various 2N5071.
i~
12
If!
~
Collector mismatch can be caused by the following
conditions:
PELLET DISTANCEIMAJOR AXIS)-INCH
101
~
~170r-'-~--r-'-~--r-'--'
~162r--r-+--~~.,~r--r~
i 1461---t:..""~-:!!!:...-"'--:L-\t---j
~
o1-
132
Billl
I-
~
8301:--'-",*:;--'-;,,*,,-'-....,.,=-,--;:-:(
Ib)
Figure 3-6. Thermal profile of a powertransistar during rf operation: (a) under mismatched conditions; (b) under matched conditions.
levels of VSWR and collector supply voltage. 81s-c
responds to even slight increases in VSWR above 1.0
and saturates at a VSWR in the range of 3 to 6. The
saturated level increases with increasing supply voltage.
Devices with high knee voltages tend to show smaller
changes of 61s-c with VSWR and supply voltage. lhs-c
under mismatch is independent of frequency and power
level, and reaches its highest values at load angles that
72
I. Antenna loading changes in mobile applications
when the vehicle passes near a metallic structure.
2. Antenna damage.
3. Transmission-line failure ,because of line, connector, or switch defects.
4. Variable loading caused by nonlinearinput characteristics of a following transistor (particularly broadband) or varactor stage.
5. Supply-voltage changes that reflect different loadline requirements in class C.
6. Tolerance variations on fixed-tuned or strip line
circuits.
7. Matching network variations in broadband service.
Case-Temperature E:tTects--The thermal resistance
of both silicon and beryllium oxide, two materials that
are ,commonly used in rf power transistors, increases
about 70 per cent as the temperature increases from 25 to
200°C. Other package materials such as steel, kovar,
copper, or silver, exhibit only minor increases in thermal
resistance (about 5 per cent). The over-all increase in
lhs-c of a device depends on the relative amounts of these
materials used in the thermal path of the device; typically
the increase of 61s-c ranges from 5 per cent to 70 per cent.
Fig. 3-8 shows the rfand dc thermal resistance coefficients for a typical rf transistor. "For both cases, the
coefficient is referenced to a 100°C case and is defined as
follows:
frequency = "'T I p, T/ = empirical constant ranging
from 2 to 10, and", = operating frequency
In reality
The rf coefficient changes more than the dc coefficient,
because of the power constriction that occurs in rf operation at elevated case temperature.
1.5 r---,---,---r--.----.
~
2 ?Tfo
1
"'p
I-
"'01'" P is a relationship between the de-
vice transit times (i.e., time constants) and the operating frequency, for example:
Z
2?T
Tp
To
Tp
"'u
H:
l!lu
RF
where
= beta
T
transit time
~gl.Ot-::::;;;;;F---b""'T-.;;Il::---j
=
Ta
e~
and
-'
The ratio'" I "'P' therefore, normalizes the time (duration) of voltage stress to the time of transit of the
device.
Ri0:
'" Q~~O--7~O--9-0--II-O--13LO--'~50
ffi
To
period (time of one cycle)
:I;
....
CASE TEMPERATURE (Tcl -
·c
Figure 3-8. Thermal-resistance coefficient for the 2N5071.
RF Avalanche Breakdown Voltage-The voltage
breakdown mechanism is a time dependent phenomenon; and, therefore, breakdown voltages under pulsed
and rf conditions are higher than the dc values. This is
obviously true when the time during which the device is
subject to fields of breakdown intensity is short with
respect to the mechanislTl.time constant and the off-time
is sufficiently long to permit the relaxation of this
mechanism. Under these conditions, a catastrophic level
cannot be reached during a single pulse, and the accumulative effect of several pulses is prevented by the
off-time relaxation. Tests have demonstrated that a de.vice that has a dc breakdown voltage (BVcHo) of between 60 and 80 volts can often withstand about 135 volts
(collector to base) under pulse lengths shorter than 0.25
microsecond. RF performance (particularly classes B
and C) is analogous to pulsed operation in the sense that
the instantaneous rf voltages are at their peak value for
only a fraction of the cycle. (For example, at 1.3 GHz,
the period of a cycle is 0.77 nanosecond and the voltage
is peaked for less than \4 cycle. Therefore, the highintensity fields exist for less than 0.19 nanosecond.
The increased rf breakdown-voltage capability has
been shown empirically. RF breakdown voltages approximately twice that at low frequencies have been
achieved. One possible theoretical explanation is based
on the following relationship between rf breakdown
and current gain which in effect expresses the relationship at one operating frequency in terms of the alpha and
beta cut-off frequencies of the device.
VCBO(RF)
Veno
{[ 1
+(
:p )
2 ]
X
[1 + 2M ( : p )
The curve of this function is shown in Fig. 3-9. This
curve indicates that a transistor operating at its cutoff
frequency", ,could theoretically have a breakdown voltage equal to six times the dc breakdown voltage. More
typically, two to three times the dc breakdown voltage
has been observed. A further increase in safety factor is
obtained from the fact that the VCE", is greater under rf
conditions because the instantaneous peak voltage is
given by
V inst. = Vcc + (VRF peak)
= Vcc + (Vcc - VCEsat)
= 2 VCC - VCEsat
VCEsat increases with operating frequency; the maximum instantaneous voltage, therefore, is lower at the
higher frequencies further increasing the safety factor .
Both theoretical and empirical evidence support the
contention that rf breakdown voltage can be considerably higher than BVCHO (static). Therefore, reliable
operation can be obtained even though Vcc is more than
one-half BVCHO (static).
VCBO(RFI
eM
where M = "excess phase" factor, '" p = beta cut-off
VCBO(DCl
4
,
.;: to
•
6
.....-
4
,
I
0.01
2 ] } 1/2n
=
-
...........
.....-
6
8
0.1
---6
I.e
8
w/Wt
92C5-22822
Fig. 3-9- Relationship of rf voltage breakdown to dc voltage
breakdown as a function of frequency.
73
Reliability as a Function of Current
Density and Junction Temperature
Questions are frequently asked concerning the iife of
rf power transistors that use an aluminum metallization
system in connection with electromigration-related failure modes. Electromigration of the aluminum has been
shown to occur in the presence of high current densities
and elevated temperatures. This condition results from
the mass transport of metal by momentum exchange
between thermally activated metal ions and conducting
electrons. As a consequence, the original uniform
aluminum film is reconstructed to form thin conductor
regions and extruded appearing hilocks.
The process can be accompanied by the solid-state
dissolution of silicon in the aluminum. This latter effect
usually occurs to a limited extent in transistormanufacturing heat treatments until the aluminumsilicon saturation point is reached. As a result, only a
very small additional amount of silicon dissolves during
normal operation of the device. At high current densities
and elevated temperatures, however, the electromigration process can act to transport the thermally diffused
silicon ions away from the silicon-aluminum interface,
and silicon diffusion into the aluminum is then allowed
to continue until eventually failure of the transistor junctions occurs.
Test Conditions-The effects of electromigration on
the lifetime of RCA rf power transistors in relation to
various current densities and junction temperatures were
evaluated in an accelerated-operating-life test program.
DC current-voltage conditions were used because electromigration is responsive to the de components of the
total wave form used in rf applications, i.e., electromigration is effected by the unidirectional components of
the field. Tests were conducted at three different emitter
stripe currerit densities (.IE). The tests at each current
density, in turn, were conducted at three different peak
junction temperatures (Tj), all of which were accelerated
above normal use conditions. Peak junction temperature
was determined by infrared scanning of the transistor
pellet at each life-test condition. Table 3-2 shows the
matrix of test conditions. The sample size per test condition ranged from 10 to 15 units.
Test Vehicle-The RCA 2N6267 was used as the test
vehicle because it is required to withstand one of the
highest current of densities of any RCA rf power transistor (this transistor, therefore, represents a "worst-case"
candidate). All the transistors used iii the test were
standard-product commercial devices, i.e., they were
not subjected to conventional high-reliability screening
prior to life testing.
Failure Mode-The accelerated test conditions produced failures that resulted from electromigration of
aluminum and silicon. The failure indicator was degradation of the transistor junctions. RF power output
measured at" frequent life-tesl down periods prior to device junction failure exhibited only slight degradation
(typically8%); this degradation is extremely small in
view of the severity of the test conditions.
Test Data-An Arrhenious plot (I/T-Iog scale) of the
log-normal median time to failure (MTF) obtained from
each test is shown in Fig. 3-"10. The curves shown are
extrapolated down from the data points in order to enable
prediction of the MTF at operating junction temperatures below the maximum rated value of 200°C. An
MTF of 9.5 x 105 hours (or greater than 100 years) is
estimated for the 2N6267 test vehicle at its typical application current density of 8.5 x 104 A/em' and junction
temperature of 150°C.
Points from each curve in the Arrhenious plot were
taken in the temperature range of 200°C to 100°C and
replotted on a log-log scale, shown in Fig. 3-11, for
extrapolation over various current densities. Fig. 3-11
represents general curves ofMTF as a function of emitter
current density and peak junction temperature. These
curves can be used to estimate the MTF of an rf power
transistor at its typical operating current density. Table
3-3 lists several RCA transistors designed to operate at
microwave frequencies and shows the predicted MTF of
these devices for typical application values of collector
current, emitter stripe current density, and peak junction
temperature. The microwave transistors are glasspassi vated devices. It has been shown that the MTF of
devices in which the glass passivation is not used is
reduced by a factor of 10. Table 3-4 shows the MTF for
non-glass-passivated rf devices predicted by use of this
acceleration factor.
Table 3-2 Accelerated Llle-Test Conditions
Collector
Current
(A)
1
2
3
Emitter
Current
(A)
1.02
2.07
3.22
Emitter Stripe
Current Density
(A/em')
8.5 x 104
1.7 x 10'
2.7 x 10'
Peak Junction Temperature
In Degrees Centigrade"
TI1
1i2
1i3
300
283
300
280
258
273
154
230
240
.. Represents peak temperature as averaged over several devices at each life--test condition. External heat-sink
size Is adjusted to achieve the differences in junction
lemperalure on Ihe life lest.
74
Table 3-4 - Estimated MTF for Non-Glass-Passivated Devices at
Typical-Application Current Densities.
350
300
~.
250
r-...
Type
" ~""""~'6
200
"~K
v. ..
150
;:'>"'/0" 4 .....,,-71 ...
~>..../0
4/~
C'..,,~
4~"",,,,,
100
50
10
10 2
10 3
105
10 4
•
'-.
107
10
10
,
MEDIAN TIME TO FAILURE (HOURS)
Fig. 3-10-Arrhenious plot showing extrapolation to lower
temperatures from the life-test MTF paints.
10 3
(mAl
JE
(10' amps/cm2)
25
375
1.5
500
50
350
150
600
70
900
1300
85
50
120
480
800
2400
5100
1350
100
MTF 1i = 150·C·
(10' hours)
2.5
2.7
0.72
3.5
5.1
2.4
1.0
2.1
3.8
4.5
3.7
4.6
2.7
5.7
5.7
4.0
7.2
4.8
4.4
5.4
3.5
2.5
15.0
1.3
0.4
2.8
12.0
6.0
1.0
.6
1.2
.58
2.5
0.3
0.3
0.8
0.15
.5
.7
.35
RCA JAN, JANTX, and JANTXV RF Power Tran·
sistors
RCA can supply a number of rf power transistors that
have been qualified as JAN, JANTX, and/or JANTXV
types in accordance with MIL-S-19500. These transistors, together with the MIL-S- 19500 detailed electrical
(slash-sheet) specifications for them, a:e listed below:
46810424681052
46810824681072468108
MEDIAN TIME TO FAILURE (HOURS)
92CS-2Z824
Fig. 3-11- MTF as a function of current density and junction
temperature.Table 3-3 - Estimated MTF for Glass-Passivated RF Power Transistors at Typical-Application Current Densities
MTF (10· Hours)
Type
2N1493
2N2631
2N2857
2N2876
2N3118
2N3375
2N3553
2N3632
2N3866
2N5016
2N5071
2N5090
2N5109
2N5916
2N5918
2N5919A
2N5994
2N6093
2N6105
41024
Typical IE
IE(Amps)
2N5470
2N5920
2N5921
2N6265
2N6266
2N6267
2N6268
2N6269
RCA20li1
0.119
0.180
0.450
0.215
0.540
1.10
0.275
0.920
O:12cr
RCA2003
RCA2005
RCA2010
RCA3001
RCA3003
RCA3005
0.300
0.540
1.10
0.120
0.300
0.540
40915
41039
0.0015
0.030
J. (104A1CM2)
5.2
5.5
3.5
6.5
4.2
8.5
8.3
7.2
3.8
9
4.2
8.5
3.8
9
8
4.2
1i = 150"C
4
3.5
12
2
7
.95
1.5
10
.8
7
.95
10
.8
1.1
7
300
Basic Device Type No.
2N918
2N1493
2N2857
2N3375,2N3553,2N4440
2N3866
2N5071
2N5109
2N5918
2N5919A
Electrical Specification No"
MIL-S-19500/301
MIL-S-19500/247
MIL-S-19500/343
MIL-S-19500/341
MIL-S-19500/398
MIL-S-19500/442
MIL-S-19500/453
MIL-S-19500/473
MIL-S-19500/475
• MIL-S-t9S00 detailed electrical specifications for JAN, JANTX. and
JANTXV devices can be obtained from the Naval Publications and
Forms Center, 5801 Tabor Avenue, Philadelphia. Pa.
RCA HR·Series RF Power TransistorsProcessing and Screening
RCA HR-series types are high-reliability rf and microwave power transistors intended for applications in
aerospace, military,' and industrial equipment. These
transistors are supplied to three screening levels (/1, /2,
/3) which meet the electrical mechanical, and environmental test, methods, and procedures established for
power transistors in MIL-STD-750. Table 3-5 defines
75
these reliability levels in tenns of system-application
usage.
RCA can provide on request SEM (Scanning Electron Microscope) inspection photographs to NASAGoddard Specification GSFC-S-31.1-P-12A· for each
wafer lot tested to level/I. Precap Visual Inspection is
conducted in conformance with Method 2072 of
MIL-STD-750.
Table 3-5- Reliability Levels for RCA High-Reliability RF and MIcrowave Transistor
RCA
Level
II
Application
Satellite and
Aerospace
Description
For devices intended for applications in which mai ntenance
and replacement are extremely difficult or impossible,
and Reliability is imperative.
12
Military and
Industrial (For
example in Airborne
Electronics)
For devices intended for applications in which maintenance
and replacement can be performed, but are difficult and
expensive.
13
Military and
'Industrial (For
example In Ground
Based Electronics~
For devices intended for applications in which replacement
can reljdily be accomplished.
HR-series transistors are available in RCA HF-28
and, HF-46 and JEDEC TO-60, TO-201AA,
to-215AA, TO-216AA TO-5, TO-39, and TO-72
packages. The product-flow diagram shown in Fig. 3-12
lists a summary of processing, screening, tests, and
sampling procedures followed in the manufacture of
these transistors.
Table 3-6 provides detailed information for the
screening tests included in the product-flow diagram.
Table 3-7 gives pre-bum-in and post-bum-in electrical
tests and delta limits for' critical test parameters.
When ordering HR-series types, the appropriate reliability level should be indicated by addition 'of the
suffix /1, /2, or /3 to the type number. For example, the
2N6265 processed to level /3 requirements should be
marked HR2N6265/3.
1'11(;' parameters listed in Table 3-7 are tested before
and after burn-in, and the data are recorded for all devices in the lot. The parameters measured shall not have
changed dunng burn-in trom the milial value by more
than the specified delta (a) limit or beyond the end-point
limits given in Table 3-7.
All devices that exceed these limits are removed from
the inspection lot, and the quality removed are noted in
the lot history. If the quantity removed after burn-in
exceeds 10 per cent of the devices subjected to burn-in,
the entire lot is rejected.
Table 3olj- Description of Total Lot Screening for HR-Serles rf pbwer transistors·
Test
Wafer Lot Identification
SEM Inspection
Precap Visual
Seal and Lot Identification
Stabilization Bake
Temperature Cycling
Centrifuge
Conditions
MIL-STD-7S0 or -202
Method
Condo
X
GSFC-S-311-P-12A.
2072
24 hrs min at
200°C
10 cycles
20,OOOG, y,
direction
Fine Leak
Gross Leak
HTRB (High-Temperature
Reverse Bias)
80% Vce, 150°C min
Serialize
Pre-Burn-in Electrical
Burn-In
See detail Specification
Post-Burn-in Electrical
Final Group A
1051/107C
2006
112
112
* Data on specific HR-Series types given In following pages show test
conditions and limits.
• x ~ 100% Testing; S ~ Sample of 5 (random selection from each
wafer); - ~ not perlormed,
• This specification, which was written by NASA Goddard Space Flight
Canter, is the industry standard.
76
Screening Levels.
II
12
13
CIII
Aor B
S
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Table 3-7- Burn-In Test Measurements
Test
MIL-STD-7S0
Method
Collector
culoff current
3041
Forward-current
transfer ratio
3076
Conditions & Limits
Per
Detailed
Electrical
Specification
tFE
Power output
LEVEL I
Symbol
D. Limits
100% of pre-bum-in value or
10% of Group -A Limit
whichever is greater
± 20% of pre-bum-in value
Pout
LEVEL 2
LEVEL 3
CONDITIONING
SCREENS
BAKE
TEMP. CYCLE
CENTRIFUGE
FINE LEAK
GROSS LEAK
HTRB
92CM-22692RI
Fig. 3-12-Product Flow Diagram for RCA HR-Series rf power transistors (See Tables 3-6 and 3-7 for
additional detailS)
RCA Premium - and Ultra-High-Reliability RF
Power Transistors
trical characteristics. All processes, work instructions, and quality inspections are clearly defined
and documented.
RCA also supplies several transistors referred to as
premium- or ultra-high-reliability types. Processing and
screening requirements and ratings and electrical characteristics for these transistors are included in the technical
data for these types at the end of this section.
2. Maintenance of test equipment and tools kept in
strict compliance with MIL-C-45662, "Calibration System Requirements."
3. Quality Inspection in accordance with MIL-I45208. Specifically, this program incorporates
the following quality inspections:
(a) A thorough inspection of incoming raw parts
and materials.
(b) Wafer-processing visual inspections and
bond-pull tests to check metallization-to-wafer
adherence.
(c) Pellet visual inspection after wafer dicing
(SEM inspection of pellets when required by
purchase order).
(d) Package-assembly visual inspection.
(e) In-process bond-pull test to monitor pellet-topackage adherence.
(f) In-process bond-pull test to monitor integrity of
bond- wire contact.
Quality Assurance Program
In addition to the prescribed screening requirements,
RCA maintains a general Quality Assurance Program
for high-reliability rf transistors which includes the following functions:
I. A system for controlling the conversion of a customer specification into an internal RCA specification which assures complete compliance with
customer requirements. Also, this system provides for control of documentation regarding
changes in design, processes, materials, and elec-
77
(g) Precap visual inspection.
(h) Package cap-seal visual inspection.
(i) Hermeticity (fine and gross) leak-test audit performed after 100% testing.
(j) Group A electrical-test audit performed after
100% testing.
(k) Completed-unit external visual inspection
(I) Group B reliability test sampling from parent
types in accordance with MIL-STD-750 test
methods.
4. Quality-control sampling procedures in accordance with MIL-STD-105 and MIL-S-19500.
78
5. Thorough records kept on all inspections. All data
kept on active file for a minimum of 3 years.
Technical Data
Significant electrical ratings and characteristics and
special features of RCA JAN, JANTX, and JANTXV
rf power transistors; HR-series rf power transistors;
and premium- and ultra-high-reliability rf power transistors are given in the data charts on the following pages.
Silicon Epitaxial Planar VHF Transistor
JAN2N918
JAN Electrical Specifications: MI L-S·19500/301A
Package: JEDEC TO·72
Maximum Ratings
PT
TC - 25°C.!.i
TA-25°C.:J
VCBO
VEBO
VCEO
IC
TJ
mW
mW
--
Vde
Vde
--
Vde
°c
°c
300
--
mAde
200
30
3
15
+200
-65 to +200
-!J Derate linearly 1.71
--
--
Tstg
--
50
mW/oC for TC >25°C.
11 Derate linearly 1.14 mW/oC for TA >25°C.
Primary Electrical Characteristics
hFE
hfe
limits
Ic=3mAde
VCE=l Vde
IC=4 mAde
VCE = 10 Vde
f= 100 MHz
psec
Min
20
6.0
-
Max
200
-
25
'b' Ce
NF
VCE = 6 Vde
IC = 1 mAde
f= 60 MHz
gs = 2.5 mmho
VCB= 12Vde
IC =6.0 mAde
f = 200 MHz
pF
dB
dB
-
-
15
1.7
6.0
-
Cabo
IE = -4.0 mAde
VCB = 10 Vde
VCB = 10 Vde
IE = 0
f = 79.8 MHz 100 kHz';; f';; 1 MHz
GPE
For characteristic curves and test conditions, refer to data on basic type in File No. 83.
Silicon N-P-N VHF Transistor
JAN2N1493
JAN Electrical Specification: MIL-S·19500/247
Package: JEDEC TO-39
Maximum Ratings
pT.!i
VCBO
VCEX
VEBO
ROJC
TJ
.Ji.
Vde
Vde
Vde
°C/W
~
°C
3.5
100
100
4.5
50
+200
-65 to +200
Tstg
llThis power-dissipation rating is for 1,000 hours expected life at TA = +25 0 ±3°C.
Primary Electrical Characteristics
Limits
PG
(at: f = 70 MHz
VCC= 50 Vde
IC= 25 mAde
..!ill..
hfe
f = 70 MHz
VCC = 20 Vde
IC = 15 mAde
VCE = 20 Vde
IE = 10 mAde
-
-
hFE
Min_
10
2.5
50
Max.
-
-
200
_.
Cob
f = 0.1 to 1.0 MHz
VCB= 20 Vde
IE = 0
L
5.0
'b 'Ce
VCC= 20 Vde
IC = 10 mAde
~
100
For characteristic curves and test conditions, refer to data on basic type in File No. 10.
79
Silicon N-P-N Epitaxial
Planar UHF Transistor
JAN2N2857,
J ANTX2N2857
JAN.Eloctrical Specifications: MIL-5-195001343A
Service: For UH F
Package: JEDEC TO·72
Maximum Ratings
..,.U
pT!.i
TA=25'C
TC= 25°C
VCBO
VCEO
VEBO
TA
IC
mW
mW
Vdc
Vdc
Vdc
°c
mAdc
200
300
30
15
3
·65 to +200
40
~ Derate linearly 1.14 mWI"C for TA>2SoC.
1/ Derate linearly 1.71 mW/oC for T 25°C.
11 Derate linearly at 5.71 mW/oC for TA > 25°C.
!I Derate
11 Derate
linearly at 0.066 w/oe for TC
linearly at 0.04
wrC
for TC
> 25°C.
> 25°C.
Primary Electrical Characteristics
Limits
VCE(sat)!.l
Ic=500mAdc
IC= 250 mAde
IB = 100 mAde
IB=50mAdc
2N3375
2N4440
2N3553
Vdc
Cobo
IE=O
VCB=30Vdc
100kHz 2SoC.
Primary Electrical Characteristics
hFE
limits VCE = 5.0Vdc
IC =50 mAde
Ihfel
VCE = 15 Vdc
Ic=50mAdc
f=200 MHz
Cobo
VCB=2SVdc
IE=O
100 kHz';;;f';;; 1 MHz
pF
VCE(sat)
IC= 100 mAde
IB= 10 mAde
POE
VCC=2SVdc
PiE =0.15W
f=400 MHz
POE
VCC=2SVdc
PIE =0.075W
f= 400 MHz
15
-
Y:!.
2.5
Vdc
--
W
Min
1.0
0.5
Max
200
8.0
3.0
1.0
2.0
-
For characteristic curves and test conditions, refer to data on basic type in File No. 80.
Silicon N-'-N Emitt.....Ballast.d
Ov.rlay VHF Transistor
JAN2N5071,
JANTX2N5071
JAN Electrical Specification: MIL-S-19500l442
Package: JEDEC TO·GO
Maximum Ratings
pT!I
PTY
TA = 25DC
TC = 25°C
.-
W
W
2.6
VCEO
VEBO
VCEX
IC
-
Vdc
--
Vdc
Adc
70
35
TOter.
Tstg.
-
Vdc
!l Derate linearly at 15 mW/oC for TA >2SoC
-
4
65
.Y Derate
-10
linearly at 400 mW/oC for T
DC
-
-65 to
+200
c> 2SoC
Primary Electrical Characteristics
Limits
hFE
VCE =5 Vdc
IC = 3 Adc
Min.
Max.
15
100
Cobo
VCB=30Vdc
IE=O
. lQOkHz';;;f';;;lMHz
~
85
POE
PIE =3W
f = 76 MHz
VSWR
f = 30 MHz
POE = 30W
W
24
34
°CIW
3:1
All Phases
For characteristic curves and test conditions, refer to data on basic type in File No. 269.
82
ROJC
2.5
Silicon N-P-N Overlay
VHF-UHF Transistors
JAN2N5109,
JANTX2N5109
JAN Electrical Specification: MIL-S·19S00/453
Package: JEDEC TO-39
Maximum Ratings
PT.!./
TA = 25°C
W
.-
VCBO
VEBO
VCEO
VCER
Ic
Tstg
TJ
Vdc
Vdc
Vdc
--
Vdc
Adc
--
°c
~
40
3.0
20
40
0.4
·65 to +200
+200
-- --
1.0
-
Primary Electrical Characteristics
hFE
Ihfel
Cobo
VCE(sat)
VCE = 15 Vde
IC =50 mAde
VCE = 15 Vde
IC = 50 mAde
f = 200 MHz
VCB = 28 Vde
IE=O
100 kHz';;f';; 1 MHz
IC = 100 mAde
IB = 10 mAde
Min
40
6.0
-
Max
120
9.0
3.5
Limits
Z
..
For-characteristic curves and test conditions, refer to data on baSIC type
In
Gpe
VCE = 15 Vde
PIE = 10 dBM
IC = 10 mAde
f = 200 MHz
Vdc
dB
-
11.0
0.5
-
File No. 281 .
Silicon N-P-N Emitter-Ballasted
VHF-UHF Transistor
JAN2N5918JAN Electrical Specification: MIL-S-19500/473
Package: JEDEC TD·216AA
Maximum Ratings
pT.!.I
PT:oJ
TA = 25°C
TC = 75°C
W
-W
2.4
TJ
IC
VCEO
VEBO
VCEX
Vde
Vdc
Vdc
Adc
~
30
4
60
0.75
·65 to +200
10
.!J Derate linearly 13.7 mW/oC for TA>2SoC
!l Derate linearly 80 mW/oC for TC >7SoC
Primary Electrical Characteristics
Limits
VCE(sat)
hFE
Ic=2Ade
IB=400 mAde
VCE=4Vde
IC=O.S Ade
Vdc
Cobo
VCB=30Vde
IE = 0
100 kHz ';;f';; 1 MHz
POE
PIE = 1.S9W
f= 400 MHz
pF
-W
Min
-
15
-
10
Max
-
200
13
13
For characteristic curves and test conditions, refer to data on basic type in File No. 448.
83
JAN2N5919A
JANTX2N5919A
JAN Electrical Specifications:
Service: For UHF
Package: JEDEC TO-216AA
Maximum Ratings
..,.'
TA = 25°C
Silicon N-P-N Emitter-Ballasted
Overlay -VHF/UHF Transistor
MIL.s~195001475
..,.2
TC = 25°C
VCEO
VEBO
VCEX
IC
W
Y:L
Vdc
Vdc
Vdc
Adc
2.6
25
30
4
65
4.5
, Derate linearlv 15 mWFC for TA
TA
~
-65 to +200
>25°C.
2 Derate linearly 200 mW/oCfor TC >75°C.
Primary Electrical Characteristics
Limits
VCE!S.t)
IC = 2 Adc
IB = 400 mAde
Vdc
hFE
VCE = 4 Vdc
IC=0.5 Ade
Min
--
to
Max
2
200
Cabo
VCB = 30 Vde
IE = 0
100 khz <;;;t.;; 1 MHz
Pout
Pin = 4 W
f = 400 MHz
L
16
22
22
For characteristic curves and test conditions, refer to data on basic type in File No. 505.
84
W
--
RF Power Transistors
ffil(]5LJD
Solid State
Division
HR2N2857
Silicon N-P-N Epitaxial
Planar Transistor
For UHF Applications in Industrial
and Military Equipment
Features:
" High gain-bandwidth product fT ~ 1000 MHz min_
JEDEC TO-72
H-1299
" High converter (450-to-30-MHz) gain Gc ~ 15 dB typ_ for circuit bandwidth of
approximately 2 MHz
The RCA-HR2N2857 is a high-reliability version of the
RCA-2N2857 _ It is specially processed and screened for
high reliability in accordance with the basic schedules outlined earlier in the discussion of Processing and Screening of
HR-Series High-Reliability Transistors_ The maximum ratings, specific electrical (Group A) tests and test limits, and
the burn-in conditions for the HR2N2857 are shown below_
The basic electrical-characteristics curves and test conditions and the mechanical details for this device are the
same as those given for the basic 2N2857 transistor in RCA
data bulletin file No_ 61.
" High·power gain as neutralized amplifier Gpe ~ 12_5 dB min_ at 450 MHz for circuit
bandwidth of 20 MHz
" High power output as uhf oscillator p ~ {3D mW min., 40 mW typ_ at 500 MHz
a
20 mW typ., at 1 GHz
a Low device noise figure NF ~{4_5 dB max_ as 450 MHz amplifier
7_5 dB typ_ as 450-to-30-MHz converter
" Low collector-to-base ti me constant rb'Cc~7pstyp_
" Low collector-to-base feedback capacitance Ccb ~ 0.6 pF typo
'- MAXIMUM RATINGS,Absolute-Maximum Values:
COLLECTOR-TO-BASE VOLTAGE ............. _.......................... .
COLLECTOR'TO-EMITTER VOLTAGE .. _..... ___ ..... _.................. _.
EMITTER-TO-BASE VOLTAGE ........................ _.. _.... _......... .
COLLECTOR CURRENT ............... _.......................... _..... .
TRANSISTOR DISSIPATION:
At case temperature up to 250 C .................... __ ........... _...... .
At case temperatures above 25 0 C ............... _ ... _.................. _ .
At ambient temperatures up to 25 0 C
At ambient temperatures abovr 25 0 C .................................... .
TEMPERATURE RANGE:
Storage and operating (Junction) ............. __ ........................ .
LEAD TEMPERATURE (During Soldering):
AtdistancesL 1/32 in. from seating surface for 10 s max ......... _.... _...... .
VCBO
VCEO
VEBO
IC
PT
30
15
2.5
40
V
V
V
rnA
300
mW
Derate at 1.72 mW/oC
200
mW
Derate at 1. 14 mWlaC
-65 to +200
oC
265
oC
85
HR2N2857 _________________________________________________________
II. GROUP A TESTS, at Ambient Temperature (TAJ = 2fjO C
TEST CONDITIONS
CHARACTERISTIC
Svmbol frequency
I
MHz
Collector Cutoff Current
Collector-ta-Base
Breakdown Voltage
BVCBC
Collector-ta-Emitter
Breakdown Voltage
BVCEC
Emitter-ta-Base
Breakdown Voltage
BVEBC
Static Forward Current
Transfer Ratio
hFE
Small-Signal Forward
Current Transfer Ratio
hie
Collector-ta-Base
DC
Emitter-
DC
to-Base
Voltage
Voltage
Voltage
Emitter
Current
VCB
VCE
VEB
IE
V
V
V
mA
DC
Base
DC
Colloe·
tor
Current
Current
IB
IC
mA
mA
0
-0.01
O.OO1c
looc
Feedback Capacitance
Ccb
0.1 to Ib
rb'Cc
31.9c
Small-Signal CommonEmitter Power Gain in
Neutralized Amplifier
Circuit
Gpe
450c
Units
Min.
Max.
-
10
0.001
30
-
V
3
15
-
V
-
V
0
0
Collector-ta-Base Time
Constant
Power Output as Oscil·
DC
Col lectorto-Emitter
15
ICBO
LIMITS
DC
Collector·
to-Base
0
2.5
1
3
30
150
6
6
2
5
50
10
220
19
nA
10
0
-
1.0
pF
6
-2
4
15
ps
12.5
19
dB
6
1.5
Po
;;'5000
30
-
mW
Figure
NF
45OC. d ,f
6
1.5
-
4.5
dB
UHF Measured Noise
Figure
NF
45OC. d
6
1.5
-
5.0
dB
lator
UHF Device Noise
a
10
-12
Fourth lead (case) not connected .
. b Three-terminal measurement: Lead No.1 (Emitter) and lead No.4 (Case) connected to guard terminal.
c
Fourth lead (case) grounded.
d
Generator resistance Rg = 50 ohms.
e
Generator resistance Rg = 400 ohms.
Device noise figure is approximatelv 0.5 dB lower than the measured noise figure. The difference is due to the insertion loss at the input of
the test circuit (0.25 dB) and the contribution of the following stages in the test setup (0.25 dB).
"'Recorded before and after burn-in for each device (serialized).
III. BURN·IN CONDITIONS
TA=250 C
VCB= 15V
PT=O.2W
86
RF Power Transistors
OOCIBm
Solid State
Division
HR2N3375
Silicon N-P-N Overlay Transistor
For VHF/UHF Applications
Features:
II
JEDEC TD-60
H-1307
..
..
..
"
..
7_5 W (MIN) output at 100 MHz Class C
3_0 W (MIN) output at 400 MHz Class C
2_5 W (Typ) output at 500 MHz. Oscillator
High Voltage Ratings
Hermetic stud-type package
All electrodes isolated from stud
The RCA-HR2N3375 is a high-reliability version of the
RCA-2N3375_ It is specially processed and screened for high
reliability in accordance with the basic schedules outlined
earlier in the discussion of Processing and Screening of
HR-Series High-Reliability Transistors_ The maximum ratings.
specific electrical (Group A) tests and test limits. and the
burn-in conditions for the H R2N3375 are shown below_ The
basic electrical-characteristics curves and tes.t conditions and
the mechanical details for this device are the same as those
given for the basic 2N3375 transistor in RCA data bulletin file
No_ 386_
I. MAXIMUM RATINGS. Absolute-Maximum Values:
COLLECTOR-TO-BASE VOLTAGE ___________________________ _
65
v
VCEV
65
v
40
V
EMITTER-TO-BASE VOLTAGE _____________________________ _
VCEO
V EBO
4
V
CONTINUOUS COLLECTOR CURRENT
IC
0_5
A
TRANSISTOR DISSIPATION:
PT
VCBO
COLLECTOR-TO-EMITTER VOLTAGE:
With external base-to-emitter voltage VBE = -1.5 V _____________ _
With base open _________________________________________ _
At case temperatures up to 25°C
At case temperatures above 25°C ___________________________ _
TEMPERATURE RANGE:
Storage and Operating (Junction) ___________________________ _
11.6
Derate linearly at
0_066
W
W/Dc
-65 to +200
DC
230
DC
LEAD TEMPERATURE (During soldering):
At distances;;' 1/16 in_ (1_58 mm) from insulating wafer for 10 s max_
87
HR2N3375 ______~-----------------------------------------------II. GROUP A TESTS. At Case Temperature (TC) = 25°C.
STATIC
SYMBOL
CHARACTERISTIC
VCR
Collector-Cutoff Curren!
TEST CONDITIONS
DC
DC
Current
Base
(Milliamperes)
Volts
DC
Collector
Volts
ICEO
VCE
30
VBE
IE
LIMITS
-
Max.
_1
mA
0_1
65
-
V
o to 200"
o to 200"
4()b-
V
65b
-
0
4
-
V
500
-
1
V
150
10
-
IB
0
IC
0
Min.
UNITS
Collector-to-Base
Breakdown Voltage
Collector-to-Emitter
Breakdown Voltage
0
V(BR)CBO
V(BR)CEO
-1.5
V(BRICEV
V
Emitter-to-Base
Breakdown Voltage
0_1
V(BR)EBO
Collector-to-Emitter
·Saturation Voltage
100
VCE(sat)
DC Forward Current
Transfer Ratio
5
hFE
DYNAMIC
CHARACTERISTIC
SYMBOL
DC
Collector
Volts
VCB
Collector-to-Base Capacitance
Measured at 1 MHz
Cobo
TEST CONDITIONS
DC
DC
Current
Base
(Milliampere.)
Volts
VCE
30
VBE
IE
0
RF Power Output
Amplifier. Unneutralized
At 100 MHz
28
IB
IC
LIMITS
UNITS
Min.
Max.
-
10
7_5<
W
POE
400 MHz
-BPulsed through an inductor (25 mH); duty factor
28
=50%.
bMeasured at a current where the breakdown voltage is a minimum.
cFor Pie = 1.0 W;minimum efficiency 65%.
d For PIE =1.0W minimum efficiency 40%.
-Recorded before and after burn-in for each device (serialized).
III. BURN-IN CONDITIONS
TA = 25°C
V CB =30V
PT =2_6W
88
pF
3_ad
-
RF Power Transistors
OO(]5LJI]
Solid State
Division
HR2N3553
Silicon N-P-N Overlay Transistor
For VHF/UHF Applications
R
TIT
Features:
JEDEC TO·39
H-13B1
• 2.5 W (MIN) output at 175 MHz, Class C Amplifier
• 1.5 W (Typ) output at 500 MHz, Oscillator
• High Voltage Ratings
The RCA·HR2N3553 is a high·reliability version of the
RCA·2N3553. It is specially processed and screened for high
reliability in accordance with the basic schedules outlined
earlier in the discussion of Processing and Screening of
HR·Series High·Reliability Transistors. The maximum ratings,
specific electrical (Group A) tests and test limits, and the
burn·in conditions for the HR2N3553 are shown below. The
basic electrical·characteristics curves and test conditions and
the mechanical details for this device are the same as those
given for the basic 2N3553 transistor in RCA data bulletin file
No. 386.
I. MAXIMUM RATINGS,Absolure-Maximtim Values:
COLLECTOR·TO·BASE VOLTAGE ............................ .
VCBO
65
v
COLLECTOR·TO·EMITTER VOLTAGE:
= -1.5 V .............. .
VCEV
65
v
With base open .......................................... .
40
V
EMITTER·TO·BASE VOLTAGE .............................. .
VCEO
V EBO
CONTINUOUS COLLECTOR CURRENT ........................ .
IC
TRANSISTOR DISSIPATION:
PT
With external base·to·emitter voltage V BE
At case temperatures up to 25°C
At case temperatures above 25°C ............................ .
4
V
0.33
A
7
Derate linearly at
0.04
W
W/oC
TEMPERATURE RANGE:
Storage and Operating (Junction) ............................ .
-65 to +200
°c
230
°c
LEAD TEMPERATURE (During soldering):
At distances;;' 1/16 in. (1.58 mm) from seating plane for 10 s max.
89
HR2N3553
II. GROUP A TESTS. At Case Temperature (TC) = 25°C.
STATIC
SYMBOL
CHARACTERISTIC
VCB
Coliector·Cutoff Current
TEST CONDITIONS
DC
DC
Current
Base
(Milliamperes)
Volts
DC
Collector
Volts
ICEO
V CE
30
IE
"BE
UNITS
LIMITS
IB
IC
0
Min.
Max.
-
.1
mA
V
Coliector-to·Base
Breakdown Voltage
Collector-to-Emitter
Breakdown Voltage
0
V(BR)CBO
0
V(BR)CEO
-1.5
V(BR)CEV
0.3
65
-
o to 200·
o to 200'
40D
65b
-
V
0
4
-
V
250
-
1
V
150
10
-
V
Emitter-to·Base
Breakdown Voltage
0.1
V(BR)EBO
Collector-ta-Emitter
Saturation Voltage
50
VCE(sat)
DC Forward Current
Transfer Ratio
5
hFE
DYNAMIC
CHARACTERISTIC
SYMBOL
DC
Collector
Volts
VCB
Collector-to-Base Capacitance
Measured at 1 MHz
R F Power Output
Amplifier. Unneutralized
At 175 MHz
Cobo
TEST CONDITIONS
DC
DC
Current
Bas.
(Milliamperes)
Volts
VCE
POE
28
8pulsed through an inductor (25 mHl; duty factor:::: 50%.
bMeasured at a current where the breakdown voltage is a minimum.
cFor PIE = 2.5 W; minimum efficiency = 50%.
III. BURN-IN CONDITIONS
TA = 25°C
V CE 30 V
PT =lW
=
90
IE
0
30
·Recorded before and after bum-in for each device (serialized).
V BE
IB
IC
LIMITS
Min.
Max.
-
10
2.5<
UNITS
pF
W
RF Power Transistors
DClOBLJD
Solid State
Division
HR2N3632
Silicon N-P-N Overlay Transistor
For VHF Applications
Features:
JEDEC TO-60
H-1307
•
a
"
"
"
13.5 W (MIN) output at 175 MHz Class C
10.0 W (Typ) output at 260 MHz Class C
High Voltage Ratings
Hermetic stud·type package
All electrodes isolated from stud
The RCA-HR2N3632 is a high·reliability version of the
RCA·2N3632. It is specially processed and screened for high
reliability in accordance with the basic schedules outlined
earlier in the discussion of Processing and Screening of
HR·Series High·Reliability Transistors. The maximum ratings,
specific electrical (Group A) tests and test limits, and the
burn·in conditions for the HR2N3632 are shown below. The
basic electrical·characteristics curves and test conditions and
the mechanical details for this device are the same as those
given for the basic 2N3632 transistor in RCA data bulletin file
No. 386.
I. MAXIMUM RATINGS, Absolute-Maximum Values:
VCBO
65
v
VCEV
VCEO
V EBO
65
v
CONTINUOUS COLLECTOR CURRENT
IC
TRANSISTOR DISSIPATION:
PT
COLLECTOR·TO-8ASE VOLTAGE ........................... .
COLLECTOR·TO-EMITTER VOLTAGE:
With external base-to-emittervoltage V8E = -1.5 V .............. .
With base open .......................................... .
EMITTER-TO-BASE VOLTAGE .............................. .
At case temperatures up to 25°C
At case temperatures above 25°C ............................ .
40
V
4
V
1.0
A
23
Derate linearly at
0.13
W
W/oC
TEMPERATURE RANGE:
Storage and Operating (Junction) ............................ .
-65 to +200
°c
230
°c
LEAD TEMPERATURE (During soldering):
At distances;;;' 1/16 in (1.58 mm) from insulating waferfor 10 s max.
91
HR2N3632
II. GROUP A TESTS. At Case Temperature (TC) = 25°C.
STATIC
CHARACTERISTIC
SYMBOL
VCB
Coliector·Cutoff Current
TEST CONDITIONS
DC
DC
Base
Current
(Milliamperes)
Volts
DC
Collector
Volts
VCE
V BE
IE
IB
30
ICEO
LIMITS
IC
Min.
0
' UNITS
Max.
0.25
mA
V
Coliector·to·Base
Breakdown Voltage
V(BR)CBO
Collector·ta-Emitter
V(BR)CEO
Breakdown Voltage
V(BR)CEV
0
0
-1.5
0.5
65
-
Oto 200'
-
V
o to 200'
40D
65b
0
4
-
V
500
-
1
V
300
10
-
V
Emitter·to·Base
Breakdown Voltage
.25
V(BR)EBO
Collector·to·Emitter
Saturation Voltage
100
VCE(sat)
DC Forward Current
Transfer Ratio
5
hFE
DYNAMIC
TEST CONDITIONS
CHARACTERISTIC
SYMBOL
DC
Collector
Volts
VCB
Collector-to-Base Capacitance
Measured at 1 MHz
R F Power Output
Amplifier, Unneutralized
At 175 MHz
260 MHz
Cabo
POE
VCE
30
III. BURN·IN CONDITIONS
PT =2.6W
92
V BE
DC
Current
(Milliamperes)
IE
0
IB
IC
LIMITS
Min.
Max.
-
20
28
13.5c
28
10d
aPulsed through an inductor (25 mH); duty factor = 50%.
bMeasured at a current where the breakdown voltage is a minimum.
c For PI E ::: 3.5 W; minimum efficiency = 70%.
dFor PtE'" 3.0 W; typical efficiency "" 60%.
*Recorded before and after burn-in for each device (serialized},
TA = 25°C
V CB =30V
DC
Base
Volts
UNITS
pF
W
RF Power Transistors
OO(]5LJ1]
Solid State
Division·
HR2N3866
Silicon N-P-N Overlay Transistor
High·Gain Driver for VHF/UHF Applications
in Military and Industrial Communications Equipment
Features:
• High power gain, unneutralized Class C amplifier
l·W output at 400 MHz (10-dB gain)
l·W output at 250 MHz (15-<1B gain)
l·W output at 175 MHz (17-dB gain).
JEDECTO·39
H·1391
l·W output at 100 MHz (20·dB gain)
The RCA·HR2N3B66 is a high·reliability version of the
RCA·2N3B66. It is specially processed and screened for
high reliability in accordance with the basic schedules outlined earlier in the discussion of Processing and Screening
of HR-5eries High-Reliability Transistors. The maximum
ratings, specific electrical (Group A) tests and test limits,
and the burn· in conditions for the HR2N3866 are shown
below. The basic electrical-characteristics curves and test
conditions and the mechanical details for this device are
the same as those given for the basic 2N3B66 transistor in
RCA data bulletin file No. 80.
.. Low output capacitance
Cobo = 3 pF max.
I. MAXIMUM RATINGS,Absolute-Maximum Values:
COLLECTOR·TO·BASE VOLTAGE ........................................ .
COLLECTOR-TO·EMITTER VOLTAGE:
With external base-to·emitter resistance, RBE = 10 n ........................ .
With base open ...................................................... .
EMITTER·TO-BASE VOLTAGE ........................................... .
CONTINUOUS COLLECTOR CURRENT ................................... .
CONTINUOUS BASE CURRENT .......................................... .
TRANSISTOR DISSIPATION:
At case temperature up to 250 C ........................................ .
At case temperatures above 250 C ....................................... .
TEMPERATURE RANGE:
Storage and Operating (Junction) ........................................ .
LEAD TEMPERATURE:
Atdistances2.1/16 in. (1.5B mm) from seating plane for 10 s max .............. .
VCBO
55
V
VCER
VCEO
VEBO
IC
IB
PT
55
30
3.5
0.4
0.4
V
V
V
A
A
5
Derate at 0.0286
W/oC
-65 to +200
oc
230
oc
W
93
HR2N3866 ___________________________________________________________
II. GROUP A TESTS, at Case Temperature (Tcl
=250 C
STATIC
TEST CONDITIONS
CHARACTERISTIC
SYMBOL
DC
CURRENT
(mA)
DC
VOLTAGE
(V)
VCE
VEB
1.5
IE
IB
LIMITS
UNITS
MIN.
IC
MAX.
Collector Cutoff Current:
Base-emitter junction reverse biased
ICEX
55
Base open
ICEO
28
ColiectoHo-Base Breakdown Voltage
-
0.1
mA
-
20
IlA
0.1
55
-
5
30
-
5
55
0
3.5
0.1
mA
100
-
1.0
V
50
10
200
-
35
0
0
V(BR)CBO
V
Coliector-to·Emitter Breakdown Voltage:
With base open
0
V(BR)CEO
V
With base connected to emitter
through 1fX»hm resistor
0
V(BR)CER
Emitter-ta-Base Breakdown Voltage
V(BR)EBO
Emitter-Cutoff Current
lEBO
Collector-to-Emitter Saturation Voltage
VCE(sad
DC Forward-Current Transfer Ratio
hFE
Thermal Resistance (Junction-to-Case)
ROJC
0.1
3.5
20
5
V
OC/W
DYNAMIC
TEST AND CONDITIONS
SYMBOL
Power Output (VCC = 28 V):
PIE =0.1 W
Large-5ignal Common-Emitter Power Gain (Vee
::z
FREQUENCY
MHz
LIMITS
UNITS
MIN.
MAX.
POE
400
1.0
-
W
GpE
400
10
-
dB
'1C
400
45
-
%
Ihl.1
200
2.5
-
Pi
400
-
0.1
28 V):
PIE=O.IW
Collector Efficiency (Vee - 28 VI:
PIE =0.1 W, POE = 1 W,Source Impedance = 50
n
Magnitude of Common-Emitter. Small.signal. Short-Circuit
Forward-Current Transfer Ratio:
IC
=50 mAo VCE = 15 V
Available Amplifier Signal Input Power, POE
Source Impedance "" 50
n
= 1 W.
Common-Base Output Capacitance (VCS = 28 V)
*Recorded before and after burn-in for each device (serialized).
III. BURN·IN CONDITIONS
TA=25 0 C
VCB =28V
Pr= 1 W
94
Cabo
1
3
W
pF
RF Power Transistors
OO(]5LJ[]
Solid State
Division
~1 d
'·~·~~~"
HR2N5071
24-W (CW), 76-MHz EmitterBallasted Overlay Transistor
r~·'"""
T
,--
Silicon N-P-N Device for 24-Volt Applications
~
in VHF Communications Equipment
::>
Features:
:;t:
•
For class B or class C am plifiers
•
For 24-V FM (30 to 76 MHz) communications
~
""-:
a 24 W output at 76 MHz with 9 dB gain (Min.)
JEDEC TD-6D
H-1307
• Low thermal resistances
The RCA-HR2N5071 is a high-reliability version of the
RCA-2N5071. It is specially processed and screened for high
reliability in accordance with the basic schedules outlined
earlier in the discussion of Processing and Screening of
HR-Series High-Reliability Transistors. The maximum ratings,
specific electrical (Group A) tests and test limits, and the
burn-in conditions for the HR2N5071 are shown below. The
basic electrical-characteristics curves and test conditions and
the mechanical details for this device are the same as those
given for the basic 2N5071 transistor in RCA data bulletin file
No. 269.
I. MAXIMUM RATINGS, Absolute-Maximum Values:
COLLECTOR-TO-BASE VOLTAGE ...................... VCBO
65
V
eOLLECTOR-TO-EMITTER VOLTAGE ................... VCEO
30
V
EMITTER-TO-BASE VOLTAGE ......................... VEBO
4
V
Continuous ........................................ Ie
Peak ............................................ .
3.3
10
A
CONTINUOUS BASE CURRENT ......................... IB
1
A
COLLECTOR CURRENT:
A
'TRANSISTOR DISSIPATION:
At case temperatures up to 250 e
At case temperatures above 250 e
Derates linearly at
70
W
0.4
W/oe
'TEMPERATURE RANGE:
Storage and operating (junction) ....................... .
-65 to 200
°e
230
°c
. LEAD TEMPERATURE (During soldering):
At distances;;:: 1/32 in. (0.8 mm) from insulating wafer for
lOs max. . ..................................... .
95
HR2N5D71
II. GROUP A TESTS. At Case Temperature ITCI = 2SoC.
STATIC
TEST CONDITIONS
CHARACTERISTIC
DC
Base
VoltageV
DC
Collector
Voltege·V
SYMBOL
VCB
VCE
V BE
DC
Current
mA
IE
LIMITS
IB
UNITS
MIN.
MAX.
-
10
30
-
200'
40
-
0
4
-
lA
20
-
-
2.5
IC
Collector· Cutoff Current:
With base open
With emitter open
ICEO
ICBO
30
0
60
S
mA
Collector to Emitter
Sustaining Voltage:
With base open
200·
0
VCEOlsusl
With external base·
to-emitter resistance
VCERlsusl
V
(RBEI =5,Q
Emitter·to·Base
Breakdown Voltage
10
V(BRIEBO
V
DC Forward Current
Transfer Ratio
hFE
5
Thermal Resistance
(Junction·to·Casel
ROJC
°C/W
DYNAMIC
TEST CONDITIONS
CHARACTERISTIC
Power Output
Power Gain
SYMBOL
POE
GpE
Available Amplifier
Signal Input Power
Collector Efficiency
Input Power
(PIEI-W
Frequency
(fl-MHz
MIN.
MAX.
24
3
76
24
24
3
76
9
-
dB
POE =24W
76
-
3-
W-
3
76
60
-
%
1.2
30
GO/NOGO
VSWR = 3:1
-
1
Source impedance
Pi
(Zgl = 50
24
TIC
Load Mismatch
LM
Collector-to-Base Capacitance
Cabo
8pulsed through a 25~mH inductor; duty factor
24
VCB =30V
"=
50%; repetition rate> 60 Hz.
* Recorded before and after burn·in for each device (serialized).
III. BURN-IN CONDITIONS
TA = 25°C
VC8=28V
PT =2_6W
96
LIMITS
DC Collector
Supply IVCCI-V
-
UNITS
85
W
pF
OOCIBLJD
RF Power Transistors
Solid State
Division
HR2N5090
High-Power Silicon N-P-N
Overlay Transistor
High-Gain Type for Class A, B, or C
Operation in VHF/UHF Circuits
Features:
1:1
Maximum.safe-area-of-operation curve
a 1_2-W (min_I output at 400 MHz (7_8-dB gainl
JEDECTO-60
H-1307
II
1_6-W (typ_) output at 175 MHz (12-dB gain)
The RCA-HR2N5090 is a high-reliability version of the
RCA-2N5090_ It is specially processed and screened for
high reliability in accordance with the basic schedules outlined earlier in the discussion of Processing and Screening
of HR-5eries High-Reliability Transistors_ The maximum
ratings, specific electrical (Group A) tests and test limits,
and the burn-in conditions for the HR2N5090 are shown
below_ The basic electrical-characteristics curves and test
conditions and the mechanical details for this device are
the same as those given for the basic 2N5090 transistor in
RCA data bulletin file No_ 270_
" Hermetic stud-type package
a All electrodes isolated from stud
I. MAXIMUM RATINGS, Absolute-Maximum Values:
COLLECTOR-TO-BASE VOLTAGE ________________________________________ _
55
V
55
30
3_5
0.4
0.4
V
V
V
A
A
4
Derate linearly at 0_04
W
W/oC
-65 to +200
oc
230
oc
VCBO
COLLECTOR-TO-EMITTE R VOLTAGE:
With external base-to-emitter resistance, RBE = 10 n ________________________ _
VCER
With base open ______________________________________________________ _
VCEO
EMITTER-TO-BASE VOLTAGE __________________________________________ _
VEBO
CONTINUOUS COLLECTOR CURRENT ____________________________________ _
IC
CONTINUOUS BASE CURRENT _________________________________________ _
IB
TRANSISTOR DISSIPATION:
PT
At case temperatures up to 1000 C _______________________________________ _
At case temperatures above 1000 C ...................................... .
TEMPERATURE RANGE:
Storage and Operating (Junction) ________________________________________ _
LEAD TEMPERATURE (During Soldering):
At distances~ 1/16 in_ (1.58 mm) from insulating waferfor 10 s max ____________ _
97
HR2N5090
II. GROUP A TESTS, at Case Temperature (Tel = 250 C
STATIC
TEST CONO ITIONS
CHARACTERISTIC
SYMBOL
Collector Cutoff Current:
With base open
With base-emittar junction reverse-biased
OC
COLLECTOR
VOLTAGE
V
DC
BASE
VOLTAGE
V
DC
CURRENT
VCE
VBE
IE
ICEO
28
ICEV
55
Emitter Cutoff Current
lEBO
Collector-ta-Base Breakdown Voltage
V(BRICBO
LIMITS
UNITS
rnA
IB
MIN.
IC
-
0.02
-
0.1
0.1
55
-
5
30
-
5
558
-
0
-1.5
3.5
0
0
MAX.
0.1
rnA
rnA
V
Collector-ta-Emitter Sustaining Voltage:
With base open
V
n
Emitter-to~Base
0
VCEO(susi
With external base-to-emitter
resistance (Rae) "" 10
VCER(susi
Breakdown Voltage
0.1
V(BRIEBO
Collector-ta-Emitter Saturation Voltage
VCE(sad
DC Forward-Current Transfer Ratio
hFE
Thermal Resistance (Junction-la-Case)
ROJC
20
5
0
3.5
-
V
100
-
1.0
V
50
10
200
-
25
oCM
DYNAMIC
TEST CONDITIONS
CHARACTERISTIC
SYMBOL
DC
COLLECTOR
VOLTAGE
V
Power Output (Class C amplifier,
unneutralizedl
POE
VCC' 28
OUTPUT
POWER
(POEI
W
INPUT
POWER
(PIE I
W
COLLECTOR
CURRENT
(lCI
rnA
0.2
FREQUENCY
LIMITS
UNITS
(II
MHz
400
MIN.
MAX.
1.2
-
W
MHz
Gain-Bandwidth Product
IT
VCE'15
50
500
-
Magnitude of Common Emitter,
Small-5ignal, Short-Circuit
Forward-Current Transfer Ratio
Ihlel
VCE'15
50
2.5
-
Available Amplifier Signal
Input Power
Pi
-
0.2
Collector Efficiency
'lc
Collector-to-Base Capacitance
Cobo
1.2
1.2
VCB·30
apulse through a 25·mH inductor; duty factor;:; 0.05.
* Recorded before and after burn·in for each device (serialized).
III. BURN·IN CONDITIONS
TA = 250 C
VCB = 28 V
PT~
98
1.75 W
400
1
W
45
-
%
-
3.5
pF
ffi1(]5LJD
RF Power Transistors
Solid State
Division
HR2N5470
Silicon N-P-N Overlay Transistor
For UHF/Microwave Power Amplifiers,
Microwave Fundamental-Frequency Oscillators,
and Frequency Multipliers
Features:
" l-W output with 5-dB gain (min.) at 2 GHz
JEOEC TO·215M Package
,H-1598
" 2-W output with 10·dB gain (typ) at 1 GHz
The RCA-H R2N5470 is a high-reliability version of the
RCA-2N5470. It is specially processed and screened for
high reliability in accordance with the basic schedules outlined earlier in the discussion of Processing and Screening
of H R-Series High-Reliability Transistors. The maximum
ratings, specific electrical (Group A) tests and test limits,
and the burn-in conditions for the HR2N5470 are shown
below. The basic electrical-characteristics curves and test
conditions and the mechanical details for this device are
the same as those given for the basic 2N5470 transistor in
RCA data bulletin file No. 350.
" Ceramic· metal hermetic package with low inductance
and low parasitic capacitances
I. MAXIMUM RATINGS,Absolute-Maximum Values:
COLLECTOR-TO·BASE VOLTAGE.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCBO
COLLECTOR-TO-EMITTER VOLTAGE:
With external base-to-emitter resistance, RBE = 10 n .......... __ .. __ .. _... _. _ veER
EMITTER-TO-BASE VOLTAGE ........................................... .
VEBO
PEAK COLLECTOR CURRENT ........................................... .
CONTINUOUS COLLECTOR CURRENT
TRANSISTOR DISSIPATION:
At case temperatures up to 250 C
At case temperatures above 25 0 C
TEMPERATURE RANGE:
Storage and operating (Junction) ........................................ .
55
V
55
3.5
0.4
0.2
V
V
A
A
3.5
Derate at 0.02
W
WloC
-65 to +200
oC
99
HR2N5470
II. GROUP A TESTS, at Case Temperature (TCI = 250 C
TEST CONDITIONS
CHARACTERISTIC
SYMBOL
COllector Cutoff Current
ICES
Collector-fo-Base Breakdown Voltage
V(BRICBO
COllector-to-Emitter Sustaining Voltage:
With external base-ta-emitter resistance
(RBEI = IOn
VCER(susl
DC
DC
Collector
Current
Voltag.IVI
ImAI
VCB
IE
VCE
LIMITS
UNITS
IB
Min.
IC
0
0.1
Emitter-to-Base Breakdown Voltage
V(BRIEBO
Collector-ta-Emitter Saturation Voltage
VeE (satl
COliector-to-Base Capacitance
(M ••sured at 1 MHz!
Ccb
30
POB
2B
10
Max.
-
1
mA
0.1
55
-
V
5
55
-
V
0
3.5
-
V
100
-
1.0
V
-
3.0
pF
1.0
-
W
30
150
50
0
RF Power Output (Common-Base Amplifier):
At2GHz8
Forward Current Transfer Ratio
aFor PIS"" 0.316 W; minimum efficiency
hFE
= 30%.
·Recorded before and after burn-in for each device (serialized).
III. BURN-IN CONDITIONS
TA=250 C
VCB= 15V
PT= lW
100
5
50
RFPower Transistors
OOCTI5LJD
Solid State
Division
HR2N5916
High-Gain Silicon N-P-N
Overlay Transistor
For VHF/UHF Communications Equipment
Features:
•
Radial leads for micros1ripline circuits
" 2-W (min_) output at 400 MHz (10-
.
Overdrive Capability of 20 W Output
Features:
" 6-dB gain (min_) at 400 MHz with 16-W (min.) output
.. Integral emitter·ballasting resistors
JEDEC TO-216AA
H-1693
a Broadband performance (225-400 MHz)
" Low-inductance ceramic-metal hermetic package
The RCA-HR2N5919A is a high-reliability version of the
RCA-2N5919A. It is specially processed and screened for
high reliability in accordance with the basic schedules outlined earlier in the discussion of Processing and Screening
of H R·Series High-Reliability Transistors. The maximum
ratings. specific electrical (Group A) tests and test limits,
and the burn-in conditions for the HR2N5919A are shown
below. The basic electrical-characteristics curves and test
conditions and the mechanical details for this device are
the same as those given for the basic 2N5919A transisto; in
RCA data bulletin file No. 505.
"Radial leads for microstripline circuits
'
"All electrodes isolated from the stud
I. MAXIMUM RATINGS,Absolute·Maximum Values:
COLLECTOR-TO-EMITTER VOLTAGE:
With base open ...................................................... .
COLLECTOR·TO·BASE VOLTAGE ....................................... .
EM ITTER·TO·BASE VOLTAGE .......................................... .
CONTINUOUS COLLECTOR CURRENT ................................... .
TRANSISTOR DISSIPATION:
At case temperatures up to 750 C
At case temperatures above 750 C
TEMPERATURE RANGE:
Storage and operating (Junction) ....................................... .
CASE TEMPERATURE (During Soldering):
For 10 s max. . ..................................................... .
VCEO
VCBO
VEBO
IC
PT
30
65
4
4.5
'V
V
V
A
25
Derate at 0.2
WloC
-65 to +200
oc
230
oc
W
105
HR2N5919A _______________________________________________________
II. GROUP A TESTS, at Case Temperature (TC ' = 25° C
STATIC
TEST CONDITIONS
CHARACTERISTIC
SYMBOL
DC
Collector
Voltage·V
DC
Ba..
Voltage·V
DC
Current
mA
VCE
VBE
'E
30
0
LIMITS
UNITS
Min.
Max.
-
10
2000
65
-
V
2000
30
V
IC
'B
Collector-ta-Emitter Cutoff Current:
With base connected to emitter
Collector-fa-Emitter Breakdown Voltage:
With base connected to eminer
With base open
'CES
0
V(BRICES
0
V(BRICEO
Emitter-ta-Base Breakdown Voltage
V(BRIEBO
forward Current Transfer Ratio.
hFE
Thermal Resistance (Junction-fo-case)
R8JC
5
4
0
4
-
500
10
200
-
5.0
mA
oC/W
.Pulsed through 8 25-mH inductor; duty factor = 50%
DYNAMIC
TEST CONDITIONS
CHARACTERISTIC
SYMBOL
Output Power
Overdrive Objective Test
POE
4.0
400
16
28
7.0
400
20
28
lIC
28
Collector-l0-Base Output Capacitance
Cobo
30 (VcBI
-Recorded before and after burn-in for each device (serialized).
TA=25 0 C
VCB = 28 V
PT= 2.6W
106
LIMITS
28
GpE
III. BURN-IN CONDITIONS
Frequency
(fl
MHz
Input
Power
(P'E)·W
DC Collector
Collector Efficiency
Power Gain
Output
Power
(POE)-W
Supply
(VCC'·V
16
4.0
UNITS
Min.
Max.
-
400
6
400
65
-
1
-
22
W
dB
%
pF
RF Power Transistors
OOCTI3LlD
Solid State
Division
HR2N5920
2-W, 2-GHz, Emitter-Ballasted
Silicon N-P-N Overlay Transistor
For UHF/Microwave Power Amplifiers,
Microwave Fundamental-Frequency
Oscillators, and Frequency Multipliers
Feawres:
• 2-W output with 10-r
At case temperature up to 750 C •.....•..•.......•....•....
At case temperature above 750 C ............ Derate linearly at
TEMPERATURE RANGE:
Storage and operating (Junction) ........................... .
LEAD TEMPERATURE (During Soldering):
At distances ;;. 0.02 in. (0.5 mm) from seating plane for lOs max. ..
HR3001
HR3003
50
3.5
50
50
V
3.5
3.5
V
5
0.04
8.34
0.067
14.7
0.118
W
WJOC
HR3005
-65 to +200
oc
230
°c
129
HR3001, HR3003, HR3005
II. GROUP A TESTS, at Case Temperature fTC)
= 2fjO C
STATIC
TEST CONDITIONS
CHARACTERISTIC
SYMBOL
Voltage
Vde
VCE VCB
Collector Cutoff Current:
With emitter open
28
ICBO
Current
mAde
IE
LIMITS
HR3001
HR3003
HR3005
UNITS
IC ~IN. MAX. MIN. MAX. MIN. MAX.
0
-
0.5
-
0.5
-
0.5
rnA
Coliector·to·Base Breakdown
Voltage
V(BR)CBO
0
5
50
-
50
-
50
-
V
Emitter·to·Base Breakdown
Voltage
V(BR)EBO
0.1
0
3.5
-
3.5
-
3.5
-
V
100
15
120
15
120
15
120
-
25
-
15
-
8.5
Forward Current Transfer Ratio
Thermal Resistance:
(Junction·to·Case)
hFE
5
ROJC
°CIW
DYNAMIC
TEST CONDITIONS
CHARACTERISTIC
Output Power
Large·Signal
Common-Base
Power Gain
SYMBOL
POB
GpB
Collector Efficiency
7lC
Collector-to-Base
Output Capacitance
Cobo
FREQUENCY
GHz
VCC
f
PIS POB MIN. MAX. MIN. MAX. MIN. MAX.
28
28
28
3
3
3
0.2
0.8
1.4
28
28
28
3
3
3
1.0
2.5
4.5
28
28
28
3
3
3
1.0
2.5
4.5
VCB = 28
1 MHz
*Recorded before and after burn-in for each device (serialized).
III. BURN·IN CONDITIONS
HR3001
HR3003
HR3005
25
TA
°c
°c
TC
130
VCB
15
15
8
V
Pr
1.9
2.0
3.2
W
130
LIMITS
VOLTAGE
Vdc
145
POWER
W
HR3001
1.0
-
7
-
30
HR3003
-
-
HR3005
-
-
-
-
4.5
-
-
-
30
-
-
2.5
-
-
5
-
-
UNITS
W
-
-
-
5
-
dB
-
-
-
-
30
-
%
-
-
3
-
5
-
7
pF
[ID(]3LJ[J
RF Transistors
Solid State
Division
HR40915
O.2-to-1.4-GHz Low-Noise
Silicon N-P-N Transistor
For High·Gain Small·Signal Applications
Features:
a Low noise figure:
JEDEC TO·72
NF = 2.5 dB (max.) with 11 dB gain at 450 MHz
= 3.0 dB (typ.) at 890 MHz
= 4.5 dB (typ.) at 1.3 GHz
a High gain·bandwidth product
CI Large dynamic range
a High gain (tuned, unneutralized):
GpE = 14 dB (min.) at 450 MHz D Low distortion
= 6.5 dB (typ.) at 1.3 GHz
The RCA·HR40915 is a high·reliability version of the
RCA-40915. It is specially processed and screened for high
reliability in accordance with the basic schedules outlined
earlier in the discussion of Processing and Screening of
HR·Series High·Reliability Transistors. The maximum ratings,
specific electrical (Group A) tests and test limits, and the
burn·in conditions for the HR40915 are shown below. The
basic electrical·characteristics curves and test conditions and
the mechanical details for this device are the same as those
given for the basic 40915 transistor in RCA data bulletin file
No. 574.
I. MAXIMUM RATINGS, Absolute·Maximum Values:
COLLECTOR·TO·BASE VOLTAGE ........................... .
V
VCBO
VCEO
35
COLLECTOR·TO·EMITTER VOLTAGE ....................... .
15
V
EMITTER·TO·BASE VOLTAGE ............................. .
VEBO
3.5
V
CONTINUOUS COLLECTOR CURRENT
IC
40
mA
TRANSISTOR DISSIPATION:
PT
At ambient temperatures up to 25°C
At ambient temperatures above 25°C ........................ .
200
Derate linearly at
1.14
TEMPERATURE RANGE:
Storage and Operating (Junction) ........................... .
-65 to + 200
131
HR40915
II. GROUP A TESTS, At Ambient Temperature ITAI = 25·C.
TEST CONDITIONS
CHARACTERISTIC
SYMBOL
DC
COLLECTOR
VOLTAGE
(V)
VCB
I
VCE
DC
CURRENT
(rnA)
IE
I I
IB
LIMITS
IC
MIN.
I
UNITS
MAX.
STATIC
Collector Cutoff Current
ICBO
Collector·to-Base
Breakdown Voltage
V(BR)CBO
Collector-to-Emitter
Breakdown Voltage
V(BR)CEO
Emitter-to-Base
Breakdown Voltage
V(BR)EBO
OC Forward·Current
Transfer Ratio
hFE
Thermal Resistance:
ROJA
(Junction-to-Ambient)
-
20
0.01
35
-
V
0.1
15
-
V
0
3.5
-
V
3
20
-
-
-
880
·CIW
0
10
0
0
0.01
10
nA
DYNAMIC
Device Noise Figure (f = 450 MHz)
NF
10
1.5
-
2.5
d8
Small-Signal Common-Emitter
Power Gain (f =450 MHz)
Unneutralized Amplifier
GpE
10
1.5
14
-
dB
At minimum noise figure
GpE
10
1.5
11.0
-
dB
1.0
pF
Collector·to-Base Output
Capacitance (f = 1 MHz)
Cobo
*Recorded before and after burn·in for each device (serialized).
III. BURN-IN CONDITIONS
TA = 25·C
VCB = 15V
PT=0.2W
132
10
0
-
RF Transistors
DClCIBLJD
Solid State
Division
HR41039
Silicon N-P-N Overlay Transistor
For VHF Broadband Amplifiers in CATV and MATV Equipment
Features:
• Low Device Noise Figure:
200·MHz narrow·band (30 mAl = 3 dB max.
6D-MHz narrow·band (30 mAl = 2.2 dB max.
5D-250·MHz broadband = 6.5 dB typo
JEOEC TO·39
H-1381
• High Gain:
GpE (200 MHz, 30 mAl = 15 dB min.
GVE (5D-250 MHz, broadband) = 10 dB typo
fT (30 mAl =1.8 GHz min .
The RCA·HR41039 is a high·reliability version of the
RCA·41 039. It is specially processed and screened for high
reliability in accordance with the basic schedules outlined
earlier in the discussion of Processing and Screening of
HR·Series High·Reliability Transistors. The maximum ratings,
specific electrical (Group A) tests and test limits, and the
burn·in conditions for the HR41039 are shown below. The
!;lasic electrical·characteristics curves and test conditions and
the mechanical details for this device are the same as those
given for the basic 41039 transistor in RCA data bulletin file
No. 764.
• Low Distortion:
Cross·modulation (40 dBmV, 17 V, 60 mAl =-67 dBtyp.
IMD (50 dBmV, 17 V, 60 mAl = -55 dB typo
• Coliector·to·Base Time Constant:
(f = 31.9 MHz) = 7.0 ps typo
I. MAXIMUM RATINGS, Absolute·Maximum Values:
COLLECTOR-TO-BASE VOLTAGE ........................... .
VCBO
40
V
VCEO
V EBO
25
V
EMITTER-TO'BASE VOLTAGE __ . __ ............. __ ...... __ .. .
3.5
V
CONTINUOUS COLLECTOR CURRENT __ ....... __ . __ ........ .
IC
0.25
A
TRANSISTOR DISSIPATION:
PT
COLLECTOR-TO·EMITTER VOLTAGE:
With base open .•.. __ .......... ____ .............. __ .. __ ..
At case temperatures up to 75D C
At case temperatures above 75D C ........................... .
2.5
Derate linearly at
0.02
W
W/Dc
TEMPERATURE RANGE:
Storage & Operating (Junction) .................... __ ....... .
-65 to 200
LEAD TEMPERATURE (During soldering):
At distances~ 1/32 in. (0.8 mm) from seating plane for 10 s max...
230
133
HR41039
II. GROUP A TESTS, At Case Temperature ITC) = 25°C
STATIC
TEST CONDITIONS
CHARACTERISTIC
SYMBOL
DC
Voltage
V
V CB
Coliector·Cutoff Current
Coliector·to·Base Breakdown Voltage
Emitter-to-Base Breakdown Voltage
I CBO
V CE
DC
Current
mA
IE
18
IB
LIMITS
IC
0
Min.
Max.
-
100
p.A
V
V(BR)CBO
0
1
40
V(BR)EBO
0_1
0
3.5
-
0
20
25
-
V
10
100
-
0.25
V
50
60
350
-
50
Collector-to-Emitter Sustaining Voltage:
With base open
Collector-to-Emitter Saturation Voltage
UNITS
VVEO(sus)
VCE(sat)
DC Forward-Current Transfer Ratio
hFE
Thermal Resistance: (Junction-to-Case)
ROJC
15
V
°C/W
DYNAMIC
CHARACTERISTIC
SYMBOL
TEST CONDITIONS
DC
DC
Voltage
Current
mA
V
V CB
Small-Signal, Common-Emitter
Power Gain (f = 200 MHz)
GpE
Noise Figure (Measured) (f = 200 MHz)
Wideband Voltage Gain (f = 50-250 MHz)
LIMITS
UNITS
IC
Min.
Max.
15
30
15
-
dB
V CE
IE
IB
NF
15
30
-
3.2'
dB
G VE
17
60
9.5
-
dB
CMD
17
60
-62
-
dB
15
30
1.8
-
15
60
2
-
-
2.5
12-Channel Cross Modulation
Distortion (f = 50-250 MHz;
output level
=40 dBmV)
Gain-Bandwidth Product
fT
(f = 200 MHz)
Collector-to-Base Capacitance (f = 1 MHz)
Cobo
30
BBecause of insertion loss of input test circuit. device noise figure is approximately 0.2 dB less than measured.
*Recorded before and after burn-in for each device (serialized).
III. BURN-IN CONDITIONS
TA = 25°C
VCB = 15 V
PT = 1 W
134
GHz
pF
File No. 46
[R1(]5LJL]
RF Power Transistors
Solid State
Division
40279
The RCA·40279 is the ultra·high reliability version of the
RCA·2N3375 epitaxial silicon N·P·N planar transistor intended for
class-A, -B, or -C amplifier, frequency multiplier, or oscillator
operation. This device is subjected to special preconditioning
tests for selection in ultra-high-reliability, large-signal, highpower, VHF-UHF applications in Space, Military, and Industrial
communications equipment.
•
High-Power
VHF-UHF
Amplifier
Ultra-High Reliability
o Complete Qualification Testing
JEDEC TO-60
RF SERVICE, Maximum Ratings (Absolute-Maximum Values)
Collector-To-Base Voltage, VCBO
Collector-To-Emitter Voltage:
With base open, VCEO
65
volts
40
volts
With VBE =-1.5 volts, VGEV
65
volts
Temperature Range:
Storage
Operating (Junction)
amps.
1.5
oC
-65 to 200
-65 to 200
Lead Temperature (During soldering):
At distances 1/32" from insulating
wafer for 10 sec. max.
.
volts
Emitter-To·Base Voltage, VEBO
Collector Current, IC
Transistor Dissipation, PT:
At TC up to 25 0C
11.6
watls
At TC above 250 C • • . • • .• Derate linearly to 0 watts at 200 0 C
°c
oC
230
ELECTRICAL CHARACTERISTICS - Case Temp. = 250 C (Unless Otherwise Specified)
TEST CONDITIONS
CHARACTERISTIC
SYMBOL
DC
DC
COLLECTOR BASE
VOLTS
VOLTS
VCE
VBE
VCB
DC
CURRENT
(MILLIAMPERES)
IB
IC
IE
LIMITS
UNITS
Min.
Max.
-
ICEO
-
30
-
-
0
-
0.1
~
Collector To-Base Breakdown Voltage
BVCBO
-
-
0
_.
-
0.1
65
-
Volis
Collector-To-Emitter Breakdown Voltage
-
0
65"
-
Volis
-
oto 200'
oto 200*
40"
-1.5
0
4
-
Volts
Collector-Cutoff Current
BVCEO
-
Collector-To-Emitter Breakdown Voltage
BVCEV
-
Emitter-To-Base Breakdown Voltage
BVE80
-
VCE(sat)
-
Collector-To-Emitter Saturation Voltage
Output Capacitance
Cob
30
RF Power Output Amplifier,
Unneutralized
At 100 Mc (See Fig. I)
At 400 Mc (See Fig. 2)
Forward Current Transfer Ratio
POUT
-
hFE
-
28
28
5
• Pulsed through an Inductor (25 mb); duty factor = 50 '7e
. , Measured at a current where the breakdown Voltage is a minimum.
11-63
-
0.1
-
-
100
0.5 amp
-
1
Volt
-
0
-
-
-
10
pf
-
-
-
-
7.5 0
3'10
-
Watts
Watts
•
-
-
-
For PIN
& For PIN
150
=
=
-
Volis
-
1.0 Wi minimum efficiency = 65 '7e
1.0 Wi minimum efriclenoy = 40%
135
40279
File No_ 46
FIGURE 1
TO-60 DIMENSIONAL OUTLINE
RF AMPLIFIER CIRCUIT FOR 40279
POWER-OUTPUT TEST
(lOOoMc Dpe,atian)
'"
+VCC
NOTE 1;
NOTE 21
3 PINS .046 OIA.
.030
CNOTEI)
GENERATOR IMPEDANCE = BO OHMS.
LOAD IMPEDANCE == GO OHMS,
FOR IOO-Me OPERATION
Ct. C z : 7·100 PF
Ca. c 4 :
CS:
4.-10 PF
380 PF. DISC CERAMIC
Ce:
1500 PF
c7 :
O.005JLF, DISC CERAMIC
L,I
3 TURNS NO. 18 WIRE, 1/4" 10, s/Ie" L.ONG
L Z:
FERRITE CHOKE, Z
= 7150(±ZO%J
OHMS
La: 2.4-,uH CHOKE
L4:
R, I
15 TURNS NO. 16 WIRE, 5/10" 10, 7/10" LONG
1.35 OHMS, NON-INDUCTIVE
FIGURE 2.
RF AMPLI FIER CIRCUIT FOR 40279
POWER-OUTPUT TEST
(400-Mc Operation)+vCC
92CS-1204Sft~
RELIABILITY TESTING
Electrically, the RCA-40279 is similar to the RCA-2N3375;
the exception being the 40279 ICED is 100 nanoamperes maximum. In addition to Preconditioning and Group A tests, a Quali-
fication Approval test series (Group B Tests) is performed on a
semi-annual basis. All units are tested to assure freedom from
second breakdown in Class-A applications.
Preconditioning (100 Per Cent Testing of Each Transistor)
1_ Serialization
2. Record ICED, hFE' VeE (sat)
3. Temperature Cycling-Method 102A of MIL-STO-202, 5 cycles,
-650 C +2000 C
4. Bake, 72 hours minimum, +2000 C
*10. Record ICED, hFE' VCE (sat) at 168 h~urs and SOO hours
11. Helium Leak, 1 x 10-8 cc/sec. max.
12. Methanol Bomb, 70 pSig, 18 to 24 hours
13. X-Ray, RCA spec. 1750326
14. Record Subgroups 2 and 3 of Group A Tests
S. Constant Acceleration'Method 2006 of MIL-STO·7S0, 10, OOOG,
Y1 and Y2 axes
6. Record ICED, hFE, VCE (sat)
7. Reverse Bias Age, TA = IS00C, VCB = 28V, t = 168 hours
*8. Record ICED, hFE' VCE(sat)
9. Power Age, TA = 2SoC, VCB = 28V, t = SOO hours,
Po = 2.6 W, free air
136
Delta criteria after 168 hours Reverse Bias Age and after 168 hours
and SOO hour Power Age
b.ICED
+100 %or +10 nanoamperes whichever is greater
b.hFE
±30%
b. VCE (sat) ±O.! V
40279
File No. 46
Group A Tests
TEST METHOD PER
MIL·STD·750
EXAMINA TION OR TEST
CONDITIONS
Subgroup I
2071
LIMITS
LTPD SYMBOL MIN. MAX.
UNITS
10
-
Visual and Mechanical
Examination
Subgroup 2
-
-
-
-
-
-
100
namps
S
30360
Coliector·To· Emiller
Cutoff Current
VCE = 30 V, 18 = 0
-
ICEO
30010
Collector· To·Base
Breakdown Vollage
IC = 100pa,
IE = 0
-
BVCBO
65
-
Volts
3026D
Emiller·To·Base
Breakdown Voltage
IE = 100pa,
IC = 0
BVEBO
4
-
Volts
30110
Collector·To· Em iller
Breakdown Voltage
IC = 0 to 200ma
(Inductive) IB = 0
-
BVCEO
40
-
Volts
30llA
Coliector·To·Emiller
Breakdown Voltage
IC = 0 to 200ma
(inductive)
VBE = ·l.SV
-
BVCEV
6S
-
Volts
3071
Collector·To·Emitter
Saturation Voltage
IC = SOOma,
IB = 100ma
-
VCE(sat)
-
I
Volt
3076
Forward Current
Transfer Ratio
~
hFE
10
-
-
Cob
-
10
pf
-
POUT
7.S
-
Watts
-
POUT
3
-
Watts
= ISOma
CE = SV
Subgroup 3
5
3236
Output Capacitance
f=140KC\,t
VCB =30,
IpO
See Fig. I
R.F. Power Output
(Min. Elf. = 6S %)
VCE = 28V
Pi = IW,
f = 100me
See Fig. 2
R. F. Power Output
(Min. Elf. = 40 %)
VCE=28V,
Pi = IW,
f = 400mc
IS
Subgroup 4
30360
Collector Cutolf Current
TA = ISOoC ± 30 C,
VCB = 30V,
1[= 0
-
ICBO
-
100
pamp
3076
Forward Current
Transfer Ratio
TA = ISOoC ± 30 C,
IC= IS0ma,
VCE = SV
-
hFE
-
200
-
137
40279
File No. 46
Group B Tests
TEST METHOD PER
MIL-STD-750
EXAMINA TION OR TEST
Subgroup 1 (10 samples)
2066
Physical Dimensions
CONDITIONS
To-60
202/102A
Temperature Cycle
5~, -650 C,
1056B
Thermal Shock
OoC, !OOoC
1021
Moisture Resistance
Omit lead fatigue
20360
Torque-To-Stud
I minute, 12 inch
pounds
2000 C
500G, 5 blows
Xl, VI, ZI, 1 msec.
2016
Impact Shock
2046
Vibration Fatigue
-
2056
Vibration Var. Freq.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
7
Subgroup 3 (!O samples)
-
2026
Solderability
1066
Oew Point
250 C, -650 C
read ICED
1001
Barometric Pressure
100,000 ft.
read ICED
Subgroup 4 (25 samples)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
7
1031
Storage Life
2000 C, 1000 hr
2006
Conslant Acceleration
20,OOOG, VI, V2
Subgroup 5 (25 samples)
Operating Life
7
7
Subgroup 2(10 samples)
1026
LIMITS
LTPD* SYMBOL MIN. MAX. UNITS
7
1000 hrs
TC=1400 c,
VCB=28V,
Po = 4W
-
End Points
Subgroups 1,2,3,4,5
30360
Collector-Cutoff Current
VCE = 30, IB ~ 0
-
ICED
-
1
fllimp
30llA
Collector-To-Emitter
Breakdown Voltage
IC = 0 to 200ma
(inductive)
VBE-1.5V
-
BVCEV
60
-
Volts
R.F. Power Output
(See Fig. 1)
f = 100mcl,t
VCE ~ 28 ,
Pi = lW
-
POUT
6.5
-
Watts
Forward Current Transfer
Ratio
!,p,. = 150ma,
-
hFE
9
-
-
Emitter-To-Base
Breakdown Voltage
IE = 100flli, IC= 0
-
BVEBO
3.5
-
Volts
3076
30260
CE = 5V
* Acceptance/ReJectIOn CrIterIa of Group B tesls: For an LTPD plan of 7 % the total sample
SIze IS 80 fQr which
the maximum number of rejects allowed is 2. Acceptance is also subject to a maximum of one (1) reject per Subgroup.
138 Group B tests are performed once every six months as part of Qualification Approval.
File No. 202
RF Power Transistors
OOm5LJ1]
Solid State
Division
40294
RCA-40294 is an ultra-high-reliability double-diffused, epitaxial planar transistor of the silicon NPN
type for low-noise amplifier, mixer, and oscillator applications at frequencies up to 500 MHz EC
TO-72
For UHF Applications
in Critical Aerospace
and Military Equipment
Features
The curves of TYpical Characteristics shown in
the technical bulletin for RCA-2N2857 also apply
for RCA-40294.
Maximum Rotings,
o Extra-rigorous control and inspection of all parts,
materials, and internal assemblies before sealing
Absolute-Maximum Values:
COLLECTOR-TO-BASE VOLTAGE, VCBO ••
30 max.
V
COLLECTOR-TO-EMITTER VOLTAGE, VCEO 15 max.
V
EMITTER-TO-BASE VOLTAGE, VEBO . . . . . 2.5 max.
V
COLLECTOR CURRENT, IC' . • . . . . . . • ..
TRANSISTOR DISSIPATION, PT:
For operation with heat sink:
At case tern-} up to 25°C . • . . • . • • . . • .
peratures*
above 25°C . . . . . . Derate
For operation in free air:
At ambient } up to 25°C .••.•....••.
temperatures above 250C ..•.•. Derate
40 max.
rnA
o 100% thermal and mechanical preconditioning after
sealing
• complete electrical and mechanical QUALITY CONFORMANCE test program
o 100% RELIABILITY ASSURANCE testing
300 max. mW
at 1.72 mW/oC
o 100% PERFORMANCE-REQUIREMENTS testing
o 100% Noise Figure and Power Gain Tests at 450 MHz
200 max. mW
at 1.14 mW/DC
TEMPERATURE RANGE:
Storage and Operating (Junction) . . . . . . . • -65 to +200 DC
LEAD TEMPERATURE (During soldering):
At distances..2: 1132 inch from
seating surface for 10 seconds maximum. • • . 265 max.
* Measured ut center of seating surface.
o Meets performance requirements of TX2N2857 MI L-S·
19500/343 USAF, 7 March 1966
o high gain.bandwidth product fT = 1000 MHz min.
o very low Device Noise Figure -
NF
DC
= 4.5 dB max. at 450 MHz
• high power gain as neutralized amplifier -
Gpe = 12.5 dB min. at 450 MHz for circuit
bandwidth of 20 MHz
• high power output as uhf oscillator-
Po = 30 mW min. at 500 MHz
• low collector-to-base time constant -
rb'C c = 15 ps max.
12-66
139
40294
FileNo. 202
100%
RELIABILITY
ASSURANCE
TESTS
(SEE TABLE IV)
100%
PERFORMANCE
REQUIREMENTS
TESTS
(SEE TABLE V)
Fig.l .. High"Reliability Testing Process Flow Diagram
TABLE I 100% PRECONDITIONING
BEFORE FACTORY, QUAl{TY, RELIABILITY·ASSURANCE AND PERFORMANCE REQUIREMENTS TESTS
STABILIZATION BAKE ••.•.. :. , .••••••••••.•.....•.•••.•••..•...•••.• 48 hours minimum at 2000 C
TEMPERATURE CYCLING
(PER MllrSTD-750 METHOD 1051, CONDo C) ••••.••••.. 5 complete cycles from -65 0 C to +2000 C, each including
15 minutes at -65 0 C, 1~ minutes at +200 0 C, and 5 minutes at 250 C
HELIUM-LEAK TEST (PER MIL-STD-202, METHOD 112 CONDo C. PROC.llIA).•.. Leakage may not exceed 10-8 aim cc/s
BUBBLE TEST (PER MllrSTD-202, METHOD 112 CONDo A) ...••••••... 1500 C minimum, 1 minute, ethylene glycol
CONSTANT-ACCELERATION (CENTRIFUGE) TEST (PER MlL-STD-750, METHOD 2006) •. 20,000 G's; Yl plone, 1 minute
DIMENSIONAL OUTLINE
TERMINAL DIAGRAM
JEDEC TO·72
:l
Bottom View
~DIA.~~::r
LEAD I-EMITTER
J9S MAX.
"~I.t'!"·-nl
LEAD 2 - BASE
----,
LEAD ~ - COLLECTOR
LEAD U - CONNECTED
TO CASE
.21) MAX.
.170 "MIN.
r
t
SEATING PLANE
L..030 MAX.
.017
HOTEl:
THE SPEC I FI ED LEAD 0 I AMETER APPLI ES I N THE
ZONE BETWEEN 0.050" AND 0.250" FROM THE SEATING PLANE.
FRDH 0.250" TO THE END OF THE LEAD A MAXIMUM DIAMETER
OF 0.021" IS HELD. OUTS) DE OF THESE ZONES. THE LEAD
DIAMETER I S NOT CONTROLLED.
HOTE 2:
MAXIMUM DIAMETER LEADS AT A GAUGING PLANE
o .05U" + 0.001" - 0.000" BELOW SEATING PLANE TO BE
WITHIN 0.007' OF THEIR TRUE LOCATION RELATIVE TO MAX.
WIDTH TAB AND TO THE MAXIMUM 0.2~0" DIAMETER MEASURED
WITH A SUITABLE GAUGE. WHEN GAUGE IS NOT USED, MEASUREMENT WI LL BE MADE AT SEATING PLANE,
4 LEADS
DIA.
(NOTE I)
!.:ggf
92C5-12817
140
NOTE 3:
FOR VISUAL ORIENTATION ONLY.
HOTE~:
TAB LENGTH TO BE 0.02B" MINIMUM - O.OUB"
MAXIMUM. AND WILL BE DETERMINED BY SUBTRACTING DIAMETER
A FROM DIMENSION B.
File No. 202
40294
TA8Lt: II
GROUP A TESTS
Lot
Sub.
group
Toler.
once
Pe.
Characteristic
Test
MIL-STD
Symbol
Cont
Defoc.-
750
Roference
Test
Method
iYe
Visual and Mechanical
Examination
Collector.
Cutoff
Current
Collector_
Cutoff
Current
Collector-la-Bose
Breakdown
Voltage
TEST CONDiTIONS
LIMITS
DC
Fro_
DC
Collector.
DC
DC
DC
Collector.
toCollector Emitter Base
Tem- quenRCA
cy
to.Bose
Units
Emitter
pera_
Curront Curront Cur40294
f
Voltage
rent
Voltage
iC
IE
t~_r;
VCB
IB
VCE
• C MHz
mA
mA
rnA Min. Max.
v
v
Am-
bient
2071
3036
ICBO
Bios Condi- 2S!3
ICES
3041
Bias Condi- 2S±3
15
16
BVCBO Test Condl- 25.!:3
tion 0
Static Forward
Current_Transfer
Ratio
Small-Signal Power
Gain .. _.
Device Noise Figure<&:
Generator Resistance
(RG) = 50 U'
Measured Noi so Figure
~;~r;) Resistance
10
Collector-to-Base Time
Constant.&
nA
0.001
30
v
3"
15
v
2.5
v
3026
-0.001
BVEBO Test Condi- 25:!:3
tion D
3066
VCE
3071
2S:t3
3076
25,3
v
10
Test Condi- 2S:!;3
tion A
CollectorVoltage
100
3001
Bose-toEmitter
Voltage
to.Emitter
nA
tion C
Collector.ta-Emitter
Breakdown
Voltage
Emltter.'a.Base
Breakdown
Voltage
10
tion D
10
0.4
V
30
150
12.5
19
dB
Gpe
25,3
450
1.5
NF
25:1:3
450
1.5
4.5
dB
IIF
25±3
450
1.5
5.0
dB
rbrCc
25,3
31.9
15
ps
Oscillator Power
O.utp~t
25,3 ~500
~0.1
Collector-to-Base
•
Feedback Capacitance
10
~1
Static Forward Current
Transfer Ratio
(Low Temperature)
hFE
Collector-Cutoff
Current (High
Temperature)
ICBO
~7r~I~~i~~~:a~~C~r_
3076
-55,3
3036
0
10
-12
mW
30
pF
10
10
Bios Condi- 150+ 5
tion 0
-
15
3206
25,3
0.001
50
220
3206
25,3
100
10
19
rent-Transfer Ratio,"
* Pulse Test
.& Lead No.4 (Case) Grounded
• Device noise figure Is approximately 0.5 dB lower than the measured noise figure.
The difference is due to the insertion !oss at the input of the lest amplifier and
the contribution of the following stages in the tes.. setup.
• Three-terminal meosurement with emitter and case leads guarded.
141
40294
File No. 202
TABLE III
GROUP B TESTS
INITIAL AND ENDPOINT
CHARACTERISTICS TESTS
MIL_STD
750
Test
Subgroup
Reference
Lo'
RCA.40294
Tolerance
Charoc~
Per Cent
teristic
Defective
Test
~
MIL_STD
750
Reference
Test
Conditions
Inilial
Values
Min. Mox.
End Point
Values
Min.
Units
Max.
PHYSICAL DIMENSIONS
(See Dimensional 0..,1line Drawing on page
7)
SOLDERABILITY
Solder Temp. :: 260±PC
TEMPERATURE.
CYCLING TEST
2066
20
2026
ICBO
1051
T A :::2St3 °C
V
30360
VCB=15
--
10
3076
TA :::2St3 °C
30
Vee"l V
\50
10
nA
(Condition C)
THERMAL.SHOCK TEST:
T min
=O:6°C
T max::
100~~
1056
Tesl Cand;
10
lion A
DC
MOISTUR f_RE_SIST ANCE
TEST
hPE
30
150
IC~3mA
1021
SHOCK TEST:
NON·OPERATING
1500 G's, 0.5 ms
2016
ICBO
5 blows each in X"
Y,. Y2. ond ZI planes
30360
T A =25!30C
VCB=15 V
--
10
TA =25~30C
VCE",I V
30
150
10
nA
VIBRATION FATIGUE
TEST: NON.OPERATING
60 !20 Hz, 20 G's
2046
VIBRATION VARIABLE.
FREQUENCY TEST
2056
CONSTANT .ACCELERA.
TION TEST: 20,000 G's
2006
10
3076
hPE
Helium
TERMINAL STRENGTH
TEST
2036
Test Condi.
tion E
Leak
20
Test
Bubble
Test
SAL T .ATMOSPHERE
TEST
142
HIGH.TEMPERATURE
LIFE TEST (NON.
OPERATING):
T A =200dO·C
Du ral,on=1000 I1rs,
1031
STEADY·STATE OPERA.
TION LIFE TeST:
Common.Sose Circuit
T A =25z3' C
Vca=12.5±0.5 V
PT=200 mW
Durotion=1000 hrs.
1026
Condition C
Procedure
--
10"
atm
cm3/s
10
nA
III A
MIL·STO
202
Condition
A
TA"150a C
(m'".)
1 minute
30360
--
3076
T A =25~30C
VCE"l V
IC=3 mA
30
ICBO
30360
T A =25!3* C
hPE
3076
leBO
30360
20
hPE
150
MIL·STO
202
Methad1l2
T A =25~3 °C
VCS=15 V
ICBO
1041
30
Ic"3mA
Vca=15
'" 7%
10
150
30
10
V
150
20
nA
T A =25:3 0 C
'" 7%
hPE
3076
VCE=l V
IC=3 rnA
30
150
T A=2S±30C
VCS=15 V
--
10
30
150
TA =25~3 °C
Vce=l V
IC=3 rnA
24
180
20
24
180
nA
File No. 202
40294
TABLE IV
100% RELIABILITY ASSURANCE TEST
THE CUMULATIVE REJECTS OF TABLES IV AND V SHALL NOT EXCEED 10% OF THE LOT
INITIAL AND ENDPOINT CHARACTERISTICS TESTS
Test
MIL·STD
750
Choracterist.ic
Reference
Test
RCA·40294
POWER BURN·IN,
Common.Base Circuit
i\ICBO
TA =25,3 0 C
VCB=12.5,0.5 V
Initial
Endpoint
Value
Value
10 max.
i\d5
nA
nA
MIL·STD
750
3036
30 min.
i\hFE
PT=200 mW
i\:±15%
150 max.
TA =25,3 0 C
Bios Condi_
tion
1026
Duration=340 hours
Test
Conditions
Reference
VCS=IS V
0
T A =25,3 0 C
VCE=I V
IC:3 mA
3076
TABLE V
100% PERFORMANCE REQUIREMENTS TESTS
THE CUMULATIVE REJECTS OF TABLES IV AND V SHALL NOT EXCEED 10% OF THE LOT
TEST CONDITIONS
Test
Symbol
MIL·STD
750
Reference
Ambient FreTempera_ quenture
oy
TA
f
°C
Colleclor.Cutoff
Current
Collector_Cutoff
Currenl
Collector_to.Base
Breakdown Voltage
Collector-la.Emitter
Breakdown Voltage
Emitter-fa-Base
Breakdown Voltage
MHz
DC
DC
LIMITS
DC
lector
Emit_
te.
Voltage
Curront
Current
VCB
VCE
IC
IE
IB
V
V
mA
mA
mA
Col.
RCA
40294
Min.
ICBO
ICES
Bios Condition C
3041
3001
15
2St3
25,3
16
Units
Max.
10
nA
100
nA
BVeBO Test Condi-
25,3
0.001
30
V
3011
BVCEO Test Condi-
25,3
3-
IS
V
2.5
V
tion 0
(sus)
lion D
3026
BVEBO Tesl Can dr-
2St3
-0.001
lion D
3066
Tesl Cond!lion A
2St3
10
Collector_lo.Emitter
Voltage
VCE
3071
25,3
10
Static Forward
Current_Transfer
Ratio
hFE
3076
25,3
soO,.
Bose
Currenl
3036
Bios Condi_
tion 0
VBE
Measured Hoi se
Figure Generator
Resistance RG =
DC
Voltoglit
Collector- Collectorlo·Base to-Emitter
Bose_to_Emitter
Voltage
Device Noise
Figure ... : Generator
Resistance (RG)=SO
Ohms
-
DC
NF
25,3
450
1.5
NF
25±3
4SO
1.5
Visual Examinalion
(External)
Under 20-Power
Magnification
V
0.4
V
30
ISO
--
4.5
dB
5.0
dB-
Examine leads, header, and shell for visual defects ..
... Pulse Test
... Lead No.4 (Case) Grounded
143
File No. 603
RF Power Transistors
OOOBLJD
Solid State
Division
40298
Ultra- High-Reliability Silicon
N-P-N Epitaxial Planar Transistor
f~
JEDECTO·72
For UHF Applications in Critical
Aerospace and Military Equipment
Features:
• Meets performance requirements of TX2N2857 MIL-S19500/343 USAF,? March 1966
• Extra·rigorous control and inspection of all parts,
materials, and internal assemblies before sealing
• 100% thermal and mechanical preconditioning atter
.. aling
RCA·40296 is an ultra-high-reliability double-diffused, epitaxial planar transistor of the silicon n-p-n type for low-noise
amplifier, mixer, and oscillator applications at frequencies up
to 500 MHz (common-emitter configuration), and up to
1200 MHz (common-base configuration).
This transistor is electrically and mechanically like RCA2N2857, but is specially processed, preconditioned, and
tested for critical aerospace and military applications.
The 40296 utilizes a hermetically sealed JEDEC TO-72
package. All active transistor elements are insulated from the
case, which may be grounded by a fourth lead in applications
requiring shielding of the device.
• Complete electrical and mechanical QUALITY CONFORMANCE test program
• 100% RELIABILITY ASSURANCE testing
• 100% PERFORMANCE-REQUIREMENTS testing
• 100% noise figure and power gain tests at 450 MHz
The curves of Typical Characteristics shown in the technical
bulletin for RCA-2N2857 also apply for RCA·40296.
MAXIMUM RATINGS,Absolute-Maximum Values:
COLLECTOR-TO-EMITTER VOLTAGE ...................... .
COLLECTOR-TO-BASE VOLTAGE .......................... .
EMITTER-TO-BASE VOLTAGE ............................. .
CONTINUOUS COLLECTOR CURRENT ...................... .
TRANSISTOR DISSIPATION ............................... .
With heat sink, at case' temperatures up to 25°C .............. .
With heat sink, at case' temperatures above 25°C .............. .
At ambient temperatures up to 25°C ....................... .
At ambient temperatures above 25°C ....................... .
TEMPERATURE RANGE;
Storage & Operating (Junction) ........................... .
CASE TEMPERATURE (During soldering):
At distances ~ 1/32 in. (0.8 mm) from seating
surface for 10 seconds max.
VCEO
VCBO
VEBO
IC
PT
15
30
2.5
40
300
Derate linearly 1.72
200
Derate linearly 1.14
V
V
V
rnA
mW
mWfC
mW
mWtC
-65 to +200
°c
265
°c
* Measured at center of seating surface.
144
10-72
File No. 603
40296
100%
100%
100%
SERIALIZE
PRECONDITIONING
(SEE TABLE I)
RELIABILITY
ASSURANCE
TESTS
(SEE TABLE IV)
100%
PERFORMANCE
REQUIREMENTS
TESTS
(SEE TABLE V)
Fig.l· High-Reliability Testing Process Flow Diagram
NOTE 1, (NEUTRALIZATION PROCEDURE): (A) CONNECT
~H~~NMp1JTS~~~~~N~t~'b~A{~:A~~I~FF~~ (~gg~~)E~~
A 50-OHM RF VOLTMETER ACROSS THE OUTPUT TERMINALS OF THE AMPLIFIER. (C) APPLY VEE, AND WITH THE
SIGNAL GENERATOR ADJUSTED FOR 5 mV OUTPUT FROM
THE AMPLIFIER, TUNE CI, C3, AND C4 FOR MAXIMUM
OUTPUT. (D) INTERCHANGE THE CONNECTIONS TO THE
SIGNAL GENERATOR AND THE RF VOLTMETER. (E) WITH
SUFFICIENT SIGNAL APPLIED TO THE OUTPUT TERMI-
1 500
1000
l--~WH
1
500
&800
-.: -:::.~:~ ::0 I:A:!~~~LL:A~~O
1pr.
('000
+i
RESISTAIIC[ VAlUES I"OHMS.
CAP'CHAIICE VALUES I"
"EE"7.5V
Q.= RCA Type 40296
92eS-1214M'
~NAD~~A~O~HlT'i~LI~~~';t. A(~iWp~~lPfE~S~i~,I~~~
AND (C) TO DETERMINE IF RETUNING IS NECESSARY.
NOTE 2, LI & L2-SILVER-PLATED BRASS ROD, 1-1/2"
LONG x 1/4" DIA. INSTALL AT LEAST 1/2" FROM NEAREST VERTICAL CHASSIS SURFACE.
NOTE 3, EXTERNAL INTERLEAD SHIELD TO ISOLATE
THE COLLECTOR LEAD FROM THE EMITTER AND BASE
LEADS.
Fig.2 - Neutralized Amplifier Circuit Used to Measure 450·MHz Power Gain and Noise Figure.
TABLE I 100% PRECONDITIONING
BEFORE FACTORY, QUALITY, RELIABILITY-ASSURANCE AND PERFORMANCE REQUIREMENTS TESTS
STABILIZATION BAKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 hours minimum at 2000 C
TEMPERATURE CYCLING
(PER MIL-STD-750 METHOD 1051. CONDo C) . . . . . . . . . . . 5 complete cycles from -65 0 C to +200 0 C, euch including
15 minutes ut -65 0 C. 15 minutes at +200 0 C. and 5 minutes at 25 0 C
HELIUM-LEAK TEST (PER MIL-STD-202, METHOD 112 CONDo C. PROC.IIIA). . . . Leakage lOlly nol exceed 10-8 aIm ccls
BUBBLE TEST O'ER MIL-STD-202, METHOD 112 CONDo A) . . . . . . . . . . .. 150 0 C minimum, 1 minute, ethylene glycol
CONSfANT-ACCELERATJON (CENTRIFUGEI TEST (Plm MIL-STD-750, METHOD 2006) .. 20,000 G'.; Yl plane, I minute
145
40296
File No. 603
TABLE II
GROUP A TESTS
Lo.
Toler.
Sub ..
group
once
Po.
Characteristic
Test
Symbol
bient
Reference
pera-
Test
Method
Cent
Defect.
Ive
Am·
MIL-STD
750
Cutoff
Collector.
Cutoff
Current
'¥r;,
Voltage
f
MHz
Collector.
'0·
Emitter
VVI~o:e
Voltage
V
v
LIMITS
DC
DC
DC
Collector Emitter Base
lC
IE
~."~i
rnA
rnA
rnA
Current
Current
VCE
RCA
IB
Min. Max.
15
Bias CORdl- 25:13
tion 0
10
nA
100
nA
3041
ICES
16
Bias Condi- 25:!;3
tion C
3001
BVCBO Test Condi- 25:1;3
tion 0
Collector .. to .. Emitter
Breakdown
0.001
30
v
3*
15
v
2.5
v
Voltage
3026
Emitter-la-Base
Breakdown
Voltage
3066
Collector.
VCE
Static Forward
Current-T ransler
Ratio
Small-Signal Power
Measured Noise figure
Generator Resl stance
10
~G ~SOO
Collector_to_Base Tim
Constant..
30
150
450
1.5
11.5 16.5
dB
NF
25,3
450
1.5
3.4
dB
NF
25'3
450
1.5
4.2
dB
rb'C c
25,3
31.9
lS
ps
25,3 ~500
~0.1
Collector-to-Base
•
Feedback Capacitance
~1
ICBO
3076
·55,3
3036
+0
10
·12
mW
30
pF
10
10
15
Bias Condi- 150 5
tion D
-
"A
3206
25,3
0.001
50
220
3206
25,3
100
10
20
* Pulse Test
~
Lead No.4 (Case) Grounded
,. Device noise figure is approximately 0.5 dB lower than the measured noise figure.
The difference is due to the insertion lass at the input of the test amplifier and
the contribution of the fallowing stages In the .est setup.
• Three-terminal measurement with emitter and case leads guarded.
146
V
25±3
Static Forward Current
Transfer Ratio
(Low Temperature)
10
0.4
3076
OSCillator Power
Outpu_t
Collector_Cutoff
Current (High
Temperature)
v
1.
10
3071
Gain~
Device Noise Figure*':
Generator Resistance
(RG) ~ 50 {l
10
Test Condi .. 2S"!;3
tian A
Emitter
Voltage
Voltage
0.001
BVEBO Test Condi .. 2513
tion 0
Bose-too.
to.Emitter
Units
40296
3036
ICBO
Collector-la-Bose
Breakdown
TEST CONDITIONS
DC
2071
CollectorCurrent
DC
CollectorTern. quency
to·Bose
•C
Visual and Mechanical
Examination
Fre-
40296
File No. 603
TABLE III
GROUP B TESTS
INITIAL AND ENDPOINT
CHARACTERISTICS TESTS
MIL·STD
750
Tesl
Subgroup
Reference
L ••
RCA·40296
10lcronl;c
Charac~
Pcr Cent
teristic
I Defc~live
MIL·STD
750
Reference
Test
Tesl
Conditions
Iniliol
Values
Min. MOK.
PHYSICAL DIMENSIONS
(See Dimensional Out_
line Dra .... ing on page 7)
SOLDERABILITY
Solder Temp.
=260±5°C
2066
Value!>
Units
MOll.
20
2026
TA :::25!30C
ICBO
TEMPERATURE.
CYCLING TEST
End Point
Min.
1051
30360
Vea::15 V
3076
Vee,,1 V
--
10
30
150
--
10
30
150
10
nA
(Condition C)
THERMAL.SHOCK TEST:
1min
=O:E °c
T mOle::
100~~
1056
Test Cand;
tian
10
MOISTURE.RESIST ANCE
TEST
T A =25~3 °C
A
°C
hFE"
IC~3
30
150
rnA
1021
SHOCK TEST:
NON-OPERATING
1500 C's, 0.5 ms
5 blows each in Xl.
YI. Y2, and Z 1 planes
VIBRATION FATIGUE
TEST: NON_OPERATING
2016
30360
2046
60 :20 Hz. 20 C'S
2056
CONST ANT .ACCELERA.
TION TEST: 20,000 G's
2006
SAL T .ATMOSPHERE
TeST
TA
=25:3 0 C
VCB=lSV
10
nA
10
TA =2S:30C
VIBRATION iVARIABLE.
:FREQUENCY TEST
TERMINAL STRENGTH
TEST
ICBO
2036
Tesl Condi.
lion E
1041
3076
hFE
20
MIL·STD
202
Helium Methodl12
Leek Condition C
Test
IP.ocedu,e
I---Ji
1031
STEADY·STATE OPERA.
nON LIFE TEST:
Corrmon.Bose Circuit
TA -=25!3' C
VCB=12.S!O.5 V
PT=200 mW
Durolion=1000 hrs.
1026
30
150
--
10"
crn3 /s
10
nA
c.m
III A
Bubble
Test
MIL.STD
202
Condition
I CBO
30360
T A =2S~3
VCB=15 V
3076
TA =25!30C
Vce=1 V
le=3 rnA
I CBO
30360
TA =25:3' C
hFE
3076
ICBO
30360
A
20
hFE
HIGH. TEMPERATURE
LIFE TE5T (NON.
OPERATING):
TA :o200!IO'C
Ouration=IOOQ h,s.
VCE",I V
Ic~3 rnA
T+=~5qoC
,min.
I minule
ac
-30
10
150
30
10
150
20
VCB=15 V
1\= 7%
nA
T A =25~30C
VCe=l V
le=3 mA
30
150
24
180
T A=25~30C
--
10
--
20
30
150
24
180
VCB=IS V
A= 7%
hFE
3076
T A =25:3 0 C
VCE=l V
nA
le=3 rnA
147
40296
File No. 603
TABLE IV
100% RELIABILITY ASSURANCE TEST
THE CUMULATIVE REJECTS OF TABLES IV AND V SHALL NOT EXCEED 10% OF THE LOT
INITIAL AND ENDPOINT CHARACTERISTICS TESTS
MIL·STD
7S0
Test
RCA·40296
Characteristic
Test
Reference
Initial
POWER BURN.IN,
Cammon ..8ase Circuit
,'ICBO
TA =2S,3"C
VCB=12.S,0.SV
Py=200 mW
10 max.
nA
ddS
nA
Bias Condi.
tion 0
h=±lS%
3076
30 min.
t\hFE
Test
Conditions
Endpoint
Value
1026
150mox.
Duration=340 hours
MIL.STO
750
Value
Reference
3036
TA =25,3"C
VCB=15 V
TA =25,3"C
VCE=1 V
IC=3 mA
TABLE V
100% PERFORMANCE REQUIREMENTS TESTS
THE CUMULATIVE REJECTS OF TABLES IV AND V SHALL NOT EXCEED 10% OF THE LOT
TEST CONDITIONS
Tnt
Symbol
MIL·STO
750
Re~erence
Ambient Fre_
Tempera- quen_
ture
cy
TA
"C
Collector-Cutoff
Current
CoJleclc;r.CutoH
Currenl
Collector.to·Bose
Breakdown Voltage
MHz
DC
Collector. Collector.
to .. Sase lo.Emitter
Voltage
Voltoge
LIMITS
DC
DC
DC
Col.
lector
Current
Current
VCB
VCE
IC
IE
IB
V
V
mA
mA
mA
Emi ••
te.
Base
Current
RCA
40296
.... In.
ICBO
ICES
Bias Condi_
25'3
15
10
nA
100
nA
3041
25'3
16
tion C
3001
BVCBO Test Condi~
25·3
0.001
30
V
25·3
3'
15
V
2.5
V
.ion 0
3011
BVCEO Test Condi(sl.ls)
lian 0
Emitter-la-Base
Breakdown Voltage
BVEBO
Test Candi.
tion D
Base.to_Em itter
Voltage
VBE
Test Condi_
tion A
2S'3
10
Collector-to_Emitter
Voltage
VCE
3071
25-3
10
Static Forward
Current ..Transfer
Ratio
hFE
3076
25'3
3026
0.001
25-3
3066
NF
Visual Examination
(External)
Under 20-Power
Magnification
• Pulse Test
'" Lead No.4 (Case) Grounded
Units
Mex •
3036
8ios Condi
tion 0
CoI'ec:to._to.Emitter
Breakdown Vaita,e
Device Noise
Figure",: Generator
Resistance (RG)=50
Ohms (See Fig_ 3
for Test Circuit)
148
I
DC
25-3
450
1.5
Examine leads, header, and shell for visual defects.
V
0.4
30
150
--
3.9
V
dB
File No. 603
40296
DIMENSIONAL OUTLINE
JEDECTO-12
INCHES
MILliMETERS
SYMBOL.
..
0°
,0O,
"h
~
•
;
--~
MAX.
0.170
0.210
0.016
0.021
0.016
0.019
0.209
0.230
0.118
0.195
0.100 T.P.
0.050 T.P.
A
.',
-,
NOTES
MIN.
0.036
10030
0.046
0.028
0.048
0.500
I
0.050
0.250
45° T.P.
"
"
MIN.
MAX.
5.33
0.533
0.483
5.84
5.31
4.95
4.52
2.54 T.P.
1.27 T.P.
0.762
1.17
0.111
1.22
12.70
1.21
63.
45° T.P.
4.32
0.406
0.406
0'9'41
4.6
'NSULATION
J~~.
92CS-17444
Note 1: (Four leads). Maximum number leads omitted in this outline. "none" taL The'number and position of leads actually present
are indicated in the product registration. Outline designation determined by the location and minimum angular or linear spacing of
any t'NO adjacent leads.
Note 2: (All leads) I'bb2 applies between '1 and '2- cfib applies between 12 and 0.50 in. 112.70 mm) from seating plane. Diameter is
uncontrolled in
and beyond 0.50 in. (12.70 mm) from seating
plane.
Note 3: Measured from maximum diameter of the product.
Note 4: Leads having maximum diameter 0.019 in. (0.484 mm)
measured in gaging plane 0.054 in. (1.37 mm) +0.001 in. (0.025
mm) - 0.000 (0.000 mm) below the seating plane of the product
shall be within 0.007 in. (0.178 mm) of their ·true position relative
to a maximum width tab.
Note 5: The product may be measured by direct methods or by
gage.
Note 6: Tab centerline.
1,
TERMINAL CONNECTIONS
Lead 1 Lead 2 Lead 3 Lead 4 -
Emitter
Base
Collector
Connected to case
149
File No. 144
OOm5LJD
RF Power Transistors
40305
40306
40307
Solid State
Division
RCA-40305. 40306. and 40307 are high-reliability variants of RCA-2N3553. 2N3375. and 2N3632
epitaxial silicon n-p-n overlay transistors. They
are intended for Class-~ -8. or -C amplifier. frequency multiplier. or oscillator operation.
High
Reliability
High-Power
These devices are subjected to special preconditioning tests for selection in high-reliability.
large-signal. high-power. VHF-UHF applications
in Space. Military. and Industrial communications
equipment.
VHF-UHF
Amplifier
40305
40306
40307
JEDEC TO·60
JEDEC TO-39
FEATURES
• High-Reliability Assured By Seven (7) Preconditioning Steps
• Data Recorded Before and After "Power-Age Test"
and Held to Critical Delta Criteria
• High Voltage Ratings VCBO = 65 volts max.
VCEV = 65 volts max.
VCEO = 40 volts max.
• 100 Per-Cent Tested to Assure Freedom from Second Breakdown for Operation in Class-A Applications
• High Power Output, POUT' Unneutralized Class-C
Amplifier At 400 Me,
3 w min. (40306)
175 M {13.5 w min. (40307)
c
2.5 w min. (40305)
100 Me, 7.5 w min. (40306)
RF SERVICE"
Maximum Ratings, Absolute-Maximum Values
40305 40306 40307
40305 40306 40307
COLLECTOR-TQ.BASE
VOLTAGE.VCBO········
COLLECTOR-TQ.EMITTER
VOLTAGE:
With base open. VCEO •••••
With VBE -1.5 volts. VCEV.
EMITTER-TQ.BASE
VOLTAGE.VEBO········
COLLECTOR CURRENT. Ie ..
=
65
65
65
volts
volts
volts
40
65
40
65
40
65
4
1.0
4
1.5
volts
4
3.0 amperes
7.0
11.6
Tg~~~~T~~N. PT":
At CRse temperatures
up to 250 C •••••••••••
23
watts
At CRse temperatures
above 250 C •••••••• Derate linearly to 0 watts at 2000 C
TEMPERATURE RANGE:
-65 to 200
°c
Storage •••••••••••••••
-65 to 200
°c
Operating (Junction)
PIN OR LEAD TEMPERATURE
(During soldering):
At distances ~ 1/32" from
insulating wafer (T0-60
package) or from seating
plane (TO-39 package)
230
°c
for 10 sec. max ••••••••••
ASecondary breakdown considerations limit maximum DC operating conditions - contact your RCA representative for specific data.
150
11·65
40305-40307
File No. 144
ELECTRICAL CHARACTERISTICS
Case Temperature
= 250
C
LIMITS
TEST CONDITIONS
Characteristic
Collector-Cutoff Current
Symbol
ICEO
DC
Collector
Base
DC
Volts
Volts
Current
(Milliamperes)
DC
VCB VCE VBE
30
IE
IB
0
40305
IC
BVCBO
0.1
0.3
0.5
Emitter-to-Bsse
Breakdown Voltage
BV EBO
0.1
0.25
Collector-to--Emitter
Breakdown Voltage
BVCEO
0
0
0
Ot0200·
Ot0200o
Collector-to-Emitter
Saturation Voltage
VCE(Bat)
100
50
500
250
DC Forward-Current
Transfer Ratio
Collector-to-Base Capacitance
Measured at 1 Me
-1.5
BVCEX
5
5
hFE
a
30
Cob
150
300
Min.
Max.
-
0.1
Min.
65
-4
4
- -- 40b
40b
40307
0.1
-65
-4
0.25
IUlmp
--
volta
-40b 65 b -- 1
- -10
-
-
10
65
-
Units
Max. Min. Max.
-65 b 65 b -- -1 -- 110
10
- -- - ---
-
0
0
0
Collector..to-Basc
Breakdown Voltage
40306
volts
volta
volts
volt
20
pf
- - --- 7.5"
-- -'3' --- 13~5e
- --
watts
10
RF Power Output
Amplifier; Unneutralized
At 100 Me
175 Me
175 Me
400 Me
POUT
a Pulsed through an inductor (25 mh); duty factor
28
28
28
28
2.Sd
--
= 50%.
d For PIN
b Measured at a current where the breakdown voltage is a minimum.
C
For PIN
= 1.0 w;
minimum efficiency
= 65%.
e For PIN
= 1/4 w;
= 3.5 w;
minimum efficiency
=50%.
minimum efficiency
= 70%.
f For PIN:: 1.0 w; minimum efficiency:: 40%.
RELIABILITY TESTING
RCA types 40305, 40306, and 40307 are electrically lower collector-cutoff current. ICEO for the 40305 and
similar to RCA-2N3553, 2N3375 , and 2N3632 respec- 40306 is 100 nanoamperes maximum and ICEO for the
tively; but they differ in that they have substantially 40307 is 250 nanoamperes maximum.
Preconditioning (100 Per-Cent Testing of Each Tronsistor)
1. Helium Leak, 1 x 10-8 cc/sec. max.
2. Temperature Cycling-Method 102A of MIL-8TD-202,
3 cycles, -65 0 C to +2000 C
8. Power Age, TA = 250 C, V CB = 28V, t = 168 hours,
free air
Po(40305) = 1 watt
P 0(40306,40307) = 2.6 watts
'" 9. Record 'CEO' hFE' VCE(sat)
3. Methanol Bomb, 70 psig, 16 hours minimum
10. X-Ray Inspection, RCA Spec. 1750326
11. Record Subgroups 2 and 3 of Group A Tests.
4. Bake, 72 hours minimum, +2000 C
• Delta criteria after 168 hours Power Age
5. Constant Acceleration-Method 2006 of MIlrSTD-750,
10,OOOG, Y1 axis
{ 40305 + 100% or + 10 nanoamperes
40306 whichever is greater
40307
6. Serialization
+ 100% or +25 nanoamperes
whichever is greater
±30%
±0.1 V
151
40305-40307
File No. 144
Group A Tests
TEST
METHOD
PER
MIL·STD·7S0
EXAMINATION
OR
TEST
2071
Visual and Mechanical
Examination
30410
Colleetor-To-Emitter
Cutoff Current
30010
Collector..To--Bose
Subgroup 1
LIMITS
SYMBOL
CONDITIONS
.
30260
·
VCE =30V.IB =0
BVCBO
IC = 100 1"', IE = 0
~=500I"',IE-0
IE - 100 1"', IC - 0
BVEBO
30110
Coileeto<-To-Emitter
Breakdown Voltage
BV CEO
IC = Oto200maa , IB = 0
30llA
Colleeto ..To-Emitter
Breakdown Voltage
BVCEX
IC = Oto200maa ,
VBE =.1.5 V
3071
Saturation Voltage
Colleetor-To-Emitter
VCE(sat)
IE = 250 1"',
Ie = 0
IC = 250 rna, IB = 50 ma
IC = 500 rna, IB =100ma
Forward Current
Transfer Ratio
IC = 150 rna, VCE = 5 V
hFE
·
·
·
·
·
·
·
·
·
·
·
IC = 300 ma, VCE = 5 V
·
f = 1 Me, VCB = 30 V,
IE =0
·
·
Subgroup 3
3236
40307
UNITS
·
·
·
·
·
0.1
0.1
65
·
·
·
·
·
·
· ·
.
5
ICEO
Breakdown Voltage
3076
40306
10
.
IC = 300 1"', IE = 0
Emitter-To-B8se
40305
Min.• Max. MIn. Max. MIn. Max.
Subgroup 2
Breakdown Voltage
LTPD
·
·
4
65
·
4
·
·
·
65
4
·
·
·
·
·
40 b
·
·
40 b
·
·
65 b
65 b
·
·
·
·
1
·
·
10
·
·
10
2.5
·
·
10
·
1
·
·
·
·
·
40 b
0.25
/UIlIlP
·
·
·
·
·
·
volts
volts
volts
volts
volta
volts
65 b
·
volts
·
·
·
·
volts
1
volts
·
·
·
10
·
10
20
pf
·
-
·
·
·
·
watts
5
Open Circuit
Output Capacitance
Cob
R. F. Power Output
POUT
VCE=28V,
PIN = 0.25 watt,
f= 175 Me,
Min. Effie. = 50%
VCE=28V,
PIN = 1 watt,
f= 100 Me,
Min. Effie. = 65%
·
·
·
7.5
·
·
·
watts
VCE=28V,
PIN = 3.5 watts,
·
·
·
·
·
13.5
·
watts
·
·
·
3
·
·
·
watts
·
·
·
100
·
·
100
·
250
I'WDP
200
·
·
r = 175 Me,
Min. Effie. = 70%
VCE=28V,
PIN = 1 watt,
f= 400 Me.
Min. Effie. = 40%
Subgroup 4
30360
3076
Collector Cutoff
Current
Fcrward Current
Transfer Ratio
15
ICBO
TA = 150°C ± 3°C,
VCB=30V,IE=0
TA = 150°C ± 3°C,
IC = 150 ma, VCE = 5 V
hFE
TA = 150°C ± 3°C,
IC = 300 rna, VCE = 5 V
• Pulsed through an inductor (25 mh); duty factor = 50% •.
b Measured at a current where the breakdown voltsge is a minimum.
152
·
·
·
200
·
-
·
·
200
40305-40307
File No. 144
DIMENSIONAL OUTLINES
FOR TY PES 40306, 40307
JEDEC TO.60
FOR TY PE 40305
JEDEC TO-J9
f
L
•100
··~~~ ~~':"l
OIA
.335 MAX •
. 305 MIN.]
O'A •
.~
MIN.
.260 MAX .
.240 MIN.
SEATING PLANE
DETAILS OF OUTLINE IN THIS
ZONE OPTIONAL
3 PINS
:g:~
DIA.
(NOTE I)
LEAD
INSULATING
EYELETS
INDEX TAB
92C5-12742
Dimensions in Inches
92CS-120045A!rI
Dimensions In Inches
NOTE 1: THE PIN SPACING PERMITS INSERTION IN ANY
SOCKET HAVING A PIN·CIRCLE DIAMETER OF 0.200" AND
CONTACTS WHICH WILL ACCOMMODATE PINS HAVING A
DIAMETER OF 0.035" MIN., 0.045" MAX.
NOTE 2: THE TORQUE APPLIED TO A 10-32 HEX NUT
ASSEMBLED ON THE THREAD DURING INSTALLATION
SHOULD NOT EXCEED 12 INCH-POUNDS.
NOTE 3: THIS DEVICE MAY BE OPERATED IN ANY POSITION.
TERMINAL CONNECTIONS
Pin or Lead No.1 - Emitter
Pin or Lead No.2 - Base
Pin or Leod No.3 - Collector (For 40306,40307)
Collector, Case (For 40305)
153
- -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 259
OOcn5LJI]
RF Power Transistors
Solid State
Division
40414
High-Reliability Silicon N-P-N
Epitaxial Planar Transistor
For UHF Applications in Industrial
and Military Equipment
!~~~
Features:
1\ \
1iI,
1,\
JEDECTO·72
\
H·1299
• High gain·bandwidth product: fT = 1000 MHz min.
• High converter (450-to·30 MHz) gain: Gc = 15 dB typo for circuit
bandwidth of approximately 2 MHz
• High power gain as neutralized amplifier: GpE = 12.5 dB min. at 450 MHz
for circuit bandwidth of 20 MHz
.
.
{30 mW min. 40 mW typo at 500 MHz
• HIgh power output as uhf oscIllator: POE = 20 mW tyP.: at 1 GHz
RCA-40414 is a double·diffused epitaxial planar transistor of
the silicon n·p-n type. It is extremely useful in low·noise·
•
amplifier, osr:illator, and converter applications at frequencies
Low device noise figure:
NF = {4.5 dB max. as 450 MHz amplifier
7.5 dB typ., as 450-to-30 MHz converter
Low collector-to-base time constant: rb'Cc = 7 ps typo
Low collector-to- base feedback capacitance:
Ccb = 0.6 pF typo
up to 500 MHz in the common-emitter configuration, and up
to 1200 MHz in the common-base configuration.
•
•
The 40414 is electrically and mechanically like the RCA·
2N2857, but each shipment of the RCA-40414 is accom·
panied by a certified summary of the results of the Group A
Electrical Tests and the Group B Environmental Tests shown
in Tables I and II, respectively. The Test Data Summary and
Certification shown in the Specimen Copy on page 5 are the
results of the acceptance tests for the production lot from
which the shipment is made.
RCA-40414 utilizes a hermetically sealed 4-leadJEDEC TO-72
package. All active elements of the transistor are insulated
from the case, which may be grounded by means of the fourth
lead in applications requiring shielding of the device.
Maximum Ratings, Absolute-Maximum Values:
COLLECTOR-TO·EMITTER VOLTAGE.
COLLECTOR-TO·BASE VOLTAGE . .
EMITTER·TO-BASE VOLTAGE
CONTINUOUS COLLECTOR CURRENT.
TRANSISTOR DISSIPATION
At case temperatures* up to 25°C .
At case temperatures' above 25 0 C .
At ambient temperatures up to 250 C
At ambient temperatures above 250 C
TEMPERATURE RANGE:
Storage & Operating (Junction)
The curves of Typical Characteristics shown in the Technical
Bulletin for RCA-2N2857 also apply for RCA-40414.
VCEO
VCBO
VEBO
IC
PT
15
30
2.5
40
300
Derate linearly 1.71
200
Derate linearly 1.14
-65 to +200
V
V
V
mA
mW
mW/oC
mW
mW/oC
DC
CASE TEMPERATURE (During soldering):
At distances~ 1/32 in .. (O.8 mm) from seating
surface for 10 seconds max.
~
.
265
DC
Measured at center of seating surface.
154
1()'72
FileNo. 259
40414
TABLE I - GROUP A TESTS
Lot
Toler·
ance
Sub·
Per
group
Cent
Oefect·
ive
MIL·STO
Characteristic
Test
750
Symbol
Reference
Test
Method
TEST CONOITIONS
LIMITS
Am·
OC
DC
bient Fre- Collector· Collector·
OC
DC
Tern- quen- to·Base
toCollector Emitter
pera- cy
Emitter Current Current
Voltage
ture
Voltage
VCB
VCE
TA
IC
IE
40414
oC
10
MHz
V
rnA
rnA
RCA
Units
Min. Max.
Visual and Mechanical
2071
Examination
Coilecto!Cutoff
3036
leBO
Collector-te-Base
Breakdown
Voltage
Voltage
10
nA
25~3
0,001
25 ~ 3
3'
30
V
Ie =0
IS
V
-0.01
2.5
V
3011
BV CEO Test Condi(sus)
tion 0
Emitter·la-Base
Breakdown
IS
2S±3
3001
BVCBO TestConditian 0
CollectoHo-Emitter
Breakdown
Voltage
Bias Condi-
tion 0
Current
3026
BVEBO Test Condition 0
2S!3
Static Forward
Current-Transfer
hFE
25:!3
3076
30
150
12.5
19
dB
Ratio
Small-Signal Power
Gain'"
Device Noise FigUle«
Generator Resistance
(RGI ~ soC
Gp,
25.'3
450
1.5
NF
25'3
450
1.5
4.5
dB
NF
25 ~ 3
450
1.5
5.0
dB
rb'Cc
25-3
31.9
15
p,
Po
25j3
'::500
Cob
25,3
Measured Noise Figure:
Generator Resistance
15
(RG)= 5011' ...
Collector-ta-Base Time
Constant·
Oscillator Power
Output (See Fig.4
10
·12
mW
30
for Test Circuit)
Collector-to-Base
Feedback Capacitance-
~>
0.1
o 1
pF
10
Static forward CUllent
Transfer Ratio
hFE
3076
ICBO
Bias Condi-
10
-55'3
(Low Temperature)
Collector-Cutoff
CUllent (Hrgh
3036
Temperature)
tion D
15
'0
150
,A
15
·5
Small-Signal, Short
Circuit Forwald CUI-
h"
3206
25f3
0.001
50
220
Ihr,1
3206
25+3
100
10
19
rent-Transfer Ratio·
Magnitude of SmallSignal, Short-Circuit
Forward CUllentTransfer Ratio·
• Pulse Test
~ead No.4 (Case) Grounded
-Three-terminal measurement with emitter
and case leads guarded.
: Delta shall be determined by subtracting the parameter value measured before application of stress
from the value measured after the application of
stress.
d9. Record ICBO' hFE ·
Group A Tests
TEST METHOD
PER
LIMITS
EXAMINATION OR TEST
CONDITIONS
LTPD SYMBOL
2071
Subgroup 1
Visual and Mechanical Examination
Max.
-
-
-
-
30360
30010
30260
30110
Collector-Cutoff Current
Collector-to-Emitter Breakdown Voltage
Emitter-to-Base Breakdown Voltage
Collector-to-Emitter Breakdown Voltage
ICBO
BVCEV
BVEBO
-
10
859
4
-
nA
volts
volts
3076
DC Forward-Current Transfer Ratio
3236
Subgroup 3
Output Capacitance
Power Output
RF Power Output (Min. Err. = 45'l'.,
3306
-3036P
3201
3231
Small-Signa} Forward-Current
Transfer Ratio
Subgroup 4
Collector-Cutoff Current
Input Impedance
Qutput Admittance
fpulsed through an inductor (25 !ill); duty factor = 50%.
160
10
-
Subgroup 2
UNITS
Min.
MIL·STD·750
5.
VCB = 30V. IE = 0
IC = 100 !lA. VBE = -1.5 V
IE = 100 !lA. IC = 0
IC = 10 mAl
IB =0
iC 100 rnA. VCE 5V
=
=
-
-
-
VCEO
hFE
-
609
50 275
volts
5
f = 0.1 to 1.0 MHz. VCB=28V.
IE = 0
f = 50 MHz. VCE = 28V
Pin=O.lW
VCE = 28 V. PIN = 0.1 W
f = 150 MHz
IC = 25 rnA. VCE = 28 V
f=50MHz
-
Cob
-
6.0
pF
-
POUT
1.0
-
watts
-
POUT
0.4
-
watts
-
hre
-
5.0
15
TA = 150°C. VCB = 30 V
VCE = 28V. IC =25 rnA
r = 50 MHz
VCE = 28 V. IC = 25 rnA
r = 50 MHz
-
ICBO
-
5
hie
25
75
Y22
1
2
9Meosured at a current where the breakdown voltage is
!lA
ohms
mmho
8
minimum.
File No. 297
40577
General Reliability Specifications that are applicable ta all rf power transistors are given in booklet RFT -701
andmustbeused in conjunction with the specific Preconditioning, Group A Tests, and Group B T.sts .hown below.
Group B Telts h
TEST METHOD
PER
MIL·STD·750
EXAMINATION OR TEST
113 Samples)
JEOEC TD-5 Pkg.
Subgroup 1
2066
Physical Dimensions
2026
Solderability
1051
1056
Thermal Shock (Temp. Cycling)
Thermal Shock (Glass Strain)
Seal (Leak Rate)
1021
Moisture Resistance
2016
Shock
2046
2056
2006
Vibration Fatigue
Vibration VOl. Freq.
Constant Acceleration
2036
Subgroup A
Terminal Strength (Lead Fatique)
<13 Samples)
Test Condo E
Subgroup 5
Salt Atmosphere
<13 Samples)
1041
Subgroup 2
-
20,000 G YI, Y2
1031
Subgroup 6
(25 Samples)
High Temperature Life (Non-operating) T storage = 2000 C
t = 1000 hr••
1026
Steady-State Operation
(25 Samples)
P T = 1.5 W, TC = 100 0 C
t = 1000 hr•• VCB = 40 V
Subgroup 7
30360
30010
3076
<13 Samples)
Omit aging, Dwell time =
10 8 ± 1 8
Test Condition C
Test Condition B
Method 112 of MIL-STD-202
Test Condo C. procedure III;
Test Condo A for gross leak.
<13 Sample.)
I,SOO g. 0.5 ms, 5 blows each
orientation:
Xl' Y1' Y2, Zl
Nonoperating
Subgroup 3
TEST METHOD
PER
MIL·STD·7S0
CONDITIONS
LIMITS
EXAMINATION OR TEST
CONDITIONS
SYMBOL
UNITS
Min. Max.
End Points
Subgroups (2, 3, 5, 6)
Collector Base Cutoff Current
Collector Base Breakdown Voltage
DC Forward-Current Transfer Ratio
VCB = 30 V, IE = 0
VBE = -1.5 V, le= 100 /LA
IC =100 mA, VCE = 5 V
ICBO
BVCEV
hFE
80
35
1.0
IlA
325
-
hAcceptance/Rejection Criteria of Group B tests: For an LTPD plan of 7% the tota1 sample size is 115 for which the maximum
number of rejects allowed is 4. Acceptance is also subject to a maximum of one (1) reject per Sub-group. Group B tests are performed on each lot for Qualification or Lot Acceptance.
i Pulsed through an inductor (25 mH); duty factor = 50%.
kMeasured at a current where the breakdown voltage is a minimum.
161
40571
File No. 297
DIMENSIONAL OUTLINE
JEDEC No. TO_5
L
.10012.54l
f
:mD~~IDI~
.335 (8.51)
.305 7.75
OIA.
J
.~
.
:~:g(~:~8J
MIN.
SEATING PLANE
o0
DETAILS OF OUTLINE IN THIS
Q_ I.'~~:'OI
ZONE OPTIONAL
.200 •
~·I~~)
c--!g::
INDEX TAB
Nota
DIA.
92CS-12656R2
Dimensions in parentheses are in "millimeters and
are derived (rom thp. bas ic inch dimens ions as indicated.
TERMINAL CONNECTIONS
Lead 1 - Emitter
Lend 2 - Base
Lead 3 - Collector.
Case
162
LEADS
(::~)
File No. 298
OO(]5L)O
RF Power Transistors
Solid State
Division
40578
HIGH- RELIABILITY TRANSISTOR
RCA-40578* is a high-reliahility variant of the
RCA-2N3866, an epitaxial n-p-n planar transistor of
High-Gain Device for Class A,B, or C
Operation in VHF-UHF Circuits
"overlay" emitter electrode construction. It is especially processed for high reliability. It is intended for
Class A, B, and C amplifier, frequency multiplier, or
JEDEC
TO·39
oscillator operation in high-reliability, driver or predriver stages, VHF-UHF applications in Space, Military,
and Industrial communications equipment.
H-1381
High reliability is assured by eight preconditioning
steps, including drift temperature measurements after
the High Temperature Reverse Bias and Power Age
tests. The 40578 also features complete qualification
and lot acceptance testing.
* Formerly RCA-Dev.
No. TA7080
08 Preconditioning Steps
GComplete Qualification and Lot Acceptance Testing
0High Power Gain, Unneutralized Class C Amplifier
At 400 MHz, 1 Woutput with 10 dB gain (min.)
250 MHz, 1 Woutput with 15 dB gain (typ.)
175 MHz, 1 Woutput with 17 dB gain (typ.)
100 MHz, 1 Woutput with 20 dB gain (typ.)
RATINGS
Maximum Ratings, Absolute-Maximum Values:
COLLECTOR-TO-BASE
VOLTAGE. • . • • • • • . • • . • . . . .
COLLECTOR-TD-EMITTER
VOLTAGE:
With external base-ta-emitter
resistance • • • • . . . . . • . • . . . . .
RBE
VCBO
DISSIPATION DERATING CURVE
55
V
CASE TEMPERATURE ITel
FREE-AIR TEMPERATURE(TFA1
55
V
= 10 ohms
With base open. . . • . . . . . . . . • • .
V CEO
30
V
EMlTTER-TD-BASE VOLTAGE.. . . .
COLLECTOR CURRENT. . • • . . . . •
VEBO
IC
3.5
0.4
V
A
TRANSISTOR DISSIPATION. • . . . . .
PT
W
At case temperature B up to 25 0 C. • . • . • • . . .
5
W
At free-air temperatures up to 25° C •.•••••• 1.0
At temperatures above 25° C ••.•.••....•. See Fig. 1
TEMPERATURE RANGE:
Storage & Operating (Junction). • . . .
-65 to 200 °c
.,
.!<
~
I
z
0
~
~
is
LEAD TEMPERATURE (During soldering):
At distances ~ 1/32 in. from
seating plane for 10 s max.
8-S7
TEMPERATURE-OC
•.......••••
230°C
Fig.1
92CS-I0446R3
163
40578
File No. 298
ELE<::TRICAL CHARACTERISTICS
Case Temperature
=25° C
TEST CONDITIONS
Symbol
Characteristic
DC
DC
DC
Collector
Base
Volts
Current
Volts
VC8
Collector-Cutoff Current
IcEO
Collector-to-B8se
Breakdown Voltage
VCE
V8E
IE
18
28
0
VCEO(SUB)
BVEBO
Collector-to-Emitter
VCE(sat)
Saturation Voltage
Collector-to-B8se Capacitance
0
0.1
20
Cob
(Measured at 1 MHz)
RF Power Output
Class-C Amplifier,Unneutralized
At 100 MHz
At 250 MHz
At 400 MHz
30
100
0.1
55
5
55
5
30
-
0
3.5
100
0
28 b
POUT
15
50
°With external base-emitter resistance (RBE)
bVCC value,
cFor PIN = 0.05 Wi minimum efficiency
dFor PIN = 0.1 Wi minimum efficiency
eFor PIN = 0.1 Wi minimum efficiency
nA
V
V
V
'"
V
-
1.0
V
-
3.0
pF
1.8 (typ,)~
U·(tj')
28 b
28 b
f'T
Gain-Bandwidth Product
Max.
-
IC
VCER(sus)o
Emitter-to-Base
Breakdown Voltage
Units
Min.
0
BV CBO
Collector-to-Emitter
Voltage (Sustaining)
LIMITS
(mAl
800 (typ.)
W
MHz
= 10 Q.
= 600/'0'
= 50%.
= 45%.
DIMENSIONAL OUTLINE
JEDEC TO·39
L
f
:mJ~p)~
.335 (8.51)
.305 7.75
DlA.
J
.~
.100 (2.54)
MIN.
:~~g(~:~8)
TERMINAL CONNECTIONS.
Lead No. 1 - Emitter
DETAILS OF OUTLINE IN THIS
ZONE OPTIONAL
Lead No.2 - Base
Case, Lead No.3 - Collector
DIMENSIONS IN INCHES AND MILLIMETERS
INDEX TAB
164
Note: Dimensions in parentheses are in millimeters and are
92CS-12656R2
derived from the basic inch dimensions as indicated.
40578
File No. 298
RELIABILITY
SPECIFI.CATIONS
In ·addition to Preconditioning and Group A tests·,
a Qualification Approval test series -C-. ·'O~
At ambient temperatures above 250C
derate linearly at •••••••••••••
5.71 mW/oC
TEMPERATURE RANGE:
Storage & Operating (Junction) ••••••
w
-65 to +20QoC
6~~~~
""
00
~
LEAD TEMPERATURE (During Soldering):
~
At distancm. ~ 1/32 in. W.8 mm) from
scating plane for 10 s mllx_. • • • • • • • •
~o
~
230°C
"
"
"
~
28
-
6
~,
4~
~
0
""",~l",.,
"""'" """,~l"s(
1'--..
"",,
~1'--.
.......... ~
~
2
0
50
1--
~~):-t--
i'-..~
r----.:
i'k.~h-I
Qos~
I
200
250 300 350400
-- t---t-- t-- ~o"
75
100
150
FREQUENCY! f 1- MHz
92CS-12111RI'
Fig.! . Typical power output vs. frequency.
6-69
167
40605
File No. 389
ELECTRICAL CHARACTERISTICS, Case Temperature (Te)
STATIC
SYMBOL
CHARACTERISTIC
Collector·Cutoff Current
TEST CONDITIONS
DC
DC
Base
Current
rnA
Volts
DC
Collector
Volts
VCE
30
ICEO
Collector·to-Base
Breakdown Voltage
V(BR)CBO
Collector·to-Emiller
Breakdown Voltage:
(See Fig. 2.)
With base open
V(BR)CEO
=2SoC
VBE
IE
MIN.
MAX.
-
0.1
pA
0.3
65
-
V
200·
40 b
-
IB
0
IC
0
0
UNITS
LIMITS
V
With base·emiller junction
reverse biased & external
base·to·emiller resistance
(RBE) = 3311
-1.5
V(BR)CEX
Emiller·to·Base
Breakdown Voltage
V(BR)EBO
Collector·to·Emiller
Saturation Voltage
VCE(sat)
200-
65 b
-
0
4
-
V
250
-
1
V
0.1
50
=50%
b Measured at a current where the breakdown voltage is a minimum.
a Pulsed through a 25-mH inductor; duty factor
DYNAMIC
TEST CON OITIONS
CHARACTERISTIC
SYMBOL
DC Collector
Supply (VCC) - V
Input Power
(P,E)-W
POE
28
0.25
Collector-toBase Capacitance
Cabo
VCB=30V
IC =0
Gain-Bandwidth
Product
IT
VCE =28 V
'C =125mA
Power Output
C
Frequency
(1)- MHz
LIMITS
UNITS
MIN.
TYP.
175
2.5 e
-
W
-
1
-
10
pF
-
-
350
-
MHz
Minimum efficiency = 50%
RESISTIVE
LOAD
UNCLAMPED
INDUCTIVE
LOAD
L: 25 mH at 100 mA
RBB1 : 1500
RS: 10
S: Clare Mercury Relay or equivalent
R Of
INOUCTANCE
RS82
VCC: 20 V
V BB1 : 20 V
=-
V(BRlCEO Measurement
VERTICAL
DEFLECTION
RBB2
VBB2 = 0
R of inductance = 83
L-_ _...._ _......'\N~.... ~c
Rs
R$:5
~g~c
I
V(BR)CEX Measurement
0
92CM-,5054
Fig.2 - Circuit useel to measure voltages V(BR)CEO anel V(BR)CEX (une/ampeel).
168
RBB2 =330
VBB2 =-1.5 V
File No. 389
40605
RELIABILITY SPECIFICATIONS . ..
General Reliability Specifications that are applicable to all rl power transistors are given in booklet RFT.701
and must be used in conjunction with the specific lot screening, Group A Tests,and Group B Tests shown below.
Lot Acceptance Data
Conditioning Screens (100% Testing, see Table I)
a) Attributes Data on Burn· In
b) Attributes Data on Radiographic Inspection
(Lot Sampling, see Table II)
a) Variables Data
Table
c) Variables Data on Burn·ln
(Lot Sampling, see Table III)
a) Attributes Data (From a member of the family)
Group A
Group B
1. Description 01 Total Lot Screening - 100% Testing
TEST
MIL·STD·750
CONDITIONS
MI L-STD·202
METHOD
CONDITIONS
METHOD
-
-
-
-
-
In accordance with
RCA's RFT·)OI
(See note I)
-
-
-
-
5 cycles
1051
C
-
-
4. High Temp. storage
72 hrs. min. at
TA=200 0 C
-
-
-
-
5. Acce lerati on
20,000 g min.;
VI direction only
2006
-
-
-
1I2
C
-
-
-
-
-
1. Lot identification
2. Pre·seal visual inspection
3. Temp. cycling
6. Fine ieak
-
). Gross leak
Fluorocarbon bubble test
(See note 2)
-
8. Serialize
9. Pre burn·in electrical
See Table I A
10. Burn·in
(See note 3)
-
-
-
II. Post burn·in electrical
Delta requirements
See table I A
-
-
12: Radiographic inspection
-
-
-
-
CONDITIONS
-
-
-
Note 1: Complete title of RFT-70l is: "General Reliability Specifications of RCA RF Power Transistors".
Note 2: Immersed in fluOfochemical
and observed for bubbles.
Fe
78 at 65 psig for 4 hrs, unit is than placed in fluorochemical
Fe
48 at 80 0 C (nominal)
Note 3: Burn-in tests:
Reverse bias age - all transistors shall be operated for 96 hrs
at T A 150° C. VCS 50 V
=
=
Power age - all transistors shall be operated for 340 hrs
at T A = 25° C ± 3° C. VCS = 30 V, PT = I w.
169
40605
File No. 389
Table 1 A. Pre Burn-In & Post Burn-In Tests and Delta (Ll) Limits
TEST
MIL-STD'750
SYMBOL
METHOD
LIMITS
CONDITIONS
UNITS
MIN.
MAX.
Colleclor·Culoff Current
ICEO
3041
VCE = 30 V, bias condo D
-
0.1
J-LA
DC Forward-Current
Transfer Ratio
hFE
3076
VCE = 5 V, IC = 150 mA pulsed
15
150
-
Della (L1) Limils:
ICED and hFE of Table 1A shall be relesled after each burn· in lesl and Ihe dala recorded for all devices in Ihe 101.
The tests measured shall not have changed during each burn·in test from the initial value by more than the specified
amount as follows:
L1'ICEO = ± 100% or 10 nA, whichever is grealer
L1h FE = ±20%
All Iransislors Ihal exceed Ihe della (L1) limils or Ihe limils of Table 1A after each burn-in lesl shall be removed
from Ihe 101 and Ihe quanlily removed shall be recorded in Ihe 101 hislory.
Table II. Group A Electrical Sampling Inspection
MIL-STD·750
EXAMINATION OR TEST
METHOD
Subgroup 1
Visual and Mechanical Examination
LTPD SYMBOL
CONDITIONS
-
2071
Colleclor-Culoff Currenl
30410
VCE =30 V, IB =0
Colleclor-ID-Base Bceakdown Vollage
30010
IC =0.3 rnA
Emitter·to-Base Breakdown Voltage
30260
IE =0.1 rnA
Colleclor-Io-Emiller Breakdown Vollage
30110
See Fig. 2.
30llB
See Fig. 2.
IC =200mAa
IC =200 rnA", VBE =-1.5 V,
RBE =330
Collector-ta-Emitter SatuTation Voltage
3071
IC = 250 rnA, IB = 50 rnA
DC Forward-Current Transfer Ratio
3076
IC = 150 rnA, VeE = 5 V
Output Capacitance
3236
Extrapolated Unity Gain Frequency
3261
VCB =30 V,IC =0
IC = 125 rnA, VCE = 28 V,
f=100MHz
Subgroup 3
RF Power Oulpul (Min. Elf. = 50%)
10
-
-
-
-
-
100
-
-
-
ICED
V(BR)CBO 65
4
V(BR)EBO
-
nA
V
V
-
V(BR)CEO 40 b
-
V
V(BR)CEX 65 b
-
V
-
VeE (sal)
-
hFE
15
1
V
150
-
5
See Fig. 3.
VeE = 28 V, PIE = 0.25W,
1=175MHz
-
Cobo
-
-
'T
350
-
POE
2.5
-
-
ICBO
-
100
pA
-
hFE
10
-
-
10
pF
MHz
W
15
Subgroup 4
Colleclor-Culoff Curren I
30360
DC Forward-Current Transfer Ratio
3076
a Pulsed thloug~ a 25 mH inductor; duty factor == 50%
b Measured at a current where the breakdown voltage is a minimum
170
UNITS
5
Subgroup 2
Collector-Io-Emiller Breakdown Voltage
LIMITS
MIN. MAX.
TA = 150 0 C ± 30 C,
VCB =30V
TA =-550 C ± 30 C,
IC = 150 rnA, VCE =5 V
File No. 389
40605
Table III Group B Environmental Sampling Inspeetian
MIL-STD-750
EXAMINATION OR TEST
CONDITIONS
Physical Dimensions
2066
-
Subgroup 2
Solderability
Thermal Shock (Temp. Cycling)
Thermal Shock (Glass Strain)
Seal (Leak Rate)
2026
1051
1056
Subgroup 1
-
15
-
-
-
-
-
-
--
-
Test Condition C
Test Condition B
-
Method 11201 MIL-STO·202
Test Condo C, procedure III a
For Gross Leaks, Refer
-
-
-
-
-
-
ICEO
-
to Note 1 in Lot Screening sequence
Moisture Resistance
UNITS
MIN. MAX.
20
-
LIMITS
LTPD SYMBOL
METHOD
-
-
1021
-
-
-
lXH}"7 almec/s
End Points:
Collectol-Cutoff Current
30410
30110
See Fig. 2.
Collector-ta-Emitter Breakdown Voltage
DC Forward-Current'Transfer Ratio
3076
RF Power Oulput (Min. Eff = 50%)
See Fig. 3
VCE =30V, IB=O
IC =200mAo
IC = ISO mA, VCE = 5 V
VCE = 28 V, PIE = 0.25 W,
1= 175 MHz
Subgroup 3
100
nA
V(BR)CEO 40
-
V
hFE
12
-
-
POE
2.5
-
W
-
-
-
-
-
-
-
IS
Shock
2016
1,500 g, 0.5 ms, 5 blows each
orientation:
XI, YI, ZI, Y2,(15 blows
total)
Vibration Fatigue
2046
Vibration, Variable Frequency
2056
-
Constant Acceleration
2006
20,000 g YI , Y2
-
-
Nonoperating
-
-
-
-
-
End Points:
(Same as Subgroup 2)
Subgroup 4
Terminal Strength (Lead Fatigue)
2036E
-
Subgroup 5
Sail Atmosphere
1041
-
IS
-
-
-
-
15
-
-
-
-
T stg = + 200 0 C, t = 1000 hrs.
-
-
-
-
-
VCE = 30 V, IB = 0
-
IC = 200 mAO
-
IC = ISO mA, VCE = 5 V
-
VCE = 28 V, PIE = 0.25 W,
-
Subgroup 6
High Temperature Lile (Nonoperating)
End Points:
Coliector-Cutoff Current
30410
Collector-ta-Emitter Breakdown Voltage
30110
See Fig. 2.
Q
DC Forward-Current Transfer Ratio
3076
RF Power Output (Min. Ell. = 50%)
See Fig. 3
Pulsed through a 25,uti inductor; duty factor
==
1= 175 MHz
-
I
p.A
40
-
V
hFE
12
-
-
POE
2.3
-
W
ICEO
V(BR)CEO
50%
171
40605 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 389
DIMENSIONAL OUTLINE
JEDEC No.TO·39
SYMBOL
¢a
A
<#J
¢b2
¢O
¢OI
h
j
92CS.15641
Note 1: This zone is controlled tor automatic handling. The variation
in actual diameter within this zone shall not exceed .010 in
(.254 mm).
Note 2: (Three leads)¢b2 applies between 11 and 12. ¢b applies be·
tween 12 and .5 in (12.70 mm) from seating plane. Diameter is
uncontrolled in 11 and beyond .5 in (12.70 mm) from seating
plane.
Note 3: Measured from maximum diameter of the actual device.
Note 4: Details of outline In this zone optional.
k
I
11
12
P
Q
a
f3
TERMINAL DIAGRAM
LEAD 1 - EMITTER
LEAD 2 - BASE
CASE, LEAD 3 - COLLECTOR
172
INCHES
MAX.
MIN.
.210
.190
.260
.240
.016
.021
.016
.019
.350
.370
.335
.315
.009
.125
.034
.028
.029
.040
.500
.050
.250
.100
45° NOMINAL
90° NOMINAL
MILLIMETERS
MAX.
MIN.
4.83
5.33
6.10
6.60
.406
.533
.406
.483
9.40
8.89
8.00
8.51
.229
3.18
.864
.711
1.02
.737
12.70
1.27
6.35
2.54
NOTES
2
2
3
2
2
2
1
4
File No. 600
OOCTI5LJI]
RF. Power Transistors
Solid State
Division
40606
High-Reliability
Silicon N-P-N Overlay Transistor
·r·~·n!.l"
~~?
For Large-Signal, High-Power VHF/UHF
Applications in Military and Industrial
Communications Equipment
.
Features:
....
• High power output. unneutralized class C amplifier
t"
• High voltage ratings
-::
JEDECTO·60
H-1307
• 100 per cent tested to assure freedom from second breakdown for operation
in class A applications
• All three electrodes electrically isolated from case for design flexibility
RCA-40606 is an epitaxial silicon n-p-n planar transistor.
This device is intended for class A, B, C amplifier, fre·.
quency multiplier, or oscillator operation. The device
was developed for vhf/uhf applications.
The transistor employs the overlay concept in emitterelectrode design -
an emitter electrode consisting of
many microscopic areas connected together through the
use of a diffused·grid structure and an overlay of metal
which is applied on the silicon wafer by means of a
photo·etching technique. This arrangement provides the
very high emitter periphery-ta-emitter area ratio required
for high efficiency at high frequencies.
MAXIMUM RATINGS, Absolute·Maximum Values:
COLLECTOR·TO-BASE VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . .
COLLECTOR·TO·EMITTER VOLTAGE:
With base·emitter junction reverse·biased (VBE = ·1.5 V) . . . . . . . . . .
With base open
VCBO
EMITTER-TO·BASE VOLTAGE
COLLECTOR CURRENT . . . . . . . . . . . . . . . . . . . . . . . . . .
TRANSISTOR DISSIPATION. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
At case temperatures up to 25°C
At case temperatures above 25°C
TEMPERATURE RANGE:
Storage and operating (junction) . . . . . . . . . . . . . . . . . . . . . . . . . .
TEMPERATURE (During soldering):
At distances;;' 1/32 in. (O.8 mm) from insulating wafer for lOs max ...
65
V
65
40
4
V
V
V
3
A
PT
23
Derate linearly to 0 watts at
200°C
W
-65 to 200
°c
230
°c
1()'72
173
File No. 600
40606
ELECTRICAL CHARACTERISTICS, At Case Temperature (Tel = 25 0 C
TEST CONDITIONS
Symbol
Characteristic
DC
Collector
Base
Current
Volts
Volts
(Mi lIiamperes)
VC8
Collector-Cutoff Current
DC
VCE
V 8E
DC
IE
30
'CEO
18
IC
0
LIMITS
Max.
-
0.25
Collector-to-Base
Breakdown Voltage
BVCBO
Collector-co-Emitter
Breakdown Voltage
BVCEO
0
0
-1.5
BVCEV
Emitter-co-Base
Breakdown Voltage
BVEBO
Collector-co-Emitter
Saturation Voltage
VCE(sat)
Collector-co-Base Capacitance
0.25
30
Cob
Measured at 1 MHz
RF Power Output
Amplifier. Unneutralized
Gain-Bandwidc}. Product
rnA
0.5
65
-
volts
o to 200'"
o to 200·
40"
65"
-
volls
0
4
-
volts
500
-
1
volt
-
20
pF
:ci·;·yyp:)
watts
0
volts
Vee =
POE
At 260 MHz
400 MHz·
100
Units
Min.
28
28
IT
28
150
Base-Spreading Resistance
Measured at 200 MHz
cbb'
28
250
Collector-co-Case Capacitance
Cs
DC Forward-Current
Transfer Ratio
hFE
5
Second· Breakdown
Collector Currenta
(Base forward-biased)
[Sib
28
300
400 ('Yp.)
MHz
(~YP')
ohms
-
6
pF
10
-
0.33
-
6.5
A
• Pulsed through an inductor (25 mh); duty factor = 50% •
•• Measured at a currcnt where the breakdown volcagc is a minimum .
• For PIE
For PIE
.a.
= 4.0 w;
= 4.0 w;
minimum efficiency = 60% .
minimum efficiency
= 45%.
a .Pulse duration = 1 s.
COLLECTOR-TO-EMITTER VOLTS (VCE)=28
CASE TEMPERATURE eTC)" 25" C
I.
;'"
I
......
14
>-
13
w
II
-
10
,J>
>=>
~
>=>
0
r-...
......
12
-
9
-9... "
~~',
-9,
I~o".
8
'2
-/
7
~
'"
3
~~"" ~)'".
ffi
co
~
......4
...........
i
6
200
250
300
350
400 450 500
FREQUENCY -
MHz
Fig. '-Power output vs. frequency.
174
9ZCS-20618
600
700 BOO
92CS-13134
c 1 • C2 :
7.8-17 pF
R 1 : 0.56 ohm
Fig.2-RF ampUfier circuit for power-output test at 400 MHz.
File No. 600
40606
RELIABILITY SPECIFICATIONS:
Lot Acceptance Data
Conditioning Screens (100% Testing, see Table II
(bl Attributes Data on Radiographic Inspection
lal Attributes Data on Burn-In
Ie) Variables Data on Burn-In
Group 8 (Lot Sampling, see Table 1111
Group A (Lot Sampling, see Table II)
lal Attributes Data (From a member of the family)
lal Variables Data
Table 1. Description of Total Lot Screening - 100% Testing
TEST
1. Read:
Collector-toEmitter Current
DC Forward-Current
CONDITIONS
MI L-5TD·750
METHOD
CONDITIONS
MIN.
VCE· 30 V.IS· 0
LIMITS
MAX.
UNITS
250
nA
250
nA
10
IC • 300 mAo VCE· 5 V
Transfer Ratio
1051C
2. Temp. Cycling
3. High-Temp. Storage
TA· 200°C. t · 72 hrs.
200S
4. Acceleration
5. Helium Leak
S. Gross Leak
Ethylene Glycol,
Temp. "" 150o C,
t::: 155min.
7. Serialization
8. Radiographic
Inspection
9. Read and Record:
Collector-toEmitter Current
DC Forward-Current
Transfer Ratio
10. Reverse-Bias Age
11. Read and Record
Reverse-Bias End
Points
12. Power Age
13. Read and Record
Power-Age End
Points
VCE· 30 V. IS • 0
IC· 300 mAo VCE • 5 V
10
TA· 150°C. VCS· 50 V.
t =96hrs.
See Table 1 A.
TA· 25°C. VCS· 30 V.
t = 340 hrs. Po = 2.6 W free air
Interim down period = 168 hrs.
See Table 1 A.
14. Read and Record
Subgroups 2, 3 of
Group A; Sample
Subgroup 4 of Group A
175
40606
File No. 600
Table 1A. Power Age and Reve ..... Bias Age
MIL·STD· 750
SYMBOL
TEST
Coliector·Cutoff Current
LIMITS
CONDITIONS
METHOD
ICED
3041
VCE=30V,IB=D
hFE
3076
VCE = 5 V, IC =300
DC F orward·Current
Transfer Ratio
rnA pulsed
UNITS
MIN.
MAX.
-
250
nA
-
-
10
Delta (~) Limits:
I CEO and hfE of Table IA shall be retested after each burn-in test and the data recorded for all devices In the lot.
The tests measured shall not have changed during each burn·in test from the initial value by more than the specified
amount as follows:
l\"I CEO = ± 100% or 25 nA. whichever is greater
~hFE= ±20%
All transistors that exceed the delta
(1\) limits or the limits of Table IA after each burn-in test shall be removed
from the lot and the quantity removed shall be recorded in the lot history.
Table II. Group A Electrical Sampling Inspection
MIL·STD·750
LTPD
EXAMINATION OR TEST
METHOD
10
2071
-
-
Subgroup 2
-
30410
VCE = 30 V, IB = 0
Collector-to· Base Breakdown Voltage
30010
IC = 0.5mA,IE =0
Emiller·to·Base Breakdown Voltage
30260
IE = 0.25 mA, IC = 0
30110
Collector·to·Emiller Breakdown Voltage
JOllA
IC =200 mAo,IB = 0
IC = 200 mAO, V BE =-1.5 V,
-
Collector·ta-Emiller Saturation Voltage
3071
IC = 500 mA, IB = 100 mA
DC Forward·Current Transfer Ratio
3076
IC = 300 mA, VCE = 5 V
-
Second Breakdown Collector Current
-
VCE =28 V, t = 1 5 pur,e
-
V CB =30V,I B =0
-
Subgroup 3
ICEO
-
Circuit Forward Current Transfer Ratio
See fig. 3.
IC = 250 mA, VCE
f = 100 MHz
= 28 V.
VCE = 28 V, PIE =4W.
I =400 MHz
Subgroup 4
Collector-Cutoff Current
DC fnrward·Current Transfer Ratio
3076
= 50%
b Measured at a current where the breakdown Yoltage is a minimum
176
-
250
V(BR)CEO 40b
-
b
VIBRICEV 65
-
V(BR)EBO
4
VCE (satl
-
I
nA
V
V
V
V
V
hFE
10
-
-
ISlb
0.33
-
A
Cobo
-
20
pf
hIe
2.4
-
-
POE
10
-
W
-
ICBO
-
250
-
hFE
10
-
IS
30360
TA = 1500 C ± 30 C,
VCE=JOV
TA =.550 C ± 30 C,
IC = 300 mAo V CE • 5 V
o Pulsed through a 25 mH inductor; duty factor
65
5
3236
Common-Emitter, Small-Signal Short
RF Power Output (Min. Eff. = 45%1
- -
V(BR)CBO
RBE =330
Output Capac itance
UNITS
MAX.
5
Collector·Cutoff Current
Collector·ta-Emitter Breakdown Voltage
LIMITS
MIN.
Subgroup 1
Visual and Mechanical Examination
SYMBOL
CONDITIONS
pA
-
File No. 600
40606
Table III. Group B Environmental Sampling Inspection
MIL·STD·750
EXAMINATION OR TEST
CONDITIONS
2066
-
Subgroup 1
Physical Dimensions
Subgroup 2
-
2026
Solderability
Thermal Shock (Temp. Cycling)
1051
Seal (Leak Rate)
1071
Terminal Strength
2036
Moisture Resistance
1021
LIMITS
LTPD SYMBOL
METHOD
UNITS
MIN. MAX.
20
IS
5 cycles
_65 0 C to +2000 C
-
-
-
-
-
-
-
-
-
-
-
ICEO
-
-
IXH)"7 almcc/s
-
-
-
-
-
-
250
nA
-
V
End Points:
Coliector·Cutoff Current
-
30410
VCE = 30 V, IB = 0
30110
IC .200mAa ,le=O
DC Forward·Current Transfer Ratio
3076
IC = 300 mA, VCE = 5 V
hFE
10
-
-
RF Power Output (Min, Eff = 45%)
See Fig. 3
VCE =28 V, PIE =4W,
( = 400 MHz
POE
10
-
W
Collector·ta-Emitter Breakdown Voltage
Subgroup 3
Shock
V(BR)CEO 40
15
2016
500 g. 1.0 ms, 5 blows each
orientation:
XI, VI, ZI' V2,(20blows
total)
-Vibration Fatigue
2046
Vibration. Variable Frequency
2056
-
Constant Acee ler ali on
2006
20,000 g VI, V2
1031
T stg = + 200 0 C, t = 1000 hrs.
Coliectm·Cutoff Current
30410
VCE = 30 V, Ie = 0
Collector·ta-Emitter Bleakdown Voltage
30110
Nonoperating
-
-
-
-
-
-
-
-
-
-
-
End Points:
(Same as Subgroup 2)
Subgroup 6
High Temperature Lile (Nonoperating)
_.
End Points:
DC Forward-Cuneot Transfer Ratio
3076
RF Power Output (Min. Ell. = 45%)
IC =200mAa,l s =0
-
IC = 300 mA, VCE = 5 V
-
V CE =28 V, PIE = 4W,
-
f =400 MHz
-
2.5
JJA
40
-
V
hFE
9
-
-
POE
10
-
W
-
-
-
ICEO
V(BR)CEO
Subgroup 7
Operating Life
SteaQ.,.~State
DC
End Points:
1026
Vcs=28V,PD=4W,
TA = 170°C
-
(Same as Subgroup 6)
a Pulsed through a 25 !ill inductor; duty factor = 50%
177
File No. 600
40606
DIMENSIONAL OUTLINE JEDEC TO-60
MILLIMETERS
INCHES
SYMBOL
I 0.215
A
A,
ob
00
..,
0o,
E
F
J
T
I
I
i
U1
J
oM
N
N,
r
oW
r-).--J.;:__________"J--i-.._,
A'
SEATI~G
PLANE
_.;
-~,
r
+M
MIN.
-
0:030
0.360
0.320
0.424
0.185
0,090
0.090
0.355
0.163
0.375
0.1658
MAX.
MIN.
MAX.
0.320
0.165
0.046
0.437
0.360
5.46
8.13
-
0.437
10.77
4.70
2.29
2.29
9.02
4.14
9.53
4.19
1.11
11.10
9.14
11.10
5.46
2.79
3.43
0.215
0.110
0.135
0.480
0.189
0,455
0.078
0.1697
0.762
9,14
8.13
I
4.212
NOTES
2
4
2
,
12.19
4.80
11.56
'.98
4.310
3.5
NOTES:
1. Dimension does not include sealing flanges
2. Package contour'optional within dimensions specified
3. Pitch diameter - 10·32 UNF 2A thread (coated)
4. Pin spacing perimts insertion in any socket having a
pin'circle diameter of 0.200 in. (5.08 mm) and con·
tacts which will accommodate pins with a diameter
of 0.030 in. (0.762 mm) min •• 0.046 in.ll.17mm) max.
6. The tORlue applied to a 10·32 hex n'ut auembled on the
thread during installation should not exceed 12 inchpounds.
TERMINAL CONNECTIONS
Mounting Stud, Case, Pin NO.1 - Emitter
Pin No.2 - Base
Pin NO.3 - Collector
178
oornLJD
RF Power Transistors
Solid State
Division
Application Note
AN-6229
Microwave Power-Transistor Reliability
as a Function of Current Density
and Junction Temperature
by S. Gottesfeld
Questions concerning the effect of electromigration·related
failure modes on the life of microwave power transistors using
an aluminum metallization system are frequently asked. This
Note answers these questions as they pertain to RCA microwave
power transistors. First, the design aspects of these transistors
which aid in reducing the incidence of electromigration failure
to a negligible level under normal operating conditions are dis·
cussed. Second, supporting life· test data on commercial·level
RCA microwave power transistors is presented. The lifetime
of the products in this line can be predicted from the data as a
function of current density and junction temperature - the
two main factors involved in electromigration failure modes.
Electromigration
Electromigration of the aluminum in the presence of high·
current densities and elevated temperatures is well known! and
results from the mass transport of metal by momentum ex·
change between thermally activated metal ions and con·
ducting electrons. As a consequence, the original uniform aluminum film reconstructs to form thin conductor regions and ex·
truded.appearing hillocks that may cause device degradation.
The electromigration process can be accompanied by the
dissolution of silicon into the aluminum. This dissolution
usually occurs during heat treatments employed in transistor
manufacturing until the aluminum·silicon saturation point is
reached. Therefore, little silicon can dissolve when the device
is in n0Tl1U11 operation. At high.current densities and elevated
temperatures, however, the silicon ions which were diffused
into the aluminum during the manufacturing process can
be transported along with' the aluminum ions undergoing
electromigration away from the silicon·aluminum interface
and into the aluminum. This situation allows further diffusion
of silicon into the aluminum and leads to the eventual failure
of the transistor junctions2.
RELIABILITY DESIGN FEATURES
Overlay-Transistor Construction
The basic transistor construction used by RCA for rf power
transistors is the "overlay" design. The emitters in this type
of device are separated into many discrete sites which are paral·
leled for high·power performance. The overlay configuration
provides the high ratio of effective emitter periphery to base
area3 needed for high-power generation at microwave frequencies. In addition, this structure has the advantage of
permitting lower current densities in the emitter metallizing stripes than other high-frequency structures. This
advantage results from .the relatively broad emitter-metal
stripes which interconnect the discrete emitters. These
stripes are typically 35 microns wide compared to 3 to 5
microns for other interdigitated or matrix designs. Further·
more, the separation of the emitter- and base-metal fingers
is 3 to 4 times greater in the overlay structure than competitive.
structures. This separation permits the deposition of thicker
metal layers with greater cross-sectional areas; and further
reduces current densities.
Polycrystalline Silicon Layer (PSL)
Another advantage of the overlay transistor structure with its
broad emitter fingers and non-critical metal-definition is that
it is readily adaptable to the introduction of additional conducting and insulating layers between the aluminum metallization and the shallow diffused emitter sites required for
microwave performance. RCA has developed a polycrystalline
silicon layer (PSL), shown in Fig.l, which is deposited over the
emitter sites and under the aluminum metallization. The PSL
forms a barrier between the aluminum emitter finger and the
oxide insulating layer over the base; the barrier minimizes
failures caused by the interaction of aluminum with silicon
dioxide. In addition, the PSL layer' helps to minimize thermally induced failure modes by providing a barrier between
the aluminum and the shallow-emitter diffused region to
prevent "alloy spike" failures; PSL also increases the distance
that the silicon ions must travel from emitter-site region to
metallization, Fig.I. Therefore, the amount of silicon that can
be diffused into the aluminum is limited, and the possibility of
device failure as a result of the electromigration of the silicon
in the aluminum is reduced.
11-73
179
9
2
2
~
N
A
___________________________________________________________
gigahertz chain of microwave power devices are also site·
ballasted, and are also rated at a 10: I VSWR capacity.
Fig. 1 - Cross section of (In overlay transistor showing the polysi/icon
layer (PSL) between the metallization and emitter sites, and
how emitter ballasting may be placed in series with each emit·
ter sire by controlling the doping and contacting geometry of
thePSL.
Emitter-Site Ballasting
RCA has utilized the PSL technology as a medium to intro·
duce emitter·site ballasting into its microwave power transistors. Emitter-site ballasting permits more uniform injection across the transistor chips by reducing hot·spotting. By
oontrolling the' resistivity of the PSL and restricting the contacting geometry of the aluminum to the PSL layer, a ballast
resistor is placed in series with each emitter site, as shown in
Fig.1. These resistors function as negative·feedback elements
to control that portion of the transistor that is drawing excessive current. Since the overlay construction results in an
emitter thatis segmented into many sites which are connected
in parallel, each hot-spot may be isolated and controlled.
Furthermore, the large number of resistors in parallel mini·
mize the effects of excessive emitter resistance on input impedance and gain. In fact, one microwave transistor, the
type 2N5921, which had low levels of emitter-site ballasting
added to its structure, exhibited a 35-percent improvement in
power output for the same drive level. At the same time, the
measurement of the de safe-operating area, as defined by a
200 0 C hot-spot junction temperature. (infrared measurement),
indicated an approximate doubling of the allowable current at
15 volts (see Fig.2).
Glass-Passivated-Aluminum Metallization
The standard metallization system used on all commercial
RCA microwave power transistors consists of an evaporated
aluminum-silicon film which is defined by means of photolithographic and chemical-etching techniques. The addition
of silicon to the aluminum brings the state of the metallization closer to the aluminum·silicon saturation point and
retards the electromigration of silicon into the aluminum.
Aluminum electromigration is also significantly retarded by
the deposition of a glass passivation layer over the aluminum
film subsequent to the definition procedures. It has been
shown! that the use of glass passivation results in a 40·percent
increase in the activation energy required before eleclromigration can begin. The silicon-dioxide layer also protects the
aluminum from contamination and from scratches or smears
that may occur during device assembly.
OPERATING·LIFE-TEST PROGRAM
Test Conditions
An accelerated operating-life-test program was undertaken to
study the effects of electromigration at various current densi·
ties on the lifetime of RCA microwave power transistors.
DC current-voltage conditions were used since electromigration is responsive to the de componenls of the total waveform used in rf applications, i.e., electromigralion is effecled
by the unidirectional components of the field. Tesls were run
at three different emitter-stripe current densities (JE) with each
current density in turn run at three different peak junction temperatures (Tj); all tests represented stress levels above normal-
"'
2
..'~"
TC"'IOO·C
TJ"'200·C
:i 1000
..J
;;
I
u
~
•
I\,
6
I\'
!::!
It is also known that hot-spotting under rf conditions in·
creases as the VSWR increases4. Device failures which occur
under high VSWR conditions at the output are often related
to a forward-bias second·breakdown failure mechanism which
is characterized by extremely high localized currents. Thus, it
could be expected that an emitter·ballasted transistor would
have greater resistance to failure under highYSWR conditions,
such as those encountered in some broadband amplifiers. In
fact, the 2-gigahertz power transistors which are site-ballasted,
types 2N6265 and 2N6266, have been characterized for their
ability to withstand ~: I VSWR at all phases at rated power;
the 2N6267 has been characterized at a 10: I VSWR. The 3-
180
...
i:l0:
4
0:
il
0:
o
2
~
o
u
1
2
4
I~'TE BALLASTED
rlrE~~
6
4
• 10
COLLECTOR-BASE VOLTAGE (VCB)-VOLTS
B 100
92($-22511
Fig.2 - DC infrared safe-area for ballasted and unballasted microwave
transistor (2N5921 coaxial packaged).
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ AN-6229
400
use conditions. Peak junction temperature was determined by
infrared scanning of the transistor pellet at each life-test
condition. Table I shows the matrix of test conditions. The
sarnple size per test condition ranged between 10 and 15
units. A total of 114 units were tested.
-
350
300
~
250
i
1"
20 0
~
"";.
40 HI.
OUTPUT TRANSISTOR CAN BE CALCULATED
FROM PHAV)
FROM ..
=;
~
Po
~~M
~.,\"
AND EFFICIENCY
• WHERE Po IS THE OUTPUT
POWER AHD YOM IS THE PEAK VALUE OF THE
OUTPUT VOLTAGE.
FOR EFFICIENCY OERUIHG AT HIGH
FREQUENCIES, see FIG. 8
*~'b~•t
~
e.
·~·H:ih~ 1:!i~.T'-":.....-;t-'t+
i --,-..-- "T"l.
75
i!i
-~'-T
~
50
Q
25
25
"
1S
tOO
125
ISO
CASE TEMPERATURE (Tel _ oc
25
"
100
125
150
1S
CASE TEMPERATURE fTel _ DC
92CS-24211
Fig. 2-Diss;pation (average) derating curve for each output
transistor (for symmetrical waveforms with f
40 Hz).
>
92CS-24272
Fig. 3-Dissipation (dc) derating curve for each output transistor.
TEST ARRANGEMENTS AND PROCEDURES
+37.5 V
-315 V
92CS-24277
Fig. 4- Circuit for measurement of common-mode input impedance.
PROCEDURE FOR MEASUREMENT OF COMMON-MOOE INPUT IMPEOANCE
a) Insert unit
bl Apply ±37.5 V
c) Close 51
d) Adjust signal generator for 1 Von voltmeter Vl
el Open 51
Read voltmeter Vl
V1
g) Input impedance = (10 k)x--
1)
I-VI
Note: Circuit under test must have a heat sink so that T C :::::25 0 C, unless
otherwise noted.
189
HC2000H/ ... _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 789
92CM-24278
Fig. 5- Circuit for measurement of open-loop gain.
PROCEDURE FOR MEASUREMENT OF OPEN· LOOP GAIN
a) Insert unit
b) Apply ±37.5 V
c) Set generator at 1 kHz and adjust until
Vl '" 10Vrms
d) Re.dV2
e) Open-loop gain'" V1/V2
22n
Fig. 6- Circuit for burn-in and life test.
1. BURN·IN (ACCELERATED THERMAL FATIGUE) PROCEDURE
a) Set R 1 '" 0, close 51
b) I nsert unit
c) Apply ± 27.5 V
d) Adjust Rl for 13.0 V AC across load
e) Monitor flange temperature and adjust Rl (if necessary)
so that flange temperature stabilizes at 135°C ±SoC
f) Total power dissipation ~ 35 W
g) Cycle switch 51: time on = 2.5 min., time off = 2.5 min.
h) Cool flange during off-cycle to 4SoC ± 2°C in moving air.
2. L1FE·TEST PROCEDURE
a) Set Rl :::; 0, close 51
b) I nsert unit
c) Apply ±27.5 V
d) Adjust Rl so that flange temperature stabilizes at 75°C max.
e) Cycle switch 51: time on "" 2.5 min .• time off = 2.5 min.
t) Cool flange during off-cycle to 4SoC ± 2°C in moving air.
190
File No. 789 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ HC2000H/ ...
+37.5 V
92CS-24280
Fig. 1- Circuit for measurement
of offset voltage
and quiescent current.
PROCEDURE FOR MEASUREMENT OF OFFSET VOLTAGE AND QUIESCENT CURRENT
A
V
81
b)
"'" DC ammeter 100 mA range
"" DC voltmeter ± 250 mV range
CloseSl
Insert unit
cl Apply ±37.5 V
d) Read offset voltage on voltmeter. Change polarity if required.
el OpenSl
f)
Read positive and negative quiescent current on ammeter.
+ 37.SV
22Q
SIGNAL
GENERATOR
i
SOI'Fi
12V
92CM-24281
Fig.
8- ·Circuit for measurement of closed4oop voltage gain, total harmonic distortion, maximum voltage swing,
maximum power, short-circuit current, bandwidth, and slew-rate.
1. PROCEDURE FOR MEASUREMENT OF CLOSED·LOOP VOLTAGE GAIN
a) Insert unit
b) Adjust signal generator to 1 kHz, V2
cl Apply ± 37.5 V
=0
d) Adjust signal generator for 2 V rms on voltmeter VT
e) Read voltmeter V2
II
Voltage gain = ~
V2
191
HC2000H/ ... _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 789
2. PROCEDURE FOR MEASUREMENT OF TOTAL HARMONIC DISTORTION
8) Aclust signal generator for 15.5 V fms on V1
b) Adjust distortion anatyzer. Record the meter reading as Total Harmonic
Distortion (THO).
3. PROCEDURE FOR MEASUREMENT OF MAXIMUM VOLTAGE SWING AND MAXIMUM POWER
al Adjust signal generatol for maximum output on scope No.1
with no clipping. Read peak voltage 8S maximum voltage swing.
bl Read Vl
V12
c) Maximum power
=-4
4. PROCEDURE FOR MEASUREMENT OF SHORT-CIRCUIT CURRENT
al Lower power supply to ± 26 V
b) Momentarily replace +Ohm toad with O.5-ohm load
c) Scope No.1 must show symmetriCal square wave of less than ± 1.75 V
5. PROCEDURE FOR MEASUREMENT OF BANDWIDTH
al Raise power supply to ± 37.5 V
bl Adjust signal generator at 43 kHz to 2 V fms on V1
c) Adjust distortion analyzer and verify that THO
0.5%
<
6. PROCEDURE FOR MEASUREMENT OF SLEW RATE
8) Replace signal generator with SQuare-wave generator.
b) Adjust generator for 500 Hz and V1 40 V peak-to·peak.
e) Read time required for swing from peak to peak.
d) Slew rate _
40 V
=
--l ri.:~~:~~~
rU5.0B-20.32lt
0.160
14r)
I
Measured time
•
I
136
0.320 0
118.13) lIi.07)
0.040" R
r:::JM\~
L::::FfLLEAD
0.075~
MIN.
StfOULD
BE UNDISTURBED
OVER THIS
LENGTH
92CS-24282
0.125
(3.17)
Fig. 9- Recommended learJ.bending specification.
DIMENSIONS IN INCHES AND
(MILLIMETERS)
92CS-IIl2't
Fig. lO-Socket for u•• with HC2000HI. •••
DIMENSIONAL OUTLINE
fh
rr~fin
.-------T-I-
(TYPl
1
. "_
~,~-I
I
1
2
3
4
,1 .
6
:-.
,,_.
2.5
163.5)
1
(1275
(699)
ITYP.)
OTERMlNALS 6 AND II ARE CONNECTED INTERNALLY
192
0.10
(2.54)
1
1
nCIi
DIMENSIONS IN INCHES AND
(MILLIMETERS)
Pin No.
,-,-
J-
7
B
,
J.~
92CS-18037A2
5
9
10
TERMINAL CONNECTIONS
Connection
o
Negative supply voltage
-VS
Feedback voltage
VFB
VOUT Output voltage
Phase compensation
PC
GND
Ground
Base plate (internal
BP
connection)
Non·inverting input
+VIN
GND
Ground
-VIN Inverting input
Positive supply voltage
+VS
High-Reliability Thyristors
193
High-Reliability Thyristors
RcA offers, on a custom basis, high-reliability versions of a variety of standard-product thyristors (triacs
and SCR's). These devices may be processed and
screened to any of four different reliability levels that are
approximately equivalent to, or exceed, the reliability
classes (JAN, JANTX and JANTXV) defined by
MIL-S-19500. They are supplied in hermetic packages
that meet the stringent mechanical and environmental
requirements of military, aerospace, and critical industrial applications. Fig. 4-1 shows the package options
available for RCA high reliability triacs and SCR's.
Basic Reliability Considerations
RCA high-reliability thyristors are the result of careful design and screening and of careful adherence to
basic reliability-assurance techniques.
A good basic design is essential for devices for which
an assured high degree of reliability is a prime requirement. Any standard-product RCA triac or SCR selected
to undergo high-reliability processing, therefore, is subjected to extensive design evaluations. RCA assesses the
inherent reliability of each device type under conditions
that simulate the types of service for which the device
may be employed in recommended applications.
Testing to failure is one method that RCA uses for
device reliability evaluations. The natural boundaries of
any life-test program used to evaluate device reliability,
however, are time and the number of available samples.
Accelerated testing is an accepted technique used to
obtain meaningful information in a reasonable time from
a limited number of samples. In this testing, the sample
devices are subjected to stresses that exceed rated or
normal operating conditions for relatively short periods
in order to generate failures that would normally occur
under typical conditions over longer stress periods. If
true acceleration exists, the results can be extrapolated to
predict the mean time to failure under typical operating
conditions. A device that survives the abnormal stresses
of accelerated life tests is presumed to be very reliable
when subjected to the less stringent conditions encountered in actual use. RCA uses accelerated life tests in
ev'aluation of high-reliability thyristors.
The operating conditions that a device is subjected to
in an actual system application have an important bearing on its reliability. A numerical expression of reliability is meaningless unless the prevailing electrical,
mechanical, and environmental conditions under which
the reliability was assessed are also specified, because if
these conditions are altered, the numerical value may
also be changed. Reliability specifications, therefore,
must define limit values for the electrical, mechanical,
arid environmental conditions that affect the life or behavior of a device.
RCA defines the limiting operating conditions and
requirements of the system and of the circuit in which a
device is to be used and specifies in detail the necessary
device parameters.
194
The equipment manufacturer must select deVices tor
his system that can safely withstand the mechanical and
environmental conditions they may be expected to encounter in the application. In addition, he must design
his circuits so that the system does not impose any excess
electrical strains that may adversely affect the life or
performance of the devices and thereby reduce over-all
system reliability. Special care must be taken to assure
that no maximum rating of a device is exceeded under
any condition of equipment operation. The equipment
designer should also realize that the maximum and
minimum ratings specified for the devices are worst-case
limits. A reliable equipment design should be conservative so that devices are not operated at or near
maximum ratings.
In the design of equipment and circuits that use RCA
high-reliability triacs and SCR's, the designer should
adhere strictly to the specifications that govern the use of
such devices.
Failure Analysis
The various problems encountered with thyristors
may be categorized in two large groups, as indicated in
the following listings:
1. Manufacturing defects
2. Application faults
a. Overvoltage, surface or bulk
b. di/dt, overvoltage turn-on
(1) di/dt tum-on
(2) Gated turn-on
(3) Gate noise tum-on
c. Gate dissipation, forward-reverse interchanged
cathode
d. Surge
e. Overload
f. Hermeticity
Manufacturing defects, and the required corrective
actions, are clearly the responsibility of the device manufacturer. In application defects, the user and the manufacturer have a joint responsibility. Experience has
shown that, in general, application defects outnumber
design or manufacturing defects by at least an order of
magnitude. Such problems can usually be solved, however, through careful analysis and close communication
between manufacturer and user.
Applications faults fall into several general
categories. The first and most prevalent is that arising
from overvoltage. Overvoltage damage can be either in
the bulk of the device, at defects in the crystal, at diffusion irregularities, or at localized spots on the surface.
The concentration of power dissipation at these small
areas causes material degradation in either the silicon or
the encapsulating materials at the edge. Closely associated with overvoltage turn-on, is a di/dt stress that
results from turn-on initiated by the overvoltage. If overvoltage tum-on is accomplished without damage within
the chip, a danger is still present in that the current
Appendix
(Tn
JY
-.t
I ..
H-1600
>.-~.-)
',--,
Stud!
TO-4S
TO-S
with Heat Spreader
H-1599
"
'~H-1601
Press-Fit
Isolated..stud
TO-S
with Heat
Radiator
TO-S
TO-S
low-Profile
(eF)
"..
/
i
TO-3
TO-66
t"_~
Press-Fit
with Flex.
Leads
H-1812
f/
'B
11
1"
~I
'-~l
~~
.-
~~
Stud
with Flex.
Isolated-Stud
with Flex.
Loads
Leads
L~
~H-1813
1(, :qii!f;11
~.
;~ H·1814
Fig, 4-1-Paekages used for RCA high-reliability triaes and SCR's,
195
resulting from the thyristor turn-on is concentrated in the
small area within which turn-on began. Such localized
current conduction can result in over-temperature in a
small area. In turn-on initiated from overvoltage, the
mechanism to cause spreading of the current is not present. The dildt capability for a thyristor turned on from
overvoltage is much lower than the dildt capability of the
thyristor turned on by a gate signal. As a result, even
though the dildt in a circuit might be at a very comfortable level for gated turn-on, it may exceed the overvoltage
turn-on di/dt capability. Often, during an examination of
the damaged area of the chip, it is difficult to determine
whether the failure is caused by the initial overvoltage or
the initial rise of current. Both types of faults result in
small burnt areas through the chip bulk or at the edge.
The di/dt capability for gated turn-on is high but it can
still be exceeded, particularly with very low values of
gate drive. A gated di/dt failure in RCA devices always
occurs at the inside edge of the n-type emitter, which is
the area at which conduction begins. This type of failure
results in a small area of molten silicon. Such a failure
mechanism is easily seen in the chip. Most users today
are conscious of the fact that adequate gate signal must
be provided, particularly in applications involving fast
rising pulses of large magnitude. Frequently, analyses
are made of devices from such circuits in which adequate
gate signal is provided and yet di/dt failures that stem
from inadequate gate signal are found. The conclusion is
that turn-on is initiated by noise in the gate circuit somewhere, and the designer of the equipment must correct
these unwanted signals.
Failure may also result because of gate overdissipation. RCA thyristors have relatively large gates
and robust gate leads, so that a good deal of dissipation is
acceptable. The dissipation limit, however, can be exceeded. A triac will operate as a triac when the gate lead
is inadvertently interchanged with the Main Terminal
No. I. The gate area is much smaller than the Main
Terminal No.1 area, and if full current flows, the gate
will be damaged. Triac gate damage often destroys
blocking voltage in the first quadrant without damage to
the blocking voltage in the third quadrant. A consistent
failure of first quadrant blocking voltage, therefore, suggests gate damage.
Short-time surge failure generally results from a gross
melting of silicon over much of the cathode or main
terminal areas. In some RCA packages for lower-current
devices, the internal leads fuse at several hundred amperes of short-circuit current. Consequently if a device
fails because the internal leads of a device are fused, it
may be assumed that a momentarily shorted load condition existed. Overload results from a long duration of
current in excess of the steady-state rated current which
causes a gradual heat build up. The first area to be
attacked is the ohmic contact system. In an overload
[iiiure, . iiu) --hIgh-temperature solder used on the chip
melts and flows out from under the chip. This flow,
which occurs priorto a resulting gross degradation of the
ohmic contact system and pellet, characterizes overload
failure.
196
Hermeticity failures on hermetic devices generally
lead to the presence of ionizable material in the encapsulated resin next to the surface. This condition leads to
surface current, surface inversion layers, a reduction in a
device blocking-voltage capability, and increased blocking leakage current because of the high surface current.
Therefore, it is particularly important to maintain hermeticity on hermetically sealed devices. For device failure
because of degraded blocking characteristic, a gross and
time leak check is performed before any inspection for
other possible defects.
The most significant factor in the control failures is
careful process control in the factory and communication
between users and manufacturers in application defects.
Basic Reliability Testing
The most important factors in the control of manufacturing defects arise through know ledge of the device
design and tight process control in manufacture. Nothing
that can be done in terms of statistics or testing comes
close to the importance of good process control in manufacture. This control is complemented by reliability
testing to monitor product capability. During the development phase, various reliability tests are conducted
by the product development group. During the early
production phase, the device capability is monitored by
an engineering reliability group. During normal production, the manufacturing-plant quality-control department regularly performs various mechanical, environmental, and life tests. Fig. 4-2 outlines the basic tests and
analyses performed in reliability evaluations of RCA
thyristors.
The high-temperature blocking test exposes the device to the maximum blocking voltage and the maximum
operating temperature. The blocking test is followed by
thermal-fatigue testing during which the rated current is
passed through the thyristor, and the resulting power
dissipation is used to heat the device to the maximum
junction temperature. The current is then interrupted,
and the thyristor is cooled rapidly. Thousands of thermal
cycles are accumulated to verify the mechanical soundness of the pellet and its mounting system.
During the operating life tests, synthetic switching
circuits simultaneously apply maximum current and
maximum voltage to the device at the normal line frequency and maximum rated case temperature. This type
of testing simulates actual operating conditions. Hightemperature storage is used to accentuate instability that
may exist at the surface of the device. Temperature
cycling, surge, vibration, and shock are the familiar
environmental tests used to assess the mechanical
robustness of the package, the pellet, and the leadattachment system. Surge testing stresses the ohmic contact system of the device to assure that low thermal
resistance and an even distribution is maintained under
the surge condition.
During the development phase, these tests are generally performed on a step-stress basis. During the quality
control phase, they are conducted at rated conditions.
I
MECHANICAL
I
ENVIRONMENTAL
I
I
Centrifuge
Impact Shock
Vibration
Lead Fatigue
Lead Pull
Relative Humidity
Moisture Resistance
Salt Atmosphere
Temperature Cycling
I
LIFE
I
High-Temperature Blocking
High-Temperature Storage
Operating Life
Surge
Thermal Fatigue
SELECTED TESTS FOR CORRECTIVE-ACTION
EVALUATIONS
Fig. 4-2-0utline of reliability evaluations performed on RCA thyristors.
The data obtained from life testing can provide some
statistical representation of failure rate. Fig. 4-3 shows
an example of a method used to represent failure rate in
the United States Military Handbook on "Reliability of
Electronic Components." The curves shown present
failure rates for transistors as a function of temperature.
However, because the blocking junctions in thyristors
typically form a p-n-p transistor structure, use of these
derating curves for thyristors is justified when sufficient
test data are available. Different failure rates have been
projected from the statistical summing of experimental
data. A derating curve that describes the failure rate of an
RCA-2N5442 40-ampere triac is superimposed (dashed
line) on the family of transistor derating curves shown in
Fig. 4-3. As indicated by this curve, the failure rate of
the 2N5442 triac (and of other thyristors that have been
studied) is similar to that for other silicon power devices.
Processing and Screening
0.1
NORMALIZED JUNCTION TEMPERATURE X Icooe
~2CS·25056
Fig. 4-3-Failure rates (in failures per 10· hours) for MIL5-19S00 transistors, (for power transistors, 1 watt or greater
at TA = 2S"C muWply values shown by two) and for the
RCA-2NS442 40-ampere triac (dashed line).
RCA high-reliability thyristors· that are subjected to
high-reliability preconditioning and screening in accordance with the Group A, B, and C Sampling Tests as
specified in MIL-STD-750 or special customer requirements can be obtained on a custom basis. These
thyristors can be supplied to four basic reliability levels
that are approximately equivalent to, or exceed, the
reliability classes (JAN, JANTX, JANTXV) defined
by MIL-S-19500.
Fig. 4-4 shows the basic processing steps required for
RCA high-reliability thyristors for each reliability level,
and Table 4-1 lists the screening tests to which these
devices are subjected. Tables 4-2, 4-3, and 4-4 list the
Groups A, B, and C Sampling Tests and the test
methods specified by MIL-STD-750.
197
LEVEL
Fig. 4-4-Basic processing and screening required for RCA high-reliability triacs and SCR's.
Table 4-1-,Screenlng Tests for High-Reliability Thyristors
Test
1. Precap visual
2. Seal and lot identification
3. High-temperature
Storage
4. Temperature cycling
5.
6.
7.
8.
9.
Acceleration
Hermeticily-fine leak
Hermeticity-gross leak
Serialize
Preburn-in eleclricalrecord
10. Preburn-in electrical
11. Burn-in
12. Post burn-In electrical
13. Post burn-in electricalrecord .1's
14. Final electrical
15. Hermeticity-fine leak
16. Hermeticity-gross leak
17. Radiographic
18. External visual
198
Condition
MIL-STO-750
Method
Conditions
20 power
24 hrs. at 150·C
1031
Low temperature
per device
Y1 direction
1051
F
2006
1071
1071
H
0
Screening Levels
1
2
3
4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
24 to 168 hrs.;
100·C to 125·C
X
2076
2071
X
X
X
X
X
X
X
X
X
Table 4-2- Group A Tests
Test
Subgroup
2
2
3
3
3
3
4
4
4
4
4
4
Table 4-3- Group B Tests
MIL-STD-7S0
Method
2071
Visual
4206.1
Forward blocking current
4211.1
Reverse blocking current
High-temp. forward blocking current
High-temp. reverse blocking current
High-temp. gate-trigger voltage or
4221.1
gate-trigger current
4231.2
Exponential rate of voltage rise
Gate-trigger voltage or gate-trigger
current at 25"C
Gate-controlled turn-on time
4223
4224
Circuit-commutated turn-off time
4225
Gate-controlled turn-off time
4226.1
Forward "on" voltage
4201.2
Holding current
Technical Data
Electrical ratings and gate or turn-off-time characteristics for RCA triacs and SCR's for which high-reliability versions can be obtained are shown in the data
charts on the following pages.
MIL-STD-7S0
Method
Test
Reverse gate current
Surge current
Temperature cycling
Thermal shock (glass strain)
Terminal strength
Moisture resistance
AC blocking voltage
4219
4066
1051
1056
2036
1021
Table 4-4- Group C Tests
Subgroup
Test
2
2
2
3
4
5
6
Physical dimensions
Shock
Vibration, variable-frequency
Constant acceleration
Barometric pressure
Salt atmosphere
Solderability
Intermillentlife
MIL-STD-7S0
Method
2066
2016
2056
2006
1001
1041
2026
199
ffil(]5LJO
Thyristors
Solid State
Division
2N5441-2N5446
T6400 T6410 T6420 Series
40-A Silicon Triacs
BASIC RATINGS
2N5441
2N5444
T6420B
For Operation with Sinusoidal Supply Voltage at Frequencies
up to 50/60 Hz and with Resistive or Inductive Load.
"REPETITIVE PEAK OFF-STATE VOLTAGE:.
Gate open, T J = -65 to 110°C ... __ ................... .
V DROM
RMS ON-STATE CURRENT (Conduction angle = 360°):
Case temperature
TC = (2N5441-2N5443, T6400N) ................... .
= (2N5444-2N5446, T6401 N) ................... .
= (T6420B, D, M, N) .......................... .
IT(RMS)
PEAK SURGE (NON-REPETITIVE) ON-STATE CURRENT:
For 0,,0 cycle of applied principal voltage
60 Hz (sinusoidal) ................................ .
50 Hz (sinusoidal) ......•..........................
ITSM
RATE OF CHANGE OF ON-STATE CURRENT:
V DM = V DROM ' IGT = 200 rnA, tr = 0.1 /1S .•......•.....
FUSING CURRENT (for Triac Protection):
TJ = -65 to 110°C, t = 1.25 to 10 ms ................... .
di/dt
"PEAK GATE-TRIGGER CURRENT:.
For 1 /1S max...................................... .
"GATE POWER DISSIPATION:
PEAK (For 10/1s max., IGTM< 4 A)
'TEMPERATURE RANGE:
Storage •..........................................
Operating (Case) ..............................•.....
GATE CHARACTERISTICS
DC Gate-Trigger Current: ••
Mode
V MT2
1+
positive
n
IW
negative
negative
TC= 25°C
1111+
positive
negative
negative
positive
RL = 30
DC Gate-Trigger Voltage: ••
For vD = 12 V (de), RL = 30
600
800
40
40
40
A
A
A
300
265
A
A
100
A//1s
450
A 2s
IGTM
12
A
PGM
40
W
T stg
TC
-65 to 150
-65 to 110
°c
°c
TYP.
MAX.
15
50
20
50
30
40
80
80
1.35
2.5
IGT
UNITS
rnA
V GT
Press-Fit (2N5441-2N5443, T6400N)
Stud (2N5444-2N5446, T6401 N)
Isolated-Stud (T6420 Series)
The basic electrical-characteristics curves and test conditions and the mechanical details for these devices are given in
the RCA data bulletin File No. 593 .
• For either polarity of main terminal 2 voltage (VMT2' with reference to main terminal 1.
• For either polarity of gate voltage (V G) with reference to main terminal 1.
* In accordance with JEDEC registration data format (JS·14, RDF2) filed for the JEOEC (2N·Seriesl types.
200
V
n,-
T C = 25°C
PACKAGE:
400
T6400N
T6410N
T6420N
12t
SYMBOL
VG
positive
For vD = 12 V (de)
200
2N5442 2N5443
2N5445 2N5446
T6420D T6420M
V
DDJ]3LJD
Thyristors
2N5567 -2N5570
T4101 T4111 T4121 Series
Solid State
Division
10·A Silicon Triacs
BASIC RATINGS:
For Operation with Sinusoidal Supply Voltage at Frequencies
up to 50/60 Hz and with Resistive or Inductive Load.
'REPETITIVE PEAK OFF·STATE VOLTAGE:.
Gate open, T J = -65 to 100°C ••.••.•..••.•.•..........••..••
'RMS ON·STATE CURRENT (Conduction angle = 360°):
Case temperature (TC) = 85°C ..••.•.•••.•...........•.•..••.
PEAK SURGE (NON-REPETITIVE) ON·STATE CURRENT:
For one cycle of applied prinicpal voltage
60 Hz (sinusoidal) •.•••.•.....•...•••.••••.••...........•
50 Hz (sinusoidal) .•.•......••.•.••...............•..••••
RATE·OF-CHANGE OF ON·STATE CURRENT:
V DM = V DROM ' IGT = 160 rnA, tr = 0.1 /.Is .....•..•.•.•.••....
FUSING CURRENT (for Triac Protection):
T J = -65 to 100°C, t = 1.25 to 10 ms •..........••.•••••......
2N5567
2N5569
T4121B
2N5568
2N5570
T41210
T4101M
T4111M
T4121M
200
400
600
V OROM
V
IT(RMS)
10
A
100
85
A
A
di/dt
150
A//.Is
12t
50
A 2s
4
A
ITSM
PEAK GATE-TRIGGER CURRENT:·
For 1 /.IS max.•..•................•....................•••
'GATE POWER DISSIPATION:
PEAK (For 1 /.Is max., I GTM ';; 4 A .....•.•.••••....••........
PGM
16
W
'TEMPERATURE RANGE:
Storage •.••••...........•...••.•................•••••..•
Operating (Case) .......••••••.•.•.•..•.....•.••....•..••.•
T stg
TC
-65 to 150
-65 to 100
°c
°c
GATE CHARACTERISTICS
DC Gate-Trigger Current: ••
For Vo = 12 V (de),
RL =30n,
TC = 25°C
PACKAGE:
SYMBOL
Mode
V MT2
1+
1111111+
positive
VG
positive
negative
positive
negative
negative
negative
positive
DC Gate-Trigger Voltage:. a
ForV O =12V(dc),R L =30n,TC =25°C
IGTM
TYP.
MAX.
UNITS
IGT
10
10
20
20
25
25
40
40
rnA
V GT
1
2.5
V
Press·Fit (2N5567, 2N5568, T4101M)
Stud (2N5569, 2N5570, T4111 M)
Isolated·Stud (T4121B, 0, M)
The basic electrical·characteristics curves and test conditions and the mechanical details for these devices are given in
the RCA data bulletin File No. 457.
* In accordance with JEDEC registration data format US-14, RDF 2) filed for the JEOEC (2N Series) types .
• For either p'c,larity of main terminal 2 voltage (VMT2) with reference to main terminal 1.
• For either polarity of gate voltage (VG) with reference to main terminal 1.
201
Thyristors
[ID(]3LJ[]
Solid State
2N5571-2N5574
T4100 T4110 T4120 Series
Division
15·A Silicon Trlacs
BASIC RATINGS:
For Operation with Sinusoidal Supply Voltage at Frequencies up to
50/60 Hz and with Resistive or Inductive Load.
"REPETITIVE PEAK OFF·STATE VOLTAGE:.
Gate open, T J = -65 to 100°C ..............•..••••..........
"RMS ON·STATE CURRENT (Conduction angle = 360°):
.
Case temperature
T C = aooc (2N5571-2N5574, T4100M, T4110M) ....•••.•..•..
= 75°C (T4120 Series) .•..•••••••.•••..............•.•.
PEAK SURGE (NON-REPETITIVE) ON-STATE CURRENT:
For one cycle of applied prinicpal voltage
60 Hz (sinusoidal) ••..•.••••.............••••..•.......•.
50 Hz (sinusoidal) ..•.........•••..••••..........•..•....
RATE OF CHANGE OF ON·STATE CURRENT:
V DM = V DROM ' IGT = 160 rnA, tr = 0.1/.15 ..•....••..•.......•
, FUSING CURRENT (for Triac Protection):
T J = -65 to 100°C, t = 1.25 to 10 ms •.•••••....••..•.•..•...•
PEAK GATE'TRIGGER CURRENT:·
For 1 /.Is max .•........•.....••••.......••...•••..•••..•..
"GATE POWER DISSIPATION:
Peak (For 1 /.Is max., IGTM .;; 4 A
"TEMPERATURE RANGE:
Storage ...•...••....••.••....•••..•.•.....•...•.•.•.•••.
Operating (Case) ......•.••.•...•........•..••••.•...•...•.
GATE CHARACTERISTICS
DC Gate·Trigger Current:·-
Mode
V MT2
For V D = 12 V (de),
1+
positive
RL =30n,
1111111+
negative
negative
positive
negative
negative
positive
T C =25°C
T4100M
t4110M
T4120M
200
400
600
15
15
A
100
85
A
A
dildt
150
A//.Is
12t
50
A 2s
ITSM
IGTM
4
A
16
W
PGM
T stg
TC
IGT
V GT
-65 to 150 - - -65 to 100 - - -
TYP.
MAX.
20
50
20
50
35
35
80
80
1
2.5
UNITS
rnA
V
Press·Fit (2N5571, 2N5572, T41ooM)
Stud (2N5573, 2N5574, T4110M)
Isolated·Stud (T4120B, D, M)
The basic electrical·characteristics curves and test conditions and the mechanical details for these devices are given in
the RCA data bulletin File No. 458.
• In accordance with JEDEC registration data format (J5-14, RDF21 filad for the JEDEC (2N·Seriesl Types.
• For either polarity of main terminal 2 voltage (VMn) with reference to main terminal 1.
• For either polarity of gate voltage (V G) with reference to main terminal 1.
202
V
IT(RMS)
DC Gate·Trigger Voltage:··
ForV D = 12V (dc),R L =30n, TC = 25°C
PACKAGE:
2N5572
2N5574
T4120D
V DROM
SYMBOL
VG
positive
2N5571
2N5573
T4120B
°c
°c
Thyristors
2N5754-2N5757
T2303 T2313 Series
[Jl(]5LJD
Solid State
Division
2.5-A Silicon Triacs
BASIC RATINGS:
For Operation with Sinusoidal Supply Voltage at Frequencies
up to 50/60 Hz and with Resistive or Inductive Load.
'REPETITIVE PEAK OFF·STATE VOLTAGE:·
Gate open, TJ = -65 to 100°C ........................ .
RMS ON·STATE CURRENT (Conduction angle = 360°):
Case temperature
2N5754
T2313A
2N5755 2N5756
T2313B T2313D
V DROM
100
200
PEAK SURGE (NON·REPETITIVE) ON·STATE CURRENT:
ITSM
For one cycle of applied principal voltage
60 Hz (sinusoidal) •....•...•.......................
50 Hz (sinusoidal) ........•.....•...•..............
RATE OF CHANGE OF ON·STATE CURRENT:
V DM = V DROM ' IGT = 50 rnA, tr = 0.1 f.J.s .•.............. di/dt
FUSING CURRENT (for Triac Protection):
T J = -65 to 100°C, t = 1.25 to 10 ms ..............••.... 12t
"PEAK GATE-TRIGGER CURRENT:·
IGTM
For 1 f.J.s max .....•..•..........••..................
"GATE POWER DISSIPATION:
PGM
PEAK (For 10 f.J.s max.) ..............•...............
"TEMPERATURE RANGE:
Storage ..•...•..•...........•.....•.......•.••.... T stg
Operating (Case) ................•.•....•.•.......... TC
GATE CHARACTERISTICS
For V D = 12 V (de)
RL = 30 n
T C =25°C
DC Gate-Trigger Voltage:··
For V D = 12 V (de), RL = 30
PACKAGE:
Mode
V MT2
1+
1111111+
positive
negative
positive
negative
400
V
600
IT(RMS)
T C = 70° C (T2303 Series) ....•...................•..
Ambient temperature
T A = 25°C (T2313 Series) •...•......................
DC Gate-Trigger Current: ••
2N5757
T2313M
n, T C = 25°C
A
1.9
A
25
21
A
A
100
A/f.J.s
3
A 2s
A
10
W
-65 to 150
-65 to 100
°c
°c
TYP.
MAX.
UNITS
IGT
5
5
10
10
25
25
40
40
rnA
V GT
0.9
2.2
V
SYMBOL
VG
positive
negative
negative
positive
2.5
Modified JEDEC TO-5 (2N5754-2N5757)
Modified JEDEC TO-5 with Heat Radiator (T2313 Series)
The basic electrical-characteristics curves and test conditions and the mechanical details for these devices are given in
the RCA data bulletin File No. 414.
* In accordance with JEDEC registration data format (JS-14. RDF-2 filed for the JEDEC (2N Series) types .
• For either polarity of main terminal 2 voltage (VMT2) with reference to main terminal 1 .
• For either polarity of gate voltage (VG) with reference to main terminal 1.
203
[JlrnLJ[]
Solid State
Division
Thyristors
T2300 T2302 T2310 T2312
Series
2.S-Ampere Sensitive-Gate
Silicon Triacs
BASIC RATINGS
For Operation with 50160-Hz, Sinusoidal Supply Voltage and Resistive or Inductive Load
REPETITIVE PEAK OFF-STATE VOLTAGE· (Gate Open):
VDROM
TJ = _40°C to +90°C: T2300A, T2310A ___ ... _ ............... .
T2300B, T2310B ...................... .
T2300D, T231 00 ...................... .
TJ = -40°C to +100°C: T2302A, T2312A ........... _ .......... .
T2302B, T2312B ...................... .
T2302D, T2312D ...................... .
RMS ON-STATE
T C = 60° C:
T C = 70°C:
T A = 25"C:
CURRENT (Conduction Angle = 360°):
T2300 series .................................
T2302 series .................................
T2300 series .................................
T2302 series .................................
PEAK SURGE (NON-REPETITIVE) ON-STATE CURRENT:
For one full cycle of applied principal voltage
60 Hz sinusoidal .......................................
50 Hz sinusoidal .......................................
.
.
.
.
IT(RMS)
.
.
PEAK GATE-TRIGGER CURRENT·:
For 1 j.ls max ............................................. .
GATE POWER DISSIPATION:·
Peak (For 1 j.ls max.) ...................................... .
Average:
i~: ~~:~
:::::::::::::::::::::::::::::::::::::
TEMPERATURE RANGE:
Storage ................................................ .
T2300 Series ............................ .
Operating (case):
T2302 Series ............................ .
T2310, T2312 Series (From -40°C) Upper limits
GATE CHARACTERISTICS
DC Gate-Trigger Current: ••
Mode
VMT2
1+
For VD = 12 V (DC),
positive
IIr
RL = 300 11, and
negative
r
TC = 25 C
pOSitive
111+
negative
DC Gate-Trigger Voltage: ••
ForV D = 12V (DC) and RL =3011
At TC = 25°C
400
V
V
V
V
V
V
2.5
2.5
0.35
0.40
A
A
A
A
25
21
A
A
0.5
A
10
0.15
0.05
W
W
W
100
200
400
100
200
°c
°c
°c
-40 to +150
-40 to +90
-40 to +100
See RCA data bulletin
File No. 470
TYP.
MAX.
IGT
3.5
3.5
7
7
10
10
10
10
VGT
1
2.2
SYMBOL
VG
positive
negative
negative
positive
UNITS
mA
V
PACKAGES: Modified JEDEC TO-5 (T2300, T2302 Series)
Modified JEDEC TO-5 with Heat Radiator (T2310, T2312 Series)
The basic electrical·characteristics curves and test conditions and the mechanical details for these devices are given in
the RCA data bulletin File No. 470.
• For either polarity of main terminal 2 voltage (VMT2) with reference to main terminal 1.
• For either polarity of gate voltage (VG) with reference to main terminal 1.
204
Thyristors
[JCl(]3LJD
T2304 T2305
Series
Solid State
Division
400-Hz, 0.5 -A Sensitive-Gate Silicon Triacs
BASIC RATINGS:
For Operation with Sinusoidal Supply Voltage at Frequencies
up to 50160 Hz and with Resistive or Inductive Load
REPETITIVE PEAK OFF-STATE VOLTAGE:.
V DROM
Gate open, T J = -65 to 100°C ___________ • ___________________ _
RMS ON-STATE CURRENT (Conduction angle = 360°):
IT(RMS)
Case temperature T C = 70° C _________________________________ _
Ambient temperature T A = 25°C (without heat sink) ______________ _
T2304B
T2305B
T2304D
T2305D
200
400
PEAK SURGE (NON-REPETITIVE) ON-STATE CURRENT:
ITSM
For one cycle of applied prinicpal voltage
400 Hz (Sinusoidal) _____________________________________ _
60 Hz (Sinusoidal) _______________________________________ _
RATE OF CHANGE OF ON-STATE CURRENT:
V DM = V DROM ' IGT = 60 mA, tr = 0_1 IlS - - - - - - - - - - __ - - - - - - - - - - dildt
FUSING CURRENT (for Triac Protection):
TJ =-65 to 100°Ct= 1.25 to 10ms __________________________ _ 12t
V
0_5
0_4
A
A
50
25
A
A
100
A/lls
2
PEAK
CURRENT:·
For GATE-TRIGGER
1 IlS max_ ____________________________________________
_ IGTM
A
GATE POWER DISSIPATION:
P
Peak (For 1 Ils max_) ______________________________________ _ GM
10
TEMPERATURE RANGE:
Storage _________________________________________________ _
Operating (Case) __________________________________________ _ T stg
TC
GATE CHARACTERISTICS
DC Gate-Trigger Current:· •
For V D = 12 V (de)
RL = 30 n
TC = 25°C
Mode
V MT2
1+
1111111+
positive
negative
positive
negative
PACKAGE:
MAX_
UNITS
IGT
5
5
10
10
25
25
40
40
mA
V GT
1
2_2
V
positive
DC Gate-Trigger Voltage:··
ForV D = 12V (de), RL =30n, TC= 25°C
°c
°c
-50 to 150 - - -50 to 100 - - -
TYP_
SYMBOL
VG
positive
negative
negative
W
Modified JEDEC TO-5
The basic electrical-characteristics curves and test conditions and the mechanical details for these devices are given in
the RCA data bulletin File No_ 441.
• For either polarity of main terminal 2 voltage (VMT2) with reference to main terminal 1.
• For either polarity of gate voltage (VG) with reference to main terminal 1.
205
D\lCIBLJD
Thyristors
Solid State
T2700 T2710
Series
Division
6-Ampere Silicon Triacs
BASIC RATINGS
For Operation with Sinusoidal Supply Voltage at Frequencies
of 50160 Hz, and with Resistive or Inductive Load.
REPETITIVE PEAK OFF·STATE VOLTAGE:·
Gate Open, for TJ = -65 to +100°C .......••••...•..•..•.•••.•
V DROM
RMS ON-STATE CURRENT
For case temperature (T of +75°C
and a conduction angle of 3600 • • • • • • • • • • •
IT(RMS)
cl
••••••••••••••••••••
PEAK SURGE (NON-REPETITIVE) ON-STATE CURRENT:
For one cycle of applied prinicpal voltage ..••••....•.•..........
I TSM
FUSING CURRENT (for triac protection):
TJ = -65 to 100°C, t = 1.25 to 10 ms .......••........•.......•
12t
PEAK GATE-TRIGGER CURRNET:·
For 1 /-IS max..•...........•..•........•.•......•.......•.
IGTM
GATE POWER DISSIPATION:·
Peak (For 1 ps max., I GTM "; 4 A (peak) •..•...•.••...•...•••.•
PGM
TEMPERATURE RANGE:
Storage ...•••.........•..••.......••••..•••......•.•••..
Operating (Case) •....•.............•.••..•..••..•......•..
GATE CHARACTERISTICS
DC Gate·Trigger Current: ••
For VD = 12 volts (DC), RL = 1212
TC = +25°C, and specified triggering mode:
1+ Mode: positive VMT2, positive VGT
111- Mode: negative VMT2, negative VGT
1- Mode: positive VMT2, negative VGT
111+ Mode: negative VMT2, positive VGT
DC Gate-Triggering Volgate: ••
For VD = 12 volts (DC) and RL = 12 12
AtTC=+25°C
PACKAGE:
T stg
TC
T2700B
T2710B
T2700D
T2710D
200
400
V
6
6
A
100
100
A
50
50
4
4
A
16
16
W
A 2s
°c
°c
- - -65 to +150-- - -65 to +100--
SYMBOL
TYP.
MAX.
UNITS
IGT
15
15
25
25
25
25
40
40
rnA
VGT
1
2.2
V
JEDEC TO-66 (T2700 Series)
JEDEC TO-66 with Heat Radiator (T2710 Series)
The basic electrical-characteristics curves and test conditions and the mechanical details for these devices are given in
the RCA data bulletin File No. 351 .
• For either polarity of main terminal 2 voltage (VMT2) with reference to main terminal 1.
• For either polarity of gate voltage (VGT) with reference to main terminal 1.
206
Thyristors
ffil(]3LJO
T4103 T4104 T4105
T4113 T4114 T4115
Series
Solid State
Division
400-Hz, 6,10, & 15-A Silicon Triacs
BASIC RATINGS:
T4103B
T4104B
T410SB
For Operation with Sinusoidal Supply Voltage at Frequencies
up to 400 Hz and with Resistive or Inductive Load.
REPETITIVE PEAK OFF-STATE VOLTAGE:·
Gate open, T J = -SO to 100°C ..•....•...•...•.•...•...
RMS ON-STATE CURRENT (Conduction angle = 360°):
Case temperature
T C = 90°C (T410SB, T410SD, T411SB, T411SD) .; ..... .
= BSoC (T4104B, T4104D, T4114B, T4114D) ....•...
= BO°C (T4103B, T4103D, T4113B, T4113D) ....... .
PEAK SURGE (NON-REPETITIVE) ON-STATE CURRENT:
For one cycle of applied principal voltage
400 Hz (Sinusoidall ...................•.•..•.••.•••
60 Hz (Sinusoidall ..••••..••••..••••.•............
RATE OF CHANGE OF ON-STATE CURRENT:
V DM = VDROM,IGT = 160 rnA, tr = O.l/.1.s ..........•..•
FUSING CURRENT (for triac protection):
T J = -SO to 100°C, t = 1.2S to 10 ms .....•••.•.••..•.••
T4113B
T4114B
T411SB
200
di/dt
12t
For V D = 12 V (de),
RL =30n,
TC= 2SoC
V MT2
1+
positive
1111111+
negative
positive
negative
negative
6
10
lS
A
A
A
200
100
A
A
lS0
A//.I.s
3
A 2s
4
A
16
W
-SO to lS0
-SO to 100
°c
°c
MAX.
UNITS
IGT
20
20
3S
3S
SO
SO
BO
BO
rnA
V GT
1
2.S
V
VG
positive
negative
positive
DC Gate·Trigger Voltage:· •
ForV D = 12V (de), RL =30n, TC= 2SoC
PACKAGE:
V
TYP.
SYMBOL
GATE CHARACTERISTICS
Mode
400
IT(RMS)
PEAK GATE-TRIGGER CURRENT:·
IGTM
For l/.1.s max •••...•....••••..•.•.•..•...•.•........
GATE POWER DISSIPATION:
PGM
Peak (For 1 /.1.5 max., IGTM ",;; 4 A) .•....................
TEMPERATURE RANGE:
Storage ..•.•...•.......•.............•....•••••... T stg
Operating (Case) ...........................••.•....• T C
DC Gate-Trigger Current:··
T4103D T4113D
T4104D T4114D
T410SD T411SD
Press·Fit (T41 03, T4104, T410S Series)
Stud (T4113, T4114, T411S Series)
The basic electrical-characteristics curves and test conditions and the mechanical details for these devices are given in
the RCA data bulletin File No. 443.
• For either polaritY of main terminal 2 voltage (VMT2) with reference to main terminal 1.
• For either polarity of gate voltage (VG) with reference to main terminal 1.
207
OO(]3LJD
Thyristors
Solid State
Division
T6401 T6411 T6421
Series
30·A Silieon Triaes
BASIC RATINGS:
For Operation with Sinusoidal Supply Voltage at Frequencies
up to 50/60 Hz and with Resistive or Inductive Load.
REPETITIVE PEAK OFF-STATE VOLTAGE:·
Gate open, T J ~ -50 to 100°C .. , .....................•.......
RMS ON·STATE CURRENT (Conduction angle ~ 360°):
T6401B
T6411B
T6421B
T6401D
T6411D
T6421D
T6401M
T6411M
T6421M
200
400
600
V DROM
Case temperature
T C ~ 65°C (T6401 Series) ................................ .
~ 60° C (T6411 Seri es) ................................ .
~ 55°C (T6421 Series) ...........•.....................
PEAK SURGE (NON-REPETITIVE) ON-STATE CURRENT:
For one cycle of applied principal voltage
60 Hz (Sinusoidal) ...................................... .
50 Hz (Sinusoidal) ...................................... .
RATE OF CHANGE OF ON·STATE CURRENT:
V DM ~ VDROM,IGT ~ 200 rnA, tr ~ O.l/1s .................... .
FUSING CURRENT (for triac protection):
T J ~ -40 to 100°C, t ~ 1.25 to 10 ms ......................... .
SYMBOL
GATE CHARACTERISTICS
For V D ~ 12 V (de),
RL
~
30 Q,
TC~25°C
V MT2
300
265
A
A
100
AI/1s
450
A 2s
12
A
40
W
-65 to 150
-65 to 100
°c
°c
TYP.
MAX.
50
1+
positive
positive
15
1111111+
negative
negative
20
50
positive
negative
negative
positive
30
40
80
80
1.35
2.5
IGT
V GT
Press·Fit (T6401 Series)
Stud (T6411 Series)
Isolated·Stud (T6421 Series)
The basic electrical-characteristics curves and test conditions and the mechanical details for these devices are given in
the RCA data bulletin File No. 459 .
• For either polarity of main terminal 2 voltage (VMT2) with reference to main terminal 1.
• For either polarity of gate voltage (VG) with reference to main terminal 1.
208
UNITS
VG
DC Gate·Trigger Voltage:··
ForVD~ 12V (de), RL ~30Q, TC~25°C
PACKAGES:
A
A
A
12t
«
Mode
30
30
30
di/dt
PEAK GATE·TRIGGER CURRENT:·
IGTM
For l/1s max ............................................. .
GATE POWER DISSIPATION:
PGM
Peak (For l/1s max., IGTM 4 A) .......•.....................
TEMPERATURE RANGE:
Storage .................................................. T stg
Operating (Case) ........................................... T C
DC Gate·Trigger Current:··
V
IT(RMS)
rnA
V
Thyristors
[RlCTI3LJD
T6404 T6405
T6414 T6415
Series
Solid State
Division
400-Hz, 25 & 40-A Silicon Triacs
BASIC RATINGS. Absolute-Maximum Values:
For Operation with Sinusoidal Supply Voltage at 400 Hz
and with Resistive or Inductive Load.
REPETITIVE PEAK OFF·STATE VOLTAGE:·
Gate open. TJ = -50 to 110°C ............................... .
RMS ON·STATE CURRENT (Conduction Angle = 360°):
'T(RMS)
Case temperature
T C = 85°C (T6405 Series) ••........•.......••.......•......
= 80°C (T6415 Series) ....•••••......•..............•.•.
= 70°C (T6404 Series) •.•......•......••...•...••.......
= 65°C (T6414 Series) ...•..•..•..•..•......•......•••..
PEAK SURGE (NON-REPETITIVE) ON-STATE CURRENT:
For one cycle of applied principal voltage
400 Hz (Sinusoidal) ........•.••.......•............•.....
60 Hz (Sinusoidal) •.....•.............•••.•..•...•.......
RATE OF CHANGE OF ON-STATE CURRENT:
di/dt
V OM = V OROM ' IGT = 200 rnA. \ = 0.1 j.ts .................... .
FUSING CURRENT (for Triac Protection):
12t
TJ = -50 to 110°C. t = 1.25 to 10 ms ......................... .
PEAK GATE-TRIGGER CURRENT:·
For 1 j.ts max •.•.....•..•••...••.........•...........•••...
GATE POWER DISSIPATION:
Peak (For 10 j.ts max .• I GTM .;; 4 A (peak) ...................... .
TEMPERATURE RANGE:
Storage •......••.••.......•......•.••..•••••..•...•......
Operating (Case) _..........................................
GATE CHARACTERISTICS
OC Gate-Trigger Current:··
For Vo = 12 V (dc).
RL = 30
TC = 2SOC
n.
DC Gate-Trigger Voltage:.·
For Vo = 12 V (dc). RL = 30
PACKAGE:
Mode
V MT2
1+
111-
positive
negative
negative
positive
111+
negative
negative
positive
,-
T64040
T64050
T6414D
T641S0
200
400
----------
----
n. TC = 2SOC
V
2S
2S
40
40
A
A
A
A
600
300
A
A
100
A!j.ts
270
A 2s
12
A
42
W
-so to ISO
-SO to 110 - - -
T stg
TC
SYMBOL
VG
positive
T6404B
T6405B
T6414B
T6415B
°c
°c
TYP.
MAX.
UNITS
IGT
20
SO
80
80
80
80
120
120
rnA
V GT
2
3
V
Press-Fit (T6404. T640S Series)
Stud (T6414. T641SSeries)
The basic electrical-characteristics curves and test conditions and the mechanical details for these devices are given in
the RCA data bulletin File No. 487 .
• For either polarity of main terminal 2 voltage IVMT2) with reference to main terminal 1 .
• For either polarity of gate voltage (VG) with reference to main terminal 1.
209
[Rl(]5LJD
Thyristors
T8401B
T8401D
T8401M
Solid State
Division
T8411B
T8411D
T8411M
T8421B
T8421D
T8421M
60-A Silicon Triacs
BASIC RATINGS
For Operation with Sinusoidal Supply Voltage at Frequencies
up to 50160 Hz and with Resistive or Inductive Load.
REPETITIVE PEAK OFF·STATE VOLTAGE:.
Gate open, T J =-40to 110°C .............................. .
V DROM
RMS ON·STATE CURRENT (Conduction angle = 360°):
Case Temperature
T C = 85° C (T8401 Series) ............................... .
.
= 80°C (T8411 Series) ............................... .
= 75°C (T8421 Series) ........•...•.•.................
IT(RMS)
PEAK SURGE (NON·REPETITIVE) ON·STATE CURRENT:
For one cycle of applied principal voltage
60 Hz (sinusoidal) ...................•...•...............
50 Hz (sinusoidal) ...................................... .
ITSM
T8401B
T8411B
T8421B
T840lD
T841lD
T842lD
T8401M
T8411M
T8421M
200
400
600
V
60
60
60
A
A
A
600
500
A
A
300
A//1s
1800
A 2s
RATE OF CHANGE OF ON·STATE CURRENT:
V DM = V DROM ' IGT = 300 mA, tr = O.l/1s ........•............
dildt
FUSING CURRENT (for Triac Protection):
TJ = -40 to 100°C, t = 1.25 to 10 ms .........•................
12t
PEAK GATE·TRIGGER CURRENT:·
For 10 /1S max. . ..•.................•.....................
GATE POWER DISSIPATION
Peak (For 10 /1S max., I GTM ";; 7 A (peak) ..................... .
IGTM
7
A
PGM
42
W
TEMPERATURE RANGE:
Storage ......•...........................................
Operating (Case) .........................•................
Mode
1+
1111111+
V MT2
positive
negative
positive
negative
VG
positive
negative
negative
positive
DC Gate·Trigger Voltage:··
For vD = 12 V (de), RL = 30 n,
TC = 25°C
PACKAGE:
-40 to 150 - - -40 to 1 1 0 - - _
TC
SYMBOL
GATE CHARACTERISTICS
DC Gate·Trigger Current:· •
For vD = 12 V (de)
RL = 30 n
T C =25°C
T stg
UNITS
TYP.
MAX.
IGT
20
40
40
100
75
75
150
150
mA
V GT
1.35
2.8
V
Press·Fit with Flexible Leads (T8401 Series)
Stud with Flexible Leads (T8411 Series)
Isolates·Stud with Flexible Leads (T8421 Series)
The basic electrical-characteristics curves and test conditions and the mechanical details for these devices are given in
the RCA data bulletin File No. 725 .
• For either polarity of main terminal 2 voltage (VMT2) with reference to main terminal 1.
• For either polarity of gate voltage (V G) with reference to main terminal 1.
210
°c
°c
Thyristors
OOClBm
Solid State
Division
T8430 T8440 T8450
Series
SO ..A Silicon Triacs
BASIC RATINGS
For Operation with Sinusoidal Supply Voltage at Frequencies
up to 50/60 Hz and with Resistive or Inductive Load.
REPETITIVE PEAK OFF·STATE VOLTAGE:·
Gate open, T J = -40 to 11 DoC .............................. .
V DROM
RMS ON·STATE CUR RENT (Conduction Angle = 360°1:
Case temperature
T C = 75:C (T8430 Seriesl ................................ .
= 650 C (T8440 Senesl ................................ .
= 55 C (T8450 Seriesl ............................... .
IT(RMSI
PEAK SURGE (NON·REPETITIVEI ON·STATE CURRENT:
For one cycle of applied principal voltage
60 Hz (sinusoidall ...................................... .
50 Hz (sinusoidall ...................................... .
ITSM
RATE·OF·CHANGE OF ON·STATE CURRENT:
dildt
V DM = V DROM ' IGT = 300 rnA, tr = 0.111s .•.••..............•
FUSING CURRENT (for Triac Protectionl:
T J = -40 to 110°C, t = 1.25 to 10 ms ......................... .
12t
PEAK GATE·TRIGGER CURRENT:·
For 10 I1S max. . .................•........................
IGTM
GATE POWER DISSIPATION:
Peak (For 10 I1s max., IGTM <;; 7 A (peakl ...................... .
TEMPERATURE RANGE:
Storage ................................................ .
Operating (Case I .....•...•................................
For
';Po = 12 V (dcl
= 30n
T~=25°C
Mode
1+
1111111+
V MT2
positive
negative
positive
negative
T8430M
T8440M
T8450M
200
400
600
SYMBOL
VG
positive
negative
negative
positive
1;
v
80
80
80
A
A
850
720
A
A
300
All1s
3600
A 2s
A
7
A
40
W
°c
°c
-40 to 150---40 to 110---
T stg
TC
DC Gate-Trigger Voltage:··
For
= 12 0V (dcl, RL = 30 n,
C= 25 C
PACKAGE:
T8430D
T8440D
T8450D
PGM
GATE CHARACTERISTICS
DC Gate·Trigger Current:· •
T8430B
T8440B
T8450B
TYP.
MAX.
UNITS
IGT
20
40
40
100
75
75
150
150
rnA
V GT
1.35
2.5
V
Press·Fit (T8430 Seriesl
Stud (T8440 Seriesl
Isolated·Stud (T8450 Seriesl
The basic electrical·characteristics curves and test conditions and the mechanical details for these devices are given in
the RCA data bulletin File No. 549 .
• For either polarity of main terminal 2 voltage (VMT21 with reference to main terminal 1.
• For either polarity of gate voltage (VGI with reference to main terminal 1.
211
mlCIBLJD
Solid State
Thyristors
Division
2N681-2N690
2S-A Silicon Controled Rectifiers
BASIC RATINGS:
V RSOM
"NON-REPETITIVE PEAK REVERSE VOLTAGE:·
Gate open ..................................... .
35
NON-REPETITIVE PEAK OFF-STATE VOLTAGE:·
V DSOM
Gate open ...................................... .
35
'REPETITIVE PEAK REVERSE VOLTAGE:·
V RROM
Gate open .... _................................ .
25
REPETITIVE PEAK OFF-STATE VOLTAGE:·
V DROM
Gate open ..................................... .
25
ON-STATE CURRENT:
TC = 65°C, conduction angle = 180°:
75 150 225 300 350 400 500 600 720
V
75 150 225 300 350 400 500 600 720
V
50 100 150 200 250 300 400 500 600
V
50 100 150 200 250 300 400 500 600
V
" ::~a~'-::: ::::::::::::::::::::::::::::::::::::::~::~~) ______
25
16
A
A
'PEAK SURGE (NON-REPETITIVE) ON-STATE CURRENT: I TSM
For one full cycle of applied principal voltage ......... .
RATE OF CHANGE OF ON-STATE CURRENT:
150
A
V D = V DROM ' IGT = mA, tr = 0.51's ................ dildt
FUSING CURRENT (for SCR protection):
TJ = -65 to 125°C, t = 1 to 8.3 ms .................. 12t
AIl's
"GATE POWER DISSIPATION:·
Peak Forward (for 10 I's max.) ...................... PGM
Average (averaging time = 10 ms max.) ................ PG(AV)
"TEMPERATURE RANGE:·
5
Storage ........... - - ....... - ........... _....... T stg
Operating (Case) .........................•....... T C
GATE CHARACTERISTICS
SYMBOL
MIN.
DC Gate Trigger Current:
V D = 12 V (de), RL = 30 n, TC = 125°C
IGT
-
DC Gate Trigger Voltage:
V D = 12 V (de), RL = 30n, TC= 125°C
V GT
0_25
= -65 to 125°C
PACKAGE:
-
W'
0.5
W
-65 to 150
-65 to 125
°c
°c
TYP_
MAX_
-
25
-
3
-
UNITS
mA
V
JEDEC TO-48
The basic electrical-characteristics curves and test conditions and the mechanical details for these devices are given in
the RCA data bulletin File No_ 96.
* In accordance with JEDEC registration data format filed for the JEDEC (2N"Series) types.
-These values do not apply if there is a positive gate signal. Gate must be open or negatively biased .
• Any product of gate current and gate voltage which results in a liate power less than the maximum is permitted.
212
Thyristors
2N3228 2N3528
2N3525 2N3529
2N4101 2N4102
mlCIBLJD
Solid State
Division
5-A Silicon Controlled Rectifiers
2N322B 2N3525 2N4101 2N352B 2N3529 2N4102
BASIC RATINGS:
NON·REPETITIVE PEAK REVERSE VOLTAGE
V RSOM
330
660
700
330
660
700
V
REPETITIVE PEAK REVERSE VOLTAGE ......•..•
V RROM
200
400
600
200
400
600
V
REPETITIVE PEAK OFF·STATE VOLTAGE
V DROM
200
400
600
200
400
600
V
ON·STATE CURRENT:
For case temperature (TC) of + 75°C,
and unit mounted on heat sink
Average dc value at a conduction angle of 1BO° ...
RMSValue ..........•...••..............
For free-air temperature (T FA) of 25°C,
and with no heat sink employed
Average dc value at a conduction angle of 1BO° .. .
RMS Value ............................. .
PEAK SURGE CURRENT:
For one cycle of applied voltage •.•..............
FUSING CURRENT (For SCR protection)
For a period of 1 ms to B.3 ms •.....•...••......
RATE OF CHANGE OF ON·STATE CURRENT
V FB = V BOO (Min. value)
IGT = 200 mA, 0.51ls rise time
GATE POWER:·
Peak, Forward or Reverse, for lOlls duration ...••..
GATE CHARACTERISTICS
PACKAGE:
A
A
IT(AV) - - - 3 . 2 - - IT(RMS) - - - 5.0
1.3---A
2.0---A
IT(AV)
IT(RMS)
ITSM
60
A
12t
15
A 2s
200
Allls
di/dt
PGM
SYMBOL
W
13
TYP.
MAX.
UNITS
DC Gate·Trigger Current At T C =+25°C
IGT
B
15
mA(dc)
DC Gate·Trigger Voltage At T C = 25°C
V GT
1.2
2.0
V (de)
JEDEC TO·66 (2N322B, 2N3525, 2N4101)
JEDEC TO·B (2N352B, 2N3529, 2N41 02)
The basic electrical-characteristics curves and test conditions and the mechanical details for these devices are given in
RCA data bulletin No. 114.
*In accordance with JEDEC registration data fo~mat (JS-14. RDF-1) filed for the JEOEC (2N series) tYpes.
_These values do not apply if there is a positive gate signal. Gate must be open or negatively biased.
_Any product of gate current and gate voltage which results in a gate power less than the maximum is permitted.
213
OO(]5LJD
Thyristors
Solid State
Division
2N3650-2N3653,S7430M
35-A Silicon Controlled Rectifiers
2N3650 2N3651 2N3652 2N3653 S7430M
BASIC RATINGS:
V RSOM
'NON-REPETITIVE PEAK REVERSE VOLTAGE:
Gate open ____ ....••.....•....•.. '..•...••....•••.••
NON-REPETITIVE PEAK FORWARD VOLTAGE:
V DSOM
Gateopen ........................................ .
'REPETITIVE PEAK REVERSE VOLTAGE:
V RROM
Gate open ........................................ .
V DROM
'REPETITIVE PEAK OFF-STATE VOLTAGE:
Gateopen ........................................ .
'PEAK SURGE (NON-REPETITIVE) ON-STATE CURRENT:
ITSM
For one cycle of applied principal voltage (60 Hz. sinusoidal) •.
ON-STATE CURRENT:
For case temperature (T = 25°C
Average DC value. conduction angle of 180°· .•.•••.•..•. IT(AV)
RMSvalue •...••....•...•••....•.•.•.••.••..•.... ITJ,RMS)
di dt
'RATE OF CHANGE OF ON-STATE CURRENT:
V DM = V (BO)O' IGT = 200 rnA. tr = 0.1 1'5 .............. .
PGM
'GATE POWER DISSIPATION:
Peak Forward (for 101'5 max.) ..••..•••...•..•.........
TEMPERATURE RANGE:
Storage .......................................... . T stg
Operating (Case) .••......•••••..•...••.......•••.•.. TC
150
300
400
500
700
150
300
100
200
100
200
V
400
500
700
V
300
400
600
V
300
400
600
V
180
A
25
35
A
A
400
AIl's
cl
GATE CHARACTERISTICS
DC GATE TRIGGER CURRENT:
V D =6V(dc),R L =4fl,TC=25°C
SYMBOL
IGT
V D =6V(dc),R L =2fl,TC =-65°C
DC GATE TRIGGER VOLTAGE:
Vo = 6 V (de), RL = 4 fl, TC = 25°C
V D = V DROM ' RL = 200 fl, TC = 120°C
V D =6V (de), RL =2fl,TC =-65°C
PACKAGE:
V GT
Types 2N3650. 2N3651,
2N2652, 2N3653
TYP.
MAX.
MIN.
40
W
-65 to 150
-65 to 120
°c
°c
TypeS7430M
MIN. TYP.
MAX.
-
80
180
-
80
180
150
500'
-
150
500
-
1.5
-
1.5
3
0.25
-
-
-
2
4.5
3
0.25'
-
-
-
2
4.5'
JEDEC TO-48
The basic electrical-characteristics curves and test conditions and the mechanical details for these devices are given in
the RCA data bulletin File No. 408 .
• In accordance with JEDEC registration data format (J8-14. RDF 1 )-applies to the JEDEC (2N Series) types only.
214
UNITS
rnA
V
Thyristors
ffilCIBLJD
Solid State
Division
2N3654-2N3658, 57432M
35-A 5 ilicon Controlled Rectifiers
2N3654 2N3655 2N3656 2N3657 2N3658 S7432M
BASIC RATINGS:
'NON-REPETITIVE
PEAK REVERSE VOLTAGE:·
Gate open _________________________________
_ V RSOM
NON-REPETITIVE
PEAK OFF-STATE VOLTAGE:· _ V OSOM
Gate open _________________________________
'REPETITIVE
REVERSE VOLTAGE:·
Gate open PEAK
_________________________________
_ V RROM
"REPETITIVE
OFF-STATE VOLTAGE:·
Gate open PEAK
_________________________________
_ V OROM
75
150
300
400
500
700
V
75
150
300
400
500
700
V
50
100
200
300
400
600
V
50
100
200
300
400
600
V
ON-STATE CURRENT:
C, conduction angle = 180°:
T
C = 40°
RMS
_____________________________________
_
35
25
A
A
180
A
400
A/p.s
165
A 2s
40
W
-65 to 150
-65 to 120
°c
°c
Average _____ • _____________________________ _ IT(RMS)
IT(AV)
"PEAK SURGE (NON-REPETITIVE) ON-STATE
CURRENT:
ITSM
For o"ne full cycle of applied principal voltage
60 Hz (sinusoidal) -' _________ . _.••.....••.••.
"RATE OF CHANGE OF ON-STATE CURRENT:
Vo = V OROM ' IGT= 200 rnA, tr= 0.1 p.s _. _. _•.•• di/dt
FUSING CURRENT (for SCR protection):
TJ = -65 to 120°C, t = 1 to 8.3 ms __ •••.. _••.. _.
12t
"GATE POWER OISSIPATION:·
PGM
Peak Forward (for 10 p.s max.) ...... _........ _..
'TEMPERATURE RANGE:
Storage __ .... __ . _•. __ ....... _.••. _...••... _ T stg
Operating (Case) _•.....•.••..•••... __ ••.. __ .. TC
TURN-OFF TIME CHARACTERISTICS
• Circuit Commutated Turn-Off Time:
(Sinusoidal Pulse)
VOX = V OROM ' IT = 100 A, pulse duration = 1.5p.s,
dv/dt = 200 Vlp.s, V RX = 30 V min., V GK = 0 V (at
turn-off), TC = 115°C •
PACKAGE:
SYMBOL
tq
MIN_
-
TYP.
MAX •
UNITS
-
10
p.s
JEDEC TO-48
The basic electrical-characteristics curves and test conditions and the mechanical details for these devices are given in
the RCA data bulletin File No. 724.
* In accordance with JEOEC registration data format (J5-14. RDF-U filed for the JEOEC (2N Seriesl types.
-These values do not apply if there is a positive gate signal. Gate must be open or negatively biased .
• Any product of gate current and gate voltage which results in a gate power less than the maximum is permitted.
215
oornLlD
Thyristors
Solid State
Division
2N3668-2N3670 2N4103
12.S-A Silicon Controlled Rectifiers
BASIC RATINGS:
2N3668
2N3669 2N3670
2N4103
NON·REPETITIVE PEAK REVERSE VOLTAGE ••..••.•.••.
V RSOM
150
300
660
V RROM
100
200
400
700
. 600
V
REPETITIVE PEAK REVERSE VOLTAGE .......•••.••••..
REPETITIVE PEAK OFF·STATE VOLTAGE
V DROM
100
200
400
600
V
ON·STATE CURRENT:
For case temperature (TC) of +BO°C
at conduction angle of lBO°C,
Average ..•.......••..•..•••.•...••••.........•.
RMS value .•....••......•............••....•.•..
IT(AV)
IT(RMS)
8
12.5
A
A
PEAK SURGE CURRENT:
For one cycle of applied voltage .•••............•....•••
ITSM
200
A
FUSING CURRENT (for SCR protection)
For a period of 1ms to B.3ms ...•••..•..•.•.....•....••
V
12t
165
A 2s
dildt
200
A//.Is
GATE POWER"
Peak, Forward or Reverse, for 1O/.ls duration
PGM
40
W
TEMPERATURE:
Storage ..•...............................••..•....
Operating (Case) ..••...••..•••••.•.....•.••..•.•....
T stg
TC
-40 to +125
-40 to +100
°c
°c
RATE OF CHANGE OF ON·STATE CURRENT ....••.•.•••••
V FB = V BOO (min. value)
IGT = 200 mA, 0.5/.1s rise time
GATE CHARACTERISTICS
SYMBOL
DC Gate·Trigger Current
At TC = +25°C
IGT
Gate·Trigger Voltage
At TC = +25°C
V GT
PACKAGE:
MIN.
TYP.
MAX.
UNITS
1
20
40
mA (de)
-
1.5
2
V (de)
JEDEC TO·3
The basic electrical·characteristics curves and test conditions and the mechanical details for these devices are given in
RCA data bulletin File No. 116•
• Any values of peak gate current or peak gate voltage to give the maximum gate power is permissible.
216
OU(]5LlD
Solid State
Division
Thyristors
2N3870-2N3873 2N3896-2N3899
56400 56410 564205eries
35-A Silicon Controlled Rectifiers
2N3870 2N3871 2N3872 2N3873 S6400N
2N3896 2N3897 2N3898 2N3899 S641 ON
S6420A S6420B S64200 S6420M S6420N
BASIC RATINGS
"NON-REPETITIVE PEAK REVERSE VOLTAGE:'"
Gate Open .•••..•••••............•...•••...........
NON-REPETITIVE PEAK OFF- STATE VOLTAGE:'"
Gate Open .••••.••••..........•••.........••.••....
"REPETITIVE PEAK REVERSE VOLTAGE:'"
Gate Open .••••••••••..•.......••..•.••.......•.•..
"REPETITIVE PEAK OFF-STATE VOLTAGE:'"
Gate Open .•.•••.•.••........•••••..........••.••..
ON-STATE CURRENT:
TC = 65·C., conduction angle = 180·:
RMS ..•.••.............•..•••.... _ ..•..•.•.....••
Average •..........................•..........••...
PEAK SURGE (NON-REPETITIVE) ON-STATE CURRENT:
For one full cycle of applied principal voltage
60 Hz (sinusoidal) .•..•.•.........•.......•••.••..
50 Hz (sinusoidal) ••.......•••..........•...•.....
RATE OF CHANGE OF ON-STATE CURRENT:
Vo = V OROM ' IGT = 200 rnA, tr = 0.5 liS ............... .
FUSING CURRENT (for SCR protection):
TJ =-40 to 100·C, t = 1 to 8.3 ms .•.......••......•.•.•
GATE POWER DISSIPATION:·
Peak Forward (for 10 lis Max.) ........................ .
"TEMPERATURE RANGE:
~~;:;t~ng '(i:~;~)'::::::::::::::::::::::::::::::::::::
GATE CHARACTERISTICS
V RSOM
V OSOM
V RROM
V OROM
150
330
660
700
900
V
150
330
660
700
900
V
100
200
400
600
800
V
100
200
400
600
BOO
V
35
22
A
A
350
300
A
A
di/dt
200
A/liS
12t
300
A 2s
:T(RMS)
T(AV)
I TSM
40
W
40 to 125
-40 to 100
·C
·C
PGM
T stg
TC
SYMBOL
MIN.
TYP.
MAX.
UNITS
n, TC = -40·C
n, TC = 25·C
VGT
-
1.5
1.1
3"
2
V
DC Gate Trigger Current:
Vo = 12 V (de), RL = 30 n, TC =-40·C
Vo = 12 V (de), RL = 30 n, TC = 25·C
IGT
-
46
25·
80'
40
rnA
DC Gate Trigger Voltage:
Vo = 12 V (de), RL = 30
Vo = 12 V (de), RL = 30
PACKAGE:
1
Press-Fit (2N3870-2N3873, T6400N)
Stud (2N3896-2N3899, T6410N)
Isolated-Stud (S6420A, B, 0, M, N)
The basic electrical-characteristics curves and test conditions and the mechanical details for these devices are given in
the RCA data bulletin File No. 57B .
... In accordance with JEDEC registration data filed for the JEDEC (2N·seriesl types.
.A. These values do not apply if there is a positive gate signal. Gate must be open or negatively biased.
tTC = 60° for isolated-stud package types .
• Any product of gate current and gate voltage which results in a gate power less than the maximum is permitted.
217
OO(]5L7D
Thyristors
Solid State
Division
S2400 Series
4.5- A Silicon Controlled Rectifiers
For Capacitive-Discharge Systems
BASIC RATINGS:
S2400A
NON-REPETITIVE PEAK REVERSE VOLTAGE:'"
V RSOM'
Gate open _•.••••...•••••..............••.•••......
NON-REPETITIVE PEAK FORWARD VOLTAGE:'"
V DSOM
Gate open ..••.•••••••..•..•..••..• _.••••••••••....
REPETITIVE PEAK REVERSE VOLTAGE:'"
V RROM
Gate open '" _.••••••••••.......•....•..•. _......•.
REPETITIVE PEAK OFF-STATE VOLTAGE:'"
V DROM
Gate open •.••.••.••••..•.• _.•....•.•.•.••.••••..••
ON-STATE CURRENT:
TC = 75°C, conduction angle = 180°:
RMS •• _ •.•••••••••••••.....••.....•..•.•.......•• IT(RMS)
Average _•.•..•.•••.....••••.••.•••••..•..••••.••.. IT(AV)
PEAK SURGE (NON-REPETITIVE) ON-5TATE CURRENT:
ITSM
For one cycle of applied principal voltage
50 Hz, (Sinusoidal) _.•.••••••••••.• _•...••..••.••••
60 Hz, (Sinusoidal) •••..•.....•....•.•.•.•.•.•...••
RATE OF CHANGE OF ON-STATE CURRENT:
dildt
V D = V DROM ' IGT = 200 rnA, tr = 0.5ps ............... .
FUSING CURRENT (for SCR Protection):
12t
T J = -40 to 100°C, t = 1.5 to 10 ms ••....••••.•...•...••
GATE POWER DISSIPATION:·
PGM
Peak forward (for 1 ps max.) ••••••••.••..•.••••..•.•.••
TEMPERATURE RANGE:·
Storage •....•••••••••••.••.••••••••••.•.•••.••••.. T stg
Operating (Case) •.•••••••••..•••••••••....••••••••..• T C
GATE CHARACTERISTICS
S2400B S2400D
100
200
150
S2400M
400
600
V
250
500
700
V
100
200
400
600
V
100
200
400
600
V
4.5
3.3
A
A
170
200
A
A
200
Alps
150
A 2s
40
W
-40 to 150
-40 to 100
°c
°c
SYMBOL
TYP.
MAX.
UNITS
DC Gate-Trigger Voltage:
V D = 12 V (de), RL =30n,TC =25°C
V GT
1.1
2
V
DC Gate-Trigger Current:
V D =12V(dc),R L =30n,T C =25°C
IGT
8
15
rnA
PACKAGE:
JEDEC TO-8
The basic electrical·characteristics curves and test conditions and the mechanical details for these devices are given in
the. RCA data bulletin File No. 567 •
... These values do not applV if there is a positive gate signal. Gate must be open or negatively biased .
• Any product of gate current and gate voltage which results in a gate power less than the maximum is permitted.
-Temperature measurement point is shown on the DIMENSIONAL OUTLINE.
218
Thyristors .
[Rl(]5LJD
Solid State
Division
S2600 S2610 S2620
Series
7-Ampere "Low-Profile"
Silicon Controlled Rectifiers
BASIC RATINGS
NON·REPETITIVE PEAK REVERSE VOLTAGE:·
Gateopen ..........•....................................
NON·REPETITIVE PEAK FORWARD VOLTAGE:·
Gate open ............. , ................................ .
REPETITIVE PEAK REVERSE VOLTAGE:·
Gate open .............................................. .
REPETITIVE PEAK OFF·STATE VOLTAGE:·
Gate open .............................................. .
PEAK SURGE (NON·REPETITIVE) ON·STATE CURRENT:
For one cycle of applied principal voltage
60 Hz (sinusoidal) ...................................... .
50 Hz (sinusoidal) ...................................... .
PEAK REPETITIVE ON·STATE CURRENT:t
Duty factor = 0.1%, TC = 75°C
Pulse duration = 5 j1s (min.), 20 j1s (max.) .........•.............
RATE OF CHANGE OF ON·STATE CURRENT:
VDM=VDROM,IGT=200mA,tr=0.5j1s ....................
FUSING CURRENT (for SCR protection):
TJ = -65 to 100°C, t = 1 to 8.3 ms. . . . . . . . . . .. . . .. . . . . . . .. . . . .
GATE POWER DISSIPATION:·
Peak Forward (for 1 j1S max.) ................................
TEMPERATURE RANGE:
Storage .................................................
Operating (Case) ............................•.............
V RSOM
V DSOM
S2600D
S2610D
S2620D
S2600M
5261 OM
S2620M
250
500
700
250
500
700
V
200
400
600
V
200
400
600
V
100
85
100
85
100
85
A
A
100
100
100
A
V RROM
V DROM
V
ITSM
di/dt
----:200----
12t
----40---40
PGM
40
W
40
- - - - - 6 5 to +150-------65to+l00---
T stg
TC
52600 Series
GATE CHARACTERISTICS
S2600B
S2610B
S2620B
°c
°c
52610 S.ri~s
52620 Series
UNITS
SYMBOLS
TYP.
MAX.
TYP.
MAX.
6
15
6
15
rnA
0.65
1.5
0.65
1.5
V
DC GATE TRIGGER CURRENT:
VD= 12 V (DC)
RL =30Q
TC = +25°C
IGT
DC GATE TRIGGER VOLTAGE:
VD=12V(DC)
RL=30Q
TC=+25°C
VGT
_.
PACKAGE:
Low·Profile TO·5 (S2600 Series)
Low·Profile TO·5 with Heat Radiator (S2610 Series)
Low·Profile TO·5 with Heat Spreader (S2620 Series)
The basic electrical·characteristics curves and test conditions and the mechanical details for these devices are given in
the RCA data bulletin File No. 496.
t When rms current exceeds 4 amperes (maximum rating for the anode lead), connection must be made to the case .
• These values do not apply if there is a positive gate signal. Gate must be open, terminated. or have negative bias .
... Any values of peak gate current or peak gate voltage that veild the maximum gate power are permissible.
219
OO(]3LlD
Thyristors
Solid State
Division
53700 Series
5-Ampere All-Diffused
Silicon Controlled Rectifiers
for Inverter Applications
BASIC RATINGS
NON-REPETITIVE PEAK REVERSE VOLTAGE:
Gate Open ______________________________________________ _
V RSOM
REPETITIVE PEAK REVERSE VOLTAGE:
Gate Open ______________________________________________ _
V RROM
REPETITIVE PEAK OFF-STATE VOLTAGE:
Gate Open ______________________________________________ _
V OROM
ON-STATE CURRENT:
For case temperature of +60°C and 60 Hz:
Average DC value at a conduction angle of 180° _______________ _
RMS value ___________________________________________ _
PEAK SURGE (NON-REPETITIVE) ON-STATE CURRENT:
TEMPERATURE RANGE:
Storage _____________ .. __________________________________ _
Operating (Case) _________________________________________ _
TURN-OFF TIME CHARACTERISTICS
Circuit-Com mutated Turn-Off Time,
(Reverse Recovery Time.+ Gate Recovery Time)
VOX = V(BO)O rated value.
ITM = 2A. 50lls min_ pulse width.
VRX = .80 V min .• rise time = 0.1I1s.
dvldt = 100 VIlis. diRldt = 10 Allis.
IGT = 100 rnA at turn-on.
VGT = 0 V at turn-off. and
TC=+800C
PACKAGE:
SYMBOLS
IT(AV)
IT(RMS)
ITSM
837000
S3700M
330
660
700
V
200
400
600
V
200
400
600
V
3_2
3_2
3_2
5
5
5
A
A
- - - -40 to +150--- - - -40 to +100---
T stg
TC
S3700B
Typ_
Max_
S3700B
S37000
Typ_
Max_
S3700M
Typ_
Max_
6
4
6
4
6
JEOEC TO-66
The basic electrical-characteristics curves and test conditions and the mechanical details for these devices are given in
~~~~~~~~
220
UNITS
tq
4
.
°c
°c
liS
OO(]3LJD
Thyristors
Solid State
Division
53701M
5 .. Ampere Silicon
Controlled Rectifier
BASIC RATINGS:
REPETITIVE PEAK OFF-STATE VOLTAGE:
Gate open _______________________________________________ _
RMS" ON-STATE CURRENT (Conduction angle = 180°): .. _......•.. _.
REPETITIVE PEAK ON-STATE CURRENT (0.2 /J.s Pulse Width):
Free-air cooling, f = 500 Hz : ..••.... __ ...... _.......... _...•.
Free-air cooling, f = 5000 Hz .••.•. _•...•. _•.•.••.•......•.. __
Infinite heat sink, f - 10,000 Hz ___ •.....• _.•..• _. _..•..•......
I nfinite heat sink, f = 1,000 Hz ..... _......... _. _.... _... __ ..••
GATE POWER DISSIPATION:
Peak (for 10 /J.s pulse) . __ ••. _.. __ • _..... _.•.. __ ....•..• _.....
TEMPERATURE RANGE:
Storage _..•....•• _.... _. _.. _ .• _... _ .. _•• _.• _. . . . . . . • . . . .. T stg
Operating (Case) .. _..... _.... - - _............ - _...•. _..... - - TC
GATE CHARACTERISTICS
PACKAGE:
600
5
V
A
75
40
40
75
A
A
A
A
25
W
-40 to 125
-40 to 100
°c
°c
MAX.
UNITS
DC Gate-Trigger Current: TC = 25°C
IGT
35
rnA
DC Gate-Trigger Voltage: TC = 25°C
V GT
4
V
SYMBOL
JEDEC TO-66
The basic electrical-characteristics curves and test conditions and the mechanical details for these devices are given in
the R"CA data bulletin File No. 476.
221
oornLJD
Thyristors
Solid State
Division
S3704 S3714 Series
5-A Silicon Controlled Rectifiers
BASIC RATINGS:
83704A S3704B S37040 S3704M 837048
S3714A S3714B S37140 83714M 837148
NON·REPETITIVE PEAK REVERSE VOLTAGE:·
Gate open ..•.•..•..•.•.••.•...••..••.•..•...••..••
NON·REPETITIVE PEAK OFF·STATE VOLTAGE:·
Gate open ••••••..••.••..•.......•.•..........•..•.
REPETITIVE PEAK REVERSE VOLTAGE:·
Gate open .........................................
REPETITIVE PEAK OFF·STATE VOLTAGE:·
Gate open .........................................
ON·STATE CURRENT:
T C = 60~C. conduction angle = 180°:
RMS .............................................
Average •.•..•.•.••.••••.•••..•..•••••.•.•...•...••
PEAK SURGE (NON·REPETITIVE) ON·STATE CURRENT:
For one full cycle of applied prinicpal voltage
60 Hz (Sinusoidal) ................................
RATE OF CHANGE OF ON·STATE CURRENT:
Vo = V OROM ' IG = 50 rnA. tr = 0.1 J,lS ..................
FUSING CURRENT (for SCR protection):
T J = -40 to 100°C. t = 1 to 8.3 ms .....................
GATE POWER OISSIPATION:·
Peak Forward (for 10 J,lS max.) .........................
Peak Reverse (for 10 J,lS max.) .•..•••...••••••..•..•....
Average (averaging time = 10 ms max.) ...................
TEMPERATURE RANGE:
Storage ..•..•.....•••.••••.•••.•.•..•..............
Operating (Case) ....................................
V RSOM
300
500
700
800
V
150
300
500
700
800
V
100
200
400
600
700
V
100
200
400
600
700
V
V RROM
V OROM
5
3.2
A
A
I TSM
80
A
di/dt
200
A/J,ls
12t
25
A
13
13
0.5
W
W
W
-40 to 150
-40 to 100
°c
°c
IT(RMS)
IT(AV)
PGM
PRGM
PG(AV)
T stg
TC
TURN·OFF TIME CHARACTERISTIC
Circuit Commutated Turn·Off Time:
VOX = V OROM ' IT = 2 A. pulse duration = 50J,ls. dv/dt =
100 VlJ.IS. -di/dt = -10 AlJ,ls. IGT = 100 rnA. V GT = 0 V (at
turn·off). T C = 80° C
PACKAGE:
150
V OSOM
SYMBOL
tq
TYP.
MAX.
UNITS
4
8
J,lS
JEOEC TO·66 (S3704 Series)
JEOEC TO·66 with Heat Radiator (S3714 Series)
The basic electrical-characteristics curves and test conditions and the mechanical details for these devices are given in
the RCA data bulletin File No. 690 .
• These values do not apply if there is a positive gate signal. Gate must be open or negatively biased .
• Any product of gate current and gate voltage which results in a gate power less than the maximum is permitted.
222
ffil(]3LJD
Solid State
Division
Thyristors
56200 56210 56220
Series
20 -Ampere Silicon
Controlled Rectifiers
BASIC RATINGS:
NON-REPETITIVE PEAK REVERSE VOLTAGE:
V RSOM
Gate open ...•.....••••.•.•..............••.•..•...
NON-REPETITIVE PEAK FORWARD VOLTAGE:
V DSOM
Gate open ...•...••.••.•••.......•.........••..•...
REPETITIVE PEAK REVERSE VOLTAGE:
V RROM
Gate open ...................•....•..•••..••...•...
REPETITIVE PEAK OFF-STATE VOLTAGE:
V DROM
Gate open ....••.......•....•.....................•
PEAK SURGE (NON-REPETITIVE) ON-STATE CURRENT:
ITSM
For one cycle of applied principal voltage
50 Hz (Sinusoidal) ....•...•..•.•..•. _............ .
60 Hz (Sinusoidal) •••...•..............•.......••.
ON-STATE CURRENT:
For case temperature (T = 75° C, conduction angle of 180°:
Average DC value ...... _...••.•••.•.•...••...••... IT(AV)
RMS value •...•...••.......••...•.........•..•.. IT(RMS)
RATE OF CHANGE OF ON-STATE CURRENT:
V DM = V (BO)O' IGT = 200 rnA, tr = 0.51's ..••..•..•••.•. dildt
FUSING CURRENT (for SCR protection):
12t
TJ = -65 to 100°C, t = 1 to 8.3 rns: ....•.....•....•...••
GATE POWER DISSIPATION:
PGM
Peak Forward (for 10 I's max.) .•••.•.•.•.•.. _ •••.. _••..
TEMPERATURE RANGE:
Storage ........•••••••.•••...••....••...•........• T stg
Operating (Case) ..•.•..•••..••..•.....•........ _...• TC
S6200A
S6210A
S6220A
S6200B
S6210B
S6220B
S6200D
S6210D
S6220D
S6200M
S6210M
S6220M
100
200
400
600
V
150
250
500
700
V
100
200
400
600
V
100
200
400
600
V
170
200
A
A
12.5
20
1\
A
200
AIl's
170
A 2s
40
W
-65 to 150
-65 to 100
°c
°c
cl
GATE CHARACTERISTICS
DC Gate-Trigger Current:
V D =12V(de),R L =30n,T C =25°C
DC Gate-Trigger Voltage:
V D = 12 V (de), Rt.: = 30 n, T C = 25°C
PACKAGE:
SYMBOL
TYP.
MAX.
UNITS
IGT
8
15
mA
V GT
1.1
2
V
Press-Fit (S6200)
Stud (S6210)
Isolated-Stud (S6220)
The basic electrical·characteristics curves and test conditions and the mechanical details for these devices are given in
the RCA data bulletin File No. 418.
223
Thyristors
ffilCTI5LJO
Solid State
Division
S6431M
35-A Silicon Controlled Rectifiers
BASIC RATINGS:
NON-REPETITIVE PEAK REVERSE VOLTAGE
720
V
REPETITIVE PEAK REVERSE VOLTAGE - - - - - - - - - - - - - - - - - - - - - - - - V RROM
600
V
REPETITIVE PEAK OFF-STATE VOLTAGE
600
V
ON-STATE CURRENT:
For case temperature of +65°C
RMS value - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PEAK PULSE CURRENT ___________________ •.•.••..•.....•••..
IT(RMS)
DYNAMIC DISSIPATION:
For case temperature of +65°C .............•...•..•.........•.
GATE POWER:'
Peak, Forward or Reverse, for 10 IlS duration . . . . . . . . . . . . . . . . . . . ..
PGM
TEMPERATURE:
Storage ................................................... T stg
Operating (Case) .....................•......•..•......•....
GATE CHARACTERISTICS
TC
35
A
900
A
30
W
40
W
-65 to +150
°c
-65 to +125
°c
SYMBOL
TYP.
MAX.
UNITS
DC Gate-Trigger Current At TC = +25°C
IGT
25
80
rnA (de)
DC Gate-Trigger Voltage At T C = +25°C
V GT
1.1
2
V (de)
PACKAGE:
JEDEC TO-48
The basic electrical-characteristics curves and test conditions and the mechanical details for these devices are given in
RCA data bulletin No. 247 .
... Any values of peak gate current or peak gate voltage to give the maximum gate power is permissible.
224
High-Reliability
Integrated Circuits
225
High-Reliability Integrated Circuits
RCA offers high-reliability versions of a broad range
of standard COS/MOS and linear integrated circuits
that are processed in accordance with MIL-STD-883
(Military Standard for Test Methods, Microelectronics).
In addition, twenty-seven COS/MOS integrated circuits
are currently being "qualified" to meet the requirements
of MI(-M-3851O (Military Standard for Microelectronics or Integrated Circuits). RCA plans to qualify
a number of its more than 100 standard linear integrated
circuits in accordance with MIL-M-3851O in the future.
RCA also offers a broad line of high-reliability
integrated-circuit chips for use in hybrid circuits. Standard chips are normally inspected to MIL-STD-883,
Method 2010.1, Condition B Visual. Chips subjected
to the more critical Condition A Visual inspections and
to SEM (scanning-electron-microscope) inspections are
also available.
General Considerations
RCA high-reliability integrated circuits are supplied
in hermetically sealed packages. that are specially engineered and developed to meet the requirements of
military, aerospace, and critical industrial applications.
Most COS/MOS devices are supplied in either the dualin-line package shown in Fig. 5-I(a) or the flat pack
shown in Fig. 5-1(b). These packages feature a ceramic
body with a welded cap. They are light in weight and can
safely withstand the thermal shock levels specified by
MIL-STD-883, Method 1011, Condition C. The flat
pack and dual-in-line package have been in use since
1964, and the excellent reliability exhibited by these
packages has been firmly established. Many currently
~
,
'(b;"' ."
'
(e)
Fig. 5-1- Packages used for RCA highreliability integrated circuits: (a)
dual-in-line ceramic package;
(b) ceramic flat pack; (c) TO5'style package.
226
available RCA high-reliability linear integrated circuits
are supplied in the TO-5 style package shown in Fig.
5-1(c).
For all COS/MOS and many linear integrated circuits, the package in which a particular type is supplied is
identified by the letter "D" (dual-in-line ceramic), "K"
(ceramic flat pack), or "T" (TO-5 style in the device
type-number designation. The charts shown in Figs. 5-2
and 5-3 illustrate how the device type number may be
used to define the basic device, the reliability class, the
type of package, and the lead finish for RCA highreliability integrated circuits processed in accordance
with MIL-STD-883 or MIL-M-38510, respectively.
RCA high-reliability integrated-circuit products are
currently being used for a broad variety of functions in
military, aerospace, and critical industrial applications.
Table 5-1 lists a few typical examples of the use of RCA
high-reliability COS/MOS and linear integrated circuits
in satellite and military systems.
Manufacturing Controls
RCA high-reliability integrated circuits are processed in accordance with the Product Assurance Program defined in Appendix A of MIL-M-38510. The
program includes the following items:
. I. A clearly defined procedure for the conversion
of a customer specification into an RCA internal
specification with built-in safeguards to assure the
customer that the delivered parts meet or exceed
his specification requirements.
2. A formalized personnel training and testing program which assures that each operation is performed correctly.
3. A complete inspection of incoming materials,
utilities, and work in process using on-site facilities
such as scanning-electron-microscope, gas-chromatography, atomic-absorption, and X-ray equipm_en~.
4. Maintenance of cleanliness in work areas, e.g.,
all critical operations are performed in a Class 100
environment.
5. Rigorous control over changes in design, materials, and processes with documentation kept in
active files for a minimum of three years and in
inactive fil~s for a minimum of 20 years.
6. Tool and test equipment maintenance and cali bra:
tion in strict accordance with MIL-C-45662,
"Calibration System Requirements".
7. A quality-assurance program in accordance with
MIL-Q-9858, "Quality Program Requirements".
Detailed processing and screening requirements for
RCA high-reliability integrated circuits are defined sub.sequently in the discussions of MIL-STD-883 and.
MIL-M-38510 Requirements.
CD4000AD/l
~I
I
I
High-Reliability Class
Part Number
Package Designation
C04000A
O=Dual-ln·Line
K=Flal Pack
All have solder dipped lead flush
11
11 N
/1 R
/2
Class A
Class A
Class A
Class A
Condition
Condition
Condition
Condition
B Precap Visual
A· Precap VisualtSEM Inspection
B Precap Visual+SEM Inspection
B Precap Visual X-Ray Inspection Omitted
In the Condition A Visual Inspection, the specification for metallization alIgnment
/3
Class B
in section 3.1.1.7 (a) of the general specification will be ch
+1
UNITS
5
2
±D.5
200
10
±20
±2
nA
500
75
+50
±8
nA
mV
Levels /1 and 12 require pre burn-in electrical and post burn-in electrical tests, and delta limits
Level 13 requires pre burn-in electrical test only. The burn-in and operating life test circuit is shown in Fig. 19.
243
CA101, CA101A Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 826
Table II. Final Electrical Tests and Group A Sampling Inspection
EST CONDITIONSA
.LIIVITS
CA1O'
CA 01A
Supply Voltage (v±)
MINIMUM
MAXIMUM
MINIMUM
MAXIMUM
CHARACTERISTIC SYMBOL - 15V unless other·
UNITS
wise specified
-55 +25 125 -55 +25 125 -55 +25 +125 -55 +25 125
Input Offset Voltage
R~10kn
VIO
I RS.;;sOkn
Average Temperature
Coefficient of Input
Offset Voltage
aVIO
Average Temperature
Coefficient of Input
Offset Current
alia
Input Offset Current
110
Input Bias Current
liB
I±
Supply Current
Open· Loop Differen·
tial Voltage Gain
AOL
R~50n
-55°C to +25°C
+25°C to +125°C
V± = 20V
Va - ±lOV RL';;2kn
-
-
-
-
- -
-
-
-
-
-
-
25
50
0.3
-
5
6
-
-
-
- - -
-
- - - - - - -
-
-
-
3
2
3
-
15
-
jJ.vfc
-
- - -
-
0.2
0.1
-
nA/oC
-
-
-
20
10
20
nA
-
-
100
75
100
nA
-
-
4
3.0 2.5
mA
-
4
3
2.5
-
25
-
-
-
25
50
25
-
-
-
-
1.5
-
-
-
-
-
I nput Resistance
RI
-
Output Voltage
Swing
VOPP
RL -10kn ±12 ±12 ±12
IRL 2W ±10 ±10 ±10
Common·Mode
Input·Voltage
Range
VICR
Common·Mode
Rejection Ratio
CMRR
Supply·Voltage
Rejection Ratio
PSRR
V± - 15V
V± 20V
6
-
±12 ±12 ±12
500 200 200
1500 500 500
-
±12 ±12 ±12
±10 ±10 ±1O
-
-
-
-
-
V/mV
-
Mn
-
-
-
-
-
-
-
V
-
-
-
dB
-
-
-
dB
±15 ±15 ±15
RS';;10kn 70
RS';;50kn
70
70
-
-
RS';;lOkn 70
RS';;50kn
70
70
-
-
-
-
-
-
-
-
-
-
80
80
-
-
-
80
80
80
Table III. Group C Electrical Characteristics Sampling Tests
V+=+15V
CHARACTERISTIC
V-=-15V
SYMBOL
Input Offset Voltage
Via
SPECIAL
TEST CONDITIONS
RS';; 10kn
RS';; 50kn
I nput Offset Current
I nput Bias Current
Large,Signal
Voltage Gain
244
CA10l
CA101A
110
CA10l
CA101A
II
CA101
CAIOlA
AOL
Va =±10V
RL =;;>2kn
V
80
"Ambient temperature range TA = -55 to +12SoC unless otherwise specified.
TA = +25°C
mV
LIMITS
MIN.
MAX.
UNITS
-
5
2
inV
-
200
10
nA
-
500
75
nA
50
-
-
V/mV
File No. 826 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA 101, CA101A Slash
(II Series
TYPICAL STATIC CHARACTERISTICS
SUPPLY VOLTAGE (V-)-15V'
~l--H--
.,5
-
-t :\:!=., -1:1:
-: -
ttl_
~-
iI
,,~
~ ¢-~
t
_1-~
tiD
"''"
~
-m!-"'-
.5
g
tt~
2.5
7.5
10
SUPPLY VOLTAGE
12.5
15
17.5
±5
20
tiC
<15
.25
:!:20
!
Ii
I-
'"
l -Ill
.30
OUTPUT CURRENT (leI-rnA
IV:!:I.-V
92C$-23981
92CS-24Q02
Fig. 3-lnput bias current vs. supply valtage for CA 101.
Fig. 4-0urput characteristics for CA 101, CA tOtA.
VOLTA~E SUP~LT
"0
w
100r--
"~
C2
§:
" "-"-
80
~
~~
>--~
[51
60
1'-.
~~
0- 40
"-V
G~
;;
o~
g"
C2'-'-
2 ... 10 R2
20
CI
150 pF
9:?CS-24019
135
~
0
~
S
'I
90
~
ill
45
"--
~
:5
'0.3 MHz
225
180
~~
.
I
I vii,: 15 V
AMBIENT TEMPERATURE IT AI= 25°C
FEEDFORWARD COMPENSATION
~
~
a
-20
10
Fig. 5- Test circuit employing feedforward compensation.
100
10k
lOOk
1M
FREOUENCY (fl-Hz
Ik
10M
100M
92CS-24021
Fig. 6- Voltage gain and phase lag vs. frequencv.
±IS
7.5 -
I
~
1: ±12
~
2.5
~~
::
gl
z
~
0l-~l ~il l~jl lil lil l .1l1l1l1l1l1l
~-25
~>
~
OUTPUT
.
-5
.
~
VOLTAGE SUPPLY IV±1-15V
AMBIENT TEMPERATURE (T AI: 2S-C
FEEDFORWARD COMPENSATION
-7.5
E
"z
~
w
'8
\
1\
'\
VOLTAGE SUPPLY IV±I= ISV
AMBIENT TEMPERATURE I T A)~ 2S"C
FEEDFORWARD COMPENSATION
~
"
~
~
.." '4
>->--
"
0
"-
"-
-........,
a
-10
o
lOOk
TIME (11-1'5
Fig. 7-lnverrer pulse response.
10M
1M
FREQuENCY If I-Hz
92CS-24020
92C5-24022
Fig. 8-0utput voltage swing vs. frequency.
245
CA101, CA101A Slash
(II Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 826
TYPICAL DYNAMIC CHARACTERISTICS AND TEST CIRCUITS FOR TYPE CA101A
Single-Pole Compensation
III
I
i
~
Ii"
'"z
100
-
.
I
0
;:
60
g
151
60
"''''.~
0....
~o
5~ 40
i'''' 20
ffi
::&
f?-
.0
100
lOOk
Ik
10'
FREQUENCY (t) - Hz
I
PHASE
"" ""
0
135
90
Ik
100
10
10k
100
~
i!l
~
'"
0
45
.
~
0
\
-'0
1M
1M
10M
FREQUENCY It 1- Hz
92CS-24023
92CS-24012
Fig. 9-Common·mode rejection ratio v.s. frequency for CA IOtA.
Fig. to-Voltage gain and phase lag vs. frequency.
tI.
••
180
L
4,.('
)
GAIN~ ~
~'
g!
i1;
2.5
~,
~~ ~!
ffi"":J
0
10
80
;:~
~
z 40
8
.. .,
-'
....1'0"..
8
100
~
~~
~~"
VOLTAGE SUPPLY (V±)·15V
AMBIENT TEMPERATURE (TA )=25°C
SINGLE- POLE COMPENSATION
i---
l'!I
'
Oo~
80
:.l
~
I.
120 SOURCE RESISTANCE (R S).\ kn
AMBIENT TEMPERATURE ITA)=25-C
~L!. si.L!LL.' II
1:I tl2
AMBIENT TEMPERATURE ITA1;:-25
SINGLE-~OLE COMPEN.S~TlON
~
";;;z
en ±a
'"~
CI;:-3pF
~
g
"CI =30pF
~
C I ~ iii+'"R2
Cs -3D pF
±4
~
RI Cs
0
92CS-24009
0
2
Ik
4
6'
Fig. "-Test circuit employing singlo-pole compensation.
10.
f\
" -
\.
2
2
4 6'
4
lOOk
FREQUENCY (f)-Hz
6'
1M
4
2
6.
10M
92CS-24013
Fig. 12-0utput IIOltage swing vs. frequency •
.,
I~ IOO~====F===~~
e;
io
80
z
o 601----1-'
~
_
40r---r---t--
10
100
lOOk
Ik
FREQUENCY (f I -
TIME (1)-,...5
1M
Hz
92CS-24010
Fig. 13-Voltage follower (V,. VOl pulse response.
246
Fig. 14-Supply voltage rejection ratio vs. frequency.
10M
File No. 826 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA101, CA101A Slash (I) Series
TYPICAL DYNAMIC CHARACTERISTICS AND TEST CIRCUITS FOR TYPE CA101A
Two·Pole Compensation
120
.,
'"
100
~
.3
225
\
80
~
~~
ffi I 60
ffi--:"
~
~o
B:: 40
9~
RI Cs
z
C5-30 pF
C2-IOCI
20 VOLTAGE SUPPLY
1.15
o CAPACITANCE: (e21. 300 pF
TW~~~IOLE C,~iPENs~rON
Fig. 15- Test circuit employing rwo-pole compensation.
v
AMBIENT TEMPERATURE ITA).2S·C
CAPACITANCE: leI)- 30pF
'"lS
9i?CS-2"'OI5
(vi
-20
10
~
/
135~
~
I
90~
GA~
.. z
CI ~"'iii"+'i2
180U)
~ i'..
II
~
45 ~
I'"I~,O
100
Ik
10k
lOOk
FREQUENCY {t 1- Hz
1M
10M
92CS-2401T
Fig. 1S-Volts/J8 gain and phase lag
1.5
V.$'.
frequency.
.,.
INPUT
OUTPUT
I
1: ±12
1\
~
"z
~
'"~
VOLTAGE SUPPLY (vi ).15 v
AMBIENT TEMPERATURE tTA'''ZS''C
-10
o
10
20
g
.. ••
40
50
60
\
!:;
CAPACITANCE: lell- 30 pF
30
\
••
CAPACITANCE; le2). 300 pF
TWO-POLE COMPENSATION
~
=>
70
80
-
\
I'" . . . 1---.
~
=>
0
92CS-24016
0
Fig. 17- Voltage follower pulse response.
VOLTAGE SUPPLY IV! )-1$ v
AMBIENT TEMPERATURE (TAI-2S-C _
CAPACITANCE: (CI)- 30pF
CAPACITANCE; (C2)' 300 pF
TWO-POLE COMPENSATION
10.
•
100.
FREQUENCY 1ft-Hz
B
I.
92CS-24018
Fig. 18-0utput voltage swing vs. frequency,
+15V
'OVPP.Jllr'kHl
OV··
LJU
92CS-24694
Fig. 1S-Burn-in and operating /ife test circuit for CA 101 and CA 101A.
247
CA101.CA101A Slash (II Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. '826
TYPICAL DYNAMIC CHARACTERISTICS
FOR TYPE CA101
120
."
~
g
'" '"'"
80
-'
"'"
t-'"
60
t::
e-
4O
iSl
ffi"':J
.. z '
9~
is
2;
±I
VOLTAGE SUPPLY (vil""15V
AMBIENT TEMPERATURE ITA)-25°C_
100
20
~
0
::
CI"3pF
~
~
'" '" """'" ",
Ca-3D pF
.."~
±B
g
10
100
Ik
I
k'
IJOk
1M
\CI =3pF
.." ••
00-
'\.
"
0
0
I
I
CI.30pF
~
\
·20
AMBIENT TEMPERATURE (TAI;r2S-C
I
.
0
vLL 5LH !v.'!") II
>
11:12
10 M
Ik
,
• 6. 10k
,
I\.
- .""
• 6. lOOk ,
FREQUENCY
FREQUENCY If 1- Hz
\
,t) -
,
• 6. 10M
92C5-240;15
92CS-24024
Fig. 20- Voltage gain vs. ft-equency.
Fig. 21-0utput voltage swing
...
>
TIME (tl-,..s
92CS-23997
Fig. 22- Voltage follower pulse response.
Laad Finish:
In accordance with MI L-M-38510. paragraph 3.6.2.5, lead finish" AU.
248
1M
Hz
VS'.
frequency •
File No. 827
D\1m5LJD
Linear Integrated Circuits
Solid State
Division
High-Reliability Slash (I) Series
CA107/ ...
Monolithic Silicon
High-Reliability
Operational Amplifiers
For Applications in Aerospace, Military, and Critical Industrial Equipment
• Low input current over temperature range (100 rnA max)
•
CA107S
B-LEAO TO-S
with Dual-in-Lino
CA107T
8-LEAOTD-S
~
Type
formed Leads
(OIL-CANI
H-1787
3D-pF on-chip capacitor provides internal frequency compensation
H-1528
CA107
The RCA-CAl 07 "Slash" (/) Series type is a high-reliability
linear integrated circuit operational amplifier intended for
applications in aerospace, military, and industrial equipment_
It is electricallY and mechanically identical with the standard
type CA107A described in Data Bulletin File No_ 7B5 but is
specially processed and tested to meet the electrical,
mechanical and environmental test methods and procedures
established for microelectronic devices in MIL-STD-BB3.
Max. VIO
(mV)
Max. 110
(nA)
Max. liB
(nA)
Temp.
Range (TA)
°C
3
20
100
-55 to +125
Applications:
a Long-interval integrators
II Timers
• Sample-and-hold circuits
•
Summing amplifiers
• Multivibrators
The CAl 07 'features a 30-pF on-chip capacitor to provide
internal frequency compensation. Low input current over
temperature range (100 nA max.) for the CAl 07 make this
type especially well suited for applications such as long
interval timers and sample-and-hold circuits_
The packaged type can be supplied to six screening levels /1N, /1 R, /1, 12, 13, and 14 - which correspond to
MIL-STD-BB3 Classes A, B, and C. The chip version can be
supplied to three screening levels -/M,/N, and IR.
These screening levels and detailed information on test
methods, procedures and test sequence are given in Reliability Report RIC202A "High-Reliability CA3000 Slash (/)
Series Types Screened to MI L-STD-BB3".
The CA107 is supplied in the standard B-Iead TO-5 style
package ("T" suffix), the B-Iead, TO-5 style with dual-in-line
formed leads ("S" suffix), and in chip form ("H" suffix). It
is a direct replacement for industry type 107 in packages
with similar terminal arrangements.
9-74
VNOTE' PIN 4 IS CONNECTED TO CASE
TOP VIEW
92CS-23982
Functional diagram for TO-5 style packages
249
CA107 Slash VI Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 827
Maximum Ratings. Absolute-Maximum Values at TA - 250C:
D~ SUPPLY VOLTAGE (Between V+ and V- Terminal,):
CA107 ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• "
DC INPUT VOLTAGE •••••••••••••••••••••.••••••••••••••••••••••••••••••••••••••••••••••••••••••••••
(For supply voltages less than ±'Is V. the absolute maximum input voltage is equal to the supply voltage)
DIFFERENTIAL INPUT VOLTAGE ••••••••••••••••••••••••••••.••••••..••••.••••••••••••••••••.•••••.
OUTPUT SHORT·CIRCUIT DURATION
••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••
DEVICE DISSIPATION UP TO TA = 700C •••.••••••••••••••••••••••••••••••••••••••••••••••••••••••••••
Above T A = 7o"C Derate linaarly at •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••
AMBIENT TEMPERATURE RANGE:
Operating ••.•.....••••••••••••••.••••••••••••••.•••••..••.••••.••••••••••••••••••••.•••••••••••.
Storage ••••.•.••.••.••••••••••••••••••••••••••••••••.•••••••••••••••••••••••••••••••••.••••••.••
LEAD TEMPERATURE (During Soldering):
At distance 1116 ±1/32 inch 11.59 ~.79 mm)from case for 10 seconds max. . ••••••••••••..••.•••••.•.•••••••
±15
44
V
V
:1:30
V
Indallnito
mW
500
6.67mW/oC
-55°C to +12sOC
-65 0 C to +15o"C
v·
92CM-23983
Fig. 1-Schematic diagram of CA '07.
250
File No. 827 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA107 Slash II) Series
ELECTRICAL CHARACTERISTICS For Design Guidance Only
TEST CONDIT IONS
CHARACTERISTIC
Input Offset Voltage
Average Temperature Coefficient
of Input Offset Voltage
Input Offset Current
SYMBOL
VIO
Supply Voltage (V±) =
5 V to 15 V
TYPICAL
VALUES
TA = 250 C, RS';;; 50 k.l1
UNITS
0.7
mV
VIO
-55 to + 125 0 C
3
110
TA = 250 C
+25 to +125 0 C
-55 to +25 0 C
1.5
nA
0.01
0.02
nAloC
Average Temperature Coefficient
of Input Offset Current
110
Input Bias Current
lIB
Supply Current
I±
TA = 250 C
30
TA=+1250 C,V±=20V
1.2
!lV/OC
nA
rnA
TA = 250 C, V± = 20 V,
I.B
Open· Loop Differential
Voltage Gain
Input Resistance
Output Voltage Swing
AOL
RI
VOPP
V±=15V,VO=±10V
RL;;'2 kn, TA = 250 C
160
V/mV
4
TA = 250 C
V±=15V,RL=10kn
+14
V±=15V,RL=2k.l1
±13
M.I1
V
Common·Mode Rejection Ratio
CMRR
RS';;; 50 kn
96
dB
Supply·Voltage Rejection Ratio
PSRR
RS';;;50 kn
96
dB
Table I. Pre Burn·in Electrical and Post Burn-in Electrical Tests, and Delta Limits *
ELECTRICAL CHARACTERISTICS, at TA = 25°C,
CHARACTERISTIC
V- = -;5 V
TEST CONDITIONS
MIN.
LIMITS
MAX. MAX."
UNITS
Input Offset Voltage
VIO
-
2
±0.5
mV
Input Offset Current
110
-
10
±2
nA
75
±B
nA
Input Bias Current
*
SYMBOL
v+ =+15 V,
Levels
Level
II
/1 and 12 require pre burn-in electrical and post burn-in electrical tests, and delta limits.
13 requires pre .burn-in electrical
test only. The burn-in and operating life test circuit is shown in Fig. 4.
251
CA107 Slash
VI Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
File No. 827
Table II Final Electrical TeslS and Group A Sampling Inspection
TEST CONDITIONS
CHARACTERISTIC
SYMBOL
Input Offset Voltage
V IO .
LIMITS
Supply Voltage (V±)
=5Vto15V
TA = 25°C, RS <0;50 kU
MINIMUM
MAXIMUM
UNITS
·55
+25
+125
·55
+25
+125
-
-
-
3
2
3
mV
Average Temperature
Coefficient of Input
Offset Voltage
aVIO
-
-
-
15
15
15
/lVrC
Input Offset Current
110
-
-
-
20
10
20
nA
Average Temperature
Coefficient of Input
Offset Current
aiiO
-
-
-
0.2
-
0.1
nAloC
Input Bias Current
liB
-
100
75
100
nA
I±
-
-
-
Supply Current
-
4
3
2.5
mA
V±= 15V. VO =±10V
R L;;;'2 kU. TA = 25°C
25
50
25
-
-
-
V/mV
-
1.5
-
-
±12
±12
±12
-
-
V±= 15V. RL =2kU
±10
±10
±10
-
-
MU
V±= 15V. RL = 10kU
Open-Loop Differential
Voltage Gain
AOL
Input ·Resistance
RI
Output Voltage Swing
VOPP
V
Input Voltage Range
V ICR
V±=20V
±15
±15
±15
-
-
Common-Mode
Rejection Ratio
CMRR
RS
"'-
~
OJ
g
40
"'"-0
Q.
0
';1
ffi
g;
20
""""'-
0
-20
10
0
,
10
,
10
\
I
]:
,
10
±12
E
'"z
~
"" '"
,
10
,
10
'"'"
1\
±B
~
\
0
>
0-
=>
Q.
±4
"~ r-
!;
0
~
10 6
0
10 7
,
,
6
.
,
10'
FREQUENCY Ifl-Hz
.
r-
6
92CS-23996
92CS-23995
Fig. 2-0pen-/oop differential voltage gain vs. frequency.
,
FREQUENCY (f I-Hz
Fig. 3-0utpur voltage swing vs. frequency.
SUPPLY VOLTAGE (V-)"'15V
.,0
+15V
+5Vjlf
ov
-5V ,·rooo
elN
Hz
SQUARE WAVE
IOkn
:!:5
tiC
tl5
:!:20
t25
±30
OUTPUT CURRENT (Io)-mA
92CS-23987
Fig. 3-0utput voltage swing vs. output current.
92CS-2~1I9
Fig. 4-Burn-in and operating life test circuit.
253
File No. 828
Linear Integrated Circuits
OOCD3LlD
Solid State
Monolithic Silicon
High-Reliability Slash (I) Series
CA10S1 ... , CA10SAI ...
Division
High-Reliability
Precision Operational Amplifiers
For Applications in Aerospace, Military, and Critical Industrial Equipment
Features:
• Maximum input bias current - 2 nA
•
CA10BS,AS
CA108T,AT
8-Lead TO-5
with Dual-In-Line
8-Lead TO-5
Maximum input offset current - 0.2 nA
• Supply current of only 300 p.A, even in saturation
• Maximum input offset voltage of 0,5 mV for "A" suffix types
Formed Leads
H·1787
The RCA-CA 108 and CA 10BA Slash (II Series types are
uncompensated precision operational amplifiers using super-
beta transistors and feature very low offset parameters, high
input impedance, and defined drift rates with temperature
change_ They are intended for applications in aerospace,
military, and industrial equipment, They are electrically and
mechanically identical with the standard type CA 108 Series
described in Data Bulletin File No. 621 but are specially
processed and tested to meet the electrical, mechanical and
environmental test methods and procedures established for
microelectronic devices in MI L-STO-883_
The packaged type can be supplied to six screening levels 11 N, 11 R, 11, 12, 13, and 14 - which correspond to
MIL-STO-883 Classes A, B, and C_ the chip version can be
supplied to three screening levels - 1M, IN, and IR_ These
screening levels and detailed information on test methods,
procedures and test sequence are given in Reliability Report
RIC-202A "High-Reliability CA3000 Slash (I) Series Types
Screened to MIL-STO-883_"
The "A" versions have all the desirable features and
characteristics of their prototypes plus exceptionally low
input offset voltage characteristics_ The CA 108, CA 1OBA, are
direct replacements for industry types 108 and 108A in
packages with similar terminal arrangements_ The CA 108 and
CA 108A are supplied in standard 8-lead TO-5 packages,
8-lead TO-5 packages with dual-in-line formed leads ("01 LCAN"), or in chip form (H suffix)_
Applications:
•
• Multivibrators
• Band-pass filters
• Sample and hold
Instrumentation
• Summing amplifier
• Comparator
vNOTE: PIN 4 IS CONNECTED TO CASE
92CS-22020
Fig. 1-Functional Diagram
ELECTRICAL
CHARACTERISTICS,
MAXIMUM VALUES
ATTA = 25°C
Input Offset Voltage (V IO )
Input Offset Current (110)
Input Bias Current (lIB)
Average Temperature Coefficient
of Input Offset Voltage
(l>VIO/l>T)
Ambient OperatingTemperature Range
CA10BT
CA108S
CA108AT
CA108AS
2mV
0_5 mV
0.2 nA
2nA
15p.V/oC
5p.VtC
-55 to +125°C
9-74
254
FileNo. 828 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CA 108, CA 1 08A Slash (I) Series
Maximum Ratings, Absolute-Maximum Values at TA = 25'C
DC SUPPLY VOLTAGE (Between V+ and V- Terminals):
CA108, CA10BA •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••
DC INPUT VOLTAGE ••••••••••••••.•••••..••••••.••.••••••.•.•.•..•••••.••••••..••..•
(For supply voltages less than ±15 V. the absolute maximum
input voltage is equal to the supply voltage)
DIFFERENTIAL INPUT CURRt:NT •.••.••..••..•..•..••..••.••.•••••••••••.••..••.••.••.•
OUTPUT SHORT·CIRCUIT DURATION •••.••...•.••..••••••.••.•.•••..••••••••••.••••. '" •
DEVICE DISSIPATION •..•.•...•••••.•.•••.•.••....•.....•.••...•...•.•••.•••.•..••...•
AMBIENT TEMPERATURE RANGE:
Operating ... ...................................................................... .
Storage . .......... " ...................... , ....................................... .
LEAD TEMPERATURE (During Soldering):
At distance 1/16 ± 1/32 inch (1.59 ±O.79 mm) from case for 10 seconds max . . . . . . . . . . . . . . . . . . . . .
40
±15-
V
V
±1O
Indefinite
rnA
500
rnW
_55 to +125
_65 0 to +150
'c
'c
+300
'c
0
4
v-
92CM-211Z9
Fig. 2-Schematic diagram for CA 108 and CA IOBA.
255
CA 108, CA108A Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 828
ELECTRICAL CHARACTERISTICS For Design Guidance Only
TEST CONDITIONS
CHARACTERISTIC
SYMBOL
Supply Voltage (VI = ±5 V to ±15 V
Ambient Temperature T A = 25° C
CA10S
CA108A
Typ.
Typ.
Input Offset Voltage
Via
0.7
0.7
Average Temperature Coefficient
of Input Offset Voltage
~VIO
3
1
UNITS
mV
flV/oC
~T
Input Offset Current
110
0.05
0.05
nA
Average Temperature Coefficient
of Input Offset Current
~IIO
0.5
0.5
pAtC
Input
~T
Bia~Current
O.B
O.B
nA
10
+1250 C
T,,=250C
0.15
0.3
0.15
0.3
mA
AV
V=±15V,
Vo = ±10 V, RL ;;'10 kr!
300
300
V/mV
70
70
Mr!
V=±15V, RL = 10kr!
±14
±14
liB
Supply Current
Large·Signal Voltage Gain
TA~
Input Resistance RI
Output Voltage
Va
Common·Mode Rejection Ratio
CMRR
100
110
dB
Supply·Voltage Rejection Ratio
V RR
96
110
dB
V
TABLE I Pre Burn·ln Electrical and Post Burn·ln Electrical Tests and Delta Limits'
ELECTRICAL CHARACTERISTICS, at TA = 25°C,
CHARACTERISTIC
Input Offset Voltage
Input Offset Current
Input Bias Current
* Levels /1 and
Level
256
SYMBOL
VIO
v+= +15 V, V- =-15 V
TEST CONDITIONS
LIMITS
MAX.
MAX..6.
UNITS
CA10B
-
2
,CA10BA
-
0.5
±0.25
-
0.2
±0.05
nA
2
±0.2
nA
110
II
/2 require pre burn-in electrical and post burn-in electrical
13 requires pre
MIN.
tests and delta limits.
burn-in electrical test only. The bum-in and operating life test circuit is shown in Fig. 8.
±1
mV
File No. 828 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA108. CA108A Slash (I) Series
Table II Final Electrical Tests and Group A Sampling Inspection
Test Conditions
LIMITS
CHARACTERISTIC SYMBOL Supply Voltage (V)
CA10S
±15 Volts
MINIMUM
·55
CA108A
MAXIMUM
MINIMUM
+25 +125 -55 +25 +125 ·55
UNITS
MAXIMUM
+25 +125 -55 +25 +125
-
-
-
3
2
3
-
-
-
I
0.5
1
mV
-"T
-
-
-
15
15
15
-
-
-
5
5
5
/lVrC
Input Offset Current
110
-
-
-
0.4
0.2
0.4
-
-
-
0.4 0.2 0.4
nA
Average Temperature
Coefficient of Input
Offset Current
"110
-"T
-
-
-
2.5
2.5 2.5
-
-
-
2.5 2.5 2.5
pArC
Input Offset Voltage
Via
Average Temperature
Coefficient of Input
Offset Voltage
"V IO
liB
-
-
-
3
2
3
-
-
-
Supply Current
10
0.6
0.4
-
Large-Signal Voltage
Gain
AV
-
-
Input Resistance
RI
Input Bias Current
Output Voltage
3
-
-
-
0.8
-
-
V=±15V.
V6=±10V.
R L ;l>10k!l
25
50
25
-
48
80
40
-
30
-
-
Va
±13
±13
±13
- - - - - - ±13
30
V =±15 V.
RL = 10k!l
±13
±13
VI
V = ±15 V
-
2
3
nA
0.8 0.6 0.4
rnA
-
-
V/mV
-
-
-
M!l
-
-
-
V
-
-
-
-
V
CMRR
85
85
85
-
-
-
96
96
96
-
-
-
Common-Mode
Reiection Ratio
-
dB
Supply-Voltage
Reiection Ratio
V RR
80
80
80
-
-
-
96
96
96
-
-
-
d8
Input Voltage Range
±13.5 ±13.5 ±13.5
±13.5 ±13.5 ±13.5
Table III Group C Electrical Characteristics Sampling Tests
TA =+25°C
V+= +15 V
CHARACTER ISTIC
V-=-15V
SYMBOL
Input Offset Voltage
Via
Input Offset Current
110
Output Voltage
Va
Large-Signal Voltage Gain
AOL
SPECIAL
TEST CONDITIONS
CA108
CA108A
R L =10k!l
Vo = 10 V
R L ;l>10k!l
I CA108
I CA108A
LIMITS
UNITS
MIN.
MAX_
-
3
1
mV
-
0_4
nA
±13
V
40
70
-
V/mV
257
CA108. CA108A Slash
(II
Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-...:_ File No. 828
TYPICAL CHARACTERISTICS FOR TYPES CA108 AND CA108A
>
IO"!6
I
4
E
c,.o
AMBIENT TEMPERATURE tTAI-25-C
FREQUENCY IF1 -IDa Hz
~... ,
.
~
g
10,
t;
4
i"""""'"
l"JC-'\..
I
6
!;;
4
~
,
;I
~
V
"'XI"~I-
,
i
>
c 110
z
./
,
~
FOR TEST CIRCUIT, SEE FIG.2
I
1/
6
i!;
.
120
• ,
Icr'
4
10
,
, 10
6
6
6
4
,
107
,
4
90
6 ,
o
20
5
10
15
SUPPLY VOLTAGE IY+,Y-)-V
INPUT RESISTANCE (RI)-n
'2C$-21142
92CS-2J134
Fig. 4- Volrage gain
Fig. 3-lnpur offset voltage .". input resistance.
SUPPLY VOLTAGE:Y+s+l5V,Y-a-15V
I.
100~ r-...
,.
I
80
i'>
!
10
I
~
::>
5
0
40
20
I
>
I
·20
o
2
•
10
6
OUTPUT CURRENT IIo1-mA
..
180
135
/
.".,
.7.... ~'
~
FOR TEST CIRCUITS
SEE FIGS 2 AND 3
0
' ,:'
Ii'
I
60
GAIN-PHASE---
~~~
C,"'OO OF "-
!:
i!:
il
I
C'"~OF+Cr··OF
"" "
" "
..
....
"
..
>
~...
supply va/tags,
AMBIENT TEMPERATURE (TA )-25-C
;:
...
VI'.
~
C,"'OOF -
" " .....
~
C.-IOOpF
I
90
C,·30pF
..
45
itl
'\
/Ii..
•z
10
10
10
10
FREQUENCY (F1-Hz:
.
..l!ItI.
1
::!'
..
10
•
0
10 T
92CS- 21150
Fig. 5-Output va/tags v,. output current
Fig. 6-Open4oop frequency re$pOnse.
for CA1OBandCA1OBA.
16
> 12
I
~
....
...
\
+15V
\ SUPPLY VOLTAGE:yf.+ 15 v, Y-a-I!5V
10
\
\
\lc,.,I
vp _p
f,. 100Hz
OVWTOOSC.
OF
8~ ",".OOF
I
!:;
0
FOR TEST CIRCUIT
>
...
~
I
AMBIENT TEMPERATURE ~TA)- 215~1
4
\
\
10'
'\
""'-.
0
4
6 8 10 4
2
IOkil
SEE FIG.2
...
4
---
-15V
6 8 10 "
FREQUENCY (F)- Hz
92CS-24741
9ZCS-21151
Fig. 7-Large-signal frequency rB$ponse.
258
Fig. 8-Bum-ln lind operating life telt circuit.
File No. 832 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Linear Integrated Circuits
OOCIBLJD
Monolithic Silicon
Solid State
High-Reliability Slash (I) Series
CA1111 ...
Division
High-Reliability Voltage Comparators
For Applications In Aerospace, Military and Critical Industrial Equipment
I"S" SUffix)
S·LeadTO-5
with Dual-In-Line
Formed Leads
I"T" Suffixl
S·Load TO-5
"OIL-CAN"
H-17S7
H-1528
Features:
Applications:
-
-
Single· or dual·supplv operation
Power consumption - 135 mW at ±15 V
Strobe capability
Low input·offset current - 4 nA (typ.)
Differential input·voltage range - ±30 V
The RCA-CA 111 "Slash" (f) Series type is a high·reliability
linear·integrated·circuit voltage comparator intended for appli·
cations in aerospace, military, and industrial equipment. It is
electricallv and mechanicallv identical with the standard type
CA 111 described in Data Bulletin File No. 797 but is speciallv
processed and tested to meet the electrical, mechanical, and
environmental test methods and procedures established for
microelectronic devices in MI L-STD·883.
The packaged types can be supplied to six screening levelsI1N.llR.ll.12,/3, and l4-which correspond to MIL-STD·BS3
Classes A, B, and C. The chip version can be supplied to three
screening levels-/M,/N, and IR. These screening levels and
detailed information on test methods, procedures, and test
sequence are given in Reliability Report RIC·202A "High·
Reliabilitv CA3000 Slash (I) Series Tvpes Screened to MI L·
STD·883."
v'
Multivibrators
Positive and negative peak detectors
Crystal oscillators
Zero-crossing detectors
Solenoid, relav, and lamp drivers
The CA 111 Slash (I) Series types are supplied in 8·lead TO·5
stvle packages ("T" suffix), and in "DIL·CAN" packages,
S·lead TO·5 stvle packages with dual·in·line formed leads
("S" suffix). The CA 111 is also supplied in chip form ("H"
suffix).
MAXIMUM RATI NGS, Absolute-Maximum Values at TA=2!PC
OC SUPPL Y VOLTAGE IBetween V+ and V- terminal,l ....•.. 36 V
DCINPUTVOLTAGE* ............................... ±15V
DIFFERENTIAL INPUT VOLTAGE ..................... ± 30 V
OUTPUT TO NEGATIVE SUPPLY VOLTAGE IV 7 -4) ••.•••.. 50 V
GROUND TO NEGATIVE SUPPLY VOLTAGE IV 1-4) ........ 30 V
OUTPUT SHORT-CIRCUIT DURATION .................... 10'
OEVICE DISSIPATION:
Up ,oTA = 25°C ................................ 500mW
Above TA = 25°C .............. derate linearly at 6.67 mWf'C
6
INPUT OFFSET I
STROBE
.-
NOTE: PIN 4 IS CONNECTED TO CASE
92CS-24319
Functional Diagram
9-74
AMBIENT TEMPERATURE RANGE:
Operating ............................... -55 to +l25 oC
S,orage ................................. -65 to +1500C
LEAD TEMPERATURE IDURING SOLDERING):
At distance 1/16 ± 1/32 in. 11.59 ± 0.79 mml
from case for 10 seconds max. . ..... _ ....... _ ....... +265 oC
-This rating applies for ± 15 V supplies. The positive input-voltage
limit is 30 V above the negative supply. The negative input-voltage
limit is equal to the negative supply voltage or 30 V below the
positive supply. The negative input-voltage limit is equal to the
negative supply voltage or 30 V below the positive supply. whichever
is less.
259
CAn1 Slash (II Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 832
ELECTRICAL CHARACTERISTICS For Design Guidance Only
CHARACTERISTIC
Input Offset Voltage"
SYMBOL
VIO
Saturation Voltage
Input Voltage Range
VIPP
TEST CONDITIONS
SUPPLY VOLTAGE (V±) = 15 V
AMBIENT TEMPERATURE (TAl = 250 C
Unless Otherwise Specified
TYPICAL
VALUES
UNITS
mV
RS';;5 kn
0.7
VI = -5 mV,lO = 50 mA
0.75
V
TA = -55 to +1250 C
±14
V
nA
Input Offset·Current"
110
4
Input Bias Current"
60
nA
Positive Supply Current
liB
1+
5.1
rnA
Negative Supply Current
1-
4.1
mA
Output Leakage Current
VI;;> 5 mV, Vo = 35 V
Strobe On Current
Voltage Gain
A
nA
3
mA
200
VlmV
200
ns
MAXIMUM
LIMITS
UNITS
100 mV I nput Step with
5 mV Overdrive Voltage
Response Time
0.2
Final Electrical Tests and Group A Sampling Inspection
TEST CONDITIONS
CHARACTERISTIC
Input Offset Voltage"
SYMBOL
VIO
Saturation Voltage
SUPPLY VOLTAGE (V±) = 15 V
Unless Otherwise Specified
-55 +25 +125
RS';;5kn
4
3
4
VI = -5 mV, 10 = 50 mA
-
1.5
-
V+;;>.4.5 V, V =O,VI';;-6mV,
ISINK';;SmA
0.4
0.4
0.4
10
20
Input Offset Current"
110
20
Input Bias Current"
150 100 150
Positive Supply Current
liB
1+
Negative Supply Current
1-
Output Leakage Current
VI;;>5mV,VO=35V .
500
mV
V
nA
nA
-
mA
5
-
rnA
10
500
nA
6
* The input offset characteristics given are the values required to drive the output to within 1 V of either supply with a 1-mA load. These
characteristics define an error band which takes into account the worsH:ase effects of voltage gain and input impedance. The input
off~
set voltage, input offset current, and input bias current specifications apply for any supply voltage from a 5 V single supply up to a ±15 V
dual supply.
260
File No. 832 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA111 Slash (I) Series
Table III. Pre Burn-in Electrical and Post Burn-in Electrical Tests, and Delta Limits* For All Types
ELECTRICAL CHARACTERISTICS AT TA = 250 C, V+ = +15 V, V- = -15 V
CHARACTERISTIC
SYMBOL
Input Offset Voltage
VIO
Input Offset Current
110
Input Bias Current
II
TEST CONDITIONS
LIMITS
MAX. MAX.t.
MIN.
RS';;;5kn
UNITS
-
3
±1
mV
-
10
±2
nA
100
±10
nA
* Levels 11 and 12 require pre burn~in electrical and post burn-in electrical tests. and delta limits.
Level 13 requires pre burn-in electrical test only. The burn-in and operating life test circuit is shown in Fig. 9.
Table IV. Group C Electrical Characteristics Sampling Tests
TA=+250 C, V±=15V
CHARACTERISTIC
SPECIAL
TEST CONDITIONS
SYMBOL
Input Offset Voltage
VIO
I nput Offset Current
110
Input Bias Current
II
E
~
H
0 ••
,.
I
12.
3
mV
14
nA
110
nA
175 ::~i~TV6E::GE:t:tUI~~5(~AI.25.C
0.7
150
UNITS
MAX.
-
RS';;;S kn
AMBIENT TEMPERATURE (TA)-2S-C
"'
LIMITS
MIN.
O.5~
150
125
I-
z
::1
a'"
I-
=>
100
POWER DISSIPATION (Po)
z
0.40
100
~
75
0.3
g:
75
'"
50
0
'"
~
0
50
~
••
0.2 ~
SHORT-CIRCUIT CURRENT
~
lIse)
10
0.1
25
0
o
-15
15
-10
-5
0
5
10
9ZCS-24385
Fig. I-Output limiting characteristics.
15
DIFFERENTIAL INPUT VOLTAGE (VIO)-V
OUTPUT VOLTAGE 1Vo)-V
92CS-24389
Fig. 2-lnpur characteristics.
261
CA111 Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 832
INPUT
OFFSETI
STROBE
INPUT
OFFSET
v'
B
NOTE: ALL RESISTANCES ARE IN OHMS
Fig. 3-Schematic diagram for CA 11,.
SUPPLY YOLTAGE(V t )-15V
TERMINALS 5. 6. AND 8 SHORTED
SUPPLY VOLTAGE (y:i: • I!5V
'
TERMINALS 5, 6. AND 8 SHORTED
.
..
:!
I
i
!::!
~II:
...
il
30
a!::!
H
...
92CM-24380
400
300
S
...
.."
200
~
100
0
-75
NORMAL
o
-50
-25
0
25
50
75
100
125
92CS-24381
Fig. 4-lnput bis, current VB. ambient tlNTlperBture.
262
~
~
_
0
~
50
75
~
~
AMBIENT TEMPERATURE CTA)--C
AMBIENT TEMPERATURE (TAJ _·C
92CS-Z4388
Fig. 5-lnput offset current VJ. ambient temperature.
File No. 832 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA111 Slash (II Series
AMBIENT TEMPERATURE {TA)-2S-C
SUPPLY VOLTAGE (V+)-30V
60
>
I
50
~
...
~
NORMAL OUTPUT
LOAD RESISTANCE (RL).' kQ
V7_4- 50V
40
EMITTER -FOLLOWER
OUTPUT
0
30 RL-SOO Q
>
I-
~
I-
20
"
0
10
o
-I
-0.5
0
0.5
DIFFERENTIAL INPUT VOLTAGE (VIo)-mV
OUTPUT CURRENT (IO'-mA
92C5-24391
92C5-24392
Fig. 7-0utput $aNTation voltage vs. output current.
Fig. 6- Transfer function.
100. AMBIENT TEMPERATURE ITA) -2S·C
6 V'XO.YIO+RS1:rO
>
E
I
~...
2
V
10
::!:i ••
0
>
...
V
1/
+15V
/
,...u...
...~
•
IOVp-p,lkHz
~!\C(lt.\.. Vi-'
2
I-
~
0
k":
•
OV
~ .........
I
In nr
uu u
••
~ •
2
0.1
10k
.
6 8 100 ..
2
4
-usv
6 8 1M
92C5-24897
INPUT RESISTANCE (RI)- Q
92C5-24395
Fig. 8-0ffset er,or.
Fig. 9-Burn-ln and operating life test circuit.
263
- - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 829
OOCI8LJD
Linear Integrat~d Circuits
Monolithic Silicon
High-Reliability Slash (I) Series
CA723T/ ...
Solid State
Division
High-Reliability
Voltage Regulators
For Regulated,Output Voltages Adjustable from 2 V to 37 V
at Currents up to 150 mA Without External Pass Transistors
I n Aerospace, Military, and Critical I ndustrial Equipment
Features:
lG-L..dT()'5
"r'Suffix
H-1384
•
•
•
•
•
•
•
Up to 150 mA output current
Positive and negative voltage regulation
Regulation in excess of 10 A with suitable pass transistors
Input and output short·circuit protection
Load and line regulation: 0.03%
Direct replacement for 723 industry types
Adjustable output voltage: 2 to 37 V
The RCA·CA723 Slash (I) Series types are high·reliability
silicon monolithic integrated circuits designed for service as
voltage regulators at output voltages ranging from 2 to 37
volts at currents up to 150 milliamperes. These devices are
intended for applications in aerospace. military. and
industrial equipment. They are electrically and mechanically
identical with the standard type CA723 described in Data
Bulletin File No. 7BB but are specially processed and tested
to meet the electrical. mechanical and environmental test
methods and procedures established for microelectronic
devices in MI L-STD-BB3.
Each type includes a temperature-compensated reference
The CA723 is supplied in the 1()'Lead TO-5 style ceramic
package IT suffix). and is a direct replacement for industry
type 723 in packages with similar terminal arrangements. It is
also available in chip form IH suffix).
Applications
•
"
•
•
•
Series and shunt voltage regulator
Floating regulator
Switch ing voltage regulator
High-current voltage regulator
Temperature controller
amplifier, an error amplifier, a power series pass transistor,
and a current-limiting circuit. They also provide·
independently accessible inputs for adjustable current
limiting and remote shutdown and. in addition. feature low
standby current drain. low temperature drift. and high ripple
rejection.
The CA723 may be used with positive and negative power
supplies in a wide variety of series, shunt, switching. and
floating regulator applications. They can provide regulation
at load currents greater than 150 milliamperes and in excess
of 10 amperes with the use of suitable n·p-n or p-n-p external
pass transisto ....
The packaged type can be supplied to six screening levels /1 N. /1 R. /1. /2. /3. and /4 - which correspond to
MI L-STD-BB3 Classes A. B. and C. The chip version caOl be
supplied to three screening levels -/M./N./R.
These screening levels and detailed information on test
methods. procedures and test sequence are given in
Reliability Report RIC-202A "High-Reliability CA30aa Slash
III Series Types Screened to MIL-STD-BB3".
264
v-
CURRENT
SENSE
CURRENT
LIMITER
92CS-24742
Fig. 1-Functional diagram of the CA723.
9-74
File No. 829 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA723 Slash
MAXIMUM RATINGS, Absolute Maximum Values
DC SUPPLY VOLTAGE
(Bet\M!en V+ and V- Terminals) . . . . . . . . . • . . . 40
PULSE VOLTAGE FOR 50-ms PULSE WIDTH
(Between V+ and V- Terminals) . . . . . . . . . . . . . 50
DIF FERENTIAL INPUT·OUTPUT VOLTAGE
40
DIFFERENTIAL INPUT VOLTAGE:
Between Inverting and Non-Inverting Inputs
Between Non-Inverting Input and V- . . . . . . . . . .
Series
DEVICE DISSIPATION:
Up to TA :::::125°C
CA 723T . . . . . • • • . . • . . • . • • • . • • • •• 800
mW
V
V
Above T A • 25°C
CA723T . . . . . . . • . . . • . . . Derate linearly 6.3 mWfC
V
AMBI ENT TEMPERATURE RANGE:
is
V
8
V
CURRENT FROM VOLTAGE REFERENCE
TERMINAL (VREF) • . • . . • • • . • . . . • . • • • . 15
II)
mA
Operating ........ . . . . . . . . . . . . . . ..
Storage
.......................
-55 to +125°C
-65 to +150oC
LEAD TEMPERATURE (During Soldering):
At adistancol116" ±1/32" (1.59 ±o.79 mm)
from case for 10 seconds max. . . . . . . . . . . . +265
°c
92CS-24157
Fig. 2- Terminal arrangement of the CA723T
in the T0-5 style package.
Vc
+------o~~~~~~~i;ON
l-___-oC~~~~NT
' -_ _ _--(::>~~~~~NT
NON-INVERTING
INPUT
V-
INVERTING
INPUT
9ii!CM-24143
Fig. 3-Equivalent schematic diagram of thfl CA723.
265
CA723 Slash (/) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-..,._ _ _ _ _ _ _ File No. 829
ELECTRICAL CHARACTERISTICS For Design Guidance Only
CHARACTERISTIC
Quiescent Regulator
Current
Reference Voltage
SYMBOL
IQ
fiNO
Ripple Rejection
Equivalent Noise
Output Voltage
ILiM
VNOISE
CA723
Typ.
2.3
VI=12to40V
VI.-12to15V
Line Regulation
Short·Circuit Limiting
Current
IL = O. VI = 30 V
VREF
Load Regulation
Output· Voltage Tem·
perature Coefficient
TEST CONDITIONS (See Note)
TA - 25°C, VI =v+= Vc= 12V, V- = 0,
Vo =5V,IL = 1 rnA,CI = 100pF,
ZDIVIDER ';;10 kn (into error
amplifier as shown in Fig. 14) un·
less otherwise indicated
UNITS
mA
7.15
V
0.02
0.01
%VO
IL= 1 to50mA
0.03
%VO
TA = -55 to +125°C
0.002
%/"C
f = 50 Hz to 10 kHz
f- 50 Hz to 10 kHz, CREF - 51lF
74
86
dB
RSCp= Ion VO=O
65
mA
BW - 100 to 10 kHz CRI'I' - 0
BW = 100 to 10 kHz, CREF = 51lF
20
2.5
IlV RMS
;:. Note: Une and load regulation specifications are given for condition of a constant chip temperature for high dissipation
conditions. temperature drifts must be separately taken into account.
Table I. Pre Burn-In Electrical Post Burn-In Electrical Tesls, end Delta LimilsELECTRICAL CHARACTERISTICS, at TA = 25"C
CHARACTERISTICS
Reference
Voltage
Quiescent
Regulator Current
•
266
SYMBOL
VREF
10
LIMITS
TEST CONDITIONS
IL=O
VI=30V
UNITS
MIN.
MAX.
MAX.I!.
6.95
7.35
±0.05
V
-
3.5
±0.5
mA
Levels /1 and 12 require pre burn-in electrical and post burn-in electrical tests, and delta limits
Level 3 requires pre burn-in test only. The bum-in and operating life testeireuit is shown in Fig. 13
File No. 829 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA723 Slash (I) Series
Table II. Final Electrical Tests and Group A Sampling Inspection
CHARACTERISTIC
TEST CONDITIONS (See Note)
TA=25°C.VI=V+=Vc=12V.V =0.
VO=5V.IL =1mA.CI=100pF.
LIMITS
SYMBOL ZDIVIDER<10k!1 (into error
UNITS
MINIMUM
MAXIMUM
amplifier as shown in Fig. 14) unless otherwise indicated
-55 +25 +125
-55 +25 +125
Quiescent Regulator
Current
IQ
-
-
I nput Voltage Range
VI
-
9.5
IL=O.VI=30V
Vo
-
2.0
Differential InputOutput Voltage
VI-VO
-
3.0
Reference Voltage
VREF
-
6.95
Output Voltage Range
_. -
-
-
-
-
37
-
-
38
-
7.35
Line Regulation
VI=12to40V
VI-12to15V
-
-
IL= 1 to 50 rnA
-
-
Load Regulation
-
-
-
3.5
40
-
rnA
V
V
V
V
-
0.3
0.2
0.1
0.3 %VO
0.6
0.15
0.6 %VO
Note: U!"o and load regulation specific:ations are given for condition of a constant chip temperature: for high dissipation conditions, temperature
drifts must be separatelv taken mto account.
Table III. Group C Electrical Characteristics Sampling Tests
(TA =25"C VCC=+6 V. VEE =-6 VJ
LIMITS
CHARACTERISTIC
Reference
Voltage
SYMBOL TEST CONDITIONS
VREF
UNITS
MIN.
MAX.
6.95
7.35
V
Line
Regulation
VI=12to15V
-
0.15
%VO
Load
Reglliation
IL=lto50rnA
-
0.2
%VO
IL = 0 VI = 30 V
-
3.5
rnA
Quiescent
Regulator Current
IQ
267
CA723 Slash
II) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 829
TYPICAL CHARACTERISTICS CURVES FOR TYPE CA723
150
4'
E
MAX. JUNCTION TEMP. ITJ )~150·C
THERMAL RESISTANCE ~1!50·CIW
QUIESCENT DISSIPATION IPQ106OrnW
(NO HEAT SINK)
1
...
..J
o
o
10
20
30
40
DIFFERENTIAL INPUT-OUTPUT VOLTAGE IVl~VO I-V
OUTPUT CURRENT I IO )-mA
92CS-24161
92C5-24160
Fig. 4-Max. load current VI. differential input-output voltage.
Fig. 5-Load regulation without current limiting.
OUTPUT
OUTPUT CURRENT lI.o'-mA
CUR~ENT
IIOI-rnA
92C5-24163
92C5-24162
Fig. 6-Load regulation with current limiting.
Fig. 7-Load regulation with current limiting.
>
I
"
0.8
~
:l!
~
0.6
0
>
~
5
0
o.
OUTPUT C.U~.RENT lID l-mA
Fig. 8-Current limiting characteristics.
268
92C5-24164
TIME (f)-,.u
92C5-24174
Fig. 9-Line transient response.
File No. 829 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ CA723 Slash (II Series
TYPICAL CHARACTERISTICS CURVES (Cant'd)
0.01
468
100
JUNCTION TEMPERATURE ITJ I_oc
Ik
2468
r
k
2
4682468
I Ok
1M
FREQUENCY (1)- Hz
92CS-24111
92CS-24175
Fig. , I-Output impedance vs. frequency.
Fig. to-Current limiting characteristics vs. junction temperature.
TIME (U-p.s
!J2CS-24176
Fig. 12-Load transient response.
+3QV
CA723
CA723C
NON
INV·
INPUT
R3
R2
REFI =
C
RSC.20n,1/4 WATT
R2 '" 2kn t5 %,112 WATT
CIRCUIT PERfORMANCE DATA:
RI- BOOn ±S%,1I2 WATT
R3.580n 15"1.,1/2 WATT
REGULATEDOUTPUrVOLTAGE • . •
5
V
LINE REGULATION {toV..' 3 VI • • • • 0.5 mV
LOAD REGULATION (AIL. 50 mAIo • • 1.5 mV
CA723T AT OPERATING
TEMPERATURE OF 125·C
Noto: R3"
92CS-24744
Fig. 13-Burn-in and operating life test circuit.
=!+=~ for minimum temper.tuft drift
92C5-24178
Fig. 14-Low-voltage regulator circuit (Va
=2 to 7 volts).
269
- - - - - - - - - - - - - - - - - - - - , -_ _ _ _ _ _ _ _ _ _ _ _ File No. 718
Linear Integrated Circuits
Monolithic Silicon
High-Reliability Slash(/) Series
CA741/ •••, CA747/•••,
CA74~/..•, CA1558/ ..•
OOCI8LlD
Solid State
Division
High-Reliability
Operational Amplifiers
c~
~."'.,
iii
I
:'/1.
f/j!!
J I
8·Lead TO:S Style
Package with
S:Le8d TO:S Style
Package
Dual·in--Line
Formed Leads
High-Gain Single and Dual Operational Amplifiers
For Applications in Aerospace, Military, and Critical Industrial Equipment
Features:
~.!3B4
10-Lead TO:S
Style PackB!le
• Input bias current lall types): 500 nA max.
• Input offset current lall types): 200 nA max.
RCA·CA741, CA747, CA74B, and CA155B "Slash"") Series
types are high·reliability linear integrated circuit High·Gain
Single and Dual Operational Amplifiers intended for
applications in aerospace, military, and industrial equipment.
They are electrically and mechanically identical with the
standard types described in Data Bulletin File No. 531 but
are specially processed and tested to meet the eleelrical,
mechanical and environmental test methods and procedures
established for microelectronic devices in MIL·STD·BB3.
The packaged types can be supplied to six screening levels11N,/1R.ll.12,/3, and 14-which correspond to MIL-STD-BB3
Classes A, B, and C. The chip version can be supplied to three
screening levels-1M, IN, and IR. These screening levels and
detailed information on test methods, procedures, and test
sequence are given in Reliability Report RIC·202A "High·
Reliability CA3000 Slash III Series Types Screened to MIL·
STD-BB3."
RCA
·TYPE NO.
NO.OF
AMPLI.
CA1558T
dual
CA741
single
CA747
dual
CA748
single
270
PHASE
COMPo
PACKAGE
TYPE
internal 8·leadTO:S
internal 8,leadTO·S
Internal 10-1aedTO:S
external 8·leadTO:S
Applications:
•
•
•
•
•
•
Comparator
DCamplifier
Integrator or differentiator
Multivibrator
Narrow-band or band'pass filter
Summing amplifier
The CA741, CA74B, and CAI55B Slash '" Series types are
supplied in the B·lead TO·5 style package '''T'' suffix) and in
the B·lead TO·5 style package with dual·in·line formed leads,
DIL·CAN '''S'' suffix). The CA747 is supplied in the 10·lead
TO·5 style package '''T'' suffix). All the types are also
available in chip form '''H'' suffix).
OFFSET
VOLT. NULL
AOL
IMIN.)
Vlci
(MAX.)
TAOPERATING
RANGE
COMPATIBLE WITH
INDUSTRY TYPE(S)
no
yes
no
yes
SO,OOO
SmV
SmV
-55 to 125°C
-5S to 12SoC
MC1S58i 55S58
50,000
50,000
SmV
SO,OOO
5mV
-55 to 125°C
-55 to 12SoC
"A747
,.A748
"A741
9-74
File No. 718 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA741. CA747. CA748. CA1558 Slash II) Series
MAXIMUM RATINGS, Absolute-Maximum Values at TA"' 25"C
DC SUPPLY VOLTAGE (between V+ and V- terminals):
.44V
CA741T, CA747T, CA748T, CA155BT
±30V
Differential Input Voltage
±15V
DC Input Voltage'
Indefinite
Output Short-Circuit Duration
DEVICE DISSIPATION:
.500mW
BoomW
. 680mW
Up to 75'C (CA741T, CA748T)
Up to 30"C (CA747T)
Up to 3O'C (CA 155BT) . . . . _
. Derate linearly 11.67 mWl'C
Above Indicated Temperatures
Voltage between Offset Null and V-CA741T
. . . . . . . . . . . . ±0.5V
TEMPERATURE RANGE:
. -55 to +125'C
-65 to +150'C
Operating .............•.•.•......•...•••
Storage . . . . . . . . . . . . . . . . . . . . . . . .
LEAD TEMPE RA TU RE (During Soldering)
At distance 1/16±1/31 inch (1.59±0.79 mm) from case for 10 seconds max
.. . . . . . . . . . . . . . . . . . . . 3OO·C
ill If Supply voltage Is less than ± 15 volts, the Absolute Maximum Input Voltage Is equal to the Supply Voltage.
"Voltage values apply for each of the dual operational amplifiers.
ALL RESISTANCE VALUES ARE IN OHMS
92CM-19432
Fig. 1 - Schematic diagram of operational amplifier with extemal phase compen5ation for CA748T.
271
CA741, CA747, CA748, CA1558 Slash (I) series _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 718
ELECTRICAL CHARACTERISTICS at TA = 25"C
CHARACTERISTICS
TOP VIEW
UNITS
SYMBOLS suWLYVOLTI
V+·+15V
Y---1SY
TYP.
Input Offset Voltage
V,O
I nput Offset Current
RS
s: 10 kSl
1
mV
',0
20
nA
I nput Bias Current
liB
BO
nA
Input Resistance
R,
2
MSl
92C5-19430
la) -
FunctionaldlagramofCAI558Twith
internal phase compensation.
TOP VIEW
Open·Loop
Differential
Voltage Gain
AOL
Common·Mode Input
Voltage Range
V,CR
RL ~2 kSl
VO= ±10V
200,000
±13
V
vNOTE: PIN 4 IS CONNECTED TO CASE
Common·Mode
Rejection Ratio
CMRR
Supply Voltage
Rejection Ratio
VRR
RS
s: 1() kSl
90
dB
92CS-19426
Ib) -
RS
s: 10 kSl
30
Functionsldiagram of CA741T with
Internal phase compenlBrlon.
"VN
TOP VIEVtr
RL ~ 10 kSl
Output Voltage
Swing
±14
V
VO(P·PI
RL
~2
kSl
Supply Current
±13
1.7
rnA
Po
50
mW
CI
1.4
pF
±15
mV
75
Sl
25
rnA
Unity Gain
V, =20mV
0.3
"s
RL =2kSl
CL 100 pF
5.0
%
92(S-19427
Device Dissipation
Input Capacitance
Offset Voltage Adjust·
ment Range
Output Resistance
Ro
Output Short-Circu it
Current
Transient Response
Risetime
tr
s:
Overshoot
Slew Rate:
Closed Loop
vNOTE: PIN 4 IS CONNECTED TO CASE
92CS-19428
SR
0.5
RL~2
V/p.s
kSl
Open Loop"
• Values apply for each of the dual operational amplifiers.
272
Ie) - . Functional diagram of CA747T with
Internal phase cotnpenllItion.
40
Id) -
Functional diagram of CA748Twlth
external ph8IfJ compensation
Fig. 2-Functional diagrams of
operational amplifiers.
File No. 718 _ _ _ _ _ _ _ _ _ _ _ _ __
CA741, CA747, CA748, CA1558 Slash (/I Series
r-~--------~~---1----------------_.--------------_.----_<.~v+
INVERTING
INPUT
NON-INVERTING
INPUT
Rg
25
OUTPUT
"5
,gK
R,O
50
R.
ALL RESISTANCE VALUES ARE IN OHMS
R"
R'2
50K
'K
BO
* SEE FUNCTIONAL DIAGRAM FOR TERMINAL
92CM-19433
NUMBERS OF RESPECTIVE TYPE NUMBERS
Fig. 3 - Schematic diagram of operational amplifiers with internal phase compensation for CA741 T and for each
amplifier of the CA748T and CA 1558T.
TBbI8/- Pre Burn·ln Electrical and Post Bum.fn ElflCtrical Tests. and Delta Limits- For All Types
ELECTRICAL CHARACTERISTICS, at TA = 25"C, vr=+15V, \I" =·15 V
CHARACTERISTIC
SYMBOL
TEST CONDITIONS
LIMITS
MIN.
MAX.
MAX.tJ.
UNITS
Input Offset Voltage
VIO
.1
mV
110
-
5
Input Offset Current
200
.24
nA
Input Bias Current
II
-
SOO
.60
nA
Device Dissipation
PD
85
.18
mW
• Lovels/1 and 12 require pre burn-In electrical and post burn-In electrical tests, and delta limits.
Level /3 requires pre burn-In electrical test only. The burn-In and operating life test circuit Is shown In Fig. 5.
273
CA741. CA747. CA748. CA 1558 Slash (/I Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 718
Table
11- Final Elsctricalllnd Group A.
CHARACTERISTIC
Electrical Sampling Inspection for All Types
TEST CONDITIONS
SYMBOL
v+ -+15 V. V-. -15 V
LIMITS FOR INDICATED TEMPERATURES lOCI
MAXIMUM
MINIMUM
+125
+25
+126
+26
55
-55
UNITS
STATIC
Input Offset Voltage
VIO
Input Offset Current
110
Input Bias Current
-
-
II
Po
-
-
Supply Current
Device DIssipation
-
-
-
-
-
-
-
6
5
6
mV
500
200
200
nA
-
1500
500
500
nA
3.8
3.3
2.8
mA
-
100
85
75
mW
DYNAMIC
Open· Loop Differsn-
tiel Voltage Gain
RL =2k, VO =±10V
AOL
Common-Mode
Rejection Ratio
CMRR
Maximum OutputVoltage Swing
VOIP-PI
Input Resistance
RI
25000
50000
25000
-
-
-
70
70
70
-
-
-
-
-
RL~
RL~
.12
.,0
lOkI)
2kl)
-
Common-Mode InputVoltage Rango
VieR
RS .;;10kl)
Supply Voltage
V RR
RS .;;10kl)
.12
.10
-
.12
.10
-
0.3
.12
.12
.12
Table III - Group C. Electrical Characteristics Sampling Tests
V+=+15V, V-=-15V
CHARACTERISTIC
SYMBOL
SPECIAL
TEST CONDITIONS
LIMITS
MIN.
Input Offset Voltage
VIO
-
Input Offset Current
110
Input Bias Current
II
-
Open-Loop Differential
Voltage Gain
SupplV Current
274
AOL
150
Rejection Ratio
TA = +2SoC
-
-
RL = 2 k, Vo = ±ID V ~OOO
-
UNITS
MAX.
8
240
800
mV
p.A
p.A
3
rnA
-
150
dB
-
V
-
Mn
-
V
150
,"V/v
File No. 718 _ _ _ _ _ _ _ _ _ _ _ _ _ __
CA741 , CA747, CA748, CA 1558 Slash (I) Series
DC SUPPLY VOLTS (V+aI5, Y-a-151
AMBIENT TEMPERATURE ITA)-25-C
10-'
03
rt"
OS
FREQUENCY (t)-Hz
·~6
92CS-17620
Fig.4 - Open4oop voltage gain vs. frequency for all types.
68ktl
.----.--.._JVvv---O Y+.+JSV
+S.rLrL
1kHz
±2%
-S
TO DEVICES
UNDER TEST
~~I
I
Y-a-15V
u,o,'&
_
1kHz
-
tlO%
DRIVER CIRCUIT
1.3lr.n
1.3kA
.& THESE RESISTORS MAY BE ADJUSTED TO GIVE REQUIRED
DRIVE UNDER DIFFERENT LOAD CONDITIONS
92CM-22B37
TERMINAL No'S IN CIRCLES ARE FOR UNIT No.1
TERMINAL No'S IN SQUARES ARE FOR UNIT No.
2.
Fig.5 - Burn-in and operating life test circuit for CA741, CA747, CA748, CA 1558.
275
File No. 705
[R1(]5LJD
Linear Integrated Circuits
Monolithic Silicon
Solid State
High-Reliability Slash(/) Series
Division
CA3000/ ...
High-Reliability
DC Amplifier
For Applications in Aerospace"Military and Critical Industrial Equipment
Features:
• Input Impedance . . . . . . . . . . .' ....•...
• Voltage Gain .....•...... - .... _ . _ . _
• Common-Mode Rejection Ratio . . . . . . . . . .
• Input Offset Voltage . _ . . . . . . . . . . . . . . .
195 Kf!
37 dB
98dS
1.4 mV
typ_
typo
typo
typ_
• Push-Pull Input and Output
H-1528
10-Le.d TO-S SMe Package
• Frequency Capability
DC to 30 MHz (with extemal C and R)
• Wide AGC Range .... __ ..... __ ..... .
90 dB typ-
Applications
RCA-CA3000 "Slash" (I) Series type is a high-reliability
linear integrated circuit DC Amplifier intended for applications in aerospace, military, and industrial equipment. It is
electrically and mechanically identical with the standard type
CA3000 described in Data Bulletin File No, 121 but is
specially processed and tested to meet the electrical,
mechanical and environmental test methods and procedures
established for microelectronic devices in MI L-STD-883,
• Schmitt Trigger
• RC-Coupled Feedback Amplifier
•
•
•
•
•
•
Mixer
Comparator
Modulator
Crystal Oscillator
Sense Amplifier
See Companion Application Note ICAN-5030
"Applications of RCA-CA3000 IC DC Amplifier_"
The packaged types can be supplied to six screening levels11N,/1R.ll.12,/3, and 14-which correspond to MIL-STD-883
Classes A. B, and C, The chip version can be supplied to three
screening levels-1M, IN, and IR_ These screening levels and
detailed information on test methods, procedures, and test
sequence are given in Reliability Report RIC-202A "HighReliability CA3000 Slash (I) Series Types Screened to MILSTD-883,"
The CA3000 Slash (I) Series type is supplied in the 10-lead
TO-5 style package ("T" suffix) or in chip form ("H" suffix).
92CS-12979
Fig. 1 - Schematic diagram
276
9-74
File No.. 70S"-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA3000 Slash (II Series Type
Maximum Ratings, Absolute-Maximum Values
·55°C to +125°C
·65°C to +150°C
OPERATING TEMPERATURE RANGE
STORAGE-TEMPERATURE RANGE ..
LEAD TEMPERATURE (During Soldering):
At distance 1/16" ± 1/32"
(1.59 mm ±0.79 mm)
from case for lOs max. . . . . . . . . . . . . . . . . . .
MAXIMUM SINGLE-ENDED INPUT·SIGNAL VOLTAGE
MAXIMUM COMMON-MODE INPUT-SIGNAL VOLTAGE
26~C
±2 V
. ±2 V
MAXIMUM DEVICE DISSIPATION. . . . . . . . . . . . .. 300 mW
Absolute Maximum Voltage and Current Limits at TA = 25° C
The following chart gives the range of voltages which can be applied to the terminals listed
vertically with respect to the terminals listed horizontally. For example, the voltage range of
the vertical terminal 1 with respect to terminal 9 is 0 to -12 volts.
Terminal
No.
1
2
3
4
5
1
2
.
4
3
+16&
0
+16
·5
5
6
. .
. . ·
. ·
·
+5
·5
+5
·10
0
·16
6
7
7
8
+4
·4
co ~
~~
c ~
m
(')
~
gO
+1
·12
10
+1
0
·16
0
·16
0
·16
0
·16
0
-12
Internal Connection
00 not use
0
·16
8
Rotings
0.1
·12
·
·
·
·
·
0.1
·
+16
0
9
10
10
Case
·
·
·
·
·
9
0
·12
Maximum Current
Connected to Terminal #3 - Do Not Ground
.Voltages are not normally applied between these terminals. Voltages appearing between these tllrminals will be safe If the specified limits
between all other terminals are not exceeded•
... This rating applies to the more positive of Terminals #1 or #6.
277
CA3000 Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No.,
ELECTRICAL CHARACTERISTICS, at TA
705
=2fiOC, v+ = +6 V, V- =-6V, unless otherwise specified
LIMITS
CHARACTERISTICS
STATIC CHARACTERISTICS
Input Offset Voltage
Input Offset Current
Input Bias Current
SYMBOLS
SPECIAL TEST CONDITIONS
Terminals No.~ & No.5 Not
Connected Unless Specified
VIO
110
II
TYPE
CA3000
Typ.
Units
I.~
mV
J1.A
1.2
23
JJ.A
TERMINALS
Quiescent. Operating
Voltage
Va
or
VIO
~
NC
NC
V·
V·
5
NC
2.6
V·
~.2
NC
-1.5
0.6
V
V
V
V
30
mW
32
37
650
dB
dB
,kHz
6.~
V(P-P)
V·
Device Dissipation
NC
NC
PI
DYNAMIC CHARACTERISTICS
Differential Voltage Gain
Single-Ended Output f = I kHz
ADIFF
Single-Ended Input
Double-Ended Output f = I kHz
Bandwidth at -3 dB Point
BW
Maximum Output Voltage
f = I kHz
VOUT(P-P)
Swing
Common-Mode Rejection
Ratio
Single~Ended Input
Impedance
Single-Ended Output
Impedance
.CMRR
f
=I
kHz
98
dB
liN
f
=I
kHz
195K
f1
lOUT
f
=I
kHz
8K
f1
Total Harmonic Distortion
THD
f
=I
kHz
0.2
%
AGe Range (Max imum Vo Itage
Gain to Complete Cutoff)
AGC
f
=I
kHz
90
dB
278
File NO.,70S
CA3000 Slash
(II
Series
Table I - Group A Electrical Sampling Inspection
Limits for Indicated Temp. (0 C)
Characteristics
Sym·
bol
Test Conditions
V+ = +6 V,
V· =·6 V
Minimum
·55
+25
Maximum
Units
+125
-55
+25
+125
STATIC
Input Offset
Voltage
VIO
-
-
-
-
6.5
5
6.5
mV
/Input Offset
Current
110
-
-
-
-
20
10
20
IJA
Input Bias Current
II
-
-
-
-
70
36
25
IJA
3.2
V
Quiescent
Operating
Va
or
Voltage
VlO
Terminal
4
Terminal
5
NC
NC
Terminal
Terminal
5
4
NC
Oevice
PT
NC
1.5-
1.5
3.2
3.2.
30
25
20
60
60
50
mW
mW
25
20
15
55
55
50
55
50
45
105
105
90
mW
35
35
25
70
70
65
mW
-
28
-
-
-
-
dB
-
5
-
-
-
-
Vp_p
vI = 10mV, RS= 1 kG
-
600
-
-
-
f= 1 kHz
-
70
-
-
-
-
-
70k
-
-
-
-
Q
Si ngle- Ended
Output Impedance ZoUT
-
5.5k
-
10.5 k
-
Q
Total Harmonic
Distortion
THO
-
-
-
-
5
-
%
AGC Range
(Maximum Voltage Gain to
Complete Cut-
AGC
-
80
-
-
-
-
dB
Dissipation
NC
-V
-V
DYNAMIC
-V
1.5
NC
-V
All tests at 1 kHz, except BW
Differential
Voltage Gain
Maximum Output
Voltage
SingleEnded
Oqtput
AOiff
VOUT
f= 1 kHz
(p-p)
Bandwidth at -3
dB Point
BW
Common-Mode
Rejection Ratio
CMR
Single-Ended
Input Impedance
ZIN
f= 1 kHz
kHz
dB
off)
279
CA3000 Slash III Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 705
Table II - Pre Burn·ln Electrical and Post Burn·ln Electrical Tests, and Delta Limits'
Electrical CharllCteriltles, at TA - 25' C, V+ ~ -16 V, V- =-6 V
CHARACTERISTIC
TEST CONDITIONS
SYMBOL
-
Input Offset Current
II
Quiescent
Operstlng Voltage
Vsor
Terminal 4: NC
Vl0
TerminalS: NC
Device Dissipation
IT
Terminal 4: NC
Terminal 5: NC
LIMITS
MAX.
MIN.
UNITS
MAX. A
-
35
'4
p.A
1.5
3.2
'0.3
V
25
60
.6
mW
·.'Levels 1 and 2 'require pre burn-in electrical and post burn-in electrical tests, and delta limits.
Level 3 requires pre burn-in electrical test only_ The burn-in and operating life test circuit is shown in Fig. 7.
Table JII - Final Electrical Tests
CHARACTERISTIC
Input Offset
Voltage
Input Offset
I
Current
Input Bias
~
TEST CONDITIONS
V+=+6 V.
V' =-6V
LIMITS FOR INDICATED TEMPERATURES ('CI
MAXIMUM
MINIMUM
-55
+125
+125
+26
+25
VIO
-
-
-
-
6.5
5
6.5
mV
110
-
-
-
-
20
10
20
I'A
-
II
-
-
-
70
36
25
I'A
Quiescent Operating Voltage
Vsor
V'O
Terminals 4 and 5
No connection
1.5
1.5
1.5
3.2
3.2
3.2
V
Device Dissipation
IT
Terminals 4 and 5
No Connection
30
25
20
60
60
50
mW
AOlff
f= 1 kHz
-
2S
-
-
-
-
dB
Ended Output
I
Table IV - Group C Electrical Characteristics Sampling Tests. (TA = 2fjOC)
Characteristic
Llml,s
TEST CONnlTlciNS
v+ = +6 V, V'= -6 V
Min.
-
Max.
Units
5
mV
10
IlA
IlA
Input Offset Voltage
VIO
110
Input Bias Current
II
-
36
Va or V 10
1.5
3.2
V
PT
25
60
mW
28
-
dB
Device Dissipation
Differential Voltage Gain
,
Symbol
. Input Offset Curr;nt
Quiescent Operating Voltage
280
UNITS
-55
Current
.2 Differential Voltage Gain Single
!
SYMBOL
.Slngl.. Ended Input
AOIFF
Single Ended
Output f 1 kHz
=
File
No. 705 ·_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA3000 Slash (I) Series
STATIC CHARACTERISTICS
I IV DC UP LV VOLTS Vee • +6
NEGATI~E DC SUPPLY VOLTS (YEE).
6
FREQUENCY ( f) • I kc/s
rl
POSITIVE DC SUPPLY VOLTS (Ved- +6
NEGATIVE DC SUPPLY VOLTS (YEE). -6
.
10
~
0
T
III
III
II
FREE-AIR TEMPERATURE (TFA)--55"C
-!-or!.
z
DOUBLE-
125
;;i
ED OUTPU,;
[lj
-10
1'-25
~
~
SING~E-ENDED 0 T~Ut
-20
::l
:ii~
fil
2
-15
-00
-25
0
25
50
100
15
125
-30
-.
2
0.001
4
6.
0.01
FREE-AIR TEMPERATURE (TFA)--C
2
4
6.
0.1
2
•
6.
2
Mels
Fig.3- Bandwidth at·3 dB point V$ temperature
Fig.2- Differential voltage gain vs temperature
POSITIVE DC SUPPLY VOLTS (Vee)
~
6.
92CS-13294
92C:S~1359"
.
+6
~~GA~~vNEC.;>c,ls~~~;J. VOLTS (VEE)- -6
9.
•
10
FREQUENCY (1) -
POSITIVE DC SUPPLY VOLTS
(Vee.
+6
NEGATIVE DC SUPPLY VOLTS tyEE). -6
fREQUENCY (f) ~ Ikc/s
150
100
9'
.0
-00
-25
0
25
50
75
100
125
FREE-AIR TEMPERATURE (TFA)-~
92CS-13297
o
-10
-'0
-25
25
50
75
100
125
FREE-AIR TEMPERATURE (TFA)-'"C
92CS-13298
Fig.5-SingltHnded Input impedance vs temperature
Fig.4- Common·mode rejection ratio vs temperature
"i
1
POSITIVE DC SUPPLY VOLTS (Vee)· +6
NEGATIVE DC SUPPLY VOLTS (VEE'.
6
fREQUENCY (11 ,. I ke/l
+6V
m
!
B
0-
~
5o
.,
-15
~~.• +U
-50
-25
0
25
15
125
100
FREE-AIR TEMPERATURE (TfA)--C
-6V
92LS·2839
92CS-13301
Fig.6- SingllHlnded outPut Impedance VI temperature
F ;9.7- Burn-in snd operating
life test c/~uit
281
File No. 714
Linear Integrate~ Circuits
OOcn3LJD
Monolithic Silicon
Solid State
Division
High-Reliability Slash(/) Series
CA3001/...
High - Reliability
Video Amplifier
For Applications In Aerospace, Military' and Critical Industrial Equipment
Features:
• Push-Pull Input & Output
• AGC Range ..•.•.•..•..•...•••.••• -
H-1463
12-Lead TO-5 Style Package
60 dB typo
• Bandwidth .. .. .. .. .. .. .. .. .. .. .. .. .
• Input Resistance . • . • • . . • . • • • • . . . . • . ..
• Output Resistance ... ; . . . . . . . . . . . . . . .
29 MHz
150 kO typo
450 typo
• Voltage Gain •.•••.....••.••..•••••.
19dB typo
1.5 mV typ>
•
Input Offset Voltage
RCA-CA3001 "Slash" (I) Series type is a high-reliability
linear integrated circuit Video Amplifier intended for
applications in aerospace, military. and industrial equipment.
It is electrically and mechanically identical with the standard
type CA3001 described in Data Bulletin File No. 122 but is
specially processed 'and tested to meet the electrical,
mechanical and environmental test methods and procedures
established for microelectronic devices in MIL·STD-883.
Applications
•
DC.IF.& Video Amplifier
• Schmitt Trigger
• Mixer
• Modulator
• See Companion Application Note ICAN-5038
"Applications of the RCA-CA3001 IC Video Amplifier"
The packaged types can be supplied to six screening ,Ievels11N,I1R,I1,12./3, and 14-which correspond to MIL-STD-883
Classes A. B, and C. The chip version can be supplied to three
screening levels-1M. IN. and IR. These screening levels and
detailed information on test methods, procedures. and test
sequence are given in Reliability Report RIC-202A "HighReliability CA3000 Slash (I) Series Types Screened to MILSTD-883."
The CA3001 Slash (I) Series type is supplied in the 12-lead
TO-S style package ("T" suffix) or in chip form ("H" suffix).
D,
D2
,. R"
2,2 K
2
•
All resistors
are in ohms.
·'2
VEE 3
'Inlornal Connectlon- DO NOT USE
Fig. 1 - Schematic dllllJram.
282
9-74
File No. 714 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA3001 Slash (I) Series Type
MAXIMUM RATINGS, Absolute-Maximum Values
OPERATING TEMPERATURE RANGE ...•
STORAGE TEMPERATURE RANGE
-ss"C to +l2S"C
-6S"C to +150"C
LEAD TEMPERATURE (During Solderingl:
At distance 1/16" .1/32"
11.59 mm .0.79 mml
from case for 10 s max.
26S"C
. ........... .
MAXIMUM SINGLE·ENDED INPUT·
SIGNAL VOLTAGE . • . . • . • • . . . . . . •
MAXIMUM COMMON·MODE INPUTSIGNAL VOLTAGE . . . . . . . • . . . . • • •
MAXIMUM DEVICE DISSIPATION . . . • . . .
ABSOLUTE-MAXIMUM
LIMITS at TA = 25°C
VOLTAGE
AND
±2.SV
±2.SV
30DmW
CURRENT
Indicated voltage or current limits for each terminal can be applied
under the specified conditions for other terminals. All Voltages are
with respect to ground (common terminal of Positive and Negative
DC Supplies).
VOLTAGE OR
VOLTAGE DR
TERMINAL
CURRENT LIMITS
NEGATIVE
I
CONDITIONS
-2.5
POSITIVE
+2.5
NEGATIVE
TERMINAL
2,6
0
-6
+6
1,6
3
·8.5
-10
0
3,10
0
-8.5
9
+6
1,2,6
0
9
+6
-6
0
10
4
·8.5
6
-6
-2.5
+2.5
8
0
3
-6
9
+6
200-0 RESISTOR
25 rnA
CONNECTEOBETWEEN
TERMINALS NO.8 & No.1
9
0
+10
10
·10
0
I, 2, 6, 10
3
0
-6
1,2,6
0
-6
0
9
+6
-6
1,2,6,10
0
3
-6
+6
1,2,6
0
3,10
9
-6
+6
1,2
0
3,10
-6
+6
9
INTERNAL CONNECTION
7
VOLTAGE
1,2,6,10
1,2,6
0
0
CONDITIONS
TERMINAL
3
9
10
5
POSITIVE
VOLTAGE
3,10
9
2
CURRENT LIMITS
TERMINAL
DO NOT USE
11
9
25 rnA
+6
2Oa-fl RESISTOR
CONNECTEO BETWEEN
TERMINALSNCLIO&NCLlI
INTERNAL CONNECTION ..
12
CASE
DO NOT USE
INTERNALLY CONNECTED TO TERMINAL No.3
(SUBSTRATE)
00 NOT GROUND
283
CA3001 Slash
(II
Series Type _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 714
ELECTRICAL CHARACTERISTICS, AT TA
=2SoC, VCC =+6V, VEE =-6V
LIMITS
SPECIAL TEST CONDITIONS
CHARACTERISTICS
SYMBOLS
Terminals No.4 and No.5
TYPE
Not Connected
CA3001
Unless Specilied
Typ.
Units
STATIC CHARACTERISTICS:
Input Offset Voltage
VIC
1.5
mV
Input Ollset Current
110
1
jJA
II
16
jJA
VOO
54
mV
V·
Input Bias Current
Output Offset Voltage
TERNINALS
Quiescent Operating
Voltage
V8
4
5
A
NC
NC
4.4
B
NC
VEE
4.8
V
C
VEE
NC
2.7
V
D
VEE
VEE
4
V
A
NC
NC
78
mW
B
NC
VEE
71
mW
C
VEE
NC
110
mW
VEE
86
mW
OR
V11
Device Dissipation
MODE
PT
D
VEE
DYNAMIC CHARACTERISTICS:
Differential Voltage Gain
(Single-ended input and output)
Bandwidth at -3 dB Point
Maximum Output Voltage Swing
Noise Figure
Common-Mode Rejection Ratio
ADIFF
I = 1.75 MHz
19
dB
I = 20 MHz
14
dB
29
MHz
BW
VOUTcP-P)
I = 1.75 MHz
5
Vp_p
I = 1.75 MHZ, RS = 1 KD
5
dB
1= 11.7 MHz, RS =1 KD
7.7
dB
88
dB
NF
CMR
1=1 KHz
Input Impedance Components:
Parallel Input Resistance
Parallel Input Capacitance
Output Resistance
AGC Range (Maximum voltage
gain to complete cutoll)
284
RIN
I = 1.75 MHz
140
KD
CIN
f = 1.75 MHz
3.4
pF
ROUT
f = 1.75 MHz
45
0
AGC
I = 1.75 MHz
60
dB
File No. 714 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _CA3001 Slash (I) Series Type
Table I. Group A Electrical Sampling Inspection
Limits for Indicated Temp. (oC)
Characteristics
~ymbol
Test Conditions
VCr:: = -Iii V ,
VEE = ·6V
Maximum
Minimum
'55
-125
+125 '55
Units
-125 +125
Static
Input Unbalance
CUllent
Input Bi as CUllent
Output Oflset VoltagE
IIU
-
-
-
-
23
10
5
~
II
-
-
-
-
66
36
22
~
Voo
-
-
-
-
420
300
260
mV
3.8
3.8
3.8
4.8
4.8
4.8
V
Terminal 4
TerminalS
NC
NC
Terminal 4
TerminalS
NC
NC
60
60
50
125
ll5
llO
mW
NC
-VEE
55
55
45
120
105
105
mW
-VEE
NC
80
80
70
175
160
155
mW
,V EE
,V EE
60
60
50
135
125
125
mW
-
16
-
-
dB
-
-
-
10
-
dB
-
16
-
-
-
-
MHz
1= 1.75 MHz
-
4
-
-
-
-
NF
1= 1.75 MHz, Rs = IkQ
-
-
-
-
8
-
dB
CMR
I = I kHz
-
70
-
-
-
-
dB
V CMR
f = I kHz
-
-
-
-
-
V
Parallel Input R
RIN
f = 1.75 MHz
-
50
-
-
-
-
kQ
Parallel Input C
C IN
f = 1.75 MHz
-
-
-
-
7
-
pF
ROU
f = 1.75 MHz
-
-
-
-
70
-
Q
f = 1.75 MHz
-
55
-
-
-
-
dB
Quiescent
Operating Voltage
Device
Dissipation
~or
II
PT
Dynamic
Differential Voltage
Gain (single-ended
input and output)
Bandwidth at ·3
dB Point
Maximum Output
Voltage Swing
Noi se Fi gure
Common-Mode
Rej ection Ratio
Common Mode
Input Voltage Range
Output Resistance
AGe Range (max.
voltage gain to
complete cutoff)
1= 1.75 MHz
ADil1
1= 20 MHz
BW
V OUT
(P·P)
AGC
-.35
to
+2.5
Vp• p
285
CA3001 Slash (f) Series Type _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 714
Table IL Pre Bum-In Electrical and Post Bum-In Electrical Tests, and Delta Limits *
Electrical Cherecteristics, at TA = 25"C, V+ = +6 V. V- = -6 V
Characteristic
Symbol
Input Offset Current
110
I IIPut· Bi as Current
II
Output Offset Voltage
Voo
Vs or
Vu
Quiescent Operating
Voltage
Device Oi ssipation
PT
Limits
Test Conditions
Min.
Max.tl.
10
±2
~A
36
±4
~A
300
±loo
mV
-
-
-
Units
Max.
TermInal 4: NC
TerminalS: NC
3.S
4.S
±0.5
V
Terminal 4: NC
TerminalS: NC
60
US
±12
mW
• Level 11 and 12 require pre burn-In electrical and post: burn-In electrical tests, and delta limlb
Lev.lt3 requires pre burn-in electr.icaJ test only. The burn-In and operating life tast circuit Is shown in Fig. 5,
Table IlL Final Electrical Tests
TO$.t Conditions
Characteristic
~l
Limits for Indicated
-55
+25
-
-
-
(DC)
Maximum
+125
-55
+25
-
10
-
~A
36
22
~A
-
420
300
260
mV
3.S
3.8
4.8
4.8
4.8
-
60
-
-
US
-
16
-
-
-
110
II
Output Offset Vol tage
V••
Quiescenl Operating
Voltage
Vs or
Vu
Terminal 4: NC
Terminal 5: NC
3.S
p.
T
Terminal 4: NC
TerminalS: NC
ADiff
f= 1.75 MHz
-
-
-
-
Table IV. Group C Electrical Ozaracteristics Sampling Tests (TA = 250 C, VC= +6 V, VEE = -6 V)
Limits
Characteristic
Input Bias Current
Test Conditions
II
-
VOO
Quiescent Operating
Voltage
Vsor
VII
Device
Dissipation
Voltage Gain
286
Symbol
Output Offset Voltage
PT
ADiff
Units
+125
66
I nput Offset Current
Differential Voltage Gain
(single-ended input & output)
Te~p.
Minimum
V+=+6V,
V-=-6V
Input BIas Current
@n Uevlce Dissipation
I~
Symbol
Min.
Max.
Units
-
36
I1A
-
300
mV
Terminal
4 5
NclNC
3.S
4.S
V
Terminal
4 5
NclNC
60
115
mW
16
-
dB
-
f= 1.75 MHz
V
mW
dB
File No. 714 _ _ _ _ _ _ _ _ _-.,..._ _ _ _ _ _ _ _ _ _ _ CA3001 Slash (I) Series Type
TYPICAL DYNAMIC CHARACTERISTICS
POSITIVE DC SUPPLY VOLTS (VCC)· ... 6
NEGATIVE DC SUPPLY VOLTS IVEE)--6
POSITIVE DC SUPPLY VOLTS (Vcc)-+&
NEGATIVE DC SUPPLY VOLTS (VEE)--6
AMBIENT TEMPERATURE (TA)-2S-C
FREQUENCY W a l,7S MHz
20
......
IB.7
'"
i
'"
I
18."
:lz
.
z
g
"" 18.'
C>
llJ
~0
C>
~
18.4
g
16
"
1\
8
>
18..
-7.
1\
\
4
18.3
-'0
-25
2S
50
75
100
AMBIENT TEMPERATURE (TAJ-aC
125
2
0.1
4
6.
2
4
6.
10
4
2
6.
100
2
4
6.
1000
FREQUENCY ( f I - MH:
92CS-13281
Fig. 2 - Differential voltage gain vs. temperature.
Fig. 3 - Differentiall/olrage gain
liS.
frequency.
SOURCE RESISTANCE CRSI-4
92.CS-I5284
Fig. 4 - Noise figure
V5.
source resistance and frequency.
VEE
-6V
9:?LS-2837
Fig. 5 -
Bum-in and operating life test circuit.
287
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 713
ffilm3LJD
Solid State
Linear Integrated Circuits
Monolithic Silicon
High-Reliability Slash(l) Series
CA3002/ . ..
Division
High - Reliability
IF Amplifier
For Applications in Aerospace, Military and Critical Industrial Equipment
Features:
H-1528
10·Lead TO-5 Style Package
•
•
•
•
•
•
•
Input Resistance - 100 kn typo
Output Resistance - 70 n typo
Voltage Gain - 24 dB typo @ 1.75 MHz
Push·Pull Input, Single·Ended Output
·3 dB Bandwidth - 11 MHz typo
AGC Range - 80 dB typo
Useful Frequency Range DC to - 15 MHz
RCA·CA3002 Slash (/) Series type is a high·reliability
integrated·circuit IF Amplifier intended for applications in
aerospace, military. and critical industrial equipment. It is
electrically and mechanically identical with the standard type
CA3002 described in Data Bulletin File No. 123 but is
specially processed and tested to meet the electrical,
mechanical, and environmental test methods and procedures
established for microelectronic devices in MIL·STD·883.
• AM Detector
• Product Detector
• Schmitt Trigger
• IF & Video
Amplifier
• See Companion Application Note ICAN·503S
"Application of RCA·30021C IF Amplifier"
The packaged types can be supplied to six screening levels/IN.llR.ll.12,/3, and /4-which correspond to MIL·STD·883
Classes A, B, and C. The chip version can be supplied to three
screening levels-1M, IN, and IR. These screening levels and
detailed information on test methods, procedures. and test
sequence are given in Reliability Report RIC·202A "High·
Reliability CA3000 Slash (/) Series Types Screened to MIL·
STD·883."
The CA3002 Slash (/) Series type is supplied in the 10·lead
TO·5 style package ("T" suffix), or in chip form ("H"
suffix).
*
R9
500
Terminal No.6 is an
internal connection
DO NOT USE!
R7
5K
RII
IK
All resistors are in ohms.
92C$-12953R'
Fig. 1 Schematic Diagram
288
9·74
File No. 713 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA3002 Slash
(II Series
MAXIMUM RATINGS. Absolute-Maximum Values:
OPERATING TEMPERATURE RANGE . . • . . . . ·55°Cto+125°C
STORAGE·TEMPERATURE RANGE . . . • . . • . . -65"Cto+150"C
MAXIMUM INPUT·SIGNAL VOLTAGE . . • . . . . . . . . . •3.5V
MAXIMUM DEVICE DISSIPATION . . . . . . . . • . . . . • • 300 mW
LEAD TEMPERATURE (During Soldering):
AI distance 1/16'". 1/32'"
11.59mm. 0.79 mml
from case for 10s max . . . . . . . . . . . . . . . . . . . . . . 26SoC
ABSOLLrrE·MAXIMUM VOLTAGE AND CURRENT LIMITS••t
TA -25°C
Indicated voltage or current limits for each terminal can be applied
under the specified operating conditions for other terminals.
All voltages are with respect to ground (-Vce, +VEE) or common
terminal of Positive and Negative DC supplies).
VOLTAGE OR CURRENT
CONDITIONS
LIMITS
TERMINAL
NEGATIVE POSITIVE TERMINAL VOLTAGE
1
-8 V
.a
2,7
5, 10
Ol!-
0
+6
9
2
3
4
-10
-8.5
V
V
-BV
1,5, 10
OV
OV
CASE
-3.5
V
+3.5
.0
9
+6
1,5, 10
2,7
0
-8
+6
V
1,5, 10
7
·12
V
OV
2
9
0
1,5, 10
7
9
5
INTERNAL CONNECTION
DO NOT USE
6
0
+6
9
OV
VOLTAGE OR CURRENT
CONDITIONS
LIMITS
TERMINAL
NEGATIVE POSITIVE TERMINAL VOLTAGE
.0
9
+6
0
.0
9
+6
20 rnA
n Resistor Between
200
Terminals 7 & 8
0
1,10
2,7
2
I, 5,7, 10
8
0
.0
+6
OV
9
INTERNALLY CONNECTED TO TERMINAL No.2
(SUBSTRATE) DO NOT GROUND
10
·3.5
V
+10
V
+3.5
V
1,5, 10
2,3,7
0
.0
1,5
2,7
.0
9
+6
0
Table 1 - Pre-Burn-In and Post Bum-In Electrical TtJSrs and Delta Lim/a·
TEST CONDITIONS
CHARACTERISTIC
SYMBOL
MIN.
LIMITS
MAX.
-
31
.,0
~A
5.0
15.8
".5
mA
AT TA • 25°C, y+. +6 Y.
V'--6V
v+ .. +6 V, Terminal
No.2'" -6 V,
Input Bias Current
II
Terminal No. 1 to ground
Total Drain Current
IT
12
= 19 -
IT
MAX•. lI
UNITS
-Level, 11 N, 11 A, 11, and 12 require pra and post burn-In electrical tam and delta limits Lwei /3 requlrea pre burn-In electrical
test only. The burn-In circuit JI shown in Fig. 7.
289
CA3002 Slash (I) S e r i e s - - - - - - - - - - - - - - - - - - - - - File No. 713
ELECTRICAL CHARACTERISTICS. at TA = 2~C. V+ = +6 V. V- = -6 V
LIMITS
CHARACTER ISTICS
SYMBOLS
SPECIAL TEST CONDiTIONS
TERMINALS No.3 & No.4
NOT CONNECTED
UNLESS OTHERWISE NOTED
CA3002
Typ.
Units
STATIC CHARACTERISTICS:
Input Unbalance Voltage
VIU
2.2
mV
Input Unbalance Current
IIU
2.2
}LA
II
20
}LA
Input Bias Current
MODE
TERMINAL
2
4
A
VEE
NC
2.8
V
B
VEE
VEE
3.9
V
55
mW
f = 1.75 MHz
24
dB
-
11
MHz
5.5
Vp_p
4
dB
Quiescent Operating
Voltage
Device Dissipation
PT
DYNAMIC CHARACTERISTICS:
Differential Voltage Gain
(Single-Ended Input
ADiFF
and Output)
Bandwidth at -3 dB Point
Maximum Output Voltage Swing
Noise Figure
BW
VOUT(P-P)
NF
f = 1.75 MHz RS = 1
kD
Input Impedance Components:
Parallel Input Resistance
RIN
f = 1.75 MHz
lOOk
D
Parallel Input Capacitance
CIN
f = 1.75 MHz
4
pF
Output Resistance
ROUT
f = 1.75 MHz.
70
D
IMD
-
-40
dB
80
dB
3rd Harmonic Intermodulation Distortion
AGC Range (Maximum Voltage
Gain to Complete Cutoff
290
AGC
f
= 1.75
MHz
File No. 713 - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ __
CA3002 Slash (II Series
Table II - Final Electrical Tests
TEST CONDITIONS
CHARACTERISTIC
SYMBOL
Input Unbalance
Current
IIU
Input Bias Current
II
Total Drain Current
IT
LIMITS FOR INDICATED TEMPERATURES 1°C'
MAXIMUM
MINIMUM
+125
-55
+25
+125
+25
y+ = ->ti Y. Y-. -6 Y
-55
110- 15= IIU
12 + 19 = IT
UNITS
,
-
-
-
35
10
10
IJA
-
-
-
85
35
30
IJA
-
-
-
167
15.8
15.0
mA
Table III - Group A Electrical Sampling Inspection
TEST CONDITIONS
CHARACTERISTIC
SYMBOL
LIMITS FOR INDICATED TEMPERATURES lOCI
MAXIMUM
MINIMUM
+125
-55
+25
+125
-55
+25
V+ =+6V, V-=-6V
UNITS
Static
I"put Unbalance Current
IIU
Input Bias Current
1\
Total Drain Current
IT
Max Output Voltage
+VOM
Min. Output Voltage
+VOM
-
-
-
35
10
10
I'A
-
-
-
8S
35
30
pA
-
-
-
16.7
15.8
15.0
mA
-
4.6
-.
-
5.4
-
V
-
-
-
-
O.OS
-
V
f = 1.75 MHz. RS = 1 kn
-
-
-
-
B
-
dB
-
19
-
-
-
-
dB
-
60
-
-
-
-
dB
IIO·I S = IIU
12+19=IT
Terminal No.1 Ground
Dynamic
Noise Figure
NF
Voltage Gain
A
f"" 1.75 MHz, single-ended
AGC
f= 1.75 MHz
input and output
AGe Range (Maximum
Voltage gain to complete
cutoff)
Table IV - Group C Electrical Characteristics Sampling Tests (TA = 25°C)
CHARACTERISTIC
SYMBOL
Jhput Unbalance Current
IIU
Input Bias Current
TEST CONDITIONS
Y+=->tiY,Y·.-6Y
110. 15= IIU
LIMITS
UNITS
MIN.
MAX.
-
10
IJA
35
IJA
15.8
mA
-
d8
II
-
Total Drain Current
IT
12 + 19 = IT
5.0
Yoltage Gain
A
f = 1.75 MHz, singleended input and output
19
291
CA3002 Slash (II Series'_ _ _ _- - - - - - - - - - - - - - - - - - - - File No. 713
DYNAMIC CHARACTERISTICS
POSITIVE "DC SUPPLY VOLTS (Vee)" +6
NEGATIVE DC SUPPLY .VOLTS (VEE)- 6
POSITIVE DC SUPPLY VOLTS lVee)" +6
NEGATIVE DC SUPPLY VOLTS (VEE)- -6
AMBIENT TEMPERATURE ITA)-2S·C
FREQUENCY (f) .. 1.75 MHz
FREQUENCY ttl -1.75 MHz
25
22
-75
-50
-25
0
25
50
75
100
125
500
92CS-13344
+,.
20
"
~z ,.
I\.
~
~
2000
92CS-13397
POSITIVE DC SUPPLY VOLTS (Vecl a +6
NEGATIVE DC SUPPLY VOLTS (VEE)" -6
AMBIENT TEMPERATURE (fA) .. 25°C
POSITIVE DC SUPPLY VOLTS (Vee)"
NEGATIVE DC SUPPLY VOLTS lYE E) .. -6
AMBIENT TEMPERATURE (TA) ·ZsoC
'"
1500
Fig.S - Noise fig~re vs source resistance.
Fig.2 - Differentia/voltage gain vs temperature.
m
1000
SOURCE RESISTANCE (Rs)-{l
AMBIENT. TEMPERATURE ITAI--C
'\.
10
\
g
1\
5
, ,
2
0.1
.
2
, ,
.
10
, ,
2
.
FREQUENCY (t)- MHz
92CS-13382
Fig.3 - Differential voltage gain
liS
frequency.
100
o
10
15
20
25
30
FREQUENCY (f)-MHz
Fig. 6 - AGe range vs frequency.
92CS-I3401
V+"+16 V
POSITIVE DC SUPPLY VOLTS (Vee)" +6
NEGATIVE OC SUPPLY VOLTS lYEE)" -6
~
~ 10
o
i
•
-75
-50
-25
0
25
50
75
100
125
AMBIENT TEMPERATURE (TAI-OC
92CS-13346
F;g.4 - Bandwidth at -3 dB point Va' temperature.
292
Fig. 7 - Burn-in and operating life test circuit
File No. 712
OOCIBLJD
Linear Integrated Circuits
Monolithic Silicon
Solid State
Division
High-Reliability Slash(/) Series
CA3004/ ...
High-Reliability
RF Amplifier
For Aerospace, Military and Critical Industrial Equipment
Features:
• Operation from DC to 100 MHz
• R F, IF, and Video frequency capability
" Balanced differential amplifier configuration
with controlled constant-current source
12-Lead TO·S Style Package
Applications:
• Detector
• Push·Pull Input and Output
" Wide and Narrow·Band Amplifier
RCA·CA3004 "Slash" (I) Series type is a high·reliability
linear integrated circuit RF Amplifier intended for
applications in aerospace, military, and industrial equipment.
It is electrically and mechanically identical with the standard
type CA3004 described in Data Bulletin File No. 124 but is
specially processed and tested to meet the electrical.
mechanical and enviromental test methods and procedures
established for microelectronic devices in MIL·STD·883.
" AGC
• Mixer
" Limiter
a Modulator
• Companion Application Note ICAN·5022
"Applications of RCS·CA30D4, CA3005, and
CA3006 IC RF Amplifiers"
The packaged types can be supplied to six screening levels-
11 N,/l R ,/1,/2, 13, and 14-which correspond to MI L·STD·883
Cla.,es A, B. and C. The chip version can be supplied to three
screening levels-1M, IN, and IR. These screening levels and
detailed ir:,formation on test methods, procedures, and test
sequence are given in Reliability Report RIC·202A "High·
Reliability CA3000 Slash (I) Series Types Screened to MI L·
STD·883."
The CA3004 Slash (I) Series type is supplied in the 12·lead
TO·5 style package ("T" suffix) or in chip form ("H" suffix).
2.BK
·3
500
·5
0,
.,
0.
5K
'K
2.2K
·2
••
92CS-12959R2
Fig. 1 - Schematic Diagram
9-74
293
CA3004 Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
ABSOLUTE·MAXIMUM VOl-TAGE LIMITS,
File No. 712
at T A =25·C
Voltage limits shown. Cor each terminal can be applied under the indicated circuit conditions for other terminals.
All voltages are with respect to GROUND (common terminal of Positive and Negative DC Supplies)
TERMINAL
VOLTAGE LIMITS
CONDITIONS
NEGATIVE POSITIVE TERMINAL VOLTAGE
1
NO CONN ECTION
6
12
2
3
4
5
-9.5
- -12
-12
~
3
9
0
0
0
·3.5
+3.5
NO CONN ECTION
7
8
0
0
NO CONNECTION
2
-9.5
3
0
-6
0
11
<6
~I
.s
.s
2
6
9
10
0
0
12
0
2
0
-6
.0
9
0
+12
.s
6
10
3
11
<6
<6
9
12
0
.s
11
<6
2
6
0
0
12
0
2
3
6
10
0
-6
0
10
+12
0
6
9
.s
10
11
<6
<6
12
0
II
.s
2,6,12
0
-6
12
0
2
<6
<6
3
0
-6
0
11
.s
2
0
-6
3
9
11
<6
<6
<6
12
0
10
11
12
CASE
0
+12
-3.5
+3.5
MAXIMUM SINGLE-ENDED INPUT.
SIGNAL VOLTAGE . . . . . . . • • . . . . . •
MAXIMUM COMMON-MODE INPUTSIGNAL VOLTAGE •••.••..• '. • . . . .
MAXIMUM DEVICE DISSIPATION .•••.•.
-2.5 V. +3.S V
300 mW'
OPERATING-TEMPERATURE RANGE •..•
STORAGE-TEMPERATURE RANGE • • . . . .
-SS"C 10 +125"C
-6S"C to +ISO"C
.3.S V
LEAD TEMPERATURE (During Soldering):
At distance 1116" .1/32"
(1.59 mm .0.79 min)
from case for 10 s max.
............
6
9
10
11
<6
.s
.s
.s
INTERNALLY CONNECTED TO TERMINAL
NO.3 (SUBSTRATE) DO NOr-GROUND
MAXIMUM RATINGS. Absolu.Maximum V.lues·
294
CONDITIONS
POSITIVE TERMINAL VOLTAGE
.s
.s
10
6
VOLTAGE LIMITS
NEGATIVE
10
3
9
0
TERMINAL
265°C
File No. 712 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CA3004 Slash (I) Series
ELECTRICAL CHARACTERISTICS. at TA = 25°C. V+ = +6V.
V' = ·6 V unless otherwise specified
LIMITS
CHARACTERISTICS
SYMBOLS
TEST CONDITIONS
Terminals No.4 and NO.5 Open
Unless Utherwise Specified
TYPE
CA3004
Typ.
Units
STATIC CHARACTERISTICS
Input Offset Voltage
VIO
l.7
.mV
Input Offset Current
lID
0.125
J-LA
21
,uA
Input Bias Current
II
TE~MINALS
4
5
NC
NC
1
rnA
V·
NC
2.7
rnA
NC
V·
0.45
rnA
V·
V·
l.25
rnA
Ig II 11
1.1
-
PT
26
mW
MHz
12
dB
MHz
6.3
dB
98
dB
-
dB
19
Quiescent
Operating
Current
or
111
Quiescent Operating
Current Ratio
Device Dissipation
DYNAMIC CHARACTERISTICS
Power Gain
Gp
f
Noise Figure
NF
f
= 100
= 100
CMRR
f
=1
AGC
f
= 1.75
common Mode
Rejection Ratio
AGC Range (Max. voltage
Gain to Complete Cutoff)
kHz
MHz
Table I - Pre Burn-In and Post Burn·ln Electrical Tt!$ts and Delta Limits"
CHARACTERISTIC
SVMBOL
Input Offset Voltage
V IO
Input BIIS Current
II
Davice Dissipation
Po
TEST CONDITIONS
TA· 25"C. v+· +6 V.
V---6V
LIMITS
MIN.
-
MAX.
MAX. A
UNITS
5
±2
mV
40
±4
pA
45
i5
mW
'Levels 11N,I1R./1, and 12 require pre and post burn-In electrical tests and delta limits
Lev.1 /3 requires pre burn-In electrlc,l test only. The burn-In circuit is shown in Fig. 4.
295
CA3004 Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 712
Table II - Final Electrical Tests
CHARACTERISTIC
SYMBOL
TEST CONDITIONS
y+. +61( Y-· -6 Y
LIMITS FOR INDICATED TEMPERATURES (OCI
MINIMUM
MAXIMUM
+25
+125
+25
+125
-55
UNITS
. -55
STATIC
-
16
-
-
45
-
mW
110
-
-
-
9
5
7
I'A
II
-
-
-
60
40
40
I'A
10
-
-
-
-
dB
-
-
9
-
dB
Device Dissipation
Po
Input Offset Current
Input Bias Current
DYNAMIC
Power Gain
Noise Figure
Gp
Dill. Amp., f = 100 MHz
-
NF
Dill. Amp., f = 100 MHz
-
-
Table III - Group A Electrical Sampling Inspection
CHARACTERISTIC
SYMBOL
TEST CONDITIONS
T A • 25"c, y+ +6Y,
Y-=-6Y
LIMITS FOR INDICATED TEMPERATURES (oCI
MAXIMUM
MINIMUM
+125
+25
+125
+25
-55
-55
UNITS
I
STATIC
Input Offset Voltage
VIO
-
-
-
5
Input Offset Current
110
-
-
-
9
Input Bias Current
II
-
-
-
Device
Dissipation
Po
16'
16
14
100 MHz
-
10
f=I00MHz
-
-
Terminals 4 & 5 NC
5
mV
5
7
I'A
60
40
40
I'A
50
45
45
mW
-
-
-
-
dB
-
-
-
9
-
dB
-60
-
-
-
-
dB
i5
OYNAMIC
Power Gain
Gp
Noise Figure
NF
AGC Range (Ma•.
Yoitage gain to
Complete Cutoffl
f~
AGC.
Table IV - Group C Electrical Characteristics Sampling Tests (TA = 250 C)
CHARACTERISTIC
SYMBOL
Device Dissipation
Po
Power Gain
Gp
Iinput Bias Current
II
TEST CONDITIONS
V+=+6Y,Y-=-6Y
f= 100MHz
LIMITS
MIN •.
,.
MAX.
UNITS
-
45
mW
10
-
dB
-
40
I'A
Input Offset Voltage
VIO
-
5
mV
Input Offset Current
110
-
5
IJA
296
File No. 712 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA3004 Slash (I) Series
TYPICAL DYNAMIC CHARACTERISTICS FOR TYPE CA3004
POSITIVE DC SUPPLY VOLTS (Vee)- +6
NEGATiVE DC SUPPLY VOLTS (VEE)--6
FREE-AIR TEMPERATURE {TFAI • 2~·C
SOURCE RESISTANCE (R,J • 50 Q
POSITIVE DC SUPPLY VOLTS Wee)· +6
NEGATIVE DC SUPPLY VOLTS (VEE). -6
FREE -AIR TEMPERATURE (TFA) • 2~-C
SOURCE IMPEDANCE (R,I • ~o tl
LOAD IMPEDANCE (RLI •
so Q
7
""
...
"'
......
2
i
. ,.
i"'
I"-
!'!
i..
..
..
~
!
r-..
Vi'"
S
;;:
10
V
~ ..•
•
10
6
... ...
2
•
• • •
FREQUENCY (f)-Mell
Fig. 2 - Power Gain Vs Frequency
1
••
100
92CS-I5369
/
4
2
10
•
• • •
FREQUENCY (f)-Me/l
1
.,
100
Fig. 3 - Noise Figure Vs Frequency
+6V
V-·-6V
Fig. 4 -
Bum-In and Operating Life Test Circuit
297
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 763
llCI8LJD
Solid State
Linear Integrated Circuits
Monolithic Silicon
High-Reliability. Slash(/) Series
CA3006/•••
Division
High-Reliability
RF Amplifier
For Applications in Aerospace, Military and Critical Industrial Equipment
Features:
12·Lead T().5 Styl. Package
H-1463
•
•
•
•
•
•
•
Input offset voltoge (V,ol = 1 mV (max.1
AGC range = 60 dB (min.) at 1.75 MHz
Cascode power gain = 20 dB (typ.l at 100 MHz
Operation from de to 100 MHz
Sharp limiting characteristics
Balanced input and output
Uncommitted bases and collectors
RCA·CA3006 "Slash"' (I) Series types are high·reliability linear
integrated circuits intended for a wide variety of applications in
aeraspace, military. and critical industrial equipment aperating
at frequencies up to. 100 MHz. They are electrically and
mechanically identical with the standard type CA3006 de·
scribed in Data Bulletin File Na.125 but are specially pro.·
cessed and tested to. meet the electrical. mechanical and
enviranmental test methads and pracedures estabiished far
micraelectranic devices in MIL-STD·B83.
The packaged types can be supplied to. six screening levels11N./lR.ll.12./3. and 14-which carrespand to. MIL-STD-883
Classes A. B. and C. The chip versian can be supplied to. three
screening levels-1M, IN, and IR. These screening levels and
detailed infarmatian an test methads. pracedures, and test
sequence are given in Reliability Report RIC·202A "'High·
Reliability CA3000 Slash (II Series Types Screened to. MIL·
STD-883."'
Applications:
• Wide and narraw band
amplifiers
• Detectors
• Mixers
• Limiters
• Modulatars
• Cascade Amplifiers
Y-.6V
92CS-15381R2
. Burn-in and operating life test circuit.
",
OK
2.2K
SEE NOTE
®
CASE AND
The CA3006 Slash (II Series types are supplied in the 12·lead
TO·5 style package ("'T"' suffix), and in chip farm ("'H"' suffix).
SUBSTRATE
RESISTANCE VALUES
IN OHMS
92CS-13343RI
NOTE: Connect Terminal No.9 to most ~.
tive de supply voltage used for circuit.
Fig. 1 - Schematic diagram of CA3006.
MAXIMUM RATINGS, Absalute·Maximum Values
atTA = 25°C:
DEVICE DISSIPATION. • . .
SINGLE·ENDED INPUT·SIGNAL
VOLTAGE . • . . • . .
COMMON·MODE INPUT·SIGNAL
VOLTAGE. . . . • . .
298
300
mW
±:l.5
V
-2.5 to +3.5
V
AMBIENT TEMPERATURE RANGE:
Operating . . • . . . . .
Storage. . . . . . . . .
LEAD TEMPERATURE (During Soldering):
At distance 1/16 ± 1/32 in.
(1.59 ± 0.79 mm) from case for
10smax.
-55 to +125
-65 to +150
+300
9-74
File No. 763 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA3006 Slash (/) Series
Maximum Voltage Ratings at TA = 25°C
This chart gives the range of voltages which can be applied to the terminals listed vertically
with respect to the terminals listed horizontally. For example, the voltage range of the
vertical terminal 9 with respect to terminal 5 is 0 to +18 volts.
,
.
·
. . · ·
.
·
·
. .
10
9
12
11
1
2
+18
0
3
+18
0
+18
0
*
.
+12
0
*
*
+18
-18
*
*
+1
-4
+18
-18
·
lOUT
·
INAL
No.
',N
No .
mA
mA
+18
0
9
9
-
-
+12
-1
+18
0
10
10
+20
-I{).1
+18
0
11
11
+20
-I{).1
+18
-5
12
12
-
-
1
+2
-I{).1
. ·
. ·
*
+10
-4
+,
-4
*
1
*
"
+10
0
+,
-1
"
2
2
+20
+20
"
*
+1
-4
"
+10
-5
"
*
+10
-5
"
*
*
+12
-1
*
TERM-
TERM·
INAl
8
7
+18
0
+18
0
+12
0
+12
-1
6
5
Maximum
Current Ratings
.
+4
-10
3
3
-
-
,
4
-
-
*
*
5
5
-
-
6
6
-
-
*
)
7
+2
-I{).1
8
8
+0.1
+20
REF.
SUB·
STRATE
• Voltages are not normally applied between these terminals.
Voltages appearing
between these terminals will be safe if the specified limits between all other
terminals are not exceeded.
DIFF ERENTIAL -AMPLIFIER CONF IGURATION
AMBIENT TEMPERATURE (TA}'2S-C
30
CASCOOE CONFIGURATION
AMBIENT TEMPERATURE (TA,-2S·C
..
i ..
::
25
20
r-....
~,>
sJ
~'"
«
w
~
~
'~"'"~v.
30
......
I
· ... 1
"z
...... ,~:::-
z
~
II
I II
r-..: "0,,)
[-....su~1
40
20
.
~
'"w
1'"'-......
~
("':",... ~
1"3 :::..."
a
i'-
15
10
"
"
10
•
10
,
,
,
•
, , , , ,
100
FREQUENCY t f 1 - IolHl
,
,
,
10
FREQUENCY{f J -
,
6
7
.
"-
"-
,
100
MHz
92CS'13520RI
Fig.3 - Power gain vs. frequency, differential amplifier configuration.
l-i9.2 - ,Power gain vs. frequency. cascade configuration.
Table I - Pre Bum-In Electrical and Post Burn-In Electrical Tests, and Delta Limits·
ELECTRICAL CHARACTERISTICS at TA = 250 C V+ = 6 V V-
c
6 V
LIMITS
CHARACTERISTIC
Input-Elias Current
Quiesce'nt
Operating Current
Device Dissipation
SYMBOL
TEST CONDITIONS
118
110
or
111
Po
UNITS
Min.
Max.
Max"",
-
-
40
±4
~A
Terminal 4: NC
Terminal 5: NC
0.6
1.6
±0.2
rnA
Terminal 4: NC
Terminal 5: NC
16
45
±5.4
rnW
• Levels)1 and /2 require pre burn-in electrical and post burn-in electrical tests, and delta limits:.
Level/3 requires pre burn-in electrical test only. The burn-in and operating life test circuit is: shown on page 298.
299
CA3006 Slash (I) Series
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 763
ELECTRICAL CHARACTERISTICS, Typical Values Intended Only For Design Guidance
LIMITS
SPECIAL TEST CONDITIONS
CHARACTERISTIC
SYMBOL
TYPE
CAlOO6
Terminals No.3..4.5. and 6 Not
Connected Except Where Noted
UNITS
Typ.
STATIC
Input Offset Voltage
YIO
0.8
Input Offset Current
110
1.4
!JA
Input Bias Current
liB
19
!JA
mY
TERMINALS
5
4
-NC-Nt-
110
Quiescent Operating
Current
or
111
~
Y-
NC
Y-
1
mA
2.7
mA
...!:i£...
0.45
mA
1.25
mA
1.05
-
26
mW
20
dB
Y-
..'lQ..
Quiescent Operating
Current Ratio
I"
Po
Device Dissipation
DYNAMIC
Power Gain
Gp
f=
Cascade Configuration
100
MHz
Differential-Ampl.
f
Noise Figure
NF
Common-Mode
Rejection Ratio
CMRR
AGC Range (Max. Yaltage
Gain to Complete CutaW
AGC
16
dB
7.8
dB
7.8
dB
101
dB
-
dB
Configuration
=
Cascade
100
MHz
Configuration
Differential Ampl.
Configuration
f = 1 kHz
f = 1.75 MHz
Table II - Final Electrical Tests
CHARACTERISTIC
SYMBOL
LIMITS
FOR INDICATED TEMPERATURE (oCI
TEST CONDITIONS
Minimum
V+ = 6 V. V- = 6 V
-55
I
+25
I
UNITS
Maximum
+125
-55
I
+25
I
+125
STATIC
Input Offset Current
110
Input Bias Current
liB
Quiescent Operating
110
111
Terminal 4
NC
Te~minal
PD
Terminal 4
NC
Terminal 5
NC
Current
Device Dissipation
5
NC
-
-
-
-
2
-
"A
-
-
60
40
30
"A
0.6
0.6
0.5
1.7
1.6
1.4
rnA
-
16
-
-
45
-
rnW
DYNAMIC
Power Gain
Noise Figure
300
I
Gp
I f = 100 MHz
Diff. Amplifier
NF
f = 100 MHz
Configuration
I I -
14
-
-
-
I
I
-
I I 9
- I
dB
I
dB
-
File No. 763
CA3006 Slash (/) Series
Table III - Group A Electrical Sampling Inspection
Limits for Indicated Temp. (OC)
CHARACTERISTIC
SYMBOL
TEST CONDITIONS
I
Minimum
V+=6 V. V- = 6V
-55
+25
+125
UNITS
Maximum
-55
+25
+125
STATIC
Input Offset Voltage
VIO
Input Offset Current
110
4
Input Bias Current
liB
60
Terminal 4
110
Quiescent Operating Current
I"
Device Dissipation
PD
1.5
rnV
40
30
"A
"A
Terminal 5
NC
NC
0.6
0.6
0.5
1.7
1.6
14
rnA
NC
V-
1.6
1.6
1.4
4.5
4.4
4
rnA
V-
NC
0.25
0.25
0.25
O.S
0.75
0.S5
rnA
V-
v-
0.7
O.S
0.75
2.3
2.4
2.2
rnA
Terminal 4
Terminal 5
NC
NC
16
16
14
50
45
45
rnW
NC
V-
45
45
40
125
120
110
rnW
V-
NC
10
10
30
30
30
rnW
v-
V-
20
25
70
70
70
rnW
20
DYNAMIC
Cascade
16
dS
14
dB
Configuration
Power Gain
Gp
f = 100 MHz
Djfferential
Amplifier
Configuration
Cascade
NF
Noise Figure
dB
Configuration
f = 100MHz
Differential
Amplifier
9
dB
Configuration
AGe Range
(Max. Voltage Gain
AGC
-60
f = 1.75 MHz
dB
to Complete Cutoff)
Table IV - Group C E1eclIical Characteristics Sampling Tests (TA = 25 0 C, v+ = 6 V, V- = 6 V)
LIMITS
CHARACTERISTIC
SYMBOL
TEST CONDITIONS
UNITS
Max.
Max."
-
40
±4
"A
0.6
1.6
±O.2
rnA
16
45
±5.4
rnW
14
-
±2
dB
Min.
Input Bias Current
Quiescent
Operating
Current
-
liB
110 or
Terminal
I"
Terminal
Device
Dissipation
PD
Power Gain
(Differential)
Gp
~
NC NC
*
NC
f'" 100 MHz
NC
301
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 715
mcraLJO
Linear Integrated Circuits
Monolithic Silicon
Solid Stata
Division
High-Reliability Slash(/) Series
CA3015A/•••
High-Reliability
Operational Amplifier
For Applications In Aerospace, Military and Critical Industrial Equipment
Features:
• Open-loop voltage gain ••••••••••..
•
•
•
•
•
•
H-I463
12-Lead TO-S Style Package
Common-mode rejection ratio _ . _ ••..
Input impedance . . • • . . • • . . . • . • . •
Input offset voltage •.••.•••••••••
Input offset current •.•.•••..•.•••
Input bias current
Static power drain at ± 12 V
...............
........
70 dB
103 dB
10kn
1 mV
0.51'A
4.71'A
175mW
MAXIMUM RATINGS, Absolute-Maximum Values:
Applications:
Operating-Temperature Range
• Narrow-band and bandpass amplifier
Storage-Temperature Range
....•..•••..
....•...•....
-55°C to +125°C
-6SoC to +15a'C
LEAD TEMPERATURE lOuring Solderingl:
At distance 1116" ± 1/32"
11_59 mm ± 0_79 mml
from case for 10 s max. . . . . • . . . • . . . . . . . . . .
265°C
Maximum lnput-Gignal Voltage . • . • • • . • . . • . . . . . -8 V. +1 V
MAXIMUM DEVICE DISSIPATION:
Upto70"C .. _ . . . . . . . . . ____ 700mW
At Ambient
Above 70"C .•••• _ • •. Derate at 6.7 mWfC
Temperatures
At Case
Up to 125°C. • . . . • • • • • • • • • •• 830 mW
Temperatures
2kn
.OII'F
92CS-22841
Bum-in and operating life ,test circuit.
302
•
•
•
•
Operational functions
Feedback amplifier
DC. and video amplifier
Multivibrator
typo
typo
typo
typo
typo
typo
typo
•
•
•
•
•
Oscillator
Comparator
Servo driver
Scaling adder
Balanced
modulator-driver
RCA-CA3015A "Slash" (I) Series type is a high-reliability
linear integrated circuit operational amplifier intended for
applications in aerospace, military, and industrial equipment.
It is electrically and mechanically identical with the standard
type CA3015A described in Data Bulletin File No. 310 but is
specially processed and tested to meet the electrical,
mechanical and environmental test melhods and procedures
established for microelectronic devices in MIL-STD-883.
The packaged types can be supplied to six screening levels11N.l1R,/1.12,/3, and 14-which correspond to MIL-STD-883
Classes A, B, and C_ The chip version can be supplied to three
screening levels-1M, IN, and IR. These screening levels and
detailed information on test methods, procedures, and test
sequence are given in Reliability Report RIC·202A "HighReliability CA3000 Slash (I) Series Types Screened to MILSTD-883."
The 'CA3015A Slash (I) Series type is supplied in the 12-lead
TO-5 style package ("T" suffix) or in chip form ("H" suffix).
9-74
File No. 715
CA3015A Slash
III Series
Maximum Valtage Ratings at T A = 2Sa C
The following chart gives the range of voltages wnich can be applied to the terminals
listed vertically with respect to the terminals listed horizontally. For example, the
voltage range of the vertical terminal 12 with respect to terminal 10 is 0 to -15 volts.
TERMINAL
No.
12
1
2
3
4·
5
6
7
12
I
.
2
3
4"
5
6
. . ·
. .
· ·
· ·
·
+15
+5
-5
-I
+20
·5
+5
·5
+18
·5
Note 2
+18
·5
+1
·15
Note 2
0
-30
Note 3
*
7
8
9
10
11
Maximum
Current Ratings
TERMINAL
No.
· · ·
· · · · ·
· · · · ·
· · · · ·
0
-15
0
·30
*
0
·30
+1
-15
lOUT
mA
1
1
1
-
-
2
1
0.1
3
1
0.1
12
-
0
-32
*
4·
-
-
· · · ·
· ·
·
0
-30
·
5
-
-
0
·20
*
6
1
1
0
·20
·
7
3
3
+1
·5
0
-30
·
8
3
3
0
·32
·
9
30
30
+20
0
10
-
-
11
3
3
8
+1
·15
+20
-5
9
10
11
.&
liN
mA
CA3015A Case is internally connected to the substrate (Terminal Lead J#4), DO NOT GROUND.
Note 1: For normal circuit operation, external voltages should not be
applied to terminals 5,6,8. and 12.
Note 2: This rating applies only to the more positive terminal of terminals 2 or 3.
Note 3: Carefully observe maximum dissipation ratings.
these terminals. Voltages
appearing between these terminals will be safe if the specified limits
between all other terminals are not exceeded.
* Voltages are not normally applied between
303
CA3015A Slash
III Series
- -_ _ _"'--_ _ _ _ _ _ _ _.....,..._ _ _ _ _ _ _ File No. 715
r----------------T------~----~----~--ovcc
10
RI6
I.SK
IK
5
RI5
92CM-15435
Fig. 1 - Schematic diagram.
POSITIVE DC SUPPLY VOLTS
POSITIVE DC SUPPLY VOLTS (v+,
NEGATIVE DC SUPPLY VOlTS (V-)
AMBIENT TEMPERATURE (TA)'25°C
TERMINAL No. 10 OPEN
(V+l
NEGATIVE DC SUPPLY VOLTS (v-)
T
SOURCE RESISTANCE (RS'-Ik.n
TERMINAL No. 10 OPE~
":.
110
~z 75~~~~~~~fE~~=Ht=~~tt~t=:~
~
[I'"
60
50 AMBIENT TEMPERATURE
40
1~~.-55.C
V+"12V
~
20
II
10I--+--+Iftt-+-t-+tt-+-+f-tt-+
I~!:tl\\c~:::li"\i<\\-,f-H
I
II
0.01
• ,2
n
0.1
FREQUENCY Ifl-MHr
1\\\
10
\~
70
304
Open loop voltage gain
VI.
frequency
v""
12 V
r'-..
50
\
40
100
-
"V-"'-12V -
60
0.001
92CS-14848RI
Fig. 2 -
V+;6 V
V-"-6V
~
°z-'I 301--+--+-+t+-++++I-+-+ .
~V-:-12V
~::-~~ ~ I\~
0001
"-
BO
is
~
......
90
IT ro;;;;;
~
i
100
TOF
0.01
0.1
FREQUENCY (f)-MHz
10
100
92CS-14859RI
Fig. 3 -
Common-mode rejection ratio VI. frequency
File No. 715 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA3015A Slash
II)
Series
ELECTRICAL CHARACTERISTICSATTA =2SoC
SYMBOLS
CHARACTERISTICS
TEST CONDITIONS
V+~+12V. V= -12V
TERMINAL NO.5 NOT
CONNECTED UNLESS
OTHERWISE SPECIFIED
CA3015A
UNITS
f.-TYP.
STA TIC CHARACTERISTICS:
Input Offset Voltage
VIO
1
mV
Input Offset Current
110
0.5
J!.A
Input Bias Current
II
4.7
~A
Input Offset Voltage
Positive
Sensitivity:
AVIO/AVCC
AVIO/AVEE
Negative
PT
Device Dissipation
Terminal 8 shorted to
0.096
0.156
mV/V
175
500
mV
Terminal 12
,DYNAMIC CHARACTERISTICS:
Open-Loop Differential
Voltage Gain
dB
AOL
70
Open-Loop Bandwidth
kHz
BWOL
at -3 dB Point
320
7
RS=lkll
Slew Rate
SR
Common-Mode Rejection
Ratio
CMRR
VI",
dB
103
Maximum Output-Voltage
VOIP.P)
Swing
Input Impedance
14
Vp.p
kll
ZIN
10
11
Output Impedance
ZOUT
85
Common-Mode
V
VeMR
+0.65
·8
Input·Voltage Range
dB
R,=lkll
NF
Noise Figure
11
17.5
IJ>
15
"'
~12.5
VCC"12V
VEE~-12V
!:;
~
10
AMBIENT TEMPERATURE (TAl· -55°C
5
i!f
;.
~
7.5
~
2.'
;
.LJ..LLJ...L_
.
POSITIVE DC SUPPLY VOLTS (Vee») ~
NEGATIVE DC SUPPLY VOLTS (VEE)
TERMINAL NO.8 ~ SHORTED TO
TERMINAL No.12 ~1 . '1 '
0.25
0.5
0.75
1.25
1.5
1.75
10
LOAD RESISTANCE IRLI-K OHMS
2
"
LOAD RESISTANCE IRLI- K OHMS
92C5-14849
Fig. 4 - Maximum peak-to-peak output voltage
20
92CS-14862
I'S.
load resistance.
305
CA3015A Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 715
Table I
Pre Bum·ln and Post Burn·ln Electrical Tests and Delta Limits*
ELECTRICAL CHARACTERISTICS, at TA = V+ = +12\(, V· = ·12V
LIMITS
CHARACTERISTIC
SYMBOL
Input Offset Voltage
VIO
Input Offset Current
110
Input Bias Current
.
Device Dissipation
TEST CONDITIONS
II
PT
5 shorted to 9
Min.
UNITS
Max.
Max.to
-
2
±I
mV
-
1.6
±I
110
6
240
±I
±25
p.A
p.A
320
600
±50
mW
• Levels 11 and 12 require pre burn-in electrical and post burn-in electrical tests, and delta limits.
Level/3 requires pre burn-In electrical test only. The burn-In lind operating life test circuit Is shown on page 302.
Tablen
Final Electrical Tests
CHARACTERISTICS
TEST CONDITIONS
SYMBOL
LIMITS FOR INDICATED TEMP,(°C)
UNITS
Maximum
Minimum
V+=+I2V, V·=·12V
·55
+25
+125
-
-
-
-
I ·55
+25
+125
3
3
2
3
mV
1.6
2
flA
STATIC
Input Offset Voltage
Input Offset Current
Input Bias Current
Device Dissipation.
-
-
115
110
95
14
280
6
240
8
235
flA
mW
5 shorted to 9
330
320
-
700
600
-
mW
f = 1 kHz
-
66
-
-
-
-
dB
-
VIO
lin
I
PT
-
DYNAMIC
Open· Loop Differential
Voltage Gain
AOL
Table III
Group C Electrical Sampling Tests
TA = +25°C
v+=+12VV·=·12V
CHARACTERISTIC
SYMBOL
SPECIAL
TEST CONDITIONS
Input. Offset Voltage
VIO
-
Input Offset Current
lin
-
LIMITS
UNITS
MIN. MAX.
mV
2
p.A
1.6
Input Bias Current
II
-
-
6
-
-
0.5
mVIV
-
-
0.5
Inpilt Offset Voltage Sensitivity:
Positive
LWIO/LWr.r.
Negative
LWIO/LWEE
Device Dissipation
PT
Open-Loop Differential
Voltage Gain
AOL
Common-Mode Rejection Ratio
CMR
306
p.A
-
110
240
mV/V
mW
Terminal
5 shorted to 9
320
600
mW
f
= 1 kHz
66
dB
f
= 1 kHz
80
-
dB
File No. 715
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA3015A Slash II) Series
Table IV
Group A Electrical Sampling Inspection
Characteristics
Test Coooitions
Symbol V+=+12V.
V·=·12 V
Limits for Indicated
Temperature'lDC)
Minimum
Units
Maximum
·55 +25 +125 ·55 +25 +125
STATIC
Input Ollset Current
Vln
110
-
Input Bias Current
II
-
- - - - - - -
Positive
£lVIO
t::.v+
-
-
Negative
t::.VIO
t::.V·
-
- -
Input Offset Voltage
3
2
8
!LA
0.5
-
mV!V
- 0.5
-
mV!V
3 2
3 1.6
14 6
mV
!LA
Input Ollset Voltage
Sensitivity
Device Dissipation
DYNAMIC
PT
-
115 lIO
5 shorted to 9 330 320
-
95 280 240 235
700 600 -
-
mW
mW
All tests are at 1 kHz except BWOL
Open-Loop Dillerential
Voltage Gain
AOL
-
-
Open· Loop Bandwidth
at ·3 dB Point
BWOL
-
Common·Mode
Rejection Ratio
CMR
Maximum Output·
Voltage Swing
VO(P·P)
-
-
dB
- 200
- - - -
kHz
-
-
80
-
- -
dB
-
-
12
7.5
- - - - - - - - 120 - - - -
66
Input Impedance
liN
Output Impedance
lOUT
-
-
Common·Mode Input·
Voltage Range
VCMR
-
- +0.35
to ·8
NF
RS= 1 K
Noise Figure
- -
-
-
-
-
-
-
-
16
-
-'
Vp.p
k,l1
fl
V
dB
307
File No. 762
OO(]5LJD
Linear Integrated Circuits
Solid State
High-Reliability Slash(l) Series
CA3018A/ ...
Monolithic Silicon
Division
High-Reliability
General-Purpose Transistor Array
For Applications in Aerospace, Military and Critical Industrial Equipment
Features:
• Matched monolithic general-purpose transistors
HFE matched ± 10%
VBE matched ± 2 mV
Operation from DC to 120 MHz
Wide operating current range
CA3018A performance characteristics controlled
from 10 /lA to 10 mA
• Low noise figure - - 3.2 dB typical at 1 kHz
•
•
•
•
•
12-Lead TO-5 Package
H·1463
RCA·CA3018A "Slash" (I) Series types are high·reliability
linear integrated circuits intende9 for a wide variety of
applications in aerospace, military, and critical industrial
Applications:
• General use in signal processing systems in DC
through VH F range
equipment. It consists of four general·purpose silicon n·p·n
transistors on a common monolithic substrate. Two of the
• Custom designed differential amplifiers
four transistors are connected in the Darlington configuration,
• Temperature compensated amplifiers
and the substrate is connected to a separate terminal for maxi·
mum flexibility. The CA3018A is eiectrically and mechanically
identical with the standard type CA3018A described in Data
Bulletin File No. 338 but is specially processed and tested to
meet the electrical, mechanical, and environmental test
methods and procedures established for microelectronic de·
vice in MIL·STD·883.
The packaged types can be supplied to six screening levels11N,I1R,Il.12./3, and 14-which correspond to MIL-STD-883
Classes A, B, and C. The chip version can be supplied to three
screening levels-1M, IN, and IR. These screening levels and
detailed information on test methods, procedures, and test
sequence are given in Reliability Report RIC·202A "High·
Reliability CA3000 Slash (I) Series Types Screened to MIL·
STD·883."
I
o
The CA3018A Slash (I) Series types are supplied in the 12·lead
TO·5 style package ("T" suffix), and in chip form ("H" suffix).
CASE
AND
SUBSTRATE
010
9itCS-I4244RI
Fig. 1 - Schematic diagram for CA3018A.
9·74
30B
File No. 762 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
MAXIMUM RATINGS, Absolute Maximum Values at TA = 25" C
DEVICE DISSIPATION:
Anyone transistor ........................ "
300
Total package ..........•.................. 450
T A >SSOC ..................... derate linearly at 5
AMBIENT TEMPERATURE RANGE:
mW
mW
mwtc
~:::a~!~g.. ::::::::::: ::::::::::::::::::: =~:::: ~~b:~
*
The collector of each transistor of the CA3018AI is isolated from the
substrate by an integral diode. The substrate (terminal to) must be
connected to the most negative point in the external circuit to main-
CA3018A Slash (/) Series
The following ratings apply for each transistor in the device:
15
30
40
5
50
rnA
from case for 10 5 max. . .........•.......... +300
°c
Collector-ta-Emitter Voltage. VCEO .............
Collector-ta-Base Voltage, Vceo ...............
Collector-ta-Substrate Voltage. VCI 0* ............
Emitter-te-Base Voltage, V ESO .................
Collector Current, Ie .........................
LEAD TEMPERATURE lOURING SOLDERINGI:
At distance 1/16± 1/32 in. (1.59 ±O.79 mml
.
.
.
.
.
V
V
V
V
tain isolation between transistors and to provide for normal transistor
action.
ELECTRICAL CHARACTERISTICS (For Each Transistor) Intended For Design Guidance
CHARACTERISTICS
AT TA = 25°C
SYMBOL
SPECIAL TEST CONDITIONS
CA301BA
LIMITS
UNITS
Typ.
STATIC CHARACTERISTICS
Collector-Cutoff Current
I CBO
V CB =10V,I E =0
0.002
nA
Collector-Cutoff Current
I CEO
V CE =10V,I B =0
See Curve
IlA
VIBRICEO
IC = 1 rnA, IB = 0
24
Collector-to-Emitter Breakdown
Voltage
V
Collector-to-Base Breakdown Voltage
V(BRICBO
I C = IO IlA,I E =O
60
V
Emitter-to-Base Breakdown Voltage
VIBRIEBO
IE= IOIlA,IC=O
7
V
VIBRICIO
IC = 10 IlA, ICI = 0
60
V
V CES
IB= 1 rnA,IC= lOrnA
Collector-to-Substrate Breakdown
Voltage
Collector-to-Emitter Saturation Voltage
Static Forward Current Transfer Ratio
0.23
V
IC=10rnA
100
IC= 1 rnA
100
IC = 10llA
54
-
0.97
-
V CE =3V,
hFE
Magnitude of Static-Beta Ratio
V CE = 3 V, ICI = IC2 = 1 rnA
(Isolated Transistors 01 and 02)
Static Forward Current Transfer Ratio
hFED
VCE = 3 V
Base-to-Emitter Voltage
V BE
VCE = 3 V
Input Offset Voltage
I I
Darlington Pair (Q3 and 04)
Temperature Coefficient:
Base-to-Emitter Voltage
BE1
.V
V BE2
°
1 - 02
Base (031·to Ernit1er 1°41 Vollage
Darlington Pair
I
aV BE
I
IC= 1 rnA
5400
IC = 100llA
2800
-
IE= 1 rnA
0.715
IE = 10 rnA
0.800
V CE =3V,
IE= 1 rnA
0.48
rnV
V CE =3V,
IE= 1 rnA
·1.9
rnV/oC
V
aT
VB ED
IV 9 . 1 1
VCE = 3 V
IE = 10 rnA
1.46
IE = 1 rnA
1.32
IE= 1 rnA
4.4
rnVI"C
10
rnV/oC
V
Temperature Coefficient:
Base-to-Emitter Voltage Darlington
Pair.03,04
Temperature Coefficient:
Magnitude of I nput-Offset Voltage
I avBEDI
aT
V CE =3V,
IV BE,.V BE21 VCC = +6 V, V- = 6 V
aT
Ic, = IC2= 1 rnA
309
CA3018A Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 762
TYPICAL CHARACTERISTICS, (Cont'd)
,
CA3018A
DYNAMIC CHARACTERISTICS
SPECIAL TEST CONDITIONS
SYMBOL
f= 1 kHz. VCE=3V.IC=100I'A
low Frequency Noise Figure
NF
Source resistance = 1 Kn
TYP.
UNITS
3.25
dB
Low·Frequency. Small-Signal
Equivalent~Circuit
Characteristics:
Forward Current-Transfer Ratio
hIe
Short-Circuit Input Impedance
hie
Open-Circuit Output Impedance
hoe
t
1=1 kHz. V CE = 3 V.IC = 1 mA
,
~
Open·Circuit Reverse Voltagehre
Transfer Ratio
Admittance Characteristics:
Forward Transfer Admittance
VIe
I nput Admittance
Vie
Output Admittance
Voe
V re
Reverse Transfer Admittance
Gain-Bandwidth Product
Emitter-ta-Base Capacitance
Collector-to-Base Capacitance
K!l
15.6
I'mho
-
1.8 x 10-4
1=IMHz,VCE=3V.IC=1 mA
~
31-jl.5
mmho
0.3+ jO.04
mmho
0.001 + jO.03
mmho
See Curve
mmho
IT
VCE = 3V.IC =3mA
500
CEB
V EB =3V.I E =0
0.6
VCB=3V.IC=0
0.58
pF
2.8
pF
CCI
Collector-to-Substrate Capacitance
110
3.5
VCI=3V.IC=0
CCI
MHz
pF
STATIC CHARACTERISTICS
lO"t
EMITTER CURRENT (IE)-O
I~~
4
2
'0
":!
I
..
"0
24
. .."~
!:!
... '2
:5
u
..
•~
:0
0
COLLECTOR-lO-EMITTER VOLTAGE (VeE)- 3 V
>
9Po·
g
..ffi
.::!':'
V
AMBIENT TEMPERATURE ITA)-25-c
>
VOLTAGE • \~eE\
I I
680.1
2
4
."~
II
6 8 I
2
EMITTER CURRENT (IE1-mA
...~o.a
a
~
~>
I
...
0
.~
~
-:K)
25
50
75
125
Fig. 1 - Typical base·ro-emitter voltage characteristics for each
transistor VI. ambient temperature.
1.7 COLLECTOR-lO-EMITTER VOLTAGE eVCE)-3V
AtISIENT TEMPERATURE (TAl- 2~·C
COLLECTOR-lO-EMITTER VOLTAGE (VeE)-3 V
>
•I •
>
I
....
... '"
....
.. "
LLI
1.6
1I
~o
i
~2:
I
a:: a::
2
/
I.~
/
....
t: z
...-
:00
6~ 1.4
~~
;a
m~I.3
V V
0.1
AMBIENT TEMPERATURE (TA1--C
92CS-Z37BI
Fig. 8 - Typical offset voltage characteristics vs. ambient temperature.
314
100
92C5-23780
Fig. 6 - Typical static base-to-emitter voltage characteristic and
input offset voltage for 0 1 and 02 vs. emitter current.
it
0
-2&
AMBIENT TEMPERATURE (TAI--C
92C5-23779
/
,......
.
•
•
I
/
• • • 10
EMITTER CURRENT CIE)-mA
2
•
92CS-Z371Z
Fig. 9 - Typical static input valtags characteristics fo' Da,lington pai,
(03 and 04) lIS. emitter CUmlnt.
File No. 762 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA3018A Slash (I) Series
COLLECTOR-TO-EMITTER VOLTAGE IVCE,-3V
ffi 1.50
i
'i'1.25
r~
I
.7
-15
-50
-25
AMBIENT TEMPERATURE (TA)--C
92CS-23183
Fig. 10 - Typical static input voltage characteristics for Darlington pair
(Q3 and °41 vs. ambient temperature.
+12(}------~------~------~------_,
-·cr----~~----_4~--_4~--~----'
NOTE: ALL RESISTORS 1/2 WATT
COLLECTOR CURRENT IIcl-fI'IA 92CS-2S792
Fig. 11 - Typical gain-bandwidth product (Ir) vs. collector current.
92CS-23502
Fig. 12 - Bum-in and operating life testcircuir.
315
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 722
Linear Integrated Circuits
llCI8LJ1J
Monolithic Silicon
Solid State
High-Reliability Slash(/) Series
CA3019/ ...
Division
High-Reliability
Diode Array
Diode Quad and Two Individual Diodes
For Applications In Aerospace, Military and Critical Industrial Equipment
Features:
H-1528
10·LEAD TO.s STYLE PACKAGE
J
• Excellent diode match
• Low leakage current
• Low pedestal voltage when gating
RCA·CA3019 "Slash" (/) Series type is a high·reliability
linear integrated circuit Diode Array consisting of a diode
quad and two individual diodes. It is intended for telemetry,
Applications:
• Modulator
data processing, instrumentation and communications appli-
•
cations in aerospace, military, and industrial equipment. It is
electrically and mechanically identical with the standard type
CA30l9 deseribed in Data Bulletin File No. 236 but is
specially processed and tested to meet the electrical, me·
chanical and environmental test methods and procedures
established for microelectronic devices in MIL·STD-883.
• Balanced modulator
The packaged types ean be supplied to six screening levelsI1N, I1R.ll.12, 13, and 14-which correspond to MIL·STD·883
Classes A, B, and C. The chip version ca~ be supplied to three
sereening levels-1M, IN, and IR. These screening levels and
detailed information on lest methods, procedures, and test
sequence. are given in Reliability Report RIC·202A "High·
Reliability CA3000 Slash (/) Series Types Screened to MI L·
STD·883."
Mixer
• Analog switch
• Diode gate for chopper·
modulator applications
• See companion application note ICAN-529ll
application of the RCA CA3019 IC Diode Array
The CA3019 Slash (/) Series type is supplied in the 10·lead
TO·5 style package ("T" suffix) or in chip form ("H" suffix).
* Connect to most negative circuit potential.
Fig. 1 - Schematic diagram.
316
9-74
File No_ 722 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---,_CA3019 Slash (I) Series
Table I - Pre Burn-In and Post Bum'ln Electrical Tests and Delta Limits*
TEST CONDITIONS
SYMBOL
CHARACTERISTIC
MIN.
-
IF-I mA
Each Diode:
-
IF=0.2mA
IF = 20mA
VF
DC Forward Voltage Drop
-
LIMITS
MAX.
MAX."
0.78
0.72
0.95
UNITS
.0.010
.0.010
.0.010
V
V
V
• Le\lels'1 N, '1 R./1, and /2 require pre and post burn-In electrical tests and delta limits
Laval /3 ruqulr•• pre burn-In electrical test only. The burn-In circuit Is shawn In Fig. 5.
TYPICAL CHARACTERISTICS
DC REVERSE VOL.TS (VR) ACROSS DIODE.-4
DC FORWARD CURRENT (I.Ft -lrnA
"'
"T
~O.9
i!s
gj
O.B
w
~
15
w
1'0
u
c
0.'
-75
-50
-25
25
50
75
100
"125
-75
-50
AMBIENT TEMPERATURE ITAI--C
-25
25
50
75
100
Fig. 2 - DC Forward Voltage Drop (any Diode)
CA3019.
VS'
125
AMBIENT TEMPERATURE (TAI-·C
92CS-142~1
CJ2CS-142~3
Temperature for
Fig. 3 - Reverse (Leakage} Current (any Diode) VB Temperature for
CA3019.
Absolute-Maximum Voltage Limits at TA = 25°C
ABSOLUTE-MAXIMUM RATINGS:
TERMINAL
DISSIPATION:
Anyone diode unit
Total for device • . . . . . . • . . . . . •
20 max.
120 max.
mW
mW
TEMPERATURE RANGE:
Storage . . . . • . ' . . . • • . • . . . . . •
Operating . . . • . . • . . . . . . • . . .
1
2
3
-65 10 +150
-5510 +125
'c
'c
4
5
6
LEAD TEMPERATURE (Our;ngSolder;ng):
At distance 1/16" ±1/32"
VOLTAGE LIMITS
POSITIVE
TERMINAL
VOLTAGE
-3
-3
-3
-3
-3
-3
+ 12
7
+ 12
7
+ 12
7
+ 12
7
-6
-6
-6
-6
+12
7
-s
+12
7
-6
0
I, 2,
3,6,
0
(1.59 mm .0.79 mm)
from case for 10$ max.
265"c
7
CONDITIONS
NEGATIVE
-18
8
8
-3
-3
+ 12
7
-6
-6
10
7
NO CONNECTION
CASE
INTERNALLY CONNECTED TO TERMINAL 7
DO NOT GROUND
9
+ 12
317
CA3019 Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 722
ELECTRICAL CHARACTERISTICS. at an Ambient Tom............ T A' of 25"c
CHARACTERISTICS APPLY FOR EACH DIODE UNIT, UNLESS OTHERWISE SPECIFIED.
LIMITS
CHARACTERISTICS
SYMBOLS
DC FOIwald Voltage Drop
VF
SPECIAL TEST CONDITIONS
DC Forwald Current (IF) -I rnA
TYPE
CA3019
Typ.
Units
0.73
V
DC Reverse Breakdown Voltage
V(BR)R
DC Reverse Current (IR) =-IO}LA
6
V
DC Reverse Breakdown Voltage
Between any Diode Unit and
Substrate
V(BR)R
DC Reverse Current (IR) =-IO}LA
80
V
DC Reverse (Leakage) Current
IR
DC Reverse Voltage (VR) =-4 V
0.0055
}LA
DC Reverse (Leakage) Current
Between any Diode Unit and
Substrate
IR
DC Reverse Voltage (VR) = -4 V
0.010
}LA
1
mV
1.8
pF
Terminal 2 or 6 to Terminal 7
4.4
pF
Terminal 5 or 8 to Terminal 7
2.7
pF
10
mV
Magnitooe of Diode Offsel
Voltage (Difference in DC
Forward Voltage Drops of
any Two Diode Units)
IVFI- VF21 DC Forward Current (IF) = 1 rnA
Single Diode Capacitance
CD
Diode Quad-tlrSubstrate
Capacitance
CDQ-I
Series Gale Switching
Pedestal Voltage
Frequency (f) = 1 MHz
DC Reverse Voltage (VR) = -2 V
Frequency (f) - 1 MHz
DC Reverse Voltage (VR) between
Terminal 2,5,6, or 8 of Diode Quad
and Terminal 7 (Substrate) =-2 V
Vs
TYPICAL CHARACTERISTICS
AMBIENT TEMPERATURE TA)·~
FREQUENCY (F) -IMHz
o
I
2
3
DC REVERSE VOLTS (VAl ACROSS
V+ II -6V
D~ODE
92(:5-14252
'32CS-22934·
Fig. 4 - Diode capacitance (any diode) vs revel'8B voltage
forCA3019.
318
Fig. 5 - Burn-ln and operating /ife test Circuit
File No. 722 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA3019 Slash (I) Series
Table II - Final Electrical Tests
CHARACTERISTIC
TEST CONDITIONS
SYMBOL
Each Diode:
l~cO.2mA
-
-
-
-
-
-
~A
-
-
-
10
-
~A
-
-
-
-
5
-
mV
-
50
-
-25
-25
V
VR 0 -4 V
IF = 1 mA
IVF1- VF21
-50 V through a 25 KG to terminal 7.
Ground terminal 1 through 6, 8 and 9,
Breakdown Voltage
Measure voltage at terminal 1
-
-
IR
Isolation-to-Substrate
-
0.72
0.79
0.95
10
IR
DC Reverse Leakage Current
DC Reverse Leakage Current
To Substrate
-
0.97
0.76
VF
UNITS
0.41
IF-I mA
IF = 20mA
VR 0-4 V
DC Forward Voltage Drop
Between Any Two Diodes:
Diode Offset Voltage
LIMITS FDR INDICATED TEMPERATURES lOCI
MINIMUM
MAXIMUM
-55
+25
+125
55
+25
+125
0.60
-25
V
V
V
Table III - Group A Eledtrical Sampling Inspection
CHARACTERISTIC
TEST
SYMBOL
CO~'OITION"
LIMITS FDR INDICATED TEMPERATURES lOCI
MINIMUM
MAXIMUM
-55
+25
+125
-55
+25
+125
Each Diode:
DC Forward Voltage Drop
VF
1.=0.2mA
IF"mA
IF = 20mA
DC Reverse Leakage Current
DC Reverse Leakage Current
To Substrate
IR
VR' -4V
IR
VR' -4 V
-
IF = 1 mA
-
Between Any Two Diodes:
Diode Offset Voltage
lsolation-to-Substrate
Breakdown Voltage
IVFl 'VF21
-
.76
-50 V through a 25 Kn to terminal 7.
-
V
V
V
0.41
0.97
-
-
-
10
-
~A
-
-
-
5
-
mV
-
-25
-25
-25
V
-
Ground terminal 1 through 6, 8 and 9.
0.72
0.78
0.95
UNITS
-
50
0.60
10
~A
Measure voltage at terminal 7
Table IV - Group C Electrical Characteristics Sampling Tests (TA = 250 C)
CHARACTERISTIC
SYMBOL
TEST CONDITIONS
LIMITS
MIN
MAX
UNITS
Each Diode:
DC Forward Voltage Drop
VF
IF=0.2mA
0.39
0.73
V
IF= 1 mA
0.49
0.79
V
IF=20mA
0.59
0.96
10
~A
10
I'A
mV
DC Reverse Leakage Current
IR
VR-4V
DC Reverse Leakage Current
To Substrate
IR
VR =-4V
-
IF= 1 mA
-
5
-50 V through a 25 Kn to terminal
7.Ground terminal 1 through 6, 8 and
9. Measure voltage at terminal 7
-
-25
Between Any Two Diodes:
Diode Offset Voltage
lsolation-to-Substrate
Breakdown Voltage
VF1- VF2
V
V
319
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 767
OO(]5LJD
Linear Integrated Circuits
Monolithic Silicon
Solid State
High-Reliability Slash (I) Series
CA3020A/...
Division
High-Reliability
Multipurpose Wide-Band
Power Amplifier
For Applications in Aerospace, Military and Critical Industrial Equipment
Features:
• Single power supply for class B
• High power output - class B amplifier ...
12·Load TM Style Package
1.0 W typo at V+ = +12 V
• Wide frequency range ...
Up to 8 MHz with resistive loads
• High power gain ...75
+ 25°C
50
75
75
a
-25
25
50
25
-25
0
50
DIFFERENTIAL AMPLIFIER INPUT VOLTAGE (VZ3)-mV
DIFFERENTIAL AMPLIFIER INPUT VOLTAGE (V23)-mV
92CS-1522!5RI
92.CS-15226RI
Fig.2 - Typical trannercharacteristics with R'0shorted out.
AMBIENT TEMPERATURE
75
I."ON·-+- I7'ON"
I"'ON" - + - I7 'ON"
Fig.3 - Typical transfer characteristics with R 10 in circuit.
(TA)~25°C
"I 300
E
..
+12V
H
4.
!
'"
....
z
200
~
~
~
100
'"
~
~
-6V
POWER AMPLIFIER COLLECTOR VOLTAGE eV4.Vr)-V
92LS-2842
92CS-152Z8RI
Fig.4 - nMinimum drive~' typo current-voltage saturation curve.
Fig.5 - Burn-in and operating life test circuit.
TABLE I~ PRE BURN-IN ELECTRICAL AND POST BURN-IN ELECTRICAL TESTS, AND DELTA LIMITS'
Electrical Characteristics at T A = 25°C
CHARACTERISTIC
SYMBOL
TEST CONDITIONS
V+l·
LIMITS
v+t"
Min.
Max.
Max.A
UNITS
Peak Output Currents, 06 & 07
14PK ,I7PK
9V
2V
180
-
±15
mA
Cutoff Currents, 06 & 07
14 Cutoff
9V
2V
-
1
±O.l
mA
17 Cutoff
Differential Amplifier Current Drain
Total Current Drain
*
1+1
9V
9V
6.3
12.5
±1.3
mA
1+1 + 1+2
9V
9V
14
30
±3
mA
Levels /1 and /2 require pre burn·m electrical and post burn-m electrical tests, and delta limits.
Level 13 requires pre burn-in electrical test onlv_ The burn-in and operating life test circuit is shown in
.. v+1 is the collector voltage applied to 01 through Q5
V+2 is the collector voltage applied to Os and 07
322
~ig.
5.
File No. 767 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA3020A Slash (I) Series
ELECTRICAL CHARACTERISTICS AT TA = 25°C
Intended Onlv For Design Guidance
CHARACTERISTIC
SYMBOL
TEST CONDITIONS
LIMITS
DC SUPPLY VOLTAGE
CA3020A
V+l""
Idle Currents.
Os &
Q7
MIN.
TYP.
MAX.
5.5
-
14 10LE
17 10LE
9
2
-
rnA
1+1
9
9
6.3
9.4
12.5
rnA
1+1 + 1+2
9
9
14
21.5
30
rnA
-
1.11
-
Differential Amplifier Current Drain
Total Current Drain
UNITS
V+2'"
Differential Amplifier Input Terminal Voltages
V2
V3
9
2
Regulator Terminal Voltage
Vll
9
2
Forward Current Transfer Ratio, 01 at 3 rnA
hFEl
6
.-
30
75
-
BW
6
6
-
B
-
6
6
200
300"
-
9
9
400
550"
-
9
12
800
1000b
-
"IN
9
12
-
50b
100
rnV
RIN3
6
6
-
1000
-
n
Bandwidth at -3 dB Point
Maximum Power Output
POIMAXI
Sensitivity for POUT = 800 mW
Inpul Resistance - Terminal 3 to Ground
V
2.35
V
MHz
rnW
a RCC=130n
b RCC=200n
TABLE II - FINAL ELECTRICAL TESTS
CHARACTERISTIC
SYMBOL
LIMITS FOR INDICATED TEMP.loCI
TEST
CONDITIONS
V+1'"
V+2'"
MINIMUM
-55
+25
MAXIMUM
+125
-55
+25
UNITS
+125
STATIC
Peak Output Currents, 06 & Q7
14PK,I]PK
9V
2V
-
180
-
-
-
-
rnA
Cutoff Currents, 06 & Q7
'4Cut,'7Cut
9V
2V
,-
-
-
-
1
-
rnA
1+1
9V
9V
5.5
6,3
3,5
16,5
12.5
10
rnA
Differential Amplifier Current Drain
DYNAMIC
Total Current Drain
Sensitivity for POUT
1+1
= 800 mW
... v+ 1 is the collector voltage applied
+ 1+2
"In
to Q, through
V+2 is the collector voltage applied to 06 and 07
9V
9V
6
14
8
51
'30
25
rnA
9V
12V
-
-
-
-
100
-
rnV
aS
323
CA3020A Slash (II Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _:...........
File No. 767
TABLE In - GROUP A ELECTRICAL SAMPLING INSPECTION
TEST
CONOITIONS
CHARACTERISTIC
SYMBOL
LIMITS FOR INDICATED TEMP.(oCI
DC SUPPLY
VOLTAGE
V+l&
V+2A.
UNITS
MINIMUM
-55
MAXIMUM
+25
+125
-55
+25
+125
-
-
-
V
-
-
V
-
-
mA
STATIC
Collector-ta-Emitter Breakdown Voltage,
06& 07 a! 10 mA
Collector-ta-Emitter Bre&kdown Voltage,
Q1 at 0.1 rnA
Peak Output Currents,
Os &
Cutoff Currents, 06 &
Q7
07
Differential Amplifier Current Drain
VIBRICER
-
-
-
25
V(BRICEO
-
-
-
21
-
VIBRICEO
-
-
-
10
-
9V
2V
-
180
-
-
9V
2V
-
-
-
-
1
-
mA
14PK
17PK
14Cutoff
17Cutoff
1+,
,+, + 1+2
9V
9V
5.5
6.3
3.5
16.5
12.5
10
mA
9V
9V
6
14
8
51
30
25
mA
Collector-ta-Emitter
ICEO
10V
3V
-
-
Collector-ta-Base
ICBO
3V
-
-
-
-
0.1
-
-
-
lEBO
-
100
Emitter-ta-Base
0.1
-
hFEl
6V
-
-
30
-
-
-
-
POIMax.1
9V
12V
-
800
-
-
-
-
mW
"In
9V
12 V
-
-
-
-
100
-
mV
Total Current Drain
01 Cutoff (Leakage) ~urrents:
Forward Current Transfer Ratio,
0, at3mA
~A
"A
"A
DYNAMIC
Maximum Power Output,
RCC =200 n
Sensitivity for POUT = 800 mW
TABLE IV - GROUP C ELECTRICAL CHARACTERISTICS SAMPLING TESTS at T A = 25°C
TEST CONDITIONS
CHARACTERISTIC
Peak Output Currents.
Os& 07
Cutoff Currents,
0s&07
Differential Amplifier Current Drain
Total Current Drain
Sensitivity for POUT - 800 mW
SYMBOL
14PK
17PK
'4Cutoff
'7Cutoff
LIMITS
UNITS
V+2'"
MIN.
MAX.
9V
2V
180
-
mA
9V
2V
-
1
mA
1+,
9V
9V
6.3
12.5
mA
1+1 + 1+2
9V
9V
14'
30
mA
"IN
9V
12V
-
100
mV
.. V+l is the collector voltage applied to 01 through aS
V+2 is the collector voltage applied to Os and 07
324
V+,~
File No. 706
OOOBLJD
. Solid State
Linear Integrated Circuits
Monolithic Silicon
High-Reliability Slash(l) Series
CA3028/...
Division
High-Reliability
Transistor Array
Dual Independent Differential Amplifier
For Applications In Aerospace, Military and Critical Industrial Equipment
Features:
• Two differential amplifiers on a common substrate
12 Lead TO-5 Style Package
H-1463
• Independently accessible inputs and outputs
• Maximum input offset voltage - ±5 mV
" Full military temperature range capability - ·55°C to +125°C
RCA·CA3026 "Slash" (II Series type is a high·reliability linear
integrated circuit Dual Independent and Differential Amplifier
is intended for applications in aerospace, military, and
industrial equipment. It is electrically and mechanically
identical with the standard type CA3026 described in Data
Bulletin File No. 388 but is specially processed and tested to
meet the electrical, mechanical and environmental test
methods and procedures established for microelectronic
devices in MIL·STD883.
Applications:
II
Dual sense amplifiers
" Dual Schmitt triggers
" Multifunction combinations - RF/Mixer/Oscillator; Converter/lF
" I F amplifiers (differential andlor cascade)
" Product detectors
• Doubly balanced modulators and demodulators
• Balanced quadrature detectors
• Cascade limiters
The packaged types ean be supplied to six screening levelslIN, I1R.ll.12, 13, and 14-which correspond to MIL-STD·883
Classes A, 8, and C. The chip version can be supplied to three
screening levels-1M, IN, and IR. These screening levels and
detailed information on test methods, procedures, and test
sequence are given in Reliability Report RIC·202A "High·
Reliability CA3000 Slash (I) Series Types Screened to MIL·
STD·883."
• Synchronous detectors
•
Pairs of balanced mixers
• Synthesizer mixers
• Balanced (push·pull) cascade amplifiers
0,
The CA3026 Slash (I) Series type is supplied in the 12·lead
TO·5 style package ("T" suffix) or in chip form ("H" suffix).
'----10,
SUBSTRATE
AND CASE
9
Fig. 1 - Schematic Diagram
CAUTION: Substrate MUST be maintained negative with
rcSJEct to all collector terminals of this device. See
Maximum Voltage Ratings chart.
9·74
325
CA3026 Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 706
MAXIMUM RATINGS, Absolute·Maximum Values, at TA = 25°C
The following ratings apply for each transistor in the device:
POWER OISSIPATION.
Anv one transistor
.............. .
Total package . . . . . . . . . . . . . . . . . . .
ForTA > 5SoC
................ .
TEMPERATURE RANGE:
Operating . . . . . . . . . . . . . . . . . . . . .
Storage . . . . . . . . . . . . . . . . . . . . . . .
300
600
mW
mW
Collector-ta-Emitter Voltage, VCEO . . . . . . .
Collector-ta-Base Voltage, VCBO . . . . . . . . .
Collector-to-Substrate Voltage, Velo" .....
Emitter-to-Base Voltage, VEBO . . . . . . . . .
Collector Current. Ie ...............
Derateat5 mwfC
-55 to +125
ClC
-65 to +200
°c
LEAO TEMPERATURE (Ouring Solderingl:
At distance 1/16" ±1132"
.
(1.59 mm ±0.79 mml
from case for 10 s max. . . . . . . . . . • . . .
V
V
V
5
V
50
rnA
.. The collector of each transistor of the CA3026 is isolated from the
substrate by an integral diode. The substrate must be connected to a
voltage which is more negatille than any collector lIoltage in order to
maintain isolation between transistors and provide for normal
transistor action. The substrate should be maintained at signal rAe)
ground by means of a suitable grounding capacitor~ to alloid
undesired coupling between transistors.
·C
265
15
20
20
MAXIMUM VOLTAGE RATINGS
The following chart gives the range of voltages which can be applied to the terminals listed vertically with respect to the
terminals listed horizontally. For example, the voltage range between vertical terminal 1 and horizontal terminal 3 is
+15 to -5 volts.
Maximum
Current Ratings
CA302_
TERMINAL
No.
10 '
II
12
I
2
3
4
5
10
11
0
·20
12
I
2
. ·
..·
·
·
+5
·5
+20
0
3
+15
·5
+20
0
+20
0
+15
·5
+1
·5
4
5
6
7
8
Note 1
9
CA3026
TERMINAL
No.
liN
rnA
lOUT
rnA
· · ·· · ·
10
5
0.1
+20
0
11
50
0.1
+20
0
12
50
0.1
I
5
0.1
2
5
0.1
· · ··
· · ··
·. · · ·
. ·· ·· ··
·
··
0
·20
6
7
8
9
+5
·5
+20
0
·
·
· ·
· ·
··
·
·
·
·
3
0.1
·50
+15
·5
4
5
0.1
+20
0
5
50
0.1
+20
0
6
50
0.1
+15
·5
7
5
0.1
+1
'5
8
5
0.1
9
0.1
50
·
Ref
9
·Voltages are not normally applied between these terminals.
Voltages appearing between these terminals will be safe If the
specltled IImlu between all other terminals are not exceeded.
326
Substrate
Note 1: In the CA3026 terminal No.9 is connected to the emitter
of Q4. the reference substrate. and the case; therefore, should not be
grounded.
File No. 706 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA3026 Slash (II Series
ELECTRICAL CHARACTERISTICS at TA = 25°C
CH ARACTERISTIC.S
SYMBOLS
TEST CONDITIONS
CA3026
LIMITS
UNITS
TYP.
STATIC CHARACTERISTICS
For Each Differential Amplifier
Input Offset VO Itage
VIO
Input Offset Current
110
Input Bias Current
Quiescent Operating
Current Ratio
Temperature Coefficient
Magnitude of Input· Offset Voltage
For Each Transistor
IC(QsI
IC(Q2)
IC(Q6)
-or16
0.3
pA
10
pA'
IE(Q3t IE(Q4)= 2 rnA
0.98 to
1.02
-
1.1
I.N/oC
0.630
0.715
0.750
0.800
V
·1.9
mV:oC
0.002
nA
VIol
6T
t
\ IC = 50,lA
DC Forward Base·to·
Emiller Voltage
Temperature Coefficient of Base·
to·Emiller Voltage
Coliector·Cutoff Current
VBE
LWBE
--:lrf"
ICBO
mV
VCB = 3 V
II
Ic(QIl
0.45
VCB ,J V
1 rnA
3 rnA
10 rnA
VCB = 3 V, IC = 1 rnA
VCB
=
10 V, IE = a
Collector·to- Emi lIer
Breakdown Voltage
V(BR)CEO
IC
1 rnA, IB = 0
24
V
Collector·to-Base
Breakdown Voltage
V( BR)CBO
IC=10~,IE=0
60
V
Collector-to· Substrate
Breakdown Voltage
V( BR)CIO
IC
= 10~,
ICI = a
60
V
Emitter·to-Base Breakdown Voltage
V(BR)EBO
IE
= 10~,
IC = a
7
V
100
dB
75
dB
32
dB
105
dB
60
dB
=
DYNAMI'C CHARACTERISTICS
Common-Mode Reject,ion Ratio
For Each Amplifier
CMR
AGC Range, One Stage
AGC
Voltage Gain, Single Stage
Double-Ended Output
AGC Range, Two Stage
Voltage Gain, Two Stage
Double-Ended Output
A
AGC
A
VCC = 12 V
VEE = ·6 V
Vx = ·3.3 V
f = 1 kHz
327
CA3026.Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 706
ELECTRICAL CHARACTERISTICS at TA
-'
=25°C -
Cant'd.
CA3026
LIMITS
TEST CONDITIONS
SYMBOLS
CHARACTERISTIC,S
UNITS
TYP.
DYNAMIC CHARACTERISTICS (Cant'd.)
Low·Frequency, Small·Signal
Equivalenl·Circuit Characteristics:
(For Single Transistor)
Forward Current· Transfer Ratio
hIe
Short·Circuit Input Impedance
hie
Open·Circuit Output Impedance
hoe
f
Open·Circuit Reverse VoltageTransfer Ratio
l/f Noise Figure
(For Single Transistor)
hre
IC
NF
f = 1 kHz, VCE = 3 V
3.25
dB
fT
VCE.= 3 V, IC = 3 mA
550
MHz
Forward Transfer Admittance
Y?I
VCB = 3 V
Each Collector
IC;:'; 1.25 mA
f = 1 MHz
·20+jO
mmho
0.22+jO.l
mmho
O.OI+jO
mmho
·0.003 +jO
mmho
68·jO
mmho
0.55+jO
mmho
Gain·Bandwidth Product
(For Single Transistor)
110
=
1 kHz, VCE
=
=
3 V,
1 mA
3.5
kO
15.6
/-Lmho
l.8x 10. 4
Admittance Charactelistics;
Differential Circuit Configuration:
(For Each Amplifier)
Input Admittance
YI1
Output Admittance
Y22
Rever~e
Yl?
Transfer Admittance
Admittance Characteristics;
Cascode Circuit Configuration:
(For Each Amplifier)
Forward Transfer Admittance
Y?l
Input Admittance
Yll
Output Admittance
Y22
Reverse Transfer Admittance
Yl?
NF
Noise Figure
VCB = 3 V
Total Stage
IC:t 2.5 mA
f = 1 MHz
0+jO.02
mmho
0.004-jO.005
J1lDho
8
dB
f = 100 MHz
Table I. Pre Burn-In and Post Burn-In Electrical Tests and Delta Limits'"
CHARACTERISTIC
SYMBOL
Input Bias Current
For Each Transistor
01, 02, 05, and
as
Base·to-Emitter Voltage
For Each Transistor Q3 and Q4
Input Offset Voltage
For Each Differential Amplifier
-Levels I1N, 11R,/1. and /2 require pre
an~
TEST CONOITIONS
= 2mA
LIMITS
MIN.
MAX.
MAX./),
-
24
.S.O
0.8
.0.1
II
VeE = 3V, IE
VBE
VeE
=3V, IE = lmA
0.7
VIO
VeE
=3V, IE = 2mA
-
5
post burn-In electrical tests and delta limits.
Level/3 requires pre burn-in electrical test only. The burn-In and operating life test circuit Is shown on page 329.
328
.2
UNITS
~A
V
mV
CA3026 Slash
File No. 706
(II Series
Table II. Group A Electrical Sampling Inspection Tests and Final Electrical Tests
CHARACTERISTIC
TEST CONDITIONS
SYMBOL
LIMITS FOR INDICATED TEMPERATURES I·CI
MAXIMUM
MINIMUM
-55
+125
+25
+125
+25
UNITS
-55
For Each Transistor:
Collector Cutoff
ICBO
VCB = 10 V. IE = 0
-
-
-
0.1
Breakdown Voltage
VIBRICBO
IC = lO~A. IE= 0
-
20
-
-
Emitter-To-Base
Breakdown Voltage
VIBRIEBO
IE=10~A.IC=0
-
5
-
VIBRICIO
IC = lOll A. ICl = 0
-
20
VIBRICEO
IC= lmA.IB=O
-
15
II
VCE=3V,IE=2mA
-
II
VCE = 3 V, IE = 2mA
VCE = 3V,IE = lmA
Current
Collector To-Base
Collector-To-Substrate
Breakdown Voltage
Collector-To-Emitter
Breakdown Voltage
20
~A
-
-
V
-
-
-
V
-
-
-
V
-
-
-
-
.V
-
-
50
25
20
~A
-
-
-
50
25
20
~A
0.7
0.7
0.4
1.06
0.8
-
-
-
Input Bias Current
For Transistors 03
-
0.1
and Q4
Input Bias Current
For Transistors a 1,
02, OS, and 06
Base-To-Emitter Volt-
age For Transistors
03 and 04
VBE
0.75
V
-
~A
For Each Differential Amplifier
Input Offset Current
110
Input Offset Voltage
VIO
Table III., Group C Electical
2
VCE-3V,IE-2mA
I
VCE=3V,IE=2mA
-
5
I -
mV
Characteristics Sampling Tests ITA = 2S0C)
CHARACTERISTIC
SYMBOL
For Each Transistor:
Collector Cutoff Current
I nput Bias Current
For Transistors Q1, 02,
ICBO
TEST CONDITIONS
VCB = 10 V, Ie = 0
LIMITS
MIN.
-
II
VCE = 3 V, IE = 2mA
-
Base-to-Emitter Voltage
For Transistors Q3 and Q4
VBE
VCE"3V,IE=lmA
0.65
For Each Differential Amplifier:
Input Offset Voltage
VIO
VCE = 3 V, IE = 2mA
-
as, & 06
MAX.
UNITS
0.2
I'A
28
~A
0.85
V
6
mV
50n
Y-·-t.6 Y
92CS-22937
Burn-in and operating life test circuit.
329
CA3026 Slash (I) Series
File No. 706
COLLECTOR-lO-BASE VOLTS (Vea). '3
COLLECTOR -10- BASE YOLTSIVCeJ. 3
ulLLIAMPEIIES \lE'·\o.
~
EMITTEII
0..9
w
,:>
;;; OB
~
g
~
.'"
g
o
> 0.1
~
~Q.6
~
0.75
~ 0.50
0.2.
0.5
0.'
-75
-50
-25
0
o
2~
50
75
AMBIENT TEMPERATURE CTA)--C
100
125
~75
transistor VI ambient temperature.
•4
'0
H
!:!
-25
25
50
75
100
AMBIENT TEMPERATURE 11A)--<:
Fig. 3 _ Offset voltage charBCteristic
ture for differential pain.
Fig. 2 - Bass·to-emlrter voltage characrer;st;c for each
10.. COLLECTOR-TO-BASE VOLTS
. -50
92CS-ISI86RI
125
92CS-ISI88RI
VS' ambient
tempera-
IVesl-'
AMBIENT TEMPERATURE (TA)-25-C
2
::J0:
1/
I
~
:0
g
~
.
§.
i
~
•
4•
2
./
0.1
••
4l--"""
z
H
c;;
2
0.01
0.01
4
6 8 0 .1
4
6
8 I
COLLECTOR MILLIAMPERES (Ie)
4
6 8 ,0
92CS-I!l216RI
DC BIAS VOLTS ON TERMINAL 8
92CS-15254RI
Fig. 4-lnput offset current for matched differential
pairs VB collector current.
Fig. 5 - Singltrstage voltage gain
100 COLLECTOR-TO-BASEVOLTS IVCB1·3
6 FREQUENCY (f)al kHz
4 AMBIENT TEMPERATURE(TAI-2SoC
I
2~
10f-.-
••
t--...
-
4
2
--
I~""
'"
-
V
1/
1"'""
-~
K4,
I--'
N
....
4
6 8 0 .1
4
6
a
I
COLLECTOR MILLIAMPERES (ICI
DC BIAS VOLTS ON TERMINALS 2 AND 8
Fig. 6 - Two-stage voltags gain.
330
92CS-I$Z5SRI
'oe
7
~
0.1
0.01
II
hre =1.88K 10-4 of IrnA
hoe -15.Ei ,..mho
I
••
I II
hie- 3.S J asoe derate linearly . • • • . . . • • . . . • . . . . . . • • . . . . • . . . . . . • . . 5 mwrC
AMBIENT TEMPERATURE RANGE:
Operating . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to +12SoC
Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . -65 to +l50°C
LEAD TEMPERATURE (During Soldering):
At distanca1l1S" .1132"
(1.59 mm .0.79 mm)
from case for 105 max. . . . . • • • . . • • . . . • . • . . . . . . . . . • . . . • . . . • . . • 265°C
MAXIMUM
CURRENT RATINGS
MAXIMUM VOL TAGE RATINGS at T A = 2S DC
TERMINAL
No.
1
1
2
o.
to
-15
2
3
a
4
S
a
+5
-15
+5
-15
+5
to
to
-5
+15
to
-11
3+
to
-1
+10
to
0
4
to
to
0
·+15·
6
7
*
*
•
+15
8
+20
to
+30.
to
0
*
0
+15
+30
to
to
to
to
0
+15
0
0
0
•
*
•
.*
*
*
*
to
0
+2011>
S
to
0
6
7
This chart gives the range
of voltages which can be applied
to Ihe terminals listed horizontally
with respect to the terminals
listed vertically. For example,
the voltage range of the horizontal
terminal 4 with respect to tenninal
2 is -1 to ¥.i volts.
+strate and case.
Terminal #3 Is connected to the sub·
* Voltages
are not normally applied between these terminals. Voltages
•
appearing between these terminals
will be safe, if the specified volt~
age limits between all othe, termi·
nals are not exceeded.
Limit is +24V
*
8
ELECTRICAL CHARACTERISTICS at TA = 25°C '.
-
CHARACTERISTIC
SVMBOL
TEST CONDITIONS
LIMITS
UNITS
TYP.
STATIC CHARACTERIST,ICS
v+
V-
VIO
6V
12 V
6V
12 V
110
6V
12V
6V
12V
II
6.V
12 V
6V
12 V
16.6
36
p.A
16 or 18
6V
12 V
6V
12 V
1.25
3.3
mA
Input Current
(Terminal No.7)
17
6V
12V
6V
12V
0.85
Device Dissipation
PT
6V
12V
6V
12 V
36
175
Input Offset Voltage
Input Offset Current
Input Bias Current
Quiescent Operating
Current
332
0.98
0.89
0.56
1.06
1.65
mV
p.A
mA
mW
TERMINAL
No.
lIN
mA
lOUT
mA
1
0.6
0.1
2
4
0.1
3
0.1
23
4
20
0.1
5
0.6
0.1
6
20
0.1
7
4
0.1
8
20
0.1
File No. 711 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA3028B Slash (I) Series Type
ELECTRICAL CHARACTERISTICS AT TA = 25"C - Cont'd.
CHARACTER ISTIC
TEST
WMBOL
CONDITIONS
LIMITS
I
Typ.
OYNAMIC CHARACTERISTICS
1= 100 MHz
Power Gain
Noise Figure
Input Admittance
Reverse Transler
Admittance
Forward Transler
Admittance
Gp
NF
Cascode
20
I VCC = +9V
I - 10.7 MHz
Dil'.·Ampl.
Cascode
17
39
VCC = +9V
I - 100 MHz
Dil'.·Ampl.
Cascode
32
7.2
VCC = +9V
Dil'.·Ampl.
6.7
i
Y11
YI2
Y 21
Output
Admittance
Y22
Power Output
(Untunedl
Po
Cascode
0.6 + j 1.6
Dil'.·Ampl.
0.5 + j 0.5
Cascode
0.0003· jO
UNIT
J
1= 10.7 MHz
Dill.·Ampl. 0.01 . jO.0002
VCC = +9V
Cascode
1= 10.7 MHz
99· jiB
Diff.·Ampl.
·37 + jO.5
Cascode
O. + jO.OB
Dilf.·Ampl.
0.04 + jO.23
~J'h·~nm:.,lt.
5.7
Outout
dB
dB
dB
mmho
mmho
mmho
mmho
uW
AGC Range
(~~'F~I~wd'~t~,~\n
AGC
at
1= 10.7 MHz
VCC = +9V
Diff.·Ampl.
62
1= 10.7 MHz
Cascode
40
VCC = +OV
Diff.·Ampl.
30
dB
dB
RL=lkil
Voltage
.Gain
A
CC = <£V,
Differential
at
I = I kHz
~L = 2 kO
VEE = '6V,
38
dB
~CC
= +12V,
~CC
= <£V,
VEE = ·12V
~L = 1.6 kO
Max. Peak·to·Peak
Output Voltage
at I = I kHz
Vo(P'P)
~L = 2 kO
~CC = +12V,
~~
11.5
BW
WCC = +12V,
V CMR
Common-Mode
Rejection Rati 0
eMR
Input Impedance
at I = 1 kHz
ZIN
Peak-to-Peak
Output
Current
Ip_p
Vp_p
VEE = -12V
23
VEE = ·6V,
7.3
RL = 2 kO
~L
Common-Mode
Input-Voltage Range
VEE = '6V,
= 1.6 kO
WCC = +6V,
Bandwidth
at -3 dB point
42.5
MHz
VEE = ·12V
8
= 1.6 kO
WCC = <£V,
WCC = +12V,
VEE = ·6V
(-3.2 - 4.5)
VEE = ·12V
(-7 - 9)
Vee = <£V,
VEE = ·6V
110
Vee = +12V,
VEE = -12V
90
Vee. = <£V,
VEE = -6V
5.5
Vee = +12V,
VEE = -12V
3
V
dB
kO
Vee = +9V
1= 10.7 MHz
4
!vee = +12V
ein = 400mV
Dill.-Ampl.
6
rnA
333
CA3028B Slash (/) Series Type _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _,File No. 711
TABLE I. GROUP A ELECTRICAL SAMPLING INSPECTION
limits for Indicated Temp. (oC)
Test Conditions
Character Istles
ymbol
VCC
VEE
-55
+25
Units
Maximum
Minimum
+125 -55
+25 +125
Stat,c
Input Offset
Voltage
VIO
Input Offset
Current
110
Input Bias
Current
Quiescent Oper.
Current
Input Current
(terminal 7)
Device
Di ssipation
+6
·6
+ 12
-12
- - - - - -
-
- -
+6
-6
+ 12
-12
+6
-6
+ 12
-12
16
or
+6
-6
0.5
1.0
18
+ 12
-12
2.0
2.5
+6
-6
+ 12
-12
II
7
5
7.5
5
5
6
10
5
7.5
12
6
9
70
40
35
130
80
55
0.5
2.0
1.5
2.0
1.5
4.5
4.0
4.0
0.5
0.5 0.35 1.5 1.0
1.2
1.0
1.0 0.75 2.5
2.1
2.0
20
42
flA
flA
mA
mA
17
PT
mV
1-
+6
-6
20
24
+ 12
-12
120
120 105 230 220 210
45
45
mW
Dynamic
=+ 9V
~ Cascode
=10.7 MHz
Dlff-Ampl
V CC
f
Power Gain
Gp
V ce
f
Noise Figure
NF
= + 9V ~
=100 MHz
=100 MHz
Vce VEE
A
Diff-Ampl
VCC " + 9V ~ Cascode
f
Voltage Gain
(Differential)
Cascode
+6
Diff-Ampl
Freq.
kHz
-6
1
+ 12
Max. Peak-toPeak Output
Voltage
VO(p.p
Common-Mode
Input-Voltage
Range
VCMR
Common-Mode
Rejection Ratio
CMRR
334
-12
+6
-6
+ 12
-12
+6
-6
+ 12
-12
+6
-6
+ 12
-12
35
28
dB
16
14
9
dB
9
RL
kIt
2
1.6
1
- - - - - - - - - - - - - - - - - - -
2
1.6
_.
-
-
35
40
·7
15
-2.5
to+ 4
to -5
+
60
60
- -
42
-
- - - - - - - - - - - - - -
-
dB
45
"(P-P)
V
dB
File No. 711 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA3028B Slash (f) Series Type
Table II. PRE BURN·IN ELECTRICAL AND POST BURN·IN ELECTRICAL TESTS,
AND DELTA LIMITS'
CHARACTERISTIC
SYMBOL
Input Bias Currenl
Input Offset Voltage
Quiescenl Oper. Current
Input Current (term. 7)
Device Dissipation
TEST CONDITIONS
LIMITS
Max.
Maxll
Min.
UNITS
II
80
!8
/J A
VIO
5
,2
mV
16 or 18
2.5
4
,0.4
mA
h
1.0
2.1
,0.2
mA
PT
120
220
• 24
mW
• Levels /1 and /2 roqu ire pro burn·!n electrical and post burn-in electrical tests, and delta limits.
Level /3 requires pro burn-In electrical test only. Tho burn-In and operating lifo test circuit is shown In Fig. 2.
Table III. FINAL ELECTRICAL TESTS
SYM·
BOLS
CHARACTERISTICS
I
TEST CONDITIONS
v+
v'
VIO
+6
+ 11
·6
·11
110
+6
+ 11
·6
·12
II
+6
+ 12
·6
·11
I
or 16
+6
+ 12
·6
·12
t6
tl2
t6
+12
·6
·12
I
LIMITS FOR INDICATED TEMPERATURE (oC)
Minimum
Maximum
I UNITS
+125 I :55
·55
+25
+25
+125
I
STATIC
Inpul Offset
Voltage
Inpul Offsel
Current
Input Bias
Current
Quiescenl Oper.
Current
Inpul Currenl
(lerminal7)
Device
17
PT
Dissipation
·6
·12
2.0
I
2.5
1.0
0.5
1.0
110
24
110
1.5
0.75
5
5
5
6
mV
12
5
6
9
IJA
130
40
80
55
I'A
4.5
1.5
4.0
4.0
mA
2.5
1.0
2.1
2.0
rnA
210
mW
42
105
130
220
DYNAMIC
Gp
Power Ga in
Noise Figure
Voltage Gain
(Dilf.)
VCC = +9V. f = 10.7 MHz
Dilf.·Ampl. Config.
28
dB
VCC = +9V, 1= 100 MHz
Cascade Ampl. Conllg.
16
dB
NF
VCC = +9V, I = 100 MHz
Cascade Ampl. Conlig.
A
VCC = +12V. I = I kHz
RL = 1.6 k"
40
9
dB
45
dB
Table IV. GROUP C ELECTRICAL CHARACTERISTICS SAMPLING TESTS ITA = 2SoC, V+ = + 12V, V· = ·12V)
CHARACTERISTIC
Input Offset Voltage
Input Bias Current
Quiesce~t
SYMBOL
TEST CONDITIONS
LIMITS
Min.
Max.
UNITS
VIO
5
mV
II
80
pA
mA
16 or 18
2.5
4.0
17
1.0
2.1
rnA
Device Dissipation
PT
120
220
mW
Power Gain
Gp
Oper. Current
Input Current (term. 7)
VCC = +9V, I = 10.7 MHz
DiIL·Ampl. Config.
28
dB
335
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - -_ _ File No. 704
oornLJD
Solid State
Division
Linear Integrated Circuits
Monolithic Silicon
High-Reliability Slash(/) Series
CA3039/...
High-Reliability
Diode Array
Six Ultra - Fast Low
Capacitance Matched Diodes
For Applications in Communications and Switching Systems of
Aerospace, Military and Critical Industrial Equipment
H-1463
12·Lead TO·5 Style Package
RCA·CA3039 "Slash" (I) Series type is a high·reliability
I inear integrated circuit Diode Array intended for
applications in aerospace, military. and industrial equipment.
It is electrically and mechanically identical with the stan<;lard
type CA3039 described in Data Bulletin File No. 343 but is
specially processed and tested to meet the electrical,
mechanical and environmental test methods and procedures
established for microelectronic devices in MIL·STD·883.
The packaged types can be supplied to six screening levels11N,/1R.ll.12./3, and 14-which correspond to MIL-STD-883
Classes A, B, and C. The chip version can be supplied to three
screening levels-1M. IN, and IR. These screening levels and
detailed information on test methods, procedures, and test
sequence are given in Reliability Report Ric·202A "High·
Reliability CA3000 Slash (I) Series Types Screened to MIL·
STD·883."
Features:
• Excellent reverse recovery time - 1 ns typo
• Matched monolithic construction VF matched within 5 m V
•
Low diode capacitance Co = 0.65 pF typical at VR = - 2 V
Applications:
• Balanced modulators or demodulators
• Ring modulators
• High speed diode gates
• Analog switches
The CA3039 Slash (I) Series type is supplied in the 12·lead
TO·5 style package ("T" suffix) or in chip form ("H" suffix).
~ ~ J;-:~l
~
Os
SUBSTRATE
AND CASE
92C$-1:5262
Fig. 1 - Schematic Diagram
336
9·74
File No. 7 0 4 - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ CA3039 Slash (I) Series
ABSOLUTE MAXIMUM RATINGS at TA = 25°C
DISSIPATION:
mW
Peak Inverse Voltage, PIV for: 0,-05 . . . . . .
SV
Total for device. . . . . . . . . . . . . . . . .. 600
mW
For T A
55 C c .... " .. . derate linearly 5.7 rnwtc
TEMPERATURE RANGE
Operating
. . . . . . . . . . • • • . • .. .55 to + 125°C
Storage . . . . . . . . . . . . . • . • . . • -65 to + 150°C
Anyone diod,e unit
.............•
100
Os •....•••
O.S V
Peak Diode-to-Substrate Voltage, VOl
for °,,0 5 (term. 1,4,5,8 or 12 to term. 101
+20, - 1 V
DC Forward Current, IF' . . . . . . . . . . . . .
Peak Recurrent Forward Current, If
...•..
Peak Forward Surge Current, If (surge). . . . ..
25
100
100
>
LEAD TEMPERATURE (During Soldering): At distance 1/6" ± 1/32" (1.59 mm ±O.79 mm) from case for 10 s max.........
rnA
rnA
rnA
265 0 C
ELECTRICAL CHARACTERISTICS, at TA = 25° C
Characteristics apply for each diode unit, unless otherwise specified.
LIMITS
CHARACTERISTICS
SYMBOLS
TEST CONDITIONS
UNITS
TYP.
VF
IF = 50j.LA
1 rnA
3 rnA
10 rnA
0.65
0.73
0.76
0.81
V
V
V
V
DC Reverse Breakdown Voltage
V(BR)R
IR = 40llA
7
V
DC Reverse Breakdown Voltage
Between any Diode Unit and Substrate
V(BR)R
IR=-10j.LA
-
V
DC Reverse (Leakage) Current
IR
VR = -4 V
0.016
nA
DC Reverse (Leakage) Current
Between any Diode Unit and Substrate
IR
VR = -10 V
0.022
nA
IF = 1 rnA
0.5
mV
IF = 1 rnA
1
j.LV/oC
--
IF = 1 rnA
-1.9
mV;oC
DC Forward Voltage Drop for
Anode-ta-Substrate Diode (DS)
VF
IF = 1 rnA
0.65
V
Reverse Recovery Time
trr
IF
1
ns
Diode Resistance
RD
f = 1 kHz, IF = 1 mA
30
11
Diode Capacitance
CD
VR = -2 V, IF = 0
0.65
pF
VOl
3.2
pF
DC Forward Voltage Drop
Magnitude of Diode Offset Voltage
(Difference in DC Forward Voltage
Drops of any Two Diode Units)
I
Temperature Coefficient of VFl - VF21
Temperature Coefficient of Forward Drop
! VFl - VF2!
61VFl - VF21
6T
6 VF
6T
Di ode-to-Substrate Capacitance
COl
=
10 rnA, IR = 10 rnA
=
+4 V, IF = 0
337
CA3039 Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 704
Table I - Pre Burn-In and Post Burn4n Electrical Tests and Deltll Limits-
CHARACTERISTIC
Each Diode
DC Forward Voltage Drop
SYMBOL
TEST CONDITIONS
ATTA-25°C
MIN.
VF
IF=3rnA
0.69
LIMITS
MAX.
UNITS
MAX. A
.0.010
0.81
V
• Levels 11 N, /1 R. 11, and 12 require pre and POlt burn-In electrical tests and delta limIts
Level/3 requires pre burn-In electrical test only. The burn-In and operating life tast circuit II shown In Fig. 7.
Table 1/- Final Electrical Tests and Group A Electrical Sampling Inspection
SYMBOL
CHARACTERISTIC
LIMITS FOR INDICATED TEMPERATURES (OCI
MAXIMUM
MINIMUM
+25
+125
+125
-55
-55
+25
TEST CONDITIONS
UNITS
Each Diode:
OC Forward Voltage Orop
VF
IF = 3 rnA
0.82
0.69
0.47
1.0
0.86
0.63
V
IR
VR --4V
-
-
-
-
100
-
nA
V(BRIR
IR=40"A
-
5
-
-
-
-
V
IVFl -VF21
IF=1 rnA
-50 V through a 25 kn reo
sistor to terminal 10. Ground
terminals 1 through 9, 11 and
DC Reverse Leakage Current
DC Reverse Breakdown Voltage
Between Any Two
Diodes:
Dlod. Offset Voltage
Breakdown Voltage
Isolation-to-5ubS'b'ate
12. Measure voltage at termi-
-
-
-
-
8
-
rnV
-
-
-
-25
-25
-25
V
nall0.
Table 1//.- GrDup C Electrical Characteristics Sampling Tests iTA
CHARACTERISTIC
Each Diod.:
DC Forward Voltag. Drop
DC Reverse Leakage Current
DC Reverse Breakdown Voltage
Between Any Two Diodes!
Diode Offset Voltage
338
a
2ft C)
SYMBOL
.TEST CONDITIONS
VF
IR
IF-3rnA
VR =-4V
0.69
V(BRIR
IR -40"A
IVF1- V F21
IF=1 rnA
MIN.
LIMITS
MAX.
UNITS
0.81
100
V
nA
5
-
V
-
8
rnV
-
File No. 704 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
AMBIENT TEMPERATURE ITA)-2S-C
II
0.0
""''"
~
g
~
""
l
i
,
O.le
-
~
iQ
~
cr 0.01
"
"
,
0.001
-75
6 8 I
-50
DC FORWARD MILLIAMPERES (IF'
-25
./
25
50
75
100
92CS-I~66
Fig. 3 - DC reverse (leakage) c~~rrent (diodos 1,2,3,4,5) vs temperature.
FIg. 2 - DC forward voltage drop (any diode) and diode
offset voltage Vof DC forward current
,UU,
DC REVERSE VOLTAGE (VRI--IOV
4
/
2
~
i
i
/
10
4
/
2
I
4
z
/
2
!
125
AMBIENT TEMPERATURE {TAI--e
92C5-15268
::IE
0.1
~
4
~o.s
2
4
.
2
-
~
./
"QaDI
0.001
0.6
'" -
50
.
-
0.1
0 0 .4
.0
AMBIENT TEMPERATURE {TAl-tiC
'"
100
125
-75
-so
-250~5075
100
125
AMBIENT TEMPERATURE ITAI- ·C
92CS-I:i26S
Fig. 4 - DC reverse (leakage) current between diodes (1 ~,3.4,5) and
substrate vs temperature.
92CS-I~269
Fig. 5 - Diode offset voltage (any diode) vs temperature.
FREQUENCY {fl-lkHz
001
4
6
801
4
6
8 I
DC FORWARD MILLIAMPERES IIFI
Fig. 6 - Diode resistance (any diode) vs DC forward current
92C5-22936
Fig. 7 - Burn·in and operating life test circuit.
339
File No. 710
Linear Integrated Circuits
0008.DD
Solid State
Monolithic Silicon
High-Reliability Slash(/) Series
CA3045/•.•
Division
High-Reliability
General-Purpose Transistor Array
:'''~~.jOI.··I''·
. ..
\
'J
'-
~'
I
"
.. I
J
Three Isolated Transistors and One Differentially·Connected Transistor
Pair
For Low·Power Applications at Frequencies Through the VHF Range
In Aerospace, Military, and Critical Industrial Equipment
Features:
14-Lead Dual In-Line
Ceramic Package
• Two matcheil pairs of transistors
VBE matched ±5 mV
Input offset current 2 p.A max. at IC = 1 mA
• 5 general purpose monolithic transistors
RCA-CA-3045 "Slash" (I) Series type is a high-reliability
linear integrated circuit general-purpose transistor array
intended for applications in aerospace, military, and industrial equipment. It is electrically and mechanically identical
with the standard type CA3045 described in Data Bulletin
File No. 341 but is specially processed and tested to meet the
electrical, mechanical and environmental test methods and
procedures established for microelectronic devices in MILSTD·883.
The packaged types can be supplied to six screening levels11N,I1R,Il,12, 13, and 14-which correspond to MIL-STD-883
Classes A, B, and C. The chip version can be supplied to three
screening levels-1M, IN, and IR. These screening levels and
detailed information on test methods, procedures, and test
sequence are given in Reliability Report Ric-202A "HighReliability CA3000 Slash (I) Series Types Screened to MI LSTD-883."
The CA3045 Slash (I) Series type is supplied in the 14-lead
dual-in-line ceramic package ("D" suffix) or in chip form
("H" suffix).
•
•
•
•
Operation from DC to 120 MHz
Wide operating current range
Low noise figure - 3.2 dB typ. at 1 kHz
Full military temperature range for CA3045
-55 to +125°C
Applications:
• General use in all types of signal processing systems
operating anywhere in the frequency range from
DC to VHF
• Custom designed differential amplifiers
• Temperature compensated amplifiers
• See RCA Application Note, ICAN-52!!6 "Application
of the RCA-CA3018Integrated-Circuit Transistor
Array" for suggested applications.
4frlrlrl
3
6
7
9
10
12
13
SUB-
STRATE
Fig. 1 - Schematic diagram..
9-74
340
File No. 710 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA3045 Slash (I) Series
ABSOLUTE MAXIMUM.RATINGS AT TA';' 25°C:
EACH
TRANSISTOR
TOTAL
PACKAGF
POWER DISSIPATION:
AtTAupto7SoC
M~>.C
................. .
300
750
Derate at 8 mwtc
..................... .
V
15
20
20
5
50
Collector-ta-Emitter Voltage, VCEO . . . . . . . . . .
Collector-ta-Base Voltage, VCBO . . . . . . . . . . . .
Collector-to-Substrate Voltage, Velo· ....... .
Emitter-ta-Base Voltage, Veeo ............ .
Collector Current, Ie ................. .
mW
V
V
V
mA
TEMPERATURE RANGE:
Operating
·C
·C
·55 to +125
-65 to +150
....................... .
Storage . • . • • . • • . . • • • • • • • • • • • . . . • •
LEAD TEMPERATURE (During Soldering):
At distance 1/16" ± 1/32" (1.59 mrn ±o.79 mm) from case for 105 max...... .... ..
26So C
·The collector of each transistor of the CA3045 is isolated from the substrate by an integral
diode,
The substrate (terminal 13) must be connected to the most negative point in the
external circuit to maintain isolation betvveen transistors and to provide for normal transistor
action.
ELECTRICAL CHARACTERISTICS, at TA = 25°C
LIMITS
CHARACTERISTICS
SYMBOLS
SPECIAL TEST CON DlTIONS
Type CA3045 UNITS
TYP.
CHARAC- .
TERISTIC
CURVES
FIG.
STATIC CHARACTERISTICS
Colleclor-to-Base Breakdown Voltage
V(BR)CBO
'C ·1Oj1A, IF =0
60
V
Coliector·to·Emitter Breakdown Voltage
VIRR1r.m
'C = I rnA, 'B = 0
24
V
Coliector·to·Substrate Breakdown Voltage
V(BR)CIO
'C = 10j1A, 'C' = 0
60
V
Emitter,to-Base Breakdown Voltage
V(BR1EBO
'E = 10JiA, 'c = 0
VCB = 10 V, IE = 0
7
V
0.002
nA
2
VCE = 10 V, 'B = 0
See curve
JiA
3
Collector-Cutoff CUrient
Collector·Cutoff CUrient
'CBO
ICED
Static Forward Current-Transfel Ratio
(Static Beta)
hFE
\ 'C = 10 mA
VCE = 3 V) 'C = I rnA
Ic = 10 /lA
100
100
54
VCE = 3 V, 'C = I mA
0.3
JiA
5
V = 3 V{'E = I rnA
CE
'E = 10 mA
0.715
0.800
V
6
Magnitude of Input Offset Voltage for Diffelentia I Pair IVBE I - VBE21
VCE
3 V, Ic = I mA
0.45
mV
6,8
Magnitude of Input Offset Voltage for Isolated Transistors IVBE3' VBE4 1,
I VBE4 . VBE51, I VBE5 . VBE31
VCE = 3 V, 'C = I rnA
0.45
mV
6,8
mVIC
7
Input Offset CUrient fOI Matched Pair
QI and Q2' 11101 -11021
Base·to·Emitter Voltage
Temperature Coefficient of
Base-to·Emitter Voltage
Coliector-to·Emitter Saturation Voltage
Temperature Coefficient:
Magnitude of Input-Offset Voltage
VBE
6V BE
L\T
Vr.F~
16 V,O I
t.T
=
4
3 V, 'C " I mA
, -1.9
'B = I rnA, Ir. = 10 mA
0.23
V
VCE = 3 V, 'C = I rnA
1.1
/lvlc
VCE
=
8
341
CA3045 Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 710
ELECTRICAL CHARACTERISTICS (Cont'd)
CHARACTERISTICS
SYMBOLS
LIMITS
Type CA3045 UNITS
SPECIAL TEST CONDITIONS
CHARAC'
TERISTIC
CURVES
~
TYP.
DYNAMIC CHARACTERISTICS
low-Frequency Noise Figure
NF
~o:r~:~~s~~a~c: 3.~, J\,IOO/.A
3.25
dB
hi
hie
hoe
1
I· I kHz, VCE ·3 V, IC • I rnA
llO
3.5
15.6
ill
,..,ho
101b'
Low·Frequency, Sma"·Signal
Equivalent-Circuit Characteristics:
FOlWard Cunent-Transfer Ratio
Shorl·Circuil Input Impedance
Open·Circuil Oulpul Impedance
Open-Circuit Reverse
I
hre
Voltage·Transler Ralio
Admittance Characteristics:
FOfward Transfer Admittance
I
Y'e
Yi
Yoe
'npul Admillance
Oulpul Admillance
Reverse Transfer Admittance
' • 1 MHz, VCE • 3 V, IC ·1 rnA
I
Y"
'T
CEB
CCB
CCI
Gain·Bandwidlh Product
E!'Iitter-to-Base Capacitance
Co"ecIOT·lo·Base Capacilance
Colleclor·lo·Subslrale Capac ilance
11
1.8xlO·4
31·j1.5
0.3
Max.
±0.5
5
= lOV, IB =0
Units
V
0.5
±0,l5
/lA
5
25
±3
/lA
0.6
0,8
±Q,lO
V
• Levels 11 and /2 require pre burn-In electrlcal and post burn-In electrical tests, and delta limits.
Level 3 requires pre burn-In test only. The burn-In and operating life test circuit Is shown in Fig. 6.
0,8 COLLECTOR-TO-EMITTER VOLTStvCE1.3
AMBIENT TEMPERATURE (,TA1.2S·C
W
~
V
0.7
~
'"
!J
g
~
3
/"
2
:i
~
~ a.•
. . ,...v
ill
~
~T OFFSET VOLTAGE
0.'
O. I
2
4
I eo.I
6
l
EMITTER
UILLIAMPERES \'LEl- IO
m
g
j
...
~
to;
/
I
0-
~
~ 0.15
:::to;
I-
~
0.50
0.1
025
0
2
4
6 , I
2
EMITTER "'ILLIA~P£RES(IE I
4
6
e 10
92CS-15217
Fig. 2- Typical static ba8lHo-emitter vol;ie characteristic
and input ofhet voltage for differential pair and
paired isolated transistors vs emitter current
342
~
'"
!J
II
/"
a.•
COLLECTOR-lO-EMITTER VOLTS !VCE)-3
Vi-'
-75
-50
-25
25
50
75
AMBIENT TEMPERATURE (TA)---C
100
It'
92CS-1521e
Fig. 3- Typical input offset voltage characteristics for
differential pair and paired isolated transistors
vs ambient temperature.
File No. 710 - - - - - - - - - - - - - - - - - - - - - - - C A 3 0 4 5 Slash (I) Series
Table 11.- Final Electrical Tests (For each transistor unless otherwise indicated}
Characteristics
Symbol
Test Cond itions
Limits For Indicated Temperature (oC)
Minimum
Maximum
T
-55
-55
+25
+125
+25
+125
I
I Units
STATIC
Collector-to-Base
Breakdown Voltage
V(BR)CBO
IC = 101lA, IE = 0
20
V
Collector-to-Em itter
Breakdown Voltage
V(BR)CEO
IC = ImA, IB = 0
15
V
Collector-to-Substrate
Breakdown Voltage
V(BR)CIO
IC = IOIlA, ICI = 0
20
V
Emitter-to-Base
Breakdown Voltage
V(BR)EBO
IE = 101lA, IC = 0
(Except Q5)
5
V
Collector-Cutoff
Current
ICBO
VCB = 10V, IE = 0
40
Collector-Cutoff
Current
ICED
VCE = 10V, IB = 0
0.5
Static Forward
Current-Transfer
Ratio
hFE
fC = lOrnA
VCE = 3V IC = ImA
IC = lallA
Input Offset
Current for
Differential Pair
1110 1110 2 1
VCE = 3V, IC = ImA
Base-to-Emitter
Voltage
VBE
V = 3{IC = lOrnA
CE
IC = ImA
Input Offset
Voltage for
Differential Pair
IV BEI VBEZ I
30
40
15
18
45
-
VIO
VCE=3V,I C = ImA
Co Ilector -to-Emitter
Saturation Voltage
VCES
IB = ImA, IC = lOrnA
100
IlA
-
2
0.7
0.6
0.4
IlA
1.0
0.8
1.0
V
0.7
5
mV
5
mV
0.5
V
VCE=3V,I C = ImA
Input Offset
Voltage for
Isolated Transistors
nA
-
100 COLLECTOR-lO-EMITTER VOLTS fVCE):3
6 FREQUENCY (I) =1 kHZ'
4 AMBIENT TEMPERATURE (TA)E25°C
I
COllECTOR-lO-EMITTER VOLTS IVCEI-3
AMBlE NT TEMPERATURE ITA)-2S-C
' F r--.....
~ •
l!
Ii
10
"
-
~
I
~
~
~
000
~
;)
~
15z·
500
6
,
-
,
-
0.01
.lL./
I-
/
, ,
""
l'I oe :15.6,..mho
I
OIV
II
}
~
I'......
.
I II
hie=3.5K.n
hre=I.BSltlo-4 ollrnA
,
,
,
1
",,'"0
.... 1»
/
0.1
",~.::
['..:··h.
N,
~
.
V
,
,
6 •
I
,
, ,
COLLECTOR MILLIAMPERES IIel
.
10
92CS-t5190
Fig. 5 - Typical normalized forward current-transfer
COLLECTOR MILLIAMPERES (Ie)
92CS-li5196
Fig. 4 - Typical gain-bandwidth product vs collector
current.
ratio, short-circuit input impedance, open·
circuit output impedance, and open-circuit
reverse voltage-transfer ratio V$ col/ector
current.
343
CA3045 Slash (I) Series _ _ _ _ _ _ _ _ _--'-_ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 710
Table 111.- .Group A Electrical Sampling Inspection
Symbol
Characteristics
Limits for Indicated Temperature (DC)
Minimum
Maximum
I
Test Conditions
·55
+25
+125
·55
+25
Units
+125
STATIC
Collector-ta-Base Breakdown Voltage
V(BR)CBO
IC : 10,L'A, IE : a
20
v
Collector-ta-Emitter Breakdown Voltage
V(BR)CEO
IC: ImA,l B :0
15
V
Collector-ta-Substrate Breakdown Voltage
20
V
V(BR)CIO
IC : 10!,A, ICI : a
Emitter-ta-Base Breakdown Voltage
V(BR)EBO
IE : 10!,A, IC : a (Except Q5)
Collector-Cutoff Current
ICBO
VCB : 10V, IE : a
Collector-Cutoff Current
ICEO
V CE : 10V, IB : a
Static Forward Cunent -Transfer Ratio
VCE:3
hFE
5
0.5
r'~'
18
IC: ImA
VBE
100
I·A
45
200
-
2
I·A
15
0.7
0.6
0.4
1.0
0.8
0.70
V
VCE : 3V, IC : 10m A
1.0
V
lmA
5
mV
1 VCE : 3V, IC :
Input Offset Voltage for Differential Pair, (Ql' Q21 !veE ' VBE
I
2
Input Offset Voltage for Isolated Transistors
40
VeE: 3V,IC: ImA
VCE : 3V, IC : ImA
Base-ta-Emitter Voltage
nA
30
IC: 10!,A
Input Offset dunent for pifferentlal Pair. (Q1' Q2l PIO ·110 \
2
I
V
40
IQ3' Q4\' \Q4 • Q51 ,I Q5' Q31
Via
VCE : 3V, IC : ImA
5
mV
Collector-ta-Emitter Saturation Voltage
VCES
IB : ImA, IC : 10mA
0.5
V
IT
VCE : 3V, IC : 3m A, I : 100 MHz
DYNAMIC
Gain-Bandwidth P,Dduct (Q3)
300
MHz
Table IV - Group C Electrical Characteristics Sampling Tests
(TA=2!t'C, VCC~+6V, VEE=-6VI
Limits
Characteristic
Symbol
Test Condi tions
Emitter·to·Base
Breakdown Voltage
V(BR)EBO
IE = 10 /LA
IC =0
(Except Q5)
5
V
Collector·to·Em iller
Breakdown Voltage
V(BR)CEO
IC -1 rnA
IB = 0
15
V
Min.
Coliector·Cutoff
Current
ICEO
VCE -10 V
IB =0
Input Current
-II
VCE - 3 V
IC = 1 rnA
5
VCE - 3 V
IC = 1 rnA
0.6
Base·to·Emiller
Voltage
344
VBE
Max.
Units
0.5
/LA
25
/LA
+6V
520n
L-__
0.8
V
~~
____
5200.
~
-6V
HC5·15823
Fig. 6 - Burn-in and operating life
test circuit.
File No. 707
OO(]5LJ[]
Linear Integrated Circuits
Monolithic Silicon
Solid State
Division
High-Reliability Slash(l) Series
CA3049/ . ..
High-Reliability
Dual High-Frequency
Differential Amplifier
For Low·Power Applications at Frequencies up to 500 MHz in
Aerospace, Military and Critical Industrial Equipment
Features:
12·Lead TO-5 Style Package
• Power Gain 23 dB (typ.) at 200 MHz
a Noise Figure 4.6 dB (typ.) at 200 MHz
EI Two differential amplifiers on a common substrate
• Independently accessible inputs and outputs
RCA·CA3049 "Slash" (I) Series type is a high -reliability
linear integrated circuit dual high-frequency differential
amplifier intended for low-power applications at frequencies
up to 500 MHz in aerospace, military, and industrial
equipment. It is electrically and mechanically identical with
the standard type CA3049 described in Data Bulletin File
No_ 611 but is specially processed and tested to meet the
electrical, mechanical and envimnmental test methods and
procedures
established
for
microelectronic
devices
in
MIL-STD-883_
The packaged types can be supplied to six screening levels11N./lR.ll.12, 13, and 14-which correspond to MIL-STD-883
Classes A, B. and C. The chip version can be supplied to three
screening levels-1M, IN, and IR. These screening levels and
detailed information on test methods, procedures, and test
sequence are given in Reliability Report Ric-202A "HighReliability CA3000 Slash (I) Series Types Screened to MI LSTD-883_"
Applications
• VH F amplifers
• VHF mixers
combinations
RF/Mixer/Osciliator;
• Multifunction
Converterll F
• I F amplifiers (differential andlor cascade)
•
•
•
•
Product detectors
Doubly balanced modulators and demodulators
Balanced quadrature detectors
Cascade limiters
• Synchronous detectors
•
Balanced mixers
.. Synthesizers
.. Balanced (push-pull) cascade amplifiers
• Sense amplifiers
The CA3049 Slash (I) Series type is supplied in the 12-lead
TO-5 style package ("T" suffix) or in chip form ("H" suffix).
5'2C5-15245
Fig. 1· Schematic Diagram
9-74
345
CA3049 Slash (/) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 707
MAXIMUM RATINGS. Absolute·Maximum Values at TA =2f11C
POWER DISSIPATION, P:
Anyone transistor . • . • . • . . _ . . . • . . . . .
Total package . . . . . • . . . . . . . . . . . . . . .
For TA > 55°C Derate at:
TEMPERATURE RANGE:
Operating . . . • . . . . . . . . . . . . . . • . . . .
Storage . • . • . • . . . . . . . . . . . . . . . . . . .
300
600
5 mW/oC
-55 to +1250 C
-65 to +150oC
LEAD TEMPERATURE (During Soldering):
At distance 1/16 ±1/32"
(1.59 mm ±O.79 mm)
from case for 10 s max.
265"C
Collector-to-Emitter Voltage, VCEO . . . . . . . . .
CollectoNo-Base Voltage, VeBO . . . . . . . . . . .
Collector-to.substrate Voltage, VCIO· . . . . . . ..
Emitter-tooBase Voltage. VEBO . . . . . . . . . . . .
Collector Current, IC . . . . . . . . . . . . . . . . . .
15
20
20
5
60
5.SpF
INPUTr
The following ratings apply for each transistor in the devices
Rg "'50fl
-=
v
L.I
V
V
V
.00112k
rnA
·The collector of each transistor of the CA3049T Is
isolated from the substrate Ly an Integral diode. The substrate
(terminal 9) must be connected to the most negative point In the
external circuit to maintain Isolation between transistors and to
provide for normal transistor action.
+12v-~I----------+-----;
NOTE~: NUMBERS IN PARENTHESES REFER
TO OTHER
.001
.I._
HAL.F OF THE CA3049T
[;1, L2 - Appro •. 1/2 TUrn #18 Tinned Copper Wire, 5/8" Di••
C1, C2 - 15 pF Variable Capacitors (Hammarlund, MAC-15; or
Equ ivalent)
All Capacitors in ",F Unless Otherwise Indicated
All Resistors in Ohms Unless Otherwise Imlicated
"11
Fig. 3 - 200 MHz cascade power gain and noile figure telt circuit.
V-(-6Vl
92CS-2079~
Fig. 2 - Static characteristics test circuit
Table 1- Pre Burn-ln and POIt Burn-In Electrical Tests and Delta Limits~
CHARACTERISTIC
SYMBOL
Input Bias CurrentQ1, Q2, 05, 06
I,
Base Breakdown
Voltage 03, 04
Collector Cutoff Current 01 to 06
'3= '9 = 2rnA
v+ =+6V
I
'3~ '9
Input Bias Current 03, 04
Emitter~to
TEST CONDITIONS
at TA -25"C
= 2rnA
"
V+ =+6V
V EBO
'E = 101lA
'C=O
VCB =10V
' CBO
'Eail
• Levels 11 N," R, 11. and 12 require pre and post burn-In electrical tests and delta IImlu
Lev.r/3 requires pre burn-In electrIcal test only. Tha burn 1n circuit Is shown In Fig. 9.
4
346
LIMITS
MIN.
-
MAX.
25.2
MAX. 11
UNITS
.6
"A
-
50.4
.12
"A
·5.3
-
'1.0
V
.50
nA
-
95
File'No. 707 - - - - - - - - - - - - - - - -_ _ _ _ _ _~CA3049 Slash (I) Series
ELECTRICAL CHARACTERISTICS at T A
=2SoC
LIMITS
CHARACTERISTICS
SYMBOLS
TEST CONDITIONS
CA3049T
UNITS
TYP.
STATIC CHARACTERISTICS
For Each Diffarential Amplifier
I nput Offset Voltage
VIO
I nput Offset Current
110
Input Blal Current
liB
IAVIOI
AT
Temperature Coefficient Mag·
nltude of I nput·Offset Voltaga
13=lg=2mA
0.25
mV
0.3
p.,A
13.5
p.A
1.1
p.V/oC
774
mV
For Each Transistor
DC Forward Base-to·
Emitter Voltage
VBE
Temperature Coefficient of
AVBE
Base-to· Emitter Voltage
Coliector·Cutoff Current
Collector·to·Emitter
Breakdown Voltage
Collector-to-Base
Breakdllwn Voltage
Collector-to·Substrate
Breakdown Voltage
Emitter·to-Base Breakdown
Voltage
DVNAMIC
CHARACTERISTICS
,llf Noise Figure (For
Single Transistor)
Gain·Bandwidth Product
(For Single Transistor)
AT
ICBO
6V
VCE
IC= 1 mA
-o.g
VCE = 6 V, IC = 1 mA
0.0013
VCB - 10 V, IE - 0
IC=lmA,IB=O
24
V
V(BR)CBO
IC= 10p.A, IE = 0
SO
V
V(BR)CIO
IC = 10p.A, IB = 0, IE = 0
SO
V
7
V
V(BR)EBO
IE=10p.A,IC=0
NF
f - 100KHz,RS
IC= 1 mA
fT
VCE = 6 V, IC = 5 mA
500
n
CCB
IC = 0
Collector·Substrate Capacitance
For Each Differential
Amplifier
CCI
IC
Common·Mode Rejection Ratio
CMR
AGC
13 - Ig - 2 mA
Bias Voltage - -SV
Bias Voltage - -4,2V
f= 10MHz
f = 200 MHz
Cascade
Cascade
VCC = 12V
A
Noise Figure
Gil
NF
I nput Admittance
VII
Reverse Transfer Admittance
V 12
0
V22
5V
1.35
GHz
0.2B
O,2B
l,S5
pF
pF
pF
100
75
dB.
dB
22
dB
23
4.6
dB
dB
Cascade
Diff.Amp. 0.B78 + j 1.3
For Diff.
Amplifier
Cascade
1.5 + j 2.45
O-jO.OOB
Configuration
collector
IC'" 2mA)
Output Admittance
VCI
dB
13=lg=2mA
(each
V21
VCB = 5V
1.5
For Cascade
Configuration
13= Ig=4mA
Forward Transfer Admittance
nA
V(BR)CEO
Collector· Base Capacitance
AGC Range, Ona Stage
Voltage Gain, Single-Ended
Output
I nserticn Power Gain
mV/oC
mmho
mmho
Diff.Amp. 0-jO.013
Cascode
17.9 - j 30.7
mmho
Diff. Amp. -10.5+j13
- 0.503 - j 15
Cascade
Diff.Amp. 0.071 + j 0.62
mmho
347
CA3049 Slash (II Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 707
Table /I - Final EIBCtril:sl Tes ..
-
CHARACTERISTIC
iLiMITS FOR
MINIMUM
1+26
TEST CONDITIONS
SYMBOL
I-55
[+125
---55-
~UNITS
+25
+125
STATIC lEach Differ·
ential Amplifer)
Input Offset Voltage
V IO
, Current
110
Input Bias Current
II
-
7
5
7.5
mV
3
3
IJA
13=lg=2mA
V+ =+5V
-
-
-
9
13 = Ig
V+ =+6 V
-
-
-
41
25.2
18
!JA
= 2mA
V CB = 10 V.I E = 0
--
-
-
-
100
-
nA
V BE
VCE = 6V. Ic -lmA
-
-
-
-
874
-
mV
VIBRICEO
IC· lmA.I B =0
-
15
-
-
-
-
V
VIBRlC80
IC= lOIJA.IE =0
-
20
-
-
-
-
V
VI8RlCIO
IC = lOIJA.IB = IE = 0
-
20
-
-
-
-
V
VIBRIEBO
IE = 10IJA. IC = O·
-
5
-
-
-
-
V
Current
Forward Base-toEmitter Voltage
Collector-to-Emltter
Collector-to.sase
Breakdown
Voltage
-
I CBO
Collector Cutoff
Breakdown
Voltage
-
carrector-to-Sub-
strate Breakdown
Voltage
Emitter-to-Base
Breakdown
Voltage
Table III-Group A Electrical Sampling Inspection
CHARACTERISTIC
TEST CONDITIONS
SYMBOL
---
-
I
LIMITS FOR INDICATED TEMPERATURES lOCI
MAXIMUM
MINIMUM
+125
+25
-55
-55
1+125
1+25
UNITS
1
These tests are the same ~ the Final Electrical Tests except for the addition of the Dynamic test shown below
Dynamic
Voltage gain ISlngleEnded Outputl
A
Bias Voltage =4.2V. f - 10 MHz
1
18
I-
-
-
-
Table IV - Group C Electrical Characteristics Sampling Tests (TA = 2S'C)
LIMITS
CHARACTERISTIC
I n put Offset
Voltage
348
SYMBOL
UNITS
TEST CONDITIONS
VIO
MIN.
MAX.
-
S
rnV
Input Bias Current
01. 02. OS. 06
II
13 = 19 = 2 rnA. V+ = +6 V
-
2S.2
JlA
Input Bias Current
03,04
II
13 = 19 = 2 rnA. V+ = +6 V
-
SO.4
Il A
Power Gain
PG
26
dB
19
dB
File No. 707
CA3049 Slash (I) Series
TYPICAL CHARACTERISTICS
.
lODe
AMBIENT TEMPERATURE (TAl ~ 25·C
0.'
6
"I"-
>
e
?,
.
"E
~>-
0.4
..
z
~
!J
g
t;
1£
0
II
0.3i'-..
1'--1-t-
i
(12
(11
6
V
•
2
I
.
EMITTER CURRENT (13.19) ~ mA
V
~
ACLINE
osaLLOSCOPE
WITH
HIGH·GAlN
INPUT
~150
'"
"'''''
:::
'~IOO
"
.
c
~
TEIiAf.J OPEN
7'
~50
-75
-50
-25
a
25
50
75
AMBIENT TEMPERATURE ITAI-DC
100
125
92CS-18066
ALL RESISTANCE VALUES ARE IN OHMS
Fig. 5a-Peak output (pulsed) and gate trigger current with
internal power supply test circuit
354
File No. 703 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA3058 Slash (II Series
y+
"
IDk
120V RMS
60 H~
Ig
OSCILLOSCOPE
WITH
!m ~~~TGAIN
ALL RESISTANCE
VAL.UES ARE
IHOH/IIS
92CS-Z5161
Fig. 6a-Peak output current (pulsed) with external power
supply test circuit
120 V RillS, 50/60-HI OPERATION
AMBIEHT TEMPERATURE (T,,) • 25· C
GATE TRIGGER VOLTAGE (VCTl- 0 v
5
10
15
EXTERNAL POWER SUPPLY VOLTS (V +I
Fig. 6b-10M
vs.
AMBIENT TEMPERATURE (TA )_OC
9ZC~H8064
Fig. 6c-10M with external powersupp/y vs. TA
external power supply voltage
V+~+l2 V
~I
~
i
I.
f,.···==.:::.::::::;·~
11111111111111111111111
01
DI MUST BE Gooa FOR IO > 100 mA
92CS-22935
AMBIENT TEMPERATURE
_lie
92SH2!J
Fig. 7-0perating regions for built-in protection circuit
Fig. 8- Burn-in and operating life test circuit
355
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 831
D\lCIBLJD
Linear Integrated Circuits
Monolithic Silicon
Solid State
High-Reliability Slash (I) Series
CA3078AI ...
Division
High-Reliability
Micropower Operational Amplifier
For Applications in Aerospace, Military, and Critical Industrial Equipment
Features:
•
•
•
•
•
8·LEAO TO-6
with Dual-In-Line
Formed Leads
I""S" Suffix)
H·1787
8·LEAO TO-6
I"T" Suffix)
H·1528
Low standby power: as low as 700 nW
Wide supply voltage range: ±0.75 to ±15 V
High peak output current: 6.5 mA min.
Adiustable quiescent current
Output short-circuit protection
Applications:
•
•
•
•
Portable electronics
Medical electronics
Instrumentation
Telemetry
The CA307BA "Slash" (I) Series types are high·reliability
linear integrated circuit operational amplifiers intended for
applications in aerospace. military. and industrial equipment.
It is electrically and mechanically identical with the standard
type CA307BA described in Data Bulletin File No. 535 but
is specially processed and tested to meet the electrical,
mechanical and environmental test methods and procedures
established for microelectronic devices in MIL·STO·BB3.
The packaged types can be supplied to six screening levels /1 R, /1, 12, 13, and 14 - which correspond to
MI L·STO·BB3 Classes A, B, and C. The chip version can be
supplied to three screening levels - 1M, IN, and IR. These
11 N,
screening levels and detailed information on test methods,
procedures and test sequence are given in Reliability Report
RIC·202A '.'High·Reliability CA3000 Slash (I) Series Types
Screened to MI L-STO-BB3."
The CA307BAS and CA307BAT can deliver milliamperes of
current yet only consume microwatts of standby power.
Their operating points are externally adiustable and fre·
quency compensation may be accomplished with one
external capacitor. The CA307BAS and CA307BAT provide
the designer with the opportunity to tailor the frequency
response and improve the slew rate without sacrificing
power. Operation with a single 1.5-volt battery is a practical
reality with these devices.
The CA307BA is supplied in the standard B-Iead TO·5
package ("T" suffix), the B·lead dual·in-line formed-lead
"01 L-CAN" package ("S" suffix), or in chip form ("H"
suffix).
vNOTE: PIN 8 IS INDICATED BY THE CASE INDEX TAB
nCS-J7552RI
Fig. 1-Functional diagram of the CA3078AS
and CA3078A T.
MAXIMUM RATINGS,
Absolute Maximum Values at TA = 25° C
DC SUPPLY VOLTAGE
(Between V+ and V- terminal) ....... .
36V
DIFFERENTIAL INPUT VOLTAGE ..•••.
:i6V
V+toVDC INPUT VOLTAGE ••...............
INPUT SIGNAL CURRENT ••....••....•
0.1 mA
OUTPUT SHORT·CIRCUIT DURATION'
No Limitation
DEVICE DISSIPATION ••...•••.....•.. 250 mW lup to 125°C)
TEMPERATURE RANGE:
Operating ........................ .
Storage . ...............•.......•..
-55 to +125°C
-65 to +150oC
LEAD TEMPERATURE lOuring Soldering):
At distance 1/16 ± 1/32 in.
(1.59 ± 0.79 mm) from case
for lOs max .••••.•••.••.••.••••••
+3000 C
*Short circuit may be applied to ground or to either supply.
356
9-74
File No. 831 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA3078A Slash (I) Series
ELECTRICAL CHARACTERISTICS, at TA = 250 C
Typical Values Intended Only for Design Guidance
TYPICAL VALUES
CA3078A
V+=+0.75 V,
V-=-0.75V
RSET= 10Mn
10 = lIlA
CHARACTERISTIC
SYMBOLS
V+=+1.3V,
V-= -1.3V
RSET=2Mn
10= lO /lA
VIO
0.7
0.9
0.3
0.054
118
3.7
0.45
AOL
84
65
dB
110
CHARACTERISTICS
CURVES
Fig.
UNITS
-
mV
nA
nA
4,10
10
10
1
/lA
Po
26
1.5
/lW
1.4
0.3
V
-O.B
0.2
to
+0.5
VOPP
~o
VICR
+1.1
-
V
dB
CMRR
10M±
100
90
12
0.5
7
rnA
"'-VIO/"'-V±
20
50
-
/lV/V
Typical Values Intended Only for Design Guidance, at TA = 25°C and
v+ = +6 V,
V- = -6 V
CA307BA
CHARACTERISTIC
SYMBOLS
TEST
CONDITIONS
RSET=5.1 Mn
10= 20/lA
RSET= 1 Mn
10 = 100/lA
UNITS
Input Offset Voltage Drift
"'-VIO/"'-TA
RS';;10Kn
5
6
/lV/oC
Input Offset Current Drift
!:NIO/IlTA
RS';; 10 Kn
6.3
70
pA/oC
3dB pt.
0.3
2
kHz
0.027
0.5
0.04
1.5
V//ls
Open· Loop Bandwidth
BWOL
Slew Rate:
Unity Gain
Comparator
SR
Transient Response
-
Input Resistance
RI
Output Resistance
See Fig. 11
10% to 90%
Rise Time
3
2.5
/lS
7.4
1.7
Mn
1
O.B
RO
Equiv. Input Noise Voltage
eNll0 Hz)
RS= 0
Equiv. Input Noise Current
iNll0 Hz)
RS= 1 Mn
Kn
-
40
0.25
nVii./Hz
pA/v'Hz
Table I. Pre Burn·ln Electrical and Post Burn·ln Electrical Tests, and Delta Limits'
ELECTRICAL CHARACTERISTICS, at TA = 250C, v+ = +6 V, V- = -6 V
CHARACTERISTIC
SYMBOL
TEST
CONDITIONS
L.IMITS
MIN.
MAX.
MAX."'-
UNITS
±1
mV
nA
Input Offset Voltage
VIO
-
3.5
Input Offset Current
110
-
2.5
±0.4
II
-
12
±1.5
nA
10M+orIOM
6.5
-
±1
rnA
Input Bias Current
Maximum Output Current
RS=';;10K
• Lavals /1 and 12 require pre burn-in electrical post burn-in electrical tests. and delta limits.
Level/3 requires pre burn-in electrical test onlv. The burn-in and operating life test circuit is shown in Fig. 18.
357
CA3078A Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 831
Table II Final Electrical Tests and Group A Sampling Inspection
TEST
LIMITS
CONDITIONS
CHARACTERISTIC
SYMBOL
Rset = 5.1 MQ
v+
MINIMUM
I Q =20IIA
MAXIMUM
UNITS
&
v-
RS
KQ
RL
KQ
·55
+25
+125
-55
+25
+125
..
<0;10
-
-
-
4.5
3.5
4.5
mV
5
2.5
5
nA
50
12
50
nA
-
-
-
dB
Input Offset Voltage
V IO
Input Offset Current
110
-
Input Bias Current
liB
-
-
AOL
-
;;'10
90
92
90
-
-
-
-
-
45
25
45
I1A
-
-
-
-
-
540
300
540
IIW
;;'10
±5
±5.1
±5
-
-
-
V
·5
to
+5
·5
to
+5
·5
to
+5
-
-
-
V
Open·Loop Oiff. Voltage Gain
Total Quiescent Current
Device Dissipation
Maximum Output Voltage
IQ
Po
V OM
6
Common·Mode Input Voltage
Range
V ICR
<0;10
-
Common·Mode Rejection Ratio
CMRR
<0;10
10M+orIOM
-
-
Maximum Output Current
-
80
-
-
-
-
dB
6.5
6.5
6.5
30
30
30
mA
-
-
-
IIVN
Input Offset Voltage Sensitivity:
Positive
AVIO/AV+
Negative
AVIO/AV'
f
-
-
76
-
-
-
76
-
<0;10
-
-
-
-
;;'10
88
92
88
-
-
-
-
-
;;'10 ±13.5 ±14.1 ±13.5
<0;10
RSET = 13MQ, IQ = 20!IA
Input Offset Voltage
V IO
t
Total Quiescent Current
IQ
Device Dissipation
Po
-
V OM
-
CMRR
<0;10
-
-
-
-
Open-Loop Diff. Voltage Gain
Maximum Output Voltage
Common-Mode Rejection Ratio
AOL
I nput Bias Current
lIB
I nput Offset Current
110
358
15
r
-
4.5
3.5
4.5
-
50
30
50
I1A
-
1350
750
1350
I1W
-
-
-
V
-
-
-
dB
mV
dB
80
-
-
-
-
55
14
55
nA
-
-
-
5.5
2.7
5.5
nA
File No. 831 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CA3078A Slash II) Series
y+
92CS-17551RI
I
COMPENSATION
8
Fig. 2-Schematic diagram of the CA3078A.
Table III. Group C Electrical Characteristics Sampling Tests at T A = +250 C
CHARACTERISTIC
SYMBOL
Input Offset Voltage
VIO
Input Offset Current
110
Input Bias Current
TEST
CONDITIONS
V+
and
VRS
t
LIMITS
RSET-5.1 MU
IQ =201lA
MIN.
MAX.
RL
4.5
mV
-
4
nA
28
nA
84
-
dB
±4.0
-
V
-
4.5
mV
;;'10KU
84
-
dB
;;'10KU
±10
-
V
6
II
Open· Loop Differential
Voltage Gain
AOL
Maximum Output Voltage
VOM
Input Offset Voltage
VIO
Large·Signal
Voltage Gain
AOL
Maximum Output Voltage
VOM
t
,+
;;'10KU
;;'10KU
IO=20 IlA
RSET= 13m!l
<;;10KU
15
UNITS
-
<;;10KU
r-_-r,..,.:-_ _---c+_ _ _ _ _ _T'T_ _,T..:Y..:P..:ICr.-A,::L:.,C::.;HARACTE RI~TsIUCppSLY VOLTS Y+'+ •• Y_ ._.
SUPPLY VOLTS V =+6, V-"'-6
AMBIENT TEMPERATURE (TA'''Z5°C
SOURCE RESISTANCE (RS) ~ 10 Kn
2 AMBIENT TEMPERATURE
109 (TAl-25°C
1:
i'l •
g 4r-+-~++t-1-~+++.C~A~30~7-B~~+++--+-+~H--+~
2:
~
0
~
j
<'!
>
~
0W
~
~
2.4
0-
1.8
z
1.2
'"~
0
=>
~
.
""O~~~ttU
z
i
'"
2r-+__rttt-~_r~t--,_,+++__+-+_rH--+~
8
•
2r-+_~~t-1_~++t-~_++++__+-+~H--+~
i ':~~~~~~~~~~~~~~~~~~~
2r-1__++++-~_++++_~-+++1_-+-+~H--+~
0.1
468
468
10
468
100
TOTAL QUIESCENT MICROAMPERES IIal
1000
92CS-24745
Fig. 3-lnput offset voltage vs. total quiescent
current.
2
468
2" 6 8
10
100
2
4 68
2
1000
TOTAL CUIESCENT MICROAMPERES
IIQI
4 68
10000
92CS-24746
Fig. 4-lnput bial current VI. total quiescent
current.
359
CA3078A Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
File No, 831
TYPICAL CHARACTERISTICS (Cont'd)
b"
""I
~~I--t---I--I-H---t--t--I-+l-+-I-I-+1~
z
~
!;r--t-+--HH--t--t-++f-+~f-f-H:o
Y
-:.
:e~
~
108
LOAD RESISTANCE IRL): I Mn
108
~
90
IOKn
90
9
..;5
54
~ 72-~
o
18
18
UPPLY VOLTS
S
:
~±::!::g
2
r7'i7' :;
I
-I
10.
~
72
36
ICO,
tl ••
2
'"z
F
I,
~
0.18
•
4
~I
54
36
+6,-6
2
~
: 1261_-I---I--HH__-t--I--I-+l-+-1_1-fI '26
~
AMBIENT TEMPERATURE(TAl lr 25"C
RSET CONNECTED BETWEEN TERMINAL 5 AND v+
1000
AMBIENT TEMPERATURE (T A)=25"'C
'"
2
••
a;
2
o
0.01
468
468
10
TOTAL QUIESCENT MICROAMPERES
864
1000
468
roo
rooo
2
IIQl
864
100
2
86 4
10
2
864
I
2
864
0.1
2
86 4
0.01
TOTAL OUIESCENT MICROAMPERES II Q)
92CS-19631
92CS-19629
Fig. 6-Bias-setting resistance VI, total
quiescent current.
Fig. 5-Open-Joop voltage gain ...s. total
quiescent current.
'~ 100
!~~i~/~i~~E~:;~~E~;~;:5 ~~
V+"+15.V-"-15V
+}
4r--r-"nrr--r-'""r--r-,,,.-f-+~~
~
2r--r-r,rrf--r-~-rf--r~r4+f-+~·~
ill
8~
~~ 4!o-/OY-,+-H+-I--HH+-I--HH+-I-+-l
~~~~~~~~~~~~~~~~~~~
~
2
8
0.001
10
~
~
g
/.5
LOAD RESISTA C IRL1"SOKn
J
'"z
~
~n
I
)
O~
~A1,
1.0
\"1-
'"'"
~
g
~ 0.5
0.1
.. , .. ,
10
~
o
SUPPLY VOLTS V+"+1.3.V-"-1.3
AMBIENT TEMPERATUREtTAI" 25·C
•••1000
100
as
o
1.0
1.5
2.0
TOTAL QUIESCENT MICROAMPERES flO.
TOTAL QUIESCENT MICROAMPERES 11Q)
92CS-19627
92CS-19630
Fig. 8-0utPut voltage swing vs. total
quiescent current.
Fig. 7-Msximum outPut current vs. total
quiescent current.
SUPPLY VOlTS:V+.+S.V-.-6
120f--+---r---t--t---H--r--I
100
~
ffl
I
~
...
.'"'"
z
...
'"
25 ~
~
~
OJ
10
r
103
/04
10'
FREQUENCY If)-Hz
Fig. 9-0pen·/oop voltage gain VS, frequency
for I Q = 20 i'A - CA307BA.
360
10·
92CS-19593
~
_
_
a
~
00
~
~
~
AMBIENT TEMPERATURE (TAJ _·C
92CS-19623
Fig. to-Input bias current vs. temperature.
File No. 831 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ . CA3078A Slash (/) Series
TYPICAL CHARACTERISTICS (Cont'd)
0.6
(II
-i!-
0.5
I"
.- 0.4
ffi
-:
RESISTOR-CAPACITOR
COMPENSATION
(RI-CI BETWEEN
TERMINALS I a~)
CAPACITOR
COMPENSATION
{BETWEEN TERMINALS I a BI
~ 0.3
SUPPLY VOLTS: V+.t6,V-.·'
~
QUIESCENT CURRENT (101- 2O/lA
AMBIENT TEMPERATURE ITA] -zs"c
LOAD IMPEDANCE: RL-iOKIl,CL-l00pF
fEED8ACK RESISTANCE IRF'-O.1 Mil
~ 0.2
OUTPUT VOLTAGE eVopp)·'D v
0./
o
a
R, DETERMINED FOR TRANSIENT
RESPONSE WITH 10"f0 OVERSHOOT
ON A 100 mV OUTPUT SIGNAL
IR,xC,"'2xlo-61
0
ro
ro
~
19J
29>7
40
00
~
CLOSED-LOOP NON-INVERTING VOLTAGE GAIN
6
6
50
60
CLOSED-LOOP INVERTING VOLTAGE GAIN -
ro
00
90
70
80
90
dB
dB
92CS-19591
Fig. 1'-Slew rate vs. closed-loop gain for
10 = 20 ~A - CA3078A.
OPERATING CONSIDERATIONS
Compensation Techniques
The CA307BA can be phase-compensated with one or two
external components depending upon the closed-loop gain,
power consumption, and speed desired_ The recommended
compensation is a resistor in series with a capacitor
connected from terminal 1 to terminal B_ Values of the
resistor and capacitor required for compensation as a
function of closed loop gain are shown in Fig. 12. These
curves represent the compensation necessary at quiescent
NON-INVERTING
INPUT
CLOSED-LOOP NONINVERTING VOLTAGE GAIN- dB
b6
~
_
~
W
~
CLOSED-LOOP INVERTING VOLTAGE -
ro
00
dB
90
92C5-19590
Fig. 12-Phase compensation capacitance vs.
closed-loop gain - CA3078A T.
currents of 20 !lA and 100!lA. respectively, for a transient
response with 10% overshoot. Fig. 11 shows the slew rates
that can be obtained with the two different compensation
techniques. Higher speeds can be achieved with input
compensation, bu t th is increases noise output.
Compensation can also be accomplished with a single
capacitor connected from terminal 1 to terminal B, with
speed being sacrificed for simplicity. Table 4 gives an
indication of slew rates that can be obtained with various
compensation techniques at quiescent currents of 20 pA and
lOO!lA.
RI
v+
I MEG
V~lu~ol
Re reQu,ri!d 10 nave a
nuUadJuslmenlrangeot '75mV
'Re'
f~I~~R~;7.5~Hf.T
auumong RS .
'~F
92C5-25164
RF
UIV
•
·AA'CELL.
"
"
-·;-"~":
fJ
",
'c
ValueolRercquoredlnnavea
null adJUSlment rangeot '7.5mV
Fig. 14-lnverting 20.cJB amplifier circuit.
Fig. 15-Non inverting 20.cJ8 amplifier circuit.
RB~~\0-3
assumingRe >"> RI
92C5-25165
Fig. 13-0ffset voltage null circuits.
361
CA3078A Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 831
v·
v·
IOQkSJ
v·
RSET
V,N
., I
OPTIONAl
R2-C2 COMPo
51kJl
RI
tOPTIONAL
R2-C2 fCOMP.
92CS-25168
92CS-25169
Fig. 16-Transient response and slew-rate,
Fig. 17-Slew-rate, unity gain (non-inverting)
test circuit.
unity gain finVfJrtlng) test circuit.
Table IV. Unity·gain slew rate vs. compensation - CA3078A
SUPPLY VOLTS: V+= 6, V- =-6
TRANSIENT RESPONSE: 10% OVERSHOOT FOR AN OUTPUT
VOLTAGE OF 100 mV
AMBIENT TEMPERATURE (TA) = 25°C
OUTPUT VOLTAGE (VO) =±5V
LOAD RESISTANCE (RtJ = 10kU
UNITY GAIN (INVERTING) Fig. 16
COMPENSATION
TECHNIQUE
Cl
R2
C2
kU
pF
kU
IIF
0
300
Resistor & Capacitor
14
100
=
=
Input
=
0
CA307BAT -IQ = 20llA
Single Capacitor
Rl
0.644
UNITY GAIN (NON-INVERTING) Fig. 17
SLEW
RATE
Rl
R2
C2
SLEW
RATE
VIlis
kU
pF
kU
IIF
0
0.0095
0
BOO
0
0.003
0
0.027
34
125
=
=
0
0.02
0.156
0.29
=
0
0.77
0.4
0.4
TO OSC, .....JV
' OV·"II.j.......(
L-----()_IOV
92CS-24747
Fig. t8-Sum-ln and operating life test circuit.
362
Cl
VIlis
File No. 709 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Linear Integrated Circuits
OOCIBLJD
Monolithic Silicon
Solid State
Division
High-Reliability Slash(/) Series
CA3080/ . .., CA3080A/ ...
f,
High-Reliability Operational
Transconductance Amplifiers
Gateable-Gain Blocks
.~
'-'1
For Applications In Aerospace, Military and Critical Industrial Equipment
Features:
H·1787
H·1528
8-LEAO TO-5 Style
Package with DualIn-Line Formed Leads
8·LEAO
TO·5 Style
Package
• Slew rate (unity gain, compensated): 50 VIlls
• Adjustable power consumption: 10 IlW to 3D mW
• Flexible supply voltage range: ±2 V to ±15 V
• Fully adjustable gain: 0 to gmRL limit
• Tight gm spread: CA3080 (2:11, CA3080A (1.6:1)
•
•
Extended gm linearity: 3 decades
Hermetic package: 8·lead TO·5 style
RCA-CA30BO and CA30BOA "Slash" II) Series types are
high'reliability linear integrated circuit Operational
Transconductance Amplifiers. These gateable-gain blocks,
which utilize the same unique OTA (Operational
Transconductance Amplifier) concept first introduced in the
RCA-CA3060. are intended for applications in aerospace,
military, and industrial equipment. They are electrically and
mechanically identical with the standard types CA30BO and
CA30BOA described in Data Bulletin File No. 475 but are
specially processed and tested to meet the electrical,
mechanical and environmental test methods and procedures
established for microelectronic devices in MIL-STD-BB3.
Applications:
• Sample and hold
• Multiplex
" Voltage follower
Multiplier
.. Comparator
II
sequence are given in Reliability Report RIC-202A "HighReliability CA3000 Slash II) Series Types Screened to MILSTD-aa3."
The CA30BO and CA30BOA Slash II) Series types are
supplied in the B-Iead TO-5 style package ("T" suffix), in the
a-lead TO-5 style package with dual-in-line formed leads,
DI L-CAN, ("S" suffix), or in chip form ("H" suffix).
The packaged types can be supplied to six screening levels11N,/1R,Il,12, 13, and 14-which correspond to MIL-STD-BB3
Classes A, B, and C. The chip version can be supplied to three
screening levels-1M, IN, and IR. These screening levels and
detailed information on test methods, proc~dures. and test
MAXIMUM RATINGS,Absolute-Maximum Values at TA = 25"C
DC Supply Voltage (between V+ and V- terminals)
Differential Input Voltage
. . . . . • 36 V
. . • . . . . . . . . . . . . . . . . . . ±5 V
DC Input Voltage . . • . • . . . . . . . • . . • • . . . . . . . v+ to VInput Signal Current • • • . • • • . • • . • • • • • • • • • . • • • 1 rnA
Amplifier Bias Current • . . . . . . . • . . . . . . . . . . . . . • 2 rnA
Output Short·Circuit Duration . . . . . . . • . . • . . . . Indefinite
Device Dissipation
. . . . . . . . . . . . . . . . . . . . . . . 125 mW
Temperature Range:
Operating
CA3080 . . . . . . . . . . . . . . . . . . . . . . . . Ot070 'c
CA3080A .. .. .. .. .. .. .. .. . . . . -55 to + 125' C
Storage . . . . . . . . . . . . . . . • . . . . . . . . . 65 to +150 DC
Lead Temperature (During Soldering):
At distance 1/16 ±1/32 in. (1.59 ±0.79 mml
from case for lOs max. . . . . . . . . . . . . . . . . .
92CS-17587
+ 300"C
Fig. 1 - Schematic diagram for CA3080 and CA3OBDA.
9·74
363
CA3080. CA3080A Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
File No. 709
ELECTRICAL CHARACTERISTICS
For Equipment Design
CA30BO
TEST CONDITIONS
v+ = 15V. V- = -15V
CHARACTERISTICS
SYMBOLS
' ABC ' 5OOI'A
TA = 25°C
lunless indicated
otherwiseJ
Input Offset Voltage
V ,O
Input Offset Current
',0
Input Bias Current
I,
Forward Transconductance
(large signal)
9m
Peak Output Current
LIMITS
UNITS
TYP.
0.4
mV
0.12
I'A
2
I'A
9600
RL=O
Ilrnho
500
I'A
l'oMI
Peak Output Voltage:
Positive
V~M
Negative
YOM
Amplifier Supply Current
RL =
~
~
V
-14.4
'A
1
Device Dissipation
Po
30
mW
Common-Mode Rejection Ratio
CMRR
110
dB
Common-Mode Input-Voltage Range
V CMR
'~.:~o
Input Resistance
R,
26
mA
V
kf!
ELECTRICAL CHARACTERISTICS
CA3080
Typical Values Intended Only For Design Guidance
V ,O
' ABC -5I'A
0.3
mV
Input Offset Voltage Change
I flV,ol
Change in VIO between
' ABC =500l'A
and ' ABC = 51'A
0.2
mV
Peak Output Current
'0M
' ABC =5I'A
5
I'A
' ABC =5I'A
-14.5
Input Offset Voltage
Peak Output Voltage:
Positive
Negative
VbM
YOM
Magnitude of Leakage Current
Differential Input Current
Amplifier Bias Voltage
Slew Rate:
Maximum (uncompensated)
Unity Gain (compensated)
' ABC = O. VTP - 0
36V
O.OB
'ABC= 0, VTP
0.3
' ABC - 0, V OIFF - 4V
0.008
0.71
V ABC
-
SR
-
75
50
2
V
nA
nA
V
VII'S
MHz
Open-Loop Bandwidth
BWOL
Input Capacitance
C,
f= 1 MHz
3.6
Co
1= 1 MHz
5.6
pF
15
Mf!
Output Capacitance
364
13.8
Qutput Resistance
RO
Input-to-Output Capacitance
C,·D
~ -1 MHz
0.024
pF
pF
File No. 709 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA3080, CA3080A Slash (I) Series
ELECTRICAL CHARACTERISTICS
For Equipment Design
CA3080A
TEST CONDITIONS
CHARACTERISTICS
SYMBOLS
V+·15V.V '-15V
I ABC ' 500I'A
TA • 25°C
(unless indicated
otherwise)
Typ.
0.3
Input Offset Voltage
VIO
I ABC ' 51'A
Input Offset Voltage Change
IIIVlol
Change in VIO
between,' ABC = 500 P A
and I ABC ' 51'A
I"put Offset Current
1'0
Input Bias Current
Forward Transconduct:mce
(large signal)
Peak Output Current
LIMITS JNITS
~
mV
0.1
mV
0.12
I'A
2
I'A
'I
l'oMI
pmho
9600
9m
'ABC· 51'A, RL • 0
RL • 0
r--soo
5
I'A
Peak Output Voltage:
Positive
V~M
'ABC· 5 I'A
Negative
V OM
RL
Positive
V
Negative
OM
V OM
13.8
14.5
~
V
13.5
Rl '"
O?
-14.4
Amplifier Supply Current
IA
1
mA
Device Dissipation
PD
30
mW
Input Offset Voltage Sensitivity:
Positive
I!N I OIIlV+
Negative
IIVIO/IIV
I ABC ' 0, V TP '
Magnitude of Leakage Current
Differential Input Current
a,
I'VIV
O.OB
I ABC • 0, V TP - 36V
I~
nA
IABC·O,VDlFF·4V
O.OOB
nA
Common-Mode Rejection Ratio
CMRR
110
dB
Common-Mode Input-Voltage Range
V CMR
13.6to
-14.6
V
RI
26
kn
Input Resistance
ELECTRICAL CHARACTERISTICS
Typical Values Intended Ony For Design Guidance
Amplifier Bias Voltage
Slew Rate:
Ma)(imum (uncompensated)
Unity Gain (compensated)
CA3080A
V ABC
0.71
75
SR
50
-
V
VI,,"
Open- Loop Bandwidth
BWOL
Input Capacitance
CI
f= 1 MHz
3.6
Output Capacitance
Co
1'1 MHz
5.6
pF
Output Resistance
RO
15
Mn
Input-to-OutpU'l Capacitance
CI·O
0.024
pF
1'1 MHz
2
MHz
pF
365
CA3080, CA3080A Slash (II Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 709
Table 1- Final Electrical Tesa
TEST CONDITIONS
CHARACTERISTIC
SYMBOL
v+ ~ +15 V. IABC ~ 0.5 mA
V-~-15V
LIMITS FOR INDICATED TEMPERATURES "C)
MAXIMUM
MINIMUM
-55
+25
+125
+25
+125
-
-
-
6
5
5
2
6
5
mV
-
-
1.2
1.2
0.6
0.6
0.7
0.7
jJA
8
8
5
5
13000
9000
13000
12000
8
8
20000
18000
-
-
-
-
-
-
750
750
650
650
750
750
jJA
1.4
1.4
1.2
1.2
1.4
1.4
mA
-
-
Via
CA3OBO
CA3OBOA
Input Offset Current
110
CA3OBO
CA3OBOA
Input Bias Current
II
CA3OBO
CA3OBOA
-
9m
CA3080
CA3OBOA
5400
4000
6700
7700
11.6
12
12
11.B
12
12
CA3OBO
CA3OBOA
350
350
350
350
CA30BO
CA30BOA
0.7
0.7
CMRR
CA3OBO
CA3OBOA
80
O.B
O.B
BO
80
320
320
0.7
0.7
80
VRR
CA3OBO
CA3OBOA
-
lnput Offset Voltage
Forward Transconductance
Peak
Output
Positive
+VOM
Voltage
Negative
-YOM
RL -~
Peak Output Current
Amplifier Supply
Current
Common-Mode
Rejection Ratio
Supply Voltage
Rejection Ratio
RL -0
Ii0MI
IA
CA3OBO
CA3OBOA
CA3OBO
CA3OBOA
UNITS
-55
BO
-
5400
4000
BO
-
-
-
150
150
150
150
-
150
150
jJA
umho
V
d8
jJV!V
Table /1- Group A Electrical Sampling Inspection
CHARACTERISTIC
Input Offset Voltage
Input Offset Current
Input Bias Current
Forward T ransconductance
Peak
Output
Voltage
Positive
V-
TEST CONDITIONS
-15 V. V+ = +15 V.
IABc-0.5mA
D
Negative
Amplifier Supply
Current
Common-Mode
Rejection Ratio
Supply Voltage
Rejection Ratio
~ntiallnput
Current
Magnitude of Leakage
Current
LIMITS FOR INDICATED TEMPERATURES "CI
MAXIMUM
MINIMUM
+125
-55
+25
+125
-55
+25
-
-
B
8
5
5
B
B
jJA
5400
4000
6700
7700
5400
4000
13000
9000
13000
12000
20000
lBooo
umho
11.6
12
12
-
-
-
11.8
12
12
-
-
-
CA3080
CA3OBOA
350
350
350
350
320
320
750
750
650
650
750
750
jJA
CA3OBO
CA3OBOA
0.7
0.7
0.7
0.7
1.4
1.4
1.2
1.2
1.4
1.4
mA
CMRR
CA3OBO
CA30BOA
80
80
0.8
O.B
80
80
80
80
-
-
-
VRR
-
-
150
150
150
150
CA3OBO
CA3OBOA
-
-
-
-
CA3OBO
CA3OBOA
-
-
-
-
CA30BO
CA30BOA
110
CA30BO
CA30BOA
II
CA30BO
CA3OBOA
9m
CA30BO
CA3080A
+VOM
-YOM
110M I
RL -0
IA
IABC - IOmA.
VDIFF -4V
CA3OBO
CA3OBOA
CA30BO
CA3OBOA
CA3OBO
IABC - O. VTP - 0
CA3OBOA
CA3OBO
IABC-0.VTP-3
CA3OBOA
-
-
-
UNITS
-
Via
RL -~
Peak Output Current
366
SYMBOL
-
6
5
5
2
6
5
mV
1.2
1.2
0.6
0.6
0.7
0.7
jJA
-
150
150
7
5
-
7
5
7
5
-
-
V
dB
jJVIV
nA
nA
nA
File No. 709 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA3080, CA3080A Slash (I) Series
Table lil- Pre Burn-In and Post Burn-In Electrical Tests and Delta Limits·
CHARACTERISTIC
SYMBOL
Input Offset Voltage
Input Offset CUrrent
Input Bias Current
Forward Transconductance
TEST CONDITIONS
ATTA=25"C
V+Q+15V,V-=-15V
IABC= 0.5 mA
VIO
CA3D80
CA3080A
110
CA3D80
CA3D80A
II
CA3080
CA3D80A
gm
CA3080
CAJD80A
LIMITS
MIN.
MAX.
MAX.!;
-
5
2
.0.2
'0.15
.0.05
.0.05
0.6
0.6
-
-
5
5
6700
7700
UNITS
mV
~A
'0.25
.0.25
.3000
<3000
13000
12000
~A
umho
"'Levels /1 N, /1 A, /1, and 12 require pre and post burn-in electrical tasts and dalta limits
Level 13 requires pre burn-in electrical test only. The burn-in and operating life test circuit is shown in Fig. 12.
Table I V- Group C Electrical Characteristics Sampling Tests (TA ::::: 2!t'C)
CHARACTERISTIC
SYMBOL
Input Offset Voltage
Input Bias Current
Forward Transconductance to
Terminal No, 1
Peak Output Current
MIN.
CA3080
VIO
Input Offset Current
LIMITS
TEST CONDITIONS
V+= +15 V, V-= -15 V
~A3080A
MAX.
-
-
6.5
5.5
-
1.2
-
10
10
~A
umho
110
CA3080
CA3080A
II
CA3080
CA3080A
gm
CA3081!
CA3080A
6590
7000
14000
13000
Ii0MI
CA3080
CA3080A
300
300
700
700
CA3080_
11
+VOM
-
CA3080A
CA3080
Peak Output Voltage
-YOM
mV
~A
~A
_CC
-
11
V
-
-11
-1
c:A~80~
UNITS
Typical Characteristics Curves for the CA30BO and CA30BOA
:~s_u,P_PL_YTV_O,LTTsT:v_+_·r+_15,._vTT·T'_5-+__~~__~~~1
+l2.5·C
TOP VIEW
+90
~
~
I -5SOC
~
~
ollFo
j
i
~
~
0
vNOTE: PIN 815 INDICATED BY THE CASE INDEX TAB
92C5-17660
~
'"
v
_1~90
V
+25
-2
-.-.
/
.f-I25·C
-5
-6
1
-7/
468
0.1
Fig. 2 - Functional diagram of CA30BO
and CA3080A.
468
468
t
[a
100
AMPLIFIER BIAS MICROAMPERES I rABe)
466
1000
92C5-17588
Fig. 3 - Input offset voltage vs. amplifier bias current
367
CA3080, CA3080A Slash (II Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 709
Tvpical Characteristics Curves for the CA3080 and CA3080A (Cont'd.)
IO~ Supp~y
10 16 SUPPLY VOLTS! V+=+15. V-: 15
VOLTS: V+=+l5, V-=-15
~
w
w
.'"
2
"~ 10•
4
;i!
0-
w
~
:::
0
~
:!O
2
I
;• ....
0.1
2
ODI
468
468
I
0.1
468
10
468
468
100
1000
0.1
AMPLIfiER BIAS MICROAMPERES (IABCI
468
468
468
I
10
roo
AMPLIFIER BIAS MICROAMPERES (I.ABe'
1000
92Cs-t7!590
92CS-17589
Fig. 5 - Input bias current vs. amplifier bias current.
Fit!- 4 -Input offset current vs. amplifier bias current
IO~ SUPPLY VOLTS: V+=+l5, V-=-15
4
••
2
4
68
2
"68
2
4
6 8
I
10
100
AMPLIfiER BIAS MICROAMPERES (IABC'
1000
0.1
468
,
468
10
468
100
468
1000
AMPLIFIER BIAS MICROAMPERES I lABC)
92CS-11591
92C$-11592
Fig. 6 - Peak output current vs. amplifier bias current.
Fig. 7 - Peak output voltage vs. amplifier bias current
10: AMBIENT TEMPERATURE (TAJ =25"C
4681
0.1
468
468
4
I
10
100
AMPLIFIER BIAS MICROAMPERES (IABCI
••
1000
92CS·17593
Fig. 8 - Amplifier supply current vs. amplifier bias current.
368
468
468
468
468
I
10
100
AMPLIFIER BIAS MICROAMPERES IIABC)
1000
92C$-11t594
Fig. 9 - Total power dissipation vs. amplifier bias current.
File No. 709 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA30BO, CA30BOA Slash (/) Series
Typical Characteristics Curves for CA30BO and CA30BOA - Confd.
10 56 SUPPLY VOLTS:V+=+15,V
SUPPLY VOLTS V"'·+15.V-:-15
15
,
10'
·
·,
·, ·
2
10'
'r---
_
/
+12S·C
/
2
/
10 2
7'[-/'
2
10
./
_ + 25"~
2
I
,
:2
4
4
I
0.1
INP,UT DIFFERENTIAL VOLTS
68
10
AMPLIFIER BIAS MICROAMPERES
100
(IABC}
92C5-17598
1000
92CS-17599
Fig. 11 - Transconductance vs. amplifier bias current.
Fig. 10 -Input current vs. input differential voltage.
BURN IN
CIRCUIT NO. I
2kfi
tOka
68 kn
180 kn
UNIT
5 /UNDER
TEST
10 k.n
180kn
TO TERMINAL
>-----r--""1"-""1"--''--T---"""1-,
UNREGULATE
INPUT
.,
40k
R!5
500
COMPENSATION
,---t-t---{'!)7 AND
EXTERNAL
INHIBIT
CURRENT
BOOSTER
Fig_2-Schematic diagram of CA3085 Series.
371
CA3085, CA3085A, CA3085B Slash (II Series _ _ _ _ _ _ _ _ _ _ __
File No. 708
ELECTRICAL CHARACTERISTICS
LIMITS
TEST CONDITIONS
CA3085 CA3085A CA3085B
TA = 25°C
CHARACTERISTICS
Reference Voltage
Quiescent Regulator
Current
I nput Voltage Range
SYMBOL
VREF
'quiescent
TYP.
TYP.
TYP.
V+'N = 15V
1.6
1.6
1.6
V+'N = 30V
3.3
-
-
(Unless indicated otherwise)
V+IN = 40V
-
3.65
V+IN= 50V
27
37
1.6
1.6
1.6
V
-
-
-
V
V+IN = 16V, V+OUT= 10V
RSCP' = 6n
96
96
96
IL = 1 to l00mA, RSCp = 0
-
0.025
0.025
-
0.035
0.035
Maximum Output
Voltage
Vo(max.)
Minimum Output
Voltage
Vo(min.)
V+'N = 30V
Input·Output Voltage
Differential
V,N,VOUT
•
Load Regulation
-
'L = 1 to l00mA, RSCp= 0
-
TA = OOC to +700 C
IL= lto12mA,Rscp= 0
IL
Line Regulation'"
-
= 1 mA, RSCp:"
0
I L = 1 mA, RSCp = 0
T A = OoC to +700 C
Equivalent Noise
Output Voltage
VNOISE
-
Ripple Rejection
Output Resistance
Temperature Coel·
licient 01 Reference
and Output Voltages
Load Transient
Recovery Time:
Turn On
Turn Off
Line Transient
Recovery Time:
Turn On
Turn Olf
ro
~VREF.
~Vo
4.05
-
V
47
V
0.003
-
-
0.025
0.025
0.025
0.04
0.04
0.04
mA
%VOUT
%/V
CREF = 0
0.5
0.5
0.5
'CREF = O.22j.tF
0.3
0.3
0.3
V+'N = 25V
CREF = 0
50
50
50
I = 1kHz
CREF = 2j.tF
56
56
56
0.075
0.075
0.075
0.0035
0.0035
0.0035
%flC
V+IN = 25V
V+'N
= 25V, I
= 1 kHz
'L = 0, VREF = 1.6V
mVp·p
dS
n
tON
V+IN = 25V, +50mA Step
1
1
1
j.ts
tOFF
V+'N = 25V, -50mA Step
3
3
3
j.ts
tON
V+IN = 25V, I = 1 kHz, 2V Step
tOFF
#30 (CA3085), 40V(CA3085A). 50V(CA3086B)
• RSCp: Short-circuit protection resistance
372
mA
-
-
VIN(range;
ILiM
V
-
V+IN = 30,40,50V#; R L = 365 n;
Term. No.6 to Gnd.
Limiting Current
-
UNITS
• load Regulation '"
VOUTtinitial)
Xl"""
0.8
0.8
0.8
j.ts
0.4
0.4
0.4
j.ts
File No. 708 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA3085, CA3085A, CA3085B Slash (II Series
Table I - Pre Burn-In and Post Burn In Electrical Test and Delta Limits*
CHARACTERISTIC
TEST CONDITIONS
TA=25°C
MIN.
LIMITS
MAX.
MAX.
CA30B5A. B
1.5
1.7
iO.05
V
CA30B5
1.4
1.B
iO.05
V
-
1.7
iO.l
V
1.7
iO.l
V
loB
iO.l
V
-
iO.5
V
SYMBOL
Reference Voltage
VREF
VIN +7.5 V or +50 CA30B5B
Output Voltage
VO(min.)
VIN +7.5 V or +40 V CA30B5A
VIN +7.5 Var+30V CA30B5
VO(max.)
Limiting Current
:it
VIN = 50 V CA30B5/B
46
VIN = 40 V CA30B5/A
36
VIN = 30 V CA30B5
26
VIW 7.5V RSCp=7
ILiM
n, RL=10 n
-
115
UNITS
iO.5
V
iO.5
V
+10
rnA
Levels/1 N,ll R,ll, and/2 require pre and post burn-in electrical tests and delta limits
Level/3 requires pre burn-in electrical test only. The burn-in circuit is shown in Fig. 7.
Table 1/ - Final Electrical Tests and Group A Electrical Sampling Inspection
LIMITS FOR INDICATED TEMPERATURES (OC)
CHARACTERISTIC SYMBOL
TEST CONDITIONS
MINIMUM
-55
Reference Voltage
OUtput Voltage
Minimum Value
VREF
VIN = 7.5V or 50V CA30B5/B
VO(min.)
VIN -7.5V or 40V CA30B5/A
VIN - 7.5 V or 30V CA30B5
55
+25
UNITS
+125
1.4
1.4
1.3
1.9
1.B
loB
V
-
-
-
loB
1.7
1.7
V
-
-
1.B
1.7
1.7
V
1.9
loB
loB
V
25
26
24
-
-
-
35
36
34'
-
-
-
V+IN = 50 V, CA30B5B
45
46
44
-
-
-
-
CA30B5A
-
RSCp = 0
CA30B5B
-
IL=lta12mA
CA30B5
= 1 rnA
RSCp = 0
CA30B5
-
IL
Load Regulation
= 1 to 100 rnA
IL
Line Rgulatian
CA30B5A
CA30B5B
Table 111- Group C Electrical Characteristics Sampling Tests ITA
CHARACTERISTIC
Reference Voltage
SYMBOL
-
Minimum Output Voltage
TEST CONDITIONS
VREF
VO{rnin)
V
-
0.75
0.15
0.75 %IVOUT
-
0.75
0.15
0.75 %IVOUT
0.15
0.10
0.15 %IVOUT
0.2
0.1
0.2
0.15
0.075
0.15 %IV
0.12
0.04
0.12 %IV
%IV
= 25"C)
V+'N = 30 V, CA3085
Load Regulation
MAXIMUM
+125
VO(max.) V+IN = 40V, CA30B5A
V+IN = 30V, CA30B5
Maximum Value
+25
LIMITS
MIN.
MAX.
UNITS
1.4
1.8
V
-
1.9
V
= 40 V, CA3085A
-
1.9
V
V+IN = 50 V, CA3085B
-
2.0
V
IL = 1 to 100 rnA
CA3085A
-
0.3
CA3085B
CA3085
-
0.75
V+'N
\RSCp= 0
\'L=1to12mA
IL= 1 rnA
Line Regulation
RSCp = 0
CA3085
CA3085A
CA3085B
0.15
-
%/VOUT
0.25
0.1
%/V
0.05
373
CA3085, CA3085A, CA3085B Slash
(/I Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 708
.. " INPUT VOLTS IV+1N )zI5
120 :- OUTPUT VOLTS (VbUT ,aIO .
+- .
oct'
..
c:-'-!'0
t"e~--
8~
i:;:~ r-1:
::::j:
0:'
-75
'rt;-H-~
-i-"""" ~.t-t,
-50
-25
25
50
15
100
125
AMBIENT TEMPERATURE ITAI-·C
LOAD CURRENT II.Ll- mA
92CS-18098
92CS-I7351
Fig. 4- Load regulation characteristics.
INPUT VOLTS I Y+IN1= 20
OUTPUT VOLTS IV+our)-'O
REFERENCE VOLTS IVREF) =+1.6V {AT TA=2soCl
LOAD CURRENT IIL)-O
~~
~i5
0
z%_O.1
....""55-0.2
wW
zz
.,.,
0.01
-75
-50
-25
0
25
50
75
100
12.
AMBIENT TEMPERATURE ITA 1-·C
-0.'
-7'
lOll
CA3085
CA3085A
CA3085B
~-------+--~--
___ TO DCVM
I'll
1%,2W
Fig. 7- Burn-in and operating life telt circuit.
374
7.
100
12.
Fig. 6- Temperature coefficient of VREFand YOUr.
Fig. 5- Line regulation femperawTfI characteristics.
1%
00
AMBIENT TEMPERATURE ITA1_oC
92CS-I7546
~2CS'17345
File No. 692 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
oornLJD
Linear Integrated Circuits
Monolithic Silicon
Solid State
Division
,.
High-Reliability Slash (I) Series
CA3094/... CA3094A/... CA3094B/...
.I
(
a·LEAo TO·S·
with Dual-In-Line
Formod Leads
("S" Suffix)
a·LEAD TO·S
("T" SUFFIX)
High-Reliability
Programmable Power Switch/Amplifiers
For Control & General·Purpose Applications
In Aerospace, Military, and Critical Industrial Equipment
Features:
•
•
•
•
Designed for single or dual power supply
Programmable: strobing, gating, squelching, AGC capabilities
Can deliver 3 watts (avg.) or 10 W (peak) to external load (in switching mode)
High·power, single'ended class A amplifier will deliver power output of 0.6
watt (1.6 W device dissipation)
• Total harmonic distortion (THO) @0.6W in class A operation -1.4% typo
• High current·handling capability - 100 mA (avg.), 300 mA (peak)
RCA·CA3094, CA3094A, and CA3094B "Slash" (/) Series are
high·reliability linear integrated circuit differential·input power·
control switch amplifiers with auxiliary circuit features for ease
of programmability. They are intended for use in a variety of
control and general-purpose applications for aerospace, military and industrial equipment. These devices are electrically
and mechanically identical with standard types CA3094,
CA3094A and CA3094B described in Data Bulletin File
No. 598, but are specially processed and tested to meet the
electrical, mechanical, and environmental test methods and
procedures established for microelectronic devices in MILSTD·883. The CA3094 is intended for operation up to 24
volts. The CA3094A and CA3094B are like the CA3094
but are intended for operation up to 36 and 44 volts, reo
spectively (single or dual supply).
The packaged types can be supplied to six screening levelsI1N.llR,/l.12, 13, and 14-which correspond to MIL·STD·883
Classes A, B, and C. The chip version can be supplied to three
screening levels-1M, IN, and IR. These screening levels and
detailed information on test methods, procedures, and test
sequence are given in Reliability Report RIC·202A "High·
Reliability CA3000 Slash (I) Series Types Screened to MIL·
STD·883."
The CA3094, CA3094A, and CA3094B "Slash" (I) Series
types are suppl ied in the 8·lead TO·5 style ceramic package
("T" Suffix), in 8·lead TO·5 style ceramic package with I
dual·in·line formed leads - ("S" Suffix DIL·CAN) - or in
chip form ("H" Suffix).
• Sensitivity controlled by varying bias current
a Output: usink" or ·'drive" capability
Applications:
iii
•
•
•
a
Error-signal detector: temperature control with thermistor
sensor; speed control for shunt wound de motor
Over-current, over-voltage, over-temperature protectors
Dual·tracking power supply with RCA·CA3085
Wide-frequency-range oscillator • Analog timer
Level detector a Alarm systems a Voltage follower
a Ramp-voltage generator
• High-power comparator
• Ground·fault interrupter (GFI) circuits
GROUND*
4
DIFFERENTIAL
VOLTAGE
INPUTS ___ 2
EXTERNAL
FREQUENCY
COMPENSATION
OR INHIBIT
INPUT
lABe CURRENT
PROGRAMMABLE J
~INPUT
(STROBE OR AGCI
DRIVE OUTPUT
[EMITTERI
SINK OUTPUT
[COLLECTORI
92C5-20415
*GROUNDj V- IN
DUAL' SUPPLY
OPERATION
Terminal Connections (Bottom View, Terminal End)
9·74
375
CA3094. CA3094A. CA3094B Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 692
%[T).RG~NTIAL
INPUTS
INPUTS
!NV. NON-INY.
2
3
92CS-20294
Fig.1 - Schematic diagram of CA3094, CA3094A, and CA30948
Slash (/) Series Tvpes.
MAXIMUM RATINGS. Absolute-Maximum Values:
CA3094/Series
DC Supply Voltage:
Dual Supply .............. "................... .
Single Supply ............................... .
DC Differential Input Voltage
(Terminals 2 and 3) ........................... .
DC Common-Mode Input Voltage ......... _ . __ ... __ .
Peak Input Signal Current
(Terminals 2 and 3) ............... _.. _... _.... .
Peak Amplifier Bias Current
(Terminal 5) .......... __ .. __ .. ____ ....... _ . _ .
Output Current:
Peak _____ . ______ ........... __ .............. .
Average . __ . _... _........ _... _.... ___ .. _ . _.. .
Device Dissipation:
Up to T A = 55°C:
Without heat sink ......... _. ___ .... __ ... _.. .
With heat sink
Above TA = 55°C:
Without heat sink derate linearly
With heat sink derate linearly
Thermal Resistance
(Junction to Air)
Ambient Temperature Range:
Operating .... _ . ___ . _... _................ _.. __
Storage ..................................... ..
Lead Temperature (During Soldering):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm)
from case for lOs max.
± 12V
24V
CA3094A/Series
CA3094B/Series
± 18V
36V
± 5*
Pin 4::;; Pins 2 & 3::;; Pin 7
V
V
V
+1
mA
2
mA
300
100
mA
mA
630
1.6
mW
W
'6.67
16.7
mW/oC
mW/oC
140
°C/W
55 to +125
-65 to +150
oc
°C
+300
°C
*exceeding this voltage rating will not damage the device unless the peak input signal current (1 rnA) is also exceeded.
376
± 22 V
44V
File No. 692 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA3094. CA3094A. CA3094B Slash (I) Series
ELECTRICAL CHARACTERISTICS TA = 25 0 C
Typical Values Intended Only for Design Guidance
TEST CONDITIONS
LIMITS
I Single Supply V+ = 30 V
CHARACTERISTIC
SYMBOL
!
Dual Supply V+ = 15 V,
V-= 15V
IABC = 100 p.A
Unless Otherwise
Specified
Typ.
UNITS
0.4
mV
1
mV
INPUT PARAMETERS
Input Offset Voltage
Via
Input·Offset·Voltage Change
It.Vlol
Change in Via
Between IABC = 100 p.A
and IABC = 5 p.A
Input Offset Current
110
Input Bias Current
II
Device Dissipation
Po
Common-Mode Rejection Ratio
CMRR
Common·Mode InputVoltage Range
VCMR
0.02
p.A
0.2
/lA
10
mW
110
dB
V+ = 30 V High
Low
28.8
V
O.S
V
V+ = lS V
+13.8
V
V- = lS V
-14.S
V
lout = 0
Ic=7.SmA
Unity Gain-Bandwidth
VCE=lSV
30
MHz
4
kHz
IABC = SOD /lA
IC = 7.S mA
Open-Loop Bandwidth
At -3 dB Point
BWOL
VCE=lSV
IA8C = SOO/lA
Total Harmonic Distortion
(Class A Operation)
THO
PD = 220 mW
0.4
PD = 600 mW
1.4
Amplifier Bias Voltage
(Terminal (No.S to Terminal No.4)
0.68
VABC
Input Offset Voltage
Temperature Coefficient
Power-Supply Rejection
4
t.VIO/t.T
t.VIO/t.V
f = 10 Hz
l/F Noise Voltage
EN
IN
Differential Input Resistance
RI
Differential Input Capacitance
/lV/oC
15
/lV/V
18
nV/1Hz
1.8
pA/Fz
1
Mn
2.6
pF
IABC= SO/lA
IABC= 20/lA
.f = 1 MHz
CI
V
IABC = SO /lA
f = 10 Hz
l/F Noise Current
%
·V+=30V
377
CA3094, CA3094A, CA3094B Slash
(II Series
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 692
ELECTRICAL CHARACTERISTICS TA = 25°C
Typical Values Intended Only for Design Guidance
TEST CONDITIONS
CHARACTERISTIC
Single Supply v+ = 30 V
Dual Supply v+ = 15 V,
V-= 15V
SYMBOL
IABC= 100/1A
Unless Otherwise
Specified
LIMITS
Typ.
UNITS
OUTPUT PARAMETERS (Differential Input Voltage = 1VI.
Peak Output Voltage:
(Terminal No. 61
With 013 "ON"
With 013 "OFF"
Peak Output Voltage:
(Terminal No. 61
Positive
Negative
Peak Output Voltage:
(Terminal No. BI
With 013 "ON"
With 013 "OFF"
Peak Output Voltage:
(Terminal No. 81
Positive
Negative
Collector-ta-Emitter
Saturation Voltage
+VOM
V+=30V
RL = 2 kH to ground
-YOM
27
0.01
V
V
+12
-14.99
V
V
29.99
0.040
V
V
+14.99
14.96
V
V
0.17
V
V+=+15V, V-=-15V
+VOM
RL=2kHto-15V
-YOM
+VOM
V+ = 30 V
-YOM
RL = 2 kSl to 30 V
+VOM
V+ = 15 V, V- = - 15 V
RL = 2 kS! to + 15 V
-YOM
VCE(satl
(Terminal No. 81
v+ 30 V
IC = 50 rnA
Terminal No.6 grounded
Output Leakage Current
V+ = 30 V
(Terminal No.6 to
Terminal No. 41
Composite Small·Signal
Current Transfer Ratio (Beta)
(Q12 and 0131
Output Capacitance:
Terminal No.6
Terminal No.8
hie
Co
V+ - 30 V
VCE = 5 V
IC = 50 mA
f = 1 MHz
All Remaining
Terminals Tied to
Terminal No.4
2
IlA
100,000
5.5
17
pF
pF
TRANSFER PARAMETERS
Voltage Gain
Forward Transconductance
To Terminal No.1
Slew Rate:
Open Loop:
Positive Slope
Negative Slope
Unity Gain
(Non·lnverting,
Compensatedl
378
A
V+ = 30 V
IABC = 100 llA
IWout = 20 V
RL=2kS!
gm
SR
100,000
100
2200
V/V
dB
Ilmhos
IABC= 500 llA
RL = 2 kSl
500
50
VIlIS
VIlIS
IABC= 500/1A
RL = 2 kSl
0.7
VIlIS
File No. 692 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA3094, CA3094A, CA3094B Slash (I) Series
Table I - Pre Burn·ln Electrical and Post Burn·ln Electrical Tests. and Delta Limits'·
Test Conditions
Characteristic
Symbol
V+
Limits
= 30 V, IABC = 100 IlA
TA =250 C
Min.
Max.
Units
Max.
Input Offset Voltage
VjQ
-
5
±1
mV
Input Offset Current
110
-
0.2
±0.02
Il A
Input Bias Current
II
0.04
0.5
to.1
IlA
Forward Transconductance
To Terminal No.1
gm
1650
2750
±660
Ilmh O
-
0.8
±0.02
V
Collector·to·Emitter
Saturation Voltage
(Terminal
VCE(sat)
No.B)
IC =50 mA
Terminal No.6 grounded
* Levels IIN,/IR,/1, and 12 require pre and post burn-in electrical tests and delta limits.
Level/3 requires pre-burn in electrical test only. The burn-in circuit is shawn in Fig. 13.
Table II - Final Electrical Tests
Characteristic
Symbol
Test Conditions
V+ = 30 V, IABC = 100 IlA
Unless Otherwise Specified
Limits For Indicated Temperatures (DC)
-55
Input Offset Voltage
VIO
-
Input Offset Current
110
Input Bias Current
II
-
Forward Transconductance
To Terminal No.1
Input Offset Voltage Change
910
gm
I/\VIol
Minimum
+25 +125
-
-
16S0 18S0
Maximum
-55
+25
Units
+125
mV
7
5
7
0.85
0.2
0.22
I1A
3.2
O.S
1.1
IlA
2100 2750 4000
Ilmho
Change in VIO
between IABC = 100 I1A
and IABC = SI1A
-
-
-
-
8
-
mV
Change in VIO
between IABC = 100l1A
and IABC = ISI1A
-
-
-
3.2
-
3.2
mV
Peak Output Voltage
(Terminal No.6) with 013 "ON"
V+OM
26
26
26
-
-
-
V
Common Mode Rejection Ratio
CMRR
70
70
70
-
-
-
dB
Supply Current
I+Suppl y
-
-
400
400
400
IlA
-
-
-
ISO
ISO
150
I1VN
-
8
-
-
12
-
mW
-
-
-
0.8
0.8
1.0
V
Power Supply Rejection
Power Dissipation
Collector·to·Emitter
Saturation Voltage
(Terminal No.8)
RL = 2 kU to ground
/\VjQ//\V
Po
VCE(sat)
10M =0
IC= SOmA
Terminal No.6 Grounded
OPERATING CONSIDERATIONS
The "Sink" Output (terminal No.8) and the "Drive" Output
(terminal No.6) of the CA3094T are not inherently current
(or power) limited. Therefore, if a load is connected between
terminal No.6 and terminal No.4 (V-· or ground), it is
important to connect a current-limiting resistor between
terminal 8 and terminal No.7 (V+) to protect transistor 013
under shorted load conditions. Similarly, if a load is
connected between terminal No.8 and terminal No.7, the
current· limiting resistor should be connected between ter·
minal 6 and terminal No.4 or ground. In circuit applications
where the emitter of the output transistor is not connected
to the most negative potential in the system, it is recommended that a 100·ohm current·limiting resistor be inserted
between terminal No.7 and the V+ supply.
379
CA3094, CA3094A, CA3094B Slash (/) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 692
Table III - Group A Electrical Sampling Inspection
Characteristic
Symbol
Test Conditions
V+ - 30 V. IABC - 100 pA
Unless Otherwise Specified
Input Offset Voltage
VIO
Input Offset Current
',0
II
Input Bias Current
Forward Transconductance
To Terminal No.1
Input Offset Voltage Change
+25 +125
-
-
910
Units
Maximum
Minimum
-55
-
gm
I"VIOl
Ljmits For Indicated Temperatures (OC)
+25
-55
-
+125
7
5
7
mV
0.85
0.2
0.22
/lA
3.2
0.5
1.1
/lA
2100 2750 4000
1650 1850
/lmho
Change in VIO
between IABC = 100 /lA
and IABC = 5/lA
-
-
-
-
8
-
mV
Change in V,O
between IABC = 100/lA
and IA8C = 15/lA
-
-
-
3.2
-
3.2
mV
26
26
26
-
-
-
V
Peak Output Voltage
(Terminal No.6) with 013 "ON"
V+OM
Common Mode Rejection Ratio
CMRR
70
70
70
-
-
-
d8
Supply Current
I+Supply
-
-
-
400
400
400
/lA
150
150
150
/lVN
-
-
-
0.8
0.8
1.0
V
0.1
0.1
0.1
/lA
-98
"":98
-98
mA
Power Supply Rejection
RL = 2 kU to ground
fWIO/fW
Collector-ta-Emitter
Saturation Voltage
(Terminal No.8)
Output Leakage Current
QI3"OFF"
IC = 50mA
VCE(sat)
Terminal No.6 Grounded
-IOL
V+=25V
-10M
IA8C= 15/lA
-10
-10 -10
Max. Output Current
QI3"ON"
-140 -140 -140
Table IV - Group C Electrical Characteristics Sampling Tests (TA = 250 C)
Characteristic
Input Offset Voltage
Input Offset Current
Forward Transconductance
to Terminal No.1
Peak Output Voltage
(Terminal No.6) with 013 "ON"
380
TEST CONDITIONS
V+ - 30V. IABC = 100/lA
Unless Otherwise Specified
LIMITS
Min.
Max.
Units
-
5
mV
110
0.25
/lA
gm
1420
3350
/lmho
25
-
V
Symbol
V,O
+VOM
Supply Current
I+Supply
Output Leakage Current Q13 "OFF"
-IOL
Max. Output Current Q13 "ON"
-10M
RL = 2 kU to ground
V+ = 25 V
IA8C=3pA
-
400
-15
-
/lA
/lA
-
-45
rnA
II)
File No. 692 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA3094, CA3094A, CA3094B Slash
I
SUPPLY VOLTS:V+-:+l5, V-"-15
I
I
10 36 SUPPLY VOLTS: V t :H5, V-:-15
I
+9
v
I -55°C
~
~
.'"
10•
w
I
~
0.1
w
~
w
0 1 \ +70
~ ~r~_2~5_90+lrt+--r~-+1+_+--r~4--5_5+._c_+~a41~7H
~ -3r--r~-++t-r--r+4+--+-~44-+--r~H
o -4~/~M-~+#-f--+H~-H~
I
+12.5"C
~_ -5r-~-+-++t--r--r+4+--+-~44-+--r~H
-6
/
.~
~
)/
,
0.01
468
0.1
Series
468
1
10
100
AMPLIFIER BIAS MICROAMPERES (rABe)
•
4
68
4 6 B
I
10
100
AMPLIFIER BIAS MICROAMPERES I IABCI
0.1
466
1000
4
6 B
1000
92CS-L15S9
'32CS-17588
Fig.3 - Input offset current vs. amplifier bias current
(lASe. terminal No.5J.
Fig.2 - Input offset voltage vs. amplifier bias current
(IABe, terminal No.5).
10 46 SUPPLY VOLTS:V+.+15,V-"'-15
~
10 56
4 AMBIENT TEMPERATURE {TA)"25°C
••
!:!
~
~ 10'•
g •
.iDII 10 ••
." "•f--+~$t~;/"'--t-+-H+---1\- +_;5.25·Clc"+--+--+--+I
.-:/
;!;
~
Q.
I
0.1
./
/'
·
4
:p
·
~
,
.I
~ 10 4
103
:·.......
o
4
if.
2
~
iii 10 2
~
0.1
468
1000
V
.\~~.~ ..( ~~"
l::::=c=:: cY. .~'i." ~"' .. If .. "'""'J~
5 ~ ~~~
w
I-;,"Y
" 10• /
I
466
468
468
0.88f1A I
10
100
AMPLIFIER BIAS MICROAMPERES t lABel
.....
~v
..~
2
~ 10 3
Z
•
·;v. ..
4
0.1
f7c':~
.....-
,
4
.. , ... .
9ZCS-Z0385
92.CS-20414
Fig.4 - Input bias current vs. amplifier bias current
Fig.5 - Device dissipation vs. amplifier bias current
(IASC, terminal No.5),
(lABe, terminal No.5).
·
lot
«
f
SUPPLY VOLTS:V
"'+15,V-"'-15
,I.Hii+Z5~
Ik~!c
2
-- 10 3
•
~!5 •
"
~
-55"C
.·•
10 2
w
\'~5.C·-
i
..df'
~
...'"..~
\'\~
.~
'!J.
:::E
!:l' •
4681
1000
I
10
100
AMPLIFIER BIAS CURRENT UABCI-JLA
vs. amplifier bias current
-15
0-1
2
468
46B
468
I
10
100
AMPLIFIER BIAS CURRENT UABC 1-p.A
4
,.
1000
9ZCS-Z0381
Fig. 7 - Common mode input voltage vs. amplifier bias current
flASe, terminal No.5),
381
CA3094, CA3094A, CA3094B Slash (II Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 692
103
102
10
104
IO!!i
(f I-Hz
FREQUENCY
106
468
107
0.1
468
1000
9ZCS-17599
92CS-20392
Fig. 8 - Open-loop voltage gain vs. frequency.
SUPPLY VOLTAGE IV 1=+15V;IV-}s-J5V
AMBIENT TEMPERATURE (TAl =25 D C
FOR TEST CIRcurr, SEE FIG. 23
468
I
10
100
AMPLIfiER alAS MICROAMPERES (IABC)
Fig. 9 - Forward transconductance vs. amplifier bias current.
lODe SUPPLY VOLTAGE (vtl;+I~Vi tV-l~-15V
6 AMPLIFIER BIAS CURRENT tIABCl=500p,A
4 AMBIENT TEMPERATURE (TAl; 25°C
FOR TEST CIRCUIT SEE FIG. 24 ~
v
b-l""":::r:---j
1.7
~I 10B'I=~::::::=±=±=tt:::::::--tl---=td=fj::::::=±::::::--=tI-=tjj
7
~ ,~~~~~_I ___ .~/~I.7___~_~~I-.-+__-+-+-+"
S
4
~
I
•
"
~1.7
0.1
nl
4
6
e
10
4
6
BIOO
4
6
BlOOD
100
20
40
60
80
CLOSED-l.OOP VOLTAGE GAIN (ACLl- dB
92CS-20394
AMPLIFIER BIAS CURRENT (IABC)-,.A
92C5-20393
Fig. 10 - Slew rate vs. amplifier bias current.
Fig. 11 - Slew rate vs. closed-loop voltage.gain.
+15 V
II TO FOLLOWING UNITS
UNDER TEST
~
W
W
~
~
W
CLOSED-LOOP VOLTAGE GAIN (ACLI- dB
70
92CS-20395
10k
-15V
Fig. 12 - Phase compensation capacitance and resistance vs.
closed-loop voltage gain.
4700 pF
92CS-22730
Fig. 13 - Burn-in and life-test circuit.
382
File No. 825
OOCI8LJD
Linear Integrated Circuits
Monolithic Silicon
Solid State
Division
High-Reliability Slash (I) Series
CA31001 ...
High-Reliability
Wideband Operational Amplifiers
< .~
L~)
i,I:' \
i,:, I'" I
ili"" \
",
8-LEAOTO·5
with Dual-I n-Line
Formed Loads
8-LEAOTO·5
("T"Suffix)
("S" Suffix)
H-1787
H-1528
For Applications in Aerospace, Military, and Critical
I ndustrial Equipment
Features:
.. High unity-gain crossover frequency (tr) - 38 MHz typo
.. Wide power Bandwidth - Vo = 18 V p.p typo at 1.2 MHz
.. High slew rate - 70 VIlls (typ.) in 20 dB amplifier
25 VIlls (typ.) in unity·gain amplifier
.. Fast settling time - 0.6 IlS typo
" High open·loop gain at video frequencies - 42 dB typo at 1 MHz
" Single capacitor compensation
II High output current - ±15 mA min.
" LM118, 748/LM101 pin compatibility
II Offset null terminals
The RCA-CA3100S, CA3100T Slash II) Series types are
high-reliability large-signal wideband, high-speed operational
amplifiers intended for applications in aerospace, military,
and industrial equipment. They are electrically and mechanically identical with the standard type CA3100 described in
Data Bulletin File No. 625 but are specially processed and
tested to meet the electrical, mechanical and environmental
test methods and procedures established for microelectronic
devices in MIL-STD-883.
The packaged type can be supplied to six screening levels 1N, 11 R, 11, 12, 13, and 14 - which correspond to
MIL-STD-883 Classes A, B, and C. The chip version can be
supplied to three screening levels - 1M, IN, and IR. These
screening levels and detailed information on tests methods,
procedures and test sequence are given in Reliability Report
RIC-202A "High-Reliability CA3000 Slash II) Series Types
Screened to MI L-STD-B83".
Applications:
.. Video amplifiers
" Fast peak detectors
" Meter-driver amplifiers
" Video pre-drivers
II Oscillators
II Multivibrators
" High-frequency feedback amplifiers
The CA3100S and CA3100T have a unity gain crossover
frequency (tr) of approximately 38 MHz and an open-loop,
3 dB corner frequency of approximately 110 kHz. They can
operate at a total supply voltage of from 14 to 36 volts (±7
to ±lB volts when using split supplies) and can provide at
least 18 V Pop and 30 mA POp at the output when operating
from ±15 volt supplies. The CA3100 can be compensated
with a single external capacitor and has dc offset adjust
terminals for those applications requiring offset null.
The CA3100 circuit contains both bipolar and P-MOS
transistors on a single monolithic chip.
The CA3100 is supplied in either the standard B-Iead TO-5
package (T suffix), in the S-Iead TO-5 dual-in-line formedlead "DI L-CAN" package (S suffix). or in chip form (H
suffix)_
9-74
Fig. 1-Functional diagram of CA3100S, CA3100T.
383
CA31 00 Slash (II Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 825
Maximum Ratings. Absolute-Maximum Values at TA ~ 25"C:
Ambient Temperature Range:
Operating .••••..••.••••••.•.•.••••••.• -55 to +l25°C
Storage • . • . • • . . • • • • • • • . . • • • • • • • • • • • •. -65 to +150oC
Lead Temperature (During Soldering):
At distance 1/16 ±lf32 inch 11.69 ±o.79 mm)
from case for 10 s max. • J • • ;. • • • • • • • • • • • • •• 300
°c
• If supply voltage is less than ±Is volts. the maximum input voltage
to ground is equal to the supply voltage
.CA3100S, CA3100T does not contain circuitry to protect against
short circuits in the output.
v
Supply Voltage (between V+ and V- terminals)
Differential Input Voltage •..... ,".•.•..... ::: :: :
Input Voltage to Ground· ••••••• • • • • • • • • • • . • • • •
36
±12
±15
Offset Terminal to V- Terminal Voltage..... •....•
±a.S
V
V
V
Output Current .•.••••..••••.••••.•.••.•..•..
Device Dissipation:
UptoTA=55°C ..........................
Above T A '" sSOC Derate linearly at ...........
50
mA-
630
6.67
mW
mW"C
ELECTRICAL CHARACTERISTICS. At TA ~ 25"C: For Design Guidance
CHARACTERISTIC
SYMBOL
TEST CONDITIONS
SUPPLY VOLTAGE (V+.V-}=15V
UNLESS OTHERWISE SPECIFIED
TYP.
UNITS
STATIC
Input Offset Voltage
VIO
Input Bias Current
liB
Input Offset Current
110
VO=O±O.1 V
VO=O±1 V
Low·Frequency
Open· Loop Voltage Gain-
AOL
Vo = ± 1 V Peak, f
Common·Mode Input
Voltage Range
VICR
CMRR;;' 76 dB
Common·Mode
Rejection Ratio _
CMRR
VI Common Mode = ±12 V
Maximum Output Voltage
Positive
Negative
Maximum Output Current
Positive
Negative
Power·Supply
Rejection Ratio
1 kHz
mV
/lA
±0.05
J1A
61
dB
+14
-13
90
VOM+
Differential Input Voltage = 0 ±0.1 V
+11
VOM
RL =2 KU
-11
10M+
Differential Input Voltage = 0 ±0.1 V
+30
10M-
RL~250U
-30
1+
Supply Current
~
±1
0.7
PSRR
Vo = 0±0.1 V. RL;;'10 KU
V
dB
V
mA
8.5
mA
70
dB
0, Vo = 0.3 V (P·P}
38
MHz
~
42
dB
6V+~±IV.6V-=±IV
DYNAMIC
Unit·Gain
Crossover Frequency
f,-
I-MHz Open·Loop
Voltage Gain
AOL
Slew Rate:
20-dB Amplifier
SR
Cc
~
f = 1 MHz. Cc
AV = 10.
O. Vo = 10 V (P·P}
Cc = 0, VI
= 1 V (Pulse}
AV = 1, Cc = 10 pF. VI ~ 10 V (Pulse}
Follower Mode
Pdwer BandwidthA:
20-dB Amplifier
PBW
Follower Mode
70
AV = 10, Cc = O. Vo = 18 V (P·P}
1.2
AV-l.CC-l0pF, VO= 18V (P·P}
0.4
Open· Loop Differential
I nput Impedance
21
f
~
1 MHz
30
Open· Loop
Output Impedance
Zo
f
~
1 MHz
110
Wideband Noise Voltage
Referred to Input
Settling Time
GTO Within ±50 mV of 9 V]
Output Swing
.
Slew Rate
.. Power BandWIdth "" "Va (P_P)
384
•
eN (Totall
BW= 1 MHz, RS= 1 KU
ts
RL = 2 KU, CL = 20 pF
Low-frequency dynamic characteristic
V//lS
25
8
0.6
MHz
KU
U
/lVRMS
Il S
File No. 825
- - - - - - - - - - - - - - - - - - - - - - - CA3100 Slash (II Series
v+
R4
7500
RS
750n
R.
12K
NON-INVERTING
INPUT
+
RI.
150 n
RI7
600n
RI9
600
RIB
150 n
n
OFFSET
NULL
V-r4!)-~----~----~----~------------~--------~----------~------------~--"
AND
PHASE
COMPENSATION
92CM-21655RI
Fig. 2-Schematic diagram for CA3100.
Table I. Pre Burn·in Electrical and Post Burn·in Electrical Tests. and Delta Limits. o
ELECTRICAL CHARACTERISTICS. at TA = 25"C.
CHARACTERISTIC
TEST CONDITIONS
MIN.
LIMITS
MAX.
MAX.!'.
UNITS
5
±1
rnV
400
±40
nA
Vo = O±lV
-
2
±0.5
Vo =O±lV
-
10.5
±1.5
/1 A
rnA
Input Offset Voltage
VIO
VO=O±O.l V
Input Offset Current
110
VO-O±lV
Input Bias Current
liB
1+
Supply Current
•
SYMBOL
v+ = 15V. V- =-15V
Levels 11 and 12 require pre burn-in electrical and post burn-in electrical tests and delta limits.
Lavelt3 requires pre burn-in electrical test only. The burn-in and operating life test circuit is shown in Fig. 9
385
CA3l00 Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 825
Table II. Final Electrical Tests and Group A Sampling Inspection
CHARACTERISTIC
TEST CONDITIONS
LIMITS
SYMBOL SUPPLY VOLTAGE (V+,V-I=15V
MINIMUM
. MAXIMUM
UNITS
UNLESS OTHERWISE SPECIFIED 1-55/+251+125
-55 1+25 1 +1251
STATIC
Input Offset Voltage
Input Bias Current
Input Offset Current
VIO
liB
110
VO=O±O.l V
-
VO=O±l V
-
-
-
Low-Frequency
Open-Loop Voltage Gaine
AOL
Vo =±1 V Peak
50
56
50
Common-Mode Input
Voltage Range
VICR
CMRR;;> 76 dB
-
±12
Common-Mode
Rejection Radio
CMRR
VI Common Mode = ±12 V
-
Maximum Output Voltage
Positive
Negative
VOM+
VOM
Differential Input Voltage =O±O.lV
RL= 2Kn
+9
-9
Maximum Output Current
Positive
Negative
6
5
6 mV
4
2
2 IlA
1000 400 600 nA
-
-
-
dB
-
_.
-
-
V
76
-
-
-
-
dB
+9
-9
+9
-9
-
-
-
V
-
-
mA
IOM+
Differential Input Voltage = O±O_lV
+15 +15 +12
-
RL=250n
-15 -15 -12
VO=O±O.lV.RL;;>lOKn
-
-
-
Supply Current
10M1+
-
Power Supply
Rejection Ratio
PSRR
6.V+ = ±1 V, 6.V- = ±1 V
60
60
60
-
-
-
dB
AOL
f = 1 MHz, Cc = 0, Vo = 10 V (P-P)
-
36
-
-
-
-
dB
AV = 10, CC=O, VI = 1 V (Pulsel
-
50
-
-
-
-
V/p.s
AV = 10, Cc = 0, Vo = 18 V (P-PI
-
0.8
-
-
-
-
MHz
10.5 10.5 10.5 mA
DYNAMIC
l-MHz Open-Loop
Voltage Gain
Slew Rate:
20-dB Ampl ifier
SR
Power Bandwidth .:
20-dB Amplifier
•
Po
wer
PBW
Ba dw·dth = Slew Rate
n I
'lNO (P_P)
•
Low-frequency dynamic characteristic
Table III. Group C Electrical Characteristics Sampling Tests
V+=+15V
CHARACTERISTIC
SYMBOL
SPECIAL
TEST CONDITIONS
LIMITS
UNITS
MIN.
MAX.
5
400
nA
2
IlA
Input Offset Voltage
VIO
VO=O±O.l V
-
Input Offset Current
110
Vo =0±0.1 V
Input Bias Current
II
Vo =0±0.1 V
-
Large-Signal
Voltage Gain
AOL
Vo = ±lV Peak
56
1+
VO=O±O.l V
-
Supply Current
386
V-=-15V
10.5
rnV
d8
rnA
File No. 825 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA3100 Slash (II Series
TYPICAL CHARACTERISTICS CURVES
~
I
5 60
C'o~
"""".0
~ 40
r,
~ 30
20 1-10
0
0.001
~
ill
pf
t
~o
~
~'l,tJ,Qi
0
• B.
2
QI
.Be
• B.
2
10
~
Q.
0
~
~
."100
2
~
401- -
w
-
"I)JI
~
'0
-270~
.'l,Arlc~
2
~
s
pF -225 ~
-160 (I)
-135 ~
-90
-45
-- -
60
I'"
z
~
12pF
0
."001
2
w
w
0
{:I.t)~~
v~..
l';
~
0..
£.>\e.~-"
~
LOAD RESISTANCE tRLI.2 Kn
LOAD CAPACITANCE (CL1220 pF
OMPENSATION CAPACITANCE (Ccl=
~
~"l
~~~~
~0~
~\
\'
III
"0.1
25
~ 20
II
II
-
10
2
in
z
"'"
0
.
U
~.,.
-
92C5-21572
g
--
~
0001
I
m
~
30
100
AMBIENT TEMPERATURE (TA)-25°C
LOAD RESISTANCE {RL)22 Kn
J,..OAD CAPACITANCE (CL)-20pF
~
1l.1
I- - -
l';
is
t' ~,.lJt=
'<'l......
40
~
2
Fig. 4-0pen-loop gain vs. frequency and
supply vo/rage.
SUPPLY VOLTAGE (V I V-"15 V
COMPENSATION CAPACITANCE (Cc)-O
LOAD RESISTANCE IRLI-Z KG
I- -
z
1
• B.
10
2
i
~\
• B.
~lto,i~}-
"
'6('4Qi
10
("~h
"'·'8"
5
10V
10
10
20
NONINVERTING GAIN-dB
0
FREQUENCY !f1-MHz
19.1
6
INVERTING GAIN -
92CS-21:i71
dB
CLOSED-LOOP GAIN (ACLI-dB
92C5-21573
Fig. 5-0pen-loop gain vs. frequencvand
temperature.
Fig. 6-Requ;red compensation capacitance
vs. closed·loop gain.
2. AMBIENT TEMPERATURE (TAI 22S·C
SUPPLY VOLTAGE (V~ V-I.IS V
>
I
1
I
20
w
1\
~
~
~
~
6
15
g
~
(FOLLOWER)
10
Fig. 7-Slew rare vs. compensation
capacitance.
pF
9ZCS-ZI~74
1\
5
0
0.01
COMPENSATION CAPACITANCE (Ce' PINS I TO 9 -
\
C~~~~~ ~
~
'l-
2
•
6
II
I~'RCU'T
FI~_'20
lOX AMPL
t
.
\
,1"r-. ~
B• I
FREQUENCY III-MHz
92C5-21582
Fig. 8-Maximum output voltage
swing vs.. frequency.
387
CA3100 Slash
II) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
-12V
92CS-24703
Fig. 9-Ufe test and burn-in circuit.
388
File No. 825
File No. 830 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
D\lCIBLlO
Linear Integrated Circuits
Solid State
Division
High-Reliability Slash (I) Series
CA31181 ..., CA3118AI ...
,
I
II'
Monolithic Silicon
High-Reliability
High-Voltage Transistor Arrays
For Applications in Aerospace, Military, and Critical Industrial Equipment
Applications:
• General use in signal processing systems in DC through VHF range
•
Custom designed differential amplifiers
• Temperature compensated amplifiers
Features:
12-Lead TO..s
H-1463
•
•
..
•
Matched general-purpose transistors
VBE matched ±5 mV max .
Operation from DC to 120 MHz (CA3118AT, TI.
Low-noise figure: 3,2 dB typ, at 1 kHz (CA3118AT. T).
The CA3118T and CA3l18AT Slash (I) Series types are
high-reliability, general·purpose silicon n·p-n transistor arrays
on a common monolithic substrate. They are intended for
applications in aerospace, military and industrial equipment.
They are electrically and mechanically identical with the
standard type CA3ll8 described in Data Bulletin File No.
532 but are specially processed and tested to meet the
electrical. mechanical and environmental test methods and
procedures established for microelectronic devices in MILSTD-883.
The packaged type can be supplied to six screening levels 11 N, 11 R, 11, 12, 13, and 14 - which correspond to
MI L-STD-883 Classes A, B, and C. The chip version can be
supplied to three screening levels - 1M, IN, and IR. These
screening levels and detailed information on test methods,
procedures and test sequence are given in Reliability Report
RIC-202A "High-Reliability CA3000 Slash (I) Series Types
Screened to MI L-STD-883".
Types CA3ll8AT and CA3ll8T consist of four transistors
with two of the transistors connected in a Darlington
configuration. These types are well su ited for a wide variety
of applications in low-power systems in the DC through VHF
range. Both types are supplied in a hermetically sealed
12-lead TO-5 type package, ("T" suffix), and in chip form
("H" suffix), and operate over the full military temperature
range. (CA3ll8AT and CA3ll8T are high-voltage versions of
the popular predecessor type CA30l8.)
The types with an "A" suffix are premium versions of their
non-"A" counterparts and feature tighter control of breakdown voltages making them more suitable for higher voltage
applications.
For detailed application information, see companion Application Note, ICAN-5296 "Application of the RCA CA3018
Integrated Circuit Transistor Array."
S
~;~
Q2P3
8
5
~Q71
SUBSTRATE
010
92CS-23843
CA3118AT,CA3118T
Fig. I-Schematic diagram.
9-74
389
CA3118, CA3118A Slash
II) Series
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 830
MAXIMUM RATINGS,Absolu~Maximum Values at TA = 2fiOC
POWER DISSIPATION:
Anyone transistor CA311BAT,CA311BT •••••••••••••••.••••••••.•••••••••••••••.••••••
Total package Up to B5DC (CA311BAT, CA311BT) •••••••.•••..••.•••••.•.•••.••••••••••.
Above BSOC (CA311BAT, CA311ST) •••.•••.•.••••••••••••••••••••••••••••
AMBIENT TEMPERATURE RANGE:
Operating CA311 BAT, CA3118T ••••••••••••••••••••••••••••••••.•••••••.••••••
Storage (all types) . • • • • • • • . • • • • • • • • • • • . • • • • • • • • • • • • . • • • • . . • . . • • • • • . • ••
THE FOLLOWING RATINGS APPLY FOR EACH TRANSISTOR IN THE DEVICE:
Collector·to-Emitter Voltage (VCEO):
CA311SAT •••••••••••••••••••••••••••••••••••••••..••..••••••...
CA3118T •••••.••••••••.•.•••••••••••.•..••••••••••••••••••••••
Coliector·to·Sa.. VDltaga (VCSO):
CA311SAT ••••••••••••••.•••••••••••••.•••••••••.••••..•.•.•.••
CA311ST
•••••••••.•••••••••••••••••••••.•••.•••.•••.•••••••••
Coliector·tO-Substr.te Voltage (VCIO):·
CA311SAT ••••••••••••••••••.•••••••••••••••••••.•••...••..•..•
CA3118T
•••••••••••••••••••••.•••.•.•••••••••••••.•••••••••••
EMITTER·TO·SASE VOLTAGE (VESO) all types •••••••••••••••••••••••.•.•.•.•••.
300
450
derate linearly 5
mW
mW
mWfDC
-55 to +125
-55 to +150
DC
DC
40
30
V
V
50
40
V
V
50
40
5
V
V
V
50
mA
Collector Current CA311SAT, CA3118T .•••••••••••••••••..••••••••••••••••••••••.••••
Wfhe collector of each transistor is isolated from the substrate by an integral diode. The substrate must be connected to a voltage wh ich is more
negative than any collector voltage in order to maintain isolation between transistors and provide normal transistor action. To avoid undesired
coupling between transistors. the substrate terminal should be maintained at either DC or signal (AC) ground. A suitable bypass capacitor can be
used to estabfish a signal ground.
390
File No. 830 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CA3118, CA3118A Slash (I) Series
STATIC ELECTRICAL CHARACTERISTICS For Design Guidance Only
TEST CONDITIONS
CHARACTERISTIC
SYMBOL
TA = 25°C
Typ.
Char.
Curve
Fig.No.
Typ.
Values
UNITS
For Each Transistor:
Collector·to·Base
Breakdown Voltage
Collector·to·Emitter
Breakdown Voltage
V(BRICBO
V(BRICEO
IC= 101lA,IE=0
-
72
V
IC= lmA,IB=O
-
56
V
72
V
V
Collector·ta-Substrate
Breakdown Voltage
V(BRICIO
ICI = IOIlA,IB = 0
IE=O
-
Emitter·to·Base
Breakdown Voltage
V(BRIEBO
IE= 10IlA.IC=0
-
7
see
Collector·Cutoff Current
ICEO
VCE= 10V,IB=0
2
Collector·Cutoff Current
ICBO
VCB=10V,IE=0
3
0.002
4
4
4
85
100
90
DC Forward·Cu rrent
Ilc=10mA
IIC-l mA
llc= 10llA
~"'v.
IIA
nA
hFE
VCE=5V
Base·to·Emitter Voltage
VBE
VCE=3v,lc=lmA
-
0.73
V
Collector·to·Emitter
Saturation Voltage
VCEsat
IC= 10mA.IB= lmA
5
0.33
V
IIA
Transfer Ratio
For transistors 03 and 04 (Darlington Configuration):
Collector·Cutoff
ICEO
VCE= 10V,IB=0
-
-
DC Forward·Current
Transfer Ratio
hFE
VCE = 5V,IC= 1 rnA
6
9000
Base·to·Emitter
(03 to 041
VBE
VCE=5V
.7
7
1.46
1.32
-
4.4
mV"C
VCE = 5V. IE = 1 rnA
-
0.48
mV
VCE= 5V,
ICI = IC2 = lmA
-
1
Curr~nt
Magnitude of Base·to·
Emitter Temperature
Coefficient
16~~EI
IIE=10mA
liE 1 rnA
VCE = 5V. IE = 1 rnA
V
For transistors 01 and Q2 (As a Differential Amplifier):
Magnitude of Input
Offset Voltage
IVBE1 - VBE21
Magnitude of
hFE
IVlol
Magnitude of Base·to·
Emitter Temprature
Coefficient
16~~EI
VCE= 5V,
IE= lmA
-
1.9
mV/oC
Magnitude of VIO
(VBE1- VBE2) Temp·
erature Coefficient
1:~101
VCE=5V,
ICI = IC2 = lmA
-
1.1
IlV/OC
391
CA3118, CA3118A Slash (I) Series
File No. 830
DYNAMIC ELECTRICAL CHARACTERISTICS For Design Guidance Only
CHARACTERISTIC
SYMBOL
Low Frequency Noise Figure
NF
Low·Frequency, Small·Signal
Equivalent·Circuit
Characteristics:
Forward·Current Transfer
Ratio
hfe
TEST CONDITIONS
Typ.
Char.
Curve
TA=250 C
Fig. No.
CA3118AT
UNITS
Typ.
Typ.
3.25
3.25
8
100
100
f=lkHz, VCE=5V,
IC = 100 /lA, Source
resistance = kU
f= 1kHz, VCE =5V,
Ic=lmA
CA3118T
dB
Short·Circuit Input
Impedance
hie
8
3.5
2.7
kU
Open-circuit Output
Impedance
hoe
8
15.6
15.6
/Lmho
Open·Circuit Reverse
Voltage Transfer Ratio
h re
B
1.8 x 10.4
Admittance Characteristics:
Forward Transfer Admittance
Yie
Output Admittance
Yoe
Reverse Transfer Admittance
Vre
Gain·Bandwidth Product
9
31·jt.5
3t·jl.5
mmho
f= lMHz, VCE = 5V,
Ic=lmA
10
0.3+ jO.04
0.35 + jO.04
mmho
11
0.001 + jO.03
0.001 + jO.03 mmhci
12
See curve
See curve
mmho
VCE = 5V, IC = 3mA
13
500
500
MHz
Yfe
Input Admittance
fT
t.B x 10.4
Emitter·to·Base Capacitance
CEB
VEB=5V,IE=0
14
0.70
0.70
pF
Coliector·to·Base Capacitance
CCB
VCB = 5V, IC = 0
14
0.37
0.37
pF
Collector·to·Substrate
Capacitance
CCI
VCI = 5V,lc= 0
14
2.2
2.2
pF
Table I. Pre Burn-ln Electrical and Post Burn·ln Electrical Tests and Delta Limits"
ELECTRICAL CHARACTERISTICS, at TA = 2!PC
LIMITS
CHARACTERISTIC
Emitter·to·Base Breakdown
Volts 01,02
SVMBOL
V(BR)EBO
TEST CONDITIONS
5
IE=10/LA,IC=0
Collector Cutoff Current
01,02
ICEO
VCE= 10V,IB=O
Collector Cutoff Current
03,04
ICEO(D)
VCE= tOV,IB=O
*
MIN.
MAX.
-
MAXI'
UNITS
±0.5
V
-
5
±1
/LA
/lA
±1
II
IC = 1 mA, VCE = 5 V
-
5
Input Current Ot, 02
33
±3
/LA
Input Current 03, 04
11(0)
IC = 1 mA, VCE = 5 V
-
0.66
±0.1
/LA
Base to Emitter Voltage
01,02
VBE
IE= 1 mA, VCE=3V
0.63
0.83
±0.1
V
Levels /1 and /2 require pre burn-in electrical and post burn-in electrical tests, and delta limits.
Level /3 requires pre burn-in electrical test only. The burn-in and operating life test circuit is shown in Fig, 15.
392
File No. 830 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CA3118,CA3118ASIash (II Series
Table II Final Electrical Tests and Group A Sampling Inspection
CHARACTERISTIC
SYMBOL
TEST CONDITIONS
LIMITS
NOTE - Unless otherwise
specified, limits apply
MINIMUM
MAXIMUM
to both CA3118 and
CA3118A
+25 +125 -55
·55
+25
+125
UNITS
For Each Transistor:
-
-
-
-
30
40
-
-
-
40
-
-
-
50
-
-
-
5
-
-
CA3118
CA3118A
-
IC= 1 mA
IB =0
CA3118
CA3118A
V(BR)CIO
ICI = lOIlA
IB = 0
IE = 0
CA3118
V(BR)EBO
IE = lO IlA,I C =O
V(BR)CBO
Collector-to-Emitter
Breakdown Voltage
V(BR)CEO
Collector-to-Substrate
Breakdown Voltage
Emitter-to-Base
Breakdown Voltage
40
50
IC= 101lA
IE = 0
Collector-to-Base
Breakdown Voltage
CA3118A
-
-
-
V
-
V
-
-
V
-
-
5
100
Il A
100
mA
-
-
-.
V
Collector-Cutoff Current
ICEO
VCE =10V,I B =0
ICBO
VCB = 10V, IE=O
-
-
Collector-Cutoff Current
-
-
DC Forward-Current
Transfer Ratio
hFE
VCE = 5 V, IC = 1 mA
15
30
40
-
Base-to-Emitter Voltage
VBE
V CE =3V,I C = 1 mA
_7
0.63
0.43
1.3
0.83
0.73
V
IlA
-
For transistors Q3 and 04 (Darlington Configuration):
Collector-Cutoff Current
DC Forward-Current
Transfer Ratio
-
-
-
2000
1500
2000
-
5
750
-
-
VCE =5V,I E =lmA
-
-
-
-
5
-
VCE =5V,
ICl = IC2 = 1 mA
-
0.9
-
1.1
-
VCE = 5 V, IC = 3 mA
-
300
-
-
-
ICEO
V CE = 10 V, IB = 0
hFE
VCE =5V, Ic= 1 mA
For transistors 01 and 02 (As a Differential Amplifier):
Magnitude of Input
Offset Voltage
IV BE1 - VBE2 1
IVlol
Magnitude of hFE
mV
Dynamic Characteristics:
Gain Bandwidth Product
fT
-
MHz
393
CA3118, CA3118A Slash (II Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
File No. 830
Table III. Group C Electrical Characteristics Sampling Tests ITA = 250 CI
LIMITS
MIN.
MAX.
UNITS
IE=10/LA.IC=0
4
-
V
V(BRICEO
IC = 1 rnA, IB = 0
28
-
V
liN
IC= 1 rnA, VCE= 5V
-
50
/LA
/LA
V
CHARACTERISTIC
SYMBOL
TEST CONDITIONS
Emitter·to·Base Breakdown Volts,
01,02,03. <4
V(BRIEBO
Coliector·to·Emitter Breakdown
Volts. 01. 02,03. <4
Input Current. 01, 02
Input Current. Darlington Pair,
03. 0 4
IIN(DI
IC= 1 rnA. VCE = 5V
-
1
Base·to·Emitter Voltage, 01, 02
VBE
IE=1mA,VCE=3V
0.63
0.83
STATIC CHARACTERISTICS CURVES
IO~~
I02~
BASE CURRENT (:t8)-0
•,
".:#=
10'
I
~
,•
I
S
-5
~
eIi!
t,-fj/
·,
0
i::
I
..
',"
...
u
••
~
,~"///
~~'l
",tf
",&'7//
/'/'
~ 10'
0
::l
8
'//
"...,-/ /
2
10" •
·,
:-/
0
10-3
0
10'
u
///
10" •
2.
10-4
100
15
50
I 5
o
AMBIENT TEMPERATURE (TA)-'"C
COLLECTOR-TQ-EMITTER VOLTAGE tVeE) =5 V
AMBIENT TEMPERATURE (T AlIE 12SoC
i
140,..,
ffi
120
~
...a!
100
§ 80
~I
Ii!
60
eg
40
-
0.01
I
•
6 • 0.1
, •
I
4
8 8 1
COLLECTOR CURRENT (Ic)-mA
92CS-19648
Fig. 4-hFE VI'. Ie for any transistor.
394
""",
---
J..lc
2
~
--..,"
I
20
75
100
125
AMBIENT TEMPERATUREtTA )=25-C
.......
25·C
~
50
Fig. 3-ICBO VI. TA for any transistor.
Fig. 2-ICEO vs. TA for any trans/nor.
0
25
AMBIENT TEMPERATURE (TA )-'"e
92CS-15194
~160
~oV
~
2
fo
&"7/
,
•
~
",.
..,-z~c ~~
/
2
"'W/
CJ
•
ffi
u
6
8::l
u
§
~
lole
1
..
I
77
... I.0
~/
I.
/
·
':!
!:!
~
~ ,•
10
"0
,€"
~ 10e
~
'/.,
EMITTER CURRENT (I ~}-O
•2
/.
6 8 10
~
~>
::II
1.5
1.25
""0-
~~
1.0
:IE"
b~
~~
~g
~
8
0.75
0.5
0.25
o
10
20
30
COLLECTOR CLRRENT CIc)-mA
40
9US-19847
Fig. 5-VCESBtvs.lcforany trans/ltOr.
File No. 830 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
!I)
CA3118, CA3118A Slash
Series
STATIC CHARACTERISTICS CURVES (Cant'd)
1.7
COLL.ECTOR-lO-EMITTER VOLTAGE IVCE)=5V
2
~
II
14K
!.-p",
I I_,
AMBIENT TEMPERATURE (TAI-2S·C
I..
>-
~~
~~IOK
!iii!
0:"
,,,,
uz
~~ 6K
0:0:
~e
~
-
-
~I-
....Si~
ffi~ /.5
25~C
......
,....V
"'''
IZ
~~ 1.4
at~
CD~
-55"C
I..
4
0.01
••
4
0.1
/
6.
68,
0.1
10
I
.,/
V
u
2K
V
/
V V
l:ja
4K
a
V
!J~
~'"
~~ BK
COLLECTOR-lO-EMITTER VOLTS (VeE) ~~v
6810
EMITTER MILLIAMPERES (IE)
COLLECTOR CURRENT IIC1-mA
92CS-19645
92CS-I!5183RI
Fig. 6-hFE VI, Ie for Darlington pair
(03 and 04) for types CA3118AT
and CA3118T.
Fig. 7-VSE vs.IEfor Darlington pair
(03and04).
TYPICAL DYNAMIC CHARACTERISTICS CURVES (For Any Transistor)
COMMON-EMITTER CIRCUIT, BASE INPUT
AMBIENT TEMPERATURE (TA)=25 D C
COLLECTOR-TO-EMITTER VOLTS(VCE)-5 V
COLLECTOR MILLIAMPERESlIcl=1
100
6 ~~~~~~~~~,~?=~~~~TTER VOLTS(VCE1=5V
4 AMBIENT TEMPERATUREITAI-2S Cl C
I
2_
10
8
-
t-.....
6
I II
I
h,,'lOO
,
"'" "- .....
2
-
I
-
,.
4
./"
2
,-
0.1 ,,0.01
2
6 •
4
""l!~
~~
h"
hOI ~ 15.6 14 mho
4
••
I
}
hie=2.7 ka
hre=I.BBJl.IO-4 atimA
0.1
~l 20
V
~
/
al
lo
or",
..
_hfe..::=
"'u
I"~
0:",
~Z
"'
~t:
..
8 I
VS.
~~
6 a 10
0.1
6 8,
/"
4
4
68 10
FREQUENCY (f)-MHz
92CS-14257RI
..(
STROBING
NOTE:
DIODES O!) THROUGH 08 PROVIDE GATE-OXIDE PROTECTION
FOR MOS/FETS INPUT STAGE.
92CL-24714
Fig. 2-Schematic diagram of the CA3130 Serial.
398
418 mW
BELOW 12SoC ............. Increase linearly at 18.7 mWJOC
File No. 833 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA3130A, CA3130B Slash (I) Series
ELECTRICAL CHARACTERISTICS
Typical Values Intended Only for Oesign Guidance
TEST
CONDITIONS
V+=15 V
V-=OV
TA=25 0 C
(Unle••
Specified
Otherwi.e)
CHARACTERISTIC
SYMBOL
Input Offset Voltage
IVlol
V±=±7.5 V
2
0.8
mV
Input Offset Current
11101
V i =±7.5 V
0.5
0.5
pA
II
V-=±7.5 V
5
5
pA
320k
320 k
V/V
110
110
dB
Input Current
large· Signal Voltage
Gain
AOL
VO=10V p .p
RL =2 kU
CA3130A
CA3130B
UNITS
Common·Mode
Rejection Ratio
CMRR
90
100
dB
Common·Mode
Input· Voltage
Range
VICR
-0.5
to
12
-0.5
to
12
V
Power·Supply
Rejection Ratio
8VI0/8V+
VOM+
Maximum Output
Voltage
V±=±7.5 V
8VIO/8V
VOMIVOM+I
RL=2 kU
RL=
IVOM-I
Maximum Output
Current:
Source
Sink
large·Signal Voltage
Gain
32
13.3
13.3
0.002
0.002
15
15
0
0
IlV/V
V
IOM+
VO=OV
22
22
VO=15V
20
20
10
10
2
2
10
5
IlV!DC
320 k
320k
VN
110
110
dB
1+
RL=~
8VIO/8T
AOL
rnA
rnA
VO-OV
RL=
Input Offset Volt·
age Temperature
Drift
32
32
10M
VO=7.5 V
Supply Current
32
TA=-55
to 1250 C
V±=±7.5 V"
VO=10 V p.p
RL =2 k!2 •
.
• Applill only to AOL .
• Applie. only to!:J. VIO,!:J. T.
399
CA3130A, CA3130B Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 833
TYPICAL VALUES INTENDED ONLY FOR DESIGN GUIDANCE
CHARACTERISTIC
SYMBOL
I nput Offset VQltage
Adjustment Range
CA3130A
CA3130B
UNITS
10 kU across
Terms. 4 and 5
or4 and 1
±22
±22
mV
TU
I nput Resistance
RI
1.5
1.5
Input Capacitance
CI
f= 1 MHz
4.3
4.3
pF
Equivalent Input Noise
en
BW=0.2 MHz
RS=l MU*
23
23
jJ.V
Unity Gain Crossover
Frequency
CC=O
15
15
fT
Cc - 47 pF
4
4
CC=O
30
30
Cc = 56 pF
10
10
0.09
0.09
10
10
%
1.2
jJ.S
Slew Rate:
Open Loop
SR
Closed Loop
Transient Response:
Rise Time
tr
Overshoot
Settling Time (4 Vp·p Input
toV+
jJ.A
jJ.V/v
File No. 833 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CA3130A, CA3130B Slash (II Series
Table I. Pre Burn·ln and Post Burn·ln Electrical Tests and Delta Limits·
ELECTRICAL CHARACTERISTICS AtTA = 25 0 C, V+ =+7.5 V, V- = -7.5 V
CHARACTERISTIC
I nput Offset Voltage
I nput Offset Current
I nput Bias Current
SYMBOL
LIMITS
TEST CONDITIONS
MAX.
CA3130A
CA3130B
Via
CA3130A
CA3130B
110
CA3130A
CA3130B
II
UNITS
MAX.Ll
5
±1
2
±0.5
20
±2
10
±1
30
±3
20
±2
mV
nA
nA
• Levels 11 and 12 require pre burn-in electrical and post burn-in electrical tests, and delta limits.
Level 13 requires pre burn-in electrical test only. The burn-in and operating life test circuit is shown in Fig. 6.
Table II. Final Electrical Tests and Group A Sampling Inspection
CHARACTERISTIC
Input Offset Voltage
TEST CONDITIONS
LIMITS
V+=+15V,V-=OV
SYMBOL
MINIMUM
MAXIMUM
UNITS
Unless Otherwise
Specified
-55 +25
+125 -55 +25 +125
CA3130A
CA3130B
Via
V±=±7.5V
110
V±=±7.5V
II
V± = ±7.5 V
CA3130A
Input Offset Current
CA3130B
CA3130A
I nput Current
CA3130B
Large Signal
Voltage Gain
CA3130B
CA3130A
Common·Mode
Rejection Ratio
CA3130B
CA3130A
Common·Mode
I nput Voltage Range
Power Supply
Rejection Ratio
Maximum Output Voltage
AOL
CA3130B
VOM+
VOM+
10M+
10M-
Supply Current
Input Offset Voltage
Temperature Coefficient
1+
7
5
7
-
3.5
2
3.5
30
20
30
-
-
20
10
20
-
-
15
0.03
15
15
0.03
15
-
-
94
88
94
100
94
80
80
80
-
86
86
86
-
-
-
0
0
0
10
10
10
V± = ±7.5 V
RL = 2 k!1
-
150
150
150
-
-
-
100
100
-
-
-
10
12
10
-
-
-
-
-
-
-
-
mV
pA
nA
dB
dB
V
IlVN
V
0.05 0.01 0.05
-
-
Va =OV
-
12
-
-
45
Va = 15 V
-
12
-
45
VO=25V.RL==
-
VO=OV,RL==
-
-
-
-
-
-
-
15
LlVIO/LlT CA3130B Only
-
100
14.95 14.99 14.95
RL ==
YOM
Maximum Output Current
-
88
YOM
Maximum Output Voltage
-
-
RL = 2 k!1
CMRR
PSRR
-
Va = 10 V p.p
VICR
CA3130A
-
-
0.05 0.01 0.05
-
15
-
3
-
15
15
V
mA
mA
/lV/DC
401
CA3130A. CA3130B Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 833
Table III. Group C Electrical Characteristics Sampling Tests
CHARACTERISTIC
TEST CONDITIONS
ATTA=25OC
V+=+15V.V-=-15V
SYMBOL
LIMITS
MIN.
MAX.
5
CA3130A
-
30
CA3130B
-
20
CA3130A
91
CA3130B
97
-
CA3130A
I nput Offset Voltage
VIO
I nput Offset Current
110
Input Bias Current
II
CA3130B
CA3130A
Large Signal Voltage Gain
CA3130B
AoL
UNITS
mV
2
20
pA
10
pA
dB
1CA3i:iO--------------------, v+
I
7
I
200".
8m'"
I
I
I
Om'' ' I
I
I
I
I
I
I
+ I
120
AO
e
'" 100
T
10UTPUT
6
~
o·
:!.
..
z
80
;;:
-200!:
OJ
3
~ 60
~
0
>
.
0
..
-300~
il:
40
11;
9,
z
OFFSET
~
NULL
*
9
,:,
20
0
TOTAL SUPPLY VOI-TAGE (FOR INDICATED VOLTAGE GAINS) -IS V
WITH INPUT TERMINALS BIASED SO THAT TERM. 6 POTENT1AL
0
10
IS +1.SV ABOVE TERM. 4.
"'WITH OUTPUT TERMINAL DRIVEN TO EITHER SUPPLY RAIL.
*
10'
92CS-2471&
Fig. 4-0pen4oop voltage gain and phase shift vs. frequency
for various valuesofCV CC,and R L "
Fig. 3-8lock diagram of the CA3130 Series.
I
..
11.5 SUPPLY VOLTAGE: V+= 15, V- = 0 V
AMBIENT TEMPERATURE (TA) = 25·e
15
+15V
: 12.5
,;
..·..l
ffi
I-
2.5V
,.
nr
7.5V-UU
10
2 kJl
2kJl
o
U
5
g
~
~
ffi
GATE VOLTAGE eVG) [TERMS.4 a
~
W
8]-V
~
92CS· 24883
92CS-24718
Fig. 5- Voltage transfer characteristics of COSMOS
output stage.
402
Fig. 6-Burn·in and life test circuit.
File No. 823 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
OOCU3LJ1]
MOS Field-Effect Transistors
N·Chann,el Depletion Types
Solid State
Division
High-Reliability Type
HR3N187
High-Reliability
Silicon Dual Insulated-Gate
Field-Effect Transistor
With Integrated Gate·Protection Circuits
For Applications in Aerospace, Military, and Critical Industrial
Equipment up to 300 MHz
Device Features:
• Back-to·back diodes to protect each gate against handling and in-circuit transients
• High forward transconductance - 9FS = 12,000 Ilmho (typ.)
• High unneutralized RF power gain - Gps = 18 dB(typ.) at 200 MHz
• Low VHF noise figure -,3.5 dB(typ.) at 200 MHz
JEOEC TO·72
The RCA·HR3N187 is a high·reliability n·channel silicon,
depletion type, dual insulated·gate field-effect transistor. It is
intended for applications in aerospace, military, and indus-
trial equipment. It is electrically and mechanically identical
with the standard type 3N187 described in Data 8ulletin File
No. 436 but is specially processed and tested to meet the
electrical, mechanical and environmental test methods and
Applications
• RF amplifier amplifier, mixer, and IF amplifier in military,
and'industrial communications equipmerit
• Aircraft and marine vehicular receivers
• CATV and MATV equipment
• Telemetry and multiplex equipment
procedures established for microelectronic devices in MI L-
STD·883.
The excellent over·all performance characteristics of
HR3N187 make it useful for a wide variety of rf·amplifier
applications at frequencies up to 300 MHz. The two
serially-connected channels with independent control gates
make possible a greater dynam ic range and lower cross·
modulation than is normally achieved using devices having
only a single control element. The HR3N187 is hermetically
sealed in the metal JEDEC TO·72 package.
Performance Features
• Superior cross·modulation performance and greater
dynamic range than bipolar or single-gate FET's
• Wide dynamic range permits large-signal handling
before overload
• Virtually no age power required
• Greatly reduces spurious responses in FM receivers
Maximum Ratings, Absolute-Maximum Values, at TA = 25"C
DRAIN·To-SDURCE VOLTAGE. Vos •••
GATE NO.l·TO-SOURCE VOLTAGE. VG1S:
Continuous (de) ...................
-0.2 to +20
-6 to +3
Peak ae ••..•..••••.•....•.••••.•.
-6 to
Io
I
"
:!
~
~
hsUPPLY VOL rAGE
~ (VOO)aISV
:!
10
~
10
10 V
10
-5S·C
~
o
...>
~
o
5
5
3.5
10
15
INPUT VOLTAGE (VII-V
10
9ZCS-I1779RI
Fig. 5- Min. and max. voltage transfer characteristics.
430
INPUT VOLTAGE (VII-V
15
92CS-I7780RI
Fig_ 6- Typ. voltage transfer characteristics
as a function of temperature.
File No. 687
CD4000A, CD4001A,
- - - - - - - - - - - - - - - - - - - CD4002A, CD4025A Slash (/) Series
AMBIENT TEMPERATURE ITAI
AMBIENT TEMPERATURE (TAl. 2S·C
= 2S·C
UPPLY VOLTS (v:
TYPICAL TEMP. COEFFICIENT AT ALL VALUES OF VGSo=-Q3"1.'·C
15
) '" I
GATE-TO-SOURCE VOLTAGE (Va )-15V
~'25
10
15
10V
10
5V
7.5
10
12.5
INPUT VOLTS IVII
2.5
15
5
7.5
10
12.5
15
DRAIN - TO - SOURCE VOLTAGE (Vosl-V
92CS-17178
92CS-22144
Fig. 8 -
Fig. 7- Typ. current and voltage transfer characteristics.
Min. n-channel drain characteristics.
DRAIN-TO-SOURCE VOLTS (Vos'
-15
-10
-5
i AMBIENT TEMPERATURE (TA ) .2S·C
LOAD CAPACITANCE (C L )· 15 pF
AMBIENT TEMPERATURE tTA 1=2S"C
TYPICAL TEMPERATURE COEFFICIENT
FOR ALL VALUES OF VGS = -0.3% loe
H-
-5
60
-10-2.5 ~
".
~
50
...
Z
>c
,..,.."
~3
~ 140
!:
.
1
GATE -TO-SOURCE VOLTS; -15
10
7.5
10
20
15
SUPPLY VOLTS (Vaal
92CS-19866
92CS-22743RI
Fig. 9 - Min. p-channel drain characteristics.
Fig. 10 - Typ. propagation delay time vs. V DD.
AMBIENT TEMPERATURE (TA) " 2S"C
TYPICAL TEMPERATURE COEFFICIENT FOR ALL VALUES
:!! 150 OF Voo ~ 0.3% loe
I
300
AMBIENT TEMPERATURE {TA}=2S"C
TYPICAL TEMPERATURE COEFFICIENT FOR ALL VALUES
OF VaD = 0.3 % 1°C
5
~
SUPPLY VOLTS (Vaol • 5
z
o
i= 100
!l1
~
15
20
30
40
SUPPLY VOLTS {Vo } = 5
...
10
10
200
50
GO
70
10
ao
LOAD CAPACITANCE (ell ...... pF
LOAa CAPACITANCE (CL)-pF
92CS-I7781
Fig. "
-,Typ. propagation delay time Vs.CL _
92CS-I7782
Fig. 12 - Typ. transition time vs. CL.
431
CD4000A, CD4001 A,
CD4002A, CD4025A Slash (I) S e r i e s - - - - - - - - - - - - - - - - - - TEST CIRCUITS
AMBIENT TEMPERATURE (TA). 25·C
POWER DISSIPATION P=CVoo2, + PaUIESCENT'
lOS
File No. 687
~
I 104
?
~ 103
to
SUPPLY VOLTS I Voo J "" 15
'" 102
~
EXAMPLE
IL INPUTS I
EXAMPLE
10
ILINPUTS I
~
~
.S
10
~
~
c
'L
PIN CONNECTIONS
MEASUREMENT
INPUTS I
INPUTS 2
LOAD CAPACITANCE (CLJ"'15pF
I
CL'S~;~
INPUTS 3
~
.!QJlliQ.
3,11,8,14
4,12.8.14
5,13,8,14
4,5,7,12,13
IL
3,~7.11.13
3,4,7,11,12
MEASUREMENT
INPUTS I
INPUTS 2
106
102
INPUT FREQUENCY (tl) -Hz
PIN CONNECTIONS
~
TO OND
1,5,8,12,14
2,6,9,13,14
2,6,7,9,13
1,5,7,8,12
92CS-17865
Fig. 14 - Quiescent device current Fig. 15 - Quiescent device current
test circuit for CD4000A.
test circuit for CD4001A.
Fig. 13 - Typ. dissipation characteristics.
v,,
6
'L
J,
PIN CONNECTIONS
MEASUREMENT
TO Voo
TOGNO
INPUTS I
'2,'9.'i4
INPUTS 2
INPUTS 3
INPUTS 4
3,10.14
4,11,14
5, 12,14
3,4,5,7,10,1\12
2,4,5,7,9.II,IZ
2,3,5,7,9,10,12
Fig. 16 -
EXAMPLE
INPUTS,lL
3VOR 711
(VOO"IOV)
PIN cQHNECTIONS
~
2,3,49J.:~:~~;1,~,
Quiescent device current
test circuit for CD4002A.
ISUifi.I,l
2,4,5,7,8,12,13
1,3,',7,8,11,13
1,2,3,4,7,11,12
1.3,11,14
2,4,12,14
8,5,13,14
Fig. 17 - Quiescent device current
test circuit for CD4025A.
Fig. 18 -
Noise immunity test
circuit for CD4000A.
Voo
5VORIOV
14
13
12
3.5 V OR 7 V
"
IO~~==-.?
61.5
0--015'1 OR 3'1
V OR :3 V
92CS - 20736RI
92CS- 20735RI
Fig. 19 - Noise immunity test
drcuit for CD4001A.
432
Fig. 20 -
Noise immunity test
circuit for CD4002A.
Fig. 21 -
Noise immunity test
circuit for CD4025A.
File No. 689 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Digital Integrated Circuits
OOm5LlD
Solid State
Monolithic Silicon
High-Reliability Slash(l) Series
CD4006A/ ...
Division
High-Reliability COSIMOS
18-Stage Static Shift Register
For Logic Systems Applications in Aerospace,
Military, and Critical Industrial Equipment
Special Features:
• Fully static operation
• Up to 5 MHz shifting rates
• Permanent register storage with clock line "high" or "low" no information recirculation required
Applications:
iii
Serial shift registers
• Time delay circuits
RCA CD4006A "Slash" (/) Series are high·reliability COS/MaS
integrated circuits intended for a wide variety of uses in aerospace, military, and critical industrial equipment. CD4006A
types are comprised of 4 separate "shift register" sections;
two sections of four stages and two sections of five stages with
an output tap at the fourth stage. Each section has an independent "single rail" data path.
A common clock signal is used for all stages. Data is shifted to
the next stage on negative-going transitions of the clock.
Through appropriate connections of inputs and outputs,
multiple register sections of 4, 5, 8, and 9 stages or single
register sections of 10, 12, 13, 14, 16, 17, and 18 can be im·
plemented using one CD4006A package. Longer shift register
sections can be assembled by using more than one CD4006A.
These devices are electrically and mechanically identical with
standard COS/MOS CD4006A types described in data bulletin
479 and DATABOOK SSD·203 Series, but are specially pro·
cessed and tested to meet the electrical, mechanical, and
environmental test methods and procedures established for
microelectronic devices in MI L·STD·883.
• Frequency division
In addition to the RCA high·reliability "Slash" (I) Series,
RCA will offer these circuits screened to MI L·M·38510 as
shown in RIC·l04, "MIL·M·38510 COS/MaS CD~OOOA
Series Types".
RCA Designation
MI L·M·3851 0 Designation
CD4006A
MI L·M·3851 0/05701
The packaged types can be supplied to siy screening levels 11N, 11R, 11. /2, 13, /4 - which correspond to MIL·STD·883
Classes "A", "B", and "C". The chip versions of these types
can be supplied to three screening levels - /M, IN, and /R.
For a description of these screening levels and for detailed
information on test methods, procedures, and test sequence
employed with high·reliability COSIMOS devices refer to
High·Reliability Report RIC·l02C, "High·Reliability COSI
MaS CD4000A "Slash" (I) Series Types".
The CD4006A "Slash" Series Types are supplied in 14·lead
dual·in·line ceramic packages ("D" suffix), in 14·lead ceramic
flat packages ("K" suffix), or in chip form ("H" suffix).
TRUTH TABLE FOR SHIFT REGISTER STAGE
0"
0
CL'
0+ 1
O®O+I
0
I.
I.
0
J
NO
CL
1
CL
0
---to-
CL
CL
OUT
IF41hOR
51h STAGE
1
X
1
NC : NO CHANGE
X: DON'T CARE
. : LEVEL CHANGE
92CS·17881
Fig. 1- Logic diagram and truth table (one register stage) for type CD4006A.
9·74
433
CD4006A Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
MAXIMUM RATINGS, Absolute-Maximum Values:
Storage.Temperature Range ..........
Operating-Temperature Range ______ ....
DC Supply-Voltage Range:
(VDD - VSS) ....................
Device Dissipation (Per Package) ..._.....
Recommended
DC Supply-Voltage (VDD - VSS)
3 to 15
Recommended
Input-Voltage Swing. . . . . . . . . . . . . . .. VDD to VSS
Lead Temperature (During Soldering)
At d;stance 1/16" ± 1/32"
(1.59 ± 0.79 mm) from case
for 10 s max. . ............ __ . . . . . .
+265
°c
°c
. -65 to +150
. -55 to +125
File No. 689
. -0.5 to +15 V
mW
200
.
Allinputs . _ ....................... . VSSSV,SVDD
V
°c
STATIC ELECTRICAL CHARACTERISTICS (All Inputs •. _ VSS:::; V,:::; VDD)
Recommended DC Supply Voltage 3 to 15 V
N
LIMITS
CHARACTERISTIC
SYMBOL
rEST
CONDITIONS
Vo
Quiescent Device
Dissipation/Package
-55°!;'
Voo
Volts Volts
OuiescentOevice
Current
CD4006AD. CD4006AK
Min.
10
Po
10
VOL
10
Typ.
0.01
O.S
,.
30
0.01
2.S
0.05
2.S
ISO
10
0.1
10
200
10
20·
0.55-
0.5-
0.01
0.01
0.05
0.01
0.01
0.05
0.5-
0.55-
"A
"W
V
2.3-
2.25-
yO"
S
Max.
,.
IS
High-level
Max. Min.
0
T
e
125°C
25°C
Min.
O.S
'l
Output Voltage
Low-Level
Max.
UNITS
4.99
4.99
999
9.99
9.95
4.45-
14.5-
IS
V
4.95
10
-
Threshold Voltage:
N-Channel
Vn-l N
10= 20/JA
-0.7-
-3·
P·Channel
Vni p
'0=20 IJA
0.7-
3·
Noise Immunity
(Any'nput)
For Definition,
See Appendix
SSO·207
Output Drive Current:
V Nl
t---
P·Channel
Diode Test,lOOIJA
Test Pin
1.S
-3· -0.33·
0.3-
S
I.S
1.5-
2.25
1.4
O.S
10
3·
3·
4.S
2.9-
I.'
1.5-
2.25
1.S
2.9-
'3·
4.S
3·
4.S
9.S
'DN
O.S
'DP
-1.5
O.S
V N"
N-Channel
-0.7-
0.7-
10
0.155
0.125-
0.25
0.085
O.S
10
0.31
0.25-
O.S
0.175
4.S
S
-0.125
9.S
10
-0.25
V OF
Input Current
0.1-0.2-
-0.07
0.15
-0.14
--0.3
1.5-
1.5-
--33·
V
V
-
mA
-
rnA
1.5-
10
V
pA
Limits with black dot (_I designate 100% testing. Refer to RIC·l02B "High-Reliability COS/MOS CD4000A Slash (I) Series Types", Tables 2
through 7 for testing sequence, All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1: Complete functional test, all inpuls and outputs to truth table.
Note 3: Test on all inputs and outputs.
Note 2: Test is either a one input Of one output only.
For Threshold Voltage Test Circuits, Operating and Biased Ufe Test Circuits. Output Drive Currenr Test Circ!:its.
and for Operating Considerations, s;e Appendix..
434
File No. 689 - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4006A Slash (/) Series
~
FROM
PREVIOUS
STAGE
(OR INPUT
IF 1st
STAGE)
T
e-i
C
L
CL
CL VDD
~~
fI{
i
-:1
NOTE: ALL "P""-UNIT SUBSTRATES
ARE CONNECTED TO VDD
ALL ""N"" -UNIT SUBSTRATEs
ARE CONNECTED TO VSS
-+-i
rv:s
92CS·17894
Fig. 2- Schematic diagram (one register stage)
(or type CD4DO~.
DRAIN-TO-SOURCE VOLTS (VDS)
I
DRAIN-TO-SOURCE VOLTS (Vosl
92CS-22747
Fig. 3- Minimum n-channel drain characteristics.
92CS-22746
Fig. 4- Minimum p-channel drain characteristics.
435
CD4006A Slash (I) Series - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 689
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25 oC. CL = 15 pF. and input rise and fall times = 20 ns except trCL. ttCL
Typical Temperature Coefficient for all values of VDD O.3%/oC (See Appendix for Waveforms'
=
LIMITS
CHARACTERISTICS
TEST
CONDITIONS
SYMBOLS
Min.
Typ.
Max.
-
250
125
400
200·
ns
1
-
25!i
125
400
200·
ns
1
200
100
500
200
ns
-
-
-
15
5·
IlS
1
-
50
25
80
40
ns
-
1
2.5·
2.5
5
-
MHz
1
-
5
30
-
pF
-
tTHl·
tTlH
5
10
Minimum Clock
Pulse Width
twl.
tWH
5
10
Clock
Rise & Fall Time
trCl·
tlCl·
5
10
-
5
10
Set·UpTime
Maximum Clock
5
10
fCl
Frequency
Input Capacitance
Data Input
Clock Input
C,
N
0
T
E
S
5
10
Transition Time
UNITS
VDD
(Volts'
tpHL.
tplH
Propagation Delay Time
CD4006AD.CD4006AK
-
Limits with black dot (.) designate 100% testing. Refer·to RIC-l02B "High-Reliability COS/MOS CD4000A Slash (f) Series Types", Tables 2
through 7 for testing sequence, All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1: Test is a one input one output only.
* If more
than one unit is cascaded tfCL should be made less than or equal to the sum of the fixed propagation delay at 15 pF and the transition
time of the output driving stage for the estimated capacitive load.
AMBIENT TEMPERATURE (TA)= 25 ·C
TYPICAL TEMPERATURE COEFFICIENT
FOR ALL VALUES OF VOO =0.3"D/DC
AMBIEN.T TEMPERATURE (TA)·25'"C
TYPICAL TEMPERATURE COEFFICIENT
FOR ALL VALUES OF VDO-O.3'"1.'-C
...
g~
'"~300
300
0200
;
z
i\l
... 100
100
10
20
30
40
50
60
LOAD CAPACITANCE (CL)-pF
70
80
92CS- 17604
Fig. 5- Typical propagation delay time vs. CL .
436
10
U>
15
to
10
...is
10
z
10
20
30
40
50
60
LOAD CAPACITANCE (CL)-pF
70
92CS-1760'5
Fig. 6- Typical transition time vs. CL -
File No. 689 - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ CD4006A Slash (I) Series
AMBIENT TEMPERATURE (TAl· 25°C
ALTERNATING "0"
AND" I " PATTERN
10
SUPPLY VOLTSIVool
104
I NPUT FREQUENCY (f
+) -
Hz
Fig. 7- Typical dissipation characteristics.
15
20
nCS-I9S61
Fig. 8- Typical clock frequency vs. VDD'
10V
5V OR IOV
1.5 OR 3V
3.5 OR 7VQ-o
10
7 '
With S1 at ground, clock unit 18 timBS
by connecting S2 to pulse generator.
Return 52 to ground and measure leak-
age current. Repeat with 52 at VOD.
Fig. 10- Noise immunity test circuit.
Fig. 9- Quiescent device current test circuit.
SZINPRESETPUTSICUTINALL""'STATE
52 IN TEST WHEN MAKING DISSIPATION a.I[ASUREIoI[NT
Fig. 11- Device dissipation test setup.
437
File No. 695
oornLJ1]
Digital Integrated Circuits
Monolithic Silicon
Solid State
Division
High-Reliability Slash(/) Series
CD4007A1.•.
High-Reliability COSIMOS
Dual Complementary Pair Plus Inverter
For Logic Systems Applications in Aerospace,
Military, and Critical Industrial Equipment
Special Features:
• Medium speed operation ... tpHL = tpLH = 20 ns (typ.) at CL = 15 pF
• Low "high"· and "Iow"-output impedance .•. 500 n (typ.)
at VDD - VSS = 10 V
TERMINAL No. 14"' Voo
TERMINAL No.7 = Vss
92CS-22242
Applications:
• Extremely high·input impedance amplifiers, inverters, shapers, linear
amplifiers, threshold detectors
RCA CD4007A "Slash" (I) Series high·reliability COS/MOS
integrated circuits are comprised of three n-channel and three
p-channel enhancement·type MaS transistors. The transistor
elements are accessible through the package terminals to pro·
vide a convenient means for constructing the various typical
circuits shown in Fig. 1. More complex functions are possible
using multiple packages. Numbers shown in parentheses indicate terminals that are connected together to form the various
configurations listed. For proper operation VSS VI VDD
must be satisfied.
:s :s.
The CD4007 A "Slash" (I) Series are electrically and mechani·
cally identical to the standard COS/MOS CD4007 A types
described in data bulletin 479 and DATABOOK SSD·203
Series, but are specially processed and tested to meet the
electrical, mechanical, and environmental test methods and
procedures established for microelectronic devices in MI L·
STD·SS3. In addition to the RCA high·reliability "Slash" (I)
Series, RCA will offer these circuits screened to MI L·M·3851 0
as shown in RIC·l04, "MIL·M·38510 COS/MOS CD4000A
Series Types".
MIL·M·38510 Designation
RCA Designation
CD4007A
MIL·M·38510/05301
The CD4007 A "Slash" (I) Series types are supplied in 14·lead
dual·in·line ceramic packages ("0" suffix), in 14·lead ceramic
flat packages ("K" suffix), or in chip form ("H" suffix).
MAXIMUM RATINGS, Absolute·Maximum Values:
Storage·Temperature Range .......... .
Operating·Temperature Range .......... .
DC Supply·Voltage Range:
(VDD - VSS)·····················
Device Dissipation (Per Package) ........ .
All Inputs ......................... .
Recommended
DC Supply·Voltage (VDD - VSS) .....
Recommended
Input·Voltage Swing ................
Lead Temperature (During Soldering)
At distance 1/16" ± 1/32"
(1.59 ± 0.79 mm) from case
for lOs max. .....................
-65 to +150
-55 to +125
°c
°c
-0.5 to +15 V
200 mW
VSS $ VI $. VDD
3 to 15
V
VDD to VSS
+265
°c
The packaged types can be supplied to six screening levels lIN, I1R, II, 12, 13, 14 - which correspond to MIL·STD·SS3
Classes "A", "S", and "C". The chip versions of these types
can be supplied to three screening levels - 1M, IN, and IR.
For a description of these screening levels and for detailed
information on test methods, procedures, and test sequence
employed with high·reliability COSIMOS devices refer to
High·Reliability Report RIC·l02C, "High·Reliability COSI
MOS CD4000A "Slash" II) Series Types".
438
9·74
File No, 695 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4007A Slash (/) Series
a} Triple Inver.ers
(14,2,11); (8,13); (1,5); (7,4,9)
(6,3,10); (8,5,12);
(11,14); (7,4,9)
e) High Sink-Current Driver
(OPTIONAL Vee PULL-UP)
92CS-15350
b} l-Input NOR Gate
(13,2); (I,ll); (12,5,8); (7,4,9)
+--_---.....-1@
~~""12
10~
92CS-J5349
c} l.lnput NAND Gate
(1,12,13); (2,14,11); (4,8); (5,9)
~~12
10~
92CS-l~330
92CS-15348
d} Tree (Relay) Logic
(13,12,5); (4,9,8);
(14,2); (l,ll)
f)
Dual Bi_Directionol Transmission Gating
(1,5,12); (2,9);
(11,4); (8,13,10);
(6,3)
VOO
OUT
t'---+--oOUT
A
#
~
ALL P-UNIT SUBSTRATES
ARE CONNECTED TO VOO
ALL N-UNIT SUBSTRATES
ARE CONNECTED TO 'Iss
B
OUT (VOO):C+AB
OUT (VSSJ"CA+CB
::Ivss
¥CS-L5347
92CS-15329
g) High Slnk- and Source-Current Driver
(6,3,10); (14,2,11);
(7,4,9); (13,8,1,5,12)
h) High Source-Current Driver
Voo
(6,3,10); (13,1,12);
(14,2,11); (7,9)
Voo
I-+-
~
(OPTIONAL VSSPULL-DOWN)
VSS
Vss
92CS-15327
92CS-I~328
Fig.
t- Sample COS/MOS logic circuit arrangements using type CD4007A.
439
CD4007 A Slash (/) Series
File
LIMITS
CHARACTERISTIC
SYMBOL
TEST
CONDITIONS
Vo
IL
Quiescent Device
Dissipation/Package
PD.
_55°C
VOO
Volts Volts
Quiescent Device
Current
C0400ZAO, C04007AK
Min.
Max.
10
O.OS
0.1·
0.001
0.1·
O.OOS
0.25
a
a
0.Q1
10
0.Q1
V OH
5
4.99
4.99
10
9.99
9.99
Threshold Voltage:
N·Channel
P-Channel
Noise Immunity
(Any Input)
VTHN
10=-1O~A
-0.7-
-3·
VTHP
10=10 ~A
0.7-
3·
3.6
V NL
7.2
V NH
0.95
2.9
ION
VI=V OD 0.4·
0.5
P-Channel
lOP
Test Pin
10
VI=VSS 2.5 t
9.5
Diode Test,lOO IlA
10
0
Output Drive Current:
N·Channel
10
10
-0.70.7-
15
0.Q1
O.OS
0.01
O.OS
0.6-
0.7-
-1.5
1.5
-3· -0.33·
0.3"
1.5-
2.25
1.4
4.5
2.9-
1.4
1.5-
2.25
1.5
2.9-
3·
4.5
3·
0.04-
0.05·
2.5
0.95
0.6-
-0.04·
-0.05-
-1.4-
-4
-1.35
-1.1·
-2.5
V OF
V
-3·
V
V
rnA
2
rnA
'-1.
-0.75'
1.5-
1.5-
V
3·
0.4
-1.15
I nput Current
V
14.3-
3·
1.5-
~W
4.95
9.95
10
1.5
1.6
Max.
~A
3·
0.75
N
0
T
E
S
200
14.4-
15
695
2·
0.01
15
High·Level
125°C
Max. Min.
0.001
0.25
VOL
25°C
Typ.
O.OS
10
Output Voltage
Low-Level
Min.
UNITS
No,
1.5-
10
V
3
pA
Limits with black dot ,_) designate 100% testing. Refer to RIC·l02B "High-Reliability COS/MOS CD4000A Slash (f) Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters un~er given test conditions and do not represent 100% testin.g.
Note 1: Complete functional test. all inputs and outputs to truth table.
Note 2: Test is either a one input or one output only.
Note 3: Test on all inputs and outputs.
"Maximum noise·free saturated Bipolar output voltage.
tMinimum noise-free saturated Bipolar output voltage.
For Threshold Voltage Test Circuits, Operating and Biased Life Test Circuits. Output Drive Current Test Circuits,
and for Operating Considerations, see Appendix..
440
File No. 695. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4007A Slash (II Series
DYNAMIC ELECTRICAL CHARACTERISTICS at TA ~ 25 0 C, CL ~ 15 pF, and input rise and fall times ~ 20 ns
Typical Temperature Coefficient for all values of VDD ~ 0.3%/oC ISee Appendix for Waveforms)
N
LIMITS
0
CHARACTERISTIC
TEST
CONDITIONS
SYMBOL
Propagation Delay Time:
tpHL
High·ta-Law Level
VDD
IVolts)
Min.
Typ.
Max.
5
-
35
60
10
-
20
40·
35
60
20
40·
5
Low-ta-High Level
tpLH
10
5
Transition Time:
tTHL
High-ta-Low Level
10
5
Law-ta-High Level
tTLH
I nput Capacitance
10
Any Input
CI
UNITS
T
E
S
ns
1
ns
1
ns
1
ns
1
pF
-
CD4007 AD,CD4007 AK
50
75
30
40·
50
75
30
40·
-
5
limits with black dot Ie) designate 100% testing. Refer to RIC-l02B "High-Reliability COS/MaS CD4000A Slash (JJ.~eries Types", Tabl~s 2
through 7 for testing sequence. All other limits are designer's parameters undp.r given test conditions and do not represent 100% testing.
10V
Note 1: Test is a one input one output only_
5VOR 10V
92CS-17902RI
92CS-17901
Fig. 2- Noise immunity test circuit.
Fig. 3- Quiescent device current test circuit.
AMBIENT TEMPERATURE
15
SUPPLY VOLTS (Voo)
or
15
v~
12.5
~
~
0
>
5
10
IT A )·2S·C
10
7.5
~
0
3.5
2.5
2.5
7.5
10
12.5
15
INPUT VOLTS IV I )
2.5
92CS-1778ei
7.5
10.
12.5
15.
INPUT VOLTS (Vr)
92CS-17867
Fig. 4- Min. and max. voltage transfer characteristics for inverter.
Fig. 5- Typ. voltage transfer charBCteristics for NOR gate.
441
CD4007A Slash (/) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 695
AMBIENT TEMPERATURE (TA
1·2~C
~r~:D1V.~~~A~,E
15
>
!0
.....
T A =125"'<:
-5S"C
~
10V
10
-5S"C
!:;
Q
>
-H12.-""
....
~
5 V
5
Q
H-t
55""
12S-C
0
10
15
INPUT VOLTAGE (Vl1-V
INPUT VOLTS IVI)
92CS-I7780RI
92CS-I7786
Fig. 6- Typ. voltage transfer characteristics for NAND gate.
Fig. 7- Typ. voltage transfer characteristics as a function of temp.
AMBIENT TEMPERATURE (TA) - 2!5·C
TYPICAL TEMPERATURE COEFFICIENT FOR 10 • - 0.3% ,GC
AMBIENT TEMPERATURE ITA)" 25·C
15
UPPLY VOLTS
(v:
15
)-1
ATE - TO - SOURCE VOLTS tVc;S) -I
Q
12.5
>
~
....
~
10
10
I Vo 10
10
15
~)9
7
7.5
"
0
IO
2.5
0
TERM. 3
10
2.5
7.5
12.5 !:!
~
Q
10
12.5
~
"
~
12.5
~
~
7.5 j
12
;;
z
Vo
5
10--
a 6 TO GND.
~
2.5
2.5
15
INPUT VOLTS (VI)
7.5
10
12.5
15
ORAIN - TO - SOURCE VOLTS IVos )
92CS-17787
Fig. 8- Typ. current and voltage transfer characteristics for inverter.
Fig. 9- Minimum n-channel drain characteristics.
DRAIN - TO - SOURCE VOLTS (Vos)
-17.5
-15
-12.5
-10
-7.5
-5
-2.5
I
2.5
AMBIENT TEMPERATURE fT A) ·2S G C
TYPICAL TEMPERATURE COEFFICIENT FOR
150 ALL VALUES OF Voo-O.3 '"Ie'·C
10
7.5 i:
~
AMBIENT TEMPERATURE (TA' '" 25·e
-10
TYPICAL TEMPERATURE COEFFICIENT
FOR 10=-0.3"10
~
:[
==
100
!II
SUPPLY VOLTS Voo -5
~
I"e
-12.5~
10
15
GATE - TO - SOURCE VOLTS IV
)" -15
15
-17.5
10
92CS·22784
Fig. 10- Minimum p-channei drain characteristics.
442
20
30
40
SO
60
70
80
CAPACITANCE ICL1- pF
92CS-I7789
Fig. 71- Typical propagation delay time vs. CL'
File No. 695 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4007A Slash (I) Series
AMBIENT TEMPERATURE {TA,a25·C
LOAD CAPACITANCE lell =15 pF
UJ
150
::E
=~
100
SUPPLY VOLTS (Veol =5
"'i=::E
z
o
:;;
=1:10
50
...~
+.-
I•
10
20
30
40
50
60
70
CAPACITANCE lel' - pF
BO
92CS-227B5
Fig. 13- Maximum propalJdtion delay time vs. VDO"
Fig. 12- Typical transition rime vs. CLo
10'
20
10
15
SUPPLY VOLTS (Vool
92CS-I7790
AMBIENT TEMPERATURE ITA'· 25·C
POWER DISSIPATION p3CV002, + PaUIESCENT
~
I 104
C
~
~
103
SUPPLY VOLTS IVo ) ·15
or
~ 102
il
~
~
10
......
3.'
10
LOAD CAPACITANCE (ell "'15pF
I
CL·5~~~
103
104
105
loG
INPUT FREQUENCY (f,1 - Hz
92.CS-17865
Fig. 14- Typical dissipation characteristics.
443
File No. 696
Digital Integrated Circuits
OO(]5L}[]
Monolithic Silicon
Solid State
Division
High-Reliability Slash(/) Series
CD4008A/.•.
Co
0;
s.
A;
"
High-Reliability COS/MOS
Four-Bit Full Adder
With Parallel Carry-Out
For Logic Systems Applications in Aerospace,
Military, and Critical Industrial Equipment
'2
"
(CARRY-IN)
Special Features:
Applications:
• MSI complexity on a single chip ... 4 Sum Outputs
plus parallel Carry Output
• High speed operation ... Carry·ln to Carry·Out
delay, tpHL' tpLH = 45 ns at CL = 15 pF
• Binary addition/arithmetic uni!
RCA C04008A "Slash" (I) Series are high·reliability COS/MOS
integrated circuits intended for a wide variety of logic function
configurations in aerospace, military, and critical industrial
equipment. The CD400BA types consist of four full-adder
stages with fast look-ahead carry provision from stage to stage.
Circuitry is included to provide a fast "parallel-carry·out" bit
to permit high-speed operation in arithmetic sections using
several C04008A's. C0400BA inputs include the four sets of
bits to be added, A1 to A4 and S1 to S4, in addition to the
"carry-in" bit from a previous section. C0400BA outputs
include the four sum bits, 51 to 54, in addition to the highspeed "parallel·carry·out" which may be utilized at a succeeding
C04008A section_
00
RCA Designation
MI L-M-3B510 Designation
C0400BA
MI L·M-38510/05401
The packaged types can be supplied to six screening levels I1N, I1R, 11, 12,/3, 14 - which correspond to MIL-STO-8B3
Classes "A", "S", and "C"_ The chip versions of these types
can be supplied to three screening levels - 1M, IN, and IR.
For a description of these screening levels and for detailed
information on test methods, procedures, and test sequence
employed with high-reliability COSIMOS devices refer to
High-Reliability Report RIC-l02C, "High-Reliability COSI
MOS CD4000A "Slash" (Ii Series Types".
'"
AO
0,
A,
02
These devices are electrically and mechanically identical to the
standard COS/MOS C04008A described in data bulletin 479
and OATASOOK 550-203 Series, but are specially processed
and tested to meet the electrical, mechanical. and environmental test methods and procedures established for micro·
electronic devices in MI L·STO-883. In addition to the RCA
high-reliability "Slash" (I) Series, RCA will offer these circuits
screened to MIL-M-3B510 as described in RIC·l04, "MIL-M·
38510 COS/MOS C04000A Series Types".
The C04008A "Slash" (I) Series types are supplied in 16-lead
dual-in-line ceramic packages ("0" suffix), in 16·lead ceramic
flat packages ("K" suffix), or in chip form ("H" suffix).
0
A2
0,
A; 0,
A,
TERMINAL No. 16 -VDD, TERMINAL NO.8· Vss
92CS-I~842
,
,
,
0
Fig. 1- Logic diagram for type CD4008A.
444
C;
a 0
a a
0
, aa
a a
, a
(I-
,
Co SUM
a
0
a
,
a
,
,
!!,~TH
TABLE
, a ,
, ,
, , , a
, , , ,
0
0
9-74
CD4008A Slash (J) Series
File No. 696
Recommended
V
3to 15
DC Supply·Voltage (VDD - VSS)
Storage-Temperature Range . . . . . . . . . . -65 to +150 °c Recommended
I nput·Voltage Swing ................ VDD to VSS
Operating·Temperature Range ........... -55 to +125 °c
Lead Temperature (During Soldering)
DC Supply·Voltage Range:
At distance 1/16" ± 1/32"
(VDD - VSS) ..................... -0.5 to +15 V
(1.59 ± 0.79 mm) from case
mW
200
Device Dissipation (Per Package) .........
+265 °c
for 10 s max. .....................
All Inputs .......................... VSS:::; VI:::; VDD
MAXIMUM RATlNGS,Absolute·Maximum Values:
.
STATIC ELECTRICAL CHARACTERISTICS (All Inputs ... VSS::; VI ::; VDD)
Recommended DC Supply Voltage 3 to 15 V
LIMITS
CHARACTERISTIC
SYMBOL
TEST
CONDITIONS
I~o
Volts Volts
55~C
Voo
Min.
Max.
Min.
Quiescent Device
O,s~ipation/Pack age
'L
0.5
25
1.5
10
100
3
0.55-
0.5-
0.01
0.01
0.05
0.01
0.01
0.5-
0.05
VOL
15
V OH
10
499
499
fl9n
9.99
15
P·Channel
Noise Immunity
(Any Input)
For Definition,
See Appendix
VTHN
I D ,·-20 lolA
VTHP
I D '- 20
~A
V NL
200·
25
1500
100
2000
-3·
0.7-
3·
V
V
9.95
14.45-
-0.7-
-1.5
0.7-
1.5
-3· -0.33·
0.3-
5
1.5
1.5-
2.25
1.4
2.9
10
3·
3·
4.5
2.9-
1.4
1.5-
2.25
1,5
10
2.9-
3·
4.5
3·
0.31
0.25-
0.5
0.175
10
0.93
0.75·
1.5
0.53
10
0.12.
0.31
0.'0.25-
0.2
0.5
0.07
0.175
-0.31
-0.25-
-0.5
-0.93
0,06-
-0.75- -1.5
-0,05 1-0.06
-0.15- '-0.3
7.2
.W
4.95
10
145'
-0.7-
.A
0.55-
0.95
3.6
V NH
10·
2.3-
2.25-
Threshold Voltage:
N·Channel
300
10·
PD
T
E
S
Max.
10
10
Hlgh·Level
Max. Min.
0.3
Output Voltage
Low-Level
Typ.
UNITS
12Soc
2SoC
Quiescent Device
Current
N
0
CD4008AD,C04008AK
-3·
V
3·
V
V
550·207
Output Dnve Current
'ON
N·Channel
Carry
0.5
Output
0.5
Sum
Output
P·Channel
'OP
Carry
Output
Sum
Output
3
4.5
9.5
10
5
10
-0.185
mA
-0.~75
0.53
-0.03
mA
-0.105
Oiode Test.l00 jJ.A
Test Pm
V DF
Input Current
1.5-
1.5·
1.5-
10
V
pA
Limits with black dot (-) designate 100% testing. Refer to RIC-l02C "High-Reliability COS/MOS CD4000A Slash (f) Series Types", Tables 2
through 7 for testing sequence. All other Ii"!its are designer's parameters under given test conditions and do not represent 100% test.
Note 1: Complete functional test. all inputs and outputs to truth table.
Note 3: Test on all inputs and outputs.
Note 2: Test is either a one mput or one output only.
For Threshold Voltage Test Circuits, Operating and Biased Life Test Circuits, Output Drive Current Test Circuits,
and for Operating Considerations, see Appendix
445
CD400BA Slash (II Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 696
DYNAMIC ELECTRICAL CHARACTERISTICS at T A =250 C. CL =15 pF and input rise and faU times =20 ns
Typical Temperature Coefficient for all values of VOD = O.3%JOC. (See Appendix for Waveformsl
N
0
T
E
S
LIMITS
CHARACTERISTICS
SYMBOLS
TEST
CONDITIONS
VOD
(Volts)
5
Propagation Delay Time:
At Sum Outputs;
From Sum Input
From Carry Input
At Carry 0 utput;
From Sum Input
tpHL'
tpLH
From Carry Input
Transition Time:
At Sum Outputs
At Carry Output
Input Capacitance
CD4008AD.CD400BAK
tTHL'
tTLH
el
10
5
10
5
10
5
10
5
10
5
10
Anv Input
Min.
Typ.
Max.
-
900
1300
-
325
900
325
320
120
100
45
1250
550
125
45
10
500·
1300
500
600
200
175
75·
2200
900
225
75
UNITS
ns
-
-
-
-
1
ns
ns
-
ns
1
ns
-
-
ns
-
pF
-
limits with black dot (e) designate 100% testing. Refer to RIC·l 028 "High-Reliability COS/MOS CD4000A Slash (J) Series Types", Tables:
through 7 for testina sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1: Test isa one input one output only.
13-16 {
A
813-16
"'::E
AMBIENT TEMPERATURE (T A) ·25·C
TYPICAL TEMPERATURE COEFFICIENT
600 FOR ALL VALUES OF Von .:0.3 %'·C
10
15
Vss
o
NOTES
ALL "A" s"s· INPUT BITS OCCUR ATI-O
ALL SUMS SETTLED AT t· 660".
CL-15pF, TA-t2S·C,VOD-YSS·+ lOY
20
30
40
50
60
LOAD CAPACITANCE ICL)-pF
70
BO
92CS-17822
92CS-17761
Fig. 2- Typical speed characteristics of a 16-bit adder.
446
10
Fig. 3- Sum-in to carry-out propagation delay time
V.f.
CL .
File No. 6 9 6 , , - - - - - - - - - - - - - - - - - - - - - - - - CD4008A Slash (/) Series
g
AMBIENT TEMPERATURE ITAI ;; 25·C
TYPICAL TEMPERATURE COEFFICIENT
I!
AMBIENT TEMPERATURE ITA Ie 25 "C
ti),
TYPICAL TEMPERATURE CaEFACIENT
~:r 1500 FOR VALUES OF VOO"'O.3%/"C
FOR All VALUES OF Voo"O.3'"1o'oC
o.
i:q
~~
.~
~~ 1000
~~o
10
.."'-...
15
1"-
u
~
.0
150
10
15
o
10
20
30
40
50
60
70
BO
10
20
LOAD CAPACITANCE (CLI- pF
30
40
50
60
70
LOAD CAPACITANCE (CL)-pF
Fig. 4- Sum-in or carry-in to sum-out propagation delay time vs. CL .
I 600
3
80
92CS-11824
92CS-11823
Fig. 5- Carry-in to carry-out propagation delay time vs. CL'
AMBIENT TEMPERATURE ITAI ·2S·C
LOAD CAPACITANCE (el' -15 pF
~D.500
...
::.
400
'"
li 300
g
;:
z 200
0
li
:
100 CD4OO8AD,c0400BAK
f
0
10
20
15
10
10 2
INPUT FREQUENCY (f
SUPPLY VOLTS (Vool
+) -
10 3
Fig. 6- Max. propagation delay time vs. V DD for carry-in to carry-out.
104
k Hz
92CS-22145
92CS-11825RI
Fig. 7- Typical dissipation characteristics.
1.5V OR 3V
SVOR IOV
+
Exercise inputs through
switches and perform
leakage test for each
input condition.
92CS -17904R2
Fig. 8- Quiescent device current test circuit.
Fig. 9- Noise immunity test circuit.
447
CD4008A Slash (/) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 696
~~
]
~
11f- ~r
:J C
~
[1=-r=r
84·
[1-
I~L
:r::
:......J~ -
I~L.....
Tv55
~
:r: I
W:.':
Tvss
A4
6-
83
...,::[1= d
....,:J
:r::
j: h~'
DD
1--;1
~- ~
3
A3
] ~L.
- :; L
:......J-
JVDD
VDD
J
B2
~:-
II~
:} ;S
1
Vss
~ss
~
Vss
~
-----.J :;:I
lv
'"J
JV DD
-t-~5lv
ss
JVDD
-(j---J
ss
Tvss
-.tDD
--':r--'
- I--
1l~1
L
Ii
,--
ss
:~L
rvss
5
~~~
~~:J
::?'
~L
A2
tr-
lv
tDD
~
-
JV DD
,J~L.
....c
Tvss
...J:'-~L
A.
AI
9
CIN
ALL P UNIT I ~) SUBSTRATES CONNECTED TO VDD
ALL N UNIT I "') SUBSTRATES CONNECTED TO VSS
I::::J
DRAIN 6 SOURCE REGION WIDTHS'3 MILS
I::::J
DRAIN 6 SOURCE REGION WIDTHS-IO 1.41 LS
DRAIN 6 SOURCE REGION WIDTHS ON ALL
o TH ER DEVICES • 1.1 MIL
Fig. 10- Schematic Diagram.
448
-
File No. 696 - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ CD4008A Slash (I) Series
r
-
10
H.
1.
92SL·4Z . .
449
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 719
Digital Integrated' Circuits
ffil(]5LJ[]
Monolithic Silicon
Solid State
Division
High-Reliability Slash(/) Series
CD4009A/•••, CD4010A/•••
High-Reliability COSIMOS
Hex Buffers/Converters
---r:- +-C>-
--c>---c>---c>---c>---c>-CD4009A
-C>-C>-C>-C>-
CD4010A
For Logic Systems Applications in Aerospace,
Military, and Critical Industrial Equipment
Inverting Type: CD4009AD, CD4009AK
Non-Inverting Type: CD401()AD"CD4010AK
Special Features (Each Buffer):
- High current sinking capability ... 8 rnA Imin. at VOL = 0.5 Vand
VOO=+10V
Applications:
- COS/MOS to OTLmL hex converter
- COSIMOS hex inverter
• COSIMOS current "sink" or "source" driver
- COSIMOS logic-level converter
- Multiplexer - 1 to 6 or 6 to 1
CAUTION:
VCC VOLTAGE LEVEL MUST BE .EQUAL TO OR LESS THAN
VDD' FOR 10.5- TO 15-VOLT SUPPLIES, CLOAD MUST BE
EQUAL TO OR LESS THAN 5000 pF.
RCA C04009A and C04010A "Slash" (I) Series are highreliability integrated circuits intended for a wide variety of
logic function configurations in aerospace, military, and
critical industrial equipment. CD4D09A types may be used as
a hex COS/MOS inverter, a COS/MOS to DTL or TTL logiclevel converter, or a COS/MOS current driver. C04010A types
may be used as a COS/MOS to DTL or TTL hex converter or a
COS/MOS current driver.
Conversion ranges are from GOS/MOS logic operating at +3 v
to +15 V supply levels to DTL or TTL logic operating at +3 V
to +6 V supply levels. Conversion to ·Iogic output levels greater
than +6 V is permitted' providing VCCIDTLITTL)
~
VOOICOS/MOSl.
circuits' screened ·to MIL·M-3B510 as described in RIC-l04,
"MI L-M·3B510 COS/MOS CD4000A Series Types".
RCA Designation
MI L-M·3B510 Designation
CD4009A
CD4010A
MI L-M-3B51 0/05501
MI L-M-3B510/05502
The packaged types can be supplied to six screening levels - .
11 N, 11 R, 11, 12, 13, 14 - which correspond to MI L·STO-883
Classes "A", "B". and "C". The chip versions of these types
can be supplied to three screening levels -1M. IN, and IR.
For a description of these screening levels and for detailed
information on test methods, procedures, and test sequence
employed with high·reliability COSIMOS devices refer to
High-Reliability Report RIC·/02C, "High·Reliability COSI
MaS CD4000A "Slash" (I) Series Types".
These devices are electrically and mechanically identical with
standard COS/MOS types CD4009A and CD4010A described
in data bulletin 479 and DATABOOK SSO·203 Series, but are
specially processed and tested to meet the electrical, mechanical, and environmental test methods and procedures established
for' microelectronic devices in MI L-ST0-883. In addition to the
RCA high·reliability "Slash" Series, RCA will offer these.
The C04009A and C04Dl0A "Slash" (I) Series types are
supplied in HI·lead dual·in-line ceramic packages 1"0" suffix),
in IS·lead ceramic flat packages ("K" suffix), or in chip
form I"H" suffix).
MAXIMUM RATI NGS. Absolute·Maximum Values:
Recommended
Storage-Temperature Range ..........
Operating·Temperature Range ..........
DC Supply-Voltage Range:
IVDD - VSS) ....................
. Device ~issipation IPer Package) ........
. -S5 to +150
. -55 to +125
°c
°c
. -0.5 to +15 V
200
mW
.
All Inputs ......................... . VSs::;VI~Vr
450
DC Supply·Voltage IVOO - VSS)
3 to 15
V
Recommended
Input·Voltage Swing ................ VOD to VSS
Lead Temperature (During Soldering)
At distance IllS" ± 1/32"
11.59 ± 0.79 mm) from case
+265 0C
for lOs max. .....................
9-74
File No. 719 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4009A, CD4010A Slash (I) Series
3_~~
.....
A~G~A
~9
~"',....
~II
~_
~
_
D~J"D
O~J.D
NC(>..!l
VCC
o-J.
E~-"",K'E
NC~
veeo---!GNDo--!!
GNDo--!
VDO~
VDD~
~
E~K.E
~
F~L.F
92SS-4142R2
Fig. 1- Logic diagrams for types C04009A and C04010A.
"DD
P
INPUT
J
OUTPUT -, r VCC
U_GND
n - VDD
LGND
92SS4139
VSS
CONFIGURATION·
HEX COS. MOS TO DTl DR TTL
CONVERTER (INVERTING)
WIRING SCHEDULE,
CONNECT VCC TO OTl DR
TTL SUPPLY.
CONNECT VDD TO COS· MOS
SUPPLY
Fig. 2- Schematic diagram for types CD4009A
fone of 6 identical stages).
AMBIENT TEMPERATURE ITA )·25"C
l:j
INPUT
J
n-VDD
LGND
CONFIGURATION,
HEX COSIMOS TO OTl DR TTL
CONVERTER (NON.INVERTlNG)
WIRING SCHEDULE,
CONNECT VCC TO DTl OR
TTL SUPPLY
CONNECT VDO TO COS MOS
SUPPLY.
Fig. 3- Schematic diagram for types CD4010A
(one of 6 identical srages).
--MAX.
---MIN.
"C4>-Q0
~g~~ITION:
VCC ·5V
....
"~
o
o
68101214
INPUT VOLTS (V,)
92,CS-20061'
Fig. 4- Min. and max. voltage transfer charac teristics - CD4009A.
4
6
•
INPUT VOLTS IV,'
10
12
92.CS-17837
Fig. 5- Typical voltage transfer characteristics as function
of temp. - C04009A.
451
CD4009A, CD4010A Slash (II Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 719
STATIC ELECTRICAL CHARACTERISTICS (All input••..••....•..•...•..•.....•....•.. vss < VI < VOO)
(Recommended OC Supply Voltage (VOO - VSS) . . . . . • • .. 3'0 15 V}
LIMITS
CHARACTERISTIC
SYMBOL
TEST
CONDITIONS
Vo
CD4009AO.C04009AK.C04010AD.CD4010AK
Quiescent Device
Current:
5
IL
10
5
Quiescent Device
Dissipation/Package
Output Voltage:
Low-Level
Po
10
5
10
VOL
Threshold Voltage:
N-Channel
P·Channel
VOH
Min.
-
125°C
25°C
Typ.
Max. Min.
0.Q1
0.3
0.5"
-
0.Q1
0.5"
1.5
-
0.05
1.5
5
-
0.1
Max. Min.
0.3
0.01
0.01
5
0
0.01
0
0.01
-
0.6-
5
4.99
10
9.99
-
15
-
-
14.4"
-
-
15
High-Level
_55°C
V DD
Volts Vol.s
-
N
UNITS 0
T
E
L£
Max.
20
10"
IlA
1
IlW
-
100
100
0.05
0.05
V
0.7-
4.99
5
10
-
4.95
9.99
9.95
-
14.3"·
-
VTHN
lo=-10IlA
-0.7"
-3"
-0.7"
-1.5
-3"
-0.3" -3"
VTH P
IO=10IlA
0.7"
3"
0.7"
1.5
3"
0.3"
-
I"
2.25
-
0.9
-
2"
4.5
-
1.9"
-
1.5"
2.25
1.4
4.5
-
2.9"
2.25
-
1.5
-
1
V
V
2
3"
Noise Immunity
(Any Input)
CD4009A
V NL
CD4010A
C04009A
V NH
C04010A
P-Channel
Diode Test
I"put Current
5
1
10
2"
VOL =0.95 V
5
VOL =2.9 V
10
ION
-
3"
5
1.4
-
loS-
VOL =2.0 V
10
2.9"
-
3"
VOW 3.6V
5
1.4
-
1.5-
VOF
3"
4.5
-
2.25
-
10
2.9"
-
3"
4.5
-
CD4009A
0.4
5
3.75
-
3"
4
C04010A
0.5
10
10
-
8"
10
-
CD4009A
0
3
0.4"
-
0.5"
C04010A
0
3
0.02"
0.025"
-
C04009A
2.5
5
-1.85
-
-1.25"
-1.75
C04010A
9.5
10
-0.9
-
-0.6"
-0.8
C04009A
3
3
-0.04"
-
-0.05"
-
CD4010A
3
3
-0.02"
-
-0.025"
1.5"
-
a
a
lOP
1.5
VOL =0.95 V
VO H=7.2 V
Output Drive Current:
N·Channel
VOH =3.6V
VOH =7.2 V
100 IlA Test Pin
II
-
1.5"
-
-
-
-
-
10
-
3"
1.5
-
-
-
-
-
-0.9
-
-0.4
-
3"
2.1
5.6
-
V
1
V
2
rnA
2
1.5"
V
3
-
pA
-
Limits with black dot {el designate 100% testing. Refer to AIC-l02B "High-Reliability COS/MOS CD4000A Slash (f) Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given ,test conditions and do not represent 100% testing.
Note 1: Complete functional test, all inputs and outputs to truth table.
Note 2: Test is either iii one input or one output onlv.
Note 3: Test on all rnputs and outputs.
For Threshold Voltage Test Gircu;ts, Operating and Biased Life Test Circuits, Output Drive Current Test Circuits,
and for Operating Considerations. see Appendix.
452
-
File No. 719--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4009A, CD4010A Slash (I) Series
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25 0 C, CL = 15 pF, and input rise and fall times = 20 ns
Typical Temperature Coefficient for all values of VDD = 0.3%I"C. (See Appendix for Waveforms)
LIMITS
CHARACTERISTICS
TEST
CONDITIONS
SYMBOLS
N
CD4009AD ,CD4009AK
UNITS
CD4010AD,CD4010AK
0
T
E
S
VDD
(Volts)
Propagation Delay Time:
High·to·Low Level
VCC = VDD
5
10
Min.
Typ.
Max.
-
15
10
55
30·
-
10
25
tpHL
VDD = 10 V
VCC = 5 V
Low·to·High Level
tpLH
VCC = VDD
5
-
50
80
10
-
25
55·
-
15
30
VDD = 10 V
ns
1
ns
~
1
f--
VCC = 5 V
5
-
20
45
10
-
16
40·
5
-
80
125
10
-
50
100·
CD4009A
-
15
CD4010A
-
5
Transition Time:
High·to·Low Level
tTHL
VCC = VDD
Low·to·High Level
tTLH
VCC = VDD
I nput Capacitance
(Any Input)
CI
-
ns
1
ns
1
pF
-
Limits with black dot 1-' designate 100% testing. Refer to RIC·l028 "High-Reliability COS/MOS CD40QOA Slash (/) Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1: Test is a one input one output onlv.
AMBIENT TEMPERATURE (TA 1·25C
COLLEC10R SUPPLY VOLTAGE
(vca·sv
DRAIN SUPPLY VOLTAGE (Vao)" 5 V
~
o
MIN.
MAX.
o
3
4
5
INPUT VOLTS (VI)
92CS-19955
INPUT VOLTS (VI)
9l~I95RI
Fig. 6- Min. and max. voltage transfer characteristics
(VOO
= 5)
- C04010A.
Fig. 7- Min. and max. voltage transfer characteristics
(VOO = 10) - C04010A.
453
CD4009A, CD4010A Slash (II Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 719
INPUT VOLTS (VI)
INPUT VOLTS (VI)
92ss.420lRi
92ss-4I98Rl
Fig. 9- Typical voltage transfer characteristics as 8 function
of temp. - CD4010A.
Fig. 8- Min. and max. voltage transfer characteristics
(VOD ~ 15) - C04010A.
AMBIENT TEMPERATURE (TAl. 25-C
LOAD CAA\CITANCE (el). 15pF
i
300
60
~
C
i
~
'" 200
...'"
~
CERAMIC PACKAGES ItpLH)
9
50
!j
100
~
40
~
30
~
20
10
z
CERAMIC PACKAGES (tPtlL)
1f
10
~
o
10
SUPPLY VOLTS
15
10
(Voo· Vee)
15
20
DRAIN-TO-SOURCE VOLTS (Vas)
'2CS-Z2'27
Ffg· 10- Maximum propagation delay time
VB.
V DO - CD40tOA.
92CS-17876
Fig. 71- Minimum n-channel drain characteristics.
40
60
80
100
LOAD CAPACITANCE (CL ) - pF
Fig. 12- Typical high-to-/owlevel propagation delay time
vs. CL - C04009A. C04010A.
454
92CS-17873
Fig. 13- Typical low-to-hlgh level propagation delay time
vso CL - C04009A. CD4010A.
File No. 719 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4009A. CD4010A Slash (f). Series
AMBIENT TEMPERATURE (TAl -25·C
TYPICAL TEMPERATURE COEFFICIENT
fOR ALL VALUES OF Voo ·O.3%"·C
20
Fig. 14- Typical high-to-Iowlevel transition time
Fig. 15- Typicallow-to-high level transition time
vs. CL - CD4009A. CD40l0A.
vs. CL - CD4009A, CD4010A.
10 4 8
AMBIENT TEMPERATURE ITAI • 25·C
~ 300
J
1&1
"...
~
~
z
o
~QQ
100
<,<>
~
10'
~
~
CERAMIC PACKAGES tpHLl
4V
~
•
10
10
15
SUPPLY VOLTS (Voo· Veel
10
V
•
[7
4
••
V-
I
=
~~~~o ~~PAC 7ANCE;CLltpr
• •
10'
INPUT FREQUENCY
I
6
If~)
•
elba
4
••
10
kHz
92CS-19807
Fig. 16- Maximum propagation delay time vs. Voo - CD4009A.
Fig. 17- Typical dissipation characteristics - CD4009A, CD4010A.
5 VOR IOV
IOV
92.CS-19806
Fig. 18- Quiescent device current test circuit.
./
:J:
V
/
./
92CS·2Z927
r----+--------~~IL
/1.- V
'/
6·
:r
11:
V
V
.,
!l!l·"-\
8
6
4
•
V.
,. • L .
~
~
/
"
.£lv" '.--/;.(1 I
~
CERAMIC PACKAGES It PL.H'
./
25·C
\~v
•
~
;
ITAI~
1.1 V""
10 3
~
200
TEMPERATURE
4
~
i.;
AMBI~NT
6
,..
LOAD CAPACITANCE (eL.I. ISpF
5 V OR 10 V
92CS -19805RI
Fig. 19- Noise immunity test circuit
for CD4009A.
92CS-24423
Fig. 20- Noise immunity test circuit
for CD40l0A.
455
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 717
OO(]5LJD
Digital Integrated Circuits
Monolithic Silicon
High-Reliability Slash(/) Series
CD4011A/..., CD4012A/•••,
CD4023A/•••
Solid State
Division
High-Reliability COS/MOS NAND Gates
For Logic Systems Applications in Aerospace,
Military, and Critical Industrial Equipment
Quad 2 Input - - - CD4011AD, CD4011AK
Dual 4 Input - - - CD4012AD, CD4012AK
Triple 3 Input - - - CD4023AD, CD4023AK
Special Features:
CD4011A
• Medium speed operation .•. tpHL = tpLH = 25 ns (typ.) at CL = 15 pF
• Low "high"· and "Iow"",eve' output impedance ... 400 and 800 n (typ.),
respectively, at VOO - VSS = 10 V
RCA C04011 A, C04012A, and C04023A "Slash" (II Series
are high·reliability COS/MaS integrated circuits intended for a
wide variety of uses in aerospace, military, and critical industrial
equipment. The combination of these devices and the RCA
NOR positive logic gate types C04000A, C04001A, C04002A,
and C04025A can account for appreCiable package count
The C04011 A, CD4012A, and C04023A "Slash" II) Series
types are supplied in 14·lead dual·in·line ceramic packages
("0" suffix), in 14·lead ceramic flat packages ("K" suffix), or
in chip form ("H" suffix).
,. "00
savings in various logic function configurations. These devices
are electrically and mechanically identical with standard
COS/MaS types CD4011 A. CD4012A. and CD4023A described
in data bulletin 479 and DATABOOK SSO·203 Series, but are
specially processed and tested to meet the electrical, mechanical,
and environmental test methods and procedures established for
microelectronic devices in Mll-STD·B83. In addition to the
RCA high·reliability "Slash" II) Series, RCA will offer these
circuits screened to MIL·M·38510 as described in RIC·l04,
"MIL·M·38510 COS/MOS CD4000A Series Types".
RCA Designation
MIL·M·38510 Designation
C04011A
MIL·M·38510/05001
CD4012A
MI L-M-3851 0/05002
C04023A
MI L·M-3851 0/05003
The packaged types can be supplied to six screening levels lIN, /lR, II, 12, /3, /4 - which correspond to MIL-STD-BB3
Classes "A", "B", and "C". The chip versions of these types
.can be supplied to three screening levels - /M, /N, and IR.
For a description at these screening levels and for detailed
information on test methods, procedures, and test sequence
employed with high-reliability COSIMOS devices refer to
High-Reliability Report RIC-102C, "High-Reliability COSI
MOS C04000A "Slash" (II Series Types".
For a listing of the Screening Level Options available for both
packaged devices and chips, and for a description of the
COS/MaS high·reliability integrated circuit part numbers, see
the following page.
456
"
NC
Vss 7
IC"~
CD4012A
NC
CD4023A
MAXIMUM RATINGS,Absolute·Maximum Values:
Storage-Temperature Range .......... ,
Operating-Temperature Range. . . . . . . . . ..
DC Supply-Voltage Range:
(VOO -VSS)·················· .. ·
Device Dissipation (Per Package) ........ .
All Inputs
Recommend~d ...................... .
-65 to +150
-55 to +125
0c
0c
-0.5 to +15 V
200 mW
VSSSVISVOO
DC Supply· Voltage (VOO - VSS) .... .
3 to 15
V
Recommended
Input-Voltage Swing ................ VDO to VSS
Lead Temperature (During Soldering)
At distance 1/16" ± 1/32"
(1.59 ± 6.79 mm) from case
for 10 s max ...................... .
+265 °c
9·74
File No. 717 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4011A, CD4012A, CD4023A Slash (I) Series
e
50~-------------------~
,--~-+--o13
13
12
IOcr----~~--_t---~
lIo---------~---~
V55
Fig.
12o-------------~
2- Schematic diagram for type C0401 tA.
V55
1
92C$-15970
Fig. 1- Schematic diagram for type C04012A.
~~--+---1_J::JNOUTb"~---+---4-J
~---+---~~N
II:f
D'2~__-+__-4--'
'ueS-I" .• ,
Fig. 3- Schematic diagram for type CD4023A.
457
CD4011A, CD4012A, CD4023A Slash (I) Series
File
No. 717
STATIC.ELECTRICAL CHARACTERISTICS (All Inputs ... VSS:::; VI:::;' VOO'
Recommended OC Supply Voltage 3 to 15 V
LIMITS
CHARACTERISTIC
SYMBOL
CD4011AD,CD4012AD.CD4023AD.
CD401 lAK.co401 2AK,CD4023AK
TEST
CONDITIONS
V DD
I~o
Volts Volts
-550 C
Ma ••
Min.
Quiescent Device
Current
Quiescent Device
Dissipation/Package
'L
10
Po
Output Voltage
Low-L&vel
VOL
10
I -
5
I!
Min.
25°C
Typ.
-
10
0.05
3
0.'·
0.001
0.1·
2°
0.25
0.005
0.25
Threshold Voltage:
N·Channel
P·Channel
Noise Immunity
Any Input
0
0.01
0.05
0.D1
0
0.01
0.05
0.6-
0.7-
4.99
4.99
5
4.95
9.99
9.99
10
9.95
For Defin;tioli,
See Append;x
'0·-10.A
-0.7-
_J o
VTHP
'0=10.A
0.7-
JO
V NH
CD4011A
C04023A
eries
Output Drive Current:
N·Channel
'ON
CD4012A
Series
Diode Test
Input Current
lOP
VOF
-1.5
_J o
0.7-
1.5
JO
1.5-
2.25
1.4
JO
4.5
2.9-
0.95
5
1.4
1.5-
2.25
1.5
2.9
10
2.9-
JO
4.5
JO
0
3
0.02-
0.5
10
,
-
0.31
0.025°
' 0.25-
0.5
0.175
0.62
0.5-
0.6
0.35
0
0.02-
0.025°
0.5
0.15
0.12-
0.25
0.085
J.l
0.25-
0.6
0.175
0.5
10
4.5
5
-0.31
-0.25-
-0.5
-0.17!
9.5
10
-0.75
-0.6-
-1.2
-0.4
100 IlA Test Pin
_J o
-0.3-
1.5
0.5
V
V
0.3-
JO
-0.02P·Channel
-0.7-
10
J.6
7.2
.W
14.3-
14.4-
VTHN
V NL
15
.A
20
0.D1
15
N
O'
T
E
S
Max.
0.001
0.D1
10
VOH
125°C
Ma •• Min.
0.05
15
High·Level
UNITS
V
2
V
2
JO
V
mA
2
mA
-0.025-
loS-
1.510
mA
2
I
1.5-
V
pA
Limits with black dot (_I designate 100% testing. Refer to RIC·1028 "High-Reliability COS/MOS CD4000A Slash (II Series Types", Tables 2
·through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1: Complete functional test, all inputs and outputs to truth table.
Note 3: Test on all inputs and outputs.
Note 2: Test is either a one input or a one output only.
458
File No. 717 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4011A, CD4012A, CD4023A Slash (I) Series
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25 0 C, CL = 15 pF, and input rise and fan times = 20 ns
Typical Temperature Coefficient for aU values of VDD = O.3%l"c (See Appendix for Waveforms)
CHARACTERISTICS
SYMBOLS
Propagation Delay Time:
tpLH
Low·to-High Level
LIMITS
CD4011AD, AK
CD4012AD, AK
CD4023AD, AK
TEST
CONDITIONS
High-to-Low Level
CD4011A and
CD4023A Series
Min.
Typ.
Max.
5
-
50
75
10
-
25
40·
5
-
50
75
25
40·
5
CD4012A Series
10
Transition Time:
5
tTLH
Low-to-High Level
10
High-to-Low Level
CD4011Aand
tTHL
CD4012A Series
Input Capacitance
150
75·
50
75
100
60·
40
-
50
5
-
250
375
10
-
125
200·
-
5
Any Input
el
100
10
5
CD4023A Series
UNITS
VDD
(Volts)
10
tpHL
:1
I
N
0
T
E
S
ns
1
ns
1
ns
1
ns
1
ns
1
ns
1
pF
-
·125
75
75·
-
Limits with black dot 1_) designate 100% testing. Refer to RIC-l02B "High-Reliabitity COS/MOS CD4000A Slash III Series Types", Tables 2
through 7 for testing sequence, All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note1: Test is a one input one output on Iv.
AMBIE~T TEMPER~~URE
AMBIENT TEMPERATURE
15
SUPPLY VOLTS 'Vool
= 15
15
Voo
~o
12.5
~
ITAI "25°C
10
>
10
'"
10
u
I-
7.5
>
~
~
"o
TA=12S"C
-5S"C
2:
'"
~
(TA }-2S"C
~PLY VOLTAGE
(VOOI .. I5V
10
10 V
- 5S"C
m2S 0 C
5 V
m
3.5
~soC
2.5
125°C
2.5
7.5
10
12.5
INPUT VOLTS IVII
I~
92CS-I7191
10
15
INPUT VOLTAGE (VrJ-V
Fig. 4- Min. and max. voltage transfer characteristics.
459
CD4011A, CD4012A,CD4023A Slash (/) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 717
AMBIENT TEMPERATURE (TA 1 .. 25"C
S
IS
~~n''''.;'f!hW-
.
.
.... 12.S
~
10
~
AMBIENT TEMPERATURE (TA' .. 2SoC
10
d
IS
~
b
0
UPPlY VOLTS IVI
'"~
.
..
10
10
0
>
>
7.S
0
b
ii'
vDD
~
S
0
2.5
.
IS
7.5
:>
S
b
=I
~
0
!;
)
12.5
.
c=3 INPUTS
d-4 INPUTS
2.S
ID
ALL OTHER INPUTS TO YOO
7.5
2.S
0
a =1 INPUT
b"2 INPUTS
d
10
12.5
0
15
INPUT VOLTS (VI)
2.5
7.5
10
12.5
INPUT VOLTS IVI)
92CS-17868RI
15
92CS-I7792.
Fig. 7- Typical current and voltage transfer characteristics.
Fig. 6- Typical multiple input switching transfer characteristics
for CD4012A.
AMBIENT TEMPERATURE ITA )= 25-C
TYPICAL TEMPERATURE COEFFICIENT FOR 1 0 ,,-0.3%/'"<:
GAtt - TO - SOURCE VOLTS IVGs ) = IS
t-_
:a
.:3
'" 4
~
:l
3
z
~
2
!!;
10
10
i
~I
.'L
.
AMBIENT TEMPERATURE ITA)" 2!1°C
TYPICAL TEMPERATURE COEFFICIENT
FOR loa -0.3% laC
10
5
10
15
DRAIN - TO - SOURCE VOLTS (Vas)
15
SOURCE - TO - DRAIN VOLTS (VOS)
92CS·22714
92CS-22712
Fig. 8- Minimum n-channel drain characteristics - CD4011A
and CD4023A.
Fig. 9- Minimum n-channel drain characteristics - CD4012A.
DRAIN-TO-SOURCE VOLTAGE (Vos)-V
-15
-10
AMBIENT TEMPERATURE ITA)= 25 "c
TYPICAL TEMPERATURE COEFFICIENT
FOR IO=-O.3%I"C
+t#
AMBIENT TEMPERATURE ITA'c25°C
TYPICAL TEMPERATURE COEFFICIENT
150 FOR ALL VALUES OF Voo" 0.3%'OC
-5
-t~v
+t -
.
I
~
.
10V
- S E
GATE-TO-SOURCE VOLTAGE
'VGS)~15
:~
"'~
100
SUPPLY VOLTS (V OO J=5
~
10
15
-IS
10
20
30
40
50
60
LOAD CAPACITANCE (C l ) -
70
pF
80
92CS-I1794
92CS-221n
Fig. 10- Minimum p-channel drain characteristics.
460
Fig. 11- Typicallow-to-high level propagation delay time vs. CL •
File No. 717 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _CD4011A. CD4012A. CD4023A Slash (I) Series
I..J 300
AMBIENT TEMPERATURE (TA ' • 25°C
TYPICAL TEMPERATURE COEFFICIENT
j
FOR ALL VALUES OF Veo -0.3,../·C
=~
::.a
'"'"
!l!
I-
AMBIENT TEMPERATURE (TA ) ·2S·C
TYPICAL TEMPERATURE COEFFICIENT FOR
ALL VALUES OF VDO "0.3'Y./"C
300
~
1;
200
5:g
200
SUPPLY VOLTS (V
g
z
o
SUPPLY VOLTS
i
Z
Voo -5
o
ti
~
100
100
10
~
10
~
)- S
15
15
o
10
20
30
40
50
60
70
eo
o.
10
20
30
40
50
60
92CS-I7795
Fig. 12- Typical high-to-Iow level propagation delay time
V~ CL - CD401IA.andCD4023A.
Fig. 13- Typical high-to-Iow level propagation delay time vs. CL CD4012A.
600
r
AMBIENT TEMPERATURE (TA' "2S"C
TYPICAL TEMPERATURE COEFFICIENT FOR
AU VALUES OF Voo " 0.3% /"~
500
~...
....
:: 100
f
400
z
,.'"
...
300
~
;::
~
80
92CS-I7796
150
o
......Z
70
LOAD CAPACITANCE (CL)-pF
LOAD CAPACITANCE ICLI- pF
Z
0
15
50
SUPPLY VOLTS (VOD'-5
...
200
~
100
!!1
,AMBIENT TEMPERATURE
ITA)- 25·C
10
15
~J:'i~t ~~~~~~AclFURv~DC~F~:;~~T
o
10
20
30
40
50
60
70
LOAD CAPACITANCE ICLI-pf
80
10
AMBIENT TEMPERATURE (TAl· 25·C
TYPICAL TEMPERATURE COEFFICIENT
300 FOR ALL VALUES OF Voo ·0.3%'OC
50
60
70
80
600
.
~
jsoo
-::.
j!:
~200
~ 400
,....
SUPPLY VOLTSIVoolaS
;::
~
i!i
;::
in
...
40
AMBIENT TEMPERATURE (TA I " 25"C
LOAD CAPACITANCE (CL'" 15 pF
~
1.
I
!
30
Fid. 15- Typical high-to-Iow level transition time vs. CL CD401lA and CD4023A.
Fig. 14- Typicallow-to-high transition time vs. CL -
!
20
LOAD CAPACITANCE (C l ) - pF
92CS-I7797
10
Z
,.
100
o 200
~
10
20
CD4023A. CD40llA
(tPLH). (tpHLl
CD4012A (I PHLJ
~
g:
o
300
30
40
50
60
70
LOAD CAPACITANCE ICLI- pF
80
92CS-I779B
Fig. 16- Typical high-fO-/OW level transition time vs. CL CD4012A.
CD4012A(t PLH)
100
10
15
SUPPLY VOLTS (Vee)
20
9ZCS-22770
Fig. 17- Minimum propagation delay time vs. VDO'
461
CD4011A, CD4012A, CD4023A Slash II) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 717
105
AMBtENT TEMPERATURE (TAl" 25 -C
POWER DISSIPATION p. Cyoo2, + POUIESCENT
EXAMPLE
IL INPUTS I
~
I 104
Q
!!o
~
103
~
102
.
SUPPLY VOLTS(V D)-IS:
0
i'i
f
.5
10
Zl
0
, LOAD CAPACITANCE (Cl)·I~pF
I
CL·5~~~
102
IL
MEASUREMENT
INPUTS I
INPUTS 2
10'
IIIPUT FREQLENCV (tl) -Hz
92CS-17865
PIN CONNECTIONS
~~
1.5,8.12,14 2,6,7,9,13
2,6,9,13,14 1,5,7,8,12
92C5-20737
Fig. 19- Quiescent device current test circuit for CD4011A.
Fig. 18- Typical dissipation characteristics.
EXAMPLE
IL INPUTS 1
IL
MEASUREMENT
INPUTS I
INPUTS 2
INPUTS 3
INPUTS 4
PIN CONNECTIONS
TO VOO
TO GNO
2,9,14
3,10,14
3,4,5.7,10,11,12
2,4,5,9,11,12
4.11.14
5,12,'4
2.3,5,9.10,12
2.3,4,9,10,11
IL
MEASUREMENT
INPUTS I
INPUTS 2
INPUTS 3
PIN CONNECTIONS
~
llL!itl.Il
1,3,11,14
2,4,12,14
8,5,13,14
2,4,5,7,8,12,13
1,3,5,7.8,11,13
1,2,3,4,7,11,12
92CS-20739
92CS-20741
Fig. 20- Quiescent dellicecurrent testc;rcu;t for CD4012A.
Fig. 21- Quiescent del/ice current ttnt circuit for CD4023A.
5VOR IOV
14
13
12
II
10
9
92CS - 20740RI
92CS-20738RI
Fig. 22-Noise.fmmunity test circuit
for CD4071A.
462
Fig.
23~Nolse";mmunity
forCD4012A
test circuit
92CS - 20742Rf
Fig. 24-Noise';mmunity test circuit
for CD4023A.
File No. 697 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.,.,--_ _ _ _ _._ _---,
Digital Integrated Circ·uits
D\l(]5LJD
Monolithic Silicon
Solid State
Division
voo
14
SETI 6
High-Reliability Slash(l) Series
CD4013A/•.•
High-Reliability Dual nO"_Type Flip-Flop
With Set-Reset Capability
For Logic Systems Applications in Aerospace,
Military, and Critical Industrial Equipment
0, 5
CLOCK I 3
RESET I 4
Special Features:
SET28
• Static flip·flop operation ... retains state indefinitely with clock level
either "high" or "Iow"
• Medium speed operation ... 10 MHz (typ.) clock toggle rate at
02 9
CLOCK2 II
vss
VOO - VSS = 10 V
.. low "high"· and "low"-output impedance ... 400 nand 200 n,
respectively, at VOO - VSS = 10 V
Applications:
iii
Register. counters. control circuits
RCA CD4013A "Slash" (I) Series are high·reliability COS/MOS
integrated circuits intended for a wide variety of uses in aerospace. military, and critical industrial equipment. CD4013A
types consist of two identical, independent data~type flip-flops.
Each flip·flop has independent data, set, reset, and clock inputs
and "Q" and "0" outputs. These devices can be used for
shift register applications, and, by connecting "0" output to
the data input, for counter and toggle applications. The logic
level present at the "D" input is transferred to the "Q" output
during the positive·going transition of the clock pulse. Setting
or resetting is independent of the clock and is accomplished by
a high level on the set or reset line, respectively.
This device is electrically and mechanically identical with
standard COS/MOS CD4013A types described in data bulletin
479 and DATABOOK SSD·203 Series, but are specially pro·
cessed and tested to meet the electrical, mechanical, and en·
vironmental test methods and procedures established for micro·
electronic devices in MIL·STD·8B3. In addition to the RCA
high·reliability "Slash" (II Series, RCA will offer these circuits
screened to MIL·M·36510 as described in RIC·l04, "MIL·M·
36510 COS/MOS CD4000A Series Types".
RCA Designation
MIL·M·36510 Designation
CD4013A
MIL·M·36510/05101
TRUTH TABLE
0
R
S
a a
J
J
0
0
0
0
I
1
0
0
1
0
"'"'x
x
x
0
0
a a
1
0
0
1
X
X
0
I
1
0
X
X
1
1
1
1
CL'
5/9
NO
CHANGE
2112
• = LEVEL CHANGE
CL
~- t ~_t
~
]/11-
TERMINAL 14
m
x = DON'T CARE CASE
111]
** = FF1IFF2 TERMINAL ASSIGNMENTS
VOD
TERMINAL 7 = GNO
9-74
BUFFERED OUTPUTS
Fig. 1- Logic diagram and truth table (one of two identical flip·flops).
463
· CD4013A Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 697
The packaged types can be supplied to six screening levels 11 N, 11 R, 11, 12, 13, 14 - which correspond to MI L·STD·BB3
Classes "A", "B", and "C". The chip versions of these types
can be supplied to three screening levels -/M,/N, and IR.
MAXIMUM RATINGS. Absolute-Maximum Values:
Storage·Temperature Range .......... . -65 to +150 °c
Operating·Temperature Range .......... . -55 to +125 °c
DC Supply·Voltage Range:
For a description of these screening levels and for detailed
(VDD -VSS)····················· -0.5 to +15 V
information on test methods, procedures, and test sequence Device Dissipation (Per Package) ........ .
200
mW
employed with high·reliability COS/MaS devices refer to All Inputs .......................... VSS$VI$VDD
High·Reliability Report RIC·l02C, "High·Reliability COS/ Recommended
MaS CD4000A "Slash" (/J Series Types".
3 to 15
V
DC Supply·Voltage (VDD - VSS) .....
Recommended
Input·Voltage Swing ............... . VDD to VSS
The CD4013A "Slash" (I) Series types are supplied in 14-lead
dual·in·line ceramic packages ("0" suffix), in 14-lead ceramic Lead Temperature (During Soldering)
At distance 1116" ± 1/32"
flat packages ("K" suffix), or in chip form ("H" suffix).
(1.59 ± 0.79 mm) from case
for 10 s max ..................... .
+265 °c
DRAIN - TO - SOURCE VOLTS (Vos'
-15
-12.5
-10
-7.5
-5"
15
~12.!S
i
::l
GATE - TO - SOURCE VOLTS (Vos)
-25
-.
AMBIENT TEMPERATURE (TA) • 2S D C
TYPICAL TEMPERATURE COEFFICIENT FOR ID h o.3% ,·C
~ 15
-10
10
GATE-TO- SOURCE VOLTS (VG ). -15
7.5
AMBIENT TEMPERATURE ITA). 2S·C
"z
TYPICAL TEMPERATURE COEFFICIENT
10V
~
2.5
fOR 10--0.3%/'"(:
-7.5
';l
.V
2.5
7.5
10
12.5
15
DRAIN - TO - SOURCE VOLTS (Vos)
Fig. 3- Minimum p-channel drain characteristics.
92CS-22749
Fig. 2- Minimum n-channel drain characteristics.
AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (TA)"25 ~
INPUT I, a It .20 ns
TA • 2/S·C
LOAD CAPACITANCE (ell· 15 pF
15
'"
IILDAD CAPACITANCE (C )·15 pF.
1'"104
~I
1--').1
1111111111
~ 103
15 pF
SUPPLY VOLTS(Voo)aI5
~
'" 102
~
ISpF
so,_
III
15 pF
I--'
~
z
~
l'f
in
11
10
103
10 4
105
10 6
INPUT FREQUENCY (f,)- Hz
Fig. 4- Typical dissipation characteristics.
464
10
SUPPLY VOLTS(VODJ
15
20
'2C5-19868
Fig. 5- Typical clock' frequency vs. VDO-
CD4013A Slash (/) Series
File No. 697
STATIC ELECTRICAL CHARACTERISTICS (All Inputs ... VSS ~ VI ~ VOO)
Recommended DC Supply Voltage 3 to 15 V
CHARACTERISTIC
LIMITS
SYMBOL
CHARACTERISTIC
TEST
CD4013AD,CD4013AK
UNITS
CONDITIONS
Vo
_5S o C
Voo
Volts Volts
Min.
Max.
125°C
25°C
Max. Min.
Typ.
Min.
0.005
Quiescent Device
Current
'L
Quiescent Device
Dissipation/Package
Po
2·
10
0.005
0.05
20
Output Voltage
CIRCUITS
Max.
2·
60
40·
20
400
0.025
10
N
0
CURVES
& TEST
Fig. No.
10
"A
300
0.55-
0.5-
0.01
0.01
0.05
0.01
0.01
0.05
0.5-
0.55-
"W
VOL
Low·Level
10
15
2.25-
V OH
Hlgh·Level
10
V
2.3-
400
4.99
099
9.99
9.95
14.5-
15
V
4.95
10
4.45·'
Threshold Voltage:
N-Channel
VTHN
10=
P-Channel
VTHP
t D 20 IJA
Noise Immunity
V NL
For Definition,
See Appendllf
V NH
Output Drive Current'
ION
P·Channel
9.5
~A
1.5
1.5-
. 2.25
10
3·
3·
4.5
1.•
1.5-
2.25
1.5
10
2.9-
3·
4.5
3·
10
-3· -0.33·
0.3-
V
2.911
V
-0.25-
-0.5
-0.175
-O.S
-0.65-
-1.3
-0.45
1.5-
1.5-
1.5-
2;4
mA
3, 5
V
pA
10
Input Current
mA
0.75
2.5
-0.31
V OF
V
3·
0.35
,.
1.25
-3·
1.4
0.5-
0.65
10
4.5
lOP
Oiode Test,100
Test Pin
1.5
0.5
0.5
3·
-1.5
4.2
N·Channel
-3-,
0.7-
-0.7-
0.8
IAlllnputs)
-0.7-
0.7-
20jJ.A
=
limits with black dot (_) designate 100% testing. Refer to RIC-102B "High·Reliability COS/MaS CD4000A Slash (I) Series Types". Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 1 00% testing.
Note 1: Complete functional test, all inputs and outputs to truth table.
Note 2: Test is either a one input or one output on IV.
Note 3: Test on all inputs and outputs.
For ThreshOld Voltage Test Circuits, Operating and Biased Life Test Circuits, Output Drive Current Test Circuin,
and for Operating Considerations, see Appendix.
i
'"
AMBIENT TEMPERATURE (TA)"'Z5·C
TYPICAL TEMPERATURE COEFFICIENT FOR
ALL VALUES OF VOD"0.3%
AMBIENT TEMPERATURE ITA)-25·C
TYPICAL TEMPERATURE COEFFICIENT FOR
300 ALL VALUES OF VOD"O.3 "I.'·C
,·e
Ht-':it-++t-
t
j
-I-
~
.- t-
:200
::E
t
f:+;
t-
+4-!+-
t;::;l1t
+-!-I:::.
;:
z
o
10
.10
j:: 100
.
::
~
o
~
~
~
W
~
w
o
ro
M
LOAD CAPACITANCE (CL)-pF
~
~
10
LOAD CAPACITANCE ICLJ-pF
92C5-19094
Fig. 6- Typical propagation delay time vs. CL'
Fig. 7- Typical transition time vs. CL'
465
CD4013A Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 697
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C. CL = 15 pF. and input rise an
times = 20 ns except trCL. ttCL
Typical Temperature Coefficient for all values of VOO = 0.3%JOC
LIMITS
CHARACTERISTICS
SYMBOLS
TEST
CONDITIONS
VDD
(Volts)
C04013AO.
CD4013AK
UNITS
Min.
Typ.
Max.
300
N
0
T
E
S
CLOCKED OPERATION
Propagation Delay Time
Transition Time
Minimum Clock Pulse
Width
Clock Rise &
Fall Time
tpHL·
5
-
150
tpLH
10
-
75
110-
tTHL·
5
-
75
125
tTLH
10
50
70
125
200
50
80
-
5-
10
-
5
2.5
tWL·
5
tWH
10
*trCL.
5
tfCL
10
5
Set·Up Time
Maximum Clock
Frequency
fCL
Input Capacitance
CI
10
7-
15
20
40
10
20
4
'10
-
Any Input
-
5
tpHL(R).
5
300
10
-
175
tPLH(R)
75
110
125
250
50
100
ns
1
ns
-
ns
-
ps
1
ns
-
MHz
1
pF
-
ns
-
ns
-
SET & RESET OPERATION
Propagation Delay Time.;
Minimum Set and Reset
Pulse Widths
tWH(S).
5
tWH(R)
10
en
Limits With black dot (e) designate 100% testing. Refer to RIC-l028 "High-Reliability COS/MQS CD4000A Slash
Senes Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1: Test is a one input one output only.
* If more than one unit is cascaded in a parallel clocked operation, tfel should be made less than or equal to the sum of the fixed propagation
delay at 15 pF and the transition time of the output driving stage for the estimated capacitive load.
fOV
Test performed with
the following sequence
of "1'5" and "0'5",
cL
0
o
1
0
0
o
o
o
92.CS-1790~
Fig. 8- Quiescent devic8 current test circuit.
466
s
o
3.SV
OR
7V
R
o
o
1.5V
OR
3V
92CS-17906
Fig. 9-Noise immunity test circuit.
File No. 697 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4013A Slash (I) Series
VDD
'"SET
6/8cr--~VV~~~r_--------------------------------------_,
SLAVE SECTION
RESET
VSS
Vss
ALL P·SUBSTRATES
(1~ ) CONNECTED TO VDD
ALL N·SUBSTRATES ( J~
) CONNECTED TO Vss
*" FF1/FF2 TERMINAL ASSIGNMENTS
92SM4387R1
Fig. 11- Schematic diagram (one of two identical flip-flops).
467
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 720
DDL03LJD
Solid State
Digital Integrated Circuits
Monolithic Silicon
High-Reliability Slash(/) Serios
CD4014A/ •••
Division -
High-Reliabil ity
COS/MOS a-Stage
Static Shift Register
;~::--2.
CONT.
SER. II
IN_
06
12
CLOCK!!!
•
Vss
Q7
Synchronous Parallel or SeriallnputlSerial Output
For Logic Systems Applications in Aerospace,
Military, and Critical Industrial EquipmentSpecial Features:
• Medium speed operation •••.•• 5 MHz (typ.1 clock rate at V DO - VSS = 10 V
• Fully static operation
• MSI complexity on a single chip•••••• 8 master-slave flip-flops plus output
buffering and control gating
Applications:
• Synchronous parallel input/serial output data queueing
RCA C04014A "Slash" (II Series are high-reliability COS/
MOS integrated circuits intended for a wide variety of logic
function configurations in aerospace, military, and critical
industrial equipment. C04014A types are 8-stage parallelinput/serial output registers having common Clock and
Parallel/Serial Control inputs, a single Serial Data input, and
individual parallel "Jam" inputs to each register stage_ Each
register stage is a Ootype, master-slave flip-flop. In addition
to an output from stage 8, "Q" outputs are also available
from stages 6 and 7.
Parallel as well as serial entry is made into the register synchronous with the positive clock line transition and under
control of the Parallel/Serial Control input. When the
Parallel/Serial Control input is "low", data is serially shifted
into the 8-stage register synchronously with the positive
transition of the clock line. When the Parallel/Serial Control
input is "high", data is jammed .into the 8-stage register via
the parallel input lines and synchronous with the positive
transition of the clock line. Register expansion using
multiple C04014A packages is permitted_
These types are electrically and mechanically identical to
standard COS/MOS C04014A types described in data bulletin 479 and OATABOOK 550-203 Series, but are specially
processed and tested to meet the electrical, mechanical, and
environmental test methods and procedures established for
microelectronic devices in MI L-STO-883. In addition to the
RCA high-reliability "Slash" (II Series, RCA will offer these
circuits screened to MI L-M-38510 as described in RIC-l04,
"MI L-M-38510 COS/MOS C04000A Series Types".
RCA Designation
C04014A
MI L-M-3851 0 Designation
MI L-M-3851 0/05702
• Parallel to serial data conversion
• General purpose register
The packaged types can be supplied to six screening levels /1 N, /1 R, /1, /2, /3, /4 - which correspond to MI L-STD-883
Classes "A", "B", and "C". The chip versions of these types
can be supplied to three screening levels - 1M, IN, and /R.
For a description of these screening levels and for detailed
information on test methods, procedures. and test sequence
employed with high-reliability- COSIMOS devices refer to
High-Reliability Report RIC-102C, "High·Reliability COSI
MaS CD4000A "Slash" -II) Series Types".
The C04014A "Slash" (II Series types are supplied in 16lead dual-in-line ceramic -packages ("0" suffix), in 16-lead
ceramic flat packages ("K" suffix I, or in chip form ("H"
suffix).
MAXIMUM RATINGS, Absolute-Maximum Values:
Storage-Temperature Range .......... .
Operating-Temperature Range .......... .
DC Supply·Voltage Range:
(VOO - VSSI .................... .
Device Dissipation (Per Package) ........ .
All Inputs
Recommended
DC Supply-Voltage (VDD - VSSI .....
Recommended
Input-Voltage Swing ................
Lead Temperature (During Solderingl
At distance 1/16" ± 1/32"
(1.59 ± 0.79 mm) from case
for 105 max ..................... .
-65 to +150
-55 to +125
°c
°c
-0.5 to +15 V
200 mW
VSSSVI::;VDD
3 to 15
V
VOD to VSS
+265
°C
9-74
468
File No. 720 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4014A Slash (I) Series
PARALLEL
'"PUT _I
PARALLEL
SERIAL
CONTROL
~RI'L
INPUT
CLOCIC
x
~
X· DON'T CARE
X
01
en
..... LEVEL CHANGE
TERlI.tNAlNO.I- CND
Fig. I-Logic block diagram and truth tab/e.
AMBIENT TEMPERATURE (TA 1· 25·C
LOAD CAPACITANCE eel) • 15 pF
ll:
3
~
:z
2
~
10
10 2
INPUT CLOCK FREQUENCY (fel) -
103
104
kH: 92CS-17806R3
Fig. 2- Typ. dissipation characteristics.
I
10
SUPPLY VOLTS(VOD)
15
20
Fig. 3-Tvp. clock frequency VI. V DD
469
CD4014A Slash (I) Series _ _ _ _ _- - - - - - - - - - - - - - - - _ File No, 720
STATIC ELECTRICAL CHARACTERISTICS (AI/Inputs, " VSS E;; VIE;; VOrY Recommended DC Supply Voltage 3 to 15 V
LIMITS
CHARACTERISTIC
SYMBOL
TEST
CONDITIONS
Vo
CD4014AD, CD4014AK
Quiescent Device
'L
CUrrent
Quiescent Device
Dissipation/Package
~~"C
VDD
Volts Volts
Po
Min.
5
-
5
10
-
10"
5
-
25
10
100
5
-
10
-
3
OutPUt Voltage
VOL
Low Level
-
VOH
2.25"
5
4.99
10
9.99
P·Channel
VTHN
10=-20IlA
VTHP
10 = 20llA
Noise Immunity
(AnV Input'
VNL
For Definition,
See Appendix
VNH
SS()'207
Output Drive Current:
ION
N·Channel
P·Channel
lOP
Diode Test, 100 IJA
Test Pin
VOF
Input Current
I,
ID"
25
100
-
O.S"
0
0.01
5
1.5
0.5
10
3"
4.2
5
1.4
9.5
10
2.9
0.5
5
0.15
0.5
10
4.5
5
0.D1
-
2.3"
-
-
4.99
5
4.95
9.99
10
-
9.5
10
0.31
-0.25
-
9.95
0.05
0.55"
14.45
-3"
0.3"
3"
-
1.S-
2.25
1.4
3"
4.5
-
-
1.5-
2.25
-
0.12"
-
-
-0.2"
-0.44
-
-
1.5-
-
-
4.5
0.5
2.9"
1.5
3"
1.5-
-
10
V
1
V
2
-
-0.3"
-0.16
1
0.05
3"
0.25"
V
-
-3"
-O.Os"
-
2000
1.5
0.3
IlW
1500
-1.5
:r"
-0.1
-
0.5"
-
1
300
300"
0.7"
3"
IlA
Max.
-3" -0.7"
0.7"
0.8
-
-
14.5
-0.7"
Min.
0
0.01
IS
Threshold Voltage:
N-Channel
5
2.5
-
0.01
-
0.5
10
-
3
Max.
-
0.55"
15
High-Level
Typ.
1
N
0
T
E
S
12S"C
25"C
Min.
Max.
UNITS
0.085
0.175
-0.055
-0.14
-
V
1
V
mA
2
mA
2
1.5-
V
3
-
pA
-
Limits with black dot 1_) designate 100% testing. Refer to AIC·l02B "High-Reliability COS/MOS CD4000A Slash II) Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1: Complete"functional test, all inputs and outputs to truth table.
Note 2: Test is either a one input or one output onlv.
Note 3: Test on all inputs and outputs.
For Threshold Voltage Test Circuits, Operating and Biased Life Test Circuits. Output Drive Current Test Circuits, and for Operating
Considerations, see Appendix.
AMBIENT TEMPERATURE ITAl "25·C
TYPICAL TEMPERATURE COEFFICIENT FOR
ALL VALUES OF VOO" 0.3 %/"C
I
"e
5
f
~M8IENT TEMPERATURE ITA) ,,2S·C
TYPICAL TEMPERATURE COEFFICIENT FOR
600 ALL VALUES OF Voo • 0.3% / ~C
-'5
'... sao
S500
!
.
w
g
is
.
200
~
100
~
1f
;: 300
30
10
is
0Il)
z
200
D1
0
... 100
10
20
30
40
50
60
70
80
lOAD CAPACITANCE (Cll - pF
92CS-17807
Fig. 4-Typ. propagation delay time VI. CL"
470
10
20
30
40
50
60
lOAD CAPACITANCE ICll -
70
80
pF
92CS-17808
Fig. 5- Typ. transition time n. CL"
File No. 720 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4014A Slash (/) Series
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C. CL
=
15 pF, and input rise and fall times = 20 ns except trCL, t,cL
Typical Temperawre Coefficient for all values of V DD = a3%~C (See Appendix for Waveforms).
LIMITS
CHARACTERISTICS
SYMBOLS
TEST
CONDITIONS
VDD
(Volts)
CD4014AD, CD4014AK
UNITS
N
0
T
E
S
Min.
Typ.
Max.
Propagation Delay Time
tpHl·
tplH
5
10
-
300
100
750
225-
ns
1
Transition Time
tTHl'
tTlH
5
10
-
150
75
300
125
ns
-
Minimum Clock
Pulse Width
tWl'
tWH
5
10
200
100
500
175
ns
-
Clock
Rise & Fall Time
trCl'
tfCl'
5
10
-
15
15-
J.l.s
1
ns
-
-
MHz
1
-
pF
-
Set-Up Time
Maximum Clock
Frequency
fCl
Input Capacitance
5
10
-
100
50
350
80
5
10
1
3-
2.5
5
-
Any Input
CI
-
-
5
Limits with biack dot (.) designate 100% testing. Refer to RIC-102B "Hi9h-Reli~bility COS/MOS CD4000A Slash (I) Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1: Test is a one input one output only_
* If more than one unit is cascaded tteL should be made less than or equal to
the sum of the fixed propagation delay at 15 pF and the transition
time of the output driving stage for the estimated capacitive load.
10V
r-----------------~~~~L
5V OR IOV
1.5Y OR 3V
92C5-17908
9~CS-17907
Test performed with the following
sequence of "l's" and "O's"
Fig. 7-Noise immunity test circuit.
51 52 53 54 55
Don't
Test
Test
Test
Test
Test
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
1
0
0
Fig. 6-Quiescent dellice current test circuit
471
CD4014A Slash (Il Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--:-_ _ _ _ File No. 720
F --::0--
PARAlLEL 1E1JIAL JD
CONTROL
_
~
· 9
,:JJlL
-!
LJ~
1_
PARALLEL
--I
I
I
'P
1,1S
I
I ,L
I~
P
'IS
--FIIHTiiEoismsTAG'E'iONE O'FEiGHTSTAGEs)- - -
Q
TO STAGE 2
'NPUTftll
_~ nd'· nBI ~
'NPu~~lJ~9I
"L "L '"t..,
I I~
I ~ fLr- CLr~'DD
I ~'D'
CL~ Il._ _~ I ~~L
~~ 11J~
I ' 1 ~\~:
L __
'""L'IS
'IS
Q-
9
Vss
n
T'
'IS
-UNIT\UB'TR.TE' .RE CONNECTED
'IS
AlL . N . _UNIT 'UBITRnE' .RE CONNECTED
TOYSS______
Fig. 8-Schematic diagram - CD4D14A.
472
I
~~8_J
-~~
rr-!
,I
I'
I'I'
I -{]
~
BUFFERED OUTPUT
~ I
~.~~).
9I
'\I
~~6~_J
7.'81
File No. 721
OO(]5LJD
Digital Integrated Circuits
Monolithic Silicon
Solid State
Division
VDD
DATA A
Cl.OCKA
4
STAGE
RESET A
0,_
0"
0,.
0..
" 0,.
0,•
0,.
0••
ID
DATA a
CLOCKp
RESETs
IS
,.
.
12
STAGE
Vss
High-Reliability Slash (I) Series
CD4015A/ •..
High-Reliability
COS/MOS Dual 4-Stage
Static Shift Register
With Serial Input/Parallel Output
For Logic Systems Applications in Aerospace,
Military, and Critical Industrial Equipment
Special Features
• Medium speed operation....•• 5 MHz (typ.) clock rate at Vee - Vss = 10 V
• Fully static operation
.
• MSI complexity on a single chip•..••. 8 master·slave f1ip·f1ops plus output
buffering
Applications
• Serial·input!parallel·output data queueing
RCA CD4015A "Slash" (II Series are high·reliability COS/
MOS integrated circuits intended for a wide variety of uses
in aerospace, military, and critical industrial equipment.
CD4015A types consist of two identical, independent,
4-stage serial input/parallel·output registers. each register has
independent "Clock" and "Reset" inputs a~ well as a single
serial IIData" input. "a" outputs are available from each of
the four stages on both registers. All register stages are D·
type, master·slave flip·flops. The logic level present at the
d~ta input is transferred into the first register stage and
shifted over one stage at each positive·going clock transition.
Resetting of all stages is accomplished by a high level on the
reset line. Register expansion to 8 stages using one CD4015A
package, or to more than B stages using additional CD4015A
packages is possible.
These devices are electrically and mechanically identical with
standard COS/MOS C04015A types described in data bulle·
tin 479 and OATABOOK SSD·203 Series, but are specially
processed and tested to meet the electr!cal, mecha'licai, and
environmental test methods and procedures established for
microelectronic devices in MI L·STO·BB3. In addition to the
RCA high·reliability "Slash" (/) Series, RCA will offer these
circuits screened to MI L·M·3B510 as described in RIC·I04,
"MIL·M·3B510 COS/MOS C04000A Series Types".
RCA Designation
C04015A
MIL·M·3B510 Designation
MI L·M·3B51 0/05703
The packaged types can be supplied to six sereening levels IIN,IIR, 11,/2,/3,14 - which correspom;l to MIL·STO·8B3
Classes "A", "B", and "C". The chip versions of these types
can be supplied to three screening levels - 1M, IN, and IR.
• Serial to parallel aata conversion
• General purpose register
For a description of these screening levels and for detailed
information on test methods, procedures, and test sequence
employed with high·reliability COSIMOS devices refer to
High·Reliability Report RIC·102C, "High·Reliability COS/
MaS CD4000A "Slash" (II Series Types".
The C04015A "Slash" (II Series types are supplied in 16·
lead dual·in·line ceramic packages ("0" suffix I, in 16·lead
ceramic flat packages ("K" suffix I, or in chip form ("H"
suffix!'
MAXIMUM RATINGS, Absolute·Maximum Values:
Storage-Temperature Range ..........
Operating-Temperature Range ..........
DC Supply·Voltage. Range:
(VDD - VSSI ....................
Device Dissipation (Per Package) ........
. -65 to +150 °c
. -55 to +125 °C
. -0.5 to +15 V
.
200 mW
All Inputs ......................... . VSS S. VI:S VOO
Recommended
3 to 15
V
DC Supply·Voltage (VDD - VSSI .....
Recommended
Input·Voltage Swing ............... . VDD to VSS
Lead Temperature (During Soldering)
At distance 1/16" ± 1/32"
(1.59 ± 0.79 mml from case
for 10 s max ..................... .
9·74
473
CD4015A Slash
II)
Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
File No. 721
D.
TRUTH TABLE
".
CL·
.r
.r
D
R
0
0
Ql
0
1
0
1
"\... x
0
X
1
Ql
0
x
Qn
Qn·l
Qn·l
Qn
0
,,
NO
HANG lEI
•• LEVEL CHANGE
X. DON'T CARE CASE
CLa
TERMINAL PlO. 16· Veo
TERMINAL NO. 8 ~ GHD
Fig. 1-Logic diagram and truth table.
AMBIENT TEMPERATURE (TA) ·25·C
AMBIENT TEMPERATURE (TAl· 25·C
LOAD CAPACITANCE eel). 15 pF
TYPICAL TEMPERATURE COEFFICIENT FOR
ALL VALUES OF Voo -O,'3%'-C
6
[jl
if
3
~
z
2
~
I
u
10
15
o
10
SU~PLY VOLTSIYool
15
20
92CS-19B67
Fig. 2- Typ. clock frequency ... V DU
474
10
20
30
40
50
60
70
LOAD CAPACITANCE (ell -pF
Fig. 3- Typ. propagation delay time va. CL"
80
CD4015A Slash (I) Series
file No. 721
STATIC ELECTRICAL CHARACTERISTICS (AI/Inputs • •• VSS '" V, '" V OO'
Recommended OC Supply Voltage 3 to 75 V
LIMITS
CHARACTERISTIC
SYMBOL
TEST
CONDITIONS
CD4015AD. C04015AK
-55·C
Vo VOO
Volts Volts
Min.
Max.
Min.
Quiescent Device
Current
Quiescent Device
Dissipation/Package
IL
0.5-
10
Po
2.5
10
VOL
VOH
Noise Immunity
(Any Input)
For Definition.
See Appendix
550·207
OJtput Drive Current:
\N·Channel
P-Channel
ION
lOP
Diode Test. 100 IJA
Test Pin
VOF
Input Current
II
100
0
0.01
0.05
0.D1
0
0.01
0.05
0.5·
0.55·
3
2.25·
2.3·
4.99
4.99
10
9.99
9.99
4.95
10
14.46-
-0.7·
-1.5
-3-
.-0.7°
_3°
3·
0.7-
1.5
3·
0.7·
3·
1.5
1.5-
2.25
1.4
10
3·
3·
4.5
2.9·
1.4
1.5-
2.25
1.5
10
2.90
3·
4.5
3·
0.15
0.125·
0.3
O.OSS
0.5
10
0.31
0.25·
0.5
0.175
4.5
5
9.5
10
0.5
V
V
-3·
4.2
pW
9.95
14.5-
O.S
pA
0.5·
0.3·
10 = -20pA
10=20pA
VNH
1500
·0.3·
VTHN
VTHP
VNL
10·
2.5
0.D1
15
P·Channel
Max.
JOO
10
0.55·
3
15
Threshold Voltage:
N·Channel
Min.
0.5·
25
10
Hi9.h-Level
Max.
0.5
Output Voltage
Low-Level
Typ.
UNITS
125·C
25°C
N
0
T
E
S
-{l.1
-{l.OS·
-{l.16
-0.055
·-0.25
-O.~
-{l,44
-0.14
1.5-
1.5-
10
V
V
V
mA
-
1.5-
mA
V
pA
Limits with black dot Ie) designate 100% testing. Refer to RIC·l02B "High-Reliability COS/MOS CD4000A Slash (f) Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1: Complete functional test, all inputs and outputs to truth table.
Note 2: Test is either a one input or one output only.
Note 3: Test on all inputs and outputs.
For Threshold Voltage Test Circuits. Operating and Biased Life Test Circuits. Output Drive Current Test Circuits, and for Operating
Considerations. see Appendix.
475
CD4015A Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 721
DYNAMIC ELECTRICAL CHARACTERISTICS at TA ~ 25°C and CL ~ 15 pF
Typical Temperature Coefficient for all values of VDO = O.3'J61'C. (See Appendix for Waveforms)
LIMITS
CHARACTERISTICS
TEST
CONDITIONS
SYMBOLS
VDD
IVoltsl
N
0
CD4015AD.
CD4015AK
Min.
UNITS
Typ.
Max.
T
E
S
CLPCKED OPERATION
tpHL'
tpLH
5
-
300
750
10
-
100
225.
tTHL'
tTLH
5
300
75
125
Minimum Clock Pulse
Width
tWL'
tWH
5
-
150
10
200
500
10
-
100
175
Clock Rise & Fall Time
*trCL'
ttCL
5
10
-
-
-
100
350
10
50
80
5
1
2.5
-
Prollagation Delay Time
Transition Time
5
Set-UpTime
Maximum Clock
Frequency
tCL
Input Capacitance
CI
10
ns
1
ns
-
ns
-
jlS
1
ns
-
MHz
1
pF
-
ns
-
ns
-
15
15.
3.
5
-
5
5
-
300
750
10
100
225
5
-
200
500
10
-
100
175
RESET OPERATION
Propagation Delay Time
tPHLIRl
Minimum Set and Reset
tWHIRl
Pulse Widths
* If more than one unit Is cascaded in a parallel clocked operation, t,CL should be made less than or equal to the sum of the fixed propagation
delay time 8t 15pF and the transition time of the output driving stage for the estimated capacitive load.
Limits with black dot (.) designate 100% testing. Refer to RIC·l02B "High-Reliability COS/MOS C04000A Slash (/I Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
NOTE 1. Test Is a one Input one output only.
~
AMBIENT TEMPERATURE (TAl • 2~·C
TYPICAL TEMPERATURE COEFFICIENT FOR
600 ALL VALUES OF Voo. 0.3% I co\:
3:500
!II
,... 300
z
o
~
i\l
200
,... 100
lOAD CAPACITANCE ICl)-15pF
- - - - CL-SOpF
10
20
30
40
50
60
LOAD CAPACITANCE (Cl) -
70
80
pF
92CS-17808
Fig. 4-Typ. transition time VB. CL"
476
10
10 2
INPUT CLOCK FREQUENCY "Cl) -
103
104
kHz 92CS-17806R3
Fig. 5- Typ. dissipation characteristics..
File No. 721 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4015A Slash (I) Series
IOV
92CS-17909
Test performed with the following
sequence of "1's" and "0'5"
51 5 2 53
Test
Don't Test
Oon't Test
Oon't Test
Don't Test
Oon't Test
Test
Don't Test
Test
Fig.
0
0
0
0
0 1
0 0 0
1 0 0
0 0
0 1
0 0 0
0 0
Fig. 7-Noise immunity test circuit.
6-0uiescent device current
test circuit.
I
I
I
TO OATA INPUT
OF STAGE NO.2
I
I
I
I
CL
~
ALL P SUBSTRATES ARE CONNECTED TO VOO
ALL N SUBSTRATES ARE CONNECTEO TO VSS
Fig. 8-Schematic diagram.
477
File No. 744
oornLJD
Digital Integrated Circuits
Monolithic Silicon
Solid State
High-Reliability Slash(/) Series
CD4016A/ ...
Division
High-Reliability
COS/MOS Quad Bilateral Switch
For Transmission or Multiplexing of Analog or Digital Signals
For Logic Systems Applications in Aerospace,
Military, and Critical Industrial Equipment
Special Features
• Wide range of digital and analog signal levels ~igital or analog signal to 15 V peak
Analog signal ± 7.5 V peak
• Low "'ON" resistance300 n typo over 15 Vpl' signal input ranga. for VOO - VSS = 15 V
• Matchad switch characteristics 40 n typo difference between RON values at a fixed bias point over 15 Vp.p
signal input ranga VOO - Vss = 15 V
• High "On/Off" output voltage ratio - 65 dB type@fis = 10 kHz. RL = 10 kn
• High degree of linearity - < 0.5% distortion typo @fis = 1kHz.
Vis = 5V p.p • VOO-VSS ;;'10 V. RL = 10 kn.
RCA C04016A "Slash" (I) Series are high·reliability COSI
MOS integrated circuits intended for a wide variety of logic
function configurations in aerospace. military. and critical
industrial equipment. These devices are electrically and me·
chanically identical with standard COS/MOS C04016A types
describedin data bulletin 479 and DATABOOK SSO·203
Series, but are specially processed and tested to meet the
electrical. mechanical, and environmental test methods and
procedures established for microelectronic devices in MI L·
STD-883. In addition to the RCA high·reliability "Slash"
III Series, RCA will offer these circuits screened to MI L·M·
38510 as described in RIC·I04, "MIL·M·38510 COS/MOS
CD4000A Series Types".
RCA Designation
CD4016A
MI L·M·3851 0 Designation
MI L·M·3851 0/05801
The packaged types can be supplied to six screening levels lIN, 11 R, II, 12, 13, 14 - which correspond to MI L·STD·B83
Classes "A", "B", and "C". The chip versions of these types
can be supplied to three screening levels -1M, IN, and IR.
Applications
• Analog signal switching/multiplexing
Signal gating
Modulator
Squelch control
Demodulator
Chopper
Commutating switch
• Digital signal switching/Multiplexing
• COS/MOS logic implementation
• Analog·to-digital & digital·to·analog conversion
• Digital control of frequency. impedance, phase, and
analog·signal gain
• Extremely low "OFF" switch leakage resulting in very low
offset current and high effective "OFF" resistance10 pA typ,@VOO-VSS= 10V, TA =25° C
• Extremely high control input impadance (control circuit
isolatad from signal circuit! - 10 12 n typo
• Low crosstalk between switches -50 dB typo @fis = 0.9 MHz. RL = 1 kn
• Matchad control·input to signal-output capacitances Reduces output signal transients
• Transmits frequencies up to 10 MHz
For a description of these screening levels and for detailed
information on
employed with
High·Reliability
MOS CD4000A
478
test methods, procedures, and test sequence
high·reliability COSIMOS devices refer to
Report RIC·l02C, "High·Reliability COSI
"Slash" (I) Series Types".
The CD4016A "Slash" (I) Series types are supplied in 14·
lead dual·in·line ceramic packages ("0" suffixl, in 14-lead
ceramic flat packages ("K" suffix I, or in chip form ("H"
suffixl.
9-74
File No. 744 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4016A Slash (/) Series
141 Voo
CONTROL
VD~ ~orE
__
vss--
J
l
IVe
l3
r---~---t--
voo
INPUT SIGNALS (VI.)
TERMINAL Nos,I,4.8.11
II~INJOUT
!
_
~
~N
JUTPUT SIGNAL5 lVo.1
rERMINAL Not. 2,3,9,10
"'ALL GATE INPUTS PROTECTED
e.!
I
BY STANDARD COS/MOS
DIODE
;I:~T/N
All switch P-channeJ substrates are internally connected to terminal No. 14.
All ~wilch N·channcl substrates are internallv connected to terminal No.7.
NOTE:
C,llltlon:
If Vh
1lI11:tt
t!KCl:t:CI:. VOD' input currents
nut be allowed to exceed 5 rnA.
92SM-383E1R2
SWITCH 0
SWITCH B
SWITCH A
NETWORK
NORMAL OPERATION:
Control·Line'Biasing
Switch "ON": Vc "1" .. VOO
Switch "OFF": Vc "0" "" VSS
SIGNAL·LEVEL RANGE:
VSS~ Vis =s;;;; V OD
Fig. t-Schematic diagram.
Recommended
MAXIMUM RATINGS. Absolute-Maximum Values:
Storage-Temperature Range .......... . -65 to +150
Operating-Temperature Range .......... . -55 to +125
V
3 to 15
DC Supply-Voltage (VDD - V SS )
°c
°c
Recommended
Input-Voltage Swing ................ VDD to VSS
Lea(l Temperature (During Soldering)
At distance 1/16" ± 1/32"
(1.59 ± 0.79 mm) from COSI)
I'){i!;
for 10 s max . . . . . . .
DC'Supply-Voltage Range:
(VDD -VSS) .................... . -0.5to+15 V
200
mW
Ol!vice Dis!.ipation (Per PilckilUe)
Allillput',
VSS
I;
;£
~ -I
~>+~Kj-J
0
-2
VC'~OD
-2
-.
INPUT SIGNAL VOLTS (VIS)
92CS-'7836
Fig. 6- Typ. "ON u characteristics for 1 of 4 switches with
VOO=+5V. VSS =·5V.
482
Vos
_
-2
-I
o
I
RL
2
INPUT SIGNAL VOLTS (VIS)
3
92C5-11839
Fig. 7- Typ. I'ON" characteristics for 1 of
4 switches with V DD - +2.5V.
VSS ··2.5V.
File No. 744 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4016A Slash (I) Series
Ir
J.
pPLY VOLTS: VDD-+5. VSS-·5
CONTROL VOLTS IVe). ~5
INPUT SIGNAL VOLTS (Vis)-S Vp_p SINE WAVE (1.77 RMS)
30 LOAD CAPACITANCE (CU-CFIXTURE +CMETER"2.3+2.!I-4;8pF
t.,
~:~~~:UR~~'~8~;TER
g
25
d
:>
20
::;
sf.ITqff
T
i !L:
•
,"
""'-'"""
~~~r~I~~~'O
jf
VI.Nt
~
'" 10 with multiple CD4017A's
• For further application information, see ICAN6166
"COS/MOS MSI Counter and Registe'- Design &
Applications"
Johnson decade counter configuration permits high speed
operation, 2-input decimal decode gating, and spike-free
decoded outputs. Anti-lock gating is provided, thus assuring
proper counting sequence_ The 10 decoded outputs are
normally "low" and go "high" for one full clock cycle_
A carry-out (COUT) signal completes one cycle every 10
"9"
TERMINAL NO. B. GND = Vss
TERMINAL NO. 16 = Vao
Fig.1-Logic diagram_
92$S-414SRl
484
9-74
File No. 7 4 1 - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4017A Slash (/) Series
clock input cycles and is used to directly clock the
succeeding decade in a multi·decade counting chain.
These devices are electrically and mechanically identical
with standard COS/MaS C04017A types described in data
bulletin 479 and OATABOOK SSO·203 Series, but are
specially processed and tested to meet the electrical, mechanical, and environmental test methods and procedures
established for microelectronic devices in MI L·STO·8B3.
In addition to the RCAhigh·reliability"Slash" (I) Series." RCA
will offer these circuits screened to MI L·M·38510 as de·
scribed in RIC·l04, "MIL·M·38510 COS/MaS C04000A
Series Types".
RCA Oesignation
C04017A
MI L·M·3851 0 Oesignation
MI L·M·38510/05601
The packaged types can be supplied to six screening levels /1 N. /1 R, /1, /2, /3, /4 - which correspond to MI L·STD,883
Classes "A", "B", and "C". The chip versions of these types
can be supplied to three screening levels - /M, /N, and /R.
For a description of these screening levels and for detailed
information on test methods, procedures, and test sequence
employed with high·reliability COSIMOS devices refer to
High·Reliability Report RIC·l02C, "High· Reliability COSI
MOS CD4000A "Slash" II) Series Types".
The C04017 A "Slash" (I) Series types are supplied in 16·
lead dual·in-line ceramic packages ("0" suffix), in 16-lead
ceramic flat packages ("K" suffix), or in chip form ("H"
suffix).
CLOCK
RESET
'
...._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CLOCKE~N~AB~L~E~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _..J~
"0"
"\"
"2"
_ _-..Jfl'....___________-..Jr2l-
"S"
____
_____
_____________
"6"
________
"3"
"4"
"7"
"S"
"9"
~f3l
~f4l~
,_________________________
....--____________________
~f5l
-Jf6l~
___________
---------~f7I~------____________
________
~ral~
_________________
~G\~======
CARRY OUT
nSs-4146RI
Fig. 2- Timing diagram.
.,-----1-------- ~g~~
t6
f. CLOCK.;. tI'
t-'==-1--'-"""~""''''-'--f-o- :~!E:~A2T;OC~~T
,. CLOCK.,.N
I
I
I
L ______________ ..:. ____ J
Fig. 3- D/."de by N counter (N ~ 10) with N dBcoded outpUts.
When the Nth decoded output is reached (Nth clock pulse)
the $oR flip flop (constructed from two NOR gates of the
C04001A) generates a reset pulse which clears the C04017 A
to its zero count. At this time, if the Nth decoded output is
greater than or equal to 6, the COUT line goes "high" to
clock the next C04017A counter section. The "0" decoded
output also goes high at this time. Coincidence of the clock
"low" and decoded "0" output "low" resets the S,R flip
flop to enable the C04017 A. If the Nth decoded output is
less tlian 6, the COUT line will not go "high" and, therefore, cannot be used. In this case "0" decoded output may
be used to perform the clocking function for the next countere
485
CD4017A Slash (II Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
File No. 741
STATIC ELECTRICAL CHARACTERISTICS (AI/Inputs •• • VSS<' V, <. VDrY Recommended DC Supply Valtag.3 to 15 V '
LIMITS
CHARACTERISTIC
SYMBOL
TEST
CONOITIONS
Vo
VOO
Volts Volts
Quiescent Device
Current
5
Quiescent Device
OissipationlPackage
Po
Low-Level
5
VOL
Threshold Voltage:
N·Channel
P-Channel
VOH
P-Channel
Test Pin
5
0.5
10-
5
-
-
-
0
-
-
2.25-
2.3-
5
4.99
10
9.99
15
-
25
100
0.5-
0
15
-
0.3
1.5
3
-
4.99
5
9.99
10
14.5-
-
0.01
0.Q1
Min.
-
Mo••
300
2001500
2000
-
0.05
-
0.05
0.5-
-
0.55-
-
-
-
-
4.95
9.95
14.45-
-3-
-0,7-
-1.5
-3-
-O,~
-3-
~
0.7-
1.5
3-
0,3-
3-
1,5-
2.25
4,S
VNL
1
4.2
10
-
1.5
3-
-
3-
5
1.4
1.5-
2.25
10
2.9-
-
3-
4.5
Decoded 0,5
Outputs 0.5
5
0.06
-
0.05-
0.1
10
0.12
0.1-
0.4
Cerry
0,5
5
0.185
0.15-
0.4
Output
0,5
10
0.45
0.35-
1
Decoded
4.5
5
O.O~
-0.075
Outputs
9.5
10
-0.12
CarrV
Output-
4.5
5
9.5
10
VNH
9
ION
lOP
-
0.0375
-
-0.1-
-0.2
-0.185
-0.15-
-0,4
-0.45
-0,35-
-1
VOF
II
-
1.5-
-
-
1,4
-
2.9-
-
1.5
3-
-
-
0,035
-
0.07
-
0,25
-0.021
-0.07
1
jN/
-
V
1
V
1
V
2
V
V
1
-
0,105
-
i'A
-
0.75
T
E
S
-
-0.7-
0.8
0
-
IO-20pA
Oiod. T.... 100 i'A
Input Current
-
125"C
Mo••
10 --20i'A
Output Orive Current
N-Channel
0.Q1
-
Tva.
VTHN
For Definition,
S.. Ap(J(lfldix
550·207
0,01
Min.
VTHP
Noise Immunity
(Any Inputl
100
0.55-
-
3
10
High·Levei
25
10
Output Voltage
Mo ••
5
10-
-
10
UNITS
25"C
-SS"C
Min.
5
IL
N
C04017AO. C04017AK
-
-0.105
rnA
2
rnA
2
-0.25
-
1.5-
10
-
-
1.5-
V
3
pA
-
Limits with black dot (e) designate 100% testing. Refer to RIC·1Q2B "High-Reliability COS/MOS CD4000A Slash (t) Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing,
Note 1: Complete'functionallest. all inputs and outputs to truth table.
Note 2: Test is either a one input or a one output onlv.
Note 3: Test on all inputs and outputs.
MAXIMUM RATINGS, Absolute·Maximum Values:
Storage-Temperature Range ,.".,' .. ,. -65 to +150 °c
Operating·Temperature Range, ' . , ... , .. , -55 to +125 °c
DC Supply·Voltage Range:
(VDD - VSS) .. , . , , , .. , , , .... , .... -0.5 to +15 V
Device Dissipation (Per Package) ... , , , , ..
200 mW
All Inputs .... , .... , ...... ,.' ... , .. . VSSSVISVDD
Recommended
DC Supply·Voltage NDD - VSS) , ... ,
3to 15
V
486
Recommended
Input·Voltage Swing, .. , .. , ... , , .... VDD to VSS
Lead Temperature (During Soldering)
At distance 1'16" ± 1'32"
11.59 ± 0.79 mm) from case
for 10 5 max. . .. , ...... ' ...... ' .. .
+265
°c
File No. 741 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4017A Slash {II Series
DVNAMIC ELECTRICAL CHARACTERISTICS, at TA - 25"C, CL - 15 pF, and input ,ise and fall times - 20 ns except t,CL, t,cL
Typical Temperature Coefficient for all values of VOO = O.3%/ oC.
LIMITS
CHARACTERISTICS
TEST
CONDITIONS
VDD
(Voltsl
SYMBOLS
CD4017AD.
CD4017AK
Min.
Typ.
Max.
1000
UNITS
N
0
T
E
S
ns
1
ns
1
ns
1
ns
1
ns
-
jls
1
ns
-
MHz
-
pF
-
ns
-
ns
-
ns
-
ns
-
CLOCKED OPERATION
5
-
350
10
-
125
5
5
-
10
-
5
300
900
125
350.
Propagation Delay Time:
Corry Out line
tpHl'
tpLH
Decode Out lines
10
. Transition Time:
Corry Out line
tTHL
250.
500
1200
200
400.
100
300
50
160.
Minimum Clock •
tWl:
5
-
200
500
Pulse Width
tWH
10
-
100
170
trCl'
5
'tCl
10
-
-
t TLH •
Decode Out lines
10
Clock Rise & Fall Time
Clock Enable Set·Up
5
Time
10
tCl
Input Capacitance
500
75
200
5
1
2.5
-
3.
6
-
-
5
-
Any
Input
CI
175
10
Maximum Clock
Frequency
15
15.
RESET OPERATION
Propagation Delay Time:
5
-
350
1000
To Corry Out Line
10
-
125
250
5
450
1200
200
400
5
-
200
500
10
-
100
165
5
-
300
750
100
225
tpHL(R)
To Decode Out Lines
10
Reset Pulse Width
WH(RI
Reset Removal Time
10
Limits with black dot I_I designate 100""(' testing. Refer to RIC-l02B "High-Reliability COS/MOS CD4000A Slash (f) Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1: Test Is a one Input ono output only.
•
Measured with respect to carry output line
10V
5VORIOV
Test performed with the following
I"
sequllncil of "l's and "O's" at each stage.
81
1
0
0
0
0
a
82
1
a
1
0
1
0
sa
81
1
0
0
0
0
0
a
0
0
Fig. 4 -.Quiescent device current test circuit.
a
0
0
a
82
1
0
1
83
a
a
1
0
1
0
0
0
a
0
0
~
DVM
TO
-:="
15
3
,
OUAT~1JT 5
"
7
I'
13
12
0--0
1.5 V
OR
3V
11
10
92CS-17912RI
Fig. 5 - Noise immunity test circuit.
487
CD4017A Slash (f) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 741
AMBIENT TEMPERATURE (TAJ c 25-C
~
TYPICAL TEMPERATURE COEFFICIENT FOR
I
1500 ALL VALUES OF Voo· 0.3"4 ,·C
..
500
J..
-'
~
600
.i
}
1
.i
1000
SUPPLY . VOLTS (Vool = 5
....
200
1f
100
~
30
40
50
70
60
LOAD CAPACITANCE (e l ) -
300
~
15
~
10
20
400
:I
11
10
AMBIENT TEMPERATURE (TA)-.25°C
TYPICAL TEMPERATURE FOR At L
VALUES OF Voo ·O.3%'-C
\0
\5
80
10
20
pF
30
40
50
60
LOAD CAPACITANCE (CL) -
10
80
pF
92CS-17826
Fig. 6 - TyP. propagation delay time
CL for decoded outputs.
!! 1500
Fig. 7 - -Typ. propagation delav time
for carry output.
Vof.
AMBIENT TEMPERATUtlE (TA) -25·C
TYPICAL TEMPERATURE COEFFICIENT FOR
ALL VALUES OF Voo" 0.3 -to/·C
VI.
CL
AMBIENT TEMPERATURE (T A) • 25·C
YPiCAL TEMPERATURE COEFFICIEN
300 FOR ALL VALUES OF VOD z O.3 %I·C
I
}
'W
SIOOO
'l!
....
z
10
~ 100
~
10
o
10
20
15
i!:
15
30
40
50
60
LOAD CAPACITANCE (CL1-pF
70
80
10
20
30
40
50
60
LOAD CAPACITANCE (CL1- pF
70
U.CS-11828
80
92CS-17879RI
Fig. 9 - Typ. transition time VB. t;L for
carry output.
Fig. 8 - TyP. transition time vs. CL for
decoded outputs.
AMBIENT TEMPERATURE (TA ) • 25·C
LOAD CAPACITANCE eel). 15 pF
6
~.
::: 3
~
z
~
2
I
LOAD CAPACITANCE (Cl)-15pF
- - - - Cl .50pF
o
10
SUPPLY VOLTS(Voo)
15
20
92CS-19867
10
102
INPUT CLOCK FREQUENCY (tCl) -
103
10'
kHz
92CS-17829RI
Fig. 10 - Typ. clock frequency vs. V DO'
488
Fig. 11 - -Typ. dissipation characterlstics.
.File No. 742 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
OO(]5LJI]
Digital Integrated Circuits
Monolithic Silicon
Solid State
Division
IN~t"lS
High-Reliabilty
COS/MOS
Presettable Divide-By-'N' Counter
\IDe
~
"I" "3" "5"
0,
CLOCK
RESET
02
Special Features
• Medium speed operation. . • . . 5 MHz (typ.) at VDD - VSS = 10 V
• Fully static operation
- MSI complexity on a single chip
" -0 ,
13 05
Vss 8
For Logic Systems Applications in Aerospace,
Military, and Critical Industrial Equipment
0,
· -J
.
High-Reliability Slash{/) Series
CD4018A/ •••
Applications
•
•
"
•
Fixed and programmable divide·by·10, 9, 8, 7,6,5,4,3,2 counters
Fixed and programmable counters greater than 10
Programmable decade counters
• Frequency division
Divide·by·"N" counters/frequency synthesizers
• Counter control/timers
RCA CD4018A "Slash" (/) Series are high·reliability cost
MaS integrated circuits intended for a wide variety of uses
in aerospace, military, and critical industrial equipment.
CD4018A types consist of 5 Johnson·Counter stages, buf·
fered a outputs from each stage, and counter preset control
gating. "Clock", "Reset", "Data", "Preset Enable", and 5
individual "jam" inputs are provided. Divide by 10, 8, 6, 4,
or 2 counter configurations can be implemented by feeding
the as, a4, 03, 02, a1 signals, respectively, back to the
Data input. Divide-bY-9, 7. 5, or 3 counter configurations
can be implemented by the use of a CD4011 A gate package
to properly gate the feedback connection to the Data input.
Divide-by functions greater than 10 can be achieved by use
of multiple CD4018A units. The counter is advanced one
count at the positive clock-signal transition. A "high" Reset
signal clears the counter to an "all-zero" condition. A "high"
Fig. I-Logic Diagram.
489
CD4018A Slash
(II Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Preset-Enable signal allows information on the Jam inputs to
preset the counter. Anti-Jock.gating is provided to assure the
proper counting. sequence.
These devices are electrically and mechanically identical with
standard CD4018A types described in data bulletin 479 and
DATABDOK SSD-203 Series, but are specially processed and
tested to meet the electrical, mechanical, and environmental test methods and procedures established for microelectronic devices in MI L-STD-883. In addition to the RCA
high-reliability "Slash" (/) Series, RCA will offer these circuits screened to MIL-M-38510 as described in RIC-l04,
"MI L-M-3851 0 COS/MOS CD4000A Series Types".
RCA Designation
MI L-M-3851 0 Designation
CD4018A
MI L-M-3851 0/05602
The packaged types can be supplied to six screening levels 11N,I1R, /1,12,/3, /4 - which correspond to MIL·STD-SS3
Classes "A", "B", and "C". The chip versions of these types
can be supplied to three screening levels -1M, IN, and IR.
For a description of these screening levels and for detailed
information on test methods, procedures, and test sequence
employed with high-reliability COS/MOS devices refer to
High-Reliability Report RIC-702C, "High-Reliability COS/
MOS CD4000A "Slash" (/l Series Types".
CD4018A "Slash" (I) Series types are supplied in 1&Iead
dual-in-line ceramic packages ("D" suffix), in 16-lead ceramic flat packages ("K" suffix), or in chip form ("H" suffix).
MAXIMUM RATINGS, Absolute·Maximum Values:
Storage·Temperature Range ........ . ..
Operating-Temperature Range .......... .
DC Supply·Voltage Range:
(VDD - VSS) .................... .
Device Dissipation (Per Package) ........ .
All Inputs
Recommended
DC Supply·Voltage (VDD - VSS) .....
Recommended
Input·Voltage Swing ................
. Lead Temperature (During Soldering)
At distance 1/16" ± 1/32"
(1.59 ± 0.79 mm) from case
for 10 s max. .....................
r'DATA' INPUT TIED TO
-65 to +150
-55 to +125
0c
CLOCK
°c
RnET
OJ
FOR DECADE COUNTER CONFIGURATIONl
tt tt~
I
PRESET
-0.5 to +15 V
200
mW
It rt·I tt r-r- r-r- r-r- tt
!
I,
I
i
Ii!
VSS:::;VI~VDD
3 to 15
File No. 742
OOt.rTCAAEUNTLL
V
I
Ja",s
Ii,
VDD to VSS
I
I
I
I
I
!
II
I
I I
I-
ii,
Ir
P=
h
Ii,
ii,
+:./tit>"C
I I I I I I
,
PRESET" GOE5HIGHI
I
n-rrn
I I I I IIITI
I
I I
92SS-4141R2
Fig" 2- Timing diagram.
AMBIENT TEMPERATURE (TA)" 2S·C
~
I
TYPICAL TEMPERATURE COEFFICIENT FOR
1500 ALL VALUES OF Yoo· 0.3%
I-e
}
....
J IOoo
!;l
SUPPLY 'VOLTS (VDD)·
e
;:
g
~
300
iii
200
~
10
if
~
10
20
30
40
50
60
LOAD CAPACITANCE -_____-I___-,
479 and OATABOOK 550·203 Series, but are specially
processed and tested to meet the electrical, mechanical, and K.
environmental test methods and procedures established for 0---1>-",
microelectronic devices in MIL·STO·883. In addition to the
RCA high·reliability "Slash" (I) Series, RCA will offer these
circuits screened to MIL·M-385l0 as described in RIC·l04,
"MIL·M-385l0 COS/MaS C04000A Series Types".
RCA Designation
C040l9A
MIL·M·38510 Designation
MIL-M-385l 0/05302
The packaged types can be supplied to six screening levels 11N, 11R, 11, 12, 13, 14 - which correspon-d to MIL-STO-883
Classes "A", "B", and "C"_ The chip versions of these types
can be supplied to three screening levels - 1M, IN. and IR.
For a description of these screening levels and for detailed
information on fest methods, procedures, and test sequence
employed with high-reliability COSIMOS devices refer to
High·Reliability Report RIC-l02C, "High-Reliability COSI
MaS CD4000A "Slash" (II Series Types"_
92SS·U!;
Fig, 1 - Schematic diagram for 1 of 4 identical stages.
9-74
494
File No. 743
CD4019A Slash (I) Series
STATIC ELECTRICAL CHARACTERISTICS IAII inputs
...........................
VSS S V, ::; Vool
IRecommended DC SupplV Voltage 1VOO - VSS) . . . . . . . . . . 31015VI
N
LIMITS
CHARACTERISTIC
0
TEST
CONDITIONS
SYMBOL
Vo
Voo
Volts Volt.
-55°C
Min.
MaK.
Current
Quiescent Device
Dissipation/Package
Low·Level
300
10
10-
0.05
10-
200-
25
0.15
10
100
0.5
3
0.55-
5
0.Q1
0
0.01
0.05
0.01
0
0.Q1
0.05
2.25-
2.3-
5
4.99
10
9.99
4.99
9.99
V OH
P·Channel
Noise Immunitv
(Any Inputs)
For Definition.
See Appendi)(
550·207
Output Orive Current'
N·Channel
P·Channel
Diode Test, 100 IJA
Test Pin
VTHN
'0=-20"A
-0.7-
VTHP
'0= 20"A
0.7-
V NL
V NH
ION
lOP
1500
2000
-3"
3"
-
4.95
5
10
14.45
-0.7-
-1.5
0.7-
1.5
-3" -0.33"
1.5-
2.25
1.4
4.5
2.9-
3.6
5
1.4
3"
1.5-
2.25
1.5
7.2
10
2.9-
3"
4.5
3"
0.5
5
0.6
0.7-
0.9
0.3
0.5
10
0.9
1.2-
1.5
0.55
4.5
5
9.5
10
-0.25- -0.5
-0.7-
0.95
V
V
V
rnA
rnA
0.5
1.5-
1.5-
V
10
Input Current
2
3"
-0.175
-1.5
1.5-
V OF
-3"
0.3-
1.5
-0.31
V
9.95
3"
2.9
V
0.55-
10
0.95 5
~W
4.95
14.45-
15
Threshold Voltage:
N·Channel
25
0.5-
3
~A
100
0.5-
15
High·Level
MIx.
5
f-;o.
VOL
T
E
S
125°C
Mo •• Min.
0.03
Po
Output Voltage
25°C
Typ.
Min.
5
QuieS(;ent Oevice
'L
UNITS
CD4019AD, CD4019AK
pA
Limits with black dot (_, designate 100% testing. Refer to RIC·1028 "High-Reliability COS/MaS C04000A Slash (/) Series Types", Tables 2
through 7 for testinR sequence. All other limits are deslgner's parameters under given test conditions and do not represent 100% testing.
Note 1: Complete f\Jnct,onaltest. all inputs and outputs to truth table
Note 3: Test on all ,nputs and outputs.
Note 2: Test is either a one input or one output onlv_
For Threshold Voltage Test Circuits. Operating and Biased Life Test Circuits. Output Drive Current Test Circuits.
and for Operating Considerations. see Appendix
,
MAXIMUM RATINGS,Absolute-Maximum Values:
Storage-Temperature Range .......... .
Operating-Temperature Range '.......... .
DC Supply-Voltage Range:
(VDD -VSS)·····················
Device Dissipation (Per Package) ........ .
All Inputs ..........................
Recommended
DC Supply-Voltage (VDD - VSS) .... ,
Recommended
Input-Voltage Swing ... '............ .
Lead Temperature (During Soldering)
At distance 1/16" ± 1/32"
(1.59 ± 0.i9 mm) from case
for 10 s max ...................... .
....
:::J:
-65 to +150 °c
-55 to +125 °C
-0.5 to +15 V
200
mW
VSS:';VIS.VDD
3to 15
300
AMBIENT TEMPERATURE ITA). 25 D C
TYPICAL TEMPERATURE COEFFICIENT FOR ALL
VALUES OF Voo • 0.3% 'DC
~
-'
J
:; 200
~
SUPPLY VOLTS
Voo - 5
10
V
15
VDD to VSS
10
20
30
40
50
60
70
LOAD CAPACITANCE (Cl'- pF
+265
°c
80
92CS'17B30
Fig.6- Typ. propagation delay time vs CL'
495
CD4019A Slash (I) Series-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 743
OYNAMIC ELECTRICAL CHARACTERISTICS at TA = 250 C. CL - 15 pF. and input rise and fa" times = 20 ns
Tvpical Temperature Coefficioni for an values of VOO = 0.3 %I"c (See Appendix for Waveformsl
LIMITS
CHARACTERISTICS
TEST
CONDITIONS
SYMBOLS
CD4019AD.CD4019AK.
VDD
(Voltsl
Propagation Delay Time:
Transition Time
Input Capacitance
Min.
Typ.
tpHL'
5
-
100
225
tPLH
10
-
50
100·
tTHL'
5
-
100
200
tTLH
10
-
40
65·
All A and B Inputs
-
5
12
-
KA and KB Inputs
C,
..
UNITS
NOTES
ns
1
ns
1
pF
-
Max.
-
..
Limits with black dot (-, deSignate 100% testing. Refer to AIC·1028 "Hlgh-Reliablllty COS/MOS CD4000A Slash (/) Series Types", Tables 2
through 7 for testing sequence. All other limits
designer's parameters under given test conditions and do not represent 100% testing.
NOTE 1: TeSt IS a one input one output only.
are
AMBIENT TEMPERAnm: (TAl. 25-C
f
300
VALUES OF
AMBIENT TEMPERATURE (TAJa25"C
LOAD CAPACITANCE (eL) " 15 pF
!!
TYACAl TEMPERATURE COEFFICIENT FOR ALL
I
Voo· 0.3% I-e
600
'3
~
S500
~ 400
5U'A.Y VOlTS lVool-'
1200
"
II tffttl mill 111I1 11111 III II 11111 11111 I!!!!!!
o
10
20
30
40
50
60
LOAD CAPACITANCE {CL)-pF
70
BO
92CS-I7831
•
rrrrm=111 I I I
o
S
~:
Cj.~9Aq.~1!4019~K
I'
~
h:::T.::;:E.::~......:.-::-:".L"_~_
SUPP~~ YOLlS IVD0115
92cs-22"n4
Fig. 4-Max. propagation delay time VI VOD.
Fig. 3-'Typ. transition time V$ eL'
10V
10" AMBIENT
.
TEMPERATURE (TAI-2S·C
V
10'
;0
~
!>
~,,,
103
~
z
0
i
,0
r3:'~
10'
,~O
Fig. 6- Quiescent device current teft circuit.
3.5V OR 7.0V
......
m
c
tr
5V OR IOV
10
'";0
..
0
,
'I
LOAD CAPACITANCE (CL)-I:IIpF
- - - - CL -:II0pF
ID~
10
102
INPUT FREQUENCY ('.) -
103
104
kHz
92CS-11832RI
92CS-17916
Fig. 5-Typ. dissipation charactsri8tic8 (per output).
Fig. 7- Noiie immunity test cin:uit.
File No. 750 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
OOCG3LJD
Solid State
Digital Integrated Circuits
Monolithic Silicon
High-Reliability Slash(l) Series
CD4020A/ ...
Division
High-Reliability COS/MOS
14-Stage Ripple-Carry
Binary Counter/Divider
DO
16
9
01
7
04
5
05
4 06
6 07
13 oe
12 09
10
INPUT
PULSES
14 QIO
15 011
I
012
2
013
3
014
II
RESET
...
"oo
...
...~
For Logic Systems Applications in Aerospace,
Military, and Criticallildustrial Equipment
0:
.
Special Features
::>
• Medium speed operation••••. 7 MHz (typ.) at VOO - Vss = 10 V
• Low "high"· and "low" ·Ievel output impedance.•.•.• 1000n (typ.) at
VOO-VSS=10V
~
• MSI complexity on a single chip•.•..• 14 fully static,
master.. lave stages
a
Vss
RCA C04020A "Slash" III Series are high·rellability COS/
MaS integrated circuits intended for a wide variety of logic
function configurations in aerospace, military, and critical in·
dustrial equipment. C04020A types consist of a pulse input
shaping circuit, reset line driver circuitry, and 14 ripple·carry
binary counter stages. Buffered outputs are externally avail·
able from stages 1, and 4 through 14. The counter is reset to
its "all zeroes" state by a high level on the reset inverter in·
put line. Ea~h counter stage is a static master·slave flip·flop.
The counter is advanced one count on the negative·going
transition of each input pulse. These devices are electrically
and mechanically identical with standard COS/MaS types
CD4020A described in data bulletin 479 and DATABOOK
SSD·203 Series, but are specially processed and tested to
• COS/MOS gate·input loading at both Reset and
Input·pulse lines
Applications
• Frequency.cJividing circuits
• Time·delay circuits
• Counter control
• Counting functions
RCA Designation
MIL·M·38510 Designation
CD4020A
MI L·M·3851 0/05603
meet the electrical, mechanical, and environmental test
methods and procedures established for microelectronic de·
vices in MIL·STD·883.
In addition to the RCA high·
reliability "Slash" (/1 Series, RCA will offer these circuits
screened to MIL·M·38510.
INPUT
PULSE
SHAPER
X>t---+
• R· HIGH DOMINATES (RESETS ALL STAGES)
• ACTION OCCURS ON NEGATIVE GOING TRANSITION OF INPUT
PULSE. COUNTER ADVANCES ONE BINARY COUNT ON EACH
NEGATIVE ~ TRANSITION (16.384 TOTAL BINARY COUNTS).
+
Fig. I-Logic diagram for 1 to 4 binary stages.
9·74
497
CD4020A Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 750
The packaged types can be supplied to six screening levels lIN, I1R, II, 12, 13, 14 - which correspono to MIL·STO·883
Classes "A", "B", and "C". The chip versions of these types
can be supplied to three screening levels - 1M, IN, and IR.
For a description of these screening levels and for detailed
information on test methods, procedures, and test sequence
employed with high·reliability COSIMOS devices refer to
High·Reliability Report RIC·l02C, "High·Reliability COSI
MaS CD4000A "Slash" II) Series Types".
The C04020A "Slash" (I) Series types are supplied in 16lead dual-in-line ceramic packages ("0" suffix), in 16-lead
ceramic flat packages ("K" suffix), or in chip form ("H"
suffix).
MAXIMUM RATINGS, Absolute-Maximum Values:
Storage-Temperature Range .... . . . . . .. -65 to +150 °c
Operating-Temperature Range .. ' ......... -55 to +125 0c
DC Supply-Voltage Range:
(VOO - VSS)····················· -0.5 to +15 V
Device Dissipation (Per Package) ........ .
200
mW
All Inputs ......................... . VSS:S,v1 ~yoo
Recommended
DC Supply·Voltage (VOO - VSS) .....
3 to 15
V
Recommended
Input·Voltage Swing. . . . . . . . . . . . . . .. VOO to VSS
Lead Temperature (During Soldering)
At distance 1/16" ± 1/32"
0.59 ± 0.79 mm) from case
for 10 s max ..................... .
+265
,----Q
TO NEXT STAGE
.----0
RESET TO
ALL STAGES
NOTE: SUBSTRATES FOR ALL "p" UNITS ARE CONNECTED TO Voo
SUBSTRATES FOR ALL" n" UNITS, UNLESS OTHERWISE SHOWN, ARE CONNECTED TO GROUND.
SUBSTRATES FOR THESE" not UNITS ARE CONNECTED TO RESET LINE
*
Fig. 2-SchemBtic diagram of pulse shapers and 1 of 14 binary stages.
498
°c
File No. 750 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4020A Slash (I) Series
STATIC ELECTRICAL CHARACTERISTICS (AI/Inputs • •• VSS
< V, < VOW
RBCOmmendtld DC Supply Voltllf/ll
3 to '5 V
LIMITS
CHARACTERISTIC
SYMBOL
CD4020AD. CD4020AK
_55°C
Vo Voo
Valts Volts
Current
Q.liescent Device
Olssipationi1'ackage
Output Voltage
Low-Level
Min.
-
6
Oulescent Device
IL
5
5
10
VOH
P-Channel
Noise Immunity
(Any Input)
For Definition~
See Appendix
SSO·207
Output Drive Current:
N·Charlnel
P-Chan"el
VTHN
10= -20 "A
VTHP
10 ' 20 l'A
V NL
ION
lOP
I
!
Diode TIS" 100 I'A
Test Pin
Input CUrrent
0.01
Min.
Max.
15
900
1
2se
-
2.5
75
-
-
0.5-
-
0
0.01
0
0.01
0.5-
2.3-
-
-
4.99
5
14.se
-
~.~
....J'I
~.~
O.~
~
0.71.5-
2.25
~
4.5
1.5-
2.25
~
4.5
-
0.15-
0.2
-
O~
0.4
10
9.99
~
5
1.4
10
2.ge
0.5
5
0.9
0.5
10
4.5
5
~.11
9.5
10
~.25
0.185
VOF
II
-
1.5-
-
-
250
10
-
4.99
10
9
MIX.
0.5
10
5
1.5
4.2
Typ.
9.99
2.25-
5
0.8
1
VNH
0.01
3
15
Inresnolo 0 tage:
N-Channel
0.55-
Min.
-
15
Hi!tl·Level
75
250
-
3
VOL
2se
-
10
Max.
~.~
-
-
-
-
500"
4500
5000
0.05
"W
-
V
1
V
1
V
2
-
-1.5
-~
~.~
-~
1.5
~
0.3-
~
1.4
-
-
1
0.55-
14.4se
10
"A
0.05
-
~.5
T
E
S
-
-
~.oge ~.25
UNITS
1~"C
25"C
15
-
10
Po
N
0
TEST
CONDITIONS
-
-
1.5-
-
4.95
9.95
2.ge
1.5
~
0.05
0.105
~.065
~.14
-
V
1
V
mA
2
-
mA
2
1.5-
V
3
-
pA
-
Limits with black dot ,.) designate 100% testing. Refer to RIC-102B "High-Reliability COS/MOS C04000A Slash II) Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1: Complete functional test, all inputs and outputs to truth tabfe.
Note 2: Test is either a one input or a one output onlV.
Note 3: Test on all inputs and outputs.
499
CD4020A Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
File No. 750
DYNAMIC ELECTRICAL CHARACTERISTICS at TA - 250 C. CL - 15 pF. and input rise and fall times - 20 n. except treL, rtcL
Typical Temperatura Coafficient for all values of V OD = 0.3%/C. (Sse Appendix for Wa""forms)
lIMITS
CHARACTERISTICS
TEST
CONOITIONS
VDD
(Volts)
SYMBOLS
CD402OAD.
CD4020AK
Min.
Tv ...
Max.
UNITS
N
0
T
E
S
ns
1
ns
1
ns
-
jls
1
CLOCKED OPERATION
5
-
450
600
10
-
150
225.
tTHl'
5
-
450
600
t"flH
10
200
300.
•
tpHl'
Propagation Delay Time
tplH
Transition Time
Minimum Clock
Pulse Width
Clock
Rise & Fall Time
tWl'
5
-
200
335
twH
10
-
70
125
trCl'
5
-
-
15
!tCl
10
-
-
15·
5
1.5
Maximum Clock
Frequancy
fCl
Input Capacitance
CI
10
7
-
MHz
1
5
-
pF
-
2000
500 .
3000
ns
-
1800
2500
:!~
475
ns
-
2.5
4.
-
Any
Input
RESET OPERATION
5
Propagation Da!ay Time:
tpHl(R)
Minimum Reset
P:.:!:::W::'!th
10
5
tWH(R)
I
on
v
-
775
Limits with black dot I_I designate 100% testing. Refer to RIC·t028 "High-Reliability COS/MOS CD4000A Slash It) Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1: Test Is a one Input one output only .
• Propagation Delay Is from clock Input to
Q,
output.
DRAIN-TO- SOURCE VOLTS (VOS)
-15
-w
-5
0
·5
GATE - TO - SOURCE VOLTS (VGSI " 15
-I
AMBIENT TEMPERATURE (TAl" 25°C
TYPICAL TEMPERATURE COEFFICIEN
FOR 10 =- 0.3% 1°C
~
-10
.'"
~
10
-z
GAT - TO - SOURCE VOLTS IVGs ) • -15
~
H
"-3
AMBIENT TEMPERATURE (TA)· 25°C
TYPICAL TEMPERATURE COEFFICIENT FOR 10" - 0.3% loe
10
15
ORAIN-TO-SOURCE VOLTS Nos)
92CS- 22155
92CS-22756
Fig. 3-Min. n-channtJl drain characteristics.
500
Fig. 4-Min. p-channel drain characteristics.
File No. 750 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4020A Slash (I) Series
AMBIENT TEMPERATURE (TA). 25·C
AMBIENT TEMPERATURE (TA). 2~·C
TYPICAL TEMPERATURE COEFFICIENT
FOR ALL VALUES OF VOO· 0.3% lac
TYPICAL TEMPERATURE COEFFICIENT FOR
i
ALL VALUES Of Voo '" 0.3% '·C
}
~'OOO
~
.""'
;
600
z
400
0
...
800
i
~
..!:1'"
~
~
'OOO
ill;:
200
10
,5
to
,5
IE
,0
500
20
30
40
~o
60
LOAD CAPACITANCE (CL'-pF
70
80
o
90
i2CS-1781!5
10
20
30
40
50
60
LOAD CAPACITANCE (CLI-pF
10
80
90
92CS-17816
Fig. 5-Typ. propagation delay time vs. CL ,
Fig. 6- Typ. transition time
VI.
CL,
AMBIENT TEMPERATURE (TA )· 25·C
LOAD CAPACITANCE (C L )· 15 pF
15
,.,"
~
~1...>,Itltl~\O~
>,Iov
~'V~/
"I~
~.
LL
'"~
10
15
10
20
LOAD CAPACITANCE (CLl=ISpF
- - - CL =50pF
104
SUPPLY VOLTS (Voo)
92C5-19865
105
106
INPUT FREQUENCY U.;l-Hz
'92CS-17S17
101
Fig. 8- Typ. dissipation characteristics.
Fig. 7- Typ. clock frequency vs. VDU
5V OR IOV
5V OR 10V
10V
PRESET Q,
TO "I"
TEST PERFORMED
IN ALL "aS" STATE
92C5-17917
Fig. 9-Oui6scent device dissipation test
92CS'1791S
Fig. 70-Noise immunity test circuit.
92CS-17919
Fig. 11- Reset noise immunity test circuit.
circuit.
501
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 730
OOCIDLJD
Solid State
Digital Integrated Circuits
Monolithic Silicon
High-Reliability Slash(/) Series
.
CD4021A/...
Division
High-Reliability
COS/MOS 8-Stage
Static Shift Register
~~::-i
CONT.
SER. II
IN.
CLOCK!Q.
o.
12
Q,
, o.
•
Vss
Asynchronous Parallel Input/Serial Output,
Synchronous Serial Input/Serial Output
For Logic Systems Applications in Aerospace,
Military, and Critical Industrial Equipment
Special Features:
- Asynchronous parallel or synchronous serial operation under control of
parallellserial control-input
- Individual "jam" inputs to each register stage
- Master-slave flip-flop regilter stages
- Fully static operation.•.••• DC to 5 MHz
RCA C04021A "Slash" (I) Series are high-reliability COSI
MOS integrated circuits intended for a wide variety of logic
function configurations in aerospace, military, and critical
industrial equipment. C04021 A types are 8-stage parallel or
serial·input/serial·output shift registers having common Clock
and ParaliellSerial Control inputs, a single Serial Data input,
and individual parallel "Jam" inputs to each register stage.
Each register stage is aD-type, master·slave flip·flop. "Q"
outputs are available from the sixth, seventh, and eighth
stages.
When the parallellSerial Control input is "low", data is
-serially shifted into the 8·stage register synchronously with
the positive·going transition of the Clock pulse. When the
ParallellSerial Control input is "high", data is Jammed into
the 8-stage register via the parallel input lines asychronously
with the clock line. Register expansion is possible using
additional C04021A packages.
These devices are electrically and mechanically identical with
standard COS/MOS C04021A types described in data
bulletin 479 and OATABOOK SSD-203 Series, but are
specially processed and tested to meet the electrical,
mechanical, and environmental test methods and procedures
established for microelectronic devices in MIL-STD·883. In
addition to the RCA high-reliability "Slash" (I) Series, RCA
will offer these circuits screenijd to MIL-M-3B510 as shown
in RIC-l04, "MIL-M·38510' COS/MOS C04000A Series
types."
Applications:
- Asynchronous parallel input/serial output data queueing
- Parallel to serial data conversion
- General purpose register
Classes "A". "B". and "C". The chip versions of these types
can be supplied to three screening levels - 1M, IN, and IR.
For a description of these screening levels and for detailed
information on test methods, procedures, and test sequence
employed With hign-reiiabiiiry COS/iviOS ur:v;r;t::, ,'i3fi3'- tv
High-Reliability Report RIC-I02C, "High-Reliability COSI
MOS CD4000A "Slash" (I) Series Types".
The C04021A "Slash" II) Series types are supplied in
IS-lead dual-in-line ceramic packages ("0" suffix), in IS-lead
ceramic flat packages ("K" suffix), or in chip form ("H"
suffix).
MAXIMUM RATINGS,AbsoluteMaximum Values:
Storage·Temperature Range .......... .
Operating·Temperature Range', ......... .
DC Supply·Voltage Range:
(VDO -VSS)·····················
Device Dissipation (Per Package) ........ .
All Inputs
Recommendoid ...................... .
-65 to +150
-55 to +125
°c
°c
-0.5 to +15 V
200 mW
VSS::;VI::;VOD
DC Supply-Voltage (VOO - VSS) .... .
3to 15
V
Recommended
MIL·M-3B510 Designation
Input-Voltage Swing ............... . VOO to VSS
MI L-M·3851 0/05704
Lead Temperature (During Soldering)
At distance l/lS"± 1/32"
The packaged types can be supplied to six screening levels (1.59 ± 0.79 mm) from case
/1N,/IR,/I,/2,/3,/4 - which correspond to MIL-STO-883
for 105 max ..................... .
+265 °c
RCA Designation
C04021 A
9-74
502
File No. 730 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4021A Slash (I) Series
PARALLEL
INPUT-I
7
PARALLEL I
SERIAL
PI-7
PI-6
CONTROL
'0---
I
I
I
,
PI
---0
4- STAGES
SAME AS STAGE I
.
I
CL
CL
CL
I
_I
L
CLOCK
TRUTH TABLE
10
Str,al
Von = TERMINAL 16
''''''''
Vss = TERMINAL 8
PiI.alleil
Sen,,!
Control
0,
(lnlernall
On
06
07
OB
92CM -17141RI
LL..!:=:.L-"--'_"::"'-'."'::'.L-,_O::'_..L:0:::.JR NO CHANGE
.lit. ,
LEVEL CHANGE
X ' DON°r CARE CASE
Fig. 1-Logic diagram and truth rable.
P.I
PIs
Q ,
I
~;f7
ONL~·y
o
CL
92CM-17139RI
Fig. 2-One typical stage and its equivalent detai/~d circuit.
503
CD4021A Slash (/) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 730
1-- -- --t
YDD
!
i:J
I
~I
I
PARALLEL/SERIAL
CONTROL
~
ffl PIS
~YIS
PARALLEL
ALL "P" - UNIT SUBSTRATES ARE CONNECTED TO VDD
tJ .
:=t-
ALL .,." - UNIT SUBSTRATES ARE CONNECTED TO Vss
d
PIS
YDD
__ ~VIS
I
'""1::;
-.--ARi'T'REGisTERSrAGE'iONeOFiiGitTSTAGEsI-- - - - -
Voo
I
I
--'--
PIS.
~i
TO STAGE 2
TI
I
I
P/~
I
I
'P
3
"tI:·~
I.!.
!.
I
I
I
YD~ b
ier
~hF1 J
~lSl I
rr---=f-'---~
CLOCK
n-----+---~
~
I
1.Iq: n~!;.L
,!YDD
~ IU"""""
L ~
10
!:1
YIS
__
~
II
LJl~ I
T~
III
QlJ9~~)
J.r'j
II
T d
II
I
~ ---.J L~'~ __ J
ED
l(Os)
BUFFERED OUTPUT
Yss
_ _ _ C_L_ _
92CM-172!8RI
Fig. 3-Schematic diagram-CD4021A.
AMBIENT TEMPERATURE 'TA ) • ze,·C
LOAD CAPACITANCE (el) • 115 pF
AMBIENT TEMPERATURE (T A) ·25
·c
TYPICAL TEMPERATURE COEFFICIENT FOR
ALL VALUES Of Yo o • 0.3 %/-C
6
g~ 30
is
~
200
~
100
10
15
if
o
'0
SUPPLY VOLTS(YoO)
15
20
92C5-19867
Fig. 4- Typ. clock frequency vs. V DD.
504
'0
20
30
40
50
60
10
80
lOAD CAPACITANCE (CLI-pF
92C5-11807
Fig. 5- Typ. propagation delay time vs. CL.
File No. 730 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4021A Slash (/) Series
STATIC ELECTRICAL CHARACTERISTICS (All inputs .....••••••••.••.•.•••••.•••..•• VSS'" VI'" VOO)
(Recommended OC Supply Voltage (VOO -VSS) . • • . • • •• 3 to 15 V)
LIMITS
CHARACTERISTIC
Quiescent Device
Current
SYMBOL
TEST
CONDITIONS
Vo
VDD
Volts Volts Min.
_55°C
Typ. Max. Min.
25°C
Typ. Max. Min.
IL
5
10
-
-
5
10.
-
0.5
1
5
10.
Quiescent Oeivce
PD
Dissipation/Package
5
10
-
-
25
100
-
2.5
10
25
100
-
-
0.55.
0.01
0.D1
-
0
0
-
-
-
0.5.
0.01
0.01
0.5.
Output Voltage:
Low·Level
3
5
10
15
3
5
10
15
VOL
High-Level
VOH
Threshold Voltage:
N-Channel
P-Channel
VTHN
Noise Immunity
(Allinputsl
VNL
For Definition,
See Appendix in
VTHP
ID
10
=·20/JA
= 20j./A
VNH
UNITS NOTES
C04021 AD. CD4021AK
-
-
-
-
125°C
Typ. Max.
-
-
300
200
/JA
-
1500
2000
IN"
-
-
-
-
V
1
-
V
1
-3.
3.
V
V
2
-
-
2.3.
4.99
5
9.99 10
14.5. -
-0.7.
0.7.
·1.7
1.7
-3.
3.
-0.7. -1.5
0.7. 1.5
-
-
-
-
1.5.
3.
1.5.
3.
2.25
4.5
2.25
4.5
-
1.4
2.9.
1.5
3.
-
-
0.15.
0.25.
-0.08.
-0.20.
0.3
0.5
-0.16
-0.44
-
0.085 0.175 -0.055 -0.14 -
-
2.25.
4.99
9.99
-
0.8
1.0
4.2
9.0
5
10
5
10
1.5
3.
1.4
2.9.
0.5
0.5
4.5
9.5
5
10
5
10
0.15
0.31
-0.1
-0.25'
-
-
-
-3.
3.
-
4.95
9.95
-
-
0.05
0.05
0.55.
-
1
-
14A5
-0.3. -1.3
0.3. 1.3
-
V
1
V
SS0-207
Output Drive Current:
ION
N·Channel
P-Channel
lOP
Diode Test 100 j./A
Test Pin
Input Current
~OF
II
-
mA
-
-
-
-
1.5.
-
-
1.5.
'-
-
1.5.
V
-
-
-
-
10
-
-
-
-
pA
2
mA
3
-
Limits with black dot (e) designate 100% testing. Refer to RIC·l02B "High-Reliability COS/MOS CD4000A Slash (f) Series Types". Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1: Complete functional test, all inputs and outputs to truth table.
Note 3: Test on all inputs and outputs.
Note 2: Test is either a one input or one output onlv.
For·Threshold Voltage Test Circuits, Operating and Biased Life Test Circuits, Output Drive Current Test Circuits,
and for Operating Considerations, see Appendix.
f
AMBIENT TEMPERATURE (TA ) .25·C
600
!~rle:tuTE~M6;RvADTDU~~.~~~F:~gIENT
FOR
"....
~500
....
"
,t400
!i.j
I-
300
z
o
><1'1
200
I-
100
z
~
10
20
30
40
50
60
LOAD CAPACITANCE CeL) -
70
pF
80
10
102
103
INPUT CLOCK FREQUENCY (fCL1- kHz
Fig. 6- Typ. transition time vs. CL'
104
92CS-11BOSR:5
92CS-1780B
Fig. 7- Typ. dissipation characteristic:..
505
CD4021 A Slash (/) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _""--_ File No. 730
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C, CL = 15 pF and input rise and fall times = 20 ns
except trCL, tfCL Typical Temperature Coefficient for all values of VDD =0.3%/oC (See Appendix for Waveforms
LIMITS
CHARACTERISTICS
TEST CONDITIONS
YDD
(Voltsl
SYMBOL
Typ-
Max.
300
100
750
225.
ns
-
150
75
300
125.
ns
200
100
500
175
-
200
100
500
175
5
10
-
-
IJs
1
5
10
-
100
50
350
80
ns
-
2.5
-
MHz
1
5
5
-
pF
-
Propagation Delay Time*·
5
1'0
Transition Time
tTHl.
tTlH
5
10
Minimum Clock Pulse
Width
tWl =
tWH
5
10
Minimum High·level
Parallel/Serial Control
Pulse Width
tWH(P/SI
Clock Rise &
Fall Time
*trCl =
tlCl
Maximum Clock
Frequencv
ICl
Input Capacitance
CI
NOTES
-
tpHL.
tPlH
5
10
Set-UpTime
UNITS
CD4021AD. CD4021AK
5
10
Min.
-
-
-
1
3.
-
-
Any Input
1
-
-
ns
-
15
15.
Limits with black dot f.) designate 100% testing. Refer to RIC·l028 "High·Reliability COS/MOS CD4000A Slash (f) Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
* If more than one unit is cascaded in a parallel clocked operation
--From Clock or Parallel/Serial Control Input
trCL should be made less than or equai to tne sum aT tne fixed
NOTE 1: Test is a one Input one output only
propagation delay time at 15pF and the transition time of the
output driving stage for the estimated capacitive load,
10V
~-----------
1.5V OR 3V
12
"
10
9
NOTE:
PRESET VOl TO 1 BY
MEANS OF CLOCK
PULSE
92.CS-17B98RI
Fig. 12- Reset noise immunity t8,t circuit.
File No. 733 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Digitial Integrated Circuits
D\l(]5Ll[]
Monolithic Silicon
Solid State
Division
High-Reliability 'Slash' (I) Series
CD4026A/... CD4033A/...
High-Reliability
COS/MOS Decade Counters/Dividers
CLCCM
nIA'U
With Decoded 7·Segment Display Outputs and:
'00
Display Enable - CD4026A
Ripple Blanking - CD4033A
Special Features:
DISPLAY
(NAaU
'"
CD4026A
•
•
•
•
•
•
Counter and 7-segment decoding in one package
Ideal for low-power displays
Easily interfaced with 7·sogment display types
Fully static counter operation: DC to 2.5 MHz Ityp.)
Display Enable Output ICD4026A)
"Ripple Blanking" and Lamp Test ICD4033A)
RCA CD4026A and CD4033A "Slash" II) Series are
high·reliability COSIMOS integrated circuits intended for a
wide variety of logic function configurations in aerospace,
military. and critical industrial equipment. The CD4026A
and CD4033A each consists of a 5·stage Johnson decade
counter and an output decoder which converts the Johnson
code to a 7·segment decoded output for driving each stage in
a numerical display.
These devices are particularly advantageous in display
applications where low power dissipation and/or low package
counter are important.
Inputs common to both types are Clock. Reset, and Clock
Enable; common outputs are carry out and seven decoded
outputs la, b, c, d, e, f, g). Additional inputs and outputs for
the CD4026A include Display Enable input and Display
Enable and Ungated "C·segment" outputs. Signals peculiar to
the CD4033A are Ripple·Blanking and Lamp Test inputs and
a Ripple·Blanking output.
A "high" Reset signal clears the decade counter to its zero
count. The counter is advanced one count at the positive
clock signal transition if the Clock Enable signal is "low".
Counter advancement via the clock line is inhibited when the
Clock Enable signal is "high". Antilock gating is provided on
the Johnson counter. thus assuring proper counting se~
quence. The Carry·Out ICou,t) Signal completes one cycle
every ten clock input cycles and is used to directly clock the
succeeding decade in a multidecade counting chain.
The seven decoded outputs la, b, c, d, e, f, g) illuminate the
proper segments in a seven segment display device used for
9·74
1
17 b ~
CLOCI\'
[NAIILE
13 c
6
OJ It
~
II
~
...
,
LAMP
l[ST
•
CARRY
$OUT
RIPPLE
RIPPLE
~~II
'"
'"
'"'
CD4033A
Applications:
•
•
•
•
Decade counting!7-segment decimal display
Frequency division!7-segment decimal displays
Clock/watches/timers le.g. -;. 60, -;. 60,
-;. 12 counter/display)
Counter/display driver for meter applications
representing the decimal number 0 to 9. The 7·segment
outputs go "high" on selection in the CD4033A; in the
CD4026A these outputs go "high" only when the Display
Enable I N is "high".
CD4026A
When the Display Enable IN is "low" the seven decoded
outputs are forced "low" regardless of the state of the
counter. Activation of the display only when required results
in significant power savings. This system also facil itates
implementation of display·character mUltiplexing.
The Carry Out and ungated "C·segment" signals are not
gated by the Display Enable and therefore are available
continuously. This feature is a requirement in implementa~
tion of cettain divider· functions such as divide·by·60 and
divide·bY·12.
CD4033A
The CD4033A has provisions for automatic blanking of the
non~significant zeros in a multi-digit decimal number which
results in an easily readable display, consistent with normal
writing practice. For example, the number 0050.07000 in an
eight digit display would be displayed as 50.07. Zero
517
CD4026A, CD4033A Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 733
suppression on the integer side is obtained by connecting the
RBl terminal of the C04033A associated with the most
significant digit in the display to a "'Iow·level"' voltage and
connecting the RBO terminal of that stage to the RBl ofthe
C04033A in the next·lower significant position in the
display. This procedure is continued for each succeeding
C04033A on the integer side of the display.
On the fraction side of the display the RB 1 of the C04033A
associated with the least significant bit is connected to a
"'low level"' voltage and the RBO of the C04033A is
connected to the RB 1 terminal of the C04033A in the next
more-significant·bit position. Again. this procedure is can·
tinued for all C04033A's on the fraction side of the display.
The C04033A has a "'Lamp Test" input which. when
connected to a "'high level'" voltage. overrides normal
decoder operation and enables a check to be made on
possible display malfunctions by putting the seven outputs in
the "'high"' state.
These devices are electrically and mechanically identical with
standard COSIMOS C04026A and C04033A types described
in data bulletin 503 and OATABOOK 550·203 Series. but
are specially processed and tested to meet the electrical.
mechanical. and environmental test methods and procedures
established for microelectronic devices in MI L-5TO·883.
The packaged types can be supplied to six screening levels -
11 N. 11 R, 11, 12, 13, 14 - which correspond to MI L·STD·883
In a purely fractional number the zero immediately
preceding the decimal point can be displayed by connecting
the RBl of that stage to a "'high level" voltage (instead of the
RBO of the next more·significant·stage). For Example:
optional zero. 0.7346.
Likewise. the zero in a number such as 763.0 can be
displayed by connecting the RBl of the C04033A associated
with it to a "'high level"' voltage.
Ripple blanking of non·significant zeroes provides an
appreciable savings in display power.
Classes "A", "B", and "'C", The chip versions of these types
can be supplied to three screening levels -/M,/N, and IR,
For a description of these screening levels and for detailed
information on rest methods, procedures, and test sequence
employed with high·reliability COS/MaS devices refer to
High·Reliability Report RIC·t02C, "High·Reliability COS/
MaS CD4000A "Slash" (I) Series Types':
.,'
The C04026A and C04033A "Slash" (/) Series types are
supplied in 16-lead dual·in·line ceramic packages ("0"
suffix). in 16·lead ceramic flat packages ("K" suffix), or in
chip form ("H" suffix).
~CoUT
1-_ _ _
~~CLOC.+IQ)
v
v
UNGATEO"C"
SEGMENT
CLOCK
CLOCK ENABLE
~
CL
2
DISPLAV
ENABLE
IN
3
DISPLAY
ENABLE
0---------------------i
OUT
16
YDD
0
GND
0
,
92CM-190a1Rl
SEGMENT
DESIGNATIONS
Fig. I-CD4026A logic diagram.
518
File No. 733 _ _ _ _ _ _ _ _ _ _ _ _ _ _---.,-_ _ _ _ CD4026A, CD4033A Slash
(II Series
SEGIIEHT
DESIGNATIONS
SCOUT
jCLOCK
CLOCK
CLOCK ENABLE
~
,
+ 101
CL
RESET
.B'O--------------------given test conditions and do not rt:present 100% testing.
Note 1: Complete functional test, all inputs and outputs to truth table.
Note 2= Test is either a one input or a one output on Iv .
530
Note 3: Test on all inputs and outputs.
1
3
File No. 735 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4028A Slash (I) Series
DYNAMIC ELECTRICAL CHARACTERISTICS atTA = 25°C. Vss= OV. CI = 15pF. and all input rise and fail times = 20 ns
Typical Temperature Coefficient for all values of VDD = 0.3%I"C (See Appendix for Waveformsl
LIMITS
CHARACTERISTICS
SYMBOL
CD402BAD. CD402BAK
TEST CONDITIONS
VDD
(Volts)
NOTES
UNITS
Typ.
Max.
Propagation Delay Time
tpHL.
tpLH
5
10
-
250
100
4BO
lBO.
ns
1
Transition Time
tTHL.
tTLH
5
10
-
60
30
150
75.
ns
1
Input Capacitance
CI
-
5
-
pF
-
Min.
Any Input
'Limits with black dot te) designate 100% testing. Refer to RIC-102B "High-Reliability COS/MOS CD4000A Slash II) Series Types", Tables 2
,through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
NOTE 1: Test is a one-input, one output only.
DRAIN-TO-SouRCE VOLTS 1VOS)
-20
-15
-10
o
-5
AMBIENT TEMPERATURE ITAI-Z5-C
TYPICAL TEMPERATURE COEFFICIENT
FOR ALL VALUES OF ID- -0.3 ,,-lac
GATE-lO-SOURCE VOLTS IVGs)-15
o
o
-10 ....
10
::J
~ 20
"c
:l
z"
:..
10
10
GATE-TO-SOURCE VOLTS (VGSI-15
-'0
o
o
,
10
20
"
92C5-.19099
DRAIN-lO-SOURCE VOLTS (Voo)
92CS-19098
Fig. 2- Typ. N-channel drain characteristics.
Fig. 3- Typ. P-channel drain characteristics•.
AMBIENT TEMPERATURE (TA) - 25·C
TYPICAL TEMPERATURE COEFFICIENT
FOR ALL VALUES OF Voo·0.3 %'·C
AMBIENT TEMPERATURE ITA'-25-C
TYPICAL TEMPERATURE COEFFICIENT
• 300 FOR ALL VALUES Of VDD-0.3 %'-C
I
,.
~ 300
:!!
z
0200
10
J
O
:::
"
100
o
o
w
o
~
~
00
~
~
~
~
LOAD CAPACITANCE ICL)- pF
o
w
~
~
00
~
~
~
~
LOAD CAPACITANCEICL)"-pF
92CS-19100
. Fig.4- Typ. prof!8gation delay time vs. CL.
92CS-19101
Fig. 5- Typ. transition time
V.f.
CL.
531
CD4028A Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 735
AMBIENT TEMPERATURE CTA)-25-C
LOAD CAPACITANCE(CL)-15pF
.0'
10
SUPPLY VOLTS(YDDI
Fig. 6-Max. propagation delav time
VI.
IO~
V Df).
104
FREQUENCY t 1 ) - HI
zo
.,
Fig. 7-Dlssipar/on vs.lnpur frequency.
5VOR IOV
,.
16
I.
•
5
13
I.
3.5VOR7V
10
9
l
_
PERFORM TEST
UNDER EACH
-
INPUT CONDITION
1.5 V OR 3 V
92CS-19103
Fig. 8-Quiescent del/ice
current test circuit.
532
o-Q
Fig.S - Noise-immunity test circuit.
File No. 736 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...,.
OOCIBLJO
Digital Integrated Circuits
Monolithic Silicon
Solid State
Division
High-Reliability Slash(l) Series
CD4029A/ ...
High-Reliability COSIMOS
Presettable Up/Down Counter
PRESET
ENABLE
CARRY IN
~~~5~EI
5
rL-.L>c.z..;....,
BINARYI
UP/DOWN
10
CLOCK
15
Binary or BCD-Decade
For Logic Systems Applications in Aerospace,
Military, and Critical Industrial Equipment
DECADE
Special Features:
•
•
vss
92CS-17190RZ
•
•
Medium speed operation •••• 5 MHz hyp.) @ CL = 15 pF and VOO-VSS = 10 V
Multi-package parallel clocking for synchronous high speed output response of ripple
clocking for slow dock input rise and fall times
··Preset Enablo" and individual U Jam" inputs provided
Binary or decade uP/down counting
• BCD outputs in decade mode
Applications:
•
•
Programmable binary and decade countinolfrequency synthesizers-BCD output
Analog to digital and digital to analog conversion
• Up/Down binary counting
• Up/Down decade counting
RCA CD4029A "Slash" (I) Series are high-reliability COS/
• Magnitude and sign generation
• Difference counting
MOS integrated circuits intended for a wide variety of logic
function configurations in "aerospace, military, and critical
industrial equipment. The CD4029A types consist of a
four-stage binary or BCD decade up/down counter with
provisions for "Iook~ahead" carry in both counting modes.
The inputs consist of a single Clock, Carry-in (Clock Enable),
Binary/Decade, Up/Down. Preset Enable, and four individual
Jam signals. Four separate buffered a signals and a Carry·Out
signal are provided as outputs.
A "high" Preset Enable signal allows information on the Jam
inputs to preset the counter to any state asynchronously
with the clock. A "low" on each Jam line, when the Preset·
Enable signal is "high", resets the counter to its zero
count. The counter is advanced one count at the positive
transition of the clock when the Carry·ln and Preset·Enable
signals are "low". Advancement is inhibited when the
Carry· In or Preset-Enable signals are "high". The Carry-Out
signal is normally "high" and goes "low" when the counter
reaches its maximum count in the IIUp" mode or the
minimum count in the "Down" mode provided the Carry·1 n
signal is "low". The Carry-In signal in the "low" state can
thus be considered a Clock Enable. The Carry-In terminal
.
must be connected to VSS when not in use.
Binary counting is accomplished when the Binary/Decade
input is "high"; the counter counts in the Decade mode
when the Binary/Decade input is "low", The counter counts
"Up" when the Up/Down input is "high", and "Down"
when the Up/Down input is "low". Multiple packages can be
connected in either a parallel-clocking or a ripple-clocking
arrangement as shown in Fig. 10. Parallel clocking provides
synchronous control and hence faster response from all
counting outputs. Ripple-clocking allows for longer clock
input rise and fall times.
These devices are electrically and mechanically identical with
standard COS/MOS CD4029A types described in data
bulletin 503 and DATA BOOK 550-203 Series. but are
specially processed and tested to meet the electrical,
9-74
The packaged types can be supplied to six screening levels /IN. I1R. 11,/2./3./4 - which correspond to MIL-STD-8B3
Classes "'A"'. "B"'. and "C... The chip versions of these types
can be supplied to three screening levels - 1M. IN. and /R.
For a description of these screening levels and for detailed
information on test methods, procedures, and test sequence
employed with high-reliability COSIMOS devices refer to
High-Reliability Report RIC-l02C, "'High-Reliability COSI
MOS CD4000A "Slash" II) Series Types".
The CD4029A "Slash" (I) Series types are supplied in
16-lead dual-in·line ceramic packages ("0" suffix). in 16-lead
ceramic flat packages ("K" suffix), or in chip form ("H"
suffix).
MAXIMUM RATINGS, Absolute-Maximum Values:
Storage-Temperature Range .......... .
Operating·Temperature Range .......... .
DC Supply-Voltage Range:
(VDD - VSS) .................... .
Device Dissipation (Per Package) ........ .
All Inputs
Recommended
DC Supply-Voltage (VDD - VSS) .....
Recommended
Input·Voltage Swing ................
Lead Temperature (During Soldering)
At distance 1/16·· ± 1/32··
(1.59 ± 0.79 mm) from case
for 105 max ..................... .
-65 to +150 °c
-55 to +125 °C
-0.5 to +15 V
200 mW
VSS:S VI:S VDD
3 to 15
V
VDD to VSS
+265
°c
533
CD4029A Slash (/) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 736
4
BINARYI
DECADE
9
ti
*
_
•
d,
Ed
TE
Q,
CL
Q,
NC-NO CHANGE
CLOCK TE PE J
x
x
,,
"L
x
x
"L
0
r
x
0
,
0
,
0
0
0
, ,
X
X
X
ti
**
TRUTH TABLE FOR F-F No.1
0
0
0
a
,
0
·0
Q NC
Q NC
TE-TOGGLE ENABLE
TRUTH TAiLE FOR F-F'S 2,3,4
x
x
,
CONTROl
Q
0
BIN/DEC.
19/0)
0
DECADE COUNT
0
0
,x
0
Q NC
Q NC
UP/DOWN
(U/D)
0
UP COUNT
DOWN COUNT
0
0
0
"L
,x
, ,
x
,,
r
x
Q
6
a
0
CLOC' TE PE J
Ed
_ TE
CL
d4
"L
x
0
X
0
LOGIC
LEVEL
INPUT
PRESET ENABLE
(PEl
0
JAM IN
NO JAM
,
NO COUNTER
ADVANCE AT POS.
CLOCK TRANSITION
0
ADVANCE COUNTER
AT POS. CLOCK
TRANSITION
X-DON'T CARE
CARRY IN (C:I)
(CLOCK ENABLE)
92CL-17191AI
ACTION
,
,
,
BINARY COUNT
Fig. I-Logic diagram.
t4=tfffE=b.1r!rlfW;Rr:r
I
!I
L
COUNT
9
10! II
:I
I
!
12
Fig. 2- Timing diagram-binary mode.
534
Lr
I
5
14
I
'3
2
I
I
I! O! 0
I
I
!
15
File No. 736
CD4029A Slash (/) Series
~~~~~-+-+-7-7-7-7~~~~~~~+-+'~:~ftt1
I
I
Fig. 3- Timing diagram-decade mode.
,
LOAD CAPACITANCE (CLl- pF
LOAD CAPACITANCE ICL1-pF
92CS·19105
Fig. 4- Typ. propagation delay time vs. CL for Q outputs.
92CS-19106
Fig. 5- Typ. propagation delay time vs. CL for carry output,
,
,20
LOAD CAPACITANCE {CLJ;- pF
LOAD CAPACITANCE ICLI-pF
92CS-19107
Fig. 6- Typ. transition time vs. CL for Q outputs.
92CS-1910e
Fig. 7- Typ. transition time vs. CL for carry output.
535
CD4029A Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
File No. 736
STATIC ELECTRICAL CHARACTERISTICS (All inputs .•....••.•..•......•..•....•.•..... vss" VI" Vool
(Recommended OC SUpply Voltage (VOO - VSSI .••........ 3 to 15 VI
LIMITS
CHARACTERISTIC
Quiescent Device
Current
Quiescent Device
Dissipation/Package
Output Voltage:
Low·Level
High·Level
SYMBOL
TEST
UNITS NOTES
CD4029AD, CD4029AK
CONDITIONS
-55'C
125 C
2!j°c
Vo
VOO
Max.
Volt. Volt. Min.
Max. Min. Typ. Max. Min.
IL
5
10
-
-
5
10.
Po
5
10
-
25
100
VOL
3
5
10
15
3
5
10.
15
VOH
-
2.25.
4.99
9.99
-
-
-
-
2.3.
4.99
5
9.99 10
14.5. -
-
:3.
3.
0.55.
0.Q1
0.Q1
0,5
1
5
10.
2.5
10
25
100
-
0.5.
0.01
0.01
0.5.
0
0
-
-
-
-
300
IJA
200
1
1500
p.W
2000
0.05
V
0.05
0.55.
,
1
-
-
V
-
4.95
9.95
14.45
·0.7. -1.5
0.7. 1.5
-3.
3.
-0.3.
0.3.
·3.
V
3.
V
-
1
Threshold Voltage:
N-Channel
VTHN
P·Channel
VTHP
Noise Immunity
(All Inputs)
1.5
3.
1.4
. 2.9.
-
1.5.
3.
1.5.
3.
2.25
4.5
2.25
4.5
-
4.2
9.0
5
10
5
10
-
1.4
2.9.
1.5
3•
0.5
0.5
5
10
0.5
0.74
-
0.4.
0.6.
0.15
0.3
-
0.28
0.42
-
Carry 0.5
Out· 0.5
puts
b
U.l
-
-
0.4
0.08. 0.5
0.32. 1
V.UU
10
-
0.22
-
5
10
·0.18
·0.3
·0.17 • ·0.07!
·0.2. -0.15
-
-0.08
-0.14
-
5
10
-0.09 I ·0.15
-
·0.06 ·0.4
-0.1. -0.8
-
-0.04
·0.01
-
-
0.8
VNL
1.1'
For Definition,
See Appendix
VNH
Output Drive
Current
Q
OutION
N'Channel
puts
Q
P-Channel
Diode Test 100 p.A
Test Pin
Input Current
lOP
·0.7.
0.7.
10" ·20p.A
10" 20p.A
4.5
Out- 9.5
put
Carry 4.5
Out- 9.5
put
II
~
-
-
1.5.
-
-
-
-
-
-
-
2
V
1
V
rnA
-
1
rnA
-
1.5.
-
1.5.
V
10
-
-
-
pA
:
3
Limits with black dot 1-) designate 100% testing. Refer to RIC-102B "High-Reliability COS/MOS CD4000A Slash (II Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters un~r given test conditions and do not represent 100% testing.
Note 1: Complete functional test, all inputs and outputs to truth table;Note 2: Test is either a one input or a one output only.
536
Note 3;· Test on all inputs and outputs.
File No. 736
- - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4029A Slash (/) Series
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C, VSS = OV, CL = 15 pF, and input rise and fall times = 20 ns,
except trCL and tfCL Tvpical Temperature Coefficient for all values of VDD = 0.3%/OC
LIMITS
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
VDD
(Volts'
UNITS
NOTES
650
230.
ns
1
425
150
850
300.
ns
1
100
50
200
100
ns
-
200
100
400
200
ns
-
200
100
340
170
ns
-
CD4029AD, CD4029AK
Min.
Typ.
Max.
325
115
CLOCKED OPERATION
tTHL,
tTLH
5
10
Minimum Clock
Pulse Width
tWL.
tWH
5
10
-
Clock Rise & Fall Time
trCL ....
tlCL
5
10
-
-
tSHL.
tSLH
5
10
-
325
115
ICL
5
10
1.5
3.
2.5
5
Propagation Delay Time:
o Outputs
5
10
tpHL,
tPLH
5
10
Carry Output
Transition Time:
Outputs
5
10
o
Carry Output
Set-Up Times
*
Maximum Clock
Frequency.
Input Capacitance
15
650
230
5
5
10
-
325
115
650
230
5
10
-
425
150
tWH
5
10
-
115
80
850
300
330
160
t rem
5
10
-
-
325
115
650
230
CI
ns
-
-
Any Input
/.Is
IS.
MHz
pF
-
PRESET ENABLE
Propagation Delay Time:
o Outputs
Carry Output
Reset Enable
Pulse Width
Preset Enable
Removal Time
tPHL.
tpLH
-
ns
ns
ns
-
ns
-
ns
-
CARRY INPUT
Prop~tion
Delay Time:
Cerry Output
tpHL,
tPLH
I
5
10
I
-
I
175
50
I
350
100
I
*From Up/Down, Binarv/Decade or Carry Input Control Inputs to Clock Input.
.
.. If more than one unit is cascaded in the parallel clocked application, tret. should be made less than or equal to the sum of the fixed propaga-
tion delay at 15 pF and the transition time of the carry output driving stage for the estimate capacitive load.
NOTE1: Test Is a one-input, one·output only.
Limits with black dot (-) designa"te 100% testing. Refer to RIC·102B "High-Reliability COS/MaS C04000A Slash (/J Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
537
CD4029A Slash (/) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 736
106 AMBIENT TEMPERATURE (TA)·ZSoC
INPUT tr"tf-20ns
~
i
!!.
IIJ
105
10 4
'!>.
LOAD CAPACITANCE
- - Cl *50pF
10 2
10
103
(CLl'l~pF
104
INPUT CLOCK FREQUENCY (fCLI- kHz
$2CS'22840
Fig. 8-Max. clock frequency vs. VDO-
92CS-1782.9RI
Fig. 9- Typ. dissipation characteristics.
10V
16
51/0RIOV
15
16
15
14
I.
'"i--+-.......
13
I.
o
"
10
10
0-0
L&V vi; :;j;i
~
TOl~!\::'.:7 ...L
-=-
OUTPUT
92CS-19111Rl
92CS-19110
Fig. 10- Quiescent device current test circuit.
538
Fig. 11- -Noise-immunity test circuit.
File No. 737 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
OOm5Ll[]
Digital Integrated Circuits
Monolithic Silicon
Solid State
Division
High-Reliability Slash(/) Series
CD4030A/...
14
voo
13 H
High-Reliability' COSIMOS
Quad Exclusive-OR Gate
(Positive Logic)
12 G
"
M
10 L
9 F
vss
8 E
J-A(t)B
L" E®F
K"C(£)D
M"GG;)H
For Logic Systems Applications in Aerospace,
Military, and Critical Industrial Equipment
Special Features:
• Medium speed operation ....... tpHL = tPLH = 40 ns (typ.) @ CL = 15 pF
and VOO-VSS = 10 V
• Low output impedance ....... soon (typ.) @ VOO-Vss = 10 V
Applications:
• Even and odd-parity generators and checkers
• Logical comparators
• Adderslsubtractors
• General logic functions
RCA C04030A "Slash" (I) Series are high-reliability COSI
MOS integrated circuits intended for a wide variety of logic
function configurations in aerospace, military, and critical
industrial equipment. The C04030A types each contain
four independent Exclusive-OR gates integrated on a single
monolithic silicon chip. Each ElIClusive-OR gate consists of
four N·channel and four P-channel enhancement-type transistors. All inputs and outputs are protected against electro·
static effects.
92CS-11410RI
These devices are electrically and mechanically identical with
standard COSIMOS C04030A types described in data
bulletin 503 and OATA800K SSO·203 Series, but are
specially processed and tested to meet the electrical,
mechanical, and environmental test methods and procedures
established for microelectronic devices in MI L-STO-883.
ALL P-CHANNEL sueSTR~A::T:ES:-t=~=::;:=1-_.J
ARE INTERNALLY CONNECTED TO Voo
ALL N- CHANNEL SUBSTRATES
ARE INTERNALLY CONNECTED TO Vss
Fig. I-Schematic diagram for 1 of 4 identical exclusive-OR gates.
The packaged types can be supplied to six screening levels lIN, I1R, II, 12, 13, 14 - which correspond to MIL-STO-883
Classes "A". "B", and "C". The chip versions of these types
can be supplied to three screening levels - 1M, IN, and IR.
For a description of these screening levels and for detailed
TRUTH TABLE FOR ONE OF
FOUR IOENTICAL GATES
information on test methods, procedures, and test sequence
A
B
employed with high-reliability COSIMOS devices refer to
High-Reliability Report RIC-702C, "High-Reliability COSI
MaS CD4000A "Slash" (II Series Types".
0
,
0
0
,
1
The C04030A "Slash" (I) Series types are supplied in
14·lead dual-in-line ceramic packages ("0" suffix), in 14 lead
0
J
0
, ,,
0
WHERE "'" = HIGH LEVEL
"0" = LOW LEVEL
ceramic flat packages ("K" suffix), or in chip form ("H"
suffix).
9-74
539
CD4030A Slash (I) Series _ _ _ _ _ _ _ _ _---..,_ _ _ _ _ _ _ _ _ _ _ _ FiI~ No. 737
STATIC ELECTRICAL CHARACTERISTICS (All inputs ..•......•.•......•.•..••...•..••• VSS'" vI:> VODI
(Recommended DC Supply Voltage (VDD - VSSI •.••••..••• 3 to 15 VI
LIMITS
CHARACTERISTIC
SYMBOL
TEST
CONDITIONS
UNITS NOTES
CD4030AD. CD4030AK
Vo VDD
Volts Volts Min.
-ssoC
Typ. Max. Min.
25°C
Typ. Max. Min.
12SoC
Typ. Max.
S
10
O.S
O.Se
O.OOS 0.5
0.D1 0.5.
30
'L
lQ.
PA
Quiescent Device
Dissipation/Package Po
5
10
2.5
10
0.025 1.5
0.1
10
150
100
lIN
3
5
10
15
0.55.
0.D1
0.01
Quiescent Device
Current
Output Voltage:
Low-Level
VOL
3
High-Level
VOH
Threshold Voltage:
N·Channel
P·Channel
VTHN
VTHP
Noise Immunity
(All inputs)
For Definition,
See Appendix in
4.99
9.99
ID =·10PA
'D - 10PA
VNL
-
VNH
2.3.
4.99
5
9.99 10
14S.
2.25
10
15
0
0
0.5.
0.01
0.01
0.5.
-0.7. ·1.7
0.7. 1.7
.c.7. ·1.5
-0.7e 1.5
·3.
3.
0.95
2.9
3.6
7.2
5
10
5
10
1.5
3.
1.4
2.9.
1.5.
3.
1.5.
3.
0.5
0.5
4.5
9.5
10
5
10
0.75
1.5
·0.45
·0.95
0.6. 1.2
1.2. 2.4
-0.25. ·0.6
-0.6. ·1.3
0.05
V
0.05
0.55.
4.95
9.95
14A50 -
·3.
3.
2.25
4.5
2.25
4.5
V
-0.3. 1.3
0.3a 1.3
·3.
3.
V
V
1.4_
2.9
V
1.5.
3
V
2
550·207
Output Drive Current:
N-Channel
P-Channel
ION
lOP
Diode Test 1 OO~
Test Pin
I
Input Current
1.5.
III
V,
=0
orVOO
0.45
0.9
·0.21
.(l.45
rnA
2
rnA
1.5.
I- I- I- I-
110
1.5.
V
3
I- I- i- i
I-
PA
Limits with black dot (.) designate 100% testing. Refer to RIC·l02B "High-Reliability COS/MOS C04000A Slash (J) Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1: Complete functional test, all inputs and outputs to truth table.
Note 3: Test on all inputs and outputs.
Note 2: Test is either a one input or one output on Iv.
For·Threshold Voltage Test Circuits. Operating and Biased Life Test Circuits. Output Drive Current Telt Circuits.
and for Operating Considerations, see Appendix
MAXIMUM RATINGS,Absolute·Maximum Values:
Storage·Temperature Range ... . . . . . . ..
Operating·Temperature Range. . . . . . . . . ..
DC Supply·Voltage Range:
(VDD - VSS) ..................... .
Device Dissipation (Per Package) ........ .
All Inputs
-65 to +150
-55 tp +125
GATE-TO-SOURCE VOLTS(VGSI-re
-0.5to+15 V
200
mW
VSS::YI.:'SVDD
Recommended
DC Supply·Voltage (VDD - VSS)
AMBIENT TEMPERATURElTA)-2e "C
TYPICAL TEMPERATURE COEFFICIENT
30 FOR ID --0.3 %'-C
°c
°c
3 to 15
V
Recommended
Input·Voltage Swing ................ VDD to VSS
Lead Temperature (During SOldering)
At distance 1/16" ± 1/32"
(1.59 ± 0.79 mm) from case
+265 DC
for 10 s max . . . . . . . . . . . . .
j
'z"
10
~ 10
5
_
10
15
DRAIN-TO-SOURCE VOLTS (VDsl
20
9:1!:CS-19113
Fig. 2- Typ. N-channel drain characteristics.
540
File No. 737 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD4030A Slash (/) Series
DYNAMIC ELECTRICAL CHARACTERISTICS atTA = 25°C. VSS= OV. CL = 15pF. and all input rise and fall times = 20ns
Typical Temperature Coefficient for all values of VDD = 0.3%lo C. (See Appendix for Waveforms)
LIMITS
TEST CONDITIONS
CHARACTERISTICS
SYMBOL
CD4030AD. CD4030AK
VDD
IVolts)
Propagation Delav Time
Transition Time:
'TLH
Input Capacitance
-
5
10
5
10
'THL
Low-la-High Level
-
5
10
·'PHL.
'PLH
High-ta-Low Level
Min.
-
Any Input
CI
Typ.
Max.
100
40
200
100.
70
25
80
30
150
75.
150
75.
ns
1
ns
1
ns
-
5
NOTES
UNITS
-
pF
en
Limits with black dot (.) designate 100% testing. Refer to RIC·l028 "High-Reliability COS/MOS CD4000A Slash
Series Tvpes", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
NOTE 1: Test is a one input one output onlv.
DRAIN-TO-SOURCE VOLTS (VOSI
-zo
-15
-10
o
-5
-5
o
~~~:~:l :::~~~~:~~~~~ ~~AJF=F~~~iNT FOR
I
'i!300 ALL VALUES OF VDD ·O.3%I·C
2-
-10
1
"' 200
::::E
ATE-TO-SOURCE VOLTSIVGS'--15V
1;
g
z
0100
10
15
~
-30
AMBIENT TEMPERATURE (TA'- 25-C
TYPICAL TEMPERATURE COEFFICIENT
FOR ALL VALUES OF VDD--o.3%/OC
92CS~19114RI
;t
~
o
o
20
40
60
80
100
lOAD CAPACITANCE ICll -
Fig. 3- Typ. P-channel drain chacteristics.
120
pF
140
160
92CS-19115
Fig. 4-.Tvp. propagation delay time \fl. CL.
•
.300
I
AMBIENT TEMPER ATURE (TAl ~ 2SoC
TYPICAL TEMPER ATURE COEFFICIENT FOR
ALL VALUES OF VDD·0.3°/0/,,(;
:}i"PPLY
VOLTS
-.
(VDDI
,~~
3
::
,\;1.o/t."
..J-200
LW,
}o
::"
0
....
}s
,,~
"'';:"
z
AMBIENT TEMPERATURE ITA). 25·C
LOAD CAPACITANCEICLJ.ISpF
«"l:.:
<~
100
't,.,,\..
..
in
z
CD4030AE
CD4030AD
CD4030AK
....
0
20
40
60
80
100
120
LOAD CAPACITANCE (Cli -
pF
140
160
10
SUPPLY VOLTS IVDOI
zo
15
92CS-191L7RI
Fig. 5- Typ. transition time
VI.
CL.
Fig. 6-Max. propagation delay time ..s. VDD.
541
CD4030A Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 737
104
1 "IIIBIENTTEMPERATUREIT,,)=25OC
10V
14
13
r--+"'--v-
I.I--......Hi--o-10
TO·,zl--+-++-++-I-++-++-+----JH+t-+-+-Hci
INPUT FREQUENCY (fi)-Hz
92CS-174rZRt
;ZCS-19118
Fig. 8-Quiescen t device current test circuit.
Fig. 7- Dissipation VI. input frequency.
VOO
3 V OR 7 V
5VORIOV
14
13
I.
11
10
7
8
I~--
--±G=-
~
-:;:"
ANY
OUTPUT
I
92CS -t9fJ9RZ
Fig. 9- Noise-immunity test circuit.
542
File No. 738 _ _ _ _ _ _ _----:_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
[IDOBLJD
Solid State
Division
IN
CL
NC{
Monolithic Silicon
High-Reliability Slash(l) Series
CD4031A/ ...
High-Reliability COS/MOS
64-stage Static Shift Register
RECIRCU-
LATION
Digital Integrated Circuits
I.
2
I.
I.
TOP
VIEW
I.
"
12
..
"
Q
ii
vss
10
VDD
DATA IN
For Logic Systems Applications in Aerospace,
Military, and Critical Industrial Equipment
}NC
MODE CONTROL
CLD
TERMINAL ASSIGNMENT
C04031AD
CD4031AK
92CS-2Z903
Applications:
For use in digital equipment where low-power dissipation,
low package count, andlor high noise immunity are primary
design requirements.
• Serial shift registers
" Time delay circuits
RCA CD4031A "Slash" (I) Series are high-reliability COSI
MOS integrated circuits intended for a wide variety of logic
function configurations in aerospace, military, and critical
industrial equipment. The CD4031A is a 64-stage static shift
register in which each stage is a D-type, master-slave flip-flop.
The logic level present at the data input is transferred into
the first stage and shifted one stage at each positive·going
clock transition. Maximum clock frequencies up to 2
Megahert2 can be obtained. Because fully static operation is
allowed, information can be permanently stored with the
clock line in either the "low" or "high" state. the CD4031A
has a mode control input that, when in the "high" state,
allows operation in the recirculating mode. Register packages
ean be cascaded and the clock lines driven directly for
high-speed operation. Alternatively, a delayed clock output
(CLD) is provided that enables cascading register packages
while allowing reduced clock drive fan-out and transition-
Features:
• Fully static operation: DC to 4 MHz @ VDD-VSS = 10V
" Operation from a single 3 to 15 V positive or negative
power su pply
II High noise immunity
" Microwatt quiescent power dissipation: 10/J.W (typ.1
" Full military operating temperature range: _55°C to
+125°C
" Single-phase clocking requirements
• Protection against electrostatic effects on all inputs
a Data compatible with TTL-DTL
" Recirculation capability
a Two cascading modes:
Direct clocking for high-speed operation
Delayed clocking for reduced clock drive requirements
time requirements.
Data (0) and Data (0) outputs are provided from the 64th
register stage. The Data (a) output is capable of driving one
TTL or DTL load. These devices are electrically and
mechanically identical with standard COS/MOS CD4031 A
types described in data bulletin 569 and DATABOOK
SSD-203 Series, but are specially processed and tested to
meet the electrical, mechanical, and environmental test
methods and procedures established for microelectronic
devices in MIL-STD-BB3. In addition to the RCA HighReliability "Slash" (II Series, RCA will offer these circuits
screened to MI L-M-3B51 O.
RECIRCULATION
IN
92CS-19145RI
Fig. 1-Functional diagram.
9-74
543
CD4031A Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No_ 738
MIL-M-3851 0 Designation
MIL-M-3851 0/05705
RCA Designation
C04031A
MAXIMUM RATI NGS, Absolute-Maximum Values:
Storage-Temperature Range .......... .
The packaged types can be supplied to six screening levels - Operating-Temperature Range·.......... .
I1N,I1R, 11,/2,/3, 14 - which correspond to MIL-STO·883 DC Supply-Voltage Range:
Classes "A", "B", and "C". The chip versions of these types
(VOO -VSS)·····················
Device Dissipation (Per Package) ........ .
can be supplied to three screening levels - 1M, IN, and IR.
All Inputs
For a description of these screening levels and for detailed Recommenci.;d ...................... .
information on test methods, procedures, and test sequence
employed with high·reliability COSIMOS devices refer to
High-Reliability Report RIC-l02C, "High-Reliability COSI
MOS CD4000A "Slash" (I) Series Types".
Th~
C04031A "Slash" (/) Series types are supplied in
16-lead dual-in-line ceramic packages ("0" suffix), in 16-lead
ceramic flat packages ("K" suffix), or in chip form ("H"
suffix).
-65 to +150
-55 to +125
-0.5 to +15 V
200 mW
VSS~VI~VOO
DC Supply-Voltage (VOO - VSS) .... .
3to 15
V
Recommended
Input-Voltage Swing. . . . . . . . . . . . . . .. VOO to VSS
Lead Temperature (During Soldering)
At distance 1/16" ± 1/32"
(1.59 ± 0.79 mm) from case
for 10 s max................ : .... .
+265 °c
MODE
CONTROL
CL
CL
C
t
fi.
INPUT CONTROL CIRCUIT TRUTH TABLE
L
,
RECIRe.
MODE
X
0
X
0
0
0
,
DATA
CLo
X
X
,
BIT INTO
STAGE I
,
,
0
J
0
X' DONT CARE
Input to Output is:
(al A Bidirectional Shan Circuit when Control
Input 1 il "loW-' and Control Input 2 is
TYPICAL STAGE TRUTH TABLE
0
CL·
0
J
J
,
x
"-
0+'
0
,
NC
NC· NO CHANGE
X· DON'T CARE
... LEVEL CHANGE
92CS-19019
"High"
(I))
An Open Circuit when Control Input 1 i.
"High" and Control Input 2 Is "Low"
·TG.~ TRANSMISSION GATE
Vss
Fig. 2-CD4031A logic diagram and truth rabies.
10V
5V OR IOV
WITH 51 AT GROUND ,CLOCK UNIT 64 TIMES
BY CONNECTING 52 TO PULSE GENERATOR.
RETURN S2 TO GNo AND MEASURE LEAKAGE
CURRENT. REPEAT WITH SI AT Voo.
Fig. 3-QuiescBnt device cum:nt.
544
°c
°c
Fig. 4-Noise immunity.
File No. 738
CD4031 A Slash (/) Series
STATIC ELECTRICAL CHARACTERISTICS (All inputs .................................. VSS';;; VI .;;; Vool
(Recommended OC Supply Voltage (VOO - Vssl •.••••••••• 3to 15 VI
CHARACTERISTIC
Quiescent Device
Current
Quiescent Device
Dissipation/Package
Output Voltage:
Low-Level
SYMBOL
LIMITS
TEST
C04031AO. C04031AK
CON ITIONS
Vo VOO
-5SoC
25°C
Volts Volts Min. Typ. Max. Min. Typ. Max. Min.
10
25.
0.5
10
10
25.
600
500.
/JA
Po
5
10
50
250
2.5
10
50
250
3000
5000
JNI
VOL
3
5
10
15
0.550
0.01
0.01
0
0
0.5.
0.01
0.01
O.s.
0.05
0.05
0.550
OH
4.99
10 9.99
15
IL
2.2So
High-Level
Threshold Voltage:
N-Channel
P-Channel
Noise Immunity
IAlllnpu,sJ
For Definition,
See Appendix in
SSO-207
VTHN
VTHP
P·Channel
0.8
1.0
4.2
9.0
VNH
0.4
0.5
0.5
0.5
0.5
CLO
0.5
4.5
0
9.5
4.5
Q
9.5
4.5
CLD
9.5
0
ION
lOP
a
2.34.99
5
9.99 10
14S.
-0.7_ -1.7
10" ·20/JA
10" 20/JA
VNL
Output Drive Current:
N·Channel
UNITS NOTES
125°C
Typ. Max.
0.7.
1.7
-3.
3.
1.5.
3.
1.5.
3.
1.5
10 3.
5 1.4
10 2.9.
4.5
10
5
10
5
10
10
5
10
5
10
1.6
-
0.11
0.24
0.48
1.5
-0.4
-0.850
-0.11
-0.24
-0.48
-1.0
-0.7. -1.5
0.7. 1.5
1.S.
-0.3. -1.3
1.3
-3.
3.
0.3e
-
1.4
2.9.
1.5
V
-3.
3.
V
V
V
V
30
1.3. 2.6
8
0.09. 0.18
0.2. 0.4
0.4. O.S
1.2. 2.4
-0.32 -0.64
-0.70. -1.4
-0.09 -0.18
-0.20. -0.4
-0.40 -O.S
-O.SOo -1.6
9.6
Diode Test 100 IJA.
2.25
4.5
2.25
4.5
4.95
9.95
14.45, -
V
0.91
5.6
0.06
0.14
0.28
0.84
-0.22
-OA9
-0.06
-0.14
-0.28
-0.56
1.5.
rnA
-
-
rnA
1.5.
V
3
Test Pin
Input Current
II
10
pA
Limits with black dot 1_) designate 100% testing. Refer to RIC·102B "High·Reliability COS/MaS CD4000A Slash (I) Series Types". Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
NOle 1: Complete.functional lest. all inputs and oulputs to truth lable.
NOle 2: Test is either a one inpul or one output onlv.
Note 3: Te51 on all inpulS and oulpUlS.
545
CD4031A Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 738
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C. Vss = OV, Cl = 15pF (unless otherwise specified), and input
rise and fall times = 20 ns, except trCl and tfCl.
Typical Temperature Coefficient for all values of VDD = 0.3%fOC. (See Appendix for Waveforms)
liMITS
CHARACTERISTICS
Propagation Delay Clock
to Data Output Q & O·
Clock to ClD
SYMBOL
t~HL
CL = 60pF
tPLH
Transition Time:
Q Output
Q Output
TEST CONDITIONS
VDD
IVolts)
tTHL,
tTLH
CD4031AD CD4031AK
Min.
-
5
10
5
10
-
5
10
5
10
5
10
-
-
Max.
400
200
400
200
800
400
800
400
75
30
300
150
200
100
150
60
600
300
400
200
ns
-
2
1
/.IS
1
200
50
400
100
ns
-
0
20
50
ns
-
MHz
1
pF
-
Clock Rise & Fall Time··
trCL.
t,CL
5
10
Set-UpTime
tSHL.
tSLH
5
10
too
5
10
'CL
5
10
0.8
2.
2
4
-
60
5
CL = 60pF
Data Overhang Time
Maximum Clock"'''''''
Frequency
Input Capacitance Clock
All Others
·Capacitive loading on
-
CI
NOTES
Typ.
-
CLD Output
UNITS
-
-
-
ns
1
Q output affects propagation delay of Q output. These limits apply for Dload CL < 15pF •
... *If more than one unit is cascaded in the parallel docked application. trCL should be I1'8de 'lSI than or equal to the sum of the PropaSllltion
delay.' 16pF and the transition time of the output driving stage •
•• -Maximum Ctock Frequency for Cascaded Units;
al Using Delayed Clock Feature - 'max = (n.1 J CLO prop. delay + a'prop, delay + ".-up time where"· number of peckegH
b) Not Using Delayed Clock -
fmax " propagation delay1+ .t-up tinw
Limits with black dot 'e) designate 1(~O% testing. Refer to RIC-102B "High-Reliability COS/MOS CD4000A Slash (n Series Types". Tables 2
through 7 for tes~ing sequence. All other limits are designer's parameters under given test conditions and do not repre;ent 100% testing.
AMBIENT TEMPERATURE {TA 1- 25"C
TYPICAL TEMPERATURE COEFFICENT FOR
30 ALL VALUES OF VOO"-0.3"1./"C
lrlil
111
·tHIIL' I".j 'tI'
~t·:-~·t- i -r:: !fi
...'"
'" 20
"-'-'
-20
DRAIN-TO-SOURCE VOLTS(VoS.
-15
-10
-5
o
-5
o
-10
-IO~
~
~
~
:Ii
"
ATE-Ta-SOURCE V-
15
ro
";::z
Q
10
'DO
~
~
~
30
20
LOAD CAPACITANCE ICL 1- pF
92CS-19749
NOTE: 'TIlL FOR Q OUTPUT IS SIGNIFICANTLY LESS THAN 'TLH
Fig. 9- Tvpical transition time vs, CL for data outputs.
AMBIENT TEMPERATURE ITAI-25·C
3
ALL VALUES OF VOO
a
0
,
O.3%/oC
AMBIENT TEMPERATURE ITA)' 25°C
TYPICAL TEMPERATURE COEFFICIENT
FOR ALL VALUES OF Voo:O 3%/ O C
,
,
''''''''II':~
-Q"" q~
~
..... oq ,c., ~'\)o, o+~
~ .....
0 Q'\)o A",.... ~
.....
/,,"'.v.I~I
.
8
0
/
DO'
10 2
2
4
h
6
e 10 3
2
~""
"<.,.9:-
~ ....0
,
20
~~"p'-6-
c.,
,y ...
,
92CS-22904
4~
.........<,.;
~'9-~.?~
0'
10
15
SUPPLY VOLTS IVOOI
/I
~·:'
,
8
0CO
-. .
o
100
.rl ~~~~~
,
o
90
92CS-197150
Fig. 10-Typical transition time vs. CL for delayed clock output.
,0
TYPICAL -TEMPERATURE COEFFICENT FOR
~
80
40
50
60
70
lOAD CAPACITANCE (Cl) - pF
1
vYi
~~ LA
1.1
r.
4
6
104
o~
'J
,G;,
0
2
4
6
e 105
2
CLOCK FREOUENCY (fCl) - Hz
92CS-19752
Fig. 1 7-Maximum clock frequency vs. V DO
Fig. 12- Typical pOII'.'f!r dissipation vs_ frequency.
547
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ·File No. 739
Digital Integrated Circuits
OO(]3LJ1]
Monolithic Silicon
Solid State
High-Reliability Slash(/) Series
CD4032A/... CD4038A/...
Division
High-Reliability
COS/MOS Triple Serial Adder
',-""--,--,
., '
INVERT,
Positive Logic Adder - CD4032A
Negative Logic Adder - CD4038A
For Logic Systems Applications in Aerospace,
Military, and Critical Industrial Equipment
'2 ~-+l-r-"
·2 '
INVERT 2
'
I
Special Features:
SUM3
• Invert inputs on all adders for sum complementing applications
• Fully static operation. . . . .dc to 5 MHz (typ.1
• Buffered outputs
• Single-phase clocking
• Microwatt quiescent power dissipation. . . . . 5 p.W (typ.1
RCA CD4032A and CD4038A "Slash" (I) Series are high·
reliability COS/MaS integrated circuits intended for a wide
variety of logic function configurations in aerospace, military,
and critical industrial equipment. The CD4032A and CD4038A
types consist of three serial-adder circuits with common clock
and carry·reset inputs. Each adder has provisions for two serial·
data input signals and an invert command signal which (when
a logical "1 ") complements the sum. Data words enter the
adder with the least sign'ificant bit first; the sign bit trails.
The output is the MOD 2 sum of the input bits plus the carry
from the previous bit position. The carry is only added at the
positive·going clock transition for the CD4032A or at the
negative-going clock for the CD4038A. For spike·free oper·
ation the input data transitions shou"ld occur as soon as possible after the triggering edge.
The carry is reset to a logical "0" at the end of each word by
applying a logical "1" signal to a carry·reset input one bit·
"~~~p
·'iT
Applications:
• Serial arithmetic units
• Digital correlators
• Digital datalink computers
• Flight control computers
• Digital servo control systems
position before the application of the first bit of Ihe next
word. Figs.2 and 4 show definitive waveforms for all inpui and
output signals.
These devices are electrically and mechanically identical with
standard COS/MaS CD4032A and CD4038A types described
in data bulletin 503 and DATABOOK SSD·203 Series, but are
specially processed and tested to meet the electrical, mechani·
cal, and environmental test methods and procedures established
for microelectronic devices in MIL·STD·883.
A
CL
INVERT
CARRY
-+-+-+-+-++++...r-t-t-t-t-j-j--1H
RESET
SUM
CLOC
WORD I 0.0111100 = +60
WORD 2 0,01 IDOl 0" +50
0.1101110 =+110
~gDERS
> ____......__]
WORD 3 1.1011011--37
WORD 4 1.1001110"-50
T.OTOTOOT. -87
283
Fig.2 - CD4032A timing diagram.
92CS-17661RI
Fig. ,.- CD4032A logic diagram of one of three serial adders.
548
9·74
File No. 739 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4032A, CD4038A Slash (I) Series
The packaged types can be supplied to six screening levels 11 N, 11 R, 11, 12, 13, 14 - which correspond to MI L·STD·883
Classes "A", "6", and "C". The chip versions of these types
can be supplied to three screening levels -1M, IN, and IR.
For a description of these screening levels and for detailed
information on test methods, procedures, and test sequence
employed with high·reliability COSIMOS devices refer to
High·Reliability Report RIC·l02C, "High·Reliability COSI
MaS CD4000A "Slash" III Series Types".
The CD4032A and CD4038A "Slash" (I) Series types are
supplied in 16·lead dual·in·line ceramic packages ("D" suffix),
in 16·lead ceramic flat packages ("K" suffix), or in chip
form ("H" suffix).
MAXIMUM RATINGS,Absolute-Maximum Values:
Storage·Temperature Range . , , , • , , •...
Operating·Temperature Range:, , , , •......
DC Supply·Voltage Range:
(VDD - VSS) .....................
Device Dissipation (Per Package) • , . . . . . . .
All Inputs , .............. , ..........
Recommended
DC Supp,ly·Voltage (VDD - VSS) .. ,"
Recommended
Input·Voltage Swing ......... , , , , , ..
Lead Temperature (During Soldering)
At distance 1/16"± 1/32"
(1.59 ± 0,79 mm) from case
for 10 s max. . ......... ,"', ..•...
CL
INVERT
CARRY
RESET
SUM
CLOCK
':».......f':>--......---I---
] ~~DERS
-0,5 to +15 V
200 mW
VSS~VI~VDD
3 to 15
V
VDD to VSS
°c
+265
-ijjjjjjci\::t:t:±:±:±±:l--t=
WORD I 1.1000011 --61
WORD2 1.1001101 =-51
1.0010000 "'-112
2 6"3
-65 to +150 °C
-55 to +125 °c
WORD 3 0.0100100 =+36
WORD 4 0.0110001 -+49
0.1010100 -+85
92C5-19121
Fig.3 - CD4038A logic diagram of one of three serialadders.
Fig.4 - CD4038A timing diagram.
AMBIENT TEMPERATURE ITA)- 25·C
TYPICAL TEMPERATURE COEFFICIENT
FOR ALL VALUES OF voo·a.?
'.I-e
LOAD CAPACITANCE (ell -
LOAD CAPACJTANCEICLI-pF
pF
92CS-1912.2.
Fig.S - Typ. propagation delay time
invert inputs to sum outputs.
VR.
CL for A, 8. or
92CS-19123
Fig.6 - Typ. transition time vs. CL for sum outputs.
549
CD4032A, CD4038A Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 739
STATIC ELECTRICAL CHARACTERISTICS (All Inputs ••. VSS ~ VI::;' VDD)
Recommended DC Supply Voltage 3 to 15 V
N
LIMITS
CHARACTERISTIC
SYMBOL
Vo
-55°C
V DD
Volts Volts
Quiescent Device
5
IL
Current
Quiescent Device
Dissipation/Package
Output Voltage:
Low Level
10
5
Po
10
3
5
'VOL
High-Level
10
VOH
Threshold Voltage:
N-Channel
P-Channel
Noise Immunity
(Alllnpu,s)
See Appendix in
550·207
Output Drive
Curr~nt:
N-Channel
P-Channel
ION
lOP
Diode Test
100 IlA test pin
-
0.5
5
10"
-
1
10-
25
100
-
2.5
1500
10
25
100
-
-
-
2000
-
0.5-
-
-
-
5
4.99
10
9.99
15
-
10 = 20 "A
VNH
Min.
5
2.25-
VTHP
For Definition,
Max.
-
3
10 = -20 "A
VNL
Min".
JOO
200-
-
0
0.01
-
0.01
'-
0
-
-
-
0.01
0.5-
-
0.05
0.05
0.55-
4.95
-
"A
1
9.95
14.45
-
"W
V
1
V
1
-
2.34.99
5
9.99
14.5-
10
-
-
-
-0.7.
-3.
-0.7
-1.5
-3.
-O.t.
-3.
V
0.7•.
3.
0.7.
1.5
3.
0.3.
3.
V
1.5
3-
-
1.5-
2.25
-
3-
4.5
-
1.4
.-
2.9..
V
2.25
4.5
-
U;
-
0.9.
2.4
-
0.3
0.6
•
O.B
5
1.0
10
4.2
5
9.0 .10
-
1.5-
2.9-
0.5
0.5
5
10
0.6
0,75
-
0.5-
-
0.7-
4.5
5
-0.21
9.5
10
-0.7
.-
-0.55-
1.4'
3-
-0.23- -0.4
-1.2
1.5-
-
II
-
0.01
-
T
E
S
-
VOF
Input Current
0.55-
UNITs!
125°C
Max.
Max. Min.
25°C
Typ.
15
VTHP
0
CD4032AD, CD4032AK
CD403BAD, CD403BAK
TEST
CONDITIONS
-
-
3_
10
-
1
V
rnA
2
0.07
-
-0.3E
-
rnA
1.5-
V
-
pA
1.5-
-
-
2
-
3
Limits with black dot (e' designate 100% testln9. Refer to RIC·l02B "High-Reliability COS/MOS CD4000A $:Iash (/) Series Types", "Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1: Complete functional test, all inputs and outputs to truth table.
Note 2: Test is either a one input or one outpu1 onty.
Nate 3: Test on all Inputs and outputs.
AMBIENT TEMPERATURE ITA)02S0C
INPUT Ir 0,,020"1
LOAD CAPACITANCE {CU o I5pF
10'
'§.
I
~
SUPPLY VOLTS
{VDD)~15
10
10'
5
z
a
~
~
10'
Ei
<5
~
;
lOP
-:;;
5'
1--1·-
lOl
, ---f-
l--\-10
10
10
CLOCK FREQUENCY !tCL )-kHl
92CS-19124
Fig.7 - Typ. dissipation characteristics.
550
Fig.8 - Quiescent del/ice current test circuit CD4032A.
File No. 739 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4032A, CD4038A Slash (I) Series
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 2So C. Vss = OV. C l = ISpF. and input rise and fan times - 2On., except
Typical Temperature CoefficiBnt for an valuB' of VDD =O.3%I"C. (See Appendix for Waveforms)
t,Cl and 'tCl .
LIMITS
CHARACTERiSTICS
SYMBOLS
NOTES
TEST CONDITIONS CD4032AD,CD4032AK
CD4038AD, CD4038AK UNITS
""\i"i)[)
(Volts)
Propagation Delay Time:
A, B, or Invert
Inputs to Sum Outputs
Clock Input
to Sum Outputs
t pHl ,
Transition Time
(Sum Outputs)
t THl .
tTlH
** trCl.
tlCl
Clock
Rise & Fali.Time
tplH
Min.
Typ.
Max.
5
-
400
1100
10
-
125
250
5
-
800
•
2200
10
-
250
500.
5
-
125
375
10
-
50
150.
5
-
-
15
10
-
-
15
-
-
5
Input Set·Up Times *
~
10
Maximum Clock
Frequency
IC'l
Input Capacitance
CI
Any Input
t,Cl
5
1.5
2.5
-
10
3.
5
-
-
5
-
ns
1
ns
1
ns
1
I.IS
1
•
-
1
MHz
pF
* "This characteristic refers to the minimum time required for the A, B. or Reset Inputs to change state following a POSitive clock transition
(CD4032A) or negative transition ICD4038A\.
** If more than one unit is cascaded t,el should be made less than or equal to the sum of the transition time and the fixed propagation delay
of the output of the driving stage for the estimated capacitive load.
Limits with black dot (_) designate 100% testing. Refer to R1C-102B "High-Rp.liabilitv COS/MOS CD4000A Slash (II Series Types", Tables 2
through 7 for testing sequence. All other limits are desiqne('s parameters under given test conditioPoS·and do not represent 100% testing.
I.
Note 1: Test is a one-input, one-output only.
15
3.5VOR7V
"
13
12
1.5 v OR 3 v FOR "0" TEST
3.5vOR7v FOR "1 TEST
M
10
r-------------------~----------~_{Il
10V
1.5VOR 3.5V
LOVOR 3V
9
o v t "0"
V
TEST)
5VORIOV'-I"TEST]
92CS-I!;I126
Fig_9 - Noise-immunity test circuit CD4032A.
"1..fo---H-j
92CS-19128
92C5-19121
Fig. TO - Quiescent device current test circuit CD4038A.
1.5 V OR:5 V
L5vOR3v
Fig.lt - Noise-immunity test circuit CD4038A.
551
File No. 740
OOm5LJD
Solid State
Division
CD4034AK
Digital Integrated Circuits
Monolithic Silicon
High-Reliability Slash(/) Series
CD4034A/•..
High-Reliability COS/MOS
MSI a-Stage Static
Bidirectional Parallel/Serial
Input/Output Bus Register
24.Lead
CD4034AD
:z4.L..d
DIC
'"
~
,:
,
I'· "",-
'
,,""
For Logic Systems Applications in Aerospace,
Military, and Critical Industrial Equipment
24
VIEW
• Bidirectional parallel data input
• Parallel or serial inputs/parallel outputs
• Asynchronous or synchronous parallel data loading
"A" ENABLE
SERIAL INPUT
• Parallel data-input enable on "A" data lines
RCA CD4034A "Slash" (I) Series are high-reliability COS/MOS
integrated circuits intended for a wide variety of logic
function configurations in aerospace, military, and critical
industrial equipment. The CD4034A is a static eight-stage
parallel- or serial-input parallel-output register. It can be used
to: 1) bidirectionally transfer parallel information between
two buses, 2) convert serial data to parallel form and direct the
parallel data to either of two buses, 3) store (recirculate)
parallel data, or 4) accept parallel data from either of two
buses and convert that data to serial form. Inputs that control
the operations include a single phase clock (Cl), "A"-data
enable (AE), Asynchronous/synchronous (A/S), "A" bus to
"B" bus/"B" bus to "A" bus (A/B), and parallel/serial (P/S).
Data inputs include 16 bidirectional parallel data lines of which
the eight "A" data lines are inputs (outputs) and the "B" data
lines are outputs (inputs) depending on the signal level on the
A/B input. In addition, an input for serial data is also provided.
All register stages are D-type master-slave flip-flops with
separate master and slave clock inputs generated internally to
allow synchronous or asynchronous data transfer from master
to slave. Isolation from external noise and the effects of
loading is provided by output buffering.
PARAllEL OPERATION
A "high" PIS input signal allows data transfer into the register
via the parallel data lines synchronously with the positive
transition of the clock provided the A/S input is "low". If the
AtS input is "high" this transfer is independent of the clock.
The direction of data flow is controlled by the A/B input.
When this signal is "high" the A data lines are inputs
(and B data lines are outputs); a "low" A/B signal reverses the
direction of data flow.
. .
TOP
Special Features:
AlB
Vss
~
""
~
~
3
CLOCI
AIS
PIS
TERMINAL ASSIGNMENT
CD4034AI<
CD4034AD
• Data recirculation for register storage
• Multipackage register expansion
• Fully static operation DC-to-5 MHz (typ.) at VOD-VSS = 10 V
App/ications:
• Parallel Input/Parallel Output,
Parallel Input/Serial Output,
Serial Input!Paraliel Output,
Serial Input/Serial Output Register
• Shift right/shift left register
• Shift right/shift left with parallel loading
•
•
•
•
Address register
Buffer register
Bus system register with enable parallel lines at bus side
Double bus register system
• Up-Down Johnson or ring counter
• Pseudo-random code generators
• Sample and hold register (storage, counting, display)
• Frequency and phase comparator
'A'
ENABLE
A'.
AIS
PIS
CLOCK
92(5-19202
Fig. I-Functional diagram.
552
...
8 Voo
" ,
0
'"",. a
"", , !<
"
""
22
9-74
File No. 740 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4034A Slash (/) Series
These devices are electrically and mechanically identical with
standard COS/MOS C04034A types described in data bulletin
575 and OATABOOK SSO-203 Series, but are specially pro-
MAXIMUM RATI NGS, Absolute-Maximum Values:
Storage-Temperature Range
Operating-Temperature Range ..... .
OC Supply-Voltage Range:
(V OO - VSS) ...
Device Dissipation (Per Package) ...
All Inputs
Recommended
OC Supply-Voltage (VOO - VSS)
Recommended
I nput-Voltage Swing .....
Lead Temperature (Ouring Soldering)
At distance 1116" ± 1/32"
(1.59 ± 0.79 mm) from case
for 10 s max . . . . . . . . . . . . . . . . . . .
cessed and tested to meet the electrical, mechanical, and
environmental test methods and procedures established for
microelectronic devices in M I L-STO-883.
The packaged types can be supplied to six screening levels 11 N, 11 R, 11,12, 13, 14 - which correspond to MI L·STD-883
Classes "A", "8", and "e", The chip versions of these types
can be supplied to three screening levels -1M. IN, and IR.
For a description of these screening levels and for detailed
information on
employed with
High-Reliability
MaS CD4000A
test methods, procedures, and test sequence
high-reliability COSIMOS devices refer to
Report RIC-102C, "High-Reliability COSI
"Slash" II) Series Types'~
-65 to +150 aC
-55 to +125 aC
-0.5 to +15 V
200
mW
VSS:S VI:S VOO
3 to 15
V
VOO to VSS
+265
aC
The C04034A "Slash" (I) Series types are supplied in 24-lead
dual-in-line ceramic packages ("0" suffix), in 24-lead ceramic
flat packages ("K" suffix), or in chip form ("H" suffix!'
STATIC ELECTRICAL CHARACTERISTICS (All Inputs .. _ VSS S VI S VOO)
Recommended OC Supply Voltage 3 to 15 V
UNITS
N
0
T
E
S
"A
1
"W
-
V
1
V
1
V
2
LIMITS
CHARACTERISTIC
TEST
SYMBOL
CONDITIONS
Vo
Quiescent Device
D is!:ipat ion/Pack age
'L
PD
Output Voltage
Low·Level
Hlgh·Level
P·Channel
Noise Immunity
(Any Input)
For Definition,
See Appendix
VTHN
IO=-10}..lA
VTHP
10'" 10}..lA
V NL
V NH
I
12SoC
2SoC
Max.
Min.
Typ.
Max.
Min.
0.3
5
-
-
5
-
Max.
300
10
-
10"
-
0.5
10"
-
200·
5
-
25
-
2.5
25
-
1500
10
-
100
--
10
100
-
2000
3
-
0.55-
-
-
0.5-
-
-
5
-
0.01
-
0
0.01
-
0.05
10
0,01
0.01
-
0.5-
-
O.OS
-
-
0
15
-
0.55-
3
2.25-
-
2.3-
-
-
--
-
5
499
-
10
999
15
Threshold Voltage
N·Channel
Min.
5
VOL
VOH
_55°C
VOO
Volts Volts
Quiescent Device
Current
CD4034AD, CD4034AK
-
i -
4.99
5
-
4.95
-
999
10
9.95
14S e
-
--
-
0.70
·3.
·~0.7
0.7 0
30
07
--
1.5-
O.B
5
1.5
1.0
10
3"
4.2
.
0
-1.5
14.4S e
-3. -0.30
1.4
-
2.9-
-
1.5
-
2.25
3"
4.5
--
.
-3.
3 •
-
0.3
•
1.5
3
5
1.4
1.5-
2.25
9_0
10
2.g e
3"
4.5
0.5
5
0.124
D.'·
0.2
0.07
-
0.5
10
0.31
0.5
0.175
-
4.5
5
-0.075
-0.05-
a 1
9.5
10
-O.lBB
-0,125-
-0.25
V
1
V
3.
S50·207
Output Drive Current
'ON
N·Channel
P·Channel
'DP
0.25 e
-
0.035
-
mA
2
mA
2
O.OB
Diode Test,lOO JJA
Test Pin
V OF
1.5-
1.510
Input Current
"
l.5 e
V
-
pA
3
--
..
" Tables 2
Limits with black dot (e) deSIgnate 100% testing. Refer to RIC·' 026 Hlgh·Rellablllty COS/MOS CD4000A Slash (Il Series Types.
through 7 for testing sequence. All other limits are deSigner's parameters under given test conditions and do not represent 100% testing.
Note'
Complete functional test. all mputs and outputs to truth table
Note 3: Test on all mputs and outputs.
Note 2: Test is either a one Input or one output only
553
CD4034A Slash (/) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 740
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 250 C, Cl = 15 pF
Typical Temperature Coefficient for all value. of VDD = 0.3%I"C (See Appendix for Waveform.)
CHARACTERISTICS
SYMBOLS
TEST
CONDITIONS
CD4034AD,CD4034AK
VDD
Volts
Typ.
600
1200
240
480·
5
200
400
tWH
10
-
100
175
Minimum High·level
AE, PIS, AIS
Pulse Width
tWH
5
10
-
240
85
480
195
Clock Rise
*trCL,
5
15
10
-
-
tfCl
-
15·
5
tpHL'
tOI
10
Transition
tTHl,
5
Time
tTlH
10
Minimum Clock
Pulse Width
and Fall Time
5
-
Set-Up Time
10
Maximum Clock
Frequency
Input Capacitance
fCl
CI
Any Input
ns
1
ns
-
ns
-
ns
-
IlS
1
ns
-
Max.
tWl,
Delay Time
*
Min.
-
Propagation
UNITS
N
0
T
E
S
250
750
100
300
250
500
100
2110
2.5
5
1.5
10
3.0·
5
-
MHz
1
-
5
-
pF
-
If more than one unit is cascaded, trCL should be made less than or equal to the sum of the fixed propagation delay at 15 pF
(see chart above) and the transition time of the output driving stage for the estimated capacitvie load.
Note 1: Test is aone input one outPrUrt~o=n=IY3'S;===t=A~I'~'~===t~J~~jJ20_\ll-
___"
A.
23
6 STAGES
SAME AS STAGE I
IASYN~:~YNC) 0----1.....-'
•
/If
Tt:. TRANSItISSION GATE
o0
o0
o ..
INPUT TO OUTPUT IS
.) A BIDIRECTIONAL LOW IMPEDANCE
WHEN CONTROL INPUT I IS "LOw"
AND CONTROL INPUT 2 IS "HIGH"
'\,
'\,
.r
'\,
'\,
J'
OPEN CIRCUIT WHENCOHTROl.
.r
.r x
'\,
'\,
~)AN
INPUT 1 IS "HIGH" AND CONTROL. INPUT 2 IS "L.Ow"
.r
Fig. 2- Logic diagram.
554
'\,
.r
0
II
II
'*
t::. LEVEL CHANGE
X OON'T CARE
'"'INVALID CONDITION
File No. 740 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4034A Slash (/) Series
CLOCK
ENAABLE
1
PIS
AlB
I
A/S
n'--___----'n'--________--'r--
n~======~===--
SERIAL
DATA
AI
A2r-l_ _ _ _ _ _ _ _ _ _ _ _ __
A3
A4 r - l ' - -_ _ _ _ _ _ _ _ _ _ _ _ __
A5
A6r-l'--_ _ _ _ _ _ _ _ _ _ _ ___
A7
ABr-l~
______________________~r_tIl_
L-________
-I---~
B2
~
84
B5
' - - - - -_ _ _ _ _ILJL
L-JL..Jl
I
r - I- - - - - - ,
,.--u-u
B61
B7~----------~;---~====
B8 'I----------~
.~---
r!
'------'
B DATA LINES ARE OUTPUTS
---_-!92CM-19196
Fig. 3- Timing diagram.
AMBIENT TEMPERATURE (TAl: 25"C
TYPICAL. TEMPERATURE COEFFICIENT
FOR ALL VALUES OF Voo =0.3 "/oI"e
800
400
20
60
LOAD CAPACITANCE ICLI- pF
Fig. 4-TypicaJ propagation delay time vs. CL.
60
LOAD CAPACITANCE {Cll- pF
92C5-19213
Fig. 5-Typical transition time vs. CL.
555
CD4034A Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 740
::2
2:
]
::
~
8
:::
MBIENT TEMPERATURE
10' AMBIENT TEMPERATURE ITAla2S-C
ITAI·2~·C
LOAD CAPACITANCE ICL)aI5pF
ALTERNATING ·0"
.
;0
~
6
~
AND "'," PATTERN
10'
w
10·
4
11
10'
~
==
Q
i
2ii5
i
10
15
,
:>."\~
~
fl":'''
~,~
"
"
10
~_E
"/
FS\)~
~
10 2
I,,~OQ ~I
d-'S ~
--
20
10
LOAD CAPACITANCE tCL}-15pF
- CL -50pF
10 2
103
104
INPUT CLOCK FREQUENCY ifCL1- kHz 92CS-17806R3
SUPPLY VOLTS (VOO)
92CS-20071
Fig. 7- Typical dissipation characteristics,
Fig. 6- Typical input frequency vs. VDD'
5 V OR 10 V
10V
TEST PERFORMED WITH
THE FOLLOWING SEQUENCE OF HIGH (HI AND
LOW-LEVEL{LI INPUTS
51
L
52
H
S3
H
L
H
H
H
L
L
H
H
H
S4 55
l
H
H
L
H
L
L
L
H
H
L
L
H
L
L
l
H
H
92CS-19206
1.5 V OR 3 V
92CS-19207RI
Fig. 9- Noise immunity test circuit.
Fig. 8- Quiescent device current test circuit.
,VDD
----=-90%
-----50%
-----'10% 0
~AM
OR"B"
DATA
INPUTS
~~-------~. 0
"B" OR "A"
DATA
OUTPUTS
LOD
tTHL
----90%
----50%
----10%0
92CS-20077
*~'fR~IL R,if;uRf, l~:~~/°t. 6~EA~~'~~~~aT~ATA
** tSLH
INPUTS,"A"ENA8LE,
AND ISH!.. ARE SET-UP TIMES
92CS-20018
Fig. 10- Synchronous operation propagation
delay times, transition times, and set-up times.
556
Fig. 11-Asynchronous operation propagation
delay time.
File No. 751 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
ffil(]5LJO
Solid State
Division
Digital Integrated Circuits
Monolithic Silicon
High-Reliability Slash(/) Series
CD4035A/ ...
High-Reliability COS/MOS 4-Stage
Parallel In/Parallel Out
2
3
Shift Register
Ol/el
TRUE/COMP.
SER.{'
IN
1{
ClK
PIS
TIC
RESET
I.
with J-K Serial Inputs and True/
Complement Outputs
vDD
CLOCK
PIS
10
"
Q2I02
03/Q3
04/Q4
PI-4
PI-3
PI-2
vss
9
PI-I
RESET
CD4035A
4-STAGE REGISTER
I.
I.
TOP
VIEW
i5
13
12
TERMINAL ASSIGNMENT
C04035AO
CD4035AK
92CS-ZZ905
For Logic Systems Applications on Aerospace,
Military, and Critical Industrial Equipment
RCA C04035A "Slash" (I) Series are high·reliability COS/
MOS integrated circuits intended for a wide variety of logic
function configurations in aerospace, military. and critical
industrial equipment. The C04035A is a four·stage clocked
serial register having provisions for synchronous parallel
inputs to each stage and serial inputs to the first stage via JK
logic. Register stages 2, 3, and 4 are coupled in a serial "0"
flip·flop configuration when the register is in the serial mode
(ParaliellSerial control low).
Parallel entry via the "0" line of each register stage is per·
mitted only when the Parallel/Serial control is "high". In the
parallel or serial mode information is transferred on positive
clock transitions.
When the True/Complement control is "high", the True con·
tents of the register are available at the output terminals.
When the True/Complement control is "low", the outputs
are the complement> of the data in the register. The True/
Complement control functions asynchronously with respect
to the clock signal.
JK input
logic is provided on the first stage serial input to
minimize logic requirements particularly in counting and
sequence·generation applications. With JK inputs connected
together, the first stage becomes a "0" flip·flop. An asyn·
chronous common reset is also provided.
These devices are electrically and mechanically identical with
standard COS/MOS C04035A types described in data bulle·
tin 568 and OATA800 K 550·203 Series, but are specially
processed and tested to meet the electrical, mechanical, and
environmental test methods and procedures established for
microelectronic devices in MI L·STO·883.
Applications:
a Sequence generation, control circuits, code conversion
.. Counters, Registers, Arithmetic·Unit Registers, Shift
Left - Shift Right Registers, Serial·to·ParalieIlParallel·toSerial conversions.
Features:
" 4·Stage clocked shift operation
" Synchronous parallel entry on all 4 stages
inputs on first stage
" Asynchronous True/Complement control on all outputs
" Reset control
D Static flip·flop operation; Master·slave configuration
" Buffered outputs
II Low·Power Oissipation . 5 iJ. W typo (ceramic)
a High speed - to 5 MHz
" .iR
The packaged types can be supplied to six s'i::reening levels /1 N, /1 R, /1, /2, /3, /4 - which correspond to Mi L-STO-883
Classes "A", "B", and "C". The chip versions of these types
can be supplied to three screening levels - /M, IN, and /R.
For a description of these screening levels and for detailed
information on test methods, procedures, and test sequence
employed with high-reliability COSIMOS devices refer to
High·Reliability Report RIC-l02C, "High· Reliability COSI
MaS CD4000A "Slash" III Series Types'~
The C04035A "Slash" (I) Series types are supplied in 16·
lead dual·in·line ceramic packages ("0" suffix). in 16·lead
ceramic flat packages ("K" suffix), or in chip form ("H"
suffix).
9·74
557
CD4035A Slash (/) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 751
MAXIMUM RATINGS, Absolute·Maximum Values:
Storage-Temperature Range ..........
Operating-Temperature Range ..........
DC Supply·Voltage Range:
(VOO - VSSI ....................
Device Dissipation- (Per Packagel __ ......
All Inputs
. -65 to +150
. -55 to +125
°c
°c
. -0.5 to +15 V
.
200
mW
VSS$VI$VOO
Recommended
DC Supply·Voltage (VOO - VSSI
3 to 15
V
Recommended
Input·Voltage Swing...........
VOO to VSS
Lead Temperature (During Solderingl
At distance 1/16" ± 1132"
(1.59 ± 0.79 mml from case
for 10 s max. .....................
+265
0c
STATIC ELECTRICAL-CHARACTERISTICS (All Inputs ... V SS '" V , '" VOO' Recommended OCSupplv Voltage 3 to 15 V
LIMITS
CHARACTERISTIC
SYMBOL
TEST
CONDITIONS
VDD
Volts Valts
-55·C
Vo
c).liescent Oevice
IL
Current
Ouiescent Device
Dissipation/Package
Output Voltage
Po
Min.
-
5
-
10"
5
25
5
-
om
10
-
0.01
VOH
-
100
0.55-
3
2.2S-
5
4.99
10
9.99
15
-
-
-0.7O.~
15
High-Level
Max.
5
3
N-Channel
VTHN
In= -201'A
VTHP
10 = 20pA
Noise Immunity
VNL
(Any Inputl
VNH
N·Channel
P-Channel
- Diode Test. 100 pA
Test Pin
Input Current
ION
lOP
-
Max.
Min.
0.3
5
0.5
10-
1.5
25
-
5
100
-
0.5-
0
0.01
0
0.01
0.5-
-
4.99
5
9.99
10
14.S-
-
-3'"
-O.~
-1.5
3-
O.~
1.5
1.5-
2.25
-3'"
3'"
-
3-
4.5
5
1.4
-
1.5-
2.25
10
2.9-
3'"
4.5
0.5
5
0.62
0.5
10
4.5
5
1.55
-{l.31
-
1.2S-{l.2S-
-0.5
9.5
10
-{l.Bl
-
-0.65-
-1.3
-
1.S-
-
-
1.5-
10
-
4.2
5
VOF
-
II
-
0.5-
-
-
MM.
300
2001500
2000
1
2.5
I'W
-
V
1
V
1
V
2
0.55-
9.95
14.45
-
-0.3'"
1
0.05
-
4.95
I'A
0.05
-a3'"
0.3
1.4
10
O.B
9
Output Drive Current:
Typ.
T
E
S
125°.C
1.5
3-
1
For Definition,
See Appendi.
Min.
2.3-
Threshold Voltage:
P-Channel
UNITS
25·C
10
10
VOL
Low-Level
N
0
CD4035AD, CD4035AK
V
-{l.45
-
-
1.S-
V
3
-
pA
-
2.se
1.5
30.35
0.B7
-{l.17
1
V
rnA
2
rnA
2
Limits with black dot (-, designate 100% testing. Refer to RIC·1028 "High-Reliability COS/MaS CD4000A Slash (II Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1: Complete functional test, all inputs and outputs to truth table.
Note 2: Test is either a one input or a one output only.
Note 3: Test on all inputs and outputs.
For Threshold Voltage Test Circuits, Operating and Biased Life Test Circuits, Output Drive Current Test Circuits, and for Operating
5 V OR 10 V
Considerations, see Appendi)(~
16
~VOR
IOV
IS
"13
12
"
10
9
9'2CS-L9976Ri
Fig. 1-Noise immunity test circuit.
558
92C5-L9975
Fig. 2-Quiescent device current test circuit.
File No. 751 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4035A Slash (I) Series
PARALLEL
.'
SERIAL'
CONTROLIP/SI
.ov--t"'"l_/
.A.!I
RESET
TRUE/taMPL.
'&2
.TICI
P/S'O'SERIAL .... OOE
TIC' ,. TRUE OUTPUTS
.,
FIRST STAGE TRUTH TA8I..E
I,.IOUTPUTS)
In_,tINPUTSI
oJ
..
.,
.0
.,
TERMINAL No.l6,vOD
Cft_1
TERMINAl. No. II'GND
~,
INPUT TO output 15;
alA IIIDIREe110NAL LOW IMPEDANCE
W!'IEN C01'ITROL IPriPUT , IS'LOW'
AfrI.O CONTR~L INPUT Z IS 'tllGH'
INPUT PROT[CTIONCIRCUIT
bl AN OPEN CIRCUIT WHEN CONTROL
INPUT liS "HIGH' AND CONTROL
INPUT Z IS'LDW'
Fig. 3-Logic Black Diagram.
AMBIENT TEMPERATURE
ITA1~25·C
TYPICAL TEMPERATURE COEFFICIENT FOR ALL VALUES
OF Veo -0.3 -'" I·e
CLOCKED OPERATION
I'
J
~
:; 400
~
a 300
13
z
o
!«
~g:
;:
~
200
100
e:
100
~
~
~
~
~
W
LOAD CAPACITANCE ICLI- pF
~
00
~
10
20
30
40
50
60
70
80
90
LOAD CAPACITANCE (CL1-pF
92:C5-19968
Fig. 4- Tvpical Propagation Delay Time vs. Load Capacitance.
92CS-19969
Fig. 5- Typical Transition Time vs. Load Capacitance.
559
CD4035A Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 751
DYNAMIC ELECTRICAL CHARACTERISTICS at TA - 25"C and CL - 15 pF
Typical Temperature Coefficient for all values of VOO = 0.3')(,!C
LIMITS
CHARACTERISTICS
SYMBOLS
TEST
CONDITIONS
VDD
(VollS)
CD403IiAD.
CD403IiAK
N
0
T
E
S
UNITS
Min.
Typ.
Mall.
5
-
250
500
10
100
200.
100
200
10
-
CLOCKED OPERATION
Propagation Delay Time:
Transition Time:
tplH'
tpHl
5
tTHl'
tTlH
Minimum Clock
'Wl'
tWH
Pulse Duration
Clock
Rise & Fall Time
'fCl
ttCl
*.
Setup Time:
:iiKlines
Maximum Clock
5
-
200
335
-
100
165
15
5
10
-
-
Input Capacitance
CI
-
250
100
5
500
100
350
50
80
1.5
2.5
-
5
-
-
5
-
-
250
500
10
100
200
5
-
200
400
10
-
100
175
3 •
10
Any Input
1
ns
1
ns
-
jIS
1
ns
200
-
5
tCl
FreqUency
100.
10
5
10
5
10
Parallel·ln line.
50
ns
MHz
1
pF
-
ns
-
ns
-
RESET OPERATION
Propagation Delay Time:
Minimum Reset Pulse
Duration
5
tpHl'
tplH
tWl'
tWH
Limits with black dot '.1 designate 100% testing. Refer to RIC-l02B "High-Reliability COS/MOS CD4000A Slash (n Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1: Test is either a one Input or a one output only_
.'If mare than one unit is cascaded t rCL should be made less than or equal to the sum of the fixed propagation delay time at 15 pF and the
transition time of the output driving stage for the estimated capacitive load.
.
10' AMBIENT TEMPERATURE (TA)-2S-C
ALTERNATING ·0·
'"
i
!!o
....
g
if:
~
AND ·1· PATTERN
10'
104
10'
Q
f
iii<;
!
.~~
== == ~~
-~
V
~~"
10'
v
10
LOAD CAPACI'mNCE (CL)-"pF
--CL-SOpF
V
10
10
SUPPLY VOLTS (VDD)
... ~_E
,.\~
\.~O:O: ~
10 2
INPUT CLOCK FREQUENCY (feL) -
10'
Fig. 6- Typical clock input frequency VB. V DO
560
104
kHz 9ZCS-17806R3
92CS-19970
Fig. 7- Typical dissipation characteristics.
File No. 749
Digital Integrated Circuits
ffil(]3L}[]
Monolithic Silicon
Solid State
High-Reliability Slash(/) Series
C04036A/ ... , C04039A/ ...
Division
High-Reliability COS/MOS
4-Word by 8-Bit
Random-Access NORO Memory
C04036AK
CD4039AK
"
.. -~"
24-Lead
~~:latPack
For Logic Systems Applications on Aerospace,
Military, and Critical Industrial Equipment
CD4036AD
CD4039AD
24-Lead
DIC
.
~
~-• -
H·t7S0
Binary Addressing
Direct Word-Line Addressing
CD4036AD, CD4036AK
CD4039AD, CD4039AK
Special Features:
•
•
•
COS/MOS logic compatibility at all input and output terminals
Memory bit expansion
Memory word expansion via Wire·OR capability at the 8 INPUT-BIT
and 8 OUTPUT-BIT lines
RCA CD4036A and CD4039A "Slash" (/) Series are high·
reliability COSIMOS integrated circuits intended for a wide
variety of logic function configurations in aerospace, military, and critical industrial equipment. The C04036A is a
single monolithic integrated circuit containing a 4-word x
B·bit Random Access NORD Memory. Inputs include B
INPUT-BIT lines, CHIP INHIBIT, WRITE, READ INHIBIT,
MEMORY BYPASS, and 2 ADDRESS inputs. B OUTPUT·
BIT lines are provided.
All input and output lines utilize standard COSIMOS inverter
configurations and hence can be directly interfaced with
COSIMOS logic devices.
CHIP INHIBIT allows memory word expansion by WIREDRing of multiple CD4036A packages at either the B·bit
input andlor output lines (See Fig. 1). With CHIP INHIBIT
"high", both READ and WRITE operations are inhibited on
the CD4036A. With CHIP INHIBIT "low", information can
•
•
•
•
•
Memory bypass capability for all bits
Buffering on all outputs
CD4036A- on-chip binary address decoding, separate READ
INHIBIT and WRITE controls
CD4039A-Direct word·line addressing
Access Time-200 ns(Typ) at V 00=10 V
Applications
Digital equipment where low power dissipation and/or high
noise immunity are primary design requirements.
• Channel Preset Memory in digital frequency·synthes;"zer
circuits
• General-purpose and scratch-pad memory in COS/MOS and
other low-power systems.
be written into and/or read· continuously from one of the
,'
"
BYPASS
\ 1-------6,
\1-------6,
BIT OUlPUTS
BIT O!JTPUTS
Fig. 1- CD4036A -
9·74
Logic block diagram.
Fig. 2-CD4039A -- Logic block diagram.
561
CD4036A, CD4039A Slash (II Serie.s _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
File No. 749
The packaged types can be supplied to six screening levels /IN,/lR,/l,/2,/3,/4 - which correspono to MIL-STD·883
Classes "A", "B", and "C". The chip versions of these types
can be supplied to three screening levels - 1M, IN, and fR.
four words selected by the binary code on the two address
lines. With CHIP INHIBIT "low", a "high" WRITE signal
and a "low" READ INHIBIT signal activate WRITE and
READ operations, respectively, at the addressed word location (See Fig. 91.
For a description of these screening levels and for detailed
information on test methods, procedures, and test sequence
The MEMORY BYPASS signal, when "high", allows shunting of information from the B I NPUT-BIT lines directly to
the B OUTPUT-BIT lines without disturbing the state of the
4 words. During the bypass operation input information may
also be written into a selected word location, provided the
CHIP INHIBIT is "low" and the WRITE is "high". The
READ operation is deactivated during the BYPASS operation because information is fed directly from the B INPUTBIT lines to the B OUTPUT-BIT lines.
employed with high-reliability COSIMOS devices refer to
High-Reliability Report RIC-102C, "High-Reliability COSI
MaS CD4000A "Slash" (II Series Types".
The CD4036A and CD4039A "Slash" (II Series types are
supplied in 24-lead dual-in-line ceramic packages ("0"
suffixl, in 24·lead ceramic flat pack'ages ("K" suffixl, or in
chip form ("H" suffixl.
RCA type CD4039A is identical to the CD4036A with the
exception that individual address-line inputs have been provided for each memory word in place of the binary
ADDRESS, CHIP INHIBIT, and READ INHIBIT inputs.
When Wire·Oring multiple CD4039A packages for memory
word expansion, an individual CD4039A is selected by'
addressing one of its word locations. The READ operation is
MAXIMUM RATINGS, Absolute-Maximum Values:
Storage-Temperature Range .......... . -65 to +150 °c
Operating-Temper.ature Range .......... . -55 to +125 °c
DC Supply-Voltage Range:
.
(VDD - VSS) , . , . , . , .. , . , ... , ..... -0.5 to +15 V
Device Dissipation (Per Package) , , , . , , , , '
200
mW
activated whenever a word location is addressed (via a "high"
All Inputs ." .. ,.,." .. "., .. " .. , .. VSS < VI < VDD
Recommended
3 to 15
V
DC Supply-Voltage (VDD - VSS) ... ,.
Recommended
Input-Voltage Swing ........ , . . . . . .. VDD to VSS
Lead Temperature (During Soldering)
At distance 1/16" ± 1/32"
(1,59 ± 0,79 mml from case
for 10 s max . . . . . . . ,', ..... , ..... .
+265 °c
signal-see Fig. 101.
These devices are electrically and mechanically identical with
standard COS/MOS CD4036A and CD4039A types de- "
scribed in data bulletin 613 and DATABOOK SSD-203
Series, but are specially processed and tested to meet the
electrical, mechanical, and environmental test methods and
procedures established for microelectronic devices in MI LSTD-BB3.
10V
5VORIOV 3.5VOR7V
0
•
7
•
C
D
•
0
0
6
A
I.
I.
17
I.
10
,.
"
"
13
12
TEST PERFORMED WITH
6~E 1'~O~~~'f: SEQUENCE
S,
'0
D
0
0
I
I
I
I
S2
aD
I
I
0
D
I
I
10V
So
,D
I
0
I
0
I
0
92CS-lOl03
4
• g 20
6 • I.
7 g I•
.:
17
16
S,
,0
"
I.
I>
92CS-20104
Fig. 3- Quiescent current (CD4036A).
562
Fig. 4- Quiescent current (CD4039AJ.
1.5VOR3V
92CS-20705RI
Fig. 5-·Noise im"!unity.
File
No.
749
CD4036A, CD4039A Slash (I) Series
STATIC ELECTRICAL CHARACTERISTICS
IMln
CHARACTERISTIC
Vo
Volts
N
0
T
CD4036AD. CD4036AK
CD4039AD. CD4039AK
TEST
CONOITIONS
SYMBOL
Voo
Volts
_55°C
Min.
125°C
25°C
Max,
Min.
Max.
TVp·
Min.
0.5
Quiescent Device
Current
IL
Quiescent Device
Dissipation/Package
Po
10
2.5
25
1500
100
10
100
2rlJO
0.5-
0.01
VOL
Low-Level
10
0.01
0.01
0
15
High-Level
VOH
10
200·
25
0.55-
Output Voltage:
1.45-
1.5-
4.99
4.99
9.99
9.99
15
S
f----
Joo
W-
lO-
10
Max.
0.05
0.01
0.05
0.5-
0.54.95
10
9.95
14.45-
14.5-
Threshold Voltage:
N-Channel
VTH N
10· -20pA
P·Channel
VTHP
10·20pA
Noise Immunity
0.8
VNL
(All inputs except
bit inputs when
in memory by-
10
VNH
9
pass mode.)
Output Drive Current:
Norm.1
Read
lOP
4.5
Modes
9.5
ION
Mem-
ION
N·Channel
P-Channel
Output Drive Current
N·Channel
0.5
0.5
lOP
0.5
BV'
4.5
pass
9.5
Mode +
Diode Test
10
1.5
1.58
J-
2.25
1.4
4.5
2.9-
1.5-
2.25
1.5
3-
-1.58
2.9_
J-
4.5
J-
0.12
0.10·
0.2
0.07
0.25-
O.J
0.5
0.17
-0.12
-0.10- -0.2
-0.07
-0.3
-0.25-
-0.17
0.5
0.03-
0.06
0.02
10
0.09
0.075
0.15
0.05
-0.04
-0.03°
0.06
-0.02
10
-0.09
-0.075
0.15
100 IJA Test Pin
VOF
3-
0.7-
0.04
0.5
O'V
P·Channel
10
_Jo
0.3-
-0.7-
J-
1.4
10
-O.J-
J-
-J-
0.71.5
4.2
_Jo
-0.7-
Input Current
2
-0.05
1.5·
1.5-
2
-
1.5·
10
Limits with black dot (-, designate 100% testing. Refer to RIC·102B "High·Reliability COS/MOS CD4000A Slash (f) Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's para~eters under given test conditions and do not represent 100% testing.
Note 1: Complete functional test, all il1,pulS and outputs 10 truth table.
Note J: Test on all mputs and outputs.
Note 2: Test is either a one Input or a one output only_
+Blt Inputs driven from low-impedance driver.
For Threshold Voltage Test Circuits, Operating and Biased Life Test Circuits, Output Drive Current Test Circuits, and for Operating
Considerations, see Appendix.
'1
2'
WRITE
2.
""~
22
21
20
IN
5
6
7
8
MEMORY
BYPASS
GND
5
6 CD4036A
7
10
/I
12
(V~~~)
"18
17
16
15
I.
13
WORD I
WRITE
VDD
A,
2'
2.
22
CHIP INHIBIT
READ INHIBIT
J~
5
6
7
OUT
•
B
Fig. 6aJ-C04036AD and CD4036AK tenninal assignments.
21
20
5
6 CD4039A 19
IN
•
""f
6
7
8
MEMORY
BYPASS
GND
7
B
9
10
/I
VOP)
VIEW
18
17
16
I.
I.
12
"
VDD
WORD 3
WORD 4
WORD 2
J'~
5
6
7
8
OUT
92CS-19936
bJ-CD4039AD and CD4039AK terminal assignments.
563
File No. 749
CD4036A, CD4039A Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25"c and CL ~ 15 pF
Typical Temparatuffl Coefficient for all value. of VDD = O.3%l'c
CHARACTERISTICS
SYMBOLS
Read Delay Time:
(Access time)
Read Inhibit (RI)
Chip Inhibit (CI)
OUTPUT TIED
THROUGH 100 kn
TO Vss FOR DATA
OUTPUT "HIGH"
AND TO VDD FOR
DATA OUTPUT
"LOW"
trd
Memory Bypass
(MB)
Address (ADD)
Write Set·up Time
tws
Write Removal Time
tWR
Write Pulse Duration
tw
Data Set· up Time
tDS
Data Overlap Time
too
tTHL,
tTLH
CI
Output Transition Time
I nput Capacitance
CD4036AD, CD4036AK
CD4039AD, CD4039AK
TEST
CONDITIONS
Min.
Typ.
5
10
-
375
150
750
300·
5
10
5
10
-
500
200
375
150
1000
400·
750
300·
500
200
125
50
0
0
75
30
O'
O'
250
100·
0
30·
150
60·
100A
40A
-
-
Any Input
UNITS
T
E
VDD
Volts
5
10
5
10
5
10
5
10
5
10
5
10
5
10
N
0
Max.
S
ns
4
ns'
4,7
ns
7
1000
400·
ns
1,7
-
J.l.s
2,7
ns
3, 7
ns
7
-
-
0
0
50
20
200
100
5
ns
5
-
ns
6
400
200
ns
-
-
pF
-
1. For CD4036A only. remove 10Q-kntest condition and write all 1's in word one, and all a's In word two, or vice·versa.
2. Delay from change of ADDRESS or CHIP·INHIBIT signals to application of WRITE pulse.
•
For footnote, SBS Page 563.
3. Delay from removal of WRITE pulse to change of ADDRESS or CHIP-INHIBIT signals.
4. Values for CD4036AD & 4036AK only.
5. The time that DATA signal must be present before the WRITE pulse removal.
S. The time that OAT A signal must remain present after the WR ITE pulse removal.
7. Test Is a one Input one output only.
.. Min. indicates satisfactory operation If too equals or exceeds this value.
Max. indicates satisfactory operation if tos equa's or exceeds this value,
1
15
DRAIN-TO-SOURCE VOLTAGE (VDS'-V
-15
2'·
fAloll!i}'
4
Q
/
,.,0"
I
!!o
/'
(CONSTANT ADDRESS)
4
8,0
/,,"
4
6
8100
4
FREQUENCY (f)-KHz
6 131000
92CS~207JO
Fig. 11- Typical power dissipation vs. frequency.
A.
0
I
'MlRD I
0---------------------0----------------------__
0----------------------
AI
0
I
I
I ••
WORD'
WRITE
0
WORD 3
CHIP
INHIBIT
0
IOORD 4
READ
0t;;=! ~ FwR
INHIBITO
MEMORY
BYPASS
I
WRITE
~ ----1- tw -L
I
0
MEMORY
BYPASS
DATA
IN
0
DATA
OUT
DATA
IN
,-
1_
0--
-.,...-----~~
(Rl)
I,d
(ADD)
(MBl
92CS~206t11
Fig. 12-C04036A Timing Diagram.
Fig. 13-CD4039A TIming Diagram.
565
- - - - - - - - - - - - - - - - 7 " ' - ' - - - - - - - - - - - - - - - - File No. 748
Digital Integrated Circuits
OOCIBLJD
Monolithic Silicon
Solid State
Division
High-Reliability Slash(/) Series
CD4040A/ •••
High-Reliability COS/MOS
12-Stage Ripple-Carry
Binary Counter/Divider
For Logic Systems Applications in Aerospace,
Military, and Critical Industrial Equipment
Features:
~
12 BUFFERED OUTPUTS
• Medium·speed operation . . . . .5-MHz (typ.) input pulse rate at
VOO-VSS = 10V
• Low "high"· and "low"·level output impedance . . . . . . 750 n
(typ.) at VOO-VSS = 10 V and VOS = 0.5 V
• Common reset
• Fully static operation
• All 12 buffered outputs available
• Low.power TTL compatible
012
I.
RCA C04040A "Slash" (I) Series are high·reliability COS/
MOS integrated circuits intended for a wide variety of logic
function configurations in aerospace, military, and critical
industrial equipment. The C04040A consists of an input·
pulse'shaping circuit and 12 ripple·carry binary counter
stages. Resetting the counter to the all-O's state is accomplished by a high·level on the reset line. A master·slave flipflop configuration is utilized for each counter stage. The
state of the counter is advanced one step in binary order on
the negative-going transition of the input pulse. All inputs
and outputs are fully buffered.
Applications:
• Frequency~ividing circuits
• Time~delay circuits
• Control counters
as
as
TOP
07
VIEW
04
03
02
13
08
09
12
•
10
01
vss
TERMINAL ASSIGNMENT
CD4040AD
CD4040AK
92CS- 22901
01 OUT = (QIHEr..)('Rl
>0----09
The paCkaged types can be supplied to six screening levels /1 N, /1 R, /1, /2, /3, /4 - which correspond to MI L·STO·883
Classes "A", "B", and "C". The chip versions of these types
can be supplied to three screening levels -1M, IN, and IR.
For a listing of the Screening Level Options available for
both packaged devices and chips, and for a description of the
C04040A "Slash" (I) Series types are supplied in 16lead dual-in-line ceramic packages ("0" suffix), in 16-lead
ceramic packages ("K" suffix), or in chip form ("H"
suffix).
voo
all
010
II
These devices are electrically and mechanically identical with
standard COSIMOS C04040A types described in data bulletin 624 and OATABOOK 550-203 Series, but are specially
processed and tested to meet the electrical, mechanical, and
environmental test mp.thods and procedures established for
microelectronic devices in MI L-STO-883.
For a description of these screening levels and for detailed
information on test methods, procedures, and test sequence
employed with high·reliability COSIMOS devices refer to
High-Reliability Report RIC-l02C, "High-Reliability COSI
MaS CD4000A "Slash" (I) Series Types".
IS
15
14
I} INPUTS
TO 2 nd
STAGE
01
• R-HIGH DOMINATES (RESETS ALL STAGES)
.ACTION OCCURS ON NEGATIVE GOING
TRANSITION OF INPUT PULSE.COUNTER
ADVANCES ONE BINARY COUNT ON EACH
NEGATiVE. TRANSITION (4096 TOTAL
BINARY COUNTS).
Fig. 1-Logic diagram of CD4040A input pulse shaper and
1 of 12 stages.
.
9·74
566
File No. 748 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4040A Slash (/) Series
INPUT PULSE SHAl'ER
Voo
.p-+-+--t---i
~
~-+----~r---~
iii}
'-------;---;-_'ll
TO NEXT
STAGE
ON COUNTER STAGE
NOTE: SUBSTRATES FOR ALL .p" UNITS ARE CONNECTED TO VDD
SUBSTRATES FOR AL L on- UNITS, UNLESS OTHERWISES SHOWN. ARE CONNECTED TO GROUND
9ZCM·21~9
Fig. 2-Schematic diagram of input shaping, reset buffe~, and one counter stage of CD4040A.
AMBIENT TEMPERATURE (TA) " 25·C
TYPICAL TEMP. COEFFICIENT AT ALL VALUES OF VGS=-Q3-J./·C
MAXIMUM RATINGS. Absolute·Maximum Values:
Storage-Temperature Range .......... .
Operating·Temperature Range .......... .
DC Supply·Voltage Range:
(VDD - VSS) .................... .
Device Dissipation (Per Package) ........ .
All Inputs
Recommend~d ..................... .
DC Supply·Voltage (VDD - VSS) .... .
-65 to +150
-55 to +125
°c
°c
-0.5 to +15 V
200
mW
VSS < VI < VDD
3 to 15
V
Recommended
Input·Voltage Swing ............... . VDD to VSS
Lead Temperature (During Soldering)
At distance 1/16" ± 1/32"
(1.59 ± 0.79 mm) from case
+265 °C
for 10 s max ..................... .
7.5
ATE-lO-SOURCE VOLTAGE IVG )-15V
B3.75
z
~ 2.5
IOV
1.25
5V
o
2.5
5
7.5
10
125
15
DRAIN - TO - SOURCE VOLTAGE (Vosl-V
92C5-21512
Fig. 3-Minimum n-channel drain, characteristics.
567
CD4040A Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 748
STATIC ELECTRICAL CHARACTERISTICS (AI/Inputs . •• Vss <. V, <. VOcY Recommendsd OC Supply Voltage 3 to 15 V
LIMITS
CHARACTERISTIC
SYMBOL
TEST
CONOITIONS
10
Ouiescent Device
DissipationlPlICkage
-
5
IL
Current
Min.
-
5
Po
10
. Ou"'1't Voltage
Low-Level
3
V
OL
HiQll·Level
VOH
5
Fanout
10
0150
COS/MOS
Inputs
15
-
15
2s"'
75
260
Min.
-
-
Typ.
15
1
2s"'
2.5
75
-
-
O.s"'
0
0.01
0.01
-
0
0.01
-
O.s"'
-
-
2.~
5
9.99
10
-
14.s"'
-
...{l.~
4
...{l.~
-1.5
o.r
r
O.r
1.5
4.99
10
9.99
15
-
-
4.99
2.2s"'
5
260
0.01
0.55-
-
3
MIX.
0.5
10
N
0
T
E
UNITS
125"C-
~·C
-66·C
Vo
VOO
Volts Volts
Quiescent Device
-.
C0404OAO. C04040AK
-
-
Min.
-
-
4.95
9.95
14.4s"'
S
MIX.
900
soo4500
5000
I'A
1
fJW
-
V
1
V
1
V
2
0.05
0.05
0.5s"'
-
-
Threshold Voltage:
N-·Channel
VTHN
'0= -20fJA
P..channel
Noise Immunity
VTHP
'0 - 201'A
0.8
VNL
IAnv Inputl
For Oefinition
SIlo Appendix
SS[)'207
l
VNH
Qnput Drive Current:
N·Channel
ION
P·Channe1
lOP
DiodeTest.lOOfJA
Test Pin
Input Current
I
4.2
5
1.5
2.25
3-
-
1.S-
10
~
4.5
5
1.4
-
1.5-
2.25
-
~
4.5
10
2.0-
0.5
5
0.22
0.5
10
0.44
4.5
5
...{l.15
9.5
10
...{l.3
9
VOF
II
-
-
1.s"'
-
0.145-
0.38
0.4-
0.75
0.1·
...{l.25
...{l.25-
...{l.6
-
~
r
-
-
-
I.s"'
10
-
...{l.~
~
O.r
3-
1.4
-
-
V
~
-
V
0.125
-
2.01.5
0.25
...{l.OSE
...{l.175
-
-
I
I
-
rnA
2
-
rnA
2
1.s"'
V
3
-
pA
-
-
Limits with black dot f.) designate 100% testing. Refer to RIC·102B "High-Reli_oilitv COS/MOS CD4000A Slash (II Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1: Complete functional test, all inputs and outputs to truth table.
Note 2: Test is either a one input or one output only.
Note 3: Test on all inputs and outputs.
For Threshold Voltage Test Circuits, Operating and Biased Life Test Circuits, Output Drive Current Test Circuits, and for Operating
Considerations, see Appendix.
568
File No. 748 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4040A Slash (I) Series
DYNAMIC ELECTRICAL CHARACTERISTICS, At TA =25°C, Vss =OV, CL = 15pF (unlossothBrwisespecified),
and input rise and fall times'" 20 ns, except t,cL and r,cL. Typical TemperaturB Coefficient for all values of VDO ... o.396fc.
TEST CONDITIONS
CHARACTERISTIC
SYMBOL
I VDD · I
Min.
Input-Pulse Operation
Propagation Delay
Time
Transition Time
Min.lnput·Pulse Width
Input-Pulse
Rise & Fall Ti me
I
UNITS
5
-
300
400
-
150
200·
'THL'
'TLH
5
-
150
300
10
-
75
5
f = 100KHz
'WL'
'WH
'rt/>
5
'ft/l
10
-
5
1.5
10
200
400
75
110
-
15
1.75
7.5
5-
6
-
5
-
5
-
500
10
250
500
5
-
500
1000
10
-
250
500
Any input
C1
ns
1,4
ns
4
ns
-
ps
2,4
MHz
4
pF
150.
-
10
NOTE
MBx.
10
ft/l
Input Capacitance
I
'PHL"
'PLH
Max. Input-Pulse
Frequency
CD4040AK, AD
Typ.
•
Reset Operation
Propagation Delay
'PHL
Time
Minimum Reset
'WH
Pulse Width
1000
ns
3
ns
-
Limits with black dot Ie' designate 100% testing. Refer to RIC-102B "High-Reliability COS/MOS CD4000A Slash II) Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
NOTES:
2. Maximum input rise or fall time for functional operation.
3. Measured from the pOsitive edge of tho roset pulse to tho
negative edge of any output (01 to Q12).
4. Test is a one input one output only.
1. Measured from the 50% level of the negetive clock edgo to tho
50% level of either the positive or negative edge of the Q1 output Ipin 9); or measured from the negative edge of Q1 through
Q11 outPuts to the positive or negative edge of the next higher
output.
DRAIN- TO-SOlKE VOLTAGE (VDS)-V
-15
-10
o
-5
5V
10V
-2.5
..
g
z
~
GATE - TO - SOURCE VOLTAGE (\tSl-15 V
AMBIENT TEMPERATURE ITA) - 2S·C
TYPICAL TEMP. COEFFICIENT AT ALL VALUES OF VGS - -Q3'"1.I·C
-7.5
9ZCS-Z1513
LOAD CAPACITANCE CCL)-pF
Fig.
4- Minimum p-channel drain, chafBcrerisrics.
Fig. 5- Typical propagation delay tima
load capacitance (per stage).
9ZCS-ZJ514
VI.
569
CD4040A Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 748
.
10' AMBIENT TEMPERATURE ITAI;25·C
~
I
10'
~~7 I"-
g
w
10'
~
10'
<#.,\10 /'
./
~
""
ill
'"
~
.,
~~
~
~
.,
i.'I;I"~ ~
'!>l>
./
10 2
.
"
10
I
./ ./
-
LOAD CAPACITANCE ICLi"15pF
- - - - CL s50pF
104
106
105
INPUT FREaUENCY (f.) -Hor
LOAD CAPACITANCE IC L'-pF
92CS-21S1'
92CS-20754
Fig. 7- Typical dissipation characteristics,
Fig. 6- Typical transit;on time w. load capacirance.
AMBIENT TEMPERATURE «T A) • 25-C
lOAD CAPACITANCE (Cl) -15 pF
5V OR IOV
I"
I'
C04040AO,A
3.5V
OR
14
13
.,.!.::!....
1.5 V
OR
3v
o
10
15
SUPPLY VOLTAGE CVDD)-V
20
92CS-17919
92CS-22902
Fig. 8- Maximum Input-pulse frequency vs. supply voltage.
Fig. 9- Rem-no;se";mmunity test circuit.
10V
5V OR IOV
TEST PERFORMED
IN ALL "o'SM STATE
AND ALL"j's·STATE
92CS-21521
92CS-119IeRI
Fig. 10-lnput-pulse nO;I8-immunity test/circuit.
570
.p
t=
Fig. 1,-.Qulescent-dev;cewcurrent test circuit.
File No. 753 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
[Rl(]5LJD
Digital Integrated Circuits
Monolithic Silicon
Solid State
Division
A
E
3~'
E.A
ZF
F·l
•
G
6~4
G'.
_'H
H·.
High-Reliability Slash(/) Series
CD4041A/•••
High-Reliability COS/MOS
Quad True/Complement Buffer
For Logic Systems Applications in Aerospace.
Military. and Critical Industrial Equipment
Features:
E
True Output
High current source and sink capability
8 mA (typ.1 @ VOS =0.5 V, VOO = 10 V
3.2 mA (tyP.) @ VOS = 0.4 V, VOO = 5 V
(two TTL loads)
Complement Output
Medium current source and sink capability
3.6 mA (typ) @ VOS • 0.5 V, VOO = 10 V
1.6 mA (typ.) @ VOS = 0.5 V, VOO = 5 V
F
•
H
Ie
2
3
4
5
B
6
A
G
RCA C04041A "Slash" (II Series types are high·reliability
COS/MOS integrated circuit Quad True/Complement Buffers
designed for a wide variety of logic function configurations
in aerospace, military, and critical industrial equipment. The
C04041A cbnsists:of n·and p·channel units having low channel
resistance and high current (source and sink) capability. It is
intended for use as a buffer, line driver, or COS/MOS·to·TTL
driver. It can also be used as an ultra·low power resistor·
network driver, and in other applications where high noise
immunity and low power dissipation are primary design
requirements.
These devices are electrically and mechanically identical with
standard COS/MaS C04041 A types described in data bulletin
572 and OATABOOK' SSO·203 Series, but are specially pro·
cessed and tested to meet the electrical, mechanical, and
environmental test methods and procedures established for
microelectronic devices in MI L-STO-883.
'The packaged types can be supplied to six screening levels '/1N,/1R,/l,/2,/3, 14 - which correspond to MIL-STO-883
Classes "A", "B", and "C", The chip versions of these types
can be supplied to three screening levels - 1M, IN, and IR,
For a description of these sc~eening levels and for detailed
information on
employed with
High-Reliability
MaS CD4000A
test methods, procedures, and test sequence
high-reliability COSIMOS devices refer to
Report RIC-102C, "High-Reliability COSI
"Slash" (I) Series Types':
The C04041A "Slash" (I) Series types are supplied in 14-lead
dual-in·line ceramic packages ("0" suffix), in the 14·lead
ceramic flat package ("K" suffix), or in chip form ("H" suffix I.
9-74
7
VSS
•
TOP
VIEW
14
13
12
II
10
9
8
VDD
D
N
M
C
L
K
TERMINAL ASSIGNMENT
CD4041AD
CD4041AK
92CS- 20755
Applications:
•
•
•
•
•
High current source/sink driver
COS/MOS-to-OTL/TTL converter
~isplay driver
MOS clock driver
Resistor network driver
(Ladder Dr weighted R)
•
Buffer
Transmission line driver
g
VDD
JD
j"D
U'~TRUE
~
vss
L~OUTPUT
I I
vss
Vss
VDO
,
d
]
Vss
0 COMPLEMENT
92CS- 20035
Fig. 1 - CD4041A schematic diagram.
571
CD4041A Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 753
MAXIMUM RATINGS, Absolute-Maximum Values:
Storage Temperature Range ••...••..
Operating Temperature Range:. . . . . • • .
DC Supply Voltage Range
{Vee - vssl ............
Device Dissipation (Per Pkg.) .•••••..
Average Dissipation Per Output. • . . . . •
Allowable Input Rise and Fall Time
VI Supply and Frequency .•.••••.
-6SOC to +150
-550C to +125
DC
DC
-0.5 V to +15
200
100
V
mW
mW
All Inputs ..................•....
Recommended
OCSupply Voltage {VOO- VSSI ..
VSS"VI"VOO
3t015
V
Recommended
VOO to Vss
Input Voltage Swing .••••..••••.
lead Temperature (During soldering):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mml
from case for 10 seconds max. . .
See Fig. 17
265
STATIC ELECTRICAL CHARACTERISTICS (All Input•... VSS::; VI::;' VOO) Recommended OC SupplV Voltage 3 to 15 V
CHARACTERISTIC
SYMBOL
Quiescent
Devi~
IL
Current
5
10
Inputs
to
Ground
Quiescent Device
Dissipation/Package
Po
_55°C
TEST CONDITIONS
Vo VDD
Volts Vol1S
5
10
or
VDD
Low-Level
5
10
15
VOL
rHigh·Level
Fan-out
of 50
COS/MOS
Inputs
3
5
10
VOH
VTHN
IO~-10,.A
VTHP
IO=10"A
Noise Immunity·
{Allinputsl
VNL
-
True
Output
VNH
Output Drive Current:
N·Channel
ION
Typ.
Max.
Min.
Max.
-
I
-
2-
-
0.005
0.005
2-
-
60
40-
IlA
5
-
0.025
0.05
5
20
-
300
400
IlW
0
0
0.500.Q1
0.Q1
0.05
V
20
0.550.Q1
0.Q1
-
-
-
4.99
9.99
4.99
5
-
4.95
-
10
-
9.95
14.45-
-
-
Comple·
lOP
-3.0·
-oJ'
0.7-
1.5
3.0-
0.3"
-
1.53-
2.25
-
-
4.5
-
1.53-
2.25
-
4.5
'-
1.4
2.9-
5
10
2.1
6.25"
1.65-
3.2
-
10
-
-
1".5
3-
-
1.2
3.5'
-
-
0.55
-
1.4
-
-
5
1
-
0.8-
1.6
2.5·'
-
2-
4
True
4.5
5
-1.75
-
-1.4- -2.8
-
-1
Output
9.5
10
-5"
-
-4-
-
-2.8··
-
Cample-
4.5
5
10
-0.75
-2.25'.
-
-0.6- -1.2
-1.8- -3.6
-
-0.4
-
-1.25:
-
9.5
10 IlA at any
Any Input
-
-8
1.5-
-
-
-
10
-
-
V
2
V
2
•
1.5-
1
V
-
-
V
-
10
input or output
II
-
!-1-
3.0-
1.4
2.9-
111
V
-3.0
0.5
Output
Diode Test
,
-0.7
0.5
ment
Input Current
-1.5
3.0··
Output
ment
P-Channel
-3.0·
0.7-
5
10
0.05
0.55-
9.99
14.40-
-0.7-
3.6
7.2
0.5
-
2.3-
2.25- :
1.5
3-
0.4
.-1-
0.50-
5
10
True
1
Min.
I
0.95
2.9
Output
Notes
Max.
15
N-Channel
UNITS
-
Threshold Voltage:
P-Channel
125°C
Min.
3
Output Voltage:
LIMITS
CD4041AO. CD4041AK
25°C
mA
-
mA
-
1.5
V
-
pA
3
Limits with black dot (e) designate'100% testing. Refer to RIC·102B "High-Reliabilitv COS/MOS CD4000A Slash (/) Series Types""Tables 2
through 7 for testing sequence. All other limits are designer's parameters under ~iven test conditions and do not represent 100% testing.
Note 1: Complete functional test, all inputs and outputs to truth table.
Note 2: Test is e.ither a one input or a one output only.
572
Note 3: Test on all inputs and outputs.
J;.
Values shown are for True Output.
File No. 753 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4041A Slash (/) Series
-10
-15
DRAIN-TO-SOURCE VOLTAGE (Vas I-V
92C5-22910
.
92C$-22909
Fig. 3- Minimum p-channel drain characteristics-true output.
Fig. 2- Minimum n-channel drain characteristics-true output.
50
e
~40
!:!
...
~
30
~
20
a
10
5
ORAIN-TO-SOURCE
DRAIN-lO-SOURCE VOLTAGE 1VOS1-V
92C5-22930
92C$-22.910
Fig. 4-Minimum n-channel drain characteristics-complement output.
Fig. 5- Minimum p-channel drain characreristics-complement output.
14
AMBIENT TEMPERATURE
ITA'- 2.5-C
15
12
>
~
l'J
~
0
...>
..."-
Voo; 5V
~o
12.5
10
10V
7.5
~
5V
~
0
3.5
2.5
10
12
INPUT VOLTAGE {VII-V
14
16
I.
2.5
7.5
10
12.5. 15
INPUT VOLTAGE (VII-V
17.5
20
92C5-20045
92CS-20044
Fig. 6- Minimum and maximum transfer characteristics-true output.
Fig. 7- Minimum and maximum transfer characreristicscomfJlement output.
573
CD4041A Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 753
DYNAMIC ELECTRICAL CHARACTERISTICS al TA = 25°C and CL = 15pF
Typical Temperature Coefficient for all values of V OD = o.3%fC
LIMITS
CHARACTERISTIC
SYMBOL
Propagation Delay Time:
High-to-Low Level
'PHL
TEST
CD4041AD.
CONDITIONS
CD4041AK
VDD
(VOII,I MIN. TYP. MAX.
True
5
Output
10
Complement
5
10
5
10
5
10
5
10
5
10
5
10
5
10
Output
True
LOW-To-High Level
'pLH
Output
Complement
Transition Time:
tTHL
High-to-Low Level
Output
True
Output
Complement
Output
True
tTLH
Low-to-High Level
Output
Complement
"put Capacitance
Output
Any Input
CI
-
-
-
65
40
55
30
75
45
45
25
20
13
40
25
20
13
35
25
5
115
75 •
100
45 •
125
75
100
40·
40
25 •
60
40·
40
25 •
55
40·
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
pF
limits with black dot (.j designate 100% testing. Refer to RIC-l02B "High-Reliability COS/MOS CD4000A Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1: Test is a one input one output only.
DYNAMIC ELECTRICAL CHARACTERISTICS (D'iving TTL,DTLI ATTA = 25°C, VDD-VSS=5V.CL = 15pF (T,ueOulput!
TEST CONDITIONS
CHARACTERISTIC
Driving
TTL.DTL
Propagation Delav Time:
AL = 2kfl
tpHL
High·To·low level
AL =20kfl
RL = 2kfl
low·To·High level
tpLH
AL = 20kfl
AL = 2kfl
'THL=
Transition Time
tTLH
AM~lENT ITEM~ERAT~RE
o
o
(TA) " 25°C
T I
0-
I
I
0
~
l'IDD'~\O"
\'II
D'S'!'"
~
~
I I0 I w
w
MIN. TYP. MAX.
-
75
150
-
75
150
-
85
175
-
85
175
-
20
50
20
50
n,
ns
ns
~
.~~ ,.-V
J,
'5U~~1j.
AL = 20kfl
Med.
Power
Low
Power
Med.
Power
Low
Power
Med.
Power
Low
Power
UNITS
.I~
~,l~/
..Jo\..."'i~
0
LIMITS
CD4041AD
CD4041AK
SYMBOL
- r:::
I--::
ro
ro
00
00
LOAD CAPACITANCE (CL)-PF
92CS-20046
Fig. 8- Typical transition time vs. CL-true output.
574
92CS-20047
Fig. 9- Typical high~to-Iow level transition time vs.
CL -complement output.
File No. 753 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4041A Slash (I) Series
0
0
0
0
0
J.
AMBIENT TEMPERATURE
(TA)= 25D C
--
1
I
p!J'Ij' ~
I
,0c,"G~'i-:--
I
I
k-:
supP\..~
~
~~
I--
l\l ol",\5\1
i0
'I
--
;::
I--
Bof--t-+--,
~ 60
l!l
I-
~40~-I--+
!i
20f---f=+--
C>
'I
I I
LOAD CAPACITANCE (CL)-PF
LOAD CAPACITANCE (CL)-PF
92C5-20049
92C5-20048
Fig. 10- Typicallow-ro-high level propagation delay time vs.
CL-true output.
Fig. 11- Typicallow-to-high level propagation delay time vs.
CL -complement output.
•
106
f+-
'FWt-t~QI
D,
fCONTROLCLOCK
-
-r: - - - ---l
0---1---";
CL
c"c
I
l'
I
I
I
I
I
I
~P
V
~_
I
• IIL ________
.-:___ -1
POLARITVO
,2CS-20110
CLOCK
POLARITY
a
0
0
0
,
-,
0
LATCH
,
0
J"
'-
LATCH
Fig. I - Logic block diagram and truth rable.
File No. 756---_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4042A Slash (/) Series
can be supplied to three screening levels - 1M. IN. and IR.
For a description of these screening levels and for detailed
information on
employed with
High·Reliability
MaS CD4000A
test methods, procedures, and test sequence
high·reliability COSIMOS devices refer to
Report RIC·l02C. "High·Reliability COS!
"Slash" (I) Series Types".
The C04042A "Slash" (I) Series types are supplied in 16·lead
welded·seal dual·in·line ceramic packages ("0" suffix). in the
16·lead ceramic flat packages ("K" suffix). or in chip form
("H" suffix).
STATIC ELECTRICAL CHARACTERISTICS (All Inputs ••• VSS ~ VI ~ VOO)
Recommended OC Supply Voltage 3 to 15 V
LIMITS
C04042AD, C04042AK
CHARACTERISTIC
SYMBOL
Vo VOO
Volts Volts
Quiescent Device
Current
IL
5
10
Inputs
to
Ground
Quiescent Device
Dissipation/Package
Po
Typ.
Max.
Min.
Max.
-
1
~
2"
-
0.005
0.005
2"
-
60
40·
5
20
-
0.025
5
-
300
0.05
20
-
400
-
0.05
0.05
VOO
10
-
3
Fan-out
Inputs
VOH
125 0 C
Min.
-
VOL
25 0 C
1
-
5
o! 50
COS/MOS
High-Level
Min. Max.
or
Output Voltage:
Low-Level
-SSoC
TEST CONOITIONS
-
om
-
a
-
/).01
-
0
am
om
VTHN
IO·-IO~A
VTHP
10 ·'0~A
Noise Immunity
(All Inputs)
VNL
VNH
Output Drive Current:
N-Channel
P-Channel
Diode Test
Input Current
1
~W
-
3
2.25"
5
4.99
-
4.99
5
10
9.99
-
9.99
14.50
10
V
0.55·
0.50·
-
4.95
-
9.95
14.45·
-
_0.7° _3.0·
f--.=-1
-0.30
-3.d'
V
3.0·
0.3 0
3.0·
V
2.25
-
4.5
-
1.4
2.9·
2.25
4.5
-
1.5
3.0··
0.7 0
1.5
1.5
3·
-
1.5 0
3"
1.4
2.9·
-
1.5°
0.95
5
2.9
10
3.6
7.2
5
10
0.5
5
0.5
-
0.40
1
0.5
10
1.25
-
1°
4.5
5
0.45
-
9.5
10
1.15
-
-
1
3"
V
-
0.27
-
rnA
2
-
0.7
-
rnA
-0.35
-1
-
-0.25
-
-
-O.gO
-2
-
-0.6
-
-
1.5-
-
-
-
-
-
10
ION
2
0
lOP
V OF
II
2
V
-
3·
r---=1
I-
_3.0·
_0.7° -1.5
0.7 0
e-!-
I-
e-!-
2.3"
15
N-Channel
~A
0.50·
0.55"
5
10
15
Threshold Voltage:
P-Channel
UNITS Notes
2
10 IlA at any
input or output
Any Input
1.5-
-
-
uP
-
-
3
pA
-
Limits with black dot (_I designate 100% testing. Refer to RIC-l02B "High-Reliability COS/MaS CD4000A Slash (II Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not r~present 100% testing.
Note 1: Complete functional test, all input~ and outputs to truth table.
Note 3: Test on all inputs and outputs.
Note 2: Test is e.ither a one input or a one output only.
For/Thrfihold Vo~tag(J Test qi,.,:uits. Operating and Biased Life Test Circuits, Output Drive Current Test Circuits, {and for Operating
'Considerations, see Appendix',
577
CD4042A Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 756
DYNAMIC ELECTRICAL CHARACTERISTICS atTA =25OC, Vss = OV, CL
=15pF, and input rise and fall times = 20 n.,
except t,CL and tfCL.
LIMITS
CHARACTERISTICS
TEST CONDITIONS
.--- CD4042AD. CD4042AK
SYMBOLS
VDD
(Volts)
Propagation Delay Ti me
Transition Time
Minimum Clock Pulse
Width
Clock
Rise & Fall Time
tPHl·
tPlH
tTHL,
tTlH
tWl.
tWH
5
10
trell
tlCl
5
10
5
10
5
10
5
10
Set-UpTime
C,
Input Capacitance
-
Min.
-
-
-
TVp·
Max.
150
300
125"
75
100
50
175
50
-
200
100"
250
75
15
25
5
NOTES
ns
1
ns
1
ns
-
~s
1
100
50
ns
-
-
pF
5"
50
UNITS
Limits with black dot 1-) designate 100% testing. Refer to RIC·l02B "High-Reliability COS/MOS CD4000A Slash {/) Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not repres'!nt 100% testing.
Note 1: Test is a one input. one output only.
MAXIMUM RATINGS.Ab....lur...Maximum Values:
Storage·Temperature Range . . . . . . . . . ..
Operating·Temperature Range·...........
DC Supply·Voltage Range:
(VDD -VSS)···············.·.··.
Device Dissipation (Per Package) ........ .
All Inputs
R~commend~d ...................... .
-65 to +150
-55 to +125
°c
0c
-0.5 to +15 V
200 mW
VSS::;V,::;VDD
DC Supply·Voltage (VDD - VSS) .... .
3to 15
V
Recommended
Input·Voltage Swing ................ VDD to VSS
Lead Temperature (During Soldering)
At distance 1/16" ± 1/32"
(1.59 ± 0.79 mm) from case
for 10 s max ..................... .
+265
AMBIENT TEMPERATURE (TA' " 25"C
TYPICAL TEMPERATURE COEFFICIENT FOR Ie
t
R
-0.3%
I·~t
15
ATE-TO'-SOURCE VOLTAGE IVGS';15V
1
12 . 5
8
~
DRAIN -TO-SOURCE VOLTAGE (Vosl-V
-15
-10
-5
AMBIENT TEMPERATURE ITA'" 25 "c
TYPICAL TEMPERATURE COEFFICIENT
FOR Io--0.3"1o/"C
SV
.
10V
10
- 5 E
7.5
~
I
z
~
a'"
~
z
z
GATE-TO-SOURCE VOLTAGE{VG '~15V
10V
~
2.5
5V
2.5
-15
7.5
10
12.5
15
ORA IN - TO - SOURCE VOLTAGE (VOS)
!J2CS-22848
Fig. 2- Min. n-channel drain characteristics.
578
92CS-2284T
Fig. 3- Min. p·channel drain characteristics.
File No. 756 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4042A Slash (/) Series
",0
~
105
~
104
~
:\.\~~
~
z 10'
s'"
0
i
Bi
~o..J.
\."~\012:
/'
~
'"'
., 10
~
I
Ii' 12'"
V ,V
10'
4
..
LOAD CAPACITANCE CL· 15 pF
CL-SOpF--:
,
4
•• 105 , • • •106 ,
-F
4 681
104
CLOCK FREQUENCY "ell-HI
92CS-20200
92CS-20192
Fig. 4- Typical propagation delay time vs. V DD-
.".
.1"
10'
c
6
8
/0
SUPPLY VOLTAGE (Vool-V
.~
.~~
Fig: 5- Typical dissipation characteristics.
10V
15
I.
13
12
A OOIlIOOJ TEST
B 0110111
C 0000001
SEQUENI
10
9
92CS-2019B
Fig. 6- Quiescent device current.
Fig. 7- NOise immunity.
579
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~------_,_-_,_-FileNo. 754
OO(]5LJD
Solid State
Division·
High-Reliability COS/MOS
Quad 3-State RIS Latches
v~
" v---r,---,----,
.,
·2
S,
0,
0,
.,
0,
ENABLE
For Logic Systems Applications in Aerospace,
Military, and Critical Industrial Equipment
02
.,
s,
Monolithic Silicon
High-Reliability Slash(/) Series
CD4043A/..•, CD4044A/..•
C04043A TERMINAL DIAGRAM
'2
Digital Integrated Circuits
Quad NOR R/S Latch - CD4043A
Quad NAND R/S Latch - CD4044A
Special Features:
Applications:
• Medium Speed Operation
• 3-Level Outputs with Common
Output Enable
• Separate Set and Reset Inputs
for Each Latch
• Low Power TTL Compatible
• NOR and NAND Configurations
• Holding Register in MultiRegister System
• Four Bits of Independent
Storage with Output Enable
• Strobed Register
• General Digital Logic
RCA-CD4043A and CD4044A "Slash" (f) Series are highreliability COS/MOS integrated circuit Quad 3·State RIS
Latches intended for a wide variety of logic function configurations in aerospace, military, and critical industrial
equipment. The CD4043A types are quad cross-coupled 3-State
NOR latches; the CD4044A types, quad cross-coupled 3-State
NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are gated through
transmission gates controlled by a common ENABLE input. A
logic "1" or "high" on the ENABLE input connects the latch
states to the Q outputs. A logic "0" or "low" on the ENABLE
input disconnects the latch states from the,Q outputs, resulting
in an open circuit condition on the Q outputs. The open circuit
feature allows common busing of the outputs. The logic operation of the latches is summarized in the truth table on the
following page.
For a description of these screening levels and for detailed
information an lest methods. procedures, and test sequence
emploved with high-reliabilitv COSIMOS devices refer to
High·Reliabilitv Report RIC·l02C, "High-Reliabilitv COSI
MOS CD4000A "Slash" (Ii Series Types".
The CD4043A and CD4044A "Slash" (I) Series types are
supplied in 16-lead dual·i.n-line ceramic packages ("D" suffix),
in 16-lead ceramic flat packages (UK" suffix), or in chip form
("H" suffix).
MAXIMUM RATINGS,Absolute-Maximum Values:
Storage-Temperature Range . . . . . . . . . ..
Operating-Temperature Range· ...........
DC Supply·Voltage Range:
(VDD - VSS) .................... .
These devices are electrically and mechanically identical with Device Dissipation (Per Package) ........ .
standard COS/MOS CD4043A and CD4044A types described Allinputs ......................... .
in data bulletin 590 and DATABOOK SSD-203B Series, but
are specially processed and tested to meet the electrical, Recommended
DC Supply-Voltage (VDD - VSS) .....
mechanical, and environmental test methods and procedures
Recommended
established for microelectronic devices in MI L-STD-883.
Input-Voltage Swing ................
Lead Temperature (During Soldering)
The packaged types can be supplied to six screening levels At distance 1/16"± 1/32"
lIN, /1R, /1, 12, 13, f4 - which correspond to MIL·STD·.883
(1.59 ± 0.79 mm) from case
Classes "A", "B", and "c", The chip versions of these types
for 10 s max. . ................... .
can be supplied to three screening levels - 1M, IN, and fR.
-65 to +150
-55 to +125
°c
°c
-0.5 to +15 V
200
mW
VSS:S VI:S VDD
3 to 15
V
VDD to VSS
+265
°c
9-74
580
File No. 754 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4043A, CD4044A Slash (/) Series
STATIC ELECTRICAL CHARACTERISTICS
(All Inputs . .. VSS ~ VI::;' VDD) Recommended DC Supply
Voltage 3 to 15 V
LIMITS
C04043AO, C04043AK, C04044AO. C04044AK
CHARACTERISTIC
SYMBOL
TEST CONOITIO,.N_S_-+__-_5_5rOC
_ _+-_ _..-2_5_0.oC..-_ _+-_1_25_0TC_ _ luNITS Notes
VOO
Volts
Quiescent Device
Current
I--------+----i
Quiescent Device
DiSSipation/Package
Min.
5
10
Inputs
to
Ground
or
VOO
5
10
Output Voltage:
. Low-Level
Fan-out
1--------+---1 ~~~~MOS
Inputs
3
5
10
15
Max.
Min.
Typ.
Max.
2"
0.005
0.005
2"
20
0.025
0.05
5
20
Max.
60
40"
"A
300
400
0.5"
0.55"
0.01
0.01
o
o
0.01
0.01
0.05
0.05
0.5-
3
2.25"
4.99
2.3"
4.99
10
15
9.99
9.99
High-Level
Min.
v
0.55-
4.95
9.95
14.45"
10
v
Threshold Voltage:
-0.7" -3.0"
N-Channel
0.7"
P-Channel
Va'" 0.95 V
Noise Immunity
(All Inputs)
V O ""2.9V
10
Va = 3.6 V
5
V O -7.2V
Output Drive Current:
N-Channel
ION
-0.7" -1.5
0.7"
1.5
1.5
loS"
2.25
3"
3"
4.5
-3.0"
3.0"
-0.3" -3.0"
0.3"
V
1.4
1.4
loS"
2.25
2.9"
3"
4.5
1.5
3"
0.25
0.2 0
0.5
0.14
V
V
mA
V O =4.5V
0.61
-0.22
10
-0.5
-0.175- -0.5
-0.12
-0.4-
-1
mA
V
input or output
Any Input
Input Current
2
-0.28
100 IJ.A at any
Diode Test
2
0.35
r------+---+--+--+---+--r---+---+--4
V o ""9,5V
V
3.0
V O "'O.5V
10
P-Channel
3.0"
10
3
pA
Limits with black dot ,_) designate 100% testing. Refer to RIC-1D28 "High-Reliability COS/MOS CD4000A Slash (II Senes Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1: Complete functional test, all inputs and outputs to truth table.
Note 2: Test is e.ither a one input or a one output only.
Note 3: Test on all inputs and outputs.
Voo
5VORIOV
lOY
3.5VOR7V
I.
TEST PERFORMED WITH THE
FOLLOWING SEQUENCE
OF"I'S" AND "o's"
13
12
"
10
9
10
1.5VOR 3V
92C5-20202
92C5- 20203RI
Fig. I-Ouiescentcurrent.
Fig. 2- Noise immunity.
581
CD4043A, CD4044A Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 754
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 250 C. VSS = OV. CL = 15pF, and input rise and fall times = 20 ns,
except trCL and tfCL.
LIMITS
CHARACTERISTICS
SYMBOLS
TEST CONDITIONS
.--
CD4043AD,CD4043AK
CD4044AD,CD4044AK
VDD
IVoltsl
Propagation Delay Time
Transition Time
Min.
Typ.
Max.
175
350
tTHL,
5
-
tTLH
10
-
50
-
80
200
40
100·
tPHL,
5
tPLH
10
Minimum Set and Reset
tWHISl,
5
Pulse Width
Input Capacitance
tWHIRI
C,
10
-
UNITS
NOTES
ns
1
ns
1
ns
,
pF
-
175·
75
100
200
100·
-
5
Limits with black dot (e) designate 100% testing. Refer to RIC~102B "High·Reliability COS/MOS CD4000A Slash (I) Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1: Test is
o~e
input or a one output onlV.
CD4044A-NAND
r ONEOFFOURlATCH~l
I
E
I
"
5
5
E~~
•
E~~
•
R E
x x
o 0
'0
0'
"
·OPEN CIRCUIT
R E
x x
DC·
NC+
I
I
0
I
0'
'0
o 0
~
DC·
NC+
I
0
46
*OPEN CIRCUIT
+ NO CHANGE
611 DOMINATED BY R=O INPUT
,. NO CHANGE
l:t. DOMINATED BY S" I INPUT
CD4044A Terminal Diagram
92C$-20ZIi!:
92C5-20ZI1
Fig. 3-Logic diagrams & truth tables.
J~
}-Ja-o.
9T
'"
'"
nn:J'" d'"
...~1JJ-,
Vss
~-~
Vss
'l.:rcS"OJ'"
Fig. 5-Schematic diagram·CD4044A.
582
File No. 754 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4043A, CD4044A Slash (I) Series
ORAIN-TO-SOURCE VOLTAGE
(Vosl-V
4
e
I
....'"
z
a
z
~
92CS-22932
92CS-229ll
Fig.7-Min. p-channel drain characteristics.
Fig.6-Min. n-channel drain characteristics.
AMBIENT TEMPERATURE ITA)o2S0C
TYPICAL TEMPERATURE COEFFICIENT
FOR 100 0.3 % J·e
~25
.
;200
~
,. 150
:
.
z 100
~
15 V
~
z
~ 50
LOAD CAPACITANCE ICL)-pF
LOAD CAPACITANCE ICL)-pF
92.CS-ZOZI9
92CS-20220
Fig.9-Typ. trans/stion time VI. CL-
Flg.8-Typ. propagation delay time vs. CL-
.,
~
I
106 AMBIENT TEMPERATURE ITAI-25°C
?... 10'
~
,.\'>~
10'
suv~
~o
~~,,~
10'
~
10'
LOAD CAPACITANCE
0
.,...'"
~
~
.,,~
0
~
~~~
,...;. '>~
10
CL o l5pF
CL· 50 pF
I
104
lOS
OUTPUT FREQUENCY-Hz
10·
92CS·20Z01
Fig. 10- Typ. dissipation characteristics.
583
File No. 755
D\l(]3LJD
Solid State
Division
Digital Integrated Circuits
Monolithic Silicon
High-Reliability Slash(/) Series
CD4045A/...
High-Reliability COSIMOS
21-Stage Counter
For Logic Systems Applications in Aerospace,
Military, and Critical Industrial Equipment
Applications:
+
VDD)
Vss
I.
4, S,6.9.IO,II.12.13NO CONNECTION
• Digital equipment in which ultra· low dissipation and/or
operation using a battery source are primary design requirements.
• Accurate timing from a crystal oscillator for timing applications
such as wall clocks, table clocks, automobile clocks, and digital
timing references in any circuit requiring accurately timed outputs
at various intervals in the counting sequence.
• Driving miniature synchronous motors, stepping motors, or
external bipolar transistors in push·pull fashion.
RCA C04045A "Slash" (I) S~ries types are high·reliability
COS/MOS integrated circuit 21·Stage Counters intended for a
wide variety of logic function configurations in aerospace,
military, and critical industrial equipment. The C04045A is a
timing circuit consisting of 21 counter stages: two ou~put
shaping flip-flops, two inverter output drivers, three 5.5 V
zener diodes (providing transient protection at 16.5 V), and
input inverters for use in a crystal oscillator. This device may be
operated over a 3·to·15 V supply voltage range. The CD4045A
configuration provides 21 flip·flop counting stages, and two
flip·flops for shaping the output waveform for a 3.125% duty
cycle. Push·pull operation is provided by the inverter output
drivers.
The first inverter is intended for use as a crystal oscillator/
amplifier. How~ver, it may be used as a 'normal logic inverter
if desired.
Features:
• Operation from 3 to 15 volts
• Microwatt quiescent dissipation ...
2.51lW (typ.) @ VDD = 5 V; 10llW (typ.)
@
VOO = 10 V
• Very·low operating dissipation ...
1 mW (typ.);@VDD=5V,f(b = 1 MHz
• Output drivers with sink or source capability ...
7 rnA (typ.) @ Vo = 0.5 V, VDD = 5 V (sink)
5 mA (typ.) @VO=4.5V, VDD = 5 V (source)
• Medium speed (typ.) ... f(b = 5 MHz
@
VDO = 5 V
f(b = 10 MHz
@
VDD = 10 V
• 16.5 V zener diode transient protection
on chip for automotive use
The packaged types can be supplied to six screening levels A crystal oscillator circuit can be made less sensitive to voltage I1N, I1R, 11, 12, 13, 14 - which correspond to MIL-STD-883
supply variations by the use of source resistors. In this device, Classes "A", "B", and "C". The chip versions of these types
the sources of the p and n transistors have been brought out to can be supplied to three screening levels -1M. IN. and IR.
package terminals. If external resistors are not required, the
For a description of these screening levels and for detailed
sources must be shorted to their respective substrates
information on test methods, procedures, and test sequence
(Sp to V DO ' SN to VSS ). See Fig. 1.
employed with high·reliability COS/MOS devices refer to
These devices are electrically and mechanically identical with High·Reliability Report RIC-l02C, "High·Reliability COS/
standard COS/MOS CD4045A types described in data bulletin MOS CD4000A "Slash" (I) Series Types".
614 and DATABOOK SSO·203 Series, but are specially
processed and tested to meet the electrical, mechanical, and The C04045A "Slash" (I) Series types are supplied in 16-lead
environmental test methods and procedures established for dual·in·line ceramic packages ("0" suffix), in 16·lead ceramic
flat packages ("K" suffix), or in chip form "("H" suffix).
microelectronic devices in MI L·STO·883.
9·74
584
CD4045A Slash (I) Series
File No. 755
REFER TO APPLICATION
r-
NOTES leAN 6086
I OR
T~~ CJ~~I~E6503F9
I
FOR
g5~~~LN~~Ot VALUES
L--.I>j-(}---,
AND TYPICAL OSCILLATOR
CURRENTS
2.097152
MH,
=
.~.",~."
J
'I
t
I
14"_'_'
~
-_.
-
{
4>
16
1021110
I"'".[RTER
'~~\I
J
.,
"
L
EXTERNAL
--.J
,JLJLJL
~
;. 1/]25[C
IIZSEC~
~
J+~~
SCtlE"'ATlCOF
COMPONENTS
FIRSTINV[RTEIl
Fig, 1- CD4045A and outboard components in a
typical21~stage
counter application.
MAXIMUM RATINGS. Absolute·Maximum Values:
Storage·Temperature Range
Operating-Temperature Range:
Ceramic packages .............. .
Plastic package ................ .
-65 to +150 °C
-55°C to + 125°C
-40°C to +85 0 C
AMBIENT TEMPERATURE ITA l-Z5-C
DC Supply·Voltage Range:
(VDD - VSSI .......... .
Device Dissipation:
(Per package, including zener diodes)
All Inputs
Recommended
DC Supply·Voltage (VDD - VSSI
-0.5to+15
V
200mW
VSS:':::VI:':::VDD
3 to 15
V
Recommended
Input-Voltage Swing
Peak Zener Diode Current
(Decay T = 80 msl ............. .
VDD to VSS
150mA
Note 1: To minimize power dissipation in the zener diodes. and to
ensure device dissipation less than 200 mW. a 150 !Z current-limiting resistor must be placed in series with the
power supply for VOO
> 13 V.
Noto 2: Observe power supplV
terminal No.3 and VSS
terminal connections. VOO is
terminal No. 14 fnot 16 and 8
10'
10 4
10 5
10 6
INPUT FREQUENCY (f,)-Hz
10 7
10 8
92CS-22938
Fig. 2- Typical dissipation VI. input f;equency
(21 counting stages).
IS
respectively. as in all other CD4000A Series 16-lead devices I.
585
CD4045A Slash (/) Series
File No. 755
STATIC ELECTRICAL CHARACTERISTICS (All Inputs ••• VSS ~ VI:::;' VOOI
Recommended OC Supply Voltage 3 to 15 V
LIMITS
CHARACTERISTIC
SYMBOL
TEST CONDITIONS
Vo
V DD
Volts Volts
Min.
IL
Current
Quiescent Device"
Dissipation/Package
Po
-
0.075
10
VOL
0.25
0.55-
25"
5
10
COS/MOS
0.25
0.50.01
0.01
a
0.01
9.99
Max.
9.99
500·
-
4.5
~
0.05
9.95
10
-0.3- -3" -0.3' -1.5
-2.S- -0.3-
-2.~
0.3-
2.S-
2.8 •
Sum
VTHS
10
2.9-
Output Drive
1.4
V NH
N·Channel
4.4
0.5
Cur~ent
'ON
0.5
10
P·Channel
lOP
9.5
6.9
3.1
4.5
10
.. 5.6
2.25
1.4
3"
4.5
2.9·
1.5-
2.25
1.5
3"
4.5
V
3 "
2.5
3.5 •
5.5-
11
3.9
'-2.5-
-5
-1.8
·-4.5- -9
-3.2
mA
mA
pA
10
"
V OF
1.5-
1.5-
100 IJA at each input or output
V
3.7
1.5 •
Input Current
Diode Test
0.3-
3.6
3.7
Noise Immunity
(Any Input)
1.5
-
---T-
14,45
'0-10"A
3 "
1
~
V
'0" -10"A
0.3-
-=-
-
0.55-
VTHP
1.5
V
0.05
-
VTHN
10
mW
-
P·Channel
V NL
"A
4.95
14.5-
3"
S
2.34.99
15
Threshold Voltage:
N·Channel
0.01
a
-
T
900
25"
0.075
0.01
4.99
10
15
0.50·
2.25-
V OH
Max. Min.
0.0025
15
Driving
High-Level
Typ.
0.5
-
10
Output Voltage
Low· Level
Max. Min.
15
Quiescent Device.
0
1250C
250 C
-55 0 C
N
UNITS
CD4045AD,CD4045AK
1.5-
V
18.2
V
3
Zener Breakdown
Voltage
V(BR)Z
,
<
100 "A
13.3
17.8
13.5
16.5
18
13.7
Limits with black dot (e) designate 100% testing. Refer to RIC·1028 "High·Reliability COS/MOS CD4000A/Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
586
Note 1: Complete functional test, all inputs and outputs to truth table.
Note 2: Test is either a one input or a one output only.
Note 3: Test on all inputs and outputs.
4Maximum noise·free saturated Bipolar output voltage.
tMinimum noise·free saturated Bipolar output voltage.
File No. 755 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4045A Slash U) Series
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C. CL = 15 pF. and input rise and fall times = 20 ns. except t,4> and t{4l.
Typical Temperature Coefficient for all values of VDD = 0.3%/oC
LIMITS
CHARACTERISTIC
TEST
CONDITIONS
VDD
(Volts)
SYMBOL
Propagation Delay Time
tpHL'
5
'111 to y or y+d out
tpLH
10
Transition Time
2.2
4.4
1.2
2.4
-
450
800
375
650
100
115
50
60
-
15
-
10
tr'll.
5
-
t{4l
10
-
f'll
3
50·
fm'll
5
4.4
5
-
fm'll
10
8.5
10
-
15
2-
-
-
5
10
f'll
Input fapacitance
-
5
tWH
Frequency
Max.
10
tWL.
Maximum Input·Pulse
Typ.
tTLH
Pulse Width
Rise & Fall Time
Min.
tTHL'
Minimum Input·
Input Pulse
C04045AD.CD4045AK
Any Input
CI
-
-
5
UNITS
N
0
T
E
S
p.s
-
ns
-
ns
-
p.s
-
kHz
1
MHz
-
MHz
1
pF
-
Limits with black dot (.) designate 100% testing. Refer to RIC·102B "High-Reliability COS/MOS CD40COA Slash (f) Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1: Complete functional tests, all inputs/outputs to truth table.
DRAIN TO SOURCE VOLTAGE (VosI-V
DRAIN TO SOURCE VOLTAGE IVos)-V
92CS-22911
Fig. 3-Minimum n-channel drain characteristics.
Fig. 4-Min;mum
p~hannel
drain characteristics.
587
CD4045A Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 755
10
15
20
IVzl-V
~CS-20900
Fig. 5 - Typical zener diode characteristics.
~UPPLY VOLTAGE (Vool-V
92C5-2091515
Fig. 6 - Tvpical propagation delay
(4), to y or y+d out) VSo VDO
LOAD CAPACITANCE ICL1- pF
Fig. 7 - Typical transition time
VI.
SUPPLY VOLTAGE IVDDI-Y
92C5-20902
CLo
92C5-20903
Fig. 8 - Minimum f mtP vs. VOD
TEST CIRCUITS
92C5-22894
92C5-20904
Fig. 9 - Quiescent current.
588
Fig. 10 - Noise immunity.
File No. 752 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
[IlOBLJD
Digital Integrated Circuits
Monolithic Silicon
Solid State
Division
PHASE
PULSES
I.
I OUT
veo
OUT
INHIBIT
TOP
5
I.
VOO
14
SIGNAL IN
13
PHASE CaMP
II OUT
..
PHASE COMP
COMPARATOR
IN
CD4046A/...
VIEW 12
CHII
ZENER
R2 TO Vss
RI TO Vss
High-Reliability COSIMOS
Micropower Phase-Locked Loop
For Logic Systems Applications in Aerospace,
Military, and Critical Industrial Equipment
Features:
Very low power consumption ...... 70 I1W (typ.) at VCO fo = 10 kHz, VOO =5 V
Operating frequency range ............... up to 1.2 MHz (typ.) at VOO = 10 V
Wide supply·voltage range ......................... VOO - VSS = 5 to 15 V
TERMINAL ASSIGNMENT
low frequency drift ......................
0.06%/"C (typ.) at VOO = 10 V
Choice of two phase ................ 1. Exclusive-OR network
comparators
2. Edge·controlled memory network with
phase·pulse output for lock indication
• High VCO linearity ..............•.......................... 1% (typ.)
RCA-C04046A "Slash" (I) Series are high·reliability COS/MOS
integrated circuit Phase· Locked Loops intended for a wide
a VCO inhibit control for ON·OFF keying and ultra·low
C1(2)
Vss
10
DEMODULATOR
OUT
veo
IN
•
•
a
•
•
variety of logic function configurations in aerospace, military,
and critical industrial equipment.
These devices are electrically and mechanically identical with
standard COS/MOS C04046A types described in data bulletin
637 and OATABOOK SSO·203 Series, but are specially
processed and tested to meet the electrical, mechanical, and
environmental test methods and procedures established for
microelectronic devices in MIL·STO·883.
The packaged types can be supplied to six screening levels 11N. 11R. 11. 12. 13, 14 - which correspond to MIL·STO·883
Classes "A", "B", and "C". The chip versions of these types
can be supplied to three screening leveI5'- 1M, IN, and IR.
standby power consumption
• Zener diode to assist supply regulation
• Source·follower output of VCO control input (Oemod.
output)
Applications:
01 FM demodulator and modulator
• Frequency synthesis and multiplication
II Tone decoding
• Frequency discriminator
• Data synchronization
01 FSK - Modems
01 Voltage·to·frequency conversion
.. Signal conditioning
a (See companion application note ICAN·6101 for application
information and circuit details)
For a description of these screening levels and for detailed
information on test methods, procedures, and test sequence
employed with high·reliability COS/MaS devices refer to
High·Reliability Report RIC·702C, "High· Reliability COS/
MaS CD4000A "Slash" (/) Series Types".
PHASE COMP. lOUT
2
The C04046A "Slash" (I) Series types are supplied in 16·lead
dual·in·line ceramic packages ("0" suffix). in 16·lead ceramic
flat packages ("K" suffix), or in chip form ("H" suffix).
The RCA·C04046A COS/MOS Micropower Phase· Locked Loop
(PPL) consists of a low·power, linear voltage·controlled oscil·
lator (VCO) and two different phase comparators having a
R'
CI
92CS-20006
Fig. 1 - COS/MOS phase-Jocked loop block diagram.
9·74
589
CD4046A Slash (/) Series _ _ _ _ _- - - - - - - - - - - - - - - - - - File No. 752
common signal·input amplifier and a common comparator in-
put. A 5.2·V zener diode is provided for supply regulation if
necessary. The CD4046A is supplied in a 16·lead dual·in·line
ceramic package (CD4046ADI. It is also available in chip
form (CD4046AH).
veo
One characteristic of this type of phase comparator is that it
may lock onto input frequencies that are close to harmonics of
the veo center-frequency. A second characteristic is that the
phase angle between the signal and the comparator input varies
between 0 0 and 1800 , and is 900 at the center frequency. Fig. 2
shows the typical, triangular, phase·to·output response charac·
; tz
Section
>
I
The VCO requires one external capacitor CI and one or two
external resistors (RI or RI and R2). Resistor Rl and capaci·
tor CI determine the frequency range of the VCO and resistor
R2 enables the VCO to have a frequency offset if required.
The high input impedance (10 12u) of the VCO simplifies the
design of low·pass filters by permitting the designer a wide
g
Voo
~
g
VOO/2
w
~
choice of resistor-ta-capacitor ratios. In order not to load the
low·pass filter, a source·follower output of the VCO input
voltage is provided at terminal 10 (DEMOOULATED OUT·
PUT). If this terminal is used, a load resistor (RS) of 10 kU or
more should be connected from this terminal to VSS' If
unused this terminal should be left open. The VCO can be
connected either directly or through frequency dividers to the
comparator input of the phase comparators. A full COS/MOS
logic swing is available at the output of the VCO and allows
direct coupling to COS/MOS frequency dividers such as the
RCA·CD4024A,CD4018A, CD4020A,CD4022A, or CD4029A.
One or more CD4018A (Presettable Divide·by·N Counter) or
C04029A (Presettable Up/Oown Counter), together with the
C04046A (Phase· Locked Loop) can be used to build a micro·
power low·frequency synthesizer. A logic 0 on the INHIBIT
input "enables" the VCO and the source follower, while a logic
1 "turns off" both to minimize stand-by power consumption.
VOLTAGE
I-:
~
0
90 0
1B00
SIGNAL-TO- COMPARATOR
INPUTS PHASE DIFFERENCE
92CS-20009
Fig.2 - Phase-comparator I characteristics
at low--pass filter output.
teristic of phase'comparator I. Typical waveforms for a COS/
MOS phase·locked·loop employing phase comparator I in
locked condition of fa is shown in Fig. 3.
Phase· comparator II is an edge-controlled digital memory net·
work. It consists of four flip·flop stages, control gating, and a
three-state output circuit comprising p- and n-type drivers having a common output node. When the p·MOS or n·MOS
drivers are ON they pull the output up to VOO or down to
VSS, respectively. This type of phase comparator acts only on
the positive edges of the signal and comparator inputs. The
Phase Comparators
The phase'comparator signal input (terminal 14) can be direct·
coupled provided the signal swing is within COS/MOS logic
levels [logic "0" .. 30% (VOO-VSS), logic "I" ;;. 70%
(VOO-VSS)]. For smaller swings the signal must be capaci·
tively coupled to the self·biasing amplifier at the signal input.
Phase comparator I is an exclusive·OR network; it operates
analagously to an over-driven balanced mixer. To maximize
the lock range, the signal· and comparator·input frequencies
must have a 50% duty cycle. With no signal or noise on the
signal input, this phase comparator has an average output
voltage equal to VOO/2. The low·pass filter connected to the
output of phase comparator I supplies the averaged voltage to
the VCO input, and causes the VCO to oscillate at the center
frequency (fa).
The frequency range of input signals on which the PLL will
lock if it was initially out of lock is defined as the frequency
capture range (2f d.
The frequency range of input signals on which the loop will
stay locked if it was initially in lock is defined as the frequency
lock range (2fL). The capture range is .. the lock range.
With phase comparator I the range of frequencies over which
the PLL can acquire lock (capture range) is dependent on the
low·pass·filter characteristics, and can be made as large as the
lock range. Phase·comparator I enables a PLL system to remain
in lock in spite of high amounts of noise in the input signal.
590
SIGNAL INPUT ITERM.141
VCO OUTPUT (TERM 41 =
COMPARATOR INPUT
(TERM 3)
PHASE COMPARATOR I
OUTPUT tTERM. 2)
veo
INPUT (TERM. 9)"
LOW-PASS FILTER
OUTPUT
~-VDD
~
-vSS
92CS-20010RI
Fig.3 - Typical wavelorms lor COS/MOS phase-locked loop em·
ploying phase comparator I in locked condition 0"0.
duty cycles of the signal and comparator inputs are not im·
portant since positive transitions control the PLL system utilizing this type of comparator. If the signal·input frequency is
higher than the comparator·input frequency, the p·type out·
put driver is maintained ON continuously. If the signal·input
frequency is lower than the comparator·input frequency, the
n·type output driver is maintained ON cOntinuously. If the
signal· and comparator·input frequencies are the same, but the
signal input lags the comparator input in phase. the n-type output driver is maintained ON for a time corresponding to the
phase difference. If the signal· and comparator·input frequen·
cies are the same, but the comparator input lags the signal in
phase, the p·type output driver is maintained ON for a time
corresponding to the phase difference. Subsequently, the capa·
citor voltage of the low·pass filter connected to this phase
comparator is adjusted until the signal and comparator inputs
File No. 752 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~_ _ _ _ _ CD4046A Slash (I) Series
are equal in both phase and frequency. At this stable point
both II" and n-type output drivers remain OFF and thus the
phase comparator output becomes an open circuit and holds
the voltage on the capacitor of the low-pass filter constant.
Moreover the signal at the "phase pulses" output is a high level
which can be used for indicating a locked condition. Thus,
for phase comparator II, no phase difference exists between
signal and comparator input over the full VCO frequency
range. Moreover, the power dissipation due to the low-pass
filter is reduced when this type of phase comparator is used
because both the p- and n-type output drivers are OFF for most
of the signal input cycle. It should be noted that the PLL lock
range for this type of phase comparator is equal to the capture
range, independent of the low-pass filter. With no signal
present at the signal input, the VCO is adjusted to its lowest
trequency for phase comparator II. Fig. 4 shows typical wave-
forms for a COS/MOS PLL employing phase comparator II in
a locked condition.
SIGNAL INPUT (TERM. 141
yeo
OUTPUT ITERM 41-
COMPARATOR INPUT
(TERW3)
PHASE COMPARATOR
OUTPUT (TERM. 131
n
--!l- -"._=~~~
_JI- - - +- - - -
U-----YOD
ZZ
yeo
INPUT (TERM. 91:
• LOW-PASS FILTER
OUTPUT
PHASE PULSE (TERM. II
-Vss
~::~:
92CS-2001lRI
NOTE: DASHED LINE IS AN OPEN-CIRCUIT CONDITION
FigA - Typical waveforms for COS/MOS phase-locked loop employing phase comparator II in locked condition.
MAXIMUM RATINGS, Absolute-Maximum Values:
Storage Temperature Range
-650 C to +150 °C
Operating Temperature Range:
Ceramic Package Types
-550 C to +125 °c
DC Supply Voltage Range
(VDD - VSS)
-0.5 V to +15
Device Dissipation (Per Pkg.l
All Inputs
200
mW
VSS";VI";VOO
Lead Temperature (During soldering):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm)
from case for 10 seconds max.
265
V
°C
4
10
6 8 102
92CS-21886
Fig.S (a) - Typical VCD power dissipation
at center frequencV"$ RI.
F----=.....;::~-k------"",,;::;~
~-----+------=~
4
10
6 8
4
10 2
so p-
1,,_
50 pF
1,,_
4
6 8 103
10
6 8
1o
4
;!:
Rs-
R2-Kn
92C5-21887
6
8 103
Kn
4
6'
92CS-21888
Fig. 5(c) Tvpical source follower power dissipation vs. RS-
Fig.5 fbI - Typical VCO power dissipation
at f min
V$
R2.
NOTE: To obtain approximate total power dissipation of PLL system for no-signal input
Po (Totan • Po (1 0 1 + Po (IMINI + Po (RSI - Pha,' Comparator I
Po (Totan
2
Po (fMINI - Pha .. Comparator II
591
CD4046A Slash (/) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 752
10 kn.;; Rl. R2. RS .;; 1 Mn
Cl ~ 100 pF at VDD ~ 5 V;
Cl ~ 50 pF at VDD ~ 10 V
In addition to the given design information refer to Fig. 5
for Rl. R2. and Cl component selections.
DESIGN INFORMATION
This information is a guide for approximating the values of
external components for the CD4046A in a Phase-lockedloop system. The selected external components must be
within the following ranges:
USING PHASE COMPARATOR II
USING PHASE COMPARATOR I
CHARACTERISTICI'
yeo WITHOUT OFFSET
Rz-
RZ- -
t1L E
'MAX
-I----
-
fa
VCO Frequency
yeo WITHOUT OFFSET
YCO WITH OFFSET
--
'MIN
12ft
2fL
Voo
Voo/2
veo
veo
INPUT VOLTAGE
-
rL
'MAX
----
fMN
--I-
2fl
If MIN
VOO/2
Voo/2
Voo
veo INPUT VOLTAGE
INPUT VOLTAGE
2fL
I
I
I
VDD
VDoI2
l~[
to
I
'MIN
YCO WITH OFFSET
00
veo
Voo
INPUT VOLTAGE
92CS-ZOOI2~'
For
No Signal
1nput
2 fL '" full
Frequency Lock Aange,2fL
Frequency Capture
Range, 2f c
Loop Filter
Component
Selection
Phase Angle between
Signal and Comparator
2 fL
IN
R'
OUT
IN
t
R'
veo frequency
1~
2'C"'- - "
11
'e' 'L
For 2 fe.see Ref. (2)
~C2
92CS-2'901
at center frequency (fa), approximating 0 0 and
1800 at ends of lock range (2fL)
goO
Always OD in lock
No
Ves
Low
High
- Given: fa
- Use fa with Fig.5a to
determine R1 and C1
- Given: fa and fL
- Calculate f mi n from
the equation
fmin = fa - fL
- Use fmin with Fig. 5b
to determine A2 and C1
f max
- Calculate fmin
- Given: f max
- Calculate fa from
the equation
f max
fa =-2-
- Given: 1min & fmax
- Use fmin with Fig.5b
to determine R2andC1
f max
- Calculate fmin
- Use fa with Fig.5a to
determine R1 and C1
f max
- Use fmin with Fig.5c
from the equation
f max 'o+'L
-=-fmin fa -fL
f max
- Use fmin with
Fig.5c to determine
ratio R2/R 1 to obtain
Rl
For further information, see
(1) F. Gardner,"Phase-Lock Techniques", John Wiley and Sons, New York, 1966
(2) G. S. Moschytz, "Miniaturized RC Filters Using Phase-Locked Loop", BSTJ, May, 1965.
592
range
fmax-fmin
OUT
Signal Input Noise
Rejection
Component
Selection
c
11),121
=F
Locks on Harmonics of
Center Frequency
veo
veo in PLL system will adjust
to lowest operating frequency, fmin
veo in PLL system will adjust to center frequencY,f o
to determine
ratio R2/R1 to
obtain R1
File No. 752 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4046A Slash (/) Series
ELECTRICAL CHARACTERISTICS AT TA = 25°C
LIMITS
CHARACTERISTIC
TEST
CONDITIONS
SYMBOL
CD4046AD. CD4046AK
Vo
Voo
VOLTS
VOLTS
MIN.
TYP.
I
UNITS
MAX.
CHARAC
TERISTIC
CURVES
Be TEST
CIRCUITS
FIG,NO.
VCOSection
Operating Supply Voltage
PD
R2"
VCO'N"-2-
RI '" 10kn
M8ICimum Operating Frequencv
'MAX
A2=00
veD,N
Center Frequency and
Ie, "00 of
'0
'5
0.25
0.5
0.6
'.2
1.5
Programmable with external components RI, R2, and
Sa
MH,
Se.
Design
10
'MAX-
Frequency Range
=
'5
>Ief =50pf
Voo
,u;
600
2400
'0
VOD
00
V
70
R, =1 Mn
'0= 10kHz
Operating Power
Dissipation
'5
'5
As fixed oscillator only
Phase-lock-loop operation
VOO-VSS
C,
Info.
'MIN
veolN = 2.5 V ±O.3 V. AI >10
kn
=5V+2.5V,Rl >400kn
Linearity
""7.5V !5V,Rl = 1 Mn
Temperature·Frequency Stability:
%
'0
'5
%/occx_'_
No Frequency Offset
R2 =
0.04-0,08
'0
'5
"VOD
00
7a,b
0.12-0.24
'MIN=O
0.015-0.03
%/oC
0.06-0.12
Frequencv Ofhet
fMIN
%/oCa:_..lf'VDD
'5
0.05-0.1
0.03-0.06
AI
5,10.15
10 12
VOL
5,10.15
=ro
Input Resistance of VCOIN
!Term 9'
VCO Output
Vol~age
'0
(Term 4'
Low Level
High level
VOH
veo Output TranSItion Times
0.01
10
9.99
'5
14.99
.0
5,10,15
-Vo
tTHl·
tTlH
V
4.99
DriVing COS/MOS·TVpe
load (e.g. Torm 3
Phase Comparator Inputl
VCO Output Dutv Cvcle
n
VOLTS
75
50
40
'0
'5
%
'50
'00
VCO Output Drive Current:
n·Channel (Smk)
p-Chenn.' (Source)
ION
0.5
0.5
lOp
4.5
9.5
Source·Foltower Output
(Demoduilltld Output):
I
RS>10kn
Offlllt Voltage IveOIN-VDEM)
AS >50 kn
Linearltv
'0
'0
0.43
0.86
'.3
-0.3
-0.9
-0.6
-1.8
5,10
'.5
'.5
'5
VeOIN' 2.6 to.3 V
~ 5 ±2.5 V
=7.6t5V
2.6
rnA
2.2
0.'
0 .•
O.B
10
'5
V
"
Zener Diode Voltage
C04046AD, CD4046AK
Vz
IZ ·501JA
Zltner Dvnltmic Resistance
AZ
I Z '" 1 mA
4.7
5.2
'00
5.7
V
n
593
CD4046A Slash (I) Series
File No. 752
ELECTRICAL CHARACTERISTICS AT TA = 25°C
CHARAC·
TERISTIC
CURVES
• TEST
CIRCUITS
FIG; NO.
LIMITS
SYMBOL
CHARACTERISTIC
TEST
CONDITIONS
UNITS
CD4046AD. CD4048AK
Vo
VDD
VOLTS VOLTS
MIN.
TYP.
MAX.
PHASE COMPARATOR Section
Operating Supply Voltage
15
15
Amplifier Operation
VOO-VSS
Comparators only
V
Total Quiescent Device Current:
Term. 14 Open
Term. 14 at
Vss or VOO
Term. 14 (SIGNAlINI
Input Impedance
IL
Term. 15 open
Term. 5 at VOO
Terms. 3 Be 9 at VSS
10
25
200
55
410
5
10
25
60
10
15
Z14
AC·Coupled Signal Input
Voltage Sensitivity
and Comparator Input
10
15
Voltage Sensitivity:
low Level
va
VOLTS
High Level
Output Drive Current:
n-Channel (Sink I
200
400
700
1.5
3
4.5
2.75
5.5
8.25
10
15
0.43
0.5
0.5
10
1.3
Phase Pulses
0.5
0.5
0.23
0.7
0.47
10
4.5
9.5
-0.6
10
-0.3
-0.9
4.5
9.5
10
-0.08
-0.25
1& II Term.28t 13
lOP
Phase Pulses
TYPICAL CENTER FREQUENCY
UNIT-TO-UNIT VARIATION
- 611f 0-%
400
BlO
rnV
2.25
4.5
6.75
Phase Comparator
IoN
MO
0.4
0.2
1& II Term. 2 Be 13
Phase Comparator
p·Channel (Source I
1
0.2
10
15
DC·Coupled Signal Input
IJA
15
V
3.5
7
0.86
2.5
1.4
rnA
-1.8
-0.16
-0.5
TYPICAL tMIN
UNIT- TO-UNIT VARIATION
16ft.UN 'fMIN)- '%
16f1101-%
CD4046AD
CD4046AK
CD4046AD
CD4046AK
±30
15V
lOV
~
____+-____+-____+-____~~~~5V
I5V
lOV
5V
2
VCO
92CS-22907
Fig. 6ta} - Typical center frequency vs. CI for RI = 10 kn, 100 kn,
and 1 Mn. Lower frequency values are obtainable if larger
values of CI are used.
594
46
e
TIMING CAPACITOR ICI)-I'F
92CS-22906
Fig. 6tb) - Typical frequency offset vs. C1 for R2 = 10 kn, 100 kn,
and 1 Mn. Lower frequency values are obtainable if
larger values of C1 are used.
CD4046A Slash (/) Series
File No. 752
ELECTRICAL CHARACTERISTICS
ltMITS AT INDICATED TEMPERATURES
C04046AD. CD404IlAK
CHARACTERISTIC
TEST CONDITIONS
Va
VoL"
VollS
lTerm16atV oo I
'L
Po
,,'
Dl.ltput Voltage:
Adjuu R:z Or'l
lO,IIA
Term 12 For
-IOaIlA
31
-210
30'
-200·
-260·
QUlput Drille Current:
n-Channel:
Oul (Term 4)
veo
CllTerm 61
C1ITerm71
R:z to VSS Term 12
Phase Compo I
10 - 10IJA
Qui (Term 13)
IPhase /Term I)
Pulses
p..Ch..Jnnel:
veo Out
(Term 4)
Phase Camp. I Out (Term 21
Out (Term 13)
Pha$(! Comp.1I
l:haSenermn
Pulses
7.5-
7.S-
7"
7.5-
7.B-
7.S-
0.5
10
~
~
!
f f
+
~
V
~
Zener Diode Voltage
Vz
VSS
Diode Ten
V,
100 IJA al each Input Or output
,
"
-250
,A
,A
0.25-
10
It
'OP
_190
10
t
'ON
OUIITe.m21
PhaseComp.Lt
lOjJA
'0'
VTHP
-19
0.50.5
Threshold Voltage:
VTHN
,A
, O·
14.5
J 95-
V OH
p-Channel
200·
,W
20'
0.55-
'.5
VOL
High·Leve'
,,'
"0
Iveo
veo OscilialOr Current
+12SoC
MIN.
TOL"I QUIescent Device Current
Qu'elcent Device Dissipation Per
Package (Term lliat V OO '
+2SoC
-5SoC
V OD
1.31.9
,,'
5.0·
1.3-
,,'
1.3-
1,6-
0.7-
0.90.9-0.9-
-1.1-
0.7-
-0.654.7-
Ground, 50 IJA InIO Term 15
1.5-
5.71.5
1.5-
Dymlmie
Phase Compo No.1 Output Voltage
~
Input SIgnal Voltage ITerm 141
E
10 kHl, See FIg. 7
400 mV
2.4-
2.6-
4.S-
5.2-
f
PhlIs.e Compo No.1 Output Vollage
Input SIgnal Vollage (Term 141 - BOO mV
1- 10 kHz, See Fig. 7
Limits with black dot (0) designate 100% testing. Refer to RIC-1 026 "High·Reliability COS/MaS CD4000A Slash II) Series Types", Tables 2
through 7 for testing sequence_ All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1: Complete functional test, all inputs and outputs to truth table.
Note 2: Test is e.ither a one input or a one output only.
··•
··r-
AMBIENT TEMPERATURE {T A }. 2~-C
'MAX. WHEN YCOIN-YOD,INHleIT-Yss
fMIN WHEN YCOIN-VSS
2
100
z
6
_i
,
x
I
TYPICAL 'MAX"MIN
UNIT-TO-UNIT VARIATION
Voo
2
~
~
lOa
r-------
·
6
CD4046AD
CD4046AK
I
2
-I.
5V
±30
10 V
+ 15
"I.
I5V
t 10
0,.
I
~
2
0.01
Voo
,
6 8
0.1
~
OV
/
.
6
8
I
R2IRI
.,".'
#
. .
....oJ,,'V'V
10 k!l
oJ"
.,
~"
CD4046A
(VTVM) OR
DIGITAL
•
6 8
•
10
Fig, 6(c) - Typical f max./fmin. vs. R2IRl.
~~L;~~hER
6 8
Vss
100
Fig. 7 - Test circuit for Phase Comparator I Output voltage.
595
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 745
Digital Integrated Circuits
OOm3LJO
Monolithic Silicon
High-Reliability Slash(/) Series
CD4047A/...
Solid State
Division
VDD
14
R-C COMMON
ASTABLE
ASTABLE
-TRIGGER
Vss
asc OUT
:; RETRIGGER
4
5
6
II
10
:
n
T. RESET
+TRIGGER
92C5-21431
High-Reliability
COS/MOS Low-Power
Monostable/Astable Multivibrator
For Logic Systems Applications in Aerospace,
Military, and Critical Industrial Equipment
Special Features:
•
-
Low power consumption: special COSIMOS oscillator configuration
Monostable (one-shot! or astable (free-running) operation
True and complemented buffered outputs
Only one external Rand C required
Monostable Multivibrator Features:
C04047A Block Diagram
- Positive- or negative-edge trigger
- Output pulse width independent of trigger pulse duration
RCA CD4047 A "Slash" (I) Series are high-reliability COS/MOS
integrated circuits intended for a wide variety of logic
function configurations in aerospace, military, and critical
industrial equipment.
RCA CD4047A consists of a gatable astable multivibrator
with logic techniques incorporated to permit positive or
,negative edge-triggered monostable multivibrator action having
retriggering and external counting options.
Inputs include +Trigger, -Trigger. Astable. Astable. Retrigger.
and External Reset. Buffered outputs are a, 0, and Oscillator.
In all modes of operation an external capacitor must be connected between C-Timing and RC-Common terminals, and an
external resistor .must be connected between the R-Timing and
RC-Common terminals.
Astable operation is enabled by a high level on the Astable
input. The period of the square wave at the a and outputs
in this mode of operation is a function of the external components employed. "True" input pulses on the Astable input
or "Complement" pulses on the Astable input allow the circuit
to be used as a gatable multivibrator. An output whose period
is half of that which appears at the a terminal is available at
the Oscillator Output terminal. However, a 50% duty cycle is
not guaranteed at this output. A high level should be applied to
the external reset whenever V DD power is applied or removed.
a
In the monostable mode positive-edge triggering is accom:
plished by application of a leading-edge pulse to the
"+Trigger" input and a low level to the "-Trigger" input.
For negative-edge triggering a trailing-edge pulse is applied to
the "-Trigger" and a high level is applied to the "+Trigger".
Input pulses may be of any duration relative to the output
pUlse. The multivibrator can be retriggered (on the leading
edge only) by applying a common pulse to both the
"Retrigger" and "+Trigger" inputs. In this mode the output
- Retriggerable option for pulse width expansion
- long pulse widths possible using small RC components by
means of exte'rnal counter provision
- Fast recovery time essentially independent of pulse width
- Pulse-width accuracy maintained at duty cycles approaching
100%
Astable Mu/tivibrator Features:
-
Free-running or gatable operating modes
50% duty cycle
Oscillator output available
Good astable frequency stability:
frequency deviation = ±2% + 0.03%fO& @ 100 kHz'
= ±0.5% + 0.015%fOC @ 10 kHz'
COS/MOS Features:
- Microwatt quiescent power dissipation: 0.511W (typ.)
- High noise immunity: 45% of supply voltage (typ.)
_ Wide operating-temperature range: -550 C to +1250 C
Applications:
Digital equipment where low-power dissipation andlor high
noise immunity are primary design requirements:
- Frequency discriminators - Envelope detection
- Timing circuits
- Frequency multiplication
- Time-delay applications
- Frequency division
.. Circuits "trimmed" to frequency; VOO = 10 V ± 10%.
pulse remains "high" as long as the input pulse period is shorter
than the period determined by the RC components.
An external countdown option can be implemented by
coupling "a" to an external "N" counter (e.g. CD4017A)
and resetting the counter with the trigger pulse. The counter
output pulse is fed back to the Astable input and has a dura·
tion equal to N times the period of the multivibrator.
9-74
596
File No. 745 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4047A Slash (I) Series
A high level on the External· Reset input assures no output
pulse during an "ON" power condition. This input can also
be activated to terminate the output pulse at any time.
These devices are electrically and mechanicallY identical with
standard COS/MOS C04047 A types described in data bulletin
623 and OATA800K SSO·203 Series, but are specially
processed and tested to meet the electrical, mechanical, and
environmental test methods and procedures established for
microelectronic devices in MIL-STO-883.
For a description of these screening levels and for detailed
information on test methods, procedures, and test sequence
employed with high-reliability COSIMOS devices refer to
High-Reliability Report RIC-l02C, "High-Reliability COSI
MOS CD4000A "Slash" III Series Types".
The C04047A "Slash" (I) Series types are supplied in 14-lead
dual-in-line ceramic packages ("0" suffix). in 14-lead ceramic
flat packages ("K" suffix), or in chip form ("H" suffix).
The packaged types can be supplied to six screening levels /1 N, /1 R, /1, 12, /3, 14 - which correspond to MI L-STO-883
Classes "A", "8", and "C"_ The chip versions of these types
can be supplied to three screening levels -1M, IN, and IR_
MAXIMUM RATlNGS,Absolute-Maximum Values:
Storage-Temperature Range
. ......... . -65 to +150
Operating-Temperature Range . ......... . -55 to +125
°c
°c
DC Supply-Voltage Range:
(VOO - VSS) .. - _. _ .. _ .. -. _ .. - .... -0.5to+15 V
Device Dissipation (Per Package) , .
200
mW
All )nputst _.... __ .. _ .. _ .. _.
VSS::; VI <; VOO
Recommended
OC Supply-Voltage (VOO - VSS) . _ .. .
3 to 15
V
Recommended
Input-Voltage Swing. ___ . _.... _ .. _ .. VDD to VSS
t
Special input protection circuit permits terminal 3 voltage to exceed
V DO or V55 by as much as 15 volts.
Fig.1 - CD4047A logic block diagram.
92CS-20026R2
597
CD4047A Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 745
CD4047A FUNCTIONAL TERMINAL CONNECTIONS
NOTE: IN ALL CASES EXTERNAL RESISTOR BETWEEN TERMINALS 2 AND 3A
EXTERNAL CAPACITOR BETWEEN TERMINALS 1 AND 3A
TERMINAL CONNECTIONS
FUNCTION
Astable Multivibrator:
Free Running
True Gating
Complement Gating
Monostable Multivibrator:
Positive·Edge Trigger
Negative·Edge Trigger
Retriggerable
External Countdown *
*
TOVDD
TOVSS.
4,5,6,14
4,6,14
6,14
7,8,9,12
7,8,9,12
5,7,8,9,12
4,14
4,8,14
4,14
14
5,6,7,9,12
5,7,9,12
5,6,7,9
5, 6, 7, B, 9, 12
INPUT PULSE OUTPUT PULSE
TO
FROM
5
4
8
6
8,12
-
10,11,13
10,11,13
10,11,13
10,11
10,11
10,11
10,11
OUTPUT PERIOD
OR
PULSE WIDTH
tA(10,ll )=4.40 RC
tA(13)=2.20 RC
tM(10,lll=2.4B RC
Input Pulse to Reset of External Counting Chip
External Counting Chip Output To Terminal 4
&
See Text.
ASTABLE
*
c
~,)-------------------...,
*
*
~ 4')-~;>--------------,
+TRIGGER
-TRIGGER
*
t-t--f--------{OZ
RETRIGGER
*
INPUTS PROTECTED BY
STANDARD COS/MOS
RESISTOR-DIODE NETWORK
~
**
'---------«(Sr
vss
EXTERNAL
MODIFIED INPUT PROTECTION
CIRCUIT TO PERMIT LARGER
INPUT- VOLTAGE SWINGS
RESET
Fig.2 - CD4041A logic diagram.
598
File
No.
745
CD4047A Slash
(II Series
STATIC ELECTRICAL CHARACTERISTICS (All Inputs ... VSs:S VI :S Vee)
Recommended ec Supply Voltage 3 to 15 V
CHARACTERISTIC
SYMBOL
LIMITS
TEST
CD4D47AD,CD4047AK
CONDITIONS
VDD
-55°C
25°C
Vo
Volts Volts Min.
Typ. Max.
Min. Typ. Max. Min.
Quiescent Device
Current
Quiescent Device
Dissipation/Package
0.5
IL
10·
10
5
PD
10
Output Voltage:
Low-Level
VOL
VOH
300
200·
10·
25
2.5
25
1500
100
10
100
2000
3
0.55-
5
0.01
0
0.01
0.05
10
0.01
0
0.01
0.05
0.5·
0.55-
3
2.25·
2.3-
5
4.99
4.99
10
9.99
9.99
4.95
10
20
pW
V
V
9.95
14.5·
15
pA
N
D
T
E
S
0.5·
15
High.Level
CHARAC·
TERISTIC
UNITS CURVES
& TEST
125°C
CIRCUITS
Typ. Max.
Fig.No.
14.45·
Threshold Voltage:
N-Channel
VTHN
ID· -10pA
-0.7- -1.7 -3·
-0.7- -1.5 -3"
-0.3- -1.3 -3"
p..channel
VTHP
ID ·10pA
0.7-
0.7-
1.5
0.3-
Noise Immunity
(Any input)
For Definition,
see Appendix in
SSO·207
VNL
VNH
1.7
3"
3"
0.8
5
1.5
1.5-
2.25
1.4
1.0
10
3·
3·
4.5
2.9·
4.2
5
1.4
1.5-
2.25
1.5
9.0
10
2.9-
3·
4.5
0.5
0.4·
0.8
0.28
1.25
1·
2
0.7
1.3
3"
V
V
21
V
3·
Output Drive Current:
(Q and Q)
N-Channel
IDN
0.5
5
0.5
10
4.5
P-Channel
IDP
(OSCILLATOR)
N·Channel
P-Channel
9.5
10
-0.5
-0.4- -0.8
-0.28
-1.25
-1·
-0.7
0.5
IDN
IDP
Diode Test
100 IlA Test Pin
V DF
Input Current
II
0.5
-2
rnA
3,4
rnA
5,6
0.8
10
4.5
5
9.5
10
-0.8
-2
1.5·
1.510
1.5-
V
3
pA
Limits with black dot (-) designate 100% testing. Refer to IAIC-102C"High·Reliability COS/MOS CD4000A Slash (J) Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1: Complete functional test, all inputs and outputs to truth table.
Note 2: Test is either a one input or one output only_
Note 3: Test on all inputs and outputs.
For Threshold Voltage Test Circuits. Operating and Biased Life Test Circuits. qutput Drive Current Test Circuits.
and for Operating Considerations, see Appendix
599
CD4047A Slash (II Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 745
DYNAMIC ELECTRICAL CHARACTERISTICS at TA =250 C, CL
Typical Temperature Coefficient for all values of VDD = 0.3%I"C
=15 pF
LIMITS
CHARACTERISTIC
SYMBOL
CD4047AK
CD4047AD
TEST CONDITIONS
VDD
(Volts)
Propagation Delay Time:
Astable, Astiibie
to Osc. Out
Typ.
Max.
200
400
100
200
5
-
550
900
10
-
250
500·
5
700
1200
300
600·
5
5
Astable, Astable
toO,5
tr-
5
tf
10
-
-
-
+Trigger, -Trigger
to Q, Q
10
tpHL
+Trigger, Retrigger
5
tpLH
toQ,a
10
External Reset
5
toQ,Q
10
Transition Time:
5
o,a
10
tTHL,
Osc, Out
5
tTLH
Minimum Input Pulse
Duration (Any input)
+Trigger, Retrigger
Rise & Fall Time
Average Input
Capacitance
10
tWL,
5
tWH
10
CI
Any input
300
600
175
300
300
600
125
250
75
125
45
75
75
150
45
100
500
1000
200
400
-
S
-
-
-
1
7
1
-
-
-
-
8
-
-
-
ns
-
-
I1S
-
-
pF
-
-
UNITS
Min.
10
CHARAC·
TERISTIC
CURVES
& TEST
CIRCUITS
Fig. No.
ns
N
0
T
E
ns
15
5
-
Note 1: Test IS a one Input, one output only.
Limits with black dot fe' designate 100% testing. Refer to RIC·102B "High-Reliability COS/MOS CD4000A Slash If) Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
AMBIENT TEMPERATURE ITA I ;'2S·C
TYPICAL TEMPERATURE COEFFICIENT AT ALL VALUES
OF VGS"-O.3 %'OC
4
E
t§ .GATE~TO-SOURCE
....
~ 50
VOLTAGE IVGS!; 15
~ 40
v
z
30
"...
~ 20
AMBIENT TEMPERATURE ITA) .·2S-C
TYPICAL TEMPERATURE COEFFICIENT AT ALL VALUES
~~~O~FIV~GS~·~-IDt·.~%~/I·ic~~~~~~~~~lI~~
25
~
ffi
GATE~TO-SOURCE
VOLTAGE IVGS)- 15 V
20
15
10 V
-'
10
~
z
z
10
~
5V
10
15
DRAIN-TO-SOURCE VOLTAGE IVDSI-V
92CS-2r3B6
Fig.3 - Typical n-channel drain characteristics for Q and Q buffers.
600
~
~
10 V
~
~
~E
~z
il
:
4
5V
10
IS
DRAIN-TO-SOURCE VOLTAGE 1VoSI-V
92CS-22898
FigA - Minimum n-channel drain characteristics for Q and Q buffers.
File No. 745 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4047A Slash (I) Series
ORAIN-TO-SOURCE VOLTAGE 1VOSI-V
-IS
-10
AMBIENT TEMPERATURE ITAla'ZSoC
TYPICAL TEMPERATURE COEFFICIENT
AT ALL VALUES OF VGS.-0.3 .,.. ,oC
ORAIN-TO-SOURCE VOLTAGE 1Vosl-V
-IS
-10
-5
AMBIENT TEMPERATURE ITAl a 2SoC
5V
TYPICAL TEMPERATURE COEffiCIENT
AT ALL VALUES OF VGs.-O.3 %,OC
-S
5V
a
10 V
-10
~
~
'"zz
c
GATE-TO-SOURCE VOLTAGE
IVGS}~
-15
IiI
15 V
GATE-TO-SOURCE VOLTAGE IVGSI"! 15 V
Fig.6 - Minimum p--t:hannel drain characteristic~
for Q and Q buffers.
92CS-213BB
Fig.5 - Typical p-channel drain characteristics for
Q and Q buffers.
r
I. Astable Mode O.'ign Information
A.· Unit-to·Unit Transfer-Voltage Variations
The following analysis presents worst-case variations
from unit-to-unit as a function of transfer-voltage
(VTR) shift (33%-67% VOO) for. free·running (astable) operation.
AMBIENT TEMPERATURE ITAla2SoC
TYPICAL TEMP. COEFFICIENT AT ALL VALUES OF VOO'0.3 .,%C
"i-
'"~IOOO
5~ 800
SUPPLY VOLTAGE (Vool-SV
i!l
TERMINAL
3 600
13~
TERMINALIO~
If
o
If 400
~IA---1
10V
g
~
9ZCS-22897
.. ISV
ZOO
6
Fig.9 - Astable mode waveforms.
'"
o
10
203040
SO
6070
8090
LOAO CAPACJTANCE ICL)-pF
92CS-21439
'I • -RC In
Fig.7 - Typicallow-to-high level propagation delay
time vs. load capacitance for Q and ii buffers.
Vee
+ VTR
Vee-VTR
'2' -RC In 2Vee - VTR
'A·2 hI +'2)
AMBIENT TEMPERATURE ITAI"25°C
TYPICAL TEMP. COEFFICIENT AT ALL VALUES OF VDO"o.3
%/-t
• -2 RC In (Vee
r
~I-
%'200
E
~
VTR' 0.5 Vee
Min;
VTR' 0.33 Vee
Max;
VTR' 0.67 Vee
'A '4.40 RC
'A '4.62 RC
'A '4.62 RC
150
thus if ItA = 4.40 RC I is used, the maximum variation will be
I-
il
100
~
50
5i
Typ:
+ VTR) 12Vee - VTR)
10V
10
20
30
40
50
60
LOAD CAPACITANCE (CLI-pF
70
(+5.0%, -0.0%).
80
92CS-21440
Fig.8 - Typical transition time vs. load capacitance
for Q and Qbuffers.
90
B. Variations Oue to VOO and Temperature Changes
In addition to variations from unit-ta-unit, the astable
period may vary as a function of frequency with respect to VOO and temperature. Typical variations are
presented in graphical form in Figs. 10 to 20 with 10 V
as reference for voltage variation curves and 2SoC as
reference for temperature variation curves.
601
CD4047A Slash(/) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~_ _ _ _ _ _ _ File No. 745
II. Monostable Mode Design Information
The following analysis presents worst-case variations from
unit-to-unit as a function of transfer-voltage (VTR) shift
(33% - 67% VOO) for one-shot (monostable) operation_
TERMINAL 8
1L---fL..-
TERMINAL 13
~
TERMINALIO~
92CS-2002B
Fig.21 - Monostable waveforms.
tl' =
-RC In
VTR
2V ee
1M = ·(t1' + t2)
tM =
(VTR) (Vee - VTR)
-RC In
SUPPLY VOLTAGE CVOD1-V
92CS-21451
(2Vee - VTR) (2V ee)
Fig.tt -
Typical O-and-O-pulse-width accuracy VI.
supply voltage I'M = 75, 60, 120 ,..)_
where tM • Monostable mode pulse width. Values for tM are as
follows:
=0.5 Voe
tM = 2.48 RC
Typ:
VTR
Min:
VTR = 0.33 Vee
tM = 2.71 RC
Max_ VTR = 0.67 Voe
tM = 2.48 RC
Thus if
11M = 2.48 RC I is used, the maximum variation will be
(+9.3%. -0.0%).
Note:
In the astable mode, the first positive half cycle has a
duration of TM; succeeding durations are tA/2.
In addition to variations from unit to unit, the monostable
pulse width may vary as a function of frequency with
respect to VOO and temperature. These variations are
presented in graphical form in Figs.l0 to 14 with 10 V
as reference for voltage variation curves and 2S oC as refer-
5
10
15
SUPPLY VOLTAGE (VOD)-Y
92CS-21430
Fig. 12 - Tvpical O-and-"lJ..pulse-width accu;acv
ence for temperature variation curves ..
VI.
supply voltage I'M ;;. 100 ms).
.
e
'"
..:l
~
AMBIENT TEMPERATURE (fA I_
MONOSTABLE MODE
zs-c
...
~
±4
10 +10
a: +15
t
I
~
~
:l
'"
b
iii
"
t3
~
*" V I
i2
..
Q
Z
"
IO
I
10- 4
I
5V±IO%
Fig.
to -
15
~
-~
10'5
T
pi
ool-15V!IO%
S,PPLY VOLTAGE IV
%
60
C
R Voo
pF KD
V
100 47 5,10
100 220 5,10
.1
10-3
10"2
o AND tI-PULSE
10- 1
la'
100
WIDTH-SECONDS
92CS-Z1391
Typical (J.and-{I:.pulse-width accuracy VI.
o andO pull6 width for a variation of
± 10% from value Indicated.
602
.5
5 Y± 10.,.
~
I~
MONOSTABLE MOOE
t5
-5'
-35
-1&
+5
+25
+45
+65
.85
AMBIENT TEMPERATURE (TA)--C
Fig. 13 - Typical O-anrJ.7i-pulse-width accuracy
ttlmperature (high frequency).
+105
+125
Q?CS-2I4S3
VI.
File No. 745 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4047A Slash II) Series
1------,
OPTIONAL
BUEFER
f:;;--.........D~-OUT
INPUT
PULSE
J'L_ _ _ _ _ _ _J
J
L
-oj 'EXT I-
IA)IOo,.l StMSlms
Voo .!S,ICY
92CS-Z0030RI
(BJlM2:IOms
Voo-5.IOV
Fig. 16 - Implementation of external
counter option.
V.
-3!5
-15
+s
+25
+45
+65
+85
AMBIENT TEMPERATURE ITA1--C
+10!5
+I~
92CS-21454
Fig. 14 - Typical O-and-7f.pu/strwidth accuracy
However, in consideration of accuracy, C must be much
larger than the inherent stray capacitance in the system
(unless this capacitance can be measured and taken into
account). R must be much larger than the COS/MOS
"ON" resistance in series with it, which typically is
hundreds of ohms. In addition, with very large vaiues
of R, some short·term· instability with respect to time
may be noted.
range vs. temperature.
III.
Timinll"Component Limitations
The capacitor used in the circuit should be non·polarized
and have low I"eakage (i. e. the parallel resistance of the
capacitor should" be an order of magnitude greater than
the external resistor used). There is no upper or lower
limit for either it or C value to maintain oscillation.
Retrigger Mode Operation
The C04047A can be used in the retrigger mode to ex·
tend the output·pulse duration. or to compare the fre·
quency of an input signal with that of the internal
oscillator. In the retrigger mode the input pulse is applied
to terminals 8 and 12. and the output is taken from
terminal 10 or 11. As shown in Fig.15, normal mono·
stable action is obtained when one retrigger pulse is
applied. Extended pulse duration is obtained when
more than one pulse is applied. For two input pulses,
tRE = tl' + tl + 2t2. For more than two pulses,
tRE (0 OUTPUT) terminates at some variable time to
The recommended values for these components to main·
tain agreement with previously calculated formulas with·
out trimming should be:
"
C ~ 100 pF, up to any practical value, for astable
modes;
C ~ 1000 pF, up to any practical value for monostable modes.
10KO~ R~
1 MO.
o OUTPUT
TERMINAL 10
Fig. 15 - Rerrigger-mode waveforms.
VI.
after the termination of the last retrigger pulse. to is
variable because tRE (0 OUTPUT) terminates after the
second positive edge of the oscillator output appears at
flip-flop 4 (see Fig.2).
IV.
External Counter Option
Time tM can be extended by any amount with the use of
external counting circuitry. Advantages include digi·
tally controlled pulse duration, small timing capacitors
for long time periods, and extremely fast recovery time.
A typical implementation is shown in Fig.29. The pulse
duration at the output is
text = (N -1) (tA) + (tM + tA/2)
where text = pulse duration of the circuitry, and N is the
number of counts used.
Power Consumption
In the standby mode (Monostable or Astable). power
dissipation will be a function of leakage current in the
circuit, as shown in the static· electrical characteristics.
For dynamic operation, the power needed to charge the
external timing capacitor C is given by the following
formulae:
Astable Mode: P = 2CV2f. (Output at terminal No.
13)
P = 4CV2f. (Output at terminal Nos.
10and 11)
Monostable Mode:
P=
(2.9CV2) (Outy Cycle)
T
(Output at terminal
Nos. 10 and 11)
603
CD4047A Slash (I) Series _ _ _ _ _ _ _~_ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 745
The circuit is designed so that most of the total power is
consumed in the external components. In practice, the
lower the values of frequency and voltage used, the closer
the actual power dissipation will be to the calculated
value.
10 5 ASTABLE MODE
SUPPLY VOLTAGE (Vool-SY
~,~.t---+--+--t_-_+--+_--f_-_l
~
e:
Because the power dissipation does not depend on R, a
design for minimum power dissipation would be a small
value of C. The value of R would depend on the desired
period (within the limitations discussed above). See
Figs. 30-32 for typical power consumption in astable
mode.
10 6
ASTABLE MODE
SUPPLY VOLTAGE (Vool=IO"!
10°
Q OR
lo5-l=--_+--+--f---+--+---f--_l
:it
~
10'
Q
10 2
10 3
104
10 5
FREQUENCY tf 1 - Hz
92CS-21415
Fig. 17 - Power dissipation
IVOO -5 VI.
- lo4-l=--_+--+--f---+--+--
V.I.
output frequency
z
o
~
~ 103-b---l--
ASTABLE MODE
SUPPLY VOLTAGE (VDD1~ISV
Q
'""'~
~ 10'-l:----j--+--t---t--+---I-.....,,-J
I02~---l--_r-~+_--+--+--+_--+
1o
10'
z
o
0.
10°
10'
10 2
10 3
oOR Q FREQUENCY III-HI:
104
10 5
92CS-21413
Fig.f8 - Po·wer dissipation VI. output frequency
IVoo-tO VI.
106
~~
I04-t---I---+--+_"""
lo3i=~~=-~~~~t:=--t~-+---~-~
Q
i'" I02+--f---+--+----l--+--+_--+
L--1407,~-ll10~O~LUI0+.'~~140~2~~10~3~~10~4~LU,+O'~~~,~
aORO FREQUENCY If)-HI'
10V
I.
Fig. 19 ~ Power dissipation vs. output frequency
IVOO = 15 V).
13
12
"10
9
8
TEST
~v OR IOV
, •
TERMINAL Nos·
5
8
0
NC
I
0
I
•
0
0
I
0
I
0
0
9
12
0
I
I
0
I
0
0
0
92CS- 21HI
."
"12"
5
10
Fig.20 - Quiescent device current.
92CS-21322
Fig.21 - Noise immunity.
604
File No. 747 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Digital Integrated Circuits
OOm3LJD
Monolithic Silicon
Solid State
Division
High-Reliability Slash(/) Series
CD4048A/ .••.
High-Reliability COS/MOS
Multi-Function Expandable
8-lnput Gate
BINARY CON!ROL INPUTS
'FUNCTION CONTROL'
Ka Kb Kt Kd
INPUTS
Ii
~~~~~oEL
For Logic Systems Applications in Aerospace,
Military, and Critical Industrial Equipment
12
EXPAND
15
J
OUTPUT
Special Features
Applications:
• Medium-power TTL drive capability
a Selection of up to 8 logic functions
• Three-state output
.. Digital control of logic
• General-purpose gating logic
" High-current source and sink capability
9 mA (typ,)@V DS =0.5V, V DD = 10 V
-Decoding
.. Many logic functions available in one package
-Encoding
vss·e
VOC"IS
92CS-22249
RCA CD4048A "Slash" (I) Series are high· reliability COS/
MOS integrated circuits intended for a wide variety of logic
function configurations in aerospace, military, and critical
industrial equipment. The CD404BA is an B·input gate
having four control inputs. Three binary control inputs Ka, Kb, and Kc - provide the implementation of eight different logic functions. These functions are OR, NOR, AND,
NAND, OR/AND, OR/NAND, AND/OR, and AND/NOR.
A fourth control input - Kd - provides the user with 3-state
outputs. When control input Kd is "high" the output is
either a logic 1 or a logic 0 depending on the input states.
When control input Kd is "low", the output is an open circuit. This feature enables the user to connect this device to a
common bus line. In addition to the eight input lines, an
EXPAND input is provided that permits the user to increase
NOR
the number of inputs to one CD404BA, (see Fig. 2). For
example, two CD404BA's can be cascaded to provide a 16·
input multifunction gate. When the EXPAND input is not
used, it should be connected to VSS'
These devices are electrically and mechanically identical with
standard COS/MOS CD404BA types described in data bulletin 636 and DATABOOK SSD-203 Series, but are specially
processed and tested to meet the electrical, mechanical, and
environmental test methods and procedures established for
microelectronic devices in MI L·STD-BB3.
The packaged .types can be. supplied to six screening level./IN,/lR,/l,12,/3,/4 - which correspond to MIL·STD-BB3
Classes "A", "B", and "C". The chip versions of these types
can be supplied to three screening levels -1M, /N, and IR.
OR
~~
NAND
A~
A~
C 0
C
E F
G H
E F
G H
EXP
EXP
ORlAND
AND
D
OR/NAND-
A~
C D
E
F
G
H
EXP
AND/OR
ANDtHOR
;~ ;~;~;~
G.
~
G
~
G
~
G
~
92CM-2Z250
Fig. I-Basic logic configurations.
9-74
605
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 747
CD4048A Slash (I) Series
For a description of these screening levels and for detailed
information on test methods, procedures, and test sequence
employed with high·reliability COSIMOS devices refer to
High·Reliability Report RIC·l02C, "High·Reliability COSI
MaS CD4000A "Slash" (I) Series Types".
The C04048A "Slash" (I) Series types are supplied in 16·
lead dual·in·line ceramic packages ("0" suffix), in l&lead
ceramic flat packages ("K" suffix), or in chip form ("H"
suffix).
MAXIMUM RATINGS,Absolute·Maximum Values:
DC Supply·Voltage IVOO - VSS) .....
3 to 15
V
Storage·Temperature Range ........ . .. -65 to +150 °c
Operating·Temperature Range ........... -55 to +125 °c Recommended
Input·Voltage Swing ................ VOO to VSS
OC Supply·Voltage Range:
IVOO -VSS) .................... . -0.5 to +15 V Lead Temperature lOuring Soldering)
At distance 1/16" ± 1/32"
200 mW
Device Dissipation (Per Package) ........ .
11.59 ± 0.79 mm) from case
All Inputs ......................... . VSS
~4.
w
3
~
~
g
5
~
__•
MINIMUM
MAXIMUM
2
I
o
o
I
2
3
INPUT VOLTAGE (VI l-V
INPUT VOLTAGE
tV~I-V
92CS-20480
Fig. 3-Min. & max. voltage transfer characteristics of CD4050A.
Fig. 4-Min. & max. voltage transfer characteristics for CD4049A.
611
CD4049A, CD4050A Slash (II Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 746
STATIC-ELECTRICAL CHARACTERISTICS
LIMITS
CHARAC·
TERISTIC
C04049AO, C04049AK
TEST
UNITS CURVES NOTES
C04050AO, C04050AK
CONDITIONS
& TEST
IVO IVee
55°C
25°C
CIRCUITS
125°C
Volts Volt. Min. Max. Min. Typ. Max. Min. Max.
Fig. No.
CHARACTERISTIC
SYMBOL
au iescent Device
Current
IL
VIH=
VCC
5
15
-
Quiescent Device
Dj~ipation Package
Po
VIH=
VCC
5
15
Output Voltage
Low·Level
VOL
3
5
High·Level
Threshold Voltage
N-Channel
P·Channel
Noise I mmu n ity
-
VNL
C04050A
C04050A
-
VNH
C04049A
For Definition,
See Appendix
550·207
Output Drive Current
N·Channel
ION
VOH=
7.2 V
VOL =
0.95 V
VOL=
2.9 V
VOH =
7.2 V
VOH =
3.6V
VOH =
2.9 V
VOL =
0.95 V
lOP
V OF
Input Current
II
VIH=
VCC
0.01 0.3
U.Ul :U.5"
-
1.5
5
-
0.05
0.1
1.5
5
-
-
0.2.
0.01
-
-
0.6.
0.01
-
-
-
0.05
0.05
0.7.
-
-
0
U.Ul
U
-
u.ul
2.2.
4.99
5
9.99 10
14.4.
-
·0.7. ·1.5
0.7. 1.5
·3.
3.
·3.
3.
5
1
-
1.
10
2.
-
5 1.5
-
20
lU'
0.6.
-0.7.
0.7.
IO=·IO/lA
IO-101lA
p.channel
Diode Test 100 IlA
·Test Pin
-
lU
VOH=
3.6 V
(Allinputsl
C04049A
-
15
3 2.B.
5 4.99
10 9.99
15
VOH
VTHN
VTHP
0.3
U.5·
100
100
4.95
9.95
14.3.
·0.30 ·3.
3.
0.3.
-
0.9
-
2.
4.5
-
1.9.
-
-
1.5.
2.25
-
1.4
-
-
3.
4.5
-
2.9.
-
10 2.9.
-
3.
4.5
-
3.
-
5 1.4
-
1.5.
2.25
-
10 2.9.
-
3.
4.5
-
5 1.4
3.
1.5
3.
j.IW
V
2-7
V
V
2
18
1
B.9
2
-
-
1.5.
2.25
-
1.5
-
4.5 3.3
5 3.75
10 10
-
5.2
6
16
-
5 ·0.62
5 ·1.B5
10 ·1.B5
-
-
1.B
2.1
5.6
4.5
2.5
9.5
2.6.
3.0.
B'
·0.5.
·1.25.
·1.25
·0.35
·0.9
·0.9
-
-
1.5.
-
-
1.5.
-
1.5.
-
-
-
10
-
-
-
rnA
pA
... --Limits with black dot (.) designate 100% testing. Refer to RIC·l02B "High·Reliability COS/MOS CD4QOOA Slash (I) Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1: Complete functional test, all inputs and outputs to truth table.
Note 2: Test is either 8 one input or a one output only.
612
Note 3: Test on all inputs and outputs.
1
-
0.4
0.4
0.5
·1
·2.5
·2.5
17
V
2.25
10
jJA
File No. 746 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4049A. CD4050A Slash (I) Series
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C, CL = 15 pF, and input rise and fall times = 20 ns
Typical Temperature Coefficient for all values of VCC = 0.3%/o C. (See Appendix for Waveforms)
LIMITS
CHARACTERISTICS
SYMBOL
TESTCON~
VCC
(Volts)
Propagation Delav Time:
High-la-Low Level
Low-ta-High Level
Transition Time:
High-ta-Low Level
tpHL
VIH=VCC
tpLH
VIH =Vee
tTHL
VIH =VCC
Low-ta-High Level
Input Capacitance
tTLH
VIH =Vee
el
Any Input
5
10
5
10
5
10
5
10
'CD4049AD
CD4049AK
Min.
Typ.
Max. Min.
-
15
10
50
25
55
30'
80
55'
-
Typ.
CHARAC·
TERISTIC
UNITS CURVES
& TEST
CIRCUITS
Max.
Fig. No.
55
25
90
40
110
55'
140
85'
20
16
45
40'
100
60'
CD4050AD
CD4050AK
-
-
-
20
16
45
40'
-
50
30
100
60.
-
50
30
-
5
-
-
5
-
ns
10,11
ns
12,13
n,
14
ns
15
pF
-
NOTES
1
1
-
NOTE 1: Test is a one-input, one-output only.
Limits with black dot (-, designate 100% testing. Refer to R1C-l028 "High-Reliability COS/MOS CD4000A Slash III Series Types", Tables 2
through 7 for testing sequence, All other limits are designer's parameters under given test conditions and do not represent 100% testinq.
INPUT VOLTAGE (VI)- V
92CS-20483
92CS-20482
Fig. 5-Min. & max. voltage transfer characteristics for CD4050A.
Fig. 6- TVp. voltage transfer characteristics as a function of temperature for CD4049A.
INPUT
92CS-20484
Fig. 7- Typ. voltage transfer characteristics as a function of temperature for CD4050A.
92CS-2048~
Fig. 8- Typ. & min. n-channel drain characteristics as a function of
gate-to-source 1I0ltage (VGS) for CD4049A, C04050A.
613
CD4049A, CD4050A Slash (II Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 746
DRAIN-TO-SOURCE VOLTAGE
Nos)-V
LOAD CAPACITANCE ICLI-pF
Fig. 9- Typ. & min. P-channel drain characteristics as a function of
gate-fa-source voltage (VGS) for CD4049A, CD4050A.
92C5-20529
Fig. to-Typ_ high-to-low level propagation delay time "s. CL for
C04049A.
%
250
~i=
200
it
1<
~
ii
150
Ii
~
100
0
If
§
50
~
"
20
a
100
20
LOAD CAPACITANCE (CL)-pF
40
60
BO
100
LOAD CAPACITANCE (CLI- pF 92C5-20528
92C5-20487
Fig. 1t-Typ. high-to-Iow level propagation delay rime
V.i.
CL for
Fig. 12- Typ. low-to-high level propagation delay time V.i. CL for
CD4049A.
CD4050A.
AMBIENT TEMPERATURE (TA) ·25·C
TYPICAL TEMPERATURE COEFFICIENT
FOR ALL VALUES OF Vee· 0.3%'·C
....
!- 80
"'";:
ii
;: 60
!l1
~
40
~
20
;t
9
LOAD CAPACITANCE (C l )-pF
Q2CS-20526
92C5-20488
Fig. 13-TVp. low-to-high level propagation delay time V.i. CL for
CD4050A.
614
Fig. 14- Typ. high·to-/ow level transition time vs. CL for CD4049A,
C04050A.
File No. 746 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4049A. CD4050A Slash (I) Series
INPUT FREQUENCY ",I kH:r
92CS-20527
92CS-20489
Fig. IS-Typ. low-fa-high level transistion time vs CL for CD4049A.
CD4050A.
Fig. 16- Typ. diuipation characteristics for CD4049A. CD4050A.
5VORIDV
5VOR 10 V
3.5VOR 1V
3.5VOR7V
16
I>
16
15
I.
J
--±Q-
13
OUTPUT
"
•
6
ro~
12
IVOR2V
I.
3
-=-
13
5
12
I.~VOR3V
"
10
10
9
<)2CS-205J6RI
92CS-20515RI
(C04049A)
(C04050AJ
92CS-24422
Fig. IS-Noise immunity test circuits.
Fig. 17-Quiescent device current test circuit.
106 AMBIENT TEMPERATURE ITA }~25°C
1'" ,0 ,
~
..
0
'"
"''"Ir
~
¥i'"
~
~
~
0
Z
0
~
'"
z
~
~
i:l
10
~
~
10
10'
10'
..
..
~'/o~'
",,\00
10'
~~t
10 2
J" . \",~l
10
-1-'
~o"
.'
,...,00"
c,~-1-'
,...,0"
4,.\."
...~
,,<0
1=
",0
. ~'f
,..
,0
~."
,.~~
",'
.",.,;<
,.0~""~
I
la'
10
TRANSITION TIME-ns
TRANSITION TIME-ns
'i?C.S-204QO
Fig. 79- Typ. power dissipation vs. transition time per inverter
CD4049A.
DISSIPATION PER PACKAGE
-1-'
\
0
:r
~1
\,:;"."
\
~
~
c
'"
~
10 4
MAXIMUM
92CS-20491
Fig. 20-Typ. power dissipation vs. transition time per inverter
CD4050A.
615
File No. 849
ffil(]3LJlJ
Digital Integrated Circuits
Monolithic Silicon
Solid State
Division
High-Reliability Slash (I) Series
CD4057A1...
High-Reliability
COS/MOS LSI 4-Bit Arithmetic
Logic Unit
CD4057AK
28·LEAD FLAT·PACK CERAMIC
For Logic Systems Applications in Aerospace,
Military, and Critical Industrial Equipment
Features:
• LSI Complexity on a Single Chip
• 16·lnstruction Capability
H~1786
CD4057AD
2B·LEAD DUAL·IN·LlNE CERAMIC
• Instruction Decoding on Chip
• Fully Static Operation
• Single-Phase Clocking
·Add, Subtract, Count
·AND, OR, Exclusive·OR
·Right, Left, or Cyclic Shifts
RCA-CD4057A Slash (I) Series is a low-power arithmetic logic
unit (ALU) designed for use in LSI computers_ An arithmetic
system of virtually any size can be constructed by wiring together. number of CD4057A ALU's_ The CD4057A provides
4-bit arithmetic operations, time sharing of data terminals, and
full functional decoding for all control lines. The distributed
control system of this device provides great flexibility in
system designs by allowing hard-wired connection of N units
in 4N unique combinations. Four control lines provide 16
instructions which include Addition, Subtraction, Bidirec-.
tional and Cycle Shifts, Up-Down Counting, AND, OR, and
Exclusive-OR logic operations_
a
Two mode control lines allow the CD4057A to function as
any 4-bit section of a larger arithmetic unit by controlling
the bidirectional serial transfer of data to adjacent arithmetic
arrays_ By means at' three "Conditional Control" lines
Overflow, All Zeros, and Negative State conditions may be
detected and used to establish a conditional operation_
Predetermined operation of the CD4057A on a conditional
basis allows greater ALU flexibility. Although especially
applicable as a parallel arithmetic unit, the CD4057 A also
finds use in virtually any application requiring one or more
of its 16 basic instructions. The CD4057A is supplied in a
hermetically sealed 28-lead dual-in-line ceramic package
(CD4057 AD), in a flat-pack (CD4057 AK), and in chip
form (CD4057AH),
These devices are electrically and mechanically identical with
standard COS/MOS CD4057A types described in data bulletin
635 and DATABOO K SSD-203 Series, but are specially processed and tested to meet the electrical, mechanical, and
environmental test methods and procedures established for
microelectronic devices in MIL-STD-883_
616
• Bidirectional Data" Busses
• Easily Expandable to 8, 12, 16,. . . Bit Operation
• Conditional-Operation Controls on Chip
• Low Quiescent Device Dissipation. _. _ 10 JlW (typ) at
VDD= 10V
• Add Time (Data In-To Sum Out) =375ns(typ)at10V
• All Terminals Protected Against Static Discharge
• High Noise Immunity _ .. 45% of VDD (typ) Over Full
Temperature Range
• Operation from Single Positive or Negative
Power Supply ... 3 V to 15 V
• Full Military Temperature Range. __ -550 C to +1250 C
Applications:
• Parallel Arithmetic Units
• Process Controllers
• Remote Data Sets
• Graphic Display Terminals
RIGHT SERIAL
OATA LINE
CLOCK
CONOITIONAL{
INPUTS
:1.._ _-,-_--l
TO
REGISTER
INPUT/OuTPUT
92CS-
202~8RI
F;g. 1 - Block diagram - CD4057A.
9-74
File No. 849
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4057A Slash
The packaged types in the CD4057A "Slash" (I) Series can be
supplied to five screening levels - 1R, II, 12, 13, 14 - which
correspond to MIL-STD·883 Classes "A", "8", and "C".
The chip versions of these types can be supplied to three
screening levels - 1M, IN, and IR.
(II Series
MAXIMUM RATINGS, Absolute Maximum Values:
STORAGE·TEMPERATURE RANGE ........•..
-65 to +150
OPERATING· TEMPERATURE RANGE ........
-55 to +125
DISSIPATION PER PACKAGE.... .... .. ............
°c
°c
200 mW
DC SUPPLY·VOLTAGE RANGE IVDD-VSSI ...... -0.5 to +15 V
ALL INPUTS ............................. VSS
For a description of these screening levels and for detailed
information on test methods, procedures, and test sequence
employed with high·reliability COSIMOS devices refer to
High·Reliability Report RIC·102C, "High·Reliability COSI
MaS CD4000A "Slash" II) Series Types':
-S VI '::YDD
lead Temperature lOuring sOldering)
At distance 1/16 ± 1/32 inch 11.59 ± 0.79 mml
from case for 10 seconds max. ................... 265°C
MINIMUM RECOMMENDED
DCSUPPLYVOLTAGEIVDD-VSSI ....................
3V
PARALLEL DATA
IN/OUT LINES
~------''-------
FUNCTION { :
SELECT
c
,
I
6
7
CLOCK
A
CONDITIONAL {
INPUTS
•
B
C
OVERFLOW
1/0
OVERFLOW
IND.
LEFT
NEG
SERIAL IND.
"
BYPASS
4
2.
Z!
ROTATE-2
(Ro2)
OUTPUT
DATA
LINE
Fig.2 - Simplified logic diagram.
617
File No. 849
CD4057A Slash III Series
STATIC ELECTRICAL CHARACTERISTICS
TEST
CONDITIONS
CHARACTERISTIC
SYMBOL
Vo
.Volts
Quiescent Device
Current
IL
Quiescent Device
Dissipation/Package
PD
Output Voltage: 1
Low·Level
5
10
5
10
3
5
10
15
3
5
10
15
VOL
VOH
High·Level
Threshold Voltage2
N·Channel
P-Channel
VTHN
VTHP
Noise Immunity 1
(All Inputs)
VNIL
VDD
Volts
IO~-20pA
-5SOC
Min. Max.
-
-
2.25
4.99
9.99
-0.7-
IO~20pA
O.~
·0.8
1
4.2
9
5
10
5
10
l.se
ION
0.5
0.5
5
10
IDP
3
7
VNIH
a1.42.ge
3.7
7.5-
-
LIMITS
25°C
Typ. Max•
Min.
-
-
-
0.55
O.ot
0.01
-
-
0.5
1
2.5
10
5
loe
2.5
100
-
0.5
0.01
0.01
0.5
-
-
-
-
-
-
2.3
4.99
9.99
5
10
-aa-
14.5
-
-0.70.7-
-1.5
1.5
1.5-
2.25
4.5
2.25
4.5
-aa-
a1.5-
-
a-
-
-
125°C
Min. Max.
-
-
-
4.95
9.95
150
200e
750
2000
UNITS
p.A
pW
0.05
0.05
0.55
-
V
1495
-0.3-
-3-
O.a-
a-
1.42.ge
-
-
l.se
ae
-
-
0.06
0.07
-
V
V
Output Drive Current 2
Zero Indicator
N-Channel
P·Channel
5
10
0.11
0.12
-0.04
-0.08
-
O.Oge
O.loe
-0.03
-0.07-
-0.06
-0.13
0.5
0.5
4.5
9.5
5
10
5
10
0.11
0.12
-0.07
-0.12
-
0.09
O.loe
-0.06
-O.loe
0.30
0.40
-0.19
-0.30
0.5
0.5
4.5
9.5
5
10
5
10
0.25
0.37
-0.08
-0.12
-
-
0.20
0.3oe
-0.07
-O.loe
0.50
0.90
-0.21
-0.38
0.5
0.5
4.5
9.5
5
10
5
10
0.11
0.06
-0.02
-0.06
-
0.09
0.05-0.02
-0.05-
0.10
0.12
-0.05
-0.08
-
1.5-
-
-
0.16
0.16
-
-0.02
-0.05
-
Negative Indicator
N-Channel
ION
P·Channel
lOP
-
-
-
0.06
0.07
-0.04
-0.07
-
-
mA
Overflow Indicator
N·Channel
P·Channel
ION
lOP
-
-
-
-
-
0.14
0.21
-0.05
-0.07
-
-
-
All Other Outputs
N-Channel
ION
P·Channel
lOP
Diode Test3
l00pA Test Pin
VOF
-
-
-
0.06
0.03
-0.01
-0.03
1.5·
-
l.se
-
V
limits with black dot 'e) designate 100% testing. Refer to RIC·102C "High-Reliability COS/MOS CD4000A Slash If) Series Types", Tables
2 through 7 for testing sequence. All other limits are designer"s parameters under given test conditions and do not represent 100% testing.
Nate 1: Complete functional tast,811 inputs and outputs to truth table.
Note 3: Test on all inputs and outputs.
Note 2: Test is either 8 one input or a one output only_
618
CD4057 A Slash (II Series
File No. 849
DYNAMIC ELECTRICAL CHARACTERISTICS. at TA = 2SOC and CL = 15 pF
Typical Temperature Coefficient at all values of V DO = O.3%/"C
CHARACTERISTICS
SYMBOLS
TEST
CONDITIONS •
VDD
Volts
LIMITS
CD4057AD CD4057AK
Min.
Typ.
Max.
5
10
-
1430
375
3900
720
5
10
-
915
310
2550
840
DATAIN·toCARRY OUT
5
10
-
950
265
2580
720
GARRY IN·to·
CARRY OUT
5
10
-
485
175
1320
480
-
1980
750
265
5400
2040
720
110
300
5
10
5
10
5
10
-
3700
1650
420
220
300
165
10350
4500
1140
600
825
450
5
10
1000
475
2775
1275
5
-
400
1200
10
-
125
375
5
-
-
15
-
20
10
1675
485
20
10
40
20
4590
1320
40
20
-
Propagation Delay Time:
DATA IN·to·
SUM OUT
CARRY IN·toSUM OUT
Zllnput
·toZIOutput
tplH.
tpHl
tplH
tpHl
5
10
5
10
-
UNITS
ns
Transition Time:
ZIOutput
tTlH
tTHl
Negative Indicator and
Overflow Indicator
All Other
Outputs
tTlH'
tTHl
Minimum Clock Pulse
Width
Clock Rise and Fall Time
tWl, tWH
trCl, tfCl
10
-
-
-
ns
ns
15
/.Is
Set UpTime:
DATA
tSlH' tSHl
OPCODE
Data Hold Time
tDh
5
10
5
10
5
10
-
ns
ns
ns
Maximum Clock Frequency:
Count Mode
fCl
5
10
0.13
0.46.
0.36
1.35
Shift Mode
fCl
5
10
0.33
1.4
0.90
3.8
-
5
Input Capacitance
CI
ANY INPUT
-
MHz
pF
Limits with black dot ,e) designate 100% testing. Refer to RIC·l02C "High-Reliability COS/MOS CD4000A Slash (f) Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
*'
Tests are either several inputs or several outputs.
619
CD4057A Slash (II Series _ _ _ _---'_ _ _ _ _ _ _ _ _ _ _ _ _ _ __
LOGIC DESCRIPTION
OPERATIONAL MODES
The CD4057 A arithmetic logic unit operates in one of four
possible modes. These modes control the transfer of inform~tion, either serial data or arithmetic operation carries, to
and from the serial·data lines. Fig. 3 shows the manner in
which the four modes control the data on the serial·data
lines.
Examples of how one "hard·wired" combination of three
ALU's can form (a) a 12-bit parallel processor, (b) one B-bit
and one 4·bit parallel processor, or (c) three 4·bit parallel
processors, merely by changes in the modes of each ALU
are shown in Fig. 4.
.. ~
..~
r--------,
.,.",
IVSs
MODE 0
VSS 1 RIGHT
~
~J~ :
: ~J:
~
LEFT
L
-----lByPAss-~
r--
LEFT
---
--...,
~s: RIGHT
~OATA
~ ~~
__________
LINE
DATA _
LINE
!
J
c.~
.~
92CS-20254
Fig.4 - UMode" connectiDns for parallel
plOC8SS0r:
BYPASS
r--------,
LEFT
File No. 849
fa) 12-bit unit.
:~RIGHT
(b) one 8."it and one 4.JJit unit
fe) three 4-bit units.
DATA~~~OATA
LINE
~
LINE
L_________
BYPASS
,...---------,
LEFT
:V~S:
RIGHT
DATA~DATA
LINE
L__________ J
LINE
92CS-20252RI
BYPASS
Data·flow interruptions are shown by shaded areas. With
these three ··ALU's and the four available modes, 61 more
system combinations can be fo.med. If 4· ALU's are used,
44 combinations (256) are possible.
Fig.3 - Schematic of uMode" concept.
In MODE 0, data can enter or leave from either the left or
the right serial·data line.
In MODE 1, data can enter or leave only on the left serial·
data line;
NOTE: The BYPASS terminal of the "most significant"
CD4057 A is connected to the bypass terminal of the "least
significant" CD4057 A. The bypass terminals on all other
CD4057 A's are left floating. This interconnection is per·
formed whenever more than one CD4057 A are used to form
a processor.
In MODE 2, data can enter or leave only on the right serial·
data line.
In MODE 3, serial data can neither enter nor leave the regis'
ter, regardless of the nature of the operation.
Furthermore, the register is by-passed electri·
cally, i.e., there is an electrical bidirectional
path between the right and left serial data
terminals.
The two input lines labeled C1 and C2 in the terminal assign·
ment diagram define one of four possible modes shown in
Table 1.
Through the use of mode control, individual arithinetic arrays
can be cascaded to form one large processor or many processors of various lengths.
TABLE I - MODE DEFINITION
620
C2
Cl
0
0
1
1
0
1
0
1
MODE
0
1
2
3
INSTRUCTION REPERTOIRE
Four encoded lines are used to represent 16 instructions.
Encoded instructions are as follows:
abc d
o0 0 0
000 1
00 1 0
00 1 1
000
o 0 1
o
o
0
1 000
o0 1
o10
o1 1
00
o1
1 0
1 1
NO·OP (Operational Inhibit)
AND
Count down
Count up
Subtract Stored number from zero (SMZ)
Subtract from paraliel data lines (SM)
(stored number from paraliel data lines)
Add (AD)
Subtract (SUB) (Parallel data lines from stored
number)
.
Set to all ones (SET)
Clear to all zeroes (CLEAR)
Exclusive·OR
OR
Input Data (From parallel data lines)
Left shift
Right shift
Rotate (cycle) right
All instructions ar executed on the positive edge of the clock.
File No, 849 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4057A Slash (/) Series
CONDITIONAL OPERATION
Inhibition of the clock pulse can be accomplished with a
programmed NO-OP instruction or through conditional input
terminals A, B, and C. In a system of many CD4057A's, each
CD4057A can be made to automatically control its own
operation or the operation of any other CD4057 A in the
system in conjunction with the Overflow, Zero, or Negative
(Number) indicators. Table II, the conditional-inputs truth
table, defines the interactions among A, B, and C.
TABLE II - CONDITIONAL-INPUTS TRUTH TABLE
sum or difference is one's complemented and stored in the
most-significant-bit position of the register.
The overflow flip-flop is updated at the same time the new
result is stored in the CD4057A. Whenever data on the
parallel-data lines are loaded into the CD4057 A, whatever is
on the Overflow 1/0 line is loaded into the overflow flip-flop.
Also, whenever data are dumped on the parallel data lines
from the CD4057 A, the contents of the overflow flip-flop are
dumped on the Overflow 1/0 line. Thus ov~rflows may be
stored elsewhere and then fed into the CD4057 A at another
time.
OPERATION
A
B
C
0
X
X
Ves
1
0
0
Ves
1
0
1
No
1
I
0
No
1
1
1
Ves
PERMITTED
OPERATIONAL SEQUENCE AND WAVEFORMS FOR
X = don't care
PROPAGATION-DELAV MEASUREMENTS
1. DATA IN-to-CARRV OUT and DATA IN-to-SUM OUT
Two examples of how the conditional operation can be
used are as follows:
1) For the Multiplication Algorithm
A.
B.
C.
D.
E_
F.
Apply Word A and IN instruction
Apply Clock to load word A into register
Apply AD instruction
Apply Word B (data in)
Apply Clock to load result (,urn out)
Apply DATA OUT CONTROL to look at result
A = I, for step 7 (1)
A = 0, for step 7 (2)
B=l
C = negative Indicator
2)
For the Division Algorithm
A= l,for step 7 (1)
A = 0, for step 7 (2)
8=1
C = Co (left data line)
A
0
I
I
INPUT
:j~:t i l=r--
INPUT
c
INPUT
I
I
I
I
I
i
INPUT d
I
OVERFLOW DETECTION
The CD4057A is capable of detecting and indicating the
presence or absence of an arithmetic two's-complement
overflow. A two's-complement overflow is defined as having
occurred if the signs of the two initial words are the same
and the sign of the result is different while performing a
carry-ge,nerating instruction.
DATA OUT CONTROL
DATA I"
-
DATA 2"
-
DATA 3~
-
0.011
For example:
(+) ~
1.001
Overflows can be detected and indicated only during
operation in Mode 2 or Mode 3 and can occur for only four
instructions (AD, SMZ, SM, and SUB). If an overflow is
detected and stored in the overflow flip-flop, anyone of the
five instructions AD, SMZ, SM, SUB, or IN can change the
overflow indicator.
When any of the three subtraction instructions is used, the
sign bit of the data being subtracted is complemented and
this value is used as one of the two initial signs to detect
overflows. If an overflow has occurred. the final sign of the
~
--,
,
I
'----
I
i
I-~
CARRY OUT
CD DATA IN
® CARRY OUT
® SUM OUT
CD - ® DATA IN TO CARRY OUT
CD - ® DATA IN TO SUM OUT
'-L
,I
'-----
I
CLOCK
i
-
n
r-L---r
tl
II
SOLID LINE REPRESENTS INPUT
FROM EXTERIOR SOURCE WHEN
"DATA OUT" IS LOW. DASHED LINES
REPRESENT OUTPUT WHEN "DATA
OlIT" IS HIGH
92C5-21878
Fig. 5 - DATA IN-to-CARRY OUT and DATA IN-to-SUM OUT.
621
CD4057 A Slash
II) Series
File No. 849
2. CARRY IN-to-CARRY OUT and CARRY IN-to-SUM OUT
PoB.
C.
D.
E.
F.
G.
AMBIENT TEMPERATURE IT.)0:25°C
TYPICAL TEMP. COEFFICIENT
Apply Word A and IN instruction
Apply Clock to load word A into register
Apply AD instruction
Apply Word B
Apply CARRY IN (carry in)
Apply Clock to load result (sum out)
Apply DATA OUT CONTROL to look at result
'"~ 1500
z
~
F G
+j
~
INPUT a
INPUT
b
INPUT
c
"0.3 % -C
AT ALL VALUES OF V
500
25
50
75
100
LOAD CAPACITANCE (CLI-pF
92CS-21881
--t--,---'
+-+-___
INPUT d _ _' -_ _-
Fig.
8~
Transition timevs.loadcapacitance for Data Outputs (D1-04).
_ _.;.-.-_ _
DATA OUT CONTROL
f--I-JH-----
CLOCK PULSE RISE AND FALL TIMES
Voo
L
DATA 2*
QATA
?l--t--t-----!
DATA 4*
92CS-21872
CLOCK
Fig. 9-Clock Pulse Rise and Fall Times.
CARRY IN
CARRY OUT --'--t----t--+~
CD CARRY IN
® CARRY OUT
@
'II
SUM OUT
CD -@CARRY IN TO CARRY OUT
CD -@CARRY IN TO SUM OUT
fVOO
SOLID LINE REPRESENTS INPUT
FROM EXTERIOR SOURCE WHEN
'bATA OUT" 15 LOW. DASHED LINES
REPRESENT OUTPUT WHEN "DATA
OUT" IS HIGH
- - _ _ _ 50%
92C5-21879
Fig. 6 - CARRY IN·to-CARRY OUT and CARRY IN·to·SUM OUT.
-----------50%
AMBIENT TEMPERATURE (TA) =25°C
COUNT !,IP MODE
92CS-21873
15
Fig. 10 - Data setup time.
>
I
"C
~
...,'"
10
.
!:;
§!
f
~
~
C_L_O_C_K_"___
r-----VDD
SO %
DATA OUT"
CONTROL
o
0.25
0.5
Q75
1.25
1.5
1.75
2.25
MAX. COUNTING FREQUENCY IfM)-MHz
92CS-218BO
Fig.7 - Max. counting frequency vs. supply voltage
for a typical CD4057A.
622
Fig.1';-Dataholdtime.
File No. 849
CD4057 A Slash (I) Series
~SCOPE
..
OUTPUT
OUTPUT
NIC
6.
7
2B
NIC
27
26
OUTPUT
IOV
25
GNO
24
23
NIC
CD4057A 22
21
8 (TOP VIEW)
10
v
9
10
NIC
Nle
GNO
Nle
14
20
19
tpo IDJ -Col + JrpD lel-col- 790nl
I
013·16
Ipo I~ - Col + 21PO ICI- COli cPO lei-Sol = 92Snl
513·16
IOV
GNO
GNO
CLOCK IN
I
~
n
09·12
59·12
10V
IB
OUTPUT
12
17
13
16
NIC
NIC
15
GNO
IpO
m
1S0 os
!t>r. - Col + IpO ICI - Col - 440 n.
I
os 8
SS·8
TERM 20
tpo 101 - Col· IpO ICI- co,. IpO ICI - Sol
IpO 101 - Col + tpo ICI _ SOl. S7S ns
IpOIOz.-col = 26Sns
CLOCK IN
TERM I
fl2
01.4
1 51·4
IpoIOr- SoJ"'J7Sns
TERM 3
fl4
Vss
Fig. 13- Typicalspeedcharacteristicsofa 16·birALUat VOO= 10 V.
'----_---'I
TERM 7
fiB
'"6 _________
TERM 2
.J
PARALLEL DATA I
2B
PARALLEL DATA 4
27
DATA 2
26
PARALLEL
NOTE:
I. CONNECT DEVICE AS SHOWN ABOVE, APPLY SIGNAL GENERATOR
INPUT TO TERMINAL 20 - f=0.5 MHz, t r • tf" 20 ns,O AND 10 VOLTS.
2. CONNECT SCOPE FIRST TO TERMINAL I, THEN TO 3, 7 AND 2
FOR PROPER COUNT AND OPERAT rON.
NEGATIVE INDICATOR
25
Zl INPUT
24
INPUT
92CS- 24977
Fig. 12 - Dynamic test'circuit and waveforms
(maximum frequency).
c
INPUT d
7
CONDITIONAL INPUT A
C04057A
(TOP VIEwl
CONDITIONAL INPUT C
TYPICAL APPLICATION
The CD4057 A has been designed for use as a parallel processor in flexible, programmable, easily expandable, special
or general purpose computers, where minimization of external connections and data busing are primary design goals.
The block diagram of Fig. 15 is an example of a computer
that processes 8 bits in parallel.
RIGHT SERIAL DATA
LINE
BYPASS
NC
MODE-CONTROL INPUT
LINE CI
•• I
•• 2
PARALLEL DATA 3
*VOO
*VSS
23
ZERO INDICATOR
OUTPUT
"DATA OUT "CONTROL
22
INPUT a
2 I
INPUT
20
CLOCK
b
10
19
CONDITIONAL INPUT B
"
IB
LEFT SERIAL DATA LINE
12
17
OVERFLOW INDICATOR
13
16
OvERFLOW
14
15
MODE-CONTROL INPUT
LINE C2
110
* NOTE: NON-STANDARD
',ERMINAL LOCATIONS FOR
VSS AND VOD' MOST OTHER COS/MOS TYPES
USE CORNER TERMINALS FOR POWERSUPPLY CONNECTIONS
92C5-20253
Fig. 14'- Terminal assignments.
C04Q34A
INPUT-OUTPUT
EXTERNAL
DATA
REGISTER
92CM-21882
Fig. 15- Example of Computer Organization Using C04057A.
623
File No. 850
[Jl(]3LJD
Digital Integrated Circuits
Solid State
Division
High-Reliability Slash (I) Series
CD4060Al...
Monolithic Silicon
High-Reliability
COS/MOS 14-Stage Ripple-Carry
Binary Counter/Divider and Oscillator
For Logic Systems Applications in Aerospace,
Military, and Critical Industrial Equipment
Features:
92CS-23762RI
CD4060A Functional Diagram
a 4·MHz operating frequency (typ.) at VOO-VSS = 10 V
II Common reset
• Fully static operation
• 10 buffered outputs available
The RCA·C04060A Slash (I) Series consists of an oscillator
section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC or crystal
oscillator circuits_ A RESET input is provided which resets
the counter to the all-D's state and disables the oscillator.
A high level on the RESET line accomplishes the reset
function. All counter stages are master-slave flip-flops. The
state of the counter is advanced one step in binary order on the
negative transition of <1>[(<1>01. All inputs and outputs are
fully buffered_
Oscillator Features:
a All active components on chip
• RC or crystal oscillator configuration
Applications:
• Timers
D
Frequency dividers
ose'L~ATOR
These devices are electrically and mechanically identical with
standard COS/MOS CD4060A types described in data bulletin
813 and DATABOOK SSD-203 Series, but are specially processed and tested to meet the electrical, mechanical, and
environmental test methods and procedures established for
microelectronic devices in MI L-STD-883.
The packaged types in the CD4060A "Slash" (I) Series can be
supplied to six screening levels - I1N, I1R, 11, 12./3,14which correspond to MIL-STD-883 Classes "A", "B", and
"C". The chip versions of these types can be supplied to
three screening levels - 1M, IN, and IR.
For a description of these screening levels and for detailed
information on test methods procedures, and test sequence
employed with high-reliability COSIMOS devices refer to
High-Reliability Report RIC-l02C, "High-Reliability COSI
MaS CD4000A "Slash" II) Series Types".
l
STAGE I
624
INPUTS
TO 2 nd
• R=HIGH DOMINATES (RESETS ALL STAGES)
.. COUNTER ADVANCES ONE BINARY COUNT
ON EACH NEGATIVE -GOING TRANSITION
The CD4060A "Slash" (I) Series types are supplied in 16-lead
dual-in-line ceramic packages ("D" suffix), in 16-lead ceramic
flat packages ("K" suffix), or in chip form ("H" suffix)_
o£\
OJ
OF ~I(AND
I/J o)
"55
INPUT PROTECTION
CIRCUIT ON ALL
INPUTS
92CS-23763Rl
Fig. 1-Logic diagram of CD4060A oscillator, pulse shapero
and 1 of 14 counter stages.
9-74
File No. 850 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4060A Slash (I) Series
~o
o,*"--_____-'O::S:::GI:::LL::A:.:T.::OR.:....:::IN:::V::ERc:.:Tc::E::RS=--_ _---,
~ 0..::*------------1
~Ocr*------------+-+------~-~~,
+----+~
INPUT
PULSE
SHAPER
* STANDARD
ALL INPUTS PROTECTED BY
caS/MOS PROTECTION
NETWORK
~o--------,
4
Vss
OUTPUT BUFFER,
STAGES 4-10, 12-14
'-----4-----+---------------+.--+-----+ QI TO ¢ 2ND STAGE
ATRANSMISSION GATLE-SU-.-S-TR-A-T-E--------------......-
...
Qi
TO
4)
2NQSTAGE
CONNECTIONS: p-TYPE TO Vao. n-TYPE TO Vss
92CM-245~3
Fig. 2-Schematic diagram of input pulse shapers, reset buffers, and 1 of 14
binary counter stages of the CD4060A.
625
CD4060A Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 850
STATIC ELECTRICAL CHARACTERISTICS (All inpu1S .•.•.•....••.••.•.•.••••.•••.••..•..•••. VSS1 to Q4 Out
Propagation Delay
Time. Q n to Qn+1
Tr~nsition
Time
Min. Input·Pulse Width
5
-
200
400
10
-
75
110
tr<1>'
5
-
-
tl<1>
10
-
-
tWL·
1=100kHz
tWH
Input·Pulse
Rise & Fall Time
Max. Input·Pulse
Frequency
Input Capacitance
I",
ns
ns
ns
15
7.5
I-IS
-
5
1·
10
30
4
-
-
5
-
II
1.75
ns
MHz
pF
Reset Operation
Propagation Delay
Time
tpHL
Minimum Reset
Pulse Width
tWH
5
-
500
1000·
10
-
250
500-
5
-
500
10000
10
-
250
500·
ns
ns
Limits with black dot (0) designate 100% testing. Refer to RIC-l02C "High-Reliability COS/MOS C04000A Slash (t) Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
*
Tests are either several inputs or several outputs.
MAXIMUM RATINGS. Absolute·Maximum Values:
STORAGE·TEMPERATURE RANGE.
OPERATING-TEMPERATURE RANGE
OC SUPPLY·VOLTAGE RANGE:
(VOo-V SS )' . . . . .•••.... •. . . . . .• .
OEVICE DISSIPATION (PER PACKAGE)
ALL INPUTS...........................
-65 to +150o C
-55 to +12SoC
-0.5 to +15 V
. . . . . . .. 200 mW
VSSl
-~u'?'?..j
~o
_
-
:\~,
150
0
I-
I
J
~
100
w
g
I
50
---20
40
60
LOAD CAPACITANCE (eL) -
80
pF
t
10
15
SUPPLY VOLTAGE (VOO) -
20
V
92C5-24556
Fig. 7 - Typical output transition time vs. load capacitance.
628
Fig. 8 - Typical maximum-input·pulse frequency vs. supply voltage.
File No. 850 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4060A Slash (I) Series
5VORIOV
~
~
10'
~
10'
rf
10'
~
IS
~
~
ill
10'
5
'"
~
10
r
LOAD CAPACITANCE (CL}215pF
- - - - CL ~50pF
4.5 V OR 9,5 V
IF OUTPUT
10
10 2
10 3
INPUT FREQUENCY U.)-kHz
HIGH
92C5-24560
92CS-21S15Rl
Fig. 9 - Typical dynamic power dissipation characteristics.
Fig. 10 -Output drive current rest circuit.
10 V
TEST PERFORMED
WITH UNIT IN All
,.
AND INPUTS AT 10 V
"13
12
ISf------+
il'(ilr.~TS\::J>
AND GROUND
5VORIOV
IS
15
"13
"
10
92C5-24562
. Fig. 7t-Quiescent device current test circuit.
16
15
5VORIOV
I.
13
o-Q35VOR 7V
92CS-24563
Fig. 12 -Input-pulse noise Immunity rest circuit.
TERMINAL ASSIGNMENT
CD4060A
012
013
01'
06
05
07
O.
V55
I.
2
3
5
6
IS
15
I.
13
12
"
10
9
Voo
010
OB
09
R
.'
~o
·0
(TOP VIEW)
Fig. 13-Reser-pulse noise immunity test circuit.
92CS-23761RI
629
File No. 842
rnrnoo
Digital Integrated Circuits
Monolithic Silicon
Solid State
Division
I.
•
AO
15
AI
AZ
*
vDD*
V••
S
CD4QGIA
13
12
A.
A4
NC
CHIP ENABLE
WRITE/READ
DATA
"
•
High-Reliability Slash (I) Series
CD4061A1•••
OUT
DATA OUT
DATA IN
A7
10
A.
AS
92CS-21526
High-Reliability
COS/MOS 256-Word by 1-Bit
Static Random-Access Memory
For Logic Systems Applications in Aerospace,
Military, and Critical Industrial Equipment
Features:
• Low standby power: 10 Nanowatts/bit (typ.) @VDD= 10 V
• Access time: 380 ns (max.) @ VDD = 10 V
• Single 3-to·15 V power supply
• Noise immunity: 45% of VDD (typ.)
• Fully decoded addressing
• COS/MOS input/output logic. compatibility
• TTL output drive capability
• Single write/read control line
The RCA·CD4061 A "Slash" (II Series are single monolithic
integrated circuits containing a 256·word by l·bit fully static,
random·access, NDRO memory. The memory is fully decoded
and requires 8 address input lines (Ao - A7) to select one of
256 storage locations. Additional connections are provided for
a WRITE/READ command CHIP ENABLE, DATA IN, and
DATA OUT and DATA OUT lines.
To perform READ and WRITE operations the CHIP·ENABLE
signal must be low. When the CHIP·ENABLE signal is high,
read and write operations are inhibited and the output is a high
impedance. To change addresses, the CHlp·ENABLE signal
must be returned to a high level, regardless of the logic level of
theWRITE/READ input. In a multiple package application, the
CHIP·ENABLE signal may be used to permit the selection of
individual packages.
Output·voltage levels appear on the outputs only when the
CHlp·ENABLE and WRITE/READ signals are both low.
Separate data inputs and outputs are provided; they may be
tied together; or, to eliminate interaction between READ and
WRITE functions, may be used separately. The circuit ar·
rangement permits the outputs from many arravs to be tied to
a common bus.
• Three-state data outputs for bus-oriented systems
• 1101·type pin designations*
• Separate data output and data input lines
The packaged types can be supplied to five screening levels
11 R, 11,/2,/3,/4 - which correspond to MIL·STD·883 Classes.
"A", "B", and "C". The chip versions of these types can be
supplied to two screening levels - 1M and /R.
For a description of these screening levels and for detailed
information on test methods, procedures, and test sequence
employed with high·reliability COS/MOS devices refer to
High·Reliability Report RIC·102C, "High·Reliability COSI
MOS CD4000A "Slash" (II Series Types':
The CD4061 A "Slash" (II Series types are supplied in l6·lead
dual·in·line side-brazed ceramic packages ("0" suffix) or in
chip form ("H" suffix).
MAXIMUM RATINGS. Absolute-Maximum Values:
STORAGE·TEMPERATURE RANGE .•.•••••.••• -65 to +150 °c
OPERATlNG·TEMPERATURE RANGE .••.•••••• -65 to +125 °c
All input and output lines are buffered. The CD4061 A output
buffers are capable of direct interfacing with TTL devices.
OC SUPPL Y·VOLTAGE RANGE
IV OD - VSSI •......•••.•••••••.••.•.••••. -0.5 to +15 V
DEVICE DISSIPATION IPER PKG.I. •• ••• .•. . .• .•••. .• 200 mW
These devices are electrically and mechanically identical with
standard COS/MOS CD4061 A types described in data bulletin
715B and DATABOOK 550·203 Series, but are specially pro·
cessed and tested to meet the electrical, mechanical, and
environmental test methods and procedures established for
microelectronic devices in MI L-STD·883.
ALL INPUTS ....•...•.••.•••••••..••••..... VSS ';;VI';;V DD
RECOMMENDED DC SUPPLY VOLTAGE
IVDD-VSSI •.•.....••..••.•.....••......••.
LEAD TEMPERATURE lOURING SOLDERINGI
At distance 1/16 ±i/32 inch 11.59 :10.79 mml
from case for 10 seconds max. . • . . . • . . .• .•. . .•••• •..
3to15V
266°C
• The pin designations are compatible with other static 266-Bit memories and are, therefore, not compatible with standard COS/MOS
C04000A-5eries devices: i.e. VOO is pin 6 and VSS is pin 4.
630
9·74
File No. 842 _ _ _ _ _ _ _ _- - - - - - - - - - - - - - CD4061A Slash (II Series
-I
AO
CE
A
0
0
AI
A2
R
vfs"
E
5
5
z
~I
1
z
'OJ"
3
8 ~ 8
;!:
~
A,
-'
-'
~
6
u
.!l~!
;!:
~
-'
-'
~
u
!!!
!!!
~
z
~
'"
"
*
0
~
K
~
K
SYMBOL REPRESENTS
THREE-STATE INVERTER
K~I.
NORMAL
K-O, HIGH IMPEDANCE
FOR SINGLE n AND
P
I~
FROM
Y DECODE
!
>-----------.rt
vss
1
iii
12
.,
''""
l..'"
CE
O ....'VIIV--+.-GATE
t;
0
DATA IN
I
I
I
I
Il.-"v~s
FROM
X DECODE
VOO
I ....,
..... ,
NC--@
DATA BUS __ COMMON TO 16 COLUMNS
voo----0
-
vss---0
I.
DATA BUS __ COMMON TO 16 COLUMNS
L.- _ _ _ _ _ _ _ _ _
-----.J
256 -BIT STORAGE ARRAY
DEVICES) ALL p-5UBSTRATES TIED TO Voo·
lALL n-SUBSTRATES TIED TO Vss.
92CL-23852
Fig. , - CD4061 A logic diagram.
CD4D61A OPERATIONAL MODES
OPERATION
Write "0"
ADDRESS LINES
CHIP-ENABLE
WRITE/READ
Write "'"
Read
*ReadlWrite
Stable
Stable
Stable
Stable
0
0
0
0
1
1
0
0/1
Address Change
Changing
1
X
DATA IN
0
1
X
X
X
DATA OUTPUTS
High-I mpedance
High-I mpedance
Valid' or 0
Valid 1 or O/HighImpedance
High-I mpedance
X = Don't Care
* For a READIWRITE operation on the same address, chip.enable may be held to a logic 0 for both successive
operations.
631
CD4061A Slash(/) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 842
STATIC ELECTRICAL CHARACTERISTICS (All inputs .................................... vss';; vI';; VOO)
(Recommended DC Supply Voltage (VOO - VSS) ............ 3 to 15 V)
CHARACTERISTIC
TEST
SYMBOL CONDITIONS
Vo
Volts
Quiescent Device
Current 1
Quiescent Device
Dissipation/Package
IL
PD
VOL
10
-
5
10-
5
-
-
-
10
-
-
-
10
Threshold Voltage 2
N·Channel
P·Channel
Noise Immunity3
(All Inputs)
Output Drive Current: 4
(Data Out, Data Out)
P·Channel (Source)
Output Off Resistance 4
(High·lmpedance State)
Diode Test 3
100 p.A Test Pin
0.01
-
0
0,01
-
0.05
0
0.5-
-
0.55-
0,01
-33-
-0.7-
-1.5 -3- -0.3-
0.7-
1.5
0.5
2.5
4.6
9.5
p.W
0
14.5-
0.4
750
2000
-
-
10
p.A
-
-
9
150
200-
0.01
15
5
VDF
0.5-
Max.
0.55-
10
1.5
3-
Ro(Off)
-
-
5
10
IDP
25
100
9.99
0.8
IDN
0.6
2.5
4.99
0.7-
N·Channel (Sink)
-
-
ID = -20p.A ~0.7-
VNH
0.25 10-·
4.99
ID=20p.A
4.2
-
9.99
VTHP
1
5
5
2.25-
VTHN
VNL
Typ. Max. Min.
0.12
10
3
VOH
125°C
-
15
High·Level
Min.
-
5
Low· Level
25°C
5
3
Output Voltage 5 ,6
UNITS
LIMITS
_55°C
VOO
Max.
Volts Min.
2.3-
-
-
-
-
3-
4.95
9.95
14.45-
-
0.05
-
-3-
0.3-
3-
-
1.5-
2.25
-
1.4
-
3-
4.5
-
1.5-
2.25
2.9-
-
3-
4.5
-
2.9-
1.4
-
1.5
3-
-
4.5
2
-
1.6-
2.5
10
4.3
-
3.5-
5
5
-1.1
-
-0.9-
-1.8
5
-0.5
-
-0.4-
-0.8
10
-1.1
-
-0.9-
-1.8
5
5
10
-
10-
-
10
10
-
10-
-
-
-
1.5-
-
-
1.5-
V
1.1
-
2.4
-
-0.65
-
V
V
rnA
-0.3
-
Mn
10
-
1:5-
V
-0.65
10
rnA
Limits with black dot (e) designate 100% testing. Refer to RIC·102C "High-Reliability COS/MOS CD4000A Slash (f) Series Types", Tables
2 through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1: Functional test, all inputs and outputs.
Note 2: Test is either a one input or a one output only.
Note 4: Tests on all outputs.
Note 5: Functional GAL PAT test for 5 volts at 800 kHz and 10 volts at 2 MHz.
Note 3: Test on all inputs and outputs.
Note 6: Functional MARCH test for 3 volts at 250 kHz and 15 volts at 2 MHz.
632
File No. 842 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4061A Slash
= 50 pF, and t r , If = 20 ns
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C, VSS = 0 V, CL
CHARACTERISTICS
SYMBOLS
TEST CONDITIONs&
Voo
(Volts)
w
-'
w
-'
w
a:
==
1000
450
-
ns
0
-
ns
-
ns
ns
Max.*
Chip·Enable Pulse Width
tCE
Chip·Enable Setup Time
5
460·
-
tCES
10
200 0
-
-
Read Access Time
tRA
5
10
-
-
450
250
750
380
5
10
40·
5
700·
500
10
350·
250
0°'
Write Cycle Time
twc
5
10
1200·
550·
Chip-Enable Hold Time
tCEH
5
10
40 0
00
Chip-Enable Pulse Width
tCE
5
10
700
350
Chip-Enable Setup Time
tCES
5
10
460 0
200 0
Write Hold Time
tWH
Write Pulse Width
tw
Data Setu p Ti me
tos
Data Hold Time
>
CJ
I-
Typ.
1200·
550·
tCEH
CJ
5
LIMITS
Read Cycle Time
10
5
0
-
0
-
-
500
250
-
-
-
100
5
150·
100
10
100·
70
80
140
80
tOH
5
10
25 0
20·
5
tTLH
10
5
-
tTHL
10
trCE.
5
10
15
-
tfCE
1000
450
70
5
Input Rise and
Fall Time
0
10
Output Transition Time
Chip-Enable
150
100
0
-
~
10
(II Series
35
0
-
-
60
100
-
50
75
35
60
25
40
-
-
-
ns
-
-
-
0
ns
-
10
10
0
15
5
ns
IlS
1
* See "Symbol Definitions"
Limits with black dot (el designate 100% testing. Refer to RIC-l02C "High-Reliability COS/MOS CD4000A Slash U) Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
6. Tests are on all inputs and outputs.
633
CD4061A Slash (fI Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 842
0) READ-CYCLE WAVEFORMS
W/R-LOGIC-o-
____ "'\
ADDRESS
tRC
DAtA IN- DON'T CARE
r _________ tr -·,-20"s
-------<'"
~'--·----------------.II'------~~:.LE
I-- teEH--'I!o----- teE - - - -..~
L ......l__teEH - ~
I"----------J-,
.~'-_ _ _ __
tCES
DATA OUT
b) WRITE-CYCLE WAVEFORMS
---,
ADDRESS
----J
CHIP
ENABLE
'_ _ _ _ _ _ _ _ twe
_________ J
-teEH
WRITE/READ
Y
1-
teE
tCES
r----------tCEH--A
tw
-twH-----:
I
DATA IN
f-tDS---
Q.
NOTE: CHIP ENABLE MUST 8E HIGH DURING AN ADDRESS CHANGE
92CM-238S'
Fig. 2 - Typical write-read waveforms.
SYMBOL DEFINITIONS
READ CYCLE
operating frequency for the memory, with minimum write
cycle time equal to tCEH (min.) + tCE (min.) + tCES (min.).
tRC - READ CYCLE TIME - Time required between address
changes during a read cycle. Minimum read cycle time is equal
to tCEH (min.\ + tCE (min.\ + tCES (min.\. (See Definitions
below\.
teEH - CHIP·ENABLE HOLD TIME - See Definition under
read cycle.
teEH - CHlp·ENABLE HOLD TIME - Time required before
chip-enable level can be lowered after an address transition.
teE - CHIP·ENABLE PULSI: WIDTH - See Definition under
read cycle.
tCE - CHlp·ENABLE PULSE WIDTH - Time required for the
chip to be active for valid reading of output data.
teES - CHIP·ENABLE SETUP TIME - See Definition under
read read cycle.
teES - CHlp·ENABLE SETUP TIME - Time required before
ar address transition can take place after chip·enable level has
been increased. tCES(min.\ + tCEH(min.\ is the minimum time
required to discharge internal nodes and allow settling of ad·
dress decoders during an address transition. Chip·enable level
must be raised during each address change. even if read cycles
only or write cycles only are successively performed. However,
if address is not changed, chip enable may remain in its active
(low) state during successive read and write cycles.
twH - WRITE HOLD TIME - Measured from chip-enable
transition; time required before negative transition of write
pulse can occur for successful write operation.
tRA - READ ACCESS TIME - Measured from chip-enable
transition; time before output data is valid.
WRITE CYCLE
twc - WRITE CYCLE TIME - Time required between ad·
dress changes during a write cycle. This time sets the maximum
634
tw - WRITE PULSE WIDTH - Time required for W/R pulse to
be high. Note that no specification for positive transition of
this pulse is made - it may occur before or after the chip·
enable transition. In many applications, the W/R control is
normally low and is strobed high during a write cycle.
tDS - DATA SETUP TIME - Measured from write·pulse
negative transition; time required for data input to be valid.
tDH - DATA HOLD TIME - Measured from write·pulse
negative transition; time required for data input to be valid
after W/R is returned to a low level. The minimum data pulse
width is equal to tDS (min.) + tDH (min.).
File No. 842 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4061 A Slash (II Series
AMBIENT TEMPERATURE ITA'-2SoC
TYPICAL TEMPERATURE COEFFICIENT IS -O.3%'OC
AT ALL VALUES OF VGS
DRAIN-TO-SOURCE VOLTAGE (VOS)-V
_ -
-
. MAXIMUM AVERAGE
PKG. DISSIPATION (200 mW)
50
mn-
~ttl-:
-15
-5
-10
AMBIENT TEMPERATURE (TA)-25-C
TYPICAL TEMPERATURE COEFFICIENT
IS -0.3%'·C,AT ALL VALUES OF VGS
0
-2.5
GATE-fO-SOURCE VOLTAGE
(VGSI-15 V
if,
-5
~
-7.5
!
!e
10V
30
-'
..i3
'"zz
20
~
10
•I
0<
5V
10V
.
z
1-
B
A""B
CASCADING
INPUTS
r
lA8
A'"e
A B) and three cas·
cading inputs (A < B, A ~ B, A > B) that permit systems
designers to expand the comparator function to 8, 12, 16 .. AN
bits. When a single CD4063B is used, the cascading inputs are
connected as follows: (A < BI ~ low, (A ~ B) ~ high, (A> B) ~
low.
significant comparator. Cascading inputs (A < B, A
~
B, and
A > B) on the least significant comparator are connected to a
low, a high, and a low level, respectively.
All outputs have equal source- and sink-current capabilities and
conform to standard B-series output drive (see Static Electrical Characteristics).
These devices are electrically and mechanically identical with
standard COS/MaS CD4063B types described in data bulletin
805 and DATABOOK SSD·203 Series, but are specially pro·
TRUTH TABLE
INPUTS
COMPARING
A3, B3
A2, B2
AO, BO
AB
A B3
A3 ~ B3
A3 ~ B3
A3 ~ B3
X
X
X
X
X
X
a
A2> B2
A2 ~ B2
A2 ~ B2
X
X
X
X
X
0
A1 >B1
A1 ~ B1
X
X
X
X
a
0
AO>BO
X
X
X
0
A2
A2
A2
~
B2
B2
B2
A1
A1
A1
~
AO
AO
AO
BO
BO
BO
a
a
a
1
1
0
a
a
~
B1
B1
B1
a
a
1
a
0
1
A2
A2
~
B2
B2
A1
~
B1
AO< BO
X
X
X
X
X
X
X
1
1
1
1
A3
~
B3
A3
A3
~
B3
B3
A3
A3
A3
~
~
~
~
B3
B3
B3
x
~
~
~
A1, B1
~
A1 B
a
a
1
1
1
1
1
0
0
a
0
a
1
a
a
a
a
a
a
0" Low State
9·74
File No. 852 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4063B Slash (II Series
cessed and tested to meet the electrical. mechanical, and
environmental test methods and procedures established for
microelectronic devices in MIL-STO-883.
For a description of these screening levels and for detailed
information on test methods, procedures, and test sequence
employed with high-reliability COS/MaS devices refer to
High-Reliability Report RIC-l02C, "High-Reliability COS/
MaS CD4000A "Slash" (/) Series Types'~
The packaged types can be supplied to six screening levels -
lIN, I1R, 11, 12, 13, 14 - which correspond to MIL·STO·.883
Classes "A", "S", and "C", The chip versions of these types
can be supplied to three screening levels - 1M, IN, and IA.
The C04063B "Slash" (I) Series types are supplied in 16-lead
dual-in·line ceramic packages ("0" suffix). in 16-lead ceramic
flat packages ("K" suffix). or in chip form ("H" suffix).
STATIC ELECTRICAL CHARACTERISTICS
CHARACTERISTIC
SYMBOL
TEST CONDITIONS
V
Min.
Max.
Min.
5
-
S
-
0.02
5
-
300-
10
10°
0.02
10°
-
-
0.02
-
-
200-
15
-
3
5
-
-
0.50.01
0.05
0.01
-
O.S-
-
0.55-
-
-
-
IL
VOL
10
15
3
High-Level
Threshold Voltage 2
N-Channel
P·Channel
VOH
-
-
-
2.3-
a
a
a
0.05
4.99
-
4.99
5
-
4.95
-
-
9.99
10
9.95
15
-
-
14.5°
15
-
-
-3-
-0.7-
-1.5 -3- -0.3°
VTHP
10 = 20llA
0.7°
3°
0.7°
1.5
-
5
1.5
1
10
3°
1.5
15
-
4.2
5
104
9
10
2.90
Noise Immunity'
13.5 15
-
3°
0.3-
-3-
1.5-
2.25
-
1.4
-
4.5
-
2.9-
-
-
6.75
2.25
1.5
-
3-
-
6.75
-
-
1.5°
-
-
3-
0.8
-
0.3
1.8
-
0.65
6
-1.3
-
4.5
004
5
0.5
-
0.4-
0.5
10
1.1
-
0.9 0
1.5
15
-
3
-1.6° -3.2
-
-004- -0.8
-
-0.3
-0.65
ION
lOP
VOF
Input Current
II
V
rnA
2.5
5
-1.8
4.6
5
-O.S
.-
9.5
10
-1.1
-
-0.9°
-1.8
-
-
-
-3
-6
-
-
1.5-
-
-
1.5°
-
-
-
13.5 15
Diode Test 3
100 IlA Test Pin
V
3-
3-
-
V
-
9.99
14.45-
Il A
-
5
-0.7-
VNH
Max.
10
10=-20IlA
0.8
P·Channel
(Source)
2.25-
0.01
-
0.55°
0.01
Typ. Max. Min.
VTHN
VNL
Output Drive Current: 2
N-Channel
(Sink)
12So C
V
Output Voltage: 1
Low-Leuel
UNITS
2So C
VDe
Quiescent Device 1
Current
LIMITS
_SSOC
Vo
-
15
±1O-5 ±1
-
-
-
-
1.5-
-
-
rnA
V
IlA
Limits with black dot (_, designate 100% testing. Refer to RIC·l02C "High·Reliability COS/MOS CD400QA Slash III Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1: Complete functional test all inputs and outputs to truth table.
Note 2: Test is either a one input or a one output only.
Note 3: Test on aU inputs and outputs.
645
CD4063B Slash (/) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 852
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25 0 C. Input t r • tt = 20 ns. and CL = 50 pF
TEST CONDITIONS*
CHARACTERISTIC
SYMBOL
Propagation Delay Time:
Comparing Inputs to
Outputs
Cascading I nputs to
Outputs
LIMITS
UNITS
VDD
Volts
Typ.
Max.
tpHL·
tpLH
5
10
15
625
250
175
1250·
500·
-
tpHL·
tpLH
5
10
15
500
200
140
1000·
400·
-
5
10
15
100
50
40
200·
100·
tTHL
Transition Time
tTLH
Average Input Capacitance
Any Input
CI
ns
ns
80
-
5
pF
Limits with black dot (e) designate 100% testing. Refer to RIC·l02C "High-Reliability COS/MOS CD4000A Slash (f) Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
*
T~~ts are either several inputs or several outputs.
MAXIMUM RATINGS. Absolute·Maximum Values:
STORAGE·TEMPERATURE RANGE.
-65 to +150 o C
OPERATING·TEMPERATURE RANGE
-55 to +12SoC
DC SUPPLY·VOLTAGE RANGE
V DD • ................. .
. ... -0.5 to +18 V
DEVICE DISSIPATION (PER PACKAGE) ...
200 mW
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm)
from case for 10 seconds max. . ..
• All voltage values are referenced to
Vss
B3
(AB)IN
(A>B)OUT
(A"Bl oUT
(ABIIN~A>Bli-1
,~A
,
BI
,
AI
ALL INPUTS PROTECTED
BY THE STANDARD
COS/MOS PROTECTION
NETWORK
Bo
I
AO
'
~~
I
VSS
*
I
'_
~~~~ -
!
- _______ -
I
-___I
92CM-2l823
Fig. 3- Logic diagram CD4063B.
92CM-23824
tp TOTAL'" tp
(f~p~~RE)
+ 2 x Ip
(f:pS~:~E). AT CL = 15 pF (each outpull. VOO '" lOV
13 STAGES)
=
250 + 2 x (200) '" 650 ns (TYP.,
Fig. 4- Typical speed characteristics of a 12-bit comparator.
647
\
CD4063B Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 852
!
AMBIENT TEMPERATURE (TA)· 2S"C
LOAD CAPACITANCE tCl) " 50 pF
700 AMBIENT TEMPERATURE (TAl" 2S"C
UPPlY VOLTAGElVOOlc5V
600
0500
~
3
~.. 500
~ 1250
1
1...
...'"2
400
1<
.00
z
200
2
OOV
~
0
i.
~
05V
0000
5l!l
750
is
500
!;;
~
000
00
250
~
20
40
50
60
70
LOAD CAPACI TANCE ttt.) - pF
30
80
90
2.5
100
7.S
10
12.5
15
17.5
20
SUPPLY VOLTAGE (Vao I-V
92C5-24517
92C5-24518
Fig. 6- Typical propagation delay time ..s. supply voltage
(licomparing inputs" to outputs).
Fig. 5- Typical propagation delay time vs. load capacitance.
~Z:.Z
10: IAMBIENT TEMPERATURE (TA)=2S"C
4
./'
,s~~
2
t
I
00'
•
~
il"~
4
z
2
Q
lr
~
<><0
4
2
00
<-""
"ov
2
I
o,r
,f]
q~
/
,R
•
4"- -
2
-rrIi".,r.Y.
468
r
2
4 68 ro 2
FREQUENCY
LOAD CAPACITANCE (CL)-pF
~,
~~
•
iii
#~
."~~%~., ..,0
"
~ 10'
"~
V/
468,022
4681032
468'04
tf) - kHz
'J2CS-24519
92CS-24322
Fig. 7- Typical transition time
VS.
Fig. 8-Typical dynamic power dissipation characteristics.
load capacitance.
VDD
06
05
14
.
02
"
00
9
92C5-24521
92CS-24'22
Fig. 9-Quiescent del/ice current test circuit.
Fig. 1D-No;$e immunity test circuit.
92CS-24520
Fig. 1 1-Dynamic power dissipation test circuit.
648
File No. 853 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
D\lC18LlO
Digital Integrated Circuits
Solid State
High-Reliability Slash (I) Series
CD4066A/...
Monolithic Silicon
Division
High-Reliability
.COS/MOS Quad Bilateral Switch
INIOUT 1
51G A
For Logic Systems Applications in Aerospace,
Military, and Critical Industrial Equipment
SIG B
IN/OUT
51G 0
Special Features:
a 15-V digital or ± 7.5-V peak·to-peak switching
9 QUTIIN
SIG C
B INIOUT
92:CS-21627
" soon typical ON resistance for 15·V operation
.. Switch ON resistance matched to within 5 n over 15-V
signal-input range
a ON resistance flat over full peak·to-peak signal range
The RCA-CD4066A Slash (/) Series is a quad bilateral switch
intended for the transmission or mUltiplexing of analog or digital signals. It is pin-far-pin compatible with RCA-CD4016A,
but exhibits much lower ON resistance_ In addition, ON resistance is relatively constant over the full input-signal range.
The CD4066A consists of four independent bilateral switches.
A single control signal is required per switch. Both the p and
the n device in a given switch are biased ON or OFF simul·
taneously by the control signal. As shown in Fig. 1, the well of
the n-channel device on each switch is either tied to the input
when the switch is ON or to VSS when the switch is OFF.
This configuration minimizes the variation of the switchtransistor threshold voltage with input signal, and thus keeps
the ON resistance low over the full operating·signal range.
The advantages over single·channel switches include peak
input·signal voltage swings equal to the full supply voltage,
and more constB;nt ON impedance over the input-signal range.
For sample·and·hold applications, however, the CD4016A
a High ONIOF F output·voltage ratio: 65 dB typo
@fis= 10 kHz, RL = 10 kn
.. High degree of linearity:
< 0.5% distortion tyP.@tis=1
kHz
Vis = 5 Vp.p, VDO-VSS;;' 10 V, RL = 10 kn
a Extremely low OFF switch leakage resulting in very low
offset current and high effective OFF resistance:
10 pA typo @VDD-VSS= 10 V, TA = 250 C
" Extremely high control input impedance (control circuit
isolated from signal circuid: 1012 n typo
II
Low crosstalk between switches:
-50 dB typo @ fis = 0.9 MHz, R L = 1 kn
II
Matched control-input to signal-output capacitance:
Reduces output signal transients
II
Frequency response, switch ON = 40 MHz (tyP.)
is recommended.
CONTROL_ _- ,
____
-I,,~
~
IN
Applications:
NORMAL OPERATION
CONTROL-LINE BIASING:
SWITCH ON,V(:"I".VOD
SWITCH OFF, Vc "0" aVss
• Analog signal switching/multiplexing
Modulator
Signal gating
Demodulator
Squelch control
Chopper
Com mutating switch
II Digital signal switching/Multiplexing
• Transmission-gate logic implementation
Fig. 1 :... Schematic diagram of 1 of 4 identical switches and its
associated control circuitry.
9-74
• Analog-to-digital & digital-to·analog conversion
II Digital control of frequency, impedance, phase, and
analog-signal gain
649
CD4066A Slash (I) Series--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 853
These devices are electrically and mechanically identical with
standard COSIMOS C04066A types described in data bulletin
769 and OATABOOK SSO·203 Series, but are specially
processed and tested to meet the electrical, mechanical, and
environmental test methods and procedures established for
microelectronic devices in MIL-sT0-883.
The packaged types in the C04066A ''Slash'' (I) Series can be
supplied to six screening levels - I1N, 11R, II, 12,/3,/4which correspond to MIL-STO·883 Classes "A", "B", and
"C". The chip versions of these types can be supplied to
three screening levels -1M, IN, and IR.
For 8 description of these screening levels and for detai/eo
information on test methods, procedures, and test sequence
employed with high-reliabllity COS/MaS devices refer to
"High·Reliability Report RIC·102C "High·Reliability COSI
MaS CD4000A "Slash" (/J Series Types'~
The C04066A ''Slash'' (I) Series types are supplied in 14·lead
dual·in·line ceramic packages ("0" suffix), in 14·lead ceramic
flat packages ("K" suffix), or in chip form ("H" suffix).
STATIC ELECTRICAL CHARACTERISTICS, All Inputs ........ '" ............................ Vss <; VI <; VOO
Recommended DC Supply Voltage (VDO-VSS)' • . . • . • • . • •• . •. 3 to 15 V
TEST CONDITIONS
CHARACTERISTIC
Vo VDO
SYMBOL
V
Quiescent Device
V
LIMITS
-550 C
Min. Max.
250 C
Min. Tyl" Max.
1250 C
Min. Max.
10
-
0.5-
-
-
0.5-
-
loe
15
-
1-
-
-
-
10
-
0.5-
-
-
1-
lOoe
loe
0.55-
-
-
Current
All Switches OFF·
All Switches ON'"
IL
0.5-
UNITS
pA
-
pA
Output Voltage 1
L"Ow·Level
VOL
3
15
-
High·Level
VOH
3
15
2.28"
Threshold Voltage2
N·Channel
P·Channel
Noise Immunity 1
VTHN
ID = -20j.lA
VTHP
ID=20j.lA
VNL
(Any Input)
VNH
Diode Test3
100 pA Test Pin
0.5
TERMINALS
1
5,6,12,13
4.5
9
-
-
-0.7-
-3-
a-
10
0.71
2
5
10
4
8
-
-
1.5-
5
VDF
VOLTS
TERMINALS APPLIED
VSS
Vc
VIS
VOS
7
5,6,12,13
1.4,8,11
2,3,9,10
GND
GND
<;;+ 10
<;;+ 10
2.a13.9-
-0.7- -1.5
0.71-
1.5
0.51.1-
-
-
-
1.1-
-
13.ge
-
-3-
-0.3-
-a-
a-
O.a-
a-
-
-
-
-
9
1.8
-
3.8
7.8
-
se
-
-
-
1.5-
-
1.5-
~
4-
V
V
V
V
VOLTS
'"
TERMINALS
7
VSS
5,6,12,13
Vc
VIS =VOS 1.4,8,11
~
GND
+10
<;;+ 10 (Thru
lOOn)
Limits with black dot (e) designate 100% testing. Refer to RIC-102C "High-Reliability COS/MOS C04000A Slash (0 Series Types:: Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1: Complete functional test, all inputs and outputs to truth table.
Note 2: Test is either a one input or a one output only.
650
Note 3: Test on all inputs and outputs.
File No. 853
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4066A Slash (I) Series
SPECIAL CONSIDERATIONS - CD4066A
MAXIMUM RATINGS, Absolute-Maximum Values:
STORAGE TEMPERATURE RANGE
-65°C to +1500 C
OPERATING TEMPERATURE RANGE
-55°C to +125 0 C
DISSIPATION PER PACKAGE
200 mW
DC SUPPLY VOLTAGES:
Voo-Vss; VOO-VEE·
.
-0.5 to +15 V
ALL SIGNAL AND DIGITAL CONTROL INPUTS
VSS';;; VI ';;;VDD
MINIMUM RECOMMENDED POWER SUPPLY VOLTAGES
VDD-VSS; VDD-VEE·
•
.
.
3V
•
LEAD TEMPERATURE lOURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm)
from case for 10 seconds max.. . . . .
.
1. In applications wtlere separate power sources are used to
drive VDD and the signal inputs, the VDD current capability should exceed VDD/RL (RL = effective external
load of the 4 CD4066A bilateral switches)' This provision
avoids any permanent current flow or clamp action on the
VDD supply when power is applied or removed from
CD4066A.
2. I n certain applications, the external load-resistor current
may include both VOO and signal·line components. To
avoid drawing VDD current when switch current flows
into terminals 1, 4, 8, or 11, the voltage drop across the
bidirectional switch must not exceed 0.8 volt (calculated
from RON values shown).
No VDD current will flow through R L if the switch current
flows into terminals 2, 3, 9, or 10. Failure to observe this
condition may result in distortion of the signal.
ELECTRICAL CHARACTERISTICS, All Inputs .•...•................................. VSS';; VI';; VDD
Recommended DC Supply Voltage (VDD-VSS) . . . . . . . . . . . . . .. 3 to 15 V
CHARACTERISTIC
SYMBOL
I
I
TEST CONOITIONS
LIMITS
·5S o C
Typ. Max.
12SoC
25°C
I Typ. I
Max.
Typ.
Max.
UNITS
I
SIGNAL INPUTS IVis) AND OUTPUTS IVasl
VC=Voo
Vis
VSS
-7.5 V
+7.5 V
-7.5 V
to
+7.5 V
0
ON
Resistance
RON
RL=10kH
+15 V
OV
.5 V
-5 V
+10 V
OV
t2.5 V
2.5 V
10
60
2200
80
2800
145
3200
85
4000
120
5000
190
5500
160 30000
270
50000
360
55000
+15 V
-5 V
to
'5 V
010
II
tl0V
- 2.5 V
to
+2.5 V
OV
Oto
.5 V
- 7.5 V
+7.5 to -7.5
'5 V
t
.10N Resistance
Between Any 2
of 4.switches
7.5 V
DC
£\RON
RL=10kH
OV
t15toOV
-5 V
+5V to-5V
t15 V
.5 V
DC
Sine Wave Response
(Distortion)
Input or Output
Leakage-Switch OFF
(Effective OFF
Resistance)
RL = 10 kH
= 1 kHz
'"
VOO
OV
i10VtoOV
'0 V
-0 V
5 V(p.p)A
~
VSS
+7.5 V
-7.5 V
'0 V
-5 V
-
-
-
10
-
-
-
OA
-
-
-
-
±200*
-
0
-
II
+10 V
Vc
-
~
-
*
.!.7.5 V
-
±100
±SV
-
±100* ±a.Ol
til. 1
*
:t100
!100*
%
*
±200
nA
*
Limit determined by minimum feasible leakage measurement for automatic testing .
..... Symmetrical about 0 volts.
Limits with black dot (e) designate 100% testing. Refer to RIC~102C "High·Reliability COS/MOS CD4000A Slash (/) Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
651
CD4066A Slash (II S e r i e s - - - - - -_ _ _ _ _ _ _ _ _ _ _~--ELECTRICAL CHARACTERISTICS (All inputs . • • • • • • • • • • • •
(Recommended ec Supply Voltage (Vee-Vssl
File No. 853
• • VSS .;; VI .;; Vee)
3to 15V)
LIMITS
CHARACTERISTIC
SYMBOL
TEST CONOITIONS
1--.,:5;,:5:,.0..:C+:-::-.,..:2:::5:,.0..:C,,::--II':25::o-0..:C,-! UNITS
Min.
Min. Typ.
Max. Min.
VC=VOO=+5V VSS=-5V
Frequency ResponseSwitch ON
°v:;Vos
RL::: 1 kfl
(Sine Wave Input)
20 l091
Vis;.5 V (pop)
Voo = +5 V, Vc ::: Vss
Feedthrough
=
Vis (A) =
(Frequency at -50 dB
5 V Ip·p)
-+__C..;.IS'--I
Capacitance _In_p_"_,_ _
1.25
MHz
0.9
MHz
VclA!" VDD - +5V
VCIB) , VSS ' -5 V
RL:: 1 Kn
Crosstalk Between any 2
of the 4 switches
MHz
-5 V
20 LaglO v~s = -50 dB
V"
Switch OFF
40
= -3 dB
VoslSI
-50 dB
VisIA):::
20 laglO
Voo::: +5 V. Vc = VSS
=
8
-5 V
Output
COS
8
Feedthrough
elOS
0.5
Propagation Delay·
Signal Input to
Signal Output
Vc - VOO::: +10 V. VSS - GND. CL::: 15 pF
Vis = 10 V (square wave)
10
pF
20e
ns
tr '" tf ::: 20 ns (input signa II
ControllVcl
Noise Immunity
4.5
Input Current
±lO
V
pF
Average Input Capacitance
VOD VSS-l0V
Crosstalk
Control Input to
Signal Output
50
Vc - 10V.
Propagation Delays·
(square wavel
tre '" tfc '" 20 ns
RL - 300n
Vis ~ 10V, CL = 15 pF
VDD -10V. VSS - GND. RL
Maximum Allowable
Control Input
Repetition Rate
35
mV
90e
1 kn
CL'15pf
VC'" 10 V (square wave)
t '" tf '" 20 ns
10
MHz
... Test is a one input or one output only.
Limits with black dot (e) designate 100% testing. Refer to RIC-102C "High-Reliability COS/MOS CD4000A Slash (II Series Types", Tables
2 through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
3~0 AMBIENT TEMPERATURE
Io
~
(TA)-25°C
SUPPLY VOLTAGE
Voo-Vssl" 5V
I
~
f
250
"
200
..
150
i3
!il
~
'"w
'"z
z
0
...
..15
0
10V
100
200
150
100
50
50
o
·0
-8
-6
-8
-4
-2
0
2
4
SIGNAL VOLTAGE (Vl s) - VOLTS
92CS-23913
Fig.2 (a) - Typical channel ON resistance vs. signal voltage for
three values of supply voltage (VOD-VSS).
652
250
15V
w
z
z
AMBIENT TEMPERATUR
ITA1·125°C
w
w
z
~
350 SUPPLY VOLTAGE
(Voo-VSS}·5V
o 300
I
300
-6
-4
-2
a
2
4
SIGNAL VOLTAGE (Vl s ) -VOLTS
92CS-23914
Fig.2 (b) - Typical channel ON resistance vs. signal voltage
with supply voltage (VOO-VSS) = 5 V.
File No. 853 - - - - - - - - - - - - - - - - - - - - - - - -
.,
350
'"
SUPPLY VOLTAGE (Voo-VSS);IOV _
:Ii
I
Z
~2!50
~ 250
w
~
z 200
~
u
z
AMBIENT TEMPERATURE
.,w~
(TAl. J2S"C
150
'"z
z
0
0
100
g
200
AMBIENT TEMPERATURE
150
ITAl"25'C
.,.j.4.j H-
-IH·
100
J
. °ft+
~5rr
_
W
Z
z
~ 50
u
pr-
SUPPLY VOLTAGE (Voo-VSS).15V
o 300
I
~
(II Series
350
~
~ 300
CD4066A Slash
~
a
-8
-6
-4
a
-2
50
- S5
IH
a
2
-B
-6
-4
-2
0
2.
4
SIGNAL VOL TAGE:IV~s) - VOL T5
SIGNAL VOLTAGE (Vi.sl -VOLTS
92CS-23915
Fig.2 (e) - Typical channel ON resistance vs. signal voltage
with supply voltage fVDD-VSS)
92CS-23916
Fig.2 (d) - Typical channel ON resistance vs. signal voltage
with supply voltage (VDD-VSS) = 15
= 10 V.
v.
H.P.
x-v
'-__-+____+--lPLOTTER
MOSELEY
7030A
92CS-22716
Fig.3 - Channel ON resistance measurement circuit.
INPUT SIGNAL VOLTAGE
Nul - VOLTS
92CS-23917
FigA - Typical ON charactE:ristics for 1 of 4 channels.
TEST CIRCUITS
Cios
r----'i------.
:. VC"-5V
~
CAPACITANCE BRIDGE
MODEL 75A (IMHz)
TEST FIXTURE CAPACITANCE
I NULLED OUT
I
I
I
I
I
Cis:t:
I
MEASURED ON BOONTOI')!
Voo =+5V :
VSS·-5V
V55
ALL UNUSED TERMINALS
ARE CONNECTED TO Vss.
*cos
I
~
92CS-2391B
Fig.5 - Capacitance.
92CS-23919
Fig.6 - OFF switch input or output leakage
653
CD4066A Slash (II Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No" 853
TEST CIRCUITS (Cont"d)
+IOV~
tr-'t
-20,,11
IOkSl
ALL UNUSED TERMINALS
ARE CONNECTED TO vss.
ALL UNUSED INPUTS ARE CONNECTED TO VSS.
92C5-23921
92t5-23920
Fig.8 - Crosstalk-control input to signal output.
Fig.7 - Propagation delay time signa/Input (V'S) to
signal output (Vas).
RATE
~
p.
Vc
',·',-20"s
~OS90~-1
IO%:
+IOV~
I
20
-0
"~~~
.,-.,-20ns
+IO~
3004
Vc
t r ·t,-20ns
ALL UNUSED TERMINALS ARE CONNECTED TO Vss.
Ok"
92C5-23922
ALL UNUSED INPUTS ARE CONNECTED TO Vss.
tpLH~
Flg.9 - Propagation delay
92CS-25923
tpHL contro/-signal output.
Fig. fa
-
Maximum allowable control input repetition rate.
10. AMBIENT TEMPERATURE (TA)a25·C
r-
~
~
~
ANALOG INPUTS
6
4
•
~.,.,,, /
••, - - - 1-- ..,>f>~.?- ,0"
~?......
~./'
10'
0:
z
0
2
~
2i0
10'
15
4
V
••
/'
./
...
/~'-
""
~1·• =
CO,OSSA
2
10
1,/
10
-
"..
~~7 VSS
...............
'~"
(± 5 v)
..............
\",OQ
4
~
I
... v
/
68,02
2
SWITCHING FREQUENCY (f)-kHz
.
I
ANALOG OUTPUTS (i5 Vl
9:lCS-216t4
92c5-23924
Fig. t 1 - Power diuipation per package
654
tiS switching
frequency.
Fig. 12 - Bidirectional signal transmission Ilia digital control logic.
File No. 843 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
OU(]3LlD
Digital Integrated Circuits
Monolithic Silicon
Solid State
Division
High-Reliability Slash (I) Series
CD4068B/•..
High-Reliability
COS/MOS 8-lnput NAND Gate
For Logic Systems Applications in Aerospace,
Military, and Critical Industrial Equipment
Features:
VOO·14
~
Vss .7
92CS-2'lB74
~
Medium·Speed Operation - tpHL = 130 ns. tpLH = 100 ns (typ.) at 10 V
Standard B·Series Output Drive
CD4068B Functional Diagram
The RCA·CD4068B "Slash" (I) Series NAND gates provide the
system designer with direct implementation of the positive·
logic 8·input NAND function and supplement the existing
family of COS/MOS gates. These devices have equal source· and
sink-current capabilities and conform to standard B-series output drive (see Static Electrical Characteristics).
These devices are electrically and mechanically identical with
standard COS/MOS C04068B types described in data bulletin
809 and OATABOOK SSO·203 Series, but are specially pro·
cessed and tested to meet the electrical, mechanical, and
environmental test methods and procedures established for
microelectronic devices in MIL-STO·883.
The packaged types can be supplied to six screening levels -
11N,/1R,/l,/2,/3,/4 - which correspond to MIL·STO·883
Classes "A", "B",and "C". Thechip versions of these types can
be supplied to three screening levels -/M,/N, and IR.
The C04068B "Slash" (I) Series types are supplied in 14·lead
dual·in·line ceramic packages ("0" suffix), in 14·lead ceramic
flat packages ("K" suffix), or in chip form ("H" suffix).
MAXIMUM RATINGS. Absolute·Maximum Values:
STORAGE·TEMPERATURE RANGE ............. -66 to +150 0 C
OPERATING·TEMPERATURE RANGE ........... -55 to +125 o C
DC SUPPLY·VOLTAGE RANGE
Voo * ................................... -0.5 to +18 V
DEVICE DISSIPATION (PER PACKAGEI .... . .. . ... . .. 200 mW
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm)
from case for 10 seconds max. ................... 265 0 C
• All voltage values are referenced to VSS terminal.
OPERATING CONDITIONS AT TA = 25 0 C
For maximum reliability. nominal operating conditions should be
selected so that operation is always within the fol/owing ranges.
Characteristic
SuppiV Voltage Range
For a description of these screening levels and for detailed
information on
employed with
High·Reliability
MOS CD4000A
9·74
test methods, procedures, and test sequence
high·reliability COSIMOS devices refer to
Report RIC·l02C, "High·Reliability COSI
"Slash" II) Series Types".
I nput Voltage Swing
(Recommended VSS to V OO )
Voo
Min.
Max.
3
18
0.2 V DD -0.5 V
to
Units Fig.
V
V
to
0.8 V DD V DD +
(Anyone
input)
0.5 V
655
CD4068B Slash III Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 843
STATIC ELECTRICAL CHARACTERISTICS
CHARACTERISTIC
SYMBOL
TEST CONDITIONS
V
V
Min.
Max.
. Min.
5
10
-
0.5
15
-
-
Output Voltage:'
Low· Level
3
5
-
High· Level
Threshold Voltage 2
N·Channel
P·Channel
IL
VOL
VOH
-
Typ. Max. Min.
0.01
0.5
0.01
1-
-
20-
-
-
0.05
0.55-
0.01
-
-
0
10
-
0.01
-
0
0.01
-
15
-
-
-
0
0.5-
-
-
-
-
4.99
5
-
4.95
-
9.99
10
9.95
14.5-
15
-
-
3
2.25-
5
4.99
10
9.99
15
-
-
2.3-
14.45-
-0.7-
-3-
-0.7-
-1.5 -3- -0.3-
Vi"HP
ID=20J1A
0.7-
3-
0.7-
1.5
6.75 2.25 -
3-
2.25
104
-
2.9-
-
1.5
-
1.5-
3-
3-
13.5 15
-
-
5
1.4
-
1.5-
-
3-
-
6.75
004-
O.B
-
0.9-
1.B
-
0.65
6
-
1
10
2.9-
1.5
15
-
004
4.5
0.5
0.5
10
1.1
-
1.5
15
-
-
3
4.5
2.5
5
-2
4.6
5
-0.5
.-
-0.4-
-O.B
9.5
10
-1.1
-
-0.9-
-l.B
-
-
-
-3
-6
-
-
1.5-
-
-
1.5-
-
-
-
13.5 15
Diode Test 3
100 J1A Test Pin
VDF
Input Current
II
1.5
3-
V
V
-
-
-
0.3
mA
IDN
IDP
-
V
-3-
4.5
5
10
-
0.05
3-
9
J1A
-
0.3-
4.2
O.B
30
0.50.01
ID = -20J1A
VNH
Max.
0.550.01
Noise Immunity'
P·Channel
ISource)
1-
125°C
V1HN
VNL
Output Drive Current: 2
N·Channel
ISink)
UNITS
25°C
YDD
Quiescent Device1
Current
LIMITS
_55°C
Vo
-
15
-1.6- -3.2
±10- 5 ±1
-1.15
-
-0.3
-
-0.65
-
-
-
-
1.5-
-
-
mA
V
J1A
Limits with black dot (el designate 100% testing. Refer to RIC·l02C "High-Reliability COS/MOS CD4OQOA Slash (I) Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1; Complete functional test,all inputs and outputs to truth table.
Note 2: Test is either a one input or a one output only.
656
Note 3: Test on all inputs and outputs.
File No.843 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4068B Slash (I) Series
DYNAMIC ELECTRICAL CHARACTERISTICS at TA
=25°C.
Input tr.lf
=20 ns, and CL =50 pF
LIMITS
TEST CONDITIONS*
CHARACTERISTIC
SYMBOL
VDD
Volts
5
Propagation Delay Time:
Max.
tpHL
10
15
325
130
100
650·
260·
-
ns
tpLH
5
10
15
250
100
75
500·
200
-
ns
5
10
15
100
50
40
200·
100·
High-to-Low Level
Low-to-High Level
UNITS
Typ.
tTHL
Transition Time
tTLH
Average Input Capacitance
Any Input
GI
5
ns
80
-
pF
limits with black dot (01 designate 100% testing. Refer to RIC-1 02C "High-Reliability COS/MOS CD4000A Slash (I) Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
*
Tests are either several inputs or several outputs .
• 3
*
VDD
C 4 "
d, ,
HH
D. "
)---®J
:f :1'
* STANDARD
ALL INPUTS PROTECTED
COS/Mas
"
~r
J=ABCDEFGH
LOGIC I. HIGH
LOGIC a-LOW
BY
PROTECTION NETWORK
F IO}-------__~----_+------~
V OO ·14
Vss~
H
*"
I~------
7
________________~
9~CM-23a75RI
vss
Fig. 1-CD40688 schematic diagram.
657
CD4068B Slash
II)
Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 843
.
,.
~
MAX.
I
~
!
~
...
_MIN.
>
AMBIENT TEMPERATURE ITA );2S·C
15
;: 12.5
~
_
10
10
GAT~-TO-SOURCE
B
VOLTAGE (VGs)-15V
>
.
10 V
0~
0-
S
5V
o
10
10
DRAIN-TO-SOURCE VOLTAGE (V051-V
15
INPUT VOLTAGE I":I)-V
92CS-24512
Fig.2-Min. and max. voltage transfer characteristics.
Fig,3-Minimum output-N-channel drain characteristics.
DRAIN-TO-SOURCE VOLTAGE IVosl-V
-15
-10
-5
AMBIENT TEMPERATURE (T A 1-2S-C
GATE-TO-SOURCE VOLTAGE
IVGS)~-
5V
10V
z
-10
~
-15
I
-15V
~
LOAD CAPACITANCE {Cl)-pF
92CS-24573
92CS-24321
Fig.4-Minimum output-P-channel drain characteristics.
Fig.5- Typical high-to-Iow level propagation delay
time vs. load capacitance.
AMBIENT TEMPERATURE (TA)=25°C
i
.,.
1000
0-
~
i'i
750
500
!i
:
~
92CS-24574
tPLH
tPHL
250
10
I~
SUPPLY VOLTAGE (Voo)-V
20
92CS-24S15
Fig.6- Typicallow-ro-high lellel propagation delay
time
658
10'5.
load capacitance.
Fig.7- Typical propagation delay time vs. supply voltage.
File No. 843 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD4068B Slash (I) Series
10' AMBIENT TEMPERATURE ITA)- 25-C
..
i>
1.0
.
z
i:iQ
....,'"
~
,"Q~"~
,
,,4
,0
'\..(:,~
10'
0
i
i-f-
10'
~
~~~fi'"
1<1
..'"
1/
/1/
CL·~pF
/
CL-15pF -
'..I'
'0 '
10°
10 1
10°
FREQUENCY (f) -
LOAD CAPACITANCE tCL)-pF
10 2
kHz
92CS·24322
Fig.8- Typical transition time vs. load capacitance.
Fig.9- Typical power dissipation
VI.
frequency.
VDD
vDD
VOO-VNH
b
Y
VHl
13
"
12
TEST
"
10
9
8
92CS-24~77
92CS-24~76
Fig. 7 '-Noise immunity test circuit.
Fig.lo-Ouiescent del/ice current rest circuit.
TERMINAL ASSIGNMENT
CD4068B
NC
I.
2
3
I.
13
12
VDD
JaA·8·C·D·[·F·G·H
"
10
NC
NC
VSS
(TOP VIEWI
92CS-24578
659
_ _ _-,-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 854
OOCD3Ll[]
Digital Integrated Circuits
Solid State
High-Reliability Slash(l) Series
CD4069B/ ••.
Monolithic Silicon
Division
-'---{>o--!- G
a..L..(>o-i-H
A
C~I
D..L.(::>o-!L J
EJ.L{>oJ2-K
F~L
92CS-23737RI
CD4069B FUNCTIONAL DIAGRAM
High-Reliability
COS/MOS Hex Inverter
For Logic Systems Applications in Aerospace,
Military, and Critical Industrial Equipment
Features:
• Medium Speed Operation - tpHl' tplH = 40 ns Ityp.) at 10 V
• Standard B·Series Output Drive
Applications:
• Logic inversion
• Pulse shaping
• Oscillators
• High·input·impedance amplifiers
The RCA·CD4069B Slash II) Series consists of six COS/MOS
inverter circuits. All outputs have equal source and sink
current capabilities and conform to the standard B-series
output drive Isee Static Electrical Characteristics).
This device is intended for all general·purpose inverter appli·
cations where the medium·power TTL·drive and logic·level·
conversion capabilities of circuits such as the CD4009A and
CD4049A Hex Inverter/Buffers are not required.
MAXIMUM RATINGS, Absolute·Maximum Values:
STORAGE·TEMPERATURE RANGE. , .. , , ....... -66 to +1500 C
OPERATING·TEMPERATURE RANGE ........... -55 to+1250C
DC SUPPLY·VOLTAGE RANGE
V DO •...... , ....... , , ... , , , ..... , , .• , . ,. -0.5 to +18 V
DEVICE DISSIPATION (PER PACKAGE) .. ,........ ... 200 mW
ALL INPUTS ............................ Vss";; VI ..;; V DD
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch 11.59 ± 0.79 mm)
from case for 10 seconds max. ...................
These devices are electrically and mechanically identical with
standard COS/MOS CD4069B types described in data bulletin
804 and DATABOOK SSD·203 Series, but are specially pro·
cessed and tested to meet the electrical, mechanical, and
environmental test methods and procedures established for
microelectronic devices in MIL·STD·883.
The packaged types in the C04069B "Slash"lI) Series can be
supplied to six screening levels-/1 N, /1 R, /1, 12, /3, 14which correspond to MIL·STD·883 Classes "A", "B", and
"C". The chip versions of these types can be supplied to
three screening levels-/M,/N, and IR.
For a description of these screening levels and' for detailed
information on test methods, procedures, and test sequence
employed with high·reliability COS/MaS devices refer to
High·Reliability Report RIC·l02C, "High·Reliability COS/MaS
CD4000A "Slash" (/) Series Types".
The CD4069B "Slash"lI) Series types are supplied in 14·lead
dual-in-line ceramic packages ("0" suffix), in 14-lead ceramic
flat packages I"K" suffix). or in chip form I"H" suffix),
• All voltage values are referenced to
266°C
Vss terminal.
OPERATING CONDITIONS AT TA = 2S0C
For maximum reliability, nominal operating conditions should be
selected so that operation is always within the following ranges
V OD
Min.
Max.
Supply Voltage Range
-
3
18
Input Voltage Swing
(Recommended VSS to V OO )
-
Characteristic
Acr~~JV~
0.2 V DD -0.5 V
to
to
0.8 V DD V DD +
(Anyone 0.5 V
inputl
Units Fig.
V
V
-
__~-'~
1(3,5,9,II,t31
Vss
Fig. I-Schematic diagram of one of six identical inverters.
660
9·74
File No. 854 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4069B Slash(/) Series
STATIC ELECTRICAL CHARACTERISTICS
CHARACTERISTIC
SYMBOL
TEST
CONOITIONS
Vo
V
0.01
0.5
-
30
1-
0.01
1-
-
20-
-
-
-
0.01
-
-
-
0.55-
10
-
0.01
15
-
-
-
3
5
Low· Level
High·Level
Threshold Voltage
N·Channel
P·Channel
VOL
VOH
Diode Test 3
100 p.A Test Pin
Input Current
2.3-
-
-
0.05
0
0.01
0
0.5-
-
0.55-
-
-
-
-
4.95
-
4.99
5
9.99
-
9.99
10
15
-
-
14.5-
15
-0.7-
-3-
14.458
9.95
-1.5
-3-
-0.3-
-3-
3-
0.7-
1.5
3-
0.3·
3-
-
5
1.5
-
1.5·
2.25
-
104
7.2
10
3-
3-
4.5
15
-
-
6.75
104
5
1.4
1.5-
2.25
-
2.9-
10.8
-
2.8
10
2.9-
-
3-
4.5
4.2
15
-
-
-
6.75
-
3-
004-
0.8
0.9-
1.8
-
0.65
6
-
-
-
-3.2
-
-1.15
-
-0.4-
-0.8
-
-0.3
-
-0.9-
-1.8
-
-0.65
-
-
-
-
1.5-
-
1.5D
±1
-
-
0.4
5
0.5
0.5
10
1.1
-
1.5
15
-
-
2.5
5
-2
-
-1.6-
3
4.6
5
-0.5
-
9.5
10
-1.1
-
13.5
15
-
-
-3
-6
-
1.5-
-
-
-
-
-
15
1.5
±10-5
0.3
UNITS
p.A
0.05
-
3.6
VOF
II
-
0.01
4.99
-0.7°
lOP
0.5-
5
0.7-
ION
0
10
10 = -20p.A
Output Orive 2
Current:
P·Channel
(Source)
-
10=20p.A
VNH
N·Channel
(Sink)
2.25-
VTHP
Noise Immunity 1
0.01
3
VTHN
VNL
Max.
125D C
Min.
Max.
-
15
Output Voltage 1
Min.
25 D C
Typ.
0.5
10
IL
-55 DC
Min.
Max.
-
5
Quiescent Device 1
Current
Voo
V
LIMITS
V
V
V
rnA
V
p.A
limits with black dot 1_) designate 100% testing. Refer to RIC·102C "High-Reliability COS/MOS CD4QOOA Slash (f) Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1: Complete functional test, all inputs and outputs to truth table.
Note 2: Test is either a one input or a one output only.
Note 3: Test on all inputs and outputs.
661
CD4069B Slash(/) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 854
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 250 C. Input t r• tt = 20 ns. and CL = 50 pF
TEST CONDITIONS'
CHARACTERISTIC
SYMBOL
Propagation Delay Time:
LIMITS
VDD
Volts
UNITS
Typ.
Max.
tpHL.
tpLH
5
10
15
65
40
30
125·
80·
tTHL'
tTLH
5
10
15
100
50
40
200·
100·
80
Transition Time
Average Input Capacitance
Any Input
CI
ns
ns
-
5
pF
Limits with black dot 1_) designate 100% testing. Refer to RIC~102C "High-Reliability COS/MOS CD4000A Slash (f).Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
*Note: Test is a one input, one output only.
17.5 AMBIENT TEMPtRATURE (TA I
hTT
IE
25°C
+++++++ j
17.5
1TTTTTT.lJ..LI
15
SUPPLY VOLTAGE (V
) =ISV
I
----MIN.
10
~
g
7.5
~
t>l
I!
..J
o
10
0
> 7.5
..55
~t-'5V
5
v
t+
'0
MAX. -
10V
~
= 15
\-H+f~tt++~~~IIE~~I~EIMlp~~~+~RE (TAl" +l2S·C
>
I 12.S
12..
~
SUPPLY VOL.TAGE (Voo)
15
>
5
10V
!±L+I25°C
-5S'"C
5V
0
125·C
-5S·C
2.'
2."
2."
o
7.5
10
12.5
15
17.5
20
22.5
o
7.5
10
12.5
15
INPUT VOLTAGE (VI'-V
2.5
INPUT VOLTAGE (V:r1-V
17.S
20
92CS-24432
92CS-24431
Fig. 3- Typical voltage transfer characteristics as a
Fig. 2-Min. and max. voltage transfer characteristics.
17.5 AMBIENT TEMPERATURE (TAl· 25· C
::t+
function of temperature.
.
17.5
r nTITTTTTITTI I I I
SUPPLY VOLTAGE IVool
15
>12.5
I
~
-
~g
10
~
t-
"
0
"
15
r~. f
.
_.v
_t~5V
..
!:! 12.5
"0
10 !:!
~
~
a
• .g;
r
.j.2."
"V
2.5
a
10
GATE-TO-SOURCE VOLTAGE
.
IVGS)~15V
~ 1.5
..J
~
~
'7
2.5
10 V
.v
0
5
7.5
10
12.5
10
15
DRAIN-TO-SOURCE VOLTAGE 1VOS)-V
15
INPUT VOLTAGE (VI)-V
92CS-24433
Fig. 4- Typical current and voltage transfer characteristics.
662
t-
z
10V
15
12.5 E
7.S
2."
o
t
AMBIENT TEMPERATURE ITA I,.. 2S-C
E
I
CH1U
I tJ- j
IOV
7.5
t-
=15V
92CS-24319
Fig. 5-Minimum output-N-channel drain characteristics.
File No. 854,_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4069B Slash(/) Series
DRAIN-lO-SOURCE VOLTAGE (Vosl-V
-I!»
-10
-5
AMBIENT TEMPERATURE (T A I-ZS-C
GATE-TO-:-SOURCE VOLTAGE
IVGSI;~
5V.
10V
Z
-10 ~
-15V
·15
I
LOAD CAPACITANCE (CL)-pF
92CS-24434
Fig. 7- Typical propagation delay time vs. load capacitance.
Fig. 6-Minimum output-P-channel drain characteristics.
AMBIENT TEMPERATURE (TA 1= 25· C
I
120
-:.
'"
~IOO
t
i
80
;:
1<
g 60
iii
40
'"~~
~~
,."
..... ~" .
,"z 10'
"'-
~~ la',- ~
:r ,,
10,
,
4
''''''''~" ~7
~p;';O'
"::IS'!,
O~f)
';;;O~:''m
~~
4
4
4
'8 10
,
4
'8
la'
FREaUENCY (f) -
,
4
'8
,
4
'8
10'
KHz
92CS-2443G
Fig. 10- Typical dynamic power dissipation.
663
CD4069B Slash(!) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 854
TEST CIRCUITS
VDD
I
2
•
"I.
12
"
13
12
10
10
9
8
VDD
~
92C5-24441
92C5-24442
Fig. 12-Noise immunity.
Fig. 1'-Quiescent device current.
5V
OR
lav
I.
I.
PULSE GEN.
12
tr~t,.20ns
IN
10
t------------auT
92CM-24443
Fig. 13-Dvnamic electrical characteristics test circuit and waveforms.
CD4069B
TERMINAL ASSIGNMENT
•
G=A
8
H=B
c
I•
2
vaD
I.
"
12
"
10
F
L=F
K-'E
0
J=D
I"C
vss
(TOP VIEW)
92C5-24444
664
File No. 845
Digital Integrated Circuits
Solid State
Division
Monolithic Silicon
High-Reliability Slash (I) Series
CD4071B/••. , CD4072B/•••, CD4075B/•.•
!HI igh-Reliabmty
COS/MOS OR Gates
For Logic Systems Applications in Aerospace,
Military, and Critical Industrial Equipment
CD4071 B Quad 2·lnput OR Gate
CD4072B Dual4·lnput OR Gate
CD4075B Triple 3·lnput OR Gate
Features:
" Medium·Speed Operation tpLH = 70 ns (typ.); tpHL = 100 ns (typ.) at 10 V
FUNCTIONAL OIAGRAMS
" Standard B·Series Output Drive
The RCA·C04071 B. C04072B, and C04075B "Slash" (I)
Series OR gates provide the system designer with direct
implementation of the positive· logic OR function and supple·
ment the existing family of COS/MaS gates. These devices
have equal source- and sink-current capabilities and conform
to standard B·Series output drive (see Static Electrical
Characteristics).
These devices are electrically and mechanically identical with
standard COS/MaS C04071 B, C04072B, C04075B types
described in data bulletin 807 and OATABOOK SSO·203 Series,
but are specially processed and tested to meet the electrical,
mechanical, and environmental test methods and procedures
establ ished for microelectronic devices in MI L·STO·BB3.
MAXIMUM RATINGS, Absolute·Maximum Values:
STORAGE·TEMPERATURE RANGE ............. -65 to +150°C
OPERATING·TEMPERATURE RANGE .......... -55 to +l25 oC
OC SUPPLY·VOLTAGE RANGE
~D····································~W-V
DEVICE DISSIPATION IPER PACKAGEI . .............
LEAD TEMPERATURE IDURING SOLOERINGI:
At distance 1/16 ± 1/32 inch 11.59 ± 0.79 mm)
200 mW
from case for 10 seconds max. ...................
265°C
• All voltage values are referenced to VSS terminal.
The packaged types can be supplied to six screening levels 11 N. 11 R, II, 12, 13, 14 - which correspond to MI L·STO·BB3
Classes "A", "B", and "C", The chip versions of these types
can be supplied to three screening levels -1M, IN, and IR.
For a description of these screening levels and for detailed
test methods, procedures, and test sequence
high·reliability COSIMOS devices refer to
information on
employed with
High·Reliability
MaS CD4000A
Report RIC·l02C, "High· Reliability COSI
"Slash" III Series Types".
OPERATING CONDITIONS AT TA = 25 0 C
For maximum reliability, nominal operating conditions should be
selected so that operation is always within the following ranges.
Characteristic
I nput Voltage Swing
The C04071 B, CD4072B, C04075B "Slash" (I) Series types
are supplied in 14·lead dual·in·line ceramic packages ("0"
suffix). in 14·lead ceramic flat packages ("K" suffix), or in chip
form ("H" suffix).
9·74
Voo
Min.
(Recommended VSS to V OO '
Max.
18
Supply Voltage Range
0.2 V DD -0.5 V
to
to
0.8 V DD V DD +
(Anyone
Units Fig.
V
V
0.5 V
input I
665
CD4071 B. CD4072B. CD4075B Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 845
STATIC ELECTRICAL CHARACTERISTICS
CHARACTERISTIC
SYMBOL
TEST CONDITIONS
Vo
V
Quiescent Device1
Current
Il
V
Min.
Max.
Min.
-
0.5
10
-
I-
-
-
0.550.01
3
5
VOL
10
15
High·level
Threshold Voltage 2
N·Channel
P·Channel
VOH
2.25-
5
4.99
10
9.99
15
-
Typ. Max. Min.
-
0.5
0.01
I-
-
0.01
-
-
-
0
0.05'
0.01
-
0.05
0.01
-
0
0.01
-
0.05
-
-
0
0.5-
-
0.55-
4.99
5
9.99
10
14.5-
15
-
2.3-
-
-
4.95
9.95
14.45-
-0.7-
-3-
-0.7-
-1.5 -3- -0.3-
VTHP
IO= 2O IlA
0.7-
3-
0.7-
1.5
3-
VNH
Max.
0.01
IO=-20IlA
Noise Immunity 1
P·Channel
(Source)
3
125°C
VTHN
VNl
Output Drive Current: 2
N·Channel
(Sink)
-
UNITS
25°C
5
15
Output Voltage: 1
low· level
LIMITS
_55°C
VD[
0.3-
30
20-
-
-3-
5
1.5
-
1.5-
2.25
-
1.4
-
10
3-
-
3-
4.5
-
2.9-
-
1.5
15
-
-
-
6.75
2.25
-
-
1.4
1.5-
3-
4.5
-
3
-
-
6.75
-
-
10
9
13.5 15
2.9-
-
-
0.4
4.5
0.5
-
0.4-
O.B
-
0.3
0.5
10
1.1
-
0.9-
1.B
-
0.65
1.5
15
-
3
6
-
-1.6-
-3.2
-0.4-
-O.B
5
rnA
2.5
5
-2
4.6
5
-0.5
.-
9.5
10
-1.1
-
-0.9-
-1.B
-
-
-
-3
-6
-
-
1.5-
-
-
1.5·
-
-
-
13.5 15
Oiode Test 3
100llA Test Pin
VOF
Input Current
II
V
-
ION
lOP
V
3-
1
4.2
V
-
O.B
1.5-
IlA
-
15
±10-5 ±1
-1.15
-
-0.3
-
-0.65
-
-
-
-
1.5-
-
-
rnA
V
IlA
Limits with black dot te) designate 100% testing. Refer to RIC·l02C "High-Reliability COS/MOS CD4000A Slash {I} Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1: Complete functional test all inputs and outputs to truth table.
Note 2: Test is either a one input or a one output onlv.
666
Note 3: Test on all inputs and outputs.
,File No. 845 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4071B. CD4072B. CD4075B Slash (I) Series
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25°C. Input t r• tt = 20 ns. and CL = 50 pF
TEST CONDITIONS.
CHARACTERISTIC
SYMBOL
VDD
Volts
Propagation Delay Time:
Max.
5
10
15
250
100
75
500·
200·
tpLH
5
10
15
175
70
55
350·
140·
5
10
15
100
50
40
200·
100·
80
tTHL
Transition Time
tTLH
Average Input Capacitance
UNITS
Typ.
tpHL
High-to-Low Level
Low-to-High Level
LIMITS
Any Input
el
5
ns
ns
ns
-
pF
Limits with black dot (e) designate 100% testing. Refer to RIC-l02C "High-Reliability COS/MOS CD4000A Slash (II Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
* Tests are either several inputs or several outputs.
115,8,t2)
B*
216,9,13)
* ALL
INPUTS PROTECTED BY STANDARD
COSI MOS PROTECTION CIRCUIT
92CS-23812RI
Fig. 1-(:04071 8 schematic diagram (1 of 4 identical DR gates).
AMBIENT TEMPERATURE ITA ,- 25-C
15
>
c
1VOD,-15 V
12.5
CURRENT
PEAK
~!:!
...
.. I-
cz
10
I-U
~~
g~
~
VI
rl~
>~
1.11
SUPPLY VOLTS
E
11
0 0
lOY
7,'
CURRENT
PEAK
CURRENT
PEAK
5
2,'
_
\
_
_"}
I
f
>
0
Y~
~
~
o
10I-'-lTtt+1~ttmtttH-tttttti
~DD
I•
1=_ ' -/
VI
t+1+++t-t-H-H-rrl++-t-Il
~++THH+++I++++THH++t-HH -
-
~
t
I
Vo
Vss
.V
a
25
7.5
to
12.5
INPUT VOLTAGE I v~ )-v
15
92CS-23815RI
Fig. 2- Typical voltage and current transfer characrerisrics.
INPUT VOLTAGE 1VI)-V
92C5-24488
Fig.3-Min. and max. voltage transfer characteristics.
667
CD4071B, CD4072B, CD4075B Slash (I) Series
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 845
A*
21910---1r------------,
V DD
. d
--1
d J
B*
3\1010-+--~r---~--,
~
C*
41 111 0--1--1---1----.-----,
0*
.11210-+---j---+---.....,
f
J -A+B+C+D
?tf_ ~:':'~
LOGIC I,HIGH
~VDD
Vss
* ALL INPUTS PROTECTE 0
Vss
BY STANDARD COS/MOS
PROTECTION NETWORK
VS5
92CS-2J813RI
Fig. 4 - CD4072B schematic diagram (1 of 2 identical OR gates).
t"~kJ
9"
A*
1\3,III0-------~,
B*
214,'210-----.----+,
H9t6.IOl
>=r ~~tl~~:~'GH
C*
810,1310-,---+---+,
LOGIC 0
~
LOW
Vss
* ALL INPUTS PROTECTE
0
COSI
BY STANDARD
MQS
PROTECTION NETWORK
Vss
92C5-23814RI
Fig. 5- CD40758 schematic diagram (1 of 3 identical OR gates).
DRAIN-TO -SOURCE VOLTAGE (Vosl- v
1
C±J:
t:"!:"
_ _ _..::-,,15,.
AMBIENT TEMPERATURE ITA )225°C
15
-
~
H
-12.5
-10
-5
AMBIENT TEMPERATURE ITA J=2S-C
.. ·--Wl
em
GATE-TO-SOURCE VOLTAGE IVGS'=- 5V
~
z
a'"'"
10
10V
-GATE-lO-SOURCE VOLTAGE IVGS)'15V
I
z
__
++
z
10 V
-10
i
~
'"zz
-ISV
+.
~
G
'V
·,5 6.
10
15
DRAIN-lO-SOURCE vOLTAGE 1Vasl-V
!:I2CS-24)19
Fig. 6- Minimum output-N-channel drain characteristics.
668
Fig. 7- Minimum output·P·channel drain characteristics.
File No. 845 - - - - - - - - - - - - - - - - C D 4 0 7 1 B , CD4072B, CD4075B Slash (/) Series
LOAD CAPACITANCE (ell -
pF
LOAD CAPACITANCE (CL1- pF
92CS-24489
92CS-24490
Fig. 8 - Typical
high-to%~~w
level propagation delay time
Fig. 9 - Tvpicallow-to-high level propagation delay time
vs. load capacitance.
700
f
~
vs. load capacitance .
• AMBIENT TEMPERATURE (TAl" 25°C I
. LOAD CAPACITANCE (ell" 50 pF
600
1
500
w
400
g
300
"
1
z
0
~
~
~
200
100
~
75
10
las
15
175
W
SUPPLY VOLTAGE (V oo ) - V
92C5-24491
LOAD CAPACITANCE (e l }-pF
92C5-24322
Fig. 10 - Typical propagation delays vs. supply voltage.
Fig. 11- Typical transition time vs. load capacitance.
105
~
AMBIENT TEMPERATURE (TA 1= 25°C
10'
~
.'.
Q
~
10'
z
0
~
~
~
10'
~
CL=50pF
0
Cl "15 pF
~
w
~
10 '
.I--l--+-l-+C-+.. 1_1-1.t-!--+-.--~
10°
10- 1
10°
10 I
FREQuENCY (f) -
10 2
kHz
10'
Fig. 12 - Typical dynamic power dissipation vs. frequency.
669
CD4071B. CD4072B.CD4075B Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ FiJe No. 845
Voo
t
CD4071B
••
CD4075B - PUT METER IN SAME
PLACE AS CD4011B
'3
.2
TIE PINS 1.2.3.4.~.1I.12.13
TO SWITCH,
.0
•
C04072B - PUT METER IN SAME
PLACE AS CD4071B
TIE PINS 2.3,4,5,9,10,11.12
TO SWITCH.
92'C5-24492
Fig. 13 -Ouiescent current test circuits.
0.7 VOO
!
•
0.7 Voo
TrEsT
"
O.3Yoo
'0
0.7 YOO
CD4Q72B
TEST
VDD
••
13
r
'2
!
"
0.3 Yeo
.0
r
!
C040758
•
••
•
.0
VOD
13
.2
5
TES
•
0.3 Voo
9"CM-2'4493
Fig. 14 -Noise immunity rest circuits.
..
2
J:oA+B
K~C+D
C
VSS
TERMINAL ASSIGNMENTS
(Top Views)
••
13
VDD
H
"
•
13
VDD
K-E+F+G+H
•
•
..
2
••
VDD
G
'0
L-G+H+I
13
.2
M~G+H
L"E+F
CD4071B
92C5-24494
670
2
.2
'2
.0
••
• ••
J·A .... B+C+O
NC
Vss
•
7
.0
••
K-O+E+F
NC
Vss
•
J ~A+B+C
C
CD40758
C04072B
92C5-24496
92CS-2449!1
File No. 844 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Digital Integrated Circuits
[RlcrBLlD
Solid State
Division
Monolithic SiliC;on
High-Reliability Slash (I) Series
CD4081B/.. ., CD4082B/..., CD4073B/...
High-Reliability
COS/MOS AND Gates
For Logic Systems Applications in Aerospace,
Military, and Critical Industrial Equipment
CD4081 B Quad 2·lnput AND Gate
CD4082B Dual 4·lnput AND Gate
CD4073B Triple 3·lnput AND Gate
Features:
" Medium-Speed Operation - tpLH
DIAGRAMS
= B5 ns (typ.l:
tpHL
= 65 ns (typ.1 at 10 V
" Standard B·Series Output Drive
The RCA·CD408IB, CD4082B, and CD4073B "Slash" (/1
Series AND gates provide the system designer with direct
implementation of the AND function and supplement the
existing family of COS/MOS gates. These devices have equal
source- and sink-current capabilities and conform to standard
B-series output drive (see Electrical Characteristics).
These devices are electrically and mechanically identical
with standard COS/MOS CD4081B, CD4082B, C04073B
types described in data bulletin 806 and DATABOOK SSO·
203 Series, but are specially processed and tested to meet
the electrical, mechanical, and environmental test methods
and procedures established for microelectronic devices in
MI L-STD·B83.
The packaged types can be supplied to six screening levels /1 N, /1 R, /1, /2, /3, /4 - which correspond to MI L·STD·8B3
Classes "A", "8", and "C". The chip versions of these types
can be supplied to three screening levels - /M, IN, and /R.
For a description of these screening levels and for detailed
information on test methods, procedures, and test sequence
employed with high·reliability COSIMOS devices refer to
High·Reliability Report RIC·l02C, "High· Reliability COSI
MaS CD4000A "Slash" (I) Series Types".
The CD4081 B, CD4082B, CD4073B "Slash" (/1 Series types
are supplied in 14·lead dual·in·line ceramic packages ("D"
suffixl, in 14·lead ceramic flat packages ("K" suffix). or
in chip form ("H" suffixl.
= 25 0 C
MAXIMUM RATINGS, Absolute·Maximum Values:
OPERATING CONDITIONS AT TA
STORAGE·TEMPERATURE RANGE ............. -65 to +150o C
OPERATING·TEMPERATURE RANGE .......... -55 to +125 0 C
DC SUPPLY·VOL TAGE RANGE
V DO •................................... -0.5 to +18 V
DEVICE DISSIPATION (PER PACKAGE) . .. . .. ..... . .. 200 mW
LEAD TEMPERATURE (DURING SOLDERING),
At distance 1/16 ± 1/32 inch 11.59 ± 0.79 mm)
from case for 10 seconds max. ................... 265°C
For maximum reliability, nominal operating conditions should be
selected so that operation is always within the following ra,}ges.
• All voltage values are referenced to VSS terminal.
9·74
Characteristic
Supply Voltage Range
I nput Voltage Swing
(Recommended VSS to VDD )
VOD
Min.
Max.
3
18
0.2 VOO -0.5 V
to
to
0.8 V DO VOO +
(Anyone 0.5 V
input)
Units Fig.
V
V
671
CD4081B. CD4082B. CD4073B Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 844
STATIC ELECTRICAL CHARACTERISTICS
CHARACTERISTIC
Quiescent Device 1
Current
SYMBOL
TEST CONDITIONS
V
V
Min.
Max.
Min.
5
-
0.5
-
3
5
-
0.55°
0.01
10
-
0.01
15
-
IL
10
High-Level
Threshold Voltage 2
N-Channel
P-Channel
VOL
VOH
3
2.25°
Typ. Max. Min.
0.5
-
30
0.01
1°
-
20°
0.01
-
-
-
0:05'
0.01
0.05
0.05
0.55°
-
0
0
0.01
-
-
0
0.5°
-
-
-
-
-
5
4.99
-
4.99
5
-
4.95
10
9.99
-
9.99
10
-
9.95
15
-
-
14.5°
15
-
14.45°
-
= -20)JA
-0.7°
-3°
-0.7·
-1.5 -3° -0.3°
ID
= 20)JA
0.7°
3°
0.7°
1.5
3°
1.5°
2.25
3°
4.5
3°
-
1.4
-
2.9°
5
1.5
1
10
3°
1.5
15
-
-
-
6.75
-
-
-
4.2
5
1.4
-
1.5°
2.25
-
1.5
-
2.9°
-
3°
4.5
-
3
-
-
-
-
6.75
-
0.4°
0.8
0.9°
1.8
0.4
5
0.5
0.5
10
1.1
-
1.5
15
-
-
-
-
-
0.3
-
-
0.65
-
-
-
IDN
lOP
V
-3°
0.3°
0.8
9 10
13.5 15
)JA
-
-
2.3°
10
VNH
Max.
0.01
VTHN
Noise Immunity 1
P-Channel
(Source)
-
125°C
VTHP
VNL
Output Drive Current: 2
N-Channel
(Sink)
1°
-
UNITS
25°C
VDe
15
Output Voltage:'
Low· Level
LIMITS
_55°C
Vo
V
V
rnA
2.5
5
-2
-
4.6
5
-0.5
.-
9.5
10
-1.1
-
-1.6° -3.2 -0.4° -0.8 -0.9° -1.8 -
-
-
-3
-
1.50
-
-
-
-
13.5 15
3
6
-6
-
-
1.5°
-1.15
-0.3
-0.65
-
-
-
-
1.5°
-
-
rnA
~iode Test 3
100)JA Test Pin
Input Current
VDF
II
-
15
±10- 5 ±1
V
)JA
Limits with black dot 1-) designate 100% testing. Refer to RIC·l02C "High-Reliability COS/MOS CD4000A Slash {II Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1: Complete functional test all inputs and outputs to truth table,
Note 2: Test is either a one input or a one output only_
672
Note 3: Test on all inputs and outputs.
File No. 844 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4081B, CD4082B, CD4073B Slash
In Series
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25 0 C. Input t r • 1t = 20 ns. and CL = 50 pF
TEST CONDITIONS *
CHARACTERISTIC
VDD
Volts
Propagation Delay Time:
tpHL
High·to·Low Level
Low·to·High Level
tpLH
tTHL
Transition Time
tTLH
Average Input Capacitance
LIMITS
UNITS
SYMBOL
Typ.
Max.
5
10
15
160
65
50
320130-
5
10
15
210
85
65
420·
170 _
5
10
15
100
50
40
200lOO80
ns
-
-
5
Any Input
CI
ns
-
ns
pF
Limits with black dot ,e) designate 100% testing. Refer to RIC·l02C "High-Reliability COS/MOS CD40QQA Slash 1/) Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing .
• Tests are either several inputs or several outputs.
115 •••
';~~~·· ik,
L-_-+-'~".
'NPUT8*
H' ~'
Vss
* ALL
~t:;:.",
L\
9"
2 ( 6 . 9 . 1 3 ) 0 - - - - ' ' - - - - - - - < . . . . . Vts
S
rJ
LOGIC I_HIGH
LOGIC O!l LOW
INPUTS PROTECTED BY
STANDARD COS/MOS PROTECTION
NETWORK
v,s
9:i?CS·:i?38:i?6RI
Fig. 1-CD40818 schematic diagram (1 of 4 identical AND gates).
AMBIENT TEMPE~ATURE ITA ,- 2~·C :
t
~
~
o>~
j.
;:!:di:
l :UI\: I: ~ ~: :i!~
::
,ol':'!li't
..!I 11:
i" ,;" I" "v
:
:::1 .,1 ;:
_"4
•
I ••
,.
'25 1:
7.5
~
6
!. t I : t
==~~x
"~~~~~~E'! ,,;! !IIIIIIII' 1:::1:1,:1:::1.1::::
V
I oo)·'5V lill 111:11 :. ::
~VDD
:1111111 111111111"111!1
5
2.5
'
,I
I 1
' I ,
:::; Ii
Itl
I ..
J
-
~
"0
:. :.
VSS~_7_
::1: , :1
f-++t'H+---I+--+-'-'-I+'-+--+--+--1
::l1d H
!j: id:::t:J:::
5Y"
.,,
~
_ -
::
,.
- 12.5
z
J
, •
E
I-
I
I
~
~
10
,.. ; +
GATE-TO-SOURCE VOLTAGE IVGS)'15V
r.5
10 V
-
2.5
5
7·5
10
12.5
15
INPUT VOlTAGE I VI'-V
Fig. 2- -Min. and max. voltage transfer characteristics.
2.5
5V
10
15
DRAIN-lO-SOURCE VOLTAGE 1VOS1-V
Fig. 3- Minimum output·N-channel drain characteristics.
673
CD4081B. CD4082B. CD4073B Slash (f) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 844
A*
2t.,O~----_+---_t_--_1r
B"
3(10}
C ..
4(1IIU--------+-----i1-'
0*
5(121
* ALL
INPUTS PROTECTED BY
STANDARD COS/MOS PROTECTION
NETWORK
nCS-;?l827
Fig. 4-CD40828 Schematic diagram (1 of 2 identical AND gates).
~J~ tHd'
J.H J""
1" ?"
)-D9(6.101
+ ___f--'~"
.J
113,111 A>*"----+_ _ _
B*
2(4,121U---_
_......_ _ _ j-J ~ "
,.J
Bt5.13IIU------_ _ _ _+-J
c*
9"
Vss
* ALL
INPUTS PROTECTED By
STANDARD COS/MOS PROTECTION
NETWORK
_
£\
~
~"
:J
LOGIC
LOGIC
,=
HIGH
a :: LOW
vss
Vss
92C5-23828
Fig. 5-CD40738 schematic diagram (1 of 3 identical AND gates).
DRAIN - TO - SOURCE VOLTAGE (1I 05 1-V
-15 _
-10
-5
AMBIENT TEMPERATURE ITA 1=25-C
"~
GATE-lO-SOURCE VOLTAGE (VGS)=-5V
~
-5 ~
~
z
-IOV
w
~
z
-to
-1511
-15
i
;
lif~
lir1!5
•• •• H
El
.
H.··.·
so
I:
100
li~
50
~
LOAD CAPACITANC~ (CLI-pF
Fig. 6- -Minimum outpur·P-channel drain characteristics.
674
92CS-24531
Fig. 7- Typical high·to-low level propagation delay vs,
load capacitance.
File No. 844 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4081B. CD4082B. CD4073B Slash II) Series
1
~
t;": :p:":1 I'"
m
..i I U. -'JIIlI:iI tiJr!! I!I! I:.\!! ! ::!, ..
'I
AMBIENT TEMPERATURE (TA'· 25·C:~t"t.l
LOAD CAPACITANCE (el'" 50 pF
: _:::-
600
1
'",.>= 400
5 300 II
i!l
fi
200
~
100
~
i
~
I!
ii
ffi
~
I
11
II
I.
: I
!
It'
,
:1
!
II!
.~
.~.
.~
Iii
fm-llj:
2.5
7.5
10
12.5
15
SUPPLY VOLTAGE 1Voo) -
17.5
20
III
v
LOAD .cAPACITANCE ICL)-pF
Fig. 8- Typical/aw-ro-high level propagation delay
II;;
I
,
!
.; 500
iii
,Ii!
92C5-24533
Fig. 9
VI.
~ Typical
propagation delays vs. supply voltage.
load capacitance.
10' AMBIENT TEMPERATURE ITA)- 25·C
...
1
;
z
0
>=
:.
i:i
;;
.
'"'"
~
1-1-
10'
~
,~<>
"\'i-~ft,
10'
.~
,Q
.,'"
",..),0" ./
,"
e;,..;:J~fl
1/
CL·~OpF
CL·I~pF -
/
10'
1/
-
10°
10°
LOAD CAPACITANCE ItL l-pF
10'
Fig. 10- Typical transition time
VI.
10 2
10'
10'
FREQuENCY (I J- kHz
92C5-24323
92C5-24322
Fig. 11- Typical dynamic power dissipation vs. frequency.
load capacitance.
VDO
l
CD40BIB
VDD
CD4073B - PUT METER IN SAME
PLACE AS CD40BI
TIE PINS 1,2,3,4,5,11,12,13
TO SWITCH
CD40B2B - PUT METER IN SAME
PLACE AS CD40el
TIE PINS 2,3,4,5,9,10,11,12
TO SWITCH.
92CS-24534
Fig. 12-Quiescent current test circuits.
675
CD4081B, CD4082B, CD4073B Slash
(II
Series _ _ _ _ _ _ _ _ _ _ _ _ _ __
File No. 844
92CM -24535
Fig. 13- Noise immunity test circuits.
TERMINAL ASSIGNMENTS
A
B
J=A·B
K=C'O
I.
2
Voo
"
•
10
0
Vss
J=A'B'C'D
"
13
12
MEG·H
L"E· F
(TOP VIEW)
C
0
NC
Vss
I.
2
14
13
12
676
I.
2
"
10
9
7
(TOP VIEW)
•
CD4082B
I.
13
12
"
E
NC
K"Q'E ·F
10
9
Vss
Voo
G
L=G'H'I
J=A'B'C
C
(TOP VIEW)
92C5-24537
9:i!CS-245J6
CD4081B
Voo
K=E·F·G·H
92C$-24538
CD4073B
File No. 855 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Digital Integrated Circuits
OOCI8LJD
Monolithic Silicon
Solid State
Division
High-Reliability Slash (I) Series
CD4078B/...
High-Reliability
COS/MaS 8-lnput NOR Gate
For Logic Systems Applications in Aerospace,
Military, and Critical Industrial Equipment
VDD a l4
vss -7
Features:
92CS-23817RI
Medium·speed operation - tpHL = 80 ns, tpLH = 170 ns 'typ.1 at 10 V
• Standard B·series output drive
D
CC40788 Functional Diagram
The RCA·C04078B Slash (I) Series NOR Gate provides the
system designer with direct implementation of the positive·
logic 8·input NOR function and supplements the existing
family of COS/MOS gates.
This device has equal source· and sink·current capabil ity and
conforms to standard B-series output drive (see Static Elec-
trical Characteristics).
These devices are electrically and mechanically identical with
standard COS/MOS C04078B types described in data bulletin
Bl0 and OATABOOK 550·203 Series. but are specially pro·
cessed and tested to meet the electrical. mechanical, and
environmental test methods and procedures established for
microelectronic devices in MI L-STO·883.
MAXIMUM RATINGS, Absolute·Maximum Values:
STORAGE·TEMPERATURE RANGE ............. -66 to +1500 C
OPERATING·TEMPERATURE RANGE .......... -55 to + 125°C
DC SUPPLY·VOLTAGE RANGE
Voo ••.................................. -0.5 to +18 V
DEVICE DISSIPATION (PER PACKAGE) . . . . . . . . . . . . .. 200 mW
LEAD TEMPERATURE (DURING SOLOERING):
At distance 1/16 ± 1132 inch 11.59 ± 0.79 mm)
from case for 10 seconds max, ...........•....... 265°C
• All voltage values are referenced to VSS terminal.
The packaged types can be supplied to six screening levels /IN. /1R,/I,/2, 13, 14 - which correspon'd 10 MIL·STD·883
Classes "A", "B", and "C", The chip versions of these types
can be supplied
10
three screening levels - 1M, IN, and IR.
For a description of these screening levels and for detailed
information on test methods, procedures, and test sequence
employed with high·reliability COS/MaS devices refer to
High·Reliability Report RIC·102C, "High·Reliability COS/
MaS CD4000A "Slash" (/J Series Types':
The C04078B "Slash" (I) Series types are supplied in 14·lead
dual·in·line ceramic packages '''0'' suffix), in 14·lead ceramic
flat packages '''K'' suffix), or in chip form '''H"' suffix).
9·74
OPERATING CONOITIONS AT TA = 2S0 C
For maximum reliability, nominal operating conditions should be
selected so that operation is always within the following ranges
VOO
Min.
Max.
Supply Voltage Range
-
3
18
I"put Voltage Swing
(Recommended VSS to V OO '
-
Characteristic
0.2 V OD -0.5 V
to
to
0.8 V DD V DD +
(Anyone 0.5 V
Units Fig.
V
-
V
-
input)
677
CD4078B Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 855
STATIC ELECTRICAL CHARACTERISTICS
CHARACTERISTIC
SYMBOL
TEST CONDITIONS
Vo
V
Quiescent Device'
Current
IL
V
Min.
Max.
Min.
-
0.5
I-
-
10
VOL
High·level
Threshold Voltage2
N·Channel
P·Channel
VOH
-
30
I-
-
0.01
-
-
20-
-
0
0.50.01
0.01
-
0.05
0
0
0.5-
-
0.55-
-
-
-
-
0.550.01
10
-
0.01
15
-
-
-
-
2.3-
5
4.99
-
4.99
5
10
9.99
-
9.99
10
15
-
-
14.5-
15
4.95
9.95
14.45-
-0.7-
-3-
-0.7-
-1.5 -3- -0.3-
VTHP
10 = 20jJ.A
0.7-
3-
0.7-
1.5
3-
1.5
-
1.5-
2.25
-
1.4
3-
-
3-
4.5
-
2.9-
-
-
-
6.75
-
-
5
1.4
-
1.5-
2.25
1.5
1
10
2.9-
-
3-
4.5
1.5
15
-
-
-
6.75
-
0.4-
0.8
0.9-
1.8
0.4
5
0.5
0.5
10
1.1
-
1.5
15
-
-
lOP
Oiode Test 3
100 jJ.A Test Pin
VOF
Input Current
II
-
0.3
-
0.65
-
-
-
2.5
5
-2
-
5
-0.5
.-
9.5
10
-1.1
-
-
-
-3
-
1.5-
-
-
-
-
15
6
-6
-
-
1.5-
±10-5 ±1
-1.15
-0.3
-0.65
V
-
-
4.6
-
-3-
-
-1.6- -3.2 -0.4- -0.8 -0.9- -1.8 -
13.5 15
-
-
ION
3
3-
V
-
-
5
10
0.8
0.05
3-
9
jJ.A
-
0.3-
4.2
13.5 15
VNH
P·Channel
(Source)
0.5
0.01
10 =-20jJ.A
Noise Immunity'
Max.
-
VTHN
VNl
Output Orive Current: 2
N·Channel
(Sink)
Typ. Max. Min.
-
-
2.25-
12SoC
0.01
3
5
3
UNITS
2Soc
5
15
Output Voltage:'
Low· level
LIMITS
-ssoc
VDC
V
rnA
-
-
-
1.5-
-
-
rnA
V
jJ.A
Limits with black dot Ie) designate 100% testing. Refer to RIC-l02C "High-Reliability COS/MOS CD4000A Slash (I) Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1: Complete functional test.all inputs and outputs to truth table.
Note 2: Test is either a one input or a one output only.
678
Note 3: Test on all inputs and outputs:
File No.855 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4078B Slash (I) Series
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 250 C, Input t r, tf = 20 n5, and CL = 50 pF
LIMITS
TEST CONDITIONS.
CHARACTERISTIC
SYMBOL
Propagation Delay Time:
tpHL
High·to·Low Level
Low.t~.High
Level
tpLH
tTHL
Transition Time
tTLH
el
UNITS
VDD
Volts
Typ.
Max.
5
10
15
5
10
15
200
80
60
425
170
120
400·
160·
5
10
15
100
50
40
5
m
850·
340·
n5
200·
100·
80
ns
pF
Limits with black dot Ie) designate 100% testing. Refer to AIC-l02C "H!gh-Reliability COS/MOS CD4000A Slash (I) Series Types", Tables 2
Average Input Capacitance
Any Input
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
• Tests are either several inputs or several outputs.
VDD
AO(:2~~~------------------~
.0
3
co(..U-~------~----,-----~
Do .»--4------~----+-----~
Eo 9»--4--------------------,
J .A+B+C+ D+E+FtG+H
L\
LOGIC I-HIGH
LOGIC O. lOW
Go(lI~I~~----_+----~~----_,
VDD
Hol~~~----+-----~----_.~
*ALL INPUTS PROTECTED BY
STANDARD COS/Mas PROTECTION
NETWORK
.
5S
9ZCM-23878RI
Fig. I-C040788 schematic diagram.
679
CD4078B Slash (II Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No.855
.
AMBIENT TEMPERATURE I T A).2~·C
~
AMBIENT TEMPERATURE (TA ):25-C
15
z
>
I
__ MIN.
12.5
~
MAX.
10
~
VI
~
7.5
~
~
~
5
2.5
0
~
~
_
5
~
...o 12.5
Voo
~
z
w
-----..,
High-Reliability Slash (I) Series
CD4086B/•••
High-Reliability
COSIMOS Expandable 4-Wide
2-lnput AND-OR-INVERT Gate
For Logic Systems Applications in Aerospace,
Military, and Critical Industrial Equipment
Features:
J _INH
+ ENABLE +AB+CD+EF+GH
CD4086B Functional Diagram
• Medium·speed operation - tpH L = 90 ns; tpLH = 140 ns Ityp.) at 10 V
• INHIBIT and ENABLE inputs
• Standard B-series output drive
The RCA·CD40868 "Slash" (I) Series contains one 4·wide
2·input ANO·OR·INVERT gate with an INHIBIT/EXP input
and an ENABLE/EXP input. For a 4·wide A·O·I function
INHIBIT/EXP is tied to VSS and ENABLE/EXP to VOO"
See Fig. 2 and its associated explanation for applications where,
a capability greater than 4·wide is required. This device has
equal source- and sink-current capabilities and conforms to
standard 8 .. eries output drive (see Static Electrical Charac'l
teristics).
MAXIMUM RATINGS, Absolute·Maximum Values:
STORAGE·TEMPERATURE RANGE ... , , ........ -65 10 +1500 C
OPERATING·TEMPERATURE RANGE, •........ -551o +125 oC
DC SUPPLY·VOLTAGE RANGE
V DD ' .............. , .... , ............... -0.510+18 V
DEVICE DISSIPATION (PER PACKAGE I •........ , .. ,. 200 mW
LEAD TEMPERATURE (DURING SOLDERINGI:
At distance 1116 ± 1132 inch (1.59 ± 0.79 mm)
from case for 10 seconds max. ....•..............
265°C
* All voltage values are referenced to Vss terminal.
These devices are electrically and mechanically identical with
standard COS/MOS CD4086B types described in data bulletin
812 and OATABOOK 550·203 Series, but are specially pro·
cessed and tested to meet the electrical, mechanical. and
environmental test methods and procedures established for
microelectronic devices in MIL-STO·883.
The packaged types can be supplied to six screening levels /IN, 11R, II, 12, 13,/4 - which correspond to MIL·STO·883
Classes "A", "B", and "C". The chip versions of these types
can be supplied to three screening levels -1M, IN, and IR.
OPERATING CONDITIONS AT T A = 250C
For a description of these screening levels and for detailed
For maximum reliability. nominal operating conditions should be
information on test methods, procedures, and test sequence
selected so that operation
employed with high·reliability COSIMOS devices refer to
High·Reliability Report RIC·102C, "High· Reliability COSI
MOS CD4000A "Slash" II) Series Types".
The CD4086B "Slash" (I) Series types are supplied in 14·lead
dual·in·line ceramic packages ("0" suffix), in 14·lead ceramic
flat packages ("K" suffix), or in chip form ("H" suffix).
688
;s always within the following ranges
Characteristic
V DD
Min.
Max.
SupplV Voltage Range
-
3
18
Input Voltage Swing
(Recommended Vss to V OO )
-
0.2V DD -0.5 V
10
10
OBV DD V DO +
(Any one 0.5 V
inpud
Units Fig.
V
-
V
-
9·74
File No. 846 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4086B Slash.(/) Series
VOO
A 1*
D 13
*
H
*
ENABlE/EXP
9
Q.lli)*.:.....:V.;!SS:!..._ _ _ _ _ _ _--1
INHIBIT/EXP(,IIIOJ}*"'------------_ _ _ _ _..J
Fig.
INHIBITlOO,
fVss
92CM-23sn
r-CD40868 schematic diagram.
INHIBITlEXP2
r--------,
.,
AI
CI
01
EI
FI
GI
HI
vo
ENABlE/EXP, UL_ _ _-::-;:;:;~~=""==;;~~~~;;;~:;;:~~---'
J2;AIBI+ CI 01 .. EI FI +GI HI .. A2 82+ C2 02 ... E2 F2+G2 H2
Fig. 2- Two CD4086B's connected as an 8-wide 2·;nput A-O-' gate.
Fig. 2 above shows two CD4086B's utilized to obtain an
8·wide 2·input A·a·1 function. The output (Jl) of one
CD4086B is fed directly to the ENABLE/EXP2 line of the
second CD4086B. In a similar fashion, any NAND gate
output can be fed directly into the ENABLE/EXP input to
obtain a 5·wide A·a·1 function. In addition, any AND gate
output can be fed directly into the INHIBIT/EXP input with
the same result.
689
CD40868 Slash (II Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No.846
STATIC ELECTRICAL CHARACTERISTICS
CHARACTERISTIC
SYMBOL
TEST CONDITIONS
Vo
V
Quiescent Device'
Current
Output Voltage:'
Low· Level
High·Level
Threshold Voltage2
N·Channel
P·Channel
IL
VOL
VOH
Min.
Max.
Min.
-
0.5
10
-
1-
-
15
-
-
-
3
5
-
0.550.01
-
10
-
0.01
15
3
-
-
2.25-
-
-
-
-
0.50.01
-
-
-
0
0.01
-
0.05
0
0.5-
-
0.55-
-
-
4.99
5
4.95
-
9.99
-
9.99
10
-
9.95
15
-
-
14.5-
15
-
-
14.45-
-
-1.5 -3- -0.3-
-0.7-
VTHP
1.5
3-
O.a-
-3-
5
1.5
-
1.5-
2.25
-
1.4
-
10
3-
-
3-
4.5
-
2.9-
6.75
-
-
2.25
-
1.5
3-
1
10
2.9-
1.5
15
-
-
-
0.4
4.5
0.5
-
0.4-
0.8
-
-
0.3
-
0.5
10
1.1
-
0.9-
1.8
-
0.65
-
1.5
15
-
-
3
6
-
-
-
-
-
-
5
1.4
1.53-
4.5
-
6.75
ION
2.5
5
-2
-
-1.6- -3.2
5
-0.5
..-
-0.4- -0.8
-
-0.3
9.5
10
-1.1
-
-0.9- -1.8
-
-0.65
-
-
-3
-6
-
-
-
-
1.5-
-
-
1.5-
-
1.5-
-
-
-
-
13.5 15
-
15
±10-5 ±1
V
rnA
4.6
-1.15
V
3-
9
0.8
V
-
4.2
13.5 15
p.A
0.05
4.99
0.7-
II
0
30
20-
5
-3-
VOF
0.01
-
0.5
1-
10
3-
Input Current
0.01
Max.
-
-0.7-
Diode Test3
100 p.A Test Pin
Typ. Max Min.
0.01
2.3-
0.7-
lOP
125°C
-
10 = -20p.A
VNH
P·Channel
(Source)
V
5
10 = 20p.A
Noise Immunity'
UNITS
25°C
VTHN
VNL
Output Drive Current: 2
N·Channel
(Sink)
LIMITS
_55°C
VD[
rnA
V
p.A
Limits with black dot (e) designate 100% testing. Refer to RIC·l02C "High-Reliability COS/MOS CD4000A Slash II) Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
Note 1: Complete functional test. all inputs and outputs to truth table.
Note 2: Test is either a one input or a one output only.
690
Note 3: Test on all inputs and outputs.
File No. 846 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4086B Slash (I) Series
DYNAMIC ELECTRICAL CHARACTERISTICS AT TA
= 250 C.
CL = 50 pF. Input tr.tt = 20 ns
TEST CONDITIONS*
CHARACTERISTIC
SYMBOL
Propagation Delay
Time (Data):
High-to-Low Level
tpHL
Low-to-High Level
tPLH
Propagation Delay
Time (Inhibit):
High-to-Low Level
Low-to-High Level
tpHL(lNH)
tpLH(lNH)
tTHL.
Transition Time
tTLH
Average Input
Capacitance
LIMITS
UNITS
VDD
Volts
TYP.
5
225
450·
10
90
180·
15
60
-
5
350
700·
10
140
280·
15
100
-
5
150
300·
10
60
120·
15
40
-
5
250
500·
10
100
200·
15
70
ns
ns
ns
ns
-
5
100
200·
10
50
100·
15
40
80
ns
-
5
Any Input
CI
MAX.
pF
Limits with black dot (_) designate 100% testing. Refer to RIC-102C "High-Reliability COS/MOS CD4000A Slash(/) Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
* Tests are either several inputs or several outputs.
.,
IS
_ _ _ MIN.
_ _ MAX.
>
I
~12.5
!
w
~
f5
AMBIENT TEMPERATURE ITA 1=25°C
E
>--
z
w
a
~
10
~
>
~
>--
10
GATE-TO-SOURCE VOLTAGE IVGS1'15V
7,5
10.
~
~
-'
>--
~
15
!i
y
10
15
5
2.5
5.
5
INPUT VOLTAGE IV1)-V
10
15
DRAIN-TO-SOURCE VOL.TAGE (Vos)-V
92C5-24500
Fig.3- Min. and max. voltage transfer characteristics.
g2CS-24319
Fig.4-Minimum output n-channel drain characteristics.
691
CD4086B Slash
(/I Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ FileNo. 846
DRAIN-TO-SOURCE VOLTAGE (Vos)-V
-15
-10
a
-5
AMBIENT TEMPERATURE (fA )"'2'·C
10V
z
10
~
irlz
-15V
~
15 ::a.
LOAD CAPACITANCE ICL1-pF
92CS-24501
92CS-24321
Fig.5-·Minimum output p-channel drain characteristics.
Fig.6- Typical DA TA or ENABLE high-to-low level propagation
delay time vs, load capacitance.
AMBIENT TEMPERATURE (TA)-25-C
(ell· 50 pF
LOAD CAPACITANCE
1250
1000
tPLH
750
500
tpHL
250
2.5
7.5
10
12.5
IS
20
11.5
SUPPLY VOLTAGE (Voo)-V
LOAD CAPACITANCE (CLl-pF
92CS-24503
92C5-24502
Fig.8- Typical DATA or ENABLE propagation delay
Fig.7- Typical DATA or ENABLE low-to-high level
propagation delay time vs. load capacitance.
time vs. supply yoltage.
10'
.
1.
.
~
AMBIENT TEMPERATURE IT A)~ 2'5-C
10'
,,~
0
~'"i-~fi,
10'
z
;:
iii
is
'"'"
~
~
~
.,~
"~&-I/
0
:
,~
Q~.~~
,?~Jl'l"
""
10 1
1/1/
CLIf'50pF
CL lf l5pF -
V
10°
10°
LOAD CAPACITANCE tC l '-pF
92C5-24322
Fig.9- Typical transition time V$. load capacitance.
692
10 1
FREQUENCY
10 2
If) - kHz
Fig. 10-Typical power dissipation
92CS-24323
VI.
frequency.
File No. 846 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4086B Slash
•
0.7 Voo
14
13
12
"
10
•
92CS-24!504
Fig.17-Quiescent device current
test circuit.
~
14
Il
Y
TEST
0,3 Voo
12
"
10
•
'Ji!CS-24!!\05
Fig. 12-Noise immunity
I"
J-INH+ENABLE+
AS"'CD+EF+GH
Nt
4
E
5
V5S
14
Voo
13
0
II) Series
12
ENABLE/EXP
10
•
INHIBIT/EXP
H
92CS-23B69RI
(Top View)
TERMINAL ASSIGNMENT
CD4086B
test circuit.
693
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ File No. 847
Digital Integrated Circuits
OO(]3L}[]
Monolithic Silicon
Solid State
Division
VOD~24
High-Reliability Slash(/)Series
CD4514B/. • .CD4515B/•.•
I~
VSS~12
SO
10 51
•7 52
53
DATA I
2
DATA 2
3
DATA 3 21
DATA4 22
STROBE
I
INHIBIT.~2"'3~~~;:==-.....J
CD4514B, CD4515B
FUNCTIONAL DIAGRAM
• ••
5 55
• ••
IB 51
17
~:
High-Reliability
COS/MOS 4-Bit Latch/4-to-16
Line Decoder
For Logic Systems Applications in Aerospace,
Military, and Critical Industrial Equipment
TERMINAL ASSIGNMENT
CD4514B
CD4515B
20 SIO
19
sir
14
13
16
15
SIZ
513
514
515
CD4514B Output "High" on Select
CD4515B Output "Low" on Select
STROBE
DATA I
DATA 2
Features:
57
56
55
54
53
51
52
• Strobed input latch
• Inhibit control
The RCA·CD4514B'" and CD4515B'" "Slash" (I) Series are
monolithic integrated circuits consisting of a 4·bit strobed
latch and a 4·to·16 line decoder. The latches hold the last
input data presented prior to the strobe transition from 1 to
0. Inhibit control allows all outputs to be placed at 0
(CD4514B) or 1 (CD4515B) regardless of the state of the
data or strobe inputs.
Applications:
so
V5.
• Digital multiplexing
,_
VDD
2
INHIBIT
2.
23
22
21
20
19
18
17
16
10
15
I.
13
-,,,,12,--_=--
• Address decoding
• Hexadecimal/BCD decoding
DATA 4
DATA 3
,'0
511
58
59
51'
SIS
512
.13
92CS-24554
• Program·counter decoding
• Control decoder
The decode truth table indicates all combinations of data
inputs and appropriate selected outputs.
These devices are electrically and mechanically identical with
standard COS/MOS CD4514B and CD4515B types described
in data bulletin 814 and DATABOOK SSD·203 Series, but are
specially processed and tested to meet the electrical, mechani·
cal, and environmental test methods and procedures established
for microelectronic-devices in' MI L·STD-883.
DECODE TRUTH TABLE (Strobe = 1)
INHIBIT
For a description of these screening levels and for detailed
. information. on test methods, procedures, and test sequence
employed with high·reliability COS/MOS devices refer to
High·Reliability Report RIC·102C· "High·Reliability COS/
MOS CD4000A "Slash" (IJ Series Types':
The CD4514B and CD4515B "Slash" (I) Series types are
supplied in 24·lead dual·in·line ceramic packages ("0" suffix),
in 24·lead ceramic flat packages ("K" suffix), or in chip form
("H" suffix).
.6.
Formerly C04064A and CD4065A. respectively.
694
c
B
A
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
x
x
X
X
0
0
0
0
The packaged types can be supplied to six screening levels I1N,/1R.ll,/2.13.14·- which correspond to MIL-STD·883
Classes "A", "B", and "C". The chip versions of these types
can be supplied to three screening levels -/M,/N, and IR.
x ;:
DATA INPUTS
D
1
1
1
1
0
0
0
0
1
,
0
1
0
1
SELECTED OUTPUT
CD4514B • Logic 1 (High I
CD4515B • Logic 0 (Lawl
so
SI
S2
S3
S4
S5
S6
S7
58
S9
510
Sl1
S12
S13
5,4
515
AU Outputs:. 0, CD4514B
All Outputs ~ 1, C04515B
Don't Care
9·14
File No. 847 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CD4514B. CD4515B Slash
II) Series
=2S0C
MAXIMUM RATINGS. Absolute-Maximum Values:
OPERATING CONDITIONS AT TA
STORAGE-TEMPERATURE RANGE ...........•. -65 to +1500 C
OPERATING-TEMPERATURE RANGE ..•........ -55 to +125 o C
DC SUPPLY-VOLTAGE RANGE
V DD .................................... -0.5 to +18 V
DEVICE DISSIPATION (PER PACKAGE) . . . ... .•.... .. 200 mW
ALLINPUTS .................. _......... Vss" V, .. VDD
LEAD TEMPERATURE (DURING SOLDERING):
At dinance 1116 ± 1/32 inch (1.59 ± 0.79 mm)
For maximum reliability, nominal operating conditions should be
selecred so that operation ;s always within the following ranges
from case for 10 seconds max. ........••.•......•
• All voltage values are referenced to
Characteristic
V DD
Supply Voltage Range
-
Input Voltage Swing
(Recommended Vss to VOOI
-
266°C
Vss terminal.
Min.
Ma._
3
18
Units Fig.
V
-
V
0.2V DD -0.5 V
to
to
0.8 V DD V DD +
(Anyone 0.5 V
input)
Setup Time
5
10
250
100
None
ns
A
Strobe Pulse Width
5
10
350
100
None
ns
A
92C5-24598
.Watleforrns lor setup time and st;obe pulse width.
lin'll
ABeD
ABeD
A BCD
DATA I
ABeD
ABeD
DATA 2 3o--t.:>o---.t-r~)-,....__-l
l' B c'6
II
so
9
"
o 52
8 53
7 54
6 55.
• 56
ABelS
ABCD
ABeD
A SCD
A
SCO
ABeD
STROBE
ABCD
INHIBlT 23
i
*
* STANDARD
ALL IN~UTS PROTECTED BY
COS/MOS
PROTECTION NETWORK
92CL- 23770RI
4-
B CD
A BCD
I.
57
sa
1759
20510
19511
14512
13515
16514
5 515
THESE INVERTERS
USED ONLY ON
CD4515B
V55
Fig. I-Logic diagram. for CD4514B and C04515B.
695
CD4514B,CD4515B Slash (I) Series
File No. 847
STATIC ELECTRICAL CHARACTERISTICS
CHARAC·
TERISTIC
Quiescent Device 1
Current
Output Voltage 1
Low·Level
High·Level
TEST
CONOI·
TlONS
SYMBOL
Vo(V)
..
*
IL
LIMITS
VOH
25°C
UNITS
1250 V
V
Min.
Max.
Min.
Typ.
Max.
Min .
Max.
5
10
15
-
5
-
5
10-
-
-
-
-
0.02
0.02
0.02
300
200-
0.550.01
0.D1
-
3
5
10
15
3
5
10
15
VOL
-55°C
VOO
-
10-
-
-
0.50.01
0.D1
0.5-
-
-
-
2.34.99
9.99
14.5-
0
0
0
5
10
15
-
4.95
9.95
14.45-
-
2.254.99
9.99
-
-
-
-
-
JlA
0.05
0.05
0.55-
-
V
-
-
Threshold Voltage
N·Channel
VTHN
10 = -20JlA
-0.7-
-3-
-0.7-
-1.5
-3-
-0.3-
-3-
P·Channel
VTHP
10=20JlA
0.7-
3-
0.7-
1.5
3-
0.3-
3-
1.53-
2.26
4.5
6.75
-
1.4
2.9-
-
-
2.25
4.5
6.75
-
-
1.5
3-
-
-
-
-
Noise Immunity 1
Any Input
VNL
0.8
1
1.5
4.2
9
13.5
5
10
15
1.5
3-
-
-
-
0.8
1
1.5
5
10
15
1.4
2.9-
-
VNH
4.2
9
13.5
-
-
1.53-
0.4
5-
0.5
-
0.4-
0.8
-
0.3
-
0.5
1.5
lOt
15
1.1
-
-
2
7.8
4.6
2.5
5-
-0.25
-1
-0.2-0.8-
-0.4
-1.6
-
0.65
-0.62
-
0.9-
-0.5-
-0.9
-3.5
-
-0.35
-
-
-
V
V
Output Orive2
Current:
N·Channel
(Sink)
P·Charinel
(Source)
Oiode Test 3
100 JlA Test Pin
Input Current
... For CD45148
*
For CD4515B
ION
lOP
*
-0.15
-0.60
mA
9.5
5t
lOt
13.5
15
-
-
-
-
1.5-
-
-
1.5-
-
1.5-
V
Any Input
15
-
-
±10-5
±1
-
-
JlA
VDF
II
-
-
-
-
mA
See Note 1
t See Note 2
limits witlrblack dot (e) designate 100% testing. Refer to A Ie 102C "High-Reliability COS/MOS CD4000A Slash II) Series Types", Tables 2
through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent 100% .testing.
Note 1: Comalete functional test, all inputs and outputs to truth table.
Note 2: Test is either a one input or a one outputonly.
696
Note 3: Test on all inputs and outputs.
CD4514B, CD4515B Slash (II Series
File No. 847
DYNAMIC ELECTRICAL CHARACTERISTICS AT T A = 25°C; Input tr.tt = 20 ns. CL = 50 pF
TEST CONDITIONS·
CHARACTERISTIC
SYMBOL
LIMITS
VDD
Volts
Propagation
Delay Time:
Strobe or Data
tpHL·
tpLH
Inhibit
Transition Time:
High-to-Low
tTHL
Low-to-High
tTLH
Average Input Capacitance
C,
UNITS
TYP.
MAX.
5
550
1100·
10
225
450·
15
5
150
400
800·
-
10
150
300·
15
100
-
5
100
200·
10
50
100·
15
40
80
5
200
400·
10
100
15
60
-
5
-
Any Input
ns
ns
200·
pF
Limits with black dot (e) designate 100% testing. Refer to RIC...1Q2C "High~Reliability COS/MOS CD4000A Slash (J) Series Types",
Tables 2 through 7 for testing sequence. All other limits are designer's parameters under given test conditions and do not represent
100% testing.
* Tests are either several inputs or several outputs.
VDD
(VOO-vNH)
~
VDD
6
22
21
VNL
I.
I.
20
TO
TERMINAL
12 OR 24
I.I.
18
17
VOL.TMETER
10
"
12
I.
17
15
10
15
12
"13
"13
92CS-24539
Fig. 2-Noise immunity test circuit.
92C5-24541,)
Fig. 3-Quiescenr device current test circuit.
697
CD4614B.iCD4515B Slash (I) Series _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ . File No. 847
Voo
82"1-24542
Fig. 4 -Dynamic poMr diu/pst/on tI,t circuit lind wIIWlform.
Voo
Fig.5 '-Switching
rim. r.t circuit and waveform,.
nC'-Z4545
ORAIN-TO-SOURCE VO~TAGE (VOS1-V
1"
I
z
I
~iPf:
Km~~~'
' ~,.\!I
"
'~
. SOpPl-"f VO\..'T"G'E. _\~
300
'J
;- 250
!
'"
;:
I
200
'"
I
li
g '50
i:i
.\0\1"
,
ti
~
i
~
!i
1+1:
5: 11
~
-j!
,.v
100 •
W
W
~
W
w
ro
~
H
~
~
LOAD CAPACITANCE (CL1- pF
LOAD CAPACITANCE ICL )-pF
92CS-24501
92CS'24322
Fig. 6- Typical propagation delay vs. load capacitance
(clock or enable to output).
Fig. 7- Typical transition time VI. load capacitance.
II
~
10: AMBIENT TEMPERATURE ITA I =25-C
4
I II
I
I II,.~
2
? .0'
~
:.'"'"
~
z
.0
0
;:
g
d
If
"",'"
2
--
.0'
"i
..""
~
10
15
SUPPLY VOLTAGE (Voo)-V
20
92C5-24508
,j-
..o"~
,/
'''~71 ,0
?-1
""
;,jJ"
6
4
-CV'O pF
iiiC 2
.0
'" 46
5
o
6
4
,/
--CL cl5pF
,/
.'v
0.12
IIII I
/
IIII
468 1
2
468 10 2
4681022
FREQUENCY
(fI -
46810:52
468104
kHz
92C5-24509
Fig. 8- Typical maximum-clock-frBquency vs. supply voltage.
704
Fig. 9- Tvpical power dissipation characteristics.
File No. 857 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CD4518B, CD4520B Slash (I) Series
CLOCK
INPUT
-------------l
I
I
I
I
I
I
I
I
L ____ .:!:.4.,./20B _ _ _ _ _ J
92CM -24011
Fig. to-Ripple cascading of four counters with positive-edge triggering.
92C5-24513
Fig. 11- Noise immunity test circuit.
I.
2
3
VDD
I.
"
14
13
12
"
10
9
92C5-24514
92CM-24512
Fig. 13- Quiescent device current
test circuit.
Fig. 12-Synchronous cascading of four binary counters with negative-edge triggering.
VOD
TERMINAL ASSIGNMENT
QII------,
l
jf
t20 os
O%
20 ",
~
I 10~.
VARIABLE ---l
I.
2
3
I.
Voo
RESET 8
"
14
13
12
a4.
a3.
a2.
"
al.
10
9
ENABLE B
CLOCK B
(TOP VIEW)
50%
WIDTH
CLOCK A
ENABLE A
alA
a2A
a3A
a4A
RESET A
Vss
Voo
L
CD4518B and CD4520B
92C5-24515
Vss
.
92C5-24510
Fig. 14-·Power dissipation test circuit and waveform.
705
OO(]3LJ[]
Digital Integrated Circuits
Solid State'
Division
Application Note
ICAN-6000
Handling and Operating Considerations
for MOS Integrated Circuits
by S. Dansky
R. E. Funk
This Note describes practices for handling and operating
MOS integrated circuits that will guard against device damage
and assure optimum performance.
Table I - General Handling Considerations
Should b.
Should be
conductive
Handling Considerations
The input protection networks incorporated in all RCA
COS/MOS devices are effective in a wide variety of device
handling situations', To be totally safe, however, it is
desirable to restate the general conditions for eliminating all
possibilities of device .damage,
Handling Equipment
x
Metal Parts of Fixtures
x
and Tools
Handling Trays
Soldering Irons
Because MOS devices have extremely high input resistance, Table Tops
they are susceptible to damage when exposed to eXlremely Transport Carts
high static electrical I.!harges. To avoid possihle damage to
the devices during h~ndling. testing. ur actual u?cration. Manufacturing Operating
Personnel
therefore. the followlllg procedures should be followed:
x
X
X
X
1. The leads of devices should be in contact with a
conductive material, except when being tested or in
actual operation, to avoid build·up of static charge.
2. Soldering-iron tips, metal parts of fixtures and tools,
and handling facilities should be grounded.
3. Devices should not be inserted into or removed from
circuits with the power on because transient voltages
may cause permanent damage,
4. Signals should not be applied to the inputs while the
device power supply is off.
5. All unused input leads must be connected to either
VSS (ground) or Von (device supply), whichever is
appropriate for the logic circuit involved.
Table I indicates general handling procedures recommended
to prevent damage from static electrical charges,
grounded to
common point
General Handling of Devices
X
(Static Discharge Strapsl
• (Utilize
grounded metal
wrist straps)
• (Utilize
grounded metal
wrist straps)
Total protection results when personnel and materials are all at
the same or ground potential.
Dry weather {relative humidity less than 30%1 tends to multiply
the accumulation of static charges on any surface. Conversely ~
higher humidity levels tend to reduce the magnitude of the
static voltage generated. In a low-humidity environment, the
handling precautions listed above take on added importance and
should be adhered to without exceptions.
•
l-megohm series resistor.
Handling of Unmounted Chips
In handling of unmounted chips, care should be taken to
avoid differences in voltage potential. A conductive carrier,
or a carrier having a conductive overlay, should be used.
Another important consideration is the sequence in
which bonds are made; the VOO (device supply) connection
should always be made before the VSS (ground) bond.
in which the proper voltages are applied, the board is no.
more than an extension of the leads of the device mounted
on the board.
It is good practice to put conductive clips or conductive
tapel on the circuit-board terminals. This precaution prevents
static charges from being transmitted through the board
wiring to the devices mounted on the board.
Handling of Subassembly Boards
After COS/MOS units have been mounted on circuit
boards, proper handling precautions should still be observed.
Until these subassemblies are inserted into a complete system
Automatic Handling Equipment
When automatic handling equipment is used, static
electricity may not always be eliminated through grounding
706
I See TableU for sources of anti-static materials.
3-74
ICAN-6000
techniques alone. Automatic feed mechanisms .must be
insulated from the devices under test at the point where the
devices are connected to the test set. The device-insulated
part of the automatic handling mechanism (anvil transport)
. can generate very high levels of static electricity which are
developed by the continuous flow of devices sliding over and
then separating from the anvil. Total control of these static
voltages is critical because of the high throughputs associated
with automatic handling.
Fortunately, the resolution of this problem is simple,
practical, and inexpensive. Ionized-air blowers, which supply
large volumes of ionized air to objects that arc to be charge
neutralized, are commercially available from many supply
sources. Field experience with ionized-air techniques reveals
this method to be extremely effective in eliminating static
electricity when grounding techniques cannot be used.
Lead Bending and Forming Considerations
Other problems that can occur in handling COS/MaS
devices relate to the proper handling of leads during
mounting of devices. In any method of mounting integrated
circuits that involves bending or forming of the device leads,
it is extremely important that the leads be supported and
clamped between the bend and the package seal, and that
bends be made with extreme care to avoid damage to lead
plating. In no case should the radius of the bend be less than
the diameter of the lead, or in the case of rectangular leads,
such as those used in RCA 14·lead flat-packaged integrated
circuits less than the lead thickness. It is also extremely
import':"t that the ends of the bent leads be perfectly
straight and parallel to assure easy insertion through the holes
in the printed-circuit board.
Bending, forming, and clinching of integrated-circuit
leads produce. stresses in the leads and can cause stresses in
the seals if the above precautions arc not taken. In addition,
wide variations in temperature during normal use result in
stresses in the device leads. Tests of 14-I,ead flat-pack
integrated circuits, conducted under worst-case conditions in
which the packages were rigidly attached to posts extending
from the printed·circuit board, showed that over a tempera·
ture swing of ISOoC (from -55 0 C to +125 0 C) the stress
developed in the leads, the tensile pull on the leads, the shear
stress introduced on the seal, and the tensile stress developed
in the seal were all well within the limits for these materials.
The use of thermal- stress·relief bends is, therefore, not
necessary .
Soldering Time and Temperalure
All device leads can withstand exposure to temperatures
as high as 265 0 C for as long as ten seconds, and as close as
1/16 ± 1/32 inch from the body of the device.
Storing of COS/MOS Chips
COS/MaS chips, unlike most packaged devices, are
non-hermetic devices, fragile and small in physical size, and
therefore require the following special handling considera·
tions:
I. Chips must be stored under proper conditions to
assure that they are not subjected to a moist and/or
contaminated atmosphere that could alter their
electrical, physical, or mechanical characteristics.
After the shipping container is opened, the storage
temperature should not exceed 400 C and the
environment should be clean, dust·free, and less than
50% relative humidity.
2. After mounting and bonding, these non·hermetic
chips should not be subjected to moist or contaminated atmospheres that might cause the development
of electrical conductive paths across the relatively
small insulating surfaces. In addition, proper consideration must be given to the protection of these
devices from other harmful environments which
could conceivably adversely affect their proper
performance.
For further information on COS/MaS chip handling, refer to
File No. 517, "CD4000AH Series COS/MaS Chips".
Storing of Printed-Circuit Boards
Excessive humidity (greater than 60%) should be avoided
during circuit-board check-out to prevent the false impression of excessive device internal leakage. High relative
humidity may cause leakage paths between closely spaced
elements of the circuit boards, such as the terminals and
insulated metallized connection strips. Normally this added
leakage is not significant in non-COS/MaS devi~es. However,
when the nanoampere-Ieakage advantages of COS/MOS
devices are desired, leakage currents un circuit boards or
non-hermetic modules which are affected by high humidity
become of major concern and must be controlled by coating,
cleaning, or better environmental controls.
Effects of Humidity on Static Eloctricity
Dry weather (relative humidity less than 30%) tends to
multiply the accumulation of static charges on any surface.
Conversely, higher humidity levels tend to reduce the
magnitude of the static voltage generated. In a low-humidity
environment. the handling precautions listed in Table I take
on added importance and should be adhered to without
exceptions.
Electrical Failure Modes Due To Improper Handling
When the possibilities exist for appreciable static-energy
discharge, and proper handling techniques are not used,
electrical damage can result as follows:
(a) shorted input protection diodes,
(b) shorted or open gates,
(c) opening in metal paths frum the device input.
The presence of this type of device damage can be detected
by curve-tracer checks of the input protection diodes of the
gate·oxide protection circuits described on page 3, and also
by a check of the device characteristics, especially mutual
transconductance (gm).
707
ICAN-6000 _ _ _ _ _ _ _ _ _ _ _
~
_ _ _ _ _ _ _ _ _ _ _ _ _ __
Operating Considerations
CD4000A Series
Maximum Ratings
-65 to +150 oC
Storage-1emperature Range
Operating·Temperature Range:
Ceramic·Package Types
-55 to +125°C
Plastic·Package Types
-40 to + 85°C
DC Supply·Voltage Range:
VDD - VSS
-0.5 to +15 V
VDD - VEE
-0.5 to
VCC - Vss
-0.5 to +15 V
DC Input·Voltage Range
+ 15 V
VSS';; VI';; VDD
for CD4009A, CD4010A
VSS';; VI';; VDD ;. VCC
Vss';; VI';; 15 V
for CD4049A, CD4050A
for CD4051A, CD4052A, CD4053A:
Controls
VSS';;VI';; VDD
Signals
VEE ';;VI';; VDD
200mW
Device Dissipation (per package)
Lead Temperature (during soldering)
at a distance 1/16 ± 1/32 inch
(1.59 ± 0.79 mml from case for
+ 26SoC
10 seconds maximum
Operating Voltage
When operating near the maximum supply-voltage range
of 15 volts. care should be taken to avoid or suppress
power-supply turn-on or turn-off transients. power-supply
ripple or regulation. and ground noise: any of the above
conditions must not cause (VDD - VSS) to exceed the
absolute maximum rating.
Power supplies should have a current compliance
compatible with 'actual COS/MOS current drain.
Another good power-supply practice is to usc a zener
protection diode in parallel with the power bus. The zener
value should be above the expected maximum regulation
excursion, but should not exceed 15 volts. Fig. I illustrates a
practical zener shunt circuit. A current-limiting resistor is
included if the supply-current compliance is higher than the
zener power-dissipation rating for a given zener voltage. The
shunt capacitance value is chosen to supply required peak
current switching transients.
SUPPLytTVDD
nCS-2ZBB'S
Fig. 1 - Zener-diode shunt circuit.
Unused Inputs
All unused input leads must be connected to either Vss
or V oo , whichever is appropriate for the logic circuit
708
involved. A noating input on a high-current type (such as the
CD4009A. CD4010A. CD4041A, CD4049A, CD4050A) not
only can result in fuulty logic operation, but can cause the
maximum power dissipation of 200 milliwatts to be
exceeded and may result in damage to the device. Another
consideration with these high-current types is that a pull-up
resistor from their inputs to Vss or V OD should be used if
there is any possibility that the device may become
temporarily untcrminatcd (e.g., if the printed circuit board
driving the high-current types is removed from the chassis).
A useful range of values for such resistors is from 0.2 to I
megohm.
Input Signals
Signals shall not be applied to the inputs while the device
power supply is off unless the input current is limited to a
steady-state value of typically less than IDmilliamperes.lnput
signal interfaces having the allowable 0.5 volt above Voo or
below Vss. respectively, should be current-limited to
typically 10 milliamperes or less.
Whenever the possibility of exceeding 10 milliamperes of
input current exists, a resistor in series with the input is
recommended. The value of this resistor can be as high as
ID kilohms without affecting static electrical characteristics.
Speed, however, will be reduced due to the added RC delay.
Particular attention should be given to long input-signal lines
where high inductance can increase the likelihood of large
signal pickup in noisy environments., In these cases, series
resistance with shunt capacitance at the IC input terminals is
ICAN-6000
recommended_ The shunt capacitance should be made as·
large as possible consistent with the system speed
requirements.
Interfacing with T2L Devices
The COS/MOS hex buffers (CD4009A, CD40IOA,
CD4049A, and CD4050A) are designed to drive two
normal-power T2L loads. Other device types (such as the
CD4041 A, CD4048A, and CD4031 A) can also directly drive
at least one T2L load. Always consult the published data on
the particular COS/MOS type for this capability. Most gates
and inverters and some MSI types can drive one or more
low-power TtL loads. To provide a good noise margin in the
logic "I" state, T2L devices that drive COS/MOS devices
require a pull-up resistor at the COS/MOS input. The
COS/MOS hex buffers can also convert COS/MOS logic levels
(5 to 15 volts) to T2L logic levels (5 volts), i.e., down-level
conversion.
Rules for safe system design when COS/MOS interfaces
with T2L and both logic systems have independent power
supplies of the same voltage level but possibly on at different
times are as follows:
a) T2 L driving COS/MOS -- use I kilohm in series
with COS/MOS input
b) COS/MOS driving T2L - connect directly
Interfacing with p-MOS Devices
COS/MOS devices can operate at VDD = 0 and Vss =-.1
to -15 volts to inierface directly with p-MOS devices with no
degradation in noise immunity or other t.:haructcristics.
Interfacing with noMOS Devices
COS/MOS devices can be interfaced directly with noMOS
devices over the +3 to + 15 volt range of power supplies.
Fan-Out - COS/MaS to COS/MaS
All RCA COS/MOS devices have a de fan-out capability of
50. The reduction in COS/MOS switching speed caused by
added capacitive loading should, however, be consistent with
high-speed system design. The input capacitance is typically
5 pF for most types; the CD4009A and CD4049A buffers
have an input capacitance of typically 15 pF.
a logic "0" is 0 to 3 volts, and a logic "I" is 7 to 10 volts.
For 5-volt operation, a logic "0" is 0 to 1.5 volts. and a logic
"I" is 3.5 to 5 volts. COS/MOS noise immunity is
30 per cent of the supply voltage for the range from +3 to
+15 volts.
The inherent 30-per-cent noise immunity of COS/MOS
also permits a I-volt noise margin when interfaced with T2 L
or DTL. For example, standard T2L and DTL interfacing
with COS/MOS at a nominal V DD = Vee = 5 volts provides
at least I-volt noise margin; i.e., VOLmax(T2L) = 0.4 volt
and VOLmin(DTL) = 0.45 volt; 30% of 5 volts = 1.5 volts.
This example applies typically to the 5400/7400 series,
the 9000 series, and the 8000 series. HI NIL (300 series) can
interface with COS/MOS at a nominal VDo Vee 12 volts
with a worst-case noise margin of 2.1 volts.
Because
COS/MOS
voltage-transfer
switching
characteristics vary from 30 to 70 per cent of the supply
voltage,
system
designers
employing
COS/MOS
multivibrators, level detectors, and RC networks must
consider this variation. Application Note ICAN-6267
illustrates an accurate multivibrator design technique which
minimizes the switching-point variation.
=
=
Output Short Circuits
Shorting of outputs to VSS or VDo can cause the device
power dissipation to exceed the safe value of 200 milliwatts
for high-output-current types such as the CD4007A,
CD4009A. CD4010A, CD404IA, CD4049A, and CD4050A.
In general, outputs of these types can all be safely shorted
when operated with VOD - VSS .;; 5 volts, but may exceed
the 20D-milliwatt dissipation rating at higher power-supply
voltages. Fur cases in which a short-circuited load, such as
the base of a p·n·p or n-p-n bipolar transistor, is directly
driven. the device output characteristics given in the
published data should be consulted to determine the
requirements for safe operation below 200 milliwatts.
COS/MaS Characteristics
Quiescent Device Leakage Current (Id:
Quiescent device leakage is measured for inputs tied high
(lDD) and also for all inputs tied low (Iss), as illustrated
below:
Maximum Clock Rise and Fall Time
All COS/MOS clocked devices show maximum clock rise·
and fall-time ratings (normally 5 to 15 microseconds). With
longer rise or fall times, a device may not function properly.
Parallel Clocking
When two or more different COS/MOS devices use a
common clock, the clock rise time must be kept at a value
less than the sum of the propagation delay time, the output
transition time, and the setup time. Most flip-flop and
shift-register types are included in this rule and are so noted
in the indiv'iual data sheets.
Noise Immunity
COS/MOS inputs normally switch at 30 to 70 per cent of
the power-supply voltage. For example, for a I O-volt sup.ply,
9<'CS-22866
Quiescent Device Dissipation (P D):
Quiescent device dissipation is given by
P D = (VDD - Vss) IL
where lL = IDD or Iss
709
ICAN-6000 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Output Voltage Levels (COS/MOS driving COS/MOS):
VOL
VOH
=Low-Level(''O'')Output =10 mV' at 25°C
=High-Level("1 ")Output =Voo - 10 mV' at +25°C
Noise Immunity:
VNL = the maximum noise voltage that can be applied to
a logic "0" input (added to Vss) before the
output changes state.
VNH = the maximum noise voltage that can be applied to
a logic "\" input (subtracted from Voo) before
the output changes state.
Gate-Oxide Protection Circuits
Most COS/MOS gate inputs have the protection shown in
Fig. 2. An exception to this statement is the input network
for the CD4049A and CD4050A shown in Fig. 3. Figs. 4
and 5 illustrate the protection diodes inherently present at all
transmission-gate input/output terminals and all inverter
outputs. IeAN-62IS gives further information on protection
circuits.
The protection networks ·can typically protect against
1-2 kilovolts of energy discharge from a 250-pF source.
~
02
R
Output Drive Current:
Sink Current (IoN) = the output sink current provided by
the n-channel transistor without exceeding a given
output voltage (Vo) as shown on each data sheet.
Source Current (loP) the output source current
provided by the p-channel transistor without
dropping below a given output voltage (Vo) as
shown on each data sheet.
=
Input Current (I.):
Input current is typically 10 picoamperes (3 to 15 volts)
at TA 25°C. Maximum input currents for COS/MOS
devices are normally below 10 nanoamperes at IS volts. and
below 50 nanoamperes at T A = + 125°C.
01
25 V
a
sov
02;
GATES
"R:: 200 TO 2000
01
Vss
t=F:
03
GATES
03
D3"Z5V
L.._ _~_Vss
92'C5-22888
Fig. 3 - CD4049AICD4050A gate-input-protection circuit.
p-WELL
02"
INPUT
02"
Vss
01*
OUTPUT
Von 01*
n-SUB
p'
GATE
.,
01·2:5 V
02=50V
p'
~
92(5-22883
Fig. 4 - Transmission gate-;nput-Butput protection.
1~
VDD"
Ht-
IIss
02
•
01
01
01 = 25 V
02 = 50 V
(MOST
OUTPUTS)
9ZCS- 22884
Fig. 5 - Active (inverter) output protection.
* This
voltage may be difficult to measure depending on accuracy.
resolution, and offset voltage of test equipment used; Although
device output
or "0" limits to which RCA tests i,n manufacture
are 10 millivolts, a value of 50 miUivoits may be used for customer
measurements without compromise of device quality or system
perfonnance.
h."
710
n
92CS-2Z8S7
Fig. 2 - Normal gate-input-protection circuit.
=
AC (Dynamic) Characteristics:
Test parameters shown in the published data are
measured at T A = 25°C with a 15-pF load and an
input-signal rise or fall time of 20 nanoseconds. Actual
system delays and transition times may be increased due to
longer input rise and fall times. Graphs arc included in the
individual data sheets to illustrate. typical variation of d·elays
and transition times with capacitive loading. The designer
should use a typical temperature ·coefficient of O.3%tc for
estimating speeds at temperatures other than +2SoC.
Propagation delays and transition times increase with rising
temperature; maximum clock input frequencies decrease
with rising temperatures.
Dynamic power dissipation for each device type is shown
graphically in the published data as a function of device
operating frequency.
VDD
02
... THESE DIODES ARE
INHERENTLY PART OF
THE MANUFACTURING
PROCE:SS
-----------------------------ICAN.6000
Table II - Partial List of Materials and Equipment Available
for the Control of Static Charge
Company
Custom Material Inc.
Chelmsford, Mass.
Conductive
Foam
Conductive
Envelopes
Velofoam
#7672
Velobags
#1798M
Static
Neutralizing
Air Blowers
TEC Oynastat
05120
3M Company
St. Paul, Minn.
Ionized Air
Blower #905
Scientific Enterprises, Inc.
Bloomfield, Colo.
Micro Stat
575 Portable
Ionizer
Emerson & Cuming, Inc.
Canton, Mass.
ECCOSORB
L026
Anti·Static
Sprays
Conductive
Tape
P.C.
Con tab Shunt
See Technical
Bulletins
Scotch
Shielding Tapes
See Technical
Bulletins
711
ICAN-6224 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
OO(]5LJD
.Digital Integrated Circuits
Solid State
Division
Application Note
ICAN-6224
Radiation Resistance of the
COS/MOS CD4000A Series
by M. N. Vincoff
Complementary MOS (COS/MOS) integrated circuits
possess many advantages which recommend their use in
radiation-susceptible space and military environments.
Several of the most significant of these advantages are:
ultra-low standby-power consumption, high noise immunity,l extremely high packaging density, and inherently
high reliability.2 These advantages, along with the improved
radiation resistance of the RCA CD4000A series over the
CD4000 series described in earlier radiation studies,3 exhibit
the maturity reached by the MOS technology since 1971.
A number of studies of the radiation resistance of
complement~ry MOS devices by NASA, the Navy and various
companies in the space industry have revealed two areas of
prime concern.4- 15 The first, permanent radiation exposure,
as experienced in a space environment, causes a shift in
threshold or switching voltage and a possible increase in
leakage current, IL. The second, transient radiation exposure,
as experienced in an atomic environment, causes the outputvoltage levels to respond to a pulse of ionizing radiation; this
effect could change the state of the logic circuitry and
require resetting of that circuitry for proper equipment or
system operation.
Permanent-Radiation Resistance
The CD4000 series was resistant to permanent radiation
levels of 2 x 104 rads (approximately 10 12 e/cm2). Now,
however, RCA CD4000A-series devices without special
shielding have been found to be resistant to radiation levels
up to 2 x 105 rads (approximately 1013 e/cm 2 ), as shown in
Fig. 1.3 In this figure the change in switching voltage LNS is
plotted as a function of dose. The value of boVS was
calculated from the average value of boVTN and boVTP for the
devices mentioned. The new radiation level of the CD4000A
series represents a significant improvement over the CD4000
series. In addition, with minimal shielding (for example,
1/16-inch of aluminum) the CD4000A series can be used in
application with levels of radiation up to 3 x 106 rads
(approximately 10 14 e/cm2 ).
712
Voo: 10 VOLTS, DOSAGE :Co 60 GAMMA SOURCE
*
I CD4QQ7A
2 CD4011A *
3 CD4016A it
4 CD4013A 115 CD40QIA *
;;;
I-
el
6 C04004A-*
3
7 C04007 *It
8 CD4QQI _.
~
'"
>
""
(RADS)
10 10
I
lOll
I
10 13
lOll.
(e/cm 2
)
... BIAS APPLIED 10D % OF THE TIME
APPLIED
50% OF THE TIME
.*' BIAS
92C5-22496
Fig. 1 - Permanent radiation resistance of CD4000A· and C04000-
series devices.
Transient-Radiation Resistance
The resistance of the CD4000A series to transient
radiation is expected to be ten times better than that of the
CD4000 series, which can withstand pulses of radiation of
approximately 10 10 rads/s. S
Design Considerations
The resistance of the CD4000A-series devices to either
permanent- or transient-radiation exposure can be increased
by providing either minimal shielding through the design of
the equipment enclosure containing the devices or by
locating the devices deep within the equipment in which they
are used. In any case, the action taken will depend on the
constraints dictated by the radiation environment imposed
by the system or program. Each application must be tested
and the results analyzed with the data in this Note as criteria.
Test items to be considered are radiation environment, which
11-73
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN·6224
will vary greatly depending on dosage rate; time of exposure;
amount of normal shielding; distance of the device from the
radiation source; shielding afforded by the atmosphere;
power·supply voltage selection; and switching cycles used
during exposure. For example, consider the effects of
permanent radiation on two spacecraft in 90·degree orbits at
600 and 1500 nautical miles from the earth, respectively.
The dose·depth is determined as shown in the curves of
Fig. 2. In these curves the dose in rads(AI)/day is plotted as
a function of the thickness of spacecraft aluminum required
to shield the devices from trapped electrons and protons.4
10'
10'
10'
10'
~
~
;:: 10"
;: 10$
:!
~
:!
:g
10 3
~
AI THICKNESS-MILS
(a) 600-MILE. 90" ORBIT
10"
THICKNESS-MILS
(bl 1500-MILE, 90" ORBIT
Fig. 2 - Oose-depth curves for trapped electrons and pro tons in spacecraft in orbit.
2. Vincoff, M. N. and Schnable, G. L., "COS/MOS is a
High·Reliability Technology", RCA Technical Publica·
tion ST·6112.
3. Ezzard, G., "Radiation Effects on COS/MOS Devices",
RCA Application Note ICAN·6604 (covers CD4000
series).
4. Brucker, G. J., "COS/MOS Device Sensitivity in Outer·
Space Radiation Environment", Report No. X72002,
Oct. 17, 1973, RCA Astro Electronics Division.
5. Dennehy, W. J., et aI., "Transient Radiation Response in
Complementary·Symmetry MOS Integrated Circuits",
RCA Technical Publication ST 4308.
6. Poch, W. J., and Holmes·Siedle, A. G., "Permanent
Radiation Effects in COS/MOS Integrated Circuits",
RCA Technical Publication ST4174 (covers CD4000
series).
7. Schambeck, W., "Radiation Resistance and Typical
Applications of RCA COS/MOS Circuits in Spacecrafts",
Telemetry Journal, June/July 1970 (covers CD4000
series).
.
8. Schambeck, W., "Effects of Ionizing Radiation on
Low·Threshold C·MOS . Integrated Circuits", DFVLR
Institute for Satellite Electronics, Oberpfaffen·hofen, W.
Germany, April 1972 (covers CD4000A series).
9. Danchenko, V., "Radiation Damage in MOS Integrated
Circuits, Part I", Sept. 1971, Goddard Space Flight
Center, Report X·711·71410 (covers CD4000A series).
10. Poch, W. J., and Holmes·Siedle, A. G., "The Long·Term
Effects of Radiation on Complementary MOS Logic
Networks", IEEE Transactions on Nuclear Science
Conclusion
The RCA COS/MOS CD4000A series exhibits improved
radiation resistance over the CD4000'series, and is well suited
for use in many applications in which permanent and
transient radiation effects are factors. When stringent
radiation requirements are imposed, additional shielding can
be employed to increase the radiation life of COS/MOS
CD4000A'series devices to any desired level, i.e., to make
their radiation resistance equivalent to that of bipolar
devices.
Custom COS/MOS devices that can resist a radiation level
of 106 rads are now being developed by means of an
aluminum implantation process which re~uires one
additional masking step in the production line. I I· 4
NS·17 (6), Dec. 1970 (covers CD4000 series).
II. Smith, J. M., and Murray, L. A., "Radiation Resistant
COS/MOS Devices", RCA Technical Publication
ST4723.
12. King, E. E., Nelson, G. P., and Hughes, H. L., "The
Effects of Ionizing Radiation on Various COS/MOS
Integrated Circuit Structures", IEEE Transaction in
Nuclear Science, No.6, pg. 264, Dec. 1972, RCA
Technical Publication ST·6161.
1'3. Peel, John L., et aI., "Radiation·Hardened Comple·
mentary MOS Using Si02 Gate Insulators", IEEE .
Transactions on Nuclear Science, No.6, pg. 271, Dec.
1972.
14 .. Schlesier, K. M., et aI., "COS/MOS Hardening Tech·
niques", IEEE Transactions on Nuclear Science, No.6,
pg. 275, Dec. 1972.
Reference.
I. Eaton, S. S., "Noise Immunity of RCA COS/MOS
Integrated Circuit Logic Gates", RCA Application Note
ICAN·6I66.
713
RIC-102C _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Digital Integrated Circuits
OOCIBLJD
Solid State
Division
High-Reliability COS/MaS
CD4000A Slash III Series Types
Screened to M I L-STD-883
RCA COS/MOS high-reliability slash (I) series digital integrated circuits are available for applications in aerospace,
military, and industrial equipment. These COS/MOS circuits
are supplied to six screening levels (l1N, /1R, /1, 12, /3,/4)
which meet the electrical, mechanical, and environmental
test methods and procedures established for microelectronic
devices in Mll-STD-883. These six screening levels are
equivalent to Mll-STD-883 Classes A, B, and C and are
summarized in Table 1.
RCA also offers standard commercial product with a
16B-hour burn-in, designated level/5.
This bulletin defines the test procedures employed with
COS/MOS devices to meet the reliability standards required
by Mll·STD·8B3. The level /1 N part includes SEM (Scanning
Electron Microscope) Inspection to NASA·Goddard Specification GSFC-S-311·P-12A of Mll-M-38510, and Precap
Visual Inspection, Condition A, Method 2010-1, Mll·STD-
883. The level /R part includes the SEM inspection in
addition to the requirements of level /1 part. RCA also offers
the CD4000A slash (I). series screened to Mll-M·38510
(Slash (I) 05()'Series Types). For COS/MOS devices in this
series, refer to R1C-1 04A, "High-Reliability COS/MOS
MIl-M·38510 CD4000A-5eries Types".
The Product Flow Diagram shown in Fig. 1 lists a summary
of processing, screening tests, and sampling procedures
followed in the manufacture of high·reliability COS/MOS
devices.
Table 2 gives detailed information for the screening tests,
included in the Product Flow Diagram. Table 3 gives pre
burn-in and post burn-in electrical tests and delta limits for
critical test parameters. Tables 4 and 5 give test criteria for
Final Electrical and Group A Electrical Tests. Tables 6 and 7
describe Group Band C Environmental Sampling Inspection
tests.
CONDITIONING SCREENS
STABILIZATION BAKE
MIL-STD-883
201D.fA OR
2010.28
SEM
INSPECTION
AS REQUIRED
THERMAL SHOCK
TEMPERATURE CYCLING
MECHANICAL SHOCK
CENTRIFUGE
FINE LEAK
GROSS LEAK
STABILIZATION BAKE
TEMPERATURE CYCLING
CENTRIFUGE
1---,...--...
FINE LEAK
GROSS LEAK
92CL-24949
Fig. 1 - Product flow diagram. See Tables 2, 4, 5, 6, lind 7 for details.
714
9·74
- - - - - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ RIC-102C
Table 1 - Description of RCA Integrated-Circuit Screening Levels
Screening Levels"
RCA
Levels
Equivalent to MIL-STD-883,
Method 5004_ 1
Application
Description
For Packaged Devices
I1N
Class A with SEM" Inspection and
For devices intended for use
Condition A Precap Visual Inspection
where maintenance and replace-
ment are impossible and
reliability is imperative
I1R
Class A with SEM" Inspection and
Condition B Precap Visual Inspection
11
Class A with Condition B Precap
Visual Inspection
12
Class A with Condition B Pre cap
Visual Inspection. Radiographic
Inspection Omitted
Aerospace and
Missiles
Aerospace and
Missiles
For devices intended for use
where maintenance and replacement are extremely difficult or
impossible and reliability is
imperative
13
Class B
Military and Industrial
For devices intended for use
For example, in Airborne
where maintenance and replacement can be performed but are
Electronics
difficult and expensive
14
15
Class C
-
Standard
commercial
plus burn·in
Military and Industrial
For example, in GroundBased Electronics
For devices intended for use
where replacement can readily
be accomplished
Commercial and
For devices intended for use
Industrial
where a higher level of reliability
is required than can be provided
by product without a burn-in
For Chips·
IN
SEM" Inspection and Condition A
Precap Visual Inspection
For hybrid applications where
maintenance and replacement
are extremely difficult and
Aerospace and
reliability is imperative
Missiles
IR
SEM" Inspection and Condition B
Precap Visual Inspection
1M
Condition B Precap Visual Inspection
Military and Industrial
For general applications
·SEM - Scanning Electron Microscope Inspection per NASA Specification GSFC-S-311-P·12
A For details on Condition A and Condition B Precap Visual Inspection, refer to MI L-STO-883 Method 2010.1
• lot acceptance testing for ch ips is available on a custom basis
715
RIC-102C-'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Ordering Information
1_ Packaged Device and Chip Tvpe Number Identification
When ordering a packaged device or a chip, it is important
that the desired Screening Level and Package Designation
for the Packaged Device, and the desired Screening Level
for the Chip Version indicated by the appropriate suffix
letters be added to the Part Number as shown below. For
example, a CD4024A in a 14-lead dual-in-line ceramic
package and processed to meet MIL-STD-883 Class A
requirements with SEM Inspection plus Condition A
Precap Visual would be identified as the CD4024AD/1 N.
In similar manner, a CD4024A Chip having SEM
inspection plus Condition A Precap Visual would be
identified as the CD4024AH/N.
2. Data Supplied With Order for Packaged Devices
For the Following
a) Product Screening Data
RCA Screening Levels
Certificate of Compliance Signed by RCA Representative Provides lot identity. customer order identity, lists and certifies tests, methods and
conditions of required processing per MIL-STD·BB3 .................................... AII except /5
Group A Subgroup - Test Summary Attributes Data ................................... All except 15
Variables Data, Pre Burn-In and Post Burn-In ........................................ ./1 N, II R, /1./2
Radiographic Inspection Film and Film Inspection Record .............................. ./1 N, II R, II
SEM Inspection Certificate of Compliance to NASA Specification GSFC·S-311·P-12
Includes lot identification and one worst·case photograph .............................. ./1 N, II R
b) Lot Quality Conformance Data Group B and Group C Subgroups
Attributes Data Summary of the Latest Group B
and/or Group C Subgroup can be ordered at a nominal
charge.
Special Group B and/or Group C quality conformance
tests on samples from the specific lot of parts ordered
will be considered on a custom basis only.
Description of RCA COSIMOS IC High·Reliability Part Numbers
Packaged Device CD4000AD/1 N
CD4000A
-..........-...
Type
Designation
716
D
Package
Suffix
Letter
D = Dual-in-Line
Ceramic Weld-Seal
K = Ceramic
Flat Pack
F = Dual-in-Line
Ceramic Frit-Seal
Chip Version, CD4000AH/N
/1N
CD4000A
-..........-...
Screening
Level
I1N 12
/1R 13
/1
14 /5
For Description.
See Table·l
Type
Designation
H
IN
..........
Package
Suffix
Letter
Screening
Level
H = Chip
IN
IR
1M
For Description,
See Table 1
Version
RIC-102C
Table 2 - Description of Total Lot Screening (X = 100% Testing)
Test
MIL-STD-883
Method
Conditions
Conditions
SEM Inspection
/1N
RCA Screening Levels'
/lR
/2
/3
/1
NASA Per GSFC·S·311-P-12
-
-
X
X
2010.1
A
X
Precap Visual
-
2010.1
B
Preseal Bake
16 to 32 hrs at 200°C
-
-
-
48 hrs. at 150°C
1008
Precap Visual
Seal & Lot Identification
Stabilization Bake
/4
-
-
-
-
-
X
X
X
X
X
X
X
X
X
X
X
-
X
X
X
X
X
X
C
X
X
X
X
X
X
-
Thermal Shock
15 cycles
1011
C
X
X
X
X
-
-
Temperature Cycling
10 cycles
1010
C
X
X
X
X
X
X
5 pulses, Y 1 direction
2002
B
X
X
X
X
-
-
Centrifuge
Y2, Yl direction
Y 1 direction only
2001
2001
E
E
X
X
X
X
-
-
-
-
-
-
X
X
Fine Leak
-
1014
A
X
X
X
X
X
X
Mechanical Shock
Gross Leak
1014
'C
X
X
X
X
X
X
-
X
X
X
X
X
-
-
-
-
X
X
X
X
see Table 3
-
-
X
X
X
X
-
-
240 hours
168 hours
1015
1015
Dar E
Dor E
X
X
X
X
-
-
-
-
-
X
-
Delta Requirements
(See Table 3)
-
-
X
X
X
X
-
-
-
-
-
-
-
-
-
-
-
see Table 4
see Table 4
X
X
X
X
X
X
X
X
X
X
X
S
1 view
2012
X
X
X
-
-
-
-
2009
X
X
X
X
X
X
Serialize
Pre Burn-in Electrical
Burn-in
Post Burn·in Electrical
See Note 1
-
Electrical Tests
Final Electrical
a) 25°C
b) -55 and +125°C
Radiographic Inspection
External Visual
-
Note"': See specific type data bulletin for test conditions and limits
• RCA screening level
15 consists of a 1GB-hour burn-in screen performed on standard commercial product. The ambient test temperature is the
maximum possible without exceeding device thermal ratings. After burn-in, /5 devices meet all of the electrical requirements specified in the
appropriate commercial data bulletin. Reference: RCA DATABOOK S50-203.
Table 3 - Pre and Post Burn-In Electrical Tests and Delta Limits (TA= 25°C)
CRITICAL PARAMETERS
(at VDD = 10 V)
SYMBOLS
LIMIT VALUES: For specific CD4000A Series Types and corresponding
lllimits for High-Reliability Versions •
Total
IL(max)
0.1
0.5
1
2
5
10
15
25
50
Unit
Jl.A
lllL
0,05
0.2
0.3
0.5
1.0
1.3
1.5
2.5
5.0
Jl.A
QUIESCENT DEVICE CURRENT
THRESHOLD VOLTAGE:
"N" Channel
"p" Channel
llVTH"N"
llVTH"P"
...
DEVICE DRAIN CURRENT:
Total
"N" Channel
"P" Channel
Total
IDs(min)
llIDS"N"
llIDS"P"
-0.1·0.5
±0.1
±0.1
•
+0,3
•
+0.3
0.5·2
±0.5
±O,5
2-5
±0.75
±O.75
5 ·10
±1
±1
10 - 25
±2
±2
25·50
±5
±5
V
V
mA
mA
mA
.,
* For example, If a specifiC
CD4000A Series type has a maximum qUiescent device current of 0.5 pA at T A"" 2SuC, RCA Will test to a
.6. limit of 0.2 iJA for the high-reliability version of that type. In a similar manner, if a type has a quiescent device current rating of
SpA, RCA will test to a .6. limit of 1.0 pA.
717
RIC-102C _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Table 4 - Final Electrical Tests
TEST CRITERIA
TEMPERATURE
(TA)
TEST
LEVELS
/1N,/1R,/l,/2·
LEVEL
13
LEVEL
14
+25°C
Selected Static Parameters
100%
100%
100%
+125°C
Selected Static Parameters
100%
100%
-
-55°C
Selected Static Parameters
100%
100%
-
+25°C
Selected Dynamic Parameters
100%
100%
-
Table 5 - Group A Electrical Sampling Inspection
LTPD
SUBGROUP
TEST
CONDITION
LEVELS
11N, /1R, /1,/2
LEVEL
13
LEVEL
14
1
Selected Static Parameters
TA.= +25°C
5
5
5
2
Selected Static Parameters
TA = +125°C
5
7
10
3
Selected Static Parameters
TA = -55°C
5
7
10
4
Selected Dynamic Parameters
TA = +25°C
5
5
5
Details of static and dynamic tests, conditions, and limits appear in the
High-Reliability Devices DATABOOK 550·207. Tested static and
dynamic characteristics are identified for each Slash (II Series type
by a dot (-,
Table 6 - Group B Environmental Sampling Inspection (Note 1)
MI L-STD-883
SUBGROUP
TEST
REFERENCE
CONDITIONS
LTPD
LEVELS
/1N,/1R,
/1,/2
LEVEL
13
10
15
LEVEL
14
1
Physical Dimensions
2008
Test Condo A per
applicable data sheet
20
2
Marking Permanency
2008
Test Condo B per
Par. 3.2.1
4devices._
(no failures)
Visual and Mechanical
2008
Test Condo B
10 X mag.
1 device
(no f a i l u r e ) -
Bond Strength
2011
Test Condo D
20
5
15
10
15
15
10
15
15
10 Devices minimum
3
Solderability
2003
4
Lead Fatigue
2004
Test Condo B2
any 5 leads
Fine Leak
1014
Test Condo A
Gross Leak
1014
Test Condo C
Note 1: Group B tests are performed on"each inspection lot per requirements of MIL-M-38510.
Nota 2: Operating life circuits are included in specifictvpe high-reliability data bulletins.
718
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ RIC-102C
Table 7 - Group C Environmental Sampling Inspection (Note 11
LTPD
MI L-STD-883
SUBGROUP
TEST
REFERl:NCE
1
Thermal Shock
Temperature Cycling
Moisture Resistance
Fine Leak
Gross Leak
Critical Post Tests - Note 3
2
Mechanical Shock
Vibration, Var. Freq.
Constant
Accel~ration
Fine Leak
Gross Leak
Critical Post Test - Note 3
CONDITIONS
LEVELS
/IN,I1R, LEVEL
/3
11,/2
LEVEL
/4
1011
1010
1004
1014
1014
Test Condo C
Test Condo C
No Voltage Applied
Test Condo A
Test Condo C
10
15
15
2002
2007
2001
1014
1014
Test Condo
Test Condo
Test Condo
Test Condo
Test Condo
10
15
15
10
15
15
B, 0.5 ms
A
E
A
C
3
Salt Atmosphere
1009
Test Condo A
Omit Initial Conditioning
4
High Temp .. Storage
Critical Post Tests - Note 3
1008
Test Condo C
1000 hours
7
7
7
5
Operating Life
Critical Post Tests - Notes 2
and 3
Steady State Bias
1005
TA = 125°C, 1000 hrs.
Test Circuit (Note 21
5
5
5
1015
Test Condo A, 72 hrs.
At TA = 150°C (Note 31
7
-
6
Critical Post Tests - Note 3
-
Note 1: Group C tests are performed at 3·month intervals for
reliability history.
Nota 2: Operating life circuits are included in specific type high·
reliability data bulletins.
Nota 3: Static parameters and limits are shown in High-Reliability
Devices DATABOOK 850-207, and in specific type high-
reliabilitr data bulletins.
719
RIC-104A _ _ _ _ _ _ _ _ _--,-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
rn1CBLlD
Solid State
Division
Digital Integrated Circuits
High-Reliability COS/MaS
MIL-M-38510 CD4000A Series Types
RCA COS/MaS high-reliability digital integrated circuits are
available for. applications in aerospace, military, and industrial equipment where screening requirements of MI L-M38510 are specified_ COS/MOS. circuits are supplied to the
three screening classes of MI L-M-3851 0 as specified in
MIL-STD·883 Method 5004 Classes A, B, and C. Table 1
describes the screening levels.
This bulletin defines the procedures employed to manu·
facture COS/MaS CD4000A Series devices to meet the
reliability requirements of MIL·M·38510. These COS/MaS
devices are available in flat pack and dual·in-line ceramic
packages.
Since 1970, RCA has been working closely with various
aerospace and military agencies to qualify and provide
COS/MaS devices to MIL·M-3B51 0 specifications. Among
these agencies are the NASA Goddard Space Flight Center,
NASA Marshall Space Flight Center, NASA Headquarters
Center in Washington, Rome Air Development Cen,er, and
the Defense Electronic Supply Center (DESC) at Dayton, a
branch of the Defense Supply Agency.
MI L·M-3851 0 is· the general specification for integrated
circ.uits and is more comprehensive than MIL·STD-883. This
general specification, introduced a year after MIL·STD-883
was in existence, adds a number of quality constraints not
included in MI L·STD-883, which is a specification of test
methods, procedures, and screening tests. COS/MaS parts are
provided to MIL·M-38510 under a series of /050 numbers of
procedures followed in the manufacture of high·reliability
COS/MaS devices. The additional criteria for each class of
product are indicated by an X in Table 2. Also provided in
MI L·M·3851 0 tests are PDA's (Per·Cent Defective Allowable)
of 10 per cent for the three burn·in operations performed on
Class A product, and 10 percent for the one burn·in of Class
B product. Table 3 provides a list of the COS/MaS devices
for . which MIL·M·38510 /05Q-number specification sheets
have been written. The /054(CD400BA) and /058(CD4016A)
types are still in preliminary status and are available for
custom screening. Table 4 compares the screening require-
ments for COS/MaS integrated circuits to Class A Parts of
MI L·M·3851 O. Tables 5 and 6 give test criteria for Final
Electrical and Group A Electrical Tests. Tables 7 and 8
describe Group Band C Environmental Sampling Inspection
tests. Table 9 describes the product·assurance program RCA
implements in the performance of MIL·M·38510. Table 10
provides a classification guide for COS/MOg circuits.
The processing of high·ieliability COS/MOS integrated
circuits is shown in Fig. 3. The wafer processing and
metallization steps, the wafer finishing operations, and the
wafer testing are the same as for standard·product COS/MOS
devices. For Class A parts, an SEM inspection step is inserted
after the wafer processing and metallization, as shown in Fig.
2. After these four basic operations are completed, the tested
wafer is subjected to the special high·reliability processing.
As shown in Fig. 3, thirty·five additional processing and
screening operations are required for Class A COS/MOS
parts.
which nine are in existence. These nine numbers cover
twenty·seven COS/MaS types. Parts meet requirements
similar to those of Classes A, 8, and C of MIL·STD·883,
Method 5004 screening, except that additional requirements,
including more test conditions and tightened limits, are
imposed. The Product Flow Diagram shown in Fig. 1 lists a
summary of
processing,
screening tests, and sampling
Orderi ng Information
Order COS/MOS MI L·M·38510 Series types by giving the
appropriate reliability screen as shown in Fig. 4. For
example, the CD4013AD processed to Class A requirements
should be marked MIL·M·38510/05101ACA.
Table 1: Description of MI L·M·3851 0 Screening Levels for RCA Integrated Circuits
MIL·M·38510
Application
Class A
(See Note 1)
Aerospace & Missiles
Class 8
Military & Industrial
Description
For devices intended for use where maintenance and replacement are
extremely difficult or impossible and Reliability is imperative
For example, in Airborne
For devices intended for use where maintenance and replacement can
be performed but are difficult and expensive
Electronics
Class C
For devices intended for use where replacement can readily be
Military & Industrial
accomplished
For example, in Ground·
Based Electronics
.. A Visual InspecNote 1: In the Condition
i alignment:
covered by the metallization.
tion of COS/MOS devices. the specification : 1.
for metallization alignment in section
3.1.1.7(a) of the general specification will
'2.
, be changed. to read as folloV\lS:
720
Contact window that has less than
50 per cent of its area covered by the
metallization.
Contact which has less than 75 per cent
of the length of two adjacent sides
3. A metallization path not intended to
cover a contact window which is
separated from the window by less than
0.25 mil.
4. Any exposure of the gate oxide.
9·74
RIC-104A
WAFER
FORM
METHOD
2010.1
COND.A
CONDITIONING SCREENS
STABILIZATION BAKE
THERMAL SHOCK
TEMPERATURE CYCLING
MECHANICAL SHOCK
CENTRIFUGE
FINE LEAK
GROSS LEAK
CONDITIONING SCREENS
STABILIZATION BAKE
~~;~~ 1-----1 ~~~~~~/U~~RE CYCLING
FINE LEAK
GROSS LEAK
M~ci,~~~
CONDo B
92CL-24950
Fig. 1 - Product flow diagram for RCA high-reliability COS/MOS integrated circuits processed in accordance with MIL-M-38510.
Table 2 - MIL-M-38510 Processing and Screening Requirements for RCA High-Reliability COS/MOS Integrated Circuits
MIL-M-38510
Processing
• Wafer
SEM Inspection
• Assembly
Precap Visual
Precap Visual
• Preconditioning
Stabilization Bake
Thermal Shock
Temperature Cycle
Mechanical Shock
Centrifuge Yl
Centrifuge Yl & Y2
Fine Leak
Gross Leak
MI L-STD-883
METHOD
GSFC-S-311-P-12
2010_1
2010_1
1008
1011
1010
2002
2001
2001
1014
1014
Condition
MI L-M-3851 0
CLASS
A
B
C
Photographs Available
X
-
-
A
B
X
-
X
X
X
C, 48 hours at 150°C
C, 15 cycles, -65°C to +150°C
C, 10 cycles, -65°C to +150 o C
B, 5 pulses
E, 30000 G's
E, 30000 G's
A
C
X
X
X
X
X
X
X
-
-
-
X
X
X
X
X
-
-
X
X
X
X
X
-
-
-
-
-
-
-
• Test and Burn-In
Initial Test
-
MIL-M-38510/50 Series
1015
A, Bias at 150°C
X
X
X
1015
A, Bias at 150°C
X
1015
0, Dynamic at +125°C
MIL-M-38510/50 Series
MI L-M-3B51 0/50 Series
MIL-M-38510/50 Series
MIL-M-38510/50 Series
MIL-M-38510/50 Series
MI L-M-3B51 0/50 Series
-
X
-
X
X
X
S
X
S
X
X
X
S
X
S
X
S
S
S
S
S
Two views
X
-
-
Serialize
Bias Burn-In,
Two 36-Hr. Deltas
Operating Burn-In,
240-Hr_ Deltas
Operating Burn-In 16B Hrs.
Final Electrical DC +250 C
Final Electrical AC +250 C
Final Electrical DC -55°C
Final Electrical AC - 55°C
Final Electrical DC +125°C
Final Electrical AC +125°C
• X-ray Inspection
NH853004(3E)
-
721
RIC-104A _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
LEAK TRIM
AND CARRIER
SCRIBE AND
BREAK
WAFER
LOAD
PROCESSING
THROUGH
METALLIZATION
SEM INSPECTION
PER NASA
SPECIFICATION
TEMPERATURE
PELLET
SORT
CYCLE
PELLET
CLEAN
LEAK TEST
GSFC-S-31'-P-12
WAFER FINISHING
OPERATIONS
HELIUM
STATIC
BURN-IN
CONDITION A
PELLET
WAFER TESTING AND
SHIPMENT INTO
HIGH-REL MFG.
OPERATION
INSPECTION
100"/0
STABILIZATION
BAKE (48 HR.
AT 150"C)
MOUNT
100"10 THERMAL
SHOCK
ASSEMBLY
100%
TEMPERATURE
CLEAN
INTERIM
ELECTRICAL
PARAMETERS
CYCLING
INTERIM
ELECTRICAL
PARAMETERS
STATIC
BURN-IN
CONDITION B
INTERIM
ELECTRICAL
PARAMETERS
100%
BOND
MECHANICAL
SHOCK-YI
DIRECTION
100"!..
ASSEMBLY
CLEAN
CENTRIFUGE
3O,OOOG
YI AND Y2
DIRECTIONS
0
~
100%
FINE LEAK
BRAND
POST-BOND
100"10
GROSS LEAK
FINAL
ELECTRICAL
TESTS
RADIOGRAPHIC
EXAMINATION
PRODUCTION PROCESS
IN-PROCESS QUALITY
ASSURANCE INSPECTION
EXTERNAL
VISUAL
SHELL TACK
WELD
D
0
PDSTDYNAMIC
ELECTRICAL
PARAMETERS
CODE
BRAND
INSPECTION
LEGEND:
DYNAMIC
BURN-IN
IN -PROCESS QUALITY
ASSURANCE-GATE
PAE-SEAL
BAKE
SOLDER DIP
CRITICAL INSPECTION
POINT
CONTROL CHART
SEAL
DATA (OPERATOR INSPECTION,
RECORDS, CHARTS, ETC)
92CL-24952
Fig. 3 - Flow Chart for COS/MOS High-Reliabilitv Flat-Pack MIL·M·38510 Class A Device.
722
- - - - - - - - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ RIC-104A
Table 3 - COS/MOS Devices For Which MIL-M-38510/50
Specifications Have Been Written
Detailed Electrical
Specification,
MIL-M-38510
M I L·M·3851O/050
01
02
03
MI L·M·3851O/051
01
02
MI L·M·38510/052
01
02
03
04
MI L·M·3851 0/053
01
02
MIL·M·38510/054
01
Detailed Electrical
Specification,
MIL-M-38510
Device
Covered
CD4011A
CD4012A
CD4023A
CD4013A
CD4027A
CD4000A
CD4001A
CD4002A
CD4025A
CD4007A
CD4019A
CD4008A
Device
Covered
MIL·M·38510/055
01
02
03
04
MIL·M·38510/056
01
02
03
04
05
MIL·M·38510/057
01
02
03
04
05
MIL·M·38510/058
01
CD4009A
CD4010A
CD4049A
CD4050A
CD4017A
CD4018A
CD4020A
CD4022A
CD4024A
CD4006A
CD4014A
CD4015A
CD4021A
CD4031A
CD4016A
Table 4 - Comparison of Screening Requirements for RCA Lev.II1N COS/MOS Devices
and MIL-M·38510 Class A COS/MOS Devices
RCA LEVEL /IN
SCREENING PROCEDURES
CLASS A MIL·M·38510
(PER MIL·STD-883)
1. SEM Inspection
Yes
Yes
2. Visual, Precap
2010.1 Condo A
2010.1 Condo A
3. Pre-conditioning
MIL·STD·883
4. Bias Burn·in High
None
MIL·STD·883
36hrs@150°C,tP)PDA(I)
5. Bias Burn-in Low
None
36 hrs@ 150°C, t,(2) 5%
6. Operating Burn·in 240 hrs @
125°C
Cirteria 10% Lot Reject Max; If
Exceeded, Repeat Allowed
PDA 5% Max; if over 5% Reject
7. DC Elect. Tests
Measurements on Selected Inputs
and Outputs
Entire Lot Ii (2)
Measurements on all Inputs and
Outputs
8. DC Test·Limit Resolution
50 nA Minimum; 10 mV Minimum
1 nA Minimum; 1 mV Minimum
9. AC Dynamic Tests
Measurements on Selected Inputs
and Outputs
Measurements on all Inputs and
Outputs
10. AC Test Limits
At 15·pF Load
AT 50·pF Load
11. Radiographic
View in One Dimension
View in Two Dimensions
9 Detailed Electrical Specifications
12. Parts Qualification
Requirement
13. Group Band C Qualification
Conformance
(1I pDA '" Per-Cent Defective Allowable
10 Generic Families for 50
COS/MOS Types
9 Generic Families for ,?-7 COS/MOS
Types
(21.6== Delta Variables. Data Required
723
RIC·104A _ _ _
~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Table 5 - Final Electrical Tests
TEMPERATURE
(TAl
TEST CRITERIA
TESTS TO
MIL·M·38510 SPECIFICATIONS
Class A
Class B
Class C
+25°C
DC & Functional Parameters
100%
100%
100%
+125°C
DC & Functional Parameters
100%
100%
-
-55°C
DC & Functional Parameters
100%
100%
-
+25°C
AC Parameters
100%
100%
-
Table 6 - Group A Electrical Sampling Inspection
SUBGROUP OF
TESTS TO
MI L·STD-883
MIL·M·38510 SPECIFICATIONS
5005.1
LTPD
CONDITION
Class A
Class B
ClassC
1,7
DC & Functional Parameters
TA = +25°C
5
5
5
2,8
DC & Functional Parameters
TA = +125°C
5
7
10
10
3,8
DC & Functional Parameters
TA=-55°C
5
7
4,9
AC Parameters
TA = +25°C
5
5
5
10
AC Parameters
TA=+12SoC
5
5
11
AC Parameters
TA = -55°C
7
7
-
Details of static. functional, and dynamic tests. conditions, and limits appear in the specific MIL-M·38510/050 series specifications.
Table 7 - Group B Environmental Sampling Inspection to MIL·M·38510 (Note 1)
MI L·STD·883
SUBGROUP
TEST
REFERENCE
CONDITIONS
CLASS
B
CLASS
C
15
20
1
Physical Dimensions
2008
Test Condo A per
applicable data sheet
2
Marking Permanency
2008
Test Condo B per
Par. 3.2.1
4devices._
(no failures)
Visual and Mechanical
2008
Test Condo B
10 X mag.
1device._
(no failure)
Bond Strength
2011
Test Condo D
10 Devices minimum
3
Solderability
2003
4
Lead Fatigue
2004
Test Condo B2
any 5 leads
Fine Leak
1014
Test Condo A
Gross Leak
1014
Test Condo C
Note 1: Group B tests are performed on each inspection lot per requirements of MI L~M·38510.
Nota 2: Operating life circuits are included in MIL-M-38510 detailed specifications (f sheets),
724
LTPD
CLASS
A
10
5
15
10
15
15
10
15
15
20
- - - - - - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ RIC-104A
Table 8 - Group C Environmental Sampling Inspection to MIL-M·38510 (Note 1)
MI L·STD·883
SUBGROUP
REFERENCE
1
LTPD
TEST
Thermal Shock
Temperature Cycling
Moisture Resistance
Fine Leak
Gross Leak
CONDITIONS
CLASS
A
CLASS
B
CLASS
C
1011
1010
1004
1014
1014
Test Condo C
Test Condo C
No Voltage Applied
Test Condo A
Test Condo C
10
15
15
Test
Test
Test
Test
Test
10
15
15
10
15
15
7
7
7
5
5
5
Critical Post Tests - Note 3
2
Mechanical Shock
Vibration, Var. Freq.
Constant Acceleration
Fine Leak
Gross Leak
Critical Post Test - Note 3
2002
2007
2001
1014
1014
3
Salt Atmosphere
1009
Condo
Condo
Condo
Condo
Condo
B, 0.5 ms
A
E
A
C
Test Condo A
Omit Initial Conditioning
4
High Temp .. Storage
Critical Post Tests - Note 3
1008
Test Condo C
1000 hours
5
Operating Life .
Critical Post Tests - Notes 2
and 3
Steady State Bias
1005
TA = 125°C, 1000 hrs.
Test Circuit (Note 21
1015
Test Condo A, 72 hrs.
At TA = 150°C (Note 3)
6
Critical Post Tests - Note 3
7
-
-
Nota 1: Group C tests are performed at 3-month mtervals.
Nota 2: Operating life circuits are included in MI L·M·3851Q detailed specifications (f sheets).
Nota 3: Static parameters and limits are shown in MIL-M-38510 detailed specifications (/ sheets).
Table 9 - MIL·M·38510 Product-Assurance Program RequirementS
In·House Documentation Covering These
In·House Records Covering These Areas A Program Plan Covering These Areas
Areas
a. Conversion of customer requirements into a. Personnel training and testing
a. Functional block organization chart
manufacturer's internal instructions
b. Inspection operations
b. Manufacturing flow chart
b. Personnel training and testing
c. Failure reports and analyses
c. Proprietary·document listing
c. Inspection of incoming materials,
d. Changes in design, materials, or
d. Examples of design, material, equip·
utilities and work in process
processing
me-nt, and processing instructions
d. Quality·control operations
e. Equipment calibrations
e. Examples of records
e. Quality-assurance operations
f. Process utility and material controls f. Examples of design, material and
f. Design, processing, tool and materials
process change control documents
g. Product lot identification
standards and instructions
g. Examples of failure and defect
analysis and feedback documents
g. Cleanliness and atmospheres in work areas
h. Design, material, and process change control
i. Tool and "test equipment maintenance" and
h. Examples of corrective action and
evaluation documents
calibration
j. Failure and defect analysis and data feedback
k. Corrective action and evaluation
I. Incoming, in process, and outgoing "inventory
control
= 14·Terminal Dual·ln·Line
= 14·Terminal Flat Pack (114" x 3/S")
= l6·Terminal Dual·in·Line
= l6·Terminal Fiat Pack (1/4" x 3/S")
. Note 1: A "J" or "JAN" prefix indicates qualified parts.
J = 24-Terminal Flat Pack
K = 24·Terminal Dual·in·Line
Fig. 4 - Guide to the reliability. class. package. and lead finish of RCA high-reliability COS/MOS integrated circuits processed in accordance with
MIL·M·38510.
725
Appendix __________________________
~
_______________________________________
DRIVE CURRENT TEST CIRCUIT CONNECTIONS To be used as an example of test method.
Example:
Example:
C04000A lOP
16-i.ead Types
Type
Mt Ground
VDD
VDD
~
~
"
"
"
•
CD4024A'
(K,O)
M
I.
ID
CD4024A'
,tes-ITIU"!
Type
Mt
Grou'"
VDO
YO
CD4000A
ION
1-4,7.8,11,13
5,14
6
loP
1·5,7.8,11·13
14
CD4001A
ION 2,5-9,12,13
lOP
CD4002A
CD4006A*
C04007A
2,14
lOP
2·5.7.9-12
14
ION
1,4-7
14
lOP
4·7
1,14
ION 3,7,10
CD40D9A
CD4010A
CD4011A
C04012A
C04015A*
CD4017A
1
13
8
ION 1-9.15
16
14
lOP
1-7.9.15.16
8
ION 5,7-9,11,14
1,3,16
lOP
3,5,7-9"',14
1,16
ION 3,5,7-9,11,14
1,16
lOP
1,3,16
5,7-9,11.14
ION 5-9,12,13
1,2,14
lOP
2,14
1.5-9,12.13
ION 7,9·12
2.7.9-12
ION 3,6-11
3-5,7-11
2-5.14
4,14
CD4031A
CD4032A
3
CD4033A
1
1
1.4-8,11,13-15 9,16
4-8.11.13-15
ION
1.6-8.14.15
16
lOP
1.6.8,14,15
7,16
3
CD4035A
1,9,16
5
ION 8
13-16
3
lOP
13-16
2
CD4036A
CD4037A
11
'-3.7-10.12
14--16
9,12,14-16
CD4D19A
ION
1-9
14-16
lOP
HI
9.14-16
CD402OA*
ION 8.11
16
9
CD4D21A
lOP B,II
ION 1.4-8.10.11,.
16
9,16
3
CD403BA
13
CD4039A
C04040A-
13-15
lOP
16
8,13,15
16
ION 1,2,7.8,11·13
3-6.14
1-3,7.8."·13
4.5,14
lOP
12
lOP
2,7
14
ION
1,12
2,3
lOP
3.12
2
ION
1-4,7.8,1\.13
5,14
lOP
1·5,7.8,11·13
14
11
6
ION
1.:1.8,16
16
loP
1,2.8
3,16,16
ION
3,5-13
4,16
lOP
3-6,8-13
7,16
ION
8,1()'13
16
2
lOP
8,10·13
3.4,8,10,12,
13,15
5,8,15
16
1,5,9,16
3
6
3
ION
ION
1,2,5-9,12,13
1.3,4,9,10,12,
13,16
14
lOP
2,5-9,12,13
1,14
ION
1,2,8,10,15
7,16
lOP
1,2,7.8,10,15
16
ION
2,3,5-8,1()'15
16
lOP
2.3,5.6.B,1().16
7,16
ION
1.:1,8,14
16,16
lOP
1.:1,8,16
14,16
ION
1.fl,1()'12,16
9,13,14,24
lOP
1()'12,15
1.g,13,14,24
ION
2-4,6-12
2,5,16
lOP
2-4,&·12
5,16
ION
3·12,21·23
1,2,24
lOP
11,12,21·23
1·10,24
ION
7
1-5,14
lOP
2·7
14·
ION
2,3,6.fl,1()'16
10,11,16
lOP
2.3,5.6,8,12·15
7,10,11,16
ION
3·12,21·23
1,2,24
lOP
11,12,21·23
1-10,24
ION
B,10
11,16
..ION
B,11
16
4-8.10.11,13-15 1.9,16
ION 8,13,15
lOP
2
6
Refer to applicable data sheet for Va values.
Voltage outputs shall be supplied by an external power supply,
726
CD4034A
6,14
lOP
2,14
lOP
2
1-3,7,8,10
CD4D23A
CD4029A
CD4030A
ION
CD4022A*
CD4028A
2
lOP
CD4018A
CD4027A
3·5,14
ION
8
CD4025A
CD4026A
13
lOP
C04014A·
6.14
YO
1,7
10
3
14
lOP
CD4013A
3,6,7,10
(T)
14
ION 3-5,7,9-12
lOP
CD4008A
1,2,5-9,12,13
1,14
YOD
ION
-0
16
C04041 A
(TRUE)
C04041A
(COMP)
ION
3.6,7,10,13
14
lOP
6,7,10,13
3,14
ION
6,7,10,13
3,14
lOP
3,6,7,10,13
14
• M "" Measurement
• These types must be clocked Into the proper state.
1
6
9
10
16
1
13
10
9
13
9
1
2
__________________________________________________________________
App~dix
DaIVE-CURRENT TEST-CIRCUIT CONNECTIONS (Cont'dl
Typo
Mt
CD4042A
IoN 4.7,8.13.14
5.6.16
CD4043A
InP
ION
4-6.16
3.5.16
ION
7.8.13.14
4.&-8.11.12
14.15
3.&8.11.12
14.15
4.8
lOP
3,8
lOP
CD4044A
Ground
VOO
ION
2.14
2.14
1.3
CD4046A
ION
5,8.9
3.14.16
COMPI
lOP
5,8.9.14
3.16
ION
5.8.9.14
3.16
COMP2
lOP
5,8.9
3.14.16
CD4047A
ION
5.7.12
4.6,8.9.14
lOP
7,8
3-6.8.12.14
ION
3-14
2.15.16
loP
2-14
15.16
ION
5.7-9.11.14
1.3
lOP
5.7-9.11.14
1
ION
3.5.7-9.11.14
1
lOP
5.7-9.11.14
1.3
ION
2.7-15
1.16
lOP
2.7-14
1.15.16
ION
2-4.5-8
5.16
lOP
2-8
16
ION
2-4.5-8
1.5.16
CD4049A
CD4050A
CD4054A
CD4055A
CD4056A
CD4057A
ZEROINO
NEGINO
OVERFLOWINO
OTHER OUTPUTS
OATAOUTI &3
CD4060A*
CD4061A*
M.
Ground
VOD
C04062AK*
ION
2-5,8
11.13.16
CLO
lOP
3-5,8
2.11.13.16
ION
2-5.8
11.13.16
Q
lOP
3-5.8
2.11.13.16
2
13
8
ION
2-5.7
9.11.12
CLO
lOP
3-5.7
2,9.11.12
ION
2-5.7
9.11.12
Q
lOP
3-5.7
2.9.11.12
ION
1.3.4.8-15
3.16
lOP
1-3,8-15
4.16
C04066A
13
CD4068B
10
8.12
16
ION
1-4.6.7.9-12.
15.16
1-4.6.7.9-11.
15.16
5
C04069B
CD4071B
1
CD4072B
CD4073B
2
C04075B
3
CD4078B
9
C040S1B
9
C04082A
C04085B
C040S6S
CD4514S
C04515B
CD4520S
• M
7
12
6
10
5
NO ION. lOP
ION
7
2-5.9-12.14
lOP
2-5.7.9-12
14
ION
7
1.3.5.9.11.13.14
lOP
1.3.5.7.9.11.13
14
ION
1.2.5-9.12.13
14
lOP
7
1.2.5-9.12.13.14
ION 2-5.7,9-12
14
7
2-5;9-12.14
ION
1-5.7.8.11-13
14
lOP
7
1-5,8.11-14
ION
1-5.7,8.11-13
14
lOP
7
1-5.8.11-14
ION
7
2-5.9-12.14
lOP
2-5.7.9-12
14
ION
lOP
1.2.5-9.12.13
7
ION
2-5.7.9-12
14
1.2.5.6,8.9.
12-14
14
lOP
7
2-5.9-12.14
ION
1.2.5-9.11-13
10-14
lOP
1.2.5-13
14
ION
1.2.5-9.11.13
11.14
InP
12.5-10.1213
11.14
ION
2.3.12.21.22
1.2.3.24
lOP
2.3.12.21-23
1.24
ION
2.3.12.21-23
IOP* 2.3.12.21.22
CD451SS"
Vo
ION
~
lOP
2
1.16
2-8
24
1-3.6.7.14.21
8.9.13.15.19.
23.25.27,28
22.26
1-3.7-9.13.15.
lOP 6.14.21.23
25.28
19.20.22.26.27
4
ION 1-3.6.14.21.23. 7-9.13.15.19
25.27.28
20.22.26
lOP 1-3.6.7.14.21.
8.9.13.15.19.
23.25.27.28
20.22.26
17
ION 1-3.5.7.9.14.19 6.13.15.20.
22.23.25.27.28 21.26
lOP 5.7-9.14.19.22. 1-3.6.13.15.20.
23.25.28
21.26.27
8.9.13.15.19.20. 1
ION 6.7.21.25
22.23.26
8.9.13.15.19.20. 27
lOP 6.7.21.22.25
23.26
12.16
7
ION 8.11
lOP
C04063B
2
lOP
ION
lOP
Type
CD4062AT*
lOP
CD4048A
2
4,5.16
3.5-7.11.12.
14-16
4-7.11.12.
14-16
1.3
CD4045A
(iflto 16)
Vo
1.24
13
2
10
1
6
6
13
3
1
3
3
11
11
1.23.24
ION
1.2.7-10
15.16
lOP
1.2.7.8.10.15
16
ION
1.2.7-10
15.16
lOP
1.2.7 .S.1 0.15
16
14
14
= Measurement
... These types must be clocked into the proper state.
13
5.12
727
Appendix ______________________________________________________________________
THRESHOLD-VOLTAGE TEST-CIRCUIT CONNECTIONS
N-Channel Tests
--,---;;;--
2
-
13 f2'-
-
3
4
11-
5
10 -
-
6
9-
-
. -~-
P-Channel Tests
10V
-r;--;;;-r-
--0
~-20~A
SUPPLY
2
-
3
4
12
5
10
-
--
DVM
13
-
.
!-
r- ~20~A
SUPPLY
1If--
r-
DVM
9f--
-~r-.
~-'O~A
SUPPLY
-IOV
-----<>
~'O~A
SUPPLY
DVM
DVM
10V
-,..,---,;;-
--0
-
2
-
3
4
~-20~A
SUPPLY
-
5
-
6
7
15
14
13
12
-
- -,------;s -
DVM
10 -
Ground
3
10V
14
CD4001A
CD4002A
CD4006A
CD4007A
CD4008A
CD4009A
CD4010A
CD4011A
CD4012A
CD4013A
CD4014A
CD4015A
CD4016A
CD4017A
CD4018A
CD4019A
CD4020A
CD4021A
CD4022A
CD4023A
CD4024A
(K,D)
CD4024A
(T)
1
2
3
6
9
3
3
2
2
3
10
1
13
15
15
9
10,11
10
14
3
1,2
14
14
14
14,8
2,4,6,15,16
1,16
1,16
1,14
3-5,14
14
16
16
5,6,12,14
16
16
14-16
16
16
13,15,16
4,5,14
14
1,3
2
CD4025A
3
14
CD4026A
CD4027A
CD4028A
CD4029A
1
13
10
10
CD4030A
CD4031A
CD4032A
CD4033A
8
2
3
1
2,3,15,16
3-7,9-12,16
16
1,3-5,9,12,13,
15,16
14
1,10,15,16*
2,5-7,10-16
2,3,14-16
728
-
.
-
~-'O~A
SUPPLY
-
3
4
15 14 13 -
5
12-
7
~v
~20~A
SUPPLY
DVM
1110-
-~-
DVM
~'O~A
SUPPLY
DVM
92CS-22944
Type
CD4000A
2
-
11-
-~-
-
92CS-22945
VTHN measured at
20llASupply
10 IlA Supply
-10V
lh~5,7,8,
3
lh~5,7,8,
2,5·9,12,13
3-5,7,9-12
1
2
3
6
9
3
3
2
2
3
10
1
13
15
·15
9
10
10
14
3
1
2,5-9,12,13
3-5,7,9-12
1,4-7
7,13
1,3,5,7,8
5,7-9,11,14
5,7-9,11,14
5-9,12,13
7,9-12
4-11
1,4-9,11,13-15
6-9,14,15
5-7,12
8
1-3,7-10,12,14
1-8
8,11
1,4-9,11,13-15
8,13,15
1,2,7,8,11-13
2,7
1,4-7
7
1,3,5,7,8
5,7-9,11,14
5,7-9,11,14
5-9,12,13
7,9-12
4-11
1,4-9,11,13-15
6-9,14,15
7
8,13,14
1-3,7-10,12,14
1-8
8
1,4-9,11,13-15
8
1,2,7,8,11-13
7
12
1,2,4,5,7,8,
11-13
8
8
8,n.13
8
1,2,5-7,12,13
8
8
8
Ground
1
3,12
3
1,2,4,5,7,8,
11-13
2,3,8,15
3-12
8,11-13
1,3-5,8,9,12,
13,15
1,2,5-7,9,12,13
1,8,10,15*
2,5-8,10-15
2,3,8,14,15
1
13
10
10
8
2
3
1
VTHP measured at
20llASupply 10 IlASuPPi'L
14
14
14
14
14
2,4,6,15,16
1,16
1,16
1,14
3-5,14
14
16
16
14
13,14,16
16
14-16
16
16
16
4,5,14
14
2
14
16
16
16
16
14
16
16
16
______________________________________________________________________ Appendix
THRESHOLD-VOLTAGE TEST-CIRCUIT CONNECTIONS (CONT'D)
P-Channel Tests
N-Channel Tests
Type
Ground
10V
VTHN measured at
-20 pA Supply -10 pA Supply
CD4034A
CD4035A
10
6
9,11,13·24
16
2·5,7·12
12
12
CD4036A
23
1·11,21,22,14
CD403BA
3
2,5,6,10·16
CD4039A
23
1·11,21,22,24
12
CD4040A
10,11
3
16
14
8
CD4041A
CD4042A
CD4043A
6
5
CD4044A
CD4045A
8
Ground
-10V
VTHP measured at
20pA Supply 10pA Supply
10
1·9,11·15
6
23
2·5,7·12
1·12,21,22
3
2,5·8,10·15
23
1·12,21,22
24
10
B,I1
6,7,10,13
16
24
16
24
16
6,7,10,13
3
16
16
4,5,7,8,13,14
3,4,6·8,11,12,
14,15
6
5
4,5,7,8,13,14
3.4,6·8,11,12,
14,15
16
16
5
16
3.4,6·8,11,12,
14,15
5
3.4,6·8,11,12,
14,15
16
16
3,5·8,14
1,3·
2,14,15
16
2,14,15·
1,3
9,11,12,16
10
16
7
3,5·9,11,14
4,8,12
12
14
5,7·9,11,14
3
CD4046A
CD4047A
CD404BA
4,8,12
10
3,5,6,14
CD4049A
3
1
CD4050A
3
1
16
2·9,11·15
5,7·9,11,14
3
A special detailed test set-up is reuired
CD4057A
CD4060A
12
16
CD4061A
1
2,3,5,6,7,9,10
11,15,16
CD4062AK
CD4062AT
CD4063B
5
5
10,13,16
8,11,12
1
CD4066A
13
16
5,6,12,14
CD406BB
2
10
9·11
4
3,5·7,9
2·9,11·15
16
1
5,7·9,11,14
5,7·9,11,14
1
12
9,10,11
1
2·4,6,7,9·12,
15,16
5
13,16
11,12
2·4,8
10
2·5,B
2·4,7
8
2·5,7
1
16
7
13
2·4,8·15
5·7,12
3·5,14
7,9·12
2
7,9·12
1
14
3,5,7,9,11,13
1
14
2,5·9,12,13
1
3,5,7,9,11,13
2,5·9,12,13
CD4072B
1
2
CD4073B
CD4075B
3
3
14
4,5,14
3·5,7,9·12
1,2,7,B,11·13
2
3
3·5,7,9·12
1,2,7,8,11-13
14
4,5,14
14
1,2.4,5,7,B,
11,12,13
3
1,2.4,5,7,8,
11·13
14
3·5,7,9·12
5·9,12,13
7,9-12
2
2
3·5,7,9·12
5·9,12,13
14
1,14
2
1
1
7,9·12
3·5,14
5·13
5·13
2,14
2,14
2,3,12,21'23
2,3,12,21·23
24
24
CD4069B
CD4071B
CD407BB
2
14
CD4081B
2
1,14
2·4,8-15
14
CD4082B
2
CD4085B
CD4086B
1
1
3·5,14
2,14
2,14
CD4514B
1
24
5·13
5·13
2,3,12,21·23
CD4515B
1
24
2,3,12,21·23
CD4518B
15
16
CD4520B
15
16
•
1,2,7'10
1,2,7·10
1
1
15
15
16
14
3·5,14
14
14
1,2,7·10
16
1,2,7·10
16
Use 5V for n-channel test, -5V for p-channel test.
Use 4V for n-channel test, -4 V for p-channel test.
729
Appendix _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
LlFE·TEST CIRCUIT CONNECTIONS
Biased Life Tests
-r"TIi~
2
,,-
Operating Life Tests
- , ,,--- ,,, ,,,,"
,,- -0
-
r,---""i6 ~v
-,
- ,
- ,
'- ,
-
25kHz
osc.
TRIGGER
-,
!lOkH,
osc
Z
,,,,,,\'-
,
"
--0
"-
CONNECTIONS TO ALL TERMINALS
IEXCEPT eal61 ARE MADE
THROUGH 47.n RESISTORS
~~_92CS.22940
CONNECTIONS TO ALL TERMINALS IEXCEPT 88161 ARE
MADE THROUGH 47 Ul RESISTORS
ose.
TRIGGER
50kHz
osc
.
,
,
2
-
-
"l-
"I'0 r-
"r"I'0 r, 'rf--
: ,
-,
'v
;.
.
-0
92C5-22941
CONNECTIONS TO ALL TERMINALS IEXCEPT 7
MADE THROUGH 47 kR RESISTORS
---- ------
.,
-
-
15°
24
0
0.020 0.080
0.020 0.060
2
3
3
3
4
5
6
2.29
3.81
0.51
1.65
0.381
0.508
1.143
1.397
0.204
0.304
29.21
30.98
15.24
15.87
12.20
13.20
. 2.54 TP
15.24 TP
2.54
4.57
0.00
0.76
0°
15°
24
0
0.51
2.03
0.51
1.52
MILLIMETERS
INCHES
SYMBOL
MAX.
MIN.
MAX.
.100
.000
.200
.070
2,6
0
5.0
1.77
.015
.015
.020
.055
.508
1.39
.008
1.380
.012
1.420
.381
,39
,204
35.06
.600
.485
.100
.600
.625
.515
MIN.
A
A1
B
B1
C
D
E
E1
·1
·A
L
L2 .
0
"
N
N1
TP
TP
.200
.030
15
.100
,000
.020
Q1
.040
S
See Note 1
2.6
0
5.0
.76
150
0°
28
0
.070
.070
2
.304
36.06
15.87
15.24
13.08
12.32
2.54 TP
15.24 TP
28
0
NOTES
,51
1.02
3
3
4
5
6
1.77
1.77
92CS-1994B
92CM-20250
-II.
\~mT.
l
--rF~s a
BASE PLANE
SEATING PLANE
A
~
L
G~A;UG;E;:P~L=A~NE~==J
_
B~" ~ Bj
NOTES,
1. REFER TO RULES FOR DIMENSIONING
(JEDEC PUBLICATION No. 13) AXIAL LEAD
PRODUCT OUTLINES.
2. WHEN BASE OF BODY IS TO BE ATTACHED
TO HEAT SINK, TERMINAL LEAD STANDOFFS ARE NOT REQUIRED AND A1" O.
WHEN Al = 0, THE LEADS EMERGE FROM
THE BODY WITH THE B1 DIMENSION AND
REDUCE TO THE B DIMENSION ABOVE THE
SEATING PLANE.
3.
L
A,
L
L,
c,
AND eA APPL Y IN ZONE lZ WHEN UNIT
INSTALLED. LEADS WITHIN ,005" RADIUS
OF TRUE POSITION (TP) AT GAUGE PLANE
WITH MAXIMUM MATERIAL CONDITION.
4. APPLIES TO SPREAD LEADS PRIOR TO
INSTALLATION.
5. N IS THE MAXIMUM QUANTITY OF LEAD
POSITIONS.
6. N, IS THE QUANTITY OF ALLOWABLE
MISSING LEADS,
The lead finish for the packaged types is in accordance with MIL-M-38510, Paragraph 3.6.2,5, Lead Finish "A",
When these devices are supplied solder-dipped, the maximum lead thickness (narrow portion) will not exceed 0.013",
737
Appendix--------------------______________________________________________
TO-5 Style Packages
II-LEAD TO-5 WITH DUAL-IN-LiNE FORMED LEADS
8-LEAD TO-5 STYLE PACKAGE
MIL-M-38510 CASE OUTLINE A-1
~r=:~I~ j
·-,=F---r,
REFERE. NeE
PLANE ""\
8ASE a
\.
SEATING--.
PLANE
GAGE PLANE
_016
.021
(8 LEADS)
F
L,
Q
A
L2
1l100~.
'\: ~ b
., ~
~bl
,
92CS~20296RI
SYMBOL
INCHES
MIN.
MAX.
NOTE
MILLIMETERS
MIN.
MAX.
4.19,
4.70
A
0.165
lib
0.016
0.019
1
0.41
DAB
1
0.016
0.021
1
0.41
0.53
0.185
~D
0.335
0.370
8.51
9.40
~Dl
0.305
0.335
7.75
8.51
~D2
0.120
0.160
3.05
4.05
•
·1
F
0.200BSC
O.I00BSC
5.08BSC
2.548SC
1.02
0.D4D
k
0.027
0.034
kl
L
0.027
0.045
0.500
0.750
Ll
0.000
0.050
L2
0
0.010
a
3
3
0.69
0.86
2
0.69
1.14
1
12.70
1
0.00
6.35
19.05
1.27
1
0.250
0.045
460 8SC
0.25
3
1.14
460 BSC
NOTES:
1. (All lead.) ~b applies batween Ll and L2' ~bl applies ba_n L2 and
0.500 in. (12.70 mm) from the reference plane. Diameter is uncontrolled
in L, and beyond 0.500 in. (12.70 mm) from the reference plane.
2. Measured from the maximum diameter of the product.
3. Leads having 8 maximum diameter 0.019 in. (0.48 mm) measured in
gaging plane 0.054 in . .fl.37 mm) +0.001 in. (0.03 mm) -0.000 in.
(0.00 mm) below the base plane of the product shall be within 0.007 in.
(0.18 mm) of their true position relative to a maximum width tab.
4. The product may be measured by direct methods or by gage.
92CS-24774
The lead finish for the packaged types is in accordance with MIL-M-38510, Paragraph 3.6.2.5, Lead Finish "A".
738
______________________________________________________________________ Appendix
TO-5 Style Packages (Cont'd)
lO-LEAD TO-5 STYLE PACKAGE JEDEC MO-OOS-AF
SYMBOL
a
A
A2
oB
.Bl
oB2
.0
.01
Fl
j
k
Ll
L2
L3
.
N
Nl
INCHES
MIN.
MAX.
0.230TP
10
a
0.165
0.185
0.016
0.019
a
NOTE
2
MAX.
MIN.
5.84 TP
a
a
3
4.19
0.407
4.70
0.482
a
a
a
0.016
0.021
0.370
0.335
0.305
0.335
0.020
0.040
0.034
0.028
0.029
0.045
0.000
0.050
0.500
0.250
0.500
0.562
360TP
10
1
3
4
3
3
3
6
5
l2-LEAD TO-5 PACKAGE JEDEC MO-OOS-AG
MILLIMETERS
0.407
0.533
9.39
8.51
7.75
8.50
0.51
1.01
0.712
0.863
0.74
1.14
1.27
0.00
6.4
12.7
14.27
12.7
360TP
10
1
SYMBOL
INCHES
MIN.
MAX.
NOTE
0.230
2
a
MILLIMETERS
MIN.
MAX.
5.84 TP
AI
0
a
a
a
A2
¢B
0.165
0.016
0.185
0.019
3
4.19
0.407
4.70
0.482
¢Bl
¢B2
a
a
a
a
0.016
0.021
3
0.407
0.533
¢D
¢Dl
0.335
0.305
0.370
0.335
8.51
7.75
9.39
8.50
Fl
j
k
Ll
0.020
0.028
0.029
0.000
0.040
0.034
0.045
0.050
4
3
0.51
0.712
0.74
0.00
1.01
0.863
1.14
1.27
L2
L3
0.250
0.500
0.500
0.562
3
3
6.4
12.7
12.7
14.27
.
N
Nl
30'TP
12
1
6
5
30'TP
12
1
92CS-19774
NOTES:
1. Refer to Rules for Dimensioning Axial Lead Product Out-
lines.
2. Leads at gauge plane within 0.007" (0.178 mm) radius of
True Position (TP) at maximum material condition.
3. liB applies between L1 and L2. IlB2 applies between L2
and 0.500" (12.70 mm) from seating. plane. Diameter is
uncontrolled in L1 and beyond 0.500" (12.70 mm).
4. Measure from Max.q,D.
5. N 1 is the quantity of allowable missing leads.
6. N is the maximum quantity of lead positions.
The lead finish for the packaged types is in accordance with MI L-M-385l0, Paragraph 3.S.2.5, Lead Finish "A".
739
Solid State Device!!
OOaBLJD
Solid State
Division
Operating Considerations
.1CE-40~
Operating Considerations for
RCA- Solid State Devices
Solid state devices are being designed into an increasing
variety of electronic equipment because of their high
standards of reliability and performance. However, it is
essential that equipment designers be mindful of good
engineering practices in the use of these devices to achieve
the desired performance.
This Note summarizes important operating recommendations and precautions which should be followed in the
interest of maintaining the high standards of performance of
solid state devices.
The ratings included in RCA Solid State Devices data
bulletins are based on the Absolute Maximum Rating
System, which is defined by the following Industry Standard
(JEDEC) statement:
Absolute-Maximum Ratings are limiting values of operating and environmental conditions applicable to any electron
device of a specified type as defined by' its published data,
and should not be exceeded under the worst probable
conditions.
The device manufacturer chooses these values to provide
acceptable serviceability of the device, taking no responsi·
bility for equipment variations, environmental variations, and
the effects of changes in operating conditions due to
variations in device characteristics.
The equipment manufacturer should design so that
initially and throughout life no absolute-maximum value for
the intended service is exceeded with any device under the
worst probable operating conditions with respect to supplyvoltage variation, equipment component variation, equipment control adjustment, load variation, signal variation,
environmental conditions, and variations in device characteristics.
It is recommended that equipment manufacturers consult
RCA whenever device applications involve unusual electrical,
mechanical or environmental operating conditions.
GENERAL CONSIDERATIONS
The design flexibility prOvided by these devices makes
possible their use in a broad range of applications and under
740
many different operating conditions. When incorporating
these devices in equipment, therefore, designers should
antiCipate the rare 'possibility of device failure and make
certain that no safety hazard would result from such an
occurrence.
The small size of most solid state products provides
obvious advantages to the designers of electronic equipment.
However, it should be recognized that these compact devices
usually provide only relatively small insulation area between
adjacent leads and the metal envelope. When these devices
are used in moist or contaminated atmospheres, therefore,
supplemental protection must be prOvided to prevent the
development of electrical conductive paths across the
relatively small insulating surfaces. For specific information
on voltage creepage, the user should consult references such
as the JEDEC Standard No. 7 "Suggested Standard on
Thyristors," and JEDEC Standard RS282 "Standards for
Silicon Rectifier Diodes and Stacks".
The metal shells of some solid state devices operate at the
collector voltage and for some rectifiers and thyristors at the
anode voltage. Therefore, consideration should be given to
the possibility of shock hazard if the shells are to operate at
voltages appreciably above or below ground potential. In
general,. in any application in which devices are operated at
voltages which may be dangerous to personnel, suitable
precautionary measures should be taken to prevent direct
contact with these devices.
Devices should not be connected into or disconnected
from circuits with the power on because high transient
voltages may cause permanent damage to the devices.
TESTI NG PRECAUTIONS
In common with many electronic components, solid-state
devices should be operated and tested in circuits which have
reasonable values of current limiting resistance, or other
forms of effective current overload protection. Failure to
observe these precautions can cause excessive internal heating
of the device resulting in destruction and/or possible
shattering of the enclosure.
19·74
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ lCE-402
TRANSISTORS AND THYRISTORS
WITH FLEXIBLE LEADS
Flexible leads are usually soldered to the circuit elements.
H is desirable in all soldering operatings to provide some
slack or an expansion elbow in each lead to prevent
excessive tension on the leads. It is important during the
soldering operation to avoid excessive heat in order to
prevent possible damage to the devices. Some of the heat can
be absorbed if the flexible lead of the device is grasped
between the case and the soldering point with a pair of pliers.
TRANSISTORS AND THYRISTORS
WITH MOUNTING FLANGES
The mounting flanges of JEDEC-type packages such as
the TO-3 or TO-66 often serve as the collector or anode
terminal. In such cases, it is essential that the mounting
flange be securely fastened to the heat sink, which may be
the equipment chassis. Under no circumstances, however,
should the mounting flange of a transistor be soldered
directly to the heat sink or chassis because the heat of the
soldering operation could permanently damage the device.
Soldering is the preferred method for mounting thyristors:
see HRectifiers and Thyristors," below. Devices which cannot
be soldered can be installed in commercially available
sockets. Electrical connections may also be made by
soldering directly to the terminal pins. Such connections may
be soldered to the pins close to the pin seals provided care is
taken to conduct excessive heat away from the seals;
otherwise the heat of the soldering operation could crack the
pin seals and damage the device.
During operation, the mounting-flange temperature is
higher than the ambient temperature by an amount which
depends on the heat sink used. The heat sink must have
sufficient thermal capacity to assure that the heat dissipated
in the heat sink itself does not raise the device mountingflange temperature above the rated value. The heat sink or
chassis may be connected to either the positive or negative
supply.
In many applications the chassis is connected to the
voltage-supply terminal. If the recommended mounting
hardware shown in the data bulletin for the specific
solid-state device is not available, it is necessary to use either
an anodized aluminum insulator having high thermal conductivity or a mica insulator between the mounting-flange
and the chassis. If an insulating aluminum washer is required,
it should be drilled or punched to provide the two mounting
holes for the terminal pins. The burrs should then be
removed from the washer and the washer anodized. To insure
that the anodized insulating layer is not destroyed during
mounting, it is necessary to remove the burrs from the holes
in the chassis.
It is also important that an insulating bushing, such as
glass-filled nylon, be used between each mounting bolt and
the chassis to prevent a short circuit. However, the insulating
bushing should not exhibit shrinkage or softening under the
operating temperatures encountered. Otherwise the thermal
resistance at the interface between device and heat sink
may increase as a result of decreasing pressure.
PLASTIC POWER TRANSISTORS AND THYRISTORS
RCA power transistors and thyristors (SCR's and triacs)
in molded-silicone-plastic packages are available in a wide
range of power-dissipation ratings and a variety of package
configurations. The following paragraphs provide guidelines
for handling and mounting of these plastic-package devices,
recommend forming of leads to meet specific mounting
requirements, and describe various mounting arrangements,
thermal considerations, and cleaning methods. This information is intended to augment the data on electrical characteristics, safe operating area, and performance capabilities in the
technical bulletin for each type of plastic-package transistor
or thyristor.
Lead-Forming Techniques
The leads of the RCA VERSAWATT in-line plastic
packages can be formed to a custom shape, prOVided they are
not indiscriminately twisted or bent. Although these leads
can be formed, they are not flexible in the general sense, nor
are they sufficiently rigid for unrestrained wire wrapping
Before an attempt is made to form the leads of an in-line
package to meet the requirements of a specific application,
the desired lead configuration should be determined, and a
lead-bending fixture should be designed and constructed. The
use of a properly designed fixture for this operation
eliminates the need for repeated lead bending. When the use
of a special bending fixture is not practical, a pair of
long-nosed pliers may be used. The pliers should hold the
lead firmly between the bending point and the case, but
should not touch the case.
When the leads of an in-line plastic package are to be
formed, whether by use of long-nosed pliers or a special
bending fixture, the following precautions must be observed
to avoid internal damage to the device:
1. Restrain the le~d between the bending point and the
plastic case to prevent relative movement between the
lead and the case.
2. When the bend is made in the plane of the lead
(spreading), bend only the narrow part of the lead.
3. When the bend is made in the plane perpendicular to that
of the leads, make the bend at least 1/8 inch from the
plastic case.
4. Do not use a lead-bend radius of less than 1/16 inch.
5. Avoid repeated bending of leads.
The leads of the TO-220AB VERSAWATT in-line
package are not designed to withstand excessive axial pull.
Force in this direction greater than 4 pounds may result in
permanent damage to the device. If the mounting arrangement tends to impose .xial stress on the leads, some method
of strain relief should be devised.
Wire wrapping of the leads is permissible, provided that
the lead is restrained between the plastic case and the point
of the wrapping. Soldering to the leads is also allowed. The
maximum soldering temperature, however, must not exceed
275 0 C and must be applied for not more than 5 seconds at a
distance not less than 1/8 inch from the plastic case. When
741
1CE-402 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
wires are used for connections, care should be exercised to
assure that movement of the wire does not cause movement
of the lead at the lead-to-plastic junctions.
The leads of RCA molded-plastic high-power packages
are not designed to be reshaped. However, simple bending of
the leads is permitted to change them from a standard
vertical to a standard horizontal configuration, or conversely.
Bending of the leads in this manner is restricted to three
9O-degree bends; repeated bendings should be avoided.
Mounting
Recommended mounting arrangements and suggested
hardward for the VERSAWATT package are given in the data
bulletins for specific devices and in RCA Application Note
AN4142. When the package is fastened to a heat sink, a
rectangular washer (RCA Part No. NR23 I A) is recommended
to minimize distortion of the mounting flange. Excessive
distortion of the flange could cause damage to the package.
The washer is particularly important when the size of the
mounting hole exceeds 0.140 inch (6·32 clearance). Larger
holes are needed to accommodate insulating bushings;
however, the holes should not be larger than necessary to
provide hardware clearance and, in any case, should not
exceed a diameter of 0.250 inch.
Flange distortion is also possible if excessive torque is
used during mounting. A maximum torque of 8 inch·pounds
is specified. Care should be exercised to assure that the tool
used to drive the mounting screw never comes in contact
with the plastic body during the driving operation. Such
contact can result in damage to the plastic body and internal
device connections. An excellent method of avoiding this
problem is to use. a spacer or combination spacer·isolating
bushing which raises the screw head or nut above the top
surface of the plastic body. The material used for such a
spacer or spacer·isolating bushing should, of course, be
carefully selected to avoid "cold flow" and consequent
reduction in mounting force. Suggested materials for these
bushings are diallphtalate, fiberglass·filled nylon, or
fiberglass·filled polycarbonate. Unfilled nylon should be
avoided.
Modification of the flange can also result in flange
distortion and should not be attempted. The package should
not be soldered to the heat sink by use of lead·tin solder
because the heat required with this type of solder will cause
the junction temperature of the device to become excessively
high.
.
The TO·220AA plastic package can be mounted in
commercially available TO·66 sockets, such as UID
Electronics Corp. Socket No. PTS-4 or equivalent. For
testing purposes, the TO·220AB in·line package can be
mounted in a letron Socket No. DC74·104 or equivalent.
Regardless of the mounting method, the following
precautions should be taken:
1. Use appropriate hardware.
2. Always fasten the package to the heat sink before the
leads are soldered to fixed terminals.
3. Never allow the mounting tool to come in contact with
the plastic case.
742
4. Never exceed a torque of 8 inch·pounds.
5. Avoid oversize mounting holes.
6. Provide strain relief if there is any probability that axial
stress will be applied to the leads.
7. Use insulating bushings to prevent hot~reep problems.
Such bushings should be made of diallphthalate, fiberglass-filled nylon, or fiberglass-filled polycarbonate.
The maximum allowable power dissipation in a solid
state device is limited by the junction temperature. An
important factor in assuring that the junction temperature
remains below the specified maximum value is the ability of
the associated thermal circuit to conduct heat away from the
device.
When a solid state device is operated in free air, without a
heat sink, the steady-state thermal circuit is defined by the
junction-ta-free-air thermal resistance given in the published
data for the device. Thermal considerations require that a
free flow of air around the device is always present and that
the power dissipation be maintained below the level which
would cause the junction temperature to rise above the
maximum rating. However, when the device is mounted on a
heat sink, care must be taken to assure that all portions of
the thermal circuit are considered.
To assure efficient heat transfer from case to heat sink
when mounting RCA molded'plastic solid state power
devices, the following special precautions should be
observed:
1. Mounting torque should be between 4 and 8 inchpounds.
2. The mounting holes should be kept as small as possible.
3. Holes should be drilled or punched clean with no burrs or
ridges, and chamfered to a maximum radius of 0.010
inch.
4. The mounting surface should be flat within 0.002
inch/inch.
5. Thermal grease (Dow Corning 340 or eqUivalent) should
always be used on both sides of the insulating washer if
one is employed.
6. Thin insulating washers should be used. (Thickness of
factory-supplied mica washers range from 2 to 4 mils).
7. A lock washer or torque washer, made of material having
sufficient creep strength, should be used to prevent
degradation of heat sink efficiency during life;
A wide variety of solvents is available for degreasing and
flux removal. The usual practice is to submerge components
in a solvent bath for a specified time. However, from a
reliability stand point it is extremely important that the
solvent, together with other chemicals in the solder~leaning
system (such as flux and solder covers), do not adversely
affect the life of the component. This consideration applies
to all non-hermetic and molded-plastic components.
It is, of course, impractical to evaluate the effect on
long·term device life of all cleaning solvents, which are
marketed with numerous additives under a variety of brand
names. These solvents can, however, be classified with
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 1CE-402.
respect to their component parts as either acceptable or
unacceptable. Chlorinated solvents tend to dissolve the outer
package and, therefore, make operation in a humid atmosphere unreliable. Gasoline and other hydrocarbons cause the
inner encapsulant to swell and damage the transistor. Alcohol
is an acceptable solvent. Examples of specific, acceptable
alchols are isopropanol, methanol, and special denatured
alcohols, such as SDA I, SDA30, SDA34, and SDA44.
Care must also be used in the selection of fluxes for lead
soldering. Rosin or activated rosin fluxes are recommended,
while organic or acid fluxes are not. Examples of acceptable
fluxes are:
I. Alpha Reliaros No. 320-33
2. Alpha Reliaros No. 346
3. Alpha Reliaros No. 711
4. Alpha Reliafoam No. 807
5. Alpha Reliafoam No. 809
6. Alpha Reliafoam No. 811-13
7. Alpha Reliafoam No. 815-35
8_ Kester No. 44
If the completed assembly is to be encapsulated, the
effect on the molded-plastic transistor must be studied from
both a chemical and a physical standpoint.
RECTIFIERS AND THYRISTORS
A surge-limiting impedance should always be used in
series with silicon rectifiers and thyristors. The impedance
value must be sufficient to limit the surge current to the
value speCified under the maximum ratings. This impedance
may be proVided by the power transformer winding, or by an
external resistor or choke.
A very efficient method for mounting thyristors utilizing
the "modified TO-S" package is to provide intimate contact
between the heat sink and at least one half of the base of the
device opposite the leads. This package can be mounted to
the heat sink mechanically with glue or an expoxy adhesive,
or by soldering, the most efficient method.
The use of a "self-jigging" arrangement and a solder
preform is recommended. If each unit is soldered individually, the heat source should be held on the heat sink and the
solder on the unit. Heat should be applied only long enough
to permit solder to flow freely. For more detailed thyristor
mounting considerations, refer to Application Note AN3822,
"Thermal Considerations in Mounting of RCA Thyristors".
MOS FIELD-EFFECT TRANSISTORS
Insulated-Gate Metal Oxide-Semiconductor Field-Effect
Transistors (MOS FETs), like bipolar high-frequency
transistors, are susceptible to gate insulation damage by the
electrostatic discharge of energy through the devices.
Electrostatic discharges can occur in an MOS FET if a type
with an unprotected gate is picked up and the static charge,
built in the handler's body capacitance, is discharged through
the device. With proper handling and applications
procedures, however, MOS transistors are currently being
extensively used in production by numerous equipment
manufacturers in military, industrial, and consumer applica-
tions, with virtually no problems of damage due to
electrostatic discharge.
In some MOS FETs, diodes are electrically connected
between each insulated gate and the transistor's source.
These diodes offer protection against static discharge and
in-circuit transients without the need for external shorting
mechanisms. MOS FETs which do not include gateprotection diodes can be handled safely if the following basic
precautions are taken:
1. Prior to assembly into a circuit, all leads should be kept
shorted together either by the use of metal shorting
springs attached to the device by the vendor, or by the
insertion into conductive material such as "ECCOSORB*
LD26" or equivalent.
(NOTE: Polystyrene insulating "SNOW" is not sufficiently conductive and should not be used.)
2. When devices are removed by hand from their carriers,
the hand being used should be grounded by any suitable
means, for example, with a metallic wristband.
3. Tips of soldering irons should be grounded.
4. Devices should never be inserted into or removed from
circuits with power on.
RF POWER TRANSISTORS
Mounting and Handling
Stripline rf devices should be mounted so that the leads
are not bent or pulled away from the stud (heat sink) side of
the device. When leads are formed, they should be supported
to avoid transmitting the bending or cutting stress to the
ceramic portion of the device. Excessive stresses may destroy
the hermeticity of the package without displaying visible
damage.
Devices empluying silver leads are susceptible to
tarnishing; these parts should not be removed from the
original tarnish-preventive containers and wrappings until
ready for use. Lead solderability is retarded by the presence
of silver tarnish; the tarnish can be removed with a silver
cleaning solution, such as thiourea:
The ceramic bodies of many rf devices contain beryllium
oxide as a major ingredient. These portions of the transistors
should not be crushed, ground, or abraded in any way
because the dust created could be hazardous if inhaled.
Operating
Forward-BiaSlld Operation. For Class A or AB operation,
the allowable quiescent bias point is determined by reference
to the infrared safe-area curve in the appropriate data
bulletin. This curve depicts the safe current/voltage combinations for extended continuous operation.
Load VSWR. Excessive collector load or tuning mismatch
can cause device destruction by over-dissipation or secondary
breakdown. Mismatch capability is generally included on the
data bulletins for the more recent rf transistors.
See RCA RF Power Transitor Manual, Technical Series
RMF-430, pp 39-41, for additional information concerning
the handling and mounting of rf power transistors.
*Trade Mark: Emerson and Cumming, Inc.
743
1CE-402 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
INTEGRATED CIRCUITS
Handing
All COS/MaS gate inputs have a resistor/diode gate
protection network. All transmission gate inputs and all
outputs have diode protection provided by inherent p·n
junction diodes. These diode networks at input and output
interfaces protect COS/MaS devices from gate·oxide failure
in handling environments where static discharge is not
excessive. In low-temperature, low·humidity environments,
improper handling may result in device damage. See
ICAN·6000, "Handling and Operating Considerations for
MaS Integrated Circuits", for proper handling procedures.
Mounting
Integrated circuits are normally supplied with lead·tin
plated leads to facilitate soldering into circuit boards. In
those relatively few applications requiring welding of the
device leads, rather than soldering, the devices may be
obtained with gold or nickel plated Kovar leads.* It should be
recognized that this type of plating will not provide complete
protection against lead corrosion in the presence of high
humidity and mechanical stress. The aluminum·foil·lined
cardboard "sandwich pack" employed for static protection
of the flat·pack also provides some additional protection
against lead corrosion, and it is recommended that the
devices be stored in this package until used.
When integrated circuits are welded onto printed circuit
boards or equipment, the presence of moisture between the
closely spaced terminals can result in conductive paths that
may impair deyice performance in high·impedance appli·
cations. It is therefore recommended that conformal coatings
or potting be provided as an added measure of protection
against moisture penetration.
In any method of mounting integrated circuits which
involves bending or forming of the device leads, it is
extremely important that the lead be supported and clamped
between the bend and the package seal, and that bending be
done with care to avoid damage to lead plating. In no case
should the radius of the bend be less than the diameter of the
lead, or in the case of rectangular leads, such as those used in
RCA 14·lead and 16·lead flat.packages, less than the lead
thickness. It is also extremely important that the ends of the
bent leads be straight to assure proper insertion through the
holes in the printed·circuit board.
Operating
Unused Inputs
All unused input leads must be connected to either VSS
or VDD, whichever is appropriate for the logic circuit
involved. A floating input on a high·current type, such as the
CD4049 or CD4050, not only can result in faulty logic
operation, but can cause the maximum power dissipation of
200.milliwatts to be exceeded and may result in damage to
the device. Inputs to these types, which are mounted on
printed·circuit boards that may temporarily become
unterminated, should have a pull·up resistor to VSS or VDD.
A useful range of values for such resistors is from 10 kilohms
to I megohm.
744
Input Signals
Signals shall not be applied to the inputs while the device
power supply is off unless the input current is limited to a
steady state value of less than 10 milliamperes. Input
currents of less than 10 milliamperes prevent device damage;
however, proper operation may be impaired as a result of
current flow through structural diode junctions.
Output Short Circuits
Shorting of outputs to VSS or VDD can damage many of
the higher.output·current COS/MaS types, such as the
CD4007, CD4041, CD4049, and CD4050. In general, these
types can all be safely shorted for supplies up to 5 volts, but
will be damaged (depending on type) at higher power·supply
voltages. For cases in which a short·circuit load, such as the
base of a p·n-p or an n·p·n bipolar transistor, is directly
driven, the device output characteristics given in the
published data should be consulted to determine the
requirements for a safe operation below 200 milliwatts.
For detailed COS/MaS IC operating and handling
considerations, refer to Application Note ICAN·6000
"Handling and Operating Considerations for MaS Integrated
Circuits",
SOLID STATE CHIPS
Solid state chips, unlike packaged devices, are nonhermetic devices, normally fragile and small in physical size,
and therefore, require special handling considerations as
follows:
1. Chips must be stored under proper conditions to insure
that they are not subjected to a moist and/or contaminated atmosphere that could alter their electrical,
physical, or mechanical characteristics. After the shipping
container is opened, the chip must be stored under the
following conditions:
A. Storage temperature, 400 C max.
B. Relative humidity, 50% max.
C. Clean, dust-free environment.
2. The user must exercise proper care when handling chips
to prevent even the slightest physical damage to the chip.
3. During mounting and lead bonding of chips the user must
use proper assembly techniques to obtain proper electrical, thermal, and mechanical performance.
4. After the chip has been mounted and bonded, any
necessary procedure must be followed by the user to
insure that these non-hermetic chips are not subjected to
moist or contaminated atmosphere which might cause
the development of electrical conductive paths across the
relatively small insulating surfaces. In addition, proper
consideration must be given to the protection of these
devices from other harmful environments which could
conceivably adversely affect their proper performance.
*Mil-M-38510A, paragraph 3.5,6.1 la), lead material.
Subject Index
Page
Nos.
12
o.cceptance criteria
12
il.cceptable quality level (AOL)
12
il.cceptable reliability level
Aerospace high-reliability requirements
11
14
Alpha (a) risk
_69
Aluminum, glass-passivated
Aluminum TO-3 packages, hermeticity evaluation of
(AN-6071)
51
52
Engineering problem (AN-6071)
Failure analysis (AN-6071)
51
Failure data (AN-6071)
51
Thermal-cycling test results (AN-6071)
52
AND gates, high-relaibility COS/MOS
(technical data, File No. 844)
671
Arrays, high-reliability integrated-circuit
(technical data):
Diode (File Nos_ 722, 704)
316,336
308
Transistor (File No_ 762)
12
Assignable causes of variation
12
Average
12
Average outgoing quality (AOO)
13
Average outgoing quality limit (AOOL)
B
Ballasting, emitter-site
Ballasting resistors
Beta
risk
Bulk leakages
Burn-in
(m
68,71
68
13
21
13
Page
Nos.
Consumer's risk
13
Control chart, quality
13
Control limits, quality
13
23
Controlled solder process
COS/MOS chips:
Handling of (ICAN-6000)
706
Storing of (ICAN-6000)
707
COS/MOS CD4000A slash-series types
screened to MIL-STD-883 (RIC-l02C)
714
Electrical-test and delta limits (RIC-l02C)
718
Environmental sampling inspections (RIC-l02C)
718
Final electrical tests (RIC-l02C)
718
Ordering information (RIC-l02C)
716
Part-number code (RIC-l02C)
716
Product-flow diagram (RIC-l02C)
719
Screening levels, description of (RIC-l02C)
717
Total lot screening, description of (RIC-l02C)
717
COS/MOS integrated circuits, high-reliability
228,427-731
COS/MOS life-test data
238
COS/MOS MI L-M-38510 CD4000A series types
720
(RIC-l04A)
723
Electrical sampling inspection (RIC-l04A)
724
Environmental sampling inspection (RIC-l04A)
723
Final electrical tests (RIC-l04A)
721
Processing and screening requirements (RIC-l04A)
720
Product flow diagram (RIC-l04A)
725
Product-number code (RIC-l04A)
720
Screening levels (RIC-l04A)
724
Specification numbers (RIC-l04A)
Counters, high-reliability COS/MOS
517,533,584
(technical data, 733, 736, 755)
74,179
Current density, effect on reliability
20
Current gain
20
Currents, collector leakage
c
D
Case-temperature effects
Catastrophic failure
Chance failure
Characteristic
Collector current, reverse
Collector-ta-emitter saturation voltage
Collector leakage currents
Bulk leakages
Surface leakage
Collector mismatch
Commercial reliability requirements
Comparator, high-relability COS/MOS
(technical data, File No. 852)
Comparator, high reliability bipolar integrated
circuit (technical data, File 832)
Confidence interval
Confidence level
72
13
13
13
20
20
20
21
21
72
13
Darlington power transistor
(technical data)
DC safe area
Defect
Defective
Degradation failure
Delta tests or limits
Derating curve, power-transistor
Differential amplifiers, integrated-circuit
high-relaibility types (technical data,
File Nos_ 705, 706, 711, 707)
644
259
13
13
Diffusion current
Dimensional outlines (for integrated circuits)
Diode array (technical data, File No_ 722, 704)
Dissipated-limited region
46,48
69
13
13
13
233
20
276-287,
325-335, 345
20
732
316,336
20
745
Subject Index
Page
Nos.
E
Effect of temperature on silicon transistors
Electrical considerations power-transistor
Electromigration
Emitter-finger structure
Emitter-site ballasting
Energy-handling capability, power-transistor
Environment
Excess-phase factor
20
16
69,179
68
68,71
19
4
73
F
Failure analysis
Failure, catastrophic
Failure, chance or random
Failure, degradation
Failure mechanism
Failure mode
Failure rate
Final Qualification
Forward-bias second breakdown
194
13
13
13
13
13
13
240
17
G
Gain, current
General·purpose transistor
Glass-passivated aluminum
Group A inspections, power-transistor
15
42-44
69
24
H
Hermetic rf transistor packages
Heterogeneity
High-power transistors (technical data)
High-reliability COS/MaS CD4000A
slash-series types (R IC-l 02C)
High-reliability integrated circuits
Applications
Device nomenclature
General considerations
Life-test data, COS/MaS
Manufacturing controls
MI L-M-3851 0 requirements
MI L-STD-883 requirements
Packages
Technical data, COS/MaS types
Technical data, DMOS types
Technical data, linear types
746
70
13
47
714
225
228
227
226
238
226
234
228
226
427-705
403·414
241-402
High-reliability power transistors
Application notes on
Electrical considerations
JAN, JANTX, and JANTXV types
Processing and screening
Reliability considerations
Special rating considerations
Technical data on RCA types
High-reliability power transistors
(technical data)
High-reliability rf power transistors
Application note on
Design features
JAN, JANTX, and JANTXV types
H R-series types
Premium and ultra-high-reliability types
Special rating concepts
Technical data
High-reliability solid-state devices
Commercial requirements
Index to RCA types
Introduction to
Military and aerospace requirements
Military specifications for
High-reliability terms and definitions
High-reliability thyristors
8asic reliabilty considerations
Basic reliabilty testing
Failure analysis
Processing and screening
Technical data
High-speed power transistors
(technical data)
High-voltage power transistors
(technical data)
Homogeniety
Hometaxial-base power transistors
(technical data)
Hot-spot thermal resistance
HR-series rf power transistors
Burn-in test measurements
Product-flow diagram
Processing and screening
Reliability levels
Technical data
Inductive voltage-breakdown tesing,
power-transistor
Inherent reliability
Inspection:
By attributes
By variables
Pagl
Nos
15
51
16
25,30-37
25
16
16
30-50
30-50
67
179
68
75,74-84
75,85-134
77,135-182
70
79-178
11
6
11
11
11
12,239
193
194
196
196
197
200-224
39-42,45
42,46
13
30-32, 38, 40, 43
71
75,85-134
77
77
75
76
85-134
19
13
13
13
Su bject Index
Page
Nos_
inspection act
Inspection, final
Inspection item
Inspection lot
Inspection point
Inspection process
Inspection, sampling
Integrated circuit, high-reliability
Integrated circuits (1CE-402):
Handling and mounting
Input signals (for COS/MaS types)
Operating considerations
Output short circuits (in COS/MaS types)
Unused inputs (for COS/MaS types)
Interim Qualification
Ionizing electromagnetic pulse (AN-6320)
Irradiated power-transistor switches (AN-6320)
13
13
13
14
14
14
14
188
744
744
744
744
744
187
58
59
J
JAN, JANTX, and JANTXV power transistors
RCA types
Processing and screening
Technical data
JAN, JANTX, JANTXV rf power transistors:
RCA types
Technical data
Junction temperature, effect on reliability
25
26
25
30-37
75
79-84
74
Page
Nos_
Lot tolerance per cent defective
(LTPD)
LTPD sampling plans
13,229
28
M
Manufacturing Certification
Mathematical reliability
Mean time between failure
Medium power transistor
(technical data)
Microwave power-transistor reliability
(AN-6229)
186
14
14
38,41,45
179
Microwave power transistors
(technical data)
Military high-reliability requirements
Military specifications
MIL-M-38510
MIL-S-19500
MIL-STD-750
MI L-STD-883 requirements
COS/MaS integrated circuits
Linear integrated circuits
Mismatch, collector
MaS field-effect transistors, handling
and mounting (1 CE-402)
MaS integrated circuit,
handling considerations (lCAN-6000)
MTTForMTBF
113-130
11
12
12
12,26
26
228
228
233
72
743
706
240
L
Lambda
Layer, polycrystalline silicon
Lead-forming techniques (lCE-402)
Life-te~t conditions (for rf power transistors)
Life-test failure rate
Life, useful
Line Certification
Linear integrated circuits, CA3000
MIL-M-38510 series types (RIC-204)
Linear integrated circuits (CA3000 slash-series types)
screened to MIL-STD-883 (RIC-202A)
Electrical sampling inspection (RIC-202A)
Environmental sampling inspection (RIC-202A)
Final electrical tests (RIC-202A)
Ordering information (RIC-202A)
Part-number code (RIC-202A)
Product flow diagram (R IC-202A)
Screening levels (RIC-202A)
Total lot screening (RIC-202A)
13
69
74
14
14
339
421
415
419
420
419
420
420
415
416
418
N
Neutron-damage coefficeint,
derivation of (AN-6320)
Neutron testing (AN-6320)
Neclear radiation, effects of
65
59
24
o
Operating time
14
Operational amplifiers, high-reliability
COS/MaS-bipolar (technical data, File No_ 823)
397
Operational amplifiers, high-reliability integratedcircuit general-purpose types (technical data,
File Nos_ 826, 827, 832, 829, 718,715)
241-275,302
Operation amplifier, high-reliability micro power
(technical data, File No_ 831)
356
747
Subject Index
Page
Nos.
Operation amplifier, high-reliability powerhybrid, multipurpose (technical data,
File No_ 789)
Operational transconductance amplifier
(technical data, File No_ 709)
Operating considerations for RCA solid-state
device (1 CE-402)
Integrated circuits
MOS transistors.
R F power transistors
Rectifiers
Solid-state chips
Testing precautions
Thyristors
Transistors
Operating-life-test program, microwavetransistor (AN-6229)
Estimated MTF
Failure mode
Test conditions
Test data
Test vehicle
Overlay transistor structure
183
Programmable power-switch amplifier,
high-reliability integrated-circuit
(technical data, File No. 692)
37!
363
Q
744
741,743
743
743
744
740
743
741
179
182
181
180
181
181
69
p
Parameter
14
Photo current characteristics, transistor (AN-6320)
65
Photocurrent testing (AN-6320)
63
Plan, sampling
14
Polycrystalline silicon layer
69
Population (universe)
14
Power-switch/amplifier, programmable
(technical data, File No. 692)
375
Power transistors, high-reliability:
Electrical considerations
16
JAN, JANTX, and JANTXV types
27,30-36
Manufacturing controls
26
Reliability considerations
16
Power transistors (technical data):
Darlington types
46,48
High-current types
34
High-power types
47
High-speed types
32, 34-37, 42, 46
JAN, JANTX, andJANTXV types
30-36
Radiation-hardened types
49
Precision
14
Premium-and ultra-high-reliability
135-178
rf power transistors technical data
14
Process average
748
Pa
Nc
Quality-control chart
Quality-control limits
Quality level, acceptable
Quality level, indifference
Quality limit, average outgoing
Qualified Parts List (QPL)
Oualified products list
R
Radiation dose rate
Radiation, effect on power transistors
Displacement damage
Photocurrents
Radiation-enery effects, transient (AN-6320)
Radiation-hardened power transistors
(technical data)
Radiation levels
Radiation parameter
Radiation resistance of COS/MOS
CD4000A (lCAN-6224)
Random access memory, RAM
(technical data, File Nos. 751, 842)
Random failure
Random selection
Range
Real-time control
Redandancy
Reliability:
As a function of current density
As a function of junction temperature
Classes (MI L-M-38510)
Inherent
Levels (MIL-S-19500)
Mathematical
Requirements
Terms and definitions
Risk:
Alpha
Beta
Consumer's
Producer's
Reverse collector current
R F avalanche breakdown voltage
25
24
25
25
65
49
25
25
712
561,630
13
14
14
14
14
66
66
12
13
12
14
12
12
14
13
13
14
20
73
Subject Index
Page
Nos_
Page
Nos_
v
iafe-area systems, plused
lafe-operating-area chart
lample
iampling inspection
,ampling plan
Sampling plans, LTPD
Sampling plans, single, for normal inspection
Sample size code letters
Saturation current
Screening tests, power-transistor
Second breakdown
SEM specification
Shelf life
Shift registers, high-reliability COS/MaS
(technical data, File Nos_ 689,720,730,
738,740,751 )
"Slash" sheets
Solid-state chips, handling considerations
Specification
Specification, military
Stralified sample
Surface leakage
21
21
14
14
14
28
29
29
20
27
16
240
14
433, 468, 502,
543, 552, 557
Variables testing
Video amplifier, high-reliability
integrated-circuit (technical data,
File No. 714)
Voltage:
Base-to-emitter
Collector-to-emitter saturation
Voltage regulator, positive,
high-reliability integrated-circuit
(technical data, File No. 708)
14
282
20
20
370
w
Wide-band operational amplifier,
high-relaibility intergrated-circuit
(technical data, File No. 825)
383
186
14
13
14
20
z
Zero-voltage switch, high-reliability
integrated-circuit
(technical data, File No. 703)
350
T
Temperature, effect of on silicon transistors
Test circuits and connections for COS/MaS
Integrated circuits
Thermal-cycling capability
Effect of assembly methods on
Effect of package materials on
Thermal-cycling rating chart
Thermal fatigue
Thermal-fatigue testing
Thermal resistance, hot-spot
Thyristor package, hermetic
Tolerance
Transistor packages, hermetic (AN-6071)
Transistor structure, overlay
20
726
23
23
24,51
23
22
24
71
70
14
50
68
u
Universe
Useful life
14
14
749
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