1975_TI_The_Semiconductor_Memory_Data_Book 1975 TI The Semiconductor Memory Data Book

User Manual: 1975_TI_The_Semiconductor_Memory_Data_Book

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GENERAL INFORMATION

lie of Contents •

Alphanumeric Index •

Selection Guides •

Glossary

INTERCHANGEABiliTY GUIDE

MOS MEMORIES

TTL MEMORIES

ECl MEMORIES

MICROPROCESSOR SUMMARY

38510/MACH IV PROCUREMENT SPECIFICATION

JAN Mll-M-38510 INTEGRATED CIRCUITS

IC SOCKETS AND INTERCONNECTION PANELS

TI worldwide sales offices
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$2 95
(In U.S.A.>

The
Semiconductor
Memory
Data Book
for

Design Engineers

First Edition

TEXAS INSTRUMENTS
INCORPORATED
CC-420
43037-65-GI

Printed in U.S.A.

IMPORTANT NOTICES

Texas Instruments reserves the right to make changes at any time in
order to improve design and to supply the best product possible.
TI cannot assume any responsibility for any circuits shown or

represent that they are free from patent infringement.
Information contained herein supercedes previously published data
on these devices from TI.
Copyright © 1975
Texas Instruments Incorporated

4

I NTRODUCTI ON
This book contains detailed specifications for 111 semiconductor memory integrated circuits manufactured and supplied
worldwide by Texas Instruments. A continuous upgrading of process and design technology has resulted in a wide spectrum
of memory products with information retrieval times from a few nanoseconds to a few microseconds. They cover the basic
memory functions of serial storage, random·access mass storage, permanent read·only storage and programmable read-only
storage of binary information. These lSI high·technology products include:
•

59 MaS Memory products to provide system economy and large storage capacity from:
11 state-of-the·art high-density single transistor cell 4096·bit RAM's designed specifically for mass storage
systems
12 economical industry-standard 1024-bit static RAM's for simplified application in small or medium size
systems
24 different shift registers featuring highly efficient organizations for implementing serial and recirculating
memories in data communications and display systems

•

43 TTL high-performance memories, 38 with Schottky clamping, including:
256-bit and 1024-bit RAM's featuring modified
reliability

12 l

cell design and single-level metalization to enhance

PROM's featuring Titanium-Tungsten fuse links for fast and reliable programming
New high density 20-pin 2048-bit and 4096-bit PROM's for reduced board area and system cost
•

7 ECl ultra-high performance memories including:
5 RAM's with access times from 10 ns to 15 ns typically
1 256-bit PROM using Titanium-Tungsten fuse links with a typical access time of 15 ns

Also included are brief product descriptions of 4 microprocessor products from Texas Instruments, 3 manufactured with
MaS technology and the other with Integrated Injection logic (l 2 ll, a revolutionary new semiconductor technology. These
new microprocessor products are directly compatible with most of the semiconductor memory products included in this
book.
An eight-page glossary defines symbols and terms used with memory integrated circuits in accordance with current
deliberations by the EIA/JEDEC (Electronic Industries Association) and IEC (International Electrotechnical Commission).
Ordering instructions and mechanical data for the package types available are given at the end of the section for each
technology (MaS, TTL, and ECl).
The 38510/MACH IV Procurement Specification is included in its entirety and has been updated to include provisions for
memory circuits and for the CMOS technology. A current listing of JAN MI l-M-3851 0 integrated circuits provideds
cross-reference from circuit type number to 38510 slash sheet and from 38510 slash sheet to circuit type number. Also
covered are the 4096-bit RAMs processed to level III of the MACH IV specification.
The final section in the book is on IC sockets and interconnection panels. TI produces a complete line of these products, and
their inclusion here provides a handy reference for the design engineer.

5

6

II

General Information

7

TABLE OF CONTENTS
Alphanumeric Index
Selection Guides
Glossary
Interchangeability Guide
MOS Random Access Memories
TMS 1103, TMS 1103-1 1024-Bit (1024 X 1) Dynamic RAMs
TMS 4030, TMS 4030-1, TMS 4030-2 4096-Bit (4096 Xl) Dynamic RAMs
TMS 4033 1024-Bit (1024 X 1) Static RAM
TMS 4034 1024-Bit (1024 X 1) Static RAM
__ . . . . . . .
TMS 4035 1024-Bit (1024 X 1) Static RAM
........ .
TMS 4036, TMS 4036-1, TMS 4036-2 512-Bit (64 X 8) Static RAMs
TMS 4039, TMS 4039-1, TMS 4039-2 1024-Bit (256 X 4) Static RAMs
TMS 4042, TMS 4042-1, TMS 4042-2 1024-Bit (256 X 4) Static RAMs
TMS 4043, TMS 4043-1, TMS 4043-2 1024-Bit (256 X 4) Static RAMs
TMS 4050, TMS 4050-1, TMS 4050-2 4096-Bit (4096 X 1) Dynamic RAMs
TMS 4051, TMS 4051-1 4096-Bit (4096 X 1) Dynamic RAMs
.....
TMS 4060, TMS 4060-1, TMS 4060-2 4096-Bit (4096 Xl) Dynamic RAMs
TMS 4062 1024-Bit (1024 X 1) Dynamic RAM
TMS 4063 1024-Bit (1024 X 1) Dynamic RAM
Extended Temperature Range and Hi-Rei 4096-Bit RAMs
MOS Read-Only Memories
TMS 2501 64 X 5 X 7 Static USASCII Character Generator
TMS 4103 64 X 5 X 7 Static USASCII Character Generator
TMS 4700 8192-Bit (1024 X 8) ROM . . . . . . . . .
TMS 4800 16384-Bit (2048 X 8 or 4096 X 4) ROM
TMS 5001 Four-Mode Dynamic 90-Key Keyboard Encoder
MOS Shift Registers
TMS 3101 Dual 100-Bit Static Shift Register
TMS 3112 Hex 32-Bit Static Shift Register
TMS 3122 Hex 32-Bit Static Shift Register .
TMS 3123 Hex 32-Bit Static Shift Register .
TMS 3113 Dual 133-Bit Static Shift Register
TMS 3114 Dual 128-Bit Static Shift Register
TMS 3120 Quadruple 80-Bit Static Shift Register
TMS 3121 Quadruple 64-Bit Static Shift Register
TMS 3126 Dual 96-Bit Static Shift Register .
TMS 3127 Dual 100-Bit Static Shift Register
TMS 3128 Dual 128-Bit Static Shift Register
TMS 3129 Dual 132-B it Static Sh ift Register
TMS 3130 Dual 133-Bit Static Shift Register
TMS 3131 Dual 136-Bit Static Shift Register
TMS 3132 Dual 144-Bit Static Shift Register
TMS 3133 1024-Bit Static Shift Register . .
TMS 3135 9- by 80-Bit Static Shift Register .
TMS 3137 9- by 100-Bit Static Shift Register
TMS 3138 9- by 128-Bit Static Sh ift Register
TMS 3139 9- by 132-Bit Static Shift Register
TMS 3140 9- by 133-Bit Static Shift Register
TMS 3401 512-Bit Dynamic Shift Register
TMS 3409 Quadruple 8-Bit Dynamic Shift Register
TMS 3417 Quadr.uple 64-Bit Dynamic Shift Register

II

8

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Page
10
11
15
23
36
41
49
49
49
53
57
61
65
69
77
85
93
93
101
105
106
107
111
117
123
124
124
124
128
128
131
131
134
134
134
134
134
134
134
137
140
140
140
140
140
143
144
144

TABLE OF CONTENTS

Page
Other MOS Circuits
TMS 4024 9- by 64-Bit Dynamic FIFO Memory . . . . . . .
TMS 6011 Asynchronous Data Interface (UART)
..... .
Power Supplies, Interfaces, and Input/Output Circuits for MOS Memories
MOS Ordering I nstructions and Mechanical Data . . . . . . . . . .
TTL Random-Access Read!Write Memories
SN54S189, SN74S189 64-Bit (16 X 4) RAMs with 3-State Outputs
SN54S201, SN74S201 256-Bit (256 X 1) RAMs with 3-State Outputs
SN74S209 1024-Bit (1024 X 1) RAM with 3-State Output . . . .
SN54S289, SN74S289 64-Bit (1£? X 4) RAMs with Open-Collector Outputs
SN54S301, SN74S301 256-Bit (256 X 1) RAMs with Open-Collector Outputs
SN74S309 1024-Bit (1024 X 1) RAM with Open-Collector Output
SN7489 64-Bit (16 X 4) RAM with Open-Collector Outputs
.... ..
TTL Programmable Read-Only Memories
SN54186, SN74186 512-Bit (64 X 8) PROMs with Open-Collector Outputs
SN54188A, SN74188A 256-Bit (32 X 8) PROMs with Open-Collector Outputs
SN54S188, SN74S188 256-Bit (32 X 8) PROMs with Open-Collector Outputs
SN54S287, SN74S287 1024-Bit (256 X 4) PROMs with 3-State Outputs
SN54S288, SN74S288 256-Bit (32 X 8) PROMs with 3-State Outputs
SN54S387, SN74S387 1024-Bit (256 X 4) PROMs with Open-Collector Outputs
SN54S470, SN74S470 2048-Bit (256 X 8) PROMs with Open-Collector Outputs
SN54S471, SN74S471 2048-Bit (256 X 8) PROMs with 3-State Outputs
SN54S472, SN74S472 4096-Bit (512 X 8) PROMs with 3-State Outputs
SN54S473, SN74S473 4096-Bit (512 X 8) PROMs with Open-Collector Outputs
TTL Read-Only Memories
SN5488A, SN7488A 256-Bit (32 X 8) ROMs with Open-Collector Outputs
SN54187, SN74187 1024-Bit (256 X 4) ROMs with Open-Collector Outputs
SN54S270, SN74S270 2048-Bit (512 X 4) ROMs with Open-Collector Outputs
SN54S271, SN74S271 2048-Bit (256 X 8) ROMs with Open-Collector Outputs
SN54S370, SN74S370 2048-Bit (512 X 4) ROMs with 3-State Outputs
SN54S371, SN74S371 2048-Bit (256 X 8) ROMs with 3-State Outputs
TTL Ordering I nstructions and Mechanical Data . . . . . . . .
ECl Memories
SN 10139 256-Bit (32 X 8) Programmable Read-Only Memory
SN 10140 64-Bit (64 X 1) Random-Access Memory
SN10142 64-Bit (64 X 1) Random-Access Memory .
SN10148 64-Bit (64 X 1) Random-Access Memory .
SN 10144 256-Bit (256 X 1) Random-Access Memory
SN10145 64-Bit (16 X 4) Random-Access Memory .
SN10147 128-Bit (128 X 1) Random-Access Memory
ECl Ordering I nstructions and Mechanical Data
.......... .
Microprocessors
38510/MACH IV Procurement Specification
JAN Mll-M-38510 Integrated Circuits
IC Sockets and Interconnection Panels . .

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147
152
159
163
172
172
172
172
172
172
178

II

I

182
182
182
182
182
182
182
182
182
182
190
190
190
190
190
190
198
203
208
208
208
211
214
217
222
223
229
259
265

9

ALPHANUMERIC INDEX

SBP0400
SN10139
SN10140
SN10142
SN10144
SN10145
SN10147
SN10148
SN5488A
SN54186
SN54187
SN54188A
SN54S188
SN54S189
SN54S201
SN54S270
SN54S271
SN54S287
SN54S288
SN54S289
SN54S301
SN54S370
SN54S371
SN54S387
SN54S470
SN54S471
SN54S472
SN54S473
SN7488A
SN7489
SN74186
SN74187
SN74188A
SN74S188
SN74S189
SN74S201
SN74S209
SN74S270
SN74S271

a

Page
224
203
208
208
211
214
217
208
190
182
190
182
182
172
172
190
190
182
182
172
172
190
190
182
182
182
182
182
190
178
182
190
182
182
172
172
172
190
190

Page
182
182
172
172
172
190
190
182
182
182
182
182
226
36
36
105
123
124
128
128
131
131
124
124
134
134
134
134
134
134
134
137
140
140
140
140
140
143

SN74S287
SN74S288
SN74S289
SN74S301
SN74S309
SN74S370
SN74S371
SN74S387
SN74S470
SN74S471
SN74S472
SN74S473
TMS 1000
TMS 1103
TMS 1103-1
TMS 2501
TMS 3101
TMS 3112
TMS 3113
TMS3114
TMS 3120
TMS 3121
TMS 3122
TMS 3123
TMS 3126
TMS 3127
TMS 3128
TMS 3129
TMS 3130
TMS 3131
TMS 3132
TMS 3133
TMS 3135
TMS 3137
TMS 3138
TMS 3139
TMS 3140
TMS 3401

*Extended Temperature Range and Hi-ReI (SMC) versions start on page 101.

10

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TMS 3409
TMS 3417
TMS 4024
TMS 4030*
TMS 4030-1
TMS 4030-2
TMS 4033
TMS 4034
TMS 4035
TMS 4036
TMS 4036-1
TMS 4036-2
TMS 4039
TMS 4039-1
TMS 4039-2
TMS 4042
TMS 4042-1
TMS 4042-2
TMS 4043
TMS 4043-1
TMS 4043-2
TMS 4050*
TMS 4050-1
TMS 4050-2
TMS 4051
TMS 4051-1
TMS 4060*
TMS 4060-1
TMS 4060-2
TMS4062
TMS 4063
TMS 4103
TMS 4700
TMS 4800
TMS 5001
TMS 5501
TMS 6011
TMS 8080

Page
144
144
147
41
41
41
49
49
49
53
53
53
57
57
57
61
61
61
65
65
65
69
69
69

77
77
85
85
85
93
93
106
107
111
117
228
152
228

RAMs, PROMs, ROMs
SELECTION GUIDE
BITS PER WORD

WORDS

16

B

4

2

1

RAMs
SN10145
SN54S189/SN74S189
SN54S289/SN74S289
SN7489

,\'0

I?J'},.

32

..B.Q.Mj
SN5488A1SN7488A
PROMS
SN54188A1SN74188A
SN54S188/SN74S188
SN 54S288/SN 74S288

'Ot>.

II
I

,\'},.CO
RAMs
niis4036

RAMs
SN10140
SN10142
SN10148

64

eBQM.s
SN541861SN74186

'},.<;,'O

RAMs
S'NiOi47

128

<;,'\'1-

256

RAMs
TMS 4039, TMS 4042, TMS 4043
ROMs
SN541ii7TsN74187
PROMs
SN54S287/SN74S287
SN54S387/SN74S387

RAMs
SN'i"0144
SN54S201/SN74S201
SN54S301/SN74S301

ROMs
SN54S2711SN74S271
SN54S3711SN74S371

~
SN54S4701SN74S470
SN54S4711SN74S471

,\()'J}c
PROMs
SN"74S472
SN74S473

ROMs
SN54S27O!SN74S270
SN54S370/SN 74S370

512
CO
'1-()r:..
~
TMS 1103 TMS 4033
TMS 4034 TMS 4035
TMS 4062 TMS 4063
SN74S209 SN74S309

1024

~
TMS4700

r:..()C?>'O

~

"C?>'},.

2048

TMS4800

CO
.

'J,COr:..

,\'0

4096

RAMs
TMS 4030
TMS4Q50
TMS 4051
TMS 4060

ROMs
TMS4'800

(I'OCO
I?J'1-

Numbers on shaded lines indicate overall complexity

11

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•

-"'
N

cn:=

m>
:;:i:

POWER DISSIPATION PER BIT
vs
MEMORY ACCESS TIME

1~

t

I I II

(7)

.;--...

I

I I

n!!'
-4

-

II~

II

-a

0:=
20

C):i:
C!!,

IE'4

4~

.....I

~

2r-

@

2~

-i
[TI

><
)-

(J)

z_

8z
~(J)

O.....j

:0

~

E
I

.~
Co

0

o~

a.

[TI

~
.0.

Z

.....j

A ~~ @

0.4

.~

~;o
~c

07~

c:

~

0

~
A

0.+

2048

>

f-

0.1

(J)

0.07

~
0.04 l-

0.02

I E = ECl

0= RAM
M= MOS 6= PROM
T=TTl
0= ROM
Numbers inside symbols
indicate number of bits.

0.01
2

4

7

10

20

40

70

Typical Memory Access Time-ns

100

200

400

700

tooo

c:=

mo
:i:
en

RAMs. PROMs. ROMs
SELECTION GUIDE

I

II
I

c
I

E

f=

Q)

u

u

«

o>E

~
rou

.0.
>

I-

~6tJed Jad Sl!8-Al!Xaldwo:J

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13

SHIFT REGISTERS
SELECTION GUIDE

SHIFT REGISTERS
REGISTERS PER PACKAGE

BITS PER
REGISTER

1

4

2

6

9

TMS 3112
TMS 3122

32

a

TMS 3123
TMS 3121
64
TMS 3417
TMS 3120
TMS 3135

80
TMS 3409
96

TMS 3126
TMS 3101
TMS 3137

100
TMS 3127
TMS 3114

TMS 3138

128
TMS 3128
132

TMS 3139

TMS 3129
TMS 3113

TMS 3140

133
TMS 3130

14

136

TMS 3131

144

TMS 3132

512

TMS 3401

1024

TMS 3133

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.

GLOSSARY
MEMORY INTEGRATED CIRCUIT TERMS AND DEFINITIONS
INTRODUCTION
This glossary consists of three parts: (1) general concepts and types of memories, (2) operating conditions and
characteristics (including letter symbols). and (3) graphic symbols and logic conventions. The terms, symbols,
abbreviations, and definitions used with memory integrated circuits have not, as yet, been standardized. All are
currently under consideration by the EIA/JEDEC (Electronic Industries Association) and the IEC (International
Electrotechnical Commission). The following are as consistent with the past and future works of these organizations as
is possible to anticipate at this time.

PART I-GENERAL CONCEPTS AND TYPES OF MEMORIES

II

Chip-Enable Input
A control input to an integrated circuit that, depending on the logic level applied to it, will either permit or prevent
operation of the device for input, internal transfer, manipulation, refreshing, and output of data.
NOTES: 1. Retention of data by a static memory is not affected by the logic level of the chip-enable input.
2. See "Chip-Select Input."

I

Chip-Select Input, Output-Enable Input
A control input to an integrated circuit that, depending on the logic level applied to it, will either permit or prevent the
output of data from the device ..
NOTES: 1. A chip-select input usually differs from a chip-enable input in that the chip-select input does not
necessarily prevent input and internal manipulation of data when it disables the output, while the
chip-enable input has that broader function.
2. When disabled by a chip-enable or chip-select signal, the outputs will assume a low level, a high level, or a
floating (high-impedance) state, depending on the design of the particular circuit.

Dynamic (Read/Write) Memory
A read/write
stored.
NOTES: 1.
2.
3.
4.

memory in which the cells require the repetitive application of control signals in order to retain the data
The words "read/write" may be omitted from the term when no misunderstanding will result.
Such repetitive application of the control signals is normally called a refresh operation.
A dynamic memory may use static addressing or sensing circuits.
This definition applies whether the control signals are generated inside or outside the integrated circuit.

First-In, First-Out (FI FO) Memory; Digital Storage Buffer
A memory from which data bytes or words can be read in the same order, but not necessarily at the same rate, as that
of the data entry.

Last-In, First-Out (L1 FO) Memory
A memory from which data bytes or words can be read with the order reversed from that of data entry.

Mask-Programmed Read-Only Memory
A read-only memory in which the data content of each cell is determined during manufacture by the use of a mask, the
data content thereafter being unalterable.

Memory Cell
The smallest subdivision of a memory into which data has been or can be entered, in which it is or can be stored, and
from which it can be retrieved.

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GLOSSARY
MEMORY INTEGRATED CIRCUIT TERMS AND DEFINITIONS
Memory Integrated Circuit
An integrated circuit consisting of memory cells and usually including associated circuits such as those for address
selection, ampl ifiers, etc.

Parallel Access
A feature of a memory by which all the bits of a byte or word are entered simultaneously at several inputs or retrieved
simultaneously from several outputs.

a

Programmable Read-Only Memory (PROM)
A read-only memory that after being manufactured can have the data content of each memory cell altered once only.

Random-Access Memory (RAM)
A memory that provides access to any' of its address locations in any desired sequence with similar nominal access time
for each location.
NOTE: Although this term can be used with either read/write or read-only memories, it is often used by itself in
referring to a read/write memory.

Read-Only Memory (ROM)
A memory intended to be read only.
NOTE: Unless otherwise qualified, the term "read-only memory" implies that the content is unalterable and defined
by construction.

Read/Write Memory
A memory in which each cell may be selected by applying appropriate electronic input signals and the stored data may
be either (a) sensed at appropriate output terminals, or (b) changed in response to other similar electronic input signals.

Reprogrammable Read-Only Memory
A read-only memory that after being manufactured can have the data content of each memory cell altered more than
once.

Serial Access
A feature of a memory by which all the bits of a byte or word are entered sequentially at a single input or retrieved
sequentially from a single output.

Static (Read/Write) Memory
A read/write memory in which the data is retained in the absence of control signals.
NOTES: 1. The words "read/write" may be omitted from the term when no misunderstanding will result.
2. A static memory may use dynamic addressing or sensing circuits.

Volatile Memory
A memory the data content of which is lost when power is removed.

16

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GLOSSARY
MEMORY INTEGRATED CIRCUIT TERMS AND DEFINITIONS
PART II-OPERATING CONDITIONS AND CHARACTERISTICS (INCLUDING LETTER SYMBOLS)
The symbols for quantities involving time use upper and lower case letters according to the following historically
evolved principles:
a. Time itself, is always represented by a lower case t.
b. Subscripts are lower case when one or more letters represent single words, e.g. d for delay, su for setup, rd for
read, wr for write.

a

c. Multiple subscripts are upper case when each letter stands for a different word, e.g. CS for chip select, PLH for
propagation delay from low to high, RMW for read, modify write.

Access Time
The time between the application of a specified input pulse during a read cycle and the availability of valid data signals
at an output.
Example symbology:
ta(ad,LH)
ta(ad,HL)
ta(CE)
ta(CS)

Access
Access
Access
Access

time
time
time
time

from
from
from
from

address, low-to-high-Ievel output
address, high-to-Iow-Ievel output
chip enable
chip select

Current
High-level input current, II H
The current into* an input when a high-level voltage is applied to that input.
High-level output current, 10H
The current into* an output with input conditions applied that according to the product specification will establish a
high level at the output.
Low-level input current, III
The current into* an input when a low-level voltage is applied to that input.
Low-level output current, 10L
The current into * an output with input conditions applied that according to the product specification will establish a
low level at the output.
Off-state (high-impedance-state) output current (of a three-state output), IOZ
The current into* an output having three-state capability with input conditio~s applied that according to the product
specification will establish the high-impedance state at the output.
Short-circuit output current, lOS
The current into * an output when the output is short-circuited to ground (or other specified potential) with input
conditions applied to establish the output logic level farthest from ground potential (or other specified potential).
Supply current, ICC, 100, lEE, IGG, ISS
The current into*, respectively, the VCC, VDD, VEE, VGG, or VSS supply terminal of an integrated circuit.

'Current out of a terminal is given as a negative value.

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I

GLOSSARY
MEMORY INTEGRATED CIRCUIT TERMS AND DEFINITIONS
Cycle Time
Read cycle time, tc(rd) (see note)
The time interval between the start of a read cycle and the start of the next cycle.
Read, modify write cycle time, tc(RMW) (see note)
The time interval between the start of a cycle in which the memory is read and new data is entered and the start of the
next cycle.

a

Write cycle time, tc(wr) (see note)
The time interval between the start of a write cycle and the start of the next cycle.
NOTE: The read, write, or read, modify write cycle time is the actual interval between two impulses and may be
insufficient for the completion of operations within the memory. A minimum value is specified that is the
shortest time in which the memory will perform its read and/or write function correctly.

Data Valid Time
Data valid time with respect to chip select, tDV(CS)
The interval following chip deselection during which output data continues to be valid.
Data valid time with respect to address, tDV(ad)
The interval following an initial change of address during which data stored at the initial address continues to be valid at
the output.

Delay Time
The time between the specified reference points on two waveforms.
Example symbology:
td(¢1-¢2)
td(PH-CEH)

Delay time, clock 1 to clock 2
Delay time, precharge high to chip enable high

Hold Time
Hold time, th
The interval during which a signal is retained at a specified input terminal after an active transition occurs at another
specified input terminal.
NOTES: 1. The hold time is the actual time between two events and may be insufficient to accomplish the intended
result. A minimum value is specified that is the shortest interval for which correct operation of the logic
element is guaranteed.
2. The hold time may have a negative value in which case the minimum limit defines the longest interval
(between the release of data and the active transition) for which correct operation of the logic element is
guaranteed.
Example symbology:
th(ad)
thIda)
thIrd)
th(wr)
th(rs)

18

Address hold time
Data hold time
Read hold time
Write hold time
Reset hold time

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GLOSSARY
MEMORY INTEGRATED CIRCUIT TERMS AND DEFINITIONS
Output Enable and Disable Time
Output enable time (of a three-state output) to high level, tpZH (or low level, tPZL)
The propagation delay time between the specified reference points on the input and output voltage waveforms with the
three-state output changing from a high-impedance (off) state to the defined high (or low) level.

..

Output enable time (of a three-state output) to high or low level, tpzx
The propagation delay time between the specified reference points on the input and output voltage waveforms with the
three-state output changing from a high-impedance (off) state to either of the defined active levels (high or low).
Output disable time (of a three-state output) from high level, tPHZ (or low level, tPLZ)
The propagation delay time between the specified reference points on the input and output voltage waveforms with the
three-state output changing from the defined high (or low) level to a high-impedance (off) state.
Output disable time (of a three-state output) from high or low level, tpxz
The propagation delay time between the specified reference points on the input and output voltage waveforms with the
three-state output changing from either of the defined active levels (high or low) to a high-impedance (off) state.

Propagation Time
Propagation delay time, tPD
The time between the specified reference points on the input and output voltage waveforms with the output changing
from one defined level (high or low) to the other defined level.
Propagation delay time, low-to-high-Ievel output, tPLH
The time between the specified reference points on the input and output voltage waveforms with the output changing
from the defined low level to the defined high level.
Propagation delay time, high-to-Iow-Ievel output, tpHL
The time between the specified reference points on the input and output voltage waveforms with the output changing
from the defined high level to the defined low level.

Pulse Width
Pulse width, tw
The time interval between specified reference points on the leading and trailing edges of the pulse waveform.
Example symbology:
tw(CEH)
tw(CEL)
tw(clr)
tw(CS)
tw(

VDD~

Riw 0

I>

A5 A6 A7 AS A9
COLUMN ADDRESSES

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VOO (see Note 1)
Supply voltage, VSS (see Note 1)
Input voltage (any input) .
Continuous power dissipation.
Operating free-air temperature range: TMS 1103
TMS 1103-1
Storage temperature range.

-25 to 0.3 V
-25 to 0.3 V
-25 to 0.3 V
1W

O°C to 70°C
O°C to 55°C
-65°C to 150°C

NOTE 1: Under absolute maximum ratings. voltage values are with respect to the most·positive supply voltage, VSB (substrate). Throughout
the remainder of this data sheet. voltage values are with respect to VOO.

recommended operating conditions
TMS 1103

PARAMETER

MIN

NOM

15.2

16

TMS 1103·1

MAX

MIN

NOM

16.8

18

19

0

Supply voltage, VOO
Supply voltage, VSS

MAX

UNIT
V

0
20

V

Supply voltage, VBB-VSS (see Note 2)

3

4

3

4

V

Operating free-air temperature, T A

0

70

0

55

°c

NOTE 2. VSB-VSS supply should be applied at the same time as or before VSS.

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II

w

CIQ

- .....

electrical characteristics at specified free-air temperatures

~3:

Vss = 16.8 v. (VBB-VSS) = 3 V. VDD = 0 V (TMS 1103 JL. NL)
VSS = 20 v. (VBB-VSS) = 3 V. VDD = 0 V (TMS 1103-1 JL. NL)

~cn

-. . . =
CD -

PARAMETER

VIH
VIL
VIL

TEST CONDITIONSt
TA = MIN

High-level input voltage

TA - MAX

[TI

><
~ :t>
~

~
[Jl

~8Z

~~en

100(3)

'""'l

100(4)

~
~
~

Z

en

VSS +1
VSS+1
VSS -18

VSS -20

VSS -18

Low-level input voltage (precharge, chip·

TA

VSS -17

VSS -14.7

VSS -20

VSS -18

enable, and read/write inputs) (see Note 3)

IBB

[TI

VSS-1
VSS-1
VSS -20

IO(oft)

~

VSS+1
VSS+1
VSS -14.2

High-level output current

:o~

VSS-1
VSS -0.7

VSS -14.5

IOH

~~c:

MAX

VSS -17

High-level output voltage

100(2)

TYPt

VSS -17

Input current

g;;o

MIN

TA - MIN

II

100(1)

MAX

TA - MAX

VOH

• 0'""'l

TYPt

Low-level input voltage (all addresses

MIN

TA - MAX
RL

100n,

Vss -17
TA

Vss -15

Vss -20

25 C

60

90

500

115

130

900

50

80

500

90

115

900

RL - 100 n,

TA - MAX
TA - MIN to MAX

RL=100n,

TA = 25°C

600

900

5000

1150

1130

9000

RL=100n,

TA = MAX

500

800

5000

900

1150

9000

Off-state output current

Vo = 0 V,

TA = MIN to MAX

Supply current from VBB

TA - MIN to MAX

Supply current from VOO during

All addresses - 0 V,

et: at VSS, VI=VSS

precharge pulse width

Precharge = 0 V,

TA = 25°C

Supply current from VOO during

All addresses = 0 V, CE at 0 V, VI =VSS

precharge and chip-enable overlap

Precharge = 0 V,

TA=25°C

Supply current from VOO during

Precharge = VSS,

CE atO V, VI =VSS

precharge to end of chip enable

TA = 25°C

Supply current from VOO during

Precharge = VSS,

chip enable to precharge delay

TA = 25°C

1

CE at VSS, VI = VSS

C

UNIT

10

Zr
V

l>Z

3::.V

n .....
::J::J3:

V

l>en

Z_

C-

mV

O~

p.A

3:.!.A
I

l>c...

p.A

1

10

p.A

100

100

p.A

nr
n

mz

37

56

45

60

mA

en
en

38

59

50

68

mA

m

5.5

11

8_5

11

p.A

0
::J::J

3

4

3

4

mA

3:
3:

m

en

:

AVerage supply current
100(av)

from VOO

TMS 1103
TMS 1103-1

twW) - 190 ns,

tc - 580 ns,

TA = 25°C

twW) - 105 ns,

I

tc = 340 ns

17

25

20

23

mA

TA = 25°C
I

t For conditions shown as MI N or MAX. use the appropriate value specified under recommended operating conditions.

l

All typical values are at T A

= 25° C.

NOTE 3. The maximum values for V I L for precharge. chip-enable. and read/write ofthe TMS 1103 may be increased to VSS - 14.2 Vat 0° C and VSS - 14.5 Vat 70° C (same values as
those specified for the address and data-in lines) with a 40-ns degradation (worst case) in tsu(ad-CE). td(PL.CEL). tc(rd). tc(RW). ta(ad). and taW)'

~

W

-

a.Q.
~

""

10

20

30

40

50

T A - Free-Air Temperature -

60

30

~~~--+---~---r=-~=---~~

I

~
o
o

251-----.,I----+---~---r----+----~_l
CURRENT MEASURED AT
MINIMUM CYCLE TIMES

20

MAXIMUM RECOMMENDED

o

175 200

~

10

1

125 150

E

'"

2

100

45

«

I

Ji

75

AVERAGECURRENTvsTEMPERATURE

1000

E

50

CL - Load Capacitance - pF

70

°c

15

~--~--+----t----r---+----~~

~~~--~--~--~--~----~~

o

10

20

30

40

50

60

T A - Free-Air Temperature -

P~INTED

48

70

°c

IN USA

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MOS
LSI

TMS 4033 JL, NL; TMS 4034 JL, NL; TMS 4035 JL, NL
1024-WORD BY 1-81T STATIC RANDOM-ACCESS MEMORIES
BULLETIN NO. DL-S 7512189, OCTOBER 1974-REVISED MAY 1975

•

1024 x 1-Bit Organization

•

Static Operation (No Clocks,

16-PIN CERAMIC AND PLASTIC
DUAL-IN-LiNE PACKAGES
(TOP VIEW)

No Refresh)
•

Input Interface
Fully Decoded

A6

16

A7

AS

15

AS

R/W

14

A9

TTL Compatible
Static Charge Protection
•

A1

Output Interface
3-State

A2

Fan-out 1 Series 74 TTL Load
OR-Tie Capability
•

CE

A3

Interchangeable with Intel 2102-1,
2102-2, and 2102 Respectively

•

N-Channel Silicon-Gate Technology

AO

DATA OUT
DATA IN

A4

Access Time
TMS 4033 JL, NL ... 450 ns Max
TMS 4034 JL, NL ... 650 ns Max
TMS 4035 JL, NL ... 1000 ns Max

•

12

10

8

VCC

II

GND

description
This series is a family of static random-access memories, each organized as 1024 one-bit words_ Due to their static
design, system overhead costs are minimized by elimination of refresh-clocking circuitry and by simplification of the
timing requirements. In addition all inputs and outputs are fully compatible with Series 74 TTL, including the single
5-volt power supply. These memories are fabricated by means of the same technology employed with the TMS 4030
JL, NL 4K RAM - N-channel silicon-gate. This technology provides optimum chip density and performance when cost
is considered_ Three performance ranges allow the designer to better match the memory to the specific system
requirements, thereby maximizing the cost/performance trade-off.
The TMS 4033, TMS 4034, and TMS 4035 are offered in 16-pin dual-in-line ceramic (JL suffix) and plastic (NL suffix)
packages designed for insertion in mounting-hole rows on 300-mil centers. These devices are characterized for operation
from 0° C to 70° C.

operation
Addresses (AO-A9)
Address inputs are used to select individual storage locations within the RAM_ Since the addresses are not latched, the
address-valid time determines the cycle time during both the read and write cycle_ Therefore, the address-valid time
must be a minimum of 450 nanoseconds for the TMS 4033, 650 nanoseconds for the TMS 4034, and 1000
nanoseconds for the TMS 4035. The address inputs can be driven from standard Series 54/74 TTL with no external
pull-up resistors.

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TMS 4033 JL, NL; TMS 4034 JL, NL; TMS 4035 JL, NL
1024-WORD BY 1-BIT STATIC RANDOM-ACCESS MEMORIES
operation (continued)
Chip Enable (CE)
The CE input is used to enable the memory chip for a reading or writing operation. In a single·chip system, this pin can
be hardwired to ground so that the chip is continuously enabled. For the read cycle, chip·enable low must extend past
the address to ensure valid data for that address. Once the chip·enable goes high, the output buffer will immediately
return to the high·impedance state. For the write cycle, chip·enable low must occur before the read/write input goes to
the write state ensuring no ambiguity in the chip enabled for a particular write cycle. This input can be driven from
Series 54/74 TTL with no external pull·up resistors.
ReadlWrite (R;W)
In the write mode prior to an address change, R/W must be in the read state (high level) and must remain in that state for
a minimum period to eliminate the possibility of data being written into an unwanted location. The read/write input is
TTL compatible without external pull·up resistors.
Data In (01)

II

The 01 input accepts the input data during the write mode. During a write cycle, data must be valid for a minimum
time period before the read/write input is brought to the read state ensuring that proper data will enter the location
selected. To eliminate any data ambiguity, data must be held valid past the end of the write pulse.
Data Out (DO)
Data out is a three·state terminal controlled by the chip·enable input, which supplies output data during a read cycle. A
high level on chip enable places the data-out terminal in the high-impedance state.

functional block diagram

~__~A~D__~~--------,

AD

AD
A1

A1

A2
A2

A3

FUNCTION TABLE

A1

A2

1 OF 32
ROW
DECODE

32 ROWS BY
32 COLUMNS
STATIC MEMORY
STORAGE ELEMENTS

A3
A4

A4

A4

CE

RIW

I/O

L

L

WRITE

L

H

READ

H

X

HIGH Z

H

=

HIGH LEVEL

L

= LOW

LEVEL

vee
GROUND

RiW
DATA IN

DATA OUT

A5

A6

A7

AS

A9
5~

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TMS 4033 JL, NL; TMS 4034. JL, NL; TMS 4035 JL, NL
1024-WORD BY l-BIT STATIC RANDOM-ACCESS MEMORIES
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)*
Supply voltage, V cc (see Note 1)
Input voltage (any input) (see Note 1)
Continuous power dissipation.
Operating free-air temperature range
Storage temperature range.

-0.5 to 7 V
-0.5 to 7 V
.1W
O°C to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to the ground terminal.
'COMMENT: Stresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.

recommended operating conditions
MIN
4.75
2.2
-0.3
0

Supply voltage, Vee
High-level input voltage, V I H
Low-level input voltage, V I L (see Note 2)
Operating free-air temperature, T A

NOM
5

MAX
5.25
Vee
0.65
70

UNIT
V
V
V
°e

II

NOTE 2: The algebraic convention where the most negative limit is designated as minimum is used in this data sheet for logic voltage levels only.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
VOH
VOL
II
IOZH
IOZL

PARAMETER
High-level output voltage
Low-level output voltage
Input current
Off-state output current,
high-level voltage applied
Off-state output current,
low-level voltage applied

lee

Supply current from Vee

e·

Input capacitance
Output capacitance

eo

t All typical values are at VCC

=5

V, T A

=

TEST CONDITIONS
Vee =4.75 V
IOH = -100pA.
IOL = 1.9 rnA.
Vee = 5.25 V
V I = 0 to 5.25 V

CE at 2.2

V,

MIN
2.2

Typt

0.45
±10

eE at 2.2 V,

Vo = 0.45 V

Vee - 5.25 V,
All inputs at 5.25 V
TA = 25°e,
TA = 25°e,

Data out open,
f = 1 MHz
f = 1 MHz

UNIT
V
V
pA

10

pA

-10

-100

pA

45

70

rnA

3
7

5
10

pF
pF

VO=4 V

-

MAX

25°C.

conditions for testing timing requirements
Input high levels
Input low levels
Input rise and fall times
Output load
All timing requirements

2.2V
0.65 V
20 ns
1 Series 74 TTL load, CL = 100 pF
. 50% point of waveform

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TMS 4033 JL, NL; TMS 4034 JL, NL; TMS 4035 JL, NL
1024-WORD BY 1-BIT STATIC RANDOM-ACCESS MEMORIES
= O°C to 70°C

read cycle timing requirements over recommended supply voltage range, T A
(unless otherwise noted)
PARAMETER

MIN

Read cycle time

ta(ad)

Access time from address

ta(CE)

Access time from chip enable

tDV(ad)

Previous output data valid from address

tpHZ or tPLZ

Output disable time from chip enable

=5

TMS4035

TMS4034
MIN

Typt

MAX

450

650

MIN

450

300

500

1000

ns

500

ns

ns

200

ns

50

50

0

MAX

300

200
50

UNIT

Typt

1000

650

450

tc(rd)

t All typical values are at Vee

TMS4033
Typt MAX

200

0

ns

200

0

V, T A = 25°e.

14

~I

tc(rd)

~~------------------A-D-D-R-E-S-S-V-A-L-I-D------------------------~~

ADDRESS

II

0'----

~

CHIP ENABLE

~~~:~~?~~'£~~~~~~------~/
__:--________14____t_a(_C_E)_-----l_~I

DATA OUT

-----~I

______________________________________________________

,t

-.l;

:

PHZ

XDATA
I
I VALlD)lI----I

-J

I

14

ta(ad)

-+I

14

--------~~~I

14-tpLZ

.1

tDV(ad)

write cycle timing requirements over recommended supply voltage range, TA = O°C to 70°C
TMS 4033

PARAMETER

MIN

TMS4034

MAX

MIN

MAX

TMS 4035
MIN

MAX

UNIT

tC(wrl

Write cycle time

450

650

1000

ns

tw(wrl

Write pulse width

250

400

750

ns

tsu (ad)

Address setup time

150

200

200

ns

tsu(CE)

Chip enable to write setup time

350

550

850

ns

tsu(da)

Data-in to write setup time

300

450

800

ns

th(ad)

Address hold time

50

50

50

ns

thIda)

Data hold time

50

50

50

ns

~

10114
___- - - - - - - - - - - - - - tc(wr)

ADDRESS

----~)(------------------------)(~----

READ/WRITE

_----.J/

14- tsu(ad)

~

~----;(
14141---- tw(wr)

~

CHIP ENABLE

.14

I

~I

th(ad)

/

f4
DATA-IN

/4
~~~7~~~~~

_______________

tsu(da)

D_A
___
TA
___V_A_L_I_D_______________

~

~:__J)+(~_____
~th(da)

PRINTED IN u.S A

52

57!

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TEXAS INSTRUMENTS RESERVES THE RIGHT TO MAKE CHANGES AT ANY TIME
IN ORDER TO IMPROVE DESIGN AND TO SUPPLY THE BEST PRODUCT POSSIBLE.

TMS 4036 Jl, Nl; TMS 4036-1 Jl, Nl; TMS 4036-2 Jl, Nl
64-WORD BY 8-BIT STATIC RANDOM-ACCESS MEMORIES

MOS
lSI

BULLETIN NO. DL-S 7512277, MAY 1975

•
o

64 x 8 Organization
Static Operation (No Clocks, No Refresh)

o

Compact 20-Pin 300-Mil Dual-in-Line Package

•

3 Performance Ranges:

TMS 4036
TMS 4036-1
TMS 4036-2

ACCESS
TIME
(MAX)
1000 ns
650 ns
450 ns

20-PIN CERAMIC AND PLASTIC
DUAL-IN-LiNE PACKAGES
(TOP VIEW)

READ OR WRITE
CYCLE
(MIN)

•

Multiplexed Common Bus I/O

o

Input Interface

1000 ns
650 ns
450 ns

1/07

20

1/06

AS

19

1/05

18

NC

17

1/04

AD

3

A1

Fully Decoded

A2

5

16

OE

GND

6

15

VCC

A4

7

14

CE

A3

8

13

RiW

12

1/03

11

1/02

TTL Compatible
Static Charge Protection
o

Output Interface
3-State
Fan-Out 1 Series 74 TTL Load

1/00

II
I

OR-Tie Capability
o

1/01

Power Dissipation ... 450 mW Maximum

•

N-Channel Silicon-Gate Technology

•

8-Bit Word Length Ideal for Microprocessor-Based Systems

10

description
This series of static random-access memories is organized as 64 words of 8 bits. Data inputs and outputs are multiplexed
on an 8-bit, bidirectional bus controlled by the combination of chip enable and output enable. Static design results in
reduced overhead costs by elimination of refresh-clocking circuitry and by simplification of the timing requirements. In
addition, all inputs and outputs are fully compatible with Series 74 TTL, including the single 5-volt power supply. The
TMS 4036 series is manufactured using TI's reliable N-channel silicon-gate technology to optimize the cost/performance
relationship. Readout is nondestructive and the output data polarity is not inverted from data-in.
The TMS 4036 is offered in compact 20-pin ceramic (JL suffix) and plastic (N L suffix) dual-in-line packages designed
for insertion in mounting-hole rows on 300-mil centers. The series is guaranteed for operation from O°C to 70°C.

operation
addresses (AO-A5)
The 6-bit address selects one of 64 8-bit words. The address-valid time determines cycle time during both the read and
write cycles. The address inputs can be driven directly from standard Series 54/74 TTL with no external pull-up
resistors required.

75

PRELIMINARY DATA SHEET:
Supplementary data may be
published at a later date.

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

OALLAS. TEXAS 75222

53

TMS 4036 JL, NL; TMS 4036-1 JL, NL; TMS 4036-2 JL. NL
64-WORD BY 8-BIT STATIC RANDOM-ACCESS MEMORIES
operation (continued)
chip enable (CE)
The CE terminal is used to enable a specific memory device. If CE is low, the device is enabled for either a read or write
cycle, depending on the state of the read/write and output-enable terminals. When CE is high, the I/O buffers are in the
high-impedance state. CE may be driven from Series 74 TTL. For a more complete understanding of CE, see the section
on output enable.
read/write (RtW)
The RIW input must be high during read and low during write operations. Prior to an address change, RiW must be in
the read state and must remain in that state for a minimum period to eliminate the possibility of data being written into
an unwanted position. The R/W input is TTL-compatible and does not require external resistors.
output enable (OE)
The output enable terminal controls the I/O buffer and determines whether the bus is in an input or output mode.
When OE is low, the I/O terminals are in the input configuration; when OE is high, the I/O terminals are in the output
configuration. The read cycle and write cycle timing diagrams show in detail the relation between CE, OE, and the
other signals (refer to the function table). This input is also compatible with Series 74 TTL circuits.

II

input/output buffer (1/00-1/07)
Each of these terminals interface directly with the external data bus and have the capability of being both an input and
an output buffer. These buffers are controlled by a combination of CE and OE as described in the output enable
section. Each buffer is three-state and fully TTL compatible, both as an input and an output.

functional block diagram
FUNCTION TABLE

AO
A1

64 ROWS BY

RtW

CE

OE

8 COLUMNS

L

L

H

Not recommended

A4

L

L

Write (I/O

L

H

Read

X

H

X

Device disabled (I/O

H

X

L

Device disabled (I/O

STATIC MEMORY

AS

STORAGE ELEMENT

H

L
X
Z

CE

= High
= Low
= Irrelevant
= High Impedance

(I)

«-IwO:Z

0:

o:~O

1/02
1/03

::::l

1/04
1/05

LL
LL

u

1/01

w

III

g

1/06
1/07

OE

54

(Off)

1/00

...J

...... wO

01-0:

R/W

= Z)

L
H

A2

A3

OPERATION

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TO I/O BUS

= Z)
= Z)

TMS 4036 Jl, Nl; TMS 4036-1 Jl, Nl; TMS 4036-2 Jl, Nl
64-WORD BY 8-BIT STATIC RANDOM-ACCESS MEMORIES
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)*
Supply voltage, Vee (see Notes 1 and 2)
Input voltage (any input) (see Notes 1 and 2)
Operating free-air temperature range
Storage temperature range

-0.5 to 7 V
-0.5 to 7 V
oOe to 70 0 e
0

-65°e to 150 e

NOTES:
1. Voltage values are with respect to the ground terminal.
2. For all combinations of inputs, the 1/0 lines may be shorted to Vss or VCC for a period not to exceed five milliseconds.
'Stresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions"
section of this specification is not implied. Exposure to absolute·maximum-rated conditions for extended periods may affect device reliabilitY.

recommended operating conditions
TMS 4036-1

TMS4036

PARAMETER
Supply voltage, VCC

MIN

NOM

MAX

4.75

5

5.25

Supply voltage, VSS

MIN NOM
4.75
5

2.2

MIN

5.25

4.75

NOM
5

0

0

High-level input voltage, VIH

TMS 4036-2

MAX

VCC
0.8

2.2
-0.3

MAX
5.25

2.2
-0.3

V
V

0
VCC
0.8

UNIT

VCC
0.8

V

-0.3

Read cycle time, tc(rd)

1000

650

450

ns

Write cycle time, tc(wrl

1000

650

450

ns

Write pulse width, tw(wrl

500

300

200

ns

Address setup time, tsu (ad)

450

300

200

ns

Chip-enable setup time, tsu(CE)

700

500

400

ns

Data setup time, tsu(da)

600

400

300

ns

Address hold time, th(ad)

50

50

50

ns

Data hold time, thIda)
Operating free-air temperature, T A

50

50

50

70

0

0

70

0

70

II

V

low-level input voltage, VI l (see Note 3)

ns
°c

NOTE 3: The albegraic convention where the most negative limit is designated as minimum is used in this data sheet for logic voltage levels only.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage

10H = -100 /lA,

VCC = 4.75 V

VOL

low-level output voltage

10l = 1.9 mA,

VCC = 4.75 V

High-level input current into address,
IIH

R/IN. CE, or OE

VI = 5.25 V
Vo = 5.25 V,

OEatOV,

CE at 5.25 V
10ZH

Off-state output current, high-level voltage

Vo = 5.25 V,

applied at I/O terminal

CEat 2.2 V

Off-state output current, low-level voltage
10Zl

applied at I/O terminal

OE at 5.25 V,

Vo = 5.25 V,
CE at 0 V

OE at 0.8 V,

Vo = 0 V,

OE at 5.25 V,

-

CE at 2.2 V
Vo = 0 V,

-

OE at 0.8 V,

CE at 0 V

MIN

MAX

2.4

UNIT
V

0.4

V

10

!J.A

10
10

!J.A

10
-100
!J.A
-100

ICC
Ci

Supply current from VCC

85

rnA

I nput capacitance

f=1 MHz,

TA=25°C

10

Ci/o

I/O terminal capacitance

f= 1 MHz,

TA =25°C

20

pF
pF

575

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

55

TMS 4036 JL, NL; TMS 4036-1 JL, NL; TMS 4036-2 JL, NL
64-WORD BY 8-BIT STATIC RANDOM-ACCESS MEMORIES
switching characteristics over recommended supply voltage ranges, T A = 0° C to 70° C
TMS4036

PARAMETER

TMS 4036-1

TMS4036-2

UNIT

MIN Typt MAX

MIN Typt MAX

MIN Typt MAX

1000

650

450

ns
ns

ta(ad)

Access time from address

ta(CE)

Access time from chip enable

200

190

180

ta(OE)

Access time from output enable

200

190

180

ns

tpxz

Output disable time from chip enable

0

60

200

0

60

200

0

60

200

ns

tpxz

Output disable time from output enable (see Note 4)

0

60

200

0

60

200

0

60

200

ns

NOTE 4: This parameter defines the delay for the 1/0 bus to enter the input mode_
t All typical values are at T A ~ 25° C.

read cycle timing

I" - - - ----------------.1_,
--y~----------- tc(rd)

=>r<

ADDRESS, AO-A5

I

II

READ/WRITE, R/W

..

----.J



<><

ns and all timing points are 50% points.

PklNTfD IN USA

60

575

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

OALLAS, TEXAS 75222

TEXAS INSTRUMENTS RESERVES THE RIGHT TO MAKE CHANGES AT ANY TIME
IN ORDER TO IMPROVE DESIGN AND TO SUPPLY THE BEST PRODUCT POSSIBLE.

TMS 4042 JL. NL; TMS 4042-1 JL. NL; TMS 4042-2 JL, NL
256-WORD BY 4-BIT STATIC RANDOM-ACCESS MEMORIES

MOS
LSI

BULLETIN

•
•
•
•
•

256 x 4 Organization
Common I/O
18-Pin Package
Static Operation (No Clocks, No Refresh)
3 Performance Ranges:
ACCESS
TIME
(MAX)
TMS 4042
TMS 4042-1
TMS 4042-2

•

•

1000 ns
650 ns
450 ns

NO_

DL-5

7512269,

MAY

1975

18-PIN CERAMIC AND PLASTIC
DUAL-IN-LiNE PACKAGES
(TOP VIEW)

READ OR WRITE
CYCLE
(MIN)
1000 ns
650 ns
450 ns

Input Interface
Fully Decoded
TT L-Compati bl e
Static Charge Protection

A3

18 Vce

A2

17 A4

A1

3

16 R/W

AO

4

15 CE1

A5

5

14 1/04

A6

6

13 1/03

A7

7

12 1/02

GND

8

11 1/01

OE

9

10 CE2

•
•

Output Interface
Two Chip-Enable Inputs for OR-Tie Capability
Fan-out to 1 Series 74 TTL Load
3-State Outputs and Output Enable Control
for Common I/O Data Bus Systems
Power Dissipation ... 175 mW Typical
Organized for Microprocessor-Based Systems

•

I nterchangeable with Intel 2111, 2111-2, and 2111-1 , Respectively

II
I

description
This series of static random-access memories is organized as 256 words of 4 bits. Static design results in reduced
overhead costs by elimination of refresh-clocking circuitry and by simplification of timing requirements. The use of
common input/output terminals, controlled by the chip enable and output enable terminals, allows the use of an 18-pin
package and saves board space in comparison to the TMS 4039. The common input/outputs are fully compatible with
Series 74 TTL. The device requires a single 5-volt power supply. The TMS 4042 series is manufactured using TI's
reliable N-channel enhancement-type silicon-gate technology to optimize the cost/performance relationship. Readout is
nondestructive and output data is not inverted from data in.
The TMS 4042 series is offered in 18-pin dual-in-line ceramic (JL suffix) and plastic (NL suffix) packages designed for
insertion in mounting-hole rows on 300-mil centers. The series is characterized for operation from O°C to 70°C.

operation
addresses (AO-A7)
The eight address inputs select one of 256 4-bit words. The address inputs can be driven directly from standard Series
54/74 TTL with no external pull-up resistors.
chip enable 1 and chip enable 2 (CE 1 and CE2)
To enable the device, CE1 and CE2 must be low. The two chip-enable terminals can be driven from a common source
or either terminal can be hard wired low. When the memory is disabled, data cannot be entered and the outputs are in
the high-impedance state.

;75

PRELIMINARY DATA SHEET:
Supplementary data may be
published at a later date.

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

61

TMS 4042 JL, NL; TMS 4042-1 JL, NL; TMS 4042-2 JL, NL
256-WORD BY 4-BIT STATIC RANDOM-ACCESS MEMORIES
operation (continued)
read/write (R/W)
The R/TN input must be high during read and low during write operations. Prior to an address change, R7W must be in
the read state and must remain in that state for a minimum period to eliminate the possibility of data being written into
an unwanted position. The RM input is TTL·compatible and does not require external resistors.
output enable (OE)
The output enable must be low to read for when it is high the outputs are in the high·impedance state.

input/output (1/01-1/04)
The common input/output terminals are used for both read and write operations. During a write cycle, data must be set
up a minimum time before Riw goes to the read state (high) to ensure that correct data will enter the addressed
memory cell. Also, input data must be held valid a minimum time after the rise of RiW.

a

The output buffers are three-state and are controlled by OE, CE 1, and CE2. The input buffers are controlled by RIW,
CE1, and CE2. To read data, CE1, CE2, and OE must be low. If anyone of these three inputs goes to the high level,
the output terminals are forced to the high-impedance state. The common I/O terminals can be driven directly by
Series 74 TTL and the buffers can drive Series 74 TTL circuits without external resistors.

functional block diagram
FUNCTION TABLE

AD - - - - f
A1 - - - - - f
A2 - - - - - f

ROW
SELECT

A3 - - - - - f

MEMORY ARRAY
32 ROWS
32 COLUMNS

A4 - - - - - f

R/w

CEl

CE2

OE

OPERATION

L
L
H
X
X
H

L
L
L
H
X
X

L
L
L
X
H
X

L
H
L
X
X
H

Not recommended
Write (I/O = Z)
Read
Device Disabled (I/O = Z)
Device Disabled (I/O = Z)
Device Disabled (I/O = Z)

H = High

L= Low
Irrelevant

x=

Z = High Impedance

Riw

----f

COLUMN I/O CIRCUITS
COLUMN SELECT

1/01
INPUT
1/02

---'+-f

DATA
CONTROL

1/03 --4t-+-+-I
AS

AS

A7

1/04 -*-l-t-oH

CE1------------O--

-+I

DATA VALID

write cycle timing

I..

~I

tc(wr)

.1:\
------------------~~~II'-______________________________________~~II

ADDRESS, AO-A7

/.\

'-_______

ADDRESS VALID

READ/WRITE, R/W

CHIP ENABLE,

CE

I

I..

INPUT/OUTPUT,I/01-1/04

j+- tsuldal-J

~Ltpxz

\/V\/VVVV\l\lW
~

NOT E: For measuring timing requirements and characteristics, VI H

= 2.2

V, V I L

= 0.65

I+--- thldal--.j
DATA VALID

V, tr

= tf = 20

~
.~

ns and all timing points are 50% points.

PRINTED IN U.S A

68

57E

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TEXAS INSTRUMENTS RESERVES THE RIGHT TO MAKE CHANGES AT ANY TIME
IN ORDER TO IMPROVE DESIGN AND TO SUPPLY THE BEST PRODUCT POSSIBLE.

MOS
LSI

TMS 4050 Jl, Nl; TMS 4050-1 Jl, Nl; TMS 4050-2 Jl, Nl
4096-81T DYNAMIC RANDOM-ACCESS MEMORIES
BULLETIN NO. DL-S 7512242, FEBRUARY 1975-REVISED MAY 1975

•
•
•
•

4096 x 1 Organization
18-Pin 300-Mil Package Configuration
Multiplexed Data Input/Output
3 Performance Ranges:
READ,

TMS 4050
TMS 4050-1
TMS 4050-2

•
•
•
•

•
•

ACCESS
TIME
(MAX)

READ OR
WRITE
CYCLE
(MIN)

MODIFY
WRITE
CYCLE
(MIN)

300 ns
250 ns
200 ns

470 ns
430 ns
400 ns

730 ns
660 ns
600 ns

18-PIN CERAMIC AND PLASTIC
DUAL-IN-L1NE PACKAGES
(Top VIEW)

Full TTL Compatibility on All Inputs
(No Pull-up Resistors Needed)
Registers for Addresses Provided on Chip
Open-Drain Output Buffer
Single Low-Capacitance Clock
Low-Power Dissipation
- 420 mW Operating (Typical)
- 0.1 mW Standby (Typical)
N-Channel Silicon-Gate Technology

vBB

18

VSS

I/O

17

A11

AO

16

A10

A1

15

A9

A2

14

A8

R/W

13

A7

CE

12

A6

A3

11

A5

A4

10

V DD

II

description
The TMS 4050 series is composed of high-speed dynamic 4096-bit MOS random-access memories, organized as 4096
one-bit words. N-channel silicon-gate technology is employed to optimize the speed/power/density trade-off. Three
performance options are offered: 300 ns access for the TMS 4050, 250 ns access for the TMS 4050-1, and 200 ns for
TMS 4050-2. These options allow the system designer to more closely match the memory performance to the capability
of the arithmetic processor.
All inputs except the chip enable are fully TTL-compatible and require no pull-up resistors. The input buffers allow a
minimum 200 mV noise margin when driven by a series 74 TTL device. The TTL-compatible open-drain buffer is
guaranteed to drive 1 series 74 TTL gate. The low capacitance of the address and control inputs precludes the need for
specialized drivers. The TMS 4050 series uses only one clock (chip enable) to simplify system design. The lowcapacitance chip-enable input requires a positive voltage swing (12 volts), which can be driven by a variety of widely
available drivers. The data input and output are multiplexed to facilitate compatibility with a common bus system.
A 121ine address is available, which minimizes external control logic and optimizes system performance.
The typical power dissipation of these RAM's is 420 mW active and 0.1 mW standby. To retain data only 6 mW average
power is required, which includes the power consumed to refresh the contents of the memory.
The TMS 4050 series is offered in both 18-pin ceramic (JL suffix) and plastic (NL suffix) dual-in-line packages. The
o
series is guaranteed for operation from O°C to 70 e. Packages are designed for insertion in mounting hole rows on
300-mil centers.

operation
chip enable (CE)
A single external clock input is required. All read, write, and read, modify write operations take place when the chip
enable input is high. When the chip enable is low, the memory is in the low-power standby mode and is not selected. No
read/write operations can take place during the standby mode because the chip is deselected and is automatically
precharging.

575

PRELIMINARY DATA SHEET:
Supplementary data may be
published at a later date.

TEXASINCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

69

TMS 4050 JL, NL; TMS 4050-1 JL, NL; TMS 4050-2 JL, NL
4096-81T DYNAMIC RANDOM-ACCESS MEMORIES
operation (continued)
mode select (RjijiJ)

Riw

The read or write mode is selected through the read/write (R/W) input. A logic high on the
input selects the read
mode and a logic low selects the write mode. The read/write terminal can be driven from standard TTL circuits without
a pull-up resistor. The data input is disabled when the read mode is selected and the data output is disabled when the
write mode is selected.
address (AO-A 11)
All addresses must be stable on or before the rising edge of the chip-enable pulse. All address inputs can be driven from
standard TTL circuits without pull-up resistors. Address registers are provided on chip to reduce overhead and simplify
system design.
data input/output (I/O)

Riw

Data input and output are multiplexed on a common input/output terminal, which is controlled by the
input. Data
is written during a write or read, modify write cycle while the chip enable is high. The I/O terminal requires connection
to an external pull-up resistor since the output buffer has an open-drain configuration. The open-drain output buffer
provides direct TTL sink compatibility with a fan-out of one Series 74 TTL gate. A low logic level results from conduction in the open-drain output buffer while a high level occurs with the buffer in its high-impedance state. Data written
into the memory is read out in its true form.

II

refresh
Refresh of the cell matrix is accomplished by performing a memory cycle at each of the 64 row addresses (AO through
A5) every 2 milliseconds or less. Addressing any row refreshes all 64 bits in that row. The column addresses (A6
through A 11) can be indeterminate during refresh.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VDD (see Note 1)
Supply voltage, VSS (see Note 1)
All input voltages (see Note 1)
Chip-enable voltage (see Note 1) .
Output voltage (operating, with respect to VSS)
Operating free-air temperature range
Storage temperature range.
NOTE:

1.

-0.3
-0.3
-0.3
-0.3

to 20 V
to 20 V
to 20 V
to 20 V
. -2 to 7 V
O°C to 70°C
-55°C to 150°C

Under absolute maximum ratings, voltage values are with respect to the most-negative supply voltage, VSS (substrate), unless
otherwise noted. Throughout the remainder of this data sheet, voltage values are with respect to VSS.

functional block diagram
_VDD
_VSS
A6

-Vss

V+

R/W

~

A11

r----------------l

AD

I

~

Ul

1-16

A5

INTERNAL
DATA IN - - - - - - i

II ~~ i=~
I f-Z
I~
I

W
-I
CD
<{

R/W
CE

:t:4;::=====~

1

6 INVERTED
U DATA OUT

I

L_________________ ..:'~...J

Z

w

a.
I

U

I/O LOGIC

5

70

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TMS 4050 JL, NL; TMS 4050-1 JL, NL; TMS 4050-2 JL, NL
4096-81T DYNAMIC RANDOM-ACCESS MEMORIES
recommended operating conditions
PARAMETER
Supply voltage, VDD

MIN

NOM

MAX

UNIT

11.4

12

12.6

V

Supply voltage, VSS

V

0
-5

-4.5

Supply voltage, VSS
High-level input voltage, VIH (all inputs except chip enable)
High-level chip enable input voltage, VIH(CE)

-5.5

V

2.2

5.5

V

VDD -0.6

VDD+1

V

-0.6

0.6

V

-1

0.6

V

2

ms

70

°c

Low-level input voltage, VI L (all inputs except chip enable) (see Note 2)
Low-level chip enable input voltage, VIL(CE) (see Note 2)
Refresh time, trefresh
Operating free-air temperature, T A

0

NOTE 2: The algebraic convention where the most negative limit is designated as minimum is used in this data sheet for logic voltage levels only.

electrical characteristics over full ranges of recommended operating conditions, T A
(unless otherwise noted)
TEST CONDITIONS

PARAMETER
VOH

High-level output voltage

VOL

Low-level output voltage

10L

Low-level output current

II(CE)

VOL = 0.4 V

VI=-1t013.2V

Chip enable input current

IDD

Supply current from VDD

VIH(CE) = 13.2 V

Supply current from VDD, standby

during read or write cycle

Average supply current from VDD
IDD(av)

ISS

10

J.1.A

TMS4050-2

35

70

10

200

TMS 4050

32

TMS4050-1

TMS 4050-1

35

TMS 4050-2

38

timing

TMS 4050

32

TMS 4050-1

35

TMS 4050-2

38

VSS = -5.5 V,

Supply current from VSS

J.1.A

60

Minimum cycle

during read, modify write cycle

10

35

VIL(CE) = 0.6 V

Average supply current from VDD
IDD(av)

V
rnA

5

VI = -0.6 to 5.5 V

I/O except chip enable)

II

UNIT
V

0.4

TMS4050
IDD

MAX

2.4
VSS

Load = 1 Series 74 TTL gate

CL = 50 pF,

Typt

CL=50pF,

ta = guaranteed maximum access time,

Input current (all inputs including
II

MIN

ta = guaranteed maximum access time,
RL = 2.2 kn to 5.5 V,

= oDe to 70°C

VDD = 12.6 V,

5

VSS = 0 V

rnA

J.1.A
rnA

rnA

100

J.1.A

t All typical values are at T A = 25°C.

capacitance at V DD = 12 V, VSS = 0 V, V BB = -5 V, VI(CE)
T A = 0 C to 70 C (unless otherwise noted)
0

= 0 V, VI = 0 V, f = 1 MHz,

0

Typt

MAX

5

7

VI(CE) = 12 V

24

28

VI(CE) = 0 V

29

33

TEST CONDITIONS

PARAMETER
Cj(ad)

Input capacitance address inputs

Ci(CE)

Input capacitance clock input

MIN

UNIT
pF
pF

Ci(R/W)

Input capacitance read/write input

5

7

pF

CO/Oj

I/O terminal capacitance

7

9

pF

t All typical values are at T A = 25° C.

575

TEXAS INSTRUMENTS
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•

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71

TMS 4050 JL, NL; TMS 4050-1 JL, NL; TMS 4050-2 Jl, NL
4096-81T DYNAMIC RANDOM-ACCESS MEMORIES
read cycle timing requirements over recommended supply voltage range, T A = O°C to 70°C
TMS4050

PARAMETER

MIN

MAX

TMS 4050-1

TMS4050-2

MIN

MIN

MAX

MAX

400

UNIT

tc(rd)

Read cycle time

470

tw(CEH)

Pulse width, chip enable high

300

tw(CEL)

Pulse width, chip enable low

130

triCE)

Chip-enable rise time

40

40

40

ns

tf(CE)

Chip-enable fall time

40

40

40

ns

tsu(ad)

Address setup time

ot

ot

ot

ns

tsu(rd)

Read setup time

at

ot

ot

ns

th(ad)

Address hold time

150t

150t

150t

ns

thIrd)

Read hold time

40-l-

40-l-

40-l-

ns

430
4000

260

4000

230

ns
4000

130

130

ns
ns

t -l- The arrow indicates the edge of the ch ip-enable pulse used for reference: t for the rising edge, -l- for the falling edge.

a

read cycle switching characteristics over recommended supply voltage range, T A =\O°C to 70°C
TMS4050

PARAMETER

MIN

MAX

TMS 4050-1

TMS4050-2

MIN

MIN

MAX

MAX

UNIT

ta(CE)

Access time from chip enable *

280

230

180

ns

ta(ad)

Access time from addresses t

300

250

200

ns

tpLH

Propagation delay time, low-to-high level output from
chip enable*

40

40

40

ns

• Test conditions: CL = 50 P F, R L = 2.2 kfl to 5.5 V, Load = 1 Series 74 TTL gate.
tTestconditions: CL = 50 pF, RL = 2.2 kfl to 5.5 V, Load = 1 Series 74 TTL gate, trICE) = 20 ns.

write cycle timing requirements over recommended supply voltage range, T A = 0° C to 70° C
TMS4050

PARAMETER

MIN

Riw

TMS 4050-1

TMS4050-2

MIN

MIN

MAX

MAX

UNIT

tc(wr)

Write cycle time

470

tw(CEH)

Pulse width, chip enable high

300

tw(CEL)

Pulse width, chip enable low

130

130

130

tw(wr)

Write pulse width

200

190

180

triCE)

Chip-enable rise time

40

40

40

ns

tf(CE)

Chip-enable fall time

40

40

40

ns

tsu(ad)

Address setup time

ot

ot

ot

ns

tsu(da-wr)

Data-to-write setup time*

0

0

0

ns

tsu(wr)
td(CEH-wr)

Write-pulse setup time
Chip-enable-high-to-write delay timet

th(ad)

Address hold time

thIda)

Data hold time

430
4000

24O-l-

260

400
4000

220-l40t

t-l- The arrow indicates the edge of the chip-enable pulse used for reference:
'If

MAX

230

ns
4000

ns
ns

ns

210-l40t

ns

40t

ns

150t

150t

150t

ns

40-l-

40-l-

40-l-

ns

t for the rising edge, -l- for the falling edge.

is low before CE goes high, then I/O (data in) must be valid when CE goes high.

tThe write pulse must go low at least tsu(wr) minimum before CE_goes low_ If R;W remains high more than td(CEH-wr) maximum (40 ns)
after CE goes high, the data-in driver must be disabled until R/W goes low since additional power to overcome the output buffer may be
required when writing in a high with some of the faster devices (see comments on Region 1 under read, modify write timing diagram).

57!

72

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TMS 4050 Jl, Nl; TMS 4050-1 Jl, Nl; TMS 4050-2 Jl, Nl
4096-81T DYNAMIC RANDOM-ACCESS MEMORIES

read or refresh cycle timing
tc(rd)
tw(CEH)
CHIP ENABLE, CE

-------I~

tw(CEL)

--tI~,\I~- tf(CE)

-~I/"""""- triCE)

------;-14---- th(ad)
tsu(ad)
ADDRESS, AO-A11

tsu(rd)

READ/WRITE, RtW

..

, . . - - - - ta(CE)

DATA INPUT/OUTPUT, I/O

NOTE:

ta(ad)

DATA OUT VALID

For the chip-enable input, high and low timing points are 3.0 V (high) and 1.0 V (low). Other input timing points are 0.6 V (low) and
2.2 V (high). Output timing points are 0.4 V (low) and 2.4 V (high).

I

For minimum cycle, tr(CE) and tf(CE) are equal to 20 ns.

write cycle timing
tc(wr) - - - - - - - - - - - - . - t
I C - - - - - - tw(CEH) ------~

CHIP ENABLE, CE

ADDR ESS, AO-A 11

fo4----I*- td(CEH-wr) *
I C - - - - - lsu(wr)

, . . - - - tw(wr)
READ/WRITE, R/Vi
lsu(da-wr)

NOTE: For the chip-enable input, high and low timing points are 3.0 V (high) and 1.0 V (low). Other timing points are 0.6 V (low) and 2.2 V
(high). Output timing points are 0.4 V (low) and 2.4 V (high).
'The w~e pulse must go low at least tsu(wr) minimum before CE_goes high. If R/iN remains high more than td(CEL-wr) maximum (60 ns)
after CE goes low, the data-in driver must be -::Iisabled until R/W goes low since additional power to overcome the output buffer may be
required when writing in a high with some of the faster devices. During td(CEH-wr), R/W is permitted to change from high to low only.

75

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

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73

TMS 4050 JL, NL; TMS 4050-1 JL, NL; TMS 4050-2 JL, NL
4096-81T DYNAMIC RANDOM-ACCESS MEMORIES
read, modify write cycle timing requirements over recommended supply voltage range, TA =0° e to 70° e

II

TMS 4050-1

TMS4050-2

MAX

MIN

MAX

MIN

4000

'490

4000

430

TMS4050

PARAMETER

MIN

tc(RMW)

Read, modify write cycle timet

730

tw(CEH)

Pulse width, chip enable high t

560

660

MAX

ns

600

tw(CEL)

Pulse width, chip enable low

130

130

130

tw(wr)

Write pulse width

200

190

180

triCE)

Chip-enable rise time

40

40

UNIT

4000

ns
ns
ns

40

ns

tf(CE)

Chip-enable fall time

40

40

40

ns

td(wr-daL)

Write to data-in-Iow delay time

20

20

20

ns

tsu(ad)

Address setup time

tsu(daH)

ns

ot

ot

ot

Data-in-high setup time

240,),

220,),

210,),

ns

tsu(rd)

Read-pulse setup time
Write-pulse setup time

ot
220,),

ot
210,),

ns

tsu(wr)

ot
240,),

th(ad)

Address hold time

150t

150t

150t

ns

thIrd)

Read hold time

300t

250t

200t

ns

thIda)

Data hold time

40,),

40,),

40,),

ns

t,), The arrow indicates the edge of the chip-enable pulse for reference: t
tTest conditions: tf(rd)

= 20

ns

for the rising edge;,), for the falling edge_

ns_

read, modify write cycle switching characteristics over recommended supply voltage range, T A =ooe to 70°C
TMS4050

PARAMETER

MIN

MAX

TMS 4050-1
MIN

MAX

TMS4050-2
MIN

MAX

UNIT

ta(CE)

Access time from chip enable *

280

230

180

ns

ta(ad)

Access Time from addresses t

300

250

200

ns

'Test conditions: CL
tTest conditions: CL

= 50 pF,
= 50 pF,

RL
RL

= 2.2 kn,
= 2.2 kn,

Load
Load

= 1 Series 74 TTL
= 1 Series 74 TTL

gate.
gate. trICE)

= 20

ns.

read, modify write cycle timing

CHIP ENABLE. CE

ADDRESS. AD-Al1

READIWRITE. RNi

DATA INPUTI
OUTPUT. 110
REGION 1

REGION 1 -

REGION 2

In region 1, data-out is valid until the 1/0
terminal is forced high or low by the data-in
driver. A transition from low to high is
persmissible but additional power to overcome
the output buffer will be required. A transition
from high to low is permitted without power
penalty.

REGION 2 -In region 2 a single transition is permitted.
It is NOT a true "Don't Care" region.
If a low is to be written it must be valid by
the end of region 2.

NOTE: For the chip enable input high and low timing points are 90% and 10% of VIH(CE)' Other input timing points are 0.6 V (low) and
2.2 V (high). Output timing points are 0.4 V (low) and 2.4 V (high).
For minimum cycle, trICE) and tf(CE) are equal to 20 ns.

74

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•

DALLAS. TEXAS 75222

TMS 4050 Jl, NL; TMS 4050-1 JL, NL; TMS 4050-2 JL, NL
4096-81T DYNAMIC RANDOM-ACCESS MEMORIES
timing diagram conventions
MEANING
TIMING DIAGRAM
SYMBOL

INPUT
FORCING FUNCTIONS

\\\\\\
////II

OUTPUT
RESPONSE FUNCTIONS

Must be steady high or low

Will be steady high or low

High-to-Iow changes
permitted

Will be changing from high
to low sometime during
designated interval

Low-to-high changes
permitted

Will be changing from low
to high sometime during
designated interval

Don't care

State unknown or changing

(Does not apply)

Center line is high-impedance
off-state

II
I

TYPICAL WAVEFORMS

VIH[
CHIP ENABLE
VIL

100

100 (rnA)

50

0

IIICE) (rnA)

_::t
II (rnA)
(All inputs
except CE)

OJ
470
TIME (ns)

0

940

575

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•

DALLAS, TEXAS 75222

75

TMS 4050 JL, NL; TMS 4050-1 JL, NL; TMS 4050-2 JL, NL
4096-81T DYNAMIC RANDOM-ACCESS MEMORIES

REFRESH TIME vs TEMPERATURE

ACCESS TIMES vs TEMPERATURE
350
300

1000

E
I
Ql
E

i=
-£5
~Ql
a:

'"c:

r----...I"-..II'

I

~"1 I. IY~'

100

I

I

E

~~

~

!-

'"'"

Ql

10

~

I

150

:c

~

MA~IMUMI REC~MME~DED

...ca

50
0

o

10
20
30
40
50
T A - Free-Air Temperature -

60

70

°c

TYPIF TiS

4051=

rI 40
S

TYP1ICAL

41~

TYPICAL MS

0-2-

1

VDD = 12 V
VSS = -5 V
VIH(CE) = 12 VCl = 50 pF

2

1

~~

MAX

.!:!. 100

1

II

~050-11

~1050-2 MAX
i""'"""""

U
U

«

TMS

1

i= 200

"

-£5

250

Ql

IMSh050 JAX

~

I

o

10
20
30
40
50
T A - Free-Air Temperature -

60

P~INTED

76

70

°c

IN

u.s

A

57

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TEXAS INSTRUMENTS RESERVES THE RIGHT TO MAKE CHANGES AT ANY TIME
IN ORDER TO IMPROVE DESIGN AND TO SUPPLY THE BEST PRODUCT POSSIBLE.

MOS
LSI

TMS 4051 JL, NL; TMS 4051-1 JL, NL
4096-81T DYNAMIC RANDOM-ACCESS MEMORIES
BULLETIN NO. DL·S 7512256, MAY 1975

•
•
•
•
•

•
•
•
•

•

4096 x 1 Organization
18-Pin 300-Mil Package Configuration
Single Low-Capacitance TTL-Compatible Clock
MUltiplexed Data Input/Output
2 Performance Ranges:
READ,
READ OR MODIFY
WRITE
ACCESS WRITE
CYCLE
CYCLE
TIME
(MIN)
(MIN)
(MAX)
470 ns
730 ns
TMS 4051
300ns
430 ns
660 ns
TMS 4051-1 250 ns
Full TTL Compatibility on All Inputs
(No Pull-up Resistors Needed Except with CE)
Registers for Addresses Provided on Chip
Open-Drain Output Buffer
Low-Power Dissipation
- 460 mW Operating (Typical)
- 60 mW Standby (Typical)
N-Channel Silicon-Gate Technology

18-PIN CERAMIC AND PLASTIC
DUAL-IN-LiNE PACKAGES
(Top VIEW)

Vas

18

VSS

I/O

17

All

AO

16

A10

Al

15

A9

A2

14

A8

R/W

13

A7

CE

12

A6
I

A3

11

A5

A4

10

V DD

II

description
The TMS 4051 series is composed of high-speed dynamic 4096-bit MOS random-access memories, organized as 4096
one-bit words. N-channel silicon-gate technology is employed to optimize the speed/power/density trade-off_ Two
performance options are offered: 300 ns access for the TMS 4051 and 250 ns access for the TMS 4051-1_ These options
allow the system designer to more closely match the memory performance to the capability of the arithmetic
processor_
The address, data input/output, and read/write inputs can be driven directly from Series 74 TTL circuits. A 200-mV
noise margin is guaranteed in this configuration, which eliminates the need for specialized drivers. The chip-enable input
is TTL-compatible and can interface with a Series 74 TTL circuit as long as a pull-up resistor to VCC is employed in
order to provide a high-level input voltage of 3 V minimum. The data input and output are multiplexed to facilitate
compatibility with a common bus system. A 12-line address is available, which minimizes external control logic and
optimizes system performance_

The typical power dissipation of these RAM's is 460 mW active and 60 mW standby_ To retain data only 70 mW average
power is required, which includes the power consumed to refresh the contents of the memory.
The TMS 4051 series is offered in both 18-pin ceramic (JL suffix) and plastic (NL suffix) dual-in-line packages_ The
series is guaranteed for operation from O°C to 70°C. Packages are designed for insertion in mounting-hole rows on
300-mil centers.

operation
chip enable (CE)
A single external clock input is required. All read, write, and read, modify write operations take place when the chip
enable input is low_ When the chip enable is h'igh, the memory is in the low-power standby mode and is not selected_ No
read/write operations can take place during the standby mode because the chip is deselected and is automatically
precharging. The CE input can be driven by a standard TTL circuit with a pull-up resistor.

;75

PRELIMINARY DATA SHEET:

Supplementary data may be
published at a later date_

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TMS 4051 JL, NL; TMS 4051-1 JL, NL
4096-BIT DYNAMIC RANDOM-ACCESS MEMORIES
operation (continued)
mode select (R/W)
The read or write mode is selected through the read/write (R/W) input. A logic high on the RIW input selects the read
mode and a logic low selects the write mode. The read/write terminal can be driven from standard TTL circuits without
a pull-up resistor. The data input is disabled when the read mode is selected and the data output is disabled when the
write mode is selected.
address (AO-A 11)
All addresses must be stable on or before the falling edge of the chip-enable pulse. All address inputs can be driven from
standard TTL circuits without pull-up resistors. Address registers are provided on chip to reduce overhead and simplify
system design.
data input/output (t/O)
Data input and output are multiplexed on a common input/output terminal, which is controlled by the R/W input.
Data is written during a write or read, modify write cycle while the chip enable is low. The I/O terminal requires
connection to an external pull-up resistor since the output buffer has an open·drain configuration. The open·drain
output buffer provides direct TTL sink compatibility with a fan·out of one Series 74 TTL gate. A low logic level results
from conduction in the open·drain output buffer while a high level occurs with the buffer in its high·impedance state.
Data written into the memory is read out in its true form.

II

refresh
Refresh of the cell matrix is accomplished by performing a memory cycle at each of the 64 row addresses (AO through
A5) every 2 milliseconds or less. Addressing any row refreshes all 64 bits in that row. The column addresses (A6
through A 11) can be indeterminate during refresh.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
-0.3
-0.3
-0.3
-0.3

to 20 V
to 20 V
to 20 V
to 20 V
-2 to 7 V
D
. ODC to 70 C
D
D
-55 C to 150 C

Supply voltage, VDD (see Note 1)
Supply voltage, VSS (see Note 1)
All input voltages (see Note 1)
Chip-enable voltage (see Note 1)
Output voltage (operating, with respect to VSS)
Operating free·air temperature range
Storage temperature range . . . . . . . .

NOTE: 1. Under absolute maximum ratings, voltage values are with respect to the most-negative supply voltage, VBB (substrate), unless
otherwise noted. Throughout the remainder of this data sheet, voltage values are with respect to VSS.

functional block diagram

_VDD
_VSS
-VBB
A6
~

V+

R/W
R

A11

,----------------l

AD

I

~

CIl INTERNAL
DATA IN - - - - - - {

I..J 5
I ~ f=
I~ ~

A5

R/W

I

o

_--------.J

CE

1

II-~
I ~ 0 INVERTED
U DATA OUT

'2
«
I«

I

L_________________ -='~.J
I/O LOGIC

57

78

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TMS 4051 JL, NL; TMS 4051-1 JL, NL
4096-81T DYNAMIC RANDOM-ACCESS MEMORIES
recommended operating conditions
MIN

PARAMETER
Supply voltage, Voo

,"

11.4

MAX

NOM

12.6

12

-4.5

Supply voltage, VBB

V
V

0

Supply voltage, VSS

UNIT

-5

-5.5

V

2.2

5.5

V

5.5
0.6

V

Low-level input voltage, VIL (all inputs except chip enable) (see Note 2)

3
-0.6

Low-level chip enable input voltage, VI L(CE) (see Note 2)

-0.6

0.6

High·level input voltage, V IH (all inputs except chip enable)
High·level chip enable input voltage, VIH(CE)

Refresh time, trefresh

0

Operating free-air temperature, T A

V
V

2

ms

70

°c

NOTE 2: The algebraic convention where the most negative limit is designated as minimum is used in this data sheet for logic voltage levels
only.

electrical characteristics over full ranges of recommended operating conditions, T A = O°C to 70
(unless otherwise noted)
PARAMETER
VOH

TEST CONOITIONS
ta = guaranteed maximum access time,

High-level output voltage

RL = 2.2 kn to 5.5 V,

VOL

Low-level output voltage

10L

Low-level output current

ta = guaranteed maximum access time,

Input current (all inputs including

Typt

MAX

2.4

UNIT
V

VOL = 0.4 V

0.4

VSS

5

rnA

VI = -0.6 to 5.5 V

10

p.A

II(CE)

VI = -0.6 to 5.5 V

10

p.A

100

Supply current from VOO

VIL(CE) = 0.6 V

37

Supply current from VOO, standby

VIH(CE) = 3.5 V

5

70
8

rnA

100

I/O except chip enable)

Average supply current from VOO
IOO(av)
IOO(av)
IBB

TMS 4051

45

during read or write cycle

Minimum cycle

TMS 4051-1

47

Average supply current from VOO

timing

TMS 4051

50
54

TMS 4051-1

during read, modify write cycle
VBB = -5.5 V,

Supply current from VBB

t All typical values are at T A

=

VOO = 12.6 V,

5

VSS = 0 V

rnA
rnA
rnA

100

p.A

25°C.

capacitance at VDD = 12 V, VSS = 0 V, VBB = -5 V, Vl(eE)
TA = oOe to 70 0e (unless otherwise noted)

= 0 V, VI = 0 V, f = 1 MHz,
MIN Typt

MAX

Ci(ad)

Input capacitance address inputs

5

7

pF

Ci(CE)

Input capacitance clock input

5

7

pF

Ci(R/W)

Input capacitance read/write input

5

7

pF

Co/a)

I/O terminal capacitance

7

9

pF

PARAMETER

t All typical values are at T A

=

I

V

Chip enable input current

II

..

e

CL = 50 pF,

Load = 1 Series 74 TTL gate
CL = 50 pF,

MIN

0

UNIT

25° C.

75

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TMS 4051 JL, NL; TMS 4051-1 JL, NL
4096-BIT DYNAMIC RANDOM-ACCESS MEMORIES
read cycle timing requirements over recommended supply voltage range, T A =

oDe to 70De
TMS 4051

PARAMETER

MIN

MAX

TMS 4051-1
MIN

MAX

UNIT

tc(rd)

Read cycle time

470

430

tw(CEH)

Pulse width, chip enable high

130

130

tw(CEL)

Pulse width, chip enable low

300

triCE)

Chip-enable rise time

40

40

ns

tf(CE)

Chip-enable fall time

40

40

ns

tsu(ad)

Address setup time

O~

O~

ns

tsu(rd)

Read setup time

O!

O~

ns

th(ad)

Address hold time

lS0!

165!

ns

thIrd)

Read hold time

Sot

SOt

4000

260

ns
ns
4000

ns

t! The arrow indicates the edge of the chip-enable pulse used for reference: Hor the rising edge, Hor the falling edge.

read cycle switching characteristics over recommended supply voltage range, T A = oDe to 70De

II

PARAMETER

TMS4051
Typt MAX

TMS 4051-1
Typt MAX

UNIT

ta(CE)

Access time from chip enable;

2S0

230

ns

ta(ad)

Access time from addresses*

300

250

ns

tpLH

Propagation delay time, low-to-high level output from chip enable;

t All typical values are at T A ~ 25° C.
;Test conditions: CL ~ 50 pF, R L ~ 2.2
°Test conditions: CL ~ 50 pF, RL ~ 2.2

kn to 5.5 V, Load ~ 1 Series 74 TTL gate.
kn to 5.5 V, Load ~ 1 Series 74 TTL gate, tf(CE)

60

~

ns

60

20 ns.

write cycle timing requirements over recommended supply voltage range, TA

= oDe to 70De
TMS 4051

PARAMETER

MIN

MAX

TMS 4051-1
MIN

MAX

UNIT

tC(wrl

Write cycle ti me

470

430

tw(CEH)

Pulse width, chip enable high

130

130

tw(CEL)

Pulse width, chip enable low

300

tw(wrl

Write pulse width

200

trICE)

Chip-enable rise time

tf(CE)

Chip-enable fall time

tsu(ad)

Address setup time

O!

O!

ns

tsu(da-wrl

Data-to-write setup time*

0

0

ns

tsu(wrl

Write-pulse setup time

td(CEL-wrl

Chip-enable-Iow-to-write delay timet

th(ad)

Address hold time

thIda)

Data hold time

4000

260

ns
ns
4000

ns

40

ns

40

ns

ns

190
40
40

240t

220t

ns
60~

60~

ns

lS0~

165~

ns

sot

Sot

ns

t ~ The arrow indicates the edge of the chip-enable pulse used for reference: Hor the rising edge, Hor the falling edge.
°If R/iN is low before CE goes low, then I/O (data in) must be valid when CE goes low.
tThe write pulse must go low at least tsu(wr) minimum before CE goes high. If R/iN remains high more than td(CEL-wr) maximum (60 ns)
after CE goes low, the data-in driver must be disabled until R/iN goes low since additional power to overcome the output buffer may be
required when writing in a high with some of the faster devices (see comments on Region 1 under read, modify write timing diagram).

5~

80

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

OALLAS. TEXAS 75222

TMS 4051 JL, NL; TMS 4051-1 JL, NL
4096-BIT DYNAMIC RANDOM-ACCESS MEMORIES
read or refresh cycle timing

. .- - - - - - - - - - - - - t c ( r d ) - - - - - - - - - - - - . I
. .- - - - - - t w ( C E L l - - - - - . . . . . . . ,

CHIP ENABLE, CE
th(ad)
tsu(ad)

ADDRESS, AO-A11

tsu(rd)

READ/WRITE, RiW

DATA INPUT/OUTPUT, I/O

ta(ad)

II

DATA OUT VALID

NOTE: For the chip-enable input, high and low timing points are 3.0 V (high) and 1.0 V (low). Other input timing points are 0.6 V (low) and
2.2 V (high). Output timing points are 0.4 V (low) and 2.4 V (high).
For minimum cycle, trICE) and tf(CE) are equal to 20 ns.

write cycle timing
~------------------------tc(wr)I------------------------~~

~----------tw(CEL)I------~

CHIP ENABLE, CE

ADDRESS, AO-A"

READ/WRITE, R/Iii
tsu(da-wr)

NOTE: For the chip-enable input, high and low timing points are 3.0 V (h igh) and 1.0 V (low). Other timing points are 0.6 V (low) and 2.2 V
(high). Output timing points are 0.4 V (low) and 2.4 V ~gh).
'The w~te pulse must go low at least tsu(wr) minimum before C~goes high. If R/W remains high more than td(CEL-wr) maximum (60 ns)
after CE goes low, the data-in driver must be disabled until R/W goes low since additional power to overcome the output buffer may be
required when writing in a high with SOme of the faster devices. During td(CEL-wr), R/W is permitted to change from high to low only.

75

TEXAS INSTRUMENTS
INCOHPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

81

TMS 4051 JL, NL; TMS 4051-1 JL, NL
4096-811 DYNAMIC RANDOM-ACCESS MEMORIES
read, modify write cycle timing requirements over recommended supply voltage range, TA
TMS 4051

PARAMETER

II

MIN

MAX

= oOe to 70
TMS 4051-1
MIN

tc(RMW)

Read, modify write cycle timet

730

660

tw(CEH)

Pulse width, chip enable high t

130

130

tw(CEL)

Pulse width, chip enable low

tw(wrl

Write pulse width

560
200

triCE)

Chip-enable rise time

tf(CE)

4000

490

MAX

0

e

UNIT
ns
ns

4000

190

ns
ns

40
40

ns

Chip-enable fall time

40
40

td(wr-daL)

Write to data-in-low delay time

20

20

ns

tsu(ad)

Address setup time

tsu(daH)

Data-in-high setup time

tsu(rd)

Read-pulse setup time

tsu(wrl
th(ad)

ns

Ot
240t

Ot
220t

ns

Ot
220t

ns

Write-pulse setup time

Ot
240t

Address hold time

180t

165t

ns

thIrd)

Read hold time

ns

Data hold time

320t
80t

270t

thIda)

80t

ns

ns
ns

t t The arrow indicates the edge of the chip-enable pulse for reference: Hor the rising edge; Hor the falling edge.
tTest conditions: tf(rd)

= 20

ns.

read, modify write cycle swithcing characteristics over recommended supply voltage range, TA
TMS 4051

PARAMETER
ta(CE)
ta(ad)

MIN

MAX

Access time from chip enable*
Access time from addresses t

= OOeto 70 e
0

TMS 4051-1
MIN

MAX

UNIT

280

230

ns

300

250

ns

• Test conditions: C L = 50 p F, R L = 2.2 k n, Load = 1 Series 74 TTL gate.
tTest conditions: CL = 50 pF, RL = 22 kn, Load = 1 Series 74 TTL gate. tf(CE) = 20 ns.

read, modify write cycle timing

CHIP ENABLE.

CE

ADDRESS. AO-All

REAOIWRITE. RIW

DATA INPUTI
OUTPUT. 1/0
REGION I
REGION 1 ~

REGION 2

In region 1. data-out IS valid until the I/O
termmal is forced high or low by the data-m
dnver. A tranSition from low to high IS

REGION 2 - In region 2 a single transition is permitted.
It is NOT a true "Don't Care" region.
If a low is to be written it must be valid by
the end of region 2.

persmlsslble but additional power to overcome
the output buffer will be required. A tranSition
from high to low

IS

permitted Without power

penalty.

NOTE: For the chip enable input high and low timing points are 3.0 V (high) and 1.0 V (low). Other input timing points are 0.6 V (low) and
2.2 V (high). Output timing points are 0.4 V (low) and 2.4 V (high).
For minimum cycle, tr(CE) and tf(CE) are equal to 20 ns.

57

82

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TMS 4051 JL, NL; TMS 4051-1 JL, NL
4096-81T DYNAMIC RANDOM-ACCESS MEMORIES
timing diagram conventions
MEANING
TIMING DIAGRAM
SYMBOL

INPUT
FORCING FUNCTIONS

\\\\\\
1/1///

OUTPUT
RESPONSE FUNCTIONS

Must be steady high or low

Will be steady high or low

High-to-Iow changes
permitted

Will be changing from high
to low sometime during
designated interval

Low-to-high changes
permitted

Will be changing from low
to high sometime during
designated interval

Don't Care

State unknown or changing

(Does not apply)

Center line is high-impedance
off-state

II

TYPICAL WAVEFORMS

VIH
CHIP ENABLE [
VIL

100

100 (rnA)

50

o

II (rnA)
(All inputs
except CE)

0.3 [
0

o

470

940

TIME (ns)

,75

TEXAS INSTRUMENTS
INCORPORATED

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•

DALLAS. TEXAS 75222

83

TMS 4051 JL, NL; TMS 4051-1 JL, NL
4096-81T DYNAMIC RANDOM-ACCESS MEMORIES

ACCESS TIMES vs TEMPERATURE

REFRESH TIME vs TEMPERATURE
350
300

1000

E
I
Q)

E

i=
~

~

100

Q)

c:
I

'"'"

ell

c:

~C~l.

I

i= 200

~t:.

QU/~

ell

II>

Q)

~.

(J
(J


Ci
Q.

"'I"---

I

~

30r---t---+---4----+=--cl~--t--4

I

~ 25r---t---+---4----+--~----t-~
o
o

CURRENT MEASURED AT

20 -MINIMUM CYCLE TIMES -1---r-----1

MAXIMUM RECOMMENDED

2

40t-----"'1r--_=__

~

~( Ii'

c:

f

100

E

E

Y

75

AVERAGE CURRENT vs TEMPERATURE

E

~

50

CL - Load Capacitance - rF

REFRESH TIME vs TEMPERATURE

~

25

°c

15~--~--~--~--~--~----~~

o

10

20

30

40

50

T A - Free·Air Temperature -

92

60

70

°c

o

10

20

30

40

60

70

PRINTED IN

U.S

50

T A - Free-Air Temperature -

°c

A

275

TEXAS INSTRUMENTS
INCORPORATED

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•

DALLAS. TEXAS 75222

TEXAS INSTRUMENTS RESERVES THE RIGHT TO MAKE CHANGES AT ANY TIME
IN ORDER TO IMPROVE DESIGN AND TO SUPPLY THE BEST PRODUCT POSSIBLE.

TMS 4062 JL, NL; TMS 4063 JL, NL
1024-WORD BY l-BIT DYNAMIC RANDOM-ACCESS MEMORIES

MOS
LSI

BULLETIN

•

1024 x 1 Organization

•

Access Time ... 130 ns Maximum

•

Cycle Time ... 200 ns Maximum

•

Low Power Dissipation:

NO.

DL-S

7512272.

MAY

1975

TMS 4062 JL, NL
22-PIN CERAMIC AND PLASTIC
DUAL-IN-LiNE PACKAGES
(TOP VIEW)
V BB

CS

VSS

VDD

Operating ... 120 mW Typical
Standby ... 2 mW Typical
•

A9

Differential Output

I/O

•

Wire·OR Capability

A8

•

Chip Select For Simplified Memory Expansion

A7

N/C

•

22-Pin or 18-Pin Dual-In-Line Package

description
The TMS 4062 JL, NL and TMS 4063 JL, NL
are high-speed, 1024-word by l-bit, dynamic
random-access memories fabricated on a single
monolithic chip with P·channel enhancement-type
MOS processing. The devices are designed for use in
low-cost, high-performance memory applications.
High performance and low power dissipation are
achieved with a four-transistor storage cell and unique
support circuitry. Low-capacitance inputs minimize
driver-circuit power requirements, simplify
TTL-to-MOS conversion, and reduce overall system
costs.

4

I/O

A6

CK

A5

N/C

N/C

AO

VREF

A1

AS

A2

A4

A3

II

I

TMS 4063 JL, NL
18·PIN CERAMIC AND PLASTIC
DUAL·IN-LiNE PACKAGES
(TOP VIEW)

VBB

The memory is fully decoded and its differential
outputs can be OR-tied. The chip-select input allows
the selection of individual components in large
memory
arrays. Stored information is
nondestructively read and the differential output
voltage is of the same polarity as the differential
input voltage during the write operation. Since the
memory is dynamic, it must be refreshed periodically.
The TMS 4062 is offered in 22-pin dual-in-line
ceramic (JL suffix) and plastic (NL suffix) packages
designed for insertion in mounting-hole rows on
400-mil centers. The TMS 4063 is offered in l8-pin
ceramic (JL suffix) and plastic (NL suffix)
dual-in-line packages designed for insertion in
mounting-hole rows on 300-mil centers.

18

VSS

A9

2

17

VDD

A8

3

16

I/O

A7

4

15

I/O

A6

5

14

CS AND Ci<

A5

6

AO

VREF

7

A1

RS

8

A2

A4

9

A3

operation
Reset (RS)
Every device cycle begins with the reset pulse. When the reset input is low, the internal circuits are precharged and the
address inverters are turned off. Address inputs must be valid and stable before reset goes high and must be held stable a
minimum time after reset goes high to allow the row and column decoders to function.

575

TEXAS INCORPORATED
(NSTRUMENTS
POST OFFICE BOX 5012

•

OALLAS. TEXAS 75222

93

TMS 4062 JL, NL; TMS 4063 JL, NL
1024-WORD' BY 1-B11 DYNAMIC RANDOM-ACCESS MEMORIES
operation (continued)
Clock and Chip-Select Clock (CK, CS)
The clock input is gated by the row decoders to activate a row the address of which is specified by AO-A4. The
chip-select clock input is gated by the column decoders to select a column of address A5·A9. Thus, the clock and
chip-select clock pulses, at the low level and along with a lO-bit address, isolate a single memory cell and allow transfer
of information to or from the input/output lines, which are also gated by the chip-select clock. After output data is
read, the clock and chip-select clock must return to the high level before the start of the next cycle.
Address (AO-A9)
Addresses must be valid before reset goes high. The address inputs exhibit small input capacitances since these inputs
are connected to the drains of MOS transistors that are turned off during the reset and clock pulses.
Data Input/Output 0/0)
Data is read or written through two input/output terminals that operate in a differential mode. To write, one I/O input
is taken high while the other remains at VREF. During a later read cycle, the input that was taken high will source
current while the other will not. The I/O terminals may be connected by resistors to VREF for voltage sensing or
directly to a current sense amplifier such as the SN75370. The I/O terminals are gated by chip select.

II

Refresh
Each cell must be refreshed at least once in every 2·millisecond period by cycling through the lower order row addresses
(AO-A4) or by addressing each row at least once in that period. Addressing any row refreshes all 32 cells in that row.
The chip-select clock need not be activated during refresh; however, the clock input must be cycled from high to low to
high.

functional block diagram

MEMORY MATRIX
32 ROWS

1 OF 32

&

ROW DECODER

32 COLUMNS

(1024 BITS)
32

CLOCK,CK

INPUT/OUTPUT
MULTIPLEXER

1 - -

- -

INPUT/OUTPUT

- - - - - 32

1 OF 32
RESET,RS

o--VBB

COLUMN DECODER

o--Vss
o--VREF
o--VDD
A5

As

A7

AS

Ag CHIP SELECT
CLOCK,CS

5n

94

TEXAS INSTRUMENTS
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•

DALLAS, TEXAS 75222

TMS 4062 JL, Nl; TMS 4063 Jl, Nl
1024-WORD BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORIES
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltages:
VOO and VREF, with respect to VSS
VOO and VREF, with respect to VBB
VBB, with respect to VSS
All input voltages, with respect to VSS
Operating free-air temperature range
Storage temperature range

-27 V to 0.5 V
-30 V to 0.5 V
-0.5 V to 10 V
-30 V to 0.5 V
. _ooe to 70°C
-55°C to 125°C

recommended operating conditions
PARAMETER
Supply voltage, VBB-VSS (see Notes 1 and 2)

MIN

NOM

MAX

2.3

2.5

2.7

Supply voltage, Voo

V
V

0

Supply voltage, VSS
Supply voltage, VREF
High-level input voltage, all inputs, VIH
Low-level address input voltage, VIL(ad) (see Note 3)
Low-level input voltage at reset and both clocks, VI L(rs.

<1»

(see Note 3)

Low-level input voltage at I/O, VI L(I/O)

19

20

21

V

6.6

7

7.4

V

VSS -2
-2

VSS
1

V

0

-5

0

0.4

V

VREF -1

Refresh time, trefresh
Operating free-air temperature, T A
NOTES:

UNIT

V
V

VREF VREF +1
2

ms

70

°c

0

1. Throughout this data sheet supply voltage values are with respect to VOO. unless otherwise noted.
2. VBB must be applied prior to VSS.
3. The algebraic convention where the most positive limit is designated as maximum is used in this data sheet for logic voltage levels
only.

electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)
PARAMETER

TEST CONDITIONS

IOOH

High-level differential output current

IHad)

Address input current

II(rs. ct»

Reset or either clock input current

11(1/0)

I/O input current

MIN

Typt

MAX

UNIT

J1.A

100

= VOO (0 V)
VI = VOO (0 V)
VI = VREF

1

J.J.A

10

VI

IBB

Supply current from VBB

All inputs at VSS

10

IREF

Supply current from VREF

All inputs at VSS

10

J1.A
J1.A
J1.A
J1.A

100

J1.A

9

15

rnA

18

30

mA

100

J1.A

ISS(1)
ISS(2)

ISS(3)

All address and reset inputs at VSS,

Supply current from VSS

(see Figure 1)
Reset at VOO (0 Vl.Clocks at VSS,

Supply current from VSS

TA

= 25°C

Reset and both clocks at VSS.

Peak supply current from VSS
(see Note 4)

All addresses at VOO (0 V),
TA

ISS(4)

2

= 25°C

Reset at VSS.
All other inputs at VOO (0 V)

Supply current from VSS

ISS(av) Average supply current from VSS

All supply voltages nominal,
tc

= 290 ns

6

mA

t All typical values are at T A = 25°C.
NOTE 4: The steady-state value of ISS(3) is less than 100

J1.A.

5

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

95

TMS 4062 JL, NL; TMS 4063 JL, NL
1024-WORD BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORIES
VSS
RESET
VDD
Vss
CLOCKS
VDD
Vss
ALL ADDRESSES

••--

-"-ofoIIl.~- ISS2 ~''''I

I
-I

ISS1

VDD

FIGURE 1-TIME INTERVALS FOR MEASURING SUPPLY CURRENTS

capacitances over full ranges of recommended operating conditions (unless otherwise noted)

II

PARAMETER

TEST CONDITIONS

Cj(ad)

Input capacitance. address inputs

VI

Ci(rs)

Input capacitance. reset inputs

VI

Ci(cfJ)

Input capacitance. both clock inputs

VI

Co/a)

I/O terminal capacitance

VI

= VSS.
= VSS.
= VSS.
= VSS.

f
f

= 1 MHz
= 1 MHz

Typt

MAX

2.5

3.5

pF

30

40

pF

UNIT

f= 1 MHz

15

18

pF

f = 1 MHz

2.5

3.5

pF

t All typical values are at T A = 25° c.

TYPICAL DYNAMIC CURRENT WAVEFORMS

I~

1

RESET

1

J

1

CLOCKS

ADDRESS. AO·A9

'DO (mAl

~I

290 ns

;~: I

Vss

f

VDD

1

J

JVss
VDD
Vss

1

J

VDD

-20
-10

o
'REF (mAl

----

E±
~±

________~_______________J/l~___JA~

_ _ _ _ _ _ ___

57!

96

TEXAS INSTRUMENTS
INCORPORATED

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•

DALLAS. TEXAS 75222

TMS 4062 JL, Nl; TMS 4063 Jl, Nl
1024-WORD BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORIES
read cycle timing requirements over recommended supply voltage ranges, T A
PARAMETER

=

O°C to 70°C

TEST CONDITIONS

MIN

VIL(rs -rs)

Delay time, either clock high to reset

tsu(ad)

Address setup time

t w (<1»

Pulse width, either clock low

tsu(da)

Data setup time

th(ad)

Address hold time

thIda)

Data hold time

60
0
VILlrs, <1»

=0 V

VILlrs, <1»

= -5 V

ns
ns

ns

0
70
60

ns

50
0

ns

ns

ns

write cycle timing diagram

RESET,RS

CLOCK,CKOR
CHIP.sELECT
CLOCK,Cs

ADDRESS, AO-A9

INPUT/OUTPUT,I/O

NOTE: All reference points on inputs are 90% and 10% points.

575

98

TEXAS INSTRUMENTS
INCORPORATED

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DALLAS. TEXAS 75222

TMS 4062 JL, NL; TMS 4063 Jl, NL
1024-WORD BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORIES

read, modify write cycle timing requirements over recommended supply voltage ranges, T A = O°C to 70° C
PARAMETER

TEST CONDITIONS

MIN

VILlrs..:I

j.-- tpxz - ,

I

---------i~

---------H-I-.Z-S-T-A-T-E----------------~([FI-----D-A-T-A--V-A-L_ID

______

VOL

~J>----

NOTE: Timing points are 90% (high) and 10% (low).

TEXAS INSTRUMENTS
INCOHPOHATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

109

TMS 4700 JL, NL
1024-WORD BY 8-BIT READ-ONLY MEMORY
SOFTWARE PACKAGE
The TMS 4700 JL, NL is a fixed-program memory in which the programming is performed by TI at the factory during the
manufacturing cycle to the specific customer inputs supplied in the format shown_ The device is organized as 1024 8-bit
words with address locations numbered 0 to 1023. Any 8-bit word can be coded as a 2-digit hexadecimal number between 00
and F F. All stored words and addresses in the following format are coded in hexadecimal numbers. In coding, all binary
words must be in positive logic before con'version to hexadecimal. 01 is considered the least-significant bit and 08 the
most-significant bit_ For addresses AO is least significant and A9 is most significant.
Every card should include the TI Custom Device Number in the form ZAXXXX (4-digit number to be assigned by TI) in
columns 75 through 80.
Output enable 2 is customer programmable. Every card should include in column 74 a 1 if the output is to be enabled with a
high-level input at OE2 or a 0 for enabling with a low-level input.
The 1024 coded words must be supplied on 64 cards with 16 2-digit hex numbers per card.

II

CARD

COLUMN

HEXADECIMAL INFORMATION

1-9

BLANK
: (ASCII character colon)

10

10 (specifies 16 words per card)

11-12
13
14-16
17-18

BLANK
Hex address of 1st word on 1st card (Oth word, address normally 000)
BLANK
Oth word in Hex

19-20

64

49-50

15th word in Hex

51-73

BLANK

1-9
10
11-12

BLANK
: (ASCII character colon)
10
BLANK

13
14-16
17-18

Hex address of 1st word on 64th card (1008th word, address normally 3FO)
BLANK

19-20

1008th word in Hex

49-50

1023rd word in Hex

51-73

BLANK

PRINTED IN USA

110

5n

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TEXAS INSTRUMENTS RESERVES THE RIGHT TO MAKE (HANGES AT ANY TIME
IN ORDER TO IMPROVE DESIGN AND TO SUPPLY THE BEST PRODUCT POSSIBLE.

TMS 4800 JL, NL
16384-BIT READ-ONLY MEMORY

MOS
LSI

BULLETIN NO. DL-S 7512260, MAY 1975

24-PIN CERAMIC AND PLASTIC
DUAL-IN·LlNE PACKAGES
(TOP VIEW)

• 2048 x 8 or 4096 x 4 Organization
• Total TTL-Compatibility
• Maximum Access Time ... 700 ns

VSS

• Minimum Cycle Time ... 1000 ns

Al

24

OEl

2

23

01

22

• Typical Power Dissipation ... 450 mW

A2

3

• Open-Drain Output for Wire-OR Configurations

A3

4

• 24-Pin 600-Mil Dual-in-Line Packages

A4

5

20

04
05

• Two Chip-Enable Controls
description
The TMS 4800 JL, NL is a 16384-bit read-only
memory, organized as either 2048 words of 8-bits or
4096 words of 4-bits. All inputs are TTL-compatible.
The eight open-drain outputs must be connected by
pull-down resistors to an external negative supply to
drive standard TTL circuits. Two output-enable
terminals allow each 2048 x 4-bit array to be read
independently as 4-bit words or simultaneously as
8-bit words.

02
03

A5

6

19

A6

7

18

06

Al0

8

17

07

VGG

9

16

08

A9

10

15

All

A8

11

14

OE2

A7

12

13

AR

a

Two devices can be OR-tied, with proper choice of programming on the output-enable terminals to be specified by the
customer. Addresses may change up to 50 ns after the clock cycle begins. This allows TTL address-decoding circuits to
synchronize on the rise of the clock and stabilize during this interval effectively shortening the device read-access time.
The TMS 4800 is designed with P-channel enhancement-type technology for high-density, fixed-memory applications
such as logic function generation and microprogramming. This ROM is supplied in a ceramic (JL suffix) or plastic (NL
suffix) 24-pin package designed for insertion in mounting-hole rows on 600-mil centers.

operation
address read (AR)
Address read constitutes the master timing signal of the device. After AR goes high, address and output enable inputs
latch. The address-read clock is high during the address-valid and output-enable-valid intervals. Data out is valid both
before and after AR goes low, since enabled outputs latch during the cycle.
address (A 1-A 11)
Any of the 2048-word addresses are selected by an ll-bit positive-logic binary word, A 1 being the least-significant bit
progressing through to All, which is the most-significant bit. Address inputs can change up to 50 ns after the AR clock
goes high and must remain valid 250 ns after AR goes high. This input latching feature allows the user to change address
while data is being read. These system advantages result from latching of the internal address register during a short
address-valid interval.
output enable (OE1 and OE2)
The ROM consists of two side-by-side 2048-word-bY-4-bit arrays. OEl enables output terminals 01 through 04 and
OE2 outputs 05 through 08 with the two arrays being enabled independently. The user may choose any of four
combinations by enabling with, either a low or high level on OEl or OE2. To read 8-bit words with a single address,
both OEl and OE2 must be enabled. For 8-bit readout, two devices may be OR-tied to increase the effective size of the
ROM system by programming complementary enable levels on corresponding device terminals.

75

PRELIMINARY DATA SHEET:
Supplementary data may be
published at a later date.

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111

I

TMS 4800 JL, NL
16384-81T READ-ONLY MEMORY
operation (continued)
Output terminals on a single device are OR-tied for a 4096-word x 4-bit organization as follows: 01 to 05; 02 to 06;
03 to 07; and 04 to OB. Since the OEl and OE2 inputs latch internally, the enable signals may change before or
during the output data-valid interval. For additional information on OR-ties, see the section on Expanded Memory
Configurations.
data out (01-08)
Outputs 01 through 04 are enabled by OE 1 with outputs 05 through 08 enabled by OE2. Output transistors are
open-drain and compatible with TTL circuits when connected to an external negative supply through a pull-down
resistor. All outputs go low immediately after the rise of AR. A disabled output rises to a high level after a propagation
delay following the fall of the AR clock if a high logic level was stored. If devices are OR-tied, an enabled output should
be read before AR goes low in order to distinguish a stored high from a high coming from the OR-tied disabled output.
Because the outputs latch, data on an enabled output remains valid until the next rise of the AR clock.

functional block diagram
OE1

II

I
AR
A1

,.......L

r---

e

ex:
w

l~

Cl

w

A6

ex:

A7

I-

:l
Q.

A8

~

I-

0

:l
0

u

••
w

e

...

:;:

:I:
Cl
:l
0

2048 x 8

ex:

i-.--

03

ex:

e

04

.~
I-

05

(/)

ex:
:l W
Q.

:I:

I-

:;:

A10

02

~

MEMORY MATRIX

I-

A9

A11

01

:l ex:
w
Q.

w

A3

A5

~
I- C/l

A2

A4

I

:l
0

0......--

I

06

>
a:
e

07
08

=c
I
OE2

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)*
Supply voltage, V GG (see Note 1)
All input voltages (see Note 1)
Operating free-air temperature range
Storage temperature range
NOTE:

-20 to 0.3 V
-20 to 0.3 V
O°C to 70°C
-55°C to 150°C

1. Under absolute maximum ratings, voltage values are with respect to VSS(substrate). Throughout the remainder of this data sheet
voltage values are with respect to a floating ground.

'COMMENT: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum·rated conditions for extended periods may affect
device reliability.

57!

112

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TMS 4800 JL, NL
16384-BIT READ-ONLY MEMORY
recommended operating conditions
PARAMETER
Supply voltage, VSS
Supply voltage, VGG
High-level input voltage, VIH (all inputs)
Low-level input voltage, VIL (all inputs) (see Note 2)
Read cycle time, tc(rd)
Pulse width, address read high, tw(ARH)
Pulse width, address read low, tw(ARU

MIN

NOM

MAX

UNIT

4.75
-11

5
-12

5.25
-13

V

VSS -1.5

VSS

V

-4

0.6

V

1000
500
450

100000

Address-read fall time, tf(AR)
Address-read-high-to-address delay time, td(ARH-ad)
Address-read-high-to-output-enable delay time, td(ARH-OE)

250
250

ns
ns
ns
ns

..

ns
ns

a

Operating free-air temperature, T A

ns
ns

40
40
50
50

Output-enable hold time, th(OE)

--

ns

Address-read rise time, tr(AR)

Address hold time, th(ad)

V

70

°c

NOTE 2. The algebraic convention where the most positive limit is designated as maximum is used in this data sheet for logic voltage levels only.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage

IOL

Low-level output current

II

Input current (all inputs)

ISS

Supply current from VSS

IGG

Supply current from VGG

+AII typical values are at T A

=

= 2.4 rnA
VOL = 0.4 V
VI = VSS
IOH

MIN

TYP+

MAX

2.5

UNIT
V

29
-29

50

J..LA

1
40
-40

rnA

J..LA
rnA

25°C.

switching characteristics over recommended supply voltage range, T A = O°C to 70°C (unless otherwise noted)
PARAMETER
ta(ad)

MIN

Propagation delay time, low-to-high level output from
tpLH
tpD

NOTES:

V, V GG

= -12

700

UNIT
ns
ns

600

Propagation delay time from address read to data valid

=5

MAX

200

address read (output disabled)

+TYPical values are measured at Vss

TYP+

550

Access time from address

750

ns

V. and T A = 25° C.

3. Enabled outputs remain valid until next AR pulse. Disabled outputs may be considered valid until 200 ns after the high-to-Iow
transition of AR.
4. All rise and fall times are <:20 ns.

,75

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113

TMS 4800 JL, NL
16384-81T READ-ONLY MEMORY
voltage waveforms

I..
ADDRESS READ, AR

ADDRESS, AO-A11

OUTPUT ENABLE, OE1 OR OE2

II

OUTPUT,01-08,ENABLED
"0" STORED

~!f6'RED

t==\

\

OUTPUT, 01-08, DISABLED

"0" STORED

EXPANDED READ-ONLY MEMORY CONFIGURATIONS
4K x 8

8K x 4
OE1
I OE1

c

l~

01
04

01
C

:1>0)

CIl

-I'

:I>!:

05 rr-r08 f - - -

2

co
em
CIl

08

OE2

1

OE
OE3

OE2

T OE3

I
01

01

-

-

04
05 ff--

r08 f - - -

08

OE4

D - Disa ble
I OE4

E - Enable

WORDS

OE1

OE2

OE3

OE4

WORDS

OE

0-2048
2049-4096
4097-6144
6145-8192

E
D
D
D

D
E
D
D

D
D
E
D

D
D
D
E

0-2048
2049-4096

E
D

NOTE: One device programmed to enable with OE1 = OE2 = 1
Other device programmed to enable with OE1 = OE2 = 0
575

114

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TMS 4800 JL, NL
16384-811 READ-ONLY MEMORY
SOFTWARE PACKAGE
The TMS 4800 JL, N L is a fixed program memory in which the programming is performed by TI, at the factory during
the manufacturing cycle,to the specific customer inputs supplied in the format shown. The device is organized so that it
can be used for storing either 2048 words of 8 bits or 4096 words of 4 bits. Words of 8- or 4-bit lengths are read by
proper enable levels on OE 1 and OE2. Output 01 is the least-significant bit in an 8-bit word, 05 and 01 in 4-bit words.
All addresses and stored words in either organization are coded in octal. Any address up to 2048 can be written as a
4-digit octal number. Any 8-bit binary word can be converted to a 3-bit octal number. In coding, all binary words must
be in positive logic and right justified before conversion to octal.
Every card must include the following coded information.
Column 73-0El enable code
Column 74-0E2 enable code
Columns 75-80 - TI CUSTOM DEVICE NUMBER ZAXXXX (4-DIGIT NUMBER ASSIGNED BY TI)
The output enable (OE) option is programmed on the chip with the customer pattern. A high voltage level enable is
specified by a "1" in columns 73 or 74, a low voltage level enable by a "a".

II

2048-word by 8-bits

I

Code deck format Card

Column
1-4
5-7
8-10

50-52
2

1-4
5-7

50-52
128

1-4
5-7

50-52

Octal Information
Octal address (N) of 1st output word on 1st card
1st stored 8-bit word (in octal)
2nd stored 8-bit word (in octal)

16th stored 8-bit word (in octal)
Octal address (N + 16) of 1 st output word on 2nd card
17th stored 8-bit word

32nd stored 8-bit word
Octal address (N + 2032) of 1st output word on 128th card
2033rd stored 8-bit word

2048th stored 8-bit word

4096-word by 4-bits
Terminals OEl and OE2 independently enable outputs 01-04 and 05-08. Each enable terminal can be programmed to
enable with a high or low level input.
To read only 4 bits simultaneously from either set of output terminals, the stored information must be coded as an
8-bit positive logic binary word converted to octal. Each 4-bit binary word is right justified before forming the 8-bit
word. In coding, words 1 and 2049, 2 and 2050, ... and 2048 and 4096 are combined (08-05 on the left of 04-01) as
8-bit words and converted to octal as in the case of the 2048 by 8 coding instructions. This coding format also requires
128 cards with 16 octal words (32 4-bit binary words) per card.

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115

TMS 4800 JL, NL
16384-81T READ-ONLY MEMORY
OUTPUT INTERFACE
single resistor TTL interface

MOS interface
VGG = -12 V NOM

VGG = -12 V NOM

R1

r-+----).-.. DO 1

R1
...4-_ _. . D08

I
--L-

~

a

C1

Vss = 5 V NOM

Vss = 5 V NOM

R1 = 12 kn
C1 = 10pF

R1 = 6.8 kn
C1=15pF
MAX TTL FAN-OUT = 1

TYPICAL CHARACTER ISTICS
750

ACCESS TIME vs TEMPERATURE

I

I

I 700

«

«

V)

~

650

V

E

.g
Q)

E

Q)

u

«
I

~ 500 ~

V
./

-6:

30

TYPICAL

t---

r---- t--- r----

0.
:J

en

~ 25

"""

t--- r---

.!!'
Cl

.5? 20
tsu (ad) ~ 50 ns

..,ro

1

450

a

~

:;

. / VTYPICAL

550

C 35
u

V

V)

u

V

/'

600

i=
'"

40

I

Q)

-0

1

E

'"
'"

"'C

1

MAXIMUM

MAXIMUM

'"c

SUPPLY CURRENT vs TEMPERATURE

45

10

20

30

I

40

50
60
T A - Free-Air Temperature - DC

15

70

a

10

20

30

40

50

60

70

T A - Free-Air Temperature - DC

PRINTED IN U.S A

116

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575

TI lannol assume any responsibility for ony lirluits shown
or represent 'hot they ore free from po'en' infringement

TEXAS INSTRUMENTS RESERVES THE RIGHT TO MAKE CHANGES AT ANY TIME
IN ORDER TO IMPROVE DESIGN AND TO SUPPLY THE BEST PRODUCT POSSIBLE.

TMS 5001 NL
4-MODE DYNAMIC 90-KEY KEYBOARD ENCODER

MOS
LSI

BULLETIN NO. DL·S 7512274, MAY 1975

•
•
•
•
•
•
•
•
•
•
•
•

ASCII Logical Bit-Pairing and Typewriter Codes

40-PIN PLASTIC
DUAL-IN-LiNE PACKAGE
(TOP VIEW)

ASR33 Teletype Code
Baudot Paper Tape Punch Code

40

R1

COM

2

39

R2

RES
LO/RO

3
4

38
37

R3
R4

0010

5

36

R5

009

6

35

R6

008
007

7
8

34
33

R7
R8

006

CAP

N-Key Roll-Over or Lockout Mode
Data-Ready Pulsed Output
Internal Oscillator
Latched Data Outputs
Adjustable Key-Noise Protection
Keyboard Column Leakage Compensation
Compatible with Reed and Mechanical Switches
TTL-Compatible Inputs and Outputs
1 O-Bit Output Words

description

9

32

R9

005 10

31

ON

004 11
003 12
002 13

30 VSS
29 MS2
28 MS1

001

14

27

VDD 15
DR 16

26

II

VGG
C10

I

25 C9
The TMS 5001 N L is an MOS LSI dynamic encoder
for use with standard keyboards having up to gO
24 C8
C1 17
keys. The encoder is pre-programmed to generate in
23 C7
C2 18
positive logic two ANSI-standard codes - the logical
22 C6
C3 19
bit pairing and the typewriter codes - the ASR33
C4 20
21 C5
teletype code, and the Baudot paper tape code. The
device utilizes a 3600-bit ROM (40 x gO
organization), a g-row by 10-column key-scanning matrix, driver and sense amplifier interface circuits, a control circuit,
a shift-register memory, and an on-chip oscillator with frequency determined by an external resistor and capacitor.

The circuit can operate in the N-key roll-over or N-key lockout mode with external logic control. Key-make and
key-break noise is ignored after initial key identification because scanning is terminated for a time interval that can be
adjusted with another external capacitor at the delay-node terminal.
One of four key modes is selected by proper input levels at two mode-select terminals. A data-ready pulse is generated
to indicate that a key is depressed, the binary word has been encoded, and that word is available at the I/O terminals.
The control inputs are compatible with Series 74 TTL circuits using pull-up resistors. Each data output can drive one
Series 74 TTL circuit without external resistors.
The TMS 5001 N L is offered in a 40-pin dual-in-line plastic (N L suffix) package designed for insertion in mounting-hole
D
rows on 600-mil centers. The device is characterized for operation from ODC to 70 C.

operation
The TMS 5001 subsystem consists basically of an oscillator, row and column matrix scanners, a control section with
memory, and a ROM with buffered outputs.
oscillator
The internal oscillator generates two internal clock signals at the oscillator frequency that control the precharge of the
column inputs and drive the row and column scanning counters. The oscillator frequency is set by an external resistor
connected between the resistor (RES) and common (COM) terminals and an external capacitor connected between the
capacitor (CAP) and common (COM) terminals.

575

PRELIMINARY DATA SHEET:
Supplementary data may be
published at a later date.

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117

TMS 5001 NL

4-MODE DYNAMIC gO-KEY KEYBOARD ENCODER
operation (continued)
row and column matrix scanners
The keyboard is connected to the column (C1-C10) inputs and the row (R1-R9) outputs. Ouring one half of an
oscillator cycle, the column inputs and row outputs are precharged to a negative voltage. In the next half-cycle, the
moduI0-10-counter column scanner enables one of the ten column-input gates and the moduI0-9-counter row scanner
allows one row to be connected to VSS (nominally 5 V) through an MOS transistor having an impedance of about 600
ohms. If the keyboard switch for that row and column is closed, the column input line capacitance discharges through
the MOS load to VSS' At a voltage VSH (near VSS) the key closure is detected and scanning immediately stops. The
row and column position is uniquely identified and stored as a single bit in a 90-bit shift register (see control section).
Any single key depression is detected within one keyboard scan cycle, which is 90 oscillator or clock cycles. Within
one-half clock cycle after detection, the output word becomes valid at the data out (001-0010) terminals.
In the roll-over mode, two clock cycles plus one delay-node interval after detection of a depressed key the scanning
operation resumes and the next depressed-key location is detected and stored in the memory. Any new output word
becomes valid one-half clock cycle after detection. If multiple keys are depressed simultaneously, the scanners will
ultimately locate and store all locations in the memory and each output word will become valid in rapid sequence.

II

In the lockout mode as the delay node voltage drops through VSL, scanning does not resume until the first key is
released and the first output remains valid until the second depressed key is detected. Thus the second and subsequent
depressed keys are ignored until the first key is released.
In either mode when a key is released, scanning in the next cycle is halted when that key location is reached. The halt
signal is obtained from the information in the memory identifying that key location. Key-release noise is therefore
ignored until the delay node again precharges to VSL' Then scanning resumes and the next depressed key is identified
and its location stored in the memory.

control section
The delay node (ON) terminal voltage controls the time during which scanning stops after key detection. An external
capacitor may be connected between ON and VOO to lengthen this delay. Key-noise immunity can therefore be
adjusted according to the key-switch characteristics.
A high-level data ready (OR) output pulse having a length of one clock cycle appears one-half clock cycle after the
output data becomes valid to indicate that the encoded output word is available at the ten outputs.

-,

The lockout/roll-over (LO/RO) terminal places the device in the lockout operating mode when the LO/RO input is high
or in the roll-over mode when LO/RO is low.
ROM and output buffers
The row counter output addresses the ROM to generate a unique 10-bit binary word for each of the four modes and
each of the 90 key positions. One of the four modes is selected by combinations of high- and low-level inputs at the
mode select terminals (MS1 and MS2) as shown in the Character Output Charts.
The data outputs (001-008) can drive Series 74 TTL circuits without external resistors. Output data becomes valid
within one-half clock cycle after a key is detected.
In the lockout mode, output words are latched and data remains valid until all three of the following events occur:
1) the key is released, 2) the delay node precharges to VSL and scanning starts, and 3) a new key is depressed and
detected.
I n the roll-over mode, output data remains valid only until the delay node charges to VSL and another key is detected.
The OR pulse is generated within one cycle after key detection.
57!

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TMS 5001 NL
4-MODE DYNAMIC gO-KEY KEYBOARD ENCODER
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) *
Supply voltage, Voo (see Note 1)
Supply voltage, V GG (see Note 1)
I nput voltages (all inputs) (see Note 1)
Operating free-air temperature range
Storage temperature range

-20 V to 0.3 V
-20 V to 0.3 V
-20 V to 0.3 V
oOe to 70°C
-55°C to 150°C

NOTE 1: Under absolute maximum ratings, voltage values are with respect to the normally most positive supply, VSS (substrate). Throughout
the remainder of this data sheet voltage values are with respect to VOO'
'Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions"
section of this specification is not implied. Exposure to absolute·maximum·rated conditions for extended periods may affect device reliability.

functional block diagram
KEYBOARD COLUMN INPUTS

r~--------------~~---------------~\
Cl0

C3

C2

Cl

II

I

MS1 ~(~2~B)~~r-----------,
COLUMN
SCAN
COUNTER

MODE SELECT 1-----(29) I
MS2'-----~

I

0010
009

(5)

I

(6)
(7)

I-

:::l

0
0

007

0

006

80

005

u

0

004

~

003

a:
~

(31)

DOB
(B)

til

a:
w
u.
u.

(9)

:::l

co

(10)

~

(11)

LOCKOUTI
ROLL·OVER,

LO/RD

I-

:::l

0

(12)

002

(4)

CONTROL
CIRCUIT

I-

DELAY
NODE, ON

1(16)

DATA
READY, DR

(13)

(14)
001-

ROW SCAN
COUNTER

I

J
R9

RB

R7

R6

R5

R4

R3

R2

RES

Rl

COM

CAP

~fJ.,

------------~~~-------------

KEYBOARD ROW OUTPUTS

575

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119

TMS 5001 NL
4-MODE DYNAMIC 90-KEY KEYBOARD ENCODER
recommended operating conditions
PARAMETER

MIN

NOM

Supply voltage, VDD

MAX

UNIT
V

0

V

Supply voltage, VGG

-11

-12

-13

Supply voltage, VSS

4.75

5

5.25

V

-1.6

V~~

V

10

VSS -3.9
100

0

70

High-level input voltage (MS and LO/RO inputs), VIH

V~~

Low-level input voltage (MS and LO/RO inputs), VIL
Oscillator frequency, fosc
Operating free-air temperature, T A

V
kHz

DC

electrical characteristics over recommended operating free-air temperature range
PARAMETER

TEST CONDITIONS

High-level sense voltage, VSH

MIN

MAX

VSS -2.2

VSS
VSS -7.8

Low-level sense voltage (see Note 2), VSL

II

High-level output voltage, data ready and DO outputs, VOH

10H = 100p.A

Low-level output voltage, data ready and DO outputs, VOL

10L = 1.6 mA

VSS-1
0

Precharge voltage at column inputs (see Note 2)

VGG +7.5
-42

Supply current from VGG, IGG
Row or column line capacitance
NOTE

VSS
0.5

f=100kHz

1000

UNIT
V
V
V
V
V
mA
pF

2: The algebraic convention where the most positive (least negative) limit is designated as maximum is used in this data sheet for sense
and precharge voltage levels only.

TYPICAL OPERATING CHARACTERISTICS
DELAY NODE INTERVAL
vs EXTERNAL CAPACITANCE

OSCILLATOR FREQUENCY vs EXTERNAL
RESISTANCE AND CAPACITANCE

100

.........

I"

50

I

40

l'..

~

30
>
u
c

OJ

::l
0"

\:: 20

"

I

~ ~ominal operatinglconditions
i'..

1'00...

60

100

TA = 2SOC

......

80

"-

If

/

,,~ R = 50 kn

~~

'"

'~.20~

"'

10
100

I

co
>

e
c

"

200

300

'/

OJ

"'C
0

/V

Z

>
ro
a:;

'" ""
""

150

/

E 10

"-~ R=100k~

r'--.~

LL

50

TA 2SOC
Nominal operating conditions

f

0

0.1
0.001

400 500

Capacitance - pF

0.01

0.1

Capacitance - flF

575

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VI

-.J

01

n
:::r

Ql
~

TYPEWRITER PAIRING

Rl

Cl

C2

C3

C4

C5

C6

C7

C8

C9

Cl0

MODEt

Cl

ESC

2

ETX

4

NUL

6

7

8

9

0

0

ESC

ESC

@

ETX

$

NUL

1\

&

(

)

ESC

R2

ETX

ESC
2

-l
" rr'I

><
~ »
~

R4

CIJ

oIII z
_

~8z

~~CIJ
. 0-1

R5

g;;c

~~c

: Os::
~

~

;;:
~

R6

rr'I

Z

-I

en

R7

R8

4

NUL

3

R

5

!

#

R

%

1
2

6

7

8

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MOS
LSI

TMS 3101 LC, NC
DUAL 100-BIT STATIC SHIFT REGISTER
MAY 1975

•

DC to 2.5-MHz Operation

•

Static Configuration

•

Inputs and Outputs Fully TTL-Compatible

•

Push-Pull Output Buffers

•

Power Supplies ... 5 V, -12 V

•

Low-Threshold Technology

TO-100 HERMETICALLY SEALED PACKAGE
(TOP VIEW)
VGG

description
The TMS 3101 LC , NC is a dual 100-bit static shift
register with independent inputs and outputs for each
register. Two external clocks are common to both
registers. All inputs and outputs are fully compatible
with Series 74 TTL and require no external resistors.

NO CONNECTION
I

II

16-PIN PLASTIC DUAL-IN-LiNE PACKAGE
(Top VIEW)

I

CLOCK 2

The TMS 3101 is offered in 10-pin TO-100 (LC
suffix) and 16-pin dual-in-line plastic (NL suffix)
packages_ The 16-pin package is designed for insertion
in mounting-hole rows on 300-mil centers_

16

NO CONNECTION

NO CONNECTION
NO CONNECTION

CLOCK 1

3

14

IN 1

OUT 1
VDD

applications
IN 2

The TMS 3101 can be used in display, terminal, and
card read/punch equipment.

5

12

NO CONNECTION

NO CONNECTION

NO CONNECTION

functional block diagram

10

VGG

,-----------

OUT2

NO CONNECTION
VSS

l

I

OUTPUT 1

INPUT 1
CLOCK <1>1

e-------~-

CLOCK <1>2

e-~-4-------_+_

INPUT 2

t---+-

vss

VDD
vGG
OUTPUT 2

A complete data sheet may be obtained by writing directly to:
Marketing and Information Services
Texas I nstruments Incorporated
P_O_ Box 5012 MS 308
Dallas, Texas 75222

575

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

123

MOS
LSI

TMS 3112 JC, NC; TMS 3122 JC, NC; TMS 3123 JC, NC
HEX 32-81T STATIC SHIFT REGISTERS
BULLETIN NO. DL-S 7512261, MAY 1975

•
•
•

•
•
•
•
•

•

DC to 2-MHz Operation
Static Configuration
Single TTL-Compatible Clock
Inputs and Outputs are Fully
TTL-Compatible
Single-Ended (Open-Drain) Buffers
On-Chip Recirculate Logic
Gated-Output Control (TMS 3112,
TMS 3123)
Power Supplies ... 5 V, -12 V
MOS Low-Threshold
P-Channel Technology

CERAMIC AND PLASTIC
DUAL-IN-LiNE PACKAGES
TMS 3112
(TOP VIEW)
INPUT4

1

24

INPUT 3

INPUT 5

2

23

INPUT 2

INPUT6

3

22

INPUT 1

NO CONNECTION

4

21

NO CONNECTION

REC CONTROL

5

20

Vss

VGG

6

19

NO CONNECTION

CLOCK

18 OUTPUT CONTROL

OUTPUT 6

8

17 OUTPUT 1

NO CONNECTION

description

II

The TMS 3112, TMS 3122, and TMS 3123 JC, NC
are 6-channel by 32-bit shift registers on a single
monolithic chip with separate inputs and outputs and
a common recirculate control. The TMS 3112 and
TMS 3123 feature a common output gating control.
The clock and all inputs can be driven directly from
Series 74 TTL circuits and all outputs are capable of
driving one Series 74 TTL circuit.

16 NO CONNECTION

NO CONNECTION

10

15 NO CONNECTION

OUTPUT5

11

14 OUTPUT 2

OUTPUT 4 12

13 OUTPUT 3

TMS 3122
(TOP VIEW)
INPUT 4

16

INPUT 5

Vss
INPUT 3

INPUT 6

Cross-coupled inverters (flip-flops) are employed to
implement each bit storage location. This static
design allows input data rates from dc to 2 MHz and
long-term data storage.
P-channel enhancement-type low-threshold processing
has been employed to reduce power dissipation and
provide simple interfaces with bipolar circuits.
The TMS 3122 and TMS 3123 are offered in 16-pin
and 18-pin dual-in-line packages, respectively. The
TMS 3112 is offered in a 24-pin dual-in-I ine package.
All three devices are available in ceramic (JC suffix)
or plastic (NC suffix) packages. The 16- and 18-pin
packages are designed for insertion in mounting-hole
rows on 300-mil centers. These devices are characterized for operation from -25°C to 85°C.

RECIRCULATE

CLOCK

OUTPUT 2

OUTPUT 6
OUTPUT 5

OUTPUT 4

TMS 3123
(TOP VIEW)
INPUT 4
INPUT 5

INPUT 3

INPUT 6
RECIRCULATE
OUTPUT 1

applications
The TMS 3112, TMS 3122 and TMS 3123 can be
used in printers, terminals, and peripheral (18M
System 3) applications where 32, 64, or 96 bits of
serial storage are needed.

CLOCK

OUTPUT 2

OUTPUT 6

OUTPUT 3

OUTPUT 5

OUTPUT 4

NO CONNECTION

OUTPUT CONTROL

NOTE: The TMS 3122 and TMS 3123 are compatible pin for pin
except for output gate control, which necessitates one extra pin.

57!

124

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

TMS 3112 JC, NC; TMS 3122 JC, NC; TMS 3123 JC, NC
HEX 32-81T STATIC SHIFT REGISTERS
operation
Transfer of data into and out of the shift register occurs on the low-to-high transition of the clock. I nput data must be
set up a minimum time before the low-to-high transition and must be held for a minimum time after that transition.
For long-term data storage, the clock must be maintained high, and in this mode the recirculate and data input levels
may change without affecting the data output levels.
Recirculate occurs on the low-to-high clock transition with the recirculate control high. The recirculate control level
must be set up a minimum time before this transition and held a minimum time after the transition. Data is entered
with the recirculate control low. During recirculation, data is continuously available at the outputs when the output
gate control is low. A high level on the output gate control forces all outputs low. Data inputs are inhibited during
recirculation.

functional block diagram
FUNCTION TABLE
OUTPUT GATING CONTROL
(TMS 3112 AND TMS 3123)

Vss

,r _l - -

RECIRCULATE

----------------

I

OUT 1
IN 1

INPUT

FUNCTION

H

L

Recirculate

H

H

Reci rcu late

L

L

L is written

L

H

H is written

II
I

H ; high level
L; low level

OUT2
IN2

,,
I,

, ,
OUTS

INS

- - - - - - - - - - - --------T
RECIRCULATE
CONTROL

CLOCK

NOTE: TMS 3122 does not have output gating.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)*
-20 V to 0.3 V
-20 V to 0.3 V
-20 V to 0.3 V
_25° C to 85° C
-55°C to 150°C

Supply voltage, V GG (see Note 1)
Clock input voltage (see Note 1)
Data input voltage (see Note 1)
Operating free-air temperature range
Storage temperature range

NOTE 1: Under absolute maximum ratings, voltage values are with respect to the normally most-positive supply, VSS (substrate). Throughout
the remainder of this data sheet voltage values are with respect to a floating ground.
'Comment: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

125

TMS 3112 JC, NC; TMS 3122 JC, NC; TMS 3123 JC, NC
HEX 32-81T STATIC SHIFT REGISTERS
recommended operating conditions
PARAMETER

MIN

NOM

MAX

UNIT

Supply voltage, VGG

-11

-12

-13

V

Supply voltage, VSS

4.75

5

5.25

V
V

High-level input voltage, VI H

VSS -1.3

VSS

High-level clock voltage, VIH(q.,)

VSS -1.3

VSS

V

Low-level input voltage, V I L

V~~-4

V

Low-level clock voltage, VI L(q.,)

VSS-4

V

5000

ns

5000

ns

Clock pulse transition time,low-to-high-level, tTLH(q.,)
Clock pulse transition time, high-to-Iow-Ievel, tTHUt»
Pulse width, clock high, tw(q.,H)

300

Pulse width, clock low, tw(q.,Ll

150

Recirculate pulse width, tw(rec)

250

Data setup time, tsu(da)
Recirculate setup time, tsu(rec)
Data hold time, thIda)

II

Recirculate hold time, th(rec)
Clock frequency, f
Operating free-air temperature, T A

electrical characteristics under nominal operating conditions, TA
PARAMETER
VOH
VOL

Low-level output voltage

II

Input current (all inputs)

IGG

Supply current from VGG

ISS
Po

50000

RL = 7.5 kn to VGG

ns

60

ns

120

ns

60

ns

100

ns

0

2

-25

85

Typt

MIN

0.6

VI =OV
Load = 1 TTL gate (see Note 2),
TA = 25°C

Load = 1 TTL gate (see Note 2),
f = 1 MHz,

TA = 25°C

f = 1 MHz,

°c

UNIT

TA = 25°C

V

-500

nA

-15

-25

mA

25

30

mA

425

500

mW

Load = 1 TTL gate (see Note 2),

Power dissipation

MHz

V

IOL"" -1.6 mA

Supply current from VSS

MAX

VSS-1

RL = 7.5 kn to VGG,

f= 1 MHz,

ns
ns

= -25° C to 85° C (unless otherwise noted)

TEST CONDITIONS

High-level output voltage

00

Ci

Input capacitance, all inputs except clock

VI = VSS,

f= 1 MHz

5

7

pF

Ci(¢)

Clock input capacitance

VI(q.,) = VSS,

f = 1 MHz

6

7

pF

t All typical values are at T A = 25° C.

NOTE 2: For final test purposes. a worst-case TTL load is simulated by a load of 2.7 kn and a capacitance of 10 pF.

switching characteristics under nominal operating conditions, T A
PARAMETER

= -25°C to 85°C (unless otherwise noted)

TEST CONDITIONS

MIN

Typt

MAX

350

440

ns

350

440

ns

180

250

ns

180

250

ns

UNIT

Propagation delay time, low-to-hightPLH
tpHL

level output from clock

RL = 7.5 kn to VGG.

Propagation delay time, high-to-Iow-

CL = 70 pF

level output from clock
Propagation delay time, low-to-high-

tpLH
tpHL

level output from output control

RL = 7.5 kn to VGG,

Propagation delay time, high-to-Iow-

CL = 70 pF

level output from output control

t All tYpical values are at T A

=

25° C.

57!

126

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TMS 3112 JC, NC; TMS 3122 JC, NC; TMS 3123 JC, NC
HEX 32-81T STATIC SHIFT REGISTERS

voltage waveforms

CLOCK INPUT

DATA INPUT

RECIRCULATE
CONTROL

VIH

..

VIL

I

GATE OUTPUT
CONTROL

VIH
VIL

I

VOH
DATA OUTPUT
VOL

NOTE: Measurements are made at 90% (high) and 10% (low) timing points.

15

PRINTED IN U.S A

TEXAS INSTRUMENTS
INCOf{PORATED

TEXAS INSTRUMENTS RESERVES THE RIGHT TO MAKE CHANGES AT ANY TIME
IN ORDER TO IMPROVE DESIGN AND TO SUPPLY THE BEST PRODUCT POSSIBLE.

POST OFFICE BOX 5012

•

OALLAS. TEXAS 75222

127

MOS
LSI

TMS 3113 JC, NC; TMS 3114 JC, NC
DUAL 133-, 128-81T STATIC SHIFT REGISTERS
BULLETIN NO. DL-S 7512262. MAY 1975

•
•
•
•
•
•
•

DC to 2-MHz Operation

16-PIN CERAMIC AND PLASTIC
DUAL-IN-LiNE PACKAGES
(TOP VIEW)

Static Configuration
Single TTL-Compatible Clock
Inputs and Outputs Fully TTL-Compatible
On-Chip Recirculate Logic
Power Supplies ... 5 V, -12 V
Low-Threshold Technology

description
The TMS 3113 JC, NC and TMS 3114 JC, NC are
dual static shift registers with independent input,
output, and recirculate controls for each register. A
single-phase clock is common to both registers. The
clock and all inputs can be driven from Series 74 TTL
circuits and each output can drive one Series 74 TTL
circuit.

..

No Connection

16

No Connection

Input A

2

15

Input B

Rec Input A

3

14

Rec Input B

Rec Control A

4

13

Rec Control B

Output A

5

12

Output B

VDD

6

11

VGG

VSS

7

10

No Connection

8

9

No Connection

Clock Input

Three clocks are generated internally. Cross-coupled inverters (flip-flops) are employed to implement each bit storage
location. This static design allows data rates from dc to 2 MHz and long-term data storage.
P-channel enhancement-type low-threshold processing has been employed to reduce power dissipation and provide
simple interfaces with bipolar circuits.
The TMS 3113 and TMS 3114 are offered in 16-pin dual-in-line ceramic (JC suffix) or plastic (NC suffix) packages
designed for insertion in mounting-hole rows on 300-mil centers. These devices are characterized for operation from
-25°C to 85°C.
.

applications
The TMS 3113 and TMS 3114 can be used in printers, peripherals, and display equipment.

operation
Transfer of data into and out of the shift register occurs on the low-to-high transition of the clock. Input data must be
set up a minimum time before the low-to-high transition and must be held for a minimum time after that transition.
For long-term data storage, the clock must be maintained high, and in this mode the recirculate and data input levels
may change without affecting the data output levels.
Data recirculation is accomplished by externally connecting each output to the corresponding input. Recirculate occurs
on the low-to-high clock transition with the recirculate control high. The recirculate control level must be set up a
minimum time before this transition and held a minimum time after the transition. Data is entered with the recirculate
control low. During recirculation, data is continuously available at the outputs and data inputs are inhibited.

57E

128

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012 •

DALLAS. TEXAS 75222

TMS 3113 JC, NC; TMS 3114 JC, NC
DUAL 133-, 128-81T STATIC SHIFT REGISTERS
functional block diagram

---------,

REC INPUT A ---'-------r-""I
REC CONTROL A--I----+--~

1-_ _--1-_ _ OUTPUT A

INPUT A
REC INPUT B - - - - - - - - - /
REC CONTROL B --I----+--~
/------'--- OUTPUT B
INPUT B - - 1 - - - - - - 1

I

L------

1

----

VOO

II

CLOCK INPUT

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)*
-6 V to 0.3 V
-20 V to 0.3 V
-15 V to 0.3 V
-15 V to 0.3 V
-25°C to 85°C
-55°C to 150°C

Supply voltage VDD (see Note 1)
Supply voltage V GG (see Note 1)
Clock input voltage (see Note 1)
Data input voltage (see Note 1)
Operating free-air temperature range
Storage temperature range

NOTE 1: Under absolute maximum ratings, voltage values are with respect to the normally most-positive supply, VSS (substrate). Throughout
the remainder of this data sheet voltage values are with respect to VOO'
• Comment: Stresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. Th is is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliabilitY.

recommended operating conditions
PARAMETER

MIN

NOM

MAX

Supply voltage, VGG

-11

0
-12

-13

V

Supply voltage, VSS

4.75

5

5.25

V

Supply voltage, VOO

High-level input voltage, VIH

3.5

High-level clock input voltage, VI H (cp)

3.5

UNIT
V

V
V

Low-level input voltage, VIL

0.6

V

Low-level clock input voltage, VI L(cp)

0.6
5

V
}J.s

5

}J.s

00

ns

0.02
0.02

Clock pulse transition time, low-to-high-Ievel, tTLH(cp)
Clock pulse transition time, high-to-Iow-Ievel, tTH L(cp)

Data setup time, tsu(da)

330
130
100

Recirculate setup time, tsu(rec)

100

ns

Data hold time, th(da)

100
150

ns

Pulse width, clock high, tw(cpH)
Pulse width, clock low, tw(L)

Recirculate hold time, th (rec)
Clock frequency, f
Operating free-air temperature, T A

50000

ns
ns

ns

0

2

-25

85

MHz

°c

;75

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

129

TMS 3113 JC, NC; TMS 3114 JC, NC
DUAL 133-, 128-81T STATIC SHIFT REGISTERS
electrical characteristics under nominal operating conditions, T A
VOH
VOL
II
IGG
ISS
PD
Cj
Ci(¢)

PARAMETER
High-level output voltage
Low-level output voltage
Input current (all inputs)
Supply current from VGG
Supply current from VSS
Power dissipation
Input capacitance, all inputs except clock
Clock input capacitance

= -25°C to 85°C (unless otherwise noted)

TEST CONDITIONS
IOH = 0.2 mA
IOL = 1.6 mA
VI =0.6V
Load = 1 TTL gate (see Note 2)
Load - 1 TTL gate (see Note 2)
Load = 1 TTL gate (see Note 2)
VI =5V,

MIN
4

Typt

0.5
-500

-17
32
360
8
9

f = 1 MHz
f = 1 MHz

VI(¢)=5V,

MAX

12
13

UNIT
V
V
nA
mA
mA
mW
pF
pF

t All typical values are at T A = 25°C.
NOTE 2: For final test purposes, a worst-case TTL load is simulated by a load of 2.7 k.!1 and a capacitance of 10 pF.

switching characteristics under nominal operating conditions, T A = -25°C to 85°C (unless otherwise noted)

tpLH

II

tpHL

PARAMETER
Propagation delay time, low-to-high-Ievel
output from clock
Propagation delay time, high·to-Iow-Ievel
output from clock

TEST CONDITIONS
1 Series 74 TTL Load + 10 pF
OR
10 M.!1 + 10 pF (MOS Load)
(see Note 3)

MIN

Typt

MAX

300

350

ns

300

350

ns

UNIT

t All typical values are at T A = 25°C.

NOTE 3: For final test purposes, a worst-case TTL load is simulated by a load of 2.7 k.!1 and a capacitance of 10 pF. A worst-case MaS load is
simulated by a load of 10 M.!1 and 10 pF. All loads are connected between output and VSS'

voltage waveforms
VIH(¢)
CLOCK

tsu(da)

I~

---~

DATA INPUT

~I~

~I

K---------K----------

i

thida)

. +- -----~ .
I

tsu(rec)

,...

~ I~

~I

---)1 :
I

RECIRCULATE
CONTROL

th(rec)

, i=...------4

.

I

I4tPLH~

-------TY.
I

DATA OUTPUT

,

~----

I,...tPHL~
NOTE: Timing points are at 90% (high) and 10% (low) unless otherwise noted.

PRINTED IN U.S.A

130

57

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TEXAS INSTRUMENTS RESERVES THE RIGHT TO MAKE CHANGES AT ANY TIME
IN ORDER TO IMPROVE DESIGN AND TO SUPPLY THE BEST PRODUCT POSSIBLE.

MOS
LSI

TMS 3120 JC, NC; TMS 3121 JC, NC
QUADRUPLE 80-, 64-BIT STATIC SHIFT REGISTERS
BULLETIN

•

DC to 2.5-MHz Operation

•

Static Configuration

•

Single TTL-Compatible Clock

•

Inputs and Outputs Fully TTL-Compatible

•

Push-Pull Output Buffers

•

On-Chip Recirculate Logic

•

Power Supplies ... 5 V, -12 V

•

Low-Threshold MOS Technology

NO.

DL-S

7512267,

MAY

1975

16-PIN CERAMIC AND PLASTIC
DUAL~N~INEPACKAGES

(TOP VIEW)
OUT A

description

16 VSS

RECA

2

15

INA

3

14 REC D

OUTB

4

13 OUTD

REC B

5

12 VGG

INB

6

11

CLOCK

OUTC

7

10

INC

VCC

8

9

IN D

RECC

II

The TMS 3120 and TMS 3121 are quad 80-bit and quad 64-bit shift registers with independent inputs, outputs, and
recirculate controls for each register. A single-phase clock is common to all registers. The clock and data inputs can be
driven from Series 74 TTL circuits and the push-pull output buffers can drive one TTL load or low-level MOS loads
without external pull-up resistors.
Cross-coupled inverters (flip-flops) are employed to implement each bit storage location. This static design allows input
data rates from dc to 2.5 MHz and long-term data storage.
P-channel enhancement-type low-threshold processing has been employed to reduce power dissipation and provide
simple interface with bipolar circuits.
The TMS 3120 and TMS 3121 are offered in 16-pin dual-in-line ceramic (JC suffix) or plastic (NC suffix) packages
designed for insertion in mounting-hole rows on 300-mil centers. These devices are characterized for operation from
-25°C to 85°C.

applications
The TMS 3120 can be used in card punch, key-to-tape, key-to-disk, printer, and CRT display equipment for both 40and 80-column applications. The TMS 3121 is used in general purpose buffer memories.

operation
Transfer of data into and out of the shift register occurs on the h igh-to-Iow transition of the clock. Input data must be
set up a minimum time before the high-to-Iow clock transition and must be held for a minimum time after that
transition. For long term data storage, the clock must be maintained low, and in this mode the recirculate and data
input levels may change without affecting the data output levels.
Recirculate occurs on the high-to-Iow clock transition with the recirculate control high. The recirculate control must be
set up a minimum time before this transition and held a minimum time after the transition. Data is entered with the
recirculate control low. During recirculation, data is continuously available at the output and the data input is
inhibited.

575

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

131

TMS 3120 JC, NC; TMS 3121 JC, NC
QUADRUPLE 80-, 64-BIT STATIC SHIFT REGISTERS
functional block diagram

j------------j

t-

OUT A

RECA ---.-,-~

VSS

IN D

REt D

OUTB

RECB-_..-1.

INB---~~

CLOCK

OUTC

IN C

I

I

RECC

VDD--,

fL

II

___ _

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)*
-20 V to 0.3 V
-20 V to 0.3 V
-20 V to 0.3 V
-20 V to 0.3 V
-25°C to 85°C
-55°C to 150°C

Supply voltage, VDD (see Note 1)
Supply voltage, VGG (see Note 1)
Clock input voltage (see Note 1)
Data input voltage (see Note 1 )
Operating free-air temperature range
Storage temperature range
NOTE

1: Under absolute maximum ratings, voltage values are with respect to the normally most-positive supply, VSS (substrate). Throughout
the remainder of this data sheet voltage values are with respect to VOO'
'Comment: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.

recommended operating conditions
PARAMETER

MIN

NOM

MAX

Supply voltage, VGG

-11

0
-12

-13

Supply voltage, VSS

4.75

5

5.25

Supply voltage, VDD

High-level input voltage, VIH

VSS -1.6

High-level clock input voltage, VIH(cp)

VSS -1.6

UNIT
V
V
V
V
V

Low-level input voltage, VIL

0.8

Low-level clock input voltage, VI L(cp)

0.8

V

10

fJ.S

10
100000

ns

Clock pulse transition time, low·to-high-Ievel, tTLH(dl)
Clock pulse transition time, high-to-Iow·level, tTH L(cp)
Pulse width, clock high, tw(et>H)

V

fJ.S

Pulse width, clock low, tw(cpL)

200
200

Data setup time, tsu(da)

190

ns

Recirculate setup time, tsu(rec)

190

ns

Data hold time, th(da)

90

ns

Recirculate hold time, th(rec)

90

Clock frequency, fet> (see Note 2)

0
-25

Operating free-air temperature, T A
NOTE 2: For cascading, data input frequency

=2

00

ns

ns

2.5

MHz

85

°C

M Hz maximum.
575

132

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TMS 3120 JC, NC; TMS 3121 JC, NC
QUADRUPLE 80-, 64-BIT STATIC SHIFT REGISTERS
electrical characteristics under nominal operating conditions, T A = -25° C to 85° C (unless otherwise noted)
PARAMETER

TEST CONDITIONS

MIN

Typt

VOH

High-level output voltage

IOH =

100~A

VSS-1 VSS -0.5

VOL

LOW-level output voltage

IOL = 1.6 mA

0.2

II

Input current (all inputs)

VI = 0

IGG

Supply current from VGG

ISS

Supply current from VSS

Po

Power dissipation

Load = 1 TTL gate (see Note 3)
f = 1 MHz,

TA=25°C

Load = 1 TTL gate (see Note 3)
f = 1 MHz,

TA=25°C

MAX

UNIT
V

0.4

V

-0.1

~A

-10

-15

mA

30

35

mA

355

mW

Load = 1 TTL gate (see Note 3)
f= 1 MHz,

TA = 25°C

Ci

Input capacitance, all inputs except clock

VI = VSS,

f= 1 MHz

3.5

5

pF

Ci(H)

300

00

ns

Pulse width, clock low, tw(ct>U

100

1000000

ns

Recirculate pulse width, tw(rec)

125

ns

80

ns

0.02

Clock pulse transition time, high-to-Iow level, tTHL(ct»

Data setup time, tsu(da)

100

ns

Data hold time, th(da)

80

ns

Recirculate hold time, th(rec)

25

Recirculate setup time, tsu(rec)

Clock frequency, fct>

0
-25

Operating free-air temperature, T A

ns

2.5
85

MHz

°c

575

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

135

TMS 3126, 3127, 3128, 3129, 3130, 3131, 3132 LC, NC
DUAL 96-, 100-, 128-, 132-, 133-, 136-, 144-81T STATIC SHIFT REGISTERS
electrical characteristics under nominal operating conditions, T A = -25°C to 85°C
(unless otherwise noted)
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage

10H = 0.2 rnA

VOL

Low-level output voltage

10L = 1.6 rnA

II

Input current (all inputs)

VI = 0.8 V

MIN

Typt

MAX

4

UNIT
V

0.4

V

-500

nA

lOS

Short-circuit output current

Vo = 0 V,

VGG = -11 V

-10

rnA

IGG

Supply current from VGG

f = 2.5 MHz,

1 TTL load (see Note 2)

-22

-30

rnA

Po

Power dissipation

f = 2.5 MHz,

1 TTL load (see Note 2)

374

510

mW

I nput capacitance, all inputs
Ci

except clock
Clock input capacitance

Ci(cP)

VI = 5 V,

f = 1 MHz

3.5

5

pF

VI(cJ» =5V,

f = 1 MHz

3.5

5

pF

= 25° c.
NOTE 2: For test purposes, a TTL load is simulated by a load of 2.7

t All typical values are at T A

a

kn

and 20 pF between the output and VSS.

switching characteristics under nominal operating conditions, TA = _25° C to 85° C
PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Propagation delay time, low-to-hightpLH

level output from clock
Propagation delay time, high-to-Iow-

tpHL

250

ns

250

ns

Load = 1 TTL gate (see Note 3)

level output from clock

NOTE 3: For test purposes, a TTL load is simulated by a load of 2.7

kn

and 20 pF between the output and VSS.

voltage waveforms

CLOCK

I

I

r-+th(da)

~""""-I--!----INPUT DATA

II J
I. IT .1

I

'-

tsu(rec)

t- ~·4

_-1

I

tw(rec)

~

RECIRCULATE
CONTROL

I

th(rec)

L __ ,I

__r.n'.LH

OUTPUT DATA

_____ _

~~ ______ _

_________1'-- - -

-x-------

NOTE: All timing measurements are made at 10% or 90% points.

PRINTED IN U.S A

136

575

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TEXAS INSTRUMENTS RESERVES THE RIGHT TO MAKE CHANGES AT ANY TIME
IN ORDER TO IMPROVE DESIGN AND TO SUPPLY THE BEST PRODUCT POSSIBLE.

MOS
LSI

TMS 3133 NC
1024-81T STATIC SHIFT REGISTER
BULLETIN NO. DL-S 7512264, MAY 1975

•

DC to 2-MHz Operation

•

Static Configuration

•

Single TTL-Compatible Clock

•

Inputs and Outputs Fully TTL-Compatible

•

Push-Pull Output Buffers

•

Power Supplies ... 5 V, -12 V

•

MOS Low-Threshold P-Channel Technology

8-PIN PLASTIC
DUAL-IN-LiNE PACKAGE
(TOP VIEW)

OUTPUT

8

VSS

7

INPUT 2

INPUT SELECT

3

6

CLOCK

VDD

4

5

INPUT 1

description
The TMS 3133 NC is a 1024-bit static shift register designed with on-chip pull-up resistors on the inputs and the
low-capacitance clock. The input can be driven directly from Series 74 TTL circuits without the use of external
components. The push-pull output buffer will drive a TTL or MOS load without external components.

..

Two input terminals are provided. Data can be entered in either input depending on the state of the input select
control. Cross-coupled inverters (flip-flops) are employed to implement each bit storage location. This static design
allows input data rates from dc to 2 MHz and long-term data storage.
lon-implant depletion-type P-channel low-threshold processing has been employed to reduce power dissipation and
provide simple interfaces with bipolar circuits.
The TMS 3133 NC is offered in an 8-pin plastic (NC suffix) package designed for insertion in mounting-hole rows on
300-mil centers. The device is characterized for operation from -25°C to 85°C.

applications
The TMS 3133 NC is ideally suited for applications requiring a long serial memory where ease of use and low overhead
circuitry are required. These applications include low-cost sequential-access memories, CRT refresh memories, drum
memory replacements, and delay lines.

operation
Transfer of data into and out of the shift register occurs on the high-to-Iow transition of the clock. Input data must be
set up a minimum time before the high-to-Iow transition and must be held for a minimum time after that transition.
For long-term data storage, the clock must be maintained low, and in this mode the input select and data input levels
may change without affecting the data output levels.
Data recirculation is accomplished by externally connecting the output to either input. Recirculate occurs on the
high-to-Iow clock transition with the input select control set to enter data at the input connected to the output. The
input select control level must be set up a minimum time before this transition and held a minimum time after the
transition. During recirculation, data is continuously available at the output and the unselected data input is inhibited.

575

PRELIMINARY DATA SHEET:
Supplementary data may be
published at a later date.

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

137

TMS 3133 NC
1024-81T STATIC SHIFT REGISTER
functional block diagram

--,

,---

I

l"-

OUTPUT

VSS

I
I

I

I

I

I

I

----i

INPUT 2

CLOCK

INPUT SELECT
I

I
I

I

I

II

--l

INPUT 1

I
_..J

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)*
-20 V to 0_3 V
-20 V to 0_3 V
-20 V to 0_3 V
-20 V to 0_3 V
-25°C to 85°C
-55°C to 150°C

Supply voltage, VDD (c;ee Note 1)
Supply voltage, V GG (see Note 1)
Clock input voltage (see Note 1)
Data input voltage (see Note 1)
Operating free-air temperature range
Storage temperature range

NOTE 1: Under absolute maximum ratings, voltage values are with respect to the normally most-positive supply, Vss (substrate)_ Throughout
the remainder of this data sheet voltage values are with respect to VDD'
·Comment: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.

recommended operating conditions
MIN

NOM

MAX

Supply voltage, VGG

-11

0
-12

-13

V

Supply voltage, VSS

4.75

5

5.25

V

PARAMETER
Supply voltage, VDD

High-level input voltage, VIH (see Note 2)

V

VSS -1.4

V

0.8
10

Low-level input voltage, VI L
Clock pulse transition time, low-to-high-Ievel, tTLH(ct»
Clock pulse transition time, high-to-Iow-Ievel, tTLH(ct»
Pulse width, clock high, tw(ct>H)

200

Pulse width, clock low, tw(U

200

Data setup time, tsu(da)

100
100
100
100
0
-25

Input select setup time, tsu(sel)
Data hold time, thIda)
Input select hold time, th(sel)
Clock frequency, fq,
Operating free-air temperature, T A

UNIT

V
J..IS

10
100000

J..IS

00

ns

ns
ns
ns
ns
ns

2

MHz

85

°c

NOTE 2: TTL compatibility of all inputs is ensured by incorporation of internal pull-up resistors on the chip.

57!

138

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

OALLAS. TEXAS 75222

TMS 3133 NC
1024-81T STATIC SHIFT REGISTER
electrical characteristics under nominal operating conditions, T A = _25° C to 85° C
(unless otherwise noted)
PARAMETER

MIN

Typt

VSS -1

VSS -005

TEST CONDITIONS

VOH

High-level output voltage

IOH = 100J,LA

VOL

Low-level output voltage

IOL = 106 rnA

II

Input current (all inputs)

IGG

Supply current from VGG

f = 1 MHz,

ISS

Supply current from VSS

1 Series 74 TTL Load (see Note 3)

PD

Power dissipation

TA= 2S oC

Ci

Input capacitance

VI = VSS,

VI =0 V,

002
VSS = 5 V,

UNIT
V

0.4

V

-008

rnA

-10

-14

rnA

35

50

rnA

250

420

mW

5

7

TA=25°C
Duty cycle = 50%,

MAX

f = 1 MHz

pF

t All typical values are at T A = 25°Co
NOTE 3:

For final test purposes, a worst-case TTL load is simulated by a load of 207 kn and a capacitance of 10 p Fo

switching characteristics under nominal operating conditions, T A
PARAMETER

TEST CONDITIONS

Propagation delay time, low-to-high-Ievel
tpLH
tpHL
NOTE

MIN

MAX

110

350

ns

110

350

ns

1 Series 74 TTL Load + 10 pF,
OR

output from clock

..

= -25° C to 85° C

Propagation delay time, high-to-Iow-Ievel

10 Mn + 10 pF (MOS Load),

output from clock

(see Note 4)

UNIT

I

4: For final test purposes, a worst-case TTL load is simulated by a load of 207 kn and a capacitance of 10 pFo A worst-case MaS load is
simulated by a load of 10 Mn and 10 pFo All loads are connected between output and VSSo

voltage waveforms

d \.--

:::,::-_VI..---N /
tTLH(H)
Pulse width, clock low, tw(U
Width of clear pulse, tw(clrl
Clear inactive-state setup time, tsu(clrU
Data setup time, tsu(da)
Recirculate setup time, tsu(ree)
Data hold time, thIda)
Recirculate hold time, th (ree)
Clock frequency, f
Operating free-air temperature, T A

UNIT
V

0

Supply voltage, VGG

NOTE

NOM

V
V
V

0.8
10
10
100000
00

V
J.LS
J.LS

ns
ns
J.LS

ns
ns
ns
ns
ns

1.5
85

MHz

°c

2: TTL compatibilitY of all inputs is ensured by the incorporation of internal pull-up resistors on the chip.

75

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

141

TMS 3135, 3137, 3138, 3139, 3140 JC, NC
9- BY 80-, 100-, 128-, 132-, 133-BIT STATIC SHIFT REGISTERS
electrical characteristics under nominal operating conditions, TA = -25°C to 85°C (unless otherwise noted)
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage

VOL

Low-level output voltage

= 100 J.lA
IOL = 1.6 rnA

II

Input current (all inputs)

VI -0

IOH

Load
IGG

Supply current from VGG

f

= 1 TTL gate

= 1 MHz,

Duty cycle

MIN

Typt

VSS-l

VSS -0.5

MAX

UNIT
V

0.6

0.4
-0.5

-0.8

V
rnA

-9

-12

rnA

45

60

rnA

330

450

mW

(see Note 3),

TA

= 25°C,

= 50%

= 1 TTL gate (see Note 3),
= 1 MHz,
TA = 25°C,
Duty cycle = 50%
Load = 1 TTL gate (see Note 3),
f = 1 MHz,
TA = 25°C,
Duty cycle = 50%
f = 1 MHz
VI = VSS,
f = 1 MHz
VI(CP) = VSS,
Load

II

ISS

Supply current from VSS

Po

Power dissipation

f

Ci

Input capacitance, all inputs except clock

Cj(cp)

Clock input capacitance

5

7

pF

5

7

pF

t All typical values are at T A = 25°C and nominal operating conditions.
NOTE 3: For test purposes, a TTL load is simulated by a load of 2.7 kn and 20 pF between the output and VSS'

switching characteristics under nominal operating conditions, T A = -25° C to 85° C
PARAMETER

TEST CONDITIONS

Propagation delay time, low-to-hightPLH

level output from clock
Propagation delay time, high-to-Iow-

tPHL

level output from clock

1 Series 74 TTL load

+ 10 pF

MIN

MAX

UNIT

110

550

ns

110

550

ns

or
RL

= 10 Mn, CL = 10 pF

(MOS load)

voltage waveforms

CLOCK

INPUT DATA

RECIRCULATE
CONTROL
VIL
VIH
MASTER CLEAR
VIL
VOH
OUTPUT DATA
VOL
NOTE: For the clock input and output data, timing points are 90% (high) and 10% (low). All other timing points are 50%.

PRINTED IN US A

142

57!

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TEXAS INSTRUMENTS RESERVES THE RIGHT TO MAKE CHANGES AT ANY TIME
IN ORDER TO IMPROVE DESIGN AND TO SUPPLY THE BEST PRODUCT POSSIBLE.

TMS 3401 LC, NC
512-81T DYNAMIC SHIFT REGISTER

MOS
LSI

MAY 1975

•

1-kHz to 5-MHz Operation

•

Dynamic Configuration

•

Inputs and Outputs Fully TTL-Compatible

TO-100 HERMETICALLY-SEALED PACKAGE
(TOP VIEW)
CLOCK 1

•

Push-Pull Output Buffers

•

Power Supplies ... 5 V, -12 V

•

Low-Threshold Technology

description
The TMS 3401 LC, NC is a single 512-bit dynamic
shift register designed for high speed and low power
dissipation. The input and output are fully
compatible with Series 74 TTL and require no
external resistors.

..

NO CONNECTION

I

16-PIN PLASTIC DUAL-IN-LiNE PACKAGE
(TOP VIEW)

The TMS 3401 is offered in 10-pin TO-l00 (LC
suffix) and 16-pin dual-in-line plastic (NC suffix)
packages. The 16-pin package is designed for insertion
in mounting-hole rows on 300-mil centers.

I

IN

16

VSS

R2

15

R1

14

NO CONNECTION

CLOCK 2

applications

3

NO CONNECTION

The TMS 3401 can be used in display, delay line, and
long serial storage applications.

functional block diagram

NO CONNECTION

CLOCK 1

5

VDD

6

NO CONNECTION

7

OUT

8

12

NO CONNECTION
NO CONNECTION

10

NO CONNECTION
VGG

,----- -- - - ---- - --I
I

I

VDD

I

I

INPUT

I

CLOCK 1

512-BIT REGISTER

I

I

I

I
I
L __

I

OUTPUT

I

I
CLOCK 2

BUFFER

I

I
6kn ~~MINAL
1.5 kjf}J"OMINAL

vv

-

-- -

-----

I

:
_J

VGG
R2
R1

A complete data sheet may be obtained by writing directly to:
Marketing and Information Services
Texas Instruments Incorporation
P_O_ Box 5012 MS 308
Dallas, Texas 75222
575

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

143

MOS
LSI

TMS 3409 JC, NC; TMS 3417 JC, NC
QUADRUPLE 80-, 64-BIT DYNAMIC SHIFT REGISTERS
BULLETIN NO. DL-S 7512266, MAY 1975

•

10-kHz to 5-MHz Operation

•

Dynamic Configuration

•

Single TTL-Compatible Clock

16-PIN CERAMIC AND PLASTIC
DUAL-IN-LiNE PACKAGES
(TOP VIEW)

•

Inputs and Outputs Fully TTL-Compatible

OUT A

•

On-Chip Recirculate Logic

REC A

•

Power Supplies ... 5 V, -12 V

IN A

•

MOS Low-Threshold Self-Aligned-Gate

16

VSS

2

15

IN D

3

14

REC D

OUT B

Technology

REC B

description

OUT D
5

12

IN B

The TMS 3409 and TMS 3417 are quad 80-bit and
quad 64-bit shift registers, respectively, with
independent inputs, outputs, and recirculate controls
for each register. A single external clock signal
generates two internal clock phases to each register.
The clock and all inputs can be driven from Series 74
TTL circuits and all outputs can drive TTL circuits
without the use of external resistors.

II

CLOCK

OUT C
VDD

VGG

10

8

9

IN C
REC C

P-channel enhancement-type low-threshold processing with self-aligned gates has been employed to reduce power
dissipation and provide simple interfaces with bipolar circuits.
The TMS 3409 and TMS 3417 are offered in 16-pin dual-in-line ceramic (JC suffix) or plastic (NC suffix) packages
designed for insertion in mounting-hole rows on 300-mil centers. These devices are characterized for operation from
-25°C to 85°C.

applications
The TMS 3409 and TMS 3417 can be used in terminals, CRT displays, key-to-tape, key-to-disk, and card-punch
applications.

operation
Transfer of data into and out of the shift register occurs on the high-to-Iow transition of the clock with output data
becoming valid after a specified propagation delay following that transition. Input data must be set up a minimum time
before the high-to-Iow transition and must be held for a minimum time after that transition.
Recirculate occurs on the high-to-Iow clock transition with the recirculate control high. The recirculate control level
must be set up a minimum time before this transition and held a minimum time after the transition. Data is entered
with the recirculate control low. During recirculation, data is continuously available at the outputs and data inputs are
inhibited.

575

144

TEXAS INCORPORATED
(NSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TMS 3409 JC, NC; TMS 3417 JC, NC
QUADRUPLE 80-, 64-BIT DYNAMIC SHIFT REGISTERS

,L__

functional block diagram

vss

IN D REC D

I
I
I
I

I
I
I
I
I
I
I

..

L_
OUT B

RECA

REC B

OUT A
IN A

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)*
Supply voltage, VDD (see Note 1)
Supply voltage, VGG (see Note 1)
Clock input voltage (see Note 1)
Data input voltage (see Note 1)
Operating free-air temperature range
Storage temperature range

-20 V to 0.3 V
-20 V to 0.3 V
-20 V to 0.3 V
-20 V to 0.3 V
-25°C to 85°C
-55°C to 150°C

NOTE 1: Under absolute maximum ratings, voltage values are with respect to the normally most-positive supply, VSS (substrate). Throughout
the remainder of this data sheet voltage values are with respect to VOO .
• Comment: Stresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliabilitY.

recommended operating conditions
PARAMETER

MIN

NOM

MAX

-11
4.75

0
-12
5

-13
5.25

Supply voltage, VDD
Supply voltage, VGG
Supply voltage, VSS

UNIT
V
V
V

High-level input voltage, VIH

VSS -2

VSS

V

High-level clock input voltage, VIH(¢)

VSS -2

VSS

V

0
0
75
125
50
200
50
100
0.01
-25

0.8
0.4
50000
50000

V

Low-level input voltage, V I L
Low-level clock input voltage, VI L(¢)
Pulse width, clock high, tw(¢H)
Pulse width, clock low, tw(U
Data setup time, tsu(da)
Recirculate setup time, tsu(rec)
Data hold time, th(da)
Recirculate hold time, th(rec)
Clock frequency, f¢
Operating free-air temperature, T A

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

V
ns
ns
ns
ns
ns
ns

5
85

MHz

°c

145

TMS 3409 JC, NC; TMS 3417 JC, NC
QUADRUPLE 80-, 64-BIT DYNAMIC SHIFT REGISTERS
electrical characteristics under nominal operating conditions, T A = -25° C to 85° C
(unless otherwise noted)
VOH

MIN

Typt

MAX

UNIT

VSS-1

VSS -0.5
0.3

VSS
0.4

V

TEST CONDITIONS

PARAMETER
High-level output voltage

IOH = 0.5 rnA

VOL
II

Low-level output voltage

IOL = 1.6 rnA

Input current (all inputs)

IGG

Supply current from VGG

VI =0
Load = 1 TTL gate (see Note 2),
f = 1 MHz

ISS

Supgly current from VSS

Load = 1 TTL gate (see Note 2),
f = 1 MHz
Load = 1 TTL gate (see Note 2),

Po

Power dissipation

Ci

Input capacitance, all inputs except clock

Ci(l/l)

Clock input capacitance

f = 1 MHz

-100

V
nA

-10

-12

rnA

33

47

rnA

285

400

mW

VI = VSS,

f = 1 MHz

10

pF

VI(I/l) = VSS,

f - 1 MHz

25

pF

t All typical values are at T A = 25° C.
NOTE 2: For final test purposes, a worst-case TTL load is simulated by a load of 2.7 kil and a capacitance of 10 pF.

switching characteristics under nominal operating conditions, T A = -25°C to 85°C
(unless otherwise noted)

II

tpLH
tpHL
tTLH
tTHL

PARAMETER
Propagation delay time, low-to-high-Ievel

TEST CONDITIONS
1 Series 74 TTL Load + 10 pF

output from clock
Propagation delay time, high-to-Iow-Ievel

OR
10 Mil + 10 pF (MOS Load)
(see Note 3)

output from clock
Transition time, low-to-high-Ievel output
Transition time, high-to-Iow-Ievel output

t All typical values are at T A

MIN

Typt

MAX

100

160

ns

160

ns

60

ns

50

ns

100

1 Series 74 TTL Load + 10 pF
(see Note 3)

:

UNIT

25° C.
NOTE 3: For final test purposes a worst-case TTL load is simulated by a load of 2.7 kn and a capacitance of 10 pF. A worst-case MaS load is
simu lated by a load of 10 Mil and 10 pF. All loads are connected between output and VSS'
=

voltage waveforms
VIH(I/l)

__--.J~i.~~:~J: t

~F-~_tT_H_L

'WI.Ll

CLOCK
VIL(I/l)

---1 ! r------------tsu(da)

VIH
INPUT DATA
VIL

_ _ _ _ _ _..J_

RECIRCULATE
CONTROL

I~

~14

thIda)

-1 _

1'-_

I~

~I

~14 ~I

___-_-_'...Jt_Lr--------- --tsu(rec)

VIH

_ __

VIL

!.---.I--

VOH

th(rec)

tpLH or tpHL

_-_-__-__-_-__-_-t_:_',.J( ____ _

OUTPUT DATA
VOL

NOTE 3. All timings are with respect to 50% points of transitions with the exception of clock transition times, which are measured at 90%
(high) and 10% (low!.

PRINTED IN U.S.A.

146

57!

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

TEXAS INSTRUMENTS RESERVES THE RIGHT TO MAKE CHANGES AT ANY TIME
IN ORDER TO IMPROVE DESIGN AND TO SUPPLY THE BEST PRODUCT POSSIBLE.

MOS
LSI

TMS 4024 JC, NC
9 X 64 DIGITAL STORAGE BUFFER (FIFO)
BULLETIN

•
•
•
•
•
•
•
•
•
•

64 Words of 9 Bits of Elastic Storage
TTL-Compatibility on All Inputs
Including Clocks
3-State Output Buffers
3 Control Inputs (Read, Write, Clear)
DC to 250-kHz Data Rate
Status Outputs (Full, Empty)
Synchronous and Asynchronous Operation
2-Cycle (4-l1s) Throughput
Long-Term Data Retention
Output Pins Directly Opposite
Corresponding Inputs

NO.

DL-S

7512268,

MAY

1975

28·PIN CERAMIC AND PLASTIC
DUAL-IN·LlNE PACKAGES
(TOP VIEW)
28

VDD

READ

2

27

VGG

CLOCK 2

3

26

VSS

OUT 1

4

25

IN1

OUT2

5

24

IN2

OUT3

6

23

IN3

OUT4

7

22

IN4

OUT5

8

21

IN5

OUT6

9

20

IN6

OUT7

10

19

IN7

OUT8

11

18

WRITE

description

..

IN8
IN9

17
OUT9 12
The TMS 4024 JC, NC is a first-in, first-out digital
16 CLOCK 1
FULL FLAG 13
storage buffer that will store up to 64 nine-bit words.
The major components of the device include a 9 x 64
.
15
CLEAR
EMPTY FLAG 14
dynamic RAM, three shift counters, and comparison
and control logic. A RAM-type organization results in
minimal ripple-through time. Data written at the
input when the RAM is empty is available at the output two clock cycles later. The input and output are completely
independent of each other. Input and output timing can be dependent on the clock timing (synchronous mode) or can
be operated independently (asynchronous mode). The dynamic RAM requires two-phase continuous clocking at a
specified minimum frequency. The clocks can be driven directly from TTL logic.

I

Low-threshold, thick-oxide, MOS p-channel enhancement·type technology is employed to allow interfacing with TTL
circuits without external components.
The TMS 4024 is suitable for many applications as an interface between systems clocked at different speeds and in
keyboard buffers, data concentrators, etc.
This device is offered in 28·pin dual-in-line ceramic (JC suffix) and plastic (NC suffix) packages designed for insertion in
mounting-hole rows on 600-mil centers. The TMS 4024 is characterized for operation from -25°C to 85°C.

operation (refer to diagram "basic internal operation")
The TMS 4024 will process data at any desired rate from dc to one-half the continuous clock frequency with every
other cycle used for automatic refresh. At a nominal 500-kHz clock rate the maximum data rate is 250 kHz. Data is
processed in parallel format, word by word.
Writing and reading may be done either synchronously or asynchronously in relation to the clocks. Asynchronous
operation is limited to data rates of less than one-third of the clock frequency. Read and write commands must have a
minimum separation of one clock cycle.
A positive-going transition at the read or write input is recognized as a command and must occur a minimum time
before the rise of clock 2.
A write command causes the data present at the input to be transferred into the buffer. Data·in must be valid for the
period during which clock 2 is low. For asynchronous operation, data-in must be valid for two periods after a write
command is given because a write command may be given at any time in relation to the clock.
575

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

147

TMS 4024 JC, NC
9 X 64 DIGITAL STORAGE BUFFER (FIFO)
operation (continued)
If both read and write inputs are brought to a high logic level, the read and write operations are disabled and the data
outputs float. The data present in the RAM is retained while the read and write operations are disabled.

A clear command will clear all contents of the digital storage buffer, except for the output latches. When the clear input
is brought to a high level, it invalidates all other commands. Completion of a clear operation is detected by a. high level
at the empty status output. The clear command should be synchronized with clock 2.
Status outputs (empty and full) are provided to avoid invalid operation and to facilitate cascading of the device. A high
level at the full status output invalidates write commands and a high level at the empty status output invalidates read
commands.

functional block diagram
DATA INPUTS
rr---------------~--------------~\
IN1 IN2 IN3 IN4 INS IN6 IN7 INS IN9

II

DATA AMPLIFIERS

CLOCK 1

WRITE
READ

CLOCK 2
EMPTY
FULL

Q1

02

03

04

..e.__

O_6__0_7__
0_S_0~~

DATA OUTPUTS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
~15

V to 0.3 V
-20 V to 0.3 V
-15 V to 0.3 V
-15 V to 0.3 V
-25°C to 85°C
-55°C to 150°C

Supply voltage, VDD (see Note 1)
Supply voltage, V GG (see Note 1)
Clock input voltage range (see Note 1)
Data input voltage range (see Note 1)
Operating free-air temperature range
Storage temperature range

NOTE 1: Under absolute maximum ratings voltage values are with respect to VSS (substrate). Throughout the remainder of this data sheet
voltage values are with respect to a floating ground.
575

148

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TMS 4024 JC. NC
9 X 64 DIGITAL STORAGE BUFFER (FIFO)
recommended operating conditions
MIN

NOM

MAX

UNIT

Supply voltage, VDD (see Note 2)

-4.75

-5

-5.25

V

Supply voltage, VGG (see Note 2)

-10.8

-12

-13.2

V

4.75

5

5.25

V

High·level input voltage, all inputs including clocks, VIH (see Note 3)

VSS -1.5

3.5

VSS

V

Low-level input voltage, all inputs including clocks, VIL (see Note 3)

-5.5

0

0.3

V

Clock pulse rise time, tr(2)
Read pulse width, tw(rd)
Write pulse width, tw(wr)

300

2000

Clear pulse width, tw(clr)

1

Delay time, clock 1 to clock 2, td(1-2)

300

Delay time, clock 2 to clock 1, td (2-1> 1 )

0

Delay time, clock 2 to clock 1, plus clock-l pulse width, td(2-1>1)

+ tw ( 1 )

ns

700

Clock-l pulse width, tw( 1 )

ns
ck cyc
ns
ns

300

1000

II

ns

Delay time, read to clock 2, td(rd-1>2)

400

600

Delay time, write to clock 2, td(wr-2)

400

600

Data setup time, tsu (da)

350

ns
ns

I

Data hold time, thIda)

ns
ns

350
0

250

kHz

Clock frequency, f

120

500

kHz

Operating free-air temperature, T A

-25

85

Data input frequency, fdata

°c

NOTES:
2. Voltage values are with respect to a floating ground.
3. The algebraic convention where the most negative limit is designated as minimum is used in this data sheet for logic voltage levels only.
4. Nominal timing is given for 500-kHz operation.

electrical characteristics under nominal operating conditions, T A
PARAMETER
VOH

High-level output voltage

VOL

Low-level output voltage

= -25

TEST CONDITIONS

= -0.5 rnA
IOL = 1.6 rnA (see Note 5)
IOH

0

0

C to 85 C (unless otherwise noted)
MIN

Typt

MAX

UNIT

VSS-l

VSS -0.5

VSS
0.4

V

1000

nA

0

Input current, all inputs including
II

clocks
Average supply current from VDD

IDD(avg)

(see Note 6)
Average supply current from VGG

IGG(avg)
Po

(see Note 6)
Power dissipation
Input capacitance, all inputs

Ci

including clock

V

MOS load

-8

rnA

MOS load

-6

rnA

MOS load

182

mW

7

pF

f

= 100 kHz

~

t All typical values are at T A = 25°C.
NOTES:
5. VOL is measured with a 1.5-k.l1 resistor in series with the output and includes the drop across the resistor.
6. Typical values of IOO(avg) and I GG(avg) are -25 mA and -8 mA at 85° C, each output driving a Series 74 TTL load with a 1.5-k.l1 resistor
in series, a 25% clock duty cycle (% of time clock is high) and a 75% output current dutY cycle (% of time outputs are low).
Typical values of IOO(avg) and IGG(avg) are -60 mA and -8 mA at 85°C. each output driving a Series 74 TTL load with no resistor in
series. a 25% clock duty cycle and all outputs low continuously.

575

TEXAS INSTRUMENTS
INCOHPORATED

POST OFFICE BOX 5012

•

OALLAS. TEXAS 75222

149

TMS 4024 JC. NC
9 X 64 DIGITAL STORAGE BUFFER (FIFO)
switching characteristics under nominal operating conditions, T A
PARAMETER

TEST CONDITIONS

t a(1 )

Access time from clock 1

t a (ct>2)

Access time from clock 2

tpLH

(unless otherwise noted)
Typt

MIN
950

25 pF in parallel.

1000

1.5 kn in series

level flag outputs from clock 2

MAX

UNIT
ns

1200

ns

400

1 Series 74 TTL load.

Propagation delay time. low-to-high

t All typical values a re at T A

= -25°C to 85°C

400

ns

= 25° C.

timing diagram and voltage waveforms

CLOCK 1.1
CLOCK 2. 2

a

____

---II

1\...-_ _ _---1

..:....


t----*tw lct>2)
tdlct>H>2) .,...,
1

J

WRITE

I-

.: td(Wr~2)tL...-

_ _ _ _ _ _ _ _ _ _-;-_-:-_ _ _ _ _-:--_ _

I---tw(wr)~

I

I

I

1\ I

.~

READ

tdlrd-2)t
- - - - - - - - 1- - - - - - : - 1--~l._tw(rd'~\......:...I----1- - -

DATA IN

.fl--t su Id a ,-.J
---.l~
----.

1

~thldaL..o,J\.
I-'~

I

DATA OUT

1

I-

1

1
~tpLH

~ta(11

.....
1 t..;:.a. ;.:Ict>-=2.:. . '_ __

t

-,
I

-F---

I

,I

FULL

1

tpLH

\

M-I

EMPTY

I

REFRESH

READ

REFRESH

WRITE
NOTE: Timing points are 90% (high) and 10% (low).

basic internal operation
¢1

2

(I\~----~I\~----~(\~
)I
1 :~____I____~r---\~

____~______~r___\~____~I

--t.*I__-Previously established

j+-R/W
commands I
I accepted I
I

address of R/W counters
j.- RAM
I outputs I
Iprecharged

-l

I---

I

I
1-..0 Internal..

i

read ~r write
signal
becomes I
true
I
"'1

..

_I_

---t.~I_RAM

_________

Address counters -----<_~If--+_
outputs 1
shifted to next address
1
I sampled
!.Full and..j
I
I on read
1 empty
I
I
1 operation
outputs
RAM outputs become ----.J sampled
valid for reading
I
1
OR
l+-tnterna~
Data written into RAM
refresh
1 starts
1

Next command
accepted

I

1

I
INPUT DATA
must be valid

I

·1

575

150

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

TMS 4024 JC, NC

9 X 64 DIGITAL STORAGE BUFFER (FIFO)
interface circuits
a)

TTL

1.5 kH*

5V

5V
TTL SN54174 SERI ES

TMS 4024

TTL SN54174 SERIES

".5 kl1 resistor OPtional - the presence of this resistor helps to reduce power dissipation in the TMS 4024 while driving TTL.
I

b)

II

MOS
-12V -5V

-5V

LJ}----I

~J

i

~J

!

~-~~i

5V

5V

-12V-5V

-5V

5V
MaS LOAD

TMS 4024

MaS DRIVE

TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIMES FOR FULL OR EMPTY
FLAGS FROM CLOCK 2 OR ACCESS TIME FROM
CLOCK 1 vs LOAD CAPACITANCE

SUPPLY CURRENT vs DUTY CYCLE
60

600

o
I
I
I
TA = 25 C, t w (rJ>l) = t w (¢2) = 1 ~s
Nominal operating conditions

I

TA

50 -TTL LOAD

500

=

I

0

I

- - -- ' -

~
:;

V

400

------

30

u

>

a.c.
::J

Vl

20

---

10

r-_-':::

IDD_

E

V

-- --f--

20
30
40
Clock Duty Cycle - %

./

J

200

r-=-J~

100

~~

IDD

~
TTL

IGG
IGG-

50

---

,V

11

0
10

?-

300

t=

0

o

~
I

f----

--~--~

MOS LOAD- - -

-__---1---..:.(1.:.::9:.:..). .

b--J~(1~8:!..)_

Data Ready

RECEIVER COMMANDS
Data Ready Reset

L -____________.('-!.17!.!1__ Receiver Clock

14-________..:..1---'(:::4)~

Receiver Output Disable

I
I

- - ~
(5)

(61

(7)

(8)

(9) (10) (11) (12)

-------------'-

OUTPUT

DATA HANDLING EQUIPMENT
(PERIPHERAL, DISPLAY,
COMPUTER, ETC,)

575

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

155

TMS 6011 JC, NC
ASYNCHRONOUS DATA INTERFACE (UART)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) *
Supply voltage, VDD (see Note 1)
Supply voltage, V GG (see Note 1)
I nput voltage (any input) (see Note 1)
Operating free-air temperature range
Storage temperature range

-20 V to 0.3 V
-20 V to 0.3 V
-20 V to 0.3 V
-25°C to 85°C
-55°C to 150°C

NOTE 1: Under absolute maximum ratings, voltage values are with respect to the normally most positive supply, VSS (substrate). Throughout
the remainder of this data sheet voltage values are with respect to VDD'
'Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions"
section of this specification is not implied. Exposure to absolute·maximum-rated conditions for extended periods may affect device reliabilitY.

recommended operating conditions
PARAMETER

MIN

Supply voltage, VDD

MAX

Supply voltage, VSS

V

-11.5

-12

-12.5

4.75

5

5.25

V
V

High-level input voltage, all inputs, VI H (see Notes 2 and 3)

VSS -1.5

VSS +0.3

Low-level input voltage, all inputs, V I L (see Notes 2 and 3)

-12

0.8

Clock

Pulse width, tw

UNIT

0

Supply voltage, VGG

II

NOM

V

V

2.5

IlS

Transmitter buffer register load

400

ns

Control register load

250

ns

Parity inhibit (see Notes 4 and 5)

400

ns

Parity select (see Notes 4 and 5)

300

ns

Word length select and stop bit select (see Notes 4 and 5)

300

ns

1.5

IlS

Master reset
Data ready reset

ns

250

Data setup time, tsu (da)

10-!-

Data hold time, thIda)

20t

Clock frequency, fciJ (see Note 6)

ns
ns
kHz

200

0

Operating free-air temperature, T A
°c
-25
85
NOTES: 2. All data, clock, and command inputs have Internal pull·up resistors to allow direct clocking by any TTL circuit.
3. The algebraic convention where the most negative limit is designated as minimum is used in this data sheet for logic voltage levels
only.
4. Inputs to PI, PS, WLS1, WLS2, and SBS are normally static signals. A minimum pulse width has been indicated for possible pulsed
operation.
5. All control signal pulses should be centered with respect to CRL to ensure maximum setup and hold time.
6. Clock frequency is 16 times the baud rate.
t -!-The arrow indicates the edge of the TBRL pulse used for reference: t for the rising edge, -!- for the falling edge.

electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)
PARAMETER

TEST CONDITIONS

MIN

Typt

VOH

High·level output voltage

IOH = -2001lA

VOL

Low-level output voltage

IOL - 1.6 rnA

IIH

High·level input current, all inputs

VI =5V

IlL

Low-level input current, all inputs

VI =0 V

IGG

Supply current from VGG

All inputs at a high level

-7

ISS

Supply current from VSS

All inputs at a high level

PD

Power dissipation

All inputs at a high level

Ci

Input capacitance, all inputs

VI = VSS,

MAX

2.4

f= 1 MHz

UNIT
V

0.6

V

10

J.l.A

-1.6

rnA

-12

rnA

20

30

rnA

190

300

rnW

10

20

pF

t All tYpical values are at T A = 25° C and nom inal voltages.

575

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TMS 6011 JC. NC
ASYNCHRONOUS DATA INTERFACE (UART)
switching characteristics over full ranges of recommended operating conditions (unless otherwise noted)
PARAMETER

TEST CONDITIONS

MIN

Propagation delay time, high-to-Iow
tpHL

level DR output from ORR
Propagation delay time, high-to-Iow

tpHL

level TBRE output from TBRL

tpzx

Enable time, receiver output from ROD

tpxz

Disable time, receiver output from ROD

1 Series 74 TTL load

Enable time, outputs PE, FE, DE, DR, or
tpzx

TBRE from SFD
Disable time, outputs PE, FE, DE, DR, or

tpxz

TBRE from SFD

Typt

MAX

UNIT

800

1000

ns

800

1000

ns

300

500

ns

300

500

ns

300

500

ns

300

500

ns

t All tYpical values are at T A = 25°C and nominal voltages.

voltage waveforms
I

II

\~---I...

--A

INPUT ROD OR SFD

~tpxz ~

tpzx

~I

~~----------------------------~~~---------------

OUTPUTROORFLAGSVOH ______________________

:i

VOL

HI-Z STATE

ENABLE AND DISABLE TIMES

INPUT DRR OR TBRL

:::~I
ItpH L

------+\

~~----------------------------------

VOH
OUTPUT DR OR TBRE

PROPAGATION DELAY TIMES

50%~
~50%
I ,,-,____________
I

INPUT TBRL

----J

~I-.---------tw ------~~~I

---.j
I

INPUTS T11- TI8

!4-tsu (da)

I+-+t- thida)
I

50_%~P*(

~~O_o/c_o______________________

_________________

DATA SETUP AND HOLD TIMES
NOTE: All enable. disable, and propagation delay times are referenced to the 90% or 10% points. All pulse widths are referenced to the 50%
points.

575

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157

TMS 6011 JC, NC
ASYNCHRONOUS DATA INTERFACE (UART)

operation timing diagram
TRANSMITTER TIMINGt
See Note 3

L
TO (NOT
3-STATE)

TRE(NOT3_STAT~~___________________________________________(_Y._C_L_O_C_K_C_Y_C_L_E_)_--t-:~
_________

t Transmitter initially assumed inactive at start of diagram, shown for 8 level code and parity and 2 stops.
NOTES:

II

1.

Bit time is 16 clock cycles.

2.

If transmitter is inactive the start pulse will appear on line within one clock cycle of time data strobe occurs (see detail below).

I

TBRL
CLOCK

~

--.I
TO
3.

I.

~

1/16 BIT

Because transmitter is double buffered, another data strobe can occur anywhere during transmission of character 1.

4. TBRE goes to a low for a period of approximately one clock cycle following a TBR L pulse.

RECEIVER TIMING
H
RI (see Note 3)

Start Data 1 Data 2 Data 3 Data 4

Data 5 Data 6 Data 7 Data 8

Parity Stop 1 Stop 2 Start

---,
;---.--"T'--,---r--.-,---,--,-.
L
L...-l_L~J. __ 1 __ ..1_ -.J __ -L _ ~ __ 1. M~B l _ ~

I

Data 1
1---

L...-.J__ _

INTERNAL
DATA SAMPLING

I

PULSE (seeNote4) ________~__~____~____~____~__~~__~____~____~__~~__~____~____~____~__
PE

See Note 1

FE

See Note 1

~I

~I

--1\4R01-ROB

See Note 2

OE

See Note 1

1 CLOCK CYCLE
1/16 BIT TIME

~I

NOTES: 1. This is the point at which the error condition is detected, if error occurs.
2. A high-to-Iow transition on the DR pin indicates that the contents of the receiver register has been transferred to the receiver
buffer register and that the three error-flag signals are valid. Output data remains valid until the next word is transferred into the
receiver buffer register.
3. The RI waveform illustrates an eight-bit word with parity and two stop bits. If parity is inhibited, the stop bits immediately follow
the last data bit. For all word lengths, the data in the buffer register must be right justified, i.e., R01 (pin 12) is the least significant
bit.
4. Data sampling occurs at the center of each data bit (8 clock cycles after the beginning of the bitl.

PRINTED IN U.S A

158

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TEXAS INSTRUMENTS RESERVES THE RIGHT TO MAKE CHANGES AT ANY TIME
IN ORDER TO IMPROVE DESIGN AND TO SUPPLY THE BEST PRODUCT POSSIBLE.

MOS MEMORY SYSTEM COMPATIBILITY
MOS MEMORY SYSTEM COMPATIBILITY
1)

POWER SUPPLIES

In P-channel MOS Memories the substrate is normally biased positive with respect to the drain or source nodes. The
substrate bias is normally negative for N-channel devices. In order to provide compatible interfaces with bipolar integrated
circuits, power supply voltages are translated for most MOS Mem9ry devices of recent design to maintain the recommended
substrate bias conditions and to provide input and output voltage levels between ground (0 volts) and Vee (+5 volts), the
standard system supply voltage in equipment using TTL integrated circuits.
The chart below shows the recommended supply voltages for the MOS Memory devices in this catalog along with the
symbols used for the various supply terminals.
MOS MEMORY NOMINAL POWER SUPPLY VOLTAGES AND TERMINAL SYMBOLOGY
TECHNOLOGY
SUPPLY VOLTAGE
22.5V - - - -

P-CHANNEL
METAL GATE
I

I

I

I

VBB--

N-CHANNEL
SILICON GATE

I

I

I

1

I
Vss--I

20 V
19V

II

IVBB--

I
16 V

I VSS--

12V

I
I

I

VDDI----

I

VDD---

I
I
VREF-I

7V
5V

I

VSS - - -

Vcc---

I

Vcc---

I

I

o

----+-VDD-----41 VDD---tVDD----L

GND---~I VSS

----toI

-3 V

I

I

I

-5 V

I

I

I

I

I

I

I

I
I

I
I
I

I

I
I

I

I

I

I

I

I

I

-12V
PRODUCT TYPE

TYPE NUMBERS

I
VGG--

1

Static and
; Dynamic
dynamic shift I RAM's
registers, ROM's,
keyboard
I
encoder, UART I

I

I

I

I
I

VBB

I

I
I

I
Static
RAM's

I
I

I

I

I

I

4K Dynamic
RAM's

I

I

I
I
I

TMS 3101 thru I TMS 4062 I TMS 1103
TMS 4033
TMS 3409 (all I TMS 4063
TMS 4034
I
SIR's)
I
I TMS 4035 I
I
I TMS 4036 series I
TMS 4800
I
TMS 2501
I
I TMS 4039 series I
TMS 4103
I
: TMS 4042 series I
TMS 5001 I
I
I
TMS 6011 I
ITMS
4043 series I
I

TMS 4030 series I

I
I

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ROM

I

I

POST OFFICE BOX 5012

VBB---

I

I

I
I

I

--~

I

I

I Dynamic I
I RAM

VSS

I

I
I

I

TMS 4050 series

I
I

TMS 4051 series

I

TMS 5400

TMS 4060 series :
I

159

MOS MEMORY SYSTEM COMPATIBILITY
SERIES 74 TTL INPUT AND
OUTPUT SPECIFICATIONS

2)

INPUT COMPATIBILITY

5

Figure 1 illustrates how Series 74 TTL circuits are
specified to guarantee that any Series 74 circuit will drive
or can be driven by any other Series 74 circuit. The O.4·volt
difference in output and input specifications is called the
noise margin. These margins guarantee that any Series 74
circuit is compatible with any other Series 74 circuit and
that the probability of false data inputs from spurious
switching transients or induced voltage levels is minimized.

4
"HIGH"

3
VOH min = 2.4 V
2

0.4 V
Output

II

1

VIH min = 2.0 V

Series 74 TTL

o

Series 74 TTL
Input

Noise Margins

O.4Vl
VILmax=0.8V
V--O-L-m-a-x-=-O-.4-V-"-L..Jt...-,,-1I L max = -1.6 mA
OW
FIGURE 1

+5 V

All TI shift registers and most ROM's and RAM's are
designed with inputs that can be driven directly without
level-shifter or amplifier circuits. The phrase '''fully
TTL-compatible" has been used to indicate that aMOS
Memory device will drive or be driven by Series 74 circuits
with adequate noise margins without the use of external
pull-up or pull-down components. Some P-channel MOS
Memories require a pull-up resistor on the input to meet the
minimum input voltage high level, VIH min. Figure 2
illustrates the interface with TTL. I n all cases, the input of
the MOS circuit has a very high impedance. Therefore, TTL
input compatibility is easily achieved.

VSS

R*
LOWTHRESHOLD
MOS
SN7400
OR OTHER
TTL GATE

-12 V

*The value of the R resistor varies depending on
speed-power requirements. I n many cases this resistor is
diffused on the MOS chip. For low-threshold MOS the
resistor assures that the worst-case TTL output is pulled
up to at least 3.5 V for proper MOS circuit operation.
FIGURE 2

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MOS MEMORY SYSTEM COMPATIBILITY
3)

OUTPUT COMPATIBILITY
Three types of buffers are commonly used on MOS devices:
•

a)

Open-drain

•

Internal pull-up

•

Push-pull

Open-drain and internal pull-up

The buffer is simply a current switch_ In the "off" state the impedance of the buffer is extremely large, while in the
"on" state it is typically under 1 kil. A discrete resistor or an MOS transistor may be used as a load with an open-drain
buffer. This resistor or transistor may be internal to the MOS circuit.

JOUTPUT

~VGG

1

VGG

J---..o

DATA-.Jl'

DATAJ

1

}-----o

OUTPUT

DATAJ

VSS
OPEN-DRAIN BUFFER

I

1

INTERNAL

INTERNAL

PULL-UP BUFFER

PULL-UP BUFFER

WITH LOAD RESISTOR

II
OUTPUT

WITH MOS LOAD TRANSISTOR

In every case compatibility with MOS is easily achieved. For instance, for an open-drain buffer with MOS:
+V

r--j-'
I

I

I

I

I I .... I
I

I
I

I

L _____ .J

I

I

I

I

I

L_-_

-12V

I

__...1

R2 provides the necessary current sink for the TTL input; Rl is sometimes used to limit power dissipation or the positive
excursion of the TTL input to +5 V. If R2 is on the chip, no external components may be necessary.

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161

MOS MEMORY SYSTEM COMPATIBILITY
-12V

+5 V (

Ir~-'I
I

.....

I
I
•

I-

I
I
I

r--I
I
I

J r-

-

--,

4kn

.

I

I
I

I

I

I

I

~~

I

-:.!:"

IDATA ~
L
____ -.II
+5 V

SERIES
74 LOGIC

I

I
I

__ ...J

L_-_

VSS

Two types are common. The unsaturated push'pull buffer is the most commonly used for low-threshold circuits since
the smaller drain-source voltage permits the upper output transistor to operate in the unsaturated or low-resistance region of
the 10 vs VOS characteristic curve. As a result, the output voltage swings near VOO without going negative and permits direct
TTL compatibility without external components.

II

~12V' ~PUT
,J'l
l
I

1

I,

DATA

VSS(+5 V)

VSS(+5 V)
UNSATURATED PUSH-PULL BUFFER

SATURATED PUSH-PULL BUFFER

4)

CLOCKS
Depending on the circuit type, there are different clock requirements:
No clocks - Static RAMs, ROMs, etc.

1 clock - with other clocks generated internally
2 clocks - most dynamic shift registers
a)

One external clock

An internal circuit generates the clocks from a single outside clock signal. The outside clock signal has the same swing as
the data input signal and the compatibility is identical (see preceeding paragraph 3).

b)

Single-clock low-threshold MaS circuits will accept a TTL clock without adding components.
Two or four clocks

The clock signals must swing between VSS and VGG. To go from a single-TTL-Ievel clock to a multiple-MaS-level
clock, two circuits are required: 1) a clock generator to generate the necessary clock pulses, and 2) a clock driver to bring the
clock levels to the required values. In most cases only one clock circuit is needed for an entire MaS LSI system.

162

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MOS lSI MECHANICAL DATA
general
Electrical characteristics presented in this catalog, unless otherwise noted, apply for circuit type(s) listed in the page
heading, regardless of package. Factory orders for circuits described should include the complete part·type numbers
listed on each page.

,

EXAMPLE: TM

o.

TI MaS Prefix)

2.

Product Status
S
X
C
T

3.

S

4030

Mas NUMBERING SYSTEM
N
L

t

~""5-.--T""e-m-p-er-a-tu-r-e-R""""an-g-e"")

Package)
F Flat
Ceramic dual-in-line
N Plastic dual-in-line
L Metal can
U Unencapsulated
(beam lead, etc.)

Standard devices
Prototype or experimental
Custom design
High reliability

C
L
M
R
S

-25°C to 85°C
O°C to 70°C
-55°C to 125°C
-55°C to 85°C
Special range

Unique Product Identification Number

II

manufacturing information

I

Alloying is performed in an inert atmosphere. A silicon gold eutectic is formed during the alloying operation.
Thermal compression bonding is used. Typical bond strength is 5 grams. Bond strength is monitored on a lot-to-Iot
basis. Any bond strength of less than 2 grams causes rejection of the entire lot of devices.
TI uses a low-temperature alloy brazing to seal ceramic packages. Metal-can packages are welded. Glass leaks are
eliminated by testing in a fluorocarbon solution heated to 150°C. Fine-leak elimination is performed through mass
spectrometer techniques. All MaS LSI devices produced by TI are capable of withstanding 5 x 10-7 ppm fine-leak
inspection, and may be screened to 5 x 10-8 ppm fine leak, if desired by the customer, for special applications.
All packages are capable of withstanding a shock of 3,000 G. All packages are capable of passing a 20,OOO-G
acceleration (centrifuge) test in the Y axis. Pin strength is measured by a pin-shearing test. All pins are able to withstand
the application of a force of 6 pounds at 45° in the peel-off direction.

dual-in-line packages
A pin-to-pin spacing of 100 mils has been selected for all dual-in-line packages.
TI uses several hermetically sealed ceramic dual-in-line packages, each of which consist of a ceramic base, plated metal
cap, and tin-plated leads.
The following dual-in-line packages are available in plastic or ceramic:
8
PIN

xt

300 mils between rows
400 mils between rows
600 mils between rows

10
PIN

xt

16
PIN
X

18
PIN
X

22
PIN

24
PIN

X

xt
X

28
PIN

40
PIN

X

X

tThere are no products shown in this data book in the 8-pin ceramic package or the ceramic or plastic 10-pin or 24-pin. 400-mil package.

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163

MOS LSI MECHANICAL DATA
16-PIN CERAMIC DUAL-IN-LiNE PACKAGE

@ . . . --:------0

r

ct.

0. 3oo

±0.010

1ct.
0.020

F9

II

0.010 NOM---ll.-

MIN~~
L
SEATING
PLANE

f~

PIN SPACING 0.100 TP
(See Note AI

J~0.032

f

0.185 MAX

I

I

•

0.lJ±0.030

NOM

0.050 ± 0.010

j~.018

± 0.003

0.050 ± 0.020

18-PIN CERAMIC DUAL-IN-LINE PACKAGE

0-----0

r ±~:~~~j

0.010

A

NOM~~

0.020
MIN

SEATlNG1~~--'
-

PLANET

0.018 ± 0.003--.1 / . -

I

PIN SPACING 0.100 TP-1
(See Note AI

NOTES:

A. Each pin centerline is located within 0.010 of its true longitudinal
position.
B. All linear dimensions are in inches.

575

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MOS LSI MECHANICAL DATA
22-PIN CERAMIC DUAL-IN-LiNE PACKAGE

8---------@

It, lit
0.400
±0.010

0.020

A

SEATING
-

PLANE

I

II

~

I

I

~

~~0.010NOM

0.050 ± 0.020

PIN SPACING 0.100 TP
(See Note A)

le-r-----------1'1
--@

24-PIN CERAMIC DUAL-IN-LiNE PACKAGE
1.290 MAX

~-.

..-,.--.r---t..-,r---t

INDEX
~
DOT

~

-

~------------------~,~

I

0.600
±O.OlD - ,

Fi
~~O.010NOM

0.020
SEATING
-

In-1--.-....--r-r-~~~::;::;~~~:;::;:::;:::;;:::;::::;:::;:;---T

PLANET
I

~
PIN SPACING 0.100 TP
(See Note A)

NOTES:

0.050 ± 0.010

A. Each pin centerline is located within 0.010 of its true longitudinal
position.
B. All linear dimensions are in inches.

575

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165

MOS LSI MECHANICAL DATA
28-PIN CERAMIC DUAL-IN-LiNE PACKAGE

~14-_--1.415MAX---~·1

(§+. -----@

D

INDEX

1 - - - - - - - - - - - - - - - ' DOT

a
0.050 ± 0.010

40-PIN CERAMIC DUAL-IN-LiNE PACKAGE

I-

ct.

L

r.=

ct.
0.600 ± 0.010

J

0.010 NOM

-\

®

0)

_@

~~,,1:::::: CI ::::: :]
0.020

~

F9j

2.020 MAX

~.

1MINrr-TT"1r"T......--mT"""1rTTT""T11T"""~c;:;:;;::;;:;;::::;;;;::;;;::::;;;;::t,;;;::;;:;;::;;:;;::::;;:::;;;:;;:;;::;;;;;::;::;-~
T

SEATING
-PLANE

l
I.--

0.Q18

± 0.003-+11+-1

1

j....../-PIN SPACING 0.100 T.P.

ISee Note Al

NOTES:

A. Each pin centerline is located within 0.010 of its true longitudinal
position.
B. All linear dimensions are in inches.

,
166

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MOS LSI MECHANICAL DATA
8-PIN PLASTIC DUAL-IN-L1NE PACKAGE

EITHER OR BOTH
INDEXES

0.020
MIN

-

-*-

SEATING PLANE

11

0.011 ± 0.003

f
0.Q18 ± 0.003

-.j j.-

II

r

PIN SPACING 0.100 TP
(See Note A)

16-PIN PLASTIC DUAL-IN-L1NE PACKAGE

~

O.870MAX;;i1

@.
c

coo

G
000

EITHER OR
BOTH
INDEXES

NOTES:

A. Each pin centerline is located within 0.010 of its true longitudinal
position.
B. All linear dimensions are in inches.

575

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167

MOS LSI MECHANICAL DATA
18-PIN PLASTIC DUAL-IN-LiNE PACKAGE

II
1\

0.011 ±0.003

22-PIN PLASTIC DUAL-IN-LiNE PACKAGE

£

£

(See Note A)

0.060 NOM

NOTES:

A. Each pin centerline is located within 0.010 of its true longitudinal
position.
B. All linear dimensions are in inches.

575

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MOS LSI MECHANICAL DATA
24-PIN PLASTIC DUAL-IN-LiNE PACKAGE

~-------1.290 MAX

---------.1

EITHER~
~

INDEX

~====================~

r= ::J

f

'50" ""

f
105
0

I

II

I

l-SEATINGPLANE

goo

1\0.011 ± 0.003

28-PIN PLASTIC DUAL-IN-LiNE PACKAGE

1+--------1.440MAX----------.1

EITHER _ _~....
INDEX

£

£

r,="" "'' :J

t

f

105

0

1 - S E A T I N G PLANE

f

goo
1 r O . 0 1 1 ±0.003

±~:~~~-J~ W-,

I

PIN SPACING 0.100 TP
(See Note A)

NOTES:

j Lj

0'020MIN~~
~
~~

I I

0.125MIN
0.033 MIN
0.050 ± 0.020

0.060 NOM

A. Each pin centerline is located within 0.010 of its true longitudinal
position.
B. All linear dimensions are in inches.

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169

MOS LSI MECHANICAL DATA
40-PIN PLASTIC DUAL-IN-LiNE PACKAGE

I'

1\

2.090 MAX

~:~~~'~::::::::::::::::::I
G

.@

£r,=!~~~~:J£

II

t 1

MIN~'-----'-

0

10:

90'

-SEATING

1\4""

J

0.020

~0.200MAX

PLANE~
0018-+!~ ~

~
~

0.011:t 0.003

1\

±0.OO3

0.033 MIN
0.Q75! 0.020
PIN SPACING 0.100 TP
(See Note AI

NOTES:

0.125MIN

0.060 NOM

A. Each pin centerline is located within 0.010 of its true longitudinal
position.
B. All linear dimensions are in inches.

metal-can
For devices such as shift registers requiring few inputs and outputs, TI uses two metal-can packages_
10-PIN METAL CAN

8-PIN METAL CAN

r
l
ALL DIMENSIONS ARE IN INCHES
UNLESS OTHERWISE SPECIFIED

ALL DIMENSIONS ARE IN INCHES
UNLESS OTHERWISE SPECIFIED
Same as JEDEC TO-99 and

Same as JEDEC TO-1 00 and
MO-006AD except for
diameter of standoff

MO·002AK except for
diameter of standoff

57E

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TTL
•
MemorIes

•

171

I

TTL
MEMORIES

SERIES 54S/74S
RANDOM-ACCESS READ/WRITE MEMORIES
BULLETIN NO. DL·S 7512257, MAY 1975

64 BITS (16 WORDS BY 4 BITS)
'S189, 'S289

256 BITS (256 WORDS BY 1 BIT)
'S201, 'S301

1024 BITS (1024 WORDS BY 1 BIT)
SN74S209,SN74S309
CE

16

VCC

ADA

16

VCC

16

VCC

CE

2

15

AD B

AD B

2

15

ADC

ADA

2

15

DI

R/W

3

14

ADC

GE1

3

14

AD H

AD B 3

14

RM

DI1

4

13

AD D

CE2

4

13

DI

ADC 4

13

AD J

D01

12

DI4

CE3

5

12

R/W

ADD

12

ADI

DI2

11

D04

DO

6

D02

10

DI3

AD D

GND

9

D03

GND

ADA

5

11

AD G

AD E 6

11

AD H

10

AD F

DO

7

10

AD G

9

AD E

GND

9

AD F

8

Pin assignments for all of these memories are the same for all packages.

•
•
•
•

•

Schottky-Clamped for High Performance
Full On-Chip Decoding and Fast Chip-Enable Simplify System Decoding
P-N-P Inputs Reduce Loading on System Buffers/Drivers
Choice of 3-State or Open-Collector Outputs

TYPE NUMBER (PACKAGES)

TYPE OF

BITSIZE

-55°C to 125°C

o°c to 70°C

OUTPUT(S)

SN54S189(J, W)

SN74S189(J, N)

3-State

64 Bits

TYPICAL ACCESS TIMES WRITE CYCLE TIME

(ORGANIZATIONS) CHIP-SELECT

SN54S289(J, W)

SN74S289(J, N)

Open-Collector

(16Wx4B)

SN54S201 (J, W)

SN74S201(J, N)

3-State

256 Bits

SN54S301 (J, W)

SN74S301 (J, N)

Open-Collector

(256W x 1 B)

SN74S209(J, N)

3-State

1024 Bits

SN74S309(J, N)

Open-Collector

(1024W x 1 B)

ADDRESS

SN54S'

SN74S'

12 ns

25 ns

25 ns

25 ns

13 ns

42 ns

100 ns

65 ns

20 ns

70 ns

150 ns

description
These monolithic TTL memories feature Schottky clamping for high performance, a fast chip-select access time to
enhance decoding at the system level, and the 'S201 and 'S209 RAMs utilize inverted-cell memory elements to achieve
high densities. The memories feature p-n-p input transistors that reduce the low-level input current requirement to a
maximum of -0.25 milliamperes, only one-eighth that of a Series 54S/74S standard load factor.
A three-state-output version and an open-collector-output version are offered for each of the three organizations_ A
three-state output offers the convenience of an open-collector output with the speed of a totem-pole output; it can be
bus-connected to other similar outputs, yet it retains the fast rise time characteristic of the TTL totem-pole output_ An
open-collector output offers the capability of direct interface with a data line having a passive pull-up.

write cycle
Information to be stored in the memory is written into the selected address (AD) location when the chip-enable (eE)
and the read/write (R/W) inputs are low. While the read/write input is low, the memory output(s) is(are) off
(three-state = Hi-Z, open-collector = high). When a number of outputs are bus-connected, this off state neither loads nor
drives the data bus; however, it permits the bus line to be driven by other active outputs or a passive pUll-up.

read cycle
Information stored in the memory (see function table for input/output phase relationship) is available at the output(s)
when the read/write input is high and the chip-enable input(s) is(are) low_ When one (or more) chip-enable input is(are)
high, the output(s) will be off.

575

172

TEXAS INCORPORATED
INSTRUMENTS
POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

SERIES 54S/74S
RANDOM-ACCESS READ/WRITE MEMORIES
FUNCTION TABLE
INPUTS
FUNCTION

READ/

'S189

'S289

ENABLEt

WRITE

'S201

'S301

Write

L

L

Read

L

H

H

X

Inhibit
H

~

high level, L

~

OUTPUTS

CHIP

low level, X

~

SN74S209

High Impedance

H

Complement of

Complement of

Data Entered

Data Entered

High Impedance

H

SN74S309

High Impedance

H

Data Entered

Data Entered

High Impedance

H

irrelevant

t For chip-enable of 'S201 and 'S301: L ~ all

CE

inputs low, H ~ one or more CE inputs high.

functional block diagrams

'S201

'S189, 'S289
A 111
B (151

/14)

ADDRESS
BUFFERS

1 OF 16
DECODERS

64 BIT MEMQRY

MATRIX
ORGANIZED

16 X·4

{

: 113[

II

G (11)

ADDRESS { F 110[
INPUTS

E

(9)

o

(7)

4·TO·16

256-8ITMEMORV

LINE

MATRIX ORGANIZED

DECODER

16-BY·16

SN74S209
ADDRES~

INPUTS

'S301
Same as 'S201 except output is as shown below.

: II::
c

ADDRESS
INPUTS

{

(4)

o

(5)

E

(6)

SN74S309
Same as SN74S209 except output is as shown below.

l024·BITMEMORY
MATRIX ORGANIZED
32-BY-32

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1)
Input voltage . . . . . . .
Off-state output voltage
Operating free-air temperature range: SN54S' Circuits
SN74S' Circuits
Storage temperature range

7V
5.5V
5.5 V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

NOTE 1: Voltage values are with respect to network ground terminal.

5

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

173

II

.....

......
01::0

=
en
z=

recommended operating conditions
SN74S189

SN54S189
Supply voltage, Vee

SN54S201

MIN

NOM

MAX

MIN

NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

4.5

5

5.5

MIN
4.75

NOM
5

l>m

SN74S209

SN74S201
MAX

NOM

MIN

5.25 4.75

MAX

5

5.25

UNIT

em
en

V

High-level output current, 10H

-2

-6.5

-2

-10.3

-10.3

mA

Low-level output current, 10L

16

16

16

16

16

mA

Q
I

Width of write pulse, tw(wrl (see Figure 1)
Setup

25

25

100

65

O~

O~

O~

O~

10~

O~

O~

O~

O~

10~

25t

25t

100t

65t

140t

at

at

at

ot

10t

time (see ehip enable after write pulse, th(eE)

at

ot

at

at

10t

Figure 1) Data after write pulse, thIda)

at

at

at

at

10t

Address before write pulse, tsu(ad)

time (see ehip enable before write pulse, tsu(eE)
Figure 1) Data before end of write pulse, tsu(da)

I~

n-...

ns

130

n
I

ns
I

Hold

Address after write pulse, th(ad)

Operating free-air temperature, T A
1l

o
~

~
rrI

70

a

-55

125

a

70

~ (J)
o z_

PARAMETER

~8z
~~(J)

VIH

'0-1
~;~
~~c:

:Cls;:
~ rrI
~ Z
-i

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

VOL

Low-level output voltage

10ZH

(J)

10ZL

TEST eONDITIONSt

a

MIN

TVP:j:

MAX

70

MIN

TVP:j:

SN74S209
MAX

2

2

+

°e

0.8

0.8

V

-1.5

V

VIH=2V,

Series 54S'

2.4

3.4

2.4

3.3

10H = MAX

Series 74S'

2.4

3.2

2.4

2.9

Vee = MIN,

VIH = 2 V,

Series 54S'

0.35

0.5

0.38

0.5

VIL=0.8V,

IOL=16mA Series 74S'

0.35

0.45

0.38

0.45

Off-state output current,

Vee = MAX, VIH = 2 V,

low-level voltage applied

VIL = 0.8 V,

Vo = 2.4 V
Vo = 0.4 V

2.4

V

2.9
0_38

0.45

V

40

100

IJ-A

-50

-40

-100

IJ-A

II

Input current at maximum input voltage

Vee = MAX, VI = 5.5 V

1

1

1

mA

High-level input current

Vee = MAX, VI = 2.7 V

25

25

25

IJ-A

IlL

Low-level input current

Vee = MAX, VI = 0.5 V

-250

-250

-250

IJ-A

lOS

Short-circuit output current §

Vee = MAX

-100

mA

lee

Supply current

-30

Vee = MAX, Series 54S'

TA = 25°e

See Note 2

TA = MIN
Series 74S'

m

-100

Full range

-30

-100

110

100

110
75

110

-30

140

mA

155
100

140

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAil typical values are at Vee = 5 V, T A = 25°C.
§Ouration of the short circuit should not exceed one second.
+11 = -18 mA for 'S189 and 'S201, -12 mA for 'S209.
NOTE 2: For the'S 189 I ee is measured with the read/write and chip-enable inputs grounded, all other inputs at 4.5 V, and the outputs open.
For the 'S201 and SN74S209 Ice is measured with all chip-enable inputs grounded, all other inputs at 4.5 V, and the output open.

3:
3:

m
Q

=
en
m

:e
:z::
w
en
I

-t

~

m
Q

C

-t

115

110
75

I

=t

50

IIH

TA = MAX

~

V

-1.2

VIL = 0.8 V,

VIL ='0.8 V,

MAX

0.8
Vee = MIN,

high-level voltage applied

TVP:j:

UNIT

-1.2

II =

Vee = MAX, VIH = 2 V,

MIN
2

Vee= MIN,

Off-state output current,

=
-...
=
:e
=
=t
m

'S201

'S189

--.J

m~

en en
en

l>

I

electrical characteristics over recommended operating free-air temperature (unless otherwise noted)

OJ

r:l

125

!

ns

t ~ The arrow indicates the transition of the read/write input used for reference: Hor the low-to-high-transition, Hor the high-to-Iow transition.

><
~ ;l>

~

-55

3:U'I
l>en

110

140

""tJ
C

-t

en

-.J

U1

recommended operating conditions
SN54S289
Supply voltage, Vee

~

(JJ

~

•

o~

g;;c
~~c:

:o~
~

~

rT'I

...,Z
(JJ

5.5

4.75

MIN

NOM

MAX

5

5.25

4.5

5

5.5

MIN
4.75

NOM
5

SN74S309

MAX

MIN

NOM

5.25 4.75

MAX

5

5.25

UNIT
V

5.5

V

Low-level output current, IOL

16

16

16

16

16

mA

Address before write pulse, tsu(ad)

Address after write pulse, th(ad)

Operating free-air temperature, T A

t ~ The arrow indicates the transition

25

25

O~

100

O~

65

O~

130

O~

ns

10~

ns

O~

O~

O~

O~

10~

25t

25t

100t

65t

140t

ot

ot

ot

ot

10t

ot

ot

ot

ot

10t

Ot

ot

ot

ot

10t

-55

125

0

70

-55

125

0

70

ns

0

70

°e

of the read/write input used for reference: Hor the low-to-high-transition, Hor the high-to-Iow transition.

electrical characteristics over recommended operating free-air temperature (unless otherwise noted)

z_

~8z
~~(JJ

5

SN74S301

MAX

5.5

Hold

><
~ ;1>

4.5

SN54S301

NOM

5.5

time (see ehip enable after write pulse, th(eE)
Figure 2) Data after write pulse, thIda)

~
rT'I

MIN

5.5

time (see ehip enable before write pulse, tsu(eE)
Figure 2) Data before end of write pulse, tsu(da)

VI
-i

MAX
5.5

Setup

o

NOM

High·level output voltage, VOH
Width of write pulse, tw(wrl (see Figure 1)

1J

SN74S289

MIN

PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

IOH

TEST CONDITIONSt

High-level output current

'S289
MIN

TYP+

'S301
MAX

2
Vee= MIN,

II =.

Vee = MIN,

VIH=2V,

VIL = 0.8 V

MIN

TYP+

SN74S309
MAX

2
0.8

0.8

V

-1.5

V

Vo = 2.4 V

40

40

100

Vo = 5.5 V

100

100

250

Series 54S'

0.5

0.38

0.5

VIL = 0.8 V,

IOL=16mA Series 74S'

0.45

0.38

0.45

II

Input current at maximum input voltage

IIH

High-level input current

Vee = MAX, VI = 2.7 V

25

IlL

Low-level input current

Vee = MAX, VI = 0.5 V

-250
105

110

Vee = MAX, VI = 5.5 V

TA = MAX
Vee= MAX, Series 54S'

TA = 25°e

See Note 3

TA = MIN

75

105

100

75

105

25

25

).lA

-250

).lA

140

mA

155
100

V

-250

140

t For condhions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

+AII typical values arc at V CC = 5 V, T A = 25° C.

·11

0.45

mA

1

105

Full range

0.38

).lA

1

1

= -18 mA for 'S289 and 'S301, -12 mA for 'S309.
NOTE 3: For the 'S289 ICC is measured with the read/write and chip-enable inputs grounded, all other inputs at 4.5 V. and the outputs open.
For the 'S301 and SN74S309 ICC is measured with all chip-enable inputs grounded, all other inputs at 4.5 V, and the output open.

>
2

V

-1.2

VIH = 2 V,

=

UNIT

0.8

Vee = MIN,

Series 74S'

MAX

-1.2

Low-level output voltage

Supply current

TYP+

2

VOL

lee

MIN

110

140

C

o

3:

:e>
-n
1

-4n

==m

o~

",

m=
2m

I>
nc

0 ..........
r-:e
~=en
n.......... m=
Om_

=3:~
omU"l
c3:~

-40 en
",=
.....
c - ......
-4m~
en en en

....
-"

U'I

II

..

--

.....

en

switching characteristics over recommended operating ranges of TA and
random-access memories with three-state outputs
PARAMETER

TEST CONDITIONS

tw(wr,min) Minimum width of write pulse
Access time from address
ta(ad)
ta(CE)

Access time from chip enable (enable time)

tSR

Sense recovery time

tpxz

Disable time from high or low level
-------

TYP+ MAX

I from CE
__ ~om R/W

n,

:a en
l>m

(unless otherwise noted)

SN54S189

CL = 30 pF,
RL = 300

Vee

SN74S189
TYP+

MAX

SN54S201

SN74S201

TYP+

MAX

TYP+

MAX

SN74S209
TYP+

UNIT!

MAX

15

25

15

25

40

100

40

65

65

85

ns

25

50

25

35

42

85

42

65

70

100

ns

12

25

12

17

13

40

13

30

20

40

ns

22

40

22

35

20

50

20

40

20

40

ns

CL = 5 pF, RL1 = 300 n,

12

25

12

17

9

30

9

20

15

30

See Figure 1

12

13

45

13

35

25

See Figure 1

12

40
- - -

ns
- - "

random-access memories with open-collector·outputs
PARAMETER

g I'T1

. . ><
~ >~

(J)

ta(CE)

Access time from chip enable (enable time)

tSR

Sense recovery time

atil z
_

Propagation delay time, low-to-

~8Z
~~(J)

tpLH

• 0-1

high-level output (disable time)

+AII typical values are at V CC

~~

=5

V, T A

Lfrom CE

I from R/W

loP-

l>en
n
.....
n-""
moP-

en en
en
:a
m
l>

TEST CONDITIONS

tw(wr,min) Minimum width of write pulse
Access time from address
ta(ad)

1J"""'i

Z:a
eiTi
o en
3:c.n

SN54S289

SN74S289

SN54S301

TYP+ MAX

TYP+ MAX

SN74S301

SN74S309

e

UNIT

..........

:a

:e

TYP+

MAX

TYP+

MAX

TYP+

15

25

15

25

40

100

40

65

65

85

ns

CL=30pF,

25

50

25

35

42

85

42

65

70

100

ns

RL1 = 300

n,
RL2 = 600 n,

12

25

12

17

13

40

13

30

20

40

ns

m

22

40

22

35

20

50

20

40

20

40

ns

See Figure 2

12

25

12

17

8

30

8

20

15

30

15

45

15

35

25

40

3:
m
3:

12

12

MAX

ns

=4

o
:a
m

= 25° C .

~c

en

03:

schematics of inputs and outputs

I'T1

z

'5189, '5201, SN74S209,
'5289, '5301, SN74S309

-I

(J)

EQUIVALENT OF EACH INPUT

Vcc

'5189, '5201, SN74S209

'5289, '5301, SN74S309
OUTPUT

OUTPUT

Vcc

__ ~OUT'UT
INPUT

U1

::!

'.II1II'

SERIES 54S/74S
RANDOM-ACCESS READ/WRITE MEMORIES
PARAMETER MEASUREMENT INFORMATION
I4---+t-t

j4- t h(adl ....

lU tadl

~

'r-+------"'1---..1
~ 1.5 V I

ADDRESS

I"

__ .J

INPUTS

3V

1.SV

"'---OV

tlU(dal~·r~~_"-,,·~th(da)

I

~N~1~s~G";i-~~

TEST

POINT

3V

-------i---.J'~'\:~--OV
~t"'Il:!1

CHlp·ENABLE
INPUTS

~thll:!1

:1113V
1.5 V I
I
15 V
I '
I

~
~tw(wrl---tol

------oV

~.t.,.o:\.~3V
~_______ _

REAO/WRITE
INPUT

~--------OV

:

:-tsR+ __ . . 4.5V

r--tpLZ..,

WAVEFORM 1

tSlc1osed.S2open,
:O.5Vii~-seeNoteBl
~
:
..... "-VOL
I+tPHZ~

WAVEFORM 2
(Slopen.S2closed,
see Note BJ

, '1.5V
--.../:

'

I+-ta("'I~

~~:~~~CIOsed)

ENABLE~3V

INPUTS
(See NoteCl
3V

1.5V
1''-------OV

I+-tal'dl~

~.5V

~VOH
-----VOL

ACCESS TIME FROM ADDRESS INPUTS

1.5 V

1.5 V

I

WAVEFORM 1

-I-------DV

:+tatUI"",:

r:-tpLZ

~.5V

(Slclosed.S2open.
s&eNoteB):

:~

t+-t'Il:!I~

j

I

Y,.5V:

}---'~~VVOH

tPHZ~ ~'t.ov

------'

ACCESS (ENABLE) TIME AND

VOLTAGE WAVEFORMS

""4.SV

"1-,---VOl

I

~~~::n~:~c~osed.
see Note B}

NOTES:

- - --,. OV

CHIP·

=-------'

(S_Not.AI

I

O.5V

WRITE CYCLE VOLTAGE WAVEFORMS

LOAD CIRCUIT

ADDRESS
INPUTS

_tsR~

~1.5V
VOH
J

DIS~BL.tEHTiME

FROM CHIP ENABLE

VOLTAGE WAVEFORMS

II

A. When measuring access times from address inputs, the chip enable input(s) is(are) low and the read/write is high.
B. Waveform 1 is for the output with internal conditions such that the output is low except when disabled. Waveform 2 is for the
output with internal conditions such that the output is high except when disabled.
C. When measuring access and disable times from chip enable input(s), the address inputs are steady-state and the read/write input is
high.
O. Input waveforms are supplied by pulse generators having the following characteristics: tr .;; 2.5 ns tf';; 2.5 ns, PRR .;; 1 MHz,
and Zout '" 50

n.
FIGURE 1-TESTING RAM'sWITH 3-STATE OUTPUTS
~t5U(da)

tSU(da)!

vee

~th(ad)-+{

---- --1- - ~,~3V
~~-ov

~,~",'7IT

~~~~~ss __ ~

,..._..!~_ . . . .

!

thIda)

~,;;;-r-~~

DATA

3V

.

----------"·~.:-+-/"<,~ ~--OV

INPUTS

HtSU(C[)

~

CHIP·ENABLE
INPUT

1.5V

r---tth(C!)

I

i

3

v

~

::"...--0 V

.....---tw(wrl----..j

~

READNiRITE
INPUT

1.5 V

I

'

LOAD CIRCUIT

Io---tSR~
-I--VOH

~
t.5V

(see Note BI

3V

1,5 V
;...e---------OV

!-tPLH-o!

'.5V

VOL

WRITE CYCLE VOLTAGE WAVEFORMS
~~~~~ss

~;-----*,.5V

(See Note A)

__

J:

3V

I '-------OV

_tal.dl---ot

I<--t'I"'I~

ENABLE
INPUT
(see Note C)

- ---VOL

1,5V

1.5V
""'i------OV

I

J..-ta(UI--.t

~tpLH

~.5V

~VOH

"".5 V

NOTES:

CHIP_~3V

(see

y,;;-VOH
---VOL

Note B)

ACCESS TIME FROM ADDRESS INPUTS

ACCESS (ENABLE) TIME AND DISABLE TIME FROM CHIP ENABLE

VOLTAGE WAVEFORMS

VOLTAGE WAVEFORMS

A. When measuring access times from address inputs, the chip-enable input(s) is(are) low and the read/write input is high.
B. Waveform shown is for the output with internal conditions such that the output is low except when disabled.
C. When measuring access and disable times from chip-enable input(s), the address inputs are steady-state and the read/write input is
high.
D. Input waveforms are supplied by pulse generators having the following characteristics: tr .;; 2.5 ns, tf .;; 2.5 ns, PRR .;; 1 MHz,
and Zout '" 50

n.
FIGURE 2-TESTING RAM'sWITH OPEN·COLLECTOR OUTPUTS

575

PRINTED IN USA.

TI cannot assume any (esponsibility for any circuits shown
or represent that they ore free from potent infringement.

TEXAS INSTRUMENTS RESERVES THE RIGHT TO MAKE CHANGES AT ANY TIME
IN ORDER TO IMPROVE DESIGN AND TO SUPPLY THE BEST PRODUCT POSSIBLE.

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

OALLAS. TEXAS 75222

171

TYPE SN7489
64-BIT RANDOM-ACCESS READ/WRITE MEMORY

TTL
MEMORIES

BULLETIN NO. DL·S 7511386, DECEMBER 1972-REVISED MAY 1975

For Application as a "Scratch Pad" Memory
with Nondestructive Read-Out

J OR N PACKAGE

•

Fully Decoded Memory Organized as 16
Words of Four Bits Each

•

Fast Access Time ... 33 ns Typical

•

Diode-Clamped, Buffered Inputs

ME

•

Open-Collector Outputs Provide Wire-AND
Capability

•

Typical Power Dissipation ... 375 mW

•

Compatible with Most TTL and DTL Circuits

ADA

16

VCC

2

15

ADB

WE

3

14

ADC

DI1

4

13

ADD

D01

5

12

DI 4

DI2

6

11

Di54

D02

7

10

DI 3

GND

8

9

503

description
This 64·bit active-element memory is a monolithic,
high-speed, transistor-transistor logic (TTL) array of
64 flip·flop memory cells organized in a matrix to
provide 16 words of four bits each. Each of the 16
words is addressed in straight binary with full on·chip
decoding.

II

The buffered memory inputs consist of four address
lines, four data inputs, a write enable, and a memory
enable for controll ing the entry and access of data.
The memory has open·collector outputs which may
be wire-AND connected to permit expansion up to
4704 words of N-bit length without additional output
buffering. Access time is typically 33 nanoseconds;
power dissipation is typically 375 milliwatts.

ME

WE

L

L

OPERATION
Write

CONDITION OF OUTPUTS
Complement of Data Inputs

L

H

Read

Complement of Selected Word

H

L

Inhibit Storage

Complement of Data Inputs

H

H

Do Nothing

High

write operation
I nformation present at the data inputs is written into the memory by addressing the desired word and holding both the
memory enable and write enable low. Since the internal output of the data input gate is common to the input of the
sense amplifier, the sense output will assume the opposite state of the information at the data inputs when the write
enable is low.
read operation
The complement of the information which has been written into the memory is nondestructively read out at the four
sense outputs. This is accomplished by holding the memory enable low, the write enable high, and selecting the desired
address.

575

178

TEXAS INCORPORATED
INSTRUMENTS
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•

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TYPE SN7489

64-BIT RANDOM-ACCESS READ/WRITE MEMORY
functional block diagram

ADDRESS
INPUTS

•
r-I----+----------','.:.,:.;;
r-t_:----_ _ _ _ _ _

:2}

----'.:.:.(9) 503

DATA
OUTPUTS

~-q.)o------~(111004
~~---r.---~~--~
Dil

""'4''--_ _-4.---.J

012",'6:-,.'- - - - - - - - '

DATA

INPUTS

013 :,::110,,-'_ _ _ _ _ _ _ _ _----'

{ D'4;.:.'12'-'.'_ _ _ _ _ _ _ _ _ _ _ _ _--'

schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS

EQUIVALENT OF EACH INPUT

VCC13--

~~OUTPUT

Req

INPUT

--

Data Inputs:

Req ~ 6 kn NOM

All others:

Req ~ 4 kn NOM

575

TEXAS INSTRUMENTS
INCORPORATED

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•

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179

TYPE SN7489
64-BIT RANDOM-ACCESS READ/WRITE MEMORY
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
7V
5.5 V
5.5 V

Supply voltage, Vee (see Note 1)
..... .
I nput voltage (see Note 1)
. . . . . .
High·level output voltage, VOH (see Notes 1 and 2)
Operating free·air temperature range
Storage temperature range
NOTES:

oOe to 70°C
-65°C to 150°C

1. Voltage values are with respect to network ground terminal.
2. This is the maximum voltage that should be applied to any output when it is in the off state.

recommended operating conditions
NOM

MIN

4.75
40
40
5

Supply voltage, Vee
Width of write-enable pulse, tw . . . . . . . . . . . . . . .
Setup time, data input with respect to wrhe enable, tsu (see Figure 1)
Hold time, data input with respect to write enable, th (see Figure 1)
Select input setup time with respect to write enable, tsu
Select input hold time after writing, th (see Figure 1)
Operating free-air temperature, T A

5

MAX UNIT

5.25

V
ns
ns
ns
ns
ns

a
5

a

°e

70

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

a

PARAMETER
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

I nput clamp voltage

IOH

High-level output current

VOL

TEST CONDITIONSt

MIN

TVP:j: MAX UNIT

2

V
0.8

Low-level output voltage

Vee = MIN,

II = -12 mA

Vee = MIN,

VIH=2V,

-1.5
20

VIL = 0.8 V,

VOH = 5.5 V

Vee = MIN,

V I H = 2 V, II 0 L = 12 mA

0.4

VIL = 0.8 V,

IIOL=16mA

0.45

V
V
J.1.A
V

II

I nput current at maximum input voltage

Vee= MAX,

VI = 5.5 V

1

IIH

High-level input current

Vee= MAX,

VI = 2.4 V

40

J.1.A

IlL

Low-level input current

Vec= MAX,

VI = 0.4 V

-1.6

mA

lec

Supply current

VCC = MAX,

See Note 3

105

mA

VCC = 5 V,

Co

Off-state output capacitance

VO=2.4V,

75

pF

6.5

f= 1 MHz

mA

NOTE 3: ICC is measured with the memory enable grounded, all other inputs at 4.5 V, and all outputs open.
tFor conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j: All typical values are at V CC = 5 V, T A = 25° C.

switching characteristics, Vee = 5 V, T A = 25° C
PARAMETER

TEST CONDITIONS

Propagation delay time, low-to-high-Ievel
tpLH

output from memory enable

tpLH

tpHL

tSR

TVP

MAX UNIT

26

50

33

50

30

60

35

60

ns

Propagation delay time, high-to·low-Ievel
tpHL

MIN

output from memory enable

CL=30pF,

Propagation delay time, low-to-high-Ievel

RL 1 = 300.11,

output from any address input

RL2 = 600.11,

Propagation delay time, high-to-Iow-Ievel

See Figure 1

output from any address input

ns

Sense recovery time

loutput initially high

39

70

after writing

loutput initially low

48

70

ns

575

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TEXAS INSTRUMENTS
I NCOHPORATED

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TYPE SN7489
64-BIT RANDOM-ACCESS READ/WRITE MEMORY
PARAMETER MEASUREMENT INFORMATION
VCC

~

-------------

RL1 = 300

From output
under test
- -..............- - - - - - ,
CL=30pF
RL2=600n

~

=

(See Note B)

""------------- 0 V
tsu
3V

t..-.I--

r-:------,

~Y
I

ANY

1/1.5

ADDRE:'S./

.

MEMORY
1.5 V

-I----ov
1

1,---,1

ANY
ADDRESS

1.5 V

1

1

~tPHL

---~\L '1.5 V
f\\

7

OUTPUT

""------'

1.5V

I

--I~t;;- - - - -

I,

----------~I

ANY HIGH
OUTPUT

~

I

1.0

-

14ANY

~I

"....

1
I

v-:-~
1.5 :OH

OV

3V

1

w

~tPLH

1

ANY

I

I

"----"'--1------J.- tSR -.I

3V

1\ 1.5 V
I ~--OV

_.../ I

tsu

1.5 V

1

WRITE
ENABLE

0V

~th
---+t
- - - - - 3V

I-- t

3V

II

;r,~

I

DATA
INPUT

____

>.t,.5 V .

:

I
I.!--I

LOAD CIRCUIT

ENABLE

3V

MEMORY
ENABLE

n

OV

VOH

1.5 V

- - - - - VOL

--l

tSR

II

LO~
r-~" ~5 ~OH
~-----'-=~--VOL

OUTPUT

--VOL

Write enable is high.

WRITE CYCLE FROM WRITE ENABLE

READ CYCLE
NOTES:

A. The input pulse generators have the following characteristics: tr';;; 10 ns, tf .;;; 10 ns, PR R
B. CL includes probe and jig capacitance.

=

1 MHz, Zout ~ 50

n.

FIGURE 1-SWITCHING CHARACTERISTICS

TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME

INPUT CURRENT
vs

vs

INPUT VOLTAGE

FREE-AIR TEMPERATURE
40

4

2

VCC = 5 V
D
I- TA = 25 C

35

I

0 f--- DATA INPUTS
E

.!.

-2

::J

-4

~

u

::J

C.

c

I

-

30

. .!----.;:t.=.::f

---.....•...I-ta(CS)

tpxz

= tpHZ

VOL

I

~

(SI open, S2 closed,
71.5 V
See Note C)
-------'

""45 V
.

'-l-;::~ VOH
I; ~ V
""0 V

I

tpHZ~

or tpLZ

ACCESS (ENABLE) TIME AND DISABLE TIME FROM CHIP SELECT
VOLTAGE WAVEFORMS

LOAD CIRCUIT

NOTES:

3 V

)t(i.5 V

---' :

51

WAVEFORM 2
CL includes probe and jig capacitance.
All diodes are 1 N3064.

______ - '

1.5 V

A. When measuring access times from address inputs, the chip-select input(s) is(are) low.
B. When measuring access and disable times from chip-select input(s), the address inputs are steady-state.
C. Waveform 1 is for the output with internal conditions such that the output is low except when disabled. Waveform 2 is for the
output with internal conditions such that the output is high except when disabled.
D. Input waveforms are supplied by pulse generators having the following characteristics: tr .;; 2.5 ns, tf .;; 2.5 ns, PRR .;; 1 MHz,
and Zout "" 50

n.

FIGURE 5-SWITCHING TIMES OF 'S287, 'S288, 'S471 , AND 'S472
575

PRINTED IN U.S A
TI cannol allume any relponlibilily for any eireui" Ihown
or reprelenl Ihal Ihey are free from palenl infringemenl.

TEXAS INSTRUMENTS
INCORPORATED

TEXAS INSTRUMENTS RESERVES THE RIGHT TO MAKE CHANGES AT ANY TIME
IN ORDER TO IMPROVE DESIGN AND TO SUPPlY THE BEST PRODUCT POSSIBLE.

POST OFFICE BOX 5012

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189

TTL
MEMORIES

SERIES 54/74, 54S/74S
READ-ONLY MEMORIES
BULLETIN NO. DL·S 7512259, MAY 1975

Mask-Programmed Memories That Can Replace PROMs

•

Full On-Chip Decoding and Fast Chip Select(s) Simplify System
Decoding

•

•

All Schottky-Clamped ROMs Offer
-Choice of 3-State or Open-Collector Outputs
-P-N-P Inputs for Reduced Loading on System Buffers/Drivers
Applications Include:
-Microprogramming Firmware/Firmware Loaders
-Code Converters/Character Generators
- Translators/Emulators
-Address Mapping/Look-Up Tables

TYPE NUMBER (PACKAGES)
-55°C to 125°C
SN5488A(J, W)
SN54187(J, W)
SN54S270(J)

•

256 BITS (32 WORDS BY 8 BITS)
'88A

•

o°c to 70°C
SN7488A(J, N)
SN74187(J, N)
SN74S270(J, N)

TYPE OF
OUTPUT(S)
Open-Collector
Open-Collector
Open-Collector

BIT SIZE

22 ns

(32Wx8B)
1024 Bits

20 ns

(256 W x 4 B)
2048 Bits

SN74S370(J, N)

3-State

SN74S271(J, N)

Open-Collector

2048 Bits

SN54S371 (J)

SN74S371 (J, N)

3-State

(256 W x 8 B)

VCC

15

CS

D03 3

14

AD E

D04 4

13

AD D

DO 5

12

ADC

006

11

AD B

DO 7

10

ADA

GND

9

008

TYPICAL ACCESS TIMES

256 Bits

SN54S271 (J)

16

1024 BITS (256 WORDS BY 4 BITS)
'187

(ORGANIZATION) CHIP-SELECT ADDRESS

SN54S370(J)

DO 1
DO 2 2

(512Wx4B)

26 ns
40 ns

15 ns

45 ns

15 ns

45 ns

AD G

16 VCC

AD F 2

15

AD H

AD E 3

14

CS2

AD 0

4

13

CS1

ADA

5

12

DO 1

AD B 6

11

DO 2

ADC

10

003

9

004

7

GND 8

2048 BITS (512 WORDS BY 4 BITS)
'S270, 'S370

description
These monolithic TTL custom-programmed read-only memories (ROMs) are
particularly attractive for applications requiring medium to large quantities of the
same bit pattern. Plug-in replacements can be obtained for most of the popular TTL
PROMs.
The high-complexity 2048-bit ROMs can be used to significantly improve system
bit density for fixed memory as all are offered in compact 16- or 20-pin dual-in-line
packages having pin-row spacings of O.300-inch.

ADG

16

VCC

AD F 2

15

AD H

AD E 3

14

ADI

AD 0

4

13

CS

AD A

5

12

DO 1

AD B 6

11

002

The Schottky-clamped versions offer considerable flexibility for upgrading existing
ADC 7
10 003
designs or improving new designs as they feature improved performance; plus, they
9
GND 8
004
offer low-current MaS-compatible p-n-p inputs, choice of bus-driving three-state or
open-collector outputs, and improved chip-select access times.
2048 BITS (256 WORDS BY 8 BITS)
Data from a sequenced deck of data cards punched according to the specified
format are permanently programmed by the factory into the monolithic structure
for all bit locations. Upon receipt of the order, Texas Instruments will assign a
special identifying number for each pattern programmed according to the order.
The completed devices will be marked with the appropriate TI special device
number. It is important that the customer specify not only the output levels desired
at all bit locations, but also the other information requested under ordering
instructions.

'S271, 'S371
20

VCC

AD B

2

19

AD H

ADC

3

18

AD G

AD 0

4

17 AD F

ADA

AD E 5

16

CS2

6

15

CS 1

14

008

DO 1

The three-state outputs offer the convenience of an open-collector output with the
speed of a totem-pole output: they can be bus-connected to other similar outputs
yet they retain the fast rise time characteristic of the TTL totem-pole output. The
open-collector outputs offer the capability of direct interface with a data line
having a passive pull-up.

003

8

13

DO 7

004

9

12

006

11

005

Word-addressing is accomplished in straight positive-logic binary and the memory
may be read when all CS inputs are low. A high at any CS input causes the outputs
to be off.
Pin assignments for all of these memories
are the same for all packages.

575

190

TEXASINCORPORATED
INSTRUMENTS
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•

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SERIES 54/74, 54S/74S
READ-ONLY MEMORIES
functional block diagrams

.
1

SN54187, SN74187

SN5488A, SN7488A
H

G

1101

F

1111

ADDRESS
INPUTS

:

o

lll
121

EI31

32X8
MEMORY MATRIX

(121

I1S1

~N~~~isS

(131

0 (4)

E(141

CHIP
SELECT

os

SN54S270,SN74S270

SN5~S271,SN74S271

A (1)

alZ)

C(3)

32·BY·64
MEMORY MATRIX

D~'g~g:R

0(4)

ADDRESS
INPUTS

ADDRESS
INPUTS

a
SN54S370,SN74S730

SN54S371,SN74S371

Same as SN54S270, SN74S270 except
outputs are as shown below:

Same as SN54S271, SN74S271 except
outputs are as shown below:

word addressing
'88A

'187, 'S271, 'S371

'5270, 'S370

WORD ADDRESS TABLE

WORD ADDRESS TABLE

WORD ADDRESS TABLE

WORD

INPUTS

WORD

E

D

C

B

A

L
L

L
L

L
L

L

1

L
H

0

L
H

2

L

L

L

3

L

4

L
H

5

L
L

L
L
L

H

L
L

6

L

L

H

H

L

7

L

H

H

L

L
H

H

8

L

L

L

H

L
H
L
H

0
1
2
3

4
5
6
7
8

H
L
L
L
L
L
L
L
L
L

G
L
L
L
L
L
L
L
L
L

INPUTS
F E D
L L L
L L L
L L L
L L L
L L L
L L L
L L L
L L L
L L H

C B A

L
L
L
L
H
H
H
H
L

L
L
H
H
L
L
H
H
L

L
H
L
H
L
H
L
H
L

WORD

5
6
7
8

507
508
509
510
511

H
H
H
H
H

0
1
2
3

4

251

26 omitted

H

H

L

H

H

28

H
H

H
H

H
H

L

29

L
H

30

H

H

H

H

L

31

H

H

H

H

H

L

252
253
254
255

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

L
H
H
H
H

H
L
L
H
H

H
L
H
L
H

H
L
L
L
L
L
L
L
L
L

G
L
L
L
L
L
L
L
L
L

INPUTS
F E D C B A

L
L
L
L
L
L
L
L
L

L
L
L
L
L
L
L
L
L

L
L
L
L
L
L
L
L
H

L
II
L
L
H
H
H
H
L

L
L
H
H
L
L
H
H
L

L
H
L
H
L
H
L
H
L

Words 9 thru 506 omitted

Words 9 thru 250 omitted

Words 9 thru
27

I

L
L
L
L
L
L
L
L
L

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

L
H
H
H
H

H
L
L
H
H

H
L
H
L
H

Word selection is accomplished in a conventional positive-logic binary code with the A address input being the
least-significant bit progressing alphabetically through the address inputs to the most-significant bit.
575

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SERIES 54/74, 545/745
READ-ONLY MEMORIES

schematics of inputs and outputs
'88A, '187

'88A

'187

EQUIVALENT OF

TYPICAL OF
ALL OUTPUTS

TYPICAL OF
ALL OUTPUTS

EACH INPUT

V cc------.---

_ _ ~OUTPUT

~~~OUTPUT

INPUT

a

'S270, 'S271, 'S370, 'S371

'S270, 'S271

'S370, 'S371

EQUIVALENT OF

TYPICAL OF
ALL OUTPUTS

TYPICAL OF
ALL OUTPUTS

EACH INPUT

vec

vec
_ _ ~OUT>UT

INPUT

OUTPUT

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V CC (see Note 1) .
Input voltage . . . . . . . .
Off·state output voltage
Operating free·air temperature range: SN54', SN54S' Circuits (see Note 2)
SN74', SN74S' Circuits.
Storage temperature range. . . . . . . . . . . . . . . . . . .
NOTES:

7V
5.5 V
5.5 V
D
D
-55 C to 125 C
D
ODC to 70 C
D
D
-65 C to 150 C

1. Voltage values are with respect to network ground terminal.
2. An. SN54187 in the W pac~age operating at free-air tem~eratures above 111°C requires a heat sink that provides a thermal
resistance from case-to-free-alr, ROCA, of not more than 46 e/w.

575

192

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

SERIES 54/74
READ-ONLY MEMORIES
recommended operating conditions
SN5488A
MIN
Supply volt~ge, Vee

SN7488A

SN54187

NOM

MAX

MIN

NOM

MAX

MIN

5

5.5

4.75

5

5.25

4.5

4.5

SN74187

NOM

MAX

MIN

NOM

MAX

5

5.5

4.75

5

5.25

UNIT
V

High·level output voltage, VOH

5.5

5.5

5.5

5.5

V

low·level output current, IOl

12

12

16

16

mA

70

°e

Operating free·air temperature, T A

-55

(see Note 2)
NOTE 2:

125

0

70

-55

125

0

An SN54187 in the W package operating at free·air temperatures above 111° C requires a heat sink that provides a thermal
resistance from case·to·free·air, ReCA, of not more than 46°C/W.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
'88A
MIN
VIH

High·level input voltage

Vil

low·level input voltage

VIK

Input clamp voltage

IOH

High·level output current

'187

TEST eONDITIONSt

PARAMETER

TYP:j:

MAX

11= -12 mA

Vee = MIN,

VIH=2V,
VOH = 5.5 V

Vil = 0.8 V,
Vee = MIN,

0.2

IOl=12mA

UNIT

TYP:j: MAX
V

2

2
Vee = MIN,

MIN

0.8

0.8

-1.5

-1.5

40

40

0.4

0.4

V
V

VOL

low·level output voltage

II

Input current at maximum input voltage

Vee= MAX,

VI = 5.5 V

1

1

IIH

High·level input current

Vee= MAX,

VI = 2.4 V

25

40

J.lA

III

low·level input current

Vee = MAX,

VI = 0.4 V

-1

-1

mA

ICC

Supply current

Vee= MAX,

See Note 3

130

mA

Vee - 5 V,

Vo - 5 V,

V

VIH = 2 V,

Off·state output capacitance

0.45

IOl = 16 mA

Vil = 0.8 V

Co

a

J.lA

64

92

80

pF

6.5

6.5

f = 1 MHz

mA

t For conditions shown as M IN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at VCC = 5 V, T A = 25°C.
NOTE 3: With outputs open and CS input(s) grounded, ICC is measured first by selecting a word that contains the maximum number of
programmed high·level outputs, then by selecting a word that contains the maximum number of programmed low·level outputs.

switching characteristics, Vee

= 5 V, TA = 25°e

PARAMETER

'88A

TEST CONDITIONS
TYP

'187

UNIT

MAX

TYP

MAX

ta(ad)

Access time from address

el=30pF,

26

45

40

60

ns

taleS)

Access time from chip select (enable time)

22

35

20

30

ns

low·to·high·level output

n ('88A1
300 n ('187)
Rl2= 600 n,

22

35

20

30

ns

from chip select (disable time)

See Figure 1

Propagation delay time,
tplH

R L1 = 400

575

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193

SERIES 54S/74S
READ-ONLY MEMORIES
recommended operating conditions

MIN
Supply voltage, Vee

SN54S270

SN74S270

SN54S370

SN74S370

SN54S271

SN74S271

SN54S371

SN74S371

NOM

MAX

MIN

NOM

MAX

MIN

5

5.5

4.75

5

5.25

4.5

4.5

High-level output voltage, VOH

5.5

MAX

MIN

NOM

MAX

5

5.5

4.75

5

5.25

V

-6.5

mA

16

mA

70

°e

5.5

V

High-level output current, 10H

-2

Low-level output current, 10L
Operating free-air temperature, T A

16

16
125

-55

UNIT

NOM

16

70

0

-55

125

0

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER

'S270, 'S271

TEST CONDITIONSt

TYP:j:

MIN
VIH

High-level input voltage

VIL

Low-level input voltage

VIK

Input clamp voltage

VOH

High-level output voltage

10H

High-level output current

Vee = MIN,

II = -18mA

Vee= MIN,

VIH=2V,

VIL = 0.8 V,

10H = MAX

VIH=2V,
VIL = 0.8 V

VOL
10ZH
10ZL

MIN

2

Vee = MIN,

a

'S370, 'S371
MAX

Low-level output voltage

I
I

2

V

0.8

0.8

V

-1.2

-1.2

V

2.4

V

50

p.A

V OH=5.5V

100

p.A

VIH=2V,

VIL = 0.8 V,

10L = MAX

Off-state output current,

Vee= MAX,

VIH = 2 V,

high-level voltage applied

Vo = 2.4 V

Off-state output current

Vee = MAX,

low-level voltage applied

Vo = 0.5 V

Input current at maximum input voltage Vee- MAX,

UNIT

MAX

VOH = 2.4 V

Vee = MIN,

II

TYP:j:

0.5

VIH=2V,
VI - 5.5 V

0.5

V

50

}J.A

-50

}J.A

1

mA

1

IIH

High-level input current

Vee= MAX,

VI = 2.7 V

25

25

p.A

IlL

Low-level input current

Vee= MAX,

VI = 0.5 V

-0.25

-0.25

mA

-100

mA

155

mA

lOS

Short-circuit output current §

Vee = MAX

Ice

Supply current

Vee = MAX,

See Note 4

Co

Off-state output capacitance

Vee=5V,

Vo = 5 V,

-30
105

155

105

6.5

f = 1 MHz

pF

6.5

t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
tAli typical values are at Vee = 5 V, T A = 25°e.

§Not more than one output should ~shorted at a time and duration of the short-circuit should not exceed one second.
NOTE 4: With outputs open and es input(s) grounded, lec is measured first by selecting a word that contains the maximum number of
programmed high-level outputs; then by selecting a word that contains the maximum number of programmed low-level outputs.

switching characteristics over recommended ranges of T A and
TEST

PARAMETER

CONDITIONS

ta(ad)

Access time from address

ta(eS}

Access time from chip select (enable time)
Propagation delay time,

tPLH

RL2 = 600

n,

See Figure 1

low-to-high-Ievel output

Vee

(unless otherwise noted)

SN54270

SN74270

SN54370

SN54271

SN74271

SN54370
TYP:j:

SN74370
SN74370

MAX

TYP:j:

MAX

45

95

45

70

ns

15

45

15

30

ns

15

40

15

25

ns

MAX

TYP:j:

UNIT

TYP:j:

MAX

from chip select (disable time)
ta(ad)

Access time from address

eL=30pF,

45

95

45

70

ns

ta(eS}

Access time from chip select (enable time)

See Figure 2

15

45

15

30

ns

10

40

10

25

ns

tpxz

Disable time from high or low level

t All typical values are at V CC

=5

V, T A

eL=5pF,
See Figure 2

= 25° C.
575

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SERIES 54/74, 54S/74S
READ-ONLY MEMORIES
PARAMETER MEASUREMENT INFORMATION

Vcc

CHIP
SELECT
INPUTISJ

FROM OUTPUT -~t---------.
UNDER TEST

J

CL = 30 pF
(See Note B)

RL2

= 600 n

_---3V
'.5 v
0 v

'.5 V

I

'---------------'.-t - - - I

,----+--Xl.5
V
/1 '----..../

ADDRESS
--1----'
INPUTS
I
¥,.5 V
ISee Note CJ
talCSJ-l.--taladJ t----1

I

~.5V

OUTPUT

NOTES:

I .

I

talad)

~tPLH

~'.5V

F,.5V

1.---.1

0 V

~VOH

I I

/,.5V

. ,

LOAD CI RCUIT

3 V

I

. .

- - - VOL

VOLTAGE WAVEFORMS

A. The input pulse generator has the following characteristics: PRR ~ 1 MHz, Zout "" 50 n. For Series 54/74, tr ~ 7 ns, tf ~ 7 ns,
for Series 54S/74S, tr ~ 2.5 ns, tf ~ 2.5 ns.
B. CL includes probe and jig capacitance.
C. The pulse generator is connected to the input under test. The other inputs, memory content permitting, are connected so that the
input will switch the output under test.

II

FIGURE 1-SWITCHING TIMES OF 'SSA, '1S7, 'S270, AND 'S271 (OPEN-COLLECTOR OUTPUTS)

VCC

6

S1

TEST
POINT

ADDRESS
INPUTS
(See Note A)

RL

= 300 n

,

foVOH

~.5 V_~~~~ VOL

ACCESS TIME FROM ADDRESS INPUTS
VOLTAGE WAVEFORMS

"
CHIP-

"

._---3 V
1.5 V
1.5 V
'--------'-l------OV
i+----~If-ta( CS)
""45 V
WAVEFORM 1 - - - . . . . . - -.......... I
(S1 closed, S2 open,
V
I
VOL
See Note C)
-I ta(CS)
I
i•
WAVEFORM 2
SELECT
INPUTS
(See Note B)

~tPLZ

~.5

::Fv'
.r--{-- --

_!I.'

i ~-l-;::~VOH

(S1 open, S2 closed,
,;-1.5 V
See Note C)
------

CL includes probe and jig capacitance.
All diodes are 1 N3064.

tpxz

!.

.!

I
~ V
tpHZ ~
""0 V

= tpHZ or tpLZ

ACCESS (ENABLE) TIME AND DISABLE TIME FROM CHIP SELECT
VOLTAGE WAVEFORMS

LOAD CIRCUIT

NOTES:

3 V

Xi.5 V
I -------0 V
!.ta(ad)'"

I

OUTPUT
(S1 and S2 closed)

FROM OUTPUT
...
UN DER TEST - i . - -.....---filr--.

1 kn

-y-------...

, 1.5 V
---' :
~ta(ad)~

A. When measuring access times from address inputs, the chip-select input(s) is(are) low.
B. When measuring access and disable times from chip-select input(s) the address inputs are steady-state.
C. Waveform 1 is for the output with internal conditions such that the output is low except when disabled. Waveform 2 is for the
output with internal conditions such that the output is high except when disabled.
D. Input waveforms are supplied by pulse generators having the following characteristics: tr ~ 2.5 ns, tf ~ 2.5 ns, PRR ~ 1 MHz,
and Zout "" 50 n.

FIGURE 2-SWITCHING TIMES OF 'S370 AND 'S371 (3-STATE OUTPUTS)

575

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195

SERIES 54/74, 54S/74S
READ-ONLY MEMORIES
ORDERING INSTRUCTIONS
Programming instructions for these read-only
memories are solicited in the form of a sequenced
deck of standard 80-column data cards providing the
information requested under "data card format,"
accompanied by a properly sequenced listing of these
cards, and the supplementary ordering data_ Upon
receipt of these items, a computer run will be made
from the deck of cards which will produce a complete
function table for the requested part_ This function
table, showing output conditions for each of the
words, will be forwarded to the purchaser as verification of the input data as interpreted by the computerautomated design (CAD) program_ This single run
also generates mask and test program data; therefore,
verification of the function table should be
completed promptly.

15
16-19
20
21-24
25
26-29
30
31-34
35
36-39
40

Each card in the data deck prepared by the purchaser
identifies the words specified and describes the levels
at the outputs for each of those words. All addresses
must have all outputs defined and columns designated
as "blank" must not be punched. Cards should be
punched according to the data card format shown.

a

57-58
59

6-9
10
11-14

Blank
Punch "H" or "L" for output DO 3.
Blank
Punch "H" or "L" for output DO 2.
Blank
Punch "H" or "L" for output DO 1.

Blank
Punch an alphabetic abbreviation representing the
current month.
Blank
Punch the last two digits of the current year.
Blank

60-61

Punch "SN"

62-66

Punch a left-justified integer representing the
Texas Instruments part number. This is supplied
by the factory through a TI sales representative.

67-68

Blank

69-80

Preferably these columns should be punched to
reflect the customer's part or specification-control
number. This information is not essential.

'187 DATA CARD FORMAT (32 CARDS)

Column
1-2 Punch a right-justified integer representing the
positive-logic binary input address (00-31) for the
word described on the card.

5

Punch "H" or "L" for output DO 4.

Punch a right-justified integer representing the
current calendar day of the month.

'88A DATA CARD FORMAT (32 CARDS)

3-4

Blank

50-51

56

The following information will be furnished to the
customer by Texas Instruments:
a) TI part number
b) TI sales order number
c) Date received.

Punch "H" or "L" for output DO 5.

Blank

52

Submit the following information with the data
cards:
a) Customer's name and address
b) Customer's purchase order number
c) Customer's drawing number.

Blank

41-49

53-55

SUPPLEMENTARY ORDERING DATA

Punch "H" or "L" for output DO 6.

Column
1- 3

Blank
4

Punch "H" or "L" for output V8. H = highvoltage-level output, L = low-voltage-level output

Punch a "-" (Minus sign)

5- 7

Punch a right-justified integer representing
the binary input address (007-255) for the
last set of outputs described on the card.

8- 9

Blank

Blank
Punch "H" or "L" for output DO 7.

Punch a right-justified integer representing
the binary input address (000-248) for the
first set of outputs described on the card.

Blank
575

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SERIES 54/74, 54S/74S
READ-ONLY MEMORIES
ORDERING INSTRUCTIONS
10-13

14
15-18
19
20-23
24
25-28
29
30-33
34
35-38
39
40-43
44
45-48
49
50-51
52
53-55

56
57-58
59

Blank
Punch "H", "L", or "X" for the second set
of outputs.
Blank

69-80

Blank
Punch "H" "L", or "X" for the fourth set
of outputs.
Blank
Punch "H", "L", or "X" for the fifth set of
outputs.

Column
1-3

4
5-7

8-80

Blank

Punch "H", "L", or "X" for the eighth set
of outputs.

1· 3

4

Blank
Punch "SN"

62-66

Punch a left-justified integer representing
the Texas Instruments part number. This is
supplied by the factory through a TI sales
representative.
Blank

Punch a right-justified integer representing
the binary input address (007-511) for the
last set of outputs described on the card.
Same as the '187 data card format.

18
19-26
27
28-35
36

I

Punch a "_" (Minus sign)

Blank

10-17

II

Punch a right-justified integer representing
the binary input address (000-252) for the
first set of outputs described on the card.

8- 9

Blank

Punch the last two digits of the current
year.

(Minus sign)

Punch a right·justified integer representing
the binary input address (003-255) for the
last set of outputs described on the card.

Punch a right-justified integer representing
the current calendar day of the month.

Blank

II - "

5- 7

Blank

Punch
an
alphabetic
abbreviation
representing the current month.

Punch a

Column

Punch "H ", "L", or "X" for the seventh set
of outputs.
Blank

Punch a right-justif ied integer representing
the binary input address (000-504) for the
first set of outputs described on the card.

'S271, 'S371 DATA CARD FORMAT (64 CARDS)

Blank
Punch "H", "L", or "X" for the sixth set of
outputs.

Preferably these columns should be
punched to reflect the customer's part or
specification-control number. This information is not essential.

'S270, 'S370 DATA CARD FORMAT (64 CARDS)

Punch "H", "L", or "X" for the third set of
outputs.

60-61

67-68

575

Punch "H", "L", or "X" for bits four,
three, two, and one (outputs DO 4, DO 3,
DO 2 and DO 1 in that order) for the first
set of outputs specified on the card.
H == high-voltage-level output, L == lowvoltage-level output, X == output level
irrelevant.

Punch "H", "L", or "X" for bits eight,
seven, six, five, four, three, two, and one
(outputs DO 8, DO 7, DO 6, DO 5, DO 4,
DO 3, DO 2, and DO 1 in that order) for the
first set of outputs specified on the card.
H == high~voltage-Ievel output, L == lowvoltage-level output, X == output level
irrelevant.
Blank
Punch "H", "L", or "X" for the second set
of outputs.
Blank
Punch "H", "L", or "X" for the third set of
outputs.
Blank

37-44

Punch "H", "L", or "X" for the fourth set
of outputs.

45-49

Blank

50-80

Same as the '187 data card format.

PRINTED IN U.S.A

TI (annat assume any responsibility for any circuits shown
or represent that they are free from patent infringement.

TEXAS INSTRUMENTS RESERVES THE RIGHT TO MAKE CHANGES AT ANY TIME
IN ORDER TO IMPROVE DESIGN AND TO SUPPLY THE BEST PRODUCT POSSIBLE.

TEXAS INSTRUMENTS
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197

TTL MEMORIES MECHANICAL DATA
general
The availability of a particular TTL memory in a particular package is denoted by an alphabetical reference in a table
on the data sheet for that type of memory, or above the pin-connection diagram. These letters refer to mechanical
outline drawings shown in this section. Orders for these memories should include the package outline letter at the end
of the circuit type number; e.g., SN54S287W, SN74S470J

W ceramic flat packages
These hermetically sealed flat packages consist of an electrically nonconductive ceramic base and cap, and a 16- or
24-lead frame. Hermetic sealing is accomplished with glass. Tin-plated ("bright-dipped") leads (-00) require no
additional cleaning or processing when used in soldered assembly.

24-PIN W CERAMIC

16-PIN W CERAMIC

~ ~~~--1~

16 lEADS

-~

(See NOleel

a

IASlAND
SUTING
'lANE

BASE AND

SEATING PLANE

~

006"38::~NX-

I-

0008880088(~)(0

Falls Within
JEDEC MO-004AG Dimensions

NOTES:

Falls Within
JEDEC MO-019AA Dimensions

a. All dimensions are in inches.
b. I ndex point is provided on cap for terminal identification only.
Leads are within 0.005 radius of true position (TP) at
maximum material condition.
d. This dimension determines a zone within which all
body and lead irregularities lie.
e. Not applicable for solder-dipped leads.
f. When solder-dipped leads are specified, dipped area
extends from lead tip to within 0.050 of package
body.
g. End configuration of 24-pin package is at the oPtion
of TI.

16 PIN

24PIN

24PIN

575

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TTL MEMORIES MECHANICAL DATA
J ceramic dual-in-line packages
These hermetically sealed dual·in·line packages consist of a ceramic base, ceramic cap, and a 16·, 20·, or 24·lead frame.
The packages are intended for insertion in mounting·hole rows on 0.300·inch or 0.600·inch centers. Once the leads
are compressed and inserted, sufficient tension is provided to secure the package in the board during soldering.
Tin·plated ("bright·dipped") leads (-00) require no additional cleaning or processing when used in soldered assembly.
20·PIN J CERAMIC

16·PIN J CERAMIC

r--~ - - j

~

g

,

,

••• 00

_ ...

00000000

O.245

-1

~

0050 NOM

~

0.200

-SEATINGPLANE

llii'

t
0.130

90°

16PLACES

_{::::::j

~@@@@®@)(!)

MIN

....)1-- ~

t

0070MAX16PLACES

GLASS
SEALANT

~

MAX

f

0. 020
MIN

~.J
--,

1

:::~~:d

I II

0.030 MIN

12f'LACES

I 11~r- &Ws

I··· .. ·;:l~50
' - - - . r - - - - - ' o:oTS

,.PLACES

1. . . . . . . . . . .

II

4PlACES

PIN SPACING 0.100 TP
(See Notea)

24·PIN J CERAMIC

Falls Within
JEDEC MO·015AA Dimensions

NOTES:

a. Each pin centerline is located within 0.010 of its true
longitudinal position.
b. All dimensions are in inches unless otherwise noted.

16·PIN

20·PIN

24·PIN

575

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199

TTL MEMORIES MECHANICAL DATA
N plastic dual-in-line packages
These dual-in-line packages consist of a circuit mounted on a 16-, 20-, or 24-lead frame and encapsulated within an
electrically nonconductive plastic compound. The compound will withstand soldering temperature with no deformation
and circuit performance characteristics remain stable when operated in high-humidity conditions. These packages are
intended for insertion in mounting-hole rows on 0.300-inch or 0.600-inch centers. Once the leads are compressed and
inserted, sufficient tension is provided to secure the package in the board during soldering. Leads require no additional
cleaning or processing when used in soldered assembly.
20-PIN N PLASTIC

--1

a

t'-0.070 MAX 20 PLACES

ALTERNATE SIDE VIEW

Package configuration of
16-pin N package (see
alternative sideviews) is
at the option of TI.

NOTES:

24-PIN N PLASTIC

a. Each pin centerline is located within 0.010 of its true
longitudinal position.
b. All dimensions are in inches unless otherwise noted.
c. This dimension does not apply for solder-dipped leads.
d. When solder-dipped leads are specified, dipped area of
the lead extends from the lead tip to at least 0.020
above the seating plane.

16-PIN

20-PIN

24-PIN

575

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EeL
•

MemorIes

II

201

SERIES SN10000
MEMORIES

Eel INTEGRATED CIRCU ITS

BULLETIN NO. DL-S 7512255, MAY 1975

•

Full On-Chip Address Decoding and Output-Sense Amplification

•

Constant Current Drain Over a Wide Supply Voltage Range

•

Logic Levels Compatible with Series SN10000 Logic Levels

•

Compatible for Wired-OR Word Expansion

PAGE
SN10139

32 X 8 Bit Programmable Read-Only Memory

SN10140

64 X 1 Bit Random-Access Memory (Drives 90-0hm Loads)

208

SN10142

64 X 1 Bit Random-Access Memory

208

SN10144

256 X 1 Bit Random-Access Memory

211

SN10145

16 X 4 Bit Random-Access Memory

214

SN10147

128 X 1 Bit Random·Access Memory

217

SN10148

64 X 1 Bit Random-Access Memory

208

.

203

Typical Characteristics .

221

Mechanical Data and Ordering Instructions

II

.

222

absolute maximum ratings over operating ambient temperature range t (unless otherwise noted)
-7V

Supply voltage VEE (see Note 1)
Input voltage range . . . . .
Output current
Operating ambient temperature range
Storage temperature range
Lead temperature 1/16 inch from case for 10 seconds

o V to VEE
-50mA
O°C to 85°C
-55°C to 125°C
300°C

NOTE1: Unless otherwise noted all voltage values are with respect to the

Vee

terminals and all

Vee

terminals must be connected in parallel.

tThe ambient temperature conditions assume air moving perpendicular to the longitudinal axis and parallel to the seating plane of the device at
a velocity of 500 feet per minute with the device under test soldered to a 4 x 6 x 0.062·inch double-sided 2-oz copper-clad circuit board.

575

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TYPE SN10139
256-BIT PROGRAMMABLE READ-ONLY MEMORY
APRIL 1975

•

32-Word-by-Eight-Bit Organization

•

Full On-Chip Address Decoding and
Output-Sensing Amplification

•

Capability for Wired-OR Connections

•

Easy Programming

J OR JE
DUAL-IN-L1NE PACKAGE (TOP VIEW)

Y1

description
The SN 1 0139 is a field-programmable, 256-bit readonly memory organized as 32 words of eight bits
each_ Full address decoding and output sense amplification are included on the chip_ Each of the 32
words is addressed by the binary address inputs AO
through A4_ The outputs Y 1 through Y8 can be
connected to other emitter-follower outputs to
achieve wired-OR word expansion_ An enable input,

E, is provided for ease in expansion_ The device is
enabled when the enable input is low_ When the
enable input is high, all outputs are forced low_
Data can be electronically programmed, as desired, at
any of the 256 bit locations in accordance with the
programming procedure specified_ Prior to programming, the memory contains a low-logic-level output
condition at all bit locations_ The programming
procedure open-circuits metal links, which results in a
high-logic-level output at the selected locations. The
procedure is irreversible; once altered, the output for
that bit is permanently programmed to provide a high
logic level. Outputs never having been altered may
later be programmed to supply a high-level output.
Operation of the device within the recommended
operating conditions will not alter the memory
content.

16

VCC

Y2

2

15

E

Y3

3

14

A4

Y4

4

13

A3

Y5

5

12

A2

Y6

6

11

A1

Y7

7

10

AO

VEE

8

9

Y8

a

functional block diagram

I

115)

AO

Vl

110)

V2

Al

A2

111)
V3

V4

112)
32WORD
DECODER

A3 113)

V5

V6

V7
A4 114)
VB

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203

TYPE SN10139
256-BIT PROGRAMMABLE READ-ONLY MEMORY
recommended operating conditions
B

NOM

A

UNIT

(SEE NOTE 3)

-5.72

Supply voltage, VEE
Operating ambient temperature, T A

-5.2

-4.68

0

85

V
C

electrical characteristics at specified ambient temperature t
TEST CONDITIONS

PARAMETER

VIH

VIH

VIL

VIL'

VOH

II

VOL

VOH'

VOL'

IIH
IlL

B

(SEE NOTES 1 AND 2)

High·level input voltage

High·level input voltage

Low·level input voltage

Low·level input voltage

High·level output voltage

VIH = VIHB,

Low·level output voltage

VIH = VIHB,

High·level output voltage

VIH = VIH'B,

Low-level output voltage

VIH = VIH'B,

VIL = VILA

VIL = VILA

VIL = VIL'A

VIL = VIL'A

VI = -810 mV,

High-level input current

o°c

-1020

-840

-980

-810

85°C

-910

-700

O°C

-1145

25°C

-1105

85°C

-1035

Supply current

O°C

VEE
VEE

-1630

85°C

VEE

-1595

-1645

O°C

-1490

25°C

-1475

85°C

-1440

O°C

-1000

-840

25°C

-960

-810

85°C

-890

-700

O°C

-1870

-1665

25°C

-1850

-1650

85°C

-1825

-1615

O°C

-1020

-840

25°C

-980

-810

85°C

-910

-700
-1645

O°C

-1870

25°C

-1850

-1630

85°C

-1825

-1595

25°C

All inputs at -810 mV,
All outputs open

mV

mV

25°C

25°C

Other inputs open

UNIT

25°C

All inputs and outputs open
lEE

A

25°C

Other inputs open
VI = -1850 mV,

Low-level input current

TYP
(SEE NOTE 3)

265
0.5

mV

mV

mV

mV

mV

mV

IJA

IJA

-145

-107

-145

-110

mA

switching characteristics at 25°C free-air temperature
TEST

PARAMETER

CONDITIONS
CL=3.5pF,

ta(ad)

Access time from address

tPLH

Propagation delay time, low-to-high-Ievel output from E (enable time)

tpHL

Propagation delay time, high-to-Iow-Ievel output from E (disable time)

RL = 50

n,

See Figures
1 and 2

B

A

UNIT

(SEE NOTE 3)
20

ns

15

ns

15

ns

1. All parameters are measured wIth VEE = -5.200 V, VCC = 0 V, and (unless otherwIse noted) the output IS connected to
-2.000 V through 50 51.
2. Test conditions stating VIH = VIHB (or VIH'B) andlor VIL = VILA (or VIL'A) mean that the high·level input voltages are equal
to the B limit of V I H (or V IH') specified for the particular temperature (see note 3) andlor the low-level input voltages are equal
to the appropriate A limit of VIL (or VIL'). The output voltage limits are guaranteed for any appropriate combination of input
conditions for the desired output.
3. This data sheet uses the algebraic·limit system that has been adopted by the International Electrotechnical Commission. The A
limit is the more positive (less negative) limit; the B limit is the less positive (more negative) limit.
tThe ambient temperature conditions assume air moving perpendicular to the longitudinal axis and parallel to the seating plane of the dev·ice at
a velocity of 500 feet per minute with the device under test soldered to a 4 x 6 x 0.062·inch double·sided 2·oz copper·clad circuit board.

NOTES:

47E

204

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TYPE SN10139
256-BIT PROGRAMMABLE READ-ONLY MEMORY
PARAMETER MEASUREMENT INFORMATION

ADDRESS
INPUT
(See Notes A, B, and D)

DEVICE
UNDER

OUTPUT

t-~....- - - (See Note B)

TEST
ENABLE
INPUT
(See Notes A, B, and E)

CL = 3.5 pF
(See Note C)

0.1 j./F

NOTES:

=

A. The input waveforms are supplied by generators having the following characteristics: Zout = 5D.I1. PRR = 2 MHz. Transition
times of input waveforms are 2 ± D.l ns between the 20% and 80% levels and are determined with no device in the socket.
B. The waveforms are monitored on an oscilloscope having the following characteristics: tr';; 0.35 ns, Rin = 50.11. Input and output
cables are equal lengths of 50-.11 coaxial cable.
C. CL includes jig capacitance_
D. All address lines not under test must be biased to select a memory cell.
E. If the enable line is not under test, it must be at a low logic level.

M"'--

•

FIGURE 1-TEST CIRCUIT
t+-r210.1 ns
ADDRESS
INPUTS
(See Note B)

DATA
OUTPUT

--;"I.
20%

~2:t0.1 ns

1

+-I ~~

80% I

~

I

I

OJU'"

I~~--- -7>-- -~

I

I.-

:.... ta(ad)

ta(ad)

~

---+1110mV
(See Note A)

20%

+310mV

-I

~~
ACCESS TIME FROM ADDRESS INPUTS

~2:t0.1 ns

ENABLE
INPUT
(See Note C)

50%

~I 80%

N
I

20%
_ _ _ _ _ _ _ _ _ _2_o_%~

I

14DATA
OUTPUT

~2:t0.1 ns

-8~~j

+1110mV

50%

_1 _ _ _ _ _
I

tpLH ~

-

+310mV

!.- tPHL -I
I

I

________

I

-J~O%

50%"---

ENABLE AND DISABLE TIMES
NOTES:

A. Voltage values on input waveforms are with respect to ground.
B. The enable input is low.
C. The bit location addressed contains high-level data.

FIGURE 2-VOL TAGE WAVEFORMS

475

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205

TYPE SN10139
256-BIT PROGRAMMABLE READ-ONLY MEMORY
step-by-step programming procedure
manual
1.

Connect VEE (Pin 8) to ground and Vee (Pin 16) to 5.2 V. See Figure 3. Address the word to be programmed by
applying to the appropriate address inputs 4 to 4.6 V for a high level and 0 to 1 V for a low level.

2.

Raise Vee (Pin 16) to 12 V. This level must not be maintained longer than 1 second. Maximum supply current during
programming is 250 mAo

3.

After Vee has stabilized at 12 V (including any ringing that may be present on the Vee line), apply a current pulse of
2.5 mA to the output corresponding to the bit to be programmed to a high.

4.

ReturnVeet05.2V.
CAUTION: To prevent excessive chip temperature rise, Vee should not be allowf'd to remain at 12 V for more than
1 second.

5.

Verify that the selected bit has programmed by connecting a 460·[2 resistor to ground and measuring the voltage at the
output. If a high level (Va;;;' 4.2 V) is not detected at the output, the programming procedure should be repeated
once.

6.

If verification is positive, proceed to next bit to be programmed.

automatic

II

1.

Connect VEE (Pin 8) to ground and Vee (Pin 16) to 5.2 V. See Figure 3. Address the word to be programmed by
applying to the appropriate address inputs 4 to 4.6 V for a high level and 0 to 1 V for a low level.

2.

Raise Vee (Pin 16) to 12 V. This level must not be maintained longer than 1 second. Maximum supply current during
programming is 250 mAo

3.

After a delay of 10011s minimum, 1 ms maximum, apply a 2.5-mA current pulse to the output corresponding to the
first bit to be programmed to a high. This output pulse is maintained between 0.5 and 1 ms. See Figure 4.

4.

Repeat step 3 for each bit of the selected word specified as a high. (Program only one bit at a time; the delay between
output programming pulses should not be greater than 1 ms.)

5.

After all the desired bits of the selected word have been programmed, change address data and repeat the preceeding
two paragraphs.
NOTE: If all the maximum times listed above are maintained, the entire memory will program in less than 1 second.
Therefore, it would be permissable for Vee to remain at 12 V during the entire programming time.

6.

After stepping through all address words, return Vee to 5.2 V and verify that each bit has programmed. If one or
more bits have not programmed, repeat the entire programming procedure once.

recommended conditions for programming
B

NOM

A

UNIT

(SEE NOTE 3)
Supply voltage,

To program

Vee

Input voltage

11.5

12

To verify

5

5.2

High level

4

Low level

0

Output current during programming

2

Programming pulse width, tw(p) (See Note 4)

0.5

Programming pulse rise time

I

Programming pulse delay (See Note 4)
NOTES:

Following

Vee

change, td(1)

I Between output pulses, td(2)

12.5
5.4
4.6
1

2.5

V
V

3

rnA

1

ms

10

~s

0.1

1

0.01

1

ms

3. This data sheet uses the algebraic' limit system that has been adopted by the International Electrotechnical Commission. The A
limit is the more positive (less negative) limit; the B limit is the less positive (more negative) limit.
4. These maximum times are specified to minimize the amount of time Vee is at 12 V.

475

206

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TYPE SN10139
256-BIT PROGRAMMABLE READ-ONLY MEMORY
PROGRAMMING INFORMATION
12 V

S.2 V

I

PROGRAM
(MOMENTARY)

4 V to
4.6 V

20 V

--- -----,
1

I
ADDRESS
H_-O

Vee

1

TEST
POINT

_----,,J-----, AO

__-...r----.

A1

____.r----,

A3

SN10139

Y4

lOUT·
PUTS

1
1

Y6
A4

_-..~---.

-=

I

YS

Y7

ya
GND

7.S kn
(ALL OUTPUTS)

-=

-=

-

-

II

FIGURE 3-PROGRAMMING CIRCUIT

I

..
I

.1_

WORD 0

I

----.J
:
1

2

3

a

I

-----.J
1
1

I

~~---12V

1

I

I

WORDS 2·31
ADDRESSED

I

I

I

OUTPUT

_,_

ADDRESSED

I
I

I

Vee

WORD 1

I

ADDRESSED

1

2

3

a

~.

L-

I

:

II

S.2 V

1

1

2

a

1.

Inn
n n:n n n nln n nT--:·
~ H ~ (--J LU LJ L...I '-1 ~ LLJ LJ '-1 (-J ! -

eURRENT----t-1

I I I ~

1-..\
-.I

I"

I+-

t

rnA

I

d(2)

I

I+-tw(p)

I4- t d(1)

srnA

';;;1 SECOND

.1
--------------+1--

FIGURE 4-TIMING DIAGRAM FOR AUTOMATIC PROGRAMMING

475

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207

TYPES SN10140, SN10142, SN10148
64-BIT RANDOM-ACCESS MEMORIES
MAY 1975

•

SN10140 Drives gO-Ohm Loads

•

SN10142 and SN10148 Drive 50-Ohm Loads

•

Fast Access Times:
10 ns Max (SN10142)
15 ns Max (SN10140, SN10148)

•

64-Word-by-One-Bit Organization

•

Full On-Chip Address Decoding and
Output-Sense Amplification

•

Capability for Wired-OR Connections

•

J OR JE
DUAL-IN-LiNE PACKAGE (TOP VIEW)

Low Sensitivity to Supply Voltage
Variation

description
These 64-bit active-element memories are monolithic,
high-speed, emitter-coupled-Iogic (Eel) arrays of 64
storage cells organized to provide 64 words of one bit
each. Full address decoding and output sense amplification are included on the chip. An additional level of
decoding is provided for memory systems by the two
enable inputs. Each of the 64 words is addressed by
the binary address inputs AO through A5. The output
can be connected to other emitter-follower outputs
to achieve wired-O R word expansion. The SN 1 0140,
SN10142, and SN10148 are fully compatible with
the SN10000 logic family. The SN10148 and
SN 10142 are specified to meet SN 1 0000 levels when
driving 50-ohm loads and the SN 10140 is specified to
drive a gO-ohm load.

II

16

VCC2

AO

2

15

DATA OUT

A1

3

14

NC

VCC1

E1

4

13

DATA IN

E2

5

12

R/W

A2

6

11

NC

A3

7

10

A5

VEE

B

9

A4

functional block diagram

I nformation at the data input is written into the
memory by addressing the desired word with the
address lines and taking the read/write input low
while both enable inputs are held low. The output is
forced low while the memory is in the write mode.

DATA
OUTPUT

I nformation stored in the memory is read out by
holding the read/write line high, selecting the desired
address, and taking both enable inputs low.
FUNCTION TABLE
READ!

ENABLE

WRITE

E1

E2

H

OPERATION
Write (output low)

L

L

L

H

L

L

Read

X

H

X

Chip disabled (output low)

X

X

H

Chip disabled (output low)

= high

level,

L

= low

level,

X

= irrelevant

575

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TYPES SN10140. SN10142, SN10148
64-BIT RANDOM-ACCESS MEMORIES
recommended operating conditions
NOM

B

A

(SEE NOTE 3)
-5.72

SUppl\l voltage, VEE
Width of write pulse, tw(wr) (see Figure 9)

-5.2

-4.68

10

Setup time, tsu (see Figure 9)

Address before write pulse

5

Enable before write pulse

3

Data before end of write pulse

V
ns
ns

10

Address after write pulse
Hold time, th (see Figure 9)

UNIT

3

Enable after write pulse

0

Data after write pulse

3

Operating ambient temperature, T A

ns

0

85

°c

electrical characteristics at specified ambient temperature t
TEST CONDITIONS

PARAMETER

VIH

VIH'

VIL

VIL'

VOH

VOL

VOH'

VOL'

IIH

NOTES:

High-level input voltage

High-level input voltage

Low-level input voltage

Low-level input voltage

High-level output voltage

VIH = VIHB,

Low-level output voltage

VIH = VIHB,

High-level output voltage

VIH = VIH'B,

Low-level output voltage

High-level input current

IlL

Low-level input current

lEE

Supply current

VIH = VIH'B,

I Read/Write

I

Other inputs

VIL = VILA

VIL = VILA

VIL = VIL'A

VIL = VIL'A

VI = -810mV,

All inputs and the output open

=

-5.200 V, VCC1

=

VCC2

o°c

-1020

-840

25°C

-980

-810

85°C

-910

-700

O°C

-1145

25°C

-1105

85°C

-1035

O°C

VEE
VEE

-1630

85°C

VEE

-1595

O°C

-1490
-1475

85°C

-1440

O°C

-1000

-840

25°C

-960

-810

85°C

-890

-700

O°C

-2000

-1665

25°C

-1990

-1650

85°C

-1920

-1615

O°C

-1020

-840

25°C

-980

-810

85°C

-910

-700

O°C

-2000

-1645

25°C

-1990

-1630

85°C

-1920

-1595
355

=0

265
0.5
-103

mV

-1645

25°C

25°C

UNIT

mV

25°C

25°C'

Other inputs open

A

(SEE NOTE 3)

25°C

Other inputs open
VI = -1990 mV,

1. All parameters are measured with VEE

TYP

B

(SEE NOTES 1 AND 2)

mV

II

mV

mV

mV

mV

mV

J.lA
J.lA

-85

mA

V, and (unless otherwise noted) the output is connected

to -2.000 V through 50 n for SN10142 and SN10148 or 90 n for SN10140.
2. Test conditions stating VIH = VIHB (or VIH'B) and/dr VIL = VILA (or VIL'A) mean that the high-level input voltages are equal
to the B limit of VIH (or VIH') specified for the particular temperature (see note 3) and/or the low-level input voltages are equal
to the appropriate A limit of VIL (or VIL'). The output voltage limits are guaranteed for any appropriate combination of input
conditions specified by the function table for the desired output.

3. This data sheet uses the algebraic-limit system that has been adopted by the International Electrotechnical Commission. The
A limit is the,more positive (less negative) limit; the B limit is the less positive (more negative) limit.
tThe ambient temperature conditions assume air moving perpendicular to the longitudinal axis and parallel to the seating plane of the device at
a velocity of 500 feet per minute with the device under test soldered to a 4 x 6 x 0.062-inch double-sided 2-oz copper-clad circuit board.

575

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209

TYPES SN10140, SN10142, SN10148
64-BIT RANDOM-ACCESS MEMORIES

switching characteristics at 25°C free-air temperature
SN10140
PARAMETER

ta(ad)
tpLH

E (enable

output from

n

tSR

A

UNIT

15

8

10

ns

12

7

12

ns

7

12

7

12

ns

2.5

2.5

ns

2.5

2.5

ns

10

10

ns

(SN10142, SN10148),

See Figures 5 and 9

Transition time,
tTHL

TYP

7

= 3.5 pF,
RL = 90 n (SN10140)
50

low·to-high·level output (20% to 80%)

B

10

CL

Transition time,
tTLH

A

(SEE NOTE 3)

time)

E (disable time)

TYP

(SEE NOTE 3)
Access time from address

Propagation delay time, high-to-Iow-Ievel
tpHL

B

Propagation delay ti me, low-to-high-Ievel
output from

SN10142

SN10148

TEST CONDITIONS

high·to·low-Ievel output (80% to 20%)
Sense recovery time

NOTE 3: This data sheet uses the algebraic·limit system that has been adopted by the International Electrotechnical Commission. The A limit
is the more positive (less neagtive) limit; the B limit is the less positive (more negative) limit.

PARAMETER MEASUREMENT INFORMATION

ADDRESS
INPUT
(See Notes A, B, and D)

II

ENABLE
INPUT
(See Notes A, B, and E)

(See Note F)
DEVICE
UNDER
TEST

READ/WRITE
INPUT
(See Notes A and B)

40

n

(A)

SN10140 OUTPUT
(See Note B)

e _ - - - SN10142, SN10148 OUTPUT

(See Note B)
CL = 3.5 pF
(See Note C)

DATA
INPUT
(See Notes A and B)

0.1/-1 F

2V

+ 11'-'--4II~---I

NOTES:

A. The input waveforms are supplied by generators having the following characteristics: Zout = 50 n, PRR = 2 MHz. Transition
times of input waveforms are 2 ± 0.1 ns between the 20% and 80% levels and are determined with no device in the socket.

B. The waveforms are monitored on an oscilloscope having the following characteristics: tr .;; 0.35 ns, Rin = 50 n. Input and output
cables are equal lengths of 50-n coaxial cable.
C. CL includes jig capacitance.
O. All address lines not under test must be biased to select a memory cell.
E. Enable line(s) not under test must be ata low logic level.
F. 40·n external resistor shown is used for SN10140 only. When testing SN10142 or SN10148, connect point (A) directly to
50·n output cable.

FIGURE 5-TEST CIRCUIT

575

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TYPE SN10144
256-811 RANDOM-ACCESS MEMORY
MAY 1975

•

Fast Access Time ... 18 ns Typical

•

256-Word-by-One-Bit Organization

•

Drives 50-Ohm Loads

•

Full On-Chip Address Decoding and
Output-Sense Amplification

•
•

J OR JE
DUAL-IN-LiNE PACKAGE (TOP VIEW)

16

VCC

2

15

DATA OUT

A2

3

14

RJW

A3

4

13

DATA IN

E1

5

12

A7

E2

6

11

A6

E3

7

10

AS

VEE

8

9

A4

AO
A1

Capability for Wired-OR Connections
Low Sensitivity to Supply Voltage Variation

description
This 256-bit active-element memory is a monolithic
high-speed, emitter-coupled-Iogic (Eel) array of 256
storage cells organized to provide 256 words of one
bit each_ Full address decoding and output sense
amplification are included on the chip. An additional
level of decoding is provided for memory systems by
the three enable inputs. Each of the 256 words is
addressed by the binary address inputs AD through
A7. The output can be connected to other emitterfollower outputs to achieve wired-OR word
expansion.

functional block diagram

Information at the data input is written into the
memory by addressing the desired word with the
address lines and taking the read/write input low
while all enable inputs are held low. The output is
forced low while the memory is in the write mode_

II

Information stored in the memory is read out by
holding the read/write line high, selecting the desired
address, and taking all enable inputs low_
FUNCTION TABLE
ENABLE

READ/
WRITE

E1

E2

E3

L

L

L

L

H

OPERATION
Write (output low)

H

L

L

L

Read

X

H

X

X

Chip disabled (output low)

X

X

H

X

Chip disabled (output low)

X

X

X

H

Chip disabled (output low)

= high level,

L

= low level,

X

= irrelevant

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211

TYPE SN10144
256-81T RANDOM-ACCESS MEMORY
recommended operating conditions
B

NOM

A

UNIT

(SEE NOTE 3)

-5.72

Supply voltage, VEE

-5.2

-4.68

25

Width of write pulse, tw(wr) (see Figure 9)

8

Address before write pulse

2

Enable before write pulse

Setup time, tsu (see Figure 9)

Data before end of write pulse

Hold time, th (see Figure 9)

V
ns

Address after write pulse

27t
2

Enable after write pulse

2

Data after write pulse

2

ns

ns

0

Operating ambient temperature, T A

85

°c

tNote that this setup time is referenced to the end of the write pulse. With a minimum·width (25·ns) write pulse, this limit is equivalent to a
2-ns setup time referenced to the start of the write pulse. The setup·time requirement is thus made independent of write pulse width.

electrical characteristics at specified ambient temperature:!:

VIH

VIH'

VIL

VIL'

VOH

VOL

VOH'

VOL'

(SEE NOTES 1 AND 2)

High-level input voltage

High-level input voltage

Low-level input voltage

Low·level input voltage

High-level output voltage

VIH

Low-level output voltage

VIH

High-level output voltage

VIH

Low-level output voltage

IIH

High-level input current

IlL

Low-level input current

lEE

Supply current

B

TEST CONDITIONS

PARAMETER

VIH
E inputs
Other inputs

VI

= VIHS,

= VIHS,

= VIH'S,

= VIH'S,

VIL

VIL

VIL

VIL

= VILA

= VILA

= VIL'A

= VIL'A

= -810 mV,

Other inputs open

= -1850 mV,

E inputs

VI

Other inputs

Other inputs open
All inputs and the output open

TYP

A

UNIT

(SEE NOTE 3)

O°C

-1020

-840

25°C

-980

-810

85°C

-910

-700

O°C

-1145

25°C

-1105

85°C

-1035

mV

mV

O°C

VEE

-1645

25°C

VEE

-1630

85°C

VEE

-1595

O°C

-1490

25°C

-1475

85°C

-1440

O°C

-1000

25°C

-960

-810

85°C

-890

-700

O°C -1870
25°C -1850

-1665

85°C -1825

-1615

mV

mV

-840

-1650

O°C

-1020

-840

25°C

-980

-810

85°C

-910

-700

O°C

-1870

-1645

25°C

-1850

-1630

85°C

-1825

-1595
265

25°C

50

mV

mV

mV

mV

!J. A

0.5
25°C
25°C

-50
-125

!J. A

-90

mA

1. All par,ameters are measured with VEE = -5.200 V, VCC = 0 V, and (unless otherwise noted) the output is connected to
-2.000 V through 50 il.
2. Test conditions stating V lI'.j = V I H B (or V I H'B) and/or V IL = V I LA (or V I L' A) mean that the high-level input voltages are equal
to the B limit of V I H (or V I H ') specified for the particular temperature (see note 3) and/or the low-level input voltages are equal
to the appropriate A limit of V I L (or V I L'). The output voltage limits are guaranteed for any appropriate combination of input
conditions specified by the function table for the desired output.
3. This data sheet uses the algebraic-limit system that has been adopted by the International Electrotechnical Commission. The
A limit is the more positive (less negative) limit; the B limit is the less positive (more negative) limit.
+The ambient temperature conditions assume air moving perpendicular to the longitudinal axis and parallel to the seating plane of the device at
a velocity of 500 feet per minute with the device under test soldered to a 4 x 6 x 0.062-inch double-sided 2·oz copper-clad circuit board.
NOTES:

212

575

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TYPE SN10144
256-81T RANDOM-ACCESS MEMORY
switching characteristics at 25°C free-air temperature
PARAMETER

TEST CONDITIONS

TYP

B

Access time from address

ta(ad)

-

tpLH

A

(SEE NOTE 3)

Propagation delay time, low-to-high-Ievel output from E (enable time)

18

35

8

12

tpHL

Propagation delay time, high-to-Iow-Ievel output from E (disable time)

8

12

tpHL

Propagation delay time, high-to-Iow-Ievel output from read/write

8

17

tTLH

Transition time, low-to-high-Ievel output (20% to 80%)

tTHL

Transition time, high-to-Iow-Ievel output (80% to 20%)

tSR

Sense recovery time

= 3.5 pF,
RL = 50 n,

tw(wr,min)

Minimum width of write pulse

See Figures 6 and 9

2.5

and Note 4

Address before write pulse
tsu(min)

th(min)

NOTES:

Minimum setup time

Minimum hold time

ns
ns
ns
ns

2.5

CL

UNIT

8
15

17

ns

25

ns

-15

8

Enable before write pulse

-8

2

Data before end of write pulse

27

Address after write pulse

8
-3

Enable after write pulse

-8

2

Data after write pulse

-7

2

ns

2
ns

3. This data sheet uses the algebraic limit system that has been adopted by the International Electrotechnical Commission. The A
limit is the more positive (less negative) limit; the B limit is the less positive (more negative) limit.
4. Actual values for the minimum width of write pulse, the three minimum setup times, and the three minimum hold times can each
be determined separately by setting the other six intervals at their A-limit values.

PARAMETER MEASUREMENT INFORMATION

ADDRESS
INPUT
(See Notes A, B, and D)

ENABLE
INPUT
(See Notes A, B, and E)

DEVICE
UNDER
TEST

READ/WRITE
INPUT
(See Notes A and B)

DATA
INPUT
(See Notes A and B)

I_ _ _ _ _--e-_OUTPUT
(See Note B)

I

CL ~ 3.5 pF
(See Note CI

5.2 V

0.1 jJF

NOTES:

A. The input waveforms are supplied by generators having the following characteristics: Zout = 50 n, PRR = 2 MHz. Transition
times of input waveforms are 2 ± 0.1 ns between the 20% and 80% levels and are determined with no device in the socket.
B. The waveforms are monitored on an oscilloscope having the following characteristics: tr .;; 0.35 ns, Rin

= 50 n. I nput and output

cables are equal lengths of 50·n coaxial cable.
C. CL includes jig capacitance.
D. All address lines not under test must be biased to select a memory cell.
E. Enable lines not under test must be at a low logic level.

FIGURE 6- TEST CIRCUIT
575

TEXAS INCORPORATED
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213

TYPE'SN10145
64-BIT RANDOM-ACCESS MEMORY
MAY 1975

•

Fast Access Time ... 9 ns Typical

•

16-Word-by-Four-Bit Organization

•

Drives 50-Ohm Loads

•

Full On-Chip Address Decoding and
Output-Sense Amplification

•

Capability for Wired-OR Connections

•

Low Sensitivity to Supply Voltage Variation

J OR JE
DUAL-IN-LiNE PACKAGE (TOP VIEW)

YO

description
This 64-bit active-element memory is a monolithic
high-speed, emitter-coupled-Iogic (Eel) array of
64 storage cells organized to provide 16 words of four
bits each. This organization and the high speed makes
the SN10145 particularly useful in register file or
small scratch-pad applications. Full address decoding
and output sense amplification are included on the
chip. Each of the 16 words is addressed by the binary
address inputs AO through A3. The output can be
connected to other emitter-follower outputs to
achieve wired-OR word expansion. The SN10145 is
fully compatible with the SN10000 logic family.

II

Information at the data input is written into the
memory by addressing the desired word with the
address lines and taking the read/write input low
while the enable input is held low. The output is
forced low while the memory is in the write mode.

16

VCC

Y1

2

15

Y2

E

3

14

Y3

DO

4

13

R/W

D1

5

12

D3

AO

6

11

D2

A1

7

10

A3

VEE

8

9

A2

functional block diagram

YO}
Yl

DATA

Y'l

OUTPUTS

Y3
~

(13)

AIW

E_'3_1____~--~~----~----------

Information stored in the memory is read out by
holding the read/write line high, selecting the desired
address, and taking the enable input low.
FUNCTION TABLE
READIWRITE ENABLE

H

RMi

E

OPERATION
Write (output low)

L

L

H

L

Read

X

H

Chip disabled (output low)

= high

level, L

= low

level, X

= irrelevant

575

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TYPE SN10145
64-BIT RANDOM-ACCESS MEMORY
recommended operating conditions
B

NOM

A

(SEE NOTE 3)
Supply voltage, VEE

-5.72

Width of write pulse, tw(wr) (see Figure 9)
Address before write pulse
Setup time, tsu (see Figure 9)

Enable before write pulse
Data before end of write pulse

-4.68

V

7.5
3.5

ns

3

ns

7.5
3.5

Address after write pulse
Hold time, th (see Figure 9)

-5.2

UNIT

Enable after write pulse

3
3

Data after write pulse
Operating ambient temperature, T A

ns

0

85

°e

electrical characteristics at specified ambient temperature t

VIH

VIH'

VIL

B

TEST CONDITIONS

PARAMETER

(SEE NOTES 1 AND 2)

A
(SEE NOTE 3)

ooe

-1020

-840

High·level input voltage

25°C

-980

-810
-700

High-level input voltage

85°C
-910
Joe -1145
25°C -1105

Low-level input voltage

UNIT

mV

mV

85°C -1035
oOe
VEE

-1645

25°C

VEE

-1630

85°C
oOe

VEE

-1595
-1490
-1475

mV

Low-level input voltage

25°C

-1440

VOH

High-level output voltage

VIH

= VIHB,

VIL

= VILA

85°C
oOe -1000
25°C
-960
85°C
-890
oOe -1870

-810
-700
-1665

mV

VOL

Low-level output voltage

VIH

= VIHB,

VIL

= VILA

-1650
-1615

mV

VOH'

High-level output voltage

VIH

= VIH'B,

VIL

= VIL'A

25°C -1850
85°C -1825
oOe -1020
25°C
-980

VIL'

VOL'

Low-level output voltage

VIH

Any Data input
High-level
IIH

input current

Read/Write input

= VIH'B.

VIL

= VIL'A

VI = -810 mV,
Other inputs open

Low-level input current

lEE

Supply current

VI

= -1850 mV,

Other inputs open
All inputs and outputs open

-840

-840
-810
-700

85°C
oOe

-910
-1870

25°C

-1850

-1645
-1630

85°C

-1825

-1595

I

mV

mV

220
25°C

470
200

Any Address or E input
IlL

II

mV

J.1.A

25°C

0.5

J.1.A

25°C

-150

mA

= -5.200 V, V CC = 0 V, and (unless otherwise noted) the output is connected to
-2.000 V through 50 fl_
2. Test conditions stating VIH = VIHB (or VIH'B) and/or VIL = VILA (or VIL'A) mean that the high-level input voltages are equal
to the B limit of VI H (or V IH') specified for the particular temperature (see note 3) and/or the low-level input voltages are equal
to the appropriate A limit of V I L (or V I L'). The output voltage limits are guaranteed for any appropriate combination of input
conditions specified by the function table for the desired output.
3. This data sheet uses the algebraic-limit system that has been adopted by the International Electrotechnical Commission. The
A limit is the more positive (less negative) limit; the B limit is the less positive (more negative) limit.
tThe ambient temperature conditions assume air moving perpendicular to the longitudinal axis and parallel to the seating plane of the device at
a velocity of 500 feet per minute with the device under test soldered to a 4 x 6 x 0.062-inch double-sided 2-oz copper-clad circuit board.

NOTES:

1. All parameters are measured with VEE

575

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215

TYPE SN10145
64-BIT RANDOM-ACCESS MEMORY
switching characteristics at 25°C free-air temperature
PARAMETER

TEST CONDITIONS

ta(ad)

Access time from address

tpLH

Propagation delay time, low-to-high-Ievel output from E (enable time)

tpHL

Propagation delay time, high-to-Iow-Ievel output from E (disable time)

tTLH

Transition time, low-to-high-Ievel output (20% to 80%)

tTHL

Transition time, high-to-Iow-Ievel output (80% to 20%)

tSR

Sense recovery ti me

TYP

B

A

(SEE NOTE 3)

6
6

CL = 3.5 pF,

UNIT
ns
ns

9

RL = 50.11,

2.5

See Figures 7 and 9

2.5
7.5

ns
ns

NOTE 3: This data sheet uses the algebraic·limit system that has been adopted by the International Electrotechnical Commission. The A limit
is the more positive (less negative) limit; the B limit is the less positive (more negative) limit.

PARAMETER MEASUREMENT INFORMATION

ADDRESS
INPUT
(See Notes A, B, and D)

ENABLE
INPUT
(See Notes A and B)

II

1--------.- OUTPUT
(See Note B)
DEVICE
UNDER
TEST

READ/WRITE
INPUT
(See Notes A and B)

CL = 3.5 pF
(See Note C)
EACH OUTPUT
NOT UNDER
TEST

DATA
INPUT
(See Notes A and B)

5.2 V
50n
0.1 pF

NOTES:

A. The input waveforms are supplied by generators having the following characteristics: Zout = 50 n, PRR = 2 MHz. Transition
times of input waveforms are 2 ± 0.1 ns between the 20% and 80% levels and are determined with no device in the socket.
B. The waveforms are monitored on an oscilloscope having the following characteristics: tr .;; 0.35 ns, Rin
cables are equal lengths of 50·.11 coaxial cable.
C. CL includes jig capacitance.
D. All address lines not under test must be biased to select a memory cell.

=

50 n. Input and output

FIGURE 7-TEST CIRCUIT

575

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TYPE SN10147
128-811 RANDOM-ACCESS MEMORY
MAY 1975

•

Fast Access Time ___ 15 ns Maximum

•

128-Word-by-One-Bit Organization

•

Full On-Chip Address Decoding and
Output-Sense Amplification

•

Capability for Wired-OR Connections

•

J OR JE
DUAL-IN-L1NE PACKAGE (TOP VIEW)

VCC1

Low Sensitivity to Supply Voltage
Variation

description
This 128-bit active-element memory is a monolithic,
high-speed, emitter-coupled-Iogic (EeL) array of 128
storage celis organized to provide 128 words of one
bit each. Full address decoding and output sense
amplification are included on the chip. An additional
level of decoding is provided for memory systems by
the two enable inputs. Each of the 128 words is
addressed by the binary address inputs AO through
A6. The output can be connected to other emitterfollower outputs to achieve wired-OR word
expansion.

16

VCC2

AO

2

15

DATA OUT

A1

3

14

E2

A2

4

13

E1

A3

5

12

R/Vii

A4

6

11

DATA IN

A5

7

10

A6

VEE

8

9

NC

NC-No internal connection

functional block diagram
Information at the data input is written into the
memory by addressing the desired word with the
address lines and taking the read/write input low
while both enable inputs are held low. The output is
forced low while the memory is in the write mode.
Information stored in the memory is read out by
holding the read/write line high, selecting the desired
address, and taking both enable inputs low.

II

AO (2)

Al

(3)

A2 (4)

ADDRESS
INPUTS

FUNCTION TABLE
READ/

ENABLE

WRITE

E1

H

L

L

L

H

L

L

Read

X

H

X

Chip disabled (output low)

X

X

H

Chip disabled (output low)

= high level,

L

DATA
OUTPUT

OPERATION

E2

Write (output low)

= low level,

X

= irrelevant

575

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217

TYPE SN10147
128-81T RANDOM-ACCESS MEMORY
recommended operating conditions
NOM

B

A

(SEE NOTE 3)
Supply voltage, VEE

-5.72

Width of write pulse, tw(wr) (see Figure 9)

-5.2

-4.68

8
Address before write pulse

Setup time, tsu (see Figure 9)

Hold time, th (see Figure 9)

UNIT
V
ns

4

Enable before write pulse

1

Data before end of write pulse

8

Address after write pulse

3

Enable after write pulse

1

Data after write pulse

1

Operating ambient temperature, T A

ns

ns

0

85

°c

electrical characteristics at specified ambient temperature t
TEST CONDITIONS

PARAMETER

VIH

VIH'

VIL

B

(SEE NOTES 1 AND 2)

High·level input voltage

High-level input voltage

Low-level input voltage

TYP

O°C

-1020

-840

25°C

-980

-810

85°C

-910

-700

O°C

-1145

25°C

-1105

85°C

-1035

II

VOH

VOL

VOH'

VOL'

Low-level input voltage

High-level output voltage

VIH = VIHB,

Low-level output voltage

VIH = VIHB,

High-level output voltage

VIH = VIH'B,

Low-level output voltage

IIH

High-level input current

IlL

Low-level input current

lEE

Supply current

VIH = VIH'B,

IRead/Write

IOther inputs

VIL = VILA

VIL = VILA

VIL = VIL'A

VIL = VIL'A

VI = -810mV,
Other inputs open
VI = -1990 mV,
Other inputs open
All inputs and the output open

UNIT

mV

mV

O°C

VEE

-1645

25°C

VEE

-1630

85°C

VEE

-1595

O°C
VIL'

A

(SEE NOTE 3)

mV

-1490

25°C

-1475

85°C

-1440

O°C

-1000

-840

25°C

-960

-810

85°C

-890

-700

O°C

-2000

-1665

25°C

-1990

-1650

85°C

-1920

-1615

O°C

-1020

-840

25°C

-980

-810

85°C

-910

-700

O°C

-2000

. -1645

25°C

-1990

-1630

85°C

-1920

-1595
355

25°C

265
25°C

0.5

25°C

-100

mV

mV

mV

mV

mV

)J.A
)J.A

-85

-50

mA

1. All parameters are measured with VEE = -5.200 V, V CC1 = V CC2 = 0 V, and (unless otherwise noted) the output is connected
to -2.000 V through 50 n.
2. Test conditions stating V I H = VIH B (or V IH'B) and/or V I L = V I LA (or V I L' A) mean that the high-level input voltages are equal
to the B limit of VIH (or VIH') specified for the particular temperature (see note 3) and/or the low-level input voltages are equal
to the appropriate A limit of V I L (or V I L'I. The output voltage limits are guaranteed for any appropriate combination of input
conditions specified by the function table for the desired output.
3. This data sheet uses the algebraic·limit system that has been adopted by the International Electrotechnical Commission. The
A limit is the more positive (less negative) limit; the B limit is the less positive (more negative) limit.
tThe ambient temperature conditions assume air moving perpendicular to the longitudinal axis and parallel to the seating plane of the device at
a velocity of 500 feet per minute with the device under test soldered to a 4 x 6 x 0.062-inch double-sided 2-oz copper-clad circuit board.

NOTES:

575

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TYPE SN10147
128-811 RANDOM-ACCESS MEMORY

switching characteristics at 25° C free-air temperature
PARAMETER

TEST CONDITIONS

ta(ad)

Access time from address

tpLH

Propagation delay time, low-to-high-Ievel output from E (enable time)

B

A

(SEE NOTE 3)
15

tpHL

Propagation delay time, high-to-Iow-Ievel output from E (disable time)

tTLH

Transition time, low-to-high-Ievel output (20% to 80%)

tTHL

Transition time, high-to-Iow-Ievel output (80% to 20%)

tSR

Sense recovery time

CL
RL

= 3.5 pF,
= 50.11,

See Figures 8 and 9

3

8.5

3

8.5

1

2.5

1

2.5
10

UNIT
ns
ns
ns
ns

NOTE 3: This data sheet uses the algebraic-limit system that has been adopted by the International E lectrotechnical Commission. The A limit
is the more positive (less negative) limit; the B limit is the less positive (more negative) limit.

PARAMETER MEASUREMENT INFORMATION

ADDRESS
INPUT
(See Notes A, B, and D)

ENABLE
INPUT
(See Notes A, B, and E)

READ/WRITE
INPUT
(See Notes A and B)

DATA
INPUT
(See Notes A and B)

VCC1

DEVICE
UNDER
TEST

a

OUTPUT
(See Note B)

CL = 3.5 pF
(See Note C)

VEE

O.lI1F

NOTES:

A. The input waveforms are supplied by generators having the following characteristics: Zout = 50 .11, P R R = 2 MHz. Transition
times of input waveforms are 2 ± 0.1 ns between the 20% and 80% levels and are determined with no device in the socket.
B. The waveforms are monitored on an oscilloscope having the following characteristics: tr .;;; 0.35 ns, Rin = 50 n. Input and output
cables are equal lengths of 50·.11 coaxial cable.
C. CL includes jig capacitance.
D. All address lines not under test must be biased to select a memory cell.
E. Enable line(s) not under test must be at a low logic level.
FIGURE 8-TEST CIRCUIT

575

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POST OFFICE BOX 5012

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219

SERIES SN10000
MEMORIES
PARAMETER MEASUREMENT INFORMATION
ADDRESS
INPUTS

-- '"'"" ,

r -/50%

,50%

I

~

___ _

- .../1

I

I-

I--- tsu -----1
I

ENABLE
INPUTS

tsu

----L--

------------.
READ/WRITE

te--- tsu
I

I
"~V

-- - - - - -

~~~

I

I.-

- - - +1110mV

I ,,~%
~
'-,- - - -

-

+310 mV

---I
(SeeNoteB))~
I

i--tSR

~'"
~O%

/-50%

- - - - --

------'

+310mV

---.jr-----th
_ _I

!7\5..0%
-----------~.
'- - tpHL -eo!

/_

+310 mV

~O%

/1""= _____

~
1

I

I

I

I- th--l
tw(wr) -..., ,r------ +1110 mV

"J.... 55(0%

INPUT

DATA
OUTPUT

+1110mV

1

I

t--

DATA
INPUT

+310 mV

th-l

I
I
I '-_____~-------I:___--"~ - - I

+1110mV
(See Note AI

--

WRITE CYCLE VOLTAGE WAVEFORMS

•

__
ADDRESS
INPUTS
(See Note C)

~2~:2...n2.... _ _ _

1-+2±0,lns

80~,
I

80%
+50%

80%

I

I

: -h22 £. ____
0

I

~S _ _ ~oU

:

+1110 mV
+310 mV

I

~

I+- ta(adl

';80%
+50%
20%

Ioe---- ta(adl~

I

I

DATA
OUTPUT

180%~0%1
I
I
50%

~
50%
20% I

I

:

I

I

I

~tTLH

20%
I

~tTHL

ACCESS TIME FROM ADDRESS INPUTS

L.-..t- 2

ENABLE
INPUTS
(See Note 01

'I

~
80~%

f-+2 ± 0.1 ns

± 0.1 ns

I

+1110 mV

Wc

:

20%

,20%

180%
I
50%
1

1 - - - - - -+310mV

I

~ tPLH--j
I

DATA
OUTPUT

0

50%

_ _ _ _ _ _~2~0~%

I

I

80%~
50%

' 8 0%
I
:

1

I

I

I

20%
I
I

~tTHL

r---;-tTLH
ENABLE AND DISABLE TIMES
NOTES:

A.
B.
C.
D.

Voltage values on input waveforms are with respect to ground.
Sense recovery time can ofJly be measured following the writing of a high-level input.
All enable inputs are low, read/write input is high.
Read/write input is high, other enable input(s) is(are) low, bit location addressed contains high-level data.

FIGURE 9-VOLTAGE WAVEFORMS

575

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SERIES SN10000
MEMORIES
TYPICAL CHARACTERISTICSt
HIGH~LEVEL

AND LOW·LEVEL
OUTPUT VOLTAGES

HIGH·LEVEL and LOW·LEVEL OUTPUT VOLTAGES
SUPPL Y VOLTAGE

AMBIENT TEMPERATURE
VEE = -5.2 V
-0.2 LOAD = 50 ~ 10 -2 V
1--1-10_14,:O--,o-,nI.:.:Yi--+---+---(
-0.4 f----r----r(9-,-0rll,--f.:,.o'...::S-,-Nr:

1
g

-0.6
-0.8

-0.2

-0.4 t--~t-----(I-----(I-----(------f~----l

f---+--+---+---+~I--+--+---+---+---(

>

~ - - - V6H

-0.6 t--~t-----(,----(----(------f--j
-0.8

"0

-1.0 f---+--+---+--+--I--+--+--t---+---(

>

VOH

-1.0

a. -1.2

-1.2 I-+--+--+--+~t--+--+--+---+---(

o

0

-1.4

I-+--+--+--+~t--+-+-+---+---(

-1.6

f---+--+---+---+~I--+--+---+---+---(

-1.6

VOL
-1.8 Fof=+~----:;;~t--+-+-+-t--1

-1.8

-2.0 0

10

20 30

LOAD = 50 II 10 -2 V
T A = 25"C

40

50 60

-1.4

VOL

-2.0
-5.8

70 80 90 100

~~

~.4

lA-Ambient Temperature-OC

~2

~~

~.8

~~

VEE-Supply Vollage-V

FIGURE 10

FIGURE 11

OUTPUT VOLTAGE

INPUT CURRENT

OUTPUT CURRENT

INPUT VOLTAGE

-0.6

300
VEE = -5.2 V
TA = 25°C

-0.8
250

> -1.0

~


0

I

-1.4

u

-1.6

I1-

0

> -1.8

200
150

--

50

-2.0

o

-2.0

-5 -10 -15 -20 -25 -30 -35 -40 ~5 -50

f-

-1.6

TRANSITION TIME,
OUTPUT

:
J

w 3.0 1----'

_~

SUPPLY VOLTAGE

Y 4.0 r-~r-~r-~r-~r----'r----'

CL

=

~

3.5 pF

- T A = DoC 10 85°C

2.5

~

2.0

E'

1.5

--J----+-----t--t----r---

1.0

I-~I__~I__~t__~t__~I__-----j

0.5

r----I----r---

3~ pF

3.5 t-----(------f--TA

=

DoC to 85"C

~

2.5

I--~t__~t__~t--~t__---(I-----(

-§,

2.0

~=I==F===F==F==1==--.j

E'

1.5 t--~t--~t__~t---.t-----('-----(

S

-1----

i

i=

3.0

I

f---~I__~I__~St-ee-F-ig-ut-res-M-7....,ar-nd-M-9--1

90%

t~ 10%

i=

:~

~

--t-~--t-----1

1.0

i! 0.5

t__~I--~t-----(I-----(------f~-----f

t-

I

~

bL

=

<5

!

~~~_~~t-'e~~~

______
10% to 90%

I

.=

-0.4

vs

SUPPL Y VOLTAGE
4.0 r-~r-~r-~r-~-~-----'

J- --- ---

-0.8

TRANSITION TIME,
HIGH·TO·LOW·LEVEL OUTPUT

LOW·TO~HIGH·LEVEL

3.5

-1.2

FIGURE 13

FIGURE 12

o

!

VI-Inpul Vollage-V

la-Output Current-rnA

I

II

)

100

~

:I:

-5.8

-5.6

-5.4

-5.2

-5.0

-4.8

!:"

-4.6

-5.8

-5.6

-5.4

-5.2

-5.0

VEE-Supply Vollage-V

VEE-Supply Vollage-V

FIGURE 14

FIGURE 15

-4.8

-4.6

tThe ambient temperature conditions assume air moving perpendicular to the longitudinal axis and parallel to the seating plane of the device at
a velocity of 500 feet per minute with the device under test soldered to a 4 x 6 x 0.062-inch double-sided 2-oz copper-clad circuit board.

575

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221

ECl MEMORIES MECHANICAL DATA

MECHANICAL DATA AND ORDERING INSTRUCTIONS

general
The availability of a particular Series SN10000 part in a particular package is denoted by an alphabetical reference
above the pin-connection diagrams. Series SN10000 memories are available in the J and JE ceramic packages. Orders for
these circuits should include the package outline letter(s) (J or JE) at the end of the circuit type number; e.g.,
SN10139J, SN10145JE.

JE ceramic dual-in-line package

J ceramic dual-in-line package
This hermetically sealed, dual-in-line package consists
of a ceramic base, ceramic cap, and 16-lead frame.
The
package is intended for
insertion in
mounting-hole rows on O.300-inch centers. Once the
leads are compressed to O.300-inch separation,
sufficient tension is provided to secure the package in
the board during soldering. Tin-plated (bright-dipped)
leads require no additional cleaning or processing
when used in soldered assembly.

II

This ceramic dual-in-line package has 16 leads
attached by brazing and a gold-plated lid hermetically
sealed to the header at relatively low temperature
using a solder preform. The package is intended for
insertion in mounting-hole rows on O.300-inch
centers. The gold-plated leads require no additional
cleaning or processing when used in soldered or
welded assembly.

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PIN SPACtNG 0.100 TP

ISeeNoteal

NOTES:

a. Each pin centerline is located within 0.010 inch of its
true longitudinal position.
b. All dimensions are in inches unless otherwise noted.

NOTES:

a. Terminal identification is provided by either a notch
with a nominal radius of 0.032 inch or a dot on the
body near the number-one terminal.
b. Each pin centerline is located within 0.010 inch of its
true longitudinal position.
c. All dimensions are in inches.

PRINTfD IN US A

222

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575

TI (annat assume any responsibility for any (i"uits shown
or represent that they are free from potent infringement.

TEXAS INSTRUMENTS RESERVES THE RIGHT TO MAKE CHANGES AT ANY TIME
IN ORDER TO IMPROVE DESIGN AND TO SUPPLY THE BEST PRODUCT POSSIBLE.

Microprocessor
Summary
II
I

223

SBP0400
4-BIT BINARY PROCESSOR ELEMENT

II

224

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SBP0400
4-BIT BINARY PROCESSOR ELEMENT

SBP0400
4-bit slice microprogrammable
microprocessor element.
Integrated Injection Logic.
.... from Texas Instruments.
The SBP0400 is a digital processor
building block and the first of the
standard Integrated Injection Logic
(FL) ICs from TI.
The 0400 combines the unique
properties of FL technology with an
expandable 4-bit slice architecture
to offer an unmatched level of performance and design flexibility.
It's microprogrammable. You
build instructions by externally
sequencing the 0400's factory-programmed micro-operations. Emulate existing designs, at either the
micro or macro level, with software
compatibility. Or create highly efficient new designs with tailored
instructions.
With over 1,600 gates, monolithically integrated into a 40-pin package, the 0400 offers the basis for
efficient, low cost design solutions to
a host of applications in both industrial (0° to 70°C) and military (-55° to
125°C) environments.
The SBP0400 is also directly expandable to any word size which is a
multiple of 4-bits.
Some examples: One SBP0400
can make a basic 4-bit intelligent
controller. Two, in parallel, makes
an 8-bit dedicated processor. Three
makes a 12-bit controller. And, with
four- the CPU of a general purpose
16-bit "mini".
SBP0400 is characterized by the
ability to perform anyone of its 512
preprogrammed micro - operations
within a single clock cycle.

Basic Architecture
• Microprogrammable, bit·slice design
expandable in 4·bit multiples.
• Parallel access to all control, data and
address functions.
• 16·function ALU with full'carry look
ahead capability.
• a·word general register file including
independent program counter
with incrementor.
• Dual4-bit working registers with full
shilling capability.
• On-chip factory programmable logic array
(PLA) contains a repertoire of 512
micro·operations.

Functional Power
• Static edge-triggered operation with full
TTL compatibility.
• ALU operand modifications/combination
via a arithmetic or a Boolean functions.
• Bidirectional logic/arithmetic shift/circulate
of single/double signed, single/double
precision binary words.
• Single clock ALU·shift combinations simplify
implementation of iterative multiply and
non-restore divide algorithms.
• Internal operation register and independent
program counter provide pipelining
capability.

Performance: The SBP0400 operates
at a constant speed X power product
over a 10:' performance range. Virtually any single DC power source,
voltage or current, can be used.
Speed is a direct function of supply current. As the graph shows:
For typical microcycle times of one

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microsecond,just over100 milliamps
of total supply current is required.
Any point along the constant speed
X power plot can be chosen. Down to
one microamp of total supply current for corresponding microcycles
of 100 milliseconds.
INJECTOR CURRENT

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Icc-lnjectorCurrenl-mA

Design with the 0400 and the
choice is yours: Word size. Instruction set. Power and speed. Use your
imagination. The SBP0400 is just
the beginning.
Engineering evaluation devices
are available now. Designated
X0400N, they are $90.00 each 0-24).
Order directly from your nearest TI
Sales Office. A product manual
accompanies purchase. For a "MiniSpec" write Texas Instruments
Incorporated, P.O. Box ~
5012 MIS 308, Dallas,
TJ
Texas 75222.

225

TMS 1000 NCr TMS 1200 NC
MICROCOMPUTERS

DESCRIPTION
The TMS1000 series is a family of P-channel MOS four-bit microcomputers with a ROM, a RAM, and an arithmetic
logic unit on a single semiconductor chip. The TMS1000 family is unique in the field of microprocessors because this
device is a single-chip binary computer. A customer's specification determines the software that is reproduced during
wafer processing by a single-level mask technique that defines a fixed ROM pattern. This versatile one-chip computer is
very cost effective and capable of performing a variety of complex functions.
Key features of the TMS1000 series are:
•

8192-bit Read-Only Memory (ROM) on chip

•

256-bit Random-Access Memory (RAM) on chip

•

Four-bit parallel data input

•

11 latched control/data-strobe outputs in a 28-pin package

•

Programmable instruction decoder

•

Conditional branching and subroutines

•

13 latched control/data-strobe outputs in a 40-pin package

•

Single-power-supply operation

•

8 parallel data outputs and output programmable logic array (PLA)

•

TTL compatible

•

Arithmetic Logic Unit (ALU) and 2 four-bit working registers on chip

•

~----------------~

TMS1000SERIES

DEVICE

On-chip oscillator, or external synchronization if desired

R OUPUTS
111 OR 13 BITS)

ROM
1024 WORDS
8 BITSIWORD

R-OUTPUT
LATCH
110 BUFFER

PACKAGE

TMS1000NC

28-Pin DIP

TMS1200NC

40-Pin DIP

RAM
64 WORDS
4 BITSIWORD

K INPUTS
14 BITS)

o OUTPUTS
(BBITS)

TMS1000-SERIES LOGIC BLOCKS

One major advantage of the TMS1000 series is flexibility. The TMS1000 series is effective in applications such as
printer controllers, data terminals, remote sensing systems, cash registers, appliance controls, and automotive
applications. Through the TMS1000 series versatility, a wide range of systems realize reduced costs, fewer parts, and
high reliability.
The microcomputer's ROM program controls data input, storage, processing, and output. Data processing takes place in
the arithmetic logic unit. K input data goes into the ALU, as shown in the figure above, and is stored in the four-bit
accumulator. The accumulator output accesses the output latches, the RAM storage cells, and the adder input. Data
storage in the 256-bit RAM is organized into 64 words, four bits per word. The four-bit words are conveniently grouped
into four 16-word files addressed by a two-bit register. A four-bit register addresses one of the 16 words in a file by
ROM control.
The 0 outputs and the R outputs are the output channels. The eight parallel 0 outputs are decoded from five data
latches. The 0 outputs serve many applications because the decoder is a programmable logic array (PLA) that is
modified by changing the gate-level mask tooling. Each of the thirteen R outputs of the TMS1200NC and the eleven R

226

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TMS 1000 NCr TMS 1200 NC
MICROCOMPUTERS
outputs on the TMS1000NC has an individual storage
element that can be set or reset by program control.
The R outputs send status or enable signals to
external devices. The R outputs strobe the outputs
to displays, to other TMS1 000 series chips, or to TTL
and other interface circuits. The same R outputs
mUltiplex data into the K inputs whenever necessary.

°

There are 43 basic instructions that handle I/O,
constant data from the ROM, bit contrOl, internal
data transfer, arithmetic processing, branching, looping, and subroutines. The eight-bit instruction word
performs 256 unique operations for maximum
efficiency.
DESIGN SUPPORT
Through a staff of experienced application programmers, Texas Instruments will, upon request,
assist customers in evaluating applications, in training
designers to program the TMS 1000 series and in
simulating programs. TI will also contract to write
programs to customer's specifications.
TI has developed an assembler and simulator for
aiding software designs. These programs are available
on nationwide time-sharing systems and at TI
computer facilities.

..

A TMS 1000 series program (see flowchart) is written
in assembly language using standard mnemonics. The
assembler converts the source code (assembly
language program) into machine code, which is
transferred to a software simulation program. Also
the assembler produces a machine code object deck.
The object deck is used to produce a tape for
hardware simulation or a tape for generating prototype tool ing.

I

The TMS1000 series programs are checked by software and hardware simulation. The software
simulation offers the advantages of printed outputs
for instruction traces or periodic outputs. The
hardware simulation offers the designer the
advantages of real-time simulation and testing asynchronous inputs. A software user's guide is available.
After the algorithms have been checked and approved
by the customer, the final object code and machine
option statements are supplied to TI. A gate mask is
generated and slices produced. After assembly and
testing, the prototypes are shipped to the customer
for approval. Upon receiving final approval, the part
is released for volume production at the required rate
as one unique version of the TMS1000 family.

TMS1000-SERIES ALGORITHM DEVELOPMENT

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227

TMS 8080, TMS 5501
8-BIT MOS MICROPROCESSOR SYSTEM
TMS 8080
An Eight-Bit Central Process Unit

•
•
•
•
•

II

•
•
•
•
•

2-J..Ls Instruction Cycle Time

Addresses up to 65,536 Words of Memory
8-Bit Bidirectional I/O Bus
Serves up to 256 Input and 256 Output Ports
Uses a Memory Stack for Subroutine Saves

8 Vectored Interrupts
9 Internal Registers
78 Instructions
Power Supplies: 12 V, 5 V, 0 V, -5 V
TTL-Compatible

TMS 5501
A multifunction input/output circuit that is
controlled by the TMS 8080 through
memory
referencing instructions. The
TMS 5501
provides
a
TMS 8080
microprocessor system with a synchronous
data interface, data I/O buffers, interrupt
control logic, and interval timers. The
TMS 8080 causes data to be transferred by
the TMS 5501 by issuing commands via the
system address bus. These commands
include:

•
•
•
•
•
•
•
•
•
•
228

read the serial receive register
read the external data input lines
read the interrupt address
read TMS 5501 status information
issue discrete commands
load baud-rate register
load the serial transmiter register
load the output register
load the interrupt mask
load an interval timer

INT8SYN
CE
C

CONTROL
AOA3

4

SENS

1'fC'J

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38510/MACH IV
High-Reliability Microelectronics
Procurement Specifications

MIL-STD-883

a

229

CONTENTS
SECTION
1.0
2.0
3.0
4.0
5.0
6.0

..

230

PAGE
SCOPE.... . . . . .
APPLICABLE DOCUMENTS
GENERAL REQUIREMENTS
QUALITY ASSURANCE PROVISIONS
PREPARATION FOR DELIVERY
NOTES . . . . . . . . . . . . .

233
233
235
245
256
257

REVISIONS
CLASSIFICATION
(MAJOR/MINOR)

DATE CODE EFFECTIVITY

LTR

DESCRIPTION

Major

7040

A

Incorporate MIL-M-38510 and Revision Notice 2
of M I L-STD-883

Major

7239

B

Incorporate Revision Notice 3 and 4
of M I L-STD-883 and Revision A of
M I L-STD-3851 0

Major

7401

C

Incorporate revised Level IV (SNH)
processing with inclusion of recorded
electrical data with delta requirements;
incorporate technological criteria in
Table III for precap of complex circuits.

Minor

7518

0

Incorporate Revision A of
M I L-STD-883 and provisions
for MaS LSI and CMOS devices

1/1/74

~~

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3}

4/15/75

a
I

UNLESS OTHE RWISE SPECIFI ED
DIMENSIONS ARE IN INCHES
TOLERANCES:
ANGLES ± 1°
3 PLACE DECIMAL i.OlO
2 PLACE DECIMAL %.02
INTERPRET DWG. IN
ACCORDANCE WITH STD.
DESCRIBED IN MIL-STD-100

~

TEXAS INSTRUMENTS
INCORPORATED

SEMICONDUCTOR CIRCUITS DIVISIOI\J DALLAS, TEXAS

MICROELECTRONICS, HIGH RELIABILITY
PROCUREMENT SPECIFICATION
(MIL-STD 38510/883)

MATERIAL:
CODE IDENT NO. .

SHEET

231

..

232

38510/MACH IV PROCUREMENT SPECIFICATION

38510/MACH IV PROGRAM
1.0

SCOPE

1.1

This specification establishes standards for materials, workmanship, performance
capabilities, identification, and processing of high-reliability monolithic integrated
circuits.

1.2

Intent
The intent of this document is such as to recognize that quality and reliability are built into,
not tested into, a product. There is no specification or screening procedure that can
substitute for inherent, built-in reliability. However, it must be realized that irrespective of
lot quality, there will always be some small percentage of devices that are subject to early
failure (infant mortality). A well engineered screening procedure will eliminate most, if not
all, of these early failures. Secondly, the screening and acceptance testing described herein
will also serve to demonstrate, with a high degree of statistical confidence, that the required
levels of quality and reliability have, in fact, been built into the product.

2.0

APPLICABLE DOCUMENTS

2.1

The following specifications and standards, of the issue in effect on the date of invitation
for bids or request for proposal, form a part of this specification to the extent specified
herein:

2.2

Specifications

11

Military

M I L-M-55565
MI L-M-38510

Microcircuits, Packaging of
Microcircuits devices, general specification for

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233

385l0/MACH IV PROCUREMENT SPECIFICATION

2.3

Standards
Military
MI L-STD·1 05

Sampling Procedures and Tables for
Inspection by Attributes

MI L-STD·883

Test Methods and Procedures for
Microelectronics

MI L-STD-790

Reliability Assurance Program for
Electronic Parts Specification

MIL-STD-1276

Leads, Weldable, for Electronic
Components Parts

MI L-STD-1313

Microelectronics Terms and Definitions

Detail Specifications
SNXXXX (Bipolar)
TMSXXXX (MaS LSI)
TFXXXX (CMOS)

2.4

Detail Specification for a Particular
Part Type (e.g., Manufacturer's
Data Sheet)

Precedence of Documents
For the purpose of interpretation, in case of any conflicts, the following order of
precedence shall apply:

II

2.5

234

a)

Purchase Order

- The purchase order shall have
precedence over any referenced
specification.

b)

Detail Specification

-The detail specification shall have
precedence over this specification
and other referenced specifications.

c)

Th is Specification

- This specification shall have
precedence over all referenced
specifications.

d)

Referenced
Specifications

-Referenced Specifications shall apply
to the extent specified herein.

Federal and/or military specifications and standards required shall be obtained from the
usual government sources.

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38510/MACH IV PROCUREMENT SPECIFICATION

3.0

GENERAL REQUIREMENTS
The individual item requirements shall be as specified herein and in accordance with the
applicable detail specification. In the event of any conflict between the requirements of this
specification and the detail specification, the latter shall govern. The static and dynamic
electrical performance requirements of the integrated circuits plus absolute maximum
ratings and test methods shall be as specified in the detail specifications.

3.1.1

3.1.2

Definitions
a)

LTPD

Lot Tolerance Percent Defective shall be as
defined by MI L-M-38510.

b)

A

Lambda, stated in percent per 1000 hours as
defined by MI L-M-38510.

c)

MRN

Minimum reject number as defined by MI L-M-3851 O.

d)

Production
Lot

For the purpose of this specification, a production
lot shall be defined per MIL-M-38510.

e)

Inspection
Lot

An inspection lot shall be as defined in
MI L-M-38510.

f)

C

Acceptance number as defined by MI L-M-3851 O.

Terms and Definitions
Terms and definitions shall be as defined in MI L-STD-1313.
I

3.1.3

II

Classification of Requirements
The requirements for the integrated circuits are classified herein as follows:
Requirement

Paragraph

Process Conditioning, Testing and Screening

3.2

Qual ification

3.3

Design and Construction

3.4

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235

38510/MACH IV PROCUREMENT SPECIFICATION

3.2

Marking of I ntegrated Circuits

3.5

Product Assurance

3.6

Workmanship

3.7

Performance Capabilities

3.8

Quality and Reliability Assurance Program Plan

3.9

Process Conditioning, Testing and Screening
Three levels of screening and quality assurance for integrated circuits are provided for in this
specification. Process conditioning, testing and screening shall be as specified in 4.3 and the applicable
figure for the appropriate quality assurance level stated on the purchase order and defined as follows:

SCREENING LEVEL
38510/883 Class A (Level IV)
38510/883 Class B (Level III)
38510/883 Class C (Level I)

3.3

PART NUMBER PREFIX
BIPOLAR
CMOS
MOS LSI
SNH
TFH
Not Avail.
TFC
SNC
SMC
SNM
TFM
Not Avail.

APPLICABLE
FLOW CHART
Figure 4
Figure 3
Figure 2
Figure 1

Qualification
Vendor qualification for delivery of integrated circuits to this specification shall be as
specified in paragraph 4.2.

3.4

II

Design and Construction
Integrated circuit design and construction shall be in accordance with the requirements
specified herein and in the applicable detail specification.

3.4.1

Topography
Integrated circuits furnished under this specification shall have topography information
available for review by procuring activity. The information made available shall provide
sufficient data for thorough circuit design, application, performance, and failure analysis
studies.

3.4.1.1

Monolithic Die Topography
An enlarged photograph or drawing (to scale) with a minimum magnification of 80 times
the die (chip) size showing the topography of elements formed on the silicon monolithic die
shall be available for review. This shall be identified with the specific detail integrated circuit
part-type in which it is used and the applicable detail specification.

236

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OPERATION

APPLICABLE
PARAGRAPH

OPERATION

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FIGURE 1-FLOW CHART FOR 38510 CLASS C LEVEL I

FIGURE 2-FLOW CHART FOR MOS LSI
38510 CLASS B (LEVEL III SMC)

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APPLICABLE
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FIGURE 3-FLOW CHART FOR 38510 CLASS B LEVEL III

FIGURE 4-FLOW CHART FOR 38510 CLASS A LEVEL IV

38510/MACH IV PROCUREMENT SPECIFICATION

3.4.1.2

Die Intraconnection Pattern
An enlarged photograph or drawing (to scale) with a minimum magnification of 80 times
the die (chip) size showing the specific intraconnection pattern utiliied to intraconnect the
elements in the circuit. This shall be in the same scale as the die topography 3.4.1.1 so that
the elements utilized and those not being used can easily be determined.

3.4.2

Materials
Materials shall be inherently non-nutrient to fungus and shall not blister, crack, outgas,
soften, flow or exhibit other immediate or latent defects that adversely affect storage,
operation or environmental capabilities of integrated circuits.

3.4.2.1

Material Selection
Materials selected for use in the construction of the integrated circuits shall be chosen for
maximum suitability for the application. This shall include consideration of the best balance
for:

3.4.2.2

a)

Electrical performance

b)

Thermal compatibility and conductivity

c)

Chemical stability including resistance to deleterious interactions with other
materials

d)

Metallurgical stability with respect to adjacent materials and change in crystal
configuration

e)

Maximum stability with regard to continued uniform performance through the
specified environmental conditions and life.

•

Foreign Materials
No lacquer, grease, paste, desiccant or other similar foreign encapsulant or coating material
shall be included in the circuit enclosure nor applied to any part of the internal circuit
assembly.

3.4.3

Mechanical

3.4.3.1

Case
Each integrated circuit shall be securely mounted and hermetically sealed within a case
designed and constructed to conform to the outline and physical dimensions shown in the
detailed specification.

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239

I

38510/MACH IV PROCUREMENT SPECIFICATION

3.4.3.2

Interconnections
Interconnections within the integrated circuit case shall be minimized and there shall
be no wire crossovers. Circuit intraconnections by means of wire jumpers shall not be
used. (See Note 6.2)

3.4.3.3

Leads
Lead material, construction, and outline shall be as specified on the detail specification and
shall be capable of meeting the solderability test of MI L-STD-883, Method 2003. (See
note 6.4).

3.4.3.3.1 Lead Size
Lead outline and dimensions shall be as specified in the detail specification.
3.4.3.3.2 Lead Surface Condition
Leads shall be free of the following defects over their entire length when inspected under a
minimum of 4X magnification:

•

a)

Foreign materials adhering to the leads such as paint, film, deposits and dust.
Where adherence of such foreign materials is in question, leads may be sUbjected
to a clean, contaminant-free (e.g., oil, dust, etc.), filtered air stream (suction or
expulsion) of 88 feet per second maximum, or a wash/rinse as necessary and
reinspected.

b)

Nicks, cuts, scratches or other surface defacing defects which expose the base
metal.

3.4.3.3.3 Lead Straightness
Leads shall be aligned within a 0.050-inch diameter, 0.050-inch length cylinder concentric
to the point of lead emergence from the case and the X-axis (the axis parallel to the lead
axis). Along the remaining lead length, there shall be no unspecified bend whose radius is
less than 0.10 inch and no twist whose angle is greater than 30° (ribbon leads, only).
3.4.3.3.4 Preformed Leads
Preformed leads, when specified, shall be in accordance with the detail specification. The
part number of the integrated circuit shall remain as specified in the applicable detail
specification or purchase order, the applicable suffix designation shall appear on the
purchase order but shall not be marked on the device.

240

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38510/MACH IV PROCUREMENT SPECIFICATION

3.4.3.3.5 Carriers (Mech-Pak Carrier)
Carrier-matrix assemblies consisting of individually mounted integrated circuits shall be
furnished when so specified by purchase order. The individual carriers shall have provisions
for use with automatic test equipment contacts. Devices supplied "clipped-out" of the
Mech-Pak Carrier shall be supplied in the Barnes Carrier type 029-188 or equ ivalent.
(Applicable to Flat Packs only.)
3.5

Marking of Integrated Circuits

3.5.1

Legibility
All marking shall be permanent in nature and remain legible when subjected to specified
operating, storage, and environmental requirements. All markings shall be insoluble in
standard solvents such as trichlorethylene, water and xylene.

3.5.2

Marking Details
Marking of the integrated circuits shall be located as follows unless otherwise specified in
the detail specification:

3.5.3

a)

TO-99, TO-1 00, and similar "can" cases shall be marked on the top of the case.
Where space limitations exist, the side of the case may be used.

b)

Flat Packs shall be marked on the top of the case. Where space limitation exists,
the bottom of the package may be utilized as necessary. As a minimum the top of
the package shall show the manufacturer's identification mark or symbol, the
device part number, date code, and pin 1 orientation mark (where applicable).

c)

Dual-in-line plug-in packages shall be marked in the same manner as flat packs.

a

Required Device Marking
a)

Index point indicating the starting point for numbering of leads shall be as
indicated in the detail specification. The indexing point may be a tab, color dot,
or other suitable indicator.

b)

Manufacturer's identification mark or symbol.

c)

An alpha-numeric lot date code indicating the week of initial submission for
screening or inspection. The date code shall be as follows:
1)

EIA four-digit date code, the first two numbers shall be the last two
digits of the year, the last two numbers shall indicate the calendar
week.

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2)

A Gothic letter which identifies separate lots of the same device type
processed within the same calendar week. (If no more than one lot is
processed through screening or inspection in a given calendar week, the
Gothic letter may be omitted.)

d)

Manufacturer's part number defining circuit type and applicable
MI L-STD·883 screening level and MI L-M·38510 product assurance level as
defined in paragraph 3.2.

e)

Individual device serial number is required for Class A (SNH).

f)

A dot to indicate acceptance by Radiographic inspection
NOTE:
When a color dot is used to identify pin one, the radiographic inspection
acceptance dot shall be placed on the bottom of the package.

g)

3.6

Gothic letter per U.S. Customs code preceding data code identifies assembly
location.

Product Assurance
The manufacturer shall establish and maintain a reliability assurance program that complies
with the basic intent of MI L-STD-790. Furthermore, it is intended that each integrated
circuit delivered shall be free of any defect in design, material, manufacturing process,
testing and handling, which would degrade or otherwise limit its performance when used
within the specified limits.

3.6.1

Visual and Mechanical Examination
I ntegrated circuits shall be examined to verify that material, design, construction, physical
dimensions, marking and workmanship are in accordance with the specified acceptance
criteriCl.

II

3.6.2

Test Equipment
The manufacturer shall prepare and maintain a current list, by name and drawing number or
other unique identification, of test equipment used in the manufacturing and testing of
devices submitted for acceptance inspection under this specification. This list shall be made
available to the procuring activity representative upon request.

3.6.3

Process Controls
Each integrated circuit shall be constructed by manufacturing processes which are under the
surveillance of the manufacturer's Quality Control department. The processes shall be
monitored and controlled by use of statistical techniques in accordance with published
specifications and procedures. The manufacturer shall prepare and maintain suitable
documentation (such as quality control manuals, inspection instructions, control charts,
etc.) covering all phases of incoming part and material inspection and in-process inspections
required to assure that product quality meets the requirements of this specification. The

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procuring activity may verify, with the permission of and in the company of the
manufacturer's designated representative, that suitable documentation exists and is being
applied. Information designated as proprietary by the manufacturer will be made available
to the procuring activity or its representative only with the written permission of the
manufacturer.

Process control is recognized as being vital to the concept of "built-in" quality. The
process control program shall include a scanning electron microscope (SEM) monitor
program for evaluating the metal integrity over oxide step and oxide step contour.
The SEM analysis will be defined in a Quality & Reliability Assurance document.
3.6.4

Production Changes
The manufacturer shall advise the procuring activity of the time at which any major
change(s) in production or QC methods or documentation become effective during the
period of device production for delivery against any given purchase order referencing this
specification.

3.7

Workmanship
Integrated circuits shall be manufactured and processed in a careful and workmanlike
manner, in accordance with the production processes, workmanship instructions, inspection
and test procedures, and training aids prepared by the manufacturer in fulfillment of the
reliability assurance program established by paragraph 3.6.

3.7.1

Personnel Certification
The manufacturer shall be responsible for training, testing and certification of personnel
involved in producing integrated circuits. Training shall be commensurate and consistent
with the requirements of this specification and in conformance to the basic intent of
MI L-STD-790. Training aids in the form of satisfactory criteria shall be available for
operator and inspector review at any time.

II
I

3.7.2

Personnel Evaluation
The supplier shall maintain a continuous evaluation of the proficiency of personnel
concerned with production and inspection. Retraining of an operator or inspector shall be
required when this evaluation establishes that a degree of proficiency necessary to meet the
requirements of th is specification is not being exercised.

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3.7.3

Rework provisions

3.7.3.1

Rework
All rework on micorcircuits manufactured under this specification shall be accomplished in
accordance with paragraph 3.7.1 of MIL-M-38510 as defined herein.

3.7.3.2

Rebonding
Rebonding shall be in accordance with M I L-M-3851 0, as defined herein (see Note 6.5)

3.8

Performance Capabilities
The integrated circuits delivered to this specification shall be designed to be capable
of meeting the environmental requirements specified in Table II. The manufacturer
need not perform these tests specifically for the contract or specification, but shall
provide data which demonstrates the ability of the integrated circuits to pass the
environmental tests. The data shall have been generated on devices from the same
generic family as the circuits being supplied to this specification, and the package
configuration shall be the same as for the delivered parts (i.e., Flat Pack, TO-1 00, etc.).

3.9

Quality and Reliability Assurance Program Plan
The manufacturer shall establish and implement a Quality and Reliability Assurance
Program Plan that meets the intent of MI L-M-38510, Appendix A. Submission of the
program plan to the procuring activity shall not be a requirement of this specification;
however, the program plan shall be maintained by the manufacturer and shall be available for review by the procuring activity.

II

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4.0

QUALITY ASSURANCE PROVISIONS

4.1

Responsibility for Inspection
Unless otherwise specified in the contract or purchase order, the manufacturer is responsible
for the performance of all inspection requ irements specified herein. Except as otherwise
specified, the manufacturer may utilize his own facilities or any commercial laboratory
acceptable to the procuring activity. The procuring activity may, at its discretion, perform
any of the inspections set forth in the specification where such inspections are deemed
necessary to assure supplies and services conform to prescribed requirements.

4.1.1

Inspection and Testing Procedures Coverage
Inspection and testing processes and procedures prepared in fulfillment of the reliability
assurance program established per paragraph 3.6 sllall be prescribed by clear, complete and
current instructions. These instructions shall assure inspection and test of materials, work in
process and completed integrated circuits as required by this specification. In addition,
criteria for approval and rejection of materials and integrated circuits shall be included.

4.1.2

Inspection at Point of Delivery
The procuring activity may, at its discretion, reinspect any or all of the delivered parts
excluding Group Band C destructive samples as defined by MI L-STD-883. All parts
found to be defective, excluding devices exhibiting damage from use, may be returned
to the manufacturer at the manufacturer's expense.

4.1.3

II

Inspection Records
The manufacturer shall maintain a reliability data and records library. This library shall have
on file, for review by the procuring activity, records of examination, qualification test
results, variables data (when required) and all other pertinent data generated on devices
manufactured to this specification.

4.1.4

Control of Procurement Sources
The manufacturer shall be responsible for assuring that all supplies and services conform to
this specification, the detail specification and the manufacturer's procurement requirements.

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4.1.4.1

Manufacturer's Receiving Inspection
Purchased supplies shall be subjected to inspection after receipt as necessary to ensure
conformance to contract requirements. In selecting sampling plans, consideration shall be
given to the controls exercised by the procurement source and evidence of sustained quality
conformance.

4.1.4.2

The manufacturer shall provide procedures for withholding from use all incoming supplies
pending completion of required tests or receipt of necessary certification or test records and
their evaluation.

4.1.4.3

The manufacturer shall initiate corrective action with the procurement source depending
upon the nature and frequency of receipt of nonconforming supplies.

4.1.5

Procuring Activity Quality Assurance Representative
The procuring activity, may, at its discretion, place quality assurance representatives in
the manufacturer's plant as deemed necessary to assure conformance to contract
requirements in any non-proprietary phase of design, fabrication, processing, inspection, and testing of the integrated circuits being produced. The manufacturer shall
provide reasonable facilities and assistance for the safety and convenience of such
personnel in the performance of their duties. Inspection and test procedures shall be
made available for review by the quality assurance representative.

4.2

Qualification and Quality Conformance Inspection

4.2.1

Qualification

II

Manufacturer's specific device qualification shall be based on compliance with the
quality conformance test per Table III for MOS LSI devices. Qualification for other
technologies shall be per Table 1 except that the testing will be to one LTPD level
tighter than as defined in Table 8-1 of MI L-M-3851 o.
4.2.1.2

Procedures and Definitions

4.2.1.2.1 Sampling Procedure
Device selection for the qualification procedure of 4.2.1 shall be based on a random
sampling technique and will be selected from a generic family.

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4.2.1.2.2 Generic Family
Electrically and structurally similar devices shall be said to comprise a generic family
(e.g., TTL) if they meet the following criteria:

4.2.2

a)

Are designed with the same basic circuit-element configuration
such as TTL, TTL Schottky, DTL, CMOS, MaS metal-gate, or MaS
silicon-gate, and differ only in the number or complexity of
specified circuits which they contain. Generic family for linear
circuits is defined by circuit function (e.g. op amp, comparator,
etc.).

b)

Are designed for the same supply, bias and signal voltage, and for
input/output capability with each other under an established set of
loading rules.

c)

Are enclosed in housings (packages) of the same basic construction
(e.g., hermetically sealed flat packages, dual-in-line ceramic, dual-inline plastic) and outline, differing only in the number of active
housing terminals included and/or utilized.

Quality Conformance Inspection
Quality conformance inspection group 8 and C requirements are per Tables I and II,
Table II shall apply to MaS LSI and Table I to other technologies.
a)

When specifically called out and funded on the purchase order or contract,
the manufacturer shall perform the quality conformance inspections (Group 8
and/or Group C) on a lot-by-Iot basis.

b)

The manufacturer shall, upon request, make available for review generic
quality conformance inspection and data. Data on Group 8 shall be by
package type, number of pins, and assembly location for all subgroups.
Data on Group C, subgroups 1, 2, and 3, shall be by package type, number of
pins, and assembly location. Subgroups 4 and 5 by chip generic family in
hermetic packages.

4.2.2.1

11

Lot Acceptance Sampling
Statistical sampling for quality conformance inspections shall be in accordance with
MIL-M-38510Table 8-1.

I

Group 8 samples, except bond strength samples, shall be selected from sublots that
have successfully completed all of the 100% processing steps specified on the
applicable process flow chart.
4.2.2.2

Resubmission of Failed Lots
When any lot submitted for quality conformance inspection fails any subgroup
requirement, it may be resubmitted a maximum of one time for that particular
subgroup. One additional submission is permitted, provided an analysis is performed
to determine the failure mechanism for each reject device in the subgroup, and that it
is determined that the failures are due to one of the following:
a)

Testing error resulting in electrical damage to devices

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4.2.2.3

b)

A defect that can effectively be removed by rescreening the lot

c)

Random defects which do not reflect poor basic device designs or
poor workmanship.

Early Shipments
When quality conformance inspection is being performed for a specific contract or
purchase order, the accepted Group A devices that are awaiting shipment pending
successful completion of Group B and/or Group C, shall be stored in the Quality
Assurance test area. Under no circumstances shall such parts be shipped prior to the
successful completion of the Group B tests.

4.2.2.4

Groups Band C Test Data
All lot-by-Iot data generated by Group B and/or Group C testing when specifically
called out and funded on the purchase order, shall accompany the initial shipment of
devices. This data shall consist, at a minimum, of the following:

4.2.2.5

a)

Attributes data for Group B. Endpoints for the subgroups are visual
per the applicable M I L-STD-883 test method.

b)

Attributes data for Group C subgroups 1,2,4 and 5. Endpoints for
these subgroups shall be per Table I and II.

Precedure in Case of Test Equipment Failure or Operator Error
Where an integrated circuit is believed to have failed as a result of faulty test
equipment or operator error, the failure shall be entered in the test record which shall
be retained for review along with a complete explanation verifying why the failure is
believed to be invalid. If it is determined that the failure is invalid, a replacement
integrated circuit from the same inspection lot may be added to the sample. The
replacement integrated circuit shall be subjected to all those tests to which the
discarded integrated circuit was submitted prior to its failure, and any remaining
specified test to which the discarded integrated circuit was not subjected prior to its
failure.

a
4.3

Quality Assurance Processing, Methods and Procedures
This section establishes the test methods and conditions to be used for the 100%
processing (screening) requirements specified by the applicable process flow chart.

4.3.1

Precap Visual Inspection
Each microcircuit shall be required to pass the appropriate precap visual inspection
defined as follows. Precap Lot Acceptance shall be per paragraph 4.6.

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4.3.1.1

38510 Class C (Level I) and 38510 Class (Level III) devices shall be visually inspected
in accordance with M I L-STD-883, Method 2010, Condition B.

4.3.1.2

38510A (Level IV) devices (designated for NASA type applications) shall be visually
inspected in accordance with MI L-STD-883, Method 2010, Condition A. (See
notes 6.1.1.1 and 6.1.1.2).

4.3.1.3

Complex MSI and LSI circuits as defined in M I L-STD-883, Method 5004,
paragraph 3.3 may be precap inspected per M I L-STD-883, Method 5004,
paragraph 3.3.1 for 38510 Class B (Level III) and paragraph 3.3.2 for 38510 Class C
(Levell).

4.3.2

Stabilization Bake
The purpose of this test is to determine the effect on microelectronic devices of
baking at elevated temperatures without electrical stress applied. Test shall be
performed in accordance with MI L-STD-883, Method 1008, Condition C.

4.3.3

Thermal Shock
The purpose of this test is to determine the resistance of the device to sudden
exposure to extreme changes in temperature. Test shall be performed in accordance
with MI L-STD-883, Method 1011.1, Condition A.

4.3.4

Temperature Cycle
This test is conducted for the purpose of determining the resistance of a part to
exposures to extremes of high and low temperatures, and to the effect of alternate
exposures to these extremes, such as would be experienced when equipment or parts
are transferred to and from heated shelters in arctic areas. Test shall be performed in
accordance with M I L-STD-883, Method 1010, Condition C, minimum of 10 cycles.
For MSI and LSI complex devices as defined in M I L-STD-883, Method 5004,
paragraph 3.3, 50 cycles may be used in lieu of alternate pre-cap visual inspection
criteria.

4.3.5

II

Mechanical Shock
The shock test is intended to determine the suitability of the devices for use in
electronic equipment which may be subjected to moderately severe shocks as a result of
suddenly applied forces or abrupt changes in motion produced by rough handling,
transportation, or field operation. Test shall be performed in accordance with
MI L-STD-883, Method 2002, Condition B, five blows minimum.

4.3.6

Centrifuge (Constant Acceleration)
The centrifuge test is used to determine the effects on microelectronics devices of a
centrifugal force. This test is designed to indicate structural and mechanical
weaknesses not necessarily detected in shock and vibration tests. Test shall be
performed in accordance with MI L-STD-883, Method 2002, Condition E for devices
having less than 20 pins and Condition 0 for those having more than 20 pins.

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4.3.7

Fine Leak Test
Each integrated circuit for 38510 Class C (Level I), 38510 Class B (Level III), and
38510 Class A (Level IV) screens shall be subject to a fine leak test in accordance
with paragraph 4.3.7.1 or 4.3.7.2. The method shall be optional providing it is
consistent with and capable of detecting the specified leak rate of the applicable
process flow chart.

4.3.7.1

Helium Leak Test
Helium leak test shall be
Method 1014, Condition A.

4.3.7.2

performed

in

accordance

with

M I L-STD-883,

Radiflo Leak Test
Radiflo leak test shall be performed in accordance with M IL-STD-883,
Method 1014, Condition B. Krypton 85 bomb pressure and dwell time are a
function of the radioactivity level and shall be selected so as to conform to the
equations given in Condition B.

4.3.8

Gross-Leak Test
Each integrated circuit for 38510 Class C (Levell), 38510 Class B, (Level III) and
38510 Class A (Level IV) screens shall be subjected to the appropriate gross-leak test
of paragraph 4.3.8.1 or 4.3.8.2, or an approved equivalent. The manufacturer may, at
his option, perform gross-leak testing after the Set I Electrical Tests of paragraph
4.3.9.

II

4.3.8.1

When specifically called out and funded on the purchase order or contract, units will
be bombed 2 hours minimum at 30 psig in FC-78, or equivalent. Units will then be
immersed in FC-40 or equivalent at +125°C ±5°C for 30 seconds minimum and
observed for for a definite stream of bubbles, more than two large bubbles, or an
attached bubble that grows in size, per M I L-STD-883, Method 1014, Condition C2.

4.3.8.2

Units will be immersed in FC-40 or equivalent at +25°C ± 5°C for 30 seconds
minimum and observed for a definite stream of bubbles, more than two large bubbles
or an attached bubble that grows in size, per M I L-STD-883, Method 1015,
Condition C1,.

4.3.9

Final Electrical Test (Set I)
Each integrated circuit shall be required to pass the electrical requirements of the data
sheet. The manufacturer shall also perform such additional testing necessary to assure
the parts will meet the temperature extreme limits. MOS LSI memory devices will be
100% dc and ac tested both at 25°C and at high temperature.
When specifically called out and funded on the purchase order or contract, the
manufacturer shall perform subgroups 2, 3, and 4 of paragraph 4.4 in accordance with
Method 5004 of M I L-STD-883.

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4.3.10

Burn-In
The burn-in screen is performed for the purpose of eliminating marginal devices and
early-life failures evidenced as time and stress dependent. Test shall be in accordance
with MIL-STD-883, Method 1015, Condition A, 0, or E at 125 ± 5°C for digital
circuits and Conditions A, B, C, or 0 for linear circuits. 38510 Class B (Level III) MSI
and LSI complex devices, as defined in M I L-STD-883, paragraph 3.3.1, may receive a
240-hour-minimum burn-in in lieu of alternate precap visual inspection criteria per
MI L-STD-883, Method 5004, paragraph 3.3.1.

4.3.11

Final Electrical Test (Set II)
Each 38510 Class A (Level IV) integrated circuit shall be required to pass the
electrical requirements of the detail specifications. The following tests shall be
performed as a minimum: dc parameters at maximum and minimum rated
temperatures, and switching parameters at 25°C. In addition, each bipolar device shall
have critical 25°C dc electrical parameters read and recorded by serial number and
shall pass the following delta requirements:
PARAMETER
VOL
VOH
IlL
IIH

±10%
±10%
± 1 0%
±10%

DELTA LIMIT
of detail specification
of detail specification
of detail specification
of detail specification

limit
limit
limit
limit

CMOS recorded parameters and delta limits will be defined by the manufacturer as
required.
One copy of the pre-burn-in and post-burn-in recorded data with delta calculations
shall be shipped with each lot. Data will not be available for the metal flat pack (T).
See MIL-M-38510, Class S. The manufacturer may, when deemed necessary, elect to
perform additional electrical testing over and above the requirements stated herein.
4.3.12

..

Radiographic Inspection (X-ray)

I

Test shall be performed in accordance with M I L-STD-883, Method 2012. X-ray may
be performed at any point after serialization at the manufacturer's option. (see
note 6.3).
4.3.13

External Visual Inspection

I

The purpose of this examination is to verify that materials, construction, marking,
and general workmanship are as specified. Examination shall be in accordance with
M I L-STD-883, Method 2009.
4.3.14

Voltage Stress
Selected n-channel MOS LSI devices will be voltage stressed for 40 hours minimum at
25°C min per MIL-STD-883 Method 10155, Condition D.

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4.4

Group A Conformance
Group A conformance shall consist of the electrical parameters in the manufacturer's data
sheet. If an inspection lot is made up of a collection of sublots, each sublot shall conform to
Group A, as specified.

SUBGROUP
LEVEL I
38510C
Subgroup 1

LTPD
LEVEL II

5

(%)

LEVEL III
38510B

LEVEL IV
38510A

5

5

25°C, dc
Subgroup 2

10

10

7

5

10

10

7

5

10

10

High Temperature, dc
Subgroup 3
Low Temperature, dc
Subgroup 4

5

Dynamic and Switching Tests @ 25°C
NOTE: Functional tests included in dc tests.

4.5

Certification
The manufacturer shall include a certificate of compliance with each shipment of parts if
requested on the purchase order. This certificate shall indicate that all specified tests and
requirements of this specification have been made or met, and that the lot of devices
(identified by lot and/or batch number) is acceptable. The certificate shall bear the name
and signature of the manufacturer's Quality Control representative, the date of acceptance
or signing, and any pertinent notes as applicable.

•

4.6

Precap Lot Acceptance
After each precap inspection the lot of devices shall be sampled by quality control and
inspected for the specified visual criteria.

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TABLE I
QUALITY CONFORMANCE TEST (GROUP B/GROUP C)

TEST

LTPD

MIL-STD-883

CONDITIONS

METHOD

LEVEL IV

LEVEL III

LEVEL I

38510A

38510B

38510C

19

15

20

10

15

20

10

15

15

10

15

15

10

15

15

Subgroup 12
Physical Dimensions

2016

Subgroup 22
Marking Permanency

2015

Visual and Mechanical

2014

Bond Strength 1

2011

Condition CorD
2 grams for Au bonds
1.5 grams for AI bonds

Subgroup 32
Solderabi lity

2003

Omit Aging

Lead Fatigue

2004

Conditions B2

Fine Leak

1014

Conditions A or B, per

Gross Leak

1014

Condition C, per para. 4.3.8

Subgroup 4 2

para. 4.3.7 of this spec.
of this spec.
GROUPC
Subgroup 1
Thermal Shock

1011

Temp. Cycle

1010

Condition B
Condition C

Moisture Resistance

1004

Omit Initial Condo

Fine Leak

1014

Conditions A or B, per

Gross Leak

1014

Condition C, per para. 4.3.8

Electrical End Points

5005

Subgroups 1, 2, 3, and 7

Mechanical Shock

2002

Condition B

Vibration Variable Freq.

2007

Condition A

Constant Acceleration

2001

Condition E3

Fine Leak

1014

Conditions A or B, per

Gr,oss Leak

1014

Condition C, per para. 4.3.8

Electrical End Points

5005

Subgroups 1,2,3, and 7

1009

Condition A Omit Initial

para 4.3.7 herein
herein

..

Subgroup 2

para. 4.3.7 herein
herein

I

10

15

15

10

15

15

7

7

7

5

5

5

Subgroup 3
Salt Atmosphere

Conditioning
Subgroup 4
High Temp Storage

1008

150°C, 1000 Hrs.

Electrical End Points

5005

Subgroups 1, 2, 3, and 7

Subgroup 6
Operating Life Test

1005

125°C, 1000 Hrs. Minimum

Electrical End Points

5005

Subgroups 1, 2, 3, and 7

1. Bond strength test may be performed on samples randomly selected immediately following internal visual prior to sealing.
2. Visual and/or hermetic end points; hence, electrical or visual rejects may be used. Reference MIL-STD-883, Method 5005.2, para. 3.4.
3. Condition 0 for packages with 20 pins or more. Condition E for packages with less than 20 pins.

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TABLE II
QUALITY CONFORMANCE TEST
MOS LSI CIRCUIT
TEST

MI L-STD-883

CONDITIONS

METHOD

LTPD

Subgroup 1
Temperature Cycle

1001

Condition C

Constant Acceleration

2001
5005

Condition 0 1 , Y 1 Plane

Electrical End Points

Subgroup 1

15

Subgroup 2
Operating Life

1005

Condition 0,500 Hrs. Minimum

Electrical End Points

5005

Subgroup 1

1. Condition 0 for packages with 20 pins or more. Condition E for packages with less than 20 pins.

II

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TABLE III
MANUFACTURERS QUALIFICATION PROCEDURE
MOS LSI CIRCUITS

TEST

MIL·STD·883

CONDITIONS

METHOD

LTPD

Subgroup 11
Physical Dimensions

2016

Visual and Mechanical

2014

15

Subgroup 21
2003

Omit Aging

Thermal Shock

1011

Condition B

Temperature Cycling

1010

Condition C

Moisture Resistance

1004

Omit Initial Conditioning

Electrical End Points

5005

Subgroup 1

Mechanical Shock

2002

Condition B

Vibration Variable Freq.

2007

Condition A

Constant Acceleration

2001

Condition E3

Electrical End Points

5005

Subgroup 1

Lead Fatigue

2004

Condition B2

Fine Leak

1014

Condition A or B Per Para.

Gross Leak

1014

Condition C2 Per Para.

Solderability

15

Subgroup 32

15

Subgroup 4 2

15

Subgroup 51

4.3.7 Herein
15

4.3.7 Herein
Subgroup 6 1
Salt Atmosphere

1009

Condition A, Omit

15

Initial Conditioning
Subgroup 72
Storage Life

1008

150°C, 1000 Hrs. Minimum

Electrical End Points

5005

Subgroup 1

1005

85°C, 1000 Hrs. Minimum

5005

Subgroup 1

7

Subgroup 8 2
Operating LIfe
Electrical End Points

a

10

Subgroup 9 1
10 devices
Bond Strength

2011

Condition B, D

not greater

I

than 1%
defective

1. Visual and/or hermetic end points; hence, electrical rejects may be used. Reference M I L-STD-883, Method 5005.2, Para. 3.4.
2. Electrical end points only.
3. Condition 0 for packages with 20 pins or more. Condition E for packages with less than 20 pins.

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255

38510/MACH IV PROCUREMENT SPECIFICATION

5.0

PREPARATION FOR DELIVERY

5.1

Final Visual Shipping Inspection
Each lot of microcircuits and its associated documentation shall be sampled by Quality
Control and visually inspected for the following:
a)

5.2

Scratched, nicked or bent leads

b)

Damaged header (packages)

c)

All test data specified in section 4.0

d)

Certificate of Compliance as specified in section 4.0

e)

All other pertinent documentation required and specified by this
specification.

Packing Requirements
Parts shall be packed in containers of the type, size, and kind commonly used which
will ensure acceptance by common carriers and safe delivery at the destination and in
accordance with M I L-M-55565, Level C, bulk pack. The containers shall be clearly
marked with manufacturer's name or symbol.

5.3

Preservation and Package Identification
The package shall be marked with the following:
The country of origin if other than U.S.A.

II

Procuring activity parts number
Purchase order number
Material nomenclature
Quantity
Lot number
Date code
This information shall appear on the label or shall be directly marked on each container.
Method is optional.

256

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38510/MACH IV PROCUREMENT SPECIFICATION

6.0

NOTES

6.1

Precap Visual Method 2010
The following criteria may be in conflict with the circuit design topology and
construction techniques of some microcircuit manufacturers. Where such a conflict
does exist, the inspection criteria listed herein may be waived. (Reference paragraph
3.0 of M I L-STD-883, Method 2010).

6.1.1

Preseat Visual Inspection, Test Condition B [38510 Class B (Level III) and 38510
Class C (Levell)].

6.1.1.1

Paragraph 3.2: a 20-PSI minimum blow-off prior to seal will be performed to meet
the intent of a controlled environment.

6.1.1.2

For titanium-tungsten, gold, titanium-tungsten multilayered systems, the underlying
metal is defined as the bottom titanium tungsten and the top layer is defined as gold.

..
I

I

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257

38510/MACH IV PROCUREMENT SPECIFICATION

6.2

Interconnections
Circuit interconnections (metallization pattern) shall be designed so that no properly
fabricated connection shall experience a current density greater than 5 X 105 amperes/cm 2 ,
including allowances for worst-case conductor composition, normal production tolerances
on design dimensions, and nominal thickness at critical areas such as contact windows.

6.3

X-Ray Method 2012
Paragraph 3.9.2.2a(2) and (3) delete and replace with: "Cause for rejection shall be a
single void in the bar attachment material opening two adjacent sides and exceeding
50% of the length of one side and 100% of the length of the other side."

6.4

Salt Atmosphere Test, Method 1009
Where package design considerations necessitate (such as 0.75-inch tip-to-tip metal
flat packs), there may be a conformal coating applied prior to the salt atmosphere
test.

6.5

Rebonding
Attempts to bond where only impressions have been made in the metal and where the
bond did not make a physical attachment to the pad or post shall not be considered
evidence of rebonding .

..
258

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JAN MIL-M-38S10
Integrated Circuits

I

II
I

259

JAN MIL-M-38510 INTEGRATED CIRCUITS
The M IL-M-3851 0 JAN Program implemented by Texas Instruments provides a standardized qualification and specificatibn
system for high-reliability military applications. The program covers a wide range of monolithic integrated circuits including
digital and linear device types in both dual-in-line and' flat pack configurations. For device types not yet covered by
M I L-M·3851 0 JAN slash sheets or for cost-effectivity and improved availability, the Texas Instruments 38510/MACH IV
Program is recommended. It includes all the significant and practical controls, lot acceptances, and screenings included in the
MI L-M-3851 0 JAN Program and is available at approximately one-third of the cost. The 38510/MACH IV Program includes a
controlled procurement document encompassing general specifications MI L-M-38510A and M IL-STD-883A dated
15 November 1974. Revision D of the TI 38510/MACH IV specification is included in Tab Section 7 of this book.
The TI 38510/MACH IV Program also offers an aid to specification writing by providing a cost-effective 38510 and 883 base
document, whereby special device program specifications may be written invoking any additional testing options unique to a
specific program. The TI 38510/MACH IV specification is organized and written per MIL-STD-100 to allow its use as a
program specification by merely adding the user's company name and drawing number, as well as any required additions or
deletions necessary to meet the specific program goals.
Table I provides a convenient cross-reference from the JAN part numbers to the corresponding standard catalog part numbers.
The cross reference from the catalog numbers to the JAN slash sheet numbers is provided in Table II.
The complete JAN p,art number with the tables of class, case, and lead finish codes is given in Table III, along with a cross
reference to the TI 38510/MACH IV part number. A table of standard TI cases and lead finishes is also provided to assist in
specifying the proper JAN part number. It is imperative that the proper case and lead finish shown in the table be specified
on the parts list and procurement documentation. The specific package for each device is determined by referring to the
proper data sheet.
The following figure defines the reliability classes of MI L-M-3851 0 JAN and TI 38510/MACH IV ICs, and the intended areas
of application. MI L-M-3851 0 recommends that for original equipment complements, the device class appropriate to the need
be used, while Class B is recommended for spare parts for logistic support.

RECOMMENDED USE

II

TYPICAL
SYSTEM APPLICATIONS

Where repair or replacement
is readily accomplished and
"down time" is not critical

Prototype, noncritical support
or ground systems

Where repair or replacement
is difficult or impossible and
reliability is vital

Avionics and tactical
missile systems

Where repair or replacement
is difficult or impossible and
reliability is imperative

Critical avionics, space
and strategic missile
systems

MIL-STD-883
MIL-M-38510
CLASS
Class C

38510/MACH IV
LEVEL
I (SNM)

Class B

III (SNC)

Class A/S

IV (SNH)

Wide acceptance of TI 3851O/MACH IV Class B "SNC" level devices has made possible improved availability thru distributor
and factory stocking programs. The following military documents (see Note 1) establish the processing, quality, and
reliability assurance requirements for JAN integrated circuits. The detail requirements of each individual JAN device are
specified in the slash sheets.
MI L-M-3851 O/XXX, Microcircuits, Digital, TTL" , " , , "
Monolithic Silicon (Slash Sheets)
M I L-M-3851 OA, Microcircuits, General Specification for
M I L-STD-883A, Test Methods and Procedures for Microelectronics
QPL-38510, Qualified Products List for MIL-M-38510
NOTE 1: Copies of these documents may be requested from the Naval Pulbications and Forms Center, 5801 Tabor Avenue, Philadelphia,
Pa.19120.

260

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JAN MIL-M-38510 INTEGRATED CIRCUITS
TABLE I. JAN INTEGRATED CIRCUITS AND CIRCUIT·TYPE CROSS·REFERENCE
JAN

IND.
00101
00102
00103
00104
00105
00106
00107
00108
00109
00201
00202
00203
00204
00205
00206
00207
00301
00302
00303
00401
00402
00403
00404
00501
00502
00503
00504
00601
00602
00603
00701
00801
00802
00803
00804
00805
00901
00902
00903
00904
00905
00906
00907t
00908t
00909t
00910t
01001
01002
01003
01004
01005
01006
01007
01008
01009
01101
01102
01201
01202
01203
01301
01302
01303
01304
01305
01306
01307
01308
01309
01310t
01311t
01312t

CKT
TYPE
5430
5420
5410
5400
5404
5412
5401
5405
5403
5472
5473
54107
5476
5474
5470
5479t
5440
5437
5438
5402
5423
5425
5427
5450
5451
5453
5454
5482
5483
9304t
5486
5406
5416
5407
5417
5426
5495
5496
54164
54165
54194
54195
9300t
9328
54198
54166
5442
5443
5444
5445
54145
5446
5447
5448
5449
54181
54182
54121
54122
54123
5492
5493
54160
54163
54162
54161
5490
54192
54193
54196
54197
54177

JAN

IND.
01401
01402
01403
01404
01405
01406t
01501
01502
01503
01504
01601
01602
01701
01702
01703t
01801t
01901t
02001
02002
02003
02004
02005
02006
02101
02102
02103
02104
02105
02201
02202
02203
02204
02205
02206
02301
02302
02303
02304
02305
02306
02307
02401
02501
02502
02503t
02504t
02505t
02601
02701
02801
02802
02803
02804
02805
02806+
02901
02902
02903
02904
02905
02906
03001
03002
03003
03004
03005
03101
03102
03103
03104
03105
03501

JAN

CKT
TYPE
54150
9312t
54153
9309
54157
54151
5475
5477
54116
9314t
5408
5409
54174
54175
54173
54170
54180
54L30
54L20
54L10
54LOO
54L04
54LOl/54L03
54L71
54L72
54L73
54L78
54L74
54H72
54H73
54H74
54H76
54Hl0l
54Hl03
54H30
54H20
54Hl0
54HOO
54H04
54HOl
54H22
54H40
54L90
54L93
54L193
93Ll0
93L16
54L86
54L02
54L95
54L164
93L28:j:
93LOO
76L70
54L91
54L42
54L43
54L44
54L46
54L47
76L42A
15930
15935
15936
15946
15962
15932
15944
15957
15958
15933
MH0026

IND.
04001
04002
04003
04004
04005
04101
04102
04103
04104+
04201
04202
05001
05002
05003
05101
05102
05201
05202
05203
05204
05301
0:3302
05303
05401
05501
05502
05503
05504
05601
05602
05603
05604
05605
05701
05702
05703
05704
05705
05706t
05707t
05801 t
06001
06002
06003
06004
06005
06006
06101t
06102t
06103t
06104t
07001
07002
07003
07004
07005
07006
07007
07008
07009
07010
07101
07102
07103
07104
07105
07106
07201
07301
07401
07402
07403

CKT
TYPE
54H50
54H51
54H53
54H54
54H55
54L51
54L54
54L55
54L54
54L121
54L 122
4011A
4012A
4023A
4013A
4027A
4000A
4001A
4002A
4025A
4007A
4019A
4030A
4008A
4009A
4010A
4049A
4050A
4017A
4018A
4020A
4022A
4024A
4006A
4014A
4015A
4021A
4031A
4035A
4034A
4016A
10501t
10502t
10505t
10506t
10507t
10509t
1053q
10631:j:
10576t
10535t
54S00
54S03
54S04
54505
54510
54520
54S22
54530
545133
54S134
54S74
54S112
545113
545114
545174
545175
54540
54502
54S51
54564
54565

NOTE: Only the basic JAN and SN numbers are shown. Complete the numbers as shown in Table
tSlash sheets not released as of date of this publication.
:j:Not recommended for new designs.
+Class S only.

TEXAS INSTRUMENTS
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JAN

IND.
07501t
07502t
07601t
07602t
07701t
07702t
07703t
07801t
07802t
07901t
07902t
07903t
07904t
07905t
07906t
07907t
08001t
08002t
08101t
08201t
10101
10102
10103
10104
10105t
10106t
10201
10202t
10203t
10301
10302
10303
10304
10401
10402
10403
10404
10405
10406t
10501t
10601
10602
10701
1080lt
10802t
15001
15101
15102
15103
15201t
15202t
15203t
15204t
15205t
15206t
15301t
15302t
1550lt
15502t
15601t
15602t
15801t
15802t
15803t
15804t
20101
20102
20103t
20201 t
20202t
23001t
23002t

CKT
TYPE
54586
54S135
54S194
54S195
54S138
545139
545280
545181
545182
545151
54S153
54S157
545158
545251
545257
545258
54S11
54S15
54S140
54S85
52741
52747
52101A
52108A
LH2101A
LH2108A
52723
52104
52105
52710
52711
52106
52111
55107
55108
55114
55115
55113
7831
52733
LM102t
52110
52109
3018A
3045
5485
5413
5414
54132
54154
54155
54156
8250
8251
8252
54125
54126
54H08
54Hl1
54147
54148
9321
9301
9311
9317
54186 (PROM 512)
MCM5304t
IM5603A
54S387 (PROM 1024)
IM5623
5531 (256 RAM)
93410 (256 RAM)

I

II

I

III.

261

JAN MI L-M-38510 INTEGRATED CIRCUITS
TABLE I. JAN INTEGRATED CIRCUITS AND CIRCUIT-TYPE CROSS-REFERENCE
JAN
INO.
2350H
23502t
30001t
30002t
30003t
30004t
30005t
30006t
30007t
30008t
30009t
30101t
30102t
30103t
30104t
30105t
30106t
30107t
30108t

CKT
TYPE
TMS4060 (4K RAM)
TMS4050 (4K RAM)
54 LSOO
54LS03
54LS04
54LS05
54LS10
54LS12
54LS20
54LS22
54LS30
54LS73
54LS74
54LS112
54LS113
54LS114
54LS174
54LS175
54LS107

CKT
TYPE
LH2101A
LH2108A
LM102
MCM5304:1:
MH0026
TMS4050
TMS4060
1M5600
1M5603A
1M5623
10501:1:
10502:1:
10505:1:
10506:1:
10507:1:
10509:1:
10531:1:
10535:1:
10576:1:
10631:1:
15930
15932
15933
15935
15936
15944
15946
15957
15958
15962
3018A
3045
4000A
4001A
4002A
4006A
4007A
4008A
4009A
4010A
4011A
4012A
4013A
4014A
4015A

JAN
INO.
10105t
10106t
10601
20102
03501
23502 (4K RAM)
23501 (4K RAM)
20103
20103t
20202t
06001
06002
06003
06004
06005
06006
06101t
06104t
06103t
06102t
03001
03101
03105
03002
03003
03102
03004
03103
03104
03005
10801t
10802t
05201
05202
05203
05701
05301
05401
05501
05502
05001
05002
05101
05702
05703

CKT
TYPE
54LS109
54LS40
54LS37
54LS38
54LS02
54LS27
54LS266
54LS51
54LS54
54LS32
54LS86
54LS194
54LS195
54LS95
54LS96
54LS164
54LS298
54LS395
54LS670

JAN
INO.
30109t
30201t
30202t
30203t
30301t
30302t
30303t
30401t
30402t
30501t
30502t
30601t
30602t
30603t
30604t
30605t
30606t
30607t
30608t

JAN
INO.
3070H
30702t
30703t
30704t
30801t
30901t
30902t
30903t
30904t
30905t
30906t
30907t
30908t
31001t
31002t
31003t
31004t
31101t
31201t

CKT
TYPE
54LS138
54LS139
54LS42
54LS47
54LS181
54LS151
54LS153
54LS157
54LS158
54LS251
54LS257
54LS258
54LS253
54LS11
54LS15
54LS21
54LS08
54LS85
54LS83A

JAN
INO.
31202t
3130H
31302t
31303t
3140H
31402t
3150H
31502t
31503t
31504t
31505t
31506t
31507t
31508t
3160H
31602t
31701t
31702t
31801t

CKT
TYPE
54LS283
54LS13
54LS14
54LS132
54LS123
54LS221
54LS90
54LS93
54LS160
54LS161
54LS168
54LS169
54LS192
54LS193
54LS75
54LS279
54LS124
54LS324
54LS261

TABLE II. CIRCUIT-TYPE AND JAN INTEGRATED CIRCUITS CROSS-REFERENCE

II

CKT
TYPE
4016A
4017A
4018A
4019A
4020A
4021A
4022A
4023A
4024A
4025A
4027A
4030A
4031A
4034A
4035A
4049A
4050A
52101A
52104
52105
52106
52108A
52109
52110
52111
52710
52711
52723
52733
52741
54HOO
54H01
54H04
54H08
54H10
54H11
54H20
54H22
54H30
54H40
54H50
54H51
54H53
54H54
54H55

JAN
INO.
05801t
05601
05602
05302
05603
05704
05604
05003
05605
05204
05102
05303
05705
05706t
05707t
05503
05504
10103
10202t
10203t
10303
10104
10701
10602
10304
10301
10302
10201
10501t
10101
02304
02306
02305
15501t
02303
15502t
02302
02307
02301
02401
04001
04002
04003
04004
04005

CKT
TYPE
54H72
54H73
54H74
54H76
54H101
54H103
54LSOO
54LS02
54LS03
54LS04
54LS05
54LS08
54LS10
54LS11
54LS12
54LS13
54LS14
54LS15
54LS20
54LS21
54LS22
54LS27
54LS30
54LS32
54LS37
54LS38
54LS40
54LS42
54LS47
54LS51
54LS54
54LS73
54LS74
54LS75
54LS83A
54LS85
54LS86
54LS90
54LS93
54LS95
54LS96
54LS107
54LS109
54LS112
54LS113

JAN
INO.
02201
02202
02203
02204
02205
02206
30001t
30301t
30002t
30003t
30004t
31004t
30005t
31001t
30006t
31301t
31302t
31002t
30007t
31003t
31008t
30302t
30009t
30501t
30202t
30203t
30201t
30703t
30704t
30401t
30402t
30101t
30102t
31601t
31201t
31101t
30502t
31501t
31502t
30603t
30604t
30108t
30109t
30103t
30104t

NOTE: Only the basic JAN and SN numbers are shown. Complete the numbers as shown in Table III.
tSlash sheets not released as of date of this publication.
:I: Not, recommended for new designs.

262

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS, TEXAS 75222

CKT
TYPE
54LS114
54LS123
54LS124
54LS132
54LS138
54LS139
54LS151
54LS153
54LS157
54LS158
54LS160
54LS161
54LS164
54LS168
54LS169
54LS174
54LS175
54LS181
54LS192
54LS193
54LS194
54LS195
54LS221
54LS251
54LS253
54LS257
54LS258
54LS261
54LS266
54LS279
54LS283
54LS298
54LS324
54LS395
54LS670
54LOO
54L01
54L02
54L03
54L04
54L10
54L20
54L30
54L42
54L43

JAN
INO.
30105t
31401t
31701t
31303t
30701t
30702t
30901t
30902t
30903t
30904t
31503t
31504t
30605t
31505t
31506t
30106t
30107t
30801t
31507t
31508t
30601t
30602t
31402t
30905t
30908t
30906t
30907t
3180H
30303t
31602t
31202t
30606t
31702t
30607t
30608t
02004
02006
02701
02006
02005
02003
02002
02001
02901
02902

JAN MIL-M-38510 INTEGRATED CIRCU ITS
TABLE II. CIRCUIT·TYPE AND JAN INTEGRATED CIRCUITS CROSS-REFERENCE
CKT
TYPE
54L44
54L46
54L47
54L51
54L54
54L55
54L71
54L72
54L73
54L74
54L78
54L86
54L90
54L91
54L93
54L95
54L 121
54L122
54L164
54L193
54500
54502
54503
54504
54505
54510
54511
54515
54520
54522
54530
54540
54551
54564
54565
54574
54585
54586
545112
545113
545114
545133
545134
545135
545138
545139

JAN
INO.
02903
02904
02905
04101
04102,04104.
04103
02101
02102
02103
02105
02104
02601
02501
02806.
02502
02801
04201
04202
02802
02503t
07001
07301t
07002
07003
07004
07005
08001t
08002t
07006
07007
07008
07201
07401
07402
07403
07101
08201
07501t
07102
07103
07104
07009
07010
07502t
07701t
07702t

CKT
TYPE
545140
545151
545153
545157
545158
545174
545175
545181
545182
545194
545195
545251
545257
545258
545280
545387
5400
5401
5402
5403
5404
5405
5406
5407
5408
5409
5410
5412
5413
5414
5416
5417
5420
5423
5425
5426
5427
5430
5437
5438
5440
5442
5443
5444
5445
5446

JAN
INO.
08101t
07901t
07902t
07903t
07904t
07105
07106
07801 t
07802t
07601t
07602t
07905t
07906t
07907t
07703t
20201t
00104
00107
00401
00109
00105
00108
00801
00803
01601
01602
00103
00106
15101
15102
00802
00804
00102
00402
00403
00805
00404
00101
00302
00303
00301
01001
01002
01003
01004
01006

CKT
TYPE
5447
5448
5449
5450
5451
5453
5454
5470
5472
5473
5474
5475
5476
5477
5479:j:
5482
5483
5485
5486
5490
5492
5493
5495
5496
54107
54116
54121
54122
54123
54125
54126
54132
54145
54147
54148
54150
54151
54153
54154
54155
54156
54157
54160
54161
54162
54163

JAN
INO.
01007
01008
01009
00501
00502
00503
00504
00206
00201
00202
00205
01501
00204
01502
00207
00601
00602
15001
00701
01307
01301
01302
00901
00902
00203
01503
01201
01202
01203
15301t
15302t
15103
01005
15601t
15602t
01401
01406t
01403
15201t
15202t
15203t
01405
01303
01306
01305
01304

CKT
TYPE
54164
54165
54166
54173
54174
54175
53177
54180
54181
54182
54186
54192
54193
54194
54195
54196
54197
54198
5531
55107
55108
55113
55114
55115
76L42A
76L70
7831
8250
8251
8252
93LOO
93L10
93L16
93L28:j:
9300:j:
9301+
9304+
9308
9309
9311
9312+
9314+
9317
9322
9328
93410

JAN
IND.
00903
00904
00910t
01703t
01701
01702
01312t
01901t
01101
01102
20101
01308
01309
00905
00906
01310
01311t
00909t
23001 t (256 RAM)
10401
10402
10405
10403
10404
02906
02805
10406t
15204t
15205t
15206t
02804
02504t
02505t
02803
00907t
15802t
00603
01503
01404
15803t
01402
01504
15804t
01405
00908
23002 (266 RAM)

NOTE: Only the basic JAN and SN numbers are shown. Complete the numbers as shown in Table III.
tSlash sheets not released as of date of this publication.
+Not recommended for new designs.
+Class S only.
I

I

II

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

DALLAS. TEXAS 75222

263

JAN MIL-M-38510 INTEGRATED CIRCUITS

TABLE III. TI JAN AND 38510/MACH IV INTEGRATED CIRCUITS
JAN PIN

_I

JAN M38510

I /

38510/MACH IV P / N - - - - -••

CLASS

A/S'
B

CASE OUTLINE ISEE BLOCK AI

See Cross
Reference
Tables I & II

H
C
M

C

C

CIRCUIT TYPE

t385101
MACH IV

JAN

~

PACKAGE

JAN
A

38510

1/4" X 1/4" FLAT·14

BIT' 1/4" X 1/8" FLAT·14
C

DIP·14

0

1/4" X 3/8" FLAT·14

F·l

FA

F·3

T

F·2

E DIP·16

0·2

JAN CASE OUTLINE & FINISH FOR TI FAMILIES

F·5

PRODUCT

G TO·gg

A B C D E F G

SERIES 54

I

X X X X

SERIES 54H

J

L

H

X X

X X X X

1/4" X 3/8" FLAT·16

W

114" X 1/4" FLAT·l0

F4
A·2
F·6

W

SERIES 54S

X X X X

X X

L

3/S" X 1/2" FLAT·24

F·7

W

X

X

X
X

DIP·22

X X

X X

Y

LEAD FINISH B

X X X X
X X

F·S

X X X X
X X

II

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 5012

•

suffixes for
to the basic

Complete the JAN number by adding a three
suffix

for

class,

case

Example:

TO·3

tPrefix designation for Class B 38510/MACH-IV for CMOS is "TFC" and for MOS LSI is "SMC".
:j: Unassigned.
·Per MIL-M-0038510B.

264

and

lead finish

lead finish as shown above.

Z 114" X 3/S" FLAT ·24

LEAD FINISH A

for class,

SNC5430J·OO

2.

letter

X TO·5

tMOS LSI

LEAD FINISH C

J

DIP·1S

X X
X X X

prefix

Example:

0·3

X

1. Complete the 38510/MACH IV number by

L

DIP·24
3/S" X 5/S" FLAT·24

SERIES 55

10
00
00

adding

K

SERIES 52

SOLDER DIP
TIN·PLATE
GOLD·PLATE

circuit type number as shown above.

X X

tSERI ES 4000 (CMOS)

A

case outline and

X X X X

X

3S5101
MACH IV

U

SERIES 54LS

SERIES 54L

TYPE

NOTES:

w/ss

A·l

TO·l00

JAN

B
C

0·1

F

BLOCK A

LEAD FINISH (SEE BLOCK AI

385101

IAPP.CI MACH IV

DALLAS. TEXAS 75222

JAN M3B510/00101BCB

outline,

and

Ie Sockets
and
Interconnection Panels

II

265

IC SOCKETS AND INTERCONNECTION PANELS

Texas Instruments lines of off-the-shelf interconnection products are designed specifically to meet the performance needs of
volume commercial applications. They provide both the economy of a standard product line and performance features
developed after many year's experience with custom designs. Foremost among these is our ability to selectively bond a
wrought gold stripe at the contact point. No waste. Reduced cost. Reliable contacts.
Wrought Gold Contact
Plate a contact with gold and you get a better contact. More reliable, longer lasting. Increase the gold, you improve the
contact. But gold is precious, so improved performance has to be costly - right? Wrong_ Because now you can get the gold
only where it is needed - at the point of contact.
How? With selective metallurgical bonding; a gold stripe inlay. Not porous plating, but durable wrought gold bonded to the
contact by the same technology used to produce clad coins and thermostat metals.
Texas Instruments, Attleboro. Massachusetts, is the world's largest producer of these multimetal systems. We also know our
way around electronics. The result? A full line of reliable, low cost, interconnection systems featuring an extra measure of
gold where it's needed. Premium performance at no premium in price.
IC Sockets
Texas Instruments family of IC sockets includes every type and size in common use today, and as wide a choice of contact
materials as you'll find anywhere. Choose from open or closed entry w;re-wrapped t sockets, standard or low profile solder
tail sockets, cable plugs, and component platforms. Sizes from 8 to 40 pins.
IC Panels
To match the industry's broadest line of IC sockets TI offers one of the industry's widest selections of off-the-shelf socket
panel products. Logic panels. Logic cards. Accessories. Add TI's custom design capability and wire wrapping for full service.

Additional information including pricing and delivery quotations may be obtained from your nearest TI Distributor, TI
Representative, or:
Texas Instruments Incorporated
Connector Systems Department
MS 2-16
Attleboro, Massachusetts 02703
Telephone: (617) 222-2800
TELEX: ABORA927708

II

t Registered trademark of Gardner-Denver

266

LOW PROFILE SOCKETS
SOLDER TAIL
C-93 SERIES GOLD-CLAD CONTACTS
C-83 SERIES TIN-PLATED CONTACTS
•
•
•
•
•

Universal mounting and packaging
Anti-wicking wafer
Stand-off tabs on base for solder flush
Redundant contact points for low contact resistance, high reliability and repetitive insertion
Closed entry construction

MATERIAL:
A. Body-glass filled nylon (GFN)
B. Contact-copper nickel alloy
C. Finish-see part number schedule

PART NO. SCHEDULE

NOTES:

IDENTIFICATION NOTCH

~r~'~Nl1
~~
-

~

TOLERANCE
NON-CUMULATIVE

1--.

100

TYP.

A. Sockets meet requirements of Texas Instruments
test specification TS-0005 and test report
TR-0003
B. Operating temperature _65°C to ±150°C
C. Contacts have redundant spring elements
D. Accommodates standard·IC leads up to .024"
square, rectangular, or .024" diameter
E. Contact is designed and oriented in the plastic
body to generate maximum possible contact
pressure
F. Socket is designed to achieve maximum density
on boards
G. Sockets may be mounted end to end on .100"
centers continuous line or on .400" centers
row to row
H. Socket is designed to prevent IC leads from
contacting P.C. board
I. Closed entry feature provided to facilitate
automatic IC insertion and protects the IC
leads against damage

~W=;J

~~

I

007

f--

I

-.L. 145

X~

Pins C-93 SERIES C-83 SERIES
8

C930810

14

C931410

C831410

16

C931610

C831610

C830810

18

C931810

C831810

20

C932010

C832010

22

C932210

C832210

24

C932410

C832410

28

C932810

C832810

40

C934010

C934010
I

minimum

gold

stripe inlay

l·125

.

NOMEX ANTI-WICKING WAFER

CONTACT FINISH
C-93 SERIES:
100 micro inch

.350 MAX

.15~ MAX

BLACK BODY

C-83 SERIES:

II

200 microinch minimum bright
tin plate

IC LEAD GUARD

8 Pin

14 Pin

16 Pin

18 Pin

20 Pin

22 Pin

24 Pin

28 Pin

Dimension X ±.005

.300

.300

.300

.300

.300

.400

.600

.600

.600

Dimension V ±.01O

.400

.700

.800

.900

1.000

1.100

1.200

1.400

2.000

Dimension W (max)

.400

.400

.400

.400

.400

.500

.700

.700

.700

I

40 Pin

267

STANDARD PROFILE SOCKET
SOLDER TAIL
C-S2 SERIES PLATED CONTACTS •

C-92 SERIES GOLD CLAD CONTACTS

WIRE WRAP
C-S1 SERIES PLATED CONTACTS •

C-91 SERIES GOLD CLAD CONTACTS

• Designed for low cost, reliable, high density production packaging
• Universal mounting and packaging capabilities
• S to 40 pin lead configur~tions
• Contacts accommodate .015" through .024" rectangular or round
dual-in-line leads
• Wire wrap posts held to true position of .015" providing a true
position of .020" on boards for efficient automatic wire wrapping

WIRE WRAP
IDENTIFICATION
FOR PIN NO.1

SOLDER TAIL

-;;;::7

e-~r~~-T
·ota[x
u~.d.

I

. I§-~~ ~1al~U"""1J;!l~·~---'--

..

---11001NON·CUMULA TlVE ITYP I

MATERIAL:
A. Body-glass filled
nylon (GFN)
B. Contact-phosphor
bronze per 00-B-750
(C-81) copper nickel
alloy (C-91)
C. Finish-see part
number schedule

II

268

IIIjlll

111111

Ii

---1100

TOL.

ITYP.

NOTES:
A. Sockets meet requirements of Texas
Instruments test specification TS-0003
and test report TR-0001
B. Contacts are replaceable
C. Contacts have redundant spring elements
D. Cover is removeable
E. Contact is designed and oriented in the
plastic body to generate maximum
possible contact pressure
F. Operating temperature -65°C to +150°C

G. Sockets are designed to achieve maxirrrum
density on boards and may be mounted
0400" row to row centers
H. Closed entry cover is provided to facilitate
automatic insertion and protect IC leads
against damage
I. Accommodates standard IC leads up to
.024" square, rectangular or .024" dia.
J. Contact retention - 7 Ibs. min.
K. Sockets are capable of being automatically or semiautomatically wire wrapped

8 Pin

14 Pin

16 Pin

18 Pin

20Pin

24 Pin

28 Pin

36 P.in

40 Pin

Dimension V ±0.10

0465

.765

.865

.965

1.065

1.280

10480

1.845

2.045

Dimension W (max)

0400

0400

0400

.400

0400

.700

.700

.700

.700

Dimension X ±.005

.300

.300

.300

.300

.300

.600

.600

.600

.600

Dimension Y ±0.1 0

NA

0400

0400

0400

0400

.500

.500

.800

1.000

Dimension Z ±.005

.280

.280

.280

.280

.280

.280

.280

.325

.325

WIRE WRAP

PART
NUMBER
SCHEDULE

Contact
Finish
Series

C-81
200-400
microinch
min tin
per
MIL-T-10727

Pins

C-91
50 microinch
min
gold stripe
inlay

CLOSED ENTRY

••

OPEN ENTRY
PART

Black

Contact

Cover

Finish

8

C810854

C810804

14

C811454

C811404

16

C811654

C811604

18

C811854

C811804

20

C812054

C812004

24

C812454

C812404

28

C812854

C812804

36

Series

C-82
30 microinch
min gold per
MI L-G-45204
over
50 microinch
min nickel per
QQ-N-290

C813604
C814004

8

C910850

C910800

14

C911450

C911400

16

C911650

C911600

18

C911450

C911400

20

C912050

C911800

24

C912450

C912000

28

C912850

C912800

8

C820850

14

C821450

C821400

16

C821650

C821600

18

C821850

C821800

24

C822450

C822400

28

C822850

C822800

SCHEDULE

Body

Series

C-82
50 microinch
min gold per
MI L-G-45204
over
100 microinch
min nickel per
QQ-N-290

Pins

Black
Body

36

C913600

Series

C914000

C-82
200-400
microinch
min tin per
MIL-T-10727

Series

C-92
100-microinch
min
gold stripe
inlay

Black

Cover

C820800

36

C823600

40

C824000

8

C820852

14

C821452

C821402

16

C821652

C821602

C820802

C821802

18

C821852

24

C822452

C822402

28

C822852

C822802
C823602

36
40

40

CLOSED ENTRY

'"

NUMBER

Black

40
Series

,..

SOLDER TAIL
OPEN ENTRY

C824002

8

C820854

C820804

14

C821454

C821404

16

C821654

C821604

18

C821854

C821604

24

C822454

C822404

28

C822854

C822804

36

C823604

40

C824004

8

C920850

14

C921450

C921400

16

C921650

C921600
C921800

C920800

18

C921850

24

C922450

C922400

28

C922850

C922800

36

C923600

40

C924000

II

269

SOCKET PANELS
STANDARD
04 SERIES

• 180 position panel or multiples of
30 position with 14 or 16 position
socket pattern
• I/O - 4 rows with 13 pins per row
or 3 - 14 pin sockets
• Low cost standard hardware
• Available in 98 standard series
• Off-the-shelf availability

1-------------16.175

(180 PATTmr")

PIC BOARD MATERIAL
1/8 thick Glass Epoxy, 2 oz.
Copper Circuitry both sides,
Tin Plated

-----------~

--------------i
t------------13.100 ------------1

t---------------15.800

:~~~~~-_-5-.-0-00--7.-7-00-,~·400-----1----~I
:1T~~~1

125 OIA. THRU HOLE
TYP

I

r.400 TYP.

.290 MAX.

*

1.

.187

125

. I

.187

~

I~
I

SQ.

I

I

6.875
IGRPI.II.IIII

1302p%i~E~

I~

5.375 160 PATTERN)---1

t - - - - - 8.075 (90 PATTERN)

JJ

7.475
IGRPIVI

I
Ie

SEATING
PLANE

~

1-_ _ _ _ _ _ 10.775 (120 PATTERN)

II

1 - - - - - - - - - - 1 3 . 4 7 5 (150 PATTERN)
NOTE: Dimensions shown are nominal. Detail information and
tolerances available on request (indicate series and group number).
STANDARD SOCKETS
C·81 or C-91 series, 14 pin
or 16 pin, closed entry
sockets as designated in
the Part No. Schedule at
right. See pages 7 and 8
for complete socket
information.

270

C-Sl SERIES SOCKETS
Body ••••••.•. Glass filled nylon
Contact •••• Phosphor bronze per 00-8·750
Finish ..••••• 30.microinch min. gold per
M I L-G-45204 over
50 microinch min. nickel per
00-N-290

C-9l SERIES SOCKETS
Body •........ Glass filled nylon
Contact .... Copper nickel alloy
Finish ..•.•.• 50 microinch min.
gold stripe inlay

545 REF.

STANDARD PANEL PART NO. SCHEDULE -04 Series

Group No.

I/O Option

~~
., co

~a..
OJ ..

C-81
Sockets

C-91
Sockets

0"

cna..

Group I

14 Pin

PIN 14 .... vee
PIN 7 ...... GRO

~" '~.
2

•

•
•

13
12

3

•

4

•

•
•

11

,
5

•

1

~

•

8

o 10,

Group II

•

FEED·THRU
PINS

G~
2

•

13

•

12

4

•
•

11
10

5

·
•

,

3

&

1

8

Group III

•
••
••
16 Pin

PIN 16 .... vee
PIN 8 ...... GRO

,,---..,

&

••
••

1

•

1
•

15

•

14

w"·,
•

13

•
•

12
Jl

•

10

2
3
4
5

•

16 Pin

,.

PIN v ...... vee
PIN G .... __ GRO
~

~v
•

1&

G~
2

•

•

15

3

•

•

14

4

•

5

•
•~ , ••
•

13

•

12

&

•

11
10

1

SOCKETS

II

-

SOCKETS

II

FEED-THRU
PINS

•

8~

Group IV

FEED·THRU
PINS

•

PIN V ...... vee
PIN G ...... GRO

~':

II

-

14 Pin

1

-

SOCKETS

.~

-

SOCKETS

II

FEED-THRU
PINS

30 0411211
60 0411212
90 0411213
120 0411214
150 0411215
180 0411216

0411231
0411232
0411233
0411234
0411235
0411236

30
60
90
120
150
180

0411411
0411412
0411413
0411414
0411415
0411416

0411431
0411432
0411433
0411434
0411435
0411436

30
60
90
120
150
180

0434211
0434212
0434213
0434214
0434215
0434216

0434231
0434232
0434233
0434234
0434235
0434236

30
60
90
120
150
180

0434411
0434412
0434413
0434414
0434415
0434416

0434431
0434432
0434433
0434434
0434435
0434436

30
60
90
120
150
180

0423211
0423212
0423213
0423214
0423215
0423216

0423231
0423232
0423233
0423234
0423235
11423236

30
60
90
120
150
180

0423411
0423412
0423413
0423414
0423415
0423416

0423431
0423432
0423433
0423434
0423435
0423436

30
60
90
120
150
180

0444211
0444212
0444213
0444214
0444215
0444216

0444231
0444232
0444233
0444234
0444235
0444236

30
60
90
120
150
180

0444411
0444412
0444413
0444414
0444415
0444416

0444431
0444432
0444433
0444434
0444435
0444436

I

II
I

271

SOCKET CARDS
STANDARD
002 SERIES

• Low Cost
• 14 - 16 pin socket pattern 60 position
• Standard ground and power pin
commitment
• 8 standard designs
• Mates with dual 60 position edge
connector

002 Series
PIC BOARD MATERI.AL
1/16 and 1/8 thick Glass Epoxy. 2 oz. Copper Circuitry both sides. Tin Plated

STANDARD CARD PART NO. SCHEDULE
Group No.
Group I

C-Sl
Sockets

C-9l
Sockets

1/16"

0022110

0022130

1/S"

0021110

0021130

1/16"

0022310

0022330

14 Pin

PIN 14 .... vce
PIN 7 ..... GRO

,.

~.··.. ···,.~...
·..
•

Board
Thk.

"
"
" ,

1l

Group II

.
14 Pin

PIN V ..... vce
PIN G ..... GRD

..
·...

~ ..~
~"
•
•

NOTE: Dimensions shown are nominal. Detail information and tolerances
available on request {indicate series and group number!.

U
12

2
1

•
•

·. '.
•

11

••

•

10

I.

175l

II ~,t6"
lIT

AOAPTE R
Part no. Z501300

~

~

~1.500~

272

EJECTOR KEYS
Material: Nylon
.
Part no. Z501200 (l/S'"
Z501201 (1/16'"

MULTIPURPOSE
CARD PART NO.
SCHEDULE

-I/O

II

Board
Thk.

Part No.

1/16"

Z012510

1/8"

ZOl1510

0021310 0021330

1/16"

0022210 0022230

l/S"

0021210 0021230

1/16"

0022410 0022430

16 Pin

Group III

PIN 16 .... vce
PIN 8 ..... GRO
DO Series

1/8"

~•...,. 4.3.~
.,5 2.
•

n

•
•

12
11

I.
I.

•

10

7

•

•• • i
Group IV

16 Pin

PIN v ..... VCC
PIN G ..... GRO

~. ;~

~:...:1:
•

11

,

i

•

15

2

•

•

11

I.

•

10

7.

~

l/S"

0021410

0021430



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PDF Version                     : 1.3
Linearized                      : No
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Metadata Date                   : 2011:01:09 19:37:16-08:00
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