1976_National_Memory_Databook 1976 National Memory Databook

User Manual: 1976_National_Memory_Databook

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~

Edge Index
by Product Family

NAll0NAL

This is National's first Memory handbook contalnmg information on MOS and Bipolar Memory
Components, Systems, Application Notes lmd Support Circuits. For detailed information on Interface
Circuits and other major product lines, contact a National sales office, representative, or distributor.

MOS RAM,s

0

Bipolar RAMs

g

CMOS RAMs

0

MOS EPROMs
Bipolar PROMs
MOS ROMs

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(/)

DI

Shift Registers

0
D
ml
ID

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Memory Systems

lO:

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Interface

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App Notes/Briefs

a.

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Manufactured under one or more of the following U.S. patents: 3083262, 3189758, 3231197, 3303356, 3317671, 3323071,3381071, 3408542, 3421025, 3426423, 3440498, 3518750, 3519897, 3557431, 3560765,
3S662~, 3571630, 3575609, 3579059, 3593069, 3597640, 3607469,3617859,3631312,3633052.3638131,3648071,3651565,3693248.

National does not aS$ume any responsibility for use of any circuitry described; no circuit patent licenses are implied; and National reserves the right, at any time without noti,:-e. to

© 1976 National Semiconductor Corp.

a

Bipolar ROMs
(/)

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9
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chang~

said circuitry.

~

Future Products

NAll0NAL

I naddition to the products contained in this catalog, the following products are planned for 1976:

DEVICE NUMBER

DESCRIPTION

AVAILABLE

MOS RAMs
MM2101A
MM2102A
MM2111,/\
MM21112A
MM5255
MM5256
MM5257
MM5275

256 x 4 Static RAM-22 Pin
1k xl Static RAM
256 x 4 Static RAM-18 Pin
256 x 4. Static RAM-16 Pin
lk x 4 Static RAM-18 Pin
1k x 4 Static RAM-22 Pin
4k x 1 Static RAM-18 Pin
1kx 4 Dynamic RAM

First Quarter, 1976
First Quarter, 1976
First Quarter, 1976
First Quarter, 1976
Third Quarter, 1976
Third Quarter, 1976
Third Quarter, 1976
Second Quarter, 1976

Bipolar RAMs
DM93415

1k x 1 TTL RAM

Fourth Quarter, 1976

CMOS.RAMs
MM74C921
MM74C929
MM74C930

256 x 4 Silicon Gate-18 Pin
1k x 1 Silicon Gate-16 Pin
1k x 1 Silicon Gate-18 Pin

First Quarter, 1976
Second Quarter, 1976
Second Quarter, 1976

Bipolar PROMs
DM74S472
DM74S473
DM87S295
DM87S296

512 x
512 x
512 x
512 x

Third
Third
Third
Third

Quarter, 1976
Quarter ,1976
Quarter, 1976
Quarter, 1976

MOS ROMs
MM5238
MM5245
MM5247
MM5249

512 x 8 N-Channel ROM
2048 x 4 N-Channel ROM
4096 x 4 N-Channel ROM
1024 x 4 N-Channel ROM

Third
Third
Third
Third

Quarter,
Quarter,
Quarter,
Quarter,

Shift Registers
MM5062
MM5063
MM5064
MM5065

P-Channel Quad 80-Bit Static
N-Channel Quad 2156-Bit Static
N-Channel Dual 512-Bit Static
N-Channel Single 1024-Bit Static

Second Quarter, 1976
Fourth Quarter, 1976
Fourth Quarter, 1976
Fourth Quarter, 1976

8-20
8-20
8,-24
8-24

Pin
Pin
Pin
Pin

ii

1976
1976_
1976
1976

~

Table of Contents

NAnONAL

Edge Index by Product Family ........................... ',' ............... ; ......•..........
Introduction ........... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . '. . . . . . . . . . . . . " ...... '. .
Alpba-Numerical Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . '.' . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . .

ii
viii

MOS RAMS-SECTION 1
MMll0l, MM11011 256-Bit (256 x 1) Static. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . .
1.1
MMll01A,MMll01Al,MMll01A2 256-Bit (256 x 1) Static ............. _._ ... _ . . . . . . . . . . . . . . . . . . .
1-1
MM2101, MM2101-1, MM2101-2 1024-Bit (256 x 4) Static with Separate I/O . . . . . . . . . . . . . . . . . . . . . . . _ . . . . .
1-5
MM2102, MM2102-1, MM2102-2 1024-Bit (1024 xl) Static ..... __ ..............•........ '.' . . . . . . . .
1-8
MM2102MD, MM2102-2MD 1024-Bit (1024 x 1) Static, Military Temperature Range. . . . . . . .. . . . . . . . . . . . . . .. 1-12
MM2111, MM2111-1, MM2111-2 1024-Bit (256 x 4) Static with Common Data I/O ..... _ . . . .. . . . . . . . . . . . . .. 1-16
1-19
MM2112, MM2112-2 1024-Bit (256 x 4) Static with Common Data I/O ... , . , . , ..... , . , , , ..... , , .... , _ "
MM4250 256-Bit (256 x 1) Static, Military Temperature Range .. , .. , , . , .... _ ............ , .... , .. _ . . . .
1-1
MM4261/MM5261 1024-Bit (1024 xl) D.ynamic ......... , . , .... ' ............. , ....... , .. , ... , . ,. 1-22
MM4262/MM5262 2048-Bit (2048 x 1) Dynamic ..............•....... , .. , .. , ............. '.' •.• ; 1-26
MM5269 1024-Bit (256 x 4) Static with On-Chip Registers. , ...... _ . . . . . . . . . . . . . . . . . . _ .. " " . ' ... ; . .. 1-32
MM52704096-Bit (4096 xl) TRI-SHARETM Port, Dynamic ......•..... , .. , . , .. ; ...... _ ..... , . . . . ..1-34
MM5210-5 4096-Bit (4096 xl) TRI.-SHARETM Port, Dynamic .............. , ............. _ . . . . . . . . .1-39
MM5271 4096-Sit (4096 x 1)Fully TTL Compatible, Dynamic ..... , .... , ................. , ... ; . . . .. 1-41
MM5280 4096-Bit (4096 xl) Dynamic . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . , .. , . , ... , . . . . . . . .. 1-46
M1\iI5280-5 4096-Bit (4096 x 1) Dynamic . . . . . . . . . . . . . . . . . , .............. , ....•....... , , , . . • .. 1-50
MM5281 4096-Bit (4096 xl) Fully TTL Compatible, Dynamic ....................•...•...... , .... ,. 1-52

BIPOLAR RAMS-SECTION 2
DI\iI5489/DM74B9 64-Bit (16 x 4) Open-Collector .......• '...........• _ .............. , . ; ... , .. '.' .
DM74L89A !)4-Bit (16 x 4) Low Power. , ........ , . , ... , .......... _ .......... , .... , . , _ ..... , .
DM54S189/DM74S189 64-Bit (16x4) TRI-STATE®Schottky . . . . . . . . . . . . . . . . . . . . . . . . . . , ' , . . . . . . . . .
DM54S200/DM74S200 256-Bit (256 xl) TRI:STATE®Schottky. _ .................. , ...... , ..... _...
DM54S206/DM74S206 256-Bit (256 xl) Open-Collector Schottky ......... _ ..... , ... , , . , , .. , ; , ...... ,
DM54S289/DM74S289 64-Bit (16 x 4) Open-Collector Schottky ....•.. , . . . . . . . . . . . . . . . . . . , .. _ ..... _.
DM75S68/DM85S68 64-Bit (16 x 4) Schottky Edge-Triggered Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... ..
DM7599/DM8599 64-Bit (16 x 4) TRI-STATE® ...... , ..... , . , ... , ..•............. _ ... , , , . , , • , ..
DM86S21 64-Bit (3~ x 2) Schottky .. " ............... , .... , ..... , ..... _ ........ _ ...... , , . ..
DM86L99 64-Bit (16 x 4) Low Power . . . . . . . . . . . . . . . . . . . , . , ... , , ... , . . . . . . . . . . . . . . . . . , ... , ,.

2-1
2-4
2-6
2-10
2-14
2-18
2-21
2-25
2-29
2-32

CMOS RAMS-SECTION 3
MM54C89/MM74C89 64-Bit (16 x 4) TRI-STATE® ......... , ..•. , , ... , . . . . . . . . . . . . . • . . . . . . . . . .
MM54C200/MM74C200 256-Bit (256 x 1) TRI-STATE®....... , .', . . . . . . . . . . . . . . . . . . , . • . . . . . . . . . .
MM54C910/MM74C910 256-Bit (256 x 1) TRI-STATE®. . . . . . . . . . . . . . . . . . . . . . . . . , . , ... , . . • . . . . . .
MM54C920/MM74C920 1024·Bit (256 x 4) Silicon Gate ........................... , . , , .. , , , , •... ,

,.
..
..
..

3-1
3·5
3·8
3·12

MM1702A 204B-Bit (256 x 8) Electrically Programmable and Erasable ROM .. , .... '............ , ......... ,
MM4203/MM5203 204B·Bit (256 x 8 or 512 x 4) Electrically Programmable and Erasable ROM ............... , .
MM4204/MM5204 4096·Bit (512 x 8) Electrically Programmable and Erasable ROM ........ , , ..... , . . • . . . ..

4·1
4-7
4·12

MOS EPROMS-SECTION 4

iii

BIPOLAR PROMS-5ECTION 5
DM54S287/DM74S287 1024-Bit(256x4)TRI-STAT~Schottky __ ......................... _ .. _ .. _..
DM54S387/DM74S387 1024,Bit (256 X 4) Open-Collector Schottky. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54S470/DM74S470 2048-Bit (256 x 8) Open-Collector Schottky •....•.............. _ ... _ . . . . . . . . . .
DM54S471/DM74S4712048-Bit (256 x 8) TRI-STATE® Schottky ..... __ . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54S570/DM74S570 2048-Bit (512x4) TRI-STATE®Schottky_ ....... , .......... _ .......... _.....
DM54S571/DM74S571 2048-Bit (512x4) TRI-STf,TE®Schottky ....... _ ........ _ ....... _...........
DM72S114/DM82S114 2048-Bit (256 x 8) TRI-STATE® Schottky PROM with Latches ................ __ . . . .
DM7573/DM8573 1024-Bit (256 x 4) Open-Collector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . .
DM7574/DM8574 1024-Bit (256 x 4) TRI-STATE® .......... _ .....................•.......... '... ,
DM7577/DM8577 256-Bit (32 x 8) Open·Coliector .....•.....•....... : . . . . . . . . . . • • . . . . . . . . . • . . . ..
DM7578/DM8578 256·Bit (32 x 8) TRI-STATE® . . . . . . . . . • . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . ..
DM75S222/DM85S222 2048·Bit (256 x 8) TRI-STATE® Schottky PROM with Latches ................•... :.

5-1
5-1
5-3
5-3
5-5
5-5
5-7
5-9
5·12'
5·15
5·18
5'21

MOS ROMS-SECTION 6
MM35011024·Bit (128 x8) Mask Programmable ........................... " . .. • . . . . . . . . . . . . . . .
6·1
MM4210/MM5210 1024-Bit (256 x 4) Mask Programmable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . .6·3
MM4211/MM5211 1024-Bit (256 x 4) Mask Programmable .................... , .. . . .. . . •. .. . ...•...
6·6
MM5212 12,288·Bit (lk x 12) Mask Programmable ...........•............. , . • . . . . . . . . . . . . . .. . . . .
6·9
MM4213/MM5213 2048-Bit (256 x 8 or 512 x 4) Mask Programmable ..............•. , .•.......•.••... , 6-11
MM4214/MM5214 4096·Bit (512 x 8) Mask Programmable ........... , . . . . . . . . . . . • . . • . . . . . . . . • . . . .. 6·13
MM5215 12,288-Bit (lk x 12) Mask Programmable ...... , ....•............ ; . . . . . .. . . . . . . . . . . . . . .. 6-15
MM4220/MM5220 1024'Bit (l28 x 8 or 256 x 4) Mask Programmable ............ ~ .. '.. . . . . . • . . . . . . . . . .. 6·17
MM4220AE/MM5220AE ASCII·7 to Hollerith Code Converter. . . . . . . . . . . . . . .. . . . . . . . • . . . . . . .. . • . . . .. 6·21
MM4220AP/MM5220AP BCDIC to ASCII Code Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . ... 6-24
MM4220BL/MM5220BL Baudot to ASCII Code Converter ................... , .•..............•••.... 6·26
MM4220BM/MM5220B.M Sine Look·Up Table ................... , ... '................. '.... : • . . . .. 6·28
MM4220BN/MM5220BNArctangent Look-Up Table . ~ ........................•...•........ '. . . . .. 6-32
MM4220DF/MM5220DF "Quick Brown Fox" Generator......... '. , ................. , . .. . . . . . . . . • . .. 6:34
MM4220EK/MM5220EK BCDIC to EBCDIC/ASCII to EBCDIC Code Converter. . . . . . . . . . . . . . . . .. . . . . . . . .. 6-36
MM4220LR/MM5220LR BCOIC to ASCII-7/ASCII-7 to BCDIC Code Converter. . . . . . . . . . . . • . . . . .. . . • . . . .. 6-39
MM4220NP/MM5220NP 7 x 9 Horizontal Scan Display Character Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 642
MM4221/MM5221 1024·Bit (128 x 8 or 256 x 4) Mask Programmable. . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . .• .6-44
MM4221 ROIMM5221 RQ ASCII-7 to EIA RS244A/EIA RS244A to ASCII-7 . . .. • . . . . . . . . . . . . . . . . . . • . . . .. 648
MM4221 RR/MM5221 RR ASCII-7 to EBCDIC Code Converter ........................... _ . . . . . . . . . .. 6·51
MM4229/MM5229 30n·Bit (256 x 12) Mask Programmable ............ ~ ......................... ,. 6-54
MM4230/MM5230 2048·Bit (256 x 8 or 512 x 4) Mask Programmable, , . '.' , , , . , , . , .•... _ ...... '. . . . . . . .. 6-56
MM4230BO/MM5230BO Hollerith to ASCII Code Converter ....•.... ; ..........• _ ................. "
6·60
MM4230FE/MM5230FE Selectric to EBCDIC/EBCDIC to Selectric Code Converter ..... ; • . • . • . . . . . . . . .. . . .. 6·62
MM4230JT/MM523OJT BCOIC to EBCDIC/EBCDIC to BCDIC Code Converter· .......••...... _ . . . . . . . • . .. 6·67
MM4230KP/MM5230KP ASCII·7 to Selectric Code Converter ...................•.......... _ .. __ .... :6·73
MM4230NN/MM5230NN 7 x 9 Horizontal Scan Displlays and Printers. . . . . . • . . . • • • . . • . . . . . . . . . . . . . . ..
AN-86 A 5imple Power Saving Technique for the MM5262 2k RAM .•...•...•.•.•....... '....... " . _. . ..
AN-89 How to Design with Programmabhi Logie Arrays ... ; •................. : .............•.•.....
AN·100 Custom ROM Programming. . • . . . . . . . . . . . . . . . . . . • . . . . . . . • . . . . . . . . . . . . . ',' . . • . . . . . . . ..
AN·144 Designing Memory Systems Using the MM5262....•......•...............•..... ; •....•....
MB-l0 Trig Function Generators ....•......•............•........... _ ...... _ ......•........
MB-14 Mask Programming 5pecializes M05 5hift Register Designs ....•.•...•..........................
MB-16 Double·Clocking Cuts Standard Registers to Nonstandard Sizes ....•.•........ ; •..•....•.........

11·1
11·13
11-17
11·21
11-27
11-37
11-45
11-49
11-57
11·65
11·78
11·80
11-82

Definition of Terms .......•....................•.....•.............•....•....• .- ........ '
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . : . . . . . . . . . . • . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I
III

vii

~

Alpha-Numerical Index

NAnONAL

BSM1000 Memory System (512k to 1 Mega~ord) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . • . . ..
DM54B8/DM7488 256-Bit (32 x 8) Open-Collector Mask Programmable ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM5489/DM7489 64·Bit (16 x 4) Open-Collector RAM . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . ;. . . . . . . . . .
DM74L89A 64-Bit (16 x 4) LowPower RAM . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '.' . . . . .. . .
DM54187/DM74187 1024-Bit (256 x 4) Open·Coliector Mask Programmable ROM. . . . . . . . . . . . .. . . . . . . . . . . .
DM54L187A/DM74L187A 1024-Bit (256 x 4) Low Power Open-Collector Mask Programmable ROM. . . . . . . . . .. . .
DM54S187/DM74S187 1024-Bit (256 x 4) Open-Collector Schottky Mask Programmable ROM. . . . . . . . . . . . . . ...
DM.54S189/DM74S189 64-Bit (16 x 4) TRI-STATE® Schottky RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . , . • . . • .
DM54S200/DM74S200 256-Bit (256 xl) TR I·STATE® Schottky RAM . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . .
DM54S206/DM74S206 256-Bit (256 xl) Open·Coliector Schottky RAM . . . . . . . . . . . . . . . . . . . . . . . ',' . . . . . ..
DM54S270/DM74S270 2048-Bit (512 x 4) Open-Collector Schottky Mask Programmable ROM. . . . . . . . . . . . . . . .•
DM54S271/DM74S271 2048-Bit (256 x 8) Open-Collector Schottky Mask Programmable ROM. . . . . . . . . . . . . . . ..
DM54S287/DM74S287 1024-Bit (256 x 4) TRI·STATE® Schottky EPROM. . . . . . . . . . . . . . . . . . .. . . . . • . . . . .
DM54S289/DM74S289 64-Bit (16 x 4) Open-Collector Schottky RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .'.
DM54S370/DM74S370 2048-Bit (512 x 4) TRI·STATE® Schottky Mask Programmable ,ROM " . . . . . . .. . . .• . . •.
DM54S371/DM74S371 2048·Bit (256 x 8) TRI·STATE® Schottky Mask Programmable ROM .. ' ............. " ..
DM54S387/DM74S387 1024·Bit (256 x 4) Open-Collector Schottky EPROM. . . . . . . . . . . . .. . . . . . . . . . • . . . . .
DM54S470/DM74S470 2048-Bit (256 x 8) Open·Coliector Schottky EPROM ......... ' .... :. . . . . . . . . . . . . . .
DM54S471/DM74S471 2048-Bit (256 x 8) TRI·STATE® Schottky EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . •
DM54S570/DM74S570 2048-Bit (512 x 4) TRI·STATE® Schottky EPROM. . . . . . . . . . . . . . . . . . . . . . . . .. . . ..
DM54S571/DM74S571 2048-Bit (512 x 4)TRI·STATE® Schottky EPROM. . . . . . . . . . . • . . .. . . . . . . . . . . . . . .
DM72S04/DM82S04 2048-Bit (256 x 8) TR I-STATE® Schottky Mask Programmable ROM with Latches. . .. . .. . . . ..
DM72S114/DM82S114 2048~Bit (256 x 8) TRI·STATE® Schottky EPROM with Latches. . . . . . . . . . . . . . . . . . . . .
DM75S28/DM85S28 8192-Bit (1024 x 8) TR I·STATE® Schottky Mask Programmable ROM. . . . . . . . . . . . . . . . . ..
DM75S29(DM85S29 8192-Bit (1024 x 8) Open-Collector Schottky Mask Programmable ROM. . . . . . . . . . . . . . . . ..
DM8531 16,384-Bit (2048 x 8) Mask Programmable ROM . . . . . • . . . . . . . . . . . . . '. . . . . . . . . . . . . . . . . . . . . ..
DM75S68/DM85S68 64-Bit (16 x 4) Schottky Edge-Triggered Register ...........• : . . . . . . . . . . . . . . . . . . ..
DM7573/DM8573 1024-Bit (256 x 4) Open-Collector EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . .
DM7574/DM8574 1024-Bit (256 x 4) TRI-STATE® EPROM. . . . . . . . . . . . . . .• . . . . . . . . . . . . . . . . . . . . . . ..
DM7575/DM8575 Programmable Logic Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7576/DM8576 Programmable Logic Array .. , .................................. '. . . . . . . . . . . . ..
DM7577/DM8577 256-Bit (32 x 8) Open-Collector EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7578/DM8578 256-Bit (32 x 8) TRI-STATE®EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM8581 16,384-Bit (1024 x 16) Mask Programmable ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . ..
DM7595/DM8595 4096-Bit (512 x 8). Open-Collector Mask Programmable ROM. . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7596/DM8596 4096-Bit (512 x 8) TRI-STATE® Mask Programmable ROM. . . . . . . • . . . . . . . . . . . . . . . . . . ..
DM7597/DM8597 1024-Bit (256 x 4)TRI-STATE® Mask Programmable ROM. . . . . . . . . . . . . . . . . . . . . . . • . . ..
DM75S97/DM85S97 1024-Bit (256 x 4) TRI-STATE® Schottky Mask Programmable ROM .... , . . . . . . . . . . . . . ..
DM7598/DM8598 256,Bit (32 x 8) TRI-STATE® Mask Programmable ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7599/DM8599 64-Bit (16 x 4) TRI-STATE® RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM75S202/DM85S202 2048-Bit (256 x 8) TRI·STATE® Schottky Mask Programmable ROM with Latches. . . . . . . ..
DM75S222/DM85S222 2048-Bit (256 x 8) TRI-STATE® Schottky EPROM with Latches ...... , . . . . . . . . . . . . ..
DM86S21 64-Bit (32 x 2) Schottky RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7678/DM8678 7 x 9 Character Generator. . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7679/DM8679 7 x 9 Character Generator • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "
DM76L97/DM86L97 1024-Bit (256 x 4) TRI-STATE® Low Power Mask Programmable ROM. . . . . . . . . . . . . . . . ..
DM86L99 64'Bit (16 x 4) Low Power RAM ............. , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7795/DM8795 4096-Bit (512 x 8) Open-Collector Mask Programmble ROM. . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM7796/DM8796 4096·Bit (512 x 8) TRI-STATE® Mask Programmable ROM ..... , . . . . . . . . . . . . . . . . . . . . ..
DS0025/DS0025C 2·Phase MOS Clock Driver. : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

viii

9-14
7·1
2·1
2·4
7-5
7·8
7-11
2·6
2·10
2-14
7-13
7-15
5-1
2-18
7-13
7-15
5·1
5·3
5·3
5-5
5-5
7-17
5·7
7-19
7-19
7-21
2-21
5-9
5-12
7-24
7-24
5-15
5-18
7-31
7-34
7-37
7-40
7-11
7-43
2-25
7-49
5-21
2-29
7-51
7-51
7-53
2-32
7-34
7-37
10-1

OS0026 5 MHz 2-Phase MOS Clock Oriver ....... " . . . . . . ... . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . .. 10-2
OS0056 5 MHz 2-Phase MOS Clock Oriver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-2
OS1603/0S3603 Oual MOS Sense Amplifier .. , .... , . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-3
OS3604 Oual MOS Sense Amplifier. . . . . . . . . . ... . . . . . . . . . . . . . . . . .... _ . . . . . . . . . . . .. . . . . . . . . . .. 10-3
OS1605/0S3605 High Speed Hex MOS Sense Amplifier. . . . . . . . . . ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 104
OS1606/053606 High Speed Hex MOS Sense Amplifier . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . . . . . _. 104
OS1607/0S3607 High Speed Hex MOS Sense Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. 104
OS1608/0S3608 High Speed Hex MOS Sense Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-4
OS3625 Oual High Speed MOS Sense Amplifier .. _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . • .. 10-5
053629 Memory Oriver with Oecode Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . _ . . . . . . . .. 10-6
OS1640/0S3640 Quad TRI-SHARETM MOS Oriver . . . . . . . . . . . . . . . . • . . . . . . . _ .... _ . . . . . . . . . . . . . . . . . 10-7
OS1642/0S3642 Oual Bootstrapped MOS Clock Oriver.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . .. . .10-8
OS3643 Oecoded Quad MOS Clock Oriver ... , .... ; . . . . . . . . . . . . . . . . . . . . . . . . . .. , .. . . . . . . . . . . . .. 10-9
OS3644 Quad MOS Clock Oriver . . . • . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
OSl645/053645 Hex TRI-STATE® MOS Latch/Oriver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
OS1646/053646 6-Bit TRI-STATE® MOS Refresh Counter/Oriver . . . . . . . . . . . . . . . . . . . . • . . ... . . . . . . . . . .. 10-12
OS1647/0S3647 Quad TRI-STATE® Memory I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _. 10-13
OS1648/DS3648 TRI-5TATE® MOS Multiplexer/Oriver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ; . :. 10-'14
OSl649/053649 Hex TRI-STATE® MOS Oriver . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
OS3651 Quad High SpeedMOS Sense Amplifier ...................•.....; . . . . . . . . . . . . . . . . . . . . . . . . 10-16
OS3653 Quad High Speed MOS Sense Amplifier . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
OS1670/0S3670 QuadTRI-SHARETM MOS Oriver . . . . . . . . . . . . . . . . . . . . __ . . . . . . . . . . . . . . . . . . . . . . .. 10-7
OS1671/053671 2-Phase Bootstrapped MOS Clock Oriver ........... , . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . 10-17
OS1672/0S3672 Oual Bootstrapped MOS Clock Oriver.·.... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-8
OS3673 Oecoded Quad MOS Clock Oriv.er . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . • . . . . . . . . . . , 10-9
OS3674 Quad MOSClock Oriver ........... _ . . . . . . . . . . . . . . . • . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . 10-10
OS1675/0S3675 Hex TRI-STATE® MOS Latch/Oriver. . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . 10,11
OS1676/0S3676 6·Bit TRI·STATE® MOS Refresh Counter/Oriver. , . . . . . . . . . . . . . . . . • . . . . '. . . . . . . . . . . . . 10·12
OS1677/0S3677 QuadTRI-STATE® MOS Mempry I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
OS1678/0S3678 TRI-STATE® MOS Multiplexer/Oriver . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . , 10-14
OS1679/0S3679 Hex TRI·STATE® MOS Driver . . . . . . . . . . . . . . . . . . . . . . • . • . . . . . . . . . . . . . . . . . . . . . . . 10·15
OS16147/0S36147 Quad TRI-STATE® MOS Memory I/O Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
OS16149/0S36149 Hex MOS Oriver .. ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . 10-18
0516177/0S36177 Quad TRI-STATE® MOS Memory I/O Register. . . . . . . . . . . • . . . . • . . . . . . . . . . . . . . . . . . . 10-13
OS16179/0S36179 Hex MOS Oriver . . . . . . . . . . . . . . . . . . . . . . . . : .... : . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18
OS55107/DS75107 Oual Line Receiver. . . . . . . . . . .. . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . ... . . . . .. 10-3
OS55108/0S75108 Oual Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ; . . . . . . . . . . . . . . , . . . . .. 10-3
OS551 09/0S751 09 Oual Line Oriver . . . . . . . . . . . . . . . . . • . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . ; . . . .. 10-19
OS55110/0S75110 Oual Line Oriver . . . . . . . . . . . . . . . . . . . . . . . . . ~ • . . . . • . . . . . . . . . . . . . . . . . . . . . . . . 10-19
OS55121/0S75121 Oual Line Oriver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • • . . . . . . . _ . . . . . . . . . . . . . . . . 10-20
OS55122/0S75122 Triple Line Receiver........ ~ ...........•.••....•................ ; . . . . . . . . . 10-21
OS75123 Oual Line Oriver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .'. . . . . . . . . • . . . . . . . . . . . . . . . .. 10-22
OS75124 Triple Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . .. 10-23
OS75150 Oual Line Oriver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . _ .... '.' . . . . . . . . . . . . . . . . . . 10-24
OS75154 Quad Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ ..... _ . . . . . . . . . . . . . . . . . . . • . . ... 10-25
OS75207 Oual Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . '.' ......... " . . . . .. . . . . . . . . . . . • . . . .. 10-3
OS75208 Oual Line Receiver . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . . . . . . _ . . . .. 10-3
OS75324 Memory Oriver with Oecode Inputs .............•..... _ ..... _ . . . . . . . . . . . . . . . . . . . . . . . . 10-26
"OS55325/0S75325 Memory Oriver . . . . . . . . . • . . . . . . . . . . . : .... _ ...................... " ....... , 10-27
OS75361 ·Oual TTL to MOS Oriver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . • . . . . . . . . . . . . . . . . . . . . 10-28
OS75362 Oual TTL to MOS Oriver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , 10-29
OS75364 Oual MOS Clock Oriver . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ ................ " . . . . . . . . . . . . .. 10-30
OS75365 Quad TTL to MOS Oriver . . . . . . . . . . . . . . . . . . . . . . . . . . _ .... __ . . . . . . . . . . . . . . . . . . . . . . . . 10-31
OS7803/0S8803 2·Phase Oscillator/Clock Oriver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32
OS7807/0S8807 2~Phase Oscillator/Clock Oriver . • . . . . . . . . . . . . . . . • . . . . . • . . . . . . . . . . . . . . . . . . " . . . .. 10-33
OS8813 2-Phase Oscillator/Clock Oriver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32
OS8817 2·Phase Oscillator/Clock Oriver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . • . . . . . . . . . " 10-33
MM400/MM500 Series Oynamic Shift Register. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . • . .. . . . . . . . . .
8·1
MM404/MM504 Oual 16-8it Static Shift Register . . . . . . . . . . . . . . . . . . . : . . . . . . . . . . • . . .. . . . . . . . . . . . . .
8·5
8·5
MM405/MM505 Oual 32-Bit Static Shift Register. . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . .

ix

MM1101 256-Bit (256 xl) Static RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-1
MM1101A 256-Bit(256 x 1) Static RAM.....................................................
1-1
MMll01Al 256-Bit (256 x 1) Static RAM • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _.... . ... .. .....
1-1
MM1101A2 256-Bit (256 x 1) Static RAM. . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .
H
MM11011 256-Bit (256 x 1) Static RAM .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-1
MM1402A Quad 256·Bit Dynamic Shift Register. . . . . . . . . . . . . . . . .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-8
MM1403A Dual 512-Bit Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . , .. . . .. . . . . . . . . . . . . . . . . . . .
8-8
MM1404A 1024-Bit Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . ... . . .. . . . . . . . . . . . . . . . . . . . . . . . .
8-8
MM1702A 2048-Bit (256 x 8) Electrically Programmable and Erasable ROM.. . . . . .• . . . . . . . . . . . . . . .. . . . . . .
4-1
MM2101 1024-Bit (256 x 4) Static RAM with Separate I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . .
1-5
MM2101-1 1024-Bit (256 x 4) Static RAM with Separate.l/O. . . . . . . .. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .
1-5
MM2101-2 1024-Bit (256 x 4) Static RAM with Separate I/O... . . .. .. .. ...... ..... ..... .. .. ... . .... .
1-5
MM2102 1024-Bit (1024 x 1) Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . ; . . . .. . .
1-8
MM2102-1 1024·Bit (1024 x.l) Static RAM. . . . . . . . . . . . . . . . . . . . . . . . . . .. .. . . . . . . .. .. . . .. . . . .. . .
1-8
MM2102-21024-Bit (1024 x 1) Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . .. . .. .. ......
1-8
MM2102MD 1024-Bit (1024 x 1) Static RAM, Military Temperature Range . . . . . . . . . . . . ;. . .. .. . . .. . . . .. .• 1-12
MM2102-2MD 1024-Bit (1024 x 1) Static RAM, Military Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-12
1-16
MM2111 1024-Bit (256 x 4) Static RAM with Common Data I/O . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . "
MM2111-1 1024-Bit (256 x 4) Static RAM with Common Data I/O. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. 1-16
MM2111-2 1024-Bit (256 x 4) Static HAM With Common Data I/O. . . . . . . . . . .. . . . . . . . . . . . . . . . .. . . . . . .. 1-16
MM2112 1024-Bit (256 x 4) Static RAM with Common. Data 1/0 . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . . . . . . .. 1-19
MM2112-2 1024-Bit (256 x 4) Static RAM with Common Data I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-19
MM3501 1024.Bit (128 x 8) Mask Programmable ROM . . . . . . . . . . . . . . . . . . . ; ........ , ......•...... , .
6·1
MM4001A/MM5001A Dual 64-Bit Dynamic Shift Register. .. . . . . . . . . . .. . . . . . . . .. . . .. . •. . .. . . . . . . . .. 8-12
MM4006A/MM5006A Dual 1OO-Bit Dynamic Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : 8-15
MM4007/MM5007 Duall00-Bit Dynamic Mask Programmable Shift Register ........ : . . . . . . . . . . . . . . . . .. .. 8-15
MM4010A/MM5010A Dual 64-Bit Accumulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-12
MM4013/MM5013 .1024-Bit Dynamic Register/Accumulator . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . ; .... , .. .. 8-18
MM4015A/MM5015A Triple 6014-Bit Dynamic Register/Accumulator.. . . . . . . . . . • . . .. . . . . . . . . . . . . . . . . .. 8·22
MM4016/MM.5016 512-Bit Dynamic Shift Register. . . . . . . . . . . . _ • . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .. 8·25
MM4017/MM5017 Dual 512-Bit Dynamic Shift Register. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .. . . . . .. 8-28
MM4019/MM5019 Dual 256-Bit Dynamic Mask Programmable Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-15
MM5024A 1024-Bit Dynamic Shift Register .... " . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-8
MM4025/MM5025 Dual 1024-Bit Dynamic Shift Register. . . . . . . . . .. . . . . . . .. . . . . . . . . . .. . . . . . . . . . . .. 8-31
MM4026/MM5026 Dual 1024-Bit DynamicShift Register . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . , .. . . . . .. 8·31
MM4027/MM5027 2048-Bit Dynamic Shift Register. . . . . . . .. . . . . . . ... . .. . . . . . . . . . . . . . . . . . . . . . . . . .. 8-31
MM4040/MM5040 Dual 16-Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . .. . . . . .. 8-36
MM4050A/MM5050A Dual 32-Bit Static Shift Register. . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-39
MM4051A/MM5051A Dual 32~Bit Static Split Clock Shift Register. . . . . . . . . . . . . . . ... . .. . . . . . . . . . . . . . ... 8·39
MM4052/MM5052 Dual 80-Bit Static Shift Register. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-42
MM4053/MM5053 Dual 100.BitStatic Shift Register. . . . .. . . . . . . . . . .. .. . . . . ... . . . . . . . . . . . . . . . . . . .. 8-42
MM5054 Dual 64/72/80-Bit Static Shift Register. . . . . .. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. 8-.45
MM4055/MM5055 Quad 128-Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ .. . . . . . . . ... 8-48
MM4056/Mtvi5056 Dual 256-Bit Static Shift Register. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... 8-48
MM4057/MM5057 512-Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : . . . . . . . . . . . . . . . . . .. 8-48
MM5058 1024-Bit Static Shift Register. . . . . . . . . . . . . . , . . . • .. . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . .. 8-53
MM5060 Dual 144-Bit Mask Programmable Static Shift Register . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . '. . .. 8-56
MM5061 Quad 1OO-Bit Static Shift Register· . . . . . . . .. . . . .. . . . . . . . . • . . . . . . . . • . . . . . .. . . . . . . . . . . .. 8.59
MM4104/MM5104 Multiple Length, Electrically Adjustable Shift Register _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-62
MM4203/MM5203 2048-Bit (256 x 80r 512 x 4) Electrically Programmable and Erasable ROM . . . . . . . . . , . . .. . ..
4-7
MM4204/MM5204 4096-Bit (512 x 8) Electrically Programmable and Erasable ROM. . . . . . . .. . . . . . . . . . . . . . . .4-12
MM4210/MM5210 1024·Bit (256 x 4) Mask Programmable ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . .
6-3
MM42.11/MM5211 1024-Bit (256 x 4) Mask Programmable ROM, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-6
MM521212,288-Bit (lk x 12) Mask Programmable ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . .' . . . . .. . . . . . . . .
6-9
MM4213/MM5213 20413-Bit (256 x 8 or 512 x 4) Mask Programmable ROM. _ . . . . . . . . . . . . . . : . . . . . . . . . . : .. 6·11
Mtvi4214/MM5214 4096-Bit (512 x 8) Mask Programm50
MAX

Power Supply Current, Voo
Power Supply

10

Power Supply Current, Vo

V"

Input .LOW Voltage

Vss -10

Vss -4.2

V'H

Input HIGH Voltage

Vss - 2.0

Vss .... ·0.3

10L

Output Sink Current

12,0

T... =Q C

3.0
2.0

'9.0
25.0

18.0

8.0

UNITS

1.0
13.0

18.0

mA

24.0

mA

Vss -10

Vss -4.2

v

Vss - 2.0

Vss -+ 0.3

12.0

24.0

VOUT",+O.45V, T...·=25°C

MAX

1.0

25.0

IDe

VD

TV'

19.0

10

Curren~,

MIN

3.0

•. 0

V

mA

loc

Output Si~k Current

V OUT = +O.45V, T A = 70°C

'e,

Output Clamp Current

VOUT *-1.0V, TA

10H

Output.Source Currl'llnt

-3.0

-8.0

-3.0

-8.0

mA

10H

Output ~ource Current

-2.0

-7.0

-2.0

-7.0

mA

VOH

Output HIGH Voltage

3.'

4.'

3.'

4.'

'V"]

C,.

Input Capacitance (Note 3)
fAil Input Pins)

COUT

Output Capacitance

VOUT= Vss

Cv

Vo Power Supply
Capacitance

Vo = Vss

100

Power Supply Current, Veo

10

Power Supply Current, Vo

o
T ... =25~C
_
T A =25C

V,.

I

-o"c

2.0
6.0

f= 1 MHz

Continuous
Operation
IOL=O.OmA

mA

13.0

6.0

7.0

13.0

mA

pF

7.0

10.0

7.0

10.0

7.0

10.0

pF

20.0

35.0

20.0

35.0

pF

10.0

14.0

18.0

mA

17.0

20.0

mA

ac characteristics
TA =-O°Cto+70°CforMMll01 Family. TA =-55°Cto+l~5°CforMM4250:
Vss' +5V t5%, Vo' Voo' -9V ±5% for MM4250, MMll01A, MMll01Al, MM1101A2;
Vss == +5V :t5%. Vo ;", -lOV ±5%, Voo "" -7V :t5%, fo~ MMll01, MM11011 (unless otherwise specified).
SYMBOL

TEST

MIN

t",

Read Cycle MM1101, MM1101A·
MM11011, MMll01Al
MM1101A2
MM4250

1.5
1.0
500.0
650.0

1.2 (Note 41
0.7 (Note 41
0.2 (Note 41
0.35 (Note 41

Access Time MM1101, MMll01A
MMll0l', MMll01Al
MMll01A.2
MM4250

t,

p:revious 'Read Data Valid
1:
2:
3:
4:

MAX

0.85
0.65
400.0
400.0
50.0

All voltage measurements are referenc;ed to ground.
Typical values are at TA = +25°C and nominal supply voltages.
Capacitances are measured periodically only.

Maximum value. for tac measured at minimum read cycle,

1-2

UNITS
/1S
/1S
ns
ns

Address to Chip Select Delay
MMll01, MMll01A,
·MM11011,"MMll01Al
·MM1101A
MM4250'

toe

Note
Note
Note
N01:e

TYP
(Note 21

1.5
1.0
500.0
650.0

/1S
/1s
/1S
/1S
/1s
/1s
ns
ns
ns

ac characteristics (con't)
WRITE CYCLE (MM1101. MMll011. MMll01-A. MMnOIAI. MMII01A2)
TEST

SYMBOL

TYP
(Note 21

MIN

MAX

UNITS

twe

Write Cycle

0.8

/.IS

two

Address to Write Pulse Delay

0.3

/.IS

twp

Write Pulse Width

0.4

/.Is

tow

Data Set up Time

0.3

/.Is

tOH

Data Hold Time

0.1

/.Is

WRITE CYCLE (MM4250)

t..c

Write Cycle

1.0

/.IS

t...

Address to Write Pulse Delay

0.35

/.IS

t...

Write Pulse Width

0.50

/.IS

tdw

Data Set-up Time

0.35

/.IS

lo"

Data Hold Time

0.15

/.IS

CHIP SELECT AND DESELECT (MM1101. MM11011. MMI1D1A. MMll01AI. MM1101A2. MM4250)
tew

Chip Select Pulse Width

0.4

tcs

Access Time Through Chip

/.IS
0.2

0.3

/.IS

0.1

0.3

/.IS

Select Input
Chip Deselect Time

te~

Note 1: All voltage measurements are referenced to ground.
Note 2: Typical values, are at T A = +25°C and nominal supply voltages.
Capacitan~es are measured periodically only.

Note 3:

Note 4: Maximum value for tac measured at minimum read cycle.

typical performance characteristics
Typical Access Time vs
Voltage
1000

!

BO~

!

700

e""

600

4DO

v~·-\"r

':UI1A

N~

ID
Q.VI
_11"Ai~

i7~~''-':C
-

VDIII--IV

-.11V

.VDD~-IV~

'1~'I"v

~~ilV

VDD~-IV

ZOO

r-t+VIHI"-IV

-7

-8

...
oS

!iii!

-:::~ >:::t~

-II

,-10

MM1101A. MM1101Al.
MM1101A2. MM4250
Operating Region

Typical Access Time VI
Temperatura

"

14Iio T. - HOC
Vc:c =5.OV
1200 CL=ZOpF
lTULOAO
1000 _1101Ai

j:

..~""

.....

BDD
600

4110

zao e-

-11

-311

MUll0lA ~-:- 1-1-io-i"""

-...

10.0.

.-

-10

10

'"

,

~
l- I-

50

3G

!:;

~

~

...,

"'1101A2.~

.

II
17
1&

TYPICAL OPERATING
15
, REGION.!V'
r:J
14 -f-- liGUARAIlnE
I-- OP1RATINGi::: ::J
13
REGION
12 ~~
II
11

•

7.

TEMPERATURE rCI

VO (VI

ac test circuit
Test Setup for MM11D1A and MMll01A Speed Measurement

...

+3:n

ADD.'SS
.NPUT

Y'D Yv. 1."D. .A
,.1101/
_1101A

..v
1

OUTPUT

,~ ~y

C'.,..
CONDITIONS Of TEST

Input pulse amplitudu: OV to +5.0V.
'nputpulSB riw Ind fall times::; 10 ns.
Speed nt8i1SUrel1lentsare retel1lnced to the 1.5V level (unless otherwise notedl:
at the output of the TTL !IIIte (tpd::; 10 ns) CL ::;'20 pF.

TTL .ATE

OUTPUT

Ii

I.

IZ

14

V.. -VooIVI

16

D

switching time waveforms

Read Cycle

Chip Select and Deselect

ADDRESSES
ADDRESSES

:XI-:(c=x~~-~~~­

_____'_"J=L

READIWRITE
OUTPUTS

'.--_-I,-t--+OUTPUTS

, _ _ _ _ _ _ _ _ _ _ _ _J

"'.

Power Switching For Reduced Power Applications

Write Cycle

ADDRESSES

~

ADDRESSES

---r___________
--J~2:On$

v~------_:_::::"'J

VD AND CS LEAD

90%

READI'WRITE
OUTPUTS

DATA IN
Voo = -IV t 5%

Note 1: All inputs of the MM11 01 A accept standard TTL outputs with Vec
Note 2,: Maximum value for tAC measured at minimum read cycle.

'·4

=

+5.0V ±5%.

'.

~

MOS RAMs

NAnONAL

MM2101, MM2101-1. MM2101-2 1024-bit(256 x 4) static MOS RAM
with separate I/O
general description

features

The National MM2101 is a 256 word by 4 bit static
random access memory element. fabricated using NChannel enhancement mode Silicon Gate technology.
Static storage cells eliminate the need for refresh and
the additional peripheral circuitry associated with refresh.
The data is read out nondestructively and has the same
polarity as the input data.

•

Organization 256 Words by 4 Bits

•

Access Time - 0.5 to 1.0 f.1S Max.

•

Single +5 V Supply Voltage

The 2101 is directly TTL compatible in all respects:
inputs, outputs, and a single +5 V supply. Two chipenables allow easy selection of an individual package
when outputs are OR-tied. An output disable is provided
so that data inputs and outputs can be tied for common
I/O systems. The features of this memory device can be
combined to make a low cost, high performance, and
easy to manufacture memory system.

s:
s:N

.......o,
N

•

Directly TTL Compatible - All Inputs and Outputs·

•

Static MOS - No Clocks or Refreshing Required

•

Simple Memory Expansion - Chip Enable Input

•

Low Cost Packaging - 22 Pin Epoxy B Dual·ln·Line
Configuration

•

Low Power - Typically 150 mW

•

Tri-State ® Output - OR·Tie Capability

•

Output Disable Provided for Ease of Use in Common
Data Bus Systems

National's silicon gate technology also provides protec·
tion against contamination, and permits the use of low
cost Epoxy B packaging.

block and connection diagrams

-Eo
---.!-o

AD

ROW
SELECT

A2

CELL ARRAY
32 ROWS
32 COLUMNS

AJ

RIW

-=----'-, --.",--,

COLUMN 110 ·CIRCUITS

INPUT

DATA
CONTROL

VCC
GNO

VCC

A3
A2

21

A4

Al

20

RIW

AD

19

eEl

AS

18

00

A6

17

CE2

A7

16

004

GNO

15

014

011

14

003

001

10

13

01 3

01 2

11

12

002

PIN NAMES
01, - 014

AO· A7
CEI
CE1

R/W

CEt,

--------1

eE2

00
DO,-004

Vec

OO~-_I~~---~

DATA INPUT
ADDRESS INPUTS
READ/WRITE INPUT
CHIP ENABLE
OUTPUT DISABLE
DATA OUTPUT
POWER (+5 VI

Order Number MM2101D,
MM2101·1D Dr MM2101-2D
See Package 5
Order Number MM2101-N,
MM2101-1N Dr MM2101-2N
See Package 17

1-5

absolute maximum ratings
O°C to +70°C
Ambi'ent Temperature Under Bias
-65°C to +150°C
Storage Temperature
Voltage on Any Pin With Respect to Ground
-0.5 V to +7 V
Power Dissipation
1 Watt

dc electrical characteristics

....
o

Symbol

~
~

III
ILOH
ILOL
ICCl

Input Current
I/O Leakage Current[2]
I/O Leakage Current[21
Power Supply Current

ICC2

Power Supply Current

VIL
VIH
VOL
VOH

Input "Low" Voltage
Input "High" Voltage
Output "Low" Voltage
Output "High" Voltage

....N

TA =

ooc to +70°C,

Parameter

Min.

Max.

Unit

30

10
15
-50
60

pA
pA
pA
mA

70

mA

+0.65
VCC
+0.45

V
V
V
V

2.2

Typical values are for T A = 25°C and nominal supply voltage.

Ndte 2:

Input and Output tied together.

Test Conditions
VIN = 0 to 5.25 V
CEl = 2.2 V, VOUT =4.0 V
CEl = 2.2 V, VOUT = 0.45 V
VIN = 5.25 V, 10 = 0 mA
TA = 25°C
VIN = 5.25 V, 10 = OmA
TA = O°C

10L = 2.0 mA
10H = -150pA

TA=25°C,f=1 MHz

Symbol
CIN
COUT

Typ.!ll

-0.5
2.2

Note 1:

capacitance

VCC" 5 V ± 5% unless otherwise specified.

Limits (pF)

Test

Typ.

Max.

4
8

8
12

Input Capacitance (All Input Pins) VIN = 0 V
Output Capacitance VOUT = 0 V

switching time waveforms

READ CYCLE (R!W= "1")

.

WRITE CYCLE[2]

1...-

---tcoCEl- ~

I

CE2

-

00 (COMMON

--J

~tco

______

, _ t oo _

1/01(3)

-

[lATA OUT

-

.

.

tRey

ADDRESS

--------.I

~tA_

\

I--

CEl-

-

ItoH~
DATA OUT VALID

-.

/
_tcw---

00

~

--

.

DATA IN

t O F I _ t DW _

X.

DATA IN STABLE

1·6

~tOH

,-

~-twP- -tWR_

tOF is with respect to the trailing edge of CE1, CE2, Or 00, whichever occurs first.
During the write cycle, 00 is a logical 1 for common I/O and "don't care" for separate 110 operation.
00 should be tied low ·for separate I/O operation.

I--

\. I--

--J

RIW-

Note 1:
Note 2:
Note 3:

1-

_tCW------.

n

CE2

I--

tOF(1)1_

.

lWCY

AOORESS

ac electrical characteristics

TA = o°c to + 70°C, VCC = 5 V ± 5%, unless otherwise specified.

MM2101

s:
s:N

...

9

Symbol

Parameter

Min.

Typ.

Max.

Unit

Test Conditions

1,000
800
700
200

ns
ns
ns
ns
ns
ns

Input Pulse Levels: +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
CL = 100 pF

ns
ns
ns
ns
ns
ns
ns

Input Pulse Levels:. +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20 ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
CL=lOOpF

READ CYCLE
tRCY
tA
tco
tOD
tDF [1]
tOH

Read Cycle
Access Time
Ch ip Enable to Output
Output Disable to Output
Data Output to High Z State
Previous Data Read Valid after
change of Address

1,000

0
0

WRITE CYCLE
tWCY
tAW
tcw
tow
tDH
twp
tWR

Write Cycle
Write Delay
Chip Enable to Write
Data Setup
Data Hold
Write Pulse
Write Recovery

1,000
150
900
700
100
750
50

MM2101-1 (500 ns Access Time)
Symbol

Parameter

Min.

Typ.

Max.

Unit

500
350
300
150

ns
ns
ns
ns
ns
ns

Input Pulse Levels: +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20 ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
CL = 100 pF

ns
ns
ns
ns
ns
ns
ns

Input Pulse Levels: +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20 ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
CL = 100 pF

Test Conditions

READ CYCLE
tRCY
tA
tco
tOD
tDFI1J
tOH

Read Cycle
Access Time
Chip Enable to Output
Output Disable to Output
Data Output to High Z State
Previous Data Read Valid after
change of Address

500

0
0

WRITE CYCLE
tWCY
tAW
tcw
tow
tDH
twp
tWR

Write Cycle
Write Delay
Chip Enable to Write
Data Setup
Data Hold
Write Pulse
Write Recovery

500
100
400
280
100
300
50

MM2101-2 (650 ns Access Time)
Symbol

Parameter

Min.

Typ,

Max.

Unit

Test Conditions

650
400
350
150

ns
ns
ns
ns
ns
ns

Input Pulse Levels: +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20 ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
CL = 100 pF

ns
nS
ns
ns
ns
ns
ns

Input Pulse Levels: +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20 ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
CL = 100 pF

READ CYCLE
tRCY
tA
tco
too
tDFI1J
tOH

Read Cycle
Access Time
Chip Enable to Output
Output Disable to Output
Data Output to High Z State
Previous Data Read Valid after
change of Address

650

0
0

WRITE CYCLE
tWCY
tAW
tcw
tDW
tDH
twP
tWR
Note 1:

Write Cycle
Write Delay
Chip Enable to Write
Data Setup
Data Hold
Write Pulse
Write Recovery

650
150
550
400
100
400
50

tOF is with respect to the trailing edge of eEl, CE2, or 00, whichever occurs first.
.'

1·7

s:
s:N

......o
,

N

D

N,
N

o
....
N
:IE
:IE

~

MOS RAMs

NAll0NAL

MM2102, MM2102-1, MM2102-2
1024-bit fully decoded static random access memories
N

o....

N

:IE
:IE

general description

features

The MM2102 family of 1024 word by one bit static
random access read write memories are manufactured
using N-channel enhancement mode silicon gate technology. Static storage cells eliminate the need for clocks
and refresh. Data in and data out have the same polarity
and the read operation is nondestructive.

• Single +5V supply
• All inputs and output directly DTL/TTL compatible
• Static operation-no clocks or refreshing required

Low threshold silicon gate. N-channel technology allows
complete DTL/TTL compatibility of all inputs and
outputs as well asuingle +5V supply. The separate
chip enable input (CE) controlling the TRI-STATE®
output allows easy memory expansion by OR-tying
individual devices to a data bus.

•

Low power

•

Fast access
MM2102
MM2102-1
MM2102-2

150 mW typ
l/ls
500 ns
650 ns

• TRI-STATE output for bus interface
• Chip enable allows simple memory expansion
• On chip address decode

The simple interface and high performance make the
MM2102 family ideally suited for those applications,
for large and small storage capacity, where cost is· an
important design consideration.

• All inputs protected against static discharge
•

Low cost 16-pin Epoxy B package

block and connection diagrams

A.
Dual-ln~Line

Package

,.

A,
A,

CELL
ARRAY
32 RDWS

""

,...!.-oGND

llCOlUMNS

A,

A,

15 As

RtW

14 Ag

A,
A.

R/W

COLUMN 110 CIRCUITS

DATA

CE

A,

13

A,

12 DATA OUT
11

A,

DATA IN

OUT
1Q Vee

..
A.

COLUMN SELECTOR

GND

CE

TDP VIEW

Order Number MM21020,
MM21 02-1 D or MM2102-2D
See Package 3

Order Number MM2102N,
MM2102-1N or MM2102-2N
See Package 15

1-8

absolute maximum ratings

s:
s:N

(Note 1)

....
0

--{).5V to + 7.0V
0°Cto+70°C
-65°C to +150°C
lW
300°C

Voltage at Any Pin
Operating Temperature Range
Storage Temperature Range
Power Dissipation
Lead Temperature (Soldering, 10 seconds)

N

s:
s:N

....
0
N
.!..

s:
s:N

dc electrical characteristics
(T A within operating temperature range, Vcc = 5V ±5%, unless otherwise noted.)

....

0

CONDITIONS

PARAMETER

MIN

Logical "1" Input Voltage (V IH )

2.2

Logical "0" Input Voltage (V IL )

-{l_5

TYP

MAX

UNITS

Vcc

V

0.65

V
V

2.2

Logical "'" Output Voltage (VOH )

IOH = -100/lA

Logical "0" Output Voltage (VOL)

IOL = 1.9 mA

0.45

Input Load Current (I LI)

VIN = 0 to 5.25V

10

pA

Output Leakage Current (I LOH )

CE = 2.2V, VOUT = 4.0V

10

pA

Output Leakage Current (I Lod

CE = 2.2V, VOUT = 0.45V

-100

pA

60

mA

70

mA

MAX

UNITS

Power Supply Current (lCC1 )

30

All Inputs = 5.25V, Data Out Open,
= 25°C

V

TA

Power Supply Current (lCC2)

All Inputs = 5.25V, Data Out Open,
TA =O°C

ac electrical characteristics
(T A within operating temperature range, Vcc = 5V ±5%, unless otherwise specifiedJ
See ac test circuit and switching time waveforms.
PARAMETER

CONDITIONS

MIN

TYP

READ CYCLE
Read Cycle (t RC )
MM2102
MM2102-1
MM21 02-2
Access Time (t A
MM2102
MM2102-1
MM2102-2

RJiN=V IH
R/W=V IH
RJiN = V IH

ns
ns
ns

1000
500
650

)

Chip Enable to Output Time (tco)
MM2102
MM2102-1
MM2102-2

1000
500
650

ns
ns
ns

500
350
400

ns
ns
ns

Previous Read Data Valid with
Respect to Address (to H1 )

50

ns

Previous Read Data Valid with·
Respect to Chip, Enable (tOH2)

o

ns

'-9

N
I
N

D

('II

N

o....
('II

~
~

('II

o....
('II

~
~

ac electrical characteristics (con't)
PARAMETER

MIN

CONDITIONS

WRITE CYCLE

TYP

MAX

UNITS

,

Write Cycle (t wc )
MM2102
MM2102-1
MM2102-2

1000
500
650

ns
ns
ns

Address to Write Set-up Time (tAW)
MM2102
MM2102-1
MM2102-2

200
150
200

ns
ns
ns

Write Pulse Width (twp )
MM2102
MM2102-1
MM2102-2

750
300
400

ns
ns
ns

Write Recovery Time (tWR )

50

ns

Data Set-up Time (t DW )
MM2102
MM2102-1
MM2102-2

BOO
330
450

ns
ns
ns

Data Hold Time (tDH )

100

ns

Chip Enable to Write Set-up Time (t cw )
MM2102
MM2102-1
MM2102-2

900
400
550

ns
ns
ns

CAPACITANCE
Input Capacitance (All Inputs) (C IN )
(Note 4)
Output Capacitance (C OUT ) (Note 4)

VIN

=OV. TA =25°C, f = 1.0 MHz

3.0

5.0

pF

7.0

10.0

pF

(Note 2)

VOUT

=OV. T A = 25°C.

f" 1.0 MHz

(Note 2)
Note 1: "Absolu'te Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The.table of "Electrical Characteristics"
provides conditions for actual device operation.

Note 2: Cap8citan'ce is guaranteed by periodic testing.
Note 3: Positive true logic notation j's us'ed: Logical "1" most· positive voltage level, Logical "0"'= 'most negative voltage level.
Note 4: Typical values are for TA = 25°C and nominal supply voltage.
0;::

SWitching time waveforms
Read Cycle

Write Cycle
,~

'00

r'"'----

VIH,
ADDRESS
V'L - - '

CHIP
ENABLE

v"

V"
V~

~~~
'.

DATA

OUT

Yo,

V'H~

ADDRESS
Vll-J

'cw

V-

r~

r--...

V"-i
-.".~~~v"
V-V"
'-

~~,
,r

CHIP

READ!
WRllE

- -

\.... .J "'0.,

V~

DATA

IN

NIltl1: All timn measured witll re$pfltt to 1.5V level
wittlt,andltS20ns.

DATA CAN

CHANGE
Yo,

1-10

,~

,I

DATA STABLE

DATA CAN

CHANGE

ac test circuit

CL

MM2,12

~11DPf

typical performance characteristics
Power Supply Current vs

Output Source Current
V$ Temperature

Temperature

"

40

~

]0

r"- r--.

~

~

~

20

l<

10

~

vs Temperatl:lre

-B

Vee'" 5.5V
ALL INPUTS' 5.5V
DATA OUT OPEN

~

s::
~
N.
.....

Output Sink Current

---

~

......

1- ...

-

Vo~' o.~5V

"I

~::::::::

,.--

VCC'4.~:::::".. ""'=

~

o

o
-75 -50 -25

0

25

50

-75 -50 -25

75 100 125

TA - AMBIENTTEMPERATURE'I'CI

0

25

50

75

-75 -50 -25

,00 125

Access Time vs Temperature

:!

1.75

!!....
~

w

~
....

1.50

~

600

500

vc~ - S!5V

J.....t-

~ 400

300
-75 -50 -25
POWER SUPPLV VOLTAGE (VI

,.,. v V

Vee ::: 4.5V

~A -

.,/

V

!

!!
,..

200

'00

o
0

25

50

75 100 125

AMBIENT TEMPERATURE ( C)

1-11

I

]00

V

I

1.25

75 '00 '25

400

~

"z

50

Temperature

700

~

25

Write Pulse Width and Chip
Enable-To Output Delay vs

I nput Levels YS Power
SupplV Voltage

~

0

TA - AMBIENTTEMPERATURE I'CI

TA - AMBIENT TEMPERATURE I'CI

"'

Tco

Vee'" 4.5

Twp

Vee '4.5

Vee '" 5.5

Tco

T

T",

vr'r

-75 -50 -25

I
0

N

1
Vl'5 5V

I

Jl

o

N

25

50

75 100 '25

TA - AMBIENT TEMPERATURE ("C)

D

o

:E

NI
N

o
N
:E
:E

ci

~

MOS RAMs

NATIONAL

o

MM2102MD, MM2102-2MD military temperature range
1024-bitfully decoded static random access memo.ries

:E
:E

general description

features

The MM2102 family of 1024 word by one bit static
random access read write memories are· manufactured
using N-channelenhancement mode silicon gate technology_ Static storage cells eliminate the need for clocks
and refresh_ I;)ata in and data out have the same polarity
and the read operation is nondestructive.

• Single +5V supply

•

Low power

Low threshold silicon gate N-channel technology allows
complete DTUTTL compatibility of all inputs and
outputs as well as a single' +5V supply. The separate
chip enable input (CEl controlling the TRI-STATE®
output allows easy memory· expansion by OR-tying
individual devices to a data bus.

•

Fast Access
MM2102
MM2102-2

:E

N

N

• All inputs and output directly DTUTTL compatible
• Static 'operation-no clocks 'or refreshing required
150 mWtyp

1Ms

650 ns

• TRI-STATE output for bus interface
• Chip enable allows simple memory expansion
• On ch ip address decode .

The simple interface and high performance make the
MM2102 family ideally suited for those applications,
for large and small storage capacity, where cost is an
important design consideration.

• All inputs protected against static discharge
• -55°C to +125°C Operation

block and connection diagrams

AD

Dual-I n-line Package

A'

CELL
ARRAV
32 ROWS

A2

16 A7

A6

12COlUMNS

15

,. A.

AS

A3

R/Vii 3

13

A'

12 DATA OUT

A2

R/W

COLUMN 1/0 CIRCUITS

DATA
OUT

••fi

A3

11 DATA IN

A4

10 Va;

AD

GNO

COLUMN SELECTOR

TOP VIEW

A5

A6

A7

AS

Ordor Number MM2102MD
or MM2102-2MD

A9

Se. Pock_go 3

1-12

absolute maximum ratings

s:
s:

(Note 1)

~

o

Voltage at Any Pin
Operating Temperature Range
Storage Temperature Range
Power Dissipation
Lead Temperature (Soldering, 10 seconds)

N

s:C
s:
s:N

--{).5V to + 7.0V
-55°C to +125°C
-65°C to +150°C
1W
300°C

...o

.

N
N

s:C
dc electrical characteristics
(T A within operating temperature range, Vee ~ 5V ±10%, unless otherwise noted.)
PARAMETER

COND.lTIONS

MIN

TYP

MAX

UNITS

V'H

Logical "1" Input Voltage

2.2

V'L

Logical "0" I nput Voltage

-{).5

V OH

Logical "1" Output Voltage

VOL

Logical "0" Output Voltage

10L ~ 2.1 mA

0.45

III

Input Load Current

V'N ~ 0 to 5.5V

10

I LOH

Output Leakage Current

10

/lA

I LOL

Output Leakage Current

CE ~ 2.2V,
-

/lA

Icc1

Power Supply Current

Icc2

Power Supply Current

~

10H

CE

~

-100/lA

~

4.0V

2.2V, V OUT

~

0.45V

~

0.65

2.2

V OUT

All Inputs

Vec

5.5V, Data Out Open,

V
V
V

25

V

-50

/lA

45

mA

55

mA

MAX

UNITS

T A ~ 25'C, (Note 4)
All Inputs

~

5.5V, Data Out Open,

TA ~-55°C to +125°C

ac electrical characteristics
(T A within operating temperature range, Vee ~ 5V ±1 0%, unless otherwise specified.)
See ac test circuit and switching time waveforms.
PARAMETER

CONDITIONS

MIN

TYP

READ CYCLE
t RC

tA

tco

Read Cycle

-

MM2102

RIW ~ V'H

1000

ns

MM2102,2

R/W ~ V'H

650

ns

Access Time
MM2102

1000

ns

MM21022

650

ns

MM2102

500

ns

MM2102·2

400

Chip Enable to Output Time

tOH1

Previous Read Data Valid with

tOH2

Previous Read Data Valid with

ns

50

ns

0

ns

Respect to Address

Respect to Chip, Enable

'·13

III

c

:E

ac electrical characteristics (con't)

...o

N

WRITE CYCLE

:E
:E

twc

N,
N

PARAMETER

TYP

MAX

UNITS

Write Cycle
1000

ns

MM2102-2

650

ns

MM2102

200

ns

MM2102-2

200

ns

MM2102

750

ns

MM2102-2

400

ns

50

ns

MM2102

800

ns

MM2102-2

450

ns

tOH

Data Hold Time

100

ns

tcw

Chip Enable to Write Set-Up Time

tAW

N

o
N
:E
:E

MIN

MM2102

c

:E

CONDITIONS

twp

Address to Write Set-Up Time

Write Pulse Width

tWR

Write Recovery Time

tow

Data Set'Up Time

MM2102

900

ns

MM2102-2

550

ns

CAPACITANCE
C'N

Input Capacitance (All Inputs)

V'N

= OV,

TA

= 25°C,

f

= 1.0 MHz

3

5

pF

"1

10

pF

(Notes 2 and 4)
COUT

Output Capacitance

V OUT

= OV,

TA

= 25°C,

f

= 1.0 MHz

(Notes 2 and 4)
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety'o'f the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Capacitance is guaranteed bV periodic testing.
Note 3: Positive tru'e logic notation is used: Logical "1" = most positive voltage level, Logical "0" = most negative voltage level.
Note 4: Typical values are for TA = 25°C and nominal supply voltage.

"

switching time waveforms
Read Cycle

ADDRESS

CHIP
ENABLE

V,"

Iwe

IRe

'V

V-

.....J
V,"

f~o-

V"
'A

DATA
OUT

Write Cycle

VO"
Voc

ADDRESS

f\...-

VIH CHIP
ENABLE

V"

N.
'AW

READ!
W~ITE

\.... f--/ \...
tOl-l1

~

VIL - - '

~~,
lri\r
-

V-

V'"'V

V,"

lew

~tWR

r-

,~

r-

V"
--'-I""

~

Va"

,. Voc

DATA

Note; All lImes meilsuled with respect til 1.5V level
witllt,and 11 ~20 ns

114

DATA CAN
CHANGE

DATA STABLE

'0"
DATA CAN
CHANGE

3:
3:
~
o
N
3:

ac test circuit

MMZ102

"Delay times

c

CL

T'00PF
mea~ured

3:
3:
N
o

...

at MMZ102 Dutput

typical performance characteristics

NI
N

.,
.E

Power Supply Current vs
Temperature

':

Output Sink Current
vs Temperature

Temperature

All INPUTS '" 5.5V
DATA OUT OPEN

30

20

:r,

10

r--. t-

t- r- r-

,~

'"

t--

o
-75 -50 -25
TA

-

0

25

50

~~-L~

-75 -50 -25

75 100 125

AMBIENT TEMPERATURE

re)

25

50

15

"

;....

400

600

300

~

1.50

"

~

z

....<

1.25

500

I

J

V~

V

/

/

,.

:g
200

>=

400

TA

-

0

25

50

75

100 125

AMBIENT TEMPERATURE (,'C)

1-15

25

50

15

100 125

re)

I

"'"

T

vee:: 4.5

T:,

Vee

~I5

Tw,

VrT

-75 -50 ...,25

Teo

Teo

Vee'" 5.5

100

300
-15 -50 -25
POWER SUPPLY VOLTAGE IVI

I..--' /

Vee - 4.5V

0

Write Pulse Width and Chip
Enable-To Output Delay YS
Temperature

700

>=

w

::::::::

TA - AMBIENT TEMPERATURE

Access Time vs Temperature

~

~

Vee "'4.5V

-'--75 -50 -25

10(1 125

I nput Levels V$ Power

1.75

,I)

!::::~:5V

o

__~~~__~

0

TA - AMBIENT TEMPERATURE lOCI

Supply Voltage

~

~

I-- r--

2

3:

I)
VOl "'O.45V

Vee'" 5.5V

~

"'
!O

YS

40

....

I

Output Source Current

1
0

25

50

75 100 125

TA - AMBIENT TEMPERATURE

eel

c

~

MOS RAMs

NAnONAL

MM2111. MM2111-1. MM2111-2 1024 -bit (256 x 4) static MOS RAM
with common 1/0 and output disable
general description

features

The National MM2111 is a 256 by 4 static random
access memory element fabricated using N-channel
enhancement mode Silicon Gate technology. Static
storage celis eliminate the need for refresh and the
peripheral circuitry associated with refresh. The data is
read out nondestructively and has the same polarity as
the input data. Common Data Input/Output pins are
provided.

•

The 2111 is directly TTL in al.l respects: inputs, outputs
and a single +5 V supply. The two Chip-enables allow
easy selectioFl of an individual package when outputs
are OR-tied. The features of this memory device can be
combined to make a low cost, high performance, and
easy to manufacture memory system.

Organization 256 Words by 4 Bits

•

Common Data Input and Output

•

Single +5V Supply Voltage

•

Directly TTL Compatible - AI.I Inputs and Outputs

•

Static MOS - No Clocks or Refreshing Required

•

Access Time - 0.5 to 1.0 /1s Max.

•

Simple Memory Expansion -

•

Low Cost Packaging - 18 Pin Epoxy B Dual-In-Line
Configurati·on

Chip Enaple Input

•

Low Power - Typical.ly 150 mW

•

Tri-State ® Output - OR-Tie Capability

National's silicon gate technology provides excellent
protection against contamination and permits the use of
low cost Epoxy B packaging.

block and connection diagrams

An

18
---OVCC

A3

18
17

A4

Al

--.s..o

A2

Al

16

RiW

ROW
SELECT

RIW - - - - . __- - '

MEMORY ARRAY
32 ROWS
32 COLUMNS

COLUMN I/O CIRCUITS

VCC

GNO

Ao

15

CEI

A5

14

1/04

A6

13

1/0 3

A7

12

1/0 2

GNO·

11

1/01

00

10

fE2

1/01
INPUT

1/0 2

COLUMN SElECT

DATA
CONTROL

1/03

PIN NAMES
AO-A7
A5

OD
R/W

A7

CE1
CE2
110 1. 1/ 0 4

ADDRESS INPUTS
OUTPUT DISABLE
READ/WRITE INPUT
CHIP ENABLE 1
CHIP ENABLE 2
DATA INPUTIOUTPUT

Order Number MM21110,
MM2111-1D or MM2111-2D
See Package 4

Order Number MM21 1 1 N,
MM2111·1N or MM2111-2N

00

See Package 16

1-16

s:
s:N

absolute maximum ratings

......

O°C to +70°C
Ambient Temperature Under Bias
_65°C to +150°C
Storage Temperature
Voltage On Any Pin With Respect to Ground -0.5Vto+7V
Power Dissipation
1 Watt

s:
s:N

......
...,
dc electrical characteristics
Symbol

Min.

III
ILOH
ILOL
ICCl

Input Current
I/O Leakage Current[2]
I/O Leakage Current[2]
Power Supply Current

ICC2

Power Supply Current

VIL
VIH
VOL
VOH

Input "Low" Voltage
Input "High" Voltage
Output "Low" Voltage
Output "High" Voltage

Note 1:

Typ. [11

Max.

Unit

Test Cond itions

30

10
15
-50
60

Il A
Il A
Il A
mA

70

mA

VIN = 0 to 5.25 V
CE = 2.2 V, Vila = 4.0V
CE = 2.2 V, VI/a = 0.45 V
VIN = 5.25 V, 11/0 = 0 mA
TA'" 25°C
VIN= 5.25 V, 1110 = 0 mA
TA = O°C

+0.65
VCC
+0.45

V
V
V
V

-0.5
2.2

2.2

10L =2.0 rnA
10H = -150 IlA

Typical values are for T A = 25°C and nominal supply voltage.

capacitance

TA = 25°C, f = 1 MHz

Symbol

Limits (pF)

Test

Typ.

Max.

4
10

15

Input Capacitance (All Input Pins) VIN = 0 V
I/O Capacitance VI/O = 0 V

CIN
CliO

s:
s:N

TA = o°c to +70°C, VCC = 5 V ±5%, unless otherwise specified.

Parameter

8

switching time waveforms

READ CYCLE (R/W= "1")

--..

-

.

WRITE CYCLE

.I----tco -------...
. I-.-too---

OUTPUT DISABLE
______- t A - - - - . .

-- ------ ------

DATA I/O

/

\.

1

tOH_

DATA OUT VALID

ADDRESS

r-

!--tOF(1)---

.I-+----- tcw ___________
\.

CEI. CE2 .

--

OUTPUT DISAB~
-4-

-

DATA 110

,-

r r--

--::-1'-'-- tow _____ tDH~I~

to F

-I

DATA IN STABLE

~

ll~twp--------+- --tWR---

READ/WRITE

Note 1:

.

twCY

1,....-

-

,-

ADDRESS

CEt. eE2

.

.,,.-

tRCV

tOF is with respect to the trailing edge of CE1, CE2, or 00, whichever occurs first.

1·17

---tAW~'\

......,
N

......
N
I

ac electrical characteristics

TA = o°c to +70°C, VCC = 5 V ± 5%, unless otherwise specified .

N

:iE
:iE

...;::...
I

N

:iE
:iE

......

N

:iE
:iE

MM2111
Symbol

Parameter

Min.

Typ.

Max.

Unit

1,000
800
700
200

ns
ns
ns
ns
ns

Test Conditions

READ CYCLE
tRCY
tA
tco
too
tDFI1]
tOH

Read Cycle
Access Time
Ch ip Enable to Output
Output Disable to Output
Data OutPut to High Z State
Previous Data Read Val id after
change of Address

1,000

0

ns

Input Pulse Levels: +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20 ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
CL = 100 pF

1,000
150
900
700
100
750
50

ns
ns
ns
ns
ns
ns
ns

Input Pulse Levels: +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20 ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
CL=100pF
..

0

WRITE CYCLE
tWCY
tAW
tcw
tow
tDH
twp
tWR

Write Cycle
Write Delay
Chip Enable to Write
D.ata Setup
Data Hold
Write Pulse
Write Recovery

MM2111-1 (500 ns Access Time)
Symbol

Parameter

Min.

Typ.

Max.

Unit

500
350
300
150

ns
ns
ns
ns
ns

Test Conditions

READ CYCLE
tRCY
tA
tco
too
tDF[1]
tOH

Read Cycle
Access Time
Ch ip Enable to Output
Output Disable to Output
Data Output to High Z State
Previous Data Read Valid after
change of Address

500

0

ns

Input Pulse Levels: +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20 ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
CL = 100 pF

500
100
400
280
100
300
50

ns
ns
ns
ns
ns
ns
ns

Input Pulse Levels: +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20 ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
CL=100pF

0

WRITE CYCLE
tWCY
tAW
tcw
tow
tDH
twp
tWR

Write Cycle
Write Delay
Chip Enable to Write
Data Setup
Data Hold
Write Pulse
Write Recovery

MM2111-2 (650 ns Access Time)
Symbol

Parameter

Min.

Typ.

Max.

Unit

650
400
350
150

ns
ns
ns
ns
ns

Test Conditions

READ CYCLE
tRCY
tA
tco
too
tDF I1 ]
tOH

Read Cycle
Access Time
Chip Enable to Output
Output Disable to Output
Data Output to High Z State
Previous Data Read Valid after
change of Address

650

0

ns

Input Pulse Levels: +0.65 to +2.2 V
Input Pulse Rise and F211 Times:
20 ns
Timing Meas.urement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
CL = 100 pF

650
150
550
400
100
400
50

ns
ns
ns
ns
ns
ns
ns

Input Pulse Levels: +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20 ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
CL=100pF

0

WRITE CYCLE
tWCY
tAW
tcw
tow
tDH
twp
tWR

Write Cycle
Write Delay
Chip Enable to Write
Data Setup
Data Hold
Write Pulse
Write Recovery

1·18

MOS RAMs

s:
s:N
-II
-II

N

s:
s:N

.....
N
N
-II

MM2112. MM2112-2 1024-bit (256 x 4) static MOS RAM
with common data I/O
general description

features

The National MM2112 is a 256 by 4 static random
access memory element fabricated using N-Channel
enhancement mode Silicon Gate technology. Static
storage cells eliminate the need for refresh and the
peripheral circuitry associated with refresh. The data is
read out nondestructively and has the same polarity as
the input data. Common Data Input/Output pins are
provided.

• Organ ization 256 Words by 4 Bits

The MM2112 is directly TTL in all respects: inputs,
outputs and a single +5 V supply. The Chip·enable
allows easy selection of an individual package when
outputs are OR-tied. The features of this memory device
can be combined to make alow cost, high performance,
and easy to manufacture memory system.

• Simple Memory Expansion - Chip Enable Input

• Common Data Input and Output
• Single +5 V Supply Voltage
• Directly TTL Compatible - All Inputs and Outputs
• Static MOS - No Clocks or Refreshing Required
• Access Time - 0.65 to 1 !J.S Max.
• Low Cost Packaging - 16 Pin Epoxy B Dual-In-Line
Configuration
•

Low Power - Typically 150 mW

• Tri-State ® Output - OR.-Tie Capability

National's silicon gate technology provides excellent
protection against contamination and permits the use of
low cost Epoxy B packaging.

block and connection diagrams

16

VCC

A]

----.!.o GNO

AZ

15

A4

Al

14

RIW

-----0

AO

MEMORY ARRAY
32 ROWS
]2 COLUMNS

Ao

I]

EE

A5

12

1104

A6

11

liD]

A7

10

1102

GNU
1101

vCC

1101

COLUMN 110 CIRCUITS

IIOZ
COLUMN SELECT

c....."""---.

liD] ..:..:.........

PIN NAMES
ADDRESS INPUTS
READ/WRITE INPUT
CHIP ENABLE INPUT
110 1. 110 4 DATA INPUT/OUTPUT
POWER (+5 Vi
VCC
AO·A7

R/W

CE

Order Number MM2112D
or MM2112-2D
See Package 3
Order Number MM2112N
orMM2112-2N
See Package 15

1·19

NI
N

.....
.....

N

~
~

absolute maximum ratings
O°C to +70°C
Ambient Temperature Under Bias
_65°C to +150°C
Storage Temperature
Voltage On Any Pin With Respect to Ground -0.5Vto+7V
1 Watt
Power Dissipation

dc electrical characteristics
Parameter

Symbol

Min.

III
ILOH
ILal
ICCl

Input Current
I/O leakage Current
I/O leakage Current
Power Supply Current

ICC2

Power Supply Current

Vil
VIH
Val
VOH

Input "low" Voltage
Input "High" Voltage
Output "Low" Voltage
Output "High" Voltage

Typ.[1]

Max.

Unit

Test Conditions

30

10
15
-50
60

J.l.A
J.l.A
J.l.A
mA

70

mA

VIN = 0 to 5.25 V
CE = 2.2 V, VI/a = 4.0 V
CE = 2.2V, VI/a = 0.45 V
VIN = 5.25 V, 11/0 = 0 mA
TA = 25°C
VIN = 5.25 V, 11/0 = 0 mA
TA = O°C

+0.65
VCC
+0.45

V
V
V
V

-0.5
2.2
2.2

10l = 2 mA
10H = -150J.l.A

Typical values are for TA = 25°C and nominal supply voltage.

Note 1:

capacitance

TA=25°C,f=1 MHz

Symbol
GIN
GI/O

T A = o°c to +70°C, VCC = 5 V ± 5% unless otherwise specified.

limits (pF)

Test

Typ.
4
10

Input Capacitance (All Input Pins) VIN = 0 V
I/O Capacitance Vila = 0 V

Max.
8
18

switching time waveforms
READ CYCLE (R/W = "1 ")
-'W

CE

~-'CO-

u~

"uu"uu,,;;~

.

WRITE CYCLE #2
;

'WCY1

......

I

tWCY2

~

l..-tCSl

-- ~

--"+~CHl

I

\.

X.

INPUT/OUTPUT
READiWRIT;-" ~
tAWl

DATA IN
STABLE

'DH1111-

X

INPUT/OUTPUT

.~

-'WR1-

.1·tDWZ....
_XDATA IN
STABLE

'WDZ--READiWRITE

~tWP1-

.-tCSz

CE

~DW1----+-

.

1-

ADDRESS

CE

Note 1:

'CO~iX

WRITE CYCLE #1

ADDRESS

-

r-

.tAW2_

1--

----i:CHZ
1

X

'1-1DHZ(1)

~'wRz_1

Data Hold Time (TOH) is referenced to the trailing edge of CHIP ENABLE (CE) or READ/WRITE (R/W) whichever comes first.

1-20

ac electrical characteristics

T A = 0° C to +70° C, V CC = 5 V ± 5% unless otherwise specified.

MM2112
Symbol

Parameter

Min.

Typ.

Max.

Unit

1,000
800
200

ns
ns
. ns
ns
ns

Test Conditions

READ CYCLE
tRCY
tA
tco
tCD
tOH

Read Cycle
Access Time
Chip Enable to Output Time
Chip Enable to Output Disable Time
Previous Read Data Val id After
Change of Address

1,000

0
50

Input Pulse Levels: +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20 ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
CL=100pF

WRITE CYCLE #1
Write Cycle
tWCYl
Address to Write Setup Time
tAW 1
Write Setup Time
tDWl
Write Pulse Width
tWPl
Chip Enable Setup Time
tCSl
Chip Enable Hold Time
tCHl
Write Recovery Time
tWRl
Data Hold Time
tDHl
WRITE CYCLE #2
tWCY2
tAW2
tDW2
tWD2
tCS2
tCH2
tWR2
tDH2

Write Cycle
Address to Write Setup Time
Write Setup Time
Write to Output Disable Time
Chip Enable Setup Time
Chip Enable Hold Time
Write Recovery Ti me
Data Hold Time

850
150
650
650
0
0
50
100

100

1,050
150
650
200
0
0
50
100

ns
ns
ns
ns
ns
ns
ns
ns

Input Pulse Levels: +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20 ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TT'L Gate and
CL = 100 pF

ns
ns
ns
ns
ns
ns
ns
ns

Input Pulse Levels: +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20 ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
Cl = 100 pF

MM2112-2 (650 ns Access Time)
Symbol

Parameter

Min.

Typ.

Max.

Unit

650
500
150

os
ns
ns
ns
ns

Test Conditions

READ CYCLE
tRCY
tA
tco
tCD
tOH

Read Cycle
Access Time
Chi p Enable to Output Time
Chip Enable to Output Disable Time
Previous Read Data Valid After
Change of Address

650

0
50

Input Pulse Levels: +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20 ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
CL = 100 pF

WRITE CYCLE #1
tWCYl
tAWl
tDWl
tW01
tCSl
tCHl
tWRl
tDHl

Write Cycle
Address to Write Setup Time
Write Setup Time
Write Pulse Width
Chip Enable Setup Time
Chip Enable Hold Time
Write Recovery Time
Data Hold Time

500
100
350
350
0
0
50
50

50

ns
ns
ns
ns
ns
ns
ns
ns

Input Pulse Levels: +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20 ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
CL = 100 pF

ns
ns
ns
ns
ns
ns
ns
ns

Input Pulse Levels: +0.65 to +2.2 V
Input Pulse Rise and Fall Times:
20 ns
Timing Measurement Reference
Level: 1.5 V
Output Load: 1 TTL Gate and
CL = 100 pF

WRITE CYCLE #2
tWCY2
tAW2
tDW2
twD2
tCS2
tCH2
tWR2
tDH2

Write Cycle
Address to Write Setup Ti me
Write Setup Time
Write to Output Disable Time
Chip Enable Setup Time
Chip Enable Hold Time
Write Recovery Time
Data Hold Time

700
100
350
200
0
0
50
50

1-21

D

MOS RAMs

~
NAnONAL

MM42611MM5261 1024-bit fully decoded
dynamic random access memory
general description
The MM4261/MM5261 fully decoded dynamic
1024 word x l-bit word read/write Random
Access Memory is a monolithic MOS integrated
circuit using silicon gate low threshold technology
to achieve bipolar compatibility on all I/O lines
except the precharge and read/write lines_ This
provides an efficient approach to memory design
using these systems oriented devices_ The MM4261/
MM5261 is used for main memory applications
where large bit storage and improved operating
performance are important_ A TRI-STATE® output is utilized to allow wired "OR" capability and
common I/O data busing in memory applications_

•

Low overhead circuit count

Fully decoded

• Systems-oriented design
Bipolar compatible (address lines, chip enable
data I/O)
Common data I/O line
TRI-STATE output
•

2_0 ms

Refresh cycle

• Easy memory expansion
• Device protection

All 110 lines have protection against static charge

• Low power dissipation

features

• Small package size

• Fast access ti me
300 typ
• Fastcycletime MM4261 600 ns r.ead cycle min
MM5261 500 ns read cycle min
MM4261 750 ns write cycle min
MM5261625nswritecyciemin

Chip enable

400.mW

18 pin dual-in-line package

applications
• High speed mainframe memory
• Mass memory storage

typical application
Main Memory Module Stor,ing 4096 16-Bit Words

!lUlIOR"

_URU!';;:"'c..'---LJ-~---'~------------------'----------;

1-22

absolute maximum ratings

(Note 3)
+0.3V to -22V

All Input or Output Voltages With Respect
to Most Positive Supply Voltage Vss

700mW

Power Dissipation
Operating Temperature Range

O°C to +70°C
-55°C to +125°C
-65°C to +160°C
300°C

MM5261
MM4261

Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)

dc operating characteristics
Vss = +5.0V ±5%, V DD = -12V ±5%, (V BB

-

PARAMETER

(MM4261) T A'" -55°C to +125°C,
V ss ) = 1.5V to 2.0V (Note 2). unless otherwise noted.

CONDITIONS

MAX'

UNITS

VSS - 2.0

Vss + 0.7
Vss - 4.2

V
V

Vss - 1.5
Vss - 15

Vss + 0.7
Vss - 18

V
V

0.4

V
V

6.0

12

rnA

20

34

rnA

100

",A

MIN

TYP

Input Voltage (Addiess Input, Chip Enable
and Data Input)

LogiC "1" IV,H)
Logic "0" IV,c!
Input Voltage (Precharge and Read/Write)
Logic "1" IV,H)
Logic "0" IV,c!

Output Voltage Data Output
Logic "1" IV oH )
Logic "0" (Vo eI

IL = 200",A Source
IL '= '.6 mA Sink

Standby Current INote 11

No Clocks,

Average Supply Current (Iss) (Note 1)

tpw

2.4

CE = V ,H

= 300,

lAC =

600 ns

Vea Supply Current

ac operating characteristics
Vss = +5.0V ±5%. V DD = -12V ±5%. (V Be

(MM4261) T A = -55°C to +125°C.
V ss ) = 1.5V to 2.0V (Note 2)., unless otherwise noted.

-

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Read Cycle ItRc)

600

ns

Write Cycle (twe)

750

ns

+ to + twp
+ tWRP -tAP

Read!Write Cyc:1e (tRwcl

tAce

Address to Chip Enable (tAC)

0

50

ns

Address to Precharge (tAP)

0

50

ns

Precharge Width (tpw)

300

450

ns

Address Hold Time (tAH)

50

ns

Chip Enable Hold Time (tCH)

110

ns

350

Access Time (tAcc)
Precharge 'Off Time (tpp)
Precharge Leading Edge to
(tpwel

Riw Leading Edge

225

ns

300

Read/Write Trailing Edge to Precharge Leading
Edge ItwRP)

225

Precharge Trailing to R/Vii Trailing (tPTW)

225

R/W Delay

ns
500

ns

1.0

rns

)

TYP

MAX

UNITS

5.0

7.0

Chip Enable Capacitance (CCf';)

pF

5.0

9.0

pF

25

45

pF

'10

20

pF

9.0

.pF

(MM4261) (Note 4)

CONDITIONS

PARAMETER

V'N = VSS}
V'N = Vss f = 1 MHz

Pre charge Capacitcfnce (C pc J

V

- V

Read/Write Capacitance (CAW I

V IN = Vs. 5

Data .Input/Output Capacitance (C IN lOUT)

V IN

IN -

ns
ns

INote 6)

capacitance characteristics
Address Capacitance (e A

450

(tPWD)

Refresh Interval (tREF)

ns
ns

Read/Write Pulse Width lt wp )

Precharge to

450

300

55

= Vss

All Unused
Inputs Are
at AC Ground
_

1-23

MIN

7.0

III

dc operating characteristics (MM5261) TA ; o°c to +70°C,
Vss ; +5.0V ±5%, Voo = -12V ±5%, (V BB - V ss ) = 1.5V to 2.0V (Note 2). unless otherwise noted.
PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Input Voltage (Address Input, Chip Enable
and nata Input)
Logic "1" (V 1H I
Logic "O~' (V 1L )

Vss

~2.0

+ 0.7
4.2

V
V

Vss +0.7
Vss ~ 18

V
V

0.4

V
V

Vss
Vss

~

Input Voltage (Precharge and Read/Write)
Logic "1" (V 1H )
Logic "0" (V 1L )

Vss
Vss

~
~

1.5
15

Output Voltage Data Output
Logic "1" (V OH

IL
IL

)

Logic "0" (VOL)

=:
='

200pA Source
1.6 mA Sink

2.4

-

Standby Current (Note 1)

No Clocks, CE = V IH

Average Supply Current (Iss) (Note 1)

trw

250 ns,

=

tRC'=

500 ns

6.0

12

mA

20

34

rnA

100

IlA

Vsa Supply Current

ac operating characteristics (MM5261) TA ; O°Cto +70°C,
Vss ; +5.0V ±5%, Voo = -12V ±5%, (V BB - V ss ) ;1.5V to 2.0V(Note 2). unless otherwise noted.
PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Read Cycle (t Re )

500

ns

Write Cycle (twd

625

ns

tAce + to + twp
+ t WRP ~tAP

Read/Write Cycle (tRwcl

Address to Chip Enable (tAd

0

50

Address to Precharge (tAP)

0

50

ns

Precharge-Width (tpw)

250

400

ns

Address Hold Time (tAH)

50

Chip Enable Hold Time (tCH)

110

ns
ns
300

Access Time (tACC)

ns

400

ns

Precharge Off, Time (tpp)

250

ns

Precharge Leading Edge to R/Vi Leading Edge
(tPWL)

175

ns

250

Read/Write Pulse Width (t wp )
Read/Write Trailing Edge to Precharge Leading
Edge (tWAP)

..

400

200

ns

175

Precharge Trailing to R!WTrailing (tPTW)

ns

Precharge to R/iN' Delay (tPWD)
(Note 6)

Refresh Interval (tREF')

capacitance characteristics
PARAMETER

'. "'~}

Chip Enable Capacitance (CCE)

V1N

Precharge Capacitance (e pc )

V IN = V

Read/Write Capacitance (C RW )

Y,N = Vss

Data Input/Output Capacitance

(GIN/OUT)

500

ns

2.0

rns

(MM5261) (Note 4)

CONDITIONS

Address Capacitance (C A )

ns

= VS5

,

5S

MIN

TYP

MAX

UNITS

5.0

7.0

pF

f= 1 MHz

5.0

9.0

pF

All Unused
Inputs Are

25

45

pF

10

20

pF

7.0

9.0

pF

at AC Ground

V IN = VS5

Note 1: VSS '" 5.0V, Von '" 12V, TA '" 2S"C.
Note 2: Under power turn on conditio~s care must be taken to insure, that VSS is a!~ays the most positive potential in the
system or large transient currents could result causing permanent damage.
Note 3: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to imply that the dev!ces should be operated at these limits. The
table of "Electrical Char'acteristics" provides conditions for actual device operation.
Note 4: Capacitance is guaranteed by periodic testiAg
Note 5: Positive true logic notation is used·
Logic "1" = most positive voftage level
Logic "0" ~ most negative voltage level
Note 6: Each of the 32 rOws addressed by Address inputs AO through A4 must be refreshed withi" the maximum interval,
tREF, by performing a write cycle. The row will be refreshed with Chip Enable (eEl at VIH or VIL. Note, if CE = VIL the
memory cell defined by Address inputs AO thrQugh Ag will be altered In accordance with information present on I/O line

1-24

switching time waveforms

connection diagram

Read Cycle

Dual·1 n·i.ine Package

~------~------~
A,

ADDRESS

I

11 A,

"

.. Z

CHiP
ENABLE

•

.. ••

A,

PRECHARGE

A,

~ . ' - - - - - - - - - - - - - - -__~

A,

..

I/O

.

"..
....,,-

READ' :I
iOIiITf.

mm

14OA1AINI
OUT

"

,
'

PftECHARGE

12yss
I1"DD

"v..

Ne •
TOPYIEW

Write Cycle

1 - - - - - - - -...

Order Number MM4261D
orMM5261D

ADDRESS

See Package 4
Order Number MM5261N

See Package 16

'RECHARGE

.Iii

DATA

IN

CHIP
ENABLE

Read/Write Cycle
I------------~~,--------~-------

110

CHIP
ENAlLE

,t,.cc

w:; "-________________________________+_

NOTE 1: ALL TIMING MEASUREMErfTS MADE WITH 111% TO 90% 1R AND IF $" za lIS FROM"" POINTS.
NOTE 2: ACCESS TWE MEASURED WITH OUTPUT LOADED WITfI DM8OII3 AND 15 IIF.

1·25

MOSRAMs

~

NA1IONAL

MM4262/MM5262 2048-bit fully decoded
dynamic random access read/write memory
general description
The MM4262/MM5262 is a fully decoded 2048
word by 1 bit dynamic read/write random access
memory fabricated using National Semiconductor's
proprietary silicon gate low threshold technology.
All inputs except the clocks are TTL compatible.
The output p,rovides a current pu Ise allowing
a large number of devices to be bussed together
without compromising system performance due
to capacitive loading. The current pulse output
is converted to TTL levels by means of a sense
amplifier.

•

•
•
•

•
•

features

•

Fast access time
Fast cycle time
Short Read
Read/Write
Write
Refresh cycle

•
•

MM4262
470 ns (max)

MM5262
365 ns (max)

565 ns (min)
750 ns (min)
750 ns (min)
1.0 ms

475 ns (min)
635 ns (min)
635 ns (min)
2.0 ms

MM4262
MM5262
Low power
Operating
360 mW (max) 400 mW (max)
Standby
2.5 mW (max) 2.5 mW (max)
+5.0V, +8.5V, -15V
Power supplies
Fully decoded with internal
Low overhead
circuits
memory add ress register
System oriented design
Bipolar compatible except for .clocks
Current sense output
Chip Select for easy memory expansion
Package
22 pin DIP (Cavity and Molded)
Device protection
All inputs and outputs
protected against static charge

applications
•
•
•
•

Core memory replacement
Mainframe memory
Buffer storage
Non-volatile memory using battery back up

block and connection diagrams
As

Ae

A7

Ae

161

(1J

(I)

(B)

DUQ:I-I n-Line Package

,,--CHIPSELECT

Ag

no)

21

CLOCK1'';1t191~

ClDCIC2.~

1171¢--"

CLOCK l. ~ UI'

(4) DATA OUT

"

y--+

"
"
"

DATA OUT

V~D(51~

~DD

V.1201~

17

VIIB (116--+

A. (16)

I

v~

CLOCK 1 (0,",
CLDCKl(·'31

CLOCK2il':zl

A.

~(151

X ADDRESS

(COLUMN)

204B-BITDYNAMIC
RAMMATAIX

~(141

(3)

Am

..
A7

:: : : ) Y ADDRESS
Z

1l

A,
A"

I
IL

DATA IN

11

12

'------'

.,

(Z2)

_________________

Ci

~

TOP VIEW

Order Number MM42620
orMM52620

See Package 5
Order Number MM5262N

See Package 17

recommended interface circuits
CLOCK DRIVERS:

MH0026
MH8808

SENSE AMPLIFIERS:

LM167
LM168
DM7806/DM8806

'·26

A,
Ao

(ROW)

absolute maximum ratings
Voltage at Any Pin
Power Dissipation
Operating Temperature Range

v •• + O.3V to V •• -

(Note 1)
27V (Note 16)

1.OW
-55°C to +125°C
aOc to +70°C

MM4262 (T CASE)
MM5262 (T AMBIENT)

-65°C to +150°C
300°C

Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)

dc electrical characteristics
V BB

-

CONDITIONS

PARAMETER

Inputs
(Chip Select, Read/Write,

MM4262 (-55°C:::; TeASE:::; +125°C, VSS = 5.0V ±0.25V,

=-15V ±1.0V, unless otherwise noted)

Vss = 3.5V ±0.5V, Voo

TYP
(NotoI8)

MIN

MAX

UNITS

(Notes 14. 151

Addresses, f?ata In)
Voltage
Logical "1" CVIHI
Logical "0" (V, d

Vss
Vss

o~

Current

1.5
10

Vss

VIN ~ Vss

1.0

t

Vss

4.2

1.0

V
V
~A

Clock Inputs
Voltage
Logical "1" (V IPH )
Logical "0" (V 41L )

Vss
Voo

VIN =

Current

Outputs
Current

1.0
1.0

Vss I 1.0
Voo t 1.0

~16V

V
V

50

"A

100
6.0

mA

(Note 15)

Logical '''0'' (lOL J
logical "1" (lOH I
Leakage Current

Power Supply Current

V OUT

= OV
= 1.2V. CS = 0.4V
= 1.8V. CS = O.4V

V OUT

= OV. CS = 3.5V

V OUT

VOUT

I

10

~A

18

mA

(Note 17)
T A :: 2SoC, V aB

- Vss = 3.5V. Vss = 5.0V,
Voo ='-'5V, VOUT = 1.2V, Reading l's at

T CYCLE"" 750 ns

(100)
(lB.)

~A
~A

500

12

Operating
Standby (No Clocks)

150
100

~A

~A

ac electrical characteristics MM4262 (All times measured from 50% points, t" tf:::; 20 ns,
see ac test circuit and timing diagram, conditions under dc electrical characteristics apply.)
CONOITIONS

PARAMETER

MIN

TYP
(Note 181

MAK

UNITS

ns

4>, Clock Pulse Width (T, pw)

(Not. 41

115

70

4>2 Clock Pulse Width (T 2PW)

(Note 6)

275

160

, Clock to <1>2 Clock Delay IT 121

(Note 51

110

60

ns

1/>2 Clock to 2 Clock to t/>3 Clock Delay (T 23)

(Note 7)

50

10

ns

r/>, Clock to t/>, Clock Delay (T,,)

(Note 9)

60

40

n,

Chip Select and Address Set Up
Time (T Asl

80

60

ns

Chip Select and Address Hold
Time (TAH)

90

50

n,

Read/Write Read Set Up Time

70

30

ns

65

30

ns

75

30

n,

PARAMETER

CONDITIONS

MAX

UNITS
ns

400

ns

(T Rwsa)

Read/Write Read Hold Time

n RWH3)
ReadlWrite Write Set Up Time
(T RWS ,)

1-28

ac electrical characteristics (con't)

MM5262

CONDITIONS

PARAMETER

s:
s:
~

MIN

TYP
(Note 18t

MAX

en
......

25

0

ns

(Note lOt

120

60

ns

(Note 101

60

30

ns

50

20

ns

ReialWrite Write Hold Time

(T.wo3 t
logical "1" Data Ir:t Set UpTime

(Tos,t
Logical "0" Data In Set Up Time
Data In Hold Time (TOHl )

Read Access Time (T ACC2)
Read Access Time IT Ace,)

T Ace , :: T As

Read Only Cycle

(Note

(TSHOAT/AEAOI

+ Tt2 + T ACC2

In

Read. Write, Read Modify Write
Cycle (TCYCLE)
Refresh Time

(Note 121

Output Hold Time (TOH t

(Note 13t

Chip Select, Address, ReadlWrite,
Data In, Data Out Capacitance (ex)

~

N

s:
s:C1I
N

en

(Too,l

~,

N

UNITS

Clock Capacitance (C, t
Clock Capacitance (C,l

195

ns

365

ns

475

ns

635

ns
2.0

ms

7.0

pF

1000

V Be - Vss = 3.5V, ~ss
V TEST = 5.0 Voe With

C""

150
300

=

ns

s.av

$15mVRMSat
f = 1.0 MHz

50

pF

25

pF

25

pF

Clock Rise/Fall Time

100

ns

!nput Rise/Fall Time

50

ns

tIJ:J Clock Capacitance

(e3 )

Note 1; "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The
table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2:' Capacitance is guaranteed by periodic testing.
Note 3: Positive true logic notation is used: Logic "1" = most positive voltage level
Logic "0" = most negative voltage level
Note 4: T 1 pW, <1>1 clock - used to change input logic address and chip select.
Note 5: T 12, interval between clock 1 and 2 - for decode.
Note 6: T2PW, <1>2 clock - cell access.
Note 7: .T23, interval be~ween clock 2 and 3 - decision time.
Note 8: T3PW. CP3 clock - write or refresh clock.
Not8 9: T31. write recovery 'time.
Note 10: If a "1" is being written then data in must go high TOSI before the end of <1>2 and remain in that state until TOHI
after cP3 goes low. If a "0" is bei~g written. data in must go low at least T052 before CP3, and remain in that state until TDHl
after <1>3 goes low.
Note 11: For a short read cycle, <1>3 may be inhibited and the next cycle may begin T23 after <1>2.
Note 12: Addresses AO through A4 are the row addresses. To accomplish a refresh, at least one location in each row must be
accessed during any 2 ms period for the MMS262 and 1 ms for the MM4262. The row will refresh when reading or writing with
the chip disabled or enabled as long as <1>3 is applied.
Note 13: During a read cycle the output will remain valid until the next V

Pin Names
AO-A11

Address Inputs'"

Vee

PoWer (-5V)

CE

Chip Enable

Voo

Power (+12V)

TSP

TRI·SHARE Pon

Vss

Ground

*Refresh Addess

AO~A5

A2

absolute maximum ratings

(Note 1)
O°c to +70°C
-65°C to +150°C
'-O.3V to +25V

Operating Temperature Range
·Storage Temperature
All Input or Output Voltages with Respect
to the Most Negative Supply Voltage, VSB
Supply Voltages Voo and Vss with
Respect to Vss
Power Dissipation

-o.3V to +20V
1.0W

dc electrical characteristics
TA

= O°C to +70°C, Voo

=

+12V ±5%, VBB (Note 2)

I nput Load Current

ILl

=-5V ±5%, V~ = OV, unless otherwise noted

PARAMETER

SYMBOL

CONDITIONS
V IN

""

MIN

TYP(3)

MAX

0.01

10

OV to V IH max, (All Inputs

UNITS
p.A

hceptCE)
ILC

I nput Load Cu rrent

VIN

10

p.A

Output Leakage Current Up
For High Impedance State

CE

= OV to V'HC max
= V'LC' Vo = OV to 5.25V

om

ILO

0.01

10

p.A

' Voo Supply Current During

CE

=

-IV to +0.6V. (Note 4)

110

p.A

20

mA

35

mA

1001

CE "'OFF"
'002

V OD Supply Current During

CE = V'HC' TA = 25°C

CE "ON"

= 230 ns
= 230 ns.

'ODAV1

Average V DO Current

TA = 25°C. Cycle Time·= 400 ns,

100 AV2

Average V OD Current

TA

IB8

V BS Supply Current Average

V'L

Input Low Voltage

V'H

Input High Voltage

VILe

CE Input Low Voltage

-1.0

V 1HC

CE Input High Voltage

Voo-l

VOL

Output Low Voltage

10L

VOH

Output High Voltage

10 H'

:::

tCE

2SoC. Cycle Time = 1000 ns,

mA

15

tCE

tT

= 20 ns.

0.6

-1.0

(Figure41

2.4

= 2.0mA
= ~2.0 mA

p.A

100

5

V
V

Vcc +l

V

1.0

V
V

0.45

0.0

V

2.4

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for ··Operating
Temperature Range"' they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"

provides conditions for actual device operation.
Note 2: The only requirement for the sequence of applying voltage to the device is that VDO or VSS should never be O.3V more negative than
VilB·
.
Note 3: Typical value. are for T A = 25" C and nominal power supply volteges.
Note 4; The IDD current is to VSS. The IBB current i. the sum of ali leakage currents.

ac electrical characteristics
SYMBOL

I

T A = o°c to +70°C, Voo = 12V ±5%, Vee = -5V±5%
CONDITIONS

PARAMETER

I

MIN

I

TYP

I MAX I UNITS

READ, WRITE, READ/MOOIFY/WRITE, AND REFRESH CYCLE
tSEF

'. Time Between Refresh

2

Address to CE Set·Up Time

tAH

Address Hold Time

50

ns

tee

CE"'OFF" Time

130

ns

tAC

is MeasuredFrom End of Address Transition

0

ms

tAC

ns

tT

CE Transition Time

10

teF

CE "'OFF" to Output High
Impedance State

0

40

ns·
ns

tTC

TRI·SHARE Port to CE Set·Up
Time

0

-ns

tTH

TRI·SHARE Port Hold Time

50

ns

READ CYCLE
tCY

Cycle Time

tCE

.CE "'ON" Time

tco

CE Output Delay

tAce

Address to Output Access

tTL

CEto TSP

ns

400

tT"" 20 ns

C~OAO

= 50 pF. Load = One TTL Gate

230

Ref 1 = 2.0V. Ref 0 = O.BV
tAcc

= tAC + teo

+ tT
0

1·35

3000

ns

180

ns

200

n;
ns

U

o

t:::;

switching time waveforms

It)

~
~
Read Cyel.

T CV {400J

V,H
ADDRESS
CAN
CHANGE

ADDRESS

V,L

~

tACtO) -

CD
0

CD

-

~tA-H(5Oj~

CE

CD

TSP CAN
CHANGE

---10)

0

K

ADDRESS CAN CHANGE

.. ----

tTI20J~

-~~~-TCE(230)

II

II

1\
___ fCCt"301

~V1\
CHANGE

1--.

.,~.,-.--.--

, -®

t COI1801

HIGH IMPEDANCE

_tTUO)

. ..

~tCFtOl

.

Refresh Cyel.

-CD
CD

)(

ADDRESS CAN CHANGE

CE

CD

/

--- ----

tT(201~

..

tcE(230)

V 1HC

-

OOI-

tT(20)~

l\

CHANGE'

®

...'.,----

TSP CAN CHANGE

_'0",.,_1. I
f'OHlO1

D,.

DIN

CAN CHANGE

CD

V"

VOL -

J
I-- '<:CI130I---

/

I--;--

V'H

DouT

~tTI20'

r--

\

twP/50l

.EV

VOH -

f-- ----

I---

V'L

.{

-

®

i-I-

tTC[O)~

TSP,

t Tl20, ......
tcRW(410)

f-tcO[l80l------

-

-

-

-

-

WJ

1-

~V®

-1=-=- - --./ CD
HIGH IMPEDANCE

I\.

tACC[200I~

r--

DIN STABLE

two(50)

DIN

CAN CHANGE

MAX

-- ------ - - - -- - HIGH IMPEDANCE

Note 1: If DIN' is forced prior to DOUT becoming high impedance (tIlVDIMAX'). then maximum ambient
temperature should be der.ated by TWfTCYCLE (35"C). Where Toy is time between forcing DIN and Dour
becoming TRI-STATE.
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:

V1L MAX is the reference level for measuring timing of the addresses. Tsp and DIN'

V'H MIN is the reference level for mnsuring timing of the addresSeS. TSf' and DIN.
Vss' +' 2.0V is the reference level for measuring timing of CEo
Voo - 2V is the reference level fOT m~uring timing of CEo
Vss + 2.0V i'S the reference level for ml:8suring the timing of Dour for a high output.

Note 7: Vss + 0.8V is the reference level tor measuring timm9 of Dour for a low output.
Note 8: For minimum cycle. ~ = 0, for test purposes tM = 10 ns.

1-38

pF

with the current equal to a

~

'MOS RAMs

NA110NAL

MMS270-S TRI-SHARETM4096-bit random access read/write memory
genera I description

features

The MM521()'5 is a slower speed version of National's
MM5270 dynamic RAM. Please refer to the MM5270
specification for pin configuration, block diagram and
switching time. waveforms.

• Access time-270 ns
• Cycle time-470 ns

absolute maximum ratings

o

(Note 1)
Order Number MM527OD-5

O°Cto +70°C
--uSoC to +150°C
-:-D.3V to +25V

Operating Temperature Range
Storage Temperature
All Input or Output Voltages with Respect
to the Most Negative Supply Voltage, Vse
Supply Voltages Voo and Vss with
Respect to V ss
Power Dissipation

SaePac,,-4

-:-D.3V to +20V
1.0W

dc electrical characteristics
T A = o·c to +70°C, Voo = +12V ±5%, Vee (Note 2) = -5V ±5%, Vss
SYMBOL
ILl

PARAMETER
Input Load Current

=OV. unless otherwise noted

CONDITIONS
V,N

=

=OV to V tHC max

MIN

OV to VIH max. (All Inputs
Except CEI

TYP{31

MAX

0.01

10

0.D1

10

/JA

0.01

to

p.A

I,c

Input Load Current

V IN

11,01

Output leakage Current Up
For High Impedance State

CE

tOOl

Veo SuI9PIV Current During
CE "OFF"

110

1002

VDO Supply Current Ouring
CE"ON"

20

lOOAv1

Average VDO CU rrent

TA

=:

'OOAV2

Aver$Qe v'OD Current

TA

= 2SoC, Cycle Time = 1000 ns, teE;::: 300 ns

~

V,Le. Vo

~

OV '" S.2SV

25"C, Cycle Time!:: 470 AS, teE

= 3QO"ns

35

rnA

15

rnA

5

IBB

Vee Sup:pJy Current Average

V"

Input low Voltage

-1.0

V,~

Input High Voltage

2.4

VILe

CE Input Low Voltage

-1.0

V 1HC

CE Input High Voltage

Voo-l

VOL

Output Low Vortage

10L· 2.0 mA

0.0

VOH

Output High Voltage

lo~ =

2.4

-2.0 mA

UNITS

100

0.6
Vcc +l

/JA
V
V

1.0

V

V DD +l

V

0.45

V
V

Note 1: "Absolute Maximum Rating$" ere those values bevond which the safetY of tbe devioe '"!nnot be guaranteed. ElICBpt for "Operating
Temperature Range" mey are not meant to imply th,.t the devi_ ~1d be .OPllnttOEl .at th... limits. Tile table of "EI~riea.1 Characteristics"
provide!l conditions for actual device operation.
Not. 2: Tile only requirement for the sequence of applVing voltage to me device i. that VOO or VSS should newr be O.3V mor.e.negative than
VBB·
Note 3: Typical values are for T A = 26" C and nominal power supply voltages.
Note 4: The 11}0 current i. to VSS. The ISB current is tile sum of all leakage cur .."t•.

1·39

ac electrical characteristics
T A = o°c to +70°C~ V DD = 12V ±5%, V BB = -5V ±5%

CONDITIONS

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

READ. WRITE. READ/MODIFY/WRITE. AND REFRESH CYCLE
tREF

Time Between Refresh

tAc

Address to CE Set-Up Time

2

ms

0

n,

tAH

Address Hold Time

50

n,

tcc

CE "OFF" Time

130

tT

CE Transition Time

10

tCF

CE "OF F" to Output High

0

n,

0

"5

80

n,

tAC is. Measured From End of Address Transition

n,

40

n,

Impedance State
tTc

TRI-SHARE Port to CE Set-Up
Time

tTH

TRI-SHARE Port Hold Time

READ CYCLE
n,

tCY

Cycle Time

tCE

CE "ON" Time

tco

CE Output Delay

tAce

Address to Output Access

tTL

CE to TSP

0

tCY

Cycle Time

470

tCE

CE "ON" Time

300

tWI

TSP to CE "OFF"

150

tcw

CE to TSP

tD

O'N to CE "OFF"

150

ns

tDH

0

0

ns

twp

TSP Pu Ise Width

50

ns

650

ns

470
tT

-= 20 ns

C LOAO

= 50 pF.

Load

=One TTL Gate

300

3000

ns

250

ns

Refl = 2.0V. Ref 0 = 0.8V

270
tAce = t AC

ns

+ teo + tT
ns

WRITE CYCLE

1,"\1

tT =

ns

3000

ns

20 ns

115

Hold Time

ns

ns

READ/MODIFY/wRITE CYCLE

t RWC

Read Modify Write (RMWI
Cycle Time

3000

480

n,

tCRW

CE Width During RMW

twc

TSP to CE "ON"

tT = 20 ns

a

n,

tW2

TSP to CE "OFF"

C LOAD = 50 pF, Load -= One TTL Gate

200

n,

twP

TSP Pulse Width

Ref 1 - 2.0V. Ref 0 " O.8V

50

ns

tD

DIN to CE "OFF"

tAce = t Ac

150

ns

tDH

DIN Hold Time

tco

CE to Output Delay

180

+ teo + tT

ns

0

n,

tAce

Access Time

270

ns

two

TSP to Output High Impedance

250

n'

tM

Modify Time

n,

0

CAPACITANCE (Note 11
CAD

Address Capacitance. CS

V 1N

:=:

CCE

CE Capacitance

V 1N

= Vss

ClIO

Data 110 C(lpacitance

V OUT

C'N

TSP Capacitance

V 1N

Vss

'"

OV

= Vss

Note 1: Capacitance measured with. Boonton Meter or effective capacitance calculated from the equation C '"'
constant 20 mA.

1-40

2

pF

15

pF

8

pF

5

pF

IAt/~V

with the current equal to a

~

MOS RAMs

Advance Information

NAl10NAL

MM5271 TRI-SHARETM4096-bit fully TTL compatible
dynamic random access read/write memory
general description
The MM5271 is a fully tTL compatible 4096-bit dynamic
random access memory. with TRI-SHARE. Because of
this unique design fea~ure, National is able to house a
4k device in an 18-pin dual-in-line package. The device
is manufactured using N,channel silicon gate technology
with a single transistor cell which provides higher density
'On a monolithic chip and thus I'ower ·cost.

write, the TSP must be pulsed low after the minimum
hold time and the appropriate data placed 011 the I/O.
When the MM5271 goes into write, the output circuit is
disabled. If the TSP is low at the start of the cycle, the
memory is not selected but it will be refreshed when the
chip enable clock is pulsed.

The TRI-SHARE Port (TSP) is a multifunction input
that, along with a common input/output, allows National
to manufacture an l8-pin version of a 4k RAM. The
functions controlled by the TSP are read/write, Vee,
and logical chip select. In order to understand how the
TSP works, consider the timing diagrams. The state of
the TSi' at the leading edge of the chip enable clock
determines whether the device .is selected. If it is at a
TTL high level, the chip is selected and the device goes
into a read mode after chip enable goes high. This high
level also controls the Vee 'function in that it enables
a reference voltage for a TTL high output. The supply
for the output buffer is V oo , not the TR I-SHA RE Port; .
thus, no special driver is required. In order to perform a

features

01

•
•
•
•
I!I

4096 x 1 bit organization
Access time 250 ns maximum
Cycle time 400 ns minimum
TRI-SHARE port
High memory density-18-pin package

•
•
•
•
•

TTL compatible inputs
TR I-STATE® com~on input/output
Registers on chip for addresses and chip select
Two. power supplies, +12V, -5V
Simple read-modify-write operation

block and connection diagrams
Dual-In-Line Package
TIP(5)

CRi1'

Vss

AI

h.

Al1141
AlO(3)

n

Al

11

Ali

15

AI 121

Voo

EIDil

"

AS

"

13

A4

A3

to

11

ASlnI
AlIIl)
A6(151
A5(121

110

MII1I
A3UO)

(6)

l-

r-

A2~1

AliI)
AD I")

,

I
~

M

3

m

• • • , • I'
w

m

~

M

TO. VIEW

Order Number MM5271D
Sa. Package 4

VDO (14) _ _ +lZV
YssUII--OV

Yu l1l - - - ' v

Pin Names
AO-All

Address Inputs *

VB.

Power (-5V)

CE

Chip Enable

Voo

Power (+12V)

TSP

TRI-SHARE P9rt

Vss

Ground

·Refresh Addess AO--AS

1-41

M

A2

absolute maximum ratings

(Note 1)
oDe to +70 o e
--u5°e to +150o e
-O.3V to +25V

Operating Temperature Range
Storage Temperature
All Input or Output Voltages with Respect
to the Most Negative Supply Voltage, VSB
Supply Voltages Voo and Vss with
Respect to V ss
Power Dissipation

-D.3V to +20V
1.0W

dc electrical characteristics
TA

oDe to +70o e, Voo - +12V ±5%, Vss (Note 2) - -5V ±5%. Vss - OV, unless otherwise noted

-

SYMBOL

PARAMEnR

CONOlnONS

ILl

Input Load Current

VIN

IILOI

Output Leakage Current Up

CE

MIN

OV to V1H max

TYP(3)

MAX

UNITS

0.01

·10

IlA

= V IH , Va = OV to 5.25V

0.01

10

IlA

CE

= V ,H , (Note 41

1

mil.

CE

= V'c, TA

20

mA

mA

::::

For High Impedance State
1001

V DO Supply Cun-ent During

CE "OFF"
1002

Voo Supply Current During

= 25°C

CE"ON"
100 AVl

Average Voo Current

T A = 25·C, Cycl. Time = 400 ns, tCE

35

100 AV2

Average V DO Current

TA = 25·C. Cycle Time

15

IBB

Vee Supply Current Average

V'c

Inpu~

V ,H

Input High Voltage

Low Voltage

= 240 os
= 1000 ns, teE = 240 ns

5
tT = 111' fl', (Figure 4)

mA
100

IlA

0.6

-1.0

V

2.4

V cc+l

V

0.45

V

Voc

Output Lew Voltage

lac =2.0mA

0.0

VOH

Output High Voltage

IOH = -2.0ml!.

2.4

V

Note 1: "Absolute Maxir:num Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for 1.I0perating

Temper"ature Range" they are not meant to imply'mat the devices should be operated at these. limits. The table of "Electrical Characteristics"
provides conditions for actual device opeEGtion.
Note 2: The only requirement for the sequellCe of applying voltage to the device is that VOO or VSS should never be 0.3V more negative then
VBB'
Note 3: Typical values are for T A = 25" C and ROminal pellU8r supply voltages.
Note 4: The IDO ~urrent is to VSS. The IBB curren';'. the sU,m of aU leekage current••

ac electrical characteristics
SYMBOL

Til. = oDe to +70°C, Voo

PARAMETER

=12V ±5%, VSB =...sv ±5%

CONDlTI.ONS

MIN

TVP

M~X

I

UNITS

READ, WRITE, REAO/MODIFYtWRITE, AND REFRESH CYCLE

Time Between Refresh

tcc

ms

o

ns

Address Hold Time

100

ns

CE "OFF" Time

140

Address to CE Set·Up Time

tAC is MeasuredFrom End of Addre~s Transition

CE Transition Time

ns
40

ns
ns

50

CE "OFF". to Output High
I~pedance State

TRI-SHARE Port to CE Set·Up

'0

llS

Time
TRI-SHARE Port Hold Time

ns

100

REAOCVCLE
tCY

Cycle Time

tCE

CE"ON"Time

tco

CE Output Oelay

400

tT=10ns
CCOAO = 50 pF, Load = One TIL'Gate

Address to Output Access
CE to TSP

240

Ref 1 = 2,QV, Ref 0 = O.BV

ns

3000

ns

250

ns

250

t,.cc = lAC + leo

o
142

ns

switching time waveforms

Read Cycle
~--------------T~(~OII----------------~

ADDRESS

'y (10)
VIL----------r---~~------------------------'I

TSP

VIH---------.~~_r--------------------------_r~~----~
V,L

D

i-----Ico (2501----1
VOH - - - - - - - - - - - -.....
HIGH IMPEDANCE

VOL -

-

,- -

-,... -

-

-

---------,

1 - - - - - - 'ACe (250)------1-1

Refresh Cycle (Sea Note 11

1-----------------TCy (4001-------,---------..,
VIH
ADDRESS

V,L

ADDRESS
CAN
CHANGE
'AC

'y (101

(01

V,H
i!JiImAlI[E

V,L

'TC (0)
V,H
TSI'CAN
CHANGE

TSP

V,L

VOH-~ -

-

-

-- -- -

-

-

-

-- -

-

--

HIGH IIilPEDANCE

~------------------Note 1: For Refresh cvcle. row and -;.olumn addresses must be stable before tAC and remain 5t1ble for
entire tAH period.
Note 2: V1l MAX is the reference level for measuring timing of ttie addresses. Tsp and DIN and CE.
Note 3: VIH MIN is the reference levet for.measuring timing of the addresses, lsp and DIN and CE.
Note 4: Vss + 2.0V is the referen~ level for measuring the timing of DouT for a higb out!"'t.
Note 5: Vss + n.lv is the reference level for measuring timing of QOUT for a low output.

1-43

ac electrical characteristics (con't)
SYMBOL

T A = O°C to +70°C, Voo = 12V ±5%, Vee = -5V ±5%

PARAMETER

MIN

CON OI.TI ONS

TYP

MAX

UNITS

WRITE CYCLE.

Cycle Time

tCE

CE "ON" Time

240

tw,

TSP to CE "OFF"

100

-

lcw

CE to TSP

to

D'N to

tOH

'wp

ns

400

tCY

, 'T

= 10 ns, (No'e 4)

3000

130

CE "OFF"

ns
ns
ns

70

ns

DIN Hold Time

50

ns

TSP Pu Ise Width

50

ns

switching time waveforms (con't)

Writ. Cycl. (S•• Not. 4)
Tcy (400)
-'AH(100)V'H

Q?

) fCP®

ADDRESS

-

V'L
V,H
CHIP ENABLE

®

®\

'TC (0)-1

V,L

TSP
CAN
CHANGE

1I

®
--tcwIMAXI (130)_

1\\

/

r-'TH (100)-

,·f

~,wp(~O) I--'ee (140)_

V TS~ C~N

CHANGE

10. "~'"-HI- }'""0" ~,""M"

V'H
D'N CAN CHANGE

D'N

I--tT (10)

I--'T(10) -'w,(100)-

V,H
TSP

ADDRESS CAN CHANGE

teE (240)

'AC (0)

V'L

K

V,L

'0(70)

------ ----

VOH

- - - - - - - - -

VOL

- - - - - - - - - - - - - - -

HIGH IMPEDANCE

GOUT

Note 1: For Refresh cyele, row and column addresses must be stable before
entire

tAH

tAc

----

and "main stable for

period.

Note2: V1L MAX is1he reference level for measuring timing of the addresses, lSI" and DIN and CE.
Note 3: VIH MIN is the reference levelfor measuring timing of the addresses, TSf" and DIN and CE.
Note 4: If tcwlMAXI is greater than 130 os then memory operation is like ReadlModifylWrite cycle.

1-44

ac electrical characteristics (con't)
SYMBOL

TA ~ O°C to +70°C, V DD ~ 12V ±5%, Vss ~ -5V±5%
CONDITIONS

PARAMETER

MIN

TYP

MAX

UNITS

READ/MODlFYIWRITE CYCLE
Read Modify Write (RMW)

t RWC

560

ns

Cycle Time
tCRW

CE Width During

'W2

TSP to CE "OFF"

C LOAD

Ref 1 . 2.0V, Ref 0

tT'"

RMW

400

10 ns

3000

ns

-

t~p

TSP Pulse Width

to

D'N to

tOH

DIN Hold Time

tco

CE to

CE "OFF"

=;;

50 pF, Load'" One TTL Gate

tAce == t AC

~

0.8V

+ teo

150

os

50

ns

70

ns

50

ns

Output Delay

250

ns

tAce

Access Time

250

ns

two

TS? to Output High Impedance

50

ns

tM

Modify Time

0

os

CAPACITANCE INote 1)
CAO

Address Capacitance, CS

V 1N

=0

Vss

2

C eE

CE Capacitance

V 1N

""

Vss

5

pF

ClIO

Data I/O Capacitance

V OUT -= OV

8

pF

C'N

TS? Capacitance

V IN

5

pF

""

Vss

pF

Note 1: Capacitance measured wi'th Boonton Meter or effective capacitance calculated from the equation C == ltJ.t/AV With the current equal to a
constant 20 rnA.

switching time waveforms (con't)
Read ModifV Write Cycle

T Rwe (560)

:--tAH (100)V'H

ADDRESS)
CAN
CHANGE

ADDRESS
V IL

~

0
0

K

ADDRESS CAN CHANGE

0\

CHIP ENABLE
-

-l

trc (0)

r-

twp (50)

tdl0)-

II

TSP CAN
CHANGE
V'l

®
It. (0)-'-

I-:-

V'H
O'N CAN CHANGE

O'N

I--

V'l

wI

_

-td1DI

V

0

V'H
TSP

~tdlD)

teRw (400)

'AC (0)

I---tW2 (150)_

V'H

V1L

0
0

VOH

- - -

VOL

- - -

teo (250) -

-

---,;) ®
HIGH IMPEDANCE

DOUT

(j)

---

@)

-tec(1401-

TSPrCtN CHANGE

1--

-to (70) -

)~$ D'N STABLE
,-- tWDIMAX)

tOH (50)

K

D,N CAN CHANGE

(50)

-------HIGH IMPEDANCE

--------

--lAce (250)--

Note 1: For Refresh cycle, row and column addresses must be stable before tAC and remain stahle for
entin!

tAH

period.

Note 2: V1L MAX is the reference Jeveffor measuring timing of the addresses, Tgp and DIN and EE.
Note 3: ViH MIN is the reference level for measuring timing of the 'addresses, TSf' and DIN and CE.
Note 4: Vss + 2.0V. is the reference level for measuring the timing of DouT for a high output.
Note 5: Vss + D.BV isthe reference level for measuring timing of DouT for a low output.
Note 6: For minimum cvcle, tM = O. for test purposes ~ = 10 ns.
Note 7: If DIN is forced prior to OOUT becoming high impedance (tWDjMAXIl. then maximum
ambient temperature shou~ derate~ by Tov/TcYCLE (35°C). 'Where Tov is time
between forcing DIN and OouTbecoming TRI-STATE'.

MOS RAMs
MM5280 4096-bit dynamic random access memory
general description
National's MM5280 is a 4096 word by 1 bit dynamic
RAM. It incorporates the latest memory design features
and can be used in a wide variety of applications, from
those which require very high speed to ones where low
cost and large bit capacity are the prime criteria.

in the on-chip peripheral circuits, yields a high performance memory device.

The MM5280 IT]ust be refreshed every 2ms. This can be
accomplished by performing a read cycle at each of the
64 row addresses (AO-A5). The chip select input can
be either high or low for refresh.

•
•
•
•

The MM5280 has been designed with minimum production costs as a prime criterion. It is fabricated using
N·channel silicon gate MOS techn910gy, which is an ideal
choice for' high density integrated circuits. The MM5280
uses a single transistor cell to minimize the device area.
The single device cell, along with unique design, features

•
•
•
•

features
Organization: 4096 x 1
Access time 200 ns maximum
Cycle time 400 ns minimum
Easy system interface
• One high voltage input-chip enable
• TTL compatible-all other inputs and output
Address registers on-chip
TRI·STATE® output
Simple read-modify-write operation
Industry standard pin configuration

block and connectien diagrams

mnz--------------------1
1:'1(5)

Dual-In-line Package
Al1(4)
A1Q(J)
AI (2)

I"

AI'Z1)

"lUI

Z1

"

\9

"

" "

11

14

"

12

Ali 1'1}

Ail'S)

MIt.
Al(131

AZl1ut
AHa)

ADell

, , , •
CEI171

v.

AI

--.,OY

AID

All

5

Ef

• , • ,
0 1111

DoUr

AD

Al

TOPVIEW

You It.)
'laCUl'--OV

v.nI ___.v

Ordor Number MM5280D

S.. Package 5

Vc:cI11I - - ' ....

Pin Names
Address Inputs *
Chip Enable

VB.

Power (-5V)

CE

Vee

Power (+5V)

Voo

Power (+12V)

D'N

Chip Select
Data Input

Vss

DouT

Data Output

WE

Ground
Write Enable

NC

Not Connected

AO~All

es

*Aefresh Address AU-A5

1,46

111
A2

111
Vee

absolute maximum ratings
Operating Temperature Range
Storage Temperature

(Note 1)
o°C to +70°C

AII.lnput or Output Voltages with Respect
to the Most Negative Supply Voliage, VBB

-Q.3V to +20V

Supply Voltages VDD, VCC and VSS with

--s5"c to +150"C

Respect to VBS

-Q.3V to +25V

Power Dissipation

1.25W

dc electrical characteristics
TA = o°c to +70°C Voe = +12V ±5%, Vcc = +5V ±5%, Vss (Note 2) = --5V ±5%, Vss = OV, unless otherwise noted.
PARAMETER

SYMBOL

Input Load Current

ILl

CONDITIONS
VIN

= OV

MIN

TYP

to V 1H max, (All Inputs

MAX

0.01

10

UNITS
pA

Except CE)
I LC

Input Load Current

V IN = OV to V 1HC max

0.01

10

pA

IlLOI

Output Leakage Current Up For

CE = V'Le or CS = V ,H , Va = OV to 5.25V

0.01

10

pA

1001

V DO Supply Current During

CE = -lV to +6V. Note 4

110

pA

20

rnA

35

rnA

High Impedance State

CE "OFF"

V00 Supply Current During

1002

CE "ON"
100 AV1

Average V DO Current

Cycle Time

AV2

Average Voo Current

Cycle Time

100

V cc Supply Current During

ICCl

= 400 ns, tCE = 230 ns
= 1000 ns, tCE = 230 ns

rnA

15
0.01

CE= V'Le or CS= V,H.INote 5)

10

pA

100

/-LA

CE "OFF"
I ••

VBS Supply Current Average

V ,L

Input Low Voltage

V ,H

Input High Voltage

VILe

CE Input Low Voltage

V1HC

CE Input High Voltage

VOL

Output Low Voltage
Output High Voltage

V OH

5
-1.0

tT = 20 ns (Figure 4)

2.4

0.6

V

V ec +l

V

1.0

V

V oo +l

V

-1.0

10L

= 2.0rhA

0.45

V

Vee

V

IOH = -2.0mA

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for UOperating Temperature Range" they are not meant to implv that the devices shoUld be operated at these limits. The table of "Electrical Characteristics" provides
conditions for actual device operation.
Note 2·: The only requirement for the sequence of applying voltage to the device is that VDO. Vee, and VSS should never be O.3V more negative
than VBB.

Note 3: Typical values are for T A:::: '2SoC and nominal power supply voltages.
Note 4: The tDD and ICC currents flow to VSS. The Isa current is the ,sum of all leakage currents.
Note 5: During CE "'ON" Vee ,supply current is dependent on output loading. Vee is connected to output buffer only.

ac electrical characteristics
SYMBOL

I

TA = o°c to +70°C, Vee = 12V ±5%, Vcc = 5V ±5%, Vss = -5V ±5%

PARAMETER

CONDITIONS

I

MIN

I

TYP

I

MAX

I

UNITS

READ. WRITE, READ/MODIFY/WRITE. AND REFRESH CYCLE

tREF

Time Between Refresh

tAC

Address to CE Set-Up Time

tAH

2
t AC is Measured From End of Address Transition

ms

0

ns

Address Hold Time

50

ns

Icc

CE "OFF" Time

130

tT

CE Transition Time

10

tCF

CE "OFF·' to Output High

0

ns
40

ns
ns

Impedance State
READ CYCLE
tty

Cycle Time

400

tCE

CE "ON" Time

230.

tco

CE Output Delay

tAce

Address to Output Access

tWL

CE to

WE

0

ns

twe

WE to CE "ON"

0

ns

C LOAD = 50 pF, Load = 1 TTL Gate, Ref = 2.0V,

tAce ""

tAC

+ teo + 1 tT

1-47

ns
3000

ns

180

ns

200

ns

s:
s:
C1I

N
00

o

o

~

ac electrical characteristics (con't)

~

T A : O°C to +70 o C, V OD

:E

SYMBOL

I-

:

12V ±5%, Vcc : 5V ±5%, V BB

PARAMETER

:

-5% ±5%

CONDITIONS

MIN-

I-

TYP

I

MAX

UNITS-

WRITE CYCLE

ns

ICY

Cycle Time

400

ICE

CE "ON" Time

230

Iw

WE 10 CE "OFF"

150

ns

tcw

CE to WE

100

ns

to

D'N to CE Sel-Up

150

ns

tOH

D'N Hold Time

0

ns

twp

WE Puis. Width

50

ns

switching

'T

= 20 ns

time waveforms
Read and Refresh CycleG)
Icv (400)

ADDRESS
ANDCS

V'H
VOL
icE (230)
V.He

CE
VILe

WE
) - - - - - - - I c o (180)------1

~

Write Cycle
Icv 1400)
ADDRESS
AND CS

CE
VILe

---"",",@

V'H

.WE

WE CAN CHANGE

V'L
V'H
D'N

D'N CAN CHANGE

V'L

OOUT

~i""'-VOL

~

---

Note 1: For refresh cyde, row and column addresses must be stable before tAC and remain stable for entire tAH Plltriod.
Note 2: V1L max is the reference levettor measuring timing of the address, &Sand DIN.
Note3: V1H min is the reference level tor measur,iog timing of the addresses, CS and DIN.
Note 4; Vss + Z,OV is (he reference level for measuring timing of CEo
Note 5: VDb -2V is the reference level for measuring timing of CEo
Note 6: Vss + 2.0V is the reference level for measuring the timing of GOUT for a high output.

1-48

3000

ns

s:
s:

ac electrical characteristics (con't)
T A = oDe to +70o e, Voo = 12V ±5%, Vee = 5V ±5%,
SYMBOL

I

I

PARAMETER

Vss

U1

= -5% ±5%

N

I

CONOITIONS

I

MIN

I

TYP

MAX

I

CO

UNITS

READ/MODIFY/WRITE CYCLE
t RwC

Read Modify Write (RMW)

. ns

520

,

Cycle Time
tCRW

CE Width During RMW

350

twc

WE

a

ns

150

ns

50

ns

150

ns

tw

to CE "ON"

-

WE to CE "OFF"

twp

WE Pulse Width

to

DIN

tOH

DIN. Hold Time

tco

CE to Output Delay

two

WE to DouT Invalid

tA'CC

Access Time

tT

0=

Ref

20 ns, C LOAD =
=

50 pF,

3000

ns

Load = 1 TTL Gate,

2.0V, tAce '" tAC + teo + 1 tT

to CE Set· Up

0

ns
180

ns

200

ns

0

CAPACITANCE (Note 1)

T A = 25°C

CAD

Address Capacitance, CS

VIN = Vss

CCE

CE Capacitance

VIN ;;::

Vss

COUT

Data Output Capacitance

VOUT

=

C 'N

DIN and WE Capacitance

OV

2

pF

15

pF

5

pF

4

pF

-

VIN = Vss

Note 1: Capacitance measured with Boonton Meter or effective capacitance calculated from the equation C;;:: IAt/AV with the current
equal to a constant 20 rnA.

switching time waveforms (con't)
Read Modify Write Cycle

ADDRESS
AND CS

VI~)
V'L
tAC(O)--

g

t Rwe (520)
ADDRESS VALID

K

~tAH(50)~

V.He

)(

ADDRESS CAN CHANGE

~tT(20)_

tCRW (350)

®

I--

r

I--

CE
V,Le V,H

WE

tw (150)

®

-

-twe (0)



U)

DM74L89A

0

+70

= 5.0V, TA = 25°C unless otherwise specified.
LIMITS

CONDITIONS
MIN

UNITS
TYP

MAX

Logical "1" Input Voltage (V ,H )

Vee = Min

Logical "1" Input Current (I,H)

Vee = Max, Y'N = 2.4V
Vee = Max, Y'N = S.5V

Logical "0" Input Vortage (V,d

Vee ~ Min

0.7

V

Logical "0" Input Current (l,d

Vee = Max, Y'N =0.3V

-180

/lA

Input Clamp Voltage (VeD)

Vee = Min, liN =-12 rnA

-1.5

Logical "1" Output Current (I OH )

Vee = Max, V OUT = 5.5V

50

2.0

V
10
100

0.4

/lA
/lA

V
/lA

Logical "0" Output Voltage (Vod

Vee = Min, lOUT = 3.2 rnA

Supply Current (lec!

Vee = Max

IS

19

Propagation Delay to a Logical "0" From
Address to Output (t pdO )

Vee = 5.0V, TA = 25"C

78

ISO

ns

Propagation Delay to a Logical "1" From
Address to Output (tpd' )

Vee = S.OV, TA ~ 2SoC

90

ISO

ns

Propagation Delay to a Logical "0" From
Memory Enable to Output (tpdO)

Vee = S.OV, T A = 25°C

33

60

ns

Propagation Delayto a Logical" 1" From
Memory Enable to Output (tpd')

Vee ~ 5.0V, TA = 25"C

64

90

ns

V
rnA

ns

Write Enable Pulse Width

Vee = S.OV, TA = 25°C

50

Setup Time, Data Input

Vee = 5.0V, T A = 25°C

0

ns

Hold Time, Data Input

Vee = 5.0V, T A = 25°C

0

ns

Setup Time, Address Input

Vee = 5.0V, TA = 25°C

0

ns

Hold Time, Address Input

Vee =5.0V, T A = 25°C

0

ns

Setup Time, Memory Enable

Vee = 5.0V, TA = 25°C

0

ns

Hold Time, Memory Enable

Vee = 5.0V, TA = 25°C

0

Sense Recovery Time From Write Enable (tSR)

Vee = 5.0V, TA = 25°C

110

165

ns

Disable Time From Write Enable (tEN)

Vee = S.OV, TA = 25°C

47

71

ns

30

ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the de~ice cannot be guaranteed. Except
.for "Operating Temperature Range" they are not meant to imply that the 'devices should be operated at these limits. The
table of "electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the O°C to +7CtC range for the DM74L89. All typicals are
given for Vee = 5.0V and TA =25 °C.
Note 3: All currents into device pins shown as positive, out of device pins as negative. all voltage referenced to ground unless
otherwise noted. All valu'es shown as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.

connection diagram

(Dual-in-Line Package)

s,

GN'

TOP VIEW

2-5

.j:I.

r-

Temperature (T A)

(Notes 2 and 3) Vee

PARAMETER

MIN

s:.....

operating conditions

truth table

MEMORY
ENABLE

WRITE
ENABLE

OPERATION

0

0

0

,

Write
Read

,

X

Hold

OUTPUTS

Logical "1" State
Complement of Data
Stored in Memory
Logical "1" State

~

Bipolar RAMs

NAnONAL

DM54S189/DM74S189 64-bit random access
memories with TRI-STATE® outputs
general description
These 64-bit active-element memories are monolithic
Schottky-damped transistor-transistor logic (TTL) arrays
organized as 16 words of four·bits each. They are fully
decoded and feature a chip-enable input to simplify
decoding required to achieve the desired system organiza·
tion. The memories feature PNP input transistors that
reduce the low level input current requirement to a
maximum of -0.25 mA, only one·eighth that of a
DM54S/DM74S standard load factor. The chip-enable
circuitry is implemented with minimal delay times to
compensate for added system decoding.

input is high and the chip·enable is low. When the chipenable input is high, the outputs will be in the high·
impedance state.
The fast access time of the DM54S189 makes it
particularly attractive for implementing high·performance
memory functions requiring access times on the order
of 25 ns. The high capacitive-drive capability of the
outputs permits expansion without additional output
buffering. The unique functional capability of the
DM54S189 outputs being at a high impedance during
writing combined with the data inputs being inhibited
during reading means that both data inputs and outputs
can be connected to the data lines of a bus·organized
system without the need for interface circuits.

The TRI-STATE output combines the convenience of
an open·collector with the speed of a totem·pole output;
it can be bus·connected to other similar outputs,yet it
retains the fast·rise·time characteristics of the TTL
totem·pole output. Systems utilizing data·bus lines with
a defined pull·up impedance can employ the open·
collector DM54S289.

features

Write Cycle: The complement of the information at the
data input is written into the selected location when both
the chip·enable input and the read/write input are low.
While the read/write input is low, the outputs are in the
high-impedance state. When a number of the DM54S189
outputs are bus·connected, this high·impedance state
will neither load nor drive the bus line, but it will allow
the bus line to be driven by another active output or a
passive pull·up if desired.
Read Cycle: The stored information (complement of
information applied at the data inputs during the write
cycle) is available at the outputs when the read/write

• Schottky·clamped for high·speed applications:
access from chip-enable input
12 ns typ
access from address inputs
25 ns typ
• TRI·STATE outputs drive bus·organized systems
and/or high capacitive loads
• DM54S289, DM74S289 are functionally equilva·
lent, have open-collector outputs, and are compat·
ible with Intel 3101A in most applicationS
• DM54S189 is guaranteed for operation over the full
military temperature range of -55°C to +125°C
• Compatible with most TTL and DTL logic circuits
• Chip-enable input simplifies system decoding

connection diagram

truth table

DuaHn-Line and Flat Package

,
Vcr

1.6

SHECT INPUTS

B
15

,.

,
D

DATA
INPUT
4

13

DATA
OUTPUT
V.
11

12

INPUT
3

OUTPUT
V3

10

INPUTS
FUNCTION

CHIP
ENABLE

READ!
WRITE

OUTPUT
High Impedance

Write

(Store Complement of Datal

0-

Read
Inhibit
H

H

Stored Data

X

High Impedance

High Level

L
X

H

Low Level
0

Don't Care

Order Number DM54S189J or DM74S189J
SElECT
CHIP
INPUT A ENABLE

READI
WRITE

DATA

OUTPUT

INPUT

Yl

1

OATA
INPUT

See Package 10

OUTPUT
V2

Ordor Number DM74S189N

2

Sao Package 15

TOP VIEW

2-6

absolute maximum ratings
Supply Voltage. Vee
. Input Voltage
Output Voltage

Storage Temperatufe Range
Lead Temperature (Soldering. 10 seconds)

operating conditions

(Note 1)

7.0V
5.5V
5.5V
~5°e to +150o e
3000 e

Supply Voltage (Vee)
DM54S189
DM74S189
Temperature (T A)
DM54S189
DM74S189

MIN

MAX

UNITS

4.5
4.75

5.5
5.25

V
V

+125
+70

°e
°c

--55
0

electrical characteristics
over recommended operating free-air temperature range (unless otherwise noted) (Notes 2 and 3)

PARAMETER

LIMITS

CONDITIONS
MIN

VIH

High Level Input Voltage

VIL

Low+Levellnput Voltage

VOH

High-Level Outp'ut Voltage

VOL

Low Level Output Voltage

UNITS

MAX

TYP

V

2
0.8

LIOH = -2.0 rnA. DM54S189
I IOH = -6.5 rnA. DM74S189
.
I DM54S189
Vee = MIn.l oc = 16 rnA I

Vee

-==

2.4

M'

In

V

3.4
3.2

2.4

V
0.5

DM74S189

V

0.45

IIH

High Level I "put' Current

Vee" Max. VI = 2.7

25

p.A

II

High Level 'nput Current·at Maximum Voltage

Vee

1.0

rnA

IlL

Low Level I nput Current

=Max. VI = 5.5V
Vee =Max. VI = 0.45V

los

Short Circuit Output Current (Note 4)

Vee = Max. Va =OV

-30

-250

ilA

-100

rnA

110

rnA

Icc

Supply C,urrent (Note 5)

Vee = Max

VIC

Input Clamp Voltage

Vee

= Min, I. = -18 rnA

-1.2

V

IOZH

TRI·STATE Output Current. High Level Voltage

Vee

= Max. Vo = 2.4V

50

p.A

10ZL

TRI-STATE Output Current. Low Level Voltage
Applied

Vee

=Max. Vo = 0.45V

-50

p.A

75

Applied

"'

switching chara.cteristics
over recommended operating ranges of TA and Vee (unless otherwise noted)

LIMITS
PARAMETER

CONDITIONS

OM54S189
MIN

DM74S189

TYP(1)

MAX

MIN

UNITS

TYP{1J

MAX

tAA

Access Times From Address

25

50

25

35

ns

teZH

Output Enable Time to

12

25

12

17

ns

12

25

12

17

ns

22

40

22

35

n,

22

40

22

35

n,

ten

High Level

Access Times From

Output Enable Time to

ehip Enable

Low Level
twZH

Output Enable TIme to
High Leve'

twZL

eL =30pF. RL = 2800.
(Figure II

Output Enable Time to

Sense Recovery Times
From ReadlWrite

Low,level

2-7

en
CO
.-

en
;!
:E

switching characteristics (con't)

........

0

PARAMETER

LIMITS
CONDITIONS

en

CO
.en

MIN
tCHZ

'It

it)

:E
0

tCLZ
tWHZ

Output Disable Time
From High Level

CL = 5 pF. RL
(Figur.l)

Output Disable Time
From High Level

MAX

25

12

17

os

25

12

17

ns

MAX

12

12

..

Output Disable Time
From low level

TYP(1)

TYPll)

Disable Times From
Chip Enable

MIN

= 280n

Disable Times From
Read/VVrite

12

12

ns

12

12

ns

tWLZ

Output Disable Time
From Low Level

twp

Width of Write-Enable Pulse (ReadiWrite Low)

25

25

tASW

Set-Up Time (Figure 1)

0

0

Address to Read/VVrite

tosw

Data to ReadIWrite

25

25

tcsw

Chip·Enable to
Read/Write

0

0

Hold Time (Figure 1)

Address From ReadIWrite

0

0

tOHW

Data From ReadIWrite

0

0

tCHW

Chip-Enable From

0

0

tAHW

UNITS

DM74S189

DM54S189

ns

ns

ns

Re~d!Write
Note 1: "Absolute Maximum Ratings" are those, values beyond which the safety of the device cannot, be guaranteed. Except'for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified minimax limits apply across the -5SoC to +12SoC temperature r'ange for the DM54S189 and across the O°C to
+7(j°C range for the DM74S189. All typicals are given for VCC = 5.0V and TA = 25°C.
Note 3: All currents into device pins shown as positive, out of device pins as negative, aU voltages referenced to ground unless otherwise noted. All
values shown as max or m in on absolute value basis.
Note 4. Only one output at a time should be shorted.
Note 5: ICC is ~easured with all inputs grounded, and the outputs open.

switching time waveforms
f-tAM~

JV

CHIP ENABLE
INPUT
(SEE NOTE J)

DV
"1.5V

-~"---1

V

WAVEFORM 2
ISH NOTE 1)

OH

~"

""'1.5V

~

INPUTS

ov __ J

------

--,

-lAJ:lW-

DATA
INPUTS

D.'V

ov---

--

_ _ J' /

-'V
) ,~---

1.5V

---tcsw---

D.5V

:-T

~

,.5V
DV

-'.,-

JV

Enable and Disable Time From Chip Enable

f-,'ICflW-

JV~

CHIP·ENABlE
INPUT

---

...1.5V

- - IOflW -

,

JV

~

--I tOH'

r~.5V·

tosw-"

7<-'

-~,"--j

;Yak

-

JV~

ADDRESS

/I"""

~T

WAVEFGRM 1
(SEE NOTE 1)

Yo,

I

-

"

1.5V

;7

'-!:SV

READ/WAITE
INPUT

OV

ADDRESS
INPUTS
(NOTE,2)

OUTPUT

JV~~-------"""'{
15V

v:: -- /tAA--~1

'l.SV

~

~

WAVI;fORM 1
(NOTE 1)

15V

~':I--,---_.

Yo,
WAVEfORM2
(51 OPEN,
52 CLOSED}
(NOTE I)

~5V

Yo, _________________, ____________- 'y..sv

Access Time From Address Inputs

V

OH _ _ _ _

'1.5V

~V

.:......--..:.:tWH::.:..'-:t~_f--'W'H-k'
.
'\J
'1
o.'v

'" T

t

D.SV

Write Cycle
FIGURE 1

Note 1: Waveform 1 is for the output with internal conditions such that the output is low 'e>;.cept when disabled. Waveform 2 is for the output
with internal conditions such that the output is high except when disabled.
Note 2. When measuring delay times from address inputs, the chip enable input is low and the read/write input is high.
Note 3: When measuring delay times from chip enable input, the address inputs are steady-state and the read/write input is high.
Note 4: Input waveforms are supplied by pulse generators having the following characteristics:, tr :S 2.5 ns, tf :S. 2.5 ns, PRR :S. 1 MHz, and
ZOUT ~ 50n.

2-8

ac test circuit

block .diagram

l

A :.

ADDRESS

IN'UTS

a

'0 14

64-6ITMEMORY

ADDRESS
BUFFERS

TEST
POINT

MATRIX
ORGANIZED

1 OF 16

DECODERS

16 ~ <1

fROM

°uU~~~~

13

-1f---.-II4-i

TEST

10k

CHIP ENABLE (CE)
REAO/WRtTe (RtW)

DATA INPUT'

m

C( IIlcllldes plobe arid
An d,odes31e lN3064

-+_+.J

_,==,_ _

VI

Y2

Y)

Y4.1

OUTPUTS

2-9

1'9 tapaCl!a,,~.

o
o
en

Bipolar RAMs

N

~
::!
o
......

o

o

N

en

•::!

DM54S200/DM74S200 256-bit read/write schottky
memories with TRI-STATE®outputs

I.C)

o

general description
The DM54S200/DM745200 256-bit active-element
memories are monolithic transistor-transistor logic
(TTL) integrated circuits prganized as 256 words
of one bit each_ They are fully decoded and have
three gated memory-enable inputs to simplify
decoding required to achieve the desired system
organization. The memories feature PNP input
transistors which reduce the low-level input current
requirement to a maximum of -0.25 milliamperes,
only one-eighth that of a normalized Series 545/
745 load factor. The memory-enable circuitry is
implemented with minimal delay times to compensate for added system decoding.
The TRI-STATE output combines the convenience
of an open-collector with the speed of a totempole output; it can be bus-connected to other
similar outputs, yet it retains the fast-rise-time
characteristics of the TTL totem-pole output.
Write Cycle: The complement of the information
at the data input is written into the selected
location when all memory-enable inputs and writeenable input are low. Whi.le the write-enable input
is low, the output is in the high-impedance state.
When a number of outputs are bus-connected, this
high-impedance output state will neither load nor
drive the bus line, but it will allow the bus line to

be driven by another active output or a passive
pull-up if desired_

Read Cycle: The stored information (complement
of information applied at the data input during
the write cycle) is available at the output when the
write-enable input is high and the three memoryenable inputs are low_ When anyone of the
memory enable inputs is high, the output will be
in the. high-impedance state_

features
• Schottky-clamped for high-speed memory
systems:
Access from memory-enable inputs 20 ns typ
Access from address inputs
31 ns typ
Power dissipation
1_7 mW/bit typ
• TRI-STATE output for driving bus-organized
systems and/or highly capacitive loads
• Fully decoded, organized as 256 words of one
bit each.
• Compatible with most TTL and DTL logic
circuits
• Multiple memory-enable inputs to minimize
external decoding

block and connection diagrams
ADDRESS

Dual-In-Line arid Flat Package

IfI'UTS

ADDRUS
NfIIUTS

I

s""
F ''''
E III

.m

~
ADORESS
IDUlI

MIl

-a .,

O";'UT AOO~ESS ,.D
INPUT

Tor VIEW

Order Number DM54S2OOJ
or DM74S200.J
SaaP"",,-10

Order Nu...... DM74S2OON
SaaP"",,-15
D....r Number DM54S2OOW
or DM74S2OOW
Saa PacIcaga 28

c

absolute maximum ratings

operating conditions

(Note 1)

MIN
Supply Voltage, VCC
Input Voltage
Output Voltage

s:UI

7.0V
5.5V
5.5V

~

UNITS

en

N

Supply Voltage (V CC)
DM54S200
DM74S200

Storage Temperature Range
-6So C to +150°C
Lead Temperature (Soldering. 10 seconds)
300°C

MAX

5.5
5.25

4.5

4.75

Temperature (TAl
DM54S200
DM74S200

-55

V

V

c

s:

+125
+70

o

o
o

......

~

(f)

N

o
o

recommended operating conditions
PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

High Level' Output Current (I OH )
DM54S200
DM74S200

-2.0
-5.2

rnA
mA

Low Level ,Output Current (I OL )

16

rnA

Width of Write Enable Pulse (tw)
DM54S200
DM74S200

Setup Time

50
40

OS
ns

o

os
os
os

10
10

ns
ns
ns

(tSETUP)

Address to, Write Enable
Data to Write Enable
Memory Enable to Write Enable

o
o

Hold Time (tHOLD)
Address from Write Enable
Data from Write Enable
Memory Enable from Write Enable

o

electrical characteristics
PARAMETER

(Note 2)
CONDITIONS

MIN

High Level Input Voltage (V'H)

TYP

0.8

Input Clamp Voltage (V,)

Vee = Min, I, = -18 rnA

High Level Output Voltage (V OH )

Vee

Off State (High Impedance State)

Output Current

(IO(OFFd

= Min, V 1H = 2.0V,
V'L = D.8V, IOH = Max
Vee = Min, V'H = 2.0V
V'L = O.BV, IOL = Max

-1.2
2.4

Vee" Max, V, = 5.5V

High Level Input Current (lIH)

Vee = Max, V, = 2.7V

Low Level Input Current (IlL)

Vee

Short Circuit Output Current (los)

Vee

= Max, V, = 0.5V
= Max

V

V
V

0.5
0.45

DM54S200
DM74S200

Vee = Max, V'H = 2.0V
Vo = 2.4V
Va = 0.5V

Input Current at Maximum Input
Voltage (I,)

UNITS

V

2.0

Low Level Input Voltage (V IL )

Low Level Output Voltage (Vod

MAX

V

50
-50

1.0

mA

25
-250

-30

-100

mA

130

mA

(Note 3)
Supply Current (Icc!

Vee = Max (Note 5)

2-11

87

o
o
N

(I)

~
:E
Q
......

o
o
N

U)

switching characteristics AI.I Typical Values are at Vcc = 5.0V, T A
SYMBOL

tpLH

tpHL

IIIIt

in

:E
Q

tZH

PARAMETER
CONDITIO,.S

PARAMETER
Propagation Delay Time.
Low to Hjgh Level Output

tze
'ZH
tze

Access Time from

Access Time from

High to low Level Output

Address

Output Enable Time to

Access Times from
Memory Enable

Output Enable Time to
Low Level

Access Times from
Memory Enable

Output Enable Time to

Sense Recovery Times

High Level

from Write Enable

Output Enable Time to
Low Level

Sense Recovery Times
Disable Times from

High Level

Memory Enable

Output Disable Time from
low Level

Disable Times from
Memory Enable

'HZ

Output Disable Time from
High Level

Disable Times from
Write Enable

tez

Output Disable Time from
Low Level

Disable Times fr.om
Write Enable

tL.Z

UNITS
TYP

MAX

33

MIN

TYP

MAX

·70

33

50

ns

29

70

29

50

ns

21

45

21

35

ns

10

30

10

20

ns

24

50

24

40

ns

12

50

12

40

ns

7.0

30

7.0

20

ns

20

45

20

35

ns

13

40

13

30

ns

16

40

16

30

ns

C e =30pF,
Re = 300n

from Write Enable

Output Disable Time from

tHZ

DM74S200

DM54S200
MIN

Address

Propagation Delay Time,

High Level

TEST
CONDITIONS

= 25°C. (Note 2)

C e = 5.0 pF

Re = 300n

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to imply that the devices shoulc;l be operated at these limits. The
table of "Electrical Characteristics" prov.ides conditions for actual device operation.
Note 2: Unless otherwise specified minimax limits apply across the -55°C to +125°C temperature range for DM54S200 and
across the oOe to +70o e range for the DM74S200. All typicals are given for Vee = 5.0V and TA = +25°e.
Note 3: Duration of the short-circuit should not exceed one second.
Note 4: All voltage values are with respect to network ground terminal.
Nota 5: ICC is measured with the write enable and memory enable inputs grounded, all other inputs at 4.5V, and the output
open.

truth table

ac test circuit
Vee

TEST

INPUTS
FUNCTION

POINT

OUTPUT

MEMORY
ENABLEt

WRITE
ENABLE

L

L

High Impedance

Read

L

H

Stored Data

InhiQit

H

X

High Impedance

Write ·(Store

FROM

O~J~~~

Complement
olDa,a)

_ ....-_........~........

TEST

•

loOk

~

~,

"

H'" hIgh level, l " low level, X "irrelevant
tFor memory enable: L::: all M~ inputs low;

CL INCLUDES PROBE AND JIG CAPACITANCE.
ALL DIODES ARE lN3064.

H "one or more ME inputs high.

2·12

c

!:

switching time waveforms

A"RESS 3OV=f - - - INPUT

:SV

(SEE MOTE II

OV-

:::

J

~',

toV

U'I

t

~

UJ
N

l.GV

15V

' - ____ _

o

AODRESS
INPUTS

~"F

o
......

c

l.DV

!:
~

...

UJ
N

MEMORY

o

ENABLE
INPUTS

l.OV
WRITE
ENABLE

MEMORY ENABLE
INPUTS (SEE NOTE CI

o

l,GV

INPUT

ov---4-'---~---------J'

~ 1.IiV
WAVEFORM I

WAVEFORM 1

(SEE NOTE AI

(SEE NOTE A)

vo.--4--I_'-'-----¥

----f-:--tJ'-t-......+

Voc----4'"T""J

v~--------I_r~--------~

v~

WAVEFORM 2

WAVEFORM 2

iSEENOTEAI

(SEE NOTE AI

-----t-X

" 1.5Y

NOTE A: WAVEFOAM liS FOR THE OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE
OUTPUT IS LOW nCEPTWMEN DISABLED. WAVEFORM 218 FOR THE OUTPUT WITH INTERNAL

CONDITIONS SUCH THAT THE OUTPUT IS HIGH EXCEPTWKEN DISABLED.
NOTE B: WHEN MEASURING DELAY TIMES FROM ADDRESS INPUTS, THE MEMORY ENABLE
INPUTS ARE LOW AND THE WRITE ENABLE INPUT IS HIGH.
NOTE c: WftEN MEASURING DELAY TIMEs FROM MEMORY ENABLE INPUTS. THE ADDRESS
INPUTS ARE STEAOY·STATE AND THE WRIn ENABLE INPUT IS HIGH.
NOTE 0: INPUl WAVEfORMS ARE SUPPLIED BY PULSE GENERATORS HAVING THE FOLLOWING
CHARACTERISTICS: t.::;. 2.5 ns, I, :..: Z,S ns, PRR:;. 1.11 MHz, AND louT ~ Sll.!.

2-13

~

Bipolar RAMs

NAnoNAL

DM54S206lDM74S206 256-bit read/write schottky
memories with open-collector outputs
general description
The OM54S206/DM74S206 256-bit active-element memories are monolithic transistor-transistor logic (TTL)
integrated circuits organized as 256 words of one bit
each. They are fully decoded and have three gated
memory-enable inputs to simplify decoding required to
achieve the desired system organization. The memories
feature PNP input transistors which reduce the lowlevel input current requirement to a maximum of
-0.25 milliamperes, only one-eighth that of a normalized Series 54S/74S load factor. The memory·
enable circuitry is implemented with 'minimal delay
times to compensate for added system decoding."

Read Cycle: The stored information (complement of
information applied at the data input during the write
cycle) is available at the output when the write-enable
input is high and the three memory-enable inputs are
low. When anyone of the memory enable inputs is
high. the output will be off.

features
• Schottky-clamped for high-speed memory systems:
Access from memory-enable inputs
17 ns typ
Access from address inputs
35 ns typ
Power dissipation
1.4 mW/bit typ
• Open-collector output for word expansion
• Fully decoded, organized as 256 words of one bit
each
• Compatible with most TTL and DTL logic circuits
• Multiple memory-enable inputs to minimize external
decoding

Write. Cycle: The complement of the information at
the data input is written into the selected location
when all memory-enable inputs and write·enable input
are low. WhHe the write-enable input is low, tile output is off.

block and connection diagrams

ADDRESS
INPUTt

Dual·ln-Line and Flat Package

"

!
111}

•

FIlIII

ADDRESS

INI'UTS

9

4-TO-16
LINE

E I I DECODER

om

~

V

ME.

INPUTS

0

GNU

OU1PUT ADDRESS

ADDRESS

INPUT

TO' VIEW

iiI
OUTPUT

y

Order Number DM54S206J or DM74S206J

SaeP,",*-10
Order Number DM74S206N
See Packege 15
Order Number DM54S206Wor DM74S206W
See Package 28

2-14

absolute maximum ratings

operating conditions

(Note 1)

Supply Voltage (VCCI
DM54S206
DM74S206

7.0V
5.5V
5.5V
-il5°C to +150°C
300°C

SupplV Voltage, Vex;
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldering, 1.0 seconds)

Temperature (TAl
DM54S206
DM74S206

MIN

MAX

UNITS

4.5
4.75

5.5
5.25

V
V

+125
+70

o'C
°c

-55
0

operating conditions
PARAMETER

CONDITIONS

MIN

TYP

Low Level Output Current (loLl

MAX

UNITS

16

mA

Width of Write Enable Pulse (tw)
DM54S206
OM 74S206

50
40

ns
ns

Setup Time (tSETUP)
Address to Write Enable
Data to Write Enable
Memory Enable to Write Enable

0
0
0

ns
ns
ns

10

ns
ns
ns

Hold Time (tHOLO)
Address from Write Enable
Data from Write Enable
.Memory Enable from Write Enable

10
0

'I

electrical characteristics

(Note 2)

PARAMETER

CONDITIONS

High-Level Input Voltage (V IH )

MIN

TYP

MAX

V

2

Low-Level Input Voltage (VILl

0.8

V

-1.2

V

Input elamp voltage

Vee = Min, 11 = -18 mA

High-Level Output Current (I0H)

Vee = Min, V IH = 2V, V IL = O.BV
VOH = 2.4V
V OH = 5.5V

40
100

Vee= Min, V IH = 2V, V IL = 0.8V,
IOL = Max

0.45

Low-Level Output Voltage (VoLl

DM54S206
DM74S206

UNITS

0.5

JJA
I1A
V

Vee = Max, VI = 5.5V

1

mA

High-Level Input Current (IIH)

Vee = Max, VI = 2.7V

25

'JJA

Low-Level Input Current (lId

Vee = Max, VI = 0.5V

-250

JJA

Supply Current (led

Vee = Max, Note 2

130

mA

Input Current at Maximum Input Voltage (II)

:2-15

70

U)

o
N
en

it

switching characteristics
All typical values are at Vee = 5.0V. T A = 25°C. (Note 2)

:E
C

.......

LIMITS

U)

o

PARAMETER

N

CONDITIONS
MIN

:E

C

UNITS

TYP

MAX

Access Times from Address (tPLH)

38

80

38

60

ns

Access Times from Address (tPHL)

32

80

32

60

ns

21

45

21

35

ns

13

35

13

25

ns

Disable Time from Write Enable (tPLH)

20

50

20

40

ns

Sense-Recovery Time (tSR)

14

50

14

40

ns

o:t

an

DM74S206

DM54S206

en

Disable Time from Memory Enable (tpLH)
Enable Time from Memory Enable (tPHL)

CL = 30 pF. RL = 3000

MIN

TYP

MAX

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device o p e r a t i o n . '

.

Note 2:" Unless otherwise specified minImax limits apply across the --5SoC to +12SoC temperature range for DM54S206 and across the" oOe to
+70·C range for the DM74S20B- All typica.ls are given for VCC = 5.0V and TA = +25·C.
Note 3: All voltage values are with respect to network ground terminal.'
Note 4: ICC is measured with the write enable and memory enable inputs grounded, all other inputs at 4.SV, and the output open.

truth table

ac test circuit

TEST
POINT

INPUTS
FUNCTION

OUTPUT

MEMORY

WRITE

ENABLEt

ENABLE

L

L

H

Read

L

H

Stored Data

Inhibit

H

x

H

Write (Store

FROM

O~J~~_~--.
TEST

Complement
of Data)

aDD

H "' high level. L = lo"Y leltel, X = irrelevant
tFor memory enable: L "' all ME inputs low;
H = one

or more ME mputs high.

Cl includes probe ilnd jig capacitance.

2-16

switching time waveforms
Writot-Cycle

WAIT£-ENABL£ 3V - - -.......

INPUT

...... I

av----+"-~~

OUTPUT VOH----'---'-t7"~~(NOTE" VOL _ _ _ _ _ _J

Aceess 'Enable) Time and Disable Time from Mel'll(l!y Enable

Ace.... Time from Address Inputs

MEE':~~3V~'
INPUTS
1.5V
1.SV-

t

t~,

(NOTEt) BV

OUTPUT VOH
INOTE AI VOL

.

.

15V

.

ADDRESS

~.

(NOTEB) BV---'

_ _ _ _ _ _ ~,

1.5V

,:::-!

...

O.UTPUT ::-----~.5V

l!iV

•

Nat, A:
Note B:
..ott c:
Note D:

3V~

INPUTS

}!(1.5V

~ ~:-F-=-

Waveform thown if; for the outpp' with internal t;:umlitions such that ttt. otItpvt is low except when disabled.
When measuriDf delay times fnNA i1hIress ipputs. the lRtmory'flllllte iltJluu 1ft low nd ttte wfite.. ~bIe illPIII is high.
WheA measuring delay times from memory-enaltle inputs. ttle Iddms_ts art steady_II and the writHolbie inpat is high.
Input waveforms are supplied by pilsegeneratorsltningtbe foIIowingclllulmristi&l: t, ... 2.5 liS. "~2.5 RI, PRR·.;" 1 MHz. lid louT '" 50!!.

2·17

y.Jv--

Bipolar RAMs

DM54S289/DM74S289 64-bit random access memories
with open-collector outputs
general description
These 64-bit active-element memories are monolithic
Schottky-clamped transistor-transistor logic (TTL)
arrays organiled as 16 words of four-bits each. They are
fully decoded and feature a chip-enable input to simplify
decoding' required to aChieve the desired system organization, The memories feature PNP input transistors that
reduce the low level input current' requirement to a
maximum of ~.25 mAo only one-eighth that of a
DM54S/DM74S standard load factor. The chip-enable
circuitry is implemented with minimal delay times to
compensate for added system decoding.

The. fast access time of the DM54S289 makes it particularly attractive for implementinll high-performance
memory functions requiring access times on the order
of 25 ns. The unique functional capability of' the
DM54S289 outputs being at a high during writing
combined with the data inputs being inhibited during
reading means that both data inputs I!nd outputs can be
connected to the data lines of a bus-organiled system
without the need for interfaCe circuits.

features
• Schottky-clamped for high·speed applications:
AccesS from chip-enable
12 ns typ
Access from address inputs
25 ns typ
• Open collector outputs for controlled·impedance
bus lines
• DM54S189/DM74S189 are functionally equivalent.
but have TRI-STATE@ outputs
• DM54S289 is guaranteed for operation over the full
military temperature range of -55°C to +125°C
• Compatible with most TTL and DTL logic circui~s
• Chip-enable input simplifies system decoding
• Compatible with Intel 3101A in most applications

Write Cycle: The complement of the information at
the data input is written into the selected location
when both the chip-enable input and the read/write
input are low. While the read/write input is low. the
outputs are in the high,logic level ("OFF").
Read Cycle: The stored information (complement .of
information applied at the data inputs during the write
cycle) is available at the outputs when the read/write
input is high and the chip-enable is low. When the chipenable input is high. the outputs are high ("OFF").

connection

diagra~

truth table

Dual-In-Line ""__
DATA

SELECTfNPm

vTCC
16

••

o·
15

OUTPUT

INPUT

OUTPUT

4

Y4

3

V3

13

14

DATA

IffPUT

11

"

10

INPUTS
FUNCTION

CHIP
ENABLE

READI
WRITE

OUTPUT

Write

L

L

H

L

H

Stored Data

H

X

H

(S,ore Complement ~f Da'a)
Read
Inhibit
H

=High Level

L = Low Level
SUECT CHIP
INPUT A ENABLE

READI
WRITE

DATA OUTPUT
INPUT.
VI

I

DATA
INPUT

OUTPUT
Y2

X

Z

TOPIIIEW

Order Number DM!i4S288J Dr DM74S288J
See Package 10
Order Number DM74S289N
See Package 15

2-18

=-=

Don't Care

7.0V
5.5V
5.5V
-es"C to +15O"C
300"C

Supply Voltage, VCC
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)

c

operating conditions

absolute maximum ratings

Supply Voltage (VCC)
DM54S2S9
DM74S2S9
Tempereture (TA)
DM54S289
DM74S2B9

MIN

MAX

UNITS

4.5
4.75

5.5
5.25

V
V

-55
0

+125
+70

·c
·c

s:UI
.po

en

N
00
CD

.......
C

s:
~

electrical characteristics

en
N

over recommended operating free·air temperature range

CD
CD

(unless otherwise noted) (Notes 2 and 3)
PARAMETER
V IH

High Level Input Voltage

VIL

Low Level Input Voltage

IOH

High Level Output Current

CONDITIONS

TVP

MAX

V

Low Level Output Voltage

I

M'
In

Vee = Min,

I

V OH =2.4V
V OH =S.SV

10L

= 16 mA

I

I

UNITS
V

2

cc;:;:

VOL

MIN

DM54S289
DM74S289

0.8

V

40
100

J.lA

0.5
0.45

V

IIH

High Level I nput Current

Vee = Max. V, = 2.7.

25

J.lA

II

High Level Input Current at Maximum Voltage

Vee = Max, V, = 5.5V

1.0

mA

IlL

Low Level I nput Current

Vee = Max. V, = 0.45V

Ice

Supply Current

Vee = Max (Note 4)

VIC

Input Clamp Voltage

Vee = Min,l, = -18 mA

switching characteristics

-250

J.lA

105

mA

-1.2

V

75

over recommended operating ranges of T A and V CC

(unless otherwise noted)

PARAMETER

CONDITIONS

DM54S289
MIN

Access Times, From

tAA

DM74S289

TYP(1)

MAX

25

UNITS

TVP(1)

MAX

50

25

35

ns

12

25

12

17

ns

22

40

22

35

ns

12

25

12

17

ns

MIN

Address
teHL

Enable Time From

Chip Enable
twHL
teLH

Enable Time From

Sense Recoverv Time

Read/Write

From Reacl/Write

CL = 30 pF, RL1 = 300n,
RL2 = 600n, (Figure 1)

Disable Time From

Chip Enable

twp

Width of Write Enable Pulse (ReadlWrite Low)

25

25

tASW

Set-Up Time (Figure 1)

0

0

Address to ReadlWrite

tosw

Data to ReadIWrite

25

25

tcsw

Chip-Enable to

0

0

Address From ReadlWrite

0

0

tDHW

Data From ReadlWrite

0

0

tCHW

Chip-Enable From

0

0

ns

n.

Read/VVrite

tAHW

Hold Time (Figure 1)

ns

ReadlWrite

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature RangeW they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the -5s"C to +125°C temperature range for the DM54S289 and across the o"C to
+7o"C range for the DM74S289. All typicals are given for VCC = 5.0V and TA = 2s"C.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All

values shown as max or min on absolute value basis.
Note 4: ICC is measured with all inputs grounded, and the outputs open.

2·19

en
co

N

switching time waveforms

~
:E
c
......

CHIP ENABLE
IlI'Ul

en

en
co

N

en

'It

an

-_.. "4 -t :t:

3V

3V

'

ADDRESS
INPUTS

1.5Y

~$

WAVEFORM 1 YOH

($tENOTE 1)

3V------r---~r---~
DATA
INPUTS

1.5V

UV
Yo,

:E

C

3V

Enable and Disable Time From Chip Enable

ADDRESS

INPUTS

CHIP·ENABLE
INPUT

3V~'_ _ _ _ - - - " "

I.OYEZ) OV _ _ J '

'1.5V.

.

t~::j
OUTPUT YOH

--------------~.V

Vo, ________________

~~·

{::,.5V
.
"- ____ _

READ/WAITE
INPUT

... , _

/t .

WAV~=g~~,~

V.

______________J_

,v ----------"
OV--------------~----------'

"'H'~

VOH--------------------~~----~-----

________________....J/'-SV

,1.5V

Yo,

Access Time From Address Inputs

Write Cycle

FIGURE 1

Note 1: Waveform 1 is for the output with internal conditions such that the output is low except when disabled.
Note 2: When measuring delav times from address inputs, the chip enable input is low and the read/write input is high.
Note 3: When measuring delay times from chip enable input, the address inputs are steady state and the read/write input is high.
Note 4: Input waveforms are supplied bV pulse generators having the following characteristic.: tr $. 2.5 ns, tf $. 2.5 ns, PRR $. 1 MHz and
ZOUT"'50.ll.

block diagram

·_·r
INPUTS

C

ac test circuit

15

,.

ADDRESS
BUFFERS

64-81T MEMORY
MATRIX
ORGANIZED
16K4

1 OF 16
DECODERS

t3

D

CHIP ENABLE (fEl
REAOIWRITE (RtWI

11

.V1

V2

V3

.

V4

OUTPUTS

2-20

c

Bipolar RAMs

~

~

CJ1

rn

en

00

........

NAnONAL

DM75S68/DM85S68 64-bit (16 x 4) edge triggered register

C
~

general description

features

CJ1

The DM75S68/DM85S68 is an addressable" D" register
file. Any of its 16 four·bit words may be asynchronously
read or may be written into on the next clock transition.
An input terminal is provided to enable or disable the
synchronous writing of the input data into the location
specified by the address terminals. An output disable
terminal operates only as a TRI·STATE® output control
terminal. The addressable register data may be latched at
the outputs and retained as long as the output store
terminal is held in a low state. This memory storage
condition is independent of the state of the output
disable terminal.

•

On chip output register

•

Edge triggered write

•

High speed

•

TRI·STATE output

00

rn

en

00

30 ns typ

• Optimized for register stack applications
•. Typical power dissipation

All input terminals are high impedance at all times, and
all outputs have low impedance active drive logic states
and the high impedance TRI-STATE condition.

•

350mW

18-pin package

logic and connection diagrams
(WRITE CLOCK INPUT)

([lATA INPUTSl

CLK

03

14

IWRIUUIIABLE)

15

'"

AO~

A1~
A/~
AJ~

as

~
~

Dual-In-line Package
V"

03

"

.,

ClK

as

00

"

10

16.4 MEMOAY CEtL ARRAV

~
02

13

01

AO

.2

Al

01

TOPVIEW

(OUTPUT
ST(lAEl

Order Number DM75S68D
or DM85S680
See Package 4

Order Number DM85S68N
See Package 16

"

OOO-~)~'---+-~------~-+~----------~

__________~

!OUTPUT
DISA8lE)

jOUTI'UTSI

2·21

02

'NO

absolute maximum ratings
Supply Voltage
I,put Voltage
Output Voltage

Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)

operating conditions

(Note 1)

7.0V
5.5V
5.5V
-65°C to +150°C
300°C

Supply Voltage, VCC
DM85S68
DM75S68
Temperature, T A
DM85S68
DM75S68

MIN

MAX

UNITS

4.75
4.5

5.25
5.5

V
V

0
-55

°c
°c

70
+125

electrical characteristics
over recommended operating free-air temperature range (unless otherwise noted) (Notes 2 and 3)
PARAMETER
V'H

High Level Input Voltage

V'L

Low Level Input Voltage

VOH

High Level Output Voltage

VOL

Low Level Output Voltage

I'H

LIMITS

CONDITIONS

MIN

TYP

MAX

UNITS

2

V
0.8

.

II OH =-2.0mA, DM75S68
Vee =Mon 10H = -5.2 rnA, DM85S68
Vee::; Min.

High Level I "put Current

Vee

IOL

I

= 16 rnA

I

2.4

V

DM75S68

0.5

DM85S68

0.45

= Max,1 Clock Input

50

I

V'H = 2.4V All Others
I,

High Level Input Current at Maximum Voltage

Vee = Max, V'H = 5.5V

I,"

Low Level I nput Current

Vee

==

Max.I' Clock

V'L = 0.5V

V

25

Input

I All Others

V
p.A

1.0

rnA

-500
-250

p.A
p.A

-55

rnA

los

Short Circuit Output Current(4)

Vee = Max, VOL = OV

Icc

Supply Current

Vee::; Max

V,e

Input Clamp Voltage

Vee::; Min,IIN == -18 rnA

-1.2

V

loz

TRI·STATE Output Current

I V o=2.4V
Vee = Max I Vo = 0.5V

+40
-40

p.A

switching characteristics

-20
70 .

over recommended operating range of

TA

MIN

rnA

and Vee (un)ess otherwise noted)

DM75S68
PARAMETER

100

DM85S68

TYP

MAX

MIN

TYP

MAX

UNITS

tZH

Output Enable to High Level

20

40

20

35

ns

tZl

Output Enable to low Level

14

30

14

24

ns

tHZ

Output Disable Time From High Level

10

18

10

15

ns

tlZ

Output Disable Time From Low Level

12

22

12

18

tAA

Access Time

Address to Output

30

55

30

40

tOSA

Output Store to Output

teA

Clock to Output

20
25

35
50

20
25

30
40

Address to Clock

25

Data to Clock
Address to Output Store
Write Enable Set-Up Time
Store Before Write

15
40
10
15

tAHOS

Address From Clock
Data From Clock
Address From Output Store

20
10

tWEHC

Write Enable Hold Time

20

tAse

Set-Up Time

tose
tASOS

tWESC

tossc
tAHC
tOHC

Hold Time

5
5

15

15

5

15
5
0

5
30
5
10

0
15

5
5

10
15

5

0

5

a

5

15

5

ns
ns

ns

0
0

5

ns

Note 1: "Absolute Maximum Ratings" afe those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the -5S"C to +12SoC temperature range for the DM75S68 and across the
0° C to +70° C range for the DM85S68. All typicals are given for V CC = 5.0V and T A = 25° C,
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted.
All values shown as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.

2-22

o

typical applications
The DM85568 can enhance the dynamic performance of
a TTL processor, since it may safelY operate using single
phase clocking instead of the multi phase clocking systems
being used currently. This simple feature not only enhances the system's dynamic performance, since multi·
pie levels of registers need not be activated, but also
reduces component count by elimination· of one set of
buffer registers. For example, note the simplicity of
registerfile/ALU loop shown in Figure 1.

In a four-bit slice with lero delay within the arithmetic·
logic ullit, a level·triggered memory with buffering to
prevent logic oscillation requires abOut 80 ns to make
the loop whereas the DM75S68 does it in 35 ns. With a
30 ns delay in the ALU, the two compared system
speeds are 110 ns and 65 ns, respectively.

.CP

-+---------'
-+------_----....

NW -+-----------~I_t
O.DD-+---------------~~r,
A3
DATA
OUTPUT

RJ
DATA
INPUTS

AD
RO·
BAUl

DS~--....I
DD~---+.J

WORD 8
ADDRESSES

1'11----...

BADO

OJ
Vee

-+-".,..,.,.-.,

DATA
,OUTPUT

8D

A-O
AJ

AD

5~H

AlU

DM14181

51

FUNCTION

SElECT INPUTS

52

Feature;
eelpandalr!e
eMinimum PICkage CDunt
.~ lIS cycle Ityp)

53

CON

FIGURE 1. 4·Bit Ragister ALU

truth table
00
0
X
0
1
1

WE elK

X
0
X
X
X

X

S
X
X
X

o

s:
CD
CD

AADfl

A'DD

00

c.n

AA03

INPUTS

en

......

oQ')

WORD A
ADDRESSES

CONTROL

~en

Os

MODE

0
X
1
0
1

Output Store
Write Data
Read Data
Output Store
Output Disable

OUTPUTS

2·23

Data From last Addressed Location
Dependent on State of 00 and OS
Data Stored in Addressed location
High Impedance State
High Impedance State

00

~

ac test circuit and sWitching time wavefOrms

Ln
00

S.IV

...

:E
Q

......
00
CD

CL

'"

5.0 pF hlr 1Hz_ tLZ

CL = 30 pFfor ..1athm
CL indad. probe Ind iii cap.cil..ee
All diodes are 1N3D&4

U)

In

!iQ

Read Cycle

Write Cycle

A.~::: ~----------

.sv

.---- I

-----·~'""'----Ir------·
______

.UTPUTS _ _ _ _ _ _ ~j'f..,,

=- " '

FIGURE 4. Address to Output Access Time
OUTPUT
STORE

A~:~~:

1 !iV

__ J

WHiff:
CLOCK

__ -----

1 511

I_,~",,_I"-

OUTPUT
STOAE

-----:'

FIGURE 2. Clock Set·Up and Hold Time
'FIGURE 5. Output Store Access, Set,Up and Hold Time

-;:x----------.-

1.•

J
I~~: ____
t.5V

y--h-'-+:,,..;.-+-....~~

V~--~'FJ
WRITE
CLOCK

OUTPUl1

OlfTpUT

i
. LIcA~,1,--

vOH--I-::!'::'!

••5v

Uy--I--ii-~-+-...t:.+-=;:

___________1.5V
J~
FiGURE 3. Clock to Output A~

FIGURE 6. Output Disable and Enable Time

Note: Input waveform~ supplied by pulse generator having the following characteristics: V = 3.0V, tR
PRR ~ '1.0.MHz and ZOUT = 50M

2·24

~

2.5 ns,

o

~

Bipolar RAMs

s:
-.J

en

CD
CD

........

o

NAliONAL

s:CO

OM7599/0M8599 TRI-STATETM
64-bit random-access read/write memory

en

CD
CD

general description
resistors. All memories except one are gated into
the high-impedance While the one selected memory exhibits the normally totem-pole low impedance output characteristics of TTL.

The DM7599/DM8599 is a fully decoded 64-bit
RAM organized as 16 4-bit words. The memory
is addressed by applying a binary number to the
four Address inputs. After addressing, information
may be either written into or read from the
memory. To write, both the Memory Enable and
the Write Enable inputs must be in the logical "0"
state. Information applied to the four Write inputs
will then be written into the addressed location.
To read information from the memory the Mem·
ory Enable input must be in the logical "0" state
and the Write Enable input in the logical "1 "5tate.
Information will be read as the complement of
what was written into the memory. When the
Memory Enable input is in the logical "1" state,
the outputs will go to the high-impedance state.
This allows up to 128 memories to be connected
to a common bus-line without the use of pull-up

features
•
•
•
•

Series 54/74 compatible
Same pin-out as SN5489/SN7489
Organized as 16 4-bit words
Expandable to 2048 4-bit words without additional resistors (DM8599 only)
20 ns
• Typical access from chip enable
28 ns
• Typical access time
400mW
• Typical power dissipation

block diagram

ADDRESS
INPUTS

S,

SENSE
OUTPUTS

DATA

~

INPlJT$

"

connection diagram

truth table

Dual-In-Line Package

Order Number DM7599J
or DM8599J
See Package 10
Order Number DMB599N
See Pack.age 15

2-25

MEMORY
ENABLE

WRITE
ENABLE

OPERATION

OUTPUTS

0
0

0

Write

1

Read

1

X

Hold

Hi-Z State
Complement of Data
Stored in Memory
Hi-Z State

en
en

It)

absolute maximum ratings

(Note 1)

CX)

:E
c
......
en
en
It)

.....
~

Supply Voltage
Input Voltage

electrical characteristics

c

Storage Temperature Range
Operating Temperature Range

7V

S.SV
S.SV

Output Voltage
Time. that two bus-connected devices may be in
opposite low impedance states simultaneously

Indefinite

-5SoC to +12SoC
O°C to +70°C

Lead Temperature (Soldering, 10 sec)

300·C

(Note 2)

PARAMETER

CONDITIONS
DM7599

DM8599-

4.5V
Vcc =4.75V

Logical "0" Input Voltage

DM7599
DM8599

Vee == 4.5V
Vee - 4.7SV

Logical "1" Output Voltage

DM7599
DM8599

Vee'= 4.5V
Vee - 4.7SV

Logical "0" Output Voltage

DM7599
DM8599

Vee - 4.7SV

Third State Output Current

DM7599
OM8599

Vee == 5.5V
Vee -.- S.25V

Logical "1" Input Current

DM7599
DM8599

Logical "1" Input Voltage

-6SQ C to +l50°C

DM7599
DM8599

Vee

MIN

-==

MAX

TYP

UNITS
V

2.0
0.8

I

'0

I '0

Vcc~4.5V

~ -2 mA

2.4
2.4

5.2mA

-

V
V
0.4

10 == 12 mA

IV

V

V

O.4V
2.4V

±40
±40

"A

Vee = 5.5V
Vee - 5.2SV

VIN ""' 2.4V

40

"A

DM7599
DM8599

Vee"" 5.5V
Vee ,- 5.25V

VIN

1

mA

Logical "0" Input Current.

DM7599
DM8599

Vee == 5.5V
Vee'" 5.25V

VIN "" O.4V

-1.6

mA

Output Short Circuit Current
(Note 3)

DM7599
DM8599

Vee"'" 5.5V
Vee '- 5.25V

Supply Current

DM7599
DM8599

Vee
Vee

Input Clamp Voltage

DM7599
DM8599

Vee - 4.75V

Q

=

I Va

-=

5.5V

-30

=: 5.SV

80

All Inputs at GNO

5.25V

Vee"" 4.5V

-70

mA

120

mA

-1.5

IIN"'-12mA

V
!

switching characteristics, (Over recommended operating ranges of Vee
PARAMETER

DM7599

CONDITIONS
MIN

and T A)
DM8599

MAX

27

70

27

50

ns

28

70

28

50

ns

Ru = 400n,
A L2 "" 1.0 kn,

16

45

16

30

ns

C L =50pF

20

40

20

35

ns

Sense Recovery Time From Write

20

40

20

35

ns

Enable

35

65

35

55

ns

10

30

10

25

ns

14

35

14

30

ns

tplH

MIN

TYP

UNITS

TYP

MAX

Access Time From Address
tPHl
tZH
tZL
tZH
tZL
'HZ

Enable Time From Memory
Enable

All "" 400n,
Disable Time From Memory Enable

'LZ
tSETU~

R L2

CL
Setup Time

=

:::;;

1.0k.

5.0 pF

Address ta Write
Enable
Data ta Write
Enable
Memory Enable to

0

~14

0

-14

ns

0

-15

0

-15

ns

0

~10

0

-10

ns

5

~7

5

-7

ns

0

-14

0

-14

ns

0

-·10

0

-10

ns

20

ns

Write Enable
tHOLO

Hold Time

Address From Wri te
Enable
Data From Write
Enable
Memory Enable From
Write Enable

'WP

Write Pulse Width

50

20

Note 1: "Absalute, Maximum Ratings" are those values beyond which the safetY,Of the device cannot
be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the
devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions
for actual device operation.
Note 2: Unless otherwise specified minimax limits apply across the ~550C to +125°C temperature
range for the DM7599 and across the OOC to 700C range for the DM8599. All typic;als ate given
for Vee""' 5.0V and T A '" 25°C.
Note 3: Only one output at a time should be shorted.

2-26

40

c

s:...,

typical performance curves

CJ'I
Delay from Memory Enable to
High Impedance State

Delay from Address to Output

I

40

I

10 I-Vcc" 5.0V+-+-+-+f-f--l

35

~~--l-+--+-~+--l---l

30

60

!

50~+--r-+-'r-+--r-+-1

~ 40 ~~--l-+--+-~-t~ tplH;

>

CJ'I

CD
CD

L

20

~

~30r:t:*=~~~i~-:~
I

C

s:00

vee:::: 5.0V

25

~

V

15 t-- t-- I-tLZ

tpHL

'HZ

ro-

10

20~+-+--f-+--+--l--~~
10~+-+--f-+--+--lr-+-~

-15 -50 -25

0 25

-15 -50 -25 0 25 50 15 100 125

50 15 100 125

TEMPERATURE

rc)

TEMPERATURE rC)

Deley from Memory Enable to
Low Impedance State
40 .--,.--,--r--r-.---,--,--,

Minimum Write Pulse Width

40

Vee:::: 5.0V

Vee = S.OY

35 ~+--r-+--r-+--r-+-1

35

30 ~+--r-+-r-+--r-+-1
~

25

~

20

>

15

25

'"
:;

....... ...-::
'ZL I-'
k- i'ZH

10

30

]
;;:

20

::l

15

iE

'wo i"""'" ~

I- r-

10

OL-L-~~-L~~~-J

-15 -50 -26 0 26 50 15 100 125

-15 -50 -25

0

25

50

15

roo.

125

TEMPERATURE C"C)'

TEMPERATURE ("C)

Delay from Enable to Output
vs load Capacitance

Sense Recovery Time
80

r-"",,--'--r--r-.---,--,--,
Va::::: 5.0V

10 ~+--+-+-~+--r-+-1
50

~+-+--f-+--+--l--+-~

40
30

t~r:t:!=t':Z:L

40 f-I+++IIIfII-++H'IlIff-H-f+HliI

~

e:ejJ

~

'ZH - f - - -

10

3U

.. 20
10

20 ~~~~--r-~~-+-1
~+-+--f-+--+--lr--+-~

~H+tl-Hlt--++lrHfHt-+++1tttlI
~-~nw~tp~HL~1mm:=+++1
~H+tl-Hlt-'pU+j-tt1f1l11--l-+tfHliI

I
-15 -50 -25 0 25 50 15 100 125

10

TEMPERATURE C"C)

50 100

500

CL (pF)

test circuit
r-;:l
I
I

.E.

I
I

$T~l"..ED

...""
.E,

....

STORED

1
I

Note: In atypical application the output of the TRISTATE memories might be wired together and one

tit)

I-t-.....-+~...

I

I

would be switching to the low impedance state at the

"fl I
':" I
I

same time the circuit previausly selected would be
switching back into the high impedance state. The
measurements .of delay versus laad· capacitance were
made under 'conditions which simulate actual .operating
conditions in an application. (See test circuit.)

1
I

I
I
I __ ...JI
I...
o..!

TTL LOAD

Test Circuit for Delay vs Load Capacitance

2-27

CD

CD
......

ac test circuit
Vee

TEST
POINT
fROM

o~;~~~

_ ....--...--1...1-...

TEST

Ru
1.Ok

CL includes probe and jig capacitance.
All diodes are 1 NJ064.

switching time waveforms

3.0V
ADDRESS
INPUT

(SEE NOTE BI

VOH - - ' - - OUTPUT
VO '

-----J

_ _ _- - - - ....

3.0V
MEMORY
ENABLE

3.0V

3.0V

WRITE

MEMORY ENABLE
(SEE NOTE CI

ENABLE
INPUT

OV

OV

"" 1.5V

1.5V

..0;

WAVEFORM 1
(SEE NOTE Al

WAVEFORM 1
(SEE NOTE AI

Vo ,

Vo,
VOH

VOH

WAVEFORM 2
(SEE NOTE AI

WAVEFORM 2

(SEE NOTE Al
~

~1.5V

1.5V

Note A: Waveform 1 is for the output with internal conditions such that the output is low except when disabl.ed. Waveform 2 is for the output with

internal conditions such that the output is high except when disabled.
Note B: When measuring delav times from address inputs, the memory enable input is low and the write enable input is high.
Note C; When measuring delav times from memory enable input, the address inputs are steady-state lind the write enable input i$ high,
Note D; Input waveforms are supplied by pulse generators having the following characteristics: t.:::; 10 ns, tf $10 I1S, PRR S; 1.0 MHz, and ZOUT "" 5(tn.

2-28

~

Bipolar RAMs

NAnONAL

DM86S21 64-bit bipolar high speed RAM (32 x 2 RAM)
general description

features

The DM86S21 is a TTL 64-bit Write-While-Read Random
Access Memory organized in 32 words of 2 bits each.
The DM86S21 "is ideally suited for high speed buffers
and as the memory element in high speed accumulators.

•

Buffered address lines

• On chip latches
• On ch ip decoding

Words are selected through a 5 input decoder when the
Read-Write enable input, CE is at logic "1." Wo and
W, are the write inputs for bit 0 and bit 1 of the word
selected. C is the write control input. When Wx and C
are both at logic "0" data on the 10 and I, data lines
are written into the addressed word. The read function
is enabled when either Wx or C is at logic "1."

• Bit masking control lines
•

Enable control line

• Open collector outputs with 40 mA capability
• Protected inputs
• Very high speeds

An internal latch is on the chip to provide the WriteWhile-Read capability. When the latch control line, I.
is logic "1" and data is being read from the DM86S21,
the latch is effectively bypassed. The data at the output
wiil be that of the addressed word. When L goes from
a logic "1" to logic "0" the outputs are latched and
will remain latched regardless of the state of any other
address or control line. When L goes from "0" to "1"
the outputs unlatch and the outputs will be that of the
present address word.

• Second source to Signetics 82S21

applications
• Scratch pad memory
• Buffer memory
• Accumulator register
• Control store

logic and connection diagrams

Dual-In-line Package
0,

I..

15

14

2

3

12

13

11

10

,

-

1

-

,
A.

,
eE

6
-

)

00

'T'

GND

TOP VIEW

Order Number DM86S21J
See Package 10 .
Order Number DM86S21N
See Package 15

Vee
GND

()

~

= (Hi)
~

(8)

Oenotespill numbers

2-29

25 ns (typ)

.~. ~----------------------------------------------------------------~----------------------~~

N

til

absolute maximum ratings

operating conditions

(Note 1)

CD

CO

~

Q

Supply Voltage
I nput Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)

7.0V
5.5V
5.5V
-65°C to +150°C
300°C

electrical cha racteristics

Supply Voltage, VCC

MAX

4.75

5.25
+70

Temperature, T A O

UNITS
V

°c

(Notes 2 and 3)'

PARAMETER

CONDITIONS

MIN

Logical "1" Input Voltage (V IH )
Logical "1" Input Current (lIH)

MIN

TYP

MAX

V

2.0
Vee

~

Max, V IN

~

25

5.. 5V

0.85

Logical "0" Input Voltage (V IL )

jJ.A
V-

0.45V

-1.6

mA

-18 mA

-1.2

V

40

jJ.A

Logical "0" Input Current (lId

Vee

~

Max, V IN

Input Clamp Voltage (V eo )

Vee

~

Min,

~

Logical "1" Output Current (lOH)

Vee

~

Max, V OUT

Logical "0" Output Voltage (VOL)

Vee

~

Min, lOUT

Supply Current (led

Vee ~ Max

liN ~

UNITS

~

~

5.5V

40 mA

0.45

V

130

mA

Read Access Time Address to
Output (t,)

25

Address Set-up Time (t 2 )

8

ns

15

ns

Data Set·up Time (t3)

20

Address Hold Time (t4)

0

Control or Write Pulse Width (t5)

20

Write Access Time (t6)

10

Latch Address to Address Hold
Time (ts)

15

ns

20

ns

Data Hold Time Earliest (t,o)

5

50

7
15

Delatch Access Time (t9)

ns

ns

25

Address to Latch Set-up Time 1t7)

50

0

ns
ns

25

ns
ns

Note 1: Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the O°C to +70°C range for the OM86S21. All typicals are given for VCC ~ 5.0V
andTA-2!i"C.
.
Note 3; All cur~ents into device pins shown as positive, out of device pins' as negative, all voltages referenc~d to ground unless otherwise noted.
All values shown as max or min on absolute value basis.
.
H

2·30

c

s:

truth table

00

CE

C

Wo

W,

X
0

X
X

1

1

X
X
X

X
X
X

1

1

1

1

0
0

0

0

1

0

0

1

0

0

1

0

1

MODE

L

0

Output Hold

en
en

...

OUTPUTS

N

= "1"

1

Read & Write Disabled

Data from last addressed word when CE
Disabled logic "1"

X
X
0

Read

Data stored in addressed word

Read

Data stored in addressed word

Write Data

0

1

Write Data

Data from last word address when L went from "'"
to "0"
Data being written into'memory

1

X

Write Data into Bit 0 Only

0

X

Write Data into Bit 1 Only

If [= 0: Data from last word address when L
went from "'" to "0"
IfLe 1: Data being written into the sell!cted bit
location and stored in other addressed location

ac test circuit
5.0V

Vee

A'
'50

g

PULSE GENERATOR
DM86S21
A2
6••

Note 1: Pulse generator characteristits: 10% to 90% t, ~ tt = 5 ns,
pulse amplit""= 3V.

Note 2: CL indudes jig and probe capacitances.

switching time waveforms

-JE ----------

A, -_ _
-_-_-_........

1.5V

l=="-IK·;----

"-1--"---1
COAW---'--\1.5V

0, _ _ _ _ _ _ _ _ _ _ _ _ ..J ....._ _ __

FIGURE 1. Read Access Time

.

F

'---

4 -

FIGURE 2. Addre.. Set-up and Hold Time

FIGURE 3. Data Set-up and Hold Time

\I\,,'r-----------.•_

I, _ _ _ _ _ .J

CORW

\

0.

V
_ _ _ _ _ _ _ _ __

.1.5V

=

-----------------,f
1.5V

-~=1~;-----

0, _ _ _ _ _ _ _ _ _

A,

FIGURE 4. Wri,. Access Tim.

1.5V

'-----------

FIGURE 5. Latch Tim••

2-31

,

en
en

....I
CD

CD

:E
Q

Bipolar RAMs

~

NAnoNAL

DM86L99 TRI-STATE@low power 64-bit
random access memory
general description
The DM86L~9 is a fully decoded 64-bit RAM
organized as 16 4-bit words_ The memory is
addressed by applying a binary number to the
four Address inputs_ After addressing, information may be either written into or read from the
memory_ To write, both the Memory Enable
and the Write Enable inputs must be in the logical
"0" state_ Information applied to the four Write
inputs will then be written into the addressed
location. To read information from the memory
the Memory Enable input must be in the logical
"0" state and the Write Enable input in the logical
"1" state. Information will be read as the complement of what was written into the memory.
When the Memory Enable input is in the logical
"1" state, the outputs wi II. go to the highimpedance state. This allows up to 75 memories
to be connected to a common bus-line without

the use of pull-up resistors. All memories except
one are gated into the high-impedance while the
one selected memory exhibits the normally totempole low impedance output characteristics of
TTL.

features
• Series 54U74L compatible
• Same pin-out as SN7489, 3101, MM5501
• Organized as 16 4-bit words
• Expandable to 1200 4-bit words without additional resistors
• Typical access from chip enable
50 ns
80 ns
• Typical access time
• Typical power dissipation
75mW

logic diagram

~--t>-£:::
A, .. ri>o-A'
ADDRESS
INPUTS

~A1

A, ....

r-t>o-A'

~A2

A, ..... ri>o-.,

~A3

DATA
INPUTS

••
••
.3

..
WE

ME

2-32

c
absolute maximum ratingS(Note 1)
Supply Voltage
Input Voltage
Output Voltage

7.0V
5.5V
5.5V
--ils"e to +150"e
Storage Temperature Range
300'e
Lead Temperature (Soldering, 10 seconds)

electrica I cha racteristics (Notes 2 and 3)
PARAMETER

s:CO

operating conditions
MIN

MAX

UNITS

Supply Voltage (Vee)
DM86L99

4.75

5.25

V

Temperature (TA)
OM86L99

0

Vce

TYP

MAX

2cO

Vee"" Min

logical "'" Input Current (lIH)

Vee '= Max, V IN '" 2.4V
Vee:: Max. VIN '" 5.5V

10
100

Logical "0" Input Voltage {V1d

Vee;= Min

0.7

Logical "0" Input Current {lId

Vee = Max, Y'N '" O.3V

Input Clamp Voltage (V eo )

Vee

Logical "1" Output Voltage (VOH)

Vee = Min, lOUT

Output Short Circuit Current (Note 4) (los I

Vee = Max. V OUT = OV

-180

Min, liN"" -12 rnA
-1.0 mA

Logical "O"-Output Voltage (VOL)

Vee = Min, lOUT = 3.2 mA

Supply Current (Icc)

Vee

Third State Output Current

Vee = Max, V OUT = 2.4V
VOUT ""G.4V

Propagation Delay to a Logical "0': From

Vee

~A
~A

V
~A

-1.5

V

-30

mA

2.4

V

-6.0

15

Max

UNITS

V

logical "1" Input Voltage (V,HI

=

"e

+70

LIMITS
MIN

cc

;=

0.4

V

19

mA

±40

~A

2S c c

77

150

ns

Propagation Delay to a Logical" 1" From
AddreS$ to Output (tpd 1 )

Vee = 5.0V, T A = 25°C

51

120

ns

Delay From Memory Enable to High Impedance
State (From Logical "1" Level){t 1H 1

Vec "" 5.0V, T A "",25°C

18

27

ns

Delay From Memory Enable to High Impedance
State (From Logical "0" Level)(toH)

Vee"" 5_0V, TA "" 25°C

37

56

ns

Delay From Memory Enable to Logical "1" Level
(From High Impedance State) (tHl)

Vce "" 5.0V, TA "" 25"C

5Q

30

ns

Delay From Memory Enable to Logical "0" Level
(From High Impedance State)(tHO)

Vee"" S.DV, T A "" 25"C

29

43

ns

Write Enable Pulse Width

Vee"" 5.0V, TA "" 25"C

50

Setup Time, Data Input

Vee'" 5.DV, TA

25°C

0

ns

Hold Time, Data Input

Vee ~ 5.0V, TA • 25"C

0

ns

Setup Time, Address

Vee = 5 . 0V, TA

25"C

0

ns

Hold Time, Address

Vee = 5.0V, TA = 25°C

0

ns

Setup Time, Memory Enable

Vee = S.OV, TA = 2S"C

0

ns

Ho'id Time, Memory Enable

Vee' 5.0V, TA • 25"C

0

Sense Recovery Time From Write Enable '(tSR)

Vee = S.OV, TA = 2S"C

110

165

ns

Disable Time From Write Enable (tEN)

Vee'" 5.0V, T A = 25°C

73

110

ns

=

B.OV, T A

'"

Address to Output (t pdO )

=

=

30

ns

ns

I~otel: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for ';Operating Temperature Rarige" they are not meant to imply that the devices should be operated at these limits. The
table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the O°C to +70°C range. All typicals are given for Vee ~
5.0V and TA =,25°C.
Note 3: All currents into device pins shown as positive. out of device pins as negative. All voltages referenced to ground unless
otherwise noted. All values' st'lown as max or min on abSOlute value basis.
Note 4: Only one output at a time should be shorted.

2-33

reo
eo

= S.OV, TA = 25°C unless otherwise specified.

CONDITIONS

~

en

f)I

en
en
....
co
co

connection diagram

~
Q

Dual·ln-line Package

I I I I

A,

I

A,

s,

0,

s,

0,

11111
I'

I' I' 1 I'

I'

5

.I:

TQPVIEW

Order Number DM86L99J
See Package 10
Order Number DM86L99N
See Package 15
Order Number DM86L99W
See Package 28

truth table

MEMORY
ENABLE

WRITE
ENABLE

OPERATION

a
a

a

Write

1

Read

OUTPUTS
Hi·Z State

Complement of Data
Stored in Memory

1

X

Hold

2-34

Hi-Z State

~

CMOS RAMs

NATIONAL

MM54C89/MM74C89 64-bit TRI-STATE®random access
read/write memory
general description
The MM54C89/MM74C89 is a 16·word by 4·bit
random aCCllss read/write memory. Inputs to the
memory consist of four address lines, four data
input lines, a write' enable line and, a memory
enable line. The four binary address inputs are
decoded internally to select each of the 16 possible
word locations. An internal address register, latches
the address information on the positive to negative
transition of the iiieiTiOrY enable input. The four
TRI·STATE® data output lines working in con·
junction with the memory enable input provides
for easy memory expansion.

address by,'bringing write enable and memory
enable low.
Read Operation: The complement of the' information which was written into the memory is non·
destructively read out at the four outputs. This is
accomplished by selecting the desired address and
bringing memory enable low and write enable
high.
When the device is writing or disabled the output
assumes a TRI·STATE (Hi·z) condition.

features

AddreSf Operation: Address inputs must be stable
!sA prior to the positive to negative transi,tion
of memory enable. It is ,thus not necessary to
hold address information stable for more than
tHA after the memory is, enabled (positive to
negative transition of memory enable).

3.0Vto 15V
Wide supply voltage range
1.0V
Guaranteed noise margin
0.45 Vcc typ
High noise immunity
fan .Jut of 2
Low power TTL
compatibility
driving 74L
• Input address register
• Low power consumption 100 nW/package typ
@V cc =5V
• Fast access ti mOe
130 ns typ at Vcc = 10V
• TRI·STATE output
•
•
•
•

Note: The timing is different than the DM7489 in
that a positive to negative transition of the men;ory
enable must occur for the memory to be selected.
Write Operation: 'Information present at the data
inputs is written into the memory at the selected

logic and connection diagrams
DAT,A.
Di'fA DATA DATA DATA mi DATA
INPUT 1 0iffiUi'"i' I"'UT Z ifii'fiiij'f'Z INPUT 3 DUll'UT 3 INPUT 4

..mii

9n

iiiffiiiii'i

ADDRESS 'IIPUT A 1

EIIA.LE

M!MUIlY ENQtE . 2

@!.ft!
EIIIAILE

,. AGDAEIIllIIIMe

1IIIIT!mm: '

"

DATAI.rUr, 4

D'mlJUTll1JTl 5

'''''".

ADDREII INPUT D

12 lATA I"PUT 4

1r JITIlJlITIIDTc

DATA INPUTl Ii

I' DATA INPUTl

•••

IIiPUlI

• OD:IJDTPI1TJ

Topvnw
IIIPUTt

Ordar Number MM54C89D or
MM1~I!9D

SeaPack_3
Order Number MM14C89N
See Package 15

INPUT.

-,
3·1

absolute maximum ratings
-O.3V to Vee + O.3V

Voltage at Any Pin
Operating Temperature Range

-5S'C to +12S'C

MM54C89
MM74C89

-40°C to +8SoC
-6SoC to +150oC

Storage Temperature 'Range
Package Dissipation

500mW
3.0V to 15V
16V
300'C

Operating Vee Range

Absolute Maximum Vee
Lead Temperature (Soldering, 10 seconds)

dc electrical ch a racteristics
Min/max limits apply across temperature range, unless otherwise rioted.
PARAMETER

CONDITIONS

TYP

MIN

MAX

UNITS

CMOS TO CMOS

Vee = s.nv

Logica''','' Input Voltage (V 1N (1)1

3.5
8.0

vee = lOV
Logica'''O'''nput Voltage (V INID))

Vee = 5.0V
Vee = lOV

logical "'" Output Voltage

Vee = S.nV,lo ;"-10,uA
Vee = 10V, 10 = -lO~A

(V OUTl1 ))

"a.. Output Voltage

1.5
2.0

(VouT.{O')

Vee = 5.0V, 10 = +10",A
Vee =.lOV, 10 =+10J..lA

Logica'''''' Input Current Cl 1N (1I)

Vee

Logical "O"'nput Current (lINtOI)

Vee = 15Y, VIN

= OV

Output Current in High Impedance
State

Vee = 15V, Vo

= 15V

Vee ..,..15V. Vo .... OV

Supply Current lied

Vee = l!?V

Logical

V
V
V
V-

4.5
9.0

V
V0.5
.1.0-

= 15V, VIN = 15V

V
V

1.0

~A

0.005
:.0.005

1.0

~A

0.05

300

0.005
-1.0

-j).005

-1.0

~A

I'A
~A

CMOS/LPTTL INTERFACE

logical"'" Input Voltage

(VIN!l})

Logical "0" Input Voltage (V IN (O))

54C, Vee = 4.5V

Vee - 1.5

74C, Veo = 4.75V

Vee -1.5

V
V

54C, Vee = 4.5V

74C,

V cc .=

0.8
0.8

4.75V

54C, Vee = 4.5V, 10 =-36~A
= 4.75V, 10 = -360pA

logical"'" Output V,oltage
(VOUT(1))

74C, Vee

logical "0" Output Voltage
(VOUTIO»)

54C, Vee = 4.5V, 10 = +360~A
74C, Vee = 4.75V,lo = +360~A

V
V
V
V

2.4
2.4 -

V
V

0.4
0.4

OUTPUT DRIVE (See 54C174C Family Characteristics Data Sheet)
Output Source Current (lsouRce)
(P~Channell

Output Source Current (lsouRee:l
IP·Channel)

Vee = 5.0V, VOUT
TA = 2SoC

Vee = lPV, VOUT ,= OV
TA =25°C
Vee = S.OV, VOUT
TA = 2SoC

Output Sink Current (I SINK )
IN·Channel)

Output Sink Current (I SINK )
IN·Channel)

PARAMETER

Propagation Delay from Memory' Enable
Access Time from Address Input (tace .!

-1.7-5

-3.3

mA

-8,0

-15

mA

1.75

3.6

mA

~.O

16

mA

(TA = 25°C, CL = 50pF, unless otherwise noted,)
TYP

MAX

UNITS

Vee = 5.0V
Vee = 10V

CONDITIONS

270
100

500
220

ns
ns

Vee = 5.0V

350
130

650
280

ns
ns

Vee
Address Input Setup Time

= Vee

Vee"" 10V, VOUT .= Vee
TA = 2SQC

ac electrical characteristics

Itpd)

=OV

MIN

= 10V

Vee;"'lOV

150
60

ns
n.

Address Input Hold Time (tHAI

Vee = 5.0V
Vee = 10V

60
40

ns
ns

Memory Enable Pulse Width (tME)

Vee =-5,OV
Vee = 10V

400
150

250
90

n.
ns

Memory Enable Pulse Width (tM'E)

Vee =5.0V
Vee = 10V

400
150

200
70

ns
ns

(tSA)

Vee = 5.0V

3-2

s:
s:

ac electrical characteristics (con't)
PARAMETER

0l:Io

MIN

CONDITIONS

Write EOaiTe Setup Time ,for a Read
Enable Setup Time for a Write

(tws)

Vee = 5.0V
Vee:;; lOV

Write Enable Pulse Width (twe)

Vee ""- 5.0V, tws" 0

tME

300
100

Vee = 5.0V

Vee'" lOV

Data Input Setup {tso I

Vee = S.OV
Vee = lOV

160
60

UNITS

(')

ns
ns

........

ns
ns
ns
ns

50
25

os
ns

50

os
ns

25

a Logical "'"

Vee

=

5.0V, C L

:=

5.0 pF, RL

=

10k

or Logical "0" to the High Impedance
State from Memory Enable (t IH , t OH )

Vee

=

lOV, C L

=

5.0 pF, RL

=

tOk

Propagation Delay from a Logical "1"
or Lc>gical "0" to the High Impedance
State from Write ~ (tIH. tOHI

Vee" 5.0V, CL " 5.0 pF, RL" 10k
Vee= lOY, C L =5.0pF, Rt: = 10k

85

Propagation Delay from

MAX

'M.

Vee = lOV, tws::O 0
Data Input Hold Time (tHO)

TYP

0
0

Vee = 5.0V
Vee = lOV

ItSA)

Wrlte

U1

180
85

300
120

os
ns

180

300
120

ns
ns

Input Capacity (C IN )

Any I nput (Note 2)

5.0

pF

Output Capacity (C OUT )

Any Output (Note 21 '

6.5

pF

Power Dissipation Capacity (Cpd )

(Note 31

230

pF

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guarar'lteed.
Except for "Operating Range" they are not meant to imply that the devices should be operated at'these limits. The table
of "Electrical Characteristics" provides conditions for actual device operation
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: CpO determines the no load ac power consumption of any CMOS device. For complete explanation see 54C/74C
Family Characteristics application note, AN-gO.

truth table
ME

WE

L

L

Write

TRI·STATE

OPERATION

CONDiTiON OF OUTPUTS

L

H

H

L

Read
Inhibit, Storage

TRI-STATE

H

H

Inhibit, Storage

TRI·STATE

ac test circuits

switching time waveforms

3-3

Cornplement of Selected Word

CO

(g

s:
s:.....
0l:Io

0

CO

(g

switching time waveforms (con't)
Read Cycle

Write Cycle

v~

iim1iY
ENAitE

v« _ _ _ _ _--...

v.~

ADDRESS

ADDRESS
IIilPUT

INPUT

v~----~--,

v~

E:~r~

PiIm
EiiiU

I!lTI

iiiii

"'----------------------~,----------

.--------------TRI-STATE CONDITION

DATA

v~---------~

'OPUT

Read Modify Write Cycle

=

v~-----t~---~

'~.-----'

~:~--7QL·
,.
DATA

NOTE: t. = 110 ..
it-IOns

...

~

CMOS RAMs

s::
~~

n
N

g

NA110NAL

......

s::
s::

MM54C200/MM74C200 256-bit TRI-STATE®
random access read/write memory

~

general description
The MM54C200/MM74C200 is a 256-bit random
access read/write memory_ Inputs consist of eight
address lines, a data input line, a write. enable
line, and three chip enables_ The eight binary
address inputs are de~oded internally to select
each of the 256 locations_ An internal address
register, latches and address information on the
positive to negative edge of CE 3 . The TRISTATE data output line working in conjunction
with CE, or CE 2 inputs provides for easy memory
expansion.

Read Operation: The data is. read out by selecting
the proper address and bringing CE3 low and write
enable high, Holding CE, or CE 2 or CE 3 at a
high level forces the output into TRI-STATE.
When used in bus organized systems, CE" or CE 2 ,
a TRI-STATE control, .provides for fast access
times by not totally disabling the chip.

Address Operation: Address inputs must be stable
tSA prior to the positive to negative transition of
CE 3 . It is thus not necessary to hold address
informatio·n stable for more than tHA after the
memory is enabled (positive to negative transition).

features

Write Operation: Data is written into the memory
with CE 3 low and write enable low. The state of
CE, or CE 2 has no effect on the write cycle. The
output assumes TRI-STATE with write enable low.

•
•
•
•

Wide supply voltage range
3.0V to 15V
Guaranteed noise margin
1.0V
High noise immunity
0.45 Vee typ
TTL compatibility
fan out of 1 driving
standard TTL
500 nWtyp
• Low power
• Internal address register

Note: The timing is different than the DM74200
in that ·a positive to negative transition of the
memory enable must occur for the memory to be
selected.

logic and connection diagrams
ADDRESS
INPUTD

TRI-STATE

E:~~·

__ ______________t-__
~

ADDRESS
IM'UTC

ADDRESS
INPUT I

ADDRESS
IIliPUTA

ADDRESS 1
INPUT A

t-~~--~-r~L--1~~~~--L-~

DA~:---+------~------r-t---+I

X·DECODER

ADDfUiss

CEI

14 ADDRESS

•

13 DATA IN

INPUTe
INPUTH

,

5

DUT

12 WRITE
ENABLE
11 ADDRiSS
INPUTS

ADDRESS 1

10 ADDRESS

c;E3

CE,--------,=,:::::::3

15 ADDRESS

3

INPUTB

CE2

CEz- - - - - - '

16 Vee

.2

DATA

INPUTF
g ADDRESS
INPUTE

INPUlD
,ND

25&·8IT
MEMORY ARRAY

TOP VIEW

Order Numb ... MM54C200D
or. MM74C200D

Se. Packaga3
Order Number MM74C200N

Sa. Package 15

3-5

n
N
o
o

absolute maximum ratings

(Note 1)

Voltage at Any Pin
Operating Temperature Range
MM54C200
MM74C200
Storage Temperature Range·.
Package Dissipation
Operating Vee Range
Absolute Maximum Vee
Leaq Temperature (Soldering, 10 seconds)

-0.3V to Vee +0.3V
-55°C to +125°C
-40°C to +85°C
-65°C to +150°C
500mW
3.0V to 15V
16V
300°C

de electrical characteristics
Minimax limits apply across temperature range, unless otherwise noted:

I

PARAMETER

CONDITIONS

I

I

MIN

TYP

I

MAX

I

UNITS

CMOS TO CMOS
Logical "1," Input Volt;,ge (V1i'.I(lIl

3.5
8.0

Vee'" S.OV

V~c '" lOV
Logical "0" Input Voltage (V IN

(OIl

V
V

Vee:: S.OV

Vee" lOV
Logical "'" Output Voltage (VouTlul

Vee:: S.DV,

10:: -lOJ,JA
lOJ..lA

Vee =- lOV,

10 '"

Vee -= S.OV,
Vee'" lOY.

10:: +lO,uA

Logical ''1'' Input Current (1INI1))

Vee = 15V,

VIN

Logical "0" hiput Current (lINIOl)

Vee'" 15V

VIN '" OV

Supply Current Oed

Vcc:: 15V

Logical "0" Output Voltage (VoUT!OlI

..

CMOS/LPTTL

V
V

1.5
2.0
4.5
9.0

V
V

10 =+1OJ..IA

=- lSV

0.005
-1.0

0.5
1.0

V

1.0

VA

V

-0.005

VA

0.10

"A

INTERFAC~

logical ''1'' Input Voltage {V 1N (1)1

54C, Vee = 4.5V
14C, Vee = 4.75V

Logical "0" Input Voltage (V 1NI0l )

54C, Vee = 4.SV
14C, Vee = 4.75V

Logical "1" Output Voltage (V ouTm )

54t. Vee'" 4.SV. .1 0 = -1.6 mA
74C. Vee = 4.75V, 10 "" -1.6 mA

Logical "0" Output Voltage

(VOUTiOj)

V
V

Vee - 1.5
Vee

1.5
0.8
0.8

V

V
V

2.'
2.'

V

54C. Vee'" 4.SV.

V

0.4
0.'

10 = 1.6mA
74C, Vee = 4.75V. 10 = 1.6 rnA

V

OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheetl

Output Source Current

(ISOURCE)

Vee = 5.0V.

=2S(lC

IP·Channel)

TA

Output Source Current (lSOURCE)

Vee = lOY.

(P-Channel)

TA = 25°C

Output Sink Current (lStNK) IN-Channel)

Vee:: 5.0V.
TA

Output Sink Current

(lSINK

I IN·Channell

=2SoC

Vee = lOV,
TA = 25"C,

ac electrical characteristics
PARAMETER
A;ccess Time From Address hAec I
Propagation Delay From

CE3

(tPd l

Propagation Delay From eEl or CE 2
(tp Ce1)

. Address Setup Time ItSA )
Address Hold Time (tHAI

= OV

-4.0

-6.0

rnA

VOUT =, OV

-16.0

-25

rnA

V OUT

V OUT = Vee

5.0

V OUT = Vee

20.0

8.0

rnA

30

rnA

T A = 25°C, C L = 50 pF, unless otherwise specified.
TYP

MAX

Vee = 5.0V
Vee = 10V

CONDITIONS

MIN

450
200

900
'0.0

ns
ns

V~c = 5.0V
Vee = lOV

360
120

700
300

ns
ns

Vcc=50V
Vee;:: lOV

250
85

500

ns
ns

200

UNITS

Vee'" 5.0V
Vee;:: 10V.

200
100

80
30

ns
ns

Vee;:: 5.0V
Vee:= lOV

50
25

15
5

ns
ns

3·6

s:
s:UI

ac electrical characteristics (con't)

~

(')
MIN

CONDITIONS

PARAMETER

Writ~ Enable Pulse Width (tW'E I

TVP

Vee = lOV

300
150

160
70

CEa Pulse Widths (teE)

Vee -= 5.0V
Vee = lOV

400
160

200

Vee':: 5.0V

MAX

UNITS

N

o

o
.....

so

ns
ns

Input Capacity (C 1N I

Any Input (Note 21

5.0

pF

Output Capacity in TRI-STATE (GOUT J

(Note 2)

9.0

pF

Power Di5sipation Capacity (Cp,dJ

(Note 3)

400

pF

s:
s:....
~

(')

N

o

Noto 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Range" they are not meant to imply that the devices should be operated at these ~imits. The table of "Electrical
Characteristics" prav,ides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Cpd determines the no load ac power consumption of any CMOS device. For complete explanation see 54C/74C
Family Characteristics application note. AN-90.

switching time waveforms
Read and Write Cycles Using CE3 (CE1 = CEZ;' logic 01
r-------~~-------------------v~

_________________ ,v
I r--------...,...---v~

ADDRESS
INPUT

'-------_____ ,v
~---v~

DATA

j

"

om
our

.v

....

'~. -------------Lv~
TRI-sTATl

-----,
TRI.sTATE

OV

Read and Write Cycle. Using CE3 and CEl (or CEZI

\
1'-------1·-- - - - ' v

/,-------v~
r-------~----------------v~

'---------------.v
ADDRESS
INPUT

~;:±::J~~=---+-------------~~i;:t:~~~---------v~

'----------.v

4- \

DATA

I.

om
our

-

i:

V-------TaIST~E------------v~

_ _ _ _ _ _ _ _ _ ~_

TRI-sTATE

Note: Used fOf fast aecess time in busH systems.

3-7

OV

o

~

CMOS RAMs

NAll0NAL

MM54C910/MM74C910 256-bit TRI-STATE®
random access read/write memory
general description
The MM54C910/MM74C910 is a 64 word by 4 bit
random access memory. Inputs consist of six address
lines, four data input lines, a write enable, and a
memory enable line. The six address lines are internally
decoded to select one of 64 word locations. An internal
address register, latches the address information on the
positive to negative transition of memory enable. The
TRI·STATE outputs allow for easy memory expansion.

Read Operation: Data is nondestructively read from a
memory location by an address operation with write
enable held high.

Address Operation: Address inputs must be stable (tSA)
prior to the positive to negative transition of memory
enable, and (tHA) after the positive to negative transition
of memory enable. The address register holds the
information and stable address inputs are not needed at
any other time.

features

Outputs are in the TRI·STATE (Hi·Z) condition when
the device is writing or disabled.

• Supply voltage range
• High noise immunity
• TTL compatible fan out
• Input address register
• Low power consumption

Write Operation: Data is written into memory at the
selected address if write enable goes low while memory
enable is low. Write enable must be held low for tiNE
and data must remain stable tH D after write enable
returns high.

• Fast access time
• TRI·STATE outputs
• High voltage inputs

3V to 5.5V
0.45 Vee typ

1 TTL load
250 nW/package typ
(ch ip enabled or disabled)
250 ns typ at 5V

logic and connection diagrams
DIN'

OOUT\ D1N2

DOUT2 DINl

ooun

DIN4

Input Protecti.on

D.DUTII

v"

Dual·ln·Line Package
WRi'fEPmiOii'V
Vc.;

ODUTJ

OlN3

OlN4 ODUT4ffi"fIU fiijp;j[f

AC

"

Doun
TOP VIEW

Order Number MM54C910D
or MM74C910D

See Package 4
Order Number MM74C910N
Sea Packa!!,! 16

3·8

absolute maximum ratings (Note 1)

operating conditions

Voltage At Any Output Pin
·..Q.3V to VCC +O.3V
Voltage At Any Input Pin
-.ccess Time fiom Address

tpo

Propagation Delay from

tSA

Address Input Set· Up Time

140

tHA

Address I nput Hold Time

20

10

ns

tME

Memory Enable Pulse Width

200

100

ns

tME

Memory Enable Pulse Width

400

200

ns

tso

D.•t. Input Set·Up Time

0

tHO

Da~a

30

15

!WE

Write Enable Pulse Width

140

70

t lH , tOH

Delay to TRI·STATE (Note 4)

ME

Input Hold Time

70

ns
ns

ns

100

ns
ns
200

ns

CAPACITANCE
C'N

Input Capacity
Any I nput (Note 2)

COUT

Output Capacity

Cpo

Power Dissipation Capacity (Note 3)

Any Output (Note 2)

3·9

5

pF

g

pF

350

pF

D

....

0

en
0

i::E

ac electrical characteristics (con't)
C L = 50 pF
MM54C910

=-5SoC to +12SoC
Vee =4.5V to 5.5V

TA

.......

PARAMETER

....

0

MIN

C7)

0

od'

an

::E
::E

MAX

MM74C910
T A = -40'C to +8S'C
Vee = 4.75V to 5.25V
MIN

UNITS

MAX

860

700

660

540

ns

tAcc

Access Time from Address

tpD1' tpDo

Propagation Delay from

tSA

Address Input Set· Up Time

200

tHA

Address Input Hold Time

tME

Memory Enable Pulse Width

tME

Memory Enable Pulse Width

750

600

ns

tSD

Data Input Set·Up Time

0

0

ns
ns

ME

ns

160

ns

20

20

ns

280

260

ns

tHD

Data Input Hold Time

50

50

tWE

Write Enable Pulse Width

200

180

t1H. tOH

Delay to TRI·STATE (Note 4)

ns

200

ns

200

Note 1: "Absolute Maximum Ratings" are .those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"

provides conditions for actual device operation.

'

Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Cpd determines the no load ae po~er consumption for any CMOS device. For complete explanation see 54C/74C Family Characteristics

application note, AN·90.

Note 4; See ae test circuit for t1 H. tOH.

truth table

typical performance characteristics
Typical Access,Time vs Ambient
Temperature
450

I
I

400
350

~ 300

...~

~

"

5V

250

ME

,....

4.5V ...

...

,....

5.5V

200
150

WE

OPERATION

OUTPUTS
TRI·STATE

L

L

Write

L

H

Read

Data

H

L

Inhibit. Store

TRI·STATE

H

H

Inhibit, Store

TRI·STATE

100
50
0
-5'

-2.

5

35

65

FREE AIR TEMPERATURE

9'

125

re)

ac test circuits
tlH

.---

e
, Jc'l
1,1~T
!'Ie, Ie,!,
DOl

DOJ

DOl

004

'--"L"tDk

CL

3·10

~

10pF

All Other AC Tosts

.--

~D"

D"-x.

T

T

':"

':'

x-~-r.

T

C
'

C, .... F

T

C
'

switching time waveforms

v~

______

~

Read Cy'cle

Write Cycle

(See Note 1)

(See Note 1)

______

~

MEfiiRV
ENAILE

v~

________........

v,, _ _ _ _ _....

ADDRESS
INrUT

ADDRESS
INPUT

DATA
OUT

INPUT

DATA

Read Modify Write Cycle

(See Note 1)

tOH

,

v,, _ _ _ _ _,
ADDRESS

INPUT

DATA OUT

.------.../

LATCHED ADDRESS

~......._!RI.STATECONDITION·

v~-_-_-.-_._ ~-_-2A~T~E~~:~N

__

J

.

--- -.-~

ql_

E::~::v~ _ _ _ _

X'-______. . . ~

DA;: v': ______________...

. j"""

!R V"

DATA OUT

"DIIII:~lIIIISIbI,"I_~"falw£lIIIna_lIIIIs _ _ every"'drlll~h1 .....

NOhrl: t,=I,=2tn$fGraHinpllU.

3-11

Vcc

..::.::::r---1
"U

o

.

VCC

-'-- TRI-5TATE

D

~

CMOS RAMs
Advance Information

NAnONAL

MM54C920/MM74C920 1024-bit static silicon gate CMOS RAM
general description

features

The MM54C920/MM74C920 256 x 4 random access
read/write memory is manufactured using silicon gate
CMOS technology. Data output is the same polarity as
data input. Internal latches store address inputs, CES
and data output. This RAM is specifically designed to
operate from standard 54/74 TTL power supplies.
All inputs and outputs are TTL compatible.

•
•
•
•
•
•

Complete address decoding as well as two chip select
functions, CEl and CES, and TRlcSTATE® outputs
allow easy expansion with a minimum of external com·
ponents. Versatility plus high speed and low power
make the MM54C920/MM74C920 an ideal element
for use in microprocessor, minicomputer as well as
main lrame memory applications.

The functional description will reference the logic
diagram of the MM54C920/MM74C920 shown in
Figure 1. lnput addresses and CES are clocked into
the input latches by the falling edge of STROBE. Input
setup and hold times must be observed on these signals
(see timing diagrams). The true and complement address
information is fed to the row and column decoders
which access the selected 4·bit memory word.

Fast access-250 ns max
TRI·STATE outputs
low power
On-chip registers
Single +5V supply
Data retai ned with VCC as low as 2V

functional description

logic and connection diagrams
AU

AI

.,
A2

A4

011-----~----+l--1

DD 1

-----t-----+I
D13 - - - - - t - - - - - + I
014 - - - - - t - - - - - + I

DDJ

DD 2

DI2

DD'

rn--[)O-l

A5

AS

A7

FIGURE 1. Logic Diagram

Dual.in-Line-Package
Vee

22

A4

21

WE

20

m

"

Sf
18

m
17

004

"

Dl4

15

DOl
14

OIl

13

002

12

Order Number MM54C920D or MM74C920D

See Package 5
Order Number MM74C920N

See Package 17

1
AJ

2
A2

, •
Al· AD

5
AS

6
A6

7
A7

8

"GND

,
011

10
DO 1

11
012

3·12

functional description (can't)
fall after STROBE has fallen without affecting access
time.

The addressed word (4 bits) is fed to four sense ampli·
fiers through the column decoders. The information
from the sense amplifiers is retained in the output
register when' STROBE rises. The register drives the
TRI-STATE output buffers.

The outputs are in a high impedance state when the
chip is not sel.ected (CES or CEl high) or when writing
(WE low). Note that the information stored in the out·
put latches will be changed whenever STROBE falls,
regardless of the logic states .of WE, CE lor CES.

Chip select inputs, CE land CES, have identical functions
except that CES (Chip Enabled Storedl.!!..clocked into a
latch on the falling edge of STROBE; CEl (Chip Enable
level) is not_

The timing diagrams in Figures 2, 3, and 4 define the
read, write, and output enable/disable parameters
respectively. These timing diagrams and the logic
diagram in Figure 1 completely describe the operation
of the RAM.

Note that setup and hold times must be observed on
CES. Because CEl is not clocked by STROBE, it may

absolute maximum ratings
7V
-Q_3V to Vee + O.3V

Supply Voltage, Vee
Voltage at Any Pin
Operating Temperature Range
MM54C920
MM74C920
Storage Temperature Range

-55°C to +125°C
-40°C to +85°C
-u5°C to +150°C

dc electrical characteristics
PARAMETER

Vee = 5.0V ±10%, TA = Operating Range
MM54C920

CONDITIONS
MIN

Y,H

l~gical "'" Input Voltage

V ,L

Logical "0" Input Voltage

TYP

MM74Cg20
MAX

V ee -2.0

MIN

TYP

MAX

Vcc -2.0

V

0.8

V OH1

Logical "1" Output Voltage

IOf1 "" -1.0 mA

V OH2

Logical ", .. Output Voltage

lOUT:::

V OLl

Logical "0" Output Voltage

tOl ""

V OL2

Logical "0" Output Voltage

lOUT

I'L

Input Leakage

OV:O;V'N :O;Vec

10

Output Leakage

OV:O; Vo $ Vee. CEL

Ice

Supply Current

V'N::: Vee or Gnd, eEL = Vee.

e 'N

Input Capacitance

Co

Output Capacitance

V OR

Vee for Data Retention

0'0

0

0.8

2.4

2.4

Vee-D.Ol

V ce -Q.Q1

UNITS

v
V
V

2.0mA

OA

0.4

=0

0.01

0.01

1.0

1.0

IlA

1.0

1.0

IlA

100

100

IlA

= Vee

= Open

Sf = OV, WE =

CEL

=

Vee.

V

V

5

5

pF

5

5

pF
V

2.0

2.0

01::: Vee or Gnd

ac electrical characteristics

Vee = 5_0V ±10%, T A'" Operating Range
MM74C920

MM54C920

PARAMETER
MIN

TTL Interface (V'H = Vec - 2.0V, V,L. ,., O.8V, Input tAISE = tFAL.L.

TYP

= 10 ns,

MAX
Load

= 1 TTL Gate +

MIN

TYP

MAX

UNITS

50 pF)

te

~ycle

t ACC

Access Time From Address

tAS

Address Setup Time

25

10

25

10

ns

tAH

Address Hold Time

25

15

25

15

ns

tOE

Output Enable "T:"ime

60

120

60

110

ns

too

Output' Disable Time

60

120

60

110

ns

tST

Sf Pulse Width

180

80

160

80

tST

ST Purse Width (Positive)

140

60

125

60

twp

Write Pulse Width (Negative)

150

80

130

80

ns

tos

Data Setup Ti me

70

40

60

40

ns

tOH

Data Hold Time

50

25

45

25

ns

320

Time

(Negative)

140

285

120

120

275

3-13

140

ns
250

ns

ns

DI

o

N

en
o

switching time waveforms

~

.~
o

N

en
o

f+-----,.. - - - - - I - - - - - ..T - - - - - - I
AD-A1

~

It)

:e
:e

f------Io,------i

1-------.ACC~========:::j----'-DOUT

- - - - - - - - - - ----TRJ-sTATE--------------

FIGURE 2. Read Cycle (WE = VIHI

'J

)
1sT

!iT

AD-A1

~

--'
~

..-

-'

f4'AH--

}

'''''
~

Do.

-/

I

10._ _\1;
Il

~tDH

FIGURE 3.Writa Cycle

l(

m

l(

1\
WE

1/

t

'oE
DoUT

too

--------TRI..TATE-------:k'--______
FIGURE 4. Output Enable/Disable

3·14

-'~----

~

MOS EPROMs

NATIONAL

MM1702A 2048-bit electrically programmable ROM
general description
The MM1702A is fabricated with silicon gate technology.
This low threshold technology allows the design and
production of higher performance MOS circuits and
provides a higher functional density on a monolithic
chip than conventional MOS technologies.

The MM 1702A is a 256 word by 8-bit electrically
programmable ROM ideally suited for uses where fast
turn-around and pattern experimentation are important.
The MM1702A undergoes complete programming and
functional testing on each bit position prior to shipment,
thus insuring 100% programmability.
The MM 1702AQ is packaged in a 24·pin dual·in·line
package with a transparent lid. The transparent I id allows
the user to expose the chip to ultraviolet light to erase
the bit pattern. A new pattern can then be written into
the device. The MM1702AD is packaged in a 24·pin
dual-in·line package with a metal lid and is not erasable.

features

The circuitry of the MM1702A is entirely static; no
clocks are required.
A pin-for-pin metal mask programmed ROM, the
MM1302 is ideal for large volume production runs of
systems initially using the MM1702A.

•

Fast programming-30 seconds for all 2048 bits

•

All 2048 bits
factory tested

•
•

Full.y decoded, 256 x 8 organization
Static MOS-no clocks required

guaranteed

•

Inputs and outputs DTL and TTL compatible

•
•

TRI-STATE® output-OR-tie capability
Simple memory expansion-chip select input lead

•

Direct replacement for the Intel 1702A

block and connection diagrams

DuaHn-Line Package
Al

A4

21

A1~

:

INPUT _
DRIVERS

AT4L...--

AS

20

AS

19

A1

11

VGG

11

Vas

16

15

e'!
14

PRO·
GRAM

13

ES

PROGRAM
AD_'---

programmable-100%

-

DATA

2048.BIT
ROM _ _ OUTPUT
MATRIX -------... SUFFERS

DE· _
CODER

(266x81
_

_

~
OUT 1
I
I

-

LL..... DATA

_r--""OUTB

Note: In Ihe 'lid mod. II Ingle
"1" It the.ddrlQjnpu~lnd dlta
outputl ill high Ind logic "0" il
• low.

, ,
AI

A'

I

AD

4
,1

, ,
, ,

lsa

7

4

, ,
, ,

10
7

·DATA OUT

11 J12
8,
MS'

Vee

TOP VIEW
*Thilpinilthldltllinputl.ldduringprogrimmino.

Pin Names

Order Number MM1702AO

See Package 6

AO-A7

Address Inputs

CS

Chip Select Input

DOUT

1 -

DOUT 8

Order Number MM1702AQ
See' Package

21

Data Outputs
Pin Connections*

MODE/PIN
Read
Programming

12

13

14

15

16

22

23

(Vee)

(PROGRAM)

(CS)

(Vaa)

(VGG)

(Vee)

(Vee)

Vce
GND

Vee
Program Pulse

GND
GND

Vee
Vee

VGG
Pulsed Vc;c; (V'L4P)

Vce
GND

Vee
GND

*The external lead connections to the MM1702A differ, depending on whether the device is being programmed or used in
read mode. (See following table.) In the programming mode, the data inputs 1-8 are pins 4-11 respectively.

4-1

absolute maximum ratings

(Note 1)

Ambient Temperature
Storage Temperature
Power Dissipation
Read Operation
Input Voltages and Supply Voltages with
Respect to Vee
Program Operation
Input Voltages and Supply Voltages with
Respect to Vee
Lead Temperature (Soldering, 10 seconds)

o°C to +70°C
-65°C to +125°C

2W
+0.5V to -20V

-48V

read operation de characteristics
T A = o°c to + 70°C, Vee = +5V ±5%, V DO = --9V ±5%, V GG

= --9V ±5%, unless otherwise noted. Typical values are at nominal

voltages and T A = 25° C. (Note 2)

PARAMETER
ILl

Address and Chip Select

CONDITIONS

MIN

TYP

VIN = O.OV

MAX

UNITS

1

IlA

I nput Load Cu rrent
I LO

Output Leakage Current

V OUT = O.OV, CS=V ee -2

1000

Power Supply Current

VGG = Vee,

CS = V ee -2

1

Il A

5

10

mA

35

50

mA

32

46

mA

38.5

60

mA

8

14

mA

13

mA

1

Il A

IOL = 0.0 mA, T A = 25°C,
(Note 2)
1001

Power Supply Current

CS = Vee -2, IOL ~ 0.0 mA,
TA = 25°C

1002

Power Supply Current

1003

Power Supply Current

CS =0.0, 10L = 0.0 mA, T A = 25°C

-

CS = Vec -2, IOL = 0.0 mA,
TA = O°C

ICF1

Output Clamp Current

V OUT =-1.0V, TA = O°C

ICF2

Output Clamp Current

V OUT = -1.0, T A ~ 25°C

IGG

Gate Supply Current

V IL1

Input Low Voltage for

-1.0

V ec -4.1

V

V cc-6

V

Vcc+0.3

V

TTL Interface
V IL2

Input Low Voltage for

Voo

MOS Interface
V rH

Address and Chip

V ec -2

Select Input High
Voltage
IOL

Output Sink Current

V OUT =0.45V

IOH

Output Sou rce Current

V OUT = O.OV

VOL

Output Low Voltage

IOL = 1.6 mA

V OH

Output High Voltage

10H = -1 0011 A

1.6

4

mA

-2.0

mA
-iJ.7

3.5

4.5

0.45

V
V

Note 1: Stresses above those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
and functional operation of the device at these or at any other condition ,above those indicated in the operational sections of this specification is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.

Note 2: Power-Down Option: VGG may be clocked to reduce po~er dissipation. The average 100 will vary between IDDO and 1001 depending
on the VGG duty cycle (see typical characteristics)' For this option, please specify MM1702AL.

4-2

read operation ac characteristics
TA = DOC to +70°C. Vee = +5V ±5%. Voo = -9V ±5%. VGG = --9V ±5%. unless otherwise noted.
PARAMETER

TVP

MIN

MAX

UNITS

Freq.

Repetition Rate

1

tOH

Previous Read Data Valid

100

ns

1

/.I.s

0.7

tAee

Address to Output Delay

tOVGG

Clocked V GG Set· Up (Note 1)

MHz

1

/.I.s

tcs

Chip Select Delay

100

ns

teo

Output Delay From CS

900

ns

too

Output Deselect

300

ns

tOHe

Data Out Hold in Clocked VGG Mode (Note 1 )

5

/.I.s

capacitance characteristics
PARAMETER

TA = 25°C (Note 3)

CONDITIONS

TVP

MIN

MAX

UNITS

CIN

I nput Capacitance

All Unused

V IN = Vee_

8

15

pF

COUT

Output Capacitance

Pins Are

CS = Vee

10

15

pF

CVGG

V GG Capacitance

At ac

30

pF

(Note 1)

Ground

- V OUT = Vee
VGG = Vee

Note 3: This parameter is periodically sampled and is not 100% tested.

DI

read operation switching time waveforms

1

(a) Constant VGG Operation

l----

ADDRESS

~.

V"l'"
V.• =
Ci
I

V1L

V"

v..

-r11%

DA.TA

~~-

V,,

DATA OUT

INVALID

OUT
V'"

CLOCKED

\

~~OUT

DATA

INVALID

OUT

1---_--1

:::X:

.

~"'~

DATA OUT

~

--.J.

~

INVALID

vo,

I

ADDRESS V"

cs

....{j'oo
~~wr-VOL

1

1

1

tJ:;;L
rr-

V,"):

~

INDTElI

DATA OUT

INVALID

I

v",

CLOCKED

teo

'

v..
DATA OUT

ColXlitiGnsafTm:
IItptrt IlIIIa IIftplitu!lesl 0--4V, .... tt S; 60 ilL o"tput I.... is 1 TTL pt.; nlllllUrepte !1rD S; 15 1111. CL=15,f.

V"

IIIIII1smada It lIIltput af TTL

-t
,

r--- ---:-

(NDTEZ':::-;..,..

v~

V"~r--"~
V.. v., '\

V"

OUT

I

DESElEtTlON OF DATA OUTPUT IN OR-TIE OPERATION

l:SV'H----l~
DA.TA

C

.1

~".~

v"
V. .

DESEtECTION OF DATA DUTPUTIN OR-TIE OPERATION

ADDOESS

I

V~=X:

v'"

I

CYClE,TIME = 1 1 f - - - t

.:i

r--CYClETIME"I~F---i
ADDRESS

I'

(b) Power·Down Option (Note 1)

\

_>'m

r--

..,~

j

I-->""~

lI--

V-

1-'_4

Notlll: tile output will ren\lAI valid till 'oHC IS lena II docbd VGG is at Vee. An
add,.." chin. 1liiy
SDD" II the 011,,1 ilunse.!dDClr:III Vee may nillillit
Veel. Datil bllCllfllll invaticl for 1M old ..wit......n ~locI:" VGG KIIN.ned 10 VaG.

01*1,.

NOIe!: If Ci'me•• 1 trlnlitian IralD V'L to VIM 1IIIIr"'c:lldIeiI VaG iut"GG. dru
desIIlctian of Duqun DCClln at too as 1II000000n til s1tbl: DperllilA with c:oastaal VaG.

4·3

«

N

0
~

programming operation dc characteristics
TA = 25°C, Vcc = OV, Vss = 12V ±10%, CS = OV unless otherwise noted.

::E
::E

PARAMETER
I LilP

Address and Data Input

CONDITIONS

MIN

TYP

MAX

UNITS

V IN =-48V

10

rnA

V IN =-48V

10

rnA

Load Current
I Ll2P

Program and V GG Load
Current

Iss
loop

Vss Supply Load Current

(Note 5)

10

100

rnA

Peak

Voo = V PROG = -48V
VGG = -35V (Note 4)

200

300

rnA

100

Supply Load

Current

0.3

V

-46

--48

V

Address Input Low Voltage

-40

--48

V

Pulsed Input Low Voo and

-46

--48

V

-35

--40

V

V IHP

Input High Voltage

V IL1P

Pulsed Data Input Low

V IL2P

Voltage

V IL3P

Program Voltage
V IL4P

Pulsed Input Low VGG
Voltage

Note 4: lOOp flows only during VOO, VGG on time. lOOp should not be allowed to exceed 300 mA for greater than 100,",•. Average
power supply current lOOp is typically 40 mA at 20% duty cycle.
Note 5: The VBB supply must be limited to 100 mA max current to prevent damage to the device ..

programming operation ac characteristics
TA = 25°C, Vcc = OV, Vee = 12V ±10%, CS =OV unless otherwise noted.
PARAMETER

CONDITIONS

MIN

Duty Cycle (V oo , V GG )
!¢Pw

Program Pulse Width

TYP

MAX
20

3

VGG =-35V, Voo =

UNITS
%
ms

V PROG = -48V
tow

Data Set-Up Time

25

/lS

tOH

Data Hold Time

10

/ls

tvw

V oo , VGG Set-Up

100

/ls

tvo

V oo , VGG Hold

t ACW

Address Complement

10

100

/ls

(Note 6)

25

/lS

(Note 6)

25

/lS

Set-Up
tACH

Address Complement
Hold

tATw

Address True Set-Up

10

/ls

tATH

Address True Hold

10

/lS

Nota 6: All B address bits must be in the complement state when pulsed VOO and VGG move to their negative levels. The addresses
(0-255) must be programmed as shown in the timing diagram until data reads true, then over-programmed 4 times that amount.
(Symbolized by x + 4x.l

4-4

programming operation switching time waveforms

PUlSEDVDD

POWER SUf'Pl Y

PULSED Vue;
POWERSUPPLV

PI'IOGRAMMING
PULSE

DATA INPUT
(DEVICE
OUTPUT
LINES)

[MdllitlRsafTrlt
Input pliise rise lind lall time,:...
CS·OV

1~1

typical performance characteristics
Output Current
Supply Voltage

IOD Current vs Temperature

~

.'C

....z
w
'"
~

.P

39
38
37
36
35

Voo =-9V
VGG:::: -9V
INPUTS '" Vee
OUTPUTS ARE OPEN

34

33
32
31
30
29
2'
27

Z E
w;:

r=~

u

~~

~z

.... w

"''''
~'"
.... '"
gu
40

60

80

-

SPECIFIED

~ - ~PERRAJ~~~
-3

100

VGO
VOL

C ....

CS 'O.OV

20

~

"'",
C

~E-

Program Waveforms

IA

.... z

"'w

-].5

I

-4

120

'" -9V
=+O.45V

I

I

-5

-6

-7

-8

Average Current

....

12

'"'"
B
"

10

~

••

Vee =+5V
VDO = -9V
VGG = -9V
TA=+25~C

/

Z

0;

....
=>

~c

... ""
-4

-l

-2

I-cy~ ~
Vf
-1

0

10

-10

YS

40
35
~

.'C

30

J
'"

25

~

..

>

V

V

V

V'

700
600

;:: 500
400
300
200
100

Access Time vs Temperature
1000
900

-

800
700
600

~
;:: 500
400

100

-~

e..

DUTY CYCLE (%1

300

70

900

V

10

200

60

800

10 20 30 40 50 60 70 80 90 100

~..

50

Access Time vs Load
Capacitance

./

!

40

1000

,.

OUTPUT VOLTAGE (VI

30

Duty

CLOC KED VaG'" -9V
Voo =-9V
CS :::: V1H
TA '" +25°C

20

1

20

AMBIENT TEMPERATURE rCI

Cvcle for Clocked V GG
(Note 1)

16
~

-9

SUPPL Y VOLTAGE (VI

Output Sink Current vs
Output Voltage

.'C

7- 7- -

TA '" +25°C

AMBIENTTEMPERATURE ('CI

14

N

~

Vcc =+5'V

c-gc~

VOO

J

,,~

Vee'" +5V

YS

I-t-t-+-+ 1 TIL LOAD ~ 20 pF
Vee =+5V

I-t-t-+-+ VOD '-9V
I-t-t-+-+ VGG =, -9V
10 20 30 40 50 60 70 80 90
AM81ENTTEMPERATUlIE rCI

4-5

1--+-+++--+-+ 1 TIL LOAD
1--+-+++--+-+ ~:: : ~~~
VeG:=' -9V

HY---+---+--+-+ Tj

'~25°~

10 20 3D 40 50 60 10 80 90 100
LOAD CAPACITANCE (pFI

operation of the MM1702A in program mode
Initially, all 2048 bits of the ROM are in the "0"
state, (output low). Information is introduced by selec·
tively programming "1 's" (output hig(1) in the proper bit
locations.

minimum of 10/.ls before the program pulse is applied.
The addresses should be programmed in the sequence
0-255 for a minimum of 32 times. The eight output
terminals are used 'as data inputs to determine the
information pattern in the eight bits of each word. A low
data input level (-48V) will program a "1" and a high
data input level (ground) will leave a "0" (see table on
page 4·4). All eight bits of one word are programmed
simultaneously be setting the desired bit information
patterns on the data input terminals.

Word address selection is done by the same decoding
circuitry used in the READ mode (see table for logic
levels). All 8 address bits must be in the binary comple·
ment state when pulsed V DO and V GG move to their
negative levels. The addresses must be held in their binary
complement state for a minimum of 25/.1s after V DO and
VGG have moved to their negative levels. The addresses
must then make the transition to their true state a

During the programming, V GG , V OD and the Program
-Pulse are pulsed signals.

MM1702A erasing procedure
out short·wave filters, and the MM1702A to be erased
should be placed about one inch away from the lamp
tubes. There exists no absolute rule for erase time.
Establish a worst case time required with the equipment.
Then over·erase by a factor of 2, i.e., if the device
appears erased after 8 minutes, continue exposure for
an additional 16 minutes for a total of 24 minutes.
(May be expressed as x + 2x.)

The MM1702A may be erased by exposure to high
intensity short-wave ultraviolet light at a wavelength of
2537k The recommended integrated dose (i.e., UV
intensity x exposure time) is 6W sec/cm 2 . Examples of
ultraviolet sources which can erase the MM1702A in 10
to 20 minutes are the Model UVS-54 and Model S·52
short·wave ultraviolet lamps manufactured by Ultra·
Violet Products, Inc. (5114 Walnut Grove Avenue,
San Gabriel, California). The lamps should be used with·

4·6

MOS EPROMs

~

NA110NAL

MM4203/MM5203 electrically programmable
2048-bit read only memory (pROM)
general description
The MM4203iMM5203 is a 2048-bit static readonly memory which is electrically programmable
and uses silicon gate technology to achieve bipolar
compatibility. The device is a non-volatile memory
organized as a 256-8-bit words or 512-4-bit words.
Programming of the memory contents is accomplished by storing a charge in a cell location by
programming that location with a 50 volt pulse.
Separate output supply lead is provided to reduce
internal power dissipation in the output stage
(VLd·

•

Pin compatible with MM5213, MM5231 mask
programmable ROMs
• Static operation - no clocks required
• Common data busing (TRI-STATE@output)
• "0" quartz lid version erasable with short wave
ultra-violet light (i.e. 253.7 n.m.)
•
•

applications
•
•
•
•
•

features
•
•
•

Field programmable
Bipolar compatibility
High speed operation

Chip select output control
256 x 8 or 512 x 4 organization

+5V, -12V operation
l/1s max access time

Code conversion
Random logic synthesis
Table look-up
Character generator
Micro-programming

block and connection diagrams

Dual-In-Line Package

,'"

" ,
lS8 A,

]

II PROGRAM

e, •

'21'"

e, ,

""

.
".
"

e, •

" ,
~

18,.,

e

16 Voo
8,1D

."

14CS

V",,12

13 A,.MSB

Order Number MM4203D or MM5203D

See Package 6
Order Number MM42030 or MM52030
See Package 21

typical applications
256 x B PROM Showing TTL I ntorfaco

".

Operating Modes

'sn~
t

MODE

,

CIINThOL

..

"

.,

256 x 8 ROM connection (shown)
Mode Control ~ HIGH (VSSl
Ag
- LOW
~

512 x 4 ROM connections

ModeControl- LOW (GNO or VDO)
Ag
..c.- Logic HIGH enables the odd (81, B3-.B71 outputs

- Logic LOW enables theeven'(B2, 84 ,Bal outputs
The outputs are en11

Of)OO():')O'1
00111100

T8R
TB7
TBI)
TRS
T94
TB3
IS2
TBI

oo!')()o(Jnn
01(l10tOI
140
150
Z'50
40()
01 (')
100
299
197

b" LSB (Pin 4)

Notf! 3

ADOI

~

.""'MSBIPinlll

Note 1~ The code is a 7-bit ASCII code on 8 punch tape. The tape
should begin and end with 25 or more "RUBQUT" punches.

____

Note 2: The ROM input address is expressed in decimal form and is

1--1 Space

preceded by the letter A.
Note 3: The total number of "1" bits in the output word.
Notl! 4: The total number of "1" bits in each output column or bit
position.

0
4
0
4

Note 4

t

~

Space

typical performance, characteristics

Maximum Access Time (TACC)

as a Function of Vee Supply
Voltage

Maximum Supply Current ISS
as a Function of Temperature
1700

Vss" +4,75V1600
1500

60

.5
;;
jI

50
40

30
20
10

o

t--

~

NOM SUPfl Y

1400

rt"-N:
tUt!1t:8~t:si~~
-5% SUPPl Y/

tl

..!.1300

1-++l--t-r-r-1--r+H+-H--I
H++--I-+++--I-+++-H-+-I
I-++H+-H.-++H+-H--I

1200

1100
1000

~~~-L~~~~-L~-"

-50 -25

0

25

50

75

100 125

-9

T.IOC)

-10

-11
Voo (Volts)

4-11

-12

-13

~

MOS EPROMs

NAll0NAL

MM4204/MM5204
electrically programmable 4096-bit read only memory (EROM)

general description
The MM4204/MM5204 is a 4096-bit static Read Only
Memory which is electrically programmable and uses
silicon gate technology to achieve bipolar compatiblity.
The device is a non-volatile memory organized as 512
words by 8 bits per word. Programming of the memory
is accomplished by storing a charge in a cell location by
applying a -50V pulse. A logic input, "Power Saver," is
provided which gives a 5:1 decrease in power when the
memory is not being accessed.

• Low power dissipation
• "Power Saver" control for low power applications

features

applications

•
•

Field programmable
Fast program time: ten seconds typical for 4096·bits

•

Fast access time
MM4204
MM5204

•
•
•
•
•
•

•

5.0V,-12V
• Standard power supplies
• Static operation-no clock required
• Easy memory expansion-TRI·STATE® output Chip
Select input (CS)
"Q" quartz Iid version erasable with short wave ultra·
violet light (i.e., 253.7 nm)

•

1. 25j.ls
1MS

DTL!TTL compatibility

Code conversi<;>n
Random logic synthesis
Table look·up
Character generator
Microprogramming
Electronic keyboards

block and connection diagrams
Dual-ln~Line

..,l!...Vl-

L

v~

...,1.LVoo

A,

409&-8IT

A,

fROM
MATRIX

A,

512118

+--1I8B

24

2287
21 86

PRDGRAM

A,

A,
A,
A.
A,

A,

A,
A,
A,
A.
A.
v~

S

lOB,

•

IS 8"

,

IS B:!

•
•

17 8 2

16 B,

10

""

11

14 As

12

13 At

TOP VIEW

Order Number MM4204D
orMM5204D
See Pac~.ge 6
Order Number MM4204Q
orMM5204Q
See Package 21

4·12

VLI.-

" V,,

---,
CHIP SELECT

12
+--v§

POWER SAVER

1

POWER SAVER

1

~PROGRAM

A,

Package

absolute maximum ratings

(Note 1)

All Input or Output Voltages with
Respect to V ss Except During Programming

+O.3V to -20V
750mW

Power Dissipation
Operating Temperature Range

oDe to +70°C

MM5204

-55°C to +85°C

MM4204
Storage Temperature Range

-65°C to +125°C
300°C

Lead Temperature (Soldering, 10 seconds)

dc electrical characteristics
MM4204: Vss

= 5.0V ±10%,

= -12V

Voo

T A within operating temperature range, V LL

±10%, MM5204: Vss

PARAMETER

= 5.0V

±5%, Voo

= -12V

V BS = PROGRAM = V ss ,

TYP

MIN

CONDITIONS

= OV,

±5%, unless otherwise noted.

(Note 7)

MAX

UNITS

V'L

Input Low Voltage

V ss-14

Vss-~·2

V

V ,H

Input High Voltage

V ss -l.5

Vss+0.3

V

III

Input Current

Y'N = OV

1.0

I1A

VOL

Output Low Voltage

10L = 1.6 mA

V LL

0.4

V

V OH

Output High Voltage

10H

2.4

Vss

V

I LO

Output Leakage Current

V OUT = OV, CS = V ,H

1.0

I1A

100

Power Supply Current

MM5204

T A = oDe,

MM4204

TA

MM5204

TA

MM4204

TA

CS = V IH, Power Saver = V'L
CS '" V ,H , Power Saver = V'L
= DoC, CS = V IH, Power Saver = V ,H
= DoC, CS = V ,H , Power Saver = V ,H

MM5204

TA

= O°C,

V 1L

42

rnA

MM4204

TA =O'C,CS = V ,H , Power Saver=V ,L

52

rnA

MM5204

TA

= O°C, CS = V ,H , Power Saver = V ,H
TA = DoC, CS = V ,H , Power Saver = V ,H

10

mA

12

rnA

=

-D.8 mA

MM4204

ac electrical characteristics
MM4204: Vss

= 5.0V ±10%,

Voo

= -12V

=

tpo

CS

coo

V 1H • Power Saver

=0

6.0

40.0

mA

50.0

mA

8.0

mA

10.0

mA

T A within operating temperature range, V LL = OV, Vss = PROGRAM

±10%, MM5204: Vss

= 5.0V

±5%, Voo

CONDITIONS

PARAMETER
tAce

28

DoC,

= -12V
MIN

= V ss ,

±5%, unless otherwise noted.
TYP
(Note 7)

MAX

UNITS

Access' Ti me
MM5204

T A = 70°C,(Figure I}, (Note 4)

MM4204

T A = 85°C, (Figure I), (Note 4)

0.75

1.0

115

1.25

115

Power Saver Set-Up Time

MM5204

(Figure I)

1.8

I1S

MM4204

(Figure I)

2.0

I1S

MM5204

(Figure 1)

500

ns

MM4204

(Figure 1)

600

ns

tOH

Data Hold Time

(Figure 1)

taDe

Chip Select Deselect Time

teo

t ODP

Chip Select Delay

30

50

ns

MM5204

(Figure 1)

30

300

500

ns

MM4204

(Figure 1)

30

300

600

ns

MM5204

(Figure I)

30

300

500

ns

MM4204

(Figure I)

30

300

600

ns

5.0

8.0

pF

8.0

15

pF

Power Saver Deselect Time

C'N

Input Capacitance (All Inputs)

COUT

Output Capacitance

(All Outputs)

Y'N = V ss , f = 1.0 MHz, (Note 2)
V OUT = V ss , CS = V ,H , f = 1.0 MHz,
(Note 2)
4-13

a

programmer electrical characteristics

TA = 25°C, Vss = CS = Power Saver

= OV, V LL = OV to -14V,

unless otherwise specified, (see Figure 2), (Note 5).
PARAMETER

CONDITIONS

MIN

TVP
(Note 7)

MAX

UNITS

Data Input Load Current

V,N =-18V

-10

mA

Address Input Load Current

Y'N = -50V

-10

mA

Program Load Current

Y'N = -50V

-10

mA

V BB Load Current

IlOO

V00 Load Current

V'HP

Address Data and Power Saver

VOO

=

PROGRAM = ~50V
-2.0

50

mA

-200

mA

0.3

v

Input High Voltage

v

Address Input Low Voltage

-50

-11

Data Input Low Voltage

-18

-11

V OHP

VOD and Program High Voltage

-2.0

0.5

VOlP

Voo and Program Low Voltage

-50

-48

V

VBlP

VB. Low Voltage

o

0.4

V.

V•• High Voltage

11.4

V.HP

Pulse Duty Cycle

V

V

12.6

V

25

%

Program Pulse Width

0.5

Data and Address Set-Up Time

40

Data and Address Hold Time

o

tss

Pulsed VOD Set-Up Time

40

tSH

Pulsed Voo Hold Time

1.0

/1S

tBs

Pulsed V BB Set-Up Time

1.0

/1s

tBH

Pulsed VBe Hold Time

1.0

/1s

t pss

Power Saver Set-Up Time

1.0

/1s

tpSH

Power Saver Hold Time

1.0

tR, tF

V 0 0, Program, Address and Data

tpw
t

DS

5.0

ms
/1s
/1s

100

/1S

/1S
1.0

/1s

Rise and Fall Time
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices 'should be operated at these limits. The table of "Electrical Characteristics'~
provides conditions for actual device operation.

Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Positive 'true logic notation is used except on data inputs during programming
Logic "1" := most positive voltage level
Logic "0" = most negative voltage level
Note 4: tACC = 1000 ns + 25 (N-1) where N is the number of devices wire-OR'd together.
Note 5: The program cycle should be repeated until the data reads true, then over~programmed 5 times that number of cycles. (Symbolized as
X + 5X programming).
Note 6: The EROM is initially programmed with all "0',." A VIHP on any data input BO-B7 will leave the stored "0'," undisturbed, and a VILP
on any data input 80-B7 will write a logic "1'"' into that location.
Note 7: Typical values are for nominal voltages and T A = 2SoC, unless otherwise specified.

erase specification
The recommended dosage of ultraviolet light exposure is 6W sec/cm 2 _

programming
The MM4204/MM5204 is normally shipped in the un·
programmed state. All 4096-bits are at logic "0" state.
The table of electrical programming characteristics and
Figure 2 give the conditions for programming of the
device. In the program mode the device effectively
becomes a RAM with the 512 word locations selected by

address· inputs AO-AS. Data inputs are 80-87 and
write operation is controlled by pulsing the Program
input. Since the EROM is initially shipped with all "O's,"
a V IHP on any data input 80-87 will leave the stored
"O's" undisturbed· and a V ILP on any data input 80-87
will write a logic" 1" into that location.

4-14

programming (cont.)
National offers programmer options with both the
IMP16-P and the PACE IPC-16P Microprocessor Development Systems.
Microprocessor System

Programmer Part Number

IMP16-P
IPC·16P

IMP-16P/S05
IPC-16P/S05

Contact the local sales office for further information.
There are also several commercial programmers available
such as the Data I/O Model V.
Most National distributors have programming capabilities available. Those distributors should be contacted
directly to determine which data entry formats are
available.
In addition, data may be submitted to National Semiconductor for factory programming. One of the following formats should be observed:

preferred format
The custom patterns may be sent in on. a Telex or submitted as a paper tape in a 7·bit ASCII code from model 33 teletype or TWX. The paper tape should be as the following example:

Start Character

l

Stop Character

Leader Rubout for

T~~t~~e~\~;'~:,~

!rI

1

Carnage return line feed

allowed between F and B
Data Fleld*

MSa (Pin 11)

B PPPN PPN N F B N N PPN N PPF
T

25 framesl.

Word 0

LSB (Pin 41

It'

Trailer: Rubout for

TWX or letter Key

BN PN PN N N N F

for telex lat least
25 frames).

Y

1\

Word 1

,

All Address Inputs LOW

Word 511

All Address Inputs HIGH

'Data Field: Mu.t have only P's or N'. typed between Band F. No null. or rubout•• Mu.t have exactly eight P and N characters between
Band. F. Any characters except Band F may be typed between the F stop character and the B start character. If an error is made in preparing a tape the entire word including the Band F start and stop characters must be rubbed out. Data for exactly 512 words must be
entered beginning with word O.

alternate format

[Punched Tape (Note 1) or Cards]
b,. MSB (Pin 221

MM5204

boo LSB (Pin 151

Positive Logic

Spaces
4n0()
Anlll

nr')()()oon(}

n

~n()2

OOf1,)(lnf'll)

0

,\()O]

III n I n If) I

4

IVH"),{l

n0111111
0(11),1 I 1(1'1

6
.I
f1

I\IH)S

--"""--Note3

;,nn 6

()'ll')n r )i'lfl1

If) -,

1)r)11110n

l\nnf;1

on'1nnQ(W

.'~

4
f1

r--

Note 2: The ROM input address is expressed in decimal form
and i. preceded by the latter A •

-

()ltllr'l!rJ}
/-\51 I
TSI 1.-4n _ - - - - - - - t - - N o t e
T86 I "l(l
TB5 ·)St]
TB4 4nn
183 oln
TB2 ,00
1 B1 ~q9
T 80 197

"

Note 1: The code is a 7·bit ASCII code on 8 punch tape. The
tape .hould begin and end with 25 or more ··RUBOUT" punche•.

1 Space

Note 3: The total number of "1" bits in the output word.
Note 4: The total number of
bits in each output column or
bit position.

u'"

4

t

' - - - - - - - - - t - - l Space

erasing procedure

exposure for an additional 16 minutes for a total of 24
minutes. Examples of UV sources include the Model
UVS-54 and Model S·52 manufactured by Ultra-Violet
Products, Inc. (5114 Walnut Grove Avenue, San Gabriel,
California). The lamps should be used without shortwave filters. The MM4204/MM5204 should be placed
about one inch away from the lamp for about 20-30
minutes.

The MM42040/MM52040 may be erased by exposure
to short-wave ultraviolet light-253.7 nm. There exists
no absolute rule for erasing time or distance from
source. The erasing equipment output capability should
be calibrated. Establish.a worse case time required with
the equipment. Then over-erase by a factor of 2,i.e., if
the device appears erased after S minutes, continue
4·15

ac test circuit

typical application
CHIP
SELECT

5.0V±5%

"

A,

Vss

Vss PROGRAM

ADORE,.
INPUTS

r
MM4204/
MM5204

A.
OM1400

-12V 15%

-t5.DV tS%

-12V

~5"

DV

DV

o-----l
O---+--l
o-----lv"

"l",ce. tOH. teo. and loll measured at DlI'Iput 01 MM4204!MM5204.

POWER

ON

switching time waveforms

ADDRESS

PDWER SAVER

CHIP SELECT

DATA OUT

Note: All times measu,1!d wilt. '''''PUCI 10 1.5V lewel with tR and t'F :::; 20 ns.

FIGURE 1. Read Operation

programming waveforms

POWER

SAVER

ADDRESS
AND DATA V,"~==="

'-_+_______-'-+_-J

PROGRAM

FIGURE 2. Programming Waveforms

4·16

B7

~

Bipolar PROMs
Advance Information

NAnoNAL

DM54S287/DM74S287 TRI-STATE® 1024-bit PROM
DM54S387/DM74S387 open-collector 1024-bit PROM
general description
These TTL compatible memories are or.ganized in the
popular 256 words by 4 bits configuration. Two
memory enable inputs are provided to control the
output states. When both enable inputs are in the
logical "0" state, the outputs present the contents of
the word selected by the address inputs.

instructions. Once programmed, it is impossible to go
back to a logical "0"; h~wever, additional bits may be
programmed to a logical "1."

If either or both of the enable ilJPuts is raised to a logical
"1" level, it causes all four outputs to go to the "OFF"
or high impedance state. The memories are available in
both open-collector and TRI-STATE versions and. are
available as ROMs as well as PROMs.

• Schottky clamped for high speed systems

features
• High speed
Enable to output delay-typical
Address to output delay-typical
• PNP inputs reduce input loading

PROMs are shipped from the factory with a logical "0"
in all locations. A logical "1" may be programmed into
any selected locations by following the programming

• All dc and switching characteristics may be measured
prior to programming PROMs

connection diagram
Dual-In-Line Package

Ei'lliBU1 ENAiiITlOUT 1

A7
15

13

14

DUT2

OUT3

11

10

12

OUT4

-

-

A6

A5

A4

15 ns
30 ns

AD

A3

AI

A2

TOP VIEW
Order Number DM54S287D or DM54S387D

Saa Package 3
Oreier Number DM74S287N or DM74S387N

See Package 15

5·1

absolute maximum ratings
Supply Voltage (Note 2)
Input Voltage (Note 2)
Output Voltage (Note 2)

-Q.5Vto+7.0V
-1.2V to +5.5V
-Q.5V to +5.5V
-65°e to +150o e
3000 e

Storage Temperature
Lead Temperat'ure (Soldering, 10 seconds)

dc electrical characteristics

Supply Voltage (Vee)
DM54S287, DM54S387
DM74S287, DM74S387

MAX

UNITS

4.5
4.75

5.5
5.25

V
V

+125
+70

°e
°c

Ambient Temperature (TA)
DM54S287, DM54S387
DM74S287, DM74S387

-65
0

Logical "0" Input Voltage

0

0.8

V

Logical "1" Input Voltage

2.0

5.5

V

CONDITIONS

Logica) "1" Input Current

MIN

(Note 3)

PARAMETER
I'H

operating conditions

(Note 1)

MIN

'TYP

MAX

UNITS

Y'N = 2.7V

25

/LA

Y'N = 5.5V

1.0

rnA
I1A

I'L

Logical "0" Input Current

Y'N = 0.45V

-250

VeL

Input Clamp Voltage

liN = -18 mA

-1.2

VOL

Logical "0" Output Voltage

10L

lee

Maximum Supply Current

V

0.50

= 16 mA

80

130

V
rnA

DM54S387, DM74S387
10H

Logical "1" Output Current

V OUT = 2.4V
V OUT = 5.5V

50

I1A

100

/LA
,

DM54S287,DM74S287
V OH

los

Logical "I" Output Voltage
DM54S287

10H

=-2.0 mA

2.4

V

DM74S287

10H

=-6.5 mA

2.4

V

Output Short Circuit Current

V OUT ~ OV (Note 4)

-30

-100

rnA

-50

50

I1A

MAX

UNITS

Vee = Max
loz

TRI-STATE Output Current

switching characteristics
PARAMETER
tAA

0.45V -::; V OUT -::; 2.4V

(Note 3)
CONDITIONS

Address to Output Delay

tEA

Time to Enable Output

teo

Time to Disable Output

RL = 300n

MIN

TYP
30

ns

15

ns

15

ns

C,- = 30pF

Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that
the device may be operated at thE!!se values.
Note 2: These limits do not apply to PROMs during prognlmming. For the absolute maximum ratings, refer to the programming instruc~
tions.
Note 3: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee = 5.0V and TA = 25°C.
Note 4: Ouring 'OS ~easurement, only one output at a time should be grounded. Permanent damage may otherwise result.

5-2

~

'Bipolar PROMs
Advance Information

NA110NAL

OM54S470/0M74S470 open-collector 2048-bit PROM
OM54S471/DM74S471 TRI-STATE® 2048-bit PROM

general description
These TTL compatible memories are organized in the
versatile 256 words by 8 bits configuration, Two
memory enable inputs are provided to further enhance
their versatility, When both enable inputs are in the
logical "0" state, the eight outputs present the contents
of the word selected by the address inputs,

instructions, Once programmed, it is impossible to go
back to a logical "0"; however, additional bits may be
programmed to a logical "1,"

features

If either or both of the enable inputs is raised to a logical
"1" level, it causes all eight outputs to go to the "OFF"
or high impedance state, The memories are available in
both open-collector and TR I-STATE versions and are
available as ROMs as well as PROMs,

• Schottky clamped for high-speed systems
• High speed
Address to output delay
35 ns
Enable to oytput delay
15 ns
• PN~ inputs reduce input loading
• 20 pin, 300 mil package for high density
• All dc and switching characteristics may be measured
prior to programming PROMs

PROMs are shipped from the factory with a logical "0"
in all locations, A logical "1" may be programmed into
any selected locations by following the programming

6

connection diagram
Dual-ln~Line

A7

AI

19

18

AS

17

EN 2

Package

m

OUT8 OUT7 OUT lOUTS

15

16

14

13

12

11

.110

4
AD

AI'

A2

A3

A4

OUT lOUT 2 OUT 3 OUT 4

TOP VIEW

Order Number DMil4S470N or DM74S471N
See I'ackege 16A

5-3

GND

I

absolute maximum ratings
Supply Voltage (Note 2)
Input Voltage (Note 2)
Output Voltage (Note 2)
Storage Temperature
Lead Temperature (Soldering, 10 seconds)

-o.5V to +7.0V
-1.2V to +5.5V
-o.5V to +5.5V

MIN

MAX

UNITS

4.5
4.75

5.5
5.25

V
V

Ambient Temperature (T A)
OM545470,OM54S471
OM745470,OM74S471

-55
0

Logical "0" Input Voltage

0

0.8

V

Logical .. ,.....Input Voltage

2.0

5.5

V

+125
+70

·e
·e

(Note 3)

PARAMETER'
Logical "1" Input Current

Supply Voltage (Vee)
DM545470,OM545471
OM745470, OM74S471

-£5·e to +1SO·e
300·e

dc electrical characteristics

liH

operating conditions

(Note 1)

CONDITIONS

MIN

TYP

MAX

UNITS

V 1N = 2.7V

25

V 1N = 5.5V

1.0

IlA
rnA
IlA

IlL

Logical "0" Input Current

V 1N = 0.45V

-250

V CL

Input Clamp Voltage

IIN=-18mA

-1.2

VOL

Logical "0" Output Voltage

10L = 16mA

Icc

Maximum Supply Current

V

0.50

V

150

rnA

V OUT = 2.4V

50

IlA

V OUT = 5.5V

100

IlA

100

DM54S470, DM74S410
10H

Logical "1" Output Current

DM54S471,DM74S471
V OH

los

Logic~1 "1" Output Voltage
DM54S471

10H =-2.0 rnA

2.4

V

DM74S471

10H =-6.5 rnA

2.4

V

Output Short Circuit Current

V OUT = OV (Note 4)

-30

-100

rnA

-50

50

IlA

MAX

UNITS

Vce = Max
102

TRI-STATE Output Current

switching cha racteristics
PARAMETER
tAA
tEA

0.45V ~ V OUT ~ 2.4 V

(Note 3)
CONDITIONS

MIN

Address to Output Delay
Time to Enable Output

RL = 300.11

TYP
35

ns

15

ns

15

1)5

C L =30pF
tED

Time to Disable Output

Note 1: Absolute maximum ratings are those values beyond which the;! device may be permanently damaged. They do not mean that the

device may be operated at these values.

.

Note 2: These limits do not apply to PROMs during programming. For the absolute maximum ratings, refer to the programming instruc-

tions.

Note 3; These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee == 5.0V and T A = 2SoC.
Note 4; During lOS measurement, only one output at a time should be grounded. Permanent damage may otherwise result.

5-4

~

Bipolar PROMs
Advance Information

NA110NAL

DM54S570/DM74S570 open-collector 2048-bit PROM
DM54S571/DM74S571 TRI-STATE® 2048-bit PROM
general description
These TTL compatible memories are organized as 512 .
words by 4 bits. These devices effectively double the
capacity of the popular 1 k ROMs on the market by
utilizing one chip-enable input as an additional address.
When the circuit is enabled, the 4 outputs present the
contents of the word selected by the address inputs.

any selected locations by following the programming
instructions. Once programmed, it is impossible to go
back to a logical "0." Additional bits may be programmed
to a logical "1," however.

An overriding enable input is provided which, if in the
logical "I" state, causes all. outputs to go to the "OFF"
state, or high impedance state. Available in both open·
collector or TRI-5TATE, both versions are also available
as Programmable Read Only Memories.

• Schottky clamped for high speed systems
• High speed
35 ns
Address to output delay-typical
Enable to output delay-typical
15 ns
• PNP inputs reduce input loading
• All dc and switching characteristics may be measured
prior to programming PROMs

~eatures

PROM's are shipped from the factory with a logical "0"
in all locations. A logical "I" may be programmed into

connection diagram
Dual~ln·Line

V[CC
16

A6

AI

A7

14

15

A5

ENABLE

A4

Package

OUTI

13

A3
TOP

OUT2

12

AD

OUT

11

AI

3

OUT4

10

A2

VIEW

Order Number DM54S570D, DM54S571D, DM74S570D, DM74S5710
See Package 3
Order Number DM74S570N or DM74S571N
See Package 15

5·5

absolute maximum ratings
Supply Voltage (Nate 2)
Input Voltage (Note 2)
Output Voltage (Note 2)
Storage Temperature
Lead Temperature (Soldering, 10 seconds)

-o.5V to +7 .OV
-1.2V to +5.5V
-o.5V to +5.5V
~5°e to +150o e
300"e

dc electrical characteristics

logical "1" Input Current

MIN

MAX

UNITS

4.5
4.75

5.5
5.25

V
V

-55
0

+125
+70

°e
°e

Logical '''0'', I nput Voltage

0

0.8

V

Logical "1" Input Voltage

2.0

5.5

V

Supply Voltage (Vee)
DM54S570, DM54S571
DM74S570, DM74S571
Ambient Temperature (TA)
DM54S570, DM54S571
DM74S570. DM74S571

(Note 3)

PARAMETER
I'H

operating conditions

(Note 1)

CONDITIONS

MIN

TVP

MAX

UNITS

Y'N = 2.7V

25

/lA

Y'N = 5.5V

1.0

mA

I'L

logical "0" Input Current

Y'N = 0.45V

-250

/lA

VeL

Input Clamp Voltage

liN =-18 mA

-1.2

V

"0" Output Voltage

VOL

logical

lee

Maximum Supply Current

IOL=16mA
100

0.50

V

150

mA

DM54S570, DM74S570
.,

logical "1" Output Current

10H

V OUT = 2.4V

50

/lA

V OUT = 5.5V

100

/lA

DM54S571, DM74S571
V OH

logical "1" Output Voltage
DM54S571

10H = -2.0 mA

2.4

DM74S571

10H =-6.5 mA

2.4

Output Short Circuit Current

los

V OUT = OV (Note 4)

V
V

-30

-100

mA

-50

50

/lA

MAX

UNITS

Vee = Max
TRI·STATE Output Current

loz

switching characteristics
PARAMETER
tAA

(Note 3)
CONDITIONS

Address to Output Delay
Time to Enable Output

tEA

0.45V ~ V OUT ~ 2.4V

RL = 300n
C L =30 pF

Time to Disable Output

tED

MIN

TVP
35

ns

15

ns

15

ns

i

Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that
the device may be operated at these values.
Note 2: These limits do not apply to PROMs during programming. For the absolute maximum ratings, refer to the programming. instructions.
Note 3: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee = S.OV and TA = 2!JC.
Note 4: During lOS measuremer:-t, only one output at a time should be grounded. Permanent damage may otherwise result.

5·6

~

Bipolar PROMs

Advance Information

NAll0NAL

DM12S114/DM82S114 TRI-STATE® 2048-bit PROM with latches
general description
These TTL compatible memories are organized as '256
words by 8 bits. Two enable inputs are. provided. When
the strobe input is at a logical "1" level the memories
function in the conventional manner with the enable
inputs determining whl!ther the outputs present the
Contents selected by the address inputs or are in the
high impedance state. The outputs are in the high
impedance state unless enable 1 is at a logical "0" and
enable 2 is at a logical "1."

into any selected locations by following the programming
instructions. Once programmed, it is impossible to go
back to a logical "0"; however, additional bits may be
programmed to a'iogical "1."

features
• Schottky clamped for high speed systems
• High speed
Enable to output delay
15 ns
Strobe to output delay
20 ns
Address to output delay
35 ns
• PNP inputs reduce input loading
• Output latches simplify system use
• All dc and switching characteristics may be measured
prior to programming PROMs

When the strobe is at a logical "0" the outputs are
latched into the state they were in just prior, to the
strobe going low. The, outputs remain in this condition
until the strobe is again taken to the logical "1" state
regardless of the state of the address or enable inputs.
PROMs are shipped from the factory with a logical
"0" in all locations. A logical "1" may be programmed

logic and connection diagrams
ADO-

.

ADDRESS
BUFFER

AND
DECODE

A70-:

r-

··
r-·

256 X 8
ARRAY

STRD8E

ENABLE I

o-..J---r-'-I
V"--"'1r1r-'

ENABLE 2 n.o---J-L_IL---I

Dual-. n- Line Package

AD

I
A3

2
A4

3
Jc

EN!

OUTPUTS

,
EN 2 STRBE

8

•

21

20

19

18

17

16

4

•

6

r

8

9

AS

A6

I.

10
07

I

2

3

\

4,
,

NC
14

113

.,r .1.
NC

12

GNo

OUTPUTS
TOP VIEW

(NC '" No Connection Internally)

Order Number DM72S114D
or DM82S114D
See Package 6

Order Number DM82S114N
See Package 18

absolute maximum ratings

operating conditions

(Note 1)

-{i.5V to +7.0V
-1.2V to +5.5V
-{i.5V to +5.5V
~5·e to +150·e

Supply Voltage (Note 2)
Input Voltage (Note 2)
Output Voltege (Note 2)
Storage Temperature
.
Lead Temperature (Soldering, 10 seconds)-

Supply Voltage (Vee)
DM72S114
DM82S114

300"e

dc electrical characteristics

Logical "1" Input Current

MAX

UNITS

4.5
4.75

5.5
5.25

V
V

Ambient Temperature (TAJ
DM72S114
DM82S114

-55
0

Logical "0" Input Voltage

0

0.80

V

Logical "I" Input Voltege

2.0

5.5

V

·e

+125
+75

·e

(Note 3)
CONDITIONS

PARAMETER

MIN

MIN

TYP

MAX

UNITS

V IN = 2.7V

25

J.I.A

VIN = 5.5V

1

mA

-250

fJ.A
fJ.A

Logical "0" Input Current
DM72S114

V IN = 0.45V

DM82S114

-100

Input Clamp Voltage

-1.2

V

Logical "0" Output Voltage
DM72S114

lOUT

DM82S114

0.50

= 12 mA

0.45

V
V

Logical "1" Output Voltage
DM72S114

lOUT = "-2.0 mA

2.4

V

DM82S114

lOUT = -2.0 mA

2.7

V
V

DM82S114

lOUT

Output Short Circuit Current

=-6.5 mA

V OUT = OV (Note 4)

2.4

-30

-100

mA

Vee = Max
loz

Icc

TRI-STATE Output Current
DM72S114

0.45V :::; V iJUT :::; 2.4V

-50

50

DM82S114

0.45V :::; V OUT :::; 5.5V

-50

50

Maximum Supply Current

switching characteristics
PARAMETER

110

170

TYP

MAX

mA

(Note 3)
CONDITIONS

MIN

UNITS

Address to Output Delay

Strobe = "1"

35

ns

tEA

Time to Enable Output

Strobe = "1"

15

ns

tED

Time to Disable Output

Strobe = "1"

1.5

ns

tSA

Strobe to Output Delay

20

ns

tsw

Strobe Pulse Width

10

ns

tAA

Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that
the device may be operated at these values.
Note 2: These limits do not apply to PROMs during programming. For the absolute. maximum ratings, refer to the programming instruc-

tions.
Note 3: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee = 5.0V and TA = 25"e.
Note 4: During lOS measurement. only one output at a time should be grounded. Permanent damage may otherwise result.

5·8

c

~

Bipolar PROMs

3:
.....

C7I

.....

W
......

c

NA1'IONAL

DM7573/DM8573 1024-bit field-programmable read only memory
general description

state,! a 9V level is applied to the most significant
address input, Pin 15. This feature will allow a.
much more complete test to be made before a part
is shipped, thus minimizing customer returns.

The DM7573/DM8573 is a field-programmable
read-only memory organized as 256 four-bit
words. Selection of the proper word is accomplished through the eight select inputs. Two overriding memory enable inputs are provided; when
either or both of the enable inputs are taken to a
high state, all the outputs will be turned off. A
logical "1" has been built into each bit locati-Qn: A
logical "0" can be programmed into any bit by
selecting the proper word, disabling the chip, and
applying a programming pulse to the proper
output.

features
• Can be programmed in 1 sec (50% logical 1is;
50% logical D's)
• Pin compatible with SN54187/SN74187
• Can be programmed after being connected in a
system
• Outputs can be fully tested before programming
400mW
• Typical power dissipation
60 ns
• Propagation delay

An additional feature of the DM7573/DM8573 is
that its outputs can be tested. in the logical "0"
state without permanently programming the memo
ory. In order to place all outputs in the logical "0"

logic and connection diagrams

llZ4-"TMEMD~Y

CELL

'hU
IllEMO"YMATRIX·

"MARY

SELECT

MeMORY
ENAIU

Az

171

A,

OJ

Au

151

JME,o,lg:I"~~~:r::)---tf-----ti~---..,..l-----,

lMEzoif41

PiIIUI)"Vcc PiIICllzSIP
OUTPUTS

Dual-ln·Line Package

Order

Numbe~ DM7573D
or DM8573D

See Package 3
Order Number DM8573N

See Package 15

TOP VIEW

5·9

3:

00
C7I

.....

W

('It)

.....

It)

00

:!
c

absolute maximum ratings(Note

operating conditions

1)

MIN

........
('It)

.....
.....
:!
It)

c

Supply Voltage
hlput Voltage
Output Voltage
Storage Temperature Range

7.0V
S.5V 112V on Pins 13. 141
5.5V (25V for programmingl
_65°C to +150°C
Lead Temperature (Soldering, 10 sec)
300"e

electrica Icharacteristics(Note
PARAMETER

MAX

UNITS

Supply Vol tage IV eel ,
DM7573

4.5

5.5

Volts

DM8573

4.75

5.25

Volts

Temperature (T A)
DM7573

-55

+125

°e

DM8573

0

70

DC

MAX

UNITS

2)

CONDITIONS

MIN

TYP

Logical "1" Input Voltage

Vee

~ Min

Logical "0" Input Voltage

Vee

~

Min

Logical "1" Output Current

Vee

~

Max. Vo

"a" Output Voltage

Vee

~

Min. 10

Vee
Vee

~

Max. V ,N
Max. V ,N

~

~

~

204V
5.5V

40
1

jJ.A
mA

Vee

~

Max. V ,N

~

Oo4V

-1

mA

110

mA

Logical

Logical "1" Input Current

Logical

"a"

Input Current

2.0

V
0.8

~

~

4.0V

50

004

16 mA

V
jJ.A
V

Supply Current

Vee~Max

I nput Clamp Voltage

Vee

Propagation Delay to a Logica!
"a" from Address to Output.

Vee = 5.0V
T A = 25°C

60

ns

= 5.0V

28

ns

60

ns

28

ns

~

Min. liN

82
~

-1.5

-12 mA

V

tpdO

Propagation Delay to a Logical
"a" from Enable to Output.

Vee

T A ~ 25°C

tpdO

Propagation Delay to a Logical
"1" from Address to Output.

Vee

~

5.0V

T A ~ 2.5°C

tpd1

Propagation Delay to a Logical
"1" from Enable to Output.

Vee ~ 5.0V
TA = 25°C

tpd1

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The. table
of "Electrical Characteristics" provides conditions f_or actual device operation.

Note 2; Unless otherwise specified minImax limits apply across the _55° to +125°C temperature range for the DM7573 and
across the DoC to 700 e range for the DM8573. All typicals are given for Vee == 5.0V and T == 25°C.

A

5-W

o

programming procedure
The DM7573/DM8573 is manufactured such .that
the outputs are high for all addresses. To program
a logic zero (low output level I. the following procedure should be followed:
.

should be limited to 25V; the current should
be limited to 70 mA. Apply the pulse as
shown in the diagram. A reduction in current of approximately 15 mA indicates the
bit is programmed.

1. Apply aVec voltage of 5.0V and select the
word to be programmed using address inputs
2. Apply a high level (logic 1) to either or both
of the ENABLE inputs (Pins 13 and 14l.

4. To verify that the bit has been programmed,
apply a logic zero to both of the enable
inputs and check for a low level on the programmed output.

3. Apply a programming pulse to the output
where a low .Ievel is desired. The voltage

5. Advance to the next output and/or word,
programming only one bit at a time.

A, -Ao.

Vcc·$·DV

AOORESS
INIUTS

{.,
:
•

..

OM1513J
OMl5Jl

OPEN OR {ME,
LOGIC I

MEz _

1 ' - _. ._

......

GN'

Programming Pulse

Programming Connections

board programming
The DM7573/DM8573 possesses added flexibility
i.n that it can be programmed after it has already
been connected in a system. Whether soldered to a
printed circuit board or socketed, if the procedure
described below is followed the units may be programmed even though their outputs are connected.

logical "1". Because the decoder outputs are
active-low, the ENABLE input of the device to be
programmed is operated at 6V. The other
ENABLE inputs reach 9V, normally a prohibited
level, but in this case the circuit was designed to
use the 9V to prevent the outputs from being
programmed.

As shown in the diagram the decoder used to
select the appropriate package must be operated at
voltage levels which are 6 volts higher than normal.
The outputs of the decoder therefore range between about 6V for a logical "0" and 9V for a

Although all common outputs receive the programming pulse, only the memory whose ENABLE input is at the 6V level is programmed.

r-:--_

'00

bL ___ ,

II
I

SELE.CTEII
auIP T-IV

~"

I

--"-

I
I
I

,.....

_...J~

OMJS7J1

QMl573

I
I ENA8LE
I
I
I

DEI:QOER

i~ 1

....,...

I ENAI
I
I
I
I
I
I
I EMA8l.1

DM7il31

."""

.
-"-

....,.

0Ml'5l3/

I

'-----r--·-'.0

5-11

'

.,"'QIIIA

Iz"'ZOmA

!:
.....
C1I
.....

W
......

c
!:
00

C1I
.....

W

~

Bipolar PROMs

NATIONAL

DM7574/DM8574 TRI-STATE®1024-bit
field-programmable read only memory
general description
ory. In order to place all outputs in the logical "0"
state, a 9V level is applied to the most significant
address input, Pin 15. This feature will allow a
much more complete test to be made before a part
is shipped, thus minimizing customer returns.

The DM7574/DM8574 is a field-programmable
read-only memory organized as 256 four-bit
words. Selection of the proper word is accomplished through the 'eight select inputs. Two overriding memory enable inputs are provided; when
either or both of the enable inputs are taken to a
high state, all the outputs go to the high impedance
state. A logical "1 " has been built into each bit'
location. A logical "0" can be programmed into any
bit by selecting the proper word, disabling the
chip, and applying a programming pulse to the
proper output.

features
• Pin compatible with SN54187/SN74187
• Can be programmed after being connected in a
system
• Outputs can be fuliy tested before programming
400mW
• Typical power dissipation
60ns
• Propagation delay

An additional feature of the DM7574/DM8574 is
that its outputs can be tested in the logical "0"
state without permanently programming the mem-

logic and connection diagrams

1124-IITMEMIIRYCELL

3211%

MEMORY MATRIX

BINARY

SELECT

Az

(7)

Al

(I)

AD

(5)

JME1~1~1"~==r:)---t-I-----rr----It----1

MEMORY
ENABLE tME2

114J

Pin(16}~Vcc

I'in(ll~

omON 1

GilD

OUll'UTI

Dual-In-line Pac;kage

Order Number DM7574D
orDM8574D
See Package 3
Order Number DM8574N
Se. Package 15

.N.
TOP VIEW

5-12

absolute maximum ratings(Note

1)

operating conditions
MIN

Supply Voltage
7.0V
Input Voltage
5.5V (12V on Pins 13,14)
5.5V (25V for programming)
Output Voltage
Storage Temperature Range
_65°C to +150°C
Lead Temperature (Soldering, 10 sec)
300°C

electrical characteristics(Note
PARAMETER

MAX

UNITS

Supply Voltage (Vee)
DM7574

4.5

5.5

Volts

DM8574

4.75

5.25

Volts

Temperature (T A)
DM7574

-55

+125

°e

DM8574

0

70

°c

MAX

UNITS

2)

CONDITIONS

Logical "1" Input Voltage

Vee = Min

Logical "0" Input Voltage

Vee = Min

Logical "1" Output Voltage

Vee

= Max,

Logical "0" Output Voltage

Vee

= Min, 10 = 16 rnA

High·Z Output Current

Vee = Max, V OUT = 2AV, O.4V

Logical "1" Input Current

Logical "O"lnput Current

Vee

Supply Current

Vee = Max

Input Clamp Voltage

Vee = Min,.IIN

Propagation Delay to a -Logical
"0" from Address to Output,

TA

MIN

TVP

V

2.0
0.8
10

=-2.0 rnA

V

V

2.4
0.4

V

±40

iJ.A

Vee = Max, VIN = 2AV
Vee = Max, VIN = 5.5V

40
1

IJ.A
rnA

= Max, VIN = OAV

-1

mA

110

rnA

82
=;

-12 rnA

Vee =5.0V
25°C

60

Vee = 5.0V
= 25°C

28

Vee = 5.0V
T A = 2.5°C

60

= 5.0V

28

=

-1.5

V

85

ns

tpdO

Propagation Delay to a Logical
"0" from Enable to Output,

ns

TA

tpdO

Propagation Delay to a Logical
"1" from Address to Output,

85

ns

tpdl

Propagation Delay to a Logical
"1" from Enable to Output,

Vee
TA

=;

ns

25°C

tpo1

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temp'erature Range" they are not meant to imply that the devices should be operated at these limits. The table
of "Electrical Characteristics" provides conditions for actuai device operation.
Note 2: Unless otherwise specified min/m~x limits ,apply across the -55° to +125° C temperature range for the DM7574 and
across the O°C to 10°C range for the DM8574. All typicals are given forVCC =; 5.0V and T A = 25"C.
.

5·13

III

programming procedure
The DM7574/DM8574 is manufactured such that
the outputs are high for all addresses. To program
a logic zero (low output level), the following pro·
cedure should be followed:

should be limited to 25V; the current should
be limited to 70 rnA. Apply the pulse as
shown in the' diagram. it. reduction in current of approximately 15 rnA indicates the
bit is programmed.

1. Apply aVec voltage of 5.0V and select the
word to be programmed using address inputs
A7 -Ao.
2. Apply a high level (logic 1) to either or both
of the ENABLE inputs (Pins 13 and 14).

4. To veri tv that the bit has been programmed,
apply a logic zero to both of the enable
inputs and check for a low level on the programmed output.

3. Apply a programming pulse to the output
where a low 'level is desired. The voltage

5. Advance to the next output and/or word,
programmin'g only one bit at ,a time.
Vce

ADDR'
SS{
INPUTS

?

..
•

"s.ov

DM15141
DMB574

OPEN OR {M"
r--~-- DUTY CYCLE

LOGIC 1 ME2

<50%,-----1

1~~t,.S;5ps

.N.
Programming Pulse

Programming Connections

board programming
The DM7574/DM8574 possesses added flexibility
in that it can be programmed after it has already
been connected in a system. Whether soldered to a
printed circuit board or socketed, if the procedure
described below is followed the units may be programmed even though their outputs are connected.

logical "1 ". Because the decoder outputs are
active-low, the ENABLE input of the device to be
programmed is operated at 6V. The other
ENABLE inputs reach 9V, normally a prohibited
level, but in this case the circuit was designed to
use the 9V to prevent, the outputs from being
programmed.

As shown in the diagram the decoder used to
select the appropriate package must be operated at
voltage levels which are 6 volts higher than normal.
The outputs of the decoder therefore range between about 6V for a logical "0" and 9V for a

Although all common outputs receive _the programming pulse,only the memory whose EN·
ABLE input is at the 6V,Ievei is programmed.
Yo<

r----.l:sL. ___ ,
Vee ",.
ftLECTED
OUTPUT-iV

HeODER

I
I
I

_"

I

i---i-1r-J....

DM157.t1
0111514

I ERAIL

I
I
I

~I

-"0.75141
....14

I E!WABU
I
I

I

-I

I
I
I ENAILE

...,"

0II7514J.

I

..

I

L.----1"-----'

,

5-14

_...r'L

c

Bipolar PROMs s:....

~

U'I

:::I
......
c

NAll0NAL

s:00
U'I

DM7577/0M8577 256-bit programmable read only memory
general description
The DM7577/DM8577 is a field-programmable, 256-bit,
read only memory organized as 32 words of 8 bits each.
This monolithic, ·high-speed, transistor-transistor-Iogic
(TTL) memory array is addressed in 5-bit binary with
full 'on-chip decoding. An overriding memory-enable
input is provided which, when taken high, will inhibit
the function causing all eight outputs to remain high.
The organization is expandable to 1,856 words of n-bits
with no additional output buffering.

output for that -bit is permanently programmed to provide a low logic level. Outputs never having been altered
may later be programmed to supply a low-level output.
Operation of the unit within the recommended operating
conditions will not alter the memory content.
The mask-programmable DM5488/0M7488 can be used
to replace the OM7577 /DM8577 as they are functionally and mechanically identical.

The address of an 8-bit word is accomplished through
the buffered binary select inputs in coincidence with a
low logic lEivel at the enable input. Where multiple
DM7577/DM8577 devices are used in a memory system,
the· enable input allows easy decoding of additional
address bits.

features
• Field programmable for custom or prototype memories
• Mask-programmable DM5488/DM7488 is a direct
replacement for the DM7577/DM8577
35 ns
• Typical access time
• Organized as 32 words of B-bits each
• Ideal for microprogramming and code converters
• Open-collector outputs are easily expanded
• Fully-decoded buffered inputs
• Fully compatible with most TTL and DTL circuits
• Pin compatible with SN74188A

Data can be electronically programmed, as desired, at
any of the 256-bit locations of the DM7577/DM8577
in accordance with the programming procedure.specified.
Prior to programming, the memory contains a high-Iogiclevel output condition at all 256 bit locations. The programming procedure open-circuits nichrome links which
results in a low-logic-level output at selected locations.
The procedure is irreversible and, once altered, the

connection diagram
Dual-In-Line Package
BINARY SELECT

ViC

ENABLE

11.

.

VI

OUTPUT
VB

G

15

V2

V3

11

13

14

V5

V4

11

y.

OUTPuts

TOP VIEW

Order Number DM7577D
Dr DM8577D

See Package 3
. Order Number DM8577N

See Package 15

5-15

10

V)

,

:::I

....an....
co

~
C
.......

........
an

....
~

absolute maximum ratings

operating conditions

(Note 1)

7.0V
5.5V
5.5V
-55°e to +150o e

Supply Voltage, Vee
Input Voltage
Output Voltage
Storage Temperature Range

Supply Voltage (Vee)
DM7577
DM8577
T emperatu re (T A)
DM7577
DM8577

c

MIN

MAX

UNITS

4.5
4.75

5.5
5.25

V
V

-55
0

+125
+70

°e
°e

High·Level Output Voltage

5.5

V

Low-Level Output Current

12

rnA

recommended conditions for programming
CONDITIONS

MIN

MAX

TYP

UNITS

Supply Voltage, Vee

5.0

5.5

V

Input Voltage
Low Level
High Level

0
2.4

0.5
5.0

V
V

Programming Pulse Amplitude

20

22

V

Programming Pulse Rise Time

1.0

Programming Pulse Current Limit

100

Programming Pulse Width

10

Case Temperature

25

electrical characteristics

Vee

5.0

20

= 5V, TA = 25°C,

PARAMETER

10

/1S

200

mA

50

ms

75

°c

unless otherwise noted.

CONDITIONS

High Level Input Voltage (V'H)

MIN

TYP

MAX

V

2

Low Level Input Voltage (V'L)

= Min,

= ~12

I,

mA

0.8

V

~1.5

V

Input Clamp Voltage (V,)

Vee

High Level Output Current (lOH )

Vee = Min, V'H ~ 2V,
V'L = 0.8V, V OH = 5.5V

100

Low Level Output Voltage (VOL)

Vee ~ Min, V'H ~ 2V
V'L = 0.8V, IOL ~ 12 mA

0.4

Input Current at Maximum Input Voltage
(I,)

Vee ~ Max, V,

= 5.5V

High Leve) Input Current (I'H)

Vee

~

Max, V,

= 2.4V

Low Level Input Current (I,d

Vee

~

Max, V,

~

Supply Current, All Outputs High (l eeH )

Vee ~ Max (Note 2)
Vee

~

1

40
~1

O.4V

Supply Current, All Outputs Low (l eeL )

Max (Note 3)

UNITS

/1 A
V

mA

/1 A
mA

50

80

mA

82

110

mA

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.

Note 2: leCH is measured with all inputs at 4.5V, all outputs open.
Note 3: leel is measured with enable input grounded, all other inputs at 4.5V. and all outputs open. The typical value shown is for the worst-case
condition of all eight outputs low at one time. This condition may not be possible after the device has been programmed.
Note 4: For conditions shown as min or max, use the appropriate value specified under recommended operating conditions.

5·16

C

switehihg eharaete r,isties

Vee

....s:

=5V, TA = 25°C

C1I

FROM

PARAMETER

TO

....

CONDITIONS

MIN

TYP

MAX

UNITS

CL = 30 pF to GND.
R L t =400ri to Vee.
RL2 = 600n to GND'

22

35

ns

(INPUT)

(OUTPUT)

Propagation Delay Time.
Low to High Level Output (tPLH)

Enable

Any

Propagation Delay Time.
High to Low'Level Out,put (tPHd

Enable

Any

CL = 30 pF to GND.
R Lt =400n to Vee.
RL2 = 600n to GND

15

35

ns

Propagation Delay Time.
Low to High Level Output (tPLH)

Select

Any

CL =30 pF to GND.
RLl = 400n to Vee.
RL2 = 600n toGND

35

50

ns

Propagation Delay Time.
High to Low Level Output (tPHd

Select

Any

CL = 30 pF to GND.
RLl = 400n to Vee.
RL2 = 600n to GND

35

50

ns

C

programm ingproeedure
is 20 ms; however. 10 ms will program a high percentage of devices.

1. Apply steady-state supply voltage IV ce = 5.0V,
GND = OV) and address the word to be programmed
with ,speCified input voltages.
2. Disable the outputs by applying a high logic level to
the enable input.

The bit programmed may be verified by checking
the output for a low logic level after the enable input
reaches a low logic level.

3. Only one ·bit location is programmed at a tim~. Open
circuit all outputs except the one to be programmed
'
as a low logic level.

5. Repeat steps 2 through 4' for each output of this
address to be programmed as a low level.

4. Apply the specified programming pulse to the output
to be programmed. The recommended pulse width

6. Advance to next address location and repeat steps
2 through 5.

ae test circuit and switching time waveforms

ADDRESS

Tir"'

~'_':Hr: -}: .r•• v

~

-"~:.. r-

{:L

S.DV

FROM
DU,T'UT
UNDER
TEST

OUTPUT

'

"

Re>

-= R"

....
......

OUTPUT

.,....J" . v

\I..I.!'.5_V_ _ _ _ _

Input Wlveforms Ire supplied by pulse genentars hiving the following char.ett.ista:
t, s: 10 nl, tf S I. ns, PAR:; 1 MHz, PDC = 50%, Amplitude'" 3.GY, .lICIlo 11 50S!.

5-17

S:.
00

........C1I

~

Bipolar PROMs

NA110NAL

DM7578/DM8578 TRI-STATE® 256-bit programmable read only memory

general description
The procedure is irreversible and, once altered, the output for that bit is permanently programmed to provide a
low logic level. Outputs never having been altered may
later be programmed to supply a low-level output.
Operation of the unit within the recommended operating
_conditions will not alter the memory content.

The DM7578/DM8578 is a field-programmable, 256-bit,
read only memory organized as 32 words of 8 bits each.
This monolithic, high-speed, transistor-transistor-Iogic
(TTL) memory array is addressed in 5-bit binary with
full on-chip decoding. An overriding memory-enable
input is provided which, when taken high; will inhibit
the function causing all eight outputs to remain in the
high impedance (Z) state.

The mask-programmable DM7598/DM8598 can be used
to replace the DM7578/DM8578 as they are functionally and mechanically identical.

The address of an 8-bit word is accomplished through
thebiJffered binary select inputs in coincidence with a
low logic level at the enable input. Where multiple
DM7578/DM8578 devices are used in a memory system,
the enable input allows easy decoding of additional
address bits. The TRI-STATE outputs eliminates the
need for external pull-up resistors, and provides good
capacitance drive capability.

features
• Field programmable for custom or prototype memories
• Mask-programmable DM7598/DM8598 is a direct
replacement for the DM7578/DM8578.
35 nS
• Typical access time
• Organized as 32 words of 8-bits each
• Ideal for microprogramming and code converters
• TRI-STATE outputs are easily expanded
• Fully-decoded buffered inputs
• Fully compatible with most TTL and DTL circuits
• Pin compatible with SN74188A

Data can be electronically programmed, as desired, at
any of the 256-bit locations of the DM757B/DM8578
in accord ance with the prcigramm ing procedu re specified.
Prior to programming, the memory contains a high-Iogiclevel output condition at all 256 bit locations. The programming procedure open-circuits nichrome links which
results in a low-logic-level output at selected -locations.

connection diagram
Dual-In-Line Package
BINARY SELECT

Vee

ENABLE
G

116

OUTPUT
V8

15

13

14

11

12

10

2

.

VI

V2

V3

Y5

V4

v,

OUTPUTS
TOPVIEW

Order Number DM7578D or DM8578D

See Package 3
Order Number DM8578N

See Package 15

5-18

C

absolute maximum ratings

operating conditions

(Note 1)

7.0V
5.5V
5.5V
-55·C to +150·C
3OO·C

Supply Voltage. VCC
Input Voltage
Output Voltage
Storage Temperature Range

Lead Temperature (Soldering. 10 seconds)

Supply Voltage (VCC)
DM7578
DM8578
Temperature (TA)
DM7578
DMB578
High·Level Output Voltage

MIN

MAX

UNITS

4.5
4.75

5.5
5.25

V
V

+125
+70
5.5

·C
·C

12

mA

-2.0
-5.2

mA
mA

-55
0

V

Low-Level Output Current

(I0L)

!:
~
0'1

at
......
C

!:
00
0'1

at

High-Level Output Current

(I0H)
DM7578
DM8578

recommended conditions for programming
CONDITIONS

MUll

TYP

MAX

UNITS

Supply Voltage (Vee)

5

5.5

V

Input Voltage
Low Level
High Level

o

0.5
5

V
V

Programming Pulse Amplitude

20

22

V

Programming Pulse Rise Time

1

Programming Pulse Current Limit

100

Programming Pulse Width

10

Case Temperature

25

electrical characteristics

2.4

5

10

20

J1S

200

mA

50

ms

75

DC

(Note 2)

PARAMETI:R

CONDITIONS

MlfII

TYP

Low Level Input Voltage '(Vld
Input Clamp Voltage (Vd

Vee'" Min; 11 ;-12 mA

High Level Output Voltage (V OH )

Vee; Min. V IH ; 2.0V.
VII. ; a.av. 10H ; Max

Low Level Output Voltage (VOl.)

Vee'" Min. V IH ; 2.0V.
VII. ; 0.8V. 101. ; Max

Off State, (High Impedance State) Output
Current{lo (OFF))

Vee; Max. V IH ; 2.0V.
Vo ;2.4V
Vo ;0.5V

at Maximum Input Voltage (II)

Vee; Max. VI ; 2.4V

Low Level Input Current {lId

Vee; Max. VI ; 0.4V

Short Circuit Output Current (los) (Note 3)

Vee; Max

Supply Current {led

Vee; Max (Note4)

0.8

V

'-1.5

V

V

2.4

Vee; Max. VI; 5.5V

High Level Input Current (lIH)

UNITS

V

2

High Level Input Voltage (V IH)

Input Current

MAX

0.4

V

40
--40

J.lA
J.lA

1

mA

40

-30
82

J.lA

-1

mA

-70

mA

110

mA

Note 1: "Absolute Maximum Ratings" ate those values beyond which the safety of the device cannot be guaranteed. Except for ··Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless othelWise specified minimax limits apply across the -5SoC to +12SoC temperature range for DM7578 and across the OoC to

+70·C range for the DM857B. All typicals are given for VCC = 5.0V'and TA = +2SoC.
Note 3: Duration of the short·circuit should not exceed one second. Only one output at a time should be shorted.
Note 4: ICC is measured with all input. at 4.SV. all outputs open.
5·19

III

Je

It)

eo
~

,0

~

It)
,....

~

0

switching characteristics

Vee =5V, TA = 25'C

FROM
(INPUT)

TO
(OUTPUT)

Propagation Delay Time,
Low to High Level
Output (tPLH)

Select

Any

Propagation Delay Time
High to Low Level.
Output (tPHd

Select

Output Enable Time to
High Level (tzH)

PARAMETER

CONDITIONS

MIN

TYP

MAX

RL =40011,
CL = 50 pF

35

50

ns

Any

RL = 40011,
CL = 50 pF

35

50

ns

Enable

Any

RL = 40011,
CL = 50 pF

19

35

ns

Output Enable Time to
Low Level (tzd

Enable

Any

RL =40011,
CL = 50 pF

17

35

ns

Output Disable Time
from High Level (tHZ)

Enable

Any

RL = 40011,
CL = 5 pF

11

35

ns

Output Disable Time
from Low Level (tLZ)

Enable

Any

RL =40011,
CL = 5pF

21

35

ns

UNITS

programming procedure
1. Apply steady-state supply voltage (Vee = 5.0V,
GND = OV) and address the word to be programmed
with specified input voltages.
2. Disable the outputs by applying a high logic level to
the enable input.
3. Only one bit location is programmed at a time: Open
circuit all outputs ljixcept the one to be programmed
as a low logic level.
4. Apply the specified programming pulse to the output
to be programmed. The recommended pulse width is

20 ms; however, 10 ms will program a high percentage
of devices.
.
The bit programmed may be verified by checking the
output for a low logic level after the enable input·
reaches a low logic level.
5. Repeat steps 2 through 4 for each output of th is
address to be programmed as a low level.
6. Advance to next address location and repeat steps 2
through 5.

ac test circuit and switching time waveforms

s~~:~

OUTPUT

R,

....

UNDER

TEST

r

-..

"

t.Ok

Ov-J

'.

Vee

TEST
POINT

FROM
OUTPUT

,.OV:=€ - - - - ""\
1.5V

1.5V

' - ____ _

"j
"';5.

v,
O

~-lr-

J.5V .

J.OY

,.
..

ENABLE

OV
",l.!iV

-

V

Cl includes probe and iig capac:itanc;e.
All diodasar.'N3064.

OH

OUTPUT

",'.5V

J

tzc

r-j

\

OUTPUT

vo,

1.5V

\".5V

-

"ILZ-

O.5V

\1

h
Ij

I--

t'H

V~

I

!

D.5V

~

D.5V

-

tH'

Input WfI/tfOrmslre IIIpplied by pulse pnlll'atois hIVing tilt followinl characteristics:
.... $10 oS, I, $10 ns, PAR;;, MHz. PDC '" 50%, Amplitude'" 3.0V, and Zo '" son.

5-20

~

Bipolar PROMs

Advance Information

NAll0NAL

o
~
(J1

en

N
N
N

.......

o

~

DM75S222/DM85S222 TRI-STATE® 2048-bit PROM with output latches

00

general description

N
N
N

(J1

fJ)

These TTL· compatible memories are organized as 256
words by 8 bits. When the strobe input is at a logical
"1" level the memories function in the conventional
manner with the enable input determining whether the
outputs present the contents selected by the address
inputs or are turned "OF F."

to go back to a logical "0." Additional bits may be
programmed to a logical "1," however.

features
• Schottky clamped for high speed systems
•

When the strobe input is at a logical "0" the outputs
are latched into the state they were in just prior to the
strobe going low. The outputs remain in this condition
until the strobe is again taken to the logical "1" state
regardless of the .state of the address or enable inputs.

High speed
Address to output delay-typical
Enable to output delay-typical
Strobe to output delay-typical

logic and connection diagrams

0-:-

ADDRESS
BUFFER
AND
DECODE

0-

-·
·
-·

-

r-.

B·BIT
lATCH

256 X B
ARRAY

.

8 OUTPUT

-:-0

.

DRIVERS

~

I-

I

1

STROBE

o TYPE
LATCH
ENABlfo--c

Dual~ln-Line

T
20

AT
19

A6

A5

1B

17

EN

Package

STROBE OUTS OUT1 OUT 6 OUT 5

16

15

14

13

11

12

-

r

6
AD

A1

A2

A3

15 ns
20 ns

• PNP inputs reduce input loading
• Output latches simplify system use
• 20 pin, 300 mil package for high density
• Ali dc and switching characteristics may be measured
prior to programming PROMs
• Pin compatible with DM54S271/DM54S371

PROMs are, shipped from the factory with a logical
"0" in ali locations. A logical "1" may be programmed
into any selected locations by following the program·
ming instructions. Once programmed, it is impossible

ADDRESS
INPuts

35 ns

A4

1

TOP VIEW

Order Number DMB5S222N
See Package 16A

5·21

8

9

OUT lOUT 2 OUT 3 DUT4

.to
GND

OUTPUTS

absolute maximum ratings
Supply Voltage (Note 2)
Input Voltage (Note 2)
Output Voltage (Note 2)

-Q.5V to +7.0V
-1.2V to +5.5V
-Q.5V to +5.5V
-65°e to +150"e
300"e

Storage Temperature Range
Lead Temperature (Soldering,l 0 seconds)

dc electrica I characteristics

Supply Voltage (Vee)
DM75S222
DM85S222
Ambient Temperature (T A)
DM75S222
DM85S222

MAX

UNITS

4.5
4.75

5.5
5.25

V
V

-'55
0

+125
+70

°e
°e

Logical "0" Input Voltage

0

0.8

V

Logical "1" Input Voltage

2.0

5.5

V

CONDITIONS

Logica) "1" Input Current

MIN

(Note 3)

PARAMETER
I'H

operating conditions

(Note 1)

MIN

TYP

MAX

V'N= 2.7V

25

IlA

VIN = 5.5V

1.0

rnA
Il A

IlL

Logical "0" Input Current

V'N = 0.45V

-250

V CL

Input Clamp Voltage

liN = -18 mA

-1.2

VOL

Logical "0" Output Voltage
DM75S222

IOL=12mA

DM85S222

V

0.50

V

0.45

V

Logical "1" Output Voltage

V OH

los

UNITS

DM75S222

IOH = -2.0 mA

2.4

V

DM85S222

IOH = -6.5 mA

2.4

V

Output Short Circuit Current

Vo = OV (Note 4)

-30

-100

mA

-50

50

Il A

100

165

mA

TYP

MAX

Vcc=Max
loz

TRI·STATE Output Current

Icc

Maximum Supply Current

switching characteristics
PARAMETER

0.45V::; Vo::; 2.4V

(Note 3)
CONDITIONS

MIN

UNITS

tAA

Address to Output Delay

Strobe = "1"

35

ns

tEA

Time to Enable Output

Strobe = "I"

15

ns

tED

Time to Disable Output

Strobe = "1"

15

ns

tSA

Strobe to Output Delay

20

ns

tsw

Strobe Pulse Width

10

ns

Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that
the device may be operated at these limits.
Note 2; These limits do not apply to PROMs during programming. For the absolute maximum ratings, refer to the programming instruc~
tions.
Note 3: These limits apply over the entire operating range uniess' stated otherwise. All typical values are for Vec ::: S.OV and T A = 2S<> C.
Note 4: During lOS measurement, only one output at a time should be grounded. Permanent damage may otherwise result.

5·22

~

MOS ROMs

NATIONAL

MM3501 1024-bit read-only memory
general description
The MM3501 is a 1024-bit read-only memory programmed in a 128 word by 8 bit format. It is an
MOS monolithic integrated circuit utilizing Pchannel enhancement mode technology. The fixed
program memory is specified by the customer and
customized by modifying one mask in the fabrication process. This results in a fast turn-around, low
cost custom memory.

•

115 mW typical static operation

•

Low power consumption

• Bipolar compatible outputs

applications
• Microprogramming

features

• Code conversion
• Table lookup

". Chip select
• 1.5/1s typical access time

• Control logic

logic and connection diagrams

Dual-In-Line Package

o
E

C

o
o
E
CHIP SElECT READ"

o

1 2 ] 4 5 6 7

'---..,-----J

·When chip select read isat Vss the

OUTPUTS

outputs are f1031111g,

Order Number MM3501J

See Package 1.1
Order Number MM3501N

See Package 1B

switching time waveforms
Access and Chip Select Times

I------- T

ovl
~

INPUT ADDRESS
-15V

OUTPUT

•

lOGIC
LOGIC

I•

T

-----I

:-1_ _ _ _~I
J

LT;8.1DIiS

'90"ti.l-----t1,O%

I

I

I

I

"~~'=====+I::Jxb~;;!:::===:ti=~\;"'~'~======

I 1 ' 1 ...____
·T':===~11i;,:===~~f..-'}:=====:
I
TArI TA I
Note: The logic "0," "1" le\lel~ may h~ takpn 10 be (-I.OV, -IOV} or
(-2.llV, -S.OV) respe(.:tively. Guaranteed limits are at -l.OV and -lOY.

Note: For programming information see AN-100.

61

Riseandfalltima-50ns

St"d"d I"d

~~:

:OM:;

3:
3:
w
C1I
o
.....

o"'"
LO
(I)

:e
:e

absolute maximum ratings

All Voltages and Data Input Lines with Respect to Vss
Power Dissipation
Storage Temperature Range
Operating Temperature Range
Lead "Temperature (soldering, 10 sec.)

-30V to +0.3V
250mW
-65°C to +125°C
O°C to +70°C
300°C

electrical characteristics
T A within operating temperature range Voo
unless otherwise noted.

CHARACTERISTIC

= -13V ±1.0V, V GG = -27V ±2.0V, VB = -27V

CONDITIONS

MIN

Input Logic Levels
Logic "0"
Logic "1"

V ss -2.0

Input Capacitance

(Note 4)

Input Leakage

V'N

Output Logic Levels
Logic "0"
Logic "1"

IL
IL

Access Time (T A)

Output Current
Logic "1"
Logic "0"
Logic "1"

TYP

(Note 5)

= -10MA
=

V ss -l.0

+10MA

RL = 1.0Mrl,C L = 10pF
(Notes 2 and 3, See Waveform)
V OUT
V OUT
VOUT

=

1.5

-4.6V (Forced) (V B= V OD )
(Forced) (Note 6)
-10V (Forced) (Note 6)

= -1.0V
=

1.6
-0.15
0.30

= OV

MAX

Vss
V ss -9.0
7.0

= -15V

±2.0V, Vss

(GND),

UNITS

V
V

15

pF

1.0

MA

Vss
V ss -lO

V
V

4.0

MS

mA
mA
mA

-0.24
0.85

Supply Current Drain

V DD = -14V, VGG
(Note 2)

100

IGG
Power Consumption

= -29V

(Notes 1 and 2)

115

Note 1: Exclusive of 18 (load current)

Note
Note
Note
Note
Note

2:
3:
4:
5:
6:

TA : : ; +25~C.
Sample tested.
Guaranteed by design:
Address and chip select inputs all pins grounded except the one under test
VOO = ~12V, VGG = -25V (wor~t case condition of measurement)

6-2

6.5
4.0

mA
mA

215

mW

~

MOS ROMs

NAnONAL

MM4210/ MM5210 1024-bit read only memory
general description
no clocks requ ired
output wire AND
capability
• Chip enable output control.

The MM4210/MM5210 is a 1024-bit static read
only memory. It is a P-channel enhancement mode
monolithic MOS integrated circuit utilizing low
threshold technology. The device is a non-volatile
memory organized as 256-4 bit words. Programming of the memory contents is accompl ished by
changing one mask during device fabrication_ Customer programs may be su pplied in a tape, card, or
pattern sel ection format.

• Static operation
• Common data busing

applications
• Code conversion
• Random logic synthesis
• Table look-up
• Character generators
• Microprogramming.

features
• Bipolar compatibility
• High speed operation

500 ns typ

block and connection diagrams

Dual-In-Line Package

SENSE
AMPLIFIERS

INPUTS

OUTPUTS t

USB) Al

INPUT A3

"

Voo

INPUT A2

15

INPUT

lS8 INPUT At

14

INPUT A5

lSB DUTPUT 8 1

13

INPUT As

12

INPUT A7 MSB

~

8 1 (lSB)
A,

a,

A,

OUTPUT 82

,

11

V"

,",S8 OUTPUT 84

J

10

CHIP

V"

a

,

OUTPUT 83

a,
a,

A.

ENABLE
INPUT As

TOPVIEW
CHIp·
ENABLE

"The output is Enabled by applylng
a lOgic "'''10 the Chill Enable line.

tThe outputs are connected to
Voo through an internal MOS
mistorwhenDiSilbled.

Order Number MM4210J or MM5210J

See Package 10
Order Number MM5210N
See Package 15

typical application
256 x 4 Bit ROM Showing TTL Interface

-"v----....

...__,

~--------------~---,,-_-+_ _ _--:-_-"A'iJ 12

a,

1l

},-"

a,

6.8K

OnmL lOGIC

"

*Resistor value CIIn vary from 750U
to 30 k!l depending on speed requiremellts.

"::"

Note: For programming information see AN·100.

6-3

absolute maximum ratings

V G G Supply Voltage
Voo Supply Voltage
Input Voltage
(V ss -20)V
Storage Temperature
Operating Temperature MM4210
MM5210
Lead Temperature (Soldering, 10 sec)

V ss -30V
V ss -15V

< Y'N < (Vss +0.3)

_65°C to +150°C
-55°C to +125°C
O°C to +70°C
300°C

electrical characteristics
TA within operating temperature range, Vss ~ +12V ±5% and VGG ~ -12V ±5%, unless otherwise specified.
PARAMETER

CONDITION

MIN

TYP

MAX

UNITS

Vss -9.0

V
V

+0.4

V
V

Vss -8.0

V
V

Output Voltage Levels

MOSto MOS
Logical "1"
Logical "0"
MOSto TTL
Logical "1"
Logical "0"

1 Mr2 to GND Load

6.8 kl1 to V GG Plus One
Standard Series 54/74 Gate Input

Vss-l.0

+2.4

Input Voltage Levels

Logical "1"
Logical "0"
Power Supply Current
Vss
VGG (Note 1)

Vss -2.0
TA ~ 25°C
19

I nput Leakage

Y'N

I nput Capacitance

f

Access Time (Notes 2, 3)

T A ~ 25°C
(See Timing Diagram)
Vss ~ +12V VGG=-12V

T ACCESS

Output AND Connection

~

~

Vss -12V

1.0 MHz

Y'N ~ OV

MOS Load
TTL Load

25
1

mA
IlA

1

IlA

5

150

500

pF

650

ns

3

8

Note 1: The VGG supply may be clocked to reduce device power without E!ffecting access time.
Note 2: Address time is measured from the change of data on any input or Chip Enable line to the output of a TTL gate.
See Timing Diagram.
Note 3: The access time in the TT~ load configuration follows the equation: T ACCESS = the specified time + (N - 1) (50) n's
where N = number of AND connections.

6·4

I

performance characteristics
Guaranteed Access Time vs
Supply Voltages

fA

1000

'=

Typical Access Time vs
Su pply Voltages

125"C

1000

TA - lO°C

800

-

T.

~25~

~

J

800

~ 600

~ 600

J/.

~

400

.... 400

200

200

iFt 7
'" 1/'1
+~
j--'1D"C
lZS·C

ZS·C

J
10,8

12.0

13.2

10.8

12.0

Vss& VaG IV)

Power Supply Current vs
Voltage

Power Supply Current vs
Temperature

,

T(25'C
24

GUARANTEED
26

y

22

IA

nfiguration follows the equation: T ACCESS = 'the specified time + (N - 1) (50) ns
where N = number of AN 0' connections.

6·18:·'

performance characteristics
Typical Access Time vs
Supply Voltages

Guaranteed Access Time vs
Supply Voltages

TA '" '25°C

1000

1000

TA '" 75"C

800

~

~

r.-Z5=i;

ill

.

600

J

800

~

600

I-

400

125"C

200

'1~J

g

400
200

10.8

13.2

12.0

:.pt+
Icy,

25"C

Vss&VGG (V)

Power Supply· Current vs

Power Supply Current vs

Voltage

Temperature
Vss ""+12.0V
VaG;; -12.0V

T(1 25"C
24

GUARANTEED

E-

26

J;

22

<

13.2

12.0

10.B

Vss & VGG (V)

20

TYPICAl

22

<
E-

0

o 18

j

"\

"

16

r-.....

......

18

14

GUARANTEED

1'\

r-....

lo.B

13.2

12.0

"

TYPICAl'

14

-50 -25 0 25 50 75 100 125

Vss&VGo(V)

TEMPERATURE eCI

timing diagram/address time

+lv

"TL

DV

I

l.OK

.5V

I

INPUT~

E,.--!:_,

DM8810

T

E,.

DV
+12'\1

'OPF

I

I

UK

IO".I..

~

ANY DHlTTl
GATE

-Jv

Fk
E'--

·,v
DV

I

MM42201MM!;i220

~

+12V

>5V
OUTPUTB".

d

v 2D
..-

1.5Y

0
fOUT

.,v
ISV

DV

I
time

6019.>

:E-=

fOUT

15"

typical application

128-8 Bit ROM Showing TTL Interface
-t2V

.,V
'
t

.

v"

"

..
"
..

CHIP

ENABLE
t MODE

COIITADL

v"

UK

6.IK

I,

A,

S.
MM42211JMN!iUO

-{

..

Ai

I,

I,

A,

I,

DMlllD OR DM1812
TIL GATES

A,

A,

v••

"

A,

tSee operating mode note5.

lOR values elln vary from 740 (0 30 kn depending on speed requirements.

OPERATING MODES
128x8 ROM connection
Mode Control - Logic "0"
As
- Logic "1"
256x4 ROM connection
Mode Control - Logic "1"
As
- Logic "0" Enables the odd
(B 1 ___ B7 ) outputs
- Logic "1" Enables the even
(B 2 ___ Bs) outputs_
The outputs are "Enabled" when a logic "1" is
applied to the Chip Enable line_
The outputs are connected to. V DO through an
internal MaS resistor when "Disabled,"
The logic levels are in negative voltage logic notation,

6-2.0

}-

~

MOS ROMs

3:
3:
~

N
N

o

NAll0NAL

l>
m

......

3:
3:

MM4220AE/MM5220AE ASCII"7 to hollerith code converter

C1I
N
N

o

l>

m

general description
The typical application shows a recommended
circuit for re-expansion of the Hollerith code to
twelve lines_

The MM4220AE/MM5220AE 1024-bit read-only
memory has been programmed to convert the
128 entries of the American Standard Code for
Information Interchange in seven bits (ASCII-7) to
Hollerith code (compressed to eight bits)_ The
conversion performed follows the recommendation
of American National Standard ANSI x 3_261970, Hollerith punched card code_-

For electrical, environmental and mechanical details, refer to the MM4220/MM5220 data sheet_

typical application

,

PUle"

.ow

.~

DMAIa

.. , .

.DMUU

11.!!2...

r

.. ,
" ..
.. ,
""
. " ...,.AE .
_ ...u

",.

..

., "

--

,t9"I

1mLO~D

,
,

..

-

FAIIOUTAVAlU.LE

,r'

I"

7L"U

v..

··.

r

, ..

""

. ,+

TmeAL

r-

··"

f'" -'''''

"tM.'ENA'i.E

"Chip En.ble" Lo!ic "'''tD obtain outputs.
Logichvels:
DTLmL (extept ilt MOS/ROM interface). Logic: '" ," +S.OV. NOM, Logic "0" ",ound, NOM.
MOS/ROM inputs and outputs. Logic "'," more negative, Logic: "fI," more positivi.

Order Number MM4220AE/J or MM5220AE/J

See Package 11
Order Number MM5220AE/N

See Pack_lie 1.8

6-2.1

..""

'~

:P-:~

:~
.p--

,1"""AVAI"'"

HOiulUlM'U
IACTIVELfYE

"muADI

w

ct
~

code conversion tables

N

It)

:!
:!
.......
w

ct
o

b7

N
N

~

:!
:!

0

~

0
0

bs
b4 b3 b2 b1

0
0

0

I~
RO

1

0
1
0

1
1

3

0

1

2

0000

0

NUL
12-0--9-8-1

DLE
12-11-9-8-1

SP
NOPCH

0001

1

SCH
12-9-1

DCl
11-9-1

2

STX
12-9-2

DC2

0010
0011

3

0100

1
0

1
0
0

1
1

4

5

1
1

1
0

1

6

7

0
0

@

8-4

P
11-7

8-1

p
12-11-7

!
12-8-7

1
1

A
12-1

Q
11-8

a
12-0-1

q
12-11-8

11~9-2

"
8-7

2
2

8
12-2

R
11-9

b
12-0-2

r
12-11-9

ETX
12-9-3

DC3
11-9-3

#
8-3

3
3

C
12-3

S
0--2

c
12-0-3

s
11-0--2

ECT
9-7

DC4
9-8-4

$

4

11-8-3

4
4

D
12-4

T
0--3

d
12-0-4

t
11-0--3

0101

5

ENQ
0--9-8-5

NAK
9-8-5

%
0--8-4

5
5

E
12-5

U
0-4

e
12-0--5

u
11-0-4

SYN
9-2

&
12

6
6

12-6

V
0--5

f
12-0-6

v

6

ACK
0--9-8-6

F

0110

ETa
0-9-6

8-5

7
7

G
12-7

W
0--6

g
12-0-7

w

7

BEL
0--9-8-7

CAN
11-9-8

8
8

H
12-8

X
0--7

h
12-0--8

x

8

BS
11-9-6

EM
11-9-8-1

)

11-8-5

9
9

I
12-9

Y

9

HT
12-9-5

0--8

i
12-0-9

Y
11-0-8

SUB
9-8-7

*

:

11~8-4

8-2

J
11-\

Z
0--9

j
12-11-1

z

10

IF
0--9-5

;

11

ESC
0--9-7

+

1011

VT
12-9-8-3

12-8-6

11-8-6

11-2

[
12-8-2

k
12-11-2

12-0

FS
11-9-8-4

L
11-3

\

12

FF
12-9-8-4

<

1100

1
12-11-3

12-11

13

CR
12-9-8-5

GS
11-9-8-5

M
11-4

1

1101

m
12-11-4

11-0

1110

14

SO
12-9-87 6

RS
11-9-8-6

15

SI
12-9-8-7

US
11-9-8-7

0111
1000
1001
1010

1111

CD
@

®

CD

(

12-8-5

0--8-3

12-8-4

-

=

11

8-6

>
12-8-3

0--8-6

/

?
0--8-7

0--1

,K

0--8-2
11-8-2

I\@

N
11-5

11-8-7

n
12-11-5

a

-

0

11-6

0--8-5

12-11-6

may be "I"
may be","
The top line in each entry to the table'represents an assigned character (Columns 0 to 7),
The bottom line in each entry is the corresponding card hole-pattern.

6·22

11-0--5
11-0--6
11-0--7

11-0--9

f
:

I

-

11-0--1

DEL
12-9-7

code conversion taltles(con't)

ADD
RESS

OUTPUT COOE
B6 BS B4 B3

AOD_
B2

Bl

0
I
2
3
4
5
6

1

1

0

1

1

0

0

1

1

0

0

1

0

0

0

1

1

0

0

1

0

0

1

0

1

0

0

1

0

0

1

1

1

0

0

0

0

1

1

1

1

1

0

0

1

1

0

1

1

1

0

0

1

1

1

0

7

1

1

0

0

1

1

1

1

8
9
10
11

1

0

1

0

0

1

1

0

1

0

0

1

0

1

0

1

"13
1
15
16
17
18
19
20
21

"23

B B7

1

1

0

0

0

1

0

1

1

0

0

1

1

1

1

1

0

0

1

1

•
1

0

0

1

0

0

1

1

1

0

1

1

0

0

1

1

1

1

0

1

0

0

1

1

1

1

1

1

0

1

1

1

0

0

1

1

0

1

0

0

0

0

1

1

0

1

0

0

0

1

0

1

0

1

0

0

0

1

1

1

0

0

0

1

1

0

0

1

0

0

0

1

1

0

1

1

0

0

0

0

0

1

0

1

1

0

0

0

1

1

0

24
25

1

0

1

0

1

0

0

0

1

0

1

0

1

0

0

1

26

1

0"

0

0

1

1

1

1

27

,
,
,
,

1

0

0

0

1

0

,
,

0

, ,
, ,
, , ",, ,

28
29
30
31
32
33
34
35

1

0
0
0

,
1

0
0
0

0

•

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

37
38
39
40
41
42

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

,

0

0

0

1

0

0

, ,
,
,
,
,
,
,
,
, ,
,
,

341

ROW

, ,

0

0

0

0

, ,
, , ,
, ,
, ,
,
1

0
0

0

0

0

0

0

0

1

0

,
,

"0

0

0

0

0

1

0

,

1
1

0

•

0

"

'2

8

4

2

,
,
,
0

OUTPUT CODE

RESS

BB

B7

B6

43
44
45
4&
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
61_
68
&9
70
71
72
73

0

0

0

7,

0

, ,
,
,
,
, ,
,
,

0
0

0

0

0

0

0

0

0

0

B3

1

0

,
, ,
, ,
,
,
, ,
,
,
, ,

B2

Bl

86
87

0

,

0

,

0

0

0

0

0

0

(I

0

0

0

0

0

0

0

0

0

,

,
, ,

0

ROW

4

2

0

0

0
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

,
,
,
,

0

0

1

0

0

0

0

0

,

0

0

0

,

0

0

0

0

0

0

0

0

0

0

0

0

0

0
0

0

0

0

0

,
,

, ,
, 0
, ,
, ,

0

0

,
0
, ,
,
0
,
0

0

0

,

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

,
,
,
,
,
,
,

0

0

0

0

0

0

,

1

0

0

0

0

,
,
,
,
,
,
,

0

0

76

0

0

77

0

0

78
79
80
81
82
83
84
85

0

0

0

0

0

0

0

,
0
0
0

•

0
0

,
,
,

0

AOD_
RESS

0

88
89
90
91
92
93
94
95
9&
97
98
99
100
101
102
103
104
10§
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127

0

0

75

ROW

BS B.

0

,

,

, , ,
, ,
,
,
,
,
, ,
, ,
,

0

0

0

0

0

0

0

,
,

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

1

0

0

0

1

0

0

0

0

o.

"

6·23

,

0

,
,

0

0

,

0
0

,
,
,
, ,
, ,

0

0

0

i

0

•

0

0

0

0

0

0

0

12

0

0

0

"0

0

1

0

0

0

1

0

0

,

OUTPUT CODE
B6 BS 94 83

0

0

0

0

0

0

0

0

0

0

0

0

, •• ,
, ,
,

0

0

0

1

0

,

,
,
,
,
, ,

BS

o.

.7

0

,

0

0

0

0

0
0

0
0

0
0
0

0
0
0

0

,
,
,
,
,
0

,

,

,
,

1

,

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

,

0

0

0

0

0

,

0
0
0
0
0
0
0
0
0

0

,
,
,
,
1

,
,
,
,

, ,
, ,
, ,
,
, ,
,
, ,
1

1

T

B'

0

0

1

1

0

0

0

0

0

1

0

,
,
,

,
,
, ,
, ,
,
0

0

0

1

0

0

0

0

0

0

0

0

0

0

0
0

0

0
0
0
0

,
,
1

,

,
, ,
,
, ,
, ,
,. ,
0

0

0

0

0

0

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

,
, ,
, ,

,
,
,
,
0

0
0
0

, ,

,

,
,

0
0

0

0

0

0

0

T

0

0

0

0

0

0

0

0

0

0

1

0

0

0

1

0

0

0

0

0

0

, ,

,
, ,
, ,
, , ,

, , ,

0

,

0

0

0

0

1

0
1

9

0

,
0
0
0
0

0

,

, ,
,
, ,
,
1

1

,
,

0

0

,
, ,
0

0

0

0

0

0

,

0

0

0

0

0

0

0

1

0

0

0

0

1

1

0

0

0

0

,

1

0

0

0

0

0

1

0

0

0

0

1

0

0

1

0

1

1

1

"

,2

8

4

2

1

0

~

MOS ROMs

NAll0NAL

MM4220AP/MM5220AP
BCDIC-to-ASCII code converter
general description
The MM4220AP/MM5220AP is used for the conversion of the Binary Coded Decimal Interchange
Code(BCDIC) to the American Standard Code for
Information Interchange (ASCII).

The output is a seven·bit ASCII code, with an
eighth bit generated for even parity.

The input is a seven-bit BCDIC code with the
exception of the parity (check) bit (pin 18) which
is returned to +i2V dc. The alternate set of input
symbols is also shown in the Conversion Table for
reference.

device characteristics
F'or full. electrical. environmental, and mechanical
details, refer to the MM4220/MM5220 1024-J:>it
read only memory data sheet.

typical application

connection diagram
Dual-In-Line Package

-".----------------.........-.,

~v--~--------~=_---+_-t-~-_1~--

A,

M

'"

A,

"

N.C.

A,

U

N.C.

A,

",
=
•
8
~

.

-,

..
..
..
..
..

A,

lo----I-......:..::j21

."
....
""

C(1I0TUS(DI

30',

..

TY"CAL,

JUlies

v"

+ 1 2 V - - - - -. . .- 4 -..."t"~y1_ll_j';:...---."j

''''fllTV

I,

A,

I,

A,

..
..
..
..
..
I,

v"

A,

A,

v..
MO••
I;IIIITROL

.."

1D

UAIU

••

11

"

A,
II.C.

TOPVIEW

DTlmLLOGIC

'"

Order Number MM422DAP/J or MM522DAP/J
See Package 11
Order Number MM522DAP/N
See Package 18

·CHIPEN....LE _ _ _- '
ttlaDECOflTROL------I

tMode Control'" LogiC "0," A8 = logic "1.~'
*ChipEnable=Logic'T'toobtainoutpuI5.

logic Levels:
DTLfTTL ~except at MOStROM interface). Logic "1," +5.0V. NOM. LogiC "0," ground, NOM.
MUS/ROM inputs and outputs. Logic "1," more negative. logic "0," more positive.

6-24

code conversion table
CODE

FUNCTION
INP T

,INPUT

OUTPUT

OUTPUT

C

0

ROM
ADDRESS

BCDle
SYMBOL

0
1
2
3
4

Space

5.
6

7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

Sp-al;e

1

1

2
3
4
5
6
.7
8
9
O.
~o,

@or'

>

0

0
0

~.

.0
0

0
0
.0

4
5

0
0

0
0

6
7

0
0

0
0

8
9

o·

0
0
0
0
0
0
0

2

0
0

0

'"

@

,>

0
0
0

0

0

0
0

1
1
1

22
23

W

W

0

0
0
0

X

X

0

0

24
25
26
27

V

V

0

Z

Z

0
0

33

J
K

34
35
36
37
38
39
40
41
42
43
44

45
46
47
48
49'
50
51

52
53
54
55
56
57
58 ..
59
60
61
62
63

"

0

1
1
1
1

ti

'"-

1
1

0
0
0

0

HT

1

0
0
0

V

v

0
0
0
1
1

1

u

0

1

1

V

0
0
0
0

0

0
0
1
1
0

1

U

LF

0
0
0
0

0

0

,.

0
0
0
0

0
1
1

0

t

0
0
0
0
0
0

0
0
0
0

T

% or\

2

1
1
1

0
0

S

.28
29
30
31
32

4

0
0
0
1
1
1

T

!
I

8

0
0
0

S

J
Blank

A

0
0
0

0
0
0
0
0

/

0
0
0
0
0
0

1

1
1
1
1

0
0
1
1
1

1

1
1
1
1

1

1

0
0
0
0
1
1
1
1

0
0
0
0
0
0
0

0
0
0
1
1
1

0

1

1

0
0
0
0

1
1

r

Q

Q

,

·R

0
0

1

.

,

1

0

1

$

$

,0

1

0

.1

*

0

1

I

0
0

1

)

1

-

a

J
K

0
0

L

L

0

M

M

()

N
D

N

~

:R

D
P

fi

I

.& or'!

&

0
0
0
0

0
1
1
1
1
1
1

1

1
0
0
0
0
0
0
0
0
0
.0

0

,

BCDIC

ASCII
'0.
B
SYMBOL E

,
1
1

1

0

1

0

1
1

1

0

1

1

.0
1
1

1

1

0
0

0

a
a

0
0
0

l'

1

0

0
0
1
1
0
0
1
1
0

0
1
1
0'
0
1
1
0
0
1
1
0
D
1
1
O·
0
1
1

1
0

0

1

B
C

B'

0

1

1

a

C

·0
.0

1

1

0

1
1

0
0

1

0
0

1
1

1
0

1

0

1

1

1

1

1

1

1
1

1

0
0
1

1
0

1
0

1
1

1
1

0
0
0
1
1
1
1

0

D

D

E

E

F

F'

G

G

H

H

I.

I

,

IJ or)

I

<

*

,

·0
0
0
,0

0

1
'1

1

1

~

0

1

1

1

I

a

<

0
O·

1
1
1

1
'1
1

1
1
1

CR

A7

0
1

1
1
0
0
1
1

A6 A5 A4 A3 A2

6-25

b3

b2

b,

1
1
1
1

0
1
1

0

1

1
1
1
1

0
0
0
1
1
0

0
0
1
1
0
0
1
1

0
1
0

1

0
0
0
0
0

1
0
1
0

0
O·

0
1
0

0
1
1

0
0
0

1
0
1
0
1
0
1

0
0
1
1

0

1

0
0
1

1

1
1
1
1
1
1

1
0
1
1

0
0
1
1

0
0
1
1

1

0
1

1
1

0
1
'0

1
1

1
1
1

0

1
1

0
1

0
0

0

1
0

0
0

1

0
1
0
0
0
0

1

1
0
0

0
1

1
1

0
1

0
0
0
1

0

1
0
0
0
0
1
0
1
0
0
1

0
0
0
0
0
1
1
1
1
1
1

0

1
1
1

0
0
0

0
0

1

0

0

1
0
1
0
1
0
1
0

1
1
0
1
0
1

A

b4

0
0

0
1

0

A

b5

0

0

1

bS

1

0
1
1
0
0
1
0
0
1

b7

0
1
1

0
1
1

ASCII

E
P

0
1
0
1
0
1

1

1
0
0

1
1

1
1
1
1

1

1

1

0

0

0

0
O·

0
0

1
1
1

1
1
1

0

0
1
1
1

1

1

0

0
0
0
0
1

1

0

1

0
0

1
1

0
0
1
1

0

0

0

0
1
1
0
1
0

0
1
0
1

0
0

0

1

0
1

0
0
1
0
1

0
0
1
1

0

1

1

a

a
0

0

0
1
0
1

0
0

a

1

0
0

1

0

1

'1

1
1

a
0

0

0
1
0

1

a

1

1

1

0
1
0
1

1

1

0
0

0
0
1

1
1
1

0
.0
0

0
0
1

0
0
1

1

0

0
0
0
0
0
1

0

0

.1

a

0
1

0
1

0
0

1

1

0

A,

B8

B7

B6

1

'1

0

1

0
0

0
1

0
0

1

1
1

a
a
a

0

0
1

1

0

0

0

1

1

1

1
0
1

a
a

1
0

1

0

1
0
0
1

0

0
0
1
1
0
1
1
0
0
1
1

0
1
0

0
0

0
1
1
1

1
0

0

0
0

0

1
1
1
1

0

0
1

0
1

0
1

0
0
0
0
0

0

1
0
1

1

0
1
1
1
0
0

1
1
1
0
1

0
1
0

0

0
0

0

0
1
1

0
0
0
1

1

0
1

0
0
0
0
1

0
0
1
1

1
1
1

1

a

0

0

0
1
0
1
1
1
1

1
0

0

1
1

0

0
0
0
0
0
0
1
1

0
0

0

0
1

0

1
1

1
1
1

1
1

0
1

0
0
0
1
1

0

1

1

1
1

a

.0
1

1
0

1
1

0
0
1
1

1

0

1
1
1
1

0
1
1

0
0
0

1
0
0
0
0
1

B5

B4

B3

B2

B,

1

1

0
1
0
1

0
0
1
1

0
1

a

I

~

MOS ROMs

NAll0NAL

MM4220BL/MM5220BL baudot-to-ASClicode converter
general description
The MM4220B l/MM5220BL is used for conversion
of the Communications Set Baudot code to the
American Standard Code for Information Interchange (ASCII l-

Case Bit. If the bit is. externally supplied, the
·feedback. and latch circuits can be deleted (as
shown with the X's). .
The accompanying table is applic~ble for the code
conversion scheme as. shown' (or its' alternate)
rather than for the device itself. The input 'and
output codes are defined at the'TfL'gates with the
'Iogic trues high (Logic '''1'' = +5 volts, nominal;
Logic"O" = Ground, nominal) ..

The Baudot and ASCII codes have different formats. ASCII has a unique code combination for
each alphabetic, numerical, or control character.
The correct interpretation of a five bit Baudot is
dependent upon knowing its previous history;
whether upper or lower case was· last selected. In
effect a sixth-bit, which can be called the Case Bit;
is required to uniquely identify the Baudot input.
The latch circuit shown in the typical application
can store this information and will generate the

device characteristics

For. full electrical, envirOnmental, a~d mechanical
details,' refer to the MM4220/MM5220 1024-bit
read only memory data sheet.

typical application and connection diagram
Baudot to ASCII

"
s,

",
A4Z1

o'n

"

."

",

INf'UTGAT£S
AREDMBlI2

~

~

,.

MM4220BL

,..snOll

"

~

..

Alit!

DMlDDDSERI~S

~

~.

iOB,

11

DUTPUTGATP

"

..

{AU UK)

Logic Lewlsoi Input and Output Codes.
"1"=;+5.0V Nominal

"0"= Ground, Nominal
logic levels
"1"Mol1l Negative Output

"0" More Positive Output

Dual-In-Line Package

."
0;
0,

s,

s,

0,

s,

'.
s,

.s.

"

..

.
.
.

Order Number MM422(1BLIJ or MM5220BL/J

.

n

. See Package 11
Order Number MM5220BL/N'

0,

See Package .18 .

'"

MODE

CONTROL

.
6-26

code·conversion tables
FUNCTION
INPUT

BAUDOT
ROM
ADDRESS SYMBOL
0
1
2
3
4
5

OUTPUT

ASCII
SYMBOL

Blank

NULL

T
CR
0
Space

T
CR
0
Space

H

H

6
7

N
M

N

8

LF
L

M

10

R

LF
L
R

11'

G

G

12

I

I

13
14
16
16

P

P
C
V
E
Z

•

17
18
I.

20
21
22
23
24

26

C
V

E
Z
0
8
5

5

Y

y

D

8

F
X

F
X

A
W

A

W
J

26
27
28

J
Upper

2'

Q

Q

90

K

31
32
33
34
35
36
37

Lower

K
Delete

38
39
40
41
42
43

44
45
46
47
48

U

Blank
5
CR

•

Space
#/£.5/5

IS1/Can
U

NULL
5
CR

9
Space
BS/FE

0
0
0
0
0

BAUDOT
3

4

5

0
0
0
0
0

0
0
0
0

0

0
0
1
1

0
1
0
1

0
1
1
1

0
1
0
1

0
0
1
1

0
1
0
1

1
0
0

0
1
1

0

0

0
0

0

0
1

1
0

1
1

1
'0

1
0

0
1

0
1
1

1
0
1
0
1

0
1

0
0

0

0

0
0

0

0

0
0

0
0
0

0

0
0
0
0
0
0
0
0
0
0
0

0
0
1
1
1
1
1
1

0
0

0
0

0
0,
0

9

4

4

1

&
8
0

&

,

0

1
1
1

0
0
0

;

;
3

1
1
1

0
0
1
1
1

Bell

6
!

6
!
/

$
?

/
2
Upper

$
?

2
Can

7
1

7
1

(

(

Lower

Delete

1
1
1
1

1
,I

1
1

1
1
1

0
0
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1

0
0
0
0

1
1
1
1
1
1

0
0

Bel~

1
1
0
0
0

1
1
1
0
0

0

0

1
1

1
1
1
0
0

'I

..

1
1

0
0
0
1
1

I

3

1

0
0
0
0
0

I

,

0
0
0
0
1

1
1
1
1
1
1
1

0

8

1
1
1

0
1
1
1
1
1

0
0

0
0
1
1
0
0
j

1

0
1
0
0
0
0
0
1
1
0
1

0
1
0
1

1
0
0
1

0
0

0
1
0
1

1
1

0
1
0
1

0

0
0
1
1
0

0
1
0
0
1
0
1

0
0

0
1

1
1
1
1
1
0
0

0
1
1

0

1
1
0
0

0
1
1
0
0

0
0
0
0
0

0
0
1

0
0
0
1
1
I,

0
0
1
1
1
1
0
0
0
0
1

1
1

.,

0
0
1
1
0
0
1
1

0
1
0
1
0
1

EP b7

0
1

bS

bS

b4

b3

0
0
0

0
1
0

0
0
1

0
1

0
0
0

1
0
1

0
1
1
.1
0
0,

0
0
0

0
0

0

1
1
1

0

1

1

0
0

1

1

0

r

0

0
0
1

1
1
1

0

0
0
1

0
0
0

0
1
0

0

1
0

1
1

1
1
1
1
1
I,

0

1
1
0
1

1
1
1
0
0
0
0

1

0
1
1

0
1

0
1
1
0
1
0
0
0
1
0

0
0
1
1
0

o.

0
I'
1
0
0
1
1

0
0
1
0
1

0
1
1

0
0
1

1
0
0
1

1
0

0
,0

0
0

1
1

0

1
1
1

1
1
0

1

0

a

0

a

1

1
0
0

0

0

1
1

0
1

0
0

0
'0

1
1

0
1

0
1

1
1

0

0
1

1

a
0
0

0
1
0

0

a

0
1
1
1
1
1

1
1
0
1
1

0
1

a

0

a

0

0
1

a

1

1
1
1

1
1

1
1

1
0
0
1
1

0
1
0
1

0
0
1
1
0
1

a

1
1
1

6·27

0
0

1
1
1

0
1

= Ca~cer

0
1

0
0

0
1

0
1

= Stop/Start
as .. Back Space

1
1
0

1
1

1

1

151 '" Information Separator #1

0
1

1

,

0
0,

0
0
0
0
1

0
1

1
0
1
1
1
1

0
0
0
0
0
0
1
0
1
'I
1

0
0
1
0
1

1
1
0
1

1
1
1
0
0
1
0
1

0

0
1
1
0

1
1

0
0
0
1

0
1

0
1

SIS

0
1
0
1
0
1

0

0
0

0

0

EP '" Even Parity

0
1
1
1

0

1

0
0
0

1
1

LF'" Line Feed
CR '" 9arriage Return

,.

0
1
0
1
1

0
1

0
1
0
0
0
1
0
1

0
0
0
1
0
0
1

0

0
0
1
1

0
1
0
1
0
1

0

1

0
0
0
0
0

0
1
1
0
1

0
0

b2 bl

0

1
1

0

1
1

0

0

1
1
0
1

0
0
0

1
1
1

0
0

0

0
0
0

0

1
1
1
1

0
0

1

1
1
1

0

0

1
,I

1
1
1
1
1
1

1
,I

LEGEND:

Can

ASCII

2

1

50
51
52

62
63

0
0
0

OUTPUT

1

LF·

..

56
57
58
5.
60
61

INPUT
C
A
S
E

LF

49

53
54
65

CODE

1
0
0
1

1
0
0
0

a

0

1

1

0

0
0
1
1

1
0
0
1

0
1
0
1
1
0
1
0
0
1
1
0
0
0
1
1

0
1
0
0
0
1
1
0
0
1
1
0

O.

0
0
0
0

1
1
1
1
0
1
1
1

0
0

0
0

0
1

0
0

1
0

0
1

0
1

0
0

0
0
1

0

1
1
1
0

1
1
1
0
1
0
1
1
0
1
0
0
1

0
0

1
1
0
0
1
1

0
1
1
1
0

1
0
1
1
0
1

MOS ROMs

~

NAnONAL

MM4220BM/MM5220BM sine look-up table

general description
The MM4220BM/MM5220BM is a 1024·mono·
lithic MOS read o.nly memo.ry that has been
programmed to solve for the sine value x of a
known angle 8; i.e., to. o.btain the solutio.n of the
equation x = sin O.

"1" it carried into the LSB of the eight bit code,
where Ag was a'binary "0" it was simply dropped.
EXAMPLE
Find the sine of 45~

Values of 0 are 'defined in the loo.k up table for
0° ::::: 0 < 90° (quadrant I) which has corres·
Po.nding so.lutions of 0 ::::: x < 1. For .values of
90° < 0 < 1BO° (quadrant II), enter the comple·
ment (lBO° - 0) to obtain the correct solution.
Solutio.ns for quadrants III and IV differ 'in sign
with I and II. This is summarized in Table 1.

The input address is (45/90) 128 = 64 or
1000000, as expressed in binary. The converter
generates the output .10110101 whose . decimal
equivalent is 0.707131. Thus, sin 45° = 0.707.

This input is divided into 12B parts for 0 in each
quadrant. Thus, the appropriate input address is
(01/90 0 )(12B) to the nearest whole integer. The
actual input code to. the ROM is the input address
expressed in binary" with A1 being the' least
significant bit.

This value is in quadrant III; therefore 0 1 = 210°180° = 30°. The input address is then (30/90)
128 :. 43 to the nearest whole integer. The binary
input to the ROM is then 0101011. The output
value is .10000001 o.r 0.503906. Thus,sin 210° =
-0.504, with ·the sign generated by the external
logic. The solution is with.in 1%; note that address
43 is actually equal to 30:23°.
.

Find the sine of 210?

The output is the value of X expressed in binary.
The output lines B1., B2 , ..•.• B8 are binary place
values 112, 1/4, ...... 11256. The sign for nega·
tive values of X is externally generated.

device characteristics
For full electrical, environmental and mechanical
details refer to. the MM4220/MM5220 1024·bit read
only memory data sheet..

The 8 bit output code has been ro.unded off from
a larger word code, i.e., where Ag was a binary

connection diagram
Dual·ln·Line Package

A,A,_

1

ZCr-VOD

2

'Z3

A,_

3

ZZ~N.C.

1,-

•

Z1~A.

S

"t-"

.~_

"'- ,

r-

N•C.

"I-"

84 - 1

"~A1

,,-I

I1~VGG

161-~:::ROl

1,-9
81 _10.

15

-~::8LE

a,-','

14

_A~

Vu -

13 r-N.C.

12

TOP VIEW

Order Number MM4220BM/J or MM5220BM/.

See Package 11
Order Number MM5220BM/N

See Package 18

6·28

pattern selection form

ADDRESS
REFERENCE

,

0

2
3

•

FUNCTION

COOE

INPUT

OUTPUT

DEGREES

RADIANS

B8

B7

BS

B5

B4

B3

B2

B,

.00
.70
1.41

.000

0

0
0

0
0

.037

0
0
1

0

0
1
1
1
0

0
0

0
0
0

2.11
2.81
3.52.

1
0
1
0
1
1

0
0
1

0

.012

0
1
1

0
0
0
0

0
1
1
1

1
1
1
1

0
0
1

0

.025

8
9
10

5.63
7.03

.049
.061
.074
.086
.098
.110
.123

11
12
13
14
15
16

7.73

.135

8.44
9.14

.147

5
6
7

17
18

'9
20

~--22
23
2'
25
26
27
28
29
30
31
32
33
34
35
36
37
38

39
40
4;
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
6.1
62
63

4.22

4.92
6.33

9.84
10.55
11.25
11.95

.160
.172
.184

.196
.209

12.66

.221

13.36
14.06

.233

15.47

.245
.258
.270

16.17
16.88

.282
.295

17.58

.307

14.77

18'.28
18.98
19.69
20.39
21.09

.319

.331
.344
.356
.368

21.80
22.50
23.20
23.91

.380

24.61

.430

25.31

.442

26.02
26.72
27.42
28.13

.454

28.83

.503

29.53

.515

.393
.405
.41,7

.466
.479

0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1

33.75

.S89

34.45
35.16
35.86
36.56
37.27
37.97

.614
.626
.638
.650
.663

38.67

.675

39.37

.687

40.08

.699

40.78

.712

41.48
42.19
42.89
43.59
44.30

.724

.577
.601

.773

6·29

1
1
1
1
1
1
1
1

1
0

0
1

1
1

0

0

0

0

0

0

0
1

,

0

1

0
0
0
1

1
1
1
1

0

0

0
1

.552
.565

0
0

0
0
1
1

0
1
0
1
1

1
0
1
0

.761

31.64
32.34
33.05

0
0

0
0

0
0
1
1
0
0
'1

,

1
1
1

a

.540

0
1
0
1
1

0
0
1

1
1
0
0
1
1
1
0
0
0

1
1
0

.7'49

.528

0
1
0
1
1

0
1
1

.736

30.23
30.94

1
1
0
0
1
1
0
0
0
1

0
1
0
1
0
1
0

0
1
0
0
1
0
1
1
0
1
1
0
0
1
1
0
0
1
1
1
0

.491

1
1

0
0
0
0
0
0

1
0

0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
0
1
0
1
0
0
1
0
1

0

1
0

0
1

,.

0
1
1
0
1
0

,

0

0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0

,
1

0
0

1
1
0
0
0
1
1
0
0
0
1
1
1
0
0
0
1
l'

,
,

1
1
1
0
0
0

1
0
0
0
0
0
1

0
0
0

0

0
0
0
1
1
1
1
1

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1

,

1
1
1
1
1
1
1
1

,

1
1
1
1
1

1
0
0
0
0
1
1
1
0
0

1
0
0
0
0
0
0
0
1
1

0

0
0
0
0
0
0
0
0

0

1
1

1
1

1
1
1
0

0
0
0
0
0
0
1
1
1
1
1
1

1
0

0
0
0
1
1

0
0
0
0
0
0
0
0
0
0
0

1
1

1

0
0

0
0
0

0
0

, ,

1

0
0
0
0
0

1
1

1
1
1
1
0
0
0
0

0
0

0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
j

0
0
0
0
0
0
0
0
0
0
0
0

0
0
0

1
1

0
0
0
0

1

0

1
1
1
l'

1
1
1
1
1
1
1
1
1
1
1

nil
I

:E
!Xl
o
N

pattern selecti.on form(con't)

N
In

:E
:E
.......
:E

ADDRESS
REFERENCE

FUNCTION

CODE

INPUT

OUTPUT

DEGREES

RADIANS

B8

B7

B6

lis

B4

B3

B2

!Xl

64

45.00

.785

0

0

1

.798

N
N

,46.41
47;11

.810

0
0
1
1
1

1

45.70

1
1

1

65
66
67
68

1
1

1
1
1
1

1
1
1

0
·0
0

1

0
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

o

~

:E
:E

69
70
11
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97

47.S1
48.52
49.22

49.92

.822
.834
.B41
.859
,871

50.62

.884

51.33

.896
.908
.920
.933
.945
.957
.969
.982

52.03
52.73
53.44
54.14
54.84
55.55
56.25

.994

56.95
57.66
58.36
59.06

1.006
1.019
1.031

59.77
60.47

1.043
1.055

61.17

1.068

61.87

1.080
1.092

62.5.8
63.28
63.98
64.69
65.39
66.09
66.80
67.50
68.20

1.104

'.117
1.129
1.141
1,154
1.166

1.178
1.190

98
99
100

68.91

1.203

69.61

1.215

70.31

101
102
103
104
105
106
107

71.02

1.227
1.239

108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127

1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
0
0
0
1
0
0
1
0
0
1
0
1
1
0
1

1
0
1
0
0
1
0
1
0
1
1

0
1
1

0
0
0
1
1
0

1
0

0
0
1

0
0
0
0

0
1
0
1
1
0
1
1
0
1
1
0
0
1
0
0
1

1.264
1.276
1.289
1.301
1.313

0
0
1

1.325

0
1
0

0
0
1

0
1
1

1

82.27
82.97

1.436
1.448

83.67
84.38
85.08
85.78
86.48

1.460

87.19
87.89
88.59
89.30·

1.522

1.473
1.485
1.497
1.509
1.534
1.546
1.559

0
0
1
1
0
0
1
1

1

1
1
0
0
0
0
1
1
1
1.

1
1
1

1
1
1
1

1
1

1
1

6·30

0
0
0
1
1

0
0
0
0
1
1
1
1

73.83
74.53
75.23
75.94
76.64
77.34
78.05
78.75
79.45
80.16
80.86

1.399

1
1
1

0
0
1
1

1
0
0
1
1
1

1.411

0
0

0
1
0
1

1.252

1.424

0
0
0
0
1
1

0
1

71.72
72.42
73.12

81.56

0
0
1
1
0
0
0
1
1

0
1
0
1

1.338
1.350
1.362
1.374"
1.387

0
0
1

1
1
0
0
0

0
0
0
0

0
0
0
0
0
0

1
1

0

0
0
0
0
0

0
1
1

0
0
0

1

0

1
1
1

0
0
0

0
0
0

0
0
0

0
1
1
1

0
0
0
0
0
0
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1

1
1
1
1

1
1

1
1

1
1

1

1
1
1
1
1

1
1
1
1
1

1
1
1

1
1
1
1

1

1

1
1
1
1
1

.,

0
0

1
1
1
1
1

1
1
1

1
1
0
0
0
0
0
0
1
1

'0
0
0
0
0
0
0
0

1

0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

B1

1
1
1
1
1
1
1
1
1

1
1
1
1

1

1
1
1
1
1

1
1
1
1
1

1
1
1

1
1
1

1
1
1
1

1
1
1
1

1
1
1
1

1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1

1
1
1

1
1
1
1
1

1
1
1.

1

1

1

1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1

s:
s:

typical application

~

N
N

o

OJ

s:
........
s:
s:

GATES DM6810 OR DMS812
A,

A,

B,

A,

8,

A.

B,

"

U1

N
N

0

A.

20

o

B,

MM42Z0BM/
MM5220BM

OJ

A"

B;

A,

• '"

3.Dle

s:

B,

TYPICAL,
lL1h1ES

'

..

B.

OTL/TTllOGIC

'A.
'CHIPENABLE

tMODE CONTROL _ _ _ _--I
= logic "1 "
*Chip Enable = logic "1" to obtain outputs.
Logic levels'
DH/TTl (except at MOStROM interface). logiC "1," +5.0V, NOM. logic "0," ground, NOM.
MOS/ROM inputs and outputs. logiC "1." more negative. logic "0," more- positive.

tMode Control = Logi!: "0," As

Table 1, SINE

Quadrant
I
II
III
IV

INPUT
Entry to ROM (0')

Range

> 0 < 90
> 90 < 180
> 180 < 270
> 270 <:: 360
0

1800

0

-

Sign

Direct Reading

+

X

Direct Readin'g

+

Direct

0

0

OUTPUT
Binary Value

0

0

X - 1800

Direct Reading

-

0

0

360 0

Direct Reading

-

-

III

X

IV

+1

360'

-1

6-31

z

m

o

N
N

Il)

::?!
::?!
......

z

m

o

N
N

~

::?!
::?!

~

MOS ROMs

NATlONAL

MM4220BN/MM5220BN arctangent look-up table
general description
The MM4220BN/MM5220BN is a 1024-bit mono·
lithic MOS read only memory that has been pro·
grammed to solve for the angle 6 whose tangent
value x is known; i.e., to obtain the solution to the
equation: ~ arctan X.

greater than unity, either complement the output
binary code and add a 1, or complement the
resultant angular value (i.e., subtract from 90°).

e

The 8·bit output code has been rounded off. That
is, if .another bit of even lower significance had
been computed for the given arctangent value was
a binary "1", it would have carried over into the
LSB of the eight bit code. If it was a binary "0", it
wou Id have been dropped.

Values of x are defined in the Look Up table for
0< x < 1 with angles corresponding from
0° -;; 6 < 45°. For values x :;:. 1, the reciprocal of x
(i.e., 1 Ix) must be entered and the output angle
must be complemented to obtain the actual value.

EXAMPLE
The input is divided into 128 equal parts for x.
Thus, the appropriate input address is (128)(x) to
the nearest whole integer for obtaining the appro·
priate ROM address. The input code is the ROM
address expressed in binary with Al being the least
significant bit. For input values greater than unity,
the decimal reciprocal is to be taken prior to entry
of the binary address.

Find the angle whose tangent is 0.258.
The input address is 128 x 0.258, or 33 to the
nearest integer. Expressed in binary, this is
0100001, and is the actual input code to the
converter. The converter will generate the binary
value .01010010, whose decimal equivalent is
0.3203125.

The output has been normalized for 45°. To ob·
tain the true angular reading,the output should be
multiplied by 45°, i.e.: e ~ (lIou,pu,) x 45° where
eou,put is the decimal equivalent of the output.
The output code is the normalized value of the
angle 6 expressed in binary. The output lines BI ,
8 2 , •••• B. are binary place values 1/2, 1/4, ....
1/256. To obtain angles between 45° and 89.6°
which occur when input values of x are equal to or

Thus, 6 ~ 0.320 x 45° ~ 14.4°

device characteristics
For full electrical, enVironmental, and mechanical
details, refer to the MM4220/MM5220 1024·bit
read only memory data sheet.

connection diagram
Dual-I n-Line Package

A,_

1

8, -

"

82

-

5

83

-

&

B._

1

lSt-AJ

a,-.

11

r--

VaG

1._ 9

16r~g~';ROL

87 - 1 0

15~~:~8L£

I"r- At
vss "":""' ..
" _ _ _ _ _ _'...
' r",_11

Order Number MM4220BN/J or MM5220BN/J
See Package 11
Order Number MM5220BN/N
See Package 18

6·32

s:
s:

patter rl selection form
ADDRESS

128(.f

0
1
2
3
4
5
6
r"-7
8
9
10

OUTPUT CODE (OOUTF'UT')

86

as

0 0
1 0
0 1
1 1
1 0
0 1
1 1
1 0
0 1
1 1
0 0
0 1

0
0
0
0
1
1
1
0
0
0
1
1

88 97

0
0
1
1
0
0
_.1
0
0
1
1
0

a

1

1

13
14
1
16
17
18
19
20
21
22
23
24
25
26
27

0
1 0
0 1 1
0 0 0
1 1 0
1 0 1
0 0 0
0 1 0
1 0 1
1 1 1
0 1 0
0 0 1

0
0

1

1

1

1

0

0

0
0
0

0

2.

1

1
1

1
0
0
0

1

1

0 1
0 ,I

1

0
0

1

1

0

0
0
0
0

1?

29
30
31
32
33
34
35
36
37
38
39
40
41
42

1
1

1

0

0

0
0
0

0

0
1

1

1

1

1
1

1

0
1
1
0
1
0

1

1

0
0
1
0
0
1
1

0
0
0

1

0
1
1

1
0
0
0
0
1
1

1

1
1

0

0
0
0

84 93

62

0
0
0
0
0
0
0
1
1
1
1

0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
1 0 0
1 a 0
a 1 0
0 1 a
0 1 0
0 1 0
0 1 0
0 1 0
1 1 0
1 1 0
1 1 0
n
1
1 1 0
1 1 0
1 1 0
0 0 1
0 0 1
0 0 1
0 0 1
0 0 1
0 0 1
1 0 1
1 0 1
1 0 1
1 0 1
1 0 1
1 0
1 0 1
0 1 1
0 1 1
0 1 1
0 1 1

,.

.I).

OUTPUT CODE (OOUTPUT)

ADDRESS
128

B1

0

43
44
45
46
47
48
49
50
51
52
53
54
55
56
57

O.

58

0
0
0

o·
0
0
0
0
0

0
0
0

a
a
0
0
0

0
0
0
n
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

,

(~I

B3

82

0

1

0
0

1
1

1
1

0
0

1

1
1

1

1
1
1

1
1

1
1

1
1

0
0
0
0
0
0
0
0

86
87
88
89
90
91
92
93
94
95

1

9A

1

97
98
99
100

B7

86

B5

B'

0
0

0

0

1

1
1

0

1

1

1

0
0

0

1

0

0
0
1

0
0
0

1

1

0
1
1
0

0
0

0
1
1

1

1

1

1

1

0

0

1
0
0
0
0
0

Be

1

1
1
1

0
0
0
0
0
0
0

1

1

0
1

0
0
1
1
0
0

0 0
0
0

0
0

1

1
1
1
1
0
0
0
0
0

B 1

1
1

0
1
0 O~
f-'1 0 1
0 0 0 1
59
1 1 1 1 0 0 0 1
60
1 0 0 0 1 0 0 1
61
1 1 0 0 1 0 0 1
62
1 0 1 0 1 Of!!""
63
~
1 1 1 0 1 0 0 1
4
65
1 0 0 1 1 0 0 1
1 1 0 1 1 0 0 1
66
1 0 1 1 1 0 0 1
7
1 1 1 1 1 0 0 1
68
1 0 0 0 0 1 0 1
69
1 1 0 0 0 1 0 1
70
1 0 1 0 0 1 0 1
71
1 1 1 0 0 1 0 1
72
1 0 0 1 0 1 0 1
73
1 1 0 1 0 1 0 1
7,
1 0 1 1 0 1 0 1
75
0 1 1 1 0 1 0 1
76
77
0 0 0 0 1 1 0 1
78
0 1 0 0 1 1 0 1
79
0 0 1 0 1 1 0 1
80 .
0 1 1 0 1 1 0 1
0 0 0 1 1 1 0 1
81
1 0 0 1 1 1 0 1
82
1 1 0 1 1 1 0 1
83
1 0 1 1 1 1 0 1
84
1 1 1 1 1 1 0 1
85
Note: 1 more ,negative output.
0

1

1

AODRESS
128101

1
1

OUTPUT CODE (eOUTPUT)
8e

B7

86

85

1
0

0

0

0

1

0

0
0
1
1

0
1

0
1
1

1

1

0

0

1

1

1
0

0

0
1
1
0
0
0

1

0

0
1 0
1

1

1
0
0

0
1

1
1

1

1

0
0
0

1

0

1

0
0

1

1

0
0
1 1
0 0
0 1
1 1
1 0
0 1
1 1
1 0
0 1
0 0
1 0
1 1
119
0 0
120
1 0
121
1 1
f,--ill..... 0 0
1 0
123
1 1
124
0 '0
125
126
1 0
0 1
127

0
0
0

f--lQl.102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117

I---'-'!-

1

1

0
0

1

1
1
0

0
0
1
1
0
0
0
1
1
1
0
0
0
1
1
1

84

83

0 In
0 0
0 0 0
0 0 0
0 0 0
1 0 0
1 0 0
1 0 0
1 0 0
0 1 0
0 1 0
0 1 0
0 1 0
0 1 0
1 1 0
1 1 0
1 1 0
1 1 0
1 1 0
0 0 1
0 0 1
0 0 1
0 0 1
0 0 1
0 0 1
1 0 1
I 0 1
1 0 1
1 0 1
1 0 1
0 1 1
0 1 1
0 1 1
0 1 1
0 1 1
0 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1

1
1
1
1

1

1

1

1
1
1

1

s:
s:

1
1

N

1
1
1

1

o

1

1
1

1

..1....
1
1

1
1
1

1
1

1

1

1

1

1
1
1

1

1
1

1

1
1
1

1

1

1

1
1

1

1
1

1
1
1
1

1

1

1
1
1
1
1

1

1

1
1
1
1

1
1
1

1
1

1
1
1

1
1

1
1

1

1
1

1

MM522BN

typical application

DTL/TnlOGI~

tMooe CONTROl _ _ _ _--l

Logic Levels;
OTlITTL (except at MOS/R(]M intrthc~l. Lllgic "1," +S.OV, NOM. Logir: "0," grollnd. NOM.
MOS/ROM inpllts and outputs. Logic "1," mOIp. negative. logic "0," more positive.

6·33

o

B 1

o more positive output.

tMode Control" logic "D," As = logic "1."
*Chip Enable" Logic ''1'' to obtain Ollt(Juts

N
N

82

to
Z

......
(J1

N

to

Z

u..
C

o('\oj
('\oj
It)

~
~
.......

u..

C

o('\oj

~

MOS ROMs

NATlONAL

MM4220DF/MM5220DF
"quick brown fox" generator

('\oj

.::t

~.

:E

general description
along with an even parity bit for a binary count
input of 64 to 127.

The I\IIM4220DF/MM5220DF is designed for exercising and rapid testing of ASCII and Baudotcoded keyboards, typing mechanisms, and data
communic"ations links by generating the internationally accepted "Quick Brown Fox" message.

device characteristics

The input is a 7-bit binary sequential count. The
output of a 6 stage up-counter can be used; a
seventh bit selects the desired code. The message
is generated in the 5-bit Baudot Communications
Set code with a binary count input of 0 to 63: The
message is generated in the 7 -bit American Standard Code for Information Interchange (ASCII)

The message generator is fu lIy contained on a
monolithic MOS integrated circuit chip utilizing
low threshold voltage technology for increased
DTLlTTL compatibility. For complete electrical,
environmental, and mechanical details, refer to the
MM4220/MM5220 1024-bit read only memory
data sheet.

typical applications

l~rUT

connection diagram

Dual·1 ".·Line Package

GATES

DMSHI20R

"
"
"

MM4220DFI
MM522(/DF

"

-,
-,
-,
-,
-,

tMode Cantrol" logic "0," As = Logic "1"
~Chip Enable'" Logic "1" to obtaill output~,

.•
~

OutputsfOl cinuit showll
Ballda!: Logic "0"

logic levels:
OTl/TTl (except at MOS/ROM interface}, Logic "1," -tS.OV, NOM. logic "0," ground, NOM.
MOS/ROM inputs and outputs, Logic "1," more negative. logic "0," ,more positive.

QUICK
QUICK
QUICK
QUICK
QUICK
QUICK
QUICK
QUICK
QUICK
QUICK
QUICK
QUiCK

BRe\llN
BR0101N
BReWN
BR0;.oN
BR010N
Bri"IoIN
SR0101N
SReWN
BIHlWN
BR0WN
SR0i111N
BReloiN

F"I2IX
I'0X
I'0X
F"0X
F0X
F0X
r0X

FeX
F"0X
F0X
F0X
FelX

JUMPS
JUMPS
JUMPS
JUJo.,p·s
JUMPS
JU/,:PS
JUMPS
JUMPS
JUMPS
JUMPS
JUMPS
JUMPS

eVEI'<
0VER
0YER
eVE"
eVER
eVER
eVER
eVER
0VER
eVER
0VER
0VER

THE
THE
THE
THE
THE
THE
THE
THE
THE
THE
THE
HIE.

LAZY
LAZY
LAZY
LAZY
LAZY
LAZY
LAZY
LAZY
LAZY
LAZY
LAZY
l,.AZY

D0G
peG
!;l0G
P0G
DeG
peG
DeG
D0G
DeG
DeG
DeG
DeG

1234567890
123-'1561890
1234567890
1234561890
12311561890
1234561890
123~567890

12J-'lSb7890
12311561890
12311567890
1234561890
1234567890

6-34

"punch"

ASCII: logic inversian

-,
-,
-,
-,

'00

MOOE
CONTROl

Order Number MM42200F/J
or MM5220DF/J
See Package 11
Order Number MM5220DF/N
See Package 18

A typical application showing the ASCII-coded test
message as received at a computer terminal.
THE
n4E
THE
THE
THE
THE
THE
THE
THE
THE
THE
THE

=

"

"
"
"
"

DE
PE
llE
DE
DE
DE
DE
DE
DE
OE
DE
DE

s:
s:

code conversion table

~

N
N

o

OUTPUT CooE'

C

OUTPUT CODe

"TI

P

.......

A
R

ADDRESS

CHARACTER

-

0
1

CR

1

2
3

•
5
6
7

CR

1

LF

1
1

Ltr

T
H

E

T

1
1
1

Q

10
11
12
13

I

,.
15
16
17
18

1
1

SP

8
9

U
C
K
SP

8
R

0
W
N

19
20
21
22

SP

23

SP

2.
25

J

U

F
0
X

I

Baudot

OUTPUT

1
1
1
1
1
1
1
1
1
1
1
1

-

-

5

1
1

1
1

1

3

2

b7

·6

·5

b.

b3

b2

0
0

1
1

1

64

NULL

0

0

0

0

0

0

65

CR

1

1

0

0

CR

1

1

1
0

1
1

1
0

0
0
1

0

LF
T

1
1
0

1
1

0

66
67
68

0
0

0
1

0

1
1

H,

1

0

1

E

0
0
0

0
1

1
1

0
1
1
1

1
0
1

1

0
1
1
1
1
1

T

CHARACTER

y

1

I

1

1

1

1
1

1
1

0
0

0
1

0
1

0
1

1

1
1

0
1

0
1
1

0
1

1

1
0

1
1
1
1
1
1
1

1
0

71
72

SP

0
1
1
1
1
1

1
1
0

69
70

0
0
0
0
1

0

73
74
75

U

1

I

1

0
1
1

0
0
1
0
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1

1
1

1
1
1

I

l'

1

1

1
1

1
1

1

•

.,

OUTPUT
ADDRESS

1
1
0

1

1

0
1
0
0
1
1
1
0
0
1
1
1

ASCII

1

1
1

1
0
0
1

0
0
0
0
0
0
0

0
0
0

1
1
1

1

1
0
0

T

1

0
1
0
0
0
1
0
1

0
1
0

0
1
0
1
1
1
1
1

T

I

0
1

Q

C
K

76
77
78
79

SP

8

80
81
82

0
1
1

R

0

0
W

0
0
1

N

--

SP

0

83
8.

1
0
1

85
86
87

SP

88
89

U

0

1

1

0

0
0

0
1

0
0
1

0
1
1

0
1

F
0
X,
J

0
0
0
0
0
0
1

0
1

0
0

1
1
1
1

0
0
0
1

0
1

0
0

1
1
1
1

0
0
0
1

0
1
1
1

0
0

0
1

0

0

29
30

SP

1
1

1
1

0

1

1

0

0

0
0
1

1

31
32

V

l'

0
1

0
1

0

1

1
1

0

E

1
l'

0
1

1

0

1

97

1

0

1

1
1

a

1
1

98
99
100

SP

0
0

1
1
1

1
1
1
1
1
1
1

1
1

0
1

10,1

E

0

0
0
,0

102

SP

a

1
0

103

L

0
0

1
0

104
105
106
107

1
1
1
0
1
0
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
0
0
0

0
0

1

0

A
Z

33
34
35
36
37

R

1

T

SP

1

1

1
1

T

1
1

1
1

1
1

H

1
1

1

1

SP

1

L

1
1
1

T

38
39
40
41

A

1

1

1
1
1

1
0
1

Z

T

1

0

1
1

1
1
1
1
1

0
1
1

42
43
44
45
46
47
48
49
50
51
52
53
54

E

Y

1
1

SP

1

D

1
1
1
1
1

0
G
SP

Fig.

1
2
3
4
5
6

T

1

1
1

1
1
1
1
1
1

1
1
1
1

1
1
1
1

1
1
1
1

1
1
1
1

55

7

1

1

1

56
57

8
9

1
1

1

1

'I

1

58

0

1

1

59
60

SP

1

Ltr.

1
1

1
1

1
1
1

1

1

62

D
E

63

SP

61

1
1

B8

1

T

1

1

B7 B6

0
0
1
0

1

a

1
1
0
1
1
1
0
0
1
1
1

0

0

0
1

1
1

1

0
83

B2

0
1
0
1
1

0
0
1
1
0
0
1

1
0
1
1
1

1
0
0

1
0
1

1

1

0
0

1
1

0
1
1
1
1
1
0
1
0
0
0
1
0
1
1
0
0
1
0
1
0
1
1
1

0
0
1
0
1
1

0
1

1

B5 B4

Baudot: Logic "0,"

1
1
0
0
0
1

P

1
1
1

93
94

SP

0

1

0

1
0

95
,96

V

0
1
0
1
1
1

0
0
1
1

1

1
1
1
0
1

1

1

0
1

1
0

0
1

1
1

1
1

0

0
1
0

1
1

1

1

0

0

0

0

0
0
0

0
0

0
1

R

1

0

1

0
0
1

1

E

1
1

0
1

1

1
1

D
G
SP
',1"

2
3

J 15
116
117
118
119
120

4
5
6
7
8
9
0

122

SP

1
0

123
124

0

0

125
126

E
SP

DEL
DEL

0
1

B8

6-35

0
1
0
0

1
1
0
0

0
1

0

1.

0

0

1
,1

109
110

a logical

0
0
0
1

0
0
1
0
0
0

1

108

SP -- Space

0

1

0

1;21

Note: When chip enable input is at a logical 0, all outputs are at

0

1

1
1

0

y

Bl

0

1
0
1

0

SP

= "punch"

1
0
1

1

1

H

127

1

1
1

0
1

0

1

0
1

0

0
1
1

0
1

T

111
112
113
114

0
0
0
0
1
1

1
0
0
0
1

1

1
1

1

1
1
1 '

1

0
1
1

0
0

0

1

1
1

S

0
0

1
1

1

1

S

M

1
1
0

1
0
1
1

1

1

P

92

0
1
1

0

0

M

90
91

1
0
1

0
1

28

1

1
1

0
1
0
1
1
1

1
1

26
27

0

1
1

0
0
0

1
1

0
1
1

1
1
0
0

1
0

1

1

0
1

1

1

1

0
1

1
1
1

1
0

1
1

0
1

0
1
1
1
0

0
0
0
1
1
1
1
1
1
1

0
0
0
0
0
0
0

1
1
1

0
0
0

1
1
0

0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
,0

0

1
0
0
1
1
0
1
1
1
1
1
1
1
l'

1
0

0

0
1

0

1

1

1
1

1
1
1

1
1

0

0
0

0
1

0

0
0

0
0

B7

1

0

1

1
0
1
0
1
0
1
1
1
1
0,
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1

0
1
1
1
1

0
1
1
1
1

a

1
1
1
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1

'I

T

0
1

0

1
0

0

0

B6 85 8' B3 B2
ASCII: logic inversion

1

a
1
0
1
1
0

a
1

b
1
0
1
0
1
0
1
0
1
1
1

0
0

Bl

s:
s:

U1
N

N

o

C

"TI

~

MOS ROMs

NAnONAL

MM4220EK/MM5220EK
BCDIC-to-EBCDIC and ASCII-to-EBCDIC code converter

general description
. TheMM4220EK/MM5220EKisa 1024-bitread only
memory that has been programmed to convert
both Binary Coded Decimal I nterch ange Code
(BCDIC) and the American Standard Code for
Information Interchange (ASCII ) to EX.lended Binary Coded Decimal Interchange Code (EBCDIC).

ASCII code in addresses 64 through 127 has a "1"
in the most significant (A 7 ) bit which is used with
the selection logic. The resulting 6-bit ASCII input
is for display-only upper case and numerical
codes, since it will not .accept the control commands or the lower case characters.

The BCDIC-to-EBCDIC converter is located in the
first 64 S-bit bytes of the ROM. The unused parity
check bit (the most significant input BCDIC bit) is
always a "0".

device characteristics
For full electrical, environmental and mechanical
details, refer to the MM4220/MM5220 1024-bit
read only memory data sheet.

The ASCll-to-EBCDIC converter is located in the
second 134 S-bit bytes of the ROM. Thus, the input

typical application

connection diagram
Dual-In-Line Package

:av----------------+--

a

1

0

0

1

a

9

13

>

14
15

JITM)

TM

16

Space

Space

17

/

I

18

S

S

19

T

T

20

U

U

21

V

V

22

W

W

23

X
y

X
y

a

1

1

1

0

0

1

1

a a a
a 1 0
1 a 0

a 0
a a
a a
a 0
a 0
a 0
a a
a 0
a 0
0
a

0

1

1

1

1

1

0

a

0

a a

1

0

0

a

1

0

1

0

a

1

1

1

0

0

a
a

1

1

1

1

1

1

1

a

1

0

1

a
a

0

1

1

1

1

1

1

1

0

1

1

1

a

1

0

1

1

a

1

1

1

0

a a

1

a
a

0

1

1

0

0

0

a
a

0

1

0

0

1

0

1

1

0

a a
a 1

0

0

a

0

1

1

0

1

1

1

1

0

1

1

0

1

1

0

1

1

1

0

0

1

1

0

1

0

1

1

1

1

1

1

0

0

1

1

1

1

1

a

0

1

1

1

a
a

1

0

0

0

1

25

Z

Z

0

0

1

1

1

1

1

1

a

0

1

26

*IRM)

RM

a

1

1

0

1

1

1

0

0

1

1

0

1

1

1

1

1

1

0

1

1

1

1

0

1

1

1

a
a

a
a

1

1

a
a

a a
a 1

0

0

1

0

1

0

1

1

1

1

1

1

1

0

1

0

1

0

1

0

-

0

0

1

1

1

1

1

1

1

1

1

1

1

0

1

0

a

0

0

0

1

1

0

0

a

a

0

J

0
0

a
a
a

a
a

a
a

q

a
a
a a
a a
a a

a
a a
a 1

1

1

1

1

1

a

0

0

1

1

1

a

1

1

0

1

0

0

1

1

1

1

1

a

1

0

0

,.

a

1

a 0 a
a a a
a a a

a

a
a
a
a

1

0

0

1

1

0

1

0

1

0

1

0

1

a

a
a

1
1

24

27
28

%or (

29

v

30

\

31

+

'*

32

%

33

J

34

K

K

35

L

L

36

M

M

~-

N

N

38

0

39

p

0
P

40

Q

Q

41

A

R

1

1

0

1

0

1

0

a

1

1

0

1

1

0

1

0

1

1

0

0

1

1

1

1

1

0

1

0

1

1

1

1

0

0

1

1

0

1

1

0

a

0

1

1

1

1

0

1

1

1

0

1

0

1

1

a
a

0

0

1

0

-

1

0

1

0

1

a

1

1

0

1

"

0

43

$

$

)

)

6

46
47

0

a
a

0

44
45

0

a
a

a
a
a
a
a

,

1

1

a
a

,

0

1

0

a
a

42

1

1

1

1

1

0

1

1

0

1

0

1

1

0

1

1

0

1

1

0

0

0

1

0

1

1

1

0

1

1

a

1

0

1

a

1

1

1

a
a

0

1
1

0

1

1

1

0

0

1

0

1

1

1

1

0

1

0

1

1

1

1

0

i

1

1

1

1

1

1
0

1

&

a

1

1

0

a

0

1

0

1

0

0

0

A

A

0

1

1

0

0

0

0
1

0

49

1

1

B

0

1

1

a a
a 0

1

0

1

1

a
a

1

B

a
a

a

50

a
a a

1

a

1

r--~~-~

& or

+

- - --,---

0

51

c

c

a

1

1

1

0

0

0

1

1

52

D

1

1

0

1

1

a a

a

1

1

1

a

1

1

1

0

0

0

1

a
a

0

a

a a
a 1

1

E

D
E

0

53

0

1

1

0

1

54

F

F

0

1

1

0

1

1

0

1 ·1

a

0

a

.1

1

55

G

G

0

1

1

0

1

1

1

1

1

0

0

0

1

1

1

56

H

H

0

1

1

1

a

0

0

1

1

0

0

1

a

0

0

57

I

I

0

1

1

1

a a

1

1

1

0

0

1

0

0

1

a
a

1

1

1

0

1

a

1

1

0

1

1

1

1

1

a
a

,

58

,

1

1

a

1

.1

0

0

1

0

1

1

or }

0

0

1

1

0

1

1

0

1

0

1

a

I

0

1

1

1

a
a

0

I

1
1

1

61

1

0

1

a a

1

1

0

1

62

<

<

0

1

1

1

1

1

0

0

1

0

1

1

0

0

63

*

a

1

1

1

1

1

1

0

1

1

1

1

0

1

59
60

IJ

6·37

1

,.

0

N
N

o

m

"

~

w
~

code conversion tables(con't)

N
it)

~
~
.......

FUNCTION
INPUT

~

COOE

OUTPUT

w

o

N
N

~

~
~

ROM
ADDRESS

ASCII
SYMBOL

EBCOIC
SYMBOL

64
65
66
67
68
69
70
71
72
73
74
75
76

@

@

A

A

B

B

L

L

77
78
79

M

M

N

N

80
81

C

C

0
E
F

E
F

0

G

G

H

H

I
J

I

K

J
K

0
p

0
P

Q

Q

82

A

A

83
84
8S

S
T
U
V
X

S
T
U
V
W
X

Y

Y

z

Z.

I

(

86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
11.
115
116

~.~
118
119
120
121
122
123
12.
125
126
127

W

\

\

I

I

"""or"

~

!

Space
!

#
$

#
$

%

%

&

&

Space

..

..

!

(

(

I

I

+

+

/
0
1
2
3
4

/
0
1
2
3
4

C
0
D
1
1
1

0
0
0

0
0
0

1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0
0

0
0

1
1
1
1

0
0
0

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0

a
0
0
0
0
0
0
0

a
0
0
0
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

a
0
0
0
0
0
0
0

a
0
0
0
0

1
1
1
1
1

1
1
1
1
1

1
1
1

1
1
1

0
0
1
1
1

1

1
1

1
1

1
1
1
1
1
1

1
1
1

6
7
8
9

5
6
7
8
9

;

;

1
1

<
>
,

<
>
,

,

ASCII

E bS b5 b4 b3 b2 bl 0

1
1
1
1
1
1

___5___

OUTPUT

INPUT

1
1
1
1

1
1
1
1
1

a

1
1
1
1
1
1
1
1

6-38

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
0

0
0
0

0
0

0
1
1
1
1

a
0
0
1
1
1
1
1
1
1
1
0
0
0

a
0
0

a
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0

a
a a
0 a
a 0
0
0

1
1

a

1
1

0
1
1
1
1
1
1
1
1

a
0

0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1

2

1
1
1
1
1
1
1
1

1
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1

0
0
0
0
0

1
1
1
1
1

0
0

1
1
1
1
1
1

0
0
0

0
1
1
1
1
1
1
1

EBCOIC
3 4 5
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0

1
0

0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1

a
0
0
0

a

1
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

a
a a a

1
1

a a

0
1
1
1

0

a a

0
1
1
0

1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
1

0
0
1
1

0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0

0
1
1

1
0
1

1

1
0
1

0
0

0
1

a

0
1
0
1
0
1
0
1
0
1

0
0
0
0

a
0
0
0
0
0
0
0

a a
1

0

0
1

a

1

0
1
1

0
1
0
1

a

1
1
1
1
1

1

0
0
1
1

a
1

0
1
0

a
0
0
1
1
0
1

1
1

1
1

1
1

1
1

1
0
1

1
1
1

1
1
1
1
1
1

1
1
1

a

1
1
1

0
1
0

a

1
0
1

0
0

1
1
1
1
1

0

1

0
0

1
1
1
1
1
1
0

0
0
1
1
0
0
1
1
1
1
0
1
1
0
1
1
0
0

a
0
0
1
1
1
1
1
.1
1
1
1
1
1

1

1
0
1

1
1

a

0.

0

1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0

0
0
1
1
1
1

a
0
1
0

a
1
0
1
1
1
1
1
0
0
0
0

6 7
0
0
1

0
1
0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
00
0 1
1 0
1 1
0 a
0 1
a 1
0 0
0 1
1 1
0 1
0 0
1 0
1 1
1 1
1 1
0 0
0 0
a 1
0 1
0 1
0 a
1 0
1 1
0 0
1 1
0 1

a 0
a a
a 1
a 1

0
1

1
1
1

0
0
1
1

a

1

0
1
1
0
1

1
1

0

0

a

0

1
1
1

0

0
1

0

1
1
1

1
1
1
1
1

1
0
1
1
1·

1
0

0
0
0
1

MOS ROMs

~

NAllONAL

MM4220LR/MM5220LR BCOIC to ASCII-71
ASCII-7 to BCOIC code converter
genera I description
address 63, converts the 64 character ASCII
graphic subset to BCDIC. The tables show the
character assignments and their binary equivalents.

The MM4220LR/MM5220LR is a 128 x 8 read
only memory which has been 'programmed to convert the 64 characters of the Binary Coded Decimal
Interchange Code (BCDIC) to the American Standard code for Information Interchange in seven
bits (ASCII-7).

For electrical, environmental and mechanical details, refer to the MM4220/MM5220 data sheet.

The first half of the ROM, from address 0 to

typical applications and connection diagram
BCDIC to ASCII
Dual-In-Line Package

"
"
"
B,

.

B,

B,

B,

B.

B,
781T
~

"'''

OUTPUT

~

..
B,.

".
tMOOECDNTRDl_~_.,.--'

tMode Control = logic "0," As = Logic "1."
·Chip Enable = logic "'" to obtain'outputs.
LOgic levels:
OTL/ITL (except at MOS/ROM intorface), Lugic "1," +5.0V. NOM. logie "0," ground, NOM.
MOS/ROM inputs and outputs. logic "1," more flogative. Logic "0," mOrl! positive.

B.

B,

B,

'"

MODE

B.

.&DNTROL

B,

em.
ENABLE

'.

"

'

.

"

Order Number MM4220LR/J
or MM5220LR/J
See Package 11
Order Numb.r MM5220LR/N
Se. Package 18

ASCII to BCOIC

68IT

.3

ASCII
INPUT
lbeitOTUSED)

~

6IIT

BCDICOUTI'UT

l.OK,
TYPICAL.

I,LINES

tMODECDNTROl _ _ _ _..J

tMode Control'" Logic "0," As = Logic "1."
·Chip Enable = logic "1" to obtain outpats.
logic level!:
OTl!TTl (except at MOS/ROM interface).' Logie "1," +5.DV, NOM. logic "0," ground, NOM.
MOS/ROM inpuu and outputs. Logic '''t,'' more negat;~e. logic "0," more positive.

6-39

a:

...I

o

N
N

code conversion tables

It)

::!
::!
........

ASCII to BCDIC

a:

FUNCTION

...I

o

OUTPUT

ROM

ASCII

BCOIC

ADDRESS

N

('II

o:t

CODe

INPUT

::!
::!

SYMBOL

SYMBOL

a

SP

sP

1

,

E

a
a
a

H+

#

#

$

$

5

%

%

6
7

&

&

8
9

(

Blank

)

~

VT

I

0

I

0
0

v

11

12
13
14

CR

15

/

/

16
17

a

0
1

1

18

2

2

19

3

20
21

4
5

3
4
5

22
23
24

6
7

6
7

8
9

8

25

9

26
27
28

<

<
-J

29
30
31
32
33

A

A

34
35
36

8

B

C

C

0

0

-

>

>

?

?

@

@

0
0

a
a
a
a
a
a

0

F

40
41

H

H

I

I

42
43

J

J

K

K

44
45

L

L

M

M

N

N

0
P

P

a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a

Q

R

R

51
52

S

S

T

T

53

U

U

54
55
56

v

v

W

W

x

X

57
58

y

y

z

z

59

I

I

60
61
62

\

\

I

I

~

c

63

-

-

A7

DATA

P

B

A

8

4

2

,

a
a
a
a
a
a
a
a

a
a

a

0
1

a

0

a

a
a

a

0

1
1

a

a
a
a
a

1

a
a

1
1

0
1

1

a
a

a

0

a

1

1

1

1

1

a

1

1

1

1

a
a
a
a
a
a

0

1

a

1

1

1
1

1
1

1
0
0
0

0

a
a
a
a
a

E

b,

0

0
0

G

b2

a
a
a
a

a
a

,

0

b3

a
a
a
a

a

F

Q

0

0

a
a
a
a
a
a
a
a
a
a
a
a
a

b4

a
a
a
a
a
a
a

0

E

50

a
a

a

G

0

0

0
0

39

48
49

a
a
a
a
a
a
a
a
a
a

bS

a

37
38

46
47

b7

0
0

a
a
a
a

OUTPUT

ASCII

D

..!

10

1----

0

3
4

2

INPUT

C

0

a
0

a
a
a
a
a
a
0
1

,

1
1

,1

,
,1
1

1
1

0

a

a

1

a

1

,

,

a

0

,

1
1

0
1
1

a

a
a
a
a
a
a
a
a

a
a
a
a

a
a

1

a
a

1
0

,

1

,

0

,

,
,

,

0

0
0

1
1

a
a
a
a

1

a

1
1

,
,

a

,

0
0

1
1
1

a

1

1

0

1

1

0

0

1

0
0

a

1

1
1

1

,

1
1

0

0

1
1

,
a
,

a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a

A2

A,

Ba

a
a

,
,

a
1
0

,

,

0

1

1

,

a
a
a
a

a
a

1

a
a

0

1

a

+a

r_'a

0

0

a

,
1

,

,
,

1
1

,
1

1

,

1
1
1

1
1
1

1
1
1

1
1
1
1
1

A6

As

A4

,
,

1
1

a
a
1

1
1
1
A3

6-40

0

a
a
a

1
0

1

1
1

1

a

a
a
a
a
a
a
a
a

1

,
,1

,

,

,

0
0

a
a
a
a
a
a
a
a
a
a
a
a
a
a

,

a
a
0

a

a

1
1
1

1

,

,

1

1

1

1

a

1

1
1

a
a

1
1

a
a

1
1

1

1
1

1

0

,

a
1

,

1

,

a

1

1

a
a

a

,
1

a
1

a
a

,

1
0

a
a
a
a
a
a
a
a
a
a

1
1
1

a
a

a
a
a

0

0

a
0

a
a

a
a

1
1

0

0

1

,

1
1

a

1
1

0
1

a
a

a
a

a
a

1

1

a

a

,
,

a
1

a
a

1
1
1

1

1
1
1
1
1
1

1
1

1
1

a
a

1
1

1

1

a

a
a
a
a
a
a
a
a

1

a
1
1

a
a

,

1

1

1

a

1

1
1

1

,

1
1

1

a
a
a

,

,

<,

,

a

0

a

1

a

1

1

0

1

1

0

a

a

a

0

1

a

1

1
1

1
1

a
a

1

1

1

,1

a

1

a

a

0

0
1

,

a

1

a
a

0
1

1
1

1

1

a
a
a
a
a

a
a
a

a

1

1

1

a

1

a
a

1

1

0

1

1

1

a
a

a

1

a

a

a
a
a
a

1

1

0

1

a

a
a
a

1
1
1

a
a
1

a

1

a
a

a
a
a
a
a
a
a

a
a
a
a
a
a
a
a
a

a
a
a
a
a
a
a
1
1
0

a
a
1

1

a

1

a
1

1

1

1
1
1

1
1
1
1

a

a

a

B7

B6

as

B4

B3

,1

0
1

,

1
1
1

a
a
a

0

1

1

1
1

1
1
1

,
,

0
1

1
0

1

,

0

a
a

1
1
1

1

1

1
1

0

a

1

1
1
1

1

1

a

0
1
0

a

1

a

a

1
1

a
a

1

1
1

a
a

a

0

a

1
1

1

a

a

,
,

1

0

a
a

a

0
1
1

1

a

1

0

0

1

a

a
a

a
a
a
a

1

1
1

1

,

0

1

a
a

1

a
a
a
a

1
1

1
1

,

1

1
0

1
1

1

1

a
a

a

,

1

1

1
1

1

a

a
a

1
1

1
1
1

a

1

1
1
1

1

a

1

1
1

1

1

a

a
a

0

a
a

a
a
a

1

1

1
1

a

1

BCDIC

0
1
0
1

a

,

0

E

1
1

a
a
a
a
a

1

,
,

1

1
1
0
0
1
1
0
0
1
1

1
1

,

1

Mel

1
1
1
1

,

1

1

a
a
a

,

0

,
1

a
1
1

a

1

1

1

,

a
1
1

a

0

1

a
0

a
a

62

B,

$:

s:

code conversion tables(con't)

~

N
N

o
,...
BCOIC to ASCII

::xJ
......

FUNCTION
INPUT

OUTPUT

BCDIC,
SYMBOL

ASCII
SYMBOL

64

5P

5P

65
66
67

1

1

ROM
ADDRESS

68
69
70
71
72
73
7.
75
7.
77
78
79
80
81
82
83
84
85

:i

2

3

3

4
5

4

•
7

8
9
0

#

5

•

7
8
9
0

"'

C
0
D

INPUT

ecole

E

B

A

8

•

2

1
1
1

0

0

0

0

0

0
0

0

0

0

0
1

1
1

a
a

1
1
1
1

0
0
0

1
1
1

a
a
a
a

a
a
a
a

0
0

0
0

1

1

0

0

1

a

a

0
1

a

a

1

1

1

1

1

a

a

a

0
1

1

1

a
a

1

a
a

0

0

1

0

1
1
1
1

0

1

1

a

a

0

a

0
1

a

0

1

1

1
1
1

a

a

0
1

1
1

1

a

a

0
1

1
1
1
1

0
1

0
0
1

1

a

a

1
·0

1

1
1

0

0

1

a

1
1

0
0

0

0

a

1
1

,.

a

1

0
1

1
1

1

0
0
0
1

1
1

1
1

a
a

1
1
0
0
1

0
0

a

1
1
1

1

R

lOS
107
108

I
$

!
$

1
1
1

I

1
1

;

;

..

.

1
1

0
0

1
1

1
1

0

o.

1

1

1
0

0
0
1

0
1
1

0

a

1

.1
1
1

0,
0
0

0

a

1
1
1

1

0
0
0
0

0
1

O·

1
1
1

A

a

0

M

1

1
1

0

N

P

a
a

0

N

Q

0

1
1

0
0

.M

P

1

1
1

0

1

Q

1
1

a

0

1

0

1
1

0
1

1

L

104
105

0
1

0

J
K

102
103

1
1
0
0

1

0
1
1
1

1
1
1
1

1
1
0
0

0

1
1
1

1
1
1

1

1

I

1
1

1
1

A
B

1
1
1

1
1
1

1
1

1
1

0
0
0

1

0
0
1
1

1
1

0
0
0

O·
0
1

1
1
1

0
1
1

1
0
0

1

0

1
0
1

1
0

a

a

1

0
0
1
0

0
1
0

1
1

0
0

a

1

0

1

1
1.
1

0
0
0

0
1
0

0
1

1
0
1
0

1

1

0

0
0
1

1
1
1

0
0
0

1
1
1

0
·0

1

0

0
1

1
1

0

0

0

0
1

1

0
1
1

a

1

0
1

0
1

1
0

1
1

0
0

1
1

0

1
1
1

1

0
1
0
1

1

a

0

O·
0
0
0

0
0
1
0

0
1
0
1

0
0

0
1

0
1

0
0

1
1

,

0

0

0

0

1

0

1

0
0

0

1

0

1
0
1

1
1

0
0

0
0

0
0

0
1
1

0
0

1
1

0
0
O.
1

0

0

1
0

1
1

0
0

0
0

1

1
1

a

1

1

0

1
1

1
0
1

1
0

1
1

0

a

a

a

a
a
a

a
a
0

F

F

1

1

1

G

1

1

1

0

1

H

H

1

1

1

1

121
122

,

,

a
a
a

1
1
1

1
1
1

1
1
1

1
1
1

1
1

1
1
1
1

1

1
1

1
1
1
1

0
1

1
1
1

1
1
1

A7

As

As

A4

As

6-41

0
1
1

1
0

1
0

1
1
0

1

a
a

a

.·0
1

0
1
1

a
a
87

1
0

1

1

1
0
1

'12

Al

88

1

a

1

1
0
1

1
1

0

0
1
0
0

0
1

0
1

1
0

a

1
1

0
1

0

1

1

1

0

0

a

a

0
1
1

.,

0
1

0
0
·0
0
0

1

1

1
1
1

1

a

1

a

1
1
1

1
1
1

{J

0
1

a

1
0
1
0

1

1

1

0
0
0

1

1

1

1

G

0
1

1
1
1

1

119
120

0
0
1

1

1

1

118

0
1
1
1

1
0

0
0
0
0

0
1
..

0
0

CR

1

a

1

a

1
1
1

127

0
0
1

a

1
1

a

1
1

%

<

1

0
0

0

0
0

92
93
94

<
i

0

1

1
1

t

I

1
1

0

1
1

I

a

1
1

a
a

a

0
0

12S
12S

a

1
0

0

1

1
1

n

a

1
0

1

1

a

0
1

1

0

a

1
0

0

a

1

0
1

1
1

a
a

0

1
1

0
0

1
1
1

a

Z

J

1
1

1
1

VT

J

0
0

1

Z

123
124

1

1
0

90
91

C
D
·E

0

0

89

D
E

1

0
1

0
0

C

1

0

1
1
1

115

1

1

Y

11.
117

·1
0

0

0
1
1

X·

B

1
1

a

0

W

A

1
0
1

0
0
1

1

y

113
114

0
1
1
0

1
1
1

1
1
1
1

0

0
0
0

1

X

112

a

a

W

I

::0

·1

1
0

8S
87
88

~

a

1

a

0

U

109
110
111

1

1
1
1

0

T

0

a
a

1

T

L

a
a
a

1

V

99
100
101

1
1
1

0

(

J
K

o
,...

0
1

I
5

..

1

a

I
5

-

0

1
1

Blank

-

0

0
0
1

a
a

H.

1

0

1
1
1

V

9S

o·

0

0

a

u

96
97
98

a
a-

0

1
1
1

0

%

a

b,

a

1
1

a

\

1

1
1
0

1
1
1

"2

0

0

1
1

\

1

a
a
a
a

N
N

b3

0
1

0

>

V

a

1
1
1

0
0

0
0

>

1

a

0
0

ASCII
bS
b.

1

0

V·

1

a
a

b6

0

0

,

1
1
1

a

0
1
1

b7

a

0
0

O·
0

@

1

0
1

s:
s:UI

OUTPUT

0
0
1

1
1
1

@

a
a

,

COOE
P
A
R
I
T
Y

0
1
0
1
0
1
0

1

1-

1
1

a

a

1
1
1

1

a

a

0
1

0

0

1

1

0

1

as

85

B4

83

82

8,

o
z
o

MOS ROMs

M
N

Ln

:E
:E
.......

o
z
o
M
N

o:t

:E
:E
a..z
Zz

00
NM
NN
tnLn

:E:E
:E:E
..............
a..Z
ZZ

00
NM
NN

MM4220N P/MM5220NP ,MM4230NN/MM5230NN,
MM4230NO/MM5230NO,7x9 horizontal scan
display character generator
general description
techniques are similar to those described in Application Note AN-40_ DeSigns for vertical-scan fonts,

The MM4220NP/MM5220NP is a 1024-bit read-only
memory and the MM4230NN/MM5230NN and
MM4230NO/MM5230NO are 2048-bit read-only
memories programmed to generate a font of 64
7x9 dot-type raster or horizontal-scan characters_

printer character generators, and designs for fonts
larger than 7x9 are also outlined in AN-40_
For full electrical, environmental and mechanical
details, refer to the M M 4 22 O/M M 5220 and
MM4230/MM5230 data sheets_

The typical application shows the ASCII-address
system_ The display refresh memory, built with
MOS dynamic shift registers, and the TTL control

typical application
7x9 Character Generator System

o:to:t

:E:E
~:E

SUIIAl
OAUOUT

'VIOUI

Note: For additional information refer to AN-40.

h

.u

O·rder Number MM4220NP/J, MM5220NP/J,
MM4230NN/J, MM5230NN/J, MM4230NO/J,
or MM5230NO/J

See Package 11
Order Number MM5220NP/N, MM5230NN/N,
or MM5230NO/N

See Pack.age 18

6-42

:s:::s::
:s:::s::

,

character font

...... .!..._....,e.. :.....;:. :....... ·1·..·: .......
: ..-: : ·
:.:-:.: · . .!...:: ...... ~L..: .1:::.:
.. .
......
110

v--:.

I·..·::

:

11
01001.

"

IODIIDO

"

010l1li0

I

"

110000

..... !.._..-! .....
··:.......
...: reI::. :-:.:..
n

"

010010

101000:

'"

011000

i: :.i

.....

I:....

lOUO,G

•

"

00,000

II
1011110

19
1101110

.: ... . · . ..::_- : ··-..... i: :r ...J: :.i. .i :.--.:
:...::! ·r····!. ••i•• .....i I .... i...... ! . I ···1 i.....!
:.:

"

'11000

"

"

100100

1D

010 t~O

11
110100

12

13

,•

001100

101TOO

011100

....- .....:: ... .. ... .
...••• .i..i ..... ..I
!
"
,.

• :t.-:e.:!
:.: : :

011010

"

GO'OIGD

.. ..

·r

.:

=:~

"

25

111010

100110

"

010 ItO

21
110110

Z8

DDl110

111110

011110

"

1111DO

OD1D.OI."

J7
101001

31

III DIll

111001

0011101

11101[11

41
010"101

•1.

010111

100011

110101

DOll~

101101

"

111110

011101

"

"

010011

"

110011

"

DOlf111

53

101011

011011

55
111011

56
000111

51
100111

"

Otlt111

"

110111

001111

"

101111

62

011111

...... ......

:s:::s::
:s:::s::
NN
WN

"

11000'

00
ZZ
Z"'tI

U'IU'I

.::. ....·· ..- :·-i.... .. .. :.. ..: .:.. :
·...
.......
-:..:- ..:.: .. ii··i.: II
-:111:- ...::...
•••!-.: ....::. .......
: .•. ..:
.,
.. " "
.. "
. . . 1111'" ,
"
"
"'."
. ....•.
. ........ ...
:..... ... .:•••:!
..
.......... ..... ...........
.:1- . .. I ! .:...:.
...
..
:..
:
..
..
·
j
.
.
:i·····:
f:··:;;1
.... .
:.......1 .. :.....: ::::3 ·····1· ·..... e:•••:_
... .
:::::::
••
0101101

~~

NN
WN

"

111111

00
ZZ
Z"'tI

:s::
:s::
~

N
W

o
Z

o
:s::
:s::

......
U'I
N

W

o
Z

Note: Input addresses are in six bit ASCII code and are shown in the sequence Ao. A, ... As.

o

6-43

....

N
N

....

~

o:t

MM4221/MM52211024-bit read only memory

It)

.:!!
:!!
.......
N
N

:!!
:!!

MOS ROMs

NAll0NAL

general description
The MM4221/MM5221 is a 1024-bit static read
only memory. It is a P-channel enhancement mode
monolithic MOS integrated circuit utilizing low
threshold voltage technology. The device is a nonvolatile memory organized as 128-8·bit words or
256-4-bit words. Programming of the memory
contents is accomplished by changing one mask
during the device fabrication.

•

Static operation

•

Common data busing

no clocks required

•

Chip enable output control

output wire AND
capability

applications
•

features

Code conversion

•

Random logic synthesis

•

Table look-up

•

Bipolar compatibility

+5V, -12V operation

•

Character generators

•

High speed operation

<700 ns typ

•

Microprogramming.

block and connection diagrams

Dual-I n-Line Package
INPUT A,
INPUT

"

24

YOD

A~

lSBINPUTA,
LSBounUTB,

INPUT""
.211

'"PUT-. s

OUTPUTB3

OUTPUTS.

"
"

OUIPllTK.
1II0Df
CONTROL
OUTPUTB 7

10

Msa OUTPUT as

CHIP

ENABlE
INPUT""

L.f-4------~~~BLE

Order Number MM4221J
or MM5221J
See Package 11
Order Number MM5221N

See Package 18

Note: For programming informatio'n see AN-l00.

6-44

absolute maximum ratings
VGG Supply Voltage
Voo Supply Voltage
Input Voltage
(V ss - 20)V
Storage Temperature
Operating Temperature MM4221
MM5221
Lead Temperature (Soldering, 10 sec)

Vss - 20V
Vss - 20V
< Y'N < (V ss +0.3)V
_65°C to +150°C
_55°C to +125°C
O°C to +70°C
300°C

electrical characteristics
T A within operating temperature range, Vss

PARAMETER

~

+5V ±5%, VGG

Output Voltage Levels
MOS to TTL
Logical "1"
Logical "0"

6.8 kn ±5% to V GG Plus One
Standard Series 54174 Gate

Output Current Capability
Logical "0"

V OUT

2.4V

100

IGG (Note 1)

TYP

MAX

+0.4
+2.4

T A ~ 25°C
Vss ~ +5V
VGG ~ Voo

f

Address Time (Note 2)

See Timing Diagram
TA = 25°C,
Vss ~.5V
VGG ~Voo = -12V

~

1.0 MHz, Y'N

~

OV

f ~ 1.0 MHz, Y'N ~ OV

1

IJ.A

5
15

25

pF
pF

700

950

ns

Note 1: The VGG svpply may be clocked to reduce device power witholJt affecting access time.
Note 2: Address time is measured from the change of data on any input except mode control or Chip
Enable line to the output of a TTL gate. (See Timing Diagram). See curves fot guaranteed limit
over temperature.

Note 3: The address time in the TTL load configuration follows the equation:

Note 4: Capacitance guaranteed by design.

6-45

V
V

mA
IJ.A

6.8 kn ±5% to V GG Plus One
Standard Series 54174 Gate

T ACCESS = The specified limit + IN - 11 1501 ns
Where N = Number of AND connections.

V
V

12.0
1

6.5

= -12V

Input Capacitance
V GG Capacitance (Note 4)

UNITS

mA

Vss - 4.2

Y'N ~ Vss - 12V

Output AND Connections
(Note 3)

-12V ±5%, unless otherwise specified.

Vss - 2.0

I nput Leakage

TACCESS

~

2.5

Input Voltage Levels
Logical "1"
Logical "0"
Power Supply Current

Voo

MIN

CONDITIONS

~

~

8

a

performance characteristics
Power Supply Current vs
Power Supply Voltages

Power Supply Current vs
Ambient Tempera~lIre
16

16
Voo VGG
TA-25"C

14

Vss '" +5.0V
Voo = VGG-

14
12

12

"Ejl

10

10

"E

8

8

0
0

6

TYPICAl_

6

TYPICAL

4

4
2

2

0

0
16.0

18.0

17.0

-50 -25

Typical Access Time vs
Power Supply Voltages
Voo

~

"'

100

+10"C

]

1200

1

1000

!ll
;::

600

J

+125°C
+25"C

600

e

400

-

~

200

0

+)25'C
+70°C
+2S"'C

800

400
200
0

16.0

lB.O

17.0

16.0

17.0

18.0

Vss - VaG (V)

Vss - VGG (V)

timing diagram/address time
.sv

·sv

.w

I

I

I

OUTPUT By

INPUT AN

.JJL

,v

MM4221fMM5221

ANY TTL/on

E!N

-!l.. io

Vss -2 DV

,V

E,"
+5V

EOUT

pf

~

GATE

125

Von'" VaG

1 JOoo
;::

15

1400

=VGG

1200

800

50

Guaranteed Access Time vs
Power Supply Voltages

1400

J!ll

25

0

AMBIENT TEMPERATURE eCI

Vss - VGG (V)

]

12V

MAXIMUM t-.I.

MAXIMUM

10 pF

I1

S.8K

*"

l

ANY TTL(OTl

GATE

-11v

-=-b
Vss-42V

E-'-'"~

~V~_2'V

,V
.JV

1.5V

,
EmJT

'JV
1.5V

I

OV
time

6-46

"*

..L

15 pF

s:
s:

typical application

,J:.

N
N

...

......

s:
s:

U1

N

128·8 Bit ROM Showing TTL Interface

..

~

}.-

~

feNIP

"

UI"UE

.. OOf
COIITAOL

'

-I

~

..

.,

..
..

"

:

ANYl~~~rTl

"

"
"
'00

I

1
tSee operating mode notes.

"

"

l

1

OPERATING MODES

[;J

128x8 ROM connection
Control - Logic "0"
As
- Logic "1"
256x4 ROM connection
Control - Logic "1"
Aa
- Enables the odd (6 , ... 6 7 ) or even
(6 2 ••. Ba) outputs.
The outputs are "Enabled" when a logic "1" is
applied to the Chip Enable line.
The outputs are connected to ground throu gh an
internal MaS resistor when "Disabled."
Logic levels are negative true MOS logic.
Mode control should be "hard wired" to either
V DD (logical "1 ") or Vss (logical "0").
The logic levels are in negative voltage logic notation.

6·47

~
~

MOS ROMs

NAnONAL

MM4221RQ/MM5221RQ ASCIl-7 to EIA RS244A/
EIA RS244A to ASCII-7
general description
The MM4221 RO!MM5221 RQ is a 1024-bit read
only memory that has been programmed to convert between the American Standard Code for
Information Interchange, compressed to six bits,
and the Electronic Industries Association numerical control standard code, RS244A The second
group of addresses, from 64 to 127, effects the

and substituting the control codes listed for certain
unused ASCII graphic symbols.

In the second 64 entries, the RS244A parity check
bit, C5 is ignored. The bit Ca , used only for the
end of block code (EOB) is used externally to detect existence cif this symbol, and to insert a redundant code, C4 . C2 (ROM address 74). This code
will be translated arbitrarily as an ASCII EXT.

reverse conversion.

applications information
In the first 64 entries, compression of ASCII-7 to
six bits has been accomplished by dropping bit bs ,

typical application
LOW TRUE

LOW TRUE
~

~
ASCII
RS244A

Ascn

I

'"

I

I
I
I

"

...

"

I

...

"

I

~

c,o-I-----I
c, <>-1r------J

I

..
.,

...
'.
"

.

c,

c, o-ir------I

."

UK

c.o------I

INPUT
MULTIPLEXER
CODE
SELECT

4l0W" Graphlt
HIGH" COilirol

0= RSl44A to ASCII
1

~

ASCII 10 RS244A

Order Number MM5221ROIN

Order Number MM4221ROIJ or MM5221ROIJ
See Package 11

See Package 18

6·48

s:
s:

code conversion tables

~

N
N

...

ASCII to RS244A

:xl

P

FUNCTION

ROM
ADDRESS

,

0

2
3
4
5
6
7
,8
9

INPUT

OUTPUT

ASCII
SYMBOL
SP

EIA
SYMBOL

b7

SP

0

0

EOB
EOR

%
&

%
&

8S
HT

BS
TAB

'5

'8
'9
20
2'
22
23
24
25
26
27
28
29
30
3'
32
33
34
35
36
37
38
. 39
40
4,
42
43
44
45
46
47

48
49
50
51
52
53
54
55
56
57
58

+

+

I
0

I

,

0

2
3
4

2
3
4
5

5

,

6

6

7
8
9

7
8

,

"
0

0
0
0

b4

b3

b2

0
0
0
0
0

0
0"

0
0

0
0

,

b,

c8

c7

CS

,
,
, , ,

0

0

0
0

0
0
0
0

0

0

0

0

I

0
0

,

0
,0

a
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

FS
GS

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

UC
LC

0
0
0

,

c4

c3

"2

",

0

0

0

0

0
0

0
1

0
0
0

0

cS

0

•

0

9

0

0
0
0

,

,
,

0

0
0

0
0

, ,

0
0

0

0

c!
0
0
'0

,
0

, ,
,
0

0
0
0
0

0

0
0
0
0
0
0
0
0

0
i
0
0
0
,0
0

0
0
0

0
0

0
1
0
1
1
0

,0

0
0

, ,

,
,

1
1

, , ,

"
0
0

0
0

0

0
0

d

a

a

b

b

c

c

d·

d

e

f

9
h

;

i
k
I

m

·
·
f'

h

;

i

•
I.

m

n

n

0

b

0
0
0
0
0

p

p

0

q

q

r

r

0
0
0

,

·
t

0

u

0

v

v

0

w

w'

c!

x

x

V

V

0
0

t

u

,

,

I

0
0
0
0
0
0
0
0

0

1

~
0

,DEL

DEL

0

A7

0
0
0
0
0

I
I
I
I
,
As

0
0
0
0

0
0
0
0
0
0
0
0
0

I
I

rt

•
AS

A4

A3

649

1
1

A2

1

1
1

0
0
1
0
0

, ,
, , ,

,
, ,
,
,
1

0

I

0

1

0
0
0
0
0
0

I

0
0

, ,

0'

Increasing Binary
Sequence

,

1
0
0

,
1
1
1

0
0
0
0
0

1

0
0

"

1

,
0

0
0
0
0
0
0
0

0
0

1
1
0
1
0
0
1

,
0
1
0

,
, ,
1

,
,
1

,
1

0

, ,
, , ,
,
,
,
, ,
,
, ,
, ,
,
, ,

0

0
1

,

, ,
, ,

0
1

1

0
0

0
0

0
0
0
0

0

0

0
0
0

1
0

,
,

0
0
1
1
0

,

0
1

,
,
,
, ,
, ,
0
0

0

0
1

0
0

0

0
0

,
0

~
~
0

59
60
61
62
63

0

0
0
0
0

bS

OUTPUT

d

'2
'3
'4

'6
17

0
0
0
0

INPUT

0

'0

"

COOE
C
0
0
E

ETX
EOT

......

0
1
1
0

,
0

0
0

,

0
0

0
0

0
0

0

0
0
0
1
1

,
, , ,

0
0
0

"
0
0
0

,
1

1

0
0
0
0
0

0

,

0
0
0

0
0

0

0
0
1
1

0
0,
0
1
1
0

,
,
, ,

1
1
0

0

0

1
0
0
1
1

0
1
0
0
0

,

0

,
,
0

0

1

0
1
0

,

0

0
1
0

1
1

0
1
1

0
1

0
0

0
0

,

,

\

0

,

1

1

·1

1

A,

B8

B7

B6

B5

B4

B3

,
0
1

, ,
B2

B,

s:
s:U1
N
N

...

:xl

P

oex:

N

code conversion tables(con't)

N
It)

:e
:e
......

RS244A to ASCII

oex:
po

N
N

'It

:e
:e

FUNCTION

ROM
ADDRESS
64

OUTPUT

EIA
SYMBOL

ASCII
SYMBOL

Space

Spac;:e

1

1

2
3
4
5
6
7

2
3
4
5
6
7

8

8

9
EOB
EOR

ETX
EDT

o

65
66
67
68
69
70
71
72
73
74
75
76

CODE

INPUT

9

&

&

79
80
81
8'2

0
1

0
1

83
84
85

t

t

u

u

,

96
97
98
99
100
101
102
103
104
105
106
107
108
109

,

v

v

w

w

.

86
87

92
93
94
95

v

,

BS

·,
v

BS

115
116
117
118
119
120
121

1
1
1
1
1
1
1
1
1
1

INPUT

.<6

"4

c3

<2



"

B,r-----1I--_;-_;--t--t--t--q

"
l5B

B, ...,.,.....:._;-_;~_;-_;--t--+--t~c:f::>--o7 lSS

"

UK

UK

6.aK

UK

6.8K

&.BK

-11V

Order Number MM4221RR/J or MM5221RR/J
See Package 11
Order Number MM5221 R R/N
Se. Package 18

6-5~

.

UK

UK

a::
a::
N
('II

code 'conversion tables

Ln

~
~
.......

a::

...a::

FUNCTION
OUTPUT

ASCII

EBCDIC

SYMBOL

SYMBOL

MSB

NULL

NULL

0

0

0

0

0

SOH
STX

SOH

0

0

0

2

STX

0

0

0

0
0

0
0

3

ETX

ETX

0

0

0

0

ROM
ADDRESS

('II
('II

~

~

~'

CODE

INPUT

0
1

INPUT

OUTP'UT
LSB

MSB

0
1
0

0

0

0
0

0

(>

0
0
1
1

1

0

0

LSB

EDT

0

0

0

0

1

0

0

END

END

0

0

0

!

0

0

0

ACK

ACK

0
0

0
1

0

5
6

0

0

1

0

BEL

BEL

0

0

0

1

1

1

0
0

0

7

0
0

1

0
0
0
0
1
1
1

0

8

: 0

1

0

0

0

0

1

0

0

0
0'

1

0
0

0

1
1

1
1

1

0

1
0
1
0
1
0

4

EDT

BS
HT

BS
HT

0

9

0

0,
0

10

LF

LF

0

0

11

VT
FF
'CR

VT
FF

0

0
0

12
13

0

0

1

0

51

51

0
0

0
0

,0
0
0'

1

SO

'CR
'SO

0

14
15

1
1

1
1

1
1

16

OLE

OLE

0

0

1

0

0

0

0

17

DCl

DCl

0

0

1

0

0

0

1

18

DC2

DC2

19

DC3

DC3

20
21

DC4
NAK

RS
NAK

22

SYN

SYN

23

ETB

EOB

24

CAN
EM

CAN

25
26

SUB

SUB

27

ESC

BYP

28
29

FS
GS

FLS

30

RS

RDS

3'
32
33

US
SP

US
SP

!
"

!
,.

36

#
$

#
$

37

%

.

..

34
35

38,

,

I
I

EM

CONTINUING BINARY
SEQUENCE

0

(

4'
42

)

43

+

+

46

I
0

0

1

1

50

2

2

5'
52

3
4

3
4

53

5

5

54
55

6
7

6
7

56

8

8

57

9

9

58

I

;

;

60

<

'<

6'
62
63

>

>

?

?
A7,'

1

1

1

1

0

1

1

1

1

0

1

0

1

1

1

1

0
1

1
0

1

1

0

0

0

0

0

0
0

0
0

0
1

0

1
,1

0

0

0

0

0

0

0

0

0
0
0,

0
0
0

0
0
1
1

0

0

0
0

0
0

0
0
0
0
0

0

0

0

0

0
0

0
0

0

, , ,
,
,
, ,
, ,
,
,
,
,
, , ,
,

0
0
,0

0
0
0
0

,,,
0

,
,
,
,
,
,
1

0
0
0
0

6·52

0

1

0

A1

1

1

0
0
Ba

0

1

0

0

1

0

0

,

0
0

1

0

1

1

1

0

1

1

1

1

1

0

1

1

0

0

,

0

1

0
1

0
1

1

1

0

0

0
1

0

0

0

0

1

1

0
0

0

0

0

0

0

0
l'

1

1
1

0

1

0

1

,
,

1
0

0

1
1

0

,

,
, ,
,
,
,
,
,
, ,
, ,
,
,, ,
, ,
, ,
, ,
, ,
,
,
, ,
, ,
0
0
0

1
0

1

1

1

1
1

0

0

B7

1
0

0

0

1

0

0

1
1

, ,

1

1

1

1

0

1

1

1
1
0
1
0,

, ,

0

0

1
0
1

0

0
1
1
1
1

0

0

0

0

0

IAs I As IA4 I A d A2 1

1

0

0

,

0

(I

0

I

0

1
.0

0

.

0

0

0

I

0
1

0

0
0

I

,

59

0

0
0

0

0
0

0
0

0

0
0

0
0

0

0

I
I
I
I
I
I

44
,45
47
48
49

0

0

0

0

I

39
)

0

0

0

0

I

%

{

,

0

0

0

I
I

GS

40

,

0

0

1

116

1

1
1
0
1

0
1

1
1

,

1

0

0
0

0

, ,
0

,

1

,

0

,

0

0
0

0

1

,

1

, ,

0

0
0

0
1

0

0
0

1

1

,
,

1

0

0

0

0

0

,

0

1

, ,

1

, ,
1

,

,

0

1

0
0

1
1

0

0

,

1

1

0

"

0

0

1

1

0

0

0

0

1,

0

,

0

0

,

0

0

0
0

0,

,

0

0

0

1
1
1

0

0

1
0

0

1

0

1
1
1

0

0

,
,

0

0

0

,

0

0

0
1
0

0

0

1
1

0
1

0
0

1

as

B4

1

0

1

0
1

,

0

,
,
,
,
,
,
,
,
,
,
, ,
,
,
, ,
, ,
,
0
0
0
0

,
,

B3

,

0

0

0

0

1
1
1

0

B2

B,

0
1

code conversion tables(con't)

FUNCTION

"

INPUT

OUTPUT

ASCII
SYMBOL

EBCDIC
SYMBOL

6'
65
66
67
68

@

@

D

A
B
C
D

69
70
71

e

e

F

F

G

G

72

H

H

73

I
J

I
J

K

K

L
M
N

N

0

0

ROM
ADDRESS

7'
75
76
77
78
79

A
B
C

P

P

Q

Q

82
83

R
S

R
S

8'
85

T

T

U

U

86
87
88

V

V

W
X
y

W

Z

Z

I

I

\
)

NL

93
9'
95

1\

d

e
f

Q

9

h
;

h

106
11;)7
106
109

j

j

k

k

113

""

115
116
117
118
,,9

120
121
122
123
12'
125
126
127

I

m
n

m
n

0

0

P

p

.

q

t

t

u

u

v

v

,

0

w

w

x
y
z

I

,

I

-

I

I

.

0

I

0

I

o

I

MSB

0

0
1

1
1

1
1

1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

CONTINUING BINARY
SEQUENCE

1

,
,

x
y
z

DEL

I

LSB

I
I
I
I
I

;

I

q

o

.-

f

110
111
112

I

J

e

100
101

b

1

y

102
103
104
105

c

a

,

x

RES
a
b
c
d

96
97
9B
99

OUTPUT

MSB

L
M

80
81

89
90
91
92

CODE
INPUT

i

"

DEL

A7

1

0

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

0

1
1
1
1
1
1
1
1
0
1

0
0
0

0

0

0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1

I As I As I A.c I I
A3

A2

I

A,

0

0

0

l'
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
0
0
0
0
0
0
0
0

0
0
0

0

0

0

0
0

0
0

0
0

0
1
1
1
1
1
1
,1
1
1
0
1

0
1

0
0
0

0
0

0
0

0

0
0
1
0
1

0

0
B7

0
1
1

1

0

0

1

1

0

1
1
1

0

0
1
0
1

0
0
0
1
1
0
0

0
0
0

1

0
0

0
0
1
1
1
1

0
1
1

0
0'
1
1
0

0
1
1
1
1
1

1
1

0

1
1
1

1
0

0

0
1

1
1
1
0

0
1
1
0

0
0

0
0
0

,
1

0

0
0

0

0

0
0

0

0
1
1
1
1

0
0

0
0

1
1
0

lis

85

84

1
1
0
0
0
0
0
1
1
1
1
0
0

1

0
0

1
1

0
0
1
t

0

0

0
1

0
0
0

1
0
1

0

0
0
1

0

0
1
1

0
1
1
1

0
0

0
1

0
1

0
0

il

0

0

1
1

'0
0

1

0
1
0
1

1

1

0
0

0
0

0
0

0

0
0

0

1
1
0

0
1
0
1

0

0

0
0

0
1
1

0

0
0

0
1
1
1
1
1
1
1
1

0
0
0
1
1

0

0

0

0

0

1
0
1

0

1

0
0

0

0

0
0

0
0
0
0
0
0
0
0

0
0
0
0
1
1

1
1
1
1

0

0
0

1
1
1
1

0
0
0

0

0
0

0
0
0
0
0
,0

1
1
1
1
1

1

0
0
0
0

0
0

0

0

Bs

0

0
0

0

0

1

0

0
0

1
1

0

0

0

0

,
,
1
1
1

0
0

1
0

1
1
1

0
0

1

,

LSB
1

0

0

1
0

0
1
1
0

0
0
1
1

0
0
1
1
0

0

1

1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1

0
1

,

0

0
0

,
1

0

1
1
1
1

0

0
1

1
1

0

0
0
0

0
0

0

0

1
0
0
1

1
1
1
1
t

83

B2

1

1
1
1
1
1
0
1

B,

~

MOS ROMs

NA110NAL

MM4229/MM5229 3072-bit read only memory (open drain)
general description
.. Programmable chip select inputs

The MM4229/MM5229 is a 3072-bit static read
only memory. It is a P-channel enhancement
mode monolithic MOS integrated circuit utilizing
low threshold technology. The device is a 'nonvolatile memory organized in a 256 x 12 bit
word configuration.

.. Typical 1.01Ls access time
.. Open .drain outputs allow wire-OR of up to
8 devices

applications

Customer programs may be supplied on Hollerith
coded punched cards.

.. Code conversion

features

.. Random logic synthesis

•

TTL compatible

.. Table look-up

•

Low standby power

.. Microprogramming

block diagram
10

connection diagram
Dual-I n-line Package

,
OUTPUT 12 1

.. c

OUTPUT 11 2

Zl AI

OUTPUT 10 3

.. A,

DurpUH 4
OUTPUT B 5

.. A,

OUTPUT7

&

23 Vss

OUTPUT I

7

22 A,

OUTPUT 5

B

21 A.

za As

OUTPUT 4

9

OUTPUl3

to

19 A,

OUTPUT Z

n

" Ne

neE

OUTPUT' 12

16 CS,

Voo 13

15 CS2
TOP VIEW

Note: For programming
information see AN·100.

Order Number MM4229D
or MM5229D
See Package 7

6-54

Order Number MM5229N
See Package 19'

11

12

absolute maximum ratings
All Inputs or Outputs with Respect to the
Most Positive Voltage Vss (Substrate)
Supply Voltage Voo arid Vo with Respect
to Vss (Substrate)
Operating Temperature Range
MM4229
MM5229
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)

+O.3V to -20V
+3,OV to -20V
-55°C to +125°C
-25°Cto+70°C
-65°C to +125°C
300°C

electrical characteristics

(Note 1)
TA within operating temperature range, Voo = -12V ±10%, Vss = +5V ±5%, unless otherwise specified.
PARAMETER

CONDITIONS

MIN

TVP

MAX

UNITS

Data Input levels
Logical High Level (V'H)
Logical Low Level (V'L)

= +4.75V
= +4.75V

Vss
Vss

+0.8

V
V

+0.4

V
V

+2.4

Data Output Levels
Logical High Level (VOH I
Logical Low Level (VOL)

6.8 k!.l ±5% to Voo Plus One
Standard Series 54/74 Gate

Output Current Capability
Logical "0"

V OUT

Data Input Leakage IIA,)

V 1N

Data Output Leakage (I AO)

V OUT - Vss

Data Input Capacitance (C IN )

V'N - Vss

Data Output Capacitance (C OUT ')

V OUT - Vss

~

= 2.4V

+2.4

2.5

mA
2.0

IJ.A

2.0

IJ.A

5.0

pF

B.O

pF

1.0
0.8

1.4

1.2

IJ.s
IJ.S

25
25

32
32

mA
mA

2.0
2.0

IJ.A
IJ.A

18
18

mA
mA

Vss =::-5V

= -5V

(Note 1)

= OV
= OV

Access Time (T A)

Address Response (t AA I

CL
CL

C Inhibit Response (tAC)

= 20 pF
= 20 pF

Active Power Supply

Vss = +5V, V, = OV
Voo = 12V, TA = 25°C

Voo Supply 1100)
Vss Supply (Iss)
Data Input Currents
Logical High Levelll,H)
Logical Low Level (I,c!

V'N - Vss
V'N - Vss

= -2.4V
= 5V

Standby Power Supply
Vss = +5V; V, = OV
Voo = -12V, TA = 25'C

100

Iss

Note 1: Chip inhibited

12
12

orde~selected.

Note 2; The abOve logic levels are. indicated in negative logic notation.

switching time waveforms
-'~{-----I-----1.5V
I
I

~I/.'----i-----

l--tAA---J

I---- tAC----1

_____ ~'.5V
J

-----.11

I

1

I

I

I
I

I I r----

------t-------~
I .
\
I
,\..':::__ _

____ J ____ ~\..'_.5_V

__

Definitions:
Access T,me: Represents the total propagation delay through input translation decode for memory !;election and output sense amplification of the
memory signal and is measured from the last input traftSition through 1.SV to the last output transition through 1.SV.
Chip Enable: The output source and sink trilnsistor!!
memory expanSion.

an~

turned off in the chip inhibit ilnd chip de-select mode to allow OR·tieiflg of output for easy

Chip Select: The Olllputs are enabled and data hom the selected memory location will ippear at the outputs. The chip select and chi, enabr", inputs
are progr~mmilble for decoderless word el(pansioll.

6·55

~

~

MOS ROMs

NAll0NAL

MM4230/MM5230 2048-bit read only memory

general description
The MM4230/MM!5230 is a 2048-bit static read
only memory. It is a P-channel enhancement mode
monolithic MOS integrated circuit utilizing low
threshold voltage technology. The device is a nonvolatile memory organized as 256-8 bit words or
512-4 bit words. Programm ing of the memory contents is accomplished by changing one mask during
the device fabrication. Customer programs may be
supplied in a tape, card, or pattern selection format.

Bipolar compatibility

•

High speed operation

Static operation

•

Common data busing

no clocks required

•

Chip enable output control.

output wire AND
capability

applications
•

features
•

•

500 ns typ

Code conversion

•

Random logic synthesis

•

Table look·up

•

Character generators

•

Microprogramming.

block and connection diagrams

SENSE AMPLIFiERS

OUTPUTS t

Dual-In-Line Package

81 (LSB)
(UB) A,

INPUT AJ

A,

B,

B,

"
"

INPUT A,

lS8 INPUT A,

..
A,

He

22

INPUT A.

lSB OUTPUT R,

B,

Vee

OUTPUT 8,

"

OUTPUT BJ

19

INPUT -'6

OUTPUT 84

18

INPUT A1

INPUT A5

B,
B~

"

INPUT ~ MS8

OUTPUT B,

1G

V••

OUTPUT81

"

OUTPUT

B,

B.
USB OUTPUT 88

ENABLE

INPUT At

V"

. ,---....

TOP VIEW
CHIP

---'

MODE CONTROL

MODE
CONTROL
CHIP

ENABLE-

-~~~~L-./

Ord.r Nu mbar MM4230J
orMM5230J

See Package 11
Order Number MM5230N

See Package 18

Note: For programming information see AN-100.

6-56

s:
s:

absolute maximum ratings

~

N
W
VGG Suppry Voltage
Voo Supply Voltage
Input Voltage
(V ss -20)V
Storage Temperature
Operating Temperature MM4230
MM5230
Lead Temperature (Soldering, 10 sec)

<

o

Vss -30V
Vss -15V
Y'N < (V ss +O.3)V
-65°C to +150°C
_55°C to +125°C
O°C t~ +70°C
300°C

.......

s:
s:

U1

N

W

o

electrical characteristics
TA within operating temperature range, Vss = +12V ±5% and VGG = -12V ±5%, unless otherwise specified.
PARAMETER
Output Voltage Levels
MOSto MOS
Logical "'"
Logical "0"

CONDITION

, Mf! to GND Load (Note')

MIN

TYP

MAX

UNITS

V"s -9.0

V
V

+0.4

V
V

Vss -8.0

V
V

Vss -1.0

MOStoTTL
Logical "'"
Logical "0"

6.8 kf! to VGG Plus One
Standard Series 54/74 Gate lripu,t

+2.4

Input Voltage Levels
Logical ","
Logical "0"

Vss -2.0

Power Supply Current
Vss
VGG (Note 1)

TA = 25°C

Input Leakage

V'N=Vss-12V

Input Capacitance

f= 1.0MHz

Access Time (Notes 2, 3)

TA = 25°C
(See Timing Diagram)
Vss = +,2V VGG = -12V

T ACCESS

Output AND Connection

24

V,N = OV

MOS Load
TTL Load

40
1

rnA
/JA

i

/J A
pF

5
150

500

725

'ns

3
8

Note': The VGG supply may be clocked to reduce device power without affecting access time.
Note 2: Address time is measured from the change of data on any input or Chip Enable line to the output of a TTL gate.
See Timing Diagram.

Note 3: The access time in the TTL load configuration f,ollows the equation: TACCESS = the specified time + (N - 1) (50) ns
where N = number of AND connections.

Note 4: The above logic levels are indicated in negative logic notation.

6·57

a

performance characteristics
Typical Access Time vs
Supply Voltages

Guaranteed Access Time

vs Supply Voltages

_11

13

~

I-

e

1000

T•• ~

T~

800

]

j j

T•• 12So

1000

800

A
g600

600

400

>-400

200

200

10_8

12_0

13.2

125°C
I I
}il"e

-j

j~

t--;

5

10.8

12.0

13.2

VS$8t VGG IV)

Vss & VOG IVI

Power Supply Cu rrent

Power Supply Current

vs Voltages

vs TempJ!rature
60

TA "-25°C

Vss :: +12.0V

40

..:s

F-bY-

MAX

50

36

..:s

32

c

.E 28

J

TYPICAL -

24

40

VGG =-12.DV

MAX

T""l-iVPICAL

30

-

l""-

l"""

r-

20
10

20

0
10.8

12.0

13.2

-50 -25 0 25 50 75 100 125 150

Vss & VOG (V)

TEMPERATURE lOCI

timing diagram/address time

+lv .

.,.I

+JTL

.

I

3.0K

INPUT~

.,

I

OhOUTPUT~

MM423D/MMS230

DV

DM8810

' '-=rIO,'

'1

-.1-

I

f

".

""$

ANY OTL/TTL
GATE

-'!V

+12V

~
EITHER

',.

DV
+12V

f:'=-'-~
~

.,v ~
DV

U.

0

'00'

.'v
1.5Y

0.

I
timo

6-58

:E'5

'00'
,F

typical application

256 x 8 Bit ROM Showing TTL Interface

tSee operating mode notes.
*R values an vary from 740n to 30 kn.

OPERATING MODES

128x8 ROM connection
Mode Control - Logic "0"
As
- Logic "1"
256x4 ROM connection
Mode Control - Logic "1"
As
- Logic "0" Enables the odd
(B, ... B7 ) outputs
- Logic "1" Enables the even
(B 2 ••• B8 ) outputs.
The outputs are "Enabled" when a logic "1" is
applied to the Chip Enable line.
The outputs are connected to VD D through an
internal MOS resistor when "Disabled."
The logic levels are in negative voltage logic notation.

6·59

MOS ROMs

~
NAll0NAL

MM4230BO/MM5230BO, MM4231BUS/MM5231BUS
hollerith to ASel! code converter
general description
The MM4230BO/MM5230BO 2048-bit MOS ·readonly memory has been programmed to convert the
12 ·line Hollerith punched card code to eight level
ASCII. This conversion conforms to the American
National Standard (ANSI x 3.26 - 1970). Three
TTL 4-input NAND gates, and three inverters are
used to compress the 12 Hollerith lines to eight·

line binary encoded form suitable for use by· the
read-only memory. 'This application is shown
below.
For electrical, environmental and mechanical details, refer to the MM4230/MM5230 or the
MM4231/MM5231 data sheets.

typical application
'

4 IfW'UTMIIO GATES ARE
OMJ430TY'ES

..

MODE
COlfTROL
DUTl'UT.

ASCII_'

E,

",

E,

E,

.

PUNCHED
tARO
DATA

"'"

PU~~~~

""

E.

•_ _ _ _ _-----------_.....!A:j6 19

E,

( 11 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.....!:.j

..

12_ _ _ _ _ _ _ _ _ _ _...:.._ _ _ _ _.....!:j

~

AMYDTLlTTL
DEVICE

Note 1: Vss" +12V ±lO%, Voo = GND. VGG '" -12V !:1D%.
Note 2; The Hollerith input data (lines 1 through 12) is considered to be from

normally 'open swittlhes returned, in the

C85e

of I punched hole, to GNU as shOWfl.

connection diagram
Dual-In-Line Package

A,

A,

....

.

"

...

.."

A,

...

"
'.
"

,~

MODE

CONTROl
CHIP
EPlABLE

"
,~

"

.
rap VIEW

6·60

Order Number MM4230BO/J
MM5230BO/J. MM423.1BUS/J
or MM5231 BUSIJ
See Package 11
Order Number MM523OBO/N
or MM5231BUSIN
See Package 18

HIGH
TRUE

code conversion table
,Hollerith to ASCII

12

12

12
11

11

0

8-2

0

&

-


 =

8-7

!(j)

A@

?

$

8-3

(j) may be

"I"

®mav be"'"

"

13/7

Not.: The entries of Form AlB refer to the unassigned locations in the right hand side of the ASII table
(bit E8 = 1) designated for specialist use. (See National Bureau of Standards Technical Note No. 478.
Note: For the full ASCII-8 Code Table, see MM4230QY IMM5230QY data sheet.

•
.

I
I
I
I

6·61

MOS ROMs

~

NAnONAL

MM4230FE/MM5230FE selectric-to-EBCDICI
EBCDIC-to-selectric code converter

general description
counterparts, it is not necessary to encode bit
position 0 (A8). which is used instead as the code
converter selection bit. In addition to the Selectric
Correspondence output code bits there is a bit to
indicate upper or lower case. The odd parity bit
generated does not account for the case bit.

The MM4230FE/MM5230FE provides for the conversion of IBM Selectric Correspondence Code to
Extended Binary Coded Decimal Interchange Code
(EBCDIC) in both directions. These two decoders
are contained on a monol ithic MOS device.
The Selectric-to-EBCDIC converter is located in·
binary addresses 0 through 127. Input bit A7 is
used as a single line command to determine
whether upper (denoted by a "1") or a lower
(denoted by a "0") case has been selected.

device characteristics
For full electrical, environmental, and mechanical
details refer to the MM4230/MM5230 204B-bit read
only memory data sheet.

The EBCDIC-to·Selectric converter is located in
binary addresses 128 through 255. Since not all
EBCDIC control commands have Selectric code

connection diagram

typical application
-lZV1k _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

Dual-In-Line Package

.....- ,.

~-

A,

"
A,

A,

A,

,

•
IWM23UFEI
MIII!i23DFE

A, "

.. "
A,

UK.
TYPICAL,

A,

I LINES

I,

"

I,

20

A,
A,

,

I,

I,

A,

I,

" "

..
.
..

I,

..
, ..
I

"
"
"

I,

11

I,

"

"8 11
OMUI2
TTL GATES

---

Voo

I,

2

e

i

Yo.

I,

3

A. 21

l!I

.

.,

... lZVIk----~~....__.

-1211 de

V,\;

MODE
CONHIOt

ttilP

fNABLE

13

V"
TO.I/IEW

I,
DM7480SERIES
TTL GATES

Order Number MM4230FE/J
or MM5230FE/J

Sea Package 11

+12Vdc-====~
*Chip Enable'" logic "1" to obtain outPUH.
Logic levels:
OnmL (elCcept at MUS/ROM inrerface). logic "1," +5.0V, NOM. Logic "0" ground. NOM.
MaS/ROM inputs and outputs. l~ic "'," more negltive, logic "0," more positive.

6-62

Order Numbar MM5230FE/N

See Package 18

s::
s::~

code conversion table-selectric-to-EBCDIC

N
W
FUNCTION
INPUT

OUTPUT

ROM
SELECTRIC EBCOIC
SYMBOL
ADDRESS SYMBOL

0
D
E

Q

-

-

1

b

2
3
4

b
w'

w

9
q

9
q

5
6

k
;

k
;

7
8

6

6

0

y

V

0

9
10

,

,

h

0

11

0

0

P

P
e

0
0
0
0

5

12
13
14
15

.
5

16
17
18
19
20.

z

z
NULL
NULL

32
33

34

NULL.

35
36
37
38
39
40

NULL

. .

41
42
43

c

c

II

8

I

I

I

I

0

0

4

4

44

;

;

45
46
47

d

d

,
7

48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

,

7
NULL
NULL
NULL
NULL

f

f

u

u

v

3

v

3

0
0

0
0
0
0
0
0
0
0
0
0

0

0

0

0

0

0

0
0
0

0
0

0
1

1
1
1
1
1

0
0

,

0

1

1

0

0
0

1

0
0

0
1
1

0

1
0
1

1
0

0
1

0
0

1

1

0
1
1

1
0
0

,

0
0

0
0

0
0

0
0

1

0
0

1
1

1
1

0

0
0
0
0
0
0

0
0
0
0
0

0
0

0

1

0

0

0

0
0
0
0

0
1

1
1
1

0

0

0

0
0
0
1
1
1

0

0

0
0

0

0

0
0

0
.0
0
0

0
0
0
0

0

0
0
0

0
0
0
0

0

0

0
0
0

0
1
1

0
0
0

1
1
1
1
1
1
1

·0
0
.0
0
0

0

0
0
0
0
0
0
0

0
0
0
0
0

0

NULL.

0
0

0

9

0

0

x

x

0

0

m
1

,

0
0

0

0
0

1
1

0
0

0

0

NULL

m

0
0

0
0

0

9

1

1

0
0

NULL

NULL,

0
0
1

1

1

0
0

0

0

0

1

0
0

0
0
0
0
0
0
0

0
1
1

0

0
1
1

0
0

0
0

7

0

0
0

j

6

0

0
0
0
0
0
0

t
NULL

5

0

0

0
0
0
0

EBCDIC
3
4

0

NULL
NULL

NULL

2

0
0
0

NULL

NULL
NULL

1

0

0

0
0

0

0
0

0
0

2
NUL.L.

T2

Q

0

2

T1

0

0

23
24
25

SELECTRIC
R2 R1 R2A

0

0

n

m

.......

OUTPUT

0

0

n

t

0

0

21
22

j

0
0

RS

o·

-

26
27
28
29
30
31

0
0
0
0

C
A
S
E

NULL

=

."

INPUT

C

h

o

CODE

0

1
1
1

0
0

0
0

0
0
1
1

0

0
1

1
0
1

0

1
1
0
0

1
1
0
0

1
1
1

0
0
0
0

0
0

1
1
0
0
1

1
1

0

1

1
1

1
1

1
1

1
1

1
1

0
0
0
0

0
0
1
1

1
1
1
1

1
1
1
1

1
1
1
1

0
0
1
1

1
0
1
0
1

0
0

0
0

0

0

0

0

0

Q

0
0
0
0
0
0

0

1
1
0
0

1
0
1
0
1

0
0
0

0
0
0
0
0
0

0

1
.1

1
1
1

0
1
1
1
1
0
0

0
0

1

0
0

1
1

1

0

1
1

1
1

0

o·

0
0
0

1
1
1
1

1
1
1

0

0

0

1
1

1
1

0

1
1
1
l'
1
1
1

0
0
1
1
1
1
1
1
1
1

0
0
1
1
1
1

Q

1

0
0

1
1
0
0
1
1.

0

0

1
1
0
0

0

0
0
0

0
0
1

0
0
1

1
0
1

1
0
1

0

0

1

0
1

0
1

0

0
0
0
0
0
0

1
0
1

0

0
1
0
1
0
1
0
1

0
0
0
1
1
0
1
0
O.

g

1

0
1
1

0
0

0

1

0
0

0
1

0
1
1
0
0
1
1

A2

1

0

.0

0
0

0
0
1

0

0
0
0
1
1

0
0
1
1
1
0

0

0
0
1

0
1

0
0
0
0
0
1
0

0
0

1

0

0
1

0
0

0

0

0

0

1

0
1

1
1

0

0
0

0

0

0

0

0
0

0

0
0

1

0
0

1
1
1

0
0

0

0
1

0

0
0
0
0
1

1
0
0

0

B2

B,I

0
0

0
0

0

1

1
0
1

0
1
1

0
0
0

B7

B6

B5

B4

B3

1.

0

1

1
1
1
0
1
1

1
1
1

0

0
0

0

0

0
1
0
1

0
0
0
1
1
1
0

1

1
0
0
0

0

0
0
0
0

0

0

1

0

0
0
0
0
0

1

0
0
0

0
0
0

0
1
1

0

0

0
0
0
0
0

0

0

0
0

0
1
1

0

1
0
1

1
1

0
0

0
0
0

0
0

0

1
1
0
0

1
1

0

0
0

1

1
1

1

0
1
1

0
0
0

0
0

0
0

0
0
1

0

1
1

0

0
0
0

0
1

1
0

1

0
0

0
0

0

0

0
0

1

0
0
0
0

0

0

0

0

0

0
0
0
0

0
0

1
1

0
1

0
0
0
0
0
0

0

1
1

1
0

0
'0

0
0
0
1
0

0

0

0
1
0

1

0
0
1

0

0
0

1

1
0
1

0
0
0

1

1

0

o·

1
0

0

0
1

0
1

0

0

0

1
0

0
1
0
1

O·

0
0

0

0

1
1

0
0

0
0
1

1

1
1

0

1
0
1

1
1
0
.0

0

0
0

0
1
1
1

1

0

0

1
1
1

0

1

0
0
0

1

0

'0
0

0
0

1

0
0
0
0

0
1
1
0

0
0

0
0
0

0
1
1

0

1

0
0

1
0

1
1

A3

1

1
0

A7

6-63

0
0

0

lAS

A4

0

0

1
0

128

AS

1

0
0
0

0
1

0
0
0
0
1
1
1

1
1
1
1
1
1
1

0
0
0

0
1

1
1
1
4
2
64 32
16
8
IROM ADDREss IN BINARY I
0

As

1

1
1

1
1
1
1

1
1
1
1
1
1
1
1

0
1
0

1
1

1
1
1

1
1

0
0
1
1

1

1
1

0
0

0
0
1
1
0
0
0
0
1
1
1

1
A11 IBS

s::
s::
01
N

W

o

."

m

w

u.
~

code conversion table:.....selectric-to-EBCDIC(con't)

N
LC)

::i

FUNCTION

~
.......

w
u.

o(f)
N

~

::i
::i

INPUT

CODE
INPUT

OUTPUT

SELECTRIC EBCDIC
ROM
ADDRESS
SYMBOL
SYMBOL

-

-

B

B
W

C

C

0
D
E

A

(

(

68
69
70

a

a

0
0
·0
0
0

K

K

0

I

I

71
72
73

•Y

•Y

H
S

H

0
0
0
0
0
0

64'
65
66
67

74
75
76
77
78
79
80
81

82
83
84
8S
86
87
88
89
90

W

)

P
E

.

%

..

%
NULL
NULL
NULL

NULL

+

+

N

N

@

.,

.2
93
94
95
96
97
98
99
100

S

)

P
E

J
T

Z

.

@

NULL
NULL
NULL
NULL
J
T
NULL
Z
NULL
NULL
NULL
NULL

101
102
103

C

10.
105
106
107
108

?
L

?

0

0

$

,

$

0
R

0
R

&

&

10.
110
111
112
113
114
115
116
117
118
11.
120
121
122
123
12'
125
126
127

A

C
A

.
L

,

NULL

NULL
NULL

F
U

NULL
F
U

v

V

#

#
NULL

G
X
M

+

NULL
NULL
NULL
G
X
M
NULL

0
0
0
0

a
a
0
0
0
0
0

a
0
0

a
a
0
0
0
0
0
0
0

o·
0
0
0
0
0
0
0
0
0

a
0
0
0
0
0
0
0

a
0
0
0
0
0
0
0
0
0
0

S
E

R5

1
1
1
1

0
0

1
1
1
1
1
1
1
1
1

,.

1
1
1
1
1
1
1
1
1
1

a
0

a
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0

a
a

SELECTR'IC
R2
R1 R2A
0
0
0

0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1

a

1
1
1

0
0
0
0
1
1
1
1
1
1
1
1
0

a
a
0

a
0

1
1

0
0

1
1
1

a
a
0
0
0
0
1
1
1
1
1
1
1

1
1
1
1
0
0
0
0
0
0
0

1
1
1
1
1

0
0
0
0
0

1
1
1
1
1

1
1
1
1
1

a
0
0
0
1

0
1
1
1
1
1
1
1
1
0

1
1
1
1
1
1
1
1
1
1
1
1
1

1
1

1
1

0
0

)
.1
1
1
1
1
1
1
1
1
1
1

l'

1

1
1
1
1
1
1
1
1

1
1
1
1
1

,
1
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
·1
1
1
1
0
0
·0
0
1
1
1
1
0
0
0
0
1
1

a

1
1
1
1
1
1

1
1
1

0
0

OUTPUT

0
1
1
1
1
1
1
1
1
0
0

a
a
a
0
0

1
1
0
0
0
0
1
1
1

,

T1

TZ

0

1

2

0
0

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

a

1
1
1

1
0
1

1

1
0
1
0

0
0

1
0
1

0
0
1

0
0
0
0
0
1
0
1
0
0
0
1
1
0
0
0
0

0
1
0
1
0
1

o·

"

1
0
0
1
·1
0

0
1
1
0

0
1
1

a
0
1
1
0
0
1
1
0
0
1
1
0
0
1

0
0
0

a
a
1
1
0
1

a

a

a

0
1
1

1

0

a

1
0
0
0
0

1
1
1
1
0
0
0

a
a
1
1

a
0
1
1
0
0

0
0
1

0

0

1
1
1
1
1
1
1

0
0
0
1
1
1
1

0
1
1

0
0
1
1

(As

A7

6-64

0

0
0
0
1
1
1

0
1
1
1
1

A4

a

a

2,
32
16
8
4
64
(ROM ADDRESS IN BINARYI

A5

0
1
1
0

,

128

As

1
0
1
1
1
0
1
1
1

0
1

1
1
0
0
1
1
0'
0
1
1

a
a
a

0
1

1

A3

A2

1

a
a

0
1
0
1

0
1
1
0

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
1
1
0
0
1

0
1

1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1

o·
1
0
0
0
0
1
1

,

a
a
0
1

a
0
0
0
0
1
0
1

a
0
0

a

"

0
0
0
1
0
0

a
a

1
.1
1
1
1
1
1
1
1
0

0
0
0
1
1
1
0
0

0
0
0
1
1
1
1
0

0
0
0
1
1
1
0

0
0
0
1
1
1
0

0
0
1
1
1
0
0
0
0
0
1
0
0

(lis

B7

B6

1

EBCDIC
4
3
0
0
0
0
1
1
0
0
0
0
0
0
1
0
1
0
0

0

a
a
a
1
0
1
0
0
0
0
1
0
0
0

a
0

a
a
a
a
0
1

a
1
1

a

1

1
0

1
0

0
0
0
0
0

1
1

a

0
0
0
0
1
0
0
0
0
0
0
1
0

as

0

a

1
0

0
1
1
0
1
1
1
1
0
1
0
0
1
1
0
0

a
0
1
0
1
1
0
0
0
0

a
0
0
1
0
0
0
0
1

5

6

7

1
0
1
1
0

0
1 '
1

1
0
0
1
0

0
0

o·
0
0
0
1
1
1

1
1
0
0
0
0
1
1
0
1

0
0
1
0
1
0
0
1
0
1
0
1
0
0
0
0

a
a
a

a

0

1
0
1
0

a

0

0

0

a

a

0
0
0
1
0
0
0

0
0
1
1
0
1

a

a
0
0
1

0
1

1
0
0
1
1
1

0
0
1

1
1
0

1

0

a
a
a

0
0
0
0
0
1
1
1
0
0

0
0
0
0
0

0
0
1
0
0
0
0

0
0
0
0

1
1
0

a

0
0
1

a

1
1
0

0
0
0
0
0
0
0
0
0
0

0
0
1
1
0
0
1
1
0

0
0

0
1
0
0
0
0
1
1

1

0
0
'0
1
1
1
0

a
1
0
0
1
0

a
a
a
0
1
1
1
0
1
1

a
1
0

0
1
0
0
0
0
0

a
a

0
1
1
0
0

1
1
0
0
0
0
1
1
0
0

B2

B11

0
0,

1
A11

B4

B3

s:
s:.c:a.

code conversion table-EBCDIC-to-selectric
FUNCTION
INPUT

N
W

o

CODE

OUTPUT

INPUT

""
s:

OUTPUT

m
......

P

A
ROM
ADDRESS
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161

EBCDIC
SYMBOL
NUL
SOH
STX
ETX
PF

f

1
1

;

1
1
1

~

1
1

9
h

k

k

I

I

m

m

NL
BS
IL
CAN
EM
CC
CUI
IFS
IGS
IRS

n

n

0

0

P

q

P
q

r

r

ETB

182
18,3

d

1
1

j

166
167

179
180
1'81

b

c

j

164
165

176
177
178

1
1

DCl
DC2
TM
RES

BVP
,LF

173
174
175

1

FF

IUS
OS
SOS

ESC

SM
CU2
ENQ
ACK.

-

,

,

t

t

190
191

SUB

7

0

0

0

0

0

0

0

0

1

0
0

0
0

1
1

0
1

0
0
0

0

1

1

0
0

0

0

1

0
0

0
0
0

0
0
1

0
0

0

0
0

0
0

1

0
0

0
0

0

0

0
0

0

0

0
0
0

0

0
0
0
0

0

0
0

0
0

0
1

0
0

(j

0

0
1

0
0

0

1

0

0
0
1

0
0

0
1

0

1

1

0

1

1
0

1
1

0

0
0

1
1

1
1

0
1

0

0
0
1

0
1

1
1

0
1

0

0

0

0
0
0

1

0

1

0

0

0

1
1
1

0
0

,0

0
1

0
0

0
0

0

1
1
1
1
1
1

0
0
0

0
0

0
1
1

0
0
1
1

0
0

0

1
1
1
1
0

0
1

1

1
1
1
1
0
0
0

0
0

0
1
0

0
1
1
1
1

0
0
1
0
0

0
0
0

0

0
0
1
1
0
0
1

1
0
1
0
1
0
1
0
1

0

0
0

0

0

1

0
0

0
0
0

0

0
0

1
1
1

0
0
0

1
1
1

1
1
1
1
1
1
1
1

0

0

0
0
0
0
0

0
0
0
0
0

1
1

0

1
1

0
0
0
0
0

0
0
1
1

1
1
'I

1
1
1
1
1
0
0

0
0
0
0
1
1
1
1
1

0
0

1
1
1

0
1
1
1
1

0

0

0

0

.a

0
0

0

0

0

0

1
1

0

0
0

0

0

1

0

a

"1

0
0

0
1

0

1
1

1
1

1
1
1
1

0

0
0
0

0
0

1
1

0
0
1

1
1

a
a

1
1

1
1

1
1

1
1
1
1

0

1
1
1
1

0
0
0
1

1
1
1
1
1
1
1
1
1
1
1
1
1

Q

0

Y
z

1

0

1
1

,0

0
0'
0

1
0
0
1
1
0
0
1
1
0

1
1

Y
z

-

0
1

0

1
1

-

0
0

0
0

w
x

-

0

0

v

,:.

0

R5

1
1
1

0

1
1
1
1
0
0

1

1

1
1

0
0
0

0
0

1
1
1

1
1
1

0
0
0

1
1
1

1
1

0
0
1
1
1
1
1
1
1
1

1
1
0

1
0

0
1
0
1
0
1

SELECTRIC
R2
Rl R2A

E

0
0

u

~

0
0

0

0
0

A

1

w
x

EOT

CU3
DC4
NAK

6

2

v

-

C
S

5

EBCDIC
3
4

1

1
1

SVN

184
185
186
187
188
189

,

R

I
T
Y

u

BEL

PN
RS
UC

0
D
E

-

. .

SI
OLE

C

a

CR
SO

FS

171
172

b

c

d
HT
LC
f'
DEL 9
h
;
SMM
VT

162
163

16B
169
170

a

SELECTRIC
SYMBOL

0
1
0
1
0
0
0

0

0
1

0

0
0

0

0
0
0
0
0
0

0
0
0
0,

0
0
0

0

0
0

0
0'

0
0
0
0
0

0

0
1
1
0
1
0
0
1
0
0
0
0

0
0
0
1
0

0
1
1
0

0
0
0
0
0
0
0

0
1

0

1
1
0
1
1
1

1

0

0
0

0

0

0

0
0
1
1

0
0
0

a
a

1

1

0

1
0
0

1
0
1

0

0

1

0
1

0
0

a

0

0

1
1

0

0

1

0

0
0

0
0
0

0
0
0
0

0
0
0
0

0

0
0

0
0
0
0
0
0

0
0

0
0

0

0
0
0

0
0

0
0

0

0

0

0

0
0

0
0
0
0
0
0

0
1

0
'0

0
1

0

0
0

0
1

0
1

0

0
0
0

0

0
0

32
4
64
16
8
2
(ROM ADDRESS IN BINARYI

1

(AS

A7

(Ss

B7

B6

B5

A2

All

0
0

0
1

0
1

128

,0

0
0
0

0

1
0

0
0
0

a
a

0
0

1

1
1

0
0

0

0

0

1

1
0
,I

a

0
0

0
0
0
0

0
0
0
0
0
0

0
1

0

0
0
0

0

1

0
0

0

0
1

0
0
0

I'

0
0

a

0
0
1
1

0

0
0

0

0
I'

0
1

6-65

1
1
0
1
1

0

0
1
1

0
0

A3

0

0
0

0

A4

0
0
1
1
0'

1
1

0
1

0

A5

0
0
1

0

0

0
0

0

At;

0

0
1
1

0

1
1

0
0

0

1
0
1
0
0
0

0

0

0

0
1

a

0
1
0
1
0

0
0

0
0

0
0
1
1

1
1
1
1

0
0
0
0
0

0
0

0

0
0
0
0

0

0
0
0
0
0
0
0

0

0

0
1
0
1

.0

1
0
0

0
0

0

1
1
0
0
1
1

0

0

0
1
0
0

0
0
1

1

0
0
1
1
1
1

0

0

1
0
1

0
0

1
0
1

0
0
0

0

1
1
1
1

1
1
0

0

1
0
0

1
1
1
1
1
1

0
0
0

0

0

,

1
1
1

0

0
1
1

1

0
1

0
1
1

0

1

0

0

1
0
0

0
0'

0

0
0
0
0

0

0

0

0
0

T2

0
0

0
1

0
0
0

Tl

0
0
0
0

0
0

0

0
0

0

0
0
0

0
0

0

a

0
0
0
0
0
0
0
0

0
0
0

0

0
0

0
0
0

0
0
0
0

0
0

0
0
0
0
0
0
0
0,

0

0
0

0
0

83

B2

81)

0
0
0
0
0
0

0

0

B4

0
0
0

CI
0

0
0
0
0
0

s::UI
N

W

o

""

m

w

u..

o('I)

code conversion table-EBCDIC-to-selectric(con't)

N
Ion

FUNCTION

:!
:!
.......

INPUT

CODE

OUTPUT

o('I)
N

~

:!
:!

OUTPUT
p.

A

w

u..

INPUT

C
ROM
ADDRESS
192
193
194
195
196
197
198
199
200
201
202
203
204

EBCDIC SELECTRIC
SYMBOL
SYMBOL
Space

-

A

A

B
C
0

B
C
0

E

E

1

1

1
1

1
1
1

0
0
0

1
1

F

1
1
1

H

H

I

I

1
1
1

•

•
(

t

,

t

208
209

&
J

&

210
211
212
213
214
215
216
211
218
219
220
221
222
223
224

K

K

L
M

M

N

N

J
L

0
P

0
P

a

a

R

R

!

$

* or *

.

$

)

}

;

;

"

-

-

225
226
227

I
S
T

I

228
229
230

U

U

S

T

V

V

w
X
y

W
X
y

Z

Z

%

%

-or-

-

238
239
240

>

241
242
243
244

1
2
3
4
5
6
7
8
9

?
0
1
2
3
4
5
6
7
8
9

#

#

@

@

"

"

255

2

G

(

245
246
247
248
249
250
251
252
253
254

1

F

<

235
236
237

E

G

205
206
207

231
232
233
234

0
0

?
0

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
0

1
1
1

0

0

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0

0
0
1

0
0

0
1

0
1
0
1

1

1

0
1

1

0

1
1

0
1

1
1

0

0
0

1
0
1

1
1
1

1
1

0
1
0
1

0
0
0
1

0
1

0
0

1
1

0

a

1

1
1
1
1
1

0
0
1
1
1
1
0
0

1
1

a

0
0
0
0

0
0
0
0
0
0
1
1
1

0
0
1
1
0

0
1
0
1
0
1
0
1

1
1

1
1

1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1

1
1
1
1

a
0

0
1
0
1

a
1
0
1
0
1
1
0

1

1
1
1
1
1
1
1
1
0
1
1
1

0
0
1

a
a

1
1
1

0
1
1

0

1
0

0
1

0
1
0

0
0

1
1

0
0
0

0
1
0

0
0
0

0
0
1

a

a

1
0
0

0
1
0
0
1
1

1

1
1

1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
0
1
1

1
0
1
1
0
1

0
0
0

a

a

1

0
0
0
0
0
0
0
0
0
1

0
1
0
1
1
0
0
1
1
1

1
1

1

1
0
1
1
0
1
1
1

0
0
1
1
1
0
1
0
0
1
0
0
0
1
0
1

0
1
0
1
0
0
1

a
0
1
0
1
1

0

0
1
0
0

a

a

1

0

a

1
0
1
0

0
1
1
1
0
0

0
0
0

0
0
1

1
1
1
0
1

0
0
1
1
0

0

a

1
1
1
0
0
0

a
0
1
1

1
1

0
0

0
1

a
1

0
0

0
0

0
1

0
0

1
1
1
1

0
0
0
1

0
0

0
1

1
1

0
1

0
1

0
0
1
1
1
1

1
1
0

0
1

0
1
1

0
0
1

0
1

0

0

0
1

0
1

1

0
0
1
0

0
1
1

1
0

0
0
0
0

0

0
0
0
1

0
1
1
1

1
1
0

0
0
0
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
1

Aa

0
1
0

1
0
0
1
1

1
0
1

0
0
1

0

1
0
0
1
1
0
0
1
1

A7

6-66

1
0
1

0

0
.0

1
1
0
1

0
0

1
0

1
1

(AS

A4

a

0
1

0
0

1

0
0
0
0

0

1
1

1
1

0
0

64
32
16
4
2
8
(ROM ADDRESS IN BINARY)

AS

1

1
0
0

1
1

0
0
0

0
1
0
1

1
1
1
1

128

A6

0

1
1

0
0

0

0
1

1

0
0
1
1

0
1
1
1
1

0
0
0

0
0

0
0
1

0

1
1

1
1
1
1
1

0
1

1

1

.0
0
1
1
1
1
0
0

T2

0
1

1

0
0

0
1
1
0
0
1
1
0
0
1
1

Tj

0
0

0

a

0
0

0
1

1

0

1

0
1
1
1
1

a

0
0

0
0

SELECTRIC
R2
Rl R2A

0

0
0

0
0
0
0
0
0
1
1
1

RS

0
1
0
0

0
1

0
0
0

1
1
1
1
1
1
1
1

C
A
S
E

0
0
1
1

0
0
1
1

0
0
0

R
I
T
Y

0
0
0

1
1
1

1
1

1
1
1
1
1
1
1

0
0
0

1

1
1

1
1

0
0
0

1
1
1

1
1
1

1
1
1
1
1
1
1
1
1
1
1

7

0
0
0
1

1
1
1

1
1

0
0
0

6

0

1

1
1
1
1
1
1

0
0

5

0
0
1

1
1

1
1
1

0

0
0

1
1

1
1
1
1
1
1

0
0

1
1

1

0

EBCDIC
3
4

0
1
1
0
1
0
1
0
1
0
1
0
1

1
0
1
1
0
1
1
0

0
1
1
0
0
1
0
1
0

0
1
0
0

0
0
0
1
0
1

0
0
0
0

0
1
1
0

0
0
0

0
1
1

0
1

0
1

1

0
0
0
0
1
1
1
0
1
1
1
1

0

0
0
1
1

0

a
1
0
0
1

0
1

1
0
0
0
0

0
0
0
0
1
1
0
1
0

0
0
1
0
1

1
1
1
1
1

0
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1

B7

B6

B5

B4

B3

B2

1
0

0
1

a
0
1
0
1

1
1
1
1
1
U

1
1
0
0
0

1

A2 . AI) (B8

Bl)

MOS ROMs

~

NATIONAL

MM4230JT/MM5230JT BCDIC to EBCDIC/
EBCDIC to BCDIC code converter
general de.scription
The MM4230JT IMM5230JT is a 2048-bit read·only
memory that has been programmed to convert from
the 64-entry, 6-bit Binary Coded Decimal Interchange Code (BCDIC) to the eight· bit e.xtended
BCD interchange code IEBCD IC) and back again.
The tables show the two translations in binary.

connection diagram

Character assignments for the EBCDIC are given
to IBM 1130 specifications. A.II the non-alphanumeric assignments in BCDIC are subject to specialist usage, and care should be taken over them.
For electrical, environmental and mechanical details, refer to the MM4230/MM5230 data sheet.

Dual-In-line Package
INPUT A,

24

VOD

INPUT A,

INPUTA,
OUll'UTB,
B~

INPUTA.

OU11'U183

,NPUT/\,;

OUT~UT

B.

INPUT A,

OUTPUTS.

INPiJTA"

OUTPUT

MODE

IJUTPUTB,

CONTROL
CHIP

OUTPUTB.

ENABlE

Order Number MM4230JT/J
or MM5230JT/J
See Packag(t 11
Order Number MM5230JT/N

See

Packag~

18

typical applications
BCDIC to EBCDIC

~
12~
t
'~=:~=====================r=F====~~~~~~~~~~~~~~lf.~~1t~---r-.tc:~

+12V_,

.

6.11(

Be

13

6.8K

UK

6.8K

&.HK

UK

UK

6.IK:

1 OM74Q4

ENABLE

i

~16

.

"HIGH

",HIGH

r

"

4

B~-~:~.

OUTPUTS

HIGH
T~UE

8,
8,

I

jI

~ EBCDIC

I

o,DM1812

"
HIGH
TRUE INPUT

, I
3

1IMB81U

r~.

." ,

"

tMODE

CONTROL

r

, I

• I
I

'J
en

1"
tSee operating mode notes. (MM4230 data sheet.)
<-A values can vary from 6801, to 30 k;!

6-67

..,

I-

o

("')

N

typical applications (con't)

It)

:iE
:iE

.......

..,o

I-

EBCDIC to eCOle

("')

"
""
I

N

o:t

:iE
:iE

",
tCHIP

ENULE
tMQOE
CON1ROl

OW

MS <

.
2

"
"

lll-a"

"

lorl ?

~1&
OM8110

ir'

12~

",UMB81t

J.DK

3.oK

l.OK

3.011

"" 1f""

J.DK·~l1

."
..
..

i'

'"

tMIl

"

<,

." ...

UK :

I

I
I
I
I

DMl4IM

I

.

..

I

OnmLLOGIt

I

1U;1lf«:

HUiK

OUTPUT

TRUE

l~

~Z4

6_IK

<,

]~

23

OJ<

<0

<,

"
" "

TRUE

·, .
·· .,
·
<

.." """."

."

'11

I
I

I
I
I
I
I

"
!

~

l,

tSee operating mode notes. (MM 4230 data sheet.)
R vifllle:; CCln vary from 68011 to 30 kn.

6-68

~

s:
:r.

code conversion tables

N
W

o
c..

BCDIC to EBCDIC

:::!
FUNCTION

ROM
ADDRESS
0

INPUT.

OUTPUT

BCDIC
SYMBOL

EBCDIC
SYMBOL

BS

B7

BG

!Is

NULL

NULL

0

0

1
1

1

0
1

0
1

1

1

1

0
0

1

1

1

2

2

2

3

3

4

4

5
6

5
6

7

7

8

8

9

9

10

11
12
13
14
15
16
17
18
19
20
21
22

OUTPUT
EBCDIC
B4
0

3

1

1

1

1

0

1
1

1

1

1

0

5

1

1

0

1

1

1
1

1

0

1

1

1

1

1
1

1

1

1

1

1
0
0

1

1
1

1
1

0
1

1

1

1

0
1

1

1

1

0

1

1

1

0

1

1

1

•
6
7

•

0

9
0

"

@

@

s:
s:

CODE

"

1

U1

B3

B2

Bl

0
0
0

0

0
1
0
1

1
1

0
1

0

1
1

0
1

1

1

1

0

0

0

0

0
1

0

0

0

1

1

1

0
1

0

0

1

1

1

1
1

0
1
1
0

0
1
0

1

"

"

0

1

1

Space

Space

0

1

0

0

0

0

/

/

0

1

0

0

0

s

s

1

1
1

1

0

0

0

0

1

0

0
1
0

1

l'

0

0
1
1

U

U

1

1

1

0

0

1

'0

0

V

V

1

1

1

1

1
1

0

W

0
0

0

W

1
1

1

1

1

1
0
1

T

T

1

1

1

0

0
0

1

0
1

X
y

X

1

1

24

y

1

1

1

0

1

0

0

25

Z

1

1

1

0

1

0

0

0
1

26
27

NULL

Z
NULL

0

1

0

0

0

0

0

0

0

1

1

0

0

1

1

2.

%

0

1

1

0

1
1

1

0

0

0

1

0

1

1

0

1

1

0

1

1

0

1

1

1
1

0

23

%

29
30

>

>

0

1
1

0

31
32

?

,

-

0
0

1

1

0
0

0

1
0

0

33
3.

J

J

1

1

0

1

0

0

0

1

K

K

1

1

0

0

1

0
1

1

35

L

L

1
1

1

0
0

1

0

0

36

M

M

1

1

0

1

0

1

0

37

N

N

1

1

1

0

0

1

1
1

0
0

1

3B

0
0

0
1

39

P

P

.,

Q

Q

1
1

A

A

42

!

,

1
0

1
1

43

$

$

0

)

)

47

.,

.,

as

&

&

49

A

A

0
1

50

B

B

1

1

51
, 52

C
D
E
F

C

40

44
45
46

53
54

1

0

1

1

1
1

1

1

1

0

1

0

0

1
1

1

0

0
0

1

1
0
0
1

1

0
1
0
1
0
1
0

1

0

1

1

0

1

1

0

1

0

1

1

1

0

0

0

1

0

1

1

1

0

1

0

1

0

1

1

1

1

0

0

1
1

0
0
0
0

1
0

0

1

1

1

1

1

0

0

0

0
0

0

0

0
0
0

1

1

0

0

0

1

1

0

0

E

1

1

0

0

F

1

0

0

1

0

1

0
'0

1

0

1

1

1

0

0

1

0

1

1

1

0

55

G

G

1
1

1

0

0

0
0

1

1

1

56

H

H

.1

1

0

0

1

0

0

0

57

I

I

0

0

1

0

0

1
1

0

;

1
1

0

58

•

1

0

1

0

60
61

<

<

(

I

62

+

,

63

I

I

59

Q

0

1

0

1

0

1

1

0
0

1

0

0

1

1

0

1

0

0

1

1

0

0
1

0

1

0

0

1

1

1

0

0

1

0

0

1

1

1

1

6-69

0

N
W

o
c..

-t

code conversion tables(con't)
BC DIC to EBCDIC (con't)

FUNCTION

CODE

INPUT

OUTPUT

BCOIC
SYMBOL

EBCDIC
SYMBOL

B8

B7

B6

BS

B4

B3

B2

B,

64

a

a

1

1

1

1

1
2

1
2

1

1

1

1

a

67
68
69
70

3
4
5

3
4

1
1

1
1

a
a

1
1
1

a
a
a
a

a

65
66

a
a
a

5

1

1

6

6

1

71

1
0

ROM
ADDRESS

OUTPUT
EBCDIC

1

NULL

NULL

0

72

7
8
9

7
8
9

1

73
74
75

NULL

NULL

1
1
0

1
1
1
0

NULL
NULL
NULL

NULL
NULL

0
0

0
0

NULL

NULL

NULL

0
0
0
0

0
0

76
77
78
79
80
81
B2
83
84

NULL
NULL

NULL
NULL

NULL

NULL

NULL

NULL

0
0
0
0

NULL

NULL

85

NULL

NULL

B6
B7

NULL
NULL
NULL

NULL

NULL

NULL

f'JULL

NULL
NULL

9'
95
96

NULL
NULL
NULL
NULL
NULL

NULL

97

NULL

9B
99
100
101

NULL.,

NULL

NULL

NULL

102
103
104

NULL

NULL

0
0
0
0

NULL

NULL

NULL

NULL

88
89
90
91
92
93

105
106

NULL
NULL

NULL

NULL

NULL

NULL

1
1
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0

0
0
0

0

0
0
0

0
0
0
0

0
0
0
0

0

0
0

NUll

0

0

0
0
0

NULL

0

NULL
NULL

0

0
0

0
0

0
0
0
0

0
0
0

0
0

0
0
0
0

NULL

NULL
NULL

NULL

NULL

NULL

109
110
111
112
113
114

NULL

NULL

NULL

NULL

NULL

NULL

NULL

NULL

NULL

NULL

115
116
117

NULL

NULL

NULL

NULL

NULL

NULL

NULL

NULL

NULL

NULL

NULL

NULL

NULL

NULL

0
1

0
0

NULL

118
119

0
1

NULL

NULL

120
121
122

1

1
1
1

NULL

107
lOB

NULL

0
0
0
0
0
0

1
1
1

NULL

NULL

NULL

123
12.

NULL

NULL

NULL

NULL

125
126

NULL

NULL

NULL

NULL

127

NULL

NULL

0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

6-70

0
0

0

0
0
0
0
0

0
0
0

0
0
0

0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0

1
1

0
0

0
0
0
0
0
0
0
0
0
0
0
0
0

1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0

1

1

a

1

a

a

0

1

0
0

1

0
1
0
1

0
0
1

0
1
1
0
0
0
0

0
1
0

a
0

a
0
0
0

0
0
0
0

0
0
0

0
0

0
0

0

0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0

0
0
0
0
0
0
0

0
0

0

0
0

1

~
0

0
0

0
0
0

0
0

0
0

0
0
0
0

0
0

0
0

0
1

0
0
0
0

0

0
0
0
0
0
0
0
0
0
0

0
0

0
0

0
0

0

a
a
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

a
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0

0

0
0

0

0

0
0

0
0

0
0

0

0

0

0
0
0

code conversion tables(con't)

EBCDIC to BCDIC

FUNCTION

CODE

INPUT

OUTPUT

EBCDIC
SYMBOL

BCDIC
SYMBOL

128
129
130
131

NULL

132
133

NULL

NULL
NULL
NULL
NULL
NULL

ROM
ADDRESS

134
135
136
137
138
139
140
141
142
143
144

NULL
NULL

NULL

NULL

,-

NULL
NULL

,

<

<

(

(

I

I

&

&

145
146

NULL

147
148

NULL

NULL
NULL
NULL

NULL

NULL

-

NULL

BCDIC
B8

87

86

B5

84

B3

B2

0

a

0

0

0

a

0
0
0

0
0
0

0
0

a
a
a
a
a
a

a
a
a
a
a
a

0
0
0
0
1
1

0
0

0
0
0
0
0
0
0

0

1

a
a

1
1
1
1

0

a
0
0
0

-

NULL

OUTPUT

a
0
0

a
a
a
a
a
a
0
0
0
0
0
0

149
150
15,1
152
153
154

-

-

NULL
NULL

NULL
NULL

,

0

$

$

155
156
157

)

)

0
0
0

158
159
160
161
162
163
164

,

-1

I

I

-1
NULL
NULL

,
-1
NULL

0
0
0

0
0
0
0

0

a
a
a
a
a
0

a
a
a
a
a
a
0

a
0
0
0

a
0

a
a

0
1
1

1

1
1

1
1
1
1

1
1
1
1

a
a

a

1
1

a

a
a
a
a
a
a

a
a
a
a
a
a
a

0
0
0

a
a

a

a
a
a

0

a
a

0

a

0

0

a

a
a
a
a
a

1
1
0

a
a
a
a
a
a
0
0
1

a

NULL

a

NULL

NULL

a

0

165
166
167

NULL

NULL

a

NULL
NULL

NULL
NULL

0

a
a

a

0

0

168
169
170

NULL

NULL

a

a

a

0

NULL
NULL

NULL
NULL

0
0

0
0

0
0

0
0

%

0
0
0

0

%

1
1
1

171
172
173
174
175
176
177

-

>

,

>

,

0
0

NULL

NULL
NULL

0
0

178
179

NULL

NUI~L

NULL

NULL

180
181
182
183
184

NULL

NULL

-

0
0
0
0

-

185
186
187
188
189

NULL

190
191

NULL

'*

@

0
0
0
0
0
0
0

--

-

0
0

"

"

0

NULL
NULL

"

@

NULL
NULL
NULL

6-71

0
0

a
a
a

0
0
0
0
0

a

0

a
a
a

0

a

a

0

1
1

a
a
a
a

0

a

a
a

0

a

a

a

a

1
1

1
1
1

0

a

0

a
0

1

a

1
1
1
1

0
0

0
0

a

1
1

1
1
1

a
a

0

a

a
a
a
a

Bl

0

a

a
a
a

1
1
0
0

0
0

0

a
a

a
a

1

0

1
1
1
1
1
0

0
1
1
1
1
0
0

a
0
0

a
a
a

a
0
0

a
0

0
0
0
0
0
0
1
1
0

a
1
1

0

1
1

0

0
0

a
0
0
1
0
1

a

0
1
0

0
0

1
0

a
a
a
a
a

a

0
0

a

0

a
0
0

0
0

0
0

a
0

0
0

1

0

0
1

1

1
1

a

0
0
1
0
1

1
1

1
1

0
1

1
1
1

0

0
0
0
0

0

a
a

0
0

0
0

0
0

0
0
0

a
a

0
0

a

a
a

0

0
0
0

0
0
0

1
1
0

a

0
0
·0

0
0

0
0
0

0
0
0
0
0

0
0
0
0
0

0
0
0
0
0
0

0
0
0
0
0

0
0
0

0

0

0
0

0
0
1
1
1
1
1

0
0
0
0
0
0
1
1
1
1

0

a

a
0
0
1

a
0
1
1

0
0
0
0
0
0
0
1
0
1
0
1

I

....
-,
o

M
N

code conversion tables(con't)

It)

:2:
:2:

EBCDIC to BCDIC (con't)

.......
I-

-,

FUNCTION

o

M
N

"It

:2:
:2:

INPUT
ROM
" ADDRESS

CODE

OUTPUT

EBCDIC

BCDIC

SYMBOL

SYMBOL

OUTPUT
BCDiC
B8

B7

6S

B5

B4

B3

"B2

-

0

0

0

0

A

0

0
1

1

A

0
0

1

0

0

0

1

B

B

0

0

1

0

1

0

C

C

0
0

192

-

193
194

Bl
0

0

1

1

D

D

0

1

1

0

0
1

1

196

0
0

1
1

0

197

E

E

0

0

1

0

1

0

0
1

1

0

1

1

0

1

0

1

1

1

1
1

0

0

0

0

0

1

195

198

F

F

0

0

1
1

199

G

G

0

0

1

200

H

H

0

0

1

1

0

1

1

201

I

I

0

202

NULL

0

0

0

0

0

0

0

0

NULL

0

0

0

0

0

0

0

0

204

NULL
NULL
NULL

NULL

0

0

0

0

0

0

0

205

NULL

NULL

0

0

0

0

0

0

NULL

NULL

0

0

0

0

0

0

0
0

0

206
207

NULL

NULL

0

0

0

0

0

0

0

208

0

0

0
0

203

0

0

NULL

NULL

0

0

0

J

J

0

0

0

0

K

0

1

0

0

0

211

L

L

0

1

0

0

0

1

1

212

M

M

0

0
0
0
0

1

K

0
0
1

0

209
210

1

0

0

1

0

0

213

N

N

1

0
0

1

0

0
0

0

0
P

0

1

0
1

P

0
0
0

1

214

0

1

0

0

1

1

0
1

0
R

Q

0

0

1

0

1

0

0

0

A

0

0

1

0

1

0

0

1

0

0

0

0
0

0

215
216
217
218
219

NULL
NULL
NULL
NULL

NULL

0

0

0

NULL

0

0

0

0
0

0
0

0

NUL,L

1
0

1

0

0

0

0

0

221
222

NULL

0

0

0

0

0

0
0

0

0
0

NULL

NULL

0

0

0

0

0

0

0

0

223

NULL

NULL

0

0

0

0

0

0

0

224

NU,LL

NULL

0

0

0

0

0

0

225

NULL

NULL

0

0
0
0

0
0

0

0

0

0

0

0

0

0
1

0

1

0
0

0
0

1

0
0

0

1

1

1

1

0

0

220

5

0

226
227

5

T

T

0
0

228

U

U

0

229

V
W

V
W

0

0

0

1

0

1

0

0

1

0

X

X

0

0

1

0

1
1

1
1

0

231

0
0
0

1

230
232

Y

Y

0

0

0

1

1

0

0

0

1
1

233

Z

Z

0

0

0

1

1

0

0

234

NULL

NULL

0

0

0

0

0

0

0

0

235

NULL

NULL

0

0

0

0

0

0

0

236

NULL

NULL

0

0

NULL

0

0

0
0

0

NULL

0
0

0

237

0

0

0
0

0
0
0

238

NULL
NULL

NULL

0

0

0

0

0

0

0

0

239

NULL

0

0

0

0

0

0

0

240

0

0

0

0
0

0

1

0

0
0

0

0

1

1

0

0
0

0

1
0

242

2

0

0

0

1

0

0

4

0

0
0

0

244

0
0

0
0
0

0

3
4

2
3

0

243

0

1

1
0

245

5

5

0

0

0

0

0

1

0

1

246

6

6

0

0

0

0

7

0

0

0

0
0

1

7

0
0

1

247

1

1

1

248

8

8

0

0

0

1

0

0

0
0
0
0
0
0
0

0
0
0
0

0

1

0

0

0
0

0

0

0
0

0
1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0
0
0

0

0
0

0
0
0

0

0

241

249

9

9

250

NULL

NULL

251

NULL

NULL

252

NULL

NULL

253
254

NULL

NULL

NULL

NULL

NU.LL

NULL

255

6-72

1

0
1
0

0

~
~

MOS ROMs

NAll0NAL

MM4230KP/MM5230KP ASCII-7 to selectric code converter
general description
and < only for ASCII. The former problem is
handled in the MM4230KP/MM5230KP by exploiting the inherent redundancy of the bail code
(see Table 2). The latter inconsistency is resolved
by making arbitrary equivalences between the
unique characters. The two tables show the treatment of both the characters which have equivalents
in both codes, and those characters, and the functions, which do not. Encoding and decoding the
Selectric functions that the user requires is a
matter of conventional Boolean logic. A typical
example is shown below.

The MM4230KP /MM5230KP MOS read-only memory has been· programmed to perform the conversion between the American Standard Code for
Information Interchange in seven bits (ASCII)
and the Selectric correspondence bail code transin itted and received by the IBM Series 7 input/
output printers.

application hints
The ASC II field and Selectric bail code field as
defined do not map exactly: for instance "space"
is handled as a normal 7-bit code in ASCII, but is
handled as a unique switch and solenoid pair in the
Selectric printer. And .even. among the graphic
characters, ± and 

For electrical, environmental and mechanical details, refer to the MM4230/MM5230 data sheet.

typical applications
MACHIIiIECODE

J--...J

..

,----

·.H---.D--'I+t+f+-F'-

CAsE

~=~: TO

,--------lil

+-++I+t--r'"'\.,

'+t-H-t---"
,+-H---i,
L-f----..
.._ _ _ _

,

t=E§2-~=:

~---l

.--------------~

~~ A--~~,~"'=GH~A="~".~w.~,~~.~.~~,----~--~4
AlOWSlloctril:UlASClltn .... '

Encoding ~Space' by Gating In on Input
ENCODIMa

'SPACE'SY GATING IN

Decoding 'Space' on Output

SElECTRtCTAIlESHOWSSPACEASR s• T,.1I2
DECODING
'SPACE'

------.
--+_________ m

.._+~L)o-----Tii

fl

"" -------'---.,.

TO IAIL CDOE INPUTS

=l~~~~~~

....

I

SPACE MAGNET
DRIVER

----,

I
I

8AIl COOl fAOM

ABOVE

CONVERTER
LOWTFlU£

_~;L;»-----fi

iiI

"

L. _ _ _ _
lM151 PERIPHERAL

DRlvn

ff--~--~--------n)

Order Number MM5230KP/N

Order Number MM4230KP/J or MM5230KP/J
See Package 11

See Package 18

6·73

I

.J

code conversion tables
Table 1. ASCII·7 to Selectric

~b'
t s

..

b4

b3

b2

+

+

+

0

0

0

b,

*

0

.
Row +
~
0

0

0

0

1

1

0

0

1

0

2

0

0

1

1

3

0

1

0

0

4

0

1

0

1

5

0

1

1

0

6

0

1

1

1

7

1

0

0

0

8

1

0

0

1

9

1

0

1

0

A

1

0

1

1

B

1

1
1
1

1
1
1
1

0
0

1

1

0

1
0

1

C

0
E
F

0

0

0

0

0

0

1

1
2

1

0
NUL

3A
DC4
OB

ENG

NAK
13

ACK

..

2

B

R

b

r

#

3

C

5

c

s

.$

4

D

T

d

t

%

5

E

U

e

u

&

6

F

V

f

v

7

G

W

9

w

(

8

H

X

h

x

I

9

I

Y

i

y

:

J

Z

j

z

:

K

25

CAN

HT

4A
EM
5A

52

LF

.

SUB
53

VT

6A
ESC

72

FF

+

7A

<

FS

72
CR

48
GS

59

5'3
SO

40

-

51

68
US

73

78

6·74

~

>

RS
63

P
q

3B

42

25

a

ETB

85

7

Q

2B

33

.

6

A

SYN

BEL

1

1

1B

23

1
0

!

DC3

EOT'
03

1

1

P

2A

32

1

0

@

DC2

ETX

1

Ii

0

62

IA

22

0

5

DCI

STX

1
1

4

OA

12

1
3

SP

DLE
02

SOH

0
0

?

M

7F

\
60

1
77

.k
I

N

0

70

-

I

,,

m

n

-

0

7F

4B

I

I\.

50

I

L

[

77

58

DEL
00

1.

code conversion tables (con't)
Table 2. ,Selectric to ASCII·7
,

.

R5
Tl

0

0
0

R2A

R2

Rl

1 1 1 1
0

0

0

0

K

Row ----:--

'0

2/D
y

2

b

0

0

0

1

1

0

0

1

0

2

0

0

1

1

3

0

1

0

0

4

0

k

0

1

0

1

5

p

e

0

1

1

0

6

0

1

1

1

7

J

t

1

0

0

0

8

-

B.

1

0

1

1

0

~

1

1

1

0

1

3

4

5.

6

~ W~

0

s

1
0

1
0

9

"'"

h

1
0

0

1

0
i)

T2
S

0

I

I

3/0

1

1
7

rw ~
0

6/C

4

6/F

~ ~ ~ ~ ~~ ~ ~
~ ~ ~ ~ ~~~ ~
3/D

n

1

0

0

1

9

1

0

1

0

A

1

0

1

1

B

1

1

0

0

,C

'0

K

1

1

0

.1

D

P

E

1

1

1

0

E

+

N

1

1

1

1

F

J

T

Y

i

6
;

c

a

8

d

r

7

217

5

2/E

2

f

u

v

3

z

9

x

m

1

1I:d

2/1
W

H

2/C
3/B

/f#; ~ W

(

S

L

?

)

W

0

$

4/F

~ ~ ~~ ~ ~~ ~

.~ ~ ~ ~ ~ ~ ~ ~
e

I

6/3

419

..

2/E

2/C

C

A

.

I

%

:

D

R

&

@

F

U

V

#

Z

G

X

M

~o

F/F

±[

5/B

ASCII shown thus: Column No.lRow No.

6·75

DII

MOS ROMs

~

NAll0NAL

MM4230QW/MM5230QW hollerith to EBCDIC code converter
general description
lines to' eight line binary encoded form suitable
for use by the ROM,

The MM42300W/MM5230QW 2048·bit MOS read
only memory has been programmed to convert the
12 line Hollerith Gode to the 8 line EBCDIC Code.
Three TTL 4·input NAND gates and three TTL
inverters are used to compress the 12 Hollerith

For electrical, environmental and mechanical details, refer to the MM4230/MM5230 'data sheet.

typical application
Hollerith to EBCDIC
MODE
CDNTROl

v..

OUTPUT.
AUII-I

"
"2

"
"

,11,4 21

'UNCHED
CARD
DATA

E.

..

INPUT

E,

E,

PUNCKE"S---

""(,:

------"'I
,...:"1

..

12 _ _ _ _ _ _ _ _ _ _ _- ' -_ _ _ _ _

Note 1: Vss '" +12V 110%, Voo = GND,

VGG =

-12V +10%.

Not{! 2; The Hollerith input data (lines 1 through 12l is considmd to be from
normallv open switche5 returne~. in the case of it punched hole, to GNU as shown.

CHIP
ENAalE

Vpg

ANVDTL/TTl

HICH

DEVICE

TRUE

v"G

connection diagram
DUal·ln·Line Package
A,

A,

A,
A.
S,

A,

Order Number MM42300W/J or MM52300W/J.

See Package 11

S,
S.

Order Number MM52300W/N

A,

See Package 18

S,
S,
S,
So

MODE

CONTROL

CHIP
ENABLE

V" L'_'____--I
6·76

code conversion table
Hollerith to

12

12

12
11

11

I

I
I

I

a

j

-

b

k

s

c

I

t

d

m

U

e

n

v

f

0

w

9

'p

11
0
&

-

if>

1 A
2 B
3 C
4 0
5 E
6 F
7 G
8 H

J

/

K
L
M
N
a
P

S
T
U

0

X
Y

9 I

R

Z

[

1

\

<

.

(

)

+

;

!

=

® ?

"

0

x

12
11
0
70
Bl
B2
B3
B4
B5
B6
B7

88
B9
8A 9A AA BA
8B 98 AB BB
8C 9C AC BC
80 90 AD BD
8E 9E AE BE
8F 9F AF 8F
h

q

y

i

r

z

ESCDIC

12

12
11

49
SOH
STX
ETX

59
DCl
DC2
DC3
14
04
HT 15
06
BS
DEL 17
CAN
08
EM
09
OA
lA
VT lB
FF
FS
CR

so
SI

GS
RS
US

12
11

11
0
0
0
AO
80
69
90
31
41
El
21
51
22
SYN 42
62
52
33 43 53 63
23
24
34
44
64
54
45
LF
35
55
65
46
66
ETB 36
56
67
57
ESC EaT 47
38
48
68
28
58
39
NUL OLE 20
29
CA DA EA
2A
3A
CB
DB
EB
2B
3B
DC4 CC
DC
EC
2C
ED
ENO NAK CD- DO
CE
EE
DE
ACK 3E
EF
OF
BEL SU8 CF

12
11
0
BO
8-1
71 9 -1
72 9 -2
73 9 -3
74 9- -4
75 9 -5
76 9 -6
77 9 -7
78 9 -8
30 9-8-1
FA 9-8-2
FB 9-8-3
FC 9-8-4
FD 9-8-5
FE 9-8-6
FF 9-8-7

may be "'"

® may be ","

Note: Unassigned entries e.g. AF refer to the EBCDIC code as a 16 x 16 table, column then row, in hexidecimal notation.
Not.: The relationship between Hollerith as 256 valid punch combinations and EBCDIC as eight binary digits is well
establishe~. This COnverter conforms to this practice. The assignments shown in the table above are the recommendations
of the American National Standards Institute. For details on alternate non-alphanumeric graphic and control codes. see

ANSI x 3.26 - 1970.

6·77

x

o
o

M
N
In

~
~
........

~

MOS ROMs

NATIONAL

X

o
o

M
N

o:t
~
~

MM4230QX/MM5230QX
EBCDIC-8 -to- ASCII-8 code converter

general description
The MM4230QX/MM5230QX is a 2048-bit read
only· memory that has been programmed to convert Extended Binary Coded Decimal Interchange
Code (EBCD IC) to the American Standard Code
for Information Interchange extended to eight bits
(ASCII-8).

lished by the American National Standard ANSlx
3.26-1970. Exact details are shown in the code
table.
For electrical, environmental and mechanical details, refer to the MM4230/MM5230 2048·bit read
only memory data sheet.

The conversion conforms to the practice estab-

typical application

connection diagram
Dual·ln-Line Package

-t2V----------------...~,......,
.sv--...--'------------+_I--+--.--GATES DMBIID DR OM8812

A9

"

v"

INPUT A,

INPUT A,

6.8K.
TYPICAL,

INPU1A,

8 LINES

GATES DM1400

i,

OUTPUTS,

E,

i,
E,

OUTPUTS,

INPUT As

aUTPUTB,

INPU1A o
INPUT A,

i,

E,
INI'UTA"

OUTPUTS,

i,
E,
i,

,

E,

~

OUTPUT

B~

MOUe

OUTPUTS,

~(jN!HUL

OUTPUTS.

i,

E,

i,

IN.PUTA.

E,

i,

E,
DTL/TIt LOGIC

Order Number MM4230QX/J
or MM5230QX/J

See Package 11
Order Nu\"ber MM5230QX/N

See Package 18
"Chi~

Enable = Logic "1" to obtain outputs.
logic levels'
OTlfTTl (eKcept at MOS/ROM interface). Logic "1," +5.0V, NOM, logic "0" ground, NOM
M,OSIROM inputs and outputs. Logic "1," more negative, logic "0," more positive.

6·78

code conversion table

0---0

0

0

1---0
2--_0

0

•
I 0I 0I 0I ~
0

•

5

0

0

0

0

1

1

0

0

1

0

2

0

0

1

1

3

0

1

0

0

•

0

1

0

7

0

1

5

OLE
DCl
01

DC3

..

1

0

0

1

1

7

1

0

0

0

8

97

1

0

0

1

•

80

1

0

1

1

B

1

1

0

0

C

1

1

0

1

D

1

1

1

0

E

1

1

1

1

F

09

90

81

B5

O.

87
CAN
EM

,. .
.. .
98

SA

8F

IC

AS
US
OF

AC

. .,

AE

B6

CO

A6

AF

87

Cl

A7

80

B8

C2

A8

Bl

B9

07

50

=

2.

,.

2C

2A

23

25

40

SF

27

-

I

29

; 38

3E

30

A

21

5E

(~)

t """,
.

.

11-----,

3F

22

6A
k

I

66
67
I

.,

76
w

n

70

"
72

,
,

7B
79
7A

og
DA

0

C

I·

.A

DC
DO
DE
OF
EO
El

C

46
G

47
H
I

..
49

4

55

w

..

X

50

v
51

A

.,

.
.
57

4F

a

.. •

34

5

V

a

3J

54
U

4E

45
F

32
3

40
N

31

53

4C
M

44

3D
1
2

T

'3

E

9F

'B
L

0

50

S

K
'2

DB

0

\
70

J

41

B

1

F

E

I

"

A

0

Z

SA
F.

3•

J6

7

37
8

38
9

39
FA

0
1
2
3
4
5
6
7

•
9
A

Cd

CB

02

E2

E8

EE

C5

CC

03

E3

E9

EF

F5

F8

8

C6

CO

Q4

E4

EA

FO

F6

. Fe

C
0

C7

CE

0'

E.

EB

F1

F7

FD

C8

CF

06

E6

EC

F2

F.

FE

E

co

00

07

E7

ED

F3

F.

EO
FF

F

Character Address

"

Loea'tion in ASCII·S (ROM Cont)

6-79

75

6F

68

45 :I

(If Any)

7.
u

" 6E

.

,

Character Assignment

7E
73

60

0

h

,

6C
m

64
65

DB

I

63

I

01

-

68

62

Hexadecimal EBCDIC

C5

'-----,-----:0
I: IE

,

•

@

%

28

3A

7C

24

JC

9E
SUB

60

:

I

61

BF

B5

CA
I

b

BE

AS

I

IS

06

BD

B3

AO

2E
14

8EL

lF

A3

<

NAK

ACK
IE

DE
51

AB

8C

A

1

1
1

0

1

1

1

0

0

1

0

•

C3

A2

2F

BB

.

B2

S

05

BA

AA

98

ENO
10

20

I

Al

5B

DC.

Be

26

1

•

7

6

A9

I

9'

88

GS
00

SO

04

lB

19

DC
CA

EaT

0

1

0
0

AO

A.

96

17

ESC

FS

FF

95

OA

92

8E
VT

..
93

ETO
DB

7F

16

BJ

•

0
1

1

1
1

1

0

0

1

1

1

1

0

0
1

1

5

20

SVN

82

1

1

5'

91

LF

B.

DEL

A

so

B4

90

HT

1

0

13

OJ
9C

1

1

12

02
ETX

0

0

11

DC2

STX

0

1

10

00

SOH

0

0

•

3

1

1

1

0

0
1

0
1

2

1

NUL

1

0

1

0
1

0
1

3---0

0

0
0

0

~

MOS ROMs

NAllONAL

MM4230QY /MM5230QY
ASCII-8 -to- EBCDIC-8 code converter

general description
The MM42300Y IMM52300Y is a 2048·bit read
only memory -that has been programmed to con·
vert the American Standard Code for Information
Interchange extended to eight bits, (ASCII·8) to
Extended Binary Coded Decimal Interchange Code
(EBCDIC·8). The conversion conforms to the prac·
tice established by the American National Standard

ANSlx3.26 1970. Exact details are shown in the
code table.
For electrical, environmental and mechanical de·
tails, refer to the MM4230/MM5230 2048·bit read
only memory data sheet.

typical application

connection diagram

.,.

Dual-In-Line Package

-IZV

lSI

E,

E,

E,
E.

E,
E,

E,

MS.

E,
+12V

....

I""UT~

TYPICAL,

II

"

v,•

IIWUTA 2

I LINES

'rdI'UTA,

"
"
"

OUTPUT I,

INPUT A.

OUTPUT 82

'''UTA"

OUTPUT 83

IIIPUTAe

OUTPUTB4

IIW4.ITA,

OUTPUTB s

INPtITAe

o.

...

~
3

~

v~

OUTPUT&.

MODE

OtlTl'IITB 7

o.

COIIITflOl
CHIP
EIlAIlE

OUTPUTI,

.
"
..

v"

DTLmLLOGIC

tMode Control = Logic "0," As = Logic "1,"
·Chip Enable::::: LOgle "I" toobtaio outputs.
Logic levels:
DnmL (except ilt MOS/ROM interface), Logic "1," +5.DV. NOM. Logie "D." ground. NOM.
MUS/ROM inputs Ind outputs.. Logic "1," more negative. logic "D." mOn! pOsitivI.

"

TOPVlEW

"

'.UTA"

Order Number MM42300YIJ
or MM52300Y IJ
See Package 11
Order Number MM52300Y/N
See Package 18

code conversion table

"a-O

0

b7~O

0

"a-b

~

1

• •••
0

0

0

0

0

NUL

OLE

0

0

0

1

1

0

0

0

0

1

0

0

1

1

1

1

0

1
1
1

0

1
0

5
6
7
8

1

9

0

0

A

1

1

1

0

4

1

1

1

1

3

0

1

1

0

2

0

0

1

1

1

0

1

0

0

0

1

0

1

1

0
0
1
1

1
0
1
0
1

8

c
a
E
F

SP

DCl
DC2
DC3

03
ECT

13
DC4

·37
END

. 7F

3C

3D

20
SVN
2E

5
6

26

2F

18

16

19

05
IF

SUB
3F

25
ESC

liT

27

DB

F8

40

I

EM

HT

F9

50

.

5C

4E

5E

lC

DC
00

60

10
IE

DE
SI
OF '

48

I

U,S,
IF

61

,

6A.

t
94

n

DEL

96

60

00
AI

95
0

1 maybe"l"
2 maybe"--.,"
3

CO

93

SF

06

A9

:

SA

-

A8

,
I

m

I\@
OS

A7

92

EO

I

0
6F

4A

D4

A6

91
k

I

N
6E

89

i
E9

03

,

88

E8

02

7E

>

87

07

0

1
1

1
1

0
0

1

0

1

1

1
1

1

1

1

1

0

1

0

1

1

i
~

8

9

A

B

C

D

E

F

20

30

41

58

76

9F

B8

DC

21

31

42

59

77

AD

B9

DO

1

BA

DE

2

B8

OF

3

22

lA

43

62

78

AA

23

33

44

63

SO

AB

- -- 24

.34

45

15

64

.. -

Row

0

-

SA

AC

BC

EA

4

35

46

65

8B

AD

BD

EB

5

06;

36

47

66

8C

AE

BE

EC

6

17

08

48

67

80

AF

BF

ED

7

28

38

49

68

8E

SO

CA

EE

8

Bl

CB

EF

9

AS
w

V

L

M

I

RS.

SO

" 4C

6B

-

GS

CR

86
9

I

K

A4
v

h

Z
01

7A

A3
u

85

E7

C9

t

84

V

J

FS

FF

C8
I

9

.

E6

X

A2

83

E5

W
C7

99
s

f

C6

H

8

E4

1/

G

F7

10

I

CAN

BS

.CS
F

7

ETB

E3

98

,

d

U

F6

SO

32

BEL

81

E2

C4

F5

6C
&

q

c

T

E

97

79

08

C3
0

F4

58

p

a

S

C

4

%

07

Cl

F3

7B

\

0

7

6

A
b
8
F2 . C2
D9
82

3

S

NAK

ACK

2

•

7C
A

Fl

4F

..

12

Q2
ETX

1

5

p

@

40 OFO

(j)

!

11

01
STX

0

0

1

1

4

3

0

1

1

0

0
0

0

1

1

1

1

1

1

0
0

1

0

0
1

0

1

2

10

00
SOH

0
1

0

1

0

. . .3 . , b1 ROW.-

0
1

0

"a-O

0

0

0

0

29

39

51

69

8F

2A

3A

52

70

90

B2

CC

FA

10

28

3B

53

9A

' 83

CD

FB

11

2C

04

..

71

72

98

B4

CE

FC

12

09

14

55

73

9C

8S

CF

FD

13

OA

3E

56

74

90

B6

DA

FE

14

lB

El

57

7.

9E

B7

DB

EO

IS
FF

The Hexadecimal EBCDIC entry is formed thus:
Eight EBCDIC bits

The top I ine in each entry to the table represents an

MSB

assigned character (Columns 0 to 71. The bottom
line in each entrY is the corresponding EBCDIC Code,
in hexadecimal notation.

o

1 2 3

45 6 7

1st Digit

2nd Digit

Example: 0 1 0 1
5
To convert ASCI 1-8 asterisk (*1 to EBCDIC·B
ES
El
* in ASCII is a 2A or binary 0010 1010
applying this as an address to the MM5230QY IMM4230QY
bit-O bit-7
gives the output 0101 1100, which is an EBCDIC-!! asterisk.

6-81

1 1 00
C

LSB

or'

[II

C/)

a:
o(t)
N

It)

:E
:E

~

MOS ROMs

NAT10NAL

.......
C/)

a:

o
(t)
~

MM4230RS/MM5230RS binary to
modulo-n divider code converter

:E
:E

general description
Applying the required division ratio, in binary, to
the inputs of the ROM as shown, generates two
sets of. four program inputs, one for each of the
2 DM7520/DM8520 dividers.

The MM4230RS/MM5230RS binary to modulo-n
divider code converter is set up to generate the
program input settings for a pair of DM7520/
DM8520 modulo-n dividers, in order to divide by
any binary number from one to 255. Detailed
instructions for use of the DM7520/DM8520 are
given in its data sheet.

For electrical, environmental and mechanical de·
tails, refer to the MM4230/MM5230 data sheet.

connection diagram
Dual~1 "-Line

Package

INPUTAi_1
IN'U1"2.- Z

»_IIC

INPUTA,"';'3

Z2-IIIC

DUTPUTB,-4

21-''''U1",

OUTPUTB l -

S

IS-INPUT.."

OUTl'Ur6._ )

"-'.ItPUTA,

OUTPUlls":",,, a

11_INPU~""

DtlTPUra s -

IS-VOG

ZO_INf>UTAs

,

OUTPUTB7 _10

l!i-~g:ROL

DUTPUTB._:,

14 -~:~8LE

Order Number MM4230RS/J or MM5230RS/J
Se~ Package 11
Order Number MM5230RS/N
See Package 18

IISS-L"_--:=",,-_";J-IIfPUTAe
TOP.VIEW

typical application
Binary' to Modulo-n Divider

_ECT
.DiRlCTTO
.-

+If

... ,."

.-

,. .-...

1'"AR'2"
DIVISOR

"

,LSI
111611

TRUE

V

.-

....
V

v

t" ~I

"

.
."
"
'.
"
"
"

I" ...·1""

Y"

...,...
:::

CONTROL",

.

..
""..
'.
.."
..

CHIP
.."ENABlE V.VCIG

Lf-fF
-12V

6112"

•"'U11I

')
:

~

..

.......

~
......

...

I

~ ~

>.
)
P,
DIVlDlRl

>,

...

DlVlDfU

>,

>,

3:
3:

code conversion table

~

N
+BY

SETTING

I

DIVIDER 1

DIVIDER 2

B.

B,

II,;

B.

B.

B3

B,

,.

1
0
1
0
0
1
0
0
0
0

I
I
0
1
0
0
1
0
0
0

1
1
1
0
1
0
0
1
0
0

1
1
1
1
0
1
0
0
1
0

1
1
1
1
1
0
1
0
0
1

1
I
1
1
1
1

0
0

0
0

0
0
0
0
0
1
1
1
0
1

0
1
0
1
1
1
1
0
0
1

0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
0
1
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
{
1
0
1
1
0
0
1
0
0
0
0
0
0
0 ,0
1
0
1
1
0
1
l'
0
0
1
1
0
1
1
1
1
0
1
0
0"
0
0
0
0
1
0
0
1
1
0
1
1
1
1
1
I0
1
0
0

0
0
0
1
1
1
0
0
0
1

1
0
0
0
1
1.
1
0
0
0

0
1
1
0
0
1
0
0
,1
0
0
1
1
1
0
1
0
1
1
0

1
0
1
1
0
0
1
0
0
1
0
0
1
1
1
0
1
0
1
1

0

0
0
1
0
0
0
0
0
0
0
1
1
1
0
1
1
0
0
D
0
0
0
1
0
0
1
1
0
1
0
0
0
0
0
1
1
0
1
0
·1
1
1
0
0
0
0
1
0
1
1
1
1
0
0
1
0
0
0
1
1
1
0
0
0
1
0
1
1
0
0
1
0
0
1
0
0
1
1
1.
0
1
0
1
1
0
1
1
0

0

0

1
1
1
0
1
1
0
0
0
0
0
0
1
0
0
1
1
0
1
0
0
0
0
0
1
1
0
1
0
1
1
1

0

0'
0
0
0
1
0
1
1
1
1
0
0
1
0
0
0
1
1
1
0
0
0
1
0

,

1
0
0
1
0
·0

1
0
0
1
1
1
0
1
0
1
1
0

,
1

1
1
1
0
1
1
0
0
0
0
0
0
1
0
0
1
1
0
1
0
0
0
0

0
1
1
0
1
0
1
1
1
0
0
0
0
1

0'

"

1
1
1
0
0
1
0
0
0
1
1
1
0
0
0
1
0
1
1
0
0
1
0
0
1
0
0
1
1
1
0
1
0
1
1
0
1

1
0

0
0
0
0
0
1
0
0

1
1
0
1
0
0
0
0
0
1
1
0
1
0
1
1
1
0
0
0

0
1
0
0
0
1
1
1
0
0
0
1
0
1
1
0
0
1
0
0
1
'0
0
1
1
1
0
1
0
1

B,

II,;

255
254
253
252
251
250
249
248
247
246

1
0
0
1
1
1
1
0
1
1

0
1
0
0
1
1
1
1
0
1

1
0
1
0
0
1
1
1
1
0

245
244
243
242
241
240
239
238
237
236
235
234
233
232
231
230
229
228
227
226

0
1
1
1
0
1
0
0
0
1
1
0
1
1
0
0
1
1
1
0

1
0
1
1
1
0
1
0
0
0
1
1
0
1
1
0
0
1
1
1

1
1
0
1
1
1
0
1
0
0
0
1
1
0
1
1
0
0
1
1

225
224
223
222
221
220
219
218
217
216
215
214
213
212
211
210
209
208
207
206

0
1
0
1
1
0
1
0
1
0
0
1
0
1
1
1
0
1
1
1

0
0
1
0
1
1
0
1
0
1
0
0
1
0
1
1
1
0
1
1

1
0
0
1
0
1
1
0
1
0
1
0
0
1
0
1
1
1
0
1

0
0
0
1
0
1
I
1
1

1
0
0
0
0
1
0
1
1
1

205
204
203
202
201
200
199
198
197
196

1
1
0
1
1

1
1
1
0
1
1
1
0
0
1

1
1
1
1
0
1
1
1
0
0

0
0
1
0
0
0
1
1
1
0

1
0
0
1
0
0
0
1
1
1

195
194
193
192
191
190
189
188
187
186

1
0
0
0
0
1
1

0
0
1
0
1
1
0
0
1
0
0
1
0
0
1
1
1
0
1
0

0
0
0
1
0
1
1
0
0
1
0
0
1
0
0
1
1

185
194
183
182
181
180
179
178

1
1
0
0
0
0
1
1
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
1
1
1
1
1

1
1
1
1
1
1
O. 1
1
0
0
1
0
0
1
0
0
1
O. 0
0
0
0
0
0 0
0
0
0
0
1
0
1
1
1
1
0
1
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0 0
1
0
1
0
0
0
1
0
1
1
0
1
1
0
0
1
0
0
0
0
0
0
0
0
1
0
1
1
1
0
1
0
1
0
1
0
1
1
1 '1

0

I

DIVIDER 1

Bs

B,

,

0
1

177

176
175
174
173
172
171
170
169
168
167
166

: BY

SETTING

l'

0
0
1
1
0
0
0
0
1
1
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
1
1
1
1
1
0
0
1
1

0

0
1
0
1
0
1
0
0
0
1
0
1
0
1
1
1
1
1
1
0
0
1

0

0

DIVIDER 2

B. I B. Bo
I
1
0
1

0
'0
1
1
1
1
0
1
1
0
1
1
1
0
1
0
0
0
1
1
0
1
1
0
0
1
1
1

B,

I
1
1
1
0
0
0
0
0
1
0
1

0
1
1
0
1
1
0
1
0
0

1
0
1
1
0
1
1
1
0
1
0
0
0
1
1
0
1
1
0
0
1
1
1
0
0
1
0
1
1
0
1
0
1
0
0
1

1
1

1
1
1
0
1
1

1
1
1
1
0
1
1
0
1
1

165
164
163
162
161
160
159
158
157
156
155
154
153
152
1"51
150
149
148
147
146

1
0
1
0
0
0
1
1
0
1

145
144
143
142
141
140
139
138
137
136

1
l'
1
1
0
0
0
1
1
0

0
1
1
1
1
0
0

135
13.
133
132
131
130
129
128
127
126

0
0
1
0
0
0
1
0
0
1

125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107

0
1
0
0
1
1
0

0
0
0
1
0
0
0
1
0
0
1
0
1
0
0
1
1

0

0

1
1

0
1
1
0
1
1
1
1
0
1
0
1

0
1
1
1
0
0
1
0
1
1

0
0
1
1
1
0
0
1
0
1

1
0
0
1
1
1
0
0
1

1
1
1

0
1
0
1
0
0
1
0
1
1

1
0
1
0
1
0
0
1
0
1

1
1
0
1
0
1
0
0
1
0

1
1
1
1
1
0
1
1
1
0

0
1
1
1
1
1
0
1
1
1

1
0
1
1
1
1
1
0
1
1

1
1
0
1
1
1
1
1
0
1

1
1
1
0
1
1
1
1
1
0

0
1
1
0
0
0
0
1
1
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
1
1
1
1
1
0

0
0
1
1
0
0
0

"

1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
1
1
1

1
1
1
0
0
1
l'
0
0
0
0
1
1
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
1
0

0
1
0
0
1
0
1,
1
1
0

I
1
1
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
0
0

1
1
0
1
1
0
1
0
0
1

1
1
1
0
1
0
0
0
1
1
0
1
1

0
1
0
1
1
0
1

B,

1
0
1
1
0
1
0
0
1
1

1
1
0
1
1
1
0
1
0
0
0
1
1
0
1
1
0

0

Bs

0
1
1
0
1
0
0
1
1
1

0

0

0

1
1
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
1
1
1
1
1

0
0
1
1
0
0
0
0
1
1
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
1
1
1
1

0

..

i

DIVIDER 1

B,

0

106
106

104
103
102
·101

100
99
98

97
96
95
94

93
92
91
90
89
88
87
86
85
84
83
B2
81
80
79
78
77

76

0
1
1
1
1
0
1
0
1
0
1
0
1
1
0
0
0
1
1
1
1
1
1
1

DIVIDER 2

B3

B,

B,

0
0
1
1
1
1
1
0
0
0
0
0
1
0
1
0
0
0
0
1

·1
0
0
1
1
1
1
1
0
0
0
0
0
1
0
1
0
0
0
0

I
1
0
0
1
1
1
1
1
0
0
0

0
0

I
1
1
0
0
1
1
1
1
1
0
0
0
0
0
1
0
1
0
0

0
0
0
0
1
1
1
1
0
0
0
1
1
0
0

1
0
0
0
0
1
1
1
1
0

0
1
0
0
0
0
1
1
1
1

0
0
1
0
0
0
0
1
1
1

0
0
1
1
0
0
0
1
0
0

0
0
0
1
1
0
0
0
1

0
1
0
0
1
0
1
0
0
1

0
0
1
0
0
1
0
1
0
0
1
1
0
0
1
1

1
0
0
0
1
1
0
0
0
1
0
0
0
1
0
0
1
0
1
0

B'lB.

1
1
1
'1
1
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0

0
1
1
1
1
1
0
0
0
0
0
1
0
1
0

0
0
1
1
1
1
0
0
0
1

1
1
0
1
1
1
1
0
1
0

0
0
0
'1
1
1
1
0
0
0
1
1
0
0
0
1
0
0
0
1
0
0
1
0
1
0
0
1
1
0
0
1
1
0
1
1
1
1
0
1

0
1
0
1
1
0
0
0
1
1

1
0
1
0
1
1
0
0
0
1

0
1
0
1
0
1
1
0
0
0

0
0

1
1
1
1

1
1
1
1

1
1
1
1

0
1
1
1

0
0
0
0
1
0
0
0

0
1
1

1
0
0
0
1
0
0
0
1
0
0
1
0
1
0
0
1
1
0
0

; BY

SETTING

0
0
0
1
0

0,

1
0
0
0
1
0
0
1
0
1
0
0
1
1
0
0

1
1
0
1
1
1
1
0
1
0
1
0
1
0
1
1

1
0
0
1
,1
0
1
1
1
1
0
1
0
1

0
1
0
1
1
0
0
0
1
1

0
0
1
0
1

0

75
74
73
72
71
70
69
6B
67
66
65
64
63
62
61
60
59
58
57
56
55
54

53
52
51
50
49
48
47

46

0
1
1
0
0
1
1
0
1
1

'1
0
1
0
1
1

1
1
0
1
0
1
0
1
·0
1

15
14
13
12
11
10
9
8
7
6

0
0
0
1

1
0
0
0

5
4
3
2

0

1

1.
1
1
0
1
U

o

::D

45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
' 19
18
17
16

0

W

en

......

3:

3:

UI
N
W

o
::D
en

~

MOS ROMs

NAll0NAL

MM42311MM5231 2048-bit read only memory

general description
The MM4231/MM5231 is a 2048-bit static read
only memory_ It is a P-channel enhancement mode
monolithic MOS integrated circuit utilizing low
threshold voltage technology_ The device is a nonvolatile memory organized as a 256-8 bit words or
512-4 bit words_ Programming of the memory
contents is accomplished by changing one mask
during the device fabrication_

Bipolar compatibility
High speed operation

Static operation
Common data busing

•

Chip enable output control

Output wire AND
capability

applications
•
•

features
•
•

No clocks required

•
•

Code conversion
Random logic synthesis

• Table look-up
• Character generator
• Microprogramming

+5V, -12Voperation
640 ns typ_

block and connection diagrams

INPUTS

-r____

Duai-in-Line Package

.

~--~~1II5EAMPLIFIERS

OUTPUTSt

s,

INPUT",

Voo

INPUT Al

A,

"

A,

s,

"

LSBINPUTA1
lSB OUTPUT I.

"

"

"

"
"

OUTPUT

As

INPUT""
INPUT A,

OUTPUTS.

A,

INPUT A"

INPUT

OU1PU182

INPUT

B~

As MIS

OUTPUlls

Voo

OUTPUT.I,

MODE
CONTROL

CHIP
ENABLE

MIS OUTPUT ..

INPUTAg

. ----.----'

Order Number MM4231J
orMM5231J

MODECONTROl-----l_r

See Package 11

tTheoutputsareopenwhen Disabled.
*Theoutputisenllbled by applying a lo.gic"1" to the Chip En.blelioe.

Order Number MM5231N
See Package 18

Note: For programming information see AN-100.

6-84

absolute maximum ratings
VGG Supply Voltage
Voo Supply Voltage
Input Voltage
(V ss - 20)V
Storage Temperature
Operating Temperature MM4231
MM5231
Lead Temperature (Soldering, 10 sec)

Vss - 20V
Vss - 20V
< V'N < (Vss +0.3)V
_65°C to + 150°·C
-55°C to +125°C
O°C to +70°C
300°C

electrical characteristics
PARAMETER

CONDITIONS

MIN

Output Voltage Levels
MOS to TTL
Logical "1"
Logical "0"

6.8 kn ±S% toV oo Plus One
Standard Series 54/74 Gate

2.4

V
V

Output Current Capability
Logical "0"

V OUT

2.5

mA

= 2.4V

input Voltage Levels
Logical "1"
Logical "0"
Power Supply Current
100

IGG (Note 1)
I nput Leakage

TYP

MAX

+0.4

Vss - 4.2

V
V

30
1

mA
/.I.A

1

/.I.A

Vss - 2.0
TA

UNITS

= 2SoC

Vss = +5V
VGG = Voo = -12V

15

V'N = -12V

Input Capacitance

f = 1.0 MHz, V ,N = OV

5

pF

VGG Capacitance

f = 1.0 MHz, V'N = OV

15

pF

Address Time (Note, 2)

See Timing Diagram
T A = 25°C Vss = +5.0V
VGG = Voo = -12.0V

T ACCESS

Output AND Connections
(Note 3)

640

6.8 kn ±5% to Voo Plus One
Standard Series 54/74 Gate

Note 1: These specifications apply for VSS = +5V ±5%, VGG = VDD = -12V, ±5%, and T A
to +125°C (MM4231), T A = -25°C to +70oC .(MM5231) unless otherwise specified.

8

= -55"C

Note 2: The VGG supply may be clocked to reduce device power without affecting access time.
Note 3: Address, time is measured from the change of data on any input or Chip Enable line to the
output of a TTL gate. (See Timing Diagram.) See. curves .for guaranteed. limit over temperature.·
Note 4: The address time in the TTL load configuration follows the equat!on:
T ACCESS = The specified limit + (N - 1) (?O) ns ..
Where N = Number of AND connections.
No~e 5: capacitances are measured on a lot sample basis only.

6·85

950

ns

0

performance characteristics
Guaranteed Access Time (TAl
vs Power Supply Voltage
1400

Typical Accass Time (TAl
vs Power Supply Voltage
1400

~DD = VGG

1200

Voo'" VGO

1200

+!2~OC

+70"'C
+25°'C

1000

1000

BOO

g

600

~ 600

]
I

...<

BOO

400

400

200

200

+1,25:C
+7lrC
+25'C

0

0
16.0

lB.O

17.0

Power Supply Current vs
Ambient Temperature

Power Supply Current vs

32

40
TA ", 2S"C

24

1
Jl

Vss"'+5.0V'~

J6

~U~~~:T~~O

Yoo = VGG = -12V

J2

JJ III

28

20

~

oS

16
12

0

.E

TYPICAL

MAXIMUM"""
GUARANTEED

24
20
16

II I I

H4-Ll.

12

B

·nn
IIII

8

4

4

0

0
16.0

lB.O

Vss- VGG (V)

Power Supply Voltage

2B

17.0

16.0

Vss - VGG tV)

17.0

-50 -25

18.0

0 +25 +50 +15 +100+125

Vss - VaG (V)

TA"rcI

timing diagram/address time

~
EITHER

I~

E,.

~TA~'~J

~v~-',ov

"

1.5V
EOUT

1.5V

I
tillle

+5V

'Iv~

'5V

"TL
OV

I.
ANVTTL/DTl

GATE

'.'UT A"-ri MM4Z3IfMMSZ31

EIN~10Pf

*"

..,

V~I

..V

Eou.

t·

10 PF:J.:

UK

-,Tv

6·86

I

OU"TPUTIIM

~

ANY TTUDn

GATE

.:J.::
~

15 pF

typical application

256 x BBit ROM Showing TTL Interface

A.

,
,

'

l'

CHIP

..

B,

'.

'"
A.

B,

A,

B,

MM4131IMM5111

A.

"",}

B,

A,
B,

A.

,I

B,

TTL GATES

A,

.,
'00

i
tSee operat'ing mode notes.

}-.

B,

MODE

CONTROL

I

"

A,

1

Operating Modes
256 x 8 ROM connection (shown)
Mode Control ~ Logic "0"
Ag
- Log;c ".1 ".
512 x 4 ROM connection
Mode Control - Logic "P'
Ag
- Logic "0" Enables the odd

(B1, B3 ... Bgi outputs
-

l..ogic "1" Enables the e;ven

(62,64· .. 681 outputs.
The outputs are "Enabred~' when a logic "1" is
applied to the Chip· Enable line.

logic levels are negative true MOS logic.
Mode Control should be "hard'wired" to'VOD
(Logical ".1".1 or VSS (Log;cal "0"1.
The logic levels are in

negative voltage

logic notation.

I

OTt/TTtLOGIC

c..
a:
~

M
C"II

It)

~
~

~

MOS ROMs

NATIONAL

......

c..
a:

C;;
C"II

MM4231RP/MM5231RP EBCDIC to ASCII-7 co"de converter

~

~
~

general description
The MM4231RP/MM5231RP is a 2o.48-bit readonly memory that has been programmed to convert from EBCDIC,an extended binary coded
decimal interchange code used in the IBM 1130.
computer, to ASCIi-7, the American Standard
Code for Information I nterchange in seven bits.

conversion of the MM423o.QX/MM523o.QX in that
it follows certain earlier IBM 1130character assignments. Also certain EBCDIC control codes are
arbitrarily preserved and translated (see translation chart on truth table).
For electrical, environmental and mechanical details, refer to the MM4231/MM5231 data sheet.

This conversion differs from the ANSI x 3.26

typical application

EBCDIC TO ASCII-7

..v
EBCDIC
LOW TRUE

BIT

usa

•

17

11

"
,.
"

'58

ASCII
HIGH TRUE

12,15

.

•• ~"---------------..........-lI'>
II,

A,

.
.
.

HIGH'" Graphit
LOW=Control

10

~~--------------------~--~--+-~~~
~~~--------.--+--+--+-~
MM52JlflP

~~--------.--+-~--~-+-~

__-oB,

A,

B,~-------'---+-~+---+---+---+-_~~

A,

·'r---....-+--+--t--t-~I--t--:JI::---o.,

A,

.,j-:.-.....-+-+--+--t--i--I--I--l(")...

b,

DM7404

16,24,13

UK

UK

UK

6.8K

6.8K

UK

UK

S.8K

-12V

Order Number MM4231 RP/J or MM5231 RP/J
See Package 11

Order Number MM5231 RP/N

See Package 18

6-88

code conversion tables

CODE

FUI\lCTION

OUTPUT

EBCDIC
SYMBOL

ASCII

SYMBOL

MSB

0

NULL

NUL

0

0

0

1

SOH

SOH

0
0

a

0

0
0

0

a
a

a

a
a

a
a

0

0

0

ROM
ADDRESS

2

STX

STX

3

ETX

ETX

4

PF

5

HT

6

LC

7

DEL

HT

\

DEL

9
SMM

11

VT

VT

12

FF

FF

13

CA

CA

14

SO

SO

15

SI

Sl

16

·DLE

OLE

17

DCl

DCl

18

DC2

DC2

19

De3

DC3

20

AES

21

NL

22

BS
CAN

CAN

25

EM

EM

26

CC

27

CUI
FLS

FS

29

GS

GS

30

ADS

AS

US

US

28

31
32

OS

33

SOS

3.

FS

LF

LF

EO.

E.T8

39

PAE

ESC

45

ENQ -

ENQ

46

ACK

AeK

47

BEL

BEL

SY-N

SYN

53

PN
AS
UC
EOT

EO.!_~

57
58
59

CU3
DCA

1

0

a

0

1

1

0

1

a

0
0

a

I

a

I
I

a
a

I

0
0

a
a
a
a
a

LSB
0
0

a
a

a
a
a

a
a

0

a

a

0

1

a

a

0

0

0
0

1

a

1

1

a

a

1

a

0

1

1

1

1

1

1

1

1

0

a
a
a
a
a
a
a

0

1

0

1

1

0

1

1

a

a

a
a
a

1

1

0

1

1

1

1

0

1

1

1

1

1

a
a

a
a

a

a
a
a
a
a
a
0

0

a

a

1

1

1

1

a

a
a
a
a
a

1

1

a

1

1

1

a

a

0

a

1

a

0

a
a

1

1

0

a

a
a

1

1

a

a
a
a
a

a
a
a

a
a
a
a

1

1

1

1

1

a
a

0

1
1

1

1

1

a

1

1

1

1

1

0

a
a
a
a

a
a

a
a

a

a
a

a

1

a
a

0

1

a

1

1

1

0

1

1

a

1

1

a
a

a

a

a

1

a

1

0

0

0

0

1

1

0

0

0

0

0

0

1

1

1

0

a

0

1

0

1

1

a

a

0

a

1

0

1

0

0

a

a

a

0

a

1

a

0

61

NAK

NAK

62
63

SUB

SUB

a
a
0

a

I
I
I
I

De4

56

60

0

a
a
a

I

51

54

0

I

49

55

1

I

48

52

0

I
I

44

50

a

I

41
eU2

a
a
a
a

I
I

40

43

0

I
I

BYP

3.

SM

0

0

1
1

0

a
a

1

1

a

1

1

a
a
a

a

a
a

a

0

a
1

1

CONTINUING BINARY
SEOUENCE

37

42

0

I

3S
36

MSB

0

I

BS

IDL

24

CC/G

0

I

\

23

LSB
0

""

8
10

OUll'UT

INPUT

INPUT

-"

I
As

A7

I As I AS I A4

A31 A2

6-89

1

a

0

a

1

0

1

0

1

,

0

0

1

1

0

Sa

87

1
84

0

A1

0
86

83

82

81

8S

0-

...

a:
M
N

code conversion tables(con't)

It)

::!:
::!:

.......

FUNCTION

0-

...

a:

M
N

'I:t

::!:
::!:

ROM
ADDRESS
64
65
66
67

COOE

INPUT

OUTPUT

EBCDIC
SYMBOL

ASCII
SYMBOL

SP

SP

INPUT

MSB

\

"

69
,0

<
<

<

17

(

(

+

+

19
80
81

&

&

0

a

cO

a

a

1

1
0

1
1

1
0
1

1
1

1
1

1

0
0

LSB

1
1
1

0

1

0

0

0

1

0

1

0

0

a

1
1
1

0
1

1
1
1

a

1
1
0

0
1
1

1
0
1

1
0
0

1
1

0
0

0

a

0

0
0

0
1
1

0
0

1
1

0
0

1
0
1
1

1
1
0
0

1
0
1

0
1
1

1

1
0
1

a

1
1

1
1

0
0

1
0

1

0

1

1

1

1
1
1

0
1

0
1

0
1

1
1

1
,0
0
0

0

1

1
0

1

1

1

8'
88
89
!

!

$

$

,

-I

I

,

,

I'

I

I

1

0

1

0
0
0

1
1
1

CONTINUING BINARY
SEQUENCE

1
1
1

0
1
0
0

1
1

1

0
1
1

1

1
1

1

99
100

I

101
102
103

I

104
105

I
I
I
I

106
107
108
109

%

110
111

>

>

?

?

%

112
113
114
115
116
117
118

1
1
1

0
0
1

1
1

0
0

1
1

1
1

1

1

1

1

0

1

0
0
0

a

1

0

0
1

1
0
1

1

I
I

119
120
121
122
123

#

#

124
125
126

@

@

127

1

I

85
86

96
97
98

a

I
I

:

82
83
84

92
93
94
95

MSB

1

I
I

-

78

90
91

CC/G

I

I

71

75
76

LSB

I

66

72
13
7.

OUTPUT

"

1

~s I

-"
A7

I

A6

I

Asl A.

I

A3

6-90

I

A2

I A~

1

0

1
1
1
1

0
1
0
0

0
1
1

1

0

BS

B7

1

1
1

1

1
0

0

B6

B5

B.

0
1
0
1
1

0

0
1

0

B3

B2

B,

code conversion tables(col"!'t)

FUNCTION

ROM
ADDRESS

OUTPUT

EBCDIC
SYMBOL

ASCII
SYMBOL

128
129

,

130

,

131
132
133
134
135
136
137
138
139
140

CODE

INPUT

b

d

e
f

9
h

.

INPUT
LSB

MSB

a
b

,

.
d

9
h
;

141
142
143
144
J

k

k

147
14B

I

J

m

m

14.

n

n

150
151

0

0

P

P

152

q

Q

153
154

,

,

t

t

164

u

u

165 '

v

v

166

w

w

"67
168

x

x

17-1
172
173
17.

1

I

0
0

0
1

0
0

0
1
1

1
0

0
0

0
0
1

1
1
0

0
0

0
0

1
1

0
0
0
0

1

1
1
1
1
1

0

1

1

1

1

1

1
1

1

1
1

0
0
0

1

1
1

1
1
1
1

1
1
1

1

1
1
1
1
1
1
1

y

I
I

y

,

,

I

[

I

1
1
1

1

1

1
1

1
1

1
1

1

1

0
0
0
1

0

1
0
1

0

0
1
1

0
1

0

0
0

0
1

1

0

1

1

1

0
0

1
1

0
1

1

0

0

1
1
1

0

1
0

1
1
1
1
0

1

1

1
1

0

0
0
0

1

1

1

1

1

1

1

1

0
0
0

0
1
1

0
0
1

0

0

1
1
0

1

1

0
1

0
1
0

.0

1

1
1
1
1
1

1
t
1

1
1
1

1
1
1

1
1

1
1

1
1
1
1
1

1

1

0

1

1

Be

B7

1
1
1

1

1
0
1

1
1

0
0
1

0
1

1
1

0
0

1
0
0
1

1

1

0

1

1

0

1

1

1

0

1

B6

85

S.

B3

82

8.

1
1
1
t

0

1
0

I

176
177

I

178
17.
180

I
I

181
182
183
1'84

I

,.5
'186

187
,88

I

I

I

'90
.91

1

1
1

I
I

175

I ••

1

1
1

I
I

170

....

LSB

CONTINUING BINARY
SEQUENCE

,

169

1
1

I
I

158

162
163

I

I

155
156
157
159
160
161

MSB

I

I
I
I
I

f

J

CC/G

.......

\

145
146

OUTPUT

.A.

~ I I I As lAo I
A7

A6

A31 A2

6-91

I A:

Q.

a::
....

('I)

N
Ln

code conversion tables(con't)

~
~

Ii:

a::
M
N

~

~
~

FUNCTION

INPUT

OUTPUT

ROM
ADDRESS

'EBCDIC
SYMBOL

ASCII

'92
193
194
195
196
197

+ ZERO

0

0

E

E

198

F

F

199
200
201

G

G

A

SYMBOL

CODE

INPUT

,

MSB

"'"

A

B

B

C

C

H

H

I

I

203
204
205

-ZERO

209

J

J

210
211

K

K

L

212
213

M

M

N

N

214

0

0

215
216

P

P

Q

Q

R

R

217
218
219

L

224
225
T

U

U

V

V

230
231
232

W

W

y

X
y

233
234

z

z

X

0
0
0

1
1

0
0

0
0

1

0

0

1

0
0
0
0
0
0

0
0
0
0
0
0
0
1
1

0
0
0

0

1

1
1

1
1
1

0
0
1
1

0
1
0
1

1
0
0

0
1

0

0
1

0

1

1

0

0

1

0

1

1
1
1

1
1
1

0

0

1

0

1

0
0

0

1

0

,

1
1

0
0

1
1

1
1
1

0
0
0

1
1

1

1
1

0
1

1

0

1
1

1

0

1

1

1
1
1
1

1
1
1
1
1

0
0

1
0

0

-~
1

0
0

0

0
0

0
1

0

1

0

0

1

1
1
1
1

0
0
1
1

1
0
1

0

-"

0

1

0
0
0
0

1
1

0
0
0

1
1

0
0

0
1
0
1
0

1
1
1
1

0
0
0

1
1
1

,

1

1

0
0
0

0
0
1

1
1
1

0

1

1

0

0

0

0
0

1
1

1

0
0

0
0

0
1

1
1
1
1

0
0
0

1

0

0

1

0
1

,

0
0

1

1

0
0
0
0

1
1
1
1

0
0
1
1

0
1
0
1

1
1

0
0

1
1

1
1

1
1

0
0

0
0

0
1

BS

B7

BS

B5

B,

B3

82

B,

1
1

1

I

237

242
243
244
245
246
247
248
249
250
251
252
253
254
255

,
,

I

236

241

1
1

I
I
I

235

238
239
240

0
0

1
1

I
S

0

1
1

MSB

-

CONTINUING BINARY
SEQUENCE

T

1

1
1

1
1
1

222
223

S

,

1

220
221

226
227
228
229

CC/G

I

I
I
I
I
I

206
207

LSB

LSB

I
I
I
I

202

206

OUTPUT

0
1
2

I
I
I
I

,

0

2

3
4

3
4

5
6
7

5
6
7

8
9

8
9

I
1
1
1
1
1
As

,

........
1
1
1
1
1
A7

1

1
0
1

1

0
0
1

1

1

0
1

A2

A,

1

1

1

1
1
1

1
1

1
1

1

1
1

1
1

AS

A5

A4

A3

0
1
1

6-92

1
1
1

1
1
1

,
1

0
1

~

MOS ROMs

NATIONAL

MM4232/MM5232 4096-bit static read-only memory

general "escription

features

The MM4232/MM5232 4096-bit static read-only
memory is a P-channel enhancement mode monolithic MaS integrated circuit utilizing a low threshold voltage technology to achieve bipolar compatibility_ TRI-STATETM outputs provide wire ORed
capability without loading common data lines or
reducing system access times_ The ROM is organized in 512 word x 8-bit or 1024 word x 4-bit
memory organization that is controlled by the
mode control input. Programmable Chip Enables
(CE , and CE 2 ) provide logic control of up to 16K
bits without external logic. A separate output
supply lead is provided to reduce internal power
dissipation in the output stages.

• Bipolar compatibility

No external
components required
+5V, -12V

• Standard supplies·
•

a

TRI-STATE outputs

Bus aRable output

• Static operation

No clocks required

• Multiple ROM control

Two-programmable
Chip Enable lines

applications
• Character generator
• Random logic synthesis
• Microprogramming
• Table look-up

logic and connection diagrams

A,

A,

A,

Dual-In-Lina Package

..
A,

.
A,

A,

IIDOE CDNTROL
CE,
CE,

B,
8,
8,
MEMORV

8,

..

ARRAY

8,

B,

8,

A,.

24

22

..

•

21

B,

23

.
..

Aut

I
I
I
I
I
I
I
I
I

1
Z
,

.... ".
AJ

"

12

11

.

15

I, LSI

" ..

TIMI'VtEW

Order Number MM5232N

CE,

See P.~kage 18

Note: For programming information see AN-l00.

6-93

..

I. At MSB

See Package 11

CE,

~

"
" .,
" .,

Order Number MM4232J
·orMM5232J

MODE
CONTROL

Veo

.. a;

...... ,

V.

Vu

absolute maximum ratings

VGG Supply Voltage
VLL Supply Voltage
(V ss - 20)
Input Voltage
Storage Temperature Range
Operating Temperature Range MM4232
MM5232
Lead Temperature (Soldering. 10 sec)

electrical characteristics

Vss - 20V
Vss - 20V
v < Y'N < (V SS + .03)V
_65°C to +150°C
_55°C to +12SoC
O°C to +70oC
300°C

POSITIVE LOGIC

T A within operating temperature range. Vss = +5.0V ±5%. V GG = V DD = -12V ±5%. unless otherwise noted.
PARAMETER
Output Voltage Levels
Logical "0",

VOL

Logical "1", VOH

CONOITIONS

MIN

TYP

MAX

'L = 1.6 rnA Sink
IL

;

UNITS

.4

V
V

2.4

100 IJA Source

Input Voltage Levels
Logical "0", V!L
Logical "1", V 1H

VGG

Vss -4.0

Vss - 2.0

Vss + 0.3

V
V

37
20

mA
mA

15

pF

10

pF

Power Supply Current
Iss (Note 41
Iss (Note.4l

Vss = 5, VGG = -12. V LL =;; -12. TA "" 2SoC
Vss = 5, VGG = -12, V LL = -3, TA = 12SOC

Input Leakage

VIN

Input Capacitance (Note 1)

f

~

=

I'A

Vss -10V

1.0 MHz. V IN

~

OV

Output Capacitance (Note 1)

f"'" 1.0 MHz, V IN = OV

Address Time (Note 2)

T A = 2SOC. Vss

T ACCESS

23
12

=

4
150

5

1000

VGG = V LL =,-12V

20

Output AND Connections (Note 3)

Note 1: Capacitances are measured periodically only.
Note 2: Address time is measured from the change of data o"n any input or Chip Enable line to the output of a TTL gate.
(See Timing Diagram.)
Note 3: The address time follovvs the following equ-ation: TACCESS = the specified limit + (N ~ 1) x 25 ns where N .:: Number
of AND connections.
Note 4: Outputs open.

timing diagram/address time

'"

EOUT

TIME

6·94

performance characteristics
Guaranteed Access Time vs
Supply Voltage

Tvpical Aceess Time vs
Supply Voltage

Yu_ - VGG

1400

1400

125'C
12110 T.=IO"C
25'C

1200

125'C
11100 T.-IO'C
Z5'C

.. IODD

.

oS

~ 8GO

~ 8DD

600

'": 600

48D

400

200

200
·1&.2

17.0

1&.2

17.8

Vss + IVoG[ (V)

8D

17.8

Power Supply Current vs
Voltage

Power Supply Current vs
Temperature

10

17.0
Vss+IVGG I (V)

'"'4=mm-v;;:if.iiV"4
1-+
Vss - 5.0V
rt+!=t+!=t:tV~G~G:-~V;!LL~-~-;12~V~

60~~~tttt~~~
.!

40

MAXIMUM

MAXIMUM

Ji

«
5 0 .
Ji
30

3D

TYPICAL

20

20

10

10
-50 -25

a

25

TYPICAL

16.2

50 75 100 125

17.0

17.8

TEMPERATURE ('CI

typical applications
TTL/MOS Interl""e

v"

FIGURE 2. Power Saver to<
Large Memory Arr.,s

I-

B,

A,

....
B,

A.

..
.

FIGURE 1. Power Saver lor
Small Memory Arrays

As

MM42321
MM5Z32

B,

A,

I
I
I
I
v" o-"'iL----'

--,

r

---,

I

I

I

I

-= I

I
I
VC;G

.J

I
I
I
I
I
L ___ ..J

ASSUME IIVLL IIMIN" 11-3V II
VGG -VLLMIN" R (1.6 rnA) {NJwhn N" 1 for Sx1'onl.
N=8f11r6xllem.

CE;

0------'

",o-----~

Operating Modes
1024 x 4 ROM connection
Mode Control;;; VI L
Al0= VILenablest~eodd (B1 .. ' B7) outputs
VIH enables the even (82' .. Bal outputs

512 x 8 AOM connection
Mode Control = VIH
AID = VIL

Note: Both chip enables may be programmed to provide any 01 lour combinations. Example il CE, = , and CE2 = 1
outputs (Positive Logic) would be enabled only when device pins 2 and 3 are Logic "1". The outputs will be in the
third state when disabled.

6·95

~

w

..,w.
c(
,

c(

w

c(

~

MOS ROMs

NAnONAL

MM4232/MM5232 AEL AEJ. AEK sine look up table

N
C")

N

an

~
~

......
N

(")

N

'lit

general description
The MM4232/MM5232 AEI, AEJ and AEK are all
P-channel enhancement mode MOS read-only memories, each storing 4096 bits. They are programmed
to generate the sine function of any angle ex·
pressed as a binary fraction of a right·angle. They
may be combined and arranged to' provide a lookup table of varying resolution and accuracy, to

meet almost any system requ irement for generation of the sine' function.

application information
Figures 1 through 4 show the four ways that these
parts may be combined, The table shows the performance of all combinations.

~
~

performance specifications

FIGURE

ROM NO. USED

RESOLUTION
(= INPUT
WORD
LENGTH)

OUTPUT WORD
LENGTH

ACCURACY

ADDER PACKAGES
REQUIRED

+0
-lbitin8

1

AEI

9 bits

8 bits

2

AEI + AEJ

9 bits

16 bits

± 1/2 bit in 16

0

3

AEI+AEJ+
AEK

12 bits

16 bits

± 3/4 bit in 14

4

4

AEI+AEJ+
2 AEK's

15 bits

16 bits

±1 bit in 14

6

SINE LOOK-UP TABLE WITH HIGH
RESOLUTION AND ACCURACY

sine of an angle () resolved into 2'5 increments
7[12.
in the range 0 so:: ()

<

Theoretical Background

This error, due to the mathematical approximation,
is ±3.2x 10-5 maximum, corresponding to ±1 bit in
15 bits. In addition to the mathematical error, an
inevitable round-off error in the 16th bit is introduced. As there are 3 LSB outputs to be added
(Figure 4), the maximum round-off error will be
±1-1I2 bit in 16 bits or ±2.3 X lO-s The theoretical
maximum total error will then be ± (3.2 + 2.3)
.x 10'5 ~ ±5.5 x 10-5, which is slightly less than ± 1
bit in 14 bits.

The table is based upon the equation:
sin (M + L)

=

sin M cos L + cos M sin L

0

(1)

By splitting.M and L each into two parts MM,
M L, and LM, LL, and (assuming M
L) the following equation is obtained.

»

(2)
sin (M + L) '" sin (MM + ML)
+ cos (MM + 1/2 LSB of MM) sin LM
+ cos (MM + 1/2 LSB of MM) sin LL
'" sin (MM +ML)
+ cos (MM + 1/2 LSB of MM) (sin LM + sin LL)

A computer analysis shows that the actual errors
in the table as implemented are as follows:
+4.4 x 10-5 (at 61.872°)

The following approximations have been used:

-4.7 x 10- 5 (at 83.142°)

cos (LM + LL) '" 1
sin (LM + LL) '" sin (LM) + sin (LL)
cos (MM + ML) "" cos (MM + 1/2 LSB ofMM)

As the sine function is very linear in the LM·LL
range, the third term of Equation 2 can be considered as being 11(2)3 of the second term without
significant error. Therefore, the same pattern can
be used for the two lower ROMs in Figure 4, and a
total of three different masks are needed. In addition, six 4-bit adders are used.

By taking MM ~ 6 bits, ML ~ 3 bits, LM ~ 3 bits,
and LL ~ 3 bits, 15 bits resolution is obtained. The
accuracy has been computed by comparing the
values of Equation 2 with the ideal value of the
Order Number MM4232J or MM5232J

Order Number MM5232N

See Package 11

See Package 18

6-96

Ie = ,,/2 RADIANS)
SINu

A,

(Il" 17/2 RADIANS)

, . ' - A,
Z-2_ As

2--.3_ A,
MM42J2J
MM!iZJ2

Z--4_ As
2-6- A5

AEI

2--6_ A.

tEl =0
eE2 = 0

Z-7_

8, 10-2"2

A,

A,

r---

a6~Z-3

MM42321
MM523Z

AEI
tEl =0
tE2 =0

A•

85~Z..4

. . - - - - A,

84 1.-.2{i

. - - A,

to-- z-6

. - A,

83

t-- Z'~

iJ-- 2-8

8,~Z-2

A,

A,

82
8,

2-..8_ A2

z-9_

.

8S~Z"

A3

Bs~2-'

A.

SIN 0

ANGLE

FIGURE 1

8,-Z..8

II,
A,

,.

A,

Bal-- 2-9
MM42121

,~

.

A,

2~

A,

eEt =0
£E2'" t

87
MM5232

AEJ

0/2 RADIANS)

tEt CEZ

..
B.

B,

A,

8,
A,
B,
A,
B,
A,

8,
A.

8,
A,
B,
A,

MM423Z/

. - - - - - A,

MM5Z3Z
AEI
tE2: 0

A,

_A,

B,

B,
II,

8,

B,

B,

A,
B,

8,
A,

[El tEZ

ANGLE

B,

B,

A,
B,

..

A.
A,

B,

A,
A,

A,

,.,
,~

,.,

MM4ZJ2/
MM52JZ

-

A,
B,
A,
B,
A,
B,
A,

B,

A,

B,

A,

B,

A,

"
"
"

:::,
CD

c;

:::41-2-5
:::31- z-6
:::2f--2 7
::.,f--z-a

co

T
C,

::'4I-Z-9

::'31-2' ,0
:::2

to- 2-11

:::.1

I-- 2·t~

:"4

f- 2- 13

:"3

f-

CD

I

AEJ
tEl = 0
tE2=1

2'

C,
C,

A,

B,

A,

SINIl
C,

I

eEl" 0
_A,

DM5483!
OM74BJ

B,

£EI tE2

B,
-A,
B,
r - - A,
B,
r-- A,
B,
A,

C,

:::,_2"'6

-4B,

A,

B,r--

A.

B,I--

A,
A,

-

A,

-

A,

z··,o

A,

2- 11

A,

Z-12

A,

B,f----MM423Z!

MMS2;32
AEK
efT" t
tE2= 1

B'r-B,

B,
B,
CEI CEZ

FIGURE 3.

Note: Angles are expressed as binary fractions of a right-angle.

697

2. 14

" f- ",
co

f-- Z·'4

Z·,5
8 , r Z-IS

A,

All
~

B5~2-12

B41-- 2-13
B2 r

A,

FIGURE 2

Iii

t-- 2.10

~~Z'H

83

A,

2~

,~

83 -Z-6

eEl eEZ

>-'

,..,-'

"P

-r

84 _Z-5

8.. _2- 7

,.,

,~

,.,
,.,
,.,

- Z -3

Bs

ANGLE

tEl tEl

r--

B6

l>
m

"

~

w
·ct

..,w.

.

(0 = . w'RADIANS)

AN. LE

,-,-

- 1-..-

ct
W

MM

ct

I-

A,

1-

A,

p)

N

1-

~
~

A,

B,

,,-

.

.

B,

.

A,
A,
A,

.B,

A,

B,.

'.

CEICEl

.......

,,-

N

(W)

N

_

A,

_

A,

~
~

-

A,

B,
A,

..

r'
-

,-

~l

ML ,.. - \ -

A,

B,

~i

-

1-

11l-

,..--"a,
a,

r--

B,

A,

I..,

As

1-

A,

..
A,

A,

.---

-

CEteEZ

-

,,1--CO

c,

B,

OM'' '

A,
B,
A,

',f--r,
l:2

I,

CO

..

-Ae

I-.,1-.,1---

B,

i-A,

'--

~3t--

..

A,
B,
r - - A,

B,

A,

A,

..

l:2r--

B,

r----,,-

..
..

A,

-A,

.

-Ae

,.,

.
,-,.
0

.-

MM52lZ
AEK

B,-

As

B,

A,

B,

A,

I, -

B,

C£IC'U

FIGURE 4

Note: Angles are expressed as binary fractions of a right angle.

"~
l:31-

OM74t3

a,

DM7413

A,

AEK

A,

~

B,

B,

_'lZ

a,

~2

."."
."
."
."
z"

", I- z"
l::1~

CO

;!.

B,

B,

A,

~3

OM74B3

A,
A,

A,

",~

I

CEftEZ

A.

I
C,

C,

B,

..
...,

l:,~ 2·'

CO

B,

..

. - - - - A,

A,

I- 2'

" I- 2'

C.

B,

A2

~I-

,-~

AEJ

~3

r - - - A,
MM5ZlZ

~" I- 2·'

DM14t3

B,

B,

A,

I

c,

A,

-Ae
-

.
B,

B,
B,

~

CO

B,

A,
B,
A,
B,

",I- 2'
", I- 2·'
"~ 2'
1:,1-.2'

B,
A,

MM5232
AEI

OMl483

A,

A,
A,

{

It)

B,

..
B,

-

N

..

II,

A,

SIN X

e.

B,

~

MOS ROMs

NAll0NAL

MM4233/MM5233 4096-bit read only memory
general description
The MM4233/MM5233 4096-bit static read only
memory is a monolithic MOS integrated circuit
utilizing P-chann'el ion-implanted enhancement
mode low threshold technology to achieve bipolar
compatibility. The ROM is organized in a 512
word x B·bit format.

Bi polar compatible

•

Standard suppl ies

•

TRI·STATE outputs

+5.0V,-12V
Bus 0 Rabie outputs
No clocks required

•

Static operation

Four prog,rammable chip selects provide logic con·
trol of the TRI·STATE@ outputs, allowing wire
OR capability of up to 16 ROM's without loading
common data lines or reducing systems access
times. A separate output supply lead V OD is pro·
vided to reduce internal power dissipation in the
output stages.

•

Multiple
ROM control

features

•

Microprogramming

•

•

Control logic

•

Table look·up

Pin for
3514

No external components
required

•

Four programmable
chip select Ii nes

applications
•

pin compatible with the Fairchild

Code conversion

logic and connection diagrams

~

00 LSI!

2J

.

~

~

21

22

~

"

20

~

18

MSB

..

~
11

16

~
15

~

~

"

14

0,

MSB As

..
A,

I"

~

Dual-in-Line Package
lSB

0,
X

DECOQE

I-

r0,

A,

0,

A,

0,

lSB Ao

0,

1

2

J

VGG

C52

CS J

4
00

5
01

6
O2

I

03

lSB
(]1

, ,
04

o!)

10
06

11
07

112
VDD

MSB

MSB
TOPVIEW

Order Number MM4233J
or MM5233J
See Package 11

CS,

es,
os,
CS,

Note: For programming information see AN-100.

6-99

Order Number MM5233N
See Package 18

absolute maximum ratings
Voltage at Any Pin
Power Dissipation at 25°C Ambient
Operating Temperature
MM4233
MM5233
Storage Temperature
. Lead Temperature (Soldering, 10 seconds)

Vss + 0.5V to Vss - 20 V
0.8W
-55°C to + 125° C
O°C to +70°C
-65°C to +150°C
300°C

electrical characteristics
Vss

= +5.0V ±5%, V DD = OV, V GG = -12V ±5%, T A = -55°C to +125°C, unless otherwise noted.
PARAMETER

Output Voltage Levels
Logical Low
Logical High

IL
IL

CONDITIONS

MIN

= 2.4 rnA Sink
= 0.5 rnA Source

2.4

TYP

UNITS

MAX

V
V

0.4

Input Voltage Levels
Logical Low
Logical High

Vss - 4.0

V
V

21

30

mA

21

30

Vss -1.0
TA = 25°C
(Note 1)

Power Supply Current
Iss
IDD

mA

1.0

IGG
I nput Leakage

V ,N

I nput Capacitance
(Note 2)

f

Output CapaCitance
(Note 2)

f

Address Time
TACCEss
Select Time
TSELECT

= Vss -10V

mA

1.0

Il A

= 1 MHz, V ,N = Vss

5.0

pF

= 1 MHz, V DUT = Vss

9.0

pF

TA = 25°C
(Note 3 and Note 4)

1000

ns

TA = 25°C
(Note 3 and Note 4)

800

ns

Note 1: Outputs open.
Note 2: Capacitances are measured periodically only.
Note 3: See timing diagram.

Note 4: 1.5 TTL load, CL

= 20

pF.

switching time waveforms

I

~;5~---n-n---.
... _---_

CHIP SELECT INPUT__ n

ADDRESS INPUT

.....

I

tACCESS--1

____

*~;v---------·
f- -!
t SElECO

.

OUTPUT---------------*1.5V

OUTPUT·---------------*-15V

I"~--·---·

I ,------.

I

6·100

MOS ROMs

~

NATIONAL

MM4240/MM5240 2560-bit static character generator
general description

features

The MM4240/MM5240 2560-bit static character
generator is a P-channel enhancement 'made
monolithic MOS integrated circuit utilizing a low
threshold voltage technology. Six character address and three row address input lines provide
access to 64-8 x 5 characters. Customer-generated
single or multiple package character fonts are easily
programmed by completing a pattern selection
form. A standard 7 x 5 raster scan font is available by
ordering the MM4240AA/MM!l240AA.

•
•
•
•
•

Bipolar compatibility
High speed operation-500 ns max
± 12 volt power suppl ies
Static operation-no clocks required
Multiple ROM logic appl ication-chip enable
output control
• Standard fonts availabl·e-off-the-shelf delivery

applications
•
•
•
•

The MM4240/MM5240 may be used as a
512 x 5-bit read only memory for appl ications
other than character generation.

Character generation
Random logic synthesis
Micro,programming
Table look-up

connection diagram
","

{
"

ADDRESS ,l,
IN'UTS

'.

ou:,~~~

'.

I:

"

"]"

Order Number MM4240J or MM5240J

See Package 11
S UIrj£

Orde' Number MM5240N

I,",un

See Package 18

"

.,

"

I"

Ls,

CHIP
(ff..-llE

typical application

,"
,"

.
lOIlOlltECIAttllAn
CONtROL
~-----.--..r--~--~~--<

rAGE REfRESH

LINE REFRESH

MEMORY

MEMOAY

",

Note: For additional information refer to AN40.
Note: For programming information see AN-l00.

Note:,Chip enable tied to VOO to enable.

6-101

absolute maxil1'lumratings
VGG Supply Voltage
Voo Supply Voltage
Input Voltage
(Vss - 20)V
Storage Temperature
Operating Temperature MM4240
MM5240
Lead Temperature (Soldering, 10 sec)

electrical .characteristics

<

Vss - 30V
Vss - 15V
VIN
(V ss +o.3)V
-65°C to +150°C
_55°C to +125°C
0°Cto+70°C
300°C

<

(Note 1)

CONDITI'ONS

PARAMETER
Output Voltage Levels
MOSto MOS
Logical "1"
Logical "0"

.

MIN

TYP

IMnto GND

MAX

UNITS

Vss - 9.0

V
V

+0.4

V
V

Vss -1.0

MOStoTTL
Logical "1"
Logical "0"

6.8 kn to V GG Plus One
Standard Series 54174 Gate

Output Current Capability
Logical "0"

V OUT

= Vss

+2.5

mA

2.5

- 6.0V

Input Voltage Levels
Vss -8.0

Logical "'"
Logical "0"

Vss - 2.0
T A = 25°C
MaS Load

Power Supply Current
100

40
1

mA
J.l.A

1

J.l.A

5
25

8
40

pF
pF

425

500

ns

25

IGG (Note 2)

= Vss

Input Leakage

VIN

Input Capacitance (Note 5)
VGG Capacitance (Note 5)

f
f

Address Time (Note 3)

See Timing Diagram
TA = 25°C

- 12V

= 1.0 MHz, VIN = OV
= 1.0 MHz, VIN = OV

,

TACCESS
Output AND Connection
(Note 4)

150

MaS Load
TTL Load

4
10

Note 1: Thes.e specifications apply for VSS = +12V ±5%, VGG = -12V ±5%, and TA = -SSoC to
+12SoC (MM42401 TA = O°C to +70°C (MMS2401 unless otherwise specified.
Note 2: The VGG supply may be clocked to reduce device power without aff~cting access time.
Note 3: Address time is measured from the change of data on any input or Chip Enable line to the
output of a TTL gate. (See Timing Diagram). See curves for guaranteed limit over temperature.
Note 4: The address time in the TTL load configuration follows the equation:

TACCESS = The specified limit +
Where N

= Number of AND

IN - 1) (SO) ns

connections.

The number of AND ties in the MOS load configuration can be increased at the expense of MOS "0"

level.
Note 5; Guaranteed by design.

6-102

V
V

performance characteristics
Guaranteed Access Time (TA)
VI Supply Voltage

Typical Access Time (TA) VS
Supply Voltage

1000

1280

",
TAl. +126°C ---,----", ,~ ..

800

]
,:f

600

"

400

~
1 .

1000

--

.

1

I;i! m'c

,

..

0-

T4 = +25°C

200

lOG
100

400

25°C
200
0

0
10

12

11

13

10.8

14

12.0

VOO Power Supply Current vs
Temperature

Power Supply Current vs
Voltage

60

TA -2SoC
50

;

3D

~

1""'-

40

~
T~P:CAL

,

3D

r--.

0

.!!
20

20

10

10

VGG =-12.0V

-

I'-.

TYPICAL

C

.§

Vss = +12.0V

MA~

50

I I

40

13.2

Vss. -VGG (V)

Vss & - VGG (V)

c.§

70'C

r-- •
l"- I'-.

0
13.2

12.0

10.8

-50 -25 0 25 50 15 100 125 150

Vss & -VaG (V)

TEMPElIATURE I"C)

timing diagram/address time

+12V

---,
EITHER

~

DV
,~

I----T""',,,-

+12V

ov
·,V ~

~

1.5V

0

'"", .,v

T

::n..

I

UK

..V

I

_10

...

1,!iV

av

INPUT ~

Eo.:;' IO.F '1
T

~

..V

I
MM42411/MM5240

I

I

h.

r

UK

18'f~

I

':"

-Xv
6-103

I

OUTPUT 11M

ANVDTLnTL

.ATE

~'!i'F

I

"'=

''''''

MM4240AA/MM5240AA character font

i···· .....

• ·i··. ........: .....
•••••••
••:: I :i...:1.1••• ••••••1••• I•••• :

.. ..
00
000000

I I

j···i

ROW

OUTPUTS

ADDRESS

B, B2B3B.8S

00'

010
0»
'00

10'
»0

••• ••
•• ••••
••• •••

02
000010

01
OotlOOI

I

10
001000

001001

2D

Z1

010.000

010001

....

:... 1 1:1··:.. , :.:
•...1

11

03
000011

04
000100

06
000101

06
OD0110

07
000111

I• .::. : I·":
• •• :i
PU··U i
....=
: •••• : :: I:•••:
I I ••

i···.
13
001011

14
001100

15
001101

16
001110

22
010010

25

010011

24
010100

...
.:.

32
011010

011011

12
001010

..

17
001111

•••• ••• •••• ••• .-: : • •• •• •• ••
••• ••
:• • :• ••• •••••••• ••• • •• •• •••
• • •• •• . I.
••:
I·.· I •• • •• •
I
•••• • ••• • ••••• • • •
•
"
"
••• •
••••
••• ••• ••• ••• •••••
•
•• ••• •••
••• •••
• .1•...
•
•
•
•
•
•
•
•
•
•
•• •••• •• •
• •• •• •••••• •
'"
•• I• I• .:• :.
• • •• • : •:
••
••••
•
••• ••• ••••
•••
• • • •••. •• •
•
•
•••
••• ••
•• • • •••••
•••
•••••
••
I•
•• ••
I: :.;7
"
•••• •••• •••:-....: :• I·..• ••••••••
•••• • •• :'.1.
: I···•••
I• •:
: :....
•••••
I .......... I
••••
••
•• •••• ••••• :
••••••• •••••
••
I II
••
••• •....
I
•
••••••• ••••
••
••
••
••
••• ••• •• ••
•

·

31

....

..........'...

J6
011110

44
100100

100101

1110110

47
100111

53
101011

'54
101100

"
101101

56
101110

101111

63
110011

64
110100

65
110101

&6
110110

48
100000

41
100001

42
100010

43
100011

50
101000

101001

52
101010

BO
110000

61
110001

&2
110010

·

'. ..:.. ··i·· :i

....

.. .... .

.

70
111000

71
111001

72

molO

7J
111011

74
111100

FIGURE 4

Note: Negative logic assumed.

6-104

27

010111

35
011101

811081

.1.

010110

J4
011100

3J

30
011000

-

010101

75

7&

111101

111110

011111

.

...

67
110111

77
111111

~

MOS ROMs

NAnoNAL

MM4240ABU/MM5240ABU hollerith character generator
general description
The MM4240ABU/MM5240ABU is a 64 x 8x 5
read-only memory programmed to display a 64character subset of the Hollerith 12-line code,
normally used in punching 80 column cards_ Compression from 12 lines to the six needed to make

up a 64-character set may be accompl ished as
shown in the typical application_ .
For electrical, environmental and mechanical details. refer to the MM4240/MM5240 data sheet.

typical application

SERIAL

DATA
OUT

...

"

.

"

"

LINE

"0

PAGE
STORE

IUEAII401
HOLLERITH

.

,~

.,

I
I

MM424I)ABUI
MM624I1ABU

GIl

.

CODE

"

"

R-'.81<

"
'00

"-,,, ...
11 • '"

o:A4

9 =A3· Ao
8=A3

Nate: Mold present gins chaurl to GND.

Order Number MM4240ABUlJ or MM5240ABU/J
See Package 11 .
Order Number MM5240ABUIN
See Package 18

6-105

CL!JtK

character font

code table·
I:IOLLERITH
INPUTCOOE
(NON-COMPRESSED)

OCTAL
GRAPHIC
SEQUENCE DISPLAY

00

(space}

01

1

2

6

02
03
04
05
06

7

07

4
I;

MM4240ABUIMM5240ABU

.•••• •..••••: I_I.
.-1 1:::*.·..
••.::
II·....•

10

1I.... .....

11

8
8
8
8
8
8

4
5

6
7

12
13
14
15

22

o
o

26
27
28

o

o
o

·30
31
32
33
34
35

9

o
o
o

8

6

36

8

7

37

40
41
. 42

11
11
11
11
11
11
11
11
11
11

".

11
11
11
11·
11
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12

T
U

x
y

46

o

47
50
51
52
53

P

8
8
8
8

4'
5

73

U

001011

40
100000

_

v

OliO 101

000110

14

15

16

11

0011(10

001101

001110

001111

..

21
010001

0011111

....

~

DID 010

010011

010100

010101

010110

010111

••: .. ::.: It

31
011001

JZ
011010

33
0111111

"I.34

3!i

36

31

011100

011101

011110

011111

•••••
: 42.......
:
41
43
100 DOl

100010

100011

II 45 ::...::
46

44
100100

tOO 101

100110

41
IUD 111

..... :.... . :.... .)
..... . ::-• • g....i..
.....
"
• ••••••: •••••••• -:... : .... I·..• •••••
... . . . .. ..... .
::1:: I···i i··: I • : I I" r· i ·1·

: il-..•••
:...: i.....I:

Q

50
101000

00

60

8 2
8 3

12
001010

000 100

•
•• ••• :*::
• •
::
I ::....:p. ::
"
•• •• :-.-:
• • • •::•••••••••
I :.*:
::
:
..... II·.
I I I:r.·,1
.....

57

62
63
64
65
66
67
70
71
72

11
001001

011000

K
L
M
N

6;·

10
001000

I ••: •••••
.* .....

56
7

MIl 011

20

55
8

000 DID

010000

z

54

8

01
000001

m

M

~

"

••
.: .:... ....:"..: I i II i:..:
!• i• •
•
• •• • • •
:*
...n:. in :...
: *:* 1·*·1:*
*:
••••
u
m
n

v
w

44
45

43

~

000000

... ... .. I·· .., ····1 .::.....1L
:.......
...: :···1* :••: I..
: .-: :
., ••1." .:. ::

16
11
20
21
23
24
25

: .......... :

.....

110000

51
101001

•

61

52
101010

• ••••

110001

~

110010

53
lOt 011

: : •••
i"e!
: :

D
E

10
111000

F
G·
H

. (period}

74
75
76
77

6-106

J. ]

11
111 DOl

72
1110HI

101101

57

101111

•. . .1.. ••••••.
~

110011

A
C

56

101110

54

101100

::
"

111011

"

110100

6

110101

H
110110

..... .....
..... .....
e.

14
111100

75
111101

..

16
111110

•••
~

110111

.·1

.:..:
77
111111

~.

MOS ROMs

~

s:
s:
~

N

~

o

NAnONAL

»0:1

N

MM4240ABZ/MM5240ABZ EBCDIC-B character generator

......

s:
s:
U'1

N

general description

~

The MM4240ABZ/MM5240ABZ is a 64 ~ 8 x 5
read only memory .that has been programmed to
display the 64 character graphic subset of EBCDIC·
8, an Extended Binary Coded Decimal Interchange
Code with character assignments and locations con·
forming to the American Standard x 3.26-1970
(see MM5230QX data sheet for full EBCDIC-8
table).

six needed for a 64-character subset is accom·
plished by simply ignoring the two most significant
EBCDIC bits, bit 0 and bit 1.
The octal character address digits are then formed
as shown below.
For electrical, environmental and mechanical details, refer to the MM4240/MM5240 data sheet.

Compression of the eight' bits of EBCDIC-8 to the

character font

.........
:···•••..: :···.1
.1"·11
.....·.:····:····.···.
... ... .•
•••• I•••: i .... : :..:!
... .:.. .. .. .. I
... T L
..•• ..
••••
··...•... .....
.. ........ ........
.. ......
...
..... .. .-i.:••••
:.. a.. :: •.•••
·...:.I····
•• ·n:· .: ::
• •• ••

00

nooooo

: :
: :
• •
I :

01
000001

~

ro

~

000010

000011

0011100

10

001000

001001

t2
001010

13

001011

••• •
:: :

H
000101

lS
001101

:

:•
••

21

U

n

N

25

010001

010010

010011

010100

010101

30
011111lO

31
011001

J2
011010

001111

U

V

018110

010111

••!. .:. -35 ·;6
011011

011100

011101

EBCDIC BITS

16

001110

::.••::

~

010000

..

0011111

•
"
•••••••••
:::: :: ::
14

001100

•••••••••• : ·.1•••• 1 : :

:
:
::~: ••I i··•
:•

m

00
000110

:
•••

:

.1.
11

•

•• •

MSB
MSD

~
234
567
-...;,.......-

"-/

31

011110

011111

: ••••• --:-:- I. !! .:: !:..:
•••

: : I •

•

•

·•••••: ......
••• i ~i ~.:~
.::- ••~:
..
• •••••
:s.. •
.: ....
:.... .••• .
:..: -I •••••.•••••_..
:
:.-1-.
I r··:
=••. : .1. ..... ... .....
....." " "
"
••• ... :: • • •••
••
••...
·I.i·· : • .
• •....
••••
•....
•• • •••• .. : .:
"

100000

LSB
lSD

OCTAL DIGITS

: .....: I.... : i.·.!:··:

••••• •••

2

1

41
100001

42
100010

50

51

52

101000

101001

101010

43
100011

·53

101011

44
100100

•

45
100101

SA·· ••

101100

101101

46
100110

41
100111

56

t7

101110

101111

·~"I

OUTPUTS
8,8 2 83 84 85

000.
•
001..
•
010 • • •
ROW 011.
••
ADDRESS 100 •
•

1)0. •
1111.

•

111

I·" •••:

1101100

110001

••
•

"

11IDCICI

~
110010

I

11
111001

••72

111010

110011

110100

.:~ ••·1
13

111011

:
,'.1.•

"

111100

110101

~
11011(1

~
110"1

••

II

'

"

111101

"

111110

"

111111

Order Number MM4240ABZ/J or MM5240ABZ/J

Order Number MM5240ABZ/N

See Package 11

See Package 18

6-107

o

»0:1

N

.~

MOS ROMs

~

NAll0NAL

MM4240ACA/MM5240ACA EBCDIC character generator
general description
The MM4240ACAlMM5240ACA is a 64 x 8 x 5
read only memory that has been programmed to
display the 64 character graphic subset of EBCDIC;
an Extended Binary Coded Decimal Interchange
code typically used in IBM systems.

The octal character address digits are then formed
as shown below.

Compression of the eight bits of EBCDIC to the
six needed for a 64-character subset is accom-

For electrical·, environmental and mechanical details, refer to the MM4240/MM5240 data sheet.

plished by simply ignoring the two most significant
EBCDIC bits, bit zero and bit one.

character font

••••• I···:
:•••• "1"-:
I···· i···· :....
•••••
• • ••• ••• •
!-II..•: :.... L..: i....
I :..:1
os
I

'"DO
000000

01
000001

D2
000010

•••

•

•••
:• .
•..
•
1···1
:
: : ••• •
"

1D

11

001060

001001

03
000011

- ..

12
001010

04
000100

13
DOl 011

I::
...
...".
•••••

07

0011111

•• •• • :••
•• •• •••••
• •• •• •••
"

••

••
••
••••••
::
:

06
OOD110

.· ·
.
000101

14
001100

15
(}!JIIOt

1101110

17

001111

...... .

•
• ••••••••••••
•• •
••••
•• •

::::·.11 II••••

•••••
: n •• : ....
:
21
n

~

I:

25

11•••:-:
~

V

010110

Otll111

-

... ._.
e.I._ ••• ••
: :: : : ...::•..
..
:
I.:.: 1"::. • _a:. ::::: ..: :! ····1
"
....
.....
•• ..
•• .
•
..
.
.
.
•• • ••
..... ••• •••• I• :...!..••••I::..
i
...
1
:
•••
:
•
•••
...
......
...:
:...: .::: .J..
.....
•
••
• ..
.• ••
.: ....... ..:.. :1 .•••
•
ioo ·1:r~:~ 1015~1D
.: :....
...........
•••• -: ...:....: ..
. .:
:• :• : .... ... ":..:. : •.... ..,
•••• .:. :.... ..... : .......... :
20

010

~OD

010001

Dll)OHI

30

31

32

011000

011001

011010

40

100000

41
IQOODI

42
100010

010011

0101UO

34

35

36

31

011011

011100

011101

011110

011111

4J
100011

5(1

51

52

53

101000

101 DOt

10.1010

101011

"

110010

"

62

63

44
100100

010101

45
100101

S
1OI

110001

110011

64

1101DD

65

110101

••••• •••••: I: .i.!..•::
~
• •
:: :-: ...
•••
10

11

12

13

14

111000

111001

111010

111011

111100

41
10011'

57

·............. ........... .. "
110000

46
1001111

111101

66

67

110110

110111

EBCDIC BITS

~

-

MSB 234
MSO

567 LSB

'"1

2

LSD

'-../

OCTAL DIGITS

OUTPUTS
8 1 82 B3 R4 B5

000.
•
001..
•
010 • • •
ROW 011.
••
ADDRESS 100.
•
101.
•

110.
111

.

••••• II
•••••
16

11

111110

111111

Order Number MM4240ACA/J or MM5240ACA/J

Order Number MM5240ACAiN

See Package 11

See Package 18

6-108

~

MOS ROMs

NAnONAL

MM42411MM5241 3072-bit static read-only memory
general description

features

The MM4241/MM5241 3072-bit static read-only
memory is a P-channe,1 enhancement mode monolithic MaS integrated circuit utilizing a low threshold.voltage technology to achieve bipolar compatibility. TRI-STATETM outputs provide wire ORed
capability without loading common data lines or
reducing system access times. The ROM is organized in a 64 x 6 word by 8-bit memory organization. Programmable Chip Enables (CE, and CE 2 )
provide logic control of multiple packages without
external logic. A separate output supply lead is
provided to reduce internal power dissipation in
the output stages.

• Bipolar compatibility

• Static operation

No clocks requ ired

• Multiple ROM control

Two programmable
Chip Enable lines

applications
• Character generator
• Random logic synthesis
• 'Microprogramming
• Table look-up

Dual-In-Line Package

r---.....Jl-_~~-OB,

A,
A,

LSI!

A,

Ao

I--I:tra g,

A.

....
1--t:'=H>..
t--1~:r-<>g,

M~MORV

V

DfCflDE

ARRAY

.

A~

CE,
CE,
Nt

..
...
'" .

TRI-STATE outputs

• Bus aRable output

LSB
Az

+5V, -12V

• Standard supplies

logic and connection diagrams
AI

No external
components required

Ao
L.

Y.

I--I:~f-og,

,
,

.
,
,•
"
"

Y"

" ..v"
" g,
"
"
" g,
" .,g,
"
"
""
"
" c,

.
~

L,

11

TOI'VI~W

c,

"',o-,-------i
CE,o-------i

Order Number MM4241J
orMM5241J
See Package 11
Order NumberMM5241N
See Package 18

CHIP

[IiAIlf
ARRAY

typical applications
TT LIMOS Interface
v.

FIGURE 1. Power Saver for
Small Memory Arrays

ll

-Y"--,

I

I.

I
I

Yo.
AIMYTTLIOTl

I
I
I
I

___ -'

FIGURE 2. Power Saver for
Large Memory Arrays

'1r;U-~--'
,~'

I
I
I
I

-=- I
I
I
I

----'

DEVICE

",
,.. -----'

ASSUME IIVu :IMIN" 11-3v iI
VI;C -VLt MIN = R (1.& II'A) (N;lwllereN • ltDf 5 II 1 font,

N= 8fltr61Cltont.

NO,te: Both chip enables may be programmed to provide any of four combinations. Example: If CE1 = 1· and CE2 = 1 outputs
(Negative Logic) would be enabl~ only when device pins 2 and 3 are negative (Logic "1"). The outputs will be in the third state
when disabled. La, L1 and L2 (device pins 11,13 and 14) are in positive logic (1 = most positive voltage levels = Vs - 2V; a =
most negative voltage level = VSS - 4V).
,
Note: For programming information see AN:-100.

6-109

absolute maximum ratings
VGG Supply Voltage
V LL Supply Voltage
Input Voltage
Storage Temperature Range
Operating Temperature Range

Vss - 20V
Vss - 20V
(V ss - 20) V < V IN < (V ss + .03)V
_65°C to +150°C
MM4241
-55°C to +125°C
_25°C to +70°C
MM5241
300°C
Lead Temperature (Soldering, 10 sec)

electrical characteristics

NEGATIVE LOGIC (Note 5)

T A within operating temperature range, Vss = +5.0V ±5%, V GG = VDD = -12V ±5%, unless otherwise noted.
PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Output Voltage Levels
Logical "1"
Logical "0"

.4

IL'" 1.6 mA sink
IL = 100 MA source

2.4

Input Voltage Levels
Logical "l/t

Vss - 4.0

V
V

37

mA
mA

Vss-2.0

Logical "0"

V
V

Power Supply Current
Iss (Note 4)
Iss (Note 4)

Vss= 5, VGG =-12, VLL -12, TA =25°C
Vss"" 5, V GG ;= -12. V LL = -3. T A = 125°C

Input Leakage

VIN '" V ss -l0V

Input Capacitance (Note 1)

f

20
1

= 1.0MHz. Y'N = OV

Output Capacitance (Note 1)

f = 1.0 MHz, V IN

Address Time (Note 2)

TA = 25°C, Vss "" 5
'VGG = V LL = -12V

T ACCe;SS

23

=:

OV

150

~A

15

pF

4

10

pF

700

900

ns

5

20

Output AND Connections (Note 3)

Note 1: Address time is measured from the change of data on any input or Chip Enable line to the output of a TTL gate.
(See Timing DiagramJ See curves for guaranteed limit over temperature.
Note 2: Capacitances are measured periodically onlv.
Note 3':. The address time follows the following equation: T ACCESS = the specified limit + (N ~ 1) x 25 ns where N = Number
of AND connections.
.
Note 4: Outputs open.
Note 5: All addresses and outputs are in negative true logic with the exception of LO, L1, and L2 which are in positive logic.

6110

performance characteristics
Typical Access Time vs
Supply Voltage

Guaranteed Access Time

V5

Supply Voltage

1400

1600

1100

1400

VLL - VGG

1000

g 800

1200

125'C

125'C

TA"'10"C

TA,: 10~C

1000

]

15"C

25'C

< 800
"-

<
.... 600

600
400

400

200

100
16.2

11.0

16.2

11.8

Vss+ IVaG I IV)

Power Supply Current
vs Temperature
80

Power Supply Current

vs Voltage
80

Vss - 5.DV

10

VGG-V LL =

TA, - 25"C
10

12V

60

60

;< 50

;< 50

.§ 40

.g

MAXIMUM

Jl

I1.B

11.0
Vss + I VGGI (V)

Jl

_lVi' I ~G'i
MAXIMUM

40

3D

30

TYPICAL

TVPICAl
10

20

10

10

-50 -25

0

25

50

15

16.2

100 125

TEMPERATURE rCI

timing diagram/address time

E,.

EOUT

6-111

11.0

11.8

~

MOS ROMs

Advance Information

NAll0NAL

MM4242/MM5242 8192-bit read only memory
general description

features

The MM4242/MM5242 1024 x 8-bit read only memory
is a monolithic MOS integrated circuit utilizing N-channel
silicon-gate enhancement mode arid ion-implanted
depletion mode devices. Use of this technology allows
operation from a single power supply and compatibility
with TTL and DTL circuits. Programming of the memory
contents and chip selects is accomplished by changing
one mask during the device fabrication.

•
•
•
•
•
•
•

Organ ized as 1024 bytes of 8 bits
Static operation
Four programmable chip select inputs
Maximum access time-500 ns
TTL compatible
TRI-STATE outputs
Single 5V power supply

block and connection diagrams

A4
A5
A6
A7

MEMORY
MATRIX
1024 X 8

X
DECODE

OUTPUT
DRIVER

OUTPUTS

A8
A9

t t

Vee

GND
CS

Dual·ln-Line Package
AD
L4

Al

A2
23

A3
22

A4

21

A5

20

19

A6

A7

A8
17

18

A9

16

CS3
15

13

14

~

r--

1

CS2

2

3

4

5

6

7

8

9

GND

10
CS 0

OUTPUTS
TOPVIEW

Q,de, Numbs, MM4242D

0'

MM5242D

See Package 6
Q,de, Numbe, MM5242N

$ee Package 18

"1'2
CS 1

Vee

~

MOS ROMs

Advance Information

NATlONAL

MM4246/MM5246 16,384-bit read only memory
general description
The MM4246/MM5246 is a static I6,384-bit read only
memory organized in a 2048 word by 8-bit format. It is
fabricated using N-channel enhancement and depletion
mode silicon gate technology which provides complete
DTL/TTL compatibility and single power supply operation.

• Static operation
• TRI-STATE outputs for bus interface
• Programmable chip selects
• 2048 word by 8-bit organization

,Three chip select inputs controlling the TR I-STATE®
outputs permit easy memory expansion. Programming of
the memory and chip select active levels is accomplished
by changing one mask during fabrication.

•

Maximum access time-500 ns

applications
• Microprogramming

features
• Single 5.0V supply

• Control logic

• All inputs and outputs directly DTL/TTL compatible

• Table lookup

block and connection diagrams

Dual-I n-line Package
AD

Al

A2

A3

AD

124

Al

A2
23

A3
22

A4

21

A5

20

A6

19

A1
18

AS

17

16

A9
15

Alo

CS2

14

13

A4
A5
A6
A1

MEMORY
MATRIX
2048 X 8

A8

'-

r-

A9
Alo

CS 0

1

cs 1

CS2

DO Dl .02 03 04 05 06 D1

GNO

2

DO

3
01

4
02

5
03

1

6
04

05

9

8
06

01

10

TOP VIEW

Order Number MM42460 or MM5246D

See Package 6
Order Number MM5246N

See Package 18

6,113

11 ./12

CS 0 CS 1

Vee

(V)

o
o
o

~
CJ)

~

MOS ROMs

NAnONAL

SK0003 sine/cosine look-up table kit
general description
THE COSINE FUNCTION

The SK0003 Sine/Cosine Look-Up Table Kit consists of four MaS ROMs: three MM421 0/MM521 O's
and one MM4220/MM5220-1024 bit static read
only memories. They are P-channel enhancement
mode monolithic MaS integrated circuits utilizing
a low threshold technology.

To generate the cosine function cose = sin(e 90°), the input must be complemented and a
logical "1" added. Figure 2A is a logic diagram
of the circuitry used to provide the cosine function, as well as providing both sine and cosine
functions in the same system. 11-bit resolution
and 12-bit accuracy ±1-5/8-bits is ach ieved in this
configuration.

THE SINE FUNCTION
The SK0003 implements the equation sine = sin
M cos L + cos M si n L. Cos L was assu med to be
1 in the equation. However, it is a variable between
1 and 0.99998 and is a function of round off error.
Worst case error is 1-518 bits in LSB at address
1415 (62.25°). The error increases from zero to
.002% every 8 bits, therefore, the MM42201
MM5220 provides the error correction factor
cos(M - 2.81°)sin L in the equation sine = sinM+
cos(M ~ 2.81°)sin L. The circuitry to perform this
function is shown in Figure 1. Additional information is available in MOS Brief 10.,

A reduction in logic can -be achieved as shown in
Figure 28 if a loss in resolution of 1/2-bit in an
ll-bit input or 1/4-bit in a lO-bit input is acceptable.

ELECTRICAL CHARACTERISTICS
Refer to the appropriate data sheet for each
device shown in the figures. The devices noted are:
MM4210/MM5210, MM4220/MM5220, DM54831
DM7483, DM78121DM8812 and DM5486/DM7486.

logic diagram

..

.,

"

"
"
"
"
"

0,

"
~

".

"

n <,

CARRV

IlUTPUT

,.

"

~}

"
"
"

<,

Order Number SKOOO3C
or

Order Number SK0003M

CARRVINPUT

CARRY

DUTPUT

"
"

"
2,,0

,,,
,"
CAIII\VINPUT

<>-D-}
{
=?~{

II-ITO EACHOUTPUTI

FIGURE 1. SK0003 Logic Diagr.am (Kit Includes ROMs Only). ThisCircuit Provides 11·8it Resolution and 12-8it
Accuracy in a

e to Sin eConverter.

6-1.1 4

en
o
o
o
w

"

logic diagram

EX·OR GATES

DM1U6c

,-,

,<

,-,
,.

."""
ROMS

"
,-

AND

OUTPUT
ADDER!

,-,

..
2. 10

2""

SINE/COSINE
ENABLE

SIGNAL

----+--1

,"

0-....

"

A,
CARRV

"
FIGURE 2A. SinelCosine Conversion Provides 1'·Bit Resolution. 12-Bit ±1-5/B Bit Accuracy.

SKOIlO)

ROMS
AND
OUTPUT
ADDERS

l"J

SINE/
COSINE

"
"
"
"
"
"
"
"
"
,,,
,n
Z ..

"O"'S'ne

...... (: ........

SIGNAl

FIGURE 2B. Sine/Cosine Conversion with Cosine Approximated. (Cosine Conversion has 10-Bits Input Resolution
and 12-Bit ±1-5/B-Bit Accuracy.)

6-115 .•

~

Bipolar ROMs

NATIONAL.'

OM5488/0M7488 256-bit read only memories
general description.
This memary is fully campatible far use with mast TTL
.or DTL circuits. Input clamping diades are providedta
minimize transmission-line effects and simplify system
design. Input buffers lower the fan·in requirement to
.only one normalized Series 54/74 laad for all inputs
including enable (G). The apen-collector outputs are
capable .of sinking 12 mA .of current and may be
wire·AND connected to increase the number .of words
available. An external pull·up resistor from each .output
to the supply line (Vee) is required ta define the
high·level output voltage. Where multiple· DM5488/
DM7488 devices are used in a memory system, the
enable input allaws easy decoding .of additional address
bits. Access propagatian delay time is typically 20 ns
and power dissipatian is typically 240 mW.

These custom-programmed, 256-bit, read only memories
are organized as 32 words of R bits each. Each
monalithic; high-speed, transistar·transistar lagic (TTL),
32·ward memary array is addressed in straight 5·bit
binary with full an-chip decading. An .overriding memaryenable input is provided which, when taken high, will
inhibit the 32 address gates and Cause all 8 .outputs ta
remain high (.off). Data, as specified by the custamer,
are permanently programmed inta the manalithic structure far the 256-bit lacatians. This arganizatian is
expandable ta n·wards ta N·bit length.
The address .of an 8-bit ward is accamplished through
the buffered, binary select inputs which are decoded by
the 32 five·input address gates. When the memary·enable
input is high, all 32 gate .outputs are law, turning .off
the 8 .output buffers.

features

Data are pragrammed into the memary at the emitters
.of 32 eight-emitter transistars. The pragramming pracess
involves cannecting .or nat cannecting each .of the 256
emitters. If an emitter is cannected, a law·level valtage
is read aut .of that bit lacatian when its decading gate
. is addressed. If the emitter is nat connected, a high·level
valtage is read when addressed. Those decading-gate
output emitters which are used are cannected ta their
respective bit lines ta drive the 8 .output buffers. Since
.only .one decading gate is addressed at a time, .only one
.of the 32 transistars can supply currerit to the .output
buffers at a time.

• Applicatians in camputer subroutines
•

Useful in display systems and readouts

•

Memory organized as 32 wards of 8-bits each

•

Input clamping diodes simplify system design

• Open·collector outputs permit wire-AND capability
• Typical access time:
• Typical pawer dissipatian:
•

Fully campatible with most TTL and DTL circuits

connection diagram
Dual·ln·Line Package

r·1.

v

BINARY SELECT

ENABLE
G

OUTPUT

Y8
14

15

13

12

11

10

-

,VI

V2

Y3

Y5

Y4

YB

Y1

OUTPUTS

TOP VIEW

Order Number DM5488J or DM7488J

·See Package 10
Order Number DM7488N

See Package 15

7·1

20 ns
240 mW

co
co

~

~
C

absolute maximum ratings

......

Supply Voltage, Vee (Note 3)
Input Voltage

..;:t

Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)

CO
CO

operating conditions

(Note 1)

7V
5.5V
--65"e to +150"e
300"e

Supply Voltage (Veel
OM5488
OM 7488

MAX

UNITS

4.5
4.75

5.5
5.25

V
V

Temperature (TA)

t.n

OM5488
OM7488

~
C

electrical characteristics

MIN

-55

0

"e
"e

+125
+70

(Note 1)

PARAMETER

CONDITIONS

High Level Input Voltage (V'H)

MIN

TYP

MAX

UNITS

2

V

Low Level Input Voltage (V,Ll

0.8

V

Input Clamp Voltage (V,)

Vce = Min,

1,=-12mA

-1.5

V

High Level Output Current (l oH )

Vce = Min, V'H = 2V,
V'L = 0.8V, V OH = 5.5V

40

I1A

12

mA

0.4

V

Low Level Output Current (l oL )
Low Level Output Voltage (VOL)
(Note 2)

Vee = Min, V'H = 2V,
V'L = 0.8V, IOL=12mA

Input Current at Maximum Input
Voltage (I,)

Vee = Max, V, = 5.5V

0.2

1

mA

High Level Input Current (lIH)

Vee = Max, V, = 2.4V

Low Level Input Current (I'L)

Vce = Max, V,=O.4V

Supply Current, all Outputs High
(l ecH ) (Note 2)

Vcc = Max

37

65

mA

Supply Current, all Outputs Low

Vec = Max

48

80

mA

25

I1A

-1

mA

(lCCL) (Notes 2 and 4)

switching characteristics

V ec =5V,T A =25°C

FROM INPUT

TO OUTPUT

Propagation Delay Time, Low to
High Level Output (t PLH )

Enable

Any

Propagation Delay Time, High to
Low Level Output (tPH L)

Enable

Any

Propagation Delay Time, Low to
High Level Output (t pLH )

Select

Any

Propagation Delay Time, High to
Low Level Output (t PHL )

Select

Any

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

19

35

ns

18

35

ns

21

35

ns

17

35

ns

C L =30pF,
RLl ~ 400Q,
RL2 = 600Q

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operatec at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the -55°C to +125°C temperature range for DM5488 and across the O°C to +70°C
range for the OM7488. All typicals are given for Vee ~ 5V and TA

= +25"e.

Note 3: All voltage values are with respect to network ground terminal.
Note 4: All 32 words are addressed separately to ensure that the supply current does not exceed the stated maximum. The typical value shown is
for the worst·case condition of all eight outputs driven low at one time.

7·2

c

3:

ordering instructions

U1

Programming instructions for the DM5488 or DM7488
are solicited in the form of a sequenced deck of 32
standard 80·column data cards providing the information
requested under "data card format," accompanied by a
properly sequenced listing of these cards, and the
supplementary ordering data. Upon receipt of these
items, a computer run wi II be made from the deck of
cards which will produce a complete function table of
the requested part. This function table, showing output
conditions for each of the 32 words, will be forwarded
to the purchaser as verification of the input data as
interpreted by the computer-automated design (CAD)
program_ This single run also generates mask and test
program data'; therefore, verification of the function
table should be completed promptly.

50-51

Each card in the data deck prepared by the purchaser
identifies the word specified and describes the levels at
the eight outputs for that word. All addresses must have
all outputs defined and columns designated as "blank"
must not be punched. Cards should be punched according
to the data card format shown.

Punch a right-justified integer representing the
current calendar day of the month.

52

Blank

53-55

Punch an alphabetic abbreviation representing
the current month.

56

Blank

57-58

Punch the last two digits of the current year

59

Blank

60-61

Punch "DM"

62-65

Punch the National Semiconductor part number
5488 or 7488.

66-70

Blank

WORD
0
1
2
3

Submit the following information with the data cards:
a. Customer's name and address
b. Customer's purchase order num ber
c. Customer's drawing number
DATA CARD FORMAT
Column
1-2
Punch a right-justified integer representing the
positive-logic binary input address (00-31) for
the word described on the card.

D

C

B

L

L

L

L

L

L

L

L

L

H

L

L

L

H

L

L

L

L

H

H

A

4

L

L

H

L

L

5

L

L

H

L

H

6

L

L

H

H

L

7

L

L

H

H

H

8
9

L

H

L

L

L

L

H

L

L

H

10

L

H

L

H

L

11

L

H

L

H

H

12
13
14
15

L

H

H

L

L

L

H

H

L

H

L

H

H

H

L

L

H

H

H

H

H

L

L

L

L

H

L

L

L

H

H

L

L

H

L

H

L

L

H

H

Blank

5

6-9

Punch "H," "L," or "X" for output Y8_
H : h i.gh-voltage-Ievel output, L : low-voltagelevel output, X : output irrelevant.
Blank

10

Punch "H," "L," or "X" for output Y7.

11-14

Blank

L

H

L

L

Punch "H," "L," or "X" for output Y6.

20
21

H

15

H

L

H

L

H

16-19

Blank

22

H

L

H

H

L

23

H

L

H

H

H

24
25
26
27

H

H

L

L

L

H

H

L

L

H

H

H

L

H

L

H

H

L

H

H

28
29
30
31

H

H

H

L

L

H

H

H

L

H

H

H

H

H

L

H

H

H

H

H

Punch "H," "L,"
Blank

or

16
17
18
19

"X" for output Y5.

25

Punch "H," "L," or "X" for output Y4.

26-29

Blank

30

Punch "H," "L," or "X" for ouput Y3.

31-34

Blank

35

Punch "H," "L," or "X" for output Y2,

36-39

Blank

40

Punch "H," "L," or "X" for output Y1.

41-49

Blank

~

00
00

INPUTS

E

3-4

20

c
3:

truth table

SUPPLEMENTARY ORDERING DATA

21-24

it00

........

H
L

7-3

= High level
=

Low level

DI

co

co
it

functional block diagram

~
C

......

co

~

Ln
~

C

c-

o

=1

-=

0:

10

Lc

2

A

J

~

,

~

6

i=F,l
~

,

i

11

~ •

~
10

:=:::
11
:=:::
12
:::::::
13

,.
BINARY
SELECT

12

~

C

,.

15

C

11

~
19

Er;nt
~
~
~

ii

13

Lc

~
~
~

0

21
2B

14

15

~

E

2.

E

30

~

il

\YY.Y.Y.
VB

Y7

V&

V5

Y4

OUTPUTS

7·4

3
Y3

2
Y2

1
V1

~

Bipolar ROMs

NATlONAL

OM54187/0M74187 (SN54187/SN74187)
1024-bit read only memory
general description
The DM54187/DM74187 is a custom-programmed
read-only memory organized as256 four-bit words_
Selection of the proper word is accomplished
through the eight select inputs. Two overriding
memory enable inputs are provided; and when one
is taken to the logical "1" state, it will cause all
four outputs to go to the logical "1" state.

• 20 ns typica I delay from enable to output
• Open collector outputs for expansion

applications
•

Microprogramming

•

Code conversions

features

•

Look-up tables

• 36 ns typical delay from address to output

•

Use for any memory where content is fixed

logic diagram

r'
I'
I'
I

BINARY

I

E

Sf LEtT)

I, '"
I
it

l:

(1}

~Ii)

J

~I",SI----------~~__, -__

ENABLE
MEMORY

t" ""~'''C==::r::>------r+---------t1--------"1"+-------,
Ga

0;(141

Pin (UI "Vee l'in(8)=GND

connection diagram
Dual-In-Line Package

Order Number DM54187 J
or DM74187J

See Package 10
Order Number DM74187N
See Package 15

7-5

.....
co

...
~
.....

absolute maximum ratings

o

Supply Voltage
Input Voltage
Output Voltage
Operating Temperature Range
DM54187
DM74187
Storage Temperature Range
Lead Temperature (Soldering, 10 see)

:!:

.....
.....

...

CO
~

an

:!:

o

(Note 1)
7V
5.5V
5.5V
- 55°C to +125°C
O°C to +70°C
_65°C to +150°C
300°C

electrical characteristics

(Note 2)

PARAMETER

CONDITIONS

MIN·

TYP

MAX

UNITS

Logical "1" Input Voltage

DM54187 Vee ~ 4.5V
DM74187 Vee~ 4.75V

Logical "0" Input Voltage

DM54187 Vee
DM74187 Vee

Logical "1" Output Cur,ent

DM54187 Vee~ 5.5V
DM74187 Vee ~ 5.25V

Logical "0" Output Voltage

DM54187 Vee
DM74187 Vee

Logical "I" Input Current

DM54187 Vee ~ 5.5V
DM74187 Vee =.5.25V

VIN

~

2.4V

40

pA

DM54187 Vee ~ 5.5V
DM74187 Vee = 5.25V

VIN

~

5.5V

1

mA

DM54187
DM74187

Vee~ 5.5V
Vee = 5.25V

V IN

~

0.4V

-1.0

mA

Supply Current

DM54187
DM74187

Vee = 5.5V
Vee - 5.25V

All Inputs at GND.

Input Clamp Voltage

DM54187 Vee
DM74187 Vee

Logical "0" I nput Current

~

~

~
~

~

~

2.0

V

4.5V
4.75V

4.5V
4.75V

4.5V
4.75V

0.8
Vo
10

~

~

5.5V

40

16 mA

0.4

75

110
-1.5

liN = -12 mA

V
pA
V

mA
V

Propagation Delay to a Logical "0" from Vee = 5.0V
TA ~ 25°C
Enable to Output, tpdQ

CL

30 pF

20

30

ns

Propagation Delay to a Logical "0" from Vee ~ 5.0V
TA ~ 25°C
Address to Output, tpdQ

CL = 30 pF

37

60

ns

Propagation Delay to a Logical" 1" from Vee = 5.0V
TA ~ 25°C
Enable to Output, tpd 1

C L = 30 pF

20

30

ns

Propagation Delay to a Logical" 1" from Vee = 5.0V
TA = 25°C·
Address to Output, tpd 1

C L = 30 pF

36

60

ns

~

Note 1; "Absolute Maximum' Ratings" are those values beyond which the safety of the deVice
cannot be guaranteed. Except for "Operating Temperature Range" they are not me'ant to imply

that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the -5SoC to +12SoC temperature
range for the DM54181 and across the aOc to 100e range for the DM74187. All typicalsare given

for Vee ~ 5.0V and T A ~ 25'e.

76

c

s::C7I

ordering instructions

~
....
00

.....

.......
Programming instructions for the DM54187 or
DM74187 are solicited in the form of a sequenced
deck of 32 standard 80-col'umn data cards providing the information requested under data card
format, accompanied by a properly sequenced
listing of these cards, and the supplementary
ordering data_ Upon receipt of these items, a computer run wi II be made from the deck of cards
which will produce a complete truth table of the
requested part_ This truth table, showing output
conditions for each of the 256 words, will be
forwarded to the purchaser as verification of the
input data as interpreted by the computer-automated design (CAD) program. This single run also
generates mask and test· program data;· therefore,
verification of the truth table should be completed
promptly.

10·13

14

15-18
19
20-23
24
25-28
29

Each card in the data deck prepared by the purchaser identifies the eight words specified and
describes the conditions at the four outputs for
each of the eight words. All addresses must have
all outputs defined and columns designated as
"blank" must not be punched. Cards should be
punched according to the data card format shown.

30·33
34
35-38
39

supplementary ordering data

40-43

Submit the following information with the data
cards:

44
45-48

a) Customer's name and address
b) Customer's purchase order number
c) Customer's drawing number.

49
50-51

data card format

52
53-55

Column
1- 3

4
5- 7

8- 9

punch a right·justified integer representing
the binary input address (000·248) for
the first set of outputs described on the
card.

56
57·58

Punch a "-" (Minus sign)

59

Punch "H", "L", or "X" for bits four,
three, two, and one (outputs Y4, Y3,Y2,
and Y 1 in that order) for the first set of
outputs specified on the card. H = highlevel output, L = low-level output, X =
output irrelevant.
Blank
Punch "H", "L", Or "X" for the second
set of outputs.
Blank
Punch "H", "L", or "X" for the third set
of outputs.
Blank
Punch "H", "L",or"X" for the fourth set
of outputs.
Blank
Punch "H", "L", or "X" for the fifth set
of outputs.
Blank
Punch "H", "L", or "X" for the sixth set
of outputs.
Blank
Punch "H", "L", or "X" for the seventh
.set of outputs.
Blank
Punch "H", "L", or "X" for the eighth
set of outputs.
Blank
Punch a right-justified integer representing
the current calendar day of the month.
Blank
Punch an alphabetic abbreviation representi ng th-e current month.
Blank
Punch the last two digits of the current
year.
Blank

Punch a right-justified integer representing
the binary input address (007-255) for
the last set of outputs described on the
card.

60-61

Punch "DM"

62-66

Punch the National Semiconductor part
number 541870r 74187.

Blank

67-70

Blank

7-7

C

s::
.....
~

....

00

.....

~

Bipolar ROMs

NAnONAL

OM 54 L187AIDM74L187A(SN54L187A/SN74L187A)
low power 1024-bit read only memory
general description
The DM54L187A/DM74L187A is a customprogrammed Read Only Memory organized as
256 4-bit words. Selection of the proper word is
accomplished through the eight select inputs.

read either the normal memory contents or go to
the logical "1" state.

The "A" suffix is used to denote that full "tenthpower" technology has been employed in building
this ROM.

•
•
•
•
•
•

features

Two overriding memory enable inputs are provided
which when' mask·programmed in one of the three
, options described will cause all four outputs to

Full tenth·power technology
Pin compatible with SN54187/SN74187
90 mW
Typical power dissipation
85 ns
Typical access time
Custom·programmed memory enable inputs
Open·collector o,utputs

logic diagram

A,

..
A,

MEMORY
ENABLE

fME'

~E2

m
(5)

(5)
(13)

(14)

Y,

Y,

Y,
OUTPUTS

ME,~_

ME,~

ME2~

ME2~
OPTION 3

OPTION 2

7·8

Y,

absolute maximum ratings
Supply Voltage
Input Voltage

Output Voltage
Storage Temperature Range
~5°e
Lead Temperature (Soldering, 10 seconds)

electrical characteristics

operating conditions

(Note 1)

Supply Voltage IVee)
DM54L 187
DM74L 187

7.0V
5.5V
5.5V
to +150o e
300 e

Temperature (TA)
DM54L 187
DM74L187

0

MIN

MAX

UNITS

4.5
4.75

5.5
5.25

V

-55
0

+125
+70

°e
°e

TVP

MAX

UNITS

V

(Note 2)
CONDITIONS

PARAMETER
Logical "I" Input Voltage

Vee = Min

Logical "0" Input Voltage

Vee

Logical "'" Output Current

MIN

V

2.0

= Min

0.7

V

Vee ~ Max, Va ~ 5.5V
IMemory Enable ~ Logical 1)

50

IlA

Vee ~ Min, 10 ~ 2.0 mA
Vee = Min, 10 = 3.2 mA

0.3
0.4

Logical, "'" Input Current

Vee = Max, Y'N ~ 2.4V
Vee = Max, Y'N = 5.5V

10
100

Logical "0" Output Voltage
DM541187
DM741181

Logical "0" Input Current

Vee = Max, Y'N = 0.3V

Supply Current lEach Device)

Vee = Max, All Inputs at GND

Input Clamp Voltage

Vee = Min, 111""

Propagation Delay to a Logical "0"
From Enable to Output (tpdO)

V
V
IlA
IlA

-120

-180

IlA

18

25

mA

= -12 rnA

-1.5

V

Vee'~

5.0V, CL = 15 pF,
TA =25°C i RL = 2.0 H1

46

70

ns

Propagation Delay to a Logical "0"

Vee

98

ns

TA ~

5:0V, CL "15 pF,
25°C, RL = 2.0 kU

65

From Address to Output (tpdo)

~

Vee =5.0V,C L ~ 15pF,
= 25°C, RL ~ 2.0 kU

85

130

ns

From Enable to Output Itpd,)

TA

Propagation Delay to a Logical "1"

Vee ~.5.0V, CL = 15 pF,
T A = 2So.c, RL ~ 2.0 kU

120

180

ns

Propagation Delay to a Logical "1"

J

From Address to Output Itpd,)

Note 1: "Absolute Maximum Ratings" are those values beyond lNhich the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits.
Note 2: Unless otherwise specified minImax limits apply across the -55"C to +125°C temperature range'for the OM54L 187
and across the ooe to +70°C range for t~e DM74L 187. All tv,picals are given for Vec "" S.OV and T A = 2S"C.

ordering instructions
Programming instructions for the DM54L 187 or
DM74L 187 are so)icitedin the form of a sequenced
deck of 32 standard 80-column data cards providing the information requested under data card
format, accompanied by a properly sequenced
listing of these cards, and the supplementary
ordering data. Upon receipt of these items, a computer run will be made from the deck of cards
which will produce a complete truth table of the
requested part. This truth table, showing output
conditions for each. of the 256 words, will be
forwarded to the purchaser as verification of the
input data as interpreted by the computer-automated design (CAD) program. This single run also
generates mask and test program data; therefore,
verification of the truth table should be completed
promptly.

Each card in the data deck prepared by the pur·
chaser identifies the eight words specified and
describes the conditions at the four outputs for
each of the eight words. All addresses must have
all outputs defined and columns designated as
"blank" must not be punched. Cprds should be
punched accord ing to the data card format shown.

supplementary ordering data
Submit the following information with the data
cards:
a) Customer's name and address
b) Customer's purchase order number
c) Customer's drawing number.

7-9

data card format
Coiumn
1- 3

4
5- 7

30-33
Punch a right-justified integer representing
the binary input address (000-248) for
the first set of outputs described on the
card.

10-13

14
15-18
19
20-23
24
25-28
29

Blank

34
35-38

Punch a "-" (Minus sign)
39

Punch a right-justified integer representing
the binary input address (007-255) for
the last set of outputs described on the
card.

8, 9

Punch "H", "L", or "X': for the fifth set
of outputs.

40-43
44

Blank

45-48

Punch "H", "L", or "X" for bits four,
three, two, arid one (outputs Y 4, Y3, Y2,
and Y1 in that order) for the first set of
outputs specified on the card. H = highlevel output, L = low-level output, X =
output irrelevant.

50-51

Blank

53·55

49

52

Punch "H", "L", or "X" for the second
set of outputs.

56
57-58

Blank
Punch "H", "L", or "X" for the third set
of outputs.

59

Punch "H", "L", or "X" for the sixth set
of outputs.
Blank
Punch "H", "L", or "X" for the soventh
set of outputs.
Blank
Punch "H", "L",or "X" for the eighth
set of outputs.
Blank
Punch a right-justified integer representing
the current calendar day of the month.
Blank
Punch an alphabetic abbreviation representing the current month.
Blank
Punch the last two digits of the current
year.
Blank

Blank

60·61

Punch "OM"

Punch "H", "L", or "X" for the fourth set
of outputs.

62-67

Punch the National Semiconductor part
number 54L 187 or 74L187

Blank

68-70

Blank

truth table

connection diagram
Dual-I n-Line and Flat Package
MEMORY
ENABlE

OUTPUTS

BINARY
Vee

SELECT H

MEl

ME,

'(,

Y,

ME,

ME2

1

0

0

Normal

1
X

X

Logical 1

1

Logical 1

1

1

Normal

0
X

X

Logical 1

0

Logical 1

1

0

Norma!

2

3

x '" Don't care
TOP VIEW

Order Number OM54L 187AJ
or DM74L 187 AJ
See Package 10
Order Number DM54L 187AN
or DM74L 187AN
See Package 15
Order Number DM54L 187AW
or DM74L 187AW

See Package 28

7·10

OUTPUTS

OPTION

X

1

Logical 1

0

X

Logical 1

Bipolar ROMs

~

..

Advance Information

NA110NAL

DM54S187/DM74S187 open-collector 1024-bit ROM
DM75S97/DM85S97 TRI-STATE® 1024-bit ROM

general description

features

These TTL compatible memories are organized in the
popular 256 words by 4 bits configuration. Two
memory enable inputs are provided to control the
output states. When both enable inputs are in the
logical "0" state, the outputs present the contents of
the word selected by the address inputs.

• Schottky clamped for high speed systems

If either or both of the enable ilJputs is raised to a logical
"1" level, it causes all four outputs to go to the "OFF"
or high impedance state. The memories are available in
both open·collector and TRI·STATE VerSiOIlS and are
available as PROMs as well as ROMs.

• PNP inputs reduce input loading

• High speed
Enable to output delay-typical
Address to output delay-typical

15 ns
30 ns

connection diagram
Dual-In-Line Package
A7

15

ENABLE 2 ENABLE lOUT 1

OUT2

OUT 3

12

11

10

14

13

OUT4

HI
A6

A5

A3

AD

AI

A2

TOP VIEW

Order Number DM54S187J or DM74S187J, DM75S97J or QM85S97J

See Packagll 10
Order Number DM74S187N or DM85S97N

Se. Packeae 15

7·11

absolute maximum ratings
Supply Voltage (Note 2)
Input Voltage (Note 2)
Output Voltage (Note 2)
Storage Temperature
lead Temperature (Soldering, 10 seconds)

-Q.5V to +7.0V
-1.2V to +5.5V
-Q.5V to +5.5V
--{j5°e to +150o e
3000 e

dc electrical characteristics

L.,ogical "1" Input Current

Supply Voltage (Vee)
DM54S187,DM75S97
DM74S187,DM85S97

MIN

MAX

UNITS

4.5
4.75

5.5
5.25

V
V
°e
°e

Ambient Temperature (T A)
DM54S187,DM75S97
DM74S187,DM85S97

--55
0

+125
+70

logical "0" Input Voltage

0

0.8

V

logical "1" Input Voltage

2.0

5.5

V

(Note 2)

PARAMETER
'IH

operating conditions

(Note 1)

CONDITIONS

MIN

TYP

MAX

UNITS

VIN = 2.7V

25

J.lA

VIN = 5.5V

1.0

mA

'lL

logical "0" I·nput Current

VIN = 0.45V

-250

J.lA

VCL

Input Clamp Voltage

'IN =-18mA

-1.2

V

VOL

logical "0" Output Voltage
DM54S187, DM75S97
DM74S187, DM85S97

Icc

IOL=16mA

Maximum Supply Current

80

0.50

V

0.45

V

130

mA

DM54S187, DM74S187
10H

logical "1" Output Current

V OUT = 2.4V

50

JJ.A

V OUT

100

J.lA

'=

5.5V

OM75S97, DM85S97
V OH

los

logical "1" Output Voltage
DM75S97

10H =-2.0 mA

2.4

V

DM85S97

10H =-6.5mA

2.4

V

Output Short Circuit Current

V OUT = OV (Note 3)

-30

-100

mA

-50

50

J.lA

MAX

UNITS

Vcc = Max
102

TRI·STATE Output Current

switching characteristics
PARAMETER
tAA

Address to Output Delay

teA

Time to Enable Output

0.45V ::; V OUT ::; 2.4V

(Note 2)
CONDITIONS

RL = 300n

MIN

TYP
30

ns

15

ns

15

ns

C L = 30 pF
teo

Time to Disable Output

Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that
the device may be operated at thEl!se values.
Note 2: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee = 5.0V and T A = 25"e.
Note 3: During lOS measurement, only one output at a time should be grounded .. Permanent damage may otherwise result.

7·12

Bipolar ROMs

~

Advance Information

NA'I10NAL

DM54S270/DM74S270 open-collector2048-bit ROM
DM54S370/DM74S370 TRI-STATE® 2048-bit ROM

general description

features

These TTL compatible memories are organized as 512
words by 4 bits, These devices effectively double the
capacity of the popular 1 k ROMs on the market by
utilizing .one chip-enable input as an additional address,
When the circuit is enabled, the 4 outputs present the
contents of the word selected by the address inputs,

• Schottky clamped for high speed systems
• High speed
Address to output delay-typical
Enable to output delay-typical
• PNP inputs reduce input loading

An overriding enable input is provided which, if in the
logical "1" state, causes all outputs to go to the "OFF"
state, or high impedance state, Available in both opencollector or TRI-STATE, both versions are also available
as Programmable Read Only Memories,

connection diag'ram
Dual-In-Line Package

vi'"

A7

116

ENABLE

Aft

OUT 1

13

14

15

OUT 2

12

OUT3

OUT4

10 '

11

-

4
A6

A5

A4

A3

AD

AI

A2

TOP VIEW

Order Number DM54S27OJ, DM54S37OJ, DM74S270J or DM74S37OJ

See Package 10
Order Number DM74S270N or DM74S37ON
See Package 15

7,,13

35 ns
15 ns

absolute maximum ratings
Supply Voltage (Note 2)
Input Voltage (Note 2)
Output Voltage (Note 2)

Storage Temperature
Lead Temperature (Soldering, 10 seconds)

operating conditions

(Note 1)

-o.5V to + 7 .OV
-1.2V to +5.5V
-o.5V to +5.5V
-65°e to +150o e
3000 e

DM54S270. DM54S370
DM74S270, DM74S370

Logical "1" Input Current

UNITS

4.5
4.75

5.5
5.25.

V
V

-55
0

+125
+70

°e
°e

Logical "0" Input Voltage

0

0.8

V

2.0

5.5

V

(Note 2)
CONDITIONS

PARAMETER
IIH

MAX

Ambient Temperature IT A)
DM54S270, DM54S370
DM74S270, DM74S370

. Logical "1" Input Voltage

dc electrical characteristics

MIN
Supply Voltage (Vee)

V IN ; 2.7V

MIN

TYP

Vee= Max

V ,N ; 5.5V

MAX

UNITS

25
1.0

Il A
mA
Il A

I'L

Logical "0" I nput Current

V ,N ; 0.45V, Vee; Max

-250

VeL

Input Clamp Voltage

liN ;-18 mA, Vee; Min

-1.2

VOL

Logical "0" Output Voltage
DM54S270, DM54S370
DM74S270, DM74S370

Icc

IOL; 16 rnA, Vee; Min

Maximum Supply Current

100

V

0.50

V

0.45

V

150

mA

50

Il A

100

Il A

DM54S270, DM74S270
10H

Logical "1" Output Current

V OUT ; 2.4V
V OUT ; 5.5V

Vee; Max

DM54S370, DM74S370
V OH

los

Logical "1" Output Voltage

Vee; Min

DM54S370

10H ; -2.0 mA

2.4

V

DM74S370

10H ;-6.5 mA

2.4

V

Output Short Circuit Current

V OUT ; OV (Note 3)

-30

-100

mA

-50

50

Il A

MAX

UNITS

Vee; Max
102

TRI-STATE Output Current

0.45V -:; V OUT -:; 2.4V
Vee

switching characteristics
PARAMETER
tAA

= Max

(Note 2)
CONDITIONS

Address to Output Delay

tEA

Time to Enable Output

tED

Time to Disable Output

RL = 300n
C L = 30 pF

MIN

TYP
35

ns

15

ns

15

ns

Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They' do not mean that
the device may be operated at these values.
Note 2: These limits apply-over the entire operating range unless stated otherwise. All typical values are for Vee =0 5.0V and TA = 2SoC.
Note 3: During lOS measurement, only one output at a time should be grounded. Permanent damage may otherwise result.

7-14

~

Bi'polar ROMs
.

Advance Information

NA110NAL

DM54S271/DM74S271 open~collector 2048-bit ROM
DM54S371/DM74S371 TRI-STATE® 2048-bit ROM

general description

features

These TTL compatible memories are organized in the
versatile· 256 weirds by 8 bits configuration. Two
memory enable inputs are provided to further enhance
their versatility. When both enable inputs are in the
logi~al "0" state, the eight outputs present the contents
of the word selected by the address inputs.·

• Schottky clamped for high-speed systems
• High speed
Address to output delay-typical
Enable to output delay-typical
• PNP inputs reduce input loading

If either tlr both of the enable inputs is raised to a logical
"'" level; it causes all eight outputs to go to the "OFF"
or high impedance state; The memories are available in
both open-collector arid TR I-STATE versions and are
available as PROMs as well as ROMs.

,. 20 pin, 300 mil package for high density

connection diagram
Dual-I n-Line, Package

A7

19

A6

18

Eii2

A5
17

m

OUTS DUT7 OUT 6 OUTS

15

12

11

OUT lOUT 2 OUT 3 OUT 4

GND

16

14

13

Jl0
AU

Al

A2

'A3

A4

TOP VIEW

Order Number DM54S271N, DM54S371N,
DM74S271N or DM74S371N

See Package 16A

7·'5

35 ns
ns

'5

absolute maximum ratings
Supply Voltage (Note 2)
Input Voltage (Note 2)
Output Voltage (Note 2)
Storage Temperature
Lead Temperature (Soldering, 10 seconds)

-Q.5V to +7.OV
-1.2V to +5.5V
-Q.5V to +5.5V

Ambient Temperature (T A)
DM54S271, DM54S371
DM74S271, DM74S371

MIN

MI\X

UNITS

4.5
4.75

5.5
5.25

V
V

+125
+70

-55
0

°c
°e

Logical "0" Input Voltage

0

0.8

V

Logical "I" Input Voltage

2.0

5.5

V

(Note 2)
CONDITIONS

PARAMETER
Logical "1" Input Current

Supply Voltage (Vee)
DM54S271,DM54S371
DM74S271, DM74S371

-£5°(; to +1500 e
3000 e

dc electrical characteristics

IIH

operating conditions

(Note 1)

MIN

TYP

MAX

UNITS

VIN = 2.7V

25

/lA

VIN = 5.5V

1.0

mA
/lA

ill

Logical "0" Input Current

VIN = 0.45V

-250

Vel

Input Clamp Voltage

liN =-18mA

-1.2

VOL

Logical "0" Output Voltage

IOl=16mA

Icc

Maximum Supply, Current

V

0.50

V

150

mA

V OUT = 2.4V

50

/lA

V OUT = 5~5V

100

/lA

100

DM54S271,. DM74S271
10H

Logical" 1" Output Current

DM54S371. DM74S371

V OH

los

Logical "1" Output Voltage'
DM54S371

10H =-2.0 mA

2.4

DM74S371

IOH =-6.5 mA

2.4

Output Short Circuit Current

V OUT = OV (Note 3)

V
V

-3D

-100

mA

-50

50

/lA

MAX

UNITS

Vcc = Max
102

TRI·STATE Output Current

switching characteristics
PARAME;TER
tAA
tEA

0.45V ::; V OUT ::; 2.4V

(Note 2)
CONDITIONS

Address to Output Delay
Time to Enabl,e Output

Rl = 300n

MIN

TYP
35

ns

15

ns

15

ns

C l = 30 pF
tED

Time to Disable Output

Note 1: Absolute m?lximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the
device may be operated at these values.
Note 2: 'These limits apply over'the entire operating range unless stated otherwise. All typical values are for Vee = S.OV and T f\ = 2SoC.
Note 3: During lOS measurement, only one output at a time should be grounded. Permanent damage may otherwise result.

7·16

o

~

Bipolar ROMs
Advance Ir)formation

~

.....

N

en

o

:t
o

NAllONAL

~
00

DM72S04lDM82S04 TRI-STATE® 2048 bit ROM with latches

N

en

general description

o

until the strobe is' again taken to the logical "1" state
regardless of the state of the address or enable inputs.

These TTL compatible memories are organized as 256
words by 8 bits. Two enable inputs are provided. When
the strobe .input is at a logical "1" level the memories
function in the conventional manner with the enable
inputs determining whether the outputs present the
contents selected by the address inputs or are .. in the
high impedance state. The outputs are in the high
impedance state unless enable 1 is at a logical "0" and
enable 2 is at a logical "1."

~

features
• Schottky clamped for high speed systems
• High speed
Enable to output delay-typical
Strobe to output delay-typical
Address to output delay-typical
• PNP inputs redu.ce input loading
• Output latches simplify system use

When the strobe is at a logical "0" the outputs are
latched into the state they were in just prior' to the
strobe going low. The outputs remain in this condition

15 ns
20 ns
35 ns

logic and connection diagrams
AD

0:-

.

t-

A7e-:

,...

.

'-

..
t-

ADDRESS
BUFFER
AND
DECODE

..

x8

256

ARRAY

B-BIT
LATCH

f:-o
8 OUTPUT
DRIVERS

t-

l-

r

.

D1

~OB

STROBE
DTYPE
LATCH

ENABLE 1 V"--"'"'I
....--r-.... I
ENABLE 2

n.o--...J-L......II--_...J.

Dual·1 n·Line Package
OUTPUTS

,

f

AI

AD

22

EN1

21

20

EN~

STRBE

19

5

8

18

17

15

16

NC

14

Tn

&II
I

r-

AJ

2r

A4

NC

5
A5

A6

6
A7

.

10

4

OUTPUTS
TOP VIEW

(NC'" No Connection I"temlll,)

Order Number DM72S04J or DM82S04J
See Pa.kaga 11
Ordar Number DM82S04N

S.a Package 18

7·17

..1..11

J.12

NC

GND

absolute maximum ratings

operating conditions

(Note 1)

---+----1-¥----+---.,.
'-'-_-+
__++___+-¥-_i,.

23 13

I.

3

22. 2
21.,

}OA"

IN'UTS

" '.
"F,

DATA

INPUTS
F,orF,

II F,

I"

.

'
F,.,F.

,

IJ

,Ita

~"'~

.

F~

II F..

I"

"

IS F]
1· F•

'

I3 f ,

GNO'2

Order Number DM7575J, DM8575J.
DM7576J or DM8576J

SeePack_11
Order Number DM8575N or DM8576N

See Package 18

7-24

absolute maximum ratings (Note 1)

operating conditions
MAX

MIN
7.0V
5.5V
-65°C to +15O"C
300"C

Supply Voltage
Input Voltage
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)

electrical characteristics

Supply Voltage (Vcc)
DM7575, DM7576
DM8575, DM8576
Temper~ture (TA)
DM7575, DM7576
DM8575, DM8576

Vee'" Min

Logical "0" Input Volt,ge

Vee;: Min

Logical "I" Output Voltage
(DM7575/DM8575 Only)

V

= 2V r VINIO) = O.SV
In, lOUT =-~A

- M'

cc -

V1NU)

= Max. V OUT

= 5.5V

Logical "0" Output Voltage

V

'" Min V 1NI1I

'"

cc
V

LOgical "1" Input' Current

(Note 3)

DM7575176
DM8575/76

..

•
- M

cc -

MAX

TYP

V

V

°c

·C

lOUT

V'N

100
0.4

:

=2.4V

40
1

ax, VIN = 5.5V

-Vet: "" MIX, VrN = OAV

-1..0.'
-201-1:15
-181-1.65

Vee = Max. V OUT = OV

=Max

110

Supply Current

Vee

Input Diode Clamp Voltage

Vee = Min,
TA = 25°C .IIN = -12 mA

Propagation Delay to a Logical "0" f.rom Data
Inputs to Outputs, tpdD

Vee = 5.0V.
T A = 25°C CL

Propagation Delay to a logical "1" from Data
Inputs to Outputs, tpd1

Vee = 5.0V
T,,=25°C

=50 pF, RL =

400n

V
V

2.4

2V, V'N(OI '" O.BV

=+12mA

UNITS
V

0.8

Vee

Output Short Circuit Current

+125
70

2

Logical "I" Output Current
(DM75761DM8576 Only)

-~

o

MIN

CONDITIONS

PARAMETER

..

-55

5.5
5.25

(Note 2)

Logical "I" Input Voltage

togicat.ue'Ltnput Current

4.5
4.75

UNITS

100
80

~A

V
~A

mA
.,,-+-++.-II-t>-+-++<.-IH-+.,

A8 ~-____---'

,

2

3

5

4

A7 _Ai
AS_ _A4
___

~

~

7

8

,

AJ
AZ_ _AI
AD'
___
_- J

9
01

10
02

11
03

lIZ
GND

~

BINARY

OUTPUTS

SELECT
08

TOP VIEW

01

Order Number DM8595N
or DM8795N

Order Number DM7595J,
DMB595J, DM7795J
or DM8795J

See Package 18

SeePack_11

logic diagrams and truth tables for enable circuitry
DM7595/DM8595

DM7595/DM8595

,-------..,
IE4~"
I

E3

11

El

E2

E3

E4

OUTPUT

,

0
X

X
X

0
X
X
X

Read Stored Data

,

0
X "X
X

0

II

I ~ ,.
IL ~_______
21
..JI

X
X
X

,

,

Logical "'"
Logical "'"

Logical "1"
Logical "'"

X = Oon't Care
ENABLE=E'·E2·E3·E4

DM7795/DM8795

DM7795/DM8795

".------,
1E4
I
lu

19

I~ "

E'

E2

,

0
X

X
X
X

X
X

0

I
I

IL!' _______
"
..JI

,

E3

E4

, ,

X
X
0
X

X
X
X
0

OUTPUT

Read Stored Data
Logical "'"
Logical "'"
Logical "'"
Logical "'"

x = Don't Care
ENABLE = E' • E2 • E3 • E4

7-34

absolute maximum ratings
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range

operating conditions

(Note 1)

Supply Voltage (VCCI
DM7595, DM7795
DM8595, DM8795

7.0V
5.5V
5.5V

-65°C to +150°C
300°C

Lead Temperature (Soldering, 10 seconds)

electrical characteristics

Temperature (TAl
DM7595, DM7795
DM8595, DM8795

MIN

MAX

UNITS

4,5
4.75

5.5
5.25

V

+125
+70

-65
0

V

°c
°c

(Note 2)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

VIH

Logical "1" Input Voltage

Vec = Min

VIL

Logical "0" Input Voltage

Vec = Min

0.8

IOH

Logical "1" Output Current

Vee = Max, Vo = 5.5V

100

VOL

Logical "0" Output Voltage

Vee = Min, 10 = 12 mA

0.4

V

IIH

Logical "1" Input Current

40

/lA

1

mA

-1.0

mA

Vec = Max

2.0

I

I

V ,N = 2.4V
V ,N = 5.5V

IlL

Logical "0" Input Current

Vce = Max, V ,N = O.4V

Icc

Supply Current

Vee = Max

VIC

I nput Clamp Voltage

tPLH

tpHL

tPLH

tpHL

103

V
/lA

mA

158
-1.5

Vee = Min, liN =-12 mA

switching characteristics
PARAMETER

V

V

(Note 2)

PARAMETER
CONDITIONS

TEST
CONDITIONS

Propagation Delay Time,

Access Time from

Low to High Level Output

Address

Propagation Delay Time,

Acc'ess Time from

High to Low Level Output

Address

C L =30pF,

Output Disable Time to

Disable Time from

RL =400n

High Level

Memory Enables

Output Enable Time to

Access Times from

Low Level

Memory Enables

DM7595,DM7795

DM8595,DM8795
UNITS

MIN

TYP

MAX

TYP

MAX

80

150

80

120

ns

80

150

80

120

ns

60

120

60

90

ns

60

120

60

90

ns

MIN

Note': "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table bf "Electrical Characteristics" provides conditions for actual device operation.
Note 2; Unless otherwise specified minImax limits apply across the ---{j5°C to +125°C temperature range for the OM7595 and DM7795 and
across the oOe to +70(lC range for the DM8595 and DM8795. All typicals are given for Vee = 5.0V and TA ;::; 25~C~

7-35

80-columncard program data format

I.C)

en
I.C)
00

:!

c

......
I.C)
en

,...

Col. 31: (Blank)
Col. 32-39: Word Data
Col. 40: (Blank)
Col. 41-48: Word Data
Col. 49: (Blank)
Col. 50-57: Word Data
Col. 58: (Blank)
Col. 59-66: Word Data
Col. 67: (Blank)
Col. 68-75: Word Data
Col. 76-78: (Blank)
Col. 79-80: Card sequence number. 1 to 64_ Leading
zeros may be punched or suppressed_ (Note 2)

Col. 1-3: 3 Character ID code any 3 Alpha-Numeric
characters. Must be the same on all cards associated with
a particular pattern, but different for the ID code used
on 'other patterns. The purpose of this code is to prevent mixing of cards.
Col. 4: (Blank)
Col. 5-12: Word Data. Order is 08 (most significant)
to 01 (least significant). Note 1_ Characters-For TTL
high level are: H or 1. Characters-For TTL low are L
or O. "Don't Care" is X_
Col. 13: (Blank)
Col. 14-21: Word Data-same format as 5-12.
Col. 22: (Blank)
Col. 23-30: Word Data

I.C)

:!

c

Note 1; The words are listed in sequence beginning on the first card with the word associated with address 0 and ending on
the last card with the word associated with address 511. Address input AS is the most Significant; AQ, the least significant.
Note 2: Card sequence numbers reference a specific group of 8 words, Le.;
Card 01 : Word address 0 to 7
Card 02: Word address 8 to 15
Card 03: Word address 16 to 23

Card 64: Word address 504 to 511.

ac test circuit
Vee = 5V

400

OUTPUT

1

~~~~~~----.-------.
TEST

rJOPF

~

1.

"*"
switching time waveforms

t'"

'-'=),..

P-'H-F--1-'S-V-'OUTPUT-------'"-----':-t.--1.-SV---'---...
-t

Input waveforms are supplied by pulse generators having the following characteristics:

t:;: 10 ns. tf:;: 10 ns, PRR

~

1 MHz. Amplitude

7-36

~

3.0V. POC

~

50%, and Zo

= 50n.

~

Bipolar ROMs

NAl10NAL

DM7596/DM8596 TRI-STATE@4096-bit bipolar ROM
DM7796/DM8796 TRI-STATE4096-bit bipolar ROM
general description

features

The DM7596/DM8596 and DM7796/DM8796 are 4096bit bipolar mask-programmable ROMs organized as 512
eight-bit words. Nine address inputs select the desired
one-of·512 words. Fou~ enable lines are used to either
enable or disable the circuit. The two devices differ in
the enable logic. Truth tables and logic diagrams for each
device are shown below. TRI-STATE outputs allow for
expansion to greater numbers of words without sacrifice
in speed as would be evidenced by open-collector
outputs.

• Series 54/74 specification compatibility

logic and connection diagrams

• Pin compatible with Monolithic Memories MM5241/
MM6241

• Typical address time

80 ns

• TRI-STATE outputs
Dual-I n-Line Package

(Top View)
BINARY

ENABLES

SelECT
Vee

A8

OUTPUTS
f

NC

EZ

E1

E3

E4

DB

07

06

D.

04

A5
IZ4

A4
A3

Z3

ZZ

21

2D

19

lB

16

17

15

13

"

64 X 64 MEMORY ARRAY

AZ

Al
AD

-

-

AB
A7
A6

,
A7

3

2
A6

6

5

4

AS

A4

A3

B

7

A'

AZ

AD

9

07

06

Order Number OM7596J,
OM8596J, OM7796J
orOM8796J

05

See Package 18

logic diagrams and truth tables for enable circuitrY
OM7596/0M8596

,-------,

E1

E2

E3

OUTPUT

E4

'E4~'Bg,
1
" I"

0

0

0

Read Stored Data

I 'z
I E1

I

X

X

X

X
X

I

X

X
X

X

X

X
1
X

Hi -Z
Hi - Z
Hi - Z
Hi - Z

,

, '3

20

"

21

I

L _______ .J

0

I

-

-

X = Don't Care ENABLE = E, • Ez • Eo •

1'3

I,z

I

19

20
21

E.

OM7796/0M8796

OM779SioM8796

,,8"-----,I
I '4
I

E1

E2

0

0

E3
1

E4
I

OUTPUT
Read Stored 'Data

X
X Hi· Z
X
X Hi· Z
0
X
X
Hi ·Z
X
0
Hi· Z
X
X = Don't Care ENABLE = E, • Ez • Eo • E.

I

I

L!' _______ ...J

7·37

1

X

X
X
X

1

,

rz
GNu

Order Number OM8596N
orOM8796N

See Package 1.1

OM7596/DM8596

.

11

0,3

OUTPUTS

B'NARY
DB

,.
OZ

01

I

D

absolute maximum ratings

operating conditions

(Note 1)

Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldering, 10 secondsl

7.0V
5.5V
5.5V
-ii5°C to +150°C
300°C

electrical characteristics

(Note 2)

Supply Voltage (V CCI
DM7596, DM7796
DM8596, DM8796
Temperature (TAl
DM7596, DM7796
DM8596, DM8796

MIN

MAX

UNITS

4.5
4.75

5.5
5.25

V
V

+125
+70

-55
0

°c
°c

(g

en

Ln
ex)

:E
Q

......
(g

en
Ln

!iQ

CONDITIONS

PARAMETER
VIH

Logical "1." Input Voltage

Vee = Min

VIL'

Logical "0" Input Voltage

Vee = Min

VOH

Logical

VOL

Logical "0" Output Voltage

Vee = Min, 10 = 12 mA

102

TRI·STATE Output Current

Logical "1" Input Current

Vee = Max

40

p.A

1

mA

-1.0

mA

-70

mA

Icc

Supply Current

'Vee = Max, Inputs Grounded

VIC

Input Clamp Voltage

Vee = Min, I'N = -12 mA

tHZ

tL2

V

V'N = 5.5V

Vee = Max, Vo= OV, (Note 3)

tZL

0.4

V'N =2.4V

Output Short Circuit Current

tZH

V

-40

los

tPHL

V

2.4

Vo = 0.4V

Vee = Max, V'N = 0.4V

tPLH

V

40

Logical "0" I nput Current

PARAMETER

UNITS

Vo = 2.4V

IlL

switching characteristics

MAX

0.8

Vee = Min, 10 = -2 mA

IIH

TYP

2.0

"i" Output Voltage

Vee = Max

MIN

-15

p.A

170

106

mA

-1.5

V

(Note 2).

PARAMETER
CONDITIONS

Propagation Delay Time,

Access Time from

Low to High Level Output

Address

TEST
CONDITIONS

Propagation Delay Time,

Access Time from

High to Low Level Output

Address

C L = 50 pF,

Output Enable Time to

Access Times from

RL = 400n

High Level

Memory Enables

Output Enable Time

Access Times from

to Low Level

Memory Enables

Output Disable Time from

Disable Times from

High Level

Memory Enables

C L = 5.0 pF,

Output Disable Time from

Disable Times from

RL = 400n

Low Level

Memory Enables

DM7596,DM7796
MIN

DM8596,DM8796
MAX

150

80

120

ns

80

150

80

120

ns

40

120

40

90

ns

60

120

60

90

ns

20.

70

20

50

ns

25

70

25

50

ns

MAX

80

MIN

UNITS

TYP

TYP

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device ca~mot be guaranteed. "Except for "Operating
Temperature Range". they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise ,pacified minimax limits apply across the -55°C to +125'C temperature range for the DM7596 and !DM7796 and across
the O°C to 70°C range for the DM8596 andDM8796. All typicals are given for VCC = 5.0Vand TA = 25°C.
Note 3: Only one output at a time should be shorted.

7·38

c

s::.....

80-column card program data format

(J'I

CO

Col. 32·39: Word Data
Col. 40: (Blank)
Col. 41-48: Word Data
Col. 49: (Blank)
Col. 50·57: Word Data
CO,I.58: (Blank)
Col. 59·66: Word Data
Col. 67: (Blank)
Col. 68·75: Word Data
Col. 76·78: (Blank)
Col. 79-80: Card sequence nlimber. 1 to 64. Leading
zeros may be punched or suppressed. (Note 2)

Col. 1·3: 3 Character ID code any 3 Alpha·Numeric
characters. Must be the same on all cards associated
with a particular pattern, but different for the ID code
used on other patterns. The purpose of this code is to
prevent mixing of cards.
Col. 4: (Blank)
Col. 5·12: Word Data. Order is 08 (most significant) to
01 (least significant). Note 1. Characters-For TTL high
level are: H or 1. Characters-For TTL low are L or O.
"Don't Care" is X.
Col. 13: (Blank)
Col. 14·21: Word Data-same format as 5·12.
Col. 22: (Blank)
Col. 23-30: Word Data
Col. 31: (Blank)

Card 64: Word address 504 to 511

=1'fpLH}.'

ac test circuit and switching time wavefonns
BINARY
SELECT,
INPUT
INOTE II

, '

,1.5V
__
' _____

t~

Ii .SV

.

,

'

_

fpHL~

j~~------------

DUTPUT

"

1.5V

,1.5V

5,OV

400

ENABLE
INPUT
INDTE II

DUTPUT

DEVICE
UNDER
TEST

C

s::00
(J'I

~
C

s::
~

en

......
C

s::00

.....
CD
en

Note 1: The words are listed in sequence beginning on the first card with the word associated with address 0 and ending on
the last card with the· word associated with address 511. Address input AS is the most significant; AO. the least significant.
No~e 2: Card sequence numbers reference a specific group of 8 words, i.e.;
Card 01: Word address 0 to 7
Card 02: Word address 8 to 15
Card 03: Word address 16 to 23

DI

en
......

OUTPUT

--

VOH
OUTPUT

'LZ- /"t".--------O.SV

-+____

VOL _ _ _ _ _

>1.5V'

-,

-.-L

-----+---....,'~0.5V

,,1....._____

_ _ 'HZ

>1.5V

All diodes are F0100.
-1.5V
OUTPUT

_I
0.5V

-----+---~

- - - tZL ----- " ' -_ _ _ _ _ VOL

t.lH

---Id;----

OUTPUT
-1.5V _ _ _ _ _ _ _ _ _

VOH

O.5V

-I

Note 1: Input waveforms are supplied by pulse generators having the
following characteristics: .

tr ::; lCJ.ns, tf::; 10 ns, PRR
and Zo = son.

7·39

= 1 MHz. poe = 50%, Amplitude = 3.0V,

Bipolar ROMs

~.
NAnONAL

DM7597/DM8597 TRI-STATE@1024-bit read only memory
general description
The OM7597/0M8597 is a custom-programmed
read-only memory organized as 256 four-bit words_
Selection of the proper word is accomplished
through the eight select inputs. Two overriding
memory enable inputs are provided, which when
mask-programmed i'n one of three options described will cause all four outputs to either read
the normal memory contents or go to the "high
impedance" state. In this state both the upper and
lower output transistors are turned off. The outputs may therefore be paralleled to increase word

capacity; since in the high-impedance state they
present only a minimal load to the active output.

features
• Pin compatible with SN54187/SN74187
• 35 ns typical delay from address to output
• Can be expanded to 32,768 4-bit words by
simple paralleling of outputs
• Programmable memory enable inputs

logic diagram

BINARY
SELECT

'"
'"
'"

::~~
01'1'10111

truth table

connection diagram
Dual-In-Line Package

TABLE of Programmable MemolY Enable Options

MEl

ME2

1

0
1
X

0
X
1

Normal

1
0

1

Normal
HIGH Impedance
HIGH Impedance

2

X

3

1

X
0

x - don t care
TOP VIEW

Order Number DM7597J or DM8597J
See Package 10

Order Number DM8597N
See Package 15

7-40

OUTPUTS

OPTION

X
0

HIGH Impedance
HIGH Impedance

Normal

0
1

HIGH Impedance

X

HIGH Impedance

absolute maximum ratings (Note

c
3:
....
(JI

1)

CD
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature Range DM7597
DM8597
Storage Temperature Range
Lead Temperature (Soldering. 10 sec)

....

7V
5.5V
5.5V
_55°0 to +125°0
0°0 to +70°0
-65°0 to +150°0
300°0

.......
C

3:
CO

(JI

CD
....

electrical characteristics (Note 2)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Logical "1" Input Voltage

DM7597
DM8697

Vee = 4.5V
Vee -4.75V

Logical "0" Input Voltage

DM7597
DM8597

Vee = 4.5V
Vee - 4.75V

logical "1" Output Voltage

DM7597
DM8597

Vee = 4.SV
Vee = 4.7SV

10 =-2mA
10 = -5.2mA

Logical "0" Output Voltage

DM7S97
DM8S97

Vee = 4.5V
Vee =4.7SV

10 = 16mA

Third State Output Current

DM7597
DM8597

Vee = 5.5V
Vee - ~.2SV

Vo = 2.4V
Vo = 0.4V

40
-40

IlA
IlA

Logica'''1'''np.ut Current

DM7597
DM8S97

Vee = S.SV
Vee = S.2SV

VIN = 2.4V

40

./lA

DM7597
DM8597

Vee = 5.5V
Vee = 5.25V

Y'N = 5.5V

DM7597
DMS597

Vee = S.SV
Vee = 5.2SV

Y,N

DM7597
DM8597

Vee = 5.5V
Vee·· S.2SV

Vo = O.OV

DM7597
DM8S97

Vee = 5.5V
Vee = S.2SV

All Inputs at GND

DM7597
DM8597

Vee = 4.5V
Vee ~ 4.75V

liN =-12mA

2.0

V
0.8

V
V

2.4
0.4

V

1.0

rnA

-1.0

rnA

Logical "0" Input Current

Output Short Circuit Current

(Note 3)
Supply Current

Input Clamp Voltage

Propagation Delay to a Logical "0" from

=

0.4V

-20
75

-70

rnA

110

rnA

-1.5

V

Vee = 5.0V
TA = 2S·C

39

60

n,

Propagation Delay to a Logical "1" from
Address to Output,

Vee = S.OV
TA = 2SOC

31

60

n,

Delay from Enable to High Impedance
State (from Logical"," Level). t'H

Vee = 5.0V
TA = 25°C

13

30

n,

Delay from Enable to High Impedance
State (from Logical "O".Levet). tOH

Vee = S.OV
TA = 25°C

16

30

n,

Delay from Enable to Logical "1" Level

(from High Impedance State). tH'

Vee = 5.0V
TA = 25°C

18

30

ns

Delay from Enable to Logical "0" Level
(from High Impedance State). tHO

Vee = 5.0V
TA = 25°C

20

30

n'

Address to Output,

!PdO

t".,

Note 1: " Absolute Maximum Ratings" are those values beyond which the safety of the 9evice cannot
be guaranteed. Except for "Operating Temperature Range" .they are not meant to imply that the
devices should be op~rated at these limi\s. The table of "Electrical Characteristics" provides conditions

for actual devic.~ operation.
Note 2: Unless otherwise specified min/max limits apply across the -5SoC to +12SoC tempeJlature
range for the DM7597 and across the O°C to 70°C range for the DM!l597. All typicals are given for
VCC = 5.0V and T A = 25°C.
Note 3: Only one output at a time should be 'horted.

7·41

II
I

ordering instructions

Programming instructions for the DM7597 or
DM8597 are solicited in the form of a sequenced
deck of 32 standard 80-column data cards providing the information requested under data card
format, accompanied by a. properly sequenced
listing of these cards, and the supplementary
ordering data. Upon receipt of these items, a computer run will be made from the deck of cards
which will produce a complete truth table of the
requested part. This truth table, showing output
conditions for each of the 256 words, will be
forwarded to the purchaser as verification of the
input data as interpreted by the computer-automated design (CAD) program. This single run also
generates mask and test program data; therefore,
verification of the truth table should be completed
promptly.

10-13

14
15-18
19
20-23
24
25-28
29

Each card in the data deck prepared by the purchaser identifies the eight words specified and
describes the conditions at the four outputs for
each of the eight words. All addresses must have
all outputs defined ..and columns designated as
"blank" must not be punched. Cards should be
punched according to the data card format shown.

30-33
34
35-38
39
40-43

supplementary ordering data
44
45-48

Submit the following information with the data
cards:

49

a) Customer's name and address
b) Customer's purchase order number
c) Customer's drawing number.

50-51
52
53-55

data card format
56
Column
1- 3

4
5- 7

8· 9

57-58

Punch "H", "L", or "X" for bits four,
three, two, and one (outputs Y4, Y3, Y2,
and Y1 in that order) for the first set of
outputs specified on the card. H = highlevel output, L = low-level output, X =
output irrelevant.
Blank
Punch "H", "L", or "X" for the second
set of outputs.
Blank
Punch "H", "L", or "X" for the third set
of outputs.
Blank
Punch "H", "L", or "X" for the fourth set
of outputs.
Blank
Punch "H", "L", or "X" for the fifth set
of outputs.
Blank
Punch "H", "L", or "X" for the sixth set
of outputs.
Blank
Punch "H", "L", or "X" for the seventh
set of outputs.
Blank
Punch "H", "L", or "X" for the eighth
set of outputs.
Blank
Punch a right-justified integer representing
the current calendar day of the month.
Blank
Punch an alphabetic abbreviation repre·
senting the current month.
Blank
Punch the last two digits of the current
year.

Punch a right-justified integer representing
the binary input address (000-248) for
the first set of outputs described on the
card.

60-61

Punch "DM"

Punch a "-" (Minus sign)

62-65

Punch 7597 or 8597

Punch a right-justified integer representing
the binary input address (007-255) for
the last set of outputs described on the
card.

66-70

Blank

71

Punch 1, 2, or 3 for memory enable
option desired (assumed 1 if not punched).

59

Blank

7·42

Blank

~

Bipolar ROMs

NA110NAL

DM7598/DM8598 TRI-STATE® 256-bit read only memory
general description
The DM7598/DM8598 is a customer programmed
256-bit read only memory, organized as 32 8-bit words.
A 5-bit input code selects the appropriate word which
then appears on the eight outputs. An enable input
overrides the select inputs and blanks all outputs.

speed would be achieved. The low output impedance of
the DM7598/DM8598 provides good capacitance drive
capability and rapid transition from the logical "0" to
logical "1" level thus assuring both speed and waveform
integrity.

Although the DM7598/DM8598 can have its outputs
tied together for word-expansion, the outputs are not
open-collecto~, but rather the familiar totem-pole output
with the capability of being placed in a "third-state."
This unique TRI-STATE concept allows outputs to be
tied together and then connected to a common bus line.
Normal TTL outputs cannot be connected due to the
low-impedance l09ical "1" output current which one
device would have to sink from the· other. If, however,
on all but one of the connected devices both the upper
and lower output transistors are turned "OFF," then the
one remaining device in the normal low impedance state
will have to supply to or sink from the other devices
only a small amount of leakage current. This is exactly
what occurs on the DM7598/DM8598.

It is possible to connect as many as 128 DM8598s to a
common bus line and still have adequate drive capability
to allow fan-out from the bus. The example shown in
Figure 2 indicates how this guarantee can be made under
worst-case cond itio.ns.
Figure 3 indicates how multiple packages can be used to

increase word length.

features
.,
•
•
•
•
•
•

A typical system connection demonstrating expansion to
greater numbers of words is shown in Figure. 1. While it
is true that in a TTL system open-collector gates could
be used to perform the logic function of these threestate elements, neither waveform integrity nor optimum

Pin compatible with SN5488/SN7488
Organized as 32 8-bit words
Full internal decoding
26 ns typical access time
350 mW typical power dissipation
Input clamp diodes
Designed for bus-organized systems

logic and connection diagrams

BIliARY
SELECT

.C

Dual-In-Line Package

"....
,..

Y>o-

111' ....

I ...

112' ....

I ...v

1131 ....

I .......

,,~

•
r---r

~

1

,

I

-~

r r7r7r'(;'lr ? '1: 7
7

M.

".

...

,.T

PROGRMaII ... G

s....

m

'It

(5)
(41
31
11
IJI
nI
VIY1V&VSV",V3V2Y1
OUlPUTS .

DUTPUTS
TorVIE.-

Order Number DM7598J or DM8598J
. See Package 10
Order Number DM8598N

See Package 15

7-43

absolute maximum ratings
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature Range
DM7598
DM8598
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)

electrical characteristics
SYMBOL

operating conditions

(Note 1)

Temperature, TA
DM7598
DM8598

-55°C to +125°C
O°C to +70°C
4l5°C to +150°C
300°C

CONDITIONS

PARAMETER
Logical "1" Input Voltage

Vee = Min

VIL

Logical "0" Input Voltage

Vee = Min

VOH

Logical "1" Output Voltage

VOL

Logical "0" Output Voltage

loz

TRI·STATE Output Current

Vee = Min

10 = -2 mA, DM7598
10

Vee = Max

MAX

Vee = Max

UNITS
V
V
V

2.4

V

Va = O.4V

-40

Y,N =2.4V

25

/J.A

Y'N - 5.5V

1

mA

-1.0

mA

-70

mA

99

mA

Supply Current

Vee =

VIC

I nput Clamp Voltage

Vee = Min, ',N = -12 mA

tLZ

TYP

0.4

ICC

tHZ

°c
°c

40

Vee = Max, Y'N = O.4V

tZL

+125
+70

Vo =2.4V

Vee = Max, Vo = OV, (Note 3)

tZH

V
V

2.4

= -5.2 mA, DM8598

Logical "0" I nput Current

tpHL

5.5
5.25

0.8

Output Short Circuit Current

tpLH

4.5
4.75

2.0

IlL

PARAMETER

UNITS

-55
0

MIN

lOS

SYMBOL

MAX

Vee = Min, 10 = 12 mA

Logical "1" Input Current

switching characteristics

MIN

(Note 2)

VIH

IIH'

Supply Voltage, VCC
DM7598
DM8598

7V
5.5V
5.5V

-20

M~x, I nputs Grounded

70

/J.A

-1.5

V

(Note 2)

PARAMETER
CONDITIONS

TEST
CONDITIONS

Propaghtion Delay Time,

Access Time from

Low to High Level Output

Address

Propagation Delay Time,

AccessTime from

High to Low Level Output

Address

C L = 50 pF,

Output Enable Time to

Access Times from

RL =400n

High Level

Memory Enable

Output Enable Time to

Access Times from

Low Level

Memory Enable

Output Disable Time from

Disable Times from

High Level

Memory Enable

C L = 5.0 pF,

Output Disable Time from

Disable Times from

RL =4000

Low Level

Memory Enable

DM8598

DM7598
MIN

TYP

MAX

23

MIN

UNITS

TYP

MAX

65

23

50

ns

29

65

29

50

ns

16

40

16

30

ns

20

40

20

30

ns

10

30

10

20

ns

22

45

22

40

ns

,

Note 1: "Absolute Maximum Ratings" are those valuos beyond which the safety of the. device cannot be guaranteed. Except for "Operetlng
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Charactwlstics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply across the ~5°C to +12SOC temperature range for the DM7598 and across the rf'e to
+7rf'e range for the DM8598. All typicals are given for Vee = 5.0V, and T A = 2SOe.
Note 3: Only one output at a time should bo shorted.

7·44

c

s:......

typical applications

U1
CD
.......
00

c

s:00
,us
UNE

OUTPUTS

[

OF OTHER
ME MORIES

II
v,

r

Y2

~3

~4

~5

Y6

V7

JI
v,

V8

..--<:

DM1S98/0M8598

ME

A

,

C

o

J"
~4

V3

V2

V5

Y6

V7

A

YB

CO,

•

I

BINARY
} TO
SEl EeT INPUTS
OF OTHER
ME MORIES

TO ENABLE INPUTS OF OTHER MEMORIES

1

CD
00

OM7S9S/DMB598

ME

E

0

U1

1 , 1, 1
2

5

6

, ,

7

10

12

11

!1
13

14

,

15

OM54154fDM74154

•

A

I

A

H

Co

0

f

F

J

0

.,

.2

ENABLE

lOW

II

II r
H

,C

J

BINARY SELECT REGISTER

FIGURE 1. Expansion to Larger Word Capacity

16·BITWORD

O.120mA
OM7S9aJOMBSgas

GATED INTO
LOW IMPEDANCE
LOGICAL "1"
STATE

011

5.2mA

GATED INTO
HIGH IMPEDANCE
STATE

."

DM1598/0MB59B

OM7598/DMI5IB

ME
GATED INTO
HIGH IMPEOANCE
STATE

•,

C

0

E

•

C

0

E

1I0.uAx 127 " 5.01 mA

40.uA

BUS LINE

OTHER DM7!i98/DMB598
DUTPUTS

ENABLE

A

BINARY SELECT
REGISTER

FIGURE 3.

FIGURE 2.

7-45

00
~
~

truth table/order blank

c:

A special pattern has been generated for the DM7598/DM8598. The AA pattern provides a sine table. The 5-bit input code linearly divides
90° into 32 equal segments. Each .B-bit output is therefore the sine of the angle applied.

C
00

1/64) or about. 0.95, which is close to the sine of 73°. Rounding-off has not been employed, since without rounding-off it is possible to

.......

en

Ie

:E

c

EXAMPLE: Input 11010 means 26/32 of 90°, or about 73°. The corresponding output 1110100 indicates (1/2 + 114 + lIB + 1/16+
extend the accuracy with additional ROMs.
ouTPuTS

INPUTS

BINARY SELECT

WORD
0
1
2

,
,
4

6

7
8

•

10
11
12

"

14

15
16
17

,.

18
20

21
22
23
24

25
26
27
28
29
3D

31
All

E

D

C

0
0

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0

G
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1

,

1
1
1
1
1
1
1
1
1
X

0
0
0

0
0
0
0
0
1
1
1
1
1
1
1
1
X

0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X

•
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1

ENABLE
A

ME

V8

0
1

0
0
0
0

0
0
0
0
0
0
0
0
0
0
0

G
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1

X

X

0
0
0
0
0
0
0
0
0
.0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Hi·Z

Y7

Y6

V,

Y,

V3

Y2

0

0
0
0
1
1
1
0
0
1
1

0
0
1
0
1
1
0
1
0
0
1

0

0
1
0
1
0
1
0
1
0
1
0
0
1
0
0
0
1

0

0

0
0
0
0
1

0
1
1
1
0
0
0
1
1
0
1
0
0
0

0
0
0
0
0
1
1
1
1
1
0
0
0
0
0

0
0
1
1
1
1
1
1
1
1

,
1
1
1

1
1
Hi·Z

1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1

0
0
1
0
0
1
1
0
0
1
1
0
0
0
1
1

1
1
0
0
1
1
0
0
1
1
0
1
1
0
1
0
1

1
1
1
1
1

1
1
1
1
1

0
1
0
1
0
0
1
0
0
1
1
1
1
1

Hi-Z

Hi·Z

Hi-Z

1
1
1
1
0
0
1
1

0
1
0
0
1

,

1
Hi-Z

1
1
0
0
0
1
1
0
1

VI

1

1
0

1
1
1
1
0
1
1
1
0
1
0
0
1
1

0
0
0
0
1

0
1
0
0
0
0
1
0
1
1

•

Hl·2

1
Hl·Z

X" Don't Care

The output levels are not shown on the truth table since the customer specifies the output condition he desires at each of the eight ou~puts
for each of the 32 words (256 bits). The customer does this by filling out the Truth Table on this data sheet, and sending it in with his
purchase order.
OUTPUTS

INPUTS

WORD

ENABLE

BINARY SELECT

A

ME

V8

Y7

V6

Y5

Y4

Y3

Y2

Y1

Hi·Z

Hi-Z

Hi-Z

Hl_Z

Hi-Z

Hl·Z

Hi-2

I.

11
12

."
14

15

1·

•

16
17

,.
18

••

20
21
0

22
23
24

25
26
27
28
29
3D

31
Hi·Z

Xm O-

C

35

50 1-+-+~I-+-+-1-+--;

30
25

CO

"-

40

35

~

ut(0

Delay from Enable to Low
Impedance State

-

I--

Y

'LZ

:!
>-

~

IS

30
20

10
,",

10

5

---

40

--

30

II-

tpHL

tLHI

-:;

"
>-

g

III

20
IS

i--"
i--

-

5

-75 -50 -25

0

25

50

75

0'--'--'--'--'---'-'--'--'

100 125

-75 -50 -25

TEMPERATURE I'C)

TEMPERATURE I'C)

,......

-;::;

"H

10

0'---'--'--'--'---'---'--'----'

0'---'--'---'-.......-'--'--'----'
-75 .-50 -25 0 25 50 75 100 125

25

0

25

50

75 100 125

TEMPERATURE I'C)

ac test circuit and switching time waveforms

BISELECT
NARY 30V ~',V - - - - 'f:'V
ov-.J

Vee

,j

YO"

TEST
POINT

R,

' - ____ _

....

~5V

OUTPUT

FROM

'"'"1,-f.5V

vo,~~--~'-------'

OUTPUT

UNOE-R

...

TEST

~r'

~,

1.Uk

J.GV

,
,

r\'v

ME
OV
",-1_5V

-

/'.5V

'" ic-!

\

OUTPUT
VOL

CL indudes probe and jill i:lIIpilcitanal.
All diodes ill!.' lNlOB4.

V""
OUTPUT

,..1.5V

-

tLZ - - :

O.SV

1\1

k

Ij

L..-

1m

V..l.
J

O.SV

~

n.sv

t

-

I",

Note: Input waYflfotrns are supplilHi by pulse gener.tturs
having the following characteristics: t n ::; 10 os, ts::; 10ns.
PRR s: 1.0 MHz and ZollT '" 5011.

ordering instructions
interpreted by
program. This
program data;
table should be

Programming instructions for the DM7598/DM8598 are
solicited in the form of a sequenced deck of 32 standard
80-column data cards providing the information
requested under "data card format," accompanied by a
properly sequenced listing of these cards, and the supplementary ordering data: Upon receipt of these items,a
computer run will be made from the deck of cards
which· will produce a complete function table of the
requested part. This function table, showing output
conditions for each of the 32 words, will be forwarded
to the purchaser as verification of the input data as

the computer-automated design (CAD)
single run also generates mask and test
therefore, verification of the function
completed promptly.

Each card in the data deck prepared by the purchaser
identifies the word specified and describes the levels at
the eight outputs for that word. All addresses must
have all outputs defined and columns designated as
"blank" must not be punched. Cards should be punched
according to the data card format shown.

7-47

s:CO
U'I

(0

CO

ordering instructions (con't)
SUPPLEMENTARY ORDERING DATA

Col. 26-29: Blank

Submit the following information with the data cards:

Col. 30: Punch "H" or "L" for output Y3.

a)
b)
c)

Col. 31-34: Blank

Customer's name and address
Customer's purchase order number
Customer's drawing number

Col. 35: Punch "H" or "L" for output Y2.

The fo!lowing information will be furnished to the
customer:
a) National's part number
b) National's sales order number
c) Date received

Col. 36-39: Blank
Col. 40: Punch "H" or "Li' for output Y1.
Col. 41-49: Blank

DATA CARD FORMAT

Col. 50-51: Punch a right·justified integer representing
the current calendar day of the month.

Col. 1-2: Punch a right-justified integer representing
the positive-logic binary input address (00-31) for the
word described on the card.
.

Col. 52: Blank

Col. 3-4: Blank

Col. 53-55: Punch an alphabetic abbreviation representing the current month.

Col. 5: Punch "H" or "L" for output V8. H = highvoltage level output, L = low-voltage level output.

Col. 56: Blank

Col. 6-9: Blank
Col. 10: Punch "H" or "L" for output Y7.

Col. 57-58: Punch the last two digits of the current
year.

Col. 11-14: Blank

Col. 59: Blank

Col. 15: Punch

"H'~

or "L" for output Y6.

Col. 60-61: Punch "OM,"

Col. 16-.19: Blank

Col. 62-66: Punch "7598~' or "8598."

Col.20: Punch "H" or "L" for output Y5.

Col. 67-68: Blank

Col. 21-24: Blank
Col. 69-80: These columns may be used for any customer information or identification.

Col. 25: Punch "H" or "L" for output Y4.

7-48

o

Bipolar ROMs U1...,s:

~

Advance Information

C/)

N

o

N

NAnoNAL

.......

o

DM75S202/DM85S202 TRI-STATE® 2048-bit ROM with output latches

s:00

U1

(J)

N

o

general description

features

These TTL compatible memories are organized as 256
words by 8 bits. When the strobe input is at a logical
"1" level the memories function in the conventional
manner with the enable input d·etermining whether the
outputs present the contents selected by the address
inputs or are turned "OFF."

• Schottky clamped for high speed systems

N

• High speed
Address to output delay
Enable to output delay
Strobe to output delay

35 ns
15 ns
20 ns

• PNP inputs reduce input loading

When the strobe input is at a logical "O"the outputs
are latched into the state they were in just prior to the
strobe going low. The outputs remain in this condition
until the strobe is again taken to the logical "1" state
regardless of the state of the address or enable inputs.

• Output latches simplify system use
• 20 pin, 300 mil package for high density
• Pin compatible with DM54S271/DM54S371

logic and connection diagrams

ADDRESS
INPUTS

0-:-

.

ADDRESS
BUFf.ER
AND
DECODE

0-

..

..

..

f-

l,-

f-

256 X 8
ARRAY

8:81T
LATCH

f-

f-

8 DUTPUT
DRIVERS

I

I

.

OUTPUTS

f-o

f-

STROBE

~

D TYPE
LATCH

ENABlE<>--O

DuaH n-Line Package

T
20

A6

A7
19

EN

AS

18

17

STRD8E DUTS .OUT7 OUT 6 DUTS
15

16

14

13

.......

I-

2
AD

11

12

AT

3
A2

4
AJ

6
A4

7

Tor VIEW

Order Number DM85S202N

See Package 16A

7-49

B

9

OUT lOUr 2 OUT 3 o.ur 4

.1'0
GNU

HI

N

o

N

(/)

absolute maximum ratings

operating conditions

(Note 1)

Il)

CO

~
C

"o
N
N

Supply Voltage (Note 2)
Input Voltage (Note 2)
Output Voltage (Note 2)
Storage Temperature Range
Lead Temperature (Soldering,10 seconds)

·-{).5V to +7 .OV
-1.2V to +5.5V
-{).5V to +5.5V
-65°e to +150o e
3000 e

Supply Voltage (Vee)
DM75S202
DM85S202
Ambient Temperature (T A)
DM75S202
DM85S202

(/)

~

~
C

dc electrical characteristics

Logical "1" Input Current

MAX

4.5
4.75

5.25

5.5

+125
+70

°e
°e

Logical "0" Input Voltage

0

0.8

V

Logical "1" Input Voltage

2.0

5.5

V

CONDITIONS

MIN

TYP

MAX
25

/1 A

Y'N = 5.5V

1.0

mA
/1 A

Y'N = 0.45V

-250

V CL

Input Clamp Voltage

liN. = -18 mA

-1.2

VOL

LOgical "0" Output Voltage

V OH

los

UNITS

Y'N = 2.7V

Logical "0" Input Current

DM85S202

V
V

-55
0

I'L

DM75S202

UNITS

(Note 2)

PARAMETER
I'H

MIN

10L = 12mA

V

0.50

V

0.45

V

Logical "1" Output Voltage
DM75S202

10H = -2.0mA

2.4

V

DM85S202

10H =-u.5 mA

2.4

V

Output Short Circuit Current

Va

=

OV (Note 3)

-30

-100

mA

-50

50

/1 A

100

165

mA

TYP

MAX

Vee = Max
loz

TRI·STATE Output Current

Icc

Maximum Supply Current

switching characteristics
PARAMETER

0.45V::; Va ::; 2.~V

(Note 2)

CONDITIONS

MIN

UNITS

tAA

Address to Output Delay

Strobe = "1"

35

ns

tEA

Time to Enable Output

Strobe

= "1"

15

ns

tED

Time to Disable Output

Strobe = "1"

15

ns

tSA

Strobe to Output Delay

20

ns

tsw

Strobe Pulse Width

10

ns

Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that
the device may be operated at these limits.

Note 2: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vec = 5.0V and TA
Note 3: During lOS measurement, on'lv one output at a time should be grounded. Permanent damage may other~ise result.

7·50

=

2SoC.

~

Bipolar ROMs
Advance Information

NAll0NAL

OM7678/0M8678, OM7679/0M8679 7x9 character generator
general description

features

The DM7678/8678 and OM7679!OM8679 are bipolar
character generators. A maximum of 64 characters can
be displayed in a 7X9 dot matrix. Shifted characters
can be generated by the on-chip subtractor. On-chip
line counter and parallel-in-serial-out shift register reduce
package pin·out.

•

TRI-STATE output

•
•
•
•
•

On-chip input latches

The clear input and the load input are active low. Load
is synchronous with the Dot Rate Clock. Both the line
rate clock and the dot rate clock are positive triggered.
When the strobe input receives a low signal, the character
address will be held at the inputs.

connection diagram

V~6

,

SELECT

A.

A5

Al

Serial output
20 MHz typical clock rate
Shifted characters

character display example

,
A6

•

On·chip line counter
On-chip shift register

DOT
CLOCK

[jj

0

DOT RATE CLOCK (SERIAL OUTPUTl _ _

15

13

"

12

10

11

9

, ••••••••
,, ••
, •
••••
,, •
•• •
0

LINE

COUNTER
CLOCK

I

,...

2

6
9

"""

"
""

ASCII CODED
ADDRESS INPUTS

1
A3
\

2

.

A2

3

4

Al,

5T

5
CLEAR

6

1

LINE

CLOCK

RATE

CONTROL

•
•••••••

I

000101

I

I

• ••

•••
••• •••
•••••
••••••

••••••••••

•••••

I

I 100111 I

I

100111

•
••••••

•••
••••

1101111

I

.1:

elK

SELECT

Order Number DM7678J, DM7679J, DM8678J
or DM8679J
See Package 10

Order Number DM8678N or DM8679N
See Package 15

electrical characteristics
over recommended operating free·air temperature range (unless otherwise noted)
DM76!86
CONDITIONS

PARAMETER

78,79

MIN
VOH

High Level Output Voltage

IOH ~ 2 mA,

VOL

Low Level Output Voltage

IOL

IIH

High Level I nput Current

IlL

~

Vee ~ Min

TYPO)

UNITS

MAX

2.4

V

Vee ~ Min

0.4

V

Vee ~ Max,

V'N ~ 2.4V

40

jJ.A

Low Level I nput Current

Vee ~ Max,

V IN

~

-0.8

mA

Icc

Supply Current

Vee ~ Max

100

fMAX

Maximum Clock Frequency

Vee ~ 5V, TA ~ 25°C

20

Notes:

cc ~ 5V, T A

16 mA,

0.4V

------....----------(11

All typical values are at V

= 2SoC

7-51

mA
MHz

0')

f"-

cc

logic diagrams

(X)

~

DM7678/DM8678

C

STROBE

........
0')

f"-

cc
f"-

141

"

~

C

(X)

f"-

cc

(X)

~

7·61T
p.l.s.a .
SHIFT

C

........

co
f"cc
,....

REGISTER
WITH
SYNCHA
lO.AD

54 X 9 X 1

ROM t 1
81TTOTAG

SHIFTED

~

CHARACTER

C

...J.1.I1!...--

.2

_ _ LOAD

{'I
1-_ _-''''''''' DOT RATE CLOCK
AI
TAG BIT

DM7679/DM8679
STROBE

{41

1·BIT

.

64

11.1.8.0.
SHIFT

REGISTER
WITH

64X 9 X 7
ROM+ 1
81T TO TAG

SYNCHR
LOAD

SHIFTED
CHARACTER

.,t!.2L lOAD
~DOT RATE CLOCK
TAG BIT

LINE RATE CLOCK

SUBTRACT
oOR 4
Note: ) (

CLOCK CONTROL

"5X {()\leniz€ CIH1tllctj mask option.

------------........
752

~

Bipolar ROMs

NATlONAL

OM76L9710M86L97 TRI-STATE®low power
1024-bit read only memory
general description

features

The DM76L97/DM86L97 is a custom-programmed
Read Only Memory organized as 256 four-bit
words. Selection of the proper word is accomplished through the eight select inputs.

•

Fu II tenth-power technology

•

Pin compatible with SN54187/SN74187

• Typical power dissipation

Two overriding memory enable inputs are provided
which when mask-programmed in one of· the
three options described will cause all four outputs
to read either the normal memory contents or
go to the high impedance state.

• Typical access time

75 mW
70 ns

• Custom-programmed memory enable inputs
• TRI-STATE outputs

logic and connection diagrams

.,

""nil We<: P,nI81·&ND

"

-,.~----

---'

Dual-In-Line and Flat Package
MEMORV
ENABLE

OUTPUTS

BINARY
Vee

SELECT ,H

ME.

ME,

Y,

Y,

Y,

Y.

Order Number DM76l97J
or DM86l97J
See Package 10
Order Number DM76l97N
or DM86L97N
See Package 15
Order Number DM76l97W
orDM86L97W
See Package 28

BINARV SELECT

TOP VIEW

7-53

absolute maximum ratings

operating conditions

(Note 1)

Supply Voltage

7.0V
I nput Voltage
5.5V
Ou tput Vol tage
5.5V
Storage Temperature Range
-65"C to +150"C
Lead T emperatu're (Soldering, 10 seconds)
300'C

electrical characteristics

Supply Voltage (V CC)
DM76L97
DM86L97
Temperature (T A)
DM76L97
DM86L97

MIN

MAX

UNITS

4.5
4.75

5.5
5.25

V
V

+125
+70

°c
°c

-55
0

(Note 2)
CONDITIONS

PARAMETER

TVP

MAX

Vee

Vee = Min

Min

Logical "1" Output Voltage

Vee = Min, 10 = -1.0 rnA.

Logical "0" Output Voltage
DM76L97
DM86L97

Vee = Min, 10 = 2.0 mA
Vee = Min, 10 = 3.2 rnA

Third State Output Current
DM76L97
DM86L97

Vee = Max, Vo = 2.4V
Vee = Max, Vo = O.4V

0.7

Logical "1" ,Input Current

Vee = Max, V ,N = 2.4V
Vee = Max, V ,N = 5.5V

Logical "0" Input Current

Vee

= Max, V ,N = 0.3V
= Max, Vo = OV

UNITS

V

2.0

Logical "1" Input Voltage
Logical "0" Input Voltage

=:

MIN

V
V

2.4

0.3
0.4

V

±40
±40

/lA
/lA

10
100

-6.0

V

/lA
/lA

-180

/lA

-30

rnA

20

rnA

/lA
/lA

Output Short Circuit Current (Note 3)

Vee

Supply Current

Vee = Max, All Inputs at GND

Third St?te Output Current

Vee
Vee

= Max, V OUT = 2.4V
= Max, V OUT = O.4V

+40
-40

Input Clamp Voltage

Vee

= Min, liN = -12 rnA
= 5.0V, C L = 50 pF

-1.5

V

15

Propagation Delay to a Logical "0"
From Address to Output (tpdo)

Vee
TA = 25'C

55

85

ns

Propagation Delay to a Logical "1"
From Address to Output (tpd 1)

Vee = 5.0V, C L = 50 pF
TA = 25'C

86

130

ns

Delay From Enable to High Impedance
State (From Logical "1" Level) (t ,H )

Vee = 5.0V, C L = 5.0 pF
TA = 25'C

15

23

ns

Delay From Enable to High Impedance
State (From Logical "0" Level) (tOH)

Vee = 5.0V, C L
TA = 25'C

= 5.0 pF

57

86

ns

Delay From Enable to Logical "1" Level
(From High Impedance State) (tH,l

Vee = 5.0V, C L = 50 pF
TA = 25'C

34

51

ns

Delay From Enable to Logical "0" Level

Vee = 5.0V, C L
T A = 25'C

47

70

ns

(From High Impedance S.tate) (tHai

=

50 pF

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits.
Note 2: Unless otherwise specified minImax limits apply ~cross the -55°C to +125°C temperature range for the DM76L97
and across the O°C to +70°C range for the DM86L97. All typicals are given for Vee" == S.OV and T A "" 25°C.

Note 3: Only one output at a t'ime should

b~

shorted.

7·54

ordering instructions
Programming instructions for the DM76L97 or
DM86L97 are sol icited in the form of a sequenced
deck of 32 standard 80·column data cards pro·
viding the information requested under data card
format, accompanied by a properly sequenced
listing of these cards, and the supplementary
ordering data. Upon receipt of these items, a computer run will be made from the deck of cards
which will produce a complete truth table of the
requested part. This truth table, showing output
conditions for each of the 256 words, will" be
forwarded to the purchaser as verification of the
input data as interpreted by the computer·auto·
mated design (CAD) program. This single run also
generates mask and test program data; 'therefore,
verification of the truth table should be completed
promptly.

10·13

1~

15-18
19
20-23
24
25-28
29

Each card in the data deck prepared by the purchaser identifies the eight words specified and
describes the conditions at the four outputs for
each of the eight words. All addresses must have
all outputs defined and columns designated as
"blank" must not be punched. Cards should be
punched according to the data card format shown.

30-33
34
35-38
39
40-43

supplementary ordering data

44

Submit the following information with the data
cards:
a) Customer's name and address
b) Customer's purchase order number
c) Customer's drawing number.

4548
49
50·51

data card format

52

Column
1- 3 Punch a right-justified integer representing
the binary input address (000·248) for
the first set of outputs described on the
card.
4
5· 7

8· 9

53·55
56
57·58

Punch a "-" (Minus sign)

59

Punch a right-justified integer representing
the binary input address (007·255) for
the last set of outputs described on the
card.
Blank

Punch "H", "L", or "X" for bits four,
three, two, and one (outputs Y4, Y3, Y2,
and Y 1 in that order) for the first ~ of
outputs specified on the card. H = high·
level output, L = low·level output, X =
output irrelevant.
Blank
Punch "H", "L", or "X" for the second
set of outputs.
Blank
Punch "H", "L" ,or "X'~ for the third set
of outputs.
"
Blank
Punch "H". "L". or "X" for the fourth set
of outputs.
Blank
Punch "H", "L", or "X" for the fifth set
of outputs.
Blank
Punch "H", "L", or "X" for the sixth set
of outputs.
Blank
Punch "H", "L", or "X" for the seventh
set of outputs.
Blank
Punch "H", "L", or "X" for the eighth
'
set of outputs.
Blank
Punch a right-justified integer representing
the current calendar day of the month.
Blank
Punch an alphabetic abbreviation repre·
senting the current mooth.
BlanK
Punch the last two digits of the current
year."
Blank

60-61

Punch "DM"

62·67

Punch the National Semiconductor part
number DM76L97 or DM86L97.

68-70

Blank

truth table
OPTION

ME,

ME2

1

0

0

1
X

X

High Impedance

,1

High Impedance

2

3

OUTPUTS
Normal

1

1

Normal

0
X

X
0

HiWi Impedance

"

0

High Impedance

,

Normal

X
0

X

High Impedance

x = Don tcare

7-55

High Impedance

~

Shift Registers

NAnONAL

MM400/MM500 series dynamic shift registers·
general description
The National Semiconductor line of dynamic shift
registers are built on a single silicon chip utilizing
MOS P channel, enhancement mod~ transistors.
Designed to operate over a wide frequency spec·
trum, these devices can be used in any sequential
digital system that employs a two phase clocking
system. The low threshold transistors used permit
operation with a VDO supply voltage of -1 OV and
a -16V clock amplitude to obtain these device
features:

• Minimum Operating
Frequency Guarantee

•

The power dissipation of the device decreases as
the operating frequency is decreased; at 10kHz
typical dissipation is 6 /lW/bit. The minimum
operating frequency is also reduced substantially
at lower temperatures; typical minimum frequency
of operation at 2SOC is 100 Hz.

Direct DTL or TTL compatibility

• High Frequency
Operation
•

'1 MHz guaranteed

Low Power
Consumption

0.8 mW/bit @ 1 MHz

600Hz @2SoC

•

Military and Commercial Temperature Ranges
MM400 Series
-SSoC to +12SoC
MMSOO Series
O~C to +70°C

•
•

Low Output Impedance (VOH )
SOOohms
Clock inputs directly compatible with MHOOO9,
two phase clock driver

Metal Can Package

schematic and connection diagrams

..------..----~~~--------~

·v~ -----r--~------~----+---

v.
Note: Pin 4 tonnected to case.
TOP VIEW

Ordar Number MM400H.
MM500H, MM401H. MM501H,
MM402H, MM502H, MM403H,
MM503H, MM406H. MM506H,
MM407H or MM507H
See Package 23

,
ClOCIt •• O"""S

tlOC:I[~ONPlMl

typical ap.plications
FIGURE 1 - TTL/MOS Intetiace- Low Fnoquency
(see clock timing graph for detail)

FIGURE 2 - TTL/MOS Interfaces

CLOCK Vi'll. 92 REOUlRE:MENTS WITH Vss:: +10V TVP.

CLOCK VQ,. 02 REnUlREMENTS WITH Vss :: +5V

LOGIC "0" (Vss ) = +I.5V
lo.~IC "1" (V ss - V¢d:: -6.DV

CLOCK REP. RATE 650 kHz TYP.

lOGIC "O"IVss) '" -t4.5V
LOGIC'T' (Vss -V¢d '" -lOY

Waveforms for Applications

Standard Ragistar Configurations
I
I

v

ClOCk.'V••

_:'~

CLaCK h

V. - - - ,

rf-,
I U1"""1Ur-'1ur

r-:"""1
U
U

Vn-V.

'3

CONFIGURATION

...

Dual 25 bit

Dual 50 bit

--d

• Dual 100 bit

TYPICAL DATA II lVa -l. iY1
I~
~.-UV),...............
I"

t

2OKOOUTPUT
OPEN DRAIN OUTPUT
_SS9Cto
_259C to -SS°C to -25"Cto
+JOcoc
+l25°C
+70°C
·+125"C

MM400
MM402
MM406

MM500

MM401

MM501

MM502

,MM403

MM506

MM407

MM503
MM507

I

TYf'lCAL DATA OUT

::~~:5.5.:T:"~l~.,555!i=:::tle=-55~\~___
::

tFor other length registers consult your National representative.
"For New Designs, See MM4006A/MM5006A Data Sheet.

8·'

en

II)

';:

II)

VJ
0
0

It)

::?!
::?!

......
0
0

.q-

::?!
::?!

absolute maximum ratings
+0.5V to -25V
+0.5V to -25V
+0.5V to -25V
500mW

Drain Voltage (-V 00)
Clock Inputs (ViP" ViP2)
Data Inputs
Power Dissipation (Note 1)
Operating Temperature
MM400 Series
MM500 Series
Stor~ge Temperature
lead Temperature (Soldering, 10 seconds)

-55°C to +125°C
-25°C to +70°C
-£5°C to +150°C
300°C

electrical characteristics

Clock I nput Capacitance
(Pins 3 & 5)

Data Output Voltage levels
MaS to MOS
logic "0" (V OH )

MIN

CONDITIONS

PARAMETER
Clock Repetition Rate

(Note 2)

See Fig. 2
See Fig. 1
I ~ ,1 .0 MHz, OV Bias
MM400, 401, 500, 501
MM402, 403, 502, 503
MM406, 407, 506, 507
-20V Bias
MM400, 401, 500, 501
MM402, 403, 502, 503
MM406, 407,506,507

Voo ~ GND, Vss ~ +lOV
Ireq ~ 1 MHz max.
Input (d.c.)

logic "0" (V a H )
logic "1" (VOL)

IL ~2.5mA}s N
6
ee ate
IL ~ -1.6 rnA

Breakdown Voltage
On Pin 1
On Pin 2 (Note 3)
On Pin 6 (Note 3)
On Pin 7
leakage Current
Pin 1
Pin.2 (Note 4)
Pin 6 (Note 4)
Pin 7
Pin 8 (Note 4)
Power Supply Current Drain

Vss = +5V
(Vss ~ 4.75 min)
Ireq = 0.5MHz max.
IL ~ 2.5 mA }
IL = -1.6 mA See Note 6
V o ",

UNITS
MHz
MHz

22
40
85

40
60
100

pF
pF
pF

lB
32
55

25
40
65

pF
pF
pF

Vss -1.5

V
V

Vss -B.OV

MaS to TTL (Fig. 1)

logic "0" (V a H )
Logic "1" (VOL)

MAX
1.0
0.5

Voo ~ -10V, Vss ~ GND
Ireq ~ 1 MHz max.
Input (d.c.)

logic "1" (VOL)

MaS to TTL (Fig. 2)

TYP

See Note 5
See Note 5

0.4

V
V

004

V
V

2.5

= -5V,

1.0 Ill", Test Current
TA ~ 25°C
GND on Pins 2,3,4,5,6,7
-BV on Pin 8
GND on Pins 1, 4, 6, 7, B
-8V on Pins 3, 5
GND on Pins 1, 2, 4, 7, 8
-8V on Pins 3, 5
GND on Pins 1,2,3,4,5,6
-8V on Pin 8
TA = 25°C
V, ~ -lBV, Va ~ -8V
All Other Pins at GND
V 2 = -lBV, V3 = Vs = -8V
All Other Pins at G N D
V6 = -18V, V3 = Vs = -BV
All Other Pins at GND
V 7 = -lBV, Va = -BV
All Other Pins at GND
Va = -BV
All Other Pins at GND
Outputs at logic "1"
1 MHz Operations, T A = 25°C
(iP, = OAl1s, iPz = 0.2 115 )
MM400,401,500,501
MM402,403,502,503
MM406,407,506,507

8·2

2.5

-25

V

-25

V

-25

V

-25

V

4.5
9.0
18.0

0.5

I1A

0.5

I1A

0.5

I1A

0.5

I1A

0.5

I1A

9.0
14,0
30.0

mA
(Average)

3:
3:

.,.

electrical drive requirements
PARAMETER
Clock Pulse Width
, Clock pw
2 Clock pw
Clock Delay, , t~

CONDITIONS

MIN

0.4
0.2
See Definition

MAX

UNITS

10.0
10.0

/.IS
/.IS

0.1

/.IS
0.05
0.5
5.0

1 MHz, H)
Logic "I" (Vo/>L)
Data Pulse Width tdw
Data Setup Time t",
Data I nput Voltage Levels
MOSto MOS
Logic "0" (V'H)
Logic "," (V'L)
TTL to MOS (Fig. 1)
Logic "0" (V 'H)
Logic "I" (V,d
TTL to MOS (Fig. 2)
Logic "0" (V'H )
Logic "I" (V'L)

TYP

See Timing Diagram

Vss -14.5

Vss -0.5
Vss -16.0

Vss -1.5
Vss -18.0

0.4
0.1

-7.0

Voo = GND, Vss = +10V
freq = , MHz max.

Vss -7.0

Voo = -5V, Vss = +5V
(Vss = 4.75 min)
freq = 0.5 MHz max.

Vss -4.2

V
V
/.IS
/.Is

2.0

Voo = -10V, Vss = GND
freq = , MHz max.

/.IS
/.Is
/.Is

V
V

Vss

2.0

V
V

Vss

1.5

V
V

Note 1: For operating at elevated temperatures, the device must be derated based on a +150°C maximum junction temperature and a thermal
resistance of +150°C/W junction to ambient. The full rating applies for case temperatures to +12So C for MM400 Series and +70D C for
MM500 Series units.

Note 2: These specifications apply over the indicated operating temperature ranges fo'r VSS = OV and -11V < VDO < -9.5Vand 20 kn
connected between pins 2 and 8 and between pins 6 and 8 without measl,lrement load of less than 10 pF in parallel with' 10 Mn to ground
unless otherwise specified. On the MM401!MM501. MM403/MM503, and MM407/MM507 optional versions which include 20 k.Q. pull-up
resistors internal to package., the external 20 kn resistors are not used in measurement circuits.
Note 3: For the odd number devices, MM401, MM403 and MM407, the output of pins 2 and 6 will exhibit a resistance when measured with
the following bias conditions: pins 1.6 and 8 '" GND: pins 3 and 5 -- -16V; pin 4 open; meaSUre pins 2 and 6 = 25k s:. ROUT ~ 15 kn.
Note 4: Not for internal resistor devices,
Note 5: See minimum operating, fre.quency graph.
Note 6: In the logic "0" 1VOHI level the MOS register output will be sourcing 2.5 rnA into the load combination of the pull-down resistors
and the gate leakage current. In the logic "," VOL level IL represents the current that the pull-down resistor and the internal 20k resistor
combination will sink in order to insure current sinking capability for one gate.
.
=;;

operation

timing diagram

Each bit of_delay shown in the circuit ,schematic consists

of two inverters Tl and T4 accompanied bv clocked load
resistors T2 and T5 and two coupling devices T3 and T6.
The circuit fu'nctions as follows: When <1>2 goes negative
(one state) the coupling unit TA and the load resistor

T2 are clocked ON allowing information at· the input to

~.:'g t~".:'~~~r~a~ gfo~~e~n~~ri~o;r~x~~p~~,~n ~::::~;
potential (near -VOO leveil is transferred from the input
to the gate to source capacitance at node A, then T1
-Voo
turns ON allowing node F to ,be at --2-' When 0/>2 re-

turns to its zero state (ground level) T2 turns OFF allowing node F to discharge to zero Volts. When 0/>, goes nega·
tive (one state) the coupling, unit T3 and the load re-

sistor T5 are clocked ON allowing information at node F
NODE B

to be transferred to node B. T4 is held OFF if node F was
at ground potential and is turned ON if node F had been
at .,.V DO potential. Continuing the example above, T 4 is
held OFF and node G is at -Voo since T5 is ON during
0/>1 clock pulse. When <1>, returns to its zero state, node G
maintains a -VOD voltage level. This voltage level is

NODE C

maintained at node G until the "'2 clock appears. The

bit delay demonstrated in this example is repeated
through each half of the dual register.

DATA
OUTPUT

I

8·3

0
0

.......

3:
3:

UI

0
0

.

C/)
CD

(i'
til

performance characteristics
Minimum Operating Frequency

Power Dissipation vs Maximum Frequency
1000

10K'

~TA • 25'C

t-voo - 10V
~
.§ 100 f-V,=-16V -

~

L~~6

~

!>-

;;:

:in

10

M~02

t--

'"

u

C)

MM400:

'"~

v.:

~

2K

~
:;:

:z

20
0.1

1,/

I.....

1/

i'/

-20

OPERATING FREIlUENCY (kHd

~

1.4

...

1.2

.§

12

~
;;:

1.0

~C>

1.0

0.8

:

0.8

ili

0.6

;;:

ili
C
'"

C

'"

~

0.4

~

0.2

5.0

>u

z

::>

~

".
'"

r- ~:~~

3.5

ff-

l.O

r-

4.0

1.0
1.5
2.0
2.5

q"

0.<
0.3
0.2
0.15

. .,

0.2
0.2
0.2
0.15

2.5

1.0

0.1
0.05
0.05
0.05

~

...

-5

-6

-7

-8

~~

~~

S
C>

4.0

>

~

!:

0.6

3.0

;!
~

0.<

-I.

-12

-16

2.0

ons

-20

-18

UNITS l -

"'

ff-

"'
I "'
"J.- I -

~~

~

..........
400

r-.....

~
.§

...

.........

;::

:

r-.....

~~

~
o
-25

Note: All typical performance data is gathered with ¢pw

0.6 jJS 0.8 ps

1 ps

r-..,..--.-.,.......,..~~~~~

1.4

1.2

S

1.0

~

0.8

~

0.2

ili 0.6
C
'" D.'
~

'"

VIP,' V4J2 {VOLTS)

ItS

0

ili
c zoo

.1 I

~~

...

400

Power Dissipation/Bit vs. Temperature
1.8

~
.§

200 ns

CLOCK 41, WIDTH

600

FANOUT: ONE REGISTER INPUT LOAD
~y

5.0

..

Maximum Package Power Dissipation

Voo'" -tOY
TEMPERATURE: 25°C

~

w

CLOCK AMPLITUDE (VOLTSI

..... '41

2.0
1.5

-3

0.2

-12

-11

Clock Amplitude V"", V"'2
vs. Maximum Frequency

'"

-2

~

Von (VOLTSI

~

-1

Clock Timing. Direct·Coupled TTL or DTL

.

0
-10

-9

<.5

o

o1J.TPUT VOL TAGE (VOLTS) (BHoW Vssl

1.8

~

:

o itjt::::±::±::±:::::b:::b~
140

Power Dissipation/Bit YS. Clock Amplitude

1.8

...

1
100

60

20

TEMPERATURE rCI

Power Dissipation/Bit YS. Supply Voltage

.§

Voo ::: -10V
V~l =V¢2 =-t6V

1/

10
-60

1000

100

10

TYPICAL

200
50

V

1/

500

100

j,..

GUARANTEED

IK

Output Sink/Source Current
I

V

1

5K

Z5

15

1Z5

-25

=:

0.4 IJ; ¢2pw = 0.2 IJS; tPd

8-4

0

25

75

125

TEMPERATURE rCI

TEMPERATURE ('CI
=

0.1 J.ts; f

=:

1 MHz; except as otherwise noted.

~

Shift Registers

NAll0NAL

MM404/MM504 dual16 bit static register*
MM405/MM505 dual 32 bit static register*
general description
The National Semiconductor line of MOS static
shift registers are monolithic integrated circuits
utilizing P-channel enhancement mode transistors_
The use of a low threshold technology permits
operation with a V OD supply voltage of -10 volts
and a V GG supply and clock amplitude voltage of
less than -16 volts_ These registers require only a
single clock input to operate from DC to 1 MHz
in either synchronous or asynchronous systems.
Each register cell is designed specifically to avoid
race conditions during latching, thus insuring
operation under all conditions specified in the
electrical characteristics_

connection diagram

Additional features include:
•
•
•
•
•
•

Bipolar compatibility
Single phase clock input
High frequency operation
1.0 MHz
Low power consumption
1.7 mW/bit typ
Output impedance (V OH )
!?(lOn typ
Militaryand commercial temperature ranges
MM404, MM405
_55°C to +125°C
MM504, MM505
O°C to +70°C

Metal Can Package

v~

Note; Pill 4 connected to case
TOP VIEW

Order Number MM404H; MM504H,
MM405Hor MM505H
See Package 23

typical applications

2N Bit Johnson Counter

TTL/MOS Interface

Voo

GND

: .:
D+
-t
I

8

DIVIDE BY

I

2N OUTPUT

6 I

9

I

I

L ___ ,- __

CLOCK V¢l, REQUIREMENTS WITH Vss '" +l'OV

I

I

.'

N'ote: Clear register to all "0" before

lOGIC "()" ~ Vss -1.5V
lOGIC"'" "Vss -16V

counting bV applying "1" to clear input
and clocking thfOUgh 2N clock j:ycles.

Waveforms for Applications

Single 2N Bit Register
I
CLOCK ¢

_,::'

I

DATA OUTPUT

Z5V~
__\\;;
......

TYPICAL OATA IN

~1.·0V

TYPICAL DATA OUT

~:::

;;/-I__~"'===="""
I

'For New Designs, .eeMM4040/MM5040, MM4050AlMM5050A.

U
I

N BIT DELAY

L

absolute maximum ratings
+O.5V
+O.5V
+O.5V
+O.5V

to -25V
to -25V
to -25V
to -25V
300mW
_55°C to +125°C
O°C to +70 oC
_65°C to +150°C

Drain Voltage (V aa )
Gate Voltage (V GG)
Clock I nput (V 1> 1 )
Data Inputs
Power Dissipation (Note 1)
Operating Temperature MM404, MM405

MM504, MM505
Storage Temperature

electrical drive requirements

(Note 1)

CONDITION

PARAMETER

MIN

Clock. pulse Width
¢, Ctock, tP,pw

0.4

Clock Pulse Risetime, tr¢c

Falltime.

tf4lo

1 MHz With

¢pw ::

100 kHz with

10 kHz with

~s

0.6

~s

10 j.J.s

2.0

~s

Vss -14.5

td$

tdh

electrical characteristics

Clock Line Capacitance

vss -1.5

V

Vss -18.0

v

vss -2.5
Vss -7.0

V
V

0.2

~s

0.03

~s

MIN

Fan-Out "1"

TYP

MAX
1.0

de

Data Output Voltage Levels
Logic "VOH"
logic "VOL"
Data Input Capacitance
lEach Input~

vss -0.5
Vss -16.0

(Note 2)
CONDITION

PARAMETER

Clock Repetition Rate

vss -L5
1.5

f '" 1 MHz
=

UNITS

MHz

v
V

Vss -8-0
V IN

~s

2 J.l.S

Data Input Voltage Levels
Logic "V 1H
Logic "V 1L "
Data Hold Time.

UNITS

0.05

¢pw '"

4>pw '"

MAX
10

0.4 f.1.s

Clock Input Level
Logic "VIfJH"
199ic "V4lL "

Data Setup Time,

TYP

3.0

pF

OV

f '" 1 MHz, -20V Bias MM404. MM504
OV Bias

Output Impedance

Outputs at Logic "0"

I nput Leakage Current
Pin 1

T A"" 2SoC

9.5

MM405, MM505

18

15
30

pF
pF

MM404, MM504
MM405. MM505

15.0
25

20
40

pF
pF

0.5

V 1N -= -18V

1.0

kll

0.5

IJA

10.0
15.0

rnA
rnA

All Other Pins at GND

Power Supply Current Drain
(V oo )

Outputs at Logic "0"
1 MHz Operation
T A'" 25°C
MM404, MM504
MM405. MM505

5.5
10.0

Nate 1: For operating at elevated temperatures, the device must be derated based on a +150°C maximum junction
temperature and a thermal resistance of +150°C/W junction to ambient. The full rating applies for case temperatures
to +125"C.
Note 2: These specifications apply over the specified temperature ranges for -11V < VOO < -9.5V, and -18V < VGG
< -14.5V and clock repetition rate of 10 kHz with output measurement load of less than 10 pF in parallel with 10 Mn to
ground unless otherwise sp~cified.

8-6

performance characteristics
Power Dissipation vs VOO

3'

3.0

....

~

.
.
j:

2.0

!!.

t!

~

i--'"

i""'"
I""'"

is

1.0

-- ---

I

~~

.!
Q

power Dissipation vs Temp.

Power Dissipation vs VGG

j,oc ~

1o-7,'1~oC _

~

f-

~.o~

VGG " -16V
V¢ '" -16V
fRED" 10 kHz

-9

VGG ,-14V
I--+~I--+Voo -9V

-I.

-11

-10

-18

-1&

-55

25

125

TEMPERATURE

VDO

'c

Max. Frequency vs SuPPly Voltages

VOUT vs Load Current
1&

2.2

14

!·o. p

12

.....

V

V

--

~

~

1.8

....

1.4

;

4K EXTERNAL

~SINKI

. /~

1.6

~
;;;

/
I- L

2.0

"

~

V

1.2

/

/

1.0

V

V(/J"'0.4J,1sectil MHz
Vrp '" 0.3 J,l5ec ~ 1.S MHz
V(/J" O.2#L* $2.0 MHz

Voo =-lOV

r

I I I

-16

-14
VOUT

-20

-18

VGG & vrp (Volts)

operation
A diagram of a one-bit static register employing
two clock phases (,;P) is shown in the schematic.
The register requires only one external clock phase
( turns T '9
"ON" generating the complement of , that is 
and in turn 1) is used to turnT 6 and T7 "OFF".
This action allows the register's previous inforrna~
tion to be temporarily stored on the gate to source
capacitance C3 of T 8' The output at node E during this timing sequence remains unchanged. However, during 1, time, clock  returns to ground;
concurrently 1) goes to a logic "1" level turning T,
"OFF" allowing T6 and T7 to .turn "ON". The
information which was previously stored on the
gate of T 8 discharges to a logiC "0" level causing
the output at node E to switch to a logic" 1" level
thereby obtaining the required one-bit of delay.

timing diagram.
t 10

I

1 I

11 I

ii,

I I

I I

I I

I I

I, II II~

I

ir-=l.~:~ I~ !r~ g~""-iR~fG%l~
!'7'

""""\
I/>

1

9,",

.~
I

INPUT DATA

I'
OODE.

--4" 1"--'•. : I

---+----;.'
.

I

"1 I

I

I I

. -,-1 ~'"
II.

ir-----t

1

I·

1'-1--;' :

I~

I :

I I

I I

I I

NODE I

000,,--:---1
: :;----y;

Irf---\ :

1

~

'DPED~
I

I I

I I

I

, : ' I

I I

IIIODE E

-----loNE liT DtlAvt---

I

NDDEG.

• 11-1 DELAV . . •

,

I

I I

I,

I I

.~
,

8-7

I I·

I I

~
.

DATA OUTPUT •... fI 'IT DELAY

1

I I

I I

~

Shift Registers

NAll0NAL

~
~

MM1402A. MM1403A. MM1404A. MM5024A
1024-bit dynamic shift registers

~

general description

....

The MM1402A,MM1403A,MM1404A,MM5024A
1024-bit dynamic sh ift registers are MOS monolithic integrated circuits using silicon gate technology to achieve bipolar compatibility. 5 MHz
data rates are achieved by on-chip mUltiplexing.
The clock rate is one-half the data rate; i.e.,
one data bit is entered for each 1 and "'2 clock
pulse.

• Seven standard configurations
Quad 256·bit
MM1402AD
Quad 256·bit
MM1402AN
MM1403AH
Dual 512-bit
Dual 512·bit
MM1403AN
Single 1024·bit
MM1404AH
Single 1024-bit
MM1404AN
Single 1024-bit with
MM5024AH
internal pull-down resistor

All devices in the family can operate from +5V,
-5V. or +5V. -9V power supplies.

applications

features

•
•
•
•
•
•
•
•

Radar and sonar processors
CRT displays
Terminals
Desk top calculators
Disk and drum replacement
Computer peripherals
Buffer memory
Special purpose computers-signal processors,
digital fiI~ering and correlators, receivers, spectral compressors and digital differential analyzers
• Telephone equipment
• Medical equipment

• Guaranteed 5 MHz operation
.1 mW/bit at 1 MHz

•

low power dissipation

•

DTl/TTl compatible

•

low clock capacitance

125 pF

•

low clock leakage

:s:; 1 IlA

•

Inputs protected against static charge

• Operation from +5V, -5V Or +5V, -9V power
supplies

connection diagrams
Metal Can Package

Metal Can Package

Metal Can Package

'00

v~

v~

TOP VIEW

TOPvrEW

Order Number MM1404AH
See Package 23

Order Number MM5024AH

v~

TOP VIEW

Order Number MM1403AH

See Package 23

See Package 23

Dual-tn-Line Package

Dual-In-line Package

INPUT4

Nt
INPUT 1

.~

Dual-In-Line Package

151\1C

,

OU1PUT4

OUTPU12

Nt

,

12"01:1

NO

INPUT 3
OUTPUT 3

IIIIPU12

¢,

INPUT1

"
'00

TOPVIEW

Order Number MM1402AD

Order NumberMM1403AN

Order Number MM1404AN

See Package 3

See Package 12

See Package 12

Order Number MM1402AN
See Package 15

8·8

3:
3:

absolute maximum ratings

~

~

0

Data and Clock Input Voltages and Supply
Voltages with Respect to V ss

N

+0.3V to -20V
600 mW at TA = 2SOC
O°C to + 70°C
-65°C to +160°C
300°C

Power Dissipation
Operating Temperature, Range
Storage- Temperature Range
Lead Temperature (Soldering, 10 sec)

!>
3:
3:
~

~

e lectrica I cha racteristics
T A = -25°C to +70°C, Vss = 5V ±5%, V DO = -5V ±5% or -9V ±5%, unless otherwise specified.
PARAMETER

CONDITIONS

MIN

Data Input Levels
"Logical Low Level (V,d
Logical High Level (V IH)

MAX

UNITS

Vss -10.0

Vss - 4.2

V

Vss~1;7

vss ·+ 0.3

V

<10

500

nA

5

10

pF

Vss -15
Vss +0.3
Vss -12.6
Vss + 0.3

V
V

Data Input Leakage Current
Input Capacitance
Clock Input Levels

TVP

0

Co)

Voo=-5V±5%

Logical Low Level (V t;6d

Logical High Level IV~HI
Logical Low Level IV.cI
Logical High Level IV~H I

Vss -17
Vss-l
Vss -14.7
Vss-l

Voo "" -9V ± 5%

V

!>
3:
3:
~

~

0

~

!>
3:
3:

V

.~

Clock Leakage Current

Min V¢L. TA = 25°C

10

1000

nA

N

Clock Capacitance

V~ =

90

125

pF

»

Vss

Data Output Levels
Logical Low Level' (V ad

Logical High Level IVOHI
Logical Low Level

(Vod

Logical High Level IVOH I
logical High Level (V OH I
Logical High level (V OH )
Power Supply Current (100)

RL1 = 3k to V OOI tOL = 1.6 rnA, Voo = -5V 1: 5%
R L1 ::: 3k to Voo. IOH::: 100 lolA
RL1 :::; 4.7k to Voo. IOL ::: 1.6 rnA. Voo == -9V ± 5%
Ru = 4.7k· to V oo , lOH = 100.uA
RL2 ::: 4.7k to VDO , Voo:::;; -5V ± 5%
RL2 = 6.2k to Voo , Voo = -9V ± 5%
RL3~ 3.9k to Vss

2.4
2.4
Vss -1.9
Vss - 1.9

TA = 25°C, Voo = -5V ± 5%
Output Logic "0", 5 MHz
Oala Rate, 33% Duty Cycle,

Continuous Operation, VrJ>L

==

-0.3
3.5
-0.3
3.5
Vss - l
V ss - l

0.5

V
V

0.5

V
V
V

~

V

35

50

rnA

30

56
40

rnA
mA

<10

1000

Vss - 17V

TA =()"C
T A ::: 25°C. Voo = -9V 1:5%
Output at Logic ''0''. 3 MHz

Data Rate, 26% Dl,lty Cycle,
ContjnuQusOpera.tion. VrJ>L "" Vss - 14.7V
45

TA = O°C
Data Output Leakage Current

V OUT = O.OV, TA =2SoC, V., = V~2
All Other Pins +5V

Internal Resistor (MM5024A)

TA

Output Capacitance

V OUT

=25°C

ac characteristics T A

:::

3.7

Voo = -5V ± 5%

Note 1

Data Frequency
Clock Phase Delay Times 14>d, ;Pdl

Voo = -9V ± 5%
MIN

MAX
2.5

..

Note·'

5.0
0.130
10

Clock ·Transition Times (q'>t f .4>tf)

Data Input Delay Time ('tQ,)
Data Input Hold Time (tdH)
Data Ol!tput Propagation Delay

5.2
10

mA
nA

kn
pF

= -o°c to +70°C, Vss = 5V ±5%

MIN

Clock PulseWidth 14> pw l

4.7
5

Vss. f "" 1 MHz

PARAMETER

Clock Frequency 14>,1

=Vss -10V,

10

Note 1

0.170
10

1000

UNITS

MAX
1.5

MHz

3.0

MHz

10

Note 1

I"
ns

1000

ns

30

60

ns

20

20

ns

90

110

ns

Note 1: Minimu·m clock frequency is a function of temperature and clock phase delay times, ¢d and ~d as shown by the ~f
v.ersus temperature.and tPd, iPd versus temperature curves. The lowest guaranteed -clock frequency Can be attain·ed by making
tPd,equal to ifid- The minimum guaranteed clock frequency is:
¢llmin) " l/(4)d + tf «
e;

-68

TA - AMBIENTTEMPERATURE (OC)

-20

20

60

100

TA - AMBIENT TEMPERATURE rC)

switching time waveforms
BIT TIMES

I

BIT 1

I

BrT2

I

8113

I

BlTa

I

I.

I

..

LJ I
"1"

DATA IN

I I
LJ I LJ I LJI LJ I LJ I
I I I I I I I I I I
I

I

I

I

~DATAINI
1
2
"0"

I

I

I

I

I

I

I

"0"

fF1
"1"

I

I

I

I

I
"1"

I

I

I I I

U-

I

I
I

I I

I

"1"

DATA IN
3

I

I

DATA OUT

Shown is a simplified illustration of the timing of a 4-bit multiplexed register showing
input output relationships with respect to the clock. If data enters the register at ¢,
time, it exists at ¢, time. (Beginning on ¢"s negative going edge and ending on the
succeeding ¢2's negative going edge.)
8-10

timing diagram
BITN+1

BIT 1+2

BITt

BITZ

100[]- r - - - - - - ' - - - - VOH

I.

T1

I

"

CLOCK

I

I

1-

iI

I

-+i":Ir-------r-'

CLOCK

I'

II

I

I

CLOCK PERIOD

""-1-::

.

8ITN

BIT2

BIT 1

::

90%-1II --

:

.~ --I

1-;
I
i-I ""

\.___
IN BIT t

L--------

V

liD'
II
---I
.~

r--

I
I
I

:

I-OATA PERIOO-i

I

r-

II

I

II

"'--J ,!....
I

90\1

I

I

10%

I I
I I
.... --,--1

--

--.l

: :

r------------~~---------r4-----,------~
I

IN BIT 2

tpdH _ :

I

:__

VL

__\:--

tpdL

-;:;:;;U:;-------------------U----------l
:t:':-:--=:~VABnVEGNDIVDD)
_______________
\______ i'----VOL
~II,-------...J.

OUTRllf

8·11

OUTBIl2

~

Shift Registers

NAll0NAL

MM4001A/MM5001A dual 64-bit dynamic shift register
MM4010A/MM5010A dual 64-bit accumulator
general description

features

The MM4001A/MM5001A dual 64-bit dynamic
shift register is a monolithic MOS integrated circuit utilizing P-channel enhancement mode low
threshold technology. The device consists of two
64-bit registers with independent .two phase clocks
and is guaranteed to operate at a 2.5 MHz operating frequency for CRT display applications.

•

High frequency operation

•

Low power consumption 0.4 mW/bit at 1 MHz

•

DTLlTTL compatibility

•

Minimum operating frequency

The MM4010A/MM5010A is a dual accumulator
function capable of operating at very high 'frequency. The device is also constructed on a single
silicon chip utilizing MOS P·channel enhancement
transistors. With the recirculate control line at an
MOS logic "0" state, the 'device functions as an
accumulator. A logic "1" state at the recirculate
control line allows external information to enter
the register serially. It is important to note that
recirculation of data is performed internally, inde·
pendent of the output circuit thus making it
insensitive to output loading.

• Application versatility

+5V, -12V power
su ppl ies, push-pull
output stage
guaranteed
250 Hz at 25°C
"Spl it clock" operation, independent
control of each
register for
MM4001A/MM5001A

applications
• Business machine
• CRT refresh memory
• Delay line memory
• Arithmetic operations

connection diagrams
Metal Can Package

3.3 MHz typ

load control truth table
Metal Can Package

v.

MM4010A/MM5010A

LOGICAL HIGH LEVEL
IVLCHI

LOGICAL LOW LEVEL
IVLCLI

Recirculates" old" data

Loads "new" data

v.

Note: Pin 5tonnectedtocase.

Note: Pin 5 connected to

1:a$E!.

TOPtllEIY

TOP VIEW

Order Number MM4001AH
orMM5001AH
See Package 24

Order Number MM4010AH
'or MM5010AH
See Package 24

typical applications
MM4010AlMM5010A TTL/MOS Interface

MM4001A1MM5001A TTL/MOS Interface

...,

8·12

absolute maximum ratings
Voltage at Any Pin
Operating Temperature Rang~
MM40 1OA/M M4001 A
MM5010A/MM5001A
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)

Vss + 0.3V to Vss - 22V
_55°C to +125°C
O°C to +70°C
_65°C to +150°C
300°C

electrical characteristics
T A within operating temperature range, Vss

= +5.0V

PARAMETER

±5%, V GG

CONDITIONS

= -12.0V ±1 0%,
MIN

Data Input Levels
logical HIGH Level (V. H )
Logical LOW Level (V.d

TYP

Vss - 2.0
Vss - 18.5

Data Input. Leakage

V IN = -20V, T A'=' 2Soc
All Other Pins GND

Data Input Capacitance

VIN "" D.DV, f =:: 1 MHz,
All Other Pins GND

unless otherwise stated.
MAX

UNITS

VS !? + 0.3
Vss - 4.2

V
V

0.01

0.5

MA

3.0

5.0

pF

Note 2
Load Control 1nput levels
Logical !"iIGH Level (VLCHJ
Logical LOW Level (V Lcd

Vss + 0.3
Vss - 4.2

Vss - 2.0
Vss - lB.5

Load Control Input Leakage

VIN = -20V, T A. '" 25°C
All Other Pins GND

Load Control Input Capacitance

VIN ;:: O.DV;.f '" 1 MHz,
All Other Pins GND

V
V

0.01

0.5

MA

3.0

5.0

pF

Note 2
Clock Input Levels
Logical HIGH Level (V OH )
Logical LOW Level (V4>L)

Vss + 0.3
Vss - 14.5

Vss - 1.5
Vss - 18.5

Clock Input Leakage

V1" -20V. TA" 25°C.
All Other Pins GND

Clock Input Capacitance

Vrp = C.DV, f = 1 MHz,
AlrOther Pins GND

~~:~~~~~~~~~~~~

0.05

17
34

Note 2

1.0

V
V
MA

20
40

pF
pF

V"

0.4

V
V

3.0
4.5
7.0

mA
mA
mA

2.5

MHz

Data Output Levels
Logical HIGH Level (V OH )
Logical LOW Level (Vod

ISOUAC~ = -0.5 rnA
ISINK ".. 1.6 rnA

2.4

Power Supply Current
T A;= 25°C, VaG = -12V,
= 150 ns, Vss '" S.OV,
V¢L '" -12V, Data"'O-1-0-1
0.01 MHz::;: Of S 0.1 MHz
9f'"
1 MHz
Ot'" 2.5 MHz

lOG

¢PW

Clock Frequency

(¢If)

¢t, =

¢ltf '" 20 ns, Note 1

Clock Pulsewidth (¢pw)

¢t,+f/lPW+¢tr~

Clock Phase Delay Times {¢d.¢dJ

Note 1

Clock Transition Tif"!les (¢t" 9t1)

¢Itt + t/Jp,"'I '+ ¢It, S 10.5 J,lS

Partial Bit Times (T)
Input Partial Bit Time (TIN)
Output Partial Bit Time (TOUTl

Note 1

10.5p.s

2.0
3.0
5.0
0.01

3.3

0.15

10

M'

I

1"

n,

10

I

0.20
0.20

100
100

M'
MS

Data InJ?:ut Setup Time (t ds)

80

'30

ns

Data Input Hold Time (tdh)

20

0

ns

Load Control Input Setup Time

80

30

n,

20

0

ns

{tLCS~

Load Control Input Hold Time
{tLChl

'Data Output Propagation Delay
From ¢OUT
Delay to HIGH Level (tpdHl
Delay to LOW Level (tpdLJ

See ac test circuit

150
150

200
200

Note 1: Minimum clock frequency is a function of temperature' and partial bit times, T,N and TOUT.
as shown by the ¢Jt versus temperature and T,N. TOUT versus temperature curves_ The lowest guaranteed clock frequency for any temperature can be attained by making T,N equal to TOUT- The
minimum gU,aranteed clock frequency is:

¢llmin)

=

TIN + TOUT

where T,N and TOUT -may not exceed the guaranteed maximums.
Note 2: Capacitance is guaranteed by lot sample testing.

8-13

n,
ns

CJ

performance characteristics
Guaranteed Minimum Clock

Guaranteed Maximum TIN

Frequ.ency vs Temperature

and TOUT vs Temperature
(Note 1)

(Note 1)

..,

100

III

'"

~

r-

t

:i
:0

10.°9(11101

!
.2Z

TINDRTouT=ZOOns

X

1.0

~

Typical Power Supplv Current
vs Clock Frequency

3.0

~

f!:

10

c-E

,:

1:l

~

TIN

V

0.1

= TOUT- I-'- f-

-;;1'0,,~
.2~

'" 1.0

:0

~

..'"

'"

:0

'z"

0.3 I-+ttlItltl-1l-tt1ii111-

i

I

0.01
-GO

-20

20

60

100

140

0.1
-GO

Typical Power Supply Current
vs Voltage
4.5
4.0

..

J

2.5

2.0

60

100

0.01
0.10
10.0
1.0
CLOCK FREIlUENCY. '" (MHz)

140

Typical Data Output Source

TvPicjll Data Output Sink

Current vs Data Output

Current vs Data Output

Voltage

.

Voltage
12

I

-j-5J.c 1"\

10

T

;:::;r:

-

'125°C ~

I

1.5

~

..... 1-"'""

15

16

.!
~

.....

:i

'"~'"

.

IPJ=1 MHz
t/Ittw"".1S0ns

z

In

VIS = 5.OV
V"L --12.0V
DATA.= 11-1-0-1

I

1.0

c-

.--:

3.5 _1A=250C

.! 3.0

20

TEMPERATURE (OCI

TEMPERATURE rCI

5.0

~

I
-20

17

18

Vss-5.DV
V.. = -12.0V
VOL =-12.DV
-1

19

VouT(VI

Vss - VaG (V)

switching time waveforms

ac test circuit

..

8-14

~

Shift Registers

NATIONAL

MM4006A/MM5006A dual 100-bit shift register
MM4007/MM5007 dual 100-bit mask programmable shift register
MM4019/MM5019 dual 256-bit mask programmable shift register
general description
The MM4007/MM5007 and MM4019/MM5019 are
monolithic dual l00-bit and dual 256-bit dynamic
shift registers utilizing P-channel enhancement'
mode technology to achieve bipolar compatibility.
The length of the registers may be varied at manufacture by the altering of the metal mask providing
custom length of both registers. Add itional connection between registers may be accomplished at the
metal mask to provide single shift register lengths'
of up to 200 or 512-bits, with or without an
appropriate tap provided at the juncture. The
MM5006A is an MM5007 programmed as a dual
l00-bit shift register.
For the MM4007/MM5007
For the MM4019/MM5019

are assigned by National upon initial order entry.
See MOS Brief 14 for a more detailed description
of the custom mask.

features
Bipolar compatibility

•

Mask programmable length
MM4007/MM5007
MM4019/MM5019

dual 20-100 bits
dual 40-256 bits

Low clock capacitance
MM4007/MM5007
MM4019/MM5019

65 pF max
125 pF max

~

N = 20 to 100 bits
N = 40 to 256 bits

Standard +5V, -12V
power su ppl ies

•

STANDARD LENGTHS:
Dual l00-bit
Dual BO-bit
Dual 256-bit

MM4006A
MM4007/AA
MM4019

•

Standard clock frequency

250 Hz min typical at 25°C
2,5 MHz maxguaranteed over temp

•

Full temperature range
MM4007,MM4019
MM5007,MM5019

CUSTOM LENGTHS:

/

The programmed shift registers are assigned a letter
code for each option, These are designated by a
pair of letters after the number code but before
the package designation such as

_55°C to +125°C
O°C to +70°C

applications

MM5007/AA/H

• Custom shift registers
• CRT recirculate display

which is a O°C to'+70°C dual BO-bit dynamic
shift register in the TO-99 package_ Pattern codes

connection diagrams
Dual-In-Line Package

Metal Can Packages

..

OPTION A OUT'PUT I CONNECTED TO IIilPUT A

,

.,"

"
"Nt

INPUT A 2

...
....

(tPTIDIII.DUTPUTAC1IIIIItICTfDTDIIIPUrl

'00

'00

12II11'U11

OUlPUTA3

........

'.'

'

TO' VIEW
Note:Pin1con~"toC8$8.

.

TOI'VllW

TO'VIE.

rOPVIEW

Note: Pin 4 ~Dnnected to case.

Nottl: Pin 4 connected to case.

Note! Pin 4connec.ted to case.

Standard Connection

Optional

Conn~tions

ordering" information
DUAL
SO-BIT

DUAL
"lOG-BIT

MM4007AA/D
MM4oo7AA/H
MM5007AA/D
MM5007AA/H

MM4oo6AD
MM4006AH
MM5006AD
MM5006AH

DI
I

nOUlPU'1

DUAL
lOO-BIT
MM4007D
MM4007H
MM5007D
MM5007H

DUAL
256-BIT

PROGRAMMABLE
20 to 100 Bits

PROGRAMMABLE
40 to 256 Bits

SEE
PACKAGE

MM4019D
MM4019H
MM5019D
MM5019H

MM4oo7XX/D
MM4oo7XX/H
MM5OO7XX/D
MM5007XX/H

"MM4019XX/D
MM4019XX/H
MM5019XX/D
MM5019XX/H

2
23
2
23

B-15

en
....

o

absolute maximum ratings

:e
:e
.......

Operating Temperature Range

It)

en
....
o

Vss + O.3V to Vss - 22V

Voltage at Any Pin

_55°C to +125°C
O°C to +70°C
_65°C to +150°C

MM4006A,MM4007,MM4019
MM5006A,MM5007,MM5019
Storage Temperature Range

~

:e
:e
o"'"
o

electrical characteristics
TA within operating temperature range, Vss = 5.0V ±5%, VGG = -12.0V ±10%, unless otherwise noted.
PARAMETER

It)

:e
:e

S
o
~

:e
:e
t. d
Logical lOW Level (V¢'d

oIt)

Vr:o= -2.0V, TA = 25°C.
All Other Pins GND

Clock Input Capacitance

VIP'" O.DV, f = 1 MHz,
All Other Pins GND

<
o

MAX

Data Input Leakage

Clock Input Leakage

:e
:e

TYP

Vss - 2.0
Vss - 18.5

CD

o

MIN

Data Input Levels
logical HIGH Level (V 1H )
Logical LOW Level fV.d

Vss - 1.5

Vss + 0.3

Vss - 18.5

Vss - 1:4.5
0.05

1.0

V
V
pA

(Note 11

MM4006A/MM5006A &
MM4oo7IMM5007

50

65

pF

MM4019/MM5019

95

125

pF

CD

o

.~

:e
:e

Data Output Levels
Logical HIGH Level (V OH )
Logical LOW Level {Vod

2.4

ISOURCE = -0.5 mA

Vss
0.4

ISINK'" 1.6 rnA

V

V

Power Supply Current

TA = 2SOC. VGG '" -12V,
rppw'" 150 ns
Vss = 5.0V, Vt/JL = -12V,
Data = 0-1-0-1

IGG

MM4006A/MM5006A &
MM4007/MM5OO7
MM4019/MM5019

0.01 MHz :s;,: ¢f ~ O. t MHz

MM4006A/MM5006A &
MM4007/MM5.oo7
MM4019/MM5019
MM4006A/MM5006A &
MM4007/MM5007
MM4019/MM5019

¢t= 2.5 MHz

Clock Frequency {¢fl

!f.It r = q,tf = 20 ns

Clock Pulsewidth (¢pw)

rptf + ¢PW + ¢t r

. Clock Phase Delay Times (¢d, ¢dJ

:5::

.01

10.5 ,",S

rptf + ¢PW + ¢t r

Partial Bit Times IT)
Input Partial Bit Time IT IN )
Output Partial Bit Time (TOUT)

(Note 21

3.0
3.5

rnA
rnA

4.0
5.0

6.0
7.0

rnA
mA

6.0
9.0

9.0
12.0

mA
rnA

2.5

MH,

3.3

10

0.15

(Note 2)

Clock Transition Times (t!Jtr, q,tfl

2.0
2.5

~

"S
ns

10
1.0

10.5 J.l.S

100
100

0.20
0.20

"S
"S
~s

Data Input Setup Time (Ic!,)

80

30

ns

Data Input Hold Time (tdh)

20

0

ns

Data Output Propagation Delay
fromq,OUT
Delay to High Level (tpdHl
Delay to Low Level {tpcld

(See ac test .circuit)
150
150

200
200

ns
ns

Note 1: Capacitance is guaranteed by periodic testing.
Note 2: Minimum clock frequency is a function of temperature and partial bit times (TIN and TOUT) as shown by the f

versus temperature and TIN, TOUT versus temperature curves. The lowest guaranteed clock frequency for any temperature.
can be attained by making TIN equal to TOUT. The minimum guaranteed clock frequency is:
t(min)

=

1
TIN + TOUT' where TIN and TOUT do not exceed the guaranteed maximums.

Note 3: Minimum clock frequency and partial bit time curves are guaranteed by testing at a high temperature point.

8-16

.performance characteristics
Guaranteed Minimum Clock
Frequency vs Temperature
(Note 2)

Guaranteed Maximum TIN
and. TOUT vs Temperature
(Note 2)
100

10

i

-

"'~
~

~

.,.

TIN orTOln=200m:

..s

.Y

1.0

:0

Typical Data Output Source
Current vs Voltage
.

li

10

l-

i

If

.=

~

~

T'N-ToUT - l -

V

0.1

t-

'~"

..!!i'"

iii 1.0

'"

:0

.....

iii

8.1

0.01

-2D

-&0

20

IIG

100

-20

1411

BO

20

. IDa

VOUT

Typical Power Supply Current
VOltage MM4006A/MM5006A

Typical Data Output Sink.
Cllr,ent vs Voltage
10

C

.

..s

ill

'"'"~

..

........

:=:~::.ov

...

z

..... .....,.

I

-I-

I I

0
-1

5

15

14

16

17

18

14,

.. ".'

~~

3.0

15

17

Typical Power'Supply Curren"t V5 Clock
Frequency MM4006A/MM5006AI
MM4007/MM5OQ7

~

10.0 .
. .
1111
I
~E-5n
TA =25·C
3.0 H-tfflIHII-1f-t
D

-I
'Z

t.a

r-T I
1...1m·e
I I
I I

V.. -V .. !VI

Typical Power Supply Current
vs.Clock Frequency MM40191
MM5019

lo.D

19

V,,-VGGIV)

VouTIV)

'lJ

TA = 25·C

-

.... f-""

.... ~:J
" I

...

Vss= 5.0V
Vo• --12.0V
V... = -12.0V

.... i"""

- r-1s.J

--

DATA = D-l-"'l

~

....-n
TA = 25°C

I I

Il,=1.DMtb

¢tow="'ns

-55·C

oe

I-

;

Typical Power Supply Current
Voltage MM4019/MM5019

10

I I
I I

..s

jl'O~Flk-'.1

'c

J

125"C

~=150111

0.3

0.3
II
0.001

Vss-S.IV

~:~ :=!~:. tltflHr-+1I-1tfIllf--H+llI1A

D.OI D.l0

1.0

(V)

y.

I I

10

C
.!

v.

MM4007/MM5007

12

;;;

1411

TEMPERATURE"rC)

AMBIENT TEMPERATURE rCI

DATA = 1\-1-1-1

0.1
lOOI

lD.O

CLOCK FREOUENCY.~f IMHz)

0.01

0.10

lD.O

1.0

CLOCK FREOUENCY ... (MHz)

switching waveforms

ac test circuit

DATAl_1fT

·.v
.K

DATAOUTf'UT,_ _ _ _ _ __

8·17

_r_f-""

-

1.

19

~

Shift Registers

NAnONAL

MM4013/MM5013 1024-bit dynamic shift register/accumulator
general description
The MM4013/MM5013 1024·bit dynamic shift
register/accumulator is an MOS monolithic inte·
grated circuit using P·channel enhancement mode
low threshold technology to achieve direct bipolar
compatibility. There is on-chip logic to load and
recirculate data, and a read control for enabling the
bus-ORableTRI-STATE™ push pull output stage.

• Wide frequency range

2SoC typ
CPf max = 2.S MHz

over temp. guaranteed
• Built·in recirculate

.

• Package option

A"ows wire·OR bus
structure on output

• Fu" temperature operation
MM4013
MMS013

Standard +5V, -12V
power su ppl ies
No pull down or
pull up resistors
required

-SSoC to +12SoC
O°C to +70°C

applications
• "Silicon Store" replacement for drum and disc
memories
• Fi.le memories
• CRT refresh

TO·99 or
molded a·pin mini·DIP

• Low clock capacitance

Exclusive·OR and
recirculate loopon·chip

• TRI-STATE output

features
• Bipolar compatibility

¢f min = 400 Hz @

160 pF max

connection diagrams
Dual-In-line Package

Metal Can Package

..In
COtITflOL

,.

DATA

Order Number MM4013H
or MM5013H

:m:;~~'OL
IIIMIITS

3

See Package 24
v.

•

II.

typical applications

. Ii

DUTPUT

Order Number MM4013D
orMM5013D

See Package 1
Order Number MM5013N
See Package 12

fw

truth table

TTL/MOS Interface

(Positive logic)
Logic •.'," = V1H = Logical HIGH level
Logic "0" = V 1L Logical LOW Level
;0

I

L

-r

DTLfTTL.J

I

L-----··~I~""'.!..----.J

I
I

*

.r..
,..------------,
.-1

I
I
'-1
I
'-I

MM4I13/111111!i01l

I

L~'!!:...J

I
I
I.
I
I
I

L------r------.J
vOO
'A

-If\/.~111%

8·18

WRITE

READ

FUNCTION

0

0

Recirculate
Output Disabled

0

1

Recirculate
Output Enabled

1

0

1

1

Write Mode

Output Disabled

Write Mode
Output Enabled

absolute maximum ratings
Voltage at Any Pin
Operating Temperature Range MM4013
MM5013
Storage Temperature Range
lead Temperature. (Soldering, 10 sec)

Vss+O.3toVss -22
-5SoC to +12SoC

O°Cto+70°C
-6SoC to +l50G C
300°C

electrical characteristics
TA within operating temperature range, Vss:;;; +5.0V ±5%, VGG '" -12.0V ±10%, unless otherwise noted.
PARAMETER

CONDITIONS

MIN

Data Input Levels
Logical HIGH level, (V 1H )
Log'ical LOW level (V II)

TYP

MAX
Vss + 0.3
Vss - 4.2

"ss - 2.0
VSS -18.5

UNITS

V
V

Data Input Leakage

V IN '" -20.0V, T A"" 25°C,
All Other Pins GND

0.01

0.5

JJA

Data Input Capacitance

VIN '" O.OV, f '" 1 MHz,
All Other Pins GND
(Note 1)

3.0

5.0

pF

Control Input levels
Logical HIGH level (V H)
logical lOW level (V d

Vss+O.3
Vss - 4.2

Vss - 2.0
Vss - 18.5

V
V

Control Input Leakage

VIN '" -20.0V, T A"" 25°C,
All Other Pins GND

0.01

0.5

~A

Control Input Capacitance

VIN '" O.DV, f '" 1 MHz,

3.0

5.0

pF

Clock Input Levels
Logical HIGH Level (V,pH 1
Logical lOW level (V 4I d

All Other Pins GND
(Note 11

Clock Input leakage

V 4I "'-20.0V. TA '" 25 C,
All Other Pins GND

Clock Input Capacitance

V 4I = O.OV. f= 1 MHz

Data,Output Levels
Logical HIGH Level (VoHI
logical LOW Level (Vod

0.05

140

ISOURCE = -0.5 rnA
'SINK 1.6 mA

2.4

=

VOUT = -S.OV, T A'" 25°C
Output in Highlmpedance State

Power Supply Current
IGG

TA '" 25G C, Voo '" -12V.
4Jpw '" 150 ns, Vss = S.OV,
VOj)L'" -12V, Data'" 0-1·0-1
0.01 MHz~4Jf~0.1 MHz
4Jf= 1.0 MHz
41, '" 2,5MHz

4Jtr ... 411, '" 20 ns, (Note 21

0.01

4Jtf +r/Jt.w + 4Jt,~ 10.5",s

0.15

Clock Phase Delay Times (I/Jd. iiidl

(Note 2)

Clock Transition Times (1/Jt,.lPtf)

I/Jtf + rpM + tPtr s:. 10:5",5

Partial Bit Times IT)
Input Partial Bit Time (TIN)
Output Partial Bit Time (TOUT)

(Note 2)

Vss

1.60
5.3
10.3

Clock Pulsewidth '41pwl

Freql:lencv (<;fl

1.0
190

V
V
~A

pF

All Other Pins GND
(Note 11

Data Output Leakage

CI~ck

Vss + 0.3
Vss - 14.5

Vss - 1.5
Vss - 18.5
G

3.3

0.4

V
V

10.0

JJA

3.0
8.0
15.0

mA
mA
mA

2.5

MHz

10

~,

10.0
1.0
0.2
0.2

80

Data Input Setup Time I'telJ

100
100

~,

~,

~s

30

Data Input Hold Time (tdhl

20

0

Write Setup Time l'tcts)

80

30

Write Hold Time h dh )

20

.'"

Read Setup Time hAS)
Read Hold Time

(tRh)

Data Output Propagation Delay
from !POUT
Delay to HIGH Levelltpd1 1
Delay to LOW Level (tpdQ)

,. (see ac test circuit)

150
150

200
200

150
150

200
200

150
150

200
200

Propagation Delay From
Read
Disable to
HIGH Impedance State:

Control

Delay From HIGH Level1t1 H l
Delay From lOW levelltoH )
Propagation Delay From
Read Control Enable to
LOW ImpedanCe State:
Delay to HIGH Le~el (t H ,)
Delay to LOW lev~1 (tHO)

Note 1: Capacitance is guaranteed by period,ic testin'g.

Note 2: Minimum clock frequency is a function of temperature and pa,tial bit times (TIN and TOUT) as shown by the tlminl = TIN + TOUT • where TIN and TOUT do not exceed the guaranteed maximums.
Note 3: Minimum clock frequency and partial bit time curves are guaran.teed by testing at a high temperature point.

8-19

DI

perform ance characteristics
Guaranteed Minimum Clock
Frequency vs Temperature
(Note 21

Gu.aranteed Maximum TIN
and TOUT vs Temperature
(Note 21

lD111c

l00F~~""'f!IIIF'f'

Jl,om

:!

TIN OR TOUT 200n

Typical Power Supply Current
vs· Clock Frequency

100 •
10 l'I.

•

J"

TIN. TOUT

""""

10

-60

-20

20

60

100

140

10

..

~
;;;
iii 0.1

0.01
-60

-~o

20

60

100

0.1 LL.l.W.tIL-L.WJ.LW.....J...U.
0.001
0.01
0.1
1.0

140

AMBIENT TEMPERATURE (OCI

AMBIENT TEMPERATURE (OCI

Typical Power Supply Current
vs Voltage

10.0

CLOCK FREQUENCY••• (MHz)

Typical Data Output Source
Current vs Date Output
Voltage

Typical Date Output Sink
Current vs Data Output
Voltage

9.0

-r-r --

B.O
1.0

.

-55°C

6.0

C
.!

5.0

!P

4.0

....

-.::: FT.:25°C~ -

3.0
2.0

....s
....z

125°C
.,=1 MH.·
..... =150 ••
Y.. -5.0V
V... --,1Z.OV
V... - 3.5V

~

0:

...'"

..

z

;;

DATA-HO·I

t.O
15

1&

11

IB

10

OL--"--"---"-~"'-~--'

19

-1

5

VSS-VGG tV)

VouT(VI

V(JlJT(YI

Typical TrioState Data Output
Capacitance vs Voltage

.......
T. = 25°C
Test/req.-1MH.
All Othlr Pi... GNO

-1
VOUT (V)

ac test circuit

truth table

51

52

RI

Cl

tpdO

Closed

Closed

35K

20pF

'"",

20

DELAY

8·20

pf

Closed

Closed

35K

'",;

Closed

Closed

2.SK

"H
'HO
'H'

Closed

Closed

2.SK

5pF

Closed

Opeo

35K

20pF

Opeo

Closed

35K

20pF

5pF

switching time waveforms

¢OUT CLOCK

READ

Vss-2.0V

-'~'7:r-------"'"
Vss-4.2V

Vss-4.2V

OUTPUT

- - - - ',HOt

':"'--.. r'----!t'a,

O.5V

The level of ttle output when it is in the high i!'lpedance state is ,determined by the external circuitry. The correct
data will always appear. after some propagation delav. when the read control is enabled. The guaranteed delay from
the high impedanee state to the low impedance state requires tfJat the reid con trol is enabled on or before the
leading edge of ¢OUT-

!

I
I

i

I

[;)II
I

i
I
I
I
I
a.AlA OUTPUT

WITH READ CONTROL
ENABLED

I
1.5V

8·21

~.

Shift Registers

NAnoNAL

MM4015A/MM5015A triple 60+4 bit accumulator/register
general description
The MM4015A/MM5015A triple 60+4 bit dynamic
accumulator is a monolithic MOS integrated cir·
cuit utilizing P·channel enhancement mode low
threshold technology. The device consists of three
independent shift registers with logic to control
the entry of external data or to recirculate the
data stored in that register. A common two phase
clock is required to operate the device.

• Low frequency operation
• Low power consumption

250 Hz at 25°C,
guaranteed
0.4 mW/bit
typically at 1 MHz

• Recirculate logic on·chip
• BCD correction look ahead tap

applications

features

•

Data storage registers in BCD arithmetic applications
• Basic accumulator functions
• Business machine memory applications
• Recirculating delay line

• Direct DTL and TTL compatibility

No pull·up
or pull·down
resistors required
• High frequency operation 2.5 MHz guaranteed

connection diagram

Dual-in-Line Package
16 VGG

INPUT 1 1

150UTPUliA

LOAD CONTROL 1 2

oUTPUTIB 3 - + - - < > = " - - - - - - '

14 OUTPUT2A
130UTPUT3A

INPUT I 4-f-;:=:OfLr_

""""

LDADCONTRQl2 5
OUTPUT2B 6

l1a.N

INPUTl 1 - , !C-~="~~:O>-G~l.ti[h+-l0 OUTPUllS

L-=======--\--9

LOAD CONTROLl

Note: Pin 8 connected to case.
TOP VIEW

Order Number MM4015AD Dr MM5015AD
See Package 3

typical applications
TTL/MOS Interface

'Typical Arithmetic Configuration

f~.OV

r ~~' r------~5------, r-l~,
nLJDTL

MM4DISAlMMSlI5A

TTL/DTl

I I

'-

-r
-

.J'-

I I
I

---!---1---!;;;-- .J'11

12

16

¢IN

00U1'

-n.ov

-r

.J

The abo¥9circuit will generate the function:

lOildConuoi
logical low - Data is Loaded
Logical Hi9h - Data is Recirculated

A+C---B

8-C

A-A

8·22

s:
s:

absolute maximum ratings

.j::o

Voltage at Any Pin
Operating T~mperature Range MM4015A
MM5015A
Storage Temperatu re Range

...o
U1

Vss + O.3V to Vss - 22.0V
_55°C to +125°C
O°C to +70°C
-65°C to +150°C

»

........

s:
s:U1

...

o

electrical characteristics

U1

= 5.0V ±5%, VGG = -12.0V ±10%, unless otherwise stated

TA within operating temperature range, Vss
PARAMETER

CONDITIONS

Data Input Levels
l.ogical HIGH Level IV IHI

logical LOW level

MIN

TVP

Vss -2.0
Vss -18.5

(V,d

MAX

UNITS

Vss + 0.3

V
V

Vss -4.2

Data I nput Leakage

VIN =-20.0V. TA = 2SoC,
All Other Pins GND

0.01

0.5

~A

Data Input Capacitance

VIN =- O.OV. f'" 1 MHz,

3.0

5.0

pF

»

All Other Pins GND
See Note 2

Load Control Input Levels
Logical HIGH levei IV'HI

Load Control Input Leakage
Load Control Input Capacitance

Vss + 0.3
Vss - 4.2

Vss - 2.0
VSS - 18.5

Logical LOW Level (VIIJ

V
V

VIN '" -20.0V. T A = 2Soc,
All Other Pins GNO

0.01

0.5

~A

VIN '" a.DV, f= 1 MHz,
All Other Pins GND

3.0

5.0

pF

See Note 2
Clock Input levels
~ogical HIGH leveHV¢'HI
Logical LOW level IV¢d
Clock Input leakage

Vss + 0.3
Vss - 14.5

Vss - 1.. 5

Vss - 18.5
Vt/J = -20V, T A = 25°C.

V
V

1.0

~A

60.0

pF

Vss
0.4

V
V

3.0
5.5
8.5

rnA

2.5

MHz

10.0

~s

0.05

All Other Pins GND
Clock Input Capacitance

Data Output Levels
Logieal HIGH Level (VOH )
Logical' LOW Level (V o ,)
Power Supply Current
IGG

O.oy.

45.0

Vq, '"
f '" 1 MHz,
Art Other Pins GND
See Note 2
ISOURCE = -0.5 mA
= 1.6 rnA

2.4

ISINK

T A =,25°C, VGG = -12V,
¢PW = 150 ns, Vss = +5.0V,
V~L --12V,Data-G-l-G-l

0.01 MHz S; q" S; 0.1 MHz

2.2
4.5
7.0

lMHz
~f q" - 2.5 MHz

,-

Clock Frequency (rp.,)

¢ltr = ¢tf'" 20 ns. Note 1

0.01

Clock Pulsewidth (¢pwi

,ptf + q,pw + ¢1, S 10.5J,Ls

0.15

Clock Phase Delay Times ItPd, $dl

Note 1

Clock Transition Times (tPt... ¢ttl

tPt, + ¢pw + ¢tr S 10.5 ItS

Partial Bit Times (T)
Input Partial Bit Time (TIN)
Output Partial Bit Time (TOUT)

Note 1

3.3

rnA
rnA

ns

10
1.0
·0.20
0.20

100
100

'"
~s
~s

Data Input ~etup Time (let.)

80

30

ns

Data Input Hold Time tlcih)

20

0

ns

(~sl

80

30

ns

Load Input-Hold Time (tlh)

20

0

ns

Load Input

~tup

Time

Data Output Propagation Delay
FromrpOUT
Delay to HIGH Level (tpdH)
Dela,y to LOW Level (tpdd

150
150

200
200

ns
ns

Note 1: Minimum clock frequency is a function of temperature and partial bit times (TIN and TOUT) as shown by the f

versus temperature and TIN. TOUT versus temperature curves. The lowest guaranteed clock frequency for any temperature
can be attained by making TIN equal to TOUT. The minimum guaranteed clock frequency is:
t(min) =

1 . , where TIN and TOUT do not exceed the guaranteed maximums.
TIN + TOUT

Note 2: Capacitance is guaranteed by periodic 'testing.

8·23

CI
,

performance characteristics

..

Power Supply Current vs

(Note 1)

(Note 1)

Clock Frequency

100

t--

~

ffi

Typical Maximum Partial
Bit Times vii Temperature

10

~

'"
S

Typical Minimum Clock
Frequency vs Temperature

TIN Of TOUT

]
>I
;::

200 ns

X

1.0

~

~

TIN

...Z

VV

0.1

-

=TOUT- -

0
0

>=

"'"
"x
"

~

3.0

1.0

-

-55'C

1.0

0:

":Ez
0.01
-20

20

60

100

140

Power Supply Current

0

60

100

140
CLOCK FREQUENCY. . IMHz!

Data Output Sink
Current YS Voltage

10

~V
...... :::::- I-' V

----

Vss= +S.OV

1--t_-+_+_ VGG "-12.0V
V"L" -12.0V

,., 5 ~5"C r~ 'TA " 25'C

I--::::::

3.0

20

12

t>f-1MHz
IPPW= 150 ns

5.0

-20

Data Output Source
Current vs Voltage

vs Voltage
6.0

-60

AMBIENT TEMPERATURE ICI

AMBIENT TEMPERATURE I'CI

oS 4.0
0

"

0.1
-60

.

....s

10

~

a

If

~

10.0_

-125'C

r-

2.0
15

16

17

lB

19

1,

0

switching time waveforms

-1

-1

OUTPUT VOLTAGE IVI

Vss - VGG (V)

OUTPUT VOLTAGE IVI

ac test circuit
'"v
4K

ANV
MM4015A
QUTP!lT

¢'nCLDCK

Vss -l.5V

,.
9QUT

CLOCK
Vss-l.5V

.·t

~
~

1.SV

.~

...._ _ _ _ _ _ _ _ _-'

8-24

t.5V

o--....- ...,..t-+--I*-.H..-,

Shift Registers

~

NAnONAL

MM4016/MM5016 512-bit dynamic shift register
general description
The MM4016/MM5016 512-bit dynamic shift register is a monolithic MOS integrated circuit utilizing P channel enhancement· mode low threshold
technology to achieve bipolar compatibility. An
·input· tap provides the option of using the device
as either a 500 or 512-bit register.

• Militilry and Commercial Temperature Ranges
MM4016
. -55°C to +125°C
MM5016
O°C to +70°C
•

Low power dissipation

features
•

Bipolar compatibility

+5V. -12V operation
No pull-up or pull-down
resistors required.
TO-loo or choice of two
Dual-In-Line Packages

•

Package option

•

Fewer clock drivers required

<0.17 mW/bit
at 1 MHz max.
<30flW/bit
at 100 kHz typo

applications
• Glass and magnetostrictive delay line replacement.
• CRT refresh memory.

Clock line
capacitance of
100 pF typ
• System flexibility
300 Hz guaranteed min.
operating frequency at 25°C.
500 or 512-bit register length.

• Radar delay line.
• Drum memory storage (silicon store)
• Long serial memory.

connection diagrams
Dua'I-ln-Line Package

Metal Can Package

Dual-In-Line Package

1& Ne

Ne

IS

Ne
Ne
OUTPUT

Ne

¢COUT

V.,

Note: Pin 5 connected to case.
TOP VIEW

Note: Pin • connected to case.

Order Number MM4016H
orMM5016H
See Package 24

Order Number MM4016D
orMM5016D
See Package 3

TOP VIEW

TOP VIEW

typical application
TTL/MOS Interface
.5V

Note! The unused input pin must be connected to Vss.

8-25

Order Number MM5016N
See Package 12

absolute maximum ratings
Voltage at Any Pin
Operating Temperature Range

Vss + 0.3V to Vss -22V
_55°C to +125°C
0°Cto+70°C
_65°C to +150oC

MM4016
MM5016

Storage Temperature Range
Lead Temperature (Soldering, 10 sec)

300°C

electrical characteristics
TA within operating temperature range, Vss = +5.0V ±5%. VGG = -12.0V ±10%. unless otherwise specified.
PARAMETER

CONDITIONS

Data I nput Levels
Logical HIGH Level (V,H )
LO.gical LOW Level (V ,L )
Y'N = ~ 20V, T A = 25°C,
All Other Pins GND

Data Input Capacitance

Y'N ~ O.OV, f = 1 MHz.
All Other Pins GND, (Note 2)

Clock I nput Levels
Logical HIGH Level (Vf
versus temperature and TIN. TOUT versus temperature curves. The lowest guaranteed clock frequency for any temperature
can be attained by making TIN equal to TOUT. The minimum guaranteed clock frequency is:
1
, where TIN and TOUT do not exceed the guaranteed maximums.
TIN + TOUT
Note 2: Capacitance is guaranteed by periodic testing.

f(min)

=

8-26

performance characteristics
Typical Maximum TIN
and TOUT vs Tempsratur.
(Note 1)

Typical Minimum Clock
Frequency v~ Temperatura
(Note 1)

g

10K
MM4016

--

50

-- MM5tl16",:0--00
~~

_ lK

1 20
j ;.:

::>

500

lL''';i i"'-

~ 100

~
i

"
;2.0

TIN-ToUT=

~ ,200

!i

10.0

100

5K

~ 2K

ffi0:

TIN or" TOUT" 200 ns

20
10
60

100

"

c

~ 1.0
~

MM5015'iC! _ ' 5

0.5

I
-60

-20

TEMPERATURE I'CI

5.0

.. -I MHz
tfft-liOns
Vss = 5.0V

4.0

~~
1.5
1.0

0.1
0.001

0.01

0.10

1.0

10.0

CLOCK FREQUENCY. 0, IMHzI

Typical Data Output Sink
Current V5 Voltage

,..-!!!

.....
.....

125'c.... ~

Vss = S.tlV
VGG =-12.0Y -+--~,.....,f--l
VOL =-12.0Y

,
J....o"

15

15

140.

-Ss'c

T. = 2S'C......

2.0

.... =150 ..
V.. -S.OV
VG.=-IUV
VOL =-12.0V
DATA =0-1-11-1

0.3

""l
100

Typical Data Output Source
Current vs Voltage

DATA:t::~

.....r

2.5

50

""

VrpL =-12V

" .....

3.5
~
.§ 3.0 ~

C

20

TEMPERATURE I'CI

Typical Power Supply
Current vs Voltage
4.5

.1l

!'"

140

•. 12S'.C:

.§ 1.0

0.2
0.1

I
20

L-··-C.
_~', II "In

3.0

::>

5tI

-60 . -20

.1l

Typical Power Supply
Current vs Clock Frequency

17

-1

19

18

Vss - VGO IV)

VaUT(V)

switching time waveforms

ac test circuit

DATAIIIPUT

'5V

.<

-~'''t

PATAOUTPUT

uv

"k

...._ _ _ _ _ _ _J

uv

8·27

Shift Registers
MM40111MM5017 dual 512-bit dynamic shift register
general description
The MM4017/MM5017 dual 512·bit dynamic shift
register is .a monol.ithic MaS integrated circuit
utilizing P channel enhancement mode low threshold technology to achieve bipolar compatibility.
Anihput tap provides the option of using either
register ina 500·bit or 512·bit configuration.

• System flexibility

• Military and Commercial Temperature Ranges
M M 4 0 1 7 - 5 5 ° C to +125°C
MM5017
O°C to +70°C

features

• Low power dissipation

• Standard +5V. -12V supplies
Bipolar com·
patibility. No pull-up
or pull-down
resistors requ ired.

applications

<0.17 mW/bit
at 1 MHz max.
< 30 pW/bit at
.100 kHz typo

• Glass and magnetostrictive delay line replacement
• CRT refresh memory
• Radar delay line
• Drum memory storage (silicon store)
• Long serial memory

• Package option TO-l 00 or Dual-I n-Line Package.
Clock line
capacitance of
140 pF typo

• Fewer clock
drivers required

400 Hz guaranteed
m in. operating frequency
at 25°C. 500 or
512·bit register length.

connection diagrams
Dual-In-Line Package

Metal Can Package

'"
Order Number MM4017H
orMM5017H
See Package 24

'.

TOPVIEW

typical applications
1000 Or 1024 Bit Accumulator

RECtRCULATEllrlUTt-r.----l......./

DA~:_o--

_ _ _-t.J"'

TTLIMOS Interface
+!iV!;$!I.

r----J.!!!o----, r-l!"'-l
I

I

i:r

II

IIIIMIIl1~J

'-----;t-----l' l voo
.12V!;10I!t

Note: Unttsed inpuds) should be tied to Vss.

8-28

I.
JI

I

Order Number MM4017D
orMM5017D
See Package 3
Order Numb.r MM5017N
See Package 15

3:
3:

absolute maximum ratings

...~

Voltage at Any Pin
Vss + 0.3 to Vss - 22
-SSoC to +12SoC
Operating Temperature MM4017
O°C to +70°C
MM5017
-65°C to 150°C
Storage Temperature
300°C
Lead Temperature (Soldering, 10 sec)

....
......
3:
3:

electrical characteristics

U1

T A within ,operating temperature range, Vss ~ +5.0V ±5%, VGG ~ -12.0V ±10%, unless otherwise specified.

:l

CONDITIONS

PARAMETER

MIN

Data I nput Levels
Logical HIGH Level (V,H )
Logical LOW Level (V,d

TVP

Vss - 2.0
Vss -18.5

MAX

UNITS

Vss + 0,3
Vss - 4,2

V
V

Data I nput Leakage

Y'N ~ -20V, T A = 25°C,
All Other Pins GND

0.01

0.5

p.A

Data I nput Capacitance

Y'N ~ OV, f= 1 MHz,
All Other Pins GND

3.0

5.0

pF

Clock I nput Levels
Logical HIGH Level (VI/lH)
Logical LOW Level (V ~ -20V. TA~ 25°C,
All Other Pins GND

Clock Input Capacitance

VI/> ~ OV, f ~ 1 MHz,
All Other Pins GND

Data Output Levels
Logical HIGH Level (V OH )
Logi~alLOW Level (Vod

,

TA = 25°C, Vaa ~ -12V, .ppw ~ 150 ns
Vss = 5.0V. VI/JL = -12V,
Data ~ 0-1-0-1
0.01 MHz s.p,::;; 0.1 MHz

(.pf)

Clock Pulsewidth (t~

Clock Frequency

0.05

ISOURCE = -0.5 rnA
ISINK = 1.6 rnA

Power Supply Current
IGG

Vss + 0.3
Vss - 14.5

.pt, = .pt, = 20 ns, Note 1

0.01

.pt, + .ppw + .pt, S

0.15

10.5 p.s

Note 1

3.3

10

10

p.s
ns

.pt, + .ppw + .pt,s 10.5 p.s

Partial Bit Times (T)
Input Partial Bit Time (T'N)
Output Partial Bit Time (TOUT)

0.20
0:20

1.0

p.s

Note 1
Note 1

p.s
p.s

Data Input Setup Time (td.)

80

30

ns

Data Input Hold Time Itdh)

20

0

ns

Data Output Propagation Delay
from .pOUT
Delay to HIGH Level (tpdH )
Delay to LOW Level (tpdd

See ac test circuit

150
150

200
200

ns

ns

Note 1: Minimum clock frequency is a function of temperature and partial bit times (TIN and TOUT) as shown by the I/>t
versus temperature and TIN. TOUT versus temperature turves. The lowest guaranteed clock frequency for any temperature
can be attained by making TIN equal to TOUT- The minimum guaranteed clock frequency is:
4>i(minl

=

1
,where TIN and TOUT do not exceed the guaranteed maximums.
TIN + TOUT

Note 2: The

c~rves

are guaranteed by testing at a ~igh temperature

Note 3: Capacitance is guaranteed by periodic testing.

8·29

point~

0

[;)II

performance characteristics
Guaranteed Minimum Clock

Guaranteed Maximum
TIN and TOUT
(Notes 1 and 2)

Frequency vs Temperature

(Notes 1 and 2)

Typical Power Supply
Current vs Clock Frequency

100

lOOk

1== TINORTOUT~20Dn

]

10

I'

J
j

""" ==

TIN. TOUT

10

--1.0

Jl
1.0

~

0.1

0.01

10
-60

-20

20

60

100

140

-liD

AMBIENTTEMPERATURE ('C)

Typical Power l)upply
Current vs Voltage,

9.0
T.=25'C,
8.0

&.0

.

:..-r.

i--":: V

;;
.! 5.0

-20

20

60

100

140

0.1 L-I..JJ.I.1IW....J...I.llU1IL1lI.UJW-L.LW1IIII
10.0
0.001
0,01
1.0
0.1

AMBIENT TEMPERATURE ('C)

CLOCK FREQUENCY,,, IMHz)

Typical Data Output Source
Current YS Data Output Voltage

Current vs Data Output Voltage

Typical Data Output Sink

....- ......- .J.

V i--o'"'" ~ .......... V V V .......
-55'C...,

1.0

.§

'~;;"

V

;;

".

1
...
~
~w

12r'c

cpf=-l MHz
I/Jpw '" 150 ns
Vss = 5.0V

24.0
3.0

V¢L'"

~

Z f----1~<-.o(!:,.£--+--I--+-.,J

li!

-12.0V

V~H '" J.5V
DATA = 0-1-0-1

2.0
1.0
15

1&

17

18

-1

19

Vss - VGG (VI

VOUT

(VI

-1
VOUT

ac test circuit

switching time waveforms

<-S.•

•K

¢OUT

CLOCK

DATA OUTPUT

'" I_____________F
8·30

(VI

~

Shift Registers
Revised January 1976

NA'IlONAL

MM4025/MM5025 dual 1024-bit dynamic shift register
MM4026/MM5026 dual 1024-bit dynamic shift register
MM4027/MM5027 2048-bit dynamic shift register
general description
These 2048-bit dynamic shift registers are MOS
monolithic integrated circuits using P-channel .silicon gate technology. They employ a push-pull
output for bipolar .compatability and on-chip
multiplexing to achieve a 6 MHz data rate. The
clock rate is one-half the data rate, i.e., one data
bit is entered for each rf>, and rf>2 ciock pulse.

•

Low power dissipation
120 f.1W/bit
at 1 MHz rf> rate O°C, guaranteed

•

Low ciock capacitance

•

Wide operating temperature range
MM4025,MM4026,MM4027 -55°C to +125°C
O°C to 70°C
MM5025,MM5026,MM5027

The MM4025/MM5025 and MM4027/MM5027
have on-chip logic to load .and recirculate data.
The MM4026/MM5026 has an individual logic·
select line to load one of the two inputs on each
of the 1024·bit registers.

applications
•

features
Standard +5V, -12V
power su ppl ies
6 MHz
• High frequency of operation
guaranteed
•

190 pF max

"Silicon store" replacement for drum and disc
memories

Bipolar compatibility

• CR T displays
•

Buffer memories

logic and connection diagrams
Military Temperature Range
Dual-In-Line Package

Dual·ln·Line Package

Flat Package

Order Number MM4025D
Or MM5025D
See Package 3

Order Number MM4026D
Dr MM5026D

Order Number MM4027F
Dr MM5027F
See Package 26

See Package 3

Commercial Temperature Range
Dual-In-line Package

Order Number MM5025N
See Package 13

Dual-In-Line Package

Dual-I n-Line Package

Order Number MM5026N
See Package 15

Order Number MM5027N
See Package 12

8·3.1

absolute maximum ratings
+0.3 to -2D.OV

Voltage at Any Pin With Respect to Vss
Operating Ambient Temperature Range
MM4025.MM4026,MM4027
MM5025,MM5026,MM5027

-55°C to +12SoC
O°C to +70°C

-65°C to +150°C

Storage Temperature Range
Lead Temperature (Soldering. 10 sec.)

300°C

electrical characteristics

Vss = +5.0V ± 5%. Voo = GND. VGG = -12.0V ±10%
T A within operating temperature range unless otherwise stated.
CONDITIONS

PARAMETER

MIN

TYP

MAX

UNITS

Vss + 0.3
Vss - 4.2

V
V

Data Input Levels

Vss -1.5

Logical High Level (V IHI
Logical Low Level (V Id

Vss-1O

-lOV, TA::o 25°C, All other pins GND

Data Input Leakage

V IN

Data Input Capacitance

Y,N '" OV, f

""

=

1 MHz, All other pins GNO (Note 1)

0.01

1.0

~A

2.5

5.0

pF

Vss + 0.3
Vss - 4.2

V
V

Load/Select 1nput Levels

Vss -l.5
Vss -10

Logical High Level (V tH )
Logical Low Level (V tL )

Load/Select Input Leakage

VIN '" -lOY, T A"" 25°C, All other pins GNO

0.01

1.0

~

Load/Select Input Capacitance

YIN:o OY, f "" 1 MHz, All other pins GND (Note 1)

4.0

7.0

pF

Clock Input Levels
Logical High Level (V ¢H)
Logical low Level (V¢d

Vss + 0.3
Vss -14.5

Vss - 1:0
yss - 18.5

Clock Input, Leakage

VIj)'" -15V, TA ;- 25°C, All other pins GND

Clock Input Capacitance

V.p

Data Output Levels
Logical High Level (V OH)
Logical Low Level (VOL)

Isou ACE = -0.5 mA
ISINK =- 1.6 rnA

=:

.05
165

OV, f '" 1 MHz, All other pins GND (Note 1)

2.4
0.0

1.0
190

V
V
~A

pF

Vss
0.4

V
V

3.5
3.5
3.5

rnA
rnA
rnA

Power Supply Current
IGG

TA '" 2SoC, VGG' "" -12.0V. ¢pw = 160 ns
Vss= S.OV, V¢L =: -12.0V, DATA '" Note ~
Y oo = O.OV

0.01 MHz OS; f

0.03
0.003

2.0
4.0

0.240
0.240

1.0
1.25

rnA
rnA
rnA

MHz
MHz

8.0
10

ps

0.5

~s

~s

10

See Curves

Clock Transition Times (¢t r • 1>tf)
Partial Bit Times (T)
T 1 Partial Bit Time

15
32
70

~s

ns

(Note 2, Note 3)

MM4025.MM4026.MM4027
MM5025.MM5026.MM5027

0.5
0.4

16.5
165

T 2 Partial Bit Time
MM4025.MM4026.MM4027
MM5025.MM5026.MM5027

0.5
0.4

16.5
165

~s

~s

Data & Load/Select Input Setup Time (tds)

35

ns

Data & Load/Select Input Hold Time (tdh)

20

ns

Data Output Propogation Delay from ¢
Delay to High Level (tpd-tl
Delay to Low Level hpdd

15 pF Output Capacitance

Note 1: Capacitance is guaranteed by periodic testing.
Note 2: Minimum clock frequency is a function of te';'perature and partial bit times (T, and T2) as shown by ri>f versus
temperature and T 1, T 2 'versus temperature curves. The lowest guaranteed clock frequency for any temperature can be
attained by makifi9 Tl equal to T2. The minimum guaranteed clock frequency: ¢f (min) "" l/lT1 + T2' where T1 and T2 do
not exceed the guaranteed maximum.
Note 3: Minimum clock frequency and partial bit time curves are guaranteed by testing at a high temperature point.
Note 4: For data pattern of 1111000011110000 etc.
Note 5: Maximum frequency limited by maximum package power diSSipation for MM4025, MM4026 and MM4027.

8·32

160
160

ns
ns

guaranteed performance characteristics

Typical Minimum Clock
Frequency vs Temperature
(Note 21

Typical Maximum T 1 and
T2 vs Temperature INote 21
100

lOOk

~ TIN

:§

OR TOUT" 200

10

j
TIN. TOUT

j
!i

====

I\..

1.0

!!
z

1/
10
-60

"

.. 0.1

-20

20

60

100

0.01
-60

14lJ

·20

20

60

140

100

AMBIENT TEMPERATURE re)

AM81ENT TEMPERATURE re)

typical performance characteristics

82
.18
'74

10

'i

!

~

C

70
&6
62

0

58

1.0

ill

.!

=>

:::

::or

~·80n.

V¢--18.SV ~
VOD "" -5.3V
Vss - GND --'=
T. =+25"e ..

.1

E
.01

VOG

II

..P

54

-'"''

V,,··IUV

~

'lSI ,GIG

.....

'i'GG,·ruv
""U!MIlo

-

......... n

4Ii
4Z
38
34
-S.O

=

=-18.5V

1

80

j58

..:

ill

.'"
...
'"=>
z

C

52
41

W- -11.SV

~

Power Supply Current .s
Clock Pulsoi Width I/lPW

VDO =-S.3V

I-

V.. = GND

I-

9,= 3.0 MHz

.. f-VG• - -18.5V I~-80

\

1'-

DATA'" Note 4

44

l"'- I-.,

4lJ

"" ......
'"

--+~:::~:;~c

TA -.+25"C

~:1::::t±:jj~iJ:..::J
-12

-14

i

52

j

SO

'i

4.7

~

4.6 1 4.$

/

........

-20

-18.5V·

YO --18.5V

VDD =;-5.3V

Voo =-5.0V
Yeo'" -11.0'v

,

V.=-11.DV
Vso - GND-

" '\

4.4
vGG '"

/

-18

4.3

f\.

4.2

V.. -GRO

32

44
TEMPERATURE re)

/

48

38
80

i-"""

/

54

-16

Maximum Clock Frequency
vs Temperature

./

56

46

4lJ

,...~

V¢(V)

58

\

~

,...

l./

V

.,...

16
-10

-6'0

I-

'7 ~ I-

...
....-: ...

./

V•• (V)

Power Supply Current vs
Temparature
68

DATA = NlltI! 4

l/

j4lJ

24

e-

VGG "'-11.5V

~ -5.1V -

TA=-55°C
T. = -2S'C
T. =O"C

32

-5.S

100 (mA)

voo

5&

~-

-1""1

t'f=3.0MHz

j'48

--

.J..r;'-O"e

:::r-~ _12$"~~

,,..,=8U. _Vss=GND

64

--

i---- f--IT.~
;....

72

T~-~55"bp

-

-~

'''"'';....

50 '~

0102030405060101090

14

Power Supply Current
vs Clock Voltage V q,

Power,Supply Current vs
VDD

PoWer Supply Current
vs Data Rate

120

¢t==lmHz

'/
80

4.1

DATA-N ... 4

90

..

100
~(

8-33

)

4.0

110

20

41

BO

80

TA""oC

100

120

140

typical performance characteristics (con't)

Typical Sink Current vs VGG

Maximum Data Rate vs VOO
10.0

r--'-"-T""--,r----.--,

2.4

f-tT l =.2
f-- TA =
"-

~

::'::>i

.~

....
'"
~

2.2
9.5

:(

.s....

........

9.0

I---+-+-+- o.w
8.5

=

80 n.

I--+-+-+- ~:'G:G~~5V

'2.D

I'"

1.6

z

;;

1.4

/

./ , /

85'C

I

~

Q

'"

r/
V

/,/

TA = +125 &

1.8

r--+-+-~r-~:~~:~
•.0
-4.5

,

12 r-~~~-r-~~~-,
Voo = Vss - 5.0V +-+V",ss_=,.:5.:::.0V:,.---/

/

15'C

'~"

Typical Data Output Source
Current vs Data Output
Voltage

V
V

V
V V V'

V /

~~~DD=V~-5.0V­

Vss '" +5v

V'

Voo '" GND

1/ V

~!B;;q...__+-VGG = Vss -12.0V_

VrjJ"'Vss·14.5V
VOUT '" O.4V

V

~

V.=VIS-12.0V _
T. = 125'C

1.2
-5.5

-5.0

-6.8

10

12

14.0

Vss - VGG

VOUT

typical applications
Memory Expansion

'L

r----- ------,t
'OPUTlOO--+__-;
~

INPUT SELECT A

INPUT1A

INDEPENDENT

,':'OT
----~

I
I
I

'1"'

10

"'t

---- -------,I
.
I
I

OUTPUT A

•
•
0--+---,

INPUT2A o-~---"""L'/
INPUT1B
INPUT

SELECTB

OUTPUT B

12

IN,uT2B

o-;----L..I

MM50Z61

--,1--~r--~[---.J
INDEPENDENT

VGG

Voo

INPUT
INPUT2B

TTL/MOS Interface
Vee
+5V' 5%

5

r---------v,,,---------,
I

I
I

INPUT

•

L----- r -86

10

VGG-12V

8·34

Vss

~
~

truth tables

~

o

N
U1

Positive Logic
~

Logic "1" = V 1H
Logic "0"

.......
Input Select A

Logical High Level

Function

1
0

N
U1

Select 'Input 26

1
0

Recirculate
Load Data

o

Function

Input Select B

Write/Recirculate

s:
s:U1

Function
Select Input 2A
Select Input lA

1
0

V 1L = Logical Low Level

==

Select Input 1 B

s:
s:
~

o
N

0')

.......

switching time waveforms

I

BIT TIMES

BITt

I

I

Bill

I

BIll

s:
s:U1

I

BIT'"

o

N

0')

"
"
"'"

DATA IN

I

I

I

I

I

I

I

I

I

I

LJ

I

LJ

I

LJ

I

LJ

I

LJ

I

LJ I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

s:
s:U1

I

I

I

I

I

I

I

I

~

n

DA,:~,IN

~OATAINI
1
'z
"0"

"I"

"I"

"1"

I

I

Lr

-+--+--+---I----l

CATAOUT:.

enters the register at 1 time, it exits at 1 time,
(beginning on 1>1" negative going edge and ending
on the succeeding 1>2', negative going edge),

Shown is a simplified illustration of the timing of
a 4-bit multiplexed register showing input output
relationships with respect to the clock, If data

timing diagram
_~,

BIT N+2

BITN+l

BIl2

BIT 1

8ITI

'''r--r

~-----V~

"

CLOCK

I,

,~--<

:-,
-+-l

"

4>~:--:-I,
i
'-,--,-CLOC)(PERIOO--_I

__ jl

I

~_: i~
I

t,.,

90%-iu~ _________

,-- 91 %

_ _ _-+'+-'".,.;.1

CLOCK

s:
s:

I

I

I

I!
II

I

~l!~11--

v"

--!l-<:'>t,

1JTl[
I

V

I

-r-I

;;;;,..:

I

I

I

II

I

I

1-- I

I

I

'I

I

I

.I---OATA PERIOD---I

:

\

O"

VOl

i'( ____.________ ~~--_-----~-:-+-----:------'v . .

\.iNiiT~

--I

Opw

IN81TZ

t.,dt.-\ :_

(

__:

:_tpd~

V'L

;:;:;,;U-;-----------------~ill----------1------JE~~VABOVfGNO(V oo !
OUT BIT I

8-35

BUT BIT Z

~

o

N

....

.......

o

Shift Registers
MM4040/MM5040 dual 16-bit static shift register
general description
The MM4040/MM5040 dual l6-bit static shift
register is a monolithic integrated circuit utilizing
P channel enhancement mode low threshold technology to achieve direct bipolar compatibility on
the inputs and outputs. The device requires only
a single phase clock.

•

Bipolar compatibil'ity

2.2 MHz guaranteed

applications

features
•

High frequency operation

• Single phase clock

• Static data bu ffer
• Serial memory storage

+5, -12V operation
No pull-up or pulldown resistors needed

•

Printer memory

•

Telemetry systems and data sampling

connection diagram
Metal Can Package

v,,

TOP VIEW

Order Number MM4040H or MM5040H
See Package 23

typical application

·,v

I
I
I

7

I

L_J;:_J

ANY OTLITTl DEVICE

-1ZVdc

8-36

ANY DTLITTL DEVICE

s:
s:

absolute maximum ratings
Voltage at Any Pin

~

o
~
o
......

Vss + 0.3V to Vss - 22
_55°C to +125° C
O°C to + 70°C
_65°C to +150°C
300°C

Operating Temperature Range MM4040

MM5040
Storage Temperature Range

Lead Temperature (Soldering. 10 secl

s:
s:c.n
o
~
o

electrical characteristics
T A within operating temperature range, Vss

~

+S.OV ±5%, Vss':' Voo = 9V to 18.5V, VGG -= -12V ±10%, unless otherwise specified

PARAMETER

CONDITIONS

Data I nput Levels
Logical High Level (V,HI
Logical Low Level (V,LI

TYP

Vss - 2.0
Vss-18.5

Data Input Leakage

V ,N = - 20V. T A = 25'C.
All Other Pi ns GN 0

Data I nput Capacitance

V ,N = O.OV. f = 1 MHz.
All Other Pins GND (Note 11

Clock Input Levels
Logical High Level (Vq,HI
Logical Low Level (Vq,LI
Vq, = -20V. T A = 25°C.
All Other Pins GND

Clock Input Capacitance

Vq, = O.oV. f = 1 MHz.
All Other Pins GND (Note 11

Data Output Levels
Logical High Level (VoHI
Logical Low Level (Voe!

ISOURCE = -0.5 mA
ISINK = 1.6 mA

Power Supply Current

TA

MAX

Vss + 0.3
Vss-4.2

2.5

VSS - 1.5
Vss - 18.5

Clock I nput Leakage

V
V

0.5

MA

5.0

pF

Vss + 0.3
Vss - 14.5
1.0

19

UNITS

22

V
V
MA

pF

0.4

V
V

2.4

= +25°C. V GG. = -12V.
q,pw = 200 ns. Vss =5V.
Voo = -12V. Vq,L = -12V.
Data C' o-1-0~1

IGG

100

0.01 MHz:S q,1:S 0.1 MHz

1.0

2.0

mA

q,,= 1.0 MHz
q" = 2.0 MHz

1.8

3.0

mA

3.0

4.0

mA

0.01 MHz <; q,,:s

0.1 MHz

5.0

9.0

mA

=
=

1.0 MHz

5.1

9.0

mA

2.0 MHz

5.2

9.0

mA

q"
q"

q,t, = 20 ns

Clock Frequency (<1>,1

<1>t, =

Clock Pulsewidth (q,pwl

<1>t, + t,1

DC
.200

3.0
.100

q,t, + 
Delay to High Level (tpdH I
Delay to Low Level (tode!

See test circuit

Note 1: Capacitance values are 'guaranteed by statistical lot sample testing.

200
200

300
300

ns
ns

guaranteed performance characteristics
Data I nput Levels vs
Supply Voltage

2.0 MHz Operating Curve

1.0 MHz Operating Curve
1000 r--r--r-,--r--r-.,---,---,

500

¢t,=¢l1t= 20 ns
\}f = 2.0 MHz
TA '" _55°C to +125°C

3.0

~
~
~

~

~

]:800
",=~f=~M

%

~

2.0

;:0.

~

0-

~
~

"
~

~

a: 1.0

~ 200

"

13

14

15

16

17

18

~- 300
5

Vss =+5.0V
V'L .. o.av
V1H"'l.DV
V~H =J.SV

400

0.

~

~

200

~

lDO

~

12 13

14

15

16

17

18

19

20

.....1-..

V¢HI-3~

-- TTMIN",."

I T

15

Vss - Voo '" Vss - VGG =Vss - V¢'L (VI

Vss - V¢L '" Vss - Voo = Vss - VGG (V)

l--""
.".

V'L" O.SV
V'H" J.OV

11

o

0'--'--'--'---'-'--'--'---'

19

VSS '" +S.OV

'"0-

1"'-+--+_t- 9fTA=-55~Cto+125°C
=1.0MHz

600

400

16

17

18

19

VsS - Voo '" Vss - VGG ;; Vss - V¢L (VI

typical performance characteristics
Data Output Source
Current vs Voltage

Data Output Sink
Current vs Voltage

~

12

~--r--r---r-~--~-'

10

k....,+-~~-I-_

!z

i

10.0 r-~~~-"--'-"""-""""

.s

8.0

DATA -'-0-1-11+-+-+--1---,,1

~

~ 6.0
~-4~~~-I-~~~~~

,....

rPt'" 1.0 MHz
¢1>w ::: 400 IU

cr

B

.~

~

Power SupplV Current
vs Voltage

J

4.0

1--+-t7"I7.-t!"~~-l---4--I

> 2.0

b",j..""F'--+--I--t...cc.-i---+--l

~

4

a

'"
O'-......_.J.---'_...L.-,...'--'
-1

14

-1

5

18

16

20

VatJT IVI

VaUT (V)

Power Supply Current
vs OPerating Frequency

Power Supply Current

Power Supply Currant

5.0 ,---,---,,""""-r-...,.--,----.

5.0 r-T""T"TTT1mr-'-TTf",.,,-,rnrrTrm

<

..!

VGG::: -12.0V
DATA -1-11-1-0
cj)pw=200ns

4.0

~

'"~

Vss '" +5.0V
V¢lL = -12.0V

Vo;I!H = 3.5V

J.O

g

~ 2.0

¢1 '" 2.0 MHz

ffi

~T~ :0~~;_1_0

;:: 1.0 ~-4--I---I- Vss _ +5.0V
V

.......

s:
s:

MM4050A/MM5050A dual 32-bit static shift register
MM4051A/MM5051A dual 32-bit static shift register-split clock

U1

o

U1

o

l>

general description
The MM4050A/MM5050A and MM4051A/
MM5051 A dual 32-bit static shift registers are
monolithic MOS integrated circuits utilizing P
channel enhancement mode low threshold technology to achieve bipolar compatibility_ Operation
to 2_2 MHz is achieved with a single phase clock.
The MM4051A/MM5051A is a bonding option
of the MM4050A/MM5050A to provide independent clock control of each register.

features
•

Bipolar compatibility

+5V, -12V operation
No pull-up or pulldown resistors needed

•

High frequency operation

dc to 2.2 MHz

•
•

Single phase clock
Improved drive capability

Push-pull outputs

•

Military and commercial temperature ranges
MM4050A, MM4051A
_55°e to +125°C
MM5050A, MM5051A
oOe to +70 o e

13

OUTPUT A

....

•

Serial memory storage

l>

•
•

Printer memory
Telemetry systems and data sampling

Metal Can Package

Metal Can Package
Vo•

INPUT B

NC

NC

NC

V"
TOP VIEW

TOP VIEW

TOPVIEW

Order Number MM4050AH or
MM5050AH
See Package 23

Order Number MM4050AD or
MM5050AD
See Package 2

Order Number MM4051AH
or MM5051AH
See Package 23

typical applications
TTLIMOS Interface

TT LIMOS I ntertac.
+,y

ANY Oll/TTl

ANT DUfTn
DEVICE

MM4050AfMM5050A

s:
s:
o

NO

CLOCK"

~

U1

OUTPUT B

NC

~

applications

" V,,

NC
INPUT A

o

U1

logic and connection diagrams
Dual-In-Line Package

s:
s:-I=>

DEVICE

MM4051AIMM5051A

absolute maximum ratings
Voltage at Any Pin
Vss + O.3V to Vss - 22V
Operating Temperature Range MM4050A/MM4051A _55°C to +125°C
O°C to +70°C
MM5050A/MM5051A
_65°C to +150 o
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
300 0

e
e

electrical characteristics
TA within operating temperature range, Vss = +5.0V ±5%, Vss - V DO = 9V to 18.5V, VGG =- -12V ±10%, unless otherwise stated.
PARAMETER

CONOITIONS

Data I nput Levels
Logical HIGH LeveIIV ,H )
Logical LOW Level (V ,L )

TVP

V ss - 2.0
Vss - 18.5

Data I nput Leakage

Y'N = -20V, T A = 25°C,
All Other Pins GND

Data Input Capacitance

Y'N = O.OV, f = 1 MHz, All Other Pins GND
(Note 1)

Cl.ock Input Levels
Logical HIGH Level IV. H)
Logical LOW Level IV. cI

2.5

Clock Input Leakage

Vq, = -20V, TA = 25°C, All Other Pins GND
Vo = O.OV, f = 1 MHz, All Other Pins GND
INote 1)

MAX

UNITS

Vss + 0.3
Vss - 4.2

V
V

0.5

ilA

5.0

pF

Vss + 0.3
Vss -14.5

Vss - 1.5
Vss - 18.5

Clock Input Capacitance

Data Output Levels
Logical HIGH LevelIV oH )
Logical LOW LevellVoL)

MIN

1.0
25

35

ilA
pF

0.4

V
V

rnA

2.4

'SOURCE == -0.5 rnA
ISINK = 1.6 rnA

V
V

Power Supply Current
IGG

TA = +25°C, VGG = -12.0V, 'Pew = 200 ns
Vss = +5.0V, V¢L = -12.0V, Data = 0-1··0-1
Voo = -12.0V
0.01 MHz <:: , = 2.0 MHz

4.6

11.0

mA

<::,<:: 1.0 MHz

2.9

5.0

mA

<1>, <:: 2.0 MHz
Clock Frequency (1),)

t, + t" t,)

t, + t, +  1.0

-1
VOUT

8.0

.-,.---r----r-,-..,.........,.-r--1
f/!f='Z,O MHz

t

9pw""400ns

6.0

DATA = l-D-l-0'+-f-+--4---1

Vss=+5.0V

Z

~

5.0

g

4.0

::i

3.0

~

2.0

l "" Vss - VGG (VI

14

16

18

20

lL'

~ 2.0

.
~
..

1.0

Wlill I5~.1.t ~ 1
1111111 - III (I
TA"'25°C~
V
+lZ5°C

o

::
~ 2.0

12

-

Power Supply Current
vs Operating Frequency

l '" -12.GV
VH)
Logical Low Level IV L!

.01
3.0

Vss - i.5
Vss -18.5

Clock I nput Leakage

Y'N = -20V, TA = 25°C
All other pins GND

Clock Input Capacitance

Y'N = O.OV, f'= 1.0 MHz
All other pins GND

Data Output Levels
Logical High Level. IV OH)
Logical Low Level (VOL)
Logical High Level (V OH )
Logical Low Level IV OL)

ISOURCE = -500 pA
ISINK = 1.6 mA
ISOURCE = -10 pA
ISINK = 10 pA

Power Supply Current

TA

(cp,)

Clock Pulse Width Icppw)

MAX

UNITS

Vss - 4.2

V
.y

0.5

pA

5.0

pF

Vss
Vss - 14.5

V
V

1.0

pA

22

28

pF

2.4V

4.8
.,3.0

Vss -1.0

Vss
Vss - 12.0

Vss
0.4
Vss
Vss - 7.0

V
V
V
V

9.5

12.5

mA

12.0

16.0

mA

200
200

300
300

ns
ns

= 25°C
cp, = 1.6 MHz
VGG = Vss - 17V
VL = Vss - 17V

(I GG ) MM4053/MM5053

Clock Frequency

TYP

Vss - 2.0
Vss - 18.5

Data Input Leakage

Propagation Delays from Clock
Propagation Delay to a High (tpdH )
Propagation Delay to a Low (t pdL )

±10%, unless otherwise specified.

MIN

CONDITIONS

PARAMETER
Data Input Levels
Logical High Level IV ,H )
Logical Low LeveIIV ,L )

(lGG) MM4052/MM5052

= -12V

See waveform
See- waveform

See operating curves

0

1.6

MHz

See operating curves
CPt, + C
V1L = O.BV
VIH=3.0V

100

o

20

-

!AxL

.......

!~"1~80~Hz

"'-'

"'-'
Q

"

~

w

i2

("

300

Level vs Supply Voltage
~
,;

~

:!

..."
Q

::>

1.4

1.2
1.0

.8

x

,."

12

14

tV)

16

20

18

Vss - VGG (V)

typical performance characteristics
Data Output Sink Current
vs Data Output Voltage

Data Output Source Current

vs Data Output Voltage

Power Supply Current
.10

10.0

"1
§
~

'-'

g;

VGG '"

Vss '" 5.0V

-12V

4.0

I-V_""-!.f-5_.0_V-l----1---1-+_+-7"'1

3,0

1--1--1-+-,+-'7"1-71

2.0 1---1---+~"'-7""'--I-:c----1

2

...

~

1.0 1---i6'~'-+--l--I----1

g

..-

.§

8.0

iB

6.0

ill

4.D

~

2.0

...
...

in

;::
;;;

4.0

3.0

2.0

1.0

0.0

TA "'-+25°C
f. "" 1.0 MHz

'"

DATA:c 1-0-1-0

~

"

.§

."
ffi

>

"

VGG '" -12V
Vss '" S.OV

-1.0

5.0

4.0

3.0

2.0

1.0

0.0

V

L.
.04

I-

I--""

.02

-1.0

12

16

14

VOUT (V)

VOUT (V)

V

.06

0
0

w

Q

5.0

4wt,. 250ns
.08

18

20

Vss - VGG IV)

Power Supply Current
.10

111111111

;::
;;;

'"~

"

.08

t-

i; ~I~~~.c I

.06

t-

TA _+25°C

!LI

.§
0

a
w

"'"
'"~

.D4
.02

11111111 I

=~815<>C Il- TA
(·1111111 (I VGG'-12V

11111111 II ~:'T~:~~l..g
11111111 11 ..... 250 ..

"

o
10

100

1000

10,000

OPERATING FREQUENCY 1kHz)

switching time waveforms

ac test circuit

DATA INPUT

5.0V

.K
DATA OUTPUT O-.........-

8-44

-+..........,f'II-...+--IIIf--,

...

Shift Registers

~

NAll0NAL

MM5054 dual 64/72/80-bit static shift register
general description
The MM5054 dual BO-bit static shift register is a
monolithic MOS integrated circuit utilizing silicon
gate low threshold technology to achieve complete
bipolar compatibility. The device has input and
output taps that also provide register lengths of
64 or 72 bits.
The single phase bipolar compatible clock lines
may be driven by any conventional DTL or TTL
circuit. The registers may be operated asa dual
register by connecting the clock I,ines A and B
together. or as two independent registers, Two
clock control lines provide independent logical
control of the shift register clock lines,

• Standard supplies

features

applications

•

•

• Single phase clock
•

Complete bipolar compatibility
DTLlTTL
input/output and
clock line compatibility
without additional
components

DTL/TTL compatible
on-ch ip clock driver

Low clock line capacitance

• System flexibility

•

+5.0V. -12V
DC to 3.0 MHz typ

High freq. operation

8.0 pF max

Split clock or common
clock operation. Logical
control of clock lines
<600 /lW/bit typ

Low power d,issipation

• Teletype data buffers
• Printer memory - 80. 128, 136. 144 bit lengths
• Telemetry and data sampling systems
• . Serial memory storage

logic diagram
DATA
OUTPUT

DATA
INPUT
l,1S

3.13

DATA
INPUT

2,'40------'

4,12

CLOCK

1,90----{-"'\

CLOCK
~ONTROL

6,10

The unused data inputs and clock controls should be CDnnecteti to Vss to ensure proper operation
logic diagram shows 1/2 of the unit.

truth table

connection diagram
Dual-In-Line Package
INPUT-A-12/80 1

16 'voo

INPUT-A-ti4I12 2

15 INPUT-B-n/aD

OUTPUT-A-7l/811 3

14 INPUT-8-64/72

OUiPUT-A..fi4112: ..

lJ OUTPUT-a-Wall

Ne 5

12 DUTPUT-8-64n2

Positive Logic

CLOtK CONTROL A &
CLOCK A 1
v~

10 CLOCK CONTROL B

•

I

CLOCK B

TOP VIEW

Order Number MM5054D

See Package 3
Order. Number MM5054N

See Package 15

8-45

CLOCK
CONTROL

CLOCK

Low

Inhibited

High

Active

absolute maximum ratings
Vss + 0.3V to Vss -20V
O°C to +70°C
-65°C to + 150° C
300°C
600 mW@25°C

Voltage at Any Pin
Operating Ambient Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
Power Dissipation

dc electrical characteristics
T A within operating range, VGG '" -12V ±10%, Voo = GND, Vss
CONDITIONS

PARAMETER
Data., Clock Control, and Clock Levels
Logical High Level (V IH)

~

5.0V ±5%. unless otherwise noted.
MIN

TYP

Vss - 1.5

Vss +0.3

Vss - 42

Logical Low Level (V 1L )

Input Leakages

VIN -;;- -lOV, T A'" 25°C
All Other Pins GND

Data Input Capaci tailee

VIN = av, f"'" 1.0 MHz
All Other Pins GND (Note 1)

Clock and Clock Control
Capacitance

VIN "'OV,f== 1.0 MHz

Logical High Level (V OH )
Logical Low Level (VOL)
Power Supply Current
::0

Iss)

UNITS

V
V

0.5

/lA

4.5

6.0

pF

6.0

80

pF

.0.15

04

7.0
5.0

8.0

INote 11
(Figure 1)

Data Output Levels

(lGG + IDD

MAX

IGG
IOD

24

Iso URCE == -0.5 mA
ISINK

:=

1.6

mA

9, =1.5 MHz. TA = 2S"C
Vss = S.OV, V OD = GND
VGG = -12V

Vss

10

V
V
mA
mA

ac electrical characteristics
TA within operating range. VGG =-12V ±10%. Voo = GND. Vss = 5.0V ±5%. unless otherwise noted.
PARAMETER

MIN

TYP

¢t r , ¢tf::; 10 ns INote 21

DC

¢pw

¢t r :;: ¢tf -:; 10 ns

0.25

¢pw

¢t r

0.38

Clock Frequency (¢If)

CONDITIONS

MAX

UNITS

3.0

1.5

MHz

0.180

10

Clock Pulsewidth (¢pw)

=

¢tf -:; 10 ns

/ls
/lS

Clock Transition Times

500
500

Clock'Risetime (q,trJ

Clock Falltime (¢t,1

ns
ns

Clock Control Setup Time (tcs)

(Figure 1) ¢t r ""'¢tf = 10 ns

0

ns

Clock ,Control Hold Time (tch)

(Figure 1) tf "" 10 ns

0=

200
200

Delay to Output Low Level Upd d

Note 1: Capacitance is guaranteed by periodic testi ng.
Note'2:

For static

oper~tion clock must remain at VI L.

8-46

300
300

ns
ns

typic._ performance characteristics
Typical Data Output Source
Current vs Deta Output Voltage
&.I

...
C

r-..:

4.11

I'

.!

Ia

I

-....:

.L.J

""'-

~

1.0

&.0

~

,,~

o

I-

0:
0:

1••

o

7.0

....'"
"'

I' ~

I

C

oS

I"'- ~

I!l u

II

B.O

III

4.11

h

1.0

o 1.1
o

~

Q

~

0.2

10

7.0

11111

0.4

1.0

11111

'.0

'T~=II"C

1.0

-

~~'+z5·e

3.1

-

TA -+70"C

II

z.o

I'l

1.0

1;1

o

10k

lOOk

i..o'
~

po

oS

r-

11111

3.0

,/

V

",

lOOk

13

14

?:

;;:

2.0

!!

1.0

~
~

I-

f

r-;~ """O"CIV

=oO--I~II,...._I"'' -I.*'-I.*'-t.*'' ' !
T

' 'l

.=--~-------

-w~--

________--J

"r-----------------

_ _ - - - - _ _ _ oJ

1,-.- - - - - - - - - - - - - - - - -

1IIa.T£:ALtTIMUMEASUREOwtTH,ft~TO_POllns

FIGURE 1

8-47

FIGURE 2

~

Shift Registers

NA110NAL

MM4055/MM5055 quad 128-bit static shift register

MM4056/MM5056 dual 256-bit static shift registe"r
MM40571MM5057 512-bit static shift register
general description
The MM4055/MM5055, MM4056/MM5056,
MM4057/MM5057 512-bit static shift registers are
MOS monolithic integrated circuits using silicon
gate technology to achieve bipolar compatibility.
They have a guaranteed operatin!! frequency of
1.0 and 1.5 MHz respectively, and an on chip clock
generator allows TTL level clock driver for complete TTL compatibility.

• Low clock capacitance
10 pF (typ)
.Operatesfrom+5.0V,GND,and-12V
•

•

features

Three configurations
MM4055/MM5055
MM4056/MM5056
MM4057/MM5057
I nternal reCirculate

Ouad 128 bit
Dual 256 bit
Single 512 bit

applications

•

Guaranteed operation
O°C to +70°C
1.5 MHz
1.0MHz
-55°C to +125°C
• Single TTL compai:ible clock, on chip clock
generator

•
•
•
•

CRT displays
Terminals
Disk and drum replacements
Buffer memory

connection diagrams
Dual-In-Line Package

t5 NC

., ,

"

INPUT A
OUTPUT A

"

OUTPUT I

.fRlUTC 5

v.

Dual-In-Line Package

Metal Can Package

1'''110

RECIRCUUTI

OUTPUT 0

Dual-In-Line Package

RECIRCULATE

11 ''''UTD

,omUT

V.

,.

V"

Voo

OUTPUT I

lltVGG

I

.,

'",UT
It

IIilPUTI
OUTPUle

.

RfCIRCULilHE
Voo

RECIRCULATE

V'"

',.

v.

0"

TO'VlfW

TorVIEW
TtPVIEW

Order Number MM4055D
orMMS055D

Order Number MM4057D
orMM5057D
See Package 1
Ordor Number MM50S7N
See Package 12

Order Number MMS056N

See Package 13

See Package 3
Ordor Number MMS05SN

See Package 15

logic diagram

R..,'CONTROL
RCULAT':

~
.

~

DATA
INPUT

".BlH"

~

8-48

~~:UT

Order Number MM4056H
orMM5056H
See Packago 24

absolute maximum ratings

(Note 1)

Data and Clock Input Voltages and
Supply Voltages with Respect to Vss
Power Dissipation
Operating Temperature Range
MM5055. MM5056. MM5057
MM4055. MM4056. MM4057
Storage Temperature Range
Lead Temperature (Soldering. 10 seconds)

+0.3V to -20V
600 mW @ T A = 25°C
O°C to 70°C
_55°C to 125°C Case
-65°C to 160°C
300°C

electrical characteristics

(MM4055. MM4056. MM4057)

T A = -55°C to +125°C. Vss = 5.0V ±5%. VGG =~12V ±5%. Voo = OV. unless otherwise noted.
PARAMETER

MIN

CONDITIONS

MAX

UNITS

Vss +0.3
Vss -4.2

V
V

0.01

0.5

pA

4.5

6.0

pF

TVP

Data, Recirculate and Clock Input Levels

Logical High Le.el (V,HI
Logical Low Level tv IL)

VSS - 1.0
Vss - 15.

V1N

-lOV. T A

2.Soc

Data. Recirculate and Clock Input
leakage

All Other Pins GND

Data I"put Capacitance

VIN =OV.! = 1 MHz

IE:

."

All Other Pins GND (Note 2)

Recirculate Input Capacitance

V,N =OV.!=1 MHz
All Other Pins GND (Note 21

3.0

6.0

pF

Clock Capacitance

V,N =OV.!=' MHz
All Other Pins GND (Note 21

10

14

pF

Data Output Levels
logical High Level (V OH )
Logical Low level (VOL)

'SOURCE'" -0.5 mA

Vss
0.4

V
V

6.5
10.5

9.ll
15.5

mil

13
15

18
20

rnA
rnA

2,2

1.0

MHz

0.280
0.180

ui

ps

de

po

Power Supply Current

ISINK ""

TA

'"

2.4
Voo

1.6 mA

25°C, VGG :::: -12V. Vss

Voo = OV. ¢,.w = 230 ns
Data = 0·1·0·1 •••

IGG

~f

$0.1 MHz

iI>. $1.6 MHz
100 (Note 41

~.

~.

= 5.0V

.

$0.1 MHz
$1.6 MHz

Clock Frequency (¢Of)

¢tr. cf>tf '$.10 ns (Note 5)

Clock Pulse Width
(¢,.wI
(¢,.wI

lPtr. tPtf

~ 10 ns (See ac Test Circl.!it)
rAtr. fIItf ~ 10 ns (See at Test Circuit)

0.400
0.400

rnA

Data Input Setup Time (tel,)

260

os

Data Input Hold Time (td H)

120

os

260

os

120

ns

Recirculate Setup Time (tdsl
Recirculate Hold Time (tct H)

t,.,tf~10ns

For Load Conditions See ac T~t Circuit

Data OutJl.lt Propagation Delay

[)Olay to High Level  level IV I HI
Logical Low Level (V Id

0.G1

0.5

~A

V,,, = OV. f = 1 MHz.
All Other Pins GND INote 2)

4.5

6.0

pF

V'N=OV.f=lMHz.
All Other Pins GND INote 21

3.0

6.0

pF

V'N=OV,f=lMHz.

10

14

pF

Vss
0.4

V
V

Data, Recirculate and Clock Input

V,,, =-10V. TA = 25°C

Leakage

All Other Pins GND

Data Input Capacitance
Recirculate Input Capacitance
Clock Capacitance

All Other Pins GNO (Note 2)

Data Output levels
Logical High Level (V OH)

'SOURCE'"

logical Low Level (Vod

'SINK = 1.6 rnA

Power Supply Current

IGG

100

INote41

Clock Frequency (;,)

-0.5 mA

2:4
Voe

TA = 2S'C.VGG =-12V. VS$~·5.0V
Voo =9V,t/Jpw ;; 230 ns
Data = 0·1-0-1 •••
<1>,:<>0.1 MHz
<1>, :<>2.2·MHz

6.5
13

9.0
19

rnA
rnA

<1>,:<>0.1 MHz
<1>,:<>2.2 MHz

13
15

18
20

rnA
rnA

3.0

1.5

MHz

0.100
0.100

100
de

<1>". ¢,. :<> 10 ns INote 51

Clock Pulse Width
lPml
I¢,.wl

rptr. if'tf '$; 10 os
t/ltr. 'hf ~ 10 ns

0.230
0.300

~
~s

Data Input Setup Time (tds)

110

ns

Data Input Hold Time It"H I

40

ns

Recirculate Setup Time (tc.,)

110

ns

40

ns

Recirculate Hold Time h dH )

...... S IOn.
For Load COMitions See Test Circuit

Data Output Propagation Delay
Delay to High Level (tpdH}
Delay to Low Level (tpdd

250
250

345

345

ns
ns

Note'1: "Absolute Maximum Ratings" are those values tieyond which the safety of the aevice cannot be guaranteed. Except
for "Operating Temperature. Range" they are not meant to imply that the devices sheuld be operated at these limits. The
table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Positive true logic notation fS used:
Logic ",,. = most positive voltage level
logic "0" = most negative voltage level
Note 4: Outputs not loaded when mea~uring 100. A?d 1.6 mA to IDO for each
Note 5: For static operation clock must remain at. VIL.

8-50

,TTL

load to compute worst case power.

3:
3:

typical performance characteristics

.I:Jo
0

UI
UI

......
Typical IDD

VI

F~.ncy'

Z8

18
16
14

1
J

Typical' IGG
Frequency

Clock
,

Illlll~hl

20

11*
1.-J!

16
14

...

~.~

12
10 ~
1.0

I--'
C
.!

w
.II

DATA-HI·l ..

6.D

V.. ·s.ov
voo·OV
1~1'm' -12~ III

4.D

2.0
lDOt

11111
~

21

1.

V.. ' GND
Vss= +S.OV
DATA· 1-0-1-0./

IS

1

12
10

......

..9

12

I.D

10

2.0

"

-

~~

ot=1.0MHz
TA =+2S·C
Iss '" IGG + tDD

14

10

.

C

.!

.II
5.0

3:
3:
.I:Jo
0

UI

en

......
15

16

3:
3:

18

11

UI

(V.. - VGG) (V)

Of 1Hz)

UI
UI

.

IS

~

'3

- CLOCK FREQUENCY (Hz)

V

./
'GG

4.0

./

.... ~

6.0

111M

1M

3:
3:
en
0

Typical Power Supply
Current YO VGG

Clock

,.

Ili'''-

-

YO

0

UI

en

3:
3:
Typical Input Lewis
3.0

.'"

-..

~

C1Irve

VGG

{~'I.IMHZ

Vss·+5.OV
VDD'GND

~·"'·le

TA • ~'ZSJC ClOCK

I0Il

..

..

!

V,•• O.BY
VI" ""3.SY

~
~

YO

7tI

If
~. •

2.0

510

I;

~

1110

4111

1.0

15

17

16

It

I

13

15

(V.. -

v..) (V)

T.,'-55·~
............. TA=+!!.':~""'"

~

_f""'"- . . . . -

I.e I---+---l-+-+-V+"-'-=;'=.=-D--i

.. ·~JN

VOUT'" DAV

12

13

14

IS

IV.. -

1&

v.. ) (V)

17

18

11

19

1.0

,..

"

~

i

Z.O

m
a: 1.5
B
~

1.0

i

0.5

a:

VOG --12V
YOD "'OND
V.. ·+5.IV
0.6

VOUT (V)

8-51

U1

0

......

>PWMI•

11

16

18

0.8

1.0

DI

VO"-

z.s

a:

8A

t:iw.;1-

Typical Data Output Source
Currant YO Dota Output

'/.

0.2

UI

I

(v.. - Vool (V)

/
h
h,

3:
3:

I--

IfIt s 2.8MHz
","'t, = 10 ns
V." +5.0V
Yoo -oV
15

1.

... ~ -I--

t:~~'+IZ~'C+---"I--;
~+~--t--+-V

16

, ,.. . . rIf~
4,.;...,:

5.0

3.0 I---+---l-_....."'-+---+--:::I

!

lDO

Typical Outplt Sink
Gerrelit VI De'" Output
Voltage

Typical Data Out""t SiAk
Currant vs VGG

Z.o

~

a

I I I I

14'

-

UI

~

J

iIIII~ssJ56/51TA = O'C w+l0'C

l

11--

I

It

300

~ zoo

~'~~=IDns

1""""-1.

= a.lv

V,"' 3.5V-, I I

S!

!'~ r- V,"' 3.5'
'"

V'L

l-

I- V,.· ..av

(V. - VGG) (V)

i.

..

!

~·C, '" 1.5 MHz
Vss;; S.OV
Voo "'DV
TA '" 2S"C

Vss '" 5.25

VGO _ -IZ.6V

TA -AIIBI£NTTEMP£RATUR£ I'C)

Typical Clock Pulse Width
vsVGG
'] 100D

,..... ·900

=333 ns

10 ZO ]0 40 50 60 70 80 90 100

19

18

Vss - ~GG (V)

TA - AMBIENT TEMPERATURE rC)

:! 1000

17

_

I--I-+-+--+- DATA IN - 1010 •.•

600

0
10 ZO ]0 40 SO 6U 70 80 90 100

OUTPUTLOAO = '..~~I:~~~

.,~

~

f- f-

-f-

c; SOD 1-;1:.....
=-+-1-1-

ffi

I

L

10

H-tIG!"

1000

I

-r

TA '25C_ ..

ZO
10

DATA'. '1010
Voo' BV

Vss::: +5.0V. VaG = -12V ---tVOD ::: OV
- fOUTPUT LOAD =1 TTL INPUT _
fDATA =1010 ..•

J~

j~

-....L I I

Guaranteed Power Consumption
vs Temperature

I

.~u~~~~~~AD - I TTllNPur
_·33Jm

]0

",

.... u

SO

I I I I

..'1 "'1.5MHz
9fw = 333 ns

~cr:

Typical Power Supply Current
vs Supply Voltage

~

10 nl.

VOL'

co

o

CD

o

It)

::IE
::IE

~

Shift Registers

NAnONAL

MM5060 dual 144-bit mask programmable
static shift register
general description
The MM5060 is a monolithic dual 144-bit static
shift register/accumulator utilizing a silicon gate
low thre·shold P-channel enhancement mode technology to achieve complete bipolar compatibility.
The device can be programmed by metal mask
option ·to custom lengths from 125 to 144-bits
in one bit increments.

register/accumulator in an 8-lead cavity dual-in·
line package. Pattern codes are assigned by: National upon entry of .order..

features
• Complete bipolar compatibility - input/output
and clock input completely DTL/TTL compatible without additional components

Standard Lengths:
MM5060AA
Dual
MM5060AB
Dual
MM5060AC
Dual
MM5060AD
Dual

• Standard Supplies

128-Bit Shift Register/Accumulator

+5V, -12V

• High frequency operation - DC to 3:0 MHz
typk~
.

132·Bit Shift Register/Accumulator

• Single phase clock - DTl/TTL compatible on
chip clock

133·Bit Shift Register/Accumulator

•

144-Bit Shift Register/Accumulator

6.0 pF max.

Low clock line capacitance

Custom Lengths:

applications

The programmed shift registers are assigned a letter
code for each option. These are deSignated by a
pair of letters after the number code but before
the package designation such as MM5060AD/D
which is a O°C to +70°C dual 144-bit shift

• Printer memory 144·bits per line

any length from 125 to

• Telemetry systems and data sampling
• Serial memory storage

logic and connection diagrams

Dual-In-Lina Package
LOAD
CONTROL

I

Vss

IN 2

IN I
LOAD
CONTROL
INI

OUTI
OUT2

OUTI

.'N
"N

vGG

IN2
OUTZ

TOP VIEW

Order Number MM5060AAiD,
MM5060AB/D, MM5060AC/D,
MM5060AD/D or MM5060XX/D
See Package 1
Order Number MM5060AAiN,
MM5060AB/N, MM5060AC/N,
MM5060AD/N or MM5060XX/N
See Package 12

truth table
LOAD CONTROL

INPUT

o
o

0

8·56

FUNCTION
Recirculate
Recirculate
"0" is written
"1" is written

absolute maximum ratings
+0.3V to -20V

Data and Cfock Input Voltages and Supply
Voltages with respect to Vss

600 mW@T A

Power Dissipation

= 25°C

Operating Temperature Range
O°C to +70°C (Ambient)

MM5060

_65°C to +150°C

Storage Temperature

300°C

Lead Temperature (Soldering, 10 sec)

electrical characteristics
TA within specified operating temperature range, Vss
CHARACTER1STICS

= 5.0V ±5%, VGG

CONDITIONS

-12.0V ±5%, unless otherwise specified.

MIN

TYP

MAX

UNITS

Vss + 0.3
Vss - 4.2

V

om

0.5

I'A

3.0

5.0

pF

Vss + 0.3

Vss - 4.2

V
V

0.01

0.5

I'A

3.0

5.0

pF

Data Input, Levels
Logical High Level (V IH)

Vss -1.5
Vss -10.0

Logical low level (V ,L )
Data Input leakage

Y'N = -10V. T A = 25°C

All Other Pins GND

Data Input Capacitance
Load Control Input Levels

Y'N = O.OV. f = 1 MHz
All Other Pins GND
(Note 1)

Logical High Level (V H)

Vss -1.5
Vss -10.0

Logical Low Level {VLJ

load Control Input Leakage

VIN = -,10V, T A ::;:: 25°C

All Other Pins GND

,

load Control I nput Capacitance

Y'N = O.OV. f" 1 MHz
All Other Pins GND

I

(Note 1)

Clock Input Levels
Logical High Level (Vq,H)
Logical Low Level (V rPL)

Clock Input Leakage

Vss + 0.3
Vss - 4.2

V
V

om

0.5

I'A

3.5

6.0

pF

0.4

V
V
V

24.0
25.0
26.0

mA
mA
mA

1.5

MHz

Vss -1.5
Vss -10.0
V~ : -1O.OV. TA : 25°C

All Other Pins GNO

Clock Input Capacitance
Data Output Levels TTL load
Logical High Level (V OH )
Logical High Level MOS Load (V OH )
Logical Low Level (V od
Power Supply Current (lGal

Clock Frequency (4tf)
Clock Pulsewidth (~pw)
(4)pw)

V,,: O.OV, t.: 1 MHz
All Other Pins GND
(Note 1)
3.0
4.0

'SOURCE ""-0.5 rnA
'SOURCE == -0.01 rnA
ISINK ;:; 1.6 rnA

25°C, VGG ~-12V
t r =-q,tf;;:;;

10 ns, TA

=

2SoC

10 ns, TA '" 2SoC

20.0
21..0
22.0
DC
0.300
0.200

3.0
0.100

Clock Pulse Transition (4tt p tj)t r )

100
DC

1"
1"

1

p.s
ns

Data' Input Setup Time (tds)

T A =25°C. t r ,tf =10ns

70

Data Input Hold Time hdh )

TA = 25°C, tr,tf == 10ns

50

ns

TA == 25°C, tn't f

10 ns

70

n,

50

ns

Load Cont..-ol Setup

(~$)

=

Load Control Hold ("h)

TA

:

2Soc, t r• tf = 10 ns

Data Output Propagation Delay from 4J in
Delay to High Level (tpdH I
Delay to Low Level (fpdd

TA

:

25"C, t r. tf == 10 ns
250
250

Note 1: Capacitance is guaranteed by periodic testing.

8-57

350
350

ns
n,

~

typical performance characteristics
Guaranteed Input Voltage
Levels vs Supply Voltage

Guaranteed 1.5 MHz

Operating Curve
600

26

T..

'+25"e
Y~L • UII
1I",,-l.511

~I,

500

'~~1Q

II.'

s.av

..

I

o.l"'lood·_'l:~~

.

-,

-

MAXIMU~ ~INPW

j
lOO

(I

"'

I

,

~

-16.0

-11.0

1-+-+-+--+-

0',
<"

z

,

~

!;<

..!: 20

-IB.O

1.0

-16.0

-11.0

18

~I~;r

-3.5

1111

\

TA - +JO·~T

r-tttm~A

Typical Power Supply Current
vs Voltage Under TT L Load

+25"C

111111111 III 111111 I
16
10 kHz
1 MHz
100 kHz

-IB.O

1.0

1-+---+--1--+-+-1-+---1

6.0

1....
~

a:
a:

..
~

5.0

r...~

i---

4.0

~

TA ~*J5·t=B=
__ TAI -I
+JO·~_

3.0

~

2.5

~ 2.0

I I
Ty+;O·C

0.5
+4.0

-2.0 -4.0

+2.0

OUTPUT VOLTAGE (V)

switching time waveforms

v..
,~

v"

v"
DATA

I.
v"

v"
LOAO
CONTROL

v,

VO"

DATA
OUTPUT

vo,

d~ring

VGG - -12.DV

TA - +25"C

1.0

VSS-VGG (V)

V.. - +li.OV

~ 1.5 ' i--~ 1.0

~ 2.0

11 L---...L----.l._.l--'---''--'----.l.--t
-16.0
-16.5
-11.0
-11.5
-IB.O

Typical Output Source
Current vs Output Voltage

Vss '" +5.0V
VGG '" -12.0V

TA = O"C

lDMHz

.,(MHz)

Typical Output Sink Current
vs Output Voltage

25 .-,..--,--,-,----,----,-,---,

p

,It,-O·C
.:'1] ,11111
I

Vss - VGG tV)

Vss - VGG (V)

Note: DC storage is accomplished

.Vrl

o

~ ~I~~e~~~~~~

'" 9t, = tOns

V.pl =. V1L =0.8

22

;: 2.0

!

Vss = +5.0
VGG :. -12.0
= 300 ns
Dlta '" t-O-l-D

¢pw

24

~
~

I I 'G~ARANTEEo.~::I POWER SUPPLY LIMITS

-15.0

3.0

....

,,

,,

MINIMUM tPl~PW

200

24

Typical IGG vs Clock
Frequency Under TTL Load

9pw time.

8-58

-6.0

o

o

1.0

2.0

3.0

4.0

OUTPUT VOLTAGE (V)

5.0

~

Shift Registers

NAllONAL

MM5061 quad 100-bit static shift register
general description
The MMS061 quad l00-bit static shift register is a
MOS monolithic integrated circuit using silicon
gate technology to achieve bipolar compatibility.
h has a guaranteed operating frequency of 1.S
MHz ani:! an on-chip clock generator.

• Low clock capacitance
10 typ, 14 max,
• Operates from +SV. GND, and -12V
• Configuration
Quad 100-bit
• Internal recirculate

applications
features

•
•
•
•

• Guaranteed 1.S MHz operation
• Single TTL compatible clock on chip clock
generator

CRT displays
Terminals
Disk and drum replacements
Buffer memory

logic and connection diagrams
Dual-In-Line Package

"

RECIRtUlAT£

-.".. ~. .".
-~":
.

.~

I.

NO

1J

, ' , , '

.

Voo

15 Ne

INPUT A

12

INPUTC

OUTPUT A
INPUTB

ourpUTe

OUTPUT

11 INPUTo

NO

1D

OUTPUT 0

DATA

Voo

INPUT

v"

'ON

TOP VIEW

Order Number MM5061D
See Package 3
Order Numbe, MM5061N
See Package 15

truth table

test circuit
'5V

'K

ANY
MM~lo-~'-~~-I~"+-~~

RECIRCULATE
CONTROl

FUNCTION

1

Data Recirculates

OUTPUT

0

T '·

PF

8-59

Register Accepts
Inpu~

Data

absolute maximum ratings

(Note 1)

Data and Clock Input Voltages and
Supply Voltages with Respect to V55
Power Dissipation
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)

+0.3V to -20V
600 mW @ T A = 25·C
O·C to +70°C
-65·C to +160°C
300·C

electrical characteristics
TA within operating temperature range. Vss = +5V ±5%, VGG

PARAMETER

= -l~V ±10%, unless otherwise specified.

CONDITIONS

Data I nput Level
Logical High Level (V ,H )
. Logical Low Level (V lci

MIN

TYP

Vss -1.5
Vss - 10

MAX

UNITS

Vss + 0.3
Vss - 4.2

V
V

Data Input Leakage

Y'N = -to.OV, TA = 25°C.
All Other Pins GND

0.01

0.5

/JA

Data I nput Capacitance
(Note 2)

Y'N = O.OV. f = 1 MHz,
All Other Pins GND

4.5

6.0

pF

Recirculate Input .Levels
Logical High Level (V H )
Logic~1 Low Level (V d

Vss + 0.3
Vss - 4.2

V ss -l.5
Vss - 10

Ii
V

Recirculate Input leakage

Y'N = 10.0V, T A = 25°C.
All Other Pins GND

0,01

0.5

/JA

Recirculate Input Capacitance

Y'N = O.OV, f ='1 MHz.
All Other Pins GND

3.0

6.0

pF

Clock Input Levels
Logical High Level (V OH )
Logical Low Level (V ad
Clock Input Leakage

om

V¢ = -10.0V, TA = 25°C.
All Other Pins GNO

Clock Capacitance (Note 21
Data Output Levels
Logical High Level (V OH )
Logical Low Level (VOL)
Power Supply Current (lGGJ

(locHNote 4)

10.0
2.B5

ISOUACE = -3.0 rnA
ISINK = 1.6 rnA

V
V

0.5

/JA

14.0

pF

Vss
0.4

V
V

TA = 25°C, VGG = -12.0V. ¢PW = 160 ns
Vss = +5.0V. VOL = O.BV,Data = 0·1·0·1
Voo = O;OV
4>,~O.l MHz
4>, = 2.2 MHz

6.5
1'3.0

9.0
19.0

mA
mA

4>,~O.IMHz

13.0
15.0

18.0
20.0

mA
mA

1.5

MHz

10.0
DC

/Js
/JS

4>,~2.2

MHz

Clock Frequency 4>1

t, = 4>t, ~ 10 ns

Clock Pulse Width 4>pw

4>tt

pw

Vss + 0.3
Vss -4.2

Vss - 1.0
Vss - 10.0

3.0

= 4>t, ~ 10 ns

0.230
0.200

4>~=4>t,~10ns

0.100

Data Input Setup Time (tdS )

100

Data Input Hold Time ItdH)

40

ns

100

ns

40

ns

Recirculate Setup (tclS)
Recircu!ate

Hol~ (tdH)

Data Output Propagat ion Delay
from 
Delay to High Level h odH )
Delav to Low Level !todd

t r • tt $; 10 ns
for Load Conditions see
Test Circuit

ns

250
250

350
350

n.
ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The

table Qf "Electrical Characteristics" provides .conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Positive true logic notation is used: Logic "1 or ;::: most positive voltage level; Logic "0" = most negative voltage level.
Note 4: Outputs not loaded when measuring 100 therefore 100 will increase by 1;6 mA for each TTL load (TTL "0" level
output!.

8-60

typical performance characteristics

Typical I DO

YS

2Q

C
oS

14

~

12

.....

a 10
.9.

VOO'" GND

~-~

18

I-'"

~
1 •• \~"'t.

Vss '" +S.OV

DATA - 1-8-1-0
15

DATA-l·D-HI

-

4.0

V.. ' 5.DV
VDO =oV

2.0

I~~~' -12V

I-- i--

91= 1.0MHz
TA=+2S"C ~

10M

12'

13

1000

800

~

600

...'"co

14

15

1&

11

400

""
~

31111

400

!

~

II'Ct..=9lt= 10ns

~

21111
100
0

14

15

300

ZOO

100

MIN~t-

I I

13

~

I I I I

I
1.2

16

11

18

TA

Y," -~-i-t--~-.,

Y,,-----....,
~

-tiittllt-+ffiHtftl
1M

10k

V1L :: O.BV V,:.... - l.OV

=J.~V

~.;.L =

O.BV

TA '" O"C to +10"C

.J J

t-~
GJAR~NTE~D <; g: t"["".1

-l

j

X-

i\.

OPWMIN

0. ""2.0 MHz

t,=1.'" 10ns
Vss'" +5.DV
Voo = B.GV

I I
16

17

V ss - VaG (VI

switching time waveforms

v"

-;;O'C

"'IHzl

15

Vss - V.. IV)

_ _ _ _-+'......+'

_+'

VIL - - - - - -.....

v~--------~-----_.
DAtA QUlPUT

yoc--------,--t--1"

1111

I-

18

VI~

·~A~l.

I

500

2

TA =+25°C

t-

Guaranteed 2.0 MHz Operating
Curve

I I I

Vss = +5.OV
Voo '" GND

700

~

12
10

111111111
lllJlllL ~

Guaranteed 1.0 MHz Operating
Curve

]

0

Vss-V .. IVI

.. - CLOCK FREQUENCY 1Hz)

900

oS

Iss '" IGa '" 100

1M

lOOk

C

l-

I••

18

15

1&
14

~

8.0

TVPicallGG vs Clock Frequencv
20

./

L. V

./

6.0

10k

,

21

loh

111111

18
16 f-

Typical Power Supply Currant
vsVGG

Clock Frequency

tt S;1U nsAl.l T1MESMfASURED FRDM 5D% POINTS

8-61

18

10M

~

Shift Registers

NAlIONAL

MM4104/MM5104 dynamic shift register
general description
. The. MM4104/MM5104 360/359, 228/287, 40132
bit dynamic shift register is Ii monolithic MOS
integrated circuit utilizing p-channel enhancement
mode low threshold technology to achieve bipolar
compatibility. The register lengths are lengthened
or shortened by hard wiring the length select line
to VGG or Vss. The lengths available are: 40,
288, 328, 360, 400, 560, 688; or 32, 287, 319,
359, 391, 446, 678.

• MUltiple length registers Electrically adjustable
360/359,288/287,40/32 bit
registers
250 Hz min. guar.
at 25°C
2:5 MHz max. guar.
over temp.

• Wide frequency range

features

applications

• DTLITTL compatibility

+5V, .., 12V power
supply. No pull-up
or pull-down
resistors required

connection diagram

• Data store
• CRT displays
• Business machine

Metal Can Package
YGG

LENGTH SELECT

DATA INPUT 1A
{3BO,Z8arN}

1

Y"
TOPVIEW

Order Number MM4104H
orMM5104H
See Package 24

typical applications
TTL/MOS Interface
+5Y

r.1,

r - - - - - 1,1

-~ _.t~
- -

MM4f04lMM5104

-- --- ---''Ty;;;--if'I--- -:'12V

...J

QIN

Note: VGG on pia 3 resuiu in a 288·bit Nlgisttr between pin lInd pin 4 and a 287·bit regisUr bttween pins 6 and 4.
TIle unused input (6 or 11 must be returned to Vss. Also, there is a 32·bit registtt between pins 1 .nd 2.
VSS OD pin 3 fBlUlts j'o a 360 bit register between pin 7 and pin 4 and I 359·bit rtgister I»etweeo" pins & and 4. The
unused input (8 or 71 must be r8ltuned to Vss. Also, there is a 4D·mt tegis~' IIe1wttn pins 1 alld 2.

8-62

absolute maximum ratings
Voltage at Any Pin
Operating Temnerature Ra'nge MM41 04
MM5104
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)

Vss + 0.3Vto Vss - 22V
-55°e to 125°e
_25°e to 70 0 e
_65°e to 150°C
300 0 e

electrical characteristics
(T A within operating. temperature range, Vss
PARAMETER

= +5.0V, ±5%, VGG = -12.0V
CONDITIONS

±1 0%, unless otherwise specified.)

MIN

TYP

MAX

UNITS

Vss +0.3

V
V

Data Input Levels
Logical HIGH Level (V 1H )
LogioalLOW LevellV,d

Vss - 2.0
Vss - 18.5

Vss -4.2

Data Input Leakage

Y'N = -'20.0V, T A = 25°C,
All Other Pins GND

0.01

0.5

pA

Data' Input Capacitance

Y'N = O.OV, f = 1 MHz,
All Other Pins GNO. (Note 3)

3.0

5.0

pF

Length Select Input Levels
Logical HIGH LeveIIV LsH )
Logical LOW Level (V LSL )

Vss +0.3
VGG

Vss
Vss-18.5

V
V

Length Select I nput Leakage

VIN '" -20V, TA = 2SOC.
All Other Pins GND

0.01

0. 5

pA

length Select Input Capacitance

V ,N = O,OV, f = 1 MHz,
All Other Pins GND, INote 3)

6:0

9.0

pF

Clock I nput Levels
Logical HIGH Level (V.pH)
Logical LOW Level IV"L)

Vss - L5
V,,=~20V,TA=25°C,

Clock Input Leakage

Vss + 0.3
Vss -14 ..5

Vss-18.5
0.05

1.0

V
V
pA

All Other Pins GND

Clock Input Capacitance

Vo = O.OV, f = 1 MHz,

85

100

pF

All Other Pins'GND, (Note 3)

Data Output Leveis
Logical HIGH LevellVoHI

ISOURCE ~

Logical LOW Level (Va d

'SINK

-0_5

2.4

rriA

Vss
0.4

1.6 rnA

==

V
V

Power Supply Current
TA =2SoC, VGG '" -12\1, q;pw "", 150 ns

IGG

Vss = S.OV, VOL = -12V, Oata = 0·1·0·1
0.01 MHz;:; ¢, S; 0.1 MHz

1.5

2.5

mA

1 MHz

3.5

5.0

mA

¢, = 2.5 MHz

7.0

10.0

mA

3.3

2.5

MHz

¢,=

Clock Frequency (IPf)

¢tr = ¢tf "" 20 ns, (Note 1)

Clock Pulsewidth (¢pw)

(jJtf

Clock Phase Delay ~nmes (¢d, ¢d)

INote 1)

Clock Transition Time (¢tr. '¢>tf)

¢tf +¢pw +'¢tr~

+ ¢pw + f
versus tempe'rature ,and TIN, TOUT versus ~emperature curves. The lowest guaranteed dock frequency for any temperature
can be attained by ,making TIN equal to TOUT.'The 'minimum guaranteed clock 'frequency is:

tPt(min) =

1

,

T,N + TOUT

,where TIN and TOUT do not exceed the guaranteed maximums.

Note 2: The curves are guaranteed by testing at a high temperature poin't.
Note 3: Capacitance is guaranteed by periodic testing.

8·63

,

ns

10

[;II

performance characteristics
Guaranteed MinifllllM Clock
Frequency Y$ Teoliperatura
(Notes 1.2)

Guaranteed Maximum TIN
and TOUT vs Temperature

(Notes 1. 21
100

Typical Power SUpply

Cllfrent YS Clock Frequency

10

10.0

r-

i

TfNorTouT"'ZOIns

l.O

If

~ 10

....

J
!§
! 1.0

'"

~

TIN

"

-Tout~

j

--

:~~5~~!

:"

1.0

;

125°,C
""'= i1J ns
Vss=5.0V
VGo "'-12.OV

O.l

V"L =-1Z.DV

.......

0.1

-60

-20

20

60

140

100

-;!II

TEMPERATURE ('C)

Typical Power Supply

-55'C:-

C

..sc

oJ?

3.0
2.5

100

149

~ I-

:::.

~

~

....
z
::!
II:

'-'
~

lB

10

=>

;;

....
=>
I!:
=>

D~TAill-'-r-'
17

10.0

...
'"
.

",=IMHz
.... ·150..

1.0
16

1.0
(MHz)

1Z

VS5 =5.8V

15

0.10
FRE~UENCY. ¢r

C

.!

V... = -12.OV

1.5

0.01

Typical OutpUt Sink
Current vs Voltage

~

2.0

DATA ~ O~':l!-:'.

CLOCK

-=-+-urc_
T.=25·C\

3.5

60

Typical OU"""t Source
. Cur.....t YS Volt....
1.--,...-,---.---,..,....,.-7'1

5.0

4.0

2U

AMBIENT TEIIIPERATURE ('C)

Current vS V GG
4.5

0.1
0.081

0.01

19

•

V.. - V•• (V)

-1

5

1

vourfVl

switching time waveforms

-1

VOUT(V)

ac test circuit

..v
4In '
EITHER

.AT··o-..........- ...i'IIt-..........IJ>tHJIt,

,DU",,"'

8·64

Memory Systems

~

NAllONAL

INTRODUCTION
The Memory Systems Division was organized in January,
1974. A substantial financial commitment has been,
made to this division by National Semiconductor which
has enabled the division to be fully staffed with the
best' engineering and manufacturing talent available
in the industry. In addition, the division has purchased
the latest in sophisticated design support computers
and computer controlled testing equipment.

Design Expertise
NMS specializes in memory systems; by working with
National, the customer's engineering staff is free to do
what they do best.
Advances in Technology
NMS provides continual technology lead for customer
(ask about our Guarantee Against Obsolescence).

Since its founding, the division has rapidly grown. The
major thrust of the divisi,on's effort to date has been in
the development and production of memory cards and
systems for the OEM market as well as the IBM Add-On
Memory Systems market.

Product Availability
Assurance of product during periods when component
availability becomes difficult. (Assurance is due to our
long lead procurement cycle and second sourcing policy).

In the OEM market, the diyision has focused on
standard/custom memory cards and systems currently
being shipped to large OEM manufacturers for resale
in CHT terminals, test equipment, phototypesetting
equipment, airline reservation systems, large display
systems, point of sale terminals, credit card embossing
devices, CRT cluster control,lers, editing terminals and
other applications.

NMS typically manufactures' 90% of the components
used in each 'memory module.
Inventory'
Reduction of customer inventory. NMS works closely
with our customers to establish production rates
and NMS inventories consistent' with customer,
objectives.

THE DESIGN,OF MEMORY SYSTEMS

The purchase of a complete memory system from
National reduces customer purchasing requirements.

The, three fundamentals essential in producing a cost
effe,ctive and reiiable semiconductor memory system
are:
• Proper choice of memory component
• Design integrity of system
• Intensive production testing from components
through entire system

Testing
This most critical el,ement in the production of memory
systems is a specialty at NMS.
Each memory system undergoes extensive testing in
National,'s production test facility. Tests include component burn-in; aging and full system test under
,controlled temperature environment.

National Memory Systems has focused on all three
fundamentals and in doing' so provides our customers
with complete turn-key products. We specialize in
assessing customer requirements, the writing of specifications for the customer when required, designing the
system after choosing the most cost effective components
and delivering fully-tested hardware-tested to an extent
that most customers, are unable to match.

NMS has made a substantial investment in production
test facilities. A customer typically is unable to make
this huge investment in facilities, test methods and
experienced personnel to ensure the level of product
reliability achievable at National.
Quality Assurance

"MAKE OR BUY" DECISION

National maintains product integrity from design through
all phases of manufacturing with two distinct quality
groups-Quality Engineering alld Quality Control.

One of the mosr difficult decisions, to make under
normal circumstances for the company that has a
memory systll/Tl requirement is whether the system
should be designed and produced internal to their
operations; or whether the decision should be to purchase memory systems from a company who specializes
in providing systems, such as National Memory Systems.

No other memory system supplier provides the extensive
testing and stringent quality assurance standards that is
available at NMS.
Price/Performance

Following are some of the reasons that our customers
have chosen National Memory Systems (NIiIIS) to solve
their memory system requirements.

National Memory Systems provides the lowest cost,
highest quality, highest performance memory products
available_
g·l

CUSTOMER SUPPORT

• Dedicated facility capable of throughput of
100,000 devices per month. E'quipment includes:

National Memory Systems recognizes the need for a
close customer relationship, since we are truly an
extension of the customer's design and manufacturing
staff. Each customer's support requirement varies;
however, the following are common to all programs:

• Despatch Oven Co. burn·in chamber
• Dedicated error loggers
• Custom designed controller/sequencer
• Burn-in temperature and period vary with each
memory component

• A program manager is selected during early discus·
sions to act as a single point contact at the factory
for our customer

Single Card Test Stations

• Technical ,and' Quality Control interfaces are
established with the customer' to assure proper
communications on design, testing and realiability
criteria

• Dedicated Macrodata MD·l00 (with "custom"
personality card) and error logger.
Note: Minimum of one test station is reserved for
each customer

• Periodic status reports to customer inclUding frequent
. design reviews during a custom development program

• Complete board functional test in ambient conditions. Tests include:

• Technical supervision on installation of prototypes
•

Implementation

of

warranty

repair

•
•
'.
•

procedures

• Correlation of test data to ensure accurate records
and continual quality improvement

Mem Scan
•
March
•
Checkerboard March.
Short Walk
•

• Close cooperation to guarantee delivery of product
on schedule as well as reaction to increased/decreased
proc\uction requirements

Walk Pat
Gal Pat
Complete Voltage Margins
Special "customer
required" tests and/or test
parameters

CUSTOM PRODUCT DEVELOPMENT CAPABILITY
Multicard Test Stations
National Memory Systems maintains a complete product
development staff and facility specializing in providing
cost effect solutions to a customer's specific memory
requirement.

•

Each custom development program consists of a design
team with a project engineer, his staff of engineers and
technicians, and services of design and drafting support
group. The schedule for a typical custom development
program may vary depending upon the complexity of
the program and the manpower loading to satisfy a
specific customer's requirement. Typical programs range
from 8 weeks to 15 weeks for delivery of prototype
units; Production quantities are available within 30 days
after prototype acceptance.

Equipment includes dedicated Macrodata MD-l00
(with "custom" personality card), error logger, card
cage assembly and temperature chamber.
Note: Minimum of one test sta,tion is reserved for
each customer.

• Testing is performed automatically under temperature conditions. Tests inclUde:
•
•
•
•
•
•
•
•

The Memory Systems Engineering Department works
closely with the National Memory Components Group
to provide the latest cost-effective custom designs to
,our customers using state-of-the-art components.

Mem Scan
March
Checkerboard March
Short Walk
Walk Pat
Gal Pat
Complete voltage margins
Special "customer required" tests and/or test
parameters

• Testing throughput of approximately 30 cards/week
per test station. Capacity easily increased'to accomodate multiples of 30 cards/week to satisfy customer
needs.

The Memory Systems Division has an excellent track
record of completing custom design programs on schedule
with rapid customer acceptance.

Special Purpose Logic Test Station
PRODUCTION TEST FACILITY FOR
MEMORY SYSTEM PRODUCTS

•

Component Burn-In Station

• Testing of this special circuitry is accomplished in a
comparison mode (with a working sample) on a
"Trendar 2000" digital logic test station

• Dynamic testing during burn-in includes automatic
voltage margining and standard pattern tests at
pre burn-in and post burn-in
'

Used to test special "custom" memory cards which
contain overhead circuitry not associated with
memory operation

• Special personality cards and test fixtures are
developed 'by Memory Systems Engineering for
specific customer requirements

• Manual test capability for voltage margining and
selection of specific pattern tests
9·2

MEMORY SYSTEMS QUALITY ASSURANCE

MEMORY SYSTEM PRODUCTS

Memory Systems Quality Assurance Department is su bdividec! into two basic groups: Quality Engineering and
Quality Control.

In the pages which follow you will fi(1d data sheets on
several of National Memory Systems' standard products
and systems_ If one of these products matches your
memory requirement, our applications department will
be pleased to provide detailed interface information_
Pricing and delivery information are available from your
local National Semiconductor regional office_

Quality Engineering has the responsibility of ensuring
that design parameters offer the utmost in reliability
by devoting technical expertise to memory design
engineering and. production test techniques •.

If none of the standard products satisfy your requirement, give our Marketing Department a call or contact
your local National Semiconductor regional office listed
in this catalog for details on how National Memory
Systems specializes in satisfying your "custom" memory
system requirements_ We would be pleased to learn of
your needs and will respond promptly with a.complete
'
technical and business proposal.

Quality Control maintains product integrity by practicing preferred commercial computer standards 'on
incoming, in-process and final inspection of all material.
Calibration of all test equipment is traceable to the
National Bureau of Standards and is scheduled and
performed on a regular basis. Memory Systems' vendors
are qualified by their ability to meet preferred industry
standards and scheduled delivery commitments_ Vendors
are periodically source and first article inspected to
maintain overall integrity.
By maintaining a close working relationship, Quality,
Control and Quality Engineering provide state-of-theart inspection and testing of all memory systems.

o
9-3

I

'7

M

U)

Z

~

Memory Systems
Advance Information

NADONAL

NS3-1 high density memory system

GENERAL DESCRIPTION.

FEATURES

The NS3-1 is a self-contained semiconductor random
access memory system with a maximum capacity of
128k x 22 bits or 256 bytes.

•
•
•
•
•
•
•
•
•
•
•
•
•

It is structured to provide a wide range of flexibility
to satisfy individual systems applications.
The memory is configured in four modular cards. Each
card has a maximum capacity of 32k x 22 bits (64
bytes). The memory can be modified to individual
system requirements.
The basic ·storage element is a 4k dynamic RAM which
provides speed, proven reliability and low cost. Memory
Flexibility is achieved by board de-population. Optional
features are provided. These include custom interfacing,
error correction, and double word control (40 bits
word structure).

Complete system
Semiconductor memory
High speed
Low cost
Compact
Accessories
Up to 128k x 22 bits (256 bytes)
32k x 22-bit modularity
Byte control
51/4" cabinet
Customized Interfacing
Error checkand correction
TTL compatible

Optional Features
•
Error check and correction
•
Parity generation/parity check
•
Double word control-40-bit word structure
•
Late data strobe
•
Custom logic interface
•
Custom system interface cables

A remote Self-Test unit is offered as an optional accessory which exercises the memory system.
The NS3-1 system is housed in a 5 1/4" cabinet and
contains its own power supply.

MEMORV STORAGE
CARDS

~-4

Modes of Operation

Envwonment

Write
Read
Read/Modify/Write

Operating O°C to +50°C
Non-operating -40°C to +80°C
Humidity 90% without condensation
Mechanical

Performance
Access Time
Read or Write Cycle
Read/Modify!Write Cycl.e

z
~
....

CJ)

TECHNICAL SPECIFICATIONS

Chassis 51/4" x 19" x 22112"
280 ns
430 ns
*610 ns

Interfacing
Elco 90 pin (plug)
Elco 90 pin (receptacle)

"Plus user data modify time

Memory Refresh
Logic Levels

This can be implemented to individual customer applications either in asynchronous mode or in an asynchronous mode allowing handshaking with the CPU_

All levels are TTl compatible

Terminations are optional

9-5

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o

Memory Systems

~

NAnONAL

~

MOSRAM 310 bulk storage system
256k words X 24 bits. 128k words X 48 bits.
64k words X 96 bits

GENERAL DESCRIPTION

FEATURES

The MOSRAM 310 is a random access semiconductor
memory system that requires only a timing and control
card to be a complete memory system.

•

Uses National 5280 4k RAM

•

Low Cost

The memory is contained in a 19" rack mounted chassis
that measures 12.0" H x 19.0" W x 11.5" D. The
standard configuration is 256k x 24; however, the
memory can be configured as either 128k x 48 or 64k x
96. Smaller capacities are available by depopulation,
and larger capacities are. obtained by utilizing multiple
chassis.

•

High Speed

•

Double Density Version Available Soon

• Separate Timing and Control Card
•

Expandable

• Multiple Configurations:
256k x 24 STD
1 28k x 48 OPtional
64k x 96 Optional

The MOSRAM 310 is a semiconductor memory system
that was designed to offer the user the highest performance and lowest bit cost available for bulk storage
appl ications.

9·6

s:

o

TECHNICAL SPECIFICATIONS

en

::rl

Environment

Performance

Operating
Non-Operati n9
Humidity

240 ns
460 ns
460 ns

Access Time
Read Cycle Time
Write Cycle Time

o°c to +50°C
---40° C to +80 0 C
To 90% Without Condensation

Mechanical (256k x 24)
19.0" W x 12.4" H x 11.5" D
10.5" x 11.0"

Memory Chassis
Memory Module

Modes of Operation
Read
Write
Refresh

Input Signals (Storage Card)

+5V
+12V

Power Requirements

logic "1"
logic "0"
Input
Output

Data 4 Bits (ECl B1-D1)
Address 16 Bits AO-A15
Read/Write Control
MOS Timing CE
Refresh
Data Strobe

-5.2V
-5.0V

+2.4 V DC to +5.5 V DC

4 Lines
16 Lines
1 Line
1 Line
1 line
1 Line

Output Signals

0.0 V DC to +0.6 V DC
0.0. V DC to +0.4 V DC

Data 4 Bits

4 Lines

MOSRAM 310 BULK STORAGE CARD TIMING

ADDRS

zoo

100

Read Cycle

I

400

i

~===+====~==~--~--~'~~

-+C.E

-DATA STB-!-----~--_._--_+-_\i

+OATA OUT

lEeli

- / - - - - - - - - f -_ _ _ _-+_---J

Write eye Ie

,

0

I

...... '
AODRS

I
300

10
-+C.E

.- J

13<

1145
\.

DATA IN
(Eel)

-WAT ENB

42

MOS CE

460

-1

,""-

"0

I

\.
"1320

I

I

i

-

'i

lO

i

I
4'lY

-

All National memory systems must meet stringent quality and test standards prior to shipment. Memory components
are burned in, and systems undergo an extensive diagnostic test prior to shipment.

9-7

»
s:
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~

Memory Systems

NA110NAL

MOSRAM 410 memory system
4096 words X 10 bits

GENERAL DESCRIPTION

FEATURES

The MOSRAM 410 is designed to offer the systems
engineer an alternative to the high cost design-prototypetest cycle. This memory system utilizes the MM2102
N-channel, 1k part as the storage medium. These static
storage cells eliminate the need for clocks and refresh.
Data in and data out have the same polarity and the
read operation is nondestructive.

• Single +5.0V supply
• Air inputs and outputs ani DTL/TTL compatible
• Static operation-no clocks or refreshing required

The simple interface and high performance make the
MOSRAM 410 ideally suited for those memory applications, both large and small, where systems cost is an
important consideration.

•

Low power

5Wtyp

•

High speed

550 ns

• TRI-STATE® output forbus interface
• Programmable card select allows simple memory
expansion to 32k x 10
• Small size 3.93 x 6.3 x 0.5 for 4k x 10

The only interface signals required are data in, data out,
address, memory enable, and RIW, all TTL compatible.

•

9·8

Flexibility of speeds and capacities

s:

oen

TECHNICAL SPECIFICATIONS

:::D

Performance

»

Mechanical

Cycle/Access Time:

550 ns

3.93" x 6.3"*
0.5" Centers
60 Pin Card
Edge Type
0.100 Centers
(E LCO 00-6307-060-309-001)

Memory Module
Mounting
Connector

Modes of Operation
Read
Write

s:
~

o

Input Signals
Power Requirements

Data In, 1.0 Bits
Address 15 Bits AO-A14
ReadIWrite Control
External Output Enable
Memory Enable

+5 Voc at 1.0A

Interface
Logic "1"
Logic "0"
Input
Output

+2.4 VDC to +5.5 Voc

Output Signals
Data Out, 10
Bits
/

0.0 V DC to +0.6 VDC
0.0 V DC to +0.4 V DC

10 Lines

Memory Configurations
(Available as Follows:)
4kxl0 . . . . . . . . . . . . . . . . . . . . . . . . .
4k x 9 . . . . . . . . . , . . . . . . . . . . . . . . . .
4k x 8. . . . . . . . . . . . . . . . . . . . . . . . . .
2k x 10 . . . . . . . . . . . . . , ... , . . . . . . .
2k x 9 ...... , . . . . . . . . . . . . . . . . . . .
2k x 8 . . . . . . . . . . . . . . . . . . , . . . . . . .

Environment
o°C to +50°C
-40 o C to +80°C
To 90% Without
Condensation

Operating
Non·Operati ng
Humidity

10 Lines
15 Lines
1 Line
1 Line
1 Line

Model
Model
Model
Model
Model
Model

410
409
408
210
209
208

MOSRAM 410 TIM.ING
Write Cycle

Read Cycle

________ tWCI550MINI _ _ _ _ ,

-tRC (550 MINI - - - - - .

AODAESS· ...'I't_
.....
---:-IOM=I.~)_ _ _ _ _ _ _ _~.....,..:.

ADDRE~ ;;..;t!'r-----------:..JJ'f-"

MEMORY,...,.;cYF...::==::...-------+.....,."..,.

MEMORV

ENABLE

""'.,,-"'-.....;::.AM=IO:.:M:;,;.IN.;:I_ _ _ _ _+~tAWR (75 MINI

ENABLE

ReAoIW'RITE ~

I

1, .

I§

~~H210MINI

tA (550 MAX)

DATAOUT~~~~~~~"
---'

t RC (rnin)
tAM (min)
tA (max)
tOH2 (min)
tOH1 (min)

~tOH' 150 MINI

550 ns
0
550
0
50

~~~~---""----1tS;~--'MWR t75 MIN)

Ri'A'O/WRITE :.:::

~,=tDW(350. MINI~
DATAIN~

twc (min)
tAM (min)
tAwR (min)
tMW (min)
twp (min)
tMwR (min)
tow (min)
toH (min)

550 ns '

0

75
175
300
75
350
125

* Eurocard has 64 pin, on 0.100 centers connector.
A\I National memory systems must meet stringent quality and test standards prior to shipment. Memory components
are burned in, and systems undergo an extensive diagnostic test prior to shipment.

9-9

[#J

~

Memory Systems

NAnONAL

MOSRAM 644 memory system
65536 words X 4 bits

GENERAL DESCRIPTION

FEATURES

The MOSRAM 644 is a high speed random access
semiconductor memory that requires only a timing and
control card to be a complete memory system.

•

Low Cost

•

High Speed

• Separate Timing and Control Card

The memory is contained on a printed circuit card that
measures 10.0" x 11.0". The standard configuration is
64k x 4. Larger capacities are obtained by utilizing
multiple storage cards.
The MOSRAM 644 is a compact planar semiconductor
memory system that was designed to offer the user the
highest performance and lowest bit cost available.
It is designed for a wide range of applications including
large, high speed mainframe, minicomputer, and data
communication systems.

9·10

•

Card Select Input

•

Easily Expandable

•

Chassis

TECHNICAL SPECIFICATIONS
Environment

Performance

Operating
Noli·Operating
Humidity

240 ns
460 ns
460 ns

Access Time
Read Cycle Time
Write Cycle Time

O°C to +50°C
-40°C to +80°C
To 90% Without Condensation

Mechanical (64k x 4)

Modes of Operation

Memory Module
Mounting
Connectors

Read
Write
Refresh

11.0" x 10.0"
0.625" Centers
Two (2) 80 Pin Card Edge Type

, I nput Signals

Data 4 Bits (ECl 81 . Dll
Address 16 Bits AO . A 15
Read/Write Control
MOS Timing CE

-5.2 V

+5 V
+12 V

Power Requirements

-5.0 V

4 Lines
16 Lines
1 Line
1 Line
1 Line
1 Line

Interface
logic "1"
logic "0"
Input
Output

+2,4 VOC to +5.5 VOC
Output Signals,

O.O'Vocto +0.6 VOC
0.0 VOC to +0.4 VOC

Data 4 Bits

4 Lines

MOSRAM 644 - 64 k x 4 TIMING
Road eVe Ie

JOO

200

100

I

-y

AODas

10
+C.E

"

+DATA OUT
(Eel)

230

'\.
240

-'I

+C.E

,-

-

MOS CE

.
-

Y

'F

'\.
ltD

"

02

,""-

t35

3tO

1to.
'\.

31

1,.0

·V
-

'i

49V

lO

I

-

'\.

Lt

.~~~~

0&0

Y

lOO

to

I-1--

3{

I

"

DATA IN

(Eel)
-WRT ENB

I

J ___ 1\

Write eVe Ie 0
ADDRS

500
0&0

lOO

,-

-DATA STB

400

I

300

t,

I

I

~

All National memory systems must meet stringent quality and test standards prior to shipment. Memory components
are burned in, and systems undergo an extensive diagnostic test prior to shipment.

9·11

~

Memory Systems

NA110NAL

MOSRAM 817 memory system
8192 words X 17 bits

GENERAL DESCRIPTION

FEATURES

The MOSRAM 817 is a random access semiconductor
memory that requires only a timing and control card to
be a complete memory system.

•

Low Cost

•

High Speed

The memory is contained on a printed circuit card that
measures 9.0" x 11.0". The standard configuration is
8k x 17. Smaller capacities are available by depopulation,
and larger capacities are obtained by utilizing multiple
storage cards.
The MOSRAM 817 is a compact planar. semiconductor
memory system that was designed to offer the user high
performance and low bit cost.
It is designed for a wide range of applications inCluding
mainframe, minicomputer intelligent terminals, data
communication, data entry, and microprocessor exten·
sion memory. The card is compatible with National's
IMP·16 microprocessor.

9·12

• Output Data Registers

• Separate Timing and Control Card

• Card Select Input

•

Expandability to Eight Cards (64k)

TECHNICAL SPECIFICATIONS
Mechanical (8k x 17)

Perfo rmance
500 ns
505 ns
690 ns
780 ns.+ Modify Time

Access Time
Read Cycle Time
Write Cycle Time
Read/Modify /Write

9.0" x 11.0"
0.625" Centers
1 Each 144 Pin

Memory Module
Mounting
Connector

Modes of Operation
Read
Write
Split Cycle (Read/Modify/Write)

Input Signals

Power Requirements
+5 Voc at 1.5 A, -15 VOC at 0.5 A,+15 Voc at 0:1 A
Interface
Logic "1"
Logic "0"
Input
Output

+2.4 VOC to +5.5 VDc
0.0 VOC to +0.6 VOC
0.0 VOC to +0.4 Voc

Data 17 Bits
Address 13 BitsAO - A12
Read/Write Control
MOS Timing T1 T2 T3
Refresh
Data Out· Enable
Data Strobe
Card Select

17 Lines
13 Lines
1 Line
3 Lines
1 Line
Line
Line
Line

Output Signals
Data 17 Bits

17 Lines

Environment
O°Cto +60°C
_40° C to +80° C
To 90% Without Condensation

Operating
Non-Operating
Humidity

MOSRAM 817 8k

X

17 TIMING
Read Cycle

lOOns

0"

I

I

j

AOUR An - AID

-.

Write Cycle

200ns

300ftl;

400ns

SOllns

I

I

I

I

600 '"

70n ns

o ns

Ion ns

20D III

300 ns

I

I

I

I

I

I

,~DDR Au -"~12

-~~~::r,

I

:t:

400

I

ns

500 liS

600 II'i

100 ns

I

I

I

ZO~AX

CARD SELECT

B,OMIN
READ/WRITE
9SMIN

CLOCK Tl
ClOCK"T2"
CLOCK Tl
DATA STROBE

DATA ENABLE
DATA IN

DATAOUT

"1"
"0"

I

+ ________

:

TO
ADDRESS
STROBE

A.•.;.;5.;.OM:;;;A.;;;X'"t·_ _ _--t-'l'~

I
--- FULL READ CYCLE 690 ns----..J

SHORT READ CYCLE 505 ns - - -

-

. .~t=~

"'''~
"o""F4
I

I

, '

i - - - - - - F U l l WRITE CYCLE

TO
ADDRESS
STROBE

9-13

690ns-----,-~

o

I

o

o
o
....

~

Memory Systems

NAnONAL

8SM 1000 memory system
512k to 1 megaword

GENERAL DESCRIPTION

FEATURES

The National Memory Systems BSM 1000 add-on
memory is a low cost, high performance bulk storage
memory. The memory is designed for storage capability
from 512k to a total of 1 megaword. The system is selfcontained with power supply, cooling and other options
in an attractive 31"'x 18" x 60" enclosure.

•

Field· Proven

•

Low Cost

•

High Speed

•

Low Power Consumption

The BSM 1000 uses high speed 4k RAMs which are
utilized on the MOSRAM 644 storage card. The
MOSRAM 644 (65,536 x 4) card is the basic building
block for the system. In addition, timing/control and
custom interface cards are supplied. The system design
is readily adaptable to meet many custom applications.
Applications include add-on memory to the IBM 370/158
Bulk Storage Module and other high speed systems.

• Compact Size
• Chassis, Rack, Power Supplies

9-14

TECHNICAL SPECIFICATIONS.
~

o

Performance

oo

270 ns
460 ns
460 ns

Access Time
Read Cycle Time
Write Cycle Time
Power Requirements
60 Hz
50Hz

208-240 VAC
380-415 VAC

30A
30A

60 Hz
60 Hz
60 Hz

Plug
Connector
Receptacle

30A
30A
30A

3-Phase Delta
3-Phase Wye
R&S
R&S
R&S

#FS3760
#FS3934
#FS3754

Environment
Operational:
Temperature
Relative Humidity
Maximum Wet Bulb
Non-Operational
Temperature
Relative Humidity
Maximum Wet Bulb

+10°C to +40~C
20% to 90%
+26°C
-46°C to +43°C
20% to 90%
+27°C

Mechanical
Specific Physical Planning Data for the National Memory
System BSM 1000 is listed below:
31" W (78.7 cm)
Dimensions:
18" 0 (45.7 em)
60" H (152.4 cm)
Weight
KVA Rating
KW Rating
Heat Output
Airflow

700 Ibs (317.5 kg)
2.9 KVA
2.4 KW
7.215 BTU/hr
690 ct/min (19.54 em/min)
BSM ,000

SPECIAL FEATURES

OPTIONS

•

• Custom Interfaces

Easy.Maintenance

• Control Panels

• Error Correction & Control

• Power Supply Monitors

• Configurations

(~ar

yiew)

• ·Configuration Flexibility

•

•

• i;xpandable Word Capacity (4k Increments) from
256k to 1l\11egaword.

Easy Expandability

Flexible Word Length (8 to 20 Bits)

All National memory systems must meet stringent quality and test standards prior· to shipment. Memory components
are burned in. and systems undergo an extensive diagnostic test prior to shipment.

' . I'

9-15

i

....
I

o

8

,('I)

en
z

~

Memory Systems
Advance Information

NAlIONAL

NS3000,1 memory system
16k words X 20 bits
GENERAL DESCRtPTION
The NS3000-1 is a random access semiconductor
memory conta.ined on a single printe!;! .circuit card.
Standard configurations are 16k x 16, 18 and 20 bits
with individual 8, 9 or '10-bit byte structure as an
option.

Performance
Access Time
Read or Write Cycle
Read/Modify /Write Cycle
"'Plus user data modify time

Design flexibility perm'its customized applications.
Options incilJde parity generation, parity check, .Iate
data input and data available reSet.

Environment
Operating: O°C to +50°C
Non-operating: -40°C to +80°C
Humidity: 90% without condensation

The NS3000·1 .is designed for .a wide range of applicathins i'ncludin!l mainframe computers, mini-computers,
microprocessor·basetl systems, intelligem terminals and
"
'
data entry.

Mechanical
Card Size: 11.75" x 15.40"
Connectors: 2 each 80 pin edge connectors with pins
space "125" center to center

FEATURES
• low cost
• High speed
•. Proven reliability'
•
•
•
•
•

280ns
430ns
*610 ns

Input Signals
•
•
•
•
•
•
•
•
•

low power
Special options
Designed to incorporate special customer requirements
Bi-directional data transmission if required
TTL compatible

Standard Features
• Byte mode
• late Data In-enables late presentation of data for
write operation

Initiate Pulse (RP)
Byte Control levels (BlCl, BlC2)
Split Cycle (SC)
Write Pulse (WP)
Configuration Option (4 lines)
Address In (AI)
Extended Address IN (XAI)
Data In (01)
Memory Protect (MP)

Logic levels
All levels are negative true TTL compatible.
Terminations are optional.

Special Options

Memory Organization

The following is available on a customized. basis:
• Parity check
• Parity generation
• Data Available Reset-permits Data Available (DA)
to be gated within the memory cycle. It can be used
to release the data bus in a shared system.

•
•
•
•

Memory storage
Timing and control
Refresh circuitry
Optional features

Note: The memory size may be reduced by board depopulation.

TECHNICAL SPECI FICATIONS

Output Signals
Modes of Operation

• Data Out (DO)
• Data Available (DA)
• Memory Busy (MB)

Write Read
Read/Modify /Write

9-16

Z

fn
W

TECHNICAL SPECIFICATIONS (CON'T)

o
o
o,

Power Requirements

Memory Refresh

Standard +15V, -15V, +5V
Option' +12V, -5V, +5V

This can be implemented to individual customer applications either in a synchronous mode or in an asynchronous
mode allowing hand shaking with the CPU_

* Lower cost

Typical Memory Card Interface

r
+5V

llO
±5%

,I
OPTIONAL
CORRECTIONS

I

+5V

:i~-= 11'--+-t-+---t--it-----3~I..
r-

TWISTED PAIR

~I

9-17

Uk

....

N

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~

Memory Systems
Advance Information

NA110NAL

NS3000c2 memory system
32k words X 18 bits
GENERAL DESCRIPTION
Input Signals

The NS3000-2 is a random access semiconductor memory
contained on a single printed circuit card. Standard
configuration is 32k x 16 or 18 bits which is alterable
to 64k x 8, 9 using byte control.

• Initiate Pulse (RP)
• Byte Control levels (BlC1, BlC2).
• Address In (AI)
• Data In (01)
• Ge'neral Reset

Design flexibility permits customized applications.
Special features include late data input and data available reset.

Output Signals

The NS3000-2 is designed for a wide range of high
density memory applications including mainframe
computers,
mini-computers,
microprocessor-based
systems, intelligent terminals and data entry.

• Data Out (DO)
• Data Available (DA)
• Memory Busy (MB)

FEATURES
Logic Levels.

• lowcost
• High speed
• Proven reliability
• Low power
• Special options
• Designed to incorporate special customer requirements
• Bi-directional data transmission if required
• TTL compatible

All levels are negative true TTL compatible.
Terminations are optional.
Memory Organization
• Memory storage
• Timing and control
• Refresh circuitry
• Special features

Standard Features

Note: The memory size may be reduced by board depopulation.

•
•

Mechanical

Byte mode
Late Data In-enables late presentation of data for
write operation
• Data Available Reset-permits Data Available (DA)
to be gated within the memory cycle. It can be used
to release the data bus in a shared system.

Card size: 11.75" x 15.40"
Connectors: 2 each 80 pin edge connectors with pin
spaced "125" center to center
Power Requirements

TECHN ICAl SPECI FICATIONS

Standard: +15V, ~15V, +5V
Option:+12V,-5V,+5V*

Modes of Operation

* Lower cost

Write
Read

Common Data Bus

Environment

Gating is provided on the Data Input and Data Output
circuits to allow bi-directional data transmission if
desired.

Operating: O°C to +50°C
Non-operating: ~40°C to +85°C
Humidity: 90% without condensation

Memory Refresh
Performance
Access Time
Read or Write Cycle

This can be implemented to individual customer applications either in a synchronous mode or in an asynchronous mode allowing hand shaking with the CPU.

275 ns
430 ns

9-18

~

Interface

N

......
C

en

2

DS0025/DS0025C two phase MOS clock driver

U'I

n

general description

features

The DS0025/DS0025C is monolithic, low cost,
two phase MOS clock driver that is designed to be
driven by TTL/DTL line drivers or buffers such as
the DM932, DS8830 or DM7440. Two input
coupling capacitors are .used to perform the level
shift from TTL/DTL to MOS 109ic levels. Optimum
performance in turn·off delay and fall time are
obtained when the output pulse is logically can·
trolled by the input. However, output pulse widths
may be set by selection of the input capacitors
eliminating the need for tight input pulse control.

• 8·lead TO·5 or 8·lead dual·in·line package
• High Output Voltage Swings-up to 30V
• High Output Current Drive :Capability-up to
1.5A
ill Rep. Rate: 1.0 MHz into >·1000 pF

• Driven by DM932,DS8830, DM7440 (SN7440)
• "Zero" Quiescent Power

connection diagrams
Meta' Can Package

Duo'·' n-Line Package
• NC

NC 1

INPUT A 2

-+---1:>0---+- 7

v- 3
v-

INPUT B 4

Note: Pin. connected ta Clse.
TOP VIEW

-+---1 ;~--+-~ 5
Order Number DSOO25CN
See P~kage 12

tYpical application
';,

timing di.agram

CIDCkpulit
output

5'

IN

.

~ ...
18%

~

ac test circuit

-----.-,.-ov

' - -_ _ _ _ _ _ 0'

t..ON.

rt..OFF

V3 "'OV

111%,10%

sa%
Input wavefonn:
PRR =O.5MHz
Vp·p= 5.0V
t,=tt:S"10ns
Pulse width:

.

.
.
~

~

50%

Your

1"-""-..;;;;;'"'1-+----- V~:-I&V
"01 is Sf!lected high speed NPN swiu:hing transistor.

A. Ups
B.2oons

10·'

OUTPUT A

6 V·

TOP VIEW

Order Number DSOO25H or DSOO25CH
See Package 23

B,lnputpulsewidtll
set51l1a~1c pulse
width

o

U'I

NA110NAL

~~-~
>clockpul5l!

c

en
o

OUTPUT B

co

Ln

8en
Q

co
N
o

o

en

Q

~

Interface

NA110NAL

050026. 050056 5 MHz two phase MOS clock drivers
general description
OS0026/0Soo56 are low cost monolithic high speed
two phase MOS clock drivers and interface circuits.
Unique circuit design prOvides both lIery high speed
operation and the ability to drive large capacitive loads.
The device accepts standard TTL/OTL outputs and
converts them to MOS logic levels. They may be driven
from Standard 54n4 series and 54Sn4S series gates
and flip-flops or from drivers such· as the OS8830 or
OM7440. The OS0026 and OS0056 are intended for
applications in which the output pulse width is logically
controlled; i.e., the output pulse width is equal to the
input pulse width.

in pull ing up the output when it is in the high state. An
external resistor tied between these extra pins and a
supply higher than v+ will cause the output to pull up
to (V+ - 0.1 V) in the off state.
.
For OS0056 applications, it is required that an external
resistor be used to prevent damage to the device when
the driver switches low. A typical VBB connection is
shown on the next page.
These devices are available in 8-lead TO-5, one watt
copper lead frame 8-pin mini-DIP, and one and a half
watt ceramic OIP, and TO-8 packages.

The OS0026/0S0056 are designed to fulfill a wide
variety of MOS interface requirements. As a MOS clock
driver for long silicon-gate shift registers, a single device
can drive over 10k bits at 5 MHz. Six devices provide
input address imd precharge drive for a Bk by 16-bit
1103 RAM memory system. Information on the correct
\!sage of the OS0026 in these as well as other systems is
included in the application note AN·76A.

features
• Fast rise and fall times'-20 ns with 1000 pF load
• High output swing-20V
• High output current drive-±1.5 amps
• TTLIOTL compatible inputs
• High rep rate-5 to 10 MHz depending on power
dissipation
• Low power consumption in MOS "0" state-2 mW
• Orives to O.4V of GNO for RAM address drive

The OS0026 and OS0056 are .identical except each
drivei in the OS0056 is provided with a VBB connection
to supply a higher voltage to the output stage. This aids

connection d iag rams
TO-5Pack_

(Top Views)

Dual-ln·Line Package
Nt

OUT A

y+

OUT B

Nt

INA

Y-

IN8

TO-8 Package

Dual-ln·Line Pack_
OUT I

Ne

Ne

IN8

Ne

Ne

I••
Note: Pift4connectedtoase.

Order Number DS0026H
or DSOO26CH

Order Number DSOO26CN

See Package 12

See Package 23
TOoS Package

See Package 25
Dual-In-Line Package
OUTA

or

Nt
DUT A
Ne
.IA
Ne
vOrder Number DSOO26J, OSOO26CJ
orOSOO26W
See Packago 9 or 27

Nt

Order Number DS0026G
or DSOO26CG

TO-8 Package

VallB· OUTS

Dual-ln·Line Pack_
y+

VallB

OUT 8

Ne

IN •

Nt

Ne

Nt

V. A

DUTA

Nt

INA

Ne

y-

INA

y+

yI••

Note: Pin 4 connecbd to CIIL

Order Number DS0056H
or DSOO56CH

SeeP8ck_23

V88A

IN A

V-

'NB

Order Number DSOO56CN

-

See Packalll> 12

Order Number DS0056G
or DSOO56CG

Order Number DS0056J
or DS0056CJ

See Package 25

SeePack_9

10-2

~

Interface

NA110NAL '

051603/0S3603. 053604. 0555107/0575107.
0555108/0575108. OS75207. OS75208 dual line receivers
general description

features

The nine products described herein are TTL
compatible dual high speed circuits intended for
sensing in a broad range of system applications.
While the primary usage will be for line receivers
or M05 sensing, any of the products may effectively be used as voltage comparators, level translators, window detectors, transducer preamplifiers,
and in other sensing applications. As digital line
receivers the products are applicable with the
0555109/0575109 and 0555110/0575110 companion drivers, or may be used in other bahinced
or unbalanced party-line data transmisSion systems.
,The improved input sensitivity and delay specifications of the 0575207, 0575208 and 053604
make them ideal for sensing high performance
M05 memories as well as high sensitivity line
receivers and voltage comparators: TRI-5TATE®
products enhance bused organizations.

• Oiode protected input stage for power "OFF"
condition
•

17 ns typ high speed

• TTL compatible
• ±10 mV or ±25 mVinput sensitiVity
• ±3V input common-mode range
• High input impedance with normal Vee, or
Vee ~ OV

•
•
•
•
•

5trobes for channel selection
TRI-STATE outputs f~rhigh speed buses
Oual circuits
5ensitivity gntd. over full common·mode range
Logic input clamp diodes-meets both "A" and
"B" version specifications
• ±5V standard supply voltages

connection diagrams
Dual·ln·Line Pack8ClO

Dual·ln·Line Pac"Vee-

INPUT
IA

IIPOT
11

,om
2A

tIC

INPUT

"

OUTPUT
IV

.,

OUTPUT

STROlE
11

STROH
S

zv

STROI(
Vec-

"

_UT
IA

GilD

INPUT
I.

INPUT
lA

tIC

II'UT
2'1

IIC

OUTPUT
IV

STROlE
II

.U1?UT

STROft

ZV

"

otSAIU
0

GND

TOPVI£W

TOfIVIEW

Ordar Number DS55107J, DS75107J,
DS5510BJ,DS75108J,DS75207J
or DS75208J
Sea Pac"- 9,
Ordar Number DS75107N; DS751oaN,
oS75207N or DS75208N
'Sea Pac"- 14
Ordar Number DS55107W or, DS5!il0BW
Sea Package 27

'Ordar Number DS1603J, DS3603J
DS3604J or DS1603W
Sea Package 9 or 27
Ordar Number: DS3603N or DS3604N
Sea Pai:kage 14

I

product sel,ection guide
TEMPERATURE~
PACK,AGE~'

INPUT SENSITIVITV~

--55°C::;TA S+125°C

ooC :S TA $, +10°C

CAVITV OIP

CAVITV OR MOLOEO DIP

.:!:25mV

±25mV

±10mV

0575107
0575108
053603

0575207
0575208
053604

OUTPUT LOGICI
TTL Active Pull-up
TTL OPen Collector
TTL TRI'STATE

0555107
0555108
051603

10-3

1m

~ ..

Interface

NAlIONAL

051605/053605, 051606/053606, 051607/053607,
051608/053608 hex M05 sense amplifiers (M05 to TTL converters)
general description
The 053605 series is a new series of programmable
hexMOS sense amplifiers featuring high speed direct
MOS sense capability with high impedance states to
allow use of a common bus line. The OS1605/0S3605
and the .oS1606/0S3606 have TRI·STATE® outputs.
The OS1607/0S3607 and 0$1608/0S3608 have both
TR I·STATE inputs and outputs. High impedance states
are controlled by an enable input.

Outputs are high current drivers capable of sinking
50 mA in the low state and sourcing 5 mA in the high
state.

features
•

Non·inverting inputs
053607)

Input current threshold (the level at which the output
changes state). is determined .by the current at the
programming pin. The current threshold is 10CiJlA with
the programming pin grounded and 250JlA with the pin
unconnected. The threshold can be set·from 100JlA to
300pA by connecting a resistor from the pin to ground,
and set above 300JlA by connecting a resistor from the
pin to the positive supply.

•
•
•
•
•
•
•
•

Inverting inputs. (OS1606/0S3606, OS1608/0S3608)
No. external components required (direct MOS sensing)
Programmable inpu·t thresholds
Current sensing-100pA minimum
50 mA drive capability
TRI·STATE control
Single 5Vsupply
15 ns typical propagation delay (OS3605)

connection diagram

typical· application

Vee

DISABLE

Dua~-In-Line

Package

1N6

INs

OUTij

OUTs

(OS1605/053605,

OS1607/

. PACE Interface
IN4

OUT 4

lOMBS31
BUFFERS

'OM
ADDRESS
LATCH

lDSJ608

-{>HEX SENSE
AMPS

TOP VIEW

JDM8091

ordering information
ORDER NUMBERS

DATA AND ADDRESS'
OUTPUT

pACE

-o-....·C::><>----'

~I~!~~~

o-------i ><>----~-----.........

1
IN
ENBt

1
DATA A

,

1

UA

5

OATA B

i4

6
DATA C

)

Oc

I'

GNO

TOPVlfW

Order Number DS1645J, DS1675J,
DS3645J, DS3675J, DS3645N
or DS3675N
See Package 10 or 15

truth table
INPUT
ENABLE

OUTPUT
DISABLE

DATA

OUTPUT

1
1
0

0
0
0

1
0
X

0
1
Q

Data Feed·Through
Latched to Data Present
when Enable Went Low

X

1

X

Hi-z

High Impedance Output

OPERATION
Data Feed·Through

x = Don't care.
·Specifications may change.

10-11

~

Interface
Advance Information*

NAll0NAL

OS1646/0S3646, OS1676/0S3676 6-bit TRI-STATE ®
MOS refresh counter/driver
e.g

'lit

general description

C")

The OS1646/0S3646 and OS1676/0S3676 are 6-bit
refresh counters with outputs designed to drive large
capacitive loads up to 500 pF associated with MOS
memory systems. PNP input transistors are employed
to reduce input currents. The circuit has Schottkyclamped transistor logic for minimum propagation delay,
and TRI-STATE® outputs allow it to be used on
common data buses.

e.g

en

c
.....
e.g
'lit

....

e.g

en

c

The OS1646/0S3646 has a 15 ohm resistor in series
with the outputs to dampen transients caused by the
fast switching output circuit. The OS1676/0S3676 has
a direct, low impedance output, for use with or without
an external resistor.
The counter uses as its input the RAM clock signal, and

with each clock input, it advances the count by one,
thus .generating a new refresh address.
Extra pins in the package are used for a two input
NANO gate and a two input NOR gate, both of Which
have capacitive drive outputs.

features
•
•
•
•
•
•
•

Circuit counts when clock goes high
TTL/OTL compatible inputs
PNP inputs minimize loading
Capacitance-driver outputs
TRI-STATE outputs
Extra gates on unused pins
Built-in damping resistor (OS1646/0S3646)

logic diagram
OUT 1

OUT J

DUTZ

our 4

OUT 5

OUT6

ClK

OUTPUT
ENABLE

connection diagram

The OS1646/0S3646 and OS1676/0S3676 have TRISTATE outputs .which can be tied to the outputs of
another TR I-STATE driver. The refresh counter can
control the address lines into a memory array during
a short refresh cycle, and then return to the highimpedance state to allow the primary driver to control
the address lines.

Dual-In-Line Package

116

ENBl
15

OUT I;

"

OUT 5

OUT 4

13

11

0

typical application

OUT
Vee

ABC

11

,

"

0-

AODREssl
INPUTS

H-t-+.....- H-++--t--,>--

j~~~ORV
ARRAV

H-t-+-1t-+-.1

,

elK

OUT1

J
OUll

4

5

6

Dun

)

A:s

REFRESH
CONTROl

I'

OUTPUT
DISABLE

GND

TOPVIEW

OSJ646/

Order Number DS1646J, DS1676J. DS3646J,
DS3676J, DS3646N, or DS3676N

OUTPUT

ENABLE

See Package 10 or 15

CLOCK

D53676

~~~:~~~ 1----'
·specifications may change.

1012

c

Interface
Advance Information*

...

en

m

~c

en

to)

OS164710S3647, OS1677/0S3677, OS16147/0S36147, OS1617710S36177
quad TRI~STATE® MOS memory I/O registers

m

~

c

general description

...

en

DS1647/0S3647 and OS1677/DS3677 they are TRISTATE. The· "B" port outputs are also designed for use
in bus organized data transmission systems and can sink
80 mA and source -5.2 mAo The "A" port outputs in
all four types are TRI-STATE.

The OS1647/0S3647 series are 4-bit I/O buffer registers
intended for use in MOS memory systems. The circuits
employ a fall-through latch for data storage. This method
of latching captures the data in parallel with the output,
thus. eliminating the delays encountered in other designs.
The circuits use Schottky-clamped transistor logic for
minimum propagation delay and employ PNP input
transistorsC>-W'Y----Q OUTPUT

IN

RD

v"SEE GRAPH FOR VALUE

DS3671 Operating with Extra Supply
to Inhance Output Voltaga Level

Bootstrap Clock Driver Driven from' a TTL Gate
·Specifications may change.

10-17

Interface

~

Advance Information*

NAll0NAL

0516149/0536149, 0516179/0536179 hex M05 drivers
general description
The OS16149/0S36149 and OS16179/0S36179 are
Hex MOS drivers with outputs designed to drive
large capacitive loads up to 500 pF associated with MOS
memory systems. PNP input transistors are employed to
reduce input currents allowing the large fan·out to these
drivers needed in memory systems. The circuit has
Schott'ky-clamped transistor logic for minimum propaga·
tion delay, and a disable control that places the outputs in
the logical 'T' state (see truth table). This is especially
useful in MOS RAM applications where a set of address
lines has to be in the logical "1" state during refresh.

fast-switching output. The OS161791OS36179 has a
direct low impedance output for use with or without
an external resistor.

features

The DS16149/0S36149 has a 15 ohm resistor in series
with the outputs to dampen transients caused by the

schematic diagram

•

High speed capabilities
• Typ 7 ns driving 50 pF
• Typ 25 ns driving 500 pF

•

Built-in 15 ohm damping resistor (OSI6149IOS36149)

• Same pin-out as OS8096 and OS74366

EQUIVALENT INPUT

r----:......==-'--:=-=--:==::-~...",,.--1--_1,.....--Ov"

15 (DS16149/0836149 ONl VI
L - -.....~wo.-oOUTPUT
INPUT

L ___ _
L-~-

_ _ _ _ _ _~_:"""-----~--~--~G'D

connection diagram

typical application

Dual·1 n-l ine Package
0SJ6149
OR

DSJ6119

.0'

681TRAM

ADDRESS

DRIVER

r----'

1====:::1
\------1
1-_ _ _ _-,

I
I

ADDRESS
LINES

I
I
MM5210
0'
I
MM52ID
I
'Sl'"
OR
DSl679
I
1=1:t:;:==::j REfRESH
I
MO'
ORIVfR HI-t+,.-.--, ~~N~~ESS
I
I
DISABLE
L _ _ _ _ .J
MOSRAM

ARRAY

&

SilT RAM
ADDRESS

OUll

DUH

GND

IN3

TOP VIEW

Order Number DS16149J, DS16179J, DS36149J,
DS36179J, DS36149N or DS36179N
See Package 10 or 15

...

""

DR
053616

truth table

MO.
CLOCK

DISABLE INPUT
0lS1

DIS 2

OUTPUT

0

0

0

1

0

0

1

0

0

1

1

1

0
1

X
X
X

1

1

COUNTER

DRIVER

INPUT

ADDRESSOR
COUNT SELECT
'''''ADDRESS
"I~CDUNTER

1

"Specifications may change.

- Don tcare

10-18

c

~

Interface

Advance Information*

c

en
.....

...o
U'1

general description

•

Tightly controlled output currents over temperature, Vee, and common-mode variations

schematic diagram

CD

•

High speed

15 ns max

•

Wide output common-mode range

•

High output impedance

•

Inhibits for party-line applications

•

Current sink outputs

•

Dual circuits

•

Standard supply voltages

•

Input clamp diodes

•

14 pin cavity or molded DIP

INPUT
AT

INPUT
B1

INI'IIHIT
CI

INHIBfT
C2

U'1
U'1

o

........

c

6 or 12 mA

~
U'1

±5V

o

Package
INPUT

OUTPUT

OUTPUT

o

l~

n

INPUT
Al

c

en

......

connection diagram
Dual~ln·Line

'fIIPUT
a2

Order Number D855109J, 0855110J,
0875109J Dr 087511 OJ
See Package 9

Order Number OS75109N Dr 0875110N
See Package, 14

typical application
Party-Line Data Transmission System

MISTED·PAIR
T~UWISSIO~

liN,

II

II
II

I

II

I \

Notel: 1/2 of the dual·circuit shown.

...

o

........

OS55109/0S75109, OS55110/0S75110 dual line drivers

features

U'1
U'1

CD

NAll0NAL

These products are TTL compatible high speed
differential line drivers intended for use in terminated twisted-pair party-line data transmission
systems. They may also be used for level shifting
since output common·mode range is -3V to +1 OV.
An internal current sink is switched to either
output dependent on input logic conditions. The
current sink may be turned off by appropriate
inhibit input conditions_

en

Zo'2-=

II

Note 2: "Indicates connections common to second half of circuit.

*Specifications may change

......

....
....

N

....

It)

(J)

C
.......

....N
....

It)
It)

~

Interface

NAll0NAL

OS55121/0S75121 dual line drivers

(J)

C

general description

features

The OS55121/0S75121 are monolithic dual line
drivers designed to drive long lengths of coax ial
cable, strip line, or twisted pair transmission lines
having impedances from 50 to 500 ohms. Both
are compatible with standard TTL logic and
supply voltage levels.

•

Designed for digital data transm ISS Ion over 50
to 500 ohms coaxial cable, strip line, or
twisted pairtrarismission lines

•

TTL compatible

• Open emitter-follower output structure for
party-line operation

The DS55121/DS75121 will drive terminated low
impedance lines due to the low-impedance emitterfollower .outputs. In addition the outputs are
uncommitted allowing two or more drivers to
drive the same line.

• Short-circuit protection

Output short-circuit protection is incorporated
to turn off the output when the output vciltage
drops below approximately 1.5V.

•

AN~-OR

•

High speed (max propagation delay time 20 ns)

•

Plug-in replacement for the SN55121/SN75121
and the 8T13
.

connection diagram

logic configuration

typical performance
cha racteristics

Dual-In-line Package
O",tput Current vs Output Voltage
16

D2

E2

F2
15

C2

82

A2

V2

-300
Vee'" 5.0V
V1H == 2'.OV

14

=i -250 [--.
oS

+-! i T(5C
'···f-

~

~ -200
~

~"

-150

t.:I

~

~

-100

,

I

\

I

c

..2 -50

I

..

ro

1

II
\1

0.5 LO 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.1l
Vo - OUTPUT VOL TAG E IV)

A1

B1

D1

F1

E1

V1

OND

truth table

TOP VIEW

Order Number DS55121J, DS75121J, DS75121N
or DS55121W
See Package· 10, 15 or 28

OUTPUT

INPUTS

Y

A

B

C

D

E

F

H

H

H

H

X

X

H

X

X

X

X

H

H

H
L

All Other Input Combinations

H = high level, L

= low level,

X ""- Irrelevant

ac test circuit and switching time waveforms
_I ~ ~5.0ns
-1 1-J.Dv~t·
9D%
90%' i

_50",

INPUT

)'--11--1""""--1,,"""0 OUTPUT

.

r

10% '
{IV

'.5V

1.5V

'
tpLH - -

C,
(NOTE B)

OUTPUT

v
O

"

Vo,
Note 1: The l1ulsf !lenerators have the folluwing characteristics: .
ZOUT "" SOu, tw eo 200 liS, duty cycle eo 50%, t, = t, '" 5.0 ns
Note 2: CL iocludes probe illld jig capaci1allce.

10-20

.---

I

, ' tO%
:

,
'-,

1.5v/

tPHL

'

I.._----.J

~

~

Interface

c(J)
(11
(11

.....

N
N

........

NATIONAL

C

(J)

.....
(11
.....

0555122/0575122 triple line receivers
general description

features

The 055512210575122 are triple line receivers
designed for digital data transmission with line
impedances from 50Q to 500Q. Each receiver has
one input with built-in hysteresis which provides a
large noise margin. The other inputs on each
receiver are in a standard TTL configuration. The
0555122/0575122 are compatible with standard
TTL logic and supply voltage levels.

•
•

N
N

Built-in input threshold hysteresis
High speed ... typical propagation delay .time
20 ns
Independent channel strobes
Input gating increases application flexibility
5ingle 5.0V supply operation
Fanout to 10 series 54/74 standard loads
Plug-in replacement for the 5N55122/5N75122
and the 8T14

•
•
•
•
•

connection diagram

truth table

Dual-I n-Line Package

A

Y
L

OUTPUT

H

X

x

x

X
X
X

L

H

L

H

X

H

X

L

H

L

·H

X

H

L

X

L

H

L

X
X
=0

S

H
L

H

INPUTS
st R

high level, l "" low level, X '" irrelevant

tB input and last two lines of the tnJth table
are applicable to re'ceivers 1 and 2 only.

A1

B1

R2

S2

A2

B2

Y2

GNO

TOP VIEW

Order Number DS55122J, DS75122J, DS75122N
or DS55122W
See Package 10, 15 or 28

ac test circuit and switching time waveforms
2.6V

84.5

:; 5.0 ns-

2.6V

lN3064

INPUT

I

OUTPUT
5.Dk

Voc

-=
Note 1: The pUlSE !lenerator has the folluwin9 dlaraGteristics:
ZOUT "" 5B~!. tw ~ 200 ItS, duty I:Ytle '" ~O%, t, = t, '" 5:0 ns.
Note Z: CL includes probe and jig capacitance.

1021

mJ

~

Interface

NAll0NAL

0575123 dual line driver
general description

features

The OS75123 is a monolithic dual line driver
designed specifically to meet the 1/0 interface
specifications for IBM System 360. It is com:
patible with standard TTL logic and supply voltage
levels.

• Meet IBM System 360 1/0 interface specifica·
tions for digital data transmission over 50.11 to
500.11 coaxial cable, strip line, or terminated
pair transmission lines
• TTL compatible with

The low-impedance emitter-follower outputs of
the OS75123 enable driving terminated low impedance lines. In addition the outputs are uncommited allowing two or more drivers to drive
the same Ii ne.

• 3.11V output at

• Short circuit protection
•

AN~-OR

Dual-In-Line
15

16

02

E2

typic.al performance
characteristics

Pack~ge

C2

B2

logic configuration

• Plug·in replacement for the SN75123 and the
8T23

connection diagram
F2

5.0V supply

-59.3 mA

• Open emitter-follower output structure for
party-line operation

Output short·circuit protection is incorporated
to turn off the output when the output voltage
drops below approximately 1.5V.

vee

sin~le

10H =

.2

Y2

Output CUrrent vs Output Voltage
-300

14

J" l5.~V

--+-....--+-0 OUTPUT
C,
(NOTE 2)

OUTPUT

vo,
Note 1: THE PULSE GENERATORS HAVE THE FOllOWING CHARACTERISTICS:
tw = 200 ns, DUTY CYCLE = 50%.
.
Note 2:

ZOUT ,.,

50U,

CL INCLUDES P~OBE AND JIG CAPACITANCE.

10-22

~

irrelevant

Interface

0875124 triple line receivers
general description

features

The OS7!j124 is designed to meet the input!
output interface specifications for IBM System
360. It has built-in hysteresis on one input .on
each of the three receivers to provide large noise
margin. The other inputs on each receiver are in
a standard TTL configuration. The OS75124 is
compatible with standard TTL logic and supply
voltage levels.

•
•
•
•
•
•

Built-in input threshold hysteresis
High speed .. typ propagation delay time 20 ns
Independent channel strobes
Input gating increases application flexibility
Single 5.0V supply operation
Plug-in replacement for the SN75124 and the
BT24

connection diagram and truth table
Dual·ln-Line Package

A

S

Y

X

X

L

L
H

H

L
H
H
H
H

L
L

H
X
X
X

X
X

L
L

H

X

OUTPUT

INPUTS
Bf
R

X

X

L

H

X

X

L

H:: high level,l '" low level, X == irrelevant
tu input and last two lines of the truth table

AI

B2

are applicable to receivers 1 and 2 only.

V2

TOP VIEW

Order Number DS7512ljJ
See Package 10

Order Number DS75124N
Se. Package 15

typical application
A

B
C

o

95 COAXIAL CABLE

10-23

o

...

It)

~
c

~

Interface

NAlIONAL

D575150 dual line driver
general description

features

The OS75150 is a dual monolithic line driver designed
to satisfy the requirements of the standard interface
between data terminal equipment and data communication equipment as defined by EIA Standard RS-2.32-C.
A rate of 20,000 bits per second can be transmitted with
a full 2500 pF load. Other applications are in datatransmission systems using relatively short single lines,
in level translators, and for driving MaS devices. The
logic input is compatible with most TTL and DTL
families. Operation is from -12V and +12V power
supplies.

• Withstands sustained output short-circuit to any
low impedance voltage between -25V and +25V
• 2Jls max transition time through the -3V to +3V
transition region under full 2500 pF load
• Inputs compatible with most TIL and DTL families
• Common strobe input
• Inverting output
• Slew rate can be controlled with an external capacitor
at the output
• Standard supply voltages
±12V

schematic and connection diagrams
Dual·ln-Line Pack;;.ge
2Y

+Vcc

1Y

STROBE
S

INPUT
lA

-Vee

.....

+Vcc c>-<~-..-----

-~~-~~-----,

TO OTHEA
UNE DRIVER

INPUT A
STROBE

s O-HI++~-I*,H

TO OTHER
LINE DRIVER

INPUT
ZA
TOP VIEW

GND

Positive lOglCY ~AS

Order Number DS75150N

See Package 12

l---+-....-""tv-~-+--H>--+...-+<> OUTPUT

_+__-'

CND 0-.....
TO OTHER

Dual-I n-L ine Package

UNE DRIVER

NC

tVee

OUTPUT
tV

OUTPUT
ZY

-Vee

NC

NC

NC

STROBE

INPUT

INPUT

GND

NC

NC

S

lA

2A

TO OTHER

LINE DRIVER
Vee o-~-----------4----4--~--'

Component values shown are nominal

1/2 Df"ir~ujt$lJoW"

TOP VIEW
Positi~e LDgicY

AS

Order Number DS75150J

See Package 9

10-24

~

Interface

OS75154 quadruple line receiver
general description
The DS75154 is a quad monol ithic line receiver
designed to satisfy the requirements of the standard
interface between data terminal equipment and data
communication equipment as defined by EI A Standard
RS-232C_ Other applications are in relatively short,
single-line, point-to-point data transmission systems and
for level translators. Operation is normally from a single
5V supply; however, a built-in option allows operation
from a 12V supply without the use of additional components. The output is compatible with most TTL and
DTL circuits when either supply voltage is used.

the negative-going threshold voltage to be above zero_
The positive-going threshold voltage remains above zero
as it is unaffected by the disposition of the threshold
terminals. In the fail-safe mode, if the input voltage goes
to zero or an open-circuit condition, the output will .go
to the high level regardless of the previous input condition.

features

In normal operation, the threshold-control terminals are
connected to the VCC1 terminal, pin 15, even if power is
being suppl ied via the alternate VCC2 termi nal, pin 16.
This provides a wide hysteresis loop which is the difference between the positive-going and negative-going
threshold voltages_ In this mode, if the input voltage
goes to zero, the output voltage will remain at the low or
high level as determined by the previous input.

•
•
•
•
•

For fail-safe operation, the threshold-control terminals
are open. This reduces the hysteresis loop by causing

•

Input resistance, 3 kD to 7 kD over full RS-232C
voltage range
Input threshold adjustable to meet "fail-safe" requirements without using external components
Inverting output compatible with DTL or TTL
Built-in hysteresis for increased noise immunity
Output with active pull-up for symmetrical switching
speeds
Standard supply voltage-5V or 12V

schematic and connection diagrams
COMMON TO 4 CIRCUITS

------l

VCC2

{NOTE I

A1
GNO

0-+------.....
0-...I-----"Mrl
0--.--------1--.

I
I
I
I
I
I
I

Dual-In-Line Package

R1

""':..J
-------,
1 OF4RECEIVERS

1.6k

I
I

Uk

I
I
I
DUTPUT
GNO

4.2k

INPUT

.....

....

UI .
UI
~

NAll0NAL

Vee1

cCJ)

Y:

o-+"VIIV-+-H

I

I
IL

A

TOPlJlEW
1k

Order Number DS75154J or DS75154N
See Package 10 or 15

':'_ _ _ _ _ -.J
_______

Note: When using Vee1 (pin 15). VCC2 {pill 16) mav be left open or shorted to Vee1 When using VCC2 • Vee! must be left open or connected to the threshold control pins.

10-25

~

Interface

NATlONAL

DS75324 memory driver with decode inputs
general description

features

The OS75324 is a monolithic memory driver
which features two 400 mA Isource/Slnk) switch
pairs along with decoding capability from four
address lines. Inputs Band C function as mode
selection lines Isource or sink) while lines A and
o are used for switch·pair selection loutput pair
Y /Z or W/X).

•

High voltage outputs

•
•

Dual sink/source outputs
Internal decoding and timing cirCUitry

•
•

400 mA output capability
DTLlTTL compatible

•

I nput clamping diodes

schematic and connection diagrams

r--.-.....------.. . . . . ,....---------.....------"""'"
v--------....--o ~~.:~TW
TIMING
IN'UTS

r-'

MOOESutcr

AODRfSS
INPUTS

~DCffi~N"O......,....-t-_-+-H

++++-----'

SWITCH·PAIR

SH~L

-+--i-'

D O-......

Dual-In-Line Package
OUTPUT

!iND
Z

(SlIi'"

Dual-I n~Line Package
OUTPUT

OUTPUT SOURCE OUTPUT OUTPUT

l
Vee

V
COLLEC·
X
W
(SOURCE) 1011.$ (SOURtEl (SIIIK'

Z

GNb
1

(SINK)

Vee

OUTPUT

SOURCE

OIiTPUT

COllEC·

x

OUTPUT

V
ISOURCEI

TORS

I:>UURCFI

(SlflK)

W

ADDRESS

,II,utO

AOORESSINPUTS

GND 1 and GND 2 Me to be used in parallel.
TopvrEIil

Order Number DS75324J

Order Number OS75324N

See Package 10

See Package 14

10-26

c

~

Interface

rJ)

U1
U1
W
N
U1

......

NAnONAL

C

~

DS55325/DS75325 memory drivers
general description
The 0555325 and 0575325 are monolithic memory drivers which feature high current outputs as
well as internal decoding of logic inputs. These cir·

operate

at

higher

source currents

for a given

junction temperature. If this method of source
current setting IS not demed, then Nodes Rand
RINT
can be shorted externally activating an
Internal resistor connected from,V CC2 to Node R.
ThIS provides adequate base drive for source
currents up to 375 mA with V CC2 ~ 15V 01
600 mA with VCC2 ~ 24V.

cuits are designed for use with magnetic memories.

The circuit contains two 600 mA Sink-SWitch
pairs and two 600 mA source·switch pairs. Inputs
A and B determine source selection while the
source strobe 15 , 1 allows the selected source turn
on., In the same manner, inputs C and 0 determine
sink selection while the Sink strobe IS 2 1 allows the
selected sink turn on.

The OS55325 operates over the fully military
temperature range of -55°C to +125°C, while the
OS5325 operates from 0° C to + 70 0 C,

Slnk·output collectors feature an "'ternal pull·up
resistor in parallel with a clamping diode connected
to V CC2. ThiS protects the outputs from voltage

features

surges asso'ciated with switching inductive loads

The source stage features Node R which allows
extreme flexibility in source current selection by
contrOlling the amount of base drive to each source
transistor. ThiS method of setting the base dllve
brings the .power associated with the reSistor out·
side the package thereby allOWing the circuit to

•

600 mA output capability

•

24V output capability

•

Dual sink and dual source outputs

•

Fast switching times

•

Source base drive externally adjustable

•

Input clamping diodes

•

oTLITTL compatible

schematic and connection diagrams

Dual-In-Line Package

SOURCE

Sl

COllECTORS

Sl

~

STROBES

Order Number DS55325J. DS75325J.
DS75325N or DS55325W

See Package 10, 15 or 28

truth table
ADDRESS INPUTS
SOURCE

SINK

OUTPUTS

STROBE INPUTS
SOURCE

SINK

SOURCE

SINK

A

B

C

0

S1

'2

W

X

v

Z

L

H

X

L

H

ON

OFF

OFF

OFF

H

OFF

OFF

L

X

X
X

L

H

OFF

ON

X

X

L

H

H

L

OFF

Off

ON

x
x

X

H

L

H

L

OFF

OFF

OFF

ON

X

x

x

H

H

OFF

OFF

OFF

OFF

H

H

H

H

X

X

OFF

OFF

OFF

OFF

OFF

H = high level, L = low level, X = irrelevant
NOTE: Not more than one output is to be on at anyone time.

10-27

U1
W
N
U1

....

(0
C"')

In
,...,
c

en

~

Interface

NAnONAL

OS75361 dual TTL-to-MOS driver

general description

features

The DS75361 is a monolithic integrated duaITTL-toMaS driver interface circuit_ The device accepts standard
TTL and DTL input signals and provides high-current
and high-voltage output levels for driving MaS circuits.
It is used to drive address, control, and timing inputs
for several types of MaS RAMs including the 1103 and
MM5270 and MM5280.

• Capable of driving high-capacitance loads
• Compatible with many popular MaS RAMs
•

V CC2 supply voltage variable over wide range to 24V

•

Diode'clamped inputs

• TTL and DTL compatible

The DS75361 operates from standard TTL 5V supplies
and the MaS Vss supply in many applications. The
device has been optimized for operation with V CC2
supply voltage from ·16V to 20V; however, it is designed
for use over a much wider range of V CC2'

•

Operates from standard bipolar and MaS supplies

•

High-speed switching

• Transient overdrive minimi,zes power dissipation
•

Low standby power dissipation

connection diagrams

Dual-In-Li'ne Package

.,

.2

GNO

Dual-In-line Package

NC

NC

A'

'2

TOP VIEW

TOP VIEW

Order Number OS75361 N

Order Number DS75361J

See Package 12

See Package 9

10-28

NC

GNO

~

Interface

NA110NAL

OS75362 dual TTL-to-MOS driver
general description

features

The DS75362 is a dual monolithic integrated TIL-toMOS driver and interface circuit that accepts standard
TIL and DTL input signals and provides high-current
and high-voltage output levels suitable for driving MOS
circuits: It is used to drive address, control, and timing
inputs for several types of MOS RAMs including the
1103.

• Dual positive-logic NAND TTL-to-MOS driver
• Versatile interface circuit for use between TTL and
high-current, high-voltage systems
• Capable of driving high-capacitance loads
•

Compatible with many popular MOS RAMs

•

V CC2 supply voltage variable ,over wide range to 24V
maximum

•
•

V CC3 supply voltage pin available
V CC3 pin can be connected to V CC2 pin in some
applications
• TTL and DTL compatible diode-clamped inputs
• Operates from standard bipolar and MOS supply
voltages
• High-speed switch ing

The DS75362 operates from the TTL 5V supply and the
MOS Vss and V BB .supplies in many applications. This
device has been optimized for operation with V CC2
supply voltage from 16V to 20V, and with nominal
VCC3 supply voltage from 3V to 4V higher than V CC2 '
However, it is designed so as to be usable over a much
wider range of V CC2 and VCC3 ' In some applications the
VCC3 power supply can be eliminated by connecting the
V CC3 pin to the V CC2 pin.

• Transient overdrive minimizes power dissipation
•

Low standby power dissipation

schematic and connection diagrams
Dual~ln-line

Package

Y1

V2

V CC2

\l CC3

A2

GNO

VCC2

------.....,I----.

TODRIVERS
OTHER { ......
...

l'

INPUT A

0-----..................---1

....._-o~UTPUT

A1

+-M~.,

TOP\lIEW

Order Number DS75362N

See Package 12
Dual-In-Line Package

TO OTHER
DRIVERS

NO

V1

NC

Al

Ne

Y2

NO

Vce3

A2

NC

4-----t-------~-~--~~__oGNO

ONE OF 2 SHOWN

NO

TOP VIEW

Order Number DS75362J

See Package 9

10-29

GNO

~

Interface

NAll0NAL

0575364 dual MOS clock driver
general description
shifting may be done with an external PNP transistor current source or by use of capacitive coupling and
appropriate input voltage pulse characteristics.
The DS75364 is characterized for operation over the
O°C to +70°C temperature range.

The DS75364 is a dual MOS driver and interface circuit
that operates with either current source or voltage
source input signals_ The device accepts signals from
TTL levels or other logic systems and provides high
current and high voltage output levels suitable for
driving MOS circuits. It may be used to drive address,
control and/or tim ing inputs for several types of MOS
RAMs and MOS shift registers.

features
•

The DS75364 operates from standard MOS and bipolar
supplies, and has been optimized for operation with V CCl
supply voltage from 12-20V positive with respect to
VEE, and with nominal V CC2 supply voltage from 3-4V
more positive than V CC1 . However, it is designed so as to
be useable over a much wider range of V CCl and V CC2·
In some applications the V CC2 power supply can be
eliminated by connecting the V CC2 pin to the V CCl pin.

•

Versatile interface circuit for use between TTL levels
and level shifted high current, high voltage systems
Inputs may be level shifted by use of a current source
or capacitive coupling or driven directly by a voltage
source

•
•

•

Capable of driving high capacitance loads
Compatible with many popular MOS RAMs and MOS
shift registers
V CCl supply voltage variable over wide range to 22V
maximum with respect to VEE
V CC2 pull-Up supply voltage pin available
Operates from standard bipolar and/or MOS supply
voltages
High-speed switching

•

Transient overdrive minimizes power dissipation

•

Low standby power dissipation

•
Inputs of the DS75364 are referenced to the V EE terminal and contain a series current limiting resistor. The
device. will operate with either positive input current signals or input voltage signals which are positive with respect to VEE. In many applications the VEE terminal is
connected to the MOS V DD supply of -12V to -15V
with the inputs to be driven from TTL levels or other
positive voltage levels. The required negative level

•
•

connection diagrams

Dual-In-Line Package

Dual-I n-Line Package
VCC2

Yl

vee1

Y2

Ve e1

NC

Y2

NC

Y1

NC

A2

NO

NC

NC

A1

NC

v"

TOP VIEW

TOP VIEW

Order Number DS75364N

Order Number DS75364J

See Package 12

See Package 9

10-30

~

Interface

NAnONAL

0575365 quad TTl-to-M05 driver
general description
The DS75365 is a quad monolithic integrated TTL-toMOS driver and interface circuit that accepts standard
TTL and DTL input signals and provides high-current
and high-voltage output levels suitable for driving MOS
circuits_ It is used to drive address, control, and timing
inputs for several types of MOS RAMs including the
1103_

•

The DS75365 operates from the TTL 5V supply and the
MOS Vss and Vgg supplies in many applications_ This
device has been optimized for operation with V CC2
supply voltage from 16V to 20V, and with nominal
VCC3 supply voltage from 3V to 4V higher than V CC2However, it is designed so as to be usable over a much
wider range of V CC2 and V CC3 - In some applications the
VCC3 power supply can be eliminated by connecting the
V CC3 pin to the V CC2 pin_

Capable of driving high-capacitance .Ioads

• Compatible with many popular MOS RAMs
•

Interchangeable with Intel 3207

•

V CC2 supply voltage variable over wide range to 24V
maximum

•

V CC3 supply voltage pin available

•

VCC3 pin can be connected to VCC2 pin in some
applications

• TTL and DTL compatible diode-clamped inputs
•

Operates from standard bipolar and MOS supply
voltages

• Two common enable inputs per gate-pair

features
•

High-speed switching

• Quad positive-logic NAND TTL-to-MOS driver
• Transient overdrive minimizes power dissipation
• Versatile .interface circuit for use between TTL and
high-current, high-voltage systems

•

Low standby power dissipation

schematic and connection diagrams

TODRIVERS
OTHER

Dual-In-Line Package

{+--------J----.

INPVT A

o-----....-+.+-i

ENABLE E1

0-'--",---+-+."

ENABLE E2

o-...---!---+-I<....-'

V'

A4

2E2

14

2£1

13

A3

Y3

VCCJ

12

...+4..........I4IIHr--o ~VTPUT

I

VI

Al

1E1

lE2

A2

TOP VIEW

TO OTHER {
DRIVERS

PositiV\" Logic;: Y" A"Et"E2

~....~~-4--------4~--~-~--oGNO
ONE OF 4SHOWN

10-31

Order Number DS75365J
or DS75365N
See Package 10 or 1!?

V2

GND

~
I

M
0-

co
co
C/)
o
M

o

Interface

~

NAll0NAL

CO
CO

C/)

o

057803/058803, 058813 two phase oscillator/clock driver

M

general description

........

o

~
C/)
o

DIP. The DS8813 comes in an 8·pin molded DIP,
providing damped MOS outputs only.

The DS7803 is a self contained two phase oscillator/
clock driver. It requires no external components to
generate one of three primary oscillator frequencies
and pulse widths. Other frequencies can easily be
obtained by programming input voltages. Three sets of
outputs are provided: damped and undamped MOS
outputs and TTL monitor outputs. The MOS outputs
easily drive 500 p F loads with less than 150 ns rise and
fall times. In addition the outputs have current limiting
to protect against momentary shorts to the supplies.

features
•
•
•
•
•
•

The DS7803 and DS8803 areavailable in a 14·lead cavity
DIP. The DS8803 is also available in a 14·pin molded

Two phase non-overlapping outputs
No external timing components required
Frequency adjustable from 100 kHz to 500 kHz
Pulse width adjustable from 260 ns to l.4,us
Damped and undamped MOS outputs
TTL monitor outputs

block and connection diagrams
OS7803/0S8803

14Vss

INHIBIT
WIDTH

2

lJ TEST

J

12FR£Q
CONTROL

CONTROL
MOS

DAMPfD,.,

MOS"1
MOS

V"

5

DAMPED '"2
MQS0l

J
Ro

MOS
DAMPEO",

TTl "'2

GNU

Voo

....1--.....,,",.,..-+':...0 ~2~PEO y~
' - - - - - - 1 - ' - 0 MOS<;>,

L..------t-=-o MOS '"
v~

Voo

TOP VIEW

Order Number OS7803J, OS8803J
or OS8803N

See Package 9

Or

14

"ST

OS8813

Dual·ln-line Package
FR~~~~~~~ 0-"+--------,
PUlSEWIOTH

PULSE

5

1

INHIBIT

CONTROL
v~

2

"'l~~~PED

"
P----"NIr--+'-o
"

TEST

OUTPUTS

FREO

Voo

CONTROL

TOP VIEW

Order Number DS8813N

See Package 12

TEST

10·32

c

Interface ~

~

S

.......

NAll0NAL

c
en

057807/058807. 058817 two phase oscillator/clock driver

o
.....

general description

c

The OS7807 is a self contained two phase oscillator/
clock driver. It requires no external components to
generate one of three primary oscillator frequencies and
pulse widths. Other frequencies can easily be obtained
by programming input voltages. Three sets of outputs
are provided: damped and un-damped MOS outputs and
TTL monitor outputs. The MOS outputs easily drive
500 pF loads with less than 75 ns rise and fall times.
In addition the outputs have current limiting to protect
against momentary shorts to the supplies.

co
co

The OS8817 comes in an 8-pin molded DIP, providing
damped MOS outputs only.

features
•
•
•
•
•
•

The OS7807 and OS8807 are available in a 14-lead
cavity DIP. The OS8807 is also available in a 14-pin
molded DIP.

Two phase non-overlapping outputs
No· external timing components required
Frequency adjustable from 400 kHzto 2 MHz
Pu Ise width adjustable from 130 ns to 700 ns
Damped and un-damped MOS outputs
TTL monitor outputs

block and connection diagrams
O87807/0S8807

Dual-In-line Package
11
Vee

10

INHIBIT
TTL.,II

WIDTH

2

CONTROL

MaS

l

DAMPED ")1
TTL ('2

MOS~Jl

Mas 5
DAMPED 92

GND

MOS02
MOS
Ro
10

DAMPED ~)1

Voo

fJ!IOS
DAMPED <;12

TOP VIEW

Order Number OS7807J,
OS8807 J or O88807N
See Package 9 or 14

MOS"I
MOS(I2

V..

Voo

TEST

INHIBIT

OSS817

Dual·ln·Line Package

FREQUENCY
CONTROL

PULSE

1

INHIBIT

WIDTH

PULSE WIDTH
CONTROL

10

00]
'.)2

10

.

TEST
MOS
DAMPED
OUTPUTS

FREO
CONTROL

Voo

TOP VI£W

Order Number OSB817N
See Package 12
VOS

Voo

TEST

.INHIBIT

10-33

en
CO

~

~

App Notes/Briefs

NAllONAL

»
z

~

o

-4
~

CD
C/)



(/)

Q)

.c
t-

O

LINE SELECT

tOLUMN ADDRESS

INPUTS

Figure 5. Basic Digital Character Generator and CRT
Refresh Memory

CHI' ENABLE

BIPOLAR COMPATIBILITY

Figure 4b. MM5241 Vertical Scan Character Generator
Element

A dynamic register is one that must be clocked at
some minimum frequency. Data is retained in the
form of charge storage and the charges would
eventually leak out of the storage nodes if not
. re·established. In contrast, the ROMs being dis·
cussed are static devices, generating an outpu·t only
when addressed. Specifically, they are designed
and programmed to be sequenced by TTL ICs.
Furthermore, the new generations of ROMs and
registers accept and put out bi polar level signals
and operate off +5 volt and -12 volt power
supplies.

or:t
I

Z



UJ

Then, as the second of the seven recirculations
begins, the beam would have to be shifted an
additional line to start the second series of line
scans-and so forth.

Assume that on the first sweep of the CRT beam,
the ROM is being addressed by the six register
outputs representing characters N I, N2 , 1\13, etc.
The first horizontal, 5·dot line of each character in
the display row are displayed in sequence. Then
the line address inputs to the ROM from the con·
trol logic Change to their second state ~ the time
that N I has completed its recirculation to the N
register's outputs. Thus, on the second CRT
sweep, the second series of 5-dot lines are displayed horizontally for all N characters. At the
end of seven recirculations, the complete row of N
characters is on the display.

The M-N-N technique does not require any more
register stages than the M-Ioop technique and
significantly reduces control and drive circuit
requirements-again producing a lower cost per
function.
REFRESH MEMORY MODULATION
The technique employed in' the M'N-N refresh
memory is called "clock modulation". In other
applications, it has already been found to significantly reduce total storage costs. 3 It helps minimize power dissipation-in most terminals, the
amount of power consumed is unimportant in
itself since line power is used, but registers are
powered by clock drivers and the cost and complexity of the drive network is certainly important. Furthermore, the technique allows long, very
high-density MaS circuits, produced by relatively
inexpensive low threshold (bipolar compatible)
processes to operate at very high effective character rates.

Now, the contents of the N register are not returned to the input of the N register. Instead, they
are fed back to' the input of the M-N register and
this register is clocked to load the N register with
the second group of N characters. The M-N register
is then held still while the N register recirculates
Seven times to generate the second row of characters on the display. After all M characters are on
the display, the first group' of N characters is
reloaded into the N register and the entire process
is repeated to refresh the display.

CD

..c

~

o

~
I

Z

«

Human factors-chiefly the eye's response timedictate that the display be refreshed at least 30 to
35 times a second for good legibility. Most designers prefer to refresh at 60 Hz power line frequency because it is generally the most convenient
frequency.

As shown in Figure 7, the raster scan system uses
nine clOCk intervals to generate a row of characters
on the display. Seven are for the high-speed recirculations. Durina the other two intervals, the
first N characters are fed back from the output of
the N register to the input of the M-N register
while the N register is loaded from the M-N register with a new row's worth of characters. Since
two intervals are used foi th is operation, the registers operate at only half the character rate. The
rest of the time, the M-N register is chargequiescent. Its average clock frequency is only
about 11 % of the character rate.

Besides generating the line address inputs (that is,
the number of recirculations of the N register). the
control lOgic keeps track of the number of dots
and spaces in he output bit stream. The spaces
between characters in a display row are inserted as
"0" bits when the ROM outputs are serialized by
the TTL register. The counters also control the
loading and recirculations ofthe MaS registers in
the refresh memory subsystem.

In other words; most of the refresh memory
(perhaps 90% in a large display system) operates at
only half the character rate (say 1 MHz instead of
2 MHz) only two-ninths of the time. The savings in
the drive network alone can be judged from the
power-frequency plot for a typical MaS dynamic
register (Figure 8)3. In addition, the designer can

A multiple row raster scan display could be generated with the M-Ioop technique in Figure 5 but,
the implementation is cjifficult and impractical.
This technique is more appropriate for single row
displays. Using this method of display, all M characters to be displayed must recirculate seven times
to generate a 5 x 7 horizontal scan, so all stages of
the registers must operate at the full character
rate. To form several rows with a single-loop
memory requires an interlaced scan rather than an
ordinary raster scan. The first series of 5-dot lines
are generated by the first N character outputs as
before, but the next set of N inputs to the ROM
will generate the first group of 5-dot lines in the
second row of characters on the display. Therefore, the beam must jump to the new line position.
To display four rows of 5 x 7 characters, for
instance, would require a staircase generator that
would step the beam by the height of nine scan
lines (seven dot lines, plus two blank spacing lines
between rows) three times after the initial scan.

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Figure 8. Power YS Frequency Plot of Typical MOS
Dynamic Register

increase the number of characters generated per
refresh cycle, for a larger display, or increase the
number of dot lines, for a larger fClnt, or both.

11-6

»

select the dot lines and,the 6-bit ASCII code from
the 256 (2") word locations in each ROM. These
two additional bits dre supplied by the A and B
outputs of a TTL binary counter
DM8533 (SN7493) and the counter's C output is
used to commutate the MK001 and MK002. The
ROMs are enabled by an output at the TTL logical
"0" level. Thus, with the gating shown, the
MKOOl is enabled during the first four of seven
line-rate clock inputs anI:! the MK002 during the
remaining three inputs.

Remember, though, that dynamic registers must
be clocked to retain data. How long can the M·N
register be turned off] Long enough for practical
.applications. The guaranteed minimum frequency
is temperatur~ dependent, since temperature
affects charge-storage time. The minimum for
National Semiconductor's MM-series registers is
500 Hz at 25°C, rising to 3 kHz at 70°C (maximum operating temperature is 125°C, but that is
not a display environment). At room temperature,
the registers can safely be quiescent for as long as
2 msec. (The typical MM register will actually hold
data for 10 msec.) Suppose the N register stores 40
characters and operates at 2 MHz. The quiescent
period can be as short as 40 it 7 x 0.5 = 140 [..ts. If
standa~d TV raster timing is maintained then the
quiescent period will be 7 x 63 [..ts = 44111s.
Obviously, the designer has great leeway in character rates, .operating temperatures, and register
capacities.

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The data transfer from the character generator to
the bipolar memory in Figure 12 is accomplished
by sequencing the column address lines and en·
abling the appropriate memory simultaneously.
Each pair of DM8550s (SN7475s) then contains
the data for one of the five columns in a character:
The DM8842 (SN7442)-one in 10 decoder pro·
vides the decoding functions which are connected
to the enable line on the quad latches.

A seCond consideration which should not be overlooked in systems cost is the compatibility of
ROMs in multi·package character fonts. Optimum
ROM usage and organization will result in lower
systems cost. ROMs will also find applications in
micro-programming and code conversion where
synchronous operation is preferred.

LARGER, FASTER SYSTEMS
Most low cost ·terminal designs have been based on
the 5 x 7 font because of the high cost of diode
matrixes and wideband video circuits. But it is by
no means the most 'legible font. A 5 x 7 font is
acceptable for applications in Which the display
changes slowly, but human engineering studies
indicate that it causes severe eyestrain when an
operator reads rapidly changing data.

The 8 x 10' font is much better and 12 x 16 is
almost optimum for legibility. Small, lower case
characters can be sharply defined, too, and they
almost appear to be drawn with continuous
strokes.
System designers considering these fonts for lowcost displays run, at present; into CRT cost problems. The least expensive displays are televisiontype CRTs with limited video bandwidth. Bandwidth also limits the number of characters that can
be .displayed simultaneously. Not counting the
times required for beam retrace. and functions
other than character generation, which reduce the
time available in a refresh cycle for dot handling,
the necessary bandwidth is roughly:

The greatest portion of the discussion has. dealt
with a 5 x 7 font. A full 64 character display can
be coded into a single MOS package. Now that LSI
has entered the scene, we see,a different trend
towards larger, more stylized font. The economy
of MOS ROMs will provide the customer with a
more legible character font at the present cost of
"discrete" character generators. An analysis of the
most practical solutions to various fonts are tabulated in Table 2. The part types which have been
used to generate a 64 x·7 x 5 raster scan font are
the SKOOOl-3 ROM kit or the MM5240 which is
under .development. The vertical scan font is satis·
fied by the SK0002-3 ROM bit or the MM5241
which is under development. If we examine the
other possible fonts, these same two monolithic
elements will satisfy the requirements if they were
64 x 8 x 5 and 64 x 6 x 8 respectively. Therefore,
the added memory storage is being .incorporated
into the MM5240 and MM5241. In some of these
cases the font is scanned in the horizontal' dimension while in others the font· is scanned in the
vertical dimension. You find both the 8 x 5 and
6 x 8 elements capable of satisfying the font
matrix requirement. Since all the ROMs listed are
static by_design, there are no special clocking hardships induced with the solution of any of these
larger fonts. This i.s not true for all dynamic ROM
solutions.

TV-type CRTs have a maximum bandwidth of
about 4 MHz, of which only about 2.5 MHz is
generally useful. If one uses a 5 x 7 font with one
spacing bit' (6 x 7 total) at a 60-Hz refresh rate,
each displayed character needs 2.52 kHz of bandwidth, so the limit is about 1,000 characters. In
contrast, the new ROMs take as little as 700 nanoseconds to generate a dot line, or about 5 /-1s per
character, That's fast enough to generate 200,000
characters a second, or a display of more than
3,000 characters at the 60-Hz refresh rate. The
actual dot rate in the serial bit stream to the CRT
can approach 10 MHz. And if larger fonts are
generated in some multiplexed addressing mode,
the required bandwidth can be much higher.

As mentioned before and shown in the table, the
same ROM element is used in both raster scan or
vertical scan applications. If we recall the design
solutions showing the refresh memory and character generator for a 5 x 7 display, the first thing

Luckily, these problems are not insurmountable
and there are alternatives to using oscilloscopequality CRTs or storage tubes, which are fine for
high performance applications but too rich for
low cost terminals.

BW; (dots and spacing bits per character)
X (characters per display row or page)
X (refresh rate)

11-10

»

Obviously, the designer can drop the refresh rates.
New CRTs with longer persistence phosphors
facilitate this. Also, CRT manufacturers have been
responding to the new terminal market by working
on bandwidth improvements, and they are apparently going to reach 10 MHz in moderately pri~ed
video systems soon.

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The register stages can either shift the bits to the
serial output for recirculation or store the data
indefinitely. Hence, displayed characters can be
swept along a line of indicators, "frozen" on a
~tationary display, or made to reappear periodIcally at any desired repetition rate.

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A code-converting!character.generating ROM can
be placed at the register input, to display numbers
and symbols or alphanumerics. A deSigner can get
almost as much flexibility from a lamp or panel
display as from a CRT display. In fact, the first
application of the MM5081 is controlling a matrix
of neon lamps in a moving billboard display.

Finally, the designer is not obliged to display his
characters digitally just because he uses a MaS
ROM. Don't forget that the ROM is really working
as a code converter, generating a 35-bit machine
language code from a commu nications code. The
language translation can be whatever the situation
requires.

Some applications for character generators in instruments are also cropping up. Displaying range
scales on an oscilloscope is a good idea that can be
improved upon with the new ROMs. The display
frees the operator of the chores of mentally cijlculating scale factors and manually writing these on
scope photos. With an alphanumeric font, the
camera can also record information such as test
conditions, date and time of test, identification
numbers, etc. Photo sequences and the data
needed to analyze the curves can be coordinated
automatically.

All that need be done is update methods used in
analog displays, which form characters with
strokes rather than dot lines or columns. The
ROMs can be programmed such that the bit outputs, when integrated, control X and. Y ramp
generators. The slopes of the ramp functions are
determined by the number of bits in a sequence
and the lengths are determined by the locations
chosen for turn·off bits. As in the vertical scan
technique, the ROM is addressed at the character
rate.
Even though some characters can be formed with
one or two strokes (I, L, etc.), equal time should
be given to all characters in a page display to keep
the character rows aligned. A standard sized area
of the MOSFET array, such as 6 x 8 or 5 x 8
should be used for each character. Most patterns
would thus be a combination of stroke and. nostroke outputs. The single-chip fonts have an
8-stroke 'Capacity for each of 64 characters wh ich
is more legible than the standard segmented type
of instrument readout, since slant lines could be
generated wherever needed.

Similarly, a ROM can be programmed to display
standard curves for gO-no-go equipment checkout
operations. For example, if a radar's pulse amplifier should have certain output characteristics, the
ROM generates the correct outp". "\lrves through
a digital-to-analog converter and str6"',~enerator.
When an actual operating characteristIc. ~nd the
reference curve are displayed simultaneou';..." the
operator can tell at a glance whether the rad", is
functioning properly. Many curves or general pur
pose curve segments can be programmed into a
ROM and picked out as needed with selector
switches or a ROM microprogrammer.

APPENDIX

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ROMs can be programmed as lookup tables,
random,logic synthesizers," encoders, decoders,
and microprogrammers as well ascharacter generators. A single ROM can perform limited combina·
tions of these functions, virtually qualifying it as a
microcomputer. It has been suggested that this
capability be used in control panels to perform
functions like actuating an alarm when a trans·
ducer level goes out of range and initiating corrective action. ROM addresses can be derived from
digital meter circuitry. In multi-point measuring
systems, this would provide the solid state equiva·
lent of a rack of meter relays.

WHAT ABOUT INSTRUMENTS
AND CONTROLS?
While it is safe to predict that 1970 will be "the
year of the MaS" in alphanumeric terminals, MaS
applications in numeric readouts are just beginning
to emerge.
A new device with considerable promise in this
field is a high voltage, MaS static shift register, the
MM5081. Developed by National, it has a TTLcompatible serial input, 10 parallel outputs that
can stand off -55V, 10 latching-type storage
stages, and a serial output.

DEFINITIONS OF DISPLAY TERMS
Font: A set of printing or display characters of a
particular style and size. A typical dot·character
font is 5 x 7, referring to the number of dot loca·
tions per character.

This novel combination of functions means that
the MM5081 can drive lamps, numeric indicator
tubes, filament tubes in segmented number and
symbols displays, electroluminescent panels, and
the new gas·cell arrays. In short, it provides MaS
with a good foothold on the numeric side of the
readout family tree in Figure 1.

Dot Character: A character formed by a pattern of
bright dots on a CRT screen or dark spots on hard
copy, rather than by continuous strokes. The dot

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pattern. corresponds to bit-storage patterns in a
digital memory_
Column: In a dot character matrix for vertical
scanning,·a column is a vertical series of dots. On a
page display, a column contains several vertically
aligned characters. In this article, a column refers
to a dot column .
Row: A horizontally aligned group of characters
on a display.
Line: ·'n this report, line refers to the number of
dots displayed in a single scan when a raster scan
character is generated. In a 5 x 7 dot character,
there are seven lines of 5 dots each.
Page: A display consisting of several rows of characters, corresponding to lines on a printed page.
Raster Scan: See Figure 9.

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Vertical Scan: Two types of CRT vertical scans are
shown in Figure 10. In hard copy applications, the
dots in a column or character may be printed
simultaneously· by the printing transducers rather
than being scanned.

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Sawtooth Scan: See Figu re 10.

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Dynamic Element: A digital device that must be
clocked. A dynamic shift register must be clocked
to retain data_ A dynamic ROM is clocked to
decode the address and generate an output.
Static Element: A device that does not have to be
clocked to retain data. A static ROM uses direct
coupled decoding for bit selection and static output buffers.
REFERENCES

1. A.D. Hughes, Desired Characteristics of Automated Display Consoles, Proc. Society for Infor.
mation Display, Vol. 10, No.1, Winter, 1969.

2. Dale Mrazek, MOS Delay Lines, Application
Note AN-25, National Semiconductor, April, 1969.
3. Dale Mrazek, Low Power MOS Clock-Modulated Memory Systems, Application Note AN-19,
National Semiconductor, April, 1969.
4. Floyd Kvamme, Standard Read Only Memories
Complex Logic Design, Electronics,
January 5, .1970.

Simplify

Pedestal Scan: See Figure 10.

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11-12

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App Notes/Briefs

NAnoNAL

HIGH VOLTAGE SHIFT REGISTERS
MOVE DISPLAYS

There was a time when one had to go to Times
Square or Picadilly Circus to see a moving lamp
display. But now they're going into stadiumscore·
boards, stock brokers' offices, waiting rooms and
many other places where an attention· getting man·
machine interface is wanted.

REGISTER PLUS SWITCHES
Figure 1 shows in simplified form how one
MM5081 would be connected to drive a bank of
10 neon lamps. A data bit stream is entered into
the serial input and shifted at the clock rate to the
serial output. Then, it can be routed back to the
input andrecirculated to repeat the display motion.

Naturally, display designers would like to make
the control and drive circuitry more compact and
less expensive. What's needed to replace the banks
of discrete switching devices is storage and switching high-voltage circuits in monolithic form. That's
exactly why National developed the MM5081 high·
voltage MOS shift register.

The states of the data bits circulating through the
register control the switching of the MOS output
transistors. When a bit in the true state (MOS
logical "1") is being stepped down the 10 register
stages, the lamps will turn on and off in sequence
at the register clock rate. In this mode, the clock
rate is the display rate. A typical display rate will
move the light along by no more than two or
three lamps per second, making any message dis·
played on parallel rows of lamps easy to follow and
read. A latch-type register cell that can shift at frequencies to DC and a single-phase clock input are
used in the MM50~1 to achieve this effect. However. the logic formatting the data for display will
have to run at some higher rate. If the control
system has other functions as well, it may be
desirable to load the register at a clock rate in the
hundreds of kilohertz. At such a high rate, the
bit stream flashes by the 10 parallel output
switches too rapidly to see the lamps being turned
on. After loading, when the main system logic is
freed, the clock rate is dropped to. the display
rate and the message is seen. The message simply
recirculates at the display rate until new data is
ready for loading.

This unusual IC is the first MOS device capable of
driving gas·discharge tubes and other high·voltage
display elements without going through a bipolar
buffer such as a transistor or SCR. Moreover, it can
"walk" the message around and around the dis·
play when operated ina recirculating mode. The
latter feature provides a.clear-cut division between
system functions - the MM5081·s take on the responsibility of display operation per se, while the
system logic need only format messages and control updating by invading the registers. In other
words, the main system logic need pay only intermittent attention to display operation. If the main
system is a data-processing computer, for instance,
it can handle the display like any other peripheral.
Relieved of responsibilities for mOiling and refreshing the display, the main system can do more data
processing between display updates.

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The use of high-speed logic for control is facili. tated by making the MM5081 with low-threshold.
p-channel, enhancement-mode MOS transistors. As
a rule, a low threshold device allows data to be
entered at bipolar logic levels.

brings the serial output back to the serial input
through the top gate when the "new data enable"
line is low (DTL/TTL logical "0") or permits the
registers to be reloaded with new data when the
enable line is high. A pull-down resistor is placed
on the register output to handle 1.6 mA the current sinking required for operation of the TTL or
DTL recirculation control gate.

The output transistors do not need a large gatevoltage change to turn on and off. They are also
low-threshold devices in this sense. But they have
to withstand transients up to 100 volts and stand
off steady state voltages up to 55V to operate
lamp-type displays reliably. Adequate gate logic
voltages for the output transistors must be ensured
to make the lamps glow brightly when they should
be on or to make them free of any residual glow
due to switch leakage when the switching transistors are turned off. That is, a low RON and high
ROFF must be ensured despite very high voltage
on the MOSFET drains. Be·cause a pullup resistor
is used, the input gate should be .. TTL or DTL
device with an uncommitted-collector output able
to withstand at least 1OV. Amongsuch devices are
the DM881 0, DM8811 or DM7426 (SN7426) quad
NOR.gates, or the DM8812 hex inverter. All these
TTL devices will stand off to 14V.

TIC.KER-TAPE DISPLAY
A straightforward type of moving lamp display is
illustrated in Figures 2 and 3. Simple messages such
as CALLING DR. CASEY .•. CALLING DR.
CASEY ... DR. CASEY, PLEASE REPORT TO
SURGERY ... or stock quotes, or a series of
instrument readings would be displayed as 7X5
characters by this system. That is, each character
would be a lighted lamp pattern selected from a
moving matrix seven lamps high by five lamps
with a moving column of lamps turned off between
characters. The off column is a space bit in each
lamp row.
Assume that .the display is long enough for 33
characters. Each row requires 33X6 lamps and
198 register stages. Each row is a cascade of 20
MM5081's. The input of the first register and the

The other two gates used in the input switch can
be any TTL or DTL types. The arrangement shown

OATAIN
.OW,

FIGURE 2. 7XN Bit Shift Register and Display

11·14

output of the last register are connected as in
Figure 1, and the registers in between are simply
daisy-chained by connecting each serial output t~
the next serial input. All seven rows would use
140 register packages_

switch. The purpose is to limit the current and
voltage across the lamps and the MOS output transistors to ensure that they operate reliably and
have long Iives. Also, the method reduces power
consumption and allows lower power, inexpensive
high-voltage power supplies to be used.

The character data for this type of system can be
formatted by a standard character generator. For
instance, the standard ASCII code can address a
bipolar compatible read-only memory such as
National's MM5241AA, which is programmed to
generate 5X7 dot·type characters for CRT display.
However, in the lamp display system, the display
refresh function is handled without an additional
memory. The column bits are entered in each
register chain, as before, through the input gating
at a rate determined by the clock rate supplied
the MH0025C clock driver. The MH0025C is a
two-phase driver. However, since the MM5081
takes a single-phase clock input (converted to a
two-phase clock inside the register package), only
one of the dual drivers in the MH0025C package
is shown (the other half can be used to share the
clock-drive load).

The high-voltage switch seen in Figure 3 and
detailed in Figure 4 switches at a rate of 50 Hz and
a duty cycle of 25%. Thus, when any of the MOS
output transistors is on, the lamp that is "on"
during that 250 msec display-rate interval (100%
duty cycle at 2 Hz) is actually on for only 5 msec
at a time. Then it turns off for 15 msec. This refresh rate was chosen because it provides a good
lamp intensity with no apparent fl icker.

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After the registers are loaded, the clock into the
driver is dropped to a frequency of 2 Hz, if the
register was loaded at a higher frequency. This rate
is stabil ized by the coupl ing capacitor Ce . The
coupling capacitor on this type of driver determines the maximum pulse width, but the mini·
mum pulse width is established by the clock
signal. So, at the lower frequency, the characters
sweep smoothly from right to left across the display lamps. They repeat the message every 100
seconds because 200 register stages are in each of
the seven parallel rows.

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Both the clock driver and the registers operate off
the 10V and :..aV power suppl ied.

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The -125V supply turns on the lamps, and the
-45V supply turns them off. But what is actually
being used is the voltage difference, or bias. Most
glow-discharge lamps require a 65V starting voltage
and a 60V holdi ng voltage. The switch keeps the
lamps alternating between these levels while the
MOS transistors are on, but imposes a maximum
voltage of only -65V on the MOS transistors (that
is, 125-60V) for the 5 msec "on" time. The
MM5081 can easily' take this - the spec allows
-100V at 60 Hz (or 16.66 msec) and they are
stress-tested to this level.

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NEW DATA

INPUT

INDUSTRIAL DISPLAYS

The characters displayed can be any kind of
symbol within the resolution of the lamp array from letters to cartoon characters - and within the
flexibility of the controls. Getting patterns to
move back and forth while changing shape is
technically feasible, but would require complex
clocking techniques to put the bits in the desired
location. Static pictorial displays would be fairly
simple to implement, merely requiring loading of
the registers at a high rate followed by storage at
a DC display rate for the desired time. Although
the characters would appear static, the high-voltage
switch would keep the actual duty rate low.

FIGURE 3. System Block Diagram

DISPLAY DRIVE

The high voltage supply (shown in the block diagram in Figure 3) is generated from a high voltage

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There are many potential new applications for
moving-lamp displays in industrial control systems_
Functions such as process flow rates through
several feeder pipelines or subassembly line rate
in an assembly plant, cannot easily be set up on a
CRT display. Complex computer graphic techniques or very expensive multi-gun displays may
be needed.
The clock rates and lengths of a number of rows
of lamps can readily be adjusted by hand-operated
controls, such as voltage-controlled oscillators and
gating between registers chosen by selector switches. Any feeder-line display rate that can be represented by the display rate could therefore be varied
at a compressed scale of time and distance until the
display operator arrived at the optimum balance

of rates. This is a visual approach to a problem that
generally requires complex mathematics and anaItlg computers to solve.
Nor do the rows of lamps have to be al igned.
Individual rows might represent route sections in
a transportation network between junctions_ By
driving each section at a display rate simulating
the speed of a particular train, and switching the
"train" of moving lights from row to row via
switches at the junctions (serial output to serial
input register connections), control personnel
could simulate system operation. Problems such
as tie-ups - or worse - at junctions could be worked out by varying display rates for the trains whose
schedules conflicted.

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App Notes/Briefs

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FIGURE 2. Timing Diagram For Two Phase Dynamic Shift Registers

establish a "0" at node B in that case, an electrical
ratio between the on impedance of O2 and 0 3
must be considered by the cell designer.

The ratio dynamic shift register cell of Figure 1b
has only one isolated node which limits minimum
frequency operation. It, like the ratioless cell, is
the gate node of the logic transistor. The ratio cell
does not rely on stored precharge to establish a
"1" level on a succeeding logic gate mode. If a
"0" level had been transferred to node A of the
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VINITIAL

Voltage at critical node immediately
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When calculating temperature effects of a system
operating in the clock burst mode, the designer
must remember that power dissipation in the shift
register is approximately double at 2.5 MHz what
it is at 100 kHz. High frequency bursts will heat
the chip, causing high junction temperatures which
reduce the time the clocks can be off.

¢d or ¢d for ratio cells

SUMMARY

The initial voltage can be optimized in two ways:
by using the highest clock amplitude possible and
by allowing something greater than minimum clock
pulsewidth to insure that the maximum amount of
charge is coupled to the node (and in the case of
the ratioless cell, that the maximum precharge
voltage is obtained before transfer). A high value
of VGG or V oo , the negative supply voltage, in·
creases on·chip power and therefore junction tem·
perature, as well as increasing the minimum reo
quired node voltage. It is a good idea, therefore,

Dynamic shift registers can be operated at very
low clock rates if manufacturers data sheets are
consulted and the proper clock phasing is used .
Added margin can be designed into systems by
keeping clock amplitudes high, the clock pulse·
widths 10 to 20% wider than'specified minimums,
power supplies low and temperatures as low as
possible. Beware of circuit board hot spots which
increase the temperature of individual packages,
or extensive interlead coupling or ringing which
could result in positive clock spikes.

«

11·20

App Notes/Sriefs
»
3
...c;'CD
I»
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AMERICAN AND EUROPEAN FONTS IN
STANDARD CHARACTER GENERATORS

I»
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C-

Ten popular American and European 64-character
subsets for displays and printers are now available
from Natronalas single-chip, standard character
generators. These parts, listed in Table 1, are sold
off-the~shelf without a ROM masking charge.

Input-output configurations and character formats
for the ROMs are shown in Figures 1 and 2. Application NoteAN-40 The Systems Approach to
Character Generators gives examples of line and
column address-control logic, and CRT and printer
operating ,tech niques.

The ROMs are static, bipolar-compatible types,
operating without clocks on standard power supplies. Rowand column access times are typically
450 and 700ns respectively. An MM4240/MM5240
2560-bit ROM is used for the 5 x 7 horizontal-scan
fonts and an MM4241/MM5241 3072-bit ROM for.
the 7 x 5 vertical-scan fonts_ The MM4240 and
MM4241 operate at -55°C to +125°C and the
MM5240 and MM5241· at -25°C to +70°C.

::J

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Dr
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64-CHARACTER SUBSET

O

:r

FIGURE

Upper·case alphanumeric

3

ASCII

Lower-case'alpha and symbols

4

Hollerith

Upper-case alphanumeric

5

MM4240ABZ!MM5240ABZ

EBCDIC-B

Upper-case alphanumenc

6

MM4240ACA/MM5240ACA

EBCDIC

Upper-case alphanumeric (IBM)

7

MM4241ABUMM5241ABL

ASCII

Upper-case alphanumeric

8

MM4241 ABV /MM5241 ABV

ECMA

Upper-case AfN, Scandiriavian

9

ASCII

MM4240AE!MM5240AE
MM4240ABUIMM5240ABU

...

()

;...
C)
CD
::J
CD

...

I»

MM'42'41ABW/MM5:?41A'BW

ECMA

Upper-case A/N, German

MM4241ABX/MM5241ABX

ECMA

Upper-case A/N, general
European (French, British, Italian)

11

MM4241ABY IMM5241ABY

ECMA

Upper-case AJN, Spanish

12

TABLE 1. Single-Chip, Standard

Hori:iontal~~an

(CItARACTER
ADDRESSI

0,
~M424t)1

MM'' '

0,

\

Genera~ors

"
"
b,
b
4

~

,ow

COLUMN
OU1I'tJTS

•

OUTPuts

S'

iil

10

and Vertical-Scan Character

IN~~~~

h.

0,

ROW

'i

COLUM ..

001.

AODRUS '
INPUTS )
ROW

CHiPENAll£

0------'

COLUMN

ADDRESS {
INPUTS

•

DIU • • •
1\11 • • •

~OORESS100

•
'01.
110.

111.

ADDRESS

0,

DOlI 8,S~B!Je.8.

L.

\ c.

."

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MM4240AAiMM5240AA

::

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r+

Vertical Scan (7 x 5)

ADDRESS)

CD

III

Horizontal Scan (5 x· 7)

itHARU;~:.l .

c:

o
"C
o

CODE

TYPE NUMBER

m

gg'r,;ii2§

t

U-.I

'
O.

8..
••
B,.

••
•
•

•

oUTPun B. . . .

82

PROGRAMMA8LE
tUlI'ENABtE

•

0,

(M ROM COltFrGUAATIOIi

(A) ROil CONFIGURATION

fiGURE 2. Vertical-Sean Character Generator ROM

FIGURE 1. Horizontal-Scan Character, Generator ROM

11-21

•

w

..
..
.
....

1/1

g

ca
Q)

c:
Q)

C!)
Q)

(,)

~

ca
..c:

Note that each ROM has a chip-enable input to
permit multi-ROM operation with common control
logic_ For instance, two horizontal-scan ASCII
character generators may be operated in tandem to
obtain upper and lower-case characters_ In this
case, chip-enable would be controlled with bit b 6
of the normal 7-bit ASCII code, and its complement, ti6 .

characteristics of all the horizontal-scan character
generators) .
MM4240AEiMM5240AE generates unique symbols
describing the ASCII-7 control codes, as well as
lower-case letters (Figure 4). The designer may not
wish to display or dot-print the symbols. Since the
symbols are generated only when the most significant address bit is logic "0", this bit line maybe
used to disable the chip, and blank the screen when
control signals are transmitted. If not, the system
designer can use the symbols as he likes.

HORIZONTAL SCAN FONTS

(.)

'E

ca
c:
....ca

'tl
(J)

,E

....1/1c:
o

u..
c:
ca
Q)

..o

Q.
j

W
'tl

c:
ca
c:
ca
(,)

''::
Q)

E



•••: ••••: .el :::- •••• •••::

·i:

...· :..............: :••.!-....! 1··-:
....••... .... .. ... ·•-:-......
· ...: .••••
. :1.
..
.
..
·
.
.
..
.
....
..... ... :.. e: _.1._ -:- ::
·. ··..·: .·...·
•: ·
: ·· .·.
··....··• ····.....·....· ......
··
· · ·...." : · · · ·..·:" ·.. ...··......
: ·
....
.....
·..:· ·.·....•· .....
.... ....: ·.......·····....'· ..n" ::..'
"
...,..
.... ....
..."....
..........
.. ..
·
.
.
.
.
·...... ...............
.. ...... .
···:......::.......-_......
.- .......
....:......: :.. ·••.1 ·...:·... .....::
.. -_. .....•. ".. " ...
·.....:....: :....................
..••:-.:......
.:::
:... .
: ...
......
..
...
i···! .i••: :•••• •i ..: I•••• ! :...1
... ...
··:••e:··: .i.··" ...·:: .. ······ ····..• ._·.....·.·
"
"
~

ro

~

~

00

61

0(10(11(1

000011

OIlO1{!D

000101

000110

000111

" "
:...: :...! :..:
000000

10
0111 ODD

11
001001

•E

12
1101010

13
001 a11

14

IS

16

11

001100

001101

00111(1

001111

,.~.

20

12

2J

010001

"
MM424OAIU!
1oIM§24DABU

30

010011

"

.,

:

: : : .::

40

41

42

4]

100001

100010

100011

51
101001

~

61
110001

110000

JJ

011110

100000

50
101000

"

010111

35

011010

: :••

"

010100

JJ

011001

"

26
010110

52'
101010

011111

II···

4~

46

41

100101

100110

1110111

44

53
101011

56

~1

101100

101101

1111110

101111

~

~

~

110011

110100

65
110101

61
110111

~

110110

0

10
111000

FIGURE Sa .. MM4240ABU/MM5240ABU Tvpical
Address Inputs

.. . .. . . .
··.......: .......I .I:.... :: .:.''. i''.. ......: i:
·.
"
.. ........ ·..• .........
·
.
··......'.. ....···:••....I.·.... ..::::'.::
·.
·....' ...." ... " " ::. ·.•......
"
.... ..·..
.
:
.-i-•.
·Hi·
:·....
.
....
.
..
:
... :-.. .-:- ... .." .'"
· ..........
....
: : ..
:: ..
:: ..
: .....
...
.
...
!
:
!
:...
i.·.1
•••••
. ... . ... ....
·........._... i ..
...
· ......
. ·· .0:"
··"
..............: :...............
:
.
.
··:......: 1 :....
....
···:··i··
:
••.•.
'
•.
..
.. .:-., ..•.. .......... :
... ... :r.:: .•: : .....
:...::.....: :: .. . I .
..... :••:
:...: .... :: :: ·.1.·
"
-. • is·· ••• •
: • •••••
I·": i...: =....
L.. I .... i :..:;
ro

000 aGO

I

10

~

'000001

000 {J10

000011

13

14

15

0(11)10

001011

001100

001101

:

11

G01GnU

22

20

010QOO

:

010001

::

30
011000

:

31
011001

40
100000

.111
100001

~

~

00

OJ

{I0Dl00

ODD lilt

000110

000111

16
0011'0

1l

I
•• I .... :

0101110

I'

010011

I I ••••

010101

010110

011101

011110

:1

J/

3;!'

13

34

011011

011100

4J

100011

44
1011100

4~

100101

4&
100110

,

SO

010111

.1. . . . .

011010

42
100010

27

15

010100

0\1111

41
100111

• .1'

51

101000

h"

lHIOOO

1100111

001

52

1010111

~

liQUID

~

~

110011

110100

• e,

•••

~
1111101

"

110110

61

110111

e

10
11100II

11

1\1001

12
11t11.1f1

n

101

15

J6

1111111

1111flO

111101

111110

111111

FIGURE 6. MM424011ABZ/MM5240BABZ Horizontal·
Scan EBCDIC·S Graphic Subset

15

T111~O

111101

"

111110

111111

r··: :.... ..
I···: I···· r··· :.... '
·...........
... ... .

'

01

111001

14

FIGURE 5b. MM4240ABU/MM5240ABU Horizontal
Scan Hollerith Graphics Subset

••• : •••••! ... I ..•• : •••• : •••••••••

no

1J
111011

I···! i ...: :.... I•••: i .... i

:..:i

·i···!. ...·• ·....:... .. ...·· :·· ..:·.. ··•:
...·· - ·· ··,: ·" '1
.....
·
.
···'.'.....·.··...···: ...·I.·.'.····........·.......:• ·• ··...•...
.....···.•
"
"
"
.......... .-·•....:.- ..
.
..
..
··:.::-:.
.:1:.
:::::
••
:
II····!
.....
,.. . . ·
. .. .
..
..
··.............
· .: ..: .....':. ..: ....
· ..
... . . .. .
... ·:I::·.·:.·.:.··.
.-:. .....
·..•.•:..
......... ··1··.. .:.• ...
-:...
. .._...... . · .. . ··.'
••••• ••••• .s :•••••••••••:
·•...••...
.......! .!......: .....
··........ 1.:. :....•...
: 1.-1..
.
..: · :• :•
··.......
·.-..._." ..-._"..: ..:: ........
.:.:
..
• · ..··
·. •"_.· · "
00
0000(10

: :
10
001000

01

~

DIM 001

000010

11
001001

12
OLI1010

~

O~

~

000100

000101

000110

0011111

001101

001110

001111

ID

1J

14

001011

1101 100

~

Z,

U'I

~

»

3

.
~

(;'
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c.

m
c:

a

"0
~

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."

o

...

::s

(II

::s

...

en
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c.

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a.

(")

..=r
...
..

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n

~

,

:

I

I : : ·.1 :

24
010100

: I ••••

26

"

20
OIOOM

010001

610010

"

010011

]0
011000

31
011001

32
011010

u

~

35

•

31

011011

011100

011101

011110

011111

••

40
100000

4\
100001

51

~o

101000

110001]

•o

010110

010111

e.

42
100010

43

52

53

1010111

1111001

010101

•

44

45

46

41

100106

100101

100110

100111

56

57

54·· •• ~• •

101100

101101

101110

u

u

~

~

~

61

1111010

110011

1111100

110101

110110

110111

12

13
11\'011

111100

111101

111110

111111

.0
•

10

111000

11
111001

111010

15

77

FIGURE 7. MM4240ACA/MM5240ACA Horizontal·
Scan IBM EBCDIC Graphic Subset

m

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(/)

...
o

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...

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CD

... ... .... ... ... .............

VERTICAL SCAN FONTS

:... I..J I...:·: .: .: I... I... I .:
.::. : i i...: :.... i..·· i•••• ! :...!

All 'five of the standard vertical-scan subsets in
Figures 8 through 12 are generated with 6-bit
codes derived from code recommendations R646
of the International Organization for Standardization. These recommendations cover ASCII-7, European ECMA-7 and CCITT alphabet number 5 .

.. .... ...
·....... ....
::.*: :-.-::::::
:-.:
:-::-.:::.
.. . ...
· ..... ·... .. ... ............
.........
........
.
:
.
··............
..
. ............ ·-1···: .:: .....· .......
..
.
.
· .. .. . .... · ... · . .
: ....:.
. .:..
...-::.....
..................
...
:
..
:
...
· . . ...... . ....: :....: .: .....
.. .- . ..
: ·. :...........
.... -.:....
. ....- ·
·
.
·
.. :: " ..... . ..- .. :...
... ..... ....·
i-· ·.. ·..·
.. .~: ·:......:.:
."
...
...
....
...
·:.......····.......··· ·.·......·: ·....·····.........·· ··.......·· ·.........·.·....·.·
...•...·.·....."..• " .:·"·.. ..·" •.·..".:
·..." ·...··· · ··" ·,... " ..··•· ··
.........
...
i••• · ..•
·....•••.....· ·i......··: ..:.......:..·:...··.·....····..·.....•......
· ....:.
"
" ..
...·
• .·
......
.
..
·
.
···.....·· ...·· ....··• ··.....·····.......
·
...
......
• · ..... ·
• · · ·"· ·" · ·."...
·
....
·I···" ......
..:..
···............
... .......:..................... ··· ........::·· ..::.......:
.•••·....·· ·: ....·:- .
···.··: ·...: ··• ....
·
·· ·:•...··: .·...····•...·• ·• .....
· · ·.....
···· ....·..··.........··......•....•• ·...:..•.: ...
.. ::
·" ·" ·"
•.
..· ..·
······ ·····• :·1·:·· ..1:.=
00
aalluao

~

.s::.

(.)

'E

IU

"C

s:

...

IU

CIJ

s:

...s:
(/)

o

The ASCII subset for American use, in Figure 8,
is practically identical to the horizontal-scan subset.
Those in Figures 9 through 12 follow preferred
character styles in the countries indicated. The
underscore (character 37) is dropped below the
line so that it may be used as a cursor.

s:

Q.

e
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W

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s:

IU

s:

IU
CJ

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CD

E

«

oz

.

It)

z

«

000101

000110

000111

0\lloo0

001001

12
001010

001110

001111

001011

001 100

001101

i···: :...: i···: :...• "i··:

:: ::

20

21

22

~

2~

010001

010010

0100!'1

OHiIOO

010101

30
DIIDIlO

31

32

3J
011011

l4

35

011100

26

J6
011110

100010

100011

100100

1001111

100110

"

~

55

~

~7

101101

101110

101111

~

~

~

~

110010

110011

110101

"
110110

110111

"

111110

60
110000

61

1111 001

10
111000

71

12

111001

111010

·"

1111111

"

111100

111101

"

31
0110111

t1

24
010100

25

26
010110

n

21
010111

:

n

~

011011

011100

35
all UI1

~

1111110

J7
011111

::

IOltOIO

43
100011

52

53

!)4

55

Sli

101001

101010

101011

101100

IOII1}1

10111(1

101111

110001

110010

110100

nOl01

110110

110111

16

n

111100

111101

111110

!lllll

100001

44

4$
100101

46

41

100111

65

6J

111001

"

111010

111011

:

I I ••• • ••••• : •••
• 01
000010

000000

000001

.~.

~

001000

001001

nofOl0

01

OJ

000'011

000100

001011

001100

ODD 101

000110

000111

"

601110

001111

2~

26

001101

:

17

:::

~o

0101100

21
010001

22
0101110

3D
011000

24
010100

018101

J2
011010

3J
011011

34
011100

35
011101

42

•••••

100001

100010

100011

100100

100101

"

~

~

!)4

55

~

51

101010

101011

101100

101101

101110

101111

11

011001

0

100000

50

21
010 Iii

23
010011

:

100111

101 100

13

010011

on

J1

~

0111111

ECMA-7 Font for Scandinavian Use

011111

101011

16
001,110

FIGURE 9. MM4241ABV/MM5241ABV Vertical Scan

21
010111

u

22

010010

n

!

101010

101001

21

010001

111000

o·

50

101000

15
001101

0

.· .· ··....".........". . ·" ·" ..." ·
···. .· . ..·
·.
:..:: .-! ••.•: •••:. .·1 :... •••.••••::
··...
.....
.......
. .....
......
..
.........
.... .......
. ....,...
.......
··-H.·.......• ....•......•.:. · · ·····.... ..... ....······...·•.·
..
IOnnOI

14
0011011

:: ::

60

40

100000

1]

001011

10

110000

..... ....... ..... ..
...
••••: ... :
··..·..: :.......I ......
... ··I... ··.· ...··: ·...···: ......
..... .·.
···...· ...........··....•...
··.. ....
·:::• ··.. .......
.....
· ··..·.
010000

12
DOl 010

OIODUU

101000

:... :.::-:..... : : ::: I::
:
:
:: :
n

:

01
DOOlti

:

17

15

06
000110

Q5

:

50

07

000 100

000101

:

'

.~.

.....

000 010

04
1100100

:

100000

...:·i i•••...! i........: .i...· !...·,1.....
.....
.....•
...
I
...
I
·:•••....
·'" :..." ••: :.........•••• I•••..•·.z••••" ·: " · ••...•••1•
......
• ·
.·....
........
·.. •••'......·:•
···.....··:•• ·:• ·..···• ···..• ..····.··......
• :• ..·
...
.
"
" "
000001

OJ

OOOOtl

:

With standard programming, the bits in the column
outputs are sequenced for a sawtooth scan with
dot columns running in the same direction, as
illustrated in Figure 13a. For a pedestal scan,
Figure 13b, alternate columns can be .reversed
by putting an 8-bit shift left/shift right TTL
shift register (DM74198) on the output as illustrated in Figure 14.

000000

11
0(11001

W
011 000

Vertical-scan character generators are generally
used in dot-matrix tape printers, ink-dot spray
printers and high-definition sawtooth or pedestalscan CRT displays. They may also be used to
control raster-scan TV tubes or CRTs if the tube
is turned on its side so that the raster scan is made
vertically to provide a page-like format.

OJ
DOD 011

=:

10
001000

02
OOODlil

::

U-

IU
CD

:: ::

:

CJ

IU

01
000001

J6
011110

J1

011111

•• 0

46

100110

41
100111

......: ..... ..... .:: :....
.........:
: ..:.:. ........
........
:....
...
.
.....
.
• •••• ..I •• :.... •••••
: ••••• ••••• :
101000

101001

.. ..... .........
.:
·
:......
: ..
.=· ... ....
"

.........: .
·.........
~

61

110000

11

61
110 001

~

~

~

~

110010

110011

110100

110101

"
110110

111100

15
111101

J6
111110

111

11

12

Il

111000

111001

111010

111011

61

FIGURE 10, MM4241ABW/MM5241ABW Vertical-Scan
ECMA-7 Font for German Use

FIGURE 8. MM4241ABLlMM5241ABL Vertical-Scan
ASCII-7 Graphic Subset

11·24

»
z

.... ... ... .............
:...
... I...
...! i•••:! . I .: i... i... ! ..

...e.:
...........
: ...
:...
...
. ............
.. .:..................::......•...
.: ..

.. . ...........
.. ..
....
... ..... . ..
....
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For example, the extra height may be used in an
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semicolons and lower-case letters below the bottom
line of the capital letters. Fonts as large as 16 x 12
are entirely practical without additional control
logic, using the chip-enable feature of four
MM5241s. Large-font Qrganizations are discussed in
AN-40.

CUSTOM FONTS
The two ROMs can also be custom-programmed
to provide special characters, or fonts larger than
5 x 7. The MM4240/MM5240 actually stores 64
5 x 8 characters or character segments and the
MM4241/MM5241 stores 64 8 x 6 characters or
segments. They are not limited to 5 x 7 and 7 x 5.

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App Notes/Briefs

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NAnoNAL

APPLYING MODERN CLOCK
DRIVERS TO MOS MEMORIES
INTRODUCTION

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MOS memories present unique system and circuit
challenges to the engineer since they require precise
tim ing of input wave forms. Since these inputs present
large capacitive loads to drive circuits, it is often that
timing problems are not discovered until an entire
system is constructed. This paper covers the practical
aspects of using modern clock drivers in MOS memory
systems. Information includes selection of packages and
heat sinks, power dissipation, rise and fall time considerations, power supply d"ecoupling, system clock line
ringing and crosstalk, input coupling techniques, and
example calculations. Applications covered include
driving various types shift registers and RAM's (Random
Access Memories) using logical control as well as other
techniques to assure correct non·overlap of timing waveforms.

The OS0026 is a high speed, low cost, monolithic clock
driver intended for applications above one megacycle.
Table II illustrates its performance characteristics while
its unique circuit design is presented in Appendix II.
The OS0056 is a variation of the OS0026 circuit which
allows the system designer to modify the output per·
formance of the circuit. The OS0056 can be connected
(using a second power supply) to increase the positive
output voltage level and reduce the effect of cross
coupling capacitance between the clock lines in the
system. Of course the above are just examples of the
many different types that are commercially available.
Other National Semiconductor MaS interface circuits
are listed in Appendix III.
The following section will hopefully allow the design
engineer to select and apply the best circuit to his parti·
cular application while avoiding common system pro·
blems.

Although ·the information given is generally applicable
to any type of driver, monolithic integrated circuit
drivers, the OS0025, OS0026 and OS0056 are selected
as examples because of their low cost.

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PRACTICAL ASPECTS OF USING
MOS CLOCK DRIVERS

The OS0025. was the first monolithic clock driver.
It is intended for applications up to one megacycle
where low cost is.of prime concern. Table I illustrates
its performance while Appendix I describes its circuit
operation. Its monolithic, rather than hybrid or module
construction, was made possible by a new high voltagegold doped process utilizing a collector sinker to mini·
mize VCESAT.

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VI

Package and Heat Sink Selection
Package tYpe should be selected on power handling
capability. standard size, ease of handling, availabilitY
of sockets, ease or type of heat sinking required, relia·
bilitY and cost. Power handling capability for various
packages is illustrated in Table III. The following guide·
lines are recommended:

TABLE I. OS0025 CharacteristicS
PARAMETER

CONDITIONS IV+ - V-I ~ 17V

tON
tOFF

t,

C'N ~ O.OO22~F.

~

ns

25

ns

150

ns

~1mA

V+-O.7

V

I,

OV, lOUT =

ns

50n

Positive Output Voltage Swing

VIN .- V-

Negative Output Voltage Swing

liN = 10mA.louT::: lmA

On Supply Current (V+)

II~

=

UNITS

15
30

RIN =

C L ~ O.OOOlMF, RO

on

VALUE

=- lOmA

V- + 10

V

17

mA

TABLE II. OS0026 Characteristics
PARAMETER

CONDITIONS IV+ - V-I ~ 17V

tON
tOFF

C'N

I,

RO

~ O.OOlIlF. RIN
~

5m2. C L

~

=- OH

1000 pF

I,

Positive Output Voltage Swing

VIN - V-

Negative Output Voltage Swing

liN

On Supply Current (V+j

liN = 10 mA

=

=

OV,

'tOUT =

-lmA

1OmA, IOVT '" 1 mA

11-27

VALUE

UNITS

7.5

ns

7.5

ns

25
25

ns
os

v+ - 0.7

V

V- + 0.5

V

28

mA

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The TO·5 ("H,;') package is ~ated at 750 mW still air
(derate at 200 C/W above 25 C) soldered to PC board.
This popular cavity package is recommended for small
systems. Low cost (about 10 cents) clip·on heat sink
increases driving capability by 50%.

where:
v+ - V- = Total voltage across the driver
Req

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= Equivalent device resistance in the

"ON" state

The 8·pin ("N") molded mini·DIP is rated at 600 mW
still air (derate at 90°C/W above 25°C) soldered to PC
board (derate at 1.39W). Constructed with a sl?e'cial cop'
per lead frame, th is package is recommended for
medium size commercial systems particularly where
automatic insertion is used. (Please note for prototype
work', that this package is only rated at 600 mW when
mounted in a socket and not one watt until it is soldered
down.)

(3)

DC

= Duty Cycle

"ON" Time

=-----------------"ON" Time + "OFF" Time

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For the DS0025, Req is typically 1 kn while Req is
typically 600n for the DS0026. Graphical solutions for
Poc appear in Figure 1. For example if V+ = +5V,
V- = -12V, Req = 500 n, arid DC = 25%, then Poe =
145 mW. However, if the duty cycle was only 5%,
Poe = 29 mW. Thus to maximize the number of regis·
ters that can be driven by a given clock driver as well as
minimizing average system power, the minimum allow·
able clock pulse width should be used for the particular
type of MOS register.

To TO·8 ("G") package is rated at 1.5W still air (derate
at 100°C/W above 25°C) and 2.3W with clip·on heat
sink (Wakefield type 215·1.9 or equivalent·derate at
15 mWfC). Selected for its power handling capability
and moderate cost, this hermetic package will drive very
large systems at the lowest cost per bit.
Additional information is given in the section of this
data book on Maximum Power Dissipation (page 2).
Power Dissipation Considerations

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The amount of registers that can be driven by a given
clock driver is usually limited first by internal power
dissipation. There are four factors:
1. Package and heat sink selection
2. Average dc power, Poc
3. Average ac power, PAC
4. Numbers of drivers per package, n
From the package heat sink, and maximum ambient
temperature one can determine PMAX , which is the
maximum internal power a device can handle and still
operate reliably. The total average power dissipated in a
driver is the sum of de power and ac power in each
driver times the number of drivers. The total' of which
must be less than the package power rating.

DUTY C'YCLE 1%)

FIGURE 1. POC vs Duty Cycle

(1 )

In addition to Poe, the power driving a capacitive load
is given approximately by:
Average dc power has three components: input power,
power in the "OFF" state (MaS logic "0") and power
in the "ON" state (MaS logic "1").
(4)

where:

(2)

f
For most types of clock drivers, the first two terms are
negligible (less than 10 mW) and may be ignored.
Thus:
Poc

== PON =

Graphical solutions for PAC are illustrated inFigure 2.
Thus, any type of clock driver will dissipate internally
290 mW per MHz per thousand pF of load. At 5 MHz,
this would be 1.5W for a 1000 pF load. For long shift
register applications, the driver with the highest package
power rating will drive the largest number of bits.

(v+ - V-)2
Req

= Operating frequency

C L = Load capacitance

x (DC)

11·28

fW

Combining equations (11. (2). (3) and (4) yields a criterion for the maximum load capacitance which can be
driven by a given driver:

LlT
Logic rise and fal-l times must be known in order to
assure non-overlap of system timing.

500

•
i zoo

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CL =2nF

400

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300

0

100

f-

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Note the definition of rise and fall times in this application note follow the convention that rise time is the
transition from logic "0" to logic "1" levels and vice
versa for fall times. Since MaS logic is inverted from
normal TTL, "rise time" as used in this note is "Voltage
fall". and "fall time" is "voltage rise." .

p.-

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Power Supply Oecoupling

V+-V-=17V

1.0

1.5

2.0

2.S

PULSE REPETITION FREQUENCY (MH.)

FIGURE 2. PAC

VI

PRF

_ (DC)]
Req

. (5)

As an example, the OS0025CN can dissipate 890 mW at
T A = 70°C when soldered to a printed circuit board.
Req is approximately equal to lk. For V+ = 5V, V- =
-12V, f = 1 MHz, and dc = 20%, C L is:

106
CL

S

[

n

Although power supply decoupling is a wide spread and
accepted practice, the question often arises as to how
much and how· often. Our own experience indicates
that each clock drive~ sl)ol.lld have at least O.lpF decoupling to ground at the V+ and V- supply leads.
Capac·itors should be located as close as is physically
possible to each driver. Capacitors should be non-inductive ceramic discs. This decoupling .is necessary because
currents in the order of 0.5 to 1.5 amperes flow during
logic transitions.
There is a high current transient (as high as 1.5A)
during the output transition from high to low through
the V- lead. If the external interconnecting wire from
the driving circuit to the V- lead is electrically long, or
has . significant dc resistance the current transient will
appear as negative feedback and subtract from the
switching response. To minimize this effect, short interconnecting wires are necessary and high· frequency
power supply decoupling capacitors are required if V- is
different from the ground of the driving circuit.

(890 x 10-3 )
0.2]
(2)(17)2
-lxl03

Clock Line Overshoot and Cross Tal"

1340 pF (each driver)

Overshoot: The output waveform of a· clock driver can,
and often does, overshoot. It is particularly evident on
faster drivers. The overshoot is due to the finite inductance of the clock lines. Since most MaS registers require
that clock signals not exceed Vss , some l11ethod must be
found in large systems to eliminate overshoot. A straightforward approach is shown in Figure 3_ In this instance,

A typical application· might involve driving an MM5013
triple 64-bit shift register with the 050025. Using the
conditions above and· the clock line capacitance of the
MM5013 of 60 pF, a single OS0025 can drive 1340 pF/
60 pF, or 00 MM5013's.
In summary, the maximum capacitive ·Ioad that any
clock driver can drive is determined by package type and
rating, heat sink technique, maximum sys~m ambient
temperature, ac power (which depends on frequency,
voltage across the device, and capacitive load) and dc
power (which is principally determined by duty cycle).
Rise and Fall Time Considerations
In general rise and fall times are determined by (a) clock
driver design, (b) reflected effects of heavy external
load, and (C) peak transient current available. Details of
these are included in Appendixes I and II. Figures A 1-3,
A14, AII-2 and A/Il-~· illustrate performance under
various operating conditions. Under 'Iight loads, performance· is determined by internal design of the driver;
for moderate loads, by load CL being reflected (usually
as CLIP) into the driver, and for large loads by peak
output current where:

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FIGURE 3. Use of Damping Resistor to Eliminate
Clock Overshoot

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a small damping resistor is inserted between the output
of the clock driver and the load. The critical value for
Rs is given by:

+5V

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In practice, analytical determination of the value for

I

Rs is rather difficult. However, Rs is readily deter·

mined empirically, and typical values range in value
between 10 and 5on.

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FIGURE 5, ClOck Line Cross Talk

The negative going transition of!fl, (to MOS logic "1")
is capacitively coupled via C M to 
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(6)

o

One last word of caution with regard to use of a damp·
ing resistor should be mentioned. The power dissipated
in Rs can approach (V+ - V-)2fC L and accordingly
the resistor wattage rating may be in excess of lW.
There are, obviously, applications vvhere degradation of
tr and tf by use of damping resistors cannot be tolerated .
Figure 4 shows a practical circuit which will limit over·
shoot to a diode drop. The clamp network should·
physically be located in the center of the distributed
load in order to minimize inductance between' the
clamp and registers.

The OS0056 connected as shown in Figure 6 will mini·
mize the effect of cross talk. The external resistorS to
the higher power supply pull the base of a 01 up to a
higher level and forward bias the collector base junction
of 01. In this bias condition the output impedance of
the 050056 is very low and will reduce the amplitude
of the spikes.
+5V +BV +8V

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FIGURE 6. U... of 080056 to Minimize
Clock Line Cross Talk
.

-12V

Input Capacitive Coupling

FIGURE 4. Use of High Speed Clamp to Limit
Clock Overshoot

Generally, MOS shift registers are powered from +5V
and -12V supplies. A level shift from the TtL levels
(+5V) to M05 levels (-12V)is therefore required. The.
level shift could be made utilizing a PNP transistor or
zener diode. The disadvantage to de level shifting is the
increased power dissipation and propagation delay in the
level shifting device. Both the OS0025, 050026 and
050056 utilize input capacitors when level shifting from

Cross Talk: Voltage spikes from , may be transmitted
to 

.s CL

(50 mAl (20)

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050025 Input Drive Requirements

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If DC eperaticn to. a negative level is desired, a level
translater such as the OS7800 cr OS0034 may be
empleyed as shewn in Figure AI-9. Finally, the level
shift may be accemplished using PNP transisters are
shewn in Figure AI- 10.

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900

The OS0025 may be direct-ceupled in applicatiens
when level shifting to. a pesitive value enly. Fer example, the MM1103 RAM typically eperates between
greund and +20V. The OS0025 is shewn in Figure
AI-8 driving the addres er precharge line in the legically
centreiled mede.

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FIGURE AI-7. Output PW Controlled by CIN

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FIGURE AI-8. DC Coupled DS0025 Driving 1103 RAM

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FIGURE AI-g. DC Coupled Clock Driver Using DS0034

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FIGURE AI-l0. Transistor Coupled DS0025 Clock Driver

11-33

ill

APPENDIX"

Rise Time Considerations

050026 Circuit Operation

Predicting the MOS logic rise time (voltage fall) of the
OS0026 is considerably involved, but a reasonable
approximation may be made by utilizing equation
(AI-5), which reduces to:

The schematic of the OS0026 is shown in Figure AII-t.
The device is typically ac coupled on the input and
responds to input current as does the OS0025. Inter·
nal current gain allows the device to be driven by stan·
dard TTL gates and flip-flops.

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(AII-1)
For CL ~ 1000 pF, V+ ~ 5.0V, V- ~ -12V; t, == 21 ns.
Figure AII-2 shows OS0026 rise times vs C L •

With the TTL input in the low state 01, 02, OS, 06 and
07 are "OFF" allowing 03 and 04 to come "ON." R6
assures that the output will pull up to within a VBE of
V+ volts: When the TTL input starts toward logic "1,"
current is supplied via CIN to the bases of 01 and 02
turning them "ON." Simultaneously, Q3 and 04 are
snapped "OFF." As the input voltage rises (to about
1.2V), OS and 06 turn-on. Multiple emitter transistor
OS provides additional base drive to 01 and 02 assuring their complete and rapid turn-on. Since Q3 and
04 were rapidly turned "OFF" minimal power supply
current spiking will occur when 07 comes "ON."

25

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I0Il 1000 1200

LOAD CAPACITANCE CpF)
EXTERNAL

06

c,•

T

0'

INPUT

01

CD

~

01

:.;,

08

.....,

D.

'!
...Q1

~

~B

*

....0.
02

03

'"'-.~

D.!
10k

I

DB

0],
0'

O.

The MOS logic fall time of the DS0026 is determined
primarily by the capacitance Miller capacitance of 05
and 01 and RS. The fall time may be predicted by:

..... ~OU

(AII-2)

TPUT

06

....

>---

Fall Time Considerations
~D'

....

;;;

Z

c(

FIGURE AII-2. Rise Time vs Load Capacitance

to..

.."

....

where:

....0.

DID

01

Cs· ~ Capacitance to ground seen at the base of O~

l'

hFE2

~

2 pF

~

(hFEQ3

+ 1) (hFEQ4 + 1)

== SOO

FIGURE AII-1. OS0025 Schematic (One-Half Circuit)

For the values given and CL = 1000 p F, tf
Figure AII-3 gives tf for various values of C L •

06 now provides sufficient base drive to 07 to turn it
"ON," The load capacitance is then rapidly discharged
toward V-. Diode 04 affords a low impedance path to
06's collector which provides additional drive to the
load through current gain of 07. Diodes 01 and 02 prevent avalanching 03's and 04's base-emitter junction as
the collectors of Oland 02 go negative. The output of
the DS0026 continues negative stopping about O.SV
more positive than V-.

==

25

.
il

V'-V"·15V,.2OV
20

z

.... ~

I

!

...~
~
~

When the TTL input retLJrns to logic "0," the input
voltage to the DS0026 goes negative by an amount
proportional to the ·charge on CIN' Transistors 08 and
09. turn-on, pulling stored base charge out of 07 and 02
assuring their rapid turn-off. With 01, 02, 06 and 07
"OFF," Darlington connected 03 and 04 turn-on and
rapidly charge the load to within a V BE of V+.

::!:

15

........

V

10

Ro .. sOn

/
5

TA ",25"C

V
o

200

400

&00

BOO

1000

LOAO CAPACITANCE CpF)

·FIGURE AII-3. Fall Time vs Load Capacilanc~

11-34

17.S ns.

DS0026 Input Drive Requirements

5.0

The DS0026 was designed to be driven by standard
54/74 elements. The device's input characteristics are
shown in Figure AII·4. There is breakpoint at V IN ==
0.6V which corresponds to turn·on of 01 and 02. The
input current then rises with a slope of about 600n
(R2 II R3) until a second breakpoint at approximately
1.2V is encountered, corresponding to the turn·on of 05
and 06. The slope at this point is about 150n (R 1 II
R2 II R3 II R4).

4.0

~

"15

>

3.0

2.0

1.0

10

30

20

s:o

..

40

0..

16
TA -2S0C

I'
;;;

.s...
z

::l

FIGURE AII-5. Logical "1" Output Voltage
vs Source Current

V-"DV

12

CD

lOUT (rnA)

v· '" zov

(")

10

~

/

B

~
;;

1-1- r-- C .

o

V

IL

In actual practice it's a good idea to use values of about
twice those predicted by equation (AII·4) in order to
account for manufacturing tolerances in the gate, DS0026
and temperature variations.

-I-

.... i-'
o

0.5

1.0

1.5

INPUT VOLTAGE

2.0

A plot of optimum value for G'N vs desired output pulse
width is shown in Figure A 11-6.

2.5

IVI

J 2400

v+ -V-"'2DV

~- 2200

CL

5

1800
:;: 1600
j 1400

=

V
L

~ 1000
~ 800

~

600

_

400

;

200

'"
~

Input Capacitor Selection

L

0

t- I-0

V

tl

~

I MAX
ROG IN In - IMIN

.

3

D~~~ID~~-

o

(ii'

..,.r::

VJ

f-"""TRANSISTOR _
WITH 50 OHMS
TO +5V DRIVING 050026-

~

100 200 300 400 .500 600 100 800

FIGURE AIt~6. Suggested Input Capacitance
vs Output Pulse Width

DC Coupled Applications
The DS0026 may be applied in direct coupled applica·
tions. Figure AII-7 shows the device driving address or
pre·charge lines on an MM1103 RAM.

(AII·3)

or
+11V

(AII·4)

GIN

ROln

100pf

IMAX
IMIN

In this case RO equals the sum of the TTL gate output
impedance plus the input impedance of the DS0026
(about 150n). IMIN from Figure AII·5 is about 1 mAo
A standard 54/74 series gate has a high state output
impedance of about 150n in the logic" 1" state and an
output (short circuit) current of about 20 mA into 1.2V.
For an output pulse width of 500 ns,
500 x 10- 9
--------20mA
(150n + 150n)ln
1 mA

~

100 pF
DS0026CN

1

TO ADDRESS
LINES ON
MEMORY
SYSTEM

1/20M'1400

560 pF
FIGURE AII·7. DC Coupled RAM Memory Address or
Precharge Driver (Positive Supply Only)

11·35

...o
CD

foM74S00-

OUTPUT PULSE WIDTH (ns)

A major difference between the DS0025 and DS0026 is
that the DS0026 requires that the output pulse width
be logically controlled. In short, the input pulse width ==
output pulse width. Selection of GIN boils down to
choosing a capacitor small enough to assure the capaCitor
takes on nearly full charge, but large enough so that the
input current does not drop below a minimum level to
keep the DS0026 "ON." As before:

~.

VJ

s:

loon pF

~ 1200

.
..

C/)

L

TA"'25"C

~ 2000

~

o

s:o

FIGURE AII·4. Input Current vs Input Voltage

The current demanded by the input is in the 5-10 mA
region. A standard 54/74 gate can source currents in
excess of 20 mA into 1.2V. Obviously, the minimum
"1" output voltage of 2.5V under these conditions can·
not be maintained. This means that a 54/74 element
must be dedicated to driving 1/2 of a DS0026. As far as
the DS0026 is concerned, the current is the determining
turn·on mechanism not the voltage output level of the
54/74 gate.

0"
C')

In

Q)

'':::

o

E
Q)
::!:

For applications requiring a dc level shift, the circuit of
Figure AII-8 or A 11-9 are recommended.
+s.ov

en

o

Quad decoded MOS clock driver.

OS1674

Quad MOS clock driver.

OS75361

Dual TTL·to·MOS driver.

OS75365

Quad TTL·to·MOS driver.

MOS Oscillator/Clock Drivers

::!:

OS7803/0S7807,
OS7813/0S7817

7 ¢10UTPUT

....o

...

OS1673

In
Q)

>
';:

02
INPUT 9

5 92 OUTPUT

MOS RAM Memory Address and Precharge Drivers

C

O.l/-lF

.::I.

(J

o

(j

...

I:

-12V

~

Dual address and precharge driver.

OS0026

Dual high speed address and pre·
charge driver.

TTL to MOS Interface

Q)

::!:

OS0025

FIGURE AII-S. Transistor Coupled MOS Clock Driver

"C

o

Complete two phase clock system
for MOS microprocessors and cal·
culators.

TTL

,NPUTS

{

0 - -.....- ,

OH0034

Dual high speed TTL to negative
level converter.

OS7800

Dual TTL to negative level con·
verter.

C)

I:

OM7810/0M7812/ Open collector TTL to positive
OM7819
high level MOS converter gates.

>
C.
Q.

I


ca

Q.
I/)

is
><

''::

.-ca
::!
.

~

o

c:

o

'.j:i

.:o
I/)

CI)

a:
I

.s::.

,!?
:I:

,S:
I/)

::!
a
a:
C)

c:
'SO
ca
en

....: .-. -i·: I···· -i··: i··.. reM I·..·

·-: :' i...i :....

·.1.· I
011
000000

.: ...:..

: .102••• • ••••
.104••• I....
I
OJ
05

01
000001

.:.

000010

000011

000 Ion

000101

06
000110

interface terminals (although some terminal manufacturers are going to larger sizes in response to
complaints that 5 x 7 presentations Ci3use eyestrain)_ In other applications, a standard is often
set by older printing techniques. To cite a few
examples: business-machine users are accustomed
to typewriting; advertisers want characters with
"sales appeal" on their billboard displays; scor.eboards and traffic-control signs must be read
easily at a distance; and electronic printing systems
may have to simulate several metal type fonts_

-:

••••
1
01
000111

i i.··· i 1-:-11-·.1 r'

: . . . 1:
··....I"·!.! ....:.· .....::e.:
·....• • ·•
• ·
• ·
·! ·...•....··.....·• ........'.· ......
·
•
·
·... ."·• ·...... · r··!
·
"
·
.....
...• •
·•·•·.•·..• .··•.·.....•·.' ·:...•• •·•·• ...I -;-+-·'" • ·• ·• • ·. • ·•• ."·· ••."
···•• :: •• . ...· ·....·..·.......
· ·....... · .· . •
••· ··• ::i:: ··1··
.....
·..• ·· ... "·· ·• " ·•··
··•..·· ...··:.•• ··_.··..-••·• :• ·....•..........
·.- •·•
... ... " " " ...." .". ·••"
:...: :....! :: ••..•••• '.•·• ......
·
10
001000

••••

:
"

001001

DOl 010

1)

• ••••••
14

001011

001'0(1

:: 16 I •••
1
17

15
0011(11

010001

22
010010

001110

001111

:: :: :
: '.'

I -.- I e.
11

010000

•••
•
12

"

"

010011

010101

"

010110

"

0111T11

:

1I

011000

l2

011001

3J
011011

l4

011100

J5
011101

011110

011111

.: : •••••••••• I I

40
1110000

•• ••••

"

100001

I

100010

4l
100011

101000

"

"

110000

"

110 DOl

... ..
11

1\1001

100110

101011

II
50

101101

110010

110011

1101011

101110

•••••
110101

110110

12
111010

·• "·· " .'·

1J
111011

111100

4 ••••

~:

101111

.....
.....
....... ... .: .:......!:.
·i:
:. ···.....
..
..
..
... ·····i. .....; .:.....i · ..
..
,,,

111101

•

111111

~

5 6 7

'231667

,

6 •••••

~

I

111110

1 2 3

,

110111

I

.234512l45

,

"
•••••

76

12345

,

:

'

::

......···........... ..... ......
'.'....... .:... .····1
. ...: ::.: ::

"

100111

II···.

• I ••:.
I .........

: :
70
111000

101010

54
101100

.":

:

I

52

II

45

100101

n

I

50

100100

:

The matrix size is frequently enlarged to improve
lower-case character definition in UCILC applications. A 5 x 7 font typically grows to 7 x 9 for UC
and 7 x 12 for LC, as in Figure 2_ Likewise, 7 x 9
is expanded to 8 x 12 and 12 x 16 to 12 x 24 for
lower-cases .

FIGURE 2. UC/LC Characters at 5 x 7 and 7 x 12
Matrix Sizes

17

·I

(AI Upper-Case Font

. ...
.
.
···i
1-:·1
I;·;;
:!.!I
·.... ..... ..... ..... ... .
...... ......
.... ....
:...: :...: .. ..
: ·..
........·..
..
..
..
.
. ·..'...
...
.....
....
••••••• : ••1•• •• ::: ·
·.."
·
.
.
.
.
.
.
.
..
...
...
..
..
..
...
.
:.. : : ••: I·.·:, : : : :.:.:.
·:..•••·..: :...:.:..:.:_...: ...............
.... .... ... .... ....
:..•••..: ,I·:·:
:.:.: :.:.: :...:_.:-_.:.
. .. .:.:.:
. ..:•••:........
·........................................
.............................
:..:::::::::: II I::::::
:
: ... .........
..: :...
.... :....::.
.
.:
·'. ·:....
- I:
••••: •••••:
. ........... ..
.... ...... ..,..
"
.:.: .i····
GO
000000

"
000001

~

ro

~

~

~

~

DOG 010

000011

1HI0100

000101

000110

000111

10
001000

11
001001

12
0011no

13
001011

14
001100

15
0011111

16
001 liD

20
010000

21
010001

n

n

~

~

~

27

010010

1110011

010100

010101

010110

010111

»

31
011001

n

n

~

~

~

31

011010

011011

011100

011101

011110

011111

41
100001

42
100010

41
100011

44
100100

45
100101

46
100110

47
100111

,56
101110

51
101111

At 5 x 7, it is most economical, as a rule, iopro'
gram a "full set" of 128 UC!LC characters in
standard character·generator ROMs_ The full set
in Figure 1 is stored in two 64·character MaS
ROMs. This provides a mass-production base and
equalizes access times. If the 32 special symbols
generated with the ASCII control codes are not
usable, they are simply blanked by disenabling
the lower-case ROM when .the seventh ASCII bit
is "0_" But if the font is scaled up to simulate
typewriting, for example, this practice becomes
wasteful since 96 characters would suffice.
Another complication is that many special ized font
sizes, such as 11 x 9, do not fit neatly into standard
ROMs made in building block sizes. In other
words, one cannot store the font in a minimumsized ROM array without paying the extra costs
of custom ROM development or specialized lowvolumn ROMs.

· ··:.: .·· ···• ·..... ·:....·......·.
·
·
·· "·· ...·· · · · ...
"
...
...
.. .. .
.:.. :: :: :
....
..... ....
·:....::...::'.. .............
.
.
.... ..........
. ...
...·
.....· •·· ·: ··. ...···.....
·
..
···.'.····.·.......·:: .....
·
· ·· · ·· " • ·
" " ·
100000

··..:: ....: ·•'.'
"
101011Q

101001

52

101010

55

101011

101100

:

101101

CHARACTER-GENERATOR ROMs

Consequently, character-generator ROMs have been
developed that adapt to a variety of font sizes.
They may not exactly fit the theoretical matrix
array at odd sizes. but that is easily offset by
the economy of parts standardization.

:

00

61
110001

~

~

~

~

~

110000

110010

110011

110100

110101

IlOilO

61
110111

111001

12
111010

13

111000

74
111100

15
111101

"'-;110

11
111111

Two such MaS ROMs are outlined in Fi,gure 3
with their addressing for 5 x 7 horizontal scanning
and 7 x 5 vertical scanning. The vertical-scan subsystem in Figure 4 shows the amount of support
logic typically required in a display.

I

(8) lower-Case Font

FIGURE 1. ASCII Full Set Font of 128 5 x 7 Characters

11-38

»
2

rr'

}~" .......
....
...:

A,

CHARACTER
CODE

A)
A.

A,

0

A.

..W

ADDRESS

Roll.

..W

CHARACTER
CODE

AJ
A•

000011

DUTPUTS

A•

COLUMN
ADDRESS

SCAN

{''

...

010101

A,

ADDRESS

USE 2 ROMs AND,
APPLY Ar TO CE
FOR 128 CHARACTERs

'"

r

COLUMN ADDRESS

A,

• ••••

1

•••

~

:

OUTPUTS

~

en

'I»

<

:i'

CQ

CA~

C"

USf 2 ROM. ANO
APf"LY A, TO CE
FOR 128 CHARACTERS

SCAN

r

IBI 7 x 5 Vertical-Scan, 64-Characters

IAI 5 x 7 Horizontal-Scan, 64-Characters

m
UI

FIGUR'E 3. MM5240 and MM5241 Standard Character·Generator ROMs

:IJ

o

~
(II

:i'
:::t
c·
':3"
I

:IJ
CD

CHARACTER
GENERATOR

-------

Z AXIS

MOO

cS'
:::I

---- .-------,

INPUT
• CHARACTER
DATA

~
C.....

OUTPUT REGISTER

C

o....
I

s:

.

!

)c'

,....-------+-+--o

:::~~~El

C

iii'

~

LINE
COUNTER

LINE

COLUMN

DOT/COLUMN

DIVIDER

COUNTER

DIVIDER

FIGURE 4. Typical 7 x 5 Vertical..scan Display Generator Subsystem

iii
<(II

!c..

.

~

The MM5240 expands straightforwardly in 64·
character increments to larger fonts, such as the
9 x 7 or lOx 8 arrays in Figure 5A. An expansion
such as Figure 58 would be used to provide a full
set UC/LC font. These expansions keep the
character rate the same as at 5 x 7, whereas
docbling the size of each monolithic ROM would
not.

However, the chief attraction of this conversion is
in UC/LC applications. Figure 7 shows how to
use three ROMs to generate 96 7 x 9 to 8 x 12
horizontal·scan characters-a 25% savi.ngs compared
with a "full set" expansion. The chip·enable inputs
are programmed to sense the sixth and seventh
character-ad.dress bits. External decoders aren't
needed.

32·CHARACTER BLOCKS

If each ROM in Figure 7 is replaced with a paraliel
assembly of three ROMs (24 outputs). the result
is a 24 x 12, 96-character vertical-scan generator
with the same character rate as at 8 x 12. In other
words, the 32·character approach ma inta ins the
benefits of parts standardization and. performance
up to a very high resolution.·

A similar expansion of the MM5241, as in Figure
6A, would provide 7 x 9 to 8 x 12 horizontal·scan
fonts. However, the direct 64·character expa(lsion
places a ROM·enabling operation"in the middle of
the character. Such operations are common in
large-font generator designs.

Other ROMs can be used in this fashion. In Figure
8, the MM5227 TRI·ST ATE® and MM528B 256 x
12 ROMs are shown in expansions that complement those of the MM5241. These ROMs provide
access ti mes well under a microsecond. For rates
in the nanosecond range, general·purpose bipolar
ROMs with four or eight outputs, such as the
DM8597 256 x 4 and DM8596 512 x 8 can be
worked into similar organizations.

A simple solution to this problem is to "steal"
a character·address input, use it as a row·address
input, and then use a chip·enable input as a
character input (Figure 6B). This provides a 32character or 64,charact.er block enabled during the
between·characters spacing interval. A 32·character
block would be. the only ROM required in a
system using only numbers and symbols.

11·39

:i'

i

iil

iD
I

f

Sc

'j;

A.

.,-A.,

"CI

C

'"
~

(II

OUTPUT

......

Q

><

A,o-!-++-_ _....J

COLUMN

Q.
,!!

PIS

A,-As

REGISTER

'C:

~

::IE

t

Q

c
o

'+i

:J

~G)

SP'"

·.•: e.::..3
·· ...
::~!~~~:

m:
.s:.•

••
•

,~

:::E:

,5

07JCDLUMN
ADDRESS

010 , • •

•

,

•

z

•

4

RDM
OUTPUTS

,

SPAtE

10

"

(AI 9 x 7 or 10 x 8 Vertical-Scan, 64-Charactars

III

::IE

om:

tI)

c

'S;

'"

(BI 9 x 7 or 10 x 8 Vertical-Scan, 128-Characters

en
an

FIGURE 5. Expansion of MM5240 to Larger Fonts

00I
Z

<

Designs proportioned to the matrix size are not
the, most efficient at the larger font sizes. It pays
to analyze the actual character patterns to deter·
mine whether other organizations can be used.

Theoretically, they couJd all have been unique,
since'there is a possible pattern variation ranging
from 128 to 65,536 (2 7 to 2 16 ). UC/LC and
horizontal·scan fonts are more variable than upper·
case vertical·scan fonts, but they are still far from
worst·case.

For example, thfHull-dot columns in such vertical·
'scan characters as b, 8, d, D, H, T, etc., are
usually identical. An upper·case font typically
contains only 60 unique column patterns at 7 x 5,
110 at 9 x 7, 120 at 11 x 9, and 122 at 16 x 12.

This analysis led to the organization in Figure 9A.
Instead of doubling the 64 x 12 x 8 organization to
produce fonts up to 16 x 12, it adds only a 2k

.~

1ii

:!

PARALLEL

~
Q

lOSERIAt

MM52JI

CON\lERTER

25&>1.

COLUMN
GENERATOR

c
o
'.j:i
::::J

~CD

CHARACTER! . .

INPUT DATA

A7

o-....HH-----....I

a:

•......•

1234i;6719'OIlU

I

.c

.21

:

::I:

:
•

II)

•

:!
o
a:

(I)

•

••••••••

(A) 12

A. . . .

X

~~O~~L~~N

~

••••••• -- e - - - -

.5

en
.s;c
ca

.....
.

::

e.

~;

112 COLUMN

13

ClDCK~a

"15
,6

16 Vertical Scan (UC)

o - - -....-I

It)

co
I

Z

c(

A.~~~~'
A,o-....+-HI-----....I

PIS

(BI 16 x 12, 96-Character Generator (UC/LC)
FIGURE 9. Intermediate Coding Designs (MOS'ROM Organizations)

11·42

OUTPUT
DATA

l>

that holds the column output' static ,until it has
to change would be highly efficient.

ROM. Up to 128 unique column patterns are
stored in 8·bit,- half·column segments in the
MM!i231 256 x 8 ROM. These are accessed with
7·bit intermediate codes selected with the input'
array and a half·column clock at a submultiple
of the dot rate. The intermediate codes necessary to
form each character are simply listed in character·
generator fashion in the' input code converters.
At 16 x 12, the savings for an upper·case font are
12k - 8k or 4 kilobits-33%.

Figure 10 is a practical design for upper·case
fonts with 10 x 10 to 13 x 10 matrices. It saves
nearly 40% of ROM capacity. Moreover, the
matrix width varies with the character shape as
can be seen in the example word LIMB. The
characters look more natural and are 'evenly
spaced. Column height is changed by programming
the outputs to be used.

Since the 8·bitoutputs of the MM5241 ROMs'
actually allow 128 unique columns to be selected,
the savings could grow rapidly through several
expansion levels even without further rearranging.
If more than 128 unique column codes are reo
quired the second ROM in the storing Can be
changed to possibly a 512 x 8 ROM (MM5232)
therefore giving 256' unique columns which can
be generated for the larger fonts and character
'group sets (96 characters or 128 characters).

Proportional spacing makes this organization an
excellent choice for ink·dot spray printers and
other "line of type" printing applications, as well
as vertical·scan displays.
This technique does not lend itself directly to
raster·scan displays since characters are scanned
sequentially on one raster line at a time rather
than completi ng a c!'aracter before starting a new
character. To use this technique on raster·scan an
intermediate storage memory would be necessary
for as a line memories.

Assume a 16 x 12, 96·character requirement.
MM5241 ROMs added as in Figure 9B would
provide 192 unique column patterns and the
savings would be at least 18k - 12k = 6k.

PROGRAMMING AND OPERATION

It might be necessary at the 24 x 12 UC/LC size
to use two MM5227 256 x 12 ROMs in parallel,
but this would stiil, save 27k -15k = 12k (or
perhaps 36k - 18k in a 128·character application,
using four input and two output 'ROMs). The
efficiency grows with font size because the column
patterns become more redundant.

Assume a nominal matrix size of 13,x 10. This
takes a 256 x 16 ROM array. Each 16·bit output
word contains a 13-<1ot column pattern, a 2·bit
repeat code and, in the last word of a character,
an EOC bit (end of character "1" bit). Address
location 0000 0000 is reserved for an all·zero
spacing column:

At first glance, the organization appears to double
tne access time because there are two stages to be
accessed in sequence. But since there is no feed·
back, the stages can operate in a ripple mode.
Thus, an 8·bit bipolar register can be inserted
between the stages to temporarily store each
intermediate code. This restores 'the overall access
time to that of the slowest ROM ih the series
(e.g., less than a microsecond for MaS ROMs) and
the character rate is essentially the 'same as that
achieved with conventional ROM techniques.

The first address of each character is listed in the
small input ROM at locations where they will be
accessed by the standard code. The intermediate
code will then be the starting address and the next
column·select codes for each character will be
generated sequentially by the logic.
Suppose characters @ through K occupy locations
00000001 through 0010 1111 in the main ROM.
Then, L's three words occupy locations 0011 0000
through 0011 0010, M starts at 0011 0011, and so
forth. L takes three words at the 13 x 10 size
since the 2·dot bar pattern can be repeated only
four times with a 2·bit repeat code. If the columns
were programmed 12 or less dots high, a 3·bit
repeat code could be used. L would be generated
with two words and single·pattern characters like
"dash" with one word. This solution uses only
2 x 16 bits of storage for the character Land
compared with its present techn ique of lOx 12 =
120 bits.

Alternatively, the output ROM. input ROM, or
Qoth may be 'bipohir to increase the rate. The
DM8596 512 x 8 ROM fits most large·font
geometries quite well and costs less than sub·
assemblies of 1k bipolar ROMs. Again, an inter·
mediate register will maximize the rate. '

REPEAT~PATTEFiN CODING
Some character styles have bold "double dot" or
similar patterns that result in a high probability
of the' same column pattern repeating sequentially
in the same character. Tl:1is characteristic is common
in "ticker tape" systems, large·panel and billboard
displays, news bulletins broadcast to appear as a
running line across a television picture, and so
forth. Typical fonts exhibit less than 256 actual
changes of column patterns through a 64·character
sequence, not the worst·case of 320 at 7 x 5, 640
at 10 x 8, and so forth. Therefore, an organization

Now, let's generate LIMB. First, the standard code
for L (e.g. 001 100) is converted to 0011 0000,
which sets the address counter. The address counter
access that word in the main ROM, and the repeat
code in the output sets the master counter to
time out in two column scanning intervals.
L's first two columns are thus' formed. At the
master counter's terminal state, the address counter
advances to 0011 0001, the master counter is reset
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Proportional spacing is inherent. So is high·speed
since the input ROM is a small bipolar array. The
main ROM can be either MaS or bipolar general·
purpose ROMs. This .organizationshould ·also
expand efficiently since the repeat probability
tends to rise with matrix width.

to time out in four column intervals, the address
counter advances again, and word 0011 0010 is
accessed during four intervals.
This last word includes an EOC bit. When EOC
and the ti me·out state of the master counter
co.incide, gate 1 clears the address counter. Now
address 0000 0000 generates the. space· pattern in
two spacing columns. When the master counter
reaches its second state, gate 2 enables the address
counter's parallel preset inputs. Finally, the input
ROM sets the counter to the starting address for
I and the process continues through I, M and B.

I n printing applications involving more complex
characters, the operational advantages might be of
more interest than ROM savings. For example, two
64 x 6 x 8 or 512 x 8 ROMs might be used as an
UC/LC generator with the ninth address input a
direct shift control.

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It is perhaps of more interest to .examine an
actual system to determine the effects of clock
decoding. As an example a complete Sk-by-16-bit
memory has been designed and is shown in
Figure 4. This system is not optimized but will
serve as a good comparative example. Table II
shows power. consumption for operating and
standby modes with clock decoding and Table III
gives power consumption without clock decoding.
A comparison . between these tables shows a
42% decrease in power consumption by employing clock decoding. Table IV shows various memories mechanized using the basic Sk:by-16 module.
Power consumption is given with and without
clock decoding for cycle times of 635 ns and
1,000 ns. It is clear from these tables that as
memory size increases clock decoding becomes
essential. Saying this another way, the ratio of
a memory components operating power to standby
power is an important parameter for the designer.

the DM7474, as shown by the dotted line in
Figure 2, the glitch will be extended into a full
Phase 1 pulse.
The extra Phase 1 pulse after a refresh cycle
will not cause any problems but it will change
the value of the refresh current. I f refresh is
implemented by doing one refresh cycle every
62.4/.1s, the refresh power will be doubled over
what it would be if 32 refresh cycles are done
consecutively every 2.0 ms. This is due to the
fact that with 32 consecutive refresh cycles the
memory receives 33 Phase 1 clocks and with a
refresh cycle every 62.4/.1s the memory receives
64 Phase 1 clocks.
One advantage of connecting REFRESH to the
clear input of the DM7474 is that REFRESH is
no longer required to be applied for the entire
cycle and may return to a one after the positive
edge of T1.

TABLE II. Power Consumption of Bk x 16 Module (With tCYCLE
IcC (rnA) @ 5.25V
OPERATING

OPERATING

TTL

1,180

1,180

IBQ {mAI@ 8.75V

MH()()26

124

1.2

MM5262

699

12.8

650

Total Current

2,003

1,194

Total Power (Watts)

10,5

63

OPERATING

STANDBV

0

STANDBY

0

0

11

0

0

19.2

8.0

6.5

761

20.3

8.0

6.5

12.2

0,33

0.07

0.057

111

0>

= 635. nsand Clock Decoding)

100 (mA) @-16V

STANDBY

•

00

0

Total Operating Power = 10,5 + 12.2 + 0,07 '" 22.8 Watts
Total Standby Power = 6.3 + 0.3:3 + 0,057 = 6.7 Watts

TABLE Ill. Power Consumption of 8k x 16 Module (With tcYCLE

= 635 ns and No Clock Dec:oding)

Icc (rnA) @ 5.25V

IOD (rnA) @-1SV

IBB (rnA) @8.7SV

OPERATING

OPERATING

OPERATING

TTL

1,180

0

0

MHOO26

241

231

0

MM5262

1,333

1,290

9.6

Total Current

2.754

1,521

9.6

Total Power (Watts)

14.4

24.4

0.875

Total Operating Power = 14.4 + 24.4 + 0.875

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TABLE lV. Power Consumption of Larger Memory Systems Using Multiple 8k " 16 Modules
TOTAL POWER (Watts) tcVCLE ,"" 635 ns

TOTAL POWER (Watts) tcvCLE

c:

1,000 ns

NUMBER
OF CARDS

CLOCK DECODING

NO CLOCK DECODING

CLOCK DECODING

NO CLOCK DECODING

8k x 16

1

22.8

39.3

16.9

25,8

8k x 32

2

45.6

78.6

33.8

51.6

16k x 16

2

29,5

78.6

23.5

51.6

16k x 32

4

59

157.2

41

103.2

32k x 16

4

42.9

157.2

36.7

1032

32k x 32

8

85.8

3144

73.4

206.4

MEMORY
SIZE

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HOW TO DESIGN WITH PROGRAMMABLE LOGIC ARRAYS

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INTRODUCTION
A new and exciting IC device, the PLA (Programmable Logic Array), is heralding a new era of
circuit compression comparable to the introduction
of medium scale integration devices in the days
when gates and flops were the only digital building
blocks available.

The large variation in the partial product terms
possibilities of the 14 input variables are shown
below:

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P2 = 14 15 17 1'2 r:;;.1'4

As the name suggests, a PLA is an array of logic
elements such that a given input function produces
a known output function. In this sense, the device
could be as simple as a gate or as complex as a
Read Only Memory (ROM). Applications range
from the slowest and smallest systems, such as
traffic light controllers, to fast, high performance
and complex large digital processors. In the following sections, the PLA will be described and its
advantages over.alternate logic forms demonstrated.

P3

= 16 1,2

P4

= Is 19 110 111

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WHAT IS A PLA?
Since there is a difference between a Programmable
Logic Array (PLA) and a rectangularly structured
Read Only Memory (ROM). the PLA should be
described. Even though any input code can be
decoded to any output code in the PLA, not all
possible input combinations are possible within
the same package. The numbers of inputs to a PLA
are much more than would be available with ROMs
(Figure 1). In the case of the DM8575/DM8576
there are 14 inputs and 8 outputs. This would
relate to ROM with 2'4 or 16,384 words. This
PLA (DM8575/DM8576) has 96 equivalent words.
These terms are called partial prod.uct terms. Each
product term can be described as a logical AND
function which relates to a protion of the total
output terminal solution. Each product term can
be programmed to any complexity up to the input
limit of the PLA. The DM8575/DM8576 PLA may
have 14 variables in its product term or it may
only have one input which establishes the product
term. The PLA logically can be described as a
collection of "ANDs" which may be "ORed" at
any of its outputs_ Figure 2 shows the logical data
flow from the. 14 address input terminals through
the "AND" gate to the "OR" gate and to the
output terminal.

INPUT
(1~

OUTPUT

GROUP
INPUTSJ

CODE
IS OUTPUTSI

111.196 PRODUCT TERM H-INPUT PtA

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CODE

IB141lQ6 BIT ROM

FIGURE 1.

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It is possible to combine or collect by mask option
any of the product terms for any of the several
outputs to establish the output code combinatioris
desired. Logically any or all of the partial product
terms (AND terms) can be combined (ORed) at
each output.

at the outputs. The system designer must test the
possible choices to be used within the PLA. He
should combine all mutual terms within the same
package. Commonly grouped product term adds to
the efficiency of the PLA or PLA array as indio
cated in the previously mentioned equations.

The equations for the output group have the
following form:
01=Pl+PI6=P20+P42+

P92

02=P6+PI6+P17+P42+

PS2

WHY A PLA?

The appl ication of the PLA in a digital solution is
a natural evolution in system design. Several years
ago digital systems were designed with gates and
dual D memory elements. The system at that time,
was conceived and implemented in its best possible
way. A later development in system design utilized
ROM's to provide the complex decoding for the
control necessary to satisfy the same system
design objective. Now we are in a new era. The
design of the same system control function can be
achieved by utilizing the, desirable characteristics
of the .PLA (Programmable Logic Array). The
reason for this evolution of design is based upon
one or more of three possibilities. First, the new
design will yield a higher performance solution.
This generally relates to an improvement in system
dynamic performance because fewer levels of logic
are required to 'provide the same control function.
Second, the design will result in a lower parts cost.
This is due to the more efficient useaf the memory
array as compared with the normal rectangular
array ROM. The third possible advantage comes
from the reduction in system manufacturing cost
brought about because of the reduction in com·
ponent assembly cost, the reduction in printed
circuit board cost or possibly connector cost within
the system. Each time a system's physical size can
be reduced by the use of more complex elements
such as a PLA (Programmable Logic Array) the
cost of that system decreases also because fewer
cards and connectors are required.

0 3 = PI + P20 + P36 + ... P96
Each of the partial product terms labeled PI
through P96 are shown as they appear at each
output. Note that the same product term may be
used in as many output equation groups as required.
It can be seen that PI, the first product term, is
used in both outputs one and three and P16 and
P42 are used in outputs one and two.
A PLA need not have more than one output but it
is generally more efficient to build the PLA or
ROM with more than one output. The PLA in this
discussion has eight output terminals which reflect
the silicon efficiencies of today's technology. This
product has the ability to be masked with outputs
in either a positive true state or a negative true
state. (Figure 2) These capabilities enhance the
elements valuewhen applied to the system solution
since the inverter at .the output terminal is not
required.
To use this memory storage device, the memory
storage equations must be written or tabulated so
they can be stored' within the mask programmed
element. A large number of possible choices exist
when the equations or product terms are collected

11·50

l>

THE PLA AS A CODE CONVERTER

An invalid input is designed to produce an all-high
output state by virtue of the fact that it is not
a recognizable product term,

Being a device, which from its input terminals produces outputs in· accordance with a predefined set
of rules, a P LA can be viewed as a memorystoiage
device (i.e., a limited capability ROM). Hence, if all
the partial product terms for a particular code
conversion can be limited to the 96 available, then
the PLA could be used in this application.

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THE PLA AS A DECODE ELEMENT
IN A DIGITAL PROCESSOR

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Why does it naturally follow that the PLA lends
itself to the control function of a digital processor
or other simularly organized system? Many processor oriented systems have control instruction
codes which are much wider (a large number of
inputs bits) than that which can be easily satisfied
with ROM's,

Recall that a product term consists of a combination of input variables which can represent a
characters code, then the code conversion is
possible for a 96 character set_ Take the case of
12-line Hollerith to 8-line ASCII conversion as an
example. Theoretically, 12-line input represents
the possibility of 4k words. Actually, seven of the
12 Hollerith lines are not binary coded lines, they
are ordinary decimally coded lines. So that a ROM
structure with 12 input lines are not used, these
seven lines must first be encoded to 3 binary
lines using additional logic elements prior to being
presented into a common 8-input ROM (Figure 3A).
In addition, the 12-input ROM would have to
decode all the non-existent input possibilities
into don't care (or error) output states.

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The PLA solves this problem efficiently, All 12
inputs are presented to the PLA. Since selective
decoding is a feature of the PLA no provision need
be made for pre-encoding of the inputs (Figure 3B).

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FIGURE 3B.

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HOltERITH TO ASCII
MODE
CONTRDt

4 INPUT NAND GATES ARE
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FIGURE 6.

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FIGURES.

11·54

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lem. The input control code is 14·bits wide and
the output control word is 28-bits wide, Figure 9.
This means that we would use four PLA's to
generate the decoder solution if none of the packages required more than 96 partial product terms.
In our example assume that there are four output
codes which have 90 partial product solutions
without considering the terms required by the
four other output terminals of the PLA under

Note that the state diagram Figure 8 shows that
the maximum time interval X is checked to be
greater than the present value of the A elapsed
time counter. If this is true, the state counter
indexes to the next machine state (state B). The
output data transmitted to the holding memory
(DM8551's in Figure 7) will be changed with every
state step in the system. The four packages of
holding memories are used to store the control
information for the traffic indicators. The memories
(DM8551's) are sequentially updated by using the
same scan decoder which is used as a multiplex
decode of remote traffic counters (DM85L54's).

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question.

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The initial thought about solving this problem,
would suggest the use of an additional PLA with
inputs and outputs connected together to obtain
the extra product terms. Since the four PLA's
have a total of 32 outputs and only 28 are required,
the 4 unused additional outputs may be coupled
from a second PLA to the PLA which first contained the 4 high Usage partial product groups of
terms (Figure 9).

The control coding developed allows a state
interval to be shortened because one of the cross
streets has detected on coming traffic. Also, the
state interval can be lengthened if no cross or left
turn traffic is detected. As the sequencer steps from
state to state the other state conditions are tested.
In other words, while in state B state conditions for
A, C and D are tested for the necessary conditions
which might modify the timing of state B. The four
traffic counters which are shown in Figure 7 as
DM8554 elements are multiplexed sequentially into
the PLA sequencer controller where they are logi·
cally "ANDed"with present state timing. Using this
information the sequencer period is modulated per
the equations defined by the state equations.

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...»

ill

-<
(/)

It should be noted that the sequence order need
not be orderly. The sequence of states through a
complete cycle may have repeat intervals or jump
commands in any step within the vastly variable
complete sequence loop. There is no special require·
ment that the sequencer be designed with order in
mind if some sort of disorder will yield an improvement in performance. The performance advantage
may relate to a dynamic performance improvement
or it may relate to a cost performance improvement. Generally a cost improvement resu Its when
fewer parts are required in the overall solution.

OUTPUT

CONTROL
CODE
12U OUTPUTS)

FIGURE 9.

DESIGNING WITH A PLA
How should a PLA solution be developed? An
orderly approach to the solution is necessary when
the control word is wide and complex inform. The
following techniques may be of some help in
determining the decode combinations when using
a PLA solution_

Doing this allows half of the partial product terms
to be placed in each of two separate PLA's. PLA's
can be connected with common inputs and common
outputs. It should be noted that the output code
tor the common terms must be programmed using
a negative true logic for, since this permits "wireOR'ing" the outputs. This very significant design
possibility would not be allowed if standard ROM
techniques are used.

1. List all input control codes which are required
for each output.

2. Reduce this list logically to minimize the number
of partial product terms.

This interesting observation shows that memory
expansion for this product (PLA) is different than
other memory elements. The normal Read Only
Memory (ROM) or Random Access Memory (RAM)
elements have chip select inputs wh ichmust be
decoded and selected before the package is activated. When these types of memories are expanded,
additional decoder logic elements are required to
select the proper memory array Figure 4. I n case
where there are more than one output terminal,

3. Combine similar terms which may be used on
more than one output terminals.
4. Group outputs which can share the largest percentage of the same partial product term'.
There are some additional considerations with the
general solution. Let's assume the following prob·

11-55

m

~

~


.;::
C
~

CJ

.2

(.)

.

I:
CI)

-0

o

~

C)

where:

The TO·5 ("H") package is rated at 750 mW still air
(derate at 200°C!W above 25°C) soldered to PC board.
This popular cavity package is recommended for small
systems. Low cost (about 10 cents) clip·on heat sink
increases driving capability by 50%.

v+ - V- = Total voltage across the driver

"ON" state
(3)

OC

Co

<

= Duty Cycle

"ON" Time
~---------

"ON" Time + "OFF" Time

For the DS0025, Req is typically 1 kn while Req is
typically 600n for the DS0026. Graphical solutions for
Poe appear in Figure 1. For example if V+ = +5V,
V- = -12V, Req = 500 n, arid DC = 25%, then P oc =
145 mW. However, if the duty cycle was only 5%,
Poe = 29 mW. Thus to maximize the number of registers that can be driven by a given clock driver as well as
minimizing average system power, the minimum allowable clock pulse width should be used for the particular
type of MaS register.

To TO-8 ("G") package is rated at 1.5W still air (derate
at 100°C/W above 25°C) and 2.3W with clip·on heat
sink (Wakefield type 215-1.9 or equivalent-derate at
15 mWfC). Selected for its power handling capability
and moderate cost, this hermetic package will drive very
large systems at the lowest cost per bit.
Additional information is given in the section of this
data book on Maximum Power Dissipation (page 2).

I:

'>
Q.

= Equivalent device resistance in the

Req

The 8·pin ("N") molded mini-DIP is rated at 600 mW
still air (derate at 90°C/W above 25°C) soldered to PC
board (derate at 1.39W). Constructed with a slJl€cial copper lead frame, this package is recommended for
medium size commercial systems particularly where
automatic insertion is used. (Please note for prototype
work', .that this package is only rated at 600 mW when
mounted in a socket and not one watt until it is soldered
down.)

Power Dissipation Considerations
The amount of registers that can be driven by a given
clock driver, is usually limited first by internal power
dissipation. There are four factors:

225
~

1.
2.
3.
4.

.sz

Package and heat sink selection
Average dc power, P oc
Average ac power, PAC
Numbers of drivers per package, n

";::
:
ill

20V~1.

200

l' I

150

f

From the package heat sink, and maximum ambient
temperature one can determine PMAX , which is the
maximum internal power a device can handle and still
operate reliably. The total average power dissipated in a
driver is the sum of dc power and ac power in each
driver times the number of .drivers. The total of which
must be less than the package power rating.

I
1/

50

0

17

Ii. V

e-0

10

lL

V
~

.......,.

V

20

V

/ v+-Ivp

/

V

zv

15

25

.!, /

20V

,.I V /

125

15 100

'"~

/1

117:t

175

_IRED; 500
REO'" 1k
30

40

50

60

10

DUTY CYCLE 1%1

FIGURE 1. POC vs Duty Cycle

(1 )

In addition to Poe, the power driving a capacitive load
is given approximately by:
Average dc power has three components: input power,
power in the "OF F" state (MaS logic "0") and power
in the "ON" state (MaS logic "1").
(4)

(2)

where:
f

For most types of clock drivers, the first two terms are
negligible (less than 10 mW) and may be ignored.
Thus:

Graphical solutions for PAC are illustrated in Figure 2Thus, any type of clock driver will dissipate internally
290 mW per MHz per thousand pF of load. At 5 MHz,
this would be 1.5W for a 1000 pF load. For long shift
register applications, the driver with the highest package
power rating will drive the largest number of bits.

(v+ - V-)2
Poe

== PaN

=

Req

= Operating frequency

C L = Load capacitance

x (DC)

11-28

~

App Notes/Briefs

NAnONAL

APPLYING MODERN CLOCK
DRIVERS TO MOS MEMORIES

s:o

..

c..

INTRODUCTION
The OSO.0.26 is a high speed, low cost, monolithic clock
driyer intended for applications above one megacycle.
Table .II illustrates its performance characteristics while
its unique circuit design is presented in Appendix II.
The OSO.0.56 is a variation of the OSO.0.26 circuit which
allows the system designer to modify the output performance of the circuit. The 050.0.56 can be connected
(using a second power supply) to increase the positive
output voltage level and reduce the effect of cross
coupling capacitance between the clock lines in the
system. Of course the above are just examples of the
many different types that are commercially available.
Other National Semiconductor MOS interface circuits
are listed in Appendix III.

MaS memories present unique system and circuit
challenges to the engineer since they require precise
timing of input wave forms. Since these inputs present
large capacitive loads to drive circuits, it is often that
timing problems are not discovered until an entire
system is constructed. This paper covers the practical
aspects of using modern clock drivers in MaS memory
systems. Information includes selection of packages and
heat sinks, power dissipation, rise and fall time consid·
erations, power supply decoupling, system clock line
ringing and crosstalk, input coupling techniques, and
example calculations. Applications covered include
driving various types shift registers and RAM's (Random
Access Memories) using logical control as well as other
techniques to assure correct non-overlap of timing waveforms.

The following section will hopefully allow the design
engineer to select and apply the best circuit to his particular application while avoiding common system problems.

Although ·the information given is generally applicable
to any type of driver, monolithic integrated circuit
drivers, the OSO.0.25, OSO.0.26 and OSO.0.56 are selected
as examples because of their low cost.

PRACTICAL ASPECTS OF USING
MOS CLOCK DRIVERS

The OSO.0.25 was the first monolithic clock driver.
It is intended for applications up to one megacycle
where low cost is of prime concern. Table I illustrates
its performance while Appendix I describes its circuit
operation. Its rnonolithic, rather than hybrid or module
construction, was made possible by a new high voltagegold doped process utilizing a collector sinker to minimizeVCESAT.

CD
::::I

n

0"

n

7'

..
..

o

<'
CD
1/1

....o

s:

o

C/)

s:
CD

3

o

::!.

CD
1/1

Package and Heat Sink Selection
Package type should be selected on power handling
capability, standard size, ease of handling, availability
of sockets, ease or type of heat sinking required, reliability and cost. Power handling capability for various
packages is illustrated in Table III. The following guidelines are recommended:

TABLE I. OS0025 Characteristics
PARAMETER

CONDITIONS IV+ - V-I ~ 17V

VALUE

UNITS

15

ns

tON
G'N ~ O.OO22I'F.

tOFF

RIN ""

GL ~ O.OOO1~F, RO

t,

~

on

50n

~ V~

av,

V 1N

Negative Output Voltage Swing

liN"" lOmA,

On Supply Current (v+)

liN -'" lOmA

'"

ns

25

ns

150

ns

lOUT;;; -1 mA

V+ - 0.7

V

lmA

V- + 1.0

V

17

mA

tf

Positive Output Voltage Swing

30

lOUT'"

TABLE II. 050026 Characteristics
PARAMETER

CONDITIONS IV+ - V-I ~ 17V

VALUE

UNITS

7.5

ns

7.5

ns

25
25

ns
ns

tON

C'N ~ O.OOlI'F. R'N ~ 011

tOFF

RO

t,

0

50l1. C L

~

1000 "F

tf

Positive Output Voltage Swmg

VIN-V-"'OV,louT""'-lmA

V+ - 0.7

V

Negative Output Voltage Swing

liN'" 10mA. lOUT - 1mA

v-

V

On Supply Current

(v+,

liN'" 10mA

11-27

+ 0_5
28

mA

(I]

.

...

Q)

(,)

...coco

s::.

(J

"Eco

"C

c:

...co
en
,=

...c:

II)

UItE

LINE

tOUNTER

DIVIDER

--.-tOtuMIi
COU_TEA

FIGURE .14. Conversion of Sawtooth Output to Pedestal Scan

o

u.

c:

CO

Q)

.

Q.

o

;:,
W
'C

c:

CO

c:

CO

(,)

For example, the extra height may be used in an
otherwise 5 x 7 font to drop the tails of commas,
semicolons and lower-case letters below the bottom
line of the capital letters. Fonts as large as 16 x 12
are entirely practical without additional control
logic, using the chip-enable feature of four
MM5241 s. Large-font organizations are discussed in
AN-40.

CUSTOM FONTS

The two ROMs can also be custom-programmed
to provide special characters, or fonts larger than
5 x 7. The MM4240/MM5240 actually stores 64
5 x 8 characters or character segments and the
MM4241/MM5241 stores 64 8 x 6 characters or
segments. They are not Iimited to 5 x 7 and 7 x 5.

'0:::
Q)

E

«
.....
LO
I

Z

«

11-26

»

z

... ... .... ....I-.: .I...
............
.
! .:
.I... ..
·.......... .1•••..1I.....: I • ..
.: ....: ....
.... _...!::
......
··:.....:: ..:.:.i .......
I:·.:
::!:
. .. ... ..........- .... ....

... I....•J ....I...: I...• I....: .I..............
.
L.. ! .:
i i i...: :.... I..·· i.... I :..J
: : ...
:...:
·: " .: ...i I I·: I I : i le.J I !
··:I···.........
..!..-.:....:1-::...........
... ....•••: ..:!.. :::::.:
.!....:: ..:1... ..i.
...-....
.-:-........-.. [ :.... ...·1 .•••..! .
•
.....
".. . .." . .
.
....
::
..
·· ··.. ......::............::........
.
..
: ...
. ....
·
. .....:.....:.. ..... ....
:. ..! .
... . .. . :.=
...
.....
.: ..... ..... .: :.... ......-:
....
....
..... ..... ...
···...
...
...
...........
..
...... ..
.........
.... .......
. ......
...:
... ...
... ........ ......
·.........
..
.............. .
..
..
.
.:
..." ... ..
:::.

••••
00

000000

Ql
~~

~

~m

~

mrn

-:-: .-:

001000

"

001001

••••
: 13 •• : ••••
:
12
14
001010

001011

001100

21

n

~

~

0100110

010001

D1DOIO

010011

010100

la

:

011000

"

100000

31

:

I.32•••

011001

011010

41

100001

51

1010110

.~
110000

101001

61

110001

"

100010

52
101010

"

110010

011011

~

~m

mm

l4
011100

2!i
010101

011101

DB1110

2~

010110

1.

011110

43

44

45

46

100100

100101

100110

U

HOol1

10

71

12

73

11100II

1110111

111010

111011

00
0011000

54
101100

M

110100

111100

55
101101

n·

110101

15
111101

56
101110

"

110110

7&
111110

:

:1••• •••••·:••M• : •••• :,

01
OOOODI

~

~

000010

000011

000100

~

~

000101

000110

• •••1
~

0lI0111

:

I I ·16 : ·...
•
11

15
001101

100011

53
101011

~

~m

: ••::. I.·...

ro

:

.~

M
~~

10

001111

001000

12
001010

"

001001

13
001011

14
001100

15
001101

16
001110

11
1101111

I···: :...: r··: :....., .. ! I! II I

:... :.::.:..... : : ::1 I::
:

21
0111111

20

~

• • •• :

22·· ••

!

-·rs··

!

:"21·:

010100

010101

DID 110

01D111

14
011100

35
011101

36
011110

~..

. .:.
..·....-................ . ......
:.
: •• . ·a·
,e.::
. ... .: .....
•
"
.. .:........:.........
.. . . ..
.. ..:. ·
010000

010001

010010

: :: :
-:-

J1
011111

:

:

30

31

32

011000

011·001

011010

:
:

010011

011011

:: :

31
011111

::

:

. .:.....:. : :: .....
...:. ...1 :·1·:.. .•:.:
1.. ..... ..
."
.• .
: ..: . :. .........
: ..... :... ...
·...
..........
.. .......
........
.........
. ......
.. .... ••••• .....•
..... ....• .
.
.
.
.
.
.
·•...'" ......• . •".. " ..•". ··•
.

41
100111

100000

41

100001

41
010

I~O

43
100011

44
100100

45
100101

46
100110

41
100111

••1

51
Hl1111

51

101000

101001

••••• .:

~
110111

52
101010

53
101011

501
101100

••••• •••••

5!io
101101

56
101110

In 111

.: I··..........:

~

61

U

~

~

11000a

110001

110010

110011

1101110

e

110101

"

110110

~

110111

..... •••.1

n

111111

11100II

FIGURE 11. MM4241ABX/MM5241ABX Vertical·Scan
ECMA·7 Font for General European Use
IFrench, British, Italian)

11
111001

12
111010

11

13

111011

1111111

111101

1111111

111111

FIGURE 12. MM4241ABY/MM5241ABY Vertical·Scan
ECMA·7 Font for Spanish Use

I

(J'I

......

»
3

...
C:;"
CD

Gl.

:;,

III

:;,
~

m
...c
o

"
CD

III

:;,

"o:;,
...
III

3"

...

en
III

:;,

~

...

Gl
Q.

n

':1'

.,Gl

Gl

...

n

...

CD

SAW TOOTH DISPLAY

C)
CD
:;,
CD

.,

PEDESTAL DISPLAY

Gl

g

...

III
NEXT
CHARACTER

FIGURE 13a. Sawtooth Vertical Scan

FIGURE 13b. Pedestal Vertical Scan

II]
11·25

l>
Z1

....

Form IV

o
o

MM4241/M1IJI5241

eEl
CHARACTER

LINE

ADDRESS

ADDRESS
DECIMAL

(DECIMAll

_0

LSB
Bl

(')

OUTPUT CODe

B2

B3

BO

BS

B6

B8

B7

SUM

CHARACTER

LINE

ADDRESS
(DECIMAL)

ADDRESS
DECIMAL

_5

0

0
Ll L, Lo
o 0 0

LSB
Bl

OUTPUT CODE
B2 B3 80 BS BO

c

B7

B8

SUM

:JJ

1

1

o

3:

2

010

...

3

3
01 1

"'0

~

o

4

0

...

CC

100

5

5

-,

o

3

001

2

~

1 1 0

_6

0

I»

3
3

0

000

:i'

1

1

CC

001

2
.-

2
010

--_.

3

3
01 1

4

4
100

5

S
1 1 0

_2

..-

t--

_7

I

0
000

0

1

1
001

2
010

2

i

3

3
01 1

0
100

I

4

:
5

S
1 10

_3

_8

r-------.

1

1

001

r---.-.. -

2

2

010

3

3

01 1

0

4

100

s

S
101

_4

0

0
000

_9

0

r--"
1

0

1

2

2

3

3

4

4

5

5

TB

TB

Note 1: On the character address and output word negative logic is used:
f\ logic "1" most negative voltage
A logic "0" most positive voltage
on the line address positive logic is used:
A logic "0" most negative voltage
A'iogic "'" most pos,itive voltage
Note 2: Line address (L o , L 1 , Ll.) are the column select lines in a character generator application. In a read only memory
applicatipn A(, shall be considered the MSB and Lo the LSB.
Note 3: TB is the total "'" bits in a column expressed in Decimal.
Note 4: SUM is the total "1" bits in a row expressed in Decimal.

11-61

m

Cl

c

E
E
I'CI

...Cl

TAPE ENTRY FORMAT
Tape format for the following ROMs.

MM3501
MM4210(MM521O
MM4211(MM5211
MM4213(MM5213

o...

c..

MM4214(MM5214
MM4220(MM5220
MM4221(MM5221
MM4230(MM5230

Note 5

~

MM4231/MM5231
MM4232(MM5232
MM4233(MM5233

bg. MSB

Note 6 .

o

a:
E

Note 8
2 Spaces

b"

LSB

-+-'---,
--",--Note3

.s
1/1

1 Space

::s

Note 2

(J

i\lV) 6
inr)"/
(Hlr)l-<

o
o

'7
Z

rj(Jf)tJn(J(1'l

I)

()011110n
On'l()Wl(ln

(j

4

1)1 Cllrl\()] q
1 4 0 _ -_ _ _ _+_Note

4

IE1

<

T86 ?51)
Tf15

4()

B4 (lIn
TAJ

100

TEi;2 1">5
18', 197

t

-'::::=======j-l SpClce

L __

8-BIT TAPE FORMAT

Note 1: The code is a 7*bit ASCII code on 8 punch tape.
Note 2: The ROM input address is expressed in decimal form and is preceded by the letter A.
Note 3: The total number of "1" bits in the output word.
Note 4; The total number if "1" bits in each output column or bit position.

Note 5: Specify product type.
Note 6: Must type POS logic, or NEG logic depending on which is used.

Note 7: LOGIC ON ADDRESS AND OUTPUTS must be the same (either

pas

or NEG).

Note 8: Specify the pattern necessary to enable the ROM on the ROMS that need chip selects.

Tape format for the MM5202, MM4203(MM5203 and MM4204(MM5204.
PROM TAPE P AND N FORMAT
Carr,,,ge return Ime feed
allowed betwr.een F and B

StartCharacteri StoPCharac!eri { , DataF'eld·

I

,

I

MSB (Pin 11)

I

BPPPN P P N N FBN N PPN N PPF
WordO

Word 1

lS8 (P;n4)

t

I

BNPNPNNNNF
Word 255

~

~

All Address Inputs LOW

All Address Inputs HIGH

"'Data Field: Must have only P's or N's typed'between Band F. No nulls or rubouts. Must have exactly eight P and N
characters between Band F. Any characters except Band F may be typed between the F stop character and the B start
be rubbed out. Data for exactly 256 words must be entered, beginning with word O. P "" "1" or the more positive voltage.
N "" "0" or most negative voltage. When the MM4204/MM5204 is used the word length is 512.
PROM TAPE BINARY FORMAT

o

o

r-------~~---------------,-.-BITl

00
0

00
00
00
00
00
00

0 '
0
0
0

~((WORD3

'

'------.---~----...J--BIT

~WORDN

~WORD2

NO,te1:
No~e 2:
Note 3:
Note 4:

WORD 1

8

WORDO

START

Tape must be all blank except for the 513 words punched.
Tape must start with a START punch.
Data is comprised of two words the first being the actual Data the second being the complement of the data.
A punch is equal to a "1" or most positive voltage and the omission of a punch is a "0" or the mOre negative voltage.

When programming the MM5202 or MM4203/MM5203 it should be remembered that the opposite logic from what is
programmed will appear on the output of the PROM. In otherwords a P on the,tape will program a Logic "0" or VL in
the PROM.

11-62

l>

2

.!..

CARD ENTRY FORMAT
Card format f.or the:
MM3501
MM4210/MM5210
MM4211/MM5211

MM4221/MM5221
MM4230/MM5230
MM4231/MM5231

MM4213/MM5213
MM4214/MM5214
MM4220/MM5220

MM4232/MM5232
MM4233/MM5233

o
o

n
cell

S
3

::0

o

3:
"U

AD012

1-'::-::;-:,:::-:-;:::::.::-";-:;...::...::'-':------=--=-::-::----='-:''-' -'-'

1 (I

(;

01 0 1 0 1 01
(I

0

4

CC

~~7:~~-------------

------------------1

~~---------------------------------------------~------------~

----------------------1

--- - - - - - - - - - - - - - - - - - - - - - - - - 1
L-t=::=;-'--''----==c:::':::::~:

----------------- ---- ..---- -_...
--------

-------------- -

---..----- - - - - - - - - - - - - - 1
----- - - - - - - - - - - - - - - - - - - - - 1

1 - - - - - - - - - - - - - ---------- - ------- ------------ - - - - - - - - - - - - - - - 1
f---------------------------- ----------------------j

Note 1:
Note 2:

Punch three input addresses per card with the first address in columns 1-25, the second in columns 26-50 and the third in columns 51-80.
The ROM input address is e)(pressed in decimal form. and is preceded by the letter A,

Note 3:
Note 4:
Note 5:
Note 6:
Note 7:

The total number of "1" bits in the output word.
The total number if "1" bits in each output column or bit position.
Specify product type.
Must type POS logic or NEG logic depending on which is used.
LOGIC ON ADDFl:ESS, OUTPUTS AND CHIP ENABLE must be the same (either

Note 8:
Note 9:

Leading zeros must be punched,
Specify the Chip Select Logic Levels that will enable the ROM where necessary.

pas

or NEG),

Card format for the MM5212.

000000000000
I I I

I

1

I

-:-,-:-,-:,-C,;-:-,---;-

I -C, -C,

01010'

000000000000

r-

\....

0 101 0'
06
--~~

--

--------: --:-:..:.:..:.:-::~:'-:,-:
-'-:

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Nate 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:

Punch three input addresses per card with the first address in columns 1-25, the secon~ in columns 26-50 and the third in columns 51-80,
The ROM il)put address is expressed in decimal form and is preceded by the letter A.
The total number of "'" bits in the output vvorcL
The total number if "1" bits in each output column or bit position,
Specify product type.
Must type POS logic.

Not. 7:

POSITIVE LOGIC ON AOORESS AND OUTPUTS_

Note 8:
Note 9:

".'" more pOSitive output. "0" more negative output.
Leading zeroes must be punched.

11·63

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DESIGNING MEMORY SYSTEMS
USI NG TH E MM5262

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INTRODUCTION

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The objective of this application note is to describe, in
detail, the operation of the MM4262/MMS262 Dynamic
2K P·channel silicon gate RAM and how to apply this
RAM in' designing memory systems, Specificafly the
topics to be covered are:
I.

Detail description, of operation of MM4262/
MMS262

II.

Memory Systems Application of MM4262/
MMS262
A,
B,
C,
D,
E,

III.

information can be read from the memory or written
into the memory, "Dynamic" says the information is
stored in the form of voltages on capacitors. Lastly
"MOS" says the device is manufactured using Metal·
Oxide·Semiconductor technology,
Inputs consist of eleven address inputs (2 11 ~ 2048), Chip
Select, Read/Write Control, Data In, three clocks and
three power suppl ies, All inpu~s except clocks and power
supplies can be driven by standard TTL circuits, The
power supplies are nominally VDD ,,; -1SV, VSS = +SV
and VBB '" +8.SV, The clocks swing from VDD to VSS
nominally, There is one output which sources current,

Interface
System Timing
R,efresh Requirements
Power Considerations
Printed Circuit Layout Considerations

A logic diagram for the MM4262/MMS262 is shown in
Figure 1. Because dynamic logic is difficult to represent

A 16K x 10 Memory Application Example

Although the MM4262/MMS262 device is being used as
the primary example, many of the topics discJssed are
of general application to the design of memory systems,
I. Detail Description of Operation of MM4262/MMS262

The MM4262/MM5262 is a 2048 x 1 random access
read/write dynamic MOS memory, "2048 x 1" says the
device is organized as 2048 words with each word con·
taining one bit, "Random access" says that words may
be accessed in any sequence, "Read/write" says that

TTL Positive Logic
Notation (VDD = -1SV, VSS

~

in standard logic symbols it is necessary to show actual
tra'1sistors in some cases, Further, the internal logic is
shown in negative logic notation, In this notation a logic
"1" is the most negative voltage level and a logic "0" is
the most positive voltage level. Th is is opposite to the
normal TTL lOgic convention, It may seem, at first, that
this change in logic convention introduces unneccessary
confussion, particularly since all inputs and outputs to
the MM4262/MMS262 are specified using standard TTL
logic convention. However, once the negative logic con·
vention is accepted and inputs are translated to this con·
vention it will be much easier to understand the internal
operation of the MM4262/MMS262,

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Negative Logic
Notation Used In
Figure 1 (VDD ~ -15V, VSS = +5V)
Voltage Level

Logic Level

Voltag,e Level

Logic Level

3.SV to 6V

1

3,5V to,6V

0

-SV to 0,8V

0

-5V to 0,8V

1

;;;. 500llA @ 1.8V

1

;;;. SOOIlA @ 1,8V

0

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0

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1

4V to 6V

1

4V to 6V

0

-16V to -14V

0

-16V to -14V

1

5V

1

+5V

0

-15V

0

-15V

1

Clocks

Internal
Levels

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To aid in this translation Table 1 shows inputs and out·
puts in TTL positive logic format and in the negative
logic format used in Figure 1. See page 11.

Inputs

Outputs

.

3

Table 1
11·65

lD

Using the negative logic notation described~ in Table 1 a
logic "1" (-15V) applied to gate of an MOS transistor
wi II cause that transistor to turn on giv ing a low
impedance between the drain and source term inals, while
a logic "0" will cause that transistor to turn off giving a
high impedance between the drain and source terminals.

and the Y Write line will go to a logic "1" when 3 is a
logic "1".
In order for the MM4262!MM5262 to operate properly
the clocks ¢1, ¢2,and ¢3 must be applied in sequence.
Also, as can be seen from the above description of its
operation, the ciocks must not overlap one another. For
instance, if ¢1 and 2 were both on simultaneously, the
XN lines could not be discharged properly by the
memory cell transistors, QA2 and QA3' If <1>2 and <1>3
were on together, the memory cell would quickly lose
the information stored there.

Detail A, shown in Figure 1, shows the basic memory cell
used in the MM4262!MM5262. Information is written
into the cell and read out of the cell via the column line
XN' The Write and Read operation are controlled by the
two row lines, YMW and YMR respectively. Information
is stored in the cell as a voltage level on capacitor CA'

The refresh of a row will then be accomplished when
the clocks 1, <1>2 and 3 are applied in sequence. The
sequence of events would occur as follows:

At 1 clock at logic "1", all X lines are pre·
charged to a "1" level by the transistors labeled Ql.
This "1" levei is maintained by the capacitance of the X
lines until it is conditionally discharged by the cells of
the selected row.
The conditional discharge of the X lines takes place
when Y read line, YMR, goes to a logic "1" turning on
QA2' If a logic "1" is stored on capacitor CA' QA3 is
conducting, allowing the XN line to discharge to Vss
(+5V). If, on the other hand, a logic "0" is stored on
capacitor CA, OA3 is not conducting and the XN line
will maintain the logic "1" level established during (,/>1
time. Note that information being read out of the
selected cells on the X lines is of the opposite level as
that stored on capacitor CA

(1)

All X lines are precharged to a logic "1" at 1
time.

(2)

The complement of the data stored on the cell
capacitors of the selected row, is stored on the
X lines at <1>2 time.

(3)

The information stored on the X lines is written
back into the cells of the selected row at <1>3
time.

There is then only one remaining question to resolve. The
above refresh cycle restores not the original voltage
stored on capacitor CA, but its complement. When the
information is eventually read out of the cell, how can
we tell if the cell contains a logic "1" or "0", since the
voltage alternates with each application of the <1>3 clock?
The answer is the Dummy Cell shown in detail B of

Although the information from only one cell will be
output from the RAM, when the YMR line of a particular
row is taken to a logic "1 ", all 64 X lines will assume the
complement of the data stored in the 64 memory cells
of that row. This characteristic is fundamental to the
refresh operation of the MM4262!MM5262 and will be
discussed in the following text.

Figure 1.

There are 32 Dummy Cells, one for each row. The oUtput, DC, of the Dummy Cell corresponds to the XN line
of the memory cell. Like XN of a memory cen, PC is
precharged to a "1" level at ¢1 time (through Q5)'
Since the YMR and YMWlines are the same for the
Dummy Cell and its corresponding row, the output, DC,
of the Dummy Cell will alternate between a logic "1"
and a logic "0" each time the 1, 2, and <1>3 clocks are
applied. As will be discussed, the output, DC, is used to
complement or not complement the input and output
information. The Dummy Cell is equivalent to a one bit
counter and determines if the row has been complemented an even or an odd number of times. Since DC is
changing in synchronism with all memory cells in its
corresponding row, the voltage out of any cell will be
properly interpreted logically to the outside world.

The Write operation is controlled by the Y write line,
YMW ' When YMW of a particular row goes to a logic "1"
level QA 1 conducts charging the storage capacitance,
CA , to the same logic state that eXisted on the XN line
prior to YMW going to a logic "1". Note that when the
YMW line of a~ particular row goes to a logic "1" the
information on the 64 X lines will be transferred to the
64 cells of the selected row.
Since the information is stored as a voltage on a capacitor
this voltage must be restored or "refreshed" periodically
or leakage currents will cause its loss. As described above
information can ~be read out of a cellon to its corresponding X line and also can be read from the X line
back to the storage capacitor, CA' Referring to Figure 1,
the row lines YMR and YMW (M = 1 through 32)are
driven by transistors Q3 and Q4 respectively. Address
inputs AO throughA4 select which row is to be driven
by taking the gates of 0 3 and 0 4 to a logic "1 ". As can
be seen from the logic diagram the Y Read line of the
selected row will go to a logic "1" when 2 is a logic "1 ':

The description of the basic memory storage mechanism
is now complete. All (hat remains is a description of the
circuitry required to transfer information into and out
of a particular cell. In order to understand the input!
output circuitry, it is necessary to specify the timing

11-66

requirements of the MM4262/MM5262. Figure 2 shows
these timing requirements. The necessity of non·over·
lapping clocks has already been discussed, The timing
diagram quantitatively shows this with the tirning
intervals T 1 2' T23 and T31' In general, it requires a
certain amount of time for information to propagate
through the internal logic elements. This propagation
time .limits the minimum allowable clock pulse widths
(T 1PW, T 2PW and T 3PW) and the minimum allowable
time between clocks (T 12, T 23 and T 31)' I nput signals
in general must be in a stable logic state prior to a clock
edge, input set up time, and after a clock edge, input
hold time. These signals are subscripted "S" (set up) and
"H" (hold) respectively on the tim ing diagram. Set up
and hold times are also determined byini:ernal propa·
gation delays.
All timing conditions, as specified in the MM4262/
MM5262 data sheet, must be adherred to for the proper
operation of this device. This seems like an obvious
statement, but in cases of malfunction it is often found
that incorrect timing and/or voltage 'Ievels are the cause.

Any of the basic functional blocks. is simple taken by
itself. When considered in total, they only seem com·
plex. Let us examine each, for the MM4.262/MM5262,
in turn:

(1)

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Write Circuit
The Write Circuit is driven by the Input Data
Buffer and in turn drives the DS lines. The Memory
is divided into four quadrants. Each quadrant con·
tains 512 bits of storage capacity. There is a
separate Write Circuit for each quadrant. The
inputs of the four Write Circuits are tied together.

(4)

Row Decoder
The Row Decoder decodes address inputs AO
through A4 into one·of the 32 rows. The output
of the five input NOR gate, of the selected row,
goes to a'iogic "1", gating on transistors labeled
03 and, 04' Information is then read from or
written into the cells of that row, at ¢2 and ¢3
time, as previously described.

V~K

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v,,, -~f--+_--"""'\.I
v" --:-rll-:t----I-'-'

(5)

v,,-I,......_+_....;~

READ/WRITE
Vll_

v" -I--t---,......--+--t--tT-v-+•.r - VrL_

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DATAl.

Input Data Buffer
The Input Data Buffer converts TTL input voltage
levels to MOS voltage levels and gates the input
datil to the Write Circuit. The gating of input data
. is c~ntrolled by the CS, R/W and ¢3 inputs and
the output of the Dummy Cell, DC. When DC is a
logic "0", t~e complement of the input data is
written 'into the selected cell. When DC is a logic
"1 ", the input data is written into the selected cell
in the same logic sense in which it appears on the
input pin.

The basic functional blocks are: (1) Input Address
Buffer, (2) Input Data Buffer, (3) Write Circuit, (4) Row
Decoder, (5) Column Decoder, (6) Memory Storage
Array, (7) Sense Circuit and (8) Output Data Buffer.

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(1)

(1)

(2)

Up to this point, the description of the MM4262/
MM5262 has proceeded from the inside'out, so to speak.
Changing our perspective at this time will make the
description of the input/ou"tput circuitry more easily
understood. To do this, let us consider the basic functional blocks of this, and almost any other RAM for that
matter.

V,,1.

I nput Address Buffer

Addresses AO through AlO and CS are strobed into
latches by the ¢1 clock. The latches hold the
address and ch ip select information fixed until the
next ¢1 clock updates them. The true and complement of address and chip select inputs are available at the latch outp~ts. The Input Address Buffer
also converts from TTL voltage levels to MOS
voltage levels required by the internal circuitry.

--TAC(,--

• NOTE, SHADED AREAS AilE HUON'T CARE" eONOlf'ONS. ALL TIMES IIEASUREP TO 5O%POINTSWITH 1•• If " 2D Ill.

FIGURE 2. Timing Diagram for MM4262/MM5262

11·67

Column Decoder
The Column Decoder decodes address inputs A5
through AlO into one of 64 columns, The output
of the siK input NOR gate, of the selected column,
goes to a logic "1" at ¢1 time turning on' the tran·
sistor labeled 02' Turning on 02 will connect the
selected X line to its appropriate DS line. As discussed previous'ly, the X lines are precharged to a
logic "1" at ¢1 time and, as will be seen, the sense
amplifier also charges the DS line to a logic "1"
at ¢1 time. At ¢2 time, information from the
selected .cell is input to the sense circuit via the
selected X line through 02 and the DS line. At QJ3

m

time data is written into the selected cell from
the Write Circuit via the OS line, 02 and the
appropriate X line.
(6)

Memory Storage Array
The Memory Storage Array contains 2048 memory
cells (detail. A) and is arranged in 32 rows and 64
columns. This array is subdivided into four quad·
rants of 16 rows and 32 columns (512 memory
cells) each. The subdivision is necessary only to
facilitate circuit layout and improve performance
due to parasitic elements. It has no functional
significance. The operation of the storage array
has been discussed previously.

(7)

The hooker is of course, "if done properly." What ,is
proper? The wors~ case TTL "0" level is 0.4 volts
maximum when sinking 16 mAo The MM4262/MM5262
does not require any current sink, except for leakage"
and its "0" level input voltage is 0.8 volts leaving 0.4
volts for noise margin. Clearly the TTL "0" level is no
problem. The "1" level is not so straight forward. A
, worst case TTL "1" level is 2.4 volts and at VSS = 5 volts
the MM4262/MM5262 requires a minimum of (VSS -1.5)
= 3.5 volts as an input "1" level. Clearly this is in conflict. However an examination of the worst case TTL "1"
level specification in more detail will. make this picture
considerably brighter.
Figure 3 is the schematic of a typical TTL gate. The "1"

Sense Circuit

level output voltage is: Vout ( 1) = VCC - (I C2 x 1.6K +
VBE(03) + VD1)' With transistor 02 turned off 04
will be off and with no dc load on the output, IC2"; O.
The one level output voltage is then: Vout (l) = VCCV BE(03) - VOl' At 25°C V8E (03) and VDl will be
approximately 0.7 volts. The TTL "1" level output is
Vout (l) = VCC - f.4 volts, giving 0.1 volts of noise
margin. It is important to note that even though TTL
"1" levels are'specified as absolute voltages they. actually
follow the VCC supply.

The Sense Circuit is designed such that the OS
lines are forced to a logic "1" and OS lines to a
logic "0" at <1>1 time. Information from the OS
lines is strobed and latched by the Sense Circuit at
<1>2 time. The DS outputs of the Sense Circuits
drive the Oljtput Data Buffer.
(8)

Output Data Buffer
The Output Data Buffer converts the output data
from '. MOS levels to the output current levels
specified on the data sheet: Three of the OS lines,
from the three quadrants not selected, wi II be at a
logic "0" level. The fourth DS line, from the
selected ·quadrant, will be gated to the output in
the same logic sense when OC is a logic "1 ", and
complemented when OC is a logic "0".

DM5484/DM7404

r - -.......--_-1 - Latches input addresses and precharges internal
nodes.

FIGURE 3. Typical TTL Gate

Under what conditions will the "1" level output of a
TTL gate equal 2.4 volts? Several conditions have to
exist simultaneously. For a military grade part (_55°C
to +125°C) the "1" level output will equal 2.4 volts,
when VCC = 4.5 volts, Vin(O) = 0.8 volts, lout = 400f.lA
and the ambie.nt temperature is -55°C, Remember the
25°C value und~r the conditions of Vin(O) = 0.4 volts,
lout = 0 is VCC - 1.4 volts. The temperature coefficient
of a forward biased diode is approximately -2 mvtC.
Going to _55°C will then degrade the "1" level by
(25°C .• (_55°C)) x 2 mvtC = 0.16 volts or
Vout (1)/-55°C = VCC - 1.56 volts. At VCC:= 4.5 volts
Vout (1 )e55 e e = 4.5 - 1.56 = 2.94 volts. As the input
"0" level degrades to 0,8 volts transistor 02 starts turn·
ing on causing a voltage drop of IC2 x 1.6K to further
degrade the output. All these affects combine to pro·
duce a worst case "1" level output of 2.4 volts. If a "1"
level of VSS - 1.5 volts must be guaranteed, under all
the above condition, the TTL gate by it;elf can not
drive the MM4262/MM5262 inputs.

<1>2 - Reads information from selected cells.
<1>3 - Writes information into selected cells.
II. Memory System Application of
the MM4262/MM5262
A. Inteliace ,
In applying the MM4262/MM5262 device to any system
three distinct types of interface must be considered. The
inputs, the output and the clocks each has unique inter·
f.ace requirements.
The inputs are TTL compatible. Let's look in detail at
what "TTL compatible" means. It does not mean that
the user can drive the MM4262/MM5262 inputs with any
TTL gate without giving it another thought. "TTL com·
patible" means that the MM4262/MM5262 can be driven
by TTL, if done properly, without the need of voltage
translation.

11-68

One solution, that will absolutely guarantee that the
VSS - 1.5 volts "1" level requirement is met, with ample
noise margin, is to use a resistor connected between the
TTL output and the VSS supply. The penalties that are
paid for this are increased number of components and a
slight increase in power. The TTL output will pull to the
VSS supply with an RC time constant of the pull up
resistor and the capacitance of the line, after the
maximum TTL "1" level has been reached. Figure 4
shows the form the TTL output would take when going
from a "0" to a "1". There would be no appreciable
difference between the "'" to "0" transistion with or
without the pull-up resistor. The pull-up resistor should
be selected to meet speed requirements and at the same
time keep power dissipation and load on the TTL gate
within allowable limits. Since most manufacturers of
standard 54/74 TTL specify speed with 50 pF load,
eight MM4262/MM5262 device inputs (8 x 7 pF ~ 56 pF)
could be driven by a single 54/74 device. If more drive
capability is required, other devices such as the OM7096/
8096 hex Tri·State ® inverters are capable of driving
twice the capacitance that a 5404/7404 can drive, with
the same rise time.

in package count. It performs both the function of
converting current to TTL levels aswell as increasing fanout.
The OS1605/3605 family and the DS3625 sense ampli·
fiers are recommended for use with the MM4262/
MM5262. The OS3625 is a dual sense amplifier and
incorporates a latch. The OS160512605 family is a hex
sense amplifier. All have Tri-State ® outputs for bus
interface capability.
The clock signals for the MM4262/MM5262 have three
requirements which have the potential of generating
problems for the user. These requirements, highspeed,
large voltage swing and large capacitive loads, combine
to provide ample opportunity for inductive ringing on
clock lines, coupling clock signals to other clocks and/or
inputs and outputs and generating noise on the power
supplies. All of these problems have the potential of
causing the memory system to malfunction. Recognizing the source and potential of these problems early in
the design of a memory system is the most critical
step. The object here is to point out the source of these
problems and give a quantitative feel for their magnitude.

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Damping the clock driver by placing a resistance in series
with its output is effective, but there is a limit since
excessive resistance will slow down the rise and fall time
'of the clock signal. Because the typical clock driver can
be much faster than the worst case driver, the damping
resistor serves the useful function of limiting the minimum rise and fall time. This is very important because
the faster the rise and fall times the worse the ringing
problem becomes. The. size of the damping resistor varies
because it is dependent on the details of the actual application. It must be determined empirically. In practice
a resistance of 10n to 20n is usually optimum.

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Limiting the inductance of the clock lines can be accomplished bv minimizing their length and by laying out
the lines such that the return current is closelv coupled
to the clock. lines. When minimizing the length of clock
lines it is important to minimize the distance from the
clock driver output to the furthest point being driven.
Because of th is, memory boar<;fs are usuallv designed
with clock drivers in the center of the memorv arrav,
rather than on one side, reducing the maximum distance
by a factor of 2.

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Using multilayer printed circuit boards with clock lines
sandwiched between the VDD and VSS power plains
minimizes the inductance of the dock lines. It also
serves the function of preventing the clocks from
coupling noise into input and output lines. Unfortunately multilayer printed circuit boards are more expensive than two sided boards. The user must make the
decision as to the necessity of multilayer boards. Suffice
it to say here, that reliable memory boards can be
designed using two sided printed circuit boards. The 16K
words x 10 bits memory board described inthe example
at the end of this application note demonstrates this.

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FIGURE 7. Schematic 011/2 050056

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The recommended clock driver for use with the
MM4252/MM5262 is the DS0056/DS0056C dual clock
driver. This device is designed specifically for use with
dynamic circuits using a substrate, VBB supply. Typically
it will drive a 1000 pF load with 20 ns rise and fall times_
Figure 7 shows a schematic of a single driver.

-IAMP' _ _ _ _ _ __

FIGURE 8. Clock Waveforms (Voltage and Currend

In the case of the MM4262/MM5262 V+ is +5 volts and
VBB is +8.5 volts. VBB should be connected to the VBB
pin shown in Figure 7 through a 1 K resistor. This allows
transistor 08 to saturate pulling the output to within a
VCE(SAT) of the V+ supply. This is critical because as
was shown before the VSS - 1,0 volt clock level must
not be .exceeded "t any time .. Without the VBB pull up
on the base of 04 the output at best will be 0.6 volt
below the V+ supply and can be 1 volt below the V+
supply reducing the noise margin or this line to zero.

As can be seen the current is significant. This current
flows in the VDD and VSS power lines. Any significant
inductance in the lines will produce large voltage transients on the power supplies. A bypass capacitor, as
close as possible to the clock driver, is essential in minimizing this problem. This bypass is most effective when
connected between the VSS and VDD supplies. A bypass
capacitor for each DS0056 is recommended. The size
of the bypass capacitor depends on the amount of
capacitance being driven. Using a low inductance
capacitor, such as a ceramic or silver mica, is most effective. Another helpful technique is to run the VDD and
VSS lines, to the clock driver, adjacent to each other.
This tends to reduce the lines inductance and therefore
the magnitude of the voltage transients.

Because of the amount of current that the clock driver
must supply to its capacitive load, the distribution of
power to the clock driver must be considered. Figure 8
gives the idealized voltage and current waveforms for a
clock driver driving a 1000 pF capacitor with 20 ns rise
and fall time.

11-70

»z
The output current of the clock driver during the transition from high to low or low to high may be as high as
1_5 amps when driving a large capacitive load_ During the
transition from high to low this current is also conducted
through the V- lead. If the external interconnective Vwire between the clock driver and the circuit driving the
clock driver is electrically long, or has significant DC
resistance, the current transient will appear as negative
feedback and subtract from the switching response. To
minimize this effect short interconnecting wires are
necessary and high frequency power supply decoupling
capacitors are again required.

The output is current, so it is more meaningful to
examine the current that is coupled through a 1 pF
parasitic capacitance. The current would be:

CD

en

CS·
::::I

:r
CC

While discussing the clock driver it should be pointed
out that the DS0056 is a relatively low input impedance
device. It is possible to couple current noise into the
input without seeing a significant voltage. Since this
noise is difficult to detect with an oscilloscope, it is
often overlooked.

This has been a hypothetical example to emphasize that,
with 20V fast rise/fall time transitions, parasitic elements can not be, neglected_ In th is example 1 pF of
pa;asitic capacitance could cause system malfunction,
because a 7404 without a pull up resistor has typically
only 0.1 volw of noise margin in the "1" state at 25°C.
Of course it is stretching things to assume that the
inductance, L, completely isolates the clock transient
from the 7404. However, it does point out the need to
minimize inductance in input/output as well as clock
lines.

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CC

On the other hand Read Access Ti me, T A CC2' is an
MM4262/MM5262 characteristic. For the MM5262 it is
specified as 195 ns maximum and 150 ns typical. This
simply means that a typical MM52$2 has a T ACC2 of
150 ns and no MM5262 has an access of greater than
195 ns.
Other parameters, such as T ACC1' are dependent on
both system generated timing (T AS and T 121 and
MM4262/MM5262 characteristics (T ACCll. T ACC2
maximum is obtained by setting TASand T 12 to their
minimum and T ACCl to its maximum.

,

c

C

Clock coupling to inputs and outputs can be minimized
by using multilayer printed circuit boards, as mentioned
previously, physically isolating clock lines and/or running
clock lines at right angles to input/output lines. All of
these techniques tend to minimize parasitic coupling
capacitance from the clocks to the signals in question.

CD

The timing diagram in Figure 2 defines the critical timing
parameters on the MM4262/MM5262. Timing parameters
are either gen'erated by the system or controlled by the
physical characteristics of the MM4262/MM5262. There
is sometimes confusion regarding the definition of maximum and minimum for these parameters. For instance,
the .jJl clock pulse width, T lPW, is generated by the
system and for the MM5262 has a minimum value of
95 ns and a typical value of 70 ns. It does not sound
correct to have the typical value less than the minimum
value. This specification simply means that the typical
MM5262 will function properly with a Tl PW of 70 ns
but a T 1 PW of at least 95 ns must be suppl ied if all
MM5262 devices are to function properly'.

Cc
1
V ; 20V x - - - ; 20V x - - ; 0.35 volts
CL + Cc
56 + 1

,l

3:

B. System Timing

Lastly the clock lines must be considered as noise
generators. Figure 9 shows a clock coupled through a
parasitic coupling capacitor, Cc ' to eight data input lines
being driven by a 7404. A parasitic lumped line inductance, L, is also' shown. Let us assume for the sake of
argument, that Ccis 1 pF and that the rise time of the
clock is high enough to completely isolate the clock
transiem from the 7404 because of the inductance, L.
With a clock transition of 20 volts the magnitude of the
voltage generated across CL is:

,1404

This exceeds the total output current swing so it is
obviously significant.

In considering clock coupling it is also important to have
a detail knowledge of the functional characteristics of
the device being used. As an example, for the MM4262/
MM5262, coupling noise from the ¢2 clock to the
address lines is of no particular consequence_ On the
other hand the address inputs will be sensitive to noise
coupled from the ¢ 1 clock.

An excellent source of information on MOS clock drivers
is Application Note AN-76, Applying Modern Clock
Drivers to MOS Memories. AN-76 is of general application and it is recommended that the memory designer
be familiar with it.

~

tc

V

When setting up the system timing adequate margins
must be maintained such that under worst case conditions all of the timing requirements are met. The main
point to consider in establishing these margins is the
variation in propagation delay of the components driving

Tel

Vss

FIGURE 9. Clock Coupling

11-71

w

the MM4262!MM5262. An example will best serve to
illustrate the type of problem that must be considered.

From table 2:
T3(min) - T 2(max) ; 11 - 12; -11 ns

Let us look at the. timing of the rising edge of '/Ij and
address inputs to the RAM. As we saw before it is
critical to maintain address setup and hold times
(T AS and T AH) for proper operation. Figure 10 shows
the logic diagram and timing for this example. Table 2
gives the minimum and maximum propagation delays to
AO and 4>1'

IN B to 4>1

tpd 1

5 ns

22 ns

tpd 0

3 ns

15 ns

tpd 1

12 ns'

35 ns'

tpd 0

11 ns'

34 ns'

Substituting from table 2 gives:
T1AH + 3 ns - 34 ns ?90 ns
or
TIAH ;;;>59 ns
With the estimated worst case time of Table 2, TIAH,
input address hold time must be at least 59 ns.
'

Table 2

This example demonstrates how the memory system
designer must account for variations in propagation
delays of logic elements used to drive the MM4262!
MM5262. As the details of the .external logic vary the
determination of critical timing paths also vary. Some
tracking of delays in this logic can usually be anticipated.
In the above example we have assumed none. Tracking
of delays will produce, in general, a faster system. As
system performance depends more and more on com·
ponent tracking to reach speed goals the risk of failure
also increases. The memory designer, with knowledge
and experience, must trade off this improved .performance against risk,

'AM5262

.><>----..+-----\ ••

"

t/GO~mll4

"'~
1{60M74114

I12D511056

IN,

'N.

is well.

The worst case conditions for T AH occur when the 'h
delay is maximum and the Aodel~y is minimum. From
Figure 2:

"Estimated Using DS0056 Data Sheet

IN,

> -12 ns all

Maximum

Minimum

INA to AO

Theretore, since -11 ns

C. Refresh Requirements

T".
~TAH

In section I, detail description of operation of MM4262!
MM5262, the need for restoring or "refreshing" the
information stored in the RAM was indicated_ The
internal leakage is such that each cell of a MM5262
must be refreshed at least every 2 milliseconds and the
MM4262 at least every 1 millisecond_ Since thi! RAM
refreshes on a rOw basis (32 rows) refresh could be
accomplished by applying 32 4>3 clocks every .2 ms (1 ms
f6r MM4262), One 4>3 clock for ~ach row_

___

'.
FIGURE 10,

In this case, assuming there is no tracking of delays, the
worst case situation will Occur for TAS when theci>l
delay is minimum and the AO delay is maXImum, From
Figure 2:

Although address inputs AO through A4, row addresses,
must clearly be defined during refresh, it is also necessary
that normal set up and hold times be observed for the
column addresses, A5 through A1 0, A reasonable alternative is. to force them to a logic "1" or "0" state and
sequence AO thro'ugh A4 through their 32 states"lf it is
more convenient to let A5 through Al0 vary, TAS and
T AH must be observed on those addresses during refresh,

Setting T lPW at its minimum allowable value gives:
T AS ; T3(min) + 95 ns - T 2(max) ;;;> 80 ns
T3(min) - T 2 (max);;;> -15

rlS

11-72

»

z

D. Power Considerations
Power consumed by a memory system using the
MM4262/MM5262 can be divided into four categories:
(1) Power required for peripheral circuitry, (2) Clock
power, (3) dc power required by the MM4262/MM5262
and,. (4) ac power required by the MM4262/MM5262.

'1

-~~

D

TCyc=840M

Lr

.

'5V

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m

US'
::J

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CO

\

0,

Calculation of peripheral circuit power, assuming it is
TTL, is straight forward and won't be described here.
Clock power, which is dissipated almost entirely in the
ciock driver, is completely described in application note
AN-76 mentioned previously. Again it is recommended
that the memory designer be familiar with this applica·
tion note.

i:

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s:

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In describing power consumed by the MM4262/MM5262
the terms dc and ac power should be defined. When
there is a resistive path for the current it is termed dc
power, even though the current may be switching. When
there is a capacitive path for the current it is termed ac
power. These are not conventional definitions but it is
necessary to make some distinction between the two
types of current. DC power is proportional to the duty
cycle of the clocks while AC power is proportional to
the frequency of the ciocks.

/II

1S0mA

C
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1BOmA

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SOmA

/;'--.OmA _

-

200

Figure 11 shows I DO for a typical MM5262 operating at

T A = 25° C with a cycle of 840 ns. As can be seen a large
current transient, 150 mA peak, occurs during the 1
clock time. Current during 1 clock time is composed
of de and ac current, T.he dc current, 20 mA, is approxi·
mately constant throughout the It>, clock interval. The
ac current results from precharging internal capacitive
nodes dU,ring the 1 clock time. The remainder of the
currents are basically a combination of ac and dc
currents.

.J

........
- - - -_ _ _ _ _

n~

4000'

600n$

800ns

s:
s:

U1
N

0'1
N

The primary purpose for showing the 100 current waveform is to point out the magnitude of the current
transient during 1 time. If the worst case current is
calculated using the above equation, with worst case
value for A, Band C with T CYC = 635 ns we get:

100 max = 3 mA + .1.7 mA + 15.7 mA

= 20.4 mA

Note 17, on the MM4262/MM5262 data sheet, gives an
approximate relationship for calculating 100 , This rela·
tionship is:

The initial ac transient accounts for approximately 77%
(15.7/20.4) of the total power dissipation of the RAM.
In addition to the 100 current there is also a current
transient due to the input clock .capacitance of ¢1 that
must be considered. With 20 ns rise time on the 1 clock
this current is:

-A x
' T-1PW
T 2PW
I 00. + Bx - + C x1000
- -ns
TCYC
TCYC
TCYC
With the aid of Figure 11 the terms A, Band C can be
readily identified.

I = 50 x 10- 12 farads x 20 volts/20 x 10- 9 sec

The A term is the value of the dc current during the 1
clock interval, T 1PW' The resulting average current is
simply A times the duty cycle (A x T 1 PWiT CYC). The
B term is the same th ing for the 2 clock interval, T 2PW.

= 50 mA

The purpose of pointing out all these transient currents
and their magnitude is to demonstrate the need' for using
bypass capacitors with the MM4262/MM5262. If there is
significant inductance in the VDo, VSS and/or VSS
lines, serious voltage transients will result unless sufficient bypass capacitors are used. Requirements vary with
actual application, but 0.1 JlF, from VOO toVSS and
from VOO to VSB' for every other RAM is usually
sufficient. Again, since ,bypass capacitors are attempting
to defeat line resistance and/or inductance, it is
important to place them physically as close as possible

The C term accounts for the shaded area, QC in Figure
11. QC is the amount of charge transferred .to the
internal node capacitance each cycle. Therefore the
amount of charge per unit time, I, is: I = Qc/TCYC'
In the above formula for 100, C = Qc/10- 6 sec. This
corresponds to an on chip capacitance of approximately
500 pF with which the chip bypass capacitors must
charge share.

11-73

ID

Clock lines are by far the worst noise generators. Their
effects can be minimized by using series damping
resistors to guarantee that the clock voltage transitions
are no faster than is absolutely necessary.

to the RAMs they are intended to bypass. Using one
centrally located capacitor is effective for decoupling
transients generated on one board from getting into
another board, but usually will not help decoupk transient internal to the board.

CI
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CI

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~
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.q.
.q.

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«

Figure 12 gives a printed circuit pattern for laying out a
memory array using the MM4262/MM5262. This pattern
has been used successfully on RAM boards of up to 16K
words by 10 bits.

For techniques of minimizing total system power the
reader is referred to application note AN-a6. A Simple
Power Saving Technique for the MM5262 2K RAM.
AN:S6 explores the use of dock decoding to minimize
the number of clocks that must be applied. It is easy
to see from the above discussion that this could produce
significant power savings since an undocked RAM draws
only 1 COilA from the VDD line.

III. A 16K words x 10 bits Memory Application
Example
The MM4262/MM5262 has a wide variety of applications. One example is an 16K words x 10 bits memory
board developed by National Semiconductor's Memory
SYstems Division. Photographs of the memory board are
included.

E. Printed Circuit Layout Conside.rations
All of the consideration in laying out printed circuit
boards for RAMs center around minimizing the inductance of lines and capacitance coupling from one line to
another.

II II

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II

I~II

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I I l.. ,...~ I I~. ~
I

I!

C'HIPSElECT

110111
I I.

,

I I

I

3::"i+,Tll:r=

Capacitive coupling is minimized by physically isolating
or shielding noise sources. Shielding using multilayer
printed circuit boards is probably the most effective but
is also the most expensive. Physical isolation can be
accomplished by running sensitive Iines such as the data
out line at right angles to the clocks and addresses.

V50
READ/WRITE

ClOCK,

~!i i~i ii*~;:::
~ii
i~i !i*~~·
~
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Inductance can be minimized by keeping line lengths as
short as possible. Also running a line and the return for
the line close together will reduce the effective induct·
ance of the line. The effect of inductance on power
supply lines can be reduced with the use of bypass
capacitors. This solution is, of course, not acceptable for
data or clock lines.

I

J I

I

I

I I

AU

~AIO

II
II

II I
II I

VSB

Voo DATA DATA Vss

our

I II
I II
IN

FIGURE 12.

11-74

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,.L-.
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______ ....:.--1

------1
I

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11-75

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11-77

~

App Notes/Briefs

NAnONAL

TRIG FUNCTION GENERATORS
Accuracy is the major design variable of trigono-'
metric lookup tables built with MaS read-only
memories. Only a. few ROMs are needed for most
practical applications, but accuracy can be made
to increase very rapidly with memory capacity if
interpolation techniques are used.
'For instance, without interpolation a single
1024-bit ROM can store 128 angular increments
and generate an 8-bit output that will be better
than 99.9% of the handbook value (Table 1).
BINARV

DECIMAL

OUTPUT

SINE

D

.00000000

.00000011
.00000110

3

0.7
1.4
2.1

.00001001

0.000
0.012
0.023
0.035

127

89.3

11111111

0.996

ADDRESS

0
1
2

OEGAEE\S

(al

TABLE 1. MM422BM/MM522BM Sine Function Generator

If one simply cascaded ROMs to improve input
resolution and output accuracy for a high·accuracy
trig solution (X=sin 0) as in Figure 1, large numbers .of ROMs might be needed. This 24-ROM
system stores 2048 12-bit values of sin x (or other
trig functions!. giving angular resolution of 1 part
in 2" (0.05%) and output accuracy of 1 part in
2'2 (0.024%). The system in Figure 2 has the
same resolution and' is accurate to the limit of its
12 output bits (0.024%), wh ich makes it just as
good. But it only requires four1024-bit ROMs and
three 4-bit TTL full adders, so it only costs about
one-fifth as much as the more obvious solution of
Figure 1.

~

,..--..,

1

Instead of producing x = sin 0, the Figure 2 sYstem
divides the angle into two parts and implements
the equation
x = sin iJ = sin (M + L)
= sin M cos L + cos M sin L
It can be programmed for any angular range.
Assume the range is 0 to 90 degrees and let M be
the 8 most significant bits of 0 and L be the 3 least
significant bits of e (8 being the 11-bit input
angular increments, equal to 90 0 /2048, or
0.044 deg.) as in Table 2.
With an 8-bit address, the three 256x4 ROMs will
give the 12-bit value of sin M at increments of
M = 900 /28, or 0.352 deg. The cos L can only vary
between 1 and 0.99998. So we assume cos L=l
and store values of sin M at 0.352 deg. resolution

(bl
FIGURE 1. Conventional 2048-lncrement Sine Table Uses
24 ROMs

11-78

3:

in the top three ROMs, reducing the equation to

Since we are using an approximation, accuracy is
not quite as good as the Figure 1 system. The
additional error term is cos L, assumed 1 but
actually is a variable between 1 and 0.99998. At
every eighth increment, L is zero, making cos M

sin (J = sin M + cos M sinL
Values of the second term are stored in the fourth
ROM. The maximum value of the second term in
the above equation can only be cosMsin L
= 0.00539 where cos Mm • x = 1, sin Lmax
= 0.00539. This is the maximum value to be added
to sin M above. Only the five least significant bits
of a 12-bit output are needed to form the maxi·
mum output, so an MM522 is used in its 128x8
configuration.

M
M.

ADDRESS

L

0

0
1 L

1

2
3
1

5

1 0

6

1 1 0

7

1 1 1

.r-'6
32

1 0

o

0

o

0

1

1 0
1

o

0

o
o

0 0

o

0 0

o

0 0

64

1

128

1 0 0

0 0

o

o
o
o

0

o
o
o

0 0
0
0 0
0 o 0 0
0 0
0 0 o 0
0 0 0 0 o 0 0

1 1 1

1

1 1

1

256

1 0

512

1024
2048·1

0.044"

0
1

1

8

OUTPUT

o

4

v--.. 9

~A~R'I

=

1 0
1 1

1

o

1 1

1

1 1

,-.
TABLE 2. Programming of 2048-lncrement Sine Table

,-,

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-to
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sin L=O, and sin x=sin M to 12-bit accuracy. Then
the error rises to a limit of near 0.002% at -every
eighth increment where L is 0.352-0.044. This
error can be halved by adjusting the fourth ROM's
output so that

CARRYOUTPIJT
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DM82Bl

ADnER

r"

If five ROMs are used-four MM521'sand all eight
outputs of the MM522-15-bit accuracy can be
achieved, and thus improving the accuracy by a
factor of eight. The resolution could also be
smaller, of course, if the angular range were
smaller as in an application involving a sensor with
a limited field of view. Variations of the system
could be used to space the increments irregularly
to compensate for sensor nonlinearities, to improve accuracy in specific angular ranges.

3LEASTSIGBITS_j
lIla.iMOCE)

MMS22 in 128 X 8 MODE pnerates cos (M" - 2.8)
sin L 3 MM521 generate sin M
sin 0 '" sin M + cos (M A - 2.B) sin l

This example has a binary fraction output, like the
sine function generator in Table 1. For instance,
the 8·bit output at the 64th increment representing sin x = sin 45° is 10110101. This equals
1 X T' + 0 X 2- 2 + 1 X 2- 3 + 1 X T4 + 0 X T S + 1 X 2- 6 + 0 X 2- 7 + 1 X 2- 8 , which reduces to
1811256 or 0.7070_ Handbooks give the four-place
sine of 45° as 0.7071, so at this increment the
output is accurate to approximately 0.01 %. This
table, the MM422BM/MM522BM, is used in fast
Fourier transform, radar, and other signal-pro·
cessing applications.

FIGURE 2. Four·ROM Lookup Table Generates 2048
Values of Sin x-by Interpolation T,echnique.

Let the 4 most significant bits of M be called M4
and the angie at these increments be Xm = 90° 124
= 5.63 deg. Sin L (the 3 least significant bits of (J)
has the same maximum as before and cos M4 has a
maximum of cos 5.63 deg. = 0.99517, and continuing as follows:
cos (11.26) = 0.98076
cos (16.89) = 0.95686
cos (84.37) = 0.09810

Other standard tables that are available off the
shelf include an arctan generator, several code
generators (EBCDI C to ASCII, BCD toSelectric,
and Selectric to BCD) and ASCII·addressed char·
acter generators for electronic, electrical and elec·
tromechanical display and printout systems. All
interface with TTL logic and operate off 12·volt
power supplies. Write for data sheets, or use one of
our programming tables to jot down any special
input-output logic functions you need.

through the 16 increments of M4 . Now
sin (J = sin M + cos M4 sin L
and the appropriate cos M sin L values are stored
in the fourth ROM. In effect, we have divided the
0° to 90° sine curve into 16 slope sectors with M.,
each sector into 16 subsections with M, and each
subsection into'8 interpolation segments with L.
11-79

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App Notes/Briefs

NA110NAL

U)

CD

MASK 'PROGRAMMING SPECIALIZES
MOS SHIFT REGISTER DESIGNS
There are enough storage cells, 110 stages, clock
and power supply lines on each MM4007 chip
to make up to tWo 100-bit registers. The minimum
length of each register half, MA and Me, is 20 bits.
The programmable parts, PA and Pe , may be 0 to
80 bits long. Lengths need not b'e equal. For
instance, register A may be 29 bits and register l3
76 bits (PA = 9, PB = 56).

A quick, economical way of customizing MOS
shift register bit lengths is programming the metallization mask, the mask that defines the thin-film
wiring pattern etched on the silicon wafer. Metallization etching is the most convenient process step
to specialize because it is consistent from wafer
to wafer and is the last major process step before
testing.
Utilizing this technique, National Semiconductor
has developed two variable-length dynamic MOS
register designs. Both of them, MM4007/MM5007
and MM4019/MM5019, are bipolar compatible.
Dual registers 20 to 256 bits long, single registers
40 to 512 bits Icing, and a variety of taps and
pinouts provide the system designer with a method
of obtaining custom length shift registers ,quicklY
and at reasonable cost.

V"

TOP VIEW

FIGURE 1. Dual Shift Registers

Up to metal masking, wafer design and fabrication
are standardized. No time is lost-or money spentin developing custom arrays or tuning up the
process. Automatic test systems further reduce
turnaround time and production costs.

An MM4019/MM5019 chip is similarly organized,
except that MA and Me are 40 bits and PA and
Pe vary from 0 'to 216 bits. Again, lengths may
be unequal, such as 240 bits in the A half and 136
bits in the B half.
Clock and supply line pin locations are standardized, but 110 pinouts, are selectable., The I/O
terminals on the chip may bll bonded to package
pins which are more convenient for the PC board
layout.' For example; a couple of board feedthroughs might be eliminated by bonding the A
register input to Pin 7 (rather than Pin 1) if data
comes in fro'm the right and exits on the left. Or,
A and B co~ld share an input pin when they have
the same signal source.

Programming the metallization mask mainly involves routing signal connections past selected
storage cells to adjust total register length to the
desired number of cells. Wire-bonding changes
provide output tap options.
DUAL REGISTER DESIGNS

Basically, each of the variable-length types is a
dual register (Figure 1 and Table lAl.

TABLE 1 Register Length Optians

M
(BITSI

MM4007/MM5007
P
TOTAL
(BITS)
(BITS)

M
(BITS)

MM4019/MM5019
P
TOTAL
(BITS)
(BITSi

A. DUAL REGISTERS
A Register

20

o to 80

20 to 100

40

Oto 216

40 to 256

B Register

20

Ot080

20 to 100

40

Oto 216

40 to 256

MA+Ma

PA + Pa

MA+Ma

PA + P a

80

Oto 432

B. SINGLE REGISTERS
40

o to 160

40 to 200

80 to 512

C. TAPPED SINGLE REGISTERS
Total register length same as single registers with tap locations determined by :ither half of the dual registers.

11·80

SINGLE-REGISTER OPTIONS
Since clock rates are synchronized by the common
clock inputs, the registers may also be serially
connected inside the package, as diagrammed in
Figure 2. One output is internally connected to
the other input.

....

.;.
v~

This extends the maximum length of an MM4007/
MM5007 to 200 bits and the MM4019/MM5019
maximum to 512 bits. However, each half still
has the same minimum, so the minimums become
40 and 80 bits, respectively (Table 18). Again,
the customer specifies the most convenient I/O
pin connections.

TOP VIEW

FIGURE 3.

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:;II:"

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~ to VI/>H transition and the start
of a tP2 VI/>H to VI/>L transition. The same spacings
apply, when tP2 preceeds tP I .

Partial Bit Times T1I\I, TOUT: The time between
leading edges of clocks, measured at the V¢H
levels. TIN is the time between the leading edge of
tPlN and the leading edge of tPOUT. TOUT is the
time between the leading edge of : The time delay between
the 10% and 90% voltage points on the clock pulse
as it travilrses between its logic VI/>L and logic VI/>H
levels.

Output Source Current: The current which flows
out of the output terminal of the register when the
output is a logical High level. Conventional current
flow is assumed. ,

Clock Pulse Falltime, tfl/>: The time delay between
the 10% to 90% voltage points on the clock pulse
as it traverses between its logic Vt/>H and logic Vt/>L
levels.
Clock Pulse Width, L
or V~ H) which the .clock driver must assume to
insure proper device operation.

VGG Current Drain: The average current flow out
of the VGG terminal of the package with the out·
put open circuited.

Clock Control Setup Time, 1'cs: The time prior to
the clock Low to High transition at which the
clock control must be at its desired logic level.

Power Supply Voltage, VGG: The negative power
supply potential required for proper \levice operation; referenced to V55'
Power Supply Return, Vss: The Vss terminal is
the reference point for the device. It must always
be the most positive potential applied to the
device.

Clock Control Hold Time, fch: The time after the
High to Low transition for which the clock control
must be held at its desired logic level.

Data Setup Time, tm:

The time prior to the clock
High to Low transition at which the data input
level must be present to guarantee being clocked
into the register by that clock pulse.

Vss Current Drain: The average current flow into
the Vss terminal of the package. It is equal to the
sum of the IGG and 100 currents.

Data Pulse Width, tdw: The time duririg which the
data pulse is in its VIH or VIL state.

Power Supply Voltage, V DO: The negative power
supply potential required for proper device opera·
tion, referenced to V55 •

Data Hold Time, t,u,: The time after the clock
High to' Low transition which the data input level
must be held to guarantee being clocked into the
register by that clock pulse.

Clock Input Voltage Levels, Vt/>H Vt/>L: The voltage
levels (logic "1" or "0") which the clock driver
must assume to insure proper device operation.

Data Input Voltage Levels:, The voltage levels
(logic VI Lor V IH ) which the data input terminal
must assume to insure proper logic inputs.

3'

;t

Data Output Voltage Levels, VOH, VOL: The output voltage levels (logic "I" or "0") which the
output will assume with a specified load connected
between output and V55 line.

.....e
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Data Input Voltage Levels, VIH VI L: The voltage
levels (logic "1" or "a") which the data input
terminal must assume to insure proper logic
inputs.

Control Initiate Window: The time in which a load
command signal must be appl ied to affect bit time
tn. This time extends from the start of ter to the
start of teo.

Control Release Time, tor: The maximum time
that a load command signal can be changed prior
to the VrpL to VrpH transition of the output clock,


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Package 17
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PIN NO.1 INOENT

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28-Lead Molded DIP IN)

VIII

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IX

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Package 25

10-Lead TO-5 Metal Can Package (H)

12-Lead TO-S Metal Can Package (G)

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Package 26

Package 27

INCHES TO MILLIMETERS CONVERSION TABLE
INCHES

MM

INCHES

MM

INCHES

MM

0.100
0.200

2.54
5.08

0.001

0.0254

0.010

0.254

0.002

0.0508

0.020

0.003

0.0762
0.1016

0.030
0.040

0.508
0.762

0.1270

0.050

1.016
1.270

0.1524
0.1778

0.060
0.070

1.524
1.778

0.2032

0.080
0.090

0.004
0.005
0.006
0.007
0.008
0_009

0.2286

x

II.

O.019--i~

14-Lead Flat Package (W)

14-Lead Flat Package (F)

10-LeadFlat Package (F)

0.'15

0.300

7.62

00400

10.16
12.70

2.032

0.500
0.600
0.700
0.800

20.32

2.286

0.900

22.86

15.24
17.78
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