1976_National_TTL_Databook 1976 National TTL Databook

User Manual: 1976_National_TTL_Databook

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National Semiconductor

Section 1 - 54/74551 DEYICEs
Connection Diagrams • Electrical Tables
Section 2 - 54/74 MSI DEYICEs
Section 3 - National Semiconductor PROPRIETARY DEYICEs
Section 4 - National Semiconductor ADDITIONAL DEYICEs

~

NAnONAL
Manufactured under one or more of the following U.S. patents: 3083262, 3189758, 3231797, 3303356, 3317671, 3323071, 3381071, 3408542,3421025, 3426423, 3440498, 3518750.3519897,3557431,3560765,
3566218,3571630,3575609,3579059,3593069, 3597540, 3607469, 3617859, 3631312, 3633052, 3638131, 3648071, 3651565, 3693248.
National does not assume any responsibility for use of

© 1976 National Semiconductor Corp.

any

circuitry described, no circuit patent licenses are implied; and National reserves the right, at any time without notice, to change said circuitry.

•

~

-Alpha-Numerical Index

TTL Data Book
DEVICE

MIL

2502
2503
2504
5400
54HOO
54LOO
54LSOO
5401
54HOl
54LOl
54LSOl
5402
54L02
54LS02
5403
54L03
54lS03
5404
54H04
54L04
54 LS04
5405
54H05
54L05
54LS05
5406
5407
5408
54H08
54L08
54LS08
5409
54L09
54LS09

930
932
933
935
936
937
944
945
946
948
949
957
958
961
962
963
1800
1801
2502C
2503C
2504C
7400
74HOO
74LOO
74LSOO
74S00
7401
74HOl
74LOl
74LSOl
7402
74L02
74LS02
74S02
7403
74L03
74LS03
74S03
7404
74H04
74L04
74LS04
74S04
7405
74H05
74L05
74LS05
74S05
74D6
7407
7408
74H08
74L08
74LS08
7409
74L09
74LS09

DEVICE

PAGE NO.

COML

4-1
4-1
4-1
4·1
4-1
4-1
4-1
4-1
4-1
4·1
4-1
4·1
4-1
4·1
4·1
4-1
4·1
4-1
4-6
4-6
4·6
1-1,1-36
1-1,1·36
1-1, 1-36
1-1, 1-36
1-1,1·36
1-1, 1-38
(1,1·38
1-1, 1·38
1-1,1-38
1-2,1·40
1-2,1-40
1·2,1-40
1·2,1-40
1-2,1·38
!
1-2,1-38
1·2,1-38
1·2,1·38
1-2,1·36
1-2,1-36
1-2,1·36
1-2,1-36
1-2,1·36
1-3,1-38
1:3,1-38
1-3,1·38
1·3,1·38
1-3,1-38
1·3,1·42
1·3,1-42
1·4,1·44
1·4, 1-44
1-4,1-44
1-4,1-44
1·4,1-46
1-4,1-46
1-4,1·46

I

MIL

COML

5410
54H10
54L 10
54LS10

7410
74Hl0
74L10
74LS10
74S10
7411
74Hl1
74L11
74LS11
74S11
74LS12
7413
74LS13
7414
74LS14
74LS15
74S15
7416
7417
7420
74H20
74L20
74LS20
74S20
74H21
74LS21
74H22
74LS22
74S22
7423
7425
7426
74L26
74LS26
7427
74LS27
7430
74H30
74L30
74LS30
74S30
7432
74L32
74LS32
7437
74LS37
7438
74LS38
7440
74H40
74 LS40
74S40
7441A
7442
74L42A
74LS42
7445

5411
54Hll
54L11
54LSll
54LS12
5413
54LS13
5414
54LS14
54LS15
5416
5417
5420
54H20
54L20
54LS20
54H21
54LS21
54H22
54LS22
5423
5425
5426
54L26
54LS26
5427
54LS27
5430
54H30
54L30
54LS30
5432
54L32
54LS32
5437
54LS37
5438
54LS38
5440
54H40
54 LS40
5441A
5442
54L42A
54LS42
5445

DEVICE

PAGE NO.

1·4,1-36
1-4,1-36
1-4,1-36
1-4 1·36
1-4,1-36
1·5,1-44
1-5,1·44
1-5,1-44
'1·5,1-44
1·5,1·44
1-5,1-38
1·5,1·48
1-5,1·48
1-6, 1-48
1·6,1·48
1-6,1-46
1·6,1-46
1-6,1-42
1-7,1-42
1-7,1-36
1-7,1-36
1·7,1·36
1-7,1-36
1-7,1-36
1-7,1·44
1-7,1-44
1-8, '-38
1·8,1-38
1-8,1-38
1-8,1-50
1-8,1-40
1-9,1·42
1·9,1·42
1-9,1-42
1·9,1-40
1-9,1-40
1-9,1·36
1-9,1-36
1·9,1-36
1-9,1-36
1-9,1·36
1·10,1-52
1-10,1-52
1-10,1·52
1·10,1-54
1·10,1·54
1-10,1-42
1-10,1-42
1-11,1·54
1·11,1·54
1-11,154
Hl,1·54
2·1
2-3
2-3
2·3
2·6

I

MIL

COML

5446A
5447A
54LS47
5448
54LS48
54LS49
5450
54H50
5451
54H51
54L51
54LS51

7446A
7447A
74LS47
7448
74LS48
74LS49
7450
74H50
7451
74H51
74L51
74LS5l
74S51
74H52
7453
74H53
7454
74H54
74L54
74LS54
74H55
74L55
74LS55
7460
74H60
74H61
74H62
74S64
74S65
7470
74H71
74L71
7472
74H72
74L72
7473
74H73
74L73
14LS73
7474
74H74
74L74
74LS74
74S74
7475
74L75A
74LS75
7476
74H76
74LS76
74LSn
74H78
74L78
74LS78
7483
74LS83A
7485

54H52
5453
54H53
5454
54H54
54L54
54LS54
54H55
54L55
54LS55
5460
54H60
54H61
54H62

5470
54H71
54L71
5472
54H72
54L72
5473
54H73
54L73
54LS73
5474
54H74
54L74
54LS74
5475
54L75A
54LS75
5476
54H76
54LS76
54LS77
54H78
54L78
54LS78
5483
54 LS83A
5485

Note: When there are two sets of pa~e numbers, the first designates the connection diagram' page; the second indicates electrical tables.

iii

PAGE NO.

2·8
2·8
2·8
2-8
2-8
2-8
1-11,1-50
1-11, 1·50
1·12,1-56
1-12,1·56
1-12,1·56
1·12,1·56
1-12,1·56
1-13,1·50
1-13,1-50
1-13, 1-50
1-14,1-56
1·14,1-56
1·14,1-56
1-14,1·56
1·15,1·50
1·15,1·56
1·15,1-56
1·15,1·58
1-15,1·59
1·16,1-60
1·16, '·59
1-16,1·56
1·17,1-61
1-18,1·62
1-18,1·64
1-19,1-66
1·19,1-62
1·19,1·64
1-19,1-66
1·20, 1-62
1·20,1-64
1·20,1-66
1-20,1-68
1-20,1·62
1·20,1-64
1·20,1·66
1·20,1-68
1·20,1·70
2-14
2·14
2·14
1·21,1·62
1·21,1·64
1·21,1·68
2·14
1·21,1·64
'·21,1·66
1·21,1·68
2·17.
2·17
2·21

~ TTL Data Book
DEVICE
MIL
54L85
54 LS!35
5486
54L86
54LS86
5488
5489
54l89A
5490A
54L90
54LS90
5491A
54L91
5492A
54 LS'92
5493A
54L93
54LS93
5495
54L95
54LS958
5496
54LS96
54L98
54Hl03
54Hl06
54107
54LS107
54H108
54109
54LS109
54LSl12
54LS113
54LS114
54121
54LS122
54123
54L123A
54LS123
54LS124
54125
54LS125
54126
54LS126
54132
54LS132

54LS136
54LS138

COML
74185
74lS85
7486
74L86
74lS86
74S86
7488
7489
74L89A
7490A
74L90
74LS90
7491A
74L91
7492A
74LS92
7493A
74L93
74 LS93
7495
74L95
74LS958
7496
74LS96
74L98
74Hl03
74H106
74107
74LS107
74H108
74109
74LS109
74LS112
74S112
74LS113
74S113
74LS114
74S114
74121
74LS122
74123
74L123A
74LS123
74LS124
74125
74LS125
74126
74LS126
74132
74LS132
74S133
74S134
74S135
.74LS136
74S136
74LS138
74S138

Alpha-Numerical Index
DEVICE . .

PAGE NO.
2·21
2-21
1·22,1·72
1-22, 1-72
1-22,1·72
1·22, 1-72
2-25
2-28
2-89
2·30
2·30
2·30
2-34
2·34
2·30
2-30
2·30
2-30
2-30
2·36
2.36
2-36
2-39
2-39
2-42
1-23,1-74
1-23,1·74
1·23,1-62
1·23, 1-68
1-24, 1·74
1-24,1·62
1-24,1·68
1·24, 1-68
1·24, 1-70
1·25,1-68
1,25,1·70
1·25,1·68
1·25, 1-70
1-26,1-76
1-26,1·78
1·26,1·78
1·26, 1·78
1·26,1·78
2·44
1·27,1·80
1·27,1:80
1·27, 1·80
1·27,1·80
1·27,1·48
1·27,1·48
1·28,1·36
1·28,1·80
1·28,1·82
1·29,1·84
1-29,1·84
2·46
2-46

MIL

COML

54LS139

74lS139
74S139
74S140
74141
74145
74147
74148
74150
74151A
74LS151
74S151
74153
74LS153
74S153
74154
74L154A
74LS154
74155
74LS155
74156
74LS156
74157
74L157A
74LS157
74S157
74LS158
74S158
74160A
74LS160
74161A
74LS161
74162A
74LS162
74163A
74LS163
74164
74L164A
74lS164
74165
74L165A
74166
74LS168
74LS169
74170
74LS170
74173
74lS173
74174
74LS174
74S174
74175
74LS175
74S175
74176
74177
74180
74181

54141
54145
54147
54148
54150
54151A
54LS151
54153
54LS153.
54154
54L154A
54LS154
54155
54LS155
54156
54LS156
54157
54L157A
54LS157
54LS158
54160A
54LS160
54161A
54LS161
54162A
54LS162
54163A
54LS163
54164
54L 164A
54LS164
54165
54L165A
54166
54lS168
54LS169
54LS170
54173
54LS173
54174
54LS174
54175
54LS175
54176
54177
54180
54181

PAGE NO.
2·46
2·46
1-29, 1-54
2·1
2-6
2-49
2-49
2·53
2·53
2·53
2·53
2·57
2·57
2-57
2-60
2-60
2·60
2·63
2-63
2-63
2-63
2·66
2·66
2-66
2·66
2-66
2-66
2·70
2-70
2-70
2·70
2·70
2·70
2-70
2·70
2·76
2·76
2-76
2·79
2-79
2·82
2-85
2-85
2-91
2·91
2·96
2·96
2·98
2·98
2·98
2-98
2·98
2·98
2·101
2·101
2·105
2·107

DEVICE
MIL

COML

54182

74182
74S182
54184
74184
54185A
74185A
54187
74187
54L 187A
74L187A
54S189
74S189
54190
74190
54LS190
74lS190
54191
74191
54LS191
74LS191
54192
74192
54L 192
74L192
74LS192
54LS192
54193
74193
54L 193
74L193
54LS193
74LS193
54194
74194
54LS194A 74LS194A
74S194
74195
54195
54LS195A 74LS195A
74S195
54196
74196
54LS196
74LS196
54197
74197
54LS197
74LS197
54198
74198
54199
74199
54S200
74S200
54S206
74S206
54LS221
74LS221
54251
74251
54LS251
74LS251
74S251
74 LS253
54LS253
74S253
54lS257
74LS257
74S257
54 LS258
74LS258
74S258
74S260
54LS266
74LS266
54LS279
74lS279
74S280
74S281
54LS283
74LS283
54S287
74S287
54S289
74S289
54LS295A 74LS295A
74LS298
54LS298
54365
74365
54LS365
74LS365
74366
54366
54LS366
74LS366
54367
74367
54LS367
74LS367

Note: When there are two sets of page numbers, the first designates the connection diagram page; the second indicates electrical tables.

iv

PAGE NO.
2·11.3
2·113
2·116
2·116
2·122
2-122
2-125
2-128
2-128
2-128
2·128
2·133
2-133
2·133
2·133
2·133
2·133
2-140
2-140
2·140
2·144
2·144
2·144
2·101
2·101
2·101
2·101
2-148
2·148
2·154
2-157
1-30,1-76
2-160
2·160
2-160
2·163
2-163
2·165
2·165
2-165
2-165
1·31,1·40
1·31,1·84
2·168
2·170
2-173
2·17
2·177
2·179
2·182
2·184
1·32,1·86
1·32,1·86
1·32, 1·86
1·32, 1-86
1·32, 1·86
1.32,1·86

~

DEVICE
MIL

COML

54368
54LS368
54LS374
54L5386
545387
54L5395
54L5670

74368
74 LS368
74LS374
74L5386
745387
74L5395
74L5670
80L06
8090
8091
8092
8093
8094
8095
80L95
8096
80L96
8097
80L97
8098
80L98
8099
8121
81L22
8123
81L23
8130
8131
8136
8160
81L595
81L596
81L597
81L598
8200
8210
8211
8214
8219
8220
8223
8230
8280
8281
8288
8290
8291
8511
85L11
8512
85112
8520
8531
8542
8544
8546
85550

7090
7091
7092
7093
7094
7095
70L95
7096·
70L96
7097
70L97
7098
70L98
7099
7121
71L22
7123
71L23
7130
7131
7136
7160
71L595
71L596
71L597
71L598
7200
7210
7211
7214
7219
7220
7223
7230
7280
7281
7288
7290
7291
7511
75Lll
7512
75L12
7520
7542
7544
7546

Alpha-Numerical Index

TTL Data Book
DEViCE:

1·33,1·86
1·33,1·86
2·187
1·34,1·72
2-177
2·189
2·191
3-1
3·3
3-3
3·3
3-5
3-5
3-7
3-7
3-7
3-7
3-7
3-7
. 3-7
3-7
3·9
3-11
3·13
3-13
3·13
3-17
3-19
3·19
3-17
3-21
3-21
3·21
3-21
3-23
3·25
3-25
3-28
3-28
3-32
3-35
3-37
4-11
4-11
4·11
4-11
4-11
3-40
3-40
3-40
3-40
3-44
3-49
3-52
3-54
3-56
3-60

MIL

COML

7551
75L51
7552
75L52
7553
7554
75L54
7555
7556
7560
75L60
7563
75L63
75568
7570
7573
7574
7575
7576
7577
7578

8551
85L51
8552
85L52
8553
8554
85L54
8555
8556
8560
85L60
8563
85L63
85568
8570
8573
8574
8575
8576
8577
8578'
8581
8590
8595
8596
8597
8598
8599
8613
86113
86L24
86L25
86LlO
86L75
86Ll6
8678
8679
86L90
86L93
86L97
86L99
8795
8796
8853
8875A
88758
8898
8899
8280
8281
8288
8290
8291
9002C
9003C
9004C
9005C

7590
7595
7596
7597
7598
7599
7613
76L13
76L24
76L25
76LlO
76Ll5
76Ll6
7678
7679
76L90
76L93
76L97
76L99
7795
7796
7853
7875A
78758

7280
7281
7288
7290
7291

DEVICE

PAGE. NO.

PAGE NO.

MIL

3-62
3·62
3·64
3-64
3·70
3-64
3·64
3-72
3-72
3-76
3·76
~-76

3-76
3-82
3-86
3-89
3-92
3-95
3-95
3·101
3-104
3-107
3-110
3-113
3-116
3-119
3-122
3-127
3·40
3-40
3-131
3·134
3·86
3-137
3-137
3-140
3-140
3-110
3-142
3-144
3-148
3-113
3-116
3-151
3·154
3-154
3-156
3-156
4-11
4-11
4-11
4-11
4·11
4-15
4-15
4-15
4-15

9024

9300
9301
9309
9310
9311
9312
9316
9318
9322
9334
9601
9602

PAGE NO.

COML

9006C
9008C
9009C
9012C
9016C
8024
9093
9094
9097
9099
8300
8301
8309
8310
8311
8312
8316
8318
8322
8334
8601
8602

Note: When there are two sets of page numbers, the first designates the connection diagram page; the second indicates electrical tables.

v

4·15
4·15
4-15
4·15
4-15
4-17
4-1
4·1
4·1
4·1
4-19
4-22
4-24
4-27
4-33
4-24
4-27
4-36
4-38
4-40
4-43
4-46

~ TTL Data Book

Table of Contents

Alpha-Numerical I ndex _____ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
iii
TRI-STATE Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. xvi
TTL Families Comparison Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xviii
Industry Cross Reference Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. xix
Functional Index/Selection Guides. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. xxv
Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
xli

54/74 SSI-SECTION 1
DM5400/DM7400 Quad 2-1 nput NAND Gates ........... _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-1, 1-36
DM54HOO/DM74HOO Quad 2-lnput NAND Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1,1-36
DM54LOO/DM74LOO Quad2-lnputNANDGates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1,1-36
DM54LSOO/DM74LSOO Quad 2-lnput NAND Gates ... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ 1-1,1-36
DM74S00 Quad 2-lnput NAND Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . " ....... , 1-1,1-36
DM5401/DM7401 Quad 2-lnput NAND Gates with Open-Collector Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . l-t, 1-38
DM54H01/DM74H01 Quad 2-lnput NAND Gates with Open-Collector Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1,1-38
DM54L01/DM74LOl Quad 2-lnput NAND Gates with Open-Collector Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1,1-38
DM54LS01/DM74LSOl Quad 2-lnput NAND Gates with Open-Collector Outputs . . . . . . . . . . . . . . . . . . . . . . . . 1-1,1-38
DM5402/DM7402 Quad 2-lnput NOR Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ ............ 1-2,1-40
DM54L02/DM74L02 Quad 2-lnput NOR Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2,1-40
DM54LS02/DM74LS02 Quad 2-lnput NOR Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2,1-40
DM74S02 Quad 2-lnput NOR Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2,1-40
DM5403/DM7403 Quad 2-lnput NAND Gates with Open-Collector Outputs . . . . . . . . . . . . . . . . . . . . . _ ..... , 1-2,1-38
DM54L03/DM74L03 Quad 2-lnput NAND Gates with Open-Collector Outputs ......... _ . . . . . . . . . . . . . . . . 1-2,1-38
DM54LS03/DM74LS03 Quad 2-lnput NAND Gates with Open-Collector Outputs _ ...... _ ........... _ .... 1-2,1-38
DM74S03 Quad 2-lnput NAND Gates with Open-Collector Outputs ... _ ............. _ ............. _ .. 1-2,1-38
DM5404/DM7404 Hex Inverters ........... _ ... _ ....... _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2,1-36
DM54H04/DM74H04 Hex Inverters ......... _ ......... _ . _ ........ _ . . . . . . . . . . . . . . . . . . . . . _ .. 1-2, 1-36
DM54L04/DM74L04 Hex Inverters ...... _ .. _ . _ . _ . . . . . . . . . . . . . . . . . . . . . _ ............ _ ...... 1-2,1-36
DM54LS04/DM74LS04 Hex Inverters ....... _ ... _ ... _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ ........ 1-2, 1-36
DM74S04 Hex Inverters_ . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-2, 1-36
DM5405/DM7405 Hex Inverters with Open-Collector Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . .. 1-3, 1-38
DM54H05/DM74H05 Hex Inverters with Open-Collector Outputs . . . . . . . . . . . . . . . . . . . . . . . . . _ ......... 1-3,1-38
DM54L05/DM74L05 Hex Inverters with Open-Collector Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3,1-38
DM54LS05/DM74LS05 Hex Inverters with Open-Collector Outputs . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . .. 1-3, 1-38
DM74S05 Hex Inverters with Open-Collector Outputs ....... _ . . . . . . . . . . . . . . . . . . . . . . . . . _ ......... 1-3,1-38
DM5406/DM7406 Hex Buffers with Open-Collector High-Voltage Outputs . . . . . . . . . . . . . . . . . . . . . . . _ . _ ... 1-3,1-42
DM5407/DM7407 Hex Buffers with Open-Collector High-Voltage Outputs . . . . . . . . . . . . . . . . . . . _ .... _ .... 1-3,1-42
DM5408/DM7408 Quad 2-lnput AND Gates _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ ......... 1-4,1-44
DM54H08/DM74H08 Quad 2-lnput AND Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4,1-44
DM54L08/DM74L08 Quad 2-lnput AND Gates _ . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . _ .. _ ...... 1-4,1-44
DM54LS08/DM74LS08 Quad 2-lnput AND Gates . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4,1-44
DM5409/DM7409 Quad 2-lnput AND Gates with Open-Collector Outputs ..... _ . . . . . . . . . . . . . . . . . . _ .... 1-4,.1-46
DM54L09/DM74L09 Quad 2-lnput AND Gates with Open-Collector Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4,1-46
DM54LS09/DM74LS09 Quad 2-lnput AND Gates with Open-Collector Outputs ...... _ .. _ . . . . . . . . . . . . . . . 1-4,1-46
DM5410/DM7410 Triple 3-lnput NAND Gates .. _ ............. _ . . . . . . . . . . . . . . . . . . . . . . . . . _ . _ .. 1-4,1-36
DM54Hl0/DM74Hl0 Triple 3-lnput NAND Gates _ . . . . . . . . . . . . . . . . . . . . _ ... _ .............. _ .. __ 1-4,1-36
DM54L10/DM74L10 Triple 3-lnput NAND Gates .. _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ ..... 1-4,1-36
DM54LS10/DM74LS10 Triple 3-lnput NAND Gates ............. _ ..... __ . . . . . . . . . . . . . . . . . . . . . . _ 1-4,1-36
DM74S10 Triple 3-lnput NAND Gates . . . . . . . . . . . . . . _ ....... _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . _. 1-4, 1-36
DM5411/DM7411 Triple 3-lnput AND Gates . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . . . . . . 1-5,1-44
DM54Hl1/DM74Hll Triple 3-lnput AND Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5,1-44
DM54L11/DM74L 11 Triple 3-lnput AND Gates ............. _ . _ ........ _ ....... _ ... _ ... ___ . . .. 1-5, 1-44
DM54LSll/DM74LS11 Triple 3-lnput AND Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5,1:44
DM74S11 Triple 3-lnput AND.Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ ....... 1-5,1-44
DM54LS12/DM74LS12 Triple 3-lnput NAND Gates with Open-Collector Outputs . . . . . . . . . . . . . . . . . . _ . _ . _. 1-5, 1-38
DM5413/DM7413 Dual4-lnput NAND Schmitt Triggers ............. __ . _ ..... _ ... _ ...... _ ....... 1-5,1-48
DM54LS13/DM74LS13 Dual4-lnput NAND Schmitt Triggers ...... _ . . . . . . . . . . . . . . . . . . . . . . . . . __ . _. 1-5,1-48
DM5414/DM7414 Hex Schmitt Triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . __ ....... _ .......... _ ... 1-6,1-48
Note: When there are two sets of page.numbers, the first designates the connection diagram page; the second indicates electrical tables.
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Table of Contents

DM54LS14/DM74LS14 Hex Schmitt Triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6, lA8
DM54LS15/DM74LS15 Triple 3-lnput AND Gates with Open·Collector Outputs . . . . . . . . . . . . . . . . . . . .' ..... 1-6,1-46
DM74S15 Triple 3-lnput AND Gates with Open·Coliector Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,1-6,1-46
DM5416/DM7416 Hex Buffers with Open-Collector High-Voltage Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1·6,1-42
DM5417/DM7417 Hex Buffers with Open-Collector High-Voltage Outputs ................ " .... ; ...... , 1-7,1-42
DM5420/DM7420 Dual4-lnput NAND Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7,1·36
DM54H20/DM74H20 Dual4-lnput NAND Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,1-7,1-36
DM54L20/DM74L20 Dual 4-lnput NAND Gates . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . . . 1-7,1-36
DM54LS20/DM74LS20 Dual 4-lnput NAND Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _. 1-7,1-36
DM74S20 Dual4-lnput NAND Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '........ _ .... 1-7,1-36
DM54H21/DM74H21 Dual 4-lnput AND Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7,1-44
'DM54LS211DM74LS21 Dual 4-lnput AND Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '........... 1-7,1-44
DM54H22/DM74H22 Dual 4-lnput NAND Gates with Open-Collector Outputs .............. ; ........... 1-8,1-38
DM54LS22/DM74LS22 Dual4-lnput NAND Gates with Open·Coliector Outputs. . . . . . . . . . . . . . . . . . .. . . .. 1-8,1-38
DM74S22 Dual 4-lnput NAND Gates with Open-Collector Outputs . . . . . . . . . . . . . . . . . . . . . . '. . . . . . . . . .. 1-8,1-38
DM5423/DM7423 Expandable Dual 4·lnput NOR Gates .... , , . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .. 1-8,1-50
DM5425/DM7425 Dual 4-lnput NOR Gates . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . .. 1-8, 1-40
DM5426/DM7426 Quad 2-lnput High-Voltage NAND Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-9,lA2
DM54L26/DM74L26 Quad 2-lnput High-Voltage NAND Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-9,1-42
DM54LS26/DM74LS26 Quad 2-lnput High-Voltage NAND Gates. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. .. 1-9,1-42
DM5427/DM7427 Triple 3·lnput NOR Gates. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-9,1-40
DM54LS27/DM74LS27 Triple 3·lnput NOR Gates. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .. 1-9,1-40
DM5430/DM7430 8-lnput NAND Gates. . . . . . . . . . . .. .. . . . . . . .. . . . . . . . . . ... . .. . . . . . . . . . . . .. 1·9,1-36
DM54H30/DM74H30 8·lnput NAND Gates. . . . . . . . . . . . . . . . . . . . .'. . . . . . . . .. . . . . . . . . . . . . . .. . .. 1·9,1-36
DM54L30/DM74L30 8-lnput NAND Gates ........... ; . . . . . . . .. . . . . . . . .. . . . . . . . . . . . . . . . . . .. 1-9,1-36
DM54LS30/DM74LS30 8-lnput NAND Gates ... _ . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-9,1-36
,DM74S30 8·lnput NAND Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .,' . . . . . . . . . . .. 1-9,1-36
DM5432/DM7432 Quad 2-lnput OR Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10; 1-52
DM54L32/DM74L32 Quad 2-lnput OR Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . ; 1-10,1-52
DM54LS32/DM74LS32 Quad 2-lnput OR Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '...............• 1-10,1-52
DM5437/DM7437 Quad 2-lnput NAND Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10,1-54
DM54LS37/DM74LS37 Quad 2-lnput NAND Buffers . . . . . . . . . . . . . . . . . . . . . . ; . . . . . . . . . . . . . . . . . . . 1-10,1-54
DM5438/DM7438 Quad 2-lnput NAND Buffers with Open-Collector Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10,1-42
DM54LS38/DM74LS38 Quad 2-lnput NAND Buffers with Open-Collector Outputs . . . . . . . . . . . . . . . . . . . . . . 1-10,1-42
DM5440/DM7440 Dual4-lnput NAND Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11, '·54
DM54H40IDM74H40 Dual 4-lnput NAND Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11,.1-54
DM54LS40/DM74LS40 Dual 4-lnput NAND Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11,1·54
DM74S40 Dual4-lnput NAND Buffers ...... , ............ : .... _. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11,1-54
DM5450/DM7450 Dual 2-Wide 2-lnput AND-OR-INVERT Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11,1-50,'
DM54H50/DM74H50 Dual 2-Wide 2-lnput AND-OR-INV ERT Gates. . . . . . . . . . .. . . . . . • . . . . . . . . . . . . .. 1-11. 1-50
DM5451/DM7451 Dual 2-Wide 2-lnput AND-OR-INVERT Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12.1,-56
DM54H51/DM74H51 Dual 2-Wide 2-lnput AND-OR-INVERT Gates ............. , . . . . . . . . . . . . . . . . . . 1-12,1-56
DM54L51/DM74L51 Dual 2-Wide 2-lnput AND-OR-INVERT Gates ......... " . . . . . . . . . . . . . . . . . . . . . 1-12,1-56
DM54LS51/DM74LS51 Dual 2-Wide 2-lnput AND-OR-INVERT Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12,1-56
DM74S51 Dual 2-Wide 2-lnput AND-OR-INVERT Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , .... 1-12, 1-56
DM54H52/DM74H52 Expandable 4-Wide AND-OR Gates ...........•... : . . . . . . . . . . . . . . . . . . . . . . . 1-13,1-50
DM5453/DM7453 Expandable 4-Wide AND·OR-INVERT Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ; .. 1-13,1-50
DM54H53/DM74H53 Expandable 4-Wide AND-OR-INVERT Gates . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . 1-13,1-50
DM5454/DM7454 4-Wide AND-OR-INVERT Gates . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . 1-14,1-56
DM54H54/DM74H54 4-Wide AND-OR-INVERT Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14,1-56
DM54L54/DM74L54 4-Wide AND-OR-INVERT Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . ; ......... , .. 1-14,1-56
DM54LS54/DM74LS54 4-Wide AND-OR-INVERT Gates ... : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14,1-56
DM54H55/DM74H55 2-Wide 4-lnput AND-OR-INVERT Gates ............ ; . . . . . . . . . . . . . . . . . . . . . . . 1-15.1-50
DM54L55/DM74L55 2-Wide 4-lnput AND-OR-INVERT Gates . . . . . . . . . . . . . . . . . . . . ; ..........•.. " 1-15,1-56
DM54LS55/DM74LS55 2-Wide 4-lnput AND-OR-INVERT Gates . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . 1-15,1-56
DM5460/DM7460 Dual4-lnput Expanders ..................... ; ...........•.•..........•.... 1-15,1-58
DM54H60/DM74H60 Dual 4-lnput Expanders . . . . . . . . . . . . . . . . . . . . . . . '. . . . . . . . . . . . . . . . . . . . . . . . 1-15,1-59
DM54H61/DM74H61 Triple 3-lnput Expanders ... ' . . . . . . . . . . . . . . . . . . . . . : . , . . . . . . . . . . . . . . . . . . . 1-16,1-60
DM54H62/DM74H62 4-Wide AND-OR Expanders . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '... 1-16,1-59

•

Note: When there ·are two sets of page numbers, the first designates the connection diagram page; the second indicates electrical tables.

~ TTL Data Book

Table of Contents

DM74S64 4-Wide AND-OR-INVERT Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16,1-56
DM74S65 4-Wide AND-OR-INVERT Gates with Open-Collector Outputs .............................. 1-17,1-61
DM5470/DM7470 AND-Gated J-K Positive-Edge-Triggered Flip-Flops with Preset and Clear . . . . . . . . . . . . . . . . . 1-18,1-62
DM54H71/DM74H71 AND-OR-Gated J-K Master-Slave Flip-Flops with Preset . . . . . . . . . . . . . . . . . . . . . . . . . 1-18,1-64
DM54L71/DM74L71 AND-Gated R-S Master-Slave Flip-Flops with Preset and Clear ............. " ....... 1·19,1-66
DM5472/DM7472 AND-Gated J-K Master-Slave Flip-Flops with Preset and Clear . . . . . . . . . . . . . . . . . . . . . . . . 1-19,1-62
DM54H72/DM74H72 AND-Gated J-K Master-Slave Flip-Flops with Preset and Clear. . . . . . . . . . . . . . . . . . . . . . 1-19,1-64
DM54L72/DM74L72 AND-Gated J-K Master-Slave Flip-Flops with Preset and Clear . . . . . . . . . . . . . . . . . . . . . . 1-19,1-66
DM5473/DM7473 Dual J-K Flip-Flops with Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20,1·62
DM54H73/DM74H73 Dual J-K Flip-Flops with Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . .. 1-20, 1-64
DM54L73/DM74L73 Dual J-K Flip-Flops with Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , ............ 1-20,1-66
DM54LS73/DM74LS73 Dual J-K Flip-Flops with Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " ..... 1-20,1·68
DM5474/DM7474 Dual D Positive-Edge-Triggered Flip-Flops with Preset and Clear . . . . . . . . . . . . . . . . . . . . . . 1-20,1-62
DM54H74/DM74H74 Dual D Positive-Edge-Triggered Flip-Flops with Preset and Clear . . . . . . . . . . . . . . . . . . . . 1-20,1-64
DM54L74/DM74L74 Dual D Positive-Edge-Triggered Flip·Flops with Preset and Clear . . . . . . . . . . . . . . . . . . . . 1-20,1-66
DM54LS74/DM74LS74 Dual D Positive-Edge-Triggered Flip-Flops with Preset and Clear ...... '. . . . . . . . . . . .. 1-20, 1-68
DM74S74 Dual D Positive-Edge-Triggered Flip-Flops with Preset and Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20,1-70
DM5476/DM7476 Dual J-K Flip-Flops with Preset and Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21,1·62
DM54H76IDM74H76 Dual J-K Flip-Flops with Preset and Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-21, 1-64
DM54LS76/DM74LS76 Dual J-K Flip-Flops with Preset and Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21,1-68
DM54H78/DM74H78 Dual J-K Flip-Flops with Preset, Common Clear and Common CI·ock . . . . . . . . . . . . . . . .. 1-21, 1-64
DM54L78/DM74L78 Dual J-K Flip-Flops with Preset, Common Clear and Common Clock . . . . . . . . . . . . . . . . . 1-21,1-66.
DM54LS78/DM74LS78 Dual J-K Flip-Flops with Preset, Common Clear and Common Clock . . . . . . . . . . . . . . . . 1-21,1-68
DM5486/DM7486 Quad EXCLUSIVE-OR Gates . . . . . . . . . . . . . . . . . . . . : . . . . . . . . . . . . . . . . . . . . . . . . 1-22,1-72
DM54L86/DM74L86 Quad EXCLUSIVE-OR Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , 1-22,1-72
DM54LS86/DM74LS86 Quad EXCLUSIVE-OR Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22,1-72
DM74S86 Quad EXCLUSIVE-OR Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22,1-72
DM54Hl03/DM74Hl03 Dual J-K Negative-Edge-Triggered Flip-Flops with Clear . . . . . . . . . . . . . . . . . . . . . . . . 1-23,1-74
DM54H 106/DM74Hl 06 Dual J-K Negative-Edge-Triggered Flip-Flops with Preset and Clear ........ '. . . . . . . .. 1-23, 1-74
DM54107/DM74107 Dual J-K Master-Slave Flip-Flops with Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23,1-62
DM54LS107/DM74LS107 Dual J-K Master-Slave Flip-Flops with Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23,1-68
DM54Hl08/DM74Hl08 Dual J-K Negative-Edge-Triggered Flip-Flops with Preset, Common Clear,
and Common Clock ... " " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '" ....... 1-24,1-74
DM54109/DM74109 Dual J.j( Positive-Edge-Triggered Flip-Flops with Preset and Clear. . . . . . . . . . . . . . . . . . .. 1-24, 1-62
DM54LS109/DM74LS109 Dual J-K Positive-Edge-Triggered Flip-Flops with Preset and Clear . . . . . . . . . . . . . . . . 1-24,1-68
DM54LS112/DM74Ls112 Dual J-K Negative-Edge-Triggered Flip-Flops with Preset and Clear . . . . . . . . . . . . . . , 1-24, 1-68
DM74S112 Dual J-K Negative-Edge-Triggered Flip-Flops with Preset and Clear . . . . . . . . . . . . . . . . . . . . . . . . . 1-24,1-70
DM54LSl13/DM74LSl13 Dual J-K Negative-Edge-Triggered Flip-Flops with Preset . . . . . . . . . . . . . . . . . . . . . . 1-25,1-68
DM74S113 Dual J-K Negative-Edge-Triggered Flip-Flops with Preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25,1-70
DM54LSl14/DM74LSl14 DlJal J-K Negative-Edge-Triggered Flip-Flops with Preset, Common Clear,
and Common Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-25, 1-68
DM74S114 Dual J-K Negative-Edge-Triggered Flip-Flops with Preset, Common Clear, and Common Clock ....... 1-25,1-70
DM54121/DM74121 OneShots ... , ....... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26,1-76
DM54LS122/DM74LS122 Retriggerable One Shots with Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26,1-78
DM54123/DM74123 Dual Retriggerable One Shots with Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26,1-78
DM54L 123A/DM74L 123A Du~1 Retriggerable One Shots with Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1·26, 1·78
DM54LS123IDM74LS123 Dual Retriggerable One Shots with Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-26, 1-78
DM54125/DM74125 TRI-STATE Quad Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . . . . . 1-27,1-80
DM54LS125/DM74LS125 TRI-STATE Quad Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27,1-80
DM54126IDM74126 TRI-STATE Quad Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27,1-80
DM54LS126(DM74LS126 TRI-STATE Quad Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27,1-80
DM54132/DM74132 Quad 2-lnput NAND Schmitt Triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27,1-48
DM54LS132/DM74LS132 Quad 2-lnput NAND Schmitt Triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27,1-48
DM74S133 13-lnput NAND Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28,1-36
DM74S134 TRI-STATE 12-lnput NAND Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28,1-80
DM74S135 Quad EXCLUSIVE-OR/NOR Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28,1-82
DM54l-S1361DM74LS136 Quad EXCLUSIVE-OR Gates with Open-Collector Outputs . . . . . . . . . . . . . . . . . . . . 1-29,1-84
DM74S136 Quad EXCLUSIVE-OR Gates with Open-Collector Outputs ............................... 1-29,1-84
DM74S140 Dual 50-Ohm Line Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29, 1-54
Note: When there are two sets of page numbers, the first designates the connection diagram page; the second indicates electrical tables.

ix

~ 'TTL Data Book

Table of Contents

DM54lS221/DM74LS221 Dual One Shots with Schmitt-Trigger Inputs ............•.........•......•
DM74S260 Dual 5-lnput NOR Gates ........................•............................
DM54LS266/DM74LS266 Quad EXCLUSIVE-NOR Gates with Open·Coliector Outputs ...................
DM54365/DM74365 TRI-STATE Hex Buffers .....•...•................... ' .......•...........
DM54LS365/DM74LS365 TRI·STATE Hex Buffers .............•...................•.•. ; .....
DM54366/DM74366 TRI-STATE Hex Buffers .....•..................' ..... ' •............. : . :.
DM54LS366/DM74LS366 TRI·STATE Hex Buffers ...... , ., .........................•....... ,
DM54367/DM74367 TRI-STATE Hex Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54LS367/DM74LS367 TRI-STATE Hex Buffers .................................... ',' ..•..
DM54368/PM74368 TRI-STATE Hex Buffers ......... ; ......... ; ...................... -.....
DM54LS368/DM74LS368 TRI-STATE Hex Buffers ................... '........................
DM54LS386/DM74LS386 Quad EXCLUSIVE·OR Gates .............................•..........

1-30,1-76
1-31,140
1-31,1-84
1·32,1·86
1~32, 1-86
1-32,1-86
1·32,1-86
1-32,1-86
1-32,1·86
1-33,1-86
1-33,1-86
1·34,1·72

54/74 MSI-SECTION 2
DM5441A/DM7441A BCD/Decimal Decoders/Drivers .... : ............ .'. . . . . . . . . . . . . . . • . • . . . ... . . .
DM5442/DM7442 BCD/Decimal Decoders . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54L42A/DM74L42A BCD/Decimal Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ; . .
DM54LS42/DM74LS42 BCD/Decimal Decoders ........ '.................... _ ......... '. .. . . . . . .. .
DM5445/DM7445 BCD/Decimal Decoders/Drivers. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . .
DM5446A/DM7446A BCD!7-Segment Decoders/Drivers .......... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM5447A1DM7447A BCD!7-Segment Decoders/Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ; . . . .
DM54LS47/DM74LS47 BCD!7-Segment Decoders/Drivers .... .' .....•..........................•.. : .
PM5448/0M7448 BCD/7:Segment Decoders/Drivers ............................................ ;
DM54LS48/DM74LS48 BCD/7-Segment Decoders/Drivers ..............•.... ; .................• ; . . .
DM54LS49/DM74LS49 BCD/7-Segment Decoders/Drivers ................................. : ... ;. . • .
DM5475/DM7475 Quad Latches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . ..
DM54L75A/DM74L75A Quad Latches ................ :. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . ..
DM54LS75/DM74LS75 Quad Latches ........................... '.. . . . . . . . . . . . . . . . . . . . . . .. . ..
DM54LS77/DM74LS77 Quad Latches. . . . . . . . . . . . . . . .. . . . . . . . . . • .. . . . . . . . . . . . . . . . . . . . . . . . . .•
, DM5483/DM7483 4-Bit Binary Adders with Fast Carry ....... '. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . ..
OM54LS83A/DM74LS83A 4-Bit Binary Adders with Fast Carry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM5485/DM7485 4-Bit Magnitude Comparators. . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . • . ..
DM54L85/DM74L85 4-Bit Magnitude Comparators .... '. . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . • • ..
DM54LS85/DM74LS85 4-BitMagnitude Compa~ators ......... : ......... : ................'. . . . . . . ..
DM5488/DM7488 256-Bit Read Only Memories. . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . .. ..
DM5489/DM74.89 64-Bit ReadlWrite Memories. . . . . . .. . . . . .. • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
OM54L89A/DM74L89A 64-Bit ReadlWrite Memories. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . •.
OM5490A/DM7490A Decade, Divide by 12, and Binary Counters. . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . ..
DM54L90/DM74L90 Decade, Divide by 12, and Binary Counters ........... '. . . . . .. . . . ... . . . . . . . . . . . . ..
DM54L!?90/DM74LS90 Decade, Divi!le by 12.-and Binary Counters. . . . . . . .. . . . . . . . . . . . . . . • . . . . . . . . . ..
DM5491A/DM7491A 8-Bit Serial Shift Registers ............... : . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . •.
DM54L91/DM74L91 8-Bit Serial Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ; . . . . ..
DM5492A/DM7492A Decade, Divide by 12, and Binary Counters ............... ' ............... '. . . . . ..
DM54LS92/DM74LS92 Decade, Divide by 12, and Binary Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . ..
DM5493A/DM7493A Decade, Divide by 12, and Binary Counters ...........' ........ ' ............ '. . .. . ..
DM54L93/DM74L93 Decade, Divide by 12, and Binary Counters ................................ ~ . . ..
, DM54LS93/DM74LS93 Decade, Divide by 12, and Binary Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM5495/DM7495 4·Bit ParalierAccess Shift,Registers •................ '. . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54L95/DM74L95 A·Bit Parallel Access Shift Registers . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54LS95B/DM74LS95B 4·Bit Parallel Access Shift Registers. . . • . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . ..
DM5496/DM7496 5·Bit Shift Registers .......................... ; . . . . . . . . . . . . . . . . . . . . . • . . . . ..
DM54LS96/DM74LS96 5-Bit Shift Registers ................................ " . . . . . . . . . . . . . . . ..
DM54L98/DM74L98 4-Bit Storage Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .' ......•... '. . . . ..
DM54LS124/DM74LSI24 Dual Voltage Controlled Oscillators. . . . . . . . . . . . . . . . . . . . . . .• . . . . . . . . . . . . . ..
DM54LSI38/DM74LS138 Decoders/Demultiplexers. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . • . . . . . . . . . . • . ..
DM74S138 Decoders/Demultiplexers.. . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54LS139/DM74LSI39 Decoders/Dem!lltiplexers .................... : ............•....... : . . ..
DM74S139 Decoders/Demultiplexers ........... ~ ...................... ; . . • ... . . . . . . . . . . . . • . ..
Note: When there are ,two sets of page numbers, the first dttsignates the confl8ction diagram. page; the second indicates electrical tables.

x

2·1
2-3
2-3
2·3
2·6
2-8
2-8
2-8
2-8
2·8
2-8
2-14
2·14
2-14'
2·14
2-17
2-17
2·21
2-21
2-21
2-25
2·28
2-28
2·30
2-30
2·30
2;34
2·34
2-30
2-30
2-30
2·30
2-30
2·36
2·36
2·36
2·39
2-39
2·42
2-44
2·46
2·46
246
2-46

~ TTL Data Book

Table of Contents

DM54141/DM74141 BCD/Decimal Decoders/Drivers . . . . . . . . . . . . . . . '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54145/DM74145 BCD/Deciinal Decoders/Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54147/DM74147 Priority Encoders. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54148/DM74148 Priority Encoders. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54150/DM74150 Data Selectors/Multiplexers... . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54151 A/DM74151 A Data Selectors/Multiplexers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
DM54LS151/DM74LS151 Data Selectors/Multiplexers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM74S151 Data Selectors/Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54153/DM74153 Dual4·line to l·Line Data Selectors/Multiplexers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54LS153/DM74LS153 Dual4·Line to l·Line Data Selectors/Multiplexers.. .. .... . .. . .. . . . . . . . . . . . . . ..
DM74S153 Dual4·Line to l·Line Data Selectors/Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "
DM54154/DM74154 4·Line to 16·Line Decoders/Demultiplexers . . . . . . . . . . . . . . . . . '.' . . . . . . . . . . . . . . . . ..
DM54Ll54A/DM74L154A 4·Lineto 16·Line DecodersiDemultiplexers . . . . . . . . . . . . . . . . . . . . . . ,..........
DM54LSl54/DM74LS154 4·Line to 16·Line Decoders/Demultiplexers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54155/DM74155 Dual 2·Limi to 4·Line Decoders/Demultiplexers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54LS155/DM74LS155 Dual 2·Line to 4·Line Decoders/Demultiplexers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54156/DM74156 Dual 2·Line to 4·Line Decoders/Demultiplexers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54LS156/DM74LS156 Dual 2·Line to 4·Line Decoders/Demultiplexers. . . . . . . . . . . . .. . . . . . . . . . . . . . . . ..
DM54157/DM74157 Quad 2·Line to 1·Line Data Selectors/Multiplexers........... '. . . . . . . . . . . . . . . . . . . . ..
DM54L 157A/DM74L 157A Quad 2·Line to 1·Line Data Selectors/Multiplexers. . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54LS157/DM74LS157 Quad 2·Line to I·Line Data Selectors/Multiplexers. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM74S157 Quad 2·Li,ne to l·Line Data Selectors/Multiplexers. • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54LS158/DM74LS158 Quad 2·Line to 1·Line Data Selectors/Multiplexers . . . . . . . . . . . . . . . . . . . .' . . . . . . . ..
DM74S158 Quad 2·Line to I·Line Data Selectors/Multiplexers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
.. DM54160A/DM74160A Synchro·nous4·Bit,Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '......
DM54LS160/DM74LS160 Synchronous 4·BIt Counters. . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54161A/DM74161A Synchronous 4·Bit Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
OM54LS161/DM74LS161 Synchronous 4·Bit Counters: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54162A/DM74162A Synchronous 4·Bit Counters. . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
OM54LS162/DM74LS162 Synchronous 4·Bit Counters ... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . ..
DM54163A/DM74163A Synchronous 4·Bit Counters. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54LS163/DM74LS163 Synchronous4-Bit Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . ..
OM54164/0M74164 8·Bit Serial In/Parallel Out Shift Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . ..
DM54L164A/DM74L164A 8-Bit Seria,lln/Paraliel Out Shift Registers ....... '" .... " . . • . . . . . . . . . . . . . . ..
OM54LS164/DM74LS164 8;Bit Serial In/Paralle! Out Shift 'Registers ............•...•........•... ',' . . .•
OM54165/DM74165 8·Bit Parallel In/Serial Out Shift Registers •.............••••••...............• ,.
OM54L165A10M74L 165A 8-Bit Parallel In/Serial Out Shift Registers. . . . . . . . . . . . . . . . . • . . . . . . . . . . . . • • ..
OM54166/DM74166 8·Bit Parallel In/Serial Out Shift Registers . . . . . . . . . . . . . . . . . " . . . . . . . . . . . . . . . . . . ..
DM54LSl68/DM74LS168 Synchronous 4·Bit Up/Down Counters. . . . . .. . . . . .. . . . . . . . . . . . . . . . . . . . . . . ..
DM54LS169/DM74LS169 Synchronous 4·Bit Up/Down Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM74170 4 by 4 Register Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54LS170/DM74LS170 4by4 Register Files ..... ' . . . . . . . . . . . . . . . . . . . • . . . . . . . . . '. . . . . . . . . . . . . . .
DM54173/DM74173 TRI·STATE Quad.o Registers . . . . . . . . . . . . . . . . '. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
. OM54LS173/DM74LS173 TRI·STATE Quad 0 Registers .... " ...... '.' . . . . . . . . . . . . . . . . . . . . . . . . . , ..
OM54174/0M74174 Hex/Quad 0 Flip·Flops with Clear. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . ..
OM54LSi741OM74LS174 Hex/Quad 0 Flip·Flops with Clear. . . . . . . . . . . . . . . . . • . . . • . . . . • . . . . . . . • . . . ..
DM74S174 Hex/Quad 0 Flip-Flops with Clear ....•.......•..... " . . . . . . . . . . .. . . . . . . . . . . . . • . . • ..
OM541751DM74175 Hex/Quad 0 Flip·Flops with Clear. • . . • . . . . . . . . . • . • • . • • . . • . . . • . • • . . . . . • . . . • ..
OM54LSl75/DM74:LS175 Hex/Quad 0 Flip·Flops with·Clear....•.••..•••••• , ••••' •••••..••.••.•••• "
DM74S175 Hex/Qulld 0 Flip·Flops with Clear. • • . . • . . . . • . . . . . • • . . . • • .• . . . • • • . . . • • • . • . • • . • . • • . ••
OM54176/0M74176 Pnisettable Decade and 8inary Counters••....••...•. , .• , •. , , ••.••...•••..•••.•• '
DM54177/DM74177 Presettable Decade and Binary Counters.• , ........•....•••..•.•.• , .•• , •••••..••
DM541S0JOM74180 9-Blt Parity Generators/Checkers .••....•...••......•......••.••....••••••.••
OM541Bl/OM74181 Arithmetic L09ic Unit/Function Generators •.•.• '.' •..•..•...•...•..•.••..•••• , ••
DM5418WM74182 Look-Ahead Carry Generators ..••.••..•.•..•.....••• _ •..•••.•••.•...••••••.
'OM74S182 l.Qok·Ahead Carry Generators•...••...••.•.••.... ' •... .- •..••......•••••••...•••••••
OMS418410M74184 BCP·to-Binary Bnd Binary-to-BCD Converters ...•..•...•......•••.•.•••. _ .•••••••
OM541S5A/DM14185A 6CD-to·Binary and Binary-to-BCD Converters ...............•.••••••••.• , ••. "
OM54187/0M74187 1024:Bit Read Only Memories ..•.•.••.......•. ' ...•...••••...•.•. , , .•••• , •.•

xi

2·1
2·6
249
2·49
2·53
2·53
2·53
2·53
2·57
2·57
2·57
2·60
2·60
2·60
2·63
2·63
2·63
2·63
2·66
2·66
2·66
2·66
2·66
2·66
2·70
2·70
2·70
2·70
2·70
2·70
2·70
2·70
2-76,
2·76
2·76
2-79
2·79
2·82
2·85
2·85
2·91
2·91
2·96
2·96,
2·98
2·98
2·98
2-"98
2~98

2..sa
2.1.01
2·101
2·105
2-107
2-113

2·n3
2·116

2,116
2-122

~ TTL Data Book

Table of Contents

DM54L187A/DM74L187A 1024-8itRead Only Memories . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-122
DM54S189/DM74S189 TRI-STATE 64-Bit ReadIWrite Memories ... " ... ; ... : .................... , ...... 2-125
DM54190/DM74190 Synchronous Up/Down Counters with Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " 2-128
DM54LS190/DM74LS190 Synchronous Up/Down Couniers with Mode Control . . . . . . . . . . . . . . . . . . . . : . . . . .. 2-128
DM54191/DM74191 Synchronous Up/Down Counters with Mode Control. .. . . . • . . . . . . . . . . . . . . .. . . . . . . .. 2-128
DM54LS191/DM74LS191 Synchronous Up/Down Counters'with Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 2·128
DM54192/DM74192 Synchronous Up/Down Counters with Dual Clock .................................. 2-133
DM54L 192/DM74L 192 Synchronous Up(Down Counters with Dual Clock. . . . . . . . . . . . . . . . . . . . . . . • . . . . . .. 2-133
DM54LS192/DM74LS192 Synchronous Up/Down Counters with Dual Clock ............. " ............... 2·133
DM54193/DM74193 Synchronous Up/Down Counters with Dual Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-133
DM54L 193/DM74L 193 Synchronous Up/Down Counters with Dual Clock ...................' •............ 2-133
DM54LS193/DM74LS193 Synchronous Up/Down Counters with Dual Clock ....................•. '.: ... " 2-13~
DM54194/DM74194 4-Bit Bidirectional Universal Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . , ........ 2-140
DM54LS194A/DM74LS194A 4-Bit Bidirectional Universal Shift Registers ...............................• 2·140
DM74S194 ,4·Bit Bidirectional Universal Shift Registers ........ " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " 2·140
DM54195/DM74195 4·Bit Parallel Access Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2·144
DM54LS195A/DM74LS195A 4·Bit Parallel Access Shift Registers .......... '........... : ............... 2·144
DM74S195 4·Bit Parallel Access Shift Registers .........•................ '. . . . . . . . . . . . . . . . . . . . . . . 2·144
DM54196/DM74196 Presettable, Decade and Binary..counters . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . .. 2·101
DM54LS196/DM74LS196 Presettable Decade and Binary Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-101
DM54197/DM74197 Presettable Decade and Binary Counter~. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. 2·101
D~54LS197/DM74LS197 Presettable Decade and Binary Counters ..•.......... .' ...... , ..... ; ......... 2·101
DM54198/DM74198 8·Bit Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ., ............. 2·148
DM54199/DM74199 8·Bit Shift Registers. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .. 2·148
DM54S200/DM74S200 TRI·STATE 256-Bit ReadIWrite Memories ...................................... 2·154
DM54S206/DM74S206 256·Bit ReadIWrite Memories with Open·Coliector Outputs: . . . . . . . . . . . . . . . . . . . . ; . .. 2·157
DM54251/DM74251 TRI·STATE Data Selectors/Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : .... '"
2-160
DM54LS251/DM74LS251 TRI·STATE Data Selectors/Multiplexers . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . 2·160
DM74S251 ·TRI·STATE Data Selectors/Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . • . . . 2·.160
DM54LS253/DM74LS253 TRI·STATE Data Selectors/Multiplexers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... 2·16:t
DM74S253 TRI-STATE Data Selectors/Multiplexers . . . . . . . . . . • . . . . . . . . . . . . . . . . . . : ...... '.' .. , .... , 2·163
DM54LS257/DM74LS257 TRI·STATE Quad 2·Data Selectors/Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . , .. 2·165
DM74S257 TRI·STATE Quad 2·Data Selectors/Multiplexers, ........................................ 2·165
DM54LS258/DM74LS258 TRI·STATE Quad 2·Dat3 Selectors/Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2·165
DM74S258 TRI·STATE Quad 2·Data Selectors/Multiplexers. : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2·165
DM54LS279/0M74LS279 Quad S-R Latches . . . . . . . . . . . . . . . . . . . . . ' ............................... 2·168
DM74S280 9·Bit Parity Generators/Checkers. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. . . . . . . . . . . . . . . .. 2·170
DM74S281 4·Bit Parallel Binary Accumulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . • • . . . . . .• 2·173
DM54LS283/DM74LS283 4·Bit Binary Adders with Fast Carry . . . . . . . . . . . . . . . . . . . . .,. . . . . . . . . . . . . . . .. 2·17
DM54S287/DM74S287 TRI·STATE 1024·Bit Programmable Read Only Memories . . . . . . . . . . . . . . . . . . . . . . . . . . 2-177
DM54S289/DM74S289 64·Bit ReadIWrite Memories with Open·Coliector Outputs ....•...... '............... 2·179
DM54LS295A/DM74LS295A TRI-STATE 4-Bit Parallel Access Shift Registers ..............•......•...... 2·182
DM54LS298/DM74LS298 Quad 2·Multiplexers with Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . 2·184
DM54LS374/DM74LS374 TRI·STATE Octal D Flip-Flops .................. '. . . . . . . . . . . . . . . . . . . . . . . . 2·187
DM54S387/DM74S387 1024·Bit Programmable Read Only Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2~177
DM54LS395/DM74LS395 TRI·STATE 4-Bit Cascadable Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2·189
DM54LS670/DM74LS670 TRI·STATE4 by 4 Register Files ....... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2·191

PROPRIETARY-SECTION 3,
DM80L06 Quad 2;lnput .NA.ND Gates with Resistive Pull·Ups .... : . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . ...
DM7090/DM8090 Quad Inverters plus Dual 2·lnput .NA.ND Gates ..... : . . . . . . . . . . . . . . . . ... . . . . . . . . . .
DM7091/DM8091 Quad 2-lnput .NA.ND Buffers. . . . . . . . . . . . . . . . . . . . . • . . . . . . .. .. . . . . . . . . . . . . . . .
DM7092/DM8092 Dual 5·lnput .NA.ND Gates. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . • . .. . . . . . . . . . . . .
DM7093/DM8093 TRI·STATE Quad Buffers. . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . .. . . . . . . . . .
DM7094/DM,8094 TRI-STATE Quad Buffers . . . . . . . . . . . . . . . . . . ' . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . '.
DM7095/DM8095 TRI-STATE Hex Buffers .............. ; ........ ". . . . . . . . . . . . . . .. . . . . . .. . .
DM70L95/DM80L95 TRI-STATE Hex Buffers ... : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '.' . : . . . • . . . . . .
DM7096/DM8096 TRI-STATE Hex Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . :. • . . . . . . . • . . . . . . • . . . . .

xii

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.
.
.
.
.
.
.
.

.
.
.
.
.
.
.
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.

3·1
.3·3
3·3
3·3
3-5,
3-5
3-7
3-7
3·7

~ TTL Data Book

Table of Contents

DM70L96/DM80L96 TR I-STATE Hex 8uffers
DM7097/DM8097 TRI-STATE Hex 8uffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . .
DM70L97/DM80L97 TRI-STATE Hex Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ .......... .
DM7098/DM8098 TRI-STATE Hex Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM70L98/DM80L98 TRI-STATE Hex Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ .......... .
DM7099/DM8099 TRI-STATE Quad 2-lnput NAND Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7121/DM8121 TR I-STATE Data Selectors/Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM71 L22/DM81 L22 Quad 2-lnput Data Selectors/Multiplexers . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . .
DM7123/DM8123 TR I-STATE Quad 2-lnput Data Selectors/Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM71 L23/DM81 L23 TRI-STATE Quad 2-lnput Data Selectors/Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7130/DM8130 10-Bit Magnitude Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ ........ .
DM7131/DM8131 6-Bit Unified Bus Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7136/DM8136 6-Bit Unified Bus Comparators. . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . .
DM7160/DM8160 6-Bit Magnitude Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . .
DM71 LS95/DM81 LS95 TRI-STATE Octal Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _
DM71 LS96/DM81 LS96 TR I-STATE Octal Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM71 LS97/DM81 LS97 TR I-STATE Octal Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM71 LS98/DM81 LS98 TR I-STATE Octal Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7200/DM8200 4-8it Magnitude Comparators . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . . . . . . . . . _ ...... .
DM721 0/DM821 0 8-line Data Selectors/Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7211/DM8211 8-Line Data Selectors/Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7214/DM8214 TRI-STATE Data Selectors/Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM72191DM8219 TRI-STATE Data Selectors/Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7220/DM8220 9-Bit Parity Generators/Checkers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7223/DM8223 l-Line to 8-Line Demultiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7230/DM8230 TRI-STATE Dual 2/4 Demultiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ ..... .
DM7511/DM8511 Dual Gated Flip-Flops. ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM75L 11/DM85L 11 Dual Gated Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . .
DM7512/DM8512 Dual Gated Flip·Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM75L12/DM85L12 Dual Gated Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ ... .
DM7520/DM8520 Modulo-N Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM8531 TRI-STATE 16k Read Only Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7542/DM8542 TR I-STATE Quad I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ ............ _
DM7544/DM8544 TR I-STATE Quad Switch Debouncers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7546/DM8546 TRI-STATE 8-Bit Universal I/O Shift Reigsters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM85S50 6-Bit Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7551/DM8551 TR I-STATE 4-Bit 0 Type Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM75L51/DMB5L51 TRI-STATE 4-Bit 0 Type Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7552/DM8552 TRI-STATE Synchronous Counters/Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM75L52/DM85L52 TR I-STATE Synchronous Counters/Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7553/DM8553 TR I-STATE 8-Bit Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7554/DM8554 TR I-STATE Synchronous Coun~ers/Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM75L54/DM85L54 TR I-STATE Synchronous Counters/Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7555/DM8555 TRI-STATE Programmable Decade Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7556/DM8556 TRI-STATE Programmable Binary Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7560/DM8560 Synchronous 4-Bit Up/Down Decade Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM75L60/DM85L60 Synchronous 4-Bit Up/Down Decade Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . _ ...... .
DM75p3IDM8563 Synchronous 4-Bit Up/Down Binary Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM75L63/DM85L63 Synchronous 4-Bit Up/Down Binary Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM75S68/DM85S68 64-Bit Edge-Triggered Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7570IDM8570 8-Bit Serial In/Parallel Out Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7573/DM8573 1024-Bit Field Programmable Read Only Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7574/DM8574 TRI-STATE 1024-Bit Field Programmable Read Only Memories . . . . . . . . . . . . . . . . . . . . . . . . .
DM7575/DM8575_Programmable Logic Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "' ..... .
DM7576/DM8576 Programmable Logic Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '.' ......... .
DM7577/DM8577 256-Bit Programmable Read Only Memories . . . . . . . . . . . . . . . . . . . . . . . '.' ... ' .......... .
DM7578/DM8578 TRI-STATE 256-Bit Programmable Read Only Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM8581 TRI-STATE16k Read Only Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7590/DM8590 8-Bit Parallel In/Serial Out Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . , ............. .

xiii

3-7
3-7
3-7
3-7
3-7
3-9
3-11
3-13
3-13
3-13
3-17
3-19
3-19
3-17
3-21
3-21
3-21
3-21
3-23
3-25
3-25
3-28
3-28
3-32
3-35
3-37
3-40
3-40
3-40
3-40
3-44
3-49
3-52
3-54
3-56
3-60
3-62
3-62
3-64
3-64
3-70
3-64
3-64
3-72
3-72
3-76
3-76
3-76
3-76
3·82
3-86
3-89
3-92
3-95
3-95
3-101
3-104
3-107
3-110

~ TIL Data Book

Table of Contents

DM7595/DM8595 4096-8it Read Only Memories __ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7596/DM8596 TRI-STATE 4096,Bit Read Only Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "
DM7597/DM8597 TRI'STATE 1024·Bit Read Only Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • .
DM7598/DM8598 TR I·STATE 256-Bit Read Only Memories ............ '. . . . .. . . . . . . . . . . . . . . . .. . . . ..
DM7599/DM8599 TRI-STATE 64-Bit Random Access Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7613/DM8613 Quad Gated Flip-Flops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM76L13/DM86L 13 Quad Gated Flip·Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . ..
DM76L24/DM86L24 TRI-STATE Magnitude Comparators with A Almost Equal B . . . . . . . . . . . . . . . . . . . . . . . . .
DM76L25/DM86L25 TRI·STATE 7-Segmentto BCD Decoders ......... '" . . . . . . . • . . . . . . . . . . . . . . . . . .
DM76L70/DM86L70 8-Bit Serial In/rarallel Out Shift Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM76L75/DM86L75 Presettable Decade Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . .
DM76L76/DM86L76 Presettable Binary Counters, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7678/DM8678 7 by 9 Character Generators .... ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7679/DM8679 7 by 9 Character Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . , .... _ . . . . . . . . . . . . . . .
DM76L90/DM86L90 8-Bit Parallel In/Serial Out Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM76L93/DM86L93 Binary Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . ;......
DM761,.97/DM86L97 TRI-STATE 1024·Bit Read Only Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM76L99/DM86L99 TRI-STATE 64-Bit Random Access Memories . . . . . . . . . . . . . . . . . . . . . . , ..... _ ......
DM7795/DM8795 4096-Bit Read Only Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . .
DM7796/DM8796 TRI-STATE 4096-Bit Read Only Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7853/DM8853 Dual Retriggerable Resettable Monostable Multivibrators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7875A/DM8875A TRI-STATE 4-Bit Parallel Binary Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7875B/DM8875B TRI-STATE 4-Bit Parallel Binary Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM8898 TRI-STATE BCD to Binary Converters
DM8899 TR I·STATE Binary to BCD Converters

3-113
3-116
3-119
3-122
3-127
3-40
3-40
3-131
3-134
3-86
3-137
3-137
3-140
3-140
3-110
3-142
3-144
3-148
3-113
3-116
3-151
3-154
3-154
3-156
3-156

ADDITIONAL DEVICES-SECTION 4
DM930 Dual 4-lnput Gates with Expanders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-1
4-1
DM932 Dual 4-lnput Buffers with Expanders . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM933 Dual 4·lnput Extenders. . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . .
4-'
DM935 Hex Inverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-1
DM936 Hex Invert~rs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ; . . .. . ..... .
4-1
oM937 Hex Inverters . ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ' . . . . . . . . . . . . . . . . . . . . 4-1
4-1
DM944 Dual 4-lnput Power Gates with Expanders. , . . . . . . . . . . . . . . . . . . . . . . . . . . ', . . . . . . . . . . . . . . . . . .
4-1
DM945 R-S Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4·1
DM946 Quad 2-lnput Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM94B R-S Flip-Flops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . .
4-1
DM949 Quad 2-lnput Gates. _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . .
4·1
DM957 Quad 2-lnput Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-1
DM958 Quad 2·lnput Power Gates. . . . . . . . . . . . . . . . . : : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-1
4-1
DM961 Dual4-lnput Gates with Expanders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-1
DM962 Triple 3-lnput Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM963 Triple 3-lnput Gates . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4·1
DM1800 Dual 5-lnput Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-1
DM1801 Dual 5·lnput Gates . . . . . . . . . . . . . . . . '. . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-1
DM2502/DM2502C Successive Approximation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6
4-6
DM2503/DM2503C Successive Approximation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . " .........•..•...
DM2504/DM2504C Successive Approximation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4·6
DM'7280/DM8280 Presett<\ble Decade Counters . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . • • . • . . . . . . . • . • . . . . . 4-11
DM72811DM8281 Pr~settable Binary Counters ... : . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . • . . . . . • . . • _ ... 4'11
DM7288/DM8288 Presettable Divide by 12 Counters ........•.......................•....•..•....• 4-11
DM7290/DM8290 Presettable Decade Counters . . . . . . . . . . . . . • . . . . . . . . . . '...........••....•....... 4-11
.DM1291/DM8291 Presettable Binary Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . 4-11
DM9002C Quad 2·lnput NAND Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . • • 4·15
DM9003C Triple 3~lnput NAND "Gates . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . • . . . • " ........••.... 4-15
DM9004C Dual 4-lnput NAND Gates . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . • . . . . . . . • • • . . . • .' 4·15
DM9005C Expandable Dual 2·lnput AND-OR-INVERT Gates . . . • . . . . . . . . . . . . . . . • . _ • _ .........••.•.• 4·15
DM9006C Dual 4-lnput Expanders . . . . . . . . . . . . . . . . . . . . . . . . . , ......•...•.•.•...••...••.••.•• .4-15

xiv

~ TTL Data Book

Table of Contents

DM9008C Expandable 4-Wide AND-OR-INVERT Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM9009C Dual 4-lnput NAND Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,
DM9012C Quad 2-lnput NAND Gates with Open-Collector Outputs. . .. .. . . . . . . . . . . . . . . . . . . .. . . . . . . . ..
DM9016C Hex Inverters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM9024/DM8024 Dual J-K Flip-Flops with Preset and Clear ............. _ . . . . . . . . . . . . . . . . . . . . . . . . ..
DM9093 Dual J-K Flip-Flops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM9094 Dual J-K Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . . . .
DM9097 Dual J-K Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . .
DM9099 Dual J-K Flip-Flops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM9300/DM8300 4-Bit Parallel-Access Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . ..
DM9301/DM8301 1 of 10 Decoders ..... : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM9309/DM8309 Dual 4-Line to 1-Line Data Selectors/Multiplexers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM9310/DM8310 Synchronous 4-Bit Decade Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . ..
DM9311/DM8311 4-Line to 16-Line Decoders/Demultiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . _ ..... _ . . . . ..
DM9312/DM8312 8·Line to 1-Line Data Selectors/Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . ..
DM9316/DM8316 Synchronous 4-Bit Binary Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM9318/DM8318 Priority Encoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ ............ ,
DM9322/DM8322 Quad 2-Line to l-Line Data Selectors/Multiplexers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM9334/DM8334 8-Bit Addressable Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . ..
DM9601/DM8601 Retriggerable One Shots. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM9602/DM8602 Dual Retriggerable, Resettable, One Shots .......... _ . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

xv

4·15
4-15
4-15
4-15
4-17
4-1
4-1
4-1
4-1
4-19
4-22
4-24
4-27
4-33
4-24
4-27
4-36
4-38
4-40
4-43
4-46

~ T1L Data Book

TRI-STATE Selection Guide

DEVICE NO.

DM54125/DM74125
DM54LS125/DM74LS125
DM54126/DM74126
DM54 LS126/DM74LS126
DM74S134
DM54173/DM74173
DM54LS173/DM74 LS173
DM54S189/DM74S189
DM54S200/DM74S200
DM54251/DM74251
DM54LS251/DM74LS251
DM74S251
DM54LS253/DM74LS253
DM74S253
DM54 LS257 /DM74LS257
DM74S257
DM54 LS258/DM74 LS258
DM74S258
DM54S287/DM74S287
DM54 LS295A/DM74LS295A
DM54365/DM74365 .
DM54 LS365/DM74LS365
DM54366/DM74366
DM54LS366/DM74 LS366
DM54367/DM74367
DM54 LS367 /DM74 LS367
DM54368/DM74368
DM54LS368/DM74LS368
DM54LS374/DM74LS374
DM54LS395/DM74LS395
DM54 LS670/DM74LS670
DM7093/DM8093
DM7094/DM8094
DM7095/DM8095
DM70L95/DM80L95
DM7096/DM8096
DM70L96/DM80L96
DM7097/DM8097
DM70L97/DM80L97
DM7098/DM8098
DM70L98/DM80L98
DM7099/DM8099
DM7121/DM8121
DM7123/DM8123
DM71 L23/DM81 L23
DM71 LS95/DM81 LS95
DM71 LS96/DM81 LS96
DM71 LS97/DM81 LS97
DM71 LS98/DM81 LS98
DM7214/DM8214
DM7219/DM8219
. DM7230/DM8230
DM8531
DM7542/DM8542
DM7544/DM8544
DM7546/DM8546
DM7551/DM8551
DM75L51/DM85L51
DM7552/DM8552

DESCRIPTION

PAGE
NO:

TRI·STATE Quad Buffers . .' ... ; ......... , ......................... ;
1-80
TRI·STATE Quad Buffers . . . . . . . . . . . . . . . . . . . . . . . .' .........•.•.....
1-80
TRI·STATE Quad Buffers ...................................... , .. .
1-80
TRI·STATE Quad Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '," ... .
1-S0
TRI·STATE 12-lnput NAND Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-80
TRI·STATE Quad D Registers ..................... o' • • • • • • • • • • • • • • • •
2·96
TRI·STATE Quad D Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-96
TRI·STATE64-Bit Read/Write Memories............... " ............. . 2-125
TRI·STATE 256-Bit Read/Write Memories .. ; . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-154
TR I·STATE Data Selectors/Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-160
TRI·STATE Data Selectors/Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . , .. ; .. . 2.1160
TRI·STATE Data Selectors/Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-160
TRI·STATE Data Selectors/Multiplexers. '.' . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-163
TRI·STATE DataSelectors/Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . : ': .... . 2:163
TR I·STA TE Quad 2-0ata Selectors/Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . 2-165
TR I·STA TE Quad 2-Data Selectors/Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . 2-165
TRI·STATE Quad 2-Data Selectors/Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . 2-165
TRI·STATE Quad 2-Data Selectors/Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . 2-165
TRI·STATE 1024·Bit Programmable Read Only Memories .................. . 2-177
TR I·STA TE 4-Bit Parallel Access Shift Registers .................... .' .... . . 2-182
1·86
TRI·STATE Hex Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-86
TRI·STATE Hex Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-86
TRI·STATE Hex Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-86
TRI·STATE Hex Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-86
TRI·STATE Hex Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-86
TRI·STATE Hex Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-86
TRI·STATE Hex Buffers. " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TRI-STATE Hex Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
'-86
TRI·STATE Octal D Flip·Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-187
TRI·STATE 4·Bit Cascadable Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-189
TRI-.STATE4 By4 Register Files .. , ..................... , .......... . 2-191
3-5
TRI·STATE,Quad Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5
TRI·STATE Quad Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-7
TR I·STA TE Hex Buffers ...... " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-7
TR I·ST A TE Hex Buffers ................... '" .................... .
3-7
TRI·STATE Hex Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-7
TRI·STATE Hex Buffers ..... '................. : .................. .
3-7
TRI·STATE Hex Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-7
TRI·STATE Hex Buffers ................ " . . . . . . . . . . . . . . . . . . . . . . . . :
3-7
TRI·STATE Hex Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-7
TRI·STATE Hex Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-9
TRI·STATE Quad 2·lnput NAND Buffers ....................' ......... .
3-11
TR I·STATE Data Selectors/Multiplexers ......•........................
3-13
TRI-STATE Quad 2·lnput Data Selectors/Multiplexers .. ,,' ................. ,
3-13
TRI·STATE Quad 2·lnput Data Selectors/Multiplexers . . . . . . . . . . . . . . . . . . . . . .
3-21
TRt-STATE Octal Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .' ..
3-21
TRI·STATE Octal Buffers .......... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-21
TRI·STATE Octal Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-21
TR I·STA TE Octal Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3·28
TRI-STATE Qata Selectors/Multiplexers ......... '........ , ............ .
3-28
TRI·STATE Data Selectors/Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-37
TRI·STATE Dual 2/4 Demultiplexers ... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-49
TRI-STATE 16K Read Only Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-52
TRI·STATE Quad I/O Registers; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-54
TRI·STATE Quad Switch Debouncer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-56
TRI-STATE 8-Bit Universal I/O Shift Registers. , ............ , ........... .
3,62
TR I·STA TE 4·Bit D Type Registers . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . .
3-62
TR I·STATE 4·Bit D Type Registers ..........•.. , ................... .
3-64
TRI·STATE Synchronous Counters/Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . : .
xvi

~ TTL Data Book

TRI-STATE Selection Guide'
DESCRIPTION

DEVICE NO.
DM75L52/DM85L52
DM7553/DM8553
DM7554/DM8554
DM75L54/DM85L54
DM7555/DM8555
DM7556/DM8556
DM7574/DM8574
DM7578/DM8578
DM8581
DM7596/DM8596
D M7597 /DM8597
DM7598/DM8598
DM7599/DM8599
DM76L24/DM86L24
DM76L25/DM86L25
DM76L97/DM86L97
DM76L99/mil86L99
DM7796/ DM8796
DM7875A/DM8875A
DM7875B/DM8875B
DM8898
DM8899

TRI-STATE
TRI-STATE
TR I-STATE
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE

Synchronous Counters/Latches ......... '..... , ... , ......... .
8-Bit Latches ... , ...... , ..... , ...... , ..... , .... '...... .
Synchronous Counters/Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous Counters/Latches ........... , ................ .
Programmable Decode Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programmable Binary Counters .. , .... , ..... , .............. .
1024-Bit Field Programmable Read Only Memories .............. .
256-Bit Programmable Read Only Memories ................... .
16k Read Only Memories, ................ , .............. .
4096-Bit Read Only Memories. , ..... , ......... , .......... .
1024-Bit Read Only Memories ....... , .................... .
256-Bit Read Only Memories ....... , , ..... , .. , ........... .
64-Bit Ran~om Access Memories. , .. , ........ , ............. .
Magnitude Comparators with A Almost Equal B................. .
7-Segmentto BCD Decoders ............ , ................. .
1024-Bit Read Only Memories, . , ................ , ........ .
64-Bit Random Access Memories ... , . , ....... , ............. .
4096-Bit Read Only Memories ...... , ... , , ... , ...... , ..... .
4-Bit Parallel Binary Multipliers .. , ................ , ........ .
4-Bit Parallel Binary Multipliers. , .. , ... , . , .. , , , , .. , ...... , ..
BCD to Binary Converters ... '. : .................... , ..... .
BCD to Binary to BCD Converters ........ , ..... , , .. , ..... , . ,

xvii

PAGE
NO.
3-64
3-70
3-64
3-64
3-72
3-72
3-92
3-104
3-107
3-116
3-119
3-122
3-127
3-131
3-134
3-144
3-148
3-116
3-154
3-154
3-156
3-156

~

TTL Families Comparison Guide

TTL Data Book

DM54174

DM54H174H

DM54L/74L

DM54LS/74LS

00

HOO

LOO

LSoo

PARAMET,ER(lI
MIN
10H

High Level Output Current

VOH

High Level Output
Voltage

DM54
DM74

10l

VOL

TVP

los

TVP

400ltA
2.4@

MAX

,MIN

MAX

MIN

TVP

SOO

2·4@

2.5@

500IlA
2.4@

200!lA
2.4@

400/lA
2.7@

looOltA
2.7@

20

2

4

Current

DM74

16

20

3.6

S

Short Circuit OutpUt Current

'CCH SupplV Current
(Average per,'Gate)

-20

20
20

0.4@

0.5@

2mA

4mA

0.4@

0.4@

0.5@

20 rnA
0.5@

20 rnA

3.6 rnA

SmA

20 rnA

20 rnA

16mA

,

40@

5O@

10'@

20@

50@

2.4V

2.4V

2.4V

2.7V

'PV

-1.6@

-2.0@

-{l.IS@

-{l.36@

-2.0@

0.4V

0.4V

0.3V

0.4V

0.5V

High level Input Current

Low Level Input Current

V

0.3@

0.4@

0.4@'
16mA
0.4@

-55
1.0

-3

-100

-40

-15

-130

-30

0.11

2.5

itA

1000ltA

400ltA

16

DM54

UNITS
MAX

-1000

2.5@

200ltA

TVP

-400'

-200

DM54

Low Level Output

MIN

MAX

2.4@

5OO1lA

400ltA

'TVP

-500

-400
2.4@

DM74

III

MIN

low Level Output

Voltage

I'H

MAX

' DM54S/74S

rnA

V

Jl.A

rnA

-100

-40

mA

2.5

0.2

rnA

..... l

Turn "ON" Time

7

15

6.2

10

31

60

10

15

3

5

tpLH

Turn "OFF" Time

11

22

5.9

10

35

60

9

15

3

4.5

.ns
ns

Notes
(1) The 00 gate parameters were used in all cases.
(2)

The product families below will drive the indicated number of loads of each of the above products.

DM54L/74L

DM54LS174ts

DM54S/74S

DM54/74

DM54H/74H

00

HOO

LOO

LSOO

SOO

,MIN

MIN

MIN

MIN

MIN

Series DM54174

10

S

40

20

8

Series DM54HI74H

12

10

50

25

10

Series DM54L174L

2'

1

20

10

1

Series DM54LS174LS

5

4

40

20

4

Series DM54S174S

12

10

100

50

10

FANOUT CAPABILITIES(2)

...

XVIII

~ TTL Data Book

Industry Cross Reference Guide

.

This list is intended to give National replacements for competitors' parts not using the 54/74 numbering system .
Only the basic circuit numbers are cross referenced. As the pin-out sometimes varies between a flat package part and the equivalent DIP part, it is recommended that the manufacturer's specifications be consulted prior to specifying a direct replacement.
Other than parts offered only in a flat package, the dual-in-line pin-outs were used as a guide in preparing the following cross
references.
Direct Replacements were selected as pin-for-pin equivalent circuits based on similarity of electrical and mechanical characteristics as shown in currently published data. Interchangeability in any particular application is not necessarily guaranteed. Before
using a substitute, the user should compare the specifications of the substitute device with the detailed specificati'ons of the
original device.
National Semiconductor makes no warranty as to the information furnished, and buyer assumes all risk in the use thereof.
No liability is assumed for damages resulting from the use of the information contained in this list.

DEVICE
TYPE

NATIONAL DIRECT
REPLACEMENT

DEVICE
TYPE

AMD

Fairchild (con't)
DM2502/2502C
DM250212502C
DM2503/2503C
DM250312503C
DM2504/2504C
DM250412504C
DM54LS138/74LS138
DM54LS139/74LS139
DM54LS151/74LS151
DM54LS153/74LS153
DM54LS157/74LS157
DM54LS158/74LS158
DM54LS160/74LS160
DM54LS161/74LS161
DM54LS162/74LS162
DM54LS163/74LS163
DM54LS164/74LSl64
DM54LS174/74LS174
DM54LS175/74LS175
DM54181n4181
DM54LS190/74LS190
DM54LS191/74LS191
DM54LS192/74LS192
DM54LS193/74LS193
DM54LS194A/74LS194A
DM54LS195A/74LS195A
DM54LS251/74LS251
DM54LS253174LS253
DM54LS25.1 /74LS257
DM54LS258/74LS258
DM$l602/8602
DM9602/8602
DM9602/8602
DM541:z3n4123
DM54L 123A!74L123A
DM75L60/85L60
DM75L63/85L63

AM2502
AM25L02
AM2503
AM25L03.
AM2504
AM25L04
AM25LS138
AM25LS139
AM25LS151
AM25LSl53
AM25lS157
AM25LS158
AM25LS160
AM25LS161
AM25LS162
AM25LS163
AM25LS164
AM25LS174
AM25LS175
AM25LS181
AM25LS190
AM25LS191
AM25LS192
AM25LS193
AM25LSl94A
AM25LS195A
AM25LS251
AM25LS253
AM25LS257
AM25LS258
AM2602
AM26L02
AM26S02
AM26123
AM26L123
AM93L60
AM93L66
Fairchild

930
932

,

NATIONAL DIRECT
REPLACEMENT

933
935
936
937
944
945
946
948
949
961
962
963
9002
9003
.9004
9005
9006
9008
9009
9012
9016
9024
9093
9094
9097
9099
9135
9157
9158
9300
9301
9307
9309
9310
9311
9312
9315
9316

..
DM930
DM932

2~'(
xix

DM933
DM935
DM936
DM937
DM944
DM945
DM946
DM948
DM949
DM961
DM962
DM963
DM9002C
DM9003C
OM9004C
DM9005C
DM9006C
DM9008C
· DM9009C
· DM9012C
DM9016C
DM9024/8024
DM9093
OM9094
DM9097
DM9099
DM935
oM957
DM958
DM9300/8300
DM9301/8301
DM5448/7448 .
DM9309/8309
· DM9310/8310
DM9311/8311
DM9312/8312
DM5441A/7441A
DM9316/8316

~ TTL Data Book
DEVICE
TYPE

Industry Cross Reference Guide
NATIONAL DIRECT
REPLACEMENT

DEVICE
TYPE

93178
9317C
9318
9321
9322
9325
9341
9342
9345
9352,
9357A
93578
9358
9360
9366
9375
9377
9383
9385
9390
9391
9392
9393
9395
9396

DM5447A/7447A
DM5446A17446A
,DM9318/8318
DM54LS139/74LS139
DM9322/8322
DM54141/74141
DM54181/74181
DM54182/74182
DM544517445
DM544217442
DM5446A/7446A
DM5447A17447A
DM544817448
DM54192/74192
DM54193/74193
DM5475/7475
DM54LS77/74LS77
DM5483/7483
DM5485i7485
DM5490/7490
DM5491 A17491 A
DM5492/7492
DM549317493
DM5495/7495
DM5496/7496

93197
93198
93199

DM54197/74197
DM54198/74198
DM54199/74199

9601
9602
9603 '

DM9601/8601
DM9602/8602
DM54121/74121

93141
93145
93150
93151
93153
93155
93156
93157
93160
93161
93162
93163
93164
93165
93166
93170
93174
93175
93176
93177
93180
93190
93191
93194
93195
93196

DM54141/74141
DM54145174145
DM54150/74150
DM54151A/74151A
DM54153/74153
DM54155/74155
DM54156174156
DM54157/74157
DM54160A174160A
DM54161A/74161A
DM 54162A/7 4162A
DM54163A/74163A
DM54164/74164
DM54165/74165
DM54166/74166
DM74170
DM54174/74174
DM54175/74175
DM54176/74176
DM54177/74177
DM54180/74180
DM54190/74190
DM54191/74191
DM54194/74194
DM54195/74195
DM54196/74196

9HOO
9HOl
9H04
9H05
9H08
9Hl0
9Hl1
9H20
9H21
9H22
9H30
9H40
9H50
9H51
9H52
9H53
9H54
9H55
9H60
9H61
9H62
9H71
9H72
9H73
9H74
9H76
9H78
9Hl03
9Hl06
9H108

DM54HOO/74HOO,
DM54H01/74HOl
DM54H04/74H04
DM54H05/74H05
DM54H08/74H08
DM54H 10174H 10
DM54H11174Hl1
DM54H20/74H20
DM54H21174H21
DM54H22174H22
DM54H30174H30
DM54H40/74H40
DM54H50174H50
DM54H51174H51
DM54H52174H52
DM54H53174H53
DM~H54/74H54
DM 4H55/74H55
DM54H60/74H60
DM54H61174H61
DM54H62174H62
DM54H71/74H71
DM54H72/74H72
DM54H73/74H73
DM54H74174H74
DM54H76174H76
DM54H78/74H78
DM54H103/74Hl03
DM54H106/74H106
DM54H108174H108

93HOO

DM54LS195A/74LS195A

9LOO'
9L04'
9L24*
9L54'
9L86'

DM54LOO/74LOO
DM54L04/74L04
DM9024/8024
DM54L54/74L54
DM5486/7486

93LOO'
93L01'
93L09'
93L 10'
93L11'
93L12'
93L16'
93L 18'
93L22'
93L34'
93L41 ,

DM54LS195A/74LS195A
DM9301/8301
DM9309/8309
DM76L75/86L75
DM54L 154A/74L 154A
DM9312/8312
DM76L76/86L76
DM9318/8318
DM54L157A/74L157A
DM9334/8334
DM54181/74181

96L02'

DM9602/8602

Fairchild (con't)

NATIONAL DIRECT
REPLACEMENT

Fairchild (con't)

'The National Low Power circuits are "True Tenth Power," whereas the Fairchild circuits are not.

xx

~ TTL Data Book
DEVICE
TYPE

Industry Cross Reference Guide
DEVICE
TYPE

NATIONAL DIRECT
REPLACEMENT

Fairchild (con't)

Fairchild (con't)

9LSOO
9LS02
9LS03
9LS04
9LS05
9LS08
9LS09
9LS10
9LS11
9LS14
9LS15
9LS20
9LS21
9LS22
9LS27
9LS30
9LS32
9LS37
9LS38
9LS40
9LS42
9LS51
9LS54
9LS55
9LS73
9LS74
9LS83
9LS86
9LS90
9LS92
9LS93
9LS95
9LS109
9LS112
9LSl13
9lS114
9LS125
9LS126
9LS132
9LS133
9LS136
9LS138
9LS139
9LS151
9LS153
9LS155
9LS156
9LS157
9LS158
9LS160
9LS161
9LS162
9LS163
9LS164
9LS170
9LS174

NATIONAL DIRECT
REPLACEMENT

9LS175
9LS181
9LS190
9LS191
9LS192
9LS193 .
9LS194
9LS195
9LS196
9LS197
9LS251
9LS253
9LS257
9LS258
9LS259
9LS266
9LS279
9LS283
9LS295
9LS298
9LS365
9LS366
9LS367
9LS368
9LS670

DM54LSOO/74LSOO
DM54LS02/74LS02
DM54LS03/74LS03
DM54LS04/74LS04
DM54LS05/74LS05
DM54LS08/74LS08
DM54LS09/74LS09
DM54LS10/74LS10
DM54LS11/74LS11
DM54LS14/74LS14
DM54LS15/74LS15
DM54LS20/74LS20
DM54LS21/74LS21
DM54LS22!74LS22
DM54LS27/74LS27
DM54LS30/74LS30
DM54LS32/74LS32
DM54LS37/74LS37
DM54LS38/74LS38
DM54LS40/74LS40
DM54LS42/74LS42
DM54LS51/74LS51
DM54LS54/74LS54
DM54LS55174LS55
DM54LS73/74LS73
DM54LS74/74LS74
DM 54 LS83A/7 4 LS83A
DM54LS86/74LS86
DM54 LS90/74LS90
DM54LS92/74LS92
DM54LS93/74LS93
DM54LS95B/74LS858
DM54LS109/74LS109
DM54LSl12/74LSl12
DM54LSl13/74LSl13
DM54LSl14/74LSl14
DM54LS125/74LS125
DM54LS126/74LS126
DM54LS132/74LS132
DM74S133
DM54LS136/74LS136
DM54LS138/74LS138
DM54LS139/74LS139
DM54LS151/74LS151
DM54LS153/74LS153
DM54LS155/74LS155
DM54LS156/74LS156
DM54LS157/74LS157
DM54LS158/74LS158
DM54LS160/74LS160
DM54LS161/74LS161
DM54LS162/74LS162
DM54LS163/74LS163
DM54LS164/74LS164
DM54LS170174LS170
DM54LS174174LS174

9NOO
9N01
·9N02
9N03
9N04
9N05
9N06
9N07
9N08
9N09
9N10
9Nl1
9N12
9N13
9N14
9N16
9N17
9N20
9N21
9N23
9N25
9N26
9N27
9N30
9N32
9N37
9N38
9N39
9N40
9N50

"The National Low Power circuits are "True Tenth Power," whereas the Fairchild circuits are not.

xxi

DM54LS175/74LS175
DM54181/74181
DM54LS190/74LS190
DM54LS191/74LS191
DM54LS192!74LS192
DM54LS193/74LS193
DM54LS194A/74LS194A
DM54LS195A/74LS195A
DM54LS196/74LS196
DM54LS197/74LS197
DM54LS251/74LS251
DM54LS253/74LS253
DM54LS257/74LS257
DM 54 LS258/7 4LS258
DM9334/8334
DM 54 LS266/7 4 LS266
DM54LS279/74LS279
DM54LS283/74LS283
DM54LS295A/74LS295A
DM54LS298/74LS298
DM54LS365/74LS365
DM54LS366/74LS366
DM54LS367/74LS367
DM54LS368/74LS368
DM54LS670/74LS670
DM5400/7400
DM5401/7401
DM5402/7402
DM5403/7403
DM5404/7404
DM5405/7405
DM5406/7406
DM 5407 /7407
DM5408/7408
DM5409/7409
DM5410/7410
DM5411/7411
DM54LS12/74LS12
DM5413/7413
DM5414/7414
DM5416/7416
DM5417/7417
DM5420/7420
DM54LS21/74LS21
DM5423/7423
DM5425/7425
DM5426/7426
DM5427/7427
DM5430/7430
DM5432/7432
DM5437/7437
DM5438/7438
DM5401/7401
DM5440/7440
DM5450/7450

~~

TTL Data Book
DEVICE
TYPE

Industry Cross Reference Guide
DEVICE
TYPE

NATIONAL DIRECT
REPLACEMENT

Fairchild (con't)

Fairchild (con't)
9N51
9N53
9N54
9N60
9N70
9N72
9N73
9N74
9N76
9N86
9Nl07
9N122
9N123
9N132
9N279
9500
9502
9503
9504A
,9505A
9508
9509
9510
9511
9515
9520
9522
9530
9532
9540
9551
9564
9565
9574
9586
95109
95112
95113
95114
95132
95133
95134
95135
95140
93500
93510
93512
93S16
93521
93522
93541
93542
93546
93547

I

,

NATIONAL DIRECT
REPLACEMENT

DM5451/7451
DM5453/7453
DM5454/7454
DM5460/7460
DM5470/7470
DM5472/7472
OM5473/7473
OM5474/7474
OM5476/7476
DM5486/7486
OM541 07/741 07
OM54L5122/74L5122
011.154123/74123
OM54132/74132
OM54L5279/74L5279

935138
935139
935151
935153
935157
935158
935174
935175
935194
935251
935253
935257
935258

DM745138
DM745139
DM745151
OM745153
DM745157
OM745158
OM745174
OM745175
OM745194
DM745251
OM745253
DM745257
DM745258

96502

OM9602/8602

DM74500
011.174502
011.174503
011.174504
011.174505
OM74L508
OM74L509
011.174510
011.174511
011.174515
DM74520
OM74522
OM74530
OM74L532
OM74S40
DM74551
OM74564
OM74565
011.174574
OM74586
OM74L5109
OM745112
DM745113
OM745114
OM54L5132/74L5132
DM745133
DM745134
DM745135
DM745140

Motorola
MC830
MC832
MC833
MC836
MC837
MC840
MC844
MC845
MC846
MC848
MC849
MC852
MC853
MC855
MC856
MC857
Me858
MC861
MC862
MC863

011.1930
DM932
011.1933
011.1936
011.1937
011.1935
DM944
OM945
OM946
OM948
OM949
OM9099
OM9093
OM9097
OM9094
OM957
OM958
OM961
OM962
OM963

MC1BOO
MC1BOl

DM1800
DM1801

Signetics
8230
82530
8241
82541
8252
82552
8269
8280
82580
8281
82S81
8290
82590
8291

011.1745195
DM54L5160/74L5160
OM9312/8312
DM54L5161/74L5161
OM745139
OM745157
OM54181174181
OM745182
OM7160/8160
OM7160/8160

'The National Low Power circuits are "True Tenth Power," whereas the Fairchild circuits are not.

xxii

DM9312/8312
OM9312/8312
OM54L5386/74LS386
OM54L5386/74LS386
DM9301/8301
DM9301/8301
OM7200/8200
DM7280/828a
OM54LSl96174L5196
OM7281/B281
DM54LS197174LS197
OM7290/8290
DM54LS196/74LSl96
DM7291/829l

~

TTL Data Book

DEVICE
TYPE

Industry Cross Reference Guide
NATIONAL DIRECT
REPLACEMENT

DEVICE
TYPE

82S91
8292
8293
82147
82148

DM54LS197/74LS197
DM54LS196/74LS196
DM54LS197/74LS197
DM54147/74147
DM54148/74148

8415
8455
8470
8471
8480
8481
8490

DM1800
DM5440/7440
DM5410/7410
DM54LS12/74LS12
DM5400/7400
DM5403/7403
DM540417404

SN15848
SN15849
SN15857
SN15858
SN15861
SN15862
SN15863
SN151800
SN151801
SN168093
SN158094
SN158097
SN158099

DM948
DM949
DM957
DM958
DM961
DM962
DM963
DM1800
DM1801
DM9093
DM9094
DM9097
DM9099

8806
8808
8815
8828
8840
8848
8859
8875
8881
8890
8891

DM546017460
DM543017430
DM542517425
DM5474/7474
DM5451/7451
DM54LS54/74LS54
DM5440/7440
DM542717427
DM540117401
DM540417404
DM5405/7405

8H16
8H70
8H80
8H90

DM54H20/74H20
DM54H 10/74H 10
DM54HOO/74HOO
DM54H04174H04

8T10
8T22
8T54
8T95
8T96
8T97
8T98

DM7551/8551
DM9601/8601
DM544817448
DM7095/8095
DM7096/8096
DM7097/8097
DM7098/8098

SN29002
SN29003
SN29004
SN29005
SN29006
SN29008
SN29009
SN29012
SN29016
SN29024
SN29300
SN29301
SN29309
SN29310
SN29311
SN29312
SN29316
SN29318
SN29322
SN29334
SN29601
SN29602

DM9002C
DM9003C
DM9004C
DM9005C
DM9006C
DM9008C
DM9009C
DM9012C
DM9016C
DM8024
DM8300
DM8301
DM8309
DM8310
DM8311
DM8312
DM8316
DM8318
DM8322
DM8334
DM8601
DM8602

SN39024
SN39300
SN39301
SN39309
SN39310
SN39311
SN39312
SN39316
SN39318
SN39322
SN39334
SN39601
SN39602

DM9024
DM9300
DM9301
DM9309
DM9310
DM9311
DM9312
DMg316
DM9318
DM9322
DM9334
DM9601
DM9602

Signetics (con't)

TI (con't)

j

TI

SNl5830
SN15832
SN15833
SN15835
SN15836
SN15837
SN15844
SN15845
SN15846

NATIONAL DIRECT
REPLACEMENT

DM930
DM932
DM933
DM935
DM936
DM937
DM944
DM945
DM946

xxiii

~. TTL Data Book

Functional Index/Selection Guides

The following pages contain functional indexes and selection guides designed to simplify the choice of a particular function to
fit a specific application. Essential characteristics of similar or like functions are grouped for comparative analysis, and the
electrical specifications are referenced by page number. The following categories of functions are covered:

SSI FUNCTIONS
·AND Gates with Totem-Pole Outputs . . . . . . . . . . . . .
AND Gates with Open-Collector Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AND-OR-INVERT Gates with Totem-Pole Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ANDwOR-INVERT Gates with Open-Collector Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . .
Buffers/Clock Drivers with Totem-Pole Outputs . . . . . ' ....' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . ..

Buffer and Interface Gates with Open·Collector Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Interface Gates with TRI-STATE Totem-Pole Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Expandable Gates . . . . . . . . . . . . . . . . . . . . . . . . . . \. . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Expanders. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flip-Flops, Gated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flip·Flops, Single and Dual J·K Edge-Triggered. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flip·Flops, Dual D-Type. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flip·Flops, Single and Dual Pulse-Triggered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Latches, 'S-R .......................... " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Line Drivers, 50·0hm/75-0hm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
NAND Gates and Inverters with Open-Collector Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NAND Gates and Inverters with Totem-Pole Outputs . . . . . . . . . . . . . . . ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
NOR Gates with Totem·Pole Outputs . . . . . . . . . . . . . . . . . . . . . . . . .
One Shots, Retriggerable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

xxvi

xxvi
xxvi

xxvii
xxvii
xxvii

xxviii
xxviii
xxviii
xxviii
xxix
xxix
xxx
xxx
xxxi
xxxi
xxxi

xxxii
xxxii

xxxiii

One Shots with Schmitt-Trigger Inputs . . . . . .' " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. xxxiii

OR Gates with Totem-Pole Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . '.' . . . . . . . . . . . . . . . . . . . . . . . . . . . .. xxxiii
Schmitt·Triggers with Totem·Pole Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxiii

MSI FUNCTIONS
Adders ...
Accumulators, Arithmetic Logic Units, Look-Ahead Carry Generators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Arithmetic Operators . . . . .
Code Converters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Comparators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Counters, Asynchronous (Ripple Clockl-Negative·Edge Triggered. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Counters, Synchronous-Positive-Edge Triggered. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Data Selectors/Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Decoders/Demultiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Display Decoders/Drivers, Open-Collector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xxxiv

xxxiv
xxxiv

xxxiv
xxxv
xxxv
xxxvi
xxxvii
xxxviii
xxxviii
xxxix

Multipliers . . . . . . . . . . . . . . . . . ~ . . . . . . . . . . . . . . " . ; . " . . . . . . . . .' . . . . . . . . . . . . . . . . . . . . . . . . . . .. xxxix
Parity Generators/Checkers. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. xxxix

Priority Encoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , xxxix
xxxix
Register Files.
xl
Registers, Other . . . . . . . . . . . . . . . . . : . . . . . . . . . . . . . . . . . . . . . . . . .
xl
Registers, Sh if! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xxv

~

Functional Index/Selection Guides

SSI Functions

AND GATES WITH TOTEM-POLE OUTPUTS

Description
Dual4-lnput AND Gates

Triple 3-lnput AND Gates

Quad 2-lnput AND Gate.

Typ_

Typ. Power

Propagation

Dissipation

Delay Time

Per Gate·

8_2 ns

40mW

12 ns

4.25mW

4.75 ns

31 mW

8.2 ns

40mW

12 ns

Device Type and Package
Mil_

Connection
Diagram

Com!.

" - No_

Electrical

Table. Page No_

54H21

J,N

74H21

J,N

1-7

1-44

54 LS21

J,N,W

74LS21

J,N

1-7

1-44

74511

N

1-5

1-44

54Hll

J,N

74Hll

J,N

1-5

1-44

4.25 mW

54LS11

J,N,W

74LSll

J,N

1-5

1-44

12 ns

4.25 mW

54 LS08

J,N,W

74LS08

J,N

1-4

1-44

15 ns

19mW

5408

J,N,W

7408

J,N

1-4

1-44

AND GATES WITH OPEN-COLLECTOR OUTPUTS
Typ.

Description

Triple 3-lnput AND Gates

Quad 2-lnput AND Gates

ProP89ation
Delay Time

Typ. Power
Dissipation

Connection

Device Type and Package

Diagram
Mil.

Per Gate

Page No.

Coml.

y

Electrical

Tables Page No.

6 ns

28mW

74S15

N

1-6

1-46

20 ns

4.25 mW

54L515

J,N,W

74LS15

J,N

1-6

1-46

18.5 ns

19.4mW

5409

J,N,W

7409

J,N

1-4

1-46

20 ns

4.25mW

54LS09

J,N,W

74LS09

J,N

1-4

1-46

AND-OR-INVERT GATES WITH TOTEM-POLE OUTPUTS

Description

2-Wide 4-lnput

Dual 2-Wide 2-lnput

TYp.

Typ. Power

Device Type and Package

Propagation
Delay Time

Dissipation
Per Gate

MiI_

12.5 ns

2.75mW

43 ns

1.5mW

3.5 ns

28mW

6.5 ns

Connection
D~agram

Page No.

Coml.

Electrical
Tablas Page No.

54 LS55

J,N,W

74LS55

J,N

1-15

1-56

54L55

J,N,W

74L55

J,N

1-15

1-56

74S51

N

1-12

1-56

29mW

54H51

J,N

74H51

J,N

1-12

1-56

10.5 ns

14mW

5451

J,N,W

7451

J,N

1-12

1-56

12.5 ns

2.75mW

54LS51

J,N,W

74LS51

J,N

1-12

43 ns

1.5mW

54L51

J,N,W

74L51

J,N

1-12

1-56
1-56 .
1-56

4-Wide 4-2-3-2-lnput

3.5 ns

29mW

74S64

N

1-16

4-Wide 2-2-3-2-lnput

6.6 ns

41mW

54H54

J,N

74H54

J,N

1-14

I-56

4-Wide 2-lnput

10.5 ns

23mW

5454

J,N,W

7454

J,N

1-14

4-Wide 2-3-3-2-lnput

12.5 ns

4.5mW

54LS54

J,N,W

74 LS54

J,N

1-14

'-56
1-56

4-Wide 2-3-3-2-lnput

43 ns

1.5mW

54L54

J,N,W

74L54

J,N

1-14

1-56

~

Functional Index/Selection Guides

551 Functions

AND-OR-INVERT GATES WITH OPEN-COLLECTOR OUTPUTS
Typ_

Description

Propagation
Delay Time

4-Wide 4-2-3-2-lnput

5.5 ns

Typ. Power
Dissipation
Per Gate

Device Type and Package
Mil.

Connection
Diagram

Coml.

36mW

74565

Page No.

J

N

Electrical
Tables Page No.
1-61

1-17

BUFFERS/CLOCK DRIVERS WITH TOTEM-POLE OUTPUTS
(ALSO SEE CLOCK GENERATOR CIRCUITS)
Low-Level

Description

Output
Current

High-Level
Output

Current

Typ.

Typ. Power

Delay

Per

Time

Device Type and Package

Coml

Mil.

Gate

Connection
Diagram
Page No.

Electrical

1-54

T~bles

Page No.

Dual4-lnput NAND

60mA

-3mA

4 ns

44mW

74S40

N

1·11

Buffers

60mA

-1.5mA

7.5 ns

44mW

54H40

J,N

74H40

J,N

1-11

1-54

48mA

-1.2 mA

10.5 ns

26mW

5440

J,N,W

7440

J,N

1-11

1-54

24 mA

-1.2 mA

12 ns

4.3mW

74L540

J,N

12mA

-1.2 mA

12 ns

4.3 mW

54 LS40

J,N,W

Quad 2-lnput NAND

48mA

-1.2 mA

10 ns

25mW

7091

J,N,W

8091

Buffers

48mA

-1.2 mA

10.5 ns

27mW

5437

J,N,W

7437

24mA

-1.2mA

12 ns

4.3mW

74L537

12mA

-1.2mA

12 ns

4.3mW

54LS37

1-11

1-54

1-11

1-54

J,N

3-3

3-4

J,N

1-10

1-54

J,N

1-10

1-54

1-10

1-54

J,N,W

BUFFER AND INTERFACE GATES WITH OPEN-COLLECTOR OUTPUTS
High-Level

Description

Output
Voltage

Low-level
Output

Typ.

Typ. Power

Delay

Per

Current

Time

Quad 2-lnput NAND

15V

16mA

13.5 ns

10mW

Buffers

15V

8 mA

16 ns

2 mW

15V

4mA

16 ns

2mW

5.5V

48mA

12.5 ns

24.4 mW

S.5V

24mA

19 ns

4.3mW

5.5V

12 mA

19 ns

4.3 mW

30V

40mA

13 ns

21 mW

30V

30mA

13 ns

21 mW

15V

40mA

13 ns

21 mW

Hex Buffers/Drivers

Device Type and Package

Gate

15V

30mA

13 ns

21 mW

Hex Inverter Buffers!

30V

40mA

12.5 ns

26mW

Drivers

30V

30mA

12.5 ns

26mW

15V

40mA

'12.5ns

26mW

15V

30mA

12.5 ns

26mW

xxvii

Coml.

Mil.
5426

J,N

54LS26

J,N,W

5438

J,N,W

54L538

J,N,W

5407
5417

5406

Page No.

J,N

1-9

1-42

74L526

J,N

1-9

1-42

1-9

1-42

7438

J,N

1-10

1-42

74LS38

J,N

1-10

1-42

1-10

1-42
1-42

7407

J,N

1-3
1-3

1-42

7417

J,N

1-7

1-42

1-7

.1-42

7406

J,N

1-3

1-42

1-3

1-42

1-6

1-42

1-6

1-42

J,N,W
J,N,W

J,N,W
J,N,W

Electrical
Tables

7426

7416
5416

Connection
Diagram
Page No.

J,N

~

SS! Functions

Functional Index/Selection Guides
BUS INTERFACE GATES WITH TRI-STATE TOTEM-POLE OUTPUTS

Description

Typ_
Propagation
Delay Time

Quad Bus Buffers.

Hex Bus Drivers

Hex I nverter Bus Drivers

12-lnput NAND Gates

Cpnnection
Diagram
Page No.

Device Type and Package

Dissipation

Mil.

Per Gate

Coml.

Electrical Tables
Page No.

10 ns

40mW

54125

J,N,W

74125

J,N

1·27

1-80

10 ns

45mW

54126

J,N,W

74126

J,N

1··27

1-80

10 ns

40mW

7093

J,N,W

8093

J,N

3-5

3-6

10 ns

45mW

7094

J,N,W

8094

J,N

3-5

3-6

9 ns

30mW

7099

J,N,W

8099

J,N

3-9

3-10

12 ns

54mW

54365

J,W

74365

J,N

1-32

1-86

12 ns

54mW

54367

J,W

74367

J,N

1-32

1-86

12 ns

54mW

7095

J,W

8095

J,N

3-7

3-8

12 ns

54mW

7097

J,W

8097

J,N

3-7

38

33 ns

3.3mW

70L95

J,N,W

80L95

J,N

3-7

3-8

33 ns

3.3mW

70L97

J,N,W

80L97

J,N

3'7

3-8

11 ns

49mW

54366

J,W

74366

J,N

1-32

1-86

11 ns

49mW

54368

J,W

74368

J,N

1-33

1-86

11 ns

49mW

7096

J,W

8096

J,N

3-7

3-8

11 ns

49mW

7098

J,W

8098

J,N

3-7

3'8

30 ns

2.5mW

70L96

J,N,W

80L96

J,N

3-7

3·8

30 ns

2.5mW

70L98

J,N,W

80L98

J,N

3·7

3-8

13 ns

10mW

"71 LS95

N

81 LS95

N

3-21

3-22

13 ns

10mW

71 LS97

N

81 LS97

N

'3-21

3-22

9.5 ns

8mW

71 LS96

N

81 LS96

N

3-21

3·22

9.5 ns

8mW

71 LS98

N

81 LS98

N

3-21

3-22

4.5 ns

45mW

74S134

N

1-28

1-80

Octal Drivers

Octal Inverter Drivers

Typ. Power

CLOCK GENERATORS
Typ. Total

Description

Device Type and Package

Dual Voltage-Controlled Oscillators

Connection

Electrical

Diagram
Page No.

Tables
Page No.

2-44

2-45

Power

Mil.

Dissipation
90 mW

54LS124

Coml.

I

J,N,W

I

74LS124

J,N

EXPANDABLE GATES

Description

Typ.
Propagation
Delay Time

Typ. Power
Dissipation

Device Type and Package
Coml.

Mil.

Per Gate

Connection
Diagram
Pelge No.

Electrical
Tables
Page No.

2-Wide AND-OR-INVERT Gates

6.B ns

30mW

54H55

J,N

74H55

J,N

1-15

1-50

Dual2-Wide AND-OR-INVERT Gates

6.5 ns

29mW

54H50

J,N

74H50

J,N

1-11

1-50

10.5 ns

14mW

5450

J,N,W

7450.

J,N

1-11

1-50

4-Wide AND-OR Gates

9.9 ns

88mW

54H52

J,N

74H52

J,N

1-13

1-50

4·Wide AND-OR-INVERT Gates

6.6 ns

41mW

54H53

J,N

74H53

J,N

1-13

1-50

10.5 ns

23 mil'!

5453

J,N,W

7453

J,N

1-13

1-50

10.5 ns

23mW

5423

J,N,W

7423

J,N

1-8

1-50

Dual4-lnput NOR Gates With Strobe

EXPANDERS

Description

Typ. Power
Dissipation

Device Type and Package
Mil.

Per Gate

Dual4-lnput Expanders

Coml.

Connection
Diagram
Page No.

Electrical Tables
Page No.
1-58

4mW

5460

J,N,W

7460

J,N

1-15

6mW

54H60

J,N

74H60

J,N

1-15

1-59

3-2-2-3-lnput AND-OR Expanaer~

25mW

54H62

J,N

74H62

J,N

1-16

1·59

Triple 3-lnput Expanders

13mW

54H61

J,N

74H61

J,N

1-16

1-60

xxviii

~

Functional Index/Selection Guides

SSI Functions

FLIP-FLOPS, GATED
Typ. Characteristics

Data Times

fMAX
(MHzl

Pwr/F-F

Setup

(mWI

(nsl

45

105

15

30

73

24

28

110

15

10

8.0

110

9

9.3

80

7

7.3

100

Device Type and Package

-

Hold
(nsl

a
a
a
a
a
a

Mil_

Coml.

Connection
Diagram
Page No.

Electrical Tables
Page No.

7511

J,N,W

8511

J,N

3-40

3-41

7613

J,N,W

8613

J,N

3-40

3-41

7512

J,N,w

8512

J,N

3-40

3-41

75L12

J,N,W

85L12

J,N

3·40

3-41

75L11

J,N,W

85L11

J,N

3·40

3-41

76L13

J,N,W

86L13

J,N

3-40

3·41

FLIP-FLOPS, SINGLE AND DUAL J-K EDGE TRIGGERED
Typ. Characteristics
Dwg.

Data Times

Pwr/F·F

Setup

Device Type and Package

Hold
(nsl

Ref.

fMAX
(MHzl

{mWI

(nsl

A

125

75

61

at

50

100

131

01

54Hl06

45

10

201

01

45

10

201

01

125

75

61

01

50

100

131

01

54Hl08

45

10

201

01

45

10

201

01

125

75

61

0:

45

10

201

01

54LS113

50

100

13j

OJ

54Hl03

45

10

201

01

45

10

20,

OJ

40

45

1,51

101

33

10

201

51

33

45

101

35

65

201

B

C

D

E

F

Mil.

Com I.
N

1·24

1·70

J,N

74Hl06

J,N

1·23

174

54LS76

J,N,W

74LS76

N

1-21

1·68

54LSl12

J,N,W

74LSl12

J,N

1·24

1-68

745114

N

1·25

1·70

J,N

74Hl08

J,N

1·24

1·74

54LS78

.J,N,W

74LS78

J,N

1·21

1·68

54LSl14

J,N,W

74LS114

J,N

1·25

1·68

74S113

N

1-25

1·70

J,N,W

74LS113

J,N

1·25

1·68

J,N

74Hl03

J,N

1·23

1·74

54LS73

J,N,W

74LS73

J,N

1·20

1·68

54LS107

J,N

74LS107

J,N

1·23

1·68

9024

J,N,W

8024

J,N

4·17

4-17

54LS109

J,N,W

74LS109

J,N

1·24

1-68

61

54109

J,N,W

74109

J,N

1·24

1-62

51

5470

J,N,W

7470

J,N

1·18

1·62

(B)

Ur-

-<: CK

-J

T~:r

-J

--<

CK

01-

CLEAR

F·F_ K

Ii-

--(

CK

-T

-K

(E)

of--

-

TO OTHER
F·F

xxix

--Jru-

a-

K

or--

-J

-.
-

CK

CLEAR

'-----

(F)

PRESET

0-

-J

OTHER

or-

-K

for the falling edge.

-

PRESET

u-

~

(D)

(e)

.-Jm

PRESET

-J

Electrical
Tables
Page No.

74S112

t ~ The arrow indicates the edge of the clock pulse used for reference: t for the rising edge,

(AI

Connection
Diagram
Page No.

CK

arClEAR

~

~

0-

J
CK

K

a-

==r-

~

SSI Funct.ions

Functional Index/Selection Guides

""

FlIp·FlOPS, DUAL D·TVPE
Typ. Characteristics

DatalTimes

Connection
Diagram

Device Type and Package

Electrical
Tables
Page No.

Dwg.
Ref.

fMAX
(MHz)

G

110

75

31

2t

74S74

N

1-20

1-70

43

75

15t

5t

54H74

J,N

74H74

J,N

1-20

1-64

54LS74

J,N,W

1-20

1-68

J,N,W

74LS74
7474 .

J,N

5474

J,N

1-20

1-62

54L74

J,N,W

74L74

J,N

'-20

'-66

Connection
Diagram
Page No.

Electrical
Tables
Page No.

Pwr/F·F
(mW)

Hold
(ns)

Setup
(ns)

33

10

25t

25

43

20t

5t
5t

6

4

50t

15t

"Mil.

Page No.

Coml.

t.J. The arrow indicates the edge of the clock pulse used for reference: ffor the rising edge, t for the falling edge.

(G)
PRESET

-

0-

0

--(

CK

il;-CLEAR

FlIP·FlOPS, SINGLE AND DUAL PUlSE·TRIGGERED
Typ. Characteristics
Dwg.
Ref.

Data Times

Device Type and Package

fMAX
(MHz)

Pwr/F·F

Setup

(mV\()

(ns)

Hold
(ns)

30

80

Ot

01

54H73

J,N

74H73

JN

1-20

1-64

20

50

at

01

5473

J,N,W

7473

J,N

1-20

1-62

20

50

at

01

54107

J.N

74107

J,N

'-23

1·62

6

3.8

at

01

54L73

J,N,W

74L73

J.N

1·20

1·66

30

80

at

01

54H76

J.N

74H76

J.. N

1·21

1·64

20

50

ot

01

5476

J,N,W

7476

J,N

1·21

1·62

30

80

at

0;

54H78

J,N

74H78

J,N

1·21

1·64

6

3.8

ot

01

54L78

J,N,W

74L78

J,N

1·21

1·66

K

30

80

at

01

54H71

J,N

74H71

J,N

1·18

1·64

L

30

80

at

01

54H72

J,N

74H72

J,N

1·19

1·64

20

50

at

01

5472

J,N,W

7472

J,N

1-19

1·62

6

3.8

at

01

54172

J,N,W

74L72

J,N

1·19

1·66

6

3.8

at

01

54171

J,N.W

74L71

J;N

1·19

1·66

H

I

J

,

M

/II

(H)

--(

(J)

of-- -

CK

-K

--<
ilf-- -

CLEAR

0-

J

T~:r

CK

il;--

K

CLEAR

-J

III

ilf--

T-

(M)

~~- I;~r I;~~

of--

CK

OTHER
F·F_ K

Coml.

(K)

r-Jm

PRESET

-J

Mil.

TO OTHER
F·F

~

CK

-

K

xxx

CK

ill-

'--

K

.

CK

ill-

~

R

ill-

-"T-

~

Functional Index/Selection Guides

SSI Functions
LATCHES,

Description

Quad

S~R

Typ.

Typ. Total

Propagation

Power

Delay Time

Dissipation

12 ns

19mW

Latches

S-R
Connection
Diagram

Device Type and Package

I
I

Mil.
54L5279

I

J,N,W

Coml.

I

74L5279

J,N

Electrical

Page No.

Tables
Page No.

2-168

2-169

LINE DRIVERS, 50-0HM/75-0HM

Description

Dual4-lnput NAND Line

Current

Typ_
Delay
Time

Typ. Power
Per
Gate

-40 rnA

4 ns

44mW

Low~level

High-Level

Output

Output

Current

60 rnA

Device Type and Package

Coml.

Mil.

745140

I

Connection

Electrical

Diagram
Page No.

Tables
Page No.

1-29

1-54

N

Drivers

.
NAND GATES AND INVERTERS WITH OPEN-COLLECTOR OUTPUTS

Description

Dual4-lnput NAND Gates

Typ_

Typ. Power

Propagation

Dissipation

Delay Time

Per Gate

Mil.

Diagram
Page No.

Coml.

Electrical
Tables
Page No.

5 ns

17.5mW

74522

N

1-8

1-38

8 ns

22mW

54H22

J,N

74H22

J,N

1-8

1-38

16 ns

2mW

54L522

J,N,W

74L522

J,N

1-8

1-38
1-38
1-38

54L512

Triple 3-lnput NAND Gates

16 ns

2mW

Quad 2-lnput NAND Gates

5 ns

17.5 mW

8 ns

22mW

54HOl

16 ns

2mW

54L501

Hex Inverters

Connection

Device Type and Package

J,N

1-5

74S03

N

1-2

J.N

74HOl

J,N

1-1

1-38

J,N,W

74L501

J,N

1-1

1-38

J,N,W

74L512

16 ns

2mW

54L503

J,N,W

74L503

J,N

1-2

1-38

22 ns

10mW

5401

J,N,W

7401

J,N

1-1

1-38

22 ns

10mW

5403

J,N

7403

J,N

1-2

1-38

41 ns

1 mW

54LOl

W

74LOl

W

1-1

1-38

54L03

J,N

74103

J,N

1-2

1-38

80LOG

N

3-1

3-2
1-38

410s

1mW

115 ns

1.8mW

5 ns

17.5mW

8 ns

22mW

16 ns

2mW

22 ns

10mW

74S05

N

1-3,

54H05

J,N

74H05

J,N

1-3

1-38

54L505

J,N,W

74L505

J,N

1-3

1-38

5405

J,N,W

7405

J,N

1-3

1-38

.
'

.

~

551 Functions

Functional Index/Selection' Guides
NAND GATES AND INVERTERS WITH TOTEM-POLE OUTPUTS
Typ.

Description

Typ. Power
Dissipation

Propagation
Delay Time

Connection

Device Type and Package

Coml.

Mil.

Per Gate

Electrical

Diagram

Tables

Page No.

Page No.

3 ns

19 mW

74S20

J,N

1-7

1·36

6 ns

22mW

54H20

J,N

74H20

J,N

1·7

1·36

9,5 ns

'2 mW

54LS20

J,N,W

74LS20

J,N

1·7

1·36

10 ns

10mW

5420

J,N,W

7420

J,N

1·7

1-36

33 ns

1 mW

54L20

J,N,W

74L20

J,N

1-7

1-36

Dual 5-lnput NAND Gates

10 ns

20mW

7092

J,N,W

8092

J,N

3-3

3-4

Triple 3-lnput NAND Gates

3 ns

19mW

74S10

J,N

1-4

1-36

6 ns

22mW

54Hl0

J,N

74Hl0

J,N

1-4

1-36

9.5 ns

2mW

54LS10

J,N,W

74LSlO

J,N

1-4

1-36

10 ns

lOmW

33 ns

1 mW

Dual 4·lnput NAND Gates

Quad 2-1 nput NAND Gates

3 ns

19 mW

6 ns

22 mW

9.5 ns

2 mW

os

10mW

33 ns

1 mW

3 ns

19 mW

6 ns

22mW

10

Hex Inverters

•

7410

J,N

1-4

1-36

J,N,W

74L 10

J,N

1-4

1-36

74S00

N

1-1

1-36

54HOO

J,N

74HOO

J,N

1-1

1-36

54LSOO

J,N,W

74LSOO

J,N

1-1

1-36

5400

J,N,W

7400

J,N

1-1

1-36

54LOO

J,N,W

74LOO

J,N

1·1

1-36

74S04

N

1-2

1-36

J,N

74H04

J,N

1-2

1-36
1-36

54H04

2mW

54 LS04

J,N,W

74LS04

J,N

1-2

10 ns

10mW

5404

J,N,W

7404

J,N

1-2

1-36

11 ns

18mW

7090

J,N,W

8090

J,N

3-3

3-4

54L04

J,N,W

74L04

J,N

1-2

1-36

74S30

J,N

1-9

1-36

33 ns

1 mW

3 ns

19mW

6 ns

22mW

54H30

J,N

74H30

J,N

1-9

1-36

10 ns

10mW

5430

J,N,W

7430

J,N

1-9

1-36

54 LS30

J,N,W

74LS30

J,N

1-9

1-36

54L30

J,N,W

74L30

J,N

1-9

1-36

74S133

N

1-28

1-36

ns

2.4 mW

·33 ns

1 mW

3 ns

19mW

17

13-lnput NAND Gates

J,N,W

9.5 ns

,

8-lnput NAND Gates

5410
54Ll0

NOR GATES WITH TOTEM-POLE OUTPUTS
Typ.

Description

Dual 4-1 nput NOR Gates With Strobe
Dual 5-1 nput NOR Gates
Triple 3-lnput NOR pates

..

Quad 2-1 nput' NOR Gates

!

Propagation

Typ. Power
Dissipation

Delay Time

Per Gate

10.5 ns

23 mW

4 ns

54mW

8.5 ns

22mW

'10 ns

4.5 mW

3.5 ns

29mW

10 ns

2.75mW

10 ns
33 ns

Connection
Diagram

Device Type and Package
Coml.

Mil.
5425

Page No.

J,N,W

. Electrical Tables

Page No.

7425

J,N

1-8

1-40

74S260

N

1-31

1-40

5427

J,N,W

7427

J,N·

1-9

1-40

54 LS27

J,N,W

74LS27

J,N

1-9

1-40

74S02

N

1-2

1-40

54LS02

J,N,W

74 LS02

J,N

1-2

1-40

14mW

5402

J,N,W

7402

J,N

1-2

1-40

1.5mW

54L02

J,N,W

74L02

J,N

1-2

1-40

'.

~

Functional Index/Selection Guides

SSI Functions

ONE SHOTS, RETRIGGERABLE
No. of Inputs

Description

Dual

Device Type and Package

Typ.

Output
Pulse

Total

Range

Power

Connection
Diagram
Page No.

Electrical
Tables

Negative

Clear

2

2

Yes

45 ns- oo

30mW

54LS122

J.N,W

74LS122

J,N

1·26

1·78

2

2

Yes

50 ns-oo

90mW

9601

J,N,W

8601

J,N

4-43

4-44

1

1

Yes

45 ns- oo

230 mW

54123

J,N.W

74123

J,N

1-26

1-78

1

1

Yes

90

ns-~

25mW

54L 123A

J,N,W

74L 123A

J,N

1-26

1-78

1

1

Yes

45 ns- oo

60mW

54LS123

J,N,W

74LS123

J,N

1-26

1-78

1

1

Yes

72 ns·- oo

195mW

9602

J,N,W

8602

J,N

4-46

4-47

2

2

Yes

72 ns- oo

275 mW

7853

J,N,W

8853

J,N

3-151

3-152

Positive

Single

Direct

Mil.

Coml.

Page No.

ONE SHOTS WITH SCHMITT·TRIGGER INPUTS
Output
Pulse
Range

No. of Inputs

Description

Negative

1

2

40 ns-28

5

90mW

1

1

20 ns-70 s

23mW

1

1

20 ns-49 s

23 mW

Single

Dual

Device Type and Package

Typ. Total
Power
Dissipation

Positive

Connection

Coml.

Mil.
54121

J,N,W

54LS221

J,N,W

Electrical

Diagram

Tables

Page No.

Page No.
1-76

74121

J,N

1-26

74LS221

J,N

1-30

1-76

1-30

1·76

Connection
Diagram
Page No.

Electrical
Tables
Page No.

OR GATES WITH TOTEM-POLE OUTPUTS
Typ.

Description

Quad 2-lnput OR Gates

Propagation
Delay Time

12 ns
12 ns

Typ. Power
Dissipation
Per Gate
24mW
5mW

Device Tvpe and Package
Mil.
5432

I

54LS32

Coml.
J,N,W

7432

J,N

1-10

1-52

J,N,W

74LS32

J,N

1-10

1-52

Connection
Diagram
Page No.

Electrical
Tables

SCHMITT-TRIGGERS WITH TOTEM-POLE OUTPUTS

Description

Typ.

Device Type and Package

Typ.

Hysteresis

Delay
Time

Mil.

Coml.

Page No.

Dual4·lnput NAND

0.8V

16.5 ns

5413

J,N,W

7413

J.N

1-5

1-48

Schmitt Triggers

0.8V

16.5 ns

54LS13

J.N,W

74LS13

J,N

1-5

1-48

Quad 2·lnput NAND

0.8V

15 ns

54132

J.N,W

74132

J,N

1-27

1-48

Schmitt Triggers

0.8V

15 ns

54LS132

J,N,W

74LS132

J,N

1-27

1·48

Hex Schmitt Trigger Inverters

0,8V

15 ns

5414

J,N,W

7414

J,N

1-6

1-48

0.8V

15 ns

54LS14

J,N,W

74LS14

J,N

1-6

1-48

xxxiii

~

Functional Index/Selection Guides

MSI Functions
ADDERS
Typ.
Description

Carry
Time

Typ.
Add
Time

Typ. Power
Dissipation

10 ns

15 ns

24mW

54LS83A

J,N,W

74LS83A

J,N

2-17

2·18

10 ns

15 ns

24mW

54L~283

J,N,W

74LS283

J,N

2·17

2·18

10 ns

16 ns

76mW

5483

J,W

7483

J,N

2·17

2-18

Singl. 4-Bit Full Adders

Device Type and Package

Conneetion

Diagram
Mil.

Per Bit

Coml.

Page No.

Electrical
Tables
Page No.

ACCUMULATORS, ARITHMETIC LOGIC UNITS, LOOK-AHEAD CARRY GENERATORS
Typ,
Description

4~Bit

Typ. Tot.1

Time

Typ.
Add
Time

12.5 ns

24 ns

455mW

10 ns

20 ns

720mW

Carry

Arithmetic Logic Units!

Device Type and Package

Power

Mil.

Dissipation

Coml.

54181

J

Connection

Electrical

Diagram
Page No.

Table.
Page No,

74181

J,N

2·107

2-109

745281

N

2·173

2-174

74S182

N

2·113

2-114

74182

J,N

2-113

2·114

Function Generators

4·8it Parallel Binary
Accumulators
Look-Ahead Carry Generators

7 ns

260mW

13 ns

180mW

64182

J

ARITHMETIC OPERATORS
Typ.
Delay
Time

Description

Quad 2-ln"ut EXCLUSIVE-NOR

Typ. Total

Device Type and Package

Power

Mil.

Dissipation

Coml.

Connection

Electrical

Diagram
Page No.

Tables
Page No.

18 ns

40mW

54LS266

J,N,W

74LS266

J,N

1-31

1-84

18 ns

30mW

54LS136

J,N,W

74LS136

J,N

1·29

1·84

Gates
Quad 2·lnput EXCLUSIVE-OR

Gates With Open Collector Outputs
Quad 2-lnpu, EXCLUSIVE·OR
Gates with

Totem~Pole

Outputs

Quad EXCLUSIVE-OR/NOR

7 ns

250mW

74S86

N

1-22

1·72

10 ns

30mW

54LS86

J,N,W

74LS86

J,N

1-22

1-72

10 ns

30mW

54LS386

J,N,W

74LS386

J,N

1·34

1-72

14 ns

150mW

5486

J,N,W

7486

J,N

1·22

1-72

29 ns

15mW

54L86

J,N,W

74L86

J,N

1·22

1-72

8 ns

325mW

745135

N

1·28

1·82

Gates

CODE CONVERTERS

Description

Typ.
Delay Time
Per Package
Level

6-Bit Binary to 6-Bit BCD Gonverters

Device Type and Package

Typ. Total

Connection

Power

Diagram

Dissipation

25 ns

280mW

31 ns

350mW

6-Line BCD to 6-Line Binary, or

25 ns

280mW

4·Lin. to 4-Line BCD 9'.fBCD 10'.

31 n.

350mW

54185A

54184

Converters

xxxiv

Page No.

Coml.

Mil.
J,W

J,W

Electrica'
Table.
Page No,

,74185A

J,N

2·116

2·117

8899

N

3-156

3-157

74184

J,N

2·116

2-117

8898

N

3-156

3-157

~

Functional Index/Selection Guides

MSI Functions
COMPARATORS

Description

Typ.

Typ. Total

Compare

Power

Diagram

Page No.

Electrical
Tables
Page No.
3-24

4·8it Magnitude Comparators

6·8it Magnitude Comparators

10-8 it Magnitude Comparators

Connection

Device Type and Package
Mil.

Coml.

Time

Dissipation

20 ns

175mW

7200

J,N,W

8200

J,N

3-23

21 ns

275 mW

5485

J,W

7485

J,N

2-21

2-22

70 ns

20mW

54L85

J,N,W

74L85

J,N

2-21

2-22

70 ns

75mW

76L24

J,N,W

86L24

J,N

3-131

3-132

20 ns

250 mW

7131

J,w

8131

J,N

3-19

3-20

20 ns

250 mW

7136

J,W

8136

J,N

3-19

3-20

21 ns

205mW

7160

J,W

8160

J,N

3-17

3-18

21 ns

240mW

7130

J,F

8130

J,N

3-17

3-18

Connection

Electrical

Diagram
Page No.

Tables
Page No.

COUNTERS, ASYNCHRONOUS (RIPPLE CLOCK) - NEGATIVE-EDGE TRIGGERED

Description

4-Bit Binary

Decade

Divide by 12

Device Type and Package

Typ, Total

Freq.

Parallel
Load

Clear

50 MHz

Yes

Low

240mW

54197

J,N

74197

J,N

2-101

2-102

40 MHz

Yes

Low

150mW

7291

J,N,W

8291

J,N

4-11

4-12

35 MHz

Yes

Low

150mW

54177

J

74177

J,N

2-101

2·102

35 MHz

Yes

Low

150mW

7281

J,W

8281

J,N

4-11

4-12

32 MHz

None

High

39mW

54LS93

J,N,W

74LS93

J,N

2-30

2-31

32 MHz

None

High

160mW

5493A

J,W

7493A

J,N

2-30

2-31

30 MHz

Yes

Low

60mW

54LS197

J,N,W

74L5197

J,N

2-101

2-102

6 MHz

None

High

20mW

54L93

J,N,W

74L93

J,N

2-30

2-31

6 MHz

None

High

20mW

76L93

J,N,W

86L93

J,N

3-142

3-143

Count

Power

Com I.

Mil.

Dissipation

50 MHz

Yes

Low

240mW

54196

.I,N

74196

J,N

2-101

2-102

40 MHz

Yes

Low

150mW

7290

J,N,W

8290,

J,N

4-11

4-12

35 MHz

Yes

Lo'w

150mW

54176

J

74176

J,N

2-101

2-102

35 MHz

Yes

Low

150mW

7280

J,W

8280

J,N

4-11

4-12

32 MHz

Set-to-9

High

40mW

54LS90

J,N,W

74LS90

J,N

2-30

2-31

32 MHz

Set-to-9

High

160mW

5490A

J,W

7490A

J,N

2-30

2-31

30 MHz

Yes

Low

60mW

54LS196

J,N,W

74LS196

J,N

2-101

2·102

54L90

J.N,W

74L90

J.N

2-30

2-31

7288

J,W

8288

J,N

4-11

4-12

6 MHz

5et-to-9

High

20mW

35 MHz

Yes

Low

150mW

32 MHz

None

High

39mW

54LS92

J,N,W

74LS92

J,N

2·30

2·31

32 MHz

None

High

160mW

5492A

J,W

7492A

J,N

2-30

2-31

xx:xv

~

Functional Index/Selection Guides

MSI Functions

COUNTERS, SYNCHRONOUS-POSITlVE·EDGE TRIGGERED
Typ. Total
Description

4-Bit Binary

Count

Device Type and Package

Connection
Diagram

Electrical

Freq.

Parallel
Load

25 MHz

Sync

Sync·L

93 mW

54lS163

J,N,W

74LS163

J,N

2·70

2·71

25 MHz

Sync

Async-L

93 mW

54LS161

J,N,W

74LS161

J,N

2·70

2·71

25 MHz

Sync

Sync·L

305mW

54163A

J,W

74163A

J,N

2·70

2·71

25 MHz

Sync

Async-L

305mW

54161A

J,W

74161A

J,N

2·70

2·71

25 MHz

Sync

Async-L

305mW

9316

J,W

8316

J,N

4·27

4·28

25 MHz

Sync

Sync·L

375mW

7556

J.W

8556

J,N

3·72

3·73
3·138

Clear

Power

Mil.

Dissipation

Coml.

Page No.

Tables
Page No.

6MHz

Sync

Async-L

33 mW

76L76

J,N,W

86L76

J,N

3·137

4-Bit Binary

25 MHz

Sync

None

100mW

54LS169

J,N,W

74LS169

J,N

2·85

2· 86

Up/Down

25 MHz

Async

Async-H

85mW

54LS193

J,N,W

74LS193

.J,N

2·133

2·134

20 MHz

Async

Async-H

325mW

54193

J,W

74193

J,N

2·133

2·134

20 MHz

Async

Async-H

325mW

7563

J.W

8563

J,N

3·76

3·77

54LS191

J.N,W

74LS191

J,N

2·128

2·129

54191

J.N,W

74191

J,N

2·128

2·129

Decade

20 MHz

Async

None

90mW

20 MHz

Async

None

325 mW

6 MHz

Async

Async·H

40mW

54L 193

J,N,W

74L 193

J,N

2·133

2·134

Async-H

40mW

75L63

J,N,W

85L63

J,N

3·76

3·77

J,N

2·70

2·71

2·70

2·71
2-71

6 MHz

Async

25 MHz

Sync

Sync·L

93 mW

54LS162

J,N.W

74LS162

25 MHz

Sync

Async-L

93mW

54LS160

J,N,W

74LS160

J,N

25 MHz

Sync

Sync·L

305mW

54162A

J,W

74162A

J,N

2-70

25 MHz

Sync

Async-L

305mW

54160A

J.W

74160A

J,N

2·70

2·71

25 MHz

Sync

Async-L

305mW

9310

J,W

8310

J,N

4·27

4·28

400mW

7555

J,W

8555

J,W

3·72

3-73

76L75

J,N.W

S6Ll5

J,N

3·137

3-138

2-85

2·86

25 MHz

Sync

Sync-L

6 MHz

Sync

Async-L

33 mW

Decade

25 MHz

Sync

None

100mW

54LS168

J,N,W

74LS168

Up/Down

25 MHz

Async

Async-H

85mW

54LS192

J,N,W

74LS192

20 MHz

Async

Async-H

325mW

54192

J,W

Modulo·N

J,N
' J,N

2·133

2·134

74192

J,N

2-133

2·134
2·129

20 MHz

Async

None

100mW

54LS190

J,N,W

74LS190

J,N

2·128

20 MHz

Async

None

325mW

54190

J,N,W

74190

J,N

2·128

2·129

20 MHz

Async

Async~H

325mW

7560.

J,W

8560

J,N

3·76

3-77

6 MHz

Async

Async~H

40mW

54L 192

J,N,W

74L192

J,N

2·133

2·134

6 MHz

Async

Async·H

40mW

75L60

J,N,W

85L60

J,N

3-76

3·77

15 MHz

Sync

None

250mW

7520

J.W

8520

J,N

3-44

347

Divider

xxxvi

~

Functional Index/Selection Guides

MSI Functions

DATA SELECTORS/MUL TlPLEXERS
Typ. Delay Times
Description

Quad 2-Li ne to

l-Line

Type
of
Output
TRI·
STATE

Data to
Inv.
Output

4 ns

TRI-

5 ns

STATE

Standard

4 ns
5 ns

Standard
TRISTATE

12 ns

TRI-

12 ns

STATE
Standard

7 ns

l-Line

2·165

2·166

N

2·66

2-67

74S157

N

2·66

2-67

J,N,W

74LS258

J,N

2-165

2-166

54LS257

J,N,W

74LS257

J,N

2·165

2·166

54LS158

J,N,W

74LS158

J,N

2.£6

2-67

54LS157

J,N,W

74LS157

J,N

2.£6

2·67

54157

J,W

74157

J,N

2.£6

2·67

54L157A

J,N,W

74L 157A

J,N

2.£6

2-67

9322

J,W

8322

J,N

4·38

4·39

71L22

J,N,W

81L22

J,N

3·13

3·14

7123

J,W

8123

J,N

3·13

3·14

8 ns

250mW

20 ns

35mW

54LS258

20 ns

50mW

12 ns

24mW

Standard

40 ns

60 ns

15mW

9 ns

14 ns

150mW

Mil.

Coml.

40 ns

60 ns

15mW

9.5 ns

N/A

200mW

40 ns

N/A

20mW

71 L23

J,N,W

81L23

J,N

3-13

3·14

65mW

54LS298

J,N,W

74LS298

J,N

2·184

2·185

54LS253

J,N,W

20 ns
from
clock

TRI-

12 ns

16 ns

35mW

Standard

6 ns

9.5 ns

225mW

Standard

14 ns

17 os

180mW

Standard

14 ns

17 ns

31 mW

20 ns

20 ns

13.5 ns

4.5 ns

STATE

TRI·
TRISTATE
TRISTATE

J,N

2·163

2:164

N

2-57

2·58
2·58

54153

J,W

74153

J,N

2·57

J,N,W

74LS153

J,N

2-57

2·58

135mW

9309

J,W

8309

J,N

4·24

4·25

20 ns

170mW

7214

J,W

8214

J,N

3·28

3·29

8 ns

14 ns

275 mW

74S251

N

2-160

2·161

II ns

18 ns

17 ns

155mW

17 ns

21 ns

21 ns

35mW

12 ns

TRI·

STATE

74LS253
74S153

54LS153

STATE

16-Line to '-Une

N

74S158

195mW

Standard

Standard

B-Line-to '-Line

74S257

320mW

7 ns

150mW

Storage
Dual 4-Line to

2·166

14 ns

14 ns

Standard

2·165

74S258

9 ns

l-Line With

N

280mW

Standard

TRI·

Tables
Page No.

14 ns

49mW

STATE

Electrical

Diagram
Page No.

Dissipation

14 ns

STATE

Connection

Power

9 ns

TRI·

Device Type and Package

Typ. Total
From
Enable

Standard

Standard

Quad 2-line to

Data to
Non-Inv.
Output

54251

J,W

74251

J,N

2·160

2·161

54LS251

J,N,W

74LS251

J,N

2-160

2-161
2·54
2·54

Standard

4.5 ns

8 ns

9 ns

225mW

74S151

N

2-53

Standard

8 ns

16 ns

22 ns

145mW

54151A

J,W

74151A

J,N

2-53

Standard

11 ns

18 ns

27 ns

30mW

54LS151

J,N,W

74LS151

J,N

2·53

2-54

Standard

9 ns

16 ns

17 ns

135mW

9312

J,W

8312

J,N

4·24

4-25

Standard

11 ns

18 ns

17 ns

155mW

7121

J,W

8121

J,N

3·11

3·12

Standard

22 ns

N/A

100mW

7210

J,W

8210

J,N

3·25

3-26

Standard

22 ns

20 ns

100mW

7211

J,W

8211

J,N

3-25

3-26

11 ns

18 ns

200mW

54150

J,F

74150

J,N

2-53

2·54

II ns

21 ns

225mW

7219

J,F

8219

J,N

3-28

3-29

Standard
TRISTATE

,

xxxvii

~

MSI Functions

Functional Index/Selection Guides
DECODERS/DEMUL TIPLEXERS
Typ.
Select
Time

Type of
Output

Descriptio'n

T¥P·

Typ. Total

Device Type and Package

Enable
Time

Power
Dissipation

Mil.

Dual 2-Line to

Totem-Pole

7.5 ns

6 ns

300mW

4-Line

Totem-Pole

18 ns

15 ns

30mW

TRI-

Connection
Diagram

Coml.

Electrical

Tables
Page No.

Page No.

74S139

N

2,46

2-47

54LS155

J,N,W

74LS155

J,N

2·63

2·64

20 ns

15 ns

240mW

7230

J,W

8230

J,N

3-37

3-38

Totem-Pole

21 ns

16 ns

250mW

54155

J,W

74155

J,N

2·63

2·64

Totem-Pole

22 ns

19 ns

34mW

54LS139

J,N,W

74LS139

J,N

2-46

2·47

Open-Collector

23 ns

18 ns

250mW

54156

J,W

74156

J,N

2·63

2-64

Open-Collector

33 ns

26 ns

31 mW

54LS156

J,N,W

74LS156

J,N

2-63

2·64

74S138

N

2-46

2-47

54LS138

J,N,W

74LS138

J,N

2-46

2·47

7223

J

8223

J,N

3·35

3-36
2·4

STATE

3-Line to 8-Une

Totem-Pole

8 ns

7 ns

225mW

Totem-Pole

22 ns

21 ns

31 mW

Totem-Pole

25 ns

140mW

4-Une to 10-Line,

Totem-Pole

17 ns

35mW

54LS42

J,N,W

74LS42

J,N

2-3

BCD to Decimal

Totem-Pole

17 ns

140mW

5442

J,W

7442

J,N

2-3

2-4

Totem-Pole

20 ns

125mW

9301

J,W

8301

J,N

4·22

4·23

4-Lineto 16-Line

Totem-Pole

67 ns

54l42A

J,N,W

74L42A

J,N

2-3

2·4

Totem-Pole

19.5 ns

17.5 ns

170mW

54154

J,F

74154

J,N

2-60

2·61

Totem-Pole

19,5 ns

17,5 ns

170mW

9311

J,F

8311

J,N

4-33

4·34

Totem-Pole

23 ns

19 ns

45mW

54LS154

J,N,W

74LS154

J,N

2-60

2·61

Totem-Pole

55 ns

45 ns

24mW

54L 154A

F,J,N

74L154A

J,N

2·60

2-61

Connection

Electrical
Table.
Page No.

15mW

DISPLAY DECODERS/DRIVERS, OPEN·COLLECTOR

Curr'ent

Off·State
Output
Voltage

BCD to 7-

40mA

30V

320mW

Ripple

5446A

J,N,W

7446A

J,N

2·8

2-9

Segment

40mA

15V

320mW

Ripple

5447A

J,N,W

7447A

J,N

2-8

2·9

Decoders/Drivers

24mA

15V

35'mW

Ripple

74LS47

J,N

2-8

2·9

12mA

15V

35mW

Ripple

54LS47

J,N,W

2-8

2·9

6AmA

5.5V

265mW

Ripple

5448

J,N,W

6mA

5.5V

125mW

Ripple

4mA

5.5V

40mW

Direct

54LS49

J,N,W

2mA

5.5V

125mW

Ripple

54LS48

J,N,W

BCD to Decimal

80mA

30V

215mW

Invalid Codes

5445

J,W

7445

Decoders/Drivers

80mA

15V

215mW

Invalid Codes

54145

J,W

7 mA

60V

80mW

Invalid Codes

54141

3.6mA

2,4V

75mW

76L25

Output

Description

Sink

Typ. Total

Device Type and Package
Blanking

Power

Dissipation

Diagram
Mil.

Com!.

Page No,

7448

J,N

2-8

2-9

74LS48

J,N

2-8

2-9

74LS49

J,N

2-8

2·9

2-8

2·9

J,N

2-6

2·7

74145

J,N

2·6

2-7

J,W

74141

J,N

2-1

2·2

J,N,W

86L25

J,N

3·134

3-135

7-Segment to
BCD

Direct

Decoders/Drivers

RESULTANT DISPLAYS USING 46A, 47A, 48, LS47, LS48, LS49

/fl

C,j-Il

n

j
_ I_
-rjl-1~jl-l

~=1.=1
Lij~ijl-~_ _7
11
__77_7/_711_77/_

1-1

1

2

3

4

5

6

7

8

xxxviii

9

10

11

12

13

14

15

~

Functional Index/Selection Guides

MSI Functions
LATCHES
No.
of
Bits

Clear

Outputs

Typ.
Delay
Time

Typ. Total
Power
Dissipation

Addressable Latches

8

Low

a

21 ns

280mW

DG (Clocked) Latches

4

None

0,0

11 ns

4

None

10 ns

Description

Coml.

Electrical
Tables
Page No.
441

J,W

8334

J,N

440

32mW

54LS75

J,N,W

74LS75

J,N

2·14

2-15

35mW

54LS77

W

2·14

2-15

4

None

15 os

160mW

4

None

0,0

52 ns

17.5 mW

4

None

12 ns

19mW

4

None

19 ns

180mW

TAl-STATE

4

High

Counters/Latches

4

High

4

High

4

High

8

High

a
a
a
a
a
a
a

S-A Latches

Mil.

Connection
Diagram
Page No.

9334

a
a,a
-

Device Type and Package

28 ns

330mW

95 ns

38mW

28 ns

330mW

95 ns

38mW

21 ns

330mW

5475

J,N,W

7475

J,N

2'14

2·15

54L75A

J,N,W

74L75A

J,N

2'14

2-15

54LS279

J,N,W

74LS279

J,N

2-168

2-169

7544

J,N,W

8544

J,N

3-54

3-55

7552

J,W

8552

J,N

3-64

3-65

75L52

J,N,W

85L52

J,N

3-64

3-65

7554

J,W

8554

J,N

3-64

3-65

75L54

J,N,W

85L54

J,N

3-64

3-65

7553

J,W

8553

J,N

3-70

3-71

. MULTIPLIERS
Connection
Diagram
Page No.

Device Type and Package
Description
Mil.
4-Bit by 4·8it Parallel Binary Multipliers

Coml.

7875A

J

8875A

7875B

J

8875B

I

Electrical
Tables
Page No.

J,N

3-154

3-155

J,N

3-154

3-155

PARITY GENERATORS/CHECKERS
Typ.
Delay

Typ_ Total

Time

Dissipation

35 ns

170mW

9-Bit OddlEven Parity

13 ns

335mW

Generators/Checkers

34 ns

130mW

Description

8-Bit OddlEven Parity

Generators/Checkers

Connection
Diagram
Page No.

Electrical Tables
Page No_

J,N

2-105

2-106

745280

N

2-170

2-171

8220

J,N

3-32

3-33

Device Type and Package

Power
Mil.

Coml.

54180

J,W

74180

7220

J,N,W

PRIORITY ENCODERS
Typ.
Propagation
Delay Time

Description

Device Type and Package

Typ_ Total
Power
Dissipation

Connection

Electrical

Diagram
Page No.

Tables
Page No.

Coml_

Mil.

Cascadable Octal Priority

12 ns

190mW

54148

J,W

74148

J,N

249

2-50

Encoders

12 ns

190mW

9318

J,W

8318

J,N

4-36

4-37

10 ns

225mW

54147

J,W

74147

J,N

249

2-50

Full BCD Priority

Encoders

REGISTER FILES

Description

4 Words of 4-Bits

Typ_
Address

Time

Typ_ Aead
Enable
Time

Data
Input
Rate

Typ_ Total
Power
Dissipation

27 ns

15 ns

20 MHz

125mW

30 ns

15 ns

20 MHz

635mW

Connection
Diagram
Page No_

Device Type and Package
Mil.
54LS170

Coml.
J,N,W

Electrical
Tables
Page No_

74LS170

J,N

2-91

2-92

74170

J,N

2-91

2-92

4 Words of 4-Bits

24 ns

19 ns

20 MHz

135mW

54LS670

J,N,W

74LS670

J,N

2-191

2-192

(TRI-STATE Outputs)

24 ns

19 ns

30 MHz

400mW

7542

J,W

8542

J,N

3-52

3-53

xxxix

~

MSI Functions

Functional Index/Selection Guides
REGISTERS, OTHER

Description

Freq.

Quad Bus·Buffer Registers

Quad O·Type Registers

Quad Multiplexers
Wit~

Typ. Total

Async.

Electrical
Tables
Page No.

Connection

Device Type and Package

Diagram

Power

Clear

Mil.

Dissipation

Coml.

Page,Na.

25 MHz

High

250mW

54173

J,W

74173

J,N

2·96

2·97

25 MHz

High

250mW

7551

J,W

8551

J,N

3·62

3·63

75L51

J,N,W

85L51

j,N

3-62

3-63

74S175

N

2-98

2-99

'6 MHz

High

75 MHz

Low,

30 MHz

Low

55mW

25 MHz

Low

150mW

25 MHz

None

65mW

75 MHz

Low

450mW

30MHz

Low

80mW

25 MHz

Low

15 MHz

None

25 MHz

None

28mW
300mW

54LS175

J,N,W

74LS175

J,N

2-98

2-99

54175

J,W

74175

J,N

2-98

2-99

54LS298

J,N,W

74LS298

J,N'

2-184

74S174

N

2-98

2-99

54LS174

J,N,W

74LS174

J,N

2-98

2-99

225 mW

54174

J,W

74174

J,N

2-98

2-99

400mW

7546,

J,W

8546

J,N

3-56

3-57

175mW

54LS374

J,N,W

74LS374

J,N

2-187

2-188

,

2-185

Storage

Hex O·Type Registers

a-Bit Universal Shift/Storage
Registers
Octal D-Type Registers

REGISTERS, SHIFT

Description

No,
of
Bits

Serial
Data

Shift
Freq.

Input

Clear

. . ". "a
Modes

Async.

a: oJ
rh rh

0
oJ

:I:

Typ. Total

Device Type and Package

Power

Parallel-In,

8

25 MHz

D

Low

X X X X

360mW

Parallel-Out

4

70 MHz

D

Low

X X X X

450mW

(Bidirectional)

4

25 MHz

D

Low

X X X X

75mW

Com I.

Mil.

Dissipation
54198

J

Connection

Electrical

Diagram
Page No.

Tables
Page No.
2-149

74198

J,N

2-148

74S194

N

2-140

2-141

54LS194A

J,N,W

74LS194A

J,N

2-140

2-141

J,N

2-140

2-141

2-148

2-149

4

25 MHz

D

Low

X X X X

195mW

54194

J,W

74194

Parallel-In,

8

25 MHz

J-K

Low

X

X X

360mW

54199

J

74199

J,N

Paralrel-Out

5

10 MHz

D

Low

X

X

60mW

54LS96

J,N,W

74LS96

J,N

,2-39

2-40

5

10 MHz

D

Low

X

X

240mW

5496

J,W

7496

J,N

2-39

2-40

4

70 MHz

J-K

Low

375mW

74S195

N

2-144

2-145

30 MHz

J-R

Low

X
X

X

4

X

195mW

54195

J,W

74195

J,N

2-144

2-145

4

30 MHz

J-K

Low

X

X

300mW

9300

J,N,W

8300

J,N

4-19

4-20

4

30 MHz

J-K

Low

X

X

70mW

54LS195A

J,N,W

74LS195A

J,N

2-144

2-145

4

25 MHz

D

Low

X

X

75mW

54LS395

J,N,W

74LS395

J,N

2-189

2-190
2-37

-

4

25 MHz

D

None

X

X

195mW

5495

J,W

7495

J,N

2-36

4

25 MHz

D

None

X

X

65mW

54LS95B

J,N,W

74LS95B

J,N

2-36

2-37

4

6 MHz

D

None

X

X

24mW

54L95

J,N,W

74L95

J,N

2-36

2-37

Serial·ln,

8

25 MHz

Gated D

Low

X

80mW

54LS164

J,N,W

74LS164

J,N

2-76

2-77

Parallel-Out

8

25 MHz

Gated D

Low

X

175mW

54164

J,W

74164

J,N

2-76

2-77

8

25 MHz

Gated D

Low

X

175mW

7570

J,w

8570

J,N

3-86

3-87

8

6 MHz

Gated D

Low

X

30mW

54L 164A

J,N,W

74L164A

J,N

2-76

2-77

8

6 MHz

Gated D

Low

X

30mW

76L70

J,N;W

86L70

J,N

3-86

3-87
2-80

Parallel-I n,

8

25 MHz

D

None

X

X X

200mW

54165

J,W

74165

J,N

2-79

Serial-Out

8

20 MHz

D

Low

X

X X

360mW

54166

J

74166

J,N

2-82

2-83

8

14MHz

D

None

X

X X
X X

200mW

7590

J,W

8590

J,N

3-110

3-111
3-111

8

6 MHz

D

None

X

30mW

76L90

J,N,W

86L90

J,N

3-110

Serial-In,

8

10 MHz

Gated D

None

X

175mW

5491A

J,W

7491A

'J,N

2-34

2-35

Serial-Out,

8

4 MHz

Gated D

None

X

17,5mW

54L91

J,N,W

74L91

J,N

2-34

2-35

* S-R '" shift right, Sol '" shift left_

,

xl

~ TTL Data Book

Packages

DUAL-IN-LINE PACKAGES
(N)

All devi~es ordered with the oN" suffix are supplied in either the 14-pin, l.6-pin, 20-pin, or 24-pin molded dual-in-line
package. Molding material is EPOXV B, a highly reliable compound suitable for military as well as commercial temperature
range applications. Lead material is AIJoy 42 with a hot solder dipped surface to allow for ease of solderability.

(J)

All devices ordered with the "J" suffix are supplied in either the 14-pin, 16-pin, or 24-pin ceramic dual-in-line package.
The body of the package is made of ceramic and hermeticity is accomplished through a high temperature sealing of the
package. Lead material is tin-plated kovar.

FLAT PACKAGES
(W)

All devices ordered with the "W" suffix are supplied in either the 14-pin or 16-pin ceramic flat package. The'body of
the package is made of ceramic and hermeticity is accomplished through a high temperature sealing of the package.
Lead material is tin-plated kov~r.

(F)

All devices ordered with the of'' suffix are supplied in the 24-pin glass/metal flat package. The top and bottom of the
package are gold-plated kovar as are the leads. The side walls are glass, through which the leads extend forming a
hermetic seal.
Four combinations of bottom insulator and formed leads are supplied for the W or F packages. Suffix coding is as follows:

Suffix

Bottom Insulator

-00 (Ex: DM54LOOW-OO)
-01
-06
-07

Formed Leads

No
Ves
Ves
No

No
Ves
No
Ves

If no suffix is added, parts will be supplied as if the -00 suffix had been ordered.

~tr---±-~'-'~~-::l ""71~~

.it_______ .gA'~==~L_________~
if
te:=:=::~

O.O~~~J

0.000
0.005

I

1-------- 0.365--1
±0.005

Standard Flat Pack Lead Form

xli

~ TTL Data Book

Packages

~~~~~~~~~·,I--fG~

U25
RAD

0.025
RAD

D.28t1

MAX

'-T-:T'T'l'1'"T';''M'lT"1"";T'"I';T.,-;,-I~

0.2011

~

__11_ OJ. . . .125
'-0.002

80TH eNDS

14-Pin Ceramic Dual-In-Line Package CJI

8.810

MIN

16-Pin Ceramic Duel-In-Line Package (JI

"i~~~

.LASS

0.025
RAD

0.515

~~~~~~r.r~TW~~~~"'~
~~1.L

J

1-..... -I I- •..
tUGO ---,

_II--

011

10.010""1

0.•'8

!n.DOZ

.....

"070

MIN

24-Pin Ceramic Dual-In-Line Package '(JI

0.092 DIA NOM
PiN NO.1 INDENT

r·· 1 ~r

~
lJ
f ~m+"·" U-- Lo~
JD0

0.08&

~.3Z5 -o.a1fj-i

0.015
.8.01&

f---•.30. --1 r •
~fTMAX

0.138

it

.830

!

~::--\--

I -0 325 +0.025-1
,r·
.....015

. _
- TV'
-';-05:
.
~.o
.....
wo
8.

rJ ..... -=1f

......
0.015

I--- ---I TV,I-- -II---".m MiN

16-Pin Moldid Dual-In-Lina Package INI

14-Pin Molded Dual-In-Line Package (NI

xlii

8.1.1 0.125

~TTL Data Book

Packages

0.3oo--j

-0320
.
I

B.OlO
MAX

R=r------1+------,'"l

'~

H:

OO5

[1-,009
---0.010

I

I

TV'

\-0.]45 MAX-

20-Pin Molded Dual-In-Line Package (N)

---I

I
~~~~JD5

0.062

I

RAD

0.540

·L
F~"·
L~~5

0.0T5

,

_ I 1 __

0.015
±0.015

__

I
I

1--'

11.100
TYP

---II _
I

---1 oi"

11.018
iO.ODl

0.125 MIN
MIN

24-Pin Molded Dual-in-Line Package (N)

111~~111~ r

PIN NO.1

0.275

PIN NO.1
IDENT

MAX 0.840

0.275 0.880

lOENT

G~~~S 0.900

GLASS 0.B60

23""~

--.il

I

~
II
o.D19 --i1-0,015

14-Pin Flat Package (W)

0,015

II

~

D.019~f--

16-Pin Flat Package (W)

xliii

24-Pin Flat Package (F)

~ TTL Data Book

Packages

INCHES TO MILLIMETERS CONVERSION TABLE
INCHES

MM

INCHES

MM

INCHES

MM

0.001 .

0.0254

0.010

0.254

0.100

2.54

0.002

0.0508

0.020

0.508

0.200

5.08

0.003

0.0762
0.1016

0.030
0.040

0.762
1.016

0.300

7.62
10.16

0.005
0.006
0.007

0.1270
0.1524

1.270

0.1778

0.050
0.060
0.070

0.400
0.500

1.524
1.778

0.600
0.700

15.24
17.78

0.008

0.2032
0.2286

0.080
0.090

2.0.32

0.800
0.900

20.32

0.004

0.009

2.286

xliv

12.70

22.86

National Semiconductor
54f74 SSI DEVICES
Section 1

~

54/74 SSI
Device No.

Table of Contents
Conn.
Elec.
Diag.
Char.
Pg. No. Pg. No.

Description

~

DM5400/DM7400
DM54HOO/DM74HOO
DM54LOO/DM74LOO
DM54LSOO/DM74 LSOO
DM74S00
DM5401/DM7401
DM54H01/DM74HOl
DM54L01/DM74LOl
DM54LS01/DM74LSOl
DM5402/DM7402
DM54 L02/DM74 L02
DM54LS02/DM74LS02
DM74S02
DM5403/DM7403
DM54L03/DM74L03
DM54 LS03/DM74LS03
DM74S03
bM5404/DM7404
DM54H04/DM74H04
DM54L04/DM74L04
DM54LS04/DM74LS04
DM74S04
DM5405/DM7405
DM54H05/DM74H05
DM54L05/DM74L05
DM54LS05/DM74LS05
DM74S05
DM5406/DM7406
DM5407/DM7407
DM5408/DM7408
DM54H08/DM74H08
bM54L..08/DM74L08
DM54LS08/DM74LS08
DM5409/DM7409
DM54L09/DM14L09
DM 54 LS09/DM 74 LS09
DM5410/DM7410
DM54H10/DM74H10
DM54 L1 0/OM74L 10

Quad 2:lnput NAND 'Gates
Quad 2-lciput NAND-Gates
Quad 2-lnput NAND Gates
Quad 2-lnput NAND Gates
Quad 2-lnput'NAND Gates
Quad 2-lnput NAND Gates with
,open-Collector ,outputs
Quad 2-lnput NAND Gates with
,open-Collector ,outputs
Quad 2-lnput NAND Gates with
,open-Collector ,outputs
Quad 2-lnput NAND Gates with
,open-Coilector ,outputs
Quad 2-lnput N,oR Gates
Quad 2-lnput N,oR Gates
Quad 2-lnput N,oR Gates
Quad 2-1 nput N,o R Gates
Quad 2-lnput NAND Gates with
,open-Collector ,outputs
Quad 2-lnput NAND Gates with
,open-Collector ,outputs
Quad 2-1 nput NAN D Gates with
,open-Collector ,outputs
Quad 2-1 nput NAN D Gates with
Open-Collector ,outputs
Hex Inverters
Hex Inverters
Hex Inverters
Hex Inverters
Hex Inverters
Hex Inverters with ,open-Collector
,outputs
Hex Inverters with Open-Collector
,outputs
Hex Inverterswith ,open-Collector
,outputs
Hex I nverters with ,open-Collector
,outputs
Hex Inverters with Open-Collector
,outputs
Hex Buffers wjth ,open-Collector
High-Voltage ,outputs
Hex Buffers with ,open-Collector
High-Voltage ,outputs
Quad 2-lnput AND Gates
Ql.!ad 2-lnput AND Gates
Quad 2-lnput AND Gates
Quad 2-lnput ANDGates
Quad 2-lnput AND Gates with
,open-Collec~or ,outputs
Quad 2-lnput AND Gates with
,open-Collector ,outputs
Quad 2-If1put AND Gates with
,open-Collector ,outputs
Triple3-lnput NAND Gates
Triple 3_lnput NAND Gates
Triple 3-lnput NAND Gates

1·1
1-1
1-1

..

Mil

Coml

•
•
•
• N/A
•
•

1-'
1-1
1-1

1·36
1-36
1-36
1-36
1-36
1-38

1-1

1-38

1-1

1-38

N/A

1-1

1-38

1-2
1-2
1-2
1-2
1-2

1-40
1-40
1-40
1-40
1-38

•
•
•
• N/A
•

1-2

1-38

•

1-2

1-38

•

1-2

1-38

1-2
1-2
1-2
1-2
1-2
1-3

1-36,
. 1-36
1-36
1-36
1-36
1·38

1-3

1-38

1-3

1-38

1-3

1-38

1-3

1·38

1-3

1-42

"

1-3

1-42

•

1-4
1-4
1-4
1-4
1-4

l-n

J

I'"

1-44
1-44
1-44 '
1-44
1-46

1-4

1-46

1-4

1-46

1-4
1-4
1·4

1-36
1-36
1-36

•
•
•
•
•
•

Package
N
Mil Coml

•

•
•
•
•
•
•
•

'••.
N/A

•
•
•

•
•
•
•
•
•

•

•
•
•
•
•

•
•
•
•
•
•
•
•

N/A

•

•
•
•

•
•
•
•
•
•

•

•
•
•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•

•
•
•
•

•
•
•
•..
•
•
•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•

•.
•
•
•
•
•
•

Coml

• N/A •
•
• N/A •
• •

'.

•
N/A

N/A

•
•
•
•

•
•
•
•
•

•
•
•
•
•
•

W
Mil

N/A

•
•
•
•
• N/A

•
•
•
•
•

N/A
N/A

•

•
N/A

•

N/A

•
•
N/A
•

•
•
•
•

N/A

•
•

•
•
N/A

• •
• •
• •
N/A
• •
• •
• •
• •
• •
• N/A •
• •

~

Table of Contents

54n4 SSI
Device No.

DM54LS10/DM74LS10
DM74S10
DMS411/DM7411
DM54Hll/DM74Hll
DM54L 11/DM74L 11
DM54LSll/DM74LSll
DM74S11
DM54LS12/DM74LS12
DM5413/DM7413
DMS4LS13IDM74LS13
DM5414/DM7414
DMS4LS14/DM74LS14
DM54LS15/DM74LS15
DM74S1S
DMS416/DM7416
DM5417/DM7417
DM5420/DM7420
DM54H20/DM74H20
DM54L20/DM74L20
DMS4LS20/DM74 LS20
DM74S20
DM54H21IDM74H21
DMS4LS21/DM74LS21
DM54H22/DM74H22
DM 54 LS22/DM 74 LS22
DM74S22
DM5423/DM7423
DM5425/DM742S
DMS426/DM7426
DM54L26/DM74L26
DM54LS26/DM74LS26
DM5427/DM7427
DM54CS27 IDM74LS27
DM5430/DM7430
DMS4H30/DM74H30
DM54L30/DM74L30
DMS4LS30/DM74LS30
DM74S30
DM5432/DM7432
DM54L32/DM74L32
DM54LS32/DM74LS32
DM5437/DM7437
DM54LS37/DM74LS37
DM5438/DM7438
DM54LS3B/DM74LS38

Elec.
Conn.
Char.
Diag.
Pg. No. Pg. No.

Description

Triple 3·lnput NAND Gates
Triple 3-lnput NAND Gates
Triple 3-lnput AND Gates
Triple 3-lnput AND Gates
Triple 3-lnput AND Gates
Triple 3-lnput AND Gates
Triple 3-lnput AND Gates
Triple 3-lnput NAND Gates with
Open-Collector Outputs
Dual 4-lnput NAND Schmitt Triggers
Dual 4-lnput NAND Schmitt Triggers
Hex Schmitt Triggers
Hex Schmitt Triggers
Triple 3-lnput AND Gates with
Open-Collector Outputs
Triple 3-lnput AND Gates '!'lith
Open-Collector Outputs
Hex Buffers with Open-Collector
High-Voltage Outputs
Hex Buffers with Open-Collector
High-Voltage Outputs
Dual 4-lnput NAND Gates
Dual 4-lnput NAND Gates
Dual 4-lnput NAND Gates
Dual 4-lnput NAND Gates
Dual 4-lnput NAND Gates
Dual 4-lnput AND Gates
Dual 4-lnput AND Gates
Dual 4-lnput NAND Gates with
Open-Collector Outputs
Dual 4-lnput NAND Gates with
Open-Collector Outputs
Dual 4-lnput NAND Gates with
Open-Collector Outputs
Expandable Dual 4-lnput NOR Gates
Dual 4-1 nput NOR Gates
Quad 2-lnput High-Voltage NAND
Gates
Quad 2-lnput High-Voltage NAND
Gates
Quad 2-lnput High-Voltage NAND
Gates
Triple 3-lnput NOR Gates
Triple 3-lnput NOR Gates
8-lnput NAND Gates
8-lnput NAND Gates
8-lnput NAND Gates
8-lnput NAND Gates
8-lnput NAND Gates
Quad 2-1 nput 0 R Gates
Quad 2-lnput OR Gates
Quad 2-lnput OR Gates
Quad 2-lnput NAND Buffers
Quad 2-lnput NAND Buffers
Quad 2-lnput NAND Buffers with
Open-Collector Outputs
Quad 2-lnput NAND Buffers with
Open-Collector Outputs

I-iii

J
Mil Coml

• N/A
•
•
•
• N/A
•
•
•
•
•
•

•
•

Package
N
Mil Coml

•

•
•
•
•
•
•
•

W
Mil

Coml

•

•

1-4
1-4
l-S
l-S
l-S
l-S
l-S
l-S

1-36
1-36
1-44
1-44
1-44
1-44
1-44
1-38

l-S
l-S
1-6
1-6
1-6

1-48
1-48
1-48
1-48
1-46

1-6

1-46

N/A

1-6

1-42

1-7

1-42

1-7
1-7
1-7
1-7
1-7
1-7
1-7
1-8

1-36
1-36
1-36
1-36
1-36
1-44
1-44
1-38

1-8

1-38

•
•
•
•
•
• N/A
•
•
•
•

1-8

1-38

1-8
1-8
1-9

1-S0
1-40
1-42

•
•
•

•
•
•

•
•
•

•
•
•

1-9

1-42

•

•

•

•

N/A

1-9

1-42
1-40
1-40
1-36
1-36
1-36
1-36
1-36
1-S2
1-S2
1-52
1-54
1-54
1-42
1-42

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

•
•
•
•
N/A
•
• N/A
•
•
•
•
•

1-10

•
•
•
•
•
•
•
•
•
•
•
•
•
•

•

1-9
1-9
1-9
1-9
1-9
1-9
1-9
1-10
1-10
1-10
1-10
1-10
1-10

•
•
•
•
•
•
• N/A
•
•
•
•
•
•
•

..

'.

•
•
•
•
•
•
•

•

•
•
•
•
•
•
•
•
•

•
•
•
•
•
•

•
• N/A
•
•
•
•
•
•

•

•

•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•
•
•

•

•
•
•

•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•

N/A

•
•

•

•N/A
•

• N/A

•
•
•
•

N/A

•

N/A

•

•

N/A

N/A
N/A
N/A

•

•
N/A

•

•

•N/A •

•
•

•

•

•
•
•
•
•
•
•
•
•
•
•

~_54n4 SSt
Device No.

DM5440/DM7440
DM54H40/DM74H40
DM54LS40/DM74LS40
DM74S40
DM5450/DM7450
DM54H50/DM74H50
DM5451/DM7451
DM54H51/DM74H51

.

DM54L51/DM74L51
DM54LS51/DM74LS51
DM74S51
DM54H52/DM74H52
DM.5453/DM7453
DM54H53/DM74H53
DM5454/DM7454
DM54H54/DM74H54
DM54L54/DM74L54
DM54LS54/DM74LS54
DM54H55/DM74H55
DM54L55/DM74l55
DM54LS55/DM74LS55
DM5460/DM7460
DM54H60/DM74H60
DM54H61/DM74H61
DM54H62/DM74H62
DM74S64
DM74S65
DM5470/DM7470
DM54H71/DM74H71
DM54L71/DM74L71
DM5472!DM7472
DM54H72/DM74H72
DM54L72/DM74L72
DM5473/DM7473
DM54H73/DM74H73
DM54L73/DM74L 73
DM54LS73/DM74LS73

Table of Contents
Conn.
Elec.
Diag.
Char.
Pg. No. Pg. No.

Description

Dual 4·lnput NAND
Dual 4·lnput NAND
Dual 4·lnput NAND
Dual 4·lnput NAND
Dual 2Wide 2·lnput
Gates
Dual 2Wide 2·lnput
Gates
DUIlI 2·Wide 2·lnput
Gates
Dual 2·Wide 2·lnput

Buffers
Buffers
Buffers
Buffers
AND·OR·INVERT

1-11
1·11
1·11
1-11
1·11

1·54
1:54
1·54
1·54
1·50

AND·OR·INVERT

1·11

1·50

AND·OR·INVERT

(12

1·56

AND·OR·INVERT . 1·12

1·56

Gates
Dual 2·Wide 2·lnput AND·OR·INVERT
Gate,
Dual 2-Wide 2-lnput AND-OR-INVERT
Gates
Dual 2-Wide 2-lnput AND-OR-INVERT
Gates
Expandable 4Wide AND-OR
Gates
Expandable 4-Wide AND-OR
INVERT Gates
Expandable 4-Wide AND-ORINVERT Gates
4-Wide AND-OR-INVERT Gates
4-Wide AND-OR-INVERT Gates
4-Wide AND-OR-INVERT Gates
4-Wide AND-OR-INVERT Gates
2-Wide 4-lnput AND-ORINVERT Gates
2-Wide 4-lnput AND-ORINVERT Gates
2Wide 4-lnput AND-ORINVERT Gates
Dual 4-lnput Expanders
Dual 4'lnput Expanders
Triple 3-lnput Expanders
4-Wide AND-OR Expanders
4-Wide AND-OR-INVERT Gates
4-Wide AND-OR-INVERT Gates
with Open-Collector Outputs
AND-Gated J-K Positive-Edge-Triggered
Flip-Flops with Preset and Clear
AND-OR-Gated J'K Master-Slave
Flip-Flops with Preset
AN D-Gated R -S Master-Slave
Flip-Flops with Preset and Clear
AND-Gated J-K Master-Slave Flip-Flops
. with Preset and Clear
AND-Gated J-K Master-Slave Flip-Flops
with Preset and Clear
AND-Gated J-K Master-Slave Flip-Flops
with Preset and Clear
Dual J-K Flip-Flops with Clear
Dual J-K Flip-Flops with Clear
Dual J-K Flip-Flops with Clear
Dual J-K Flip-Flops with Clear

J-iv

Mil

J
Coml

•

•

.-

• •
•
N/A
• •
• •
• •
• •
• •
• •

1·12

1·56

1-12

1-56

1-12

1-56

1-13

1-50

•

1-13

1-50

1-13

1-50

•
•

1-14
1-14
1-14
1-14
1-15

1-56
1-56
1-56
1-56
1-50

1-15

1-56

1-15

1-56

1-15
1-15
1-16
1-16
1-16
1-17

1-58
1-59
1-60
1-59
1-56
1-61

1-18

1-62

1-18

1-64

1-19

1-66

1-19

1-62

1-19

1-64

1-19

1-66

1-20
1-20
1-20
1-20

1-62
1-64
1-66
1-68

Package
N
Mil
Coml

•
•
•
•

•
•
•
•
•

N/A

•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•
•
•

•
•

..

•
•

•
•
•
•
•

•

N/A
N/A

•
•
•
•
•
•
•

•
•
•
•
•
•
•

•
•

•
•
•
•
•
•

•
•
•

•
•
•

•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•

Mil

•

W
Coml

N/A

• N/A
•

•
•
•

N/A

•

•
N/A

•

•
•

•
N/A
N/A

•

•
N/A

• •
N/A
• •
• N/A •
• •
• •
• N/A •
N/A
N/A
N/A
N/A

•

•
N/A

•
•

~

•
N/A

•
•
N/A
•
•

•
•
•
•

~

54n4 SSI
Device No.

DM5474/DM7474
DM54H74/DM74H74
DM54L74/DM74L74
DM54LS74/DM74LS74
DM74S74
DM5476/DM7476
DM54H76/DM74H76
DM54LS76/DM74LS76
DM54H78/DM74H78
DM54L78/DM74L78
DM54LS78/DM74LS78
DM5486/DM7486
DM54L86/DM74L86
DM54LS86/DM74LS86
DM74S86
DM54H 103/DM74H 103
DM54H 106/DM74H1 06
DM54107/DM74107
DM54LS107/DM74LS107
DM54H108/DM74H108

DM541 09/DM741 09
DM54LS1 09/DM74LS1 09
DM54LS112/DM74LS112
DM74S112
DM54LS113/DM74LS113
DM74S113
OM54LS114/DM74LS114

DM74S114

DM54121/DM74121
DM54LS122/DM74LS122
DM54123/DM74123

Table of Contents
Elec.
Conn.
Diag.
Char.
Pg. No. Pg. No.

Description

Dual D Positive·Edge·Triggered
Flip·Flops with Preset and Clear
Dual D Positive-Edge-Triggered
Flip-Flops with Preset and Clear
Dual D Positive-Edge-Triggered
Flip-Flops with Preset and Clear
Dual D Positive-Edge-Triggered
Flip-Flops with Preset and Clear
Dual D Positive-Edge-Triggered
'Flip-Flops with Preset and Clear
Dual J-K FI ip-Flops with Preset and
Clear
Dual J-K Flip-Flops with Preset and
Clear
Dual J-K Flip-Flops with Preset and
Clear
Dual J-K FI ip-Flops with Preset,
Common Clear and Common Clock
Dual J-K Flip-Flops with Preset,
Common Clear and Common Clock
Dual J-K Flip-Flops with Preset,
Common Clear and Common Clock
Quad EXCLUSIVE-OR Gates
Quad EXCLUSIVE-OR Gates
Quad EXCLUSIVE-OR Gates
Quad EXCLUSIVE-OR Gates
Dual J-K Negative-Edge-Triggered
Flip-Flops with Clear
Dual J-K Negative-Edge-Triggered
Flip-Flops with Preset and Clear
Dual J-K Master-Slave Flip-Flops with
Clear
Dual J-K Master-Slave Flip-Flops with
Clear
Dual J-K Negative-Euge-Triggered
Flip-Flops with Preset, Common
Clear, and Common Clock
Dual J-i( Positive-Edge-Triggered
Flip-Flops with Preset and Clear
Dual J-i( Positive-Edge-Triggered
Flip-Flops with Preset and Clear
Dual J-K Negative-Edge-Triggered
Flip-Flops with Preset and Clear
Dual J-K Negative·Edge-Triggered
Flip-Flops with Preset and Clear
Dual J-K Negative-Edge-Triggered
Flip-Flops with Preset
Dual J-K Negative-Edge-Triggered
Flip-Flops with Preset
Dual J-K Negative-Edge-Triggered
Flip-Flops with Preset, Common
Clear, and Common Clock
Dual J·K Negative-Edge-Triggered
Flip-Flops with Preset, Common
Clear, and Common Clock
One Shots
Retriggerable One Shots with Clear
Dual Retriggerable One Shots with Clear'
j-v

Mil

J
Coml

•
•
•
•

•
•
•

Package
N
Mil
Coml

•

•

•

•
•
•

Mil

W
Coml

•

•

1-20

1·62

1-20

1-64

1-20

1-66

1-20

1-68

1-20

1-70

1-21

1-62

•

•

1-21

1-64

•

1-21

1-68

•

1-21

1-64
1·66

•
•

1-21

1-68

•

•

1-22
1-22
1-22
1-22
1-23

1-72
1-72
1-72
1·72
1·74

•
•
•
• •
• •
• N/A •

•

1·21

•
•
•
•
•

•
•
•

• •
• •
• N/A •

•

•

•

1-23

1-74

•

•

1-23

1·62

N/A

1-68

•

•
•

•

1-23
1-24

1-74

•
•
•

•
•

•
•
•
•
•
•

•

•

1-24

1-62

•

•

1-24

1-68

1-24

1-68

•
•

•
•

•
•
•

1-24

1-70

1-25

1-68

1·25

1-70

1-25

1-68

1-25

1-70

1-26
1-26
1·26

1-76
1-78
1-78

•

•
•

•
•
•

N/A

•

•

N/A

•

•

•

•

•

•

•
•
•

•

N/A

•

•
N/A

•

•
N/A

•

•
•

•

N/A
N/A

•
•

•

•
•
•
•
•

•
•
•

•
•
•

•
•

•

•
•
•
N/A

,.

•

•

•

•
•
•

•
N/A

•
N/A

•

N/A

•
•
•

•

•

N/A

•

N/A

•
N/A

•
•
•

•
•
•

~

Table of Contents

54n4 SSI
Device No.

DM54L 123A/DM74L123A
DM54LS123/0M74LS123
DM54125iDM74125
DM54LS125/DM74LS125
DM5412o/DM74126
DM54LS1261DM74LS126
DM54132/DM74132
DM54LS132/DM74LS132
DM74$133
DM74S134
DM74S135
DM54LS136/DM74LS136
DM74S136
DM74S140
DM54LS221/DM74LS221
DM74S260
OM 54 LS266IDM7 4 LS266
DM54365/DM74365
DM54LS365/DM74LS365
DM54366/DM74366
DM54LS366/DM74LS366
DM54367/DM74367
DM54LS367/DM74LS367
DM54368/DM74368
DM54LS368/DM74LS368
DM54LS386/DM74LS386

Conn. Elec.
Diag. Char.
Pg. No. Pg. No.

Description

Dual Retriggerable One Shots
with Clear
Dual Retriggerable One Shots
with Clear
TRI-STATE Quad Buffers
TRI-STATE Quad Buffers
TRI-STATE Quad Buffers
TRI-STATE Quad Buffers
Quad 2-lnput NAND Schmitt
Triggers
Quad 2·lnput NAND Schmitt
Triggers
13·lnput NAND Gates
TRI·STATE 12·lnput NAND
Gates
Ql,Jad EXCLUSIVE-OR/NOR
Gates
Quad EXCLUSIVE-OR Gates
with Open·Coliector OutPl,Jts
Quad EXCL_USIVE-OR Gates
with Open·Collector Ol,Jtputs
Dual 50-Ohm Line Drivers
Dual One Shots with SchmittTrigger Inputs
Dual 5·lnput NOR Gates
Quad EXCLUSIVE·NOR Gates
with Open-Collector Outputs
TRI-STATE Hex Bl,Jffers
TRI-STATE Hex Buffers
TRI-STATE Hex Buffers
TRI·STATE Hex Buffers
TRI-STATE Hex Buffers
TRI-STATE Hex Buffers
TRI-STATE Hex Buffers
TRI.STATE Hex Buffers
Quad EXCLUSIVE-OR Gates

J·vi

J
Mil

Coml

1-26

1-78

•

•

1-26

1-78

•

•

1-27
1-27
1-27
1-27
1·27

l-BO
l·BO
1-80
1-80
1·48

•

1·27

1-48

1·28
1·28

1-36
1-80

N/A
N/A

1·28

1·82

N/A

1·29

1-84

1·29

1-84

1·29
1-30

1-54
1·76

1-31
1·31

1-40
1·84

1-32
1-32
1·32
1-32
1-32
1-32
1-33
1-33
1-34

1-86
1·86
1-86
1-86
1-86
1-86
1-86
1-86
1-72

•
•
•
•

•

•
•
•
•
•

•

•

Package
'N
Mil Coml

•
•
•
•
•
•
•
•

•

•
•
•
•
•
•
N/A
N/A

N/A

•

•

•
•
• •

•

•
•
•
•
•
•
•

N/A

•
•
•
•
•
•
•
•
•

N/A

•
•
•

•
•

•
•

•

N/A

•
•
•
•
•

•

•
•
•
•

•
•
•
•
•
•
•
•

•
•

N/A

•

•

Coml

•

•

•

•

W
Mil

•

•
•
•
•

•

N/A

•

•

•
•
•
•
•
•
• •
• •
• •
• •

N/A

•
•
•

•
•
•
•
•
•
•

•

National Semiconductor
54I74 SSI DEYICES
Connection Diagrams
Section 1

~ SSI
00

DM54/DM74 Connection Diagrams/Gates

Quad 2-lnput NAND Gates

V4

B4

GND

B3

A3

Y = AS

A1

B1

Y1

A2

Y2

"

"

GNO

540017400(WI; 54L00/74LOO(WI

540017400(Jl. (NI; 54H00/74HOO(JI. (NI;
54LOO/74LOO(Jl. (NI; 54LSOO/74LSOO(JJ.(NI.(WI;
74S00(N)

See page 1-36 for electrical tables.

01

Quad 2-lnput NAND Gates with Open-Collector Outputs

14

"'

A4

GNO

B3

A3

Y= AS

5401/7401(JI. (NI; 54LS01/74LS01(JI. (NI. (WI

A1

B1

Y1

A2

B2

54H01/74H01(JI. (NI

See page 1-38 for electrical tables.

1-1

Y2

GNO

540117401 (WI; 54LOl/74LOl (W)

Y3

~ 551
02

DM54/DM74 Connection Diagrams/Gates

Quad 2-lnput NOR Gates
A3

Y4

B4

A4

GNO

"

A3

Y3

Y =A+B

Y1

52

B1

A1

540217402(JI, (N); 54L02/74L02(J), (NI;
54LS02/74LS02.(J), (NI, (INI; 74S02(NI

5402/7402(1N1; 54L02/74L02(1N1

See page 1-40 for electrical tables.

03

Quad 2-lnput NAND Gates with Open-Collector Outputs

Y=AB

5403/7403(JI, (NI; 54L03/74L03(JI. (NI;
54LS03/74LS03(Jl, (NI, (INI; 74S03(NI

See page 1·38 for electrical tables.

04

Hex Inverters

46

13

YO
12

A5

YO

A4

Y4

Y3

GNO

V1

A'

YO

GNO

YO

A5

10

11

Y=A

A1

Y1

A2

Y2

A3

5404/7404(JI, (NI; 54H04/74H04(JI, (NI;
54L04/74L04(JI, (NI; 54LS04/74LS04(JI,(NI,(INI;
74S04(NI
See page 1-36 for electrical tables.

1-2

5404/7404(1N1; 54L04/74L04(1N1

V4

~ SSI
05

DM54/DM74 Connection Diagrams/Gates·

Hex Inverters with Open-Collector Outputs

.6
14

Al

"

"

YO

11

.2

A5

11

Y2

"

A'

"

A3

Y3

GNo

"

5405174051J), IN); 54H05/74H05(J), IN);
54L05/74L051J), IN); 54LS05/74LS051J), IN), IW);
74S051N)

5405/74051W); 54L05/74L051W)

See page 1·38 for electrical tables.

06

Hex Buffers with Open-Collector High-Voltage Outputs

A6

Y6

"

"

.5
11

Y'

Y5

"

Y=A

Al

YI

A2

Y2

A3

Y3

GNo

A'

Y'

Y3

GNo

5406/74061J), IN), IW)

See page 1·42 for electrical tables.

07

Hex Buffers with Open-Collector High-Voltage Outputs

v"
14

A.

"

YB

"

A.
11

Y,

"

Y=A

Al

YI

A2

V2

A3

5407/74071J), IN), IW)

See page 1-42 for electrical tables.

'-3

.~ SSI

08

DM5.4/DM74 Connection Diagrams/Gates

Quad 2-lnput AND Gates

Y=AB

540S1740S(J), (N), (W); 54HOS174HOS(J), (N);
54l0S174l0S(J), (N), (W);
54lS0S/74lS0S(J)" (N), (W)
See page 1-44 for electrical tables.

09

Quad 2-lnput AND Gates with Open-Collector Outputs

Y= A8

5409/7409(J), (N), (W); 54l09/74l09(J), (N). (W);
54lS09174lS09(J), (N), (W)

See page 1 A6 for electrical tables.

10

Triple 3-lnput NAND Gates
C1

Y3

C3

OND

B3

'3

14

y= ABC

Al

82

541017410(J), (N); 54Hl0174Hl0(J), (N);
54l10174l10(JI, (N); 54lS10174lS10(J), (N), (W);
74S10(N)

See page 1 ~36 for electrical tables.

1-4

541017410(W); 54L 10/74l10(W)

C2

~ SSI
11

y

DM54/DM74 Connection Diagrams/Gates

Triple 3-lnput AND Gates

~

C3

"

Al

Yl

B1

C1

V1

GND

ABC

AI

B1

A1

5411/7411(Jl. (N); 54Hll/74Hl1(J), (N);
54111/74L l1(J), (N), (W); 54LSll/74LS11(J), (N), (W);
74S11(N)
See page 1-44 for electrical tables.

12

Triple 3-lnput NAND Gates with Open-Collector Outputs

y

= ABC

y

= ABCD

AI

B1

NO

C1

D1

VI

GND

5413/7413(J),(N),(W); 54LS13/74LS13(J),(N),(W)
See page 1-48 for electrical tables.

1-5

~ SSI

DM54/DM74 Connection Diagrams/Gates

14 Hex Schmitt Triggers

Y=A

5414/7414(J) ,(N) ,(W); 54LS14/74LS14(J),(N),(W)

See page 1 AS for electrical tables.

15 Triple 3-lnput AND Gates with Open-Collector Outputs

Y= ABC

54LS15/74LS15(J),(III),(W); 74S15(N)

See page 1 A46 for electrical tables.

16 Hex Buffers with Open-Collector High-Voltage Outputs
v~

14

AS
IJ

YO

12

A5
11

Y5

A4

"

V3

GNo

"

Y=A

AI

VI

A2

Y2

A3

5416/7416(J),(N),1W)

See page 1-42 for electrical tables.

1·6

~. SSI

DM54/DM74 Connection Diagrams /Gates

17 Hex Buffers with Open-Collector High-Voltage Outputs
A6
14

13

V6

A5

Y5

A4

Y4

YJ

GNO

D2

C2

10

12

Y=A

Al

Y1

A2

Y1

AJ

5417 /7417(J) ,IN),(W)

See page 1-42 for electrical tables.

20

Dual 4-lnput NAND Gates
vc

D2

13

Y

=

C2

NO

B2

A2

D1

12

"

13

"

GNO

12

Y1

10

ABeD

Al

"

NO

01

Yl

GNO

B2

5420/7420(J),(N); 54H20/74H20(J),(N);
54L20/74L20(J),IN); 54LS20/74LS20(J),IN),IW);
74S20(N)

5420/7420(W); 54L20/74L20(W)

See page 1-36 for electrical tables.

21 Dual 4-lnput AND Gates
NO

D2
14

Y

13

B2

A2

Y1

12

= ABeD

Al

"

54H21/74H21 (J) ,IN);54LS21/74LS21 (JI,(NI,(W)

See page 1 ·44 for electrical tables.

1-7

~ SSI
22

DM54/DM74 Connection Diagrams/Gates

Dual 4-lnput NAND Gates with Open Collector Outputs

"

D1

14

Y

B2

NO

A2

Y2

Yl

GNO

12

13

ABCD

~

C1

81

54H22/74H22(J),(N); 54LS22/74LS22IJ),(N),(W);
74S22(N)

See page 1 ~38 for electrical tables.

23

Expandable Dual 4-lnput NOR Gates with Strobe

Xl

D2

=

Gl (A1+B1+C1+DlI+X

Y2

=

G2 (A2+B2+C2+D2)

STROBE
G2

82

A2

Y2

C1

D1

Yl

GNO

14

16

Yl

C2

X = output of 5460/7460

XI

Al

STRUBE
G1

B1

5423/7 423(J), (N) ,(W)

See page 1 ~50 for electrical tables.

25

Dual 4-lnput NOR Gates with Strobe
STROBE
Vee

02

14

Y

=

13

C1

G2

B2

12

G(A+B+C+D)

Al

B1

5425/7 425(J) ,IN) ,(W)
See page 1-40 for electrical tables.

1-8.

A2

Y2

~ 551
26

DM54/DM74 Connection Diagrams/Gates

Quad 2-lnput High-Voltage NAND Gates

Y = AB

A1

B1

Y1

A2

B2

Y2

GND

542611426(J),(N);54L26114L26(J),(N);
54LS26/7 4LS26( J), (N) ,(WI

See page 1-42 for electrical tables.

27

Triple 3-lnput NOR Gates
BJ

CJ

A1

B1

A'

A3

Y3

Y2

"

542711427(J),(NI,(W); 54LS27114LS27(J),(N),(W)

See page 1-40 for electrical tables.

30

a-Input NAND Gates

NC

114

I"

NC
12

11

I"

2

3

,

4

NC

I.

-s

Y = ABCDEFGH

1

NC

•

NC

GND
11

10

)0-

I'

GND

"

See page 1·36 for electrical tables.

543011430(J),(N);54H30114H30(J),(N);
54L30114L30(J).(N);54LS30/74LS30(J),(N),(W)
74S30(N)

1-9

543011430(W),54L30114L30(W)

~ 881
32

DM54/DM74 Connection Diagrams/Ga~es

Quad 2-lnput OR Gates

Y=A+B

.,

"

Y1

.2

B2

Y2

GNO

543211432(J),(N),(W);54L32114L32(J),(N),(W);
54LS32/74LS32(J),(N),(W)

See page 1 ~52 for ele'etrical tables.

37

Quad 2-lnput NAND Buffers

Y=Ae

.,

"

Y1

A2

B2

Y'

GNO

5437 /7437(J) ,(N) ,(WI ;54LS37/74LS37(J) ,(N ),(W)

See page 1-54 for electrical tables.

38

Quad 2-lnput NAND Buffers with Open-Collector Outputs

Y=Ae

.,

"

Y1

'2

B2

Y'

GNO

5438/7438(J),(N),(W);54LS38174LS38(,J),(N),(W)

See page '·42 for electrical tables.

1·10

~ SSI
40

DM54/DM74 Connection Diagrams/Gates

Dual 4-lnput NAND Buffers

D2

"

C2

NC

B2

A2

V2

.,

12

Il

C1

B1

Il

14

12

ON.

V2

11

.2

C2

A2

82

D2

C2

10

y= ABeD

AI

B1

Ne

C1

.,

VI

GN.

AI

VI

Ne

5440/7440(JI, (NI; 54H40/74H40(JI, (NI;
54LS40/74LS40(JI, (NI, (W); 74S40(N)

V"

Ne

5440/7440(WI

See page 1 ~54 for electrical tables.

50

Dual 2-Wide, 2-lnput, AND-DR-INVERT Gates
v"

.,

B1

C1

VI

.,
"

y

C1
Il

GN.

VI

12

V2

11

"

=.AB+Ci5+X
50:
X = output of 5460/7460
H50: X = output of 54H60/74H60
or 54H62/74H62

AI

A2

82

&2

.,

V2

5450/7450(J), (N); 54H50/74H50(JI, (N)

See page 1-50 for electrical tables.

1-11

GN.

82

5450/7450(W)

··~SSI

DM54/DM74 Connection Diagrams/Gates

51 Dual 2·Wide, 2·lnput AND·DR·INVERT Gates
v"

81

"

.2

MAKE NO EXTERNAL
CONNECTION
~

01

C1

Y1

. 01

C1

Y1

GNO

Y2

02

C2

Al

v"

81

.,

B2

51, H51, 551

Y

= A8+Ci:5

B2

C2

0'

GNO

MA~AL
CONNECTION

5451/7451(J), (N); 54H51/74H51(J),(N);
74S51(N)

5451/7451(W)

L51, U51

Y1 = (AI' 81' Cl) + (01' El •. Fl)
Y2

= (A2

• 82)

+ (C2

• 02)

54L51/74L51 (J),(N); 54LS51/74LS51(J),(N),(W)

See page 1-56 for electrical

t~bl.s.

1-12

54L51/74L51(W)

~ 551
52

y

~

DM54/DM74 Connection Diagrams/Gates

Expandable 4-Wide AND-OR Gates

AB+COE+FG+HI+X
X

~

output of 54H61174H61

NC

GND

54H52/74H52(J). (N)

See page 1-50 for electrical tables.

53

Expandable 4-Wide AND-OR-INVERT Gates
GND

NO
10

53

Y

AB+CO+EF+GH+X
X = output of 5460/7460

5453/7453(J). (N)

5453/7453(W)

H53

Y

=

-;AC'B:C+C'C"'O"+:-;E'""'F'""'G""+:-;H7."C
1+~X
X

= output of 54H60/74H60
or 54H62174H62

GND

54H53/74H53(J), (N)

See page 1-50 for electrical tables.

1-13

~SSI

DM54/DM74 Connection Diagrams/Gates

54 4-Wide AND-OR-INVERT Gates
GND

NC
10

54

Y

~A:;:Bc;+-;;C:;:Dc;+"E"F'7+-;;G:;-;H

Ne

GNO

MAKE NO EXTERNAL
CONNECTION

5454/7454W, IN)

545417454IW)

MAKE NO EXTERNAL
CONNECTION

Ne

~

14

"

12

H54

Y =A
-;;-;;B'"'+""c"'D:-:+-;E'"'F:-;G"""+'"'H-;-;1
L541J, N), LS54

Y = AB+CDE+FGH+IJ

GNo

GNo

54H54/74H541J), IN)

54L54174L54IJI,IN}; 54LS54/74LS541J) ,IN) ,IW)

Ne

GND

L54(W)

Y = '=A-=Bc.:
C-c+-=D-=E""+-=F-=G-c+7":H"'"'IJ

54L54174L541W)

See pagel-56 for electrical tables.

1-14

~ 551

DM54/DM74 Connection Diagrams/Gates

55 2-Wide, 4-lnput AND-DR-INVERT Gates
Ne

"

13

12

H55 (EXPANDABLE)
y ~ ABCO+EFGH+X
X ~ output of 54H60/74H60
or 54H62/74H62
L55(J, NI. LS55

Y

~

ASCO+EFGH

Ne

Ne

GNO

54H55/7 4H55(J),(N)

Ne

GNO

54L55/7 4L55(J),(N); 54LS55/74LS55(J),(N),(W)

Ne

GNO

Ne

Ne

L55(W)

Y ~ "A"'S"'CC::O-+-=EC:-F-=-G'"'H

54L55/74L55(W)

See page 1-50 (H551. 1-56 (L55 and LS55) for electrical tables.

60

Dual4-lnput Expanders
v"

01

x,

x,

X2

X2

02

X2

14

X2

02

"

60

GNO

C2

11

B2

A2

C1

01

10

X =- ABeD when connected, to X and

X inputs of 542317423, 5450/7450
or 5453/7453

H60
X = ABeD when connnected to X
and X inputs of 54H50/74H50,
54H53/74H53, or 54H55/74H55

A'

B1

C1

A2

B2

C2

5460/7460(J),(N); 54H60/74H60(J),(N)
See page 1-58 (60), 1-59 (H60) for electrical tables.

1-15

GNO

x,

x,

A1

v"

B1

5460/7460(W)

~ SSl
61

DM54/DM74 Connection Diagrams/Gates

Triple 3·lnput Expanders
X3
11

XI

X2

C2

GNO

10

x = ABC when connected to X input
of 54H52/74H52

BI

AI

A2

CI

"

54H61/74H61(J) ,(N)

See page 1-60 for electrical tables.

62

4·Wide AND·OR Expander
v"
14

13

12

X = AB + CDE + FGH + iJ when
co nnected to X and X inputs
of 54H50/74H50, 54H53/74H53
or 54H55/74H55

.NO

54H62/74H62(J) ,(N)

See page 1-59 for electrical tables.

64

4 Wide AND·OR·INVERT Gates

14

13

12

Y = ABCD + EF + GHI + JK

GNO

74S64(N)
See page 1-56 for electrical tabies.

1-16

~ 551
65

DM54/DM74 Connection Diagrams/Gates

4 Wide AND-OR-INVERT Gates with Open-Collectbr Outputs

T
14

•

c

13

12

•

K

I,.

11

/,
I

Y = ABeD + EF + GHI + JK

y

•

~

-

,

•

2

,

J
F

,
G

74S65(N)

See page 1-61 for electrical tables.

1-17

J

.I'
H

!'
I

C!:

~ 551

DM54/DM74 Connection Diagrams/Flip-Flops

70 AND-Gated J-K Positive-edge-Triggered Flip-Flops with Preset and Clear
PA

elK

K'

eLR

J1

J2

KI

TRUTH TABLE
INPUTS

OUTPUTS

PR

CLR

CLK

J

K

a

L

H

L

X

X

H

a
L

H

L

L

X

X

L

H

L

L

X

X

X

H'

H'

H

H

t

L

L

ao

00

H

H

H

L

H

L
H

H

H

t
t

L

H

L

H

H

t

H

H

TOGGLE

H

H

L

X

X

ao

NC

GND

5470/7470(J),(N)

00

J=Jl ·J2·J
K=Kl ·K2·K
If inputs J and Kare not used, they
must be grounded.

J'

GNO

"

Preset or Clear function can occur
only when clock input is low.

KI

elK

PR

v"

CLR

NC

J1

5470/7470(W)

See page 1·62 for electrical tables.

H71 AND-DR-Gated J-K Master-Slave Flip'Flops with Preset
v"

TRUTH TABLE
INPUTS

14

elK

J

K

a

L

x

X

X

H

L

H

.JL
.JL
.JL
.JL

L

L

00

GO

H

L

H

L

L

H

L

H

H

H

TOGGLE

H
H

K"

KA'

KB1

JA'

JB2

PR

KAI

13

OUTPUTS

PR

H

elK

a

J = UIA • JIB) + (J2A - J2B)
K = (KIA· K1B) + (K2A' K2B)
JAI

JB1

GND

54H71/74H71(J) ,(N)

See page 1·64 for electrical tables.

Notes: ....JL "" high-level pulse; data inputs should be held constant while clock is hi,gh; data is transferred to output on the falling edge of the
~~,

'

00 = the level of Q before the indicated input conditions were established.
TOGGLE: Each output changes to the complement of its previous level on each active transition (pulse) of the clock.
*This configuration is nonstable; that is, it will not persist when preset and clear inputs return to their inactive (high) level.

1-18

~ SSI

OM 54/0M74 Connection Oiag rams/Flip-Flops

l71 AND-Gated R-S Master-Slave Flip-Flops with Preset and Clear

TRUTH TABLE
INPUTS

OUTPUTS

PR

CLR

CLK

S

R

Q

Q

L

H

X

X

X

H

L

H

L

X

X

X

L

H

L

L

X

X

H

H

H'
00

H'
60

H

H

H

L

H

L

H

H

L

H

L

H

H

H

..1L
..1L
..1L
..1L

X
L

H

H

L

NC

S2

GNO

53

INDETERMINATE

=

51

54l71/14L71(JI.(N)

RJ

R2

GNO

53

52

Nt

51

"

R = Rl • R2' R3

5

CLR

SI ·52· S3

Rl

ClK

PR

V"

ClR

54l71/74l71(W)

See page 1-66 for electrical tables.

72

AND-Gated J-K Master-Slave Flip-Flops with Preset and ciear
v"

TRUTH TABLE
INPUTS
K

Q

L

H

X

X

X

H

L

H

L

X

X

X

L

H

L

L

X

X

X

H

H

..1L
..1L
..1L
..1L

L

L

H

H
H

H

H

ClK

KJ

K2

K1

KJ

K2

GNO

JJ

"

OUTPUTS

PR CLR ClK J

H

PR

Q

H' H*
00 60

H

L

H

L

L

H

L

H

H

H

TOGGLE

J = Jl·J2·J3
K=Kl'K2'K3
5472/1472(J) ,(N );54H72/7 4H72(J) ,(N);
54L72/74L72(J),(N)

5472/1 472(W) ;54l 72/1 4l 72 (WI

See page 1-62 (72),1-64 (H721.1-66 (L72) for electrical tables.

Notes: ..JL '" high-level pulse; data inputs should be held constant while clock is high; data is transferred to output on the falling edge of the

pulse.

ao "" the level

of Q before the indicated input conditions were established.
TOGGLE: Each output changes to the complement of its previous level o,n each active transition (pulse) of the clock.
"'This configuration is nonstable; that is, it will not'persist when preset and clear inputs return to their inactive (high) level.

1-19

~ SSI

DM54/DM74 Connection Diagrams/Flip-Flops

73 Dual J-K Flip-Flops witn Clear
TRUTH TABLE
73,H73,L73
INPUTS

TRUTH TABLE
LS73
OUTPUTS

ClK

J

K

Q

Q

ClR

ClK

l

X

X

X

l

H

l

H

JL
JL
JL
JL

l

l

00

60

H

l

H

l

H

L

H

H

H

H
H

OUTPUTS

INPUTS

ClR

J

K

Q

X

X

X

l

Q

H

H

j

l

l

00

60

L

H

H,
l

H

l

H

I
I

l

H

H

l

H

TOGGLE

H

I

H

H

H

H

X

X

TOGGLE

00

60

See page 1-62 (73),1-64 (H73), 1-66 (L73), 1-68 (LS73) for electrical tables_

547317473('.1), (N), (W); 54H73174H73(J),(N);
54L73/74L73 (.I), (N), (W);
54LS73174LS73(J), (N), (W)

74 Dual D Positive-Edge-Triggered Flip-Flops witn Preset and Clear

TRUTH TABLE
INPUTS

Vee

eLR 2

elR l

01

D2

eLK 1

eLK 2

PR Z

02

Pfl 1

01

01

.ND

OUTPUTS

PR

ClR

ClK

l

H

H

L

L

L

H

H

H

H

X
X
X
t
t

H

H

l

'0

Q

Q

X
X

H

L

L

H

X

H'

H'

H

H

L

L

l

H

X

00

60

5474/7474(J),(N); 54H74/74H74(J),(N);
54L74/74L74(J),(N); 54LS74/74LS74(J),(N),(Wl;
74S74(N)

PR 1

"

.,
13

lil

ii2

GND

02

PR2

"

12

5474/7474(Wl; 54L74/74L74(Wl
See page 1-62 (74), 1-64 (H74), 1-66 (L74), 1-68 (LS74), 1-70 (S74) for electrical tables.

Notes: JL "" high-level pulse; data inputs should be held constant while clock is high; data is transferred to output
~~

on the falling edge of the
,

00 = the level of Q before the indicated input conditions were established.
TOGGLE: Each output changes'to the complement of its previous level on each active transition (pulse) of the clock.
*This configuration is nonstable; that 'is, it w'ill not persist when preset and clear inputs return to their inactive (high) level.

1-20

~ 551
76

DM54/DM74 Connection Diagrams/Flip-Flops

Dual J-K Flip-Flops with Preset and Clear
TRUTH TABLE
LS76

TRUTH TABLE
76, H76
INPUTS

INPUTS

OUTPUTS

OUTPUT&

PR

CLR

CLK

J

K

a

a

PR

CLR

CLK

J

K

a

L
H

H

X

X

X

H

L

L

H

X

X

X

H

L

L

X

X

X

L

H

H

L

X

X

X

L

H

H'

L
H

L

X

X

X

H

4-

L
H

L

W
00

W
00

L

H

L

L
H

H
H

H
L
TOGGLE

X

X

00

L

L

X

X

X

H
H

H

~

L

L

W
00

H

~

H

L

H

L

H

H

H

H

~

L

H

L

H

H

H

H

H

~

H

H

TOGGLE

H

H

t
t
t

H

H

H

00

a

00

elK 1

PR 1

ClR 1

J1

Vee

elK 2

PR 2

elR 2

5476/7476(J). (N), (W); 54H76/74H76(J), (N);
54LS76/74LS76(J), (N). (W)
See page 1-62 (76).1-64 (H76), 1-68 (LS76) for electrical tables.

78

Dual J-K Flip-Flops with Preset, Common Clear, and Common Clock

TRUTH TABLE
H78, L78
INPUTS

OUTPUTS

PR

CLR

eLK

J

K

a

L

H

X

X

X

H

L

H

L

X

X

X

L

H

W
00

L

L

X

X

X

H

H

~

L

L

W
00

a

H

H

~

H

L

H

L

H

H

~

L

H

L

H

H

H

~

H

H

.,

TOGGLE

., .,

J1

.,

.,

GND

54H78/7 4H78(J) ,(N)

TRUTH TABLE
LS78
INPUTS

OUTPUTS

PR

CLR

ClK

J

K

a

L

H

X

X

X

H

a
L

H

L

X

X

X

L

H

L

L

X

X

X

H

H

t

L

L

W
00

W
00

H

H

4-

H

L

H

L

H

H

4-

L

H

L

H

H

H

4-

H

H

TOGGLE

H

H

H

X

X

00

00
54L78/74l78(J), (N), (W);
54lS78/74lS78(J), (N).(W)

See page 1-64 .(H78), 1-66 (L78), 1-68 (LS78) for electrical tables.

Notes:

.JL

=

pulse.

high-level pulse; data inputs should be held constant while clock is high; data is transferred to output on the falling edge of the
'

QO = the level of Q before the indicated input conditions were established.
TOGGLE: Each output changes to the complement of its previous level on each active transition (pulse) of the clock.
*This configuration is nonstable; that is, it will not persist when preset and clear inputs return to their inactive (high) level.

1·21

~ 551
86

DM54/DM74 Connection Diagrams/Gates

Quad 2-lnput EXCLUSIVE-OR Gates

.,

B1

Y1

.2

B2

Y2

GND

548617486(J), (N), (W);
54LS86174LS86(J), (N), (W); 74S86(N)

A3

TRUTH TABLE
(86, L86, LS86, S86)
INPUTS

OUTPUT

Y

A

B

L

L

L

L

H

H

H

L

H

H

H

L

Y=A0B=AB + AS
A1

B1

Y1

V2

.2

B2

GND

AJ

VJ

54L86174L,86JJ),(N)

V4

84

A4

GND

OJ

54L86174L86(W)

See page 1-72 for electrical tables.

1·22

~ SSI

DM54/DM74 Connection Diagrams/Flip-Flops

103 Dual J-K Negative-Edge-Triggered Flip-Flops with Clear
J1

01

.2

K2

GND

Q1

02

TRUTH TABLE
INPUTS

OUTPUTS

ClR

ClK

J

K

Q

L

X

X

X

L

H

H

L

L

00

60

H

L

H

L

L

H

L

H

H

I
I
I
I

H

H

TOGGLE

H

H

X

X

00

H
H

Q

60

54H 103/74H 103(J),(N)

See page 1 ~74 for electrical tables.

106 Dual J-K Negative-Edge-Triggered Flip-Flops with Preset and Clear
K1

., .,

GND

K2

Jl

Vee

.2

.2

J2

TRUTH TABLE
INPUTS

OUTPUTS

PR

ClR

ClK

J

K

a

L

H

X

X

H

L

H

L

X

X

L

H

X

x

H'

H'

L

L

00

60

H

L

H

L

L

H

L

H

H

H

TOGGLE

X

X

00

H

H

X
X
X
I
I
I
I

H

H

H

L

L

H

H

H

H

H

H

a

elK1

PRl

elRl

CLK2

PR2

ClR2

60
54H106/74H106(J), (N)

See page 1-74 for electrical tables.

107 Dual J-K Master-Slave Flip-Flops with Clear

TRUTH TABLE
INPUTS

OUTPUTS

CLR

ClK

J

K

Q

L

X

X

X

L

H

H

SL
SL
SL
SL

L

L

00

60

H

L

H

L

L

H

L

H

H

H

H
H
H

Q

TOGGLE
J1

=

K1

.2

li2

GND

54107/74107(J),(N);
54lS107/74lS107(J), (N), (W)

See page 1-62 (1071.1-68 (LS107) for electrical tables.

Notes; JL

U1

high-level pulse; data inputs should be held constant while clock is high; data is transferred to output on the falling edge of the

pulse.

00 = the level of Q before the indicated input cc;inditio!,",s were establ ished.
TOGGLE: Each output changes to the complement of its previous level on each active transition (pulse) pf the clock.
*This configuration is nonstable; that is, it will not persist when preset and clear inputs return to their i'nactive '(high) level.

1·23

~ SSI

DM54/DM74 Connection Diagrams/Flip-Flops

108 Dual J-K Negative-Edge-Triggered Flip-Flops with Preset, Common Clear, and Common Clock
TRUTH TABLE
INPUTS

OUTPUTS

PR

elR

elK

J

K

Q

L

H

X

X

H

L

H

L

X

X
X
X

l

H

l

W
00

aD

L

H

L

H

l

H

l

L

X
X

H

H

j

H
H
H
H

H

j

l
H

H

j

l

X

H

j

H

H

H

H

X

X

Q

W

., .,

TOGGLE

00

aD

oz

JT

0'

.z

GND

54Hl0S/74Hl08(J), (N)

See page 1-74 for electrical tables.

109 Dual J-K Positive-Edge-Triggered Flip-Flops with Preset and Clear
Vee

eLR 2

J2

eLR1

Jl

Kl

K2

ClK2

PRl

02

0'

PR 1

01

.,

GND

TRUTH TABLE
INPUTS

OUTPUTS

PR

qR

elK

J

K

a

a

l

H

X

X

X

H

l

H

l

X

X

X

l

H

l

l

X

X

X

W

W

H

H
H
H
H
H

t

L

L

t
t
t

H

L

L

H
H

00

H

l

X

X

00

H
H

H
H

H
L
TOGGLE
H

aD
l
aD

eLK 1

54109/74109(JI, (N). (W);
54lS109n4lS109(J), (N). (W)

See page 1-62 (109). 1-68 (lSI09) for electrical tables_

112 Dual J-K Negative-Ed\le-Triggered Flip-Flops with Preset and Clear
Vee

eLR 1

eLR z

eLK 2

K2

JZ

PR'

.z

eLK 1

Kt

JT

PR1

.,

.,

li%

GND

TRUTH TABLE
OUTPUTS

INPUTS
PR

ClR

ClK

J

K

a

L

H

X

X

H

l

H

l

X

X

X
X

l

H

l

Q

l
H

X

X

X

H
H

j

L

l

W
00

ao

H

j

H

l

H

L

H

H

H

H

H
H

l
H

H

H
l
TOGGLE

X

X

00

H

••

H

W

aD

54LSl12n4LSl12(J), (N), (W); 74S112(N)

See page 1-68 (LSI12). 1-70 (5112) for electrical tables_

Notes;

00 = the level of

a before the indicated input conditions were established.

TOGGLE: Each output changes to the complement of its previous level on each active transition of the clock.
*Thjs configuration is nonstable; that is, it will not persist when preset and,clear inputs return to their inactive (high) level.

1-24

~ SSI

DM54/DM74 Connection Diagrams/Flip-Flops

113 Dual J-K Negative-Edge-Triggered Flip-Flops with Preset
eLK 2

Vee

k2

J2

PR 2

.2

02

TRUTH TABLE
INPUTS

OUTPUTS

a

PR

ClK

J

K

0

l

x

X

X

H

l

H

j

L

L

00

00

H

j

H

L

H

L

H

j

L

H

l

H

H

j

H

H

TOGGLE

H

H

X

X

00

00
elK 1

54LS113/74LS113(J), (N),

(wf; 74S113(N)

See page 1-68 (LS113), 1-70 (5113) for electrical tables.

114 Dual J-K Negative-Edge-Triggered Flip-Flops with Preset, Common Clear, .and Common Clock

TRUTH TABLE
INPUTS

OUTPUTS

ClR

elK

J

K

a

L

H

L

L

X
X
X

H

H

X
X
X

L

H

H*

H*

L

00

00

PR

a

L

L

X
X
X

H

H

j

L

H

H

j

H

L

H

l

H

H

j

L

H

L

H

H

H

j

H

H

TOGGLE

H

H

H

X

X

00

CtR

00

K'

J1

PR 1

.,

ii,

GND

54LS114/74LS114(J), (N), (W); 74S114(N)

See page 1-68 (LS1141, 1-70 (5114) for electrical tables.

Notes:

00 = the level of Q before the indicated input conditions were established.
TOG,GLE: Each output changes to the complement of its previous level on each active transition of the clock.
*This configuration is nonstable; that is. it will not persist when preset and clear inputs return to their inactive (high) level.

1-25

~ 88.1

DM54/DM74 Connection Diagrams/One 8hots

121 One Shots
TRUTH TABLE
INPUTS

OUTPUTS

A1

A2

B

0

0

L

X

H

L

H

X

L

H

L

H

X

X

L

L

H

H

H

X

L

H

.JL
.JL
.JL
.JL
.JL

lS
lS
lS
lS
lS

H

t

H

t
t

H

H

t

H

L

X

t

X

L

t

NO

Al

GND

'2

5412f/74121(J), (N), (W)

See page 1~ 76 for electrical tables.

122 Retriggerable One Shots with Clear
TRUTH TABLE
INPUTS

OUTPUTS

CLEAR

A1

A2

B1

B2

0

Q

L

X

X

X

X

L

H

X

H

H

X

X

L

H

X

X

X

L

X

L

H

X

X

X

X

L

L

H

X

L

X

H

H

L

H

JL
JL

LJ
LJ

H

L

X

t

H

H

L

X

H

t

H

X

L

H

H

L

H

H

X

L

t

H

LJ

H

X

L

H

t

JL
JL

H

H

I

H

H

H

I

I

H

H

H

I

H

H

H

t
t

L

X

H

H

X

L

H

H

See page 1 ~78 for electrical

JL
JL
JL
JL
JL

LJ
LJ

54LS122(J), (W); 74LS122(J), (N)

LJ
LJ

-LJ
LJ

ta~les.

123,123A Dual Retriggerable One Shots with Clear

REXT 1

Vee

CEXT

CEXT 1
14

02

III

"

12

elR 2

82

.2

REXT 2

GND

11

TRUTH TABLE
INPUTS

OUTPUTS

A

B

CLR

0

0

H

X

H

L

H

X

L

H

L

H

L

t

H

LJ

t

H

H

.JL
.JL

X

X

L

L

H

lS
Al

81

ClR 1

(11

Q2

CEXT 2

CeXT

54123n4123(J), IN), (W);
54L 123An4L 123A(J), (N),(W);
54LS123n4LS123(J), (N), (W)

See page 1~78 for electrical tables.

Notes: .....IL- = one high-level pulse, I S = one low-level pulse.
To use the internal timing resi~tor of 54121/74121, connect RINT to VeeAn external timing capacitor ':11ay be connected between CEXT and REXT/CeXT (positive),
For accurate repeatable pulse widths, connect an external resistor between REXT/CEXT and Vee with RINT oPBI!-circuited.
To obtain variable pulse widths, connect external variable resistance between RINT or REXT/CEXT and VCC·

1·26

~ SSI
125

DM54/DM74 Connection Diagrams/Gates

TRI-STATE Quad Buffers
C4

14

A4

Il

12

V4

11

"

AJ

VJ

V2

GND

I'

TRUTH TABLE
INPUTS

OUTPUT

A

C

Y

H

L

H

L

L

L

X

H

HI-Z

Y=A

01

AI

VI

C2

A2

54125/74125(J), (NI. (WI;
54LS125174LS125(JI. (NI. (WI

See page 1-80 for electrical tables.

126

TRI-STATE Quad Buffers
C4

A4

12

Il

V4
II

TRUTH TABLE
INPUTS

"
I'

AJ

VJ

A2

V2

GND

OUTPUT

A

C

y

H

H

H

L

H

L

X

L

Hi-Z

Y=A

01

AI

VI

C2

54126174126(J). (N). (WI;
54LS126174LS126(JI. (N), (WI

See page 1-80 for electrical tables.

132

Quad 2-lnput NAND Schmitt Triggers

Y=AB

54132/74132(JI. (N). (W);
54LS132174LS132(J). (N). (W)

See page 1-48 for electrical tables.

1-27

~ 551
133

DM54/DM74 Connection Diagrams/Gates

13-lnput NAND Gates

I"
Y

"

15

13

11

~

= ABCDEFGHIJKLM

2

1

3

,

I"

11

,

4

r-s
I'

6

p

I'

GNO

74S133(N)

See page 1-36 for electrical tables.

134

TRI-STATE 12-lnput NAND Gates
Vee

OUTPUT
CONTROL

J"

J"

"

13

11

11

,

1"

~

Y - ABCDEFGHIJKL
Output is off (disabled) when
output control is high.

)0-

2

1

3

,

4

3
,

E.

I'

I'

GNO

74S134(NI

See page '1-80 for electrical tables.

135

Quad EXCLUSIVE-OR/NOR Gates
TRUTH TABLE
OUTPUT

INPUTS

Y

A

B

C

L

L

L

L

L

H

L

H

H

L

L

H

H

H

L

L

L

L

H

H
L

L

H

H

H

L

H

L

H

H

H

H
Al

B1

VI

&1, C2

A2

Y= (A0SI0c=
ABC + ABC + ABC + ABC

74S135(NI

See page 1--82 for electrical tables.

1·28

82

Y2

GNO

~ 551
136

DM54/DM74 Connection Diagrams/Gates

Quad EXCLUSIVE-OR Gates with Open-Collector Outputs
B4

V'"

I"

13

A

OUTPUT
Y

B

L

L

L

L

H

H

H

L

H

H

H

L

Y = A

0

YO

12

83

11

~L>-

B = AB + AS

1

1

VJ

3
9

•

~L>,

1

8 12

AI

10

5))- Err

TRUTH TABLE
INPUTS

1~

,

1

85
2

A2

"

6

Y2

J:

54LSI36174LSI36(J), (N), (W)
74S136(N)

See page 1-84 for electrical tables.

140

Dual 50-Ohm Line Drivers

Vl~

14

D2
13

C2

12

NC

I"

--

Y2

B2
10

T9

8

~

Y=ABCD

1

AI

2

"

J:

,
C1

74S140(N)

See page 1 ~54 for electrical tables.

1·29

5
01

~

t J:

~ 551

DM54/DM74 Connection Diagrams/One Shots

221 Dual One Shots with Schmitt-Trigger Inputs
Vee

RUTI
CexT 1

CEXT 1

Q1

ii2

ClR2

Q2

CEXT 2

82

'2

Run!

GNU

TRUTH TABLE
INPUTS

OUTPUTS

CLEAR

A

B

Q

Q

L

X

X

L

H

X

H

H

X

X
L

L

X

L

H

H

L

t

H

j

H

JL LJ
JL l J '

.,

CEXT 2

54LS221/74LS221(J), (N), (W)

See page 1-76 for electrical tables.

Notes:

..Jl.... == one high-level pulse, L r = one low-level pulse.
An external timing capacitor may be cohnected between CEXT and ReXT/CEXT (positive).
For accurate repeatable pulse widths, connect an external resistor between R EXT/CEXT and Vee.
To obtain variable pulse widths, connect external variable resistance between ReXT!CeXT and Vee.

'-30

~ 551
260

DM54/DM74 Connection Diagrams/Gates

Dual 5-lnput NOR Gates

I..

E1

E1

D1

I"I

i"L.-

11

D2

B2

C2

•

1D

•

r--y

~

A+B+C+D+E

~
2

1

"

B1

l

C1

C
I
4
A2

I'

V1

6
V2

74S260(N)

See page 1-40 for electrical tables.

266

Quad EXCLUSIVE-NOR Gates with Open-Collector Outputs

TRUTH TABLE
INPUTS
B

A

OUTPUT
Y

L

L

L

H

L

H

L

L

H

H

H

y ~ A

0

H

B ~ AB

+

AB

54LS266/74LS266(Jl. (N), (W)

See page 1-84 for electrical tables.

1-31

I'

GNO

~ 551

DM54/DM74 Connection Diagrams/Buffers

365, TRI-STATE Hex Buffers

TRUTH TABLE
OUTPUT

INPUTS

Gl

G2

A

Y

H

X

X
L

H

X
X

Z
Z

H

H

L

L

L

L
L

54365(JI. (WI174365(JI. (NI. (WI;
54LS365174LS365(JI. (NI. (WI
See page 1·86 for electrical tables.

366 TRI-8TATE Hex Buffers
Vee

112

A'

ill

Al

Yl

y,

AS

Y5

A4

Y4

A2

Y2

A3

VJ

GND

TRUTH TABLE
INPUTS

OUTPUT

Gl

G2

A

Y

H

X

Z

X

H

X
X

L

L

H

L

L

L

L

H

Z

54366(J1. (WI174366(JI. (N). (W);
54LS366/74lS366(J). (N). (WI
See page 1-86 for electrical tables.

367 TRI-STATE Hex Buffers
Vee

G2

A'

Y'

A5

Y5

A4

V4

Al

Yl

A2

"

A3

Y3

GND

TRUTH TABLE
INPUTS

-G=A-

OUTPUT

Y

H

X

Z

L

H

H

L

L

L

54367(JI. (W)174367(J1. (N). (WI;
54LS367174LS367(JI. INI. (WI

See page 1-86 for electrical tables.

1-32

~ SSI
368

DM54/DM74 Connection Diagrams/Buffers

TRI·STATE Hex Buffers
AS

Y5

A5

Y5

A4

y.

y,

A2

V2

'3

Y3

GND

TRUTH TABLE
INPUTS

--=-G
A

OUTPUT

Y

H

X

Z

L

H

L

L

L

H

54368(J), (W)/74368(J), (N), (W);
54LS368/74LS368(J), (N), (W)

See page

1~86

for electrical tables.

1-33

~ 551
386

DM54/DM74 Connection Diagrams/Gates

Quad EXCLUSIVE-OR Gates

TRUTH TABLE
INPUTS

r--A
B

OUTPUT

L

L

L

L

H

H

H

L

H

H

H

L

Y=A0s = AS +AB

54LS386174LS386(J), (N), (WI
See page 1-72 for electrical tables.

1-34

National Semiconductor
54f74 SSI DEVICES
Electrical Tables
Section I

Max Ratings/Operating Conditions
RATINGS
Maximum Allowable
Supply Voltage
Guaranteed Operating
Supply Voltage Range

54/74

54H/74H

54L/74L

SERIES

SERIES

SERIES

7

7

8

54LS/74LS SERIES
DIODE

EMITTER

INPUTS

INPUTS

7

7

54S/74S
SERIES
7

4.50 to 5.50
4.75 to 5.25

154

J74

UNITS

V
V

Maximum Input Voltage

5.5

5.5

5.5

7

5.5

5.5

V

Maximum Voltage to OpenCollector Outputs*

7

7

8

7

7

7

V

Operating Free·Air
Temperature Range

154
174

Storage Temperature Range
*Except for selected high voltage types, as specified in electrical tables.

1-35

-55 to +125
o to +70

DC

-65 to +150

DC

Electrical Characteristics

over recommended operating free·air temperature range (unless otherwise noted).

CONDITIONS

PARAMETER

MIN

V'H

High Level Input Voltage

V'l

low Level Input Voltage

V,

Input Clamp Voltage

DM54/74

DM54HI74H

DM54L/74L

DM54 LS/74 LS

DM74S

00,04
10,20,30

HOO, H04
Hl0, H20, H30

LOO, L04
L 10, L20, L30

LSOO
LS04, LS10
LS20, LS30 '

SOO, S04
S10, S20
S30, S133

TYP(l)

MAX

2

Vee

= Min

I

~~8

It =

TYP(1)

MAX

2

MIN

TYP(1)

OB
-1.5

High Level Output Current

VOH

High Level Output Voltage

-1.5

IOH

10l

VOL

Low Level Output Current

Low Level Output Voltage

Vee

V 1H

w


Z
C
G)
til

S-

se..
~
CD

~

CD

iil

Electrical Characteristics

CONDITIONS

PARAMETER

MIN
VIH

High Level Input Voltage

VIL

Low Level Input Voltage

IOH

VOH

High Level Output Current

High Level Output Voltage

Vee = Min

Low Level Output Voltage

Others

Vee. = Min

J,.

IOL = Max

V'H = 2V

Input Current at Maximum

Vee = Max

I rrput Voltage
High Level

IIH

Input Current

Data Inputs
Strobe of 25
All Inputs

Vee = Max

IlL

Data Inputs

Input Current

Strobe of 25

,

Short Circuit Output
Current

Supply Current

IcC

02,25,27

L02

LS02, LS27

S02, S260·

TYP(1)

MAX

Vce

=Max

TYP(l)

MAX

2

Vee = Max (2)

MIN

TYPO)

MAX

2

MIN

TYP(l)

UNITS

2

0.7

0.7

N/A

DM74

0.8

0.7

0.8

0.8

N/A
N/A

-1.5

-1.2

-200

-400

-1000

25,27

-800

Others

-400

~

V

0.8

-1.5

en

MAX

DM54

V
V

f.lA

2.4
DM54

2.4

3.4

2.4

3.3

2,5

3.4

N/A

DM74

2.4

3.4

2.4

3.2

2.7

3.4

2.7

V

3.4

DM54

16

2

4

N/A

DM74

16

3.6

8

20

DM54

0,2

0.4

0.15

0.3

0.25

0.4

N/A

DM74

0,2

0.4

0.2

0.4

0.35

0.5

0.5

DM74

mA

V

0.4

V, = 5.5V

1

0.1

1
0.1

V, = 2.4V

40

10

160

N/A

=2.7V
=0.3V

mA

0

s:U'I
~

.......
C
f.lA

20

50

s:

li!
0
N

-0.18
-1.6

V, = OAV
V,

Vee = Max

MIN

V, = 7V

V,

All Inputs
lOS

IOL =4 rnA

V,

All Inputs
Low Level

DM74S

LS27

Low Level Output Current

o

II

DM54LS/74LS

I, =-18rnA

IOH = Max

VOL

DM54L!74L

I, =-12mA

Vee = Min

V'L = Max

IOL

DM54/74

2

Input Clamp Voltage

VI

~

over recommended operating free-air temperature range (unless otherwise noted).

-0.36
N/A

-6.4

mA

=0.5V

-2
DM54

-20

-55

-3

-15

-30

-130

DM74

-18

-55

-3

-15

-30

-130

N/A
-40

-100

All typical values are at Vee = 5V, TA = 25°C.
Not more than one output should be shorted at a time, and for DM54LS/DM74LS and DM74S, duration of short circuit should not exceed one second.
National Semiconductor temporarily reserves the right to ship DM54/0M74LS02, LS27 devices which have a minimum lOS = 5.0 rnA.

en
Z

0

Notes
(21
(31

en
N
0

See Table

(1)

mA

N
U'I
N
....

::D
C)
I»

It
en

748260 To Be An';ouneed In 1976
--

-

Supply Currents
DEVICE

I

ICCH (rnA)
Total With Outputs High
TYP

02
25

Switching Characteristics

8
8

ICCl (rnA)
Total With Outputs Low

MAX

TYP

MAX

16

14

27

16

10

19

DEVICE

atVcc~5V,TA~25°C

CONDITIONS

MIN
02
25

CL

~

15 pF,

RL ~

400£2

27
27
L02

10
0.8

16
1.6

16
1.4

TYP

MAX

tpHl (ns)
Propagation Delay Time,
High-To-Low Level Output
MIN

TYP

I

~
en
en

MAX

12

22

8

15

13

22

8

15

7

11

10

15

26
L02

CL

~

50 pF,

RL ~4k£2

31

60

35

60

L502, L527

CL

~

15 pF,

RL ~

2 k£2

10

15

10

15

2.6

L502

1.6

3.2

2.8

5.4

L527

2.0

4

3.4

6.8

502.

17

29

26

45

5260

17

29

26

45

502

.j:,.

tPlH (ns)
Propagation Delay Time,
Low-To-High Level Output

5260

CL

~

15 pF,

RL ~

280£2

3.5

5.5

3.5

5.5

CL

~

50 pF,

RL ~

280£2

5

7.5

5

7.5

CL

~

15 pF,

RL

= 280£2

4

5.5

4

6

o

s:

U'I

.fa

.....
o

s:
~

o
N
N

U'I

N
:oJ
en
N
en
o
Z

o

:a
C)
III

;

III

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted).
OM54/14
CONDITIONS

PARAMETER

06,07,16,17
MIN

V,H

High Level Input Voltage

V,L

Low Level Input Voltage

Input Clamp Voltage

I, :-12 rnA

Vee::: Min

10H

High Level Output Current

VOH

High Level Output Voltage

26

MAX

2

I OM54
OM74

V,

TYP(11

11 -

VOH

Low Level Output Voltage

-

V,, 121

.i>

'"

Input Current at
Maximum Input Voltage

I,

High Level Input Current

I'H

Low Level I nput Current

I,L

Supply Current

Icc

Vee"" Max

L26
MAX

TYP(11

0.8

0.8

-1.5

-1.5

250
30

16,17

15

1000

MIN

TYP(1t

LS38
MAX

'2

0.8

0.8

06,07

LS26
MAX

2

2
0.8

MIN

MIN

TYP(1)

MAX

0.7

0.7

0.7

0.8

0.8

N/A

N/A

N/A

1.5

200

50

1.5

1000

250

250

5.5

15

15

30

16

48

2

4

12

40

16

48

3.6

8

24

DM54

0.7

0.4

0.4

0.7

0.4

0.4

IOL-4mA
IOL '" 12mA

DM74
0.4

V , ·5.5V

1

1

.1

40

40

40

0.15

0.3

0.25

0.4

0.4

0.4

0.35

0.5

0.5

0.25

0.4

0.1
0.1

0.1

20

20

-{J.36

-{J.36

10

-1.6

-1.6

1.6

Notes
(1)

All typical values are at Vee· 5V, TA· 25°e.

(2)

The input

~Itage

is VIH

U'I

~
......

0

~
en
b.....
0

mA

iJA

:.a
en
:.a

.....
en
W

N
CO

mA

0

i::l

See Table

Max

0

~

~

mA

V

-{J.18

VI'" O.3V

V1 - O.4V

pA

0.4

IOL -16mA

VI =2.4V

V

5.5

DM74

OM74

en
en

V

V
15

DM54

OM74

UNITS
V

2

0.7

V, - 2.7V

Vee'" Max
=

TYP(1)

~

OM54LS/74LS

VI=7V

Vee::: Max

Vee

MIN

50

Max

IOL '" Max
Vee"': Min

38
MAX

lamA

low Level Output Current

VOL

TYP(1)

-1.5

Others
10L

MIN
2

0.8

V OH ::: 12V

Vee'" Min
V,, (21

OM54LJ74L

0

2-

= 2V or VIL :::;: max, as appropriate.

(i'

~

LS38 To Be Announced In 1976

0
:"

;,
<
0
I

;

;:;'
I»
CC

CD

m

c

::::
CD

"'-

Ci1
-------

-

Supply Currenu

DEVICE

Switching Characteristics at Vee; 5V, T A; 25°C

ICCH (mA)
Total With Outputs High
TYP

MAX

ICCl (mA)
Total With Outputs Low
TYP

MAX

DEVICE I CONDITIONS

tplH (ns)
Propagation Delay Time,
Low-To-High Level Output
MIN

06, 16

30

42

27

07, 17

29

41

21

30

26

4

8

12

22

38

5

8.5

34

54

L26

0.48

0.8

1.32

2.04

LS26

0.8

1.6

2.4

4.4

LS38

0.9

2

6

12

06, 16
07,17

CL ;15pF
RL ;

110n

26

CL

15 pF

;

RL ;

38

RL ;

L26

133n

I CL ; 15 pF
RL ;

LS38

1 H~

I C L ; 45 pF

I CL

;

RL ;

w

MAX

10

15

6

10

MIN

TYP

MAX

15
20

23
30

~
en
en

38

LS26

.;,.

TYP

tpHl (ns)
Propagation Delay Time,
High-To-Low Level Output

4 kn
15 pF
2 kn

I Cl ; 45 pF
Rl

; 667n

16

24

11

17

C

s:
U'I
~

.......
14

22

11

18

C

s:-..J

~

0

40

90

25

60

0)

17

32

15

28

:....
0)

20

32

18

28

0

-..J

~

N
0)
W

00

0

't:I

CD
::l

0

2.

Ii"

...

n

...

0

J::

<:0

;:::;'

I»

(Q

CD

IXJ

c:....

....

CD

iil

~

Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted).
PARAMETER

COIllDITIONS
MIN

V,H

High level Input Voltage

V,L

Low Level Input Voltage

V,

DM54174

DM54H/74H

DM54L174L

DM54LS174LS

DM74S

08,11

H08, H11, H21

L08, Lll

LS08, LSll, LS21

S11

TVP(H MAX

2

I

Input Clamp Voltage

MIN

TVP(l)

DM54
DM74

I

0.8
0.8

1,=-12mA

MIN

TVP(1)

High Level Output Current

High Level Output

Vee

Voltage

IOH = Max

IOl

VOL

I,

0.7

0.8

0.8

-1.5

N/A
-1.5

-1.2

N/A

Low Level Output

Input Current at

I'H

High Level I nput Current

I,l

Low Level Input Current

Vee = Min

lOL

=

tOL

-4mA

V 1l = Max

Vee = Max

Max

3.3

2.5

3.4

DM74

2.4

3.4

2.4

3.4

2.4

3.2

2.7

3.4

Vee

= Max

,

2

4

N/A

20

3.6

8

20

DM54

0.2

0.4

0.2

0.4

0.15

0.3

0.25

0.4

N/A

0.2

0.4

0.2

0.4

0.2

0.4

0.35

0.5
0.4

0.5

1

1

1

0.1
0.1

= 2.7V
= 0.3V

Short Circuit Output
Current

ICC

Supply Current

Vee = Max(2)
Vee = Max

20

V, - O.4V

-2

-1.6

50

-{l.36

V

rnA

JlA

rnA
-2

I

DM54
DM74

-20

-55

-18

-55

-

--40
-40

-100

-3

-15

-30

-130

-100

-3

-15

-30

-130

See Table

Notes
All typical values are at Vee = 5V, T A = 25°C.
(2) Not more than one output should be shorted at a time, and for DM54H/DM74H, DM54LS/DM74LS and DM74S, duration 01 short circuit should not exceed one second.
(1)

rnA

-{l.18

V, - 0.5V

los

;tA

'10

50

40

,

V

V

3.4

20

V,=7V

V,

N/A
2.7

DM74
DM74

V, = 5.5V

V,

-1000

--400

2.4

V, = 2.4V
Vc;.c = Max

-200

3.4

16

"

V

2.4

16

V

0.8

-500

CJ)
CJ)

MAX

N/A

3.4

DM54

TVP(l)

0.7

2.4

DM74

MIN

0.7

DM54

Low Level Output

Maximum Input Voltage

..,

= 2V

MAX

2

N/A

Current

Voltage

J,.

= Mi'n, V 1H

TVP(lI

0.8

-1.5

-800

IOH

MIN
2

1,- 18mA

VOH

MAX

2

II =-8mA
Vee = lYlin

MAX

2

UNITS

N/A
-40

100

0

3:

rnA

c.n
~

........

0

3:
.....
~

0

CO

~
...&

LS11, LS21 To Be Announced In 1976

N
...&

»Z
0
C)
I»

...

~

en

Supply Currents

DEVICE

Switching Characteristics at Vee

ICCH (rnA)
Total With Outputs High
TYP

ICCL (rnA)
Total With Outputs Low

MAX

TYP

MAX

21

20

33

DEVICE

I CONDITIONS I

~ 5V, TA ~ 25°C

tpLH (ns)
Propagation Delay Time
Low-To-High Level Output
MIN

OB

~
(J1

I

I

OB,ll

CL

~

15 pF

RL ~

400£1

11

B

15

14

22

HOB

2B

40

42

64

Hll

lB

30

30

4B

HOB, Hll

CL

~

25 pF

H21

RL ~

280£1

H21

~

11

12

20

20

32

tpHL (ns)
Propagation Delay Time,
High-To-Low Level Output
TYP

MAX

27

12

19

12

B.8

12

TYP

MAX

17.5

7.6

MIN

LOB

1.1

2.1

2.0

3.3

LOB

CL

50 pF

45

90

45

90

L 11

1.0

1.5

1.6

2.2

Lll

RL ~

4 k£1

40

BO

45

90

LSOB

2.4

4.B

4.4

B.B

LSOB, LS11

CL

15 pF

LS21

RL ~

2 k£1

10

15

12

20

CL

4.5

7

5

7.5

6

9

7.5

11

LSll

l.B

3.6

3.3

6.6

LS21

1.2

2.4

2.2

4.4

Sll

13.5

24

24

42

Sll

~

~

~

15 pF

RL ~

280£1

CL

~

50 pF

RL ~

2BO£1

2.5

2.5

~
en
en

c

s:C1I

~
.......

C

s:
~
o

00

:::
N

~

»z
c

C)
II)

;

III

Electrical Characteristics

DM54/74
CDNDITIONS

PARAMETER

High Level Input Voltage

V,L

low Level I nput Voltage

Input Clamp Voltage

V,

IOH

High Level Output Current

VOH

High Level Output Voltage

IOl

Low Level Output Current

Low Level Output Voltage

VOL

Input Current at Maximum Input Voltage

.,.
C>

High level Input Current

I'H

Vee::: Min

Vee::: Min

lO9
MAX

:::

Vee"" Max

Max

IOl =4 mA
V, = 5.5V

LS09, LS15
MAX

2

MIN

Supply Current

Vee::: Max

TYP(1)

UNITS

V

2

DM74

0.8

0.7

0.8

0.8

-1.5

NfA
-1.5

-1.2

NfA

V

V

250

50

100

250

IJA

5.5

5.5

5.5

5.5

V

DM54

16

2

4

N/A

DM74

16

3.6

8

20

DM54

0.2

0.4

0.15

0.3

0.25

0.4

NfA

DM74

0.2

0.4

0.2

0.4

0.35

0.5

0.5

DM74

rnA

V

0.4
1

0.1

1
0.1

40

10
20

50

0
rnA

IJA

-0.18
-1.6

-0.36

rnA

s:

C1I

~
.......

0

s:.....
~

0
CD

-2

:...

See Table

C1I

0

Notes

(11

en
en

MAX

NfA

V, = 0.5V
Icc

MIN

0.7

V, = 2.7V

V, = O.4V

S15
MAX

2

V, -7V
V, =2.4V

TYP(l)

0.7

V, = 0.3V
Vee == Max

TYP(1)

DM74S

0.8

I, =-12 rnA

Max

Vee == Max

MIN

1,=-18rnA

tOl :::

DM54LSfDM74LS

DM54

Vee" Min, V ,H = 2V, V OH = 5.5V

Low Level Input Current

I,L

TYP(ll

2

V 1L

I,

DM54LfDM74L

09
MIN

V,H

~

over recommended operating free-air temperature range (unless otherwise noted).

"

All typical values are at VCC= 5V, T A = 25°C.

~

::J

LS15 To Be Announced In 1976

(')

2-

cr
~

0

~

»
z

O·

G)
C\)

CS'
en
'-

Supply Currents

DEVICE

I

Switching Characteristics at V cc

ICCH (rnA)
Total With Outputs High

ICCl (rnA)
Total With Outputs Low

TYP

MAX

TYP

MAX

09

11

21

20

33

L09

1.1

2.1

2

3.3

LS09

2.4

4.8

4.4

8.8

LS15

1.8

3.6

3.3

6.6

S15

10.5

19.5

24

42

DEVICE

CONDITIONS

~ 5V,

L09

LS09,LS15

S15

'CL~15pF

RL

~

400Q

CL

~

15pF

RL

~

4 kQ

CL
RL

~

15 pF

~

2 kQ

CL

~

15 pF

RL

~

280Q

CL

~

50 pF

RL

~

280Q

~ 25° C

tplH (ns)
Propagation Delay Time,
Low-To-High Level Output
MIN

09

TA

2.5

TYP

MAX

21

tpHl (ns)
Propagation Delay Time,
High-To-Low Level Output
TYP

MAX

32

16

24

50

110

50

110

20

35

20

35

5.5

8.5

6

9

8.5

13

8

12

MIN

2.5

~
en
en

o

~

(JI

.;,.
-..J

~

.......

o

~

~

o

CD

:....
(JI

o
i::I
(")

2-

~
g

...

»
z
o

C')

C»

;

en

Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted).
DM54/74
CONDITIONS

PARAMETER

13
MIN

MIN

MAX

Vee

'=

5V

1.5

1.7

2

1.5

1.7

2

VT-

Negative-Going Threshold Voltage

Vee

~

5V

0.6

0.9

1.1

0.6

0.9

1.1

Vee ~ 5V

Hysteresis
Input Clamp Voltage

V,

Vee

0.4
~-12mA

I,

= Min

I, -

High Level Output Current
High Level Output Voltage

Low Level Output Voltage

O.B

-1.5

MAX

1.5

1.7

2

0.6

0.9

1.1

0.4

O.B

TYPO)

MAX

1.4

1.6

1.9

0.5

O.B

1.0

MIN

0.4
-1.5

-1.5

-1.5

--BOO

-800

-400

2.4

3.4

2.4

3.4

2.4

3.4

2.5

3.4

IOH

DM74

2.4

3.4

2.4

3.4

2.4

3.4

2.7

3.4

=:

Max

=:

IOL ~ 8 mA

IT+

Input Current at Positive-Going Threshold

Vee:: 5V, VI

IT-

Input Current at Negative-Going Threshold

Vee

I,

Input Current at Maximum Input Voltage

~

5V. V,

I

16

16

16

4

DM74

16

16

16

B

DM74
0.2

IOL -16mA

0.4

0.2

0.2

0.4

V

V
IlA

0.25

0.4

0.35

0.5

mA

V

0.4

VT +

--{l.65

-0.43

--{l.43

-0.14

rnA

~

VT -

-0.85

--{l.56

-0.56

--{l.18

rnA

Vee:: Max

Vee:o: Max

I,L

Low Level Input Current

Vee = Max,

los

Short Circuit Output Current

Vee ~ Max (2)

Icc

Supply Current

~

V,

~7.0V

V,

~

2AV

V,

~

2.7V

5.5\1

V, =QV

20

-1.0

V,

~

4.5V

-1.6
-55

--{l.S
-18

-1.2
-55

--{l.a
-18

-1.2
-55

-30

rnA

2.9

6
16

5.9

11

LS13

4.1

7

lS14

12

21

LS132

8.2

14

Others

14

20

23

32

22

39

36

60

15

26

24

40

p./i;

rnA

8.6

0

3:
CJ'I

.po

.......

-130

LS14
LS132

mA

-0.4

lS13

Others

Total Output Low

40

40

40

-18

Vee = Max

1
0.1

V,~O.4V

Total Output High

1

1

-

V

'=

V,

en
en

V

DM54

10L ~4mA

Min

UNITS

V

O.B

DM54

Vee

High Level Input Current

.

TYPO)

Vee"'" Min, V! :::: V T -- Min

Vj::::VT+Max

I'H

MIN

lBmA

l,.ow Level Output Current

VOL

0.4

-800

IOH
VOH

IOL

O.B

LS13. LS14. LS132

132

TYPO)

Positive-Going Threshold Voltage

VT-

'"

14
MAX

VT+

VT+

.;,.

TYP(l)

~

DM54LS/74LS

0

3:
~

-"

W

:..
.1)0
:..
W
N

rnA

en
(')

=r
3
;::;:

....

-4

Notes
(1)

All typical values are at V CC ~ 5V. T A ~ 25' C.

(2)

Not more than one output should be shorted at a time, and for OM54LS/DM74LS, duration of short circuit should not exceed one second.

LS13, LS14, LS132 To Be Announced In 1976
-~-

::I.

CQ
CQ

CD

iil

Switching Characteristics at Vee = 5V, TA = 25°C

DEVICE

13
14, 132
LS13
LS14, LS132

ct

I

CONDITIONS

CL

= 15 pF,

RL

= 400n

CL

= 15 pF,

RL

= 2 kn

tpLH (nsl
Propagation Delay Time,
I Low-To-High Level Output

tpHL (nsl
Propagation Delay Time,
High-To-Low Level Output

TYP

MAX

TYP

MAX

18

27
22

15

15

15

22
22

15
15

22
22

18
15

27
22

I

~
CJ)
CJ)

c

s:U'I

~

.......

c

3:
....~
W

~

~

~

W
N

CJ)

n

':

3

a
-t
~

eC'
eQ
~

ii1

Electrical Characteristics

DM54/74
PARAMETER

CONDITIONS

o

VIH

High Level Input Voltage

Vll

Low Level I nput Voltage

VI

Input Clamp Voltage

TYP(l)

II,

MAX

MIN

TYP(l)

MIN

TYP(l)

VOH

High Level Output Voltage

IOl

Low Level Output Current

VOL

Low Level Output Voltage

Vee = Min, V, = (2). IOL = Max

II

Input Current at Maximum I nput Voltage

Vee = Max, V, = 5.5V

IIH

High Level Input Current

Vee = Min, V, = (2). IOH = Max

UNITS

0.8

0.8

-1.5

-1.5

-800

-400

3.4

2.4

3.4

0.8

16
0.2

0.4

0.2

20

0.4

0.2

1

V
V
/J.A
V

3.4

16

1

Vee =Max, V, =2.4V

-500
2.4

-

V

-1.5

2.4

en
en

MAX

2

~-8 mA

High Level Output Current

Data Inputs

MAX

2

1I,=-12mA

IOH

Strobe of 23

H50, H52
H53, H55

50,53

2

Vee = Min

DM54H/74H

23

,

MIN

'"

~

over recommended operating free-air temperature range (unless otherwise noted).

0.4
1

40

40

50

160

N/A

N/A

mA
V
mA
/J.A

0

s:

UI
~

.......

0

s:
....,
~

N

W
Low Level I nput Current

III

Data Inputs
Strobe of 23

Short Circuit Output Current

los

Vee = Max, V, = O.4V

Vee = Max (3)
Vee ~ Max

Supply Current

Icc

-1.6

-2

-1.6

-

-6.4

N/A

N/A

I DM54

-20

-55

-20

-55

-40

-100

I DM74

-18

-55

-18

-55

-40

-100

mA

U1
0

J:

UI

mA

N

U1

W

See Table

J:
UI
UI

Notes
(1)

All typical values are at VCC = 5V, T A = 25°C.

(21

The input voltage is V I H

(31

Not more than one output should be shorted at a time, and for the DM54H/DM74H, duration of short circuit should not exceed one second.

=

m
><

2V or V I L = V I L max, as appropriate.

-

~
Q)

:::J

C.
Q)

C"

~
C)

...

Q)

(1)

en

-~------.-

-~-

Electrical Characteristics

using expander inputs, Vee

= Min,

Ix (mAl
(Ix for H521
Expander Current

DEVICE

CONDITIONS

MIN

TYP(l)

DM5423
Vxx "O.4V

DM5450

IOL""16mA

DM5453
DM7423

Vxx "O.4V

DM7450

10L" 16mA

DM7453
DM54H50

Vx" 1.4V

DM54H53

Ix" 0

DM54H55

tOl =

DM74H50

Vx "l.4V

DM74H53

Ix = 0

DM74H55

IOL = 0

TA

= Min

MAX

CONDITIONS

-3.5

Ix + Ix" 410pA

-2.9

Rxx

-2.9

IOL::: 16mA

-3.5

Ix + Ix " 620pA

-3.1

RX- x

-3.1

t oL =16mA

'=

=

MIN

TYP(1)

Rx:x

0;;

MAX

0

0

CONDITIONS

0

Rxx

=

IOl =

0

TYP(l)

CONDITIONS

MAX

2.4

R xx "138>1

3.4

10H "-400pA

IOL'"

2.4

Ix" -270pA

3.4

0.4

0.2

0.4

0.2

0.4

0.2

0.4

C

0.2

0.4

......

Ix + Ix" 470pA
2.4

Ix" -320pA

3.4

Rxx " 6811
IOL=20mA

10H "-500pA

Ix + Ix" 600pA

Ix" 570pA
Ix" -570pA

2.4

3.4

Rxx " 63>1
IOL =20mA

10H "-500pA

20 rnA

0.2

16 rnA

Rxx " 130>1

Ix" 320pA

1.0

MAX

IOL = 16 rnA

10H "-400pA

1.1

TYP(l)

Ix + Ix " 430pA

Ix" 270pA
1.0

MIN

Ix + Ix" 300pA

Ix "-150pA

Ix+Ix:: 1.1mA

-6.3

MIN

(J)
(J)

Low Level Output Voltage

Ix" 150pA

1.1

IOL ::: 20 rnA

0

VOL (V)

VOH (V)
High Level Output Voltage

Ix + Ix" 700pA
-5·85

~

(unless otherwise noted) (4), (5), (6)

VBEIOJ (V)
Base-Emitter Voltage of
Output Transistor Q

s:

(J1

~

Ix - -300pA

DM54H52

Vx" lV

DM74H52

10H" -500pA

Vx "1V

-4.5

-2.7

10H "-500pA

2.4

3.4

.j::o

IOL = 20 rnA

TA

=

Max

~

Notes
(1) All typical values are at Vec" 5V, T A" 25°C.
(4) The 23, 50, and 53 are designed for"use with up to four 60 expanders.
(5) The HSO, H53, and H55 are designed for use with up to four H60 expanders or one H62 expander.
(6) The H52 is designed for use with up to six H61 expanders.

N
W
Switching Characteristics

DEVICE

at Vee

CONDITIONS

23.50.53
DEVICE

Iccl. (rnA)
Total With Outputs Low

tplH (ns)
Propagation Delay Time,
low·To·High Level Output

MAX

TYP

~

15 pF. RL "40011

MAX

0
tpHl (ns)
Propagation Delay Time,
High-To-Low Level Output
TYP

MAX

CL

"

15 pF. RL "400>1

W
::I:

22

8

15

15

30

10

20

6.8

11

6.2

11

From Input of 60 Expander

8

16

10

19

50

4

8

7.4

14

H52

CL = 25 pF. RL "280>1

10.6

15

9.2

15

H53

Expander Pins Open

7

11

6.2

11

7

11

6.5

11

53

4

8

5.1

9.5

H50

8.2

12.8

15.2

24

H55
H50

CL "25 pF. RL = 280>1

N
(J1

13

23

H50

J::
(J1

MAX

Expander Pins Open
50

TYP

CL

(n

= 5V, T A = 25°C

TYP

Supply Currents
ICCH (rnA)
Total With Outputs High

C

s:

(J1
(J1

,.,m><
II)

::l

C.

II)

11

7.4

cr
CD

H52

20

31

15.2

24

H52

C " 15 pF. (GND to

14.8

9.8

C')

H53

7.1

11

9.4

14

H53

H50. H53. or H55; or

11.4

7.4

H55

4.5

6.4

7.5

12

H55

to X of H52)

11.4

7.7

Ii
en

X of

II)

Electrical Characteristics

CONDITIONS

PARAMETER

MIN
VIH

High Level Input Voltage

VIL

Low Level Input Voltage

Input Clamp Voltage

VI

DM54/74

DM54L/74L

DM54 LS/74 LS

32

L32

LS32

TYPll)

High Level Output Voltage

V OH

Vee = Min

TYP(l)

MAX

MIN

TYP(l)

V

0.8

0.7

0.7

DM74

0.8

0.7

0.8

-1.5

N/A

Input Current at Ma,ximum Input Voltage

II

High Level Input Current

IIH

Low Level Input Current

IlL

Short Circuit Output Current

lOS

Supply Current

Icc

I Total, Outputs High
I Total, Outputs Low

Notes
(1) All typical values are at Vee = 5V, T A = 25"e.
(2)

V

V

-1.5

N/A

-400

-200

Vee = Min, V'H = 2V, IOH = Max

IOL = Max

DM54

2.4

3.4

2.4

2.8

2.5

3.4

DM74

2.4

3.4

2.4

2.8

2.7

3.4

fJ.A

Vee = Max

Vee = Max

Vee = Max

V

DM54

16

2

4

DM74

16

3.6

8

DM54

0.2

0.4

DM74

0.2

0.4

0.15

0.3

0.25

0.4

0.35

IOL =4 mA DM74

'"

MAX

DM54

-800

en
en

~

Vee = Min, V'L = Max

'"

UNITS

2

2

I, =-12 mA

Low Level Output Voltage

VOL

MIN

1,=-18mA

Low Level Output Current

IOL

MAX

2

High Level Output Current

IOH

~

over recommended operating free·air temperature range (unless otherwise noted).

mA

0.4
0.5

V

0.4

V, = 5.5V

1

0.1

V, = 7V

mA

0.1

V,=2.4V

40

10

V, = 2.7V

fJ.A

20

V, = 0.3V

-0.12

-0.18

-1.6

V, =O.4V

Vee = Max(2)

Vee = Max

mA

-0.36

DM54

-20

-55

-3

DM74

-18

-55

-3

...g
...g

-15

-30

-130

-15

-30

-130

15

22

1.5

2.2

3.1

6.2

23

38

2.3

3.8

4.9

9.8

\

Not more than one output should be shorted at a time, and for Of\154LS/DM74lS, duration of short circuit should not exceed one second.

mA

mA

-

C

3:
(J1

.p.......

C

3:
~

W
N

0

::u
G')
III

;

(II

-----

Switching Characteristics at Vee = 5V, TA = 25°C

DEVICE

I

CONDITIONS

I

tpLH (ns)
Propagation Delay Time,
Low-To-High Level Output
MIN

32

L32
LS32

RL = 400Q
CL = 50 pF
RL =4kQ
CL = 15pF
RL = 2 kQ

TYP

MAX

10

tpHL (os)
Propagation Delay Time,
High-To-Low Level Output
MIN

TYP

MAX

15

14

22

40

80

50

100

14

22

14

22

~
CJ)
CJ)

'"
w

c

s:
(11

~

........

C

s:

ii!eN
N

oII
C)

...

Q)

~

en

Electrical Characteristics
PARAMETER

CONDITIONS

DM54/74

DM54H/74H

DM54LS174LS

DM74S

37,40

H40

LS37, LS40

S40, S140

MIN' TYP(l)
V,H

High Level I nput Voltage

V,L

Low Level Input Voltage

V,

MAX

2

Input Clamp Voltage

I,
Vee

10H

= Min

~-8

MIN

TYP(l)

MAX

2

MIN

TYPO)

MAX

DM54

0.8

0.8

0.7

DM74

0.8

0.8

0.8

mA

MIN

TYP(l)

12mA
I, ~-18 rnA

V
N/A
0.8

-1.5

-1.5

-1.2

-1.2

-3

I

I

IOH

= Max

-40
2.4

3.3

2.4

3.4

2.7

V'L - 0.5V, Ro

~

...en

VOL

Low Level Output Current

Low Level Output Voltage

Vee:::: Min

V ,H

~

2V

Input Current at Maximum Input Voltage

I,

Vee:::: Max

I'H

I,L

los

Icc

High Level Input Current

Vee

= Max

Vee

= Max

Vee

~

Low Level Input Current

Short Circuit Output Current

Supply Current

IOL :: Max

IOL - 12 mA
V,

~

V,

~

2.7

50n to

~

2.4V

~

2.7V

V,

~

O.4V

V,

~

0.5V

Max (2)

Vcc=Max

V

DM54

48

60

12

N/A

DM74

48

60

24

60

DM54

0.2

0.4

0.2

0.4

0.25

0.4

N/A

DM74

0.2

0.4

0.2

0.4

0.35

0.5

0.5

DM74

rnA

V

0.4
1

1
0.1

40

100
20
-4

-1.6

100

-0.36
-4

DM54

-20

-70

DM74

-18

-70

-40
-40

-125
-125

-30

-130

-30

-130

C

3:

U1

1

7V

V,

3.4

2

5.5V

V,

rnA

3.4

'oH--3mA

GND, S140 Only
10L

V

V

-1.2

Others

V1L=Max

MAX

-1.5

High Level Output Current

Vee = Min

en
en

-1.5

I, -

High Level Output Voltage

UNITS

:i

2

S140
VOH

~

over recommended operating free-air temperature range (unless otherwise noted).

-50

N/A
-225

See Table

~

rnA

p.A

rnA

rnA

.......
C

3:
.....
~
W
.....

~
0

en
....
~
0

III
Notes
(1) All typical values are at Vee ~ 5V, TA ~ 25°e.
(2r Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second for 37, L537, 40, H40 or LS40; or 100 milliseconds for 540 and 5140.
LS37, LS40 To Be Announced In 1976

C

=

CD

til

.......
C

...<'
CD

til

Supply Currents
DEVICE

I

Switching Characteristics

ICCH (rnA)
Total With Outputs High
TYP

'"
Ul

ICCL (rnA)
Total With Outputs Low

MAX

TYP

MAX

37

9

15_5

34

54

40

4

8

17

27

H40

10.4

16

25

40

LS37

0.9

2

6

12

LS40

0.45

1

3

6

S40

10

18

25

44

S140

10

18

25

44

DEVICE

atV cc =5V,T A =25°C
tpLH (ns)
Propagation Delay Time,
Low-To-High Level Output

CONDITIONS

MIN
37

CL = 45 pF, RL = 133Q

tpHL Ins)
Propagation Delay Time,
High-To-Low Level Output

TYP

MAX

MIN

TYP

13

22

8

I ~enen

MAX
15

40

CL = 15 pF, RL = 133Q

13

22

8

15

H40

CL =25pF,R L =93Q

8.5

12

6.5

12

12

24

I

12

24

4

6.5

6

9

I

f--LS37
LS40

r------S40
S140

I CL = 45 pF, RL = 667Q

I

CL = 50 pF, RL = 93Q
CL = 150 pF, RL = 93Q

I

I

2

2

4

6.5

6

9

c

3:
C1I

tc

3:

~
~

~

o

en
....
~

o

OJ

c:

::::::

CD

~
C
~

~.

U;

Electrical Characteristics

CDNDITIONS(l )

PARAMETER

MIN
V,H
V,L

V,

DM54/74

DM54H/74H

DM54l/74l

DM54lS174lS

DM74S

51,54

H51, H54

L51, l54
l55

lS51, lS54
lS55

551, S64

TYP(1)

MAX

2

High Level Input Voltage

Low Level Input Voltage

Input Clamp Voltage

MIN

TYP(1)

MAX

2

MIN

TYP(1)

2

High Level Output Current
High Level Output Voltage

V 1L = Max

IOH
10L

VOL

= Max

Low Level Output Voltage

'"

Vee -= Min
V'H =2V

C1l

I,

Input Current at Maximum
Input Voltage

I'H

I,L

High level Input Current

Vee = Max

Vee = Max

IOL =Max

Vee -= Max

0.7

N/A

0.7

0.8

0.8

Short Circuit Output

~1.5

~1.2

~4oo

~lOoo

N/A

Icc

Supply Current

Current

V

V

N/A
~200

-500

J.lA

2.4
DM54

2.4

3.4

2.4

3.4

2.4

3.3

2.5

3.4

DM74

2.4

3.4

2.4

3.4

2.4

3.2

2.7

3.4

N/A
2.7

V
3.4

DM54

16

20

2

4

N/A

DM74

16

20

3.6

8

20

DM54

0.2

0.4

0.2

0.4

0.15

0.3

0.25

0.4

N/A

DM74

0.2

0.4

0.2

0.4

0.2

0.4

0.35

0.5

0.5

e
mA

1

~

.......
V

40·

50

1

mA

50

20

J.lA

-1.6

-2

-0.36

rnA
~2

DM54

~20

DM74

-18

-55

~40

~55

-40

Vee -= Max

~100

~100

~3

~15

~3

~15

bI
~

U1
U1

-0.18

= O.4V

~

U1
~

10

V, = 2.7V

e

~

0.1
0.1

= 2.4V

~

U1

0.4
1

V, = 7V

Vee = Max (2)

-

N/A

~1.5
~1.5

V, = 0.5V
loS

en
en

V

2

0.7

IOL = 4 mA DM74

V,

MAX

0.8

V, = 0.3V

Low level Input Current

TYP(1)

0.8

V, = 5.5V

V,

MIN

0.8

lS54

Low Level Output Current

MAX

0.8

1,=~12mA

Others

TYP(1)

DM74

-400
Vee"" Min

MIN
2

I, = lBmA
10H

MAX

UNITS

DM54

I, =-8mA
Vee = Min

VOH

~

over recommended operating free-air temperature range (unless otherwise noted)_

-30

-130

-30

~130

N/A
-40

See Table

~100

en
en
~

mA

~
e
I

0

:::D

Notes
All typical values are at VCC = 5V, TA = 25°C.

I

:;,

(1)

(2)

Not more than one output should be shorted at a time, and for DM54H/DM74H, DM54LS/DM74LS and DM74S, duration of the short circuit should not exceed one second.

(3)

National Semiconductor. temporarily reserves the right to ship DM54/DM74LS51, lS54, lS55 devices which have a minimum lOS = 5.0 mAo

<
CD

::I.

G')

...

74S51 To Be Announced In 1976

Q)

CD
(I)

---------

----

-

- - - - - - - - - - - - - - - - - - - - - ----------------

--- - - - -

---

Supply Currents
DEVICE

c:n
-..J

l

I

I

Switching Characteristics at Vee = 5V, T A = 25°C

ICCH (mA)
Total With Outputs High

ICCl (mA)
Total With Outputs Low

TYP

MAX

TYP

MAX

51

4

8

7.4

14

54

4

8

5.1

9.5

H51

8.2

12.8

15.2

24

H54

7.1

11

9.4

14

DEVICE

CONDITIONS

tplH (ns)
Propagation Delay Time,
Low-To-High Level Output
MIN

TYP

MAX

tpHl (ns)
Propagation Delay Time,
High·To·Low Level Output
MIN

TYP

CL

= 15 pF,

RL

= 400Q

13

22

8

15

H51

CL

= 25 pF,

RL

= 280Q

6.8

11

6.2

11

H54

CL = 25 pF,

RL

= 280Q

7

11

6.2

11

CL = 50 pF,

RL

= 4 kQ I

50

90

35

60

L51

0.44

0.8

0.76

1.3

L54

0.39

0.8

0.60

0.99

L55

I

en
~

MAX

51,54

L51, L54

~

L55

0.22

0.4

0.38

0.65

L551,L555

CL = 15 pF,

RL

= 2 kQ

12

20

12.5

20

L551

0.8

1.6

1.4

2.8

L554

CL = 15pF,

RL

=2kQ

16

20

12.5

20

L554

0.8

1.6

1.0

2

L555

0.4

0.8

0.7

1.3

CL = 15 pF,

RL =

3.5

5.5

3.5

5.5

o

CL = 50 pF,

RL

5

8

5.5

8

U1

551

8.2

17.8

13.6

22

564

7

12.5

8.5

16

551,564

280Q

= 280Q

2

2

3:

~

.......

c

3:
~

...
U1

U1
~

Ut
U1

en
en
~

»
z
c

6XI
I

::l

~

~
C)
Ql

i

Electrical Characteristics

~

over recommended operating free-air temperature range (unless otherwise noted).
DM54

PARAMETER

60

60
CONDITIONS

VIH

DM74

High Level Input Voltage

MIN

TYP(1)

MAX

VXXIONI

On-State Voltage Between

Vee = 4.5V, V IH = 2V

Expander Outputs

Vx = 1.lV, Ix = 3.5 mA

V x =lV,lx=3.5mA

0.4

V

Vee = 4.75V, V IH = 2V
-Q.3

-Q.43

Vx = lV, Ix = 0

mA

TA = O°C

Vee = 4.5V, V IL = 0.8V
Vx = 4.5V, Rx = 1.2 kn

150

T A =-55°C

~

V

TA = O°C

TA =-55°C
Off-State Expander Current

V
0.8

Vee = 4.75V, V IH = 2V
0.4

Vee = 4.5V, V IH = 2V
Vx = 1.1V, Ix =0

Vee = 4.75V, V IL =0.8V
. Vx = 4.5V, Rx = 1.2 kn

270

IlA

mA

TA = O°C

II

Input Current at Maximum Input Voltage

Vee = 5.5V, VI = 5.5V

1

Vee = 5.25V, VI = 5.5V

1

IIH

High Level Input Current

Vee = 5.5V, VI = 2.4V

40

Vee = 5.25V, VI = 2.4V

40

IlA

IlL

Low Level Input Current

Vee = 5.5V, VI = O.4V

-1.6

Vee = 5.25V, VI = O.4V

-1.6

mA

'CCIONI

Supply Current, Expander On

1.2

2.5

mA

2

4

mA

Vee = 5.5V, VI = 4.5V
Vx = O_85V, Ix = 0

ICCIOFFI

Supply Current, Expander Off

Vee = 5.5V, VI = 0
Vx = 0.85V, Ix = 0

en
en

MAX

2

TA =-55°C

IXIOFF)

TYP(l)

0.8

Low Level Input Voltage

On-State Expander Current

MIN

2

VIL

IXIONI

CONDITIONS

UNITS

1.2

2.5

2

4

Vee = 5.25V, VI = 4.5V
Vx = 0.85V, Ix = 0

0

Vee = 5.25V, VI = 0
Vx = 0.85V, Ix = 0

3:
U1
~

.......
0

Notes
111 All typical values are at VCC = 5V, TA = 25°C.

3:
~

0)

0

m
)(

'0
I»

::;,

Co
CD-

til
----- -

- - - - - ---------

Electrical Characteristics

DM54H

DM74H

H60, H62

PARAMETER
CONDITIONS
VIH

High Level Input Voltage

Vil

Low Level Input Voltage

VXX{ON)

On-State Voltage Between Expander Outputs

MIN

H60, H62
TYP(l)

MAX

Vee = 4.5V, V IH = 2V

On-State Expander Current

V
V

Vee = 4.75V, V IH = 2V
0.4

Vee = 5.5V, V IH = 2V

Vee = 5.25V, V IH = 2V
0.4

0.4

V x = 1V, I x: = 6.3 mA
T A = O°C

V
0.4

V x =lV,Ix:=7.4mA
T A = 70°C

Vee = 4.5V, V IH = 2V

Vee = 4.75V, V IH = 2V
-470

V x =lV,Ix:=O

TA =-55°C
Off-State Expander Current

(I)

MAX

0.8

T A = -55°C

Vx = lV, IX: = 0

IXIOFF)

UNITS
TYP(l)

0.8

Vx = lV, Ix: = 7.85 mA

(!)

MIN
2

TA = 125°C

'"

CONDITIONS

2

Vx = lV, Ix: =5.85 mA

IXIONI

~I
(1)1

over recommended operating free-air temperature range (unless otherwise noted).

-BOO

JlA

T A = O°C

Vee = 4.5V, V IL = 0.8V

Vee = 4.75V, V IL = 0.8V

Vx: = 4.5V, Rx = 575[2

320

T A = -55°C

Vx: = 4.5V, Rx = 575[2

570

JlA

T A = O°C

II

Input Current at Maximum Input Voltage

Vee = 5.5V, VI = 5.5V

1

Vee = 5.25V, VI = 5.5V

1

mA

i lH

High Level Input Current

Vee = 5.5V, VI = 2.4V

50

Vee = 5.25V, VI = 2.4V

50

JlA

C
~

III

Low Level I nput Current

Vee = 5.5V, VI = O.4V

mA

-.....

ICCION)

ICCIOFF)

Supply Current, Expander On

Supply Current, Expander Off

Expander Output Capacitance

Cx

-2

Vee = 5.25V, VI = O.4V

H60

Vee = 5.5V, VI = 4.5V

1.9

3.5

Vee = 5.25V, VI = 4.5V

1.9

3.5

H62

Vx = 0.85V, Ix: = 0

3.8

7

Vx = 0.85V, IX: = 0

3.8

7

H60

Vee = 5.5V, VI = 0

3

4.5

Vee

3

4.5

H62

Vx = 0.85V, Ix: = 0

6

9

V x =0.85,1x:=0

6

9

H60

Vee, I nputs, and X

5.4

Vee, I nputs, and X

5.4

H62

Open; f = 1 MHz

6.0

Open; f = 1 MHz

6.0

= 5.25V, VI = 0

mA

mA

U1
~

C
~

~

:t:
c:n
0
J:

c:n

pF

N

m
><

"0

Notes

III

-2

Q)

All typical values are at Vee

= 5V lexcept ex), TA = 25°e.

:l

0.

.,

CD

en
-

..

---------

--

Electrical Characteristics

~

over recommended operating free-air temperature range (unless otherwise noted)_
DM54H/74H

PARAMETER

H61
CONDITIONS

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

VX(ONI

On-State Expander Output Voltage

UNITS
MIN

TYP(l)

MAX

2

Vee

(J)
(J)

V
0_8

V

= Min, V ,H = 2V, Ix = 4.5 mA for DM54H61
= Min

1

V

5.35 mA lor DM74H61, T A

cr,

IX(OFFI

Off-State Expander Current

Vee

= Min, V ,L = 0.8V, Vx = 2.2V, TA = Max

50

I1A

11

Input Current at Maximum Input Voltage

Vee

= 5.5V, V, = 5.5V

1

mA

IIH

High Level Input Current

Vee

= 5.5V, V, = 2AV

50

I1A

IlL

Low Level I nput Current

Vee

= 5.5V, V, = OAV

ICC(ONI

Supp,ly Current, Expander On

Vee

= 5.5V, V, = 4.5V

11

16

mA

ICCIOFFI

Supply Current, Expander Off

Vee

= 5.5V, V, = a

5

7

mA

Cx

Expander Output Capacitance

Vee and I nputs Open, I

-2

mA

a

= 1 MHz

504

pF

Noles
(11

All typical values are at VCC = 5V (except CX), TA

(21

The H52 is designed for use with up to six H61 expanders.

=

25°C.

C

s:
U'I
~

.......
C

s:

"::t
~

...

en

,

m
><

'0
III

:::I

C-

...

CD
1/1

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted).

~

DM74S
PARAMETER

CONDITIONS

S65
MIN

VIH

High Level Input Voltaqe

Vil

Low Level Input Voltage

VI

Input Clamp Voltage

IOH

High Level Output Current

TYP(1)

UNITS
MAX

2

Vee

= Min,

Vee

= Min, VIL = 0.8V
= 5.5V

V OH

11

Cf)
Cf)

V

= -18 mA

0_8

V

-1.2

V

250

/.l-A

V

VOH

High Level Output Voltage

5.5 .

IOl

Low Level Output Current

20

mA
V

VOL

Low Level Output Voltage

Vee

= Min, V IH = 2V,l oL = 20 mA

0.5

II

Input Current at Maximum Input Voltage

Vee

= Max, VI = 5.5V

1

mA

C
~

IIH

High Level Input Current

Vee

= Max, VI = 2.7V

50

/.l-A

Cf)

-..J

6>1

III

Low Level I nput Current

Vee

= Max, VI = 0.5V

ICCH

Supply Current, Output High

Vee

= Max

6

11

mA

ICCl

Supply Current, Output Low

Vee

= Max

8.5

16

mA

-2

mA

~

0)

U1

0

"C
CD

:::s

C")
Notes
(1) All typical values are at

0

Vee ==

CD

5V, T A = 25° c.

....

(")

...
I»z
0

Switching Characteristics

at Vee

= 5V, T A = 25°C

19

DM74S
CONDITIONS

PARAMETER

1

S65
MIN

tplH

tpHL

Propagation Delay Time, Low-To-High Level Output

Propagation Delay Time, High-To-Low Level Output

= 15 pF, RL = 28011
CL = 50 pF, RL = 28OS2

2

= 15 pF, RL = 28OS2
= 50 pF, RL = 28011

2

CL

CL
CL

TYP

UNITS

0
:Xl
,

S"

MAX

<

5

7_5

ns

8

12

ns

5.5

8.5

ns

6.5

10

ns

CD

::+

C)

....CD
C)

1/1

Electrical Characteristics

~

over recommended operating free-air temperature range (unless otherwise noted).
DM54/74

PARAMETER

CONDITIONS

70
MIN

V,H

High Level Input Voltage

V ,L

Low Level Input Voltage

V,

Input Clamp Voltage

IOH

High Level Output Current

VOH

High Level Output Vpltage

Low Level Output Current

VOL

Low Level Output Voltage

Vee

Vee

= Min,

I,

= -12

-

= Min, V ,H = 2V
= O.SV, IOH = Max

2.4

V'L

High Level Input Current

Vee

= Max, V, = 5.5V

0.2

Preset

Vee

= Max, V, = 2.4V

Clock
I'L

D, J, K, or K
Clear

Preset

Vee

= Max, V,

= O.4V

I DM54
I DM74

Clock

Icc

Current

Vee

= Max(2)

Supply Current (Average per Flip-Flop)

Vee

= Max(3)

TYP(1)

MAX

MIN

TYP(1)

V

0.8

O.S

-1.5

-1.5

-1.5

-400

-400

-400

-1200

2.4

2.4

3.4
16

0.4

0.2

16

0.4

0.2

0.4

0.2

mA

0.4

V

1

1

1

1

40

40

40

SO

SO

120

160

SO

SO

40

SO

40

SO

SO

SO

-1.6

-1.6

-1.6

-1.6

-3.2

-3.2

-3.2

-4.S

-3.2

-3.2

-1.6

-3.2

-3.2

-20

-55

-20

-55

-30

-55

-S5

-lS

-57

-18

-55

-18

-55

-30

-55

-S5

10

15

26

17

9

S.5

15

mA

C

p.A

3:
c.n
~

.......
C
mA

-3.2

-20

~57

13

V
p.A

16

40

-3.2

V

V

2.4

3.4

C/)
C/)

MAX

2

0.8

-1.6

Short Circuit Output

loS

MIN

-1.5

3.4

D, J, K, or K
Clear

MAX

UNITS

109

2

16

Input Current at Maximum Input Voltage

Low Level I nput Current

TYP(l)

74

2

mA

= Min, V ,H = 2V
= O.SV, IOL = 16 mA

Vee

I'H

0,

MIN

0.8

I,

N

MAX

2

V'L
10L

TYP(l)

72, 73, 76, 107

mA
rnA

3:
~
.....

....N0
....W
....
....en
~

Notes
(1)
(2)
(3)

.

All typical values are at VCC = 5V, TA = 25°C.
Not more than one output should be shorted at a tlme._
With all outputs open, ICC is measured with the Q and Q outputs high in turn. At the time of measurement. the clock input is at 4.5V for.the 70, and is grounded for all the others.

:..
0
.....

:..
0

CD

~

'CI

."

0"

'C

III

~

Switching Charjlcteristics at Vcc = 5V, T A = 25°C
DM54/74
PARAMETER

fMAX

Maximum Clock Frequency

tpLH

Propagation Delay Time,

Low-ta-High Level Output
tpHl

Propagation Delay Time,

tplH

Propagation Delay Time,

FROM
(INPUT)

tpHl

Propagation Delay Time,

tpLH

Propagation Delay Time,

CONDITIONS

(as applicable)

TYP

20

35

20

MAX

TYP

20

25

MAX

MIN

TYP

30

40

fJ)
fJ)

UNITS
MAX
MHz

25

9

14

D

50

25

40

40

18

29

50

16

25

25

9

14

50

25

40

40

17

25

27

50

16

25

14

25

12

18

18

50

25

40

20

40

19

28

ns

CL = 15 pF. RL = 400Q

ns

(as applicable)

0

ns

OorO

High-ta-Low Level Output

""w

15

109

74.
MIN

25

Propagation Delay Time,

Clock High

TYP

16

D

Clock

Pulse Width

MIN

50

Low-ta-High Level Output

tw

MAX

0

Clear

High-ta-Low Level Output

tPHl

72, 73, 76, 107

70
MIN

Preset

High-ta-Low Level Output

Low-ta-High Level Output

TO
(OUTPUT)

20

20

30

20

Clock Low

30

47

37

20

Preset or Clear Low

25

25

30

20

C
~

U1

ns

tsETUP

Input Setup Time(4)

20t

ot

20t

15t

ns

tHOLD

Input Hold Time(4)

5t

01

5t

lOt

ns

~

.......
C
~
-.J
~

-.J

0
;".,.

Notes
(4)

t

-l-

The arrow indicates the edge of the clock pulse used for reference: t for the rising edge, ~ for the falling edge.

N

;".,.
to)

~

;".,.
0')
~

0

-.J

~

0

to

"T1

"9'
"T1

0"

'0
/II

-

~-

Electrical Characteristics

~

over recommended operating free·air temperature range (unless otherwise noted).
DM54Hn4H

PARAMETER

CONDITIONS

H71
MIN

VIH

High Level I nput Voltage

V IL

Low Level I nput Voltage

VI

Input Clamp Voltage

10H

High Level Output Current

V OH

High Level Output Voltage

Low Level Output Current

VOL

Low Level Output Voltage

Vee = Min, V ,H = 2V

,L = O.BV, IOH = Max

Vee

I,

Input Current at Maximum Input Voltage

IIH

High Level I nput Current

= Min, V ,H

Vee

= 2V

a.av, IOL

= Max, V,

Low Level Input Current

MAX

0,2

MIN

TYP(1)

MAX

2

MIN

TYP(1)

2

V

O.S

0.8

V

-1.5

-1.5

-1.5

-1.5

V

-500

--500

-1000

--500

pA

2,4

2,4

3,4

3,4

20

0.4

0.2

2,4

3,4

20

0,4

0.2

0.4

0.2

V
20

mA

0.4

V

1

1

1

1

D,J, or K

50

50

50

50

Clear

N/A

100

150

200

150

100

100

100

100

50

100

100

Vee = Max, V, = 2,4V

-2

D,J,or K
Clear

Vee = Max, V,

Preset

N/A

= O.4V

--5
-4

Clock
-40

Vee = Max(2)

loS

Short Circuit Output Current

Icc

Supply Current (Average per Flip·Flop)
Vee = Max(3)

1lDM54
DM74

-100

-40

-2

-2

-2

-4
-4

-4

-a

-2

-4

-2

-4

-4

'-100

-100

-40

-100

19

30

16

25

15

21

16

25

19

30

16

25

15

25

16

25

Notes
All typical values are at Vee = 5V, T A = 25°e.
(2) Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
(3) With all outputs open, ICC is measured with the Q and Qoutputs high in turn. At the time of measurement, the clock input is grounded.

(1)

-40

en
en

MAX

0.8

= 20 mA

= 5.5V

UNITS

H78

O.S

3,4

Clock

I'L

TYP(1}

20

Preset

""

2,4

MIN

H74

2

Vee = Min, 'I, = -S mA

V ,L =

a,

MAX

2

V
10L

TYP(1)

H72,H73,H76

mA

C

3:

U1

JiA

~
......

C

3:
~

mA

:s
-"

~
mA
mA

....
N

~

....W

~J:

....en
~
....CO
."

'9'
."

0'

'0
(II

-

-

Switching Characteristics atV cc =5V,T A =25°C

~
DM54H174H
FROM
(INPUT)

PARAMETER

fMAX

Maximum Clock Frequency.

tpLH

Propagation Delay Time,

TO
(OUTPUT)

H71, H72
H73,H76,H78

CONDITIONS

MIN

TYP

25

30

Q

Low-to-High Level Output

6

Cf)
Cf)

H74

MAX

MIN

TYP

35

43

13

UNITS
MAX
MHz
20

Preset las applicable)
tpHL

Propagation Delay Time,

0

High-to-Low Level Output
tpLH

ns

Propagation Delay Time,

0

Low-to-H igh Level Output

C L = 25 pF,

RL =

280[2

12

24

30

6

13

20

12

24

30

Clear las applicable)
tpHL

Propagation Delay Time,
High-to-Low Level Output

0.,

tpLH

14

tSETUP

tHOLD

Setup Time(4)

15

~

-..J

ns
22

High-to-Low Level Output
tw

8.5

21

0

GorO

Propagation Delay Time,

Pulse Width

U1
~

Propagation Delay Time,
Clock

tpHL

~

........

Low-to-High Level Output

01

0

ns
G

27

13

Clock High

12

15

Clock Low

28

13.5

Clear or Preset Low

16

25

High Level Data

ot

lOt

Low Level Data

ot

15t

ot

5t

Hold Time(4)

~

:I:

20

....

-..J

:I:
-..J
N

ns

~

-..J
W

ns

~

ns

~

-..J

~

-..J

Q)

Notes
(4) .} t The arrow indicates the edge of the clock pulse used for reference; t for the rising edge,

~

+for the falling edge.

00
~

~.

'"T1

0"

'C
(II

-_ ... _ - - - -

--_ .. -

-------------------

----

-

-

-

-------

-

Electrical Characteristics

~

over recommended operating free-air temperature range (unless otherwise noted).
DM54U74L
L71, L72

CONDITIONS

PARAMETER

MIN
VIH

High Level Input Voltage

Vil

Low Level Input Voltage

TVP(1)

MAX

High Level Output Current

VOH

High Level Output Voltage

VOL

II

Vee

::0

Min, V'H "" 2V

Low Level Output Current

Low Level Output Voltage

IIH

MIN

TVP(1)

MAX

MIN

TVP(1)

0.6

V

0.7

0.6

0.7

0.7

0.7

0.7

-200

-200

-200

-200

DM54L

2.4

3.3

2.4

3.3

2.4

3.3

2.4

3.3

DM74L

2.4

3.2

2.4

3.2

2.4

3.2

2.4

3.2

DM54

2

2

2

2

DM74

3.6

3.6

3.6

3.6

DM54L

0.15

0.3

0.15

0.3

0.15

0.3

0.15

0.3

V 1L

DM74L

0.2

0.4

0.2

0.4

0.2

0.4

0.2

0.4

Max, IOL ::::: Max

Iflput Current at

R, S, J, K, or 0

100

100

100

100

Clear

200

200

300

400

Vee

High Level Input Current

Max, V, o5.5V

200

200

200

200

Clock

200

200

200

400

R, S, J, K, or 0

10

10

10

10

20

20

30

40

20

20

20

20

Clock

-200

-200

20

-400

R,S.J, K, or 0

-(J.18

-(J.18

-(J.18

-(J.18

-0.36

-(J.36

-0.36

-0.72

-(J.36

-(J.36

-(J.18

-(J.36

-0.36

-(J.36

-(J.36

-(J.72

Vee

Preset

low level I nput Current

0

Clear

Vee

Preset

0

0

Max, V, o2.4V

Max, V, °0.3V

Clock
loS

Short Circuit Output Current

Vee

= Max

IcC

Supply Current

Vee

0

Notes
(1) All typical values are at VCC 5V, TA = 25°C.
(2) With all outputs open, ICC is measured with the

-3

-9

-15

-3

1.44

0.76

Maxl2)

-9
1.52

-15
2.88

-3

--9

1.6

-15
3.0

-3

-9
1.52

V
I"A
V

Vee::::: Min, V 1H = 2V
=;

(J)
(J)

MAX

2

Maximum Input Voltage

Clear

til

MAX

UNITS

L78

2

0.6

Preset

6Q)

TVP(1)

2

Clock Input

V!L ::::: Max, IOH = Max

IOl

MIN

2
All Other Inputs

IOH

L74

L73

-15
2.88

rnA

V

I"A

0

3:

I"A

U1
.j::o.

......
0

rnA

3:
~

Ci
Ci
N

~
rnA
rnA

Ci

~
.-

0

Q

and Q outputs high in turn. At the time of measurement, the clock input is grounded.

Ci
.j::o.
Ci
CO
"T1

~
"T1
6"

tI

III

_ ..

--

-_.

--

-

----

Switching Characteristics

at Vee; 5V, T A

;

~

25°C
DM54L/74L
FROM
(INPUT)

PARAMETER

L71, L72, L73, L78

-

Maximum Clock Frequency

tpLH

Prop~gation

6

Delay Time,

Preset or Clear

Low-to-High Level Output

Oor

I

Propagation Delay Time,
High-to-Low Level Output

tpLH

CONDITIONS

MIN

fMAX

tpHL

TO
(OUTPUT)

0

-' (Clock High)
Preset or Clear
(Clock Low)

OorO

Clock

OorO

C L ; 50 pF, RL ; 4

Propagation Delay Time,

Pulse Width

a,
....,

MIN
6

TYP

UNITS
MAX

U)
U)

-

MHz

11

35

75

40

60

60

150

60

120

150

60

120

10

35

75

10

50

90

10

60

150

10

60

120

ns

ns

ns

Propagation Delay Time,
High-to-Low Level Output

tw

MAX

11

kn

Low-to-High Level Output
tpHL

TYP

L74

Clock High

100

75

Clock Low

100

75

Clear or Preset Low

100

75

ns

C

s:<11

tSETUP

Setup Time(3)

ot

50t

ns

~
.......

tHOLD

Hold Time(3)

ot

15t

ns

s:

C

~

~

Notes
(3)

t.J, The arrow indicates the

~
Ci
N

edge of the clock pulse used for reference: t for the rising edge 4. for the falling edge.

Ci

to)

Ci

~

Ci
CO

"T1

'9'
"T1

0'

'C
(II

-

-

-

-

-

--- - -

- - - - _ .. _--

----

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted).

~
DM54LS/74LS

PARAMETER

LS73. LS76, LS107
LS112, LSl13

CONDITIONS

MIN
V,H

High Level Input Voltage

V,L

Low level Input Voltage

V,

Input Clamp Voltage
High Level Output Current

VOH

High Level Output Voltage

VOL

Vee;:: Min, V 1H

=

2V

V 1L "'- Max. IOH

= -40QuA

Low Level Output Current

Low Level Output Voltage

Vee

= Min

I I OL

V 1H '" 2V

Input Current at Maximum

=

V,

D, J, K, or k

Input Voltage
Clear

m
00

Preset

Vee

= Max

~ Max

l' Ot -4mA

Max

~

7V

V,

5.5V

High Level Input Current

r

DM74

0.8

0.8

0.8

0.8

-1.5

-1.5

-1.5

-1.5

-400

-400

-400

-400

DM54

2.5

DM74

2.7

3.4

2.5

3.4

2.7

(2)

(4)

2.5

3.4

-2.5

3.4

3.4

2.7

3.4

2.7

3.4

DM54

4

4

4

4

OM74

8

8

8

8

0.25

0.4

0.25

0.4

0.25

DM74

0.35

0.5

0.35

0.5

0.35

DM74

0.4

0.4

0.25

0.4

0.5

0.35

0.5

0.6
0.2

0.2
0.2

20

120

80

60

40

60

40

80

40

160

40

D,J,Kor K

-0.36

-0.4

-0.36

-0.4

Clear

-0.8

-1.2

-1.6

-1.6

-0.8

-0.8

-0.8

-0.8

-0.72

-0.8

-1.44

-0.8

Supply Current

Vee

=:

Max(3)

4

-30

8

-130
4

8

-30

-130
4

8

....
~

'"
~

rnA

"'"
0)

CO

:...

....

0

20

-130

""3:0
W

0.8
20

-30

~

en
....

0.2

0.4

U'I

r-

r-

0.3

0.3

5.5V

60

Vee ~ Max(2)

V

0.4

0.3

5.5V

Vee"" Max, VI == OAV

rnA

0.1
0.3

0

3:

en

0.1

0.1
0.1

Vee =- Max, V, = 2.7V

V

/1A

0.4

0.4

0.4

-

V

V

20

Current

(3)

3.4

DM54

en
en

V

2

60

Short Circuit Output

Notes
(1) All typical values are at Vee

MAX

D,J,K or K

Preset

Icc

TYP(1)

0.7

Clock

los

MIN

0.7

Clock

Low Level I nput Current

MAX

Clear
Preset

I,L

TYP(l)

UNITS

0.7

V, -7V
I'H

MIN
2

2

V, -7V

V,

MAX

LS109

0.7

VI -7V
Clock

TYP(1)

5.5V

V,

V,

MIN

LS78, LSl14

DM54

Vee"" Min, II "" -18 rnA

V1L
I,

MAX

2

10H

10L

TYP(1)

LS74

-30
4

:...
pA

0
CD

:...
~

N

:...
rnA

~

W

:...
~

~

~130

rnA

0

8

rnA

!.

C

!!

= 5V, TA

25°C.
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
With all outputs open, ICC is measured with the Q and Q outputs high in turn. At the time of measurement; the clock input is grounded.
=:

National Semiconductor temporarily reserves the right to ship DM54/DM74LS73, LS74, LS76, LS78, LS107, LS109, LS112, LS113, LSl14

devices which have a minimum lOS

= 5.0 rnA.

_ .. -

_._.-

-

"9'
'TI

0'

"C

C/)

Switching Characteristics atV cc =5V,T A =25°C

~

DM54LSi74LS
PARAMETER

fMAX

Maximum Clock Frequency

tplH

PropagatIon Delay Time,

IpHL

FROM
(INPUT)

Low-ta-High Level Output

Clear, Preset, or Clock

Propagation Delay Time,

{as appropriate}

TO
(OUTPUT)

Oor

6.

CONDITIONS

CL

=

LS73, LS76, LS78, LS107
LS112, LS113, LS114
MIN

TYP

30

45

15pF,R L =2kU

Hlgh-ta-Low level Output

'w

Pulse WIdth

tSETUP

Setup Time(5J

tHOlO

MAX

LS74
MIN

TYP

25

33

LS109
MAX

MIN

TYP

25

33

MHz

20

13

25

13

25

ns

15

30

25

40

25

40

ns

20

25

25

Preset or Clear Low

25

25

25

High Level Data

201

251

201

Low Level Data

201

201

201

01

51

51

en
en

MAX

11

Clock High

Hold Tlme(5)

UNITS

ns

C

s:U1

~

r

en

ns

........

ns

....s:

C

~

Notes
(5) t t The arrow indicates the edge of the clock pulse used for reference: t for the rising edge,

-J.

for the falling edge.

r
....en

to)

m
to

",,-"
~

en
CO

:...

....0

:...
0
e.g

:...
....
N

....

:...

to)

:...
....
~

C

I:

~

"
"9'

"0'

"C

III

Electrical Characteristics

~

over recommended operating free-air temperature range (unless otherwise noted!.
DM74S
CONDITIONS

PARAMETER

S74
MIN

VIH

High Level Input Voltage

Vil

Low Level I nput Voltage

VI

Input Clamp Voltage

10H

High Level Output Current

VOH

High Level Output Voltage

Vee

Vee

10l

Low Level Output Current

VOL

Low Level Output Voltage

II

Input Current at Maximum Input Voltage

IIH

High Level I nput Current

= Min, I, = -18 mA

= Min, V'H = 2V
= 0.8V, IOH = -1 rnA

2.7

= Max, V, = 5.5V

J, K, or 0
Preset

Vee

= Max, V, = 2.7V

Clock
III

Low Level I nput Current

TYP(1)

MAX

-1.2

-1.2

-1.2

-1

-1

-1

3.4

2.7

los
Icc

Supply Current

Vee

= Max(3}

20

mA

0.5

0.5

0.5

0.5

V

1

1

1

1

50

50

50

50
200

150

100

N/A

100

100

100

100

100

100

100

200

-4
-100
30

V

20

-7

-40

3.4

V
mA

20

-4

= Max(2)

2.7

3.4

V

20

-7

Vee

V

-1
2.7

50

-1.6

-100
30

50

Notes
(1) All typical values are at VCC = 5V, T A = 25"C.
(2) Not more than one output should be shorted at a time, and duration of short circuit should not exceed one second.
(3) With all outputs open, ICC is measured with the Q and Q outputs high in turn. At the time of measurement, the clock input is grounded.

-14

-7

-7

-4
-40

-100
30

50

rnA

fJ.A

C

-1.6

N/A

-4
-40

C/)
C/)

MAX

-1.2

-1.6

Clock

TYP(11

2
0.8

-2

Short Circuit Output Current

MIN

0.8

-6

= Max, V, = 0.5V

MAX

UNITS

0.8

Clear

Vee

TYP(l)

2

J, K, or 0

Preset

MIN

S114

0.8

3.4

= Min, V'H = 2V
V'L = 0.8V, 10L = 20 mA
Vee

MIN

S113

2

Vee

Clear

.:..,

MAX

2

V'L

o

TYP(1)

S112

rnA

-8
-40
30

-100

mA

50

mA

3:
~
C/)
.....
,J:o

en...
N
en...
Co)

...

C/)

,J:o

C

c
!!!.
~

'CI

.."

S"

'C
(II

Switching Characteristics at Vee; 5V, T A ; 25°C

~
DM74S

FROM
(INPUT)

PARAMETER

fMAX

Maximum Clock Frequency

tpLH

Propagati on Del ay Ti me,
Low-to-High Level Output

-tPHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Preset or Clear

Preset or Clear

TO
(OUTPUT)

Oor
High)
II (Clock
(Clock Low)

CONDITIONS

S74
MIN

TYP

75

110

a

Oor 0

;

15 pF,

RL ;

280[1

Low-to·High Level Output
Clock
tpHL

Oor

tHOLD

125

6

2

4

7

9

13.5

2

5

7

5

8

2

5

7

6

9

2

4

7

Pulse Width

6

9

2

Clock High

6

Clock Low

7.3

6.5

Clear or Preset Low

7

8

Input Setup

High Level Data

3t

3-1,

Time(4)

Low Level Data

3t

3-1,

2t

0-1,

Input Hold Time(4)

Notes
141 t! The arrow indicates the edge of the clock pulse used for reference: t for the rising edge, .\. for the falling edge.

en
en

MHz
ns

ns

ns

Propagation Delay Time,

.:.,
tSETUP

80

0

H igh-to-Low Level Output
tw

TYP

Propagation Delay Time,

MAX

UNITS

MAX

MIN

4

CL

S112,Sl13,Sl14

5

7

6
ns

C
~

ns
ns

.....
~
en
.....
~
en

...
en
......w
......en
N

~

C

c:

Q)

::!!

"9

"T1

0'

'C

(/)

.,

Electrical Characteristics

DM54/74
CONDITIONS

PARAMETER

High Level Input Voltage

V,L

Low Level I nput Voltage

V,

IOH

High Level Output Current

High level Output Voltage

IOL

VOL

MIN

TYPll)

2

2

0.8

0.7

0.8

0.8

-1.5

-1.2

-1.5

N/A
N/A
-200

-400
3.4

V 1L

DM74

2.4

3.4

2.4

3.2

2.7

3.4

::::

Max

Vee = Max

Max

IOL =4mA

V,

=

5.5V

V,

=

7V

1000
N/A
2.7

V

V
i'A
V

3.4

DM54

16

2

4

N/A

DM74

16

3.6

8

20

DM54

0.2

OA

0.15

0.3

0.25

0.4

N/A

DM74

0.2

0.4

0.2

0.4

0.35

0.5

0.5

mA

V

C

OA

DM74
1

0.2

1
0.2

mA

N

I'H

I,L

High Level I nput Current

Vee

=

Max

V, = 2.4V

V,

Low Level I nput Current
Vee == Max

40

20

V, - 2.7V
=

40

0.3V

50

'-1.6

-0.6

mA

V, = 0.5V
los

ICCH

'eeL

Vee

Short Circuit Output Current

Supply Current, All Outputs High

Supply Current, All Olltputs Low

=

Max(2)

Vee = Max(3)

/lA

-0.36

V,=OAV

-20

-55

-3

-15

-30

-130

DM74

-18

-55

-3

-15

-30

-·130

N/A
-40

-100

DM54

30

43

2.2

4.4

6.1

10

N/A

DM74

30

50

2.2

4.4

6.1

10

50

36

57

3.8

6.68

Vee = Max(4)

s:
(J1

~
......

0

s:
l!
00
0)

-2
DM54

fJ)
fJ)

V

DM74

2.5

tOL ::::

UNITS
MAX

N/A

33

Max

TYPll)

2

2A

IOH ::::

MIN

0.7

3.4

Max,

586

MAX

0.7

2.4

Vee:::: Min

I nput Voltage

TYPll)

0.8

1,--18mA

Low Level Output Current

Input Current at Maximum

MIN

DM54

::::

DM74S

LS86, LS386
MAX

Vee:::: Min, V 1H = 2V

VIL

.:.,

L86
MAX

-800

Low Level Output Voltage

DM54 LS/74 LS

DM54

I, =-8 mA

Vee = Min

V'H = 2V

I,

TYP(11

2

Input Clamp Voltage

VOH

DM54l/74L

86
MIN

V,H

~

over recommended operating free-air temperature range (unless otherwise noted).

jrnA

fJ)

W
00

0)

75

rnA
rnA

m
X

(")
I""

C

Notes
All typical values are at V CC = 5V, T A = 25° C.

fJ)

(1)

pe shorted at a time, and for

(2)

Not more than one output should

(3)

leCH is measured with all outputs open, one input of each gate at 4.5V. and the other inputs grounded.
leeL is measured with all outputs open and all inputs at 4.5V.

(4)

DM54LS/DM74LS and DM74S, duration of short circuit should not exceed one second.

<:m

6::D

C')
III

...

m
_.

__ ._-

--

Switching Characteristics

DEVICE

CONDITIONS
(FROM INPUT A OR B)

I

tpLH (ns)
Propagation Delay Time,
Low-to-High Level Output
TYP

86

Other I nput Low

15

23

11

18

30

13

17
22

I C L = 50 pF

Other I nput Low

37

60

21

60

= 4k[1

Other I nput High

25

60

35

60

= 15 pf

Other I nput Low

12

23

10

17

= 2k[1

Other Input High

18

30

13

22

= 15 pF

Other I nput Low

12

23

10

17

= 2k[1

Other I nput High

18

30

13

22

IC L =15pF

Other I nput Low

7

10.5

6.5

10

= 280[1

Other I nput High

7

10.5

6.5

10

IC

L

IC

L

RL

S86

~I

.:.
w

,

MAX

Other Input High

RL

LS386

TYP

= 400[1

RL

LS86

MAX

tpHL (ns)
Propagation Delay Time,
High-to-Low Level Output

I CL = 15 pF
RL

L86

~

atV cc =5V,T A =25°C

RL

m
m

c

3:
(J1
0l:Io

.......

c

3:
~

CD

en
Im
eN
CD

en

~
("')

E
m
<:m
6,;J

C)

!a
CD
III

Electrical Characteristics

~

over recommended operating free-air temperature range (unless otherwise noted).
DM54H/74H
CONDITIONS

PARAMETER

H103
MfN

VIH

High Level Input Voltage

VIL

Low Level I nput Voltage

VI

Input Clamp Voltage

10H

High Level Output Current

VOH

High Level Output Voltage

TYP(1)

Vee

~

Min, II

Vee

~

Min, V IH

~

2V

O.BV, IOH

~

-500JlA

Min, V IH

~

2V

O.BV, IOL

~

20 mA

~

~

-B mA

2.4

V IL
II

Input Current at Maximum Input Voltage

IIH

High Level Input Current

Vee

~
~
~

Max, VI

~

Clear

Vee

~

Max, VI

~

Low Level I nput Current

0.2

5.5V

2.4V

Clock

Clear
Preset

Vee

~

Max, VI

~

O.4V

Clock

loS

Short Circuit Output Current

Vee ~ Max(2)

Icc

Supply Current

Vee

~

Max, (3)

TYP(1)

MAX
V

2
O.B

O.S

V

-1.5

-1.5

V

-500

-500

-500

2.4

3.4

2.4

0.4

0.2

0.4

0.2

mA

0.4

V

1

1

1

50

50

100

100

200

N/A

100

100

-1

-1

0

-1

-2

-1

-2

-1

-2

-1

-2

-1

-2

-2

-4

N/A

-1

-2

-1

-2

-3

-4.B

-3

-4.B

---u

-9.6

-40

-100
40

-40

76

= 5V, T A = 25 C.

(1)

All typical values are at VCC

(2)

Not more than one output should be shorted at a time, and duration of short circuit should not exceed one second.
With all outputs open, ICC is measured with the Q and Q outputs high .in turn. At the time of measurement, the clock input is grounded.

0

-100
40

76

-40
40

JlA

20

50

0

-

V

3.4

20

NoteS

(3)

MIN

O.B

-1

0

Any J or K

MAX

-1.5

3.4

Any J or K
Preset

IlL

TYP(1)

20
Vee

Low Level Output Voltage

.:...
",.

MIN

en
en

UNITS

H10S

2

Low Level Output Current

VOL

MAX

2

V IL
10L

H106

mA

0
~
JlA

U'I

mA

.......
0
~

mA

J:
~
0

~

~

W

-100

mA

J::

76

mA

en

~

0

J:
~
0
00

0
C

!!..

;!;!
"0
I
."

0"

"0
fI)

'---------..

Switching Characteristics

FROM
(INPUT)

PARAMETER

f MAX

Maximum Clock Frequency

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Preset or Clear

Propagation Delay Time,
High-to-Low Level Output

tplH

~

atV cc :5V,T A :25°C

Preset or Clear

II Clock High
Clock Low

TO
(OUTPUT)

Oor

a

Oor

a

MIN

TYP

40

50
8

CL

:

25 pF,

RL :

280n

Propagation Delay Time,
Low-to-High Level Output
Clock

tpHL

CONDITIONS

Propagation Delay Time,

Oor

.:..,

Pulse Width

tSETUP Setup Time(4)

01

tHOLD

Clock High

10
15

Clear or Preset Low

16

Hold Time(4)

CJ)
CJ)

12

15

20

23

35

10

15

16

20

ns

ns

ns

Clock Low

I High Level Data
I Low Level Data

UNITS
MHz

a

High-to-Low Level Output
tw

MAX

lOt
13~
O~

ns

0

3:
(J'I

~

ns

.......

ns

3:
.....

0

~

Notes
t The arrow indicates that the falling edge of the clock pulse is used for reference.

(4)

...::I:
l:
...
...::I:
0

W

0
0'1
0

CIO

C

c:
Q)

"T1

'CI
"T1

5"

'C
!II

---_._-------

--

-----

Electrical Characteristics

CONDITIONS

PARAMETER

MIN
Vol~age

VT+

Positive-Going Threshold

VT-

Negative-Going Threshold Voltage at A Input

at A Input

VT+

Positive-Going Threshold Voltage at B Input

V T-

Negative-Going Threshold Voltage at B Input

VI

Vee"" Min
Vee

=

Vee

=

.:..,

IOH

High Level

High Level Output Voltage

VOL

I,

=

= -400fJ.A

Low Level Output Current

Low Level Output Voltage

Input Current at Maximum Input Voltage

Min

Vee::: Max

High Level I nput Current

10L = 8 mA

Supply Current

TYP(l)
1.0

1.4

0.7

1.0

DM74

0.8

1.4

0.8

1.0

DM54

0.8

1.35

0.7

0.9

DM74

0.8

1.35

0.8

0.9

2

1.0

V, - 2.7V

Vce = Max(2)

Vee = Max

2

2.4

3.4

2.5

3.5

DM74

2.4

3.4

2.7

3.5

2

V
fJ.A
V

16

4

DM74

16

8

0.2

V
V

DM54

DM74

V
V

-400

DM54

en
en

MAX

-1.5

0:25

0.4

0.35

0.5

mA

V

0.4
1

V, = 7V
V, = 2.4V

UNITS

-1.5

V, = 5.5V

Low Level Input Current

Short Circuit Output Current

MIN

10L = 4 mA
:=;

Vee = Max, V, = O.4V

ICC

2

-400

'.

los

MAX

1.4

-18 mA

Vee = Min

Vee::: Max

III

TYP(l)

0.8

10L = 16 mA

IIH

LS221

Current

Vee

II

121

1.55

Vee == Min

10H

0)

DM54LS/74LS

DM54

Min

Vee = Min

V OH

IOl

Min

DM54/74

1,=-12mA

Input Clamp Voltage

O~tput

~

over recommended operating free-air temperature range (unless otherwise noted).

0.1
Al or A2

40

B

80

mA

0
~

fJ.A

......

U1

20

All
Al or A2

-1.6

--0.36

B

-3.2

--0.44

Clear

N/A

-{).54

DM54

-20

-55

-30

-150

DM74

18

-55

-30

-150

Quiescent

13

25

4.7

11

Triggered

23

40

19

27

~

0

~

I1)A

~

...

....
N

mA

r-

en
N
N

mA

....

0

::l

Notes
(1) All typical values are at VCC ~ 5V, T A ~ 25°C.
(2) Not more than one output should be shorted at a time, and for DM54LS221/DM74LS221, duration of short circuit should not exceed one second.
LS221 To Be Announced In 1976

CD

en
:r

...

0

1/1

Switching Characteristics at Vee = 5V, T A = 25° C
PARAMETER

~
FROM
(INPUT)

TO
(OUTPUT)

DM54/74

DM54LS/74LS

121

LS221

CONDITIONS

MIN

TYP

MAX

TYP

Al or A2

Q

45

70

45

70

ns

tpLH

Propagation Delay Time, Low-ta-High Level Output

B

Q

35

55

35

55

ns

tplH

Propagation Delay Time, low-ta-High Level Output

Clear

Q

CT = 80 pF

65

ns

tpHL

Propagation Delay Time, High-ta-Low Level Output

Al or A2

Q

RINT to Vee

50

80

ns

tpHL

Propagation Delay Time, High-ta-Low Level Output

B

Q

40

65

ns

tPHL

Propagation Delay Time, High-to"Low Level Output

Clear

Q

55

'"

tW(OUn

Output Pulse Width

CT

50

80

R T =2kSl

40

65

C L =15pF

RL

I nternal Timing Resistor

= 400~2

N/A
CT -- 80 pF

70

CT
Al, A2 or B

External Timing Resistor

Oar

6.

=

RINT

110

150

30

50

700

800

0

to Vee

C, = 100 pF
RT

=

10 kU

CT

"

1~F

R T =10kU

600

6

80 pF

N/A

7

8

CL

=

15 pF

RL

=

2 kU

C EXT =80pF
R EX1 = 2 ki2
CE X

T =

R EXT

=

2 kSZ

CT = 100pF
R T =10kU
CT
RT

70

120

150

20

47

70

600

6-10

750

6

67

75

0

0

1V F

=

10kU

tWON)

Input Pulse Width

50

40

tWICLEAR)

Clear Pulse Width

N/A

40

dv/dt

Rate of Rise or Fall

Schmitt Input, B

1

1

of Input Pulse

Logic I nput, A

REXT

External Timing Resistance

CEXT

External Timing Capacitance

tsETUP

Clear-Inactive State Setup Time
Duty Cycle

1

ns

1

VifJs

30

DM54

14

70

DM74

14

40

DM74

14

100

0

1000

1000

15

RT = 2 kll

67

RT

RT

90

RT = Max RT

=

Max

c

ms

Vis

1.4

N/A

ns

ns

DM54

0

(f)
(f)

MAX

Propagation Delay Time, Low-ta-High Level Output

RINT to Vee

-..J

MIN

tplH

Zero-Timing Capacitance

.:.,

CONDITIONS

UNITS

2Hl

67
90

kS2

0

3:

vF

U1

ns

.......
0

oS

~

3:
.....

.

REX1

....
....N
~

(f)

N

....N
0

::::I
CD

(f)

':!'

...

0

III
---

--

--

--

. Electrical Characteristics

PARAMETER

CONDITIONS
MIN

VIH

High Level Input Voltage

Vil

Low Level Input Voltage

VI

High Level Output Current

VOH

High Leyel Output Voltage

~
00

VOL

II

IIH

123

L123A

LS122, LS123

TYP(1)

MAX

MIN

TYP(1)

Vee = Min, IOH = Max(3)

Vee = Min IOL = Max
(3)
IOL = 4 mA

Input Current at Maximum Input Voltage

Vee = Max

2

Vee = Max

Data Inputs
Clear Input

los

Short Circuit Output Current

Icc

Supply Current (Quiescent or Triggered)

MIN

TYP(1)

2

V

0.7

0.7

DM74

0.8

0.8

0.8

-1.5

-N/A
-1.5
-200

-400

DM54

2.4

3.4

2.4

3.4

2.5

'3.5

DM74

2.4

3.4

2.4

3.4

2.7

3.5

DM54

16

2.0

4

16

3.6

8

0.2

0.4

DM74

0.2

0.4

0.22

0.3

0.25

0.4

0.4

0.35

0.5

0.25

0.4

DM74

VI = 5.5V

1

0.1

VI=7V

0.1
40

V
/lA

mA

0

V

20

mA

-10

/lA

-{l.18

-{l.4

-1.6

-Q.18

-Q.4

-12

-2.5

LS122
Vee = Max(4)(5)(6)
Others

46

66

5

7.5

N
N

:..
N

-1.6

-40

~

...

W

20

Vee = Max(2) (3)

s:....
r-

10

VI = 2.7V
Vee = Max, VI = O.4V

~

........
0

10

80

s:UI

en

VI = 2.7V
VI = 2.4V

V

V

DM74
DM54

en
en

MAX

0.8

VI = 2.4V

Data Inputs

MAX

UNITS

DM54

-800

Low Level Output Voltage

Low Level I nput Current

DM54 LS/74 LS

I

Clear Input
IlL

DM54L174L

.111=-12mA
Vee = Min
II =-18 mA

Low Level Output Current

High Level Input Current

DM54/74

2

Input Clamp Voltage

10H

10l

~

over recommended operating free·air temperature range (unless otherwise noted).

-30

-150
6

11

12

20

:...
N

mA

W

mA

0

»

C

0

m

mA

:::l

CD

-

en

:::l"
0

...
1/1

Switching Characteristics
PARAMETER

FROM
(INPUT)

Propagation Delay Time,

A

LON-ta-High Level Output

B

Propagation Delay Time,

A

High-ta-Low Level Output

B

DM54/74

DM54l/74L

123

L123A

TO
(OUTPUT)
CONDITIONS

tplH

tpHL

Q

D
Q

High-ta-Low Level Output
Propagation Delay Time,
Low-ta-High Level Output
tWQ(MIN) Minimum Width of Pulse

Aor B

at Output 0
Width of Pulse at Output

tWQ

C EXT

"'"

0

TYP

MAX

TYP

MAX

120

175

22

33

19

28

86

135

29

44

30

40

120

180

30

45

27

36

86

135

37

56

18

27

R EXT = 32 k[1

C L = 15 pF

18

27

Pulse Width

-:.,
<0

C L =15pF

RL = 2 kQ
30

45

Q

45

65

220

330

116

200

ns

34.0

37.4

4.5

5

ns

Q

R EXT = 10 kQ
C L =15pF

CEXT = 1000 pF
2.76

3.03

3.37

R EXT = 100 kQ
C L = 50 pF

CEXT = 1000 pF
30.6

RL = 4 kQ

R EXT = 10 k[1
C L = 15 pF

130

40

40

130

~

(J'1
ns

.j:a

........

40

~

5

25

5

200

5

225

DM74

5

50

5

400

5

360

0

kQ

~

-.J

.j:a
No Restriction

~
DM74

No Restriction

r

No Restriction

50

40

50

50

50

50

pF

...en
N
N

:...
N

Vee

(2)

Not more than one output should be shorted at a time, and for DM54LS/74LS duration of short circuit should not exceed one second.
Ground CEXT to measure VOH at Q, VOL at
or lOS at O. CEXT is open to measure VOH at 5, VOL at Q, or lOS at Q.
Quiescent i-cc is measured (after clearing) with 2.4V applied to all clear and A inputs, B inputs grounded, all outputs open, CEXT:=: O.02JJ.F, and REXT = 25 krl.
ICC is measured in the triggered state with 2.4V applied to all clear and 8 inputs. A inputs grounded, all outputs OPen, CEXT = O.02,uF, and REXT = 25 krl.
With all outputs open and 4.5V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5V, is applied to clock. (LS122, LS123)

(6)

0

40

All typical values are at

(5)

4

RL = 2 kQ

Notes

(4)

ns

140

( 1)
(3)

ns

95

I

Terminal

ns

40

40

Wiring Capacitance at
REXT/CEXT

65

130

External Capacitance

C W1RE

45

40

External Timing Resistance

CEXT

C L = 50 pF

I A or B Inputs High
A or 8 Inputs Low

MAX

30

CEXT = 1000 pF

I Clear Low
REXT

C EXT = 0

TYP

en
en

REXT = 5 k[1

RL = 4 kQ

RL = 400Q
tw

a

CONDITIONS

MIN

UNITS

33

GEXT =

MIN

LS122, LS123

D

Q

A or B

CONDITIONS

DM54LS/74LS

22

RL = 400Q

Clear
tpLH

MIN

R ExT = 5 kQ

Propagation Delay Time,

tpHl

~

atV cc =5V,T A =25°C

= 5V, TA == 25°C.

a,

to,)

:..
N

to,)

:t>
0

C

Q)

LS122, LS123 To Be Announced In 1976

0

::l

CD

en

:r

...
0

1/1

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted).

PARAMETER

CONDITIONS
MIN

V'H

High Level Input Voltage

V'L

Low Level Input Voltage

VI

10H

VOH

I nput Clamp Voltage'

Vee: Min

Vee: Min, V ,H

High Level Output Voltage

0;::

~

2V

Max, IOH = Max

Low Level Output Current

Low Level Output Voltage

o

IIH

III

los

Icc

Vee

~

Min

V ,H

:

2V

V jL

:=

Max

IOL :::.:

Max

IOL ~4n:A

Off-State (High Impedance State)
Output Current

II

Input Current at Maximum Input Voltage

High Level I nput Current

Low Level I nput Current

Short Circuit Output Current

Supply Current

125,126

LS125, LS126

S134

TYP(1)

MAX

MIN

TYP(1?

V'L : O.7V
~

V ,H

~

Vee

Max
V'L : O.8V

~

Max

Vee: Max

Vee: Max

Vee

~

Max(2)

Vee: Max

V,

~

t/)
t/)

MAX
V

0.8

0.7

N/A

DM74

0.8

0.8

0.8

-1.5

-1.2

V

-1.5

DM54

-2.0

-1.0

N/A

DM74

-5.2

-2.6

-6.5

DM54

2.4

3.3

2.4

3.4

DM74

2.4

3.1

2.4

3.1

V

16

8

16

16

20

DM54

0.4

0.4

N1A

DM74

0.4

0.5

0.5

Va

~

mA

3.2

DM74

DM74

V

N/A
2.4

DM54

N/A

rnA

C

V

Va

~

0.5V

Va

~

2.4V

C

s:

20
-40

/1A
-50

40

5.5V

1

(J1

~

N

1

rnA

0.1

V,: 2AV

40

V, : 2.7V

20

V,: O.4V

-1.6

/1A

50

-0.4

mA

-2
-30

-70

-30

-130

DM74

-28

-70

-30

-130
See Table

en

en
->
W

~

~

V,: 0.5V
DM54

...
~
N

50

V, : 7.0V

(J1

........

-20

2.7V

s:
~

0.4

Notes
111 All typical values are at Vee = 5V, T A = 25°C.
.121 Not more than one output should be shorted at a time, and for DM54LS/OM74LS and DM74S, duration of short circuit should not exceed one second.
131 Data for DM54LS/74LS125, 126 is preliminary.
LS125, .LS126 To Be Announced In 1976

TYP(1)

UNITS

DM54

Vo~O.4V

2V

MIN

~

2

Vo~O.4V

Vee

MAX

2

1,:-12rnA

High Level Output Current

00
10iOFF)

DM74S

I, :-18rnA

,
VOL

DM54 LS/74 LS

2

V lL

IOL

DM54174

N/A
-40

:::0

,

en
rnA

-100

i

~

~
m
IXJ

t:
.....
.....
CD

...

C/I

Supply Currents

~

CONDITIONS
DEVICE

I

OUTPUT

INPUTS

CONTROLS

OV

125

(J)

Icc (rnA)

DATA

MIN

TYP(1)

MAX

4.5V

32

54

1W

W

W

~

~

LS125

OV

4.5V

11

18

LS126

OV

OV

12

21

S134

OV

OV

7

13

5V

OV

9

16

5V

5V

14

25

Switching Characteristics at

Vee ~ 5V,

TA

~

~ 25°C
DM54/74

Co I

PARAMETER

CONDITIONS

125
MIN

tpLH

I

tpHL

I

Propagation Delay Time,
Low-la-High Level Oulput
Propagation Delay Time.
High-to-Low Level Output

----------1
tZH

I

Output Enable Time
to High Level

C ~ 50 pF
L
RL ~ 400[2
RL

~ 2 krl

(LS)

I.

DM54LS/74LS
126

TVP

MAX

10

12

MIN

LS125

TYP

MAX

15

10

18

12

MIN

TVP

MAX

15

10

18

12

MIN

CONDITIONS

TVP

MAX

15

10

15

18

12

18

I

Output Enable Time
to Low Level
Output Disable Time

tHZ

tLZ

I

U1
~

TVP

MAX

C ~ 15 pF. R ~ 280[2
CL ~ 50 pF, RL ~ 280[2

4
5.5

6
9

ns

CL ~ 15 pF. RL ~ 280[2
CL - 50 pF. RL ~ 280[2

5
7

7.5
11

ns

.......

o

3:
...,
~
.....
N

181
_

13

191
_

12

181
_

13

I

191
.

25

16

25

10

16

16

25

16

~

50 pF, RL

~

13

19.5 I

ns

N

0)

280[2

I

25

:.

14

21

I

ns

en.....

w
~

~

----------1
Output Disable Time

RL ~ 2 krl (LS)

From Low Level

3:

U1

12

16

CL 5 pF
RL ~ 400[2

From High Level

I UNITS

S134
MIN

CL
tZL

o

DM74S
LS126

I

5
9

8
14

I

14

20

1

5
9

8
14

I

10
14

16
20

I

5.5

8_5

9

14

I

ns

CL ~ 5 pF. RL ~ 280[2
ns

-I
::JJ

in

-I

~

m

OJ

s::
....

....

CD

iil

Electrical Characteristics

CONDITIONS

PARAMETER

MIN

60

'"

~

over recommended operating free-air temperature range (unless otherwise notedL

DM74S
S135
TYP(1)

UNITS
MAX

VIH

High Level Input Voltage

2

VIL

Low Level Input Voltage

VI

Input Clamp Voltage

IOH

High Level Output Current

VOH

High Level Output Voltage

IOL

Low Level Output Current

VOL

Low Level Output Voltage

Vee ~ Min, V'H ~ 2V,V'L ~ O_BV, IOL ~ 20 mA

II

Input Current at Maximum Input Voltage

Vee

~

Max,V,

~

5.5V

1

mA

IIH

High Level Input Current

Vee

~

Max, V,

~

2.7V

50

IlA

IlL

Low Level I nput Current

Vee

~

Max, V,

~

0.5V

lOS

Short Circuit Output Current

Vee

~

Max(2)

Icc

Supply Current

Vee ~ Max(3)

Vee

~

Min, I,

~

0_8

V

-1-2

V

-1
2.7

3.4

-40
65

mA
V

20

mA

0.5

V

-2

mA

-100

mA

99

mA

C

3:
~

...

en

Notes

Vee =

(1)

All typical values are at

(2)

Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.
ICC is measured with the inputs grounded and the outputs open.

(3)

-

V

-18 mA

Vee ~ Min, V'H ~ 2V, V'L ~ O.BV, IOH ~ -1 mA

en
en

5V, T A

:=

W

25° C.

U'I

m
X

n
rC

en

<:
m

0

::D

Z

0

::D

C>
.~
CD

1/1

- - --

.

- - - - - - _ .. -

--- - - - - - - - - -

"----

Switching Characteristics at Vee

~

= 5V, TA = 25°C

..

DM74S
FROM (INPUT)

PARAMETER(4)

CONDITIONS

S135
MIN

tpLH

Propagation Delay Time, Low-to-High Level Output

tpHL

Propagation Delay Time, High-ta-Low Level Output

tpLH

Propagation Delay Time, Low-to-High Level Output

tpHL

Propagation Delay Time, High-te-Low Level Output

tpLH

Propagation Delay Time, Low-te-High Level Output

tPHL

Propagation Delay Time, High-to-Low Level Output
Propagation Delay Time, Low-to-High Level Output

tpHL

Propagation Delay Time, High-te-Low Level Output

tpLH

Propagation Delay Time, Low-te-High Level Output

tpHL

Propagation Delay Time, High-to-Low Level Output

tpLH

Propagation Delay Time, Low-te-High Level Output

tpHL

Propagation Delay Time, High-te-Low Level Output

TYP

MAX

Aar B

B or A" L, C" L

8.5
11

13
15

ns

Aar B

B or A" H, C" L

8
9

12
13.5

ns

A or B

B or A" L, C" H

10
6.5

15
10

ns

8.5
7

12
11

ns

8
9.5

14.5

CL
tpLH

UNITS

A or B

B or A" H, C" H

C

A"B

C

A*B

"

15 pF,

RL

en
en

"280£2

7.5
8

12

11.5
12

ns

ns

00
w

C

3:
-..I

.

~

en

-'

W

(11

m

X

C")

r

C

en

<:m

0

:XI
I

Z

0

:XI
G)
II)

SIII

Electrical Characteristics

CONDITIONS

PARAMETER

MIN
VIH

High Level I nput Voltage

VIL

Low Level Input Voltage

VI

Input Clamp Voltage·

IOH

High Level Output Current

VOH

High Level Output Voltage

IOL

Low Level Output Current

Low Level Output Voltage

...00
II

Input Current at Maximum Input Voltage

IIH

High Level I nput Current

IlL

Low Level Input Current

Icc

Supply Current

DM54LS/74LS

DM74S

LS136,LS266

S136

TYP(11

MAX

2

Vee
Vee
V ,L

VOL

~

over recommended operating free-air temperature range (unless otherwise noted!.

~
~
~

Min, I,

~-18

Min, V ,H

Vee

~

Min

V ,H

~

2V

V ,L

~

Max

4 mA

~

Max

0.8

-1.5

-1.2

5.5

5.5

4

N/A

DM74

8

20

DM54

0.25

0.4

N/A

DM74

0.35

0.5

0.5

DM74

s:

V

.......

U'I

5.5V

V,

~

7V

0.2

2.7V

40

V,~O.4V

-0.6

~

~

Notes
(11 All typical values are at Vee ~ 5V, T A~ 25"C.
(21 Icc is measured with one input of each gate at 4.5V, the other inputs grounded, and

s:
"-I

....W
,...Ol

V
mA

V

50

-2
LS136

6.1

10

8

13

0

::s

1

Others

en

N
Ol
Ol
'C
CD

0.5V

Vee ~ Max(2)

I1A

0.4

~

V,

250

DM54

V,

~

0

V

.~

~

Vee

N/A

0.8

100

IOL

Max, V,

0.7

DM74

5.5V

Max

~

V

DM54

2V

~

~

Vee

MAX

2

mA

IOL

Vee ~ Max

TYP(1)

en
en

0

~

Max, V OH

MIN

UNITS

50

75

mA
/lA
mA

mA

(")

0

i(')
g

.

m
X
(")
r-

C

en

<:m

th~

outputs open.

0

::c

Z

0

::c

C)
I»
CD

,..
rJl

Switching Characteristics at Vee = 5V, T A = 25°C

PARAMETER

FROM
(INPUT)

~
CONDITIONS
MIN

tpLH

I Propagation Delay Time,
Low-to-High Level Output

tPHL

I Propagation Delay Time,

Aor B

Other Input Low

I

tpLH

I Propagation Delay Time,
Low-to-High Level Output

tpHL

I Propagation Delay Time,
High-to-Low Level Output

AorB

Other Input High

I

DM74S

LS136,LS266

S136

CJ)
CJ)

TYP

MAX

18

30

8

12.5

18

30

7.5

12

ns

1(11

18

30

8

12.5

ns

0
13:

18

30

7.5

12

ns

MIN

TYP

UNITS
MAX
I

ns

·0

3:

= 15 pF
RL = 2 kQ (54LS/74LS)
RL = 280Q (74S)

CL

High-to-Low Level Output

DM54LS/74LS

,J:Io

"
"...
,J:Io

I~
i-

CJ)

N

0)
0)

60

(Jl

0

'tI
CI)

:J
(1

!2.
CD

(')

g
....

m
X
(1
rC

CJ)

<:
m
0

:::c
Z
0
:::c
C')

...

II)
CI)

C/l

Electrical Characteristics

PARAMETER

CONDITIONS

DM54/74

DM54 LS/74 LS

365,366,367,368

LS365,LS366
LS367, LS368

MIN
VIH

High Level Input Voltage

VIL

Low Level Input Voltage

VI

IOH

VOH

IOL

00
a>

VOL

TYP(1)

MAX

2

Input Clamp Voltage

DM54

0.8

0.7

0.8

0.8

-1.5
-1.5
DM54

-2.0

-1.0

DM74

-5.2

-2.6

DM54

2.4

3.1

2.4

3.4

V IL = Max, IOH = Max

DM74

2.4

3.1

2.4

3.1

DM74

32

16

IOL = 16 mA, DM74
IOL = 32 mA

Vee = Max
V IH = 2V

0.5

IIH

IlL

High Level I nput Current

Vo = 0.4V

-40

Vo = 2.4V

40

Low Level Input Current

A Input

Short Circuit Output Current

ICC

Supply Current

VI = 2.7V

20

Vee = Max

-40

-20

-1.6

-0.4

-1.6

-0.4

-115

-40

Vee = Max(2)

3:
~

W
Ol
C1I

W
Ol
.....

mA

Ol
CO

-t

:JJ

,

40

VI", 0.4V

G Input

los

0.1

Vee = Max VI = 0.4V, Both G Inputs at O.4V

........

W

20

VI = 0.5V, Both G Inputs at 2V

3:
.j:I.

W
I1A

1

VI = 2.4V

C

Ol
Ol

-20

VI = 7.0V

Vee = Max

V

0.4

VI = 5.5V

Vee = Max

mA

0.4

Vo = 2.7V
Input Current at Maximum Input Voltage

mA

C
8

V IL = Max

V

C1I

32

V IH = 2V

V

V

DM54

IOL =8mA

-

MAX

DM74

Vee = Min

en
en

V

Vee = Min, V IH = 2V

Low Level Output Current

Low Level Output Voltage

TYP(1)

11=-18mA

High Level Output Current

High Level Output Voltage

MIN

UNITS

2

II =-12 mA

Vee = Min

IOIOFF) Off-State (High Impedance State) Output Current

II

~

over recommended operating free-air temperature range (unless otherwise noted).

-30

-130

365, LS365,367, LS367

65

85

22

28

366, LS366, 368, LS368

59

77

20

26

I1A
I1A
mA
rnA

~

~

m
J:

~

OJ

C

rnA

::t

...

(I)

(I)

-_ ... _--_ .. _

...

_-----

at Vee ~ 5V, T A ~ 25°C

Switching Characteristics

DM54/74
PARAMETER

tPLH

CONDITIONS

Propagation Delay Time, Low-to-High Level Output

tpHL

Propagation Delay Time, High-to-Low Level Output

tZH

Output Enable Time to High Level

tZL

Output Enable Ti me to Low Level

tHZ

Output Disable Time From High Level

CL

C,Output Disable Time From Low Level

tLZ

Notes
111 All typical values are at Vee

121
131

= 50 pF,

= 5 pF,

RL

RL

= 400D.

= 400D.

365,367

366,368

TYP

MAX

TYP

MAX

10

16

11

17

14

22

10

16

21

35

21

35

24

37

24

6

11

6

CONDITIONS

27

16

LS365, LS367
TYP

MAX
16

LS366, LS368
TYP

UNITS

17

ns

16

ns

35

35

ns

37

37

37

ns

11

11

11

ns

27

27

ns

27

=

~

15 pF,

5pF,

RL

RL

= 2 kD.

en
en

MAX

22
CL

CL
16

~

DM54LS/74LS

= 2kD.

C

3:
(J1
=

5V, T A = 25° C.

Not more than one output should be

shor~ed

~

.......

at a time, and duration of short circuit should not exceed one second.

C

Data for DM54LS/74LS is preliminary.

3:
-..J

LS365, LS366, LS367, LS368 To Be Announced In 1976

~
to)
0')

Co
-..j

(J1

W
0')
0')

W
0')
-..J

W
0')
00

-I

::D

in

-I

~
m

::I:

CD

><

OJ
I:

...

CD

1/1

----

-------

National5emiconductor
54;/74 MSI DEVICES

Section 2

~ 54/74 MSI

Max Ratings/Operating Conditions

RATINGS
Maximum Allowable
Supply Voltage
Guaranteed Operating
Supply Voltage Range

54/74

54H/74H

SERIES

SERIES

7

54L/74L 54LS/74LS SERIES 54S/745
DIODE EMITTER'
SERIES
SERIES
INPUTS INPUTS

8

7

7

7

7

4.50 to 5.50
4.75 to 5.25

154

UNITS

V
V

Maximum Input Voltage

5.5

5.5

5.5

7

5.5

5.5

V

Maximum Voltage to Open·
Collector Outputs*

7

7

8

7

7

7

V

Operating Free-Air
Temperature Range

-55 to +125

p4

o to+70

Storage Temperature Range

-65 to +150

* Except for selected high voltage types, as specified in electrical tables.

2-ii .

~

54/74 MSI

Table of Contents

DM5441 A/DM7441 A
DM5442/DM7442
DM54 L42A/DM 74 L42A
DM54LS42/DM74LS42
DM5445/DM7445
DM5446A/DM7446A
DM5447A/DM7447A
DM54LS47/DM74LS47
DM5448/DM7448
DM54LS48/DM74LS48
DM54LS49/DM74 LS49
DM54 75/DM74 75
DM54L75A/DM74L75A
DM54LS75/DM74LS75
DM54LSn/DM74LSn
DM5483/DM7483
DM54LS83A/DM74LS83A
DM5485/DM7485
DM54L85/DM74L85
DM54LS85/DM74LS85
DM5488/DM7488
DM5489/DM7489
DM54L89A/DM74L89A
DM5490A/DM7490A
DM54L90/DM74L90
DM54LS90/DM74LS90
DM5491 A/DM7491 A
DM54L91/DM74L91
DM5492A/DM7492A
DM54LS92IDM74LS92
DM5493A/DM7493A
DM54L93/DM74L93
DM54LS93/DM74LS93
DM5495/DM7495
DM54L95/DM74L95
OM 54 LS95BIDM74 LS95B
DM5496/DM7496
DM54LS96/DM74LS96
DM54L98/DM74L98
DM54LS124/DM74LS124
DM54LS138/DM74LS138
DM74S138
DM54LS139IDM74LS139
DM74S139
DM54141/DM74141
DM54145/DM74145
DM54147/DM74147
DM54148/DM74148
DM54150/DM74150
DM54151A/DM74151A
DM54LS151IDM74LS151
DM74S151
DM54153JDM74153
DM54LS153/DM74LS153

Page
No.

Description

Device No.

BCD/Decimal
BCD/Decimal
BCD/Decimal
BCD/Decimal
BCD/Decimal

DecoderslDrivers
Decoders
Decoders
Decoders
Decoders/Drivers
BCDI7~Segment Decoders/Drivers
BCDI7~Segment Decoders/Drivers
BCDI7~Segment Decoders/Drivers
BCDI7~Segment Decoders/Drivers
BCDI7 ~Segment Decoders/Drivers
BCDI7 ~Segment Decoders/Drivers
Quad Latches
Quad Latches
Quad Latches
Quad Latches
4~Bit Binary Adders with Fast Carry
4~Bit Binary Adders with Fast Carry
4~Bit Magnitude Comparators
4~Bit Magnitude Comparators
4~Bit Magnitude Comparators
256~Bit Read Only Memories
64~Bit Read/Write Memories
64~8it Read/Write Memories
Decade, Divide by 12, and Binary Counters
Decade, Divide by 12, and Binary Counters
Decade, Divide by 12, and Binary Counters
8~Bit Serial Shift Registers
8~Bit Serial Shift Registers
Decade, Divide by 12, and Binary Counters
Decade. Divide by 12, and Binary Counters
Decade, Divide by 12, and 8inary Counters
Decade, Divide by 12, and Binary Counters
Decade, Divide by 12, and Binary Counters
4~Bit Parallel Access Shift Registers
4~Bit Parallel Access Shift Registers
4~Bit Parallel Access Shift Registers
5~Bit Shift Registers
5~Bit Shift Registers
4~Bit Storage Registers
Dual Voltage Controlled Oscillators
Decoders/Demu Iti plexers
Decoders/Demultiplexers
Decoders/Demu Iti p!ex ers
Decoders/Demu Iti plexers
BCD/Decimal Decoders/Drivers
8CD/Decimal Decoders/Drivers
Priority Encoders
Priority Encoders
Data Selectors/Multiplexers
Data Selectors/Multiplexers
Data Selectors/Multiplexers
Data Selectors/Multiplexers
Dual 4~Line to 1 ~Line Data Selectors/
Multiplexers
Dual 4-Line to 1 ~Line Data Selectors/
Multiplexers

2-iii

2·1
2·3
2~3

2~3
2~6
2~8
2~8

2~8
2~8

2~8
2~8

2~ 14
2~ 14
2~ 14
2~14

2~ 17
2~ 17

2~21
2~21
2~21
2~25

2~28
2~28
2~30

2~30
2~30
2~34

2~34
2~30
2~30
2~30

2~30
2~30

2~36
2~36
2~36

2-39
2-39
2-42
2~44

2-46
2~46

2-46
2~46

2-1
2~6

2-49
2-49
2~53
2~53

2~53
2~53
2~57

2~57

J
Mil

•
•

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•

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•

Coml

Package
N
Mil
Coml

•

•
•

•
•
•
•
•
•
•
•
•
•
•
•
•
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•
•
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•
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•

•
•
•
•
•
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
N/A
• •
N/A
• •
• •
• •
• •
• •
• •
• •
N/A
•
• •

.,

•
•
•
•
•
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•
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•

•
•
•
•
•

•
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•
•
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•
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•
•
•

•
•

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•

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•

•
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•
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•
•
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•

•
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W
Mil

Coml

•

•

•

•
•
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•
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•
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•
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•

•
•
•
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•
•
•

N/A

·••
'

•

•

•
•
•
•
•
•

•
•
•
•
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
N/A
• •
N/A
• •
• •
• •
• •
• •
• •
• N/A •
• •
• •

~~ 54/74

MSI

Device No.

DM74S153
DM54154/DM74154
DM54L 154A/DM74L 154A
DM54LS154/DM74LS154
DM54155/DM74155
DM54LS155/DM74LS155
DM54156/DM74156
DM54LS156/DM74LS156
DM54157/DM74157
DM54L157A/DM74L 157 A
DM54 LS157 /DM74LS157
DM74S157
DM54LS158/DM74LS158
DM74S158
DM54160A/DM74160A
DM54LS160/DM74LS160
DM54161 A/DM74161A
DM54LS161/DM74LS161
DM54162A/DM74162A
DM54l,.S162/DM74LS162
DM54163A/DM74163A
DM54LS163/DM74 LS163
DM54164/DM74164
DM54L 164A/DM74L 164A
DM54LS164/DM74LS164
DM54165/DM74165
DM54L 165A/DM74L 16,5A
DM54166/DM74166
DM54LS168/DM74LS168
DM54LS169/DM74LS169
DM74170
DM54LS170/DM74LS170
DM54173/DM74173
DM54LS173/DM74LS173
DM54174/DM74174
DM54LS174/DM74LS174
DM74S174
DM54175/DM74175
DM54LS175/DM74LS175
DM74S175
DM54176/DM74176
DM54177 /DM74177
DM54180/DM74180
DM54181/DM74181
DM54182/DM74182

Table of Contents
Package

Page

Description

'No.

Dual 4-Line to 1-Line Data Selectors/
Multiplexers
4-Line to 16-Line Decoders/Demultiplexers
4-Line to 16-Line Decoders/Demultiplexers
4-Line to 16-Line Decoders/Demultiplexers
Dual 2-Line to 4-Line Decoders/
Demultiplexers
Dual 2-Line to 4-Line Decoders/
Demultiplexers
Dual 2-Line to 4-Line Decoders/
Demultiplexers
Dual 2-Line to 4-Line Decoders/
Demultiplexers
Quad 2-Line to 1-Line Data Selectors/
Multiplexers
Quad 2-Line to 1 Line Data Selectors/
Multiplexers
Quad 2-Line to 1 Line Data Selectors/
Multiplexers
Quad 2-Line to 1-Line Data Selectors/
Multiplexers
Quad 2-Line to 1-Line Data Selectors/
Multiplexers
Quad 2-Line to 1-Line Data Selectors/
Multiplexers
Synchronous 4-Bit Counters
Synchronous 4-Bit Counters
Synchronous 4-Bit Counters
Synchronous 4-Bit Counters
Synchronous 4-Bit Counters
Synchronous 4-Bit Counters
Synchronous 4-Bit Counters
Synchronous 4-Bit Counters
8-Bit Serial In/Parallel Out Shift Registers
8-Bit Serial In/Parallel Out Shift Registers
8-Bit Serial In/Parallel Out Shift Registers
8-Bit Parallel In/Ser;al Out Shift Registers
8-Bit Parallel In/Serial Out Shift Registers
8-Bit Parallel In/Serial Out Shift Registers
Synchronous 4-Bit Up/Down Counters
Synchronous 4-Bit Up/Down Counters
4 by 4 Register Files
4 by 4 Register Files
TRI-STATE Quad 0 Registers
TRI-STATE Quad 0 Registers
Hex/Quad 0 Flip-Flops with Clear
He~/Quad 0 Flip-Flops with Clear
Hex/Quad 0 Flip-Flops with Clear
Hex/Quad 0 Flip-Flops with Clear
Hex/Quad 0 Flip-Flops with Clear
Hex/Quad 0 Flip-Flops with Clear
Presettable Decade and Binary Counters
Presettable Decade and Binary Counters
9-Bit Parity Generators/Checkers
Arithmetic Logic Unit/Function Generators
Look-Ahead Carry Generators

2-iv

J
Mil

2-60
2-60
2-60
2-63
2-63
2-63
2-63
2-66
2-66
2-66

•
•
•
•
•
•
•

•

•

2-70
2-70
2-70
2-70
2-70
2-70
2-70
2-76
2-76
2:76
2-79
2-79
2-82
2-85
2-85
2-91
2-91
2-96
2-96
2-98
2-98
2-98
2-98
2-98
2-98
2-101
2-101
2-105
2-107
2-113

,.

•
•
•
•
•
•

N/A

2-66
2-70

•

•

•

•

N/A

•

•
•
•
•
•
•

•
•
•
•
•
•
•
•

..

•
•
•
•
•
•
•
•
•
•

•

•
•
•
•
N/A
•
•

•
•
•
•
•

N/A

Coml

Mil

•

•
•
•
•
•
•
•
•
•

2-66
2-66

Mil

N/A

2-57 -

W

N
Coml

•
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•

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Com I
N/A

(F)
(F)

(F)

(F)
(F)
(F)

•
•

•
•
•
•
•

•

•
•
•
•

•
•
N/A

•

•
N/A

•

•

•
•
•

•
•

•
• •
• •
• •
• •
• •
• •
• •
• •
• N/A •
• •
•

N/A

•

•

•
•
•
• •
• •
N/A
• •
• •
•
•

N/A
N/A
N/A

•

N/A
N/A

•

~

54/74 MSI
Device No.

DM74S182
DM54184/DM74184
DM54185A/DM74185A
DM54187/DM74187
DM54L 187A/DM74L 187 A
DM54S189/DM74S189
DM54190/OM74190
DM54LS190/DM74LS190
DM54191/OM74191
DM54LS191/DM74LS191
DM54192/OM74192
DM54L 192/DM74L 192
DM54LS192/DM74LS192
DM54193/DM74193
DM54L 193/DM74L 193
DM54LS193/OM74LS193
DM54194/DM74194
DM54LS194A/DM74LS194A
DM74S194
DM54195/DM74195
DM54LS195A/DM74LS195A
DM74S195
DM54196/DM74196
DM54LS196/DM74LS196
DM54197/DM74197
DM54LS197/DM74LS197
DM54198/DM74198
DM54199/DM74199
DM54S200/DM74S200
DM54S206/DM74S206
DM54251/DM74251
DM54LS251/DM74LS251
DM74S251
DM54LS253/DM74LS253
DIIII74S253
DM54 LS257 /OM74LS257
DM74S257
DM54LS258/DM74LS258
DM74S258
DM54LS279/DM74LS279
DM74S280

Table of Contents
Page
No.

Description
Look-Ahead Carry Generators
BCD-to-Binary and Binary-to-BCD Converters
BCD-to-Binary and Binary-to-BCD Converters
1024-Bit Read Only Memories
1024-Bit Read Only Memories
TRI-STATE 64-Bit Read/Write Memories
Synchronous Up/Down Counters with
Mode Control
Synchronous Up/Down Counters with
Mode Control
Synchronous Up/Down Counters with
Mode Control
Synchronous Up/Down Counters with
Mode Control
Synchronous Up/Down Counters with
Dual Clock
Synchronous Up/Down Counters with
Dual Clock
Synchronous Up/Down Counters with
Dual Clock
Synchronous Up/Down Counters with
Dual Clock
Synchronous Up/Down Counters with
Dual Clock
Synchronous Up/Down Counters with
Dual Clock
4-Bit Bidirectional Universal Shift Registers
4-Bit Bidirectional Universal Shift Registers
4-Bit Bidirectional Universal Shift Registers
4-Bit Parallel Access Shift Registers
4-Bit Parallel Access Shift Registers
4-Bit Parallel Access Shift Registers
Presettable Decade and Binary Counters
Presettable Decade and Binary Counters
Presettable Decade and Binary Counters
Presettable Decade ahd Binary Counters
8-Bit Shift Registers
8-Bit Shift Registers
TRI-STATE 256-Bit Read/Write Memories
256-Bit Read/Write Memories with OpenCollector Outputs
TR I-ST ATE Data Selectors/Multiplexers
TR I-STATE Data Selectors/Multiplexers
TR I-STATE Data Selectors/Multiplexers
TR I-STATE Data Selectors/Multiplexers
TR I-STATE Data Selectors/Multiplexers
TR I-ST ATE Quad 2-Data Selectors/
Multiplexers
TR I-STATE Quad 2-Data Selectors/
Multiplexers
TRI-STATE Quad 2-Data Selectors/
Multiplexers
T R I-STATE Quad 2-Data Selectors/
Multiplexers
Quad S-R Latches
9-Bit Parity Generators/Checkers

2-v

2-113
2-116
2-116
2-122
2-122
2-125
2-128

J
Mil

Coml

Package
N
Mil
Coml

•

N/A

•
•
•
•
•
•
•
•
•
•
•
•
•

•

•

•

•
•
•
•

2-133

•

2-133

•
•

•
•
•

•
•

•
•
•
•
•

•
•
•
•

2-128
2-128
2-128
2-133
2-133
2-133
2-133

2-140
2-140
2-140
2144
2-144
2-144
2-101
2-101
2-101
2-101
2-148
2-148
2-154
2-157
2-160
2-160
2160
2-163
2-163
2-165

•
•

•

•

•

•
•

•
•

•

•
N/A
•
•
•
•
•
•
•
•
•
•
N/A
•
N/A
•

•
•
•
•
•
•

•

•
•

•
•

•

•

•

•

N/A

•

•

2-165
2-168
2-170

•

•
•
•
•

• N/A •
• •

2-165
2-165

•
•
•
•

•

N/A

•

N/A

•

•

W
Mil

Coml
N/A

•

•

•

•

N/A

•

•

•
•
•

•
•
•
•

•

•

•
•
•
•

•
•
•
•
•

•
•
•
•
•

•
•
•
•
•

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

•

•
•

•
N/A

•

•
•

•
• •
• •
• •
N/A
• •
• •
N/A
N/A

•
N/A

•

•
•

N/A
N/A

•

•
• •
• •
• •
N/A
• •
N/A
• •
N/A

•

•
N/A

•

N/A

•

~ 54n4

Table of Contents

MS1

Device No.

OM74S281
OM 54 LS283/0M 74 LS283
OM54S287/0M74S287
OM54S289/0M74S289
OM 54 LS295A/OM 74 LS295A

OM54 LS298/0M 74 LS298
OM54LS3}4/0M74LS374
OM54S387/0M74S387
OM 54 LS395/0M74 LS395
OM54LS670/0M74LS670

Page
No.

Description

4-Bit Parallel Binary Accumulators
4-Bit Binary Adders with Fast Carry
TRI-STATE 1024-8it Programmable Read
Only Memories
64-Bit Read/Write Memories with OpenCollector Outputs
TR I-STATE 4-Bit Parallel Access Shift
Registers
Quad 2-Multiplexers with Storage
TRI-STATE Octal 0 Flip-Flops
1024-Bit Programmable Read Only Memories
TRI-STATE 4-Bit Cascadable Shift Registers
TR I-STATE 4 by 4 Register Files

2-vi

2-173
2-17
2-177
2-179
2-182
2-184
2-187
2-177
2-189
2-191

Package

J
Mil

Mil

N/A

•

N/A

•
•
•
•
N/A
•

•

W

N
Coml

•

•

•

•

•

•

•
•

•

•
•

•
•

Coml

•

•
•
•
•
•
•
•
•
•

Mil

Com I
N/A

• N/A •
N/A

•
•
•

•
•

•
•

N/A

•
•
•

~ MSI

DM54/DM7441A.141
BCD/Decimal Decoders/Drivers

General Description
The DM5441A/DM7441A is a BCD-to-decimal decoder
designed to drive gas-filled NI XI E tubes. The device is
also capable of driving other types of low·current lamps
and relays.

a minimum of external circuitry, can use these invalid
codes in blanking leading· and/or trailing-edge zeros in a
display.

An over-range decoding feature provides that if binary
numbers between 10 and 15 are applied to the input,
the least significant bit (0-5) will be decoded on the
output.

voltage transitions in order to minimize transmission-line

Input clamp diodes are also provided to clamp negative·
effects.

Features
•
•
•

The DM54141/DM74141 is a BCD-to·decimal decoder
designed specifically to drive cold-cathode indicator
tubes.
Full decoding is provided for all possible input states.
For binary inputs 10 through 15, all the outputs are
off. Therefore the DM54141/DM74141, combined with

Connection Diagram

.

•

OUTPUTS

o

Drive cold'cathode, numeric indicator tubes directly
Fully decoded inputs
Low leakage current
1.aIlA@50V
DM54/7441A
50llA @55V
DM54/74141
Low power dissipation
DM54/7441A
105 mW typical
55 mW typical
DM54/74141

,

OUTPUTS

13

10

4

15

16

14

p-

o-

1

3

Z

,

9

A

,

4

~

~

OUTPUTS

INPUTS

7

B

0

C

~
INPUTS

Z
OUTPUT

5441A(JI, (WI; 7441A(JI, (NI, (WI;
54141(JI, (WI; 74141(JI, (NI, (WI

Truth Tables
5441 A/7441 A
INPUT

54141/74141
OUTPUT

A

ow

L

L

L

H

L

H

L

L

L

H

H

3

L

H

L

L

4

D

C

B

L

L

L

L

L

INPUT
A

OUTPUT
ON"

L

L

0

L

H

1

L

H

L

2

L

L

H

H

3

L

H

L

L

4

D

C

B

0

L

L

1

L

L

2

L

L

H

L

H

5

L

H

L

H

5

L

H

H

L

6

L

H

H

L

6

L

H

H

H

7

L

H

H

H

7

H

L

L

L

8

H

L

L

L

8

H

L

L

H

9

H

L

L

H

9

lOVER RANGEl

lOVER RANGEl

H

L

H

L

0

H

L

H

L

NONE

H

L

H

H

1

H

L

H

H

NONE

H

H

L

L

2

H

H

L

L

NONE

H

H

L

H

3

H

H

L

H

NONE

H

H

H

L

4

H

H

H

L

NONE

H

H

H

H

5

H

H

H

H

NONE

H = High Level, L == Low Level

* All other outputs are off

2-1

~ MSI

DM54/DM7441A,141

Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted)
DM54/74
PARAMETER

CONDITIONS

41A
MIN

V,H

High Level Input Voltage

V,L

low Level Input Voltage

V,

Input Clamp Voltage

VOL

On-State Output Voltage

MIN

TYP(1)

Vee'" Min, II ;;:: -12 rnA

Vee

0::

Max

V o -: 50V

V

N/A

Off-State Reverse Current
for Input Counts 10-15

VOH

Off-State Output Voltage

I,

Input Current at Maximum
Input Voltage

I'H

High Level I nput Current

I,L

Low Leve! I nput Current

. Icc

Supply Current

Vee"" Max, Vo = 30V

Vee = Max

125"c

3.0

3.0

60
40

55°C, oOe, 25"e

=

50
TA : 55°e

N/A

TA _70 o e

N/A

10: 0.5 mA

Vee: Max, V, : O.4V

5
15
60

10 - 1.0 mA

Max, VI '" 2.4V

V

IJ.A

1.8

A Input

3

8, C, or 0 Input

3
~1.0

A Input

B, C, or 0 Input

Vee: Max(2)

1

1.0

40

40

~1.6

21

36

Notes
(1)

All typical values are at Vee: 5V, TA: 25°C.

(2)

ICC is measured with all inputs grounded and outputs open.

Logic Diagrams
5441A17441A

54141/74141

Vee - 5
GND -12

2-2

80

40
~1.6

~1.0

IJ.A

V

70

Vee;;:: Max, VI = 5.5V

Vee

V

2.5

Vo - 55V
IOH

V

~1.5

2.5

TA : 70°C
~

0.8

~55"c to +70"c

T A =125°c
TA

MAX

2
0.8

Vee =Min,f o =7mA

UNITS

141
MAX

2

Off-State Reverse Current

IOH

TYP(l)

mA

IJ.A

-

~1.6

~3.2

11

25

mA
mA

~ MSI

DM54/DM7442,L42A,LS42
BCD/Decimal Decoders

General Description
These BCD-to-decimal decoders consist of eight inverters
and ten, four-input NAND gates. The inverters are
connected in pairs to make BCD input data available for
decoding by the NAND gates. Full decoding of input
logic ensures that all outputs remain off for all invalid
(10-15) input conditions.

•
•

TYPE

Features
•

Also for application as 4-line-to-16-line decoders; 3Iine-to-8-1 ine decoders
All outputs are high for invalid input conditions
TYPICAL

TYPICAL

POWER DISSIPATION

PROPAGATION DELAY

140mW

L42A

15mW

17 ns
53 ns

LS42

35mW

17 ns

42

Diode clamped inputs

Connection Diagram

Logic Diagram
OUTPUTS

0'

I"

15

"

11

13

11

10

p-

r<

,

9

2

J

4

•

5

I'

7

GNO
OUTPUTS

5442(JI, (W); 7442(J), IN), (W);
54L42A/74L42A(J), (N), (W);
54LS42/74LS42(Jl. (N), (W)

Truth Table
42, L42A, LS42
BCD INPUT

NO.
0

C

B

A

0

1

2

3

4

5

6

7

8

9

a

L

L

L

L

L

H

H

H

H

H

H

H

H

H

1

L

L

L

H

H

L

H

H

H

H

H

H

H

H

2

L

L

H

L

H

H

L

H

H

H

H

H

H

H

3

L

L

H

H

H

H

H

L

H

H

H

H

H

H

4

L

H

L

L

H

H

H

H

L

H

H

H

H

H
H

5

L

H

L

H

H

H

H

H

H

l.

H

H

H

6

L

H

H

L

H

H

H

H

H

H

L

H

H

H

7

L

H

H

H

H

H

H

H

H

H

H

L

H

H

8

H

L

L

L

H

H

H

H

H

H

H

H

L

H

9

H

L

L

H

H

H

H

H

H

H

H

H

H

L

H

L

H

L

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

L

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H'

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

0

:::;

~

H
L

~
:=

ALL TYPES
DECIMAL OUTPUT

High Level
Low Level

2-3

Electrical Characteristics

over recommended operating free·air temperature range (unless otherwise noted)

CONDITIONS

PARAMETER

MIN
VIH
V IL

High Level Input Voltage

DM54/74

DM54L/74L

DM54LS/74LS

42

L42A

LS42

TYPO)

MAX

TYPO)

MAX

2

2

Low Level Input Voltage

MIN

MIN

TYP(1)

~
UNITS

s:

(J)

MAX
V

2

DM54

0.8

0.7

0.7

DM74

0.8

0.7

0.8

V

.
VI

Input Clamp Voltage

Vec = Min

IOH

High Level Output Current

VOH

High Level Output Voltage

-1.5

I, = -12 rnA

N/A

I, =-18mA
-800

Vee = Min
V ,H = 2V

IOH = Max

-200

VOL

N

Low Level Output Current

Low Level Output Voltage

.i>.

Vee = Min
V ,H = 2V

IOL = 4 mA
IOL = Max

V'L = Max
Input Current at Maximum Input Voltage

II

IIH

IlL

los

Icc

High Level I nput Current

Vee = Max

Vee = Max

Low Level I nput Current

Vee = Max
Short Circuit OutputCurrent

Suppiy Current

Notes:
11) All typical values are at

Vee = Max(2)

Vee = Max(3)

Vee =

-400

DM54

2.4

3.4

2.4

3.4

2.5

3.5

DM74

2.4

3.4

2.4

3.4

2.7

3.5

V'L = Max
IOL

-1.5

N/A

DM54

16

2

4

16

3.6

8
0.25

0.2

0.4

0.15

0.3

0.25

0.4

DM74

0.2

0.4

0.2

0.4

0.35

0.5

V, = 55V

0.1

1

0.1

V, =2.4V

40

10
20

V, = 2.7V
. ---0.18

V I = 0.3V for L42A

V

mA

IlA

0
mA

-1.6

V I = 0.4 V for Others

mA

0.4

DM54

V, =7V

IlA

V

DM74
DM74

V

---0.4

DM54

-20

-55

-3

-15

-30

-130

DM74

-18

-55

-3

-15

-30

-130

DM54

28

41

3.0

5.3

7

13

DM74

28

56

3.0

5.3

7

13

5V,'TA = 25°C.

(2)

Not more than one output should be shorted at a time, and for DM54LS/74LS duration of short circuit should not exceed one second.

(3)

ICC is measured with all outputs open and all inputs grounded.

s:
C1I
,J:lo

mA

........
0

rnA

,J:lo
,J:lo

s:-..I
N

~
N

'l>
r-

(J)

,J:lo

N
-- -- ---- - - - - -

Switching Characteristics vee = 5V, T A = 25°C

PARAMETER
CONDlTIONS
tpHL

~

DM54/74

DM54L{74L

DM54 LS/74 LS

42

L42A

LS42

MIN

TYP

MAX

14

25

17

30

CONDITIONS

MIN

TYP

MAX

65

130

70

140

CONDITIONS

MIN

UNITS
TYP

MAX

14

25

ns

17

30

ns

s:

en

Propagation Delay Time, High-to-Low Level
Output From A, B, C, or D Through 2
Levels of Logic

tpHL

Propagation Delay Time, High-to-Low Level
Output From A, B, C, or D Through 3
Levels of Logic

tpLH

Propagation Delay Time, Low-to-High Level
Output From A, B, C, and D Through 2

= 15 pF
RL = 400n

CL

CL
RL

= 50 pF
= 4 kn

CL
RL

= 15pF
= 2 kfl

- 10

25

30

60

10

25

ns

17

30

35

70

17

30

ns

Levels of Logic
tpLH

Propagation Delay Time, Low-to-High Level
Output From A, B, C, and D Through 3
Levels of Logic

'"


en
~

N

~ MSI

DM54/DM7445,145

BCD/Decimal Decoders/Drivers
General Description
These BCD-to-decimal decoders/drivers consist of eight
inverters and ten, four-input NAND gates. The inverters
are connected in pairs to make BCD input data available
for decoding by the NAND gates. Full decoding of BCD
input logic ensures that all outputs remain off for all
invalid (10-15) binary input conditions. These decoders
feature high-performance, NPN output transistors de·
signed for use as indicator/relay drivers, or as open·
collector logic-circuit drivers. The high·breakdown output

Connection Diagram

0'
14

13

'9

Full decoding of input logic
80 mA sink-current capability

•

All outputs are off for invalid BCD input conditions

7'

8

9

10

11

12

P-

r<

I

•
•

'OUTPUTS

INPUTS

15

Features

Logic Diagram

vee

1,6

transistors are compatible for interfacing with most MOS
integrated circuits.

2

3

4

7

6

5

18

GNO
OUTPUTS

5445(J), (W); 7445(J), (N), (W);
54145(J), IW); 74145(J), (N), (W)

Truth Table
INPUTS

OUTPUTS

NO.

0

C

B

A

0

1

2

3

4

5

6

7

8

9

a

L

L

L

L

L

H

H

H

H

H

H

H

H

H

1

L

L

L

H

H

L

H

H

H

H

H

H

H

H

2

L

L

H

L

H

H

L

H

H

H

H

H

H

H

3
4
5

L

L

H

H

H

H

H

L

H

H

H

H

H

H

L

H

L

H

H

H

H

L

H

H

H

H

H

L

H

L
L

H

H

H

H

H

H

L

H

H

H

H

6

L

H

H

L

H

H

H

H

H

H

L

H

H

H

7

L

H

H

H

H

H

H

H

H

H

H

L

H

H

8

H

L

L

L

H

H

H

H

H

H

H

H

L

H

9

H

L

L

H

H

H

H

H

H

H

H

H

H

L

H

L

H

L

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

L

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

0

:::;

~

H

= High

Level (Off), L

= Low Level

(On)

2-6

~

MSI

DM54/ DM7445 ,145

Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted)
DM54/74
PARAMETER

CONDITIONS
MIN

VIH

High Level Input Voltage

V IL

Low Level I nput Voltage

VI

Input Clamp Voltage

Vce

~

Min, I,

VO(ONI

On-State Output Voltage

Vee

~

Min, V ,H

Off-State Output Voltage

Vee
V'L

II

Input Current at Maximum
Input Voltage

IIH

High Level I nput Current

IlL

Low Level Input Current

Icc

Supply Current

TYP(l)

V

~ ~12

~

mA

I
I

2V

~

Min, V

~ O_SV,

,H

~

1010NI ~ SO mA

2V

1010FFI

0.5

~ 250llA

I
I

45

30

145

15

V

~1.5

V

0.9

V

V

Vee

~

Max, V,

~

5.5V

Vee

~

Max, V,

~

2AV

40

Il A

Vee

~

Max, V,

~

OAV

~1.6

mA

Vee

~

Max(2)

1

I
I

DM54

43

62

DM74

43

70

Notes
All typical values are at Vee = 5V, T A = 25°C.
(21 ICC is measured with all inputs grou'nded and outputs open.

Switching Characteristics vee ~ 5V, T A ~ 25°C
DM54/74
PARAMETER

CONDITIONS

Propagation Delay Time,
Low-to-High Level Output
Propagation Delay Time,

~

15 pF

RL ~

100n

CL

High-to-Low Level Output

2-7

UNITS

45, 145
MIN

tpHL

O.S

OA

1010NI ~ 20 mA

(11

tpLH

MAX

2

V'L ~ O.SV
VO(OFFI

UNITS

45, 145

TYP

MAX
30

ns

30

ns

mA

mA

.

~ MSI

~

DM54/DM7446A.47A,L$47.48.LS48.LS49

BCD/7-$egment Decoders/Drivers

General Description.

Features

The 46A, 47Aand LS47 feature active-low outputs
designed for driving common-anode LED's or incandescent indicators directly; and the 48, LS48 and LS49
feature active-high outputs for driving lamp buffers or
common-cathode LED's. All of the circuits except the
LS49 have full ripple-blanking input/output controls
and a lamp test input. The LS49 features a direct
blanking input. Segment identification and resultant
displays are shown on a following page. Display patterns
for BCD input counts above nine are unique symbols
to authenticate input conditions.

• All circuit types feature lamp intensity modulation
capability
5446A/7446A, 5447A/7447A, 54LS47/74LS47
• Open-collector outputs drive indicators directly
• Lamp-test provision
• Leading/trailing zero suppression
5448/7448,54LS48/74LS48
•
•
•

All of the circuits except the LS49 incorporate automatic leading and/or trailing-edge, zero-blanking control
(RBI and RBO). Lamp test (LT) of these devices may
be performed at any time when the BI/RBO node is at
a high logic level. All types (including LS49) contain
an overriding blanking input (BI) which can be used
to control the lamp intensity (by pulsing) , or to inhibit
the outputs.

Internal pull-ups eliminate need for external resistors
Lamp-test provision
Leadingltrailing zero suppression

54lS49/74LS49
• 'Open-collector outputs
• Blanking input

DRIVER OUTPUTS
TYPE

TYPICAL

ACTIVE

OUTPUT

SINK

MAX

POWER

LEVEL

CONFIGURATION

CURRENT

VOLTAGE

DISSIPATION

DM5446A

low

open-collector

40mA

30V

320mW

J. N,W

DM5447A

low

open-collector

40 mA

15V

320mW

J, N, W

DM5448

high

2-H2 pull·up

6.4 mA

5.SV

265mW

J, N,W

DM54LS47

low

open-collector

12 mA

15V

35mW

J, N, W

DM54LS48

high

2 kr! pull-up

2mA

5.5V

125mW

J, N, W

DM54LS49

high

open-collector

4mA

5.5V

40mW

J,N,W·

open·collector
open-collector

40mA

30V

320mW

J, N,W

rnA

15V

320 mW

J,N,W
J,N,W

.PACKAGES

DM7446A

low

DM7447A

low

DM7448

high

2-kr! pull-up

6.4 rnA

5.5V

265mW

DM74LS47

low

open-collector

24 mA

15V

35mW

J,N,W

DM74LS48

high

2 kr! pull-up

6mA

5.5V

125mW

J,N,W

DM74LS49

high

open-collector

SmA

5.5V

40mW

J, N,W

40

Connection Diagrams
OUTPUTS

2

7
~
INPUTS

LAMP SI/RBO RBI
TEST

~
INPUTS

5446A/7446A(J), (N), (W);
5447A/7447A(J), (N), (W);
54LS47174LS47(J), (N), (W)

GND

~
INPUTS

LAMP BI/RBO RBI
TEST

~
INPUTS

544817448(J), (N), (W);
54LS48174LS48(J), (N), (W)

2-8

GND

~

BI

INPUTS

e
OUTPUT

GND

54LS49174LS49(J), (N), (W)

LS47-.

LS~8.

LS49 To Be Announced In 1976

Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted)
DM54/74
PARAMETER

CONDITIONS

46A.47A
MIN

VIH

High Level Input Voltage

V ,L

Low Level Input Voltage

V,

Input Clamp Voltage

IOH

High Level

Output Current
VOH
IOL

BI/RBO

-

-

Vee - Min, V 1H - 2V

a thru 9

BI/RBO

'"'
o

o

~

U1
~

........

o

~

~
~

0)

l>

~

l>

r-

C/)

~

-..J

~

(X)

r-

C/)

~

(X)

i-

C/)
~

C.D

~ MSI

OM54/0M7446A.47 A.lS47.48 .lS48 .lS49

Output Display

SEGMENT
IDENTIFICATION

NUMERICAL DESIGNATIONS AND RESULTANT DISPLAYS

Truth Tables

46A. 47 A, LS47
DECIMAL
OR
FUNCTION

o

INPUTS

OUTPUTS

1--.-----,-------1 BI/RBOllll------------l
LT RBI
D
C
B
A
H

H

H

X

H

H

x
x
x
x

H

x

H

x

L

H

x

H

H

x
x
x
x
x
x

H

H

H

10

H

11

H

12

H

L

H

L

H

H

H

L

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H
H

H

H
H

l.
L

H

H
H

H

L

H

H

x

x

x

H

x

x

x

x

RBI

H

x

L

H

H
H

61

H

H

H

15

H
H

L

H
H

H

H
L

H

H

H

H

H

H

L
H

H

H

14

x

H

H

13

LT

L

H

x

x

H

x

L

H

NOTE

H
H

L

L

H

H

H

H

H

L

L

L

H

H

H

L

H

H

H

H

H

H

H

L

H

H

L

H

H

H

H

L

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H
H

H

H

121
L

L
L

L

L

L

H

H

H

H

H

H

H

H

131

H

H

H

H

141

H

151

4B, LS48
DECIMAL
OR
FUNCTION

o

INPUTS

H

H

H

X

H

x
x
x
x
x
x

H
H
H

H
H

H

• 9

H

10

H

11

H

12

H

13

H

14

H

15

H

BI

x

RBI

H

LT

OUTPUTS

t - - , - - , - - - - - - - - i BI/RBOl11 1 - - - - - - - - - - - - - \ NOTE
LT RBI
D
C
B
A
H
H
H

H

H
H

H
H

H

H

H

H
H

H

H

H

L

H

H

L

H

H

H

H

H

H

L

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

L

L

L

L

L

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

X
X
X
X

H
H
H
H

x
x
x
x
x

H

H

H

H

H

H

H

H

H

H

H

x

x

x

x

H
H

H

H

H
H

H

L

H

H

H

H

H

L

L

H

R

H

L

H

H

L

H

H

H

H

L

H

H

H

H

H
H

H

H

H

H

H

H

L

H

131

L

x

x

x

x

x

121

H

H

H

H

H

141
H

H

H

151

Notes
(1)

BI/RBO is wire-AND logic serving as blanking input (BI) and/or ripple-blanking output (RBO).

(21

The blanking input (BI) must be open or held at a high logic level when output functions 0 through 15 are desired. The ripple-blanking input
(RBi) must be open or high if blanking of a decimal zero is not desired.

(3)

When a low logic leveils applied directly to the blanking input (BII, all segment outputs are H regardless of the level of any other input.

(4)

When ripple-blanking input (RBI) and inputs A, B, C, and 0 are at a low level with the lamp test input high, all segment outputs go H and the
ripple-blanking output (RBO) goes to a low level (response condition).

(5)

When the blanking input/ripple blanking output (BI/RBO) is open or held high and a low is applied to the lamp-test input, all segment
outputs are L

H = High Level, L == Low Level, X == Don't.Care

2·11

~.MSI

OM54/0M7446A,47A,LS47.48 ,LS48 ,LS49

Truth Tables (Continued)
LS49
DECIMAL
OR
FUNCTiON

INPUTS
8

OUTPUTS

NOTE

81

a

b

c

d

e

f'

L

H

H

H

H

H

H

H

L

H

H

L

H

H

L

L

L

L

L

H

H

L

H

H

H

L

L

H

H

L

L

H

H

H

H

L

H

H

L

H

H

H

H

H

H

H

L

L

L

L

H

H

H

H

H

H

H

H

L

L

H

H

L

L

H

H

L

H

L

H

H

L

L

H
H

A

D

C

0

L

L

L

1

L

L

L

2

L

L

H

L

H

H

H

3

L

L

H

H

H

H

H

4

L

H

L

L

H

L

H

5

L

H

L

H

H

H

L

6
7

L

H

H

L

H

L

L

H

H

H

H

H

8

H

L

L

L

H

H

9

H

L

L

H

H

H

10

H

L

H

L

H

L

11

H

L

H

H

H

L

9

12

H

H

L

L

H

L

H

L

L

L

H

13

H

H

L

H

H

H

L

L

H

L

H

H

14

H

H

H

L

H

L

L

L

H

H

H

H

15

H

H

H'

H

H

L

L

L

L

L

L

L

BI

X

X

X

X

L

L

L

L

L

L

L

L

111

121

Notes
(1) The blanking input (81) must be open or held at a high logic level when output functions 0 through 15 are desired.
(2)

H

=

When a low logic level is applied directly to the blanking input (BI), all segment outputs are low regardless of the level of any other input.

High Level, L = Low Level, X

=

Don't Care

Logic Diagrams

46A,47A, LS47

2·12

~ MSI

DM54/DM7446A.47A.LS47.48.LS48.LS49

Logic Diagrams (Continued)
48, LS48

LS49

2-13

~ MSI

DM54/DM7475 ,L75A,LS75 ,LS77
Quad Latches

General Description
These latches are ideally suited for use as temporary
storage for binary information between processing units
and input/output or indicator units. I nformation present
at a data (0) input is transferred to the o output when
the enable (G) is high, and the 0 output will-follow
the data input as long as the enable remains high. When
the enable goes low, the information (that was pre~ent
at the data input at the time the transition occurred) is
retained at the 0 output until the enable is permitted
to go high.

The OM5475/0M7475, OM54L75A/OM74L75A, and
OM54LS75/DM74LS75 feature. complementary 0 and
Q outputs from a 4-bit latch, and are available in 16-pin
packages. For higher component density applications,
the OM54LS77/0M74LS77 4-bit latches are available
in 14-pin flat packages (only).

Connection Diagrams
ENABLE

01

01

02

1~2

GND

il3

03

04

01

01

ENABLE
1-1

GNO

NC

03

04

14

ill

01

02

ENABLE

03

Voc

04

NC

01

il4

3-4

5475/7475(J), (N), (W); 54L75A/74L75A(J), (N), (W);
54LS75/74LS75(Jl. (N), (W)

54LS77 /74LS77(W)

Truth Table (Each Latch)
INPUTS

H

=

OUTPUTS

ci

D

G

Q

L

H

L

H

H

H

L

X

L

00

Cia

H

High Level, L = Low Level, X = Don't Care
of Q Before the High-to-Low Transition of G

00 = The Level

Logic Diagrams (Each Latch)
75,L75

ENABLE

DATA

LS75

LS77

"'::+>?S
. ' ......... :

OTHER
LATCH

ro

ENABLE

ENABLE

Tentative Data For LS75, LS77

"m~.

OTHER
LATCH

2-14

0

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

CONDITIONS
MIN

VIH

High Level Input Voltage

Vll

Low Level Input Voltage

VI

Input Clamp Voltage

IOH

High Level Output Current

VO H

High Level Output Voltage

VOL

Vee

~

I,

Min

Vee

Low Level Output Voltage
Vee

~

==

Min, V ,H

Max,

IOH

~

Min, VIIi

Input Current at Maximum Input Voltage

Vee

lOS

Icc

~

Short Circuit Output Current

TYP(l)

MAX

TYP(l)

MIN

~

~

Max(2)

Supply Current
~

TYP(l)

V

2

2
0.7

0.7

DM74

0.8

0.7

0.8

-1.5

-1.5

2.4

3.4

2.4

3.4

2.5

3.5

DM74

2.4

3.4

2.4

3.4

2.7

3.5

10L
10L

~

~

~

4 mA
Max

5.5V

V,

~

7V

V,

~

2.4V

V

V

-400

-200

DM54

2V,

2.7V

16

2

4

DM74

16

3.6

8
0.25

0.4

0.3

0.25

0.4

0.4

0.35

0.5

DM74
0.2

0.4

DM74

0.2

0.4

0.2

D Input

1

0.2

G Input

1

0.4

D Input

0.1

G Input

0.4

D Input

80

20

G Input

80

40

D Input

20

G Input

80

~

V,

~

0.3V, 54L174L

D Input

-3.2

-0.36

-0.4

V,

~

O.4V, Others

G Input

-3.2

-0.72

-1.6

DM54

-20

-55

-3

-9

-15

-30

-130

DM74

-18

-55

-3

-9

-15

-30

-130

DM74

LS75
Others

32

46

3.5

.5.0

LS75
Others

32

50

3.5

mA

V

mA

C
~

UI

V,

Max(3)

pA
V

DM54

DM54

~

rJ)

MAX

0.8

2V

~

UNITS

DM54

Max

DM54
Vee

MIN

~

Max

Vee~Max

Vee

MAX

~

-1.5

Max

High Level Input Current

Low Level Input Current

LS75, LS77

==

V,
Vee

IlL

L75A

-400

V'L ~ Max

IIH

75

-12 mA

~

<.n

II

DM54LS/74LS

1,~-18mA

Low Level Output Current

~

DM54L/74L

2

V 1L
IOl

DM54/74

5.0

6.3

12

6.9

13

6.3

12

6.9

13

pA

~
......

C
~

~

mA

-..J
UI

mA

UI

Cj
l>
r

rJ)

mA

-..J
UI

i-

rn

-..J
-..J

------_._-

-

-

._-

-----

-----

----

---

-

-- '----

Switching Characteristics Vee ~ 5V, T A ~ 25°C
PARAMETER

FROM
(INPUT)

DM54/74

DM54L/74L

75

L75A

TO
(OUTPUT)
CONDITIONS

'PLH

MIN

Propagation Delay Time.
low-to_-High Level Output

D
tpHL

Propagation Delay Time,

tplH

Propagation Delay Time,

D
tpHl

tplH

11

19

9

17

9

17

120

12

20

N/A

80

7

15

N/A

30

55

100

15

14

25

50

100

24

40

75

7

15

32

MIN

MIN

s:

en

ns

CL = 50 pF
HL

C L = 15 pF

~

R L =2kll

= 4 kfl

16

30

50

100

15

27

10

18

7

15

32

80

14

25

10

18

16

30

48

100

16

30

N/A

7

15

38

80

7

15

N/A

ns

Q

High-ta-Low Level Output

Low-ta-High Level Output

G

27

MAX

RL = 400[2

Propagation Delay Time,

MAX

TYP

C L = 15 pF

tpLH

TYP

MAX

Propagation Delay Time,

PropagatLon Delay Time,

CONDITIONS
TYP

High-ta-Low Level Output

tPHl

MIN

UNITS

Q

Propagation Delay Time,

G

'"

16

CONDITIONS

LS77

ns

Low-ta-High Level Output

~

MAX

LS75

Q

High-te-Low Level Output

low-ta-High Level Output

TYP

~

DM54LS/74LS

Q

ns

tpHl

Propagation Delay~ Time,

tw

Width of Enabling Pulse

20

100

20

20

ns

tSETUP

Setup Time

20

100

20

20

ns

tHOLD

Hold Time

5

25

0

0

ns

High-ta-low Level Output

0

s:c.n

Notes
(1) All typical values are at VCC ~ 5V, T A ~ 2SoC.

~

(2)

Not more than one output should be shorted at a time, and for the OM54LS/74LS duration of short circuit should not exceed one second.

........

(3)

ICC is tested with all inputs grounded and all outputs open.

0
,

s:

~
-.J
c.n

Ci

c.n

'r-!>
en
-.J

U1

;-

en
-.J
-.J

~ MSI

DM54/DM7483.LS83A.LS283
4-Bit Binary Adders with Fast Carry

General Description

Features

These full adders perform the addition of two 4-bit
binary numbers. The sum (2:) outputs are provided for
each bit and the resultant carry (C4) is obtained from
the fourth bit. These adders feature full internal look
ahead across all four bits. This provides the system
designer with partial look-ahead performance at the
economy and reduced package count of a ripple-carry
implementation.

• Full-carry look·ahead across the four bits
• Systems achieve partial look-ahead performance with
the economy of ripple carry

The adder logic, including the carry, is implemented in
its true form meaning that the end-around carry can be
accomplished without the need for logic or level inversion.

83
LS83A

25 ns

LS283

25 ns

TYPICAL ADD TIMES
TWO

TWO

8-BIT

16-BIT

WORDS

WORDS

23 ns

43 ns
45 ns
45 ns

TYPE

TYPICAL POWER
DISSIPATION PER
4-BIT ADDER
290mW
95mW
95mW

Connection Diagrams and Truth Table
B4

C4
15

'6

A4

,,3

,.

A3

co

I"

"

..I'

B3

A'

B'

G~O
13

>:2

Vee

10

.2

"

A3

'3

A2

'"

5483(J), (W); 7483(J), (N), (W);
54LS83A/74LS83A(J), (N), (WI

A2

B'

B4

A4

L1

A'

C4

"

"

13

14

10

co

B'

G!:

54LS283/74LS283(J), (N), (W)

OUTPUT

~~

INPUT

CO~

L

CO~

H

WHEN
C2~ L

WHEN
C2~ H

.~ ~ ~ ~ ~ ~ ~ ~ ~ ~
A4

83

A3

H
L

H

H

H

L
H

L

L

H

L

H

L4

C4

L

2:3

2:4

H

L

L

L

H

L

H

L

L

L

H

H

H

L

H

L

H

H

H

L

H

L

H

H

H

H

H

L

L3

84

L

L

H

H

L

L

H

H

H

L

L

H
H

H

H

L

L

H

L
L

H

L

H

H

L

H

H

H

L

L

H

L

H

L

H

H

H

L

L

H

H

H

L

H

L

L

H

H

H

H

L

L

H

H

H

L,

H
L

H

H

H

H

L

H

H

H

L

H

L

H

H

H

H

L

H

L

H

H

H

H

H

H

L

H

H

H

H

H

H "" High Level, L "" Low Level

Note: Input conditions at A 1, 81, A2, 82, and CO are used to determine outputs 1: 1 and 2;2 and the value
of the internal carry C2. The values at C2, A3, 83, A4, and 84 are then used to determine outputs I:3, 1':4,
and C4.

2-17

LS83A, LS283 To Be Announced In 1976

~

MSI

DM54/DM7483.LS83A.LS283

Electrical Characteristics

over recommended operating free·air temperature range (unless otherwise noted)

PARAMETER

CDNDITIONS

DM54174

DM54lS/74lS

83

LS83A, lS283

UNITS

MIN TYP(1) MAX MIN TYP(1) MAX
V,H

High Level Input Voltage

V,l

Low Level Input Voltage

V,

IOH

2

Vee'" Min
High Leve,1 Output Current

I,

Input Cllrrent at

High level Input Current

-1.5
-1.5
-400

-400

-400

Vee == Min, V 1H

2V

:=

Any Output Except C4

Vee '''' Min

IOL = 4 rnA

V 1H = 2V

IOL - 8 rnA

V 1L

IOL

=

Max

Vee

'=

2.4

3.4

2.5

3.4

DM74

2.4

3.4

2.7

3.4

16

4

16

8

DM54

8

4

DM74

8

8

0.2

Max

V,

c

0.25

0.4

0.35

0.5

0.2

5.5V

1

Low Level I nput Current

Any A or B
CO

lOS

Short Circuit Output

40

V,"2.4V

80

Output C4

Icc' Supply Current

-3.2

-0.8
-0.4

3.2
DM54

··20

-55

-30

-130

DM74

-18

-55

-30

-130

DM54

-20

-70

-30

-130

DM74

··18

-70

-30

-130

All Inputs
Grounded
All B Low, Other

Vee =. Max
Outputs Open

' I nputs at 4.SV
All Inputs at
4.5V

58

79

Notes

= SV, TA = 2S"C.

(1)

All typical values are at VCC

(21

Only one output should be shorted at a time, and for 54LS174LS duration

;

2·18

p.A

20

Vee"" Max, VI == O.4V

Vee" Max(2)

mA

0.1

V, "2.7V

Any Output Except C4

Current

V

80

V, o2.7V
III

rnA

1

V, o2.4V

=Max

I'A

0.4

V, -7V

Vee

V

V

DM74

DM74

V

."

DM54

V, o7V

Max

Any Aor.B

CO

=

DM54

V, "5.5V

AnyAor8

CO
I'H

O.B

-800

Low level Output Voltage

Maximum I nput Voltage

O.B

Any Output Except C4

Output C4

VOL

·DM74

',-··18mA

V)L = Max, IOH =Max

Low Level Olltput Current

0.7

Output C4
VOH High Level Output Voltage

IOl

0.8

l,o-12mA

Input Clamp Voltage

V

2

DM54

of short cifcuit should not exceed one second.

22

39

19

34

19

34

mA

mA

mA

~ MSI

DM54/DM7483,LS83A,LS283

Switching Characteristics

Vee

= 5V, T A = 25°C
DM54LS/74LS

DM54/74

FROM
(INPUT)

PARAMETER

TO
(OUTPUT)
CONDITIONS

tpLH

Propagation Delay Time,
Low-to-Hlgh Level Output
CO

tpHl

Propagation Delay Time,

Propagation Delay Time,
Low-to-Hlgh Level Output
CO

tpHl

tPLH

Propagation Delay Time,

32

16

24

ns

20

32

15

24

ns

28

47

16

24

ns

22

38

15

24

ns

28

47

16

24

ns

28

47

15

24

ns

38

15

24

ns

33

15

24

ns

12

19

11

17

ns

12

19

11

17

ns

12

19

11

17

ns

12

19

12

17

ns

22

C L = 15 pF

Propagation Delay Time,

R L =400l2

Propagation Delay Time,

"

Ai or B j

~,

Propagation Delay Time,

Hlgh-to-Low Level Output
Propagation Delay Time,

Low-ta-High Level Output

CO
tpHL

tplH

C4

Propagation Delay Time,
High-to-Low Level Output

C L "15pF

Propagation Delay Time,

RI-

o

78011

Low-to-High Level Output
Ai or S,
tpHL

C L = 15pF
RL = 2 kn

Propagatlon Delay Time,

Low-ta-High Level Output

tpLH

MIN

~4

High-to-Low Level Output

tPHL

CONDITIONS

"

High-ta-Low Level Output

CO

tPlH

MAX

MAX

-3

Lovv-ta-High Level Output
tPHL

TYP

TYP

:'::1 or 2.:2

High·to-Low Level Output
tplH

MIN

UNITS

LS83A, LS283

83

C4

Propagation Delay Time,
High·to-Low Level Output

Logic Diagrams
83

B3 ;.;(4",1....- r -.......

A'::"3LI:j~C=:>~-1HH1-------------------~

(

2-19

~ MSI

DM54/DM7483,LS83A,LS283

Logic Diagrams (Continued)

LS83A, LS283

)0_ _ _...;.;14"",(9;;.1 C4

Note: Pin numbers shown in parenthesis are for, LS283

2-20

~

MSI

DM54/DM7485.L85.LS85
4-Bit Magnitude C6mparators

General Description

A> B and A < B inputs. The cascading paths of the 85,
and LS85 are implemented with only a two-gate-Ievel
delay to reduce overall comparison times for long words.

These four-bit magnitude comparators perform comparison of straight binary or BCD codes.
Three
fully-decoded decisions about two, 4-bit words (A, B)
are made and are externally available at three outputs.
These devices are fully expandable to any number of
bits without external gates. Words of greater length may
be compared by connecting comparators in cascade. The
A > B, A < B, and A = B outputs of a stage handling
less-significant bits are connected to the corresponding
inputs of the next stage handling more-significant bits.
The stage handling the least-significant bits must have a
high-level voltage applied to the A = B input and in
addition for the L85, low-level voltages applied to the

Features
TYPICAL
DELAY
(4-BIT WORDSI

TYPICAL
POWER
DISSIPATION

TYPE

85
L85
LS85

275mW
20mW
52mW

23 n'
55 n'
24 n'

Connection Diagrams
DATA INPUTS

T
16

A3

82

"

A2
13

14

INPUTS

Al
12

r

AD

81
11

8D
10

vI'

9

16

r-

I

.3
DATA
INPUT

OUTPUTS

A>.

'3
15

A<.

13

14

INPUTS

,

~

A3

11

12

B1

AD

pD

10

Z

3

4

A=B

A>8

,

6

A>'

A"'8

CASCADING INPUTS

7

A<'

1

J:

82

2
A2

J

INPUTS

OUTPUTS

9

l-

~

A<8

\

3
A=8
OUTPUT

,

4

,A>B

6

A:B,

A<.

CASCADING INPUTS

7

Al
INPUT

J:

54L85174L85(JI, (NI, (WI

5485(JI, (WI: 7485(JI, (NI, (WI:
54LS85174LS85(JI, (NI, (WI

Truth Tables
CASCADING
INPUTS

COMPARING
INPUTS

OUTPUTS

A3,83

A2,82

Al,81

AO, BO

A>B

AB

AB3

x

x

x

H

L

L

x

x

H

L

A2> 82

x

X

X

X
X

L

A3 = 83

x
x

x
x

x

A3 <83

x
x

H

L

L

x

X

L

H

L

x

X

H

L

L

x

X

L

H

L

X

X

H

L

L

x

X

L

H

L

L

L

H

L

L

A3 = 83

A2 < 82

x

X

A3 = 82

A2 = 82

A1 >81

A3 = 83

A2 = 82

A1 <81

x
x

A3 = 63

A2 = 82

A1 = 81

AO> 80

A3 = 83

A2 = 82

A1 = 81

AO<80

x
x
x
x
x

A3 = 83

A2 = 82

A1 = 81

AD = 80

H

A3 = 83

A2 = 82

A1 = 81

AD = 80

L

H

L

L

H

L

A3 = 83

A2 = 82

A1 = 81

AO = 80

L

L

H

L

L

H

A3 = 83

A2 = 82

Al = 81

AD = 80

X

X

H

L

L

H

A3 = 83

A2 = 82

Al

= 81

AO = BO

H

H

L

L

L

L

A3 = B3

A2 = B2

Al = 81

AD = 80

L

L

L

H

H

L

A3 = 83

A2 = B2

Al = 81

AD = 80

L

H

H

L

H

H

A3 = 83

A2 = 82

Al = Bl

AD = 80

H

L

H

H

L

H

A3 = 83

A2 = 82

Al = 81

AO = 80

H

H

H

H

H

H

A3 = 83

A2 = B2

Al = 81

AD = 80

H

H

L

H

H

L

A3 = 83

A2 = 82

Al = 81

AO = 80

L

L

L

L

L

L

85, LS85

l85

H = High Level, L = Low Level, X = Don't Care

2-21

LS85 To Be Announced In 1976

Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted)
DM54Ln4L

DM54/74

CONDITIONS

PARAMETER

85
MIN

VIH

High Level Input Voltage

Vil

Low Level Input Voltage

VI

High Level Output Current

VOH

High Level Output Voltage

Vee;;:: Min

VOL

==

L6w,Level Output Voltage

II

Input Current at Maximum

A< B,A> B,

I nput Voltage

orA = B 15)

:::

Max

High Level Input Current

=:

Max

Vee == Max

Icc

0.8

-1.5

N/A

2.4

N/A

1.5

-200

-400
2.4

2.4
16

2

4

DM74

16

3.6

8

DM54

0.4

0.15

0.3

0.25

DM74

0.4

0.2

0.4

0.35

0,5

0.25

0.4

DM74
1.0

0.1

1.0

0.3

40

10

120

30

V, = 7V

Vee::; Max

V, - 2.7V

20

-{l.4

-1.6
-{l.54

V, - 0.3V

Condition B

IlA

rnA

V

.rnA

IlA

60

V , =O.4V

Condition A
Vee == Max

V

-{l.18

4.8

V, - O.4V

Supply Current

V

0.3

V , = 2.4V

Vee = Maxl2)

. -

0.4

0.1

V, = 5.5V

3:

0

V

3.4

DM54

V, = 0.3V

All Other Inputs

los

0.7

0.7

V, = 2.7V

A< B, A>B,
or A = B 15)

Short Circuit Output Current

0.7

1.3

V,=2.4V

All Other Inputs

Low Level Input Current

IOL-4mA

V

2

V, = 7V

AB,
or A = B 15)

III

=- Max

MAX

1.3

V, = 5.5V
Vee

All Other Inputs
IIH

IOL

TYP(ll

0.8

Max, IOH == Max

Vee == Min

MIN

0.8

18mA

Low.Level Output Current

V1L

'"
'"

1.3

-800

V'H = 2V

N

2

MAX

DM74

Vee:::: Min, V tH == 2V

V1L
IOl

TYP(l)

DM54

I, =-12 mA
I, -

MIN

UNITS

LS85

l85
MAX

2

Input Clamp Voltage

10H

TYP(l)

~

DM54Lsn4LS

rnA

CJ1

1.2

DM54

-20

-55

-3

-15

-30

-130

DM74

-18

-55

-3

-15

-30

-130

.j::o

mA

6.6
131
141

88

"3:0
~

7.0
55

0

3:

mA
10.4

20

.j::o

00
CJ1
r""

00
CJ1

fen

00
CJ1

- - _ ... -

Switching Characteristics Vce

5V, T A ~ 25°C
DM54/74

PARAMETER

FROM
INPUT

TO
OUTPUT

NUMBER OF
GATE LEVELS

85
CONDITIONS

Low-ta-High Level Output

Any A or B

Any A or B

Propagation Delay Time,
Low-ta-High Level Output

tpHL

High-ta-Low Level Output

Propagation Delay Time,

tplH

Low-ta-High Level Output
Propagation Delay Time,

tPHL

"-'
w

'"

High-ta-Low Leve1 Output
Propagation Delay Time,

tplH

low-ta-High Level Output
Propagation Delay Time,

tpHl

High-to-Low Level Output

TYP

MAX

CONDITIONS

MIN

TYP

70

115
115

19

3

17

26

70

115

24

36

A-B

4

23

35

70

115

23

40

1

11

55

90

11

AB

2

15

55

90

15

3

20

30

55

90

20

30

A=B

4

20

30

55

90

20

30

A>B

1

7

11

55

100

14

22

ns

A < B or A = B

CL = 15 pF
= 400n

C L = 50 pF
RL

= 4 kn

3:

Ul

MAX

70

RL

Propagation Delay Time,

MIN

12

Data Input

tpLH

CONDITIONS

7

Propagation Delay Time,

High-ta-Low Level Output

MAX

UNITS

LS85

L85
TYP

1
AB

Data Input

tpHL

MIN

~

DM54LS/74LS

2

Propagation Delay Time,

tpLH

DM54L/74L

14

CL = 15 pF
RL

ns

I

ns

= 2 kr!

AB

1

11

17

40

65

11

17

ns

A=B

A=B

2

13

20

55

100

13

20

ns

A=B

A=B

2

11

17

40

65

11

17

ns

A> B or A = B

ABorA=B

A--<

~

~y

pJfr
A2

(13)

)0-

2 U4J

A<8

~

irfo+---' D--

(2)

131

A>B

16)

~

~

(ll)

6=8=s ~8v-

~~hl1l
..,........,
--<

AD
BO

A=8

14)

,(12)

B1

A>'

(10)

")0-IS)

~
)--

L85
AJ {l5)

83 {141

A2 (2)

6211)

A1 (1)

Bl t91

AutIO)

80 (11 )

A:>8(4)
A<..B (5)

;tl} A"'S
OUTPUT

A=B (6)

2·24

A<'

~MSI

OM54/0M7488
256-Bit Read Only Memories

General Description
These custom-programmed, 256-bit, read-only memories
are organized as 32 words of eight bits each. Each 32-word
memory array is addressed in straight 5-bit binary with
full on-chip decoding. An overriding memory-enable
input is provided which, when taken high, will inhibit the
32 address gates and cause all eight outputs to remain
high (off). Data, as specified by the customer, are
permanently programmed into the monol ithic structure
for the 256-bit locations. This organization is expandable
to n-words of N-bit length.

only one decoding gate is addressed at a time, only one
of the 32 transistors can supply current to the output
buffers at a time.
Input buffers lower the fan-in requirement to only one
normalized DM54/74 load for all inputs including enable
(G). The open-collector outputs are capable of sinking
12 milliamperes of current and may be wire-AND
connected to increase the number of words available. An
external pull-up resistor from each output to the supply
. line (V cel is required to define the high-level output
voltage. Where multiple devices are used in a memory
system, the enable input allows easy decoding of additional address bits.

The address of an eight-bit word is accomplished through
the buffered, binary select inputs which are decoded by
the 32, five-input address gates. When the memoryenable input is high, all 32 gate outputs are low, turning
off the eight output buffers.

Features

Data are programmed into the memory at the 32,
eight-emitter transistors. The programming process involves connecting or not connecting each of the 256
emitters. If an emitter is connected, a low-level voltage
is read out of that bit location when its decoding gate is
addressed. If the emitter is not connected, a high-level
voltage is read when addressed. Those decoding-gate
outpu~ emitters which are used are connected to their
respective bit lines to.drive the eight output buffers. Since

•
•
•
•
•
•
•

Typical access time: 20 ns
Typical power dissipation: 240 mW
Applications in computer subroutines
Useful in display systems and readouts
Memory organized as 32 words of 8 bits each
Input clamping diodes simplify system design
Open-collector outputs permit wire-AND capability

Connection and Schematic Diagrams
BINARY SElECT
ENABLE

v~

r"

OUTPUT

G

VB

"

14

13

3

4

"

11

10

,

,

1

9

r-

,

1

,~VI____
V_'___V_3____V~4___V_'____
V6____V~7

OUTPUTS

I'

GNO

".

5488(J), (W); 7488(J), (N), (W)

r--------~"1

I
I
I

I

I

I

I

TO]10THER
DECODING GATES

I
I
PROGRAMMABLE
LlNKS
(256 POSSIBLE)

1 OF 32 ADDRESS
DECODING GATES

L _________ ...l

r---'--I
I

--,
I
I

360

I

IB~T

I ~~~;~~s
I
I

I
I

1k

":"

Yl

va

V5

Y4

YJ

V2

VI

I'

~------------------~
2-25

,

~

DM54/DM7488

MSI

Electrical Characteristics

over recommended operating free·air temperature range (unless otherwise noted)
DM54/74
CONDITIONS

PARAMETER

VIH

High level Input Voltage
low level I.nput Voltage

VI

Input Clamp Voltage

Vcc=Min,

1,"-12mA

IOH

High level Output Current

Vcc=Min,

V,H

V'L "0.8V,

VOH "5.5V

Low Level Output Current

VOL

low level Output Voltage

TYP(1)

MAX
V

2

Vll

IOl

UNITS

88

MIN

~

2V

V;L "a.av,

V,H "2V
10L " 12 rnA

Vee

:=

Min,

0.2

0.8

V

-1.5

V

40

/lA

12

mA

0.4

V

II

Input Current at Maximum Input Voltage

Vcc" Max,

V, "5.5V

1

IIH

High level I nput Current

Vee

:=

Max,

V, " 2.4V

25

III

Low level I nput Current

Vee

=0-

Max,

V, "O.4V

ICCH

Supply Current, All Outputs High
0

Maxl2)

Icel

Supply Current, All Outputs low

Vcc

-1

37

65

48

80

mA
/lA
mA
rnA

Notes
(1)

All typical values are at VCC " 5V, T A" 25'C.

(2)

All 32 words are addressed separately to ensure that the supply current does not exceed the stated maximum. The typical value shown is for
the worst-case condition of all eight outputs driven low at one time.

Switching Characteristics vee

= 5V, T A

= 25°C
DM54/74

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

CONDITIONS

tplH

Propagation Delay Time,

low·to·High Level Output
tpHl

Propagat(on Defay Time,

High-to·Low Level Output

Enable

Any

Enable

Any

CL " 30 pF

UNITS

88

MIN

TYP

MAX

19

35

ns

18

35

ns

21

35

ns

17

35

ns

RLl "400n

tplH

Propagation Delay Time,

low·to·High Level Output
tpHL

Propagation Delay Time,

High·ta·Low Level Output

Select

Any

Select

Any

Ru "600n

Ordering Instructions
Each card in the data 'deck prepared by the purchaser
identifies the word specified and describes the levels at
the eight outputs for that word. All addresses must have
all outputs defined and columns designated as "blank"
must not be punched. Cards should be punched according
to the data card format shown.

Programming instructions for the DM5488 or DM7488
are solicited in the form of a sequenced deck of 32
standard 80·column data cards providing the information
requested under "data card format," accompanied by a
properly sequenced listing of these cards, and the
supplementary ordering data. Upon receipt of these
items, a computer run will be made from the deck of
cards which will prodUCe a complete function table of
the requested part. This function table, showing output
conditions for each of the 32 words, will be forwarded
to the purchaser as verification of the input data as
interpreted by the computer·automated design (CAD)
program. This single run also generates mask and test
program data; therefore, verification of the function
table should be completed promptly.

Supplementary Ordering .Data
Submit the following information with the data cards:
a. Customer's name and address
b. Customer's purchase order number
c. Customer's drawing number
2.-26

~ MSI

OM54/0M7488

DataCard Format
Column
Punch a right·justified integer representing the
positive-logic binary input address (00-31) for
the word described on the card.

31-34

Blank

35

Punch "H," "L," or "X" for output Y2.

36-39

Blank

3-4

Blank

40

Punch "H," "L," or "X" for output Y1.

5

Punch "H," "L," or "X" for output Y8.
H = high-voltage-level output, L = low-voltage·

41-49

Blank

50-51

Punch a right-justified integer representing the
current calendar day of the month.

52

Blank

1-2

level output, X

= output

irrelevant.

6-9

Blank

10

Punch "H," "L," or "X" for output Y7.

53-55 Punch an alphabetic abbrev iation representing

11-14

Blank

15

Punch "H," "L," or "X" for output Y6.

56

16-19

Blank

57-58 Punch the last two digits of the current year.

the current month.
Blank

20

Punch "H," "L," or "X" for output Y5.

59

Blank

21-24

Blank

60-61

Punch "OM"

25

Punch "H," "L," or "X" for output Y4.

26-29

Blank

62-65 Punch the National Semiconductor part number
5488 or 7488.

30

Punch "H," "L," or "X" for output Y3.

66-70 Blank

Logic Diagram

Word Select Table

INPUTS

WORD

E

c

D

L
L

I
lW+~¥R-~lf~\8~--r·t~~t-+-T-l
19

L

H

H

L

H

H

4

L

H

L

L

L

H

L

H

6

L

H

H

L

H

H

H

L

H

L

L

L

L

H

L

L

H

10

H

L

H

L

11

H

L

H

H

12

H

H

13

H

H

L

H

14

H

H

H

L

15

H

H

H

H

16

H

L

L

L

L

17

H

L

L

L

H

18

H

19

H

L

Y

H

20

H

H

H

21

H

.22

H

H

H

L

L

H

H

23

H

L

H

H

24

H

H

L

L

L

25

H

H

L

H

26

H

H

L

H

L

27

H

H

L

H

H

28

H

H

H

L

29

H

H

H

H

30

H

H

H

H

L

31

H

H

H

H

H

H = High Level, L

2-27

A

5

9

BINARY
SELECl

B

:=

Low Level

H

~ MSI

DM541DM7489,l89A
64-Bit Read/Write Memories

General Description
denote that full "tenth-power" technology has been
employed in building this RAM.

The DM5489/DM7489, DM54L89A/DM74L89A are fully
decoded 64-bit RAMs organized as 16, 4-bit words. The
memory is addressed by applying a binary number to
the four Address inputs. After addressing, information
may be either written into or read from the memory.
To write, both the Memory Enable and the Write Enable
inputs must be in the logical "0" state_ Information
applied to the four Write inputs will then be written
info the addressed ic;lcation. To read information from
the memory the Memory Enable input must be in the
logical "0" state and the Write Enable input in the logical
"1" state. Information will be read as the complement
of what was written into the memory. When the Memory
Enable input is in the logical "1" state, the outputs will
go to the logical "1" state.

Features
•
•
•
•
•
•

For application as a "scratch pad" memory with
nondestructive read-out
Fully decoded memory organized as 16 words of
four bits each
DM54/74-35 ns typical
Fast access ti me
DM54l/74L-110 ns
Diode-clamped, buffered inputs
Open-collector outputs provide wire-OR capability
Typical power dissipation
.DM54/74-400 mW
DM54L!74L-75 mW
Pin compatible with 3101, MM5501

The "A" suffix on the low power versions is used to

•

Connection Diagram

Truth Table
SENSE
OUTPUT

3

MEMORY
ENABLE

WRITE
ENABLE

OPERATION

0

0

Write

Logical "'" State

0

1

Read

Complement of Data

1

X

Hold

OUTPUTS

Stored in Memory

SELECT MEMORY WRITE
'----v---'

INPUT A

ENABLES

DATA
INPUT
1

SENSE
OUTPUT
t

DATA'
INPUT
2

SENSE
OUTPUT
2

GND

5489IJ); 7489IJ), IN);
54L89A/74L89AIJ), IN)' IW)

Logic Diagram

rAU~::
I~AI
AI
Al

ADDRESS
INPUTS

A2

~ A2
A2

AJ

~

A3
AJ

DI
DZ
D3

OATA
INPUTS

D.
WE
ME

2-28

Logical" 1" State

~

MSI

OM54/0M7489,L89A

Electrical Characteristics over recommended operating free·air temperature range (unless otherwise noted)
DM54/74
CONDITIONS

PARAMETER

High Level I nput Voltage

UNITS

L89A

TVP(1)

MIN
V,H

DM54L174L

89
MAX

MIN

TVP(1)

MAX
V

2

2

V,L

Low Level Input Voltage

V,

Input Clamp Voltage

Vee = Min, I, = -12 mA

IOH

High Level Output Current

Vee = Min, V'H = 2V

DM54

100

50

V 1L == Max. V OH '" 5.5V

DM74

20

50

VOH

High Level Output Voltage

IOL

Low Level Output Current

VOL

Low Level Output Voltage

Input Current at Maximum

I,

0.8

0.7

V

-1.5

--1.5

V
IJA
V

5.5

5.5

DM54

12

2.0

DM74

12

3.6

Vee = Min, V'H = 2V

DM54

0.4

0.3

V 1L

DM74

0.4

0.4

Vee = Max, V, = 5.5V

1

0.1

mA

Vee = Max, V, = 2.4V

40

10

IJA

==

Max,

IOL ==

Max

mA

V

Input Voltage
I'H

High Level Input Current

I,L

Low Level Input Current

V, = 0.3V

Vee == Max

-0.18
-1.6

V,=OAV

ICC

Supply Current

Vee = Max(2)

80

Co

Off-State Output Capacitance

Vee = 5V, Va = 2.0V, f = 1 MHz

6

120

15

19

mA
mA
pF

N/A

Notes
(1) AU. typical values are at V CC

= 5V, T A = 25° c.
ICC is measured with all inputs grounded.

(2)

Switching Characteristics vee

= 5V, T A

= 25°C
DM54/74

PARAMETER

CONDITIONS
MIN

tpLH

Propagation De:lay Time, Low-ta-High
Level Output From Memory Enable

tpHL

Propagation Delay Time. High-ta-Low
Level Output From Me~ory Enable

tpLH

tpHL

CL

Ru = 300n

Level Output From Select

RL2 = 600n

Level Output From Select

Sense Recovery Time After Writing

tw

Width of Write-Enable Pulse

!sETUP Setup Time, Data Input With Respect to

Write Enable
!sETUP Select Input Setup Time With Respect to

Write Enable
tHOLD

Hold Time, Data Input With Respect to

Write Enable
tHOLD

Select Input Hold Time after Writing

TVP

MAX

23

UNITS

TVP

MAX

35

64

90

ns

23

35

33

60

ns

34

50

90

150

ns

35

50

78

150

ns

35

50

110

165

ns

MIN

CL

Propagation Delay Time, High-ta-Low

L89A

CONDITIONS

= 30 pF

Propagation Delay Time, Low-la-High

!sR

DM54L/74L

89

RL

= 50 pF
= 4 kn

40

50

ns

a

a

ns

a

0

ns

0

a

ns

5

0

ns'

2-29

~MSI

DM54/DM7490A. L90. LS90 .92A.LS92 .93A. L93 .LS93
Decade.Divide by 12. and Binary Counters

General Description
Each of these monolithic counters contains four
master-slave flip-flops and additional gating to provide
a divide-by-two counter and a three-stage binary counter
for which the count cycle length is divide-by-five for the
90A, L90, and LS90, divide-by-six for the 92A and
LS92, and divide-by-eight for the 93A. L93, and LS93.

obtained from the 90A, L90, or LS90 counters by
connecting the Q D output to the A input and applying
the input count to the B input which gives a divide-byten square wave at output QA'

Features
All of these counters have a gated zero reset and the
90A, L90, and LS90 also have gated set-to-nine inputs
for use in BCD nine's complement applications.

TYPICAL
POWER DISSIPATION

TYPE
90A
L90
LS90
92A. 93A
LS92, LS93
L93

To use their maximum count length (decade, divideby-twelve, or four-bit binary, the. B input is connected
to the Q A output. The input count pulses are applied to
input A and the outputs are as described in the appropriate
truth table. A symmetrical divide-by-ten count can be

COUNT
FREQUENCY

145mW
20mW
45mW
130'mW
45mW
16mW

42
11
42
42
42
15

MHz
MHi
MHz
MHz
MHz
MHz

Connection Diagrams
INPUT

GN10

A

12

14

INPUT

D,

Nr

A

10

11

14

aD

D,
11

12

I"

B

-c>

1

2

,

RO(11

RO 121

Jc

4

INPUT
B

..1

6

5

1

1

R9111

Vee

R9121

B

5490A17490A(JI. (NI. (WI;
54L90/74L90(JI, (NI. (WI;
54LS90174LS90(JI. (NI, (WI

INPUT
A

14

T
13

a.

aD

12

11

T
10

Nle'

NV

INPUT

Nle'

.15

6

1

Vee

ROlli

ROl21

5492A17492A(JI. (N). (WI;
54LS92174LS92(JI, (NI. (WI

a,
9

INPUT

ae

A

I.

B

a.
13

00

12

GND

1"

Dc
10

D,

INPUT
B

B

9

-0

<10-

2
INPUT

ROlli

,
ROl21

R0(11

ROl21

B

5493A/7493A(JI. (NI, (WI;
54LS93/74LS93(JI, (N). (WI

54L93174L93fJ1. (NI. (WI

2-30

LS90, LS92, LS93 To Be Anno.unced In 1976

Electrical Characteristics

DM54/74
PARAMETER

CONDITIONS

V,H

High Level Input Voltage

V,L

Low Level I nput Voltage

High Level Output Current

VOH

H'gh Level Output Voltage

~-12

I,

Vee:::; Min

~

Min, V ,H

2

Vee = Min

0.7

0.8

DM54

2.4

3.4

Max

DM74

2.4

3.4

V'H ~ 2V

I,

Input Current at Maximum

I nput Voltage

==

Max

High Level Input Current

Vee == Min

Vec ~ Max

ce

V

==

B Input

Icc

Short Circuit Output Current

Supply Current

2.4

3.4

2.4

2.7

3.4

2

4

16

3.6

8

0.15

0.3

DM74

0.2

0.4

0.2

0.4

DM74

5.5V

1

0.1

1

0.2

V,

~

5.5V

V,

~

2.7V for LS

V,

~

204V for Others

Vee

Vee

~

~

Max

V,

~

0.3V for L

VI

~

0.4 V for Others

Max(2)

Max(4)

pA
V

16

004

0.25

0.4

0.35

0.5

0.25

0.4

C

rnA

L90

V

1

0.4
0.8

40

10

20

20

120

93

80

20

40

Others

120

40

80

-1.6

-0.18

--0.4

-32

-0.36

-2.4

93

-3.2

-0.36

-1.6

Others

-4.8

-0.72

-3.2

DM54

-20

-57

-3

-9

-15

-30

-130

DM74

-18

-57

-3

-9

-15

-30

-130

90A

29

42

26

39

5.5

s:...,
CD
0

rnA

l>
r-

0.2

80

Others

"C
.j::a

0.4

Others

s:
U1
.j::a

:

0.1

Any Reset
A Input

los

~

-400
2.5

0.2

V, - 5.5V

B Input
Low Level I nput Current

4 rnA

-200

DM54

Any Reset
A Input

I,L

~

V

-1.5

V,~7V

B Input
I'H

IOL
V,

Any Reset
A Input

Max (3)

V

N/A
N/A

=

s:

-

m

V

2

0.8
-1.5

UNITS

MAX

DM74

2V

~

.TYP(l)

0.7

~

IOL

MIN

0.7

DM54

Low Level Output Voltage

LS90, LS92, LS93
MAX

0.8

rnA

Low Level Output Current

V1L

'"
~

TYP(l)

DM54

DM74
VOL

MIN

-800
Vee

DM54LS/74LS

L90, L93

MAX

I, ---18 rnA

V 1L = Max,,1oH

10L

TYP(l)

2

I nput Clamp Voltage

IOH

DM54L/74L

90A, 92A, 93A
MIN

V,

~

over recommended operating free-air temperature range (unless otherwise noted)

·9

15

CD
0

rm
pA

CD

0
(g
N

»

rnA

rm
CD
N

rnA

rnA

(g
W

»
r-

CD
W

rm
CD

w

~

Switching Characteristics V cc =5V,T A =25°C
DM54L/74L

DM54/74
FROM
(lNPUTI

PARAMETER

f max

tpLH

Maximum Count Frequency

TO
(OUTPUT 1

B

GA
Gs

A

GA

A

CONDITIONS

90A, LS90
MIN

TYP

32

42

16

Propagation Delay Time,
Low-ta-High Level Output

tpHL

Propagation Delay Time.

CL = 50 pF

Low-ta-High Level Output

A
tpHL

GD

High-ta-Low Level Output

CL =15pF

tplH

Propagation Delay Time,

For All Others

tpHL

Propagation Delay Time,

B

Gs

92A, LS92
MIN

TYP

32

42

93A, LS93

MAX

16

MIN

TYP

32

42

MIN

TYP

6

11

MAX

MIN

TYP

6

15

UNITS

MHz

16

10

16

10

16

10

16

12

18

12

18

12

18

32

48

32

48

46

70

175

300

210

400

34

50

34

50

46

70

190

300

230

400

10

16

10

16

10

16

C

3:
C1I

ns

RL = 400n
14

21

14

21

14

21

21

32

10

16

21

32

23

35

14

21

23

35

21

32

21

32

34

51

23

35

23

35

34

51

Any

26

40

26

40

26

40

GA.O O

20

30

Gs.Clc

26

40

3:

'"w

'"

Propagation Delay Time,
Low·to-High Level Output

B
tpHL

Propagation Delay Time,

Clc

High-ta-Low Level Output
tpLH

Propagation Delay Time,

tpHL

Propagation Delay Time,

RL = 2 HI

ns

For lS90. LS92
and LS93
RL=4kfl

Low-ta-High Level Output

B

GD

ns

For L90 and L93

High-to-Low Level Output
"'Hl

Propagation Delay Time,

Set-to-O

High-to-Low Level Output
tpLH

Purse Width

I A Input

I B Input
I Reset Input

tSETUP

»
,...
-

1

I'

GND

CLOCK2
L-SHIFT

. OU.TPUTS

OUTPUTS

CLOCK2

OUTPUTS

2
IN~UT 8

SERIAL

,

14

INPUT C

INPUT

5495(JI, (W); 7495(J), (N), (W);
54LS95B174LS95B(J), (N), (W)

Vee'

•

5
INPUT 0

7

MODE

CLOCK 1

CONTROL

R·SHIFT

54L95174L95(J), (N) ,(WI

Logic Diagram
DATA INPUTS
A

2,(14)

';12l

•

c
4. III

o
',I.l

MODE 6,(61

CONTROL

Note: Pin numbers in
parenthesis ar,e for L95
t3,(13)
0.

".I12l

o.
OUTPUTS

Tentative 'Oata For LS95B

2·36

LS9SB To Be Announced In 1976

Electrical Characteristics

~

over recommended operating free·air temperature range (unless otherwise noted)
DM54/74

PARAMETER

CONDITIONS

95
MIN

VIH

High Level Input Voltage

VIL

Low Level I nput Voltage

IOH

High Level Output Current

V OH

High Level Output Voltage

~

Min

Vee

~

Min, V ,H

VOL

II

=

Max,

Low Level Output Voltage

Input Current at Maximum

Mode Control

I nput Voltage

Others

IOH :::

Vee

~

Min

V ,H

=

2V

MIN

TYP(I)

0.7

DM74

0.8

0.7

0.8

~1.5

N/A
~1.5

N/A
~200

~400

DM54

2.4

3.4

2.4

3.1

2.5

3.4

Max

DM74

2.4

3.4

2.4

3.1

2.7

3.4

IOL
V,

~

V,

~

~4mA

16

2

4

DM74

16

3.6

8

0.2

0.4

0.13

0.3

0.25

DM74

0.2

0.4

0.2

0.4

0.35

0.5

0.25

0.4

1

0.2

1

0.1

V
I'A

0.4

0.2

7V

V

mA

DM54

5.5V

V)

V

DM54

DM74

~

V

2
0.7

2V

IOL ::: Max

UNITS
MAX

V

mA

0.1

Mode Contcal
Others

Vee

Clock Inputs

~

Mode Control
Others
Mode Control

V,

=

2.4V

V,

=

2.7V

V,

~

Max

Others
Low Level Input Current

2

Vee"" Max

Others
High Level Input Current

IlL

~

MAX

0.8

mA

Low Level Output Current

Clock Inputs

IIH

TYP(1)

DM54

11~~18mA

V'L ~ Max

""....
w

~~12

MIN

~800

V 1,L
10L

II

Vee

LS95B

L95
MAX

2

Input Clamp Voltage

VI

TVP(I)

DM54LS/74LS

DM54L/74L

20

40

10
40

~

<11
~

~0.18

OAV

~1.6

Short Circuit Output Current

Vee

~

Max(2)

Icc

Supply Current

Vee

~

Max(3)

~18

~57

50

75

mA

.......
C
~

-130

mA

CD
<11

21

mA

-D.4
-D.8

~1.6

Others
lOS

C
~

-D.36

0.3V
~3.2

V,

I'A

20

Vee:::: Max

Clocks

80

~

~0.4
~3

--9
4.8

~15

8

~30

13

r-

CD
<11

Notes
All typical values are at VCC ~ 5V, T A ~ 25'C.

r-

( 1)

V)

(2)

Not more than one output should be shorted at a time, and for DM54LS174LS duration of short circuit should not exceed one second.

131

ICC is measured with all outputs and serial input open; A, B, C, and D inputs grounded; mode control at 4.5V; and a momentary 3V, then ground, applied to both clock inputs.
--

~~

CD
<11
CO

Vcc ~ 5V, T A ~ 25°C

Switching Characteristics

DM54/74
PARAMETER

Maximum Clock Frequency

MIN

TYP

25

36

MAX

CONDITIONS

MIN
6

~

DM54LS/74LS

L95

95
CONDITIONS

f max

DM54L!74L

UNITS

LS95B
TYP

MAX

CONDITIONS

14

MIN

TYP

25

36

MAX

3:

en

-

MHz

Propagation Delay- Time,

tPLH

Low"to"High Level Output

CL

From Clock

~

25

15 pF

35

42

C L ~ 50 PF:

RL ~ 400n

RL

~

90

CL~15pF"

18

27

ns

21

32

ns

RL ~ 2 kn

4 kn

Propagation Delay Time,

tpHl

High"to"Low Level Output

25

48

35

90

From Clock
90

25

ns

tSETUP

Setup Time, High-Level Data

20

10

50

20

ns

tSETUP

Setup Time, Low"Level Data

20

10

50

20

ns

0

10

ns

120

20

ns

15

tW(CLOCK) Width of Clock Pulse

Hold Time. High"Level or

tHOLD

0

Low"Level Data

'"w

00

tENABLE 1 Time to Enable Clock 1

-10

20

tENABLE2 Time io Enable Clock 2

15

100

20 '

ns

tlNHIBITl

Time to I nhibit Clock 1

10

0

20

ns

tiNHIBIT2

Time to Inhibit Clock 2

10

0

20.

ns

Truth Table
INPUTS
MODE

CLOCKS

CONTROL

2 (Ll

1 (Rl

H

H

X
X
X

•
•

H
H

L
L
L

t
t
t
t

-----

A

B

C

D

X

X

X

X

X

X

a

b

c

d

X

Qat

Oct

d
X

L

H

X

X

X

•

H

X

X

X

X

3:

X

X

X

X

<4

o.

Ce

00

OAO
a

OBO
b

OCO
e

0 00
d

OBo

Oeo

0 00

d

OAO
H
L

OBO
OAO

Dco
OBo

000
Oeo

OAo

OBo

Oeo

L
L

L

L
X

X

X

X

X

OAO

OBO

OeD

L

X

X

X

X

X

OAO

OBO

L

H

X

X

X

X

X

OAO

OBO

Dco
Dco

000
0 00
0 00

H

L

X

X

X

X

X

QAO

OBO

OeD

0 00

OAO

0,,0

Dco

0 00

H
----

PARALLEL

X
X

•

SERIAL

Oat
X

•

C

OUTPUTS

H

X

X

- - ---------------- -----

X

X

X

CJ1

oIlo
.......
C

3:

tShifting left requires external connection ofinput D.
H = High Level (Steady State),_ L
transitions)

= Low

aS to A, QC to s,' QD to C. Serial data is entered at

Level (Steady StateL X

=:

Don't Care (Any input, including

:g
(D

CJ1

r-

(D

t"" Transition from high to low level, t = Transition from low'to high level
a, b, c, d = The level of steady state input at inputs A, B, C, or D, respectively.
OAO, aBO., 0CO, 000 ~ The level of 0A. 0B. 0C, or 00. respectively, before the indicated steady
state input conditions were established.

(D

0An, 0Sn, 0Cn, oDn ~ The level of 0A. OS. 0C, or 00, respectively. before the most recent I
transition of the clock.

OJ

CJ1

r-

en
CJ1

~ MSI

DM54/DM7496,LS96
5-Bit Shift Registers

General Description
These shift registers consist of five R-S master-slave
flip-flops connected to perform parallel-to-serial or serialto-parallel conversion of binary data. Since both inputs
and outputs for all flip-flops are accessible, parallel-in/
parallel-out or serial-in/serial-out operation may also be
performed.

Transfer of information to the outputs occurs on the
positive-going edge of the clock pUlse. The proper information must be set up at the R-S inputs of each
flip-flop prior to the rising edge of the clock input
waveform. The serial input provides this information
to the first flip-flop, while the outputs of the subsequent
flip-flops provide information for the remaining R-S
inputs. The clear input must be high and the preset or
preset enable inputs must be low when clocking occurs.

All flip-flops are simultaneously set to a low output
level by applying a low-level voltage to the clear input
while the preset is low. Clearing is independent of the
level of the clock input.
The register may be parallel loaded by using the clear
input in conjunction with the preset inputs. After
clearing all stages to low output levels, data to be loaded
is applied to the individual preset inputs (A, B, C, D,
and E) and a high-level load pulse is applied to the
preset enable input. Presetting is also independent of
the level of the clock input.

Features
•

N-bit serial·to·parallel converter

•

N-bit parallel-to-serial converter

•

N-bit storage register

Connection Diagram
OUTPUTS

CLEAR

OUTPUTS

10

' GA

16

15

11

12

13

14

SERIAL
INPUT

fiE

GN

10

-

-

-p

CLOCK

,A

15

B'

E

Vee

PRESET
ENABLE

PRESET

PRESET

5496(J), (W); 7496(JI, (N), (W);
54LS96/74LS96(J), (N), (W)

Truth Table
OUTPUTS

INPUTS
CLEAR

PRESET

PRESET

ENABLE

A

B

C

D

L

X

X

L

X

X

X

L

L

L
H

CLOCK

SERIAL

X
X
X

H

H

H

H

H

H

H

L

L

L

H

H

H

L

H

H

L

H

L

X

X

X

X

L

H

L

X
X

X
X

t

H

L

X
X

x

H

X
X
X

X
X
X
X
X
X

X
H

L

X

aA

'as

ac

00

L

L

L

aE

L

H

H

H

H

H

GAO

G BO

Geo

GOO

G EO

H

GBO

H

GOO

H

GAO

GBO
GAn

Goo
GCn

G EO

H

L

GAn

Dco
G Bn
GBn

Dcn

G on

Gon

= high level (steady state), L = low level (steady state)
X = don't care (any input, including transitions)

H

t

= transition from low to high level

QAO, Os 0, etc. = the level of QA, 0B, etc., respectively before the indicated steady state input conditions were established.
0An, 0Sn, etc. = the level of QA, 0B, etc., respectively before the most recent t transition of the clock.
Tentative Data For LS96

2-39

LS96 To Be Announced In 1976

~

DM54/DM7496.lS96

MSI

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
DM54i74
CONDITIONS

PARAMETER

MIN
V ,H

High Level Input Voltage

V,l

Low Level Input Voltage

TYPO)

10H

High Level Output Current

VOH

High Level Output Voltage

Vee

=

Min

Vee

0--

Min, V 1H

VOL

Low Level Output Voltage

=-

High Level Input Current

V iH

=

2V

V1L

'"

Max

Vee

=

Max

2V

Low Level Input Current

IOL

~

tOL

=4mA

Max

2.4

3.4

2.5

3.5

DM74

2.4

3.4

2.7

3.5

16

4

DM74

16

8

DM54

0.2

0.4

0.25

0.4

DM74

0.2

0.4

0.35

0.5

0.25

0.4

DM74
1

0.1

V, = 2.4V
V, - 2.7V

20

V, = 2.4V

200

=

Max, VI = GAV

Preset Enable

los
Icc

Short Circuit Output Current

Vee ~ Max(2)

Supply Current

~A

rnA

V

rnA

~A

20

V, - 2.7V

Vee

V

40

Any Input Except
Preset Enable

V

V

DM54

VI '=7V

Preset Enable

Vee "'Max

-400

DM54

V,"5.5V

Any I nput Except

Preset Enable

I,l

0.8

-1.5

Max., IqH = -400.uA

Vee:::' Min

Input Current at MaXimum Input Voltage

I'H

0.8

-1.5

Low Level Output Current

I,

V

0.7

11 ""--lamA

'"

MAX

0.8

-400

V 1l.

IOl

TYP(l)

2

Ij 0;0--12 mA

Input Clamp Voltage

UNITS

LS96
MIN

MAX

2
DM54
DM74

V,

DM54 LS/74 LS

96

Vee = MaxI31

-1.6

-0.4

-·8

-2

DM54

-20

--57

-30

-130

DM74

-18

-57

-30

-·130

DM54

48

68

12

20

DM74

48

79

12

20

rnA

rnA

rnA

Notes
(1)

All typical values are at VCC = 5V. TA = 25°C.

(21

Not more than one output should be shorted at a time, and for DM54LS/74LS duration of short circuit should not exceed one second.
ICC is measured with the clear input grounded and all other inputs and outputs open.

(3)

Switching Characteristics vee

= 5V. T A = 25°C
DM54 LS/74LS

DM54/74
PARAMETER

96
CONDITIONS

,fmax
tplH

Maximum Shift Frequency

LS96
MIN

Propagation Delay Time, High-tolow Level Output From Clock

tplH

Propagation Delay Time, Low-to-

CONDITIONS

UNITS
MIN

TYP

MAX

10
25

40

25

40

CL = 15pF.RL =400f!

MHz

25

40

ns

25

40

ns

28

35

ns

55

ns

CL ·15pF.RL =2kf!

High Level Output From Preset
or Preset Enable
tPHl

MAX

10

Propagation Delay Time, Low·toHigh Level Output From Clock

tpHl

TYP

25

35

Propagation Delay Time, High-to55

Low Level Output From Clear
tW(CLOCKI Width of Clock Input Pulse

35

35

ns

tw

Width of Preset and Clear Input Pulse

30

30

ns

tSETUP

Serial Input Setup Time

30

30

ns

tHOlD

Seriailnput Hold Time

0

0

ns

2-40

~ MSI

DM54/DM7496,LS96

Logic Diagram
PRESET
A

PRESET
B
OUTPUT
UA

(2)

PRESET
C
OUTPUT

(3)

a,

(15)

PRESET
E

PRESET
0
OUTPUT

(4)

(6)

a,

OUTPUT
ae

(7)

(11)

(13)

(14)

OUTPUT
00

(10)

::!~~;~~--------------~~-----r-----r~-----+-----+-.-----t-----;~~----r----;~

a

INPUT

Timing Diagram
TYPICAL CLEAR, SHIFT, PRESET, AND SHIFT SEQUENCES
CLOCK

_-+______..
-+______-;-;__________________________________

PRESET __
ENA8LE

~

CLEAR
SERIAL
INPUT

A

PRESETS

--,

OA __ .'

I

--"

OB __ ... I

OUTPUTS

--.,I

Dc __ -'

I
°D --,
___
I

OE::]I

n

(I

n

I

I

-n
n

I

r-LJ
I ~

n
SHIFT

PRESET

CLEAR

2-41

I

H

SHIFT

LI L
H

~MSI

DM54/DM74L98
4-Bit Storage Registers

General Description
These data selectors/storage registers are composed of
four S-R master-slave flip-flops, four AND-OR INVERT
gates, one buffer, and six inverter/drivers.

word select will cause the selection of word 2 (A2, 82,
C2, D2). The selected wq~d is shifted to the output
terminals on the negative·going edge of the clock pulse.

When the word select input is low, word 1 (A 1, 81,
C1, D1) is applied to the flip·flops. A high level input to

Typical clock frequency is 12 MHz.

Connection Diagram

OUTPUTS
Vee

116

15

14

INPUT
1)1

OUTPUT
00

ClOCK

12

11

10

13

,--

9

f-

1

A2

WORD
SELECT

3

2

AI

81

6

5

4

01

82

02

7

D2

P

GND

INPUTS
Word select luw for wotd 1, wilrd select hIgh for word 2, see descnpl1011

54l98/74L98(J). (N), (W)

logic Diagram

(15)

ft.

(14)

1131

(111

ClOCK:,;(I;;OI_ _ _ _ _ _ _ _ _~

> _____....
2-42

0.

Oc

1lo

~

MSI

DM54/0M74L98

Electrical Characteristics

over recommended operating free-air temperature range lunless otherwise noted)
DM54L!74L

PARAMETER

CONDITIONS

VIH

High Level Input Vo1tage

VIL

Low Level Input Voltage

10H

High Level Output Current

VOH

High Level Output Voltage

MAX
V
0_7
-200

Vee

~
~

Min,

V IH

~

2V

0.7V,

I OH

~

-200j1A

Low Level Output Current

Low Level Output Voltage

VOL

TYP(1)

2

V IL
10L

UNITS

198
MIN

Vee
V IL

~
~

DM54

2

DM74

3.6

Min,

V 1H

~

2V

DM54

IOL

~

Max

DM74

'I

Input Current at Maximum Input Voltage

Vee

~

Max,

VI

IIH

High Level I nput Current

Vee

~

Max,

VI~2-4V

IlL

Low Level I nput Current

Vee

~

Max,

VI

lOS

Short Circuit Output Current

Vee

~

Max

Icc

Supply Current

Vee

~

Maxl2)

~

j1A
V

2-4

0.7V,

V

0_15

0.3
0-4

5.5V

mA

V

100

j1A

10

j1A

-0.18

mA

-15

mA

8

mA

~

0.3V
-3

-9
6

Notes
(1)
(2)

~ 5V, TA ~ 2SoC.
ICC is measured with all inputs grounded and all outputs open.

All typical values are at VCC

Switching Characteristics

Vee ~ 5V, TA ~ 25°C
DM54L!74l

PARAMETER

CONDITIONS
MIN

f max

Maximum Clock Frequency

tpLH

Propagation Delay Time, Low-to-High

6

Level Output From Clock
tpHL

CL

~

50 pF, RL = 4 kr2

Propagation Delay Time, High-to·Low
Level Output From Clock

tW(CLOCKI Width of Clock Pulse
tSETUP(HI

tSETUPILI

Setup Time for High-Level Data

Setup Time for Low·Level Data

100
A, 8, C, or D

100

Word Select

150

A, B, C, or D

120

Word Select

100

2-43

UNITS

L98
TYP

MAX
MHz

12
40

80

ns

65

100

ns

65

ns
ns

ns

~ MSI

DM54/DM74lS124
Dual Voltage Controlled Oscillators

General Description
The DM54LS124/DM74LS124 features two fully independent voltage~controlled oscillators (VCO's) in a single
monolithic chip. The output frequency of each is
establ ished by a single external component, either a
capacitor or a crystal, in combination with two voltage·
sensitive inPuts, one for frequency range and one for
frequency control. An enable input is provided that can
be used to start or stop the output pulses when it is
low or high, respectively. The internal oscillator runs
continuously, even while the output is disabled. A pulse
synchronizer ensures that the first output pulse is
neither clipped nor extended. Duty cycle of the output,
pulses is fixed at approximately 50 percent.

The enable input and the buffered output operate at
standard Schottky-clamped TTL levels. The enable input
is tine standard' load in each series. Although these
devices can operate from a single 5·volt supply, separate
supply-voltage and ground pins are provided for the
digital logic and for the oscillator/range control circuits
so that effective isolation can be accomplished in the
system.

Features

The highly stable oscillator can be set to operate at any
frequency between 0.12 Hz and 50 MHz typically. The
output frequency can be approximated as follows:

where: fo
CEXT

~

~

• Two fully independent yeO's in a 16-pin package
• Output frequency set by single external component:
Crystal for high-stability fixed-frequency operation
Capacitor for fixed- or variable-frequency operation
• Separate supply voltage pins for isolation of ,inputs
and oscillators from logic circuitry
• Stable operation over specified temperature and/or
supply voltage ranges

output frequency in MHz
external capacitance in pF

Connection Diagram

Y2
OUTPUT
10

I
I

9
6

J

rl
1
2

2

1 ,

3
RANGE 1

I

'I
~

14
tEXT

1

1

5

Cexrl

FREQUENCY CONTROL

6

7

Yl
lil
ENABLE OUTPUT

el:o

Note: While the enable input is low, the output is enabled. Whil~ the enable input is high,
the output is high.

54LS124/74LS124(J), (N), (WI

TentatIve Data

2-44

To Be Announced In 1976

~

MSI

OM54/0M74LS124

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

DM54
PARAMETER

CDNDITIONS

V,H

High Level Input Voltage at Enable

V,L

Low Level Input Voltage at Enable

V,

Input Clamp Voltage at Enable

10H

High Level Output Current

VOH

High Level Output Voltage

10L

Low Level Output Current

VOL

Low Level Output Voltage

DM74

LS124

LS124

MIN TYP(l} MAX

MIN TYP(l} MAX

2

Vee =- Min, Ij =

Vee

= Min,

~~18

V 1H

=

2

mA

2V, IOH

=

-1.2 mA

2.5

V

0.7

0.8

-1.5

-1.5

V

-1.2

-1.2

rnA

24

rnA

2.7

3.4

Vee

= Min, VENABLE == V 1L IOl = 12 rnA
= Vee (Minj-2V IOL = 24 rnA

0.25

0.4

Freq Control

Input Current

or range

I,

Input Current at Maximum
Input Voltage

I'H

High Level Input Current

I,L

Low Level Input Current

los

Short Circuit Output Current

Icc

Supply Current, Total into

Vee =- Max

Vee

= Max,

Enable

Vee

= Max,

Enable

Vee'" Max, VI

Enable

Vee =- Max,

50

250

50

250

10

50

10

50

1V

JJ.A

0.1

2.7V

20

20

JJ.A

= O.5V

--0.4

--0.4

rnA

-150

rnA

37

rnA

=

VENABLE

= 4.5V(2)

-30

-150
22

Input Voltage at Frequency

V,

V

0.1

Vee = Max(3}

Pins 15 and 16

0.4
0.5

V,
V, = 7V
VI

0.25
0.35

V,=5V
=

V

V

3.4

12

Pins 4 and 13

I,

UNITS

37

0

Control or Range Input

-30
22

5

rnA

5

0

V

Notes
(1) All typical values are at Vee:::: 5V, TA = 25°C.
(2) Not mpre than one output should be shorted at a time and duration of the short circuit should not exceed one second.
(3) ICC is measured with the outputs disabled and open.

Switching Characteristics

Vee = 5V, RL = 667.11,C L =45pF, TA = 25°C

PARAMETER

Output Frequency

I.

C

-2
EXT -

Output Duty Cycle

F
P

iVI(FREQ)

°5V,

VI(FREQJ

OV,

I

Output From Enable

~

TYP

V1(RNGi =

OV

35

50

V1(RNG} -

5V

11

20

CEXT = 8.3 pF to 500llF

50%

fo 21 Hz

30+(4}

Propagation Delay Time, High-ta-Low Level

tPHl

MIN

CONDITIONS

MAX

UNITS
MHz

ns

Notes
(4)

The delay will typically be 30 ns plus up to one half the period of one cycle O.e. 30 ns to 30 ns + 5 x 108 /f o (HZ)) depending upon the timing
of the enable pulse with respect to the signal generated by the internal oscillator.

2-45

~ MSI

DM54/DM74lS138.S138.lS139.S139
Decoders/ Demulti plexers

General Description
These Schottky-clamped circuits are designed to be used
in high-performance memory-decoding or data-routing
applications, requiring very short propagation delay
times_ In high-performance memory systems these decoders can be used to minimize the effects of system
decoding. When used with high-speed memories, the
delay times of these decoders are usually less than the,
typical access time of the memory. This means that the
effective system delay introduced by the decoder is
negligible,

All of these decoders/demultiplexers fe'ature fully
buffered inputs, presenting only one normalized load
to its driving circuit. All inputs are clamped with highperformance Schottky' diodes to suppress line-ringing
and simplify system design.

The LS138 and S138 decode one-of-eight lines, based
upon the conditions at the three binary select inputs
and the three enable inputs. Two active-low and one
active-high enable inputs reduce the need for ,external
gates or inverters when ~xpanding. A 24-line decoder
can be implemented with no external inverters. and a
32-line decoder requires only one inverter, An enable
input can be used as a data input for demultiplexing
applications.

• S138 and LS138 3-to-8-line decoders incorporate
3 enable inputs to simplify cascading and/or data
reception
• S139 and LS139 contain two fully independent
2-to-4-line decoders/demultiplexers
• Schottky clamped for high performance

Features
•

Designed specifically for high-speed:
Memory decoders
Data transmission systems

TYPICAL
TYPE

(3 LEVELS OF LOGIC)
LS138

The LS139 and S139 comprise two separate two-line-tofour-line decoders in a single package. The active-low
enable input can be used as a data line in demultiplexing
applications.

S138
LS139
S139

TYPICAL

PROPAGATION DELAY

POWER DISSIPATION

21 ns

32mW

8 ns

245 mW

21 ns

34mW

7.5 ns

300 mW

Connection and Logic Diagrams
DATA OUTPUTS

YO

116

Y1

15

Y2
14

YO
1)

Y6

11

11

0-

r-

1

•

10

2

3

4

5

6

,~G2_A_~G2_'_ _G~1.1
SELECT

I'

1

OU~~UT

GNO

ENABLE

54LS138174LS138(J), IN), (WI; 74S138(N)

54LS139/74LS139IJ), (N), (W); 74S139(N)

LS138,5138

LS139, S139

DATA
OUTPUTS

DATA
OUTPUTS

A (1)
2Y1
(2)

INPUTS

"'cui

IJI

2-46

To Be Announced In 1976

Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

CONDITIONS

High Level Input Voltage

Vll

Low Level Input Voltage

VI

Input Clamp Voltage

10H

High Level Output Current

VOH

High Level Output Voltage

10l

VOL

LS138, LS139

S138,S139

TYPO)

MAX

MIN

N/A

0.8

0.8

-1.5

-1.2

-400

-1000

2.5

3,4

N/A

V'L = Max, IOH = Max

DM74

2.7

3,4

2.7

V'L = Max

IOL = Max
IOL = 4 mA

V

0.7

DM54

3:

CJ).

MAX

DM74

Vee = Min, V'H = 2V

Vee = Min, V'H = 2\1

UNITS

DM54

Vee = Min, I, = -18 mA

Low Level Output Voltage

TYP(1)

~

2

2

Low Level Output Current

.'".;,.

DM74S

MIN

r

VIH

DM54LS/74LS

V
V
flA
V

3,4

DM54

4

NiA

DM74

8

20

DM54

0.25

0,4

N/A

DM74

0.35

0.5

0.5

rnA

V

0,4

DM74

-..J

II

Input Current at Maximum Input Voltage

IIH

High Level I nput Current

III

Low Level Input Current

lOS

Icc

Short Circuit Output Current

Supply Current

Vee = Max
Vee = Max

Vee:::: Max

V, = 5.5V

1

V, = 7V

0.1

V, = 2,7V

20

V, =O.4V

-{),36
-2
DM54

-30

-130

DM74

-30

-130

N/A
-40

-100

Vcc = Max

LS138,S138

6,3

10

49

74

Outputs Enabled and Open

LS139,S139

6.8

11

60

90

Notes
All typical values are at Vee = 5V. TA = 25°C.
(2) Not more than one output should be shorted at a time, and duration of short circuit should not exceed one second.
(1)

0

50

V, = 0,5V

Vee = Max(2)

rnA
flA

3:
(11

rnA

.......
0

mA

~

3:
'oJ
~

r-

...
en
...
CJ)

rnA

W

(X)

W

(X)

r-

...
...

CJ)

W
CD
CJ)

W
CD

Switching Characteristics vee

~ 5V, T A ~ 25°C
DM54 LS174 LS

FROM
!INPUT)

PARAMETER

TO
(OUTPUT)

LEVELS
OF DELAY

CONDITIONS

LS138
MIN

tPLH

Propagation Delay Time,

Low-ta-High Level Output

DM74S

DM54LSI74LS

MAX

13

MIN

S138

CONDITIONS

LS139

TYP

~

DM74S
S139

TYP

MAX

20

13

20

4.5

7

5

7.5

ns

27

41

22

33

7

10.5

6.5

10

ns

18

27

18

29

7.5

12

7

12

ns

26

39

25

38

8

12

8

12

ns

MIN

MAX

MIN

TYP

UNITS

TYP

MAX

s:

-

CJ)

2
tpHl

Propagation Delay Time,
High-ta-Low Level Output

tplH

Binary

Any

Select

Propagation Delay Time,
l.ow-ta-High Level Out'put

3
tpHL

tpLH

Propagation Delay Time,
High-ta-Low Level Output

CL

Propagation Delay Time,

RL

= 15pF
= 2 krl

CL
RL

low-ta-High Level Output

= 15 pF
= 28012

12

18

16

24

5

8

5

8

ns

21

32

21

32

7

11

6.5

10

ns

17

26

N/A

7

11

N/A

ns

25

38

N/A

7

11

N/A

ns

2
tpHL

Propagation Delay Time,

High-ta-Low level Output
Any

Enable
tpLH

Propagation Delay Time,

Low-ta-High Level Output

3

"".j:,.ex>

tPHL

Propagation Delay Time,

High-ta-Low level Output

0

s:

Truth Tables

(J1

.

~

LS138, S138

.......
0

s:

INPUTS

G1

G2'

OUTPUTS

SELECT

ENABLE
C

B

A

YO

Y1

Y2

Y3

Y4

LS139, S139
Y5

Y6

Y7

INPUTS

~

r'

OUTPUTS

CJ)

X

H

X

H

H

H

H

H

H

ENABLE

X

X
X

H

X

X
X

H

L

H

H

H

H

H

H

H

H

G

B

A

YO

Y1

Y2

Y3

H

L

L

L

L

L

H

H

H

H

H

H

H

L

H

L

H

H

H

H

L

H

H

H

H

H

H

X

H

H

X

L

H

H

H

H

H

H

H

H

H

H

L

L

H

L

L

L

L

L

H

L

H

H

L

L

H

H

H

L

H

H

H

H

H

H

H

H

L

H

L

H

L

H

H

L

H

L

H

H

H

H

H

L

H

L

L

H

L

H

L

L

H

H

H

H

L

H

H

H

H

L

H

L

H

H

H

H

H

H

L

H

H

H

L

H

H

L

H

H

H

H

H

H

L

H

H

L

H

H

H

H

H

H

H

H

H

H

L

'G2 ~ G2A + G2B
H::: High level, L = low level, X :::: don't care

H

=

SELECT

high level, L::: low level, X ::: don't care

"""

to)

00

...
CJ)
to)

00

...

r'.

CJ)
to)

to

...

CJ)
to)

to

~

DM54/DM74147.148

MSI

Priority Encoders

General Description

Features

These TTL encoders feature priority decoding of the
input data to ensure that only the highest-order data line
is encoded. The DM54147 and DM74147 encode nine
data lines to four-line (8-4-21) BCD. The implied
decimal zero condition requires no input condition as
zero is encoded when all nine data lines are at a high
logic level. All inputs are buffered to represent one
normalized Series 54/74 load. The DM54148 and
DM74148 encode eight data lines to three-line (4-2-1)
binary (octal). Cascading circuitry (enable input EI and
enable output EO) has been provided to allow octal
expansion without the need for external circuitry. For
all types, data inputs and outputs are active at the low
logic level.

DM54147, DM74147

..•
..

Encodes 10-1 ine deci mal to 4-line BCD
Applications include:
Keyboard encoding
Range selection
Typical data delay
Typical power dissipation

•

10 ns
225 mW

DM54148, DM74148

•

Encodes 8 data lines to 3-line binary (octal)
Applications include:
N-bit encoding
Code converters and generators
Typical data delay
Typical power dissipation

•

•
•

10 ns
190mW

Connection Diagrams

T

OUTPUT
0

Ne

L5

16

.

INPUTS

,
3

2
13

14

T

1

2

•

6

5

•

3

5

7

8

6

,

INPUTS

INPUTS

,

GS

3

I.

15

,
1

2
13

12

10

11

2

,•

9

0-

1

G!:

OUTPUT

AD

0

r-----,

~

MSI

DM54/DM74150.151A.LS151.S151
Data Selectors/Multiplexers

General Description

Features

These data selectors/multiplexers contain full on-chip
decoding to select the desired data source. The 150
selects one-of-sixteen data sources; the 151 A, LS151,
and S151 select one-of-eight data sources. The 150,
151A, LS151, and S151 have a strobe input which must
be at a low logic level to enable these devices. A high
level at the strobe forces the W output high, and the Y
output (as applicable) low.

•
•
•
•
•

The 151A, LS151, and S151 feature complementary
Wand Y outputs whereas the 150 has an inverted (W)
output only.

L4

'10

23

22

21

E12

Ell
20

E13

19

E14

18

E15

\

A

16

17

8

, E7

3
'5

'6

4
E4

5

6

E3

E2

7

8

10

9

,

11

o

EO STROBE W

'1

LS151

DATA INPUTS

04

05

07

06

14

13

30mW

4.5 ns

225mW

54150/74150

STROBE

13

D

C

B

A

S

X

X

X

X

H

L

L

L

L

L

L

L

H

L

L

L

H

L

L

L

L

H

H

L

L

H

L

L

L

L

H

L

H

L

L

H

H

L

L

L

H

H

H

L

H

L

L

L

L

J,12

H

L

L

H

L

H

L

H

L

L

GNO

H

L

H

H

L

H

H

L

L

L

H

H

L

H

L

E13

H

H

H

L

L

E14

H

H

H

H

L

E15

C

11

10

I-

r--

,03

02

3
01

DATA INPUTS

DO

,

6

5

4
Y

H

EO
El

Ez

E3
E4

E5

E6

-E7
E8
E9

El0

Ell
-

E12

54151A/74151A,54LSI51174LSI51,
74S151

9

INPUTS

2

W

L

SELECT

1

OUTPUT

\

8

A

12

135mW

SELECT

l76
15

200mW

9 ns

INPUTS

DATA SElECT

,

11 ns

12.5 ns

S151

54150(JI. (F); 74150(J), (N), (F)

v

DISSIPATION

150

OUT OATA
SELECT

DATA INPUTS

,

POWER

DATA INPUT TO W OUTPUT

C
14

15

TYPICAL

PROPAGATION DELAY TIME

151A

to-

2

Also for use as Boolean function generator

DATA SElECT

,.....

1

Permits multiplexing from N lines to one line

Truth Tables

DATA INPUTS

'9

Performs parallel·to-serial conversion

TYPICAL AVERAGE

Connection Diagrams
'8

Others select one-of-eight data lines

TYPE

The 151A incorporates address buffers which have
symmetrical propagation delay times through the complementary paths. This reduces the possibility of transients
occurring at the output(s) due to changes made at the
select inputs, even when the 151A outputs are enabled
(i.e., strobe low).

Vee

150 selects one-of-sixteen data lines

W

,

7

STROBE

J:

H

C

B

X
L

OUTPUTS
STROBE

Y

A

S

X

X

H

L

L

L

L

DO

L

L

H

L

01

L

H

L

L

D2

L

H

H

L

D3

H

L

L

L

D4

H

L

H

L

D5

H

H

L

L

06

H

H

H

L

07

W
H

-

DO
01

i52

D3
D4

55
-

06

OJ

= High Level, L = Low Level, X = Don't Care

Eo, E1 ... E15 = the complement of the level of the

OUTPUTS

respectiVe E input
DO, .01 ... 07 = the level of the respective 0 input

54151A(J), (W); 74151A(J), (N), (W);
54LS151174LS151(J), (N), (W); 74S151(N)

2-53

Electrical Characteristics

CONDITIONS

PARAMETER

MIN
VIH

High level Input Voltage

V IL

low level I nput Voltage

Input Clamp Voltage

VI

10H

High level Output Current

V OH

High level Output Voltage

10L

VOL

low level Output Voltage

.

Vee = Min

Input Current at Maximum

High level I nput Current

IIH

low level I nput Current

IlL

los
IcC

Short Circuit Output Current

DM54/74

DM74S

150, 151A

lS151

S151

TYP(l)

MAX

MIN

TYP(1)

0.8

0.7

N/A

0.8

0.8

0.8

-1.5

-1.2

-800
3.4

N/A

V'L = Max, IOH = Max

DM74

2.4

2.7

3.4

2.7

Vee = Max(2)

Supply Current

IOL = Max
IOL =4 mA

16

4·

N/A

DM74

16

8

20

DM54

0.4

0.25

0.4

N/A

DM74

0.4

0.35

0.5

0.5

DM74

(4)

V
/lA
V

3.4

DM54

mA

V

0.4

V, = 5.5V

1

1

V, = 7V

0.1

V, = 2.4V

mA

40

V, = 2.7V

20
-1.6

V, = O.4V

50

-0.4
-2

V, - 0.5V
DM54

-20

-55

-30

-130

DM74

-18

-55

~30

-130

150

40

68

151A

27

48

Others

(3)

-1000

-400
2.5

Vee = Max

V

-1.5

2.4

Vee = Max

(/)

V

DM74

DM54

Vee = Max

s:

MAX

DM54

I, =-18 mA

Vee = Min, V ,H =2V

TYP(l)

UNITS

2

N/A
-100

-40

/lA

mA

0

s:U1
~

........

0

mA

s:

...
:...
...
l>
......r~

~

U1

mA
6

N~tes

(2)

MIN

Vee = Min, V ,H = 2V

Vee = Max(3)

(1)

MAX

2

I, =-12 mA

V,L = Max

Input Voltage

DM54/74

2

low level Output Current

'"

r-

UI'

rJ)
....
UI

....
....
....UI
rJ)

-

------

~ MSI

DM54/DM74150.151A.lS151.S151

Logic Diagrams

150

ISlA. S151

STROBE (9)
(ENABLE)
(B)

EO

-C

p-

>-c

Ft-'

>-;:::::

Ft-'

m

£1

(61

E2

(5)

EJ

~

(4)

E4

>--c
(3)

E5

DATA
INPUTS

~

~
Ft)--:-

SEE ADDRESS BUFFERS BElOW

>--c
(1)

E7

>-c p--(231

E8

(22)

~

(21)

~

(201

~

-

E9

£10

Ell

f=I'"

(19)

E12

(10)

OUTPUT W

~

r;:::::;
ADDRESS BUFFERS FOR 54151A174151A

5----

j

(~

t::r

A

(141

B

(13)

ADDRESS BUFFERS FOR 54lS151174lS151. 74S151

~

1161

E15

DATA
SElECT

B

(BINARY)

B

t

c
(11)

.

C

Ft-'

(17)

A~7nill

SE~~~~ IB

Ft-'

(18)

£14

:

~

(BINARY)

Ell

(BINARY)

~
~

DATA
INPUTS

DATA
SELECT

}f..ASS'CC

(2)

E6

D4(1",8)t=f=f:f$~f3J

D
0

2-56

l ·=~i·illl
B

c

~MSI

DM54/DM74153.LS153.S153
Dual 4-Line to 1-Line Data Selectors/Multiplexel'S

General Description
Each of these data selectors/multiplexers contains inverters and drivers to supply fully complementary,
on-chip, binary decoding data selection to the AND-ORinvert gates. Separate strobe inputs are provided for
each of the two four-line sections.

• Strobe (enable) line provided for cascading (N lines
to n lines)
• High fan-out, low-impedance, totem-pole outputs
TYPICAL AVERAGE
PROPAGATION DELAY TIMES
FROM
FROM
FROM

TYPE

Features
• Permits multiplexing from N lines to 1 line
• Performs parallel-to-serial conversion

Connection Diagram

153
LS153
S153

DATA

STROBE

SELECT

11 ns
14 ns
6 ns

18 ns
19 ns
9.5 ns

20 ns
22 ns

TYPICAL
POWER
DISSIPATION
170mW
31 mW
225mW

12 ns

Truth Table

SELECT
INPUTS

DATA INPUTS

54153(JI, (W); 74153(J), (N), (W);
54LS153/74LS153(J), (N), (W);
74S153(N)

A

CO

Cl

C2

C3

G

V

x

x

x

L

L

L

i..

L

H

L

H

X

L

X

L

H

H

x

H

L

x
x

x
x
x
x
x

H

L

x
x
x

x

L

X

L

L

H

L

X

X

H

X

L

H

H

H

X

X

X

L

L

L

H

H

X

X

X

H

L

H

X

x

L

L

L

H

L

L

L

H

Select inputs A and B are common to both sections.
H = High Level, L = Low Level, X = Don't Care

.....-,

1p,~16",1--------+++

1C1.!!
5!!.,1--------+=:f::t=:t=L...J
DATA 1

1C2.:;14;:..1--'---_-+++i-+-.&..-'
1C3 .f13!L1______+~$$=lJ

___++i_~~r-~

DATA 2

2C2 "'112;;:.I-----"'1=1==t=~-"'\

2C3~11~3Ibf;:==========~~~~r=~
115)

OUTPUT

x

STROBE G1 lH

STROBE G2

STROBE

B

Logic Diagram

2C1~11~1I----

DATA INPUTS

Electrical Characteristics over recommended o'perating free-air temperature range (unless otherwise noted)

PARAMETER

CONDITIONS
MIN

VIH

High level Input Voltage

VIL

low level Input Voltage

Input Clamp Voltage

VI

10H

High level Output Current

VOH

High level Output Voltage

DM54lS/74lS

DM74S

153

lS153

S153

TYP(1)

Vee; Min

VOL

low level Output Voltage

Input Current at Maximum

II

Input Voltage
High level Input Current

IIH

low,level Input Current

III

Short Circuit Output Current

los

Supply Current

ICC

0.7

N/A
0.8

-1.5

-1.2

-1.5

-800
DM54
DM74

2.4
2.4

3.2
3.2

3.4

N/A

3.4

2.7

16
16

DM54

0.2

DM74·
DM74lS

0.2

-1000

-400
2.5
2.7

0.25

0.4
0.4

0.35

V

V

/lA
V

3.4

4

N/A

8

20

0.4
0.5

N/A
0.5

mA

/

V

0.4

Vee; Max

V,; 5.5V
V,;7V

1

V,'; 2.4V

40

Vee; Max(3)

V

0.8

IOL; 4 mA

Vee; Max(2)

MAX

0.8

V'L; Max

Vee; Max

TYP(1)

0.8

DM54

Vee; Max

MIN
2

I, --18 mA

IOL ; Max

MAX

3:
f!!

UNITS

DM54

,

V'H ; 2V

TYP(1)

~

DM74
1,;-12mA

Vee; Min, V'H ; 2V
V'L = Max,l oH ; Max

Vee = Min

MIN
2

DM74

'"81

MAX

2

low level Output Current

10l

DM54/74

1
0.1

V,; 2.7V

20

V,';O.4V

,-1.6

50

-0.36

mA

/lA

C

mA

V, ; 0.5V

3:
en

'-2
DM54

-20

-55

-30

-130

DM74

-18

-'57

-30

-130

DM54

34

52

6.2

10

DM74

34

60

6.2

10

N/A
-40

-100

N/A
45

70

~
.......

0

mA

3:

~
en

mA

~

W
Not_
(1)
(2)

All typical values are at Vcc; 5V, TA; 2SoC.

(3)

ICCl is measured with the outputs open and all inputs grounded.
National Semiconductor temporarily reserves the right to ship'OM54LS/OM74LS153 devices which have a minimum lOS = 5.0 rnA.

(4)

t;....

-

en

Not more than one output should be shorted at a time, and for DM54lS/74LS or DM74S duration of short circuit should not exceed one second.

W

en
....
en

w

.,

-

Switching Characteristics vee = 5V, T A = 25°C

PARAMETER

FROM
(INPUT)

~
DM54/74

DM54 LS/74 LS

DM74S

153

LS153

S153

TO
(OUTPUT)
CONDITIONS

tpLH

Propagation Delay Time,

Low-to-High Level Output
tpHL

Propagation Delay Time,

High-to-Low Level Output
tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,

High-to-Low Level Output
tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-ta-Law Level Output

MIN

TYP

MAX

CONDITIONS

MIN

TYP

MAX

CONDITIONS

MIN

UNITS
TYP

MAX

Data

Y

11

18

10

15

6

9

ns

Data

Y

10

23

17

26

6

9

ns

Select

Y

20

34

19

29

11.5

18

ns

CL
Select

y

Strobe

Strobe

~

C L = 15pF

30 pF

RL = 400Q

s:

V)

C L = 15pF

RL = 2 kQ

RL =28012

20

34

25

38

12

18

ns

y

19

30

16

24

10

15

ns

y

17

23

21

32

9

13.5

ns

N

c:n



0

s:

(J1

~

........

0

s:
~

(J1

w

lV)

...
...

(J1

W

V)

(J1

W
-

_.-

~

MSI

DM54/DM74154,L154A,LS154
4-Line to 16-Line Decoders/Demultiplexers

General Description

Features

Each of these 4-line-to-16-line decoders utilizes TTL
circuitry to decode four binary-coded inputs into one
of sixteen mutually exclusive outputs when both the
strobe inputs, G 1 and G2, are low. The demultiplexing
function is performed by using the 4 input lines to
address the output line, passing data from one of the
strobe inputs with the other strobe input low. When
either strobe input is high, all outputs are high. These
demultiplexers are .ideally suited for implementing,highperformance memory decoders. All inputs are buffered
and input clamping diodes are provided to minimize
transmission-I ine effects and thereby simplify system
design.

•
•
•
•

Decodes 4 binary-coded inputs into one of 16 mutually
exclusive outputs
Performs the demultiplexing func.tion by distributing
data from one input line to anyone of 16 outputs
Input clamping diodes simplify system design
High fan-out, low-i mpedance, totem-pole outputs
TYPICAL

TYPE

TYPICAL

PROPAGATION DELAY
3 LEVELS OF LOGIC

POWER

STROBE·

DISSIPATION

154
L154A

19 ns

18 ns

170mW

55'ns

LS154

23 ns

45 ns
19 ns

24mW
45mW

Connection and Logic Diagrams
Ii.

M

Wo

B
C

0
A

INPUTS

t

A

B

0

C

22

23

21

G2
20

G1
19

,

Gl (lB)

OUTPUTS

15

18

13

14

16

17

62

11

12

15

(4)3

13

14

I--

i

10-

INPUTS

rv

1

2

1

5

4

]

2

]

4

7

6
5

6

9

B

7

8

10
9

A
(6)5

A
B

B(22)

l
e l2l )

,,

(1)5

B

-v

t::~

c
C

~

11 J12
10.

GNO

(5/ 4

C

A (23)

r<

)oELz

•

G

(19)

(2'1

(8/ 7
OUTPUTS
{9)S

Or" ~r(10)9

0

D (20)

I

OUTPUTS

54154(JI. (F); 74154(J), (N), (F);
54L 154A/74L 154A(J), (N), (F);
54LS154/74LSl54(J), (N), (F)

t::l--

D

0

(11)10

(13)11

c

(14) 12

(15)13

B

A

(16)14

A

G
B
C

Tentative Data For LS154

2-60

OJI Is

O~

LS 154 To Be Announced In 1976

Electrical Characteristics

PARAMETER

CONDITIONS
MIN

VIH

High Level I nput Voltage

VIL

Low Level Input Voltage

Input Clamp Voltage

VI

IOH

High Level Output Current

VOH

High Level Output Voltage

'"~

Vee ~ Min

Low Level Output Voltage

IIH

IlL

Input Current at Maximum Input Voltage

High Level Input Current

Vee

Icc

Supply Current

L 154A

LS154(4)

TYP(1)

MAX

MIN

TYP(1)

Vee

~

Min, V ,H

2

Vee

~

Vee

= Max

Max

~

Max

Vee ~ Max(2)

Vee

~

Max(3)

~

5.5V

V,

~

7V

V,

= 2.4V

V,

~

2.7V

V,

~

0.3V

V,

= 0.4V

0.7

O.B

N/A
-1.5
-200

-400

DM54

2.4

3.4

2.4

2.B

2.5

3.5

DM74

2.4

3.4

2.4

2.8

2.7

3.5

DM54

16

2

4

16

3.6

8

DM54

0.25

0.4

0.15

0.3

0.25

0.4

DM74

0.25

0.4

0.20

0.4

0.35

0.5

0.1

1

0.1
40

V

V
IlA
V

DM74

10
20

mA

V

mA

IlA

-0.18
-1.6

-0.36

DM54

-20

-55

-3

--9

-15

-30

-130

DM74

-18

-57

-3

--9

-15

-30

-130

DM54

34

49

4.8

6.0

9

14

DM74

34

56

4.8

6.0

9

14

mA

mA

0
~

(J1
~

.......
0
~
-..J

mA

~
....

(J1
~

!:

Notes
All typical values are at Vee = 5V, TA = 25°C.
(21 Not more than one output should be shorted at a time, and for DM54LS/74LS duration of short circuit should not exceed one second.
(4)

V

O.B
-1.5

~

en

MAX

2

(J1

(1)
(3)

TYP(1)

DM74
mA

V,

MIN

0.7

~-lBmA

= 2V

MAX

UNITS

0.7

~-12

~ Min, V ,H ~ 2V
= Max, IOH = Max

Low Level I nput Current

Short Circuit Output Current

154

-BOO

Vee

loS

DM54LS/74LS

0.8

I,

V'L ~ Max, IOL ~ Max
II

DM54L/74L

DM54

I,

Low Level Output Current

VOL

DM54/74

2

V'L
IOL

~

over recommended operating free-air temperature range (unless otherwise noted)

~

»
ren
....

ICC is measured with all inputs grounded and all outputs open.
Tentative data.

(J1

~
----------

Switching Characteristics vee

~ 5V, TA ~ 25°C
DM54/74

DM54L/74L

DM54 LS174 lS

154

L154A

LS154(4)

PARAMETER
CONDITIONS
tpLH

Propagation Delay Time,

MIN

TYP

MAX

18

36

21

33

CONDITIONS

MIN

TYP

MAX

35

70

75

150

CONDITIONS

MIN

~
UNITS

TYP

MAX

24

36

nS

22

33

ns

s:

C/)

Low~to~High

Level Output, From A, B, C, o-r D Inputs
Through 3 Levels of Logic
tpHL

tpLH

Propagation Delay Time,

High~to~Low

Level Output, From A, 8, C, or D Inputs

CL =15pF

Through 3 Levels of Logic

HL

Propagation Delay Time,

RL

Low~to~High

Level Output, From Either Strobe Input
tpHL

Propagation Delay Time,

High~to~Low

Level Output, From Either Strobe Input

'"0,
'"

CL = 50 pF

=400n

C L = 15pF

= 4 kn

RL

='2kn

17

30

35

70

20

30

ns

18

27

55

110

18

27

ns

Truth Table
INPUTS

OUTPUTS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

G1

G2

D

C

B

A

o~

L

L

L

L

L

L

L

L

L

L

L

H

15

L

L

L

L

H

L

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

L

L

L

L

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

L

L

L

H

L

l

H

H

H

H

L

H

H

H

H

H

H

H

,H

H

H

H

L

L

L

H

L

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

L

L

L

H

H

L

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

L

L

L

H

H

H

H

H

H

If

H

H

H

L

H

H

H

H

H

H

H

H

C

s:C11
01=0

.......
C

s:-...I

L

L

H

L

L

L

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

H

L

L

H

L

L

H

H

H

H

H

H

H

H

H

H,

L

H

H

H

H

H

H

L

L

H

L

H

L

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

L

l

H

l

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

l

l

H

H

l

l

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

01=0

L

l

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

l

l

H

H

H'

l

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

s:
C11

l

l

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

L

H

X

X

X

X

H

H~

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

l

X

X

X

X

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

X

X

X

X

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

...
01=0

C11

01=0

l>
ro-

...

C/)

C11

H = High Level, L;:: Low Level, X = Don't Care

01=0

~ MSI

DM54/DM74155.LS155.156.LS156
Dual 2-Une to 4-Une Decoders/Demultiplexers

General Description

Features

These TTL circuits feature dual 1-line-to-4-line demultiplexers with individual strobes and common binaryaddress inputs in a single 16-pin package .. When both
sections are enabled by the strobes, the common address
inputs sequentially select and route associated input data
to the appropriate output of each" section. The individual
strobes permit activating or inhibiting each of the 4.bit
sections as desired. Data applied to input C1 is inverted
at its outputs and data applied at C2 is true through its
outputs. The inverter following the C1 data input permits
use as a 3-to-8-line decoder, or 1-to-8-line demultiplexer,'
without external gating. Input clamping diodes are
provided on these circuits to minimize transmission-line
effects and simplify system design.

•

Applications:
Dual 2-to-4-line decoder
Dual 1-to-4-line demultiplexer
3-to-8-line decoder
1-t0-8-line demultiplexer

•

Individual strobes simplify cascading for decoding or
demultiplexing larger words

•

Input clamping diodes simplify system design

•

Choice of outputs:
Totem-pole (155, LS1551
Open-collector (156, LS1561

Connection Diagram

Truth Tables
2-LlNE-TO-4-LlNE DECODER
OR 1-LlNE-TO-4-LINE DEMULTIPLEXER
INPUTS
SELECT

OUTPUTS

STROBE

DATA
Cl

B

A

Gl

1Y0

lY2

lY3
H

X

X

H

X

H

H

H

L

L

L

H

L

H

H

H

L

H

L

H

H

L

H

H
H

H

L

L

H

H

H

L

H

H

L

H

H

H

H

L

X

X

X

L

H

H

H

H

INPUTS
SELECT
B
541551J), IW); 741551J), INl.IW);
54LS155174LS155IJ), IN), IW);
5415SIJl. IW); 7415SIJ), IN), IW);
54LS156174LS15SIJ), IN), IW)

lYl

OUTPUTS

STROBE

DATA

A

G2

C2

2YO

2Yl

2Y2

2Y3

X

X

H

X

H

H

H

H

L

L

L

L

L

H

H

H

L

H

L

L

H

L

H

H

H

L

L

L

H

H

L

H

H

H

L

L

H

H

H

L

X

X

X

H

H

H

H

H

Logic Diagram
3-LlNE-TO-8-LlNE DECODER
OR 1-LlNE-TO-8-LlNE DEMULTIPLEXER
INPUTS

Ct

B

X

L

OA~~ ",115..
1 _ _- .

10)

11)

12)

13)

14)

15)

IS)

(7)

A

Gi

X

X

H

H

H

H

H

H

H

H

H

L

L

L

L

H

H

H

H

H

H

H

L

L

H

L

H

L

H

H

H

H

H

H

L

H

L

L

H

H

L

H

H

H

H

H

2YO 2Yl 2Y2 2Y3 1Y0 1Yl lY2 1Y3

L

H

H

L

H

H

H

L

H

H

H

H

H

L

L

L

H

H

H

H

L

H

H

H

H

L

H

L

H

H

H

H

H

L

H

H

H

H

L

L

H

H

H

H

H

H

L

H

H

H

H

L

H

H

H

H

H

H

H

L

tC
STRO~i ",114;;..1_ _- ,

OUTPUTS

STROBE
OR DATA

SELECT

= inputs C1 and C2 connected together

+G == inputs G 1 and G2 connected together
H = high level, L

2-63

= low

level, X

= don't care
LS155, LS156 To Be Announced In 1976

Electrical Characteristics

DM54LS/74LS

DM54174
CONDITIONS

PARAMETER

155
MIN

V ,H

High Level Input Voltage

V ,L

Low Level Input Voltage

Input Clamp-Voltage

V,

TYP(1)

=:

Min

MIN

TYP(1)

MAX

2

MIN

TYP(1)

2

=;

High Level Output Voltage

Vee
V 1L

= Min, V 1H
= Max, IOH

=:;

=:

TYP(l)

0.7

DM74

0.8

0.8

0.8

0.8

-1.5

-1.5
1.5

1.5

Max, V OH

=:

100

250

5.5V

400

2V

DM54

2.4

2.5

3.4

Max

DM74

2.4

2.7

3.4

Low Level Output Current

Low Level Output Voltage

VOL

'"
~

Vee

=:;

Min, V 1H

=:;

2V

V'L = 0.8V
Input Current at Maximum

I,

Vee::: Max

Input Voltage

High Level I nput Current

I'H

I,L

Low Level Input Current

los

Short Circuit Output

Cu~rent

Supply Current

Icc

Vee

= Max

16

16

4

4

16

16

8

8

4 mA

10L - 8 mA, DM74
IOL -16mA

V, = 5.5V

Vee = Max(3)

0.4

1

1

0.4

0.25

0.4

0.35

0.5

0.35

0.5

V, = 2.7V
-1.6

-1.6
DM54

-20

-32

-55

DM74

-18

-32

-55

0.1

0.1

20

20

-0.36

-0.36

40

40

V, = 2.4V

-30

N/A

p.A

mA

0.25

V, = 7V

Vee = Max, V, = O.4V
Vee = Max(2)

0.4

V

V

DM74
=:

V

5.5

DM54

IOL

s:

-en

V

2
0.7

5.5
10L

MAX

0.8

800
VOH

MIN

0.8

18mA

Vee"" Min, V 1H == 2V, V 1l

UNITS

LS156
MAX

DM54

1,=-12mA
I, -

LS155

156
MAX

2

Vee

High Level Output Curren!

IOH

~

over recommended operating free-air temperature range (unless otherwise noted)

,

-130
-130

-30

N/A

DM54

25

35

25

35

6.1

10

6.1

10

DM74

25

40

25

40

6.1

10

6.1

10

V

rnA

0

p.A

s:

rnA

~
.......

mA

s:.....

mA

U1

0

....
U1
~

U1

,...

en
....

Notes
(1)

All typical values are at VCC = SV, T A = 2SoC.

(2)

Not more than one output should be shorted at a time, and for DM54LSJ74LS duration of short circuit should not exceed one second.

(3)

ICC is measured with outputs open, A, B, and C1 inputs at 4_.5V, and C2, G1 and G2 inputs grounded.

..

U1
U1

:...

U1

m
r-

en
....

U1

m
_.

,

Switching Characteristics vcc = 5V, T A = 25°C

~
DM54LSI74LS

DM54/74

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

LEVELS
OF LOGIC

155

CONDITIONS

MIN
tPLH

156

TYP

MAX

13

20

MIN

LS155

CONDITIONS

TYP

MAX

15

23

MIN

LS156

TYP

MAX

10

15

MIN

UNITS

TYP

MAX

25

40

' Propagation
Delay Time,

A, B, C2

Low-to-H igh

Gl or G2

Y

2

Level Output
tPHl

s:

CJ)

ns

-

Propagation
Delay Time,

A, B, C2

H igh-to-Low

Gl or G2

Y

2

Y

3

18

27

19

30

18

27

21

32

19

30

34

51

ns

17

26

31

46

ns

Level Output
tPLH

Propagation

Delay Time,
Low-ta-High

Aor B

Level Output

CL = 15 pF

CL

= 15 pF

= 40011

RL

= 2 kl1

RL

tpHL

Propagation

Delay Time,
High-ta-Low

'"en

A or B

Y

3

17

26

18

27

19

30

34

51

ns

C1

y

3

17

24

19

27

18

27

32

48

ns

Level Output

(J'1

tPLH

Propagation

Delay Time,
Low-ta-High
Level Output
tpHl

0

Propagation

Delay Time,
High-ta-Low

C1

y

3

17

26

18

Level Output

27

18

27

32

48

ns

s:U1
~

........
0

s:

"...
~

U1
U1

r-

....U1

CJ)

U1

:..
U1

O'l

r-

....

CJ)

U1

O'l
--

~ MSI

DM54/DM74157 ,l157A.lS157 ,S157 ,lS158 ,S158
Quad 2-line to 1-line Data Selectors/Multiplexers

General Description

Features

These data selectors/multiplexers contain inverters and
drivers to supply full on-chip data selection to the .four
output gates. A separate strobe input is provided. A
4-bit word is selected from one of two sources and is
routed to the four outputs. The 157, L 157 A, LS157, and
S 157 present true data whereas the LS 158 and S 158
present inverted data to minimize propagation delay time.

•

Buffered inputs and outputs

• Three speed/power ranges available

TYPICAL
PROPAGATION

TYPICAL
POWER

TIME

DISSIPATION

9 ns
40 ns

150mW

TYPE

Applications

157·
L157A
LS157

• Expand any data input point
• Multiplex dual data buses
• Generate four functions of two variables (one variable
is common)
• Source programmable counters

S157

9 ns
5 ns

15mW
49mW
250mW

LS158
S158

7 ns
4 ns

24mW
195mW

Connection Diagrams

STROBE

T
16

,

G

INPUTS
A4

15

INPUTS

B'

I.

13

OUTPUT
V.

OUTPUT

A3

12

B3

11

T

vCC

Y3
10

9

1
SElECT

2

, AI

1

.,

•
VI

6

5
02

82

OUTPUT
INPUTS

,

7

V2
OUTPUT

INPUTS
,,.._......_-,,

G

A4

15

16

s

STROBE

84

14

INPUTS'

OUTPUT
V4

13

,

12

OUTPUT
Vl

BJ

A3

10

11

-

1

J:

3

2
AI

S

4

VI

81

OUTPUT

SElECT

INPUTS

INPUTS

low level at S sefects A inputs
High level at S selec1s B inputs

5

,A2

7

6
82

,

Y2
, OUTPUT

61:

INPUTS
lowlevtl at Sselects A inputs

High level at S selects B inputs

54157(JI, (W); 74157(JI, (NI, (WI;
54L 157A174L 157A(JI, (N), (WI;
54LS157174LS157(JI, (N), (WI; 74S157(NI

54LS158174LS158(JI, INI, (WI;
74S158(NI

Truth Table
INPUTS

OUTPUT Y
i57. L157A
LS157, S157

LS158
S158
H

STROBE

SELECT,

A

B

H

X

x

x

L

L

L

X

L
L

L

L

H

X

H

H
L

L

H

X

L

L

H

L

H

x

H

H

L

H = High Level, L. = Low Level, X = Don't Care

2-66

LS157, LS158 To Be Announced In 1976

~

Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted)
DM54L174L

DM54n4
PARAMETER

CONDITIDNS

V'H

High Level Input Voltage

V'l

Low Level I nput Voltage

V,

IOH

High Level Output Current
High Level Output Voltage

~

I,

Vee"" Min

Low level Output Voltage

= Min,

Vee

V IL

''""

Input Current at

Any Input

Max'imum Input Voltage

S or G Input

-.J

=::

0=

""

High Levell nput Current

Low Level Input Current

2

2
0.8

07

0.7

N/A

0.8

07

0.8

0.8

-1.5

N/A
--1.5

-1.2

ICC

Supply Current

-400

-200

N/A

Max, IOH

'='

Max

DM74

2,4

3.4

2.4

2.7

3.4

2,7

Max

10L

V,
Vee = Max

Vee ""Max

Vee'" Max

Vee ~ Maxl2!

Vee ~ Maxl3!

=4

mA

V,

16

2

4

N/A

DM74

16

36

8

20

DM54

0.4

0.3

0.25

0.4

DM74

0.4

0.4

0.35

0.5

1

0,1

OM74

0.25

~5.5V
~

~2.4V

V,

~

2,7V

V,

~

0,3V

V,

~

OAV

V,

~

0.5V

V

V
/lA

rnA

0.4
N/A
0,5

V

0

1
rnA

0.2

7V

V,

0

40

50

20

50

/lA

(,J1

-0.8

-1.6

-0.4

rnA

-20

DM74

-18

157

30

158

N/A

·-55
'-55

·3

48

-15

-30

-9

-15

-30

3

4

N/A

-130
-130

N/A
--40

-100

9,7

16

50

78

4.8

8

39

61

Notes

'-I

!:;
(,J1

-2
DM54

~

~

'0.18
1.6

~9

(,J1

.......

10

-3

~

~

0.1
40

-

V

3.4

DM54

'-I

mA

mA

l>

i(J)

....
'-I
en....
(,J1

(,J1

'-I

(1)

All typical values are at V CC = 5V, T A ~ 25" c.

(2)

Not more than one output should be shorted at a time, and for the DM54LS/74~S or DM74S duration of the short circuit should not excee.d one second.
ICC is measured with 4.5V applied to all inputs and all outputs open.

(3)

-1000

3.4

~

(J)

V

OM74
-'12 mA

10L ::: Max

UNITS
MAX

OM54

2.5

Min

TYP(1)

2

2.4

Any Input

Short Circuit Output Current

MIN

3,4

Any Input

lOS

S157, S158

MAX

2.4

S or G Input

A or B Input

TYP(1)

OM54

A or B Input
I'L

MIN

2V

Any Input
S or G Input

LS157, LS158
MAX

~

A or B Input

I'H

TYP(1)

DM74S

V 1H

V'H ~ 2V

I,

MIN

1,",-18rnA

Low Level Output Current

VOL

MAX

-800
Vee
V 1L

IOl

TYPI1!

2

Input Clamp Voltage

V OH

L157A

157
MIN

DM54LS/74LS

i(J)

....

(,J1

CO

en
....
(,J1

CO
--

-

_ .. -

-

Switching Characteristics V cc =5V,T A =25°C
DM54L/74L

DM54/74

FROM
(INPUT)

PARAMETER

tplH

Propagation Delay
Time, Low-to-High
Level Output

L157A

157
CONDITIONS

~
158

MIN

DM54 LS/74 LS

TYP

8

MAX

Co'NDITIONS

14

MIN

LS157, LS158
TYP
40

N/A

MAX

CONDITIONS

MIN

80

N/A

~

DM74S
S157, S158

TYP

MAX

CONDITIONS

MIN

UNITS
TYP

MAX

9

14

5

7.5

8

13

4

6

s:

en

ns

Data
tpHL

Propagation Delay
Time, High-to-Low
Level OutPlJt

tPlH

Propagation Delay
Time, Low·to-High

157

10

f--;ss
157

13

f--;ss
Strobe

Propagation Delay
Time, High-to·Low
Level Output
Propagation Delay

tpLH

Time, Low-to-High
Level Output

40

157

20

60

RL

~

CL 0 50 pF

400f!

15

157

23

19

4.5

6.5

13

4

6

16

25

8.5

12.5

14

25

6.5

11.5

RL 02 kf!
60

70

ns

ns

C L 0 15pF
RL

120

N/A

N/A

12

8

C L 0 15pF

RL 04 kf!
21

N/A

f-;58

120

N/A

C L 0 15 pF
14

7s

80

N/A.

N/A

Level Output
tpHL

14

N/A

140

N/A

o

280n

17

27

7.5

12

16

27

7

12

16.5

26

9.5

15

13

20

8

12

19

30

9.5

15

16

24

8

12

ns

ns

,'t;-J
.0>

Propagation Delay

tpHl

Time, High-to-Low

cOO

Level Output

157

f--;ss

17
N/A

27

50

100

N/A

a

s:

Select

(J1

ns

~

'"a
s:

......
~
--'

-

(J1

......

!::
(J1

......

l>
r-

en
--'
(J1

......

en
--'
(J1

......

l-

en
--'
(J1

co

en
...
(J1

co
-

-

~ MSI

OM 54/DM74157 .L157A.LS157. S157 .LS158 .5158

Logic Diagrams
157, L 157A

STROBE US)

L5157

L5158

m

Al

m

8t l31

81

131

A2 (51

A2

151

8Z'S!

"

At

(11)

Al (It)

8l

••

161

AJ

110)

BJ

(14)

(111)

(14)

A4

(O)

84 (13 )

B4

STROBE G /151

STROBE G (1S)

SElECT S

SelECT

{1}

s

(1)

5157

5158
Al

..::12~1-----;==========r-~

8t (3)

A2 (S)

82 (6)

A3 01}

83 (10)

A4 (14)

84(13)

2-69

.~ MSI

OM54/0M14160A.LS160.161A.LS161.162A.LS162.163A,LS163
Synchronous 4-Bit Counters
law level at the clear input sets all faur af the flip-flap
autputs law after the next clack pulse, regardless af the
levels af the enable inputs. This synchronous clear
allows the count length to. be modified easily, as decading
the maximum count desired can be accomplished with
one external NAND gate. The gate autput is connected
to. the clear input to. synchronously clear the counter to.
all law autputs. Low-ta-high transitians at the clear
input af the 162A and 163A are also permissible regardless af the logic levels on the clock, enable, or load inputs.

General Description
These synchronous, presettable counters feature an
internal carry look-ahead for application in high-speed·
counting designs. The 160A, 162A, LS160, LS162, are
decade counters and the 161A, 163A, LS161, LS163
are 4-bit binary counters. The carry outPUt is decoded
by means of a NOR gate, thus preventing spikes during
the normal counting mode of operation. Synchronous
operation is provided by having all flip-flops clocked
simultaneously so that the outputs change coincident
with each other when so instructed by the count-enable
inputs and internal gating. This mode ·of operation
eliminates the output co.unting spikes which are normally
associated with asynchronous (ripple clock) counters.
A buffered clock input triggers the four flip-flops on
the rising (positive-going) edge of the clock input
waveform.

The carry laok-ahead circuitry pravides far cascading
caunters far n-bit synchranous applicatians withaut
additianal gating. Instrumental in accomplishing this
functian are twa caunt-enable inputs and a ripple carry
autput. Bath caunt-enable inputs (P and T) must be
high to caunt, and input T is fed forward to enable the
ripple carry autput. The ripple carry autput thus enabled
will praduce a high-level output pulse with a duration
approximately equal to. the high-level portion af the Q A
output. This high-level overflaw ripple carry pulse can
be used to. enable successive cascaded sfages. High-tolow-level transitions at the enable P ar T inputs af the
160A thraugh 163A ar LS160 through LS163, may
occur regardless af the lagic level an the clack.

These counters are fully programmable; that is, the
outputs may be preset to either level. As presetting is
synchronous, setting up a low level at the Io.ad input
disables the counter and causes the outputs to agree
with the setup data after the next clock pulse regardless
of the levels of the enable input_ Low-to-high transitions
at the laad input af the 160A thraugh 163A ar LS160
thraugh LS163 are perfectly act:eptable, regardless af the
lagic levels an the clack or enable inputs. The clear
function far the 160A, 161A, LS160, and LS161 is
asynchronaus; and a law level at the clear input sets all
faur af the flip-flap autputs law regardless af the levels
af clock, laad, ar enable inputs. The clear functian far
the 162A, 163A, LS162, LS163, is synchranaus; and a

LS160 through LS163 feature a fully independent clack
circuit. Changes made to control inputs (enable P ar T,
laad ar clear) that will modify the aperating made have
no effect until clocking accurs. The functian of the
caunter (whether enabled, disabled, loading, ar caunting)
will be dictated salely by the canditians meeting the
stable setup and hold times.

Features
• Synchranously programmable
• Internallaok-ahead far fast caunting
• Carry output for n-bit cascading
• Synchranaus caunting
• Load cantralline
• Diade-clamped inputs

TYPE

160 thru 163
LS160 thru LS163

TYPICAL PROPAGATION
TIME, CLOCK TO

TYPICAL

TYPICAL

CLOCK

Q OUTPUT

FREQUENCY

POWER
DISSIPATION

14
14

ns
ns

35 MHz
32 MHz

Connection Diagram

I

vCC
16

OUTPUTS

RIPPLE
CARRY
OUTPUT

ENABLE
T

15

13

14

12

LOAD

10

"

54160A(J), (W); 74160A(J), (N), (W);
54LS160/74LS160IJ), (N), (W);
54161A(J), (W); 74161A(J), (N), (W);
54LS161/74LS161 (J), (N.), (W);
54162A(J), (W); 74162A(J), 010, (W);
54LS162/74LS162(J), (N), (W);
54163A(J), (W); 74163A(J), (N), (W);
54LS163/74LS163(J), (N), (W)

1

2

CLEAR

CLOCK

4

3

,

A

B

7

6

5

C

0

,

ENABLE

P

J:

DATA INPUTS

2-70

315mW
93mW

~

OM54/0M74160A.LS160.161A.LS161.162A.LS162.163A.LS163

MSI

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
"

PARAMETER

CONDITIONS

DM54/74

DM54LS/74LS

160A,161A
162A,163A

LS160, LS161
LS162, LS163

UNITS

MIN TVPl11 MAX MIN TYPl11 MAX
V ,H

High Level Input Voltage

V,L

Low Level Input Voltage

V,

Input Clamp Voltage

2

DM74

IOH

High Level Output CUrrent

V OH

High Level Output Voltage

1

I

Vee

=

==

Min, V IH

2V

=

Max, IOH ::: Max

Low Level Output Voltage

Vcc=Min
tOl =

V 1H = 2V

Input Current ax Maximum

All

Input Voltage

Data or Enable P

/

Load, Clock, or Enable T

Clear ILS160, LS1611

Max

i Ol ==4 mA

VI L = Max

I,

0.8

0.8

-1.5

II::: -18 mA

Low Level Output Current

VOL

0.7

-800

V 1L
IOL

0.8

-1.5

1 =--'2 mA
Vee"" Min

V

2

DM54

V,

= 5.5V

VI

=

-400

DM54

2.4

3.4

2.5

DM74

2A

3A

2.7

3A
3A

16

4

DM74

16

8

0.2

DM74

0.2

OA
OA

0.25

DM74

I'H

0.5

0.25

OA

Data

\

Enable P

Clear {160, 1611

0.1
Vcc=Max

0.2

7V

0.2

Vcc=Max

V,
V,

= 2AV
= 2.7V

1160A-163AI
ILS160-LS1631

Data, Enable P
Clock

Load
Enable T

Vee = Max

V, =OAV

"-

Clear 1160, 1611

ICCH

Iccj.-

Supply Current, All Outputs High

Supply Current, All Outputs Low

40

40

80

40

40

20

40

20

40

20

40

40

-1.6

-0.4

-3.2

1.2

-1.6

0.8

-3.2

0.8

-1.6

-{)A

-1.6

Clear 1162, 1631

Short CirCUit Output Current

los

Vee"" Max(2)

Vee::: Max(3)

Vee = Max(4)

-20

-57

-30

-130

DM74

-18

-57

-30

-130

DM54

59

85

18

31

DM74

59

94

18

31

DM54

63

91

19

32

DM74

63

101

19

32

11)

All typical values are at VCC ~ 5V, TA ~ 25°C.

121

Not more than one output should be shorted at a time, and for OM54LS/74LS duration of short circuit should not exceed one second.
ICCH is measured with the load input high, then again with the load input low, with all o~her inputs high and all outputs open.
leel is measured with the clock input high, then again with the clock input low, with all other inputs low and all outputs open .

14)

.~

2-71

pA

mA

-{).8

DM54

Notes

131

mA

0.1

Clear 1162, 1631
Low Level Input Current

I,L

V

1

Load

Clock, Enable T

mA

OA

0.35

Clear {LS162, LS1631
High Level I nput Current

V
pA
V

DM54

DM54

V

mA

mA

mA

~

DM54/DM74160A,LS160,161A,LS161,162A,LS162,163A,LS163

MSI

Switching Characteristics

vcc = 5V, T A = 25° C

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

DM54174

DM54LS/74LS

160A, 161A, 162A, 163A

LS160, LS161, LS162, LS163

CONDITIONS
f MAX

Maximum Clock Frequency

tpLH

Propagation Delay Time,

25

Low-ta-High Level Output
Clock

Propagation Oe.lay Time,

tpHl

MIN TYP MAX CONDITIONS

Propagation Delay Time,

tpHL

Clock

(Loap Input High)

Propagation Delay Time,

tPHl

tpLH

tpHl

Propagation Delay Time,

RL = 40011
Clock
(Load Input Low)

Low-ta-High Level Output

Enable T

Propagation Delay Time',
High-to-Low Level Output

tW(CLOCK)

Width of Clock Pulse

tW(ClEAR)

Width of Clear Pulse

tSETUP

Setup Time

tHOlO

35

ns

16

24

23

35

ns

14

20

16,

24

ns

16

23

18

27

ns

17

25

ns

Clearl5)

RL = 2 kH

14

21

18

25

19

29

ns

10

15

15

23

ns

12

16

15

23

ns -

24

36

26

38

ns

Any Q

Ripple
carry

High-ta-Low Level Output
tpHl

23

CL = 15 pF

High·ta-Low Level Output

Propagation Delay Time,

27

CL =15pF

Propagation Delay Time,

Low-ta-High Level Output

18

Any Q

High-to-Low Level Output
tpLH

MHz

carry

Propagation Delay Time,
Low-to-H igh Level Output

32

Ripple

High-ta-Low Level Output
tpLH

25

35

UNITS

MIN TYP MAX

Any Q

Data Inputs

25

25

ns

20

20

ns

A.B.C.D
Enable P

20

20

20

25

Load

25

25

Clear(6)

20

25

Hold Time at

0

Any Input

0

ns

ns

Notes

(5)

Propagation delay for clearing is measured from the clear input for the l60A, LS160, 161 A and LS161 or from the clock input transition for
the 162A, LS162, 163A and ['S163.

(6)

This applies only for ,162, 163, LS1~2 and LS163, which have synchronous clear inputs.

!

2-72

~MSI

DM54/DM74160A,LS160,161A,LS161,162A,LS162,163A,LS163

Logic Diagrams

160A, LS160

'2'

ClOCK---{;»---'-~======ttjj:~C===]rt
il'

DATAA----...J

111
CLEAR

DATA

'41
8--------++--1++1-1"'\

DATA

C-------H-t1++-t+l-1"'\

DATA

16'
D-------I+++-H+H-1-,

151

162A, LS162 are similar; however,
the clear is svochronousas shown

for the 163A, LS163 binary counters.

163A, LS163

Q,

DATAi.c.31_ _ _ _---'

Q,

171
ENABLEP
Oil}

ENA8LET--r::">--+--~

'"

OATAC-------H~F=:l=I:::j::j:::j::::::f..,

'6161-------+-Wd=UJJ:k~r:;:=~-~

OATAD-

161A, lS161 are similar; however,
the clear isasynchroflousasshown
for 160A, lS160 decade counters.

lJJ:~~~~~~~~~g®=)c

2-73

~MSI

DM54/DM74160A,LS160,161A,LS161,162A,LS162,163A,LS163

Timing Diagrams
160, 162, lS160, LS162 SYNCHRONOUS DECADE COUNTERS
TYPICAL CLEAR; PRESET, COUNT AND INHIBIT SEQUENCES
CLEAR
160A, LS16D

CLEAR
162A,LS162
LOAD

r---f-----.--------------

,----+--,-------------DATA [

:

'--+--'r= _===_========

INPUTS: _ _+----L
ClOCK---+'
160A,lSl11D
CLOCK
162A,LS162

HIIASLEP

---+-+'
ENABlET
---+-+'

RIPPLECARRY _ _ _

OUTPUT

+_+:--l-:-~
a

9

Sequence:
(1) Clear outputs to zero
(2)

Preset to BCD seven

(3)

Count 10 eight, nine, zero, one, two, and three

(4)

Inhibit

I'

0

I

2

3

- - - - - - COUNT----I----INHIBIT - - - CLEAR PRESET

161, LS161, 163, LS163 SYNCHRONOUS BINARY COUNTERS
TYPICAL CLEAR, PRESET, COUNT AND INHIBIT SEQUENCES

CLEAR
161A LS161
CLEAR
163A,lS163
LOAD

r--------------

INDp~ ~ ~~~~~~::~~~~.Lr
==============
,----+--,-------------[ D:'

L _ _ _ _ _ _ _ '_ _ _ _ _ _ _

""'--+---"T- - - - - - - - - - - - - Sequence:
(1) Clear outputs to zero
(2) Preset to binary twelve
{3) Count to thirteen, fourteen, fifteen, zero, one, and two

ClOCK---+'
16lA,LSt61

CLOCK
16lA,LS163
ENABlEP
ENABLET

(4)

--t--+'
--t--+'

'-f~;

-+-+--+--'

OD _ _

RIPPlEOCU~~~~ ---+-+,,:-10,::-,-':":-....,,
---COUNT - - -

---~INHIBIT~.---

CLEAR PRESET

2-74

Inhibit

~ MSI

DM54/DM74160A.LS160.161A.LS161.162A.LS162.163A.LS163

Parameter Measurement Information
SWITCHING TIME WAVEFORMS

CLOCK
INPUT
OV
"lH
(MEASURE AT tN+11
VOH
OUTPUT
D.
VOL

VOH
OUTPUT
DB

OUTPUT

Ilc

VOL

VOH
VOL

VOH
OUTPUT
Do

RIPPLE

VOL
VOH

CARRY
OUTPUT

VOL

Notes:
(A) The input pulses are supplied by a generator having the following characteristics: PRR $. 1 MHz, duty cycle::; 50%, ZOUT
through 1.63A, tr S 10 ns, tf S 10 ns; for LS160 through LS163, tr S 15 ns, tf S 6 ns. Vary PRR to measure fMAX.

J'::l

50n, for 160A

(B)

Outputs DD and carry are tested at t n+l0 for 160A, 162A, LS160, LS162, and at t n+16 for 161A, 163A, LS161, LS163, where tn is the
bit time when all outputs are low.

(C)

For 160A through 163A, VREF = 1.5V; for LS160 through LS163, VREF = 1.3V.

SWITCHING TIME WAVEFORMS
CLOCK INPUT 3 . 0 V - - - - - - - " " \
160A.LS160
161A, LS161
OV _ _ _ _ _ _ _

--.,,'-_J

CLEAR
INPUT

OV -_I-'-_J

LOAD 3.0V
INPUT
DATA INPUTS
A, B, C. AND 0
D OUTPUTS
161A, lS161
Q

,---+=---~;..;::==-------

3.0V

--"1--+=="{

OV-~---r---H·~--'

3.0V --t-----j---t-t,r-"""\
OV
VOH

--:-+:--,--+---{

AAND Q16~~,T~s~~~ VOL --t--+'y---I---*""'

Oa AND Dc

OUTPUTS

16M, lS160

VOH

VOl--j--''-I---I---i--J
3.0V

ENABLE P OR
ENABLE T

--I---+--......j--,-.......

ov ---l--+--:-J-J
VOH----t---~----~~~--+_------~"f,~~

CARRY
VOl----t===~~~~~----+_--------I

CLOCK INPUT

r----------

3.0V

162A, LS162

16JA,lS16J
a OUTPUTS VOH-----t~

163A, LS163
QA AND 00 OUTPUTS
162A, lS162

DB AND

Ilc OUTPUTS

Voc--------......j.-+,------*""'
VOH----...::!,;::;'

162A,lS162

VOl - - - - - - - - - - - - - , - - - - - - - - - - '
Notes:
(A) The input pulses are supplied by generators having the following characteristics: PRR S 1 MHz, duty cycle
through 163A, tr S IOns, tf :0; IOns, and for LS160 through' LS163, tr S 15 ns, tf :0; 6 ns.

(B)

Enable P and enable T setup times are measured at tn+O.

(C)

For 160A through 163A, VREF ~ 1.5V;for LS160,hrough LS163, VREF ~ 1.3V.

2·75

S

50%, ZOUT ~ 50n. For 160A

~ MSI

OM54/0M74164,L164A,LS164
8-Bit Serial In/Parallel Out Shift Registers

General Description

.Features

These S-bit shift registers feature gated serial inputs and
an asynchronous clear. A low logic level at either input
inhibits entry of the new. data, and resets the first
flip-flop to the low level at the next clock pulse, thus
providing complete control over incoming data. A high
logic level on either input enables the other input,
which will then determine the state of the first flip-flop.
Data at the serial inputs may be changed while the
clock is high or low, but only information meeting the
setup requir,ements will be entered. Clocking occurs on
the low-to-high level transition of the clock input. All
inputs are diode-clamped to minimize transmission-line
effects.

•

Gated (enable/disable) serial inputs

•

Fully buffer~d clock 'and serial inputs

•

Asynchronous clear

Connection Diagram

TYPE

TYPICAL
CLOCK FREQUENCY

TYPICAL
POWER DISSIPATION

36 MHz
14 MHz
36 MHz

185mW
30mW
80mW

164
L164A
LS164

Timing Diagram

LS

ClEARLJ
OUTPUTS

G,

I"

13

12

CLEAR

G,

"

10

CLOCK

•

9

SERIAL {

A

INPUTS

-l----.J
CLOCK

l-

r-

I

2

J

----...-...SERIAL INPUTS

G,

A

,

4

5

,

I'

GND
OUTPUTS

OUTPUTS

~".l.- - -l-~

-, ----'-_ _ _ _ _ _r
--I I
0,_-,--,
, - -~

QG:~I

541641JI, (WI; 74164(JI, (NI, (WI;
54L 164A/74L 164A(JI, (NI, (WI;
54LS164/74LS164(JI, (N), (WI

____________________________________

OH:'~,

I

~1

__ ____________________________________

CLEAR

~

L--

I

~~

I

CLEAR

logic Diagram

2-76

LS164 To Be Announ'ced In 1976

~

Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted)

CONDITIONS

PARAMETER

MIN
V IH
VIL

High Level Input Voltage
Low Level Input Voltage

High Level Output Current

V OH

High Level Output Voltage

10L

VOL

.:..,

'"

los
Icc

Short Circuit Output Cu'rrent

Supply Current

TYP(l)

MAX

MIN

TYP(l)

DM54

0.8

0.7

DM74

0.8

0.7

-1.5

N/A

V

3.2

2.4

2.5

3.5

2.4

3.2

2.4

2.7

3.5

Vee = Max

10L = Max
10L

=

Vee = Max

0.7
0.8

-400

-200

2.4

Vee=Mm

V, = 5.5V

8

2

4

DM74

8

3.6

8

DM54

0.2

0.4

0.3

0.25

0.4

DM74

0.2

0.4

0.4

0.35

0.5

0.25

0.4

Clear

1

0.2

Other

1

0.1

IlA

mA

V

mA

Clear

40

20

Other

40

10

IlA

V, = 2.7V

All

V, =0.3V, L164A

Clear

-1.6

-0.36

--{).4

V, = O.4V, Others

Other

-1.6

-0.18

-0.4

Vee = Max(2)

V

0.1

All

V, = 2.4V

V

V

DM54

DM74

4 mA

s:VJ

MAX

2

2

DM54

High Level I nput Current

Low Level I nput Current

MIN

DM74

Vee = Max

IlL

MAX

UNITS

-1.5

V, = 7V
IIH

TYP(1)

V'L = Max, 10H = Max

Input Current at Maximum
Input Voltage

LS164

Vee = Min, V'H = 2V

VIL=Max

II

L164A

-400

V'H = 2V

N

164

1,--18mA

Low Level Output Current

Low Level Output Voltage

DM54 LS/74 LS

1,=-12mA
Vee = Min

10H

DM54L/74L

2

Input Clamp Voltage

VI

DM54/74

20

DM54

-10

-27.5

-3

DM74

-9

-27.5

-3

Vee = Max(3)

37

54

'-9
-9
6

-15

-30

-130

-15

-30

-130

9

16

27

0

s:

(11

mA

~
......

mA

s:--.J

mA

0

...
~

0'1

~

!:
0'1

Notes

~

(1)

AI! typical values are at Vee = 5V, T A = 25°e.

(2)

Not more than one output should be shorted at a time, and for DM54LS/74LS duration of short circuit should not exceed one second.

(3)

ICC is measured with outputs open, serial inputs grounded, the clock input at 2.4V, and a momentary ground, then 4.5V, applied to clear.

'r!>

...VJ

0'1
~

-

----

~

Switching Characteristics vee = 5V, T A = 25°C

tpHl

Propagation Delay Time,
RL

= 800rl for the 164

RL

= 4 krl for the L 164A

RL

= 2 krl for the LS164

From Clear Input
Propagation Delay Tim~,
Low-to-High Level Outputs
From Clock Input
tpHl

Propagation Delay Time,
High-to-Low Level Outputs
From the Clock Input

tw
"l

164

L164A

LS164

TYP

25

36

MAX

24

36

C L = 50 pF

28

42

C L = 15pF

8

17

27

C L = 50 pF

10

20

30

C L = 15pF

10

21

32

C L = 50 pF

10

25

37

Width of Clock or Clear

MIN
6

C L ='15pF

Input Pulse

..:J

DM54LS/74LS

MIN
C L = 15 pF

Maxirnum Clock Frequency

High,to,Low Level Outputs

tplH

DM54L!74L

CONDITIONS

PARAMETER

f MAX

DM54/74

TYP

MAX

MIN

TYP

25

36

14

75

120

50

85

90

135

20

60

40
20

UNITS

s:

en

MAX
MHz

24

36

17

27

21

32

ns

ns

ns

20

ns

15

ns

5

ns

00

tSETUP

Data Setup Time

15

40

tHOlD

Data Hold Time

5

20

-

-5

0

s:

Truth Table

U1
~

......
H = High level (steady state), l = low level (steady state)

OUTPUTS

INPUTS

X

= Don't Care

t

=

(any input, inciuding transitions)

CLEAR

CLOCK

A

B

OA

De

L

X

L

L

L

X
X

L

H

X
X

GAO

QBO

OHO

H

t
t
t

H

H

H

0AO, aBO, 0HO = The level of 0A, 0B, or 0H, respectively,
before the indicated st,eady-state input conditions were

OAn

OGn

established.

L

X
l

L

OAn

OGn

QAn, 0Gn

L

OAn

OGn

transition of the clock; indicates a one-bit shift.

H
H

X

,-,

OH

Transition from low to high level

=

The level of QA or QG before the most recent t

0

s:....

..
~

en
~

!:=

en
~

»
r-

en
...
en
~

'

~ MSI

DM54/DM74165.L165A
8-Bit Pararallel In/Serial Out Shift Registers

General Description
parallel inputs are loaded directly into the register on a
high-to-Iow transition of the shift/load input, regardless
of the logic levels on the clock, clock inhibit, or serial
inputs.

These are B-bit serial shift registers which shift the data
in the direction of Q A toward Q H when clocked. Parallelin access is made available by eight individual direct data
inputs, which are enabled by a low level at the shift/load
input. These registers also feature gated clock inputs and
complementary outputs from the eighth bit.

Features

Clocking is accomplished through a 2-input NOR gate,
permitting one input to be used as a clock-inhibit
function. Holding either of the clock inputs high inhibits
clockil)g, and holding either clock input low with the
load input high enables the other clock input. The
clock-inhibit input should be changed to the high level
only while the clock input is high. Parallel loading is
inhibited as long as the load input is high. Data at the

•
•

Complementary outputs
Direct overriding load (data) inputs

•
•

Gated clock inputs
Parallel-to-serial data conversion
TYPICAL FREQUENCY

TYPE

TYPICAL
POWER DISSIPATION

165

20 MHz

200mW

L165A

14 MHz

30mW

Connection Diagram
PARALLEl INPUTS
,,..----"----~,

CLOCK
INHIBIT

A

15

10

11

12

13

14

SERIAL OUTPUT
INPUT
OH

-

2

1

4

3

SHIFT! CLOCK
LOAQ

,

E

1

6

5

G

F

H

,

OUTPUT

I'

GND

QH

PARALLEl INPUTS

54165(J), (W); 74165(J), (N), (W);
54L 165A/74L 165A(J), (N), (W)

Truth Table
INPUTS
PARALLEL

SHIFT!
LOAD

CLOCK
INHIBIT

CLOCK

=

OUTPUT
QH

A .. . H

QA

a. .. h
X

a

b

h

DAD

DBa

D HO

DGc

QB

L

X

X

H

L

L

X
X

H

L

t

H

X

H

D Ac

H

L

1

L

L

G AC

DGc

H

H

t

X

X
X

D AO

D BO

OHO

H "" High Level (steady state). L
X

SERIAL

INTERNAL
OUTPUTS

::=;

Low Level (steady state)

Don't Care (any input, including transitions)

t = Transition from low-ta-high level
a.
h = The level of steady-state input at inputs A through H, respectively.
GAO. aBO, 0HO = The level of QA. OS. or 0H, respectively, before the indicated steady-state
input conditions were established.
QAn, QGn = The level of QA or aG, respectively before the most recent t transition of the clock.
T

2-79

~

\

MSI

DM54/DM74165.L165A

Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted I
DM54/74
CDNDITIONS

PARAMETER

MIN
V IH

High Level Input Voltage

Vll

Low Level Input Voltage

VI

Input Clamp Voltage

10H

High Level Output Current

VOH

High Level Output Voltage

Vee'" Min,

Input Current at Maximum Input Voltage

High Level Input Current

V 1H

VII_ =Max,

IOH == Max

V
0.7

-1.5

'"

2V

Short Circuit Output Current

N/A

V
pA

2.4

V

DM54

16

2

DM74

16

3.6

V 1H

:.

2V

DM54

0.2

0.4

0.3

JOl

= Max

DM74

0.2

0.4

0.4

Vee'" Max,

V, o5.5V

Vee'" Max,

Vee == Max,

V! = 2.4V

1

0.1

80

30

40

10

V, 0 0.3V for L165A

-3.2

'0.54

VI == O.4V for 165

-1.6

-0.18

Vee o Maxl2)

Supply Current

2.4

DM54

-20

--55

-3

-9

-15

DM74

-18

-55

-3

-9

-15

40

Ve,c 0 Maxl3)

V

-200

Min,

==

Load tnput

Other Inputs

Icc

MAX

V1L=Max,

Load Input

Other Inputs

los

UNITS

TYP(1)

2

I, 0 -12 rnA

Vee'" Min,

Vee

II

Low Level I nput Current

MIN

··800

IIH

III

L165A
MAX

'0.8

Low Level Output Voltage

VOL

TYPI1)

2

Low level Output Current

10l

DM54L/74L

165

9.5

63

rnA

V
rnA
pA

mA

mA
rnA

Notes
(1)

All typical values are at Vce ~ 5V, T A ~ 25"C.

(2)

Not more than one output should be shorted at a time.

(3)

With the outputS open, clock inhibit and shift/load at 4.5V, and a clock pulse applied to the clock input, ICC is measured first with the
parallel inputs at 4.5V, then with the parallel inputs grounded.

Switching Characteristics

Vce ~ 5V, TA

PARAMETER

FROM
(INPUT)

= 25°C
DM54/74

TO
(OUTPUT)
CONDITtONS

fMAX

Maximum Clock Frequency

tPlH

Propagation Delay Time,

14

Propagation Delay Time,

Propagation Delay Time,
low-to-High Level Output
Clock
Propagation Delay Time,
CL 0 15 pF
R L 0400£2

Propagation Delay Time,
Low-to-High Level Output
H

tpHl

Propagation Delay Time,

Propagation Delay Time,
H

Propagation Delay Time,

50

44

88

ns

42

60

62

124

ns

26

40

35

70

ns

35

50

50

100

ns

33

66

ns

RL 04 kn

25

40

36

50

56

112

ns

25

40

33

66

ns

36

50

56

112

ns

OH

High-to·Low Level Output

-

34

QH

Low-ta-High Level Output
tPHl

MHz

14

CL 050 pF

High-ta-Low Level Output
tPlH

6

TYP MAX

Any

High-ta-Low Level Output
tPlH

20

MIN

Any

High-to·Low Level Output

tPHl

CONDITIONS

,-

Load

tPlH

UNITS

l165A

MIN TYP MAX

Low-to-High Level Output
tPHl

DM54 Lt14L

165

tWlclOCKI

Width of Clock Input Pulse

35

25

100

ns

tWllOAOI

Width of Load Input Pulse

35

24

100

ns

tSETUP

Parallel Input Setup Time

25

10

44

22

tSETUP

Serial Input Setup Time

40

23

44

22

tHOLD

Hold Time at Any Input

5

2-80

10

ns
ns
ns

~ MSI

OM54iOM74165,L165A

Logic Diagram

PARALLEL INPUTS

191

{7)

Timing Diagram
TYPICAL SHIFT, LOAD, AND INHIBIT SEQUENCES

r.LOCK

ClOCKINHISIT

+ ___________________

SERIALINPUT _ _ _" -_ _ _

SHIFT,LOAD

-U

:~~--~-------------------OATA

OUTPUT OM

I

I-----INHIBIT

----1---------------

LOAD

2-81

SERIAL SHIFT

~----.-----­

OUTPUT01-t

_
OUTPUT OK

~ MSI·

OM54/0M74166
8- Bit Parallel In/Serial Out Shift Registers

General Description
These parallel-in or serial-in, serial-out shift registers
. feature gated clock inputs and an overriding clear input.
All inputs are buffered to lower the drive requirement~
to one normalized Series 54/74 load, and input clamping
diodes minimize switching transients to simplify system
design. The load mode is established by the shift/load
input. When high, this input enables the serial data input
and couples the eight flip-flops for serial shifting with
each clock pulse. When low, the parallel (broadside) data
inputs are enabled and synchronous loading occurs on
the next clock pulse. During parallel loading, serial data
flow is inhibited. Clocking is accomplished on the low·to-

Connection Diagram

SHIFT/

INPUT

OUTPUT

LOA[)

H

01-/

I"

14

15

Truth Table

PARALlEL INPUTS

PARALLEL
Vee

11

12

9

10

Io

,

,

3

PARAllEL INPUTS

SHIFT!

CLOCK

LOAD

INHIBIT

L

x

H

X

CLEAR

6

CLOCK

7

CLOCK

I'

GNO

INH1BlT

INTERNAL
PARALLEL

OUTPUTS

OUTPUT

OH

CLOCK

SERIAL

X

x

x

X

L

L

L

L

L

X

X

QAO

0 80

OHO

A ...

/"i

QA

.Os

H

L

L

t

X

a .. ,h

a

b

h

H

H

L

t

H

X

H

OAn

QGn

H

H

L

X

L

QAn

°On

X

H

t
t

L

H

X

X

QAO

aBO

°HO

H = High level (steady state). l
5

o,

SERIAL
INPUT

INPUTS

CLEAR

13

r-

1

high-level edge of the clock pulse through a two-input
NOR gate, permitting one input to be used as a clockenable or clock-inhibit function. Holding either of the
clock ·inputs high inhibits clocking; holding either low
enables the other clock input. This allows the system
clock to be free-running, and the register can be stopped
on command with the other clock input. The clockinhibit input should be changed to the high level only
while the clock input is high. A buffered, direct clear
input overrides all other inputs, including the clock, and
sets all flip-flops to zero.

= low level

(steady state)

X"" Don't Care (any input, including transitions)

t =- Transition from

low to high level

a ... h == The level of steady-state input at inputs A through H, respectively.
QAO. 0SO. 0HO == The level of QA,

aS or QH, respectively, before the

indicated

steady-state input conditions were established.
0An, QGn == The level of QA or 0G, respectively, before the most recent t transition-

54166174166(J), (N)

of the clock

Logic Diagram

(9)

(1)

(l5)

CLEAR SERIAL SHIFT!

(2)
A

13)
8

(4)

c

(5)

(10)

o

PARAllEl INPUTS

2-82

{t2)

(11)

E

INPUT 'LOAD

F

G

(14)

H

",h

CLOCK CLOCK
INHIBIT

~

MSI

DM54/DM74166

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
DM54/74

PARAMETER

CONDITIONS

166
MIN

V IH

High Level Input Voltage

V IL

Low Level Input Voltage

VI

Input Clamp Voltage

10H

High Level Output Current

V OH

High l.evel Output Voltage

~

I,

Min,

VOL

l.ow Level Output Voltage

II

-12 mA

0.8

V

-1.5

V

Vee.~

V'H ~ 2V

Min,

Vee

~

IOH

Min,

~

2.4

-8001lA

V

V'H = 2V

V'L ~ 0.8V,

IOL

Vee ~ Max,

V,

~

IlA

16 mA

16

mA

0.4

V

Input Current at Maximum
Input Voltage

~

IIH

High Level Input Current

Vee

IlL

Low Level Input Current

Vee = Max,

lOS

Short Circuit Output Current

Icc

~

V

-800

V'L ~ 0.8V,
Low Level Output Current

UNITS
MAX

2

Vee

10l

TYP(1)

Supply Current

~

5.5V

V,~2.4V

Max,

V,

Vee

~

Max(2)

Vee

~

Max(3)

~

O.4V

1

mA

40

IlA

-1.6

mA

DM54

-20

-57

DM74

-18

-57

DM54

72

104

DM74

72

116

mA

mA

Notes
All typical values are at vee = 5V, T A = 25°C.
(2) Not more than one output should be shorted at a time.
(3) With all outputs open, 4.5V applied to the serial input, all other inputs except the clock grounded, ICC is measured after a momentary ground,
then 4.5V, is applied to dock.
(1)

Switching Characteristics

Vee = 5V, T A = 25°C
DM54/74

PARAMETER

f MAX

Maximum Clock Frequency

tpHl

Propagation Delay Time, High-to-Low

CONDITIONS

TYP

25

35

tpHL

Propagation Delay Time, High-to-Low

~

MHz
35

ns

8

20

30

ns

8

17

26

ns

15 pF, RL = 400n

Level Output From Clock
tplH

MAX

23

Level Output From Clear
CL

UNITS

166
MIN

Propagation Delay Time, Low-to-High
Level Output From Clock

tw

Width of Clock or Clear Pulse

20

ns

tSETUP

Mode Control Setup Time

30

ns

tSETUP

Data Setup Time

20

ns

tHOLD

Hold Time at Any Input

0

ns

2-83

~ MSI

DM54/DM74166

Timing Diagram
TYPICAL CLEAR, SHIFT, LOAD, INHIBIT, AND SHIFT SEQUENCES
CLOCK

~lOCK

INHIBIT

CLEAR
SERIAL INPUT

SHIFT/LOAD

PARALLEL
INPUTS

----...1

ouTPUT fiH .::::........:..._ _ _ _ _ _ _ _ _ _ _ _

I

CLEAR

I - - - - - - - - - S E R I A L SHIFT - - - - - - - - I I I - - ' O H I 8 I T - I
LOAD

1------- SERIAL SHIFT-----~

Parameter Measurement Information
VOL TAGE WAVEFORMS

3.0V----..
CLEAR
INPUT

OV----~-'----'

CLOCK
INPUT

DATA

OV
3.0V-----,-------~-r-_+'

INPUT
(SEE TEST TABLE)

ov ---'---l-------~
VDH - - - - - - , .

OUTPUT

n
VDL--------~-------------J

Notes
(A) The clock pulse has the following characteristics: tW(clock) 2: 20 ns and PRR
tW(clear)

=

1 MHz. The clear pulse has the following characteristics:

2: 20 ns and tHOLD = 0 ns. When testing fMAX, vary the clock PRR.

fB)

CL includes probe and jig capacitance.

(C)

All diodes are 1N3064.

(0) A clear pulse is applied prior to each test.
(E) Propagation delay times (tPLH and tpH L) are measured at t n +1- Proper shifting of data is verified at tn+8 with a functional test.
(F) tn = bit time before clocking transition
t n+1 = bit time after one clockin~ transition
tn+8 "" bit time after eight clocking transitions
TEST TABLE FOR SYNCHRONOUS INPUTS
DATA INPUT
FOR TEST

SHIFT/LOAD

H

OV

Serial Input

4.5V

2·84

OUTPUT TESTED
(SEE NOTE EI
QH

at

tn+1

Q H at t nt-8

~ MSI

DM54/DM74lS168.lS169
Synchronous 4-Bit Up/Down Counters

General Description
These synchronous presettable counters feature an
internal carry look-ahead for cascading in high·speed
counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously, so
that the outputs all change at the same ti me when so
instructed by the count-enable inputs and internal gating.
This mode of operation helps eliminate the output
counting spikes that are normally associated with
asynchronous (ripple clock) counters. A buffered clock
input triggers the four master-slave flip-flops on the
rising edge of the clock waveform.

output thus enabled will produce a low-level output
pulse with a duration approximately equal to the high
portion of the Q A output when counting up, and approximately equal to the low portion of the Q A output
when counting down. This low-level overflow carry
pulse can be used to enable successive cascaded stages.
Transitions at the enable P or T inputs are allowed
regardless of the level of the clock input. All inputs are
diode clamped to minimize transmission-line effects,
thereby simplifying system design.
These counters feature a fully independent clock circuit.
Changes at control inputs (enable p. enable T, load,
up/down), which modify the operating mode, have no
effect until clocking occurs. The function of the counter
(whether enabled, disabled, loading, or counting) will be
dictated solely by the conditions meeting the stable
setup and hold ti meso

These counters are fully programmable; that is, the
outputs may each be preset either high or low. The load
input circuitry allows loading with the carry-enable
output of cascaded counters. As loading is synchronous,
setting up a low level at the load input disables the
counter and causes the outputs to agree with the data
inputs after the next clock pulse.

Features

The carry look-ahead circuitry permits cascading counters
for n-bit synchronous applications without additional
gating. Both count-enable inputs (i> and T) must be low
to count. The direction of the count is determined by
the level of the up/down input. When the input is high,
the counter counts up; when low, it counts down. Input
T is fed forward to enable the carry output. The carry

•

Fully synchronous
programming

1,6

RIPPLE
CARRY
OUT

OUTPUTS
f

0.

15

14

Dc

Os

13

12

,

00

11

ENABLE

T

LOAD

10

9

0-

1

uti!

3

2
CLOCK

,A

for

• Internal look-ahead for fast counting
• Carry output for n-bit cascading
• Fully independent clock circuit

Connection Diagram

Vee

operation

4
B

5
C

DATA INPUTS

54LS16Sn4LS168(J). (N). (W):
54LS169174LS169(J), (N), (W)

2-85

7

6
D;

ENABLE

P

J:

counting

and

~

DM54/DM74LS168,LS169

MSI

Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted)
OM54LSf74LS16B, LS169
CONDITIONS

PARAMETER

V'H

High Level Input Voltage

V"

Low Level Input Voltage

TYP(l)

Input Clamp Voltage
High Level Output Current

VOH

High Level Output Voltage

V

2
DM54

0.7

DM74

0.8

Vee = Min, V 1H

co

2V

-1.5

DM54

2.5

3,4

DM74

2.7

3,4
4

Low Level Output Voltage

Vee = Min
V 1H "'- 2V

V1L=Max
Input Current at

A, B,C, D,

Maximum Input Voltage

ClocK, T

ii,

110L = 4 rnA

0.25

0,4

0.35

0.5

V
1.loL=BmA,

DM74

0.1

UfO

0.2 ,

Vee = Max, VI = 7V

A; B,C, 0, P, UfO
Clock, T

20
40

Vee "- Max, VI = 2.7V

Low Level Input Current

-0,4

A, 8, C, 0, P, UfO
T

Vee = Max, VI

'CO

-0.8

OAV

los

Short Circuit Output Current

Vee = Max(2)

Icc

Supply Current

Vee = Max(3)

Notes (1)

All typical values are at Vee

=;

mA

-1.2

Load ,Clock

,

MA

60

Load
"l

mA

0.3

Load
High Level Input Current

mA

8

OM74

"H

V
MA

V

OM54

Low Level Output Current

I,

V

--400

V 1L = Max, IOH = ·-400j4A

VOL

UNITS

MAX

Vee'" Min, II "" -18 rnA

V,
,IOH

10l

MIN

-30
20

-130

mA

34

mA

5V, TA = 25°C.

(2)

Not more than one output should be shorted at a time, and duration of short circuit should not exceed one second.

(3)

ICC is measured after applying a momentary 4.5V, then ground, to the clock input with all other inputs grounded and the outputs open.

Switching Characteristics V cc =5V,T A =25°C
FROM
(INPUT)

PARAMETER
f MAX

Maximum Clock Frequency

tPLH

Propagation -Delay Time.

TO
(OUTPUn

DM54LS174LS168, LS169
CONDITIONS

MIN

TYP

25

-32

Low·to-High Level Output
Clock
tpHL

Propagation Delay Time,

Propagation Delay Time,
Low-to-High Level Output
Propagation Delay Time,

C L ""15pF,RL. "'2k£2,

High-to-Low Level Output
tPLH

Propagation Delay Time,
Low-to·High Level Output
Enable

tpHL

Propagation Delay Time,
High-to-Low Level Output

tPLH

Propagation Delay Time,

tpHL

Propagation Delay Time,

T

tW(ClOCK)

Width of Clock Pulse (High or Low)

tSETUP

Setup Time

25

A, B,C, 0

35

ns

13

20

ns

15

23

ns

10

15

ns

16

23

ns

17

25

ns

19

29

ns
ns

20

Enable P or T

Notes (4)

23

Ripple Carry

High-to-Low Level Output

Hold Time

ns

-

Up/Down (4)

tHOLD

35

Ripple Carry

Low-to-High Level Output

Data Inputs

MHz

23

Any Q

Clock
tpHL

UNITS

Hipple Carry

High -to-Low Level Output
tpLH

MAX

25

Load

25

Up/Down

30

Data Inputs A, B, C, 0

0

Enable P or T

0

Load, Up/Down

0

ns

ns

Propagation delay time from up/down to ripple carry must be measured with the counter at either a minimum or a maximum count.
As the logic level of the up/down input is changed, the ripple carry output will follow. If the count is minimum (0), the ripple carry
output transition will be in phase. If the count is maximum (9 for LS168 or 15 for LS169), the ripple carry output will be out of phase.

2-86

~MSI

DM54/DM74LS168,LS169

Logic Diagrams
LS168 DECADE COUNTERS

......

_ 110)

ENABLE T

T

(7)

EN-ABLE Ii

I

(9)

I

LOAQ
(2)

v

~

~~

CLOCK

(1)

U/i!

'7
(3)

DATA A

..J

r~

~

.-L
PR

RIPPLE
CARRY
OUTPUT

(14)

Q

CLOCK

in
(4)

DATA B

>---<"ft

..J

n

41

':f)

~

~
PR

(13)

Q

~rc

G,

CLOCK
CLR [j

f---<

'--, ,.-

--C CLOC~
CLR :0

'--, c -

-

n

~

~

(6)

OATA 0

J

~

~

t-f

.("7"""-

PR

trJ,....rc

CLR

A~

Len
2~87

"

ClOCI{

G

'-- ,..-

':-T

L-=o

1-

(11)

GD

OM 54/ OM74lS168, lS169
. Logic Diagrams (Continued)
LS169 BINARY COUNTERS
ENABLE f (101

ENABLE P

LOAD

-"

I

(11

(91

I

I

(2)

~~

(IS) RIPPLE

CARRY

4

OUTPUT

r-'

CLOCK

(I)

UIO

.~
(31

DATA A

~

~

nR

~

~

~
~

b"P-r-<

+.

(13)

G,

G

CLOCK
CtR

ii

-<

--r
-l

+
0

CLOCK
ClR

-"



-r

(12)

0

i!

(111

~ MSI

DM54/DM74LS168,LS169

Timing Diagrams
LS168 DECADE COUNTERS
TYPICAL LOAD, COUNT, AND INHIBIT SEQUENCES

LOAD

'---.J

A

L

DATA
INPUTS

CLOCK

j> ANOl'

Go

---,

RIPPLE----r--H--.,

OCUAT~~~ ___ .J

II

1

I II..

··----COUNTUP----.I--INHIBIT-I

'--.,.---'
LOAD

Sequence:
(1) Load (preset) to Beq seven
(2)

Count up to eight, nine, zero, one and two

(3)

Inhibit

(4)

Count down to one, zero, nine, eight and seven

2-89

I-----COUNT DOWN - - - - -

~ MSI

DM54/ DM74 LS168, LS16 9

Timing Diagrams (Continued)
LS169 BINARY COUNTERS
TYPICAL LOAD, COUNT, AND INHIBIT SEQUENCES

lOAOL-j

A

...----l...-I L_

--.J

B----F-

OATA
INPUTS

L_

CLOCK

PANOI

G.

--..,

Go _ _

RIPPLE-

O~~~~;

-

--1

--r---H---.

-1

'3

I

I

14

152-1

I·I-·----COUNTUP---~·-II-·-INHIBIT-__I

LOAD

Sequence:
(1) Load (preset) to binary thirteen
(2)

I

Count up to fourteen, fifteen, zero, one and two

(31

Inhibit

(4)

Count down to one, zero, fifteen, fourteen and thirteen

2-90

15

14

13

.1-,----COUNT DOWN ---~-

~MSI

OM54/0M74170.LS170
4 by 4 Register Files

General Description

typical) and the read time (25 ns typical). The register
file has a nondestructive readout in that data is not lost
when addressed.

These 16-bit TTL register files are organized as 4 words
of 4 bits each, and separate on-chip decoding is provided
for addesssing the four word locations to either write-in
or retrieve data. This permits writing into one location
and reading from another word location, simultaneously.

All 170 inputs and all inputs except the read enable and
write enable of the LS 170 are buffered to lower the drive
requirements to one standard load. Input-clamping
diodes minimize switching transients to simplify system
design. High-speed, double-ended AND·OR-INVERT
gates are employed for the read-address function and
drive high-sink-current, open-collector outputs. Up to
256 of these outputs may be wire-AND connected for
increasing the capacity up to 1024 words. Any number
of these registers may be paralleled to provide n-bit
word length.

Four data inputs are available to supply the 4-bit word
to be stored. Location of the word is determined by the
write-address inputs A and B, in conjunction with a
write-enable signal. Data applied at the inputs should be
in its true form. That is, if a high-level signal is desired
from the output, a high level is applied at the data input
for that particular bit location. The latch inputs are
arranged so that new data will be accepted only if both
internal address gate inputs are high. When this condition
exists, data at the 0 input is transferred to the latch
output. When the write-enable input, Gw , is high, the
data inputs are inhibited and their levels can cause no
change in the information stored in the internal latches.
When the read-enable input, GR , is high, the data outputs
are inhibited and 'remain high.

Features

This arrangement-data entry addressing separate from
data-read addressing and individual sense line-eliminates
recovery times, permits simultaneous reading and writing,
and is limited in speed only by the write time (30 ns

• Separate addressing permits simultaneous reading and
writing
typically 20 ns
• Fast access times
• Organized as 4 words of 4 bits
• Expandable to 1024 words of n-bits
• for use as:
Scratch-pad memory
Buffer storage between processors
Bit storage in fast multiplication designs
• Open-collector outputs with low maximum off-state
current:
170
LS170
• DM54LS670 and DM74LS670 are similar but have
TRI-STATE outputs

Connection Diagram

~

The individual address lines permit direct reading of
data stored in any four of the latches. Four individual
decoding gates are used to complete the address for
reading a word. When the read address is made in conjunction with the read-enable signal, the word appears
at the four outputs.

Vr

OUTPUTS

OATA
01
14

"

16

QZ

Qt
12

13

'11

"

9

74170(J), (N);
54LS170/74LS170(J), (N), (W)

-

4

o.

03

•

~

DATA

READ
SELECT

~ .1:
OUTPUTS

Truth Tables
WRITE TRUTH TABLE (SEE NOTES A, B, AND C)
WRITE INPUTS

READ TRUTH TABLE (SEE NOTES A AND' D)

WORD

READ INPUTS

OUTPUTS

WB

WA

Gw

0

1

2

3

RB

RA

GR

01

Q2

03

Q4

L

L

L

O"D
00

Do

00

L

L

L

WOBl

WOB2

WOB3

WOB4

O"D

Do
Do

Do

L

H

L

W1Bl

W1B2

W1B3

W1B4

Do
Do
Do

Do
Do
Do

O"D

00

H

L

L

W2Bl

W2B2

W2B3

W2B4

Do
Do

O"D

H

H

L

W3Bl

W3B2

W3B3

W3B4

Do

x

X

H

H

H

H

H

L

H

L

H

L

L

H

H

L

X

X

H

Notes
(A) H

(B)
(C)

= High

Level, L

= Low Level, X = Don't Care

(Q = 0) = The four selected internal flip~flop outputs will assume the states applied to the four external data inputs.

00 = The level of Q

before the indicated input conditions were established.

(D) WOBl = The first bit of word 0, etc.

2-91

LS170 To Be Announced In 1976

Electrical Characteristics

~.

over recommended operating free·air temperature range (unless otherwise noted)

PARAMETER

CONDITIONS
MIN

VIH

High level Input Voltage

VIL

low level Input Voltage

VI

Input Clamp Voltage

DM74

DM54 lS/74 lS

170

lS170

TVP(1)

MAX

2

MIN

TVP(1)

UNITS

~

fJ)

MAX
V

2

I

DM54

/

DM74

IOH

High level· Output Current

V OH

High level Output Voltage

IOL

Low Level Output Current

VOL

low level Output Voltage

~

Min

Vee

~

Min, V ,H

Vee

~

II

Input Current at

Any

Maximum Input Voltage

Any D, R, orW

Min, V ,H

~

2V, V ,L

~

,

IIH

High level Input Current

V,
Vee

~

Max

G A or Gw

2V

Low Level Input Current

Any D, R,orW
G A or Gw

Icc

Supply Current

~

~

-1.5
Max, V OH

10l

~

4 rnA

10l

~

Max

~

5.5V

20

!J-A

5.5

5.5

V

DM54

N/A

4

DM74

16

8

DM74
DM54
DM74

0.2

5.5V

0.25

0.4

N/A

0.25

0.4

0.4

0.35

0.5

rnA

V

1
0.1

V, =7V

~

Max

rnA

Vee

~

Max, V,

Vee

~

Max(2)

40
20

V, =2.7V

!J-A

40

=0.4V
127

-1.6

--0.4

-1.6

--0.8

150

25

Notes
(1) All typical values are at Vee =5V, T A ~ 25°C.
(2)

V

30

V, = 2.4V
Vee

G A or Gw
IlL

0.8

V

0.2

Any
Any_D, R, or W

0.8

1,~-18mA

V'l ~ Max

'"cO
'"

0.7

-1.5

1,~-12mA

Vee

N/A

ICC is measured under the following worst-case conditions: 4.5V is applied ,\0 all data inputs and both enable inputs, all address inputs are grounded, and all outputs are open.

40

rnA
rnA

0
~

(11

~

.......
0

~
.....
~
.....

...
...
.....
0
r-

fJ)

0

Switching Characteristics

FROM
(INPUT)

PARAMETER

TO
(OUTPUT)

Propagation Delay Time, Low-to-High Level Output

tpHL

Propagation Delay Time, High-ta-Low Level Output

Read Enable
tpLH

Propagation Delay Time, Low-to-High Level Output

tpHL

Propagation Delay Time, High-ta-Low Level Output

tpLH

Propagation Delay Time, Low-ta-High Level Output

Read Select

tPLH

Propagation Delay Time, Low-ta-High Level Output

tpHL

Propagation Delay Time, High-ta-Low Level Output

tw

Width of Write-Enable or Read-Endble Pulse

tSETUP Setup Times, High- or
Low-Level Datal31

Data Input With Respect to
Write ~nable,

LS170
MAX

TYP

MAX

15

20

30

20

30

20

30

23

35

25

40

15pF

30

40

C L =15pF

24

40

RL = 400Q

25

40

RL = 2 kQ

34

45

MIN

Write Enable,

0---....---1·

2-9B

5174, S175 To Be

Annou~ced

In 1976

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

CONDITIONS
MIN

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

Input Clamp Voltage

IOH

High Level Output Current-

VOH

High Level Output Voltage

IOl

VOL

II

I'H

IlL

Vee

=

Min

i

MAX

MIN

TYP(l)

DM74

0.8

0.8

0.8

-1.5

-1.2

-400

V 1L

DM74

2.4

2.7

3.5

Max

High level Jrlput Current

10L = 4 rnA

=:

Max

16

4

N/A

16

8

20

DM54

0.4

0.25

0.4

N/A

DM74

0.4

0.35

0.5

0.5

1
0.1

V, =2.4V

50--

20

V,=O.4V

-1.6

-0.4

-1.6

--0.36

Vee = Max(3)

-20

-57

-30

-130

DM74

-18

-57

-30

-130

174, S17 4
175, LS175, 5175

~

IlA

0

~
r - - - - -..I
~

N/A

--100

-40

45

65

16

26

90

144

30

45

11

18

60

96

-..I

~

r-

-2
DM54

Ul

-'

- - - - - -----

!-*Hi

~

mA

mA

V, = 0.5V

Supply Current

V

'-

40

~27V

Vee = Max(2)

mA

0

1

Clock, Clear

Short Circuit Output Current

IlA

0.4

V,=7V

Vee = Max

V

-- ----

DM74

DM74

V

V

3.4

DM54

V, = 5.5V

Vee = Max

Vee

IOL ,;:: Max

-·1000
N/A
2.7

~

(J)

V
N/A

3.5

~

MAX

-1.5

Low Level Output Voltage

Input Current at Maximum Input Voltage

TYP(1)

2

2.5

Vee = Min, V'H = 2V

MIN

UNITS

0.7

2.4

=:

MAX

2

DM54

Max, IOH

S174,5175

0.8

Vee = Min, V'H = 2V
""

DM74~

DM54

I, =-18mA

Any

ICC

TYP(l)

-800

Data

lOS

LS174, LS175

1,=-12mA

Low Level Output Current

Low Level I nput Current

174, 175

I

V 1L = Max

'"cbCD

DM54LS/74LS

2

VI

DM54/74

(J)
-'
rnA

mA

-..I
~

(J)
-'

-..I
~

:..
Notes
(1) All typical values are at VCC = 5V, TA = 25°C.
(2) Not more than one output should be shorted at a time, and for OM54LS/74LS and DM74S duration of short circuit should not exceed one second.
(3) With all outputs open and 45V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5V applied to clock.
(4) National Semiconductor temporarily reseJves the right to ship DM54LS/DM74LS174. LS175 devices which have a minimum lOS = 5.0 mAo

-..I

Ul

i(J)
-'

-..I

Ul
(J)
-'

-..I

Ul
------

Switching Characteristics

Vee

= 5V, T A = 25°C

~

PARAMETER

DM54/74

DM54LS/74LS

DM74S

174, 175

LS174, LS175

S174, S175

CONDITIONS

f MAX

Maximum Clock Frequency

tpLH

Propagation Delay Time,

MIN

TYP

MAX

CONDITIONS

40

30

MIN

TYP

30

40

MAX

CONDITIONS

s:

UNITS

MIN

TYP

75

110

rJ)

MAX
MHz

-

Low-to-High Level Output

16

25

23

35

25

20

25

23

14

25

20

30

14

17

10

15

ns

13

22

ns

30

8

12

ns

35

11.5

17

ns

From Clear (175 Only)
tPHL

CL = 15 pF

Propagation Delay Time, High-toLow Level Output From Clear

tplH

= 400Q

RL

Propagation Delay Time, Low-toHigh Level Output From Clock

tpHL

Propagation Delay Time, High-toLow Level Output From Clock

tw

Pulse Width

CL

= 15 pF

RL

= 2 kQ

C L = 15 pF
RL

= 280Q

Clock

20

20

7

Clear

20

20

10

Data Input

20

20

5

Clear Inactive-State

30

25

5

0

5

3

ns

':"

o
o

tseTUP Setup Time

tHOLD

Data Hold Time

+:-

........
ns

1:1

s:-.J

+:....
-.J

?

Truth Table

ns

0

s:CJ1

+:r-

(Each Flip-Flop)

....-.J
rJ)

,

INPUTS

OUTPUTS

H = High Level (steady state)
L = Low Level (steady state)
X = Don't Care

CLEAR

CLOCK

D

a

at

L
H

X
t
t
L

X

L

H

t :::; Transition from low to high level

H

H

L

00

H

H

L

L

H

X

00

00

t

,

=

The level of Q before the indicated steady-state input
conditions were established.

= 175, LS175, and S175 only

+:-

....-.J

rJ)

+:-

~

-.J
CJ1

r-

....
-.J
rJ)

CJ1

rJ)
....

~,

-

-_ ... _ - - -

~MSI

DM54/DM74176.m .196.LS196.197.LS197
Presettable Decade and Binary Counters

General Description
These high-speed counters consist of four doc coupled,
master-slave flip-flops which are internally interconnected
to provide either a divide-by-two and a divide-by-five
counter (176, 196) or a divide-by-two and a divide-byeight counter (177, 197)_ These counters are fully
programmable; that is, the outputs may be preset to any
state by placing a low on the count/load input and
entering the desired data at the data inputs_ The outputs
will change independent of the state of the clocks_

are required_ Flip-flop A is used as a binary
element for the divide-by-two function_ The clock2 input is used to obtain binary divide-by-five
operation at the as, Oc, and 00 outputs. I n this
mode, the two counters operate independently;
however, all four flip-flops are loaded and cleared
simultaneously.

,

177, 197 AND LS197

During the count operation, transfer of information to
the outputs occurs on the negative-going edge of the
clock pulse_ These counters feature a direct clear which,
when taken low, sets all outputs low regardless of the
state of the clocks_

The output of flip-flop A is not internally connected to
the succeeding flip-flops; therefore the counter may be
operated in two independent modes:
1. When used as a high-speed 4-bit ripple-through
counter, output OA must be externally connected
to the clock-2 input_ The input count pulses are
applied to the clock-1 input_ Simultaneous divisions by 2, 4, 8, and 16 are performed at the OA'
as, Oc, and 00 outputs as shown in the truth
table.

These counters may also be used as 4-bit latches by
using the count/load input as the strobe and entering
data at the data inputs_ The outputs will directly follow
the data inputs when the count/load is low, but will
remain unchanged when the count/load is high and the
clock inputs are inactive_

2. When used as a 3-bit ripple-through counter, the
input count pulses are applied to the clock-2 input.
Simultaneous frequency divisions by 2, 4, and 8
are 'available at the as, Dc, and 00 outputs.
Independent use of flip-flop A is available if the
load and clear functions coincide with those of
the 3-bit ripple-through counter.

TYPICAL COUNT CONFIGURATIONS 176, 196
AND LS196
The output of flip-flop A is not internally connected to
the succeeding flip-flops; therefore, the count may be
operated in three independent modes:
1. When used as a BCD decade counter, the clock-2
input must be externally connected to the OA
output_ The clock-1 input receives the incoming
count, and a count sequence is obtained in accordance with the BCD count sequence truth table_

Features
• Performs BCD, bi-quinary, or binary counting
• Fully programmable
• Fully independent clear input
• Output OA maintains full fan-out capability in
addition to driving clock-2 input

2_ If a symmetrical divide-by-ten count is desired
for frequency synthesizers (or other applications
requiring division of a binary count by a power of
ten). the 00 output must be externally connected
to the clock-1 input_ The input count is then
applied at the clock-2 input and a divide-by-ten
square wave is obtained at output OA in accordance
with the bi-quinary truth table_

TYPE

176,177
196,197
LS196, LS197

3_ For operation as a divide-by-two counter and a
divide-by-five counter, no external interconnections

Connection Diagram

TYPICAL
COUNT FREQUENCY
CLOCK 2
CLOCK 1
50MHz
50MHz
40MHz

25 MHz
25 MHz
20 MHz

TYPICAL
POWER
DISSIPATION
150mW
240mW
80mW

DATA INPUTS

CLEAR
13

~

DD
12

D

11

B

10

Do
9

CLOCK
1
B

54176(J); 74176(J), (N); 54177(J); 74177(J), (N);
54196/74196(J), (N); 54LSl96/74LS196(J), (N), (W);
54197/74197(J), (N); 54LS197174LS197(J), (N), (W)

1

COUNTI
LOAD

3
C

4
A

~

DA

CLOCK
2

DATA INPUTS

Note: low input to clear sets QA. Ga. Ilc and QD ,lOW.

2-101

LS196, LS197 To Sa Announced In 1976

Electrical Characteristics

DM54/74
CDNDITIDNS

PARAMETER

176,177
MIN

VIH

High Level Input Voltage

Vll

Low Level Input Voltage

~nput

VI

IOH

High Level Output Current

High Level Output Voltage

I,

Vee
V tH

;::

,""

Input Current at

Data, Count/Load

Maximum Input Voltage

Clear. Clock 1

Clock 2

o

2V

0;;;:

;::

Min

Vee;;:; Max, VI

High Level Input Current

::=

5.5V

0.8

0.8

0.7

0.8

0.8

0.8

-1.5

-1.5

-800

--400

DM54

2.4

3.4

2.4

3.4

2.5

3.4

DM74

2.4

3.4

2.4

3.4

2.7

3.4

DM54

16

16

4

DM74

16

16

8

0.5
0.2

I

0.4

0.2

1

1

0.1

1

1

0.2

176,196

1

1

0.4

177,197

1

1

0.2
20
40

176,196

120

80

177,197

80

80

40

Data, Count/Load

-1.6

-1.6

-0.36

Clear

-3.2

-3.2

-0.72

Vee == Max, VI

Short Circuit Output Current

2.4V

Supply Current

= D.4V
176,196

Vee = Max(4)

!lA

mA

-4.8

-4.8

-2.4

-6.4

-2.8

DM54

-20

-57

DM74

18

-fJ7
30

48

-57

-30

-130

18

57

-30

-130

54

rnA

C

s:
U1
~

!lA

"C

s:

...
~

-.J

mA

-1.3

3.2
-20

39

V

-.J

-4.8
3.2

177,197

Vee = Max(2)

V

0.4

40

Clock 2

V

0.4

80

=

-

V

80
120 .

Vee;:: Max, VI

s:

en

V

2

40

Clock 1

Icc

UNITS

MAX

DM74

tOL - 16 mA

V, = 2.7V (LSI96, LS197)

lOS

TYP(l)

IOL - 8 rnA, DM74

Clock 2
Low Level Input Current

MIN

DM54

Data, Count/Load
Clear, Clock 1

III

LSI96, LS197
MAX

~.~4mA

2V

'"
IIH

TYP(1)

-1.5

Max, IOH == Max

V'L = Max(3)
II

MIN

-800
Vee;;:; Min, V tH

Low Level Output Voltage

~

196,197
MAX

18 rnA

Low Level Output Current

VOL

DM54LS174LS

2

1,=-12rnA

Vee;:: Min

V tL

IOL

TYP(1)

2

Clamp Voltage

VOH

~

over recommended operating free-air temperature range (unless otherwise noted)

16

27

rnA
rnA

en

~
-.J

:...
e.g

en
r-

...en
...en
:"'I
en
...re.g

Notes
(1)

All typical values are at V CC ~ 5V, T A = 25" C.

(2)

Not more than one output should be shorted at a time, and for DM54LS/74LS duration of short circuit should not exceed one second.
QA outputs are tested at specified IOL plus the limit value of I, L for the c1ock~2 input. This permits driving the clock-2 input while maintaining full fan-out capability.
ICC is measured with all inputs grounded and all outputs open.

(3)

(4)

e.g

e.g
-.J

Switching Characteristics vee = 5V, TA = 25°C

~

DM54!74
FRDM
(INPUT)

PARAMETER

f MAX

Maximum Input Count Frequency

tpLH

Propagation Delay Time,

TO
(OUTPUT)

Clock 1

OA

Clock 1

OA

176,177
CONDITIONS

MIN
35

Low-ta-Hlgh Level 9utput
Propagation Delay Time,

tpHL

High-ta-Low Level Output

Low-ta-High Level .output
Clock 2
Propagation Delay Time,

tpHl

196,197
MAX

50

MIN

TYP

40

50

LS196
MAX

CONDITIONS

MIN
30

TYP

LS197
MAX

40

MIN
30

TYP

UNITS
MAX

s:

en

MH,

40

9

13

9

13

8

15

8

15

m

11

17

11

16

13

20

14

21

ns

12

18

12

18

16

24

12

19

ns

14

21

14

21

22

33

23

35

ns

27

41

24

36

38

57

34

51

ns

34

51

28

42

41

62

42

63

ns

12

18
55

78

63

95

°B

High-ta-Low level Output
Propagation Delay Time,

tPLH

Low-ta-High Lf;vel Output

Clock 2

Oc

Propagation Delay Time,

tPHL

High-ta-Low Level Output

CL

Propagation Delay Time,

tpLH

176,196

Low-ta-High Level Output
Clock 2

Propagation Delay Time,

tpHL

High-ta-Low Level Output

o

w

TYP

Propagation Delay Time,

tPI.H

~

DM54LS!74LS

°D

=

15 pF

C L =15pF

RL "400Q

~

~

13

20

14

21

44

66

36

54

RL "2 krl(5)

ns

17

26

16

23

50

75

42

63

19

29

16

24

20

30

18

27

ns

31

46

25

38

29

44

29

44

n5

29

43

22

33

27

41

26

39

ns

32

48

24

36

30

45

30

45

ns

30

45

ns

0

Propagation Delay Time,

tpLH

Low-ta-High Level Output
A, B, C, D

Propagation Delay Time,

tpHL

QA, Os· Oc,

aD

High-to-Low Level Output
Propagation Delay Time,

tpLH

Low-to-High Level Output
lJOad
High-to-Low Level Output
Propagation Delay Time,

tpHL

High-to-Low Level Output
Pulse Width

tw

tHOLD

Input Hold Time

Clear

Any

32

48

25

37

34

51

34

14

14

20

20

Clock-2 Input

2B

28

30

30

Clear

25

25

15

15

Load

20

20

20

20

High-Level Data

tW(lOAD)

tW(LOAD)

tW(LOAO)

tW(lOAO}

Low-Level.Data

tW(LOAO}

tW{LOADl

tW(LOADl

tW(LOAD}

High-Level Data

15

10

10

10

Input Setup Time

tENABLE

Count Enable Time(6)

Low-Level Data

s:

..
~
~

en

Clock-' Input

tsETUP

~

'0
~

Any

Propagation Delay Time,

tpHL

s:C1I

20

15

15

15

25

30

20

20

51

Notes
(5)

Load circuit, input conditions, and vol_tage waveforms are the same as those for the 176, 177 except that for the LS196, LS197 tr ~ 15 os, tf ~ 6 ns, and VREF = 1.3V (as opposed to 1.SV).

(6)

Count enable time is the interval immediately pr-eceding the negativeiJoing edge of the clock pulse during which interval the count/load and clear inputs must both be high to ensure counting.

ns

~
~
~
~

ns

to

en

..
r-

en

ns

ns

to

en

~

to

..
~

ns

r-

en

to
~

~ MSI

DM54/DM74176.177.196.LS196.197.LS197

Truth Tables

176.196, LS196

176,196, LS196

DECADE (BCD)
(See Note A)

BI-QUINARY (5-2)
(See Note B)

OUTPUT

COUNT
00

H

COUNT

ac aB aA

(See Note A)

OUTPUT

aA

00

ac as

OUTPUT

COUNT
00

Oc

as aA

0

L

L

L

L

0

L

L

L

L

0

L

L

L

l

1

L

L

L

H

1

L

L

L

H

1

L

L

L

H

2
3

L

L

H

L

2

L

L

H

L

2

L

L

H

L

L

L

H

H

L

L

H

H

3

L

L

H

H

4

L

H

L

L

L

H

L

L

4

L

H

L

L

5

L

H

L

H

3
4
5

H

L

L

L

5

L

H

L

H

6

L

H

H

L

L

L

H

6

L

H

H

L

L

H

H

H

6
7

H

7

H

L

H

L

7

L

H

H

H

8
9

H

L

L

L

L

H

H

8

H

L

L

L

L

L

,H

8
'9

H

H

H

H

L

L

9

H

L

L

H

10

H

'L

H

L

11

H

L

H

H

= High

Level, L

= Low

Level

Notes:
(A)
(8)

177,197, LS197

Output QA connected to clock 2 input.
Output QD connected to clock 1 input.

12

H

H

L

L

13

H

H

L

H

14

H

H

H

L

15

H

H

H

H

w

w

Logic Diagrams
196, LSl96

197, LS197

~MSI

DM54/DM74180
9-Bit Parity Generators/Checkers

General Description
These universal 9-bit (8 data bits plus 1 parity bit)
parity generators/checkers feature odd/even outputs and
control inputs to facilitate operation in either odd or
even parity applications. Depending on whether even
or odd' parity is being generated or checked, the even or
odd inputs can be utilized as the parity or 9th-bit input.
The word·length capability is easily expanded by
cascading.

Input buffers are provided so that each data input
represents only one normalized series 54/74 load. A full
fan·out to 10 normalized series 54/74 loads is available
from each of the outputs at a low logic level. A fan-out
to 20 normalized loads is provided at a high logic level
to facilitate the connection of unused inputs to used
inputs.

Connection Diagram

Truth Table

INPUTS

vee

JI'

13

11

12

'"

8

9

INPUTS
OF H', AT
EVEN
A THRU H

~

-

r--

I

2

•

3

5

6

EVEN

000

l.>EVEN

I-ODD

INPUT

INPUT

OUTPUT

OUTPUT

OUTPUTS
ODD

L

L

EVEN

ODD

EVEN
000
EVEN
ODD

H

L

H

L

H

L

L

H

L

H

L

H

L

H

H

L

X

H

H

L

L

X

L

L

H

H

H "" High Level, L = Low Level, X :; Don't Care

17
GND

INPUTS

54180(JI. (WI; 74180(JI, IN I, (WI

Logic Diagram

.!LJ
A~~
:~II"I
o

LEVEN
OUTPUT

1111

DATA
INPUTS

E~1121~

F

(131

::: 000
OUTPUT

G~

H.EL.j

I~~~~I~'I----------------------------------~
1~~~~~1",31

____________________________________....

2-105

~

MSI

DM54/DM74180

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
DM54/74

PARAMETER

CONDITIONS

V,H

High level Input Volt.age

V,L

Low Level Input Voltage

V,

Input Clamp Voltage

10H

High Level Output Current

VOH

High level Output Voltage

10L

Low Level Output Current

VOL

Low Level Output Voltage

o.a

Vee::: Min, V 1H

I,

Input Current at Maximum Input Voltage

I'H

High Level Input Current

Any Data Input

-800pA

Vee"" Min, V 1H

""'

2V

=::

=::

O.8V,

tOL '"

Vce

Supply Current

~

V

'-1.5

V

-800

}1A

2.4

V

16 mA '

Max, VI = 5.5V

1.6

rnA

0.4

V
rnA

1
40

pA

80
-1.6

Vee =Max, VI =DAV

Short Circuit Output Current

Icc

2V

~

Vee::: Max, VI"" 2.4V

Even or Odd Input

los

~

=

O.aV,loH

Vee

Any Data Input
Even or Odd Input

Low Level Input Current

V

Vee'" Min,ll == -12 mA

V!L

I,L

MAX

2

V'l

-

UNITS

180
TYPO)

MIN

rnA

3.2

Max(2)

Vee"" Max(3)

DM54

-20

-55

DM74

-18

-55

DM54

34

49

DM74

34

56

rnA

rnA

Notes

= 25'C.

(1)

All typical values are at VCC = 5V, T A

(21

Not more than one output should be shorted at a time.
ICC is measured with even and odd inputs at 4.5V, all other inputs and outputs open.

(31

Switching Characteristics Vcc = 5V, TA = 25°C
DM54fl4
PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

CONDITIONS

tpLH

Propagation Delay Time.
Low-ta-High Level Output

Data
tpHL

tpLH

High-ta-Low Level Output

Cl

Propagation Delay Time,

Odd Input Grounded

~

Propagation Delay Time,

Propagation Delay Time,

Low-to-High Level Output
Data
tpHL

tpLH

High-ta-Low Level Output

CL " 15pF, Rl

Propagation Delay Time,

Even Input Grounded

Propagation Delay T,ime,

Propaga.tion Delay Time,
Low-to-High Level Output
Even or Odd

tpHL

45

68

ns

32

48

ns

25

38

ns

32

48

ns

25

38

ns

40

60

ns

45

68

ns

13

20

ns

7

10

ns

L Odd

High-to-Low Level Output
tpLH

ns

~400fl

Low-te-High Level Output
tpHl

60

}; Even

Propagation De,lay Time,

Data

40

L Odd

High-ta-Low Level Output
tPlH

MAX

15 pF, R l " 400n

Low-ta-High' Level OutP4t
tpHL

TYP

LEven

Propagation Delay Time,

Data

UNITS

180
MIN

L Even or L Odd

Propagation Delay Time,
High-to-Low Level Output

2-106

Cl

~

15 pF, RL

= 400n

,----------------------------------'-----------------------------------------------,
~MSI

DM54/DM74181

Arithmetic Logic Unit/Function Generators
General Description

Features

These arithmetic logic units (ALU)/function generators
perform 16 binary arithmetic operations on two 4-bit
words, as shown in Tables 1 and 2. These operations are
selected by the four function-select lines (SQ, S 1, S2, S3)
and include addition, subtraction, decrement, and straight
transfer. When performing arithmetic manipulations, the
internal carries must be enabled by applying a low-level
voltage to the mode control input (M). A full carry
look-ahead scheme is available in these devices for fast,
simultaneous carry generation by means of two cascadeoutputs (P and G) for the four bits in the package,
When used in conjunction with the DM54182/DM74182
full carry look-ahead circuits, high-speed arithmetic
operations can be performed, The typical addition times
shown below illustrate how little time is required for
addition of longer words, when full carry look·ahead is
employed. The method of cascading 182 circuits with
these ALU's to provide multi-level full carry look-ahead
is illustrated under typical applications data for the
DM54182/DM74182.
(Continued)

•

Arithmetic operating modes:
Addition
Subtraction
Shift operand A one position
Magnitude comparison
Plus twelve other arithmetic operations

•

Logic function modes:
EXCLUSIVE-OR
Comparator
AND, NAND, OR, NOR
Plus ten other logic operations

•

Full look-ahead for high-speed operations on long
words

Connection Diagram

J:.

Pin Designations

INPUTS

,

Al

81
23

21

22

OUTPUTS

82

A2

A3
20

19

83

\

'G

Cn+4

18

p

16

17

A:B

14

15

F3

\

13

DESIGNATION

PIN NOS,

FUNCTION

A3, A2, Al, AO

19,21,23,2

WORD A INPUTS

B3, 82, Bl, 80

18,20,22, 1

WORD B INPUTS

3,4,5,6

FUNCTION SELECT
INPUTS

S3, 52, 51, SO
Co

INV, CARRY INPUT

M

MODE CONTROL
INPUT

---

10

.

80

AO

S3

52

S1

SO

Co

M

,

\

'0

INPUTS

F1

11

F2

J

112

OUTPUTS

TYPICAL ADDITION TIMES

BITS

5 to 8
9 to 16

17 to 64

FUNCTION OUTPUTS

A=B

14

COMPARATOR OUTPUT

15

CAR RY PROPAGATE
OUTPUT,

Cn -J-4

16

INV. CARRY OUTPUT

G

17

CARRY GENERATE
OUTPUT

Vee

24

SUPPL Y VOLTAGE

GND

12

GROUND

PACKAGE COUNT

NUMBER

1 to 4

13,11,10,9

GNO

54181(J); 74181(J), (N)

OF

F3, F2, F'I, FO

20
30
30
50

ARITHMETIC!

LOOK AHEAD

LOGIC UNITS

CARRY GENERATORS

ns

CARRY METHOD
BETWEEN
ALU's
NONE

ns
ns

3or4

ns

5 to 16

0

2-107

RIPPLE
FUL.L LOOK·AHEAD

2 to 5

FULL LOOK,AHEAD

r-------------------------------------------------------------------------.-------------------~ MSI

DM54/DM74181

G.eneral Description (Continued)
If high speed is not important, a ripple·carry input

information. Again, the ALU should be placed in the
subtract mode by placing the function select inputs S3,
S2, S 1, SO at L, H, H, L, respectively.

(C n ) and a ripple·carry output (C n +4 ) are available.

However, the ripple-carry delay has also been minimized
so that arithmetic manipulations for small word lengths
can be performed without external circuitry,

These circuits have been designed to not only incorporate
all of the designer's requirements for arithmetic operations, but also to provide 16 possible functions of two
Boolean variables without the use of external circuitry.
These logic functions are selected by use of the four
function-select inputs (SO, Sl, S2, S3) with the modecontrol input (M) at a high level to disable the internal
carry. The 16 logic functions are detailed in Tables 1
and 2 and include exciusive·OR, NAND, AND, NOR,
and OR functions.

These circuits will accommodate active-high or active·
low data, if the pin designations are interpreted as
shown below.
Subtraction is accomplished byl 's complement addition
where the 1's compjement of the subtrahend is generated
internally. The resultant output is A-B-l, which
requires an end-around or forced carry to provide A-B.
The 181 can also be util ized as a comparator. The A = B
output is internally decoded from the functi on outputs
(FO, F 1, F2, F3) so that when two words of equal
magnitude are applied at the A and B inputs, it will
assume a high level to indicate equality (A = B). The ALU
should be in the subtract mode with Cn = H when
performing this comparison. The A = B output is opencollector so that it can be wire-AND connected to give a
comparison for more than four bits. The carry output
(C n +4 ) can also be used to supply relative magnitude

ALU SIGNAL DESIGNATIONS
The DM54181/DM74181 can be used with the signal
designations of either Figure 1 or Figure 2.
The logic functions and arithmetic operations obtained
with signal designations as in Figure 1 are given in
Table 1; those obtained with the signal designations of
Figure 2 are given in Table 2.

PIN NUMBER

2

1

23

22

21

20

19

18

9

10

11

13

7

16

15

Active·High Data ITable I)

AD

BO

A1

B1

A2

B2

A3

83

FD

F1

F2

F3

Cn

CnU

X

Y

Active-Low Data (Table II)

AO

BO

Al

81

A2

B2

A3

83

FO

Fl

F2

F3

en

C n-f-4

P

G

INPUT Cn

OUTPUT Cnt•

ACTIVE·HIGH DATA
IFIGURE 1)

ACTIVE·LOW DATA
IFIGURE 2)

H

H

A<;B

A::O:B

H

L

A>S

AB

L

L

A~B

A:SB

17

TABLE 1

T T (;T (T (Y
AO

I7H>-C

so

Al

B1

A2

(2f
B2

{lr (1r
A.1

ACTIVE HIGH DATA
SELECTION

B3

'0
181

Fl

F2

F3

Cnt4

Y

II16_)_

r

....11,,')

1)4)

XU

Yl

Xl

51

SO

L

L

L

L

L

L

H

L

H

l

x

J,)_,","_IO_)_"'"_,,_J_13_)__ 1,,51
1)3)
T T "f 'r
TT

YII

52

L

M" L; ARITHMETIC OPERATIONS
en :: H (no carry)

Cn :: L (with carry)

A=B-{14)

18)--- M

FO

53

M" H
LOGIC
FUNCTIONS

Y2

X2

V3

X3

x-m
1820RS182

v-om

FIGURE 1

F"A

F

F~A+8

F~A+B

F" IA

F ~ AB

F"A+8

F " IA + 8) PLUS 1

~

A PLUS 1

+ B) PLUS 1

L

L

H

H

F~O

F " MINUS 1 12', COMPL)

F " ZERO

L

H

l

L

F" AB

F" A PLUS AB

F" A PLUS AB PLUS 1

L

H

L

H

FoB

L

H

H

L

F~A

l

H

H

H

F~

H

L

L

L

H

L

L

H

H

l

H

l

F~B

F ~ IA + B) PLUS AB

F" IA + 8) PLUS AB PLUS 1

H

L

H

H

F

~

F" AS MINUS 1

F

H

H

L

L

F

=1

F

H

H

L

H

f:A+8

r

H

H

H

L

F"A+B

F " (A + 8) PLUS A

F

H

H

H

H

F"A

F=AMINUS 1

F" A

F" IA + B) PLUS AB

CD

B

A·S

F

~

A MINUS B MINUS 1

.F ~ IA + B) PLUS AB PLUS 1
F

~

A MINUS B

F"ABMINUS1

F" AB

F=A+S

F

F" A PLUS AB PLUS 1

F~

F "A PLUS B

A CDB
AB

0

A PLUS AB

~

AB

0

A PLUS A'

F " A PLUS A PLUS 1

0

IA + B) PLUS A

F" IA

*I::ach bit is shifted to the next more significant position.

2-108

F " A PLUS B PLUS 1

0

IA

+ B) PLUS A PLUS 1
+ 8) PLUS A PLUS 1

~

OM 54/ OM74181

MSI

General Description (Continued)
(X)
(1)
BO

A'

171->--

AI

Bt

A1

A3

R1

Fa

F3

Cn+4

(Xl (X) (Xl

(tt

Ft

!

F1

1t·, ~
13

GO

,

PO

GI

T {T
"

PI

S1

SO

L

L

L

F= A

F=AMINUSl

L

L

L

H

F = AB

F = AB MINUS 1

F = AB

,

lI

IX'

G3

P1

P3

':)-171

1820RS182

Cn

G :)-110)

Cn+K

Cn+Z

Cn+y

1

ut

}21

FIGURE 2

Electrical Characteristics

en :::: H (with carry)

S2

L

ril ,
G

M = L; ARITHMETIC OPERATIONS
en = L (no carry)

S3
A ~ 8 1"""(14)

-M

(ij)"

ACTIVE LOW DATA
M=H
LOGIC
FUNCTIONS

SELECTION

B3

"
tBI

(8'-

TABLE 2

(r II

I 1 (X 1)

-

F=A

,

L

L

H

L

F=A+B

F" A8 MINUS 1

F = A8

L

L

H

H

F=1

F = MINUS 1 12', COMPI

F = ZERO

L

H

L

L

F=A+B

F

PLUS IA + 81

F = A PLUS IA + 81 PLUS 1

L

H

L

H

F=8

L

H

H

L

F=A (0 B

F = AB PLUS IA + 81
F = A MINUS B MINUS 1

F = AB PLUS IA + 81 PLUS 1
F = A MINUS B
F = IA + 81 PLUS 1

=A

L

H

H

H

F=A+8

F=A+8

H

L

L

L

F = AB

F = A PLUS IA + BI

F = A PLUS IA + BI PLUS 1

H

L

L

H

F =A (0 B

F = A PLUS B

F = A PLUS B PLUS 1

H

L

H

L

F=B

F

H

L

H

H

F=A+B

F=A+B

H

H

L

L

FoO

F '" A PLUS A*

F = A PLUS A PLUS 1

H

H

L

H

F = A8

F = AB PLUS A

F = AB PLUS A PLUS 1

H

H

H

L

F = AB

F = AB PLUS A

F = A8 PLUS A PLUS 1

H

H

H

H

F=A

F=A

F = A PLUS 1

= A8

PLUS IA + BI

-

F = AB PLUS IA + BI PLUS 1
F = IA + BI PLUS 1

-

*Each bit is shifted to the next more Significant position.
over recommended operating free·air temperature range (unless otherwise noted)
DM54/74

PARAMETER

MIN
VIH

High Level Input Voltage

VIL

Low Level I nput Voltage

VI

.Input Clamp Voltage

IOH

High Level Output Current

TYPI1I

V OH

Vee == Min,

'I : :

V

-12 rnA

High Level Output Current

Vee = Min, V 1H = 2V

IA = B Output Onlyl

V,L = 0.8V, V OH = 5.5V

High Level Output Voltage

Vee = Min, V 1H == 2V

(Any Output Except A '" B)

V'L = 0.8V,

IOL

Low Level Output Current

VOL

Low level Output Voltage

10H

Vee"" Min, V 1H

=

I,

Input Current at Maximum Input Voltage

IIH

High Level Input Current

Any S Input

2V

Any S Input

16

mA

0.4

V
mA

I'A

-1.6
-4.8
--6.4

mA

-8.0
Vee = Maxl21

Condition A

Vee = Maxl31
Condition B

Notes
( 11

I'A

160

Vee'" Max, VI = O.4V

Supply r.urrent

Icc

250

200

Short Circuit Output Current
(Any Output Except A '" B)

I'A

120

Vee = Max, VI"" 2.4V

Carry Input

lOS

-800

40

Mode Input
Any A or 8 Input

V

1

Vee = Max, VI"" 5.5V

Carry Input
Low Level Input Current

V

-1.5

V

Mode Input
Any A or B Input

0.8

2.4

= -800!,A

V 1L = O.8V, IOL = 16 rnA

IlL

MAX

2

(Any Output Except A = B)

IOH

UNITS

181

CONDITIONS

All typical values are at Vec = 5V, TA = 25°e.

(21

Not more than one output should be shorted at a time.

(31

With outputs open, ICC is measured for the following conditions:
A. SO through 53, M, and A inputs are at 4.5V I all other inputs are grounded.
B. SO through S3 and M are at 4.5V, all other inputs are grounded.

2·109

DM54

-20

-55

DM74

-18

--57

DM54

88

127

DM74

88

140

DM54

92
92

135

DM74

150

mA

mA

~MSI

DM54/DM74181

Switching Characteristics vee = 5V, T A = 25°C
DM54/74
PARAMETER

FROM (lNPUTI

TO
(OUTPUTI

181

CONDITIONS
MIN

tpLH

Propagation Delay Time, Low-ta-High level Output

tpHl

Propagation Delay Time, High-ta-Low Level Output

tplH

Propagation Delay Time, Low-ta-High Level Output

tpHL

Propagation Delay Time, High-ta-Low Level_ Output

tpLH

Propagation Delay Time, Low-ta-High Level Output

tpHL

Propagation Delay Time. High-ta-Low Level-Output

tpLH

Propagation Delay Time, low-ta-High Level Output

~PHl

Propagation Delay Time, High-ta-Low Level Output

tpLH

Propagation Delay Time, Low-ta-High Level Output

tpHL

Propagation Delay Time. High-to-Low level Output

tplH

Propagation Delay Time, low-ta-High Level Output

tpHl

Propagation Delay Time, High-ta-Low Level Output

tpLH

Propagation Delay Time, Low-to-High Level Output

tpHL

Propagation Delay Time, High-ta-Low level butput

Gn

Cn +4

AnyAorB

Cn +4

AnyAorB

Cnl4

Cn

Any F

Any A or B

G

Any A or B

G

P

Any A or B

tpLH

Propagation Delay Time, Low-to-High Level Output

tpHL

Propagation Delay Time, High-to-Low level Output

Any A or B
tpLH

Propagation Delay Time, Low-to-High level, Output

tpHL

Propagation Delay Time, High-to-Low Level Output

tpLH

Propagation Delay Time, Low-to-High Level Output

tpHL

Propagation Delay Time, High-to-Low Level Output

tpLH

Propagation Delay Time, Low·to-High Level Output

tpHL

Propagation Delay Time, High-to-Low Level Output

tpLH

Propagation Delay Time, Low-tb-High 'Level Output

tpHL

Propagation Delay Time, High-to-Low Level Output

P

Ai or Bi

F;

A; or Bj

F;

Ai or Bi

F;

Any A or B

A=B

TYP

UNITS
MAX

9

18

13

19

M = OV, SO = 53 = 4.5V

20

30

S1 = 52 = OV (5UM model

22

33

ns

-

ns

M=OV,50=53=OV

20

30

51 = 52 = 4.5V (DIFF model

22

33

M = OV

11

19

(5UMor DIFF model

12

18

--

ns

M = OV, 50 = 53 = 4.5V

13

19

51 = S2 = OV (SUM model

14

19

ns

M = OV, 50 = 53 = OV

12

20

51 = 52 = 4.5V (DIFF model

15

25

M = OV, 50 = 53" 4.5V

12

19

51 = 52" OV (5UM model

17

25

M=OV,50=53=OV

14

25

51 = 52 = 4.5V (DI FF model

17

25

--

ns

ns

ns

M = OV, 50 = 53 = 4.5V

18

30

51 = 52 = OV (5UM model

19

30

M = OV, 50" 53" OV

14

24

51 = 52 = 4.5V (DIFF model

14

24

-

--

ns

ns
17

28

19

30

M=OV,50=53"OV

26

40

51 = 52" 4.5V (DIFF model

25

40

ns

M "4.5V (log;c model

--

ns

Parameter Measurement Information
LOGIC MODE TE5T TABLE
FUNCTION INPUTS: S1 = S2 = M" 4.5V, 50" S3 '" OV

PARAMETER

tpLH
t pHL
t pLH
tpHL

INPUT
UNDER
TEST

OTHER INPUT
SAME BIT
APPLY

4,5V

OTHER DATA INPUTS

APPLY
GND

APPLY

4.5V

A;

B;

None

None

B;

A;

None

None

2-110

APPLY
GND
Remaining
A and B, Cn
Remaining
A and B, Cn

ns

OUTPUT
UNDER
TEST

OUTPUT
WAVEFORM

F;

Out-of-Phase

F;

Out-of-Phase

~

MSI

DM54/DM74181

Parameter Measurement Information (Continued)
SUM MODE TEST TABLE
FUNCTION INPUTS: SO = S3 = 4.5V, S1 = S2

PARAMETER

tpLH

INPUT
UNDER
TEST

A,

OTHER INPUT
SAME BIT
APPLY
4.5V

APPLY
GND

B,

None

OTHER DATA INPUTS
APPLY
4.5V

A and B

tpU-j

Rernallllllg

tpLH

B,

A,

None

A,

B,

None

OUTPUT
UNDER
TEST

OUTPUT
WAVEFORM

C"

F,

In·Phas(~

C"

F,

In-Phase

APPLY
GND

Rermlll11119

tpHI

t pHL

= M = OV

A and B
None

Remaining

tpHL

AandB,C n

tpL.H

Remaining

t pHL

B,

A,

None

None

In-Phase
In-Phase

AandB,C n

~-

tpu~

A,

None

B,

None

B,

Remaining

Remainihg

B

A, C"

tpHl

Remaining

Remaining

tpHL

8

A, C"

t p \. H

All

All

A

B

Remaining

Remaining

tpLH

tpHL

t pl.. H
t pHL
tpL H

C"

Norle

A,

None

None

B,

A,

None
B,

B

A, Co

Remaining

Remaining

S

A, C"

A,

tpHL

DIFF MODE TEST TABLE
FUNCTION INPUTS: S1 = S2 = 4.5V, SO = S3

PARAMETER

tpLH

t pHL
tpLH

INPUT
UNDER
TEST

OTHER INPUT
SAME BIT
APPLY
4.5V

APPLY
GND

Ai

None

B,

Bi

A,

None

APPLY
4.5V

APPLY
GND

Remaining

Remaining

A

S,C"
Remaining

Remaining
A

t pLt f

Ai

None

S,

None

A and B, en
Remaining

tpLH
t pHL
tpLH

A,

None

None

Ai

B,

None

None

S,

None

Ai

None

B,

Ai

tpHL
tpU-i
tpHL
tpLH
tpHL
tPL H

Ai

B,
None

Cn

None

None

Ai

B,

None

tpHL
tpL H
tpHL
t pLH
tpHL

None

or C n

Out-af·Phase

C"14

Out-af-Phase

OUTPUT
UNDER
TEST

OUTPUT
WAVEFORM

F,

In-Phase

F,

Out-af-Phase
In-Phase
Out-of-Phase

A and B, -C n
Remaining

G

In-Phase

G

Out-af-Phase

A=S

In-Phase

AandB,C n
Remaining

Remaining

Remaining

A

B, C"

Remaining

Remaining

A

S, Cn

A and S

None

A

=

B

Cn '4
or any F

Remaining

Si

None

None

A, S, C"
A,

None

2·111

In-Phase

'4

C"14

A and B, C n

All

In-Phase

B,C"

tpl_H

Si

G
Any F

Remaining

tpHL

tpHL

Ill-Phase

= M = OV

OTHER DATA INPUTS

tpHL

G

Remaining

A, S, Cn

Out-of-Phase

I n-Phasc

C ni4

Out-of-Phase

Cn14

In-Phase

·~MSI

OM 54/DM74181

Logic Diagram

(31
S3 (4f

S2

(5)

51

I

(6)

so

G (}rY

3(18)

3

r-

I'H

I'L

los

Icc

High Level I nput Current

0.7

DM74

0.8

0.7

0.8

-1.5

-1.5
-1.5
-200

Supply Current

-400
2.5

3.4

V IL == Max, IOH == Max

DM74

2.4

2.4

2.7

3.4

Vee

=

-=

Max

Max

Vee = Max(2)

Vee = Max(3)

IOL == Max

DM54

16

2

4

16

3.6

8

DM54

0.4

0.15

0.3

0.25

DM74

0.4

0.2

0.4

0.35

IOL=4mA DM74

V

V
J-i.A
V

DM74

mA

0.4
0.5

V

C

0.4

V, = 5.5V

1

0.1

V , -7V

0.1

V, = 2.4V

40

<1

20
-0.10

-0.18

-1.6

V, = 0.4V

mA

s:

(J1

,J:Io

.......

10

V, = 2.7V
V, = 0.3V

s:

(J)

V

0.7

2.4

Vee == Min, V 1H == 2V

UNITS

MAX

2

2

2.4

Vee =Max

Short Circuit Output Current

TYPlll

DM54

Vee = Max

Low Level Input Current

MIN

I, =-18 mA

Low Level Output Current

Low Level Output Voltage

MAX

0.8

-400

Input Current at Maximum Input Voltage

I,

TYPO)

Vee = Min, V ,H = 2V

V 1L

~

MIN

DM54

I, =-12·mA

"
VOL

MAX

2

Input Clamp Voltage

IOL

TYPll)

LS192, LS193

L 192, L193

192,193
MIN

DM54LS/74LS

DM54L/74L

DM54174

V,

~

over recommended operating free-air temperature range (unless otherwise noted)

-0.4

DM54

-20

-55

-3

-9

-15

-30

-130

DM74

-18

-55

-3

-9

-15

-30

-130

DM54

65

89

8

13

19

34

DM74

65

102

8

13

19

34

J-i.A

mA

C

s:.....

...
,J:Io

CD
N
mA

mA

!:
CD
N

r-

....CD

(J)
Notes
(1) All typical values are at Vee

=

5V, TA == 25°C.

(2)

Not more than one output should be shorted at a time. and for DM54LS/74LS duration of short circuit should not exceed one second.

(3)

ICC is measured with all outputs open, clear and load inputs grounded, and all other inputs at 4.5V.

N

~

CD
to)

i....

CD
to)

r-

....
CD

(J)
to)
----_._---

~-

---

Switching Characteristics

DM54/74
PARAMETER

FROM
INPUT

TO
OUTPUT

f MAX

Maximum Clock Frequency

tPLH

Propagation Delay Time,

TYP

20

25

Propagation Delay Time,
Count down

tpLH

'"

12

~

UNITS

MIN

TYP

25

32

C/)

MAX
MHz

17

26

30

60

17

26

ns

16

24

60

120

21

33

ns

16

24

30

60

16

24

ns

16

24

50

100

21

33

ns

C L = 50 pF

C L = 15pF

Propagation Delay Time,

R L = 400[2

R L =4k[2

R L =2kl!

Propagation Delay Time,

45

90

25

38

ns

31

47

75

150

31

47

ns

27

40

55

110

27

40

ns

(J1

.......
C
~

C
~
~

High-ta-Low Level Output

High-to-Low Level Output

38

Q

Propagation Delay Time,

Propagation Delay Time,

25
Q

Propagation Delay Time,

Load

tpHL

CONDITIONS

C L =15pF

Low-ta-High Level Output

tPHL

MAX

High-ta-Low Level Output

High-ta-Low level Output
tpLH

6

LS192, LS193
TYP

Propagation Delay Time,

Either Count

'"w

MIN

Borrow

Low-to-High Level Output
tpHL

CONDtTlONS

Propagation Delay Time,

Low-ta-High Level Output

tPHL

MAX

Carry

High-to-Low Level Output
tpLH

DM54LS/74LS

L192, L193

MIN

Low-to-High Level Output
Count up

DM54L!74L

192,193
CONDtTlONS

tpHL

~

Vee = 5V, T A = 25° C

29

40

105

200

29

40

ns

22

35

95

190

22

35

ns

-.oJ

Clear

Q

tw

Width of Any I nput Pulse

25

70

20

ns

tSETUP

Data Setup Time

20

30

20

ns

tHOLD

Data Hold Time

0

0

0

ns

....
to
~

N

....tor-

N

r-

....

C/)

to

N

:..
to
W

tto
W

r-

....
CD

C/)

W
I

~ MSI

DM54/DM74192.L192.LS192.193.L193.LS193

Logic Diagrams

192, L192, LS192
(13) BORROW

'"

OUTPUT

.--

(12) CARRY

OUTPUT

J
DATA (15)
INPUT A

DOWN 14)
COUNT

/

r--'

J-

(3)

GA

OUTPUT OA

T

DA

UP (5)
COUNT

-

-

bT

DATA (1)
INPUT B

r----r

-L

~Q=>

(2)

OUTPUT De

G,
T

D, f--,...-

l>DATA (101
INPUT C

tr>-

r---''"

~

~~

(6)

Ge

OUTPUT

Dc

OUTPUT

no

T

iic-

~

-

6T

DATA (9)
INPUT D
(14)
CLEAR

rt-"
---i
r-''''"""'"
(7)

00
T

Do

LOAD

~

(11)

2,136

-

~ MSI

DM54/DM74192,L192.LS192,193,L193,LS193

Logic Diagrams (Continued)

193, L 193, LS193
113) BORROW
OUTPUT

"-

I

(12) CARRV
OUTPUT

DATA
INPUT A

(15)

~

J-

DOWN (4)
COUNT

(3)

GA

OUTPUT OA

T

OAr--

UP (,)
COUNT

~
-

6-;T

,.

DATA II)
INPUT B

J-

r---'
~---'--

-

OUTPUT

no

,.

~

-

(6)

Ge
T

fie

I

(14)

fie

tr>-

--;--

CLEAR

OUTPUT

fi,r--

r---'.
~=-=I

DATA (9)
INPUT 0

as

'-- r---

~.

DATA (10)

OUTPUT

T

1

INPUT C

(2)

G,

f--

6-;T

"-

~
'-!---1

r--' I...(7)

00
T

fiof--

LOAD

~

(11)

2·137

~ MSI

DM54/DM74192.l192.lS192.193,l193.lS193

Timing Diagrams

192, L 192, LS192 DECADE COUNTERS
TYPICAL CLEAR, LOAD, AND COUNT SEQUENCES

CLEAR

LOAD

~

____________________~_________________________________________

II u

:~~
~1'---

DATA

! i
I,

1-

COUNT----+-t----r-t---,
UP
COUNT----+-t----r-t--~----------------------+---,

DOWN

OUTPUTS

CARRY
BORROW

~~

CLEAR

I

8

9

0

1

21

~-- COUNT U P - - - - J

I

1

0

9

8

11

. -COUNT DOWN-----'

PRESET

Sequence:
(li Clear outputs to zero.
(2)

Load (preset) to BCD seven.

(3)

Count up to eight. nine, carry, zero, one, and two.

(4)

Count down to one, zero, borrow, nine, eight, and seven,

Notes:

(A) Clear overrides load, data, and count inputs.
(8)

When counting up, count-down input must be high; when counting down, count-up input must be high.

2-138

~ MSI

DM54/DM74192,L192,LS192,193,L193,LS193

'Timing Diagrams (Continued)

193, L193, LS193 BINARY COUNTERS
TYPICAL CLEAR, LOAD, AND COUNT SEQUENCES

LOAO
A

DATA

COUNT----+-~--~~--~
UP

COUNT----+-~--~~--~----------------------+---,
DOWN

OUTPUTS

Dc

CARRY

BORROW

~~

CLEAR

I

14

1&

0

1

1

I

- - - - COUNT UP - - - - ,

I

1

0

15

14

131

. - - - COUNT OOWN----'

PRESET

Sequence:
~1)
Clear outputs to zero.
(2) Load (preset) to binary thirteen.
(3) Count up to fourteen, fifteen, carry, zero, one, and two.
(4) Count down to one, zero, borrow, fifteen, fourteen, and thirteen.
Notes:
{Al Clear overrides load, data, and count inputs.
(8)

When counting up, count-down input must be hIgh; when counting down, count-up input must be high.

2-139

~MSI

DM54/DM74194,LS194A,S194
4-Bit Bidirectional Universal Shift Registers

General Description
shifts reft synchronously and new data is entered at the
shift-left serial input.

These bidirectional shift registers are designed to
incorporate virtually all of the features a system designer
may want ,in a shift register; they feature parallel inputs,
parallel outputs, right-shift and left-shift serial inputs,
operating-mode-control inputs, and a direct overriding
clear line, The register has four distinct modes of operation, namely:

Clocking of the flip-flop is inhibited when both mode
control inputs are low, The mode controls of the
DM54194/DM74194 should be changed only while the
clock input is high.

Features

Parallel (broadside) load
Shift right (in the direction G A toward Go)
Shift left (in the direction Go toward G A I
Inhibit clock (do nothing)

• Parallel inputs and outputs
• Four operating modes:
Synchronous parallel Ipad
Right shift
Left shift
Do nothing
• Positive edge-triggered clocking
• Direct overriding clear

Synchronous parallel loading is accomplished by applying
the fou'r bits of data and taking both mode control
inputs, SO and Sl, high, The data are loaded into the
associated flip-flops and appear at the outputs after the
positive transition of the clock input, During loading,
serial data flow is inhibited,

TYPE

Shift right is accomplished synchronously with the
rising edge of the clock pulse when SO is high and Sl is
low, Serial data for this mqde is entered at the shiftright data input. When SO is low and Sl is high, data

Connection Diagram
I"

1

CLEAR

S194

,
Go

2

l

,A

RIGHT
SERIAL

11

5

4

B

C

0

36 MHz
36 MHz

195mW

105 MHz

425mW

75mW

so

S1

CLOCK
12

Il

14

SHIFT

POWER DISSIPATION

194

OUTPUTS

15

TYPICAL

FREQUENCY

LS194A

D,

V,'

TYPICAL CLOCK

10

,

,

,

SHIFT
LEFT
SERIAL

PARAllEL INPUTS

J:

INPUT

INf'UT

54194(J), (W); 74194(J), IN), (WI;
54LS194A/74LS194A(J), (N), (W); 74S1941N)

Truth Table
OUTPUTS

INPUTS
CLEAR

MODE

CLOCK

LEFT

RIGHT

A

B

C

D

X
X
X
X
X

X
X
X

X
X

X
X

X
X

H

X
X
X

X
X
a
X
X
X
X
X

Sl

SO

H

X
X

X
X

H

H

H

t

H

L

H

H

L

H

H

H

L

t
t
t

H

H

L

t

L

H

L

L

X

X

L

X
L

PARALLEL

SERIAL

H
L

QA

QB

L

L

QAO QBO

Oc

Qo

L

L

Qco Q oo

b

c

d

a

X
X
X
X
X

X
X
X
X
X

X
X
X
X
X

H

Q An QBn

QCn

L

Q An QBn

Q Cn

b

c

d

QBn

QCn

QDn

H

QBn

Q Cn

QOn

L

QAO QBO

QCO Q oo

H = High Level (steady state), L = Low Level (steady state), X = Don't Care (any input, including transitions)
t =: Transition from low to high level
a, b, c, d = The level of steady state input at inputs A, B, C, or 0, respectively.
OAO" 0BO, OeD, 0DO = The level of QA, OS. Oc, or QD. respectively. before the indicated steady state input conditions were established.
QAn. 0Bn, aCn, QO n = The level of 0A, 0B, Cle, respectively, before the most recent t transition of the clock.
Tentative Data For LS194A

2-140

LS194A, 8194 To Be Announced In 1976

~

Electrical Characteristics over recommended operating free·air temperature range (unless otherwise noted)
DM54/74
PARAMETER

CONDITIONS

194
MIN

V'H

High Level Input Voltage

V'L

Low Level Input Voltage

V,

Input Clamp Voltage

10H

High Level Output Current

VOH

High Level Output Voltage

VOL

~

I,

I'H

Input Current at Maximum Input Voltage

High Level Input Current

I'L

Low Level Input Current

los

Short Circuit Output Current

Icc

Supply Current

MIN

TYP(l)

:=0

Max,

IOH =

Vee: Min, V ,H

:

2

Vee: Max

Vee: Max
Vee = Max

V
N/A

DM74

0.8

0.8

0.8

-1.5

-1.2

3.4

2.5

3.5

Max

DM74

2.4

3.4

2.7

3.5

IOL == Max

-1000

-400

2.4

N/A
2.7

16

4

N/A

DM74

16

8

20

DM54

0.2

0.4

0.25

0.4

N/A

DM74

0.2

0.4

0.35

0.5

0.5

0.25

0.4

V, : 5.5V

1

1

V, :7V

0.1

V, : 2.4V

50

40

2.7V

20

V, : OAV

-1.6

Vee: Max(2)
Vee: Max(3)

DM54

-20

DM74

-18
39

-30

-57

-30

63

-2

-0.4

-57

-130
-130
15

23

N/A
-40

-100
85

V

V
Il A
V

3.4

DM54

DM74

s:

(J)

MAX

2

DM54

~

TYP(l)

-1.5

IOL :4 mA

V,

MIN

0.7

2V

2V

UNITS

5194
MAX

0.8

-800

:

V1L=Max

::

LS194A
MAX

1,--18mA

Vee: Min, V ,H

DM74S

DM54

I, : -12 mA

Vee: Min

Low Level Output Current

Low Level Output Voltage

TYP(1)

2

V 1L
10L

DM54 LS/74LS

135

mA

V

rnA

IlA
rnA

0

rnA

s:

rnA

........

(11

~

0

Notes
(1) All typical values are at V CC : 5V, T A : 25 0 C,
12) Not more than one output should be shorted at a time, and for DM54LS/74LS or DM74S duration of short circuit should not exceed one second.
(3) With all outputs open, inputs A through 0 grounded, and 4.5V applied to SO, 81, clear, and the serial inputs, ICC is tested with a momentary GND. then 4.5V applied to clock.

s:-..J

...
~

(D

~

r(J)

...

(D

-

~

'(J)
!>

...

(D

~

~

Switching Characteristics vee = 5V, T A = 25°C
DM54/74

DM54 LS/74 LS

DM74S

194

LS194A

S194

PARAMETER
CONDITIONS
fMAX

Maximum Clock Frequency

tpHL

Propagation Delay Time, High-to-Low

MIN

TYP

25

36
19

Level Output From Clear
tpLH

Propagation Delay Time, Low-to-High
Level Output From Clock

tpHL

"'"

CONDITIONS

MIN

TYP

25

36

30

C L = 15pF

19

MAx

RL = 400n

Propagation Delay Time, High-to-Low

14

22

14

22

CONDITIONS

MIN

TYP

70

105

..

MAX

18.5

ns

4

8

12

ns

4

11

16.5

ns

C L = 15 pF

RL = 2 kn

14

22

17

22

RL = 280n

tv

........

0
~

-..J

....+:>

(D

+:>
r-

en
....

(D

+:>

»
en
~

(D

+:>

-

---_ .. -

---_ .. ----_._--- - - - - - - - - - - - - - - - - - - - - - - - -

- - - - - - _ ... -------_._--_ .. - - - - - -

~-.-

-----------------_ ... _-----

--

_ .. __..

-- -----

~MSI

OM54/0M74194,LS194A,S194

Logic Diagrams

A

SHIFT
RIGHT
SERIAL
INPUT

131

121

194
SHIFT
PARAllEL INPUTS

•1'1

D

C

151

LEFT
\ SERIAL
INPUT

I')

111

LSl94A, S194
PARAllEL INPUTS

•)'1

A
)3)

c

D

)51

161

MDDEtS1~(I~m{>04~---1~--r-----~------~---+----~~------~---r----~------~~--+-----'

CONTROL

,INPUTS so .;;1';:.I-D<>-1~---i---+~PI---+-------+---I+-:1.f---"~------+---++--.lf--fl---------~-i.f-~-'
SHIFT

SHIFT

S~~~~r .:;1':..1--------..,

.-++1____+..:.)7:.:.) ~:~iAL
INPUT

INPUT

CtOCK~ll~lIi~O---------------~--+---.f-________~~__~-i__________~__- i__+ __________~
CLEAR~)l~I

+-______________

____q)~______________~__

~~

(15)

______________-4__-+______________

.

(14)

"A
Timing Diagram

(13)

PARALLEL OUTPUTS

'"

TYPICAL CLEAR, LOAD, RIGHT·SHIFT, LEFT·SHIFT, INHIBIT, AND CLEAR SEQUENCES
CLOCK

CLEAR

SEO~~~ {R
INPUTS

L

--+-+--i---------------+-+.J

PARAtLEl\:---+-"t-I----+-t---+-------!DATA
INPUTS

c

l

O--~t--r--------------r-t-----------t-----------+_-

aA :

a,-

OUTPUTS

:

a,_

DD:
CLEAR

2·143

~

1121
110

~ MSI

DM54/DM74195,LS195A,S195
4-Bit Parallel Access Shift Registers

General Description
These 4-bit registers feature parallel inputs, parallel
outputs, J-K serial inputs, shift/lo~d control input, and
a direct overriding clear. All inputs are buffered to
lower the input drive requirements. The registers have
two modes of operation:

speed data processing systems. In most cases existing
systems can be upgraded merely by using this Schottkyclamped shift register.

Features

Parallel (broadside) load
Shift (in the direction Q A toward QD)

• Synchronous parallel load
• Positive-edge-triggered clocking
• Parallel inputs and outputs from each flip-flop
• Direct overriding clear
• J and K inputs to first stage
• Complementary outputs from last stage
• For use in high-performance:
accumulators/processors
serial-to-parallel, parallel-to-serial converters

Parallel loading is accomplished by applying the four
bi~s of data and taking the shift/load control input
low. The data is loaded into the associated flip-flop and
appears at the outputs after the positive transition of the
clock input. Duri,ng loading, serial data flow is inhibited.
Shifting is accomplished synchronously when the shift/
load control inpiJ.! is high. Serial data for this mode is
entered at the J-K inputs. These inputs permit the first
stage to perform as a J-K, D, or T-type flip-flop as shown
in the truth table.

TYPICAL CLOCK

TYPICAL

FREQUENCY

POWER DISSIPATION

195

3!l MHz

195mW

LS195A

39 MHz

70mW

105 MHz

350mW

TYPE

The high-performance S195, with a 105 MHz typical
shift frequency, is particularly attractive for very high-

S195

Connection Diagram
OUTPUTS

'~.,--u-,--u~,--Uo~-U-o"'l

V"r

"

15

K

J

11

•

3

1

1

CLEAR

13

14

5
C

~~~~

111

9

7

6

B

,A

~

CLOCK

11

D

Gt:

PARAllEL INPUTS

SERIAL INPUTS

54195(JI. (WI; 74195(J), (N), (W);
54LS195A/74LS195A(JI. IN), (W); 74S195(N)

Truth Table
INPUTS
CLEAR

SHIFTI
LOAD

CLOCK

L

X

X

H

L

t

H

H

L

H

H

H

H

H

H

H

H

t
t
t
t

OUTPUTS

SERIAL

PARALLEL

°D aD

J

K

A

B

C

D

°A

OS

X
X
X

X
X
X

X

L

L

L

L'

d

a

b

e

d

d

G eo

G DO

ODD

L

x

X
e
X
X
X
X
X

X

H

X
a
X
X
X
X

L

H

L

'L

H
H'

H = High Level (steady state), L = Low Level (steady, state), X

=

b

X
X
X
X
X

X
X
X
X
X

GAO G BO

Dc

H

°Bn

Q Co

Oen

L

GM

G BO

Q Cn

OCfl

H

QAO

°Sn

G Co

G An G sn

°en

Oen
Oen

GAO GAO

OAn

Dqn~t Care (any input, including transitions)

Transition from low to high' le~el
,'. ,
.-~~':J--,
a, b, c. d ==: The level of steady state input at A. B, e.,or D. respective~y.
0AO. 0BO, 0eo, ODO = The level of 0A_ 0B. Qc. or 00, respecti\iely, before the indicated steadY state inpl,It conditions were established.

t

=

QAn, 0Sn, QCn"'" The level of QA, 0B, or 0C. respectively, before tile most recent transition of the clock .

.

Tentative Data For LS195A

.2-144

LS195A, $195 To Be Announced In 1976

Electrical Characteristics

~

over recommended operating free-air temperature range (unless otherwise noted)
DM54/74

PARAMETER

I

I

CONDITIONS

V,H

High Level Input Voltage
Low Level Input Voltage

MAX

2

MIN

TVP(l)

IOH

DM74

0.8

0.8

0.8

-1.5

-1.2

V 1L
IOL

VOL

I

0:0

Max, IOH

= Max

Low Level Output Current

I Low

Level Output Voltage

Vee = Min, V ,H = 2V

IOL -= Max

V 1L -= Max

~I

10L

I,

Input Current at Maximum Input Voltage

I'H

High Level I nput Current

Low Level I nput Current

I'L

los
ICC

I Short Circuit Output Current
I Supply Current

Notes
(1) All typical values are at

Vee = Max

Vee -= Max

Vee = Max

= 4 mA

-400

DM54

2.4

3.4

2.5

3.4

DM74

2.4

3.4

2.7

3.4

V

'1000

16

4

N/A

16

8

20

DM54

0.2

0.4

0.25

0.4

N/A

DM74

0.2

OA

0.35

0.5

0.5

0.25

0.4

V, = 5.5V

40

V, = 2.7V

20

V,=OAV

-1.6

50

--0.4
-2

V, = 0.5V

Vee = Maxl2)
Vee = Maxl3)

DM54

-20

-57

-30

-130

DM74

--18

-57

-30

-130

39

63

14

21

mA

I

V

mA

0.1

V , =2AV

MA
V

DM74

V, = 7V

I

3.4

DM54

DM74

V

N/A
2.7

(/)

V
N/A

-1.5

Vee -= Min, V 1H -= 2V

s:

MAX

0.7

-800

I

TVP(l)

2

2

High Level,Output Current

I High Level Output Voltage

MIN

0.8

Vee=MIfI

V OH

UNITS

S195
MAX

DM54

. LI, =-12mA
i l ,=-18mA

Input Clamp Voltage

V,

TVP(ll

DM74S

LS195A

195
MIN

V,L

DM54LS/74LS

N/A
-40

-100
70

109

J.1A

rnA

mA

0

s:
(JI

:a

......
mA

0

s:

"

:a
....

Vee = 5V, TA = 25°C.

(2)

Not more than one output should be shorted at a time, and for DM54LS/74LS or DM74S duration of short circuit should not exceed one second.

(3)

With all outputs open, shift/load grounded, and 4.5V applied to the J,
ground, followed by 4,5V, to clock.

K, and data

inputs, ICC is measured by applying a momentary ground, followed by 4.5V, to clear and then applying a momentary

CD

(JI

r-

....
CD

(/)
(JI

»
en
....
CD
(JI

Switching Characteristics

Vee ~ 5V, T A ~ 25°C

~
DM54/74

DM54LS174LS

DM74S

195

LS195

S195

PARAMETER
CONDITIONS
fMAX

Maximum Clock Frequency

tpHL

Propagation Delay Time, High-to-Low
Level Output From Clear

tPLH

Propagation Delay Time, Low-la-High

MIN

TVP

30

39
19

CL
AL

= 15 pF
= 400.12

Propagation Delay Time, High-to-Low
Level Output From Clock

~

.,.

CONDITIONS

MIN

TVI'

30

39

30

1--

Level Output From Clock
tpHL

MAX

14

22

17

26

19
CL

=

AL

= 2 kn

MAX

CONDITIONS

MIN

TVP

70

105

30

15 pF

UNiTS

~

en

MAX
MHz

12.5

18_5

ns

8

12

ns

11

16.5

ns

C L =15pF
14

22

17

26

AL = 280.12

tWICLOCKI

Width of Clock Input Pulse

16

16

7

ns

tWiCLEARI

Width of Clear I nput Pulse

12

12

12

ns

tsETUP

Setup Time

Shift/Load

25

25

11

Serial and Parallel Data

15

15

5

Clear Inactive-State

25

25

9

ns

----'-tRELEASE

Shift/Load Aelease Time

tHOLD

Serial and Parallel Data Hold Time

0>

10

r--6

10

0

6
3

ns
ns

C
~
U'I
~

.......
C
~

~

(D

U'I

ren
~

(D

U'I

»
en
~

(D.

U'I

~ MSI

DM54/DM74195,lS195A,S195

Logic Diagram

SE.RIAl

PAAALLElINPUTS

INPUT
~

K
('I

StllFTllOAO (!H

a

A

(41

c

151

o
(61

171

CONTROL

PARAllEl OUTPUTS

tnls connr;ctiOIlIS mad1l on 195 only.

Timing Diagram
TYPICAL CLEAR, SHIFT, AND LOAD SEQUENCES

ClOCK

-.r-

""'' {'

i

I

SHIFT/LOAD

I

PARI:~ t~ :---t-----+I--------------I*'--If-~
____________
I I
o

I
I
-i.-;;l

l

r--, L

-+
~--~i

0A _
-_
-

-----'

t

OUTPUTS
\

I'

L..._ _ _ _ _ _ __

r.--IttH

o,:=J

~.:;l_ _ _ __

OD--

I

'

-- I
CLEAR

LOAD

2-147

'

~ MSI

DM54/DM74198.199
8-Bit Shift Registers

General Description
Clocking, of the fiip-flop is inhibited when both mode
control inputs are low. The mode controls should be
changed only while the clock input is high.

These 8-bit shift registers feature buffered inputs to
lower the drive requirements to one normal ized Series
54/74 load, and input clamping diodes to minimize
switching transients and simplify system design_ Maximum input clock frequency is typically 35 MHz and
power dissipation is typically 360 mW.

DM54199/0M74199
These registers feature parallel inputs, parallel outputs,
J-K serial inputs, shift/load control input, a direct
overriding clear line, and gated clock inputs. The register
has three modes of operation:

DM54198/DM74198
These bidirectional registers are designed to incorporate
virtually all of the features a system designer may want
in a shift register. They feature parallel inputs, parallel
outputs, right-shift and left-shift serial inputs, operating
mode control inputs, and a direct overriding clear line.
The register has four distinct modes of operation, namely:

Parallel (broadside) load
Shift (in the direction Q A toward QH)
I nhibit clock (do nothing)
Parallel loading is accomplished by applying the eight
bits of data and taking the shift/load control input
low when the clock input is not inhibited. The data is
loaded into the associated flip-flop and appears at the
outputs after the positive transition of the clock input.
During loading, serial data flow is inhibited.

Parallel (broadside) load
Shift right (in the direction Q A toward QH)
Shift left (in the direction Q H toward QA)
Inhibit clock (do nothing)
Synchronous parallel loading is accomplished by applying
the eight bits of data and taking both mode control
inputs, SO and S1 high. The data is loaded into the
associated flip-flop and appears at the outputs after the
positive transition of the clock input. During loading,
serial data flow is inhibited.

Shifting is accomplished synchronously when shift/load
is high and the clock input is not inhibited. Serial data
for this mode is entered at the J-K inputs. See the truth
table for levels required to enter serial data into the
first flip-flop.
Both of the clock inputs are identical in function and
may be used interchangeably to serve as clock or clockinhibit inputs. Holding either clock input high inhibits
clocking; but when one is held low, a clock input applied
to the other input is passed to the eight flip-flops of the
register. The clock-inhibit input should be changed to
the high level only While the clock input is high.

Shift right is accomplished synchronously with the rising
edge of the clock pulse when SO is high and S1 is low.
Serial data for this mode is entered at the shift-right
data input. When SO is low and S1 is high, data shifts
left synchronously and new data is entered at the
shift-left serial input.

Connection Diagrams
SHIFT
LEFT
SERIAL INPUT
Sl INPUT
H DH

124

23

22

21

INPUT
INPUT
G
F
D,
Dc

20

19

18

17

INPUT
E
Oe CLEAR

16

15

-

1
SO

14

SHIFT/ INPUT

Vee LOAD

L4

13

23

H

22

OH

21

INPUT
F

INPUT
G

20

19

18

INPUT

E

17

Oe CLEAR CLOCK

16

15

2

3

4

5
INPUT
B

6

n,

7
INPUT
C

8

9

10

13

-

0-

SHIFT INPUT QA
'RIGHT A
SERIAL
INPUT

14

1

U J12

Dc INPUT 0 0 CLOCK GNO
0

K

2
J

----------

3

4

5

INPUT 0, INPUT
A
B

6

7

C

54199/74199(J), (N)

2-148

10

11 J'2

D, INPUT Ilc INPUT 00 CLOCK GND

SERIAL
INPUTS

54198/74198(Jl, (N)

9

8

D

INHIBIT

~

MSI

DM54/DM74198,199

Electrical Characteristics over recommended operating free·air temperature range (unless otherwise noted)

DM54/74
PARAMETER

CONDITIONS

198, 199
MIN

VIH

UNITS
MAX

2

High Level Input Voltage

V IL

Low Level Input Voltage

VI

Input Clamp Voltage

10H

High Level Output Current

VOH

High Level Output Voltage

10L

Low Level Output Current

VOL

Low Level Output Voltage

Vee

~

Min,

1,~-12mA

Vee

~

Min,

V ,H

~

2V

V'L ~ O.BV,

IOH

~

-SOOJ1A

V
O.S

V

-,1.5

V

-SOO

Vee

~

~

IOL~16mA

II

Input Current at Maximum Input Voltage

Vee

Max,

V,

~

IIH

High Level I nput Current

Vee~Max,

V,

~204V

IlL

Low Level Input Current

Vee

los

Short Circuit Output Current

Supply Current

~

5.5V

Vee

~

Max(2)

Vee

~

Max

16

mA

004

V

1

mA

40

fJ.A

. -1.6

V,~Oo4V

Max,

(See Conditions for lee Table)

J1A
V

204

V'H ~ 2V

Min,

V'L ~ O.BV,

Icc

TYP(1)

DM54

-20

-57

DM74

-lB

-57

mA
mA

.--

DM54

72

104

DM74

72

116

mA

Notes
All typical values are at vee = 5V, T A = 25° C.
(2) Not more than one output should be shorted at a time.
( 1)

Switching Characteristics Vee

= 5V,

T A ~ 25°C

DM54/74
CONDITIONS

PARAMETER

fMAX

Maximum Input Count Freque'ncy

tpHL

Propagation Delay Time, High·to-Low

198,199
MIN

TYP

25

35

Level Output From Clear
tPHL

Propagation Delay Time, High-to-Low

CL

~

15 pF, RL

~

UNITS
MHz

23

35

ns

20

30

ns

17

26

ns

400n

Level Output From Clock
tpLH

MAX

Propagation Delay Time, Low-to-High
Level Output From Cloc,k

tw

Width of Clock or .Clear Pulse

20

ns

tSETUP

Mode-Control Setup Time

30

ns

tSETUP

Data Setu p Ti me

20

ns

tHOLD

Hold Time at Any Input

0

ns

Conditions for Icc (All outputs are open)
TYPE

APPLY 4.5V

19S

Serial Input, SO, Sl
J, K, Inputs A thru H

199

F!RST GROUND,
THEN APPL Y 4.5V

GROUND

Clock

Clear, I nputs A thru H

Clock

Clock Inhibit, Clear, Shift/Load

2-149

~ MSI

OM54/0M74198,199

Truth Tables

198

INPUTS
MODE
CLEAR

51

so

OUTPUTS
SERIAL

CLOCK

PARALLEL

LEFT

RIGHT

A". H

X

X

X

X

X

H

X

X

X

X

X

H

H

H

X

X

a .. .h

H

L

H

X

H

X

H

X

aA

a.

aG

aH

L
a AO aBO

aGO G HO

h

b

H

GAo

G Fn

GGo

H

X

L

X

GAo

G Fn

GGn

H

H

l

H

X

X

G Bn

G eo

G Hn

H

H

H

L

l

X

X

G Bn

G en

G HO

H

L

l

X

X

X

GAO G BO

X

GGO a HO

H = High Level (steady state), L = Low Level (steady state)
X

:=

Don't care (any input, including transitions)

t = Transition from low to high level
a ... h ::: The level of steady state input at inputs' A thru H. respectively.
GAO, GSO, GGO, aHO

=

The level of aA, 0B, aG, or GH, respectively, before the indicated

steady-state input conditions were established.
QAn. 0Sn, etc. = The level of QA, 0B, etc., respectively, before the mostwrecent t transition of
the clock.

199

INPUTS
SHIFTI

CLOCK

LOAD

INHIBIT

L

X

X

X

H

X

L

L

L

t

CLEAR

H
H

H

H

H

H

H

H

H

H

X

CLOCK

OUTPUTS
SERIAL
K

A". H

X

X

X

X

X

X

X

x

L
L
H

PARALLEL

Oc

GH

G eo

°HO

b

h

GAO GAO G BO

GGn

aA

L
GAO G BO

... h

H

X

as

L

L

X

L

H

H

X

H

G An aBo
G An aBO

GGo

H

L

X

DAn

a Ao

aBo

GGn

X

X

X

aAO aBO

aBO

G HO

a Gn

H = High Level (steady state) .. L == Low Level (steady state)
X

:=

Don't care (any input, including transitions)

t

0;::

Transition from low to high level

a ... h = The level of steady state input at inputs A thru H, respectively.
OAO, 0BO, 0CO· .. 0HO =: The level of 0A, QS, or QC thru 0H, respectively, before the indicated
steady·state input conditions were established.
QAn, aBn· . 0Gn ::. The level of QA or' Os thru 0G, respectively, before the most-recent t
transition of the clock

2-150

~MSI

OM 54/ OM74198 .199

Logic Diagrams

199

198
CLOCK (1l)

ClOCK..:.I1"'lI'-_--11

>.....,
1~~~B~~.!!I'!.!!lI~-L~""'"--------1
SERIAL ( J \21
INPUTS j(.:.I'::..
_ _ _ _.....,

S~~F;~::;[2""lt>.,.-<>I>....+-,=3
A (3)

r------+~--~nA
8(5)
B (5)

e(7)

c

(7)

[81 ilc

n 1'1

o (91

EllS)
E (16)

F (17)

F (t8)

G (19)

G (20)

H (21)
H (22)

s~~~~-,I::22,-1-------1--1-.)

ClE~R

-.,.O-----,--1======~~=:t,~

CLEAR.![':.::',-I

2-151

.q

.![",'4,-1_ _ _ _ _ _....ql:>:>-__....__

~ MSI

DM54/DM74198,199

Timing Diagrams

198
TYPICAL CLEAR, LOAD, RIGHT-SHIFT, LEFT-SHIFT, INHIBIT, AND CLEAR SEQUENCES

CLOCK

ClEAR

SERIAL {
DATA

R

-t-+-1---------------t-i-'

INPUTS

PARALLEL
DATA
INPUTS

OUTPUTS

199
TYPICAL CLEAR, SHIFT"LOAD, AND INHIBIT SEQUENCES
ClOCK
CLOCK
INHIBIT

CLEAR

SfRIAL{ J
INPUTS
K

SHIFT/LOAD

PARAllEL
DATA

INPUTS

OUTPUT

QO--'~---_1-----J

__

O£ - - ,

,+,-----r----------~

::::1,
--+,--+--------'
a,

j_-------CLEAR

SERIAL SHIFT
LOAD

~ MSI

OM54/0M74198,199

Parameter Measurement Information
198

199

TEST TABLE FOR SYNCHRONOUS INPUTS

TEST TABLE FOR SYNCHRONOUS INPUTS

DATA INPUT
FOR TEST

OUTPUT TESTED
(SEE NOTE EI

DATA INPUT
FOR TEST

SHIFT/LOAD

4.5V

Q A at t nf ,!

A

OV

Q A at tn+l

4.5V

0 8 at

tn+l

B

OV

4.5V

Oc at

tn+1

C

OV

Os at t n ""l
Q c at tn+l

4.5V

aD

at tn+l

D

OV

OD

4.5V

4.5V

OE

at

tn+1

E

OV

Q E at tn+1

5,

So

A

4.5V

B

4.5V

C

4.5V

D

4.5V

E

OUTPUT TESTED
(SEE NOTE EI

at tn+l

F

4.5V

4.5V

OF

at

tn+1

F

OV

OF

at tn+l

G

4.5V

4.5V

QG

at

tn+l

G

OV

OG

at

H

4.5V

4.5V

Q H at tn+l

H

OV

OH

at tn+l

L Serial Input

4.5V

OV

Q A at t n+8

4.5V

OH

at

A Serial Input

OV

4.5V

Q H at t n +8

J and

K

LOAD FOR OUTPUT UNDER TEST

OUTPUT

FROM

O~Z~~~ TEST

........~t--.t-.Hpth

l'

Cl "15 pF

ISEE NOTE 81

SWITCHING TIME WAVEFORMS

=J

CLEAR INPUT

tWIClEARIt;:

.

~1.5-V~~~~~~_----------------3V
(SEE NOTE f)

L

~

~
~3V

CLOCK INPUT

::J ~
11,...----3v
tHOlO

tSETU':j
DATA INPUT
ISEETESTTABLEI

__-+ ___. J
I

I

'l'HL
(CLEAR-ali

I-I

1.5V

OV

1.5V

-----ov

I
JtPLH
I
---IICLK-olr---

pi

tJUTPUT 0----""""'\'.5V

Notes

2: 20 ns and

(AI

The clock pulse has the following characteristics: twlclockl

(8)

The clear pulse has the following characteristics: tw(clear) :2: 20 ns and tHOLD
When testing fMAX, vary the clock PRR.
CL includes probe and jig capacitance.

IC)

All diodes are 1 N3064.

(O)

A clear pulse is applied prior to each test.
Propagation delay times (tPLH and tpH l) are measured at t n +1. Proper shifting of
data is verified at·t n+8 with a functio~~J...test.
t n ::; bit time before clocking transition,
t n +1 "" bit time after one clocking transition
t n +8 = bit time after clocking transitions

(EI
(F)

2-153

PRR = 1 MHz.
=

0 ns.

tn+l

t n +8

~ MSI

DM54/DM74S200
TRI-STATE 256-Bit ReadIWrite Memories

General Description
The DM54S200/DM74S200 256-bit active-element
memories are monolithic transistor-transistor logic (TTL)
integrated circuits organized as 256 words of one bit
each. They are fully decoded and have three gated
memory-enable inputs to simplify decoding required to
achieve the desired system organization. The memories
feature PNP input transistors which reduce the low-level
input current requirement to a maximum of -0.25 mA',
only one-eighth that of a normal Series 54S/74S load
factor. The memory-enable circuitry is implemented with
minimal delay times to compensate for added system
decoding.

neither load nor drive the bus line, but it will allow the
bus line to be driven by another' active output or a
passive pull-up if desired.
Read Cycle: The stored information (complement of
information applied at the data input during the write
cycle) is available at the output when the write-enable
input is high and the three memory-enable inputs are
low. When anyone of the memory enable inputs is high,
the output will be in the high-impedance state.

Features

The TRI-STATE output combines the convenience of
an open-collector with the speed of a totem-pole output;
it can be bus-connected to other similar outputs, yet it
retains the fast rise time characteristics of the TTL
totem-pole output.

• Schottky-clamped for high-speed memory systems:
Access from memory-enable inputs
20 ns typ
Access from address inputs
31 ns typ
Power dissipation
1.7 mW/bit typ
• TRI-STATE output for driving bus-organized systems
and/or highly capacitive loads
'. Fully decoded, organized as 256 words of one bit
, each

Write' Cycle: The complement of the information at the
data input is written into the selected location when all
memory-enable inputs and the write-enable input are
low. While the write-enable input is low, the output is
in the high-impedance state. When a number of outputs
are bus-connected, this high-impedance output state will

Connection Diagram

• Compatible with most TTL and DTL logic circuits
• Multiple memory-enable inputs to minimize external
decoding

Logic Diagram

ADDRESS
INPUTS

ADDRESS
INPUTS

ADDRESS
INPUTS

,0

!
1111

G

/101

ADDRESS
!NPUTS

F

E (9)

0/ 11

• A

MEt

ME2

ME3

OUTPUT

0

Y

ADDRESS
INPUT

ADDRESS
INPUTS

GNU

54S200IJ), IWI; 74S200(J), IN), (WI

Truth Table
INPUTS
MEMORY
ENABLEt

WRITE
ENABLE

Write (Store
Complement
of Data)

L

L

High Impedance

Read

L

H

Stored Data

Inhibit

H

X

High Impedance

Irrelevant
t = For memory enable; L = All ME inputs low'
H

OUTPUT

FUNCTION

~

High Level, L = Low

L.Y~I,

X=

H .,. One or more ME inputs high

2-154

~

MSI

DM54/DM74S200

Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted)
DM54S/74S
CONDITIONS

PARAMETER

S200
MIN

V 1H

High Level! nput Voltage

V ,L

low Le'V!(lln p ut Voltage

V,

Input

10H

High Level Output Current

UNITS

TVP(l}

MAX
V

2.0

C!a~p Voltage

i.

Vee"" Min,

= -18 rnA

I DM54

High Level Output Voltage

10L

Low Level Output Current

VOL

Low Level Output Voltage

IO(OFF~

Vee"" Min,

V 1H

V 1L =O.BV,

'OH =

Vee'" Min,

V,H

V 1L =O.BV,

IOL

=

V

-1.2

\I

-2.0

I DM74

VOH

0.8

--5.2

2V

2.4

Max

\I

16

Off-State (High Impedance State) Output Current

Vee

=

Max

V 1H

""

2.0V

= 2V
= 16 mA

I DM54
I DM74

V

0.45

I Va = OA5V

-50

I Va:= 2.4V

50

Vee =Max,

VI"" 5.5V

1.0

I'H

High Level Input Current

Vee

Max,

V,

= 2.7V

I'L

Low Level Input Current

Vee =Max,

V,

= 0.45V

loS

Short Circuit Output Current

Vee;::: Max{2)

Icc

Supply Current

Vee

=

mA

0.5

Input Current at Maximum Input Voltage

I,

rnA

-30

= Max(3}

87

)1A
mA

25

)1A

--250

)lA

-100

mA

130

mA

Notes
{21

All typical values are at V CC ~ 5V, T A ~ 25" C_
Not more than one output should be shorted at a time, and duration of short circuit should not exceed one second.

(3)

ICC is measured with the write enable and memory enable grounded, all other inputs at 4.5V and the output open.

(1)

Switching Characteristics v cc = 5V, T A = 25° C
DM54S/74S
PARAMETER

CONDITIONS

54S200
MIN

tPLH

tPHl

tZH

Propagation Delay Time,

Access Time From

Low-to-High Level Output

Address

Propagation Delay Time,

Access Time From

High-te-Low Level Output

Address

Output Enable Time To
High level

Access Time From
Memory Enable
CL

tze
tZH

tZL

'HZ

tLZ

Output Enable Time To

Access Time From

low Level

Memory Enable

Output Enable Time To

Sense Recovery Time

High Level

From Write Enable

Output Enable

Tim~

To

From Write Enable

Output Disable Time From

Disable Time From

High Level

Memory Enable

Output Disable Time From

Disable Time From

Low Level

Memory Enable

tLZ

Output Disable Time From

Disable Time From

High Level

Write Enable

Output Disable Time From

Disable Time From

Low Level

Write Enable

tw

Width of Write Enable Pulse

tSETUP

Setup Time

= 5.0 pF,

RL

UNITS

TVP

MAX

70

33

50

ns

29

70

29

50

ns

21

45

21

35

'"

10

30

10

20

05

24

50

24

40

ns

12

50

12

40·

ns

7.0

30

7.0

20

ns

20

45

20

35

ns

13

40

13

30

os

16

40

16

30

os

= 280n

50

~-

Address to Write Enable

0

Data to Write Enab!e

Hold Time

33

MIN

-

Memory Enable to Write Enable
tHOLD

MAX

15pF, R! " 280[2

Sense Recovery Time

Low Level

CL
tHZ

:::

74S200

TVP

0

40

ns

0
0
0

ns

Address From Write Enable

10

10

Data From Write Enable

10

10

Memory Enable to Write Enable

0

0

2-155

ns

I

~··MSI

OM54/0M74S200

AC Test Circuit

Vee

TEST
POINT
FROM

O~J~~~ -~--...-IIOIIII-'"
TEST

CL includes probe and jig capacitanct.
All diodes are 1NlO&4.

Switching Time Waveforms
3.0V
ADDRESS
INPUT
ISEE NOTE BI

3.0V
ADDRESS
INPUTS

VOH - " " ' - - 3.0V

OUTPUT
DATA
INPUTS

VOL----------__--,~--------__J

3.DV
MEMORY
ENABLE
INPUTS

3.0V
MEMORY ENABLE
INPUTS ISEE NOTE CI

WRITE
ENABLE
INPUT

Ov----r'------------J

3.DV

OV
~1.5V

WAVEFORM 1
(SEE NOTE Al

WAVEFORM 1
ISEE NOTE Al

VOL
VOH
WAVEFORM 2
(SEE NOTE Al

WAVEFORM 2
(SEE NOTE AI
~1.5V----J.

Notes:
(A) Waveform 1 is for the output with internal conditions such that the output is low ex~pt whe,n disabled. Waveform 2 is for the output with internal conditions such that the output is high except when disabled.
.
(B)

When measuring delay times from address inputs, the memory enable inputs are low and the write enable input is high. ,

When measuring delay times from memory enable inputs, the addres. inpu~s are steady-state and the write enable input is high.
(01 Input waveforms are supplied by pulse generators having the following characteristics: tr:S: 7 ns, tf:S: 7 ns, PRR:S: 1.0 MHz, 8.nd
ZOUT '" 50.0..
(e)

.2,156

~ MSI

OM54/0M74S206
256-Bit Read/Write Memories with Open Collector Outputs

General Description
Read Cycle: The stored information (complement of
information applied at the data input during the write
cycle) is avai'lable at the output when the write-enable
input is high and the three memory-enable inputs are
low. When anyone of the memory enable inputs is
high, the output will be off.

The DM54S206/DM74S206 256-bit active-element memories are monolithic transistor-transistor logic (TTL)
integrated circuits organized as 256 words of one bit
each. They are fully decoded and have three gated
memory·enable inputs to simplify decoding required to
achieve the desired system organization_ The memories
feature PNP input transistors which reduce the lowlevel input current requirement to a maximum of
--D_25 milliamperes, only one-eighth that of a normal Series 54S/74S load ftlctor, The memory-enable
circuitry is implemented with minimal delay times to
compensate for added system decoding.

Features
• Schottky-clamped for high-speed memory systems:
17 ns typ
Access from memory-enable inputs
Access from address inputs
35 ns typ
Power dissipation
1.4 mW/bit typ
• Open-collector output for word expansion
• Fully decoded, organized as 256 words of one bit
each
• Compatible with most TTL and DTL logic circuits
• Multiple memory-enable inputs to minimize external
decoding

Write Cycle: The complement of the information at
the. data input is written into the selected location
when all memory-enable inputs and the write-enable
input are low_ While the write-enable input is low,
the output is off.

Connection Diagram

Logic Diagram
ADDRESS
INPUTS

10

1111

G

1

1101

ADDRESS
INiJUTS

F
E (9)

o 171
A

B

~

MEl

MEl

ME3

OUTPUT

0

V

ADDRESS
INPUT

ADDRESS
INPUTS

GNO

54S206IJ), (W); 74S206(JI. (N), (W)

Truth Table
INPUTS
OUTPUT

FUNCTION

MEMORY
ENABLEt

WRITE
ENABLE

Write (Store
Comolement

L

L

Hi-Z

Read

L

H

Stored Data

Inhibit

H

X

Hi-Z

of Data)

H

=

hIgh level, L

=

low level, X::: irrelevant

tFor memory enable: L

=

all ME inputs low;

H "" one or more ME inputs high.

'~'MSI

DM54/DM74S206

Electrical Characteristics

over recommended operat'ing

fr~e-air temperature

range (unless otherwise noted)
DM54S/74S

PARAMETER

CONDITIONS

V,H

High Level Input Voltage

V,L

Low Level I nput Voltage

V,

Input Clamp Voltage

IOH

High Level Output Current

TYP(1)

Vee = Min, V ,H = 2V
. V'L = 0.8V

Low Level' Output Curr1!nt

VOL

Low Level Output Voltage

IV/AX
V

2

. Vce = Min, I, =-18 mA

IOL

UNITS

S206
MIN

0.8

.V

-12

V

V OH = 2.4V
V OH = 5.5V

40
100
16

Vee = Min, V ,H = 2V

DM54

0.5

V'L = 0.8V, IOL = 16 mA

DM74

0.45

,!,-A
mA
V

I,

Input Current at Maximum Input Voltage

Vee = Max, V, = 5.5V

1

mA

I'H

High Level I nput Current

Vee = Max, V, = 2.7V

25

.!'-A

I,L

Low Level I nput Current

Vee = Max, V, = 0.45V

-:250

!'-A

Icc

Supp'y Curre'!t

Vee = Max(2)

130

mA

70

Notes
(1) All typical values are at Vcc = 5V, TA = 25°C.
(2)

ICC is measured wit~ the write enable and mem-ory enable inputs grounded, all other inputs at 4.SV, and the output open.

Switching Characteristics vee

=5V, TA = 25°C
DM54S174S

PARAMETER

tPLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tPLH

tpHL

tpLH

74S206

MIN TYP MAX

MIN TYP MAX

Access Times from Address

38

80

38

60

ns

Access Ti mes from Address

32

80

32

60

ns

21

45

21

35

ns

13

35

13

25

ns

20

50

20

40

ns

14

50

14

40

ns

Disable Time fr0'1:'

Low-to-High Level Output

Memory Enable

Propagation Delay.Time,

Enable Time from

High-to-Low Level Output

Memory Enable

Propagation Delay Time,

Disable Time from

Low-to·High Level Output

Write Enable

tSR

Sense Recovery Time

tw

Width of Write Enable Pulse

tSETUP Setup Time

tHOLD

54S206

Propagation Delay Time:

Hold Time

Addres~

CONDITIONS

CL = 15pF

UNITS

RL =3000

50

to Write Enable

40

0

0

Data to Write Enable

0

0

Memory Enable to Write Enable

0

0

Address from Write Enable

10

10

Data from Write Enable

10

10

Memory Enable to Write Enable

0

0

2-158.

ns

ns

ns

~ MSI

DM 54/ DM74S206

AC Test Circuit

Vee

TEST
POINT
FROM

O~;~~~

--4....- -. .

TEST

c[

1.0k

CL includes probe and jig capacitance.

Switching Time Waveforms
WRITE CYCLE

ADDRESS
INPUTS

DATA
INPUTS

MEMORY-ENABLE

3V

3V

3V

INPUTS

WRITE·ENABLE

3V

INPUT OV
tecH

OUTPUT VO "
(NOTE A) VOL

J

ACCESS (ENABLE) TIME AND

t

LSV

ACCESS TIME FROM ADDRESS INPUTS

DISABLE TIME FROM MEMORY ENABLE

ME~~~~~ 3V
(~~~~T;I ov ___+ ...1._5V_~_ _ _ __

tSR~

1.5V

AODRESS 3V~------""
INPUTS
1.5V
)j(,.5V

1.5V

(NOTE 8)

. t'"e
t'y.;-eH
OUTPUT VOH - - - ; " " ' - 1.5V
1.5V
(NOTE AI Voe _ _ _ _ _ _ _"'-_ _ _ _ _'"

OUTPUT

ov __ J
OH

V

t'He::1

---'--_·

~5V

:'.{';·,:-F-='
)/,.SV

Voe------~~·~-----"'·

Notes:
(A) Waveform shown is for the output with internal conditions such that the output ;s low except when disabled.
(B) When measuring delay times from address inputs, the memory-enable inputs are low and the write-enable input is high.
(C) When measuring delay ~jmes from memory-enable inputs, the address inputs are steady-state and the write-enable input is high.
(0) Input waveforms are supplied by pulse generators having the following characteristics: tr ~ 2.5 ns;tf ~ 2.5 ns, PRR ~ 1 MHz,
and ZOUT ~ 50n.

2-159

~MSI

DM54/DM74251.lS251.S251
TRI-STATE Data Selectors/Multiplexers

General Description

Features

These data selectors/multiplexers contain full on-chip
binary decoding to select one-of-eight data sources, and
feature a strobe-controlled TRI-STATE output_ The
strobe must be at a low logic level to enable these
devices_ The TRI-STATE outputs permit direct connection to a comman bus. When the strobe input is high,
both outputs are in a high-impedance state in which
both the upper and lower transistors of each totem-pole
output are off, and the output neither drives nor loads
the bus significantly. When the strobe is low, the
outputs are activated and operate as standard TTL
totem-pole outputs.

•
•
•
•
•

To minimize the possibility that two outputs will
attempt to take a common bus to opposite logic I.evels,
the output control circuitry is designed so that the
average output disable time is shorter than the average
output enable time.

,54251

Connection Diagram

Truth Table

DATA INPUTS
D5

04

/16

15

MAX NO. OF
TYPE

COMMON
OUTPUTS

2
02

A

07

17 ns
17 ns

155mW

129

49

49

17 ns

35mW

74LS251

129

745251

129

17 ns
8 ns

275mW

4
DO

155mW
35mW

C\

11

12

13

3
01

POWER
DISSIPATION

74251
54LS251

10

,

INPUTS

-1

TYPICAL

(DTOY)

SELECT

03

TYPICAL
PROP DELAY
TIME'

DATA SELECT

06

14

TRI-STATE versions of 151, LS151, S151
Interface directly with system bus
Perform parallel-to-serial conversion
Permit multiplexing from N-lines to one line
Complementary outputs provide true and inverted
data

~------Y-------~
DATA INPUTS

5

6

Y

W

~
OUTPUTS

7
STROBE

I'

'C

B

X
l

OUTPUTS
STROBE

Y

A

S

x

X

H

Z

L

l

L

DO

W
Z
-,

l

L

H

L

Dl

L

H

L

l

D2

DO

-

Dl

52
-

L

H

H

l

D3

D3

H

L

L

l

D4

H

L

H

L

D5

D4
D5

H

H

l

l

D6

H

H

H

L

D7

-

Os

-

D7

GND

54251(JI. (WI; 74251(J), (N), (W);
54LS251/74LS251 (J), (N), (W); 74S251(N)

H

= High

X

= Don't Care, Z = High Impedance (Off)

Logic Level, L

= Low

Logic Level

DO, 01 .. _07 = The level of the respective 0 input.

Logic Diagram
STROBE (7)
(ENABLE)

DO . :;14::. 1----r=:::::=33-,

D2~12~1--------i~F=*=~rDJ~I1~I--________-t~~~~~
DATA

INPUTS

D4 (151

D5~11~41-----------t~3E~~~

-----l=I=I=FI==l=l=t-,

11 31
D8..:::::

DATA
SElECT
(BINARY)

I
2-160

LS251, S251 To Be Announced In 1976

Electrical Characteristics

DM54/74
PARAMETER

CONDITIONS

V,H

High Level Input Voltage

V,l

Low Level Input Voltage

IOH'

VOH

IOl

VOL

Input Clamp Voltage

Vee = Min

Low Level Output Voltage

I,

I'H
I,l

Low Level Input Current

IQS

Short Circuit Output Current

Icc

Supply Current

0_8

0_8

1.5

1_2

-1.5

DM54

-2

-1

--5_2

-2_6

2.4

Vee = Max

Vee = Max

Vee = Max

IOL = Max

N/A

V

V

mA

V

3.2

DM54

16

4

N/A

DM74

16

8

20

DM54

0.4

0.25

0.4

DM74

0.4

0.35

0.5

N/A
0.5

mA

V

0.4
-40

-20

Vo -2.4V

40

20

V, = 5.5V

1

--50

0.1

V, = 2.4V

40

V, - 2.7V

50

20

V, = OAV

-1,6

-0.4

V, =0.5V

-2
-18

--55

-30

-130

-100

-40

Strobe Grounded

31

51

6.1

10

55

85

Strobe at 4.5V

31

51

7.1

12

55

85

Notes
(11 All typical values are at VCC = 5V, T A = 25° c.
(2) Not mOre than one output should be shorted at a time, and for DM54lSn4LS or DM745 duration of short circuit should not exceed one second.
(3) All outputs open,all inputs at 4.5V.

IlA

50
1

V , -7V

Vee = Max(2)
Vee = Max(3)

N/A
-6.5

2.4

IOL=4mA DM74

V'L = Max

High Level Input Current

0_8

2.4

Vo =0.4V

V

2

DM74

~

en

MAX

DM74

2.4

Vo -0.5V

TYP(l)

N/A

2.4

V'H =2V

MIN

0_7

DM74

Vee = Max

UNITS

S251
MAX

2

DM54

Off-State (High Impedance

Input Voltage

TYP(1)

0_8

V'L = Max. IOH = Max

State) Output Current

Input Current at Maximum

MIN

Vee = Min, V'H = 2V

V'L = Max
IOIOFfI.

LS251
MAX

1,--18mA

Vee = Min, V'H = 2V

DM74S

DM54

I, =-12 mA

Low Level Output Current

~
!!1

TYP(l)

2

High Level Output Current

High Level Output Voltage

DM54LS/74LS

251
MIN

V,

~

over recommended operating free-air temperature range (unless otherwise noted)

mA

IlA

C

~
.po

U1

......
mA

!11A
rnA

C

~

~

N

...
...
en
...

U1

ien
N

U1

N

U1

~

Switching Characteristics Vee

=

-~

5V, TA = 25°C

I

PARAMETER

FROM
(INPUT)

DM54174

DM54LS/74LS

DM74S

251

LS251

S251

TO
(OUTPUT)
CONDITIONS

tplH

Propagation Delay Time,
Low-to-High Level Output

A,8,orC

~l

Propagation Delay Time,

(4 levels)

Propagation Delay Time,
Low-to-High Level Output

tPHl

Propagation Delay Time,

A,B,orC
(3 levels)

Propagation Delay Time,
Any D

tplH

Propagation Delay Time,
CL
RL

Propagation Delay Time,

= 50 pF
= 400Q

Low-to-High Level Output

~

Any D
tpHl

Propagation Delay Time,

Output Enabie Time to
High Level
Strobe

tZl

Output Enable Time to

Output Enable Time to

Output Enable Time to

Output Disable Time from
High Level
Strobe

tlZ

tHZ

= 5 pF

CL

Output Disable Time from

RL =400Q
Strobe

Low Level

28

45

13

19.5

ns

18

29

20

33

10

15

ns'

16

27

21

33

9

13.5

ns

8

12

ns

= 15pf
RL = 280Q

17

28

18

28

17

28

CL
RL

= 15pf
= 2 kQ

18

28

8

12

ns

10

15

4.5

7

ns

11

15

10

15

9

15

4.5

7

ns

15

27

30

45

13

'19.5

ns

18

36

26

40

14

21

ns

= 50 pF
RL = 280Q

27

17

27

e

~

13

19.5

ns

19

38

24

40

14

21

ns

4

8

30

45

5.5,

8.5

ns

14

23

15

25

9

14

ns

(J'1

~

"·0
~

~

N

(J'1

. ....A

Low Level

Output Disable Time from

36

y

Output Disable Time from

High Level
tlZ

23

W

Low Level

"

ns

15
Strobe

tHZ

18

MIN

CL

High Level
tZl

MAX

12

CONDITIONS

y

Low Level
tZH

TYP

45

W

High-to-Low Level Output
tZH

MAX

29

MIN

Y

High-to-Low Level Output

~

TYP

36

CL

Low:to-High Level Output
tpHl

MAX

22

W

High-to-Low Level Output
tplH

.'

TYP

CONDITIONS

-

0

Y

High-to-Low Level Output
tplH

MIN

~

UNITS

CL

= 5 pF

CL
iRL

RL = 2kQ
4

8

37

55

15

23

15

25

= 5 pF
= 280Q

r-0
N

....
(J'1

5.5

8.5

ns

9

14

ns

.0

W

N

(J'1
....A

~ MSI

DM54/DM74LS253,S253
TRI-STATE Data Selectors/Multiplexers

General Description
Each of these Schottky-clamped data selectors/multiplexers contains inverters and drivers to supply fully
complementary, on-chip, binary decoding data selection
to the AND-OR gates_ Separate output control inputs
are provided for each of the two four-line sections_

•
•
•
•

The TRI-STATE outputs can interface directly with data
lines of bus-organized systems_ With all but one of the
common outputs disabled (at a high impedance state),
the low impedance of the single enabled output will
drive the bus line to a high or low logic level.

Permits multiplexing from N lines to 1 line
Performs parallel-to-serial conversion
Strobe/output control
High fan-out totem-pole outputs

Features

LS253

• TRI-STATEversion of LS153,S153with same pin-out
• Schottky-diode-clamped transistors

S253

Connection Diagram

TYPICAL PROPAGATION DELAY

TYPE

Data to Output
Select to Output
Data to Output
Select to Output

TYPICAL
POWER
DISSIPATION

12 ns
21 ns
6 ns
12 n5

35mW
275mW

Truth Table
SELECT
INPUTS

OUTPUT
CONTROL

DATA INPUTS

OUTPUT

B

A

CO

C1

C2

C3

G

V

X

X

X

X

X

H

Z

L

L

L

X
X

X

X

L

L

L

L

H

X

X

L

H

L

H

X

L

X

X
X

L

L

L

H

H

X

x

L

H

H

L

X
X

X

L

L

L

L

H

H

L

L

L

H

H

X
X
X

H

H

X
X
X

X
X

l

H

H

L

H

X
X

Address inputs A and B are common to both sections.
H == High Level, L == Low level. X = Don't Care.
Z

= High

Impedance

54LS253/74LS253(JI, (N), (WI; 74S253(NI

Logic Diagram
OUTPUT (1)
CONTROL 61

.ATA 1\'C'

(s)

102 "I"'·}--------i-++tt......-

1C3 ..1;3 ;:.1----;:==:::t:tti-l-SELECT [

:lCt (11)

2C2 ..:.ll~21"-__________-;~::~~~

2C3~"--_:_----t=t:==*::r~

OUTPUT (15)
CONTROL G2

J

. - - - - - - 2-163

5253 To Be Announced In 1976

~MSI

OM54/0M74LS253.S253

Elej:trica' Characteristics

over recommended' operating free-air temperature range (unless otherwise ~oted)
DM74

DM54Lsn4LS
LS253

CONDITIONS

PARAMETER

TYP(l)

MIN
V,H

High Level Input Voltage

V,l

Low level Input Voltage

I nput Clamp

10H

High Level Output Current

VOH

2

Volt~ge

V,

Vee

V,L
10l

Val

:=

=

Min, V ,H

Max,

Low. Level Output Voltage

1010FFI

Vee

:=

High Level Input Current
,Low Level Input Current

-LS

-1.2

DM54

-1

DM74

-2.6

N/A
-6.S

3.4
3.1

..

""

2V

Max

4

DM74

8

DMS4
DM74

0.4
O.S

IOL ,., 4 rnA DM74

0.4

Vee

=Max. V,

los

Short Ci rc~ it Output Current·
Supply Current

Vee

Vee

Vo

:=

Ma>:

V,

=OAV
=2AV
=5.5V
=7V

V
N/A
20

mA

N/A

20

0.5

V

50

pA

50

1.0
0.1
50

20
-0.36

V, =OAV

=0.5V

2

= Max(2)
=Max(3)

mA

-20

= 2.7V

V,

V

3.2

Vo = O.SV

V,

Vee'" Max

Icc

IOL

V

N/A,

V

DM54

Vo

Vee .. M~x

Input Voltage

I,l

0.8

2.4

= 2V

Min. V 1H

Vee = Max, V 1H

V1L

Input Current at Maximum

I'H

0.8

2.4

Off-State (High-Impedance State)
Output Current

I,

DM74

DM74

V'L = Max

V
N/A,

DM54

.,

MAX

2

2V

Low Level Output CU'rrent

TYP(l)

0.7

= Max

='

IOH

MIN

I DM~4
Vee = Min, I, .. -18 rnA

High Level Output Voltage

UNITS

S253
MAX

-30

-130

Condition A

7

12

Condition B

8.5

14-

-40

-100

mA
pA
mA
mA

mA
55

All Outputs Open

70

Notes
(1) All typical values are at Vce = 5V. TA = 25°C.
(21 Not more than on~ output should be shorted at a time, and duration of short circuit should not exceed one second.
(31 ICC is measured with 'the outputs open under the following conditions;
A. All inputs grounded.
B. Output control at 4.5V. all inputs grounded.
(4) National S.mi~onductor temporarily reserves the right to ship DM54/DM74LS253 devices which have a minimum iOS = 5.0 rnA.

Switching Characteristics vee

= SV. T A = 2SoC
DM74

DM54Lsn4LS

,

PARAMETER

FROM
(iNPUT)

TO
(OUTPUT)

LS253
CONDITIONS

tplH

Propagation Delay Time,
Low-to-High Level Output

tPHL

Propagation Delay Time,

Propagation Delay Time,
I

Select
tpHL

Y

Propagation Delay Time,

CL = 15 pF
Rl = 2 kn

High-ta-Low Level Output
tZH

Output Enable Time
to High Le,vel

tZl

Output Enable

Output
Tim~

MAX,

17

25

13

20

CONDITIONS

Cl
Rl

Low-to-High Level Output

Control

UNITS

S253
TYP

MIN

TYP

MAX

6

9

ns

6

9

ns

11.5

18

ns

12

18

ns

13

19.5

ns

1'4

21

ns

5.5

8.5

ns

9

14

ns

Y

Data
High-to-Low Level Output
tPLH

MIN

30

45

21

32

15

23

Y
1.5

23

27

41

= 15 pF
= 280n

Cl
RL

=50 pF
=280!)

Cl

= 5 pF

to low level
tHZ

tlZ

.output Disable Time
From High Level

Output

'Output Disable Time

Control

Y

='5 pF
Rl = 2 kn

Cl

From Low level

2-164

18

27

RL = 280!)

~·MSI

OM54/0M74LS257.S257.LS258.S258
TRI-STATE Quad 2-0ata Selectors/Multiplexers

General Description

Features

These Schottky-clamped high-performance multiplexers
feature TRI-5TATE outputs that can interface directly
with data lines of bus-organized· systems. With all but
one of the common outputs disabled (at a high impedance
state I. the low impedance of the single enabled output
will drive the bus line to a high or low logic level. To
minimize the possibility that two outputs will attempt
to take a common bus to opposite logic levels, the output
enable circuitry is designed such that the output disable
times are shorter than the output enable times.

• TRI-5TATE versions L5157. 5157, L5158, 5158,
with same pin-outs
• Schottky-clamped for significant improvement in
A-C performance
• Provides bus interface from multiple sources in highperformance systems

This TRI-5TATE output feature means that n-bit
(paralleled) data selectors with up to 258 sources can
be implemented for data buses. It also permits the use
of standard TTL registers for data retention throughout
the system.

TYPE

AVERAGE PROPAGATION
DELAY FROM
DATA INPUT

TYPICAL
POWER
DISSIPATION

LS257
LS258
5257
5258

12 n.
12 ns
4.8 ns
4';.

SOmW
35mW
320mW
280mW

Connection and Logic Diagrams

.

INPUTS

Vee

OUTPUT
CONTROL

1,6

.r--....-....,
B4

A4
14

15

INPUTS
OUTPUT
V4

13

A3
11

12

OUTPUT
V3

B3
10

-

2

A1

4

3

Bl

VI

6

5

A2

B2

OUTPUT
INPUTS

7
V2
OUTPUT

OUTPUT
CONTROL

1,6

9

r-

1

SELECT

Vee

A4

15

OUTPUT
V4

B4

12

13

14

INP)JTS
A3

OUTPUT
V3

B3
11

p-

~

I

18

GNO

9

10

81

6

5

VI

A2

OUTPUT

INPUTS

INPUTS

4

3

2

AI

SELECT

B2
INPUTS

7
V2
OUTPUT

P

GNO

54L5258/74LS258(JI. (NI, (WI; 74S258(NI

54LS257/74LS257(JI, (NI. (WI; 7,4S257(NI

LS258.S258

LS257.S257
OUTPUT (15)
CONTROL

OUTPUT (15)
CONTROL

Al~~~I_·_ _ _ _----~~

Al~----------r~

+-_______

Bl~(3~1_ _ _

~~

A2~(5)~_ _~~_ _ _+-~~

B2 (61

A3 (111

+-______+-~~

B3~110~1______

+-______+-~~

A4~114~1______
V4

B4~(13~1_ _ _; -_ _ _-+-r~

V4

To S_ Announced In 1976

Electrical Characteristics

~

over recommended operating free-air temperature range (unless otherwise noted)
DM54lS/74lS

DM74S

lS257, lS258

S257, S258

TYP(l)

TYP(1)

!

PARAMETER

CONDITIONS

MIN
V ,H

High Level 'Input Voltage

V,L

Low Level Input Voltage

V,

I nput Clamp Voltage

10H

High Level OUtput Current

VOH

Vee

High Level Output Voltage

Vee

V 1L
10L

VOL

:::m
m

~

Min, I,

Current

Maximum Input Voltage

I,L

Low Level Input Current

. 1.5

-12

--10

DM74

-2.6

-6.5

2V

DM54

2.4

3.4

N/A

Max

DM74

2.4

3.1

2.4

~

Min, V ,H

~

2V

Max

Vee =-- Max

Vo~O.4V

V ,H

Vo~0.5V

~

2V

IOL

= Max

laL

~

4 mA

4

N/A

DM74

S

20

DM54

0.25

0.4

N/A

DM74

0.35

0.5

'0.5

DM74

0.25

0.4

~

V,

~7V

V,

~

~

-50
20

0.2
1

S Input
Vee'; Max

Any Other

V,

o·

0.5V

V,

~

OAV

Short Circuit Output Current

ICC

Supply Current

50

20

50

All Outputs Off
All Outputs Low
All Outputs Off

~

mA

0

IlA

(J)

Max(3)
LS258,S258

-130

s:.....
r-

N

.....
mA

-40

-100

5.9

10

44

68

9.2

16

60

93

10

17

64

99

4.1

7

36

56

6.2

11

52

81

7.0

12

56

87

(J)

N
U1

2

LS257, S257
Vee

~

-2

All Outputs High

All Outputs High

U1

U1

-{).4

--30

0
~
.......

-{)S

Vee ~ Max!21

All Outputs Low

Il A

~

40

V, " 0.5V
lOS

V

0.1

Max, V, o2.7V
OAV

mA

1

5.5V

~

mA

50

5.5V

V,

V

-20

Vo~2.4V

V,

V

V

3.2

DM54

V, - 7V
Vee

N/A

=

Vee:::: Max

Any Other

0.8

=:

S Input

S Input

0.8

Min, V 1H

Any Other
High Level"lnput Curre~t

DM74

Max, IOH

V1L=Max
I nput Current at

N/A

=

Lqw Level Output Voltage

Vee

0.7

DM54

~

(J)

V

2

DM54

-18·mA

Low Level Output Current

10lOFFI Off State (High Impedance State I Output

I'H

~

MIN

::::

V'L

I,

MAX

2

UNITS
MAX

mA

:-oJ
r(J)

N
U1
(X)

mA

(J)

N
U1

00

Switching Characteristics vee

~ 5V, T A,~ 25°C

~
DM74S

DM54LS/74LS
FROM
(INPUT)

PARAMETER

TO
(OUTPUT)

CONDITIONS
tpLH

Level Output

tZH

tZL

7 ~5

4

6

ns

12

18

4,5

6.5

4

6

ns

Any

~

14

21

8~5

15

8

12

ns

R L ~

14

21

8,5

15

7.5

12

ns

20

30

13

19.5

13

19.5

ns

Control

20

30

14

21

14

21

ns

tHZ

20

30

5.5

8.5

5,5

8.5

ns

0
~

9

14

9

14

ns

.......

2 krl

tLZ

Output
Control

Output Disable Time

15 pF

RL ~

280rl

Any

Output Disable Time
From High Level

~

CL

15 pF

Low Level

en

~ -.J

Output Enable Time to

CL

Any

~

RL ~

5 pF

CL

~

5 pF

RL ~

2 kn

17

From Low Level

25

(2)
(3)

280n

(11
~

0
~

Notes
(1)

MAX

5

Output Enable Time to
Output

TYP

18

Level Output

High Level

~

CL

Propagation Delay Time,
High~to~Low

MAX

MIN

12

Level Output

Select

TYP

Any

Propagation Delay Time,
Low~to~High

MIN

C/)

MAX

Propagation Delay Time,
High~to~Low

tpHL

CONDITIONS

~
UNITS

S258

TYP

Level Output
Data

tpLH

MIN

Propagation Delay Time,
Low~to~High

tpHL

S257

LS257, LS258

.....

All typical values are at Vee 5V, T A:::; 25° c.
Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
ICC is measured with all outputs open and all possible inputs grounded, while achieving the stated output conditions.

~

0:;

r-

C/)

N
(11

.....

Truth Table

C/)

OUTPUT Y

I~JPUTS

OUTPUT
CONTROL

SELECT

H

x

X

L

L

L

L

L

H

L
L

H
H

LS258
S258

~

x

Z

z

C/)

X

L

H

N

X

H

L

X

L

L

H

.00

X

H

H

L

A _ B

H = High Level, L :::; Low Level, X :::; Don't Care,

Z
_._--

._-

-

~

~

High Impedance (off)
--~

N

(11

LS251
S257

r-

(11

C/)

N

(11

00

,~ MSI

DM54/DM74lS279
Quad

General Description

Features

These latches are ideaily suited ·for use as temporary
storage of bfnary information between processing units
and I/O units. When either one of the data inputs is at
a low logic level, the output will follow the level of the
R input. When both data inputs are high, the output will
remain latched in its previous state. When both inputs
are low, the output will .go high. However, this high
level may not persist when either one of the data inputs
returns to the high state.

•

S-R

latches

For more advanced design S·R latches, see
DM7544/8544

• Typical power dissipation

19 mW

• Typical propagation delay

12 ns

Connection Diagram

Rl

181

iS1

Ql

R2

82

Q2

GND

54LS279174LS279(J), (N), (W)

Truth Table

INPUTS

-

OUTPUT

R

Q

H

H

Go
H

Sf

L

H

H

L

L

L

L

H*

H =' High Level
L::;: Low Level
0 0 ::;: The·level of Q before the indicated input conditions were
established .

.. This outpyJ leveUs pseudo stable: that is, it may not persist
when the Sand R inputs return to their inactive (high) level.
T For latches with double S inputs:
H = both S inpu~ high
L ::;: one or both S inputs low

2·168

To Be Announced In 1976

~

OM 54/ OM74LS279

MSI

Electrical Characteristics over recommended operating free·air temperature range (unless otherwise noted)
DM54LS/74LS
PARAMETER

MIN
V1H

High Level Input Voltage

V 1L

Low Level Input Voltage

VI

Input Clamp Voltage

10H

High Level Output Current

VOH

High Level Output Voltage

= Min, I,

Vee

=

MAX
V

DM54

0.7

DM74

0.8
-1.5

-18 mA

-400
Vee

= Min, V ,H = 2V
= Max, IOH = -400pA

Low Level Output Current

= Min
= 2V
V ,L = Max

Low Level Output Voltage

VOL

TYP(1)

2

V ,L
10L

UNITS

LS279

CONDITIONS

Vee

DM54

2.5

3.5

DM74

2.7

3.5
4

DM74

8
0.25

0.4

0.35

0.5

Input Current at Maximum
I nput Voltage

Il A

mA

V

V ,H

II

V

V

DM54

IOL=4mA

V

IOL

Vee

= Max, V, = 7V

= 8 mA

DM74

0.1

mA

IIH

High Level I nput Current

Vee

= Max, V, = 2.7V

20

pA

IlL

Low Level Input Current

Vee

= Max, V, = O.4V

--0.4

mA

los

Short Circuit Output Current

Vee

= Max(2)

-130

mA

Icc

Supply Current

Vee

= Max (3)

7

mA

-30
3.8

Notes

= 5V, TA = 25°e.

(1)

All typical values are at Vee

(2)

Not mOre than one output should be shorted at a time, and duration of short circuit should not exceed one second.

(3)

ICC is measured with all

R inputs grounded, all S inputs at 4.5V, and all outputs open.

,
Switching Characteristics Vee

= 5V, T A = 25°C

PARAMETER
tpLH

CONDITIONS

MIN

TYP

MAX

UNITS

12

22

ns

9

15

ns

15

27

ns

Propagation Delay Time,
Low·to-H igh Level

----

Output From S Input
tPHL

Propagation Delay Time,
High·to-Low Level

I Output From S Input

--

= 15 pF
RL = 2 kD.

CL

-~-tpHL Propagation Delay Time,

I High-to-Low

~evel

Output From R Input

2·169

~ MSI

DM74S280i
9-Bit Parity Generators/Checkers

General Description
Input buffers are provided so that each input represents
only one normal 74S load, and full fan-out to 10 normal
Series 74S loads is available from each of the outputs at
low logic levels. A fan-out to 20 normal Series 74S loads
is provided at high logic levels, to facilitate connection
of unused inputs to used inputs.

These universal, nine·bit parity generators/checkers utilize
Schottky-clamped TTL high-performance circuitry, and
feature odd/even outputs to facilitate operation of either
odd or even parity applications. The word-length
capability is easily expanded by cascading.
The S280 can be used to upgrade the performance of
most systems utilizing the DM74180 parity generator/
checker. Although the S280 is implemented without
expander inputs, the corresponding function is provided
by the availability of an input at pin 4, and no internal
connection at pin 3. This permits the S280 to be substituted for the 180 in existing designs to produce an
identical function, even if S280's are mixed with
existing 180's.

Features
• Generates either odd or even parity for nine data lines
• Cascadable for n-bits
• Can be used to upgrade existing systems using MSI
parity circuits
• Typical data-to-output delay--14 ns

Connection Diagram

Truth Table
INPUTS

114

13

12

11

10

-

,

r-

1

2

-----...-...G

,

9

H

rNPU1S

I'

NC

4
I
INPUT

•

5
1

EVEN

I'

GNO

ODD

OlJTPUTS

74S280{N)

Logic Diagram

2-170

OUTPUTS

NUMBER OF INPUTS (A
THRU I) THAT ARE HIGH

LEVEN

0,2.4,6,8

H

L

1. 3, 5, 7, 9

L

H

L ODD

~

DM74S280

MSI

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
DM74S
CONDITIONS

PARAMETER

VIH

High Level Input Voltage

VIL

Low Level I nput Voltage

VI

Input Clamp Voltage

10H

High Level Output Current

VOH

High Level Output Voltage

Low Level Output Current

VOL

Low Level Output Voltage

Ii

MAX
V

~

Min,

II

~-18ITlA

0.8

V

-1.2

V

-1
Min,

V IH

~

V IL ~ 0.8V,

IOH

~-1

Vee

Input Current at Maximum
I nput Voltage

~

2V
mA

Vee'" Min,

V IH = 2V

V IL = 0.8V,

IOl = 20 mA

Vee = Max,

VI

~

2.7

Vee

= Max,

VI

= 2.7V

IlL

Low Level Input Current

Vee

= Max,

VI

= 0_5V

los

Short Circuit Output Current

Vee

= Max(2)

Icc

Supply Current

Vee

= Max(3)

mA
V

3.4

5.5V

High Level I nput Current

IIH

TYP(1)

2

Vee

10L

UNITS

S280
MIN

-4.0

20

mA

0.5

V

1

mA

50

/lA

-2

mA

-100

mA

105

mA

67

Notes
(11
(2)
(3)

All typical value •• r. at VCC = 5V, TA ~ 25"C.
Not more than one output should be shorted at a tim.e, and duration of the short circuit should not exceed one second.
ICC is measured with all inputs grounded and all outputs open.

Switching Characteristics

Vee

= 5V,T A = 25°C
DM74S

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

CONDITIONS

S280
MIN

tpLH

Propagation Delav Time, Low-to-High

TYP

UNITS
MAX

14

21

ns

11.5

18

ns

14

21

ns

11.5

18

ns

Level Output
Data
tpHl

LEven

Propagation Delay Time, High-to-Low
Level Output
CL

tplH

= 15 pF, RL = 180n

Propagation Delay Time, Low-to-High
Level Output
Data

tpHl

L Odd

Propagation Delay Time, High-to-Low
Level Output
2-171

~ MSI

DM74S280

Typical Applications

Three S280's can be used to implement a 25-line parity
generator/checker_ This arrangement will provide parity
in typically 25 ns. (See Figure 1.)

(S86) or 3-input (S135) exclusive-OR gate for 18 or
27-line parity applications.
Longer word lengths can be implemented by cascading
S280's_ As shown in Figure 2, parity can be generated
for word lengths up to 81 bits in typically 25 ns_

As an alternative, the outputs of two or three parity
generators/checkers can be decoded with a 2-i nput

A
Z

EVEN

H = EVEN
L =000

A

l:

EVEN

~

EVEN
H =000
L = EVEN

F

G
H

L

000

~

EVEN

TO OTHER

S280'S

FIGURE 1: 25-LlNE PARITY/GENERATOR CHECKER

FIGURE 2: 81-LINE PARITY/GENERATOR CHECKER

2-172

H = EVEN
L = 000

H =EVEN
l = DOD

~ MSI

DM74S281
4-Bit Parallel Binary Accumulators

General Description
These Schottky-clamped four-bit accumulators integrate
high-performance versions of an arithmetic logic unit/
function generator, and a shift/storage matrix in a single
circuit. The arithmetic logic unit (ALU) portion provides
the. capability of 16 arithmetic/logic type operations, as
detailed in Table I. The accumulator includes an exchange
of subtract operands by which either A-B or B-A can
be accomplished directly. The ALU is controlled by
three function-select inputs (ASO, AS1, AS2) and a
mode-control input (M)_ When the mode-control input
is high, the ALU may perform any of seven logic functions on two binary variables, as detailed in Table II.
Full carry look-ahead is provided for fast, simultaneous
carry generation_ The carry input (C n ) and propagate
and generate outputs (P, G) are implemented for
direct use with the DM74S1 B2 look-ahead/carry generators. This permits systems to be implemented with the
added advantage of full look-ahead across any word
length to minimize the accumulator delay times. Once
data is loaded into the accumulator, the typical add
time with full look-ahead is 29 nanoseconds for
16-bit words_

or ho.ld. Control of the register is accomplished with
three inputs: register control (RC) and register selection
(RSO, RS1). The cascading input/output lines incorporate
TRI-STATE outputs multiplexed with an input. The
least-significant cascading bit is combined with the AO/FO
circuitry to provide the shift-right input and the shift-left
output (RI/LO). and the most significant bit is coupled
with the A3/F3 circuitry to provide the shift-left input
and the shift-right output (L1/RO).

Features
•
•

•
•

Logic mode operation provides seven Boolean
functions of the two variables
Full shifting capabilities:
Logic shift (left or right)
Arithmetic shift (left or right) for sign bit protection
Hold
Parallel load
Expandable to handle n-bit words with full carry
look-ahead
15 arithmetic/logic operations:
Add
Subtract (B-A or A-B)
Complement
Increment
Transfer
Plus 10 other functions
Full 4-bit binary accumulator in a single package

The shift/storage matrix has capabilities similar to the
DM74S194 universal bidirectional shift register, with
the added advantage of multiplexed input/output (I/O)
cascading lines which comprehend arithmetic shiftfunctions having a sign bit, such as 2's complements. The
matrix can be used to perform either logic or arithmetic
shifts in either direction (left or right). parallel load,

•

Connection Diagram

Truth Tables Notes Shown on Following Page
TABLE I-ARITHMETIC FUNCTIONS
Mode Control (M) = Low

FUNCTION
DATA

Vee

~~

SELECT

CLOCK Rl/lO rASa

AS1

MODE

ASZ'

CN~Rl 'FO

F1

F2

FJ'

AS2 AS1
24

23

22

21

20

19

18

11

16

15

14

ACTIVE HIGH DATA

ALU
SELECTION

DATA OUTPUTS

en

en = L
(no carry)

(with carry)

ASO

13

= H

L

L

L

FO

L

L

H

F

L

H

L

L

H

H

~

H

L

L

F

~

H

L

H

F ~ B PLUS 1

Fo ~ Bo

H

H

L

F

Fo

H

H

H

F ~ A PLUS 1

~

L. F 1 ~ F2

~

F3

~

H

Fo

~

H

F

~

B MINUS A MINUS 1

F~AMINUSB

F

~

A MINUS B MINUS 1

F

A PLUS B PLUS 1

F

~

B PLUS 1

Fo

~

~

B MINUS A

A PLUS 1

A PLUS B
~

~

Bo
Ao

Fo ~ Ao

TABLE II-LOGIC FUNCTIONS
Mode Control (M) = High
12
A1

A2

ASI

ASO

REG lIIAD

--.,....-.. ~ eNTAL
DATA IN
REGISTER
Ae

A3

en

P

Carry Input ICnl

GNO

ALU
SELECTION

DATA
IN

SElECT

AS2 AS1
74S2B1(N)

Tentative Data

2-173

= X (Don't Care)
ACTIVE-HIGH
DATA FUNCTION

ASO

L

L

L

Fo

~

L

L

X

H

Fn

=

An

L

H

L

Fo ~ Ao

H

L

L

Fo~AoBe

H

L

H

Fn = An

H

H

L

Fo

H

H

H

Fn =An +8.,

~

(i) Bo

(+)

Bo

+ Bn

AnBe

To Be Announced In 1976

~

MSI

DM74S281

Truth Tables (Continued)
TABLE III-SHIFT MODE FUNCTIONS
C n = M = SO = Sl = Low, and S2 = High
REGISTER
SELECTION
RS1

RSO

REGISTER
CONTROL
INPUT

FQ

F1

F2

F3

L

L

X

to

f1

f2

f3

L

H

L

OBo

Oeo

0 00

Ii

t
t

L

H

H

OCo

0 00

Ii

t

H

L

L

OAO
ri

OAo

OBO

OCn

SHIFT-MATRIX INPUTS

CLOCK
INPUT

H

L

H

ri

OAo

OBo

0 00

H

H

X

OAO

OBO

Oeo

0 00

t
t
t

X

X

X

OAO

OBO

Oeo

0 00

L

INPUTI
OUTPUT
RI/LO

SHIFT-MATRIX OUTPUTS
(INTERNAL)

°A

°B

OC

00

INPUTI
OUTPUT
U/RO

Z

to

f1

f2

f3

Z

OBo

OBo

OCo

0 00

Ii

Ii

OBo
ri

OBo
ri

Oeo

Ii

0 00

Ii

OAo

Q Sn

Oco

Oeo

ri

ri

OAo

OBo

0 00

Z

OAO

OBO

Oeo

000

Oeo
Z

X

OAO

OBO

Oeo

000

X

H = High Level (steady state)

L :::: Low Level (steady state)
X = Don't Care (any input,

i~cluding

transitions)

Z = High I mpedanee (output off)

t

= Transition from low to high level

fa, fl, f2, f3, ri, Ii = The level of steady-state conditions at FO, F1, F2, F3, RI/LO or Ll/RO respectively.

GAO. 0ao, QeD. 0DO = The level of GA. OS, OCI or GO. respectively', before the indicated steady state input conditions were established.

GAn, 0Sn, GCn. GO n :::: The level of GA. QS. OC. or GO, respectively, before the most recent transition of the clock.

Electrical Characteristics

over recommended operatinll free-air temperature range (unless otherwise noted)
DM74S

PARAMETER

CONDITIONS

UNITS

S281
MIN

TYP(l)

MAX

V,H

High Level Input Voltage

V,L

Low Level/nput Voltage

V,

Input Clamp Voltage

Any Input Except Ll/RO and RI/LO

10H

High Level Output Current

Any Output Except Ll/RO and RI/LO

-1

Ll/RO and RI/LO

-2

High Level Output Voltage

VOH

Low Level,Output Current

10L

Vee::!. Min,

I, =-18mA

Any Output Except Ll/RO and RI/LO

Vee =- Min,

V'H ~ 2V

2.7

3.4

Ll/RO, RI/LO

V'L - 0.8V,

IOH - Max

2.4

3.4

0.8

V

-1.2

V

20

Ll/RO and RI/LO

10

I,

Input Current at Maximum Input Voltage(3)

I'H

High Level J nput Current

Vee == Min,

V'H ~ 2V

V'L

'oL=Max

=

0.8V,

Vee'" Max,

0.5

V, = 5.5V

1

-

RSO, RS1
M, Clock
Ll/RO, RI/LQ(3)

jJ.A

250

-3

RI/LO
M, Clock

-4

Vee == Max, VI = O.5V

mA

-6
-8

ASO, AS1
Others
los

Short Circuit Output Current

Vee = Max(2)

Icc

Supply Current

Vee

0::::

Max

-40
144

Notes
(1)

All typical values are at Vee

(2)

Not more than one output should be shorted at a time, and duration q,f short circuit should not exceed one second.
When testing input current at the RI/LO or L1/RO terminals, the output under test must be in the high-impedance (off) state.

(3)

mA

-2

RSO, RSl, Ll/RO(3)

= 5V, TA =

V

150
200
. 300

Vee = Max, VI:;: 2.7V

Others
Low level Input Current

mA

50

AS2

I,L

mA

V

Any Output Except Ll/RO and R IILO

Low Level Output Voltage

VOL

V

2

25°e,

2-174

-110

mA

230

mA

~

DM74S281

MSI

Switching Characteristics vee

~ 5V, TA ~ 25°C
DM74S

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

CONDITIONS

S281
MIN

UNITS

TYP

MAX

10

20

ns

10

20

ns

18

30

ns

18

30

ns

10

20

ns

50

MHz

fMAX

Clock Frequency (For Shifting)

tpLH

Propagation Delay Time, Low-te-High level Output

tPHL

Propagation Delay Time, High-ta-low Level Output

tPLH

Propagation Delay Time. Low-ta-High Level _Output

tpHL

Propagation Delav Time, High-ta-Low Level Output

tpLH

Propagation Delay Time, Low-ta-High Level Output

tpHL

Propagation Delay Time, High-ta-Low Level Output

10

20

ns

tpLH

Propagation Delay Time, Low . to-High Level Output

14

24

ns

tpHl

Propagation Delay Time, High-ta-Low Level Output

14

24

ns

tpLH

Propagation Delay Time, Low-ta-High Level Output

12

20

ns

tPHl

Propagation Delay Time, High-to-Low Level Output

12

20

ns

tpLK

Propagation Delay Time, Low-to-High Level Output

20

35

ns

tpHL

Propagation Delay Time, High-to-Low Level Output

20

35

ns

tpLH

Propagation Delay Time, Low-to-High Level Output

30

45

ns

tPHL

Propagation Delay Time, High-to-Low Level Output

30

45

ns

tPLH

Propagation Delay Time, Low-to-High Level Output

30

45

ns

tpHL

Propagation Delay Time, High-to-Low Level Output

30

45

ns

tPLH

Propagation De!ay Time, Low-to-High Level Output

7

11

ns

tPHL

Propagation Delay Time, High-ta-Low Level Output

7

11

ns

Cn

C n +4

Any A

Cn

Cn + 4

Any F

G

Any A

P

Any A

Ai

Fi

RI/LO

Aa

CL

~

15pF

1/0 Outputs: RL ~ 560[2

tpLH

Propagation Delay Time, Low-to-High Level Output

tpHl

Propagation Delay Time, High-to-Low ,Level Output

Ll/RO

A3

Fa

RIILO

F3

Ll/RO

Other Outputs: RL

=

280n

7

11

ns

7

11

ns
ns

tpLH

Propagation Delay Time, Low-to-High Level Output

tpHL

Propagation Delay Time, High-to-Law Level Output

tplH

Propagation Delay Time, Low-to-High Level"Output

tpHL

Propagation Delay Time, High-to-Low Level Output

tpLH

Propagation Delay Time, Law-ta-High Level Output

tpHl

Propagation Delay Time, High-to-Low Level Output

tPLH

Propagation Delay Time, Low-to-High Level Output

tPHL

Propagation Delay Time, High-to-Low Level Output

tWICLOCKi

Width of Clock Pulse

8

ns

tsETUP

Data Setup Time With Respect to Clock

ot (5)

ns

tHOlD

Data Hold Time With Respect to Clock

1St (5)

Any AS

Any AS

Clock

Clock

Any For

28

45

C n +4

28

45

n5

20

33

ns

20

33

ns

30

45

ns

30

45

ns

RI/LOor

35

55

ns

LI/RO

35

55

ns

Por G

Any F

Notes
(5)

t ·The arrow indicates that the rising edge of the clock pulse is used for r,eference.

2-175

\

ns

~ MSI

DM74S281

Typic!!1 Applications

RIGHT
DATA' IN

CARJ!Y

-

INPUT -

RI/LO

LIIRO
5281

-

r-Co+4 r--

RI/LD

LIIRO
S281

Co+4 . - - Co

Co

RIILO

LIIRO
S281

C,

Co+4

-

LEFT

LIIRO ~ DATA IN
CARRY
Co+4 ~ OUTPUT

RI/LO
S281
Co

Enter and store timlt:
38 os typ
Each successive addition to stored data: 4405 typ

FIGURE A: 16-BIT BINARY ACCUMULATOR USING FOUR DM74S281 CIRCUITS IN RIPPLE-CARRY MODE

•

RIGHT
DATA IN
CARRY

INPUT

RI/LO
Co

lIlRO

lEFT
DATA IN

Co+4

CARRY

OUT

S182

Enter and stote time:
37 os typ
Each sllccessive addition to stored data: 29 IlS typ

~6~UK~!~~~;BIT BINARY ACCUMULATOR USING FOUR DM74S281 CIRCUITS AND ONE DM74S182 FOR FUlLpARRY

LEFT

RIGHT
DATA IN

DATA IN
CARRY

CARRY

OUTPUT

INPUT

S182

5182

S182

8182

Co

Co

'GO

PO

Co

G1

Co

G2

P1

P2

GJ

PJ

5182

Enter and store time:
42 os tvp
Each successive addition to stored data: 34 os typ

FIGURE C: 64-BIT BINARY ACCUMULATOR USING 16 DM74S281 CIRCUITS AND FIVE DM74S182 CIRCUITS FOR FULL CARRY
LOOK-AHEAD

2-176

~ MSI

OM54/0M74S287,S387
1024-Bit Programmable Read Only Memories

General Description
These circuits are field-programmable, 1024-bit, readonly memories organized as 256 words of four bits each.
This high-speed, Schottky-clamped, TTL memory array
is addressed in 8-bit binary with full on-chip decoding.
Two overriding chip-select inputs are provided which,
when either one or both are high, cause all four outputs
to be off (high Z state for 5287). This memory features
PNP input transistors, which reduce the low level input
current requirement to a maximum' of -0.25 mA, only
one-eighth that of a standard Series 745 load. The organization is expandable with no additional output
buffering.

in the recommended operating conditions will not alter
the memory content.
These programmable memories can be used to replace
the DM74187, as they are functionally and mechanically
identical.

Features
• Fully decoded, low-current PNP inputs
• 5387 has open-collector outputs for easy word expansion

• 5287 is functionally equivalent but has TRI-STATE
outputs
• Provides the versatility of custom designs virtually
"off the shelf"
• Applications include:
Microprogramming
Look-up tables for any fixed program
Parallel Code Converters
Sequence, routine, and subroutine generators
Random logic function generator
• I nterchangeable with most other 256 words by 4-bit
TTL PROMs/ROMs
• Fully compatible with most TTL and other saturated
low level logic families
• Schottky-clamped for high performance:
15nstyp
Chip-select access time,
30 ns typ
Address access time

The address of a 4-bit word is accomplished through
the buffered binary select inputs, with a low level at
both chip-select inputs. Where multiple devices are used
in. a memory system, the chip-select inputs allow easy
decoding of additional address bits.
Data can be electronically programmed at any of the
1024-bit locations. Prior to programming, the memory
contains a low logic level output condition at all bit
locations. The programming procedure open·circuits
metal links, which results in a high logic level output at
the selected locations. The procedure is irreversible;
once altered, the output for that bit is permanently
programmed to provide a high logic level. Outputs
never having been altered may later be programmed to
supply a high level output. Operation of the device with-

Connection Diagram

vr

SELECT
INPUT
H

16

15

ENABLES

CS2

L4

OATA OUTPUTS

,

CSI

113

VI

V2

12

V3

,
Y4

10

11

9

V)
.-

r-

I

1

,G

12
F

I

! t !
3

E

4

0

5

A

6
1
B

17
C
I

J:

SELECT INPUTS

,
54S2871JI; 74S287IJ), IN);
54S387IJ); 74S387IJ), (N)

2-177

To Be Announced In 1976

~

.'

MSI

DM54/DM14S281,S381

Electrical Characteristics over recommendedop€rating free-air temperature range (unless otherwise noted)
DM54S174S
CONDITIONS

PARAMETEIl

.5287
MIN

V'H

Hi,gh Level Input Voltage

V,"

Low Lever Input, Voltage

V,

Input Clamp Voltage

10H

High Level Output Current

Min,

Vee

Ii

High Level Output Voltage

Vcc
V IL

10l

Low Level Output Current

Low Level Output Voltage

MIN

O.8V

Vcc
ViL

1010FF) Off-State (High Impedance State)
Output Current

Vcc

=
=:

=:

=

=

Min, V 1H

-=;

~

2.4V

VOH~

5.5V

V

.. 1.2

-1.2

V

N/A

50

N/A

100
N/A

DM74

"6.5

N/A

2.4

I,

Input Current at Maximum Input Voltage

Vee"" Max, V,

High level Input Current

Vcc = Max, V,

.. I,"

Low Level Input Current

Vee

:=

Max, VI

lOS

Short Circuit Output Current

Vee

~

Max(2)

Icc

Supply Current

Vee

=

Max(3)

~A

rnA

5.5

V

16

16

rnA

0.5

0.5

V

3.2

0.8V, IOL '" 16 rnA

I'H

V

0.8

--2.0

2V

2V

,

0.8

Min, V'H =- 2V

""

MAX

DM54

0.8V, IOH "" Max

Max, V 1H

UNITS

TYP(1)

2

= -18 mA

V OH
V'L

VOL

MAX

2

Vee "'Min, V'H::: 2V

VOH

S387

TYP(l)

Vo

:=0

0:5V

-50

NIA

Va

~2.4V

50

N/A

MA

=

5.5V

1

1

mA

0;;

2.7V

25

25

~A

-250

-250

:=

O.45V

-30

-100

N/A

135

100

100

!

MA
mA

135

mA

Notes
(1)

All typical values are at VCC ~ 5V, TA ~ 25°C.

(2)

Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.

(3)

ICC is' measured with outputs open and both

Switching Characteristics vee

~ 5V,

CS inputs .grounded.

TA

~ 25°C

..
DM54S/74S
PARAMETEIl

FIlOM
/INPUT)

TO
IOUTPUT)

S287
CDNDITIONS

tplH

Propagation Delay Time,
Low-to-High Level Output
Address

tPHl

Propagation Delay Time,
High-ta-Low Level Output

tPlH

Propagation Delay Time,
Low-to-High Level Output

tpHl

tZH

Propagation Delay Time,
High-te-Low Level Output
Output Enable Time to
High Level

tZl

Output Enable Time to
Low Level

tHZ

Output Disable Time
From High Level

tLZ

Output Disable Time
From Low Level

MIN

S387
TYP

MAX

CONDITIONS

MIN

UNITS
TYP

30

35

ns

30

35

ns

15

os

15

I1S

N/A

ns

NIA

os

Any

N/A
Chip

Select

CL "30 pF

Any

CL

Rt. "400n
NIA
15

Chip

Select

MAX

Any

~

30 pF

to GND
Ru ~ 400n
to Vee
RL2

~

600n

to GND
15

-Chip
Select

Any

Notes
(4) When measuring times from address inputs, both

CS1

Cl

""

5 pF

RL

~

400n

and

CS2 are low.

held steady.

2-178

12

NIA

ns

12

N/A

os

When measuring times from chipMselect inputs, the address inputs are

-

I
I

I

~ MSI

OM54/0M74S289
64-Bit Read/Write Memories with Open Collector Outputs

General Description
The fast access time of the S289 makes it particularly
attractive for implementing high performance memory
functions requiring access times on the order of 25 ns.
The unique functional capability of the S289 outputs
being high during writing, combined with the data inputs
being inhibited during reading, means that both data
inputs and outputs can be connected to the data lines
of a bus organized system without the need for interface

These 64-bit active element memories are Schottkyclamped TTL arrays organized as 16 words of four bits
each. They are fully decoded and feature a chip-enable
input to simplify decoding required to achieve the desired
system organization. The memories feature PNP input
transistors that reduce the low level input current
requirement to a maximum of -{).25 mA, only oneeighth that of a (standard) Series 54S/74S load factor.
The chip-enable circuitry is implemented with minimal
delay times to compensate for added system decoding.

circuits.

Features
Write Cycle: The complement of the information at
the data input is written into the selected location when
both the chip-enable input and the read/write input
are low. While the read/write input is low, the outputs
are at a high logic level {off;.

• Schottky-clamped for high-speed applications:
12 ns typ
Access from chip-enable inputs
Access from address inputs
25 ns typ

Read Cycle:' The stored information (complement of
information applied at the data inputs during the write
cycle) is available at the outputs when the read/write
input is high and the chip-enable input is low. When
the chip-enable input is high, the outputs are high
(off).

SELECT INPUTS

BCD

'16

15

14

13

Open-collector outputs for controlled·impedance bus
lines

•

DM54S189/DM74S189 are functionally equivalent
but have TRI-STATE outputs

• Chip-enable input simplifies system decoding
• Compatible with Intel 3101A in most applications

Connection Diagram

....-----.------.

•

Logic Diagram
DATA
INPUT
4

,

OATA
0 UfPUI
Y4

INPUT

OUTPUT

3

Y3

11

10

12

111

9

115)
64·B1T MEMORY

ADDRESS

ADDRESS
INPUTS

114)

BUffERS

1·0F·16
DECODERS

MATRIX
ORGANIZED
16 X 4

1131

p..

r-

_

121

CHIP ENABLE (eE)

REAONvRITE IRM'I 13)

1

2

SElECT
CHIP
INPUT A ENABLE

4

3
READ!
Wf{ITE

DATA
INPUT

1

5
OUTPUT
Y1

6
DATA
INPUT

7
OUTPUT
Y2

18

GNO

DATA INPUTS \::

2

---"'1-'

-'I"'W-)

D3~~--~--~-'

04~1~12~1__~~__~__~

54S289(JI; 74S289(J), (WI

15)
Y1

171

191
Y2

1111
Y3

OUTPUTS

Truth Table
INPUTS
FUNCTION

Write

(Store Complement of Datal

CHIP
ENABLE

READ!
WRITE

OUTPUT

H

L

Read

L

H

Stored Data

Inhibit

H

X

H

H = High Level, L = Low Level, X =- Don't Care

2-179

Y4

~

MSI

OM54/0M74S289

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
DM54S04S
S289

CONDITIONS

PARAMETER

MIN

MAX

2

" High Level Input Voltage

VIH

UNITS

TYP(1)

VIL

Low Level Input Voltage

VI

Input Clamp Voltage

Vee; Min, I, = -18 mA

IOH

High Level Output Current

Vee=Min,V'H=2V

V

I V oH =2,4V

V
V

40

I VOH - 5,5V

V'L ; 0,8V

0,8
-1.2

100

J1A

VOH

High Level Output Voltage

5,5

V

IOL

Low Level Output Current

16

mA

VOL

Low Level Output Voltage

Vee = Min, V ,H

= 2V

V'L ; 0,8V, 10L = 16 mA

0,5

DM74

0.45

Vee = Max, V, ; 5,5V

I nput Current at Maximum

II

DM54

V

1

mA

Input Voltage

,

IIH

High Level Input Currerit

Vee; Max, V, ; 2.7V

IlL

Low Level I nput Current

Vee; Max, V, ; 0,45V

IcC

Supply Current

Vee = Max(2)

75

25

IJ.A

-250

J1A

105

mA

Notes
(1) All typical value, are at VCC; 5V, TA = 25°C,
(2)

ICC is measured with all inputs grounded, and the outputs open.

Switching Characteristics over recommended operating ranges of Vee

and T A (unless otherwise noted)
DM54S

PARAMETER

CONDITIONS

DM74S

S289
MIN

MAX

25

50

12

25

12

17

ns

12

25

12

17

!'IS

22

40

22

35

ns

MIN

tAA

Access Times From Address

tCLH

Disable Time From Chip Enable

tCHL

Enable Time From Chip Enable

tWHL

Sense-Recovery Time From Read/Write

twp

Width of Write-Enable Pulse (Read/Write Low)

25

25

tAsw

Setup Time

D

0

CL = 30 pF

UNITS

S289

TYP

TYP

MAX

25

35

nS

Ru =300n
R L2 = 600n

Address to Read/Write

tosw

Data to Read/Write

25

25

tcsw

Chip Enable to Read/Write

0

0

Address From Read/Write

0

0

Data From Read/Write

0

0

Chip Enable From Read/Write

0

0

I~

I~
tCHW

Hold Time

,
2-180

!'IS

ns

ns

~MSI

DM54/DM74S289

Parameter Measurement Information

LOAD CIRCUIT

-h
r
VCCRU

FROM OUTPUT
UNDER TEST

..

c
C

':' R"

ENABLE AND DISABLE TIME FROM CHIP ENABLE
CHIP ENABLE
INPUT
(SEE NOTE 31

3V
1.5V
OV----____~~----~------------I

VOH
OUTPUT
ISEE NOTE II

----+--""'1.5V

VOC--------~------~-,------_4--'

ACCESS TIME FROM ADDRESS INPUTS
ADDRESS INPUTS
INOTE 21

,:=t~·~----J@:F----·
~5V _ _ _ _ _ _ _ ____

OUTPUT

Voc __________- - - -____

15V

~~

WRITE CYCLE
3V

ADDRESS
INPUTS

JV
DATA

INPUTS

JV

CHIP·ENABlE
INPUT
OV

3V
READiWAITE
INPUT
OV

VOH

OUTPUT
(NOTE 11

-------

Vo ,

Notes
(1)

Waveform 1 is for the output with internal conditions such that the output is Jo~ except when disabled.

(2)

When measuring delay times from address inputs, the drip enable input is low and the read/write input is high.
When measuring delay times from chip enable input, the address inputs are steady state and the read/write input is high.

~3)

(4)

Input waveforms are supplied by pulse generators having the following characteristics: tr ~ 2.5 ns, tf

ZOUT

~

50n.

2·181

s: 2.5 ns, PRR

~ 1 MHz and

~ MSI

OM54/0M74LS295A
TRI-STATE 4-Bit Parallel Access Shift Registers

General Description
When the output control is high, the normal logic levels
of the four outputs are available- for driving the loads or
bus lines. The outputs are disabled independently from
the level of the clock by a low logic level at the output
control input. The outputs then present a high impedance
and neither load nor drive the bus line; however,
sequential operation of the register is not affected.

These 4-bit registers feature parallel inputs, parallel
outputs, and clock, serial, mode, and output control
inputs. The registers have three modes of operation:
Parallel (broadside) load
Shift right (the direction OA toward Op)
Shift left (the direction Op toward 0A)
Parallel loading is accompiished by applying the four
bits of data and taking the mode control input high.
The data is loaded into the associated flip·flops and
appears at the outputs after the high to low transition of
the clock input. During parallel loading, the entry of
serial data is inhibited.

Features
• TRI-STATE versions of DM54LS95B(DM74LS95B
• Schottky diode clamped transistors

Shift right is accomplished when the mode control is low;
shift left is accomplished when the mode control is high
by connecting the output of each flip-flop to the parallel
input of the previous flip-flop (OD to input C, etc.)
and serial data is entered at input D.

Connection Diagram

I"

fie

"

•

Applications:
N-bit serial-to-parallel converter
N-bit parallel-to·serial converter
N-bit storage register

70 mW typical

'"

11

OUTPUT
CONTROL

CLOCK

fio

"

Low power dissi pation (enabled)

Logic Diagram

OUTPUTS

fi,

•

8

9

DATA
INPUTS
OUTPUTS

-

r-

3

2

1

4

I'

6

5

SERIAL

MODE

INPUT

CONTROL

INPUTS

GNU

54LS295A/74LS295AIJI, IN), IWI

MODE
CONTROL

OUTPUT
CONTROL

SERIAL

INPUT

Truth Table
INPUTS
MOOE
CONTROL

CLOCK

H

H

H
H

>
>

L

H

L

>
>

L

H

OUTPUTS

SERIAL

ac

aD

OAO aBO
b
a

Q eo

c

aDO
d

aCe

Q On

d

OAO aBO

Oeo

000

H

OAe Q Sn

aCe

L

OAe G Bn aCe

aA

A

B

e

D

X

X

X

X

a

b

c

d
d

QBn

X
X
X

X
X
X
X

,
as

Oc'

X

X

X

H

X
X

X
X

X

L

aD

X

t

aB

When the output control is low, the outputs are disabled to the high-impedance state;
however, sequential operation of the registers is not affected.

Tentative Data

= High

Level Isteady-state I , L

= Low

Level IsteadY·

state), X = Don't Care (any input including transitions)

PARALLEL

2-182

t "" Transition from high to low level
a, b, c, d = The level of steady-state input at inputs A,
S, C, or 0, respectively.
0AO, 0BO, OeD, 0DO = The level of 0A, 0B, 0C, or

0D, respectively, before the indicated steady-state
input conditions were established.
0An, 0Bn, 0Cn, 0Dn = The level of OA,OB, 0C, or
QO, respectively, before the most recent t transition
of the clock.
tShifting left requires external connection of 0B to

A, QC to B, and GD to C. Ser.ial data is entered at
input D.

To 'Se Announced In 1976

~

MSI

DM54/DM74LS295A

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
DM74LS

DM54LS
PARAMETER

CONDITIONS
MIN

Level Input Voltage

V'H

High

V'L

Low Level Input Voltage

V,

Input Clamp Voltage

10H

High Level Output Current

VO H

High Level Output Voltage

10L

Low Level Output Current
Low Level Output Voltage

TYPI11

Vee::: Min, V 1H
:::

:::

2V

2.4

Max, IOH ::: Max

V

Off-State (High Impedance State)

=::

:::

Min, V 1H

:::

Max

tOL

-1.5

·15

V

2.6

rnA

2.4

3.4

Input Current at Maximum

=

2V

Vee::: Max, VI

= 7V

0.25

=4mA

tOL:":

Vee =:: Max, V 1H
V 1L ::: Max

Input Voltage

2V

V

0.8

V

3.1

4
Vee

MAX

0.7

·1

Output Current

I,

MIN
2

Vee::: Min, I, ::: ~18 rnA

V 1L
1010FFI

MAX

2

V 1L

VOL

TYPI11

UNITS

LS295A

LS295A

8

0.4

8 rnA

0.25

0.4

0.35

0.5

Vo = OAV

·-20

-20

Vo - 2.7V

20

20

0.1

0.1

rnA
V

~A

rnA

I'H

High Level Input Current

Vee::: Max, VI

= 2.7V

20

20

jJ.A

I'L

Low L~vel Input Current

Vee = Max, VI = DAV

-0.4

-0.4

rnA

los

Short Circuit Output Current

Vee = Maxl21

-130

rnA

Icc

Supply Current

Vee = Maxl31

-30

-130

-30

Condition A

14

23

14

23

Condition B

15

25

15

25

rnA

Notes
111 All typical values are at Vee = 5V, T A = 25°C.
(21 ' Not more than one output should be shorted at a time. and duration of short circuit should not exceed one second.
131

ICC is measured with the outputs open, the serial input and mode control at 4.5V, and the data inputs grounded under the following
conditions:
A. Output control at 4.SV and a momentary 3V; then ground, applied to clock input.

B. Output control and clock input grounded.

Switching Characteristics vee

=

5V, TA

=

25°C
DM54LS/74LS

PARAMETER

CONDITIONS

fMAJ(

Maximum Clock Frequency

tpLH

Propagation Delay Time, Low"ta-High Level Output

tpHL

Propagation Delay Time, High-ta-Low Level Output

tZH

LS295A
MIN

TYP

20

28

UNITS
MAX
MHz

ns

40

60

47

70

ns

Output Enable Time to High Level

15

25

ns

tZL

Output Enable Time to Low Level

21

30

ns

tHZ

Output Disable Time From High Level

CL = 5 pF

39

60

ns

.tLZ

Output Disable Time From Low Level

RL = 400n

32

50

ns

tW(CLOCK)

Width of Clock Pulse

25

ns

tSETUP

Setup Time, High Lever or Low Level pata

20

ns

tHOLD

Hold Time, High Level or Low Level Data

20

ns

CL = 15 pF
RL = 400n

,

I
2-183

. ~·.MSI

OM54/0M74LS2$8
Quad 2-Multiplexers with Storage

General Deseription

Features

Thes.e [ntegratedcircuitsprovide.eyentially the equivalent
functional capabilities of two separate MSI functions
(DM54157/DM74157 or DM54LS157/DM74LS157 and
DM54175/DM74175 or DM54LS175/DM74LS175) in a
singljl16-pin package.
.

• Selects one of two 4-bit· data sources and stores
data synchronously with system clock
• Applications:
Dual· source for oPerands and constants in arithmetic processor; can release· processor register
files for acquiring new data

Whe.n the word-select input is low, word 1 (A1, 81,
Cl, 01) is entered· into the flip-flops. A high input to
cause the selection of word 2· (A2,
word select
82, C2, 02). The selected word is then clocked to the
output terminals on the negative-going edge of the
.
clock pulse.·

Implement separate registers capable of parallel
exchange of contents, yet retain external load
capability
Universal type register for implementing various
shift· patterns; even haS compound left~right
capabilities

will

Connection Diagram

Truth Table

OUTPUTS
00

I..

15

12

13

"

WORD

DATA
INPUT

CLOCK

SelECT

C1

11

10

INPUTS

•

WORD
SELECT

CLOCK

L
H
X

OUTPUTS

,

•
•
H

OA

OB

Dc

00

a1
a2

b1
1,2

c1
02

d1
d2

QAO

Cleo Oco 000

rH ~ High level (steady .tate)
I,. = Low level (steady state)

,

1

8Z

,
A1

AZ

•
B1

5

C2

•
DZ

DATA INPUTS

1

01

I'

GNO

X = Don't Care (any input, including transitions)
• = Transition from high to low level·.
a1, a2, etc. = The level of steady-state input at Al, A2, etc.
0AO, aBO, etc. = The level of 0A, 0B, etc. entered on tha
most recent'" transition of the clock input.

54lS298/74lS298(J), (N), (W)

Logic.Diagram

Tentative Data

2-l8!1

"To Be Announced 'n 1976

~MSI

DM54/DM74lS298

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

DM54LS/74LS
PARAMETER

CONDITIONS

LS29lI
MIN

V,H

High Level Input Voltage

V,L

Low Level Input Voltage

V,

Input Clamp Voltage

10H

High Level Output Current

VOH

High Level Output Voltage

Vee

=:

V

DM54

0.7

DM74

0.8

V

-1.5

Min, II = -18 rnA

V

-400
Vee = Min, V 1H = 2V
=:

Max, IOH

=-400jJA

Low Level Output Current

.

Low Level Output Voltage

VOL

MAX

2

V IL

10L

UNITS

TYP(1)

Vee =Min, V 1H =2V

1 lot.-

V1L

]loL = 8 rnA

=

Max

DM54

2.5

3.4

DM74

2.7

3A

V

DM54

4

DM74

8

=4mA
DM74

MA

0.25

0.4

0.35

0.5

rnA

V

I,

Input Current at Maximum InpUt Voltage

Vee"" Max, VI = 7V

0.1

I'H

High Lev,el Input Current

Vee =Max, VI =2.7V

20

MA

I,L

Low Level Input Current

Vee

= Max, V, = OAV

-{).4

rnA

loS

Short Circuit Output Current

Vee

= Maxl2}

-130

rnA

Icc

Supply Current

Vee

= Max(3}

21

rnA

-30
13

rnA

Notes

= 5V. T A =25·C,

(ll

All typical values are at V CC

(2)

Not more than one output should be shorted at a time, and duration of short circuit should not exceed one second.
With all outputs open and all inputs except clock low, ICC is measured after applying a momentary 4.5V, followed by ground,
to the clock input_

(3)

Switching Characteristics vee

= 5V. T A = 25°C
DM54LS/74LS

PARAMETER

CONDITIONS

LS29lI
MIN

tpLH

Propagation Delay Time, Low-to-High Level Output

tpHL

Propagation Delay Time. High-to-Low Level Output

tw

Width of Clock Pulse, High or Low Level'

20

tsETUP

Setup Time

15

CL

tHOLD

Hold Time

= 15pF,

Data
Word Select

5
0

2-185

UNITS
MAX

18

27

ns

21

32

ns

RL =2kn

25

Data
Word Select

TYP

ns
ns

ns

~MSI

DM54/DM74LS298

Typical Applications
:

Figure 1 illustrates a BCD shift register that will shift

Another function that can be ,implemented with the
LS298 is a register that can be designed specifi,cally
for supporting multiplier or division operations_ Figure 2
is an example of a one place/two place shift register_'

an entire 4-bit BCD digit in one clock pulse_
When the word select input is high and the registers are
clocked, the contents of register 1 is transferred (shifted)
to register 2, etc. In effect, the BCD digits are shifted
one position. In addition, this application retains a
parallel-load capability which means that new BCD
data can be entered into the entire register with one clock
pulse. This arrangement can be modified to perform the
shifting of binary 'data for any number of bit locations.

When word select is low and the register is clocked, the
outputs of the arithmetic/logic units (ALU's) are shifted
one place. When word select is high and the registers are
clocked, the dat~ is shifted two places.

PARALLEL LOAD

,

,

I

L

WS
AI
A2
' - Bl
B2
' - - - Cl

0.
lS298
REG 1

0.
L....-

B2

0,

LS298
REG 2

' - - Cl
Dc

C2

D.

02

01

CLOCK

L

ws

AI
A2

' - - Bl

C2
02

I

CLOCK

'(

AI

B2
' - - - Cl

Dc

C2
01

0.

02

0LS29S

Dc
CLOCK

------------

DIGiT 1

D,

REG 2

0.

y

'(

------------

ws

A2
Bl

0,

01

CLOCK

WORD
SELECT

------------

DIGIT 2

DIGIT3

FIGURE 1

-T----,l- -T----JALU ..
181

FO

Fl

...I I
.r-C

F2

Fe

FJ

Fl

F2

F3

...- ...-

nn
~

:v

nn

At Al 81 82 Ct C2 DI D2

At AZ 81 82 Cl C2 01 02

CLOCk

CLOCK

0.
CLOCk

I

ALU
lBl

.

LS298

0,

Dc

I I I I

FIGURE 2

0.

lSZ91

o.

WSr-

Dc

0.

J

I I I I

WORD'
SELECT

,

~ MSl

OM 54/ OM74LS374
TRI-STATE Octal D Flip-Flops

General Description

Features

These 8-bi t registers contain Ootype flip-flops with
totem-pole TRI-STATE outputs capable of driving highlycapacitive or low-i mpedance loads. When the output
control is taken to a high logic level, the outputs go
into the high impedance state. When a low logic level is
applied to the output control, data at the 0 inputs are
loaded into their respective flip-flops on the next
positive-going transition of the clock. Clocked flip-flops
provide fully synchronous operation and, in addition,
these devices come in the new 20-pin dual-in-line packages
with the 0.3" centers.

•

TRI-STATE bus driving outputs

•

Parallel access for loading and reading

•

Many appl ications
Holding/working registers
I/O register port
Buffer regi sters
Register files

•

Typical propagation delay

Connection Diagram

".

"8

D1

19 ns

Truth Table
07

O.

O.

.5

05

CLOCK

OUTPUT
CLOCK
CONTROL

0

OUTPUT

H

H

L
H

L

X

00

X

X

Z

10

OUTPUT 01
CONTROL

D1

D2

02

Ol

03

D4

fi'

GNO

A

54lS37 4/7 4lS37 41 N I

Logic Diagram

Typical Application

Q1

INPUT POAT

Tentative Data

2-187

To Be A.nnounced In 1976

~

MSI

DM54/DM74LS374

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
DM54

PARAMETER

CONDITIONS
MIN

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

VI

Input Clamp Voltage

IOH

High Level Output Current

VOH

High Level Output Voltage

10L

Low Level Output Current

VOL

Low Level Output Voltage

1010FF)

DM74

LS374
TYP(1)

2

Vee -'"

Vee

=;

~in,

II:::

Min

~18

IOH

mA

:=

-1 rnA

MIN

-1.5

-1.5

V

-1.0

-5.0

rnA

2.7

IOH

5 rnA

2.4

""

2V

'"

Max

Off State (High Impedance State)

Vee

Output Current

V ,H ::: 2V

V1l

=

:=

Max

Max

V

25

V 1L = Max

V 1H

V
0.8

2.6 rnA

V 1L

MAX

2

IOH -

Vee"" Min

TYP{l)

0.7

V 1H '" 2V

:co

UNITS

LS374
MAX

IOL "'4 rnA

V

4

8

0.4

0.4

rnA

V
0.5

IPl "" 8 rnA
Va

= O.4V

-20

-20

Va

= 2.7V

20

20

pA

rnA

II

Input Current at Maximum Input Voltage

Vee

0.1

0.1

IIH

High Level Input Current

Vee::: Max, VI::: 2.7V

20

20

pA

IlL

Low Level Input Current

Vee::: Max, VI '" DAV

-0.4

-0.4

rnA

lOS

Short Circuit Output Current

Vee = Max{21

--130

rnA

Icc

Supply Current

Vee'" Max

50

rnA

:=

Max, VI =- 7V

-30

-130

-30

50

Notes:
(1)

(2)

typical. values are at V CC = 5V, T A = 250 C.
Not more than one output should be shorted at a time, and duration of short circuit should not exceed one second.

.AII

Switching Characteristics vce = 5V, T A = 25°C
DM54LS/74LS
PARAMETER

fMAX

Maximum Clock Frequency

tPlH

Propagation Delay Time,
Low-ta-High Level Output

tpHL

Propagation Delay Time,
High-ta-Low Level Output

~ZH

FROM

TO

Clock

Output

Clock

Output

CONDITIONS

CL

= 15pF,

TYP

25

30

Output Enable Time to

Output Enable Time to
Low Level

'HZ

Output Disable Time from
High Level

ILZ

Output Disable Time from

tHOLO

Setup Time
Hold Time

MHz

18

30

ns

20

30

ns

15

20

ns

10

20

ns

13

20

ns

15

20

ns

CL = 5 pF, RL = 2 kn

Low level'
tSETUP

MAX

RL =2kn

High Level

IZL

UNITS

LS374
MIN

Data

10

Output Control

20

Data

10

Output Control

2

2-188

ns
ns

~MSI

DM54/DM74lS395
TRI-STATE 4-Bit Cascadable Shift Registers

General Description

These 4-bit registers feature parallel inputs, parallel
outputs, and clock, serial, lead/shift, output control
and direct overriding clear inputs.

control input. The outputs then present a high impedance,
and neither load nor drive the bus line; however,
sequential operation of the registers is not affected.
During the high·impedance mode, the output at G D ' is
still available for cascading.

Shifting is accomplished when the load/shift control
is low. Parallel loading is accomplished by applying
the four bits of data and taking the load/shift control
input high. The data is loaded into the associated flipflops and appears at the outputs after the high to low
transition of the clock input. During parallel loading,
the entry of serial data is inhibited.

Features
• Applications:
N-bit serial-to-parallel converter
N-bit parallel-to-serial converter
N-bit storage register
• TRI-STATE, 4-bit, cascadable, parallel-in, parallel-out
registers
• Schottky diode clamped transistors
75 mW typical
• Low power dissipation (enabled)

When the output control is low, the normal logic levels
of the four outputs are available for driving the loads or
bus lines. The outputs are disabled independently from
the level of the clock by a high logic level at the output

Connection Diagram
OUTPUTS

CASCADE
OUTPUT

vee

116

Go
15

14

13

OUTPUT

uo'
12

CLOCK CONTROL

11

p-

r<

I
CLEAR

9

'0

2
SERIAL
INPUT

3

4

5

7

6

A

LOADI

P

GNO

SHIFT

PARALLEL INPUTS

54LS395174LS395(J), (N), (W)

Logic Diagram
DATA INPUTS
A
131

B

o

C

161

151

141

S~:~~~ ~1",21_ _ _ _-,

CLOCK~I'~OI~'_--Q~~~________-+__-'~______~_-'~_____~_-'

CLEAR 1'1
OUTPUT 191
CONTROL
1151

1131

1141

D,

• OA

f1c

1121
00 ,

TRI·STATE OUTPUTS

Tentative Data

2-189

To Be Announced In 1976

~

MSI

DM54/DM74LS395

Truth Table
CLEAR

LOAD/SHIFT
CLOCK SERIAL
CONTROL

PARALLEL
A

B

C

0

L

X

X

X

X

X

X

X

H

H

H

X

X

X

X

X

H

H

t

X

a

b

c

d

H

L

H

X

X

X

X

X

H

L

~

H

X

X

X

X

H

L

t

L

X

X

X

X

H = High Level (steady state). L
(steady state).

TRI-STATE OUTPUTS CASCADE
OUTPUT
OA Oe Oc 00
00'

INPUTS

L

L

L

L

0AO. 0BO. 0eo. 000 = The level' of 0A. 0B.
0C. or 00. respectively. before the indicated

steady state input conditions were established.

DO~

0An. 0Bn. 0Cn. 00n.

d

DAD D BO Dco DO~
H DAn OBn Den
L
OAn DBn Dcn

Low Level

X == Don't Care (any input including transitions)
~ = T:ransition from high to low level.

L

DAD DBO Deo DO~
a
d
b
c

=

= The

level of 0A. 0B.

CCr or 00. respectively, before the more tecent
.j. transition of the Clock.

DO~

When the output control is high. the TRI-5TATE
outputs are disabled to the high·imped~l1ce state;

Dcn
Dcn

however, sequential operation of the registers and

,

the output at 00' are not affected.

Electrical Characteristics

over recommended operating free·air temperature range (unless otherwise noted)

-.

DM54LS

PARAMETER

CONDITIONS
MIN

V,H

High Level Input Voltage

V,L

Low Level I nput Voltage

V,

Input Clamp Voltage

10H

High Level Output Current

VOH

High Level Output Voltage

Low Level Output Current

VOL

Low Level Output Voltage

TYP(1)

LS395
MIN ,TYP(l)

MAX

2

Vee': Min, V 1H

= 2V

2.4

V

0.7

0.8

-1.5

-1.5

V

-1

-2.6

mA

3.4

2.4

3.1

4

1010FFI Off-State (High Impedance State)
Output Current

= 4 mA

Vee == Min, V 1H = 2V

IOl

V 1L

IOl - 8 mA

Vee

""

Max

= Max, V 1H

== 2V

.v IL "" Max

UNITS
MAX

2

Vee::' Min, I, =-18 mA

V1L = Max, IOH = Max
10L

DM74LS

LS395

0.25

V
8

0.25

0.4

0.35

V

0.4
0.5

Vo =O.4V

-20

-20

V D = 2.7V

20

20

mA
V

p.A

I,

Input Current at Maximum Input Voltage

Vee == Max, VI "" 7V

0.1

0.1

I'H

High Level I nput Current

Vee = Max. V, = 2.7V

20

20

p.A

I,L

Low Level I nput Current

Vee = Max. V, = 0.4V

-0.4

-0.4

mA

lOS

Short Circuit Output Current

Vee = Max(2)

Icc

Supply Current

Vee = Max(3)

-30

-30

-130

Condition A

18

Condition B

15

29
25

-130
18

29

15

25

mA

rnA
mA

Notes

= 2S'C.

(1)

All typical values are at Vce = SV. TA

(2)

Not more than one output should be shorted at a time, and duration of short circuit should not exceed one second.
ICC is measured with the outputs open, the serial input and mode control at 4.5V, and the data inputs grounded under the following conditions:
A. Output controf-~t 4.SV aryd a momentary 3V. then ground. applied to clock input.
B. Output control and c;:lock input grounded.

(3)

Switching Characteristics Vee; 5V. T A; 25°C
DM54LS/74LS
PARAMETER

CONDITIONS

fMAX

Maximum Clock Frequency

tpLH

Propagation Delay Time, Low-ta-High Level Output

tpHL

Propagation Delay Time, High-to-Low level 9utput

tZH

LS395
MIN

TYP

25

35

UNITS
MAX
MHz

"8

27

ns

21

32

ns

Output Enable Time to High level

15

25

ns

tZL

Output Enable Time to Low Level

20

30

ns

tHZ

Ou~put

C l = 5 pF

30

50

ns

tLZ

Output Disable Time From Low Level

Rl =400n

30

50.

ns

tWICLOCKI

Width

tsETUP

Setup Time, High Level

tHOLD

Hold Time, High Level or low level Data

Disable Time From High LeveJ

Cl = 15 pF
Rl = 400n

at Clock Pulse

25·
o~

Low Level Data

2·190

ns

20

ns

10

ns

~MSI

DM54/DM74LS670
TRI-STATE 4 by 4 Register Files

General Description
These register files are organized as 4 words of 4 bits
each, and separate on-chip decoding is provided for
addressing the four word locations to either write-in or
retrieve data. This permits writing into one location, and
reading from another word location, simultaneously.

recovery times, permits simultaneous reading and writing,
and is limited in speed only by the write time (27 ns
typicall and the read time (24 ns typicall. The register
file has a non-volatile readout in that data is not lost
when addressed.

Four data inputs are available to supply the word to be
stored. Location of the word is determined by the write
select inputs A and B, in conjunction with a write-enable
signal. Data applied at the inputs should be in its true
form. Th'at is, if a high level signal is desired from the
output, a high level is applied at the data input for that
particular bit location. The latch inputs are arranged so
that new data will be accepted only if both internal
address gate inputs are high. When this condition exists,
data at the 0 input is transferred to the latch output.
When the write-enable input, Gw , is high, the data
inputs are inhibited and.their levels can cause no change
in the information stored in the internal latches. When the
read-enable input, G R , is high, the data outputs are
inhibited and go into the high impedance state.

All inputs (except read enable and write enablel are
buffered to lower the drive requirements to one nor·
mal Series 54LS/74LS load, and input clamping diodes
minimize switching transients to simplify system design.
High speed, double ended AND-OR-INVERT gates
are employed for the read-address function and have
high sink current, TRI-STATE outputs. Up to 12B of
these outputs may be wire-AND connected for increasing
the capacity up to 512 words. Any number of these
registers may be paralleled to provide n-bit word length.

Features
•

For use as:
Scratch pad memory
Buffer storage between processors
Bit storage in fast mUltiplication designs
• Separate read/write addressing permits simultaneous
reading and writing

The individual address lines permit direct acquisition of
data stored in any four of the latches. Four individual
decoding gates are used to complete the address for
reading a word. When the read address is made in
conjunction with the read-enable signal, the word appears at the four outputs.
This arrangement-data entry addressing separate from
data read addressing and individual sense line-eliminates

• Organized as 4 words of 4 bits
• Expandable to 512 words of n-bits
• TRI-STATE versions of DM54LS170/DM74LS170
20 ns typ
• Fast access ti mes

Connection Diagram

Truth Tables
WRITE TABLE (SEE NOTES A, B, AND C)
WORD

WRITE INPUTS

vTC

[lATA
INPUT
01

16

15

WB
WRITE SELECT

13

Gw

OUTPUTS

ENABLE

01
14

WA

11

"

0.2

O=D

Do

00

00

Do

O=D

Do

L

00

Do
Do
Do

O=D

Do
Do

H

10

H

L

H

H

L

00

X

X

H

Do

O=D

00
00

Do

READ TABLE (SEE NOTES A AND D)

I-

READ INPUTS
Ra

RA

OUTPUTS

GR

L
L

H

L

H
03

DATA
INPUTS

RB

RA

READ
SE LEer

I

04

03

I

H

H

x

x

H

Q1

02

03

04

WOBl

WOB2

WOB3

WOB4

W1Bl

W1B2

W1B3

W1B4

W2Bl

W2B2

W2B3

W2B4

W3S1

W3B2

W3B3

W3B4

Z

Z

Z

Z

OUTPUTS

Notes:
54LS670!74LS670(J), (N), (W)

(A) H = High Level, L
Impedance (Off)
(B) (0

= D) = The

=

Low Level, X

=

Don't Care, Z

=

High

four selected internal flip-flop outputs will

assume the states applied to the four external data inputs.
(C) 00 :; : ; The level of Q before the indicated input conditions
were established.
(D) WOSl = The first bit of word 0, etc.

2-191

To Be Announced In 1976

~

MSI

DM54/DM74lS670

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
DM54LS
CONDITIONS

PARAMETER

MIN
VIH

High Level Input Voltage

VIL

Low Level Input Voltage

VI

Input Clamp Voltage

10H

High Level Output Current

V OH

High Level

Ou~put

10L

low Level Output Current
Low Level Output Voltage

Vee

= Min, V ,H

= 2V

V 1L

~Max.loH

=Max

Vee

= Min,
= Max

""

V tH

2V

TYP(1)

UNITS
MAX
V

0.7

0.8

V

-1.5

-1.5

V

-1.0

-2.6

mA

3.4

0.25

IOL = 4 rnA

IOL

2.7

3.4

V
8

0.4

8 mA

0.25

0.4

0.35

0.5

Vee"" Max, V 1H = 2V

Va" O.4V

-20

-20

V1l

Vo - 2.7V

20

20

Any D, R,orW

0.1

0.1

Gw
GR

0.2

0.2

0.3

0.3

:=:

Max

Input Current at Maximum Input Voltage

Vee -= Max, VI"" 7V

High Level Input Current

Vee

= Max,

VI

= 2.7V

Low Level Input Current

IlL

2.5

MIN

4

1010FF} Off-State (High Impedance State)
Output Current

IIH

LS670
IVIAX

2

Vee"'" Min, I, -: -.18 rnA

V 1L

II

TYP(l)

2

Voltage

VOL

DM74LS

LS670

Vee::: Max, VI

=

DAV

Any 0, R,orW

20

20

Gw
GR

40

40

60

60

AnyD,R,orW

-{J.4

-{J.4

Gw
GR

-0.8

-{J.8

-1.2

-1.2

= Max(2)

los

Short Circuit Output Current

Vee

ICC

Supply Current

Vee" Maxl31

-30

-130
30

50

-30
30

mA

V

!J.A

mA

!J.A

mA

-130

mA

50

mA

Notes

typical values are at VCC

~

5V. T A ~ 25°C.

(1)

All

(2)

Not more than one output should be shorted at a time, and duration of short circuit should not exceed one second.
Maximum ICC is guaranteed for the following worst-case conditions: 4.5V is applied to all data inputs and both enable inputs. all address
inputs are grounded and all outputs are open.

(3)

2-192

~

MSI

OM 54/ OM74LS670

Switching Characteristics Vee = 5V, TA = 25°C
DM54 LS/74 LS
FROM
(INPUT)

PARAMETER

TO
(OUTPUT)

tpLH

Propagation Delay Time, Low-to-High Level Output

tpHL

Propagation Delay Time, High-ta-Low level Output

Read Select

UNITS

LS670
CONDITIONS

MIN TYP MAX
23

40

ns

25

45

ns

26

45

ns

28

50

ns

25

45

ns

Any Q

tpLH

Propagation Delay Time, Low-ta-High Level Output

tpHL

Propagation Delay Time, High-ta-Low Level Output

tPLH

Propagation Delay Time, Low-ta-High Level Output

tPHL

Propagation Delay Time, High-ta-Low Level Output

23

40

ns

tZH

Output Enable Time to High Level

15

35

ns

tZL

Output Enable Time to Low Level

22

40

ns

tHZ

Output Disable Time From High Level

30

50

ns

16

35

os

Write Enable

Data

Read Enable

Any Q

CL "15pF
RL"2kSl

Any Q

Any Q,
C L " 5 pF
RL "2kll

Read Enable

Any Q

Output Disable Time From Low Level

tlZ
tw

Width of Write-Enable or Read-Enable Pulse

tSETUP

Setup Times, High or Low Level Data(4)

Data Input With Respect to
Write-Enable, tSETUP(D)
Write-Select With Respect to
Write-Enable, tSETUP(W)

tHOlD

Hold Times, High or Low Level Oata(4)

Data Input With Respect to
Write-Enable,

os

10

ns

15

ns

15

ns

5

ns

25

ns

tHOLO(O}

Write-Select With Respect to
Write-Enable, tHOLD(W)
tlATCH

25

Latch Time for New Data(5)

Notes
(4)

Write-select setup time will protect the data written into the previous address_ If protection of data in the previous address is not required,
tSETUP(W) can be ignored as 'any address selection sustained for the final 30 ns of the write-enable pulse and during tHOLD(W) will result
in data being written into that location. Depending on the duration of the input conditions, one or a number of previous addresses may have
been written into_

(5)

Latch time is the time allowed for the internal output of the latch to assume the state Qf new data. This ;s important only when attempting
to read from a location immediately after that location has received new data.

2-193

~MSI

DM54/DM74LS670

Logic Diagram

OUTPUTS

DATA
INPUTS

1121
Gw

1131
We
WRITE INPUT

(1'1
WA

141
Rs

1111
GR

READ INPUT

151
RA

National Semiconductor
PROPRIETARY DEVICES

Section 3

~ Proprietary

Max Ratings/Operating Conditions

7X/8X 7XL!8XL
SERIES SERIES

RATINGS
Maximum Allowable
Supply Voltage
Guaranteed Operating
Voltage Range

~upply

7

8

I Mil

71LS/81LS
EMITTER

DIODE
INPUTS
7

INPUTS
7

758/85$
SERIES
7

4.50 to 5.. 50
4.75 to 5.25

. 1 Coml

UNITS

V
V

Maximum Input Voltage

5.5

5.5

7

5.5

5.5

V

Maximum Voltage to OpenCollector Outputs*

7

8

7

7

7

V

I

-55 to +125
o to +70

°c

Storage Temperature Range

,';;5 to +150

°c

Operating Free-Air
TemPerature Range

Mil
1 Coml

3·JJ

~

Table of Contents

Proprietary
Device No.

DM80L06
DM7090/DM8090
DM7091/DM8091
DM7092/DM8092
DM7093/DM8093
DM7094/DM8094
DM7095/DM8095
DM70L95/DM80L95
DM7096/DM8096
DM70L96/DM80L96
DM7097/DM8097
DM70L97/DM80L97
DM7098/DM8098
DM70L98/DM80L98
DM7099/DM8099
DM7121/DM8121
DM71 L22/DM81 L22
DM7123/DM8123
DM71 L23/DM81 L23
DM7130/DM8130
DM7131/DM8131
DM7136/DM8136
DM7160/DM8160
DM71 LS95/DM81 LS95
DM71 LS96/DM81 LS96
DM71 LS97/DM81 LS97
DM71 LS98/DM81 LS98
DM7200/DM8200
DM7210/DM8210
DM7211/DM8211
DM7214/DM8214
DM7219/DM8219
DM7220/DM8220
DM7223/DM8223
DM7230/DM8230
DM7511/DM8511
DM75L 11 /DM85L 11
DM7512/DM8512
DM75L 12/DM85L 12
DM7520/DM8520
DM8531
DM7542/DM8542
DM7544/DM8544
DM7546/DM8546
DMB5S50
DM7551/DM8551
DM75L51/DM85L51
DM7552/DM8552
DM75L52/DM85L52
DM7553/DM8553
DM7554/DM8554
DM75L54/DM85L54

Page
No.

Description

Quad 2-lnput NAND Gates with Resistive
Pull-Ups
Quad Inverters plus Dual 2-lnput NAND
Gates
Quad 2-lnput NAND 8uffers
Dual 5-lnput NAND Gates
TRI-STATE Quad Buffers
TRI-STATE Quad Buffers
TRI-STATE Hex Buffers
TRI-STATE Hex Buffers
TRI-STATE Hex Buffers
TR I-ST ATE Hex Buffers
TRI-STATE Hex Buffers
TRI-STATE Hex Buffers
TR I-STATE Hex Buffers
TRI-STATE Hex Buffers
TRI-STATE Quad 2-lnput NAND Buffers
TR I-STATE Data Selectors/Multiplexers
Quad 2-lnput Data Selectors/Multiplexers
TRI-STATE Quad 2-lnput Data Selectors/
Multiplexers
TRI-STATE Quad 2-lnput Data Selectors/
Multiplexers
1O-Bit Magnitude Comparators
6-Bit Unified Bus Comparators
6-Bit Unified Bus Comparators
6-Bit Magnitude Comparators
TRI-STATE Octal Buffers
TRI-STATE Octal Buffers
TR I-STATE Octal Buffers
TR I-STATE Octal Buffers
4-Bit Magnitude Comparators
8-Line Data Selectors/Multiplexers
8-Line Data Selectors/Multiplexers
TR I-STATE Data Selectors/Multiplexers
T R I-ST A TE Data Selectors/Multiplexers
9-Bit Parity Generators/Checkers
1-line to 8-Line Demultiplexers
TRI-STATE Dual 2/4 Demultiplexers
Dual Gated Flip-Flops
Dual Gated Flip-Flops
Dual Gated Flip-Flops
Dual Gated Flip-Flops
Modulo-N Dividers
TRI-STATE 16k Read Only Memories
TRI-STATE Quad I/O Registers
TRI-STATE Quad Switch Debouncers
TRI-STATE 8-Bit Universal I/O Shift
Registers
6-Bit Shift Registers
TR I-STATE 4-Bit 0 Type Registers
TRI-STATE 4-Bit 0 Type Registers
TR I-STATE Synchronous Counters/Latches
TR I-STATE Synchronous Counters/Latches
TRI-STATE 8-Bit Latches
T R I-STAT E Synch ronous Cou nters/ Latches
TR I-STATE Synchronous Counters/Latches

3-iii

Package

J
Mil

3-3
3-3
3-3
3-5
3-5
3-7
3-7
3-7
3-7
3-7
3·7
3-7
3-7
3·9
3-11
3-13
3-13

•

•
•
•

•
•

•
•
•
•
•
•
•
•
•
•
•
•
•

•
•
•
•

•
•
•

3-17
3-19
3-19
3-17
3-21
3-21
3-21
3-21
3-23
3-25
3·25
3-28
3-28
3-32
3-35
3-37
3-40
3-40
3-40
3-40
3-44
3-49
3-52
3-54
3-56

•
•
•
•
•
•
•

•
•

•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•
•
•
•
•

•
•
•

•
•
•
•
•
•

•

•
•
•

•

•
•
•
•
•
•

•
•
•

•
•

•

•
•
•
•
•
•
•
•

•

•
•

•

Mil

•
•
•
•
•
•
•

•

•
•

•

•
•
•

•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•

•
•
•

•
•
•
•
•
•
•

Coml

N/A

•

•

N/A

•
•
•
•
•
•

Coml

•
•
•
•
•
•

•
•
•
•
•
•
•
•
•

3-13

3-60
3-62
3-62
3-64
3-64
3-70
3-64
3-64

Mil

N/A

3-1

W

N
Coml

•
•
•
•
•

•
•
•
•
•

•

•
•
•
•
•

•
•
•
•
•
•
•
•
•

•
•

•
•

•
•
•
•
•

(F)

(F)

•

•
•
•
•
•
•
•
•
•
•
•
(F)
•

•

•
•

•
•
•
•
•
•
•(F)
•

N/A

•
•
•

•
•

•
•

•
N/A
•
•
•
N/A

•
•
•
•
•
•
•

•
•
•
•
•..
•
•
•
•
•

•
•
•

~

Proprietary
Device No.

DM7555/DM8555
DM7556/DM8556
DM7560/DM8560
DM75L60/DM85L60
DM7563/DM8563
DM75L63/DM85L63
DM75S68/DM85S68
DM7570/DM8570
DM7573/DM8573
DM7574/DM8574
DM7575/DM8575
DM7576/DM8576
DM7577 /DM8577
DM7578/DM8578
DM8581
DM7590/DM8590
DM7595/DM8595
DM7596/DM8596
DM7597/DM8597
DM7598/DM8598
DM7599/DM8599
DM7613/DM8613
DM76L 13/DM86L 13
DM76L24/DM86L24
DM76L25/DM86L25
DM76L70/DM86L70
DM76L75/DM86L75
DM76L76/DM86L76
DM7678/DM8678
DM7679/DM8679
DM76L90/DM86L90
DM76L93/DM86L93
DM76L97/DM86L97
DM76L99/DM86L99
DM7795/DM8795
DM7796/DM8796
DM7853/DM8853
DM7875A/DM8875A
DM7875B/DM8875B
DM8898
DM8899

Table of Contents
Page
No.

Description

TR I·STA TE Programmable ·DecadeCounters
TR I·STATE Programmable Binary Counters
Synchronous 4·Bit Up/Down Decade
Counters
Synchronous 4·Bit Up/Down Decade
Counters
Synchronous 4·Bit Up/Down Binary
Counters
Synchronous 4·BitUp/Down Binary
Counters
64·Bit Edge·Triggered Registers
8·Bit Serial In/Parallel Out Shift Registers
1024·Bit Field Programmable Read Only
Memories
TR I·STA TE 1024·Bit Field Programmable
Read Only Memories
Programmable Logic Arrays
Programmable Logic Arrays
256-Bit Programmable Read Only Memories
TR I-STA TE 256-Bit Programmable Read
Only Memories
TR I-ST A TE 16k Read Only Memories
8-Bit Parallel In/Serial Out Shift Registers
4096-Bit Read Only Memories
TRI-STATE·4096-Bit Read Only Memories
TRI-STATE 1024-Bit Read Only Memories
TRI-STATE 256-Bit Read Only Memories
TR I-STA TE 64-Bit Random Access Memories
Quad Gated Flip-Flops
Quad Gated Flip Flops
TR I-ST ATE Magnitude Comparators with A
Almost Equal B
TRI-STATE 7-Segment to BCD Decoders
8-Bit Serial In/Parallel Out Shift Registers
Presettable Decade Counters
Presettable Binary Counters
7 by 9 Character Generators
7 by 9 Character Generators
8·Bit Parallel In/Serial Out Shift Registers
Binary Counters
TRI-STATE 1024-Bit Read Only Memories
TRI-STATE 64'Bit Random Access Memories
4096-Bit Read Only Memories
TRI-STATE 4096,Bit Read Only M~mories
Dual Retriggerable Resettable Monostable
Multivibrators
TRI-STATE 4-Bit Parallel Binary Multipliers
TRI-STATE 4-Bit Parallel Binary Multipliers
TRI-STATE BCD to Binary Converters
TRI·STATE Binary to BCD Converters

3-iv

3·72
3·72
3·76
3·76
3·76
3·76

J
Mil

Com I

•

•
•
•
•

•
•
•
•
•

•

0

0

•
•

3-92

•

3-95
3-95
3-101
3-104

•
•
•.,

•
•
•
•
•
•
•

3-134
3·86
3·137
3·137
3-140
3-140
3-110
3,142
3-144
3-148
3-113
3·116
3-151
3-154
3-154
3-156
3-156

•

•

3·82
3·86
3·89

3-107
3-110
3-113
3-116
3-119
3-122
3-127
3-40
3-40
3-131

Package
N
Mil
Coml

•

•

•

•
•
•
•
•
•
•
•
•

D

•

•
•
•
•
•

•
•
•

•
•
•

•
•
•

•
• •
• •
N/A
• •
• •
• •
• •
• •

•
•
•
•
•
•
•
• N/A

N/A

•
•
•
•
•
•
•

•

•
•
•
•
•
•

•

•
•
•
•
•
•

•
• •
• •
N/A
• •
• •
•
•
• •
• •
• •
• •
•
•
•

•

•
•
•
•

W
Mil

Coml

•
•
•
•
•
•

•
•
•

•
•
•
N/A

•

N/A

•

N/A
N/A
N/A
N/A
N/A
N/A

•

N/A
N/A
N/A
N/A
N/A

•

• •
• •
• •
• •
• •
• •
• N/A •
N/A

•

•
•
•

•
•
•

N/A
N/A

•

•
•

N/A
N/A
N/A
N/A

~ Proprietary

DM80L06
Quad 2-lnput NAND Gates with Resistive Pull Up

General Description

Features

These quad two-input NAND gates feature internallyconnected, 20 kQ pull-up resistors on the outputs. The
pinout is the same as the very popular DM54L03/
DM74L03, and these devices provide the same "onetenth-power technology" as well.

• Typical power dissipation

12mW

• Typical propagation delay

115 ns

Connection Diagram

Vee

B4

A4

V4

B3

A3

V3

V2

GND

10

Al

Bl

VI

A2

80L06(N)

3-1

B2

~

DM80L06

Proprietary

Electrical Characteristics

overrecorrimended oi:>er~tirig free-air temperature' range (unfess otherwise noted)

.'.

DM80L
CONDITIONS

PARAMETER

VIH

High Level I nput Voltage

Vil

Low Level Input Voltage

UNITS

L06
TYP(1)

MIN

MAX
V

2
0.7
200

10H

High Level Output Current

V OH

High Level Output Voltage

10l

Low Level Output Current

VOL

Low Level Output Voltage

Vee

~

Min, IOL

II

Input Current at Maximum Input Voltage

Vct

~

Max, VI

~

S.SV

IIH

High Level I nput Current

Vee

~

Max, VI

~

2.4V

III

Low Level Input Current

Vee

~

Max, VI

~

0.3V

los

Short Circuit Output Current

Vee

~

Max

ICCH

Supply Current (Total with Outputs High)

Vee ~ Max, VI ~ 0

ICCl

Supply Current (Total with Outputs Low)

Vee

Vee ~ S.OV, V IL ~ 0.7V, IOH ~ 100/J.A

~

Max.. VI

~

Max, V IH

~

2.0

<1

-0.17

~

SV

/J.A
V

2.S

2V

V

3.6

mA

0.4

V

100

/J. A

10

/J.A •

-0.12

- word B,
2) word A < word B, or 3) word A ~ word B. A strobe
input overrides all other inputs, and when taken to a high
logic level, places both outputs in the low state. Comparison of words longer than four bits each may be
accomplished through the use of additional DM7200/
DM8200 devices.

• Typical power dissipation

175mW

• Typical propagation delay

20 ns

Connection Diagram
OUTPUT

Vr14

AflJ

Y
12

Af

11

L

l

STROBE

/9

10

B

~

+---J

L.:::4

r'-'

......

I'

84

r
--""
12
BJ

on;:

IT
x

T f'.J'

~r-I--I

~

r

:-;:;

:::»;
/

I

J

B2

14

15 _
Ne

Bl

OUtT

x

A4, 84 are most significant bits.

7200/8200(JI, IN), (WI

Truth Table

INPUTS

OUTPUTS

CONDITION

STROBE

X

Y

DON'T CARE

H

L

L

A>B

L

H

L

Ahort Circuit Output Current

Vee

-55

mA

Icc

Supply Current

Vee ~ Max

53

mA

I,

Input Current at Maximum Input Voltage

I'H

Vee

~

5.5V

mA

-18

Max(2)

35

Notes
(11 All typical values are at Vee = 5V. TA = 25'C.
121 Not more than one output should be shorted at a time.

Switching Characteristics

vee ~ 5V, TA ~ 25°C
DM72/82
FROM
TO
CONDITIONS
(INPUT) (OUTPUT)

PARAMETER

00
MIN

tpLH

Propagation Delay Time, Low-to-High Level Output

Data

Output

tpHL

Propagation Delay Time, High·to-Low Level Output

Data

Output

CL~15pF

RL

tpLH

Propagation Delay Ti me, Low·to-H igh Level Output

Strobe

Output

tpHL

Propagation Delay Time, High-to·Low Level Output

Strobe

Output

tSETUP Setup Time
tHOLD

~

400Q

10

Hold Time

0

3·24

UNITS

TYP MAX
24

40

ns

17

30

ns

15

27

ns

8

18

ns

0

ns

-10

ns

~

Proprietary

DM72/DM8210 ,11
8-Line Data Selectors/Multiplexers

General Description

Features

These monolithic data selectors/multiplexers contain full
on-chip binary decoding to select the desired one of eight
data sources. The DM7211/8211 have a strobe input,
which must be at a low logic level to enable these devices.
A high logic level on the strobe latches the output in a
high logic state, regardless of the conditions on the other
inputs. Depending upon the 3-bit binary number applied
to the select lines, the non-inverted data present on the
selected input is passed to the output. The circuit can
also be used to convert parallel input data to serial
output data. If 8 bits of parallel i'nformation are applied
to the inputs, and if the binary numbers 000 through 111
are sequenced on the select lines, the output will provide
a serial presentation of the input bits.

•

Full on-chip decoding

•

Series 54/74 compatible

•

Converts parallel data to serial data

•

One volt typical noise immunity

•

Typical propagation delay

22 ns

•

Typical power dissipation

100mW

Connection Diagrams

l

SELECT
INPUT
A
14

DATA INPUTS

,

I

1

13

5

6

11

12

OUTPUT

4

8

9

10

....-

16

r-

1

2

B

Vr

C

3

4

0

,

5

1

2

3

SELECT
INPUTS

6

7

15

13

14

,
STROBE OUTPUT

4

5

11

12

G!:

3

2

B

C

\

, ,

0

4
1

SELECT
INPUTS

DATA INPUTS

5

6

2

3

,

NV

OATA INPUTS

7210(J), (W); 8210(J), (N), (W)

7211 (J), (W); 8211 (J), (N), (W)

Truth Table
SELECT
INPUTS

STROBE
(OM7211iDM8211
ONLY)

OATAINPUTS
0

1

2

3

4

5

6

7

OUTPUT

C

B

A

L

L

L

L

L

X

X

X

X

X

X

X

L

L

L

L

L

H

X

X

X

X

X

X

X

H

L

L

H

L

X

L

X

X

X

X

X

X

L

L

L

H

L

x

H

X

X

X

X

X

X

H

L

H

L

L

X

X

L

X

X

X

X

X

L

L

H

L

L

X

X

H

X

X

X

X

X

H

L

H

H

L

X

X

X

L

X

X

X

X

L

L

H

H

L

X

X

X

H

X

X

X

X

H

H

L

L

L

X

X

X

X

L

X

X

X

L

H

L

L

L

X

X

X

X

H

X

X

X

H

H

L

H

L

X

X

X

X

X

L

X

X

L

H

L

H

L

X

X

X

X

X

H

X

X

H

H

H

L

L

X

X

X

X

X

X

L

X

L

H

H

L

L

X

X

X

X

X

X

H

X

H

H

H

H

L

X

X

X

X

X

X

X

L

L

H

H

X

X

X

X

X

X

H

H

X

L.
H

X

X

H
X

X

x

X

X

x

X

X

X

H

3-25

9

10

-

1

,

.

DATA INPUTS
I

r--

, 6

\

SELECT
INPUT
A

H
L
X

=0;

High Level

=

Low Level

0;:;

Don't Care

J:

~. Proprietary

DM721DM8210,11·

Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted)
DM72/112
CONDITIONS

PARAMETER

MIN
VIH

High Level I nput Voltage

VIL

Low Level Input Voltage

VI

Input Clamp Voltage

TYP(1)

Vee

~

Min,

II

High Level Output Vol tage

Vee

~

Min,

Low Level Output Current

VOL

Low Level Output Voltage

Vee = Min,

MAX
V

0.8

0.8

V

-1.5

-1.5

V

-400

-400

~-l:?mA

V IH

~

2V

IOH ~ -400/lA
10L

UNITS

MIN . TYPf1)
2.

High Level Output Current

VOH

MAX

2

TA ;, 25°C
10H

11

10

2.4

2.4

V IL = 0.8V

IOL = 16 mA

/lA
V

16

16

mA

0.4

0.4

V

1

1

mA

40

40

/lA

-1.6

-1.6

mA

-55

mA

33

mA

Input Current at Maximum

II

I nput Voltage

Vee

~

Max,

VI

~

5.5V

IIH

High Level I nput Current

Vee = Max,.

VI = 2.4V

IlL

Low Level Input Current

Vee = Max,

VI

los

Short Circuit Output Current

Vee = Max(2)

Ice

Supply Current

Vee = Max(3)

~

0.4V

-55

-18
20

-18
20

33

Notes
(1)

All typical values are at Vcc = 5V, T A = 25° c.

(2)

Not more than one output should be shorted ,at a time.

(3)

ICC is measured with all inputs grounded..

Switching Characteristics Vee = 5V, TA = 25°C
DM72/82
PARAMETER

FROM

TO

CONDITIONS

10

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

. tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

UNITS

11

MIN TYP MAX MIN

TYP MAX

Data

Output

23

32

23

32

ns

Data

Output

21

30

21

30

ns

Strobe

Output

N/A

21

30

ns

19

27

ns

C L = 15 pF, RL = 400n
Strobe

Output

N/A

Select

Output

31

43

31

43

ns

Select

Output

31

42

31

42

ns

3-26

~ Proprietary

OM72/0M8210 .11

Logic Diagrams

10

.;P

SElECT C
D1

1121

-6r-

V

1

I
(11)

D'

;mt>

SElECT B

D5

,....
T

{101

......

I

5
~

'--D4

191

.~

SElECT A
D3

D2

D'

DO

F'~ 4"'

181

OUTPUT

-;::::::

I ,....
3

161

~,}--

151

141

F' F=I,

131

':;:6."'
11
STROBE (10)

SelECT

~;P
7 (14

......

T

;mt>

1""'"

I

,1131

SELECT

-

V

6}--

,....

I

5

5 1121

;::::::t

4 (11)

SElECT A

(15)

I

1 (4)

,131

r--o

v

3

3 161

,151

4 "-

~'r--

1-'-"1,""'"

6'J
3·27

1'1 OUTPUT

~ . Proprietary

oM72/OM8214.19
TRI"STATE Data Selectors/Multiplexers

General Description

Features

These devices are the TAI·STATE versions of the ·very
popular DM54153 (DM7214) and DM54150 (DM7219)
data selectors/multiplexers. They contain full on·chip
decoding to select the desired data input. The DM72141
8214 is a dual, four-line multiplexer, while the DM72191
8219 selects one of sixteen input data lines, depending
upon the binary number applied to the select inputs. The
DM7214/8214 has common select lines, which therefore.
select the same input line of both multiplexers. However,
the two outputs can be individually controllec1 by means
of the separate enable lines; which, when taken to a.high
logic level, places the output in the high·imlledanc;e
TAl-STATE condition. The data at the output of the
DM7214/8214. is true, whereas the DM7219/8219 is
inverted.

• TRI·STATE pin equivalents to popular 54/74 TTL
devices
DM7214/8214 - 54153/74153
DM7219/8219 - 54150/74150
• Typical propagation delay
DM7214/8214
DM7219/8219

.• Typical power dissipation
DM7214/8214
DM7219/8219

• Strobe/enable override

Connection Diagrams

1
E7
\

2

E6

3

E5

4

E.

.

5
El

6

E2

DATA INPUTS

7

El

B

9

11.r

D GND
EO, ENABLE W
OUT DATA
SELECT

7219(J), IF}; 8219IJ}, IN}, IF}

3-28

10

13.5 ns
11 ns

170'rnW
225mW

~

Proprieta ry

Electrical Characteristics

DM72/DM8214.19
over recommended operating free-air temperature range (unless otherwise noted)
DM72/82
CONDITIONS

PARAMETER

MIN
V'H

High Level I nput Voltage

V'L

Low Level I nput Voltage

V,

Input Clamp Voltage

10H

High Level Output Current

TVP(1)

==

Min,

I, =-12 mA

I DM72

High Leve! Output Voltage

10L

Low Level Output Current

VOL

Low Level Output Voltage

1010FF)

Vee = Min

V IH = 2V

VIL = 0.8V,

10H ~

Max

Vee:;; Min,

V 1H

2V

VIL = O.8V,

10L = 16 mA

Off·State IHigh·lmpedance State)

Vee == Max

Output Current

V IH = 2V
V, .. = 0.8V

I,

Input Current at Maximum

Vee = Max,

Input Voltage

I

;;;;

MIN

TVP(1)

MAX

2

I DM82
VOH

MAX

2

Vee

UNITS

19

14

V

0.8

0.8

V

-1.5

-1.5

V

-2.0

-2.0

-5.2

-5.2

2A

V

2.4
16

16

rnA

0.4

OA

V

Va =OAV

-40

-40

Vo = 2.4V

40

40

1

1

V, =5.5V

I'H

High Level Input Current

Vee

=

Max,

V,

I'L

Low Level I nput Current

Vee

==

Max,

V I =O.4V

los

Short Circuit Output Current

Vee = Maxl21

Icc

Supply Current

~2.4V

Vee = Maxl31

~A

rnA

40

40

~A

'-1.6

-1.6

rnA

-100

mA

-55

-18

I DM72
I DM82

mA

-28

34

56

45

68

34

65

45

68

mA

Notes

= 5V, TA = 25°C.

(1)

All typical values are at VCC

(2)

Not more than one output should be shorted at a time, and for the DM7219/DM8219 duration of short circuit should not exceed one second.
ICC is measured with all inputs grounded.

131

Switching Characteristics vee = SV, T A = 2SoC
DM72!82
PARAMETER

FROM

CONDITIONS

TO

MIN

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low··to-High Level Output
Propagation Delay Time,
High-to-Low Level Output

tZH

MIN

TVP

MAX

15

23

13'

20

ns

Data

Output

12

18

9

14

ns

Select

Output

20

34

21

35

ns

Select

Output

20

34

22

33

ns

12

18

15

23

os

14

21

17

27

ns

5

10

5

10

ns

15

23

21

30

ns

= 50 pF,

RL = 40011

Output Enable Time to

Output Enable Ti me to
Low Level

tHz

MAX

Output

High Level
tZL

TVP

Data

CL

tpHl

UNITS

19

14

Output Disable Time from
High Level
C L = 5 pF, RL = 40011

tLZ

Output

Di~able

Time from

Low Level

3·29

.'

~ Proprietary

OMn/OM8214.19

Truth Tables

14

SELECT INPUTS
B

A

DATA INPUTS
CO C, C2 C3

X

X

x

L

L

H

x

x

ENABLE

OUTPUT

x

H

Hi-Z

L

v

x

x

X

X
L

X
X

X
X

H

H

H
X

H

X

H

X

X

H

L

X

X

X

X

H

X

H

X
X

X
X

X
X

L
H

H

H
H

H

H

H

L
L

X

19

SELECT
ENABLE
DATA INPUTS
OUTPUT
~D---C----B----A~
G ~E-O--E-'---E-2---E-3--E-4---E-5---E-6-.-E-7---e-8---E9---E-'-O--E-1'--E-'-2--e-'-3--E-'4--e-'-54 v
X

x

x

L

L

L

L

.L

x

x

H

L

,H

H

L

x
x

x
x

,x

X

x

x

x

x

x

L

H

H

H

H

H

H

H

H

H

H

H
H

L
L

H

L

L

L

x

x
x

L

L

x

x

H

L

x

H

L

H

H

H

H

x

x
x
x
x
x
x

L

L

x

x

L

L

x

x

X
X
X
X
X

L

H

H

L

H

H

H

H

L

H

H

H

L

H

H

H

H

H

H

H

H

x
x
x
x
x
x

x
x
x
x
x
x

x
x
x
x
x
x

H

L

L

x
x
x

L

x

H
H

H
H
H
H
H
H

L
L
L
H
H
H

H

H

x
x
x

x

x

x

L

X

X

H

X

X

x
x
x
x

X

X

H

L

x
x
x
x

x
x
x

x

H

x

x

x

L

x
x
x

x

L
H
X
X
X
X
X
X
X
X
X
X
X
X

H

x
x

x

x

x
x

H

x

x

x

x
x

H

H

x

x

H
X
X
X
X
X
X
X
X
X
X
X
X
X
X

H

x

x

X

L

x

x

X

L

x

x

L

H
H

x
x

x
x
x

L

H

L
L

x
x
x
x

x
x
x

X

L

x
x
x
x
x

x
x
x

X

H

x
x
x
x
x

x
x

L

l.

x

x

x
x

X
X
X
X

L
L

x

x
x

X

X
X
L
H

L

x
x
x
x
x
x
x

x

x

L
H
X
X

L

x
x
x
x
x
x
x

x
x
x

x

L

L

x
x
x
x
x
x
x

x
x
x

H

L

x
x
x
x
x
x
x

x
x
x

X
L

X

X

X
X

H
X

X
L

X-

X

H

X

X

X

x
x
x
x
x
x
x

x
x
x
x
x
x
x

Hi-Z

x

x

x

x

H

x

x

x

x

L

x

x

x

x

H

x
x
x
x

x

,x

x

x

x

x

x
x
x

x

x

x

x

L

x

x

x

H

x

x

x

x

x
x

x
x
x

x
x
x

x
x
x

x
x
x

x
x
x

x
x
x

H

L
H
H

L
H

x

x

x
x

x
x

H

X

x

L

x

H

X

x
x

x
x

x
x

X

X
X
X

X

L

x

x

X

X

X

H

x

X
x

x
x
x
x
x
x
x
x
x
x
x

X

x

L

X
X

X
X

X
X

L
H

X
X

X
X

x

H

X

X
X

x
x
x
x
x
x

x
x
x
x
x
x

x
x
x
x
x
x

x
x
x
x
x
x

x

x

x

x
x

H

x

X

H

X

X

X

X

X

L

X

H

X
X
X

X
X
X

X
X
X

H
X
X

X
L
H

H

x

X

x

i<

H

X

x

x

x

L

x
x
x

x
x
x

x
x
x

X
X

x
x
x

H

x

X

x

x' x

X
X
X
X
X

x

x

x

x

x

x

X
X
X

x

x

x

X

x

x

x

X

x
x
x
x
x
x

x
x
x
x
x
x
x

x
x
x
x
x
x
x

x
x
x
x
x
x
x

3-30

x

x
x
x
x
x
x
x

X
X

X
X
X
X

L
H
H

L

H
H
H

~ Proprietary

DM72/DM8214.19

logic Diagrams

14

ENABLE

(I)

STROBE 01

DATA 1

DATA 2

ENABLE 115)
STROBE G2

19
OUTPUT
W

00:)

III I I 1
tr

l

~

!1

II

\h\[1il\~
~

III

11

11

l

III

;h ~ ~
D

0
C

,,

C

A
A

.
,

I9)
STROB
(ENABl

" " " " "
"
'" '"
" " " " '"
~--------------------------------------~v~---------------------------------------'
181

111

(61

151

(41

III

l21

111

E4

(23)

IZ2)

(1:1)

(201

(191

E12

DATA
INPUTS

(18)

(17)

(16)

E15

(15)

(14)

.

(13)

DATA
SELECT
(BINARY)

(11)

~' Proprietary

DM72/DM8220
9-Bit Parity Generators/Checkers

G,eneral Description
These circuits can be used both to check 'for parity and
to generate a parity bit, When the generation of a parity
bit is desired, the eight data inputs, are connected to the'
,transmission lines. If a low logic level is then connected
to the parity input, the circuit will generate o,dd parity.
The succeeding parity checker will acknowledge an odd
number 'of "1's" (odd parity) with a low fo'gic level on
its output. If a high logic level is connected to the paritY'

input of the first parity generator, the parity checker
will acknowle(lge even parity with a high logic level on
its output, although the output of the parity generator
will be low.

Features

•
•

Connection Diagram

r

Typical propagation delay
Typical power dissipation

34 ns
130mW

Truth Table

,DATA INPUTS
f

X

H
13

14

E'

F

G

11

12

OUTPUT

T9

10

8

r-

PARITY
INPUT

OUTPUT"

INPUTS A THRU H

H

L

Even number of inputs
are High

L

L

Odd number of inputs
are High

*Single device

X

A

4

3

2

8

.

\

C

5

6
PARITY
INPUT

0

GrO

I

DATA INPUTS

7220/8220(J), (N), (W)

Typical Application
If the control line is a logical "0" the parity generator
will generate odd parity. The paritx checker will
acknowledge the presence of an odd number of "1 's"
(odd parity) with a logical "0" on its output.

If the control line is a logical "1" the parity generator
will generate even parity. The parity checker will
acknowledge the presence of an even number of "1 's"
(even parity) with' a logical "j" on its output.

,

LA

LA
I

"--

B

"--

'----

C

L.-- C

'---- 0
E

CONTROl-

B

'--- 0
OUTPUT

r-

E'

F

F

G

G

H

H

P

P

OM7220/0MB220
AS PARITY GENERATOR

OUTPUT ~

OM7220/0MB220
AS PARITY CHECKER

,

~

DM72/DM8220

Proprietary

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
DM82

DM72
PARAMETER

20

CONDITIONS
MIN

V,H

High Level Input Voltage

V ,L

Low Level Input Voltage

V,

Input Clamp Voltage

TYPlll

-~

Mill,

12 mA

II =-

VO H

High Level Output Voltage

10L

Low Level Output Current

VOL

Low Level Output Voltage

Min,

Vee

2V

V'H

400~A

V" - O.8V,

IOH -

Vee " Min,

V 1H

2V

V" - O.8V,

iOL =

16 mA

UNITS

TYPllI

MAX

2

TA - 25"C
High Level Output Current

MIN

2

Vee

IOH

20
MAX

V

0.8

0.8

V

-1.5

-1 5

V

--400

--400

MA
V

24

2.4
16

16

mA

0.4

0.4

V
mA

I,

Input Current at Maximum Input Voltage

Vee

Max,

VI"" 5.5V

1

1

I'H

High Level Input CUI"rent

Vee = Max,

VI'" 2.4V

40

40

MA

I,L

Low Level Input Current

Vee'" Max,

VI -= D.4V

-1,6

-1.6

mA

los

Short Circuit Output Current

Vee = Max(2)

-55

mA

Icc

Supply Current

Vee

35

mA

~

=-

-55

20
26

Max

-18

35

26

Notes

Vee

All typical values are at

121

Not more than one output should be shorted at a time.

Switching Characteristics

=-

5V, TA

= 25

1
CLOCK

2
G2

4

3
Gl

01

6

5
01

7

01

G!:

CLOCK

7511/8511(J), (N). (WI; 75L 11/85L 11(JI, (N), (WI

Vce

r16

G4

04

04
114

I

I

I

I

Gl

J1

t

Kl

03

G3
13

Cli:

Y

11

112

R

10

I

I

J

I

4

3
MODE 1

01

5
Jl

6
Ql

)

n1

7512/8512(JI, (N), (WI; 75L 12/85L 12(J), (N), (W)

115

I

J~K

2

·1

CLEAR

I

I l

I

4

3

GV

01

I

I

J

L6

)

02

-7613/8613(JI, (N), (WI; 76L 13/86L 13(JI. (NI. (W)

3-40

J:

J:

Electrical Characteristics

PARAMETER

CONDITIONS
MIN

VIH

High Level. Input Voltage

VIL

Low Level Input Voltage

VI

Input Clamp Voltage

~OH

High Level Output Current

VOH

High Level Output Voltage

VOL

Vee = Min,

c.>

:!':

DM76/86

DM75L/85L".12

11.12

13

DM76L/86L 13

TVP{11

MAX

Vee = Min, V IH = 2V

MIN

TVP(11

MAX

2

I, = -12 mA

Low level Output Current

MIN

TVPt11

UNITS

2

V

0.8

0_8

-1.5

-1.5

N/A

V

-800

-800

-200

/lA

2.4

2.4

0.7

16

16

2.0

16

16

3.6

Vee = Min, V IH = 2V

Military

0.4

0.4

0.3

VIL = Max, IOL = Max

Commercial

0.4

0.4

0.4

V

Input Current at Maximum Input Voltage

Vce = Max, VI = 5.5V

1.0

1.0

0.1

mA

High Level Input Current

Vee = Max, VI = 2.4V

40

40

10

/lA

IlL

Low Level Input Current

-1.6

-1.6

Short Circuit Output Current

Icc

Supply Current

--{l.18

Vee = Max(3)

11, L11

42

55

12, L 12

44

57

13, L13

(3)

-18

-55

-3

--9

3.5
58

76

-15

mA
mA

3:

3.2

4.5
7.9

0

CO

U1

4.9

5.7

0

3:
-.J
U1
......

mA

...a
...a

!:;
...a

':.
N

Notes
(1) All typical values are at Vee = 5V, TA = 25°C_
(2)

-55

-18

Vee = Max(2)

I»

-<

V

IIH

los

~-

mA

1\

II VI = 0.3V
V I =O.4V

.
~

V

2.4

Military

Vee = Max

"0

'C

MAX

Commercial

.

Low Level Output Voltage

DM75/85

2

VIL = Max, IOH = Max
IOL

~

over recommended operating free-air temperature range (unless otherwise noted)

!:;

Not more than one output should be shorted at a trme.
Supply current is measured with clear/clock at 3V, an other inputs at OV.

N

0

3:

-.J

0)

......
0

-

3:

CO

0)
...a

W

!:
w

Switching Characteristics vcc

FROM

PARAMETER

fMAX

tplH,

Propagation Delay Time,

Clock

Propagation Delay Time,

Clock

High,to,Low Level Output
tpLH

Propagation Delay Time.

Clear

Propagation Delay Ti me,

Clear

High,to,Low Level Output
tWICLOCK'),

tWICLEARI

CONDITIONS

Q

RL=4kr2

Q

11, L 11

12, L12

13, L13

MIN

TYP

30

6

Q

Width of Clock Pulse

Width of Clear Pulse

Setup Time

DM76f86

(Low Power)

.i.
!sETUP

DM75f85

0

w
N

DM75f85

CL ~ 15 pF r(Standard)
RL ~ 400n
C L = 50 pF

Low,to,High Level Output
tpHL

TO

Maximum Clock Frequency

Low,to,High Level Output
tpHL

~

= 5V, T A = 25°C

J, D Inputs

MIN

TYP

MAX

MIN

TYP

45

20

28

20

30

9

6

10

5

7

20

21

35

17

24

95

35

70

41

60

19

30

26

40

22

33

75

125

60

120

70

100

14

20

22

35

NfA

55

95

32

65

NfA

19

30

26

40

21

31

75

125

57

114

68

100

11

25

15

24

16

30

100

30

100

50

20

10

25

13

27

18

100

30

' 100

30

100

50

15

9

15

9

24

16

80

40

110

55

100

55

30
120

MHz

14

100

K Inputs

MAX

55

20

Mode Inputs

Gl or G2 Inputs

MAX

UNITS

NfA

30

20

N/A

NfA

150

85

N/A

N/A

20

13

NfA

NfA

150

80

N/A

N/A

21
60

30
150

NfA

21
85

Hold Time

All

Truth Tables

11, L11

0

0

0

0

0

0

12, L12

0

G1

G2

CLR

°n+1

On+1

J

L

L

L

L

L

H

L

K

L

M
H

L

I»

ns

ns

ns

ns

ns

0

ns

s:-..J

ns

........
0

U1

ns

s:(X)

....U1
!:
....
::..
-"

ns

ns

N

!:
ns

N

0

s:-..J

13, L13

CLEAR

ii'
....

-<

t-c

tHOW

...

':'CI
0
~.

(J)
* Asynchronous Transition

On+1

0

G

CLR

°n+1

H

L

L

H

H

L

L

L

H

L

H

L

H

L

On
H

L

L

L

L

X

H'

X

L

On

On

L

H

H

L

L

X

H

L

On

X

X

H

L

On

0"

H

H

H

L

On

X

X

H

L'

X

X

X

H

L

W

X

X

L

L

0

X

X

X

H

L'

X

=- Don't Care

........

0

s:

(X)

en
....
Co)

t

Co)

~ Proprietary

DM75/DM8511,L11,12,L12,DM76/DM8613,L13

Logic Diagrams
11, L 11

1511111

a

16)(101

. CP

12,L12
191
CLEAR---

0------------_-- - --.

---,

r----------

I
I

I

I

CLEAR

n 1-....--4:.:,171!:,!ll,,:::0)

CP

L _________ _
111_ _
CLOCK_

_ _ _ .J

0------------....- - - - +
13, L13

CLEAR

----

191

CLEAR

0

o

13116){11){141
12)(5){12){151

CLOCK

CP

----

111

3-43

14)(7){1 0)(131

0

~

-DM75/DM8520

Proprietary

Modulo-N Dividers
General Description
serial shift register, the device may be used where
four-bit parallel-in-serial-out shifting is required.
(continued)

Although extremely versatile in a number of applications,
the primary uses of these circuits are in two a~eas:
1. MODULO-N DIVIDER
A single DM7520/DM8520 can be programmed
without external components to divide by any number
from 2 to 15. Cascading of these dividers will provide
division by any number from 2 to ver." large numbers.

Features
Fu!ly programmable divider-any number from 2 to

1M

2. SHI FT REGISTER
Since the basic organization of the logic is that of a

'" Typical propagation delay

36 ns

'" Typical power dissipation

250 mW

Truth Table

Connection Diagram
EXOR

EXOR

PRESET

INPUT

OUTPUT

16

15

14

0000
OUTPUT

GNU

DETECT

1.1

13

SERIAL

EX·OR

OUTPUT CONTROL

10

11

9

--SETTING

:
I

t-

'--

-

:~

I:

P1

3
SERIAl!
PARALLEL
l

15

4

P2

7

6
P3

Vee

7

8
H

H

H

H

l

H

H

L

12

H

13

H

H

14

H

H

15

H

8

H

INPUT

P4

H

H

H
2

P: Pl4-y1

L

l

f-

·BY

H

H

SERIAL
INPUT

----1

TABLE FOR DIVISION BY N

EXTERNAL

1

00

.. Also functions as a four-bit paraliel shift register

L

H

10
11

INPUT

7520(J), (Wi; 8520(Ji, (Ni, (Wi

Logic Diagram
EX-OR OUTPUT

(141
(±)

1 I16~1t><>-=E_.X_T_E~:_X:_~_~ Ir:l- '-5_1'- _-_-~=_=_=_=_~=~=_=_J_~ ~ ~ ~ ~ --==--_-b~~~~=~ ____,
__

PRESET -

SERIAL III
INPUT

--l
(101 SERIAL
OUTPUT

INPUT~(B~II~~________~-+

(21
PI

L--c><:"f.......l-1.5V - -.....--:..-I--~;..:...

OUTPUT

3v----\-r----""
STROBE

ov ___J

I: 1 MHz
t,: t,,; 10 ns (10% t. 90%)
Duty Cycle 50%
;::E

3·51

.~ Proprietary

DM75/DM8542
TRI-STATE Quad I/O Registers

General Description

Features

These circuits are four-bit storage registers having two
terminals per bit, which may be used as either inputs or
outputs while tied to their individual bus lines. Storage
capability is also provided by means of positive·edge
triggered flip·flops having a common clock and asyn·
chronous clear. Each 1/0 terminal can be forced into the
high·impedance state by applying a high logic level to
·its disable control. The four A outputs are tied together
on one disable control, while the four B outputs are tied
together on a separate disable contrpl.

• "TRI·STATE outputs

Connection Diagram

40MHz

• . Typical clock frequency

• Typical propagation delay

24 ns

• Typical power dissipation

400mW

Truth Table
MODES OF OPERATION

v

c

T"

DIS 1

.4

."

B4
14

AJ

BJ

11

13

CLOCK

"

11

CLEAR

,

A 11-41 B (1-4)

E1

E2

L

.H

H

H

a

Hi·Z

Output data to Bus A

H

L

H

H

Hi·Z

L

H

H

a

a
a

Output data to Bus 8

L
H

H

H

H

Hi·Z

Hi·Z

Output data to both buses
S~ore

data with output in high

impedance state

r-

,

2

1
DIS 2

COMMENTS

DIS2

DIS 1

Al

"

4

6

5

A2

B2

-E2

7

-E1

.t'

X

L

L

H

Data

On

Enter data from Bus A

X

H

L

H

Data

Hi·Z

Enter data from Bus.A

Data
Data
Data

Enter data from Bus B

L

X

H

L

On

H

X

H

L

Hi·Z

X

X

L

L

Data

GND

Enter data from Bus B

Enter data from both buses
(logical "1" on either will
dominate)

75421J1, (W); 8542(J), (N), (W)

Clear = Logical "1," puts all outputs to L state.
X = Don't Care
On = Data After Clock Transition

Logic Diagram

(21

Al

(JI

B1

(51

141

A2

B2

3·52

(11)

AJ

(12)

"

{14)

A4

UJ)

B4

~~~~p-ro--p-r--i-e-ta-~-----------------~------------------------D-M--7-5-ID~M-8-5-4-2--=~ectrical

Characteristics over recommended operating free-air temperature range (unless otherwise noted)

I

1___

PA

DM85

RAMETE~~ _ _ _ _ _ _--t______C_O_.N_D_I_T_IO_N_S_____--:I-f--_M=I-N_-_-_.-_-__-_-_-_-~---t---T-y-4--:(:-1--:)-M-A-X-l, UNITS

_V_'c.H'---t_H",ig_h_Levei Input VoltagF!

II

__ ~

2

Low Levellnput Vo:tagc

VIL

1-----+---!_VI

0.8

V cc "'Min,II""--12rnA

I__
I
I '"

I'~~w"~ "","","""""eo,
- ~ -_.
VOltage---~ -v-c-c·-~--M-in-,-V-'-H-~-2-V----------I--------

!,

.I

~H

High Level Output Current

VOH

High Level Output Vol ta 9c

Vec.
\IlL

IO(OFF)

I~

Min, V: H

-;;0

=

V

- 5.2

mA
V

2.4

Max

16

mA

I

0.4

V IL

=

0.8V,

Off State (High Irnpedance State)

Vee

I

Output Current

V,c - 0.8V

I

Input Curr-e-n7'ia-'-M-ax-,-m-u-m-I'-'P-L-'t-V-o-'t-a-g-e-+-vcc

I

101

~

- 40

O.4V

-"----+---------

1

L-e-ve-I-I-n-p-c--,t-C-'u--r-re-.r-,t-----~I-V--cc-.. -C;-2-M-a-x-,-V-,-~-2-.-4-V-

IlL

-

los

Short Ci:cuit Output Current ___ ~~ CC ;:;: N1ax(2}

ice

Supply Current

High

!. Vo

Low Leve! Input Current

\I CC'

~cc

-----;otes

Max, V I

-"

OAV

1.0

-1.6

-1.0

IlA
rnA

40

pA

-1.6

mA

----------+---------- --".---------25
-70
-25
-70
mA

Max

=

~--

II-:-cV"o'---::2'C.4coV-+---------:·-::-+--------:-::--1
40

Max, VI ::.. 5.5'1

00-_

V

16 mA

rVlax, V 1H '-°2V

=

II

II

'"

- - - - - - - - - - - - - - . - + - - - - - - - - - - - r - - - - - + - - . - - - - - - - - I f - . - . - - - - - - -- -

I'H

(1)
(2)

2V

O.8V, iot-!

j

l

V

-'1.5

Level Output

-VOL

!

I

------------------------r---.-------+--------;:-t---

lnputCl2rnp'Joltage

80

120

80

120

mA

------------'----------'--------'----

All typiGal values are at Vee = 5V, TA 25°C.
Not more than one output should be shorted at a ti rne.
000

Switching Characteristics vee ~ 5V, TA ~ 25°C

'M.

PARAMETER

r

TO

CONDITIONS

-----.-------------------+-----~------------.~-------------t------------------r_----__fM:.c.:..:A:'::X_ _I--Maximurn Clock Fre~Uency
.1--_ _--1

--.+---___
I

Propagation Delay Time,

tpLH

Low-to·High Level Outout

Pro pagation Delay Time,

tpHl

Hig h-to-Low Lc\'cl Output

rl~,

Clock

Outpu t

Clock

Output

I

---------+------4--0·utPu~
Pm pagation Delay Time,

tpHL

Hi9 h-to-,Low

tZH

Clear

Level Ou-::put

j

Output Enable Time to

____ -+HiQ_h_L_e_ve_I_ _ _ _ _ _ __

tZl

_____t-L_OW

Level

~

-----

17

I

Output Disable rime frorn

tHZ

I

_ _ _ _+_Hi9h Level

I

----------------------+--------

Output Enable Time to

Tir~"e
from
.
-----

15

Output DiSC'lbl.e."
LOvi/ Levei

tW(CLOCKl

Clock Pulse Width

tW(CLEAR)

Clear Pulse Width

20

--------t------

I

tSETUP_+_E_na_b_le_-_se.tuP Time

I-'-:

UP

\

L

tHOLD

25

r_-~~-----~~------~

High Level
Low Level

Data Setup Time

High Leve!

Data Hold lime

IL~
~i9h Levei
I Low

Level

I--_O____~____
5.0

--4.0

~·----4---3~-5---

I
3-53

---------

6'
::
ns

-1

ns

I

~ Proprietary

DM75/DM8544
TRI-STATE Quad Switch Debouncers

General Description

Features

These circuits are for use. in front panels, and similar
applications where contact bou.nce must be eliminated.
Within the single package, these circuits do the job of
four R-S latches plu's pull-up resistors. A strobe is also
available which permits sampling of the switch information at a predetermined time. TRI-STATE outputs ~re
also provided for direct connections to the switch
line bus.

• Replaces SN54279174279
• Eliminates push-button noise
• Allows clocked devices to be operated 'from switches
• Maximum power dissipation
250 mW
• Bus-line connectable
• TRI-STATE outputs
18 ns
• Typical propagation delay

Connection Diagram

Vee

01

02

116

15

Truth Table
TRI-STATE
ENAaLE,

QD

14

13

C2

12

CI
It

Qe
10

r--

l-

I

STROBE

9

2

A2

3

5

.4

7

6

a.

AI

A1

A2

TRI·STATE
ENABLE

STROBE

X

X

H

X

Hj·Z

X

X

L

L

L

L

,_

QA1t- tl

L

H

L

H,

L

H·

L

L

H

H

'H

H

L

H

QA(tl

t

1
8

GNO

7544/8544(J), (N), (W)

Logic Diagram

S.Ok

(3)

~A2~(2~'t

-i-t__

__- '__

~~J---L--'
I

I
I

+

I

.

TO OTHER
LATCHES

3·54

•

I a. (71
.IOc (9)
I Go (13)

°AhI

Indeterminate

~

Proprietary

OM75/0M8544

Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted)
DM75
PARAMETER

CONDITIONS
MIN

V,H

High Level Input Voltage

V,L

Low level Input Voltage

V,

Input Clamp Voltage

IOH

High Level Output Current

V OH

High Level Output Voltage

10L
VOL

Low Level Output Voltage

44
MAX

MIN

Vee

=
=

Min, V 1H
O.SV,

""

IOH

2V

O.8V,

Off State (High Impedance State)

Vee

Output Current

V 1L =O.BV

=

IOL =

Max, V 1H

=

16 mA

I Va ~ OAV

2V

V
0.8

·-1.5

-1.5

V

-2.0

·-5.2

mA

16

16

mA

OA

OA

V

I Vo -2.4V

-40

-40

40

40

1

1

V

Input Current at Maximum

I,

Input Voltage
I'H

Hi'gh Lev,ellnput Current

I,L

Low Leve! Input Current

Vee

=:

Max, VI

Vee

=

Max, VI = 2.4V

_

=

S.SV

_

Vee - Max, VI - O.4V

los

Short Ci reuit Output Current

Vee

Icc

Supply Current

Vee - Max

~

I Strobe/Enable
! Data

Max(2)

-18

V

2A

Vee = Min, V 1H = 2V
=

UNITS
MAX

0.8

2A

= Max

TYP(1)

2

Vee = Min, I) "" --12 mA

V 1L
IOIOFF)

TYP(1)

2

V 1L

Low Level Output Current

DM85

44

-30

40

40

-1.6

-1.6

-2.5

-2.5

-55

--18

-30

50

~A

mA
~A

mA

-55

mA

50

mA

Notes
( 1)

All typical values are at Vee"" 5V, TA == 25°e.

(21

Not more than one output should be shorted at a time.

Switching Characteristics vee = 5V, T A = 25°C
DM75/85
PARAMETER

FROM

TO

CONDITIONS

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

Data

Output

Data

Output
CL

IZH

~

50 pF, RL

Output Enable Ti me to

Output Enable Time to
Low Level

'HZ

Output Disable Time from
High Level
C L = 5 pF, R L

'LZ

Output Disable Time from
Low level

355

TYP

MAX

20

36

ns

17

·30

ns

15

25

ns

12

24

ns

5

10

ns

10

20

ns

=40051

High Level
'ZL

UNITS

44
MIN

=400n

DM75/DM8546
TRI-STATE 8-Bit Universal I/O Shift Registers
General Description

Features

These circuits are TRI-STATE, 8-bit,edge-triggered,
universal shih registers which are capable of operating
in any of the following modes: shift left, shift right,
parallel load, or inhibit_ Since the clock is edge-triggered,
the control lines which determine the mode of operation
are completely independent of the logic level applied to
the clock_ Designed for bus-oriented systems, these
circuits have their TRI-STATE inputs and outputs on
the same pins_

.. Positive-edge triggered clock

Connection Diagram
C2

lice

I"

"

RSlIlSD

lIO 1

14

13

tiD 2

1103

"

1104

Cl

J

~SIIRSO

I/O B

,
1/01

Both paraliel and serial data lines are TRI-STATE

•

High impedance state does not impede shift mode
with parallel outputs

00

,

10

11

l-

,

•

Truth Table

r-

I

.. "Do nothing" state without gating the clock

,

5
1/06

liD Ii

7

CLOCK

STATE OF
PARALLEL I/O

C2

L

1-1

H

Inhibit

H

H

H

Inhibit

X

H

L

P~rallel

L

L

H

Right Shift

H

L

H

Right Shift

Hi-Z*

Data In
Data In

L

L

L

Left Shift

QOUT

GOUT 1

H

L

L

Left Shift

Hi-Z'

00UT 1

Load

RSI/LSO

LSI/RSO

GOUT
Hi-Z'

Hi-Z'

Hi-Z'

Hi-Z*

Hi-Z*

Data In

Hi-Z'

OOl.,lT

I'

ONO

STATE OF
SERIAL I/O

Cl

Hi-Z"
GOUT 8

Q OUT 8

Data In
Data In

00' Output Disable (Cl, C2 • Mode Controls)
*~oth

7546(J), (W);.8546IJl, (N), (W)

MOOE OF
OPERATION

00

Input and Output of the 1/0 pin are in the hi,gh impedance state.

Logic Diagram

C1

-,,111--~~=h~~~:::[~>-

______ ________________________________________________________j
~

C2-""1"~I~-l~~~:::::::::[2>~------------------~--------~-----------------------------------J
"TAI·SfATE GAl'£

3-56

~

OM75/0M8546

Proprietary

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
DM75

PARAMETER

CONDITIONS
MIN

V,H

High Level Input Voltage

V,l

Low Level Input Voltage

V,

Input Clamp Voltage

10H

High Level Output Current

V OH

High level Output Voltage

10l

Low l,evel Output Current

Val

Low Level Output Voltage·

1,

I,l

46
MAX

Vee = Min, II

= -12

UNITS

TYP(l)

V'L

=o.av, 10H =Max

Vee

= Min,

V
0,8

Vee

Output Current

V,L

= Max,

V 1H

Input 'Current at Maximum

Vee = Max, VI

HiQh Level Input Current

Vee

Low Level Input Current

-1.5

-1.5

V

-5,2

mA

2,4

I:;l

2V

Vee = Max. VI = O.4V

loS

Short Circuit Output Current

V ee 'Max(2)

Icc

Supply Cu~rent

Vee:;: Max

16

mA

0.4

V

=O.4V

-40

-40

40

40

1

1

= S.5V

=Max, V, =2.4V

16
0.4

V a=2.. 4V

Va

I

/-LA

mA

C'2lnput

80

80

Others

40

40

C21nput

-3.2

Others

-1.6

-3.2
-1.6

mA

-70

mA

-30

-70

ao

-30

80

115

Notes
(1) All typical value. are at VCC = 5V, T A ~ 25"C,
(2) Not more than one output should be shorted at. time,

= 5V, T A

V

2.4

=0.8V, 10L = 16 mA
=o.a'v

V

-2.0

= 2V

V 1H

MAX

2

mA

Vee = Min, V 1H = 2V

Off State (High Impedance State)

Switching Characteristics vee

,MIN

0.8

I nput Voltage
I'H

TYP(1)

2

V'c
IOIOFFI

DM85

46

125

/-LA

mA

,

= 25°C
DM75/85

PARAMETER

CONDITIONS

f MAX

Maximum Clock F'reque,ncy

tPlH

Propagation Delay, Low-ta-High Level,

From Clock to Output
tpH~

.ZH

Propagation Delay. High-to-Low Level,
From Clock to Output
Propagation Delay From High

Impeda~ce

State

,to High Logic Level (From Output Disable)
tZH

CL

=50 pF, RL

• 400n

Propagation Delay From High Impedance State
'io.Hlgh Logic Level (From Mode Control eltC2)

tZl

Propagation Delay From High Impedance State
to Low Logic Level (From Output Disable)

tZL

Propagation Delay From High Impedance State

to Low Logic Lovel (From Mode Control Cl/C2)
tHZ

Prop,gation Del!)v From High Logic level to

tHZ

Propagation Delay From High Logic Level to

High I mpedance State (From Output Disable)

High Impedance State (From Mode Control
Cl/C2)
tlZ

Propagation Delay From Low Logic Level to

CL

TVP

15

22

UNITS
MAX
MHz

16

24

ns

27

40

ns

22

33

ns

13

20

ns

18.

27

ns

15

23

ns

5

a

ns

9

14

ns

16

24

ns

17

26

ns

=5pF, RL =400n'

High Impedance State (From Output Disable)

ILz

46
MIN

Propagation Delay From Low Logic Level to
High Impedance State (From Mode Control

Cl/C21

3-57

~" Proprietary'

DM75/DM8546

Switching Characteristics Vee

=5V, TA = 25°C
DM75/85

PARAMETER

CONDITIONS

46
MIN

.tWICLOCKI
tSETUP (HIGH!

. tsETUP IHIGHI
tsETUP ILOW)

UNITS.

TYP

MAX

Clock Pulse Width

18

12

ns

Serial Data

38

25

ns

Parallel Data

33

22

ns

Serial Data

21

14

ns

12

ns

CL

= 50 pF, RL = 4000

18

tsETUP ILOW)

Parallel Data

tHOLD IHIGH)

Serial Data

0

-11

ns

tHOLD (HIGHI

Parallel Data

0

-11

ns

tHOLD ILOW)

Serial Data

0

~22

ns

tHOLD (LOW)

Parallel Data

0

-21

ns

ns

SETUP. AND HOLD TIMES BETWEEN CHANGES'IN MODE CONTROL AND CLOCKING
tSETUP'

Parallel load to Right Shift

32

21

t~ETUP

Parallel load to Left Shift

40

27

ns

tSETUP

Right Shift to Parallel Load

60

40

ns

tSETUP

Left Shift to Parallel Load

53

35

ns

tSETUP

Right Shift to left Shift

33

21

ns

tsETUP

left Shift to Right Shift

56

37

ns

tsETUP

Inhibit to Right Shift

57

38

ns

tSETUP

Inhibit to left Shift

65

43

ns

tsETUP

Right Shi,ft to Inhibit

50

33

ns

!sETUP

left Shift to Inhibit

50

32

ns

tHOLD

Parallel load to Right Shift

9

6

ns
ns

CL

= 50 pF, RL =40011

tHOLD

Parallel Load to left Shift

6

4

tHOLD

Right Shift to Parallel load

'0

-13

ns

tHOLD

Left Shift to Parallel Load

0

-46

ns

tHOLD

Right Shift to left Shift

0

-10

tHOLD

left Shift to Right Shift

0

-23

tHOLD

Inhibit to Right Shift

0

-18

tHOLD

Inhibit to left Shift

0

-16

ns

tHOLO

Right Shift to Inhibit

0

-12

ns

tHOLD

left Shift to Inhibit

0

-29

ns

ns

,

ns

.

ns

Typical Applications
CASCADING DEVICES
TO COMMON BUS

1/01·

. . .(

• • 1/0'

I/O 1-

-.lLlIIIII

•

•

t

•

•

• • ~ • • • 1/08
I I I I I II I

1/01 •

• 1/08

I I I II I II

OTHER

OTHER

LSI/RSO

DEVICES
COMMg:

BUS

~

DM7546

~ DEVICES

LSI/RSO
DM754G

RSI/I,SO

OR

DM7!i48

RSI/LSO

,

COMMON

BUS

1 I

1

I

1

I

1

C1
Cl

co
00

3-58

~ Proprietary

OM75/0M8546

Typical Applications (Continued)
SERIAL DATA TRANSFER TO A FIRST IN-FIRST OUT STORAGE MEDIUM

TO COMMON BUS

I/O l '

•

•

t

• I/O 8

I I I I I I I I
TRI-STATE BUS OF

FIRST IN-FIRST OUT
STORAGE MEDIUM

.:.s~

~

OM7S46

OTHER

• • I/O 8

•

I I I I I I I I
RSI/LSO

····DEVICES····~

I

I

I/O l '

LSI/ASO

l-

QM7546

I 1
1

00
CP

C1

C1

n

TRI·STATE BUFFER (1093/94)
DISABLE THIS OUTPUT

WHEN RECEIVING DATA
FROM STORAGE MEDIUM

SERIAL DATA

I/O CONTROL

Timing Diagram
TYPICAL PARALLEL LOAD, RIGHT SHIFT, LEFT SHIFT AND INHIBIT SEQUENCES

CLK

I
I
I

n

n

00

--~--------------~I
I
I
I
I
I ______~__________________~I__~____~I
I __~
C1--'~__________________~
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
RSI/LSO
I
I
I
I
~--------~+-~--------~----------------~--~I
I
I
I
I
I

r-

I

"'--1

--LJI

ill

I/O 1

1/02

I/O 3

1/04

I/O 5

1/06

lIn 1

I/O 8

lSI/RSO

I

I

PARALL~!~ f-~-------RIGHTSHIF~

I.

_I

OUTPUT

I-

OUTPUT

__
'_018_A_Bl_E_ _ _ _ _ _ _ _ _ _ _ lEHSHIFT _ _ _ _'_O_IS_AB_"E_t-_INHIBIT _ _

3-59

~ Proprietary

DM85S50
6-Bit Shift Registers

General Description
These 6-bit shift registers feature J-K serial inputs,
parallel outputs. and a direct overriding clear_ All inputs.'
are buffered to lower the input drive requirements to
one standard DM74S load_ Furthermore. shifting is

synchronous. and occurs on the positive-going edge of
the clock pulse. Thes~ shift registers are particularly
well-suited for very high speed data processing systems.

Connection Diagram

Truth Table

Vee

116

06

06

15

05

13

.14

04

04

12

11

CLOCK
2

1
CLEAR

CLEAR

<

2

4

3

-01

6

5

-

02

1
03

18

GND

r-;-""2

L

X

X

H

L

L

H
H

L
H

H
L

H

H

H

H
·L

H

t
t
t

H

H

01

OUTPUTS

CLOCKS

9

10

-

INPUTS

CLOCK
1

J

K

X
X
X
X
X
L

X
X
X
X
X
L

L

L

H

L

H

t

L

H

L
H

H

L

L

L

L

H

H

L

H

L

t
t
t
t

L

H

H

t

H

H

H

t

H

L

H

H

X
X

X

X

01

02

03

04

05

06

L

'-

L

L

L

L

01 0

020

030

040

050

060

01 0

0.20

030

040

050

01 0 020

030

04 0
040

060
05 0 060

050
01 0 020 030
L O1 N O2 N 03 N O4 N
O1 N 01N Q2N Q3 N 04 N
O1 N 01N 02N 03 N O4 N

060
05 N
05 N

05 N
01 N 02 N 03 N O4 N OSN
L 01 N 02 N 03N 04 N OSN
O1 N 01N 02 N 03 N O4 N OSN
O1 N 01 N O2N 03 N O4 N OSN

H

H 01 N 02 N Q3 N 04 N OSN
01 N 02 N 03 N O4 N OSN 06 N
O1 N 02 N 03 N O4 N 05 N 06 N

010.020. etc. ~ The level of Ot. 02. etc. before the indicated
steady~state input conditions were established.
01N. 02N. etc. ~ The level of 01, 02, etc.,bef~re the most-

recent t transition of the clock; indicates a l-bit shift.

Logic Diagram

\

3-60

To Be Announced In 1976

~

DM85S50

Proprietary

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

I

DM85S
PARAMETER

CONDITIONS

I

MIN
VIH

High Level I nput Voltage

VIL

Low Level I nput Voltage

VI

Input Clamp Voltage

IOH

High Level Output Current

VOH

High Level Output Voltage

10L

Low Level Output Current
Low Level Output Voltage

TYP(l)

MAX
V

2

1,~~18mA

Vee ~ Min,

VOL

UNITS

S50

Vee ~ Min,

V'H ~ 2V

V'L ~ 0.8V,

IOH

Vee ~ Min,

V'H ~ 2V

~~1

mA

2.7

0.8

V

~1.2

V

~1.0

mA

3.4

V
20

V'L

= 0.8V,

0.5

IOL~20mA

1\

Input Current at Maximum Input Voltage

Vee ~ Max,

V,

~

5.5V

IIH

High Leve! Input Current

Vee ~ Max,

V,

= 2.7V

IlL

Low Level [nput Current

Vee

= Max,

V,

= 0.5V

los

Short Circuit Output Current

Vee

= Max(2)

Icc

Supply Current

Vee ~ Max

1
50

~40

mA
V
mA

M/l·

~2

mA

--100

mA

150

mA

90

Notes
(1)
(2)

All typical values are at VCC ~ 5V, TA = 25°C.
Not more than one output should be ,shorted at a time, and the duration of the short circuit should not exceed one second.

Switching Characteristics

vee ~ 5V, TA

= 25°C
DM85S

PARAMETER

MAX
!_f
tpLH

Propagation Delay Time,

Propagation Delay Time,
High-la-Low Level Output

tpLH

Propagation Delay Time,
LOW-lo·High Level Output

tpHL

CONDITIONS

TO

Maxllnum Clock Frequency

Low-to·High Level Output
tpHL

FROM

Propagation Delay Time,
High-ta-Low Level Output

Clock

Oar 0

Clock

OorO
CL

= 15 pF,

UNITS

S50
MIN

TYP

75

110

MAX
MHz

8

12

ns

12

18

ns

RL = 280n

Clear

0

10

15

ns

Clear

Q

13

20

ns

3·61

~ Proprietary

OM75/0M8551,L51
TRI-STATE 4-Bit 0 Type .Registers

General Description
These four-bit registers contain D-type flip-flops with
totem-pole TRI-STATE outputs, capable of driving
highly capacitive or low-impedance loads. The highimpedance state and increased high-logic-level drive
provide these flip-flops with the capability of driving the
bus lines in a bus-organized system without need for
interface or pull-up components.

theoutplJt control circuitry is designed so that the
average output disable times are. shorter than the average
output enable times.

Features
• TRI-STATE outputs interface directly with system
bus
• Gated output control lines for enabling or disabling
the outputs
• Fully independent clock eliminates restrictions for
operating in one of two modes:
Parallel load
Do nothing (hold)

Gated enable inputs are provided for controlling the
entry of data into the flip-flops. When both data-enable
inputs are low, data at the D inputs are loaded into their
respective flip-flops on the next positive transition of
the buffered clock input. Gate output control inputs are
also provided. When both are low, the nc;>rmal logic
states of the four outputs are available for driving the
loads or bus Iines. The outputs are disabled independently
from the level of the clock by a high logic level at either
output control input. The outputs then present a high
impedance and neither load nor drive the bus line.
Detailed operation is given in the truth table.

•

To minimize the possibility that two outputs will
attempt to take a common bus to opposite logic levels,

Connection Diagram

For application as bus buffer registers

TYPE

TYPICAL
PRO PA ATION
G
DELAY

TYPICAL
FREQUENCY

7551/8551
75L51/85L51

18 ns
59 ns

30 MHz
15 MHz

TYPICAL
POWER
DISSIPATION

250mW
27.5 mW

Logic Diagram
DATA ENABLE
INPUTS

DATA INPUTS

~

Vee

CLEAR

116

01

"

02

14

04

OJ

13

11

GZ

Gl

10

11

I,

tf

+-_,. . .

OA~~-,I:.:.14,-1_ _ _ _ _ _

I

.----,-,./"~-o,

.~
\'
M

3

1

0'

N

'----------'
OUTPUT
CONTROL

4,
02

,

S

Q4

QJ

)

CLOCK

\'

GNO

'--~--~

DATA (13)

D2

OUTPUTS

7551(J), (W); 8551(J), (N), (W);
75L51/85L51 (J), (N), (W)

01
~LOCK

m

Truth Table
INPUTS
DATA ENABLE
CLEAR

CLOCK

Gl

G2

DATA

OUTPUT
0

D

H

X

X

X

X

L

L

L

X

X

X

L

H

X

X

L

t
t

X

H

X

00
00
00

L

1

L

L

L

L

L

t

L

L

H

H

DATA (12)

03

03

-r-......

+_--'-__

DA~:-'1..;,11i'-_ _

When either M or N (or both) is (are) high the output is
disabled to the high-impedance state; however, sequential
operation of the flip-flops is not affected.

H =: high level (steady state}
L = low level '(steady state}
t = low·to-high level transition
X = don't care (any input induding transitions)
QO,= the level of Q before the indicated steady state input
conditions were established

04
(15)

CLEAR

3-62

~

Proprietary

OM75/0M8551,L51

Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted)
DM75/85
PARAMETER

MIN
VIH

High Level Input Voltage

VIL

Low Level Input Voltage

VI

Input Clamp Voltage

10H

t-ligh Level Output Current

VOH

High Level Output Voltage

Vee

TVP(l)

MAX
V

DM75

-2.0

IDM85

-5.2

Min, V 1H == 2V

=:

Off State (High Impedance State)
Curren~

2.4

= Max

tOL ==

Max

2.0

16

3.6

DM75

0.4

0.15

0.3

DM85

0.4

0.2

0.4

-40

I Vo =2.4V

40

~igh Level Input Curre,nt

IlL

Low Level Input Current

loS

Short Circuit Output Current

Vee = Max(2)

Icc

Supply Current

Vee = Max(3)

Vee

Vee = Max, VI = 2.4V
Vee = Max

V
mA

mA

V

-40

= Max, VI = S.SV

Input

IIH

V

V

16

I Vo =O.4V

II

-1.0

DM85

Iyo =O.3V

Max

-1.0

DM75

Vee =Max
==

N/A

2.4

V ,H = 2V

V 1L
Current at Maximum Input Voltage

= Max,

0.7

-1.5

Vee == Min, V 1H == 2V
V IL

Output

MIN
2

Vee == Min, II = -12 rnA

Low Level Output Voltage

1010FFI

MAX

0.8

Low Level Output Current

VOL

UNITS

L51

TVP(l)

2

V 1L == Max, IOH

10L

DM75L/85L

51

CONDITIONS

/lA
20

1

0.Q1

0.1

mA

40

I

10

/lA

I V, = 0.3V

-0.18

I V, _ 0.4V

-1.6

-30

-70

-3

72

50

-8

mA

-15

mA

9

mA

5.5

Notes
(1)

All typical values are at Vee = SV, TA = 25°C ..

(2)

Not more than one output should

(3)

ICC is measured with all outputs open; clear grounded following momentary connection to 4.SV; N, G1, G2, and all data inputs grounded; and

be shorted at a time.

the clock input and M at 4.SV.

Switching Characteristics Vcc

=

5V, T A= 25°C
DM75/85

CONDITIONS
PARAMETER

FROM

TO
BOTH

fMAX

Maximum Clock Frequency

,"HL

Propagati.on. Delay Time,
High-to-Low Level Output

tPLH

Propag~tion

Delay Time,

Low-to·H igh Level Output
tpHL

Propagation Delay Time,
High-to-Low Level Output

tZH

tZL

STD.

tLZ

tHOLD

6

TVP

UNITS
MAX

15

MHz
110

n,

Clock

Output

16

25

39

70

n,

Cloc~

Output

20

28

77

120

ns

7

16

30

28

55

.~ns

7

21

30

35

60

n,

3

5

14

18

50

n,

3

11

20.

32

75

n,

CL = 50 pF
RL = 40011

Outpu"t Disable time from

RL = 4 kl1

CL = 5 pF

?,utput Disable Time from

. Width of Clpck or Cle.r Pulse

Hold Time

30

MIN

72

Low Level

tw

25

L51
MAX

27

Output Enable Time to

'sETUP Setup Time

TVP

18

~evel

High Level

MIN

Output

Low Level
tHZ

LOW POWER

Clear

Output Enable Time to

High

DM75L/8SL

51

20

100

Data Enable

17

45

Data

10

30

Clear I nactive State

10

30

Data Enable

2

0

Oat.

10

10

3-63

n,

n,

n,

~ Proprietary

DM75/DM85.52,L52,54.l54
'

,

TRI-STATE Synchronous Counters/Latches

.

General Description

Features

These circuits logically combine the functions of counters.
for frequency division, latches to store the data from
the counters, and output buffer gates which provide
both standard TTL outputs as well as high-impedance
outputs for multiplexing of data. The counters are fully
synchronous, and are made up of four edge-triggered
JK flip-flops. To further facilitate operation, the Count
Mode and Terminal CO'unt outputs are also operable
when the data outputs are in the high-impedance state
or the latch mode.

• DM7552/8552
DM75L52/85L52
• DM7554/8554
DM75L54/85L54

Decade counter/latch
Binary counter/latch

TYPICAL POWER
DISSIPATION

TYPE

52,54
L52, L54

330mW
38mW

TYPICAL CLOCK
FREQUENCY
23 MHz
11 MHz

I----------------------------------~------------------------~----------Connection Diagram

r

vcc

TRANSFER
ENABLE

16

15

1

2

CP

DUTPUT
. DISABLES

CLEAR

13

12

4

3

C
~

PRESET
14

\

D

11

6

5

.

B

CEP

NC

A

,

OUTPUTS

7552{J), (W); 8S52{J), IN), (W);
7SL52/85L52(J), IN), (W);
7554(J), (W); 8554IJ), IN), (W);
75L54/85L54(J), (N), (W)

Truth Table

3-64

C.ET

10

7

HAM.
CDUNT

61:

~

Proprietary

OM75/0M8552.L52.54.L54

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
DM75L/85L

DM75/85

PARAMETER

CONDITIONS

52,54
MIN

V,H

High Level I nput Voltage

V,l

Low Level Input Voltage

V,

Input Clamp Voltage

10H

High Level Output Current

V cc

I Others

Vee

V 1L

~

Low Level Output Voltage

'OIOFFI

Off State (High Impedance State)
Output Current

=:

=

Min, V 1H

High Level Input Current

Max

Short Circuit Output Current

Icc

Supply Current

~5.2

IOH -

0.4 rnA

2.4

3.3

IOH -

Max

204

3.3

V

-'=

Vee

0

Max, VI = S.5V

Max, V, "OAV (Std.1

Vee 'Max(21

-10

204

2.S

2.4

2.7

mA

V

2.0
3.6

004
004

0.15

0.3

0.2

004

mA

V

-40

Va" 0.3V

2V

V

16

0.2

::

NlA

-1.0

16

DM85

=Max, V 1H

V

DMS5

V 1L -= Max, IOL -= Max
Vee

0.7

DM75

0.2

V, "0.3V (75L1S5LI
lOS

DMS5

DM75

Vee = Max, VI = 2.4V

Low Level I nput Current

I,l

~2.0

IOH '" 0.2 mA

2V

:::

DM75

Vee'" Min, V 1H '" 2V

Vee

Input Voltage

I'H

UNITS
MAX

~1.5

V 1L -= Max

Input Current at Maximum

I,

TVP(11

2

Min, II -= -12 rnA

Low Level Output Current

VOL

MIN

O.S

High Level
Terminal Count
Output Voltage

10l

L52, L54
MAX

2

,l

VOH

TVP(11

Vo "OAV

-40

Va -2AV

40

CET Input

2

0.02

0.2

Others

1

0.01

0.1

CET Input

SO

2

20

Others

40

1

10

MA
20

CET Input

-2.0

-'3.2

-0.24

~0.36

Others

-1.0

-1.6

-0.12

~O.lS

TC Output

-·20

Others

-30

Vee'" Max

66

--55

-3

~S

-15

-70

-3

-8

-15

106

7.6

13

mA

pA

mA

mA
mA

Notes

(11

All typical values are at VCC ~ 5V, TA = 2SoC.

(21

Not more than one output should be shorted at a time, and for DM7552/8552 or DM7554/8554 duration of short circuit should not exceed
one second.

Switching Characteristics vee = 5V, TA = 25°C
PARAMETER

FROM

52,54
BOTH

f MAX

Maximum Clock Frequency

tpLH

Propagation Delay Time,

tpHL

Propagation Delay Time,

tplH

Propagation Delay Time,

tpHl

Propagation Delay Time,

Low-to-High Level Output

High-to-Low Level Output

Low-to-High Level Output

High-ta-Low Level Output

tZH

,Output Enable Time to

tZl

Output Enable Time to

'HZ

Output Disable Time

tlZ·

Output Disable Time

DM75L/85L

DM75/85

CONDITIONS

TO

STD.

LOW POWER

MIN

TVP

15

23

L52, L54
MAX

MIN
6

TVP

UNITS
MAX

11

MHz

Clock

Output

34

70

115

220

ns

Clock

Output

23

45

75

150

ns

Transfer Enable

Output

26

50

90

160

ns

26

50

90

160

ns

21

45

75

150

ns

25

50

90

150

ns

3

S

S

15

ns

17

40

57

105

ns

CL " 50 pF
Transfer Enable

Output

RL "400"

High Level

Low Level

ftom High Level

CL

"

R L "4kSl

5 pF

from Low Level

3-65

I

~ Proprietary

DM75/DM8552.L52;54.L54

Mode of Operation
When the Transfer Enable (TE) is at a logical. "1" level,
the data transfer paths between the counter outputs
and the output buffer gates are maintained. When the
Transfer Enable is at a logical "0" level, the data transfer
paths are inhibited, and the state of the output buffer
gates are locked in by the latches. The counter and
Terminal Count (TC) output remain operable during
this time.

•

To enable the count mode both CET and CEP inputs
must be at a logical" 1" level.

•

To latch the outputs the Transfer Enable (TE) input
must be taken to the logical "0" level.

Asynchronous Clear resets the counter to 0000.

•

To place the TRI·STATE outputs into the "third·
state," either of the Output Disable (00) inputs
must be taken to the logical" 1" level.

Asynchronous Preset sets the counter to 1111.
The 1111 state may be used in the 52 for blanking out
leading zeroes in visual displays. The next clock pulse
will advance the 52 to 0001 which denotes the first
count of the blanked zero. The next clock pulse will
advance the 54 to 0000.

The clock input must be high during the high to low
transition of CEP and/or CET for correct logic operation.
The CEP and CET inputs may be used in a high speed
look ahead.technique.

The Terminal Count (TC) output is active high when
the counters are at terminal count and the CET is high.
The Terminal Count logic equations are:
(52)
(54)

TC
TC

~

~

Counter stages can be cascaded to provide multiple
stage BCD or Binary synchronous counting by using the
52 or the 54 respectively. With a Terminal Count (TC)
fan OLit of ten, eleven stages are able to operate at the
maximum frequency equivalent to a two stage counter.

CET • A • B • C " 0
CET"A -B -C-O

The following logic levels control the device:
•

•

The counters change state on the positive·going
transition of the clock.

The characters displayed can be held with a low level
on the strobe line while the counters can continue
counting. The display can be updated at any time by
applying a positive pulse to the strobe line.
.

Clearing or presetting is enabled by taking the
respective input to a logical "1" level.

OM7552iOM8552
OM75L52iOM85L52
DECADE COUNT SEQUENCE
COUNT

OM7554iOM8554
OM75L54iOM85L54
BINARY COUNT SEQUENCE

OUTPUTS
A

B

C

0

COUNT

TC

H
H

H

H

L

4

.... ,f

L

B

L

L

H

L

C

H

4

5

0

TC

L

H
H

H

L

L

H

L
L

H

L

H

L

H

L

H

H

L

H

H

L

L

H

H

H

H

H

H

L

L

L

H

H

H

H

H
H
10

Applied

11

Next·

H

Count

H

H

H

H

7447A,

H

7448)

for

blanking

leading zeroes.

3·66

H

H

H

H

L

H

H

13

H

L

H

H

14

L

H

H

H

15

H

H

H

H

12

**The 1111 state may be used in conjunction witf:l certain
iDM7446A,

H

H

Preset

decoder/drivers

OUTPUTS
A

H

~ Proprietary

OM75/0M8552 ,L52 ,54 ,L54

Logic Diagrams
52,L52
TERMINAL
COUNT
OUTPUT
(7)

OUTPUT
DISABLES

111
121

SET

SET

CP

.+++--ojCP
ij
RESET

COUNT

T~~~:t~

ij
RESET

(9)

54,L54
TERMINAL
COUNT
OUTPUT

171
111

OUTPUT
DISABLES (2)

3·67

~ Proprietary

DM75/DM8552.L52.54.L54

Switching Time Waveforms

52,54

"=Tl1~~- .. -- . ---

_______~_~_~+~~~~_l____

I
1
'

PRESET-

JtJL~'

1

---.----.---,-------+~----

~I

!

3V

1

"(PRESE~

_____

~

1,5V

ov
__

CLEAR--l~-~---+~-±--~--fE-~--1
,T
----+---I

'I

--II '
+----

i'

I

I

I

,,----+---~

- - - - ,+,

3V
1.5V

ov

I

'PiClEAR)

I

3V
~~~~

t.5V

ov
3V

TE~--+I~~~---+-

I

-----l-----~-~-, --~------

I

I

I

'I

I

1.5V

+_I-,r---h,
~ \--~~

~ _____.____ ::;

1

OUTPUTS _ _

-=r:~- ~f±:l~Il'-.---------..J

vOl

tpHL

3V =£='V

=t
3t=

TE'

--l.SV--TE

I

~~--ov

OUTPUTS-~~

1.5V

---ov

I

VO H =
I
J f ' VOH
~~-1'5V-~- -1.5V

I

-vOl----

.LH
lTE1-

--

VOL

.Hl

irE)

"

r-----------------3V

3V

oV_,.PUTt.HZ~-~-,5V
-.l

ACTUAL
LOGICAL ''1''
VOLTAGE

OUTPUT

OV

'"J{

1.5V

""1.5'11
~---

5V

---_IS

tZH

INPUT~' 3'

J

INPUT----.~~_

3V

--~~-I.5V

ou

~

'ZH-

lr

OUTPUT---,"'

1.5v

OUTPUT

\ ..._ _ _ _ _ _ 1.5V

3-68

~ Proprietary

DM75/DM8552.l52.54.L54

Switching Time Waveforms (Continued)

L52, L54

I

I
'v
-------.---"~~--+----+----

t.JV

OV

lV

---~-

~~--j

i

I-----j

'SiCEI

--t---

uv
ov

1- 'Ai'"

'v

TE--i----t--l----r------~---------~--I
i
I
I

Iii

OUIPUTS

1.3V

----- ~::

I

--L--+~--HIt=tt-~-~----~=+-.
~~'PLHr- ~ ~---1 "rlSl---~"dR~

± ~---=:~v-=-t-----~:v
'V_T<~lV

TE----

=t§= ---=r-

VOH==jf1VOH

1

O!1TP.UTS----;-

•

1

--1.3V----

I

-'1'LH

_

i----------~-

'"_'U....}'

VOLTAGE

VOL

(TE)

,---------'V

'"_PU_T..J~-I-l---~

lV

-t,ll,{

oV _ _ _ _
1.3V

~

I---'HZ-~'

LOG1~~~~~~·-----------

1.JV

tl'HL

(TE)

OV _______

I

--VOL

--~v--

:=f,--_.-

OUTI'U1

tZL

b-1.3V
·------3V

INPUT-----,

INPUT

\~-~

---

'v

---1.3V

OV

~-~

'ZH

I

t~-

~--I

OUTPUT _ _ _ _ _

~

tZL

r~

--,~

-1.3'.'

OUTPU1

\L-_

'

3~69

UV

~ Proprietary

DM75/DM85'53
TRI-STATE 8-Bit latches

General Description
By utilizing TRI-STATE circuitry on the outputs, the
,inputs and outputs can be accessed on the same pins,
and these circuits provide eight separate A-S latches in
the popular 16-pin package. While in the high-i'mpedance
state, the inputs and outputs are disabled and no information can be entered. When both WRITE inputs are
brought to a low logic level, the outputs are disabled and
new information may be entered at the inputs. When
a low logic level is applied to both READ inputs,' and a

Connection Diagram

high logic ,level to both WRITE inputs, the inputs are
rendered inactive and' data may. be read from the outputs.

Features
• TRI-STATE I/O pins
• 8 latches in popular 16-pin package
• Typical propagation delay-22 ns

Logic Diagram

DATA INPUTS/OUTPUTS

Vee = 16

"

I..

"

"

"

12

11

,

10

GNO;oa

DATA INPUT/OUTPUT 1

I~----------,
,
I I

(:::4J~....._ - ; - . . .

I
I
I
I

rDATA INPUT/OUTPUT 2

,

t

REAfl

Emu

,

,

4

,

:::;(5',-+++-;-...

7

CLEAR

GNO
OA-TA INPUTS/OUTPUTS

"

7553(J), (W); B5531J1, (N), (W)

Truth Table
DATA INPUT/OUTPUT 7

CLEAR

ENABLE

READ'

WRITE**

OPERATION

DATA INPUT/OUTPUT'

STATE OF

BUS

H

L

L

H

Enter L

L

H'

L

L

L

Enter L

Hi·Z

L

X

H

H

Do Nothing

Hi·Z

L

H

X

X

Do Nothing

L

L

X

L

Write

Hi·Z
HDr L**-11

L

L

'L

H

Read

H or L H *

*Both Read Inputs
**Both Write' Inputs

***Depends on State of

lat~h

3·70

~(12:!.'-H'-i-'\

~

DM75/DM8553

Proprietary

Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted)
DM75
PARAMETER

CONDITIONS
MIN

V ,H

High Level t nput Voltage

V,l

Low Level I nput Voltage

V,

Input Clamp Voltage

10H

High Level Output Current

VOH

High Level Output Voltage

10l

Low Level Output Current
Low Level Output Voltage

I,

Vee::: Min, V 1H = 2V

Vee == Min, V 1H

Off State (H igh Impedance State)

Vee

V 1L =O.SV

Input Current at Maximum

=

:::

tOL:::

Max, V 1H

I'H

High Level Input Current

Vee::: Max, VI

I,l

Low Level Input Current

Vee

los

Short Circuit Output Current

Vee = Max(2)

ICC

Supply Current

Vcc=Max

(21

UNITS
MAX

TYPlll

V
0.8

=

Vee = 5V, T A =

=

-1.5

-1.5

V

-5.2

mA

2A

2V
16 mA

I

2V

V

-20

2A

VaoOo4V

I Va =2AV

Vee = Max, VI = 5.5V

Input Voltage

Notes
All typical values are at

MIN
2

Vee''''' Min, II =-12 rnA

Output Current

(1)

53
MAX

0.8

V 1L = a.BV,
1010FFI

TYPlll

2

V 1L =O.8V,I OH =Max

VOL

DM85

53

V

16

16

mA

OA

004

V

--40

-40

40

40

1

1

~A

mA

2.4V

40

40

~A

Max, VI::: O.4V

-1.6

-1.6

mA

-70

mA

93

mA

=

-28

-28

-70
66

93

66

25° C

Not more than one output should be shorted at a time.

Switching Characteristics vec = 5V, TA = 25°C
DM75/85
PARAMETER

FROM

TO

CONDITIONS

53
MIN

tpHL

Propagation Delay Time,

Clear

High-to-Low Level Output
'ZH

Output

Output Enable Time to

C L = 50 pF, RL = 400n

High Level
'Zl

MAX

21

32

os

22,

33

ns

25

38

ns

7

12

ns

20

30

os

Output Enable Time to
Low Level

'HZ

UNITS

TYP

Output Disable Time from
High Level
C L = 5pF, RL =400n

tlZ

Output Disable Time from
Low Level

'W
tSETUP

tHOLD

Minimum Pulse Width

Minimum Data Setup Time

Minimum Data Hold Time

Clear

15

10

Write

40

28

High Level

20

14

Low Level

36

26

High Level

-15

-26

Low Level

-8

-14

3-71

ns
ns
ns

~ Proprietary

DM75/0Ma555.56
TRI-STATE Programmable Decade/Binary C!lunters

Genera! Description

Features

These circuits are synchronous, edge·sensitive, fully·
programmable 4·bit counters. The counters feature both
conventional totem·pole and TRI'STATE outputs; such
that when the outputs are in the high·impedance mode,
they can be used to enter data from the bus lines. In
addition, the clear input operates completely independent
of all other inputs. During the programming operation,
data is loaded into the flip,flops on the positive·going
edge of the clock pulse. To facilitate cascading of these
counters, the MAX COUNT output can be tied directly
into the count enable input.

•

Connection Diagram

Truth Table

Vee

MAX
COUNT I/O D

00

DM7555/8555..,..Decade courtter

•

DM7556/8556-Binary counter

•

Typical clock frequency

•

TRI·STATE outputs

•

Fully independent clear

•

Synchro·nous loading

•

Cascading circuitry provided internally

II0 g

J

K

0

0
0

M

, , ,,
, , ,
L

0

X
X

j(

0

X

X

CLEAR

On+1

0

00

0
0
0
0

,

'* Asynchronous Transition
Note: See Timing Diagrams

7565(J), (W); 8555(J), (N), (W);
7556(J), (W); 8556(J). (N), (WI

Logic Diagrams

35 MHz

55

56

3·72

,

0

G"
D

o·

~

DM75/DM8555.56

Proprietary

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
DM75!8555

PARAMETER

MIN

High Level Input

VIL

Low Level Input Volta\)e

VI

Input Clamp Voltage

10H

High Level Output Current

Vee

=:

Min, "

Low Level Output Current
Low Level Output Voltage

I DM75
I DM85
Vee

=

Mm, V'H = 2V
-=

TVPlll

UNITS
MAX
V

= Min, V:I-l

= 2V

Off State (High Impedance State)

Vee

Output Current

V'H

0::

=:

-5.2

·5.2

-40

'-40

40

40

,

rnA
V

0.4

Vo = 2AV

mA

V
16

0.4

Vo "OAV

V ,L =Max

V

-1.5
",2.0

2.4

Max
2V

V

-1.5

16
Vee

0.8'

-2.0

24

Max

V ,L '" a.BV, tOl "'" 16 rnA
'O(OFFI

MIN

2

-12 mA

=:

V ,L = a.BV, IOH

10L

DM75!8556
MAX

0.8

High Level Output Voltage

VOL

TVPlll

2

Voltagf~

V IH

V oH

CONDITIONS

~A

rnA

II

Input Current at MaXimum Input Voltage

Vee'" Max, V, = 5.5V

1

1

IIH

High Level Input Current

Vee::" Max, V, = 2.4V

40

40

~A

IlL

Low Level Input Current

Vee

Max, V,

1.6

-1.6

rnA

los

Short Circuit Output Current

Vee =- Max(2)

-70

rnA

Icc

Supply Current

Vee

=:

=:

=:

OAV

-25

·70
80

Max

·25
75

110

100

mA

Notes

III

All typical values are at Vee ~ 5V, TA ~ 25°e.

(2)

Not more than one output should be shorted at a time.

Switching Characteristics vec = 5V, TA = 25°C
PARAMETER

fMAX

Maximum Clock Frequency

tpLH

Propagation Delay Time,

FROM

Low-ta-Hlgh Level Output
tpHL

Propagation Delay Time,

tpLH

Propagation Delay Time,

tpHL

Propagatlo~ Delay Time,

High-ta-Low Level Output

Low-ta-High Level Output

High-ta-Low Level Output
tpHL

Propagation Delay Time,
Hlgh-ta-Low Level Output

TO

DM75!8555,56

CONDITIONS

MIN

TYP

25

35

UNITS

MAX
MHz

.Clock

Output

15

22

ns

Clock

Output

34

44

ns

Clock

Max Count

23

33

ns

Clock

Max Count

23

33

ns

Clear

Output

30

44

ns

CL

= 50 pF,

RL

= 4000.

tZH

Output Enable Ti me to High Level

13

20

ns

'ZL

Output Enable Time to Low Level

14

20

ns

tHZ

Output Disable Time from High ,Level

6

12

ns

tLZ

Output Disable Time from Low Level

12

20

ns

tw

Minimum Pulse Width

teE

CL

Count Enable Time

Clock

tSETUP(1)

tHOLO(1)

tSETUP(O)

tHOLO(Ol

HOld Time - High LogIC Level

Setup Time - Low Logic Level

Hold Time - Low Logic Level

RL =4000.
25

Clear

20

Load

30

Setup

30
-30

Hold
Setup Time - High LogIC level

= 5pF,

Data

25

Load

30

Data

5

Load

10

Data

30

Load

25

Data

5

Load

-10

3·73

ns

ns

ns

ns

ns

ns

·~. ProprietarY

DM75/DM8555,56

Timing Diagrams

55 TYPICAL CLEAR, PRESET, COUII!T,INHIBIT SEOUENCE

CLEAR

--1IL-_______------------..:..------

LOAO~~.-------------------------------:,~:~i

______________. . .

r - - l L_ _ _ _ _ _ _ _ _ _ _ _ _

COUNT
DISABLE _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _. . , . . - - - - , . - - -

CLOCK

Sequence
11
Clear to zero.
(2) Load BCD five.
(3~ Co'unt six, seven, eight, nine, zero,

i

IIO{C)

::l..J

(4)
(5)
(6)

one, two, three, four.
Disable TR I·STA TE outputs.
Disable Counter.
Count to six.

..J1

O{B) : : ....
', _ _ _. J r - - l L ._ _ _ _ _. J r - - l L_ _ _ _ _

~{Cl::L....J
O{O, : : ...
', _ _ _ _ _ _- - I r - - l l ._ _ _ _ _ _ _ _ _ _ _ _ _ __
MAX - - i

LJ

COUNT __ ..f

LOAD

COUNT

-----lj

I/O USED
AS INPUTS

DISABLE
OUTPUTS

56 TYPICAL CLEAR, PRESET, COUNT, INHIBIT SEQUENCE
CLEA'

LOAD

-rlL-____________________________
~----------------------------

OUTPUT _ _ _ _ _ _ _ _ _ _.JI. - - - - - - .11._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
DISABLE

COUNT
.....- - - - - - - - - - - - - - - - - -__--....J

DISABLE _ _-

CLOCK

Sequence
(1) Clear to zero.
(2) Load'binary five.
(3) Count six, seven, eight, nine, ten,

I/O (A)
110 (B)

IIO{C)

::LJ

--,.,L-_ _ _ _ _ _ _

(4)
(5)
(6)

.J

IIO{O, __

0{C).::l-..J

-- ,

Q{O, _ _

~'

_ _ _ _ _ _ _--...J

C~~::J'---------------------'L__Jr-~------­

I:LE~'
.

DISABLE

LOAD

----- ..

, . Ito USED

--

~-.,-----~CO:.cU.:.NT---------1 ,.COUNTER'.,I~I

AS,
INPUTS

'I

~

DISABLE
OUTPUTS

I

,-,

eleven,. twelve, thirteen, fourteen,
fifteen, zero.
Disable TRI-STATE outputs.
Disable counter.
Count to one.

~ Proprietary

DM75/ DM8555 ,56

Switching Time Waveforms
CLOCK AND CLEAR VOLTAGE
3V
CLEAR

OV

CLOCK

OUTPUT

MAX

COUNT

COUNT ENABLE AND CLOCK
COUNT
ENABLE

CLOCK

\--------

OUTPUT

LOAD, DATA AND CLOCK

LOAD

DATA

CLOCK

_/

\'----~/

OUTPUT

OUTPUT DI,liABLE

DISABLE

l.SV

1ZHfCOUTPUT

----~T
O.SV

3-75

~ Proprietary

DM75/DM8560,L60,63,L63
Synchronous 4-Bit Up/Down Decade Counters

General Description
These circuits are synchronous up/down counters; the
60 and L60 circuits are BCD counters and the 63 and
L63 are 4-bit binary counters. Synchronous operation
. is provided by having all flip-flops clocked simultaneously, so that the outputs change together when so
instructed by the steering logic. This mode of operation
eliminates the output counting spikes normally associated
with asynchronous (ripple-clock) counters.

of the count and load ,inputs. The clear, count, and load
inputs are buffered to lower the drive requirements of
clock drivers, etc., required for long words .
These circuits are synchronous up/down counters; the
60 and L60 circuits are BCD counters and the 63 and
L63 are 4-bit binary counters. Synchronous operation
is provided by having all flip-flops clocked simultaneously, so that the outputs change together when so
instructed by the steering logic. This mode of operation
eliminates the output counting spikes normally associated
with asynchronous (ripple-clock) counters.

The outputs of the four master-slave flip-flops are
triggered by a low-to-high level transition of either
count (clock) input. The direction of counting is determined by which count input is pulsed, while the other
count input is held high.

Features

All four counters are fully programmable; that is, each
output may be preset to either level by entering the
desired data at the inputs while the load input is low.
The output will change independently of the count
pulses. This feature allows the counters to be used as
modulo-N dividers by simply modifying the count length
with the preset inputs.

•

Fully independent clear input

•

Synchronous operation

•
•

Cascading circuitry provided internally
Individual preset each flip-flop
TYPICAL COUNT

TYPE

A clear input has been provided which, when taken to a
high level, forces all outputs to the low level; independent

FREQUENCY

Vee

J

DATA
A

25 MHz

325 mW

L60, L63

12 MHz

40mW

OUTPUTS

16

DATA B
INPUT

CLEAR
14

15

as

QA

OUTPUTS

INPUTS

BORROW CARRY

LOAD

13

12

11

COUNT
DOWN

COUNT
UP

INPUTS

DATA

e

Qc

OUTPUTS

7560(J), (W); 8560(J), (N), (W);
75L60/85L60(J), (N), (W);
7563(Jl, (WI; 8563(J), (N), (W);
75L63/85L63(J), IN), (W)

3-76

POWER
DISSIPATION

60,63

Connection Diagram
INPUTS

TYPICAL

10

DATA

o

~

OM75/0M8560.L60.63.L63

Proprietary

Electrical Characteristics over recommended operating free-air temperature range (u~less otherwise noted)
DM75/85
PARAMETER

CONDITIONS
MIN

V,H

High Level Input Voltage

V,L

Low Level Input Voltage

V,

I nput Clamp Voltage

IOH

High Level Output Current

VOH

High Level Output Voltage

Vee

=:

Vee:= Min, V 1H
=

::;;0

2V

Low Level Output Voltage

Vee == Min, V 1H

V JL

Input Current at Maximum

I,

High Level Input Current

I'L

Low Level Input Current

Vee
Vee

los

Short Circuit Output Current

V
0.7

-1.5

-1.5

V

-400

-200

).IA

2.4

Max,

tOL

:::

2V

= Max

V

V

2.4

DM75

16

2.0

DM85

16

3.6

DM75

0.4

0.15

0.3

DM85

0.4

0.2

0.4

= Max,
= Max

V,

1

= 2.4V

40

I V, = 0.3V
I V, = O.4V

<1

Vee = Max(3)

rnA

V

0.1

-rnA

10

MA

-0.10

-{U8

-1.6

Vee = Maxl21

Supply Current

ICC

MAX

0.8

Vee = Max, VI ::: 5.5V

I nput Voltage
I'H

"'"

TYP(l)

MIN

Max, IOH "" Max

Low Level Outpu t Current

VOL

MAX

2

I, =--12 rnA

Min

UNITS

LSO, L63

TYP(l)

2

V IL

10L

DM75L/85L

60,63

DM75

-20

-55

-3

--9

-15

DM85

-18

-55

3

-9

15

DM75

65

89

8

13

DM85

65

102

8

13

rnA

rnA

rnA

Notes

Vee

III

All typical values are at

121

Not more than one output should be shorted at a time.

131

ICC is measured with all outputs open, clear and load inputs grounded, and a!! other inputs at 4.5V.

= 5V, TA =- 25"C_

Switch ing Characteristics Vcc

~ 5V, T A ~ 25° C
DM75/85
FROM
INPUT

PARAMETER

TO
OUTPUT
CONDITIONS

f MAX

MaXimum Clock Frequency

tplH

Propagation Delay Time,

20

tpHL

Count up

Propagation Delay Time,

I

Propagation Delay Time,

tpHl

Propagation Delay Time.

Low-to-Hlgh Level Output
Count down

Either Count

Q

CL

7

Propagation Delay Time,

12

MHz

26

30

60

ns

16

24

60

120

ns

16

24

30

60

ns

16

24

50

100

ns

25

38

45

90

ns

C i_
Rl.

= 50

pF

4kll

31

47

75

150

ns

27

40

55

110

ns

29

40

105

200

ns

22

35

95

'190

ns

Propagation Delay Time,
Load

Q

Propagation Delay Time,
Hlgh-ta-Low Levei Output

tpHL

UNITS
TVP MAX

17

15 pF

Low-to-High Level Output
tpHl

6

RL = 40011

High-ta-Law Level Output
tpLH

25

MIN

Propagation OeluY Time,
Law-ta-High Level Output

tPHl

CONDITIONS

Borrow

High-ta-Low Level Output
tPLH

MAX

Carry

High-w·Lovv Level Output
tpLH

L60, L63

MIN TVP

!

Low·ta-High Level Output

DM75Li85L

60,63

Propagation Delay Time,
Clear

High-to-Law Level Output

Q

tw

Width of Any Input Pulse

25

70

ns

tSETUP

Data Setup Time

20

30

ns

tHOLD

Data Hold Time

0

0

ns

f

3-77

~ Proprietary

OM75/0M8560.l60.63.l63

- logic Diagrams
60,L60
(13) BORROW
OUTPUT

"\.

~

(12) CARRY
OUTPUT

DATA (15)
INPUT A

~

rL--"
OOWN (4)
COUNT

(3)
oA

OUTPUT OA

T
QA

UP (5)
COUNT

---rp
-

I

OATA (11
INPUT B

r--

bDT

'-.

~

~
~

~
~

a,

(2)

OUTPUT Oa

T

ITs i-'-

-r--

tf>-

DATA (10)
INPUT C

r-'~

1-

~

(6)

0,

OUTPUT

Dc

OUTPUT

nD

T

0,-

"--fP
- Y
OATA (9)
INPUT 0
CLEAR

114)

~,

r--'-~

--''"'-

aD
T

jjD~

LOAO

~

(11)

3-78

(7)

~ Proprietary

DM75/DM85S0,LSO,S3,LS3

Logic Diagrams (Continued)

63, L63
(13) BORROW
OUTPUT

~

J

(12)

J
DATA (15)
INPUT A

J-

r---'

DOWN (4)
CDUNT

CARRY
OUTPUT

13)

OUTPUT

0.

0.

T

ij.~

UP (5)
COUNT

~

--

DATA (1)
INPUT B

~

rLJ'
~

L

L.L

(2)

OUTPUT QB

DB
T

1

......
f'

~

,.

DATA (10)
INPUTC

~

r--"
..... --;

-

CLEAR

~

OUTPUT

lie

Ocr--

-

(14)

(6)

lie
T

.....-r-

DATA 19)
INPUT D

fiB~

,--

Lrp. ;r-

--

,.

~
'- r--;

.-- "'-(7)

00
T

fiDi--

(11)

J

LOAD

..
3·79

~

OUTPUT Do

~. Proprietary

DM75/DM8560,L60,63,LS:3

Timing Diagrams

60, L60 DECADE COUNTERS
TYPICAL CLEAR, LOAD, AND COUNT SEQUENCES

CLEAR~~

_____________________________________________________________

LOAD
A

L-

I

DATA

L-

I

rCOUNT
UP

-.....,.....,-.....,-+-...,

COUNT----~~--+-+---+----------------~--_,
DOWN

n.
OUTPUTS

CARRY

BORROW

·1
.--"---> .--"--->
CLEAR

-

8

9

D

1

21

COUNT UP--------J

1

1

D

9

871

r--COUNTOOWN~

PRESET

Sequence:
(1) Clear outputs to zero.
(2) ·Load (preset) to BCD seven.

(3) .Count up to eight, nine, carry, zero, one, and two.
(4)

Count down to one, zero, borrow, nine, eight, and seven.

Notes:
(A) Clear overrides load, data, and count inputs.

fB)

Y'Vt:len counting up, count-down input-must be ..high;when counting 'down; countMup i.nput·must be high.

3:80

~ Proprietary

OM75/0M8560,L60,63,L63

Timing Diagrams (Continued)

TYPI~AL

CLEAR

63, L63 BINARY COUNTERS
CLEAR, LOAD, AND COUNT SEQUENCES

~~________~____________________________________________________

LOAD

A

DATA

COUNT----+-+---~~---,
UP
COUNT----+-+---~~--~--------------------~--__,
OOWN

OUTPUTS

CARRY

BORROW

.~~

CLEAR

PRESET

I

14

15

0

1

1

I

- - COUNT UP-------

I

r-1

0

15

14

13

1

COUNT D O W N - '

Sequence:
(1) Clear outputs to zero.
(21

Load (preset) to binary thirteen.

(3)

Count up to fourteen, fifteen, carry, zero, one, and two.

(4)

Count down to one, zero, borrow, fifteen, fourteen, and thirteen.

Notes:
(A) Clear overrides load, data, and count inputs.
(8)

When counting up, count-down input must be high; when counting down, count-up input must be high.

3-81

~Proprietary

DM75/DM85S&S
64-Sit Edge Triggered Regis,ters

General Description

Features

The DM75S68/DM85S68 is an addressable ~'D" register
file. Any of its 16 four-bit words may be asynchronously
read' or may be written into on the next clock transition.
An input terminal is provided to enable or disable the
synchronous writing of the input data into the location
specified by the address terminals. An output disable
terminal 'operates only as a TRI·STATE output control
terminal. The addressable register data may be latched at
the outputs and retained as long as the output store
terminal is held in a 'low state, This memory storage
condition is independent of the state of the output
'disable terminal.

•

On chip output register

•

Edge triggered write

•

High speed

All input terminals are high impedance at all times, and
all outputs have low impedance active drive logic states
and the high impedance TR I-STATE condition.

Connection Diagram

30 ns typ

• TRI-STATE outputs
•

Optimized for register stack applications
350mW

• Typical power dissipation
•

18-pi n package

Logic Diagram

(WRITE
CLOCK
(DATA INPUTS)

[..

Vee

OJ

11

04

16

WE
15

CLOCK

O'S"

14

00

12

13

04

11

1

02

,.

03

(WRITE
ENABLE)

we0 51

A'~
A1

~
...
~

A2

~
~
~

AJ

~
~
~

116 x 4MEMORY CEll ARRAY

I--

2
01

3

AD

4,
A2

5
AJ

7

6

A1

01

75S68(0); 85S68(0), (N)

,
02

INPUT)

J'

GNO

os (131
(OUTPUT
STORE)

Oo(~12{I~~---t~---------+~---------1~----------~
(OUTPUT

DISABLE)

04
(OUTPUTS)

To

Be Announced In 1976

~

DM75/DM85S68

Proprietary

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
DM75S/85S

PARAMETER

CONDITIONS

S68
MIN

V IH

High Level Input Voltage

VIL

!,-ow Level Input Voltage

VI

Input Clamp Voltage

10H

High Level Output Current

VOH

High Level Output Voltage

10L

Low Level Output Current

VOL

Low Level Output Voltage

IOCOFFI

II

Input Current at Maximum Voltage

IIH

High Level Input Current

IlL

Low Level Input Current

UNITS
MAX

2

V

Vee ~ Min, liN = -18 mA

Vee = Min

0.8

V

-1.2

V

DM75

-2.0

DM85

-5.2

10H =-2.0 mA

DM75

10H = -5.2 mA

DM86

= 16 mA

Vee = Min, 10L

Vee

= Max

Vee

= Max,

V

DM75

0.5

DM85

0.45

Va" 0.5V

-40

Va = 2.4V

+40

= 5.5V

V,

1.0

Vee = Max

Clock Input

50

V, = 2.4V

All Others

25

Vee = Max

Clock Input

-500

All Others

-250

V,

= 0.5V
= Max(2)

los

Short Circuit Output Current

Vee

Icc

Supply Current

Vee = Max

mA

2.4
16

Off-State (High Impedance State)
Output Current

TYP(l)

-55

-20
70

100

mA
V

MA
mA
MA

MA
mA
mA

Notes
(1( All typical values are at VCC = 5V and T A = 25°C.
(2) Not more than one 0l!tput should be shorted at a time.

Switching Characteristics
DM75S
PARAMETER

DM85S

CONDITIONS

UNITS
MIN

TYP

MAX

MIN

TYP

MAX
40

Address to Output

30

55

30

tOSA

Output Store to Output

20

35

20

30

tCA

Clock to Output

25

50

25

40

20

40

20

35

14

30

14

24

ns.

10

18

10

15

ns

12

22

12

18

ns

tAA

Access Time

= 30 pF
RL = 400Q

CL

tZH

Output Enable to High Level

tZL

Output Enable to Low Level

tHZ

Output Disable Time From High Level

CL

tLZ

Output Disable Time From Low Level

RL

tA/iC

Set-Up Time

= 5 pF
= 400Q

Address to Clock

25

5

15

5

tosc

Data to' Clock

15

a

5

0

tASOS

Address to Ou tput Store

40

15

30

15.

tWESC

Write Enable Set·Up Time

10

a

5

a

tossc

Store Before Write

15

0

10

0

Address From Clock

15

5

10

5

tOHC

Data From Clock

20

5

15

5

tAHOS

Address From Output Store

10

0

5

0

tWEHC

Write Enable Hold Time

20

5

15

5

tAHC

Hold Time

3-83

ns

ns

ns

ns

~. Proprietary

OM75/0M85S68

Typical Applications
The DM85S68 can enhance the dynamic performance of
a TTL processor, since it may safely operate using single
phase clocking instead of the multi phase clock ing systems
being used currently. Th is simple feature not only enhances the system's dynamic performance, since multiple levels of registers need not be activated, .but also
reduces component count by elimination of one set of
buffer registers. For example, note the simplicity of
I
the register tile/ALU loop shown in Figure 1.

r- R3
~

... RO

r- AAD3

AAD3
WDRDA
ADDRESSES

~

AADO

r-

-

In a 4-bit slice with zero delay within the arithmetic
logic unit, a level-triggered memory with buffering to
prevent logic oscillation requires about 80 ns to make
the loop whereas the DM85S68 does it in 35 ns. With a
30 ns delay in the ALU, the two compared system
speeds are 110 ns and 65 ns, respectively.

-,....

---

DMB5S68

--

CP

-

--

A3

AD •

as
O~ ..,

... /I ADO _

I

W

AFOD
CONTROL
INPUTS

CP
NW
BFDD

r- R3

R3
DATA
INPUTS

~
RO

-

RO

r- BAD3

BAD3
WORDB
ADDRESSES

~

~

-

--

----

DM85S68
CP

-

A3
DATA
OUTPUT

~
AD

BO

as
00

_BADO _

BADO

--

rB3 •

W

r- B3

A=B

M

ALU
FUNCTION
SELECt INPUTS

so
SI

S2
S3

i

-I

Vee

r- R3

J-{

------

,
DM74181

1

---

-,....

--

...

A3

B3

Fntures

BO.

-Expandable

• Minimum package c.unt
-60 n. cyd. (typ)'

Truth Table
00 WE ClK

OS

l

X

X

Data From

l
X
X
X

..r

l
X

Output Store

X

Write Data

Dependent on State, of 00 and

H

Read Data

Data Stored in Addressed Location

l

Output Store

Hi·Z

H

OutJ?ut Disable

Hi·Z

H'
H

X
X
X

MODE

BO

AD

FIGURE 1. 4-BIT REGISTER ALU

l

DATA
OUTPUT

~

OUTPUTS
Las~

Addressed Location

OS

~ Proprietary

DM75/DM85S68

AC Test Circuit and Switching Time Waveforms

[i,QV

400

DI
OUTPUT

r: L 111l:ludes prob~

and jl!1 capal;ltance
All dIOdes are 1N3064

OM75S68!
OM85S68

READ CYCLE

WRITE CYCLE

ADDRESS
INPUT

ADDRESS

1.5V

[lATA

INPUT

1.5V

INPUT

1.5·V\,r---- - - - - - -

----.II?\~'AA-l

OUTPUTS _ _ _ _ _ _

..:s:-\\.r------·
_______

FIGURE 4. ADDRESS TO OUTPUT ACCESS TIME
OUTPUT
STORE
ADDRESS
INPUTS

WRllE

ENABLE

WRITE
CLOCK

1'------

,wl

OUTPUT
STORE

---'W--"H,~-I

OUTPUTS

FIGURE 2. CLOCK SET·UP AND HOLD TIME
FIGURE 5. OUTPUT STORE ACCESS, SET·UP AND HOLD TIME

OUTPUT
DISABLE

1.5V

l":r~~

15V)(----------

----.I .

O.5V

VO'--+-"l""".J
OUTPUT

iI

WAnE

CLOCK

15V

l~tOA_1

,--

OUTPUTS _ _ _ _ _ _ _ _ _ _ _' : , " - -

FIGURE 3. CLOCK TO OUTPUT ACCESS

FIGURE 6. OUTPUT DISABLE AND ENABLE TIME

Note: Input waveforms supplied by pulse generator having the following characteristics: V:::: 3.0V, tR $. 2.5 ns,
PRR

:S

1.0 MHz, and ZOUT = 50 MD.

I
3·85

~ Proprietary

OM75/0M8570,OM76/0M86L70
8-Bit Serial In/Parallel Out Shift Registers

General Description

Features

These 8-bit shift registers feature gated serial inputs and
an asynchronous clear. A low logic level at either input
inhibits entry of the new data, and re$ets the first
flip·flop to the low level at the next clock pulse, thus
providing complete control over incoming data. A high
logic level on either input enables the other input,
which will then determine the state of the firs't flip-flop.
Data at the serial inputs may be changed while the
clock is high or low, but only information meeting the
setup requirements will be entered. Clocking occurs on
the low-to·high level tran~ition of the clock input. All
inputs are diode-clamped to minimize transmission-line
effects.

•

Gated (enable/disable) serial inputs,

•

Fully buffered clock and serial inputs

•

Asynchronous clear

TYPE

TYPICAL

TYPICAL

CLOCK FREOUENCY

POWER DISSIPATION

36 MHz
14 MHz

185mW

70
L70

30mW

Connection Diagrams
OUTPUTS
CLEAR

DF
13

12

11

CLOCK

D5

10

14

<-

a.

A
SERIAL INPUTS

CLOCK

GND

13

12

111

D4

D3

D6

U2

10

-

-

Do

Dc

CLEAR

-

D7

UB

S.

OUTPUTS

7570(J), (W); 8570IJ), (N), (W)

76L70/86L70(W)

Truth Table

INPUTS

CLEAR

OUTPUTS

CLOCK

A

8

L

x

x

x

H

L

x

X

GAO

GBO

H

t

H

H

H

GAo

x

H
H

x

GA

OB

H
X

=
=:

High Level (steady state), L

=

Low Level (steady state)

Don't Care (any input, including transitions)

t = Transition from low to high level
0AO, 0BO, OHO = The level of {lA, OB, or 0H, respectively,
before the indicated steady·state input conditions were
established.
QAn. QGn = The level of -QA or QG before the most recent t
transition of the clock; indicates a one-bit shift.

3·86

01

~

DM75/DM8570.DM76/DM86L70

P rQprietary

Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted)
-DM76L/86L

DM75/85
CONDITIONS

PARAMETER

MIN
V'H

High Level Input Voltage

V'L

Low Level ',"put Voltage
Input Clamp Voltage
High Level Output Current
Vee'" Min, V 1H
V 1L

::::

VOL Low Level Output Voltage

Input Current at Maximum
Input Voltage

ICC

MAX
V
0.7

2V

High Le~ei Input Current

Supply Current

V

-200

~A

V

2.4

DM75,76l

8

2

DM85,86l

8

3.6

DM75,76l

0.2

0.4

V 1L

DM85,86l

0.2

0.4

0.3
0.4

Clear

1

0.2

Other

1

0.1

""

Max,

tOL

= Max

Vee

=

Vee

= Max, VI:::: 2.4V

Low Level Input Current

Short Circuit Output Current

N/A

-400
3.2

2.4

Max, VI"" S.5V

M -j------~'-------------~-----'1
DATA
INPUTS

'-------+-------H.-.------+----j,

>O-ir--------+-+----------j------'14
'14

L------+--JI!:--~~-------_+-..---

14 INPUTS
FOR MASK

PROGRAMMING
96

OUTPUTS

,,
I

~ .rr:::=\
NOTE:): IS A MASK·PROGRAMMABLE CONNECTION

3-95

FB ORF8

~

DM75/DM8575,76

Proprietary

Electrical Characteristics over recommended' operating free-air temperature range (unless otherwise noted)
DM75/85
PARAMETER

CONDITIONS

V IH

High Level Input Voltage

Vee=Min

Vil

Low Level I nput Voltage

Vee = Min

VI

Input Clamp Voltage

Vee = Min, I, = -12 mA

10H

High Level Output Current

High' Level Output Voltage

TVP(1)

MAX

2

V OH =5.5V
V OH

UNITS

75, 76
MIN

Vee = Min

0_8

V

-1.5

V

DM75/S575

-SOO

DM75/S576

100

DM75/S575

V ,H = 2V

V

2.4
V

V'L = O.SV

Low Level Output Current

VOL

Low Level Output Voltage

5.5

DM75/S576

IOH = Max
tOl

Vee = Min, V ,H = 2V
V'L = 0.8V, IOL = 12 mA

II

IJ-A

12

mA

0.4

V

Input Current at Maximum
Input Voltage

Vee = Max, V, = 5.5V

1

mA

IIH

High Level Input Current

Vee = Max, V, = 2.4V

40

IJ-A

III

Low Level Input Current

Vee = Max, V, = OAV

-1.0

mA

los

Short Circuit Output
Current

Icc

Supply Current

Vee = Max(21

DM75

-20

""55

DM85

-18

-55
110

Vee = Max

mA
mA

170

Notes
111 All typical values are at Vee == 5V and T A = 25u~.
121 Not more than one output should be shorted at a ~ime.

Switching Characteristics Vee = 5V, T A = 25°c
DM75/85
PARAMETER

FROM

CONDITIONS

TO

tPlH

Propagation Delay Time,
Low-to-H igh Level Output

tpHl

Propagation Delay Time,
High-to-Low Level Output

Data

Output

Data

Output

UNITS

75, 76
MIN

TVP

MAX

80

150

ns

100

150'

ns

C L = 50 pF, RL = 400Q

PLA Programming Information

PUNCHED CARDS

Information to program the PLA can be supplied in one
of two formats:

: (Used to determine whether outputs are
CARD
presented' in their true or inverted form, :If this. card
is not used it is assumed that all.eight outputs are true.)

,

1. Punched 80-column cards
2. The applicable section of this data sheet (manual
entry of information).

Col, '-6: DM7575
DM8576.

3·96

or

DM8575

or

DM7576

or

~ Proprietary

DM75/DM8575.76

PtA Programming Information (Continued)
Col. 7·9:

(Blank)

number, program number, etc.). However the exact
combination of characters must appear on all cards,
associated with that particular device. The purpose
of this section is to prevent mixing of cards.

Col 10·17: Output Data. Outputs are F8 (most
significant) to F1 (least significant). All eight outputs
must be specified.

Col. 76·78: (Blank)

A 'T' in an output location indicates that the
output is true.

Col. 79·80: Product Term Number 01 to 96. (All 96
cards need not be used.) Zero in column 79 may be
suppressed.

A 'C' in an output location indicates that the
output is complemented (inverted).
Col. 18·39: (Blank)

MANUAL ENTRY

Col. 40·75: This space is reserved for any unique
letters/numbers desired by the customer (special part
number, program number, etc.). However the exact
combination of characters must appear on all cards,
associated with that particular device.

The matrix·blank shown in this data sheet can be used in
lieu of punched cards to submit information for pro·
gramming the PLA.
INSTRUCTIONS

Col. 76·78: (Blank)

1. Circle the appropriate part number. I n the event a
catalog part is not being purchased, circle the closest
catalog part number. If an electrical screen is required
between the military and commercial devices, the
military designation should be circled.

Col. 79·80: 00
CARDS 2·97: Term Data Cards. Used to specify the
input and output conditions.
Col. 1·6: DM7575 or DM8575 or DM7576 or DM8576.

2. Customer should write the name of his company.

Col. 7·9: (Blank)

3. Enter the total number of unique product terms
found in all eight outputs. Repeated terms count
only once.

Col. 10·17: Output Connections. Outputs are F8,
(most significant) to F1 (least significant). This field
describes the outputs on which the product term
appears.

4. Output Inverter Option. Under the appropriate output
designation specify a 'T' when the high (true) level is
desired on the output for the given input conditions.
Specify a 'C' if the complement is needed.

A '+' in one of the eight output locations indicates
that the term described by the card is one of the
"OR" terms in that output.

5. Matrix

A '(blank)' in one of the eight output locations
indicates that the term described by the card is not
one of the "OR" terms in that output.

a. Input data. This block is used to describe what
comprises each of the 96 (maximum) product
terms. In each row, opposite the appropriate
Product Term number, information on the fourteen
Input Data locations is entered. Information must
be entered on all 14 inputs.

(Care should be exercised in punching this particular
field; since in mOst cases, unless a product term is
repeated, this field will appear as one '+' and seven
blanks.)

1).

Col. 18: (Blank)
Col. 19: = (equal sign)

Enter an "H" under the appropriate input
designation if that particular input appears in
the product term as a high (true) level.

Col. 21·34: Input Data. Inputs are 113 (most signifi·
cant) to 10 (least significant).

2). Enter an "L" under the appropriate input
designation if that particular input appears in
the product term as a low (complemented)
level.

An 'H' in one of the fourteen locations indicates
that input appears in the high state in the output
term.

3). Enter an "X" under the appropriate input
designation if that particular input does not
appear in the product term.

An 'L' in one of the fourteen input locations indio
cates that input appears in the low state in the
output term.

If less than 96 product terms are used leave all
spaces for the unused terms blank.

Col. 20: (Blank)

b. Output Data. This block is used to describe the
outputs on which the product terms appear.

An 'X' in one of the fourteen input locations
indicates that input does not appear in the output

1). Enter a '+' under the appropriate output
designation if the product term is contained
in that output's expression.

term.

Col. 35·39:

(Blan~)

Col. 40·75: This space is reserved for any unique
letter/number desired by the customer (special part

2). Leave a location blank if the product term is
not contained in that output's expression.

3·97

~ . Proprietary

DM75/DM8575.76

AC Test Circuit

14 INPUTS

5V

8 OUTPUTS

Switching Time Waveforms

.r::90~%:---~90~%""-- 3.0V

ANY INPUT - - - " l

NON-IN~~~~~~ _ _ _.....,_-'

FREGUmCY ~ 1 MHz
DUTY CYCLE ~ 50%
tr = tf = 10 ns

3-98

~ Proprietary

DM75/DM8575.76

Truth Table/Order Blank
1. PART NO. -

(DM7575, DM8575, DM7576, DM8576)

2. CUSTOMER IDENTIFICATlON-

3. TOTAL NO. OF UNIQUE PRODUCT TERMS USED-

(Repeated Terms Count Only Once)
4. OUTPUT INVERTER OPTION

5. MATRIX

2
3
4

5
6
7
8
9
10
11

12
13
14

15
16
17
18
19
20
21
22
23

24

25
26
27

28
29
30
31
32

33
34

35
36
37
38
39
40
41
42

3-99

~ Proprietary

DM75/DM8575.76

Truth Table/Order Blank (Continued)

PRODUCT~-r~~r-.--r-.I_N_PTUT~DrA_T~A__r-~-r~__~~~__r-~O~U~TTPU~T~O~A~T~A~r-~~
TERM
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57

58
59
60
61
62
63.
64
65
66
67
68
69
70
71

72
73
74
75

76
77

78
79
80

81

82
83
84
85
86
87
88
89
90
91
92
93
94
95
96

III'
3·100

~ Proprietary

DM75/DM85n
256-Bit Programmable Read Only Memories

GeneraLDe~ription

output for that bit is permanently programmed to provide a low logic level. Outputs never having been altered
may later be programmed to supply a low-level output.
Operation of the unit within the recommended operating
conditions will not alter the memory content.

The DM7577/DM8577 is a field-programmable, 256-bit,
read only memory organized as 32 words of 8 bits each.
This monolithic, high-speed, transistor-transistor-Iogic
(TTL) memory array is addressed in 5-bit binary with
full on-chip decoding_ An overriding memory-enable
input is provided which, when taken high, will inhibit
the function causing all eight outputs to remain high.
The organization is expandable to 1,856 words of n-bits
with no additional output bufferi ng.

The mask-programmable DM5488/DM7488 can be used
to replace the DM7577/DM8577 as they are functionally and mechanically identical.

The address of an 8-bit word is accomplished through
the buffered binary select inputs in coincidence with a
low logic level at the enable input. Where multiple
DM7571/DM8577 devices are used in a memory system,
the enable input allows easy decoding of additional
address bits.

Features

Data can be electronically programmed, as desired, at
any of the 256-bit locations of the DM7577/DM8577
in accordance with the programming procedure specified.
Prior to programming, the memory contains a high-Iogiclevel output condition at all 256 bit locations. The programming procedure open-circuits nichrome links which
results in a low-logic-level output at selected locations.
The procedure is irreversible and, once altered, the

•

Field programmabl,e for custom or prototype memories

•

Mask-programmable DM5488/DM7488 is a direct
replacement for the DM7577/DM8577

•
•

Typical access time
Organized as 32 words

•

Ideal for microprogramming and code converters

•

Open-collector outputs are easily expanded

•

Fully-decoded buffered inputs

•

Fully compatible with most TTL and DTL circuits

•

Pin compatible with SN74188A

Connection Diagram

ENABLE

v

G

.

SELECT

,
E

OUTPUT

\

YB

A

B

C

0

r16
15

13

14

12

11

10

9

2

1
Y1
\

Y2

4

3
Y3

.

V4

5
V5

OUTPUTS

7577(J}; 8577(J}, (N)

3-101

35 ns

of 8-bits each

7

6
VB

V7

,

J:

~

DM75/DM8577

Proprietary

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
DM75/85

PARAMETER

CONDITIONS

77
MIN

VIH

High Level Input Voltage

V il

Low Level Input Voltage

VI

Input Clamp Voltage

Vee

IOH

High Level Output Current

Vee

Low Level Output Current

VOL

Low Level Output Voltage

II

MAX

2

V'L
IOL

UNITS

TVP(1)

Input Voltage

I,

= -12 mA

= Min, V ,H = 2V
V OH = 5.5V

= 0.8V,

0.8

V

-1.5

V

100

pA

12

mA
V

= Min, V ,H = 2V
= 0.8V, 10L = 12 mA

0.4

V'L
Vee

=Max, V, = 5.5V·

1

mA

40

pA

Vee

Input Current at Maximum

= Min,

V

IIH

High Level Input Current

Vee

= Max, V, = 2.4V

III

Low Level Input Current

Vee

= Max, V, = O.4V

ICCH

Supply Current, Outputs High

Vee

= Max(2)

50

80.

mA

ICCl

Supply Current, Outputs Low

Vee

= Max(3)

82

1.10

mA

-1

mA

Notes
(1 ) All typical values are at Vee == 5V and T A = 25° C.
(2) ICCH is measured with all inputs at 4.5V, all outputs open.
(3) leel is measured with enable input grounded, aiL other inputs at 4.5V, and all outputs open, The typical value shown is for the worst-case
condition of all eight outputs low at one time. This condition may not be possible after the device has been programmed.

Switching Characteristics

vee

= 5V, T A = 25°C
DM75/85

PARAMETER

FROM

TO

77

CONDITIONS
MIN

tpLH

Propagation Delay Time,

Enable

Any

Enable

Any

UNITS

TVP

MAX

22

35

ns

15

35

ns

35

50

ns

. 35

50

ns

Low-to-H igh Level Output
tpHl

Propagation Delay Time,
High-to-Low Level Output

tPlH

Propagation Delay Time,

Select

Any

Select

Any

Low-to-High L,evel Output
tpHl

Propagation Delay Time,

= 30 pF to GND
RL1 = 400[2 to Vee
RL2 = 600[2 to GND

CL

.'.

High-to-Low Level Output
3-102

;

,

~ Proprietary

DM75/DM8577

Programming Procedure
1. Apply steady-state supply voltage (Vee ~ 5.0V,
GND ~ OV) and address the word to be programmed
with' specified input voltages.

The bit programmed may be verified by checking
the output for a low logic level after the enable input
reaches a low logic level.

2. Disable the outputs by applying a high logic level to
the enable input.

5. Repeat steps 2 through 4 for each output of this
address to be programmed as a low level.

3. Only one bit location is programmed at a time. Open
circuit all outputs except the one to be programmed
as a low logic level.

6. Advance to next address location and repeat steps
2 through 5.

4. Apply the specified programming pulse to the output
to be programmed, The recommended pulse width
is 1.0 ms.

Recommended Conditions for Programming

MIN

CONDITIONS

TYP

MAX

UNITS

5.0

5.5

V

0
2.4

0.5
5.0

V

Programming Pulse Amplitude

20

22

V

Programming Pulse Rise Time

1.0

5.0

10

~s

Programming Pulse Current limit

100

Programming Pulse Width

10

20

50

ms

Cas€ Temperature

25

75

°c

Supply Voltage, Vee
Input Voltage

I
I

Low Level
High Level

200

V

mA

AC Test Circuit and Switching Time Waveforms

5.DV

RU

FROM
OUTPUT
UNDER

TEST

-~
ENABLE

ME 2f,cr-

____'-~______~~~IaI________~~~______~

oniON 1

ME1::::[)ME2

Other options on .....DIY .neMe gatI:
ME1~

ME2~
oniON 3

OPTION 2

~-119

~

OM75/0M8597

Proprietary'

Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted)
DM75/85
PARAMETER

I

~

V IH

High Level Input Voltage

Vee

V IL

Low Level Input Voltage

Vee ~ Min

VI

Input Clamp Voltage

Vee

IOH

High Level Output Current

V OH

High Level Output Voltage

~

MIN

Low Level, Output Current

VOL

Low Level Output Voltage

Off State (High Impedance
State) Output Current

II

Input Current at Maximum
Input Voltage

~

Vee
V'L

IOIOFFI

V

Min, I,

~

-12 mA

Min, V ,H

~

~

Min, V ,H

~

2V

~

Max

Vee ~ Max

V

-1.5

V

-5.2

2V

0.8V, IOL

0.8

-2.0

J DM85
~

MAX

2.0

Min

V

II Vo~OAV

~

Max, V,

~

5.5V

16

mA

OA

V

-40

Vo~2AV

Vee

mA

2A

V'L ~ 0.8V, IOH ~ Max
IOL

TYP(1)

I DM75

Vee

UNITS

97

CONDITIONS

40
1.0

/lA

mA

IIH

High Level Input Current

V ee

~

Max, V,

~

2AV

40

/lA

IlL

Low Level Input Current

Vee

~

Max, V,

~

OAV

-1.0

mA

los

Short Circuit Output Current

Vee

~

Max(2)

-70

mA

Icc

Supply Current

Vee ~ Ma~

-20
75

110

mA

Notes
11 ) All typical values are at Vee:::: 5V and TA = 25°C.
(2) Not more than one output should be shorted at a time.

Switching Characteristics vee ~ 5V, T A ~ 25°C
DM75/85
PARAMETER

FROM

TO

CONDITIONS

tplH

Propagation Delay Time,

Address

Output

Address

Output

UNiTS

97
MIN

TYP

MAX

31

60

ns

39

60

ns

Low-ta·High Level Output
tpHL

Propagation Delay Time,
High-to-Low Level Output

tZH

Output Enable Time to

CL

~

50pF

RL

~

400n

Enable

Any

20

30

ns

Enable

Any

20

30

ns

Enable

Any

20

30

ns

20

30

ns

High Level
tZl

Output Enable Time to
Low Level

tHZ

Output Disable Time from
High Level

tlZ

Output Disable Time from

Enable

Any

CL

~

5 pF

RL

~

400n

I

Low Level

3-120

~ Proprietary

DM75/DM8597

Ordering Instructions
Programming instructions for the DM7597 or DM8597
are solicited in the form of a sequenced deck of 32
standard 80-column data cards providing the information requested under data card format, accompanied
by a properly sequenced listing of these cards, and the
supplementary ordering data. Upon receipt of these
items, a computer run ·will be made from the deck of
cards which will produce a complete truth table of
the requested part. This truth table, showing output
conditions for each of the 256 words, will be forwarded
to the purchaser as verification of the input data as
interpreted by the computer·automated design (CAD)
program. This single run also generates mask and test
program data; therefore, verification of the truth table
should be completed promptly.

20·23 Punch "H," "L," or "X" for the third set of
outputs.
24
Blank
25·28 Punch "H," "L," or "X" for the fourth set of
outputs.
29
Blank
30·33 Punch "H," "L," or "X" for the fifth set of
outputs.
34
Blank
35·38 Punch "H," "L," or "X" for the sixth set of
outputs.
39
Blank
40-43 Punch "H," "L," or "X" for the seventh set
of outputs.
44
Blank
45-48 Punch "H," "L," or "X" for the eighth set
of outputs.
49
Blank
50-51 Punch a right-justified integer representing the
current calendar day of the month.
52
Blank
53-55 Punch an alphabetic abbreviation representing
the current month.
56
Blank
57-58 Punch the last two digits of the current year.
59
Blank
60-61 Punch "DM"
62-65 Punch 7597 or 8597
66-70 Blank
71
Punch 1, 2 or 3 for memory enable option
desired (assumed 1 if not punched).

Each card in the data deck prepared by the purchaser
identifies the eight words specified and describes the
conditions at the four outputs for each of the eight
words. All addresses must have all outputs defined and
columns designated as "blank" must not be punched.
Cards should be punched according to the data card
format shown.

Supplementary Ordering Data
Submit the following information with the data cards:
a) Customer's name and address
b) Customer's purchase order number
c) Customer's drawing number

Data Card Format
Column

AC Test Circuit

1-3

Punch a right-justified integer representing the
binary input address (00·248) for the first set
of outputs described on the card.
4
Punch a "-" (minus sign)
5·7
Punch a right-justified integer representing the
binary input address (007-255) for the last set
of outputs described on the card.
8·9
Blank
10-13 Punch "H," "L," or "X" for bits four, three,
two and .one (outputs Y4, Y3, Y2, and Yl in
that order) for the first set of outputs specified
on the card. H = high level output, L = low level
output, X = output irrelevant.
Blank
14
15-18 Punch "H," "L," or "X" for the second set
of outputs.
19
Blank

5.0V

RL

OUTPUT

DM7597/
DM8597

I-

lI-

3-121

I~

,.....

t"

.,,.
-I-

lK

~,

-l-

~~

.::

~ Proprietary

DM75/DM8598
TRI-STATE 256-Bjt Read Only Memories

General Description
The DM7598/DM8598 is a mask-programmed 256-bit
read only memory, organized as 32, 8-bit words. A 5-bit
input code selects the appropriate word which then
appears on the eight outputs. An enable input overrides
the select inputs and blanks all outputs.

TRI-STATE elements, neither waveform integrity nor
optimum speed would be achieved. The low output
impedance of the DM7598/DM8598 provides gOOd capa·
citance drive capability and rapid transition from the
logical "0" to logical "1" level, thus assuring both. speed
and waveform integrity.

Although the DM7598/DM8598 can have its outputs
tied together for word-expansion, the outputs are not
open-collector, but rather the familiar totem-pole output
with the capability of being placed in a "third-state."
This unique TRI-STATE concept allows outputs to be
tied together and then connected to a common bus line.
Normal TTL outputs cannot be connected due to the
low-impedance logical "1" output current which one
device would have to sink from the other. If, however,
on all but one of the connected devices both the upper
and lower output transistors are turned "OFF," then the
one remaining device in the normal low impedance state
will have to supply to, or sink from, the other devices
only a small amount of leakage current.

It is possible to connect as many as 128 DM8598s to a
common bus line and still have adequate drive capability
to allow fan-out from the bus.

Features
•
•
•
•
•
•
•

While it is true that in a TTL system open-collector gates
could be used to perform the logic function of these

TRI-STATE outputs
Pin compatible with DM5488/DM7488
Organized as 32 8-bit words
Full internal ,decoding
26 ns typical access time
350 mW typical power dissipation
Designed for bus-organized systems

Connection and Logic Diagrams

SELECT

\

,-----~-----,A

ME

..

,

OUTPUTV8

1..v

1D

"

BINARV
SHEeT

""

I'-Oov-t-H-HH
..

o,;i>

-

E(l4}

1

Y1

Y2

Y3

Y4

V5

Y6

OUTPUTS

V)

ME

(lSI

"v
PROGRAMMING

7598IJ); 8598(Jl, IN)

NOT

SHOWN

3-122

OUTPUTS

~

DM75/DM8598

Proprietary

Electrical Characteristics over recommended operating free·air temperature range (unless otherwise noted)
DM75/85
PARAMETER

CONDITIONS

98
MIN

V 1H

High Level Input Voltage
Low Level Input Voltage

Vee = Min

VI

Input Clamp Voltage

Vee = Min, I, = -12 mA

10H

High Level Output Current

I

I
High Level Output Voltage

Low Level Output Current

VOL

Low Level Output Voltage

-1.5

V

-2.0
-5.2

mA

2A

V
mA

12
Vee = Min, V ,H = 2V

10(OFF) Off·State IHigh Impedance State)
Output Current
II

V

DM85

= Max

10H

V
0.8

DM75

Vee = Min, V ,H = 2V
V ,L = 0.8V,

10L

UNITS
MAX

2

Vee. = Min

V IL

V OH

TYP(1)

Input Current at Maximum Input
Voltage

OA

V ,L = 0.8V,

10L ,"

I

Vo = OAV

-40

Vee = Max

I

Vo = 2AV

40

12 mA

Vee = Min, V, = 5.5V

IIH

High Level Input Current

Vee = Max, V, = 2AV

IlL

Low Level I nput Current

Vee = Max, V,

lOS

Output Short Circuit Current

Vee = Max(2)

Icc

Supply Current

~

V

/lA

mA

1

OAV
-20

Vee = Max, Inputs

70

Grounded

25

/lA

-1.0

mA

-70

mA

99

mA

Notes
(1) AI! typical values are at Vee = 5V and T A ~ 25°C.
(2) Not more than one output should be shorted at a time.

Switching Characteristics Vee = 5V, T A = 25°C

PARAMETER

tpLH

tpHL

tZH

tZL

tHZ

tLZ

PARAMETER
CONDITIONS

Propagation Delay Time,

AccessTime from

Low to High Level Output

Address

Propagation Delay Time,

Access Time from

High to Low Level Output

Address

Output En'able Time to

Access Time from

High Level

Memory Enable

Output Enable Time to

Access Time from

Low Level

Memory Enable

DM85

DM75

UNITS

CONDITIONS
MIN

C,-

= 50 pF

RL

=400.11

Output Disable Time from

Disable Time from

High Level

Memory Enable

CL

~

Output Disable Time from

Disable Time from

RL

= 400.11

Low Level

Memory Enable
3·123

TYP

MAX

65

23

50

ns

29

65

29

50

ns

16

40

16

30

ns

20

40

20

30

ns

10

30

10

20

ns

22

45

22

40

ns

TYP

MAX

23

MIN

5.0 pF

~

DM75/0M8598

Proprietary

AC Test Circuit and Switching Time Waveforms

r----'

J.OV

BINARY
SELECT

Vee
TEST

I.5V

15V

"_J~~~

'PLH

VO"

POINT
R[

FROM

........

OUTPUT
UNDER
TEST

OUTPUT

1"

15V

15V

Voc~~----

~,

ME
l.Ok

1

'------

~,

30V~
..

1.5V

, 1.5V

I

OV

--I

~,

-,. 1,5V

~~

'll

I

OUTPUT

\

VOI--1-:

I-

VOH
OUTPUT

J

'" 1.5V

o.sv

---r1

\

'ZH

Cl includ~s proba and jig capacitance.
All diodes are lN3064.

I ~

.

-T

I

"'=

'[Z~

05V

~_1

O.!)V

0.5V

I'

t

I,

-T

-J 1HZ t----

Note: Input waveforms are supplied by pulse generators
having the following characteristics: tn.s;; 10 os, tS:OS, 10 os,
PRR S 1.0 MHz and lOUT z" 50H.

Truth Table
A special pattern has been generated for the DM7598/DM8598. The AA pattern provides a sine look up table. The 5-bit input
code linearly devides 90 0 into 32 equal segments. Each 8-bit output is therefore the sine of the angle applied.
EXAMPLE: Input 11010 means 26/32 of 90 0 , or about 73°. The corresponding output 1110100 indicates (112 + 1/4 + 1/8 +
1/16 + 1/64) or about 0.96, which is close to the sine of 73°. Rounding-off has not been employed, since without rounding-off,
it is possible to extend the accuracy with additional ROMs.
INPUTS
BINARY SELECT
WORD

OUTPUTS

ENABLE

E

D

C

B

A

ME

YB

Y7

Y6

Y5

Y4

Y3

Y2

0

L

L

L

L

L

L

L

L

L

L

L

L

L

Y1

L

1

L

L

L

L

H

L

L

L

L

L

H

H

L

L

2

L

L

L

H

L

L

L

l

L

H

H

L

L

H

3

L

L

L

H

H

L

L

L

H

L

L

H

L

H

4

L

L

H

L

L

L

L

L

H

H

L

L

L

H

5

L

L

H

L

H

L

L

L

H

H

H

H

H

L

6

L

H

H

L

L

L

H

L

L

H

L

H

L

7

l.
L

L

H

H

H

L

L

H

L

H

L

H

H

L

8

L

H

L

L

L

L

L

H

H

L

L

L

L

H
H

9

L

H

L

L

H

L

L

H

H

L

H

H

L

10

L

H

L

H

L

L

L

H

H

H

H

L

L

L

11

L

H

L

H

H

L

H

L

L

L

L

L

H

H

12

L

H

H

L

L

L

H

L

L

L

H

H

H

L

13

L

H

H

L

H

L

H

L

L

H

H

L

L

L

14

L

H

H

H

L

L

H

L

H

L

L

L

H

L

15

L

H

H

H

H

L

H

L

H

L

H

L

H

H

16

H

L

L

L

l

L

H

L

H

H

L

H

L

H

17

H

L

L

L

H

L

H

L

H

H

H

H

L

H

18

H

L

L

H

L

L

H

H

L

L

L

H

L

H
H

19

H

L

L

H

H

L

H

H

L

L

H

H

L

20

H

L

H

L

L

L

H

H

L

H

L

H

L

L

21

H

L

H

L

H

L

H,

H

L

H

H

L

H

H

22

H

L

H

H

L

L

H

H

H

L

L

L

L

H

23

H

L

H

H

H

L

H

H

H

L

L

H

H

H

24

H

H

L

L

L

L

H

H

H

L

H

H

L

L

25

H

H

L

L

H

L

H

H

H

H

L

L

L

H

L

26

H

H

L

H

L

L

H

H

H

H

L

H

L

27

H

H

L.

H

H

L

H

H

H

H

H

L

L

L

28

H

H

H

L

L

L

H

H

H

H

H

L

H

H
H

29

H

H

H

L

H

L

H

H

H

H

H

H

L

30

H

H

H

H

L

L

H

H

H

H

H

H

H

L

31

H

H

H

H

H

L

H

H

H

H

H

H

H

H

All

X

X

X

x

X

H

X ~ Don't Care

3-124

Hi-Z Hj·Z Hi·Z Hi-Z Hi-Z Hi-Z Hj·Z Hi-Z

~ Proprietary

DM75/DM8598

Truth Table/Order Blank

The output levels are not shown on the truth taule since the customer specifies the output condition he desires at each of the
eight outputs for each of the 32 WOf~S (256 bits). The customer does this by filling out the Truth Table on this data sheet,
and sending it in with his purchase order

INPUTS
OUTPUTS
BINARY SELECT
WORD

ENABLE

E

D

C

0

L

L

L

1

L

L

L

2

L

L

L

H

L

l.

3

L

L

L

H

H

L

B

A

ME

L

L

L

L

H

L

4

L

L

H

L

L

L

5

L

L

H

L

H

L

6

L

L

H

H

L

L

7

L

L

H

H

H

L

8
9

L

H

L

L

L

L

L

H

L

L

H

L

10

L

H

L

H

L

L

11

L

H

L

H

H

L

12

L

H

H

L

L

I.

13
14

L

H

H

L

H

L

L

H

H

H

L

L

15

L

H

H

H

H

L

16

H

L

L

L

I.

L

17

H

l.

L

L

H

L

18

H

l.

L

H

L

L

19

H

l

L

H

H

L
L

2.0

H

L

H

L

L

21

H

L

H

~

H

L

22

H

L

H

H

L

L

23

H

L

H

H

H

L

24

H.

H

L

L

L

L

25

H

H

L

L

H

L

26

H

H

L

H

L

L

27

H

H

L

H

H

L

28

H

H

H

L

L

L
L

29

H

H

H

L

H

30

H

H

H

H

L

L

31

H

H

H

H

H

L

AI!

X

X

X

X

X

H

YB

Yl

Y6

Y5

Y4

Y3

Y2

Y1

-

Hi-Z Hi-Z H,·Z H,·Z Hi-Z Hi-Z Hi-Z Hi-Z

x "" Don't Care
Notice: This sheet must be completed and signed by an authorized representative of the
customer's company before an order can be entered.

To be used by National only

Authorized Representative

Date

__________ Part Number
_ _ _ _._ _ _ _ S.O. Number

Company

Date Received
Desired Part

3·125

o

DM7598

o

DM8598

~ Proprietary

DM75/DM8598

Ordering Instructions
Programming instructions for the DM7598/DM85.98 are
solicited in the form of a'sequenced deck of 32 standard
80-column data cards providing the information
requested under "data card format," accompan ied by a
properly sequenc~d listing of these cards,and the supplementary ordering data. Upon receipt of these items, a
computer run will be made from the deck of cards
which will produce a complete ·functio·n table of the
requested part. This function table, showing output
conditions for each of the 32 words, will be forwarded
to the purchaser as verification of the input data as
-interpreted by the computer'automated design (CAD)
program. This single run also generates mask and test
program data; therefore, verification of the function
table should be completed promptly.
Each card in the data deck prepared by the purchaser
identifies the word specified and describes the levels at
the eight outputs for that word. All addresses must
have all outputs defined and columns _designated as
"blank" must not be punched, Cards should be punched
according to the data card format shown.

Col. 15: Punch "H" or "L" for butput V6.
CoL 16-19: Blank
Col. 20: Punch "H" or "L" for outp~t

Y'ft' .. ~.,.

Col. 21-24: Blank
Col. 25: Punch "H" or "L" for output V4.
Col. 26-29: Blank
(:01. 30: Punch "H" or "L" for output V3.

Col. 31-34: Blahk
Col. 35: Punch "H" or "L" for output V2.
Col. 36'-39: Blank

Supplementary Ordering Data

Col. 40: Punch "H" or "L" for output Y1.

Submit the following information with the data cards:

Col. 41-49: Blank

a)
h)

c)

Customer's name and address
Customer's purchase order number
Customer's drawing number

Col. 50-51: Punch a right-justified integer representing
the current calendar day of the month.
Col_ 52: Blank

The following information will be furnished to the
customer:
a)
National's part number
b) National's sales order number
c) Date received

Col. 53-55: Punch an alphabetic abbreviation representil)g the current month.
Col. 56: Blank

Data Card ForQ1at

Col. 57-58: Punch the last two digits of the current_
year.

Col. 1-2: Punch a ,right-justified integer representing
the positive-logic binary input .address (00-31) for the
word described on the card.

Col. 59: Blank
Col. 3-4: Blank
Col. 60-61: Punch "OM,"
Col. 5: Punch "H" or "L" for output V8. H ; highvoltage level output, L = low·voltage level output.

Col. 62-66: Punch

Col. 6-9: Blank
Col_ 10: Punch

"75~8fl

or "8598."

Col. 67-68:'Blank

"tt" or "V' for output V7.

Col. 11-14: Blank

Col.-69-S0: These columns may be used for any custO,mer information or identification_

3·126

~ Proprie~ry

DM75/DM8599
TRI-STATE 64-Bit Random Acc,ss Memories

General Description
The DM7599/DM8599 is a fully decoded 64-bit RAM
organized as 16 4-bit words.The memory is addressed
by applying a binary number to the four address inputs.
After addressing, information may be either written into
or read from the memory. To write, both the memory
enable and the write enable inputs must be in the
logical "0" state_ Information applied to the four
write inputs will then be written into the addressed
location_ To read information from the memory the
memory enable input must be in the logical· "0" state
and the write enable input in the logical "1" state.
Information will be read as the complement of what
was written into the memory _ When the memory enable
input is in the rogical "1" state, the outputs will go to
the high-impedance state. This allows up to 128
memories to be connected to a common bus line with-

out the use of pull-up resistors_ All memories except one
are gated into the high impedance state while the one
selected memory exhibits the normal low impedance
output characteristics of TTL_

Connection Diagram

Truth Table

A'

AI

I"

"

AJ
1J

"

04

OJ

S4

12

11

Features
•
•
•
•

TRI-STATE outputs
Same pin-out as DM5489/DM7489
Organized as 16, 4-bit words
Expandable to 2048, 4-bit words without additional
resistors (DM8599 only)
20 ns
• Typical access from chip enable
28 ns
• Typical access time

53

•

10

MEMORV
ENABLE

r--

0-

WRITE
ENABLE

OUTPUTS

OPERATION

L

L

Write

Hi-Z

L

H

Read

Complement' of Data

H

X

Hold

Stored in, Memory

1

Aft

,

•

3

ME

WE

01

••

,

6

5

Hi-Z

02

52

GNO

"

7599{JI; 8599{J), (N)

Logic Diagram

~AO
(.1)

AD

iio
AI

.

.2

AD

ii3

~Al

A' (15)

_

-

·At

ADDRESS
INPUTS

A'

AD
iiI
ii2
ii3

~A2
'2'

A3~:J
.

A)

.'

AD
AI
A2
A3

01 (41

02(6)

DATA
INPUTS

SENSE
OUTPUTS

DJ (101
04 (12)

Vec "U61
GND-II)

3-127

~

Proprietary

DM75/DM8599

Electrical Characteristics

over recommended opeiating free-air temp~rature range (unless otherwise noted)
DM75/85

PARAMETER

CONDITIONS

V,H

High Level Input Voltage

Vee =- Min

V,L

low Level input Voltage

Vee == Min

V,

Input Clamp Voltage

V'cc == Min,l, == -12 rnA

IOH

High Level Output Current

V OH

High Level Output Voltage

IOL

Low level Output Current
Low Level Output Voltage

IOIOFFI

V

I DM75
I DMS5
Vee

=

Min, V 1H

Input Current at Maximum

Input Voltage

10H

:=

2V

= Max

Vee:: Min, V ,H

:=

V'L = D.SV,

104

= 12 rnA

Vee =Max

I Vo -2:4V

2V

l Vo =O.4V

Off State (High Impedance
State) Output Current

I,

MAK

2

V'L = O.SV,

VOL

UNITS

99
TVP(l)

MIN

0.8

V

-1.5

V

-2.0
-5.2

rnA

2.4

V

12

rnA

0.4

V

-40

IJ,A

40

Vee = Max, V, = 5.5V

1

mA

40

IJ,A

-

-1.6

mA

-30

-70

mA

I'H

High Level Input Current

Vee = Max, V, = 2.4V

I'l

Low Level Input Current

Vee = Max, V, = O.4V

los

Short Circuit Output Current

Vee

Icc

Supply Current

Vee == Max

= Max(2)

80

mA

120

Notes:

= 5V and TA = 25°C.

(11

All typical val~es are at VCC

(2)

Not more than one output should be shorted at a time.

Switching Characteristics Vee

=

5V, TA

=

25°C
DM75/85

PARAMETER

FRQM

TO

-

CONDITIONS
MIN

tpLH

Propagation Delay Time,

Low-to-High Level Output
tPHl

Address

OutP~t

Address

Output

99

UNITS

TVP

MAX

27

45

ns

28

45

ns

20

ns

Propagation Delay Time,

High-to-Low Level Output

CL = 50;iF
RL = 400n

tZH

Output Enable Time to

High Level
tZl

tHOLD

ME

Output

19

30

ns

ME

Output

12

20

ns

21

3.0

ns

CL =.6 pF
RL

Output Disable Time from

ME

low leyel
tSETUP

14

Output Disable Time from

High Level
tlZ

Output

Output Enable Time to
Low Level

tHZ

I

ME

Setup Time

Hold Time

= 400n

'Output

,
Address

0

-17

Oat.

0

-1.5.

Address

5

Data

0

twp

Write Enable 'Pulse Width

tSR

Sense Recovery Time

4.0

.. . -:7
-14

ns

23
42

3-128

ns

,

ns
60

ns

~ Proprietary

DM75/DM8599

Typical Performance Curves
DELAY FROM ADDRESS
TO OUTPUT

DELAY FROM ENABLE TO
LOW IMPEDANCE STATE

DELAY FROM ENABLE TO
HIGH IMPEDANCE STATE

1 _I
Vee'" S.OV

70

35

]

50

~

40

-

~

30
20

:g

25

~

20

_

15

30

".....

~

10

:g

-~

I"

t pHL

- -:-

35

I

30

60

~

25

~

In

>

~ 20
-

c==

-

15

~V

~ ~ f-

10

10

-75 -50 -25

0

25

50

75 100 125

-75 -50 -25

Vee"' 5.IlV

~

25

-

r-LPL

-

r-tr

§: 20

~ 15
10

~

H

;;

0.2

75 10e 125

Y

~ :.--::

~ :;;.o

TEMPERATURE 1°C)

~5~C
25°C
'_55°C
(--

25°C

K-'

'"

~

20

12t"'" L'\ ~
I\.~

1.0

25

30

35

40

I

55"C-

"~ ~~

0.5

15

75100125

Vee" S.OV

\ _55°C

o
10

50

3.0

/

!)"

i'-.. V

25

LOGICAL "'" OUTPUT
VOL TAGE VS SOURCE
CURRENT

...... V ~

il

> 0.3

o
50

O

-;:. 0.4

I
25

-

12J C

0

TEMPERATURE (' C)

3.5

0.6
0.5

0.1
0

-75 -50 -25

0:

I
-75 -50 -25

75 100 125

0.7

".....

r-

50

Vee 5.0V

--

I

30

'"

25

LOGICAL "0" OUTPUT
VOLTAGE VS SINK
CURRENT

MINIMUM WRITE PULSE
WIDTH
35

0

TEMPERATURE ( C)

TEMPERATURE rC)

o

5

10

15

20

25

30

35

40

lOUT (rnA)

lOUT (rnA)

DELAY FROM ENABLE TO
OUTPUT VS LOAD CAPACITANCE

SENSE RECOVERY TIME
70

60
]: 50

!

tSR

w 40

'"

;::

30

g

30

20

20

10
10
-75 -50 -25

0

25

50

t--Hffiffit---t-H+ttIItI--t-ttttittl

~t;t;WI~t'H;L~I:::j+tm~
t--Hffiffit---t,t~"THrrffi~~~~
5 10

75 100 125

50 100

500

CL I,F)

TEMPERATURE 1°C)

Test Circuit
TEST CIRCUIT FOR DELAY VS LOAD CAPACITANCE

Note: In a typical application the output of the TRI·STATE
memories might be wired together and one would be switching

Met

to the low impedance state at the same time the circuit previously
selected would be switching back into the high impedance state.
The measurements of delay versus load capacitance were made
under conditions which simulate actual operating conditions in
an application. (See test circuit.)

ME2

ONE TTL LOAD

3-129

~ Proprietary

.OM75/8599

AC Test Circuit

5.OV

OUTPUT

OM15991
OM8599

Switching Time Waveforms
WRITE CYCLE

ME

WE--......,--"",",
- - - - - - - - -,----!-"",":"--...,+
ISR~---

OUTPUT _ _ _ _ _ _ _

tZL & tZH
MEMORY
-'L.
ENABLE - - - - " 1.5V

OUTPUTS
ACTUAL "0"
VOLTAGE

'LZ

MEMORY~15V
ENABLE·
~~
__._ _ _ _ _ _~_ _

~V

OUTPUTS

-"',.;-------~ 1.5V

----1-...1:,

'll

f--_

---+-"' I -

0.5V

+_...;:;---.L

ACTUAL "1" _ _ _
VOLTAGE

I -..;.------~

1.5V

'HZ ~

~1.5V---+__1

'ZH

Note: The pulse generator has the following characteristics: V = 3.0V,
'" 15 ns, tf 5.0 liS, f '" 500 kHz, duty cycle'" 50%, ZOUT = 50n, VI =-1.3V@25 C.

tr

J

0:

3·130

I

r

~1.5V

~ Proprietary

DM76/DM86L24
TRI-STATE Magnitude Comparators with A almost equal B

General Description

Features

These circuits are low power, 4-bit, magnitude comparators which provide both standard totem-pole TTL
outputs as well as TRI-STATE outputs. A comparison
of two, 4-bit words is performed, and the result indicated
by the four outputs: A> B, A < B, A == B, and A ~ B.
The A ~ B output is unique with this device, and is
enabled only when Word A is within one binary count
of Word B_ The comparison is expandable to any number,
without the need for external gates_ The maximum
speed method of cascading, and typical comparison
times are shown in Figures 1 and 2.

• TRI-STATE outputs
• May be cascaded to compare words of greater length
• Typical power dissipation
75 mW
• Four separate outputs
A==B
AB

Connection Diagram

Logic Diagram

OUTPUT ENABLES
EO

A~B

•

A almost equal to B (A ~ B) output permits lookahead and anticipation of a match (A == B)

OUTPUTS
A-B

A'B

12

11

13

AB

10
·256X4
LOW POWER
ROM

1 2

f

OUTPUT E02
ENABLE l.ED 1;.;114,;:1-4t++-...

A2

Al

AD

B3

WORDA

Bo

Bl

82

++_M+--.

GNO

WORO B

76L24/86L24(J), (N), (W)

Truth Table'
COMPARING INPUTS
(MSB)

(LSB)

ENABLE
INPUTS

A3B3

A2B2

Al Bl

AO BO

EOI

E02

A3>B3

A2>B2

Ai >81

AO>80

L

L

A382

x

A3= 83

A2< 82

x
x

A3= 83

A2 = B2

Al >81

A3= 63

A2= 82

A3 =63'

A2= 62

A3 = 83"
A3= 63

X
X

OUTPUTS
A=B

A-B

A>B

L

H

H

L

H

L

L

L

L

H

L

H

L

L

L

L

L

L

L

H

L

H

L

-L

L
L_

L

L

H

H

L

L

H

L

H

L-

L

L

L

H

L

L

H

X

Hi-Z

Hi-Z

Hi-Z

Hi-Z

X

H

Hi-Z

Hi-Z

Hi-Z'

Hi-Z

ABO

L.

A2 = 82

Al = 61

AO<80

A2= 82

Al = Bl

AO= 60

X
X

X
X

X
X

'Word A > Word 8 8y I
**Word A < Word B By 1
H = High Level, L = Low Level, X

= Don't Care
3-131

N

OM76/0M86L24

Proprietary'

Electrical

Charac~eristics over recommended operating free-air temperature range (unless otherwise noted)

DM76
CONDITIONS

PARAMETE'R

MIN
VIH

High Level Input Voltage

VIL

Low Level Input Voltage

VI

Input Clamp Voltage

10H

Hiill:' Level Output Current

V OH

High Level Output Voltage

TYP(l)

Vee =Min, V,H = 2V

Low Level Output Current
Low Level Output Voltage

Off

Vee = Min, V ,H = 2V

Stat~

(High Impedance State)

Vee = Max, V,H = 2V
V'L = 0.7V

II

Input Current at Maximum
Input Voltage

Vee = Max, V, = 5.5V

IIH

High Level Input Current

Vee = Max, V, = 2.4V

IlL

Low Level Input Current

Vee = Max, V, = 0.3V

los

Short Circuit Output Current

Ver:; = Max'(2)

Icc

Supply Current

Vee = Max, V, = OV

-.".4

MAX

"~':'\

V

0.7

0.7

V

-1.5

-1.5

V

-1.0

-1.0

rnA
V

2.0

3.6

mA

0.3

0.4

V

I Va = 0.3V

-40

--40

Va = 2.4V

40

40

100

100

p.A

10

10

p.A

-180

-180

p.A

-30

mA

20

mA

I

Output Current

UNITS

TYP(li

2.4

V'L = 0.7V, 10L = Max
1010FFI

MIN
2

2.4

V'L = 0.7V, 10H = -1.0 rnA
10L

L24
MAX

2

Vee =Min, I, = -12 rnA

VOL

DM86

L24

-6

-30
15

-6
15

20

p.A

Notes
All typical values are at VCC = 5V, TA = 25°C.
(21 Not more than one output should be shorted at a time.
(11

Switching Characteristics

Vee = 5V, TA = 25°C
DM76L/86L

PARAMETER

FROM

CONDITIONS

TO

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propa~ation

Delay Time,

High·to-Low Level Output

Data

Output

Data

Output

UNITS

L24

NIIN

TYP

MAX

86

130

ns

55

85 .

ns

'34

51

ns

47

70

ns

15

23

ns

57

86

ns

C L =50pF, RL =4 kQ
tZH

Output Enable Time to
High Level

tZL

Output Enable Time to
Low Level

tHZ

Output Drsable Time from
High Level

tLZ

C L =5pF, RL =4

Output Disable Time from
Low Level

3-132

kP-

~ Proprietary

OM76/0M86L24

Typical Applications
A15· AlJ

HIGH"'A>B

A>B

OUTPUTS { HIGH-'A3.B

A,"B

8

.<8

Lr-r-r~~~~~~ ~

IMSB)

OUTPUT
ENABLE

(lSB)

FIGURE 2. MAXIMUM SPEED EXPANSION (NOT SUITABLE FOR A - BI

COMPARE
CIRCUIT DELAY
(FIGURE 2)
1A BITS
5-7

NUMBER
OF CIRCUITS

1 DELAY

1

BITS

2 DELAYS

2

8-10 BITS

2 DELAYS

3

11-13 BITS

2 DELAYS

4

14-16 BITS

2 DELAYS

5

AC Test Circuit and Switching Time Waveforms

~L'~ ____

VCC=5.0V

3V

Z.OV

Rl

v, ,
I

1.0V

I

tpHL

OUTPUT---.....

i-i

I

----I

I

OUTPUT ENABLE

tZL Be tZH
OUTPUT
ENABLE

1.0V ----I~r--_;;;_;_

VOUTlIl-----t--,.--:---1.0V ----I-~I_-=r

Note: The pulse generator has the following characteristics: V ::= 3.0V, tr::: 15 ns, tf '" 5.0 ns, f '" 600 kHz, duty cycle'" 50%, ZOUT '" 50n. Vt ::: 1.3V@25°C.

3·133

ov

tplH
VOUT(1}

~ Proprietary

DM76/DMB6l25
TRI-STATE 7·Segment to BCD Decoder

General Description

Features

These circuits are low power converters which accept
7 -segment data on the inputs, and provide binary-coded
decima,1 (BCD) data on the outputs. An input control
line is also provided, in the event that the 7-segment
input data is presented in inverted form. The BCD
outputs are normally of the standard totem-pole TTL
type, however they may also be converted ,to highimpedance (TRI-STATE) types by applying a high logic
level to either of the two output enable pins.

• TRI-STATE outputs

Connection Diagram
OUTPUT ENABLE

CSZ
1J

2'
12

11

10

a

b

c

d

e

f

9

cn

CS 1

CS 2

z1

22

2'

D
I

H

H

H

H

H

H

L

H

L

L

L

L

L

L

L

H

H

L

L

L

L

H

L

L

L

L

L

H

C'

H

H

L

H

H

L

H

H

L

L

L

L

H

L

3
'-/

H

H

H

H

L

L

H

H

L

L

L

L

H

H

L

H

H

L

L

H

H

H

L

L

L

H

L

L

5

H

L

H

H

L

H

H

H

L

L

L

H

L

H

b
5
7

L

L

H

H

H

H

H

H

L

L

L

H

H

L

H

L

H

H

H

H

H

H

L

L

L

H

H

L

H

H

H

L

L

L

L

H

L

H

H

H

H

H

H

H

H

H

H

H

L

H

L

L

L

q
'3

H

H

H

L

L

H

H

H

l
l
L

L

B

L

H

L

L

H

H

H

H

H

L

H

H

H

L

l

H

L

L

H

BLANK

L

L

L

L

L

L

L

H

L

L

H

H

H

H

:I:

Logic Diagram

2°

L

L

L

H

H

H

L

H

L

L

H

H

L

H

E
R
P

H

L

L

H

H

H

H

H

L

L

H

H

H

L

H

H

H

'L

H

H

H

H

L

L

H

L

H

L'

H

H

L

L

H

H

H

H

L

L

H

L

H

H

-

L

L

L

L

L

L

H

H

L

L

H

H

L

L

n

L

L

L

L

L

L

H

L

L

L

L

L

L

L

H

L

L

H

H

H

H

L

L

L

L

L

L

H

L

76l25/B6L25(J), (N), (W)

CONl:RG~~

70 ns

DIGIT

,

INPUTS

INPUTS

• Typical p(opagation delay

OUTPUTS

2°

GNO

SE:~~:~

75 mW

Truth Table

~.~----~~--~~

CSl

• Typical power dissipation

,,

LJ

i'
'3

L

L

H

L

L

H

L

L

L

L

L

L

H

L

13)

L

L

L

L

H

H

L

L

L

L

L

L

H

H

:

i4J

'-I

H

L

L

H

H

L

L

L

L

L

L

H

L

l

e (5)

5

L

H

L

L

H

L

L

L

L

L

L

H

L

H

f (6)

b

H

H

L

L

L

L

L

L

L

L

L

H

H

L

.9(7)

E,

L

H

L

L

L

L

L

L

L

L

L

H

H

L

7
B
q

L

L

L

H

H

H

H

L

L

L

L

H

H

H

L

L

L

L

L

L

L

L

L

L

H

L

L

L

L

L

L

H

H

L

L

L

L

L

H

L

L

H

C 05)

INPUT

_'II~"~H-~H-~H--'
C51ENABlE {CSZ..:.II","....,f+-....,f+-....,f+--.

OUTPUT

BCD OUTPUTS

Segment Identification

9

L

L

L

L

H

L

L

L

L

L

H

L

L

H

BLANK

,

H

H

H

H

H

H

L

L

L

H

H

H

H

L

H

H

H

L

H "
L

L

H

L

L

L

H

H

L

H

E
R
P
-

L
L

H

H

L

L

L

L

L

L

L

H

H

H

L

L

L

H

L

L

L

L

L

L

H

L

H

L

l.

L

Ii

H

L

L

L

L

L

H

L

H

H

H

Ii

H

H

H

H

L
L

L

L

L

H

H

L

L

X
X

X
X

X
X

X
X

X
X

X
X

X
X

X
X

H

X

Z

Z

Z

Z

X

H

Z

Z

Z

Z

L

L

H

H

H

H

All Other "Input Combinations

3-134

~

OM76/0M86L25

Proprietary

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
DM76L

PARAMETER

CONDITIONS
MIN

VIH

High Level Input Voltage

VIL

Low Level I nput Voltage

VI

Input Clamp Voltage

IOH

High Level Output Current

VOH

High Level Output Voltage

TYP(1)

Vee = Min, V ,H = 2V

VOL

Low Level Output Voltage

II

V'L = 0.7V

Input Current at Maximum

I Vo =0.3V
1va =2.4V

Vee = Max, V, = 5.5V

Input Voltage

MAX
V
0.7

-1.5

-1.5

V

-1.0

-1.0

mA

V

V

2.4

V'L = 0.7V, 10L = Max
Vee = Max, V ,H = 2V

UNITS

TYP(1)

2

Vee = Min, V ,H = 2V

IOIOFFI Off State (High Impedance State)
Output Current

MIN

0.7

2.4

V'L = 0.7V, 10H = -1.0 mA
Low Level Output Current

L25
MAX

2

Vce = Min, I, = -12 mA

IOL

DM86L

L25

2.0

3.6

mA

0.3

0.4

V

-40

-40

40

40

100

100

/lA
/lA

J1A

IIH

High Level I nput Current

Vee = Max, V, = 2.4V

10

10

IlL

Low Level Input Current

Vee = Max, V, = 0.3V

-180

-180

/lA

los

Short Circuit Output Current

Vee = Max(2)

-30

mA

Icc

Supply Current

20

mA

-6

• Vee = Max, V I = OV

-30
15

-6
15

20

Notes
All typical values are at Vee'" 5V, T A"" 25°C.
(21 Not more than one output should be shorted at a time.
(11

Switching Characteristics

Vee = 5V,

TA

= 25°C
DM76L{86L

PARAMETER

FROM

TO

CONDITIONS

L25
MIN

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tZH

Output Enable Time to

Data

Output

Data

Output

130

ns

55

85

ns

34

51

ns

47

70

ns

15

23

ns

57

86

ns

Output Disable Time from
High Level

tLZ

86

Output Enable Time to
Low Level

tHZ

MAX

C L = 50 pF, RL = 4 kU

High Level
tZL

UNITS

TYP

Output Disable Time from

C L = 5 pF, RL = 4 kU

Low Level

3-135

~ Proprietary

DM76/DM86L25

AC Test Circuit

Vee = 5.0V

OM76l25/
OM86l25
All diodes
are lN914

Switching Time Waveforms

~1~~=_-.3V
2.0V

2.0V

Vt

1
I

WORO
INPUT

I

--I

tPHl I -

OUTPUT---.......\

1.0V

r"'' "'

\.. _ _ _- ' _ _ _J.

- - VOUTlL)

OUTPUT
ENABLE

OUTPUT
ENABLE

1.0V

OV

tplH \ - -

~

-----C-j----,-'--

1.0V

-----+----+-..._-,.__
O.5V

VOUTll)----+-'-..:...-----

VOUTll)------t-I~--_:_;,

VOUTlH)----f-----:..._-:-----

VOUTlH)

LOV ----+-'-f---=T

------i-.. .

-----'L

~ 1.0V ~----_+_--+-,-'"--

Note: The pulse genenltor has the following characteristics: V '" 3.0V, tr "" 15 liS, tf '" 5.0 n5, f '" 500 kHz,
duty cycle =: 50%, ZOUT = 50n, Vt '" f.3V @ 25~C.

3·136

~ Proprietary

DM76/DM86L75,L76
Presettable Decade/Binary Counters

General Description
These synchronous, presettable counters are true tenthpower versions of the popular DM54160A/DM74160A,
DM54161A/DM74161A,
DM9310,
and
DM9316
counters. They feature an internal carry/look ahead for
high-speed cascading, and trigger on the positive-going
transition of the clock pulse. The counters are fully
programmable; and, since presetting is synchronous,
applying a low logic level to the load input disables
the counter and forces the outputs to agree with the
setup data after the next clock pulse,. regardless of the
levels of the enable inputs. Low-to·high transitions at
the load inputs are acceptable, regardless of the logic
levels on the clock or enable inputs. The clear (reset)
function is asynchronous, and a low level applied to
the clear input sets all four outputs low regardless of
the levels on the clock, load, or enable inputs. In
high-speed cascading arrangements, both count·enable
inputs (p, T) must be high to count, and input T is fed

forward toenable the ripple carry output. This high·level
overflow ripple carry pulse can be used to enable
successive stages. High·to·low level transitions at the P
or T enable inputs are permitted, regardless of the
logic level on the clock.

Features
•

Low power versions popular counters
DM76L75/DM86L75 = DM54160A/DM74160A,
DM9310 ~ decade counter
DM76L76/DM86L76 = DM54161A/DM74161A,
DM9316 ~ binary counter
• Internal look-ahead for fast cascading
• Counters are fully synchronous and presettable
• Typical power dissipation
33 mW .

Connection Diagram

OUTPUTS

TC

Vrcc
16

OUTPUT

00

15

02

CEl

Q3

11

13

14

11

PE

10

p-

1

2

CLEAR

CLOCK

3
PO

PI

P2

P3

''----v---~'

DATA INPUTS

76L75/86L75(J), (N). (WI;
76L76/86l76(JI, (N), (WI

3-137

CEP

~

DM76/DM86L75,L76

Proprietary

Electrical Characteristics

over recommended operating free-air t~mperature range (unless otherwise noted)

PARAMETER

CONDITIONS
MIN

VIH

High level Input Voltage

VIL

low level Input Voltage

10H

High Level Output Current

VOH

High level Output Voltage

10L

Low Level Output Cu'rrent
Low Level Output Voltage

Vce = Min, V ,H = 2V

Input Current at Maximum
I nput Voltage

IIH

IlL

High Level I nput Current

Low Level Input Current

Vee

=

2.4

Vee = Max, V,

Vee

MAX

MIN

UNITS

TYP(1)

MAX

2

V

0.7

0.7

-200

-200
2.4

3.1

=

Vee ""Max

Icc

Supply Current

Vee -':: Max

0.2

= Max

2.4V

= Max, V, = 0.3V

Short Circuit Output Current

Notes
All typical values are at VCC

iv

Max, V, =5.5V

los

( 1)

TYP(l)

3.1

0.2

0.3

3.6

mA

0.4

V

CET Input

200

200

Others

100

100

CET Input

20

20

Others

10

10

CET Input

-360

-360

Others

-180

-180

-3

-9
6.5

-15

-9

-3

6.5

9

V
MA
V

2.0
Ve.e = Min, V ,H =
V'L = 0.7V, IOL

II

DM86l
L75, l76

2

V'L = 0.7V, IOH = -200MA

VOL

DM76l
l75,l76

MA

!J.A

!J.A

-15

mA

9

mA

= 5V, TA = 25'C.

Switching Characteristics V cc =5V,T A =25°C
DM76l/86L
PARAMETER

FROM

CONDITIONS

TO

fMAX

Maximum Clock Frequency

tpLH

Pro.pagation Delay Time,
low·to·High level Output

tPHL

Propagation Delay Time,
H igh·to-law level Output

tpLH

Propagation Delay Time,
low-to-High level Output

tPHL

Propagation Delay Time,
High-to-low level Output

tpLH

Propagation Delay Time,
law-to-H igh level Output

tpHL

Propagation Delay Time,

High·ta-low Level Output

UNITS

l75, l76
MIN
6

TYP

MAX
MHz

13

Clock

Q Output

45

75

ns

Clock

Q Output

65

110

ns

Clock

TC Output

70

115

ns

Clock

TC Output

85

140

ns

CET

TC Output

35

60

ns

CET

TC Output

35

60

ns

C L =50pF, RL =4kH

tW(CLOCKI

Minimum Pulse Width

60

25

ns

tW!RESETI

Minimum Pulse Width

80

30

ns

tSETUP

Setup Time

CE

65

40

tHOLD

Hold Time

P Inputs

30

15

Parallel Entry

65

40

CE

80

50

P Inputs

30

15

Parallel Entry

65

40

3·138

ns

ns

~ Proprietary

DM76/DM86L75.L76

Logic Diagrams

76L75/86L75 (DECADE)

PO

P1

P2

~~19)~t>~jfl~3)::::::::::~-----rtl~4)::::::::::~~---rtl~5)::::::::::::~--~
o

n

r+-+--..q,cp

rl--+----~

I'r)__________- ,

o

n

r+-+--..q,cp

r+-+--..q,cp

cp

114)
aD

P3

113)

(11)

112)
02

G1

03

76L76/86L76 (BINARY)

~19)

PI

PO

P3

P2
(5)

14)

(3)

I')

a

a

r+-+---q,cp

r+-t---4cp

r+-+-------oI> cP

a

r+-+---of> cp

R CD 0

114)
aD

113)

al

Vee" (16)

GND" 18)

3-139

112)
a2

(11)

03

~

Proprietary

DM7618678 ,79
7 by 9 Character Generators

General Description

Features

The DM7678/8678 and DM7679/DM8679 are bipolar
character generators. A maximum of 64 characters can
be displayed in a 7X9 dot matrix. Shifted characters
can be generated by the on-chip subtractor. On·chip
line counter and parallel·in-serial·out shift register reduce
package pin-out.

•

TRI-STATE outputs

•

On-chip input latches

•
•
•
•
•

On-chip line counter

--

The clear input and the load input are active low. Load
is. synchronous with the Dot Rate Clock. Both the line
rate clock and the dot rate clock are positive triggered.
When the strobe input receives a low signal, the character
address will be held at the inputs.

Connection Diagram

On-chip shift register
Serial output
20 MHz typical clock rate
Shifted characters

Character Display Example

.

SELECT

T

f

16

A4

AS

A6

A7

\

DOT
CLOCK

[jj

0

DOT RATE CLOCK (SERIAL OUTPUTI _
15

14

13

12

11

9

10

LINE
COUNTER
CLOCK

0
1
2

.
3

4

6

1

a

ClOCK

K
INPUT
A

NC

GNU

/13

14

12

/10

11

8

9

19}

OB

--0
~

18}
Oe

--0>

1

2

3

INPUT
B

ROlli

ROI2}

14

15

NC

16

NC

Vee

17

(11)

00

NC

76L93/86L93IJ}, IN}, (W)

Truth Tables
COUNT SEQUENCE TABLE
OUTPUT

COUNT

RESET/COUNT TRUTH TABLE
RESET INPUTS

OUTPUT

ROil}

RO(2)

QD

H

H

L

L

X

COUNT

X

L

COUNT

QC

QB

QA

L

L

L

3-142

QA

Qo

Dc

QB

0

L

L

L

L

1

L

L

L

H

2

L

L

H

L

3

L

L

H

H

4

L

H

L

L

5

L

H

L

H

6

L

H

H

L

7

L

H

H

H

8

H

L

L

L

9

H

L

L.

H

10

H

L

H

L

11

H

L

H

H

12

H

H

L

L

13

H

H

L

H

14

H

H

H

L

15

H

H

H

H

~

Proprietary

Electrical Characteristics

DM76/DM86L93
over recommended operating free-air temperature range (unless otherwise noted)
DM76L

PARAMETER

CONDITIONS
MIN

VIH

High Level Input Voltage

V IL

Low Level Input Voltage

10H

High Level Output Current

V OH

High Level Output Voltage

10L

Low Level Output Current
Low Level Output Voltage

Vce

=
=

Min, V'H

=

2V

O.7V, 10H

=

-200iJ.A

=

Min, V'H

=

2V

=

0.7V, 10L

=

Max

Vee

=

Max, V,

=

5.5V

High Level I nput Current
Vee

=

Max, V,

=

2.4V

Low Level I nput Current

IlL

MIN

TYP(1)

Vee

= Max,

los

Short Circuit Output Current

Vee =Max

ICC

Supply Current

Vee

V,'

= 0.3V

UNITS
MAX
V

2

2.4

0.7

0.7

V

-200

-200

iJ.A

2.8

0.15

Input Current at Maximum Input Voltage

IIH

L93
MAX

2.4

0.2

0.3

V

2.8

2.0
Vee
V'L

II

TYPll)

2

V'L

VOL

DM86L

L93

3.6

rnA

0.4

V

Reset

100

100

A Input

200

200

B Input

200

200

Reset

10

10

A Input

20

20

B Input

20

20

Reset

-180

-180

A Input

-360

-360

B Input

-360

-360

-3

-9

= Max(2)

-15

-3

-9

iJ.A

iJ.A

iJ.A

-15

rnA

5.5

5.5

rnA

Notes
All typical values are at Vee::: 5V, TA = 25°C.
(2) ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5V, and all other inputs grounded.
(1)

Switching Characteristics vee = 5V,

TA

= 25°C
DM76L186L

PARAMETER

f MAX

Maximum Clock Frequency

tpLH

Propagation Delay Time,

Low·to-High Level Output
tpHL

Propagation Delay Time,
High-to·Low Level Output

FROM

A

CONDITIONS

TO

TYP

6

15

QD
CL

A

L93
MIN

= 50 pF,

RL

=

UNITS
MAX
MHz

210

400

ns

230

400

ns

4 kSl

Qo

tw

Pulse Width (All Inputs)

200

ns

tSETUP

Reset I nactive State Setup Time

200

ns

3·143

~ Proprietary

- DM76/DM86 L97
TRI-STATE 1024-Bit Read Only Memories,

General Description

Feat.ures

The DM76L97/DM86L97 is a custom-programmed Read
Only Memory organized as 256 four-bit words. Selection'
of the proper word is accomplished through the eight
select inputs.
.

•

Full te'lth-power technology

• ,Pin compatible with SN54187/SN74187
• Typical power dissipation

Two overriding memory enable inputs are provided
which when mask-programmed in one of the three
options described 'will cause all four outputs to read
either the normal memory contents or go to the high
impedance .state.

• Typical access ti me
• Custom-programmed memory enable inputs

INPUT

H

Truth Table

ENABLES

SELECT

70 ns

• TRI-STATE outputs

Connection Diagram

Vee

75 mW

DATA OU1PUTS

•,

ME2

MEl

YI

13

V2

12

Y3

II

Y4

10
OPTION

MEl

ME2

1

L

L

H

X

High Itnpedance

X

H

High Impedance

,,

2

3

x

= Don't

H

H

Normal

l

X

High Impedance

X

L

High Impedance

H

L

Normal

X

H

High Impedance

L

\ X

High I mpedanc..f

Care

GNO

A

SELECT INPUTS

76L97/86L97(J), (N), (WI '

Logic Diagram

H (15)
G 1,')

F (2)

1024-BIT MEMORY CEll

I OF 32
DECODER

32 BY32
MEMORY MATRIX

(3)
SELECT
INPUTS

(4)

'c I~)

!

5)

MEl (13)
ENABLES

{

/1114~)---o-AO

~AO
15)

AI

~

ADDRESS
INPUTS

~~
A2

A3

AI

AD

AI

.2
~I

A3

A2 (l4).....

rC>o-A2

~A2
lJI
~

,A3

A3

A3

14)
01

02 (6)
DATA

INPUTS

{lO)

03

d.

(12)

13)

WE
Vee" (16)
GNO" (81

ME

12)

3-148

Hi-Z

~

DM76/DM86L99

Proprietary

Electrical Characteristics over recommended operating free-air temperature range lunless otherwise noted)
DM76L1B6L
PARAMETER

CONDITIONS

- -

--

V'L

Low Level Input Voltage

Vcc""Min

V,

Input Clamp Voltage

Vee =- Min, II -- -12 rnA

10H

High Level Output Current

V OH

High Level Output Voltage

10L

low Level Output Current

VOL

IO(OFF)

Vee

Low Level Output Voltage

Min, IOH

V
0.7

=

-·1.0 rnA

V

-1.0

rnA
V

2.4
2.0

DM86L

3.6

Vee =- Min

DM76L

0.3

IOL "" Max

DM86L

0.4

Vee'" Max

Vo =0.3V

-40

Vo = 2.4V

40

Input Current at Maximum

Vee

Input Voitage

:=

Max, VI = 5.5V

I'H

HIgh level Input Current

Vee == Max, VI == 2.4V

"L

Low Level Input Current

Vee

los

Short Circuit Output

Max, VI

O.3V
-6

Vee = Maxl2)

Current
Supply Current

ICC

=

V

--1.5

DM76L

Off State {High Impedance

State} Output Current
I,

-=

MAX

2

Vee

="

TYPll)

~---------

Min

High Level Input Voltage

V'H

UNITS

L99
MIN

V

/lA

100

/lA

10

/lA

-180

/lA

-30

rnA.

19

mA

15

Vee::: Max

rnA

Notes

11 )

Vee = 5V, T A = 25°C.
Not more than one output should be shorted at a time.

All typical values are at

(2)

Switching Characteristics

Vcc=5V,TA~25°C
DM76li86L

PARAMETER

FROM

TO

-.
tplH

Propagation Delay Time,
Low~to·Hjgh

tpHl

Level Output

Propagation Delay Time,
High-to-Low Level Output

tEN

Output Disable Ti me
from Write Enable

UNITS

199

CONDITIONS
MIN

TYP

MAX

Address

Output

51

120

ns

Address

Output

77

150

ns

WE

Output

73

110

ns

C L = 50 pF, RL = 4 ki1
tSR

Sense Recovery Time
fror1'l Write Enable

tZH

Output Enable Time
to High Level

tZL

Output Enable Time
to Low Level

tHZ

Output Disable Time
from High Level

WE

Output

110

165

ns

ME

Output

30

50

ns

ME

Output

29

43

ns

ME

Output

18

27

ns

37

56

ns

Cl. = 5 pF, RL = 4 ki1
tLz

I Output Disable Time
from Low Level

tSETUP

tHQLD

Setup Time

Hold Time

Output

Data

0

Address

0

ME

0

Data

0
0
0

Address
ME
twp

ME

Write Enable Pulse Width

50

ns

ns

30

ns

~ Proprietary

DM76/DM86l99

AC Test Circuit
~

Vee

5.nv

OUTPUT

DM76L99!
DM86L99

Switching Time Waveforms
WRITE CYCLE

lE.. r 'l1\

ADDRESS INPUT1 'PHL

v,

v,

,. - - -- - - - - - ---,I--~-! ---_.

, - --- - -- - -- --.1.,--m

___ ,",

ME

I nv

nv

~_'_PL.-J:~:::::::

WE------!---.... ,

DUTPUT----.\\..,_ _ _ _ _

t
ItfNi--

OUTPUT _ _ _ _ _ _ _ ....

~

J

'k

I~----

I i-'SR

MEMORY ENABLE

'ZL & tZH

'LZ & 'HZ
MEMORY
ENABLE

MEMDRY~V'
ENABLE

J

.- . tLl Ir":-:_0°1..l..5V---VOUT(L)

---+--'-----r'

Vo UT(H)

---+--...c--..-1
I

~~V.;.,_ _ _ _ _ __

~ tll h--

1.3V---t-r-~L.Jff5---V_ _

'1.3V

d--4ir
-.-

VOUTlL)

--tf-----VOUTlH)

1.3V

~----~1.3V

n.5V

r-----

. 'ZH

Note: The plltse generator has the following characteristics: V'" 3.0V tr ~ 15 liS,
tf"" 5.0 ns, f =: 500 kHz, duty cvcle ::: 50%, Zo ur '" 50£1, Vt ::: 1.3V @25"C.
I

3-150

f---

~ Proprietary

DM78/DM8853
Dual Retriggerable Resettable One Shots

General Description

Features

The DM7853/DM8853 is a dual, retriggerable, resettable
monostable multivibrator similar to the DM9602/
DM8602 but with a unique input triggering logic.

•

72 ns to

•

Retriggerable 0 to 100% duty cycle

This device has two trigger inputs-a standard input and
a delayed input-which are Exclusive OR'ed together.
In the dual·edge triggering mode, the two inputs are tied
together. On either a positive or negative transition the
Exciusive·OR logic is satisfied for a length of time equal
to the delay on the delayed input-approximately 15
ns-thus triggering or retriggering the one·shot.

= output width

range

• TTL input gating-leading AND/OR trailing edge
triggering
•
•

Complementary TTL outputs
Pulse width compensated for Vee and temperature
variations

Once fired, the accuracy and performance of the
DM7853/DM8853 is identical to that of the DM9602/
DM8602.

•

Connection Diagram

Resettable

Logic Diagrams

14

15

Dtt l!t)(41
11

(51

(71

(31

"Pins for external timing
(91

7853/8853(JI, (N), (W)

(131
*A non-inverting buffer with delay

Truth Tables

TRIGGERING TRUTH TABLE
Dt

CD

OPERATION

L

H

Trigger

H~L

H

Trigger

H~L

H

H

Trigger

L

L~H

H

Trigger

H~L

Same as t

H

Trigger

H

Same as t

H

Trigger

X

L

Reset

t
L~

H

H

L~

X

LOADING RULES

INPUTS
3.4,5,11.12.13

OUTPUTS
6,7.9.10

3-151

LOAD
HIGH

I LOW

1 u.L.11 U.L.

DRIVE FACTOR
HIGH

I LOW

16U·L.ISU.L.

~~

DM78/DM8853

Proprietary

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
DM78
CONDITIONSl21

PARAMETER

MIN
V,H

High Level Input Voltage

V,l

Low Level Input Voltage

V,

Input Clamp Voltage

10H

High Level Output Current

VO H

High Level Output Voltage

Low Level Output Current
Low Level Output Voltage

=:

Min,

'I

=>-12 rnA

Vee == Min, V 1H == 2V
=

a.BV,

=;

Min~ V 1H

2V

""

Input Current at Maximum Input Voltage

Vee

High Level Input Current

Vee == Max, VI'''''4.5V

I,l

Low Level Input Current

0=

Vee == Max

Supply Current

Curr~nt

Vee

-1.5
-800

2A

0.2

Vee

=-

I VI

-1.1

-1.6

== O.45V

Max, V OUT

"

55

==

mA

OA

V
mA

10

60

!1A

-'1.0

-1.6

'-25

1.0VI31

16

1

1

= OAV

V
!iA
V

0.2

60

V

3.4

OA

10

Vee == Max

Notes
(11 All typical values are at

-1.5
-800

Max, VI == 5.5V

I V,

MAX
V

16
Vee

I'H

Short Circuit Output

UNITS

TYPlll

0.8

3.3

2A

== -8OO.uA(3)

'OH

I,

lOS

MIN
2

V'L " 0.8V. 10L = 16 mAI31

Icc

MAX

0.8

V 1L

VOL

53

TYPOI

2

Vee

10l

DM88

53

55

72

mA

-35

mA

72

mA

5V, T A =: 25°C.

Vee

(2)

Unless otherwise noted, 10 kSl resistor placed between RX and

(3)

Ground Pin 1 1151 for VOL on Pin 7 (9). or for VOH on Pin 6 (10), or for lOS on Pin 6 (101; also. apply momentary ground to Pin 4 (12).
Open Pin 11151 for 'VOL on Pin 6 (10), or for VOH on Pin 7 191, or for loson Pin 7 (9).
.

Switching Characteristics vee

for all tests.

~ 5V, T A ~ 25°C
DM78
FRDM

PARAMETER

CONDITIONS

TO

tPHL

tpLH

I
tpHL

Propagation Delay Time,

Standard Trigger

Low-to-High Level Output

Input

Propagation Delay Time,

Standard Trigger

High·to-Low Level Output

Input

Propagation Delay Time,

Delayed Trigger

Low-to-High Level Output

Input

Propagation Delay Time,

Delayed Trigger

High-to-Low Level Output
tWfMINl

Minimum Possible Output Pulse
.

fT

53

UNITS

TYP

MAX MIN

TYP

MAX

Q

25

35

25

40

ns

Q

29

43

29

48

ns

40

53

40

58

ns

44

61

44

66

ns

72

90

72

100

78

100

78

110

3A2

3.76

MIN
tpLH

DM88

53

CL = 15pF.Rx "5kr/

Q

ex" 0

Q

Input

Q

tw

Pulse Width Tolerance

ex =1000pF.Rx =10kfl 3.08

eSTRAY

Maximum Allowable Wiring Capacitance

Pins 121 and 1141 to GND

Rx

Timing Resistor

5

3-152

3.08

50
25

5

3.42

ns

3.76

!is

50

pF

5Q

kfl

~. Proprietary

DM78/DM8853

Typical Performance Characteristics
OUTPUT PULSE WIOTH VS
TIMING RESISTANCE AND
CAPACITANCE FOR

<

Cx

103 pF

10'

~x ,1~

I

Z

:;

kn-;: t7'7

+t!t~x ~ 20 kl! /' .....:

10 3

IR~~30kS2

~Y

Rx -50kSl

~
w

"

>- .....

~

>-

">"0

I-'"

--r-

10'

....

~

::Tlkrr
I III

10
1,0

Cx _10 3pF
t'" 0.31

RxCx

10

(1 +

1/Rxl

10'

10 3

ex - TIMING CAPACITANCE (pF)

Switching Circuit
Cx
RX

~CC

Va
VIN

-::-

va
-::-

-::-

-::-

Switching Time Waveforms

VIN_n_,SV_ __
INPUT PULSES
f"'- 100 kHz
AMP,3:0V
WIDTH :;:- 40 ns
t r '"

3·153

tf

~ 10 ns

~ Proprietary

OM78/0M8875A.75B
TRI-STATE 4-Bit Parallel Binary Multipliers

General Description
These circuits are capable of multiplying together two
4-bit binary numbers when,used together in pairs. The
DM7875A/8875A provides the most significant four
bits, and the DM7875B/8875B provides the least signifi·
cant four bits. Since the largest number that can be
obtained· by multiplying two 4-bit numbers is 225
(15 x 151, the eight output pins (four from each
packagel are sufficient to produce this number. Both
the multiplier and the multiplicand must be connected
to the eight input pins of each device. These devices are
pin compatible with the SN54284/74284, and SN542851
74285; but have the advantage that these circuits pro·
vide either standard totem-pole TTL or TRI-STATE

Connection Diagram

STROBE

I"

52

15

•
•

Pin compatible replacements for
SN54284/74284 (DM7875A/8875AI
SN54285/74285 (DM7875B/8875BI
TRI·STATE outputs
Typical propagation delay

35 ns

OUTPUTS

51

14

Features
•

Typical Application

~

V4

outputs. A gated two-input strobe control is provided.
When either one, or both, of the strobe inputs is raised
to a high logic level the outputs are forced into the
high-impedance state. Thus, multiple devices may be
connected to a common bus line.

P2

Pl

12

1]

MOST

v,

P3
11

10

V3
V2
VI

9

X4-MOST SIGNIFICANT BIT

X,
X3
X2
Xl

X3
X2
Xl-LEAST SIGNIFICANT 81T

-

"

SIGNIFICANT
BIT

P3

DM1875A!
DM8875A

P2
PI

x.v
Y4-MOST SIGNIFICANT BIT

P4

Vl
V2

P3

Yl-lEAST SIGNIFICANT BIT

2

1

Vl

V2

4

1
VI

X4

5

Xl

6

X2

7

Xl

OM787581
,OM88158

I'

P2

GNO

7875A(J); 8875A(J), (N);
7875B(J); 8875B(J), (N)

PI

AC Test Circuit
s.ov

01
OUTPUT

OM7875/
DM8875

1k

3-154

LEAST
SIGNIFICANT
BIT

~

Proprietary

DM78/DM8875A.75 B

Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER

CONDITIONS

DM78

DM88

75A,758

75A,758

MIN
V'H

High Level Input Voltage

V'l

Low Level Input Voltage

V,

Input qamp Voltage

IOH

High Level Output Current

VOH

High Level Output Voltage

Low Level Output Current

Val

Low Level Output Voltage

UNITS

MIN TVP(I) MAX
2

V
0.8

0.8
Vee = Min, I, ~ -12 mA

Vee

= Min, V 1H :; 2V
= 0.8V, 10H = Max

10L =

Off State (High Impedance State)

Vee = Max, V 1H

Output Current

V ,L = 0.8V

-1.5

V

-2.0

-'5.2

mA
V

2.4
16

16

0.4

0.4

Va = O.4V

-·40

-40

Va = 2.4V

40

40

16 mA

= 2V

V

-1.5

2.4

Vee = Min, V 1H -= 2V
V ,L = 0.8V,

IOIOFFI

MAX

2

V ,L
IOl

TVP(ll

mA
V

IlA

I,

Input Current at Maximum Input Voltage

Vee = Max, V, = 5.5V

1

1

I'H

High Level Input Current

Vee = Max, V, = 2.4V

40

40

IlA

I,L

Low Level Inpl:Jt Current

Vee = Max, V, = O.4V

-1.0

-1.0

mA

los

Short Cilfcuit Output Current

Vee = Max(2)

-70

mA

Icc

Supply Current

Vee = Maxq)

-70

-20
75

-20

110

75

110

mA

rnA

Notes

= 25°C.

(I)

All typical valu", are at VCC = 5V, TA

(2)

Not more than one output should be shorted at a time.

(3)

ICC is measured with all inputs grounded.

Switching Characteristics vee

=

5V,T A = 25°C
DM78/88

PARAMETER

FROM

TO

CONDITIONS

75A,758
MIN

tpLH

Propagation Delay Time,
Low-ta-High Level Output

tpHL

Propagation Delay Time,
High-to·Low Level Output

Data

Output

Data

Output

CL = 50 pF, RL = 400n

UNITS

TVP

MAX

35

60

n,

35

60

n,

t~H

Output Enable Time to High Level

20

30

ns

tZL

Output Enable Time to Low Level

20

30

n,

tHZ

Output Disable Time from High Level

tLZ

Output Disable Time from Low Level

CL

c

20

30

n,

20

30

n,

5 pF, R L = 400[2

Switching Time Waveforms
tZL & tZH

J

tLZ & tHZ

STROBE·~1.5V
STROBE'
X. v

-

INPUTS _ _ _ _

------_r---

1.5V

OUTPUTS

tpHL

'H5V

OUTPUTS

-

/-,.5V

I'~~
..L

tpLH
<1.5V

INPUT PULSES:
tr <: IfS 10 ns
f= 1 MHz

STROBE

~

12

tZH . - -

3-155

~1.5V

OUTPUTS

~1.5V

--

'LZ

I~v
..::r.

ACTUAL "0"
VOLTAGE

~

1.5V

I
I

ACTUAL "1"
VOLTAGE

--

'HZ

:r
I--":~v

1.5V

~ Proprietary

DM8898,99
TRI-,$TATE BCD to Binary/Binary to BCD Converters

General Description
In addition to BCD-to-binary conversion, the DM8898 is
programmed to generate BCD 9's complement or BCD
10's complement. In each case, one bit of the complement
code is logically equal to one of the BCD bits; therefore,
these complements can be produced on three lines. As
outputs V6, V7, and V8 are not required in the BCD·to·
binary conversion, they are utilized to provide these
complement codes as specified in the truth table when
the devices are connected as shown.

These circuits are the TRI-STATE versions of the popular
BCD to binary and binary to BCD converters, DM74184
and DM74185A respectively, They are derived from the
256-bit ROM, DM8598. Emitter connections are made
to provide direct read out of converted codes at outputs
Y8 through Y 1, as shown in the truth tables. Both
converters comprehend the fact that the least significant
bits (LSB) of the binary and BCD codes are 10gic~lIy
equal, anq in each case the LSB bypasses the converter.
Thus a 6-bit converter is produced in each case, and
both devices are cascadable.

DM8899 BINARV-TO-BCD CONVERTERS
An overriding enable input is provided on each converter
which, when taken high, inhibits the function, causing all
outputs to go into the high-impedance state. For this
reason, and to min-imize power consumption, unused
outputs Y7 and Y8 of the 185A and all "don't care"
conditions of the 184 are programmed high.

The function performed by these B-bit binary-to'BCD
converters is analogous to the algorithm:
a. Examine the three most significant bits. If the
sum is greater than four, add three and shift left
one bit.
b. Examine each BCD decade. If the sum is greater
than four, add three and shift left one bit:
c. Repeat step b until the least-significant Dinary
bit is in the least·significant BCD locatio!].

DM8898 BCD-TO-BINARV CONVERTERS
The 6·bit BCD-to-binary function of the DM8898 is
analogous to the algorithm:
a. Shift BCD ;'umber right one bit and examine each
decade. Subtract three from each 4-bit decade
containing a binary value greater than seven.
b. Shift right, examine, and correct after each shift
until the least significant decade contains a number
smaller than eight and all other converted decadescontain zeros.

Features
• TRI-STATE versions DM74184, DM74185A
• Typical propagation delay

I

Connection Diagram

.

BINARV SELECT
ENA8.lE

l

G
1-6

I

E
15

0
14

\

C

B
12

13

11

10

9

--

VI

OUTPUT
VB

A

V2

V3

V4

V5

OUTPUTS

8898{N); 8899{N)

3·156

VB

V7

30 ns

~

DM8898.99

Proprietary

Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted)
DM88
CONDITIONS

PARAMETER

MIN
V,H

High Level Input Voltage

V,L

Low Level Input Voltage

V,

Input Clamp Voltage

IOH

High Level Output Current

VOH

High Level Output Voltage

Low Level Output Current

VOL

Low Level Output Voltage

IOIOFFI

I,

TYP(1)

MAX
V

2
O.B
Vee

Vee
V'I.

IOL

UNITS

98,99

=

=
=

Min, I,

-12 mA

=

= 2V
= -5.2 mA

4.7SV, V ,H
a.BV, IOH

-1.S

V

-S.2

mA
V

2A
12

Vee = 4.7SV, V ,H

= 2V

V'I.

=

12 mA

=

2V

Off State (High Impedance State)

Vee

Output Current

V'L

Input Current at Maximum Input Voltage

Vee

=

O.BV, 10L

= Max,
=

V ,H

O.BV

= Max,

V,

=

I
I

V

OA
Vo

=

OAV

-40

Va

= 2AV

40

V

IlA
mA

1

5.5V

mA

IIH

High Level Input Current

Vee

= Max,

V,

=

2.4V

40

IlA

I'L

Low Level Input Current

Vee

= Max, V,

=

OAV

-1.6

mA

los

Short Circuit Output Current

Vee

-70

mA

Icc

Supply Current

Vee

99

mA

-20

Max(2)
=

70

Max, V, = OV

Notes
( 1) All typical values are at VCC = 5V, TA = 25"C_
(2) Not more than one output should be shorted at a time.

Switching Characteristics Vcc

= 5V, T A = 25°C
DM88

PARAMETER

FROM

CONDITIONS

TO

98,99
MIN

tpLH

Propagation Delay Time,
Low-to-High Level Output

tPHL

Propagation Delay Time,
High-tn-Low Level Output

tpLH

Propagation Delay Time,
Low-to-H igh Level Output

tpHL

Propagation Delay Time,

High-to-Low Level Output

UNITS

TYP

MAX

Binary Sel ect

Output

29

50

ns

Binary Select

Output

33

SO

ns

Enable

Output

23

40

ns

Enable

Output

29

40

ns

CL

= 50 pF,

RL

= 400n

tZH

Output Enable Time to High Level

16

25

ns

tZL

Output Enable Time to Low Level

26

40

ns

tHZ

Output Disable Time from
13

20

ns

24

36

ns

High Level
tLZ

C L =5pF,R L

Output Disable Time from

Low Level
3-157

=

400n

~ Proprietary

DM8898,99

Truth Tables

BCD 9's OR BCD 10', COMPLEMENT CONVERTER

BCD-TO-BINARY CONVERTER

INPUTS
(See Note A)

BCD
WORDS

OUTPUTS
(See Note

INPUTS
(See Note C)

BCD

BI

WORD

OUTPUTS
(See Note 01

E

0

C

B

A

G

Y5

Y4

Y3

Y2

Yl

E'

a

C

B

A

G

YB

Y7

Y6

L

L

L

L

L

L

L

L

L

L

L

0

L

L

L

L

L

L

H

L

H

2 3

L

L

L

L

H

L

L

L

L

L

H

1

L

L

L

L

H

L

H

L

L

4 5

L

L

L

H

L

L

L

L

L

H

L

2

L

L

L

H

L

L

L

H

H

6 7

L

t

L

H

H

L

L

L

L

H

H

3

L

L

L

H

H

L

L

H

L

8 9

L

L

H

L

L

L

L

L

H

L

L

4

L

L

H

L

L

L

L

H

H

10 11

L

H

L

L

L

L

L

L

H

L

H

5

L

L

H

L

H

L

L

H

L

12 13

L

H

L

L

H

L

L

L

H

H

L

6

L

L'

H

H

L

L

L

L

H

14 15

L

H

L

H

L

L

L

L

H

H

H

7

L

L

H

H

H

L

L

L

L

16 17

L

H

L

H

H

L

L

H

L

L

L

L

H

L

L

L

l

l

l

H

0 1

A

18 19

L

H

H

L

L

L

L

H

L

L

H

S
9

l

H

L

l

H

L

L

L

L

20 21

H

L

L

L

L

L

L

I-!

L

H

L

0

H

l

l

L

l

L

l

l

l

22 23

H

L

L

L

H

L

L

H

L

H

H

1

H

l

l

l

H

l

H

L

l

24 25

H

L

L

H

L

L

L

H

H

L

L

2

H

l

l

H

l

l

H

L

L

26 27

H

L

L

H

H

L

L

H

H

L

H

3

H

L

L

H

H

L

I.

H

H

28 29

H

L

H

L

L

L

L

H

H

H

L

4

H

L

H

l

L

l

L

H

H

30 31

H

H

L

L

I-

L

L

H

H

H

H

5

H

L

H

L

H

L

L

H

L

32 33

H

H

L

L

H

L

H

L

L

L

L

6

H

l

H

H

l

L

l

H

L

34 35

H

H

L

H

L

L

H

L

L

L

H

7

H

L

H

H

H

L

'l

L

H

36 37

H

H

L

H

H

L

H

L

L

H

L

8

H

H

l

l

L

l

L

L

H

38 39

H

H

H

L

L

L

H

L

L

H

H

9

H

H

L

l

H

L

L

l

ANY

X

X

X

X

X

H

Z

Z

Z

Z

Z

ANY

X

X

X

X

X

H

Z

l
Z

H == High Level, L == Low Level,

H = High level, L

X = Don't Care, Z

X == Don't Care, Z == High Impedance

=

High Impedance

BCD 9's
COMPLEMENT CONVERTER

6-BIT CONVERTER

=

Low Level,

BCD 10',
COMPLEMENT CONVERTER

BCD
MSD

Z

BCD

LSD
~v

~~

0

A

1
6"BfT BINARV OUTPUT
BCD 9'S COMPLEMENT

BCD 10'S COMPLEMENT

Notes:

(e)

Input conditions other than those shown produce highs at outputs Y 1 through Y5.
Outputs Y6, Y7, and YB are not used for BCD-ta-binary conversion.
Input conditions other than those shown produce highs at outputs Y6,.Y7, and VB.

(0)

Outputs Y 1 through Y5 are not used for BCD 9's or BCD 1 D's complement conversion.

(A)
(8)

tWhen these devices are used as complement converters, input E is used as a mode con'trol. With this input low, the BCD 9's complement is gen~
arated; when it is high, the BCD 10'5 complement is generated.
.

3-158

~ Proprietary

DM8898.99

Truth Tables (Continued)

BINARY·TO·BCD CONVERTER

+-__________O~U~TP~U~T~S__________-4

BINARY ~________~I~N~P~UT~S~-r______
BINARY SELECT
ENABLE
WORDS
E
D
C
BAG

o

I

L

L

L

L

L

2 3

L

L

L

L

H

L

H

4 5

L

L

6 7

L

L

H

H

8 9

L

H

L

L

10 11

L

L

H

L

H

12 13
14 15

L

L

H

H

L

L

L

H

H

H

L

H

L

L

H

L

L

H

H

L

H

L

H

H

16 17
18 19
20 21
22 23

H

L

L

L

H

32 33

H

L

L

34 35

H

36 37

H

L

38 39
4041

H

L

H

L

H

L

42 43

H

L

H

L

44 45

H

L

H

H

L

46 47

H

L

H

H

H

L

H

52 53

H

H

54 55

H

56 57

H

58 59
60 61
62 63

ALL
H = High

L

L

L

L
H

L

H

L

H

L

L

H

L

H

H

H

L

L

L

L

H

L

L

L

H

H

H

H

L
L
L
L
H
H
H
H
H
H
H

H

H

L

L

H
H
H
H
H
H
H
H
H
H
H

H

L

L

L

H
H
H
H
H
H
H
H
H
H
H

L

30 31

H

L

L

H

28 29

H

H

H

H

L

H

L
L

L

L

H

L
H

H

L

48 49

H
H

L

H

50 51

L
L

H

L

H

L

L

L

L

L

H

H

~

L

L

L
L

n

L

L

H

H

L

n

L

L
L

H

H

L

H
H
H
H

~

L

H

H

L

H

"

H
H
H
H
H

L

H

H

H
H
H
H

"

H

L

H

H
H
H
H

H
H
H
H
H

26 27

L

~

H
H
H
H

L

24 25

L

~

L
H

L

H

L

H

L

H

L

H

H

H

L

H

H

H

L

H
H
H
H

H
H
H
H

L
L
L
H

H
H
L

L

L

L

L

L

H

L

L
L

L

L

L

H

L

H

L

L

H

L

L
H
L

H

H

L

H

H
L
L

L

H

L

H

H

L

H

H

H

H

H

L

H

L

H

H

H

L

L

H

H

H

L

H

L

H

H

H

H

L

H

H

H

H

H

H

L

H

H

H

H

L

L

H

H

H
H

L

H

H
H

L

H

H
H

H

H

H

L

L

L

H

z

z

z

z

z

z

z

z

x x x x
Level, L = Low Level, X = Don't
x

H

Care, Z = High Impedance

6·BIT CONVERTER
6-BIT
BINARV INPUT

"
1

2j 2j 21 2j 2i 2

liitiil
BAD
C B
'-v--'
'-v_ _

~

. MSD

__

LSD·

6-BIT BCD DUTPUT

3·159

H

National Semiconductor
ADDITIONAL DEVICES
Section 4

·

~ Additional Devices

DTL

RATINGS
Maximum A"owable
Supply Voltage

Max Ratings/Operating Conditions

2502

72xxl

9000C

93XXI

96XXI

SERIES

82XX

SERIES

83XX

86XX

8

7

N/A
5

4.50 to 5.50
4.75to5.25

Maximum Input Voltage

5.5

5.5

5.5

Max.imum Voltage to Open·
Collector Outputs

8

7

7

N/A

-55 to +125
o to +70

Guaranteed Operating
Supply Voltage Range

Operating Free-Air
Temperature Range

I Mil
I Com I

I Mil
IComl

o to +75

7

7

4-ii

7

V

4.50 to 5.50
4.75 to 5.25

V

5.5

5.5

5.5

V

7

7

7

V

N/A
4.75-5.25

N/A

-65 to +150

Storage Temperature Range

7

UNITS

-55 to +125

o to +75

°C
°C

~. Additional Devices
Device No.
DM930
DM932
DM933
DM935
DM936
DM937
DM944
DM945
DM946
DM948
DM949
DM957
DM958
DM961
DM962
DM963
DM1800
DM1801
DM2502/DM2502C
DM2503/DM2503C
DM2504/DM2504C
DM7280/DM8280
DM7281/DM8281
DM7288/DM8288
DM7290/DM8290
DM7291/DM8291
DM9002C
DM9003C
DM9004C
DM9005C
DM9006C
DM9008C
DM9009C
DM9012C
DM9016C
DM9024/DM8024
DM9093
DM9094
DM9097
DM9099
DM9300/DM8300
DM9301/DM8301
DM9309/DM8309
DM9310/DM8310
DM9311/DM8311
DM9312/DM8312
DM9316/DM8316
DM9318/DM8318
DM9322/DM8322
DM9334/DM8334
DM9601/DM8601
DM9602/DM8602

Table of Contents
Page
No.

Description
Dual 4·lnput Gates with Expanders
Dual 4-lnput Buffers with Expanders
Dual 4-lnput Extenders
Hex Inverters
H ex Inverters
Hex Inverters
Dual 4-lnput Power Gates with Expanders
R-S Flip-Flops
Quad 2-lnput Gates
R-S Flip-Flops
Quad 2-lnput Gates
Quad 2-lnput Buffers
Quad 2-lnput Power Gates
Dual 4-lnput Gates with Expanders
Triple 3-lnput Gates
Triple 3-lnput Gates
Dual 5-lnput Gates
Dual 5-lnput Gates
Successive Approximation Registers
Successive Approximation Registers
Successive Approx imation Registers
Presettable Decade Counters
Presettable Binary Counters
Presettable Divide-by-12 Counters
Presettable Decade Counters
Presettable Binary Counters
Quad 2-lnput NAND Gates
Triple 3-lnput NAND Gates
Dual 4-lnput NAND Gates
Expandable Dual 2-lnput AND-OR-INVERT
-Gates
Dual 4-lnput Expanders
Expandable 4-Wide AND-OR-INVERT Gates
Dual 4-lnput NAND Buffers
Quad 2-lnput NAND Gates with OpenCollector Outputs
Hex Inverters
Dual J-K Flip-Flops with Preset and Clear
Dual J- K Flip-Flops
Dual J-K Flip-Flops
Dual J-K Flip-Flops
Dual J - K Flip-Flops
4-Bit Parallel-Access Shift Registers
1 of 10 Decoders
Dual 4-Line to 1-line Data Selectors/
Mul tiplexers
Synchronous 4-Bit Decade Counters
4-line to 16-Line Decoders/Demultiplexers
8-line to 1-line Data Selectors/Multiplexers
Synchronous 4-Bit Binary Counters
Priority Encoders
Quad 2-Line to 1-line Data Selectors/
Multiplexers
8-Bit Addressable Latches
Retriggerable One Shots
Dual Retriggerable, Resettable, One Shots

4·iii

J
Mil

•
•

4-'
4-'
4-1

4-'
4-1
4-1
4-1
4-'
4-1

4-"
4-11
4-11
4-11
4-15
4-15
4-15
4-15

•
•
•
•
•
•
•
•

4-15
4-15
4-15
4-15
4-15
4-17
4-1
4-1
4-1
4-1
4-19
4-22
4-24
4-27
4-33
4-24
4-27
4-36
4-38
4-40
4·43
4-46

•

•

•
•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•.•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

W
Mil

•

•
•

•
•
•
•
•
•
•
•
•
•
•
•
•

•
•

•
•

•
•
•

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

Com I
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A

•
•
•
•
•
•

•
•

4-'
4-1
4-1

4-'
4-1
4-1
4-1
4-1
4-1
4-6
4-6
4-6
4-11

Coml

Package
N
Mil
Coml

•
•
(F)
•

•
•
•
•

N/A
N/A
N/A
N/A

•
•(F)
•
•
•
•
•

N/A
N/A
N/A
N/A
N/A

•
•
•
•
•
(F)
•

•
•
•
•
•
•

N/A
N/A
N/A
N/A

•
•
•
•
•
(F)
•
•
•
•
•
•
•

~ Additional Devices

DM930 Series
DTL Circuits

General Description
The National Semiconductor family of DTL is a complete
line of compatible monolithic integrated circuits designed
to operate at medium speed with medium power dis~
sipation and high fan~out. The DTL family is available
in 14~pin epoxy B 01 ceramic dual~in~line packages for
operation over the oDe to +75"C temperature range.

The DM9093 and DM9094 are dual JK fl ip-flops of the
DM945 and DM948 variety respectively. Both flip-flops
have separate clocks and no asynchronous clear lines.
The DM9097 and DM9099 are dual JK fl ip~flops of the
DM948 and DM945 variety respectively_ Both flip-flops
have common clocks and both asynchronous set and
clear I; nes_

The DTL line is composed of a variety of NAND gates
. that allow complete design flexibility. The gates are
available with either 6k pull-up resistors for low power
dissipation, or 2k pull~up resistors for increased speed.
The gate outputs can be wired together to achieve the
wired-OR function.

The DM930 series is directly compatible with the TTL
devices manufactured by National and can be used in
conjunction with them in those portions of a system
where speed is not the main consideration.

Features

The NAND gates are complemented with the DM932
and DM957 buffers which provide higher fan~out; the
DM944 and DM958 power gates which have an open
collector, and the DM933 extender which allows in~
creased fan~in for both buffers and DM930 and DM961
gates.

•

The flip~flops in this family are of the direct coupled
master-slave type, with direct ciear and direct set lines.
The dual flip~flops include ones with either common
or separate clocks_

NAND Gates
DM930, DM961 - dual four input gates with
expanders
DM935, DM936, DM937 - hex inverters
DM946, DM949 - quad two input gates
DM962, DM963 triple three input gates
OM 1800, DM 1801 - dual five input gates

•

The DM945 and DM948 are R~S flip~flDps which can be
externally crDSS coupled to perform in the JK mode.
They are of the master-slave type with output buffers
to provide isolation from the output load. These flip~
flops feature both asynchronous set and clear lines.
The DM945 has a 6k puil~up resistor and the DM948
has a 2k pull-up resistor.

Buffers/Extenders
DM932 ~ dual four input buffer with expander
DM933 - dual four~input extender
DM944 - dual four input power gate with expander
DM957 - quad two input buffer
DM958 - quad two input power gate

•

Flip-Flops
DM945, DM948 - RS flip-flops
DM9093, DM9094, DM9097, DM9099
flip-flops

dual JK

Truth Tables

SYNCHRONOUS TRUTH TABLE

CD

a

Q

Pin 5

Pin"6

Pin 9

H

H

NC

NC

L

H

H

L

On

H

L

L

X

an

L

L

H

X

L

On
L

tn

tn

+1

51

S2

C1

C2

a

Pin 3

Pin 4

Pin 12

Pin 11

Pin 6

X

L

X

0"

X

X

L

X

L

L

x

L

L
L

I

ASYNCHRONOUS TRUTH TABLE

L

X

H

H

x

L

H

H

L

H

H

L

X

H

H

H

X

L

H

H

H

H

H

*

SD
Pin 10

JK TRUTH TABLE

+1

tn

tn

51

a

Pin 3

C1
Pin 12

Pin 6

L

L

On

H

H

L

H

H

L

H

l

H

H

On

{Connect 52 to 0., C2 to Qj Asynchronous inputs, direct set (Sol and direct
clear (CO), override the synchronous
inputs, and are independent of all other
InplJts.

*-

Indeterminate State
X - Don't Care

4-1

~ Additional Devices

DM930 Series

Connection and Logic Diagrams

I

"""-'
~.
J

I
11 -11----1 ;>0---+--10

10 -r-"--_--'
11-,--r---,

~.

12

1 3 - t - -...
11

~,
I J

10

-t===_--.1

1 3 - 1 - - - - - 1 ><:>--+-11

930IJ), IN); 932IJ), IN);
944IJ), IN); 961(J1, IN);
1800lJI, IN); 1801(JI, IN)

I

13

I

11

946(J), IN); 949IJ), IN)

9351Jl, IN); 936IJ), IN);
937IJ), IN)

~,

I

10---+-12

13-t--"'

./'

~,

I

-

~.

./'
..--..

10

I

11

I
10-1----1

12

11

13

962(J1, IN); 963IJ), IN)

1 0 - r -_ _-I

)--+-11

12

13-1---,-1

957IJ), IN); 9581JI, IN)

933IJ), IN)

10 - 1 - - - - - - .

li=E;:::1~
ll--1f-::::'L../'a.;;..~...::.1

10-1----,

10-H+---.

11-1--;
13-1--1J/

11~H+-I

12-1--;

12--'1-+-1
13

945IJ); IN); 9481JI, IN)

90931Jl, IN); 9094IJ), IN)

4-2

-t:::!==__.J
9097(J), IN); 9099IJ), IN)

~

Additional Devices

Electrical Characteristics (V cc

DM930 Series
= 5.0V)

DM930, DM935, DM936, DM937, DM946
DM949, DM961, DM962, DM963, DM1800, DM1801
PARAMETER

CONDITIONS

o°c
MIN

ICEX

VOH

Output Leakage Current

V, =0, Vo =5V

High Level Output Voltage( 1)
Low Level Output Voltage

VI = V 1H .

IIH

High Level Input Current (1)

V, = V R

IlL

Low Level Input Current

V, = V F

los

Short Circuit Output Current

ICC1

Supply Current
Propagation Delay Time,

100
100

Max

Vee - BV, V, -

6k Gates

Propagation Delay Time,

V

0.50

5

10

I1A

-1.33

rnA

1.30

-1.40
-1.B5

-3.90

-0.61

-1.30

2k Gates

5.9

4
4

2k Gates

15

60

6k Gates

25

BO

2k Gates

10

30

6k Gates

10

30

Test Conditions

GATES
(6k)

(2k)

(6k)

(2k)

10L
(rnA)

10L
(rnA)

10H
(rnA)

IOH
(rnA)
-0.5

o°C

2.0

1.2

4.0

0.45

-

12.0

11.0

-0.12

+25°~

1.9

1.1

4.0

0.45

5.0

12.0

11.0

-0.12

-0.5

+75°C

1.B

0.95

4.0

0.50

-

11.4

10.4

-0.12

-0.5

,

4-3

V

0.45

6k Gates

VR
VIH
VF
VIL
VCEX
VOLTS VOLTS VOLTS VOLTS VOLTS

I1A

5

Notes
U) Applies to all gates except DM935.

TEMP.

UNITS

MAX

0.45

a

C L = 50 pF, RL = 400n

High·to-Low Level Output

MIN

2.5

-1.40

C L =30pF, RL =3.9kn

Low-ta-High Level Output

2.6

2k Gates

Vee = 5V, V, = V R

ICC2

MAX

2k Gates

2.6

. V, = a

Supply Current

tPLH

tpHL

IOL =

MIN

6k Gates

V'L = Max, IOH = Max

VOL

75°C

25°C
MAX

-1.25

rnA

rnA
rnA
ns

ns

~

DM930 Series

Additional I;)evices

Electrical Characteristics

(Vcc = 5.0\1)

,
PARAMETER

DM932, DM933, DM944. DM957. DM958

o'c

CONDITIONS
MIN

VIL

Low Level Input Voltage

ICEX

Output Leakage,Current

VOH

High Level Output Voltage

VOL

Low Level Output, Voltage

IIH

IlL

IlL

933

= I'FD

High Level I,nput Current

IOL':::

932,957

Max

Short Circuit Output Current

IccI

Supply Current

tPLH

tPHL

0.45

0.50

5

10
10

mA

-16

-'16

-14

mA

30.0

944

22.5

·957

60.0

958

4.5
4
80

15

50

150[2

932,957

15

40

150[2

944,958

10

35

932
957

944
958

'932
957

10L
·(mA)

10L
(rnA)

10H
(rnA)

500 pF. RL

~

C L = 100 pF, RL

~

Test Conditions

BUFFERS/EXTENDERS

TEMP.

,

VR
VF
VIH
VIL
VCEX
VOLTS VOLTS VOLTS VOLTS VOLTS

IFO
rnA

O'C

2.0

1.2

4.0

0.45

-

-2

36

40

-2.0

+25'C

1.9

1.1

4.0

0.45

5.0

-2

36

40

-2.5

+75'C

1.8

0.95

4.0

0.50

-

-2

34

36

-3.0

,
4-4

/lA

-1.33

25

CL

V

-1.40

944,958

High-to-Low Level Output

/lA

'-1.40

932,957

Propagation Delay Time,

V

V

.5

933.

CL = 500 pF, RL = 510[2
C L = 20 pF, RL = 510[2
=

2.5

5

All Except

Low-to-High Level Output

Propagation Delay Time,

200

5

932,957

Vee = 8V, V, = 0

0.75

933

932

Supply Current

0.60

UNITS

MAX

Others

933

Vee = 5V, V, = V R

ICC2

2.6
0.45

All Except

V, = 0

0.82

75'C
MIN

100

2.6

933

V, = V F

loS

25

All Except

V, = V R

Low Level Input Current

0.68

MAX

100

944,958

V, = V'L' IOH = Max

V 1H •

0.90'

MIN

932,957

v,=0.Vo=5V

VI =

0.75

25'C'
MAX

mA

rnA

ns
ns

~

Additional Devices

Electrical Characteristics

(Vee

DM930 Series
= 5,OV)
DM945, DM948, DM9093, DM9094
DM9097, DM9099

PARAMETER

CONDITIONS

oOe
MIN

ICEX

Output Leakage Current

VOH

High Level Output Voltage
IOH = Max

VOL

Low Level Output Voltage

"H

High Level Input Current

Data

945,948

Set, Reset

945,948
9093,9094

All

9097,9099

100
2.6

2.5

2.6

2.6

2.6

2.6

2.6

2.5
045

0.50

5.0

10.0

Set, Reset

945,948

5.0

5.0

10.0

945,948

30

30

40

9093,9094

20

20

30

9097,9099

40

40

60

9097,9099

10

10

20

5.0

5.0

10.0

9093,9094
9097,9099

on 9097, 9099

Data

All

-0.95

-0.95

·{l.90

Set, Reset

945,948

-2.8

2.8

-2.67

-2.8

"2.8

-2.67

2.8

-2.8

-2.66

"2.8

-2.8

-2.67

-56

-5.6

9093,9094

Direct Set

9097,9099

VI "'-,V F

945
Clock

948,9093
9094

Clock, Direct

9097,9099

Clear
VI =0

Supply Current

ICC2

:=

5V (Inputs Open)

Supply Current

V cc =8V,V 1 =O

-1.77

-4.2

-1.77

-4.2

-1.60

--40

6k

0.59

-1.41

-0.59

-1.41

-0.55

-1.38

Propagation Delay Time,
Low-ta-High Level Output

tpHL

Propagation Delay Time,
High-to-L.0w Level Output

CL =30p~,RL =2kn
CL

17

9093,9099

28

9094',9097

34

945

18

948

23

9093,9099

36

Test Conditions

25

75

6k

25

100

15

55

TEMP.

mA

ns

ns

948
9094
9097
(2kl

945
9093
9099
(6kl

948
9094
9097
(2kl

945
9093
9099
(Ski

. 948
9094
9097
(2kl

V CPTH

VCPTH

(VOLTSI

(VOLTSI

10L
(mAl

10L
(mAl

10H
(mAl

10H
(mAl

945

VR
VF
VCEX
V'H
V'L
VOLTS VOLTS VOLTS VOLTS VOLTS
\

O°C

2.0

1.2

4.0

0.45

-

1.15

1.30

16.8

15.4

-D.12

-D.5

+25°C
+7SoC

1.9

1.1

4.0

0.45

5.0

0.95

1.15

16.8

15.4

-D.12

-D.5

1.8

0.95

4.0

0.50

-

0.65

0.85

16.0

14.6

-D.12

-D.5

,
!

>2.5V
"

!
!

ov

!

,!

,

I
!
!

I

PRESET
REMOVED

,

,
,
!

TEST

I

!

4·5

I
I
I

>2.5V

,
,

• vCPTH

I

ov

,I

,

PRESET
REMOVED

TEST

I

!

I
!

I

'&fb

CPa

mA

mA

FLIP-FLOPS
9093
9099
(6kl

mA

45

2k

50 pF , R L = 330n

=

MA

14

948

9094,9097
tpLH

V

-'5.34

2k

945
Vee

V

0.45

All Except Clocks,

ICC1

MA

2.6

5.0

and Direct Clear

Short Circuit Output Current

MAX

All

Clear

lOS

MIN

945,948

Clock

Low Level Input Current

UNITS

75"C

MAX

Data

VI = V 1H , tOL = Max

VI = V R

"L

MIN

945,948

VI =0, Vo ""5V

VI '-' V 1L

25'e

MAX

I

~

Additional Devices

DM2502.03.04
Successive Approximation Registers

General Description
DM2503 and DM2504 operate over --55°C to +125°C;
the DM2502C, DM2503C and DM2504C operate over
\
O°C to +70°C.

The DM2502, DM2503 and DM2504 are 8-bit and 12-bit
TTL registers designed for use in successive approximation AID converters . These devices contain all the logic
and control circuits necessary (in combination with a
D/A converter) to perform successive approximation
analog-to-digital conversions.

Features

The DM2502 has 8 bits with serial capability and is not
expandable.

•
•
•

The DM2503 has 8 bits and is expandable without serial
capabil ity.

•

The DM2504 has 12 bits with serial capability and
expandability.

•
•

•

All three devices are available in ceramic DIP, eeramic
flatpak, and molded Epoxy·B DIPs. The DM2502,

Complete logic for successive appro'xi mati on AID
converters
8-bit and 12-bit registers
Capable of short cycle or expanded operation
Continuous or start·stop operation
Compatible with D/A converters using any logic code
Active low or active high logic outputs
Use as general purpose serial·to·parallel converter or
ring counter

Connection Diagrams
v"

a7

07

f16

15

06

12

13

"

a.

as

11

T

011

•

10

-

2.

I-

2

I
(DM2502)
00
IOM2S0ll

-

ep

S

•

J

no

a"

5

01

03

1

G!:

0

all

Ne
22

21

010

O'

20

19

08

07
18

16

j'

ep

S

Ne

06

17

15

13

"

l-

;-

7

6

02

23

2
00

•

3
0"

00

5

Ul

6

02

7
03

,

8

O.

11 J12"

10

Ne

OS

0

GNO

E
2504(J), (F); 2504C(J), (N), (F)

2502(J), (W); 2502C(J), IN), (W);
2503(J), (W); 2503C(J), (N), (W)

Truth Table
OUTPUTS(1)

INPUTS

TIME

0

S

E12)

00(3)

07

06

05

04

03

02

01

00

0

x

L

L

X

X

X

X

X

X

X

X

X

X

1

D7

H

L

X

L

H

H

H

H

H

H

H

H

2

06

H

L

D7

D7

L

H

H

H

H

H

H

H

3

D5

H

L

D6

D7

D6

L

H

H

H

H

H

H

4

D4

H

L

D5

D7

D6

D5

L

H

H

H

H

H

5

D3

H

L

D4

D7

D6

D5

D4

L

H

H

H

H

6

D2

H

L

D3

D7

D6

D5

D4

D3

L

H

H

H

7

Dl

H

L

D2

D7

D6

D5

D4

D3

D2

L

H

H

8
9

DO

H

L

Dl

D7

D6

D5

D4

D3

D2

01

L

H

X

H

L

DO

D7

D6

D5

D4

03

D2

D1

DO

L

10

X

X

L

X

D7

D6

D5

D4

D3

D2

Dl

DO

L

X

X

H

X

H

NC

NC

NC

NC

NC

NC

NC

NC

tn

Notes
(1) Truth table for DM2504 is extended to include 12 outputs.
(2) Truth table for DM2502 does not include
in truth table shown.

'E column or last line

(31 Truth table for DM2503 does not include DO column.

4·6

ace

H

= High Level

L

= Low Level

X

=

NC

0

Don't Care

No Change

,

~

Additional Devices

DM2502,03,04

Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted)
DM25
PARAMETER

CONDITIONS

02,02C
MIN

V ,H

High Level I nput Voltage

V,L

Low Level Input Voltage

V,

Input Clamp Voltage

10H

High Level Output Current

VOH

High Level Output Voltage

IOL

Low Level Output Current

Low Level Output Voltage

Vee

=

Min, 11 "" --12 mA

Vee

=

Min, V ,H

I nput Current at

Maximum Input Voltage
I'H

I,L

High Level Input Current

Low Level Input Current

los

Current

ICC

TYPlll

'"

IOH

2V

-"--48OI1A

04,04C
MAX

=
:.

Min, V 1H
O.BV,

tOl ==

Vee == Max, V,

Vee

=

Max

MIN

2

2V

0.2

9.6 rnA

= 5.5V

UNITS
MAX

2

V

0.8

0.8

V

-1.5

--1.5

-1.5

V

3.6

2.4

TYPI1I

0.8

--480
2.4

-480

3.6

2.4

9.6
Vee

3.6

9.6

0.4

0,4

0.2

1

0.2

9.6

rnA

0.4

V

rnA

1

1

CP Input

6

40

6

40

6

40

D, E, S Inputs

12

80

12

80

12

80

Vee

CP, S Inputs

-·1.0

-1.6

-1.0

-1.6

--1.0

-1.6

D, E Inputs

-2.0

-3.2

-·2.0

-3.2

·--2.0

-3.2

-20

-45

-20

-45

-20

-45

Military

65

85

60

80

90

110

Commercial

65

95

60

90

90

124

~

=

=

Max

CAV

Vee

=

Max(2)

Vee

=

Max

Supply Current

-10

-10

-10

MA
V

VI'" 2.4V

VI

Short Circuit Output

MIN

-480

V 1L

I,

MAX

2

V 1L =O.BV,

VOL

TYPlll

03,03C

MA

rnA

rnA

rnA

Notes

111 All typical values are at Vec = 5V, T A = 25°C.
121 Not more than one output should be shorted at a time.

Switching Characteristics vcc

~ 5V, TA ~ 25°C
DM25

PARAMETER

fMAX

Maximum Clock Frequency

tPlH

Propagation Delay Time.

FROM

TO

CONDITIONS

Low-to"High Level Output

CP
tpHl

Propagation Delay Time,

C L = 15 pF

tpHL

Propagation Delay Time,

TYP

tSETUP

MIN

TYP

04,04C
MAX

MIN

TYP

15

21

15

21

15

21

26

38

10

26

38

10

26

38

ns

10

18

28

10

18

28

10

18

28

ns

NIA

13

19

13

19

ns

NIA

16

24

16

24

ns

Q7 (Ql1)

E

MHz

CP High
SLow

Width of

Low Level

42

30

42

30

42

30

Clock Pulse

High Level

24

17

24

17

24

17

5 Input

16

9

16

9

16

9

o Input

8

4

8

4

8

4

Setup Time

UNITS
MAX

10

High-to-Low Level Output

tw

MAX

RL = 400n

Propagation Delay Time,
Low-to-High Level Output

MIN

03,03C

Output

High-ta-Low Level Output
tPLH

02,02C

4-7

ns
ns

~ Additional Devices

DM2502.03.04

Application Information
voltage level. If D/A converters are used that turn on
with a high logic level then the digital output is active
high; a logic "1" is represented as a high voltage level.

OPERATION
The registers consist of a set of master latches that act
as the control elements in the device and change state
on the input clock high-to;low transition and a set of
slave latches that hold the register data and change on
the input clock 'Iow-to-high transition. Externally the
device acts as a special purpose serial·to·parallel converter
that accepts data a,t the D input of the register and sends
the data to the appropriate slave latch to appear at the
register output and the DO output on the DM2502 and
DM2504 when the clock goes from low-to·high. There,
are no restrictions on the data input; it can change state
at any time except during ~hort i'nterval centered about
the clock low-to·high transition. At the same time that
data enters the register bit the next less significant bit
register is set to a low ready for the next iteration.

EXPANDED OPERATION
An active low enable input, E, on the DM2503 and
DM2504 allows registers to be connected together to
form a longer register by connecting the clock, D, and S
inputs in parallel and connecting the Occ output of one
register to the E input of the next less signifi.cant
register. When the start signal resets the register, the E
signal goes high, forcing the 07 (11) bit high and
inhibiting the register from accepting data until the
previous register is full and its Occ goes low. If only
one register is used the E input should be held at a low
logic level.

a

The register is reset by holding the S (Start) signal low
during the clock low·to·high transition. The register
synchronously resets to the state 07 (11) low, and all
the remaining register outputs high. The Occ (Conver- •
sion Complete) signal is also set high at this time. The S
signal should not be brought back high until after the
clock low-to·high transition in order to 'guarantee
correct resetting. After the clock has gone high resetting
the register, the S signal must be removed. On the next
clock low·to-high t'ransition the data on the D input is
set into the 07 (11) register bit and the 06 (10) register
bit is set to a low ready for the next clock cycle. On the
next clock low-to·high transitioil data enters the 06 (10)
register bit and 05 (9) is set to a low. This operation is
repeated for each register bit in turn until the register
has been fil,led. When the data goes into 00, the Occ ,
signal goes low, and the register is inhibited from further
change until reset by a Start signal.
The DM2502, DM2503 and DM2504 have a specially
tailored two-phase clock generator to provide' nonoverlapping two·phase clock pulses (i.e., the clock
waveforms intersect below the thresholds of the gates
they drive). Thus, even at very slow dVldt rates at the
clock input (such as from relatively weak compa'rator
outputs), improper logic operation will not result.

SHORT CYCLE
If all bits are not required, the register may be truncated
and conversion time saved by using a register output
going low rather ,than the Occ signal to indicate the end
of conversion. If the register is truncated and operated
in the continuous conversion mode, a lock-up condition
may occur on power turn-on. This' condition can be
avoided by making the start input the OR function of
Dec and the appropriate register output.
COMPARATOR BIAS
To minimize the digital error belo'w ±112 LSB, the
comparator must be biased. If a DI A converter is used
whiCh requires a low voltage level to turn on, the
comparator shOUld be biased +1/2 LSB. If the D/A
converter requires a h'Igh logic level to turn on, the
comparator must be biased -1/2 LSB.

Definition of Terms (See Timing Diagram)
CP: The Clock input of the register.
D: The 'serial data input of the register.
DO: The serial data out. (The D input delayed one bit),.

LOGIC CODES

E: The register enable. This input is used to expand the
length of the register and when high forces the 07 (11)
register output high and inhibits conversion. When not
used for expansion the enable is held at a low logic level
(ground).

All three registers can be operated with various logic
codes. Two's complement code is used by offsetting the
comparator 112 full range + 1/2 LSB and using the
complement of the MSB (07 or 011) with a binary D/A
converter. Offset binary is used in the same manner but
with the MSB (07 or 011). BCD D/A converters can be
used with the addition of illegal code suppression logic.

0i i = 7 (11) to 0: The outputs of the register.

Dec: The conversion complete output. This output
remains high during a conversion and goes low when a
conversion is complete.

ACTIVE HIGH OR ACTIVE LOW LOGIC

07 (11): The true output of the MSB of the register.

The register can be used with either D/A converters that
require a low voltage level to turn on, or D/A converters
that require a high voltage level to turn the switch on. If
D/A converters are used which turn on with a low logic
level, the resulting digital output from, the register is
active low. That is, a logic "1" is represented as a lo'w

Q7 (11): The complement output of the MSB of the
register'.
S: The start input. If the start input is held low for at
least a clock period the register will be reset to 07 (11)
low and all the remaining outputs high. A start pulse that
is low for a shorter period of time can be used if it
meets the set·up time requirements of the S input.

4·8

~ Additional Devices

DM2502.03.04

Logic Diagram

.,

~~I~~~,- ---n~---I

.6

.7

I
I
I
I

I
I
I
I

ii7--~==::::tI--'
f--_____J.-_ _ _ _ _ _.....L_ _ _~------..L---'
L ___________

Timing Diagram

J

Note 1: eeu logic is repeated for register stages.
Q5to Ql DM2502,DM2503
Q9 to Ql DM2504

02,03

ee
,NPUTS

l

:

L--.J

07y===]

06L:J
05L:J
o.y===]

.JL:J
OUTPUTS

o,y===]

O'L=:J
oor:::::J
neeL:]

00 .....__'-_--''--_.....
Switching Time Waveforms
AT LEAST

AT LEAST
tpwH(CP)

WAVEFORMS

INPUTS

OUTPUTS

Must be steady

Will be steady

---1.!iV

.5V

.5V

07(11)

....

.-

May change from

Will be changing

H to L

fromHtoL

May change from

Will be changing

L to H

from LtoH

Don't care: any
change permitted

Changing: state
unknown

G6(0)

----+-~

WfJJl!!!J.

00
(DM25D2,DM25D41 _ _ _ _ _...:...--lIJ/1.@~====:::t.1/J.(jJ

(DM2503, DM250!)

-------...Jf-----·
HtPLH

IEl MAX

07(11)

~

1.5V

\---------'.5V
ENABLE TO 07 Ill)

CP =H

BtPHLIEIMAX

~\\
4-9

S=L
1.5V

~. Additional Devices

DM2502,03,04

Typical Applications
BCD ILLEGAL CODE SUPPRESSION
ACTIVE HIGH

ACTIVE LOW

00

CLOCK

CP

DM2502

DM2502

CLOCK

Dc,

01 06 05 04 03 D2 01

Dc,

ao

07 0& 05 04 03 Q2 01 00

DIA CONVERTER

D/A CONVERTER

HIGH SPEED 12-BIT AID CONVERTER
5V1.. ov

5V

JlJ1J1I

~r~

1

r

S

v"

CLOCK
INPUT

'V'""L ov

Doc

C,

DO

DM2504
SAR

~E

r----.- ~~~:u\

0

lSB

MSB

-:!PARAllEL
OUTPUT

+5V

----, L± ~~
VIN

OV TO 10V

4-10

1.2M

'N91.

~ Additional Devices

DM72/DM8280,81,88 ,90 ,91
Presettable Counters

General Description
These high-speed counters consist of four dc-coupled,
master-slave flip-flops which are internally interconnected
to provide divide-by-two, divide-by-four, divide-by-five,
divide-by-six, divide-by-eight, divide-by-ten, divide-bytwelve, or divide-by-sixteen operations_ The counters are
fully programmable; that is, the outputs may be preset
to any number by placing a low logic level on the
count/load input and entefing the desired number at the
data inputs_ Transfer of information to the outputs
occurs on the negative-going edge of the clock pulse_
These counters also feature a direct clear which, when
placed at a low logic level, sets all outputs low regardless
of the conditions on the clocks_

operated in two independent modes:
1. When used as a high-speed 4-bit ripple-through
counter, output OA must be externally connected
to the clock-2 input. The input count pulses are
applied to the clock-1 input. Simultaneous divisions
by 2, 4, B, and 16 are performed at the OA' Os,
Oc, and 0 0 outputs as shown in the truth table
for the DM72B1/B2B1, DM?291/8291.
2. When used as a 3-bit ripple-through counter, the
input count pulses are applied to the clock-2 input.
Simultaneous frequency divisions by 2, 4, and 8
are available at the Os, 0c, and 0 0 outputs.
Independent use of flip-flop A is available if the
load and clear functions coincide with those of the
3-bit ripple-through counter.

Typical C;:ount Configurations
DM7280/DM8280, DM7290/DM8290

The output of flip-flop A is not internally connected to
the succeeding flip-flops; therefore, the count may be
operated in three independent modes:

DM7288/DM8288

The 8288 divide-by-twelve counter is a four-bit subsystem
consisting of divide-by-two and divide-by-six counters in
a 14-pin package. For divide-by-twelve operation, output
A is connected externally to the clock-2 input.

1. When used as a binary-coded decimal decade
counter, the clock-2 input must be externally
connected to the OA output. The clock-' input
receives the incoming count, and a count sequence
is obtained in accordance with the BCD count
sequence truth table.

Features
•

2. If a symmetrical divide-by-ten count is desired for
frequency synthesizers (or other applications requiring division of a binary count by a power of
ten), the 0 0 .output must be externally connected
to the clock-1 input. The input count is then
applied at the clock-2 input and a divide-by-ten
square wave is obtained at output OA in accordance
with the bi-quinary truth table.

•

•
•
•
•

3. For operation as a divide-by-two counter and a
divide-by-five counter', no external interconnections
are required. Flip-flop A is used as a binary element
for the divide-by-tvvo function. The clock-2 input
is used to obtain binary divide-bY-five operation at
the Os, Oc, and 0 0 outputs. In this mode, the two
counters operate independently; however, all four
flip-flops are loaded and cleared simultaneously .

Direct replacements Signetics B2BO, 8281, 8288,
8290,8291
Pin-for-pin with popular Series 54 counters:
82BO,B290-54176,54196
8281,8291-54177,54197
Fully programmable
Independent clear input
Performs BCD, bi-quinary, or quinary counting
Output OA maintains full fan-out while driving
clock 2
TYPICAL
TYPE

CLOCK FREQUENCY

TYPICAL
POWER OISSIPATION

CLOCK 1

CLOCK 2

50 MHz

25 MHz

150mW

DM7281/DM8281, DM7291/DM8291

7280/8280
7281/8281
7288/8288

The output of flip-flop A is not internally connected to
the succeeding flip-flops, therefore the counter may be

7290/8290
7291/8291

50 MHz

25 MHz

150mW

OATAINPtlTS

Connection Diagram

CLEAR

13

COUNT!
LOAD

·0

~

c

o.

D

B

11

12

----------

.,

CLOCK
1

10

,

CLDCK

DATA INPUTS

7280(J), (W); 8280(J), (N), (W); 7281(J), (W); 8281 (J), (N), (W);
7288(J). (W); 8288(J), (N), (W); 7290/8290(J), (N), (W);
7291/8291(J),.(N), (WI

4-11

-

~

Electrical Characteristics over recom!T'ended operating free-air temperature range (unless otherwise noted)
DM72/82
CONDITIONS

PARAMETER

80,81
MIN

V,H

High Level I nput Voltage

V,L

Low Level Input Voltage

V,

Input Clamp Voltage

IOH

High Level Output Current

VOH

High Level Output Voltage

IOL

Low Level Output Current

VOL

Low Level Output Voltage

Input Current at Maximum Input Voltage

'"

MIN

TYP(1)

2

0"
V

0_8

0_8

0.8

V

-1.5

-1.5

-1.5

V

-800

-800

--800

MA

2.6

2.6

2.6
16

mA

0.4

0.4

0.4

V

Vee = Max, V, '" 5.5V

1

1

1

Count/Load, Data

40

40

40

Vee = Max

Clear, Clock 1

80

80

aD

V, =4.5V

Clock 2 (8281,8291)

40

N/A

80

Clock 2 (Others)
Count/Load

V, = O.4V

lOS

Short Circuit Output Current

Vee = Max(2)

Icc

Supply Current

Vee = Max

:::l

III

C
CD

S.
(')
CD

V

16

Vee = Max

Q;.

;:j:

MAX

16

Low Level I nput Current

I,L.

MAX

Vee = Min, V ,H = 2V
V ,L = 0.8V, IOL = 16 mA

High Level I nput Current

.I'H

TYP(1)

Q.

III

Vee = Min:V'H = 2V

'~"-.

MIN

UNITS

90,91

2

Vee = Min, I, = -12 mA

'"

!

MAX

2

V ,L = 0.8V, IOH = -800MA

I,

TYP(l)

l>

88

80

80

120

-1.6

-1.6

-1.6

Data

-1.2

-1.2

-1.2

Clear

-3.2

-3.2

-2.8

Clk 1, Clk 2 (8280,8290)

-3.2

-3.2

-4.8

Clock 2 (Others)

-1.6

-1.6

-2.4

-18

-57
30

45

-18

-57
30

45

-18
30

mA

MA

mA

C

-57

mA

48.

mA

s:
....,
N
.......
C

s:

00
N
00

Notes
(11

All typical values are at VCC = SV, TA = 2SoC.

(21

Not more than one output should be shorted at a time.

0

Co
....
Co
00

Co
0

Co
....
- - - - - - - - - - - - - - - _ .. _ - - - -

-- --

-

-

- - - - - _.. _ - - - - -

-

-

Switching Characteristics vee

~ 5V, TA ~ 25°C

~

DM72/82
PARAMETER

FROM

CONDITIONS

TO

80,81
MIN

fMAX

Maximum Clock
Frequency

tpLH

Propagation Delay Time,
Low-ta-High Level Output

tpHL

Propagation Delay Time,
High-ta-Low Level Output

'PLH

Propagation Oelay Time,
Low-ta-High Level Output

tpHL

Propagation Delay Time,
High-ta-Low Level Output

tpLH

Propagation Delay Time,
Low-ta-High Level Output

tpHL

Propagation Delay Time.
High-ta-Low Level Output

tpLH

Propagation Delay Time,
Low-ta-High Level Output

f"
w

tpHL

Propagation Delay Time,

High-ta-Low level Output
tpLH

Propagation Delay Time,
Low-ta-High Level Output

'PHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpHL

Propagation Delay Time,
High-ta-Low Level Output

tw

tHOLD

'sETUP

tENABLE
----

Pulse Width

Input Ho!d Time

Input Setup Time

Count Enable Time
- --

Clock 1

aA

35

TYP

88
MAX

50

MIN
35

TYP

UNITS

90,91
MAX

50

MIN
40

TYP

MAX

50

MHz

l>

Q.
Q.
;:j.'

S'
j

!!.

Clock 1

aA

9

13

9

13

9

13

ns

eCD

Clock 1

aA

11

17

11

17

11

17

ns

ii'

<

CD

Clock 2

a.

12

18

12

18

12

18

ns

Clock 2

a.

14

21

14

21

14

21

ns

Clock 2

Dc

27

41

27

41

24

36

ns

Clock 2

Dc

34

51

34

51

28

42

ns

13

20

13

20

14

21

44

66

N/A

36

54

til

CL " 15 pF
Clock 2

aD

Clock 2

aD

8280,8288,8290

RL "400Sl

8281,8291
8280, 8288, 8290

17

26

17

8281,8291

50

75

N/A

26

16

23

42

63

ns
ns

Any Data Input

Any Output

19

29

19

29

16

24

ns

Any Data Input

Any Output

31

46

31

46

25

38

ns

Load

Any Output

29

43

29

43

22

33

ns

Load

Any Output

32

48

32

48

24

36

ns

Clear

Anv Output

32

48

32

48

25

37

ns

Clock 1

14

14

14

Clock 2

28

28

28

Clear

25

25

25

Load

20

20

20

High-Level Data

tW(LOAOI

twtLOAOI

tWtLoAO)

Low-Level Data

tW(LOAOI

twtLOAD)

tW(LOAO)

High-Level Data

15

15

10

Low-Level Data

20

20

15

25

25

30

ns

ns
ns
ns

e

s:.....

N
......

e

s:CO
N
CO

0

Ol
....
Ol
CO

CD
0

CD
....

~ Additional Devices

DM721DM8280,81,88 ,90,91

Truth Tables
80,90
BI·QUINARY (5·21
(S.. Not. BI

80,90
DECADE (BCDI
(S•• Note AI
OUTPUT
COUNT

81,91
TRUTH TABLE
(See Note AI

OUTPUT
COUNT

88
TRUTH TABLE
OUTPUT

OUTPUT

COUNT

COUNT

Ile

Os

0

L

L

L

L

O.

L

L

L

L

0

L

L

L

L

0

L

L

L

L

1

L

L

L

H

1

L

L

L

H

1

L

L

L

H

1

L

L

L

H

L

L

H

L

L

L

H

H

L

H

L

L

L

H

L

H

00 Ile

Os

QA

QA

00 Ile

Os

QD'

Ile

QIi

QA

QD

QA

L

H

L

L

4

L

H

L

L

2
3
4

H

L

L

L

5

L

H

L

H

5

L

5
6

H

L

L

H

6

L

H

H

L

6

L

H

H

L

H

7

H

L

H

L

7

L

H

H

H

7

L

H

H

H

L

L

8

H

L

H

H

8

H

L

L

L

L

L

L

H

9

H

H

L

L

9

H

L

L

H

8
9

H

L

H

L

L

H

10

H

L

H

L

10

H

L

H

L

11

H

L

H

H

11

H

L

H

H

12

H

H

L

L

13

H

H

L

H

(A) Output QA connected to clock 2 input.

14

H

H

H

L

(BI Output QD connected to clock 1 input.

15

H

H

H

H

2

L

L

H

L

2

L

L

H

L

2

L

L

H

L

3
4
5

L

L

H

H

L

L

H

H

3

L

L

H

H

L

H

L

L

H

L

L
'H

3
4

6

L

H

H

7

L

H

H

8

H

L

9

H

L

H = High Level, L = Low Level
Not.. :

Logic Diagrams

81,91

80,90

88

4·14

~ Additional Devices

DM9000C Series
Gates/Inverters

General Description
TTL circuits offering a choice of specific performance
ranges (see Sections 1 and 2); and are designed to serve
any application from industrial numerical controllers or
high-speed computers, to sophisticated high-reliability
aerospace and defense systems. Series 54/74 pin-for-pin
equivalents are available for the following SSI types:

DM9000C series devices are designed to be used in
existing systems as replacements for Fairchild 9000-type
circuits. These DM9000C circuits offer several significant
advantages over 9000 type circuits, some of which are:
•

Input clamp diodes

• Output short-circuit current specified to guarantee
the high-level impedance.
•

DM9000C SERIES

EQUIVALENT SERi'ES 74

DM9002C
DM9003C
DM9004C
DM9005C
DM9006C
DM9008C
DM9009C
DM9012C
DM9016C
DM9024C

Power dissipation of DM9000C circuits is i[1 most
cases lower than that for the equivalent 9000 type.

DM9000C circuits are characterized for operation over
the industrial temperature range of O°C to 75°C.
For new designs, the 54/74 families of TTL circuits
offer the industry's broadest choice of high-performance
digital circuits. Included are several families of compatible

DM7400
DM7410
DM7420
DM7450
DM74H60
DM74H53
DM7440
DM7403
DM7404
DM74109

Connection Diagrams
Vee

B4

A4

Y4

BJ

A3

Vl

Vee

D2

C2

NC

B2

A2

yz

A1

81

VI

Al

82

YZ

GND

A1

B1

Nt

Cl

01

V1

GNO

9002CIJ), IN); 9012CIJ), IN)

Vee

B1

AI

A'

"

C2

9004CIJ), IN); 9009CIJ), IN)

9003CIJ), IN)

01

C1

VI

Vee

01

D2

Y2

GND

AI

B1

.

"

Xl

i•

D2

C1

A2

"

C2

GNo

,

X"OllfllUtolEltpfndl!r

9006CIJ), IN)

9006CIJ), IN)

Vee

AI

A1

V1

9008CIJ).IN)

V6

AS

YS

A4

V4

A2

Y2

A3

Vl

GNU

9016CIJ), IN)

4:15

GND
X=OIll\llltofExplnder

~

Add itionalDevices

DM9000C Series

Electrical Characteristics over recommended ·operating free-air temperature range (unless

otherwi~e

noted)

DM90
05C
PARAMETER

V,H

CONDITIONS

I

High Level Input Voltage

O°C

02C,03C
04C,16C

EXPANDABLE
GATE

NONEXPANDABLE
GATE

MIN MAX

MIN MAX

MIN MAX

1.8

1.8

175°C.

1.6·

1.6

1.6

0.85

IOH

High Level Output Current

Vee = 4.75V, V'L = 0.85V

VOH

High Level Output Voltage

V OH = 5.5V

Low Level Output Voltage

I'H

High Level Input Current

Vee"" 4.75V

IOH "" --1.2 mA

V JL

IOH '"

IOl :: 16 mA

V 1H

IOL - 48 mA

Min

Low Level Input Current

IOl "" 14.1 mA

V 1H :: Min

IOL

at 5.2SV
los

Short Circuit Output Current

ICCH

Supply Current, All Outputs

High
ICCL

Supply Current, All Outputs

Low
/llcCH

Vee

1.6

1.6

0.85

0.85

-1.5

-1.5

-1.5

-1.2

-1.2

-1.2

-1.2

-3.6

2.4

2.4

V

0.85

0.85

-1.5

0.S5
-1.5

50

50

50

50

0.45

0.45

0.45

0.45

0.45

0.45

0.45

V
mA

50

mA

V

N/A
100

0.45
0.45

0.45

V

0.45
60

.

Vee = 4.75V

Vee = 5.25Vlll

V

0.25
N/A

2.4

= 42.3 rnA

= 5.25V

1.9

2.4

Vee = 5.25V, V, = 4.5V

V, = 0.45V

1.6

UNITS

0.45

Vcc- 4 .75V

Other Inputs

1.8

-1.5

2,4

Other Inputs at Ground

I,L

1.8

1:9
1.8

3.6mA

Vee = 5.25V
""

MIN MAX

125°C

Vee = 4.75V,I, = -12 mA

VOL

MIN MAX

1.9

Input Clamp Voltage

Low Level Output Current

MIN MAX

1.9

Low Level'lnput Voltage

10L

12C

1.9

V,

O.85V

09C

1.9
1.8

V,L

:.

06C,OSC

120

60

90

60

-1.6

-2.4

·-1.6

-2.4

-3.2

-1.6

-1.41

-2.12

-1.41

--2.12

-2.82

-1.41

-18 -55

90

-20 -70

-20 -70

-40 -100

-20 -70

N/A

J.
~

l

l

l

l

l

l

l

H

l

l

H

l

1
H
l
H
H
H

2
H
H
l
H
H

DECIMAL OUTPUT
4
5
6

0
l
H
H
H

D

4-22

3
H
H
H
l
H

7

H

H

H

H

H

H

H

H

H

H

H

H

8
H
H
H

9
H
H
H

H

H

H

H

H

H

l

H

H

H

H

H

H'

l

H

H

H

H

H

H

l

H

H

H

H

H

H

l

H

H

H

l

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

~

DM93/DM8301

Additional Devices

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
DM93i83
CONDITIONS

PARAMETER

01
MIN

V IH

High Level Input Voltage

VIL

Low Level Input Voltage

VI

Input Clamp Voltage

10H

High Level Output Current

VOH

High Level Output Voltage

10L

Low Level Output Current

VOL

Low Level Output Voltage

TYP(l)

UNITS
MAX

2

Vee = Min,

V

1,=-12mA

0.8

V

-1.5

V

-BOO
Vee = Min,

V'H = 2V

V'L = O.8V,

IOH

Vee

=:

Min,

=

-BOOJ1A

2.4

V

V'H = 2V

V,c = O.BV,

10L = 16 mA

II

I nput Current at Maximum I nput Voltage

Vee :-:: Max,

V,=5.5V

J1A

16

mA

0.4

V

1

mA

IIH

High Level Input Current

Vee

~

Max,

V, = 2.4V

40

J1A

IlL

Low Level Input Current

Vee

=

Max,

V, =OAV

-1.6

mA

los

Short Circuit Output Current

Vee = Max(2)

--55

mA

Icc

Supply Current

Vee = Max(3)

41

mA

--20
25

Notes
(11 All typical values are at Vee = 5V, T A = 25' e,
(21 Not more than one output should be shorted at a time.
(31

ICC is measured with the outputs open and all inputs grounded.

Switching Characteristics vee

= 5V, TA = 25°C
DM93i83

PARAMETER

CONDITIONS

01
MIN

tpHl

Propagation Delay Time, High-to-Low Level,
Any Output from A, B, C, or D

UNITS

TYP

MAX

19

30

ns

20

30

ns

C L = 15 pF, RL = 400n
tpLH

Propagation Delay Time, Low-to-High Level,
Any Output from A, B, C, or D

l____

423

~ Additional Devices

DM93/DM8309,12
Data Selectors/Multiplexers

General Description

Features

These data selectors/multiplexers contain inverter/
drivers to supply full complementary, on-chip, binary
decoded data selection to the AND-OR-INVERT gates.

DM9309/8309

• Direct replacement for Fairchild 9309
• Complementary outputs
• Dual one-of-four data selectors

The DM9309/8309 contains two separate 4·bit multi·
plexers with complementary Y and Y outputs; however,
the two sections have common address select inputs.

DM9312/8312

•
•
•
•
•

The DM9312/8312 is a single 8-bit multiplexer with
complementary outputs and a strobe control. When the
strobe is low, the function is enabled. When a high logic
level is applied to the strobe, the outputs are latched.

Direct replacement for Fairchild 9312
Selects one-of-eight data sources
Performs parallel to serial conversion
Strobe controlled outputs
Complementary outputs

Connection Diagrams
OUTPUTS
V2

15

14

.

OATA INPUTS

SELECT
INPUT
A

'12

2eo

2el
12

13

OUTPUTS'
2C3

2C2
11

,

V

TC

10

SElECT INPUTS

C

16

15

13

14

,
STROBE

A

12

10

11

-

Vl

SElECT
INPUT

'11

leo

lel

B

OUTPUTS

le2

J:

le3

DO

DATA
INPUT
07

-

01

02

03

04

05

os

J:

DATA INPUTS

DATA INPUTS

9309(JI, (WI; 8309(JI, (N), (WI

9312(JI, (WI; 8312(JI, (NI, (WI

Truth Tables
09

12

INPUTS
DATA

SELECT
B

A

OUTPUTS

CO

C1

C2

C3

V

Y

OUTPUTS

INPUTS
STROBE

SELECT
C

B

A

G

V

Y

L

L

L

X

X

X

L

H

X

X

X

H

L

H

l.

L

H

X

X

X

H

L

L

L

L

L

L

H

X

L

X

X

L

H

L

L

H

L

00
01

L

H

X

H

X

X

H

L

L

H

L

L

00
01
02

X

X

L

X

L

H

L

H

H

L

X

X

H

X

H

L

H

L

L

L

H
H

L

H

H

X

X

X

L

L

H

H

L

H

L

H

H

X

X

X

H

H

L

H

H

L

L

H

H

H

L

03
04
05
06
07

52
03

54
D5

56
57

Select inputs A and B are common to both sections.
H ::: High Level, L::: Low Level, X "" Don't Care.

H :: High Level, L"" Low level, X = Don't Care.

DO, 01 .. . 07 = The level of the respective 0 input.

4·24

~

DM93/DM8309.12

Additional Devices

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
DM93/83
CONDITIONS

PARAMETER

09,12
MIN

V ,H

High Level Input Voltage

V,L

Low Level Input Voltage

V,

Input Clamp Voltage

IOH

High Level Output Current

V OH

High Level Output Voltage

IOL

Low Level Output Current

VOL

Low Level Output Voltage

UNITS

TYP,(11

MAX
V

2
0.8
Vee = Min, I,

= -12 rnA

Vee

= Min, V 1H

V'L

=0.8V, 10H

= 2V

2.4

= -800p.A

Vee = Min. V 1H = 2V

I,

Input Current at Maximum Input Voltage

Vee = Max, VI = 5.5V

I'H

High Level Input Current

Vee = Max, VI

I,L

Low level Input Current

Vee

los

Short Circuit Output Current

Vee = Max(21

Icc

Supply Current

Vee = Max(3)

V

-800

p.A
V

3.4

0.2

V'L = 0.8V, 10L = 16 mA

V

-1.5

16

mA

0.4

V
mA

1

= 2.4V

40

p.A

= Max, VI = O.4V

-1.6

mA

-85

mA

44

mA

-30
27

Notes

= 2SC.

(1)

All lypical values are at V CC = SV, T A

(2)

Not more than one output should be shorted at a time.

(3)

ICC is measured with the outputs open and all inputs at 4.SV for the DM9309/B309, and with the strobe and data select inputs at 4.SV,
all other inputs and outputs open for the DM9312/B312.

Switching Characteristics Vee = 5V, T A = 25° C
DM93/83
PARAMETER

FROM

TO

MIN
tpLH

Propagation Delay Time,
Low-ta-High Level Output

tpHL

Propagation Delay Time,
High-ta-Low Level Output

tpLH

Propagation Delay Time,

low-ta-High ,Level Output
'PHL

Propagation Delay Til.'"e,
High-ta-Low Level Output

tpLH

Propagation Delay Time,
Low-ta-High Level Output

'PHL

Propagation Delay Time,
H igh-to- Low Level Output

tpLH

Propagation Delay Time,
Low-ta-High Level Output

'PHL

Propagation Delay Time,
High-ta-Low Level Output

tpLH

Propagation Delay Time,
Low-ta-High Level Output

tpHL

Propagation Delay Time.
High-la-Low Level Output

tpLH

Propagation Delay Time,
Low-to~High

'otIL

Level Output

Propagation Delay Time,
High·to·Low Level Output

DM93/83

09

CONDITIONS

12

TYP

MAX

MIN

UNITS

TYP

MAX

Select

Y

27

40·

22

33

ns

Select

Y

23

36

23

35

ns

Select

Y

17

24

18

·28

ns

Select

Y

20

29

16

25

ns

Data

Y

18

27

16

23

ns

Data

Y

23

34

17

25

ns

14

21

9

13

ns

9

13

9

13

ns

CL = 15 pF
RL = 40011

Data

y

Data

Y

Strobe

Y

N/A

22

33

ns

Strobe

Y

N/A

21

32

ns

Strobe

Y

N/A

13

19

ns

Strobe

Y

N/A

15

21

ns

4-25

-

~ Additional Devices

DMS3/DM830S.12

Logic Diagrams
09

IC3 (7)
(21 1'1 }
lC2 (61

111

OUTPUTS
Vl

lel

(51

lCO (41
DATA
INPUTS
2e3

(91
(141 V2
_ }

2C2 (101
(151

2el

1111

SELECT (31
INPUT B

12

STROBE
00

01

1101
111

(21

02 (31

03

(41

DATA
INPUTS
04 (51

05

06

(61

(71

07(91

A
jj

C

4-26

OUTPUTS
V2

~ Additional Devices

DM931DM8310.16
Synchronous 4-Bit Counters

General Description
These ·synchronous, presettable counters feature an
internal carry look-ahead for application in high-speed
counting designs. The DM9310/DM8310 are decade
counters and the DM9316/DM8316 are 4-bit binary
counters. The carry output is decoded by means of a
NOR gate, thus preventing spikes during the normal
counting mode of operation. Synchronous operation
is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each
other when so instructed by the count-enable inputs
and internal gating. This mode of operation eliminates
the output counting spikes which are normally
associated with asynchronous (ripple clock) counters.
A buffered clock input triggers the four flip-flops on
the rising (positive-going) edge of the clock input
waveform.

The carry look-ahead circuitry provides for cascading
counters for n-bit synchronous applications without
additional gating. Instrumental in accomplishing this
function are two count-enable inputs and a ripple carry
output. Both count-enable inputs (P and T) must be
high to count, and input T is fed-forward to enable the
ripple carry output. The ripple carry output thus
enabled will produce a high-level output pulse with a
duration approximately equal to the high-level portion
of the Q A output. This high-level overflow ripply carry
pulse can be used to enable successive cascaded stages.
High-to-Iow level transitions at the enable P or T inputs
may occur regardless of the logic level in the clock.

Features
•
•
•
•
•
•
•
•

These counters are fully programmable; that is, the
outputs may be preset to either level. As presetting is
synchronous, setting up a low level at the load input
disables the counter and causes the outputs to agree
with the setup data after the next clock pulse regardless
of the levels of the enable input. Low-to-high transitions
at the· load input are perfectly acceptable regardless of
the logic levels on the clock or enable inputs. The clear
function is asynchronous and a low level at the clear
input sets all four of the flip-flop outputs low regardless
of the levels of clock, load, or enable inputs.

Direct replacement for Fairchild 9310, 9316
Internal look-ahead for fast counting
Carry output for n-bit cascading
Synchronous counting
Load control line
Diode-clamped inputs
35 MHz
Typical clock frequency
Pin-for-pin replacements popular 54/74 counters
9310 - 54,160A/74160A (decade)
9316 - 54161A/74161A (binary)

Connection Diagram

Vee

1",6

RIPPLE
CARRY
OUTPUT

OUTPUTS

,
U,

15

14

,

Dc

D.
13

Do

ENABLE
T

LOAD

10

9

II

12

--c

1

2

CLEAR

CLOCK

6
A
________

'~

D

~

______-J'

DATA INPUTS
9310(J), (WI; 8310(JI, (N), (W);
9316(JI, (WI; 8316(J), (N), (WI

4-27

7
ENABLE

P

~

Additional Devices

Electrical Characteristics

ove~

.DM93/DM8310.16

recommended op~rating free-air temperature range (unless otherwise noted)
PM93/83

PARAM·ETER

MIN

:

VIH

High Level Input Voltage

V ll

Low Level Input Voltage

VI

Input

I.OH

High Level Output Current

VOH

High Level Output Voltage

CI~mp

Vee

= Min, I, = -12 mA

Vee

= Min, V ,H = 2V
= 0.8V, 10H = -800jJA

VOL

Low Level Output Voltage

Vee
V'L

II

Input Current at Maximum Input Voltage

IIH

High Level Input Current

Cloc~

or Enable T

Other Inputs'
Low Level Input Current

III

Clock or Enable T
Other Inputs

Short Circuit Output Current

los

ICCH

ICCl

I

Supply Current (High Level)

Supply Current (Low Level)

Not---;======~~~~====lrt
{Jl

DATAA~-----'

III
CLEAR

'4J
B--------H--++1H---t-,

DATA

'5}

DATA C

-------+H++++1H---t-,

16l
DATA 0

(15) RIPPLE
CARRV

OUTPUT

16

0,

III
ClOCK

{Jl
DATA A

III
CLEAR

0,

LOAD

DATA

'5}

c--------I-+-I+-+++++1-1",

16'

OATAD-------+H+H+H-+--r,

(t5) RIPPLE

CARRY
OUTPUT

4-30

~ Additional Devices

DM93/DM8310 .16

Timing Diagrams

9310/8310 SYNCHRONOUS DECADE COUNTERS
TYPICAL CLEAR, PRESET, COUNT AND INHIBIT SEQUENCES
CLEAR

--U

(ASYNCHRONOUS)

lDAD---+I-,u

I

A-.J

'NDp~~~

:

r --------------

I

l==============

-1'-_I---.L

_

-------------r-------------Sequence:

CLOCK

(1)

Clear outputs to zero

ENABLE P-----I---I.J

(2)
(3)

Preset to BCD seven
Count to eight, nine, zero, one, two, and three

ENABLE T

(4)

Inhibit

---t--+-'

----COUNT---- ----lNHIBIT----

CLEAR PRESET

9316/8316 SYNCHRONOUS BINARY COUNTERS
TYPICAL CLEAR, PRESET, COUNT AND INHIBIT SEQUENCES
CLEAR

~NCHRDNDUSI

,

lDAD=8r - - - - - - - - - - - - - DATAl -1
r-=============
A

B,
C

'NPUTS

0"']

I

I

i

-

-

-

-

-

-

-

-

-

-

-

-

-

L_=============

L_____________ _

CLOCK
ENABLE P

ENABLE T

OUTPUTS \

:
Qc

Sequence:
(1) Clear outputs to zero
(2)

Preset to binary twelve

---~-+'

(3)

Count to thirteen, fourteen, fifteen, zero, one,

---t---f.I

14)

__

and two

-+--+-+--'

00

RIPPlEOCU;~~i -----I--f.:'''"'--I.,,13:--'''14:--....I15
- - '- - C O U N T - - - - - - - - I N H 1 B 1 T - - - CLEAR PRESET

4·31

Inhibit

~ Additional Devices

DM93/DM8310.16

Parameter Measurement Information
SWITCHING TIME WAVEFORMS

CLOCK
INPUT

-F\-I

OV

tplH

tpHl

(MEASURE AT tN+tl
VOH
OUTPUT
0.
VOl

(MEASURE AT 'N'2)

VOH
OUTPUT
0.

OUTPUT

Dc

Val

VOH
VOL

VOH
OUTPUT
00

RIPPLE
CARRY
OUTPUT

VOL
VOH
VOL

Notes:
(A) The input pulses are supplied by a generator having the following characteristics: PRR ::; 1 MHz, duty cycle:S. 50%, ZOUT ~ 50,0, tr S. 10 ns,
tf:S. 10 ns. Vary PRR to measure fMAX.
(8) Outputs 00 and carry are tested at t n+10 for 9310/8310, and at tn+16 for 9316/8316, where tn is the bit time when all outputs are low.
IC) VREF ~ 1.5V.

SWITCHING TIME WAVEFORMS
CLOCK INPUT l.OV - - - - - - - - - , .
160A. LS160
161A. LS161
CLEAR
INPUT
LOAD
INPUT
DATA INPUTS
A. B. C. AND D

a OUTPUTS

9316
OUTPUTS
9310

a.

AND

aD

Ils

AND

ac OUTPUTS
9310

OV
l.OV
OV
3.0V
OV
VOH
VOL
VOH

VOl

--

l.OV-ENABLE P OR
ENABLE T

OV
VOH

CARRY
VOL

Notes:
(A) The input pulses are supplied by generators having the following characteristics: PRR
tf S; 10 ns.
(B) Enable P and enable T setup times are mQ,asured at tn+O.
IC)

VREF ~ 1.5V.

4-32

S. 1 MHz, duty cycle S. 50%, ZOUT ~ 50n, tr S. 10 ns,

~ Additional Devices

DM93/DM8311
4-Line to 16-Line Decoders/Demultiplexers

General Description

Features

Each of these 4-line-to-16-line decoders utilizes TTL
circuitry to decode four binary-coded inputs into one
of sixteen mutually exclusive outputs when both the
strobe inputs, Gl and G2, are low. The demultiplexing
function is performed by using the 4 input lines to
address the output line, passing data from one of the
strobe inputs with the other strobe input low. When
either 'strobe input is high, all outputs are high. These
demultiplexers are ideally suited for implementing highperformance memory decoders. All inputs are buffered
and input clamping diodes are provided to minimize
transmission·line effects and thereby simplify system
design.

•

Direct replacement for Fairchild 9311

•

Pin for pin with popular 54154/74154

•

Decodes 4 binary·coded inputs into one of 16 mutually
exclusive outputs

•

Performs the demultiplexing function by distributing
data from one input line to anyone of 16 outputs

•

Input clamping diodes simplify system design

•

High fan-out, low-impedance, totem-pole outputs

• Typical propagation delay

19 ns

• Typical power dissipation

170mW

Connection Diagram
Vee

INPUTS

,A

124

OUTPUTS

Gl ' '15

G2

23

22

21

20

19

18

5

6

1

13

14

17

15

16

\

11

12

13

14

-c

10

11 ,r2

.,-0;......-;1_...;;,2_...;3;....-.-;4_-Y~_..;6;.......;;,1_..;8;.......;;,9_..;.10;"1 GNO
OUTPUTS

9311(J), (F); 8311(J), (N), (F)

Truth Table
INPUTS

H

OUTPUTS

Gl

G2

0

c

B

A

o

L

L

L

L

L

L

L

L

L

L

L

L

H

L

L

L

L

H

L

L

L

L

L

L

L

H

8

9

10

11

12

13

14

15

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H
H
H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

)-l

H

H

H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H

H
H

H
H

H
H

H

H

H

H

H
H

H
H

H
H

H
H

2

3

4

H

H

H

H

H

H

H

L

H

H

H

H

H

L

H

H

L

H

H

H

H

H

H

H

L

H
H

L

L

H

H

H

H

L

L

L

L

H

L

H

H

H

H

H

H

L

H

H

H

L

L

L

H

H

L

H

H

H

H

H

H

L

H

H

L

L

L

H

H

H

H

H

H

H

H

H

H

L

H

L
L
L
L
L
L
L
L

L
L
L
L
L
L
L
L

H
H
H
H
H
H
H
H

L

L

L

H

H

H

H

H

H

H

H

L

L

L

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

L

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

L

L

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

H
H
H
H

H
H

H

L

H

H

H

H

H

H

L
H

H
L

H
H

H
H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

L

H

X

X

X

X

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

X

X

X

X

H

H

H

H

H
H

H

H

H

H

H

H

H

H

H

H

H

H

H

X

X

X

X

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

= High Level, L = Low Level,

X

= Don't Care
4-,33

~

Additional D.evices

DM93/DM8311

Electrical Characteristics over recommended operating free-air temperature ;ange (unless otherwise n·oted)

DM93/83
PARAMETER

11

CONDITIONS

V,H

High Level Input Voltage

V,L

Low Level Input Voltage

V,

I nput Clamp Voltage

10H

High Level Output Current

VOH

High Level Output Voltage

,

Low Level Output Current

VOL

Low Level Output Voltage

MAX

2

V

V ce = Min. II = -12 mA

0.8

V

-1.5

V

-800
Vee = Min, V IH = 2V

304

2.4

V il = 0.8V, 10H = -800JlA
10L

UNITS

TYP(1)

MIN

Vee = Min, V IH = 2V

V

0.25

V il = 0.8V, IOl = 16 mA

JlA

16

mA

004

V

I,

Input Current at Maximum Input Voltage

Vee = Max, VI = 5.5V

1

I'H

High Level Input Current

Vee = Max, VI =·2AV

40

JlA

I,L

Low Level I nput Current

Vee = Max, VI = OAV

~1.6

mA

los

Short Circuit Output Current

Icc

Supply Current

Vee = Max(2)

Vee = Max(3)

DM93

-20

-55

DM83

-18

-57

DM93

34

49

DM83

34

56

mA

mA

ilnA

Notes
(1) All typical value. are at Vcc = 5V, TA = 25°C.
(21 Not more than one output should be shorted at a time.
(3)

ICC is measured with all inputs grounded and all outputs open.

Switching Characteristics

Vee = 5V, T A = 25°C
DM93/83

PARAMETER

CONDITIONS

tpLH

UNITS

11
MIN

TYP

MAX

18

27

ns

21

30

ns

17

25

ns

18

27

ns

Propagation Delay Time, Low-to-High
Level Output, From A, B, C, or D Inputs
Through 3 Levels of Logic

tpHL

tpLH

Propagation Delay Time, High-to-Low
Level_ Output, From A, B, C, or D Inputs

CL = 15 pF

Through 3 Levels of Logic

RL

Propagation Delay Time, Low-to-High
Level Output, From Either Strobe Input

-tpHL

Propagation Delay Time, High-to-Low
Level Output, From Either Strobe Input
4-34

= 400n

~ Additional Devices

DM93/DM8311

Logic Diagram

r-~

II

C

0

~I---..

A

H
Gl

;;U

G

G2

(4)

~

INPUTS

~olli

A

T
(22)

A

~~

)oJ!!.

B

T

B

~~

c

(21)

T -V c

~

0
(20)

(5)

..J

C
(23)

(2)

Jo-ill

B

(18)~

(I)

B

.........

~----

(B)
OUTPUTS

(9)

(10)

0

1

h-..

0

(II)

0
~

~

(13)

C

H

(14)

--I

H
B

~---

II

7=

A
B

4-35

c

0

(15)

(16)

(11)

10

11

12

13

14

15

~. Additional Devices

DM93/DM8318

General Description

Features

These TTL encoders feature PriOrity decoding of the
input data to ensure that only the highest-order data line
is encoded. All inputs are buffered to represent one
normalized Series 54/74 load. The DM9318 anq
DM8318 encode eight data lines to three-line (4-2-1)
binary (octal). Cascading circuitry (enable input E1 and
enable output EO) has been provided to allow octal
expansion without the need for external circuitry_
For all types, data inputs and outputs are active at
the low logic level.

•

Connection Diagram

.

L6

EO

, . Typical data delay

10 ns

• Typical power dissipation

190 mW

AD

I.

lD

11

12

13

3

•

,

•
. EI

,

,

6

5
A2

A1

18

GNO

H

EI

0

1

2

3

4

5

6

7

A2

Al

AO

GS

EO

H

X

X

X

X

X

X

X

X

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

L

L

X

X

X

X

X

X

X

L

L

L

L

L

X
X

X

X

L

H

L

H

L

X
L

L
H

H

H

L
.L

H
H

H

H

H

L

H

L
H

L
L

H

L

L
L

H

H.

H

H

L
L

L

X

X

X

L
L

X
X

X
X

X
X

L
L

X

X

X

H

H

H

H

X

L

L
H

H

X

H

H

H

H

H

L

X

L

H

H

H

H

H

H

H

L
L
H

L

L

H

H

H

H

H

H

H

H

H

~

X

High Logic Level, L

OUTPUTS

INPUTS

OUTPUTS

INPUTS

9

0-

2

Encodes 8 data lines to 3-line binary (octal) .

• Applications include:
N -bit encodi ng
Code converters and .generators

OUTPUT

-C

1

•

Ir,lPUTS

GS

15

Direct replacement for Fairchild 9318

• Pin for pin with popular DM54148174148

Truth Table

OUTPUTS
Vee

Priority Encoders

9318(JI, (W); 8318(JI, (N), (W)

LogiC Diagram

INPUTS

4-36

~

Low Logic Level, X

~

Don't Care

L

H

H
H

~

Additional Devices

DM93/DM8318

Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER

DM93/83
18

CONDITIONS
MIN

V ,H

High level Input Voltage

V,L

Low Level Input Voltage

V,

Input Clamp Voltage

IOH

High Level Output Current

VOH

High Level Output Voltage

MAX
V

2
0.8
Vee = Mm,'1

IOL

Low Level Output Current

VOL

Low Level Output Voltage

==

V

-1.5

-12 rnA

V

-800

,

I,

Input Current at MaXimum Input Voltage

I'H

High Level Input Current

o Input
Others

o Input

Low Level Input Current

I,L

UNITS

TVP(lI

Others

Vee'" Min,

V 1H = 2V

V 1l == O.BV,

10H

Vee = Min,

V 1H ==

2\1

V,L "0.8V,

tOL =

16 rnA

Vee = Max,

V, o5.5V

"-800I1A

Vee:: Max,

V, "2AV

Vee"" Max,

V, "OAV

los

Short Circuit Output Current

Vee

Icc

Supply Current

Vee"= Max

~

Max(2)

(3)

IlA

2.4

V
16

mA

0.4

V

1

mA

40

IlA

80
-1.6

mA

-3.2
-85

-35

I Condition 1
I Condition 2

mA

40

60

35

55

mA

Notes
(1)

All typical values are at Vee = 5V, TA = 25°e.

(2)

Not more than one output should be shorted at a time.
ICC (condition 1) is measured with inputs 7 and El grounded, other inputs and outputs open; ICC (condition

(3)

?)

is measured with all inputs

and outputs open.

Switching Characteristics

vee

PARAMETER

= 5V, T A = 25°C
FROM
(INPUT)

DM93/83

TO
(OUTPUT)

WAVEFORM

CONDITIONS

"'LH

Propagation Delay Time, Low-toHigh Level Output
o thru 7

tPHL

Propagation Delay Time, High-to-

tpLH

Propagation Delay Time, Low-to-

A, B, C, D

High Level Output

o thru 7

A, B,C, D

Propagation Delay Time, High-to-

o thru 7

EO

Propagation Delay Time, Low-toHigh Level Output

tpHL

PropagatIon Delzy Time, High-to-

tPLH

Propagation Delay Time, Low-to-

o thru 7

GS

In-Phase Output

Low Level Output

High Level Output
EI
tPHL

AO, Al, or A2

Propagation Delay Time, High-ta-

Propagation Delay TimEl, Low-toHigh Level Output
EI

"'HL

GS

Propagation Delay Time, High·to-

Propagation Delay Time, Low-taHigh Level Output

tpHL

9

14

ns

13

19

ns

12

19

ns

G

9

ns

14

21

ns

18

27

ns

14

21

ns

10

15

ns

la

15

ns

8

12

ns

10

15

ns

EI

EO

la

15

ns

17

26

ns

CL =15pF
R L = 400n

In-Phase Output

Low Level Output
""-H

ns

In-Phase Output

Low Level Output
tpLH

15

Out·of-Phase Output

Low Level Output
tPLH

10

Propagation Delay Time, Low-toHigh Level Output

tpHL

MAX

Out-of-Phase Output

Propagation Delay Time, High-toLow Level Output

"'LH

TVP

In-Phase Output

Low Level Output

tPHL

UNITS

18
MIN

In·Phase Output

Propagation Delay Time, High-toLow Level Output

4-37

~ Additional Devices

DM93/DM8322
Quad 2-Line to 1-Line Data Selectors/Multiplexers

General Description

Applications

These data selectors/multiplexers contain inverters and
drivers to supply full on-chip data selection to the four
output gates. A separate strobe input is provided. A
4-bit word is selected from one of two sources and is
routed to the four outputs. True data is presented
at the outputs.

• Expand any data input point
• Multiplex dual-data buses
• 'Generate four functions of two variables (one variable
is common)
,

Features

• Source programmable counters

• Direct replacement for Fairchild 9322
• Pin-for-pin with popular DM54157/74157
• Buffered inputs and outputs

Truth Table

Connection Diagram

.

INPUTS
Vee

STROBE

1,6

A4

"

INPUTS
OUTPUT

84

V4

13

14

OUTPUT
A3

BJ

11

12

VJ

10

9

OUTPUT

INPUTS
STROBE

SELECT

A

B

Y

H

X

X

X

L

f

-

r-

L

L

L

X

L

L

L

H

X

H

L

H

X

L

L

L

H

X

H

H

H = High Level, L = Low Level,X= Don't Care
2

1
SELECT

4

3

AI

81

Yl

6'

5
A2

82

OUTPUT
INPUTS

7
V2
OUTPUT

1

8

GND

INPUTS

9322(J), (W); 8322(J), '(N), (W)

Logic Diagram
AI 121

81 131

A2 151

82 161

A3 1111

83 1101

A4 1141

84 1131

4-,38

~

DM93/DM8322

Additional Devices

Electrical Characteristics over recommended operating free~air temperature range (unless otherwise noted)

DM93
PARAMETER

CONDITIONS
MIN

VIH

High Level Input Voltage

Vil

Low Level Input Voltage

VI

Input Clamp Voltage

~

1---

Vee == Min,

High Level Output Current

VOH

High Level Output Voltage

10l

22
MAX

-- c-----Vcc=Min,

0.8V,

10H

~

Vcc==Mm,

V IH

=

2V

V'L - O.8V,

IOL

=

16 mA

V'L

r-Low Level Output Current

~

V'H ~ 2V
-800/-lA

2,4

MIN

UNITS

TVPll)

MAX

2

I, """ ·-12 mA

_....

VOL

TVPll)

2

IOH

---

DM83

22

V

0.8

0.8

-1.5

-1.5

V

-800

-800

/-lA

3,4

2,4

3,4

V

16

Low Level' Output Voltage

II

Input Current at Maximum Input Voltage

Vee = Max,

V,

IIH

High Level Input Current

Vee = Max,

III

Low Level Input Current

Vee::: Max,

los

Short Circuit Output Current

Vec

~

Max(2)

Icc

Supply Current

Vee

~

Max(3)

~

0.2

5.5V

0,4

V

0.2

16

mA

0,4

V

1

1

V, - 2.4V

40

40

/-lA

V,~O.4V

~1.6

~-L6

mA

·20

55
30

-·18

48

mA

-55

mA

48

mA

30

Notes
All typical values are at Vee = 5V. T A = 25° C.
(2)
Not more than one output should be shorted at a time.
(3) ICC is measured with 4.5V applied to all inputs and all outputs open.

(1)

Switching Characteristics

vee ~

5V, TA ~ 25 c C

DM93/83
PARAMETER

FROM (INPUT)

22

CONDITIONS
MIN

tplH

Propagation Delay Time,
Low-to-High Level Output

TVP

UNITS
MAX

8

14

ns

10

14

ns

13

20

ns

14

21

ns

15

23

ns

17

27

ns

Data
tpHl

Propagation Delay Time,
High·to~Low

tplH

Level Output

Propagation Delay Time,
Low-to-High Level Output
Strobe

tpHl

Propagation Delay Time,
High~to~Low

tplH

CL = 15 pF, RL = 40011

Level Output

Propagation Delay Time,
Low~to~High

Level Output
Select

tpHl

Propagation Delay Time,
High·to~Low

Level Output
4~39

~ Additional Devices

DM93/DM8334
8-Bit Addressable Latches

General Description
all outputs are low and unaffected by the address and
data inputs.

The DM9334/DM8334 is a high speed 8-bit Addressable
Latch designed for general purpose storage applications
in digital systems. It is a multifunctional device capable
of storing single line data in eight addressable latches,
and being a one-of-eight decoder and demultiplexer
with active level high outputs. The device also incorporates an active level low common clear· for resetting
all latches, as well as an active level low enable.

When operating the device as an addressable latch,
changing more than one bit of the address could impose
a transient wrong address. Therefore, this should only
be done while in the memory mode.
The truth table below summarizes the operation of the
product.

The DM9334/DM8334 has four modes of operation
which are shown in the mode selection table. In the
addressable latch mode, data on the data line (D) is
written into the addressed latch. The addressed latch
will follow the data input with all non-addressed latches
remaining in their previous states. In the memory mode,
all latches remain in their previous state and are
unaffected by the data or address inputs.

Features

•
•
•

Direct replacement for Fairchild 9334
Common clear
Easily expandable
Random (addressable) data entry
Serial to parallel capability
8 bits of s~orage/outPut of each bit available
Active high demultiplexing/decoding capability

In the one-of-eight decoding or demultiplexing mode,
the addressed output will follow the state of the D input
with all other inputs in the low state. In the clear mode

•
•
•
•

Truth Tables

Connection Diagram

vr

c

E

C

MODE

L

H

Addressable Latch

H

H

Memory

L

L

Active High EightChannel Demultiplexer

H

L

Clear

E

"

16

.6

07

0

"

O.

0'
10

11

11

13

,

r--

X = Don't Care Condition
L = Low Voltage Level

,

H = High Voltage Level

0N-1 "" Previous Output State

AD

1
A1

J

,

4

.,

00

,
02

0'

7
OJ

J;

9334/8334(J), IN), (W)

INPUTS

PR ESENT OUTPUT STATES

C

E

D

AO

A1

A2

00

01

02

03

04

05

06

07 .

L

H

X

X

X

X

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

H

L

L

L

H

L

L

L

L

L

L

L

L

L

L

H

L

L

L

L

L

L

L

L

L

L

L

L

H

H

L

L

L

H

L

L

L

L

L

L

·· ·· ··
· · ·
L

L

H

H

···
H

H

H

H

X

.X

X

X

H

L

L

L

L

L

L

ON_'

ON_1

H

ON_l

ON-1

H

L

H

L

L

L

H

L

L

H

L

L

H

L

H

H

L

L

··· ··· ···

L

L

L

··
·
L

DEMUL TIPLEX

L

L

L

°N_1

ON_'

L

ON_'

ON_,

H

°N_1

H

L

L

H

···
H

H

°N-1

H

L

H

H

H

H

ON_'

···

H

.

..
.

°N_'

MEMORY

~

ADDRESSABLE
LATCH

.
~

4-40

MODE
CLEAR

ON_'
ON_'

L
H

~

Additional Devices

Electrical Characteristics

DM93/DM8334

over recommended operating free-air temperature range (unless otherwise noted)
DM93/83

PARAMETER

34

CONDITIONS
MIN

V ,H

High Level Input Voltage

V,L

Low Level Input Voltage

V,

Input Clamp Voltage

10H

High Level Output Current

VOH

High Level Output Voltage

10L

Low Level Output Current
Low Level Output Voltage

UNITS
MAX

2

V
V

0.8

Vee

= Min,ll

= -12 mA

-1.5
-800

Vee

= Min, V 1H " = 2V

2.4

V ,L = 0.8V, IOH = -aOOfJA

VOL

TYPO)

rnA

0.2

0.4

V

E Input

15

60

Others

10

40

E Input

-1.44

-2.4

Others

-{J.96

-1.6

--65

-100

rnA

86

rnA

V ,L = 0.8V,I·OL = 16 rnA
Input Current at Maximum Input Voltage

I'H

High level Input Current

I,L

Low Level Input Current

Vee

= Max,

VI

= 5.5V

Vee = Max, VI = 2.4V

Vee

= Max,

VI

los

Short Circuit Output Current

Vee = Max(2)

Icc

Supply Current

Vee

= D.4V

V

3.6
16

Vee:;;' Min, V 1H = 2V

I,

V
fJA

1

-30

= Max

56

rnA
fJA

rnA

Notes
(1)
(2)

All typical values are at VCC

= SV, T A =2SoC.

Not more than one output should be shorted at a time, and duration of short circuit should not exceed one second.

Switching Characteristics Vee

= 5V, T A

= 25°C
DM93/83

PARAMETER

FROM

TO

CONDITIONS

34
MIN

Propagation Delay Time.

tpLH

low-ta-High level Output
Enable
Propagation Oelay Time.

tpHL

(Figure 1)

Propagation Delay Time,
low·to-High level Output
Data
Propagation Delay Time,

tpHL

(Figure 2J

Propagation Delay Time,
low-to-High Level Output

Output

CL =15pF

/Figure 3)

RL = 400fl

Address
Propagation Delay Time,

.... L

High-to-low level Output
Propagation, Delay Time,

tpHL

low-to-High Level Output

Clear

Output
(Figure 5J

Enable Pulse Width

tw

tHOLD

28

ns

18

27

ns

24

35

ns

19

28

n,

23

35

ns

21

35

ns

21

31

ns

ns

19

13

High Data to Enable (Figure 4)

20

13

low Data to Enable (Figure 4)

20

14

Address to Enable(3) (Figure6J

10

5

High Data to Enable (Figure 4)

0

-10

ns

low Data to Enable (Figure 4)

0

-13

ns

(Figure 1)
tSETUP

19

Output

High-to-Low Level Output
tpLH

MAX

O,utput

High-to-low level Output
tpLH

UNITS

TYP

ns

Notes
(3)

The Address to Enable Set-Up Time is the time before, the High-ta-Low Enable transition that the Address must be stable so that the correct
latch is addressed and the other latches are not affected.

4-41

~ Additional Devices

DM93/DM8334

Logic Diagram

Switching Time Waveforms

OTHER CONDITIONS: E" l. C = H, A '" STABLE
OTHER CONDlTI.ONS: C '" H, A '" STABLE

FIGURE 1

FIGURE 2

tpHL

Al

AI

01

1.5V

OTHER CONDITIONS: E" l, C '" L, 0 = H

OTHER CONDITIONS: C = H, A = STABLE

FIGURE4

FIGURE 3

OTHER CONDITIONS: C'" H

OTHER CONDITIONS: E"" H

FIGURE 5

FIGURE 6

Note. The shaded areas indicate when the inputs are permitted to change' for predictable 'Output performance.

4-42

~ Additional Devices

DM96/DM8601
Retriggerable One Shots
Features

General Description
These retriggerable one shots provide the designer with
four inputs; two active high and two active low. This
permits a choice of either leading-edge or trailing-edge
triggering, independent of input transition times. When
input conditions for triggering are met, a new cycle
starts and the external capacitor is rapidly discharged
and then allowed to charge again_ The retriggerable
feature allows for output pulse widths to be expanded.
In fact a continuous true output can be maintained by
having an input cycle time which is shorter than the
output cycle time. Retriggering may be inhibited by
tying the Q output to an active low input.

• High speed operation-input repetition rate> 10M Hz
•

• Output pulse width range-50 ns to
•

ex

R)(

81

•

Input clamping diodes

•

DTLITTL compatible logic levels

I

v"

.2

Leading or trailing edge triggering

Truth Table

r"Nv-r---II--- r

A1

~

• Complementary outputs/inputs

Connection Diagram
I

Flexibility of operation-optional retriggering/lockout capability

"

OUTPUTS

INPUTS
NO

Nt

NO

GND

9601/8601(J), (N), (W)

Schematic Diagram
{1J}

(11)

4-43

A1

A2

B1

B2

a

a

H

H

X

X

L

H

X

X

L

X

L

H

X

X

X

L

L

H

L

X

H

H

L

H

L

X

t

H

..fL

-u-

L

x

H

t

5L

-U-

x

L

H

H

L

H

X

L

t

H

_n...

-U-U-U-U-U-

x

L

H

t

..fL

H

I

H

H

..fL

I

I

H

H

..fL

I

H

H

H

..fL

~. Additional Devices
Electrical Characteristics

DM96/DM8601

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN
V'H

DM96

DM86

01

01

CONDITIONS

High Level Input Voltage

T A =-55"C

TYP(1)

MAX

MIN

MAX

1.9

= 25°C
T A = 75°C
TA = 125°C
TA

Low Level Input Voltage

TYPllI

2.0

TA = O°C

V'L

,
UNITS

1.7.

1.8

V

1.6
1.5

TA =-55°C

0.85

TA = O°C

0.85

TA = 25°C

0.90

0.85

TA = 75°C
TA = 125 C
V,

Input Clamp Voltage

10H

High Level Output Current

VOH

High Level Output Voltage

10L

Low Level Output Current

Vee = Min, I,

0.85

=-12 mA

-1.5

-1.5

V

-720

-960

/J.A

,12.8

mA

2A

Vee == Min, IOH == Max

2A

V

10

= Max

VOL

Low Level Output Voltage

Vee = ,Min.

"H

High Level Input Current

Vee = Max, V, = 4.5V

"L

Low Level Input Current

Vee

= Max

IOl

I
I

los

Short Ci fcuit Output Current

Vee

= Max(2)

Icc

Supply Current

Vee

= Max

V,
V,

V

0.85

OAO
15

=OAOV
= 0.45V

0.45

60

15

V

60

/J.A

-1.6

mA

-1.6

'-10

-10

-40

-40

mA

25

mA

25

Notes
11) All typical values are at VCC = 511, TA = 25°C.
12} Not more than one output should be shorted at a time.
13} ·Unless otherwise specified, RX = 10 k.n between Pin 13 and VCC on all tests.
14} Ground Pin 11 for VOL test on Pin 6, VOH test on Pin 8 and 'OS test on Pin 8. Open Pin 11 for VOL test on Pin 8, VOH test on Pin 6 and
lOS test on Pin 6,

Switching Characteristics vee

=;

5V, T A'" 25°C
DM96
CONDITIONS

PARAMETER

MIN
tpLH

tpHL

Propagation Delay Time,

Negative Trigger Input

Low-to-High Level Output

to True Output

PropagatiQn Delay Time,
High-to-Low Level Output

. Negative Trigger Input

to Complement Output

CL = 15 pF, Cx = 0
Rx = 5 kU

!pw 1M',,!' Minimum True Output
Pulse Width

!PW

Pulse Width

CSTRAY

Maximum Allowable
Wiring Capacitance

Rx

~xternal

Rx = 10 kn, ex = 1000 pF

3.08

Timing

01
MAX

40

25

40

ns

25

40

2p

40

ns

45

65

45

65

ns

3_42

3.76

3.42

3.76

/J.s

50

pF

MAx

25

MIN

5

UNITS

TYP

TYP

3.08

50

Pin 13 to GND

Resistor

DM86

01

25

5

50

kO

--4-44'

~ Additional Devices

DM96/DM8601

Operating Rules
noise pickup. If remote trimming is required, Rx may
be split up such that at least RX(MIN) must be as
close as possible to the circuit and the remote portion
of the trimming resistor R< RX(MAX) - Rx.
4. Set·up time (t,) for input trigger pulse must be
> 40 ns. (See Figure 1).
Release time (t2) for input trigger pulse must be
> 40 ns. (See Figure 2).
5. Retrigger pulse width (see Figure 3) is calculated
as follows:

1. An external resistor Rx and an external capacitor
C x are required for operation, The value of Rx can
vary between the limits shown in switching charac·
teristics. The value of Cx is optional and may be
adjusted to achieve the required output pulse width.
2. Output pulse width tpw may be calculated as follows:

tpw = 0.32 RxCx [1 +

~.~] (for Cx ;:::10

3

pF)

Rx in kn, Cx in pF and tpw in ns.
(For C x < 103 pF, see curve.)
3. R x and Cx must be kept as close as possible to the
circuit in order to minimize stray capacitance and

2.5V

J"~
L5V

VIN

1.5V

tw

=tpw + tpLH =0.32 RxCx

~

'

1.5V

2.5V

1.5V

[ + 0.7]
1

Rx

"."~
D OUTPUT

VON

FIGURE 1

FIGURE 2

FIGURE 3

Typical Performance Characteristics
OUTPUT PULSE WIDTH VS
TIMING RESISTANCE AND
CAPACITANCE FOR

ex < 103pF
::c

NORMALIZED OUTPUT
PULSE WIDTH VS AMBIENT
TEMPERATURE
1.10 .-,----r-,.-.,--r--.---,

vee '" 5.DV

f-~+-+':'-'+-+Rx '" 10k
'\
Cx =10'pF

i;
iii

.~

~
!:;

~

"

~
~

""

I-+---l'-,,'-+-+-+-"T-t'-l

1.05

~

1.00 I-+--+--l-::;;o-l""+-+-t---l

I-+-+-+-+-+--+"~I.I'...--l

0.95 1"/-+-f-+-+--+-1-+--I

0.95

I '"

TA "'2SoC

-75

2.

-25

75

125

SUPPLY VOLTAGE (V)

v~ ••.bv

]

~

S
i

f-t-+-~-+-+~~~

~

1.0'

1-+-+-1-+--1--+-1""'1

~ 12 1-+--+--+-+-..."../'4-+--1

0.8

I-+--+-f-+-+--+-/--l

;;

OPERATING DUTY CYCLE (%)

./

~

~

OUTPUT PULSE WIDTH VS
AMBIENT TEMPERATURE

I-+-+--t-+-+ ex '" 103pF
16

iii

0.6 '--'--'-_'---'--L........_l..-.I
20
60
80'
100
40

0.90 '-..L....L--'_.l.--L...-'_.L-..J
4.5
5.0
5.5
6.0
4.0

0.90 '---'---'--'_.l.--L........_l..-.I

PULSE WIDTH VS TIMING
RESISTANCE
20 .-,,-"--,--,.-.,---r-,.-,.......,

1.' .---r--'--'r-,---r-r-,.--,

I-+--+-f-+-+'Cx '" 103 pF

VI-"'"

T A - AMBIENT TEMPERATURE (OC)

NORMALIZED OUTPUT
PULSE WIDTH VS
OPERATING DUTY CYCLE

1.2

-~I-'"'

'\

1.00 I-+-+--+-"'"rlf-+--+---l

ex. TIMING CAPACITANCE (pFl

f--+-+---""f-+-+ ~~:,~:V

NORMALIZED OUTPUT
PULSE WIDTH VS SUPPLY
VOLTAGE

L

B.O 1-+--ti"-:71~+--t--t--+--I

/
10

20

30

40

50

Rx - EXTERNAL TIMING RESISTANCE (on)

4·45

70 f--+-+--1-+-+-""t--'-r--:I

~

~

.!!i
z

~

COMPLEMENTARY OUTPUT

I

:0

;;

4.0

90 r---r--+~-,----r~v~cc-=~5~.D~V'
1-+--+--1-+-+ Rx = 5.Dk
ex = 0

50

1-+--+-1C-+--:T"'R'C'UE"'O"'U=Ti-:pU=T,-l

30 f--+-+--1i---+-+-j-+--l
10

L--'--'-~~~-L--'

-75

-25

25

__~~

75

TA - AMBIENTTEMPERATlJRE 1°C)

125

~ Additional Devices

DM96/DM8602
Dual Retriggerable, Resettable One Shots

. General Description
These dual resettable, retriggerable one shots have two
inputs per function; one'which is active high, and one
which is active low. This allows the designer to employ
either leading-edge or trailing-edge triggering, which is
independent of input transition times. When input con·
ditions for triggering are met, a new cycle starts and the
external capacitor is allowed to rapidly discharge and
then charge again. The retriggerable feature permits
output pulse widths to be extended. I n fact a continuous
true output can be maintained by having an input cycle
time which is shorter than the output cycle time. The
output pulse may then be terminated at any time by
applying a low logic level to the RESET pin. Retriggering

may be inhibited by either connecting the Q output to
an active high input, or the Q output to an active
low input.

Features
•
•
•
•
•
•

Connection Diagram
vee
16

Truth Table
Q

CD
. 15*

70 ns to 00 output width range
Resettableand retriggerable-O% to 100% duty cycle
TIL input gating-leading or trailing edge triggering
Complementary TIL outputs
Optional retrigger lock·out capability
Pulse width compensated for V cc and temperature
variations

Ii

14*

PIN NO'S.
5(11)

4(12)

H~L

H
X

'

3(13)

OPERATION

L

H

Trigger

L~H

H

Trigger

-X

L

Reset

H = High Voltage L 40 ns
Min. Negative Input Pulse Width> 40 ns

2.5V

2.5V

INPUT

OOUT'U:V~
Input to Pin 4 (12),
Pin 5 (11) ~ HIGH
C.

Use to obtain extended pulse widths:
This configuration can be used to obtain ex·
tended pulse widths, because of the larger
timing resistor allowed by beta multiplication.
Electrolytics with high inverse leakage currents
can be used.
R < Rx (0.7) (h FE 01) or
ever is the lesser

(Pin 3 (13)

~

HIGH)

8. The retriggerable pulse width is calculated as shown
below:
tw

< 2.5 MQ, which·

~ t + tpLH ~ 0.31

Rx Cx (1 + R1x) + tpLH

INPUT~_ _~n
I--~tw-,--'-1- - -

Rx (min) < Ry < Rx (max)
(5 kQ S Ry S 10 kQ is recommended)

Q OUTPUT

4·48

---1

LI_ __

~ Add itional Devices

DM96/DM8602

Operating Rules (Continued)
The retrigger pulse width is equal to the pulse width
(t) plus a delay time. For pulse widths greater than
500 ns, tw can be approximated as t. Retriggering
will not occur if the retrigger pulse comes within ""
0.3 ex (ns) after the initial trigger pulse. (j.e., during
the discharge cycle).

INPUT

'--------',

RESET

o OUTPUT

PULSE
I-WIDTH-j
t

n OUTPUT

.9. Reset Operation - An overriding clear (active LOW
level) is provided on each one shot. By applying a
LOW to the reset, any i:iming cycle can be terminated
or any new cycle inhibited until the LOW reset
input is removed. Trigger inputs will not produce
spikes in the output when the reset is held LOW.

10. Vee and Ground wiring should conform to good
high frequency standards so that switching transients
on Vee and Ground leads do not cause interaction
between one shots. Use of a 0.01 to O.l/-lF bypass
capacitor between Vee and Ground located near
the DM9602/DM8602 is recommended.

Typical Performance Characteristics
1.10

.-,.....,...-.,-r-...,..~--,""

::!:

Vee '" 5.DV

l;

f-++-\-t--+R x =10kn

i

i
..... Rx =30k
1Rx.- 20k
Rx'" 10k

~

i

1.00 f-++-\"'-.,...:!!'k::::lL-+--i!--1

~

~

-25
TA

-

25

75

'25

AMBIENT TEMPERATURE (OC)

10

Rx'" 10 kG

1.00

20

FIGURE 2. NORMALIZED
OUTPUT PULSE WIDTH VS
AMBIENT TEMPERATURE

+--+-4-+---+-1

I

I--f-I--I-V"*/'-+-'-+---+--I

COMPLEMENTARY OUTPUT./

V

0.90 L-...o....--l..--'_.!.......l..-'-_'--'
4.0
4.5
5.0
5.5
6.0

60
-75

Vee -SUPPLY VOLTAGE (V)

-25

25

75

TA - AMBIENT TEMPERATURE (·CI

FIGURE 4. NORMALIZED
OUTPUT PULSE WIDTH VS
SUPPLY VOLTAGE

FIGURE 5. MINIMUM
OUTPUT PULSE WIDTH VS
AMBIENT TEMPERATURE

4-49

30

4U

FIGURE 3. PULSE WIDTH
VS TIMING RESISTOR

Cx =1tJ3pF

0.95 - '

/

50

Px - EXTERNAL TIMING RESISTOR (nl

1.10 r-:"T~A-=2=5"'.C-'-"''''''--'-'--'

1.05

v

~~~---1-t--+-+---+---1~
2

10>

/

L

co

Cx - TIMING CAPACITANCE (pFi

FIGURE 1. OUTPUT PULSE
WIDTH VS TIMING RESISTANCE AND CAPACITANCE
FOR C x < 103 pF

10

\;

1-+-+-4-+---+---+-f-i

I

14

=>

r-

~ 0.95

10'

10

~

Cx "'103 pF

1-+'-P"'-:l-+---+---+---1f-i

1.05

C>

II

I I

~

18

125

Notes

Notes

National Semiconductor Corporation . 2900 Semiconductor Drive . Santa Clara, CA 95051
© 1976 Natlonal Semiconductor Corp,

Printed in U,S,A,



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