1977_Bipolar_Microprocessor 1977 Bipolar Microprocessor

User Manual: 1977_Bipolar_Microprocessor

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Expand your present 8080A based system, yet use
all of the software you've developed, with the Signetics
8080A Emulator. Built with the 3001/3002 bipolar bit
slice microprocessor, the emulator executes all 8080
instructions at speeds from 2 to 9 times faster than the
8080, uses a single 5 volt supply, a single phase
clock, and is microprogram expandable.
The emulator kit comes complete with all parts needed
to construct this bipolar replacement for the 8080A,
8228, 8224 and 8212, including preprogrammed
PROMS and p.e. board. The accompanying manual tells
how to build it, how to use it, and gives a thorough
tutorial description of the design and theory of
operation. With this $299 kit you can have 8080A
emulation in 6 hours. Order 3000KT8080SK.

!i!!lDOliC!i

1

Reach for this book anytime you need information on
bipolar microprocessors. The following pages
have everything here for quick easy reference to data
sheets on:
•
•
•
•

Bit Slice Microprocessor
Sequencers
M icrocontroller
Selected I nterface Products

with selection guides and summary data sheets for:
•
•
•
•

Memory Products (including FPLA)
Analog Interface Products
Interface Circuits
System Logic

and references and data sheets on:
• Development Systems
• Development Software

and data sheets on kits and appl ication notes.
Yes, it's all here.

2

9i!1DOliC9

Signetics is the total memory supplier. To meet the
needs of microprocessor users and system designers,
Signetics offers a complete line of memory products.
Here are a few examples:
• Bipolar and Static MOS RAMS
Bipolar 8 to 1024 bits, access times to 35ns
MOS Static 256x4 to 4096x1~ access time to 85ns
• Dynamic MOS RAMS
To 16Kx1
• Bipolar and MOS ROMS and PROMS
Bipolar and MOS Static ROMS to 16K bits
Bipolar PROMS to 16K bits*
MOS EROMS* to 8 K bits
Character Generators
• Bipolar FPLA/PLA
• Bipolar CAMS and Register Files

Selection guides are provided in the Bipolar
Microprocessor book. For more information send for the
full list of total MOS and bipolar memory line.
*Available 1st quarter 1977

!ii!lDOliC!i

3

Complete with the 8X300, clock crystal, 4 I/O ports, 256
bytes of working storage, 512 words of program
storage, and P.C. board with wire wrap area, the kit is
ready to be used as a basic starter system for your own
controller design. There are 450 empty PROM locations
that can be used to hold the program for your
controller using this, the industry's first high speed
(Schottky) complete 8-bit microprocessor. The
remaining 62 locations contain diagnostics which can be
used to check out the board or monitor the 8X300
through Single Step and_lnstructidn Jam features of this
kit. This $299 kit is a fast, inexpensive way to get started
with the 8X300. Order 8X300KT100SK.

4

!ii!lDOliCS

Making your microprocessor system do its job requires
interface to the outside world. Signetics Analog
Interface products link your microprocessor to displays
and sensors. Here are a few examples:
• Peripheral Interface
Drivers to 80 volts (DS3611 series-UDN5711 series)
Line Receivers and Drivers
• Display Interface
Display Decoder/Drivers to 100 volts-DM8880/-1
NE584, NE585, NE582
• D/A Converters to 8 bits
MC1408-8, NE5008/9
• Comparators
NE521/522, LM111/211/311, LM119/219/319,
LM139/239/339, LM193/293/393
• Timers
N E553/554/555/556

plus an assortment of popular voltage regulators, phase
locked loops, amplifiers and other specialized circuits.
Selector guides are provided in the Bipolar
Microprocessor book. For more information send for
Signetics Analog manual for data sheets and
appl ication notes.

!iI!lDOliC!i

5

An easy way to get a complete set of parts for a bit
slice microprocessor is with this kit of parts. An 8-bit
processor can be constructed using the four 3002's with
microcontrol provided by the 3001 and two 828114's
contained in the kit. In addition you get two 8T26A bus
transceivers and an 8T31 bidirectional I/O ports to
round out the parts complement. For your start in bit
slice microprocessors, get this $230 value with data
book for $100. Order 3000KT100SK.

6

9!!1DOIIC9

Development of complicated microprocessor based
systems and controllers can be difficult, but with the
help of appropriate support systems the work can be
considerably eased. Signetics presents its own as well
as commercially available support products for the new
Bipolar Microprocessor book. Send for one on your
company letterhead today. We'll tell you about the
8X300 Microcontroller Simulator, PROM Programmers,
FPLA Programmers, the Cross Assembler and other
aids for system development that will be invaluable to
you in both time and money.

9!!1DOliC9

7

Signetics "Answermen" are there to solve your
problems not just sell you a microprocessor.
Microprocessor Application Specialists, 9 in all, located
in strategic parts of the country serve customers in all
corners of the continental United States. Well versed in
Signetics MOS, bipolar bit slice and bipolar
microcontroller microprocessors through regular
intensive factory training, these "Answermen" have no
limit in technology they may draw upon to provide you
with a cost effective approach to your task. They may
suggest the 2650, the 3002, the 2901-1 or the 8X300 in
combination with System Logic, Interface and support
circuits in an architecture that can do the job with the
least cost. And for more difficult problems, the
"Answermen" may draw on the factory staff of application
experts. Call an "Answerman" for a discussion of your
specific needs or for a seminar on the Signetics
product line. "Answermen" are located in:
Sunnyvale
Irvine
Minneapolis

8

Boston
New York
Philadelphia

Los Angeles
Pompano Beach
Dallas

9!!1DOliC9

TAIII or conTlnTS

Chapter 1 BIPOLAR BIT SLICE FAMILy................................................................... 11
Introduction ............................................................................................. 13
8X02 Control Store Sequencer Data Specifications..... . .. . . ... .. .. .. ..... ........ ........ ....... .... ......
14
3000 Series Data Specifications ........................................................................... 20
SN3001 Microprogram Control Unit..................................................................... 23
SN3002 Central Processing Element .................................................................... 31
Kits
3000KT1000 Designer's Evaluation Kit................................................................... 40
3000KT8080SK 8080 Emulator Kit ......................................................................... 42
Microassembler ........................................................................................ 44
Chapter 2 BIPOLAR FIXED INSTRUCTION MICROPROCESSOR ........................................... 45
Introduction ............................................................................................. 47
8X300 I nterpreter Data Specifications ..................................................................... 48
8X300AS100SS MCCAP 8X300 Cross Assembler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Peripheral Circuits
8T32/33/35/36 8-Bit Latched Addressable Bidirectional I/O Port Data Specifications ...................... . 60
8T39 Bus Expander Data Specifications ................................................................ . 67
Kits
8X300KT100SK Designer's Evaluation Kit for Fixed Instruction Bipolar Microprocessor ................... . 71
Support Software ....................................................................................... . 73
Chapter 3 STANDARD SUPPORT CIRCUITS ............................................................. . 75
Introduction ............................................................................................ . 75
Memories
Memory Product Summary ............................................................................ . 77
I nterface Log ic
Interface Product Summary ........................................................................... . 79
8T15 Dual EIA/Mil Line Driver ......................................................................... . 83
8T16 Dual EIA/Mil Line Driver with Hysteresis .......................................................... . 85
8T26A/28 Tri-State Quad Bus Receivers ................................................................ . 88
8T31 8-Bit Bidirectional I/O Port ....................................................................... . 91
8T34 Tri-State Quad Bus Transceiver .................................................................. . 94
8T95/96 Tri-State Hex Buffers ......................................................................... . 96
8T97/98 Tri-State Hex Inverters ........................................................................ . 96
Logic
54174 Series TTL Product Summary .................................................................... . 99
8200 Series TTL Product Summary .................................................................... . 102
Logic Function Selector Guides ....................................................................... . 103
System Logic
Introduction .......................................................................................... . 111
8X01 CRC Generator Checker ......................................................................... . 113
8X08 Frequency Synthesizer ............ " ............................................................. . 116
Analog
Analog Product Summary ............................................................................. . 121
Chapter 4 APPLICATIONS ............................................................................... . 123
3000 Series Microprocessor ............................................................................. . 125
AH1 A Guide to the Selection of Support Components for the Series 3000 Microprocessor ............... . 126
MP1 A User's Guide to the Series 3000 Microprocessor ...... '" ........................................ . 130
MP2 How to Design with the Control Store Sequencer 8X02 ............................................ . 142
8X300 Microcontroller
AH3 Input/Output Design ............................................................................. . 147
AH4 8X300 Applications .............................................................................. . 149
MP3 Understanding the 8X300 Instruction Set .......................................................... . 164
SP1 The 8X300 Cross Assembly Program .............................................................. . 171
8X300 A Fast Microprocessor for Control Applications .................................................. . 178
Chapter 5 DEVELOPMENT SYSTEMS AND PROGRAMS .................................................. . 185
Introduction ............................................................................................ . 187
Compatible Products .................................................................................... . 187
Chapter 6 MILITARy ..................................................................................... . 189
Introduction ............................................................................................ . 191
Microprocessor Support Circuits ......................................................................... . 194
Military Memories .................................. ~ .................................................... . 195
Military LogiC ........................................................................................... . 196
Military Analog ......................................................................................... . 199

!i!!lDotiC!i

9

10

S!!)DotiCS

OIIAPTIR I
IIPOIAR liT
11101 rAmiiT

!i!!lDotiC!i

11

12

9i!1DOliC9

BIT-SLICE MICROPROCESSOR SERIES
M icrocontrol and
Arithmetic Units
The introduction of the Signetics Bit-Slice
Microprocessors has brought new levels of
high performance to microprocessor applications not previously possible with MOS
technology. Combining the Schottky bipolar microprocessors with industry standard
memory and support circuits, microinstruction cycle times of 100ns are possible.
In the majority of cases, the choice of a
bipolar microprocessor slice, as opposed to
an MOS device, is based on speed or flexibility of microprogramming. Starting with
these characteristics, the design of the Signetics slice microprocessors has been optimized around the following objectives:
• Fast cycle time
• All memory and support chips are industry
standard
• Cooler operation
• Lower total system cost

Furthermore, systems built with large-scale
integrated circuits are much smaller and
require less power than equivalent systems
using medium andlor small scale integrated
circuits.
Typically, slice microprocessors are employed in the realization of the Central Processing Unit (CPU) of a computer or for
implementing dedicated smart controllers.
The generalized and simplified structure of
a CPU or "Smart" controller can be typically
classified into 3 distinct but interactively
related functional sections. These sections
are generally referred to as the Processing
section, the Control section, and the liD and
Memory Interface section. A simplified
block diagram of a CPU is illustrated in
Figure 1.
The major functions of the Processing section are to:
•
•

provide data transfer paths;
manipulate data through logic and arithmetic
operations;
• provide storage facilities such as a register file;
and
• generate necessary status flags based on the
kind of operation performed by the ALU.

The major functions of the Control section
are to:
• initiate memory or I/O operations;
• decode macroinstructions;
• control the manipulation and transfer of data;
• test status conditions; and
• sample and respond to interrupts.

The major functions of the liD and Memory
Interface section are to:
• multiplex data to the proper destination;
• provide bus driving/receiving capability; and
• provide latching capability.

With state-of-the-art bipolar Schottky technology, high-performance microprocessors are designed to perform functions of the
Processing section. Due to the limitation on
the number of pins and chip size, the overall
Processing section is partitioned into several functionally equivalent slices. In today's
bipolar microprocessor market, 2-bit and 4bit slice architecture predominates. Each
architecture type has its uniqueness but, in
general, a slice contains a group of general
purpose registers, an accumulator, specialpurp,ose register(s) ALU and related status
flags. All of these elements constitute the
Processing section of a CPU. The flexibility
of slice components allows the designer to
construct a processing section of any desired width as required by his application.
The Control section of the CPU is more
complex in design. Typically this section
includes the macroinstruction decode logic, test-branch decode, microprogram sequencing logic, and the control store where
the microprogram resides. Aside from the
microprogram, the remaining portion of the
Control section (macroinstruction decode
and test-branch decode and sequencing
logic), does not lend itself to efficient partitioning into vertical slices. This is due to the
random nature of the logic usually found in
the Control section. However, horizontal
functional grouping is possible. For exampie, the macroinstruction decode and testbranch decode logic can now be replaced
by the FPLA (Field Programmable Logic
Array); the random logic traditionally

needed to implement the microprogram
sequencing can now be replaced by the
Microprogram Control Unit; and, of course,
the microprogram can be stored in high
density PROMs or ROMs. Since the designer must define his own microstructure, the
slice microprocessors permit fundamental
optimizations to be made. With slice hardware, the designer may have no macroinstructions at all, placing all of the program in
PROM for dedicated control applications.
Or he may define, as required, any number
of macroinstructions selected specifically
for his particular processor purpose. Various minicomputers and several MOS microprocessors have been emulated using slice
hardware.
The liD and Memory Interface section consists mainly of I/O ports, high power bus
drivers, receivers, and some temporary register storage facilities. Bidirectional and
tri-state devices are the most popular logic
elements for implementing this interface
structure.
Figure 2 shows an LSI approach to the
implementation of the same generalized
CPU structure indicated earlier.
The devices presented in this chapter represent Signetics line of slice microprocessor components. Included is the popular
3000 series Microprogram Control Unit and
the 2-bit slice Central Processing Element.
These Signetics devices feature improved
performance specifications over 3000 series
components available on the general market. Moreover, the unique Signetics XL plastic package design results in significantly
cooler operation of the chip than was previously possible with other plastic package
designs. This section also features the 8X02
Control Store Sequencer. This device may
be used with any TTL compatible slice
processing elements and features extreme
ease of use. The 8 simple, yet powerful,
instructions permit subroutining and looping (using internal stack), unrestricted
jumping, unrestricted conditional branching and conditional instruction skipping.

AN LSI IMPLEMENTATION OF A CPU
CONTROL SECTION

ROM-PROM
(MICROPROGRAM)
82S115

PROCESSING SECTION

"'f)

\.\.

~

A SIMPLIFIED CPU ORGANIZATION

CONTROL
SECTION

PROCESSING
SECTION

oJ

MCU (SEQUENCER)
N3001 OR 8X02

2nd SLICE
N3002
OR
N2901-1

nth SLICE
N3002
OR
N2901-1

_:n

FPLA (FOR DECODE)
82S100/101

~.

I

1st SLICE
N3002
OR
N2901-1

~

\.c

1
1/0 AND MEMORY INTERFACE SECTION

~
1/0 AND MEMORY INTERFACE

8T31 - 8-BIT 1/0 PORT
8T28/8T26A - 4-BIT HIGH DRIVE TRANSCEIVER
8T95 - 98; HEX TRI-STATE BUFFERS

*1

Figure 2

Figure 1

!i!!lDotiC!i

13

tOIlIIOt SIORE SEQ"EUCER

8A"
8X02-Xl,1

OBJECTIVE SPECIFICATION

DESCRIPTION

FEATURES

The Signetics 8X02 is a low-Power Schottky lSI device intended for use in high performance microprogrammed systems to
control the fetch sequence of microinstructions. When combined with standard ROM
or PROM, the 8X02 forms a powerful microprogrammed control section for computers,
controllers, or sequenced logic.

•
•
•
•
•
•
•
•
•
•
•

PIN CONFIGURATION

Low power Schottky process
77ns cycle time (typ)
1024 microinstruction addressability
N-way branch
4-level stack register file (LIFO type)
Automatic push/pop stack operation
"Test & skip" operation on test input line
3-bit command code
Tri-state buffered outputs
Auto-reset to address 0 during power-up
Conditional branching, pop stack, &
push stack

I.XL PACKAGE

BLOCK DIAGRAM
(12)
(10) (S)
(5)
(3)
(S)
(4)
(13)
(11)
(g)
AgASA7ASA5A4A3A2A1AO

~~~~-L~~~~

---------------,
10

(2)

(1) AC 2
(2S) AC1
(27) AC O
(25) ClK
(22) VCC~

o--J

t-o

(7) GND0--4

I

I

TEST
(2S)

I

_____________• .-JI
Bg BS B7 Bs B5 B4 B3 B2 B1 BO
(24) (21) (19) (17) (15)
(23) (20) (lS) (lS) (14)

PIN DESCRIPTION
PIN

SYMBOL

5-6
8-13

Ao-Ag

1,28,27

AC o-AC 2

14-21
23-24

Bo-Bg

2

EN

25

ClK

14

NAME AND FUNCTION

TYPE

Microprogram Address outputs

Th ree-state
Active high

Next Address Control Function inputs
All addressing control functions are selected by these command lines.

Active high

Branch Address inputs
Determines the next address of an N-way branch when used with the BRANCH
TO SUBROUTINE (BSR) or BRANCH ON TEST (BRT) command.

Active high

Enable input
When in the low state, the Microprogram Address outputs are enabled.

Active low

Clock input
All registers are triggered on the low-to-high transition of the clock.
Test input
Used in conjunction with four NEXT ADDRESS CONTROL FUNCTION
commands to effect conditional skips, branches, and stack operations.

26

TEST

7

GND

Ground

22

VCC

+5 Volt supply

!ii!]DotiC!i

Active high

8102

CONTROL STORE SEQUENCER

8X02-XL,1

OBJECTIVE SPECIFICATION
Control Store ROM/PROM may be either
the current address plus 1 (N+1) or the
current address plus 2 (N+2). If the same
Microprogram Address is to be used on
successive occasions, the clock to the 8X02
must simply be disabled; therefore, no new
address is loaded into the Address Register.

FUNCTIONAL DESCRIPTION
The Signetics 8X02 Control Store Sequencer is an LSI device using Low Power Schottky technology and is intended for use in
high performance microprogrammed applications. When used alone, the 8X02 is capable of addressing up to 1K words of microprogram. This may be expanded to any
microprogram size by conventional paging
techniques.

The Stack File Register is used to provide a
return address linkage whenever a subroutine or loop is executed. The 4X10 stack
operates in a last-in, first-out (LIFO) mode,
with the stack pointer always pointing to the
next address to be read. Operation of the
stack pointer is automatically controlled by
the Address Control Function Inputs. Since
the stack is 4 words deep, up to 4 loops
and/or subroutines may be nested.

The Address Register consists of 10 D-type,
edge-triggered flip-flops with a common
clock. A new address is entered into the
Address Register on the low-to-high transition of the clock. The next address to be
entered into the Address Register is supplied via the Address Multiplexer.

The branch input is a 10-bit field of direct
inputs to the multiplexer which can be selected as the next control store address.
USing the appropriate branch command, an
N-way branch is possible where N is the
address of any microinstruction within the
1024 word microcode page. Likewise, the
RESET command is a special case of an Nway branch in which the multiplexerselects
an all zeros input, forcing the next microinstruction address to be zero.

The Address Multiplexer is a 5-input device
that is used to select either the branch in put,
+1 adder, +2 adder, stack register file, or
ground (all zeros) as the source of the next
microinstruction address. The proper multiplexer channel is automatically selected via
the Decode Logic according to the Address
Control Function Input and Test Input line.
The +1, +2 logic is used to increment the
present contents of the Address Register by
1 or 2, depending on the function input
command. Thus, the next address to the

The Test Input line is used in conjunction
with the conditional execution of 4 Address
Control Function commands. When the
Test Input is false (low), the sequencer
simply increments to the next address
(N+1). When it is true (high), the sequencer
executes a branch as defined by the input
command, thereby transferring control to
another portion of the microprogram.
All Address Output lines of the 8X02 are
three-state buffered outputs with a common
enable line (EN). When the Enable line is
high, all outputs are placed in a highimpedance state, and external access to the
control store ROM/PROM is possible. This
allows a preprogrammed set of microinstructions to be executed from external or built-in test equipment (BITE), vectored interrupts, and Writable Control Store
if implemented.

NEXT ADDRESS CONTROL FUNCTION
MNEMONIC

TSK

DESCRIPTION

FUNCTION
AC 2 1 0

TEST

NEXT ADDRESS

STACK

STACK POINTER

Test & skip

000

False
True

Current + 1
Current + 2

N.C.
N.C.

INC

Increment

X

Current + 1

N.C.

N.C.

Branch to loop if
test input true

o0
o1

1

BLT

0

False
True

Current + 1
Stack reg fi Ie

X
POP (read)

Decr
Decr

1

X

Stack reg file

POP (read)

Decr

False
True

Current + 1
Branch address

N.C.
PUSH (Curr + 1)

N.C.
Incr

N.C.
N.C.

POP

POP stack

o1

BSR

Branch to subroutine if test
input true

100

PLP

Push for looping

1

X

Current + 1

PUSH (Curr Addr)

Incr

BRT

Branch if test
input true

1 1 0

False
True

Current + 1
Branch address

N.C.
N.C.

N.C.
N.C.

RST

Set microprogram
address output to
zero

1 1 1

X

All O's

N.C.

N.C.

o1

X Don t care
N.C. = No change

!ii!)Dl!tiC!i

15

0)(112

CONTROL STOkE SEQUEI.tEk
OBJECTIVE SPECIFICATION

8X02-XL,1

FUNCTIONAL DESCRIPTION
The following is a description of each of the eight Next Address Control Functions (AC 2-AC o)
MNEMONIC

FUNCTION DESCRIPTION

TSK

AC 2- o=000: TEST &SKI P
Perform test on TEST INPUT LINE.
If test is
Next Address = Current Address + 1
FALSE (LOW):
Stack Pointer unchanged
If test is
Next Address = Current Address + 2
TRUE (HIGH)
(i.e. Skip next microinstruction)
Stack Pointer unchanged

INC

AC 2 - o =001: INCREMENT
Next Address =Current Address + 1
Stack Pointer unchanged

BLT

AC 2 - o=010: BRANCH TO LOOP
IFTEST CONDITION TRUE.
Perform test on TEST INPUT LINE.
If test is
Next Address = Current Address + 1
Stack Pointer decremented by 1
FALSE (LOW):
If test is
Next Address = Address from Stack
TRUE (HIGH):
Register File (POP)
Stack Pointer decremented by 1

POP

AC 2 - 0 = 011: POP STACK
Next Address =Address from Stack Register File (POP)
Stack Pointer decremented by 1

BSR

AC 2 - o =100: BRANCH TO SUBROUTINE
IFTEST CONDITION TRUE.
Perform test on TEST IN PUT LI N E.
If test is
Next Address = Current Address + 1
FALSE (LOW):
Stack Pointer unchanged
If test is
Next Address = Branch Address Input (Bo-g)
TRUE (HIGH):
Stack Pointer incremented by 1
PUSH (write) Current Address + 1 --+ Stack Register File

PLP

AC 2 - o=101: PUSH FOR LOOPING
Next Address =Current Address + 1
Stack Pointer incremented by 1
PUSH (write) Current Address --+ Stack Register File

BRT

AC 2 - o =110: BRANCH ON TEST CONDITION TRUE
Perform test on TEST IN PUT LI N E.
If test is
Next Address = Current Address + 1
FALSE (LOW):
Stack Pointer unchanged
If test is
Next Address = Branch Address Input (Bo-g)
TRUE (HIGH):
Stack Pointer unchanged

RST

AC 2 - 0 =111: RESET TO ZERO
Next Address = 0
Stack Pointer unchanged

ABSOLUTE MAXIMUM RATINGS
PARAMETER
VCC
VIN
Vo
TA
T stg

16

Power supply voltage
Input voltage
Off-State output voltage
Operating temperature range
Storage temperature range

RATING

UNIT

+7
+5.5
+5.5
0° to +70°
-65° to +150°

Vdc
Vdc
Vdc
°c
°c

!ii!l0otiC!i

8](02

CaNTle' STORr Sre"L JCLR

SX02-XL,1

OBJECTIVE SPECIFICATION

DC ELECTRICAL CHARACTERISTICS O°C
PARAMETER
High level input voltage

VIL

Low level input voltage

VI

Input clamp voltage

= 4.7SV, II = -1SmA
VCC = 4.7SV, 10H = -2.6mA
V CC = 4.7SV, 10L = SmA
V CC = S.2SV, V I = S.SV

II

Input current at maximum
Input voltage

IIH

High level input current
AC 2-AC o, EN, TEST
B9 -B o
CLK

V CC

Low level input current
AC 2 -AC o, EN, TEST
B9 -B o
CLK

V CC

Short-circuit output current

VCC

10ZH High-Z state output current

Supply current

= 5V,

TA

= S.2SV,

VI

VI

O.S

V

-1.5

V

2.4

V
0.5

V

100

J.1A

40
20
60

J.1A
J.1A
J.1A

-0.72
-0.36
-1.0S

mA
mA
mA

-100

mA

20
-20

J.1A
J.1A

155

mA

= 2.7V

= O.4V,

= S.2SV
VOUT = 2.7V
VOUT = O.4V
V CC = S.2SV

10ZL High-Z state output current

NOTE
1. All typical values are at V cc

= S.2SV,

UNIT
V

V CC

VOL Low level output voltage

ICC

Min Typ1 Max
2

VOH High level output voltage

lOS

LIMITS

TEST CONDITIONS

V IH

IlL

~ +70°C, 4.7SV, VCC ~ S.2SV

-20

130

= 25° C.

PARAMETER MEASUREMENT INFORMATION
TEST LOAD CIRCUIT
PULSE WIDTHS

SETUP AND HOLD TIMES

TEST
POINT

TIMING
INPUT

,._----3V
HIGH·LEVEL
PULSE

~3V
13V
.
.

'w
w

F~~~~~~~~icr'"'- .........._ _}K~J--.

(SEE NOTE

LOW-LEVEL
PULSE

DATA
INPUT

S1

ov

B)

~
1.3V

1.3V

~~
5k

...... 7

PROPAGATION DELAY TIMES

~~

--

INPUT

IN PHASE
OUTPUT
PHL

OUT OF PHASE
OUTPUT

ALL RESISTORS VALUES ARE TYPICAL AND IN OHMS.

~
tpLH

1 3V
.

VO H
1 3V
.
- - - VOL

NOTES
A. C L includes probe and jig capacitance.
B. All diodes are 1N916 or 1 N3064.
C. RL = 2k, C = 15pF.
OUTPUT
CONTROL
(LOW-LEVEL
ENABLING)

ENABLE AND DISABLE TIMES
THREE-STATE OUTPUTS
~----3V

WAVEFORM 1

'ZH
WAVEFORM 2

S10PEN,
S2 CLOSED

~--"'1.5V

S1 AND S2 CLOSED

Si!lDotiCS

17

AC ELECTRICAL CHARACTERISTICS TA = O°C to +70°C, VCC =5.0V

TO
OUTPUT

FROM
INPUT

PARAMETER
Cycle time
tcy
Clock pulse width high
tpw
Clock pulse width low
tpw
Enable delay
low-to-high-Z
tplZ
High-to-high-Z
tpHZ
High-Z-to-Iow
tpZl
High-Z-to-high
tpZH
Propagation Delay
High-to-Iow
tpHl
low-to-high
tplH

± 5%

Min

LIMITS
Typ1
77
32
45

Max

UNIT
ns
ns
ns

EN

A9- A O

12
16
14
8

ns
ns
ns
ns

ClK

A9- A O

32
20

ns

Set-up and Hold times
With respect to ClK (1)
tSF
tHF

Set-up time high
Hold time high

Control, Data

AC 2 -AC o

70
-6

ns
ns

tSF
tHF

Set-up time high
Hold time high

Control, Data

B9- BO

22
-15

ns
ns

tSI
tHI

Set-up time high
Hold time high

Control, Data

Test

70
-6

ns
ns

tSF
tHF

Set-up time low
Hold time low

Control, Data

AC 2 -ACo

70
8

ns
ns

tSK
tHK

Set-up time low
Hold time low

Control, Data

B9-B o

24
-14

ns
ns

tSI
tHI

Set-up time low
Hold time low

Control, Data

Test

70
8

ns
ns

ts
ts

Set-up time high
Set-up time low

Function

BRT/BSR

50
37

ns
ns

ts
ts

Set-up time high
Set-up time low

Function

TSK

52
70

ns
ns

Set-up time high
ts
Set-up time high
ts
Set-up time high
ts
With respect to ClK (j)
Set-up time high
tSF
Set-up time high
tSI
Set-up time low
tSF
Set-up time low
tSI

Function
Function
Function

INC
RST
POP/BlT

32
27
70

ns
ns
ns

AC 2-AC o
Test
AC 2 -AC o
Test

23
23
22
22

ns
ns
ns
ns

Control,
Control,
Control,
Control,

Data
Data
Data
Data

NOTE
1. Typical values are for T A

18

= 25°e.

vee

= 5.0V.

S!!)DotiCS

CONTROl STORE SEQUE'ICER

8X'"

VOLTAGE WAVEFORMS

,w"

--i

~w-i--.'W=1L---.------1A
I
I-:;~~=j.-------

AoA,

)(

I
rn

=J ""________________
r=
_

-----------------

X~

1··-

----.-I1--.

tHK1X)-t

-tSKIX)r1

---ltHF.~ tSFIX)+
..

~ltHI.I,---- tSllXH

ACo·AC,-----------v;
TEST

~I

-------------

A

F:~~~lt~

Si!lDotiCS

19

SF illES

DIPOLAR MICROPkOCESS"R

100

INTRODUCTION
The introduction of the Signetics Series
3000 Bipolar Microprocessor Chip Set has
brought new levels of high performance to
microprocessor applications not previously
possible with MaS technology. Combining
the Schottky bipolar N3001 Microprogram
Control Unit (MCU) and N3002 Central
Processing Element (CPE) with industry
standard memory and support circuits, microinstruction cycle times of 100ns are
possible.
In the majority of cases, the choice of a
bipolar microprocessor slice, as opposed to
an MaS device, is based on speed or flexibility of microprogramming. Starting with
these characteristics, the design of the Signetics Series 3000 Microprocessor has been
optimized around the following objectives:
• Fast cycle time
• All memory and support chips are industry
standard
• Cooler operation
• Lower total system cost

with a minimum amount of auxiliary logic.
Features such as the multiple independent
address and data buses, tri-state logic, and
separate output enable lines eliminate the
need for time-multiplexing of buses and
associated hardware.
Each Central Processing Element represents a complete 2-bit slice through the data
processing section of a computer. Several
CPEs may be connected in parallel to form a
processor of any desired word length. The
Microprogram Control Unit controls the
sequence in which microinstructions are
fetched from the microprogram memory
(ROM/PROM), with these microinstructions controlling the step-by-step operation
of the processor.
Each CPE contains a 2-bit slice of 5 independent buses. Although they can be used
in a variety of ways, typical connections are:
Input M-bus:
Input .I-bus:

Furthermore, systems built with large-scale
integrated circuits are much smaller and
require less power than equivalent systems
using medium and/or small scale integrated
circuits.
The 2 components of the Series 3000 chip
set, when combined with industry standard
memory and peripheral circuits, allows the
design engineer to construct highperformance processors and/or controllers

Input K-bus:
Output A-bus:
Output D-bus:

Carries data from external
memory
Carries data from input/output
device
Used for microprogram mask or
literal (constant) value input
Connected to CPE Memory
Address Register
Connected to CPE accumulator.

As the CPEs are paralleled together, all
buses, data paths, and registers are correspondingly expanded.
The microfunction input bus (F-bus) con-

trois the internal operation of the CPE,
selecting both the operands and the operation to be executed upon them. The arithmetic logic unit (ALU), controlled by the
microfunction decoder, is capable of over
40 Boolean and binary operations as outlined in the Function Description section
of the N3002 data sheet. Standard carry look-ahead outputs (X and Y) are generated by the CPE for use with industry standard devices such as the 74S182.
A typical processor configuration is shown
in Figure 1. It should be remembered that in
working with slice-oriented microprocessors, the final configuration may be varied
to enhance speed, reduce component
count, or increase data-processing capability. One method of maximizing a processor's performance is called pipelining. To
accomplish this, a group of D-type flip-flops
or latches (such as the 74174 Hex D-type
Flip-Flop) are connected to the microprogram memory outputs (excluding the address control field AC o-AC 6 ) to buffer the
current microinstruction and allow the MCU
to overlap the fetch of the next instruction
with the execution of the current one. The
time saved in pipelining operations is the
shorter of either the address set-up time to
the microprogram memory (ROM/PROM)
or the access time of the ROM/PROM. A
convenient way of implementing pipelining
is to use ROMs with on-board latches, such
as the Signetics 82S115.

MICROCOMPUTER BLOCK DIAGRAM
I/O CONTROL

MEMORY ADDRESS BUS

DATA BUS

MICRO
PROGRAM
MEMORY
(82S115)

FROM I/O DEVICES

Figure 1

20

Si!)DotiCS

DATA IN FROM MEMORY

*Carry-in of first stage
"Carry-out of last stage

BI fBLAR MICRBP RBCESSBR
Figure 2 shows a typical microinstruction
format using the 82S114 PROMs contained
in the Signetics 3000 Microprocessor Designer's Evaluation Kit. Although this particular example is for a 48-bit word (6
PROMs), the allocation of bits for the mask
(K-bus) and optional processor functions
depends on the specific application of the
system and the trade offs which the designer wishes to make.
In using the K-bus, it should be kept in mind
that the K inputs are always ANDed with the
B-multiplexer outputs into the ALU. Bit
masking, frequently done in computer control systems, can be performed with the
mask su ppl ied to the K-bus directly from the
microinstruction.

SERIES JOIiO
croprogram memory (ROM/PROM). In its
classical form, the MCU would use a nextaddress field in each microinstruction.
However, the N3001 uses a modified classical approach in which the microinstruction
field specifies conditional tests on the MCU
bus inputs and registers. The next-address
logic of the MCU also makes extensive use
of a row/column addressing scheme,
whereby the next address is defined by a 5bit row address and 4-bit column address.
Thus, from a particular address location, it
is possible to jump unconditionally to any
location within that row or column, or conditionally to other specified locations in one
operation. Using this method, the processor
functions can be executed in parallel with
program branches.

By plaCing the K-bus in either the all-one or
all-zero condition (done with a single control bit in the microinstruction), the accumulator will either be selected or deselected, respectively, in a given operation.
This feature nearly doubles the amount of
microfunctions in the CPE. A description of
these various microfunctions can be found
in the N3002 data sheet under the heading
Function Description by referring to the Kbus conditions of all-ones (11) and all-zeros
(00).

As an example of this flexibility, let us assume a disk controller is being deSigned. As
part of the sequence logic, 3 bits of the disk
drive status word must be tested and all 3
must be true in order to proceed with the
particular sequencing operation. In any
sequencing operation using a status word
for conditional branch information, there
are innumerable combinations of bits which
must be tested throughout the sequencing
operation. Using discrete logic techniques,
this would involve several levels of gating.

The MCU controls the sequence in which
microinstructions are fetched from the mi-

However, the entire operation can be done
in two microinstructions. First, the mask (K-

bus) field in the microinstruction format is
encoded with a one for each corresponding
status bit to be tested and a zero for each bit
to be discarded. The status word is input via
the I-bus and ANDed with the K-bus mask
using the CPE microfunction operation
from F-Group 2, R-Group III. Assuming we
are using low-true logic (true = 0 volts),
we now test the result, which is located in
the accumulator AC, for all zeros using the
CPE microfunction operation from F-Group
5, R-Group III. Depending on the zero/nonzero status of AC, a one or zero will be
loaded into the carryout CO bit. This bit can
now be used as a condition for the next
address jump calculation within the N3001
MCU. If the AC was zero (status word was
true), we will jump to the next address within
our controller sequence. If the AC was nonzero (status word not true), then a jump
would be made back to the beginning of this
2-microinstruction loop and the test sequence repeated until the status word (all 3
bits) is true.
Figure 3 shows a typical timing diagram for
a system operating in the non-pipelined
mode. Keep in mind that the maximum
clock rate is dependent upon the total of
propagation delay times plus required setup times. It is at the designer's discretion to
resolve the speed versus complexity tradeofts.

TYPICAL MICROINSTRUCTION FORMAT
USER·DEFINABLE FUNCTION FIELDS

STANDARD FUNCTION FIELDS

r~------------------~------------------- ---------~------------

~,

47

44143

40139

USER
DEFINED
FUNCTIONS

36135

32131

28127

24123

20119 16115

MASK OR OPTIONAL
PROCESSOR FUNCTIONS

Note:
The mask field need only be used during masking operations.
At other times, it is entirely user definable.

12111

C.P.E.
FUNCTION
(FO·F6)

4 3

817
JUMP
FUNCTION
(AC O· AC 6)

0

FLAG
LOGIC
FUNCTION
(FC O· FC3)

____________ . . . ---_V""_---1
Figure 2

TO N3002

TO N3001

SYSTEM TIMING-NON-PIPELINED CONFIGURATION

MICROPROGRAM
MEMORY AOOR
(MAO-8)

-I 36n51X

I~50n~ ~8n.51

ROM
OUTPUT
N3002
OATAOUT
(O-BUS)

X

X
X

~

x=

X

40n5

r-X

x:::

Figure 3

!i!!lDotiC!i

21

al rUI AR

"ICRI FR

1(:[ S iUR

SEE'FS

FRUDin,! INFuRIA' Il,N

PARAMETE.R MEASUREMENT
INFORMATION

ABSOLUTE MAXIMUM RATINGS*

Temperature under bias
Storage temperature
All output and supply voltages
All input voltages
Output currents

N3001/N3002

53001/53002

ooe to +70 e
-60° e to +160° e
-0.5V to +7V
-1.0V to +5.5V
100mA

-55° e to +125° e
-65°e to +150 0 e
-0.5V to +7V
-1.0V to +5.5V
100mA

0

a

1

500

'Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not implied. Exposure to absolute
maximum ratings for extended periods may effect device reliability.

OUT

u-~t----4

lk

NOTE: All resistor values are typical and in ohms.
TEST CONDITIONS:
Input pulse amplitude of 2.5 volts
Input rise and fall times of 5ns between 1 volt and 2 volts
Output load of 1 OmA and 50pF
Speed measurements are taken at the 1.5 volt level

DC ELECTRICAL CHARACTERISTICS
PARAMETER

N3001/N3002

T A = 0° e to +70° e

S3001/S3002

T A = -55°e to +125°C

TEST CONDITIONS

N3001/N3002
Min

Vil
VIH
Vie

low level input voltage
High level input voltage
Input clamp voitage

Vee = 5.OV
Vee = 5.OV
Vee = 4.75V, Ie = -SmA

Val low level output voltage
VOH High level output voltage

Vee = 4.75V, I Ol =10mA
Vee = 4.75V, 10H = -1mA
mAo - mAs, I SE, Fa

Input load current N3001

Vee = 5.25V, VF = 0.45V
elK input
EN input
All other inputs
Vee = 5.25V, VR = 5.25V
elK input
EN input
All other inputs

IF

IR

Input leakage current N3001

lOS

Short circuit output current

10
(off)

Off-state output current

J

lee

Power supply current N3001

IF

Power supply current N3002
Input load eurrent N3002

Vee = 5.OV
mAo - mAs, ISE, Fa
Vee = 5.25V
PRo - PR 2, mAo - mA2' Fa
VOUT = 0.45V
mAo - mAs, Fa
VOUT = 5.25V
Vee = 5.25V2

Input leakage Current N3002

Vee = 5.25V, V R = 5.25V
Fo-F 6 , elK, Ko, K 1 , EA, ED
10, 11 , Mo, M 1 , LI
el

NOTES
1. SN3001 typical values are for T A = 25° e, Vee = 5.0V
2. SN3002 EN input grounded, all other inputs and outputs open.
SN3002 elK input grounded, other inputs open.

22

Max

Min

Typ

-0.55

-1.0

-0.8

-1.2

V
V
V

0.35
2.4

0.45
3.0

0.35
2.4

0.45
3.0

V
V

-0.21
-0.12
-0.05

-0.75
-0.50
-0.25

0.8

0.8
2.0

2.0

120
80
40
-15

UNIT

Max

-28

-60

-100
+100

-15

-0.21 -0.75
-0.12 -0.50
-0.05 -0.25
VR = 5.5V
120
80
40

mA
mA
mA

-60

mA

-28

-100
VIoUT = 5.5V
+100

J.1A
J.1A
J.1A

J.1A
J.1A
mA

170

240

170

250

145

190

145

210

-0.05
-0.85
-2.3

-0.25
-1.5
-4.0

-0.05
-0.85
-2.3

-0.25
-1.5
-4.0

mA
mA
mA

40
60
180

J.1A
J.1A
J.1A

Vee = 5.25V, V F = 0.45v
Fo-F 6 , elK, Ko, K 1 , EA, ED
1o, 11 , Mo, M 1 , LI
el

IR

Typ

53001/53002

S!!IDotiCS

40
60
180

S N30111

MICROPROGRAM CON 1IIlib ONII

N3001-1

DESCRIPTION

FEATURES

The N3001 MCU is 1 element of a bipolar
microcomputer set. When used with the
S/N3002, 54/74S182, ROM or PROM memory, a powerful microprogrammed computer
can be implemented.

• Schottky TTL process
• 45ns cycle time (typ.)
• Direct addressing of standard bipolar
PROM or ROM
• 512 microinstruction addressability
• Advanced organization:
• 9-bit microprogram address register
and bus organized to address memory
by row and column
• 4-bit program latch
• 2-flag registers
• 11 address control functions:
• 3 jump and test latch function
• 16 way jump and test instruction
• 8 flag control functions:
• 4 flag input functions
• 4 flag output functions

The 3001 MCU controls the fetch sequence
of microinstructions from the microprogram memory. Functions performed by the
3001 include:
•
•
•

Maintenance of microprogram address register
Selection of next microinstruction address
Decoding and testing of data supplied via
several input buses
• Saving and testing of carry output data from the
central processing (CP) array
• Control of carry/shift input data to the CP array
• Control of microprogram interrupts

PIN CONFIGURATION
I PACKAGE

BLOCK DIAGRAM
MA8 MAl MA6 MA5 MA4
) (
<)
~

FO
(

MA3 MA2 MA 1 MAO

)

()

(

> (

(

,...

ERA

ROW
OUTPUT

~

EN

~

l

,...
FCO
~

FC1

,.."

FC3

,.."

FLAG
CONTROL

,...
FC2
~

1

H

-

~

h

~

ADDRESS REGISTER

I
J 9

I

~~~

PR
lATCH

~

,...
AC3

3

OUT

-

~

AC4
AC5

ISE

t

,.."

,...
AC2

AC6

-

NEXT ADDRESS CONTROL

GND C>----<

,...

~

I--i

!

Vcc C>----<

AC1

c, z
FLAGS

F
LATCH

ClK C>----<

ACO

1

COLUMN
OUTPUT

~

,.."

lD

I

,.. PRO
,... PR1
~

~

PR2

-

,...

(

~

~

(

o~~~

PXl PX6 PX5 PX4

!ii!ln~tiC!i

~

)

~

~

~~~~

SX3 SX2 SX1 SXO

23

M" "Q I'lt UGIi

n.. "PI TR" lUll T

S N 11111
N3001-1

PIN DESCRIPTION
PIN

SYMBOL

1-4

PX4 -PX 7

5,6,8,10

SXO-SX3

7,9,11

PR o-PR 2

12,13
15,16

FC o-FC 3

14

FO

17

fi

18

ISE

19
20
21-24
37-39
25

CLK
GND
AC o-AC 6

26-29
30-34
35

MAo-MA3
MA4-MAs
ERA

36

LD

40

VCC

EN

Primary Instruction Bus Inputs
Data on the primary instruction bus is tested by the JPX function to
determine the next microprogram address.
Secondary Instruction Bus Inputs
Data on the secondary instruction bus is synchronously loaded into the
PR-Iatch while the data on the PX-bus is being tested (JPX). During a
subsequent cycle, the contents of the PR-Iatch may be tested by the JPR,
JLL, or JRL functions to determine the next microprogram address.
PR-Latch Outputs
The PR-Iatch outputs (SX O-SX 2 ) are synchronously enabled by the JCE function.
They can be used to modify microinstructions at the outputs of the
microprogram memory or to provide additional control lines.
Flag Logic Control Inputs
The flat logic control inputs are used to cross-switch the flags (C and Z)
with the flag logic input (FI) and the flag logic output (FO).
Flag Logic Oulput
The outputs of the flags (C and Z) are multiplexed internally to form the
common flag logic output. The output may also be forced to a logical
o or logical 1.
Flag Logic Input
The flag logic input is demultiplexed internally and applied to the inputs
of the flags (C and Z). Note: The flag input data is saved in the F-Iatch
when the clock input (CLK) is low.
Interrupt Strobe Enable Output
The interrupt strobe enable output goes to logical 1 when one of the
JZR functions are selected (see Functional Description). It can be used
to provide the strobe signal required by interrupt circuits.
Clock Input
Ground
Next Address Control Function Inputs
All jump functions are selected by these control lines.
Enable Input
When in the high state, the enable input enables the microprogram
address, PR-Iatch and flag outputs.
Microprogram Column Address Outputs
Microprogram Row Address Outputs
Enable Row Address Input
When in the low state, the enable row address input independently
disables the microprogram row address outputs. It can be used to facilitate
the implementation of priority interrupt systems.
Microprogram Address Load Input
When the active high state, the microprogram address load input inhibits
all jump functions and synchronously loads the data on the instruction
buses into the microprogram address register. However, it does not inhibit
the operation of the PR-Iatch or the generation of the interrupt strobe enable.
+5 Volt supply

THEORY OF OPERATION
The MCU controls the sequence of microinstructions in the microprogram memory.
The MCU simultaneously controls 2 flipflops (C, Z) which are interactive with the
carry-in and carry-out logic of an array of
CPEs.

24

TYPE

NAME AND FUNCTION

The functional control of the MCU provides
both unconditional jumps to new memory
locations and jumps which are dependent
on the state of MCU flags or the state of the
"PR" latch. Each instruction has a "jump
set" associated with it. This "jump set" is the
total group of memory locations which can
be addressed by that instruction.

Gi!lDotiCG

Active low

Active low

Open Collector

Active high

Active low
Three-state

Active low

Active high

Active high

Three-state
Th ree-state
Active high

Active high

The MCU utilizes a two-dimensional addressing scheme in the microprogram memory. Microprogram memory is organized
as 32 rows and 16 columns for a total of 512
words. Word length is variable according to
application. Address is accomplished by a
9-bit add ress organ ized as a 5-bit row and 4bit column address.

MICkOPROGRAM CON IkOL UNII

S N3001
N3001-1

JUMP FUNCTION TABLE
ADDRESSING ORGANIZATION

FUNCTION DESCRIPTION

MNEMONIC

JCC

Jump in current column. AC o-AC 4 are used to select 1 of 32 row addresses in the current column, specified by MAo-MA3' as the next
address.

JZR

Jump to zero row. AC o-AC 3 are used to select 1 of 16 column addresses
in rowo, as the next address.

JCR

Jump in current row. AC o-AC 3 are used to select 1 of 16 addresses in the
current row, specified by MA 4 -MAs, as the next address.

JCE

Jump in current column/row group and enable PR-Iatch outputs. AC oAC 2 are used to select 1 of 8 row addresses in the current row group,
specified by MA?-MA s, as the next row address. The current column is
specified by MAo-MA3. The PR-Iatch outputs are asynchronously en. abled.

32

ROWSr+~~~~+-r+~+-~~~

JUMP/TEST FUNCTION TABLE
MNEMONIC

1...- - - -

JFL

Jump/test F-Iatch. AC o-AC 3 are used to select 1 of 16 row addresses in
the current row group, specified by MAs, as the next row address. If the
current column group, specified by MA 3, is colo-col?, the F-Iatch is used
to select col2 or col3 as the next column address. If MA3 specifies column
group col s-coI 15 , the F-Iatch is used to select COllO or COlll as the next
column address.

JCF

Jump/test C-flag. AC o-AC 2 are used to select 1 of 8 row addresses in the
current row group, specified by MA? and MAs, as the next row address. If
the current column group specified by MA3 is colo-col?, the C-flag is
used to select col 2 or col3 as the next column address. If MA3 specifies
column group col s-coI 15 , the C-flag is used to select col lO or COlll as the
next column address.

JZF

Jump/test Z-flag. Identical to the JCF function described above, except
that the Z-flag, rather than the C-flag, is used to select the next column
address.

JPR

Jump/test PR-Iatch. AC o-AC 2 are used to select 1 of 8 row addresses in
the current row group, specified by MAl and MAs, as the next row
address. The 4 PR-Iatch bits are used to select 1 of 16 possible column
addresses as the next column address.

JLL

Jump/test leftmost PR-Iatch bits. AC o-AC 2 are used to select 1 of 8 row
addresses in the current row group, specified by MAl and MAs, as the
next row address. PR 2 and PR 3 are used to select 1 of 4 column
addresses in col 4 through col? as the next column address.

JRL

Jump/test rightmost PR-Iatch bits. AC o and AC l are used to select 1 of4
high-order row addresses in the current row group, specified by MA?
and MAs, as the next row address. PRo and PR l are used to select 1 of 4
possible column addresses in COl 1 2 through COl 16 as the next column
address.

JPX

Jump/test PX-bus and load PR-Iatch. AC oand AC l are used to select 1 of
4 row addresses in the current row group, specified by MA6 -MAs, as the
next row address. PX 4 -PX l are used to select 1 of 16 possible column
addresses as the next column address. SXO-SX3 data is locked in the PRlatch at the rising edge of the clock.

16 COLUMNS - - - - - \
MAO-MA3

FUNCTIONAL DESCRIPTION
The following is a description of each of the
eleven address control functions. The symbols shown below are used to specify row
and column addresses.
SYMBOL

MEANING

rown

5-bit next row address
where n is the decimal
rowaddress.

col n

4-bit next column address
where n is the decimal
column address.

Unconditional Address
Control (Jump) Functions
The jump functions use the current microprogram address (i.e., the contents of the
microprogram address register prior to the
rising edge of the clock) and several bits
from the address control inputs (ACO-AC6)
to generate the next microprogram address.

Flag Conditional Address
Control (Jump Test)
Functions

FUNCTION DESCRIPTION

The jump/test flag functions use the current
microprogram address, the contents of the
selected flag or latch, and several bits from
the address control function to generate the
next microprogram address.

SmDotiCS

25

S N3oo1

MICROPROGRAM CONTROE BNIT

N3001-1

FLAG CONTROL FUNCTION TABLE

PX-Bus and PR-Latch
Conditional Address Control
(Jump/Test) Functions

MNEMONIC

The PX-bus jump/test function uses the
data on the primary instruction bus (PX 4 PX 7), the current microprogram address,
and several selection bits from the address
control function to generate the next microprogram address. The PR-Iatch jump/
test functions use the data held in the PRlatch, the current microprogram address,
and several selection bits from the address
control function to generate the next microprogram address.

FUNCTION DESCRIPTION

SCZ

Set C-flag and Z-flag to FI. The C-flag and the Z-flag are both set to the
value of FI.

STZ

Set Z-flag to FI. The Z-flag is set to the value of FI. The C-flag is
unaffected.

STC

Set C-flag to FI. The C-flag is set to the value of FI. The Z-flag is
unaffected.

HCZ

Hold C-flag and Z-flag. The values in the C-flag and Z-flag are
unaffected.

FLAG OUTPUT CONTROL FUNCTION TABLE

Flag Control Functions

,MNEMONIC

The flag control functions of the MCU are
selected by the 4 input lines designated
FC o-FC 3. Function code formats are given in
"Flag Control Function summary."
The following is a detailed description of
each of the 8 flag control functions.

Flag Input Control
Functions

FUNCTION DESCRIPTION

FFO

Force FO to O. FO is forced to the value of logical O.

FFC

Force FO to C. FO is forced to the value of the C-flag.

FFZ

Force FO to Z. FO is forced to the value of the Z-flag.

FF1

Force FO to 1. FO is forced to the value of logical 1.

FLAG CONTROL FUNCTION SUMMARY

The flag input control functions select
which flag or flags will be set to the current
value of the flag input (FI) line.
Data on Fi is stored in the F-Iatch when the
clock is low. The content of the F-Iatch is
loaded into the C and/or Z flag on the rising
edge of the clock.

Flag Output Control Functions

TYPE

MNEMONIC

Flag
Input

SCZ
STZ
STC
HCZ

TYPE

MNEMONIC

The flag output control functions select the
value to which the flag output (FO) line will
be forced.

Set C-flag and Z-flag to f
Set Z-flag to f
Set C-flag to f
Hold C-flag and Z-flag

Force
Force
Force
Force

LOAD
FUNCTION

FO
FO
FO
FO

to
to
to
to

MAa

0
C-flag
Z-flag
1

2

0
0
1
1

0
1
0
1

NEXT COL

MA3
1
4
2
s
6
See Address Control Function Summary
X2
X1
X7
X3
Xs
X6
Xo
7

0

I

0

NOTE
f = Contents of the F-Iatch

0
1
0
1

FC 3

NEXT ROW

LD
0
1

0

0
0
1
1

DESCRIPTION

FFO
FFC
FFZ
FF1

Flag
Output

FC 1

DESCRIPTION

X4

x n = Data on PX- or SX-bus line n (active low)

ADDRESS CONTROL FUNCTION SUMMARY

JCC
JZR
JCR
JCE
JFL
JCF
JPR
JLL
JRL
JPX

DESCRIPTION
Jump in current column
Jump to zero row
Jump in current row
Jump in column/enable
Jump/test F-Iatch
Jump/test Z-flag
Jump/test PR-Iatch
Jump/test left PR bits
Jump/test right PR bits
Jump/test PX-bus

NOTE
d n = Data on address control line n
mn = Data in microprogram address register bit n

26

AC 6
0
0
0
1
1
1
1
1
1

1

5

4

3

2

1

0
1
1
1
0
0
1
1

d4
0
1
1
0
1
0
0
1

d3
d3
d3
0
d3
1
0
1
1

1

1

d2
d2
d2
d2
d2
d2
d2
d2
1
0

d1
d1
d1
d1
d1
d1
d1
d1
d1
d1

1
1

NEXT COL

NEXT ROW

FUNCTION
MNEMONIC

0

MAs

7

6

5

4

MA3

do
do
do
do
do
do
do
do
do
do

d4
0
ma
ma
ma
ma
ma
ma
ma
ma

d3
0
m7
m7
d3
m7
m7
m7
m7
m7

d2
0
m6
d2
d2
d2
d2
d2
1
m6

d1
0
ms
d1
d1
d1
d1
d1
d1
d1

do
0
m4
do
do
do
do
do
do
do

m3
d3
d3
m3
m3
m3
m3
P3
0
x7

Pn = Data in PR-Iatch bit n
xn = Data on PX-bus line n (active low)
f,c,z = Contents of F-Iatch, C-flag, or Z-flag, respectively

smAoties

2

1

0

m2
d2
d2
m2
0
0

m1
d1
d1
m1
1
1
1
P1
P3
Xs

mo
do
do
mo
f
c
z
Po
P2
x4

0
P2

1
X6

S N3DOI

MICROPRIIGkAM OONTROL UNII

N3001-1

STROBE FUNCTIONS

JUMP SET DIAGRAMS

The load function of the MCU is controlled
by the input line designated LD. If the LD
line is active high at the rising edge of the
clock, the data on the primary and secondary instruction buses, PX r PX 7 and SXO-SX3'
is loaded into. the microprogram address
register. PX 4 -PX 7 are loaded into MAo-MA7
and SXd-SX3 are loaded into MA4 -MA 7. The
high-order bit of the microprogram address
register MAs is set to a logical O. The bits
from the primary instruction bus select 1 of
16 possible column addresses. Likewise,
the bits from the secondary instruction bus
select 1 of the fi rst 16 row add resses.
The MCU generates an interrupt strobe
enable on the output line designated ISE.
The line is placed in the active high state
whenever a JZR to COilS is selected as the
address control function. Generally, the
start of a macroinstruction fetch sequence
is situated at row o and COilS so the interrupt
control may be enabled at the beginning of
the fetch/execute cycle. The interrupt control responds to the interrupt by pulling the
enable row address (ERA) input line low to
override the selected next row address from
the MCU. Then by gating an alternative next
row address on to the row address lines of
the microprogram memory, the microprogram may be forced to enter an interrupt
handling routine. The alternative row address placed on the microprogram memory
address lines does not alter the contents of
the microprogram address register. Therefore, subsequent jump functions will utilize
the row address in the register, and not the
alternative row address, to determine the
next microprogram address.

JCC
JUMP IN CURRENT COLUMN

JZR
JUMP TO ZERO ROW

(.

(

'of

ROW3l - - L.....L.....L...L..JL......&i_.J.........L-L...1.-1-..L-L...L..-JL.......J

t

COlO

t

CURRENT
COLUMN

t

COl 15

JLL
JUMP/TEST LEFT LATCH

JPR
JUMP/TEST PR-LATCH

Note, the load function always oVerrides the
address control function on AC o-AC 6 . It
does not, however, override the latch enable
or load sUb-functions of the JCE or JPX
instruction, respectively. In addition, it does
not inhibit the interrupt strobe enable or any
of the flag control functions.

JUMP SET DIAGRAMS
The following 10 diagrams illustrate the
jump set for each of the 11 jump and jump/
test functions of the MCU. Location 341
indicated by the circled square, represents 1
current row (row 2l ) and current column
(co Is) address. The dark boxes indicate the
microprogram locations that may be selected by the particular function as the next
address.

CURRENT
ROW
GROUP

CURRENT
ROW
GROUP

MS7
10

MS 7
10

f-ff-If-ff-ff-ff-I-

il

1-1-

f-f-

I-r-

COlO

!ii!)notiC!i

27

MICROPROGRAM CONTROL UNIT

S N3110!
N3001-1

JUMP SET DIAGRAMS

(Cont'd)

JRL
JUMP/TEST RIGHT LATCH

CURREN;LROW
GROUP
MS76
101

~

.IJ

S--

JCR
JUMP IN CURRENT ROW

JPX

JUMP/TEST PX-BUS

CURREN;lROW
GROUP
MS76
101

~

CURRENT --+ROW

~

S--

r+-r~-+~+;-r~~-r~r;

t

t

COlO

JCE
JUMP COLUMN/ENABLE

COl15

JCF, JZF
JUMP/TEST C-FLAG
JUMP/TEST Z-FLAG

JFL
JUMP/TEST F-LATCH
CURRENT
COLUMN
GROUP

CURRENT
COLUMN
GROUP

M3= 0

M3=

o·

-

--

CURRENT
ROW
GROUP
MS 7

-

CURRENT
ROW
GROUP
MS

10

1

-

•
~

r-

I-I-I-I-I-I--

--

10

!I
i

.)
r-

bOl 3 (c,z = 1)
COl2 (c,z = 0)

CURRENT COLUMN

28

CURRENT
ROW
GROUP
MS7

!ii!Jn~liC!i

MICROPkOGkAM CON I kOL UNIT

S N3001
N3001-1

N3001 T A = O°C to +70°C, VCC = 5.0V, ± 5%

AC ELECTRICAL CHARACTERISTICS

S3001 T A= -55°C to +125°C, VCC = 5.0V ± 10%
N3001

PARAMETER
Time 2

tCY Cycle
tpw Clock Pulse Width
Control and Data Input Set-Up Times:
tSF lD, AC o-AC 6 (Set to "1 "/"0")
tSK FC o, FC 1
tsx PX 4 -PX 7 (Set to "1 "/"0")
FI (Set to "1 "/"0")
tSI
tsx SXO-SX3
Control and Data Input Hold Times:
tHF lD, AC o-AC 6 (Hold to "1 "/"0")
tHK FC o, FC 1
tHX PX 4 -PX 7 (Hold to "1 "/"0")
FI (Hold to "1 "/"0")
tHI
tHX SXO-SX3
tco Propagation Delay from Clock Input (ClK) to Outputs
(mAo-mAs, Fa) (tPHl/tPlH)
t KO Propagation Delay from Control I n puts FC 2 and FC 3to Flag
Out (Fa)
t FO Propagation Delay from Control Inputs AC o-AC 6 to latch
Outputs (PR o-PR 2 )
tEO Propagation Delay from Enable Inputs EN and ERA to
Outputs (mAo-mAs, Fa, PR o-PR 2 )
Propagation Delay from Control Inputs AC o-AC 6 to
tFI
IlJterrupt Strobe Enable Output (ISE)

53001
Min

Typ1

45
10

95
40

45
10

ns
ns

20
7
28
12
15

3/14
5
4/13
-6/0
5

20
10
35
15
35

3/14
5
4/13
-6/10
5

ns
ns
ns
ns
ns

4
4
0
16
0

-3/-14
-5
-4/-13
6.5/0
-5
17/24

36

5
10
25
22
25
10

-3/-14
-5
-4/-13
6.5/0
-5
17/24

45

ns
ns
ns
ns
ns
ns

13

24

13

50

ns

21

32

21

50

ns

17

26

17

35

ns

20

32

20

40

ns

Min

Typ1

60
17

Max

Max

UNIT

NOTE
1. Typical values are for T A = 25°C and 5.0 supply voltage.
2. 83001: tCY = tWP + t8F + tCO

!ii!lDotiC!i

29

MIE"OI liOGItAII bOIi IhOL tJ NII

S N30"}
N3001-1

VOLTAGE WAVEFORMS

~
CLK
CLOCK INPUT

~

/

V

if

\

1\

.

J

_ t p w ____
tCY

\1/
/ 1\

EN, ERA
ENABLE INPUTS

-

--

-tco
tEO

\V

~~~~~~~ MEMORY

/\

ADDRESS OUTPUTS

tSF_

tHF

\V

J~

.

tEO

-

I-

tFO

\V

J~

PR O-PR 2
"PR" LATCH OUTPUTS

tSK

-tHK

\V

FCO-FC3
FLAG CONTROL
INPUTS

/1\
tHI

tSI

I----

\V

J\

FI
FLAG INPUT
_tKO

I--

-tEO
I-tco

I\V

lI\

FO
FLAG OUTPUT

_ t F I ___

\/

ISE
INTERRUPT STROBE
ENABLE OUTPUT

I~.~

SXO-PX7
___________________
INSTRUCTION
BUS INPUTS

30

-_-_-_-_-_"~:IA
~-~.-'- ~

__-_-_-___t_HX__

~ ------.~I----------------------~

_ ___ ______ts_x__

Si!lDOliCS

___

S Hal102

GLN I RAL PltuGESSING ELEMENI

S3002-1 • N3002-XL, I

DESCRIPTION

FUNCTION TRUTH TABLE

The N3002 Central Processing Element
(CPE) is one part of a bipolar microcomputer set. The N3002 is organized as a 2-bit
slice and performs the logical and arithmetic functions required by microinstructions.
A system with any number of bits in a data
word can be implemented by using multiple
N3002s, the N3001 microcomputer control
unit, the N74S182 carry look-ahead unit and
ROM or PROM memory.

XL,I PACKAGE

FUNCTION
GROUP
0
1
2
3
4
5
7

•
•
•
•
•

45ns cycle time (typ)
Easy expansion to multiple of 2 bits
11 general purpose registers
Full function accumulator
Useful functions include:
• 2's complement arithmetic
• Logical AND, OR, NOT, exclusiveNOR
• Increment, decrement
• Shift left/shift right
• Bit testing and zero detection
• Carry look-ahead generation
• Masking via K-bus
• Conditioned clocking allowing nondestructive testing of data in accumulator and scratch pad
• 3 input buses
• 2 output buses
• Control bus

Fs

Fs

F4

0

0

a
a
a

a

a

1
1
1
1

6

FEATURES

REGISTER
GROUP REGISTER

1

1
1

a

a

a

0
1
1

a

1
1

1

F3 F2 Fl
0
0

Ro
Rl
R2
R3
R4
R5
R6
R7
R8
Rg
T
AC

0
0
1
1
1
1

II

T
AC

III

T
AC

I

PIN CONFIGURATION

a
0

a
a

Fo

a a a
a a 1
0
0
1
1
1
1
0

a

1
1

a
a
1
1

a

0
1
0
1

a
1
0
1
0
1

1
1

0
0
0

1
1

0
0

1
1

a

1
1

1
1

1
1

0
1

1

BLOCK DIAGRAM
(12)

(13)

(20)

(11)0--a----J

(19)

'-------------lo-~(23)

EA

ED

(S)

Xo----1f-----________...r-.. . . . ..L....--.........---L....------,

(6)

yo-___! - - - - - - - - - - - - - - I

(7)

...----+---+---4---1f----lO--C CI

(9) LI

o--qt------------~-""T""r------""T"""r_~

(18) CLKo--oI

I
I

(28) VCco---t

I

(14) GNDO---;

(lS) F6 0 - - - t - - - - - t
(16) F S o - - - t - - - - - t
(17) F4 0 - - - - 4 - - - - - t
(24) F3 0 - - - t - - - - - t
(27) F2 0 - - - - 4 - - - - - t
(26) Fl
f----~

(10)

1----I----+---l~I__-_h__I

MERGE

I
r--

/\l.

L.

7
Rl
R2
R3

. ':>

R4
R5
R6

/<=t

....
K...

Rll
AUX

-

ALU

~K
L

MASK

K

RIGHT
ROTATE

~

....

V

K...

INTERNAL CONTROL
SIGNALS

I

fr

I

I
I

0

I

£:

DECODE
AND
CONTROL
LOGIC

12
AR

I

l

1

{r
PC

I

~

....,
I

J I

""

l.

+5 •
GND •

10-115
INSTRUCTION DATA

Figure 2

50

-....

,...

....
....

IRO-IR2

I

\1
AO-A12
INSTRUCTION ADDRESS

-

WC

,...

"

I.

RB

~

,...

I
CONTROL

!ii!lDotiC!i

IVBO-IVB7
IV BUS

~

I

11

...

I""

ARO-AR4

I

7

I,.,.

~

L_

V

~

I,.,.

I
AR5-AR12

.....

()

f-

I""

oc'"

I
I

~
:r

:3

__

(S)=o

'---

VR------------.
VCR~I~-----------

LB

SC
MCLK
HALT
RESET

INTERPRETER

8X300
8X300-1

- INSTRUCTION CYCLE INSTRUCTION OP
MNEMONIC CODE

MOVE

o

DESCRIPTION

FORMATS

I/O CONTROL
SIGNALS

SC

=

(S) - D
Move contents of register specified
by S to register specified by D. Right
0 SiR
0
I rotate contents of register S by R
S;o!07,17,20-37 8
O;o! 10,20-378 places before operation.

WC=
LB/RB =
LB/RB =

Move right rotated IV bus (source)
data specified by S to register speci15
fied by D. L specifies the length of
source data with most significant
bits set to zero.

WC =
LB/RB =
LB/RB =

Register to Register

o

23

78

101115

I I

I

IV Bus to Register:

o

23

78

10 11

SC

Instruction
Input and
Data
ProceSSing

o if

o

I

23
0

78

I s I

L

S;o!07,17,20-37 8

0=20-378

IV Bus to IV Bus:

r
ADD

0

'(

s

Move contents of register specified
by S to the IV bus. Before placement
101115 on IV bus, data is shifted as specified by D, and L bits merged with
I 0 I destination IV bus data.

'I

L

Move right rotated IV bus data
(sources) specified by S to the IV
bus. Before placement on IV bus,
data is shifted or specified by D and
0 15 merged with original source data.
1
L specifies the length of source
0=20-378 data to be operated on.

10r

SC =
WC =
LB/RB =
LB/RB =

SC

X

X

1 if D = 17
o if D = 07

o

1ifD=07,17

o

o
o

o

AND

2

SAME AS MOVE

(S)/\ (AUX) - D
Same as MOVE but contents of AUX
ANDed with source data.

SAME AS
MOVE

XOR

3

SAME AS MOVE

(S) G> (AU X) - D
Same as MOVE but contents of AUX
exclusive ORed with source data.

SAME AS
MOVE

XEC

4

Register Immediate:

Execute instruction at current page
address offset by I + (S).

4

I

I

s

I

IV Bus Immediate:

23

I

4

I

S=20-37 8

I

Execute the instruction at the address determined by concatenating 8
high order bits of PC with the 5 bit
I
sum of I and rotated IV bus data
(source) specified by S. R/L speci1=00-378
fies length of source data with most
significant bits set to zero. PC is not
incremented.

1011

78

s

=

WC =
LB/RB

o
o

o
o

x

x

o
o

o
o

= 30-37

x
x

Execute the instruction at the ad1=000-3778 dress determined by concatenating 5
high order bits of PC with the 8 bit
sum of I and register specified by S.
PC is not incremented.

S,..07,17,20-37 8

0

I

1

o if S = 20-27 o if D = 20-27
1 if S = 30-37 1 if D = 30-37

SAME AS
MOVE

I

o

o

o

(S) plus (AU X) - D
Same as MOVE but contents of AUX
added to the source data. If carry
from most significant bit then
OVF = 1, otherwise OVF = 0

SC

o
1 if D = 17
o if D = 07

1
0 if D = 20-27
1 if D = 30-37

SAME AS MOVE

r-0_-=,2r=-3_ _7~8_ _ _~15

o

D = 20-27
1 if D = 30-37

o if

=

WC =
LB/RB =
LB/RB =

1 if D = 07,17

S = 20-27
1 if S = 30-37

O;o! 10,20-378
Register to IV Bus:

o

o

=

Address/IV
Bus Output

L

I

15

I

Table 2

SC =
WC=
LB/RB =
LB/RB =

o if S = 20-27
1 if S

INSTRUCTION SET SUMMARY

!itgDotiC!i

51

8Ml'n.

IPI' it

8X300-1

+-

INSTRUCTION OP
MNEMONIC CODE

NZT

5

FORMATS

Register Immediate:
0

I

23
5

I

78

15

I

s

I

I

S~07.17.20-378

1=000-3778

IV Bus Immediate:
0

I

23
5

78

1011

XMIT

6

15

Is I I I
L

S=20-378

I

1=00-378

Register Immediate:
23

0

I

6

I

78

p

15

I

Address/IV
Bus Output

If (S) = 0, jump to current page address offset by I; if S = 0, PC + 1 ....
PC
If contents of register specified by S
is non zero then transfer to address
determined by concatenating 5 high
order bits of PC with I; if contents of
register specified by S is zero, increment PC.

SC =
WC=
LB/RB =

0
0
x

0
0
x

If right rotated IV bus data (source)
is Non Zero then Transfer to address
determined by concatenating 8 high
order bits of PC with I; if contents of
register specified by S is zero, increment PC.

SC =
WC=
CB/RB =
CB/RB =

0
0
o if S = 20-27
1 if S = 30-37

0
0
x

SC =

0

1 if 0 = 07,17

WC=
LB/RB =
CB/RD =

0
x
x

0
1 if 0 = 17
o if 0 = 07

SC =
WC=
LB/RB =
LB/RB =

0
0
o if 0 = 20-27
1 if 0 = 30-37

0
1
o if 0 = 20-27
1 if 0 = 30-37

SC =

0

0

WC=
LB/RB =

0
x

0
x

Transmit I .... 0

Transmit and store 8 bit binary pat] tern
I to register specified by D.

I

D 110, 20-378

I/O CONTROL
SIGNALS

DESCRIPTION

INSTRUCTION CYCLE ....

Instruction
Input and
Data
Processing

1=000-3778

X

IV BUS IMMEDIATE
23

0

78

1011

15

I I I I I
6

0

L

0=20-378

I

1=00-378

Transmit binary pattern I to IV bus.
Before placement on IV bus, literal
I is shifted as specified by 0 and L
bits merged with existing IV bus data.

Address Immediate:

JMP

7

0

23

I I
7

15

I

A

A = 00000-177778

NOTE
1. RB is complement of LB.
2. "0" = Low voltage
"1" = High voltage
x = Don't care

Table 2

Jump to Program Address A
Jump to program storage address
A. A is stored in the address register
(AR).
INSTRUCTION SET SUMMARY (Cont'd)

INTERPRETER PACKAGE DIMENSIONS

~

II-

2.50

25 "ADS .100 CENHRn. .,

"\-

-----==i I ."

[:::::::::::::::::::::]

3° TO 7° ~

~

~

.07_1~

.15~ ~

Iron

Wi]
.018

52

SmDHtiCS

TYP.-I~ .13

INTERPRETER

aXlIIO
8X300-1

SAND/OR D
FIELD
SPECIFICATION
(OCTAL)
00
01 to 06
07
10
11
17
2N
(N = 0,1,2,
3,4,5,6,7)

INTERPRETER
INTERNAL REGISTERS
SOURCE/DESTINATION

Programmable Registers (all 8 bits):

Auxiliary Register (AUX)
Work registers (R1 to R6) respectively
IVL write-only "register" (destination only)
Overflow status (OVF)-source only
Working register (R11)
IVR write-only "register" (destination only)

AUX - General working register. Contains second term for arithmetic
or logical operations.

a. If a source, IV bus data right rotated (7-N) bits and masked
(specified by R/L). LB = 'low' and RB = 'high' generated.

IV Bus Source Data
4
6
1
2
3
5

0

7

I I I I I I I -Il

cI

IV Bus Destination Data
2
3
4
5
6
1

3N
(N = 0,1,2,
3,4,5,6,7)

0

a. If a source, IV bus data right rotated (7-N) bits and masked
(specified by R/L). LB = 'high' and RB = 'low' generated.

IV Bus Source Data
4 5
1
2
3
6

0

rI

I

7

-I]

I I I I I I

b. If a destination, IV bus data left shifted (7-N) bits and
merged (specified by R/L). LB = 'high' and RB = 'low'
generated.

0

IV Bus Destination Data
1
2
3
4
5
6

- General working register

R3

- General working register

R4

- General working register

R5

- General working register

R6

- General working register

Address Register (AR)
- A 13-bit register containing the
address of the current instruction.
OVF - The least-significant bit of this
register is used to reflect overflow status resulting from the
most recent ADD operation (see
Instruction Set Summary).
Program Counter (PC)
- Normally contains the address of
the current instruction and is
incremented to obtain the next
instruction address.
Instruction Register (IR)
- Holds the 16-bit instruction word
currently being executed.

Table 4

7

-I' I I I I I I I I·
Table 3

R2

Other Registers:

7

-I • I I I I I I I I·

- General working register

R11 - General working register

b. If a destination, IV bus data left shifted (7-N) bits and
merged (specified by R/L). LB = 'low' and RB = 'high'
generated.

0

R1

0

DATA SOURCE DESTINATION ADDRESS

S!!Inotics

53

INTERDR' II R

8X 11.0
8X300-1

System Clock

SYSTEM DESIGN USING

THE INTERPRETER

The Interpreter has an integrated oscillator
which generates all necessary clock signals. The oscillator is designed to connect
directly to a series resonant quartz crystal
via pins X1 and X2. The crystal resonant
frequency, f, is related to the desired cycle
time, T, by the relationship f = 2/T. For a
250ns system, f = 8.00MHz.

Designing hardware around the 8X300 Interpreter reduces to selecting a program
storage devicer (ROM, PROM, etc.), selecting I/O devices (IV byte, multiplexers, RAM,
etc.), selecting clock mode (system driven
or crystal controlled) and interfacing the
Interpreter to these components, as shown
in Figure 3.

In lower speed applications where the cycle
time need not be precisely controlled, a

capacitor may be connected between X1
and X2 to drive the oscillator. Approximate
capacitor values are given in Table 6. If
cycle time is to be varied, X1 and X2 should
be driven from complementary outputs of a
pulse generator. Figure 4 shows a typical
configuration. For systems where the Interpreter is to be driven from a master clock,
the X1 and X2 lines may be interfaced to
TTL logic as shown in Figure 5.

Type:

Fundamental mode, series resonant

Impedance at Fundamental:

35 ohms maximum

Impedance at harmonics and spurs:

50 ohms minimum

Table 5

CRYSTAL CHARACTERISTICS

EXAMPLE OF CONTROL SYSTEM
+5V

SIGNETICS
8T32/33 IV BYTES

RESET HALT
C)
0

)
..... A4-A12
.1

.......
SIGNETICS
82S215
512x8
ROM

t~

110 - 17
f--

V CC

'J~~

VR

T

UDO-UD7

.1

r-

..l..

VCR

ME

I

A4-A12

-

>

IV BYTE 1

l

CE 2 CE 1

.1

....

....
~

IVBO-IVB7

STROBE
8X300
INTERPRETER

AO-A3

-

"-

r

~

.A.

SIGNETICS
82S215
512x8
ROM

~ID

A4-A12

115

MCLK,
SC, WC

LB

~

IV BYTE 2

UDO-UD7

;>

......,

,...

I

Xl~~~

RB

~

ME

GNI

8.00 MHz

l

I

.... BIC

.... BOC
~

18-115

"

UDO-UD7

;>
IV BYTE 3
CE 2 CE 1
~
ME

---<

+50

256X8
RAM

Si!lnDtics

~

""
UDO-UD7

-

...

BIC
BOC

>

-ME

I
Figu're 3

....
~

IV BYTE 4

--=---"
ME

54

1

...

A

-==

l

I

....
....

BIC
BOC

BIlOQ

IN I LRPRETER

aX300-1

Cx,pF

CYCLE TIME

100
200
500
1000

300ns
500ns
1.1J,1s
2.0J,1s

Table 6

CLOCKING WITH A PULSE GENERATOR

+

1~

PULSE
GENERATOR

CLOCK CAPACITOR VALVES

-

-'"'

i~

PULSE GENERATOR CHARACTERISTICS:
V OUT = 0-1 VOLT
ZOUT = 50D.
RISETIME': 10ns
SKEW <: 10ns
COMPLEMENTARY OUTPUTS

Halt, Reset Signals

X1

INTERPRETER
X2

-

NOTE: ALL RESISTORS VALUES ARE TYPICAL AND IN OHMS.

HALT:
A low level at the HALT input stops internal
operation of the Interpreter at the start of
the next instruction after HALT is applied
(quarter cycle after MCLK). Since HALT is
sampled at the start of each instruction
cycle it is possible to prevent a cycle by
applying HALT early in that cycle. HALT
does not inhibit MCLK or affect any internal registers. Normal operation begins with
the next complete cycle after the HALT
input goes high.

RESET:
A low level at the RESET input sets the
program counter and address register to
zero. While RESET is low MCLK is inhibited. If RESET is applied during the last 2
quarter cycles, the MCLK during that cycle
may be shortened. RESET should be applied for 1 full instruction cycle time to assure proper operation. When RESET input
goes high an MCLK occurs prior to the resumption of normal processing. RESET
does not affect the other internal registers.

Figure 4

CLOCKING WITH TTL

>O--'V'v"v---+-----i X 1
CLOCK

~--~~-~-~X2

TTL DRIVER CHARACTERISTICS: 100n
RISETIME AND FALL TIME < 10ns
SKEW BETWEEN COMPLEMENTARY
OUTPUTS < 10ns

SYSTEM TIMING
In systems with fast instruction cycle times,
most I nterpreter delays are strictly determined by internal gate propagation delays.
Since some events are constrained to occur
in certain quarter cycles, as system cycle
times become slower, the delays will appear to increase due to gating with internal
clocks. In the table of AC Electrical Characteristics, 2 columns are used: 1 to denote
times which occur due to internal clock
intervention and 1 to denote minimum delays for fast cycle times.

-=-

Figure 5

SYSTEM INSTRUCTION CYCLE TIME

I
MCLK _ _

-.II

SC, WC, LB, or RB

EXAMPLE:
A specific example of a control system,
using the 8X300 Interpreter-four 8T32/33
IV Bytes, and two 82S215 ROMs is shown in
Figure 3. Only 8 components are required to
build this system which contains 512 words
of program storage, 32 TTL I/O connection
points, and operates at a 250ns instruction
cycle time.

INTERPRETER

IVO-7

I

\~----~--------~~~----..

-,-:-1-=
I

I
I

I

I

I

I

G) MCLK to LB/RB (input phase)
~

or instruction to LB/RB
(input phase) .
IV Byte output enable (TOE) .

@

1/2 cycle· 55ns.

1~@~·55ns"'l

Figure 6

When using Signetics aT32/33/35/36 IV
Bytes, selection of instruction cycle time
involves calculating the maximum program
storage access time. Assuming the instruction is available when MCLK falls, the I/O
control lines are stable 35ns later. Signetics
IV Bytes require another 35ns to disable a
previously selected byte and enable the
desired byte (assumes a change in bank
signals). A 10ns margin has been added to
the IV Byte enable for this evaluation to
reflect the fact that most systems will have
more capacitive loading than the 50pF test

SmootiCS

condition in the IV Byte specification and
to allow for line delays.
The system instruction cycle time for·normal systems such as shown in Figure 7 is
determined by Interpreter propagation delays, program storage access time, and IV
Byte output enable times. Instruction cycle
time is normally constrained by one or
more of the following conditions:
1. Instruction to LB/RB (input phase) and IV Byte
output enable:
T OE ~ % cycle - 55ns (Figure 6).

55

I'll R REIFR

81300
8X300-1

2. Program storage access time and instruction to
LB/RB (input phase) and IV Byte output enable
and IV data (input phase) to address ~ instruction cycle time (Figure 7).
3. Program storage access time and instruction to
address ~ instruction cycle time (Figure 8).

SYSTEM INSTRUCTION CYCLE TIME

The first constraint can be used to determine the minimum cycle time. Using the
inequality 35ns + 35ns ~ % cycle - 55ns
implies 112 cycle;:: 125ns or an instruction
time of 250ns.

I

I
ICD Program storage access time.

Program storage access time for a 250ns
instruction cycle can be calculated from
the second constraint. Noting that the
specification for IV data (input phase) to
address is 115ns: Program storage access
time + 35ns + 35ns + 115ns:$ 250ns implies
program storage access time ~ 65ns.

1

3

6

5

4

7

1111111 LL

Figure 7

SYSTEM INSTRUCTION CYCLE TIME

--MCLK~II \I_~.......--I
\~
10-115

~R/L~2

I I I I I I
I I I ~1.__lo(_ _ _ _ _ :~~::
....

..... '

w.x-+--

_~!

AO-A12

""
.1
.

~

I

_,

I

!~!

R/L ~3

I I .----------R/L~6
..
.......
I ,.....------------- 0

!~d~:!~. (input phase)

I@

..... '

2

IV Byte output enable (T OEI.

I

The third constraint can be used to verify
the maximum program storage access
time. Noting that the specification for instruction to address is 185ns: Program
storage access time + 185ns ~ 250ns confirms that program storage access time
65ns is satisfactory.

o

MCLK to LB/RB (input phase)
or instruction to LB/R B
(input phase).

I

R/L~7

I

!

R/L~

IV BUS DATA
LENGTH SPECIFICATION

I

-.-

I

I

I

I

I

I
I
I

I

I

Figure 9

I

,

I
Figure 8

56

Si!lDotiCS

I

I

I

INSTRUCTION TO
PROGRAM STORAGE
ADDRESS
---....- I
ACCESS I .....

I
I

I

I

I

I

I

,

to

INTERPRETER

81300
8X300-1

ABSOLUTE MAXIMUM RATINGS

TYPICAL INSTRUCTION CYCLE TIMING

I

Supply Voltage VCC ................................. 7V
LogiC Input Voltage ............................... 5.5V
Crystal Input Voltage ............................... 2V

·1

INSTRUCTION CYCLE

:_,NPUT,PHASE _ _ I_OUTPUT PHASE---:_INPUT PHASE
I INST& IV BUS I
I INPUTS ACCEPTEO

MCLK
INSTRUCTION
ADDRESS
IAO-A121

I

I

I

1

~1

OATA
PROCESSING

AOORESS& IV I AOORESS& IV I
BUS CHANGING I BUS OUTPUT STABLIE

. ,
I

I

Y

i

I

\

I

1"----

1~!

i

:

I
I ADDRESS STABL~--I
RPROGRAM
II
I-----MCLK"(O
S~~~:~SE---y
I I_'NSTRUCTIONTOADDRESSST~BLE-1
1
I
I
I
1
I

INSTRUCTION
(lo~~i~

--:'X
-----+'
,'--___ !

.;..!_ _ _

-+"---

1

_I
_ _-1-1--.
SC/WC

1"--

~

1

1

---t-I
I

\

MCLK TO SC/WC
OUTPUT CONTROL
MCLK;O SC/WC
INPUT CONTROL

1-

--1-:-..JX

1_ _- - -

LB/RB

I
I

I

I

/

I

I

.

INSTRUCTION TO
LB/RB INPUT CONTROL

MCLK TO LB/RB -~--I'
OUTPr CONTROL
X~------';""---'X=

1- INPU,T
MCLK TO LB/RB
CONTROL

-----'1

I

_ _
~/I~'L__
I
I

1

I

I 1---INSTRu6T1oN TO IV BUS STA~LE
1

IV BUS
IIVSO-IVB7)

i

I

1

~i\j 1

III

1

l -----.l
~}-----+---------~
I

IV BUS TO

~ ADDRESS STABLE

I

I-----MCLK TO IV BUSSTABLE
----TI
I_ ' INPUTIV BUS
ACTIVE
I/O----+DEVICE
ACCESS

~

1

I

1 - OUTPUT
IV BUS
-ACTIVE

I

CROSS HATCHED
AREA INDICATES
IV BUS TRISTATE
SOLID AREA
INDICATES
CHANGING
DATA

Figure 10

AC ELECTRICAL CHARACTERISTICS vcc
DELAY DESCRIPTION

= 5V ± 5% and O°C ~ T A < 70°C

PROPAGATION
DELAY TIME

X1 falling edge to MCLK (driven from external
pulse generator)
MCLK to SC/WC falling edge (input phase)
MCLK to SC/WC rising edge (output phase)
MCLK to LB/RB (input phase)
Instruction to LB/RB output (input phase)

-

~

CYCLE TIME
LIMIT

75ns
25ns

% cycle

+ 25ns

35ns
35ns

MCLK to LB/RB (output phase)
MCLK to IV data (output phase)

185ns

IV data (input phase) to IV data (output phase)
Instruction to Address
MCLK to Address
IV data (input phase) to Address
MCLK to IV data (input phase)
MCLK to Halt falling edge to prevent
current cycle
Reset rising edge to first MCLK

115ns
185ns
185ns
115ns

% cycle + 35ns
% cycle + 60ns

Y2

cycle + 40ns
+ 40ns

% cycle

% cycle - 55ns
% cycle - 40ns

o to 1 cycle

NOTE
1. Reference to MCLK is to the falling edge when loaded with 300pF.
2. Loading on Address lines is 150pF.

!ii!ln~tiC!i

57

INTERPRETER

8X]00
8X300-1

DC ELECTRICAL CHARACTERISTICS
LIMITS
PARAMETER

TEST CONDITIONS

UNIT
Min

V'H

V ,L

High level input voltage
X1,X2
All others

Input clamp voltage
(Note 1)

"H

High level input current
X1,X2
All others
Low level input current
X1,X2
IVBO-7
10-115
HALT, RESET

VOL Low level output voltage
AO-A12
All others
V OH High level output voltage
'OS

.6
2

Short circuit output current
(Note 2)

Supply current

I REG Regulator control

'CR

V
V

V CC = 4.75V
" = -10mA

Regulator current (Note 3)

VCR Regulator voltage (Note 3)

V
V

-1.5

V

2700
<1

50

JJA

V CC = 5.25V
V IL = .4V
V cc = 5.25V
V ,L =.4V
V CC = 5.25V
V IL = .4V
V cc = 5.25V
V IL = .4V

-2500
-140

-200

JJA
JJA

-880

-1600

JJA

-230

-400

JJA

V CC = 4.75V
I OL = 4.25mA
V CC = 4.75V
'OL = 16mA

.35

.55

V

.35

.55

V

V CC = 4.75V
'OH = 3mA
V CC = 5.25V

2.4

V

-30
4.75

V CC = 5.25V
V CC = 5.0V

JJA

-140

mA

5

5.25

V

300

450

mA

-21

mA

290

mA

3.2

V

-14

VCR = 0
V

REG

= OV

2.2

NOTES
1. Crystal inputs X1 and X2 do not have clamp diodes.
2. Only one output may be grounded at a time.
3. (Limits apply for VCC = 5V ± 5% and ODC < T A < 70 DC unless specified otherwise.)"

58

.4
.8

V CC = 5.25V
V ,H = .6V
V CC = 5.25V
V IH = 4.5V

VCC Supply voltage
ICC

Max

Low level input voltage
X1,X2
All others

VCL

',L

Typ

Si!lnntics

8X 31104 S11 II IS S

MeeA' 81300 CROSS ASSEMBLER

DESCRIPTION
The MicroControlier Cross Assembly Program (MCCAP) is a program designed to
translate symbolic instructions into object
code that can be executed by the 8X300.
This program will run on most computers
that have a Fortran compiler with a computer word length of at least 16 bits and a
random access I/O capability; it can be run
on most minicomputers as well as large
scale computers.
The Assembler is written in Fortran. This
provides compatibility with most computer
systems and makes it transportable. The
program is modular and uses a minimum of
memory. However, it may be operated in an
overlay mode if necessary.

The Assembler is a two-pass program that
issues helpful error messages and produces
an easily read program listing. An object
module may be loaded into the SMS MicroController Simulator (MCSIM), the SMS
ROM Simulator 1000A, or used to produce
ROMs or PROMs.
The Assembler features symbolic addressing, forward references and expression
evaluation. It also has the capability to symbolically represent the Interface Vector (IV).
In addition, the Assembler is capable of
expressing data in several number systems
as well as in ASCII character codes.

MCCAP Output
The output from a MCCAP compilation
includes an assembler listing and an object
module. During pass 2 of the assembly
process, a program listing is produced. The
listing displays ali information pertaining to
the assembled program. This includes the
assembled octal instructions, the user's
original source code and error messages.
The listing may be used as a documentation
tool through the inclusion of comments and
remarks which describe the function of a
particular program segment. The main purpose of the listing, however, is to convey ali
pertinent information about the assembled
program, i.e., the memory addresses and
their contents.
The object module is also produced during
pass 2. This is a machine readable computer
output produced on paper tape. The output
module contains the specifications necessary for loading the memory of the SMS.*

FEATURES
• 9 track EBCDIC tape
• Cross Assembler (written in Fortran)
• Flexible Object Format MCSIM
ROM Simulator
ROM Production Format
• Symbolic Addressing
• Forward References
• Expression Evaluation
• Symbolic I/O Representation

Microcontrolier Simulator (MCSIM), for
loading the memory of ROM Simulator, or
for prodUCing ROMs or PROMs. The object
module can be produced in MCSIM, ROM
Simulator or BNPF format.
*Scientific Micro System
520 Clyde Avenue
Mountain View, CA 94043

S!!)DotiCS

59

8 BIT EAICHPn AIJIJRFHSAH' F H'OIRFt:TIONl'l

() PORT

8T12

81311 UT:l5 8136
BT32/BT33/8T35/BT36-NA, F

PIN CONFIGURATION

TYPES

FEATURES

8T32 Tri-State, Synchronous User Port
8T33 Open Collector, SynchronoLis User
Port
8T3S Open Collector, Asynchronous
User Port
8T36 Tri-State, Asynchronous User Port

• A field-programmable address allows 1
of S12 IV Bytes on a bus to be selected,
without decoders.
• Each byte has 2 ports, one to the user, the
other to a microprocessor. IV Bytes are
completely bidirectional.
• Ports are independent, with the user port
having priority for data entry.
• A selected IV Byte de-selects itself when
another IV Byte address is sensed.
• User data input available as synchronous
(8T32, 8T33) or as asynchronous (8T3S,
8T36) function.
• The User Data Bus is available with tristate (8T32, 8T36) or open collector
(8T33, 8T3S) outputs.
• At power up, the IV Byte is not selected
and the user port outputs are high.
• Tri-state TTL outputs for high drive capability.
• Directly compatible with the 8X300 Interpreter.
• Operates from a single SV power supply
over a temperature range of 0° C to 70° C.

DESCRIPTION
The Interface Vector (IV) Byte is an B-bit
bidirectional data register designed to function as an I/O interface element in microprocessor systems. It contains B data latches
accessible from either a microprocessor
(IV) port or a user port. Separate I/O control
is provided for each port. The 2 ports operate independently, except when both are
attempting to input data into the IV Byte. In
this case, the user port has priority.
A unique feature of the BT32/33/35/36 IV
Byte is the way in which it is addressed.
Each IV Byte has an B-bit, field programmable address, which is used to enable the
microprocessor port. When the SO control
signal is high, data at the microprocessor
port is treated as an address. If the address
matches the IV Byte's internally programmed address, the microprocessor port
is enabled, allowing data transfer through it.
The port remains enabled until an address
which does not match is presented, at which
time the port is disabled (data transfer is
inhibited). A Master Enable input (ME) can
serve as a ninth address bit, allowing 5121V
Bytes to be individually selected on a bus,
without decoding. The user port is accessible at all times, independent of whether or
not the microprocessor port is selected.

F,NA PACKAGE
UD7

1

24

VCC

UD6

2

23

IV7

UD5

3

22

IV6

UD4

4

21

IV5

UD3

5

20

IV4

UD2

6

19

IV3

UD1

7

18

IV2

UDO

8

17

IV1

BOC

9

16

IVO

BIC

10

15

WC

ME

11

14

SC

GND

12

13

MCLK

BLOCK DIAGRAM
, OF 8 BIT SLICES

,-----------------,
I
I
I

I
UDQ

I
I
I
I

I

A unique feature of this family is its ability
to start up in a predetermined state. If the
clock is maintained at a voltage less than .BV
until the power supply reaches 3.5V, the
user port will always be all logic 1 levels,
while the IV port will be all logic a levels.

I
I
I
I
I
I
I

L_

I

I
I
_--.J

ORDERING
The BT32/33/35/36 may be ordered in
preaddressed form. To order a preaddressed IV Byte, use the following part
number format:
NBTYY-XXX P
-P= F Ceramic package
NA Plastic package

T
L

XXX= Any address from 000
through 255 (decimal) 256 available addresses
'-----YY= IV Byte version (32, 33,
35,36)
A stock of BT32s and BT36s with addresses 1
through 10 will be maintained. A small
quantity of addresses 11 through 50 will also
be available with a longer lead time.

60

~++++-I-++++--Hf.f+- sc

'-++-+-4-++'>---- wc
1;>------+~_+++-_++-4---+_- MCLK
BOC

ME

'Switch indicates synchronous/asynchronous user write option. Switch shown for synchronous version.

!ii!lDotiC!i

8 BIT LATCHED ADDRESSABLE BIDIRECIIONnL I 0 PORI

8132 8133 8135 8136
8T32/8T33/8T35/8T36-NA, F

PIN DESCRIPTION

H

USER DATA BUS CONTROL

PIN

SYMBOL

NAME AND FUNCTION

1-8

UDO-UD?:

User Data I/O Lines. Bidirectional data lines to
communicate with user's equipment. Either tristate or open collector outputs are available.

Active high

TYPE

16-23

IVO-IV?:

Interface Vector (IV) Bus. Bidirectional data
lines to communicate with controlling digital
system (microprocessor).

Active low
th ree-state

10

BIC:

Byte Input Control. User input to control writing into the IV Byte from the User Data Lines.

Active low

9

BOC:

Byte Output Control. User input to control reading from the IV Byte onto the User Data Lines.

Active low

11

ME:

Master Enable. System input to enable or disable all other system inputs and outputs.
It has no effect on user inputs and outputs.

Active low

15

WC:

Write Command. When WC is high and SC is
low, IV Byte, if selected, stores contents of
IVO-IV? as data.

Active high

14

SC:

Select Command. When SC is high and WC is
low, data on IVO-IV? is interpreted as an address.
IV Byte selects itself if its address is identical
to IV bus data; it de-selects itself otherwise.

Active high

13

MCLK:

Master Clock. Input to strobe data into the
latches. See function tables for details.

Active high

24

VCC:

5V power connection.

12

GND:

Ground.

BOC

MCLK

H
L
L
H

L
X
X
H

X
H
L
X

L

= Low Level

High Level

X

8T32,8T33

8T35,8T36

Output Data
Input Data
Inactive
Inactive

Output Data
Input Data
Input Data
Inactive

= Don't care

Table 1

USER PORT CONTROL FUNCTION

ME

SC

WC

MCLK

BIC

STATUS
LATCH

IV BUS
FUNCTION

L
L
L
L
L
L
L
L
L
H

L
L
H
H
H
X
H
L
L
X

L
H
L
H
H
H
X
H
X
X

X
H
H
H
H
L
L
H
X
X

X
H
X
L
H
X
X
L
X
X

SET
SET
X
X
X
X
X
X
Not Set
X

Output Data
Input Data
Input Address
Input Address
Input Data and Address
Inactive
Inactive
Inactive
Inactive
Inactive

-

Table 2

For the 8T32 and 8T33, User Data Input is a
synchronous function with MCLK. A low
level on the BIC input allows data on the
User Data Bus to be written into the Data
Latches only if MCLK is at a high level. For
the 8T35 and 8T36, User Data Input is an
asynchronous function. A low level on the
BIC input allows data on the User Data Bus
to be latched regardless of the level of the
MCLK input. Note that when 8T35 or 8T36
IV Bytes are used with the 8X300 Interpreter care must be taken to insure that the IV
Bus is stable when it is being read by the
8X300 Interpreter.
To avoid conflicts at the Data Latches,
input from the Microprocessor Port is inhibited when BIC is at a low level. Under all
other conditions the 2 ports operate independently.

INTERFACE VECTOR
BUS CONTROL
As is shown in Table 2, the activity of the
microprocessor port (IV Bus) is controlled
by the ME, SC, WC and BIC inputs, as well
as the state of an internal status latch. BIC is
included to show user port priority over the
microprocessor port for data input.

USER DATA BUS FUNCTION

--

BIC

The activity of the User Data Bus is controlled by the BIC and BOC inputs as
shown in Table 1.

Each IV Byte's status latch stores the result
of the most recent IV Byte select; it is set
when the IV Byte's internal address matches
the IV Bus. It is cleared when an address that
differs from the internal address is presented on the IV Bus.
In normal operation, the state of the status
latch acts like a master enable; the microprocessor port can transfer data only when
the status latch is set.
When SC and WC are both high, data on the
IV Bus is accepted as data, whether or not
the IV Byte was selected. The data is also
interpreted as an address. The IV Byte sets
its select status if its address matches the
data read when SC and WC were both high;
it resets its select status otherwise.

BUS OPERATION
Data written into the IV Byte from one port
will appear inverted when read from the
other port. Data written into the IV Byte from
one port will not be inverted when read from
the same port.

MICROPROCESSOR PORT CONTROL FUNCTION

!ii!)DotiC!i

61

8 B' I LIITCHED ADDRESSABLE BIDIRECT DIAL I 0 PORT

8T32 8T33 8135 BT3&
8T32/8T33/8T35/8T36-NA, F

AC ELECTRICAL CHARACTERISTICS
PARAMETER

INPUT

TEST
CONDITION

UDX
MCLK*
BICt

CL

= 50pF

User output enable

BOC

CL

= 50pF

taD

User output disable

BIC
BOC

CL

= 50pF

tpD

IV data delay (Note 1)

IVBX
MCLK

CL

= 50pF

tOE

IV output enable

ME
SC
WC

CL

= 50pF

taD

IV output disable

ME
SC
WC

CL

= 50pF

tw

Minimum pulse width

tpD

User data delay (Note 1 )

tOE

tSETUP

t HOLD

Minimum setup time

Minimum hold time

Min

Typ

Max

UNIT

25
45
40

38
61
55

ns

18

26

47

ns

18
16

28
23

35
33

ns

38
48

53
61

ns

14

19

25

ns

13

17

32

ns

MCLK
BICt

40
35

ns

UDo
BIC*
IVX
ME
SC
WC

(Note 2)

15
25
55
30
30
30

ns

(Note 2)

25
10
10
5
5
5

ns

UDXo
BIC*
IVX
ME
SC
SC

• Applies for 8T32 and 8T33 only.
Applies for 8T35 and 8T36 only.
o Times are referenced to MCLK for 8T32 and 8T33. and are referenced to BIC for 8T35
and 8T36.

t

NOTES:
1. Data delays referenced to the clock are valid only if the input data is stable at the arrival
of the clock and the hold time requirement is met.
2. Set up and hold times given are for "normal" operation. BIC setup and hold times are
for a user write operation. SC setup and hold times are for an IV Byte select operation.
WC setup and hold times are for an IV Bus write operation. ME setup and hold times
are for both IV write and select operations.

62

LIMITS

!ii!)DotiC!i

8T32 8T33 8T35 8T3G

8 Bit LAIOnED ADDRESSABLE BIDIReCTIONAL I 0 PORT

ST32/ST33/ST35/ST36-NA. F

DC ELECTRICAL CHARACTERISTICS
PARAMETER

VIH
VIL
VIC
VOH
VOL
IIH
IlL
lOS

ICC

v cc = 5V ± 5%,

OcC ~ T A ~ 70 c C unless otherwise specified

TEST CONDITIONS

Input voltage
High
Low
Clamp
Output voltage
High
Low
Input current3
High
Low
Output current 4
Short circuit
UD bus
IV bus
V CC supply current

LIMITS
Typ

Min

Max

UNIT
V

2.0
.S
-1

II = -5mA
VCC = 4.75V

V
2.4
.55

VCC = 5.25V
V IH = 5.25V
V IL = .5V

J.1A
<10
-350

100
-550
mA

VCC = 4.75V
10
20
mA

150

100

V CC = 5.25V

PROGRAMMING SPECIFICATIONS5
PARAMETER
VCCP

ICCp

TEST
CONDITIONS

Programming supply voltage
Address
Protect
Programming supply current

LIMITS
Min

Typ

7.5

Max
S.O

V
V

250

mA

1.0

s

1S.0
14.0

V
V

75
150

mA
mA

.1
100

1

J.1s
J.1S

.5

1

ms

0
VCCP

= S.OV

Max time V CCP > 5.25V
Programming voltage
Address
Protect

17.5
13.5

Programming current
Address
Protect
Programming pulse rise time
Address
Protect
Programming pulse width

UNITS

NOTES
3. The input current includes the tri-statelopen collector leakage current of the output driver on the data
lines.
4. Only one output may be shorted at a time.
5. If all programming can be done in less than 1 second, vee may remain at 7.7SV for the entire
programming cycle.

S!!IDotiCS

63

o PORT

B BIT LATCHED /lDDRESSABLE BIDIRECTIONAL

8T32 BT33 BI35 BT36
BT32/BT33/BT35/BT36-NA, F

ADDRESS PROGRAMMING
The IV Byte is manufactured such that an
address of all high levels (> 2V) on the IV
Data Bus inputs matches the Byte's internal
address. To program a bit so a low-level
input « O.BV) matches, thefollowing procedure should be used:
1.

2.
,3.

4.
5.
6.

Set all control inputs to their inactive
state (BIC = BOC = ME = V CC, SC =
WC = MCLK = GND). Leave all IV Data
Bus I/O pins open.
Raise VCC to 7.75V ± .25V.
After VCC has stabilized, apply a single
programming pulse to the User Data
Bus bit where a low-level match is desired. The voltage should be limited to
1BV; the current should be limited to
75mA. Apply the pulse as shown in
Figure 1.
Return VCC to OV. (Note 6).
Repeat this procedure for each bit
where a low-level match is desired.
Verify that the proper address is programmed by setting the Byte's status
latch (IVO-IV7 = desired address, ME =
WC = L, SC = MCLK = H). If the proper
address has been programmed, data
presented at the IV Bus will appear
inverted on the User Bus outputs. (Use
normal V CC and input voltage for verification.)

After the desired address has been programmed, a second procedure must be
followed to isolate the address circuitry.
The procedure is:
1.

2.

3.

64

ABSOLUTE MAXIMUM RATINGS
RATING

UNIT

-0.5 to +7
-0.5 to +5.5
-0.5 to +5.5
-55 to +125
-65 to +150

Vdc
Vdc
Vdc
°C
°C

PARAMETER
VCC
VIN
Vo
TA
T stg

Power supply voltage
Input voltage
Off-state output voltage
Operating temperature range
Storage temperature range

ADDRESS PROGRAMMING PULSE

~r-\

Vccp

.

I

I

!-lSEC.---1

ADDRESS
PROGRAMMING

PULSE

7'75V

-1L
1

I

90%

1

JL18V

I

10%

- I t,

L

lOOns

<"t, < l~s

1

I

r--<

I
I

ov

ov

lms-I

Figure 1

PROTECT PROGRAMMING PULSE

PROTECT
PROGRAMMING
PULSE

-1LJL
90%

I

1

10%

I

--I t, I- - -

t,

> 100~s

Figure 2

Set VCC and all control inputs to OV.
(VCC = BIC = BOC = ME = SC = WC =
MCLK = OV). Leave all IV Data Bus I/O
pins open.
Apply a protect programming pulse to
every User Data Bus pin, one at a time.
The voltage should be limited to 14V;
the current should be limited to 150mA.
Apply the pulse as shown in Figure 2.
Verify that the address circuitry is isolated by applyi ng 7V to each User Data Bus
pin and measuring less than 1mA of
input current. The conditions should be
the same as in step 1 above. The rise
time on the verification voltage must be
slower than 100l1s.

Si!)DotiCS

1
1

1
I

1--> lms-l

14V
ov

8T32 8133 8135 IT36

8 BIT LATEUED ADDRESSABLE BIDIRECTIBNIlL I B PBRT

BT32/BT33/BT34/BT36-NA, F

PARAMETER MEASUREMENT INFORMATION
LOAD CIRCUIT FOR TRI-STATE OUTPUTS

LOAD CIRCUIT FOR OPEN COLLECTOR OUTPUTS

390n

S1

ALL DIODES
ARE 1N914
OR EQUIVALENT

S2

1

V CC ()---J\/\/'y-O

TEST
POINT
FROM

8~b~~T

---.......- - - i

TEST

1 K,1

L Z H Z .L H·

H
H
L
L
Z
Z

S1
S2
S1
S2
S1
S2

OPEN
CLOSED
CLOSED
OPEN
CLOSED
CLOSED

NOTE: CL includes fixture capacitance.

CLOCK PULSE WIDTH

INPUT WAVEFORM

DATA DELAY TIMES
Input Data Reference

DATA DELAY TIMES
Clock Referenced
BIC

MCLK

INPUT
DATA

~:~; _ _~ _ _ _ _ _ _ _ _- J

OUTPUT
DATA

-- 'po
g~i~uT

!ii!lDotiC!i

__

----II
/'5V

.- 'po ~I

\,-----.5V

--J

65

B BI1 [ATCHED ADDRESSIBI E BIDIRECTIQNAL I

o PORT

BT12 ST33 Blah 813&
BT32/BT33/BT35/BT36-NA, F

PARAMETER MEASUREMENT INFORMATION (Cont'd)
SETUP AND HOLD TIMES

MCLK - - - - - - - - , .

OUTPUT ENABLE AND DISABLE TIMES
(Tri-State Outputs)

CONTROL
OUTPUT

,--------I

)(

LOW LEVEL
r ____
ENABLING

*
1/

\

1.5V

I\

1.5V

'--1-------' I "-----

L'OE---I

/+tOD+1

I
OATA
OUTPUT 1

BIC
- - 'SETUP - - - - - 'HOLD - ' -

~~~~t~NVGEL

'I

I

I

I
I
~~...:........<..~_ _ _ _+I....;;;.:..~~-

-VOL

DATA
OUTPUT 2

WAVEFORM ul is FOR AN OUTPUT WiTH INTERNAL CONDITIONS SUCH THAT THE
OUTPUT IS LOW WHEN THE TRI-STATE DRiVER IS ENABLED. WAVEFORM =2 is FOR
THE OPPOSITE CONDITION.

APPLICATIONS

IV BYTE APPLICATIONS

Figure 3 shows some of the various ways
to use the IV Byte in a system. By controlling
the BIC and BOC lines, the Bytes may be
used for the input and output of data, control, and status signals. IV Byte 1 functions
bidirectionally for data transfer and IV Byte
2 provides a similar function for discrete
status and control lines. IV Bytes 3 and 4
serve as dedicated output and input ports,
respectively.

SIGNETICS
8T32/33 IV BYTES

~

UDO-UD7

IV BYTE 1

r-M1:

I

<

I

>
-0
<)

..

')
V

~

IV BYTE 2

z

[8

0

IVBO-IVB7
SIGNETICS
8X300
INTERPRETER

It
'f MCLK,

SC,WC

~

ME

I

t--

u

I

-0
,...
.....

~

VCC

BO~

BIC

-1)
y

IV BYTE 4

ME

Si!lDotiCS

~

UDO-UD7

VCC

mc-L

Figure 3

66

BOC

u

0

CI)

UDO-UD7
IV BYTE 3

ME

z
z

a:
w

~

RB

w

BIC

BOC

::>

~
V

BUS EXPANDER

8T39
aT39-I,XL

DESCRIPTION
The Bus Expander is specifically designed
to increase the I/O capability ofaX300 systems previously limited by fanout considerations. The bus expander serves as a buffer
between the aX300 and blocks of I/O devices. Each bus expander can buffer a block
of 161/0 ports while only adding a single
load to the aX300.

FEATURES
•
•
•
•

15ns propagation delay
Bidirectional
Three-state outputs on both ports
Pre-programmed address range

APPLICATIONS
The aT39 Bus Expander is designed to be
used with the aX300 microprocessor to
allow increased I/O capability in those systems previously limited by fanout considerations. Figure 1 shows a typical arrangement of the bus expander in an aX300
system. Each expander services I/O ports
whose address is within the range of the
expander. Other I/O ports or working storage may be directly can nected to the bus as
shown.
The bus expander is not limited to use with
the aX300, but may be applied in any system
which uses a combined address/data bus.

ST39 ADDRESSING
During normal operation of the aX300 when
an I/O port address is being sent on the IV
Bus (SC is high), the I/O port will examine
all eight bits of the IV Bus for an address
compare. Since the aT39 is used to buffer
blocks of I/O ports, only the four most
significant bits are examined by the aT39 for
an address compare.
Note that redundant addresses are not programmed into separate devices. Rather, a
discrete device (such as the aT39-03) may
be wired for any address requiring two 1 bits
and two 0 bits in the address. The various
address ranges for this same device are
obtained by permuting the high order (010
and 000 are MSB) data lines accordingly.
Both input and output lines must be redefined in order to maintain data and address
integrity on the extended bus. Table 1 summarizes the aT39 addressing.

Address functions are specified with the
convention that bit 0 is the MSB and bit 7 is
the LSB. The 01 bus address decoding is
active low.

NaT39-XXP

Lp =

L

{I - Ceramic Package
XL - Epoxy Package

Address Range As Determined
From Table 1

I,XL PACKAGE

FUNCTIONAL DESCRIPTION
The Bus Expander contains eight sets of
non-inverting bidirectional tri-state drivers
for the bus data bits, four non-inverting
unidirectional drivers for I/O port control,
and necessary control logic. The control
logic is required to maintain the proper
directional transfer of bus data as dictated
by the states of the I/O port control signals
and the currently enabled I/O port. Each
bus expander is programmed during manu-:facturing to respond to a specific block of
I/O port addresses. Only I/O ports with
addresses in the range of a given bus expander may be connected to that expander.
A bus expander may be used on either left
bank or right bank. Multiple expanders on
the same bank must have different address
ranges; however, expanders with the same
address range can be connected if they are
on different banks. Systems may be configured with I/O ports connected directly to the
aX300, as well as I/O ports connected
through a bus expander; however, no un-

1/0 Port Side

8X300 Side

buffered I/O port may have an address
within the span of a bus expander on the
same bank.

PIN DESIGNATION
PIN NO.

TYPE

NAME & FUNCTION

SYMBOL

2-7,9,10

000-007

I/O port data bus

Active low,
three-state

11

WC(OUT)

Write control output

Active high

12

SC(OUT)

Select control output

Active high

13

MCLK(OUT)

Master clock output

Acitve high

14

ME(OUT)

Master enable output

Active low

15

ME(IN)

Master enable input

Active low

16

MCLK

Master clock input

Active high

17

SC(IN)

Select control input

Active high

1a

WC(IN)

Write control input

Active high

19,20,22-27

010-017

Microcontroller data bus

Active low,
three-state
Active low,
three-state

1,a,21

GND

Ground

2a

VCC

+5 volt supply

ABSOLUTE MAXIMUM RATINGS
PARAMETER

ORDERING INFORMATION
The Bus Expander is ordered by specifying
the following part number:

PIN CONFIGURATION

RATING

UNIT

VCC

Power supply voltage

-0.5 to +7

Vdc

VIN

Input voltage

-0.5 to +5.5

Vdc

Vo

Off-state output voltage

-0.5 to +5.5

Vdc

TA

Operating temperature range

T stg

Storage temperature range

Si!)DotiCS

o to

+70

-65 to +150

°c
°c

67

BUS [)[PANDER

8139
BT39-I,XL

Addition of bus expanders may impact system cycle time due to the added delay in the
data path. For the purposes of calculating
allowable cycle time as described in the
BX300 data sheet, the bus expander delays
may be considered additive to the I/O port
delays so that a buffered I/O port simply
appears as a slower I/O port.

TRUTH TABLE
ME

SC

L

L

L
L

WC MCLK

SELECT
LATCH

DATA TRANSFER
DIRECTION

ADDRESS*
COMPARISON

L

X

Set

01 Bus .... DO Bus

No

L

L

X

Not set

01 Bus ..... DO Bus

No

L

H

X

X

01 Bus ..... DO Bus

No

L

H

X

L

X

01 Bus ..... DO Bus

No

L

H

X

H

X

01 Bus ..... DO Bus

Yes

H

X

X

X

X

01 Bus - DO Bus

No

NOTES
'When an address comparison is made, the select latch is set if the data on the 01 Bus is within the
manufactured address range of the IV Bus Expander. Otherwise, the select latch is cleared.

BLOCK DIAGRAM
DO;

SC

El

wc
ME

ONE CHANNEL
OF EIGHT
SC (OUT)

01;

WC (OUT)

ME

(OUT)

NOTES
'Selection made during manufacture
X = Don't care

PART TYPE

BT39-00
BT39-01
BT39-03
BT39-07
aT39-17

ADDRESS PATTERN
MSB(O) LSB(7)

ADDRESS BLOCKS
(Decimal)

OOOOXXXX
0001XXXX
0011XXXX
0111XXXX
1111XXXX

16-31,32-47,64-79,12B-143
4B-63, BO-95, 144-159,96-111,160-175,192-207
112-127,176-191, 20B-223, 224-239

0-15

Table 1 8T39 ADDRESSING SUMMARY

68

S!!Inotics

240-255

8T39

BUS EXPANDER

8T39-I,XL

TEST LOAD CIRCUIT

TYPICAL APPLICATION USING 2 BUS EXPANDERS
TO GIVE 33 1/0 PORTS PLUS WORKING STORAGE

BUS EXPANDER

BUS EXPANDER

1/0 PORT

Address 20, - 37,

Address 40, - 57,

Address 6

WORKING
STORAGE

Type for All resistors values are typical and in ohms.

16110 PORTS

16110 PORTS

Addresses
20, . 37,

Addresses
40, - 57,

BIC BOC

USER
DATA

NOTES
A. CL includes probe and jig capacitance.
B. All diodes are 1N916 or 1N3064.

Figure 1

DC ELECTRICAL CHARACTERISTICS
PARAMETER

VIL
VIH
VIC

TEST CONDITIONS

Input voltage
Low
High
Clamp

2.0
-1

IlL
IIH
lOS
ICC

Short circuit output current
Supply current

V CC
V CC

tpd

Data

tpd

Control

V
.55
2.4

VCC = 5.25V
VIL = .5V
V IH = 5.25V

AC ELECTRICAL CHARACTERISTICS

Path delay

UNIT

Max

V

VCC = 4.75V
10L = 16mA
10H = -3.2mA

PARAMETER

LIMITS
Typ

.8

Output voltage
Low
High
Input current
Low
High

VOL
VOH

Min

VCC

= 5V

= 4.75V
= 5.25V

uA
< 10

-40

± 5%, O°C ~ T A ~ 70°C, CL

TO

FROM

DOX
DIX

DIX
DOX

ME (out)
MCLK (out)
SC (out
WC (out)

ME (in)
MCLK (in)
SC (in)
WC (in)

TEST CONDITIONS

Si!lDotiCS

-250
100
mA
mA

200

= 300pF
Min

LIMITS
Typ

Max

UNIT
ns

15

15

69

BUS (IPnNDEI

BTS)
BT39-I,XL

VOLTAGE WAVEFORMS
CONTROL PATH DELAY
(THREE-STATE OUTPUTS

DATA PATH DELAY TIMES

INPUT
-----OV

~-----3V

OUTPUT
CONTROL

IN PHASE
OUTPUT
WAVEFORM 1
tZH
WAVEFORM 2

70

S10PEN,
S2 CLOSED
--------'-- -

-

-OV

Sl AND S2 CLOSED

Si!lDotiGS

OUT OF PHASE
OUTPUT

DESIGNER'S EVALUATION KIT FOR
FIXED INS I RIICTION BIPOLIlR MICIOPIOCESSOR

BX300KTIOOSK

DESCRIPTION
The Signetics 8X300 Fixed Instruction Bipolar Microprocessor provides new levels
of high performance to microprocessor
applications not previously possible with
MOS technology.
In the majority of cases, the choice of a
bipolar microprocessor slice, as opposed
to an MOS device, is based on speed. The
8X300 processor, combined with highspeed memory and I/O devices, is capable
of executing all instruction in 250ns.
The 8X300 is optimized for control and data
movement applications. It has a 13-bit address bus for selecting instructions from
program storage and a separate input bus
for entering a 16-bit instruction words. Data
handling and I/O device addressing are
accomplished via the 8-bit Interface Vector
(IV) bus. The IV bus is supported by four
additional control lines and a clock.
The unique features of the 8X300 IV bus and
instruction set permit 8-bit parallel data to
be rotated or masked before undergoing
arithmetic or logical operations. Then, the
data may be shifted and merged into any set
of from 1 to 8 contiguous bits at the destination. The entire process of input, shifting,
processing and output is done in 1 instruction cycle time. The 250ns cycle time makes
the 8X300 ideally suited for high-speed applications.
The evaluation board contains all the elements which a deSigner needs to judge the
suitability of the 8X300 for his systems
applications. Included with the 8X300 are
4 I/O ports for external device interface, 256
bytes of temporary (working) data storage,
and 512 words of prog ram storage, all properly connected to the 8X300 to allow immediate exercising of the board. For this
purpose, the PROMs are preprogramed
with the I/O control, RAM control, and RAM
integrity diagnostic programs. With the remaining PROM space, the designer may
enter his own benchmark, test, or development routines.
The board deSign allows complete flexibility in access to the address, instruction, and
IV busses as well as all controls and signals
of the 8X300. The IV bus, I/O port user
connection, clock signals control lines,
address bus and instruction bus are wired
to output pins, the board edge connector
and flat cable connectors.
The board layout permits variations and/or
expansions of the basic design. In addition
to the access to all signals for transfer off
the board, a wire wrap area is provided so
that the designer may add to the board
circuitry as he desires. The addition may
include memory, additional interfaces, or

special circuits which meet specific user
requirements.
Controls are also provided for diagnostic
and instructional purposes by allowing
various operating modes. In the WAIT
mode, the program may be single stepped
for ease of checkout. The one-shot instruction jamming allows control of the program
start location, changes of program flow,
changing or examining the internal registers, or testing of simple sequences. The
repeated instruction jamming provides a
means of repetitive execution of an instruction so that the I/O bus and the control
lines may be examined without software
changes. In both of these jam cases, the
jammed instruction is selected by boardmounted switches.
1 ea- 8T31 (Bidirectional I/O Port)
2 ea- 8T26A (Quad Bus Transceiver)
4 ea- 74157 (Quad 2-lnput Data Selector)
2 ea- 7474 (Dual DFlip Flop)
2 ea- 7400 (Quad Nand Gate)
1 ea- 7427 (3-lnput NOR Gate)
1 ea- P.C. Board
Misc. Parts
1 ea- Introductory Manual, assembly
instructions, code listings and
schematics

SjgnDtics

FEATURES
• 250ns CPU with Crystal
• 4 I/O Ports (32 Lines)
• 256 Bytes Data Storage
• 512 Words Program Storage
• Run/Wait Control
• Single Step
• Instruction Jamming
One Shot Instruction Jam
Repeated Jam
• All Buses to Output Pins
• Firmware Diagnostics
• Wire-Wrap Area
• Edge Connector
• Flat Cable Connectors
• Wire Wrap Posts for Bus Lines
COST: $299 (Total Value

= $504)

AVAILABILITY
Immediate delivery from Signetics Rep.
or Distributors.
CONTENTS
1 ea- 8X300
8 ea- 82S116 (256 x 1 RAM)
2 ea- 82S115 (512 x 8 PROM)
4 ea- 8T32 Addressable Bidirectional
I/O Port

71

R ; I "'1' I Oi. iii I "I
FllEu IllS ROC liON BIPOLAR MiERa' R"tl sgfJR
F1r C llj H'

+5V

RESET

C)
"'"- A4-A12

SIGNETICS
BT32/33 IV BYTES

HALT
()

C)

2Nrs

~

SIGNETICS
B2S215
512xB
ROM

BY u.IIK IIOUSU

...

UDO-UD7
IV BYTE 1

110- 17
VCC

VR

-ME

VCR

A4-A12

I

CE 2 CE1

...

L

""

BX300
INTERPRETER

AO-A3

.

'-

......

)I

L

~

.... A4-A12

MCLK,
SC,WC
LB

10 115 .......

~

-y

X1G~j

BIC

... BOC

IVBO-IVB7

STROBE

SIGNETICS
B2S215
512xB
ROM

">

~

I--

-

...

...

-

IV BYTE 2

UDO-UD7

>

~

ME
IND

B.O MHz
IB-115

I

I

......

""

...

BIC
BOC

UDO-UD7
">

IV BYTE 3
CE 2 CE,

~
ME

I
---4

+5()

8X300 KIT CONFIGURATION

Auxiliary Circuits
The 8X300 can be used with any bipolar (or
TTL-compatible) ICs. It can directly address 8192 program instruction locations
and up to 512 I/O ports. The memory
paging feature may be employed for larger
working storage. Typical auxiliary circuits
include:
Program Storage
110
8T32/33

8T35/36

8T31
8T39
Working Storage

72

UDO-UD7
IV BYTE 4

~

82S115 (512x8 PROM)
(8-Bit Synchronous
Bidirectional I/O
Port)
(8-Bit Asynchronous
Bidirectional 110
Port)
(8-Bit Bidirectional
I/O Port)
(Quad Bus Extender)
82S116 RAM

Si!lDotiCS

...
...

...

"""256XB
RAM

--=

I

BIC
BOC

... ">

L-

ME

~

I

'"

BIC

~ BOC

SUPPORT SOFTWARE

The Microcontroller Cross Assembly Program (MCCAP) is a program designed to
translate symbolic instructions into object
code that can be executed by the 8X300.
This program will run on most computers
that have a FORTRAN compiler with a computer word length of at least 16 bits and a
random access I/O capability; it can be run
on most minicomputers as well as large
scale computers.
The Assembler is written in FORTRAN
which provides compatibility with most
computer systems and makes it transportable. The program is modular and uses a
minimum of memory. However, it may be
operated in an overlay mode if necessary.
The Assembler is a 2-pass program that
issues helpful error messages and produces
an easily read program listing. During the
first pass, the labels are examined and
placed in a symbol table. Certain errors may
be detected during this pass and will be
displayed on the output listing.
In the second pass, the object code is completed, symbolic addresses are resolved,
and a listing and object module are produced. Certain errors not detected during
the first pass may be detected and displayed
on the listing.
The Assembler features symbolic addressing, forward references and expression
evaluation. It also has the capability to symbolically represent the Interface Vector (IV).

8X300

In addition, the Assembler is capable of
expressing data in several number systems
as well as in ASCII character codes.
MCCAP is distributed in 1 of 4 standard
forms. These distribution forms are described below.

9- Track EBCDIC MagnetiC Tape
This is standard IBM compatible magnetic
tape recorded in 9-track format. The tape is
recorded with 1 source card image per record.
Density:
Record Length:
Block Size:

800 BPI
80 Bytes
80 Bytes (1 record/block)

9- Track ASCII MagnetiC Tape
This form is the same as 9-track EBCDIC
tape except that ASCII character codes are
used with the parity bit a zero.

7- Track BCD MagnetiC Tape
This is standard IBM compatible magnetic
tape recorded in 7-track format. The tape is
recorded in even parity BCD with 1 source
card image per record.
Density:
Record Length:
Block Size:

800 BPI
80 Characters
80 Characters (1 record
/block)

029 Punch Cards
Standard 80 column punched cards,
punched in 029 (EBCDIC) punch codes.

Si!1DOliCS

73

74

!ii!lDotiC!i

CIIAPTIR S
STAnDARD SUPPORT
CIRCUITS

!ii!l0otiC!i

75

76

!ii!lDotiC!i

INTRODUCTION
In addition to the dedicated support circuits
available for the various Signetics microprocessors, Signetics offers a complete line
of standard circuits to complete the design
of a microcomputer system.
A complete line of Schottky-clamped TTL,
read/write memory arrays is offered. All
feature open collector or tri-state output
options for optimi~ation of word expansion
in bused organizations. Memory expansion
is further enhanced by full on-chip address
decoding, chip enable function and PNP
input transistors which reduce input loading requirements. All devices offer high
performance read access and write cycle
times making these devices ideally suited in
high speed memory applications such as
"cache," buffers, scratch pads, writable
control store, main store, etc.
Signetics offers the industry's broadest line

of bipolar high performance ROMs, PROMs
and FPLAs. The PROMs and FPLAs are field
programmable, which means that custom
patterns are immediately available by following the provided fusing procedures. Signetics PROMs are supplied with all outputs
at logical O. Outputs are programmed to a
logic 1 at any specified address by fusing a
Ni-Cr link matrix. All bipolar ROMs, PROMs
and FPLAs are fully TTL compatible, and
include on-Chip decoding and chip enable
functions for ease of memory expansion.
Tri-state and open collector output functions are available, and low input currents
reduce input buffer requirements. Most Signetics PROMs and FPLAs also have pin and
performance compatible ROMs and PLAs,
offering the user the ultimate in flexibility
and cost reduction.
Signetics n-channel MaS products include
a complete family of 1K static RAMs and 8K

Si!lDOliCS

static ROMs. These feature TTL compatible
inputs and outputs, and require only a
single +5V power supply. A variety of 4K
dynamic RAMs is also available for system
configurations requiring large amounts of
read/write memory.
The 8T series of interface devices includes
display drivers, bus drivers, input/output
ports, level converters, and special purpose
devices. A complete line of standard and
low power Schottky (LS) 74 series devices is
available in addition to the 8200 series of
MSI devices. Many devices from the Signetics analog product line are also suitable for
use in microcomputer systems. These include voltage regulators, operational amplifiers, comparators and timers.
This chapter provides product line summaries and data for a representative selection
of Signetics standard support circuits. Further information can be found in the Signetics Data Manual.

77

BIPOLAR MEMORIES PRODUCT SUMMARY
DEVICE
CAMS
8220
10155

DESCRIPTION

SAMS
82S12
82S 112
RAMS
82S21
82S25
54174S89
54174S 189
3101A
82S16
82S17
82S116
82S 117
54/74S200
54/74S201
54/74S301
82S09
10144
82S10
82S11
93415A
93425A

CONFIGURATION

OUTPUT**

MAXIMUM
TAA Ins)

TEMPERATURE
RANGE*

8-Bit CAM
16-Bit CAM

4x 2
8x 2

OC
OE

40
13

C
C

32-Bit SAM
32-Bit SAM

8x4
8x4

OC
TS

35
35

C
C

64-Bit
64-Bit
64-Bit
64-Bit
64-Bit
256-Bit
256-Bit
256-Bit
256-Bit
256-Bit
256-Bit
256-Bit
576-Bit
256-Bit
1024-Bit
1024-Bit
1024-Bit
1024-Bit

RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM

32
16
16
16
16
256
256
256
256
256
256
256
64
256
1024
1024
1024
1024

x2
x4
x4
x4
x4
x1
x1
x1
x1
x1
x1
x1
x9
x1
x1
x1
x1
x1

OC
OC
OC
TS
OC
TS
OC
TS
OC
TS
TS
OC
OC
OE
OC
TS
OC
TS

50
50
50
35
35
50
50
40
40
50
50
50
45
30
45
45
45
45

C
M,C
M,C
M,C
M,C
M,C
M,C
C
C
M,C
M,C
M,C
M,C
C
M,C
M,C
M,C
M,C

82S226
82S229
82S230
82S231
82S214
8228
82S215
82S280
82S281
82S290
82S291

1024-Bit
1024-Bit
2048-Bit
2048-Bit
2048-Bit
4096-Bit
4096-Bit
8096-Bit
8096-B it
16,192-Bit
16,192-Bit

ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM

256 x 4
256 x 4
512 x 4
512 x 4
256 x 8
1024 x 4
512 x 8
1024 x 8
1024 x 8
2048 x 8
2048 x 8

OC
TS
OC
TS
TS
TTL
TS
OC
TS
OC
TS

50
50
50
50
60
75
60
125
125

M,C
M,C
M,C
M,C
M,C
C
M,C
M,C
M,C
M,C
M,C

PROMS
82S23
82S123
10139
82S27
82S126
82S129
10149
82S114
82S130
82S131
82S115
82S136
82S137
82S184
82S185

256-Bit PROM
256-Bit PROM
256-Bit PROM
1024-Bit PROM
1024-Bit PROM
1024-Bit PROM
1024-Bit PROM
2048-Bit PROM
2048-Bit PROM
2048-Bit PROM
4096-Bit PROM
4096-Bit PROM
4096-Bit PROM
8192-Bit ROM
8192-Bit ROM

32
32
32
256
256
256
256
256
512
512
512
1024
1024
2048
2048

x8
x8
x8
x4
x4
x4
x4
x8
x4
x4
x8
x4
x4
x4
x4

OC
TS
OE
OC
OC
TS
OE
TS
OC
TS
TS
OC
TS
OC
TS

50
50
20
40
50
50
17
60
50
50
60
60
60
100
100

M,C
M,C
C
C
M,C
M,C
C
M,C
M,C
M,C
M,C
M,C
M,C
M,C
M,C

FPLA
FPLA

16 x 48 x 8
16 x 48 x 8

TS
OC

50
50

M,C
M,C

ROMS

FPLA
82S100
82S101
'TEMPERATURE RANGE
C = Commercial (O°C to +75°C)
M = Military (-55°C to +125°C)
All ECl 10,000 (-30°C to +85°C)

78

"OUTPUT
TS = Tri-State
OC = Open Collector
OE = Open Emitter

Si!lDOliCS

InTIRrACI
LOGIC

DEVICE
ST04
ST05
ST06
ST09
ST10
ST13
ST14
ST15
ST16
ST1S
ST20
ST22
ST23
ST24
ST25
ST26A
ST27
ST2S
ST30
ST31
ST32
ST33
ST34
ST35
ST36
ST37
ST3S
STSO
ST90
ST93
ST94
ST95
ST96
ST97
ST9S
ST363
ST3S0

Data
Book
Page
Ref.

DESCRIPTION

Commercial

Military

7-Segment Decoder/Driver
7-Segment Decoder/Transistor Driver
7-Segment Decoder/Display Driver
Tri-State Quad Bus Driver
Tri-State Quad D-Type Bus Flip-Flop
Dual Line Driver
Triple Line Receiver with Hysteresis
Dual Communications EIA/MIL Line Driver
Dual Communications EIA/MIL Line Receiver
Dual 2-lnput NAND Gate
(High Voltage to TTL Interface)
Bidirectional One Shot
Retriggerable One Shot
Dual Line Driver for IBM 360/370 Interface (75123)
Triple Line Receiver for IBM 360/370
Interface (75124)
Tri-State Dual MOS Sense Amplifier/Latch
Tri-State Quad Bus Receiver
Quad Inverting Bus Driver/Receiver
Tri-State Quad Bus Receiver
Dual TTL/DTL to MOS Transceiver/Port Controller
S-Bit Bidirectional I/O Port
Interface Vector (IV) Byte
Interface Vector (IV) Byte
Quad Bus Transceiver (DMSS34) (Tri-State Outputs)
Asynch. Programmable S-Bit I/O Port, o/c
Asynch. Programmable S-Bit I/O Port (Tri-State)
Hex Bus Receiver with Hysteresis-Schmitt Trigger
Quad Bus Transceiver (Open Collector) (DMSS3S)
Quad 2-lnput NAN D Interface Gate
Hex Inverter Interface Element
High Speed Hex Inverter (PNP Inputs)
High Speed Hex Inverter (Open Collector)
(PNP Inputs)
High Speed Hex Buffers/Inverters (74365/DMS095)
High Speed Hex Buffers/Inverters (74366/DMS096)
High Speed Hex Buffers/Inverters (74367/DMS097)
High Speed Hex Buffers/Inverters (7436S/DMS09S)
Dual Zero Crossing Detector
Quad Bus Receiver with Hysteresis-Schmitt Trigger

•
•
••
•
•
•
•
•
•

•
•
••
•
•

17
20
23
26
29
33
35
3S
40

•

43
45
49
51

!i!!)DotiC!i

•
•
•

•
•
•
DEV
•
•
•
•
•
•
DEV
•
•
•
•
•
•
•
•
•
•
•
••

•

•
•

•
•

53
56
59
N/A
59
62
71
71
71
7S
N/A
N/A
SO
S2
S3
S4
S5
S6
S6
S7
S7
S7
94
97

79

InTERfnOE
ANALOG

DEVICE
754508
754518
754528
754538
754548
MC1488
MC1489/1489A
75S107
74S108
DM7820/8820
DM7820A/8820A
DM7830/8830
DM8880
NE584/585
NE582
3207A
3207A-1
7520
7521
7522
7523
7524
7525
75S207
75S208
75315
75324
75325/55325
75361A

80

DESCRIPTION
PERIPHERAL INTERFACE
Dual Peripheral Driver
Dual Peripheral Driver
Dual Peripheral Driver
Dual Peripheral Driver
Dual Peripheral Driver
Quad Line Driver
Quad Line Receiver
Dual Line Receiver
Dual Line Receiver
Dual Differential Line
Receiver
Dual Differential Line
Receiver
Dual Differential Line Driver
INTERFACE DISPLAY
Display Decoder Driver
Gas Discharge Segment &
Digit Driver
LED Digit Driver
MEMORY INTERFACE
MOS Clock Driver
MOS Clock Driver
Dual Core Memory
Sense Amp
Dual Core Memory
Sense Amp
Dual Core Memory
Sense Amp
Dual Core Memory
Sense Amp
Dual Core Memory
Sense Amp
Dual Core Memory
Sense Amp
Dual MOS Sense Amp
Dual MOS Sense Amp
Core Memory Driver
Core Memory Driver
M emory Driver
MOS Clock Driver

Gi!l00liCG

Commercial

••
•
•
•
•
•
•
•
•
••
•
••
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•

Military

Data
Book
Page
Ref.
121
126
128
130
132
110
112
114
117

•
•
•

103
N/A
105
107
101
99
134
136
144
144
144
144
144
144
138
141
N/A
151
156
170

IN I EltrAcE COMPONENTS

DC ELECTRICAL CHARACTERISTICS
INPUT VOLTAGE
PARAMETER

VIL (V)
LOW LEVEL

V IH (V)
HIGH LEVEL

TEST CONDITIONS
Min
8T26A

Typ
N/A

Max

Min

Typ

Max

VIC
CLAMP VOLTAGE

VOLTAGE RATING

VTL (mV)20
LOW LEVEL
THRESHOLD
VOLTAGE

VCC = MIN
liN = -12mA

V IN = 10mA

VCC = MIN
VIN = O.8V
IOL = -400f.1A

Min

Typ

Max
-1.0

N/A

Min

Typ
N/A

Max

Min

Typ

Max

OUTPUT VOLTAGE
VTH (mV)2o
VOL (V)1
HIGH LEVEL
LOW LEVEL
THRESHOLD
VOLTAGE
VCC = MAX
VIN = O.8V
IOH ~ 16mA
Min

Typ

0.85

VCC = MIN

Max
2

Min

Typ

I Max

I

Driver
IOL =48mA

0.5
Receiver
IOL =20mA

I

8T28

N/A

-1.0

N/A

N/A

0.85

2

0.5

Driver
IOL =48mA
0.5
Receiver
IOL=20mA

I
8T31

N/A

N/A

N/A

liN = -5mA
-1

Si!l0otiCS

N/A

N/A

0.5

IOL=20mA

I 0.55

81

IN I ERFACE COMPO'!EN IS
DC ELECTRICAL CHARACTERISTICS

(Cont'd)

INPUT CURRENT
PARAMETER

V OH (V)
HIGH LEVEL

IlL (rnA)
LOW LEVEL

TEST
CONDITIONS

VCC " MIN
10H = -160iJA

VCC "MAX
V IN "O.4V

Min
8T26A

Typ

Max

Driver
IOL =-10mA
2.4
Receiver
IOL "-10 0IlA
3.5
IOL "-2.0mA

Min

Typ

Max

Driver
LOW Level
-200
LOW Level (Disabled)
-25
Receiver
-200

OUTPUT CURRENT

IIH (iJA)
HIGH LEVEL

lOS
SHORT CIRCUIT
CURRENT

VCC "MAX
V IN "4.5V

VIN " 2.0V

VCC = MAX
VIN "OV
VOUT" OV

Min

Typ

Max

Driver/Receiver

Driver
I OL "-10mA
2.4
Receiver
IOL "-10 0IlA
3.5
IOL "-2.0mA

Driver
LOW Level
-200
LOW Level (Disabled)
-25
Receiver
-200

25

VOUT" 2.4V
100
LOW Level
V OUT " 0.5V
-100

Uriver/Hecelver
25

VOUT" 2.4V
1uu
LOW Level
V OUT " 0.5V
-100

-10

N/A
IOL "3.2mA

2.4

Max

V IN =0.55V
-500

V IN " 5.5V
100

Typ

50

S!!IDotiCS

ICC (rnA)
VIN" 2.0V

VCC "MAX
VIN "OV
COMMERCIAL

VCC" MAX

Max

Typ

Max

Typ

Max

Min

Typ

N/A

457/87

N/A

N/A

578/100

N/A

Max

-150
Receiver

-30

-75

Driver
-50

-150
I

Hecelver

-30

-75

-20

-200

10

20

1. All voltage measurements are referenced to the ground terminal. Terminals not specifically referenced are left electrically open.
2. All measurements are taken with ground pin tied to zero volts.
3. Positive current is defined as into the terminal referenced.
4. Precautionary measures should be taken to insure current limiting in accordance with absolute
maximum ratings.
5. Measurements apply to each gate element independently.
6. Output source current is supplied through a resistor to ground.
7. Output sink current is supplied through a resistor to V cc.
8. Connect an external 1K 1% resistor to the output for this test.
9. Not more than one output shOuld be shorted at one time.
10. Previous condition is a high level output state.
11. Previous condition is a low level output state.
12. Test each driver separately.
13. For more electrical specifications see data sheet.
14. I CC is dependent upon loading. I CC limit specified is for no-load test condition for both drivers.
15. With forced output current of 240I1A, the output voltage must not exceed 0.15V.

ICC
POWER/CURRENT
CONSUMPTION (mW/mA)

MILITARY

Driver

UD Bus
IV Bus

NOTES

82

Min

HIGH Level

2.4
8T31

Min Typ

HIGH Level

2.4
8T28

POWER SUPPLY

ICBO (iJA)
LEAKAGE
CURflENT

N/A

N/A

N/A

N/A

150
100

150

DIIAL COMMUNICATIONS EIA MIL LINE DRIVER

8T15
BT15 A,F

DESCRIPTION

LOGIC DIAGRAM

PIN CONFIGURATION

The BT15 Dual Communications
Line Driver provides line driving
capability for data transmission between Data Communication and
Terminal Equipment. The device
meets or exceeds the requirements of EIA Standard RS-232B
and C, MIL STD-1BBB and CCITT
V 24.

(1)~
(2)

(5)
(3)

(10)2Jo
(4)

This dual 4-input NAND driver will
accept standard TTL logic level inputs and will drive interface lines
with nominal data levels of + 6V
and - 6V. Output slew rate may be
adjusted by attaching an external
capacitor from the output terminal
to ground. The outputs are protected against damage caused by
accidental shorting to as high as
±25V.

(11)

(12)

(13)

VEE = (8) GND = (7)
VCC = (14) ( ) = Denotes Pin Numbers

TA = 25°C, VCC = +12.0V, VEE = -12.0V

ABSOLUTE MAXIMUM
RATINGS*
Input Voltage
Output Voltage

+5.5V
±25V

VCC
VEE
Storage

+15V
-15V

Temperature

-65°C to + 150°C

Operating
Temperature

O°C to +75°C

,.... "-...
r.
~(9)

LIMITS

TEST CONDITIONS
CHARACTERISTICS

INPUTS
OUTPUTS

Output
Output
Output
Output

UNIT

Rise Time 1
Fall Time 1
Rise Time 1
Fall Time 1

Load
Load
Load
Load

A
B
C
D

Output Impedance
(Power on)
(Power on)
(Power off)

may be impaired.

MAX

TYP
4
4

}LS
}LS

ns 200
ns 200

Current from Positive Supply2
Current from Negative Supply2

* Limiting values above which serviceability

MIN

OTHER

DRIVEN

16
28

mA
mA

-3.5±1mA
+3.5±1mA
±2V

O.OV
2.0V

ohms
ohms
ohms 300

95
95
2.5M

Rise and fall times are measured between the +3V and -3V points on the output
waveform.
2 VCC = +12.6V, VEE = -12.6V

1

AC TEST FIGURES & WAVEFORMS
LOADB

LOAD A

LOADC

7k

h
~_------J

::-----lsooPFSHAPING
CAPACITOR

LOADD

3k

h
:p~-----lsOOPFSHAPING
~_------J

+61

+3

o
-3

CAPACITOR

-6

Iil!lnDliCIi

- -

- -

~

I-

- - - - -

- -

J

f- --- -\---1 ~--tfall __

~

=I

f-- trise

83

8115

'''IAI I ''''''"NIOATIO,,5 fill Mi' LINE np"'ER

8T1S A,F

SCHEMATIC DIAGRAM
14

Vee

5k

10k

10k

8k

son

iOk

iOk

iOk

19k

1.73

+------+-__.-----}

51<

MILl-I

MILl>}

12k

12k

51r2

HYST

SmOOliCS

85

ITI'

L "lOAMI" NICAfiLNb Ell Mil [INERE' EliER ."IH ii' it "EalS

8T16 A,F

TA = 250 C and VCC = 5.0V
LIMITS

TEST CONDITIONS
PARAMETER

UNITS

INPUTS

Input Resistance (EIA)
Input Resistance (MIL)
Propagation Delay
Signal Switching Acceptance

EIA

MIL{+)

MIL{-)

±25V
O.OV

O.OV
±25V

O.OV
O.OV

MIN

TYP

3

5
11.4
100

MAX

STROBE

7.5
5.00V
5.00V

7

kD.
kD.
ns
kHz

150

20

1. This test guarantees transfer of signals of up to 20kHz. Connect 1OOOpF between
the output terrninal and ground.

AC TEST FIGURE AND WAVEFORMS

HYSTERESIS CURVES
EIA - "HYSTERESIS" OPEN

+5.0V

l...---.d---~
I
I
GUARANTEED HYSTERESIS

. . . . - : TYPICAL

-'SV

-2v

HY~TERESIS -...;:--~

-1.2V

+2V

+'.2V

+'SV

EIA -"HYSTERESIS" GROUNDED

r· ·~X iJ

GUARANTEED HYSTERESIS

OV

I

jo.75VI

+.9

+6

I, - If .; 20 ns
+3V p.w. " 1 ms

I

!

I.: !.

+,.ov

+'.7V +2.1V

I

PROPAGATION DELAY

,.
+3.0V

-.9

MIL

VOUT

MIL - HYSTERESIS

t
L...----L---.J
I
I

EIA

vout

SIGNAL SWITCHING ACCEPTANCE

GUARANTEED HYSTERESIS

I
l

. . . ._ _-!-i

I

TYPICAL HYSTERESIS

I

I

+.9

+3

-+-1- _
....1
I
PRF = 20 kHz,

-O.9V

-O.6V

-O.35V

+O.35V

+O.6V

+O.9V

50"10 Duty Cycle

----l--• Vin IS REFERENCED TO THE MIL (-) INPUT TERMINAL

-.9

-3

MIL

EIA

VOUTI~_~_
_

86

1I1!110liCIi

0.4V

""At COMMIINICA'IONS EIA Mil liNE RECEIVER I'IIR HYSIERE-;IS

8T16
8T16 A,F

TYPICAL APPLICATIONS
HIGH COMMON MODE NOISE IMMUNITY
(MIL + INPUT)

HIGH DIFFERENTIAL NOISE IMMUNITY
(EIA + INPUT)

SINE TO SQUARE WAVE CONVERTER

EIA FAIL-SAFE OPERATION
INPUT OPEN OR
INPUT SHORTEO OR
TRANSMITTER
POWER OFF

"'"

.~
1/2(8T161

SCHMITT TRIGGER

AC COUPLED OPERATIONS
3V-r---\.

~I

OV~

~

-6VU

Il!IIOliC9

87

8T261' 8T28

101 S ATF QUAD BUS I RANSGEIVER
I

8T26A-B,F • BT28-B,F

DESCRIPTION

APPLICATIONS

The 8T26A/28 consists of four pairs of TriState logic elements configured as Quad
Bus Drivers/Receivers along with separate
buffered receiver enable and driver enable
lines. This single IC Quad Transceiver design distinguishes the 8T26A/28 from conventional multi-IC implementations. In addition, the 8T26/28's ultra high speed while
driving heavy bus capacitance (300pF)
makes these devices particularly suitable
for memory systems and bidirectional data
buses.

•
•
•
•
•

PIN CONFIGURATION

Half-duplex data transmission
Memory interface buffers
Data routing in bus oriented systems
High current drivers
MOS/CMOS-to- TTL interface

B,FPACKAGE

Both the Driver and Receiver gates have TriState outputs and low-current PNP inputs.
Tri-State outputs provide the high switching
speeds of totem pole TTL circuits while offering the bus capability of open collector
gates. PNP inputs reduce input loading to
200fJ.A maximum.

LOGIC DIAGRAM
8T26A -INVERTING OUTPUT (TRI-STATE)

8T28 - NON-INVERTING OUTPUT (TRI-STATE)

TEST CONDITIONS

PARAMETER
Propagation Delay tON
tOFF
tON
tOFF
Data Enable to Data Output t PZL
tpLZ
Receiver Enable to Receiver Output t PZL
tpLZ

88

DOUT to ROUT
DOUT to ROUT
D IN to DOUT
DIN to DOUT
High Z to 0
o to High Z
High Z to 0
o to High Z

CL

= 30pF,

CL

= 300pF,

Note 9

CL

= 300pF,

Note 9

CL

= 30pF,

Gi!lDOliCG

Note 9

Note 9

8T26A

8T28

Max

Max

14
14
14
14
25
20
20
15

17
17
17
17
28
23
23
18

UNIT
ns
ns
ns
ns

Til STATE QUAD 8US TRANSCEIVER

8T2611 8T28
BT26A-B,F· BT2B-B,F

BLOCK DIAGRAM
PROPAGATION DELAY (RECEIVE ENABLE TO RECEIVE OUTPUT)
2.GV

Vcc

DE

DOUT ,

RE

DOUT 2

DIN,

DOUT 3

DIN2

DOUT4

DIN3

ROUT'
ROUT 2

DIN4

ROUT3
ROUT4

S.OV

tplz __
2.4k

}

I1

1--- _I1tpzl 1---

~

240

Sk
(PROBEI

INPUT PULSE:
tr = tf = 5ns (10% to 90%)
freq = 5MHz (50% duty cycle)
Amplitude = 2.6V

-=
-=

BIDIRECTIONAL MOS - CMOS TO TTL INTERFACE

C·MOS LOGIC
OR MOS
MICROPROCESSOR

f.4--

TTL BUS IN

~

TTL BUS OUT

BIDIRECTIONAL
MOS BUS

1/4
8T26

I I
CONTROL

TYPICAL APPLICATIONS
BIDIRECTIONAL DATA BUS
,--------.,

r----------,

B~~ o---+--+-~

~--+-f---o BUS
IN

REC o--~-I----k~

-t-

VOL

0.5V
- V OH

''-t-S1 and
S2 closed

""1.5V

WAVEFORM 4

VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES

INPUT1.5V

'PHL~

~5~ -

-

-

3V

~~LH:H

OUT-O~
1.5V
~
OUTP~~PHASE;
~ ~-~

VOL

WAVEFORM 6

WAVEFORM 5

smlOlies

95

n"

81"

H'Gil sp. f n II. X • k' STATr rrEkS
lUSH SPEED HEX 181 STAlE INVERTERS

J

8T 5
19. UI08

8T95-B,F. 8T96-B,F • 8T97-B,F • 8T98-B,F

DESCRIPTION
Each of the Tri-State Bus Interface Elements described herein
has low current PNP inputs and is designed with Schottky TTL
technology for ultra high speed. The devices are used to convert
TTL/DTL or MaS/CMOS to tri-state TTL Bus levels. For
maximum systems flexibility the 8T95 and 8T97 do so without

logic inversion, whereas, the 8T96 and 8T98 provide the logical
complement of the input. The 8T95 and 8T96 feature a common
control line for all six devices, whereas, the 8T97 and 8T98 have
control lines for four devices from one input and two from another
input.

PIN CONFIGURATIONS
B,F PACKAGE
8T96

8T95

015 4

,

IN1
OUT1

3

IN2
OUT2
IN3
OUT3
GNO

15

015 2

14

IN6

13

OUT6

12

IN5

015 4

16

Vee

IN1

15

0152

OUT1

14

INS

IN2

13

OUTS

"

OUT5

IN5

OUT2

6

"

OUT5

.

10

IN4

9

OUT4

IN3
OUT3
GNO

OUT4

8

8T98
8T97

015 4

Vee

IN1

15

0152

OUT1

14

IN6

IN2

13

OUT6

OUT2

12

IN5

IN3

11

OUT5

OUT1

3

13

OUTs

11

OUT5

OUT3
GNO

OUT4

GNO

8

TRUTH TABLES
8T96

8T95

96

DISABLE
DIS1

INPUT
DIS2

INPUT

OUTPUT

DISABLE
DIS1

INPUT
DIS2

INPUT

OUTPUT

0
0
0
1
1

0
0
1
0
1

0
1
x
x
x

0
1
H-z
H-z
H-z

0
0
0
1
1

0
0
1
0
1

0
1
x
x
x

1
0
H-z
H-z
H-z

SmODrilS

8195 RT91S
BT97 BT98

HIGH SPEED HEX Til STATE BIIFFERS
HIGH SPEED HEX TRI STATE INVERTERS

8T95-B,F • 8T96-B,F • 8T97-B,F .8T98-B,F

TRUTH TABLES (Cont'd)
8T97
DISABLE
DIS4

INPUT
DIS2

0
0

x

0
0
1

1

x

8T98

INPUT

OUTPUT

0
1

0
1
H-z*
H-z**

x
x

DISABLE
DIS4

INPUT
DIS2

0
0

x

0
0
1

1

x

INPUT

OUTPUT

0
1

1
0
H-z*
H-z**

x
x

• Output 5-6 only" Output 1-4 only

x = Irrelevant

AC ELECTRICAL CHARACTERISTICS T A = 250 C and VCC = 5.0V
PARAMETER

TEST CONDITIONS

LIMITS
MIN

MAX

TYP

UNITS

95/97 96/98 95/97 96/98 95/97 96/98
Propagation Delays
(All Devices)
Data Inputs
to
Data Outputs
Disable to Outputs
Logic "1" to High Z
Logic "0" to High Z
High Z to Logic "1"
High Z to Logic "0"

ton
toft
tplH
tpOH
tpHI
tpHO

See AC Test Figures

AC TEST CIRCUIT

3

3

9

6

13

10

ns

3

4

7

7

12

11

ns

3
3
8
12

3
5
7
11

5
6
19
14

6
10
15
18

10
12
25
25

10
16
22
24

ns
ns
ns
ns

TRUTH TABLE
2000

............--...-Kl---.-~Sl Q-----AtI\IIr-- 5V
L...-_----J

ALL DIODES lN3064

ton
toft
tOH
t1 H
tHO
tH1

S1

S2

Closed
Closed
Closed
Closed
Closed
Open

Closed
Closed
Closed
Closed
Open
Closed

CL
50pF
50pF
5pF
5pF
50pF
50pF

INPUT CHARACTERISTICS
PA
3V. f
1MHz 'R
tF ~ 10ns (10% to 90%)
CL INCLUDES PROBE AND JIG CAPACITANCE

=

=

=

1~IDlill

97

HEX IBI SI'I Itl ft t I DR
111GB !H'EEH BEl I II 51' It IfIVElii EllS

81 b 8T'"
819. 8ISP

IIlrH SPEEn

8T95-8,F. 8T96-8,F • 8T97-8,F • 8T98-8,F

PROPAGATION DELAYS

1.5V

1.5V

8T95/97

OUTPUT

~
[:"" -~1.5V

1~~~5V----------_-_--_-_-_~

__
D_ISA_B_LE________

DISABLE

juv

OV

OUTPUT

I

tOH~

98

3V

'" 1.5V

\v

-

-

- - - - - - - - - 3V

J.",v=
)I"

DISABLE

LOGIC "3" LEVEL

OV

lOGIC
54/74 SERIES TTL

Data
Book

Page

DEVICE
54/7400
54/7401

5411402
5411403
5411404
5411405
54/7406

5411407
5411408
5411409
54/7410

5411411
5411412
5411413
5411414
5411415
54/7416

5411417
5411420
5411421
54/7422

5411426
5411427
5411428
54/7430

5411432
5411433
54/7437

5411438
5411439
54/7440
54/7442

5411443
5411444
5411445
5411446A
5411447A
5411448
5411450
54/7451

5411452
5411453
54/7454

5411455
5411460
5411461
5411462
5411464
5411465
54/7470

5411471
5411452
5411473
5411474
5411475
54/7476

5411477
5411478
5411480
5411483
5411483A

Ref.

DESCRIPTION
Quad 2-lnput NAND Gate
Quad 2-lnput NAND Gate with o/c
Quad 2-lnput NOR Gate
Quad 2-lnput NAND Gate with o/c
Hex Inverter
Hex Inverter with o/c
Hex Inverter with Buffer/Driver with o/c
Hex Buffer/Driver with o/c
Quad 2-lnput AN 0 Gate
Quad 2-lnput AND Gate with o/c
Triple 3-lnput NAND Gate
Triple 3-lnput NAND Gate
Triple 3-lnput NAND Gate with o/c
Dual NAND Schmitt Trigger
Hex Schmitt Trigger
Triple 3-lnput AND Gate with o/c
Hex Inverter Buffer/Driver with o/c
Hex Buffer/Driver with o/c
Dual 4-lnput NAND Gate
Dual 4-lnput AND Gate
Dual 4-lnput NAND Gate with o/c
Quad 2-lnput NAND Gate with o/c
Triple 3-lnput NOR Gate
Quad 2-lnput NOR Buffer
8-lnput NAN 0 Gate
Quad 2-lnput OR Gate
Quad 2-lnput NOR Buffer
Quad 2-lnput NAND Buffer
Quad 2-lnput NAND Buffer with o/c
Quad 2-lnput NAN 0 Buffer
Dual 4-lnput NAN 0 Buffer
BCD-to-Decimal Decoder
Excess 3-to-Decimal Decoder
Excess 3-Gray-to-Decimal Decoder
BCD-to-Decimal Decoder/Driver with o/c
BCD-to-7 Segment Decoder/Driver
BCD-to-7 Segment Decoder/Driver
BCD-to-7 Segment Decoder/Driver
Expandable Dual 2-Wide 2-lnput AOI
Dual 2-Wide 2-lnput AOI Gate
Expandable 4-Wide 2-2-2-3 Input AND/OR
4-Wide 2-lnput AOI Gate (Expandable)
4-Wide 2-lnput AOI Gate
2-Wide 4-lnput AOI Gate
Dual 4-lnput Expander
Triple 3-lnput Expander
3-2-2-3 Input AND/OR Expander
4-2-3-2 Input AOI Gate
4-2-3-2 Input AOI Gate
J-K Flip-Flop
J-K Master-Slave Flip-Flop with
AND/OR Inputs
J-K Master-Slave Flip-Flop
Dual J-K Master-S!ave Flip-Flop
Dual D-Type Edge-Triggered Flip-Flop
Quad Bistable Latch
Dual J-K Master-Slave Flip-Flop
Quad Bistable Latch
Dual J-K Negative Edge-Triggered Flip-Flop
Gated Full Adder
4-Bit Binary Full Adder
4-Bit Binary Full Adder'

!i!!lDotiC!i

••
••
••
••
•• ••
••
••
••
••
••
••
••
••
••
••
••
••
•• ••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••
••

•• ••
•• ••
••
••
•• •• •• ••

••
••
••
••
••

••
••
••
••
••
••
••
••

••
••
••
••

•• •
•• •
•• •
•
•
•
•• •
•
•
•
•
• • ••••

••
••

••
••
••

••
••

••
••

•• •• ••
••
••
••
•• ••
•• ••
••
••
••

••
••
••
••
••
••
•
••
••
••

••

••
••
••
••
••

59
59
60
60
61
62
62
63
63
64
64
65
65
66
66
67
67
68
68

69
69
70
71
72
73
74
76
77
77
78

79

••
••

••
•• ••
••
••
••
•

53
53
54
55
55
56
56
57
57
58
58

80
81
81
82
82
83
83
84
84
85
86
87
88

90
91
91
92

93
93

99

lOGIC
54/74 SERIES TTL

Data

Book

DEVICE
54/7485
54/7486
54/7490
54/7491
54/7492
54/7493
54/7494
54/7495A
54/7495B
54/7496
54/74100
54/74101
54/74102
54/74103
54/74106
54/74107
54/74108
54/74109
54/74112
54/74113
54/74114
54/74116
54/74121
54/74122
54/74123
54/74123A
54/74125
54/74126
54/74128
54/74132
54/74133
54/74134
54/74135
54/74136
54/74138
54/74139
54/74140
54/74145
54/74147
54/74148
54/74150
54/74151
54/74152
54/74153
54/74154
54/74155
54/74156
54/74157
54/74158
54/74160
54/74161
54/74162
54/74163
54/74164
54/74165
54/74166
54/74170
54/74172
54/74173
54/74174

100

Page

DESCRIPTION
4-Bit Magnitude Comparator
Quad 2-lnput Exclusive-OR Gate
Decade Counter
8-Bit Shift Register
Divide-By-Twelve Counter
4-Bit Binary Counter
4-Bit Shift Register (PI SO)
4-Bit Left-Right Shift Register
4-Bit Left-Right Shift Register
5-Bit Shift Register
4-Bit Bistable Latch (Dual)
J-K Negative Edge-Triggered Flip-Flop
J-K Negative Edge-Triggered Flip-Flop
Dual J-K Negative Edge-Triggered Flip-Flop
Dual J-K Negative Edge-Triggered Flip-Flop
Dual J-K Master-Slave Flip-Flop
Dual J-K Negative Edge-Triggered Flip-Flop
Dual J-K Positive Edge-Triggered Flip-Flop
Dual J-K Negative Edge-Triggered Flip-Flop
Dual J-K Negative Edge-Triggered Flip-Flop
Dual J-K Negative Edge-Triggered Flip-Flop
Dual 4-Bit Latch with Clear
Monostable Multivibrator
Retriggerable Monostable Multivibrator
Retriggerable Monostable Multivibrator
Retriggerable Monostable Multivibrator
Quad Bus Buffer Gate
w/Tri-State Outputs
Quad Bus Buffer Gate
w/Tri-State OutPUtS
Quad ~-Input NOR Buffer
Quad Schmitt Trigger
13-lnput NAND Gate
12-lnput NAND Gate w/Tri-State Outputs
Quad Exclusive-OR/NOR Gate
Quad Exclusive-OR with o/c
3-to-8 Line Decoder/Demux
Dual 2-to-4 Line Decoder/Demux
Dual 14-lnput NAND Line Driver
BCD-to-Decimal Decoder/Drive with o/c
10-Line to 4-Line Priority Encoder
8-Line to 3-Line Priority Encoder
16-Line to 1-Line Mux
8-Line to 1-Line M ux
8-Line to 1-Line Data Selector/Mux
Dual 4-Line to 1-Line Mux
4-Line to 16-Line Decoder/Demux
Dual 2-Line to 4-Line Decoder/Demux
2-Line to 4-Line Decoder/Demux
Quad 2-lnput Data Selector (Non-Inv.)
Quad 2-lnput Data Selector (Inv.)
Synchronous 4-Bit Decoder Counter
Synchronous 4-Bit Binary Counter
Synchronous 4-Bit Decade Counter
Synchronous 4-Bit Binary Counter
8-Bit Parallel-Out Serial Shift Register
Parallel-Load 8-Bit Shift Register
8-Bit Shift Register
4 X 4 Register File
16-Bit Multiple Port Register File
Quad D-Type Flip-Flop (Tri-State) (8T10)
Hex D-Type Flip-Flop with Clear

S!!IDOliCS

Ref.

••
••
•• ••
••
••
••
••
••
••

•• ••
•• •• • •
••
••
••
•
••

••
••
••
••
••
••
••
••
•• •• • •
•• ••
•• ••
••
••
•
••
••
••
••
••
••
••
•.. •
••
••
• • •• ••
••
••
••
••
••
.,
••
•
•
••
••
•• ••
•
•
•
•
•• ••
•• •
•
•
•
••
•
•
••
••
•
••
•
•
•
•
••
•
JUNE
••
•• •
It

•

tt

•

.

95
98
100
102
102
104
105
N/A
106
108
110
111
112
114
115
116
117
118
119
121
122
123
124
128
129
129
130
131
131
132
132
133
133
134
134
135
N/A
136
137
138
140
142
143
145
146
147
148
149
150
151
153
156
160
162
164
167
169
172
N/A
174

lOGIC
54/74 SERIES TTL

Data

Book

DEVICE

Page

DESCRIPTION

Ref.

54174174
54/74175
54174176
54174177
54174178
54174179
54174180
54/74181
54174182
54174190
54/74191
54174192
54174193

Hex D-Type Flip-Flop with Clear
Quad D-Type Edge-Triggered Flip-Flop
Presettable Decade Counter/Latch (8280)
Presettable Binary Counter/Latch (8281)
4-Bit Parallel Access Shift Register (8270)
4-Bit Parallel Shift Register (8271)
8-Bit Odd/Even Parity Checker
4-Bit Arithmetic Logic Unit
Look-Ahead Carry Generator
Synchronous Up/Down BCD Counter
Synchronous Up/Down Binary Counter
Synchronous Decade Up/Down Counter
Synchronous 4-Bit Binary
Up/Down Counter
54174194 4-Bit Bidirectional Universal Shift Reg
54/74195 4-Bit Parallel-Access Shift Register
54174196 Presettable Decade Counter/Latch (8290)
54174197 Presettable Binary Counter/Latch (8291)
54174198 8-Bit Shift Register
54174199 8-Bit Shift Register
54174221
Dual Monostable Multivibrator
54174251
Data Selector/Mux with Tri-State Outputs
54174253 Dual 4-Line to 1-Line Data Selector/Mux
54174257 Quad 2-Line to 1-Line Data Selector/Mux
54174258 Quad 2-Line to 1-Line Data Selector/Mux
54174260 Dual 5-lnput NOR Gate
54174261
2's Complement Multiplier
54174266 Quad Exclusive-NOR Gate
5417 4279 Quad S-R Latch
54174280 9-Bit Odd/Even Parity Generator/Checker
54174283 4-Bit Adder
5A17 4290 Decade Counter
54174293 4-Bit Binary Counter
54174295A 4-Bit Right-Shift Left-Shift Register
54174298 Quad 2-lnput Mux with Storage
54174375 Quad Latch
5417 4386 Exclusive-OR Gate
54174670 4 X 4 Register File (Tri-State)

S!!IDotiCS

•
•

•••
•••

DEV
DEV
•
•
•
•
•
•
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••
••
•
•
••
••
••

•

•

••
•
•
•

••
••

•
•
•

• •
.DEV .DEV
•••
DEV
DEV
DEV
DEV

• •
•••
•• ••
•••
•• ••
•• ••
• •
• •
••

••

•
•
•
•
•
•
•
•

•
•

•

174
175
176
176
177
177
178
178
183
184
187
190
192
195
197
200
201
203
206
210
212
214
215
216
217
218
220
221
221
222
223
225
227
228
N/A
230
230

101

lOGIC
8200 SERIES TTL/MSI
STANDARD
8200
DEVICE
8200
8201
8202
8203

0""'1"\
o,-'v
8231
8232
8233
8234
8235
8241
8242
8243
8250
8251
8252
8260
8261
8262
8263
8264
8266
8267
8268
8269
8270
8271
8273
8274
8275
8276
8277
8280
8281
8282
8283
8284
8285
8288
8290
8291
8292
8293

102

DESCRIPTION
Dual 5-Bit Buffer Register
Dual 5-Bit Buffer Register
with D Inputs
10-Bit Buffer Register
10-Bit Buffer Register
with D Inputs
8-lnput Digital Multiplexer
8-lnput Digital Multiplexer
8-lnput Digital Multiplexer
2-lnput 4-Bit Digital Multiplexer
2-lnput 4-Bit Digital Multiplexer
2-lnput 4-Bit Digital Multiplexer
Quad Exclusive-OR Gate
Quad Exclusive-NOR Gate
8-Bit Position Scaler
Binary-to-Octal Decoder
BCD-to-Decimal Decoder
BCD-to-Decimal Decoder
Arithmetic Logic Unit
Fast Carry Extender
9-Bit Parity Generator
and Checker
3-lnput 4-Bit Digital Multiplexer
3-lnput 4-Bit Digital Multiplexer
2-lnput 4-Bit Digital Multiplexer
2-lnput 4-Bit Digital Multiplexer
Gated Full Adder
4-Bit Comparator
4-Bit Shift Register
4-Bit Shift Register
10-Bit Serial-In, Parallel-Out
Shift Register
10-Bit Parallel-In, Serial-Out
Shift Register
Quad Bistable Latch
8-Bit Serial Shift Register
Dual 8-Bit Shift Register
Presettable Decade Counter
Presettable Binary Counter
BCD Arithmetic Unit
BCD Adder
Binary Up/Down Counter
Decade Up/Down Counter
Divide-by-Twelve Counter
Presettable High Speed
Decade Counter
Presettable High Speed
Binary Counter
Presettable Low Power
Decade Counter
Presettable Low Power
Binary Counter

Commercial

Military

•
••

•
•
•

SCHOTTKY
82S
Commercial

255
255
255

•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•
•
•
••
•
•
•
•
•
•
•
•

•
•

!ii!lDotiC!i

•

•
•
•
•

•
•
•
•
•
•
••
•
•
•

•
•
•
•
•
•
•

Military

Data
Book
Page
Ref.

•
•
•
•

•

255
257
259
259
262
262
262
264
264
267
271
271
271
275
278
280
282
282
285
285
288
291
292
292
297

•
•
•
•

299
301
302
304
306
306
310
314
318
318
321
323
323
328
328

LOGIC FUNCTION SELECTOR GUIDES
Use these charts to quickly identify the most suitable
devices to meet your system needs. The following
charts group together similar function circuits in Signetics TTL families.
ARITHMETIC UNITS/MICROPROCESSOR CPUs
!::::

::::l
t..:I

a::

en

t3

l-

e

::::l

en

l-

ai
Ll-

e

a::

LoU
CD

FUNCTION

:E
::::l
z:

DEVICE

<:

c...
~

l-

LoU

II-

::::l

c...

l-

c...

::
<:

::..::

z:

::::l

:E

I-

....J

c...
:E
e

e
:E
::::l
en

X
X

X
X
X
X
X

X
X
X
X
X

X
X
X

X

X

X

X

X

LoU

LoU

t..:I

::::l

::::l

e
>a::
a::
<:

t..:I

e
e

....J

~

>a::

>a::

t..:I

t..:I

a::
<:

a::
<:

ALU (BINARY)
8260
74181
74S181
74LS181
ALU (BCD)

GATED FULL
ADDER
(BINARY)

GATED FULL
ADDER (BCD)
LOOK-AHEAD
CARRY

2's COMPLEMENT
MULTIPLIER

4
4
4
,4

82S82

4

8268
7480
7483
74S83
74S283

2
2
4
4
4

82S83

4

8261 (Extender)
74182
74S182

4
4
4

74LS261

2x4

smAoties

103

DATA SELECTOR/MULTIPLEXER
I-::=l

e...

I-::=l
0
t.::I

CI:)

I-::=l

e...

I-::=l
0
L.L

0

a::
u.I
co

FUNCTION

SINGLE 8-INPUT
MUL TIPLEXER

SINGLE 16-INPUT
MULTIPLEXER
DUAL4-INPUT
MUL TlPLEXER

QUAD 2-INPUT
MUL TIPLEXER

QUAD3-INPUT
MUL TIPLEXER

104

DEVICE

~
::=l

z:

I-::=l

z:
i=

a::
u.I

:>
~

Z

0

z:

82301 82S30
8231/82S31
8232/82S32
74151
74LS151
74S151
74152
74LS251
74S251
9312

2
2
2
2
2
2
1
2
2
2

74150

1

74153
74LS153
74S153
74LS253
74S253
9309

2
2
2
2
2
2

X
X
X
X
X

8233/82S33
8234/82S34
8235
82661 82S66
8267/82S67
74157/74S157
74158/74S158
74S257
74S258
74298
(w I storage)

4
4
4
4
4
4
4
4
4
4

X

8263
8264

4
4

I-::=l

u.J

I-::=l
0

I-::=l

e...

I-::=l
0
t.::I

z:
i=
a::
u.J

:>
~

:>

z:

a::

Z

0
I-t...:I

0

z:

........

u.I

t.::I

z:
i=
a::
u.I

:>
~

I-t...:I

....J

0

u.I

:::.:::

t...:I
0

....J

t...:I

0
0
~

c

....J

0

:::z:::

X
X
X
X
X
X

u.J
....J
....J

0
t...:I

z:
u.I

e...

0

CI:)

0

e...

a::

e...

I-::=l
0
t.::I

z:
i=

I-::=l

a::

I-I-::=l

e...

I-::=l
0
u.J

I--

cz::
I-CJ?

ii:

I--

I-::=l

e...

I-::=l
0
0

a::

cz::
0
z:
cz::

I--

CI:)

0
t...:I

§:

=.

u.J

I--

I--

Qj

§

z:

0

Q

~
0
u.I

0
0
t...:I

z:
u.I

:i:
~

:::z:::
~

e...

co
0
a::

I--

I-::=l

I-::=l

I-::=l
0

I-::=l
0

e...

e...

I-::=l

~

X
X
X
X

X
X
X
X
X
X

X
X

X
X
X
X

X
X
X

X

X
X
X

X

X

X
X
X
X
X

X
X

X
X
X

X
X

X

X
X

X
X
X

j

X

X
X

X
X
X
X
X
X

Si!lDotiCS

X

X
X

X
X

e...

I-::=l
0
0
u.I

:::z:::

a::

u.J

I-0

u.I

:::z:::

t...:I
I--

t...:I
I--

....J

....J

cz::

cz::

t:
~

u.I

z:
u.I

e...

0

u.J

~

u.J
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e...

~
0
t...:I

cz::
I-cz::
c

X
X
X

X
X

X

X
X

X

I-::=l
0

e...

I--

z:

X
X
X

X
X
X

X
X
X

u.I

CI:)

u.I
....J
u.I

X

X
X
X

cz::
z:

I-::=l

X

X

co

I-t...:I

X
X
X

X
X
X
X
X
X

u.I

z:

:::J

X
X
X
X
X
X
X
X
X
X

X
X

u.J
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u.J

CI:)

e...

I-::=l
0

CI:)

I-::=l

u.J
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u.J
CI:)

X

X
X

X
X
X
X
X

X
X
X

X

X
X

COUNTERS
§:

I--

I--

I--

- e

en

en

en

en

c::

c::

:::l
0

en

:::l
0

:::l
0

:::l
0

0

z:

0

0

0

u
z:
>en
<

u
z:
>en
<

u
z:
>en
<

UoI

en

en

c::

Cl:I

I--

UoI

UoI

<

c::

I--

en
L.L.

0

c::
UoI
CD

::!E

FUNCTION
RIPPLE BINARY
COUNTER

RIPPLE DECADE
COUNTER

RIPPLE DIVIDE
BY 12 COUNTER

:::l

UoI

c::

I--

I--

:::l
0
U

UoI

z:

:::l
0

u

0..
:::l

z:

z:

3:

C

z:

:::l
0

u
z:

3:
0
0

........

0..
:::l

UoI

c::

0..

en

z:

c::
::z::

u
z:
>en
<

DEVICE

z:

8281/74197
8291
82S91
8293
7493
74LS93
74LS197

4
4
4
4
4
4
4

X
X
X
X
X
X
X

X
X
X
X

8280174176
8290
82S90
8292
7490
74LS90
74LS196
74S196

4
4
4
4
4
4
4
4

X
X
X
X
X
X
X
X

X
X
X
X

8288
7492
74LS92

4
4
4

X
X
X

X

SYNCHRONOUS
BINARY COUNTER 8284
74161
74LS161
74163
74LS163
74191
74LS191
74193
74LS193

4
4
4
4
4
4
4
4
4

SYNCHRONOUS
DECADE COUNTER 8285
74160
74LS160
74162
74LS162
74190
74LS190
74192
74LS192

4
4
4
4
4
4
4
4
4

C

UoI
UoI

0..

:::l
0

0

c::
::z::

u
z:
>en

X
X
X
X

X

X

X
X
X
X

z:

c::
::z::

UoI

c::

en

z:

c::
::z::

UoI
UoI

c::

en

z:

c::
::z::

X
X
X
X

UoI

c::

en

:::l
0

z:

0

c::
::z::

u
z:
>en

Cl:I

z:

a:
UoI

3:

u

0
0

........

a:
I--

0..
:::l

UoI

::..:::

...J

U
0

...J

u

UoI

Cl:I

z:

en

c::

I--

z:

3:

0..
:::l

........

0

z:

0
0

Cl:I
Cl:I

...J

0

U

I--

<
c::
<
0..
UoI

en

0
U

UoI

UoI

...J

I--

CD

<
z:

I--

UoI

~

:::l
0

I--

z:

>c::

>c::

u

<
u

<
u

:::l
0

c::

c::

:::l
0

3:
0

c::
c::

0
CD

0
0

::!E
c
UoI

I-:::l
0..

I--

CLOCK
FREQUENCY

UoI

(MHz)

:::l
0
0

0
0

0
0
U

UoI

c

u
z:

UoI

j

I
j

X
X

1
1

I
I
I

I
I

X

X
X

Gi!lDOliCG

1
1
1
1
1
1
1

I

X
X
X
X
X
X
X
X
X

X

X
X

1
1
1
1
1
1

X

X
X

X
X
X
X

X

1

X
X

32

20
40 60
85 100
5
10
30
30
85 100

j

X
X

20 25
40 60
85 100
5 10
10 18

I
I

I
I

X

Typ Max

15

j

X
X

Min

I

I
I

X
X
X
X
X
X

en

z:
0
u
z:

::..:::
...J

I

X
X
X

X
X

c::

I--

UoI

X
X

X

0

I--

X
X
X

X

X
X
X
X

en

X
X
X
X
X
X
X
X

X
X

X
X
X
X

UoI

UoI

I--

X
X
X
X
X
X
X

X

X
X
X
X

UoI

...J

in

e

I--

X
X
X
X

X
X
X
X

X

X
X

X
X
X
X
X
X
X
X

25
25
25
25
20

25
20

25 32
25
20

X
X
X
X
X
X
X
X

25

20 30

X

X
X
X
X

20
10
16

30
25

X
X
X
X

25
25
20
20 25
25
25

105

DECODERS/DEMUL TIPLEXERS
ell
I--

ell
I-~

<'

.§..

<'
.§..

~

:z

Ci)

I-~

e..

I--

FUNCTION
BCD TO 7-SEGMENT
DECODER/DRIVER

BINARY TO OCTAL
DECODER/
DEMULTIPLEXER

8T04
8T05
8T06
7446
7447
7448

e

L.U

t.:I

a::
~
e

ell
I--

I--

I--

e
a::
e

c:c

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e

:;:..
I-~

e..

I--

~

~

e

I--

%:

e..

~

e

e..

c.::J

c.::J

;:

40

~

I-t.:I

L.U
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e

t.:I

:z
L.U
e..
e

ell
I--

~

e..

I-~

e
e
a::
c:c
e
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c:c

I-ell

ell
I--

~

e..

I--

~

e

;:

~

e..

cc

~

c:c
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e

.........

:::::;
c:c

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e

:;:..
~

L.U

I--

i=
t.:I
c:c

;:

:;:..

L.U
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iii

~

L.U
L.U

cc
e
a::

I-ell
I-~

e..

~

e..

I--

~

e
a::
L.U

I-I--

iE
L.U
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L.U
e..
e

e..

I--

~

e..

I--

~

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I-~

e..

I-~

e
e

L.U

I--

e
e..

~

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e..
a::
e

a::

I-ell

:;:..
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Ci)

L.U

L.U

a::

X

40
20
20

30
15

X
X
X
X

6.4
X

X

74LS139 (Dual)
74S139 (Dual)
74155 (Dual)
74156 (Dual)

X
X
X

X
X
X
X

X
X
X
X

74LS138
74S138

X
X

X
X

X
X

4-LlNE TO
16-LlNE
DECODER/
DEMULTIPLEXER

74154

X

X

X

EXCESS 3-TODECIMAL
DECODER

7443

X

X

X

EXCESS 3-GRA YTO DECIMAL
DECODER

7444

X

X

X

3-LlNE TO
8-LlNE DECODER/
DEMULTIPLEXER

~

ell
I--

X
2.3

8250/82S50

2-LlNE TO
4-LlNE DECODER/
DEMULTIPLEXER

106

DEVICE

~

ell

L.U

ell
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X

SmDOliCS

X

X

e

~

~
c.::J

I--

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c:c
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~

cc

L.U
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e..
e..

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X
X
X
X
X
X

L.U
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L.U

e
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L.U
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c.::J

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I-ell
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c:c
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e..
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cc

c:c
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X
X
X
X
X
X

X
X
X
X
X
X

e
e
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c:c
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e
:E
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e

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X
X
X
X

X
X

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NUMBER OF BITS

c.o 0::> c.o

NUMBER OF BITS

x

ENCODED OUTPUT

xxx

EVEN PARITY OUTPUT

xxx

CASCADING INPUT

xxx

ODD PARITY OUTPUT

xx

A < B INPUT

xx

A = B INPUT

xx

A> B INPUT

c..n.:::...:::.. .:::..

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f.i

1':1

III

x

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n
m

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ww

NUMBER OF OUTPUTS

.:::.. .:::..

NON-INVERTING OUTPUTS
xx

xx

INVERTING OUTPUTS

x

x

TRI-STATE OUTPUTS

OUTPUT INHIBIT

x

ODD/EVEN SElECT

x

STANDARD OUTPUTS
OPEN COLLECTOR OUTPUTS

ODD/EVEN OUTPUT
-

'--

xxx

A> B OUTPUT

xx

xxx

A =B OUTPUT

xx

INPUT ENABLE

xxx

A < B OUTPUT

xx

OUTPUT ENABLE

x

OUTPUT ENABLE

x

INHIBIT OUTPUT (0)
-

x

GROUP SHECT OUTPUT

OUTPUT INHIBIT (0)
x

OUTPUT INHIBIT (1)

--

x

x

OUTPUT INHIBIT (Hi-Z)
OPEN EMITTER OUTPUT

-"

o......

C

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III

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FLIP-FLOPS
u::;
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D-TVPE
FLIP-FLOP

SINGLE J-K
FLIP-FLOP

DUAL J-K
FLIP-FLOP

108

:>

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c:::I

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~
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I
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X
X
X

X
X
X

I

X
X
X
X
X
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DEVICE

!:

7474 (Dual)
74LS74 (Dual)
74S74 (Dual)
74174 (Hex)
74LS174 (Hex)
74S174 (Hex)
74175 (Quad)
74LS175 (Quad)
74S175 (Quad)

X
X
X

X
X
X

X
X
X
X
X
X
X
X
X

7470
74H71
7472
74H72
74H101
74H102

X
X
X
X
X
X

X
X
X
X
X
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7473
74H73
74LS73
7476
74H76
74LS76
74LS78
74H103
74H106
74107
74LS107
74H108
74109 (J/K)
74LS109 (J/K)
74LS112
74S112
74LS113
745113
74LS114
74S114

X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
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X
X
X
X
X
X
X
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FREQUENCY
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25
25
30
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25
33
70
35
40
110

30
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40
110

X
X
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15
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15
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35
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20
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X
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20
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40
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15
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40
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45
50
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45
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33

30
80

45
125

80
30
80

125
45
125

X
X
X
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25

30
30

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X
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74172
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4x4
8x2

X
X

X
X

X
X

X
X

8x2

X

X

X

X

4
4
4
4
4
5
4
4
4
4
8
8
4

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X
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X
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X
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X
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1
1
1
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1

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L.LJ

CLOCK
FREQUENCY

L.LJ
L.LJ

Min

(MHz)
Typ Max

REGISTER FILE

GENERAL
PURPOSE
SHIFT
REGISTERS

SERIAL-IN/
SERIAL-OUT
SHIFT
REGISTERS

15
20
20

1

8270174178
82S70174S178
8271174179
82S71 /74S 179
7495
7496
74194
74S194
74195
74S195
74198
74199
9300

PARALLEL-IN/
PARALLEL-OUT 8200 (Dual)
8201 (Dual)
REGISTERS
8202
8203
PARALLEL-IN/
SERIAL-OUT
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REGISTERS

10

5
5
10
10

8274
7494 .
74165
74166
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10
4
8
8

8276
8277 /9328 (Dual)
7491

8
8
8

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74164
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X
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X
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X
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X
X
X
X
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X
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X
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40
15
40
25
10
25
70
30

36
105
39

25
25
30

35
35
38

15
15
15
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35
35
35
35

25
10
20
25

30

15
15
10

20
20
18

25

36

60
22
60
36

70

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X
X

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109

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7475
74100 (Dual)
74116 (Dual)

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74279

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BCD-TO-DECIMAL
DECODER/DRIVER

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INTRODUCTION
Recent trends in system design are focusing
on significantly lower costs and greater
reliability while simultaneously maintaining
or improving system performance. Consequently, second generation as well as new
system designs demand alternatives to conventional logic realizations which substantially reduce the system manufacturing
costs. Signetics' System Logic Family provides this alternative by employing state-ofthe-art technology to produce Large-ScaleIntegrated, system oriented building
blocks. By replacing a relatively large number of conventional logic circuits with a few
System Logic components, system costs
are reduced in proportion to system printed
circuit board area, total number of circuits
and power requirements. Moreover, system
reliability is increased in direct proportion
to the decrease in the number of integrated
circuits within the system.

SYSTEM LOGIC FAMILY
Signetics' System Logic offers the designer
a dual technology logic family to achieve
cost objectives. First, where speed is a primary objective, low power Schottky TTL
technology is employed to yield devices
which feature high speed, low power, and
medium density. Therefore, significant reduction in the number of high speed logic
components is possible without any sacrifice in performance. The distinct advantages of low power Schottky TTL give it one
of the best technologies for high performance LSI design. The particular features
of LS are:
•
•
•
•
•

•
•

Comparable propagation delay to standard
TTL7-10ns/gate average
Low power dissipation-2mW per gate typical
at 50% duty cycle
Low speed power product-19pj typical
45MHz typical maximum J-K flip-flop clock
frequency
High fan-outcapability-22 unit load-LS input
current requirement is % that of standard TTL
(0.36mA/input). Outputs are capable of sinking
8mA.
High logic density-70 gates/mm 2 of silicon
Higher system reliability due to reduced power
density.

Secondly, while lower power Schottky offers increased density at high speeds, substantial component reduction is achieved
with devices employing Integrated Injection
Logic (l2L). The very high density and low
power of 12L makes it extremely attractive
for use in realizing relatively large system
building blocks. System level functions may
each be accomplished at 10MHz speeds by
a single 12L integrated circuit. 12L features
are:
•
•
•
•

Speed-comparable to T2L (10-20ns propagation delay)
Power-1-2 orders lower than any technology
power down mode
Density-40% smaller than PMOScomparable to NMOS
Interface-capability of mixing T2L, ECL circuits on the same chip.

The System Logic series of products are
specially designed to aid system logic designers in the design of high performance,
cost effective systems with a minimal number of parts. This is achieved through a line
of standard products which are designed
with the following objectives:
•

Large Scale Building Blocks-devices are partitioned by function with high-level complexity
and sophistication. These one chip building
blocks are equivalent to 400 to 1500 elementary
logic gates.
• Highest Performance Possible-devices in
each category are optimized in performance
according to their requirements. Devices requiring highest speed are designed using low
power Schottky TTL and devices requiring
medium speed are designed using 12L to minimize device power dissipation and maximize
logic density.
• Off-the-shelf items-system logic devices are
designed to allow general purpose usage. Devices in this series can be used as stand-alone
items to enhance performance on a certain
system design or to utilize several components
within the family to design a minimal cost
system with minimum number of components,
such as in microprocessor based systems.

SIGNETICS CAPABILITIES
Signetics is a leader in the development of
bipolar LSI logic circuits using both LS and
12L technologies. Our capabilities are demonstrated by an 8-bit fixed Instruction Microprocessor that Signetics is presently
manufacturing with low power Schottky
technology.
This circuit, the 8X300 Interpreter, contains
the equivalent of 700 logic gates on a
250X250 mil chip. This capability is being
used to develop the System Logic Family
and _produce the substantial cost reduction
offered by LSI without paying a penalty in
performance.

level of producing such LSI circuits is extremely high. In addition to its own development activities, Signetics has access to N.V.
Philips' vast development resources for
continued development and enhancement
of its present capabilities. This massive
investment will result in continued improvement in speed/power performance of 12L
products.
Table 1 shows expected trends in 12L speed/power curves during the next five years.
Clearly 12L will playa major role in the
innovation of faster and possibly more complex System Logic functions in the support
of a continued exploitation of LSI circuitry
in systems design.

ADVANTAGES
The advantages of using LSI in system
design are manyfold. First, note that the
cost of an LSI chip is no more than the sum
cost of the circuits it replaces, consequently
there is a direct saving in manufacturing
costs as a result of a net reduction in the
number of parts. Moreover an LSI system
offers economic advantages over an SSI or
MSI approach besides lowering direct manufacturing costs. Some important considerations are:
•

•

•

•

Signetics is a forerunner in 12L technology.
Signetics has been researching 12L as a
standard product technology for over three
years. Presently, Signetics possesses one of
the fastest 12L processes in the industry.
Recognizing the vast potential of 12L technology, Signetics is heavily committed to
develop this high-speed line of LSI products
using this technology. Signetics' 12L process is basically the same process as its low
power Schottky process that utilizes a thin
expitaxial layer for speed improvement.
Since this process is a highly reliable standard process in Signetics, the confidence

Power supply costs are reduced because logic
cells internal to the device require less drive
capability and consequently consume less
power.
Field repair costs are reduced because reliability is higher with an LSI implementation. This
higher reliability is achieved because IC failure
rates are largely proportional to number of
devices rather than device complexity.
Another factor to be considered is that the
development cost of printed circuit boards will
decrease because of smaller number of ICs and
that to some extent, this reduction offsets the
cost of layout on the LSI devices.
Applications requiring medium speed performance are often forced to use lower density,
high speed semiconductor devices due to lack
of availability of medium speed LSI devices. 12L
has changed this picture significantly. With the
capability of controlling the amount of device
injection curre~t into an LSI circuit, the device
can be controlled to operate at the desired
speed and power for that particular application;
thus, power consumption is minimized.

USING STANDARD LS PROCESS
Average Propagation Delay
Density (Dual Layer Metal)

Chip Complexity
Speed-Power

Table 1

Si!lDOliCS

10-20ns at 200tlA/Gate Injection Cu rrent
320 gates/mm 2
Shift Register etc.
-150 gates/mm 2
Random Logic
-1.5 mil2
Single Inverter
2000 gates at maximum speed (Random Logic)
4000 gates at maximum speed (Regular Arrays)
3pj @ maximum speed
0.35pj @ < 1MHz
SIGNETICS 12L CAPABILITY

111

•
•
•

SYSTEM LOGIC PRODUCT
FAMILY
Signetics' System logic series of products
can be categorized into five major groups
according to their function. Grouping is as
follows:
• Communications
• Memory

Microprocessors
Peripheral I/O
Miscellaneous

Circuits within each group are interrelated
in function, thus insuring compatibility both
in electrical characteristics and in technology.
Figure 1 illustrates the type of products in

the System logic series. Products with part
numbers assigned are either released or
under development. Devices with no part
numbers assigned are on the product plan.
New products will be added to the family
tree at regular intervals. A brief description
of the System logic devices is given in the
pages that follow.

SYSTEM LOGIC PRODUCT STATUS
New Products
IN PRODUCTION
8X01-Cyclic Redundancy Check
Generator/Checker
-150 Gates at 10MHz (Typical)
-1 2 l Technology

PLANNED
8X05-Direct Memory Access Control Unit
-1200 Gates at 10MHz
-1 2 l Technology
8X06-64X8 FIFO
-3000 Gates at 10MHz
-1 2 l Technology

8X02-Control Store Sequencer
-300 Gates
-lS Technology

8X07-64X9 FIFO
-3000 Gates at 10MHz
-1 2 l Technology

8X08-Frequency Synthesizer

8X

-16X8 LIFO
-600 Fates at 10MHz
-1 2 l Technology

8X

-Multiplier
-1 2 l Technology

8X

-Dual Port Register File
-lS Technology

8X

-Pipe Lined I/O Port
-LS Technology

8X

-Peripheral Interface Unit
-1 2 l Technology

SIGNETICS SYSTEM LOGIC FAMILY

SYSTEM LOGIC FAMILY

MISCELLANEOUS

FREQUENCY
SYNTHESIZER
8X08

PERIPHERAL/I/O

(8X05)
DMACONTROL

MULTIPLIER

8X300 8·BIT
!,CONTROLLER

8X06/8X07
64X8/64X9 FIFO

3001
MICROPROGRAM CONTROL UNIT
3002
2·BIT CENTRAL PROC. ELEMENT

MULTI·PORT
MEMORY CONTROL

8X02 (CONTROL
STORE SEQUENCER)

MULTI-INPUT
PIPELINED I/O PORT

DUAL PORT
REGISTER FILE

PERIPHERAL
INTERFACE UNIT

Figure 1

112

MEMORY

I'PROCESSOR/SUPPORT

S(gOOliCS

COMMUNICATIONS

8X01
CRC

8X01-A,F

OBJECTIVE SPECIFICATION

DESCRIPTION

FEATURES

The CRC Generator/Checker circuit is used
to provide an error detection capability for
serial digital data handling system. The serial data stream is divided by a selected
polynomial and the division remainder is
transmitted at the end of the data stream,
as a Cyclic Redundancy check character
(CRCC). When the data is received, the
same calculation is performed. If the received message is error-free, the calculated
remainder should satiSfy a predetermined
pattern. In most cases, the remainder is
zero except in the case where Synchronous
Data Link Control type protocols are used
whereby the correct remainder is checked
for 1111000010111000 (xO - x 15).

•
•
•
•
•
•
•
•
•

PIN CONFIGURATION

12L technology
TTL inputs/outputs
10MHz (max) data rate
Total power dissipation = 175mw (max)
Vcc = 5.0V
VJJ = 1.0V
Separate preset and reset controls
SOLC specified pattern match
Automatic right justification

A,F PACKAGE

ep

Vee
ER

so

a

MR

D

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TYPICAL APPLICATIONS
• Floppy and other disc systems
• Digital cassette and cartridge systems
• Data communication systems

GND

8 polynomials are provided and can be selected via a 3-bit control bus. Popular
polynomials such as CRC-16 and CCITT are
implemented. Polynomials can be programmed to start with either all zeros or all
ones.
Automatic right justification for polynomials
of degree less than 16 is provided.

RECOMMENDED OPERATING CONDITIONS
LIMITS
PARAMETER
VCC
IJJ

Supply voltage
Supply current

MIN

TVP

MAX

UNIT

4.75
40

5.0

5.25
100

V
mA

FUNCTIONAL DESCRIPTION
The CRC Generator/Checker circuit provides a means of detecting errors in a serial
data communications environment. A binary message can be interpreted as a binary polynomial H(x). This polynomial can
be divided by a generator polynomial P(x)
such that H(x) = P(x) Q(x) + R(x) whereby
Q(x) is the quotient and P(x) is the remainder. During transmission, the remainder is
appended to the end of the message as
check bits. For a given message, a unique
remainder is generated. Hardware implementation of division is simply a feedback
shift register with Exclusive-OR gating.
Subtraction and addition in modulo 2 is
implemented by the Exclusive-OR function. The number of shift register stages is
equal to the degree of the divisor polynomial.
Table 1 shows the polynomials implemented in the CRC circuit. Each polynomial can
be selected via the 3-bit polynomial control
inputs So, S1 and S2. To generate the
check bits, the data stream is entered via
the Data (D) input, using the high to low
transition of the Clock (CP) input. This data
is gated with the most significant output
(Q) of the register, and controls the exclusive OR gates. The Check Word Enable
(CWE) must be held high while the data is
being entered. After the last data bit is
entered, the CWE is brought low and the
check bits are shifted out of the register
and appended to the data bits using external gating.

To check an incoming message for errors,
both the data and check bits are entered
through the D input with the CWE input
held high. The 8X01 is not in the data path,
but only monitors the message. The Error
output becomes valid after the last check
bit has been entered into the 8X01 by a high
to low transition of CP. If no detectable
errors have occurred during the data transmission, the resultant internal register bits
are all low and the Error output (ER) is low.
If a detectable error has occurred, ER is
high. ER remains valid until the next high to
low transition of CP or until the device has
been preset or reset. PME must be high if
ER output is used to reflect all zero result.
For data communications using the Synchronous Data Link Control protocol
(SDLC), the 8X01 is first preset to all ones
before any accumulation is done. This
applies to both transmitter and receiver.
A special pattern of 1111000010111000 (x O
- X 15 ) is used in place of all zeros during
receiving for valid message check. PME is
incorporated to select this option. If PME is
low during the last bit time of the message,
ER output is low if result matches this
special pattern. When ER is high, error has
occurred.

case of the 12 or 8-bit check polynomials
only the most significant 12 or 8 register
bits are set and the remaining bits are
cleared.

PIN DESIGNATIONS
PIN NO.

FUNCTION

SO, S1, S2

Polynominal Select inputs

0

Data input

CP

Clock (operates on high to
low transition) input

CWE

Check Word Enable

P

Preset (active low) input

MR

Master Reset
(active high) input

Q

Data output

ER

Error (active high) output

PME

Pattern match enable
(active low)

A high level on the Master Reset (MR) input
asynchronously clears the register. A low
level on the Preset (P) input asynchronously sets the entire register if the control code
inputs specify a 16-bit polynomial; in the

!ii!lDotiC!i

113

OBJECTIVE SPECIFICATION

8X01-A,F

TRUTH TABLE
12L INJECTOR CURRENT SOURCE

SELECT CODE
POLYNOMIAL

REMARKS

S2

S1

So

L

L

L

X16+X15+X2+ 1

CRC-16

L

L

H

X16+X14+X+ 1

CRC-16 REVERSE

L

H

L

X16+X15+X13+X7+X4+X2+X1+1

L

H

H

X12+X11+X3+X2+X+ 1

H

L

L

X8+X7+X5+X4+X+1

CRC-12

VCC - VJJ (5.0 - 0.8) V
RJJ
Ijj
=

H

L

H

X8+1

LRC-8

H

H

L

X16+X12+X5+ 1

CRC-CCITT

H

H

H

X16+X11+X4+ 1

CRC-CCITT REVERSE

60mA

4.20V = 700n
60mA

TEST CIRCUIT
LOGIC DIAGRAM

POLYNOMIAL
SELECT
LOGIC

DATA IN

CP

DATA OUT

INPUTIOUTPUT CIRCUITS

MASTER
RESET

INPUT STRUCTURE

TTL
INPUTS

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(Unless Otherwise Noted)
LIMITS
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OUTPUT STRUCTURE
V,H Input high voltage
V,L Input low voltage
V Ie Input clamp diode voltage
VOH Output high voltage
VOL Output low voltage

"H Max. input current
"H Input high current
I,L

Input low current

lOS Output short circuit current
Injection current
IJJ
I ee Supply current

114

2.0

V

Vee = MIN, liN = 18mA
Vee = MIN, 10H = 400p,A

Vee = MAX, Inputs open
Vee = MAX, inputs open

V

-1.5

V

0.5
0.1
20

V

V

2.7

Vee = MIN, 10L = 8mA
Vee = MAX

vee = MAX, V IN = 2.7V
vee = MAX, V,N = OAV
vee = MAX, VOUT = OV

0.8

-10
60
10

S!!IDOliCS

FROM

rnA

TTL

p,A

-0.36

rnA

-42

mA

100

mA
mA

18

12 l
OUTPUTS

NOTE: ALL RESISTORS VALUES ARE TYPICAL AND IN OHMS.

8X01-A,F

OBJECTIVE SPECIFICATION

SWITCHING CHARACTERISTICS TA = 25°C, IJJ = 60mA

TEST CONDITIONS

PARAMETER

Clock pulse width (low)
Setup time, Data to Clock
Setup time, CWE to Clock

Fig. 2
Fig. 5
Fig. 5
Fig. 5
Fig. 3

twMR(H)

Hold time, Data, CWE to Clock
Preset pulse width (low)
Master reset pulse width (high)

tREC
f max

Recovery time, MR, Preset to Clock
Maximum clock frequency

twCP(L)
tsD
tsCWE
tn
twP(L)

LIMITS

LIMITS

VCC=5V

VCC=4.5V

MIN

TYP

MAX

MIN

TYP

MAX

ns
ns
ns

30
60
45

75
65

ns
ns

0

CL = 15pF

UNITS

40

8

10

ns
ns
MHz

CL = 15pf

80

95

ns

CL = 15pf

110

125

ns

40

Fig. 5
Fig. 3,4

60

90

propagation delay
tPLH,tPHL Clock, MR, Preset to Data output
propagation delay

Fig. 2,3,4

tpLH,tpHL Clock, MR, Preset to Error Output

CHECK WORD GENERATION
DATA

CHECK WORD
(NOTE

0-.........- - - - - - - - - - - - 1

1E~~gL3~ o-~~-------__._-__._-L~
NOTE 2

VOLTAGE WAVEFORMS
CWE

P

D
CLOCK

0 - - - - 1 CP

CRC
GENERATOR/
CHECKER

PROPAGATION DELAYS
CP TO Q AND CP TO ER

Q I-------i'--J

MR

NOTE 2

NOTES:
1. Check word Enable is HIGH while data is being clocked. LOW during transmission of check bits.
2. 8XO 1 must be reset or preset before each computation
3. CRC check bits are generated and appended to data bits.

Figure 3

Figure 2

PROPAGATION DELAYS, P TO Q AND ER
PLUS RECOVERY TIME P TO CP

PROPAGATION DELAYS,
MRTO Q AND ER
PLUS RECOVERY TIME, MR TO CP

SET UP AND HOLD TIMES
D TO CP and CWE TO CP

DOR eWE

Figure 4

Figure 5

Si!lDotiCS

Figure 6

115

IX"8

AM FM FREQIIENCY SYNtHESllER

8X08-XA,F

DESCRIPTION

FEATURES

This lSI integrated circuit performs the
digital control functions required for generating AM/FM radio frequency local oscillator signals using digital phase locked loop
techniques. By the use of low power
Schottky and Eel technologies on the
Same substrate it is possible to operate at
80M Hz input frequencies with an average
system power of 1.6mW per gate typical.

•
•
•
•
•
•

PHASE LOCKED LOOP
PRINCIPLES
Digital phase lOcked loops are comprised of
4 basic building blocks: A fixed reference
frequency generator (crystal oscillator and
divider), a phase comparator, a voltage
controlled oscillator (VCO) and a programmable counter (+N).
In cases where very high frequencies must
be generated, a fixed prescaler (+M) is employed to divide the local oscillatorfrequency down to a frequency compatible with the
programmable counter. Fout from the VCO
is divided down by the prescaler and programmable counters and compared to the
reference frequency by the phase detector.
If Fout is not equal to Fref in phase and
MN
frequency, the phase detector generates a
signal which causes the VCO frequency to
increase or decrease until Fref = Fout, when
MN
this occurs, the local oscillator is essentially
as stable as the crystal reference oscillator.
The local oscillator frequency (Fout) is
changed by programming a different number into the programmable counter. The
distance between discrete frequencies or
the channel spacing is determined by the
reference frequency.

PIN CONFIGURATION

80MHz input frequency
ECl prescaler
lS process
Single 5V supply
Power dissipation-600mW (max)
External components• 1 crystal
• 2 capacitors

For the AM/FM circuit, up to 200 channels
are possible with selectable channel spaci ng of 10kHz for AM operation and 2000
channels at 100kHz for FM operation.

AM/FM Frequency Synthesizer
Circuit Description
The frequency synthesizer circuit logic diagram is shown below. Following is a description of each of the major blocks.

Programmable Counter
The programmable counter conSists of 3
stages of decade counter plu~ a divide by 1
or 0 counter to divide by numbers up to
1999. BCD programming data is presented
to the dividers in parallel form, one digit at a
time. Parallel data is strobed into internal
latches via strobe signals; one strobe for
each digit. A + 5 80MHz ECl prescaler precedes the programmable counter for FM
operation. This prescaler plus an external
160MHz + 2 flip-flop provide a + 10 160MHz
prescaler (+M) function to scale the programmable counter input frequency down
to 16MHz maximum. A logic control circuit
bypasses the +M prescaler and the first
decade counter for AM operation. By this
technique, the channel spacing is programable to 10kHz for AM operation and
100kHz for FM operation.

VCO
An externally provided integrator and voltage controlled osCillator must be provided
to perform the complete frequency synthesizer function. The integrator converts the
pulses that come from the phase detector
into a dc signal that controls the output
frequency of the voltage controlled oscillator. It is in the integrator part of the circuit
that the critical loop constants are determined. The voltage controlled oscillator is
normally a lC tuned oscillator with varactor
diode tuning that is controlled by the dc
signals from the integrator. In this case, two
are required, one for the AM band and one
for the FM band. The FM oscillator output
must be +5V ECl compatible while the AM
oscillator must be TTL compatible.

116

XA,F PACKAGE

Si!lDotiCS

PHASE LOCKED LOOP
BLOCK DIAGRAM
r-- - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - -

FOUl

--1

FREF

MN
FOUl = MNREF
CHANNEL SPACING
8X08

FOUl
-N-

MFREF

8108

#\11 FM FREQUENCV SYNTIIESIIER

8X08-XA,F

Phase Detector Circuit

PHASE DETECTOR CIRCUIT

The phase detector is a digital edgedetecting device that provides an output
three-state signal that is in a high impedance state when the 2 input signals are
equal in phase and/or frequency. The output of the phase detector is a series of
pulses that swing from the high impedance
state to .3V typical or from the high impedance state to 4.2V typical. If the positive
edge of the divider input leads the reference, the pulses will go to 4.2V. If it lags they
will go to .3V.

1121

The width of the output pulses is a function
of the time between the positive edges
(phase) of the 2 signals. An example of the
operation of the device is shown where the
reference signal is twice the frequency of
the divider signal and has a phase lead of
270 0 • The output pulses are converted to a
dc signal by integrating amplifiers causing
the output frequency of the voltage controlled oscillator to increase or decrease
(increase in this case) until the divider output and the reference output are equal in
phase and frequency.

1131
LOCK

DIVIDER

::J

I I I I I I

I

I

"1"
REFERENCE

"0"

UP

"'T1J
"0"

u u u

L

"1"
DOWN

"0" _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - - - - - - - - - - - -

NOTE: _ _ _ IS HIGH IMPEDANCE STATE.

S!!)DotiCS

117

CK = CLOCK
R = RESET
CE = COUNT ENABLE

VCC = 111
GND = 191

DATA BUFFER

KD4

11S1

Ps

KD3

1171

P4

KD2

1161

P2

KDl

1151

P1

FM

L.O.

L.O.

10 XHZ

~
AM/FM
PHASE
DETECTOR
OUTPUT

RC NETWORK

(5.51

ex>
X
ex>

o

X

]>

11

8X08

AM EM FRFQIIFNlZf SfNTHESI1FR

axoa-XA,F

RECOMMENDED OPERATING CONDITIONS
LIMITS
PARAMETER

TA
Vee

Operating free air temperature
Supply voltage
Max AM local oscillator input
operating frequency (Pin 11)
Max FM local oscillator input
operating frequency (Pin 10)
Maximum reference frequency
oscillator operating frequency

UNIT
Min

Typ

Max

-40
4.75

5.0

+a5
5.25

20
100

°e
V
MHz

ao

10

MHz
MHz

ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING CONDITIONS
LIMITS
PARAMETER

TEST CONDITIONS

UNITS
Typ

Min
VIH

VIL

VI

High level input voltage
P, K 0, AM/FM inputs
AM L.O. input
FM L.O. input
Low level input voltage
P, K 0, AM/FM inputs
AM L.O. input
FM L.O. input
Input current at maximum input voltage
P, K 0, AM/FM inputs
AM L.O. input
(with 5k n pullup to Vec)
FM L.O. input

Max

5.25

V
V
V

3.75
o.a
3.3

V
V
V

Vee = max, V I = 16V
Vee = max, VI = 5.25V

200
40

J.1A
J.1A

Vee = max, VI = 5.25V
Vee = max, VI = 5.25V

200
400

J.1A
j.1A

5.25
2
4.1

DC ELECTRICAL CHARACTERISTICS
LIMITS
PARAMETER

UNITS

TEST CONDITIONS
Min

IlL

VOL

VOH

lee

Low level inputs current
P, K 0, AM/FM inputs
AM L.O. input
(with 5k n pullup to Vee)
FM L.O. input
Low level output voltage
System clock output
Lock indicator output
Phase detector output
High level output voltage
Phase detector output
High level output current
System clock output
Lock indicator output
Supply current

Vee = max, VI = 3.75V
Vee = max, VI = OAV
Vee = max, VI = OAV

-.7

Vee = min, IOL = 16mA
Vee = min, IOL = 16mA
Vee = min, IOL = 40J.1A
Vee = min, IOH = -40j.1A
Vee = min, VOH = 16V
Vee = min, VOH = 16V
Vee = max

!ii!lDotiC!i

Typ

Max

-40

j.1A

-1.6
-40

mA
j.1A

o.a
o.a
0.5

V
V
V

250
250
130

j.1A
j.1A
mA

Vee- O.5V

119

8"08

ii" I M I'EQIII NOI SIN IHESIZER

8X08-XA,F

Crystal Oscillator Circuit
In this circuit, the cross-coupled transistor
pair form a bistable circuit. The crystal
provides positive feedback between the
emitters of T 15 and T 16 which causes the
circuit to oscillate at the crystal frequency.

CRYSTAL OSCILLATOR CIRCUIT

R17

13K

Rg
34K
OSCILLATOR OUTPUT
3.6 MHZ

120

!i!!lDotiC!i

AnAlOG
Commercial

DEVICE

DESCRIPTION

NE/SE540
NE541
NE542
NE543
NE544
NE546
NE570/571
NE/SE5596
flA758
ULN2111
ULN2208
ULN2209
TBA120S/u
TBA1440
TCA440
TBA327/395/396
CA3089
PA239
LM381/381A
LM382
LM387
MC1496-1596

CONSUMER/COMMUNICATION
CIRCUITS
Power Driver
Power Driver
Dual Preamp
Servo Amplifier
Servo Amplifier
AM Radio
Analog Compandor
Balanced Modulator/Demodulator
Stereo Decoder
FM Detector/Limiter
FM Gain Block
FM Gain Block
TV Sound IF
TV Video IF
AM Radio
TV PAL Chroma Set
FM IF System
Dual Preamp
Dual Preamp
Dual Preamp
Dual Preamp
Balanced Modulator/Demodulator

NE/SE560
NE/SE561
NE/SE562
NE/SE564
NE/SE565
NE/SE566
NE/SE567

PHASE LOCKED LOOPS
Phase Locked Loop
Phase Locked Loop
Phase Locked Loop
Phase Locked Loop
Phase Locked Loop
Function Generator
Tone Decoder PLL

LM101/201
LM 101 A/201 A/301 A
LM 107/207/307
LM 1 08/208/308
LM108A/208A/308A
LM 124/224/324
SA1458
SA534
SA709
SA741
SA747

OP AMPS
High Slew Rate Op Amp
Dual Op Amp
High Slew Rate Op Amp
FET Input Op Amp
High Performance Op Amp
Dual Op Amp
OpAmp
FET Input Op Amp
General Purpose Op Amp
Dual Op Amp
General Purpose Op Amp
High Performance Op Amp
High Performance Op Amp
General Purpose Op Amp
Precision Op Amp
Precision Op Amp
Quad OpAmp
Dual Op Amp
Quad Op Amp
OpAmp
General Purpose Op Amp
Dual Op Amp

NE/SE/SA553
NE/SE/SA554
NE/SE/SA555
NE/SE/SA556
NE557

TIMERS
Quad Timer
Quad Timer
Timer
Dual Timer
Unijunction Oscillator

NE/SE531
NE/SE/SA532
NE/SE535
NE/SU536
MC1456/1556
MC1458/1558
flA 709/709C
flA74O/740C
flA741 /741C
fl A747 /747C
~748/748C

!ii!)DotiC!i

Military
/883B

•
•
•
•
•

233
N/A
241
245
N/A
247
N/A
305
292
307
315
318
321
324
N/A
N/A
N/A
307
296
299
302
305

•
•
••
•
•
•
•
•
•
•
•
•
•
•
••
•
•
•
•
•
•
•

•
••
•
•
•
•
•
•

•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•
•

Data
Book
Page
Ref.

•

257
262
267
N/A
274
279
292

•
•
•
•
•
•
•
•
•
•

42
47
50
51
85
87
89
91
93
96
100
56
60
69
172,76
80
82
87
103
89
93
96

•

155
155
158
162
N/A

•

121

AnAlOG
DEVICE

DESCRIPTION

SD200/201
SD202/203
SD300/301
SD303
SD304
SD305
SD306
SD307
SD308
SD6000

MOSFET-RF (D-MOS)
Single Gate UHF
Single UHF
Dual Gate UHF
Dual Gate UHF
Dual Gate VHF
Dual Gate VHF Mixer
Dual Gate VHF Amp
Dual Gate UHF Mixer
Dual Gate UHF Amp
VHF Mixer/Amp IC

SD210/211
SD212/213
SD214/215
SD5000/5001
SD5100/5101
S05200
SD5300

MOSFET-ANALOG/DIGITAL
SWITCH ES (D-MOS)
Switch/Driver
Switch
Switch
Quad Switch Array IC
Quad Multiplexer IC
Quad Switch Driver IC
8x2 Crosspoint Switch

NE/SE501
NE/SE592
/-lA733/733C

VIDEO AMPLIFIERS
Video Amp
Video Amp
Video Amp

NE/SE510
NE/SE511
NE/SE515

01 FFE R ENTIAL
AMPLIFIERS
Dual Differential Amp
Dual Differential Amp
Differential Amp

LM 109/209/309
NE/SE550
/-lA723/723C
SA723
7805/06/08/12/15/18/24
78L02/05/06/12/15
78M05/06/08/12/15/20/24
LM 340-05/06/08/12/15/18/24
LM341-05/06/08/12/15/18/24

/-lA711/711C
LM111/211/311

COMPARATORS
High Speed Dual Differential
Comparator/Sense Amp
Analog Voltage Comparator
Analog Voltage Comparator
Analog Voltage Comparator
Differential Voltage
Comparator
Dual Comparator
Comparator

LM119/219/319

Dual Comparator

LM139/239/339
LM139A/2\39A/339A
MC3302
SA539

Quad
Quad
Quad
Quad

NE521/522
NE/SE526
NE/SE527
NE/SE529
/-lA71 0!71 OC

122

VOLTAGE REGULATORS
5V Power Voltage Regulator
Precision Voltage Regulator
Precision Voltage Regulator
Precision Voltage Regulator
Three Terminal Positive
Voltage Regulators
Three-Terminal Positive
Voltage Regulators
Three-Terminal Positive
Voltage Regulators
Voltage Regulators
Voltage Regulators

Comparator
Comparator
Comparator
Comparator

Si!lDOliCS

Commercial

Military
/883B

Data
Book
Page
Ref.
204,
206
206
212
212
212
218
221
N/A
N/A
228

•
•
•

•
•
•
•
•
•
•
•
•
•
•
••
•

209
209
209
224
224
224
N/A

•
•

166
167
172

•

•

•
•
•
••
•
•
•
•
••
•

•
•
•

•
•
•
•
•
•
•
•
•
•
•
•

•

106
107
109
147
112
116
122
130
139
151
N/A

177
183
184
187

•
•
•
•

202
203
190,
192
194,
195
197
198
200
N/A

CIIAPTIR4
APPliCATions

!i!!lDotiC!i

123

124

!i!!lDOliC!i

INTRODUCTION
The ability of the semiconductor industry to
manufacture complete general purpose
processors on single chips represents a
significant technological advance which
should prove to be of great benefit to digital
systems manufac~urers. In terms of chip
size and density of transistors, the processors are simply extensions of the continually evolving MaS technology. But in terms of
function provided, a significant threshold
has been crossed.
By allowing designers to convert from hardware logic to programmed logic, the integrated processor provides several important advantages.
1. Logic functions may be implemented in memory bits instead of logic gates. The user then has
greater access to the advantages of memory
circuits. Memories use patterned circuitry and
thus provide greater density and therefore
greater economy.
2. Random logic implementations of complex
functions are highly specialized and cannot be
used in other applications. They are not often
used in large volume. Programmed logic, on
the other hand, relies on general purpose processor and memory circuits that are used in

many applications. Thus, economies of volume
are available for both the user and the manufacturer.
3. Because the functional specialization resides
in the user's program rather than the hardware
logic, changes, corrections and additions can
be much easier to make and can be accomplished in a much shorter time.
4. With the programmed logic approach it is often
possible to add new features and create new
products simply by writing new programs.
5. The design cycle of a system using programmed logic can be significantly shorter
than a similar system that attempts to use
custom random logic. The debugging cycle is
also greatly compressed.

A general purpose processor designed to
implement programmed logic has many
characteristics that allow it to do conventional computer operations as Well. Many
applications will specialize in programmed
logic or in data processing, but some will
take advantage of both areas. In a line
printer application, for example, a processor can act primarily as a controller handling the housekeeping duties, control sequencing and data interfacing for the
printer. It also might buffer the data or do
some code conversions, but that is not its
primary duty. On the other hand, in a text

!ii!lDotiC!i

editing intelligent terminal, the processor is
mainly concerned with data manipulation
since it handles code translations, display
paging, insertions, deletions, line justification, hyphenation, etc.
A pOint-of-sale type of terminal represents
an application that combines both control
and data processing activities for the processor. Coordinating the activities of the
various devices and displays that make up
the terminal is an important part of the job,
as are the calculations that are essential to
the operation of the machine.
Because of the diversity of application
areas, a single microprocessor type cannot
effectively service all applications. Signetics offers a variety of microprocessor families, each of which has specific benefits in
the various application areas.
This chapter contains hardware and software application memos for the 8X300, 3000
families. Additional application memos are
in preparation. The services of a field applications engineer or the factory microprocessor applications staff are also available.

125

A GUIDE TO THE SELECTION OF SUPPORT COMPONENTS
FOR THE SERIES 3000 MICROPROCESSOR

AHI

3000 MICROPROCESSOR SERIES APPLICATION MEMO

INTRODUCTION
The Signetics Series 3000 Bipolar Microprocessor product line consists of the
N3001 MCU (Microprogram Control Unit)
and the N3002 CPE (Central Processing
Element). These two devices, using lowpower Schottky technology, can be readily
and efficiently interfaced with all other industry standard components, including the
7400, 74S, 74LS and Signetics 82S and 8T
families.
Figure 1 is a generalized functional block
diagram of a typical Bipolar Microprocessor
based system. This applications memo
categorizes various components that can be
used to implement each of the major functional blocks shown in Figure 1.

THE PROCESSING SECTION

BLOCK DIAGRAM OF TYPICAL BIPOLAR MICROPROCESSOR SYSTEM
DATA BUS

L.

~

'0::

'?"

""

'0::

INPUT/OUTPUT
INTERFACE

~

ADDRESS BUS

7

"

,11--

PROCESSING
SECTION
TIMING
GENERATION
AND
MISCELLANEOUS
CONTROL

Central Processing Element
Carry-look-Ahead Generator

"" rCONTROL

CONTROL

'"

'7
CONTROL SECTION

Figure 1

THE PROCESSING SECTION

High Speed Bipolar Cache Memories
DEVICE

DESCRIPTION

3101A
82825

RAM (16 words by 4 bits)
Write-While-Read RAM
(32 words by 2 bits)
RAM (16 words by 4 bits)
RAM (64 words by 9 bits)
RAM (256 words by 1 bit)
RAM (256 words by 1 bit)
RAM (256 words by 1 bit)
RAM (1024 words by 1 bit)
RAM (1024 words by 1 bit)
RAM (1024 words by 1 bit)

82825
82809
828116/117
748200/201
748301
93415A
93425A
82810/11

126

7

MAIN MEMORY

v---

ALU, General Purpose Registers,
and Carry-Look-Ahead circuits

N3002
748182

'"

MEMORY
INTERFACE

I'-

Signetics devices that can be used to implement the Processing Section of the CPU or
controller are listed below:

DESCRIPTION

~

v---

1/0 DEVICE

The Processing Section of a computer, or
"smart" controller, as shown in Figure 2,
provides facilities for the transfer of data,
logical and arithmetic manipulation of data,
and temporary storage of data, address and
status information. Cache memories are
frequently used to enhance system performance by providing immediately available
information and data to the CPU at high
speed.

DEVICE

7

L

Figure 2

Si!lDotiCS

L.

~

CONTROL

A GUIDE TO THE SELECTION OF SUPPORT COMPONENTS
FOR THE SERIES 3000 MICROPROCESSOR

AHI

3000 MICROPROCESSOR SERIES APPLICATION MEMO

THE CONTROL SECTION
The Control Section logic as shown in Figure 3, handles most, if not all, of the control
functions. These functions are typified by
operations such as decoding macroinstructions, testing of hardware or program status, initializing memory and I/O
operations, manipulating data, and sampling and responding to external and internal interrupts. These controi functions are
implemented by executing a single microinstruction or a series of microinstructions.
Through microprogramming, a structured
form of control can be realized.
Macro Instruction Decoding
DEVICE

DESCRIPTION

828100/101 Field Programmable Logic Array
(FPLA)
NOTE

CONTROL SECTION

In addition to the FPLA, all ROMs and PROMs listed below
under Conditional Test and Branch Decoding and Microprogram Memory can also be used.

Figure 3

Conditional Test and Branch Decoding
DEVICE

DESCRIPTION

828123
82823
828229
828226
828129
828126
82827

PROM (32 words by 8 bits)
PROM (32 words by 8 bits)
PROM (256 words by 4 bits)
ROM (256 words by 4 bits)
PROM (256 words by 4 bits)
PROM (256 words by 4 bits)
PROM (256 words by 4 bits)

Microprogram Sequencing
DEVICE

DESCRIPTION

N3001

Microprogram Control Unit
(512-word addressability)
Control 8tore 8equencer
(1024-word addressability)

8X02

NOTE

Microprogram Memory
DEVICE

DESCRIPTION

828130
828131
828114

PROM (512 words by 4 bits)
PROM (512 words by 4 bits)
PROM with output latches
(256 words by 8 bits)
ROM with output latches
(256 words by 8 bits
ROM with output latches
(512 words by 8 bits)
ROM (512 words by 4 bits)
ROM (1024 words by 4 bits)
PROM with output latches
(512 words by 8 bits)
PROM (1024 words by 4 bits)
ROM (1024 words by 4 bits)
ROM (1024 words by 8 bits)
PROM (2048 words by 4 bits)
ROM (2048 words by 4 bits)

828214
828215
828230/231
8228
828115
828136/137
828236/237
828280/281
828184/185
828284/285

In addition,all ROMs and PROMs listed in Conditional Test
and Branch Decoding can also be used.

!i!!lDOliC!i

127

A GUIDE TO THE SELECTION OF SUPPORT COMPONENTS
FOR THE SERIES 3000 MICROPROCESSOR

AHI

3000 MICROPROCESSOR SERIES APPLICATION MEMO

I/O INTERFACE LOGIC

1/0 INTERFACE LOGIC

The are many different types of bus structures (See Figure 4). To save hardware and
the number of signal lines, the use of a
bidirectional bus is an excellent solution for
handling the data bus problem, while a tristate bus structure is ideal for the address
bus. In many instances, when systems of
different logic families need to be interfaced
with each other, logic level translators are
required.

u

Bus buffers and drivers
DEVICE

DESCRIPTION

8T26A

Tri-state, inverting quad bus
transceiver.
Tri-state, non-inverting quad
bus transceiver.
Tri-state 8-bit bidirectional
I/O port.
Tri-state quad bus driver
(40mA), with individual
enable/disable
Tri-state quad D-type bus (FF)
with high drive capability
Dual-line Driver
Triple line receiver with
hysteresis
Dual Communications EIA/Mll
line driver
Dual Communication EIA/MIL
line receiver with hysteresis.
Dual-line driver
Triple-line receiver with
hysteresis
Quad bus transceiver
Tri-state, non-inverting hex
buffer
Tri-state, non-inverting hex
buffer
Tri-state, inverting hex
buffer
Tri-state, inverting hex
buffer
Quad differential line drivers
Quad differential line receivers

8T28
8T31
8T09

8T10
8T13
8T14
8T15
8T16
8T23
8T24
8T38
8T95
8T96
8T97
8T98
8T100
8T110

128

~::: ::::: ::::: ::::: :::::::::: :::::::::: :::::::~ iii:: ::::::::::: :::::

:::::: :::::: :::::: ::::: :::::: ::::::::

:::::: :::::: ;:::

:::::~::::::::::::::::::::::::::::::::::::::::;::::::;:::::::::::::::::::::::::::::::::::::::::::::::::::::f::::::::::::::::::::::::::

I~:m:::::::::::::::::::::::::::::::::::::::::::::::::::~~~~~LSEC:~~::::::::::::::::::::::::::::::::::::::::::::::::;:::::::::::

r.~~~~?:::::::::::::::::::::::::::::::::::~~.;;:;:~:~~;;:::~.:.:.:.:.:.:.:.:.:.:::.:.:::.:::::.:::.:;:::::;:::::;:::::

Figure 4

Logic level translators
DEVICE

DESCRIPTION

10124
10125
8T80

Quad TTl-to-ECl driver
Quad ECl-to-TTL receiver
Quad gate TTL to Highvoltage
Hex buffer TTL to Highvoltage
MOS-to TTL translator
High-voltage to TTL

8T90
8T25
8T18

Si!lDnliCS

~!:::

A GUIDE TO THE SELECTION OF SUPPORT COMPONENTS
FOR THE SERIES 3000 MICROPROCESSOR

AHI

3000 MICROPROCESSOR SERIES APPLICATION MEMO

MEMORY INTERFACE AND
MAIN MEMORY
When dynamic MOS memory devices are
used as main memory, see Figure 5, a memory refresh scheme will be needed. Usually
sense amplifiers, address and data buffers,
and parity generators and checkers are
considered as part of the memory interface
logic.
Sense amplifiers and drivers
DEVICE

DESCRIPTION

7520

Dual core-memory sense
amplifiers
Dual core-memory sense
amplifiers
Dual core-memory sense
amplifiers
Dual core-memory sense
amplifiers
Dual core-memory sense
amplifiers
Dual core-memory sense
amplifiers
Quad TTL-M08 clock drivers
Quad TTL-M08 clock drivers
Tri-state quad bus driver
Tri-state bus receiver,
with:
Tri-state dual sense
amplifier/latch

7521
7522
7523
7524
7525
3207A-1
3207A
8T09
8T380
8T25

Figure 5

TIMING GENERATION/MISCELLANEOUS CONTROL
:::::::::::::::::::::::::::::::~~:::::~~~:::::::::::::~'~~~q:::::::::::::::::::::::::::::::::::::::::::::~::::::::::::::::~:::
':.:.:':.:.:':.:.:'~.:~.~~~.:~;:;:;:;:.:.:,:;:;:

::::

Parity generator and checker
DEVICE

DESCRIPTION

8262
74180

9-bit parity
8-bit parity

Memory refresh logic
DEVICE

DESCRIPTION

8281
8291
74123
82833
82834

Binary counter
Binary counter
Dual one-shot
Quad 2-to-1 multiplexer
Quad 2-to-1 multiplexer

MOS Memory
DEVICE

DESCRIPTION

1103
1103-1
2602-1

1K (1024X1) RAM
1K (1024X1) RAM
1K (256X4) RAM,
static
1K (256X4) RAM,
static
1K (1 024X1) RAM
4K (4096X1) RAM
4K (4096X1) RAM

2606
2102
2680
2660

Figure 6

TIMING GENERATION AND
MISCELLANEOUS CONTROL
Most timing generation requirements as
shown in Figure 6 can be met by using a
one-shot (retriggerable monostable multivibrator). If a multiple-phase clocking system
is required, additional shift registers may be
used.

Smnotics

DEVICE

DESCRIPTION

74123
9602
748194

Dual-monostable multivibrator
Dual-monostable multivibrator
4-bit bidirectional universal
shift register
4-bit parallel-access shift
registers
4-bit shift register
4-bit shift register

748195
748178
748179

129

MPI

A USER'S GUIDE TO THE SERIES 3000 MICROPROCESSOR
INTRODUCTION
The Signetics Series 3000 Schottky Bipolar
Microprocessor Chip Set has brought new
levels of high performance and flexibility to
microprocessor applications not previously
possible with MOS technology. Combining
the Schottky Bipolar N3001 Microprogram
Control Unit (MCU) and the N3002 Central
Processing Element (CPE) with industry
standard memory and support circuits
microinstruction cycle times of 100ns are
possible, when using a pipelined architecture.
In the majority of cases, the choice of a
bipolar microprocessor slice, as opposed to
an MOS device, is based on speed and
flexibility of microprogramming. Starting
with these characteristics, the design of the
Signetics Series 3000 Microprocessor has
been optimized to achieve the following
objectives:

Furthermore, systems built with large-scale
integrated circuits are much smaller in size
and require less power than equivalent systems using medium and/or small-scale integrated circuits. Therefore, the end product
is more cost effective and competitive in the
market place.

•
•
•
•
•

DESCRIPTION OF THE
N3002 CPE

the data processing section of a computer.
Several CPEs may be connected in parallel
to form a processor of any desired word
length.
A block diagram of the N3002 CPE is shown
in Figure 1.
Each CPE contains a 2-bit slice of five
independent buses. Although these buses
may be used in a variety of ways, typical
connections are:

The two components of the Series 3000 chip
set, namely, the N3001 MCU and the N3002
CPE, when combined with industry standard memory and peripheral circuits, allows
the design engineer to construct highperformance processors and/or controllers
with a minimum amount of-auxiliary logic ..
Features such as the multiple independent
address and data buses, tri-state logic, and
separate output enable lines eliminate the
need for time-multiplexing of buses and
associated hardware.

BUS
Input M
Input I
Input K
Output A

Logic replacement capability
Higher performance in terms of speed
Industry standard memory and support chips
Cooler operation
Lower total system cost

Output D

Each N3002 Central Processing Element
(CPE) represents a complete 2-bit slice of

FUNCTION
Carries data from external
memory.
Carries data from the input!
output device.
Used for microprogrammed mask
or literal (constant) value input.
Connected to the CPE Memory
Address Register as a Memory
Address Bus.
Connected to the CPE
accumulator as a data bus.

N3002 CPE BLOCK DIAGRAM
(19)

(20)

(13)

(12~

r--------t~--1~----------~~--1:----------------l
L
.
I
I
I

(11)

-~
EA

I
I

I
I
I
I
I
I
(5) X
(6) Y

-

OUTPUT
BUFFER

I

I

1

1

MEMORY
ADDRESS
REGISTER

I

I

+

t

I

I

!

I

I

(1B) ClK
(28) VCC

(14) GND

T

J.,

t t

I

~
I

~

(16) Fs
(17) F,

FUNCTION
DECODER

(24) F,
~

I

(26) F,
(25) Fo

I
I ____________
L
1,---.

iiii ,

( 21 )

t t

MULTIPLEXER
A

II tt

SCRATCHEDPAD
REGISTERS
Ro-R •• T

t

+

JI

M0

i~

1

I
I,

( 22 )

10
(2) (1)

Figure 1

130

I

MULTIPLEXER
B

------------, , --

S!!)OOtiCS

CI (10)

RO

.J

(15) F,

(27) F,

I

1•

ARITHMETIC AND
lOGIC UNIT

~

(23)

ED

+
1
T

AC REGISTER

(7) CO
(9) LI

L

OUTPUT
BUFFER

r1 r - - - - - - - - - - - - . J

K,

Ko
(4) (3)

(3)

A USER'S GUIDE TO THE SERIES 3000 MICROPROCESSOR
The microfuntion input bus (F-bus), supplied by the microprogram, controls the
internal operation of the CPE, selecting
both the operands and the operation to be
executed upon them. The arithmetic logic
unit (ALU), controlled by the microfunction
decoder, is capable of over 40 Boolean and
MNEMONIC

F GROUP

R GROUP

binary operations as outlined in the Function Description section of the N3002 data
sheet.
Standard carry propagate and generate
outputs (X and Y) are provided in the CPE
for use with industry standard devices such
K BUS

MPI
as the
74S182.

Look-Ahead

Carry

Generator

A summary of all possible operations as
defined by the FO-6 bus is given below. These
operations are classified as Logical, Control, Arithmetic, Move and Shift functions.

EQUATIONS

FUNCTIONS

INSTRUCTION TYPE: LOGICAL OPERATIONS

ANR

4

I

ALL 1

Rn!\AC ..... Rn
CI V (Rn!\AC) ..... CO

And AC with register and test result for zero.

ANM

4

II

ALL 1

M!\AC ..... AT
CI V (M!\AC) ..... CO

And M bus with AC and test result for zero.

ANI

4

III

ALL 1

AT!\I ..... AT
CI V (AT!\I) ..... CO

And I bus with AC (ORT) and test result for zero.

TZR

5

I

ALL 1

CIVR n ..... CO

Test reg for zero.

Rn ..... Rn
CI V (Rn !\K) ..... CO
K!\Rn ..... Rn

Mask reg with K bus.

5

I

K

5

II

ALL 1

5

II

K

5

III

ALL 1

5

III

K

ORR

6

I

ORM

6

ORI

LTM

TZA

CIVM ..... CO
M ..... AT
CI V (M/\K) ..... CO
K!\M ..... AT

Load M bus in AT and test for zero.
Mask and test result for zero.

CIVAT ..... CO
AT ..... AT
CI V (AT !\K) ..... CO
K!\AT ..... AT

Test reg for zero.

ALL 1

CIVAC ..... CO
Rn VAC ..... Rn

Or AC to reg, and test previous AC value for zero.

II

ALL 1

CIVAC ..... CO
MVAC ..... AT

Or M bus to AC and test previous AC value for zero.

6

III

ALL 1

CIVI ..... CO
IVAT ..... AT

OR I bus to AT and test I bus data for lero.

XNR

7

I

ALL 1

CIV(Rn!\AC) ..... CO
Rn E9AC ..... Rn

Exclusive NOR AC with R n; force CO to 1 if
(R n!\AC) is non-zero.

XNM

7

II

ALL 1

CI V (M!\AC) ..... CO
ME9AC ..... AT

Exclusive-NOR M bus with AC; force CO to 1 if
(M!\AC) is non-zero.

XNI

7

III

ALL 1

CI V (AT!\ I) ..... CO
I eAT ..... AT

Exclusive-NOR I bus with AC or T reg; force CO
to 1 if (AT /\ I) is non-zero.

11 ..... MAR
R n -1+CI ..... R n
11 ..... MAR
M-1+CI ..... AT

Set MAR to all one's.
Decrement R n conditionally.

Mask and test result for zero.

INSTRUCTION TYPE: CONTROL OPERATIONS

DSM

1

I

ALL 1

LDM

1

II

ALL 1

CLR

4

I

ALL 0

00 ..... Rn
CI ..... CO

Clear reg and force CO to CI.

CLA

4

II

ALL 0

00 ..... AT
CI ..... CO

Clear AC or T and force CO to CI.

NOP

6

I

ALL 0

Rn ..... Rn
CI ..... CO

Null operation and force CO to CI.

CSR

2

I

ALL 0

CI-1 ..... R n

Conditionally clear or set R n to all O's or 1's,
respectively.

CSA

2

II

ALL 0

CI - 1 ..... AT

Conditionally clear or set AC arT reg to all O's or 1's,
respectively.

Table 1

Set MAR to all one's.
Load conditionally decremented M bus in AC or T reg.

N3002 INSTRUCTION SUMMARY

S!!)DotiCS

131

A USER'S GUIDE TO THE SERIES 3000 MICROPROCESSOR

MNEMONIC

F GROUP

R GROUP

K BUS

EQUATION

MPI

FUNCTIONS

INSTRUCTION TYPE: ARITHMETIC OPERATIONS
ILR

0

I

ALL 0

Rn+C; ..... Rn,AC

Load AC from R n or to increment R n and load
result in R n, AC.

ALR

0

I

ALL 1

AC + Rn + CI ..... R n ,
AC

Add AC to R n or R n + 1.

0

II

ALL 0

M + CI ..... AT

Load or increment M bus to AC or T reg.

0

II

ALL 1

M + AC + CI ..... AT

Add M bus or the incremented M bus to AC (May
be used for indexing).

LMI

1

I

ALL 0

Rn ..... MAR
Rn+CI ..... R n

Load MAR with R n; 0 r increment R n.
Used to update and maintain program counter.

DSM

1

I

ALL 1

11 ..... MAR
Rn - 1+ CI ..... Rn

LMM

1

II

ALL 0

M ..... MAR
M+ CI ..... AT

Force MAR to all 1'so Conditionally decrement
Rn·
Load MAR with M bus; add 1 to M bus with result
stored in AC or T reg. Used for indirect
Addressing.

LDM

1

II

ALL 1

11 ..... MAR
M - 1 + CI ..... AT

Force MAR to all 1'so Load M bus or decremented
M bus to AC or T reg.

CIA

1

III

ALL 0

AT + CI ..... AT

Add CI to complemented value of AT. Used to
obtain 1's or 2's complement of AC or T reg.

AMA

DCA

1

III

ALL 1

AT - 1 + CI ..... AT

Decrement at by 1 conditionally.

SDR

2

I

ALL 1

Conditionally decrement or transfer AC to R n.

SDA

2

II

ALL 1

AC-1+CI ..... R n
AC - 1 + CI ..... AT

LDI

2

III

ALL 1

1-1 + CI .... AT

Conditionally decrement I bus by 1 or transfer
I bus to AC or T reg.

INR

3

I

ALL 0

Rn+CI ..... R n

Conditionally increment R n by 1 or transfer
Rn to R n.

ADR

3

I

ALL 1

Add AC to R n if CI is false. Sum + 1 if CI is true.

INA

3

III

ALL 0

AC+Rn+CI .....
Rn
AT + CI ..... AT

AlA

3

III

ALL 1

I + AT + CI ..... AT

Add I bus to Ac or T reg if CI is false;
Sum + 1 if CI is true.

Conditionally decrement AC by 1, or transfer
AC to AC or T reg.

Conditionally increment AC or T reg by 1.

INSTRUCTION TYPE: MOVE OPERATIONS
LMI

1

I

ALL 0

Rn ..... MAR
Rn+CI ..... Rn

Move R n to MAR, conditionally increment R n.
Can be used to maintain program counter.

LMM

1

II

ALL 0

M .... MAR
M + CI ..... AT

Move M bus data to MAR;
Increment M bus by 1.

SDA

2

II

ALL 1

AC - 1 + CI ..... AT

If CI is true, move AC to AC or T reg.

LDI

III

ALL 1

1-1 + CI ..... AT

If CI is true, move I bus data to AC or T reg.

LTM

2
3
5

LMF

ACM

II

ALL 0

M + CI .... AT

If CI is false, move M bus data to AC or T reg.

II

ALL 1

M .... AT
CI M ..... CO

Move M bus to AC or T reg and test for zero.

6

II

ALL 0

CI ..... CO
M .... AT

Move M bus to AC or T reg; force CO to CI.

CMR

7

I

ALL 0

CI ..... CO
Rn ..... Rn

Complement R n; forCE CO to CI.

LCM

7

II

ALL 0

CI ..... CO

M ..... AT

Load AC or T reg with complemented M bus;
force CO to CI

CI ..... CO
AT ..... AT

Complement AC or T reg;
force CO to CI.

CMA

7

III

ALL 0

Table 1

132

N3002 INSTRUCTION SUMMARY (Cont'd)

!i!!lDotiC!i

MPI

A USER'S GUIDE TO THE SERIES 3000 MICROPROCESSOR

MNEMONIC

F GROUP

R GROUP

K BUS

EQUATION

FUNCTIONS

INSTRUCTION TYPE: SHIFT OPERATIONS

SRA

0

III

ALL 0

ATL - RO
ATH - ATL
LI - ATH

Shift or rotate right 1 BIT.

ALR

0

I

ALL 1

AC + Rn + CI R n , AC

If (R n) = (AG), the operation is equivalent to
shift left by 1 bit.

Table 1

N3002 INSTRUCTION SUMMARY (Cont'd)

DESCRIPTION OF THE N3001 MCU
The Microprogram Control Unit (MCU)
controls the sequence in which microinstructions are acessed from the microprogarm (or control program) memory (ROM,
PROM, or bipolar RAM in the case of writable control store). Each microinstruction,
in turn, controls the overall operation of the
CPU and I/O functions. Since the MCU has
a 9-bit address bus, it can access up to 512
words of control program. Additional addressing capability can be implemented via
the firmware-controlled page register. Other features include:
•
•

•
•

•
•
•

•

Direct addressing of standard bipolar PROM or
ROM
advanced Organization:
The 9-bit microprogram address register and
bus are organized to address memory by row
and column.
4-bit program Latch
2 flag registers
Eleven address control functions:
3 jump and test latch functions
16 way jump and test instructions
Eight flag control functions:
4 flag input functions
4 flag output functions

A block diagram of the 3001 MCU is shown
in Figure 2.

Schottky TTL Process
45ns cycle time (typical)

The MCU uses a two-dimensional addressing scheme in the microprogram memory.
This memory, consisting of 32 rows and 16
columns, will accommodate a total of 512
words. The word length is variable, and will
depend on the application. The 32-by-16
matrix is shown in Figure 3.
The MCU is controlled directly by the microinstruction via the AC O- 6 bus and FCo-3
bus. These two control buses define a group
of jump/t~st functions to formulate the next
microinstruction address. Details on these
jump/test functions are outlined in the
Function Description section of the N3001
data sheet. A brief summary is given below:

3001 MCU BLOCK DIAGRAM

FO

I I II f f I '- f

fa

ERA
EN

FLAG
CONTROL

FC1
FC2

eoc,",
OUTPUT

1

r

f

FCO

ROW
OUTPUT

H

C.Z
FLAGS

~

FC3
ADDRESS REGISTER

FI

~

I

I

F
lATCH

ClK

I-

V

/9
ISE

lD

!

cr--c

VCC 0-----.
GNE 0-----.

~

I
NEXT ADDRESS CONTROL

t

AC1

t

AC2

PR
lATCH

ACO

AC3

h-I~

- - 0 PRO
- - 0 PR1
- - 0 PR2

AC4
AC5
AC6

I~ I~ t~ I~
Figure 2

Si,gnotics

133

MPI

A USER'S GUIDE TO THE SERIES 3000 MICROPROCESSOR

ROW AND COLUMN ADDRESS MATRIX

JCC (JUMP IN CURRENT COLUMN)

FUNCTION

NEXT COL

NEXT ROW

AC 6

5

4

3

2

1

0

MAa

7

6

5

4

MA3

2

1

0

0

0

d4

d3

d2

d1

do

d4

d3

d2

d1

do

m3

m2

m1

mo

Figure 4
32
ROWS

JZR (JUMP TO ZERO ROW)

FUNCTION

NEXT ROW

NEXT COL

AC 6

5

4

3

2

1

0

MAa

7

6

5

4

MA3

2

1

0

0

1

0

d3

d2

d1

do

0

0

0

0

0

d3

d2

d1

do

~
I

NOTE

Figure 3

When d 3 d 2 d 1 do = 1111, the ISE signal will be active. This signal can be used to communicate with the
interrupt priority logic or some other type of logic.

Figure 5

Unconditional Address Control
Functions
MNEMONIC

FUNCTION

JCC

Jump in current column.·
AC o through AC 4 are used
to select 1 of 32 row addresses in the current column, specified by MAo
through MA 3 , as the next
address. See Figure 4.
Jump to zero row. AC o
through AC 3 are used to
select 1 of 16 column addresses in row 0, as the next
address. See Figure 5.
Jump in current row. AC o
through AC 3 are used to
select 1 of 16 addresses in
the current row, specified
by MA4 through MAs, as the
next address. See Figure 6.
Jump in current column/row group and enable PRlatch outputs. AC o through
AC 2 are used to select 1 of 8
row addresses in the current row group, specified by
MA7 and MAs as the next
row address. The current
column is specified by MAo
through MA 3 . The PR-Iatch
outputs are asynchronously enabled. See Figure 7.

JZR

JCR

JCE

134

JCR (JUMP IN CURRENT ROW)

FUNCTION

NEXT ROW

NEXT COL

AC 6

5

4

3

2

1

0

MAa

7

6

5

4

MA3

2

1

0

0

1

1

d3

d2

d1

do

ma

m7

m6

m5

m4

d3

d2

d1

do

~
I

Figure 6

JCE (JUMP IN CURRENT COLUMN/ROW
6RNP AND ENABLE PR-LATCH OUTPUTS

FUNCTION

NEXT ROW

NEXT COL

AC 6

5

4

3

2

1

0

MAa

7

6

5

4

MA3

2

1

0

1

1

1

0

d2

d1

do

ma

m7

d2

d1

do

m3

m2

m1

mo

'--y---I
I
Figure 7

!i!!]DotiC!i

MPI

A USER'S GUIDE TO THE SERIES 3000 MICROPROCESSOR
Jump/Test on Flag Functions
JFL (JUMP/TEST F LATCH)
MNEMONIC
JFL

JCF

JZF

FUNCTION
Jump/test F-Iatch. AC o
through AC 3 are used to
select 1 of 16 row addresses
in the current row group,
specified by MAs, as the
next row add ress. If the cu rrent column group, specified by MA 3, is colo through
col?, the F-Iatch is used to
select col2 or col3 as the
next column address. If MA3
specifies column group cols
through C0115, the F-Iatch is
used to select COllO or COlll
as the next column address.
See Figure 8.
Jump/test C-flag. AC o
through AC 2 are used to
select 1 of 8 row adresses in
the current row group,
specified by MA? and MAs,
as the next row ad ress. If the
current column group specified by MAs is colo through
col?, the C-flag is used to
select col2 or col3 as the
next column address. If MA3
specifies column group cols
through C0115, the C-flag is
used to select COllO or COlll
as the next column address.
See Figure 9.
Jump/test Z-flag. Identical
to the JCT function described above, except that
the Z-flag, rather than the
C-flag, is used to select the
next column address. See
Figure 10.

FUNCTION

NEXT ROW

ACe

5

4

3

2

1

1

0

0

d3

d2

dl

NEXT COL

0

MAs

7

e

5

do

ms

d3

d2

dl

4

MA3

2

1

0

do

m3

0

1

f

~
I

Figure 8

JCF (JUMP/TEST C FLAG)

FUNCTION

NEXT ROW

NEXT COL

ACe

5

4

3

2

1

0

MAs

7

e

5

4

MA3

2

1

0

1

0

1

0

d2

dl

do

ms

m7

d2

dl

do

m3

0

1

c

Figure 9

JZF (JUMP/TEST Z FLAG)

FUNCTION

NEXT ROW

NEXT COL

ACe

5

4

3

2

1

0

MA7

e

5

4

3

MA3

2

1

0

1

0

1

1

d2

dl

do

ms

m7

d2

dl

do

m3

0

1

z

Figure 10

Flag Output Control Function (C, Z)
MNEMONIC

FC 3

FC 2

FFO

0

0

FFC

0

1

FFZ

1

0

FF1

1

1

FUNCTION DESCRIPTION
Force FO to O. FO is forced to the
value of logical O.
Force FO to C. FO is forced to the
value of the C-flag.
Force FO to Z. FO is forced to the
value of the Z-flag.
Force FO to 1. FO is forced to the
value of logical 1.

Flag Input Control Functions (C, Z)
MNEMONIC

FC 1

FC o

FUNCTION DESCRIPTION

SCZ

0

0

STZ

0

1

STC

1

0

HCZ

1

1

Set C-flag and Z-flag to F1. The C-flag and
the Z-flag are both set to the value of F1.
Set Z-flag to F1. The Z-flag is set to the
value of F1. The C-flag is unaffected.
Set C-flag to F1. The C-flag is set to
the value of F1. The Z-flag is unaffected.
Hold C-flag and Z-flag. The value in
the C-flag and Z-flag are unaffected.

Si!)DotiCS

135

MPI

A USER'S GUIDE TO THE SERIES 3000 MICROPROCESSOR
Jump/Test On PX Bus
and PR Latch Functions
MNEMONIC
JPR

JLL

JRL

JPX

FUNCTION

FUNCTION
Jump/test PR-Iatch. AC o
through AC 2 are used to
select 1 or 8 row addresses
in the current row group,
specified by MA7 and MAs,
as the next row address.
The four PR-Iatch bits are
used to select 1 of 16 possible column addresses as
the next column address.
See Figure 11.
Jump/test left-most PRlatch bits. AC o through AC 2
are used to select 1 of 8 row
addresses in the current
row group, specified by
MA7 and MAs, as the next
row address. PR 2 and PR 3
are used to column addresses in col4 through col 7
as the next column address.
See Figure 12.
Jump/test right-most PRlatch bits. AC o and AC, are
used to select 1 of 4 highorder row addresses in the
current row group, specified by MA7 and MAs, as the
next row address. PRo and
PRJ are used to select 1 of 4
possible column addresses
in col'2 through col'5 as the
next column address. See
Figure 13.
Jump/test PX-bus and load
PR-Iatch. AC o and AC, are
used to select 1 of 4 row
addresses in the current
row group, specified by
MA6 through MAs, as the
next row address. PX 4
through PX 7 are used to
select 1 of 16 possible column addresses as the next
column
address.
SXo
through SX3 data is locked
in the PR-Iatch at the rising
edge of the clock. See Figure 14.

TYPICAL APPLICATIONS FOR
THE SIGNETICS SERIES 3000
Because of its high performance and flexibility features, the Signetics Series 3000 is
ideally suited for use in the following types
of applications:
• Smart peripheral controllers
Disk, magnetic tape, line printers, etc.
• Data communications
Front end communications processors
Communication controllers
Intelligent terminals
• Business Applications
Automated accounting computer

136

JPR (JUMP/TEST PR LATCH)
NEXT ROW

AC s

5

4

3

2

,

0

MAs

1

1

0

0

d2

d,

do

ms

NEXT COL

7

s

5

4

MA3

2

,

0

m7

d2

d,

do

P3

P2

p,

Po

Figure 11

JLL (JUMP/TEST LEFT-MOST
PR LATCH BITS)
FUNCTION

NEXT ROW

AC s

5

4

3

2

,

1

1

0

1

d2

d,

NEXT COL

0

MAs

7

s

S

4

MA3

2

,

0

do

ms

m7

d2

d,

do

0

1

P3

P2

Figure 12

JRL (JUMP/TEST RIGHT-MOST
PR LATCH BITS)
FUNCTION

NEXT ROW

NEXT COL

AC s

s

4

3

2

,

0

MAs

7

s

5

4

MA3

2

,

0

1

1

1

1

1

d,

do

me

m7

1

d,

do

1

1

p,

Po

'---v--I
I

Figure 13

JPX (JUMP/TEST PX BUS AND
LOAD PR LATCH)
FUNCTION

NEXT ROW

NEXT COL

AC s

5

4

3

2

,

0

MAe

7

s

S

4

MA3

2

,

0

1

1

1

1

0

d,

do

me

m7

ms

d,

do

X7

Xs

Xs

X4

'--y--I
I
Figure 14

•
•
•

•

•

Point of sale systems
Automatic banking systems
Computer emulation
General purpose minicomputer
Scientific/medical lab automation
Blood analyzing systems
Patient monitoring systems
Instrument data acquisition systems
Industrial and process control
Machine tool control
Assembly line flow control
Batch mixing and weighing control
Airborne vehicle applications
Navigation control
Weapon firing control

!i!!lDotiC!i

SERIES 3000 DESIGN
EXAMPLES USING THE
CARRY LOOK-AHEAD
GENERATOR (74S182)
Example 1: The processing section of a 16bit word CPU (data loop).
The processing section of a computer consists of data manipulation logic, storage
devices, counters, and data transfer paths.
The ePE was designed to perform the functions of the processing section of a computer.

A USER'S GUIDE TO THE SERIES 3000 MICROPROCESSOR
To obtain low cost and high performance
design, parallel carry look-ahead can be
implemented using the multi-source industry standard part, 748182. For a 16-bit CPU
configuration, 8 CPE arrays, one MCU, and
a 2 stage carry look-ahead generator can be
connected as shown in Figure 15. Note that
the three state gate 8T95 is disabled by the
detection of a 8hift Right operation (8RA);
hence, its outputto the FI input of the 3001 is
placed in a high impedance state. The 8RA
operation is detected by the 6-input NAND
function. The data, address and function
buses are not shown in Figure 15, and the
following logic state definition is observed:

K bus
I bus
M bus
D bus
A bus
LI, RO, CI
X, Y

Active
Active
Active
Active
Active
Active
Active

N3001

FI, FO

Active Low

74S182

PO-P 3 (X O- 3)
G O-G 3 (Y 0-3)
P, G (X, Y)
Cn
C n +x , C n +y ,
C n +z

Active
Active
Active
Acitve

N3002

Low
Low
Low
Low
Low
Low
High

High
High
High
Low

Active Low

TYPICAl

MAX

1st stage

74S05
74S05
N3002 TXD

7ns
7ns
4.5ns
5ns
5ns
18ns

10.5ns
7.5ns
7.0ns
7.5ns
7.5ns
33.0ns

Total Delay

46.5ns

73.0ns

74S08
2nd stage

Example 2: The control section of a 16-Bit
Word CPU (control loop)
The control section of a microprogrammed
processor usually performs the following
functions:
•
•
•
•
•
•

Decodes machine instructions
Controls ALU functions (in N3002)
Controls data paths
Updates CPU hardware status
Initiates I/O or memory operations
Other miscellaneous control functions

The N3001 MCU, ROM/PROM (8ignetics
828115,828114, etc.) and minimum additional logic (such as gates, FF's or the 8ignetics' FPLA) can be used to implement the

OTHER
lOGIC

-

8T95
N3002 TXD

745182

TYPICAl
(ns)

MAX
(ns)

1st Stage
2nd Stage
-

7
4.5
6
18

10.5
7
7.5
33

For a microprogrammed CPU, one of the
most important design efforts is in the definition of the microinstruction (microword).
In general, the microinstruction consists of
a number of control fields to handle the
following functions:
• Initiation of main memory operations
• Initiation of I/O operations
• Instruction decoding
• Manipulation data transfer
• Testing machine status
• Responding to and processing interrupts
• Address sequencing

When all the possible and necessary control
functions are defined, then the microword
can be structured. The following structure is
an attempt to define a 32-bit microword that
fulfills the above-mentioned control functions (Figure 17).
When defining the microword, it is essential
to compact each field as muchas possible
without sacrificing efficiency. To illustrate
this principle, a format field is supplied
which defines multiple usage of the lower
order 9 bits, K < 8 > and K < 7:0 > of the
microword. The formats are classified as
shown in Table 3.

CONTROL SECTION OF CPU

Depending on the availability of spare
gates, the same processing section (or data
loop) can be implemented as shown in
Figure 15. The active state of all data buses
and other signals is similar to the example
shown in Figure 15. Notethatthe8hiftRight
operation again inhibits the Carry via the
74808 gate. The 74805 is used due to its
open collector type output which can be
connected to the FI input of the N3001. The
pull up is 470 n to +5V.

CARRY
lOOKAHEAD

control section of the CPU. A simplified
logic diagram of the control section is
shown in Figure 16.

lOOKAHEAD

OTHERS

MPI

(MICRO-INSTRUCTION 32 BITS)

TOTAL DELAY THROUGH DATA LOOP
35.5 (TYP), 58ns (MAX)
Table 2 PROPAGATION DELAY
ANALYSIS FOR FIGURE 15,
EXAMPLE A

MACRO INSTRUCTIONS

STATUS

(FROM MAIN MEMORY)

Figure 16

The propagation delaY' through the two
stages of 748182 is analyzed as follows:

lii!)DotiCIi

137

A USER'S GUIDE TO THE SERIES 3000 MICROPROCESSOR

MPI

16-BIT WORD CPU (DATA LOOP)

FO
3001
F1

8T95

C n +y
74S182
C

1111 I I
F6

F5

F4

F3

F2

Y1

F1

X

C n +x

1

Yo

t xt

t t

Y
74S182
Y,

x,

t t
Y

x

C n +z

y,

C n +y

Y,

x,

t t

t t

Y

Y

x

3002

flO

Cn

C n +x

Yo

0 0 0

3002

I'"

x,

P-c

LI

x

flO

flO p.-C LI

p-<

LI

Y

X

C n+z

Y,

Y,

x,

t t

t t

Y

Y

x

0

Y

p.

x

flO

p.-c

LI

FI
FO
3001

74S05

74S05
F6
F5
74S182

Cn

F4
P,

C n +x

Go

F3
F2
F1

G
74S182

Example B

Figure 15

138

x

C n +y

Y,

J

Y

S!!)DotiCS

Po

x,

C n +x

Yo

t

J

Y

t

3002

3002

flO p--..C LI

x,

t 1

Example A

+5V

C

74S182

P-

Xo

3002

3002

n

Xo

x

t t

3002

flO

Io--c

LI

n

Xo

x

3002

flO

P--c

LI

flO

MPI

A USER'S GUIDE TO THE SERIES 3000 MICROPROCESSOR
The charts illustrated in Figures 18 and 19
further define and usage of the K < 7:0 >
field:

MICROWORD STRUCTURE

(A) When FMT < 1:0> =00, the K < 7:0 > field is used
to control the Processor status logic.
(8) When FMT < 1:0> =01 or 11, the K < 7:0 > field is
used to control the I/O-Memory operations.

bits In Reg to be set at end

In

of next microinstruction

Note that the K bits in this example are used
in four different ways depending on the
format of that microinstruction. They are
used to initiate I/O operations, memory
operations, control of the processor status
word, and to provide constants/masks on
the K bus. Refer to Figure 20 for a possible
hardware implementation of the logic. This
part of the definition and the DCDR < 2:0 >
field may vary from machine to machine and
the user can exert considerable desig n flexibility and freedom here. On the other hand,
the AC < 6:0 >, FC < 3:0 > and F < 6:0 > fields
are absolutely necessary to control the
MCU and CPE arrays.
The next consideration in designing the
control section is how to enhance performance. Three basic approaches can be employed here: (no attempt is made to explore
other possibilities).
1. Use high performance parts, such as 8ignetics
FPLA (35ns typical), 4K PROM (828115, with
35ns typical), N3001 MCU (45ns typical).
2. Improve architecture by using a pipelined register to latch up the microinstruction. With this
arrangement, simultaneous execution (of the
current microinstruction) and fetching (of the
next microinstruction) can be performed. The
8ignetics PROMs, 828114 and 828115, have
output latches built-in, and they can be used as
pipelined registers. Note that in this example,
the format field FMT < 1 :0 > and the AC < 6:0 >
field should not be buffered, since the former is
used to select the section of the pipeline register to be loaded and the latter is used to sequence the microprogram address register
(setting up the next microinstruction address).
3. Use a horizontally oriented microword structure. In a horizontal structure, the microword
itself consists of a large number of bits (sometimes more than 100), and a fewer total number
of microinstructions. The purpose for having
such a wide word is the higher degree of parallelism in operation that can be achieved in the
same machine cycle.

PS Reg is set

Sets destination Sign FF
according to sign in AC, If
byte instruction. LIse
AC 7. else use AC 15

Selects the SOllIe!'! which
supplies the carry Input
to ePE array

Figure 17

FUNCTION OF K < 8 > AND K < 7:0 >

FORMAT FIELD
0

0

0

1

K
K
K
K

<
<
<
<

7:0
8>
7:0
8>

> controls PSW logic.

masks upper byte of K bus for CPEt130
> controls I/O and memory.

masks both bytes of K bus for CPE

1

0

K < 7:0 > masks lower byte of K bus for CPE
K < 8 > masks upper byte of K bus for CPE

1

1

K < 7:0 > controls I/O and memory
K < 8 > masks upper byte of K bus for CPE
Table 3

FORMAT FIELDS

CONTROL OF THE PROCESSOR STATUS LOGIC
31

I

21 20

2524
AC

60

I

I

FC

3.0

I

12 11

1413
F

6,0

I

I

FMT

10

N3002 CPE ARRAY
FUNCTION CONTROL

N3001 MCU
FUNCTION CONTROL

N3001 MCI)
CARRY CONTROL

I

98

DC DR

2,0

I

8 7

K

8

I

K 7,0

I

I

I

SPECIFY MICRO
JUMP OECODED
BY FPLA

CPE ARRAY LOWER
BYTE CONSTANT; 1 0
MEMORY CONTROL.
PSW CONTROL
DEPENDING ON
FMT 1.0

MICRO·INSTRUCTION
FORMAT. DEFINE
USAGE OF K 8
K 70

PROVIDE CPE UPPER
BYTE CONSTANT
DEPENDING ON
FMT LO

Figure 18

CONTROL OF THE I/O-MEMORY OPERATIONS

MICROPROGRAM EXAMPLES
The following examples demonstrate how a
macroinstruction may be implemented by
executing a sequence of preprogrammed
microinstructions. To make the examples
more comprehensive, a number of assumptions were made, and they are included in
the general description associated with
each of the examples.

READ WORD;
RMW.
WRITE WORD·
WRITE BYTE

ePE Pauses
untill/O-Memory
transaction done

If asserted, DeDR
2""0 is used to define
one of 8 unique
micro-branch operations

Figure 19

Si!lDotiCS

139

MPI

A USER'S GUIDE TO THE SERIES 3000 MICROPROCESSOR
Macro Instruction
MICROWORD FORMAT CONTROL LOGIC

Move Word
10

9

OP CODE

I

15

7 6
RS

I

3

2 1

I

I

4
RD

AMS

o
K 7:0

L..-_ _ _ _- ,

r---t./

AMD
Mask 7-0

RS
RD
AMS
AMD

= Source Register (0-7)
= Destination Register (0-7)
= Address Mode of Source Operand
= Address Mode of Destination Operand

K 8 ----,----j

ClK

Address modes are user definable. But for
this example let's -consider the following
assumptions:
.
AMS

= Register direct; i.e., the source operand

AMD

= Memory indirect; i.e., the effective oper-

FMT1--~~~~

~----~

is c-ontained in RS.
and address is formed by adding the
contents of the designated RD to the
base address. The b~se address is the
location following the instruction. (In
this case it is the same as the program
counter R7)'

I/O-Mem Ctrol
7-0

FMT 0 -

___--+--~

OPERATIONS
(Source) -- (Destination)
74298

STATUS: No change

PSW l09ic Ctrl
7-0

DESCRIPTION
Basic microprogram involves the following
types of operations:
1. Fetch macro instruction, update P.C.
2. Decode macro instruction into classes by
FPLA.
3. Form Destination Address.
4. Form Source Operand Address.
5. Exec;ution
.
6. Allow for interrupts at the end of execution.

CLOCK

- - - - - - - - - 1 ~>_---~

Figure 20

MOVE WORD OPERATION

Load Immediate Byte
15

11

OP CODE

I

o

8 7

10

Rn

I

SUMMARY: Fetch instruction; update program counter;
AC =JCC; FC =HCZ, FF1; F =LMI; FMT =1; K < 8 > =0; K <
7:0 > = Mem Request, Read Mem, Wait for Mem, new
instruction.

IMM

SUMMARY: Decode; M-Bus - ACCUM; AC =JPX; FC =
HCZ, FFO; F = ACM;' FMT = 2; K < 8 > =0; K < 7:0 > = O.

OPI;RATIONS
(IMM 7-o) -- Right-hand byte of R n; Left-hand
byte of Rn undisturbed.

SUMMARY: Form destination address; PC - ACCUM,
PC; AC =JCR; FC =HCZ, FFO; F =ILR; FMT =2 K < 8 > =0;
K < 7:0> = O.

R n: Refers to Ro-R7 in N3002; R7 is also
used as a Program counter.

SUMMARY: Form destination address continued; RD +
ACCUM - RD, ACCUM; AC = JPR; FC = HCZ, FFO; F =
ALR; FMT = 1; K < 8 > = 1; K < 7:0 > = use RA < 1:0 > to
select RD_

STATUS: No change

SUMMARY: Form source address; get source operand
Rs- ACCUM; AC =JCR; FC - HCZ, FFO; F = ILR; FMT =
1; K < 8 > = 0; K < 7:0 > = use RA < 1:0 > to select Rs.

Or;:SCRIPTION
The microprogram implementation of this
macro instruction involves the following
types of operations:
1. Fetch the IT]acro instruction from Main Memory; Wait for Memory until the instruction arrives
at the Instruction register of the GPU.
2. Decode instruction by FPLA into classes.
3. Formulate operand addressing ~nd execution.

140

FETCH

SUMMARY: Store operand into memory; Jump to Fetch
AC =JZR; FC = HCZ, FFO; F = LMI; FMT =1; K < 8 > =0; K
< 7:0> = use RA < 1:0 > to select RD; Write Mem, Mem
Request, enable interrupts.

Figure 21

SmDOliCS

MPI

A USER'S GUIDE TO THE SERIES 3000 MICROPROCESSOR
4. Store results in destination.
5. During the above process, the program counter
must be updated and be ready for fetching the
next macro instruction.
6. Allow for interrupt at the end of instruction
execution.

LOAD IMMEDIATE BYTE OPERATION

I

I

I

APPENDIX A
The following symbols and their meanings
apply to the N3002 instruction summary:

SYMBOL

MEANING

I,K,M

Data on the I, K, and M
buses, respectively
Data on the carry input and
left input, respectively
Data on the carry output
and right output, respectively
Contents of register n including T and AC (R-Group
I)
Contents of the accumulator
Contents of AC or T, as
specified
Contents of the memory
address register
As subscripts, designate
low and high order bit, respectively
2's complement addition
2's complement subtraction
Logical AND
Logical OR
Exclusive-NOR
Deposit into

CI,L!
CO,RO

Rn

AC
AT
MAR
L,H

+
-

1\
V
+
-+

SUMMARY: Fetch Instr.; Update Program COlJnter; AC =
JRC; FC = HCZ, FF1; F = LMI; FMT = 1 (Memory Control
Mode); K < 8 > = 0 (both Bytes); K < 7:0 > = Read Memory,
New instruction. Mem Req. Wait for Memory.

I

I

SUMMARY: Decode, M-Bus - AC; AC = JPX: FC = HCZ,
FFO; F = ACM; FMT=2 (Mask Mode); K < 8 > = 0; K < 7:0 > =
O.

I

SUMMARY: Execution; AC
(OOFF) - AC; Mask out
right byte of (IMM) AC = JCC: FC = HCZ, FF1; F = (select
F2 and RI); FMT = 2 (Mask Mode); K < 8 > = 0; K < 7:0 > =
FF.

I

I
I

,

I

SUMMARY: Execution and store results; Jump to fetch;
AC = JZR; FC = HCZ, FFO; F = ORR: FMT = 1 (Mask and
1/0 Control Mode); K < 8 > = 1 (both bytes); K < 7:0 > = Use
RAo., to access internal Rn Enable interrupts.

I

FETCH

Figure 22

APPENDIX B
The following table summarizes the Jump/
Test instructions and symbology for the
N3001.

FUNCTION

MNEMONIC

DESCRIPTION

AC s

JCC
JZR
JCR
JCE
JFL
JCF
JZF
JPR
JLL
JRL
JPX

Jump in current column
Jump to zero row
Jump in current row
Jump in column/enable
Jump/test F-Iatch
Jump/test C-flag
Jump/test Z-flag
Jump/test PR-Iatch
Jump/test left PR bits
Jump/test right PR bits
Jump/test PX-bLis

0
0
0

i
1
1
1
1
1
1
1

5

4

3

2

1

0

MAs

0
1
1
1
0
0
0
1
1
1
1

d4
0
1
1
0
1
1

d3
d3
d3
0
d3
0
1
0

d2
d2
d2
d2
d2
d2
d2
d2
d2
1
0

d1
d1
d1
d1
d1
d1
d1
d1
d1
d1
d1

do
do
do
do
do
do
do
do
do
do
do

d4
0
ma
ma
ma
ma
ma
ma
ma
ma
ma

b
0
1
1

1

1
1

NEXT ROW
7
s
5
d3
0

NEXT COL
4

d 2 d 1 do
0
0
0
m'r m6 ms m 4
m7 d 2 d 1 do
d 3 d 2 d 1 do
m7 d 2 d 1 do
m7 d 2 d 1 do
m7 d 2 d 1 do
m7 d 2 dj do
d 1 do
m7 1
m7 m6 d 1 do

MA3
m3
d3
d3
m3
m3
m3
m3
P3
0
1
X7

2

1

0

m2 m 1 mo
d 2 d 1 do
d 2 d 1 do
m2 m 1 mo
f
0
1
1
0
c
Z
1
0
P2 P1
Po
1
P3 P2
1
P1 Po
X6 Xs X4

NOTE
dn
mn
Pn
xn
f,c,z

Data on address control line n
Data in microprogram address register bit n
Data in PR-Iatch bit n
Data on PX-bus line n (active LOW)
Contents of F-Iatch, C-flag, or Z-flag, respectively

Si!lDotiCS

141

HOW TO DESIGN WITH THE CONTROL STORE SEQUENCER 8X02

MP2

INTROI)UCTION
The basic structure of a high performance
Central Processing Unit (CPU) or a "Smart"
controller can be typically classified into
two distinct but interactively related functional sections. One section is genp,rally
referred to as the Processing Section and
the other the Control Section.
With the state of the art in bipolar Schottky
technology, high-performance microprocessors are designed to perform functions
of the Processing Section. Due to the limitation on pin numbers and chip size, the
overall Processing Section is partitioned
into several functionally equivalent slices.
In today's bipolar microprocessor market,
2-bit and 4-bit slice architecture predominates. Each architecture type has its
uniqueness but, in general, a slice contains
a group of general-purpose registers, an
accumulator, special-purpose register(s),
ALU and related status flags. All of these
elements constitute the Processing Section
of a CPU.
The Control Section of the CPU is more
complex in design. Typically this section
includes the macro-instruction decode logic, test-branch decode, microprogram sequencing logic and the control store where
the microprogram resides. Aside from the
microprogram, the remaining portion of the
Control Section (macro instruction decode,
test-branch decode and sequencing), does
not lend itself to efficient partitioning into
vertical slices. This is due to the random
nature of the logic usually found in the
Control Section. However, horizontal functional grouping is possible. For example,
the macro-instruction decode and testbranch decode logic can now be replaced
by the Signetics FPLA (Field Programmable
Logic Array); the random logic traditionally
needed to implement the microprogram
sequencing can now be replaced by the
Signetics Control Store Sequencer; and, of
course, the microprogram can be stored in a
high-density PROM or ROM such as the
82S115.

GENERAL DESCRIPTION
The Signetics Control Store Sequencer is a
low-power Schottky LS I, desig ned for use in
high-performance, microprogrammed systems. The basic function of this device is to
set up the microprogram address from
which the microinstruction is fetched. All
microinstructions are assumed to reside in
the Control Store (ROMs, PROMs, or RAMs,
in the case of Writable Control Store).

1. To design an LSI that can handle most of the
essential sequencing functions normally required for efficient microprogramming.
2. To design an LSI that is easy to use.
3. To design an LSI in a 28-pin DIP and yet
maintain a high addressability of 1024 words.

Additional address requirement can be easily met by providing external page registers,
which can be either entirely or partially
controlled via the microprogram.

Following is a detailed description of all the
possible functions performed by the Control Store Sequencer. Note that the mnemonics are in parenthesis, and the logic
state is defined as True = 5V and False = OV.

FUNCTIONAL DESCRIPTION
The Control Sequencer architecture is
shown in Figure 1. The address register is a
10-bit D-type flip-flop which holds the current address. The register changes state
when the Clock is in a low-to-high transition
(edge-triggered). The address register can
be loaded with different address sources
under control of the 3 address control lines
(AC 2 - o) and 1 test input line. These sources
are:

AC2 - 0 = 000
Test and Skip (TSK)
Perform test on Test Input line.
If test is False:
Next address = current address + 1. Stack
Pointer unchanged.
If test is True:
Next address =current address + 2, i.e., skip
next microinstructions. Stack Pointer unchanged.

• All Os for reset
• Current address + 1 for simple increment
• Current address + 2 for skip
• 10-bit branch address from outside
• Stack register file output

This function is used to facilitate transfer of
control based on the result of a test on the
Test Input line.

AC2 - 0 = 001
Increment (INC)

There is a 4-level Stack Register File and a 2bit Stack Pointer, both of which respond
automatically to operations requiring a
Push (Write to Stack Register File) or Pop
(Read Stack Register File).

Next address

= current

address + 1.

This function is used to serially sequence
the address register by 1. This simple function eliminates the need for providing 10
external address lines to do a Branch to next
address.

The file is organized as a 4 word by 10-bit
matrix and operates as a LIFO. The Stack
Pointer operates as an up/down counter.

CONTROL STORE SEQUENCER ARCHITECTURE
(

I(

)(

)(

)(

)(

)(

)(

)(

)(

)

A9 A, A, A, As A, A3 A, A, Ao

t--t·-t--r-+----------------,
(

)

( )AC,
( )AC,
( )AC o
) CLK

0-1

Vcco--l
GND

<>--1

1-0 TEST

I ()

I

I

I

IL _ _ _ _ _ _

-----------------~
B9 B, B, B, B, B, B3 B,. B, Bo
(

)(

The fundamental philosophy behind the
design of the sequencer evolved around
three points.

142

A cross section of the activities that take
place within various logic elements is
shown in Table 1. The AC 2- o and the Test
Input are the variables in the chart. This
chart may be used to gain a better understanding of the device so that its capability
can be fully utilized.

)(

)(

)(

)(

)(

)(

)(

)(

)

Figure 1

Gi!)DotiCG

MP2

HOW TO DESIGN WITH THE CONTROL STORE SEQUENCER 8X02

MNEMONIC

FUNCTION
AC 21 0

DESCRIPTION

TSK

Test and skip

000

INC

Increment

001

BLT

Branch to loop if
test input true

o1

POP

Pop stack

BSR

STACK

STACK POINTER

Current + 1
Current + 2

N.C.
N.C.

N.C.
N.C.

Current + 1

N.C.

N.C.

X

TEST

NEXT ADDRESS

False
True

X
False
True

Current + 1
Stack Register File

Pop (Read)

Decretnent
Decrement

011

X

Stack Register File

Pop (Read)

Decrement

Branch to subroutine
if test input true

100

False
True

N.C.
Push (Current + 1)

N.C.
Increment

PLP

Push for looping

1

Push (Current
Address)

Increment

BRT

Branch if test input
true

1 1 0

False
True

Current + 1
Branch Address

N.C.
N.C.

N.C.
N.C.

RST

Set microprogram address output to zero

1 1 1

X

AIIO's

N.C.

N.C.

0

o1

X

Current + 1
Branch Address
Current + 1

x = Don't care
N.C.

=

No change

Table 1

AC2 - 0 = 010
Branch to Loop if Test
Condition True (BL T)
Perform test on Test Input line.
If test is True:
Next address::: address from register file
(POP). Stack Pointer decremented by 1.
If test is False:
Next address::: current address + 1. Stack
Pointer decremented by 1.
This function is used as the last microinstruction of a loop (assuming that the beginning microinstruction is a Push for Looping
AC 2 - 0 ::: 101). By means of this function, the
loop is re-executed or exited depending on
the result of the test on the Test Input line. If
the test is True, the loop will be re-executed
by using the address supplied by the Stack
Register File. If the test is False, the control
exits the loop by moving to the next address.
In either case, the Stack Pointer is kept
current automatically.

AC2 - 0 = 011
Branch to Subroutine if Test
Input True (BSR)
If test is True:
Next address::: branch address (B9-0). Push
current address + 1 - Stack Register File.
Stack Pointer incremented by 1.
If test is False:
Next address::: current address + 1. No push
on stack. Stack Pointer unchanged.

NEXT ADDRESS CONTROL FUNCTION

This function facilitates the transfer of control based on the result of the test on the
Test Input line. If the test is False, no branch
will take place and the next instruction will
be executed. If the test is True, the address
register is loaded with B9-0 (Branch Address) lines and, at the meantime, the current address + 1 is written or pushed into
the Stack Register File. The latter condition allows branching to a micro-subroutine whose beginning address is supplied by
B9-0 and, at the meantime, the return address
is saved in the Stack Register File.

AC2 - 0 = 101
Push for Looping (PLP)
Next address::: current address + 1. Stack
Pointer incremented by 1. Push (current
address) - Stack Register File.
This function is generally used as the first
microinstruction of a program loop. The
current address is saved in the Stack Register File. This function works hand in hand
with the BL T function.

AC2 - 0 = 110
Branch if Test Condition
True (BRT)
If test is True:
Next address::: branch address (B 9-0).
If test is False:
Next address::: current address + 1.
This function is used to facilitate transfer of
control based on the result of the test on the

!ii!)DotiC!i

Test Input line. If the test is True, the next
address is supplied by the B9-0 lines. If the
test is False, the .. control proceeds to the
next address.

AC2 - 0 = 111
Reset to 0 (RST)
Next address::: 0, for reset.
This function is used to reset the address to
all O's. The state of the B 9-0 lines has no
bearing on the next address setup.
The following additional functions can be
performed by the Sequencer, although they
are not related to the state of the AC 2 - 0 and
Test Input:
1. The device will power up to a known state,
which is all a's. This feature can be used to
initiate the "power on reset" subroutine.
2. When the external clock is inhibited, all internal
register contents are undisturbed. This is a
means of retaining the current address (and
therefore executing the current microinstruction) for timing delay purposes, where the unit
time is equal to the microinstruction cycle time.
The clock inhibit signal can be supplied directly
by the micro-code or it could be the status
condition of certain control logic.
3. The three state output buffers can be disabled
(placed in a high-impedance state) when an
external address source is used to access the
microprogram. This external address can be a
microp-interrupt vector, which directly accesses the starting microinstruction of the interrupt handling subroutine. If Address a is to
be reserved for initialization, then the microinterrupt vector can be asserted on any address
lines other than AD, such as A1A2A3 for 8 levels
of interrupts.

143

HOW TO DESIGN WITH THE CONTROL STORE SEQUENCER 8X02
HOW TO DESIGN WITH THE 8X02
8X02 AS PART OF CONTROL LOOP CONFIGURATION

The 8X02 is totally compatible with all bipolar TTL logic elements. A typical hardware
setup is shown in Figure 2. This example
generally represents the control loop of a
16-bit CPU. The various major block functions partitioned by the dotted line boxes
can be described as follows:
1. One FPLA is used to decode the macroinstruction.
2. One FPLA is used to decode the hardware and
program status condition.
3. A multiplexer is used to channel one of eight
conditions to the Test Input of the 8X02. The
multiplexer select control is directly supplied
by the microcode. These conditions may vary
from system to system. The multiplexer approach is a simple way to accommodate the
multitude of conditions that need to be tested.
Note that to force a 1 and 0 can be accomplished by tying the inputs to 5V and OV respectively.
4. The 8X02 is used to sequence the microprogram.
5. The eight 82S115 PROMs are used to implement a 1K-word by 32-bit microprogram. Additional PROMs may be added as required. The
address output signals (Ag-Ao) of the 8X02 can
drive up to 8mA.

(32·BIT MICROINSTRUCTION)

...--+--1--+--+-:-:1 : : :

A9
ACol

---::1
AC 2

Ao

_'---

EN
SEQUENCER

TEST

1"1
,,====;::=..~
....--------,
8X02

B,

To control the 8X02 as it is configured in
Figure 2, the firmware basically has to provide fields for:
AC 2.0:
3 bits for address control
ACK INH: 1 bit for clock inhibit
S2-0:
3 bits for multiplexer select. In a simpler design, a 1-bit field connected
directly to the Test Input pin of 8X02
may satisfy the design requirement.

As

R:: ~I~~HI~~I

l

I

74S08
I------BO

F,

~

piiiiiiiiiiiiiiii_ _ _ __

Fo

FPLA
82S100

-

FPLA
B2S100

CE

1'5

1'5
MACROINSTRUCTION
(16·BIT)

::.:

u

HARDWARE/PROG
STATUS

rJ)

>
rJ)

MICROPROGRAMMING
CONSIDERATIONS
During the design phase of the firmware (or
microprogram), the firmware engineer may
find it necessary to allocate certain addresses in the microprogram to handle specific functions which are hardware dependent. For example:

Figure 2

1. One address each may be assigned as the entry
point for subroutine handling, depending on
the way that the interrupt vector is can nected to
the address bus (Ag-o).
2. Address 0 may be assigned to handle system
initialization functions.
3. A convenient number of addresses may be
allocated to take care of memory fetch functions as well as sampling (enabling) interrupts.

144

9u

Si!lDotiCS

MP2

HOW TO DESIGN WITH THE CONTROL STORE SEQUENCER 8X02

TEST AND SKIP PROGRAMMING
TECHNIQUE

SUBROUTINE NESTING
TECHNIQUE

MP2

PROGRAM LOOPING
TECHNIQUE

(X)

(X+2)

(X+3)

I
I

INC

I

(~+N)$
I

I
1. The TSK instruction is used to facilitate
transfer of controls.
2. When executing the TSK instruction, the
Test Input is checked and, if the Test is
True, skip the next instruction and go to
address (X + 3). If the Test is False, go to the
next address (X + 2).
3. The RST instruction is used to bring the
control to address 0 where micro-interrupts
can be enabled.

Figure 3

In this subroutine the beginning address (Y)
must be presented to B9-0 inputs during the
BSR instruction. If the Branch is taken, the
return address (X + 2) will be saved in the Stack
Register File. When the subroutine is done,
issue a POP instruction to return the main
program to address (X + 2).
NOTE
Addresses are shown in parenthesis and instructions
are shown inside the blocks.

Figure 5
CONDITIONAL BRANCHING
TECHNIQUE

1. The first instruction of the loop must be a
PLP. During the execution of a PLP, the
sequencer pushes the current address (X)
into the Stack Register File.
2. The last instruction of the loop must be a
BL T instruction. When the BL Tis exeq.Jted,
the sequencer checks the "Test Input"
which is normally connected to a loop
count overflow signal. If the loop counter
does not overflow, the loop will be reexecuted. If the loop counter does overflow,
the next instruction will be automatically
accessed and executed.

Figure 6

1. N-WAY BRANCH within the same 1024
word page is possible.
2. When the Test condition is True, the branch
will be taken. The branch address is supplied via B 9- 0. In the example it is (Y).
3. When the Test condition is False, the control will proceed to the next instruction at
address (X + 2).

Figure 4

Si!lDotiCS

145

HOW TO DESIGN WITH THE CONTROL STORE SEQUENCER 8X02

4-LEVEL SUBROUTINE NESTING TECHNIQUE

Subroutine
Level #1

(M+2)

Subroutine
Level #2

I
I
I

I

(M+X)

(W+2)

I
I
I

(W+T)

Subroutine
Level #4

When applying the subroutine nesting technique, the following can be used as guideline:
1. Use the BSR instruction to branch to the subroutine if the Test Input of the sequencer is
high.
2. Use a POP instruction to return from a subroutine.
3. Caution must be exercised to avoid stack overflow or underflow.
4. A 10-bit address (beginning address of subroutine) must be supplied to the B 9 . 0 during
BSR instruction.
NOTE
Addresses are shown in parenthesis and the instructions inside blocks of flowchart.

Figure 7

146

!ii!lDotiC!i

MP2

AH3

8X300 INPUT/OUTPUT DESIGN

8X300 MICROPROCESSOR APPLICATIONS MEMO

DESCRIPTION

device regardless of whether they are selected or not.

Typical interfaces to the 8X300 employ the
8T32/33 or 8T35/36 bidirectional I/O ports.
These devices provide a single connnection between the 8X300 and the user status
control and data lines. Each interface is
denoted as an Interface Vector and is field
programmed to a specific address.

ELECTRICAL
CHARACTERISTICS OF THE
INTERFACE VECTOR
Each IV byte consists of 8 storage latches
which hold data transferred between the
Interpreter and the User System, 8 tri-state
input/output lines and 2 input/output control lines, called Byte Input Control (BIC)
and Byte Output Control (BOC) as shown in
Figure 1. The control lines functions are
summarized in Table 1. Table 2 contains a
summary of the electrical characteristics of
the IV byte.

ADDRESSING DATA ON THE
INTERFACE VECTOR
The Interface Vector is comprised of general purpose 8-bit I/O registers called Interface Vector (IV) Bytes. The IV registers
serve to select IV bytes. In order for an
instruction to access (read or write) an IV
byte, the address of that byte must be output
to the IVL or IVR registers.
Thus, two instructions are required to operate on an I nterface Vector byte:

IV BYTE PROVIDING
DYNAMICALL Y DEFINED
DATA FLOW

XMIT ADDRESS, IVL
MACHINE INSTRUCTION

< ~.,eJ
!J

I

I

!!S~~::M!

IL ___ .II

+5V -

Figure 2

IV BYTE WIRED FOR
INPUT ONLY

< ~ .,e.J
*!

r--,

iS~:::M!
L __ J

+5V

Figure 3

INPUT/OUTPUT
) CONTROL LINES

Figure 1

ADDRESS1,IVL
ADDRESS2,IVR
LB, RB

CONTROL LINES

Once the IV byte is selected (addressed) it
will remain selected until another address is
output to the same IV register. Since an IV
register (IVL, IVR) can be used only as a
destination field of an instruction, any instruction sending data to IVL or IVR can be
used to select an IV byte.

BIC
(low true)

x

L

H
H

Table 1

PARAMETER

Working storage consisting of RAM may be
connected to either or both left and right I/O
banks. An example of such an arrangement
is shown in Figure 4. Paging may be added
to the memory to extend the addressability.

FUNCTION

BOC
(lOW true)
H
L

From the user's standpoint, however, all IV
byte outputs can be read by an external

8 I/O lines in high impedance state-disable
8 I/O lines in output mode-8 bit storage
latch data available in the output lines.
81/0 lines in input mode-data can be read by Interpreter

FUNCTIONS OF THE BIC AND BOC LINES

LIMITS

TEST CONDITIONS
Min

V IH
V IL
VIC
VOH
VOL
IIH
IlL
lOS
C IN

r--,

IV CONTROL BUS

Each of the two IV registers (IVL and IVR)
may be set to select an IV byte, therefore two
I/O ports may be active at one time-one on
the Right Bank (IVR) and one on the Left
Bank (IVL). Data may be input and output in
one instruction following the selection of IV
bytes:
XMIT
XMIT
ADD

IV BYTE WIRED FOR
USER OUTPUT ONLY

The address range of IVL and IVR is 0-25510.

High level input voltage
Low level input voltage
Input clamp voltage
High level output voltage
Low level output voltage
High level input current 1
Low level input current1
Output short circuit current
Data input capacitance

2
-1
IlL = -5mA
IOH=1mA
I OL = -16mA
V IH .:: 5.5V
V IL = O.50V
VOL = OV
V IL .:: OV

Typ

UNIT
Max

5.5
0.8
-1

2.4

-20

0.5
100
-800
-200
12

V
V
V
V
V
uA
uA
mA
pF

NOTE
1. Input current is always present regardless of the state of BIC and BOC.

Table 2

IV BYTE TERMINAL ELECTRICAL CHARACTERISTICS

!i!!)DotiC!i

147

AH3

8X300 INPUT/OUTPUT DESIGN

8X300 MICROPROCESSOR APPLICATIONS MEMO

8X300 TYPICAL SYSTEM CONFIGURATION
WITH WORKING STORAGE

,.

CONTROL
BUS

.....

DATA
BUS

I

•
.....!-

~

1/0
PORT 2

.L
LB;-MCLK

.. ADDR
'I
PROGRAM
STORAGE
(PROM. ROM) ...... INS~

--- I.J __

~
!_~

W

.

RBI

-V

1/0
PORT 1

..

.L

,.

T

LEFT BANK
DEVICES
RIGHT BANK
DEVICES

SI

8X300

H
____

~

T

___

~

WORKING
STORAGE
(RAM)

Figure 4

148

S!,gnotics

8X300 APPLICATIONS

AH4
8X300 MICROPROCESSOR APPLICATIONS MEMO

FLOPPY DISC INTERFACE
DESCRIPTION

FLOPPY DISC INTERFACE

The 8X300 controls a floppy disc drive with a
minimal amount of additional circuitry. In
this example, byte assembly and disassembly are performed by the program ("bit
banging") to reduce interface circuitry. Addition of such circuitry would increase hardware costs and decrease significantly peak
processor utilization.

IV 8YTES

Data is transferred to and from the floppy
disc via 1/0 driver routines. These 1/0 driver
routines provide a standard software interface to a floppy disc and require 180 words
of program storage. When not transferring
data to and from the disc, the 8X300 is
available to service other devices such as
keyboards, displays or data communication
lines. Figure 1 illustrates the system.

DESIGN APPROACH
Data bytes are assembled or disassembled
by sensing a clock, inputing data bit or
generating clock, and outputing a data bit.
Preamble patterns, track address, and other
disc format requirements are implemented
by programming. Disc drive head must be
stepped to the desired track before data
transfer is initiated. Disc drive status is
monitored to determine any error conditions. A four step procedure is followed to
implement the design:

IV1

r--------,

FLOPPY DISC
DRIVE

BYTE DISASSEMBLY 1---JVV'v"'"
OPTIONk-C
LOGIC:

- - - -

-1-J
r:~--71

~~O~~J

I

I

I

8X300

DATA

I
I

~f\A.

___-o +5V _ _

(MEMOREX 651)

CLOCK

I
I

~----~

IV2

WR PROTECT

1. Analyze interface. Analyze floppy disc relative
to: Number of control/data lines, timing and
data rates associated with each control/data
line, and electrical characteristics of each control/data line. Determine any supplemental
circuits needed for electrical compatibility (see
Table 1).
2. Perform functional analysis. The functions to
be programmed and any which require supplemental logic are determined. In this case, supplemental logic is utilized to process the 250ns
pulses associated with DATA, CLOCK and WR
DATA. Optional logic for byte assembly and
disassembly also are shown. The programmed
functions are:
a. Byte assembly/disassembly
b. Generate preamble, track address, timing
and sector synchronization
c. Sense clock and disc status
d. Step head to desired track
3. Define the program to process input and to
generate output (see Figure 2).
4. Determine 8X300 configuration (see Table 2).

Figure 1

S!!IDotiCS

149

AH4

8X300 APPLICATIONS

8X300 MICROPROCESSOR APPLICATIONS MEMO

SIGNAL NAME
STEP IN
STEP OUT
LOAD HEAD
UNSAFE RESET
WR ENB
WR DATA
SECTOR
INDEX
TRKOO
UNSAFE
WR PROTECT
DATA
CLOCK

DATA
RATE-1

SIGNAL
DURATION

ELECTRICAL
CHARACTERISTICS

#IV
BITS

20ms
20ms
Level
Level
Level
2J..1s
Sms
160ms
Level
Level
Level
4J..1s
4J..1s

.01-10ms
.01-10ms

TTL with pullup
TTL with pullup
TTL with pullup
TTL with pullup
TTL with pullup
SOmA current
OC output
OC o!Jtput
OC output
OC output
OC output
OC output
OC output

1
1
1
1
1
1
1
1
1
1
1
1
1

.2SJ..1s
1ms
1ms

.2SJ..1s
.2SJ..1s

R = Resistor
T = Transistor
FF = Flip-Flop

Table 1

INTERFACE
REQUIRED

FUNCTION
Step head 1 track in
Step head 1 track out
Load head
Clears unsafe condition
Enables write operation
Data/clock to disc
Sector indicated
Begin of track indicator
Head on track 00
Unsafe condition indicator
Write protected disc
Data from disc
Clock from disc

2R,T
R
R
R
R
R
R,2FF
R,FF

INTERFACE ANALYSIS

FUNCTIONAL ANALYSIS

,---------------------I
WR1

I

I

WR2

I
I
I

----.... ... ---------_
~

I
I
I

.....

WR3

WR4

NO

NXTWR

TEND
NO
-

-

-

-

-

-

-

-

..,

XEC

DATBLE (R3)

XMIT

8. R1

INITIALIZE BIT COUNT

MOVE

R2. DWRDAT

WRITE DATA BIT

XMIT

1. DWRDAT

ADD

R1. R1

NZT

R1. WR3

GET DATA BYTE

JMP

NXTWR

BYTE DISASSEMBLED

MOVE

R2(1). R2

ROTATE DATA BYTE

CALL

WAIT

XMIT

O. DWRCLK

XMIT

1. DWRCLK

SEL

DSTAT

NZT

DINDEX. *+2

JMP

TEND

SEL

DCMMD

NZT

R5. TENDL

JMP

WR2

ADD

R3. R3

NZT

R3. WRO

XMIT

O. DWRCLK

XMIT

1. DWRCLK

XMIT

2. R3

JMP

WR1

XMIT

1. R5

SEL

DCMMD

JMP

WR2

CLOCK GENERATION

DECREMENT DATA POINTER

CLOCK GENERATION

RESET POINTER

SET SWITCH

I ____________________ _
L

Through P!Jt: (a) Peak data rate: 2S0K bits/sec. (b) Peak processor utilization: 97.S%, including byte assembly/disassembly. (c) Peak processor utilization: 12.2%, with external byte assembly/disassembly.
Figure 2

ROM/PROM FOR
PROGRAM STORAGE
Input Driver ..................... 76
Output Driver .................... 74
Head Step Driver ................ 30
Total .......................... 180

words
words
words
words
Table 2

150

WORKING STORAGE FOR
DATA BUFFERS

IV BYTES FOR
INPUT/OUTPUT INTERFACE

2S6 Bytes

6 IV bits for output
7 IV bits for input
Total: 2 IV bytes

8X300 CONFIGURATION

Si!lDotiCS

8X300 APPLICATIONS

AH4
8X300 MICROPROCESSOR APPLICATIONS MEMO

TELETYPE MULTIPLEXER
DESCRIPTION

TELETYPE MULTIPLEXER

The 8X300 is easily interfaced to a teletype
or similar asynchronous device. Processor
utilization is less than .1%, even when used
in a character assembly mode.
A single 8X300 can be used as a multiplexer
for many low speed asynchronous devices.
For example, the 8X300 can be used as a
front end multiplexer for a large computer
system. Figure 3 illustrates the system.

IV BYTES

IV 1

DESIGN APPROACH
A basic teletype I/O driver routine receives,
transmits and echoes a character. Character assembly/disassembly is implemented
by sensing start bit, sampling data bit and
generating output bit timing. A four-step
procedure is followed to implement the design:

TTY OUT

TELETYPE

IV 2

8X300

TTY IN

1. Analyze interface. Analyze teletype relative to:
Number of control/data lines, timing and data
rates associated with each control/data line,
electrical characteristics of each control/data
line, and determine any supplemental circuits
needed for electrical compatibility (see Table
3).
2. Perform functional analysis. The functions to
be programmed and any which require supplemental logic are determined. In this case, no
supplemental logic is required. The programmed functions are:
a. Character assembly/disassembly
b. Sense start bit
c. Generate bit timing and simultaneous character echo
3. Define the program to process input and to
generate output (see Figure 4).
4. Determine 8X300 configuration (see Table 4).

ADDITIONA
!V BYTES ...._ _ _ TO/FROM COMPUTER INTERFACE
AS
REQUIRED

Figure 3

SIGNAL
NAME

DATA
RATE

TTY OUT 9.09ms
9.09ms
TTY IN

SIGNAL
DURATION
9.09ms
9.09ms

ELECTRICAL
INTERCHARACTER- #IV FACE REISTICS
BITS au IRED
20mA current
20mA current

1

1

3R,T
4R,T,C

FUNCTION
Data to TTY printer
Data from TTY keyboard

R = Resistor
T = Transistor
C = Capacitor

Table 3

!i!!l0otiC!i

INTERFACE ANALYSIS

151

8X300 APPLICATIONS

AH4
8X300 MICROPROCESSOR APPLICATIONS MEMO

FUNCTIONAL ANALYSIS

r----------------------------------

I
I

WAIT

4.Sms
OUTPUT START
BIT

. -_ _ _...., _

I

DELAY1

I
_____ ..J

XMIT

220.R1

CALL

DELAY

XMIT

2.IVL

MOVE

TTYIN.AUX

XOR

RS.RS

XMIT

1.IVL

XMIT

1.AUX

XOR

RS.TTYOUT

MOVE

RS(11.RS

ADD

R3.R3

NZT

R3.DELAY1

WAIT 9 MSEC

SHIFT IN DATA BIT

ECHO DATA BIT

NO

------..,I

~-...L...--...,

I
I
IL _ _ _ _ _ _ _

XMIT

220.R1

CALL

DELAY

~

BYTE ASSEMBLED?

________________________ _

Through put: (a) Peak data rate: 220 bits/sec. (b) Peak Processor utilization: .05%

Figure 4

ROM/PROM FOR
PROGRAM STORAGE

WORKING STORAGE FOR
DATA BUFFERS

Teletype driver ................... 49 words
Delay routine ..................... 10 words
Total ........................... 59 words

2 bytes per Teletype

Table 4

152

8X300 CONFIGURATION

SmDDliCS

IV BYTES FOR
INPUT/OUTPUT INTERFACE
1 IV bit, for output, per Teletype
1 IV bit for input, per Teletype
Total: 2 IV bytes per 8 Teletypes

AH4

8X300 APPLICATIONS

8X300 MICROPROCESSOR APPLICATIONS MEMO

DATA CONCENTRATOR
DESCRIPTION

DATA CONCENTRATOR

The 8X300 multiplexes multiple low speed
terminals. It buffers the data in its working
storage for efficient transmission over common carrier or other data link facilities.
Single inquiry/response terminals are interfaced to a single half-duplex synchronous
line via a Universal Asynchronous Receive/Transmit (UART) interface. This eliminates
cabling to each terminal. The 8X300 transfers inquiry and response messages between terminals and a remote computer
data base via a data communications line.
Various communication data rates are accommodated by simple program modification. Figure 5 illustrates the system.

IV BYTES

TERMINALS

UART

DESIGN APPROACH
The 8X300 polls each terminal requesting
an input character or signaling an output
character. Each character is transferred
over a high speed (9600 baud) synchronous
line whose data rate determines the scan
time of the 8X300 multiplexing program.
The multiplexer program formats polling
messages, maintains status, generates and
checks the Longitudinal Redundancy Character, performs character recognition, and
buffers characters. Additional driver programs are required to communicate with the
full duplex data communications line to/
from a remote computer data base. A four
step procedure is followed to implement the
design:

8X300
TERMINALS

TO/FROM
REMOTE COMPUTER
MODEM

Figure 5

1. Analyze interface. Analyze UART relative to:
Number of control/data lines, timing and data
rates associated with each control/data line,
electrical characteristics of each control/data
line and determine any supplemental circuits
needed for electrical compatibility (see Table
5).
2. Perform functional analysis. The functions to
be programmed and any which require supplemental logic are determined. In this case, no
supplemental logic is required. The programmed functions are:
a. Maintain current line status
b. Generate synchronization pattern, poll
command, sense character synch
c. Resynchronize with clock and monitor modem and UART status
3. Define the program to process input and to
generate output (see Figure 6).
4. Determine the 8X300 configuration (see Table
6).

Si!lDOliCS

153

AH4

8X300 APPLICATIONS

8X300 MICROPROCESSOR APPLICATIONS MEMO

SIGNAL NAME
TR1-8
THRL
MR
ORR
SFD
RRD
RR1-8
PE
FE
OE
DR
THRE
TRE
CLOCK

DATA RATE
1.041 ms
1.041 ms
level
level
level
level
1.041 ms
level
level
level
level
level
level
1.041 ms

SIGNAL
DURATION

ELECTRICAL
CHARACTERISTICS

#IV
BITS

1.2-10/.1s
1.2-10/.1s

TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL

8
1
1
1
1
1
8
1
1
1
1
1
1
1

1.041ms

1.041 ms
Table 5

INTERFACE
REQUIRED

FUNCTION
Output data
Load output data
Master reset
Data received reset
Status flag disable
Receiver Register disable
Received data
Parity error
Frame error
Over run error
Data received flag
XMTR holding reg. empty
Transmitter register empty
Data rate clock

-

-

-

-

INTERFACE ANALYSIS

FUNCTIONAL ANALYSIS

JOB

--------,

I

I

I

TSYNC1

I

I
I

I
I

DEVADR
STATE
STATE, R3

TDEVADR

GET MUX STATUS

DEVADR.R2

XEC

JOB (R3). 8

JMP

MODEMI

JMP

TSYNC

JMP

TDEVADR

JMP
JMP

TCMD
RSYNC/CHAR

XMIT

SYNC R4

CAll

TRANSMIT

TSYNC

I
I

SEL
MOVE
SEL
MOVE

SEL

STATE

XMIT
ADD

1. AUX

JMP

JOB·1

STATE. STATE

SEL

DEVADR

MOVE

DEVADR. R4

CALL

TRANSMIT

SEL

STATE

XMIT

1. AUX

ADD

STATE. STATE

SELECT NEXT
JOB

TRANSMIT SYNC
CHARACTER AND
UPDATE MUX
STATUS

1

TRANSMIT DEVICE
ADDRESS AND
UPDATE MUX
STATUS

1

I
JOB·1
L
____________________
_
JMP

UPDATE STATUS
OR
PROCESS CHARACTER
LRC RECOGNITION)
(
FORMAT

Through put: (a) Peak data rate: 2880 characters/sec. (b) Peak processor
utilization 30% including modem servicing.
Figure 6
ROM/PROM FOR
PROGRAM STORAGE
Multiplexer driver ................ 156 words
Character processing '" ......... 100 words
Total .......................... 25q words
Tallie 6

154

WORKING STORAGE FOR
DATA BUFFERS
32 bytes

8X300 CONFIGURATION

S!!)DotiCS

IV BYTES FOR
INPUT/OUTPUT INTERFACE
13 IV bits for output per UART
15 IV bits for input per UART
Total: 4 IV bytes per UART

AH4

8X300 APPLICATIONS

8X300 MICROPROCESSOR APPLICATIONS MEMO

REMOTE ALPHANUMERIC TERMINAL CONTROLLER
DESCRIPTION

REMOTE ALPHANUMERIC TERMINAL COUNTER

The 8X300 interfaces to simple keyboard/
display devices with a minimal amount of
interface circuitry. The display may be buffered or the 8X300 system can supply buffering and refresh. In this example, the
personality of the keyboard/display terminal is programmed into program storage to
implement various editing and format functions. A single 8X300 can be used to control
a local cluster of alphanumeric terminals
since the processor utilization for a single
terminal is very low. Messages to and from
each terminal are transferred to a remote
computer (interface not shown). Figure 7
illustrates the system.

DESIGN APPROACH

IV BYTES
STROBE
KEYBOARD
KBDATA
7 BITS
32 CHARACTER 5X7 LED ALPHA DISPLAY

1--_>--__ 6 BITS

ROM CHARACTER
GENERATOR

8X300
3 BITS

A terminal driver routing inputs and buffers
messages in working storage. The driver
also performs character and line deletion
functions and implements a flicker free
display of the message. A special set of
control characters are used to terminate a
message and forward the message. A four
step procedure is followed to implement the
design:

....----_..
DIGIT SEL

8 BITS

DIGIT SEL
8 BITS

1. Analyze interface. Analyze keyboard and display relative to: Number of control and data
lines, timing and data rates associated with
each control/data line, electrical characteristics of each control/data line and determine
supplemental circuits needed for electrical
compatibility. Here the interfaces are completely compatible electrically (see Table 7).
2. Perform function analysis. The functions to be
programmed and any which require supplemental logic are determined. In this case, no
supplemental logic is required. The programmed functions are:
a. Store a message input from keyboard
b. Update display to produce flicker free output
c. Implement character delete, line delete editing functions
d. Recognize end of message control character.
3. Define the program to process input and to
generate output (see Figure 8).
4. Determine the 8X300 configuration (see Table
8).

•

Figure 7

S!!IDotiCS

155

AH4

8X300 APPLICATIONS
8~300

SIGNAL NAME

}

#IV

ELECTRICAL
CHARACTERISTICS

BITS

INTERFACE
REQUIRED

TTL
TTL
TTL
TTL
TTL

1
7
6
3
32

-

4msec (mjn)
4msec (min)

level
level
level
level
level

STROBE
KBDATA
ASCII
ROW
DIGIT SEL

SIGNAL
DURATION

DATA RATE

MICROPROCESSOR APPLICATIONS MEMO

16.6msec (max)
200ns (min)

Table 7

-

FUNCTION
Input Character ready
Keyboard input character
Select character
Select row of digit
Select digit for display

INTERFACE ANALYSIS

FUNCTIONAL ANALYSIS
r- - - - - - - - - - - - - - - - - - - - -

I
I
I

CHECK

XMIT

1,IVL

XEC

STRB (STROBE)

JMP

DIS

XEC

STRBO (R6)

XEC

STRB1 (R6)

JMP

DIS

MOVE

STROBE, R6

JMP

RCHAR

JMP

DIS

MOVE

STROBE, R6

MOVE

KBDATA,R5

XMIT

012H, AUX

XOR

R5, AUX

I

NZT

AUX,' +4

I

XMIT

2,IVL

XMIT

1, EOMF

I
I

I
I
I

STRB

_ _ -.J

STRBO

STRB1

RCHAR

YES

SELECT KEYBOARD

NEW CHARACTER
READY?

} m, 'N,"",,"O,"O
CHARACTER

---,

YES
YES

RUB OUT
ALT MOE

I
I

I
I

} '""",0",'
CHARACTER

} Y,", '" >OM RAG

JMP
DIS
I
IL _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

Figure 8

ROM/PROM
FOR PROGRAM STORAGE
Keyboard/driver .................

140 words

Table 8

156

WORKING STORAGE
FOR DATA BUFFERS

IV BYTES FOR
INPUT/OUTPUT INTERFACE

32 bytes per display

41 IV bits for output per display
8 IV bits for input per display
Total: 7 IV bytes per display

8X300 CONFIGURATION

Si!]DotiCS

AH4

8X300 APPLICATIONS

8X300 MICROPROCESSOR APPLICATIONS MEMO

COMPUTER I/O BUS EMULATOR
DESCRIPTION

COMPUTER I/O BUS EMULATOR

The 8X300 system emulates a Microdata
1600 I/O bus. Microdata I/O bus compatible
peripherals may then be easily connected to
and controlled by a standard 8X300 system.
A Microdata I/O bus driver program provides a standard software interface to peripheral devices and requires only 27 words
of program storage. Figure 9 illustrates the
system.

IV BYTES

0001
0002

----

DESIGN APPROACH

DATA 0
IV 1

r--

Data bytes are transferred to and from the
I/O bus in accordance with Microdata I/O
bus specifications. Control signal timing
and data transfer sequences are generated
by programming. A four step procedure is
followed to implement the design:
1. Analyze interface. Analyze Microdata I/O bus
relative to: Number of control/data lines, timing
and data rates associated with each control/data line, electrical characteristics of each control/data line and determine supplemental circuits needed for electrical compatibility (see
Table 9).
2. Perform functional analysis. The functions to
be programmed and any which require supplemental logic are determined. In this case, no
supplemental logic is required. The programmed functions are:
a. Transfer bytes in and out
b. Generate control signal timing and data
transfer sequences
3. Define the program to process input and to
generate output (see Figu re 10).
4. Determine the 8X300 configuration (see Table
10).

0000

0003
110 BUS
DRIVERS

y

0004
0005
0006
0007

T

BIC

I

+5V

BOC

~

1000
1001
1002

8X300

- r--

...

IV 2

-

DATA I

RESISTOR
TERMINATION

""

1003

MICROOATA
1600
1/0 BUS

1004
1005
1006
1007

T

I

BOC

+5V

BIC

~
COXX
IV 3

L....L.---

DRIVERS

OIXX
OOXX

I BIC

I

+5V

BOC

l

Figure 9

S!!IDotiCS

157

AH4

8X300 APPLICATIONS

8X300 MICROPROCESSOR APPLICATIONS MEMO

D
R

SIGNAL NAME

DATA RATE

ODOO-07
IDOO-07
COXX
DIXX
DOXX

level
level
4J1s
4J1s
4J1s

SIGNAL
DURATION

ELECTRICAL
CHARACTERISTICS

#IV
BITS

INTERFACE
REQUIRED

FUNCTION

open collector
TTL
open collector
open collector
open collector

8
8
1
1
1

8D
8R
D
D
D

Data/address from computer
Data to computer
Control output timing
Data input timing
Data output timing

1.25J1s
1.25J1s
.75-1.25J1s

= Open collector driver
= Resistors

Table 9

INTERFACE ANALYSIS

FUNCTIONAL ANALYSIS

MICROIO

XMIT

1.IVL

MOVE

R1. DATAO

XMIT

3.IVL

XMIT

1. COXX

XEC

TAB (R3)

PULSE ON

NOP
NOP

OUTPUT
ADDRESS
BUFFER
MEMORY

XMIT

O.COXX

PULSE OFF

MOVE

R2.IVR

NZT

R3 •. INPUT

MOVE

WS. DATAO

OUTPUT
DATA
BYTE

NOP
DELAY
BETWEEN DATA
AND
DOXX PULSE

XMIT

3.IVL

XMIT

1. DOXX

PULSE ON

XMIT

O. DOXX

PULSE OFF

XMIT

1.IVL

XMIT

2.IVL

NOP

GENERATE
1.211 8
PULSE

GENERATE
1.251'5
DOXX PULSE

NOP
NOP

TAB

Figure 10

ROM/PROM FOR
PROGRAM STORAGE

I/O Driver .......................

27 words

Table 10

158

WORKING STORAGE
FOR DATA BUFFERS

IV BYES FOR
INPUT/OUTPUT INTERFACE

Depends on peripheral

11 IV bits for output
8 IV bits for input
Total: 3 IV bytes per peripheral

8X300 CONFIGURATION

S!!IDotiCS

8X300 APPLICATIONS

AH4
8X300 MICROPROCESSOR APPLICATIONS MEMO

INTERFACE TO EXTERNAL READ/WRITE MEMORY
DESCRIPTION
The 8X300 controls the storage, retrieval
and processing of large blocks of data. Data
is stored in a large capacity (up to 64K
bytes) read/write RAM external to the 8X300
system. The memory is assembled from
widely available n-channel (n-MOS) static
or dynamic RAM circuits. Minimal interface
circuitry is required to connect the 8X300
Interface Vector bytes to the address, data
and control lines of the external memory.
Figure 11 illustrates the system.

INTERFACE TO EXTERNAL READ/WRITE MEMORY

EXTERNAL MEMORY (UP TO 65K BYTES)

IV BYTES

ADRHI
ADDRESS/CHIP SELECT

DESIGN APPROACH

8 BITS

Data bytes are read from or written into
memory through a single IV type. Two additional IV bytes are used as a 16-bit address
reg ister to the external memory. 16 bits
provide an address range of 65K bytes. The
read/write control signals to the memory
require two IV bits. Instruction sequences
are used for memory read and memory write
operations to implement 1 to 2 microsecond
memory access times. A four step procedure is followed to implement the design:

r----------,
I

I
I
I
I

NMOS RAM ARRAY

I
I
I

I

DATAIN

1. Analyze interface. Analyze n-MOS RAM circuits relative to: Number of control/data lines,
timing and data rates associated with each
control/data line, electrical characteristics of
each control/data line and determine any supplemental circuits needed for electrical compatibility (see Table 11).
2. Perform functional analysis. The functions to
be programmed and any which require supplemental logic are determined. The programmed
functions are:
a. Store memory address in IV bytes ADRHI,
ADRLO.
b. Set appropriate read/write control bits
c. Wait for memory operation complete
3. Define the program to process input and to
generate output.
a. GET instruction sequence to read memory
location addressed by contents of IV bytes
ADRHI, ADRLO (see Figure 12).
b. PUT instruction sequence to write data into
the memory location addressed by the contents of IV bytes ADRH I, ADRLO (see Figure
13).
4. Determine the 8X300 configuration (see Table
12).

DATA

~

OUT;
I
I

I
I
READ/WRITE CONTROL

I

I

L__________ ..1

Figure 11

!i!!ln~tiC!i

159

8X300 APPLICATIONS

AH4
8X300 MICROPROCESSOR APPLICATIONS MEMO

SIGNAL NAME
ADRHI

SIGNAL
DURATION

DATA RATE

ELECTRICAL
CHARACTERISTICS

# IV
BITS

TTL

8

Level

INTERFACE
REQUIRED
*

none

ADRLO

Level

TTL

8

*

none
DATA

Level

TTL

8

*

FUNCTION
Most significant
byte, Memory
address, and chip
select input
Least significant
byte memory
address
Memory data

none
R/W

500ns (min)

TTL

>250ns

1

*

none
R/W DELAY

500ns (min)

TTL

>500ns

1

*

none

Table 11

Memory read/write
control
Data enable delay
during memory
write

INTERFACE ANALYSIS

GET INSTRUCTION SEQUENCE

l
XMIT ADRHI. IVL

STORE MEMORY
ADDRESS

MOVE "ADDRESS Hr', ADRHI
XMIT ADRLO, IVL

1

ADD"",,"'
MEMORY

MOVE "ADDRESS LOW", ADRLO
I'

--------------------------------GET

SET READ CONTROL
BIT

XMIT CNTRL, IVL
XMIT 5, CNTRL

}

'CAD
DATA

XMIT 7, CNTRL
1.0,,5

XMIT DATA, IVL

<

,...----------------------/

..,

/
/
/

DELAY 250NS

..

____ J

/

/

/

/

•
•
•

READ DATA BYTE

l
Figure 12

160

Si!lDOtiCS

) DATA AVAILABLE
FOR PROCESSING

8X300 APPLICATIONS

AH4
8X300 MICROPROCESSOR APPLICATIONS MEMO

PUT INSTRUCTION SEQUENCE

XMIT ADRHI. IVl

STORE MEMORY
ADDRESS

1

MOVE "ADDRESS HI", ADRHI

ADDRESS THE
MEMORY

XMIT ADRlO, IVl
MOVE "ADDRESS lOW", ADRlO

PUT

STORE DATA IN
IV BYTE

XMIT DATA, IVl
}

MOVE "DATA", DATA

STORE
DATA

XMIT CNTRl, IVl
XMIT 2, CNTRl

XMIT 7, CNTRl
1.5/15 (

SET WRITE CONTROL
BIT

/

1

WRITE
DATA

XMIT 3, CNTRl

r-----------------------

/
/

/
/

/
____

•
•

/

DELAY 250NS

/
.J /

•
•
Throughput:
Single byte transfer time
Memory read:
833k bytes per second
Memory write:
555k bytes per second
For multiple time transfers, throughput is reduced by the time to loop and
update addresses and byte counts to approximately:
Memory read:
250k bytes per second
Memory write:
200k bytes per second

Figure 13

ROM/PROM FOR
PROGRAM STORAGE

GET sequence ....................
PUT sequence ....................

WORKING STORAGE

4 words
6 words

Table 12

None

IV BYTES FOR
INPUT/OUTPUT INTERFACE

18 IV bits for output
8 IV bits for input and output
Total: 4 IV bytes

8X300 CONFIGURATION

G!!IDotiCG

161

AH4

8X300 APPLICATIONS

8X300 MICROPROCESSOR APPLICATIONS MEMO

256 WAY BRANCH
DESCRIPTION

8X300 EXECUTE INSTRUCTION

Many data communication applications require conversion of one code structure to
another. The 8X300's Execute instruction
provides a fast and efficient method of performing this conversion.
A single Execute instruction can provide up
to a 256 way branch based on a byte stored
in a register.

CONVERT:

This assumes one of the 256 values does not
occur during operation of the Execute table.
This is easily prevented by testing for one of
the values before entering the table, thereby
completing the 256 way branch. The example in Figure 14 details how the test for R1
equal to zero is performed first (NZT). If
zero, the appropriate conversion value is
loaded into R3 (XMIT). If not zero, then the
Execute table determines which of the other
255 combinations is in R1 and loads the
appropriate conversion value in R3.

PAGE:

TABLE:
NEXT:

The 256 way branch requires 260 words of
program storage and 1.0 microseconds
maximum to execute. The Execute table
and the Execute instruction must all be
located with one 256 byte page where the
first instruction address contains zeros in
the 8 least Significant bits. The other four
instructions may be placed anywhere within
the 8X3t)0's address space.

NZT

R1. PAGE

XMIT

VALUE. R3

JMP

NEXT

JMP

TABLE

XMIT

VALUE. R3

I

XEC.

"BRANCH IF R1 to.
"SET R3 BASED ON R1 0 O.

"MUST BE AT EVEN PAGE ADDRESS

255 XMIT INSTRUCTIONS SET
R3 TO A VALUE BASED ON
CODE COMBINATION IN R1.

TABLE (R1)

"TABLE 0377.

•
•
•

PROGRAM STORAGE-260 WORDS
MAXIMUM EXECUTABLE INSTRUCTIONS-4; 1.01'5

NOTE

Value is the appropriate conversion code for each code combination in R1.

Figure 14

162

S!!IDOliCS

8X300 APPLICATIONS

AH4
8X300 MICROPROCESSOR APPLICATIONS MEMO

FAST IV SELECT
DESCRIPTION
The fast IV select is implemented by adding
bits to the instruction word, in increments of
4 or a bits. This technique allows IV bytes
and working storage to be selected within
the same instruction where it is used. This
can save important processor time by saving one instruction cycle for each select
instruction. It eliminates the need for the IV
select instruction. It trades fewer instruction
cycle times for hardware. It also trades 16bit select instructions for 4 to a-bit select
fields, thus saving a to 12 bits· of program
storage for every select instruction saved.
To some extent, this reduces the cost impact of a larger instruction word. The technique can be used on both IV and buffer
storage (including working storage). When
used on IV, a decoder is used following an
address hold latch to select one IV per
address combination. Buffer storage does
not require the decoder, instead it utilizes
the address directly.

FAST IV SELECT CONFIGURATION FOR SMALL SYSTEMS

EXTRA BITS ADDED
FOR FAST SELECT
}

ROM

IV BUS

The fast select IV can be used on the same
system with normal select IV since all the
fast select IV contains the same address.
The Master Enable (ME) input of each fast
select IV is enabled by the AND of Bank
Select (LB, RB) and the single line decode.
Due to memory access delays, the clock
used to latch the fast select address is
delayed with a couple of inverter delays to
assure address validity. On large systems,
there are extra delays which may require the
address to be programmed in the instruction prior to its usage. Then a double set of
address hold latches are used so the address will appear sufficiently early.

Figure 15

CONFIGURATION FOR LARGE SYSTEMS

BIT N

}

EXTRA BITS
ADDED FOR
FAST SELECT

BIT 1
ROM
BANK SELECT

16
INSTRUCTION

1---1---1

8X300
IV BUS

Figure 16

Si!lDotiCS

163

UNDERSTANDING THE 8X300 INSTRUCTION SET

MP3
8X300 MICROPROCESSOR APPLICATIONS MEMO

DESCRIPTION
The 8X300 has a repertoire of 8 instruction
classes which allow the user to test input
status lines, set or reset output control lines,
and perform high speed input/output data
transfers. All instructions are 16 bits in
length. Each instruction is fetched, decoded
,and executed completely in 250ns.
Data is represented as an 8-bit byte; bit
positions are numbered from left to right,
with the least Significant bit in position 7.

o1

OPERATION

ADD

MSB

LSB

Within the Interpreter, all operations are
performed on 8-bit bytes. The Interpreter
performs 8-bit, unsigned 2's complement
complement arithmetic.

1----------------..,

If Sand 0 both are

1---------------....,

register
addresses
then R L specifies a
right rotate of R/L
places applied to the
register specified by S.

Sum of AUX and data specified by
S, R/L replaces data in field specified by 0, R/L.

Type I
Type II

AND

Logical AND of AUX and data specified by S, R/L replaces data in field
specified by 0, R/L.

XOR

Logical exclusive OR of AUX and
data specified by S, R/L replaces
data in field specified by 0, R/L.

XMIT

The literal value I replaces the data
in the field specified by S, L.

INSTRUCTION FORMATS
The general 8X300 instruction format is:

NZT

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Op
Code

Operand(s)

Table 1 contains a summary of the 8X300
instruction set and description of the operand fields.
All instructions are specified by a 3-bit
Operation (Op) Code field. The operand
may consist of the following fields: Source
(S) field, Destination (D) field, Rotatel
Length (R/L) field, Immediate (I) Operand
field, and (Program Storage) Address (A)
field.

NOTES

Content of data field addressed by
S, R/L replaces data in field specified by 0, R/L.

MOVE

2 3 4 5 6 7

III I II II I

o

RESULT

FORMAT

XEC

JMP

If S is IV or WS address
then I limited to range
! - - - - - - - - - - - - - - - - j 00-37. Otherwise IlimIf the data in the field specified by S, ited to range 000L equals zero, perform the next 377.
instruction in sequence. If the data
If S specifies an IV or
specified by S,L is not equal to WS address then I is
zero, execute the instruction at adlimited totherangeOOType II
dress determined by using the liter- 37. I is limited to the
al I as an offset to the Program
Type IV
Counter.
range 000-377 otherI - - - - - - - - - - - - - - - - j wise.
Perform the instruction at address The offset operation is
determined by applying the sum of performed by reducthe literal I and the data specified by ing the value of PC to
S,L as an offset to the Program the nearest multiple of
Counter. If that instruction does not 32 (if I: 00-37) or 256 (if
transfer control, the program se- I: 000-377) and adding
quence will continue from the XEC the offset.
instruction location.
The literal value I replaces contents
of the Program Counter.

Type V

The instructions are divided into 5 format
types based on the Op Code and the form of
the Operand(s) as shown in Figure 1.

I limited to the range
00000-07777 .

Table 1 8X300 INSTRUCTION SET

INSTRUCTION FORMATS
OPERATIONS
(REGISTER TO REGISTER)
MOVE
ADD

OPERATIONS

AND
XOR

XEC

XMIT
NZT

OPERATIONS
XEC

Type I

XMIT
NZT

Type IV
8 9 10 11 12 13 1415

OPERATIONS
MOVE
AND

OPERATIONS

ADD
XOR

JMP

Type III
3 4 5 6 7 8 9 10 11
A

Type II

164

Figure 1

G!!IDOliCG

Type V

12 13 14 15

MP3

UNDERSTANDING THE 8X300 INSTRUCTION SET

aX300 MICROPROCESSOR APPLICATIONS MEMO

INSTRUCTION FIELDS

Op Code Field (3-Bit Field)
The Op Code field is used to specify 1 of 8
8X300 instructions as shown in Table 2.

S,D Fields (S-Bit Fields)
The Sand D fields specify the source and
destination of data forthe operation defined
by the Op Code field. The Auxiliary Register
is the implied source for the instructions
ADD, AND and XOR which require two
source fields. That is, instructions of the
form:

I Field (SIS-Bit Field)

A Field (13-Bit Field)

The I field is used to load a literal value (a
binary value contained in the instruction
into a register, IV or Working Storage data
field or to modify the low order bits of the
Program Counter.

The A field is a 13-bit Program Storage
address field. This allows the 8X300 to directly address 8192 instructions.

The length of the I field is based on the S
field in XEC, NZT, and XMIT instructions.

When a register is specified as the source,
and an IV or Working Storage field as the
destination, the least significant bits of the
operations (MOVE, ADD, AND, XOR) are
merged with the original destination data.
The least significant bits of the result are
stored in the IV or Working Storage data
field specified by the D and R/L fields in the
instruction.

A. When S specifies a register, the literal I is an 8bit field (Type III format).
B. When S specifies an IVorWorking Storage data
field, the literal I is a 5-bit field (Type IV format).

ADD X, Y

imply a third operand, say Z, located in the
Auxiliary Register so that the operation
which takes place is actually X + Z, with the
result stored in Y. This powerful capability
means that 3 operands are referenced in
250ns.
The S andlor D fields may specify a register,
or a 1 to 8-bit 1/0 field, or a 1 to 8-bit Working
Storage field. Sand D field value assignments in octal are shown in Table 3.

RIL Field (3-Bit Field)
The R/L field performs one of two fu nctions,
specifying either a field length (L) or a right
rotation (R). The function it specifies for a
given instruction depends upon the contents of the Sand D fields:
A. When both Sand D specify registers, the R/L
field is used to specify a right rotation of the
data specified by the S field. (Rotation occurs
on the bus and not in the source register.) The
register source data is right rotated within one
instruction cycle time independent of the number (0 to 7) of bit positions specified in the R/L
field.
B. When either or both the Sand D fields specify
an IV or Working Storage data field, the R/L
field is used to specify the length of the data
field (within the byte) accessed, as shown in
Figure 2.

OP CODE
OCTAL
VALUE

REGISTER OPERATIONS

RE$ULT

INSTRUCTION

0
1
2
3
4

MOVE
ADD
AND
XOR
XEC

S,R/L,D
S,R/L,D
S,R/L,D
S,R/L,D
I,R/L,S or I,S

5

NZT

I,R/L,S or I,S

6

XMIT
JMP

I,R/L,D or I,D
A

7

Table 2

(S) - D
(S) plus (AUX) - D
(S) 1\ (AUX) - D
(S) 0 (AUX) - D
Execute instruction at current PC
offset by I + (S)
Jump to current PC offset by I if
(S) ~ 0
Transmit li.teral I - D
Jump to program location A

INSTRUCTION SET SUMMARY

RIL FIELD

01234567
R/L FIELD
OCTAL
VALUE

o
1

2
3
4
5
6
7

SPECIFICATION
FIELD
FIELD
FIELD
FIELD
FIELD
FIELD
FIELD
FIELD

LENGTH
LENGTH
LENGTH
LENGTH
LENGTH
LENGTH
LENGTH
LENGTH

8 BITS
1 BIT
2 BITS
3 BITS 4 BITS
5 BITS
6 BITS
7 BITS

--j
..... -

-

-

-

-

-

-

Figure 2

S!!IDotiCS

16S

MP3

UNDERSTANDING THE 8X300 INSTRUCTION SET

8X300 MICROPROCESSOR APPLICATIONS MEMO
When an IV or Working Storage field of 1 to 8
bits is specified as the source, and a register
as the destination, the 8-bit result of the
operations (MOVE, ADD, AND, XOR) is
stored in the register. The operations ADD,
AND, XOR qctually use the IV or Working
Storage data field (1 to 8 bits) with leading
zeros to obtain 8-bit source data for use with
the 8-bit AUX data during the operation.
Because IVL and IVR are write-only pseudo
registers, they can be specified as destination fields only (see Table 3). Operations
involving IVL and IVR as sources are not
possible. For example, it is not possible to
increment IVR or IVL in a single instruction,
and the contents of IVL or IVR cannot be
transferred to a working register, IV byte, or
Working Storage location.
The OVF (Overflow) Register can only be
used as a source field; it is set or reset only
by the ADD instruction.

INSTRUCTION DESCRIPTIONS
The following instruction descriptions employ MCCAP (the 8X300 Cross Assembly
Program) programming notation. This notation varies somewhat from the instruction
descriptions provided in Tables 1 and 3.
Thus, for example, explicit L field definition,
as shown in Table 1 and Table 3, is not
required by MCCAP instructions; MCCAP
creates appropriate variable field addresses
from the information contained in the Data
Declaration statements provided by the programmer at the beginning of his program.
The 8X300 instruction set is described below with examples shown in Figures 3
through 10.

08 -17 8 is used to specify 1 of 7 working registers (R1-R6, R11), Auxiliary Register,
Overflow Register, IVL and IVR write-only registers.
OCTAL
VALUE
00
01
02
03
04
05
06
07

OCTAL
VALUE
Auxiliary Register (AUX)
R1
R2
R3
R4
R5
R6
IVL Register-IV Byte address
write-only register-Specified only
in D field in all instructions

a.

R~gister

10

OVF-Overflow register-Used as
an S (source) field only.
R11
Unassigned
Unassigned
Unassigned
Unassigned
Unassigned
IVR Register-Working Storage
address
write-only
registerSpecified only in D field in all instructions

11

12
13
14
15
16
17

Specification

20- 8 -27 8 is used to specify the least significant bit of a variable length field within the IVI
WS Byte previously selected by the IVL register. The length of the field is determined
by R/L.

o1
IV/WS Byte

2 345 6 7

IIIII II I I
ffftftff
I I I I I I I I
I

OCTAL
VALUE
20
21

22
23
24
25
26
27

Field
Field
Field
Field
Field
Field
Field
Field

within
within
within
within
within
within
within
within

previously
previously
previously
previously
previously
previously
previously
previously

selected
selected
selected
selected
selected
selected
selected
selected

IV/WS
IV/WS
IV/WS
IV/WS
IV/WS
IV/WS
IV/WS
IV/WS

Byte;
Byte;
Byte;
Byte;
Byte;
Byte;
Byte;
Byte;

I I I I I I I

position
position
position
position
position
position
position
position

of
of
of
of
of
of
of
of

LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB

=0
=1
=2
=3
=4
=5
=6
=7

b. Left Bank Field Specification
30 8 -37 8 is used to specify the least Significant bit of a variable length field within the
IV/WS Byte previously selected by the IVR Register. The length of the field is determined
by R/L.

o1
IV/WS Byte

2 3 4 5 6 7

IIIII II II
fI •••
fff.
I I I I I I I
, I , I I , I ,

OCTAL
VALUE
30
31
32
33
34
35
36
37

Field
Field
Field
Field
Field
Field
Field
Field

within
within
within
within
within
within
within
within

previously
previously
previously
previously
previously
previously
previously
previously

selected
selected
selected
selected
selected
selected
selected
selected

c. Right Bank
Table 3

166

Si!JDDtiCS

IV/WS
IV/WS
IV/WS
IV/WS
IV/WS
IV/WS
IV/WS
IV/WS

Fi~ld

Byte;
Byte;
Byte;
Byte;
Byte;
Byte;
Byte;
Byte;

position
position
position
position
position
position
position
position

of
of
of
of
of
of
of
of

Specification

SAND D FIELD SPECIFICATIONS

LSB = 0
LSB = 1
LSB = 2
LSB = 3
LSB = 4
LSB = 5
LSB = 6
LSB = 7

MP3

UNDERSTANDING THE 8X300 INSTRUCTION SET

8X300 MICROPROCESSOR APPLICATIONS MEMO

MOVE S,D or
MOVE S(R),D

MOVE S,D or MOVE S(R),D

Format: Type I, Type II
o

1

2

10

0

0

3

I

4

5

6

7

B

Source

9

10

11

R/L

12

13

14

15

Destination

____ MO/5, I~ ~

o

1

2

3

4

5

6

7 B 9 1011 12 1314 15
BINARY REPRESENTATION

Operation: (S)~(D)
Description

OCTAL REPRESENTATION

Move data. The contents of S are transferred
to 0; the contents of S are unaffected. If
both Sand 0 are registers, R/L specifies a
right rotate of the source data before the
move. Otherwise, R/L is implicit and specifies the length of the source and/ordestination IV/WS field. If the MOVE is between an
IV byte and a Working Storage byte, an 8-bit .
field must always be moved.

LI
L ___=======

SPECIFIES LSB OF I/O FIELD AS BIT 6
' - -_ _ _ SPECIFIES LEFT BANK I/O FIELD

.

~:~g:~:~~ ~':~~~~~RF~LD

01234567
10

1

1

0

0

1

1

01

Example

Ix

x x

X

1

Store the least significant 3 bits of register S
(RS) in bits 4, Sand 6 of the IV byte previously addressed by the IVL register.

NOTE: X'S IN THE IV BYTE DENOTE BITS UNAFFECTED BY THE MOVE OPERATION.

III
1

0

x

R5

I

SELECTED LEFT BANK IV/WS BYTE-AFTER OPERATION

ADD S,D or
ADD S(R),D
Format: Type I, Type II
Figure 3

o

1

2

0

0

1

I

3

I

4

5

6

Source

7

B

9

10

R/L

11

12

13

14

15

Destination

ADD S,D or ADD S(R),D

Operation
(S) plus (AUX) = 0; set OVF if carry from
most significant bit (bit 0) occurs.

Description
Unsigned 2's complement 8-bit addition.
The contents of S are added to the contents
of the Auxiliary Register (which is the implied source). The result is stored in 0; OVF
is updated. If both Sand 0 are registers, R/L
specifies a right rotate of the source (S) data
before the operation. Otherwise, R/L is implicit and specifies the length of the source
and/or destination IV/WS fields. Sand AUX
are unaffected unless specified as the destination.

Example
Add the contents of R1 (rotated 4 places) to
AUX and store the result in R3.

BINARY REPRESENTATION
OCTAL REPRESENTATION

10

1

0

1

1

1

1

0

11

0

0

I

1

1

0

1

1

1

0

<:::::::::

I

0

1

0

0

0

1

0 ,0

I

AUX

0

1

0

0

I

R3-AFTER OPERATION

[2J

1

R1

1

CONTENTS OF R1 ROTATED RIGHT 4 PLACES

OVF

Figure 4

Si!lDotiCS

167

UNDERSTANDING THE 8X300 INSTRUCTION SET

MP3
8X300 MICROPROCESSOR APPLICATIONS MEMO

AND S,D or
AND S(R),D

AND S,D or AND S(R),D

Format: Type I, Type II

I

o

1

2

0

1

0

I

3

4

5

6

7

Source

I

8

9

10

RIL

Operation: (S) A
Description

11

I

12

13

14

15

Destination

BINARY REPRESENTATION

(AUX)~D

OCTAL REPRESENTATION

T

Logical AND. The AND of the source field
and the Auxiliary Register is stored into the
destination. If both Sand D are registers,
R/L specifies a right rotate of the source (S)
data before the AND operation. Otherwise
R/L is implicit and specifies the length of the
source andlor destination IV/WS fields. S
and AUX are unaffected unless specified as
a destination.

' - - - - SPECIFIES REGISTER 4
SPECIFIES 4·BIT 110 FIELD

L_~==========
01234567
/1

0

0

1

0

1

0

1

~~

I

SPECIFIES RB
LSBFIELD
OF 110 AS BIT 5
SPECIFIES

SELECTED RIGHT BANK IVIWS BYTE

SELECTED FIELD RIGHT JUSTIFIED WITH LEADING ZEROS ADDED.

00000101

AND OPERATION

Example
Store the AND of the selected right bank
byte and AUX in R4. The right bank data
field is called WSBCD and is 4 bits long and
located in bits 2, 3, 4 and 5.

I
I

0

0

o

0

0

0

1

1

0

o

0

0

o

0

1

!

!
0

I

AUX

I

R4

XOR S,D or
XOR S(R),D
Figure 5

Format: Type I, Type II
o
10

1

2

1

1

3

I

4

5

6

Source

7

8

I

Operation: (S) (!)
Description

9

10

RIL

11

I

12

13

14

15

XOR S,D or XOR S(R),D

Destination

(AUX)~D

Exclusive OR. The exclusive OR of the
source field and the Auxiliary Register is
stored in the destination. If both Sand Dare
registers, R/L specifies a right rotate of the
source (S) data before the XOR operation.
Otherwise R/L is implicit and specifies the
length of the source andlor destination
IVIWS fields. Sand AUX are unaffected
unless specified as a destination.

BINARY REPRESENTATION
OCTAL REPRESENTATION

I

o

1

2

3

4

5

6

7

0

1

1

1

0

0

1

1

Example

I

!!!!!

Replace the selected IV byte field with the
XOR of the field and AUX. The IV byte field is
called STATUS and is 5 bits in length and
located in bits 3, 4, 5, 6 and 7 of LB.

00010011

SELECTED IV BYTE-BEFORE OPERATION

SELECTED FIELD RIGHT-JUSTIFIED WITH LEADING ZEROS ADDED

XOR OPERATION
AUX

00011001

I

--0

1

1

!J !!J
1

1

0

0

1

I

SELECTED IV BYTE-AFTER OPERATION

UNAFFECTED

Figure 6

168

Smnotics

UNDERSTANDING THE 8X300 INSTRUCTION SET

MP3
8X300 MICROPROCESSOR APPLICATIONS MEMO

XEC I{S) or XEC I{S,L)

XEC 1(0)

Format:
o

1

2

11

0

0

3

4

1

5

6

7

8

9

10

11

12

13

14

15

I Field

Source

Type III

BINARY REPRESENTATION
OCTAL REPRESENTATION

o

1

2

11

0

0

3

4

1

5

6

7

8

Source

9

10

11

12

13

14

15

I Field

R L

I

Type IV

13
0

0

0

0

1

1

0

1

1

01234567

10

Operation

1

0

1

1

0

I

Description

I

0

1

1

I

ADDRESS REGISTER-BEFORE OPERATION

SELECTED IV BYTE

00000011

SELECTED FIELD RIGHT JUSTIFIED WITH LEADING ZEROS ADDED

00010100

I FIELD

o

Example

o

\\\

Execute instruction at the address specified
by the Address Register with lower 5 or 8
bits replaced by (S) + I.

Execute the instruction at the address determined by replacing the low order bits of
the Address Register (AR) with the low
order bits of the sum of the literal I and the
contents of the source field. If S is a register,
the low order 8 bits of AR are replaced; if Sis
an IV or Working Storage field, the low order
5 bits of AR are replaced, resulting in an
execute range of 256 and 32 respectively.
The Program Counter is not affected unless
the instruction executed is a JMP or NZT
(whose branch is taken).

1

0

0

0

1

0

1

1

1

~<;:

0000110110111

ADDRESS REGISTER-AFTER OPERATION

-.,UNAFFECTED

ADDRESS

INSTRUCTION

0000110110011
0000110110100

XEC *+1 (INTERPT)
JMPAl

0000110110111

JMPA4

0000110111011

JMPA8

•
••
•••

JMP A4 IS EXECUTED BECAUSE IV FIELD INTERPT

Execute one of n JMPs in a table of JMP
instructions determined by the value of the
selected IV byte field. The table follows
immediately after the XEC instruction and
the IV field is called INTERPT and is a 3-bit
field located in bits 4, 5 and 6.

I

JMP TABLE

=3

Figure 7

XMIT I,D

XMIT I,D or XMIT I,D,L
Format:
0

1

2

11

1

01

3

4

5

6

7

8

9

10

Destination

11

12

13

14

15

13

14

15

I Field

1

Type III
BINARY REPRESENTATION

0
11

1
1

2
0

3

I

4

5

6

Destination

7

8

I

9

10

11

12

OCTAL REPRESENTATION
R L

Destination

Type IV

Operation:

I~ (D)

Description
Transmit literal. The literal field I is stored in
D. If 0 is a register, an 8-bit field is transferred; if 0 is an IV orWorking Storage field,
up to a 5-bit field is transferred.

o

1

1

1 0

234
0

1

5

6

7

0

0

1

I

00000110

///
1

1

0

1

1

0

0

1

SELECTED WS BYTE-BEFORE OPERATION

I FIELD

I

SELECTED WS BYTE-AFTER OPERATION

UNAFFECTED

Example
Store the bit pattern 110 in the selected
Working Storage field. The field name is
VALUE and is located in bits 3, 4 and 5.

Figure 8

!ii!ln~tiC!i

169

MP3

UNDERSTANDING THE 8X300 INSTRUCTION SET

8X300 MICROPROCESSOR APPLICATIONS MEMO

NZTS,I

NZT 5,1

Format:
o

1

2

11

0

11

3

4

5

6

7

8

9
R

Source

10

11

12

13

14

15

14

15

I Field

L

Type III
BINARY REPRESENTATION

o

11

1

0

2

3

4

5

6

7

8

9

10

11

12

13

OCTAL REPRESENTATION

11

I Field

Source

Type IV
01234567

Operation
Non-Zero Transfer. If (S) f 0, PC offset by 1PC; otherwise PC + 1 -+ PC.

I

x x

X

1

X

X

X

x

I

SELECTED IV BYTE
OIiERFLO

Description
If the data specified by the S field is nonzero, replace the low order bits of the Program Counter with I. Otherwise, processing
continues with the next instruction in sequence. If S is a register, the low order 8 bits
of the PC are replaced; if S is an IV or
Worki ng Storage field, the low order 5 bits of
the PC are replaced, resulting in an NZT
range of 256 and 32 respectively.

ADDRESS

INSTRUCTION

••
•
0000110110011
•
••

NZT OVERFLO, ALPHA

0000110111010

ALPHA

INSTRUCTION

OFFSET

Example

Figure 9

Jump to Program Address ALPHA if the
selected IV byte field is non-zero. The field
name is OVERFLO and it is a 1-bit field
located in bit 3.

JMPA

JMPA
ALPHA

Format: Type V
o

1

2

11

1

11

3

4

5

6

Operation: A
Description

7

8

9

10

11

12

13

14

\

15

A Field

-+

0000101110001

BINARY REPRESENTATION

o

OCTAL REPRESENTATION

I
I

I

I

6

I

1

I

PC

The literal value A is placed in the Program
Counter and Address Register, and processing continues at location A. A has a
range of 0-177778 in current systems (0-

ADDRESS

••
••
•
0000101110001

0000000011011

8191).

Example

INSTRUCTION

•

ALPHA

JMP ALPHA

INSTRUCTION

Jump to location ALPHA (0000101110001)

1 0 1 0 1 0 1 0 1 0 1 01 0 1 0 11 11 1 0 11 11

1 01 0

10

10

1

PROGRAM COUNTER BEFORE OPERATION

11 1011 11 11 101 01011 1 PROGRAM COUNTER AFTER OPERATION

Figure 10

170

!ii!)DotiC!i

SPI

8X300 CROSS ASSEMBLY PROGRAM (MCCAP)

8X300 MICROPROCESSOR APPLICATIONS MEMO

DESCRIPTION
The 8X300 Cross Assembly Program,
MCCAP, provides a programming language
which allows the user to write programs for
the 8X300 in symbolic terms. MCCAPtranslates the user's symbolic instructions into
machine-oriented binary instructions. For
example, the jump instruction, ~MP, to a
user defined position, say ALPHA, in program storage is coded as:
JMP ALPHA

and is translated by MCCAP into the following 16-bit word (see Figure 1).
JMPALPHA
o

15

111111101011111010101111101010111

~

I

~i (EXAMPLE)

I

LOCATION
OF ALPHA

n

>

OP CODE FOR JMP

Figure 1
MCCAP allocates the 8X300 program storage and assigns Interface Vector and Working Storage address to symbols as declared
in the user's program.
The ability to define data of the Interface
Vector as symbolic variables is a powerful
feature of MCCAP. Interface Vector variables may be operated on directly using the
same instructions as those for variables in
Working Storage and for the working registers.
The Assembler Declaration statements of
MCCAP allow the programmer to define
symbolic variable names for data elements
tai lored to his appl ication. I nd ividual bits
and sequences of bits in Working Storage
and on the I nterface Vector may be named
and operated upon directly by 8X300 instructions.
In addition to simplifying the language and
bookkeeping of the program, MCCAP provides program segmentation and communication between segments; i.e., the main
program and any subprograms. If a sequence of code appears more than once in
a program, it can be written as a separate
program segment, a subprogram, and
called into execution whenever that subprogram's function is required. Program segmentation also permits the construction of a
program in logically discrete units. These
segments need not be written sequentially
or even by the same person. The various
program segments provide a function description, or block diagram, of the application. Communication between segments
means that control and data can be transferred in both directions. MCCAP automati-

MCCAPSOURCEPROGRAM
MICROCONTROLLER SYMBOLIC ASSEMBLER VER 1.0
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715

01544

PROC

RDCMMD

01544
01545
01546
01547
01550
01551
01552
01553
01554
01555
01556
01557
01560
01561
01562
01563
01564
01565
01566
01567
01570
01571
01572
01573
01574
01575
01576
01577

6 07003
6 20101
6 07002
o 27305
o 24306
o 21202
6 07003
6 25100
6 20100
6 27101
6 07001
5 26117
6 07003
6 27100
607001
426123
6 07003
6 20101
6 07002
o 27704
o 27503
6 07003
6 27101
6 20100
607001
5 26135
6 07003
6 27100

SEL
XMIT
SEL
MOVE
MOVE
MOVE
SEL
XMIT
XMIT
XMIT
SEL
NZT
SEL
XMIT
SEL
XEC
SEL
XMIT
SEL
MOVE
MOVE
SEL
XMIT
XMIT
SEL
NZT
SEL
XMIT

IVRESP
UR. BCTRL
IVDATA
FUNC. R5
DADDR. R6
BUFF. R2
IVRESP
O. DONE
UW, BCTRL
1, XFR
IVCTRL
CMMD,"
IVRESP
0, XFR
IVCTRL
"(CMMD), 2
IVRESP
UR, BCTRL
IVDATA
TRACK, R4
SECT, R3
IVRESP
1, XFR
UW, BCTRL
IVCTRL
CMMD,"
IVRESP
0, XFR

01600

7 01652

RTN
END

RDCMMD

FOC RESPONSE 8YTE
ESTA8LiSH USER READ ONLY
HOLDS COMMAND BYTE
FUNCTION CODE
DISK ADDRESS
BUFFER FUNCTION CODE
SHOW COMMAND IN PROGRESS
RESTORE USER WRITE
SIGNAL USER FDC ACCEPTED BYTE
USER CONTROL BYTE
WAIT FOR CMMD TO GO LOW
FDC RESPONSE BYTE
LOWER XFR SIGNAL
USER CTRL BYTE
WAIT FOR NEXT COMMAND SIGNAL
SECOND COMMAND BYTE AVAILABLE
SET IVDATA TO USER READ ONLY
2ND COMMAND BYTE
TRACK ADDRESS
SECTOR ADDRESS
FDC RESPONSE BYTE
SIGNAL USER
RESTORE USER WRITE
WAIT FOR CMMD TO GO LOW
FDC RESPONSE BYTE
LOWER XFR SIGNAL
RETURN

Figure 2
cally generates the code for subprogram
entry and exit mechanisms when the appropriate CALL and RTN statements are
invoked.

MCCAP OUTPUT
The output from a MCCAP compilation
includes an assembler listing and an object
module. During pass two of the assembly
process, a program listing is produced. The
listing displays all information pertaining to
the assembled program. This includes the
assembled octal instructions, the user's
original source code and error messages.
The listing may be used as a documentation
tool through the inclusion of comments and
remarks which describe the function of a
particular program segment. The main purpose of the listing, however, is to convey all
pertinent information about the assembled
program, i.e., the memory addresses and
their contents.
The object module is also produced during
pass tWQ. This is a machine-readable computer output produced on paper tape. The
output module contains the specifications
necessary for loading the memory of the
Microcontroller Simulator (MCSIM), for
loading the memory of the SMS ROM Simulator, or for producing ROMs or PROMs.
The object module can be produced in
MCSIM, ROM Simulator or BNPF format.
An example of a MCCAP source program is
shown in Figure 2.

S!!I0otiCS

PROGRAM STRUCTURE
Program Segments
A MCCAP program consists of one or more
program segments. Program segments are
the logically discrete units, such as the main
program and subprograms, which comprise
a user's complete program. Program segments consist of sequences of program
statements. The first program segment
must be the main program. The main program names the overall program and is
where execution begins. All other segments
are subprograms; each subprogram must
be named. Control and data can be passed
in both directions between segments. No
segment may call itself, or one of its callers,
or the main program. Program segments
take the form as shown in Figure 3.
The Assembler Declaration statements define variables and constants. They must
precede the use of the declared variables
and constants in the Executable Statements
in a program. The Executable Statements
are those which result in the generation of
one or more executable machine instructions.

Subprograms
Subprograms are program segments which
perform a specific function. A major reason
for using subprograms is that they reduce
programming and debugging labor when a
specific function is required to be executed
at more than one point in a program. By

171

8X300 CROSS ASSEMBLY PROGRAM (MCCAP)

SPI
8X300 MICROPROCESSOR APPLICATIONS MEMO

PROGRAM SEGMENTS
PROGRAM STATEMENT
DECLARATION STATEMENT(S)

•••
••
•

EXECUTABLE STATEMENT(S)

SUBPROGRAMS
END STATEMENT

a. Main Program Form

PROCEDURE STATEMENT
DECLARATION STATEMENT(S)

•
•

•
•••

EXECUTABLE STATEMENT(S)

O.5f.1s :::; Entry Time:::; 4.0f.1s
O.5f.1s :::; Exit Time:::; 4.0f.1s

Details of the code required for procedure
CALL and RTN are provided in the Programming Examples section. See Figures
21 and 22.

Macros

END STATEMENT

b. Subprogram Form
Figure 3

creating the required function as a subprogram, the statements associated with that
function may be coded once and executed
at many different points in a program.
Figure 3 illustrates an example.
The program structure in Figure 3 causes
the code associated with PROC WAIT to be
executed three times within PROG MANYWAIT. This is accomplished even though
the statements associated with PROC WAIT
are coded only once, rather than three
times.

Subprogram Calls and Returns
For user-provided procedures, a jump to the
associated procedure and a return link are
created for each procedure reference. The
instructions to accomplish this result in
subprogram entry time. The instructions to
accomplish subprogram exit result in exit
time. The user may utilize the MCCAP
procedure mechanism for linking calling
programs with called programs or he may
create his own instructions to do so. The
following describes the linkage mechanism
and timing for MCCAP user procedures.
Linkage between called and calling programs is achieved through the generation of
an indexed "return jump" table, the length of
which corresponds to the number of different times in the program that the subprograms are called. This table is generated
automatically by MCCAP when procedure
CALL and RTN statements are invoked. For
each procedure reference, MCCAP creates
two statements in the calling program.
Thus, the time required for the subprogram
entry is 0.5 microseconds. The subprogram

172

return mechanism requires the execution of
two instructions or 0.5 microseconds.
These times do not include saving and
restoring of the working registers. The total
time to save all working registers is 3.5
microseconds, the same time to restore all
registers. Saving of all working registers is
normally not necessary, but worst case
calculations for entry and exit time below do
include this time. Thus, subprogram exit
and entry times are:

A macro is a sequence of instructions that
can be inserted in the assembly source text
by encoding a Single instruction. The macro
is defined only once and may then be invoked any number of times in the program.
This facility simplifies the coding of programs, reduces the chance of errors, and
makes programs easier to change.
A macro definition consists of a heading, a
body and a terminator. This definition must
precede any calion the macro. In MCCAP,
the heading consists of the MACRO statement which marks the beginning of the
macro and names it. The body of the macro
is made up of those MCCAP statements
which will be inserted into the source code
in place of the macro call. The terminator
consists of an ENDM statement which
marks the physical end of the macro definition.

MCCAP Statements
The MCGAP language consists of thirty
statements categorized as follows:
Assembler Directive Statements
Assembler Declaration Statements
Communication Statements
Macro Statements
Machine Statements

The following lists the statements in each
category, describes their use, and provides
examples. Detailed use of the instructions
including rules of syntax and parameter
restrictions are described in the MGGAp
Reference Manual.

ENTRY Statement
END Statement
ORG Statement
OBJ Statement
IF Statement
ENDIF Statement
LIST Statement
NLIST Statement
EJCT Statement
SPAC Statement

PROG Statement
Use
Defines the names and marks the beginning
of a main program.
Example: PROG PROCESS

PROC Statement
Use
Defines the names and marks the beginning
of a subprogram.
Example: PROC WAIT

ENTRY Statement
Use
Defines the name and marks the location of
a secondary entry point to a subprogram.
Example: ENTRY POINT 2

END Statement
Use
Terminates a program segment or a complete program.
Examples: END SUB1
END MAIN

ORG Statement
Use
Sets the prog ram counter to the val ue specified in the operand field.
Example: ORG 200

OBJ Statement
Use
To specify the format of the object module.
Examples: OBJ R
OBJ M
OBJ N
NOTE
"R" indicates the ROM Simulator format. "M" indicates the
Microcontroller Simulator format. "N" indicates BNPF format·

Assembler Directive Statements
Assembler Directive statements define
program structure and control the assembler outputs. They do not result in the generation of 8X300 executable code. There are
twelve Assembler Directive statements:
PROG Statement
PROC Statement

Si!lDOliCS

IF Statement
Use
To mark the beginning of a sequence of
code, which mayor may not be assembled
depending on the value of an expression.
Examples: IF VAL
IF X + Y

SPI

8X300 CROSS ASSEMBLY PROGRAM (MCCAP)

8X300 MICROPROCESSOR APPLICATIONS MEMO

ENDIF Statement

lIV Statement

Macro Statements

Use
To mark the end of sequence of code, which
is to be conditionally assembled. In the case
of nested IF statements, an ENDIF is paired
with the most recent IF.

Use
To define and assign symbolic names to
variables, usually IV bytes, located on the
left bank of the Interface Vector.

Macro statements provide the mechanism
for defining macros and for inserting them
into the source code. There are three Macro
statements:

Example: LITE LlV 23,2,1

Example: ENDIF
NOTE

II ST Statement
Use
To select and control output of a MCCAP
assembly.

The effect of the above example is to define a variable
whose name is LITE. It is located in a byte whose addresS is
23. The right-most bit of LITE is bit 2 and its length is 1 bit.

Example: LIST S,O,M,I

R IV Statement

NliST Statement

Use
To define and assign symbolic names to
variables, usually in Working Storage, located on the right bank of the Interface Vector.

Use
To suppress elements of the output from a
MCCAP assembly.
Example: NLiST O,M,I

EJCT Statement
Use
To cause the output listing to be advanced
to the next page.
Example: EJCT

SPAC Statement
Use
To insert blank lines into the output listing.
The number of lines inserted is indicated in
the operand field.

Example: DATA RIV 200,6,3
NOTE
The effect of the above example is to define a variable
whose name is DATA. It is located in a byte whose address
is 200. The right-most bit DATA is bit 6 of the byte and its
length is 3 bits.

Communication Statements
Communication statements are executable
statements which provide the mechanism
for main program to subprogram linkage.
They provide the means by which subprograms are called and returned from. There
are two kinds of Communication statements:
CALL Statement
RTN Statement

Assembler Declaration Statement

EQU Statement
SET Statement
LlV Statement
RIV Statement

EQU Statement
Use
To define a fixed constant.
Examples: FIVE EQU 5
ON EQU 1

MACRO Statement
Use
To mark the beginning of a macro definition. The MACRO statement forms the
heading of the macro definition.
E~mp~~

MAC1 MACRO
MAC2 MACRO A,B,C

NOTE
The second example would mark the beginning of a macro
called MAC2. The "A,B,C" represents a formal parameter
list. These parameters, used in writing the macro body, will
be replaced by the actual parameters listed in the MACRO
CALL statement.

ENDM Statement

Example: SPAC 3

Assembler Declaration statements define
and describe the data, constants and variables, in a program or subprogram. There
are four Assembler Declaration statements:

MACRO Statement
ENDM Statement
MACRO CALL Statement

Use
To mark the end of a macro definition. The
ENDM statement forms the terminator of
the macro definition.
Example: ENDM

MACRO CALL Statement
Use
To indicate where a macro is to be inserted
into the source code and to specify any
actual parameters needed by the macro.
Example: MAC2 DATA, INPUT, RESULT

CALL Statement
Use
To transfer control from a calling program
to the called subprogram. The CALL statement causes the generation of two 8X300
instructions.
Examples: CALL WAIT
CALL SINE
NOTE
The above are valid statements to be coded into the
program if WAIT and SINE have been defined in PROC
statements. The effect of invoking these statements is to
transfer execution control to the procedures WAIT and
SINE respectively.

SET Statement
RTN Statement

Use
To define and assign a value to a constant,
which may later be assigned a new value by
another SET statement.

Use
To transfer control from a called subprogram to a calling program.

Example: OFF SET 0

Example: RTN

S!!IDotiCS

NOTE
There is no single macro call statement. Any macro name
which has been defined as such may be coded as if it were a
valid MCCAP statement. The macro name is coded in the
operation field and the actual parameters are placed in the
operand field.

Machine Statement
Machine statements are the MCCAP symbolic representations of the 8X300 executable statements. Machine statements have a
one to one correspondence to 8X300 instructions. Each Machine statement results
in the generation of a single 8X300 ihstruction. There are eight Machine statements:
MOVE Statement
ADD Statement
AND Statement
XOR Statement
XMIT Statement
XEC Statement
NZT Statement
JMP Statement

173

SPI

8X300 CROSS ASSEMBLY PROGRAM (MCCAP)

8X300 MICROPROCESSOR APPLICATIONS MEMO

MOVE statement
Use
To copy the contents of a specified register,
WS variable or IV variable into a specified
register, WS or IV. Defihed in Instruction
Descri ptions.
Examples: MOVE R1 (6);R6
MOVE X,Y

or IV variable and the contents of the AUX
register, and place the result in a specified
register, WS variable or IV variable. In practice, the XOR statement is often used to
complement a value and to perform comparisons.
Examples: XOR R6,R11
XOR R1 (7),R4
XOR X,Y

NOTE
The first example illustrates a six place right rotate of Rl 's
data before it is moved to R6. The contents of Rl are neit
affected. The second example may be a Working Storage
or Interface Vector variable move. depending on the way X
and Yare defined in Declaration Statements.

ADO Statement
Use
To add the contents of a specified register,
WS variable, or IV variable to the contents of
the AUX register and place the result in a
specified register, WS variable or IV variable.
Examples: ADD R1 (3),R2
ADD DATA,OUTPUT
NOTE
The first example illustrates a three place right rotate of
Rl's data before the addition is carried out. Under certain
conditions a rotate may be used to multiply the specified
operand by a power of 2 before the additiOn is done. The
contents of I'll are nco affected. The second example
suggests that the contents of WS variable have been added
to the contents of the AUX register and the result placed in
an IV variable, making the result immediately available to
the user's system.

AN 0 Statement
Use
To compute the logical AND of the contents
of a specified register, WS variable or IV
variable and the contents of the AUX register. The logical result is placed in a specified
register, WS variable or IV variable. In actual
practice, the AND statement is often used to
mask out undesired bits of a register.
Examples: AND R2,R2
AND R3(1),R5
AND X,V
NOTE
The first example illustrates the use of an AND statement in
what might be a masking operation. If the AUX register
contains 00001111 then this statement sets the 4 high order
bits of R2 to 0 no matter what they were originally. The 4
loW order bits of R2 would be unaffected.

NOTE
The first example illustrates the use of an XOR statement in
what might be a complementing operation. If the AUX
register contains all 1's then the execution of this statement
results in the complement of the contents of R6 replacing
the contents of Rll. The second and third examples are of
the same form as the second and third examples of the
AND statement.

XOR Statement

174

In the first example, the execution of the program will
transferred to one of three labeled instructions on the basis
of whether register Rl contains 0, 1 or 2. In the second
example, the XEC statement causes the execution of a
statement which transmits a special bit pattern to the AUX
register in response to an input signal which is eitherO, 1,2
or 3. After the pattern is transmitted, the execution of the
program continues with the next instruction after the XEC.

NZT Statement
Use
To carry out a conditional branch on the
basis of whether or not a register, WS variable, or IV variable is zero or non-zero.
Examples: NZT R1 ,*+2
NZT SIGN,NEG
NOTE

XMIT Statement
Use
To transmit or load literal values into registers, WS variables or IV variables.
Examples: XMIT
XMIT
XMIT
XMIT
XMIT

DATA,IVR
OUTPUT,IVL
-11 ,AUX
-00001011 B,AUX
-13H,AUX

NOTE
The first example selects a previously declared WS variable
by transmitting its address to the IVR register. The second
example selects a previously declared IV variable by transmitting its address to the IVL register. The last three
examples all result in the generation of the same machine
code. They all load the AUX register with -11 ,0 , In the first
case, the programmer has written the number in base 10. In
the second case, the programmer has written the number
in binary and has indicated this by placing a B after the
number. In the third case, the number has been written in
octal as indicated by an H after the number.

In the first example, if the contents of Rl are non-zero, then
program execution will continue with the instruction,
whose address is the sum of the address of the NZT
statement and 2. If the contents of Rl are 0, the program
execution continues with the next instruction after the NZT
statement. In the second example, if the contents of a WS
or IV variable called SIGN is non-zero, then program
execution will continue beginning with the instruction
whose address is NEG. Otherwise execution continues
with the next instruction after the NZT statement.

JMP Statement
Use
To transfer execution of the program to the
statement whose address is the operand of
the JMP statement.
Examples: JMP START
JMP *-2
NOTE
In the first example, execution of the program continues
sequentially beginning with the instruction labeled
START. In the second example, program execution continues beginning with the instruction whose address is the
JMP instruction's address minus 2.

XEC Statement
Use
To select and execute one instruction out of
a list of instructions in program memory as
determined by the value of a data variable,
and then continue the sequential execution
of the program beginning with the statement immediately fol/owing the XEC unless
the selected instruction is a JMP or NZT
statement.

JTABLE

XEC JTABLE(R1),3
JMP GR8ERTHAN
JMP LESSTHAN
JMP EQUALTO
XEC SEND(INPUT),4
"NEXT INSTRUCTION"
"NEXT INSTRUCTION"

SEND

SEL Statement
Use
Select a variable in Working Storage or on
the Interface Vector, so that subsequent
machine instructions may reference that
variable.
Examples: SEL DATA
SEL OUTPUT
NOTE

Examples:

The second example illustrates a one place rotate to the
right of R3's data before the AND is carried out. The
contents of R3 are not affected. In the third example, X and
Y may be parts of the same WS or IV byte, or one may be a
WS byte and the other an IV byte.

Use
To compute the logical exclusive OR of the
contents of a specified register, WS variable

NOTE

XMIT
XMIT
XMIT
XMIT

11011011B,AUX
11111111B,AUX
10101010B,AUX
OOOOOOOOB,AUX

Si!Jnntics

It is the programmer's responsibility to assure that the
proper page has been addressed before calling the SEL
statement if the variable may be in Working Storage. The
SEL statement causes a single instruction, XMIT, to be
assembled into the user program. The operand of the XMIT
instruction is the byte address of the named variable
(argument of the reference) as it has been allocated in
Working Storage or on the Interface Vector.·

PROGRAMMING EXAMPLES
This section contains programming examples which demonstrate how the 8X300's
instructions can be assembled to perform
some simple, commonly required functions.
These examples are written as program

8X300 CROSS ASSEMBLY PROGRAM (MCCAP)

SPI
aX300 MICROPROCESSOR APPLICATIONS MEMO

fragments. They are not complete programs
as the Data Declaration and Directive statements have been omitted. Otherwise, they
follow standard MCCAP conventions.

Looping
Looping is terminated by incrementing a
counter and testing for zero. Register R1 is
, used as counter register and is loaded with a
negative number so that the program
counts up to zero. Figure 4 illustrates the
process.
LOOPING
XMIT
ALPHA

NEG,R1
Load negative loop count.

•••
•
••

1,AUX
Store increment value in AUX register
which is an implicit operand of ADD
instruction.
R1,R1
Increment counter register. Add contents of AUX to contents of R 1 and
store the sum in R 1.
R1,AlPHA
Test contents of R1 for zero. If zero,

ADD

NZT

execute next sequential instruction,

otherwise, jump to ALPHA and continue execution from there.

••

a-BIT SUBTRACT
XMIT
XOR
XMIT
ADD
ADD
TIME: 1.25

-1,AUX
Perform 2's complement, R2.
R2,R3
1,AUX
R3,AUX
2's complement of R2 is now in AUX.
R1,R3
R1·R2 is now in R3.
microseconds

•

16-Bit ADD, Register
to Register
Add a 16-bit value stored in R1 and R2 to a
16-bit value in R3 and R4. Store the result in
R1 and R2.

MOVE

R2,AUX

ADD

R4,R2

MOVE

R1,AUX

result.

Figure

Inclusive-OR (a Bits)
Generate inclusive-OR of the contents of R1
and R2. Store the logical result in R3. Although the 8X300 does not have an OR
instruction, it can be quickly implemented
by making use of the fact that (A + B) + (A
B) is logically equivalent to A Ef) B.
INCLUSIVE-OR

AND
XOR

TIME

R2,AUX

load one of the operands into AUX
register so that it can be used as the
implicit operand of XOR and AND
instructions.
R 1 ,R3
Take exclusive OR of AUX and R 1
Store resu It in R 3.
R 1 ,AUX
Take AND of AUX and R 1. Place results in AUX.
R3,R3
Take exclusive OR of AUX IA . 8) and
R3 (A + B). Store result'" R3. R3 now
contains inclusIve OR of R 1 and R2.
1.0 microseconds

Figure 5

Two's Complement (a-Bits)

16,;.BIT ADD, MEMORY TO MEMORY
l2,IVR

MOVE
XMIT

l2,AUX
l1,IVR

ADD

l1,l1

MOVE

OVF,AUX

XMIT

H2,IVR

ADD
XMIT
ADD

H2,AUX
H1,IVR
H1,H1

Transmit address of low order byte of
second operand to IVR.
Move low order byte to AUX.
Transmit address of low order byte of
first operand to IVR.
Add low order bytes and store result in
l1.
Move possible carry from addition of
low order bytes to AUX register.
Add high order byte of second operand to possible carry. Store result in
AUX.

Figure 9

a-Bit Subtract
Subtract the contents of R2 from the contents of R1 by taking the two's complement

XMIT

0,R1

XMIT
XMIT

8,R2
INPADR,IVl

NEXT BIT NZT STROBE:+2

JMP
MOVE
XOR

*-1
INPBIT,AUX
R1(1),R1

XMIT
ADD

-1,AUX
R2,R2

R1 will be used as a character
buffer. It has been cleared.
R2 will be used as a bit counter.
Select IV Byte that contains
INPBIT and STROBE.
Test STROBE for data ready.
The MOVE instruction is executed only when STROBE c 1.
loop until STROBE c 1.
Rotate R 1 one pla<.e right. This
puts a zero in the least signifi~
cant bit pOSition. Then take the
exclusive OR of this rotated
version of R1 and of AUX. Place
the result in R 1. The least significant bit of R 1 will now equal
the latest value of INPBIT.

Decrement R2.
If R 2 is not yet zero, then more
bits must be collected to complete the byte being assembled.
R1(1),R1
This instruction will only be
MOVE
executed when 8 bits have been
COllected. Afterthis is done, it is
still necessary to rotate one
more time to get the last INPBIT into the high order bit position of R1.
TIME: 1.8 microseconds per bit (minimum)

Figure 11
XMIT

TWO'S COMPLEMENT

Figure 6

BYTE ASSEMBLY PROGRAM

16-Bit ADD, Memory to Memory
Add a 16-bit value in Working Storage,
OPERAND1, to a 16-bit value in Working
Storage, OPERAND2, and store result in
Working Storage OPERAND1, H1 and L 1
represent the high and low order of bytes
OPERAND1. H2 and L2 represent the high
and low order bytes of OPERAND2,

High order byte of sum is in H1. low
order byte of sum is in l1.
TIME: 2.25 microseconds

for XOR.
now in R3.
for ADD.
now in R3.

Figure 10

a

Generate the two's complement of the contents of R2_ Store the result in R3. Assume
that R2 does not contain 200 8 ,

XMIT
-1,AUX
load AUX in preparation
XOR
R2,R3
1 's complement of R2 is
XMIT
1,AUX
load AUX in preparation
ADD
R3,R3
2's complement of R2 is
TIME: 1.0 microseconds

IV BYTE ADDRESS, INPADR

Move low order byte of first operand
to AUX in preparation for ADD.
Add the low order bytes of the two
operands and store the result in R2.
R2 contains the low order byte of the

Move high order byte of first operand
to AUX.
ADD
OVF,AUX
Add in possible carry from addition of
low order bytes.
ADD
R3,R 1
Add the high order bytes plus carry
and place result in R 1. R 1 contains the
high order byte of the result.
TIME: 1.25 microseconds

Figure 4

XOR

BYTE ASSEMBLY

Figure 7

TIME: 750 nanoseconds

MOVE

named STROBE is used to define bit timing,
and a second bit, named INPBIT, is used as
the bit data interface, Figure 10 illustrates
the byte assembly,

16-BIT ADD, REGISTER TO REGISTER

loop start.

XMIT

of R2 and adding R1. Store the difference in
R3.

Byte Assembly From Bit
Serial Input
This is typical of problems associated with
interfacing to serial communications lines,
An 8-bit byte is assembled from bit inputs
that arrive sequentially at the Interface Vector. A single bit on the Interface Vector

G!!I0otiCG

Rotate Left
The 8X300 has no instructions which explicitly rotate data to the left. Such an instruction would be redundant because of the
circular nature of the rotate operation, For
example, a rotate of two places to the left is
identical to a rotate of six places to the right.
The rotate n places to the left in an 8-bit
register, rotate 8-n places to the right. This
example illustrates a rotate of the contents
of R4 three places to the left.
MOVE R4(5),R4
TIME: 250 nanoseconds

Three Way Compare
The contents of R1 are compared to the
contents of R2, A branch is taken to one of
three points in the program depending upon
whether R1 = R2, R1 < R2, or R1 > R2,

175

8X300 CROSS ASSEMBLY PROGRAM (MCCAP)

SPI
8X300 MICROPROCESSOR APPLICATIONS MEMO

THREE WAY COMPARE

INTERRUPT POLLING PROGRAM

RESULT

,-__________

~A~

__________

SIGN

XMIT

CONTROL,IVL

Choose proper IV Byte
by transmitting its address to IVL register.
(CONTROL),S Execute the one instruction whose address is the sum of
JTABLE and the contents of CONTROL. The
S indicates the length of
the table_

XEC

JTABLE

~

,

II I I I I I I I
WORKING STORAGE BYTE

JMP

ALPHA1

JMP
RESULT,IVR

XMIT

-1,AUX

XOR

R2,RESULT

XMIT
ADD

1,AUX
RESULT,AUX

ADD
NZT
JMP
NEQUAL
GREATER

EQUAL

Choose a working Storage byte
by transmitting its address to
IVR register,
Load AUX with all 1's, in preparation for complementing contents of R2.
Store complement of R2 in RESULT,

AUX now contains 2's complement of R2.
RESULT now contains R 1-R2.
R1,RESULT
RESULT,NEQUAL If RESULT I' 0, then R1 I'R2.
EQUAL
Sign Bit = 1 only when R1 < R2.
NZT SIGN,LESS

Continue

•
••
•••

Continue

LESS
Continue
TIME: 2.0l)1icroseconds

••
•

FROM USER SYSTEM

~M
U

Table of S instructions,
one of which is executed as a result ofthe XEC
instruction above.

THREE WAY COMPARE PROGRAM
XMIT

~S
U

••
•

Figure 12
JTABLE

CONTROL SEQUENCE #1

TO USER SYSTEM

ALPHA2
IV BYTES

JMP
ALPHAS
TIME: 750 nanoseconds.

Figure 18

Figure 15

CONTROL SEQUENCE #1 PROGRAM

Bit Pattern Detection
In An I/O Field
Test input field called Input for specific bit
pattern, for example: 1 0 1 1, If pattern is
not found, branch to NFOUND, otherwise
continue sequential execution_ Figures 16
and 17 illustrate the procedure,

XMIT

STATUS,IVL

NZT

STATUS,'+2

Choose input IV byte by transmitting its address to IVL.
Test input bit to determine
whether it is still zero. Skip next
instruction if it is not zero.
'-1
JMP
Jump to previous instruction.
XMIT
ALARM,IVL
Choose output IV byte.
1,ALARM
Set output bit by loading ALARM
XMIT
with 1.
TIME: 1.0 microseconds (minimum)

Figure 19

Figure 13
BIT PATTERN DETECTION

Control Sequence #2
Output a specific 5-bit pattern in response
to a specified 3-bit input field.

Interrupt Polling

~}

Three external interrupt signals are connected to three IV bits_ The three bits are
scanned by the program to determine the
presence of an interrupt request. A branch
is taken to one of eight program locations
depending upon whether any or all of the
interrupt request signals are present. The IV
bits associated with the interrupt requests
are wired to the low order three bits of the IV
byte named Control. Figures 14 and 15
illustrate the interrupt polling_

~

DATA FROM

~

USER SYSTEM

Subprogram Calls and
Returns
IV BYTE

Figure 16
BIT PATTERN DETECTION PROGRAM

INTERRUPT POLLING

~}

INPUT,IVL

XMIT

1011 B,AUX

XOR

INPUT,AUX

NZT

AUX,NFOUND

• •
•• ••

~

CONTROL (

XMITI

NFOUND Continue
TIME: 1.0 microseconds

Choose proper IV Byte by transmitting its address to IVL register.
Store desired bit pattern in AUX
register for use as implicit operand of XOR instruction.
Take exclusive OR of the contents of INPUT and AUX. Store
the result in AUX. Now the contents of AUX will be zero if the
contents of INPUT are 1011.
Test AUX for zero. Branch to
NFOUND if non-zero.

Figure 17

INTERRUPT SIGNALS
FROM USER SYSTEM

~
IV BYTE

Figure 14

176

Control Sequence #1
Set an output bit when an input bit goes high
(isset) (see Figure 18).

!ii!)DotiC!i

The mechanism for managing subprogram
calls and returns is based on assigning a
return link value to each subprogram caller;
this return link value is then used, on exit
from the subprogram, to index into the
return jump table which returns control to
the callers of the subprogram. Figure 21 is
an example of a subprogram called from
four different locations in the main program.
As seen from Figure 21, each subprogram
(or procedure) caller is assigned a "tag" or
index values ranging from Ot03, ora total of
four index values for the four callers. Before
jumping to the subprogram, the index value
is placed in a previously agreed upon location, register R11 in this case. Upon exit
from the subroutine, the index value stored
in R11 is used as an offset to the Program
Counter in order to execute the proper JMP
instruction. The key to returning to the
proper caller is the index jump table. Figure
22 gives a detailed description of the return
operation.

8X300 CROSS ASSEMBLY PROGRAM (MCCAP)

SPI
8X300 MICROPROCESSOR APPLICATIONS MEMO

CONTROL SEQUENCE #2 PROGRAM

PATTERN

XMIT
MOVE

STATUS,IVL
STATUS,R1

XMIT
XEC
JMP
XMIT
XMIT
XMIT

ALARM,IVL
PATTERN(R1 ),8
*+9
A,ALARM
B,ALARM
C,ALARM

•
••
•
••

•
••
••
•

XMIT

H,ALARM

TIME: 1.25 microseconds.

~ETURN
Address n

XEC*+1

Address n+1
Address n+2

JMP A
JMP 8

Address n+3
Address n+4

JMP C
JMP D

Choose the IV byte which receives the 3-bit input from user's system.
Move the 3 bits of interest from the IV byte to register R1. The 3 bits are automatically right justified.
Choose the IV byte through which the response is sent to the user's system.
Select specific pattern from PATTERN table.

Transmit proper pattern to output IV bytesubfield by executing just one
of these eight instructions. A through H represent the names associated
with eight different control bit patterns.

Figure 20

OPERATION

This instruction results in the execution of the instruction located at the
current value of the Program counter
p plus 1 plus the contents of R 11,
which is the caller index value.

SUBPROGRAM CALL
Program

Storage
Address
000137,
000140,
000141,

Jump to start of subprogram.

Next Instruction

••
•
•

The JMP table follows in consecutive
Program Storage locations following
SEC.

Figure 21

Instruction
Load AUX with OCaller # 1

XMIT 0, R11
JMP SUBR

001133,
001134,
001135.

XMIT 1, R11
JMP SUBR
Next Instruction

Load AUX with 1 Caller # 2
Jump to start of subprogram.

003260,
003261,
003262,

XMIT 2, R11
JMP SUBR

Load AUX with 2 Caller # 3
Jump to start of subprogram

003654,
003655,
003656,

XMIT 3, R11
JMP SUBR
Next Instruction

SUBR

a. Main Program
Machine Instructions
JMP TABL

•
•• •

Next Instruction

••
••

Load AUX with 3Caller #4
Jump to start of subprogram

••
••
•

•••
Subroutine
Return

Code
TABL

XEC

*+1 (R1 1)

JMP
JMP
JMP
JMP

000141,
001135,
003262,
003656,

Execute JMP located at
current PC + 1 + (R1 1).
Return to Caller #1
Return to Caller #2
Return to Caller #3
Return to Caller #4

b. Subroutine

Figure 22

!ii!)DotiC!i

177

8X300

A FAST MICROPROCESSOR FOR CONTROL APPLICATIONS
ABSTRACT
Many possible applications for microprocessors demand a very quick response to
requests for action or information. While
MOS microprocessors are relatively cheap,
they do not generally possess the necessary
speed. Although bipolar microprocessors
tend to possess greater speed, they are
mostly designed as general purpose devices, which means that they are not ideally
suited to the requirements of a fast real-time
microcomputer system. The Signetics
8X300 microprocessor has been specifically
designed to fulfill this role. This article
describes the architecture and instruction
set of the 8X300 and, by the use of examples,
explains the capabilities and applications of
the device.

MICROPHOTOGRAPH OF THE 8X300 CHIP

fll9

Considerably improved data throughout is
obtained from the use of separate data and
address buses for the program memory,
coupled with extremely flexible I/O control.
Data may be input, modified and output all
in the same instruction by the use of the two
independent, parallel I/O ports.

INTRODUCTION
As semiconductor technology improved,
allowing greater die area with economically
acceptable yield, the amount of logic that
could be put on a marketable integrated
circuit increased. It naturc;llly followed that
rather than provide more individual elementary gates on a single die, these gates would
be interconnected to afford the user of these
chips more complicated logic functions in a
single package. The attractiveness of the
more complex integrated circuits compelled semiconductor manufacturers to
strive for increasing circuit density.
The prospect of putting an entire, although
elementary, computer CPU on a single die
focused attention on those fabrication
processes which allowed the greatest
densities. Therefore, the MOS process was
the first to yield an entire microprocessor on
a chip. Unfortunately, a price was paid in
that the MOS processes did not produce as
high a speed of logic element as the usual
bipolar processes. Because of density
limitations, the bipolar process could only
produce the less dense parts of chip
microprocessors-the bit slices.
Now, however, the improvements in bipolar
technology permit the construction of
single chip microprocessors with all of the
performance advantages of bipolar Schottky technology. Such a circuit has been
fabricated and is being produced with
significantly high yield to allow commercial
availability of quantity parts. The product is
the 8X300 microprocessor produced by
Signetics. It is the purpose of this paper to

178

Figure 1
present the 8X300 by discussing the architecture and some of the key fabrication and
technology features of the microprocessor.
This paper concludes with a brief review of
some of the present as well as potential
applications of this device.
The 8X300 was optimized for control
applications rather than for extensive numerical processing, so before the main
presentation begins, it is advisable to
describe the basic requirements in the
envisaged application field of the 8X300.
Control here applies to a wide variety of
areas and is not necessarily limited to those
specific areas itemized below. The action of
control may be the sole purpose of a standalone microprocessor. In such a task, the
microprocessor examines statuses at a
particular rate and issues command words
or bits to the external circuitry to effect the
function of the whole machine as it is
described in the control program. Thus, the
microprocessor selects specific bits defined
by the program, tests the bits, and responds
or directs by setting or clearing other bits.
Although elementary on the surface, this
task may be quite complex involving timing,
interval measurement, and various forms of

S!!IDotiCS

decision making, all at potentially high
speed. Control may also take the form of bit
or word manipulation and data movement
such as in data concentrators, communication controllers, disk and tape controllers
and similar devices. Here the data destined
for storage, transfer or transmission may
require alteration (for example bit packing,
preamble addition or error detection/correction); consequently the control also
involves calculation or data generation.
Consider an industrial metal cutter required
to form a complex shape as directed by
some external data input. Matrix multiplications may be a very necessary part of this
controller's process in order to carry out its
function.
Thus, we see that controllers in this context
may perform a wide variety of bit and
arithmetic processing depending upon the
type of controller one is discussing. The
8X300 is capable of good performance in all
of these control areas.

ARCHITECTURE
The architecture of a microprocessor is
intimately connected to the technology
used to produce the device, for one could

define architectures which are realizable
only with certain fabrication approaches.
Also, a microprocessor's architecture is
described by its instruction set and its
input/output structure. So, in this section,
the 8X300 will be examined both from the
inside-technology, block diagram, etc.,
and from the outside-instruction set, 1/0
bus, timing, etc.

One functional entity is the clock generator
circuit, which oscillates at a frequency
determined by an external crystal or timing
capacitor. This circuit generates all timing
signals required internally by the 8X300 and
externally for bus timing. Secondly, a
voltage regulator in combination with an
externally connected (user-provided) pass
transistor, provides a stable low voltage
source for the operation of selected internal
segments. This voltage is approximately 3
volts and is used in areas where power
conservation rather than speed is a prime
concern. (The 3 volts does not imply 12L
utilization.) Maximum current used is
450mA (300mA typical) with 150mA used in
the 5 volt (V CC) connection and 300mA
used in the 3 volt (V CR).

The 8X300 is fabricated using standard
Schottky technology. Dual layer metallization is used to minimize die area, reduce
capacitance and hence maximize the speed
of the processor. A microphotograph of the
8X300 die is shown in Figure 1. The die
measures 250 mils square and is the largest
bipolar microprocessor in existence. The
8X300 is a complete processor on a single
chip and, as will be seen later, results in a
minimum circuit count processor system.
Linear elements are also provided on the die
as shown in Figure 2.

CLOCK AND POWER SUPPLY
REQUIREMENTS FOR THE 8X300
t5V

.IO.l

*,0.1
50
VR

VCR

c:::J

8X300

12

37

GND

Vee

-=• ICC (TVP)

With the regulator, the entire processor
operates from a single +5 volt supply over
the commercial temperature range (0 0 C to

= 300mA

Figure 2

SCHEMATIC ARCHITECTURE OF THE 8X300

...
I

I[
I

I

OVF

I

SHIFT

...

MERGE

F

1,\

I
7

0

R1
R2
R3
R4

/

R5
R6
Rll

vr==t=
-"'-

AUX

-

ALU

(/)

lJ.J

~
L __
K

(51

MASK

'"

0

~

RIGHT
ROTATE

V

-"'-

K.

'----

5
INTERNAL CONTROL
SIGNALS

-,

if

I

I
I

I

en

I

~

I
AR5-AR12

l

AR

I

l

1

{r
PC

J

r-.

r-

,..
~

h

l

I

It

LB

WC
~

~

I

IVBO-IVB7
IV BUS

RB
~

r-.

~

V
AO-A12
INSTRUCTION ADDRESS

...

r-

I
CONTROL

J-,.

---

DECODE
AND
CONTROL
LOGIC

L_

"'-

::::

h

ARO-AR4

12

0

v-"'i<...

r-

eI:

I

11

:r:

U
l-

"

SC
MCLK
HALT
RESET

,....

IRO-IR2

J

,....
....,

+5 •
GND •

10-115
INSTRUCTION DATA

VR-----VCR-·------

Figure 3

!ii!l0otiCii

179

+?O°C). The 8X300 is packaged in a 50-pin
dual-in-line ceramic package.
The block diagram of the 8X300 processor is
shown in Figure 3. It does not show the
circuitry just described. First, 110te that full
instruction decoding logic is provided to
interpret the instruction classes and perform the indicated operation. This will be
discussed in more detail later. This decoding and control logic provides all internai
signals required as well as certain control
lines for data input and output. These lines
are RB, LB, WC, SC and MCLK. External
control may be applied to hold the 8X300 in
a non-processing or wait state (via halt) or
force the processor to instruction address
zero (reset). The processor also contains its
own program counter (PC) which is automatically incremented upon instruction
execution or, in certain cases, is not incremented or is loaded with a new value. Current address control, provided by the address register (AR) may be derived all or in
part from the program counter, the instruction data (ARO-AR4) or from the output of
the ALU (AR5-AR12). Thus; the present and
future instruction to be executed may be
altered through instructions or the condition of selected data.

and is accompanied by the bus control
signals shown in Figure 4. Since the bus
carries addresses as well as data, I/O ports
must be enabled before data transfers may
take place. This is usually accomplished by
presenting an address on the bus under
program control. The control line SC is used
to indicate address content of the bus.
When presented with an address, an I/O
port either enables itself (becomes active on
the bus to accept or present data) if the
address presented is its own, or disables
itself (becomes inactive) if the address
presented does not match its own address.

+5V

q

•

-=-

PROGRAM STORAGE
AO-A12

A

VCC

VR

'i
10-115

l\

r

L

L

Xl

.-e--

SC

t-~

~

'-

-

-

r-r-

~~z t::J

L:.--.....
X2

HALT~
RESET

8T32

f-WC
MCLK
LB
RB

8X300
INTERPRETER

USER
CONNECTION

~

A IVBO-IVB7

VCR

'i
ROM/PROM/RAM
TTL COMPATIBLE
UP TO 8k x 16 BITS
(82S1151

•
•
•

...

fF~~

r-i~

1+

n
--

~

~

r1

1.

8T33

~

GND

....

ft•

!r'

BIC

•

Figure 4

INSTRUCTION EXECUTION SEQUENCE
AND LEFT BANK/RIGHT BANK ADDRESSING
OUTPUT PHASE

INPUT PHASE

f.ool.>----~---1
1
1
1

1

1

INST & IV BUS
DATA INPUT

:

1

MCLK

=LOW

- - - - - - -...1_ MCLK

1

DATA
PROCESSING

_1

I.

1

1

=HIGH ~

1
1

ADDR & IV
1
BUS DATA
1
VALID:

ADDR & IV
BUS
CHANGING

1-- '!. CYCLE --1-- '!. CYCLE - - I - '!. CYCLE

LB/RB

180

A unique feature of the 8X300 is the
partitioning of the bus into two banks,
designated left bank (LB) and right bank
(RB). Using the LB and RB signals from the
processor as master enables for the I/O
ports, the processor may dynamically select
ports as Figure 5 illustrates. Two I/O ports
may be active during one cycle provided
that they are on opposite banks. To do this,

TYPICAL SYSTEM CONFIGURATION
SHOWING USER INTERFACE

The processing part of the 8X300 is shown
in the upper half of Figure 3. The entire
processor is oriented about 8-bit data
manipulation; therefore interfaces to external circuitry use an 8-bit bus, designated the
Interface Vector (IV) bus (IVO-IV?). For
internal storage of data, eight 8"'bit read/
write registers are provided, designated R1R6, R11 and AUX (auxiliary). The auxiliary
register contains one of the operands that
are used in two operand instructions such
as ADD, AND and XOR (Exclusive-OR). A 1bit overflow register (OVF) is provided to
store the overflow resulting from add operations. The IV latch is not addressable, but
stores original data brought in from the IV
bus to be used in the merge operation prior
to output. At the heart of the processing is
the ALU which performs various arithmetic
and logic operations on data. The ALU,
when combined with the rotate, mask, shift
and merge elements, permits unique data
operations.
Before proceeding, it is essential that the IV
bus concept be explained. From this, we
shall go back and discuss the architecture
and instruction set in greater detail. The IV
bus serves both as an address and data bus

To effect input and output data transfer, the
8X300 IV outputs are three-state drivers.
Additionally, to control external devices, the
8X300 issues the write command, WC,
which indicates whether data transfers are
read (into the 8X300) or write (out of the
8X300). The bus direction is entirely under
control of the 8X300.

Together with this, processor I/O ports have
been designed which allow 1 of 512 interface vector bytes to be selected without
decoders. Having two ports, one forthe user
and the other to the microprocessor, these
IV bytes are completely bidirectional. The
unique feature of these bytes is the way in
which they are addressed.

Input/Output
Separate buses are provided for instruction
address and instruction data. the current
contents of the address register (AR) are
presented on a 13-bit bus (AO-A 12) to the
program memory to fetch the 16-bit instruction word. The 8X300 possesses the capability of directly addressing 8K of program
storage. The instruction word enters the
processor via the instruction bus (10-115)
and is stored in the instruction register (R).

Each IV byte has an 8-bit field programmable address, which is used to enable the
microprocessor port, allowing data transfer
through it.

1

1

- - 1 - '!. CYCLE --I

____x___________ ___________
~x

Figure 5

s~nDtiC!i

I/O ports recognize addresses, data or
controls only when enabled by the bank
signal to which they are connected. Clearly,
the bank partitioning may be considered as
a ninth address bit which is alterable by the
processor within an instruction. (The
8X300, therefore, has 512 direct I/O port
address capability.) A general data operation between two I/O ports could follow the
following steps. First, an address is presented to one bank enabling a selected I/O port
and disabling all others on that bank.
Secondly, another address is presented to
the opposite bank effecting a similar selection there. Subsequently, in one instruction
cycle, the 8X300 may accept data from one
port (on one bank), operate on the data and
deposit the result in the other port in the
second bank. If the working storage of the
registers is not sufficient, additional storage
can be added using an I/O port address to
add another 256X8 words of RAM . See
Figure 6.
In order to fully appreciate the speed of the
last operation, accepting data from one port
and depositing it on the other, it is necessary to explore the details of the instruction
cycle. Each 8X300 operation is executed in
one instruction cycle which is subdivided
into four quarter cycles. The quarter cycles
are shown in Figure 5. The instruction
address for an operation is presented at the
output during the third quarter of the
previous instruction cycle. With a memory
of sufficient speed, the instruction is returned and accepted by the processor
during the first quarter of the cycle in which
that instruction is to be executed. The
instruction is decoded and used to direct
the operation of the processor throughout
the cycle.
For data processing, the instruction cycle
may be viewed as having two halves. During
the fi rst half of the cycle, data to be
processed is brought into the processor and
stored in the IV latch. This is accomplished
during the first quarter cycle. The next
quarter cycle of this first half is used to bring
the data through the ALU, thereby processing the data as required by the instruction.
The second half cycle is the output phase
during which the data is presented to the IV
bus and finally clocked into the appropriate
I/O port after bus stabilization. The processor issues MCLK for this purpose.
Bank selection during input and output
phases is independent, thus data may be
input from the right bank and deposited in
the left bank or vice-versa, or to and from the
same bank if the same IV is used. Bank
selection during instruction cycle phases is
specified by the instruction. Therefore, the
processor may input data from one port,
operate on the data and return it to a second
port in one instruction cycle time. Remember that instruction fetching is concurrent
with data operations. The cycle time is
250ns, making the 8X300 comparable in

WORKING STORAGE (RAM) MAY BE
INCLUDED IN THE SYSTEM DESIGN

CONTROL
BUS

,''-

•

~

DATA
BUS

-!1/0
PORT 2
~

ADDR

..

PROGRAM
STORAGE
(PROM. ROM)

8X300
INST J\.

LB/- MCLK
lSI
W
R8L

...

H

---

~--""!-~----

..

....,.-- H

T

,

y

....

....

II

,-

LEFT BANK
DEVICES
RIGHT BANK
DEVICES

I/O
PORT 1

~

..

WORKING
STORAGE
(RAM)

Figure 6
speed on a microcycle basis, to bipolar slice
systems.

Instruction Set
The power of the 8X300 architecture is
embodied in the instruction set which
controls the ALU, rotate, mask, shift and
merge functions to provide for various data
operations. Each 16-bit instruction word is
subdivided into several fields. The arithmetic and logical instructions follow the format
shown in Figure 7. There are eight instruction classes each with variations depending
upon the operand specifications. These
instructions provide for:
Arithmetic and logic operationsAdd, And and XOR
Data movementMove and XMIT (transmit)
Context alterationJMP (unconditional jump), NZT (test and
branch on non-zero) and XEC (execute the
instruction at the address specified without
program counter alteration)

FORMAT OF ARITHMETIC AND
LOGIC INSTRUCTIONS
BIT
POSITION

0

1

2

3

7
SOURCE

8 10 11

II
L

15

DESTINATION

~'~--------~--------~
OP CODE

OPERAND(S) SPECIFICATION

L" LENGTH

Figure 7

Si!lDOliCS

The operand fields specify the sou rce of the
data as one of the internal registers or from
the IV bus as left bank or right bank, and the
destination of the data as one ofthe internal
registers, left bank or right bank or as left
bank or right bank addresses. Additionally,
these fields specify the length and position
of the data which is to be processed. As an
example, see Figure 8.
Before going through an example, some
features of this instruction should be
explained. The first 3 bits are used for the
op-code. The 5 source bits contain two
separate information groups: The first 2 bits
(3 and 4) define the actual source while the
next 3 bits (5, 6 and 7) define the least
significant bit of the variable length field of
the source. These are represented in the
diagram by two digits-the first modulo 4
and the second modulo 8. In the example
the first digit being 2 selects left bank I/O
(right bank = 3).
The length of the source data field is
specified by the length (bits 8,9 and 10). The
5 destination bits are represented by two
digits-the first modulo 4 and the second
modulo 8, as the source. In Figure 8, the
destination is an internal register, specified
by the first digit being 0 or 1. The actual
register is specified by the value of the
second digit. These operand fields control
the rotate, mask and shift operations as data
proceeds through the microprocessor.
Rather than go through the details of the
complete instruction set, it is more instructive to proceed with an example which will
serve to illustrate what may be done with a
single instruction. What shall be done in this

181

THE ADD OPERATION

TYPICAL INSTRUCTION
o

11
OP
CODE

T

T

SOURCE

LENGTH

15

"1

DESTINATION

•

SOURCE

•

Op Code: 0 (MOVE). 1 (ADD). 2 (AND). 3 (XOR)

•

Source: 20 -27. (Left bank). 30 - 37. (Right bank)

•

Length: 0 - 7 (L)

•

Dest.: 60 - 67•• 11 •• 17.

•

Action: Least Significant L bits of IV source data
are right justified and processed by the ALU. The 8bit result is deposited in the destination register.

AUX

I I I I I I I
aD

a,

I I I
x

x

a,

a,

x

x

a.

a,

bs

a,

a,

b.

I

b,

I

~
s,

s,

I a, I
"---.r--J

II

I

PREVIOUS VALUES OF
SOURCE DATA PRESERVED

SOURCE

1....----+-_ _---1

a,

~

x

I I I I I s, I
aD

a.

I I I I
I

DEST

as

DESTINATION

Figure 10
Figure 8
example is to select two 1/0 ports, add the
contents of the AUX register to a specified
segment of the source, merge the result with
the original data and deposit the result at the
destination.

ADD INSTRUCTION TO PERFORM
THE ADDITION SHOWN IN
FIGURE 10
OP CODE

Suppose the source of the data is in IV port,
address 5 on the left bank, and the destination address is contained in internal register
R3. Further suppose that the AUX register
already contains the required value to be
added. First, the 1/0 ports are selected:
XMIT 5, IVL (transmit the number 5 to the
bus as left bank address). MOVE R3,IVR
(move contents of R3 to the bus as a right
bank address). The 1/0 ports have now been
enabled using two instructions-500ns total
thus far. Now perform ADD LB, RB (add left
bank to AUX and deposit in right bank port).
The add instruction is shown in Figure 9
where the add operand fields specify the
selection of bits throughout rotate and
length (mask), and after addition specify the
position of merge (shift) in the original data.
Although the source, length and destination
fields shown here are unique to the MOVE,
ADD, AND and XOR instructions, the comments made about these fields also apply to
the fields of all the other instructions. Port 5
on the left bank is assumed to contain ao-a 7
(Figure 10) and the AUX register is assumed
to contain b o-b 7 . The source field specifies
selecting bits starting with a5 and the length
field specifies taking 3 bits to the left. Thus,
a5, a4 and a3 are masked off and right justified. Note that this requires that only contiguous bits be selected for operation. Next,
the selected bits are added to the same
length of bits (beginning at the right) from
the AUX register.

182

SOURCE

I

RIGHT
ROTATE

ADD
LEFT
BANK

DEST

L

RIGHT
BANK

MASK
(LENGTH)

SHIFT

Figure 9
Thus, the sum (a3, a4, a5) + (b 5, b 6 , b 7 ) is
computed producing a 3-bit sum, S1, S2, S3
(and a possible overflow). The destination
field of the add instruction then specifies a
shift of 1 bit to the left. The shift is made and
the 3 bits of the sum are merged with the
original source data. Note that the same
length specification (3 in the example)
applies in source selection, operation and
merge functions and is not alterable within
one instruction cycle. The destination
contains the set of bits shown in Figure 10
after the add operation. Note that the entire
set of rotate, mask, add, shift and merge
functions took place in one instruction
cycle time.
The content of each field can be represented by a set of digits. These digits have a
direct relation to the specific operations
which the data undergoes as it is directed
along the 8X300 internal data paths. The op
code for add is 1. This is followed by a two
digit source field. The source field is in fact
two fields (in this particular case) in which

Smnotics

the first digit, 2, specifies left bank, while the
second digit specifies the rotate operation
which is to be performed on the incoming
data. The L or length field specifies the
number of bits to be accepted for ALU
operation. This is the mask function specification and selects a quantity of bits counting from the right. The masking operation
takes place after the rotate. The destination
field, like the source field, specifies the bank
or internal register (right bank in this case),
and for the bank destination, also specifies
the shift operation.
There is one important point to note about
the instruction format. Since the fields are
easily represented by octal digits and since
these digits have a direct relation to the
function specified by the field, programming the 8X300 is very easy. Simple
mnemonic representation of each of the
field specifications, such as ADD for the add
function, LB and RB for left bank and right
bank and so forth, are easily translated into
the octal representation. With this convenience, several hundred lines of program
code can be easily generated by hand from
the mnemonic representation. Consequently, for small tasks (i.e., less than' 500
instructions), an assembler is not essential
for efficient programming. A simple conversion is required to generate the actual
program memory content.
The above example is typical of what can be
done with the MOVE, ADD, AND and XOR
instructions. However, the control functions
perform differently and are worthy of further
attention. Specifically, the XEC (execute)
instruction is powerful in that it may be
register or I/O vectored. The XEC instruction temporarily changes the contents of the
address register for the one instruction
cycle following the XEC while allowing sub-

sequent control to be resumed through the
program counter. In this light, XEC may be
viewed as calling a single instruction subroutine. The XEC instruction performs the
vectoring by concatenating the higher order
program counter contents with a number
determined, in part, by the contents of one
of the internal registers or by the content Gf
an I/O port. Thus, the XEC instruction may
be used to sequence through a list where
the list counter is an internal register, or it
may be used to branch to a specific service
routine based on some external status reflected in a selected I/O port.

APPLICATIONS
The 8X300 may be exploited in a variety of
applications where high speed is required
and where the architecture fits the particular requirement. The 8X300 may serve in
disk controllers, communications data
concentrators and demultiplexers, tape
controllers, industrial process controllers,
video controllers including entertainment
and games, as well as CRT/keyboard
terminals, plus a variety of other applications. Principally, the 8X300 affords its
greatest service to the user in high speed,
relatively sophisticated systems. For example, a low speed MOS processor might be
used to control a CRT display and do so
economically. However, add the requirement to do data processing for, say,
graphics or color display, then the 8X300
becomes increasingly attractive. With 8-bit
parallel to serial conversion, the 8X300 may
easily process data and directly produce
video for alphanumeric display. Generally,
one may conclude that the 8X300 serves
well where the control processor is required
to be in the data path. In controlling
computer peripherals, one alternative is to
use a single 8X300 processor to control a
number of peripherals, as opposed to
having one lower speed, less costly processor with separate memory and auxiliary
circuits in each peripheral.
Economically, the 8X300 is certainly competitive with the bit slice approach. For
those who need the performance, the 8X300
affords a complete, single chip processor at
a power consumption of only 1.5 watts in
contrast to three to four chips for a bit slice
equivalent using nearly 5 watts.

plified in Figure 4. It is clear that there is no
direct connection between the program
store and the I/O system, as opposed to
other microprocessors (the MOS microprocessor in particular) in which instructions are fetched over the same bus on wh ich
data and I/O transfers take place.
Figure 4 also emphasizes the compact
nature of the processor system. Note that
the CPU and program store are realized in
as few as three packages (e.g. 8X300 with
two 82S115 chips). I/O ports are added as
required for the particular system configuration.
Connections to the IV bus are not restricted
to the 8T32 type of addressable bidirectional I/O port. Depending upon requirements,
a number of devices may be employed.
Working storage in the form of RAM may be
interfaced directly to the IV bus with an 8T31
or other suitable device used as an address
latch. This affords the user temporary
storage for data and status information.
ROM may also be provided in order to
access fixed constants for use by the
processor. Examples of such ROM include
sine function look-up tables, coordinate
translation constants, sensor linearization
curves, etc.
Some users have objected to the overhead
cost in addressing I/O ports prior to an
operation. As in the example used in this
paper, 500ns (two instructions) were taken
up in selecting I/O ports prior to the major
data operation. This is acceptable if ports
continue to be accessed for a number of
times and thereby reduce the addressing
overhead. However, for those who see this
as a limitation, there is a convenient
alternative. The instruction memory may be
extended such that an extra field appears as
an additional bus which is applied to each
I/O port. Port selection (addressing) would
then be done upon instruction fetch. No
latch addressable I/O ports would be used,
but the normal active-on-address-decode
scheme would be employed. The address
field may be as wide as required to serve all
system I/O ports and if necessary memory.
Bus left bank and right bank partitioning
would still be used, so the address field
would contain two addresses, one for each
bank. With this scheme, an entire operation
such as described earlier, including the
selection of I/O ports, could be accomplished in 250ns.

The typical system configuration for the
8X300 is shown in Figure 4. The 8X300
interfaces to the external world through a
convenient number of I/O ports connected
to the IV bus. Program storage is provided
by a suitable ROM or PROM, but RAM could
be used here also depending upon the
user's application. However, in the more
common control applications, the function
of the processor is dedicated and, consequently, there is no need to have alterable
program storage. This reasoning is also
evident in the 8X300 architecture, as exem-

Gi!lDOliCG

183

184

Gi!lDOliCG

CIIAPTER 5
DEYEIOpmEnT SYSTEmS
AnD PROGRAmS

S!!IDOliCS

185

186

!ii!lDotiC!i

INTRODUCTION

COMPATIBLE PRODUCTS

Microprocessors are considerably different
from the random logic which they replace,
consequently the development of microprocessor based systems is equally different. The interconnection of hardware devices is generally simplified with
microprocessors and a major portion of the
system function is carried out through the
appropriate software or firmware. While the
hardware configurations are generally variations of the basic controller or CPU, structure the firmware is tailored specifically for
the system design. Thus firmware development is a significant and vital portion of a
microprocessor based system designing
and equipment which speeds this development and further enhances the attractiveness of microprocessors.

The following manufacturers produce
equipment which can be made use of in
developing systems which use Signetics
components.
INDUSTRY STANDARD
DEVELOPMENT AID

SIGNETICS PRODUCT

8X300

•

8X300, 3000 Series, 2901
FPLA/PROMs
(Programming)

•
•

•

Scientific Microsystems (SMS)
520 Clyde Ave. Mt. View 94043
Microcontroller Simulator (MCSIM)
SMS ROM Simulator
Data 1/0 Corp.
POB 308, 1297 N.W. Mall
Issaquah, Wash. 98027
Curtis Electro Devices
P.O. B 4090
Mountain View, CA. 94040

Once software is developed, the system
development advances to the firmware
hardware integration phase. This iterative
process of test and software modification
(or hardware modification) results in a functional system design. PROMS are then
fused with the debugging programs and the
system is finalized. This process is made
convenient by equipmentwhich electrically
simulates the microprocessor system along
with the firmware program.
This chapter describes the development
systems available to the microprocessor
user which expedites the two system development phases outlined above.

Si!)DotiCS

187

188

Gi!lDOliCG

CIIAPTIR6
MiliTARY

!ii!lDOliC!i

189

190

!ii!)DotiC!i

The Signetics Mil 38510/883 Program is
organized to provide a broad selection of
processing options, structured around the
most commonly requested customer flows.
The program is designed to provide our
customers:

In addition to the common specs used
throughout the industry for processing and
testing, JAN Qualified products also possess a requirement for a standard marking
to be used throughout the IC industry.

• Standard processing flows to help minimize the
need for custom specs.
• Cost savings realized by using standard processing flows in lieu of custom flows.
• Better delivery lead times by minimizing spec
negotiation time, plus allows customers to buy
product off-the-shelf or in various stages of
production rather than waiting for devices
started specifically to custom specs.

This option is extremely useful when the
reliability and screening of a JAN device is
required, however, Signetics is not listed on
the QPL forthe product needed. Processing
is performed to Mil-Std-883 Method 5004,
and product is 100% electrically tested to
the appropriate JAN slash sheet.

JAN PROCESSING

The following explains the different processing options available to you. Special
device marking clearly distinguishes the
type of screening performed.

JAN QUALIFIED
JAN Qualified product i~ designed to give
you the optimum in quality and reliability.
The JAN processing level is offered as the
result of the government's product standardization programs, and is monitored by
the Defense Electronic Supply Center
(DESC), through the use of industry-wide
procedures and specifications.
JAN Qualified products are manufactured,
processed and tested in a government certified facility to Mil-M 38510, and appropriate
device slash sheet specifications. Design
documentation, lot sampling plans, electrical test data and qualification data for each
specific part type has been approved by the
Defense Electronic Supply Center (DESC)
and products appear on the DESC Qualified
Products List (QPL-38510).
Group B testing, per Mil-Std-883 Method
5005, is performed on each six weeks of
production on each slash sheet for each
package type. Group C, per Mil-Std-883
Method 5005, is performed every ninety
days for each microcircuit group. Group D
testing, per Mil-Std-883 Method 5005, is
performed every six months for each package type.

Group B, C and D data for JAN processed
and the other military processing levels
which follow, consists of Group Band D
testing performed per Mil-Std-883 Method
5005, every six months minimum by package type and Group C per Mil-Std-883
Method 5005, is run every ninety days on
each microcircuit group.

JAN REL
Processing to this option is ideal when no
JAN slash sheets are released on devices
required. Product is processed to Mil-Std883 Method 5004, and is 100% electrically
tested to industry data sheets. (Specific
parameters required by a customer may
also be included.)

/8838
This is a lower priced version ofthe JAN Rei
option described above. Processing is
identical with the only exceptions being the
dc electrical testing over the temperature
range and ac electrical testing at room
temperature are performed as a part of
Group A instead of 100%.

MIL TEMP
If you need a Military temp. range device,
but do not require all the high reliability
screening performed in the other processing options, our Mil-Temp. product is ideal.
Mil-Temp. parts are the standard full MilTemperature range product guaranteed to a
1% AQL to the Signetics data sheet parameters.

S!!IDotiCS

MILITARY GENERIC DATA
Signetics has a new program for those
customers who require qualification data
on their products. This program allows our
customers to obtain reliability information
without the necessity of running Groups B,
C and D inspections for their particular
purchase order. It provides for the customer something that has not been readily
available before in the semiconductor industry in that all Military Generic Data is
controlled and audited by both Government Inspection and Quality Assurance.
Signetics Military Generic Data is generated by the Military Products Division. The
data is compiled from 1) JAN qualification
lots, and 2) Data generated by qualification
lots run for other reliability programs.
A Military Generic family is defined as
consisting of die function and package
type families.
A Generic die function lot qualifies a ninety
day manufacturing period and a representative package type qualifies a one hundred
and eight day manufacturing period.

Military Generic Data
• Allows our customers to qualify Signetics products based on existing qualification data performed at Signetics.
• Allows our customers to reduce costs
and improve deliveries.
• Provides assurance that all Signetics die
function families and packages meet
JAN and customer reliability requirements.
• Provides and attributes summary to the
customer backed by lot identity and
traceability.
Generic Quality Conformance Data is supplied upon customer request in a format
conforming to either Notice 2 (March 1,
1976) or Notice 1 (February 5,1975) of MilStd-883A. Testing to either notice is considered equivalent, since only the test frequency has been altered. Table 2 provides
the definition and qualifying manufacturing
periods as outlined in Notice 1 and Notice 2
of Mil-Std-883A.

191

MIL-STD-883
METHOD

CLASS

REQUIREMENT

2010

Cond A

100%

100%

Cond B

100%

1008 (24 hr min.)

Cond C min

100%

Cond C min

100%

Cond C min

100%

Temperature Cycling2

1010

Cond C

100%

Cond C

100%

Cond C

100%

Constant Acceleration

2001

Cond E min
Y1 plane

100%

Cond E min
Y1 plane

100%

Cond E min
Y1 plane

100%

Internal Visual (Preseal)1
Stabilization Bake

A

REQUIREMENT

Visual Inspection 11
Seal 4
Fine Leak
Gross Leak

Burn-in Test
Critical Electrical
Parameters (post Burn-in)
Signetics FAILURE
CRITERIA
Reverse Bias Burn-in 6
Critical Electrical
Parameters (post burn-in)
Final Electrical Test
Parameters

100%

100%
Cond A or B
Cond C2

Subgroup A-1 (note4)

Read and Record

100%
Note 8

Optional

Note 5

Not Required

240 hours min.1O

100%

160 hours min.

100%

Not Required

Read and Reco.rd

100%
Note 8

Not Required

--

Not Required

---

Not Required

--

100%

Cond A or B
Cond C2

Cond A or B
Cond C2

--

Note 7

1015 T A

= + 125°C

Subgroup A-1 (note4)

PDA5%

PDA10%

---

1015.1, T A = + 150°C
t = 72 hours

Cond A or C9

100%

Not Required

--

Not Required

--

Subgroup A-1

Read and Record

100%
Note 8

Required

100%

Not Required

--

Subgroups A 1, A2,
A3, A4, A9, Functional tests, truth
table when applicable (A7)

100%

Subgroups A 1, A2,
A3, A4, A9, Functiona I tests, truth
table when applicable (A7)

100%

Subgroup A 1, functional tests, truth
table when applicable (A7)

100%

Perform 100% go-:no-go measurements of sub-group
A parameters 12

Radiographic Inspection 3

2012

Yes

100%

Not Required

Quality Conformance
InspectionS

5005

Class A

Note 10

Class B

External Visual

2009

Yes

100%

Yes

Note 10
100%

NOTES
1. Unless otherwise specified, at the manufacturer's option, test samples for Group B, bond strength
(Method 5005) may be selected randomly immediately following internal visual (Method 5004) prior
to sealing.
2. For Class Band C devices, this test maybe replaced with thermal shock Method 1011, TestCondition
A, minimum.
3. The radiographic screen may be performed in any sequence after seal.
4. When fluorocarbon gross leak testing is utilized, Test Condition C 2 shall apply as a minimum.
5. When specified in the applicable device specification, 100% of the devices shall be tested.
6. The reverse bias burn-in is a requirement only when specified in the applicable device specification
and is recommended only for certain MOS, linear orother microcircuits where surface sensitivity may
be of concern. When reverse bias burn-in is not required, interim electrical parameter measurements
following burn-in test are omitted. The order of performing the burn-in and the reverse bias burn-in
may be inverted.
7. Class A devices shall be serialized prior to interim electrical parameter measurements.
8. Electrical parameters shall be read and recorded.
9. For Class A devices, Test Condition F of Method 1015 and 3.4.2 herein shall not apply.
10. Samples shall be selected for testing in accordance with the specific device class and lot requirements of Method 5005.
11. At the manufacturer's option, visual inspection for catastrophic failures may be conducted after each
of the thermal/mechanical screens, after the sequence or after seal test. Catastrophic failures are
defined as missing leads, broken packages or lids off.
12. Detailed test, conditions and limits applicable to each subgroup are given in Signetics data manual
electrical characteristics table. See Table 3 for corresponding Group A tests of Mil-Std-883.

Table 1

192

100%

1014

Serialization
Critical Electrical
Parameters (pre Burn-in)

REQUIREMENT

CLASS
C

CLASS
B
Cond B

SCREEN

MIL-M-38510/MIL-STD-883 PROCESSING LEVELS

!i(gnotiC!i

Not Required

-

Class C

Note 10

Yes

100%

MIL-STD-883A
GROUP A
SUBGROUP

TEST DESCRIPTION

A1

Static tests at 25°C

A2

Static tests at maximum rated operating temperature

A3

Static tests at minimum rated operating temperature

A4

Dynamic tests at 25°C*

A5

Dynamic tests at maximum rated operating temperature*

A6

Dynamic tests at minimum rated operating temperature*

A7

Functional tests at 25° C

A8

Functional tests at maximum and minimum rated operating temperatures

A9

Switching tests at 25°C

A10

Switching tests at maximum rated operating temperature

A11

SWitching tests at minimum rated operating temperature

·Applicable only to Signetics Analog Products

Table 3

MIL-STD-883 GROUP A ELECTRICAL TESTS

BIPOLAR MICROPROCESSORS
AVAILABILITY
PRODUCT
3001
3002
8X300
2901-1

DESCRIPTION
Microprogram Control Unit
Central Processing Element (2-bit slice)
Interpreter/M icrocontroller
Central Processing Element (4-bit slice)

Dip

Flat Pack

I
I
I
*

R
R
*
*

·Under development

QUALIFIED
SUB-GROUPS

QUALIFIES

NOTICE 2

NOTICE 1

A

Electrical Test

B

Package-Same package construction lead finish
and devices produced on same production line
through final seal.

Data selected from devices
manufactured within 6 weeks of
manufacturing period.

Data selected from devices
manufactured
within
24
weeks of manufacturing
period.

C

Die/Process-Devices representing
process families may be used.

Data selected from the representing devices from the
same microcircuit group and
sealed within 12 weeks of
manufacturing period.

Allows the data to be selected from the devices produced within 48 weeks of
manufacturing period.

o

Package-Qualifies the same package construction and lead finished devices produced on the
same production line through final seal.

n/a2

Data selected from the devices representing the same
package construction and
lead finish manufactured
within the 24 weeks of manufacturing period.

n/a 1

n/a 1

the same

OR

If no such data available,manufacturing period extends
to 48 weeks.
NOTES
1. Group A is performed on each lot of Signetics devices.
2. Group D not offered in Mil-Std-883 Notice 1.

Table 2

DEFINITION AND QUALIFYING MANUFACTURING PERIODS
FOR NOTICE 1 AND 2 MIL-STD-883

9i!110liC9

193

MILITARY MICROPROCESSOR SUPPORT CIRCUITS
AVAILABILITY
PRODUCT
LOGIC
54123
54180
54298
54S182
54S194
54S195
54LS365
54LS366
54LS367
54LS368
8262
8281
8291
9602
INTERFACE
8T09
8T10
8T13
8T14
8T15
8T16
8T26
8T28
8T32
8T33
8T34
8T35
8T95
8T96
8T97
8T98

DESCRIPTION

Dip

Fla'pack

Retriggerable Monostable Multivibrator
8-Bit Odd/Even Parity Checker
Quad 2-lnput Mux with Storage
Look-Ahead Carry Generator
4-Bit Bidirectional Shift Register
4-Bit Parallel Access Shift Register
High Speed Hex Tri-State Buffer
High Speed Hex Tri-State Buffer
High Speed Hex Tri-State Buffer
High Speed Hex Tri-State Buffer
9-Bit Parity Generator Checker
Presettable Binary Counter
Presettable High Speed Binary Counter
Dual Monostable Multivibrator

F
F
F

W
W
W

*
*
*

F
F
F
F
F
F
F
F

*
*
*
*
*
*
*

W
W
W
W

Quad Bus Driver with Tri-State Output
Quad D-Type Bus Latch (Tri-State Outputs)
Dual Line Driver
Triple Line Receiver/Schmitt Trigger
Dual Communication EIA/Mil Line Driver
Dual Communication EIA/Mil Line Receiver
Quad Bus Driver/Receiver (Tri-State)
Quad Bus Non-Inverting Driver/Receiver
(Tri-State)
IV Bytes (Programmable)
IV Bytes (Programmable)
IV Bytes (Programmable)
IV Bytes ,(Programmable)
High Speed Hex Buffer/Inverter (Tri-State)
High Speed Hex Buffer/Inverter (Tri-State)
High Speed Hex Buffer/Inverter (Tri-State)
High Speed Hex Buffer/Inverter (Tri-State)

F
F
F
F

W
W
W
W

*
*

*
*
*

F
F
I
I
I
I
F
F
F
F

·Under development

194

9i!1DOliC9

*
*
*
*
*

*
*
*
*

MILITARY MEMORIES
BIPOLAR MEMORIES CROSS REFERENCE
DEVICE

ORGANIZATION

PACKAGE*

PROMs

I

i

82823
828115
828123
828126
828129
828130
828131
828136
828137
828140
828141
828180
828181
828184
828185

32X8
512X8
32X8
256X4
256X4
512X4
512X4
1024X4
1024X4
512X8
512X8
1024X8
1024X8
2048X4
2048X4

FAIRCHILD

HARRIS

MMI

INTERSIL

AMD

TI

-

7602-2
7644-2
7603-2
7610-2
7611-2
7620-2
7621-2
7642-2
7643-2
7640-2
7641-2

5330

5600

-

5331
5300
5301
5305
5306
5352
5353
5340
5341
5380
5381

5610
5603
5623
5604
5624
5606
5626
5605
5625
-

27808
27809
27810
27811

548188

-

F
I
F
F
F
F
F
F,I
F,I
I
I
I
I
I
I

R
R
R
R
R
R
R
R
R
R
R
R
R
R
R

93416
93426
93436
93446
93443
93453
93438
93448
-

-

-

16X48X8
16X48X8

I
I

R
R

93459
93458

16X48X8
16X48X8

I
I

R
R

-

-

F
F
F
F
F
I
F,I
F,I
F
F
F

R
R
R
R
R
R
R
R
R
R
R

93419
93415
93425
93421
93411
93403

-

-

548288
548387
548287
-

-

-

-

-

-

828100
828101

-

-

278100
278101

-

-

-

-

-

-

-

-

2952
2953
2700
2701
3101

5489
54189
548200
548201
548301

-

FPLAs

828100
828101
PLAs

828200
828201
RAMs

54889
548189
548200
548201
548301
82809
82810
82811
82816
82817
82825

16X4
16X4
256X1
256X1
256X1
64X9
1024X1
1024X1
256X1
256X1
16X4

0064

5531
5530
5560

55808
55818
5523
5533
5501

-

-

ROMs

I

828215
828223
828224
828226
828229
828230
828231
828280
828281

512X8
32X8
32X8
256X4
256X4
512X4
512X4
1024X8
1024X8

"NOTE
R BeO Flatpack
F Cerdip
I Ceramic DIP

lii!lDOliCIi

195

MILITARY LOGIC
5400 SERIES
54
DEVICE

DESCRIPTION

54LS 54S

F W F W F W F W

GATES

5400
5401
5402
5403
5408
5409
5410
5411
5412
5415
5420
5421
5422
5426
5427
5430
5432
5450
5451
5452
5453
5454
5455
5460
5464
5465
5486
54133
54134
54136
54260
54266

Quad 2-input NAND Gate
Quad 2-lnput NAND Gate
with o/c
Quad 2-lnput NOR Gate
Quad 2-lnput NAND Gate
with o/c
Quad 2-lnput AND Gate
Quad 2-lnput AND Gate
with o/c
Triple 3-lnput NAND Gate
Triple 3-lnput NAND Gate
Triple 3-lnput NAND Gate
with o/c
Triple 3-lnput AND Gate
with o/c
Dual4-lnput NAND Gate
Dual4-lnput AND Gate
Dual 4-lnput NAND Gate
with o/c
Quad 2-lnput NAND Gate
with o/c
Triple 3-lnput NOR Gate
8-lnput NAND Gate
Quad 2-lnput OR Gate
Expandable Dual 2-Wide
2-lnput AOI Gate
Dual 2-'Nide 2-lnput AOI Gate
Expandable 4-Wide 2-2-2-3
Input AND-OR Gate
4-Wide 2-lnput AOI Gate
(Expandable)
4-Wide 2-lnput AOI Gate
2-Wide 4-lnput AOI Gate
Dual 4-lnput Expander
4-2-3-2 Input AOI Gate
4-2-3-2 Input AOI Gate
Quad 2-lnput ExclusiveOR Gate
13-lnput NAND Gate
12-lnput NAND Gate with
3-State Outputs
Quad Exclusive-OR Gate
with o/c
Dual 5-lnput NOR Gate
Quad Exclusive NOR Gate

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

- -

0

0

0

0

0

0

0

0

0

- - -

0

0

0

0

0

0

0

0

0

0

- -

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

- -

0

0

0

0

0

0

0

0

0

0

- -

0

0

0

-

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

- - - 0 0 - 0 0 0 0
- - 0 0
0

0

54

54H

0

0

- - - - - - - - 0 0
0 0 - -

DEVICE

5404
5405
5406
5407
5416
5417
5428
5433
5437
5438
5440
54125
54126
54128
54140

5470
5472
5473

0

0

- - - -

0

0

0

0

0

0

0

0

5474

- - - - - -

0

0

5476

- - - - 0 0
0 0 0 0 - - 0 0
- - 0 0 - - 0 0
0 0 - - - - 0 0
- - - - 0 0 - - - - - 0 0 - -

5478

0

0

0

0

0

0

0

0

0

0

- - -

- - - - 0 0
- - - - 0 0 - - - 0 0 - - - - - 0 0 0 0 - - - 0 0 - - - -

54101
54103
54106
54107
54108
54109
54112
54113
54114

KEY
o =Available in packages indicated at head of column unless otherwise stated
- = No plans yet
Blank = Qualification in process

196

lii!llOliCIi

DESCRIPTION
HEXINVERTERS/BUFFERS
Hex Inverter
Hex Inverter with o/c
Hex Inverter with Bufferl
Driver with o/c
Hex BufferlDriver with o/c
Hex Inverter BufferlDriver
with o/c
Hex BufferlDriver with o/c
Quad 2-lnput NOR Buffer
Quad 2-lnput NOR Buffer
Quad 2-lnput NAND Buffer
Quad 2-lnput NAND Buffer
with o/c
Dual 4-lnput NAND Buffer
Quad Bus Buffer Gate
with 3-State Outputs
Quad Bus Buffer Gate with
3-State Outputs
Quad 2-lnput NOR Buffer
Dual 4-lnput NAND
Line/Driver

54LS 54S

54H

F W F W F W F W
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

- - - - 0 0 0 0 -

0

0

0

0

0

0

0

0

- - - -

0

0

0

0

0

0

0

0

0

0

0

- - - - - - - - - - -

0

0

- - -

- -

- -

0

0

- - - - - - - - - - - -

- - - -

0

0

- -

FLIP-FLOPS
J-K Flip-Flop
0 0 - - - - - J-K Master-Slave Flip-Flop
0 0 - - 0 0
Dual J-K Master-Slave
Flip-Flop
0 0 0 0 - - 0 0
Dual D-Type Edge-Triggered
Flip-Flop
0 0 0 0 0 0 0 0
Dual J-K Master-Slave
Flip-Flop
0 0 0 0 0 0
Dual J-K Negative EdgeTriggered Flip-Flop
- - 0 0 - - - J-K Negative EdgeTriggered Flip-Flop
- - - - - - 0 0
Dual J-K Negative EdgeTriggered Flip-Flop
- - - - - - 0 0
Dual J-K Negative EdgeTriggered Flip-Flop
- - - - - - 0 0
Dual J-K Master-Slave
Flip-Flop
o Q 0 0 - - - Dual J-K Negative EdgeTriggered Flip-Flop
- - - - - - 0 Dual J-K Positive EdgeTriggered Flip-Flop
0 0 0 0 - Dual J-K Negative EdgeTriggered Flip-Flop
- - 0 0 0 0 - Dual J-K Negative EdgeTriggered Flip-Flop
- 0 0 0 0 - Dual J-K Negative EdgeTriggered Flip-Flop
- - 0 0 0 0 - -

-

-

-

-

MILITARY LOGIC
5400 SERIES Cont'd
54
DEVICE

DESCRIPTION

LATCHES
Quad Bistable Latch
5475
5477 Quad Bistable Latch
54100 4-Bit Bistable Latch (Dual)
54116 Dual 4-Bit Latch with Clear
54279 Quad S-R Latch
SCHMITT TRIGGERS
5413 Dual Hex Schmitt Trigger
Hex Schmitt Trigger
5414
54132 Quad Schmitt Trigger

5442
5443
5444
5445
5446A
5447
5448
54138
54139
54145
54154
54155
54156
54254
54261

54LS 54S

F W F W F W F W
0

0

0

0

- - - -

I
I

- - - - - Q - - - - - - - - - - - -

0

0

-

0

- - - -

0

0

0

.0

0

0

0

0

0

0

0

0

- - - -

- - - - - - -

DECODERS
BCD-to-Decimal Decoder
0 0
Excess 3-to-Decimal Decoder 0 0 - - Excess 3-Gray-to-Decimal
Decoder
0 0 - - BCD-to-Decimal Decoderl
Driver with o/c
0 0 - - BCD-to-7 Segment Decoderl
Driver
0 0 - - BCD-to-7 Segment Decoderl
Driver
0 0 - - BCD-to-7 Segment Decoderl
Driver
0 0 - - 3-to-8 Line Decoder/Demux - - 0 0 Dual 2-to-4 Line
Decoder/Demux
- - 0 0 0
BCD-to-Decimal Decoderl
Driver with o/c
0 0
4-Line to 16-Line Decoderl
Demux
I Q I Q Dual 2-Llne to 4-Line
Decoder/Demux
0 0 - - Dual 2-Line to 4-Line
Decoder/Demux
0 0 - - 4-Line to 16-Line Decoder
- - 0 0 2X4 2's Complement- - 0 0 Multiplier

ENCODERS'
54147 10-Line to 4-Line Priority
Encoder
54148 8-Line to 3-Line Priority
Encoder

- - - - - - - - - - - - - - - - 0

54

54H

- -

- - - - - - -

DEVICE

MONOSTABLE
MULTIVIBRATORS
54121 Monostable-M u Itivi brator
54122 Retriggerable Monostable
Multivibrator
54123 Retriggerable Monostable
Multivibrator
54222 Dual Monostable Multivibrator

54LS 54S

0

0

- - - -

0

0

- - - -

0

0

0

0

0

0

54150
54151
54153
54157

0

0

- - -

- - -

54158

o

0

- - - - - -

54251
54253
54257
54258
54298

- - - - - - - - - - - - - - - -

- - - - - - - - - - - - - 0 - - - -

0

- - - 0

0

- - - - - - - - - - - - -

-

DATA SELECTORSI
MULTIPLEXERS
16-Line to 1-Line Mux
8-Line to 1-Line Mux
Dual 4-Line to 1-Line Mux
Quad 2-lnput Data Selector
(non-inv.)
Quad 2-lnput Data Selector
(inv.)
Data Selector/Mux with
3-State Outputs
Dual 4-Line to 1-Line Data
Selector/Mux
Quad 2-Line to 1-Line Data
Selector/Mux
Quad 2-Line to 1-Line Data
Selector/Mux
Quad 2-lnput Mux
with Storage

54H

F W F W F W F W

COUNTERS
5490
Decade Counter
0 0
5492
Divide-by-Twelve Counter
0 0
5493 4-Bit Binary Counter
0 0
54160 Synchronous 4-Bit Decade
Counter
0 0
54161 Synchronous 4-Bit Binary
Counter
0 0
54162 Synchronous 4-Bit Decade
Counter
0 0
54163 Synchronous Binary Counter 0 0
54190 Synchronous BCD Up/Down
Counter
0 0
54191 Synchronous Binary Up/Down
Counter
0 0
54192 Synchronous Decade Upl
Down Counter
0 0
54193 Presettable Binary Up/Down
Counter
0 0
54196 Presettable Decade Counterl
Latch (8290)
- 54197 Presettable Binary Counterl
Latch
54290 Decade Counter
- 54293 4-Bit Binary Counter
- -

- - -

- - - - -

DESCRIPTION

- - - - - - - - - -

I

0

0

0

0

0

- - - - - 0 0 0 - 0 0 0 0 - -

0

0

0

0

0

0

- -

0

0

0

0

0

0

- -

- -

0

0

- - - -

- -

0

0

0

0

0

-

-

- -

- - - -

- -

- - - -

0

0

- - - - - -

KEY

= Available in packages indicated at head of column unless otherwise stated
- = No plans yet

o

Blank = Qualification in process

Gi!lnOliCG

197

MILITARY LOGIC
5400 SERIES Cont'd

8200 SERIES
54

DEVICE
5491
5494
5495
5496
54164
54165
54166
54170
54194
54195
54198
54199
54670

DESCRIPTION
SHIFT REGISTERS
8-Bit Register
4-Bit Shift Register
(PISO)
4-Bit Left-Right Shift
Register
5-Bit Shift Register
8-Bit Parallel-Out Serial
Shift Register
Parallel-Load 8-Bit Shift
Register
8-Bit Shift Register
4X4 Register File
4-Bit Bidirectional
Universal Shift Register
4-Bit Parallel-Access
Shift Register
8-Bit Shift Register
8-Bit Shift Register
4X4 Register File
(3-State)

ARITHMETIC ELEMENTS
5480
Gated Full Adder
5483
4-Bit Binary Full Adder
5485
4-Bit Magnitude Comparator
54180 8-Bit Odd/Even Parity
Generator/Checker
54181 4-Bit Arithmetic Logic Unit
54182 Look-Ahead Carry Generator

54LS 54S

54H

DEVICE

PACKAGE

8243
8260
8261
8262
8269

ARITHMETIC ELEMENTS
8-Bit Position Scaler
Arithmetic Logic Unit
Fast Carry Extender
9-Bit Parity Generator and Checker
4-Bit Comparator

I
I
F
F
F

W
W
W

- - -

8280
8281
8284
8285
8288
8290
8291
8292
8293

COUNTERS
Presettable Decade Counter
Presettable Binary Counter
Binary Up/Down Counter
Decade Up/Down Counter
Divide-by-Twelve Counter
Presettable High Speed Decade Counter
Presettable High Speed Binary Counter
Presettable Low Power Decade Counter
Presettable Low Power Binary Counter

F
F
F
F
F
F
F
F
F

W
W
W
W
W
W
W
W
W

- - - I - - - - - - I - - - - - - -

8250
8251
8252

DECODERS
Binary-to-Octal Decoder
BCD-to-Decimal Decoder
BCD-to-Decimal Decoder

F
F
F

W
W
W

8241
8242

GATES
Quad Exclusive-OR Gate
Quad Exclusive-NOR Gate

F
F

W
W

8275

LATCHES
Quad Bistable Latch

F

W

F
F
F
F
F
F
I
I
F
F

W
W
W
W
W
W

I
I
I
I
F
F

Q
Q
Q
Q

W
W

F

W

F

W

F W F VI F W F W
0

0

- -

0

0

- -

0

0

0

0

0

-

-

- -

-

-

- -

- - - - 0

0

-

- - - - - - - - - - - 0 0 - - - -

0

0

0
0

0

0

0

0

- - - -

-

0

- 0

0

0

0

0

0

0

0

- - - -

- - - - - 0 - - - 0 0 - -

0

- - - - - I - I Q I - - 0 0 - - - - - 0

0

MUL TIPLEXERS
8230 ' 8-lnput Digital Mutiplexer
8231
8-lnput Digital Multiplexer
8232
8-lnput Digital Multiplexer
8233
2-lnput 4-Bit Digital Multiplexer
8234
2-lnput 4-Bit Digital Multiplexer
8235
2-lnput 4-Bit Digital Multiplexer
8263
3-lnput 4-Bit Digital Multiplexer
8264
3-lnput 4-Bit Digital Multiplexer
8266
2-lnput 4-Bit Digital Multiplexer
8267
2-lnput 4-Bit Digital Multiplexer
8200
8201
8202
8203
8270
8271
8273
8274

KEY
Available in packages indicated at head of column unless otherwise stated
- = No plans yet
Blank = Qualification in process
0=

F = Cerdip
W = Cer Pack, Flat
Q = Ceramic Flat

198

DESCRIPTION

G!!IDotiCG

REGISTERS
Dual 5-Bit Buffer Register
Dual 5-Bit Buffer Register with D Inputs
10-Bit Buffer Register
10-Bit Buffer Register with D Inputs
4-Bit Shift Register
4-Bit Shift Register
10-Bit Serial-In, Parallel-Out
Shift Register
10-Bit Parallel-In, Serial-Out
Shift Register

Q
Q

Q
Q'

W
W

MILITARY ANALOG
INDUSTRY CROSS REFERENCE
DEVICE

DESCRIPTION

PACKAGE

FSC

MOT

-

SE526
SE527
SE529
LM139
fJ.A710
fJ.A711

COMPARATORS
Analog Voltage Comparator
Analog Voltage Comparator
Analog Voltage Comparator
Quad Comparator
Differential Voltage Comparator
Comparator

F
F
F
F
F
F

K
K
K

-

-

fJ.A139
fJ.A710
fJ.A711

MC1710
MC1711

SE510
SE511
SE515
fJ.A733

DIFFERENTIAL AMPLIFIERS
Dual Differential Amplifier
Dual Differential Amplifier
Differential Amplifier
Video Amplifier

F
F
F
F

K
K

-

LM101
LM101A
LM107
LM108
LM108A
LM124
LM158
MC1558
SE532
fJ.A709
fJ.A709A
fJ.A741
fJ.A747
fJ.A748

OPERATIONAL AMPLIFIERS
High Performance Op Amp
High Performance Op Amp
General Purpose Op Amp
Precision Op Amp
Precision Op Amp
Quad Op Amp
Dual Op Amp
Dual Op Amp
Dual Op Amp
OpAmp
OpAmp
General Purpose Op Amp
Dual Op Amp
General Purpose Op Amp

F
F
F
F
F
F

F
F
F
F
F

T
T
T
T
T
T
K
T

SE567

PHASE LOCKED LOOPS
Tone Decoder PLL

F

DM7820
DM7830

LINE RECEIVERS
Dual Differential Line Receiver
Dual Differential Line Receiver

SE555
fJ.A723

-

NSC

TI

-

-

RAYTHEON

-

-

-

LM161

-

LM139
LM710
LM711

SN52710
SN52711

-

-

-

-

-

-

-

fJ.A733

MC1733

LM733

SN52733

RM733

T
T
T
T
T

fJ.A 101
fJ.A1 01 A
fJ.A107
fJ.A 108
fJ.A108A

MLM101
MLM101A
MLM107

-

-

-

-

LM101
LM101A
LM107
LM108
LM108A
LM124

fJ.A1558

MC1558

fJ.A709
fJ.A709A
fJ.A741
fJ.A747
fJ.A748

MC1709
MC1709P2
MC1741
MC1747
MC1748

LM101
LM101A
LM107
LM108
LM108A
LM124
LM158
LM1558
LM158
LM709

T

-

F
F

-

TIMERS
Timer

F

VOLTAGE REGULATOR
Precision Voltage Regulator

F

F

-

T
K

-

-

-

-

-

SN52101A
SN52107

SN52709

-

LM139
RM710
RM711

-

RM1558

RM709

-

-

LM741
LM747
LM748

SN52741
SN52748

-

-

LM567

-

-

-

-

DM7820
DM7830

SN55182
SN55183

-

T

MC1555

-

LM555

SN52555

RM555

L

fJ.A723

MC1723

LM723

SN52723

RM723

-

. RM741
RM747

PREFIX NOMENCLATURE
S/SE
MC
LM

!-IA

Signetics Proprietary (-55°C to + 125°C)
Motorola Second Source
National Second Source
Fairchild Second Source

!ii!)notiC!i

199

How can you switch to bipolar from MOS
microprocessing without obsoleting your existing
designs? How can you reduce hardware design time,
reduce programming time, reduce debugging time?
How can you try it before you buy it?
Signetics has put it all together in bipolar
microprocessors featuring the industry's most
complete product family, fastest 2-bit j.LPA (3001),
first 8-bit fixed instruction processor (8X300),
the 8080 emulator, several designers' kits, interface elements, bipolar memories and all using
Signetics superior low power Schottky LSI
technology.

•
8080 Emulator upgrades performance of
existing system. Delivers 5 times more performance,
reduces micro-code writing time, operates from existing
software, makes designing easy. (Available now.)

•

A free microprocessing book. It's filled with

memory, logic, interface info and application notes. All

Signetics' high performance bipolar products are listed in
detail.

•
The industrY's leading selection of RAM's,
ROM's, PROM's, FPLA's, you name it. Signetics
has more configurations and performance levels available
from stock. You get the right fit and absolute maximum
efficiency in minimum time.

•
8X3OO Designer's Kit. We supply all the parts
you need to build your own general purpose controlleryou do the PROM programming, checkout prototype
system, order production quantities from Signetics. It's
just another example of Signetics total support.
•

Long list of interface products to pick from.

Signetics has the interface products you'll need to make
your bipolar microprocessing shopping easier and more
convenient. Now you get everything on your list from
one source.

@)

Introductory Designer's Kit. A $230.00
value, for $100.00. You get 12 parts and 1 manual to

let you work with bipolar, design with bipolar, program

with bipolar, and prove out all the advantages for yourself. The parts you need to actually try out Signetics'
3000 Thtal System.

•
A description of all design support systems.
Read all about 'em. SMS ROM Simulator, SMS McSim
Prototyping System, Microassembler, SMS McCAP
Assembler and more, all in the microprocessor book.
Field Applications Engineers that know
bipolar microprocessing. They have the industry's
best support systems at hand to help you solve your
design problems. They will show you exactly how
Signetics' total bipolar microprocessor capabilities will
make your design resources go further.

N ow you know when Signetics claims to
reduce your hardware design time, to reduce your
programming time, and to reduce your debugging
time ... Signetics supports it. Start saving time
in the future by mailing the coupon today.

r---~~~~;~;~~~~:~;~;~;:;-~--

o

Send me information on the 3000 Introductory
Designer's Kit .

D Send me information on the 8X300 Designer's Kit-to
dream up my own controllers.

o

I want to read the book on bipolar microprocessing.
Send it ASAP. FREE.
D Send me info now on an emulator that delivers 5 times
more performance, the 8080.

o

Have a Bipolar Microprocessing Answerman call me for
an appointment.

My application is _ _ _ _ _ _ _ _ _ _ _ _ _ __

Name

Title

l(gnDliCI
a subsidiary of Us. PIiIips Corporation
Signetics Corporation
811 East Arques Averoo
Sunnyvale, California 94086
Telephone 408/739-7700

SIGNETICS
HEADQUARTERS
811 East Arques Avenue
Sunnyvale. California 94086
Phone: (408) 739-7700
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Phone: (602) 971-2517
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Industires ltd
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Philips Electronics
Industries ltd.
Phone: (514) 342-9180

onawa. Ontario
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Industries Ltd.
Phone: (613) 237-3131
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Industries Ltd.
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Phone: (913) 492-8470
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Component Specialists
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Phone: (206) 746-8750
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Phone: (206) 767-3160
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Phone: (206) 763-8200

FOR SIGNETICS PRODUCTS
WORLDWIDE
ARGENTINA
Fapesa I. y.C.
Buenos-Aires
Phone: 652-743817478
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Wien
Phone: 93 26 11
AUSTRALIA
Philips Industries-ELCOMA
lane-Cove N.SW.
Phone: 421261
BELGIUM
M.B.l.E.
Bruselles
Phone: 523 00 00
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Ibrape. S.A.
Sao Paulo
Phone: 287-7144
CANADA
Philips Electron Devices
Toronto
Phone: 425-5161
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Philips Chilena S.A.
Phone: 39-4001
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MiniwaU A/S
Kobenhavn
Phone: (01) 69 1622
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Oy Philips Ab
Helsinki
Phone: 1 72 71
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R.T.C.
Paris
Phone: 355-44-99
GERMANY
Valvo
Hamburg
Phone: (040) 3296-1
HONG KONG
Philips Hong Kong. lid.
Kwuntong
Phone: 3-427232
INDIA
Semiconductors. Ltd.
(REPRESENTATIVE ONLY)
Bombay
Phone: 293-667

INDONESIA
P.T. Phlllps-Ralin Electronics
Jakarta
Phone: 581058
IRAN
Berkeh Company. lid.
Tehran
Phone: 831564
ISRAEL
Rlpac Eleclronlcs. Ltd.
Tel Aviv
Phone: 477115-6-7
ITALY
Philips S.p.A.
Milano
Phone: 2-6994
JAPAN
Signelics Japan. lid.
Tokyo
Phone: (03) 230-1521
KOREA
Philips Electronics Korea. Ltd.
Seoul
Phone: 44-4202
MEXICO
Electronlca S.A. de C. V.
Mexico D.F.
Phone: 533-1180
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Philips Nederland B.V.
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Phone: (040) 79 33 33
NEW ZEALAND
E.D.A.C. Ltd.
Wellington
Phone: 873-159
NORWAY
Electronica A.S.
Oslo
Phone: (02) 15 05 90
PHILIPPINES
Philips Industrial Dev .. Inc.
Makata-Rizal
Phone: 868951-9
SINGAPORE/MALAYSIA
Philips Singapore Pte .. Ltd.
Toa Payoh
Phone: 538811
SOUTH AFRICA
E.D.A.C. IPTY). LId.
Johannesburg
Phone: 24-6701-3
SPAIN
Copresa S.A.
Barcelon"
Phone: 329 63 12
SWEDEN
Elcoma A.B.
Stockholm
Phone: 08/67 97 80
SWITZERLAND
Philips A.G.
Zurich
Phone: 01144 22 11
TAIWAN
Philips Taiwan. lid.
Taipei
Phone: (02) 551-3101-5
THAILAND/LAOS
Sleng Thong Radio. lid.
Bangkok
Phone: 527195. 519763
UNITED KINGDOM
MUllard.lId.
London
Phone: 01-580 6633
UNITED STATES
Signatici International Corp.
Sunnyvale. California
Phone: (408) 739-7700
VENEZUELA. PANAMA.
ARUBA. TRINIDAD
Inltrul.b C.A.
Caracas
Phone 614138

Feb. 1977



Source Exif Data:
File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37
Producer                        : Adobe Acrobat 9.31 Paper Capture Plug-in
Modify Date                     : 2010:03:26 22:25:27-08:00
Create Date                     : 2010:03:26 22:25:27-08:00
Metadata Date                   : 2010:03:26 22:25:27-08:00
Format                          : application/pdf
Document ID                     : uuid:503268b4-ab7c-4b13-a3e5-f021543aa52a
Instance ID                     : uuid:f1ebcfda-1608-47a7-bebf-9e60a4cfdd36
Page Layout                     : SinglePage
Page Mode                       : UseOutlines
Page Count                      : 203
EXIF Metadata provided by EXIF.tools

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