1977_Fairchild_CMOS_Data_Book 1977 Fairchild CMOS Data Book

User Manual: 1977_Fairchild_CMOS_Data_Book

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MNlW
ARROW ELECTRONICS, INC.
521 WEDDELL DRIVE
SUNNYVALE, CALIFORNIA 94086
TEL (408) 745-6600
TWX 91 0-339-9371

~

o

464 Ellis Street, Mountain View, California 94042
©1977 Fairchild Camera and Instrument Corporation/464 Ellis Street, Mountain View, California 94042/(415)962-5011ITWX 91 0-379-6435

TABLE OF CONTENTS

SECTION 1 INTRODUCTION ................................................... 1-3
SECTION 2 NUMERICAL INDEX OF DEVICES ....................... . . . . . . . . . .. 2-3
SECTION 3 SELECTION GUIDES AND CROSS REFERENCE
Selector Guide by Function ................................................... 3-3
SECTION 4 FAIRCHILD 4000B SERIES CMOS GENERAL DESCRIPTION ......... 4-3
SECTION 5 DESIGN CONSIDERATIONS WITH FAIRCHILD 4000B SERIES CMOS
Introduction ..................................................................
Power Consumption ..........................................................
Supply Voltage Range ........................................................
Propagation Delay ............................................................
Noise Immunity ..............................................................
Interface to TTL ..............................................................
Input/Output Capacity ........................................................
Output Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Input Protection ..............................................................
Handling Precautions .........................................................
A Word to the TTL Designer ..................................................

5-3
5-3
5-4
5-5
5-7
5-7
5-8
5-8
5-8
5-8
5-8

SECTION 6 JEDEC INDUSTRY STANDARD "B" SERIES CMOS SPECIFICATIONS 6-3
SECTION 7 TECHNICAL DATA
Fairchild 40008 Series CMOS Family Characteristics ........................... 7-3
Definition of Symbols and Terms .............................................. 7-9
Data Sheets ................................................................. 7-11
(See Numerical index of devices for page numbers)
SECTION 8 APPLICATIONS INFORMATION .................................... 8-3
SECTION 9 FAIRCHILD ORDERING INFORMATION AND PACKAGE OUTLINES
Ordering Information ................ , ........................................ 9-3
Matrix VI Program ............................................................ 9-7
Unique 38510 Program ...................................................... 9-10
Package Physical Dimensions ................................................ 9-14
SECTION 10 FAIRCHILD FIELD SALES OFFICES SALES REPRESENTATIVES
AND DISTRIBUTOR LOCATIONS ................................. 10-3

iii

I
\

INTRODUCTION

,

INTRODUCTION

This data book provides complete technical information on Fairchild's
40008 Series Iso planar CMOS fami Iy. The family encompasses a wide
range of SSI, MSI and LSI devices offering the designer a complete
spectrum of various circuit complexities all at highest performance.
For easy reference to this broad range of devices, a number if indices,
selection guides and cross references can be found in Sections 2 and

3.
Since the first introduction of CMOS in the early 1970s, and as each
new generation of designs was developed, a large variety of functional
and performance parameters were generated by the industry creating
a great deal of customer confusion.
In late 1976, under the auspices of EIA/JEDEC, the CMOS vendor
community accepted the formidable task of clearing this confusion
via industry-wide standardization. The result, as found in Section 6 of
this book, is the new "Jedec Industry Standard '8' Series CMOS
Specification." Fairchild lauds EIA/JEDEC and the industry in total for
such a cooperative and valuable effort and encourages continuation
of this trend.
It should be noted that all Fairchild CMOS products have always,
since first introduction in early 1974, complied with today's JEDEC
CMOS specifications. Furthermore, it should be noted that Fairchild
offers the only CMOS family which meets or exceeds all functional
and performance parameters of all CMOS devices and generations of
devices introduced to date. Fairchild continues to provide leadership
in technology.

1-3

•

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NUMERICAL INDEX OF DEVICES

LOGIC DEVICES

DEVICE
NO.
40018
40028
40068
4007U8
40088
40118
40128
40138
40148
40158
40168
40178
40188
40198
40208
40218
40228
40238
40248
40258
40278
40288
40298
40308
40318
40348
40358
40408
40418
40428
40438
40448
40458
40468
40478
40498
40508
40518
40528
40538
40668
40678

DESCRIPTION

PAGE

Quad 2-lnput NOR Gate ................................................... 7-11
Dual4-lnput NOR Gate .................................................... 7-11
18-Stage Static Shift Register .............................................. 7-13
Dual Complementary Pair Plus Inverter ..................................... 7-15
4-8it 8inary Full Adder .................................................... 7-17
Quad 2-lnput NAND Gate .................................................. 7-19
Dual4-lnput NAND Gate ................................................... 7-19
Dual D Flip-Flop ........................................................... 7-21
8-8it Shift Register ........................................................ 7-24
Dual4-8it Static Shift Register ............................................. 7-27
Quad Bilateral Switches .................................................... 1-30
5-Stage Johnson Counter ................................................. 7-33
Presettable Divide-by-N Counter (Obsolete - For Ref. Only) ................. 7-36
Quad 2-lnput Multiplexer .................................................. 7-40
14-Stage 8inary Counter .................................................. 1-42
8-8it Shift Register ........................................................ 7-45
4-Stage Divide-by-8 Johnson Counter ...................................... 7-47
Triple 3-lnput NAND Gate .................................................. 7-49
7-State Binary Counter .................................................... 7-50
Triple 3-lnput NOR Gate ................................................... 7-53
Dual JK Flip-Flop ...................... , ................................... 7-54
1-of-10 Decoder .......................................................... 7-57
Synchronous Up/Down Counter ........................................... 7-59
Quad Exclusive-OR Gate ..................•............................... 7-64
64-Stage Static Shift Register .............................................. 7-65
8-8it Universal 8us Register ............................................... 7-67
4-Bit Universal Shift Register .............................................. 7-73
12-Stage 8inary Counter .................................................. 7-76
Quad True/Complement 8uffer (Obsolete - For Ref. Only) .................. 7-79
Quad D Latch ............................................... :.............. 7-81
Quad R/S Latch with 3-State Output (Obsolete - For Ref. Only) .............. 7-84
Quad R/S Latch with 3-State Output ........................................ 7-88
21-Stage 8inary Counter .................................................. 7-92
Micropower Phase-Locked Loop ........................................... 7-93
Monostable/Astable Multivibrator ........................................... 7-98
Hex Inverting Buffer ...................................................... 7-102
Hex Non-Inverting 8uffer ................................................. 7-102
8-Channel Analog Multiplexer/Demultiplexer .............................. 7-105
Dual4-Channel Analog Multiplexer/Demultiplexer ......................... 7-108
Triple 2-Channel Analog Multiplexer/Demultiplexer ........................ 7-111
Quad Bilateral Switches ................................................... 7-114
16-Channel Analog Multiplexer/Demultiplexer ............................. 7-117
2-3

NUMERICAL INDEX OF DEVICES

LOGIC DEVICES

DEVICE
NO.
40688
4069U8
40708
40718
40738
40758
40768
40778
40788
40818
40858
40868
40938
400148
400858
400978
400988
401618
401638
401748
401758
401938
401948
401958
41048
45108
45118
45128
45148
45158
45168
45188
45208
45218
45228
45268
45278
45288
45318
45328
45398
45438

DESCRIPTION

.PAGE

8-lnput NAND Gate (Obsolete - For Ref. Only) ............................
Hex Inverter .............................................................
Quad Exclusive-OR Gate .................................................
Quad 2-lnput OR Gate ....................................................
Triple 3-lnput AND Gate (Obsolete - For Ref. Only) ........................
Triple 3-lnput OR Gate (Obsolete - For Ref. Only) .........................
Quad D Flip-Flop with 3-State Output ......................................
Quad Exclusive-NOR Gate (Obsolete - For Ref. Only) .....................
8-lnput NOR Gate (Obsolete - For Ref. Only) ..............................
Quad 2-lnput AND Gate ..................................................
DuaI2-Wide, 2-lnput AND-OR-Invert Gate (Obsolete - For Ref. Only) .......
4-Wide, 2-lnput AND-OR-Invert Gate ......................................
Quad 2-lnput NAND Schmitt Trigger .......................................
Hex Schmitt Trigger ......................................................
4-8it Magnitude Comparator ..............................................
3-State Hex Non-Inverting 8uffer .........................................
3-State Hex Inverting 8uffer ..............................................
4-8it Synchronous Counter ...............................................
4-8it Synchronous Counter ...............................................
Hex D Flip-Flop ..........................................................
Quad D Flip-Flop .........................................................
4-8it Up/Down 8inary Counter ............................................
4-8it 8i-directional Universal Shift Register (Obsolete - For Ref. Only) .....
4-8it Universal Shift Register (Obsolete - For Ref. Only) ...................
Quad Low Voltage to High Voltage Translater with 3-State Outputs ..........
Up/Down Decade Counter ................................................
8CD to 7 -Segment Latch/Decoder/Driver .................................
8-lnput Multiplexer with 3-State Output ............ , ......................
1-of-16 Decoder/Demultiplexer with Input Latch ...........................
1-of-16 Decoder/Demultiplexer with Input Latch ...........................
Up/Down Counter ........................................................
Dual4-8it Decade Counter ...............................................
Dual4-8it 8inary Counter ....................... ; ........................
24-Stage 8inary Counter .................................................
4-8it 8CD Programmable Down Counter ...................................
4-8it 8inary Programmable Down Counter .................................
8CD Rate Multiplier ......................................................
Dual Retriggerable Resettable Monostable Multivibrator ....................
13-lnput Parity Checker/Generator (Obsolete - For Ref. Only) .............
8-lnput Priority Encoder (Obsolete - For Ref. Only) ........................
Dual4-lnput Multiplexer ..................................................
8CD to 7-Segment Latch/Decoder/Driverfor Liquid Crystals ...............
2-4

7-121
7-122
7-124
7-125
7-126
7-127
7-128
7-132
7-133
7-135
7-136
7-138
7-140
7-263
7-265
7-269
7-269
7-273
7-273
7-279
7~282

7-285
7-289
7-293
7-142
7-145
7-149
7-156
7-161
7-164
7-167
7-171
7-174
7-177
7-178
7-178
7-183
7-185
7-190
7-192
7-195
7-197

NUMERICAL INDEX OF DEVICES

LOGIC DEVICES

DEVICE
NO.
4555B
4556B
4557B
4582B
4702B
4703B
4710B
4720B
4722B
4723B
4724B
4725B
4727B
4731B
4741B
6508B

DESCRIPTION

PAGE

DuaI1-of-4 Decoder Demultiplexer ........................................ 7-198
DuaI1-of-4 Decoder Demultiplexer ........................................ 7-198
1-to-64-Bit Variable Length Shift Register ................................. 7-201
Carry Lookahead Generator (Obsolete - For Ref. Only) .................... 7-203
Programmable Bit Rate Generator ......................................... 7-206
FIFO Buffer Memory ...................................................... 7-214
Register Stack 16 x 4-Bit RAM with 3-State Output Register ................. 7-229
256-Bit RAM with 3-State Output .......................................... 7-234
Programmable Timer/Counter ............................................ 7-237
Dual4-Bit Addressable Latch ............................................. 7-246
8-Bit Addressable Latch .................................................. 7-250
64-Bit RAM with 3-State Output ........................................... 7-254
7-Stage Counter ......................................................... 7-257
Quad 64-Bit Static Shift Register .......................................... 7-259
4 x 4 Cross Point Switch .................................................. 7-261
1024-Bit (1024x 1) CMOS RAM with 3-State Output ....................... 7-297

2-5

I
"'------SELECTION GUIDES AND CROSS
REFERENCE

•

SELECTOR GUIDE BY FUNCTION

FUNCTION

DESCRIPTION

PAGE

Counters
4017B
4020B
4022B
4024B
4029B
4040B
4045B
4510B
4516B
4518B
4520B
4521B
4522B
4526B
4722B
4727B
40161B
40163B
40193B

5-Stage Johnson Counter ................................................. 7-33
14-Stage Binary Counter ................................................. 7-42
4-Stage Divide-by-8 Johnson Counter ..................................... 7-47
7-Stage Binary Counter ................................................... 7-50
Synchronous Up/Down Counter ........................................... 7-59
12-Stage Binary Counter ................................................. 7-76
21-Stage Binary Counter ................................................. 7-92
Up/Down Decade Counter ............................................... 7-145
Up/Down Counter ....................................................... 7-167
Dual 4-Bit Decade Counter .............................................. 7-171
Dual 4-Bit Binary Counter ............................................... 7-174
24-Stage Binary Cou nter ................................................ 7-1 77
4-Bit BCD Programmable Down Counter ................................. 7-178
4-Bit Binary Programmable Down Counter ............................... 7-178
Programmable Timer/Counter ........................................... 7-237
7-Stage Counter ........................................................ 7-257
4-Bit Synchronous Counter .............................................. 7-273
4-Bit Synchronous Counter .............................................. 7-273
4-Bit Up/Down Binary Counter ................•.......................... 7-285

Registers
4006B
4014B
4015B
4021B
4031B
4034B
4035B
4557B
4731B

18-Stage Static Shift Register ............................................ 7-13
8-Bit Shift Register ....................................................... 7-24
Dual 4-Bit Static Shift Register ............................................ 7-27
8-Bit Shift Register ....................................................... 7-45
64-Stage Static Shift Register ............................................ 7-65
8-Bit Universal Bus Register .............................................. 7-67
4-Bit Universal Shift Register ............................................. 7-73
1-to-64 Variable Length Shift Register ................................... 7-201
Quad 64-Bit Static Shift Register ........................................ 7-259

Decoders
4028B
4511 B
4514B
4515B
4543B
4555B
4556B
4723B
4724B

and Demultiplexers
1-of-10 Decoder .......................................................... 7-57
BCD to 7-Segment Latch/Decoder/Driver ................................ 7-149
1-of-16 Decoder/Demultiplexer with Input Latch .......................... 7-161
1-of-16 Decoder/Demultiplexer with Input Latch .......................... 7-164
BCD to 7-Segment Latch/Decoder/Driver for Liquid Crystals .............. 7-197
Dual 1-of-4 Decoder Demultiplexers ..................................... 7-198
Dual 1-of-4 Decoder Demultiplexer ...................................... 7-198
Dual 4-Bit Addressable Latch ............................................ 7-246
8-Bit Addressable Latch ................................................. 7-250

3-3

SELECTOR GUIDE BY FUNCTION

FUNCTION

DESCRIPTION

PAGE

Digital Multiplexers
40198
Quad 2-lnput Multiplexer ................................................. 7-40
45128
8-lnput Multiplexer with 3-State Output .................................. 7-156
45398
Dual 4-lnput Multiplexer ................................................. 7-195
Analog Switches and Multiplexers/Demultiplexers
40168
Quad 8ilateral Switch .................................................... 7-30
40518
8-Channel Analog Multiplexer/Demultiplexer ............................. 7-105
40528
Dual 4-Channel Analog Multiplexer/Demultiplexer ........................ 7-108
40538
Triple 2-Channel Analog Multiplexer/Demultiplexer ....................... 7-111
40668
Quad 8ilateral Switch ................................................... 7-114
40678
16-Channel Analog Multiplexer/Demultiplexer ............................ 7-117
47418
4 x 4 Cross Point Switch .......... , ....................................... 7-261
Latches
40428
40448
45118
45438
47238
47248
401748
401758

Quad D Latch ............................................................ 7-81
Quad R/S Latch with 3-State Output ...................................... 7-88
8CD to 7-Segment Latch/Decoder/Driver ................................ 7-149
8CD to 7-Segment Latch/Decoder/Driver for Liquid Crystals .............. 7-197
Dual 4-8it Addressable Latch ....................................... ,. '" 7-246
8-8it Addressable Latch ................................................. 7-250
Hex D Flip-Flop ......................................................... 7-279
Quad D Flip-Flop ........................................................ 7-282

Translators
41048
Quad Low Voltage to High Voltage Translator with 3-State Output ......... 7-142
Arithmetic Operators
40088
4-8it 8inary Full Adder ................................................... 7-17
45278
8CD Rate Multiplier ..................................................... 7-183
400858
4-8it Magnitude Comparator ............................................. 7-265
NAND Gates
40118
Quad 2-lnput NAND Gate ................................................. 7-19
40128
Dual 4-lnput NAND Gate .................................................. 7-19
40238
Triple 3-lnput NAND Gate ................................................ 7-49
40938
Quad 2-lnput NAND Schmitt Trigger ..................................... 7-140
AND Gates
40818
Quad 2-lnput AND Gate ................................................. 7-135

3-4

SELECTOR GUIDE BY FUNCTION

FUNCTION

DESCRIPTION

PAGE

NOR Gates
4001,8
Quad 2-lnput NOR Gate .................................................. 7-11
40028
Dual 4-lnput NOR Gate ................................................... 7-11
40258
Triple 3-lnput NOR Gate .................................................. 7-53
OR Gates
40718
Quad 2-lnput OR Gate .................................................. 7-125
Inverters
40498
40508
4069U8
400978
400988

and Buffers
Hex Inverting 8uffer .....................................................
Hex Non-Inverting 8uffer ................................................
Hex Inverter ............................................................
3-State Hex Non-Inverting 8uffer ........................................
3-State Hex Inverting 8uffer .............................................

Complex
4007U8
40308
40708
40868
40938
400148

Gates
Dual Complementary Pair Plus Inverter .................................... 7-15
Quad Exclusive-OR Gate ................................................. 7-64
Quad Exclusive-OR Gate ................................................ 7-124
4-Wide, 2-lnput AND-OR-Invert Gate .................................... 7-138
Quad 2-lnput NAND Schmitt Trigger ..................................... 7-140
Hex Schmitt Trigger ..................................................... 7-263

7-102
7-102
7-122
7-269
7-269

Flip-Flops
40138
40278
40768
401748
401758

Dual D Flip-Flop .......................................................... 7-21
Dual JK Flip-Flop ......................................................... 7-54
Quad D Flip-Flop with 3-State Output .................................... 7-128
Hex D Flip-Flop ......................................................... 7-279
Quad D Flip-Flop ........................................................ 7-282

Memories
47038
47108
47208
47258
65088

FIFO 8uffer Memory .................................................... .
Register Stack 16 x 4-8it RAM with 3-State Output Register ............. .
256-8it RAM with 3-State Output ......................................... .
64-8it RAM with 3-State Output .......................................... .
1024-8it (1024 x 1) CMOS RAM with 3-State Output .................... .

7-214
7-229
7-234
7-254
7-297

Frequency Generator
47028
Programmable Bit Rate Generator ....................................... 7-206
Multivibrators, Phase-Locked Loops, Timers
40468
Micropower Phase-Locked Loop .......................................... 7-93
40478
Low-Power Monostable/Astable Multivibrator .............................. 7-98
45288
Dual Retriggerable Resettable Monostable Multivibrator .................. 7-185
47228
Programmable Timer/Counter ............................................. 7-237

3-5

•

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•·. . •.·• . . . .·.·.0
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~~~~.····/iii

FAIRCHILD 4000
SERIES CMOS

ISOPLANAR C
The Fairchild CMOS logic family uses Isoplanar C for high
performance. This technology combines local oxidation
isolation techniques with silicon gate technology to achieve
an approximate 35% to 100% savings in area as shown in
Figure 4-1a. Operating speeds are increased due to the
self-alignment of the silicon gate and reduced sidewall capacitance.

GENERAL DESCRIPTION - Fairchild CMOS logic combines popular 4000 series functions with the advanced
Isoplanar C process. The result is a logic family with a
superior combination of noise immunity and standardized
drive characteristics. Under static conditions, these devices
dissipate very low power, typically 10 nW per gate. The
low power combined with the wide (3 to 15 Vl recommended operati ng supply voltage requirement greatly
minimizes power supply costs. The CMOS family is
designed with standardized output drive characteristics
which, combined with relative insensitivity to output
capacitance loading, simplify system design.

Conventional CMOS circuits are fabricated on an n-type
substrate as shown in Figure 4-1 b. The p-type substrate
required for complementary n-channel MOS is obtained by
diffusing a lightly doped p-region into the n-type substrate.
Conventional CMOS fabrication requires more chip area
and has slower circuit speeds than Isoplanar C CMOS. This
is a result of the n+ or p+ channel stop which surrounds
the p- or n-channels respectively in conventional metal
gate CMOS. Silicon gate CMOS (Figure 4-1cl has a negligible
reduction in area, though transient performance is improved.

•
•

LOW POWER - TYPICALLY 10 nW PER GATE STATIC
WIDE OPERATING SUPPLY VOLTAGE RANGE 3 TO 15 V RECOMMENDED
18 V ABSOLUTE MAXIMUM
• HIGH NOISE IMMUNITY
• BUFFERED OUTPUTS STANDARDIZE OUTPUT DRIVE
AND REDUCE VARIATION OF PROPAGATION DELAY
WITH OUTPUT CAPACITANCE
• WIDE OPERATING TEMPERATURE RANGE
COMMERCIAL
-40o C TO +85°C
MI LITARY
-55°C TO +125°C
• HIGH DC FAN OUT - GREATER THAN 50
POLYSIUCON

AI

N -SUBSTRATE

Fig. 4-1 •. ISOPLANAR C CMOS STRUCTURE
REDUCES AREA 35%

\
N-SUBSTRATE

N -SUBSTRATE

Fig. 4-1b. CONVENTIONAL METAL GATE CMOS STRUCTURE

Fig. 4-1c.

4-3

CONVENTIONAL SILICON GATE CMOS STRUCTURE
REDUCES AREA 8%

•

FAIRCHILD 4000 SERIES CMOS
FULLY BUFFERED CONFIGURATION DESCRIPTION
Fairchild CMOS logic is designed with the system user in mind. Output buffering is used on all devices to achieve high
performance, standardized output drive, highest noise immunity and decreased ac sensitivity to output loading. Figure4-2
illustrates a conventional unbuffered 2-lnput NOR Gate. Either n-channel transistor connected to VSS (ground) conducts
when either input is HIGH, causing the output to go LOW through the ON resistance of the device. If both inputs are HIGH,
both n-channel devices are on; effectively halving the ON resistance, thereby making the output impedance (and hence fall
time) a function of input variables. Similarly the p-channel devices are switched on by LOW signals; i.e., when both inputs are
LOW, conduction from VDD to the output will occur.
Since the p-channel devices are in series, their ON resistance must be decreased (larger chip area) to hold output HIGH
impedance within specification. As the number of gate inputs increases, even larger p-channel devices are required, and the
output impedance to VSS becomes even more pattern sensitive.
A conventiona.1 unbuffered CMOS 2-lnput NAND Gate interchanges the parallel and serial transistor gating to achieve the
NAND function (Figure 4-3)_ The changes in output resistance then move to the p-channel transistors connected to V DO'
while the n-channel devices must be increased in size due to their serial connection.
Fairchild CMOS uses small geometry logic transistors to generate the required function which drive standard low impedance
output buffers (Figures 4-4 and 5). This technique reduces chip size, since only two large output transistors are required and
rise and fall times are independent of input pattern. Buffered outputs also increase system speeds and. make propagation delay
less sensitive to output capacitance. Figure 4-6 illustrates typical propagation delay vs. output capacitance for conventional
and buffered CMOS Gates_
Another advantage of the Fairchild approach is improved noise immunity. Because of the increased voltage gain, nearly ideal
transfer characteristics are realized as shown in Figure 4-7. The high gain (greater than 10,000) also provides significant pulse
shaping; the waveforms of Figures 4-8 and 9 compare the output waveforms of conventional and buffered CMOS gates. For
input transition times of 100 ns or less, the outputs of both gate types are similar. When the input transitions are stretched to
one microsecond, the conventional gate exhibits increased transition times while the buffered gate has unchanged output
transition times. This feature eliminates progressive deterioration of pulse characteristics in a system. The combination of
Isoplanar C and buffered outputs results in new standards of CMOS logic performance.

OUTPUT

OUTPUT

~=Do--OUTPUT

~

=Do--

OUTPUT

Vss

Fig. 4-3.

Fig. 4-2. CONVENTIONAL NON-BUFFERED
2-INPUT NOR GATE

CONVENTIONAL NON-BUFFERED
2-INPUT NAND GATE

AQ----.-.,

Fig. 4-4. FAIRCHILD 4001B FULLY BUFFERED NOR GATE

Fig. 4-5. FAIRCHILD 4011B FULLY BUFFERED NAND GATE

4-4

FAIRCHILD 4000 SERIES CMOS

Fig. 4·6

Fig. 4·7

COMPARISON OF PROPAGATION
DELAY VS LOAD CAPACITANCE FOR
CONVENTIONAL AND FULLY
BUFFERED NAND GATES

TYPICAL VOLTAGE TRANSFER
CHARACTERISTICS FOR
CONVENTIONAL AND FULLY
BUFFERED DEVICES

.300r-~---r--r-~---r--r--.r-~

c

Cl

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~

~

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I

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o

o

5.0

VIN -

;
,

-,

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J

10

15

INPUT VOLTAGE -

V

Fig. 4·8

Fig. 4·9

POSITlVE·GOING INPUT RAMPS OF
O.l!'s AND 1.0!,s APPLIED TO
CONVENTIONAL AND FULLY
BUFFERED GATES

NEGATlVE·GOING INPUT RAMPS OF
0.1 !'sAND 1.0!,sAPPLIED TO
CONVENTIONAL AND FULLY
BUFFERED GATES

I
6.0

25°C

1

~ CONVENTIONAL

I-

50~.s~,r--+--+---r--T-~--~

~

DEVICE_

,V

10

0..

0..

,TA

1

~V

::;)

o

~ 15 V

N~ULLY BUFFERED

w

w

!

DD

I 15

__~-+--4

o

....

J

>

I

SZ50~-+--t--+--t-~

6.0

~+~--+--+--f---t--t--t----t---

o
TIME -~.

4-5

,FUL~ Y B~JRED CMOS

1.0 /" INP

0.2

V \

0.4
0.6
TIME -1'5

0.8

1.0

DESIGN CONSIDERATIONS WITH FAIRCHILD
4000B SERIES CMOS

DESIGN CONSIDERATIONS
WITH FAIRCHILD 4000B SERIES CMOS

INTRODUCTION

the more familiar DTL/TTL (Figure 5-1). The TTL to CMOS
Comparison Guide in Section 3 lists numerous CMOS circuits
that are pinout identical to their TTL counterparts, others that
are functionally identical only, still others that are similar and,
in most cases, offer added features.

Complementary MOS digital logic building blocks of SSI and
MSI complexity have been hailed as the ideal logic family.
They are rapidly gaining popularity as more and more
manufacturers introduce increasing numbers of parts at
reasonable prices.

CMOS speed is comparable to 74L-TTL and DTL, and about
three to six times slower than TTL or Low Power Schottky
(LS-TTL). Voltage noise immunity and fan out are almost
ideal, supply voltage is noncritical, and the quiescent power
consumption is close to zero-several orders of magnitude lower
than for any competing technology.

Originally designed for aerospace applications, CMOS now
finds its way into portable instruments, industrial and medical
electronics, automotive applications and computer peripherals,
besides dominating the electronic watch market.
In late 1973, Fairchild introduced the Fairchild 4000B CMOS
family, using Isoplanar technology to achieve superior
electrical performance. Most of these devices are functional
equivalents and pin·for-pin replacements of the well-known
4000 series; some are equivalent to TTL circuits and some are
proprietary logic designs.

POWER CONSUMPTION
Under static conditions, the p-channel (top) and the n-channel
(bottom) transistors are not conducting simultaneously, thus
only leakage current flows from the positive (VDD) to the
negative (VSS) supply connection. This leakage current is
typically 0.5 nA per gate, resulting in very attractive low
power consumption of 2.5 nW per gate (at 5 V).

A few CMOS devices, such as bidirectional analog switches,
exploit the unique features of CMOS technology; some take
advantage of the smaller device size and higher potential
packing density to achieve true LSI complexity; but most of
the available CMOS elements today are of SSI and MSI complexity and perform logic functions that have been available in
DTL or TTL for many years. Therefore, it is both helpful and
practical to compare the performance of CMOS with that of

PARAMETER

Whenever a CMOS circuit is exercised, when data or clock
inputs change, additional power is consumed to charge and
discharge capacitances (on-chip parasitic capacitances as well
as load capacitances). Moreover, .there is a short time during
the transition when both the top and the bottom transistors
are partially conducting. This dynamic power consumption is

FAIRCHILD
4000B
CMOS
10 V SUPPLY

DTL

LOW POWER
SCHOTTKY

33 ns

30 ns

5 ns

40 ns

20 ns

35 MHz

3MHz

5MHz

45 MHz

BMHz

16MHz

10nW

10 nW

STANDARD
TTL

74L

10 ns

FLIP-FLOP TOGGLE FREQUENCY
QUIESCENT POWER (GATE)

PROPAGATION DELAY (GATE)

FAIRCHILD
4000B
CMOS
5V SUPPLY

----

-

------~--~

-----~------

10mW

1 mW

B.5mW

2mW

NOISE IMMUNITY

1V

1V

1V

O.BV

2V

4V

FAN OUT

10

10

B

20

50'

50'

'OR AS DETERMINED BY ALLOWABLE PROPAGATION DELAY
Fig.5-1 CMOS COMPARED TO OTHER LOGIC FAMILIES

5-3

obviously proportional to the frequency at which the circuit is
exercised, to the load capacitance and to the square of the
supply voltage. As shown in Figure 5·2, the power
consumption of a CMOS gate exceeds that of a Low Power
Schottky gate somewhere between 500 kHz and 2 MHz of
actual output frequency.

SUPPLY VOLTAGE RANGE
CMOS is guaranteed to function over the unprecedented range
of 3 to 15 V supply voltage. Characteristics are guaranteed for
5,10 and 15 V operation and can be extrapolated for any
voltage in between. Operation below 4.5 V is not very mean·
ingful because of the increase in delay (loss of speed), the
increase in output impedance and the loss of noise immunity.
Operation above 15 V is not recommended because of high
dynamic power consumption and risk of noise spikes on the
power supply exceeding the breakdown voltage (typ>20 V),
causing SCR·latch·up and destroying the device unless the
current is externally limited.

At 100 transitions per second, the dynamic power
consumption is far greater than the static dissipation; at one
million transitions per second, it exceeds the power
consumption of LS·TTL. Comparing the power consumption
of more complex devices (MSI) in various technologies may
show a different result. In any complex design, only a small
fraction of the gates actually switch at the full clock
frequency, most gates operate at a much lower average rate
and consume, therefore, much less power.

The lower limit of power supply voltage, including ripple, is
determined by the required noise immunity, propagation delay
or interface to TTL. The upper limit of supply voltage, includ·
ing ripple and transients, is determined by power dissipation or
direct interface to TTL. The 4049B, 40508, 4104B, 40097B
and 40098B provide level translation between TTL and CMOS
when CMOS supply voltages over 5 V are used. While devices
are usable to 18 V, operation above 12 V is discouraged for
reasons of power dissipation.

A realistic comparison of power consumption between
different technologies involves a thorough analysis of the
average switching speed of each gate in the circuit. The small
static supply current, IDD is specified on individual data sheets
for 5,10 and 15 V. The dynamic power dissipation for 5,10
and 15 V, 15 and 50 pF may be found in graph form for
frequencies of 100 Hz to 10 MHz. The total power may be
calculated, PT= (lDD X VDD) + dynamic power dissipation.

Low static power consumption combined with wide supply
voltage range make CMOS the ideal logic family for battery
operated equ ipment.

Fig. 5·2
TYPICAL POWER DISSIPATION
VERSUS INPUT FREQUENCY FOR
SEVERAL POPULAR LOGIC FAMILIES

1000
w~

~

Cli
ffi ~E

10

~~~~~€~ig~~~~~j

o~ i=
~ 1.0~~~~;;~~~D~~~~--J
~:il

!!: ffi 1 0-11---+-7'4:s.-~1---l----l-~'<-l
140
-0

~

2 100
2 80
21I ~ 80

S

.... e(

Hi

40

0.

20

"a:

\

\

,/'

\ \\

\K

-- ~
--....-

ILl

- --f\.' - -- f--

f-- I-"

~-

I--

I~LH

CL= 15 pF

Fig.5·6b
PROPAGATION DELAY
VERSUS AMBIENT TEMPERATURE
WITH VOD = 10 V
100

1

.
c

V6Dl10~-

80
tPHL

>

S
w

~ CL = 10~ pF t - CL=50 pF_
V -I I'

Q

80

2
0

i=
e( 40

vC = 15 pF

......
.'\ ~ ~
...........
I ' r- r--

~CL= 50 p~

25
125
TA - AMBIENT TEMPERATURE - °c

TA'= 25 c_

'j

20

0.:--,,=-- ;.

1\
l=.--'F -

~55

Fig.5·5b
NEGATIVE·GOING PROPAGATION
DELAY VERSUS POWER SUPPLY VOLTAGE
200

.,

80

CI

c~ = 1'00 ~F

j1,

2100

00 2.0 4.0 6.0 8.0 10 12 14 16
VOO - POWER SUPPLY VOLTAGE - V

CI c160

tPHL

~ 120

vCL=50 pF

~ 5.0IV_

1 1 1

f! 160
> 140

tY.:

180

V6D

180

CI
e(

0.

-

0

a:

20

0.

CL = 100 pF

l~

--- -- --:::
'7
- -~I
= _'\..

,(1

~ct; 50 pF

~

CL - 151;';:

o

1

~

tPLH

-55
25
TA - AMBIENT TEMPERATURE -

00 2.0 4.0 8.0 8.0 10 12 14 18
VDD - POWER SUPPLY VOLTAGE - V

5-6

125
°C

CMOS delays increase with temperature. They are very
sensitive to capacitive loading but can be reduced by increasing
the supply voltage to 10 or even 15 V.

Unfortunately these impressive noise margin specifications
disregard one important fact: the output impedance of CMOS
is 10 to 100 times higher than that of TTL. CMOS interconnections are therfore less "stiff" and much more susceptible to capacitively coupled noise. In terms of such current
injected crosstalk from high noise voltages through small
coupling capacitances, CMOS has about six times less noise
margin than TTL. It takes more than 20 mA to pull a TTL
output into the threshold region, but it takes only 3 mA to
pull a CMOS output into the threshold of a 5 V system.

To determine propagation delays, the effects of capacitive
loading, supply voltage, manufacturing tolerances and ambient
temperature must be considered. Start with the values of tpLH
(propagation delay, a LOW·to·HIGH output transition) and
tPHL (propagation delay, a HIGH·to-LOW output transition)
given in the individual data sheets. Delay values for VDO at 5,
10 and 15 V and output capacity of 50 pF is provided.
Manufacturing tolerances account for the differences between
MIN, TYP and MAX. Starting with the nearest applicable
delay value, correct for effects of capacitive loading, ambient
temperature and supply voltage using the general family
characteristics of Section 7.

The nearly ideal transfer characteristic and the slow response
of CMOS circuits make them insensitive to low voltage,
magnetically coupled noise. The high output impedance,
however, results in a poor rejection of capacitively coupled
noise.
INTERFACE TO TTL
When CMOS is operated with a 5 V power supply, interface to
TTL is straightforward. The input impedance of CMOS is very
high, so that any form of TTL will drive CMOS without loss of
fan out in the LOW state. Unfortunately, most TTL has
insufficient HIGH state voltage (typically 3.5 V) to drive
CMOS reliably. A pull up resistor (1 kQ to 10 kQ) from the
output of the TTL device to the 5 V power supply will effectively pull the HIGH state level to 4.5 V or above. Alternately,
DTL Hex inverters may be used between the TTL and CMOS.
9LS Low Power Schottky and 93LOO Low Power TTLIMSI
utilize the unique output configuration shown in Figure 5-8 to
pull its output to VCC-VBC or approximately 4.3 V when
lightly loaded.

Fig. 5-7
TYPICAL TRANSFER
CHARACTERISTICS FOR TTL AND CMOS

6

TA = +25°C
SUPPLY VOLTAGE = 5 V

'"

4000B
CMOS

7400\

TTL

2

4

All Fairchild 4000B logic elements will drive a single 9LS Low
Power Schottky input fan in directly. A 9LS Hex inverter such
as the 9LS04 makes an excellent low cost TTL buffer with a
fan out of 20 into 9LS or 5 into standard TTL. Alternately,
the 4049B and 4050B Hex buffers may be used to drive a fan
out of 8 into 9LS or 2 into standard TTL.

6

INPUT VOLTAGE - V

NOISE IMMUNITY
One of the most advertised and also misunderstood CMOS
features is noise immunity. The input threshold of a CMOS
gate is approximately 50% of the supply voltage and the
voltage transfer curve is almost ideal. As a result, CMOS can
claim very good voltage noise immunity, typically 45% of the
supply voltage, i_e., 2.25 V in a 5 V system, 4.5 V in a 10 V
system. Compare this with the TTL transfer curve in Figure 5-5
and its resultant 1 V noise immunity in a lightly loaded
system and only 0.4 V worst case.

When operating CMOS at voltage higher than 5 V direct
interface to TTL cannot be used. The 4104B Quad Level
Translator converts TTL levels to high voltage CMOS up to
15 V. The 4049B and 4050B Hex Buffers will accept high
voltage CMOS levels up to 15 V and drive 2 standard
TTL loads.
Vee

KEY TO OUTPUT HIGH LEVEL
IS THE RESISTOR RETURNED
TO THE OUTPUT RATHER

Since CMOS output impedance, output voltage and input
threshold are symmetrical with respect to the supply Voltage,
the LOW and HIGH level noise immunities are practically
equal. Therefore, a CMOS system can tolerate ground or VDD
drops and noise on these supply lines of more than 1 V, even
in a 5 V system. Moreover, the inherent CMOS delays act as a
noise filter; 10 ns spikes tend to disappear in a chain of CMOS
gates, but are amplified in a chain of TTL gates. Because of
these features, CMOS is very popular with designers of industrial control equipment that must operate in an electrically
and electromagnetically "polluted" environment.

THAN GROUND
OUTPUT

Fig. 5-8
THE 93LOO AND 9LSOO TTL FAMILIES
WILL DRIVE CMOS DIRECTLY WITHOUT RESISTORS AS LONG AS
THERE ARE ONLY CMOS DEVICES
BEING DRIVEN FROM THE OUTPUT.

5-7

INPUT/OUTPUT CAPACITY

HANDLING PRECAUTIONS

CMOS devices exhibit input capacities in'the 1.5 to 5 pF range
and output capacity in the 3 to 7 pF range.

All MOS devices are subject to damage by large electrostatic
charges. All Fairchild 4000B devices employ the input
protection described in Figure 5-9, however, electrostatic
damage can still occur. The following handling precautions
should be observed.

OUTPUT IMPEDANCE
All Fairchild 4000B logic devices employ standardized output
buffers. Section 7 details output characteristics. It should be
noted that these impedances do not change with input pattern
as do conventional CMOS gates, Buffers, analog switches and
analog multiplexers employ special output configurations
which are detailed in individual data sheets.

1. All Fairchild 40008 devices are shipped in conducting
foam or antistatic tubes. They should be removed for
inspection or assembly using proper precautions.
2. Ionized air blowers are recommended when automatic
incoming inspection is performed.
3. Fairchild 40008 devices, after removal from their shipping
material, should be placed leads down on a grounded
surface. Conventional cookie tins work well. Under no
circumstances should they be placed in polystyrene foam
or plastic trays used for shipment and handling of
conventional ICs.
4. Individuals and tools should be grounded before coming in
contact with 4000B devices.
5. Do not insert or remove devices in sockets with power
applied. Ensure power supply transients, such as occur
during power turn-on or off; do not exceed maximum
ratings.
6. In the system, all unused inputs must be connected to
either a logic HIGH or logic LOW level such as VSS' VDD
or the output of a logiC element.
7. After assembly on PC boards, ensure that static discharge
cannot occur during storage or maintenance. Boards may
be stored with their connectors surrounded with conductivefoam. Board input/output pins may be protected with
large value resistors (10 Mil) to ground.
8. In extremely hostile environments, an additional series
input resistor (10 to 100 kil) provides even better protection at a slight speed penalty.

INPUT PROTECTION
The gate input to any MOS transistor appears like a small
«1 pF) very low leakage «10- 12 A) capacitor. Without
special precautions, these inputs could be electrostatically
charged to a high voltage, causing a destructive breakdown of
the dielectric and permanently damaging the device. There·
fore, all CMOS inputs are protected by a combination of series
resistor and shunt diodes. Various manufacturers have used
different approaches; some use a single diode, others use two
diodes, and some use a resistor with a parasitic substrate diode.
Each member of the Fairchild 4000B family utilizes a series
resistor, nominally 200 il, and two diodes, one to VDD' and
the other to VSS (Figure 5-9). The resistor is a poly-silicon
"true resistor" without a parasitic substrate diode. This
ensures that the input impedance is always at least 200 il
under all biasing conditions, even when VDD is short circuited
to VSS' A parasitic substrate diode would represent a poorly
defined shunt to VSS in this particular case.
The diodes exhibit typical forward voltage drops of 0.9 V at
1 rnA and reverse breakdowns of 20 V for D1 and 20 V for
02. For certain special applications such as oscillators, the
diodes actually conduct during normal operation. However,
currents must be limited to 10 rnA.

A WORD TO THE TTL DESIGNER
Designing with CMOS is generally an easy transition and allows
the designer to discard many of the old design ,inhibitions for
new found freedoms. A few of these are:
Fan out-It is practically unlimited from a dc point of view
and is restricted only by delay and rise time considerations.

VDD

200n

~D2

Power Supply Regulation-Anything between 3 V and 15 V
goes, as long as all communicating circuits are fed from the
same voltage.

NOMINAL

INPUT

<>--.J\I"""--....--~-- ~~i~~~;ORS

Ground and VCC Line Drops-The currents are normally so
small that there is no need for heavy supply line bussing.
VCC Decoupling-It can be reduced to a few capacitors per
board.
Fig. 5-9
4000B SERIES CMOS
INPUT PROTECTION CIRCUIT

Heat Problems-They do not exist, unless an attempt is made
to run CMOS very fast and from more than 10 V.
It should also be noted that there are a few warnings called for
when designing with CMOS and that many of the hard-earned
good engineering basics cannot be forgotten. A few of the new
design challenges inc,lude:
5-8

Unused Inputs-They must be connected to VSS or VDD
(VCC or ground) lest they generate a logical "maybe". The
bad TTL habit of leaving unused inputs open is definitely out.

Both TTL and CMOS tolerate deviations from the ideal LOW
and HIGH input voltages. TTL is therefore specified as
follows:
MIN

Oscillations-Slowly rising or falling input signals can lead to
oscillations and multiple triggering. A poorly regulated and
decoupled power supply magnifies this problem since the
CMOS input threshold varies with the supply voltage.

MAX

2.0
0.8

v
v

Any voltage below 0.8 V is considered LOW; any voltage
above +2.0 V is considered HIGH. The actual threshold is
somewhere in between these values, depending on manufac·
turing tolerances, supply voltage, and temperature.

Timing Details-Even slow systems require a careful analysis of
worst case timing delays, derated for maximum temperature,
minimum supply voltage and maximum capacitive loading.
Many CMOS flip·flops, registers and latches have a real hold
time requirement, i.e., inputs must remain stable even after the
active clock edge; some require a minimum clock rise time.
This hasn't been a problem with TTL. CMOS systems, even
slow ones, are prone to unsuspected clock skew problems,
especially since a heavily loaded clock generator can have a
poor rise time.

Fairchild's 4000B CMOS is specified in a similar way. For
V DD = 5 V;
MIN

MAX

3.5

V

1.5

V

The CD4000 data sheets, on the other hand, do not call out
VIH and VIL but specify a "noise immunity" which is some'
what arbitrarily defined relative to the appropriate supply
voltage.

Compatibility-The TTL· designer knows that devices sold by
different manufacturers under the same generic part number
are electrically almost identical. Many semiconductor houses
manufacture 4000-type devices with wide variations in output
drive capability and speed. Sometimes even the functions are
different and incompatible; two cases in point are the 1·of·l0
decoder (CD4028A and MC14028) and the magnitude
comparator (MC14585 and MM74C85).

VNL = VIL
VNH = VDD - VIH
For VDD = 5 V, therefore
VNL = 1.5 V min is equivalent to VIL = 1.5 V max
VNH = 1.4 V min is equivalent to V IH = 3.6 V min, etc.
Systems Oriented MSI-Available CMOS circuits, especially the
original 4000 series, are not as well suited for synchronous
systems as are the 9300/7400 TTL families. Control polarities
are inconsistent; many circuits cannot be cascaded or extended
synchronously without additional gates, etc. This will improve
as more good synchronous building blocks, like the 40160B
are introduced.

Data Sheet Format-The original CMOS data sheets may
appear confusing to the TTL user because a range of input
voltage requirements is not specified. Rather, this information
is contained in a "noise immunity" specification and is not
immediately obvious.

5-9

JEDECINDUSTRYSTANDARD"B"
SERIES CMOS SPECIFICATIONS

JEDEC Industry Standard "8" Series
CMOS
Throughout first half of 1976 the CMOS vendor industry, in total, was invited to participate in the generation
of a new JEDEC Industry Standard CMOS "8" Series specification. Unanimous agreement was reached and
confirmed by industrywide ballot in late 1976.
This section is meant to extend knowledge of the new Industry Standard "8" Series CMOS specification
to the customer and ensure that all Fairchild CMOS products meet or exceed all specifications of the new
JEDEC standard.
In fact, since first introduction of the Isoplanar CMOS Family in 1973, all Fairchild CMOS products have
been designed and tested to meet or exceed the more recently announced JEDEC specifications. The
following is a compilation of the definitions and parametric specifications as listed in the J EDEC "Standard
Specifications for description of '8' Series CMOS devices".

•

6-3

(Formulated under the cognizance of th JEDEC JC-40.2 Committee on CMOS Standardization)

1. PURPOSE AND SCOPE

1. Purpose
To develop a standard of "8" Series CMOS Specifications to provide for uniformity, multiplicity of sources,
elimination of confusion, and ease of device specification and system design by users.
1.2 Scope
This Tentative Standard covers standard specifications for description of "8" Series CMOS devices.

2. DEFINITIONS
2.1 "8" Series
"8" Series CMOS includes both buffered and unbuffered devices.
2.2 "8uffered"
A buffered output is one that has the characteristic that the output "on" impedance is independent of any
and all valid input logic conditions, both preceding and present.

3. STANDARD SPECIFICATIONS
3.1 Listing of Standard DC Specifications. Table 6-2 lists the standard dc specifications for "8" Series
CMOS devices.
3.2 Absolute Maximum Ratings. In the maximum ratings listed below voltages are referenced to VSS.
ABSOLUTE MAXIMUM RATINGS

DC Supply Voltage
Input Voltage
DC Input Current
(anyone input)
Storage Temperature Range

VDD
VIN
liN

-0.5 to +18
-0.5 to VDD +0.5
±10

Vdc
Vdc
mAdc

TS

-65 to +150

°c

3.3 Recommended Operating Conditions. Recommended operating conditions are listed below.
RECOMMENDED OPERATING CONDITIONS

DC Supply Voltage
Operating Temperature Range
Military-Range Devices
Commercial-Range Devices

VDD
TA

+3to+15
-55 to +125
-40 to +85

6-4

Vdc

3.4 Designation of "B" Series CMOS Devices
Those parts which have analog inputs and/or outputs shall be included in the "B" Series providing those
parts' maximum ratings and logical input and output parameters conform to the "B" Series, such as (including, but not limited to):
Schmitt Triggers
Analog Switches and Multiplexers
One Shot Multivibrators and Oscillators
4511 B BCD to 7-Segment LatchlDecoder/Driver
4046B Micropower Phase Lock Loop
Products that meet "B" Series specifications except that the logical outputs are not buffered and the VI L
and VIH specifications differ from "B" series as shown in Table 6-1 shall be marked with the UB designation, such as (including, but not limited to):
4007UB
4069UB

Table 6-1. INPUT VOLTAGE LEVELS FOR "UB" PRODUCTS
PARAMETER

VIL
(max)

Input LOW

TEMP

LIMITS

RANGE

VDD
(Vdc)

All

5

Vo=
0.5 V or 4.5 V

1

1

1

10

1.0 V or 9.0 V

2

2

2

1 .5 V or 13.5 V

2.5

2.5

2.5

Voltage

15

CONDITIONS

how

2Sc C

UNITS
THIGH
V

1101< 1 p.A

VIH
(min)

Input HIGH
Voltage

All

5

VO=
0.5 V or 4.5 V

10

1.0 V or 9.0 V

15

1.5 V or 13.5 V

1101< 1 p.A

6-5

4

4

4

8
12.5

8

8

12.5

12.5

V

•

Table 6-2_ STANDARDIZED "B" SERIES CMOS SPECIFICATIONS
SYMBOL

PARAMETER

Quiescent

Device Current

TEMP.

LIMITS

RANGE

VOO
(Vde)

Mil

10

CONDITIONS

TLOW"
MIN
MAX

5
VIN = VSS or VOO

15
5

GATES

Comm

10

All valid input combinations

15
5
Mil
BUFFERS,
100

10

VIN = VSS or VOO

15

FLIP-FLOPS

5
Comm

10

All valid input combinations

15
5
Mil

10

VIN = VSS or VOO

15

MSI

5
Comm

10

All valid input combinations

15
LOW·Level
VOL

Output Voltage

HIGH-Level
VOH

Output Voltage

Input LOW
VIL***

Voltage

Input HIGH
VIH***

Voltage

5
All

10
15
10
15
5

All

10
15
5

All

10
15

Output LOW
(Sink) Current

Output HIGH
(Source) Current

3-State
Output
10Z

Leakage
Current
I nput Capacitance

GIN

per Unit Load

1101

<

1,uA

VO=1.5Vor13.5V
1101

<

1 p.A

30
7.5

1

1

2

2

15

4

4

30

1

1

30

2

2

60

4

4

120

4

4

30

8

8

60

16

16

120

5

5

150

10

10

300

20

20

600

20

20

150

40

40

300

80

80

600

0.05

0.05

0.05

0.05

0.05

0.05

0.05

0.05

0.05

4.95

4.95

14.95

14.95

9.95
14.95

1 p.A

VO= 1 V or9 V

1

9.95

Vo = 1.5 V or 13.5 V
VO= 0.5 V or 4.5 V

15

1

9.95

Va = 0.5 V or 4.5 V

<

7.5

0.5

4.95

VO= 1 V or9 V
1101

0.25

0.5

1.5

3

3

3

4

4

4

3.5

3.5

7

7

,uAde

,uAde

,uAde

,uAde

,uAde

Vde

7

11

11

11
0.36

Vde

3.5

1.3

0.9

15

VO=1.5V,VIN=00r15V

4.2
0,52

3.4

2.4

0.44

0.36

VO- O.4V, VIN -Oor 5 V

,uAde

1.5

0.51

VO-O.4V,VIN-OorSV

UNITS

Vde

1.5

1.6

10

Vo = 0.5 V, VIN = 0 or 10 V

1.3

1.1

0.9

15

VO= 1.5V, VIN =Oor 15 V

3.6

3

2.4

Vo = 4.6 V, VIN = 0 or 5 V

-0.25

-0.2

-0.14

10

VO=9.5V,VIN=00r10V

-0.62

-0.5

-0.35

15

Vo = 13.5 V, VIN = 0 or 15 V

-1.8

-1.5

-1.1

Vo = 4.6 V, VIN = 0 Or 5 V

-0.2

-0.16

-0.12

10

VO=9.5 V, VIN = Oor 10V

-0.5

-0.4

-0.3

15

VO=13.5V,VIN=00r15V

-1.4

-1.2

-1

5
Comm

VIN = VSS or VOO

0.25

0.64

5
Mil

Input Current

1,uA

THIGH""
MIN
MAX

VO= 0.5 V, VIN =Oor 10V

5
Comm

liN

<

MAX

10

5

10H

1101

5
All

Mil
10L

VIN = VSS or VOO

+25'C
MIN

Vde

mAde

mAde

mAde

mAde

Mil

15

VIN=00r15V

±0.1

±0.1

±1

Comm

15

VIN =Oor 15 V

±0.3

±0.3

±1

Mil

15

Vo=OVor15V

±0.4

±0.4

±12

Comm

15

Vo=OVor15V

±1.6

±1.6

112

All

-

Any input

p.Ade

p.Ade

7.5

*TLOW = _55°C for Military Temp. Range device, _40°C for Commercial Temp. Range device
'" "'THIGH = +125°C fc;>r Military Temp. Range device, +85 b C for Commercial Temp. Range device
.. '" '" V I L and V I H specifications apply to worst case input combinations.

6-6

pF

3.5 Listing of Standard A C (Dynamic) Test Methods and Definitions.

Figure 6-1 shows the standard AC (Dynamic) test configuration and conditions. Dynamic electrical symbols
and parametric definitions are listed in Table 6-3. Figures 6-2 through 6-5 show standard AC characteristic
test waveforms.

Fig. 6-1 TEST CONFIGURATION AND CONDITIONS

~"'

DEVICE
UNDER
TEST

N
INPUTS

50 pF
200 k
25°C

Cl
Rl
TA
VDD
tr = tf

K
OUTPUTS

n

5,10,15 V
20 ns

=

Table 6-3. DYNAMIC ELECTRICAL SYMBOLS AND DEFINITIONS

CHARACTERISTIC

LIMITS

SYMBOL
MAX.

PROPAGATION DELAY:
Outputs going HIGH-to-LOW
Outputs going lOW-to-HIGH

NOTES
MIN.

X

tpHL
tpLH

X

tTHL
tTLH

X
X

OUTPUT TRANSITION TIME:
Outputs going HIGH-to-lOW
Outputs going LOW-to-HIGH
PULSE WIDTH - Set, Reset, Preset,
Enable. Disable. Strobe. Clock

tWL or tWH

X

1

CLOCKINPUTFREaUENCY

FCL

X

1.2

X

CLOCK INPUT RISE & FALL TIME

trCl. tfCL

SET-UP TIME

tsu

X

1

HOLD-TIME

tH

X

1

REMOVAL TIME - Set. Reset. Preset. Enable

tREM

X

1

THREE STATE DELAY TIMES:
HIGH level:to-tligh impedance
High impedance-to-LOW level
lOW level-to-high impedance
High impedance-to-HIGH level

tpHZ
tpZL
tpLZ
tpZH

i

X
X
X

X

NOTES:
1) By placing a defining min or max in front of definition, the limits can change from min to max, or vice versa.
2) Clock input waveform should have a 50% duty cycle and be such as to cause the outputs to be switching from 10% VDD to 90% VDD in
accordance with the device truth table.

6-7

•

Fig. 6-2 TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATIONAL LOGIC

==

='-=---=-90%VOO

INPUT

-

-----50%

-10%
I'---------VSS

_
INVERTING
OUTPUT

-90% VOO

---50%

Fig •. 6-3 CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH*

CLOCK

_-_
_
-_
-,;.;10;,;.;%VSS

.....I - - - - t w H - - - . j

1~._---tWL--_

·Outputs should be switching from 10% VDD to 90% VDD in accordance with device truth table.

&-8

Fig.6-4 SETUP TIMES. HOLD-TIMES. REMOVAL TIME. AND PROPAGATION DELAY TIMES FOR POSITIVE EDGE-TRIGGERED
SEQUENTIAL LOGIC CIRCUITS.

i--=

trCL

VDD

,..------,.---

-~

-

_90%

-----50%

CLOCK
INPUT

_ _ _ 10%

VSS

, -_ _ _ _ _ VDD

-

-50%

'---+'---------- - - - - - - - - - V S S
~VDD

'THL
-

_

-

_

-OUTPUT

-

-

-

-

_ _ _ 90%

---50%
_10%

VSS

SET RESET ENABLE

VDD

OR PRESET

i-

50%-

*(LH) OR (HL) OPTIONAL

'cem

-

~------------------------VSS

6-9

•

r. -----------9o-o/,-.'\l1
--i
Fig.6-5

3-STATE PROPAGATION DELAY WAVEFORMS

~20nS

20ns

Voo

~1~:jfB~~

50%

10%

_-I

~-tPZL

tPLZ

-VSS

___--------"\.1 - - - - - - - - - - V O O
OUTPUT LOW
TO OFF
~--------VOL

tpHZ

---j

~

OUTPUT HIGH
TO OFF

..._ _ _ _

OUTPUTS

.~

----CONNECTEO--I~

. ; 10;.;.;.%~

VOH

_ _ _ _ _ _ VSS

I_

OUTPUTS

OUTPUTS

OISCONNECTEO---t~~r-- CONNECTEO--

Fig.6·6 THREE-STATE PROPAGATION DELAY TEST CIRCUIT

I
"

~

OTHER
INPUTS

-

"

"

OUTPUT
DISABLE

"

DEVICE
UNDER
TEST
WITH
3·STATE
OUTPUT

OUTPUT RL = 1 kr2

1
I50

"

~

CL

--

6-10

PF

{

VDD for tPLZ and tpZL
VSS for tpHZ and tpZH

As defined by the above Industry Standard Specification, Fairchild offers the following devices:
40018
40028
40068
4007U8
40088
40118
40128
40138
40148
40158
40168
40178
40198
40208
40218
40228
40238

40248
40258
40278
40288
40298
40308
40318
40348
40358
40408
40428
40448
40458
40468
40478
40498
40508
40518
40528
40538
40668
40678
4069U8

40708
40718
40768
40818
40868
40938
41048
45108
45118
45128
45148
45158
45168
45188
45208
45218
45228
45268
45278
45288
45398

45438
45558
45578
47028
47038
47108
47208
47228
47238
47248
47258
47278
47318
47348
47418
400858
400978
400988

401618
401638
401748
401758
401938
65088

•
To order Fairchild Industry Standard "8" Series CMOS ...
ORDER AND PACKAGE INFORMATION
Fairchild integrated circuits may be ordered using a simplified purchasing code where the package style and
temperature range are defined as follows:
PACKAGE CODE
D = Dual In-line - Ceramic (hermetic)
P = Dual In-line - Plastic
F = Flatpak

40018

TEMPERATURE RANGE CODE

1L
D

C

T,mp,,,,",,
Range Code

Package
Code

C = Commercial
-40°C to +85°C
M = Military
-55°C to +125°C
L -_ _ _ _ _

6-11

Device
Type (or 4007U8)

FAIRCHILD 40008 SERIES
CMOS FAMILY CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS (Non-operating) above which useful life may be impaired. All voltages are referenced to VSS.
Supply Voltage VDD
Voltage on any Input
Current into any Input
Maximum Power Dissipation

-0.5 to 18 V
-0.5 to VDD +0.5 V
. . . . ±10 mA
400rriW
-65°C to 150°C
300°C

Storage Temperature
Lead Temperature (Soldering, 10 s)

RECOMMENDED OPERATING CONDITIONS
Fairchild CMOS will operate over a recommended VDD power supply range of 3 to 15 V, as referenced to VSS (usually ground). Parametric
limits are guaranteed for VOD equal to 5, 10 and 15 V. Where low power dissipation is required, the lowest power supply voltage, consistent
with required speed, should be used. For larger noise immunity, higher power supply voltages should be specified. Because of its wide operating
range, power supply regulation and filtering are less critical than with other types of logic. The lower limit of supply regulation is 3 V, or as
determined by required system speed andlor noise immunity or interface to other logic. The recommended upper limit is 15 V or as determined
by power dissipation constraints or interface to other logic.
Unused inputs must be connected to VOO, VSS or another input.
Care should be used in handling CMOS devices; large static charges may damage the device.
Operating temperature ranges are _40° C to +85° C for Commercial and _55 0 C to +125° C for Military.

4000BXM

4000BXC
PARAMETER
Supply Voltage, VDD
Operating Free Air
Temperature Range

x

MIN

TYP

MAX
15

3

+25

+85

-55

3
-40

MIN

= Package Type; F for Flatpak, D for Ceramic DIP, P for Plastic -oIP.

7-3

UNITS

TYP

MAX
15

V

+25

+125

°c

See. Ordering Information section .

•

FAIRCHILD 4000B SERIES CMOS FAMILY CHARACTERISTICS
DC CHARACTERISTICS FOR THE 40008 SERIES CMOS FAMILY - Parametric Limits listed below are guaranteed for the entire Fairchild
CMOS Family unless otherwise specified on the individual data sheets.
DC CHARACTERISTICS: VDD = 5 V, VSS = 0 V
SYMBOL

LIMITS

PARAMETER

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

MIN

TYP

MAX

3.5
1.5
4.95

VOH

Output HIGH Voltage

0.05
0.5
-0.63

IOH

IOL

Output HIGH Current

Output LOW Cu trent

V

All

Guaranteed Input HIGH Voltage

V

All

Guaranteed Input Low Voltage

V
0.05

Output LOW Voltage

TEMP

V

4.95
4.5

VOL

UNITS

V
V
rnA

Input Capacitance

Gates
XM
Quiescent
Power

IDD

Supply

XC
Buffers and
Flip-Flops

Current

XM
XC

MSI
XM

IOH
IOL

MAX
All
MIN,25°C

MIN,
25°C
MAX

7.5
XC

All

MAX
rnA

1
7.5
0.25
7.5

4
30
1
30
20
150
5
150

7-4

pF
ILA
ILA
ILA
ILA
ILA
ILA

IOH

25°C

< 1 ILA, Inputs at 0 or 5 V

< 1ILA, Inputs at 1.5 or 3.5 V
< 1 ILA, Inputs at 0 or 5 V per

the Logic Function or Truth Table

IOL

< 1 ILA, Inputs at

1.5 or 3.5 V

VOUT4.6V

Inputs at 0 or 5 V per
the Logic Function or

VOUT=
0.4V

Truth Table

Any Input

MIN,25°C
MAX
MIN,25°C
MAX
MIN,25°C
MAX

All Inputs at 0 V or VDD for

MIN,25°C

all Valid I nput Combinations

MAX
MIN,25°C
MAX
MIN, 25°C
MAX

per

the Logic Function or Truth Table

MIN,25°C

1
0.8

Per Unit Load

MAX

-0.36

0.4
CIN

Min, 25°C

TEST CONDITIONS

FAIRCHILD 4000B SERIES CMOS FAMILY CHARACTERISTICS
DC CHARACTERISTICS: VDD = 10 V, VSS = 0 V
SYMBOL

LIMITS

PARAMETER

VIH

Input HIGH Voltage

VIL

I nput LOW Voltage

MIN

TYP

MAX

7
3
9.95

VOH

Output HIGH Voltage

Output LOW Voltage

0.05
1

IOH

-1.4

Output HIGH Current

A"

Guaranteed Input HIGH Voltage

A"
MIN,2SoC

Guaranteed Input LOW Voltage

V
V
mA

-0.8
2.6

IOL

Output LOW Current

mA

1.2
I nput Capacitance
CIN

XC
Gates
XM
Quiescent

IDD

Power

Buffers,

Supply

Flip·Flops

Current

XC
XM
XC

MSI
XM

A"
MIN,2SoC
MAX
A"
MIN,2SoC
MAX
25°C
MAX

7.5

Per Unit Load

MAX

MIN,

2

2
15
0.5
15
8
60
2
60
40
300
10
300

7-5

TEST CONDITIONS

V

V
0.05

TEMP

V

V

9.95
9

VOL

UNITS

pF
!LA
!LA
!LA
!LA
!LA
!LA

25°C

IOH

< 1 !LA, Inputs at 0 V or 10 V pe

the Logic Function or Truth Table
IOH
IOL

< 1 !LA, Inputs at 3 or 7 V
< 1 !LA, Inputs at 0 or 10 V per

the Logic Function or Truth Table
IOL

< 1!L A,Inputsat3or 7V

VOUT=
9.SV

Inputs at 0 or 10 V per
the Logic Function or

VOUT=
O.SV

Truth Table

Any Input

MIN,2SoC
MAX
MIN,25°C
MAX
MIN,2SoC
MAX

A" Inputs at 0 V or VDD for

MIN,2SoC

A" Valid Input Combinations

MAX
MIN,25°C
MAX
MIN,25°C
MAX

FAIRCHILD 4000B SERIES CMOS FAMILY CHARACTERISTICS
DC CHARACTERISTICS: VOO = 15 V, VSS = 0 V
SYMBOL

LIMITS

PARAMETER

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

VOH

Output HIGH Voltage

MIN

TYP

MAX

UNITS

TEMP

V

All

Guaranteed Input HIGH Voltage

V

All

Guaranteed Input LOW Voltage

11
4
14.95
13.5

Output LOW Voltage

V

0.05
1.5
XC

0.1

XM
-4.5

Output HIGH Current

7.5

Input Capacitance
CIN

1

XM

100

Power

Bufiers,

Supply

Flip·Flops

4

Cu rrent

Truth Table

1.5V

25°C

Any Input

MAX
MAX
MAX

All Inputs at 0 V or VOO for

MIN,25°C

all Valid Input Conditions

MAX

I"A

600

MAX
MIN,25°C

20

XM

VOUT -

MAX

MIN,25°C

80

XC

the Logic Function or

MIN,25°C

I"A

120

MSI

Inputs at 0 or 15 V per

13.5 V

MIN,25°C

I"A

120

XM

VOUT=

MAX

MIN,25°C

16

XC

I nputs at 4 or 11 V

Simultaneously at 0 or 15 V

MIN,25°C

I"A

30

I"A

600

MAX

TYPICAL FAIRCHILD 40008 SERIES CHARACTERISTICS

Fig. 7-'
POSITIVE-GOING
PROPAGATION DELAY
VERSUS SUPPLY VOLTAGE
200

~7

-I

160

gS'40
~~

80

I " 60

~~

~a:

40

"- 20
0

I\~

\

\

1"<

CL=50pF

/" r,

'x

........ ........

/e~ 0 lLF

---

200

180
C!J elS0

;!;I

~ ~120

~~

I-- !-

0 2.0 4.0 6.0 8.0 10 12 14 16
Voo - POWER SUPPLY VOLTAGE - V

CL =

i\

~ 2100
,,0

,\K
'\ I"> K

I " 60

25le_

.'80

'1

I

7160

,ob p~J:Cl'= 50 pF

V

\

80

TA 10

I I

\

g ~140

~;;:

; - r-

Fig. 7-3
POSITIVE-GOING
PROPAGATION DelAY
VERSUS LOAD CAPACITANCE

200

~I

ve~o+pJ-

\

~ ~120

E
2100
<1>0

Fig. 7-2
NEGATIVE-GOING
PROPAGATION DELAY
VERSUS SUPPLY VOLTAGE

TAl 0 2~Oe

180

-II'

V CL =15pF

I I
.......
I ' r-:t::±::

:1:0 40

e-g:

20

~

00

2.0 4.0 6.0 8.0 10 12 14 16
Voo - POWER SUPPLY VOLTAGE - V

7-6

per

All other Inputs

MAX

I"A

30

Quiescent

< 1 I"A,

MIN,25°C

4

XC

Gates

< 1 I"A, I nputs at 4 or 11 V
< 1 I" A, Inputs at 0 or 15 V

Lead under test at 0 or 15 V

MAX

pF

7.5

Per Unit Load

IOL

MIN,25°C

rnA

4.5

Inputs at 0 or 15 V per

the Logic Function or Truth Table

All

rnA

-2.7

Output LOW Current

IOL

IOH
IOL

MIN,25°C

I"A

1
IOH

All
MAX

/J.A

1

Input Current

liN

< 1 I"A,

the Logic Function or Truth Table

MIN,25°C

V

0.3

IOH

MAX

V
0.05

VOL

MIN,25°C

V

14.95

TEST CONOITIONS

-T~ o 2150e '
L.

;140

,/

1

~120

2100

0

-VDD05,O~

~ 80

";;:
0

g:

L

,/

VJ"

= 10 V

~

P

-- i
. . . .-: ----r= ,It=
o ---:r-i

60

.......-r

V

40

20

V DO

0

50

100

r--

1s

..l ..l

150

CL - LOAD CAPACITANCE - pF

200

FAIRCHILD 40008 SERIES CMOS FAMILY CHARACTERISTICS

Fig. 7-5
VOLTAGE TRANSFER
CHARACTERISTICS OVER
-55"C TO +125°C RANGE

Fig. 7·4
NEGATIVE-GOING
PROPAGATION DELAY
VERSUS LOAD CAPACITANCE
200

180

M

~

7160

r-r11

0

2~oC

VOO=15V
15

I

I
I

gS'40
~ ~120

V

V

~-

j:

.

r---;;;;

~ 40

~

10

~

~OO:O1~

g
~

-I--

v

I
6

o

50
100
160
CL - LOAD CAPACITANCE -

I

~'20
o

2100

o

'r

-

f-

f-~~L

40

CL

104

106

106

INPUT FREQUENCY -

Fig. 7-8
PROPAGATION DELAY
VERSUS AMBIENT
TEMPERATURE @ VDD ~ 10 V

107

Hz

Fig. 7-9
PROPAGATION DELAY
VERSUS AMBIENT
TEMPERATURE @ VDD 15 V

=

100'-"""~~~~~~-~"""~

Voo

1'-:
tPLH- f - f -

2&

=15V

0'-:_5:::5...L....l..--.J.....,2::!::!L:!!H_.L:C~L_=.:..,.::.!:PF:,.,J,26

125

°C

TA - AMBIENT TEMPERATURE -

~
-!...- '=
......,;,
1- -

--

~f

VGS -

f

-1.

r

w
a:
a:

::>

z

,TA = 26°C

:ca:
0

I

15

VOLTAGE - V

-6

40
30
20

10

---

/

1'"

/-

VDS.~

=15v

VGS-10V

--

10

o

iii

2
.. 80

/'

40

I:"

DRAIN TO SOURCE VOLTAGE - V

3.

I:"

20

00

/

~QQ

60

I

16

...y

t= 100

i

I

VOS-6V

TA = 25°C

j:120
2

o

i

i

~

I!'
~

T

/,l ,,-

/

/

20 40

~

~
-.100

./

.~

<,0-.1

-:::::

80

80 100 120 140 180

Cl - LOAD CAPACITANCE - pF

INPUT CIRCUITRY
All inputs are protected by the network of Figure 7-13;8 series
input resistor plus diodes 01" and 02 clamp input voltages
between VSS and VOO. Forward conduction of these diodes is
tYpically 0.9 V at 1 mAo When VSS or VOO is not connected,
avalanche breakdown of the diodes limit input voltage; 01
tYpically breaks down at 20 V, 02 at 20 V. I n normal logic

Fig. 7-13
INPUT PROTECTION CIRCUIT

2000
INPUTo-_N_O...M",I/>NA_L_--4_ _, - _

Vos

-

/ ,-'

o

Yes - DRAIN TO SOURCE VOLTAGE - V

~

Fig. 7-12
OUTPUT TRANSITION TIME
VERSUS LOAD CAPACITANCE

1140

70

u

GATE TO SOURCE

I

-10

TA - AMBIENT TEMPERATURE - °C

VGS - GATE TO SOURCE
VOLTAGE -v
E 60
TYPICAL
TA = 260C
I
MINIMUM
I- 60
2

L- ,,,,"'V

/
~V~S='6~
_1

°C

Fig. 7-11
n-CHANNEL DRAIN CHARACTERISTICS

..

Vas = 6 V

VGS=10V""""-

£I-eo
-70

103

16

f-

MINIMUM-l~--

a:
a:-3O

I

CL = 60 pF

k1. -- -~
\

-

15 pF

TYPIC~L

~-20

.

II I

CL=15P~~

~

INPUT VOLTAGE - V

Fig. 7-10
p-CHANNEL DRAIN CHARACTERISTICS

°_60

A

1 '-1

TA - AMBIENT TEMPERATURE -

il
!-40
:!

10

,.

I

Ii.\. -

~&6

I

2

3

"'f(- VOO=10V
Jt,~1!15IV

...

CL=100pF --,

II

~~=60PF

20

~-10

-

r,

~

-- -- :..~ - -r' - - f-

!:~ -IE

f--

·:?'t

v~oJ50lv

180

c180

>140

I

OC

/"

"

1

5.0

200

pf

=

.

b/

I~ V

Fig. 7-7
PROPAGATION DELAY
VERSUS AMBIENT
TEMPERATURE @ VDD 5.0 V
200

voo ~~6 V

~+126°C

Iv

l - t-

Jml

0

VOO=10~
vool=6 V

5

f..- I -

--pvfT

.. 20

I

I
w

111111

0

>

~ Z100 f - J OO ; 5 X - . /
,,0
~ ~ 80
I ~ 60

Fig. 7-6
GATE POWER DISSIPATION
VERSUS FREQUENCY

operation the diodes never conduct, but for certain special
applications such as oscillators, circuit operation may actually

i~;~~~~ORS

depend on diode conduction. Operation in this mode is
permissible so long as input currents do not exceed 10 mAo

D1

I nput capacitance is tYpically 5 pF across temperature for any
input.

7-7

DEFINITION OF SYMBOLS AND TERMS

CURRENTS - Positive current is defined as conventional current flow into a device. Negative current is defined as conventional current flow out of a device.
liN - (Input Current) - The current flowing into a device at specified input voltage and VOO.
IOH - (Output HIGH Current) - The drive current flowing out of the device at specified HIGH output voltage and VOO.
IOL - (Output LOW Current) - The drive current flowing into the device at specified LOW output voltage and VOO.
100 - (Quiescent Power Supply Current) - The current flowing into the VOO lead at specified input and VOO conditions.
IOZH - (Output OFF Current HIGH) - The leakage current flowing into the output of a 3-state device in the "OFF" state at
a specified HIGH output voltage and VOO.
IOZL - (Output OFF Current LOW) - The leakage current flowing out of a 3-state device in the "OFF" state at a specified
HIGH output voltage and VOO.
IlL - (Input Current LOW) - The current flowing into a device at a specified LOW level input voltage and a specified VOO.
IIH - (Input Current HIGH) VOO·

The current flowing into a device at a specified HIGH level input voltage and a specified

IDOL - (Quiescent Power Supply Current LOW) - The current flowing into the VOO lead with a specified LOW level input
voltage on all inputs and specified VOO conditions.
IOOH - (Quiescent Power Supply Current HIGH) - The current flowing into the VOO lead with a specified HIGH level input voltage on all inputs and specified VOO conditions.
IZ - (OFF State Leakage Current) - The leakage current flowing into the output of a 3-state device in the "OFF" state at
a specified output voltage and VOO.

VOLTAGES -

All voltages are referenced to V SS (orVEe)which is the most negative potential applied to the device.

VOO - (Drain Voltage) -

The most positive potential on the device.

VIH - (Input HIGH Voltage) - The range of input voltages that represents a logic HIGH level in the system.
VIL - (Input LOW Voltage) - The range of input voltages that represents a logic LOW level in the system.
VIH (min) -

(Minimum Input HIGH Voltage) - The minimum allowed input HIGH level in .a logic system.

VIL (max) -

(Maximum Input LOW Voltage) - The maximum allowed input LOW level in a system.

VOH - (Output HIGH Voltage) - The range of voltages at an output terminal with specified output loading and supply
voltage. Device inputs are conditioned to establish a HIGH level at the output.
VOL - (Output LOW Voltage) - The range of voltages at an output terminal with specified output loading and supply voltage. Device inputs are conditioned to establish a LOW level at the output.
VSS - (Source Voltage) - For a device with a single negative power supply, the most negative power supply, used as the
reference level for other voltages. Typically ground.
Vee - (Source Voltage) - One of two (VSS and Vee) negative power supplies. For a device with dual negative power supplies, the most negative power supply used as a reference level for other voltages.

ANALOG TERMS
RON - (ON Resistance) - The effective "ON" state resistance of an analog transmission gate, at specified input voltage,
output load and VOO.
..

6. RON - ("Il. " ON Resistance) - The differen.ce in effective "ON" resistance between any two transmission gates of an
analog device at specified input voltage, output load and VOO.

7-9

•

DEFINITION OF SYMBOLS AND TERMS USED IN DATA SHEETS
AC SWITCHING PARAMETERS
fMAX - (Toggle Frequency/Operating Frequency) - The maximum rate at which clock pulses may be applied to a sequential circuit with the output of the circuit changing between 10% ofVOD and 90% of VOO. Above this frequency the device
may cease to function. See Figure 7-15.
tpLH - (Propagation Oelay Time) - The time between the specified reference points, normally 50% points on the input
and output voltage waveforms, with the output changing from the defined LOW level to the defined HIGH level. See Figure 7-14.
tpHL - (Propagation Delay Time) - The time between the specified reference points, normally 50% points on the input
and output voltage waveforms, with the output changing from the defined HIGH level to the defined LOW level. See Figure 7-14.
tTLH - (Transition Time, LOW to HIGH) - The time between two specified reference points on
to 90% of VDO' which is changing from LOW to HIGH .. See Figure 7-14.

a waveform, normally 10%

tTHL - (Transition Time, HIGH to LOW) - Th.e time between .two specified reference points on a waveform, normally 90%
to 10% of VDD' which is changing from HIGH to LOW .. See Figure 7-14.
tw -

(Pulse Width) - The time between 50% amplitude points on the leading and trailing edges of pulse.

th - (Hold Time) - The interval immediately following the a~tive transition of the timing pulse (usually the clock pulse) or
following the transition of the control input to its latching level, during which interval the data to be recognized must be
maintained at the input to ensure its continued recognition. A negative hold time indicates that the correct logic level may
be released prior to the active transition of the timing pulse and still be recognized.
ts - (Set-up Time) - The interval immediately preceding the active transition of the timing pulse (usually the clock pulse)
or preceding the transition of the control input to its latching level, during which interval the data to be recognized must be
maintain·ed at the input to ensure its recognition. A negative set-up time indicates that the correct logic level may be initiated sometime after the active transition of the timing pulse and still be recognized.
tpHZ - (3-State Output Disable Time, HIGH to Z) - The time between the specified reference points, normally·the 50%
point on the Output Enable input voltage waveform and a point representing a 0.1 VDD drop on the Output voltage waveform of a 3-state device, with the output changing from the defined HIGH level to a high impedance OFF state.
tpLZ - (3-State Output Disable Time, LOW to Z) - The time between the specified reference points, normally the 50%
point on the Output Enable input voltage waveform and a point representing a 0.1 VDD rise on the Output voltage waveform of a 3-state device, with the output changing from the defined LOW level to a high impedance OFF state.
tpZH - (3-State Output Enable Time, Z to HIGH) - The time between the specified reference points, normally the 50%
point on the Output Enable input voltage waveform and a point representing 0.5 VOD on the Output voltage waveform of
a 3-state device, with the output changing from a high impedance OFF state to the defined HIGH level.
tpZL - (3-State Output Enable Time, Z to LOW) - The time between the specified reference points, normally the 50%
point on the Output Enable input voltage waveform and a point representing 0.5 VOO on the Output voltage waveform of
a 3-state device, with the output changing from a high impedance OFF state to the defined LOW level.
trec - (Recovery Time) - The time between the end of an overriding asynchronous input, typically a Clear or Reset input,
and the earliest allowable beginning of a synchronous control input, typically a Clock input, normally measured at 50%
points on both input voltage waveforms.
tcw- (Clock Period)

~

The time between 50% amplitude points on the leading edges of a clock pulse.

1- -I ---.:----'THL

T~~\LINPUT

-.--1\ - - - - ---

-I -'THL - I-;TLH
--I

----+--.L..,. ___ _
INVERTING
OUTPUT

.\

\

---

tO

f.----------sO%

--____

____.;;TI - - - -

v
90%

-

10% Vss

Voo
90%

.L

-----50%

1_.

10% Vss

Fig. 7·14. Propagation Delay, Transition Time

Fig. 7-15. Maximum Operating Frequency

7-10

40018

40028

QUAD 2-INPUT NOR GATE. DUAL 4-1 NPUT NOR GATE
DESCRIPTION - These CMOS logic elements provide the positive input NOR function. The outputs are fully buffered for highest noise
immunity and pattern insensitivity of output impedance.

40018
LOGIC AND CONNECTION DIAOftAM
DIP (TOP VIEW)

40028
LOGIC AND CONNECTION DIAGRAM
DIP (TOP VI EW)

NOTE:

The F latpak versions have the same pinouts
(Connection Diagram) as the Dual In-line
Package.

DC CHARACTERISTICS: VDD as shown, VSS = 0 V
LIMITS
SYMBOL

PARAMETER
MIN

IDD

Quiescent
Power
Supply
Curr'ent

VDD=10V

VDD=5V

XC
XM

TYP

MAX

MIN

TYP

MIN

TYP

4
30
1
30

TEST CONDITIONS
See Note 1

MAX

2
15
0.5
15

1
7.5
0.25
7.5

TEMP

UNITS

VDD=15V

MAX

MIN,25°C
MAX
MIN,25°C
MAX

j.lA
j.lA

All inputs at
OVorVDD

AC CHARACTERISTICS: VDD as shown, VSS = 0 V, T A = 25°C, 4001 B only (See Note 2)
LIMITS
SYMBOL

PARAMETER

VDD = 5 V
MIN

tPLH

Propagation Delay

tPHL
tTLH

Output Transition Time

tTHL

TYP

VDD = 10 V

MAX

MIN

TYP

MAX

UNITS

VDD = 15V
MIN

TYP

MAX

TEST CONDITIONS
See Note 2

60

110

25

48

ns

110

25

60
60

20

60
60
60

20

48

ns

RL = 200 kn

135

30

70

20

45

ns

Input Transition

135

30

70

20

45

ns

Times ... 20 ns

CL=50pF,

AC CHARACTERISTICS: VDD as shown, VSS = 0 V, T A = 25°C, 4oo2B only
LIMITS
SYMBOL

PARAMETER

VDD = 10 V

VDD =5 V
MIN

TYP

MAX

MIN

TYP

MAX

UNITS

VDD=15V
MIN

TYP

MAX

TEST CONDITIONS
See Note 2

65

110

30

60

20

4B

ns

tPHL

70

110

30

60

23

ns

RL = 200 kn

tTLH

75

135

40

70

30

ns

I nput Transition

60

135

23

70

15

4B
45
45

ns

Times ... 20 ns

tPLH

tTHL

Propagation Delay

Output Transition Ti me

CL = 50 pF,

NOTES:

1.

Additional DC Characteristics are listed in this section under 40008 Series CMOS Family Characteristics.

2.

Propagation Delavs and Output Transition Times are graphically described in this section under 40008 Series CMOS F-amily Characteristics.

7-11

•

FAIRCHILD CMOS • 40018 • 40028
TYPICAL ELECTRICAL CHARACTERISTICS
4001 BAND 4002B
POWER DISSIPATION
VERSUS FREQUENCY

~10oo

+ll ~ I~5JJII

I

w 100
CI

:l!

10

a:
w

1,0

~
...

I

f

10- 2

iii

~

10- 3

Ilv~~ ~1~5IV

VriDI~ 10 ~

~

~~
~~

~~
~~ ... ~ VDD\ =5V

~ 10- 1

i=

I:

V~D IJ ~15 ~

~~

[~;:'VDD = J~

?: ~~ VDD~'1Ici~1IJ

".
a:
w 10-4
~ 102

...

II

IIII CL=15pFCL =, ~,O pF - - -

103
104
105
106
INPUT FREQUENCY - Hz

107

4001B
PROPAGATION DELAY
VERSUS TEMPERATURE

4002B
PROPAGATION DELAY
VERSUS TEMPERATURE

80

.
c

>

80
.. 70
c
I 60

60

:3w

50

z

40

~

30

CI

f

20

...

10

0

>

-

C

0

CL= 15 pF

CL = 15 pF
70

~

1-- - ; t P l t b J + - P c-

C

- -rpJ.'r '1'\1to~II

Z 40

I-

tJHL

= 110 V I--

30

,f

20

oa:

... 10

trLHi tP~L V1DO 1'1 ~ V ,

o

o
~

CI

,

-

a:

50

o

TA - AMBIENT TEMPERATURE - DC

4oo1B
PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

.
7so 90

Z

50

~

40

o

f

30

~ 20

... 10

-

f- l-

tPLH. tpHL Voo = 10 V

tPLH. tPHL Voo ~_ 15 V

4002B
PROPAGATION OELAY
VERSUS LOAD CAPACITANCE

_ltPLJ. tPHl

v~o= ~v ..--

~120r--r-r--r-r--r~r-~~

I
; 100

~

w

C

/f""

- --

~

r-

Sor--r-r--r~~-r~r-~~

Z

o

~ ~ tPLH. tPHL Voo = 10 V

00

I--

TA=25 DC

; 70
~ 60

-

\

l- I---

-60-40 -20 0 20 40 60 80100120140
TA - AMBIENT TEMPERATURE - DC

-60-40-20 0 2040 60 80100120140

100

t

tplH. PH ( vrio =15 Vi

~

~ ::-

- i '1--

1\

-c-"' ~

tPLr·tprL vr

oa:

...

=, 15

20 40 60 sO 100 120,140 160
CL - LOAD CAPACITANCE - pF

7-12

20~~~~~~r-~~r-~~

40068
I8-STAGE STATIC SHIFT REGISTER

DESCRIPTION - The 4006B is an 18-stage Shift Register arranged as two 4-stage and two 5-stage
shift regsiters with a common Clock Input (CP)' The two 4-stage shift registers. each have a Data
Input (Da. Db) and a Data Output (03a. 03b); the two 5-stage shift registers each have a Data Input
(Dc. Dd) and Data Outputs from the fourth and fifth stages (03c. Q4c. Q3d. 04d).
The registers can be operated in parallel or interconnected to form a single shift register of up to 18
bits. Data is shifted into the first register position of each register from the Data Inputs (Da-Dd) and
all the data i'l..!'ach register is shifted one position to the right on the HIGH-to-LOW transition of the
Clock Input (CP).

LOGIC SYMBOL,

1

CLOCK EDGE-TRIGGERED ON A HIGH-TO-LOW
TRANSITION
CASCADABLE
SERIAL-TO-SERIALDATA TRANSFER

•
•
•

PIN NAMES
Da-Dd

CP

Data Inputs
Clock Input (H .... L Edge-Triggered)
Data Outputs

CP
03a- Q3d. 04e. 04d

13

5

4

40068

10

11

12

8

Voo = Pin 14
VSS = Pin 7

NC

= Pin 2

LOGIC DIAGRAM

8

D

D,

Q

Q

Q

D

Q

CONNECTION DIAGRAM
DIP (TOP VIEW)
CP
Db

CD

14
13

12
11
10

Voo
VSS
NC

o

~

14

NOTE:

~

7
2
Number

The F latpak version has the same

Pin
Pin
=< Pin
= Pin

pinouts (Connection Diagram) as the

Dual I n~line Package.

7-13

FAIRCHILD CMOS • 4006B
DC CHARACTERISTICS: VDD as shown, VSS = 0 V (See Note 1)
LIMITS
SYMBOL

PARAMETER

VDD = 5 V
MIN

Quiescent

Power
IDD

Supply
Current

TYP

MAX

XC
XM

il DD = 15V

VDD= 10 V
MIN

TYP

MAX

MIN

TYP

TEMP

UNITS

TEST CONDITIONS

MAX

20

40

80

150

300

600

5

10

20

150

300

600

/LA
/LA

MIN,25°C
MAX

All inputs at

MIN, 25°C

o Vor VDD

MAX

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VDD as shown,VSS = 0 V, TA = 25°C (See Note 2)
LIMITS
PARAMETER

SYMBOL

tPLH
tpHL
tTLH
tTHL
twCP

Propagation Delay,

CP

VDD=10V
MIN TYP MAX

90

200

39

100

30

80

90

200

35

100

25

80

60
60

135

30

75

20

45

135

30

75

20

45

to any Q n

Output Transition Ti me

ts

CP Minimum Pulse Width
Set-Up Time, Dn to CP

th

Hold Time, Dn to

CP

Maximum Input Clock Frequency
fMAX

VDD =5 V
MIN TYP MAX

(Note 3)

100

50

50

VDD = 15V
MIN TYP MAX

20

40

30

12

15

5

15

5

1

15

4

10

4

8

19

15

30

18

36

TEST CONDITIONS

ns
ns
ns

13

30

UNITS

ns

CL =50 pF,
RL = 200 kU
Input Transition

Times.;; 20 ns

MHz

NOTES:
1-

2.
3.
4.

Additional DC Characteristics are listed in this section under 40008 Series CMOS Family Characteristics.
Propagation Delays and ,Output Transition Times are graphically described In this section under 40008 Series CMOS Family Characteristics.
For fMAX, input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.

It is recommended that input rise and fall times to the Clock Input be less than 15 /Js at VOO

= 5 V, 4/Js at VOO

VOO=15V.

SWITCHING WAVEFORMS

_twCi'-

CP~t:'~~
ts

th

~~

On

50%

,~

)c..J~
MINIMUM CLOCK PULSE WIDTH
AND SET-UP AND HOLD TIMES, Dn TO

CP

NOTE: Set-up and Hold Times are shown as positive values but may be specified as negative values.

7-14

= 10 V. and 3 IJs at

4007UB
DUAL COMPLEMENTARY PAIR PLUS INVERTER

DESCRIPTION -

The 4007UB is a Dual Complementary Pair and an Inverter with access to each

device. It has three n-channej and· three p-channel enhancement mode MOS transistors. For proper

CONNECTION DIAGRAM
DIP (TOP VI EW)

operation VSS';; V1 .;; VDD-

14

•
•

INPUT DIODE PROTECTION ON ALL INPUTS
DRAINS AND SOURCES TO N- AND P-CHANNEL
TRANSISTORS AVAILABLE

PIN NAMES
SP2, SP3
Dn Dp2
DN1. DN2
SN2. SN3
DN/P3

Source Connection to Second and Third p-channel Transistors
Drain Connection from the First and Second p-channel Transistors
Drain Connection from the First and Second n-channel Transistors
Source Connection to the Second and Third n-channel Transistors
Common Connection to the Third p-channel and n-channel
Transistor Drains
Gate Connection to n- and p-channel Transistors 1. 2 and 3

2

13

3

12

4

11

5

10

6

9

7

8

NOTE:
The Flatpak version has the same pinouts (Connection Diagram) as the
Dual In-line Package,

LOGIC SYMBOL

@

(3)

@

VDD

Sp2

Sp3

d dJ
h@

®

G1

Dp1

I DN1

hG)

12)

D p2

@

G2

DN2

G3

i--'@

i--'@

~

}'N~'

Vss

SN2

~

0

0

®

9 t1
7-15

SN3

@

•

FAIRCHILD CMOS • 4007UB
DC CHARACTERISTICS: VOO as shown VSS

~

0 V (See Note 1)
LIMITS

SYMBOL

PARAMETER

VOO -5 V
MIN

Quiescent
Power

100

Supply

XC
XM

Current

TYP

VOD-l0V

MAX

MIN

TYP

MIN

TYP

TEMP

TEST CONDITIONS

MAX

4
30
1
30

2
15
0.5
15

1
7.5
0.25
7.5

UNITS

VOO-15V

MAX

MIN,25°C
MAX
MIN,25°C
MAX

MA
MA

All inputs at

o Vor VOO

AC CHARACTERISTICS: VOO as shown, VSS ~ 0 V, T A ~ 25°C (See Note 2)
LIMITS
SYMBOL

PARAMETER

VOO
MIN

~5

VOO~10V

V

TYP

MAX

MIN

VOO

TYP

MAX

MIN

~

15V

UNITS

TYP

MAX

TEST CONDITIONS

42

B5

23

40

18

32

ns

CL

~50pF,

tPHL

42

85

23

40

18

32

ns

RL

~

tTLH

65

135

30

70

25

45

ns

Input Transition

65

135

30

70

25

45

ns

Times';;;:; 20 ns

tPLH

Propagation Delay

Output Transition Time

tTHL

200 kf!

NOTES:

1.

Additional DC Characteristics are listed in this section under 40008 Series CMOS Familv Characteristics.

2.

Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.

POWER DISSIPATION
VERSUS FREQUENCY
;:

1000

I~LI" \J ~ 11-

TA " 25,"C

E

0
0

Voo'" 10 V
0

...~

1

21--

3~

..

~-,..

V

~

~

I

1-').<'

1'-'

Voo

=

5V

TIIII

... "V
.-

I il

V

CL- 15 pF
CL = 50 pF

41-103

104

105

10 7

10·

FREQUENCY - Hz

PROPAGATION DELAY
30

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

VERSUS TEMPERATURE
r-..,-...,.....,........,,-,.-...,...,.....,........,--,

120
110

>

~

C

z
0
>=

90
80
70

""~

60

go

40

0

~

50

30

:z:

20

:5
~

10

~

TA - AMBIENT TEMPERATURE - ~c

100

0

160

0
C L - LOAD CAPACITANCE - pF

7·16

40088
4-BIT BINARY FULL ADDER

DESCRIPTION - The 4008B is a 4-Bit Binary Full Adder with two 4-bit Data Inputs (A O-A 3 •
BO-B 3 ); a Carry Input (Col. four Sum Outputs (SO-5 3 ) and a Carry Output (C4)'

LOGIC SYMBOL

The 4008B uses full lookahead across 4-bits to generate the Carry Output (C4 ). This minimizes the
necessity for extensive "Iookahead" and carry-cascading circuits .
•
•

CARRY LOOKAHEAD BUFFERED OUTPUT
EASILY CASCADED

PIN NAMES
AO-A3. BO-B3
Co
SO-53
C4

5

4

Data Inputs
Carry Input
Sum Outputs
Carry Output

3

2

1

15

14

40088

10

LOGIC DIAGRAM

11

12

13

VDO

= Pin 16

VSS

~

Pin 8

CONNECTION DIAGRAM
DIP(TOP VIEW)

16
15
14

13
12

11

9

10

So

®
NOTE:
The F latpak version has the same
pinouts (Connection Diagram) as the
Dual I n~line Package.

VDO=Pin16

vss

o

=;

Pin 8

= Pin Number

7-17

FAIRCHILD CMOS. 40088
DC CHARACTERISTICS: V DO as shown, V SS = 0 V (See Note 1)

-

SYMBOL

PARAMETER

Quiescent

Power
100

Supply

Current

XC
XM

..

LIMITS
VDD= 10V

VDD= 5 V
MIN TYp· MAX

MIN

TYP

VDD=15V

MAX

MIN

TYP

MAX

20

40

80

100

300

600

5

10

20

150

300

600

UNITS

TEMP

TEST CONDITIONS

MIN,25°C

I'A

MAX
MIN,25°C

I'A

All inputs at
OVorVDD

MAX

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: V DD as shown, VSS = 0 V, TA = 25°C (see Note 2)
SYMBOL

PARAMETER

MIN
tpLH

Propagation Delay, An' Bn to Sn

tpHL
tpLH
tpHl
tpLH

Propagation Delay, An' Bn to C4
Propagation Delay, Co to Sn

tpHL
tpLH
tpi-li
tTLH

LIMITS
VDD= 10V

VDD = 5 V

Propagation Delay, Co to C4
Output Transition Time

tTHL
NOTES:

TYP

MAX MIN

150
150

VDD=15V

UNITS

TEST CONDITIONS

TYP

MAX

MIN TYP MAX

300

60

140

50

110

ns

300

60

140

50

110

ns

138

275

63

130

50

100

ns

138

275

63

130

50

100

ns

115

250

69

115

52

90

ns

CL = 50pF,

123

250

69

115

52

90

ns

RL = 200 krl,

72

200

28

95

23

75

ns

I "put Transition

95

200

28

95

23

75

.ns

Ti mes .; 20 ns

60

135

30

75

20

45

ns

60

135

30

75

20

45

ns

1. Additional DC Characteristics are listed in this section under 4000B Series CMOS Family Characteristics.
2. Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.

APPLICATION
A 2-DIGIT BCD TO 7-BIT BINARY DECODER USING THE 4008B
BCD INPUTS
LEAST

MOST

SIGNIFICANT
DIGIT

SIGNIFICANT

. .
1

2

I

I

.

DIGIT
\1

4

8

I

.--

.r-

,

'0 20 40 80

'--

I

I

AO Bo Al B,

A2 82 Ai B3
4008B

Co
So

S,

C4
s2

t- l -

S3

~

R~
2°

2'

-

AO BO A, B,

4008B

Co
So

1

22

\

T
B I NARY OUTPUTS

7-18

A2 B2 A3 B3

S,

S2

S3

14

15

ls .

40118 • 40128
40128 DUAL
4-INPUT NAND GATE

40118 QUAD
2-INPUT NAND GATE

DESCRIPTION - These CMOS logic elements provide the positive input NAND function. The outputs are fully buffered for highest noise

immunity and pattern insensitivity of output impedance.
4012B
LOGIC AND CONNECTION DIAGRAM
DIP (TOP VIEW)

4011B
LOGIC AND CONNECTION DIAGRAM
DIP (TOP VIEW)

NOTE:
The Flatpak versions have the same pinouts
(Connection Diagram) as the Dual In-line
Package.

DC CHARACTERISTICS: VDD as shown, VSS = 0 V (See Note 1)
LIMITS
SYMBOL

PARAMETER

MIN

IDD

Quiescent
Power
Supply
Current

VDD=10V

VDD=5 V

XC
XM

TYP

MAX

MIN

TYP

TYP

TEMP

MAX

2
15
0.5
15

1
7.5
0.25
7.5

UNITS

VDD=15V
MIN

MAX

4

See Note 1
MIN,25°C
MAX
MIN,25 C
MAX

IJA

30
1

30

TEST CONDITIONS

IJA

All inputs at
OVor VDD

AC CHARACTERISTICS: VDD as shown, VSS = 0 V, TA = 25°C, 4011B only (See Note 2)
LIMITS
SYMBOL

tpLH

PARAMETER

tTLH

UNITS

60

20

48

ns

CL = 50 pF,

60

20

4B

ns

RL=200k{l

70

20

45

ns

Input Transition

70

20

45

ns

Times';; 20 ns

VDD=10V
MIN TYP MAX

60
60
60
60

110

25

110

25

135

30

135

30

Propagation Delay

tPHL
Output Transition Time

tTHL

TEST CONDITIONS

VDD = 15V
MIN TYP MAX

VDD =5 V
MIN TYP MAX

See Note 2

AC CHARACTERISTICS: VDD as shown, VSS = 0 V, TA = 25°C, 4012B only
LIMITS
SYMBOL

PARAMETER

VDD = 5 V
MIN

tpLH
tpHL
tTLH
tTHL

Propagation Delay

Output Transition Time

VDD=10V

TYP

MAX

MIN

TYP

MAX

UNITS

VDD -15V
MIN

TYP

MAX

TEST CONDITIONS
See Note 2

73

110

33

4B

ns

CL = 50 pF,

110

31

60
60

24

85

20

48

ns

RL =200 k{l

76

135

37

70

27

45

ns

Input Transition

67

135

25

70

17

45

ns

Times';; 20 ns

NOTES:
1.

Additional DC Characteristics are listed in this section under 40008 Series CMOS Family Characteristics.

2.

Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.

7-19

FAIRCHILD CMOS· 40118 • 40128
TYPICAL ELECTRICAL CHARACTERISTICS
40118 AND 40128
POWER DISSIPATION
VERSUS FREQUENCY

~1000

;:i

I

10

()

~
ex:

v~DIJ~15~

V6DI; 10
1,0

...w

\

~ 10-'

i=

~ 10- 2

iii

~

Ullv~J ~1\5IV

TA=~08

1

w '00

Cl

10- 3

~

'"

ex:

w 10-4
102

...~

~~

~

~~



~

11

70

:3W
C

pF

tPLH. tpHL VDD - 10 V

30



:3W
c
Z

0

i=

()

°10-3

II)

TA
CL

N

:z:
::I!

~

......

~

CLOCK FREQUENCY
VERSUS
POWER SUPPLY VOLTAGE

"QY

V

40

!5o

20

/'"

--- -

=,0"
--::-V
VOO =.2-.-

"99--

V V
......i-""

~

2040 60 80100120140

()

/'"

60

10

......- f--

W

f.--

~ ~ ~1001W1~1~

CL - LOAD CAPACITANCE - pF

TA - AMBIENT TEMPERATURE - °C

WAVEFORMS

SET -UP TIMES, HOLD TIMES,
AND MINIMUM CLOCK PULSE WIDTH

-

RECOVERY TIME FOR SO, RECOVERY TIME FOR CD,
MINIMUM So PULSE WIDTH, AND MINIMUM CD PULSE WIDTH

NOTE: Set-up Times and Hold Times are shown as positive values but may be specified as negative values.

7-23

40148
8-81T SHIFT REGISTER

DESCRIPTION - The 4014B is a fully synchronous edge-triggered 8-Bit Shift Register with eight
synchronous Parallel Inputs (PO-P7), a synchronous Serial Data Input (OS), a synchronous Parallel
Enable Input (PE), a LOW-to-HIGH edge-triggered Clock Input (CP) anil Buffered Parallel Outputs
from the last three stages (05-07)'
Operation is synchronous and the device. is edge-triggered on the LOW-to-HIGH transition of the Clock
Input (CP). When the Parallel Enable Input (PE) is HIGH, data is loaded into the register from the
Parallel Inputs (PO-P7) on the LOW-to-HIGH transition of the Clock Input (CP). When the Parallel
Enable Input (PE) is LOW, data is shifted into the first register position from the Serial Data Input
(OS) and all the data in the register is shifted one position to the right on the LOW-to-HIGH transition
of the Clock Input (CP).

LOGIC SYMBOL

7 6 5 4 1314 15 1

11
10

CP
12 3

Voo = Pin 16

VSS = Pin 8

=

•
•
•
•

CONNECTION DIAGRAM
DIP (TOP VI EW)

TYPICAL SHIFT FREQUENCY OF 14.7 MHz AT VDD 10 V
PARALLEL OR SERIAL TO SERIAL DATA TRANSFER
AVAILABLE OUTPUTS FROM THE LAST THREE STAGES
FULLY SYNCHRONOUS

16
15
14
13
12
11
10

PIN NAMES
PE
PO-P7

Os
CP
05, 06, 07

Parallel Enable Input
Parallel Data Inputs
Serial Data Input
Clock Input (L--H Edge-Triggered)
Buffered Parallel Outputs from the Last Three Stages

NOTE:

The Flatpak version has the same
outs (Connection Diagram)
Dual In~line Package

LOGIC DIAGRAM

Voo = Pin 16
VSS = Pin 8
= Pin Number

o

7-24

pin~

as the

FAIRCHILD CMOS • 40148
DC CHARACTERISTICS: VOO as shown, VSS

=0 V

(See Note 1)
LIMITS

PARAMETER

SYMBOL

VOO=5 V
MIN

100

Quiescent
Power

XC

Supply
Current

XM

TYP

VOO=10V

MAX

MIN

TYP

20
150
5
150

MIN

TYP

40
300
10
300

TEMP

UNITS

VOO= 15V

MAX

TEST CONOITION s

MAX
80
600
20
600

MIN,25°C
MAX
MIN,25°C
MAX

p.A
p.A

All inputs at

o Vor VOO

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VOD as shown, VSS = 0 V, T A = 25°C (See Note 2)
LIMITS
SYMBOL

PARAMETER

VOO =5 V
MIN TYP MAX

VOO=10V
MIN

TYP

MAX

UNITS

VOO = 15V
MIN

TYP

129

275

57

120

41

96

ns

tpHL

165

350

6B

120

47

96

ns

tTLH

70

135

37

75

21

ns

77

135

34

75

21

45
45

tpLH

Propegation Oelay, CP to any Q

Output Transition Time

ns

lTHL
twCP

CP Minimum Pulse Width

200

93

100

33

80

22

ns

ts

Set-Up Time PE to CP

300

118

80

44

64

29

ns
ns

th

Hold Time PE to CP

ts

Set-Up Time Os to CP

th

Hold Time Os to CP

ts

Set-Up Time Pn to CP

th

Hold Time Pn to CP
Max. Input Clock Frequency

fMAX

(Note 3)

TEST CONOITIONS

MAX

25

15

5

3

4

2

200

80

50

28

40

17

ns

10

5

0

-1

0

-1

ns

250

108

100

37

80

23

ns

20

10

5

3

4

2

ns

2

5.8

5

14.7

6

17

MHz

CL = 50 pF,
RL = 200 kn
I nput Transition

Times"; 20 ns

NOTES:
1.
2.
3.
4.

Additional DC Characteristics are listed in this saction under 4000B Series CMOS Family Characteristics.
Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.
For fMAX. input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.
It is recommended that input rise and fall times to the Clock Input be less than 15 J.Ls at VOO = 5 V, 4,.,,5 at VDO = 10 V, and 31J,s at
VOO

= 15

V.

SWITCHING WAVEFORMS

MINIMUM CLOCK PULSE WIDTH
AND SET -UP AND HOLD TIMES, PE TO CP, Os TO CP, AND Pn TO CP
NOTE: Set-up and Hold Times are shown as positive values but may be specified as negative values.

,7-25

FAIRCHILD CMOS • 40148
TYPICAL ELECTRICAL CHARACTERISTICS

POWER DISSIPATION
VERSUS FREQUENCY
1000

TAioiJi,c

;:

E
I

~Q'; J). ~

w

""
"

10

~

1.0

"

,~~

z
0
;:: 10- 1 f~

D

"~

"

10- 2

10- 3

V

~~

~

Ei

~

t I,,,~JI,

100

-.!J(J/

~~

~~

~V'

~ ~t/
t:::

V/

p

~~

"'/

r

CL" 15pF
CL'" 50 pF

104

10 6

10 5

INPUT FREQUENCY - Hz

PROPAGATION DELAY
CP TO Q n VERSUS
LOAD CAPACITANCE
c:! 240

~

w~\..'

/

~

u 180

,./

,:
~

160

Cl 140

z

~

/

120

~ 100

~ 80
I

~

!l-

40
20

..-- .---- --:--

60

~

~

f--j"HL'i OO
20

40

0

r '"

~\JQ

I.

1

s~

~_ 140

" 120
"

80

~

60

~
I

-i;5v
t PLH'1'00-j v_

~

'"~

40

!l!l-

20

0

"..-

1f-=;

-

~Q\J

I

f-" r-l

I.

I I

I_,~~
~-

-

--;'LH' Voo" 10 V

I 1 ..J.

tpLH' VOD '" 15

V

-,5 V

r'(j

0

20

40

60

7-26

q--

I I I

80

100 120

TA - AMBIENT TEMPERATURE - "C

CL - LOAD CAPACITANCE - pF

!s~

~

w\..\'\·

f-"

-60 -40 -20

1M

I

V

/

/

;::

~

1~

L

~

"~ 100

1

lo'ov

120

V

~

1
tpl-\L' VoD_ 10 V

100

w~\...'

~ 160

I I
~

~

Cl"'15pF

6

~
1

200

I 180

w\.. '

V

60

,

U"'I

TA "" 25"C

220

~ 200

PROPAGATION DELAY,
CP TO Q n
VERSUS TEMPERATURE

140

40158
DUAL 4-81T STATIC SHIFT REGISTER

DESCRIPTION - The 4015B is a Dual Edge-Triggered 4-Bit Static Shift Register (Serial-to-Parallel
Converter>. Each Shift Register has a Serial Data Input (0). a Clock Input (CP), four fully buffered

LOGIC SYMBOL

parallel Outputs (QO-Q3) and an overriding asynchronous Master Reset Input (MRL

4015B

Information present on the serial Data Input (0) is shifted into the first register position, and all the

data in the register is shifted one position to the right on the LOW-to-HIGH transition of the Clock
Input (CP),
A HIGH on the Master Reset Input (MR) clears the register and forces the Outputs (00 - 03) LOW,
independent of the Clock and Data Inputs (CP and D),

•
•
•
•

TYPICAL SHIFT FREOUENCY OF 14 MHz AT VDD = 10 V
ASYNCHRONOUS MASTER RESET
SERIAL-TO-PARALLEL DATA TRANSFER
FULLY BUFFERED OUTPUTS FROM EACH STAGE

3

10

15

PIN NAMES
DA,DB
MRA,MRB
CPA,CPB
OoA,01A,02A,03A
°OB,01B,02B,03B

Serial Data Input
Master Reset Input (Active HIGH)
Clock Input (L-->H Edge-Triggered)
Parallel Outputs
Parallel Outputs

14

LOGIC DIAGRAM

13

12

Voo

= Pin

VSS

=

•

11

16

Pin 8

CONNECTION DIAGRAM
DIP (TOP VIEW)

16
15
14
13
12

11

@ ~O-Ol>---I

10

G)C_P~B____~~>-+-

__-+______4-__-+______4-__-+____~

~M~O--Ol~______~~________~~________~~________~

NOTE:

The Flatpak version has the same

= Pin
='

7-27

8

Pin Number

pinouts (Connection Diagram) as the
Dual In-line Package.

FAIRCHILD CMOS • 40158
DC CHARACTERISTICS: VOO as shown, VSS = 0 V ISee Note 11
LIMITS
SYMBOL

PARAMETER
MIN
Quiescent
Power

100

Supply
Current

TYP

XC
XM

MAX

TYP

MIN

MAX

MIN

TYP

5
150

TEST CONDITION S

MIN,25°C
MAX
MIN,25°C
MAX

All inputs at
o V or VOO

MAX
80
600
20
600

40
300
10
300

20
150

TEMP

UNITS

VOO -15 V

VOO-10V

VOO = 5 V

p.A
p.A

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VOO as shown, VSS = 0 V, TA = 25°C ISee Note 21
LIMITS
SYMBOL

tpLH

PARAMETER

VOO - 5 V
MIN TYP MAX

Propagation Delay, CP to Q

tpHL
tPHL
tTLH

Propagation Delay, MR to Q

Output Transition Time

tTHL
ts

Set-Up Time, 0 to CP

th

Hold Time, 0 to CP

twCPILI

Minimum Clock Pulse Width

twMRIHI

Minimum MR Pulse Width

tree

MR Recovery Time

fMAX

Maximum CP Frequency (Note 3)

VOO-10V
MIN

TYP

MAX

UNITS

VOO = 15V
MIN

TYP

MAX

165

300

85

150

50

120

ns

165

300

85

150

50

120

ns

180

325

90

160

60

128

ns

85

150

45

85

30

50

ns

85

150

45

85

30

50

ns

150

70

50

30

40

25

ns

0

-5

0

-20

0

-10

ns
ns

120

60

70

35

56

25

75

40

45

25

36

20

ns

300

160

120

60

96

45

ns

4

8

7

14

8

16

MHz

TEST CONDITIONS

CL = 50 pF,
RL=200kn
I nput Transition

Times" 20 ns

NOTES:
1. Additional DC Characteristics are listed in this section under 40008 Series CMOS Family Characteristics.
2. Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.
3. For fMAX, input rise and fall times are greater than or equal to 5 ns and tess than or equal to 20 ns.
4. It is recommended that input rise and fall times to the Clock Input be less than 15}is at VOO "" 5 V, 4 J.Ls at VOD = 10 V, and 3 J,Ls at

VDD=15V.

7-28

FAIRCHILD CMOS • 40158
TYPICAL ELECTRICAL CHARACTERISTICS
PROPAGATION DELAY
VERSUS
POWER SUPPL Y VOLTAGE

POWER DISSIPATION
VERSUS FREOUENCY
1000
T

=

100

300r-~---.---.--~--~---'

I

V?I~I= 15 V \ \

~~

10

~I
~

25o~111

VDD =
1.0

w

CiiCl

W~

15~10-1

~
10- 3

~~

/~

102

«
t!l
« '<:"
~

01

CC>-

~«

1...1

~ VDD= 5

..JW

:CO

E:-

!~DP1111~~ III III

I

~
10- 4

1111

250~~~~---4---+---+--~

r-

~\~

p

~~

a:e(

w~

s:Owa: 10- 2

~~

.~~ l.-V

r--

'"
~~

file(

z
o

:c

CL = 1 5 pF
- - CL = 50 pF

103
104
105
106
INPUT FREOUENCY - Hz

50 t---t---t---+--+--"-""==i

...I

1

E:-

0'.,.0--':.--5:'--:'--1'-0----'-----'15

107

VDD - OUTPUT POWER
SUPPLY VOLTAGE - VOLTS

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE
~

~ 160

TA = 25°C

I
;

250

w
C
Z 200

VDD = 5 V

o
;=
~ 150

f..-

it

~
~

~
~

U

~

f..-f-""

VDD = 10 V
100

f-- f--

I
"

PROPAGATION DELAY
VERSUS TEMPERATURE

300

50

~
VOID =

o
o

I

>-

-

CL I= 1

S

..-

V V

~ 120

~

80

o

60

~

I

40

"

20

~
~

U

20 40 60 80 100120140160
CL - LOAD CAPACITANCE - pF

~5 V

I
V6D

Cl

a:

rV

i-V6D

100

~
it

-

J-+-- I--'

J pF

140

J10lV

r-I-- I-- I--

-

I-- I--

I
Vr

[ly-

--

I

o

-60-40-20 0

20 40 60 80100120140

TA - AM81ENT TEMPERATURE - °C

SWITCHING WAVEFORMS

I'

'i'WMRIHI

MR~

l-t..--,,,C_
CP

150%

SET·UP TIMES, HOLD TIMES
AND MINIMUM CLOCK PULSE WIDTH
RECOVERY TIME FOR MR
AND MINIMUM MR PULSE WIDTH

NOTE:

t5 and th are shown as positive values but
may be speCified as negative values.

7-29

•

4016B
QUAD BILATERAL SWITCHES

DESCRIPTION - The 4016B has four independent bilateral analog switches (transmission gates).
Each switch has two Input/Output Terminals (Y n' Zn) and an active HIGH Enable Input (En). A

LOGIC SYMBOL

HIGH on the Enable Input establishes a low impedance bidirectional path between Y nand Zn (ON

condition). A LOW on the Enable Input disables the switch and establishes a high impedance between
Y nand Zn (OFF condition) .

• DIGITAL OR ANALOG SIGNAL SWITCHING
• INDIVIDUAL ENABLE INPUTS (ACTIVE HIGH)

PIN NAMES
Enable Inputs
Input/Output Terminals
Input/Output Terminals

Voo

LOGIC DIAGRAM (1/4 of 0.4016B)

Pin 14

VSS '" Pin 7
G = Pin Numbers

CONNECTION DIAGRAM

Yn--------------t---------------------,

DIP (TOP VIEW)

14
2

13

3

12

4

11

5

10

6

9

7

8

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as the
Dua. In-line Package.

7-30

FAIRCHILD CMOS. 4016B
DC CHARACTERISTICS: VDD as shown. VSS = 0 V (See Note 1)
LIMITS
SYMBOL

PARAMETER

V DD = 5 V

MIN

TYP

V DD = 10V
MAX

MIN

TYP

V DD = 15 V

MAX

MIN

TYP

UNITS

TEMP

n

25°C

TEST CONDITIONS

MAX

610

370

660

400

840

520

MIN
MAX

V's = VDD
or VSS

RL=10k!

XC

to

1900

RON

ON
ReSIstance

XM

790

2000

850

2380

1080

600

360

660

400

960

600
775

1870

I
t1
LlRON

2000

850

2600

1230

MIN

n

25°C
MAX
MIN

n

25 u C
MAX

I

MIN

n

Leakagl3

n

10

25 u C

25°C

QUiescent

IDO

Power

Supply
Current

MIN.25 C
~A

XM

Any Y to Z

VIS = VOO
or VSS

MAX
MIN.25'C
MAX

XC

1
7.5

XM

0.25
7.5

2
15
0.5
15

Notes on following page.

4
30
1
30

KL=10k!
VOO/2

En = VOO

VIS = VOO/2
'0.25 V

V's
15

XC

Current,

0.25 V

MAX

Two SWitches

IZ

t

VDO/2

En = VOO

to

ON ReSist·

ance Between Any

OFF State

VIS = VOO/2

~A

~A

= VOO

or VSS'

En = VOO
RL = 10 k!l
V's
En

= VOO
= VSS

to

VoO/2

or VSS.

Vas = VSS or VDO

MIN. 25°C
MAX
MIN. 25°C

All inputs at VOO
or VSS

MAX

•

7-31

FAIRCHILD CMOS. 40168
AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VOO as shown, VSS = 0 V, TA = 25°C (See Note 3)
LIMITS
PARAMETER

SYMBOL

VOO = 5 V
MIN

VOO = 10 V

TYP

MAX

MIN

UNITS

VOO= 15V

TYP

MAX

MIN

TYP

MAX

TEST CONDITIONS

CL =50pF, RL = 200 kn
tpLH

Propagat'ion Delay.

17

35

14

28

13

27

tpHL

Y n to Zn or Zn to Y n

15

31

10

20

4

9

42

84

20

40

14

28

ns

Input Trfjnsition Times

<

20 ns

En = VOO
Vis = VOO (square wave)

tPZL

Output Enable Time

tPZH
tpLZ

Output Disable Time

tPHZ

45

90

22

44

18

35

80

160

78

157

76

155

74

150

70

140

62

125

ns
ns

CL 50 pF,
RL =1 kntaVssarVoo
En VOO (square wave)
J nput Transition Times < 20 ns
Vis = VOO or VSS
RL - 10 kn

Distortion, Sine

Input Frequency

0.4

Wave Response

%

=

1 kHz

En = VOO
Vis = VOO/2 (sine wave) p-p
RL - 1 kn
EA = VDO, EB = VSS

Crosstal k Between

0.9

Any Two Switches

MHz

Vis = VOO/2 (sine wave) p-p
20 LaglO
[Vas (BIIVis (All = -50 dB
I nput Transition Times ~ 20 ns

Crosstalk, Enable
I

50

I nput to Output

mV

RUOUT) = 1 kn
RUIN) = 50 n
En = VOO (square wave)

I

R L = 1 kn, En

OFF State

1.25

Feedthraugh

MHz

= VSS

Vis = VOO/2 (sine wave) p-p
20 LaglO (VoslVis) = -50 dB
RL - 1 kn

ON State

40

Frequency Response

MHz

Vis = VOO/2 (sine wave) p-p
En

= VOO, 20

Lo910

(VoslVos@ 1 kHz) = -3 dB
CL = 50 pF, R L = 1 kn
Enable Input
fMAX

10

Frequency (Note 4)

Capacitance

Capacitance

pF

4

pF

0.2

pF

VOO=10V
Vis = Open
100 kHz or

Feedthraugh Switch

Cios

4

En = VSS

Output Switch
Cos

I nput Transition Times ~ 20 ns
En = VOD (square wave)

Vas= Vas/2 at DC
Vis = VOD

I nput Switch

Cjs

MHz

Capacitance

1 MHz Bridge

NOTES:
Additional DC Characteristics are listed in this section under 4000B Series CMOS Family Characteristics.

1.
2.
3.
4.
5.

Vjs!Vos is the voltage signal at an I nput!Output Terminal (Y n!Zn)'
Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.
For f MAX , input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.
In certain applications, the current through the external load resistor (RL) may include both VOO and signal line components. To avoid
drawing VDO current when switch current flows into terminals 1, 4, 8, or 11 the voltage drop across the bidirectional switch must not
exceed 0.5 V at T A ~ 25° C, or 0.3 V at T A
25° C. No VOO current will flow through R L if the switch current flows into terminals 2, 3,
9, or 10.

>

7-32

40178
5-STAGE JOHNSON COUNTER
DESCRIPTION - The ,4017B is a 5-Stage Johnson Decade Counter with ten glitch free decoded
active HIGH Outputs (OO-Og), an active LOW Output from the most significant flip·flop (05-9),
active HIGH and active LOW Clock Inputs (CPO, CP1) and an overriding asynchronous Master Reset
Input (MRL

LOGIC SYMBOL

The counter is advanced by either a LOW·to·HIGH transition at CPa while CPl is LOW or a HIGH·
to-LOW transili.!!!!...at CPl while CPa is HIGH (see Functional Truth Table). When cascading 40178
counters, the Os-g output, which is LOW while the counter is in states 5, 6, 7, 8 and g, can be used to
drive the Cpa input of the next 40178.
A HIGH on the Master Reset Input (MR) resets the counter to zero (00 = 05-9 = HIGH, 01-09 =
LOW) independent of the Clock Inputs (CPO, CPl I.
•
•
•
•

TYPICAL COUNT FREQUENCY OF 13.8 MHz AT VDD - 10 V
ACTIVE HIGH DECODED OUTPUTS
TRIGGERS ON EITHER A HIGH.TO.LOW OR LOW·TO-HIGH TRANSITION
CASCADABLE

PIN NAMES
CPa

Clock Input (L .... H Triggered)
Clock Input (H .... L Triggered)
Master Reset Input
Decoded Outputs
Carry Output (Active LOW)

ar,

MR
Oo-Og
0s-9

12

15 3 2 4 7 10 1 5 6 9 11

VOD = Pin 16
VSS = Pin 8
CONNECTION DIAGRAM
DIP (TOP VIEW)

2
3

FUNCTIONAL TRUTH TABLE
MR

CPa

CPl

H

X

L

Counter Advances

L

H
L .... H

X
H .... L
L

Counter Advances

L

L

X

No Change

OPERATION
00

L

X

H

No Change

L

H
H .... L

L .... H

No Change

L

No Change

L

7

=05-g = H; 01-09 = L

16
15
14
13
12
11
10

8-....=-.....:.~9
H = HIGH Level
L - LOW Level
L.... H = LOW~to~H I G H Transition
H-+L'" H IGH-to-LOW Transition
X ""' Don't Care

NOTE:
The Flatpak version has the same

pinouts (Connection Diagram) as the
Dual In-line Package.

LOGIC DIAGRAM

VDO = Pin i6
VSS = Pin 8
= Pin Number

o

7-33

FAIRCHILD CMOS • 40178
DC CHARACTERISTICS: VDD as shown, VSS = 0 V (See Note 1)
LIMITS
SYMBOL

PARAMETER
MIN

IDD

Quiescent
Power

Supply
Current

VDD = 10 V

VDD =5 V
TYP

XC
XM

MAX

MIN

TYP

20
150
5
150

UNITS

VDD=15V

MAX

MIN

TYP

80
600
20
600

40
300
10
300

TEMP

TEST CONDITION S

MIN,25°C
MAX
MIN,25°C
MAX

All inputs at
OVor VDD

MAX
p.A
p.A

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VDD as shown, VSS = 0 V, TA = 25°C (See Note 2)
LIMITS
PARAMETER

SYMBOL

VDD=5 V
MIN TYP MAX

VDD = 10V
MIN

TYP

MAX

UNITS

VDD = 15V
MIN

TYP

MAX

tPLH

Propagation Delay,

278

700

114

285

82

228

ns

tPHL

226

550

94

240

67

192

ns

tPLH

CPO or CPl to On
Propagation Delay,

205

525

87

225

180

ns

tPHL

CPO or (;1'1 to 05-9

261

650

105

250

63
73

200

ns

tpHL

Propagation Delay, MR to On

170

430

80

175

52

140

ns

tPLH

Propagation Delay, MR to Q5-9

125

300

65

130

40

104

ns

59

135

31

70

23

45

ns

63

135

26

70

19

45

ns

tTLH

Output Transition Time

tTHL
twCP

Min. CPO or CPl Pulse Width

200

85

70

37

56

28

ns

twMR

Minimum MR Pulse Width

130

52

55

22

44

18

ns

tree

MR Recovery Time

Hold Time, CPO to CP1

50
200

16

th

90

25
90

6
39

20
72

3
26

ns
ns

Hold Time, CP1 to CPO

200

89

90

39

72

22

ns

2.5

5.8

7

13.8

8

16

MHz

th

Input Count" Frequency
fMAX

(Note 3)

TEST CONDITIONS

CL = 50 pF,
RL = 200 kn
Input Transition

Times';; 20 ns

NOTES:
1. Additional DC Characteristics are listed in this section under 40008 Series CMOS Family Characteristics.
2. Propagation Delays and Output Transition Times are graphically described in this section under 4000B Series CMOS Family Characteristics.
3. For fMAX, input rise and fall times are greater than or equal
6 ns and less than or equal to 20 ns.
4. It is recommended that input rise and fall times to either Clock Input (CPO or CP1) be less than 15 J..I.S at VOO = 5 V, 4 J..I.s at VOO = 10 V,
and 3/J.sat VOO= 15 V.

to

7-34

FAIRCHILD CMOS • 40178
SWITCHING WAVEFORMS

~
CPo

CPl

\

/

\

OK

/

HOLD TIMES, CPO TO CP1 AND CP1 TO CPO
Hold Times are shown as positive values, but may be specified as negative values.

CPo

MR

MINIMUM PULSE WIDTHS FOR
CP AND MR AND RECOVERY TIME FOR MR
CONDITIONS: CP1 = LOW while CPO is triggered on a LOW-to-HIGH
transition. twCP and trec also apply when CPO = HIGH anq CPl is
triggered on a HIGH-to-LOW transition.

7-35

40188
PRESETTABLE DIVIDE-8Y-N COU T,

DESCRIPTION - The 4018B is a 5-Stage Johnson Counter with a Clock Input (CP), a Data Input (D),
an async,!!on~s Parallel Load Input (PL), five Parallel Inputs (PO-P4)', five active LOW buffered
Outputs (QO-~) and an overriding asynchronous Master Reset Input (MRI.

LOGIC SYMBOL

Information on the Parallel Inputs (PO-P4) is asynchronously loaded into the counter while the
Parallel Load Input (PL) is HIGH, independent of the Clock (CP) and Data (D) Inputs. Data present in
the counter is stored on the HIGH-to-LOW transition of the Parallel Load Input (PLI. When the
Parallel Load Input is LOW, the counter advances on the LOW-to-HIGH transiti,on of the Clock Input
(CP). By connecting the Outputs (00-04) to the Data Input (D), the counter operates as a
divide-by-n counter (2"n"l0); see below.

10

2

o

Oo-~

12

6

11

13

40188

15

VOO
VSS

PIN NAMES

CP
MR

9

"

ASYNCHRONOUS MASTER RESET INPUT (ACTIVE HIGH)
ACTIVE LOW FULLY BUFFERED DECODED OUTPUTS
DIVIDE-BY-N WITH 2 .. N .. l0
CLOCK INPUT L-H EDGE-TRIGGERED
ASYNCHRONOUS PARALLEL LOAD INPUT (ACTIVE HIGH)

PL
PO-P4

7

0

A HIGH on the Master Reset Input (MR) resets the counter (00-04 = HIGH) independent of all
other inputs.
•
•
•
•
•

3

Parallel Load Input
Parallel Inputs
Data Input
Clock Input (L-H Edge-Triggered)
Master Reset Input
Buffered OutPUtS (Active, LOW)

5

•

Pin 16
Pin

8

CONNECTION DIAGRAM
DIP (TOP VIEW)

DIVIDE-BY-N MODE
SELECTION
DIVIDE BY

DINPUT

2

00

3

00- 0 1

4

01

5

01'02

6
7

02

16

15
14
13
12

02"03

8

03

11

9

03"04

10

10

04

NOTE:
The

Flatpak version has the same

pinouts (Connection Diagram) as the
Dual I n-line Package.

7-36

FAIRCHILD CMOS. 40188

kJ'©

-

~

©~
~

z

;;:

~

"

~
~©

/1
e~

18@

8
e~

~

a:

C!1

«

Q
(.)

a
9

7-37

FAIRCHILD CMOS. 40188
DC CHARACTERISTICS: V DD as shown, VSS = 0 V(See Note 1)
LIMITS
SYMBOL

PARAMETER
Quiescent
Power

IDD

Supply
Current

V DD = 10V

Vee = 5 V
MIN TYP MAX

XC
XM

MIN

TYP

UNITS

V D D=15V

MAX

MIN

TYP

TEMP

TEST CONDITIONS

MAX

20

40

80

150

300

600

5

10

20

150

300

600

MIN. 25'C

IJA

MAX

All inputs
atOVotVDD

MIN. 25'C

IJA

MAX

AC CHARACTERISTICS AND SET·UP REQUIREMENTS: VDD as shown, VSS = 0 V, TA = 25'C (See Note 2)
LIMITS
SYMBOL

PARAMETER

VDD = 5 V
MIN
TYP
MAX

VDD=10V
MIN
TYP MAX

MIN

VD D =15V
TYP MAX

UNITS

tPLH

Propagation Delay,

280

500

115

200

80

'160

tpHL

CP to Qn

280

600

115

240

80

170

ns

tPLH

Propagation Delay,

280

600

115

240

80

170

ns

ns

tpLH

Propagation Delay,

280

600

115

240

80

170

ns

tpHL

PLtoOn

280

740

115

300

80

200

ns

tTLH

Output Transition

59

135

31

75

23

45

ns

tTHL

Time

63

135

26

75

19,

45

ns

trec

MR Recovery Time

250

150

110

50

90

40

ns

twMR
tw CP

MR Minimum Pulse Width

130

60

22

ns

100

40

ns

's

Set·Up Time, D to CP

260
175

30
50

48

CP Minimum Pulse Width

65
100

25

60

35

ns

~

Hold Time, D to CP

0

ns

;

Set·Up Time, Pn to PL

85

130
75

0

0
175

Hold Time, Pn to PL
Input Count Frequency

C L =50pF,R L =
200 kn, Input Tran·
sition Times.; 20 ns

MRto On

th
f MAX

TEST CONDITIONS

85

75

25
0

0
1.5

3

60

3.5

8

4.5

35

ns

0

ns

10

MHz

(Note 3)
NOTES:
1. Additional DC Characteristics are listed in this section under 40GOB SerIes CMOS Family Characteristics,
2. Propagation Delays and Output Transition Times are graphically described In this section under 4000B Series CMOS Family Characteristics.
3. For f MAX ' input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.
4. It Is recommended that Input rise and fall times to the Clock Input be"'ess than 16J,l.sat"V OO =6 V,4/JsatV OD = 10V, and3p,satV OD
= 15 V.

7-38

FAIRCHILD CMOS. 40188
SWITCHING WAVEFORMS

CP

MINIMUM CLOCK PULSE WIDTH AND SET-UP AND HOLD TIMES, 0 TO CP

SET-UP AND HOLD TIMES, Pn to PL

CP

n
'w MR

MR _ _ _ _ _ _

J

50%

rec
"'5_0%_ _ _ _ _ __

MR RECOVERY TIME AND MINIMUM MR PULSE WIDTH

Note:

Set~up

and Hold Times are shown as positive values but may be specified as negative values.

7-39

•

4019B
QUAD 2-INPUT MULTIPLEXER

DESCRIPTION - The 40198 provides four multiplexing circuits with common selection inputs; each
circuit contains two inputs and one output. It may be used to select four bits of information from .one
of two sources. The A inputs are selected when SA is HIGH, the 8 inputs when S8 is HIGH. When
SA and SB are HIGH, output (Zn) is the logical OR of the An and 8 n inputs (Zn = An + Bn). When SA
and SB are LOW, output (Zn) is LOW independent of the multiplexer inputs (An.and 8 n ). The 40198
cannot be used to multiplex analog signals. The outputs utilize standard buffers for best performance.
PIN NAMES
SA,SB
AO - A3, 80 - 83
ZO-Z3

LOGIC SYMBOL

Select Inputs (Active HIGH)
Multiplexer Inputs
Multiplexer Outputs

6

7

4 5

2 3

15 1

9

TRUTH TABLE

4019B

SELECT

INPUTS

OUTPUT

SA

S8

An

Bn

Zn

L

L

X

X

L

H

L

L

X

L
H

H

L

H

X

L

H

X

L

L

L

H

X

H

H

H

H

H

X

H

H

H

X

H

H

H

H

L

L

L

H

14

11

10

Voo
VSS

12

13

= Pin 16
= Pin 8

HIGH Level

L

LOW Level

X

Don't Care

CONNECTION DIAGRAM
DIP (TOP VIEW)

LOGIC DIAGRAM
SA

SB

B3

A3

B2

@

A2

Bl

BO

AO
16

CD CD

2
3

15
14

4

13

5

12

6

11

7

10

8

Voo = Pin 16
VS$

= Pin

Z2
Zn

=

9

NOTE:
The F latpak version has the same

8

o -= Pin Number

---....;------

ZI

pinouts (C;onnection Diagram) as the

Dual In-line Package.

SAAn + SSBn

1-40

FAIRCHILD CMOS • 4019B

av

DC CHARACTERISTICS: VDD as shown, VSS ~

(See Note 1)
LIMITS

VOD~5V

PARAMETER

SYMBOL

TYP

MIN
Quiescent

Power
Supply
Current

100

VOO~10V

MAX

XC

20
150

XM

5
150

MIN

TYP

VDD~15V

MAX

MIN

TYP

40
300
10
300

UNITS

TEMP

TEST CONDITIONS

MAX
80
600
20
600

MIN,25°C
MAX
MIN,25°C
MAX

/-LA
/-LA

All inputs at

a v or VDD

a v, TA ~ 25°C (See Note 2)

AC CHARACTERISTICS: VDD as shown, VSS ~

LIMITS
SYMBOL

PARAMETER

VDD
MIN

~5

TYP

VDD~10V

V
MAX

MIN

TYP

MAX

VDD
MIN

~

UNITS

15V

TYP

MAX

TEST CONDITIONS

tplH

Propagation Delay,

75

150

35

70

24

56

ns

Cl

~50

tPHl

SA, SB, An or Bn to Zn

85

160

37

75

29

60

ns

Rl

~

80

135

42

70

32

45

ns

Input Transition

90

135

40

70

30

45

ns

Times.;; 20 ns

tTlH

Output Transition Time

tTHl

pF,

200 k.r!

NOTES:

1.

Additional DC Characteristics are listed in this section under 40006 Series CMOS Family Characteristics.

2.

Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.

•
TYPICAL ELECTRICAL CHARACTERISTICS

POWER DISSIPATION
VERSUS FREQUENCY
~ 1000
TA,"25 OC,r
II,
I
I

w

eo

""u;,<

..ffi
Z
0

100

10

!:!? 10-3

ffi

.

~
0

Ii'

";

/1

!

;,<

....

11;)? "

I

Voo

104

105

=5 ~t-

INPUT FREQUENCY -

106
Hz

I

PROPAGATION DELAY
VERSUS lOAD CAPACITANCE

101

' 5 JF
90 -2L" 1

~

>

~

10
60

i=

50

"eo;,<
0

g:
I

:5

.!!-

140

80

z

0

1!'iLili
I C I;I~ U1L
I' L
i!! CL" 50 PPF 1111-

~ !I
103

~

~

>
Cl

/?'.

"~V

10-4
102

~

r

I 'Ii'il VOD"'?;'i«,"
' . /
-VOO",15V I ~-!m
..
1'\ ~ ';:>.
,

j

10- 1

i= 10- 2

iii

it

1.0

PROPAGATION DELAY
VERSUS TEMPERATURE
100

~~-J

~

V

"0z

,,~

~

:...- I-'

40
30
20

I

I

__

'100

~

i- F-

VDD~1S"

10

I

a

-60 -40 -20 0
TA -

TI

20 40 60 80100120140

AMBIENT TEMPERATURE - °C

7-41

':'"

."
0

I

~

120

r-

T1"

2~OC

100
80

V

60
40

..--

20

a

J /V
l""./
&Y
I

~
'lJOO '"
'100

"",\~"

~

I

a

20

40

60

80 100 120140 160

CL - LOAD CAPACITANCE - pF

40208
14-STAGE BINARY COUNTER

DESCRIPTION - The 4020B'is a 14-Stage Binary Ripple Counter with a Clock Input (c:P), an
overriding asynchronous Master Reset Input (MR) and twelve fully buffer~ Outputs (00, °3-0131.
The counter advances on the HIGH-to-LOW transition of the Clock Input (CPI. A HIGH on the Master
Reset Input (MR) clears all counter stages and forces all Outputs (°0,°3-°13) LOW, independent
of the Clock Input (CP).

LOGIC SYMBOL

10

•
•
•

25 MHz TYPICAL COUNT FREQUENCY AT VDD = 10 V
COMMON ASYNCHRONOUS MASTER RESET
FULLY BUFFERED OUTPUTS FROM THE FIRST STAGE
AND THE LAST ELEVEN STAGES

Voo = Pin 16
VSS = Pin 8

CONNECTION DIAGRAM
DIP (TOP VIEW)
16
15

14

PIN NAMES

CP
MR
°0,°3-°13

13

Clock Input (H-+L Triggered)
Master Reset Input (Active HIGH)
Parallel Outputs

12

11
10

NOTE:
The F latpak version has the same
pinouts (Connection Diagram) as the
Dual I n-line Package.

LOGIC DIAGRAM
00

®

Voo = Pin 16
VSS "" Pin 8

o

= Pin Number

7-42

FAIRCHILD CMOS • 40208
DC CHARACTERISTICS: VOO as shown, VSS = 0 V (See Note 1)
LIMITS
SYMBOL

PARAMETER

VOO =5 V
MIN

Quiescent
Power

100

Supply
Current

TYP

VOO = 10V

MAX

TYP

MIN

20
150
5
150

XC
XM

MIN

TYP

40
300
10
300

TEMP

TEST CONDITIONS

MIN,25°C
MAX
MIN,25°C
MAX

All inputs at
OVor VOO

UNITS

VOO=15V

MAX

MAX
80
600
20
600

IJ.A
IJ.A

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VOO as shown, VSS = 0 V, TA = 25°C
LIMITS
PARAMETER

SYMBOL

VOO =5 V
MIN

tpLH

Propagation Delay,

tPHL
tpHL
tTLH

CP

to QO

Propagation Delay, MR to Q n
Output Transition Time

TYP

MAX

VOO=10V
MIN

TYP

MAX

UNITS

VOO = 15V
MIN

TYP

MAX

130

260

55

110

37

88

ns

110

220

45

90

33

72

ns

180

360

75

150

50

120

ns

65

135

35

70

25

45

ns

65

135

35

70

25

45

ns

tTHL
twCP(H)

Minimum Clock Pulse Width

100

50

40

20

twMR(H)

Minimum MR Pulse Width

140

70

55

tree

Recovery Time for MR

85

43

35

fMAX

Input Clock Frequency (Note 2)

5

10

12

32

16

ns

27

44,

20

ns

17

28

12

ns

25

14

30

MHz

TEST CONDITIONS

CL = 50 pF,
RL = 200 kn
I nput Transition

Times .. 20 ns

NOTES:
1. Add itional pC Characteristics are listed in this section under 40008 Series CMOS Family Characteristics.
2. For fMAX, input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.
3. It is recommended that input rise and fall times to the Clock Input be tess than 15 j.Ls at VOO "" 5 V, 4p.s at VOO = 10 V, and 3 /Js at

VDD=15V.

7-43

•

FAIRCHILD CMOS • 40208
TYPICAL ELECTRICAL CHARACTERISTICS

~
E1000

I

CLOCK FREQUENCY
VERSUS
POWER SUPPLY VOLTAGE

POWER DISSIPATION
VERSUS CLOCK FREQUENCY
35

T~I!12~O~

w 100

~U

10

f
iii...
~

~

1.0

~ 10- 2
10-3

~

~

![

102

~ 10-4

..-

~~

~~

2

w

/

20

;:)

0

w

II.

>t

U

0
....

U

105

CLOCK FREQUENCY -

105

10
5

o

107

Hz

/'

-

J

15

II:

II III

104

25

>-

CL=15pF-._.
CL = 50pF - - 103

30

U

~p~ =I~ I~

~;/

N

:IE
I

::t

~

~~

~~ ~?

w

II:

f:::

~;?

10- 1

C/l

is

I

1111
VDD = 15 V
VDD = 10 V,

TA = 25°C
CL = 15 pF

V
o

/

II
5

10

15

VDD - POWER SUPPLY VOLTAGE - V

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

PROPAGATION DELAY
VERSUS TEMPERATURE

;

w

Q

~

TA = 25°C
1601--+--+--+--1:-,
1401--+---+-120 I--+::::?,,'F--+ 9f--+---+-~~-;

~

~

80~9--+~~~-+~--+--r-+~

o

...

II:

I

e

I~

201-~---+-~---+--+--+---r~

o
CL - LOAD CAPACITANCE - pF

TA - AMBIENT TEMPERATURE - °C

SWITCHING WAVEFORMS

PROPAGATION DELAY MASTER
RESET. TO OUTPUT. MINIMUM MASTER RESET
PULSE WIDTH AND RECOVERY TIME FOR MASTER RESET

PROPAGATiON DELAY CLOCK TO
OUTPUT 00. OUTPUT TRANSITION
TIMES AND MINIMUM CLOCK PULSE WIDTH

7-44

40218
8-BIT SHIFT REGISTER
DESCRIPTION - The 4021 B is an Edge·Triggered B·Bit Shift Register (Parallel·to·Serial Converter)
with a synchronous Serial Data Input (OS), a Clock Input (CP), an asynchronous active HIGH Parallel
Load Input (PL), eight asynchronous Parallel Data Inputs (PO-P7) and Buffered Parallel Outputs from
the last three stages (Q5-07L
Information on the Parallel Data Inputs (PO-P7) IS asynchronously loaded into the register while the
Parallel Load Input (PL) is HIGH, independent of the Clock (CP) and Serial Data (OS) inputs. Data
present in the register is stored on the HIGH·to·LOW transition of the Parallel Load Input (PLL
When the Parallel Load Input is LOW, data on the Serial Data Input (OS) is shifted into the first
register position and all the data in the register is shifted one position to the right on the LOW·to·
HIGH transition of the Clock Input (CPL

LOGIC SYMBOL

9

76541314151

11

10
2 12 3

•
•
•
•

TYPICAL SHIFT FREQUENCY OF lB.l MHz AT VDD = 10 V
PARALLEL·TO·SERIAL DATA TRANSFER
BUFFERED OUTPUTS AVAILABLE LAST THREE STAGES
CLOCK INPUT IS L -+ H EDGE·TRIGGERED

PIN NAMES
PL
PO-P7

Os
CP
05-07

Voo = Pin 16

Vss = Pin 8

Parallel Load Input
Parallel Data Inputs
Serial Data Input
Clock Input (L-+ H Edge·Triggered)
Buffered Parallel Outputs from the Last Three Stages

CONNECTION DIAGRAM
DIP (TOP VIEW)

16
15
14
13
12

11
10

NOTE:
The F latpak version has the same
pinouts (Connection Diagram) as the
Dual I "-line Package.

LOGIC DIAGRAM

Voo = Pin 16
VSS = Pin 8
= Pin Number

o

7-45

FAIRCHILD CMOS • 40218
DC CHARACTERISTICS: VOO as shown, VSS = 0 V (See Note 1)
LIMITS
SYMBOL

PARAMETER

VOO =5 V
MIN

Quiescent
Power

100

Supply

Current

TYP

VOO = 10 V

MAX

XC

20
150

XM

5
150

MIN

TYP

UNITS

VOO-15 V

MAX

MIN

TYP

TEMP

TEST CONDITIONS

MAX

40
300
10
300

80
600
20
600

MIN,25°C
MAX
MIN,25 C
MAX

IlA
IlA

All inputs at

o V or VOO

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VOO as shown, VSS = 0 V, TA = 25°C (See Note 2)
LIMITS
SYMBOL

PARAMETER

VOO = 10 V

VOO =5 V
MIN

TYP

MAX

MIN

TYP

VOO=15V

MAX

MIN

TYP

UNITS

59

40

ns

74

49

ns

188

78

54

ns

tpHL

274

105

72

ns

tTLH

58

31

22

ns

69

27

22

tPLH

134

Propagation Delay, CP to Q n

tPHL

184

tpLH

Propagation Delay, PL to On
Output Transition Time

,

TEST CONDITIONS

MAX

ns

CL = 50 pF,

twCP

CP Minimum Pulse Width

61

21

14

ns

RL=200kn

twPL

PL Minumum Pulse Width

67

24

16

ns

I nput Transition

tree

PL Recovery Time

71

28

21

ns

Times

ts

Set-Up Time DS to CP

51

16

12

ns

th

Hold Time Os to CP

49

15

11

ns

ts

78

28

18

ns

th

Set-Up Time Pn to PL
Hold Time, Pn to PL

72

26

16

ns

fMAX

Shift Frequency (Note 3)

7.8

18.1

21

MHz

tTHL

~

20 ns

NOTES:

1.
2.
3.
4.

Additional DC Characteristics are listed in this section under 4000B Series CMOS Family Characteristics.
Propagation Delays and Output Transition Times are graphically described in this section under 4000B Series CMOS Family Characteristics.
For fMAX, input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.
It is recommended that input rise and fall times to the Clock Input be less than 15 J..Ls at VDO "" 5 V, 4J..Ls at VDO = 10 V, and 3IJ.s at
VDD=15V.

SWITCHING WAVEFORMS

CP~
l-twPL--~trec

MINIMUM PL PULSE WIDTH, RECOVERY
TIME FOR PL, AND SET·UP AND HOLD TIMES, Pn TO PL

MINIMUM CLOCK PULSE WIDTH
AND SET ·UP AND HOLD TIMES, Os TOCP
NOTE:

Set~up

and Hold Times are shown as positive values but may be specified as negative values.

7-46

40228
4-STAGE DIVIDE-8Y-8 JOHNSON COUNTER
DESCRIPTION - The 40228 is a 4-Stage Divide-by-8 Johnson Counter with eight glitch free active
HIGH Decoded Outputs (°0-071. an active LOW Output from the most significant flip-flop ('4-7!,
an active HIGH and an active LOW Clock Input (CPO, CP1! and an overriding asynchronous Master
Reset Input (MRI.

LOGIC SYMBOL

The counter is advanced by either a LOW-to-H IGH transition at CPO while CP1 is LOW or a HI GH-toLOW transition at CP1 while CPO is HIGH (see Functional Truth Tablel. When cascading the counters,
the '4-7 Output (which is LOW while the counter is in states 4, 5, 6 and 7! can be used to drive the
CPO Input of the next 40228, A HIGH on the Master Reset Input (MR! resets the counter to Zero
(00 = Cl4=7 = HIGH, 01 - 07 = LOW! independent of the Clock Inputs (CPO, CP11.
15

•
•
•

CLOCK EDGE-TRIGGERED ON EITHER A LOW-TO-HIGH TRANSITION OR A
HIGH-TO-LOW TRANSITION
BUFFERED CARRY OUTPUT (D4-7! AVAILABLE FOR CASCADING
BUFFERED FULLY DECODED OUTPUTS

21

J

7114510

= Pin
== Pin
== Pin

16
8
6,9

PIN NAMES
Clock Input (L->H Edge-Triggered!
Clock Input (H->L Edge-Triggered!
Master Reset Input
Decoded Outputs
Carry (Active LOW! Output

CPO
CP 1
MR
°0-°7
°4-7

CONNECTION DIAGRAM
DIP (TOP VIEW!

16

FUNCTIONAL TRUTH TABLE

15

MR

CP 1

H

CPO
X

L

H

H->L

00 - 04-7 - H; 01-07 - L
Cou nter Advances

13

L

L->H

L

Counter Advances

12

L

L

X

No Change

L

X

H

No Change

X

OPERATION

L

H

L->H

No Change

L

L->L

L

No Change

H

Level
= LOW Level

L~H

==

H-+L
X

NC

= Pin

= Pin

VSS

= Pin 8
= Pin Number

a

11
10

= HIGH

=
=

NOTE:

The Flatpak version has the same

LOW-to~HIGH

Transition
HIGH-to-LOW Transition
Don't Care

pinouts (connection Diagram) as the
Dual I n-line package

LOGIC DI,AGRAM

VOO

14

6,9
16

7-47

FAIRCHILD CMOS • 40228
DC CHARACTERISTICS: VDO as shown, VSS = 0 V (See Note 1)
LIMITS
SYMBOL

PARAMETER

VDD =5 V
MIN

Quiescent

Power
IDD

Supply

Current

TYP

MAX

XC
XM

TYP

MIN

UNITS

VDD = 15 V

VDD=10V
MAX

MIN

TYP

TEMP

TEST CONDITIONS

MAX

20

40

80

150

300

600

5

10

20

150

300

600

MIN,25°C
I'A

MAX

All inputs at

MIN,25°C

o Vor VDD

I'A

MAX

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VDO as shown, VSS = 0 V, TA = 25°C (See Note 2)
LIMITS
SYMBOL

PARAMETER

VDD = 5 V
MIN

TYP

MAX

VDO=10V
MIN

TYP

MAX

VDO=15V
MIN

TYP

MAX

UNITS

Propagation Delay,
-

245

615

95

240

60

150

tpHL

CPO or CP1 to On

195

490

75

190

50

125

tpLH

Propagation Delay,

190

490

75

190

50

125

tPHL

CPO or CP1 to 04-7

245

615

90

240

60

150

tPHL

Propagation Delay, MR to On

130

325

55

135

40

100

ns

tPLH

Propagation Delay, MR to Q4-7

110

275

45

110

35

90

ns

70

115

35

90

25

65

70

115

35

90

25

65

tPLH

tTLH

Output Transition Time

tTHL

TEST CONDITIONS

ns
ns

ns

twCP

Min. CPO or CP1 Pulse Width

90

35

40

15

25

10

ns

twMR

Minimum MR Pulse Width

90

35

40

15

25

10

ns

tree

MR Recovery Time

35

10

20

5

15

5

ns

th

Hold Time, CPO to CP1

190

70

85

25

70

15

ns

th

Hold Time, CP1 to CPO

190

85

85

30

70

20

ns

fMAX

Input Count Frequency (Note 3)

2.5

6

7

16

8

24

MHz

CL=50pF,
RL = 200 kil
Input Transition

Times

~

20

1)5

NOTES:

1.
2.
3.
,4.

Additional QC Characteristics are Iisted in this section under 4000B Series CMOS Family Characteristics.
Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.
For fMAX, input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.
It is recommended that input rise and fall times to the Clock I nput be less than 15 jJs at VD D = 5 V, 4 jJs at V DD = 10 V, and 3 MS at
VDD = 15 V.

HOLD TIMES, CPO TO CPt AND CP, TO CPO
NOTE: Note: Hold Times are shown as positive values, but

may be specified as negative values.

MiNIMUM PULSE WIDTHS FOR CP AND MR
AND RECOVERY TIME FOR MR
CONDITIONS:CP, = LOW while CPO is triggered on a LOW-to-HIGH
transition. twCP and tree also apply when CPO = HIGH and CP 1 is
triggered on a HIGH-to-:LOW transition.

7-48

40238
TRIPLE 3-INPUT NAND GATE
DESCRIPTION - This CMOS logic element provides a 3-input positive NAND function. The outputs are fully buffered for highest noise
immunity and pattern insensitivity of output impedance.
LOGIC AND CONNECTION DIAGRAM
DIP (TOP VIEW)

NOTE:
The Flatpak version has the same pinouts
(Connection Diagram) as the Dual In-line
Package.

DC CHARACTERISTICS: VDD as shown, VSS = 0 V (See Note 1)
LIMITS
SYMBOL

PARAMETER

VDD = 5 V
MIN

IDo

Quiescent.
XC
Power
Supply
XM
Current

TYP

VDD = 10 V

MAX

MIN

TYP

MIN

TYP

TEMP

TEST CONDITIONS

MAX

2
15
0.5
15

1
7.5
0.25
7.5

UNITS

VDD=15V

MAX

4
30
1
30

/-lA
/-lA

MIN,25°C
MAX
MIN,25 C
MAX

All inputs at

o V or VDD

AC CHARACTERISTICS: VDD as shown, VSS = 0 V, TA = 25°C (See Note 2)
LIMITS
SYMBOL

tpLH

PARAMETER

VDD =5 V
MIN TYP MAX

Propagation Delay

tPHL
tTLH

Output Transition Time

tTHL
NOTES:
1.
2.

VDD = 10V
MIN TYP MAX

VDD = 15V
MIN TYP MAX

UNITS

TEST CONDITIONS

19

4B

ns

25

60
60

12

4B

ns

RL = 200 kn

1B

70

17

45

ns

I nput Transition

1B

70

12

45

ns

Times ... 20 ns

45
51

110

25

110

45

135

45

135

CL =50 pF,

Additional DC Characteristics are listed in this section under 40008 Series CMOS Family Characteristics.
Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS ·Family Characteristics.

TYPICAL ELECTRICAL CHARACTERISTICS
PROPAGATION DELAY
VERSUS TEMPERATURE
! 40r-r-r-r-'-'--r-r-r-~-'
I

~

CL

=16 of

I .1--r1'

Y

c

36
30

.."c~

20f-+-tpLHtpHLVDD=10V

~ 2.1 ..... ~

"'~L~I tpJL ~~D ~ 6 L

TT TT
J J. J..I.

o'~

;::;or

IE ,. '--r--" 1
-1-,0~1-~'=+~~i=~~-4~

I
'5

•

->

tpLH tpH\ V,/D = 18 V

51-+-+-~-+-+-+-+--+-l

I

I

i !lao-40-20 0 20 co eo eo 1001201CO
TA - AMBIENT TEMPERATURE - 'C

7-49

!

PROPAGATION DELAY
LOAD CAPACITANCE

I~ERSUS

TA = 26°C

I

~120r-~-+--r-~-+--r-~-1
~100r-~-+--r-~-+--r-~-1

~

'PH

f

V
...-::::""""

~ 80
"eo

VD

=.~~
"V
~

........ 1

tpLHVDD

6V

I CO~ ~~tpHi V~~'=I-~

i20E=~$~~~=-~~~
VD~ =
.:.

j

tpLH tpHL

°0

20 40

16 V

80 80 100 120140 ,80

CL - LOAD CAPACITANCE - pF

•

40248
7-STAGE BINARY COUNTER

DESCRIPTION - The 4024B is a 7-Stage Binary Ripple Counter with a Clock Input (CP), an
overriding asynchronous Master Reset Input (MR) and seven fully Buffere
u

TA = 25°C
30 CL = 15 pF

:I:

~

I

w

a.
Z

25

Z
w

20

0

15

w

~

~

U

'"i5

10

...J

U

5

1/

o

107

o

PROPAGATION DELAY

~ 180.--_V,.E_R_STU_S_L,O_A_D..,-C_A...,P,A_C_ITrA_N_C,.E--,

..
c

160

;

140

5
10
15
VDD - POWER SUPPLY VOLTAGE - V
PROPAGATION DELAY
VERSUS TEMPERATURE
CL = 15 pF

TA=25°C

160~-r--b-~--~

w. 140 ~-+--+---+---+---~~;....e:1-----i

w

o
~

o

~

120~-+--+---+--~~

~

100

~

80

~

60~-=~+---+---+-~~~~~---i

o

/

0

CLOCK FREQUENCY - Hz

I

V

0:

u.

iii

/

/

:::I

o

;

I

lL':

~
~

o

0:

a.
I

a

20~~~~-+~~~~+-~~

120
VDD = 5 V

100
tPLH ......

80
60
40
20

-:: ~

-

SWITCHING WAVEFORMS

50%

1~+-tWMR----+I-~trec

1500,

\50%

-----'

MINIMUM PULSE WIDTH

FOR

:~

~

r-: t::;;; a 5 V

VDID = 10

J--' ~

\1~ tP~~ t-}D'1 = 15 V

-60 -40 -20 0 20 40 60 80100120140
TA - AM81ENT TEMPERATURE - °c

CL - LOAD CAPACITANCE - pF

MR

-

tpLH

o

°O~~~~~~~~~~~~

I-":I-:::+I-- tPHL

CP AND MR AND MR RECOVERY TIME

7-52

40258
TRIPLE 3-INPUT NOR GATE
DESCRIPTION - This CMOS logic element provides a 3-input positive NOR function. The outputs are fully buffered for highest noise immunity
and pattern insensitivity of output impedance.
LOGIC AND CONNECTION DIAGRAM
DIP (TOP VIEW)
VDD

NOTE:
The

Flatpak version has the same pinouts

(Connection Diagram) as the Dual In-line Package.

DC CHARACTERISTICS: VOO as shown, VSS = 0 V (See Note 1)
LIMITS
SYMBOL

PARAMETER

Quiescent
100

Power
Supply
Current

Voo =5 V
MIN TYP MAX

XC

Voo = 10 V
MIN TYP MAX

7.5
0.25
7.5

XM

UNITS

VOO=15V
MIN

TYP

TEMP

TEST CONDITIONS

MAX

2

4

15
0.5
15

30

MIN,25°C
MAX
MIN,25°C
MAX

/oIA

1

/oIA

30

All inputs at

o Vor VOO

AC CHARACTERISTICS: VOO as shown, VSS = 0 V, T A = 25°C (See Note 2)
LIMITS
SYMBOL

PARAMETER

VOO =5 V
MIN

VOO=10V

TYP

MAX

45

110

MIN

TYP

MAX

20

UNITS

VOO = 15V
MIN

TYP

MAX

15

4B

ns

21

TEST CONDITIONS

CL=50pF,

tpHL

47

110

25

60
60

RL = 200 kn

38

135

20

70

15

4B
45

ns

ITLH

ns

Input Transition

38

135

15

70

11

45

ns

Ti mes .; 20 ns

tPLH

Propagetion Delay
Output Transistion Time

tTHL
NOTES:
1.
2.

Additional DC Characteristics are I!sted in this section under 4000B Series CMOS Family Characteris~ics.
Propagation Delays and Output Transition Times·are graphically described in this section under 40008 Series CMOS Family Characteristics.

TYPICAL ELECTRICAL CHARACTEi'tISTICS
PROPAGATION DELAY
VERSUS TEMPERATURE

2

~

~

36~+-+-~,~
~~~~+-+-+-1

oJ

CL='6pF

V-

I

~rtpHLVDD=6V

~

_

26r-+-+--I::..+-"
l....ht"'''hH-_l+-+-+-I

.............. tpLHVDD=6V
~ 20~T-+-+-+-1--r-+-+-+-I
tpLH tPHL Voo

=10 V 1

_

IE '5f-i-'_"-i--'~'*"--;:==-=""'1-tJ.."'9_=--t-1
I

:s

8-

,01=;;j;;;:;+:~..f::~H=++--l
tPLH tpHL VOD =16 V
0

Hz

~'20r-+-1--4--4--+--+--+--I

~,001--~~--4-~--+--+--t-~
o
I
/ ....

~

801-

tp~LVIWV

40

8°1-C7!,/~ . . .-:r. . -1F:. .k=- -jf-:-:-tp:;I- "' ' LH'- 'tD' -', ' - t=. :c6-'-1V
o '--'

'00120 '40

TA - AMBIENT TEMPERATURE - °C

7-53

...

IEI 40
~ 20:...--tP~Htp~

6~+-+-+--+--+-+-+-4-1~

i ~60-40-20 ~o 8~ 8~
INPUT FREQUENCY -

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

c 140

I

~ 30r.,~9-~-r-T-~-r~~-~r1

~

•

o w

tPLH
~

~

t~HL ~D ~ , 6 ~
~'OO'W,~,~

CL - LOAD CAPACITANCE - pF

•

40278
DUAL JK FLIP-FLOP

DESCRIPTION - The 4027B is a Dual JK Flip-Flop which is edge-triggered and features independent
Direct Set, Direct Clear, and Clock inputs. Data is accepted when the Clock is LOW and transferred to
the output on the positive.going edge of the Clock. The active HIGH asynchronous Clear Direct (CD)
and Set Direct (SO) are independent and override the J, K, or Clock inputs. The outputs are buffered
for best system perfOrmance.

LOGIC SYMBOL

15

10

I

13

I

~14

11

PIN NAMES

J, K

12

Synchronous Inputs
Clock Input (L'" HEdge-Triggered)
Asynchronous Direct Set Input (Active HIGH)
Asynchronous Direct Clear Input (Active HIGH)
True Output
Complement Output

CP
So
CD
Q

0:

_-+-_~~~:r--""" I

I
I
I

CP

K

Q

0---+-

L--~
--;--.....;....1

2

I

____ .J
Voo = Pin 16
VSS = Pin 8

TRUTH TABLES

ASYNCHRONOUS
INPUTS

OUTPUTS

SYNCHRONOUS
INPUTS

CONNECTION DIAGRAMS
DIP (TOP VIEW)
OUTPUTS

So
L

CD
H

Q

Q

CP

J

K

L

H

.r

L

L

H

L

H

L

H

L

H

H

H

H

L

H

L

H

H

H

an

Qn

..r
..r

.r

L

= LOW Level
H
= HIGH Level
.r
= Positive-Going Transition
Q.,+1 == State After Clock Positive

Qn+l
Qn+l
NO CHANGE
H

16

15

L

14

4

13

Conditions: So = Co = LOW
12
11

Transition

10

8

NOTE:
The F latpak version has the same
pinouts (ConnectiOn Diagram) as the
Dual I n~line Package.

7-54

FAIRCHILD CMOS • 40278
DC CHARACTERISTICS: VDD as shown, VSS = 0 V (See Note 11
LIMITS
SYMBOL

PARAMETER
MIN
Quiescent

IDD

Power

Supply
Current

VDD = 10V

VDD =5 V
TYP

XC
XM

MAX

MIN

TYP

4
30
1
30

MIN

TYP

8
2

60

TEST CONDITION S

MIN,25°C
MAX
MIN,25°C
MAX

All inputs at
OV or VDD

MAX
16
120
4
120

60

TEMP

UNITS

VDD=15V

MAX

!J.A
!J.A

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VDD as shown, VSS = 0 V, TA = 25°C (See Note 31
LIMITS
SYMBOL

PARAMETER

VDD - 5 V
MIN

tpLH

Propagation Delay, CP to Q, Q

tPHL

TYP

MAX

VDD-l0V
MIN

TYP

MAX

UNITS

VDD = 15V
MIN

TYP

MAX

100

200

45

85

30

68

ns

100

200

45

85

30

68

ns

tpLH

Propagation Delay, SD to Q

180

350

90

175

75

140

ns

tpHL

Propagation Delay, CD to Q

180

350

90

175

75

140

ns

85

150

45

85

30

50

ns

85

150

45

85

30

50

ns

ITLH
ITHL
ts

Output Transition Time
Set-Up Time, J, K to CP
Hold Time, J, K to CP

TEST CONDITIONS

CL = 50 pF,

100

45

40

20

32

15

ns

RL = 200 k!1

0

-25

0

-10

0

-5

ns

Input Transition

Times.,,;; 20 ns

th
twCP(LI

Minimum Clock Pulse Width

150

75

70

35

56

25

ns

twSD(HI

Minimum SD Pulse Width

150

75

60

30

48

25

ns

twCD(HI

Minimum CD Pulse Width

150

75

60

30

48

25

ns

trecSD

Recovery Time for SD

0

-5

0

-4

0

-3

ns

trecCD

Recovery Time for CD

0

-5

0

-4

0

-3

ns

fMAX

Maximum CP Frequency (Note 21

4

8

8

16

9

19

MHz

NOTES:
1. Additional DC Characteristics are listed in this section under 40008 Series CMOS Family Characteristics.
2. For fMAX input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.
3. Propagation Delays and Output Transition Times are graphically described in this section under 4oo0B Series CMOS Family Characteristics.
4. It is recommended that input rise and fall times to the Clock Input be less than 15!J.s at VDD = 5 V, 4!J.s at VDD = 10 V, and 3!J.s at
VDD = 15 V.

•

FAIRCHILD CMOS • 40278
TYPICAL ELECTRICAL CHARACTERISTICS
POWER DISSIPATION
VERSUS FREQUENCY

PROPAGATION DELAY
VERSUS TEMPERATURE
l!!100

1 90

VDD = 5V

; 80
w
C 70
Z
o 60

~

~ f"'"

50

~

40

IE

30

o

l! 300
1

~

~

rv.rD = 15V

-60-40-20 0 20 40 60 80100120140
TA - AMBIENT TEMPERATURE - °C

1180

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE
TA = 25°C

./~

>-

~160

250

w

C

VD~=~

°140
Z

200r---~~-r---r---+---+--~

Z

o

~120

~
~

o~

IE

IE

1

e

V

80
60

1 40
d

50

e 20

II.
(J

II.
(J

VOD - POWER SUPPLY VOLTAGE - V

./"

..... V

~100

1501----f'r--+'~

o
d

-- -- -

o

I! 200

TA = 25°C

I--"'"

10

II.
(J

PROPAGATION DELAY
VERSUS POWER SUPPLY VOLTAGE

~

-

1 20

103
INPUT FREQUENCY - Hz

~

VDD=10V

a

e

--

CL= 15 pF

I--

~

m

JDD=~

-...-

40

60

~

~

~r-

60 100 1m 140160

CL - LOAD CAPACITANCE - pF

SWITCHING WAVEFORMS

""1

l-twSOIH)

so~_____________________

Co

--

-------+----'.

CP

NOTE:
ts & th are shown 8S positive values but may be
specified as negative values.

SET·UP TIMES, HOLD TIMES,
AND MINIMUM CLOCK PULSE WIDTH

RECOVERY TIME FOR SO, RECOVERY TIME FOR CD,
MINIMUM So PULSE WIDTH, AND MINIMUM CD PULSE WIDTH

7-56

40288
I-Of-IO DECODER
DESCRIPTION - The 40288 is a CMOS 4 8it BCD to 1-of-l0 active HIGH decoder. A 1-2-4-8 BCD
code applied to inputs AO through A3 causes the selected output to be HIGH, the other nine will be
LOW. If desired, the 4028B may be used as a 1-of-8 decoder with enable; 3-bit octal inputs are applied
to inputs AO, Al, and A2 selecting an output 0 through 7. Input A3 then becomes an active LOW
enable, forcing the selected output LOW when A3 is HIGH. The 4028B may also be used as an 8-input
demultiplexer with an active LOW data input. The outputs are fully buffered for best performance.
•
•
•

LOGIC SYMBOL

BCD TO 1-0F-l0 DECODER
1-0F-8 DECODER WITH ACTIVE LOW ENABLE
a-INPUT DEMULTIPLEXER WITH ACTIVE LOW DATA INPUT

10 13 12 11

40288

PIN NAMES
Ao- A 3
00- 0 9

Address Inputs, 1-2-4-8 BCD
Outputs (Active HIGH)

3 14 2 15 1 6

7 4 9 5

TRUTH TABLE
OUTPUTS

INPUTS
AO

Voo = Pin 16

A3

A2

Al

L

L

L

L

H

L

L

L

L

L

L

L

L

L

L

L

L

H

L

H

L

L

L

L

L

L

L

L

L

L

H

L

L

L

H

L

L

L

L

L

L

L

L

L

H

H

L

L

L

H

L

L

L

L

L

L

L

H

L

L

L

L

L

L

H

L

L

L

L

L

L

H

L

H

L

L

L

L

L

H

L

L

L

L

L

L

L
L

VSS = Pin 8

00 01 02 0 3 0 4 0 5 0 6 07 08 09

L

H

H

L

L

L

L

L

L

L

H

L

H

H

H

L

L

L

L

L

L

L

H

L

H

L

L

L

L

L

L

L

L

L

L

L

H

L

H

L

L

H

L

L

L

L

L

L

L

L

L

H

H

L

H

L

L

L

L

L

L

L

L

L

H

L

H

L

H

H

L

L

L

L

L

L

L

L

L

H

H

H

L

L

L

L

L

L

L

L

L

L

H

L

H

H

L

H

L

L

L

L

L

L

L

L

L

H

H

H

H

L

L

L

L

L

L

L

L

L

H

L

H

H

H

H

L

L

L

L

L

L

L

L

L

H

CONNECTION DIAGRAM
DIP (TOP VIEW)

15
14

12

Voo
VSS

a

= Pin 16
= Pin 8
= Pin Number

7-57

11

6

10
--...;=--~

H = HIGH Level
L= LOW Level

LOGIC DIAGRAM

13

4

9

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual I n~line Package.
'

FAIRCHILD CMOS • 4028B
DC CHARACTERISTICS: VDD as shown, VSS

~

0 V (See Note 1)
LIMITS

MIN

Quiescent
Power
Supply

100

TYP

MAX

MIN

TYP

XM

VDD~15V

MAX

20
150
5
150

XC

CUrrent

VDD~10V

VDD~5V

PARAMETER

SYMBOL

MIN

TYP

40
300
10
300

UNITS

TEMP

TEST CONDITIONS

MAX
80
600
20
600

MIN,25°C
MAX
MIN,25°C
MAX

j.tA
j.tA

All inputs at
or VDD

oV

AC CHARACTERISTICS: VDD as shown, VSS ~ 0 V, TA ~ 25°C (See Note 2)
LIMITS
SYMBOL

PARAMETER

VDD

MIN
tPLH

Propagation Delay An to On

~

VDD ~ 10 V

5V

TYP

MAX

167
157

MIN

VDD ~ 15V

MAX

145

45

53

ns

CL

145

40

46

ns

RL~200kn

40

100

31

70

ns

I nput Transition

37

100

25

70

ns

Times

MAX

325

66

325

57

85

200

110

200

MIN

I

tPHL
tTLH

Output Transistion Time

tTHL

TEST CONDITIONS

UNITS

TYP

TYP

~50

~

pF,

20 ns

NOTES,
1. Additional DC Characteristics are listed in this section under 40008 Series CMOS Family Characteristics.
2. Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS FamilY Characteristics.

TYPICAL ELECTRICAL CHARACTERISTICS

POWER DISSIPATION
VERSUS FREQUENCY

"

E 1000

I
w

co
~

"~
~
~

~

TA

i

'~: i II I iIII

Voo = 10V

1.0

I••.·•·

10-1

~ 10- 2

~ 10- 3

~ 10- 4

",

...
..

...

.. ...

..,.
,

I
103

~

i

.' .... tf;.
.. ..... .. ...
........
I
...

I
!

:::

102

i

....

Voo - 15V

'"'"

it

=26°~11

10'

INPUT FREQUENCY -

106
Hz

0

80

I

10.7

140
120

'"06
i2
0

"

CL"'15pF

160

~co

;t

Cl - 15 pF
Cl 50. pF ..•..
105

~
0
Z

I

200

I
> 180

0

1

,DIII15IV!

PROPAGATION DELAY
VERSUS TEMPERATURE

~

i -i -

1

1

I

1

60

z

0

t:::

-20

20

--

";t"

150

g:

100

0

I

J
I-

100

140

TA - AMBIENT TEMPERATURE - °C

7-58

~

a
a

~~

I
I.

\~

.fl
.L

tp\..M

50

0

60

25~C

200

;::

I

-60

TA ;

~
0

,

"OD~'O~
r- i ~ i - ~~\5V

20

a

---

I
1

'O~

> 250

1

100

300

I

"oo~~--

I--" I-"""
I

~

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

V

tP1l

I

V~D ~ l' a v

~OD~'O~

~ODd5V
'PH

20

I

.0

J.

""'" f-

'I tPlH VDD ~ 15
60

v i"

80. 10.0120 140. 160.

CL - LOAD CAPACITANCE -

pF

4029B
SYNCHRONOUS UP/DOWN COUNTER
DESCRIPTION - The 4029B is a Synchronous Edge-Triggered Up/Down 4-Bit Binary/BCD Decade
Counter with a Clock Input (CP),an active LOW Count Enable Input (CE),an Up/Down Control Input
(UP/DN), a Binary/Decade Control Input (BIN/DEC), an overriding asynchronous active HIGH
Parallel Load Input (PL), four Parallel Data"'!!!puts (PO-P3), four Parallel Buffered Outputs (QO-Q3)
and an active LOW Terminal Count Output (TCl.
Information on the Parallel Inputs (PO-P3) is loaded into the counter while the Parallel Load Input
(pL) is HIGH, independent of all other input conditions. With the Parallel Load Input (PL) LOW,
operation is synchronous and is edge-triggered on the LOW-to-HIGH transition of the Clock Input
(CP). Operation is determined by the three synchronous Mode Control Inputs; UP/DN, BIN/DEC and
CE (see the Mode Selection Tablel. These inputs must be stable only during the set-up time prior to
the LOW-to-HIGH transition of the Clock Input (CP) and the hold time after this clock transition.

LOGIC SYMBOL
4

12 13

UP/DN

10

TC

4029B

CE

3

CP

15

The Terminal Count Output (Te) is LOW when the counter is at its terminal count, as determined by
the counting mode, and the Count Enable Input (CE) is LOW (see Logic Equation for TCI.

6

11

14

2

Voo = Pin 16

•
•
•
•
•
•

BINARY OR DECADE UP/DOWN COUNTER
ASYNCHRONOUSPARALLELLOAD
ACTIVE LOW COUNT ENABLE
CLOCK EDGE-TRIGGERED ON THE LOW-TO-HIGH TRANSITION
ACTIVE LOW TERMINAL COUNT FOR CASCADING
TYPICAL COUNT FREQUENCY OF 12 MHz AT VDD = 10 V

PIN NAMES
PL
PO-P3
BIN/DEC
UP/DN
CE
CP

00- Q3
TC

VSS

= Pin

8

CONNECTION DIAGRAM
DIP (TOP VIEW)

Parallel Load Input
Parallel Data Inputs
Binary/Decade Control Input
Up/Down Control Input
Count Enable Input (Active LOW)
Clock Input (L--+H Edge-Triggered)
Buffered Parallel Outputs
Terminal Count Output IActive LOW)

16
15
14

13

•

12
11

MODE SELECTION TABLE

10

CE

CP

MODE

X

X

X

Parallel Load (P n --+ Qn)

X

H

X

No Change

L

L

..r

Count Down, Decade

H

L

J"

Count Up, Decade

H"'" HIGH Level

L = LOW Level

PL

BIN/DEC

UP/DN

H

X

L

X

L

L

L

L

L

H

L

L

J"

Count Down, Binary

L

H

H

L

.r

Count Up, Binary

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual In-I ine Package.

X = Don't Care

I = Positive-Going Transition

4029B STATE DIAGRAM, BIN/DEC = LOW

4029B STATE DIAGRAM, BIN/DEC = HIGH

~w

b

~~-o~-~
Et--L.:.:.J-t..:J----t..::..I~

CQUNTUP--COUNT DQWN- -

~

-

LOGIC EQUATION FOR TERMINAL COUNT
TC

= CE

• [UP. QO • Q 3 • (SIN + (Q1 • Q2)) +

(UP •

7-59

QO • Q, • Q2 • Q3)]

COUNTUP--COUNT OaWN- -

-

FAIRCHILD CMOS • 4029B
LOGIC DIAGRAM

Voo

=:

Pin 16

VSS = Pin 8

o

fi
,

e,

C,

Q

Q

= Pin Number

PC (Parallel Load Input) - Asynchronously Loads P into a, Overriding all Other Inputs
P (Parallel Input) - Data on this Pin is Asynchronously Loaded into a, when PI. is LOW Overriding all Other Inputs
Input) - Forces the Q Output to Synchronously Toggle when a LOW is Placed on this Input.
CP (Clock Pulse Input)
Q, Q (True and Complimentary Outputs)

T (Toggle

DC CHARACTERISTICS: VOD as shown, VSS = 0 V iSee Note 1)

LIMITS
SYMBOL

PARAMETER
MIN

IDD

Quiescent
Power

XC

Supply
Current

XM

VDD -10 V

VDD - 5 V
TYP

MAX
20
150
5
150

MIN

TYP

MAX
40
300
10
300

Notes on following page.

7-60

VDD -15 V
MIN

TYP

UNITS

TEMP

TEST CONDITIONS

MAX
80
600
20
600

p.A
p.A

MIN,25°C
MAX
MIN,25°C
MAX

All inputs at

o Vor VDD

FAIRCHILD CMOS • 4029B
AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VDD as shown, VSS ~ 0 V, TA ~ 25°C (See Note 3)
LIMITS
SYMBOL

PARAMETER

VDD
MIN

~

VDD

5V

TYP

MAX

MIN

~

10 V

TYP

MAX

VDD
MIN

~

TYP

UNITS

15V

150

350

62

160

41

128

ns

tpHL

150

350

59

160

39

128

ns

tPLH

167

450

71

180

48

144

ns

252

650

100

245

66

196

ns

tPLH

Propagation Delay, CP to

an

Propagation Delay, CP to TC

tPHL

170

325

70

150

45

120

ns

tpHL

220

450

90

195

62

156

ns

lTLH

60

135

31

75

23

45

ns

65

135

25

75

18

45

ns

tPLH

Propagation Delay, PL to an

Output Transition Time

tTHL
CP Minimum Pulse Width

125

50

60

21

PL Minumum Pulse Width

150

60

55

21

tree

PL Recovery Time

ts

Set-Up Time, BIN/DEC to CP

150
250

62
106

60
100

24
41

twCP
twPL

48
44
48

14

ns

CL

16

ns

RL~200kn

ns
ns

Times:s;,;; 20 ns

ns

th

Hold Time, BIN/DEC to CP

0

-90

0

-35

0

17
29
-25

ts

Set-Up Time, UP/DN to CP

325

145

130

55

104

38

th

Hold Time, UP/DN to CP

0

-90

0

-35

0

-25

ns

ts

Set-Up Time, CE to CP
Hold Time, CE to CP

275

118

120

49

96

23

ns

0

-40

0

-15

0

-10

ns

70

29

30

11

24

8

ns

th

Set-Up Time, Pn to PL
Hold Time, Pn to PL

0

-40

0

-20

0

-20

fMAX

Input Clock Frequency (Note 2)

2

5

5

12

6

14

th
ts

80

TEST CONDITIONS

MAX

~50

pF,

Input Transition

ns

ns
MHz

NOTES:
1. Additional DC Characteristics are listed in this section under 40008 Series CMOS Family Characteristics.
2. For fMAX input rise and fall times are greater than or equal to'5 ns and less than or equal to 20 ns.
3. Propagation Delays and Output Transition Times are graphically described in this section under 4000B Series CMOS Family Characteristics.
4.

It is recommended that input rise and fall times to the Clock Input be less than 15J,1.s at VOO = 5 V. 4j.Ls at VOO

=

10 V, and 3J,.ts at

VDD~15V.

SWITCHING WAVEFORMS

CP

ts_

50%

....---th--+-

50%

BIN/DEC

UP/ON

MINIMUM CP WIDTH, SET-UP AND HOLD
TIMES, CE TO CP, BIN/DEC TO CP AND UP/ON TO CP

MINIMUM PL PULSE WIDTH, RECOVERY
TIME FOR PL, AND SET-UP AND HOLD TIMES, Pn TO PL

NOTE: Set-up and Hold Times are shown as positive values but may be specified as neg,ative values.

7-61

•

FAIRCHILD CMOS • 4029B
TYPICAL ELECTRICAL CHARACTERISTICS

.

c
~
E 1000

I

w
Cl 100

'I!

c(
~

U

c(

10
1.0

"-

iii

c(
....

~,M
,

VDD

104

15 pF

VDD

140

,., ~ ~

z

0 100

i=
c(

III

Cl
c(

60

"-

40

I

20

....

111I

80

"0

II:

CL~50pF--

105

~

JPLHI- I-1\ ·1

160

C 120

5 V
i

CL

180

w

l

~

I ill

Ii
II

iI
103

II,

II-<~

c
d 200
0

CL-15pF

, I

10-3

~ 10-4
~
102

-<
....

PROPAGATION DELAY
VERSUS TEMPERATURE

I

POWER DISSIPATION
VERSUS FREQUENCY

106

INPUT FREQUENCY -

107

Hz

~

1~ V

I--

~PL~

I--

'r-

li~

VDD~10V

I
VIOD I

ip~~

I

V

Q60 -40 -20 0

i
....

5 V

'""""
........ f-:::: :...--'

J:

e-

~

\

.1i
I--~~HL-

I "j

20 40 60 80100120140

TA - AM81ENT TEMPERATURE -

e-

°C

..
c

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

I

c
d 240
0
220

r-I .I. L
tPH\L

_TA~25°C

....

"- 200
u

:>

VDD~5V\:~

180

~
w 160

c

140

O

120

z

~

Cl

~

0

a:

"-

...J:I

e-

...i
So

p-

-

r-

~
...-:::. ;:::.- tPLH-

tPL~ I--

100
80

~

60
40
20
0

O

I--VDD=10r""

r-

J '1 =

r20
CL -

F~

40

60

T

15V
100 I
I
80 100120140160

LOAD CAPACITANCE -

pF

APPLICATIONS
Interconnection techniques for multistage counting are shown in Figures 1 through 4. When using the schemes shown in Figures 1,3 and 4, the
BIN/DEC and UP/ON Inputs may be changed only when the Clock Input to the first stage is HIGH. However, when using the scheme shown
in Figure 2, UP/ON, BIN/DEC and CE may be changed independent of the state of the Clock Input. The methods illustrated in Figures 1 and

3 will operate with long transition times at the Clock Input to the first counter; whereas, the other schemes require a fast transition at the
Clock Input.
Figure 1 is a ripple clock expansion scheme in which the maximum counting frequency is limited only by the frequency capability of the first
counter. The disadvantage of this technique is that the Outputs of the most significant stage do not change until the clock has rippled through
all the preceding stages.
A fully synchronous expansion method is shown in Figure 2. Since the Clock Input is applied simultaneously to all stages, the Outputs of all
stages change simultaneously. The maximum counting frequency is limited by the time required for the Count Enable to ripple through all the
stages before the next Clock Input is applied.
The semi·synchronous technique illustrated in Figure 3 allows a higher counting frequency than the method shown in Figure 2 by ~wing TC
to take either 10 or 16 clock periods to ripple from the second stage to the most significant stage (10 clock periods when BIN/DEC = L, 16
clock periods when BIN/DEC = HI. The Outputs of all stages, except the first, change simultaneously. The Outputs of the first stage change
before the other stages.
The speed advantage of this scheme is lost if the count direction or count modulus is rapidly changed.
The method shown in Figure 4 is the same as in Figure 3 except an external gate is added to reduce the delay between the Clock Input to the
first stage and the Clock Input to the following stages.

7-62

FAIRCHILD CMOS • 4029B
APPLICATIONS (Cont'd)

PARALLEL LOAD
BIN/DEC

UP/i5'5"WN

Po P,

P2

P3

--

" - BIN/DEC

CLOCK

1111P3

I I I I

PL

' - - UP/Dfii
4029B
CE
CP
00 a, 02 03

'--TC

-C

PL

Po P,

4029B

TC

a, 02 03

00

I I I I

P2 P3

' - - - UP/ON

UP/ON

CP

Po P,

" - BIN/DEC

BIN/DEC

CE

L

TO MORE
SIGNIFICANT
STAGES

1111

PL

P2

4029B

CE

L

TC

p--....

CP
00 Q, 02 03

I I I I

I I I I

Fig.1 RIPPLE CLOCK EXPANSION

PARALLEL LOAD

BIN/DEC
UP/DOWN

I I I I

PL

L- BIN/DEC
COUNT

ENABLE
(ACTIVE LOW)

CLOCK

Po P,

L- BIN/DEC

' - - - UP/ON

Po P,

----<: CE

TC

L-

00 0, 02 Q3

CE

I I I I

r

00

a,

02

P2 P3

BIN/DEC

TO MORE
SIGNIFICANT
STAGES

' - - - uP/DN

40298

CP

CP

I I 11

Po P,

PL

P2 P3

' - - UP/Drii"
40298

r

JJ IJ

PL

P2 P3

TC

4029B

CE

TCjO--

r

CP

03

I I I I

00

a,

02 Q3

I I I I

Fig. 2 PARALLEL CLOCK EXPANSION (FULLY SYNCHRONOUS)

PARAllEL LOAD ----------.-------------------------~------------------------~~---------------

BIN/DEC

----~----+_------------------_t----_t-------------------p_--__1r_-------------

UP/DOWN --.-~----+_----------------~_t----_t----------------_1r_t_----r_-------------

I I I I
......
'--CLOCK

~

PL

Po P,

P2

UP/ON

CP
00

a,

I I I I
PL

P2 P3

BIN/DEC

4029B

CE
T C P - r f CP

Q2 03

00

I I I I

Po P,

P2 P3
TO MORE
SIGNIFICANT

BIN/DEC

L...- UP/ON

40298

CE

I I I I

Po P,

PL

P3
L-

BIN/DEC

UP/ON

TC:p----OI CE

STAGES

4029B

TCp--

01 02 Q3

I I I I
Fig. 3 SEMI·SYNCHRONOUS EXPANSION

PARALLELLOAD----------~------------------------_t-------------------------p_------------~~

BIN/DEC----~----1r------------------_,----_+--------------------t_----r_------------~~

UP/DOWN--t_~----+_----------------~_+----_t----------------_1~r_--__1r_------------~.

UP/ON

UP/DN
4029B

UP/ON
4029B

CLOCK

TC(o-----oI CE
CP

Fig.4 HIGH SPEEO SEMI·SYNCHRONOUS EXPANSION

7-63

4029B

TC

TO MORE
SIGNIFICANT
STAGES

•

40308
QUAD EXCLUSIVE -OR GATE
DESCRIPTION - The 4030B CMOS logic element provides the Exclusive·OR function. The outputs are fully buffered for best performance.
The 4030B is a direct replacement for the 74C86/54C86 and the 14507.

F4030 QUAD EXCLUSIVE·OR GATE

NOTE:
The F latpak version has the same
pinouts (Connection Diagram) as the

Dual

x = AB

In~line

Package.

+ AS

DC CHARACTERISTICS: VDD as shown, VSS = 0 V (See Note 1)
LIMITS
SYMBOL

PARAMETER

VDD =5 V
TYP

MIN
Quiescent
Power

IDD

MAX

XM

Current

MIN

TYP

UNITS

VDD = 15 V

MAX

1
7.5
0.25
7.5

XC

Supply

VDD = 10 V

TYP

MIN

TEMP

TEST CONDITIONS

MAX

2

4

15
0.5
15

30

MIN,25°C
MAX
MIN,25°C
MAX

!J-A

1

!J-A

30

All inputs at

o Vor VDD

AC CHARACTERISTICS: VDD as shown, VSS = 0 V, TA = 25°C (See Note 2)
LIMITS
PARAMETER

SYMBOL

VDD = 10 V

VDD =5 V
MIN

TYP

MAX

MIN

UNITS

VDD = 15V

TYP

MAX

MIN

TYP

MAX

TEST CONDITIONS

85

170

45

90

27

CL = 50 pF,

85

170

45

90

27

72
72

ns

tPHL

ns

RL = 200 kll

tTLH

50

100

23

50

17

35

ns

J nput

50

100

23

50

17

35

ns

Times

tpLH

Propagation Delay, A or B to X
Output Transition Time

tTHL

Transition
~

20 ns

NOT"ES:
1.

2.

Additional DC Characteristics are listed in this section under 4000B Series CMOS Family Characteristics.
Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.

TYPICAL ELECTRICAL CHARACTERISTICS

;:
E 1000

~

CJ

~

100

()

10

~

10

~

TflllTil
'I II

I II: I, , '

I

1

VOO"10V
I

:~'i ~.~II

, ,

VDO=15~,t--~'"
!

!I

I

:~

Q 10-1

~r

ft:'

:0-

".

~

VOO"6V

ffi

~

~a;;~,

10.

3

1 I.' I I

~ 10-~O2

iI

103

104

~

,

!

Iii;

~ 10-2 ...!/~~

lil

i Ii
I~L:'5PFCL-50pF __

10S

INPUT FREQUENCY -

106
Hz.

PROPAGATION DELAY.
VERSUS LOAD CAPACITANCE
I 140 TA 25°C

c

I 100 CL = 15 pF

!

!

.

PROPAGATION DELAY
VERSUS TEMPERATURE

c

,

I ,

"

.

POWER DISSIPATION
VERSUS FREQUENCY

107

>-

80

z
0

70

~

60

""
o.
0
0:
o.
~

""a:
~
I

~

!

>-

90

~
0

50

I

~OD"S~

f:::'

0-

~

~

0
Z
0

0

0:

40

~

""
~

-L

20l=r-:

Voo

10
0

15V -

I

7-64

~

V
"00=10" _

40
20

f---

I

~

2040 60 80 100120140

AMBIENT TEMPERATURE -

60

o.

\l00=10V

TA -

80

o.

30

I~~"I./" ./"

100

>=

"""

I---

~60-40-20

:0

120

°c

:r

a-

00

20

--

40

~

60

r--

i

80 100 120140 160

CL - LOAD CAPACITANCE - pF

40318
64-STAGE STATIC SHIFT REGISTE

DESCRIPTION - The 4031B is an edge-triggered 64-Stage Static Shift Register with two Serial Data
Inputs (DO, 01 I, a Data Select Input (S). a Clock Input (CPI, a buffered Clock Output (COl and buffered Outputs from the 64th bit position (0s3, 0631.
Data from the selected Data Inputs (DO or 01 I, as determined by the state of the Select Input (SI, is
shifted into the first shift register position and all the data in the register is shifted one position to the
right on the LOW-to-HIGH transition of the Clock Input (CPl. DO is selected by a LOW on the Select
Input (SI and 01 is selected by a HIGH on the Select Input (S).

LOGIC SYMBOL

15

10

Registers can be cascaded by connecting all the Clock Inputs (CPI together or by driving the Clock Input (CPI of the right-most register with the system clock and connecting the Clock Output (COl to the
Clock Input (CPI of the preceding register. When the second technique is used in the recirculating mode,
a flip-flop must be used to store the Output (°631 of the right-most register until the left-most register
is clocked.
•
•
•
•

CLOCK INPUT IS L-H EDGE·TRIGGERED
DATA SELECT INPUT (SI ALLOWS DATA INPUT AT EITHER
DO OR 01 INPUTS
EASILY CASCADED
TRUE
AND
COMPLEMENTARY BUFFERED OUTPUTS
AVAILABLE FROM 64TH STAGE

oro

40318
CP

063

co

V OD =Pin16
Vss = Pin 8

NC

= Pins 3.4,5,11,12,13,14

CONNECTION DIAGRAM
DIP (TOP VIEWI

PIN NAMES
00,01
S
CP
CO
063

1

Data Inputs
Data Select Input
Clock Input (L-H Edge-Triggeredl
Buffered Clock Output
Buffered Output from the 64th Stage
Complementary Buffered Output from the 64th Stage

16
15
14

13

TRUTH TABLE
S

DO

01

L

X

H

X

12

Data Into
Flip-Flop 1

L
L
H

X

L

L

H

X

H

H

11

10

L
H

NOTE:
The Flatpack version has the same
pinouts (Connection Diagram) as the
Dual In-line Package.

L = Low Level
H = High Level
X = Don't Care

LOGIC DIAGRAM

0,

00
FFO

02
FF2

FFt

CP

cp0
VDD
VSS
NC

Co

0
7·65

Pin 16
Pin 8
Pins 3,4,5, 11, 12, 13, 14
Pin Number

•

FAIRCHILD CMOS • 40318
DC CHARACTERISTICS: VDD as shown, VSS = 0 V (See Note 1)
LIMITS
SYMBOL

PARAMETER
MIN
Quiescent
Power

IDD

Supply
Current

VDD = 10 V

VDD = 5 V
TYP

MAX

MIN

TYP

20
150
5
150

XC
XM

MIN

TYP

40
300
10
300

TEMP

UNITS

VDD-15V

MAX

TEST CONDITION S

MAX
80
600
20
600

MIN,25°C
MAX
MIN,25 C
MAX

/lA
/lA

All inputs at

o Vor VDD

AC CHARACTERISTICS AND SET-UP REOUI REMENTS: VDD as shown, VSS = 0 V, T A = 25°C (See Note 2)
LIMITS
SYMBOL

PARAMETER

VDD = 5 V
MIN

tpLH
tpHL
tPLH
tpHL
tTLH

-

Propagation Delay, CP to 063, 063
Propagation Delay, CP to CO
Output Transition Time

TYP

MAX

VDD=10V
MIN

TYP

MAX

VDD - 15V
MIN

TYP

UNITS

TEST CONDITIONS

MAX

120

60

40

ns

120

60

40

ns

45

25

20

ns

45

25

20

ns

65

35

15

ns

CL = 50 pF,

65

35

15

ns

RL = 200 kn

tTHL
twCP(L)

Minimum Clock Pulse Width

25

10

8

ns

Input Transition

ts

Set-Up Ti me, S to CP

75

40

30

ns

Times

th

Hold Time, S to CP

40

20

15

ns

ts

Set-Up Time Dn to CP

75

40

30

ns

th

Hold Time, Dn to CP

40

20

15

ns

fMAX

Max_ Clock Frequency (Note 3)

4

8

9

MHz

~

20 ns

NOTES:

1.

Additional DC Characteristics are listed in this section under 40008 Series CMOS Family Characteristics.

2.
3,

Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.
For fMAX, input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.

4.

It is recommended that input rise and fall times to the Clock Input be less than 15 p,s at VOO = 5 V, 4 j.J.s at VOO = 10 V, and 3 jJs at

VDD=15V.

SWITCHING WAVEFORMS

MINIMUM CLOCK PULSE WIDTH, SET-UP AND
HOLD TIMES, On TO CP AND S TO CP
NOTE: Set~up (ts) and Hold (th) Times are shown as positive values but may be specified as negative values.

7-66

40348
8-BIT UNIVERSAL BUS REGISTE

GENERAL DESCRIPTION - The 4034B is an B Bit Bi-directional Parallel/Serial Input/Output Bus
Register with a Serial Data Input (OS!. a Clock Input (CP), an active HIGH asynchronous or synchronous Paralleled Load/Parallel Enable Input (PL/PE!. two mode control inputs, Asynchronous/Synchronous (A/5) and Data Transfer (P/O), two sets of eight bi-directional Parallel Data Inputs/Outputs
(PO-P7 and 00-07), and an active HIGH Output Enable Input (EOp) controlling the PO-P7 Parallel
Data Inputs/Outputs.

LOGIC SYMBOL

"

The Data Transfer Mode Control Input (P/O) determines the direction of data flow_ When P/O is
HIGH PO-P 7 act as a parallel data inputs and 00-07 act as parallel data outputs. When P/O is LOW,
00-07 act as parallel data inputs and PO-P 7 act as parallel data outputs. A LOW on the Output Enable
Input (EO p ) forces the PO- P7 Input/Outputs to assume a high impedance "OFF" state, regardless of
other input conditions.

20

21

22

23

4

3

2

1

Pia
4034B

AiS

(A/S) Mode Control I nput allows either asynchronous or synchronous

13

pu'PE

PIa input. Asynchronous parallel data transfer at either

PO-P 7 or 00-07 o~rs when both the AsynchronousLSynchronous (A/5) and the Parallel Load/
Parallel Enable (PL/PE) Inputs are HIGH. With the AlS input LOW parallel or serial data may be

8

tran"sferred synchronously. Synchronous serial data transfer on the Serial Dat~ I nputs (OS) occurs on

The 40348 is useful in applications requiring bi-directional transfer of parallel data between two data
buses, conversion of serial data to parallel form and transfer of the parallel data to either of two data
buses, recirculation of parallel dqta, or acceptance of parallel data from either of two buses for conversion to serial form.

7

G

5

VDD ~ Pin 24

the LOW-to-HIGH transition at the Clock Input (CP) when both PL/PE and A/S inputs are LOW. With
A/'S LOW and PL/PE HIGH, synchronous parallel data transfer on either PO-P 7 or 00-07 occurs on
the LOW-to-H IGH transition at the Clock Input (OPl. The direction of data transfer is dependent upon
the state of the P/O input.

•
•
•
•
•
•

"

EOp

data transfer. With the A/5 input H IG H, parallel data may be transferred asynchronously, independent
of the Clock Input (CP), at the PO-P 7 or 00-07 Parallel Data Inputs/Outputs with the direction of
data transfer dependent upon the state of the

13

"s
11

15

An Asynchronous/Synchronous

17

VSS

~

Pin 12

CONNECTION DIAGRAMS
DIP (TOP VIEW)

BI-DIRECTIONAL DATA TRANSFER
ASYNCHRONOUS OR SYNCHRONOUS PARALLEL OPERATION
SYNCHRONOUS SERIAL OPERATION
3-STATE OUTPUT ENABLE
SERIAL-TO-PARALLEL OR PARALLEL-TO-SERIAL DATA TRANSFER
PARALLEL LOAD OR PARALLEL ENABLE

24
23
22

21

PIN NAMES

Os
PO-P7
°0-°7
PL/PE
CP
A/S
P/O
EOp

20

Serial Data Input
Parallel Data Inputs/Outputs
Parallel Data Inputs/Outputs
Parallel Load/Parallel Enable Input
Clock Input
Asynchronous/Synchronous Mode Control Input
Data Transfer Mode Control Input
Output Enable Input for Pn Parallel Data Inputs/Outputs

19
18

15

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual In-line Package.

7-67

FAIRCHILD CMOS • 4034B
BLOCK DIAGRAM

@@@@@@@@
PoP, P2P3P4P5PSP7

r II r 1111
Sa

EO

OCTAL 2-CHANNEL
MXIDEMX

III

,--

~
DS

PE

@

POP, P2 P3 P4 P5 PS P7

DS
8-BIT SHIFT REGISTER

Pia

~
~
~

MODE
CONTROL
LOGIC

CP

0001°203040506 °7

--<

--

EO,

III
Sa

OCTAL 2-CHANNEL
MX!DEMX

11111111

0001 °20304050607

®0®®0®GlCD
VDD '" Pin 24
VSS == Pin 12
o = Pin Number

MODE SELECTION TABLE

EO p
PL!PE
~~~~~

PIO
MODE
AIS
__~~~+-~~+-~~~~~~
____~____~__~~O~P~E~R~A~T~IO~N~______~__~ _________ __

L
H

X

Serial

Synchronous Serial data input, P and Q parallel data outputs disabled.

X

Seria1

Synchronous Serial data input, Q Parallel data output.

Parallel

Q

Synchronous Parallel data inputs, P Parallel data outputs disabled.

H

Parallel

Q

Asynchronous Parallel data inputs, P Parallel data outputs disabled.

H
H

recir~~

H

H

L

Parallel

P Parallel data inputs disabled, Q Parallel data outputs, synchronous data

H

H

H

Parallel

P Parallel data Inputs disabled, Q Parallel data outputs, asynchronous data recirculation.

X

Serial

Synchronous serial data input, P Parallel data output.

X

Serial

Synchronous serial data input, Q Parallel data output.

H

L

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

Parallel

Q

Synchronous Parallel data input, P Parallel data output.

Parallel

Q

Asynchronous Parallel data input, P Parallel data output.

Parallel

P Synchronous Parallel data input, Q Parallel data output.

Parallel

P Asynchronous Parallel data input, Q Parallel data output.

X - Don't Care, H - HIGH Level, L - LOW Level

Note:
Outputs change at positive transition of clock in the serial mode and when the A/S input is LOW in the parallel mode.
During transfer from parallel to serial operation, A/S should remain lOW in order to prevent Os transfer into flip-flops.

7-68

FAIRCHILD CMOS • 40348
DC CHARACTERISTICS: V DD as shown, VSS

~

0 V (Note 1)
LIMITS

SYMBOL

PARAMETER

MIN
Output OFF
IOZH

VDD~10V

V DD - 5 V
TYP

MAX MIN

TYP

VDD~15V

MAX

MIN

TYP

UNITS
1.6

XC

MAX

pA

0.4

XM

MIN,25°C

12
Output OFF
IOZL

Current LOW
Quiescent
Power

IDD

Supply

XC
XM

Current

~

VSS

MIN,25°C

-12

MAX

pA

-0.4

XM

Output Returned
to V DD , EOp

MAX

-1.6

XC

TEST CONDITIONS

MIN,25°C

12

Current HIGH

TEMP

MAX

MIN,25°C

-12

Output Returned
to V SS ' EO p ~ VSS

MAX

20

40

80

150

300

600

5

10

20

150

300

600

MIN, 25°C
MAX

pA

MIN,25°C

All inputs
atOVorV DD

MAX

AC CHARACTERISTICS AND SET·UP REQUIREMENTS: V DD as shown, VSS ~ OV, T A ~ 25°C (See Note 2)
A SYNCHRONOUS MODE ONLY
LIMITS
SYMBOL

PARAMETER

V DD
MIN

~

5V

TYP

MAX

V DD
MIN

~

10V

TYP

MAX

V DD
MIN

~

15V

TYP

UNITS

TEST CONDITIONS

MAX

tpLH

Propagation Delay, PL!PE to

300

160

120

n.

tpHL

Qn or Pn

300

160

120

ns

tpLH

Propagation Delay, A/S"" to

285

150

115

ns

CL

tpHI
twA/S(H)

Pn or Qn

285

150

115

ns

RL~200D.

A/S Minimum Pulse Width (HIGH)

150

75

55

ns

Input Transition

twPL/I'l:(H) PL/PE Minimum Pulse Width(H IGH)

150

75

55

ns

Times~20 ns

150

75

55

ns

35

15

12

ns

-10

-5

-2

ns

twP/Q

P/Q Minimum Pulse Width

ts

Set·Up Time, Pn or Qn to PL/Pt:

th

Hold-Time, Pn or Qn to PL!!'E

~50pF,

•

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: V DD as shown, VSS = 0 V, T A = 25°C (See Note 2)
SYNCHRONOUS MODE ONLY
LIMITS
SYMBOL

PARAMETER

V DD = 5 V
MIN

TYP MAX

V DD =10V
MIN

TYP MAX

V DO =15V
MIN

UNITS

TEST CONDITIONS

TYP ~AX

tpLH

Propagation Delay, CP to

300

155

120

ns

tpHL
tw CP

~orPn

300

155

120

ns

CP Minimum Pulse Width

100

50

40

ns

ts

Set-Up Time, PL/PE to CP

35

15

12

ns

th

Hold Time, PL/PE to CP

-10

-5

-2

ns

RL = 200 kn

ts

Set-Up Time, DSIO CP

35

15

12

ns

Input Transition
Times ';;;20 ns

th

Hold Time, DS to CP

ts

Set-Up Time, A/S to CP

th

Hold Time, A/S to CP

ts

Set-Up Time, P/Q to CP

th
f MAX

Hold Time, P/O to CP
Input Count Frequency

-10

-5

-2

ns

35

15

12

ns

-10

-5

-2

ns

35

15

12

ns

-10

-5

-2

ns

4

8

9

MHz

(Note 3)
Notes are on the following page,

7-69

C L =50pF,.

FAIRCHILD CMOS • 4034B
AC CHARACTERISTICS AND SET-UP REQUIREMENTS: V DD as shown, VSS = OV, T A = 25°C (See Note 2) ALL MODES OF OPERATION
l.IMITS
SYMBOL

PARAMETER

V DD = 5V
MIN

V DD = 10V

TYP MAX MIN

TYP

V DD = 15V

MAX

MIN

TYP

UNITS

TEST CONDITIONS

MAX

tpLH

Propagation Delay, P/Q to

300

160

120

ns

tpHL

Qn or Pn

300

160

120

ns

tpZH

Output Enable Time

60

37

25

ns

tpZL

(Note 5)

60

37

25

ns

C L =50pF,

tpHZ

Output Disable Time

60

37

25

ns

tPLZ

(Note 5)

60

37

25

ns

RL =200 k.r!
Input Transition

tTLH

Output Transition Time

85

45

30

ns

Times <20 ns

85

45

30

ns

150

75

55

ns

tTHL
twEOp(H) EO p Minimum Pulse Width
(HIGH)

Notes:
1. Additional de characteristics are listed in this section under 40008 Series CMOS Famity Characteristics.
2. Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.
3, For f MAX ' input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.

4. It is recommended that input rise and fall times to the Clock I nput be less than 15 p.s at V DD "" 5 V, 4 /J.s at V DO = 10 V, and 3 J.Ls at
VOO

=

15 V.

5, For tpZH and t pHZ ' RL

=::

1 Ul to VSS' For tpZL and tPLZ, RL == 1 kf2 to V DD .

AC WAVEFORMS
ASYNCHRONOUS MODE ONLY
tw

A/S

____-J~~50-%---------------------------~~
tw

PIO

Pn or On

A/S (HI

P/O

~"5-0%-----ST-A-B-L-E----50-%~
50%

50%
PL/PE

Minimum Pulse Widths for Ai'S,
P/O and PL/PE and Set-Up and
Hold Times Pn or On to PL/PE

7-70

50%

STABLE

50%

FAIRCHILD CMOS • 40348
AC WAVEFORMS (Cont'd)
SYNCHRONOUS MODE ONLY

A/S

\:_%_______
tt,

PL/PE

CP

SET-UP AND HOLD-TIMES A/STO CP, PL/PE TO CP
AND Os TO CP AND MINIMUM CLOCK PULSE WIDTH

ALL MODES OF OPERATION

i-----tw EOp ( H ) - - - - i
EO,
50%

10%

'0---'
OUTPUT ENABLE TIME
(tPZH) AND OUTPUT DISABLE TIME (tPHZ)

,-

, .... -

'-----------------~I

OUTPUT ENABLE TIME (tPZLl. OUTPUT DISABLE TIME ItPLZ)
AND MINIMUM EOp PULSE WIDTH

NOTE:
Set-up and Hold Times are shown as positive value;;; but may be specified as negative values.

7-71

FAIRCHILD CMOS • 4034B

TYPICAL APPLICATIONS
PARALLEL ,ATA INPUTS

PL/iSE
SERIAL DATA
INPUT

PL{PE
SERIAL DATA

0,

Vooo-+---1 Pia

40348

0,

Pia

Voo

AI,

A/S-

CP

CP
SERIAL DATA
OUTPUT

... PlfPE OUTPUT

PLiPE INPUT -..>-f-t----_t-------~I_1_t-----t_---AI~ INPUT

AIS OUTPUT

CLOCK INPUT

CLOCK OUTPUT

PARALLEL DATA OUTPUTS

SHIFT
LEFT

PARALLEL 0fTA OUTPUT

OUTPUT
OUTPUT

ENABLE
INPUT

SHIFT LEfT!
SHIFT RIGHT
INPUT

1/~_~OO1B

0 UTPUT ENABLE

~

P

I

s HIFT RIGHT

I

·1

OUTPUT

-~
~

~

-

SHIFT
RIGHT

INPUT

Po p, P2 P3 P4 Ps P6 P7
L- 'Oc
PL/PE

0,

REGISTER 1

Pia

4034B

~ Aft!.

CLOCK
INPUT

Po p, p;! PJ P4 P5 P6 P7

'Oc

'--

PLJPE

l.....-- 0;,

~

REGISTER 2

Pia

4034B

At<
CP

CP
00 Q, Q2 Q3 Q4 Q5 Q6 07

00 Q, 02 03 Q4 Q5 06 Q7

-

f--

~

Ais

SHIFT LEFT INPUT

AlS

INPUT

CLOCK

L
Voo

Po p, p, Po p, P, P, p,
.Oc

~

Voo

PLfI>E

0,

4034B

AIS

CP
OQ Q, Q2 03 Q4

I

as

06 Q7

t t

PL/PE

lq

REGISTER 3

Pia

0 UTPUT ENABLE

L

Po p, P2 P3 P4 P5 P6 P7
'Oe

I

0,

PIO

REGISTER 4
40348

AI"
CP
00 Q, Q, Q3 Q4 05 OJ;

I

a

I

I

PARAL.LEL DATA INPUT

FIG.2

SHIFT RIGHT/SHIFT lEFT WITH PARAllEL INPUTS

NOTE:
A "HIGH" l"lOW") on the Shift left/Shift Right Input allows serial data on the Shift left Input IShift Right Input) to enter the register on
the positive transition of the clock signal. A "HIGH" on the Output Enable Input disables the "P" Parallel Data lines on registers 1 and 2 and
enables the "P" data lines on registers 3 and 4 and allows parallel data into registers 1 and 2. Other logic schemes may be used in place of
registers 3 and 4 for parallel loading.
When parallel inputs are not used registers 3 and 4 and associated logic are not required.
The shift left input must be disabled during parallel entry.

7-72

40358
4-81T UNIVERSAL SHIFT REGISTER
DESCRIPTION - The 4035B is a fully synchronous edge-triggered 4-Bit Shift Register with a Clock
Input (CP), four synchronous Paraliel Data Inputs (PO-P3), two synchronous Serial Data Inputs (J, K),
a synchronous Parallel Enable Input (PEL Buffered Parallel Outputs from all 4-bit positions (QO-Q31.
a True/Complement Input (TiC) and an overriding asynchronous Master Reset Input (MR).

LOGIC SYMBOL

Operation is synchronous (except for Master Reset) and is edge-triggered on the LOW-to-HIGH
transition of the Clock Input (CP). When the Parallel Enable Input (PE) is HIGH, data is loaded into
the register from p'arallel Inputs (P0-P3) on the LOW-to-HIGH transition of the Clock Input (CP).
When the Parallel Enable Input (PE) is LOW, data is shifted into the first register position from the
Serial Data Inputs (J, K) and all the data in the register is shifted one position to the right on the
LOW-to-HIGH transition of the Clock Input (CP). D-type entry is obtained by tying the two Serial
Data Inputs (J, K) together.

4035B

1151413

The_Outputs (QO-Q.;)) are either inverting or non-inverting, depending on the True/Complement Input
(TLC). With the TIC Input HIGH, the Outputs (QO-Q3) are non-iJ1verting (Active HIGH). With the
TIC Input LOW, the Outputs (QO-Q3) are inverting (Active LOW).

Voo = Pin 16

A HIGH on the Master Reset Input (MR) resets all four bit positions (QO-Q3 = LOW if TIC = HIGH,
LOW) independent of all other input conditions.

CONNECTION DIAGRAM
DIP (TOP VIEW)

VSS = Pin 8

00-Q3 = HIGH if TIC =
•

•

•
•
•
•

TYPICAL SHIFT FREQUENCY OF 17 MHz AT VDD = 10 V
J, K INPUTS TO THE FIRST STAGE

TIC INPUT FOR TRUE OR COMPLEMENTARY OUTPUTS
SYNCHRONOUS PARALLEL ENABLE
CLOCK EDGE-TRIGGERED ON LOW-TO-HIGH TRANSITION
ASYNCHRONOUS MASTER RESET

PIN NAMES
PE
PO-P3

J

K
CP

TIC
MR
QO-Q3

Parallel Enable Input
Parallel Data Inputs
First Stage J Input (Active HIGH)
First Stage K Input (Active LOW)
Clock Input (L .... H Edge-Triggered)
TruelComplement Input
Master Reset Input
Buffered Parallel Outputs

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual In-line Package.

LOGIC DIAGRAM

"-1~>--+-1--~-------1---+-~~-----+---+--~------+--~-~

®

J

Q,

--1-1-'

8)

MR®
TICCD~~~-----------t1------------~----------~+--------------'
VOO = Pin 16

o

VSS

= Pin 8

lJ

lJ

0,

0,

'(@

= Pin Number

7-73

'(@

lJ

'(@

•

FAIRCHILD CMOS • 4035B
DC CHARACTERISTICS: VDD as shown, VSS ~ 0 V ISee Note 1)
LIMITS
SYMBOL

PARAMETER

VDD
MIN

Quiescent

Power
IDD

Supply

Current

~

TYP

VDD~10V

5 V
MAX

XC
XM

MIN

TYP

VDD~15V

MAX

MIN

TYP

TEMP

UNITS

TEST CONDITIONS

MAX

20

40

80

150

300

600

5

10

20

150

300

600

MIN,25°C

MA
MA

MAX

All inputs at

MIN, 25°C

OVorVDD

MAX

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VDO as shown, VSS ~ 0 V, T A ~ 25°C ISee Note 2)
LIMITS
PARAMETER

SYMBOL

VOD
MIN

tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tTLH

Propagation Delay, CP to Q n
Propagation Delay, MR to Q n
Propagation Delay, TIC to Q n
Output Transition Time

~

5 V

TYP

MAX

VDD~10V

MIN

TYP

MAX

VDD~15V

MIN

UNITS

TYP

MAX

200

400

90

180

60

140

200

400

90

180

60

140

250

500

120

230

75

180

250

500

120

230

75

180

125

250

55

120

40

95

125

250

55

120

40

95

85

135

45

75

30

45

85

135

45

75

30

45

TEST CONDITIONS

ns

ns
ns
ns

CL

~

50 pF,

twCP

CP Minimum Pulse Width

125

50

55

20

44

14

ns

RL

~

200 krl

twMR

MR Minimum Pulse Width

150

60

70

25

56

20

ns

Input Transition

120

60

54

30

43

22

ns

Times.;;; 20 ns

250

100

110

46

88

32

10

-90

5

-32

0

-22

250

100

110

46

88

32

10

-90

5

-32

0

-22

130

125

48

100

30

25 -100

10

-37

5

-23

8

8

17

10

20

tTHL

tree

MR Recovery Time

ts

Set~Up

th

Hold Time, Pn to CP

ts

Set-Up Time, PE to CP

th

Hold Time, PE to CP

ts

Set-Up Time, J, K to CP

th

Hold Time, J, K to CP

Time, P n to CP

Maximum Input Clock Frequency

fMAX

INote 3)

275

4

ns
ns
ns
MHz

NOTES:

1.
2.
3,

4.

Additional DC Characteristics are listed in this section under 40008 Series CMOS Family Characteristics.
Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.
For fMAX, input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.

It is recommended that input rise and fall times to the Clock Input be less than 15 /Js at VDO = 5 V, 4IJs at VOO::=: 10 V, and 3 /Js at
VDD~15V.

7-74

FAIRCHILD CMOS • 4035B
SWITCHING WAVEFORMS

....--twCP---.

J

OR

K

~
50%

MINIMUM CP PULSE WIDTH AND SET-UP
AND HOLD TIMES, PE TO CP, Pn TO CP, AND J OR K TO CP

CP

.
n
lwMR_

MR

50%

t" ' -

50%

----------~

~-------------

MR RECOVERY TIME AND MINIMUM MR PULSE WIDTH

NOTE: Set-up, and Hold Times are shown as positive values but may be specified as negative values.

7-75

40408
12-STAGE BINARY COUNTER

DESCRIPTION - The 4040B'is a 12-Stage Binary Ripple Counter with a Clock Input (CP), an
overriding asynchronous Master Reset Input (MR) and twelve fully buffe~d Outputs (QO-Ql1 L The
counter advances on the HIGH-to-LOW transition of the Clock Input (CPL A HIGH on the Master
Reset Input (MR)...£lears all counter stages and forces all Outputs (QO - Q11) LOW, independent of
the Clock Input (CPL

LOGIC SYMBOL

4040B

9

25 MHz TYPICAL COUNT FREOUENCY AT VDD = 10 V
CLOCK IS H-+L TRIGGERED
COMMON ASYNCHRONOUS MASTER RESET
FULLY BUFFERED OUTPUTS FROM ALL 12 STAGES

•
•
•
•

7653

24131214151

VOD

=

Pin 16

VSS

=

Pin 8

CONNECTION DIAGRAM
DIP (TOP VIEW)

PIN NAMES

CP

Clock Input (H-+L Triggered)
Master Reset Input (Active HIGH)
Parallel Outputs

MR
00- 0 11

NOTE:
The F latpak version has the same
pinouts (Connection Diagram) as the
Dual I n-line Package.

LOGIC DIAGRAM

VDO

=

VSS

= Pin 8

o

Pin 16

= Pin

Numbers

7-76

FAIRCHILD CMOS • 40406
DC CHARACTERISTICS: VDD as shown, VSS = 0 V (See Note 1)
LIMITS
SYMBOL

PARAMETER

VDD - 5 V
MI'N

Quiescent
Power

IDD

Supply
Current

TYP

MAX

MIN

TYP

MAX

20
150
5
150

XC
XM

UNITS

VDD = 15 V

VDD-l0V

MIN

TYP

40
300
10
300

TEMP

TEST CONDITION S

MAX
80
600
20
600

MIN,25°C
MAX
MIN,25°C

!J.A
!J.A

M~X

All inputs at
or VDD

oV

AC CHARACTERISTICS AND SET·UP REQUIREMENTS: VDD as shown, VSS = 0 V, TA = 25°C
LIMITS
SYMBOL

PARAMETER

VDD = 5 V
MIN

tpLH

Propagation Delay,

tpHL
tPHL
tTLH

CP to GO

Propagation Delay, MR to Gn

Output Transition Time

tTHL
twCP(H)

Minimum Clock Pulse Width

100

twMR(H)

Minimum MR Pulse Width

tree

Recovery Time for MR

fMAX

Input Clock Frequency (Note 2)

TYP

MAX

VDD=10V
MIN

TYP

MAX

UNITS

VDD = 15V
MIN

TYP

130

260

55

110

37

88

ns

110

220

45

90

33

72

ns

180

360

75

150

50

120

ns

65

135

35

70

25

45

ns

65

135

35

70

25

45

ns

50

40

20

140

70

55

85

43

35

5

10

12

TEST CONDITIONS

MAX

32

16

ns

27

44

20

ns

17

28

12

ns

25

14

30

MHz

CL = 50 pF,
RL = 200 kn
I nput Transition

Times'; 20 ns

NOTES:
1. Additional DC Characteristics are listed in this section under 40006 Series CMOS Family Characteristics.
2. For fMAX, input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.
3. It is recommended that input rise and fall times to the Clock Input be less than 15 J-LS at VOD = 5 V. 4,us at VOO = 10 V, and 3 /Js at

VOO=15V.

7-77

FAIRCHILD CMOS • 40408
TYPICAL ELECTRICAL CHARACTERISTICS
CLOCK FREQUENCY
VERSUS
POWER SUPPLY VOLTAGE

POWER DISSIPATION
VERSUS CLOCK FREQUENCY

3:

E1000~~-r~~~MT~-rMr'-~~

~
~

ffi

35

T~I~12~od

I
100
10

III

N

I

:t:

/v,
~v.

VDD-15V

15

ffi

I

;;::f.-;

20

::>
0
w

15

><:

10

a:
u.

~~'I't-~I--+t-/++-+-+ttH--+-tI:l±-l111::-++1++-1
III

102

CJ

~04

105

CLOCK FREQUENCY -

~

I

>-

:3

106

CJ

z
o

-

1601--r--1--r--~,

~
o

1401-+-·--1-

is

1001-~-r~~r-J.

120 1--r~T--+ Y'F---r-I--r---l

;::

80~9--r~~~-t--+--1-+--r~

~

60~9-+7+~--~

-

1.0 f-tV..,:D;.;:D:....,..."...,1...,.0"t1V--Oj;"'"H~,f/~~/"I~-j-+++--1

1 0-3

~
~

:1!

~10-1~~~~~?~~~~~~m-~~
~
k;~ ~;:;~
~

~

TA
CL

30

20~~--+-~--4---f--+--+--1

I~
40
TA - AMBIENT TEMPERATURE - °C

CL - LOAD CAPACITANCE - pF

SWITCHING WAVEFORMS

MR

CP

tTLH~1
PROPAGATION DELAY MASTER
RESET TO OUTPUT. MINIMUM MASTER RESET
PULSE WIDTH AND RECOVERY TIME FOR MASTER RESET

1--

'THL

PROPAGATION DELAY CLOCK TO
OUTPUT QO. OUTPUT TRANSITION
TIMES AND MINIMUM CLOCK PULSE WIDTH

7-78

40418
QUAD TRUE/ COM PLEM ENT BU FFE

GENERAL DESCRIPTION - The 4041 B is'a Quad True/Complement Buffer which provides both an
inverted active LOW Output (Z) and a non-inverted active HIGH Output (Z) for each Input III.
CONNECTION DIAGRAM
DIP (TOP VIEW)
LOGIC DIAGRAM

14

12
11

10

Voo

= Pin

14

vss = Pin 7
0= Pin Number

PIN NAMES
la. lb. Ic. Id
Za. Zb. Zc. Zd
Za. Zb. Zc. Zd

NOTE:

Buffer Input
Buffered True Output
Buffered Complementary Output

DC CHARACTERISTICS: VDO as shown. VSS

=0

The flatpak version has the same
pinouts (Connection Diagram) as the
Dual I n-L ine Package.

V (See Note 1)
LIMITS

SYMBOL

PARAMETER

IOH

Output HIGH
Current

IOL

Output LOW
Current

VOO=5V
MIN TYP MAX

VOO= 10V
MIN TYP MAX

VOO = 15 V
UNITS
MIN TYP MAX

-2.7
-2.25
-1.6

-5.4
-4.5
-3.2

-15.5
-13
-8.7

2.7

6.25
5
3.5

18
15
10

2.25
1.6

rnA

mA

TEMP

TEST CONOITIONS

MIN
25°C
MAX

VOUT = 4.6 V for VOO = 5 V
VOUT = 9.5 V for VOO" 10 V
VOUT = 13.5 V for VOO" 15V
Inputs at VOO or VSS per
Logic Function

MIN
25°C
MAX

VOUT = 0.4 V
VOUT" 0.5 V
VOUT = 1.5 V
Inputs at VOO
Logic Function

Quiescent
100

Power
Supply
Current

XC
XM

4
30
1
30

8
60
2
60

7-79

16
120
4
120

p.A
p.A

MIN 25°C
MAX
All inputs
MIN 25 C at 0 V or VOO
MAX

for VOO" 5 V
for VOO" 10 V
for VOO " 15 V
or VSS per

FAIRCHILD CMOS. 40418
AC CHARACT!,RISTICS: Voo as shown, VSS:' 0 V, TA ~ 25°C (See Note 2)
LIMITS
SYMBOL

VOO ~ 5V

PARAMETER

MIN

TYP MAX

Propagation Delay

tpLH
tpHL

Output Transition Time

tTLH

VOD~

tTHL

MIN

10V

TYP MAX

V DD
MIN

~

15V

TEST CONDITIONS

UNITS

TYP

MAX
~

60

125

25

60

20

48

ns

CL

60

125

25

60

20

48

ns

RL ~200kn

50 pF,

30

75

15

40

12

30

ns

Input Transition

30

75

15

40

12

30

ns

Times ";;20 ns

NOTES:

1. Additional de characteristics are listed in this section under 40008 Series CMOS Family Characteristics.
2. Propagation delays and output transition times are graphically described in this section under 4000 B Series CMOS Family Characteristics.

TYPICAL ELECTRICAL CHARACTERISTICS

POWER DISSIPATION
VERSUS FREQUENCY

INPUT FREQUENCY - Hz

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

PROPAGATION DELAY
VERSUS TEMPERATURE

80~-4---t--1---t--4---t--1---1

70r-~--r-~~r-4-~~9~--~

>

60~~~-4---+---t~~~~-+---t--4

c

50r--1---+~~--~--+---+---r--1

~

Ii
~

,/'

/'"

40r--1~-+---+--~--+---+---r--1

I

tpLH. tptL. '1'0

-l5V

'O~1--+--+--t--~4--+--+--t-4
'O~-+--~--+---~-+--~--+--4
o~~~--~-L

20

40

60

80

100

120

140

-60 -40 -20

160

CL - LOAD CAPACITANCE - pF

20

__~~~__~-L~
40

60

80

TA - AMBIENT TEMPERATURE -

7-80

100 120 140

°c

40428
QUAD D LATCH

DESCRIPTION - The 4042B'is a 4-Bit Latch with four Data Inputs (00-03), four buffered Latch
Outputs (00-°3), four buffered Complementary Latch Outputs (00-03) and two Common Enable
Inputs (EO and E1l. Information on the Data Inputs (00-03) is transferred to the Outputs (00-03)
while both Enable Inputs (EO, E1) are in the same state, either HIGH or LOW, The Outputs (00-03)
follow the Data Inputs (00-03) as long as both Enable Inputs (EO, E1) remain in the same state. When
the two Enable Inputs (EO, E1) are different, the Data Inputs (00-03) do not affect the Outputs
(00-03) and the information in the latch is stored. The 60-03 Outputs are always the complement
of the 00-03 Outputs. The Exclusive-OR input structure allows the choice of either polarity for the
Enable Input, With one Enable Input HIGH, the other Enable Input is active HIGH; with one Enable
Input LOW, the other Enable Input is active LOW.

LOGIC SYMBOL

The last moment prior to the trailing end of the enable condition that the Latch Outputs can still be
affected by the inputs is specified as a set-up time. A negative set-up time, as typically exhibited by
this device, means that the latches respond to input changes after the end of the enable condition.
Following established industry practice, a hold time is specified, defining the time after the end of the
enable condition, that the inputs must be held stable, so that they do not affect the state of the
latches. It follows from this definition, that the hold time is identical with the negative set-up time.
Set-up and hold times have a tolerance, due to manufacturing process variations, temperature and
supply voltage changes. For predictable operation the data input levels must be held stable over the
full spread of this timing window starting with the earliest set-up time (largest positive or smallest
negative value) to the latest hold time.

2

ACTIVE HIGH OR ACTIVE LOW ENABLE
TRUE AND COMPLEMENTARY OUTPUTS (Q & Q)

PIN NAMES
00-0 3
EO,E1
00-03
00-0 3

Data Inputs
Enable Inputs
Parallel Latch Outputs
Complementary Parallel Latch Outputs

7

13 14

10

9

11

12

1

15

VOD = Pin 16.
VSS "'" Pin 8

TRUTH TABLE
•
•

3

4

LATCH CONDITION

EO
L
L

E1
L
H

H
H

L

Not Enabled

H

Enabled

Enabled
Not Enabled
CONNECTION DIAGRAM
DIP (TOP VIEW)

L = LOW Level

H=HIGHLevel

LOGIC DIAGRAM
16
15
14

13
12
11
10

NOTE:
The F latpak version has the same
pinouts (Connection Diagram) as the
Dual In·line Package.

"" Pin 8
= Pin Numbers

7-81

•

FAIRCHILD CMOS • 40428
DC CHARACTERISTICS: VOO as shown, VSS = 0 V (See Note 1)
LIMITS
SYMBOL

VOO = 5·V

PARAMETER
MIN

100

Quiescent
Power
Supply
Current

TYP

XC
XM

MAX

VOO-10V
MIN TYP MAX

VOO=15V
MIN TYP MAX

20
150
5
150

40
300
10
300

80
600
20
600

TEMP

TEST CONDITIONS

MIN,25°C
MAX
MIN,25 C
MAX

All inputs at
OVorVoo

UNITS

I'A
I'A

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VOO as showQ, VSS = 0 V, T A = 25°C
LIMITS
SYMBOL

PARAME;TER

VOO =5 V
MIN

VOO = 10 V

TYP

MAX

101
99

MIN

UNITS

VOO = 15V

TYP

MAX

MIN

TYP

200

45

90

33

72

200

44

88

33

70

ns

tpLH

Propagation Delay,

tpHL

Data to Output

tPLH

Propagation Delay,

156

310

66

132

47

106

ns

tpHL

Enable to Output

137

275

65

135

58
31

116
70

41
25

93
45

ns
ns

60

135

26

70

20

45

ns

tTLH

Output Transition Time

tTHL
Set-UpTime, On to EO or E1

10

-12

10

-6

th

Hold Time, On to EO or El

50

25

25

13

twEn

Minimum. Enable Pulse Width

80

40

32

16

ts

ns

20

7

ns

26

12

ns

NOTES:
1. Additional DC Characteristics are listed in this section under 40008 Series CMOS FamilY Characteristics.

7-82

ns

-4

8

TEST CONDITIONS

MAX

CL = 50 pF,
RL = 200 k.n
Input Transition

Times .. 20 ns

FAIRCHILD CMOS· 40428
TYPICAL ELECTRICAL CHARACTERISTICS

TYPICAL POWER DISSIPATION
VERSUS FREQUENCY

~

E 1000

w

TAl

~ 100

~

10

'~"

1.0

II'v~o'1'j5Iv

C
~ 10- 3

"

140

I-w

VOO= 5 V

IIII I

120

b
BO

~

60

"

40

40

5

20

~
C

-4 ' L

I

I

I

I

I

:3~140

O...J 120

160

~

140

C I-

......

C3 ~

o

10
15
VOD - POWER SUPPLY VOLTAGE - V

tPHL. ENABLE TO OUTPUT

tPLH. tpHL. DATA TO OUTPUT

60

!f~

40

5

20

I I I

o
I-

o

~

PROPAGATION DELAY
VERSUS TEMPERATURE

I
I

fl L

tpLH. ENABLE TO OUTPUT

I~

tpHL. ENABLE TO OUTPUT

t- tPLH.
o

>I~

V

tPHL. DATA TO OUTPUT

I

w w

~

~

I

1001W1W1~

Cl - LOAD CAPACITANCE -

pF

~

200
,3 160

~.!
~'--'iOO

ft;LH. ENABLE TO OUTPUT

o

200

I-

;e

1"-...

Z

o
I-

-#:'1

V
f..- .-

TA

I-

f-t--t-+-+-----t-,,---t--t-+-1
~ ~ 120 f-t--t-+

\
\

:!!
::J
:!! 20

o

If ~

;

.~

W

!l
::J

60

~
~

1\

100

80

~~

107

TA 25°C
Cl" 15 pF

I
:I:

:i

Qz 100

...-" I[

PROPAGATION DELAY

~180

L<,,;!J-::

:"i~140

~~ 120

•

I 200VERSUS LOAD CAPACITANCE

I-

I I I

CL - 15 pF

>=5 160

~~

103
104
106
106
INPUT FREQUENCY - Hz

PROPAGATION DELAY
VERSUS TEMPERATURE

Ww

MINIMUM ENABLE PULSE
WIDTH VERSUS
POWER SUPPLY VOLTAGE

~

~

V

itI- 180

5 of
L
CL=60pF - - -

102

.

f'-

~

~ 10-4

iii

.V

It

~ 10-2

~

VOO - 10 V

g 10-1

I-

~

II 2i'f1 I

Z

1200

ENABLE TO OUTPUT

~O~TPUi

'PLH. VOO"
tPHL.'VOD

10n-

=10V=1

tPLH. VDO ='15",

/

tPLH. tPHL.
VOO 10V

-

,

-- -

f-- I -

--r--t: t~L. VOO =15 V I--

20

0

-~C -

--

L tpLH. tpHL. VOO = 15 V

OW W ~ ~1001W1W1~
CL - LOAD CAPACITANCE - pF

SWITCHING WAVEFORMS

\----r ...

EO-~'

OR

E,

50%

1 .....

...1

.tpLH"

50%

1'----_tpHL

Q

SET-UP AND HOLD TIMES,
MINIMUM ENABLE PULSE WIDTH
NOTE:
Either EO or E1 is held HIGH or LOW
while the other Enable Input is pulsed as
per the Truth Table. ts and th are shown
as positive values but may be specified
as negative values.

PROPAGATION DELAY DATA
TO OUTPUT AND TRANSITION
TIMES, WITH LATCH ENABLED

PROPAGATION DELAY ENABLE TO OUTPUT
NOTE:
Either EO or E1 is held HIGH or LOW
while the other Enable I nput is pulsed as
per the Truth Table.

7-83

•

40438
QUAD RjS LATCH WITH 3-STATE

au

DESCRIPTION - The '4043B. is a Quad RIS Latch with 3-State Outputs with a common Output
Enable (EO), Each latch has an active HIGH Set Input (Sn), an active HIGH Reset Input (Rn) and an
active HIGH 3-State Output (Gn).

LOGIC SYMBOL

When the Output Enable Input (EO) is HIGH, the state of the Latch Outputs IQn) can be determined
from the Truth Table Isee below). When the Output Enable Input (EO) is LOW, the Latch Outputs are
in the high impedance OFF state. The Output Enable Input (EO) does not affect the state of the latch.
4

•
•
•
•

3

3-STATE BUFFERED OUTPUTS (ACTIVE HIGH)
COMMON OUTPUT ENABLE
SET INPUTS TO EACH LATCH (ACTIVE HIGH)
RESET INPUTS TO EACH LATCH (ACTIVE HIGH)

6

7

12

11

14

15

40438

PIN NAMES
EO

Common Output Enable Input
Set Inputs

SO-S3
RO-R3
QO-Q3

9

10

1

Reset Inputs
3-State Buffered Latch Outputs
TRUTH TABLE
INPUTS
EO

VDD
VSS

Pin 16

NC

Pin 13

Pin

8

OUTPUT
Rn
X

Qn
High Impedance

L

Sn
X

H

H

L

H

H

L

H

L

H

H

H

H

H

L

L

No Change

CONNECTION DIAGRAM
DIP ITOP VIEW)

H = HIGH Level
L = LOW Level
X = Don't Care

LOGIC DIAGRAM

16

15
14

13
12
11

10

LATCH

VDD=
VSS =
NC =
=

o

Pin
Pin
Pin
Pin

16
8
13
Number

LATCH

LATCH

LATCH

Qo

NOTE:
The Flatpack version has the same
pinouts (Connection Diagram) as the
Dual I n-line Package.

7-84

FAIRCHILD CMOS • 40438
DC CHARACTERISTICS: VDD as shown, VSS = 0 V (See Note 1)

LIMITS
SYMBOL

PARAMETER

Output OFF
IOZH

Current HIGH

Output OFF
IOZL

Current LOW

Quiescent
Power

IDD

Supply
Current

VDD =5 V
MIN TYP MAX

VDD-l0V
MIN

TYP

MAX

VDO-15V
TYP MAX
1,6

XC

12
0.4

XM

TEST CONDITIONS

MIN,25°C
MAX

p.A

MIN,25°C

-12
-0.4
40

80

150

300

600

5
150

10

20

300

600

to VDD, EO = VSS

MIN,25°C
p.A

MAX

Output Returned

MIN,25°C

to VSS EO = VSS

-12
20

Output Returned

MAX

-1.6

XM

XM

TEMP

12

XC

XC

UNITS

MIN

MAX
MrN,25°C
p.A

MAX

All inputs at

MIN, 25°C

OVor VDD

MAX

AC CHARACTERISTICS: VDD as shown, VSS - 0 V, TA - 25°C (See Note 2)
LIMITS
SYMBOL

PARAMETER

VDD -5 V
MIN TYP MAX

VDD -10 V
MIN TYP MAX

UNITS

VDD -15V
MIN

TYP

TEST CONDITIONS

MAX
CL - 50 pF,

tPLH

Propagation Delay, Sn to Q n

80

30

145

70

24

56

ns

RL -200 kn
I nput Transition

Times .. 20 ns
tpHL
tpZH

Propagation Delay, Rn to Q n
Output Enable Time

tpZL

75

135

25

60

20

48

ns

30

55

20

40

15

32

ns

(RL - 1 kn to VSS)

40

75

20

40

15

32

ns

IRL

20

20

40

18

32

ns

IRL - 1 kn to VSS)

20

40

15

32

ns

IRL - 1 kn to VDD)

30
30

75

20

45

ns

20

45

ns

tpLZ

30

45
55

tTLH

60

135

60'

135

tpHZ

Output Disable Time

Output Transition Time

tTHL
twSn

Minimum Sn Pulse Width

60

32

twR n

Minimum Rn Pulse Width

60

32

30
30

75

13

24

15

ns

13

24

15

ns

= 1 kn to

VDD)

NOTES:
1. Additional DC Characteristics are listed in this section under 40008 Series CMOS Family Characteristics.
2. Propagation Delays and Output Transition Times are graphically described in this section under 40008 S"eries CMOS Family Characteristics.

7-85

FAIRCHILD CMOS • 40438
SWITCHING WAVEFORMS

EO
EO

On ---~90%--,J

, ....

........

_--

,,"

",-- ....
"OFH~'~~T~TE

,

OUTPUT ENABLE TIME
(tPZL) AND OUTPUT DISABLE TIME ItPLZ)

OUTPUT ENABLE TIME
(tPZH) AND OUTPUT DISABLE TIME (tPHZ)

50%
Sn

Rn-----------'

\--MINIMUM RN AND SN PULSE WIDTHS
AND RECOVERY TIMES FOR RN AND SN

7-86

FAIRCHILD CMOS. 40438
TYPICAL elECTRICAL CHARACTERISTICS

POWER DISSIPATION VERSUS
INPUT FREQUENCY
1000

T~' 25 C

11l)7
.'~~

v,QQ

~~

1

k

~

~V

~

~

~f~~ ~

~::~.""

~~~

~P'

Vt--

Cl -150Fel = 50pf10'

10'

-

106

INPUT FREOUENCY - Hz

PROPAGATION DELAY. Rn OR
Sn TO Qn. VERSUS
LOAD CAPACITANCE

PROPAGATION DELAY. Rn OR
Sn TOQn. VERSUS
TEMPERATURE

~ 1~r-T-A~'~2'~OC~~~~T-~~~--~~

a
~

! 100
CL "'5pF

I

a 90

120~-4---+--~--+---~-t~~~

~80

Jf

II:

£ 100~-4~-+--~--+-~~-t--~--4
II:

~

70

~

60

"

~

.~

w~\.'

I

20

:l:

t

40

CL - LOAD CAPACITANCE - pF

0

I--""

V

50

40

.... 10

L

~t""

i:
i

"QIl~1""'""

tp"'\..."OO'" '\0\1

~,sv
tPLH. tPH\.· "00

I;'

-60

-40 -20

0

20

40

60

80

...,..

.....
100 120

1".. - AMBIENT TEMPERATURE - C

7-87

140

40448
QUAD RjS LATCH WITH 3-STATE OUTPUTS

DESCRIPTION - The 4044B is a Quad RIS Latch with 3-state Outputs with a common Output
Enable Input (EO)_ Each latch has an active LOW Set Input (s,:;), an active LOW Reset Input (An) and
an active HIGH 3-State Output (Qn).

LOGIC SYMBOL

When the Output Enable Input (EO), is HIGH, the state of the Latch Outputs (Qn) can be determined
from the Truth Table (see below). When the Output Enable Input (·EO) is LOW, the Latch Outputs are
in the high impedance OFF state. The Output Enable Input (EO) does not affect the state of the latch.
•
•
•
•

3-STATE BUFFERED OUTPUTS (ACTIVE HIGH)
COMMON OUTPUT ENABLE·
SET INPUTS TO EACH LATCH (ACTIVE LOW)
RESET INPUTS TO EACH LATCH (ACTIVE LOW)

3

4

7

PIN NAMES

6

11

12

15

14

40448

EO

Output Enable Input

SO-53

Set I nputs (Active LOW)

RO-R3

Reset I nputs (Active LOW)

00- Q 3

3·State Buffered Latch Outputs

13

9

10

1

TRUTH TABLE
INPUTS
EO

OUTPUT
Qn

Sn
X

Rn
X

H

L

H

H

H

H

L

L

H

L

L

L

H

H

H

No Change

L

H
L
X

c:::

Vee

Pin 16

VSS

Pin

8

NC

Pin

2

High Impedance

HIGH Level
Level

CONNECTION DIAGRAM
DIP (TOP VIEW)

= LOW

= Don't Care

LOGIC DIAGRAM

16

15
14
13

12
LATCH

LATCH

LATCH

LATCH

11

10

EO

®
00

VOO
VSS
NC

0

0,

02

03

= Pin 16
= Pin 8
= Pin 2
= Pin Numbers

NOTE:
The F·latpack version has the same
pinouts (Connection Diagram) as the
Dual In-line Package.

7-88

FAIRCHILD CMOS • 40448
DC CHARACTERISTICS: VDD as shown, VSS = 0 V (See Note 1)
LIMITS
SYMBOL

PARAMETER

MIN

Output OFF
IOZH

Current HIGH

Output 0FF
IOZL

Current LOW
Quiescent
Power

IDD

Supply
Current

TYP

MAX

MIN

TYP

MAX

MIN

TYP

12
0.4

XM

MAX

J1.A

MIN,25°C

12
-12
-0.4

XM

8

16

30

60

120

1

2

4

30

60

120

=

Output Returned
to VDD, EO = VSS

MAX
MIN,25°C
J1.A

MAX

Output Returned

MIN,25°C

to VSS, EO = VSS

MAX

- 12
4

AC CHARACTERISTICS: VDD as shown, VSS = 0 V, T A

TEST CONDITIONS

MIN,25°C

-1.6

XC

XM

TEMP

MAX
1.6

XC

XC

UNITS

VDD=15V

VDD = 10 V

VDD = 5 V

MIN,25°C
J1.A

MAX

All inputs at

MIN,25°C

o V or VDD

MAX

25°C (See Note 2)
LIMITS

SYMBOL

PARAMETER

VDD = 10 V

VDD = 5 V
MIN

TYP

MAX

MIN

TYP

MAX

UNITS

VDD = 15V
MIN

TYP

TEST CONDITIONS

MAX
CL = 50 pF,

tPLH

Propagation Delay, Sn to On

70

135

30

24

65

52

ns

RL = 200 k!1
Input Transition

Times.;; 20 ns
70

135

30

65

20

52

ns

30

70

15

40

12

32

ns

tpZL

42

90

20

50

15

40

ns

(RL = 1 k!1 to VDD)

tPHZ

22

55

20

50

15

40

ns

(RL = 1 k!1 to VSS)

30

70

20

50

15

40

ns

(RL = 1 k!1 to VDD)

60

135

30

75

20

45

ns

60

135

30

75

20

45

ns

tpHL
tpZH

Propagation Delay, Rn to On
Output Enable Time
Output Disable Time

tPLZ
tTLH

Output Transition Time

tTHL
twSn

Minimum Sn Pulse Width

55

27

25

14

20

10

ns

twRn

Minimum Rn Pulse Width

55

27

25

14

20

10

ns

(RL = 1 k!1 to VSS)

NOTES:
1.
2.

Additional DC Characteristics are listed in this section under 40008 Series CMOS FamilY Characteristics.
Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.

7-89

FAIRCHILD CMOS • 40448
SWITCHING WAVEFORMS

EO

Q n ----90-%""'\1

OUTPUT ENABLE TIME
(tpZH) AND OUTPUT DISABLE TIME (tPHZ)

OUTPUT ENABLE TIME
ItPZL) AND OUTPUT DISABLE TIME (tpLZ'

50%

\\.-MINIMUM SN AND RN PULSE WIDTHS

7-90

FAIRCHILD CMOS • 40448
TYPICAL ELECTRiCAL CHARACTERISTICS

POWER DISSIPATION
VERSUS FREQUENCY
1000

T~ J~5 C

IIJl~~ ~

100
10

.;d)
1.0

~

:-

~~~~

,~-l ~

f:i"

~~ ~~~-l

1

1;::7
~~
~

Vel- 1SpF-

t-

-

el"' 50pF-

INPUT FREQUENCY - Hz

PROPAGATION DELAY,

PROPAGATION DELAY
s" OR TO Qn
VERSUS TEMPERATURE

Rn OR s" TO Qn VERSUS

Rn

LOAD CAPACITANCE
140

r!i
~
I",

,-'---r-,--,--r---,-,-,
TA 25 C

~

~

100
CL = 15 pF

I

r!i

120~-1-~-1--t-~r--+__~~

90

g

1£

a:

a:

I~ 100r--i--t---~-t-~~-t--r~

o

80
<;~

70

I",

w~\..'

~- 60
o

40

~

30

~

is

g:

20

I

~ 10

...

....-V

w\..~1o'

50

£V

2

o

-l0i---.. . . .
\J 0",,\0'1

~5V

-

tp,-,""\' tpHL' Voo '" 1

~ l - t-

t ~60

-40

-20

0

20

40

60

80

100 120

TA - AMBIENT TEMPERATURE _ DC

CL - LOAD CAPACITANCE - pF

7-91

140

40458
21-STAGE BINARY COUNTER
GENERAL DESCRIPTION - The 4045B is a timing circuit consisting of an 0
staloscillator
circuit, a 21 ..tage binary ripple counter, two output pulse shaping circuits, two output buffers and
one 20V Zener diode for protection against power supply transients. The devioe has an External
Crystal Input (IX)' an External Crystal Output (OX), source connections to the n-channel and p-channel transistors of the oscillator circuit (SN and Sp), and a Data Output (-@
(i)

ZENER DIODE

VSS
'Ovco
VOLTAGECONTROLLED

OSCILLATOR

0

-

E~ ~
SOURCE

FOLLOWER
L...-

°D

Rexta

R,

Rl

Rextb

@ @ @

VOO =
VSS =
0 =

R2
VSS

'0 kn";;R,";;' Mn
'0 kn";;R 2 ";;' Mn
'0 kn";;R 4 ";;' Mn
C,;;;"OOpFatV OO = 6V
C, ;;;'50pF atVOO='O V

7-94

Pin 16
Pin

8

Pin Numbe

FAIRCHILD CMOS. 40468
FUNCTIONAL DESCRIPTION - The 4046B, Micropower Phase-Locked Loop consists of a low power linear Voltage-Controlled Oscillator
(VCO), a Source Follower circuit (SF), two Phase Comparators (PCI and PCI!) and a Zener diode_
VOLTAGE-CONTROLLED OSCILLATOR
The VCO requires one external capacitor (Cl) and one external resistor (R 1) to determine operational frequency range_ External resistor R2 is
used to allow for frequency offset, if required_ It is recommended that Rl and R2 have a value between 10 kil and 1 Mil. At VOO = 5 V, Cl
should be greater than or equal to 100 pF, and at VOO = 10 V, Cl should be greater than or equal to 50 pF.
External resistor R3 and external capacitor C2 combined serve as a low-pass filter to the Voltage-Controlled Oscillator Input Uvea). The user
is allowed a wide range of resistor-to-capacitor ratios for R3 and C2 because of the high imput impedance at IVCO (approximately 10 12 il).

To avoid loading of the lowilass filter, the Oemodulator Output (00) should be connected through external resistor R4 as shown in the Block
Oiagram. It is recommended that R4 have a value between 10 kil and 1 Mil. If the 00 output is not utilized it must be left open.
The Voltage-Controlled Oscillator Output (OVCO) provides a 0.3 VOO to 0.7 VOO output voltage swing and may be connected to the
Comparator Input (lC). 0VCO may, also be connected indirectly to IC via CMOS frequency dividers (j.e., the 4018B, 4022B, 4029B, 4040B,
4518B, 4520B, 40160B, 40161 B, 40162B, 40163B, 40192B, and 40193B.)
An Enable Input (E) to the VCO and SF is provided for minimum stand-by power dissipation. With the
SF are OFF. With E LOW, both are enabled.

E Input HIGH both the VCO and the

PHASE COMPARATORS
For direct-coupling between OVCO and IC, the voltage swing at 0VCO must be within standard CMOS logic levels (VOH ;;. 0.7 VOO and
VOL <; 0.3 VOO); otherwise the signal from OVCO must be capacitively coupled to the self-biasing amplifier at the IS Input.
Phase Comparator I is an Exclusive OR circuit (lC Ell IS). For maximum lock range, inputs to IC and IS must have 50% duty cycles. (Lock range,
2fL, is defined as that frequency range of input signals upon which the 4046B will stay locked from an initial locked condition). With no signal
or noise input, Phase Comparator I provides an average output voltage equal to VOO/2 at the OPCI Output. This average output voltage is
supplied to the IVCO Input through the low-pass filter, which in turn forces the VCO to oscillate at a center frequency (fO).
Capture range 2fC, is defined as that frequency range of input signals upon which the 4046B will lock from an initial unlocked condition.
Capture range for PCI is directly dependent upon the characteristics of the low-pass filter network and may be as great as the lock range. Thus,
PCI allows the user a phase-locked loop system which will remain in a locked condition despite high amounts of noise in the input signal.
It should be noted that with the use of PCI the system may lock onto input signals with frequencies that are near harmonics to the center
frequency of the VCO. It should further be noted that the phase angle between the IC and IS Inputs will vary between 0° and 180°. At the
center frequency the phase angle is 90°. Figure 2 illustrates a typical Phase Angle versus Average Output Voltage response characteristic for
PCI. Figure 3 illustrates the typical waveforms for a phase-locked loop system employing PCI and locked at a center frequency.
Phase Comparator II is edge-triggered digital memory network with four flip-flop stages, associated control circuitry and a 3-state output,
controlled internally. PCII triggers on LOW-to-HIGH transitions at the Signal (IS) and Comparator (lC) Inputs and is independent of duty cycle
at these inputs. If the input frequency at IS is higher than the input frequency at IC, the p-channel output transistor at OPC" is turned "ON"
continuously, pulling the output (OPCII) toward VOO. If the input frequency at IC is higher than the input frequency at IS, the n-channel
output transistor at OpC" is turned "ON" continuously, pulling the output toward VSS. If the input frequencies at IS and IC are equal, but IS
lags IC in phase, the n-channel output transistor is turned "ON" for a period of time corresponding to the phase difference. If the input
frequencies at IS and IC are equal, but IC lags IS in phase, the p-channel output transistor is turned "ON" for a period of time corresponding to
the phase difference. Thus. over a period of time the voltage at capacitor C2 is adjusted until the Ie and IS input signals are of the same
frequency and phase. Once "this stability is reached, both p- and n-channel output transistors at OPCl! are "OFF". 0PCII becomes an open
circuit holding the voltage across C2 constant.
Once this stability is attained, the Phase Pulse Output (OPII) is HIGH indicating a locked condition.
With PC" no phase difference is present between IC and IS over the entire VCO frequency range. Furthermore, since the 3-state Phase
Comparator II Output (OPCII) is mostly in the "OFF" condition, power dissipation through the low-pass filter is minimized. It should also be
noted that 2fC = 2fL independent of the filter network in a phase-locked loop utilizing PCII. Figure 4 shows typical waveforms for a
phase-locked loop system employing Phase Comparator II and locked at a center frequency.

7-95

FAIRCHILD CMOS. 4046B
Fig. 2 CHARACTERISTICS OF PHASE
COMPARATOR I AT THE LOW PASS FILTER OUTPUT.

Fig. 3 A PLL SYSTEM USING PHASE COMPARATOR I.

AVERAGE OUTPUT
VOLTAGE

VOO

~

IS·

VOO

~

§

vOO"2

/

g
~

~

V

~

VSS
VOH

Ie

.

VOL
VOH

Opel

VOL
_VOH

IVCO~

-VOL

90

0

,"0

SIGNAL TO·COMPARATOR
INPUT PHASE OIFFERENCE

Fig. 4 A PLL SYSTEM USING PHASE COMPARATOR II

Fig. 5 TYPICAL LOW·PASS FILTERS.

Voo
IS

I

I

1

'

Vss
(.)

~VOH
,
'
Ie
0plI

I

,

"

:

VOL
C2

VOH

II

I I - - _ VOL

I I

U=

opc,,--P

R3

: :

I-=

2f..,2.
C If

R3

(b)

Input~Output

~
211fL
R3C2

'~l:-"
R4

~C2

VOH

_ _ _ _ VOL

-VOH

IVCO~

_VOL

Fig. 6

,

DESIGN INFORMATION.

Using Ph_ Comparator 1

Using Phase Comparator 2

No signal on input is

VCO in PLL system adjusts to center frequency
(fO)'

VCO in P'LL system adjusts to minimum fre·
quency (f mln ).

Phase angle between IS and Ie

90° at center frequency (fO)' approaching 0°
and 180° at ends of lock range (2f L ).

Always 0° in lock (positive rising edges).

Characteristic

Locks on harmonics of center frequency.
Signal input noise rejection.

Yes

No

HIGH

LOW

Lock frequency range (2fL).

The frequency range of the Input signal on which the loop will stay locked if it was

Capture frequency range (2f C),

initially in lock. 2fL = full veo frequency range = f max - f min .
The frequency range of the input signal on which the loop will lock if it was initially
out of lock.
Oepends on low·pass filter characteristics

fC =fL

(Figure 5) fC .. fLo
Canter frequency (fO)'
0VCO freqency (f).

The frequency of 0VCO when Iveo = 1/2 V DO

K
f'"
NOTE: The information presented
here is meant only as a design guide.

[IVCO -1.65 + VOO -1.35]
Rl
R2
(C 1 + 32) (VOO + 1.6)

MHz (at 25°C)

o f max

~

~

where:
VOO in V; 5 V .. VOO .. 15 V
IVCO in V; 1.65 V.;; IVCO .;;(VO O -1.35 V)
Rl and R2 in Mn; R1 • R2 ;;'0.005 Mn
C1 in pF; C1 ;;'50 pF
K = 0.95@ VOO = 5 V
=0.95@VOO=10V
=1.08@VOO=15V

7-96

fO

:s

~

--;?miT!
I
I
I

0
l-

)
I
I

----- !

fmm
I
I

0

:I
1/2VOD
lVCO

iI

I
I

voo

FAIRCHILD CMOS. 40468
DC CHARACTERISTICS: VOO as shown, VSS = 0 V (Note 1)
LIMITS
SYMBOL

PARAMETER

VOO = 5 V
VOO= 10V
VOO= 15V
MIN TYP MAX MIN TYP MAX MIN TYP MAX

Quiescent

XC

Power
' DO

Supply

XM

Current

UNITS

TEMP

20

40

80

150

300

600

MAX

5

10

20

MIN, 25°C

150

300

600

p,A
p,A

TEST CONDITIONS

MIN,25 C All inputs
at 0 Vor VOO

MAX

ELECTRICAL CHARACTERISTICS: VOO as shown, VSS = 0 V, TA = 25°C
LIMITS
SYMBOL

PARAMETER

VO D =5V
MIN

tTHl

MIN

TYP MAX

V OO -15V
MIN

UNITS

TEST CONDITIONS

TYP MAX
C l =50pF

Propagation Delay,
tTlH

TYP MAX

VOD=10 V

Output Transition
Time

72

48

38

72

48

38

ns

Rl =200 k.!l
Input Transition
Times':; 20 ns

PHASE COMPARATORS
RIN
V,N

Input

lis

Resistance
AC Coupled Input

I'c

Sensitivity for IS
DC Coupled Input
. Sensitivity faris, IC

200
106

400
106

700
t--106

M.!l

200

400

700

mV
pop

See Note 1 for V I H and V I l Characteristics

VOLTAGE CONTROLLED OSCILLATER
0.12

0.04

~.015

0.24

0.08

0.03

0.06

0.05

0.03·

0.12

0.10

0.06

1

1

1

%

50

50

50

%

106

106

106

M.!l

0.9

1.7

2.3

MHz

See Note 6

1.65

1.65

1.65

V

R4>10k.!l

0.1

0.6

0.8

%

See Note 5

7

7

7

V

I Z =50p,A

100

100

100

.!l

I Z =l mA

No Frequency
%/oC

TemperatureFrequency Stability

Linearity
Output Duty
Cycle
Input Resistance
R'N
f max

to 'VCO
Maximum
Operating Frequency

Offset, fmin = 0
See Note 3
Frequency Offset,
fmin*O
See Note 4
See Note 2
0VCQ tied to
'C

SOURCE FOLLOWER
Offset Voltage
Vo

at 00
Linearity

ZENER DIODE
Vz
RZ

Zener Voltage
Zener Dynamic
Resistance

Notes:
1. Additional de characteristics are listed In this section under 40008 Series CMOS Family CharacterIstics.
2. Ivee=2.5 V±. 0.3 V, Rl >10k.!lforVOO=5 V.lvee=5 V±'2.5 V, Rl>400k.!lforVOO=10 V.lvee=7.5 V±'5 V, Rl >1 M.!l
for VOO = 15 V.
3. R2 = ~ %1°C ex l/(f-VOO)_
4. %1°C ex lI(f-Voo).
5. R4>50 k.!l, Ivee = 2.5 V±. 0.3 V for VOO = 5 V. Ivee = 5 V±. 2.5 V for VOO = 10 V, Ivce = 7.5 V±,5 V for VOO = 15 V.
6. Rl = 5 k.!l, R2 = 00, Ivee = VOO, el = 50 pF.

7-97

40478
MONOSTABLE/ASTABLE MULTIVIBRATOR

DESCRIPTION - The 4047B is a Monostable/Astable Multivibrator capable of operating in either the
monostable or astable mode. Operation in either mode requires an external capacitor (C x ) between
pins 1 and 3 (Cext,Rext/Cext) and an external resistor .(R x ) between pins 2 and 3 (Rext,Rext/Cext).
These external timing components (Rx,Cx ) determine the output pulse width in the monostable mode
and the output frequency in the astable mode. The 4047B also has active HIGH and active LOW
astable mode Enable Inputs (EAO,EA1), active HIGH and active LOW Trigger Inputs (TO,Tl) for
operation in the monostable mode,.!!. Retrigger Input IIRT), an Oscillator Output (0), active HIGH
and active LOW flip-flop Outputs (0,01 and an overriding asynchronous Master Reset Input (MRI.

LOGIC SYMBOL

ASTAB.!:,E OPERATION, Astable operation is obtained by either a HIGH on!!!e EAO input or a LOW
on the E:A 1 input. The frequency of the 50% duty cycle output at the 0 and 0 outputs i~determined
by the external timing components (Rx,C x )' A frequency twice that of the 0 and 0 outputs is
available at the Oscillator Output (0). Howevar, a 50% duty cycle is not guaranteed_ The 40478 can be
used as a gated oscillator by controlling the EAO and EAl inputs.
MONOSIABLE OPERATION: Monostable operation is obtained by connecting the EAO input LOW
and the EAl in~t HIGH. The device can be triggered by either a LOJ!!l-to-HIGH transition at the TO
input while the Tl input is LOW o.,!: a HIGH-to-LOW transition at theTl input while the TO is HIGH.
The output pulse width at 0 and 0 is determined by the external timing components (Rx,C x )' The
device can be retriggered by applying a simultaneous LOW-to-HIGH transition to both the Retrigger
Input IIRT) and the TO input while the 1'1 input is LOW.
A HIGH on the Master Reset Input (MR) resets the output flip-flop (0 = LOW,

0: =

VDD

VSS

Pin 14
7

Pin

HIGH independent

of all other input conditions.

•
•
•
•
•
•
•
•

MONOSTABLE OR ASTABLE OPERATION
TRUE AND COMPLEMENTARY BUFFERED OUTPUTS
ENABLED WITH EITHER A LOW OR A HIGH LEVEL IN THE ASTABLE MODE
TRIGGERED ON EITHER A LOW-TO-HIGH OR A HIGH-TO-LOW TRANSITION
IN THE MONOSTABLE MODE
ASYNCHRONOUS MASTER RESET
IN THE MONOSTABLE MODE, OUTPUT PULSE WIDTH IS INDEPENDENT OF THE TRIGGER
PULSE
RETRIGGERABLE OPTION AVAILABLE FOR PULSE WIDTH EXPANSION
IN THE ASTABLE MODE, MAY BE UTILIZED AS EITHER A FREE RUNNING OR GATED
OSCILLATOR WITH A 50% OUTPUT DUTY CYCLE

PIN NAMES
Cext
Rext
Rext/Cext
IRT
TO

1'1
EAO
EA1.
MR

o
o,a

CONNECTION DIAGRAM
DIP (TOP VIEW)

14
13

12

External Capacitor Connection
External Resistor Connection
Common External Capacitor and Resistor Connection
Retriggerlnput
Trigger Input (L-> H Triggered)
Trigger Input (H -> L Triggered)
Enable Input (Active HIGH)
Enable Input (Active LOW)
Master Reset
Oscillator Output
True and Complementary Buffered Outputs

11

10

NOTE:
The F latpak version h.. the .ame
pinouts (Connection Diagram) .. the

Dual In·line Package.

7-98

FAIRCHILD CMOS. 4047'B

BLOCK DIAGRAM

~----------------{13

RETRIGGER
CONTROL

0

14---------(12 I RT

LOW
POWER
ASTABLE
MULTI VIBRATOR

Q

MR

VOO=PIN 14
VSS = PIN 7

o

= PIN NUMBER

MODE SELECTION
INPUTS
EAO

EA1

TO

T1

IRT

H

X

L

H

L

L

Astable Multivibrator (Free Running)

X

L

L

H

L

L

Astable Multivibrator (Free Running)

.n.

H

L

H

L

L

Astable Multivibrator (True Gating)

L

H

L

L

Astable Multivibrator (Complement Gating)

L

V

MR

FUNCTION

L

H

.r

L

L

L

Monostable Multivibrator (Positive-Edge Triggering)

L

H

H

"1-

L

L

Monostable Multivibrator (Negative-Edge Triggering)

L

H

.r

L

.r

L

Monostable Multivibrator (Retriggering)

X

X

X

X

X

H

ReSj!t

H = HIGH LEVEL
L = LOW LEVEL
.n. = POSITIVE PULSE
V - NEGATIVE PULSE
I
POSITIVE-GOING TRANSITION
"1NEGATIVE-GOING TRANSITION
X
DON'T CARE

=
=
=

7-99

FAIRCHILD CMOS • 40478
OPERATION RULES

1. Under normal operating conditions of the 4047B, signals at the Common External Capacitor and Resistor Connection (Rext/Cext) may go
above VOO or below·VsS. A different input protection circuit has been utilized that is not as effective as the standard input protection
circuit on all other inputs. Additional care in handling is advised.
2. An external resistor (Rx) and an external timing capacitor (C x ) are required as shown in the Block Diagram. To simply maintain oscillation
there are no limits on Rx or ex_ However. in the interests of accuracy and predictability it is recommended thatC x be much greater than
stray capacitance in the system and Rx be much greater than the series "ON" resistance of the 40478. In addition, as Rx becomes very
large, short-term instabilities may be introduced. Recommended component values are listed below:

Cx >loopF
Cx ;;' 1000 pF

for astable operation
for monostable operation

10 kn..;; Rx";; 1 Mn
3. I n the astable mode of operation, the output period at the Q output (T Q) is determined as follows:
T Q = 4.40 • Rx • Cx, typically where:
ex is in farads
Ax is in ohms

T Q is in seconds
Actual output period (TQ) will vary with fluctuations in temperature, power supply voltage, and individual device-to-device threshold
voltages.
4.

In the monostable mode of operation the output pulse width at the Q output (twQ) is determined as follows:
tWQ = 2.48 • Rx • Cx, typically where:
ex is in farads

Rx is in ohms
tWQ

is in seconds

Actual output pulse width (twQ) will vary with fluctuations in temperature, power supply voltage, and individual device-to-device threshold
voltages.

5. It should be noted that in the astable mode of operation, the first positive half cycle will have a duration,&qual to tWQ = 2.48 • Rx • Cx.
Succeeding positive half cycles will have a duration of TQ = 4.40 . Rx • Cx,.
6.

Under all operating conditions,
pickup.

ex

and Rx must be kept as close to the circuit as possible to minimize stray capacitance and reduce noise

7. VOO and ground wiring should conform to good high frequency standards so that switching transients on VOO and ground leads do not
cause interaction between devices. Use of a 0.01 to 0.1 /"F bypass capacitor between VOO and ground located near the 4047B is
recommended.
8.

In the retriggering mode of operation extended output pulse width at the Q or Q outputs may be obtained by applying more than one input
pulse to the TO and I RT inputs simultaneously.

9. An overriding active HIGH, Master Reset Input (MR) is provided on the 4047B device. By applying a HIGH to the Master Reset Input, any
timing cycle can be terminated or any new cycle inhibited until the HIGH Master Reset signal is removed. Trigger inputs will not produce
spikes in the output when Master Reset is HIGH.

7-100

FAIRCHILD CMOS. 4047,8
DC CHARACTERISTICS: V DO as shown, V SS = 0 V (Note 1)
LIMITS
SYMBOL

PARAMETER

V DD = 5 V
MIN

Ouiescent
100

TYP MAX MIN

XC

Power

Supply

XM

Current

V DD = IOV

V DD =15V

TYP MAX MIN

UNITS

TEMP

TEST CONDITIONS

TYP MAX

20

40

80

150

300

600

5

10

20

150

300

600

JJA

MIN,25°C
MAX

All inputs
at 0 V or V DD

MIN, 25°C

JJA

MAX

AC CHARACTERISTICS AND SET-UP REOUIREMENTS: V DD as shown, VSS = 0 V, TA = 25°C (See Note 2)
LIMITS
SYMBOL

PARAMETER

VDD=loV
VDD = 15 V
VDD = 5 V
MIN TYP MAX MIN TYP MAX MIN TYP MAX

UNITS

tpLH

Propagation Delay, EAD OR

100

50

125

38

100

tpHL

EAl to 0

100

50

125

38

100

ns

tpLH

Propagation D..:lay, EAD OR

160

74

185

148

ns

tpHL

EAl toOorO

tpLH

~pagation .?elay, TO

OR

TEST CONDITIONS

ns

160

74

185

56
56

148

ns

210

94

235

68

108

ns

tpHL

Tl toOor 0

210

94

235

68

108

ns

tpLH

Propaga~on

116

60

130

46

104

ns

tpHL

to Oor 0

116

60

130

104

ns

RL =200 k!l

tpLH

Propagation Delay, MR to

100

125

100

ns

I nput Transition

100

44
44

125

46
28
28

100

ns

Times ";20 ns

31

75

24

45

ns

25

75

20

45

ns

Delay, TO' I RT

tpHL

OorO

tTLH

Output Transition

tTHL
tw

Time

tee

MR Recovery Time

th
th

Minimum Pulse Width (Any Input)

65

"135

60

135

400

160

170

68

136

44

ns

0

-3~

0

-15

-10

ns

Hold Time, Toto T 1

64

32

32

13

ns

Hold Time, T 1 to TO

64

32

32

16
16

0
26
26

13

ns

C L = 50 pF,

Notes:
1. Additional de characteristics are listed in this section under 4000B Series CMOS Family· Characteristics.
2. Propagation Delays and Output Transition Times are graphic!!!y described in this section under 40008 Series CMOS Family Characteristics.
3, It Is recommended that input rise and fall times to the TO' T l' or I RT Inputs be less than 15 Jls at V DO"" 5 V, 4 IJs at V DO = 10 V and
3

J.ls at V DO = 15 V. Also Input rise and fall times to EAO and EA 1 should be less than 500 ns at any VDO voltage.

SWITCHING WAVEFORMS

TO

MR

MINIMUM PULSE WIDTHS
AND RECOVERY TIME FOR MR

HOLD-TIMES, TO TO T 1 AND T 1 TO TO

CONDITIONS: T, = LOW while TO is triggered on a
LOW-to-HIGH transition. tw and tree also apply when
TO = HIGH and Tl is triggered on a HIGH-to-LOW

Hold Times are shown as positive values,
but may be specified as negative values.

transition.

7-101

4049B • 4050B
4049B HEX INVERTING BUFFER • 4050B HEX
NON-INVERTING BUFFER
DESCRIPTION - These CMOS buffers provide high current output capability suitable for driving TTL or high capacitance loads. Since input
voltages in excess of the buffers' supply voltage are permitted, these buffers may also be used to convert logic levels of up to 15 V to standard
TTL levels. The 4049B provides six inverting buffers, the 4050B six non-inverting buffers. Their guaranteed fan out into common bipolar logic
elements is shown in Table 1.
40498
LOGIC AND CONNECTION DIAGRAM
DIP (TOP VIEW)
NC

4060B
LOGIC AND CONNECTION DIAGRAM
DIP (TOP VIEW)

NC

NC

NC

NOTE:
The F letpak version has the same
pinouts (Connection Diagram) as the
Dual In-line Package.

TABLE 1

Guaranteed fan out of 40498. 40508 into common logic families
INPUT PROTECTION
INPUT 200H
NOMINAL

GUARANTEED
FAN OUT

DRIVEN ELEMENT

TO LOGIC

INPUT~ TRANSISTORS

1

01

TO VSS

Standard TTL. OTL

2

9lS, 93L. 74LS

9

74L

NOTE: Tvpical Breakdown Voltage
of Diode 01 is20V.

16

Conditions: VOO = Vee = 5.0.!. 0.25 V

VOl. .... O.5V, TA" 0 to 7S"e

DC CHARACTERISTICS: VOO as shown, VSS = 0 V, 4049BXM and 4050BXM (See Note 1)
LIMITS
SYMBOL PARAMETER

VOO = 5 V
MIN TYP MAX

VOO-10V
MIN

VOO-15V

UNITS

-1.85
-1.25

IOH

HIGH
Current

-2.5

mA

-0.9

Output

TEMP

TEST CONOITIONS

TYP MAX MIN TYP MAX
MIN,25°C
MAX

VOUT

= 2.5 V for VOO = 5 V

Inputs at 0 or VOO
per

Func~ion

=5 V
= 9.5 V for VOO = 10 V
VOUT = 13.5 Vfor VOO = 15 V
VOUT - 4.5 V for VOO

~0.62

-0.5

-1.85
-1

-5.5

-1.25 -2.5

-0.35

-3.75 -7.5

-0.9

mA

-2.7

MIN,25°C
MAX

VOUT

Inputs at 0 or VOO
per Function

= 0.4 V for VOO = 5 V
= 0.5 V for VOO = 10 V
V OUT = 1.5 V for VOl), = 15 V
VOUT

3.75
Output
IOL

LOW
Current

3

30

10
8

6

2.1

24

16

5.6

48

mA

16.8

MIN,25°C
MAX

VOUT

Inputs at 0 or VOO
per Function

3.3
2.6

rnA

5.2

1.8

MIN,25°C
MAX

VOUT = 0.4 V for VOO - 4.5 V
Inputs at 0 V or VOO
per Function

Quiescent
Power
100

Supply

1

2

4

30

60

120

Current
Notes on the following page.

7-102

p.A

- MIN,25°C

MAX

All Inputs at 0 V or VOO

FAIRCHILD CMOS. 4049B • 4050B
DC CHARACTERISTICS: VOO as shown, VSS = 0 V, 4049BXC and 4050BXC (Cont'd) (See Note 1)
LIMITS
SYMBOL

PARAMETER

VOO=10V

VOO = 5 V
MIN

TYP

MAX

MIN

TYP

VDD=15V
MIN

MAX

TYP

UNITS

-1.5
-1.25
Output
IOH

TEMP

TEST CONOITIONS

MAX

-2.5

-1.0

mA

MIN

VOUT = 2.5 V for V DD = 5 V

mA

25°C

mA

MAX

Inputs at 0 or VDD
per Function

mA

MIN

VOUT = 4.5 V for V OD = 5 V
VOUT = 9.5 V for VOO = 10 V

HIGH
Current

-0.6
-0.5

-1.5
-1

-4.5

-1.25

-0.4

-2.5

-3.75

-1.0

-7.5

-3

mA

25°C

mA

MAX

VO UT = 13.5 V for V DO = 15 V
Inputs at 0 or V DD
per Function

VOUT = 0.4 V for VOO = 5 V
9.6

3.6
3.0
Output
IOL

8

6

2.5

28
16

24

6.6

48

19

mA

MIN

VOUT = 0.5 V for VOO = 10 V

mA

25°C

VO UT = 1.5 V for VOO = 15 V

mA

MAX

Inputs at 0 or VOO
per Function

mA

MIN

VOUT = 0.4 V for VOO = 4.5 V

mA

25°C

mA

MAX

Inputs at 0 V or VOO
per Function

LOW
Current
3.1
2.6

5.2

2.1
Quiescent

Power
100

8

4

Supply

30

16
120

60

MIN,25°C
~A

MAX

All inputs at
OVorVoO

Current

AC CHARACTERISTICS AND SET·UP REQUIREMENTS: VDO as shown, VSS = 0 V, TA = 25°C, 4049B only (See Note 2)
LIMITS
SYMBOL

PARAMETER

VOO =5 V
MIN TYP MAX

VOO=10V
MIN TYP MAX

VOO=15V
MIN TYP MAX

30

65

29

65

130

tpHL

50

105

25

50

17

40

tTLH

73

145

40

80

30

60

33

65

13

25

9

20

tPLH

ITHL

Propagation Delay
Output Transition Time

52

UNITS

ns
ns

TEST CONOITIONS

CL = 50 pF,
RL

= 200 kn

I nput Transition

Times';; 20 ns

NOTES:

1. Additional DC Characteristics are listed in this section under 40008 Series CMOS Family Characteristics.
2. Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.

7-103

•

FAIRCHILD CMOS -4049B - 4050B
AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VDD as shown, VSS = 0 V, TA = 25°C, 4050B only (See Note 2)
LIMITS
PARAMETER

SYMBOL

tpLH

Propagation Delay

tpHL
tTLH

VDD=10V

VDD=5 V
MIN TYP MAX

Output Transition Time

tTHL

MIN

TYP

MAX

VDD=15V
MIN TYP MAX

65

130

30

65

24

52

43

95

23

45

17

36

73

145

90

80

30

60

33

65

13

25

9

20

UNITS

TEST CONDITIONS

CL = 50 pF,

ns

RL = 200 kn
Input Transition

ns

Times';; 20 ns

Notes on preceeding page.

TYPICAL ELECTRICAL CHARACTERISTICS

TYPICAL POWER DISSIPATION
VERSUS FREQUENCY
~ 1000

E
I

~

(!)

0..

1.0

~ 10- 1
10-2
10-3

it

10-4

;;:

I!

i

,;

J

;~

1

102

60
50

w

40

~

~ 30

o

IE

20

I

--'

i

:i:

;r

. I' .....
; ......

...

I
l~ ~~
~~ ; I~ID? ~ 7,Y
......

. CL-15pF
ICL = 50 pF---

I

I

II

103
104
105
106
INPUT FREQUENCY - Hz

CL-15pF

10

1

1

107

!

120

I

110

~
~

15

90 tPLH,VDD - 10 V
80 tPLI!,vDD 15 V"

~o. :~

50

g:

40

I

30

./ / \

~

0

/

.....- ..- I--

l..-t-tPHL,vDD - 6 V

1
tPLH,tPHL ,VDD

1:-

-

/f-""

1

J

10V

l-l---r

-

o

E
I

!Z

/"
-I-

tpHL,VDD

~

~
~

60

I-

I

40

15 V

1

~

r-

IlL

IlL
0
~ -60 -40 -20 0 20 40 6080 100120140
TA - AMBIENT TEMPERATURE - °C

Q
I

~

VOS

/

20
0

o

120

/

I

80
60
40
20

o

//

~

VOS

VGS

I

GATETO

SYRCj v T A r

~ -r-VFS

o

10 V

!,

-i-

r--

7-104

T

~ -30
a::

- r:.+-

1,

A
II
-

V

V
/

I
I

~-40

I
VGS-l~f-""

E

[5V

2
4
6
8 10 12 14 18
VDS - DRAIN TO SOURCE VOLTAGE - V

trLH

VGS 6V
I
VGS - GATE TO
~
SOIURCE VOLTAGE - V'J

a:: -20
a::
::>
:- VGS = \0 V
<.J

Q

f-

~ e::::-

/~

TA = 25'C

«

!Zw

/\ .......
.....

VDD 16 V
W ~ 00 00100lWl~100
CL - LOAD CAPACITANCE - pF

E -10

i

.....

trHL

\

P-CHANNEL DRAIN
CHARACTERISTICS

o
16V-

V

/ ~~
'--

TA = 25'C
140

2

E

,,\

80

00 l001Wl~100
CL - LOAD CAPACITANCE - pF

~ 100
a::
<.J
2

\
\\. VvD?=l~ ~

VDD = 5 V

I!: 100

00

~

/1\

;:: 140

iii

~ 120

.....--""'r-"

tPHL, VDD - 10 V

o w

~

>-

--

trLI~/ ~

TA = 25'C

2 160

1"1.

.....

I 200
w
::; 180

;:

160

«

::>

-..-

tPLH,tPHL,VDD - 16 V

_\

k::::;:: ~ :.r-- I~-

20
• 10

1\
;\

/'

~V

/

V

y

tPLH,vDD SVtPHL,VDD 6V, / '

100

o

!

1 1

TA-26°C

OUTPUT TRANSITION TIME
VERSUS LOAD CAPACITANCE

o

c

N-CHANNEL DRAIN
CHARACTER ISTICS

/

'-\PL~,VDD ~

Q

15

~i

PROPAGATION DELAY
VERSUS TEMPERATURE

I

~

Ii
Ii

!

o

ffi

:

}j ~ Vi

VPD=10V!

2

~
Ci

I 11

[III

'+I .:~ _:...v'6~ = 15 'V

10

a::
w

iill

III

100

PROPAGATION DELAY VERSUS
LOAD CAPACITANCE

-50

o

-

V

I

-2 -4 -6 -8 -10 -12 -14 -16
VDS - DRAIN TO SOURCE VOLTAGE - V

40518
8-CHANNEL ANALOG MULTIPLEXER/DEMULTIPLEXER
DESCRIPTION - The 4051 B Is an 8-Channel Analog Multiplexer/Demultiplexer with three Address
Inputs (AO-A2 1, an active LOW Enable Input (El eight Independent Inputs/Outputs (Y O-Y 7 ) and a
Common Input/Output (ZI.

LOGIC SYMBOL

The 4051 B contains eight bidirectional analog switches, each with one side connected to an Independent Input/Ou~ut (Y O-Y 7 ) and the other side connected to a Common Input/Output (Z). With the
Enable Input (E) LOW, one of the eight switches is selected (low Impedance, ON state) by the three
Address Inputs (AO-A2 ). With the Enable Input (E) HIGH, all switches are in the high impedance
OFF state, independent of the Address Inputs.

V DD and VSS are the two supply voltage connections for the digital control inputs (AO-A2 , f). Their
voltage limits are the same as for all other digital CMOS. The analog Inputs/outputs (Y 0-Y7' Z) can
swing between V DD as a positive limit and VEE as a negative limit. VDD-V EE may not exceed 15 V.
For operation as a digital multiplexer/demultiplexer, VEE Is connected to VSS (typically ground).
•
•

ANALOG OR DIGITAL MULTIPLEXER/DEMULTIPLEXER
COMMON ENABLE INPUT (ACTIVE LOW)

13 14 15 12

11

10

1

5

2

AOYO Y, Y2 Y3 Y4 Y5 Ya

4

Y7

A,
40518

PIN NAMES
YO-Y 7
~0-A2
E
Z

Independent Inputs/Outputs
Address Inputs
Enable Input (Active LOW)
Common Input/Output
TRUTH TABLE

INPUTS

CHANNELS

E

A2

A1

AO

YO-Z

Y1-Z

Y2 -Z

Y3 -Z

Y4 -Z

Y5 -Z

YS-Z

Y7-Z

L
L
L
L
L
L
L
L
H

L
L
L
L
H
H
H
H
X

L
L
H
H
L
L
H
H
X

L
H
L
H
L
H
L
H
X

ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF

OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF

OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF

OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF

OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF

OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF

OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF

OFF
OFF
OFF
OFF
·OFF
OFF
OFF
ON
OFF

L
H

LOW Level
HIGH Level

X

Don't Care

Voo

Vss
VEE

Pin 16
Pin 8
Pin 7

CONNECTION DIAGRAM
DIP (TOP VIEW)

4051B FUNCTIONAL LOGIC DIAGRAM
y

7

o

y6

y ~,

16
Y"

Y3

® ® 0 @

15
14

13

001--1--+-+-t-J
0,1--1--+-+-+--1-'

12

0,1--1--+-+-+--1------~~~===

11

0,1----1--+-+-+0
0,1----1--+-+,

10

0,1--1--+....
06

0,
10FBDECQDERANQ

LEVELCDNVERTER

Voo
VSS
VEE

o

=
=

Pin 16
Pin 8
Pin 7

NOTE:
The Flatpak version has the same
pinouts (Connection

= Pin Numbers

Dual I n-line Package.

7-105

Diagram as the

FAIRCHILD CMOS. 40518
DC CHARACTERISTICS: VOO as shown, VEE = 0 V (See Note 1)
LIMITS
SYMBOL

PARAMETER

ON
RON

XC

Resistance
XM

VOO= 5 V
MIN ·TYP MAX

VOO = 10 V
MIN TYP MAX

VOO=15V
MIN

TYP

UNITS

TEMP

.0.

25°C

TEST CONOITIONS

MAX
MIN

95

900

55

380

35

210

100

1000

65

500

40

2BO

125

1100

100

600

65

340

MAX

90

850

50

340

30

190

MIN

100

1000

65

500

40

280

150

1150

110

660

70

370

.0.

Vis = VOO to VEE
Note 2

25°C
MAX

"A" ON Resist·
ARON

onee Between Any

10

25

.0.

5

25°C

Note 2

Two Channels
OFF State
Leakage
Current, All
IZ

Channels OF F
Any
Channel
OFF
Quiescent
Power

100

Supply
Dissipation

XC

800

XM

80

XC

100

XM

10

XC
XM

~-VOO
VSS= VOO/2
Vis = VOO or VEE
nA

Vos = VEE or VOO

40

80

150

300

600

5

10

20

150

300

600

7-106

Vos = VEE or VOO
E = VSS - VOO/2
Vis = VOO or VEE

20

Notes on following page.

25°C

IlA
IlA

MIN,25°C
MAX
MIN,25°C
MAX

VSS = VEE
All inputs at
VOO Qr VEE

FAIRCHILD CMOS. 4051B
AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VOO as shown, VEE = 0 V, TA = 25°C ISee Note 3)
LIMITS

SYMBOL

PARAMETER

VOO = 5 V
MIN

TYP

MAX

VOO=10V
MIN

TYP

MAX

VOO=15V
MIN

TYP

tpLH

Propagation Delay,

25

10

6

tpHL

Input to Output

10

6

4

tpLH

Propagation Delay,

170

95

80

tPHL

Address to Output

210

125

95

185

95

75

205

105

85

1250

1130

1080

1240

1120

1070

tpZL

Output Enable Time

tpZH
tpLZ

Output Disable Time

tpHZ

UNITS

TEST CONOITIONS

MAX
CL = 50pF, RL =200 kn
ns

-

E = VSS = VEE,

ns

ns

An or Vis = VOO or VEE
Note 5
CL = 50 pF, RL = 1 kn
E or An = VSS = VEE

ns

Vis = VOO or VEE
Note 5

--

RL = 10 kl1
Distortion, Sine

Wave Response

0.2

0.2

0.2

%

VSS = VOO/2, E = VEE,
Vis = VOO/2 Isine wave) POp
lis = 1 kHz
RL = 1 kl1 E = VEE
Vis = VOO/2 Isine wave) Pop

Crossta I k Between

1

Any Two Channels

MHz

at -40 dB
VSS = VOO/2, 20 L0910
IV oslVis) = -40 dB
RL = 1 kn, VSS = VOD/2

OFF State

MHz

1

Feedthrough

E= VOO
Vis = VDO/2 Isine wave)p-p
20 L0910 IV oslVis) = -40 dB

ON State
IMAX

Frequency Response

13

40

70

MHz

RL = 1 kl1, E = VSS
Vis = VDO/2 Isine wave)p-p
VSS = VOO/2
20 L0910 IVoslVos @ 1 kHz)
= -3 dB

NOTES:

1.

Additional DC Characteristics are listed in this section under 4000B Series CMOS Family Characteristics.

2.
3.
4.
5.
6.

E

= VSS RL = 10 kn, any channel selected and VSS = VEE or VOD/2'
Propagation Delays and Output Transition Times are graphically described in this section under 4000B Series CMOS Family Characteristics.
Vis/Vas is the voltage signal at an Input/Output terminal (Y n/Zn).
VIN = VOO (Square Wave), Input transition times ~ 20 ns, RL = 10 kn.
In certain applications, the current through the external load resistor (RL) may include both VOO and signal line components. To avoid
drawing VOO current when switch ~urrent flows into terminals 1, 2, 4, 5, 12, 13, 14,?r 15 the VOltage dro~ across t.he bidirectional sw.i~Ch
must not exceed 0.5 V at T A ~ 25 C, or 0.3 V at T A> 25 C. No VOO current will flow through RL If the sWitch current flows Into
terminal 3.

7-107

•

40528
DUAL 4-CHANNEL ANALOG MULTIPLEXER/DEMULTIPLEXER
DESCRIPTION - The 4052B is a Dual 4-Channel Analog Multiplexer/Demultiplexer with common
channel select logic_ Each Multiplexer/Demultiplexer has four independent Inputs/Outputs (Y O-Y 3 )
and a Common Input/Output (Z). The common channel select logic includes two Address Inputs
(AO' A1 ) and an active LOW Enable Input (E).

LOGIC SYMBOL

Both multiplexer/demultiplexers contain four bidirectional analog switches, each with one sIde
connected to an Independent Input/Output (Y 0-Y3) and the other side connected to a Common
Input/Output (Z). With the Enable Input LOW. one of the four switches is selected (tow impedance.
ON state) by the two Address Inputs. With the Enable Input HIGH. all switches are in the high impedance OFF state. independent of the Address Inputs.

V DD and VSS are the two supply voltage connections for the digital control inputs (AO' A 1 • E). Their
voltage limits are the same .as for all other digital CMOS. The analog inputs/outputs (Y 0-Y3' Z) can
swing between V DO as a positive limit and VEE as a negative limit. VOO-VEE may not exceed 15 V.
For operation as a digital multiplexer/demultiplexer. VEE is connected to VSS (typically ground).
•
•

12 14 15 11

10

AO

1

5

2

4

YO a Yla Y2a Y3a YOb Ylb Y2b Y3b

Al

40528

DIGITAL OR ANALOG MULTIPLEXER/DEMULTIPLEXER
COMMON ENABLE INPUT (ACTIVE LOW)
13

Independent Input1/0utputs
Independent Inputs/Outputs
Address Inputs
Enable Input (Active LOW)
Common Input/Output

VDD

~

PIN 16

VSS~PIN8
VEE~PIN7

TRUTH TABLE
INPUTS
E

A1

AO

YO-Z

L
L
L
L
H

L
L
H
H
X

L
H
L
H
X

ON
OFF
OFF
OFF
OFF

L = LOW Level, H

= HIGH

CHANNELS
Y1 -Z Y2-Z

Y3 -Z

OFF
ON
OFF
OFF
OFF

OFF
OFF
OFF
ON
OFF

OFF
OFF
ON
OFF
OFF

CONNECTION DIAGRAM
DIP (TOP VIEW)

Level, X = Don't care

4052B FUNCTIONAL LOG1C DIAGRAM

,

4

Y3b

Y'b

5

1

Y,b

11

YOb

(iJ)
Y3 ,

Y"

12

14

Y"

Yo,

16

BIDIRECTIONAL
ANALOG SWITCHES

TG

®--

AD

E

J-

15

00

~TG

0-

A,

0,

CD-<

E

0,

TG

TG

E

E

14

t- ~
t13

13

12
11

E

10

03
TG

1·0F-4 DECODER
AND LEVEL CONVERTER

VOO
VSS
VEE

~

Pin 16

~

Pin 8

~

Pin 7

TG

TG

TG

O~ Pin Number

E

E

tt- ~

E

I-

E

t-

NOTE:

The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual In-line Package.

7-108

FAIRCHILD CMOS. 40528
DC CHARACTERISTICS: VOO as shown, VEE

=

0 V (See Note 1)
LIMITS

SYMBOL

PARAMETER

MIN

ON
RON

XC

Resistance
XM

VOO-10V

VOO = 5 V
TYP

MAX

MIN

TYP

MAX

VOO=15V
TYP MAX

UNITS

TEMP

"

TEST CONDITIONS

MIN

95

900

55

380

35

210

MIN

100

1000

65

500

40

280

25°C

125

1100

100

600

65

340

90

850

50

340

30

190

100

1000

65

500

40

280

150

1150

110

660

70

370

MAX
MIN

"

Vis = VOO to VEE
Note 2

25°C
MAX

"A" ON ResistARON

ance Between Any

10

25

5

"

Two Channels
OFF State
Leakage
Current, All
IZ

Chan nels 0 F F
Any
Channel
OFF
Quiescent
Power

100

Supply
Dissipation

XC

800

XM

80

XC

100

XM

10

XC
XM

nA

25°C

Note 2

25°C

E = VOO,
VSS = VOO/2
Vis = VOO or VEE
Vas = VEE or VOO
E = VSS = VOO/2
Vis = VOO or VEE
Vas = VEE or VOO

20

40

80

150

300

600

5

10

20

150

300

600

/-LA
/-LA

MIN,25°C
MAX
MIN,25°C
MAX

VSS = VEE
All inputs at
VOO or VEE

Notes on following page.

•

7-109

FAIRCHILD CMOS. 40528
AC CHARACTERISTICS ANO SET-UP REQUIREMENTS: VOD as shown, VEE = 0 V, TA = 25°C (See Note 3)
LIMITS
SYMBOL

PARAMETER

VOO= 5 V
MIN

TYP

MAX

VDO=10V
MIN

TYP

MAX

VDD= 15 V
MIN

TYP

tpLH

Propagation Delay,

25

10

6

tpHL

I nput to Output

10

6

4

tPLH

Propagation Delay,

170

95

80

tPHL

Address to Output

210

125

95

185

95

75

205

105

85

1250

1130

1080

1240

1120

1070

tpZL

Output Enable Time

tpZH
tpLZ

Output Disable Time

tpHZ

UNITS

TEST CONDITIONS

MAX
ns
ns

CL = 50 pF, RL = 200 kn
E = VSS = VEE,
An or Vis = VDD or VEE
Note 5
CL -50pF, RL -1 kn

ns
ns

E or An = VSS = VEE
Vis = VDO or VEE
Note 5
RL=10kn

Distortion, Sine

Wave Response

0.2

0.2

0.2

%

VSS = VDO/2,

E=

VEE,

Vis = VOO/2 (sine wave)p-p
lis = 1 kHz
RL = 1 kn,E = VEE
Vis = VDD/2 (sine wave)p-p

Crosstalk Between

MHz

1

Any Two Channels

at -40 dB
VSS = VDO/2, 20 L09l0
(V oslVis) = -40 dB
RL = 1 kn, VSS = VoO/2

OFF State

MHz

1

Feedthrough

E =VOO
Vis = VOO/2 (sine wave) p-p
20 L09l0 (VoslVis) = -40 dB
RL = 1 kn, E = VSS

ON State
IMAX

Frequency Response

13

40

70

MHz

Vis = V 00/2 (sine wave) p-p
VSS = VDO/2
20 L09l0 (VoslVos @ 1 kHz
= -3 dB

NOTES:
1. Additional DC Characteristics are listed in this section under 4000B Series CMOS Family Characteristics.
2. E = VSS,RL = 10 kil, any channel selected and VSS "" VEE or VOO/2.
3, Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.
4. Vis/Vas is the voltage signal at an Input/Output terminal (Y n/Zn).
5. VIN = VOO (Square Wave), Input transition times'" 20 ns
6. In certain applications, the current through the external load resistor (RL) may include both VOO and signal line components. To avoid
drawing V OD current when switch current flows into terminals 1, 2, 4, 5, 11, 12, 14, or 15 the voltage drop across the bidirectional switch
must not exceed 0.5 V at T A ~ 2SoC, or 0.3 V at T A > 2SoC. No VOO current will flow through R L if the switch current flows into
terminals 3 or 13.

7-110

40538
TRIPLE 2-CHANNEL ANALOG \Y1ULTIPLEXER/DEMULTIPLEXER

DESCRIPTION - The 4053B is a Triple 2-Channel Analog Multiplexer/Demultiplexer with a common
Enable Input (E). Each Multiplexer/Demultiplexer has two Independent Inputs/Outputs (YO,Y1), a
Common Input/Output (Z), and a Select Input (S). Each multiplexer/demultiplexer contains two
bidirectional analog switches, each with one side connected to an Independent Input/Qutput (YO,Y1)
and the other side connected to a Common Input/Output (Z). With the Enable Input (E) LOW, one of
the two switches is selected (low impedance, ON state) by the Select Input (S). With the Enable Input
(E) HIGH, all switches are in the high impedance OFF state, independent of the Select Inputs (Sa-Sc).

LOGIC SYMBOL

12

VDD and VSS are the two supply voltage connections for the Digital Control Inputs (Sa-Sc:E)' Their
voltage limits are the same as for all other digital CMOS. The analog Inputs/Outputs (YO,Y1,Z) can
swing between VDO as a positive limit and VeE as a negative limit. VDD-VEE may not exceed 15 V.
For operation as a digital multiplexer/demultiplexer, VEE is connected to VSS (typically ground).

•
•

13

2

1

5

3

11

10

ANALOG OR DIGITAL MULTIPLEXER/DEMULTIPLEXER
COMMON ENABLE INPUT (ACTIVE LOW)
14

15

4

Pin 16

PIN NAMES
YOa-YOc, Y1a- Y 1c

Independent Input/Outputs

Sa-Sc

Select Inputs

E

Enable I nput (Active LOW)

Za-Zc

Common Input/Outputs

Pin

8

Pin

7

CONNECTION DIAGRAM
DIP (TOP VIEW)

TRUTH TABLE
INPUTS

CHANNELS
16

E

S

YO-Z

Y1-Z

L

L

ON

OFF

L

H

OFF

ON

H

X

OFF

OFF

15
14
13

12

H

HIGH Level

L

LOW Level

X

Don't Care

11

10

NOTE:
The F latpak version has the same
pinouts (Connection Diagram) as the

Dual In-line Package.

7-111

•

FAIRCHILD CMOS. 40538
FUNCTIONAL LOGIC DIAGRAM

I - OF -6
DECODER
AND LEVEL
CONVERTER

@@0CD00
_ Y{h' Y 1a Y Ob

Y 1b YOc Ylc

BIDIRECTIONAL
ANALOG SWITCHES
TG

@@-

Sb

CD -

I-

E

00

Sa

L--JTG

Sc

I-~

E

°1
TG

--0 E

J-

E

°2
TG

I-~

E

°3
TG

l-

E

°4
TG

I-~

E

°5

VDD = PIN 16
VSS=PIN8
VEE=PIN7
o =PIN NUMBER

DC CHARACTERISTICS: VDD as shown, VEE = 0 V (See Note 1)
LIMITS
SYMBOL

PARAMETER

MIN

XC
ON
RON

VDD=10V

VDD= 5 V

Resistance
XM

TYP

MAX

MIN

VDD=15V

TYP

MAX

MIN

TYP

UNITS

TEMP

n

25°C

TEST CONDITIONS

MAX

95

900

55

380

35

210

100

1000

65

500

40

280

125

1100

100

600

65

340

MAX

90

850

50

340

30

190

MIN

100

1000

65

500

40

280

150

1150

110

660

70

370

MIN

n

Vis = VDD to VEE
Note 2

25°C
MAX

"A" ON ResistARON

ance Between Any

10

25

n

5

25°C

Note 2

Two Channels
OFF State
Leakage
Current, All
IZ

Channels OFF
Any
Channel

XC

800

XM

80

XC

100

XM

10

OFF
Quiescent
Power

IDD

Supply
Dissipation

XC
XM

nA

E = VSS = VDD/2
Vis = VDD or VEE
Vas = VEE or VDD

20

40

80

150

300

600

5

10

20

150

300

600

Notes are on the following page.

7-112

25°C

E = VDD,
VSS = VDD/2
Vis = VDD or VEE
Vas = VEE or VDD

MIN,25°C
p.A

MAX
MIN, 25°C
MAX

VSS = VEE
All inputs at
OVorVDD

FAIRCHILD CMOS. 40538
AC CHARACTERISTII!:S AND SET-UP REQUI REMENTS; VDD as shown, VEE - 0 V, TA - 25°C (See Note 31
LIMITS
SYMBOL

PARAMETER

VDD-5V
MIN

TYP

MAX

VDD-l0V
MIN

TYP

MAX

VDD-15V
MIN

TYP

tPLH

Propagation Delay,

25

10

6

tpHL

Input to Output

10

6

4

tpLH

Propagation Delay,

170

95

80

tpHL

Select to Output

210

125

95

tpZL

Output Enable Time

tpZH
tPLZ

Output Disable Time

tPHZ

185

95

75

205

105

85

1250

1130

1080

1240

1120

1070

UNITS

TEST CONDITIONS

MAX
ns

CL - 50 pF RL -200 kn
E - VSS - VEE,

ns
ns

Sn or Vis - VDD or VEE
Note 5
CL - 50 pF , RL - 1 kn
Ear Sn = VSS - VEE

ns

Vis - VDD or VEE
Note 5
RL-l0kn

Distortion, Sine
Wave Response

0_2

0.2

0.2

%

VSS - VDD/2, E - VEE,
Vis - VDD/2 (sine wavelp-p
lis

= 1 kHz

RL - 1 kn E - VEE
Vis - VDD/2 (sine wavelp-p

Crosstalk Between

MHz

1

Any Two Channels

at -40 dB
VSS - VDD/2, 20 LoglO

OFF State
Feedthrough

MHz

1

(V oslVisl - -40 dB
RL - 1 kn, VSS - VDD/2
E - VDD
Vis - VDD/2 (sine wavelp-p
20 L0910 (VoslVisl
RL

ON State
fMAX

Frequency Response

13

40

70

MHz

= 1 kn,

= -40 dB

E = VSS

Vis - VDD/2 (sine wavelp-p
VSS

= VDD/2

20 Log 10 IVoslVos @ 1 kHzI
- -3 dB
NOTES:
1.
2.

Additional DC Characteristics are listed in this section under 40008 Series CMOS Family Characteristics.
E= VSS. AL = 10 kil, any channel selected and VSS = VEE or VOO/2.

3.

Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.

4.

Vis/Vas is the voltage signal at an I nput/Output terminal (Y n/2n)'

5.

VIN = VOO (Square Wave), Input transition times" 20 ns,

6.

In certain applications, the current through the external load resistor (AL) may include both VDD and signal line components. To avoid
drawing V 00 current when switch current flows into terminals 1, 2, 3, 5, 12, or 13 the voltage drop across the bidirectional switch must
not exceed 0.5 V at T A ~ 25°C, or 0.3 V at T A> 25°C. No VOO current will flow through A L if the switch current flows into terminals
4, 14, or 15.
.

7-113

•

40668
QUAD BILATERAL SWITCHES

DESCRIPTION - The 4066B has four independent bilateral analog switches (transmission gates),
Each switch has two Input/Output Terminals (Y n' Zn) and an active HIGH Enable Input (En). A
HIGH on the Enable Input establishes a low impedance bidirectional path between Ynand Zn (ON
condition), A LOW on the Enable Input disables the switch; high impedance between Y nand Zn
(OFF condition),

•
•

LOGIC SYMBOL

DIGITAL OR ANALOG SIGNAL SWITCHING
INDIVIDUAL ENABLE INPUTS (ACTIVE HIGH)

Enable Inputs
Input/Output Terminals
Input/Output Terminals

LOGIC DIAGRAM (1/4 OF A 4066B)
V DD

=

PIn 14

VSS = PIn 7

o

= Pin Numbers

CONNECTION DIAGRAM
DIP (TOP VIEW)

yn------------~--------~~------_,

14

2

13

3

12

4

11

5

10

6

9

7

8

NOTE:

The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual In-line Package.

7-114

FAIRCHILD CMOS. 4066B

DC CHARACTERISTICS: V DO as shown, VSS = 0 V (See Note 1)
LIMITS
SYMBOL

PARAMETER

VOO= 5 V
MIN

ON
RON

TYP

VOO=15V

VOO= 10V

MAX

MIN

TYP

MAX

MIN

TYP

190

900

100

450

80

250

270

1000
1090

120

500

BO

280

170

520

130

300

XC

330
160

850

85

400

60

220

XM

270

1000

120

500

80

280

360

1150

190

550

145

320

Resistance

UNITS

TEMP

n

25°C

MIN
MAX
n

ance Between Any

MIN.

Vaa /2
Vis = Vaa to VSS

MAX
En = Vaa

25

10

n

5

25°C

Two Channels
OFF State
IZ

Leakage
Current
Quiescent
Power

100

Supply
Dissipation

XC
XM
XC
XM

En = Vaa
10 kn to

RL =

25°C

"il" ON Resist·

ilRON

TEST CONOITIONS

MAX

±300

MIN,25°C

+1000
±100

MAX
MIN,25°C

±1000
1
7.5

2

4

15

30

0.25

0.5

1

7.5

15

30

Notes on following page,

7-115

nA
IlA
IlA

MAX

RL = 10 kn toVoo 12
Vis = Vaa or VSS
En = VSS
Vis = Voa or VSS
Vos = VSS or Vaa

MIN,25°C
MAX
MIN,25°C
MAX

All inputs at
Voa or VSS

FAIRCHILD CMOS. 40668
AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VOO as shown, VSS = 0 V, TA = 25°C (See Note 3)
LIMITS
SYMBOL

PARAMETER

VOO = 5 V
MIN

TYP

MAX

VOO=10V
MIN TYP
MAX

VOO=15V
TYP
MAX

UNITS

TEST CONOITIONS

MIN

CL = 50 pF, RL = 200nta VSS
tPLH

Propagation Delay,

8

45

3

30

2

20

tPHL

Yn to Zn or Zn to Y n

8

45

4

30

2

20

32

125

16

60

13

50

32

125

16

60

13

50

ns

Input Transition Times ~ 20 ns

En = VOO

Vis = VOO (square wave)
tpZL

Output Enable Time

tpZH
tPLZ

Output Disable Time

tPHZ

380

380

400

380

380

400

0.4

0.4

ns
ns

CL=50pF,
R L = 1 kn to VSS or VOO
En = VOO (square wave)
J nput Transition Times ~ 20 ns
Vis = VOO or VSS
RL - 10 kn
Input Frequency = 1 kHz

Distortion, Sine

Wave Response

0.4

%

En = VOO
Vis = VOO/2 (sine wavel p-p
RL=lkn

Crosstalk Between

Any Two Switches

0.9

MHz

EA = VOO, EB = VSS
Vis = VOO/2 (sine wave I p-p
20 Lagl0

[Vas (BIIVis (All = -50 dB
I nput Transition Times

Crosstalk, Enable
Input to Output

OFF State
Feedthraugh

50

mV

~

20 ns

RLIOUTI = 1 kn
RLlIN) = 50 n
En = VOO (square wave)
RL - 1 kn, En = VSS

1.25

MHz

Vis = VODI2 (sine wavel p-p
20 LaglO (VasIVis) = -50 dB
RL - 1 kn

ON State
Frequency Response

40

MHz

Vis = VOO/2 (sine wavel p-p
En = VOO' 20 Lagl0

(VasIV as @ 1 kHzl = -3 dB
CL = 50 pF, RL = 1 kn
Enable Input

fMAX

Frequency (Note 41
I nput Switch

Cis

10

MHz

Vas= V isl2 at OC
Vis = VOO
4

pF

4

pF

0.2

pF

Capacitance

Output Switch
Cos

Capacitance
Feedthraugh Switch

Cios

Input Transition Times:E;;;; 20 ns
En;:: VDO (square wave)

VOO = 10 V
En = VSS
Vis = Open
100 kHz or
1 MHz Bridge

Capacitance

NOTES,
1. Additional DC Characteristics are listed in this section under 4000B Series CMOS Family Characteristics.
2.
3.
4.
5.

Vis/Vos is the voltage signal at an Input/Output Terminal (Y n/2n)'
Propagation Delays and Output Transition Times are graphically described in this section under 40006 Series CMOS Family Characteristics.
For f MAX , input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.
In certain applications, the current through the external load resistor (R L ) may include both VOO and signal line components. To avoid
drawing VOO current when switch current flows into terminals 1, 4, 8, or 11 the voltage drop across the bidirectional switch must not
exceed 0.5 V at TA ~ 25°C, or 0.3 V at T A> 2SoC. No VOO current will flow through RL if the switch current flows into terminals 2, 3,
9, or 10.

7-116

40678
16-CHANNEL ANALOG MULTIPLEXER/DEMULTIPLEXER

DESCRIPTION - The 4067B is a 16-Channel Analog Multiplexer/Demultiplexer with four Address
Inputs (A O-A 3 ), 16 Independent Inputs/Outputs (Y O-Y 15)' an active LOW Output Enable input (EO),
and a Common Input/Output (2). The 40678 contains 16 bidirectional analog switches, each with one
side connected to an Independent Input/Output (YO-Y15) and the other side connected to a Common
Input/Output (Z). One of the 16 switches is selected (low impedance, ON state) by the four Address
Inputs (AO-A3) when the Output Enable input (EO) is LOW. All unselected switches are in the high
impedance OFF state. With the Output Enable input (EO) HIGH, all 16 switches are in the high
impedance OFF state. The Analog Input/Outputs (YO-Y15,Z) can swing between VDD and VSS.
VDD-VSS may not exceed 15 V.

CONNECTION DIAGRAM
DIP (TOP VIEW)

24

•
•
•

ANALOG OR DIGITAL MULTIPLEXER/DEMULTIPLEXER
24-PIN PACKAGE
SINGLEPOWERSUPPLY

23
22

PIN NAMES

21

Independent Inputs/Outputs
20

Address Inputs
Common Input/Output

19

Output Enable Input (Active LOW)

18
17

16

LOGIC SYMBOL
15

10
9

8

7

6

5

4

3

2

23

22 21

20 19

18

17

16

10

11

14

12

13

14
13

VDD

Pin 24

VSS

Pin 12

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual I n-line Package.

TRUTH TABLE
INPUTS
A3 A2 A1

CHANNEL
AO

YO·Z

Y1-Z

Y2-Z

Y3- Z

Y4- Z

Y5- Z

Y6-Z

Y7-Z

YS-Z

Yg-Z

YlO- Z Y11' Z

Y 1 2-Z

Y13-Z

Y 14 ·Z

Y 1 5'Z

L

L

L

L

ON

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

L

L

L

H

OFF

ON

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

L

L

H

L

OFF

OFF

ON

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

L

L

H

H

OFF

OFF

OFF

ON

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

L

H

L

L

OFF

OFF

OFF

OFF

ON

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

L

H

L

H

OFF

OFF

OFF

OFF

OFF

ON

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

L

H

H

L

OFF

OFF

OFF

OFF

OFF

OFF

ON

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

L

H

H

H

OFF

OFF

OFF

OFF

OFF

OFF

OFF

ON

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

H

L

L

L

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

ON

OFF

OFF

OFF

OFF

OFF

OFF

OFF

H

L

L

H

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

ON

OFF

OFF

OFF

OFF

OFF

OFF

H

L

H

L

OFF

OFF

OfF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

ON

OFF

OFF

OFF

OFF

OFF

H

L

H

H

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

ON

OFF

OFF

OFF

OFF

H

H

L

L

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

ON

OFF

OFF

OFF

H

H

L

H

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

ON

OFF

OFF

H

H

H

L

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

H

H

H

H

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

ON
OFF

L

LOW Level

H

HIGH Level

EO

='

LOW Level

7-117

ON

•

FAIRCHILD CMOS • 40678

FUNCTIONAL LOGIC DIAGRAM

@@®®®@@@000®®0®®
Y15Y14Y13Y12YllYlO Yg Ys Y7 Y6 Y5 Y4 Y3 Y2 Yl

YO
BI-DI RECTIONAL
ANALOG SWITCHES

-@
-@

TG
AO

00

Al

°1

---ITG

E

ITG
I

E

ITG
I

E

@

~

---

A2

l-l--

°2

@

A3

J-

E

I
I

03
E

~

E

~

I

E

~

I
I TG

E

~

E

~

E

~

I
I TG E

~

ITG

1
°4

ITG
I
°5

ITG

06

°7

ITG

1
08

rI TG

Og

010

ITG

I

®

EO

E

~

E

~

°11

I.

lTG
°12

I TG
I

E

I
I TG

E

~

°13

.~

°14
I

-1

TG

J-

E

°15
VDD = Pin 24

1-0F-16
DECODER
AND
LEVEL
CONVERTER

VSS

o

7-118

= Pin

12

= Pin Number

z

CD

FAIRCHILD CMOS. 40678

DC CHARACTERISTICS: VDD as shown, VSS = 0 V (See Note 1)
LIMITS
SYMBOL

PARAMETER

VDD=5V
MIN

XC
ON
RON

Resistance
XM
"flu

flRON

TYP

VDD =10 V

MAX

MIN

VDD = 15 V

TYP

MAX

MIN

TYP

UNITS

TEMP

fl.

25°C

TEST CONDITIONS

MAX
MIN

95

900

55

380

35

210

100

1000

65

500

40

280

125

1100

100

600

65

340

MAX

90

850

50

340

30

190

MIN

100

1000

65

500

40

280

150

1150

110

660

70

370

fl.

Vis = VDD to VSS
Note 2

25°C
MAX

ON Resist-

an ce Between Any

10

25

fl.

5

25°C

Note 2

Two Channels
OFF State
Leakage
Current, All
IZ

Channels OFF
Any
Channel
OFF
Quiescent

Power
IDD

Supply
Dissipation

XC

EO = VDD

800

XM

80

XC

100

XM

10

Vis= VDD or VSS
Vos = VSS or VOD
nA

25°C
EO = VSS

XC
XM

Vis = VDD or VSS
Vos = VSS or VDD

20

40

80

150

300

600

5

10

20

150

300

600

Notes on following page.

7-119

/lA
/lA

MIN,25°C
MAX

All Inputs at

MIN,25°C

o V or VDD

MAX

FAIRCHILD CMOS. 40678
AC CHARACTERISTICS AND SET-UP REQUIREMENTS, VOO as shown, VSS = 0 V, TA = 25°C (See Note 3)
LIMITS
SYMBOL

PARAMETER

VOO = 5 V
MIN

TYP

MAX

VOO=10V
MIN

TYP

MAX

VOO = 15 V
MIN

TYP

tPLH

Propagation Delay,

25

10

6

tpHL

Input to Output

10

6

4

tPLH

Propagation Delay,

170

95

80

tpHL

Address to Output

210

125

95

185

95

75

tpZH

205

105

85

tpL,Z

1250

1130

1080

1240

1120

1070

tpZL

Output Enable Time
Output Oisable Time

tPI-jZ

UNITS

TEST CONOITIONS

MAX
CL = 50 pF, R L = 200 kn
ns
ns
ns
ns

EO = VSS
An or Vis = VOO or VSS
Note 5
CL - 50 pF, RL@ 1 kn
EO or An = VSS
Vis = VOO or VSS
Note 5
RL=10kn,

Distortion, Sine

Wave Response

0.2

0.2

0.2

%

EO = VSS
Vis = VOO/2 (sine wave) POp
lis = 1 kHz
RL = 1 kn, EO = VSS
Vis = VOO/2 (sine wave)p-p

Crosstalk Between

1

Any Two Channels

MHz

at -40 dB
20 LO§10
(VoslVis) = -40 dB
RL = 1 kfl, EO = VOO

OFF State

1

Feedthrough

MHz

Vis = VOOI2 (sine wave) pop
20 L0910 (V oslVis) = -40 dB

ON State
IMAX

Frequency Response

RL = 1 kn, EO= VSS
13

40

70

MHz

Vis = VOO/2 (sine wave) pop
20 L0910 (VoslVos@ 1 kHz)
= -3 dB

NOTES:
1. Additional DC Characteristics are listed in this section under 40006 Series CMOS Family Characteristics.
2. EO = vss, RL = 10 kS1, any channel selected,
3.

Propagation Delays and Output Transition Times are graphically described in this saction under 40008 Series CMOS Family Characteristics.

4.

Vis/Vos is the voltage signal at an I nput/Output terminal (Y n/Zn)'
V,N"" VOO (Square Wave), Input transition times ~ 20 n5.
In certain applications, the current through the external load resistor (RL) may include both VOO and signal line cOmponents. To avoid
drawing VOD current when switch current flows into terminals 2, 3, 4,6,6,7,8,9,16,17,18,19,20,21,22, or 23 the voltage drop
across the bidirectional switch must not exceed 0.6 V at T A ~ 25°C, or 0.3 Vat T A> 25°C. No VDO current will flow through RL if the
switch current flows into terminal 1.

5.

6.

7-120

40688
8-INPUT NAND GATE
DESCRIPTION - This CMOS logic element provides the positive 8-lnput NAND funct
immunity and pattern insensitivity of output impedance.

for highest noise

4068B LOGIC SYMBOL

Voo = Pin 14

Vss
NC

= Pin 7
= Pins 1, 6, 8

0
0
0
®

PIN NAMES
10

The Flatpak version

Z

12
13

®

14

@

17

NOTE:

10-11

11

Inputs

has the same pinouts

Output

(Connection Dia~
gram) as the Dual

(Active LOW)

In-line Package.

~ ::

DC CHARACTERISTICS: VDD as shown, VSS = 0 V (See Note 1)
LIMITS
SYMBOL

PARAMETER
Quiescent
Power

IDD

Supply

Current

VDD=10V

VDD = 5 V
MIN

XC
XM

TYP

MAX

MIN

TYP

1
7.5

VDD=15V

MAX

MIN

TYP

MAX

2

4

15

30

0.25

1

0.5

7.5

30

15

TEMP

UNITS

TEST CONDITIONS

MIN,25°C
/.LA

MAX
MIN,25°C

/.LA

All inpllts at 0 V
orV DD

MAX

AC CHARACTERISTICS: V DD as shown, VSS = 0 V, T A = 25°C (See Note 2)
LIMITS
SYMBOL

PARAMETER

MIN

MAX

V DD = 15 V
MIN TYP MAX

UNITS

TYP

V DD =10V

V DD = 5 V
TYP

MAX

MIN

TEST CONDITIONS

82

200

40

85

29

68

ns

C L =50pF,

tpHL

88

200

40

85

28

68

ns

RL = 200 kn

tTLH

64

135

32

70

24

45

55

135

23

70

16

45

tpLH

Propagation Delay

Output Transition Time

tTHL

Input Transition

ns

Times';; 20 ns

NOTE:
1. Additional DC Characteristics are listed in this section under 40008 Series CMOS Family Characteristics.
2. Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristic.s.

TYPICAL ELECTRICAL CHARACTERISTICS
POWER DISSIPATION
VERSUS FREQUENCY

PROPAGATION DELAY
VERSUS TEMPERATURE

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE
160

20 40
INPUT FREQUENCY - Hz

60

80 100 120 140

T A - AMBIENT TEMPERATURE - °C

7-121

140

1---1---1---1---1--1-

120

1---I---1---I--/-

20

40

60

80

100

120 140

C L - LOAD CAPACITANCE - pF

160

•

4069UB/74C04/54C04
HEX INVERTER
DESCRIPTION - The 4069UB is a general purpose Hex Inverter which has standard Fairchild input and output characteristics. A single·stage
design has been used since the output impedance of a single·input gate is not pattern sensitive. The 4096UB is a Direct Replacement for the
74C04/54C04.

LOGIC ANO CONNECTION DIAGRAM
DIP (TOP VIEW)
VDD

NOTE:
The F latpak version has the same
pinouts (Connection Diagram) as the
D'aal I n-line Package.

DC CHARACTERISTICS: VDD as shown, VSS

~

0 V (See Note 1)
LIMITS

SYMBOL

PARAMETER

VDD
MIN

Quiescent
Power

IDD

Supply
Current

XC
XM

~5

TYP

VDD~15V

VDD~10V

V
MAX

MIN

TYP

MAX

MIN

TYP

UNITS

TEMP

TEST CONDITIONS

MAX

1

2

4

7.5

15

30

0.25

0.5

1

7.5

15

30

MIN,25°C

p.A
p.A

MAX

All inputs at

MIN,25°C

o V or VDD

MAX

AC CHARACTERISTICS AND SET·UP REQUIREMENTS: VDD as shown, VSS ~ 0 V, TA ~ 25°C (See Note 2)
LIMITS
SYMBOL

PARAMETER

VDD~

MIN

VDD~

5V

TYP

MAX

MIN

10V

TYP

MAX

VDD~

MIN

15V

TYP

UNITS

32

64

16

32

13

26

tPHL

32

64

16

32

13

26

tTLH

45

135

23

70

18

45

45

135

23

70

18

45

tpLH

tTHL

Propagation Delay

Output Transition Time

TEST CONDITIONS

MAX
ns
ns

CL~50pF,

RL

~

200 kU

Input Transition
Times'; 20 ns

NOTES:
1. Additional DC Characteristics are listed in this section under 40008 Series CMOS Family Characteristics.
2. Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.

7-122

FAIRCHILD CMOS • 4069UB/74C04/54C04
TYPICAL ELECTRICAL CHARACTERISTICS

TYPICAL POWER DISSIPATION
VERSUS FREOUENCY

~

1000

~

TA=2r~



0

C L = 15llj II111

w

30

:5w

V DD = 5V

CL

.

c

",,""

..... ~

V

~

... ~~

~~
..."~

35

~

V DD = 15VL\.r.

II

100

'"
...~

PROPAGATION DELAY
VERSUS TEMPERATURE

r-==

w

z

o

i

o

-20

20

I

I

60

I
100

140

TA - AMBIENT TEMPERATURE - °C

OUTPUT TRANSITION TIME
VERSUS LOAD CAPACITANCE

w

160r-~-+~--+-~-+~--+-~~

:0

100

i=

z
o

80r-+--r~--+--r-+

60 I--+--r-+-l-

~

40 1--+--f-:7'f5>""f'--

o

I;' i l l

120r-+--r~--+--r-+--r-+--r~

~

CI

tPLHVDD;10V

tPLH "DO ; 15 "

-60

I

o

J

I\P~L ~D6; 115 V

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

;

~

5

107

_-I--

tpHL "DO =5"
~"OO-~

;;HL VDD ; 10"

INPUT FREQUENCY - Hz

~

~ 1~ pF

i=
iii 100 r-~-+~--h

z


II:

~

80 f-+--t--t-:
60
40

o

CL - LOAD CAPACITANCE - pF

CL - LOAD CAPACITANCE - pF

TYPICALVOLTAGE TRANSFER
CHARACTERISTICS

>
I

15

w

..........

CI



....
...::>....

10

'"

\

'\

::>

0

I

5.0

....

::>

0

>

o
o

\.
5.0

"
10

VIN - INPUT VOLTAGE -

7-123

15
V

40708/74C86/S4C86
QUAD EXCLUSIVE-OR GATE
DESCRIPTION - The 4070B CMOS logic element provides the Exclusive-OR function. The outputs are fully buffered for best performance.
The 4070B is a direct replacement for the 74C86i54C86.

NOTE:

The

Flatpak version has the same

pinout (Connection Diagram) as the
Dual I n-line Package.

LOGIC AND CONNECTION DIAGRAM
DIP (TOP VIEWI
DC CHARACTERISTICS: VDD as shown, VSS = 0 V (See Note 11
LIMITS
SYMBOL

PARAMETER

V DD = 5 V
MIN

Quiescent

XC

Power
IDD

Supply

XM

Current

TYP

V DD =10V
MAX

MIN

TYP

V DD =15V

MAX

0.25

TYP

2

4
30

0.5

7,5

UNITS

TEMP

TEST CONDITIONS

MAX

15

1
7,5

MIN

1
30

15

~A
~A

MIN,25°C
MAX

All inputs at 0 V
orVDD

MIN,25°C
MAX

AC CHARACTERISTICS: V DD as shown, VSS ~ 0 V, TA ~ 25°C (See Note 21
LIMITS
SYMBOL

PARAMETER

V DD
MIN

5V

~

TYP

MAX

VDD~10V

MIN

TYP

MAX

V DD ~ 15 V
MIN TYP MAX

UNITS

TEST CONDITIONS

tpLH

Propagation Delay,

85

170

45

90

27

CL

~

50 pF,

A or B to X

85

170

45

90

27

72
72

ns

tpHL

ns

RL

~

200 kfl

tTLH

Output Transition

50

100

23

50

17

35

ns

tTHL

Time

50

100

23

50

17

35

ns

Input Transition
Times.o;;; 20 ns

NOTES:

1. Additional DC Characteristics are listed in this section under 40008 Series CMOS Family Characteristics.
2. Propagation Delays and Output Transition Times are graphically described in this section under 40006 Series CMOS Family Characteristics.

TYPICAL ELECTRICAL CHARACTERISTICS

~
INPUT FREQUENCY - Hz

?60-40-20 0

20 40 60 80100120140

TA - AMBIENT TEMPERATURE -

7-124

°C

CL - LOAD CAPACITANCE - pF

40718
QUAD 2-INPUT OR GATE
DESCRIPTION - The 4071 B is a positive logic Quad 2-lnput OR Gate. The outputs are fully buffered for highest noise immunity and pattern
insensitivity of output impedance.

LOGIC AND CONNECTION DIAGRAM
DIP (TOP VIEW)

NOTE:

The

F latpak version has the same

pinouts (Connection Diagram) as the
Dual I n-line Package.

DC CHARACTERISTICS: V OD as shown, VSS

~

0 V (See Note 1)
LIMITS

SYMBOL

VOO ~ 5 V

PARAMETER

MIN
Quiescent

MAX

Supply

TYP

':tOO ~ 15 V
MIN

MAX

7.5
0.25
7.5

XM

Current

MIN

1

XC

Power
100

TYP

VOO ~ 10V

TYP

UNITS

TEST CONDITIONS

TEMP

MAX

2

4

15
0.5
15

30
1

MIN,25°C

~A

MIN,25°C

~A

30

All inputs at 0 V
orVO D

MAX
MAX

AC CHARACTERISTICS: V DD as shown, VSS ~ 0 V, TA ~ 25°C (See Note 2)
LIMITS
SYMBOL

PARAMETER

V DD
MIN

Propagation Delay

tpLH
tpHL

Output Transition Time

tTLH
tTHL

5V

~

MAX

V DD ~ 15 V
MIN TYP MAX

UNITS

TYP

VDD~10V

TYP MAX

MIN

TEST CONOITIONS

43

85

22

40

17

32

ns

CL

~

50 pF,

52

100

23

40

15

32

ns

RL

~

200 k!1

45

135

24

70

18

45

ns

I nput Transition

54

135

21

70

15

45

ns

Times <; 20 ns

NOTES:
Additional DC Characteristics are listed in this section under 40006 Series CMOS Family Characteristics.
2. Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.

1.

TYPICAL ELECTRICAL CHARACTERISTICS
~1000

II II v~~ ~1\5Iv
i v~olJ\~~ Uk
v601~ '0 V Jj ~

"'"
;t
""
~

10
1.0

~10-1

>=

« 10- 2

~

B10-3

r-:

....
.

a:
w 10-4

~0.

c
I

TA=25°C

I
w '00

'02

'0 3

~

>-

~

0
Z

o

~
;t

"Pv~o~"V

.. Voo

~~~

"

I

0

IJJlUI

voo~10vl
II II Cl-15pFCL~50pF--104

105

'06

INPUT FREQUENCY - Hz

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

PROPAGATION DELAY
VERSUS TEMPERATURE

POWER DISSIPATION
VERSUS FREQUENCY

'07

80

c

Cl=15pF

~0

60

0.

"~

TA

0

40

tPL~' tpHl

30..20

tPLH. tpHL

10
t?tHi
0
-60

-40

-20

0

"00",5'.1

f:::; .......

I

~L~
""

100

"'""
a:

"QQ

~~-::
,~" ~Q~

80
50

~tJ

0

,10 v

f-- I:-

40

60

80

100

i-

140
120

TA - AMBIENT TEMPERATURE - °C

7-125

0.

40

~V

~

"it~"

p..-

~..l_I,
HL "00/~
"00 ~'5XF- tPlt tPL" 1 '1

0.

0

tP~L ro~ ~ 'I" VI20

>=

I

=25°C

z

50

a:

;!

'40

I
>- 120

70

20
0
0

20

tp\..\'\'W

40

60

80 100120140 160

Cl - LOAD CAPACITANCE - pF

•

4073B
TRIPLE 3-INPUT AND GATE
DESCRIPTION - This CMOS logic element provides the positive Triple 3
noise immunity and pattern insensitivity of output impedance.

LOGIC AND CONNECTION DIAGRAM
DIP (TOP VIEW)

NOTE: The· Flatpak version has the same pinouts (Connection
Diagram) as the Dual In-line Package.

DC CHARACTERISTICS: VOO as shown, VSS = 0 V (See Note 1)
LIMITS
SYMBOL

PARAMETER
MIN
Quiescent
Power

100

Supply
Current

XC
XM

TYP

VOO~15V

VOD=10V

VOO =5 V
MAX

MIN

TYP

MAX

MIN

TYP

2

4

7.5

15

30

0.25

0.5

1

7.5

15

30

1

TEMP

UNITS

TEST CONDITIONS

MAX
MIN,25'C

/.LA
/.LA

MAX

All inputs at

MIN,25'C

OVorVoo

MAX

AC CHARACTERISTICS: VOO as shown, VSS = 0 V, T A = 25'C (See Note 2)
LIMITS
SYMBOL

PARAMETER

VOO =5 V
MIN

VOO = 10 V

TYP

MAX

MIN

TYP

MAX

UNITS

VOO = 15V
MIN

TYP

MAX

40

110

19

55

14

44

tPHL

44

110

26

55

21

44

tTLH

70

135

35

75

25

45

70

135

35

75

25

45

'PLH

tTHL

Propagation Delay
Output Transition Ti me

ns
ns

TEST CONDITIONS

CL=50pF,
RL = 200 kn
Input Transition

Times .. 20 ns

NOTES:
1. Additional DC Characteristics are listed in this section under 40006 Series CMOS Family Characteristics.
2. Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Famify Characteristics.

7-126

40758
TRIPLE 3-INPUT OR GATE
DESCRIPTION - This CMOS logic element provides the positive Triple 3-ln
immu nity and pattern insensitivity of output impedance.

LOGIC AND CONNECTION DIAGRAM
DIP (TOP VIEW)

Vss
NOTE: The Flatpak version has the same pinouts (Connection
Diagram) as the Dual In-line Package.,

DC CHARACTERISTICS: VDD as shown, VSS = 0 V (See Note 1)
LIMITS
SYMBOL

PARAMETER
MIN
Quiescent
Power

IDD

Supply
Current

VDD=10V

VDD - 5 V

XC
XM

TYP

MAX

MIN

TYP

UNITS

VDD=15V

MAX

MIN

TYP

2

4

7.5

15

30

0.25

0.5

1

7.5

15

30

1

TEMP

TEST CONDITIONS

MAX
MIN,25°C

p.A
p.A

MAX

All inputs at

MIN,25°C

OVorVD0

MAX

AC CHARACTERISTICS: VDD as shown, VSS = 0 V, TA = 25°C (See Note 2)
LIMITS
SYMBOL

PARAMETER

VDD = 5 V
MIN

tpLH

Propagation Delay

tPHL
tTLH
tTHL

Output Transition Time

VDD=10V

TYP

MAX

MIN

TYP

59

130

34

62

130

30

70

135

70

135

MAX

UNITS

VDD = 15V
MIN

TYP

MAX

65

28

50

65

24

50

35

75

25

35

35

75

25

35

ns
ns

TEST COND'lTIONS

CL =50 pF,
RL = 200 kn
Input Transition

Times'; 20 ns

NOTES:
1.
2.

Additional DC Characteristics are listed in this section under 40006 Series CMOS Family Characteristics.
Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.

7·127

40768/74C173/S4C173
QUAD D FLI P-FLOP WITH 3-STATE OUTPUT

°

DESCRIPTION - The 4076B is a Quad Edge-Triggered
Flip-Flop with four Data Inputs (00-03),
two active LOW Data Enable Inputs (EDO-ED1), an edge-triggered Clock Input (CP), four 3-State Outputs (QO-Q3), two active LOW Output Enable inputs (EOO, E01), and an overriding asynchronous
Master Reset Input (MR).

LOGIC SYMBOL

Information on the Data Inputs (00-03) is stored in the four flip-flops on the LOW-to-HIGH transition of the Clock Input (CP) if both Data Enable Inputs (EDO-ED1) are LOW. A HIGH on either Data
Enable Input (-EDO-ED1) prevents the flip-flops from changing on the LOW-to-HIGH transition of
the Clock Input (CP), independent of the information on the Data Inputs (00-03).
When both Output Enable inputs (EOO-E01) are LOW, the contents of the four flip-flops areavailable
at the outputs 100-03). A HIGH on either Output Enable input
E01) forces the outputs (00Q3) into the high impedance OFF state.

(mo,

14

A HIGH on the overriding asynchronous Master Reset Input (MR) resets all four Iflip~flops, indepedent
of all other input conditions.
10-"'"".!-.....

•

FULLY INDEPENDENT CLOCK

•
•
•
•
•

3-STATE OUTPUTS
CLOCK IS L .... HEDGE-TRIGGERED
ACTIVE LOW DATA ENABLE INPUTS
ACTIVE LOW OUTPUT ENABLE INPUTS
ASYNCHRONOUS MASTER RESET

12

11

ED

----fep

The 4076B is a direct replacement for the 54C173/74C173.

13

4076B

4

15

VDO

= Pin

16

Vss

= Pin

8

PIN NAMES

Data Inputs

00-0 3
EDO-EDl
EOO, E0 1
CP
MR

Data Enable Inputs (Active LOW)
Output Enable Inputs (Active LOW)
Clock Input (L .... HEdge-Triggered)

00-0 3

Data Outputs

CONNECTION DIAGRAM
DIP (TOP VIEW)

Master Reset Input

TRUTH TABLE
INPUTS
EDO

EDl

H

X

3

OUTPUTS
On

Qn +l

X

X

Qn

H

X

Qn

l

L

l

l

L

L

H

H

4

9

CONDITIONS:
MR

~

EOO

~

EOl

L

~

LOW Level

H

~

HIGH Level

X

~

Don't Care

~

LOW
NOTE:
The Flatpak version has the same pin~
outs (Connection Diagram) as the

Dual I n~line Package.

Q n +l ~ State After Positive Clock Transition

7-128

FAIRCHILD CMOS· 4076B/74C173/54C173
LOGIC DIAGRAM

D3@ ----+-----f
y---ctCP Co 01;>---<>11>-- (D03
MR@

--r:::.o----------__- - - - - l

VDD = Pin 16
VSS = Pin 8
o = Pin Number

7-129

FAIRCHILD CMOS • 4076B/74C173/54C173
DC CHARACTERISTICS: VOO as shown, VSS - 0 V (Note 1)

LIMITS
SYMBOL

PARAMETER
Output OFF

10ZH

Current High

VOO - 5 V
MIN TYP MAX

V OO -10V
MIN

TYP

V OO -15V

MAX

MIN

1.6

XC

12

XM
Output OFF
10ZL

Current LOW

XC

Quiescent

100

Supply

XC
XM

Current

TEMP
MIN,25OC

!JA

MAX

0.4
12

MIN,25°C

-1.6

MIN,25°C

-12

XM

Power

UNITS

TEST CONOITIONS

TYP MAX
Output returned to

VOO' E01 -

MAX

!JA

MAX

Output retu rned to

-0.4

MIN,25°C

VSS'

-12

MAX

VOO

20

40

80

150

300

600

5

10

10

150

300

600

EO O -

VOO

E01 = EO O =

MIN,25°C

!JA

MAX
MIN,25 C

!JA

All inputs at 0 V or
VOO

MAX

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VOO as shown, VSS = 0 V, T A = 25°C (See Note 2)

LIMITS
SYMBOL

PARAMETER

V OO - 5 V
MIN

TYP MAX

VOO = 10 V
MIN

TYP MAX

UNITS

VOO=15V
MIN

TEST CONDITIONS

TYP MAX

tpLH

Propagation Delay,

70

210

35

105

25

75

ns

C L -50pF,

tpHL

CP to On

70

210

35

105

25

75

ns

R L =200kn

80

240

40

120

25

75

ns

Propagation Delay
tpHL

Input Transition

MR to On

tpZH

Output Enable

95

290

50

150

35

105

ns

tpZL

TIme

95

290

50

150

35

105

ns

tpHZ

Output Disable

95

290

50

150

35

105

ns

tpLZ

Time

95

290

50

150

35

105

ns

tTLH

Output Transition

65

160

40

90

15

35

ns

tTHL
twCP(L)

Time

65

160

40

90

15

35

ns

Minimum Clock Pulse Width

80

25

45

10

36

8

twMR(H)

Minimum M R Pulse Width

60

35

30

20

24

15

ns

tree
ts

MR Recovery TIme

2

ns

Set-Up TIme, On to CP

th

Hold-TIme, On to CP

ts

Set-Up TIme, EOn to CP

th
f MAX

Hold-TIme, EOn to CP
Maximum Clock Frequency

5

6

TImes ';;;20 ns
(R L = 1 kn to V SS )
(R L = 1 kn to V DD )
(R L = 1 kn to V SS )
(R L = 1 kn to V DD )

ns

15
45

1

5

1

ns

20

2

2
10

0

10

2

ns

100

50

40

20

30

15

ns

20

2

12

1

8

1

ns

4

9

10

16

12

19

MHz

(Note 3)
NOTES:
1. Additional DC Characteristics are listed in this section under 4000B Series CMOS Family Characteristics.
2. Propagation Delays and Output Transition Times are graphically described in this section under 4000B Series CMOS Family Characteristics.
3. For f MAX ' input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.
4. It Is recommended that input rise and fall times to the Clock Input be less than 15 /JS at VOO = 5 V, 4 /Js at VOO = 20 V, and 3 J.Ls at
VOO = 15 V.

7-130

FAIRCHILD CMOS • 4076B/74C173/54C173
SWITCHING WAVEFORMS

OUTPUT ENABLE TIME
(tPZH) AND OUTPUT DISABLE TIME (tPHZ)

OUTPUT ENABLE TIME
(tPZL) AND OUTPUT DISABLE TIME ItpLZI

SET·UP AND HOLD·TIMES
EON TOCP

MINIMUM PULSE WIDTHS FOR CP AND MR.
MR RECOVERY TIME. AND SET· UP AND HOLD·TIMES. ON TO CP

NOTE:
Set-up and Hold Times are shown as positive values but may be specified as negative values.

7·131

40778
QUAD EXCLUSIVE-NOR GATE
DESCRIPTION - The 4077B CMOS logic element provides the Exclusive-N
The 4077 B may be used interchangeably for the 4811.
LOGIC AND CONNECTION DIAGRAM
DIP (TOP VIEW)

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual I n-line Package.

x = AS

+ AS

DC CHARACTERISTICS: V DD as shown. VSS ~ 0 V (See Note 1)
LIMITS
SYMBOL

PARAMETER

V DD
MIN

Quiescent

XC

Power

IDO

Supply

XM

Current

~

5V

TYP

VDD ~ 10V
MAX

TYP

MIN

VDD - 15 V

MAX

5
7.5

TYP

MIN

2

4

15

30

0.25

0.5

7.5

TEMP

TEST CONDITIONS

MIN. 25°C

All inputs at 0 V
orVOO

UNITS

MAX
~A

1

15

MAX
MIN. 25°C

~A

30

MAX

AC CHARACTERISTICS: VOO as shown. VSS = 0 V. TA = 25"C (See Note 2)
LIMITS
SYMBOL

PARAMETER

VOO = 10V

VOO = 5V
MIN

TYP

MAX

MIN

VOO = 15V

TYP

MAX

MIN TYP

UNITS

TEST CONOITIONS

MAX

tpLH

Propagation Delay,

55

110

27

55

17

44

ns

C L = 50 pF.

tpHI

A or B to X

65

130

27

55

20

44

ns

RL = 200 kn

tTLH

Output Transition

53

100

20

50

15

35

ns

I nput Transition

tTHL

Time

53

100

20

50

15

35

ns

Times"; 20 ns

NOTES:
1. Additional DC Characteristics are listed in this section under 40008 Series CMOS Family Characteristics,
2. Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.

TYPICAL ELECTRICAL CHARACTERISTICS
PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

PROPAGATION DELAY
~
VERSUS TEMPERATURE
I 100 Cl-15pF

I ,.0r--------r-.1--,--,--~-,

>

~

90f--+-++-+-j--f--+-+-+--l

o
~

70

801--I--H~~lH-JOO

~ 60

~

-----

:o 50~~~~~~~~--+--+-I

g: 401-+--+-+-+--+--1-+--+-+--j

;3~

3°~~:tl~~:V:O~O~O~'~o..l~~;~

20 1-

VOD = 15 V -

10~~~~~~--+--+1--+-I

~60-40-20
TA -

0

20 40 60 80100120140

AMBIENT TEMPERATURE -

7-132

°C

TA = 25°C

~ 1201-+--I-+-It---+I---+V-,.....--j
o
<~-i/
~ 100r-~--r-~:~~~~~~~

~ 801-~--~~~~4-1--+--+--+~
:0

~

~

I

V

601-~--1-+--+---+--+--+---j

401-+__1-+_')00 ",'°,",_-

I 20
§: 00

'-:::~
I

20
CL -

40

60

I

80 100 120140160

LOAD CAPACITANCE -

pF

40788
8-INPUT NOR GATE
DESCRIPTION - This CMOS logic element provides the positive a·lnput
immunity and pattern insensitivity of output impedance.

CONNECTION DIAGRAM
DIP (TOP VIEW)

4078B LOGIC SYMBOL

14
13
12

3

11
Voo
VSS
NC

~
~
~

10

Pin 14
Pin 7
Pins 1. 6. 8

8

NOTE:

PIN NAMES
NOR Gate Inputs
10-17
Output (Active LOW)
Z

The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual I n-line Package.

~----~--------.
DC CHARACTERISTICS: VDD as shown. VSS = 0 V (See Note

i)

LIMITS
SYMBOL

PARAMETER

VDD
MIN

Quiescent
Power
IDD

Supply
Current

XC
XM

=5 V

TYP

VDD
MAX

MIN

= 10V

TYP

V DD

MAX

MIN

= 15 V

TYP

1

?

4

7.5

15

30.
1

0.25

0.5
15

7.5

TEMP

UNITS

TEST CONDITIONS

MAX

30

~A

~A

MIN. 25°C
MAX
MIN. 25°C
MAX

All inputs at 0 V
orVDD

AC CHARACTERISTICS: VOO as shown. VSS = 0 V. TA = 25"C (See Note 2)
LIMITS
SYMBOL

tpLH

PARAMETER

tTHL

UNITS

85

34

68

ns

85

35

68

ns

39

70

30

45

ns

I nput Transition

32

70

24

45

ns

Times.;; 20 ns

VOO=10V
MIN TYP MAX

108

200

46

129

200

50

Output Transition

76

135

nme

80

135

Propagation Oelay

tpHL
tTLH

VOO=15V
MIN TYP MAX

VOO =5V
MIN TYP MAX

TEST CONOITIONS
CL =50pF.
RL =200kn

NOTES:
1. Additional DC Characteristics are listed In this section under 40008 Series CMOS Family Characteristics.
2. Propagation Delays and Output Transition Ti{J1es are graphically described in this section under 40008 Series CMOS Family Characteristics.

7·133

FAIRCHILD CMOS. 4078B
TYPICAL ELECTRICAL CHARACTERISTICS

:r!
I

PROPAGATION DELAY
VERSUS TEMPERATURE

110
100

;

90

~

80

... V

C L = 15pF

I:

I pHL• VOO

Q.

I

~
~

30

~ 20

V

I pHL• VOO

TA -

TA

= 250C

200

>:5w 180
~ 160
Q 140

~

!i

120

~

100

II:
Q.

I

~

80
60

~

./
I pHL• VOO

= 5 V/

"

,,-

'" ~

"QQ

/' "1'-0
/""

'"

V

/

I pHL• VOO

T -f

~

\

= 10 V

i: 40

j.

,/"

CL -

40

60

l

= 10 V
= 15 V

~
I pLH • VOO

;;r-20

1 ,I

IpLH. VOO

~.lpHL' VOO

15 V

80 100 120 140 160

LOAD CAPACITANCE -

7-134

pF

= 10 ~,
= 10 V

t:::

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

220

...-"i;H. VOO

- --

Il- I-::i-l
:f:::

-60 -40 -20 0

:r!
I

V
= 5 V_

... V

.9- 10
INPUT FREQUENCY - Hz

/

,."..

V ...... 1---""

50 c-- I pLH• VOO
40

Ii!

= 5j. ..........

"

~ l - Ii-- I -

IpHL' VOO
I pLH • VOO

15 V-

= 15 V

20 40 60 80 100 120140

AMBIENT TEMPERATURE -

°C

40818
QUAD 2-INPUT AND GATE
DESCRIPTION - The 40818 is a positive logic Quad 2-lnput AND Gate. The outputs are fully buffered for highest noise immunity and
pattern insensitivity of output impedance.
LOGIC AND CONNECTION DIAGRAM
DIP (TOP VIEW)

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as the

Dual

OC CHARACTERISTICS: VOO as shown, VSS

=0 V (See Note

In~line

Package.

1)

LIMITS
SYMBOL

VOO

PARAMETER

MIN
Quiescent

XC

Power

100

=5 V

TYP

Supply

XM

Current

VOO
MAX

MIN

= 10V

TYP

VOO

MAX

MIN

= 15 V

TYP

UNITS

TEST CONDITIONS

TEMP

MAX

1

2

4

7.5

15

30

0.25
7.5

0.5
15

1
30

MIN,25°C

~A

All inputs at OV

MAX

orVDD

MIN,25°C

~A

MAX

AC CHARACTERISTICS: VOO as shown, VSS = 0 V, TA = 25°C (See Note 2)
LIMITS
PARAMETER

SYMBOL

VOO - 5 V
MIN TYP MAX

VOO -10V
MIN TYP MAX

VOO -15 V
MIN TYP MAX

UNITS

Propagation Delay

tpLH
tpHL

TEST CONOITIONS
C L -50pF,

55

95

23

50

17

95

25

50

19

40
40

ns

60

ns

RL =200kf!

tTLH

Output Transition

70

135

30

70

23

45

ns

Input Transiton

tTHL

Time

57

135

23

70

16

45

ns

Times .; 20 ns

NOTES:
1. Additional DC Characteristics are listed in this section under 40008 Series CMOS Family Characteristics.
2. Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.

TYPICAL ELECTRICAL CHARACTERISTICS

~1000
I

w 100

.."'"
..
.i5ffi
U

;::

POWER DISSIPATION
VERSUS FREQUENCY

1.0
10 - 1

~ 10-2

iii

~

10-3

III

II

w 10-4
~ 102

vcioIJ\I.~

!!~DD; 10V

~

I

:5w

~

C

~
~

!I?-~

~ voo~JUII

z

Vno = 5 V

0

~

"~

hoo~1civll_111 1.11
.111
103

0

iE

CL=60pF1IIII cL
=1. P'

104

10·

40

>-

I,

~

50 CL= 15 pF

~

~

I'

a:

.

1IIIv~~ ~1\.lv

T±~2.oC

10

PROPAGATION DELAY
VERSUS TEMPERATURE

10·

INPUT FREQUENCY - Hz

107

~

>- 100

~
C

-r

z

./

0

20~ f- f- V~D= 10V

~

e-~

v~·IV

10 1 ..0
-60

-20

20

60

100

f-

140

TA - AMBIENT TEMPERATURE - °C

7-135

,¥J~Qt-r-

I

f - r-Jool ~ .Iv

30

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE
140
TA = 26°C
I
l/
120

~~~

80
60

"~

40

iE

20

0

~~
tp\.,\'\' tp\1L

F-t.i:'tI. j"tll

0
0 20 40 60

VDok ~

VDrY~ r---

80 100120140 160

CL - LOAD CAPACITANCE - pF

40858
DUAL 2-WIDE 2-INPUT AND-DR-INVERT
DESCRIPTION - The 40858 is a Dual 2-Wide 2-lnput AND-OR-Invert (A
used as either an Expander Input or an Inhibit Input by connecting it to
Output (F) LOW independent of the other four inputs (10-13). The Outputs

ditional input (l4A or 148 ) which ,can be
OS output, A HIGH on this Input (14) forces the
are fully buffered for highest noise immunity and

pattern insensitivity of output impedance.

CONNECTION DIAGRAM
DIP (TOP VI EW)

PIN NAMES
IOA- 14A.108- 148

Gate Inputs

FA. F8

Outputs (Active LOW)
14

LOGIC DIAGRAM

13

12
11

Voo

~

Pin 14

VSS

=

Pin 7

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual In-line Package

DC CHARACTERISTICS: VDD as shown. VSS = 0 V (See Note 1)
LIMITS
SYMBOL

PARAMETER

MIN
Quiescent

XC

Power
IDD

Supply

XM

Current

V DD - 10 V

VDD = 5 V '"
TYP

MAX

MIN

TYP

VDD - 15 V

MAX

MIN

TYP

UNITS

1

2

4

7.5

15

0.25
7.5

0.5
15

30
1
30

AC CHARACTERISTICS: VDD as shown. V SS

=0

V. T A

= 25° C

TEMP

TEST CONDITIONS

MAX
~A
~A

MIN. 25°C
MAX

All inputs at 0 V
orV DD

MIN,25°C
MAX

(See Note 2)
LIMITS

PARAMETER

SYM80L

V DD =5 V
MIN

TYP MAX

VOO=10V
MIN TYP MAX

VOO

~

MIN TYP

15 V

UNITS

TEST CONDITIONS

MAX

tpLH

Propagation Delay,

56

115

25

55

17

44

ns

tpHL

Any I to

F

74

135

30

65

20

52

ns

C L = 50 pF.
RL =200kn

tTLH

Output Transition

45

100

22

50

15

35

ns

I nput Transition

tTHL

Time

45

100

22

50

15

35

ns

Times" 20 ns

NOTES:
1. Additional DC· Characteristics are listed in this section under 40008 Series CMOS Family Characteristics.
2. Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.

7-136

FAIRCHILD CMOS. 40858
TYPICAL ELECTRICAL CHARACTERISTICS

~1000
I

POWER DISSIPATION
VERSUS FREQUENCY

T~llI2JO~

w 100
CI

~

~
a:
w

...

10
1.0

VI

15
a:

10-2
10- 3

,

YI?I? ~ 1 ~Y.-f::
VDD = 10·V",

'
~

Z

o
;::

~
o
a:

..

Y0 191=1

..'

102

5
ii:

5V

1

104

105

~",.,j
20

/"
,/

10

~

CL - 15 pF
CL = 50 pF······
103

30

...

,

.... ~ ..~V

.;,- ....
~:
.... .... 1/

CL = 15 pF

~

.~ ....

~

40

w
C

..' .~
..' . .···V

~ 10- 4 V
~

5

.. .
1-:0
.... .';'..,../'
.• r;:::'
...

IIII I

~ 10- 1

i=
~
iii

PROPAGATION DELAY
VERSUS TEMEPRATURE

...I
o

106

I-

.:

INPUT FREQUENCY - Hz

-::::

o

-60

-

-20

5

100

w
80

1--+-+-----".

~

60

I--:J,--=+-

o

CI

~
oa:

...
...I
~

.:

O~~~~~~~~~~__~~

o

W

~

~

~

1001W1~1~

CL - LOAD CAPACITANCE - pF

7-137

~

~

'1100

!-- 'IIDO=I'5~
20

60

100

140

TA - AMBIENT TEMPERATURE - °C

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

C
Z

V

Y V

4086B
4-WIDE 2-INPUT AND-DR-INVERT GATE
D_'~ - The 48i88 is a 4·Wide 2·lnput AND·OR·lnvert (AO!) Gate with two additional inputs (IS .ndlg) ~hich can be used as
eLthar el<\liander irtputs 9/' inl'!ft.it inputs by connecting them to any standard CMOS output, A HIGH on IS or a LOW on Ig forces the Output
(F) LOW i

~

Q

...

Z
0

...

C
c:I

~ 10- 1

0

S

c:I

w

IJ
C

j::

a:
w

III

...
I
I'"

.-

~
Ie,

°10-3

a:
w

.-

3:10- 4

i

102

106
INPUT FREQUENCY -

!!
I

>

S
~

z

o

~
2:

oa:

...

E

107

,

E

'01

~,.~

'0100

80

.....

/

/

.....V
...... /

60

40

20

o

----

"O~

----

"OO~

I-"

-60
-20
20
60
100
140
-40
0
40
80
120
TA - AMBIENT TEMPERATURE _·C

Hz

PROPAGATION OELAY
VERSUS
POWER SUPPLY VOLTAGE
160r---r-~r---~--~--.---'

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

!!I

180

;
w

150

~

120

c:I

90

TAI=

140~--r-~\---+---+---+-~
120r---~r-~~

25~C

Q

100r---f--'1r-''''

,. f1 'o1

2:
o
g:

60r---r---f-

-

60

I
I'"
~

20r---r---+---+---+---~~~

Ie
,

0~0--~---=5--~--~1~0~~---1~5

E

........V

~

V 'oI~""'"

~

801---1--

I'"

~
Ie

CL=15pF

2:

a:

~

~ 10- 2

100

30
0
0

20

"OO=~~-

~

40

60

"00=15"

>-

80 100 120140 1·60

CL - LOAD CAPACITANCE - pF

VDD - POWER SUPPLY VOLTAGE - V

7-139

40938
QUAD 2-INPUT NAND SCHMITT TRIGGER

GENERAL DESCRIPTION - The 40938 is a Quad 2-lnput NAND Schmitt Trigger offering positive and negative threshold
voltages, VT+ and VT- which show very low variation with temperature (typically 0.0005 Vloe at VDD = 10 V) and typical
hysteresis, VT+ to VT- 2: 0.33 VDD. Outputs are fully buffered for highest noise immunity.

LOGIC AND CONNECTION
DIAGRAM DIP (TOP VIEW)
VDD

NOTE:

The F latpak version has the same
pinouts (Connection Diagram) as the
Dual I "",line Package.

DC CHARACTERISTICS: V DD as shown, VSS = 0 V (Note 1)
LIMITS
SYMBOL

PARAMETER

V DD = 5 V
MIN

V DD =10V

TYP MAX MIN

V DD =15V

TYP MAX MIN

UNITS

TEMP

TEST CONDITIONS

TYP MAX

Positive·Going
V T+

Threshold

2.9

3.6

4.3

6.0

6.8

8.6

9

10

12.9

V

ALL

V IN = VSS to V DD

0.7

1.4

1.9

1.4

3.2

4.0

2.1

5

6

V

ALL

V IN = V DD to VSS

1.0

2.2

3.6

2.0

3.6

7.2

3

5

8

V

ALL

Voltage
Negative·Going
VT _

Threshold
Voltage

Guaranteed

VT+to
Hysteresis
VT _
Quiescent

Power
100

Hysteresis =
V T + Minus V T _

Supply
Current

XC
XM

1
7.5
0.25
7.5

2

4

15

30

0.6
15

1
30

JJA
JJA

MIN,25°C
MAX
MIN,25°C
MAX

NOTES:

1. Additional de characteristics are listed in this section under Fairchild 4000B series CMOS family characteristics.

7·140

All Inputs
at OV or
V DD ·

FAIRCHILD CMOS • 40938

GUARANTEED TRIGGER THRESHOLD VERSUS VDD

12

GUARANTEED HYSTERESIS VERSUS VDD

.A' '"I,

> 10~+--t~~+--t~~+--+--~~

.! Br-+--r~r-+--r~~~~~~~
~ 6r-+--r~~~~~~~~~~~

A' 'I 'I

I

'I
ill, fl I II, Il.
rr.
v,.
"i,
ill, Ut V
~I II II, ~
~ rll
A II, I I, I.JA II 'L ......
r17 r//, rll, UI
'/L ~ k '1: '.jl II, 'I, ill, UI
lr1'i rll. 'I I, III ./; II, ii, r/L rL.t
II. II,
1,4; rli 'II

-

o

10

5

i~

4

"~~~Tfl
10

15

15

VOD-POWER SUPPLY VOLTAGE-V

VOD-POWER SUPPLY YOLTAGE-V

INPUT AND OUTPUT CHARACTERISTICS

VDD
VO H J l

VIHIMINI-VT+IMINI-T----- VNMH - - -

VOL
VIL(MAXI -VT-(MAXI-VNML _ _ _ _ _

LOAD

DRIVER

1___ ~..,..,..,..,.."..,..,..~..,..,..,..,..,..,..

LOIlIC "0" OUTPUT
REGION

VNML - VIH(MIN) -VOL'" VIH(MIN) - VT

+ (MIN)

VNMH - VOH - VIL(MAX) '" VOO - VIL(MAX) - VOO -

VT - (MAX)

AC TEST CIRCUITS AND SWITCHING TIME WAVEFORMS

VDD------i-W-------~
V DD

V ,N

VIN~VOUT
T

OV

50pF

VDD

----kl

V OUT

OV------~_r~-----~--'

AC CHARACTERISTICS: VDD as shown, VSS - 0 V, T A - 25°C
LIMITS
SYMBOL

PARAMETER

VDD-10V
MIN

TYP

MAX

UNITS

VDD -15V
MIN

TYP

TEST CONDITIONS
See Note 2

MAX

60

110

25

60

20

48

ns

CL-50pF,

tpHL

60

110

25

60

20

48

ns

RL - 200 kn

tTLH

60

135

30

70

20

45

ns

I nput Transition

60

135

30

70

20

45

ns

Times';; 20 ns

tPLH

tTHL

Propagation Delay

VDD -5 V
MIN TYP MAX

Output Transition Time

NOTE:

Propagation Delays and Output Transitions Times are Grahicallv Described in Section Under Series CMOS Family Characteristics.

7-141

-----------

•

41048
QUAD LOW VOLTAGE TO HIGH VOLTAGE
TRANSLATOR WITH 3-STATE OUTPUTS

DESCRIPTION - The 41048 Quad Low Voltage to High Voltage Translator with 3-State Outputs
provides the capability of interfacing low voltage circuits to high voltage circuits, such 'as low voltage
CMOS and TTL to high voltage CMOS. It has four Oata Inputs (lO-Ia!,!" active HIGH Output Enable
input (EO), four Oata Outputs (ZJI:~ and their Complements (ZO-Z3)' With the Output Enable
input HIGH, the Outputs (ZO-Z3, ZO-Z3) are in the low impedance "ON" state, either HIGH or LOW
as detenmined by the Oata Inputs; with the Output Enable input LOW, the Outputs are in the high
impedance "OFF" state. The voltage level on the Output Enable input may swing between VOO I
and VSS.

CONNECTION DIAGRAM
DIP (TOP VIEW)

The device uses a common negative supply (VSS) and separate positive supplies for inputs (VOOI) and
outputs (VOOO)' VOOI must always be less than or equal to VOOO, even during power turn-on and
turn-off. For the allowable operating range of VOOI and VOOO see Figure 1. Each input protection
circuit is terminated between VOOO and VSS. This allows the input signals to be driven from any
potential between VOOO and VSS, without regard to current limiting. When driving from potentials
greater than VOOO or less than VSS, the current at each input must be limited to 10 rnA.
When used in a bus organizad systam, all 41048 devices on the same bus line should be connected to
the same VOOO and VSS supplies. Otherwise, parasitic diodes from the output to VOOO and VSS can
become forward biased, even while the device is in the OFF state, causing catastrophic failure if the
current is not limited to 10 rnA.

•
•
•

3-STATE FULLY BUFFERED OUTPUTS
OUTPUT ENABLE INPUT (ACTIVE HIGH)
DUAL POWER SUPPLY

PIN NAMES

FUNCTION
Oata Inputs
Output Enable Input
Oata Outputs
Complimentary Oata Outputs

10-13

EO

Zo-Z3
Zo-Z 3

NOTE:

The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual In·line Package.

LOGIC SYMBOL

@

®
EO

®

0

®

0)

®

Vooo ~ Pin 1
VOOI = Pin 16
= Pin 8
Vss

0

= Pin Number

7-142

®

®

@)

FAIRCHILD CMOS • 41048
DC CHARACTERISTICS: VOOO = VOOI as shown, \ISS = 0 V
LIMITS
SYMBOL

VIH
VIL

VOH

PARAMETER

Input HIGH Voltage
Input LOW Voltage
Output HIGH
Voltage

VOOO/I =5 V
MIN TYP MAX
3.5
Note
2

1
1.5

7
Note
2

Note
1
3

VOOO/I = 15 V
MIN TYP MAX
11
Note
2

4.95

9.95

14.95

4.95
4.5

9.95
9.0

14.95
13.5

Output LOW
VOL

Note

VOOO/I = 10V
MIN TYP MAX

Voltage

1
4

0.05
0.05

0.5

-1.0

1.5
0.3

XM

V

All

V

V

0.05
0,05

I nput Current

TEMP

All
MIN,25°C

0.05
0.0.5

XC
liN

Note

UNITS

V

MAX
All
MIN,25°C
MAX
All

IJ.A

MIN,25°C

1.0

MAX

0.1

MIN,2SoC

1.0

IJ.A

MAX

TEST CONDITIONS

Guaranteed Input
HIGH Voltage
Guaranteed Input
LOW Voltage
10H <1 IJ.A Note 3
101. ~______~

@IT"I>-

e

1

~~,B~----------------------------------J

0) ~IL~T-------------------------------------~
VDD

~

PIN 16

VSS~PIN8

o

~

PIN NUMBER

DC CHARACTERISTICS: V DO

~

5 V, VSS

~

0 V (Note 11
LIMITS

SYMBOL

PARAMETER
MIN
Input HIGH Voltage

TYP

3.5

Input LOW Voltage

UNITS

TEMP

V

All

Guaranteed Input HIGH Voltage

V

All

Guaranteed Input LOW Voltage

25°C

TEST CONOITIONS

MAX

1.5
XC

Output HIGH Voltage

or

4.1

4.57

V

4.24

V

3.60

4.22

IOH<1J.1A

Inputs at 0 V or V DO
per the Truth Table

XM

XC
.2.80

~~
IOH=10 rnA
25°C

4.16
4.12
4.05
4.24
3.90

XM
3.40

V

IOH-5 rnA

4.22

IOH 10 rnA

4.16

~~
IOH=20 rnA

4.12

IOH~25

4.05
0.05
Output LOW Voltage

IOH-15 rnA
IOW 20rnA
IOH 25 rnA

0.05

V

0.5

V

rnA

IOL < 'I J.lA, Inputs at 0 V or V DO
per the Truth Table
All

IOL < 1 J.lA, Inputs at 1.5 or 3.5 V

1
Output LOW Current

0.8

rnA

0.4

MAX
20

Qu iescent Power

Supply Current

XC
XM

VOUT=

150

5
150

7-150

0.4 V

Inputs at 0 V or VOO
per the Truth Table

MIN,25°C
J.lA

MAX
MIN,25°C
MAX

All Inputs at 0 V or VOO and
all Outputs Open

FAIRCHILD CMOS • 45118
DC CHARACTERISTICS: V DD = 10 V, VSS = 0 V (Note 11
LIMITS
SYMBOL

PARAMETER
MIN

V IH

Input HIGH Voltage

V IL

Input LOW Voltage

UNITS

TEMP

V

All

Guaranteed Input HIGH Voltage

V

All

Guaranteed Input LOW Voltage

9.58

V

25°C

9.26

V

TYP

7

3
XC

V OH

Output HIGH Voltage

or

TEST CONDITIONS

MAX

IOH< 1 /lA
9.1

Inputs at 0 V or V DD
per the Truth Table

XM
8.75
XC

IOH=10 mA
25°C

9.17
8.10

IOH=5 mA

9.21
9.14
9.10

IOH=25mA
V

9.26
9.00
XM

IOH-5 mA

9.21

IOH=10 mA
25°C

9.17
8.60

9.14

IOH=25 mA
MIN,25°C

0.05
Output LOW Voltage

0.05

V

1

V

Output LOW Current

2

mA

IDD

Supply Current

40
300

Quiescent Power

XM

All
25°C
MAX

1.2
XC

MAX

IOL<1/lA,lnputsatOVorV DD
per the Truth Table
IOL < 1 /lA, Inputs at 3 or 7 V

MIN

2.6
IOL

IOH=15 mA
IOH=20 mA

9.10

VOL

IOH=15 mA
IOH=20 mA

10
300

MIN,25°C
/lA

MAX

VOUT=
0.5 V

Inputs at 0 V or V DD
per the Truth Table

All Inputs at 0 V or V DD
and all Outputs Open

MIN,25°C
MAX

•

7·151

FAIRCHILD CMOS • 45118
DC CHARACTERISTICS: V DD = 15 V, VSS = 0 V (Note 1)
LIMITS
SYMBOL

PARAMETER
MIN

V IH
V IL

TYP

11

Input HIGH Voltage

TEST CONDITIONS

UNITS

TEMP

V

All

Guaranteed Input HIGH Voltage

V

All

Guaranteed Input LOW Voltage

MAX

Input LOW Voltage

4
XC

V OH

Output HIGH Voltage

or

IOH < 11lA
14.10

14.59

25°C

Inputs at 0 V or V DO
per the Truth Table

XM
13.75
XC

14.27

IOH=5 rnA

14.23

IOH-10 rnA
25°C

14.20
13.10

IOH=15 mA

14.17

IOW20 mA

14.13

IOH=25 mA
V

14.27
14.00
XM

IOH=5 mA

rOH =10 mA

14.23
25°C

14.20
13.60

IOH-15 rnA

14.17

IOH=20 mA

14.13

IOH=25 rnA
0.05

VOL

liN

Output LOW Voltage

Input Current

MIN,25°C

0.05

V

MAX

2

V

All

XC

1

XM

1

IOL <"1 1lA. Inputs at 0 V or V OD
per the Logic Function or Truth Table
IOL<1 JiA, 'Inputsat40r 11 V
Lead under test at 0 V or VOO

All
IlA

All other Inputs simultaneously at

OVorV DD
IOL

IDD

7.5

Output LOW Current

mA

4.5

MIN,25°C

V OUT -

MAX

1.5V

80

MIN,25°C

Qu iescent Power

XC

600

MAX

Supply Current

XM

20

IlA

Inputs at 0 V or V DD
per the Truth Table

All Inputs at 0 V or V OD and all
Outputs Open

MIN,2SoC

600

MAX

AC CHARACTERISTICS AND SET·UP REQUIREMENTS: V DD as shown, VSS = 0 V, T A = 25°C (see Note 2)
LIMITS
SYMBOL

PARAMETER

V DO = 5 V
MIN

tpLH

Propagation Delay, AN to a-g

tpHL
tpLH

Propagation Delay, I L T to a·g

tpHL
tpLH

Propagation Delay, I B to a·g

tpHL
tpLH

Propagation Delay, E L to a-g

V DD =15V

VDD=10V

TYP

MAX

MIN

TYP

MAX

MIN

UNITS

TYP

MAX

212

480

90

190

68

152

ns

238

480

88

190

60

152

ns

82

180

38

80

30

64

ns

85

180

34

80

24

64

ns

RL = 200 kU

147

330

60

135

42

108

ns

Input Transition Times

164

330

65

135

46

108

ns

.. 20 ns

230

550

90

210

63

168

ns
ns

275

550

98

210

66

168

tTLH

Output Transition

25

55

18

40

16

40

ns

tTHL
tw EL

Time

75

135

26

75

17

45

ns

EL Minimum Pulse Width

85

34

35

14

28

10

ns

ts

Set-Up Time,AN to EL

55

20

25

7

20

4

ns

th

Hold-Time, AN to IT

55

19

25

6

20

4

ns

tpHL

TEST CONOITIONS

CL=50pF,

NOTES:
1. Additional de characteristics are listed in this section under 40008 Series CMOS FamilY Characteristics.
2. Propagation Delays and Output Transition Times are graphically described in this section under 4000B Series CMOS Family Characteristics.

7-152

FAIRCHILD CMOS • 45118
AC WAVEFORMS

SET-UP AND HOLD-TIMES, AN TO
PULSE WIDTH

IT AND MINIMUM IT

STABLE

...--th-""

50%

NOTE: Set-up and hold-times are shown as
but may be specified as negative values

positive values

•

7-153

FAIRCHILD CMOS • 45118
TYPICAL ELECTRICAL CHARACTERISTICS

PROPAGATION DELAY. AN TO
OUTPUT VERSUS
LOAD CAPACITANCE

I
too 15

TA "" 25°C

~

300

"~ ~

-

JPHL

250

~~

200

~

V

a: 0 150

"0

'e-

~=,
.. e-

....
""

I50

.. S

40

~I~

30

.. eo"
a: 0

~

I

60

-20

.- l.-- ~

I
.-"

60

I tP~L' V?o 1

'5

60

1'-

100

1

100

==

140

120 I--I--

o

-60

25

25

"

20

ii

15

35
30

f-- f-

o

20
TA

20

10

60

100

140

~ -20

/

V,
/ I.

voo -

-40

~

~ -50

3 V

../'

o
I

.9 -60
-70
VOO-3V

If

Voo =svj VI
VDO-2V

-VODI-1OV

I-VDOr1SV

VDO-1V

Voo

VOH - OUTPUT HIGH VOLTAGE - VOLTS
(Voo '= POWER SUPPLY VOLTAGE)

7-154

o

60

20

5 V

tTL'1'v~

r-

10 V

tTHL, Voo

!-t-::::t:

tTLH. Voo

TA

e-

":r:

,..-

tTlH, Voo - 10 V
- 15 V

r

1, -10

%

--

~

f- ..--

t--- I-- '--tTHl, Voo

TYPICAL OUTPUT DRIVE
CHARACTERISTICS

a-3D

I - ,--

15 V

AMBIENT TEMPERATURE -- °C

a:
a:

I- I--"

15

I-

-60

140

140

100

tTHl, Voo

20

TA - AMBIENT TEMPERATURE - °C

60

40

...... V

voo

20

J/ V

lS'V/

Cl- 15 pF

:;
:;

'w
}

tPl~, voo ~

--

50

30

VOO=10V

po

'45

.... VVOO~5V

-- -

tPHL Voo =!'5

-20

~

-+-r

OUTPUT TRANSITION TIME
VERSUS TEMPERATURE

V

..J--1

40

-

r---..

TA -- AMBIENT TEMPERATURE - °C

°C

35

Z

I--

40

15 V-

V

""-;PLH, vool ~ 5 ~

tPLH, Voo - 10 ~

60

'"

".
liJ

-

~

,..- V

tPHL, Voo = 10 V

80

i!:
"ii:

10
tPLH, Voo = 15 V

20

15

100

MINIMUM IT PULSE WIDTH
VERSUS TEMPERATURE

w

:.-r;PLH. Voo "" 5 V

tPLH, Voo '" 10 ~\.

20

20

vim ~

g

I .... '::: ,..-

~I~

50

20

060

tPHl.

CL=15 pF

r- -tPHI,volo~lO~'

10

tPLH, VOO

I'

45

....- :.-

0...

tPHL,VOD~

TA'" AMBIENT TEMPERATURE

PROPAGATION DELAY, ILT to
CL= 15 pF

....
""g
..j.

50

OUTPU~VERSUSTEMPERATURE
100
90

J

j

Cl - LOAD CAPACITANCE - pF

,:

~ ~ 140
>=,
=,

TB

PROPAGATION DELAY.
to
OUTPUT. VERSUS TEMPERATURE

PROPAGATION DELAY. AN TO
OUTPUT VERSUS TEMPERATURE

350

20

/:

15 V
60

100

AMBIENT TEMPERATURE

ce

140

FAIRCHILD CMOS. 4511 B
TYPICAL APPLICATIONS
LIGHT EMITTING DIODE (LED) READOUT
VOO

VOO

COMMON
CATHODE LED

INCANDESCENT READOUT

FLUORESCENT READOUT

Voo

VOO

DIRECT
(LOW BRIGHTNESS)

Vss OR APPROPRIATE
VOLTAGE BELOW VSS

.. A filament pre-warm reSIstor IS recommended to reduce filament thermal
shock and Increase the Edfectlve cold resistance of the f.lament

GAS DISCHARGE READOUT
VOO

LIQUID CRYSTAL (LCD) READOUT>'
VOO

APPROPRIATE
VOLTAGE

EXCITATION
(SQUARE WAVE.
VSS TO VOO)

HDirect de dnve of LCD not recommended for life of LCD readouts

7-155

•

45128
8-INPUT MULTIPLEXER WITH 3-STATE OUTPUT

DESCRIPTION - The 4512B is an 8-lnput Multiplexer with Active LOW logic and output enables (E,
EO). One of eight binary inputs is sel~ted by Select Inputs SO, S1 and S2 and is routed to the output
F. A HIGH on the Output Enable (EO) causes the F output to assume a high impedance or "OFF"

LOGIC SYMBOL

state, regardless of other input conditions. This allows the output to interface directly with bus
oriented systems (3-state). When the active LOW Enable (E:) is HIGH, it forces the output LOW
provided the Output Enable (EO) is LOW. By proper manipulation of the inputs, the 4512B can
provide any logic functions of four variables. The 4512B cannot be used to multiplex analog signals.
•
•
•
•

SELECTS ONE-OF-EIGHT DATA SOURCES
PERFORMS PARALLEL-TO-SERIAL CONVERSION
3-STATE OUTPUTS WITH ACTIVE LOW OUTPUT ENABLE
ACTIVE LOW LOGIC ENABLE

15 10

11

So

12

S,

1

2

3

4

5

6

7

9

45128

PIN NAMES
13

Select Inputs
Output Enable (Active LOW)
Enable (Active LOW)
Multiplexer Inputs

SO,S1,S2

EO

14

Multiplexer Output
Voo = Pin 16

TRUTH TABLE

VSS = Pin 8

OUTPUT

INPUTS
EO

E

S2

S1

So

10

11

12

13

14

15

16

17

F

L

H

X

X

X

X

X

X

X

X

X

X

X

L

L

L

L

L

L

L

X

X

X

X

X

X

X

L
H

CONNECTION DIAGRAM
DIP (TOP VIEW)

L

L

L

L

L

H

X

X

X

X

X

X

X

L

L

L

L

H

X

L

X

X

X

X

X

X

L

L

L

L

L

H

X

H

X

X

X

X

X

X

H

L

L

L

H

L

X

X

L

X

X

X

X

X

L

L

L

L

H

L

X

X

H

X

X

X

X

X

H

L

L

L

H

H

X

X

X

L

X

X

X

X

L

15

L

L

L

H

H

X

X

X

H

X

X

X

X

H

14

L

L

H

L

L

X

X

X

X

L

X

X

X

L

L

L

H

L

L

X

X

X

X

H

X

X

X

H

L

L

H

L

H

X

X

X

X

X

L

X

X

L

L

L

H

L

H

X

X

X

X

X

H

X

X

H

L

L

H

H

L

X

X

X

X

X

X

L

X

L

L

L

H

H

L

X

X

X

X

X

X

H

X

H

L

L

H

H

H

X

X

X

X

X

X

X

L

L

L

L

H

H

H

X

X

X

X

X

X

X

H

H

H

X

X

X

y

X

X

X

X

X

X

X

Z

X
L

LOW Level

H

X

HIGH Level
Don't Care

Z

High Impedance State

16

13

12
11

10

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual In-line Package.

7-156

FAIRCHILD CMOS • 4512B
LOGIC DIAGRAM

(i)

0

0

0)

® ® 0

CD

•
Voo

= Pin

16

VSS

= Pin

8

o

'"' Pin Number

7-157

FAIRCHILD CMOS. 45128
DC CHARACTERISTICS: VOO as shown, VSS = 0 V (See Note 1I
LIMITS
SYMBOL

IOZH

PARAMETER
Output OFF
Current HIGH

IOZL

Output OFF
Current LOW

VDD = 5 V
MIN TYP MAX

VDD = 15 V
MIN TYP MAX

VDD = 10 V
MIN TYP MAX

1.6
12

XC
XM

0.4
12

XC

- 1.6
-12
- 0.4
-12

XM

IDD

Quiescent
Power
Supply
Current

TEST CONDTIONS

UNITS

TEMP

/loA

MIN,25'C
MAX
MIN,25'C
MAX

/loA

MIN,25'C
MAX
MIN,25'C
MAX

XC

20
150

40
300

80
600

~

XM

5
150

10
300

20
600

/loA

MIN,25'C
MAX
MIN,25'C
MAX

Output~turned to

VDD' EO

=

VDD

Output returned to
VSS'

EO = VDD

All inputs at 0 V
orVoo

AC CHARACTERISTICS: VOO as shown, VSS = 0 V, TA = 25'C (See Note 21
LIMITS
SYMBOL

PARAMETER

VOO =5 V
MIN TYP MAX
150 300

VOO = 10 V
MIN TYP MAX
75
150

VOO= 15 V
MIN TYP MAX
52
120

tPLH

Propagation Delay,

tpHL

Data to Output

150

300

75

150

52

tpLH

Propagation Delay,

175

350

85

170

tpHL

Select to Output

175

350

85

170

UNITS
ns

TEST CONDITIONS
C L = 50 pF,
RL = 200 kn

120

ns

60

136

ns

I nput Transition

65

136

ns

Times < 20 ns

ns

tpLH

Propagation Delay,

90

175

45

90

30

72

tpHL

E to

90

175

45

90

32

72

ns

tpZH

Output Enable

33

85

20

45

18

36

ns

(R L = 1 k!1 to VSSI

tpZL

Time

30

85

22

45

20

36

ns

(R L = 1 kn to VOOI

tpHZ

Output Disable

39

100

20

50

15

40

ns

(R L = 1 k!1 to VSSI

tpLZ

Time

40

100

20

50

15

40

ns

(R L = 1 k!1 to VOOI

tTLH

Output Transition

90

200

40

100

33

65

ns

tTHL

Time

100

200

40

100

30

65

ns

Output

NOTES:
1. Additional DC Characteristics are listed in this section under 40008 Series CMOS Family Characterisitcs.
2. Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.

7-158

FAIRCHILD CMOS. 4512B
TYPICAL ELECTRICAL CHARACTERISTICS

~
I

w

TYPICAL POWER DISSIPATION
VERSUS FREQUENCY
1000

~~ I~ 2~oblll

o~
~

II:

w

10
1.0

~

10- 1

i-:::k:'

j:

iii
~

~
10- 3

II:

~

o

102

~ 10-4

II.

"

~~

o

is

~

"
li ~~ j{~

~ ~

~

g: I- 120·1-?~~"""'F---tPLH. tpHL VDD= 10 V
I ti
I I I I
~~

B-~
i

CL - 15 pF
CL= 50 p F - 104

106

105

INPUT FREQUENCY -

;'w

200

5 160 f--t-:...-'I-+----1
::

V55 ---+"'-I-+-+-1~--{

~
~

:°5 0 5,

S2

I l~

c

5,
A

-----------1 '0

=====1"

52

'2

---------1 '3

----------i '4

FI-+-+-+.J

---------1 '5

Fig. 1

16

INPUT 30
INPUT 31

17

A3~

A4 ~r ~050 5, 52
32-INPUT MUL

TIPLEX~R, fl-lr-t :"'+-4-4
....

THE INPUT IS SELECTED
BY 5-BIT ADDRESS A4 - AO
AND PRESENTED AT
THE OUTPUT

Fig. 2

7-160

45148
1-0f-16 DECODER/DEMULTIPLEXER WITH I

DESCRIPTION - The 45148 is a 1-of-16 Decoder/Demultiplexer with four binary weighted Address
Inputs (AO-A3), a Latch Enable Input (EL), an active LOW Enable Input (E) and sixteen mutually
exclusive active HIGH Outputs (00-015).

CONNECTION DIAGRAM
DIP (TOP VIEW)

When the Latch Enable Input (EL) is HIGH, the selected Output (00-015) is determined by the data
on the Address Inputs (AO-A3). When the Latch Enable Input (EL) goes LOW, the last data present
at the Address inputs (AO-A3) is stored in the latches and the Outputs (00-015) remain stable. When
the Enable Input (E} is LOW, the selected Output (00-015), determined by the contents of the latch,
is HIGH. When the Enable Input (E) is HIGH, all Outputs (00-015) are LOW. The Enable Input (E)
does not affect the state of the latch.

24
23
22

With the Latch Enable Input (Ell HIGH, 16-channel demultiplexing results when data is applied to
the Enable Input (E) and the desired output is selected by AO-A3. The selected output (00-015) will
follow as the inverse of the data. All unselected outputs (00-015) are LOW.

21

LATCH ENABLE INPUT (ACTIVE HIGH)
ENABLE INPUT (ACTIVE LOW)
SELECTED BUFFERED OUTPUTS
(ACTIVE HIGH) COMPLEMENT OF THE INPUT
PIN NAMES
Address Inputs
AO-A3
E
Enable Input (Active LOW)
Latch Enable Input
Outputs
LOGIC SYMBOL
•
•
•

23

1

2

3

21

20
19

18
17

16
15

10

22

11

14

12

13

Voo = Pin 24

45148

VSS = Pin 12

NOTE:

The F latpak version has the same
pinouts (Connection Diagram) as the
Dual In-line Package.
11

9

10

8

7

6

5

4

18

17

20

19 14

13

16

15

TRUTH TABLE
OUTPUTS

INPUTS
E

AO

A1

A2

A3

00

01

02

03

04

05

06

{)7

Os

09

010

011

012

013

014

015

H

X

X

X

X

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

H

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

H

L

L

L

L

H

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

H

L

L

L

L

H

L

L

L

L

L

L

L

L

L

L

L

L

L

L

H

H

L

L

L

L

L

H

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

H

L

L

L

L

L

H

L

L

L

L

L

L

L

L

L

L

L

L

H

L

H

L

L

L

L

L

L

H

L

L

L

L

L

L

L

L

L

L

L

L

H

H

L

L

L

L

L

L

L

H

L

L

L

L

L

L

L

L

L

L

H

H

H

L

L

L

L

L

L

L

L

H

L

L

L

L

L

L

L

L

L

L

L

L

H

L

L

L

L

L

L

L

L

H

L

L

L

L

L

L

L

L

H

L

L

H

L

L

L

L

L

L

L

L

L

H

L

L

L

L

L

L

L

L

H

L

H

L

L

L

L

L

L

L

L

L

L

H

L

L

L

L

L

L

H

H

L

H

L

L

L

L

L

L

L

L

L

L

L

H

L

L

L

L

L

L

L

H

H

L

L

L

L

L

L

L

L

L

L

L

L

H

L

L

L
L

L

H

L

H

H

L

L

L

L

L

L

L

L

L

L

L

L

L

H

L

L

L

H

H

H

L

L

L

L

L

L

L

L

L

L

L

L

L

L

H

L

L

H

H

H

H

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

H

H

= HIGH Level

L = LOW Level
EL ~ HIGH

7-161

•

FAIRCHILD CMOS • 45148
LOGIC DIAGRAM

@ @ @) @ @

®

@ @

0 CD ® 0 ®

@)

015

010

09

07

02

014

013

012

011

Os

06

=

Pin 24

VSS

=

Pin 12

0

= Pin Number

VDD

7-162

05

04

03

CD @
01

00

FAIRCHILD CMOS • 45148
DC CHARACTERISTICS: VOD as shown, VSS ~ 0 V (See Note 11
LIMITS
SYMBOL

VDD ~ 5 V

PARAMETER
MIN
Quiescent

Power
100

Supply

Current

TYP

XC
XM

VDD

MAX

MIN

~

VDD~15V

10 V

TYP

MAX

MIN

TYP

UNITS

TEMP

TEST CONDITIONS

MAX

20

40

80

150

300

600

5

10

20

150

300

600

MIN,25'C
iJ.A
iJ.A

MAX

All inputs at

MIN,25'C

OVorVDD

MAX

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VDD as shown, VSS ~ 0 V, T A ~ 25'C (See Note 21
LIMITS
SYMBOL

VDD ~5 V

PARAMETER

MIN
tPLH

Propagation Delay, An to On

tPHL

TYP

VDD

MAX

MIN

= 10 V

TYP

MAX

VDD - 15V
MIN

TYP

260

95

65

260

95

65
65

260

95

tpHL

260

95

65

tPLH

200

70

50

tpHL

200

70

50

tTLH

135

75

45

135

75

45

tPLH

Propagation Delay, EL to On
Propagation Delay, E to On
Output Transition Time

tTHL
ts

Set-Up Time, An to EL

60

20

15

th

Hold Time, An to EL

60

20

15

tw EL

Minimum EL Pulse Width

60

20

15

UNITS

TEST CONDITIONS

MAX
ns
ns
ns

CL

= 50 pF,

RL

~

200 k!1

Input Transition

ns

Times

~

20 ns

ns
ns

NOTES:
1. Additional DC Characteristics are listed in this section under 40008 Series CMOS Family Characteristics.
2. Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.

SWITCHING WAVEFORMS

EL

r-tWELi
,50%

1,.5-0-%-----

t;tsJ-th~
An.O%

50%~

MINIMUM EL PULSE WIDTH AND
SET-UP AND HOLD TIMES, An TO EL

NOTE:
Set~up

(ts) and Hold (th) Times are shown as positive values but may be specified as negative values.

7-163

45158
1-OF-16 DECODER/DEMULTIPLEXER WITH

DESCRIPTION - The 4515B is a 1-of-16 Decoder/Demultiplexer with four binary weighted Address
Inputs (AO-A3), a Latch Enable Input (Ell, an active LOW Enable Input (E) and sixteen mutually
exclusive active LOW Outputs (00-015).

CONNECTION DIAGRAM
DIP (TOP VIEW)

When the Latch Enable Input (Ell is HIGH, the selected Output (00-015) is determined by the data
on the Address Inputs (AO-A3). When the Latch Enable Input (Ell goes LOW, the last data present
at the Address Inputs (AO-A3) is stored in the latches and the Outputs (00-015) remain stable. When
the Enable Input (E);s LOW, the selected Output (00-015), determined by the contents of the latch,
is LOW. When the Enable Input (E) is HIGH, all Outputs (00-015) are HIGH. The Enable Input (E)
does not affect the state of the latch.

24
AO

23
22

With the Latch Enable Input (Ell HIGH, 16-channel demultiplexing results when data is applied to
the Enable I nput (E) and the desired output is selected by AO-A3. The selected Output (00-015) will
follow the data at the Enable Input (E). All unselected outputs (00-015) are HIGH.
•
•
•

A2

21
20

LATCH ENABLE INPUT (ACTIVE HIGH)
ENABLE INPUT (ACTIVE LOW)
BUFFERED OUTPUTS (ACTIVE LOW)

19
18

PIN NAMES
Address Inputs
Enable Input (Active LOW)
Latch Enable Input
Outputs (Active LOW)

AO-A3

E
EL
°0-015

17
16

lOGIC SYMBOL
23

1

3

21

15

10

22

11

°'2

V OD "'" Pin 24
VSS =Pin12

45158

11

9

10

8

5

4

18

17

20

19

14

13

16

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual In-line Package.

15

TRUTH TABLE
INPUTS

OUTPUTS

E

AO

A1

A2

A3

00

01

°2

03

04

°5

06

°7

Os

09

010

°11

012

°13

°14

°15

H

X

X

X

X

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

L

L

L

L

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

L

L

L

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

l

H

L

L

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

L

L

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

L

L

L

H

L

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

L

H

L

H

L

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

L

L

H

H

L

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

L

H

H

H

l

H

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

l

L

L

l

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

H

L

H

L

L

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

'H

L

L

H

L

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

L

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

L

l

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

l

H

H

H

L

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

L

l

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

l

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H = HIGH Level
L = LOW Level
EL ~ HIGH

7-164

14
13

12

FAIRCHILD CMOS. 45158
LOGIC DIAGRAM

•
@
015

® @
i514

613

® 0 CD CD 0 ®

@ @) @ @
012

011

610

59

59

07

06

VOO = Pin 24
VSS =Pin12
"'" Pin Number

0

7-165

06

0-

03

@

®

@

02

Oi

00

FAIRCHILD CMOS • 45158
DC CHARACTERISTICS: VOO as shown, VSS

=

0 V (See Note 1)
LIMITS

SYMBOL

PARAMETER

VOO - 5 V
MIN

Quiescent

Power
100

Supply
Current

TYP

XC
XM

VOO-10V

MAX

MIN

TYP

MIN

TYP

TEMP

UNITS

VOO -15 V

MAX

TEST CONOITIONS

MAX

20

40

80

150

300

600

5

10

20

150

300

600

MIN,25"C
/lA
/.tA

MAX

All inputs at

MIN,25"C

o V or VOO

MAX

AC CHARACTERISTICS AND SET-UP REQUI REMENTS: VOO as shown, VSS = 0 V, T A = 25"C (See Note 2)
LIMITS
SYMBOL

PARAMETER

VOO - 5 V
MIN

tPLH

Propagation Delay, An to

tPHL
tPLH

On
-

Propagation Delay, EL to On

tpHL
tpLH

-

-

Propagation Oelay, E to On

tPHL
tTLH

Output Transition Time

tTHL

TYP

MAX

VOO-10V
MIN

TYP

MAX

VOO -15V
MIN

TYP

260

95

65

260

95

65

260

95

65

260

95

65

200

70

50

200

70

50

135

75

45

135

75

45

ts

Set-Up Time, An to EL

60

20

15

th

Hold Time, An to EL

60

20

15

twEL

Minimum EL Pulse Width

60

20

15

UNITS

TEST CONOITIONS

MAX
ns
ns
CL =50 pF,
ns

RL=200kn

Jnput Transition
ns

Times'" 20 ns

ns
ns

NOTES:
1. Additional DC Characteristics are listed in this section under 4000B Series CMOS Family Characteristics.
2. Propagation Delays and Output Transition Times are graphically described in this section under 4000B Series CMOS Family Characteristics.

SWITCHING WAVEFORMS

MINIMUM EL PULSE WIDTH AND
SET-UP AND HOLD TIMES, An TO EL

NOTE:
Set-up (t s ) and Hold (th) Times are shown as positive values but may be specified as negative values.

7-166

4516B
UP/DOWN COUNTER
DESCRIPTION - The 4516B is an edge-triggered synchronous Up/Down 4-Bit Binarv Counter with a
Clock Input (CP), an active HIGH Count Up/Down Control Input (Up/On), an active LOW count
Enable Input (CE), an asynchronous active HIGH Parallel Load Input (PL), four Parallel Inputs
(PO-P3), four parallel Outputs (QO-Q3). an active LOW Terminal Count Output (Te) and an overriding
asynchronous Master Reset Input (MR).

LOGIC SYMBOL

4 12 13 3

Information on the Parallel Inputs (PO-P3) is loaded into the counter while the Parallel Load Input
(PL) is HIGH, independent of all other input conditions except the Master Reset Input (MR) which
must be LOW. When the Parallel Load Input (PL) and the Count Enable Input (CE) are LOW, the
counter changes on the LOW-to-HIGH transition of the Clock Input (CP). The Count Up/Down
Control Input (Up/On) determines the direction of the count, HIGH for counting up, LOW for counting down. Wben counting up, the Terminal Count Output (TC) is LOW when ()o = Q1 = Q2 = Q3 =
HIGH and CE = LOW. When counting down the Terminal Count Output (TC) is LOW when
=
Q1 = Q2 = Q3 = LOW and the CE = LOW. A HIGH on the Master Reset Input (MR) resets the counter
(QO = Q1 = Q2 = Q3 = LOW) independent of all other input conditions.

15

4516B

TC 0-- 7

10

no

6 11 14 2

VOD = Pin 16

VSS

•
•
•
•

UP/DOWN COUNT CONTROL
SINGLE CLOCK INPUT (L-+H EDGE-TRIGGERED)
ASYNCHRONOUSPARALLELLOADINPUT
ASYNCHRONOUS MASTER RESET

= Pin 8

CONNECTION DIAGRAM
DIP (TOP VIEW)

16
15

MODE SELECTION TABLE

14

PL

UP/DN

CE

CP

MODE

H
L
L
L

X
X
L
H

X
H
L
L

X
X
I

Parallel Load (P n -+ Qn)
No Change
Count Down, Binary
Count Up, Binary

S

13

12
11
10

MR = LOW
H
= HIGH Level

L

= LOW

x

=

I

= Positive-Going

Level

Don't Care

Transition

NOTE:
The F latpak version has the same pinouts (Connection Diagram) as the

STATE DIAGRAM

Dual I n-line Package,

PIN NAMES
Parallel Load Input (Active
PL
HIGH)
Parallel Inputs
Count Enable Input
(Active LOW)
Clock Pulse Input (L-+H
CP
Edge-Triggered)
Up/Down Count Control
Up/On
Input
Master Reset Input
MR

COUNT UP
COUNT DOWN -----------

LOGIC EQUATION FOR TERMINAL COUNT
TC

= CE. [(UP/ON)

• QO. Q1 • Q2. Q31 + [(UP/ON) •

TC

00. 01

• 02· 031

7-167

Terminal Count Output
(Active LOW)
Parallel Outputs

FAIRCHILD CMOS • 45168
LOGIC DIAGRAM

o

®

@ @

00

CDM-R~~----~~~------~~---+------~~-1------~r---r-----~

CDPL~~L-»--q)--~~-t---t--lr--r---r--'--1---1-~

@Vcp-~=l->o-~~-1

0_---------:t
TC

VDO = Pin 16
VSS

o

PL

Q

Pin 8

Pin Number

Asynchronously Loads Pinto Q, Overriding all Other Inputs

P(Parallel Input) - Data on this Pin is Asynchronously Loaded into Q, when PL is HIGH Overriding all Other Inputs
(Toggle Input) - Forces the Q Output to Synchronously Toggle when a HIGH is placed on this Input
CP (Clock Pulse Input)
Q, Q (True and Complementary Outputs)

T

CP
--0 T

PL (Parallel Load Input) -

=

=

Q

DC CHARACTERISTICS: VDD as shown, VSS = 0 V (See Note 1)
LIMITS
SYMBOL

PARAMETER

VDD = 5 V
MIN

Quiescent
Power

IDD

Supply
Current

XC
XM

TYP

VDD=10V

MAX

MIN

TYP

UNITS

VDD=15V

MAX

MIN

TYP

20

40

80

150

300

600

5

10

20

150

300

600

Notes on followmg page

7-168

TEMP

TEST CONDITIONS

MAX
MIN,25'C
I'A
I'A

MAX

All inputs at

MIN,25'C

o Vor VDD

MAX

FAIRCHILD CMOS • 4516B
AC CHARACTERISTICS ANO SET-UP REQUIREMENTS: VOO as shown, VSS =0 V, TA = 25"C (See Note 21
LIMITS
SYMBOL

PARAMETER

MIN
tpLH

Propagation Delay, CP to On

tpHL
tPLH

VOO=10V

VOO = 5 V

-

Propagation Delay, CP to TC

tpHL

UNITS

VOD = 15V

TYP

MAX

150

350

62

160

41

128

150

350

59

160

39

128

MIN

TYP

MAX

MIN

TYP

167

450

71

180

48

144

252

650

100

245

66

196

170

325

70

150

45

120

tpHL

220

425

90

195

62

156

tpLH

225

500

170

210

105

168

tpHL

205

450

120

190

80

152

tTLH

60

135

31

75

23

45

65

135

25

75

18

45

tPLH

Propagation Delay, PL to On

Propagation Delay, MR to On. TC
Output Transition Time

tTHL

TEST CONDITIONS

MAX
ns
ns
ns
ns
ns

CL=50pF,

twCP

CP Minimum Pulse Width

125

50

60

21

48

14

ns

RL = 200 kn

twPL

PL Minimum Pulse Width

150

60

60

21

48

16

ns

I nput Transition

twMR

MR Minimum Pulse Width

150

60

60

30

48

20

ns

Times

tree

MR Recovery Time

175

75

70

30

56

20

ns
ns

tree

PL Recovery Time

150

62

60

24

48

17

ts

Set-Up Time, UP/ON to CP

325

145

140

55

110

38

th

Hold Time, UP/ON to CP

ts

Set-Up Time, CE to CP

th

Hold Time, CE to CP

ts

Set-Up Time, Pn to PL

th

Hold Time, Pn to PL
Input Clock Frequency (Note 31

-

fMAX

0

-90

0

-35

0

-25

275

118

120

49

96

33

0

-40

0

-15

0

-10

70

29

30

11

24

0

-40

0

-20

0

-20

2

5

5

12

6

15

8,

~

20 ns

ns
ns
ns
MHz

NOTES:

1.
2.

Additional DC Characteristics are listed in this section under 4000B Series CMOS Family Characteristics.
Propagation Delays and Output Transition Times are graphically described in this section under 4000B Series CMOS Family Characteristics.

3.

For fMAX, input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.
It is recommended that input rise and fall times to the Clock Input be less than 15}ls at VDO = 5 V, 4}ls at VOO = 10 V, and 3}lS at

4.

VDD=15V,

•

7-169

FAIRCHILD CMOS • 4516B
SWITCHING WAVEFORMS

UP/ON

MINIMUM CP WIDTH, SET-UP AND HOLD
TIMES, CE TO CP AND UP/ON TO CP

CP

PL

1::::1',ecMR ____________________-J;(5o%

~~5_0_%_______

MINIMUM PL AND MR PULSE WIDTH, RECOVERY
TIME FOR PL AND MR, AND SET-UP AND HOLD TIMES, Pn TO PL

NOTE:
Set~up

and Hold Times are shown as positive values but may be specified as negative values.

7-170

45188
DUAL 4-81T DECADE COUNTER
DESCRIPTION - The 45188 is a Dual 4-Bit Internally Synchronous BCD Counter. Each counter has
both an active HIGH Clock Input (CPO) and an active LOW Clock Input (CP1). buffered Outputs from
all four bit positions (00-03) and an active HIGH overriding asynchronous Master Reset Input (MR).

LOGIC SYMBOLS

The counter advances on either ~ LOW-to-HIGH transition of the CPa Input if CPl is HIGH or the
HIGH-~LOW transition of the CPl Input if CPa is LOW (see the Truth Table). Either Clock Input
(CPO. CP1) may be used as the Clock Input to the counter and the other Clock Input may be used
as a Clock I nhibit Input.
A HIGH on t~ Master Reset Input (MR) resets the counter (00-03
Inputs (CPO. CP1).

=

LOW) independent of the Clock

3

•
•
•
•
•

TYPICAL COUNT FREQUENCY OF 10 MHz AT VDD = 10 V
TRIGGERED ON EITHER A LOW-TO-HIGH OR A HIGH-TO-LOW TRANSITION
ASYNCHRONOUS ACTIVE HIGH MASTER RESET
BUFFERED OUTPUTS FROM ALL FOUR BIT POSITIONS
FULLY SYNCHRONOUS COUNTING

MR

H

L

Counter Advances

"'-

L

Counter Advances

J
L

"'- J
H
X

VDO = Pin 16
X

Don't Care

L

LOW Level

H

HIGH Level

L

No Change

L

No Change

L

L

No Change

~= Positive-Going Transition

"'-

L

No Change

~=

H

Reset (Asynchronous)

X

11 12 13 14

MODE

X

X

J

6

CP b

15

CPl

5

1/2 OF 45188

9
10

TRUTH TABLE
CPa

4

Negative-Going Transition

VSS

= Pin 8

CONNECTION DIAGRAM
DIP (TOP VIEW)

16

1/2 OF

A 4518B LOGIC

0

15

DIAGRAM

14

00
0R

@

4

13
12

11
10

(DOR@
MR-1>~4>--+---+---~--1---~--~-+--~-r----+-~

NOTE:

The Flatpak version has the same pinouts (Connection Diagram) ~.<; the
Dual In-line Package.

G)OR@
CPo

CP1

PIN NAMES
·CPOa• CPOb

@OR@

CPla. CPlb
MRa. MRb
Ooa-03a
Oob- Q3b

Voo = Pin 16
VSS = Pin 8

o

= Pin Number

7-171

Clock Input (L
(Triggered)
Clock Input (H
Triggered)

-+

H

-+

L

Master Reset Inputs
Outputs
Outputs

FAIRCHILD CMOS • 45188
DC CHARACTERISTICS: VDD as shown, VSS ~ 0 V (See Note 1j
LIMITS
SYMBOL

PARAMETER
Quiescent

Power
IDD

Supply
Current

VDD
MIN

~

VDD~10V

5V

TYP

XC

MAX

MIN

TYP

VDD~15V

MAX

MIN

TYP

MAX

20

40

80

150

300

600

5

10

20

150

300

600

XM

UNITS

p.A
IJ.A

TEMP

TEST CONDITIONS

MIN,25"C
MAX
MIN,25"C

All inputs at 0 V
orV DD

MAX

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: V DD as shown, FSS ~ 0 V, TA ~ 25"C (See Note 2)
LIMITS
SYMBOL

V DD

PARAMETER

MIN

CP1

TYP

MAX

V DD ~ 15 V
MIN TYP MAX

V DD

~5V

TYP

MAX

MIN

~

10 V

tpLH

Propagation Delay, CPO or

220

480

95

210

60

168

tpLH

to an

220

480

95

210

60

168

tpHL

Propagation Delay, MR to an

220

480

90

210

60

168

tTLH
tTHL

Output Transition Time

65

135

35

70

25

45

65

135

35

70

25

45

UNITS

ns
ns
ns

tw MR

MR Minimum Pulse Width

180

70

70

30

56

20

ns

twCP

CPa or CPl Minimum Pulse Width

275

120

120

50

96

35

ns

tree

MR Recovery Time

40

15

25

5

20

0

ns

ts

Set-Up Time, CPO to CPl

275

130

125

57

100

40

ns

ts
f MAX

Set-Up Time, CP1 to CPa

275

130

125

57

100

40

ns

2

4

4

10

5

12

MHz

Input Count Frequency (Note 3)

TEST CONDITIONS

CL

~

50 pF,

RL ~ 200 kfl
Input Transition

Times";;;; 20 ns

NOTES:
1. Additional DC Characteristics are listed in this section under 4000B Series CMOS Family Characteristics.
2. Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.
3. For f MAX ' input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.
4. ~t li~ r~~ommended that input rise and fall times to the Clock I nput be less than 15 j.Ls at V DO = 5 V, 4 Ils at V DO = 10 V, and 3 jJS at V DO

SWITCHING WAVEFORMS

_ls~_ ~

-

t?~L' 0

p"P

--

'-"

III

104

...--

>-'

JiJlr

~

30 0

u

~V

;..-~

TA 0125'C

o

~~

w

'-"

I 350

vJJlU

C

E lOa

;2

PROPAGATION DELAY,
CPO OR CPl TO an,
VERSUS LOAD CAPACITANCE

~ 50

tpU-" tpl-lL' \/00 '" "0':::-

I-

tpL1-\. 1PHL. VDO - 15\1

I

l'
~

10 5

INPUT FREQUENCY - Hz

00

20

40

80

60

'00

120

140

160

CL - LOAD CAPACITANCE - pF

PROPAGATION DELAY,
CPO OR CPl TO an,
VERSUS TEMPERATURE
~

400

I

CLio 15

PROPAGATION DELAY,
MR TO an, VERSUS
LOAD CAPACITANCE
350

~F

2

16"
a:

300

~

250

>-'

~oo>s~

~

200

t5

1S0

.-

100

- -

.,.,- (

o

~

~

~I

50

~

l'
:5

~

o

>1 25• c

I 300

o

«

TA

o

or::. 350

f-

-60 -40 -20

.,.,.,.,

.,

"~. 200

40

60

lSV

80

'00

.,

I-"'"
l~ .,.-

V V

o
z

~

·LL~
-I voo
20

<5
2
cc 250

-

100 120

150

:;l

~ 100

I

i
140

~oo

~~

if
50

~
20

TA - AMBIENT TEMPERATURE _ DC

40

-10\1

~

60

80

-

100

~

I--

120

C L - LOAD CAPACITANCE - pF

7-173

--

140

160

45208
DUAL 4-BIT BINARY COUNTER
DESCRIPTION - The 4520B is a Dual 4-Bit Internally Synchronous Binary Counter. Each counter
has both an active HIGH Clock Input (CPO) and an active LOW Clock Input (CP1), buffered Outputs
from all four bit positions (°0-°3) and an active HIGH overriding asynchronous Master Reset Input (MRI.

LOGIC SYMBOLS

The counter advances on either !b!' LOW-to-HIGH transition of the CPO Input if CPl is HIGH or the
HIGH-to-LOW transition of the CPl Input if CPO is LOW (see the Truth Table). Either Clock Input
(CPO, CPl) may be used as the Clock Input to the counter and the other Clock Input may be used
as a Clock Inhibit Input.
A HIGH on t~ Master Reset Input (MR) resets the counter (00-03
Inputs (CPO, CP1)'

=

LOW) independent of the Clock

3

•
•
•
•
•

TYPICAL COUNT FREQUENCY OF 10 MHz AT VDD = 10 V
TRIGGERED ON EITHER A LOW·TO-HIGH OR A HIGH-TO-LOW TRANSITION
ASYNCHRONOUS ACTIVE HIGH MASTER RESET
BUFFERED OUTPUTS FROM ALL FOUR BIT POSITIONS
FULLY SYNCHRONOUS COUNTING

MR

H

L

Counter Advances

"--

J
L

15

L

Counter Advances

L

No Change

L

No Change

L

L

No Change

~'=' Positive-Going Transition

"--

L

No Change

""""-.=

H

Reset (Asynchronous)

X

J

H
X

X

11 12 13 14

MODE

X

"-- J

6

1/2 OF 45208

TRUTH TABLE
CPl

5

CPb

10

CPo

4

X

Don't Care

L

LOW Level

H

HIGH Level

Voo

= Pin

VSS

== Pin 8

16

CONNECTION DIAGRAM
DIP (TOP VIEW)

Negative-Going Transition

16

15
14

1/2 OF A 4520B LOGIC DIAGRAM

00R@

°1

°2

13

®OR@ I

12
11
10

MR---i>~~~--~~---+--+---+---~~--~~--r--r--~

(j)OR@

NOTE:
The Flatpak version has the same pinouts

(Connection

Diagram)

as the

Dual I n-line Package.

PIN NAMES
CPOa, CPOb
CPla, CPlb

Voo = Pin 16

VSS

o

7-174

= Pin 8
= Pin Number

Clock Input (L-+ H
Triggered)
Clock Input (H -+ L
Triggered)

MR a, MRb

Master Reset Inputs

Ooa-03a
Oob- Q3b

Outputs
Outputs

FAIRCHILD CMOS. 4520B
DC CHARACTERISTICS: VDD as shown, VSS ~ 0 V :(See Note 1.)
LIMITS
SYMBOL

PARAMETER

Quiescent
Power
IDD

Supply
Current

VDD
MIN

~

5V

TYP

VDD

MAX

XC
XM

MIN

~

VDD~15V

10 V

TYP

MAX

MIN

TYP

MAX

20

40

80

150

300

600

5

10

20

150

300

600

UNITS

TEMP

TEST CONDITIONS

MIN,25°C

,..A

MAX
MIN,25°C

,..A

All inputs at 0 V
orV DD

MAX

AC CHARACTERISTICS AND SET·UP REQUI REMENTS: V DD as shown, VSS ~ 0 V, T A ~ 25°C (See Note 2)
LIMITS
SYMBOL

V DD

PARAMETER

MIN

~

5 V

TYP

MAX

VDD~

MIN

TYP

10V
MAX

VDD~15V

MIN

TYP

MAX

tpLH

Prooagation Delay, CPO or CP1

220

480

95

210

60

168

tpHL

to Q n

220

480

95

210

60

168

tpHL

Propagation Delay, MR to Q n

220

480

90

210

60

168

65

135

35

70

25

45

65

135

35

70

25

45

tRLH

Output Transition Time

tTHL

UNITS TEST CONDITIONS

ns
ns
ns

CL

~

50pF,

MR Minimum Pulse Width

180

70

70

30

56

20

ns

twCP

CPO or CP1 Minimum Pulse Width

275

120

120

50

96

35

ns

Input Transition

tree
ts

IVIR Recovery Time

40

15

25

5

20

0

ns

Times.,;;;;. 20 ns

Set·Up Time, CPO to CP1

275

130

125

57

100

40

ns

t,

Set·Up Time, CP1 to CPa

275

130

125

57

100

40

ns

f MAX

Input Count Frequency (Note 3)

2

4

4

10

5

12

MHz

twMR

RL~200kn

NOTES:
1. Additional DC Characteristics are listed in this section under 40008 Series CMOS Family Characteristics.
2. Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.
3, For f MAX ' input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.
4. It is recommended that input rise and fall times to the Clock Input be less than 15 jls at V DO = 5 V, 4 fJ,s at V DO = 10 V, and 3 !Js at V DD
~ 15 V.

SWITCHING WAVEFORMS
_'wCP _
CPo

MR

I~_'WMR_I
______J 150%

'ree

~o%___________ _

CP,

~

_ MINIMUM PULSE WIDTHS FOR
CPO, CP1 AND MR AND MR RECOVERY TIME

SET·UP AND HOLD TIMES, CPa TO CP1 AND CP, TO Cpa

CONDITIONS: CP1 ~ HIGH and the device triggers on a
LOW-to-HIGH transition at CPO. The timing also applies
when CPa ~ LOW and the device triggers on a HIGH-toLOW transition at CP1,
NOTE:

Set-up and Hold Times are shown as positive values but maY be specified as negative values.

7·175

•

FAIRCHILD CMOS • 4520B
TYPICAL ELECTRICAL CHARACTERISTICS

POWER DISSIPATION
VERSUS FREOUENCY

PROPAGATION DELAY. MR TO an.
VERSUS LOAD CAPACITANCE

100 0

350
TA "" 25"C

IIII

0

I)"-.\~)

1

J

J~ V;:::

-.\00*

~ ~V

is

~ 150

"0100
~

'I

CL"'50P~I- - - -

:;:::

f-- f-- ~

I
~

~

15 pF

50

o

~
o

o

20

CL

o

250

~'

w:! 200

o

V

2

"o~

100

~

50

!

0

go

~

80

I ....

1- ~

.."
~

100

120

140

160

~ 25'C

300

C; 250
!3
>'

V V

~ 200

o
~ 150

~

·LJ'0V
I-- ~

i"

>-

laO

~ 50

-

-

voJ."

0:

o

150

TA

[:2

16

o

~

60

PROPAGATION DELAY. CPo OR CP1
TO an. VERSUS LOAD CAPACITANCE

1350

~ 15 ~F

350

16a: 300
!3

40

CL - LOAD CAPACITANCE - pF

PROPAGATION DELAY. CPO OR CP1
TO an. VERSUS TEMPERATURE
400

:--I-

~

INPUT FREQUENCY - HZ

6

,.- l-

\/00",10\1

Ii:

I

CL

~

o

,,-.\

2

1?I---

V V

~'
uj 200

,,~

k~ V~

1.....<:1-.1

-.\00* ....

"00

~ 250

~

0

10-4

c300

a
[:2

,.<:P

0

TA'" 2SoC

~
I

~

;..-

I-

,.c~C,;..:.:;o-

~

tPL\4, tPHL, \lDD '" 10 V

I-

----:;;"H, tpHL VOO '" 15 V

~

-60 -40 -20

o

20

40

60

80

TA - AMBIENT TEMPERATURE -

100 120

~

140

"c

00

20

40

60

80

100

120

CL - LOAD CAPACITANCE - pF

7·176

140

160

45218
24-STAGE BINARY COUNTER

GENERAL DESCRIPTION - The 4521 B is a timing circuit consisting of an on-chip oscillator circuit
and a 24-stage binary ripple counter. The device has two Oscillator Inputs (11 and 12 ) and two Oscillator Outputs (01 and 02)' Source Connections to the n-channel and p-channel transistors of the oscillator circuit (SN and Sp), a Master Reset Input (MR) and Data Outputs from the last seven stages of the
24-stage Ripple Counter (Q17- Q 23).
The 4521 B, as shown in the Block Diagram, may be used with either an external crystal oscillator circuit, an external RC oscillator circuit, or external clock input. Oscillator Output, 02' is available for
driving additional external loads. The oscillator circuit may be made less sensitive to variations in the
power supply voltage by adding external resistors Rl and R2 (See Block DiClgram). If these external
resistors are not required, Source Connection Sp must be tied to VOO and Source Connection SN
must be tied to VSS'
The 24~Stage Ripple Counter advances on the HIGH~to~LOW transition of the clock input with parallel
Data Outputs (Q1 r Q 23) from the last seven stages available.
A HIGH on the Master Reset Input (MR) clears ali counter stages, forcing ali Paraliel Data Outputs
(Q17-Q23) LOW and disables the oscillator circuit, independent of all other inputs. This allows for
very low standby power dissipation.
•
•
•
•
•

LOGIC SYMBOL
5

3

45216

Voo = PIN 16
VSS=PIN8

10

11

12

14

13
12
11

10

NOTE:
The F latpak version has the same
pinouts (Connection Diagram) as the
Dual I n-line Package.

",'

K~---------~l
,,'
-----, I :
----,

OP~N

t

Cl

~

I I I

-1- :~,,;'®',-f-----r,
I I

~

"""'--O- _ _ --1_I~-+;;O'+_--+----'

,,'

C';ur='

Cx2

-

==~ :~

10
;;:it--D.o--+-----....-+-----..J

:~L---------_+~-------~_+_+~+++_--'
I

~

CRYSTAL

:

To

I I I
VD~'~:r~~ISCI~- _ _ ~ I I J
0,,",,

1

15

RCO""lld\'"

0'

15

16

BLOCK DIAGRAM

T~ vo~r~:\~s~'t:::.o.- _

14

CONNECTION DIAGRAM
DIP (TOP View)

ON-CHIP CRYSTAL OSCILLATOR CIRCUIT OR ON-CHIP RC OSCILLATOR CIRCUIT OR
EXTERNAL CLOCK INPUT
MASTER RESET INPUT CLEARS ALL COUNTER STAGES AND DISABLES OSCILLATOR
CIRCUIT FOR LOW STANDBY POWER
EXTERNAL SOURCE CONNECTIONS FOR IMPROVED TIMING STABILITY
OSCILLATOR OUTPUT AVAILABLE FOR DRIVING EXTERNAL LOADS
MASTER RESET INPUT FACILITATES DIAGNOSTICS

PIN NAMES
11 ,1 2
Osciliator Inputs
Sp
Source Connection~to~p~channel transistor
SN
Source Connection~to~n-channel transistor
MR
Master Reset Input
0 1 , O2
Oscillator Outputs
Q17- Q 23 Data Outputs

13

...-o----t-1J

voo

=

PIN 16

VSS

=

PIN 8

o

~..J
Op~n~ _ _ ..J

Fror" Ex,"","1 CICJtk ----0--- _ _

7-177

=PIN NUMBER

•

4522B·4526B
PROGRAMMABLE 4-BIT BCD/BINARY DOW
GENERAL DESCRIPTION - The 4522B/4526B is a synchronous Programmabl
/Binary
Down Counter with an active HIGH and an active LOW Clock Input (CPO' CP 1), an asynchronous
Parallel Load Input (PL), four Parallel Inputs (PO-P 3 ), a Carry Forward Input (CF), four buffered
Parallel Outputs (QO-Q3), a Terminal Count Output (TC) and an overriding asynchronous Master
Reset Input (MR).
Information on the Parallel Inputs (P O-P3) is loaded into the counter while the Parallel Load Input
(PL) is HIGH, independent of all other input conditions except Master Reset Input (MR) which must
be LOW. When the Parallel Load Input (PL) and the active LOW Clock Input (CP 1) are LOW, the
counter advances on a LOW-to-HIGH transition of the active HIGH Clock Input (CPO). When the
Parallel Load Input (pL) is LOW and the active HIGH Clock Input (CPO) is HIGH, the counter advances
on a HIGH-to-LOW transition of the CP, Input. The Terminal Count Output (TC) is HIGH when the
counter is in the zero state (QO ~ Q1 ~ Q2 ~ Q3 ~ LOW) and the Carry Forwaf"d Input (CF) is HIGH.
A HIGH on the Master Reset Input (MR) resets the counter IQO-Q 3 ~ LOW) independent of other
input conditions.

LOGIC SYMBOL

3

5 11 14 2

13

12

10

7

9 15 1

VDO = Pin 16

•
•
•
•
•

FULL Y SYNCHRONOUS PROGRAMMABLE BCD/BINARY DOWN
COUNTER
CLOCK INPUT EITHER HIGH-TO-LOW OR LOW·TO·HIGH EDGE·TRIGGERED
ASYNCHRONOUS MASTER RESET
CASCADABLE
ASYNCHRONOUS PARALLEL LOAD

VSS = Pin 8

CONNECTION DIAGRAM
DIP (TOP VIEW)

PIN NAMES
PL Parallel Load Input
Parallel Inputs
PO-P 3
CF
Carry Forward Input
CPa
Clock Input (L ->H Edge·Triggered)
CP 1
Clock Input (H-7l Edge·Triggered)
MR
Asynchronous Master Reset Input
TC
Terminal Count Output
Q O-Q3
Buffered Outputs

16
15
14
13

12
11

MODE SELECTION TABLE
10

MR

PL

cPo

ep ,

H

X

X

X

RESET (ASYNCHRONOUS)

L

H

X

X

PRESET (ASYNCHRONOUS)

L

L

..r

H

NO CHANGE

L

L

L

'-

NO CHANGE

L

L

'-

X

NO CHANGE

L

L

X

L

L

...r

L

L

H

MODE

..r

NO CHANGE

----

L

COUNTER ADVANCES

NOTE:

'-

COUNTER ADVANCES

The

Flatpak version

has the same

pinouts (Connection Diagram) as the
Dual I n-line Package.

DON'T CARE
L~ LOW LEVEL
H = HIGH LEVEL
f = POSITIVE GOING TRANSITION
""\....~ NEGATIVE GOING TRANSITION
X

STATE DIAGRAM
4526B

4522B

LOGIC EQUATION FOR TERMINAL COUNT

TC ~ CF •

7·178

00· (Q1 + Q2 + Q3)

FAIRCHILD CMOS· 4522B/4526B
45226 LOGIC DIAGRAM

@

CF~~r----------i----+-------~-----------{--'

o

PL~~+------------4----~----------------------r-~

@

Voo

MR~~------------~~--------------~~

=

PIN 16

VSS~PIN8
() =

PIN NUMBER

4526 LOGIC DIAGRAM

Po

00

00

•
--0
CP1 0~6"";'-+----'l-~
CPO~~1-f)~~--'

@
>1>-----=::... TC

o

PL.~~4------------4----~----------------------r-~

@

MR~~-------------4----------------~~

PL

--0 CP
--0

T

MR

VDD ~ PIN 16
VSS"PIN 8
a ~ PIN NUMBER

PL (Parallel Load Input) - Asynchronously Loads Pinto G, Overriding all Other Inputs
P (Parallel Input) - Data on this Pin is Asynchronously Loaded into Q, when PL is HIGH Overriding all Other Inputs
T (Toggle Input) - Forces the Q Output to Synchronously Toggle when a LOW is Placed on this Input.
CP lClock Pulse Input)
Q, Q (True and Complimentary-outputs)
MR (Mas",r Reset Input)

7-179

FAIRCHILD CMOS • 45228/45268
DC CHARACTERISTICS: V DD as shown VSS = 0 V (Note 1)
LIMITS
SYMBOL

PARAMETER

V DD = 5 V
MIN

Quiescent
Power

IDD

TYP

XC

Supply
XM

Current

V DD

MAX

MIN

~

10V

TYP

V DD =15V

MAX

MIN

TYP

UNITS

TEMP

TEST CONDITIONS

MAX

20

40

80

150

300

600

5

10

20

150

300

600

MIN,25OC

iJA

MAX

All inputs
atOVarV DD

MIN,25OC

iJA

MAX

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: V DD as shown, VSS ~ 0 V, T A ~ 25°C (See Note 2)
LIMITS
SYMBOL

PARAMETER

V DD
MIN

~

5 V

TYP MAX

V DD
MIN

~

10 V

TYP MAX

V DD =15V
MIN

UNITS

I TEST CONDITIONS

TYP MAX

tpLH

Prapagati on Delay, CPO or

220

95

60

ns

tpHL

CP 1 to

220

95

60

ns

tpLH

Propagation Delay, CPO or

240

105

66

ns

tpHL

CP 1 to TC

240

105

66

ns

tpLH

Propagati on Delay, CF

200

85

53

ns

tpHL

to TC

200

85

53

ns

tpLH

Propagation Delay, PL

220

90

65

ns

tpHL

to Q n

220

90

65

ns

tpHL

Propagation Delay, MR to Q n

220

95

60

ns

tTLH

Output Transition

65

25

18

ns

CL

tTHL

Time

65

25

18

ns

R L =200kn

tree
tw MR

M R Recovery Ti me

15

5

0

ns

Input Transition

MR Minimum Pulse Width

70

30

20

ns

Times ";;20 ns

Qn

tree

P L Recovery Ti me

15

5

0

ns

twPL

PL Minimum Pulse Width

70

30

20

ns
ns

twCP

CP Minimum Pulse Width

120

50

35

ts

Set-Up Time, CF to CLOCK

150

50

35

ns

th

Hold Time, CF to CLOCK

100

40

25

ns

ts

Set-Up Time, Pn to PL

30

15

10

ns

th

25

10

5

ns

th

Hold Time, Pn to PL
Hold Time, CPO to CP 1

130

57

40

ns

th
f MAX

Hold Time, CP 1 to CPO
Input Count Frequency (Note 3)

130

57

40

ns

4

10

12

MHz

~

50 pF,

NOTES:
1.
2,
3.
4.

Additional DC Characteristics are listed In this section under 40008 Series CMOS Family Characteristics.
Propagation Delays and Output Transition Times are graphically described in this section under4000B Series CMOS Family Characteristics.
For f MAX ' input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.
It is recommended that Input rise and fall times to the Clock I nput be less than 15 p.s 'at V DD = 5 V, 4 p.s at V DD = 10 V, and 3 p.s at
VDD~15V.

7-180

FAIRCHILD CMOS • 45228/45268
SWITCHING WAVEFORMS

t,.CP

CPo

CPo

PL
MR

MINIMUM PULSE WIDTHS FOR
CPo AND MR AND MR RECOVERY TIME

twMR~

..,,/50% \"'5_0_%____

MR _ _ _ _ _ _ _ _ _ _ _

MIMIMUM CPO,PL AND MR PULSE WIDTH,
RECOVERY TIME FOR PL AND MR, AND SET-UP
AND HOLD TIMES, P n TO PL
LOW and the device triggers on a
CONDITIONS:CP 1
LOW-to-HIGH transition at CPO- The timing also applies
when CPO = HIGl:!...!!.nd the device triggers on a HIGH-toLOW transition at CP 1 - MR = PL = LOW_

HOLD TIMES, CPO TO CPl AND CPl TO CPO

SET UP AND HOLD TIMES, CF TO CPO
CONDITIONS:CP 1 = LOW and the device triggers on a
LOW-to-HIGH transition at CPO- The timing also applies
when CPO = HIGH....!!..nd the device triggers on a HIGH-toLOW transition at CP 1-

NOTE:

Set-up and Hold Times are shown as positive values but may be specified as negative values.

7-181

FAIRCHILD CMOS • 45228/45268
TYPICAL APPLICATIONS

2·STAGE PROGRAMMABLE OOWN COUNTER
PARALLEL DATA INPUTS

I
"

VDD

~~~(

~~~~
c:

c:

c:

""
~

6"
~

c:

c:

6"
""
0 ?>8

0

""
~

0

~

PARALLEL
LOAD

~

1

I

PL
100Kn.

Po

P1

P2

0
,..,j1

TC

-:1

CP
MR

1

MASTER
RESET

Po

P1

P2

P3

.... CF

"---- CF

45228/45268
CLOCK

PL

P3

00

°1

°2

03
~

J

0

45228/45268
CP

'J

-DATA
OUTPUTS

7.182

T

°1

°2

TC

03

°4

I-

~ >~
0

§1

0

c:

""~
0

45278
BCD RATE MULTI PLI ER
DESCRIPTION - The 4527B is a BCD Rate Multiplier with an active LOW Coun
t (CE),
and active LOW Q Output Enable Input (EQ), and active LOW Output Enable Input (EI. a Clock Input
(CP), four Mode Select Inputs (SO-5 3 ), a Preset to Nine Input (Pg), an asynchronous Master Reset
Input (MR), an active LO~ Count Enable Output (acE), a Carry Output (Og) and True and Complementary Data Outputs (Q, Q).
When the Master Reset (MR), the Preset to Nine (Pg ) and the Count Enable (CE) Inputs are LOW, the
internal Synchronous 4-Bit Decade Counter triggers on a LOW-to-HIGH transition at the Clock Input
(CP). As shown in the Truth Table, information present on the Mode Select Inputs (SO-5 3 ) determines
the output pulse rate at the Data Outputs (Q and il). For ~ample, if S3=SO=LOW and S1=S2=HIGH,
there will be output pulses at the Data Outputs (Q and Q) for every ten input pulses at the Clock
Input (CP)' Data outputs (Q and 5) are synchronized with the HIGH-to·LOW transition at the Clock
Input (CP). When the Count Enable Input (CE) is HIGH the internal BCD Decade Counter is disabled

LOGIC SYMBOL

1415 2 3

11

and no change occurs in the state of the counter.
With the Q Output Enable Input (EQ) LOW, a I-!,!GH on the Output Enable Input (E) forces Data
Output Q LOW and Complementary Data Output Q HIGH, independent of all other input conditions.
A HIGH on the Q Output Enable Input EQ forces the Data Output Q HIGH, independent of all other
input conditions.

12

10

The Carry Output (Og) goes HIGH when the two most significant bits of the internal BCD Counter
are HI GH and provides one output pulse for every ten input pulses at the Clock Input (CP). The
Count Enable Output (DC E) goes LOW when either the Count Enable Input (CE) is HIGH or the
Carry Output (Qg) is LOW and provides one output pulse for every ten input pulses at the Clock
Input (CP).

13

Voo = PIN 16
VSS=PIN8

With Mode Select Input 53 LOW, a HIGH on the Master Reset Input (MR) resets the two least significant bits of the internal BCD Counter and forces Data Output Q LOW, Complementary Data Output
HIGH, Carry Output ~ HIGH and Count Enable Output 0CE LOW, independent of Clock Input,
CP, Count Enable Input CE and Mode Select Inputs SO-52' With Mode Select Input S3 HIGH, a HIGH
on the Master Reset Input (MR) resets the two least significant bits of the internal BCD Counter and
forces Carry Output Og H,!,GH and Count Enable Output 0CE LOW and provides 10 output pulses at
the Data Outputs (Q and Q) for every 10 input pulses at the Clock Input (CP) independent of Mode
Select Inputs SO-S2'

o

CONNECTION DIAGRAM
DIP (TOP VIEW)

A HIGH on the Preset to Nine Input (Pg ) resets the two least significant bits and sets the two most
significant bits of the internal BCD Counter and forces Data Output Q LOW, Complementary Data
Output 0: HIGH, Carry O!!,!put Og LOW and Count Enable Output 0CE HIGH independent of the
Clock (CP), Count Enable (CE) and Master Reset (MR) inputs.
4527B applications include performance of arithmetic operations, solution of algebraic and differential
equations, generation of logrithms and trigonometric functions AID and 01 A conversion, and fre-

quency synthesis.
•
•
•
•
•

INTERNAL SYNCHRONOUS COUNTERS
COUNT ENABLE AND OUTPUT ENABLE INPUTS
TRUE AND COMPLEMENTARY OUTPUTS SYNCHRONIZED WITH THE HIGH-TO·LOW
TRANSITION AT THE CLOCK INPUT
EASY CASCADING
MASTER RESET AND PRESET TO NINE INPUTS

PIN NAMES
CE

Count Enable Input (Active LOW)

EQ

Q Output Enable Input (Active LOW)

E

Output Enable Input (Active LOW)

CP

Clock Input (L--+H Triggered)

SO-S3

Mode Select Inputs

Pg
MR

Preset to Nine Input

°CE

Og

NOTE:

Master Reset Input

The

Count Enable Output (Active LOW)

Q

Data Output

5

Complementary Data Output (Active LOW)

Flatpak version has the same

pinouts (Connection Diagram) as the
Dual InRI ine Package.

Carry Output

7-183

FAIRCHILD CMOS. 45278
TRUTH TABLE
OUTPUTS

INPUTS

OUTPUT LOGIC LEVEL OR
NUMBER OF OUTPUT PULSES
EO

MR

P9

0

10
10
10
10

L
L
L
L

L
L
L
L

L
L
L
L

L
L
L
L

L
L
L
L

L
H
L
H

10
10
10
10

L
L
L
L

L
L
L
L

L
L
L
L

L
L
L
L

L
L
L
L

L
H
L
H

10
10
10
10

L
L
L
L

L
L
L
L

L
L
L
L

L
L
L

L
L
L

L

L
H
L
H

L

L

L
H
H

10
10
10
10

L
L
L

L
L
L

L
L
L
L

L
L
L
L

X
X
X

X
X
X

X
X
X

10
10
10

H
L

L
H
L

L
L
H

X
X
X

X
X
X

X
X
X

10
10
10

L
L

L
L
L

L
L
L

S1

So

L
L
L

L
L
L
L

L
L
H
H

L
H
L
H

L
L
L
L

H
H
H
H

L
L
H
H

H
H
H
H

L
L
L
L

L
L
H
H

H
H
H
H

H
H
H
H

L

X
X
X
H
L

X

-

E

S2

L

NUMBER OF CLOCK
PU LSES ON INPUT CP

CE

S3

L

L

-

--

0

09

L
1
2
3

H
1
2
3

1
1
1
1

1
1
1
1

4
5

4
5

6
7

6
7

1
1
1
1

1
1
1
1

L

8
9
8
9

8
9
8
9

1
1
1
1

1
1
1
1

L
L
L
L

8
9
8
9

8
9
8
9

1
1
1
1

1
1
1
1

L
L
L

L
L
L

L
H

..
H

1
1

1
1

H
H
L

L

10
L
L

10
H
H

H
H
L

L
L
H

L
H

°CE

. . . .

L = LOW level
H = HIGH level
X = Don't Care
Output Logic Level Depends upon the Internal State of the Counter
Output is the same as the first 16 lines of the Truth Table with the number of Output pulses depending upon the
logic levels at inputs SO·S3

7·184

45288
DUAL RETRIGGERABLE RESETTABLE
MONOSTABLE MULTIVIBRATOR

DESCRIPTION - The 4528B is a Dual Retriggerable Resettable Monostable Multivibrator. Each
Multivib~tor has an active LOW Input (
an active HIGH Input (11)' an active LOW Clear Direct
Input (CD)' an Output (Q). its Complement
and two pins for connecting the external timing
components (Cext ' Cext/Rextl. An external timing capacitor must be connected between Cext and
Cext/Rext and an external resistor must be connected between Cext/Rext and V DO.

0),

(m

VDD

A HIGH-to-LOW transition on the lQ Input when the 11 Input is LOW or a LOW·to-HIGH transition
Input is HIGH produces a positive pulse (L -+ H -+ L) on the Q Output and
on the 11 Input when the
a negative pulse (H -+ L -+ H) on the IT Output if the Clear Direct Input (Co) is HIGH. A LOW on the
Clear Direct Input (Co) forces the Q Output LOW. the IT Output HIGH and inhibits any further
pulses until the Clear Direct Input (Co) is HIGH.

ro

•
•
•
•
•
•
•
•

0,
I

RECOMMENDED OPERATING VOLTAGE. V DD = 4.5 TO 15 V
TYPICAL OUTPUT PULSE WIDTH VARIATION ± 3% AT V DD = 15 V FROM DEVICE TO
DEVICE
TYPICAL OUTPUT PULSE WIDTH STABILITY ± 1% OVER -40°C TO +85°C TEMPERATURE
RANGE AT V DD = 10 V
TYPICAL OUTPUT PULSE WIDTH STABILITY ± 1% AT VD.tI = 10 V ±0.25 V RESETTABLE
TRIGGER ON EITHER A HIGH-TO-LOW TRANSITION ON 10 OR A LOW-TO-HIGH TRANSSITIONON 11
COMPLEMENTARY OUTPUTS AVAILABLE
BROAD TIMING RESISTOR RANGE. 5 kn TO 2 Mn
OUTPUT PULSE WIDTH INDEPENDENT OF DUTY CYCLE WITH A WIDE 26 ns TO ~ RANGE

1/2 OF 4528B

VDD

0u

10

1/20F 4528B

13

VOO=PIN 16
VSS = PIN 8

PIN NAMES

roa. rob

11a. 11b
CDa.Cob
Qa.Qb

a;;.Qb

Cexta • Cextb
Cext/Rexta. Cext/Rextb

Input (H~L Triggered)
Input (L~H Triggered)
Clear Direct (Active LOW) Input
Output
Compl imentary (Active LOW) Output
External Capacitor Connections
External Capacitor/Resistor Connections

CONNECTION DIAGRAM
DIP (TOP VIEW)
16

15

14

13

12

TRUTH TABLE
10
H.... L

11
L

Co

OPERATION

"

H

Trigger

10

H

L-+H

H

Trigger

X

X

L

Reset

H
L
H-'L
L-+H
X

NOTE:

= HIGH Level
= LOW Level
= HIGH-to-LOW Transition
= LOW-to-HIGH Transition
= Don't Care

The F latpak version has the same
pinouts (Connection Diagram) as the
Dual In-line Package.

7-185

FAIRCHILD CMOS. 45288
OPERATING RULES

Timing
1. An external resistor (R t ) and external capacitor (C t ) are required as shown in the Logic Diagram. The value of R t may vary from 5 kn to
2Mn.
2. The value of Ct may vary from 0 to any necessary value available. If. however, the capacitor has significant leakage relative to V DD/R t the
timing diagrams may not represent the pulse width obtained.
3. Polarized capacitors may be used directly. The (+) terminal of a polarized capacitor is connected to pin 2 (14) and the (-) terminal to pin 1
(15). Pin 2 (14) will remain positive with respect to pin 1 (15).
4. The output pulse width can be determined from the pulse width versus Ct or R t graphs (Figures 1 and 2).
5. To obtain variable pulse width by remote trimming, the following circuit is recommended:

Rt ,"5 kO

PIN21141~-----b
Ct

~t l '

PIN 111510--1

'--

AS CLOSE AS
POSSIBLE TO
OEVICE

VOOO

Rt 2'; 2 Mil - Rt ,

-----

6. Under any operating condition, Ct and R t (min) must be kept as close to the circuit as possible to minimize stray capacitance and reduce

noise pickup.
7. V DD and ground wiring should conform to good high frequency standards so that switching transients on V DO and ground pins do not cause
interaction between one shots. Use of a 0.01 to 0.1 /LF bypass capacitor between V DD and ground located near the 4528B is recommended.
B. To minimize noise problems, it is recommended that pin 1 and pin 15 be tied externally to VSS'

Triggering
1. The minimum negative pulse width into TQ is 32 ns at V DD ~ 10 V and the minimum positive pulse width into 11 is 32 ns at V DD ~ 10 V.
2. When non-retriggerable operation is required, i.e., when input triggers are to be ignored during a quasi-stable state, input latching is used to
inhibit retriggering. The device does not retrigger if an additional trigger input occurs while the capacitor is discharging in response to the
initial trigger input.

Rt

__- __~I~-~~--voo

r-~. .-ll~-vvv---voo

I - - -....-OUTPUT SL

L

..J

OUTPUT

SL

INPUT

INPUT

Co

POSITIVE EDGE·TRIGGER

NEGATIVE EDGE-TRIGGER

co.

3. An overriding active LOW level Clear Direct '(Co) is provided on each multivibrator. By applying a LOW to the
any timing cycle can be
terminated or any new cycle inhibited until the LOW Clear Input is removed. Trigger inputs will not produce spikes in the output when the
Clear Direct Input is held LOW. A new cycle initiated less than 200 ns after removal of a Clear Direct Input
will not have a standard
output pulse width.

(eo>

7·186

FAIRCHILD CMOS. 45288
DC CHARACTERISTICS: V DD as shown, VSS = 0 V (see Note 4)
LIMITS
SYMBOL

PARAMETER

Quiescent
Power
IDD

Supply

XC
XM

Current

V DD = 10V

VDD = 5 V
TYP MAX
MIN

MIN

TYP

MAX

V DD =15V
MIN

TYP

UNITS

TEMP

TEST CONDITIONS

MAX

20

40

80

150

300

600

5

10

20

150

300

600

/LA

MIN. 25°C

Cext/Rext = V DD

MAX

All other inputs

MIN.2~C

/LA

atO V or V DD

MAX

AC CHARACTERISTICS AND SET·UP REQUIREMENTS: VDD as shown, VSS = 0 V, TA = 25°C (See Note 3)
LIMITS
SYMBOL

V DD = 5 V

PARAMETER

tpHL
tpLH
tpHL
tpLH
tpHL

iQ to 0a
Propagation Delay, 10 to

205

335

90

205

335

90

Propagation Delay, 11 to ~
11 to a

205

335

205

335

145

230

60

85

40

68

145

230

60

85

40

68

.
CD to a
Propagation Delay, 0
CDto

tTLH
tTHL

UNITS

MAX

MIN
tpLH

V DD = 15 V

TYP

VDD= 10V
MIN TYP MAX

Output Transition Time

MIN

TYP

MAX

130

60

104

130

60

104

90

130

60

104

90

130

60

104

70

135

32

70

22

45

70

135

"32

70

22

45

ns

ns

ns

CD Recovery Time (Note 1 )

-50

-90

-20

-37

0

-25

ns

twlo

1Q Minimum Pulse Width

(LOW)

70

45

32

24

26

20

ns

twll

11 Minimum Pulse Width (HIGH)

70

45

32

24

26

20

ns

65

45

32

26

26

21

400
Rt - 6 kil, Ct - 16 pF
5.3
4
6.6
8
4
R t = 10 kil, Ct = 1000 pF
±10
±1 I ±7
TA = _40°C to +85°C

150

300

ns

5

6

IJ.S

±1

±5

%

±1

±2

%

Co Minimum Pulse Width

twa

a Minimum Output Pulse Width

twa

a Output Pulse Width

300

I

Change in a Output Pulse Width

M

6.25

4.35

±2

over Temperature
Change in a Output Pulse Width

"t

Co

Set-Up Time,
to 10 or 11
(To prevent change in output)
External Timing Resistor

Rt

±4

±1

Any V DD

20

5

-25
5

External Timing Capacitor

Ct

±2

200 kil, Input Tran·
sition Times';; 20 ns
Rt = 5 kil to 2 Mil
Any Ct

ns

V DD = 5 V ±.25 V V DD = 10 V ±.25 V V DD = 15 V ± 25 V

over V DD

Is

±2

200

500

C L = 50 pF, RL =

ns

tree

twCo

TEST CONDITIONS

-45

-25
2000

No Limits

-35

ns
kil
/L F

Notes;
1.

The 45288 device does not retrigger if an additional trigger Input occurs while the capacitor Is discharging in response to the Initial trigger

input.
2. A new cycle initiated less than 200 ns after removal of a Clear Direct Input (CO) will not have a standard output pulse width.

3. Propagation Delays and Output Transition Times are graphically described in this section under 4000B Series CMOS Family Characteristics.
4. Additional o. C. Characteristics are listed in this section under Fairchild 40008 Series CMOS Familv Characteristics.
5. To minimize power dissipation unused multivibrators should have the Cextl Rext Connection tied to VDO, the Cext Connection tied to
Vss and all other inputs tied to either Voo or VSS.
6. It is recommended that Input Rise and Fall Times to inputs TO and 11 be less than 15.us atVOO "" 5V, 4~s at VOO = 10V and 3 ~sat VOO "" 15V.

7-187

•

FAIRCHILD CMOS. 4528B
TYPICAL ELECTRICAL CHARACTERISTICS
TYPICAL OUTPUT PULSE WIDTH
VERSUS Rt AND Ct
1 Q,OOOK

TYPICAL OUTPUT PULSE WIDTH
VERSUS Rt AND Ct

.---r-'-,.---r--,.----,--,

1000
TA
u.

c

c.

w

(,)

2

;!

~
i:ia:
2

~

"
~
~,
"

15 pF

~

w

~ 1000KI---+-

"

J5O~

VOO = 5 V

CL

I

~

"

U
~

~,

I

..:
(,)

"~
2

100KI--~--~+_-+_+--+_+_­

;::

~/

~

100

1
100

1000

twO - OUTPUT PULSE WIDTH - ms

/

/

1000

FIGURE 2,

AC WAVEFORMS

iQ

WITH 11
OR

fQ

~

twO - OUTPUT PULSE WIDTH - ns

FIGURE 1,

11 WITH

",,,

,,~-;'

/

10

;::

I

"-

ft

100

LOW
(ACTIVE STATE)
HIGH

CD 10 or 11, Recovery Time for
Co Pulse Width.

Set-up Time,
to
EO and Minimum

(INACTIVE STATE)

lo-or

Minimum
I, Pulse Width and Minimum
Output Pulse Width.

NOTE: Set-up Time and RecoveryTime are shown
as Positive values, but may specified as
Negative values.

7-188

10,000

FAI RCHI LD CMOS. 45288
APPLICATIONS

The 45288 Monostable Multivibrator has its pulse width determined by an externally supplied Resistor-Capacitor network. A two step procedure
is suggested for determing the proper RtC t combination (Equation I) for a specific pulse width.
The first step is to choose a capacitor. Figure 1 shows pulse width versus resistor value with the capacitor value as the running parameter. A capacitor value is chosen so that the approximate resistor value is between 20 kil and 2 Mil. Once the capacitor is determined, the timing constant
(K) is found from Figure 3 for a specific VO O' The resistor value is then determined from Equation 2. If the resistor value is less than 20 kn the
timing constant should be increased by 20% and the resistor value re-calculated. The resistor must be larger than 5 kil.

No upper limit on the capacitor is required. If a large value of R t and Ct are to be used the timing between pulses or duty cycle, must be sufficiently low that the capacitor fully charges to V DD . Large capacitor values must be sufficiently low in leakage that the resistor value can supply
the leakage of the capacitor and still charge the capacitor close to V DD.
EXAMPLE:
Three pulse widths of 0.1, 1, and 10 ms are to be generated with the 45288 using a single capacitor.

From Figure 1 a capacitor value between 0.01 and.l uF would be reasonable. A 0.022 "F capacitor is the only capacitor that is available.
The timing constant for a 0.022 "F at 10 V V DD is found from Figure 3 to be approximately 0.3.

The resistor values are then calculated:

Pulse Width
15.1 kil

0.1 ms

151.1 kil

1 ms

10 ms

1.51 Mil

The 15.1 kil is less than 20 kil so add 20% to the K value and recalculate
Pulse Width
12.5 kil

0.1 ms
Equation 1: P.W. = KRtC t
Equation 2: P.W. = Rt

P.W.

Pulse Width (seconds)

K

Timing Constant

Ct

Capacitance (Farads)

Rt

Resistance (ohms)

TIMING CONSTANT VERSUS
TIMING CAPACITANCE
1.0

0.9
0.8

!Z

0.7

:!~

0.6

~

0.5

~

z
~ 0.4
>I

~

TA = 25°C

~

~

~

VOO=15V

,/'

VOD"'5V

:s~

0.3
Voo'" 10 v
0.2
0.1
0.0
0.0001

II
II

I
I

0.001
0.01
0.1
Ct - TIMING CAPACITANCE -t'F

Fig. 3.

7-189

1.0

K = .36

45318
13-INPUT PARITY CHECKER GENER

DESCRIPTION - The 4531B is a 13-lnput Parity Checker/Generator with 13 Parity Inputs (10-112)
and a Parity Output (Z). When the number of Parity Inputs that are HIGH is even, the Output (Z) is
LOW. When the number of Parity Inputs that are HIGH is odd,the Output (Z) is HIGH. For words of
12 bits or less, the Output (Z) can be used to generate either odd or even parity by appropriate
termination of the unused Parity Input (s). For words of 14 or more bits, the devices can be cascaded
by connecting the output (Z) of one device to any Parity Input (10-112) of another device.
When cascading devices, it is recommended that the Output (Z) of one device be connected to the 112
input of the other device since there is less delay to the Output (Z) from the 112 input than from any
other Input (10-111).
•
•
•

LOGIC SYMBOL

7 6 5 4 3 2 1151413121110

VARIABLE WORD LENGTH
FULLY BUFFERED OUTPUT (ACTIVE HIGH)
pARITY INPUTS (ACTIVE HIGH)

PIN NAMES
10-112
Z

FUNCTION
Parity Inputs
Buffered Output
Voo = Pin 16

VSS ~ Pin 8

TRUTH TABLE
INPUTS

OUTPUT

10 11 12 13 14 15 16 17 18 19 110 111 112
All Thirteen
Inputs LOW

Z
L

Any One

Input HIGH

Any Two

Inputs HIGH

L

Any Three

Inputs HIGH

H

Any Four

Inputs HIGH

L

Any Five

Inputs HIGH

H

H

Any Six

Inputs HIGH

L

Any Seven

Inputs HIGH

H

Any Eight

Inputs HIGH

L

Any Nine

Inputs HIGH

H

Any Ten

Inputs HIGH

L

Any Eleven

Inputs HIGH

H

Any Twelve

Inputs HIGH

L

All Thirteen

Inputs HIGH

H

L

= LOW Level

H

~

CONNECTION DIAGRAM
DIP (TOP VIEW)

11

HIGH Level
10

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual In-line Package.

7-190

FAIRCHILD CMOS • 45318
LOGIC DIAGRAM

100
110
12

®

130
14 (])
15
16
17
18
19

0
CD

®
®

@

110@

."~
=.
11
.,-.=1L.)--f - ,'- IL>.-

111@
112 10

IJ

IJ
IJ

]]

@Z

UNITS

TEMP

II

-

II

VSS

= Pin
= Pin

0

= Pin Number

V DO

16
8

DC CHARACTERISTICS: VOO as shown, VSS = 0 V (See Note 1)
LIMITS
SYMBOL

100

PARAMETER
QuieSCent
Power
Supply
Current

VOO = 5 V
MIN TYP MAX

VOO = 10V
MIN TYP MAX

VOO = 15 V
MIN TYP MAX

20
150
5
150

40
300
10
300

80
600
20
600

XC
XM

TEST CONDITIONS

MIN,25"C
MAX
MIN,25"C
MAX

/LA
/LA

All inputs at 0 V
orVOo

AC CHARACTERISTICS: Voo as shown, VSS = 0 V, TA = 25"C (See Note 2)
LIMITS
SYMBOL

tpLH

PARAMETER
Propagation Delay, 10-111 to Z

tpHL
tpLH

Propagation Delay, 112 to Z

tTHL

Voo=10V
MIN TYP MAX

VOo=15V
MIN TYP MAX

Output Transition Time

UNITS

TEST CONOITIONS

195

500

80

225

55

180

195

500

80

225

55

180

ns

C L =50pF,

115

300
300

50

135
135

35

109
109

ns
ns

RL = 200 kn
I nput Transition

75
75

15

45
45

ns

Times .. 20 ns

115

tpHL
tTLH

VOO = 5V
MIN TYP MAX

65
65

135
135

50
35
35

35
15

ns

ns

NOTES:

1- Additional DC Characteristics are listed in this section under 40008 Series CMOS Family Characteristics.
2.

Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.

7-191

45328
8-INPUT PRIORITY ENCODE
DESCRIPTION - The 4532B is an B-Input Priority Encoder with eight active
Priority Inputs
(10-17), three active HIGH Address Outputs (AO-A2), an active HIGH Enable Input (Eln), an active
HIGH Enable Output (EO ut ) and an active HIGH Group Select Output (GS).

LOGIC SYMBOL

Data is accepted on the eight Priority Inputs (10-17). The binary code corresponding to the highest
Priority Input (10-17) which is HIGH is generated on the Address Outputs (AO-A2) if the Enable Input
(Eln) is HIGH. Priority Input 17 is assigned the highest priority. The Group Select output (GS) is
HIGH when one or more Priority Inputs (10-17) and the Enable Input (Eln) are HIGH. The Enable
Output (EO ut ) is HIGH when all the Priority Inputs (10-17) are LOW and the Enable Input (Eln) is
HIGH. The Enable Input (Eln) when LOW, forces all Outputs (AO-A2, GS, EO ut ) LOW.
10 11 12 13 1

2

3

4

45328

•
•

15

ACTIVE HIGH PRIORITY INPUTS
CASCADABLE

9

7

6

14

V DD = Pin 16
VSS = Pin 8

PIN NAMES
10-17
Eln
EOut
GS
AO-A2

Priority Inputs
Enable Input
Enable Output
Group Select Output
Address Outputs

CONNECTION DIAGRAM
DIP (TOP VIEW)

16

15

TRUTH TABLE

14

INPUTS

OUTPUTS

17
X

IS
X

15
X

14
X

13
X

12
X

11
X

10
X

GS

A2

Al

L

L

L

AO
L

EOut

L
H

L

L

L

L

L

L

L

L

L

L

L

L

H

H

H

X

X

X

X

X

X

X

H

H

H

H

L

H

L

H

X

X

X

X

X

X

H

H

H

L

L

H

L

L

H

X

X

X

X

X

H

H

L

H

L

H

L

L

L

H

X

X

X

X

H

H

L

L

L

H

L

L

L

L

H

X

X

X

H

L

H

H

L

H

L

L

L

L

L

H

X

X

H

L

H

L

L

H

L

L

L

L

L

L

H

X

H

L

L

H

L

H

L

L

L

L

L

L

L

H

H

L

L

L

L

Eln

x = Don't Care (Either HIGH or

LOW)

L == L.OW Level
H - HIGH Level

7-192

4

13
12

L
6

11
10

NOTE:
The Flatpak version has the same pinouts (Connection Diagram) as the
Dual InMline Package.

FAIRCHILD CMOS. 45328
LOGIC DIAGRAM

to...

V

"""

-r
_to...

I -""

I

>==L.-/

-

to...

v

~

=D-

- ;:::u

-'"

"....

I -""

.....
....

I -....

to...

........

:u-

_to...

=t./
V

=L)-

l"Y

•

:v

.....

:::u

....

J

-

.....
v

~

J

Jo-

-p..

-

n==rt-'
f--...I..-

r---r= Pin 16
= Pin 8
0= Pin Number

VDD
VSS

7-193

i>

@

GS

@

EOut

FAIRCHILD CMOS. 45328
DC CHARACTERISTICS: VDD as shown, VSS = 0 V (See Note 1)
LIMITS
SYMBOL

PARAMETER
Quiescent
Power

IDD

Supply
Current

VDD = 5 V
MIN

TYP

XC
XM

VDD=10V

MAX

MIN

TYP

VDD = 15 V

MAX

MIN

TYP

20

40

80

150

300

600

5

10

20

150

UNITS

MAX

TEST CONDITIONS

MIN,25°C

IJA

MAX
MIN,25°C

IJA

600

300

TEMP

All inputs at OV
or V DD

MAX

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: V DD as shown, VSS = 0 V, T A = 25°C (See Note 2)
LIMIT
SYMBOL

PARAMETER

MIN
tpLH

Propagation Delay, Eln to EO ut

tpHL
tpLH

Propagation Delay, EI n to GS

tpHL
tpLH

Propagation Delay, E I n to An

tpHL
tpLH

Propagation Delay, I n to An

tpHL

V DD =10V

V DD = 5 V
TYP

MAX

85
85

MIN

TYP

MAX

200

45

200

45

V DD =15V
MIN

TYP

MAX

90

35

70

90

35

70

65

150

35

70

25

56

65

150

35

70

25

56

70

200

35

90

30

70

70

200

35

90

30

70

70

200

35

90

30

70

70

200

35

90

30

70

75

200

40

90

31

70

tpHL

70

200

90

tTLH

65

135

35
35

75

28
15

70
45

65

135

35

75

15

45

tpLH

tTHL

Propagation Delay, I n to GS

Output Transition Time

UNITS TEST CONDITIONS

ns
ns
CL = 50pF,
ns

RL = 200 kn
Input Transition

ns

Times

~

20 ns

ns
ns

NOTES:
1. Additional DC Characteristics are listed in this section under 40008 Series CMOS Family Characteristics.
2. Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristtcs.

7-194

4539B
DUAL 4-INPUT MULTIPLEXER

DESCRIPTION - The 45398 is a Dual 4-lnput Digital Multiplexer with common select logic. Each
multiplexer has four Multiplexer Inputs (10.13). an active LOW Enable Input fE) and a Multiplexer
Output (Z). When HIGH. the Enable Input fE) forces the Multiplexer Output (Z) of the respective
multiplexer LOW. independent of the Select (SO. S1) and Multiplexer (10-13) Inputs. With the Enable
Input fE) LOW. the common Select Inputs (SO. S1) determine which Multiplexer Input (10-13) on
each of the multiplexers is routed to the respective Multiplexer Output (Z).
•
•

LOGIC SYMBOL

6

5

4

3

15

10 11 12 13

14

COMMON SELECT LOGIC
ACTIVE LOW ENABLES

4539B
5t

z,

PIN NAMES
lOa. 11a. 12a. 13a
lab. 11b. 12b. 13b
SO. S1

Ea. Eb
Za. Zb

Multiplexer Inputs
Select Inputs
Enable I nputs (Active LOW)
Multiplexer Outputs

TRUTH TABLE
INPUTS
S1

E

X

H

L

L

L

L

10

H

L

L

11

L

H

L

12

H

H

L

13

=

= Pin

Pin 16
8

CONNECTION DIAGRAM
DIP (TOP VIEW)

OUTPUT

So
X

Voo
VSS

Z

H = HIGH Level
L = LOW Level
X = Don't Care

t6

t5

LOGIC DIAGRAM
t4

t3
t2
It

to

Voo = Pin

16

= Pin

8

VSS

o

= Pin

NOTE:

The F latpak version has the same
pinouts (Connection Diagram) 8S the
Dual I n-Iine Package.

Number

7-195

FAIRCHILD CMOS· 4539B
DC CHARACTERISTICS: VOO as shown, VSS

~

av

(See Note 1)
LIMITS

SYMBOL

PARAMETER

Voo
MIN

Quiescent
Power

100

Supply

~

TYP

XC
XM

Current

VOO~10V

5 V
MAX

MIN

TYP

Voo

MAX

MIN

~

TEMP

UNITS

15 V

TYP

TEST CONOITIONS

MAX

20

40

80

150

300

600

5

10

20

150

300

600

MIN,25°C
IlA

MAX

All inputs at

MIN,25°C

o Vor Voo

IlA

MAX

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VOO as shown, VSS ~ 0 V, TA ~ 25°C (See Note 2)
LIMITS
SYMBOL

PARAMETER

VOO
MIN

tpLH

Propagation Delay, IX to Z

tPHL

~

5 V

TYP

MAX

166
140

VOO~10V

MIN

VOO
MIN

~

TYP

15V

UNITS

TYP

MAX

375

71

160

51

125

350

58

140

40

110

210

470

88

190

62

150

tpHL

210

470

88

190

62

150

tPLH

120

275

53

110

37

85

118

275

51

110

38

85

76

135

39

75

29

45

66

135

30

75

22

45

tpLH

tpHL
tTLH
tTHL

Propagation Delay, Select to Z
Propagation Delay, E to Z

Output Transition Time

TEST CONDITIONS

MAX
ns
ns
ns

CL~50pF,

RL

~

200 kD.

I nput Transition

Times

~

20 ns

ns

NOTES:
1. Additional DC Characteristics are listed in this section under 40008 Series CMOS Family Characteristics.
2. Propagation Delays and Output Transition Times are graphically described in this section under 4000B Series CMOS Family Characteristics.

7-196

45438
BCD TO 7-SEGMENT LATCH/DECODER/DRIV
LIQUID CRYSTAL

DESCRIPTION - The 4543B is a BCD to 7-Segment Latch/Decoder/Driver for Liquid Crystal Displays
with four Address Inputs (A O-A 3 ), a Latch Enable Input (Ell, a Blanking Input (I B ), a Clock Control
Input (CP), and seven Segment Outputs (a-g).

LOGIC SYMBOL
71

oJ24

When the Latch Enable Input (EL) is HIGH, the state of the Segment Outputs (a-g) is determined by
the data on the four Address Inputs (A O-A 3 ) and the Clock Control Input (CP)' For driving Liquid

Crystal Displays, a square wave must be applied to the CP input and to the electrically common
backplane of the display. For common Cathode LED displays a LOW logic level must be applied to the
CP input. For common anode LED displays a HIGH logic level must be applied to the CP input. When
the Latch Enable Input (Ell goes LOW, the last data present at the address Inputs IA O-A 3 ) is stored in
the latches and the Segment Outputs (a-g) remain stable.

CP

4543

A HIGH on the Blanking Input (I B ) forces all Segment Outputs la-g) LOW. The Blanking Input (lB)

does not affect the latch circuit.
•
•
•
•

BLANKING INPUT
MULTIPLEXING CAPABILITY
LCD DISPLAY OR COMMON ANODE OR COMMON CATHODE LED DISPLAY CAPABILITY
BLANKING ON ALL ILLEGAL INPUT COMBINATIONS

9 10 1112 1315 14
~

VDD

PIN 16

VSS ~ PIN 8

PIN NAMES
AO-A3
EL

Address (Oata) Inputs

IB
CP

Blanking Input
Clock Control Input

a-g

Segment Outputs

Latch Enable Input
CONNECTION DIAGRAM
DIP (TOP VIEW)
16

TRUTH TABLE

15

EL

IB

A3

14

OUTPUTS

INPUTS
Cpo

A2

A1

AO

a

c

b

d

e

f

13

DISPLAY

g

12

BLANK

L

X

H

X

X

X

X

L

L

L

L

L

L

H

L

L

L

L

L

H

H

H

H

H

L

H

L

L

L

L

H

L

H

H

L

L

L

H

L

L

L

H

L

H

H

L

H

L

H

L

L

L

H

H

H

H

H

H

L

H

L

L

H

L

L

L

H

H

L

L

H

L

L

H

L

H

H

L

H

H

L

H

L

L

H

H

L

H

L

H

H

H

L

H

L

L

H

H

H

H

H

H

L

L

L

L

7

L

H

L

H

L

L

L

H

H

H

H

H

H

H

8

L

H

L

H

L

L

H

H

H

H

_.H

L

H

H

9

L

H

L

H

L

H

L

L

L

L

L

L

L

L

L

H

L

H

L

H

H

L

L

L

L

L

L

L

BLANK
BLANK·-----

L

H

L

H

H

L

L

L

L...

L

L

L

L

BLANK

L

H

L

H

L
.-

H

H

H
X

-----

L

H

L

H

L

H

L

H

L
H

... ... ...
L

L

X

.---

H

L

L

H

L

L

L

H

L

H

2

L

L

H

3

L

H

H

L

H

H

4
5

H

H

6

-------

'-t:- '1-1

~

-

-.--

0

._--

----

L

L

L

L

L

L

L

BLANK

L

L

L

L

L

L

L

L

BLANK

H

H

L

L

L

L

L

X

X

..

L

L

--

11

'-

1

10

Note: The flatpack version has
the same pinouts (Connection
Diagram) as the Dual In-Line
Package.
--_.-

NUMERICAL DESIGNATIONS

._-

BLANK

.*

Inverse of the above Output Combinations

D isp lay as Above

H = HIGH Level
L = LOW Level
X = Don't Care
• = For Liquid Crystal displays a square wave is applied to CPo For common cathod Light Emitting
Diode displays a LOW logic level is applied to CPo For common anode Light Emitting Diode
displays a HIGH logic level is applied to CPo
•• = Depends upon the BCD Code applied during the HIGH-to-LOW transition of EL.
* * * == The above combinations of logic levels.

7-197

If~(lrJI:wil i~
o'~ __ ~\'

(, !',._..

~_J

:'

__

,0

lie" 171nl til
'.',.0

\'

:).

__ ,'

2345679

~

4555B

•

4556B

DUAL 1-0F-4 DECODERS/DEMULTIPLEXERS
DESCRIPTION - The 45558 and 45568 are Dual 1-of-4 Decoders/Demultiplexers. Each decoder/
demultiplexer has two Address Inputs (AO, A1), an active LOW Enable I nput (E) and four mutually
exclusive Outputs which are active HIGH for the 45558 (00-03) and active LOW for the 45568
(00-0 3)'

LOGIC SYMBOLS

When the 45558 is used as a decoder, the Enable Input (El when HIGH, forces all Outputs (00-03)
LOW. When used as a demultiplexer, the appropriate Output is selected by the Data on the Address
Inputs (AO, A1) and follows as the inverse of the Enable Input (El. All unselected Outputs are LOW.
When the 45568 is used as a decoder, the Enable Input (E) when HIGH forces all Outputs (00-0'3)
HIGH. When used as a demultiplexer, the appropriate Output is selected by the data on the Address
Inputs (AO, A1) and follows the state of the Enable Input (El. All unselected Outputs are HIGH.
•

ACTIVE HIGH OUTPUTS FOR THE 4555B AND
ACTIVE LOW OUTPUTS FOR THE 4556B
OVERRIDING ACTIVE LOW ENABLE

•

2

OR

OR OR

14

15

14

4

00-0 3

13

5

6

OR OR OR

Enable Input (Active LOW)
Address I n puts
Outputs (Active HIGH - 45558 Only)
Outputs (Active LOW - 45568 Only)

AO,A1
00-0 3

2

OR OR

15

12

11

10

13

1/2 OF 4556B

1/2 OF 4555B

PIN NAMES

E

3

OR

7

4

5

6

7

OR OR OR OR

OR

9

12

11

10

9

Voo = Pin 16
VSS = Pin 8

o

= Pin Number

LOGIC DIAGRAMS

112 OF A 45558

(5)OR@
,---8~=:Jo--ot>-- 0 ,

CONNECTION DIAGRAMS
DIP (TOP VIEW)
4555B
16
15

(i)OR@

14

0)OR(5)

0--0t>--

Voo -Pin16
VSS

o

- Pin 8
== Pin Number

13

12

03

11
10

1/2 OF A 4556B

GOR@
r-----;::::::F====FI~o--ol>_____t>o__ 00
(5)OR@
r--i=!::::f=t:=L..Jo--o[>'---t><>-0,
(i)OR@
A, --t>o-+i>O----\-,

4556B
16
15
14

13

12

(i)OR@

11

10

Voo VSS

o

Pin 16

- Pin 8
= Pin Number

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual I n-line Package.

7-198

FAIRCHILD CMOS • 4555B • 4556B

4555B TRUTH TABLE

4556B TRUTH TABLE

E

AO

A1

00

01

02

03

E

AO

A1

00

01

02

L

L

L

H

L

L

L

L

L

L

L

H

H

H

L

H

L

L

H

L

L

H

L

H

L

H

L

H

H

L

L

H

L

L

H

L

L
X

L

L

H

H

H

L

H

L

H

H

L

L

L

H

L

H

H

H

H

H

L

H

X

X

L

L

L

L

H

X

X

H

H

H

H

HIGH Level
LOW Level
Don't Care

=

03

DC CHARACTERISTICS: VDD as shown, VSS ~ 0 V ISee Note 1)
LIMITS
SYMBOL

PARAMETER

VDD
MIN

Quiescent
Power

IDD

Supply
Current

~5

TYP

XC
XM

VDD~10V

V
MAX

MIN

TYP

VDD~15V

MAX

MIN

TYP

UNITS

TEMP

TEST CONDITIONS

MAX

20

40

80

150

300

600

5

10

20

150

300

600

MIN,25°C
fJ.A
fJ.A

MAX

All inputs at

MIN,25°C

OVorVDD

MAX

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VDD as shown, VSS ~ 0 V, TA ~ 25°C, 4555B only ISee Note 2)
LIMITS
SYMBOL

PARAMETER

VDD ~ 5 V
MIN

TYP

VDD = 10 V

MAX

MIN

TYP

MAX

UNITS

VDD = 15 V
MIN

TYP

MAX
116

tPLH

Propagation Delay,

148

285

60

145

40

tpHL

Address to Output

127

265

54

120

45

96

148

315

60

150

40

120

127

295

53

140

40

112

65

135

20

70

25

45

66

135

25

70

20

45

tpLH

-

Propagation Delay, E to Output

tpHL
tTLH
tTHL

Output Transition Time

ns
ns
ns

TEST CONDITIONS

CL~50pF,

RL = 200

kn

I nput Transition

Times'" 20 ns

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VDD as shown, VSS = 0 V, TA = 25°C, 4556B only ISee Note 2)
LIMITS
SYMBOL

PARAMETER

VDD = 5 V

VDD=10V

TYP

MAX

tPLH

Propagation Delay,

140

225

57

tPHL

Address to Output

185

260

68

134

225

55

145

245

MIN

tPLH
tPHL
tTLH
tTHL

Propagation Delay,

E to Output

Output Transition Time

MIN

TYP

UNITS

VDD=15V
TYP

MAX

100

40

80

120

45

96

110

40

88

58

110

40

88

MAX

MIN

75

135

37

70

25

45

77

135

29

70

20

45

ns
ns
ns

TEST CONDITIONS

CL=50pF,
RL = 200

kn

I nput Transition

Times"" 20 ns

NOTES:
1.
2.

Additional DC Characteristics are listed in this section under 4000B Series CMOS FamilY Characteristics.
Propagation Delays and Output Transition Times are graphically described in this section under 4000B Series CMOS Family Characteristics.

7-199

•

FAIRCHILD CMOS. 4555B • 4556B
TYPICAL ELECTRICAL CHARACTERISTICS

4555B
PROPAGATION DELAY,
An TO On,
VERSUS TEMPERATURE

4555B
PROPAGATION DELAY,
TO On,
VERSUS TEMPERATURE

180

20 0
CL '" 15 pF

tpLH. VOO
<40

120

~.;::::;

100

.....- V k

::;.-

"
6'
,

'PHIVOr'1~

80
60

1-

20

=

,per' VDID ~

o

-60

-20

0

20

40

-

~

100

is

80

~
~

--

0

5V,,\

tpLH. Voo

oT~"llic

120

Z 100

o

80

<

60

~

100

5V

o

o

20

\'

40

('\0

80

3

tplH. Von" 15 V
IPHL'! voo

100

120

i

.~

~

;:.V'

~

140

g

100

i3
~
~

P;:: <-

b::::: ;:::::.

/"

VD~: 'O~?

tpHL,
'PCH, VD~

80

- 1O~,

60

"

20
-60

100

i3

80

tpHL. Voo -10V~

f-

20

o

-60

-40 -20

S

40

20

0

20

40

I

/"

V
f..--

0

60

80

100 120 140

/

T A - AMBIENT TEMPERATURE - ' C

60

80

100

120 140

C

En

/
0
tPHL. VDO '"

lPHL_ Voo

Y

20

40

60

80

tpLH. VOO ~ 5V

0

I

10V----;,..

V

120

CL - LOAD CAPACITANCE - pF

7-200

140

160

0

0

/

-:;:::. :::::-- f-

0

~tPL~_ Voo" 15V
100

sv-

0

f..---

"t;HL. Voo" lSV
0

40

/'

- r---

4556B
PROPAGATION DELAY,
TO 0,;,
VERSUS LOAD CAPACITANCE

V

-/

0

tPHL. tpHL. Voo: lSV

-r

tpHL_ Voo = lS~::;::
tplH. Voo = lSV

20

I:-

TA ,,1 25 C

0

0

K-:t::

~

0

lPHL. Voo " S V \

I-

0

tPLIV~

TA - AMBIENT TEMPERATURE -

f.-o;

y

/

:::-;;:::0

=

SV

~

tpHL. Voo ~ 10V

tPLH.VOO~~

~ 40

o

g

35 0

0

''L'tPlH , Voo" 5V

/

V/

tpLH. VOD = 5V

I: - - ::.

V

~

_-

V-

160

45558 AND 4556B
POWER DISSIPATION
VERSUS FREQUENCY

TA - 25 C

E 160

200

,so

TA - AMBIENT TEMPERATURE -

220

g

--

-40

En

,

-

~

tPHL, Voo" 5V~

/"

r--

tpLH. Voo=

C

240

\£200

'""-

V

-

40

4555B
PROPAGATION DELAY,
TO On,
VERSUS LOAD CAPACITANCE

<

V

60

0

100

TA - AMBIENT TEMPERATURE -

g
~

'fVJ l
so

60

.JV

1uJ'120

-I- 1-:tPHL. V~D '~_V::;
-

40

0

;;

I

tPLH. Voo '" 10 V \

,.,-

tplH, Voo " 5V

~ 140

~ tPtL' VOO '" 5V

I

TA = 25"C

220

'8 0

>- V

5V~

240
CL'" lSpf

-

160

0

PROPAGATION DELAY,
An TO On,
VERSUS LOAD CAPACITANCE

En

tpLI+VO D ~

-

tP!",l.VDp",15t~
tplH_ Voo '" lSV
20

40

60

80

100

120

CL -LOAD CAPACITANCE - pF

140

160

45578
I-TO-64 BIT VARIABLE LENGTH SHI FT R[
DESCRIPTION - The 4557B is a 1-to-64 Bit Variable Length Shift Register
Inputs (DA,D B), a Data Select Input (SD)' six Reg~er Length Select Inputs
S32)' active J::OW and active HIGH Clock Inputs (CPO and CP 1 ), True and r.nm"ie,-nent,,,v
puts (0 and 0) and an overriding asynchronous Master Reset Input (MR).

LOGIC SYMBOL

The 4557B register length is programmable. As shown in the Register Selection Table, any shift register
length of between 1 and 64 bits can be selected by applying appropriate logic levels to the Register
Length Select Inputs (S1' S2' S4' S8' S16 and S321. Shift register length equals the sum of the 6-bit
data word formed by the Register Length Select Inputs (S32 S16 S8 S4 S2 S1 ) plus one.
With Data Select Input (SD) LOW, information at the Serial DataJ!:put, DB' is shifted into the Variable
Length Shift Register on either~HIGH-to-LOW transition at CPO while CP 1 is HIGH or a LOW·toHIGH transition at CP 1 while CPO is LOW. With the Data Select Input (SD) HIGH, information at
Serial Data Input 0 A!....is shifted into the register on appropriate logic level transitions and logic levels
at the Clock Inputs (CPO and CP 1 ) as described above.

9

12

13

14 15

1

CP

True and Complementary Data Outputs (0 and (j) from the last stage of the variable length shift
register are made available.
A HIGH on the Master Reset Input (MR) clears all registers to zero (O~LOW, Q~HIGH) independent
of all other inputs.

10

V DD

•
•
•
•
•

1-TO-64 BIT PROGRAMMABLE SHIFT REGISTER
TRUE AND COMPLEMENTARY DATA OUTPUTS AVAILABLE
ASYNCHRONOUS MASTER RESET
TRIGGERS ON EITHER A HIGH-TO-LOW OR LOW-TO-HIGH TRANSITION
SERIAL DATA INPUT FROM EITHER OF TWO SOURCES

VSS

11

Pin 16
Pin 8

CONNECTION DIAGRAM
DIP (TOP VIEW)

PIN NAMES

o

Serial Data Inputs
Data Select Input
Register Length Select Inputs
Clock Input (H~L Triggered)
Clock Input (L~H Triggered)
Master Reset Input
Data Output

0:

Complementary Data (Active LOW) Output

DA,D B
SD
S1,S2,S4,S8,S16,S32

CPo
CP1
MR

16
15
14
13
12
11

10

NOTE:
The flatpak version has the same
(Connection Diagram) as the Dual
In-Line Package.

7-201

FAIRCHILD CMOS • 4557B

REGISTER SELECTION TABLE
SELECT INPUTS

REGISTER LENGTH

S32

S16

S8

S4

S2

L

L

L

L

L

L

1-BITS

L

L

L

L

L

H

2-BITS

L

L

L

L

H

L

3-BITS

L

L

L

L

H

H

4-BITS

L

L

L

H

L

L

5-BITS

L

L

L

H

L

H

6-BITS

S1

H

L

L

L

L

L

33-BITS

H

L

L

L

L

H

34-BITS

H

L

L

L

H

L

35-BITS

H

H

H

H

L

L

61-BITS

H

H

H

H

L

H

62-BITS

H

H

H

H

H

L

63 BITS

H

H

H

H

H

H

64-BITS

L = LOW Level
H == HIGH Level
Note: Shift Register Length equals the sum of the Register Length
Select Input "Word" (S"S2,S4,Sa,S16 and 5 32 ) plus one.

TRUTH TABLE

DATA INPUT SELECTION TABLE
INPUTS

DATA INTO THE FIRST STAGE

INPUT

OF THE SELECTED SHIFT REGISTER

MR

So

DA

DB

L

X

L

L

L

L

X

H

H

L

H

L

X

L

L

H

H

X

H

L

L

L
H
X

=
=
=

LOW Level
HIGH Level
Don't Care

CPo

OPERATION

CP 1

~

NO CHANGE

H

NO CHANGE

H

X

NO CHANGE

X

L

NO CHANGE

H

SELECTED REGISTER SHIFTS

L
~

~

L

L

H

X

~
X

SELECTED REGISTER SHIFTS
MASTER RESET

L = LOW Level
H = HIGH Level

= Don't Care
...r- = Positive-Going Transition
' - == Negative-Going Transition
X

7-202

45828
CARRY LOOKAHEAD GENERATO
DESCRIPTION - The 45828 is a Carry Lookahead Generator which n"",i'~A.,''',,"i'''''' .n.AAn
over word lengths ~ ~re than four bits, The device has a Carry InputJfn1 four
LOW Carry
Generate Inputs (GO-G31, four active LOW Carry Propagate_Inputs (PO-P31, three Carry Outputs
(Cn+x,CQiy,Cn+zl, an active LOW Carry Propagate Output (PI and an active LOW Carry Generate
Output (G). The logic equations for all outputs are shown below.

LOGIC SYMBOL

4

•
•

EXPANDABLE TO ANY NUMBER OF BITS
HIGH SPEED LOOKAHEAD OVER WORD
LENGTHS OF MORE THAN FOUR BITS

3

2

1 15 14 6

5

10
13

12

11

PIN NAMES

Cn
GO-G3
1>0-1>3
~n+x,Cn+y,Cn+z
G

P

Carry
Carry
Carry
Carry
Carry
Carry

Input
Generate I nputs (Active LOW)

Propagate Inputs (Active LOW)
Outputs
Generate Output (Active LOW)
Propagate Output (Active LOW)

VDD:::= Pin 16

VSS == Pin 8

LOGIC EQUATIONS
Cn + x

=

GO + Po - Cn

•

CONNECTION DIAGRAM
DIP (TOP VIEW)

Cn+y = G1 + P1 - GO + P1 • Po . Cn
Cn + z = G2 + P2 • G1 + P2 • P1 . GO + P2 • P, . Po • Cn

G = G3 + P3 • G2 + P3 - P2 • G, + P3 . P2 - P, . GO

I> = P3 • P2 - P, . Po
16
15

LOGIC DIAGRAM

14
4

13

6

11

12

10

NOTE:
The F latpak version has the same

VDO = Pin '6
VSS = Pin 8

o

outs (Connection Diagram)
Dual I n·line Package.

= Pin Numbers

7-203

pin~

as the

FAIRCHILD CMOS. 45828

TRUTH TABLE
INPUTS

Cn

GO

Po

X

H

H

G1

P1

OUTPUTS

P2

G2

P3

G3

Cn+x

Cn+y

Cn +z

G

P

L

L

H

X

L

X

L

X

H

H

X

L

X

X

X

H

H

L

X

H

H

H

X

L

L

H

X

H

X

L

X

X

X

L

X

H

X

L

X

X

L

H

H

X

L

X

L

H

X

X

X

X

X

H

H

L

X

X

X

H

H

H

X

L

X

H

H

H

X

H

X

L

L

H

X

H

X

H

X

L

X

X

X

X

X

L

X

H

X

X

X

L

X

X

L

H

X

L

X

X

L

X

L

H

H

X

L

X

L

X

L

H

X

X

X

X

X

H

H

H

X

X

X

H

H

H

X

H

X

H

H

H

X

H

X

H

H

H

X

H

X

H

X

H

X

X

X

X

X

L

X

L

X

X

X

L

X

X

L

L

X

L

X

X

L

X

L

L

L

X

L

X

L

X

L

L

H

H

X

X

X

H

X

H

X

X

H

X

X

H

X

H

X

X

X

H

H

L

L

L

L

L

H

=

HIGH Voltage Level

L = LOW Voltage Level

X = Don't Care

7-204

FAIRCHILD CMOS. 45828
DC CHARACTERISTICS: VOO as shown, VSS = 0 V (See Note 1)
LIMITS
SYMBOL

PARAMETER
Quiescent

Power

100

Supply
Current

VDD=10V

VDD = 5 V
MIN

TYP

XC
XM

MAX

MIN

TYP

VDO = 15 V

MAX

MIN

TYP

MAX

20

40

80

150

300

600

5

10

20

150

300

600

TEMP

UNITS

TEST CONDITIONS

MIN,25°C

IlA

MAX
MIN,25°C

IlA

All inputs at 0 V or
V OD

MAX

AC CHARACTERISTICS AND SET·UP REQUIREMENTS: V DD as shown, VSS = 0 V, TA = 25°C (See Note 2)
LIMITS
SYMBOL

PARAMETER

V DD = 5 V
MIN

TYP

MAX

VOO=10V
MIN

TYP

MAX

V DO =15V
MIN

TYP

tpLH

Propagation Delay, Cn to C n+ x '

160

75

55

tpHL

Cn+ v or Cn+ z
Propagation Delay, Pn to Cn+ x
Cn+y or Cn+ z

160

75

55

160

75

55

160

75

55

tpLH

Propagation Delay, "G n to Cn+ x '

160

75

55

tpHL

Cn+ v or Cn+ z
Propagation Delay, Pn to G
toG

160

75

55

160

75

55

160

75

55

Propagation Delay, Gn to G

160

75

55

tpLH
tpHL

tpLH
tpHL
tpLH
tpHL
tpLH

Propagation Delay, Pn to Ii

tpHL
tTLH
tTHL

Output Transition Time

160

75

55

160

75

55

160

75

55

60

30

20

60

30

20

UNITS

TEST CONDITIONS

MAX
ns
ns
ns

CL = 50 pF,
RL = 200 kn

ns

I nput Transition

Times

~

20 ns

ns
ns
ns

NOTES:
1. Additional DC Characteristics are listed in this section under 40008 Series CMOS Family Characteristics.
2. Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.

7·205

•

4702B/4702BX
PROGRAMMABLE BIT-RATE GENERATOR
FAIRCHILD CMOS MACROLOGICTM

DESCRIPTION -

The 4702Bi4702BX Bit-Rate Generator provides the necessary clock signals for

LOGIC SYMBOL

digital data transmission systems, such as Universal Asynchronous Receiver and Transmitter circuits
(UARTs). It generates any of the 14 commonly used bit rates using an on-chip crystal oscillator, but
its design also provides for easy and economical multi-channel operation, where any of the possible

frequencies must be made available on any output channel.

15 14131211

One 4702Bi4702BX can control up to eight output channels. When more than one bit-rate generator

is required, they can still be operated from one crystal. The 47028 is specified to operate over a power
supply voltage range of 5 V ± 10%. The 4702BX is a specially selected device specified to operate over
a power supply voltage range of 4.5 V to 12.5 V.

•
•
•

PROVIDES 14 COMMONLY USED BIT-RATES
ONE 4702Bi4702BX CONTROLS UP TO EIGHT TRANSMISSION CHANNELS
USES 2.4576 MHz INPUT FOR STANDARD FREQUENCY OUTPUTS
(16 TIMES BIT RATE)

•
•
•
•
•
•

CONFORMS TO EIA RS-404
ON-CHIP INPUT PULL UP CIRCUITS
TTL COMPATIBLE-OUTPUTS WILL SINK 1.6 rnA
INITIALIZATION CIRCUIT FACILITIES DIAGNOSTIC FAULT ISOLATION
LOW POWER DISSIPATION - 1.35 rnA POWER DISSIPATION AT 5 V AND 2.4576 MHz
16-PIN DUAL IN-LINE PACKAGE

9

VDD

1 2 3

:=

10

Pin 16

VSS == Pin

8

CONNECTION DIAGRAM
DIP (TOP VIEW)

TABLE 1
CLOCK MOOES AND INITIALIZATION
IX

E'CP

CP

J1JlJU'

H

L

Clocked from I X

X

L

Jl.S1.S1..j

Clocked from CP

X

H

H

Continuous Reset

X

L

Note 1:

~

16

H = HIGH Level
L = LOW Level

OPERATION

15

X = Don't Care

_SL =

1st HIGH Level

14

Clock Pulse
After ECp Goes

13

LOW

Reset During First CP = HIGH Time

JLf1...JL.J

12

Clock Pulses

11

Actual output frequency is 16 times the 'indicated output rate, assuming a clock

10

frequency of 2.4576 MHz.
TABLE 2
TRUTH TABLE FOR RATE SELECT INPUTS

So

Output Rate (Z)
Note 1

L

L

Multiplexed Input (1M)

L

H

Multiplexed Input (1M)

L

H

L

L

L

H

H

75 Baud

L

H

L

L

134.5 Baud

L

H

L

H

200 Baud

L

H

H

L

600 Baud

S3

S2

5,

L

L

L

L

L

50 Baud

L

H

H

H

2400 Baud

H

L

L

L

9600 Baud

H

L

L

H

4800 Baud

H

L

H

L

1800 Baud

H

L

H

H

1200 Baud

H

H

L

L

2400 Baud

H

H

L

H

300 Baud

H

H

H

L

150 Baud

H

H

H

H

NOTE:
The F latpak version has the same pinouts (Connection Diagram) as the
Dual In-line Package_

110 Baud

PIN NAMES

CP
E'CP
IX
1M
SO-53
CO

L = LOW Level
H = HIGH Level

7-206'

External Clock Input
External Clock Enable
Input (Active LOW)
Crystal Input
Multiplexed Input
Rate Select Inputs
Clock Output
Crystal Drive Output

Ox
00-Q2

Scan Counter Outputs

Z

Bit Rate Output

FAIRCHILD CMOS • 4702B/4702BX
BLOCK DIAGRAM

I

I

l~:~ !,.11I!!>' ,I

1 [>0

o
o

ECp
CP

I I
I

i--';:---;:=~
I....
I

I

!I

IT
CP

CP -4

I

o~:-

ICp +6
MR
I

I
I
I

IMR

I

ICp 7 16/3
I
MR

I
I

"'71'"
CO

0 0 0 , O2

0

000

Y

I

I

I
I

ICp 7 22

I"

Voo = Pin 16

o

~

I

:i

11 1200

1-

9 4800
10 ;800

12 2400
13 300
14 150

~H-I

MR

7 2400

15 110

Y :

I
I

L ________________

VSS

8 9600

I
I
I
I
I

I
I
I

6 600

I
I
I
I
I
I

~r+I

I
I

: INITIALIZATION
:
L _ _C.!!l~!!. _ _ _ _ _ _ _ _ ..J

I
I

75
3
4 134.5
5 200

Pin B

= Pin Number

7-207

I

~

I
I
I
I
I
I

2 50

y

I
I
I
I

:

1

I--

rICP718 MR

I

1n1

tU

MR

0

"K

I
I
I
I

I
I

0

rl

I
I

t,- ,,- ,-

I 1M 50 51 52 53

'

78

_______

I

r:- ~?CP

:
!

i

:

i
~

@
I.

DFFO~ Z

FAIRCHILD CMOS • 4702B/4702BX
FUNCTIONAL DESCR IPTION - Digital data transmission systems employ a wide range of standardized bit rates, ranging
from 50 baud interfacing with electromechanical devices, to 9600 baud for high speed modems. Modern electronic systems
commonly use Universal Asynchronous Receiver and Transmitter circuits (UARTs) to convert parallel data inputs into a
serial bit stream (transmitter) and to reconvert the serial bit stream into parallel outputs (receiver). In order to resynchronize
the incoming serial data, the receiver requires a clock rate that is a multiple of the incoming bit rate. Popular MaS-LSI UART
circuits use a clock that is 16 times the transmitted bit rate. The 4702B/4702BX can generate 14 standardized clock rates
from one commonly high frequency input.
The 4702B/4702BX contains the following five functional subsystems which are discussed in detail below:
1.
2.
3.
4.
5.

An Oscillator Circuit with associated gating.
A prescaler used as Scan Counter for multicr.annel operation (described in the applications section).
A Counter Network to generate the required standardized frequencies.
An output MUltiplexer (frequency selector) with resynchronizing output flip-flop.
An Initialization (reset) Circuit.

Oscillator - For conventional operation generating 16 output clock pulses per bit period, the input clock frequency must be
2.4576 MHz (i.~. 9600 baud x 16 x 16, since the scan counter and the first flip-flop of the counter chain act as an internal 7
16 prescaler). A lower input frequency will obviously result in a proportionally lower output frequency.
The 4702B/4702BX can be driven from two alternate clock sources: (1) When the ECp (active LOW External Clock Enable)
input is LOW, the CP input is the clock source. (2) When the ECp input is HIGH, a crystal connected between IX and OX, or
a signal applied to the IX input, is the clock source.
Prescaler (Scan Counter} - The clock frequency is made available on the CO (Clock Output) pin and is applied to the 7 8
prescaler with buffered outputs 00, 01' and 02' This prescaler is of no particular advantage in single frequency applications,
but it is essential for the simple economical multichannel scheme described in the Applications section of this data book.
Counter Network - The prescaler output 02 is a square wave of 1/8 the input frequency and is used to drive the frequency
counter network generating 13 standardized frequencies. Note that the frequencies are labeled in the block diagram and
described in terms of the transmission bit rate. In a conventional system using a 2.4576 MHz clock input, the actual output
frequencies are 16 times higher.
The output from the first frequency divider flip-flop is thus labeled 9600, since it is used to transmit or receive 9600 baud
(bits per second). The actual frequency at this node is 16 x 9.6 kHz = 153.6 kHz. Seven more cascaded binaries generate the
appropriate frequencies for bit rates 4800, 2400, 1200,600,300, 150, and 75.
The other five bit rates are generated by individual counters:
bit rate 1200 is divided by 6 to generate bit rate 200,
bit rate 200 is divided by 4 to generate bit rate 50,
bit rate 2400 is divided by 18 to generate bit rate 134.5 with a frequency error of -0.87%,
bit rate 2400 is also divided by 22 to generate bit rate 110 with a frequency error of -0.83%, and
bit rate 9600 is divided by 16/3 to generate bit rate 1800.
The 16/3 division is accomplished by alternating the divide ratio between 5 (twice) and 6 (once). The result is an exact average output frequency with some frequency modulation. Taking advantage of the 716 feature of the UART, the resulting
distortion is less than 0.78%, irrespective of the number of elements in a character, and therefore well within the timing
accuracy specified for high speed communications equipment. All signals except 1800, have a 50% duty cycle.
Output Multiplexer - The outputs of the counter network are fed to a 16-input multiplexer, which is controlled by the Rate
Select inputs (SO-S3)' The multiplexer output is then resynchronized with the incoming clock in order to cancel all cumulative delays and to present an output signal at the buffered output (Z) that is synchronous with the prescaler ouwuts (00-02)'
Table 2 lists the correspondence between select code and output bit rate. Two of the 16 codes do not select an internally
generated frequency, but select an input into which the user can feed either a different, nonstandardized frequency, or a
static level (H IGH or LOW) to generate "zero baud".
The bit rates most commonly used in modern data terminals (110, 150, 300, 1200, 2400 baud) require that no more than
one input be grounded, easily achieved with a single pole, 5-position switch. 2400 baud is selected by two different codes, so
that the whole spectrum of modern digital communication rates has a common HIGH on the S3 input.
Initialization (Reset) - The initialization circuit generates a common master reset signal for all flip-flops in the 4702B/4702BX.
This signal is derived from a digital differentiator that senses the first HIGH level on the CP input after the ECp input goes
LOW. When ECp is HIGH, selecting the Crystal input,SP must be LOW. A HIGH level on CP would apply a continuous reset.
All inputs to the 4702B/4702BX, except IX have on-chip pull-up circuits which improve TTL compatibility and eliminate the
need to tie a permanently HIGH input to VDD.

7-208

FAIRCHILD CMOS .4702B/4702BX
DC CHARACTERISTICS: VDD = 5 V, VSS = 0 V (Note 1)

SYMBOL

LIMITS

PARAMETER
MIN

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

VOH

TYP

UNITS

3.5
1.5
4.95
4.95
4.5

Output HIGH Voltage

I nput LOW Current
IL
(See
Note 1)

IIH

0.05
0.5
XC

O.~

XM

1
0.1
1

for Input IX

I nput LOW Current
for all Other Inputs
Input HIGH Current
for all Inputs

XC
XM

-15
-15

-30
-30

-100
-100

XC

0.3

XM

1
0.1
1

IOH

10L

Output HIGH Current
for Output Ox

-0.3
-0.1

Output HI G H Current
for all other Outputs

-1.5
-1
0.5
-0.3

All

Guaranteed Input High Voltage

All

Guaranteed I nput LOW Voltage

V
V
p.A
p.A
p.A
p.A
p.A
mA

All
MIN,250C
MAX
MIN,250C
MAX

10 L

< 1 p.A,

I nputs at 1.5 or 3.5 V

Pin under Test at 0 V
All other Inputs Simultaneously
at 5 V

25°C
MIN,250C
MAX
MIN,250C
MAX

Pin Under Test at 5 V
All other I nputs Simultaneously
at 0 V

MIN,250C

= 2.5

V

mA

VOUT

= 4.5

V

MIN,250C
MAX

MAX
MIN,250C

MIN,250C

7·209

Inputs at 1.5 or 3.5 V

VOUT

mA

See Notes on following page.

< 1 p.A,
<

MAX

3.2
1.6
100
1000
10
150

IOH

IOL
1 p.A, Inputs at 0 or 5 V per
the Logic Function or Truth Table

MIN,25 u C
MAX

mA

Output LOW Current
for all Other Outputs

XM

MIN. 25°C
MAX

<

IOH
1 p.A. Inputs at 0 or 5 V per
the Logic Function or Truth Table

V

mA

Supply Current

MAX
All

= 4.5

0.2
0.1

XC

MIN,250C

VOUT

Output LOW Current
for Output Ox

Quiescent Power

100

V

V

Output LOW Voltage

TEST CONDITIONS

V
V

0.05
VOL

TEMP

MAX

p.A
p.A

Inputs at 0 or 5 V
per Logic
Function or
Truth Table

VOUT

= 0.4

V

MAX
MIN,250C
MAX
MIN,250C
MAX

ECp = VDD, CP = 0 V,
All other I nputs at 0 V
or VDO (Note 6)

•

FAIRCHILD CMOS. 4702B/4702BX
AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VDD ~ 5 V, VSS ~
SYMBOL

PARAMETER

TEST CONDITIONS

TYP

MAX

tpLH

Propagation Delay

175

350

tpHL

IX to CO

135

275

tpLH

Propagation Delay

130

260

tPHl,

CP to CO

110

220

tpLH

53

tpHL

Propagation Delay
CO to Q-n

45

Note
5

tpLH

Propagation Delay

37

85

tpHL

CO to Z

32

75

tTLH

Output Transition

80

160

35

75

Time (Except OX)

ts

Set-Up Time, Select to CO

th

Hold Time, Select to CO

ts

Set-Up Time, 1M to CO

th

Hold Time, 1M to CO

twCP(L)

Minimum Clock Pulse Width

25°C

LIMITS
MIN

tTHL

a V, TA ~

350

UNITS
ns
ns
ns
ns

-182
190

0

-182

120

60

~

50 pF,

~

200 kn

Input Transition

ns

Times';:;';; 20 ns

CL <; 7 pF on Ox

185

350

CL
RL

ns
ns

twCP(H)

LOW and HIGH

120

60

ns

twIX(L)

Minimum IX Pulse Width

160

twIX(H)

LOW and HIGH

160

75
75

ns

NOTES:

1. Propagation Delays and Output Transition Times are graphically described under 4000B Series CMOS Family Characteristics.
2. The first HIGH level Clock Pulse after E'CP goes LOW must be at least 350 ns long to guarantee reset of all Counters.
3. It is recommended that input rise and fall times to the Clock Inputs (CP, IX) be less than 15!Js at VDD ~ 5 V, 4!Js at VDD ~ 10 V, and 3!Js
at VDD ~ 15 V, and the VDD pin should be decoupled.

4.

Input current and quiescent power supply current are relatively higher for this device because of active pull-up circuits on all inputs
except I X. This is done for TTL compatibility.

5.

For multichannel operation, propagation delay CO to an, plus set-up time, select to CO, is guaranteed to

6.

I DO is measured on Pin 8 and does not include I nput Leakage Currents.

I

:0.;;;

367 ns.

SWITCHING WAVEFORMS

CP/I X

MINIMUM CP AND IX PULSE WIDTHS AND SET-UP AND HOLD TIMES,
SELECT INPUT (Sn) TO CLOCK OUTPUT (CO) AND 1M INPUT TO CLOCK OUTPUT (CO)
NOTE: Set-up and Hold Times are shown as positive values but may be specified as negative values.

7-210

FAIRCHILD CMOS. 4702B/4702BX
APP LI CA TI ONS
Single Channel Bit Rate Generator - Figure 1 shows the simplest application of the 4702B/4702BX. This circuit generates
one of five possible bit rates as determined by the setting of a single pole, 5·position switch. The bit rate output (Z) drives one
standard TTL load or four low power Schottky loads over the full temperature range. The possible output frequencies correspond to 110, 150,300, 1200, and 2400 Baud. For many low cost terminals these five bit rates are adequate.
Simultaneous Generation of Several Bit Rates:
Fixed Programmed Multichannel Operation - Figure 2 shows a simple scheme that generates eight bit rates on eight output

lines, using one 4702B/4702BX and one 93L34 8·Bit Addressable Latch. This and the following applications take advantage
of the built·in scan counter (prescaler) outputs. As shown in the block diagram, these outputs (QO to Q2) go through a com·
plete sequence of eight states for every half·period of the highest output frequency (9600 Baud). Feeding these Scan Counter
outputs back to the Select inputs of the multiplexer causes the 4702B/4702BX to interrogate sequentially the state of eight
different frequency signals. The 93L34 8·Bit Addressable Latch, addressed by the same Scan Counter outputs, reconverts the
multiplexed single output (Z) of the 4702B/4702BX into eight parallel output frequency signals. In the simple scheme of
Figure 2, input S3 is left open (H IGH) and the following bit rates are generated:
110Baud,

Q1:

9600 Baud,

Q2:

4800 Baud,

1200 Baud,

Q5:

2400 Baud,

Q6:

300 Baud,

Q3 :
Q7:

1800 Baud,
150 Baud.

Other bit rate combinations can be generated by changing the Scan Counter to selector interconnection or by inserting logic
gates into th is path.
FullV Programmable Multichannel Operation - Figure 3 shows a fully programmable 8·channel bit rate generator system that,

under computer control, generates arbitrarily assigned bit rates on all eight outputs simultaneously. The basic operation is
similar to the previously described fixed programmed system, but two 9LS170 4 x 4 Register File MSI packages are
connected as programmable look-up tables between the Scan Counter outputs (QO to Q2) and the multiplexer Select inputs
(SO to S3). The content of this 8-word by 4-bit memory determines which frequency appears at what output.
19200 Baud Operation - Though a 19200 Baud signal is not internally routed to the multiplexer, the 4702B/4702BX can be
used to generate this bit rate by connecting the Q2 output to the 1M input and applying select code 0 or 1. An additional
2-input NAND gate can be used to retain the "Zero Baud" feature on select code O. Any multichannel operation that involves
19200 Baud must be limited to four outputs as shown in Figure 4_ Only the two least significant Scan Counter outputs are
used, so that the scan is completed within one half period of the 19200 output frequency.

Clock Expansion - One 4702B/4702BX can control up to eight output channels. For more than eight channels, additional
bit rate generators are required. These bit rate generators can all be run from the same crystal or clock input. Figure 5 shows
one possible expansion scheme. One 4702B/4702BX is provided with a crystal. All other devices derive their clock from this
master. Figure 6 shows a different scheme where the master clock output feeds into the IX input of all slaves and all ECp
inputs are normally held HIGH. This scheme retains the reset feature and the selection between two different clock sources of
the basic 4702B/4702BX circuit.
During normal operation, the common ECp line is HIGH and the common clock line (CP) is LOW. For diagnostic purposes
the common ECp is forced LOW. This deselects the crystal frequency and initiates the diagnostic mode. When CP goes HIGH
for the first time, all 4702B/4702BXs are reset through their individual on-chip initialization circuitry. Subsequent LOW-toHIGH clock transitions on the common CP line advance the scan counter, causing all 4702B/4702BXs to operate synchronously.
TYPICAL APPLICATIONS

SWITCH POSITION

BIT RATE

110 Baud
150 Baud

300 Baud
1200 Baud
2400 Baud

Fig. 2

Fig. 1

BIT RATE GENERATOR CONFIGURATION
WITH EIGHT SIMULTANEOUS FREQUENCIES

SWITCH SELECTABLE BIT RATE GENERATOR
CONFIGURATION PROVIDING FIVE BIT RATES

7-211

•

FAIRCHILD CMOS. 4702B/4702BX
TYPICAL APPLICATIONS (Cont'd)

I
~CpIM
56pF

~PF
LAo

RE
9LS170

'--

A1

00 °1 0203

III

-=-

--0 Ecp

~~10....L
MU c:J
'T

So S1 S2 S3
4702B/4702BX

'- IX
Ox
co ° 0 ° 1 ° 2

r

2c'lN~'1'1z

~o"

CHANNEL 6
°7
°6

CHANNEL5
CHANNEL 4

Os

~LSOO

L-

Z

D

CHANNEL 3

°4
93L34 03

E

°2
°1

CHANNEL 2
CHANNEL 1
CHANNELO
CHANNEL 7

00
CL
AO A1 A2

RE

LAO

9LS170

'----

A1

III

JI

J

00 ° 1 ° 2 ° 3

l<>-

LFig. 3

FULLY PROGRAMMABLE 8-CHANNEL BIT RATE GENERATOR SYSTEM

1/40FA
9LSOO

J

.0

56pF

~PF

1M So S1 S2 S3
2.4576 MHz
CP
CRYSTAL -----4..p.~U'..:G
Voo

VSS

= Pin 24
= Pin 12

o=

@@@@

Pin Numbers

FUNCTIONAL DESCRIPTION - As shown in the block diagram the 4703B/4703BX consists of three sections:

1. An Input Register with parallel and serial data inputs as well as control inputs and outputs for input handshaking and
expansion.
2. A 4·bit wide, 14·word deep fall·through stack with self·contained control logic.
3. An Output Register with parallel and serial data outputs as well as control inputs and outputs for output handshaking and
expansion.
Since these three sections operate asynchronously and almost independently, they will be described separately below:

Input Register (Data Entry):
The Input Register can receive data in either bit·serial or in 4·bit parallel form. It stores this data until it is sent to the fall·
through stack and generates the necessary status and control signals.

Figure 1 is a conceptual logic diagram of the input section, as described later, this 5·bit register is initialized by setting the F3
flip·flop and resetting the other flip·flops. The Q·output of the last flip·flop (FC) is brought out as the "Input Register Full"
output (IRF). After initialization this output is HIGH.
Parallel Entry - A HIGH on the PL input loads the 00-03 inputs into the FO-F3 flip·flops and sets the FC flip·flop. This
forces the IRFoutput LOW indicating that the input register is full. During parallel entry, the CPSI input must be LOW. If
parallel expansion is not being implemented, IES must be LOW to establish row mastership (see Expansion section). The
00-03 inputs are "ones catching" and must remain stable while PL is HIGH.

7·215

FAIRCHILD CMOS • 4703B/4703BX
I

, . . - - 0 3 - - - - - - - - - I N P U O T 2D A T A - - - - O , - - - - - - O ' O

PL--~~----------------_+~--------1_~--------~r_--------,

INITIALIZE --li-----~----....,

°s-~--I

~--=====~==~[=;~t------------t_--------_1----------_t-'

CPSI

Fig. 1
CONCEPTUAL INPUT SECTION

Serial Entry - Data on the DS input is serially entered into the F3, F2, Fl, FO, FC shift register on each HIGH·to-LOW transition of the CPSI clock input, provided IES and PL are LOW.
After the fourth clock transition, the four data bits located in the four flip-flops FO-F3' The FC flip-flop is set, forcing the
IRF output LOW and internally inhibiting CPSI clock pulses from effecting the register. Figure 2 illustrates the final positions
in a 4703B/4703BX resulting from a 64-bit serial bit train. BO is the first bit, B63 the last bit.
Transfer to the Stack - The outputs of Flip·Flops FO-F3 feed the stack. A LOW level on the TTS input initiates a "fallthrough" action. If the top location of the stack is empty, data is loaded into the stack and the input register is re-initialized.
Note that this initialization is postponed until PL is LOW again. Thus, automatic FIFO action is achieved by connecting the
i1iF" output to the TTS input.
An RS Flip-Flop (the Request Initialization Flip-Flop shown in Figure 10) in the control section records the fact that data
has been transferred to the stack. This prevents mUltiple entry of the same word into the stack despite the fact the TRF and
TTS may still be LOW. The Request Initialization Flip-Flop is not cleared until PL goes LOW. Once in the stack, data falls
through the stack automatically, pausing only when it is necessary to wait for an empty next location. In the 4703B/4703BX,
as in most modern FIFO designs, the MR input only initializes the stack control section and does not clear the data.

INPUT

R.§§.I§.T..!=!! __ ~ ___

~

_____ _

4703B,'4703BX

OUTPUT
REGISTER

Fig. 2
FINAL POSITIONS IN A 4703B/4703BX RESULTING
FROM A 64-BIT SERIAL TRAIN

7-216

FAIRCHILD CMOS • 4703B/4703BX
Output Register (Data Extraction) - The Output Register receives 4-bit data words from the bottom stack location, stores it
and outputs data on a 3-state 4-bit parallel data bus or on a 3-state serial data bus. The output section generates and receives
the necessary status and control signals. Figure 3 is a conceptual logic diagram of the output section.

, - - - - - - - - - O U T P U T FROM S T A C K - - - - - - - - ,

LOAD FADM STACK

0Es--",-_

MR-~,-~>---~----~----------~~----------~--------~----~

T O ' - -......._

~--qc>_--~--~~r----_,~_t----~-_r---_.

Fig. ~
CONCEPTUAL OUTPUT SECTION

Parallel Data Extraction - When the FIFO is empty after a LOW pulse is applied to MR, the Output Register Empty (~)
output is LOW. After data has been entered into the FIFO and has fallen through to the bottom stack location, it is transferred into the Output Register provided the "Transfer Out Parallel" (TOP) input is HIGH. As a result of the data transfer
ORE goes HIGH, indicating valid data on the data outputs (provided the 3-state buffer is enabled). TOP can now be used to
clock out the next word. When TOP goes LOW, ORE will go LOW indicating that the output data has been extracted, but the
data itself remains on the output bus until the next HIGH level at TOP permits the transfer of the next word (if available)
into the Output Register. During par.allel data extraction CPSO should be LOW. TOS should be grounded for single slice oper·
ation or connected to the appropriate 0 RE for expanded operation {see Expansion section l.
TOP is not edge triggered. Therefore, if TOP goes HIGH before data is available from the stack, but data does become avail·
able before TOP goes LOW again, that data will be transferred into the Output Register. However, internal control circuitry
prevents the same data from being transferred twice. If TOP goes HIGH and returns to LOW before data is available from
the stack, ORE remains LOW indicating that there is no valid data at the outputs.
Serial Data Extraction - When the FIFO is empty after a LOW pulse is applied to MR, the Output Register Empty (ORE) out·
put is LOW. After data has been entered into the FIFO and has fallen through to the bottom stack location, it is transferred
into the Output Register provided TOS is LOW and TOP is HIGH. As a result of the data transfer ORE goes HIGH indicating
valid data in the register. The 3·state ·Serial Data Output, aS, is automatically enabled and puts the first data bit on the out·
put bus. Data is serially shifted out on the HIGH·to·LOW transition of CPSO. To prevent false shifting, CPSO should be LOW
when the new word is being loaded into the Output Register. The fourth transition empties the shift register, forces ORE out·
put LOW and disables the serial output, aS (refer to Figure 3). For serial operation the ORE output may be tied to the TOS
input, requesting a new word from the stack as soon as the previous one has been shifted out.

7·217

•

FAIRCHILD CMOS • 4703B/4703BX
EXPANSION
Vertical Expansion - The 47038/47038X may be vertically expanded to store more words without external parts. The
interconnections necessary to form a 46-word by 4-bit FIFO are shown in Figure 4. Using the same technique, any FIFO of
(15n + 1) words by four bits can be constructed, where n is the number of devices. Note that expansion does not sacrifice any
of the 47038/47038)('s flexibility for serial/parallel input and output. For other expansion schemes, refer to the Applications section of th is book.

PARALLE
MASTER

PARALLEL
LOAD

RESET

1 DATA IN

I
D3 D2 01

I

DO

SERIAL DATA IN

-<

PL
TTS

Os

D3 D2 01

DO

IES
CPSI

SERIAL INPuT CLOCK

OES

r----<
0-

0--

°2 °1 °0 Os

Q3

N1C

PL
TTS
IES

Os

CPSI
OES
TOS

D3 D2 D1

DO
IRF

0--

ORE

0--

4703Bi4703BX

TOP
CPSG
EO
MR

°2

Q3

Q1

°0

'f

-<

ORE

4703B,'4703BX

'f

r-;::::

0--

TOS
TOP

CPSQ
EO
MR

L-<:

IRF

Qs

Jc

PL Os D3 02 D1 DO
TTS
IES

I RF

0--

CPSI
OES

4703Bi4703BX

-< ros

DUMP

TOP

SERIAL OUTPUT CLOCK
OUTPUT ENABLE

CPSO

ORE

DATA VALID

EO

MR °3 °2 °1 00 Os

I

SERIAL
DATA OUT

°3 °2 0 1 °0

-=

I
I

I

PARALLEL DATA OUT

Fig.4
A VERTICAL EXPANSION SCHEME

7-218

FAIRCHILD CMOS • 4703B/4703BX
Horizontal Expansion - The 4703B/4703BX can also be horizontally expanded to store long words (in multiples of four bits)
without external logic. The interconnections necessary to form a 16-word by 12-bit FIFO are shown in Figure 5. Using the
same technique, any FIFO of 16 words by 4n bits can be constructed, where n is the number of devices. The iRF output of
the right most device (most significant device) is connected to the TTS inputs of all devices. Similarly, the ORE output of the
most significant device is connected to the TOS inputs of all devices. As in the vertical expansion scheme, horizontal expansion does not sacrifice any of the 4703B/4703BX's flexibility for serial/parallel input and output.
It should be noted that this form of horizontal expansion extracts a penalty in speed. A single FIFO is guaranteed to operate
at 3.4 MHz; an array of four FIFOs connected in the above manner is guaranteed at 1.5 MHz. An expansion scheme that provides higher speed but requires additional components is shown in the Applications section of this book.
Horizontal and Vertical Expansion - The 4703B/4703BX can be expanded in both the horizontal and vertical directions
without any external parts and without sacrificing any of its FIFO's flexibility for serial/parallel input and output. The interconnections necessary to form a 31-word by 16-bit FIFO are shown in Figure 6. Using the same technique, any FIFO of
(15m + 1) words by (4n) bits can be constructed, where m is the number of devices in a column and n is the number of
devices in a row.
Figures 7 and 8 show the timing diagrams for serial data entry and extraction for the 31-word by 16-bit FIFO shown in
Figure 6. The final position of data after serial insertion of 496 bits into the FIFO array of Figure 6 is shown in Figure 9.

rlD-3-D-2-D-,-D-0-------PARA~~E~6D~:A ~~PUT - - - - - - - - D , - , - D , - 0 - D 9--D'1
8
CPSI

PC
DS

++

+

TfsL Ds 03 D2 01
IES

IRF

'-<>

--0 CPS I

~

Pl Os

DO

OES
TOS

4703B!4703BX

TOP

~ EO

ORE

CPSO

MR 03 °2 0 1 00 Os

u~
I<>~

03 02 01

HS
IES
CPS I

11

DO

PL
HS
IES

IPF

II I

DS 03 02 D1

DO

IRFo--

"""'"C: CPS I

DES

4703B,'4703BX

TOS
TOP
CPSG

EO
MR 03 02 01

OR EP00

J~

as

~

OES
TOS

4103B'4703BX

TOP

DA TA
RE ADY

CPSO

E~R

03 02 01 00

C

DUMP

CPSO
EO

MR

-=

°3 °2
I

0 1 00

0'1 U6 lUs a,
FARAlLEL DATA OUTPUT

Fig. 5
A HORIZONTAL EXPANSION SCHEME

7-219

U" ',\lUg . U8
1

•

FAIRCHILD CMOS • 4703B/4703BX

D-6-D-'D-4 PARALLEL OAT A INPUT -D-11-D-1O-D-9-D-8--------D-,,-D-'4-D-,-3-D,---.,1

3

0--0-,0 - , - 0 - 0 - - - - - - - - 0 - 7 -

rl

SERIAL DATA INPUT

II

PARALLEL LOAD

I

INPUT CLOCK

I

--<:

~

IRF

IES

CPS I

IES

ORE

,

DES

IRF
ORE

-----~
e>-

TOS
TDP

-C CPSO

CPSG

KED

EO
MR

Q 3 Q 2 Q 1 QOOS

MR

030201°0°$

Je

1
PL DSD3 020100

PLDSD3D2D1DO

IES

IRF

6
ORE
47038
4703BX

Q3Q2D1QOOS

'---c

IRF

L--o

CPSI
DES

TOS

~

ns
f---o IES

ns

7
4703!-l
4703BX

ORE

CPSO

cpso

MR

°3°2°1°0°5

8

OES
TOS
TOP

EO

IRF

CPSI

TOP

~

EO

MR

1

ORE

pP-~
READY

°3 °2 0 1 00 Os

l

I

I

-

Nle

'-'--<:

CPSO

ED

MR

DES

r----o

PLOSD3020100

IRF

CPSI

IRF

I
L

ns

DES

as

r - '-
PL

e
Q

MASTER
LATCH

I

--,

,,",

-v
a-

s

REQUEST
INITIALIZATION
FLIP-FLOP

,R

R

op-

'r'

L

E

S

"...

Q

Fe

iSEE FIGURE 11

-t>
0

INPUT REG
STACK
(DERIVED FROM TTS)

-0

=t..J--

a
ORE REQUEST

FLIP-FLOP

rrO R

-

INITIALIZE
(SeE FIGURE 1)

-~
D

S

FX
(SeE FIGURE 21

R

c

Q

p- rl>o-

y

4

LOAD OUTPUT IDERIVED FROM TOP AND TOS
REGISTER

Tap

ros
DES

-0[>

Fig. 10
CONCEPTUAL DIAGRAM, INTERLOCKING CIRCUITRY

7-222

FAIRCHILD CMOS • 4703B/4703BX
DC CHARACTERISTICS: VDD as shown, VSS =

a v (See Note 1)
LIMITS

SYMBOL

PARAMETER

VDD = 5 V
MIN

Output OFF
IOZH

HIGH Current

Output OFF
IOZL

LOW Current
Quiescent

Supply

MIN

TYP

UNITS

VDD = 15 V

MAX

MIN

TYP

TEMP

MIN,25°C

1.6
12
0.4

MAX

Jl.A

MIN,25°C

-12

XM

MAX
Jl.A

MIN,25°C

-12

MAX

32.5

65

130

MIN,25°C

250

500

1000

8.75

17.5

35

250

500

1000

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VDD as shown, VSS

=

to VDD, EO = VDD

MIN,25°C

-1.6
-0.4

Output Returned

MAX

12

XC

TEST CONDITIONS

MAX

XM

XM

Current

MAX

XC

XC

Power

IDD

TYP

VDD=10V

Jl.A

MAX
MIN,25°C

Jl.A

Output Returned
to VSS, EO = VDD

All Inputs at
or VDD

oV

MAX

a v, TA =

25 0 C (See Note 3)

LIMITS
SYMBOL

PARAMETER

VDD =5 V
MIN

TYP

MAX

VDD=10V
MIN

TYP

MAX

UNITS

VDD = 15V
MIN

TYP

TEST CONDITIONS

MAX

tpHL

Propagation Delay, CPSI to'iRF'

215

430

81

162

57

114

tpLH

Propagation Delay, TTS to IRF

439

878

131

262

92

184

ns
ns

CL=50pF,

.~-

tPLH

Propagation Delay, CPSO to Os

tPHL
tpLH

Propagation Delay, TOP to On

tpHL

306

612

6B

136

48

96

299

598

79

158

56

112

325

650

128

256

90

180

293

5B6

114

228

80

160

Notes on following page.

7-223

ns
ns

RL = 200 kn
Input Transition

Times

~

20 ns

FAIRCHILD CMOS • 4703B/4703BX
AC CHARACTERISTICS AND SET-UP REQUIREMENTS (Cont'd): VDD as shown, VSS = 0 V, TA = 25°C
SYMBOL

PARAMETER

VOD = 5 V
MIN TYP MAX

LIMITS
VOD=15V
VDD = 10V
MIN TYP MAX MIN TYP MAX

UNITS TEST CONDITIONS

tpHL

Propagation Delay, CPSO to ORE

159

318

74

148

52

104

ns

tPLH

Propagation Delay, TUS to OR E

320

640

114

228

80

160

ns

tpLH

401
256

802
512

134
109

268
218

94
77

188

tPHL

Propagation Delay,
TOP to BFfE

154

tPHL

Propagation Delay, PL to IRF

119

238

44

88

31

tFT

Fall Through Time

RL = 200 kU

62

ns

Input Transition

574 1148

ns

Times, 20 ns

85

102
170

24
33

48
66

17
24

34
48

ns

(RL
(RL

Output Disable Time

64
80

128
160

34
39

68
78

24
28

48
56

ns

(RL = 1 kU to VSS)
(RL = 1 kU to VDD)

46
34

92

Output Transition Time

25
18

50
36

18
13

36
26

820 1640

2020 4040
51

tpZH
tpZL

Output Enable Time

tpHZ
tPLZ
tTLH
tTHL
twCP(H)

CL = 50 pF,
ns

Min CPSI Pulse Width (HIGH)

CPSi Pulse Width

6S

118

59

44

22

ns

31

16

ns

twCP(L)

Min

220

110

108

54

76

38

ns

t w CJ5(L)

Min CPSO Pulse Width (LOW)

120

60

60

30

42

21

ns

twCP(H)

Min CPSO Pulse Width (HIGH)

110

55

72

36

51

26

ns

twPLlH)

Min PL Pulse Width (HIGH)

122

61

44

22

31

16

ns

twT'fS(L)

Min Trn Pulse Width (LOW)

160

80

124

62

87

44

ns

twTOS(L)

Min TOS Pulse Width (LOW)

182

91

60

30

42

21

ns

twTOP(L)

Min TOP Pulse Width (LOW)

142

71

52

26

37

19

ns

twMR(L)

Min MR Pulse Width (LOW)

192

96

108

54

76

38

ns

44

22

36

18

26

13

ns

(LOW)

tree

MR Recovery Time

ts
th

Set-Up and Hold Times,
Os to CPSI

104
-8

52
-15

40
24

20
12

28
18

14
9

ns

ts
th

TRF, Serial or Parallel

Set-Up and Hold Times, TTS to
Mode

186
76

93
38

98
52

49
26

70
38

35
19

ns

-151

-302

-21

-42

-15

-30

ns

1.1

2.3

2.6

5.3

3.4

6.9

ns

ts

Set-Up Time, ORE to TOS

fMAX

Input CLOCK Frequency
(Note 2)

= 1 kUto VSS)
= 1 kU to VOO)

NOTES:
1. Additional DC Characteristics are listed in this section under 40006 Series CMOS Family Characteristics.
2. For fMAX input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.

3.
4.

Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.
It is recommended that input rise and fall times to the Clock Input be less than 15 p.s at VOO = 5 V, 4 jJ.s at VOO = 10 V, and 3 J..LS at
VDD = 15 v.

SWITCHING WAVEFORMS

\

)150%

EO _ _

tpHZ

EO

~V50%

\
1\50%

~

tpZL

tpZH

1*

I---OUTPUT

I~O%

,90%

...

.....

I
HIGHZ

~

"OFF" STATE

/'-10%

--

-'

~

OUTPUT

I

OUTPUT ENABLE TIME
(tPZH) AND OUTPUT DISABLE TIME (tPHZ)

'"

10%

-

;:;;G;;-Z -

"OFF" STATE

"',

,

90%

'---

OUTPUT ENABLE TIME
(tpZL) AND OUTPUT DISABLE TIME (tPLZ)

7-224

FAIRCHILD CMOS • 4703B/4703BX
SWITCHING WAVEFORMS (Collt'd)
SERIAL INPUT UN EXPANDED OR MASTER OPERATION

twCP1LI

DS 'X:xX;(X)(X>'"''

MINIMUM CPSI PULSE WIDTH, PROPAGATION DELAY, CPS I TO IRF AND TTS TO
RECOVERY TIME, IRF TO CPSI, AND SET·UP AND HOLD
TIMES, DS TO CPSI, AND TTS TO fRF,
CONDITIONS: STACK NOT FULL, IES,

~

PL

~

LOW

SERIAL INPUT EXPANDED SLAVE OPERATION

PROPAGATION DELAY, CPSI TO IRF AND TTS TO iRF,
RECOVERY TIME, IRF TO CPSI AND SET·UP AND HOLD
TIMES, IES TO CPSI, DS TO CPSI AND TTS TO IRF,
CONDITIONS: STACK NOT FULL IES ~ HIGH
WHEN INITIALIZED, PL ~ LOW
NOTE:
Set-up and hold times are shown as positive values but may be specified as negative values,

7·225

iRF,

FAIRCHILD CMOS • 47038/47038X
SWITCHING WAVEFORMS (Cont'd)
SERIAL OUTPUT, UNEXPANDED OR MASTER OPERATION

Os

ORE RECOVERY TIME, PROPAGATI~ELAY CPSO TO OS, CPSO TO ORE,
TOS TO ORE, MINIMUM CPSO PULSE WIDTH, MINIMUM
PULSE WIDTH AND SET-UP TIME ORE TO TOS.

;:os

CONDITIONS: DATA IN STACK, TOP = HIGH, IES
WHEN INITIALIZED, OES = LOW

= LOW

SERIAL OUTPUT, SLAVE OPERATION

0i'i:E RECOVERY TIME,

PROPAGATION DELAY CPSO TO aS, CPSO TO ORE,
TOS TO ORE, AND SET·UP
AND HOLD TIMES, OES TO CPSO, ORE TO TOS, TOO TO CiES
CONDITIONS: DATA IN STACK, TOP
WHEN INITIALIZED

= HIGH, IES = HIGH

NOTE:
Set~up (t s)

and hold times (th) are shown as positive values but may be spec'ified as negative values.

7-226

FAIRCHILD CMOS • 4703B/4703BX
SWITCHING WAVEFORMS (Cont'd)
FALL THROUGH TIME

MR

--"~"'"'''={
~

_50%

tREC-~
PL

:
---------------

\l50%

tWPL(H)----I\~-----------

~--tFT--~.!J

~

n
~--

MINIMUM MR AND PL PULSE WIDTHS, RECOVERY TIME
FOR MR AND FALL THROUGH TIME
CONDITIONS: TTS CONNECTED TO iRF, TOS CONNECTED
TO ORE, IES, OES, EO, CPSO = LOW. TOP = HIGH

PARALLEL OUTPUT, FOUR BIT WORD OR
MASTER IN PARALLEL EXPANSION

TOP

50%
tPLH

~
tpHL

On

~

~50_O/'_,___NE_W__O_UT_P_U_T_______________

PROPAGATION DELAY, TOP TO ORE, TOP TO an, AND
MINIMUM TOP PULSE WIDTH
CONDITIONS: IES = LOW WHEN INITIALIZED, EO = CPSO =
LOW. DATA AVAILABLE IN STACK

7·227

FAIRCHILD CMOS • 4703B/4703BX
SWITCHING WAVEFORMS (Cont'd)
PARALLEL LOAD MODE, FOUR BIT WORD (UNEXPANDED)
OR MASTER IN PARALLEL EXPANSION
twPL(HI------<~

PL--------------~

STABLE

i+----tpLH-----i

fAi'

TTS (NOTE 21

PROPAGATION DELAY PL TO IRF, TTS TO iRF,
MINIMUM PL AND TTS PULSE WIDTHS, AND SET-UP AND
HOLD TIMES On TO PL, IRF TO PL, TTS TO iRF.
CONDITIONS: STACK NOT FULL, I ES
WHEN INITIALIZED

NOTES:

~

LOW

1. Initialization requires a master reset to occur after power has been applied.
2. TTS normally connected to fRF.

3.

If stack is full,

fRF' will stay LOW.
PARALLEL LOAD, SLAVE MODE

PL

TTS - - - - - - - - - - - - - - - - - - - - - - - - - - - - -......

PROPAGATION DELAY, TTS TO IES, IES TO IRF,PL TO IRF,
MINIMUM PL AND TTS PULSE WIDTHS, AND SET-UP AND
HOLD TIMES, On TO PL, IRF TO TTS, IRF TO PL

NOTE:

CONDITIONS: STACK NOT FULL, DEVICE INITIALIZED
WITH IES HIGH

Set-up (t5 ) and hold times (th) are shown as positive values but may be specified as negative values.

7-228

4710B/4710BX
REGISTER STACK· 16x4 RAM
WITH 3-STATE OUTPUT REGISTER
FAIRCHILD CMOS MACROLOGIC ™

DESCRIPTION - The 4710B/4710BX is a register oriented high speed 64-bit Read/Write
Memory organized as 16-words by 4-bits. An edge triggered 4-bit output register allows
new input data to be written while previous data is held. 3-state outputs are provided for
maximum versatility. The 4710B/4710BXis fully compatible with all CMOS families.
The 4710B is specified to operate over a power supply voltage range of 4.5 V to 12.5 V.
The 4710BX is specified to operate over a power supply voltage range of 3 V to 15 V.
•
•
•
•

lOGIC SYMBOL

17151311

EDGE-TRIGGERED OUTPUT REGISTER
3-STATE OUTPUTS
OPTIMIZED FOR REGISTER STACK OPERATION
l8-PIN PACKAGE

PIN NAMES
Address Inputs
Data Inputs
Chip Select Input (Active LOW)
Output Enable Input (Active LOW)
Write Enable Input (Active LOW)
Clock Input (Outputs Change on LOW
to HIGH Transition)
Outputs

AO-A3
DO-D3
CS
EO
WE
CP

16

14

12

10

VDD = Pin 18
Vss=Pin9

CONNECTION DIAGRAM
DIP (TOP VIEW)

18

BLOCK DIAGRAM
17

16
15
14

0)

CD

CP

0)

0
®
®

AO
Al
A,

13
16 X 4
MEMORY CELL
ARRAY

11

A3

cs --+---1

10

®EO------<>l>----~.r-_\r__\.f_~
VDD
Vss

o

12

Pin 18
= Pin 9
= Pin Numbers
=

7-229

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual In-line Package.

FAIRCHILD CMOS • 4710B/4710BX
FUNCTIONAL DESCRIPTION - The 471 OB/4710BX consists of a 16 X 4-bit RAM selected by four address inputs (AO -A3)
and an edge-triggered 4-bit Output Register with 3-state Output Buffers.
Write Operation - When the three control inputs: Write Enable (WE), Chip Select (CS), and Clock (CP), are LOW the
information on the data inputs (DO - D3) is written into the memory location selected by the address inputs (AO - A3).
If the input data changes while WE, CS, and CP are LOW, the contents of the selected memory location follows these
changes provided set-up time criteria are met.
Read Operation - Whenever CS is LOW and CP goes from LOW-to-HIGH, the contents of the memory location selected by
the address inputs (AO - A3) is edge triggered into the Output Register.
A 3-State Output Enable (EO) controls the output buffers. When EO is HIGH the four outputs (00 - 03) are in a high
impedance or OFF state; when EO is LOW, the outputs are determined by the state of the Output Register.

DC CHARACTERISTICS: VDD as shown, VSS = 0 V (See Note 1)
LIMITS
SYMBOL

PARAMETER

MIN

Output OFF
IOZH

IOZl

Current HIGH

Output OFF
Current lOW

Quiescent
Power
IDD

Supply

Current

VDD = 10 V

VDD =5 V
TYP

MAX

MIN

TYP

TYP

0.4

I'A

I'A

- 12
20

40

80

150

300

600

5

10

20

150

300

600

Notes on following page.

7-230

Output Returned
to

VDD, EO = VDD

MIN,25°C

-1.6
-0.4

MAX
MIN,25°C
MAX

-12

XM

TEST CONDITIONS

MIN,25°C

12

XC

TEMP

MAX

12

XM

XM

MIN

1.6

XC

XC

UNITS

VDD= 15V

MAX

MAX
MIN,25°C

Output Returned
to VSS

EO = VDD

MAX
MIN,25°C
I'A

MAX

All inputs at

MIN,25°C

o V or VDD

MAX

FAIRCHILD CMOS • 4710B/4710BX
AC CHARACTERISTICS ANO SET-UP REQUIREMENTS: VOO as shown, VSS

= 0 V, TA = 25°C

(See Note 21

LIMITS
SYMBOL

PARAMETER

VOD = 5 V
MIN

VDO=10V
TYP

MAX

292

56

250

49

TYP

MAX

146
125

MIN

UNITS

VDD=15V
MIN

TYP

MAX

112

40

80

98

34

68

TEST CONDITIONS

READ MODE
tPLH

Propagation Delay, CP to Output

tpHL
tpZH
tpZL
tpHZ
tpLZ
tTLH

Enable Time, EO to Output
Disable Time, EO to Output

Output Transition Time

tTHL

57

114

20

40

16

32

81

162

31

62

23

46

57

114

29

58

23

46

72

144

31

62

25

50

75

150

45

90

35

70

80

160

45

90

35

70

ns
ns

(RL = 1 k.l1 to VSS)
(RL = 1 k.l1 to VDD)

ns

(RL = 1 k.l1 to VSS)
(RL = 1 k.l1 to VDD)

ns

WRITE MODE
twWE

Minimum WE Pulse Width (Note 3)

218

109

104

52

62

31

ns

CL = 50 pF,

twCS

Minimum CS Pulse Width (Note 3)

226

113

124

62

74

37

ns

RL = 200 k.l1

twCP

Minimum CP Pulse Width (Note 3)

240

120

124

62

74

37

ns

Input Transition

ts

Set-Up Time CS to WE (Note 4)

326

163

198

99

134

67

ns

Times.;; 20 ns

ns

Cs to WE

th

Hold Time,

ts

Set-Up Time, CS to CP

th

Hold Time,

ts

Set-Up Time, Dn to WE (Note 4)

th

Hold Time, On to WE (Note 4)

ts
th

(Note 4)

Cs to CP

Set-Up Time, Address to WE
(Note 4)
Hold Time, Address to WE (Note 4)

0

-15

0

-10

0

-5

186

93

104

52

68

34

ns

0

-15

0

-10

0

-5

ns

176

68

70

35

48

24

ns

0

-15

0

-10

0

-5

ns

206

103

100

50

58

29

ns

0

-15

0

-10

0

-5

ns

706

353

372

186

208

104

ns

0

-15

0

-10

0

-5

ns

READ MODE
t.

Set-Up Time Address to CP

th

Hold Time Address to CP

NOTES:
1. Additional DC Characteristics are listed in this section under 40006 Series CMOS Family Characteristics.
2. Propagation Delays and Output Transition Times are graphically described in this section under 40006 Series CMOS Family Characteristics.

3.
4.
5.

Writing occurs when WE: CE. and CP are LOW.
Assuming WE is utilized as a Writing STROBE.
It is recommended that input rise and fall times to the Clock Input be less than 15 p.s at VDO = 5 V, 4fJs at VDO ""' 10 V and 3IJ.s at
VDD=15V.

7-231

FAIRCHILD CMOS • 4710B/4710BX
SWITCHING WAVEFORMS
READ MODE

50%

50%

50%

50%

EO

-

~
90%

OUTPUT

~,..-----PLZ

tpHZ

~

HIGH Z
"OFF" STATE

10%

'------'

10%

~PZL

HIGH Z
"OFF" STATE

~

EO TO OUTPUT ENABLE AND DISABLE TIMES

MINIMUM CP PULSE WIDTH, PROPAGATION DELAY CLOCK TO OUTPUT,
AND SET-UP AND HOLD TIMES ADDRESS TO CLOCK
CONDITIONS: CS = EO = LOW, WE = HIGH

WRITE MODE

~_~:

~_5:-~

_ _ _ _ _S_T_A_BL_E_ _ _ _ __

WE

____

~

~r---------twCS----------~

50%

, _ _ ___
50%

MINIMUM CS PULSE WIDTH, MINIMUM WRITE ENABLE PULSE WIDTH,
SET-UP AND HOLD TIMES AODRESS TO WE, DATA TO WE, AND

CS to WE

CONDITIONS: CP = LOW
NOTE: Set-Up (ts) and Hold Times (th) are shown as positive values but may be specified as negative values.

7-232

FAIRCHILD CMOS • 4710B/4710BX
SWITCHING WAVEFORMS (CONT'D)

WRITE MODE

cs-------~
\

50%

\

/k'::.

cp ____________________J

SET· UP AND HOLD TIMES, CS TO CP

NOTE: Set-up Times (t5 ) and Hold Times (th) are shown as positive values, but may be specified as negative values.

•

7·233

4720B/4720BX
256-BIT RANDOM ACCESS MEMORY WITH 3-STATE OUTPUT
DESCRIPTION - The 4720B/4720BX is a 256-Bit Random Access Memory with 3-State Outputs. It
has a Data Input (D), eight Ad~ss inputs (A O-A7 ), an active HIGH Write Enable Input (WE), an
active LOW Chip Select Input (CS), an active HIGH 3-State Output (0) and an active LOW 3-State
Output (0). Information on the Data Input (D) is written into the memory location selected by the
Address Inputs (A O-A7 ) when the Chip Select Input (CS) is LOW and the Write Enable Input (WE) is
HIGH. Under these conditions, the device is transparent, i.e., the data input is reflected at the True
and Complementary Outputs (0, 0). Information is read from the memory location selected by the
Address Inputs (AO-A7 ) while the Chip Select (CS) and t~.e Write Enable (WE) Inputs are LOW. The
o Output is the information written into the memory, 0 is its complement. When the Chip Select
Input (CS) is HIGH, both outputs (Q, 0) are held in the high impedance OFF state. This allows other
3-State outputs to be wired together in a bus arrangement. The 4 720B/4 720BX offers fully static
operation.
The 4720B is specified to operate over a power supply voltage range of 4.5 to 12.5 V. The 4720BX
is specified to operate over a power supply voltage range of 3 to 15 V.
•
•
•
•
•
•
•
•

LOGIC SYMBOL

16

15

12

10
11

3-STATE OUTPUTS
ORGANIZATION - 256 WORDS X I-BIT
ON-CHIP DECODING
TRUE AND COMPLEMENT OUTPUTS AVAILABLE
FULLY STATIC
LOW POWER DISSIPATION
HIGH SPEED
TYPICAL HOLDING VOLTAGE OF 1.5 V

13

14

Voo = Pin 5
VSS

= Pin

NC

"" Pin 4

8

MODE SELECTION
CS

WE

L

H

L

L

Q

Q

MODE

Data Written

Complement of
Data Written
Into Memory

Write

Into Memory

Data Written

CONNECTION DIAGRAM
DIP (TOP VIEW)

Complement "f

Into Memory

Data Written

Read

Into Memory
16

H

X

High
Impedance

High

Impedance

Inhibit

15
14

13

BLOCK DIAGRAM

12
11
VDD""Pln5
X

Vss = Pin 8

16X 16
MATRIX

INPUT
BUFFERS

10

NC "" Pin 4
0"" Pin Number

INPUT
BUFFERS
y

~===7J.===~~

~==:::;1J.====~>

a@

L-.-=----l

OUTPUT

BUFFER

@VwE---------------------------1
@

D------------------------~I

'------'

~~--------------------------------------------~

PIN NAMES
Chip Select Input (Active
CS
LOW)
Write Enable Input
WE
D
Data Input
Address Inputs
AO-A7
3-State Output (Active
o
HIGH)
3-State. Output (Active
LOW)
NOTE:
The F latPak version has the same pinouts (Connection Diagram)
Dual I n~line Package.

7-234

as the

FAIRCHILD CMOS. 4720B/4720BX
OC CHARACTERISTICS: VOD as shown, VSS

~

0 V (See Note 1 I
LIMITS

SYMBOL

PARAMETER

VDD
MIN

~

TYP

VDD~10V

5V
MAX

MIN

TYP

VDD~15V

MAX MIN

TYP

UNITS

1.6
XC

Output OFF
IOZH

Current, HIGH

Current, lOW
Quiescent

XC

IDD

Supply

12

MAX
MIN,25°C

-12

MAX

I'A

-0.4

MIN,25°C

-.12

Output Returned
to VSS, CS ~ VDD

MAX

20

40

80

150

300

600

5

10

20

150

300

600

XM

Current

Output Returned

MIN,25°C to VDD, CS ~ VDD

-1.6

XM

Power

MAX
I'A

0.4

XC

TEST CONDITIONS

MIN,25°C

12

XM

Output OFF
IOZl

TEMP

MAX

MIN,25°C
I'A

MAX
MIN,25°C

I'A

All inputs at
OVorVDD

MAX

AC CHARACTERISTICS AND SET·UP REQUIREMENTS: VDD as shown, VSS ~ 0 V, TA ~ 25°C (See Note 21
LIMITS
SYMBOL

PARAMETER

VOD ~ 5 V
MIN

VDD~10V

TYP

MAX

MIN

TYP

MAX

VDO~15V

MIN

UNITS

TYP

MAX

TEST CONDITIONS

READ MODE
tplH

Propagation Delay,

250

500

95

190

68

136

tPHl

Address to Output

250

500

95

190

68

136

30

60

15

30

11

22

35

70

17

34

12

24

25

50

15

30

11

22

27

54

16

32

12

24

75

150

35

70

25

50

75

150

35

70

25

50

tpZH

Enable Time,

tpZL
tpHZ

Disable Time,

tpLZ
tTLH

Cs to Output
Cs to Output

Output Transition Time

tTHL

ns
ns
ns

(R l ~ 1 kll to VSSI
(RL ~ 1 kll to VDDI
(RL ~ 1 kll to VSSI
(RL ~ 1 kll to VODI

ns

WRITE MODE
tPLH

Propagation Delay,

250

500

100

200

65

130

tpHL

WE to Output

250

500

100

200

65

130

ns

WRITE MODE
twWE

Minimum WE Pulse Width

ts

Set-Up Time, D to WE

80

th

Hold Time, D to WE

40

ts

Set-Up Time, Address to WE

260

th

Hold Time, Address to WE

160

ts

Set-Up Time, CS to WE

th

Hold Time, CS to WE

-

240

120

110

55

80

40

40

38

19

28

14

20

22

11

18

9

130

130

65

90

45

80

80

40

40

20

60

30

30

15

20

10

60

30

30

15

20

10

ns

CL

~

50 pF,

RL

~

200 kll

Input Transition

Times'" 20 ns
ns
ns
ns

NOTES:

1.
2.

Additional DC Characteristics are listed in this section under 4000B Series CMOS Family Characteristics.
Propagation Delays and Output Transition Times are graphically described in this s~ction under 4000B Series CMOS Family Characteristics.
3. All set-up (t s ) and hold (th) times are measured with minimum write enable pulse width (twWE).

7-235

•

FAIRCHILD CMOS. 4720B/4720BX
SWITCHING WAVEFORMS

READ MODE

,r---OUTPUT

,90%
HIGH Z
"OFF" STATE
,

....

--

-'

,

/

OUTPUT

10%

CS TO OUTPUT

-----.....'

..

HIGH Z
"OFF" STATE

10%

I;NABLE AND DISABLE TIMES

WRITE MODE

-4---

twWE--..

MINIMUM PULSE WIDTH FOR WE AND SET-UP AND HOLD TIMES,
o TO WE, An TO WE, AND CS TO WE

Note: Set-up and Hold Times are shown as positive values but may be specified as negative values.

7-236

,

90%

L-

47228
PROGRAMMABLE TIMER/COUNT
GENERAL DESCRIPTION -The 4722B Programmable TImer/Counter is a
capable of producing accurate microsecond to five day time delays. Long
up to three years,
can easBy be generated by cascading two timers. The timer consists of a time base oscillator programmable 8-blt counter and control flip-flop. An external resistor capacitor (RxC x ) network sets
the oscillator frequency and allows delay times from 1 RxCx to 255 RxCx to be selected. In the
astable mode of operation, 255 frequencies or pulse patterns can be generated from a single RxCx
network. These frequencies or pulse patterns can also easily be synchronized to an external signal. The
Irigger Input (T). Master Reset Input (MR) and Data Outputs (00' 02' 04' 08' 016, 032' 064'
0 128 ) are all TTL and DTL compatible for easy interface with digital system. The timer's high accuracy and versatility in producing a wide range of time delays makes it ideal as a direct replacement
for mechanical or electromechanical devices.

LOGIC SYMBOL
13

11

4722B

ACCURATE TIMING FROM MICROSECONDS TO DAYS
PROGRAMMABLE DELAYS FROM 1 RxCx TO 255 RxCx
TTL, DTL AND CMOS COMPATIBLE OUTPUTS
TIMING DIRECTLY PROPORTIONAL TO RxCx TIME CONSTANT
HIGH ACCURACY
EXTERNAL SYNC AND MODULATION CAPABILITY
WIDESUPPLYVOLTAGERANGE
EXCELLENT SUPPLY VOLTAGE REJECTION
LOW POWER DISSIPATION

1

2

3

° ,°

° 1 ,°2 4 ,°8'
16'°32'°64'°128

4

5

6

V DD
VSS

7

8

Pin

16

Pin 9

CONNECTION DIAGRAM
DIP (TOP VIEW)
16

PIN NAMES
Rx/Cx
T
MOD
MR
V REG
TBO

15

10

14

•
•
•
•
•
•
•
•
•

12

15

External Resistor/Capacitor Connection
Trigger Input
Modulation Input
Master Reset Input
Regulator Output
TIme Base Output (Open Drain)
Data Outputs (Active Low-Open Drain)

14
13

12
11

10

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual In-line Package.

BLOCK DIAGRAM

VDD

R,

6,

016

CD

CD

7-237

032

CD

064

CD

0128

CD

TBO

@

FAIRCHILD CMOS. 4722B
FUNCTIONAL DESCRIPTION
When power is applied to the 4722B with no Trigger (T) or Master Reset (MR) Inputs, the circuit starts with all outputs in a high impedance
OFF state, Application of a positive-going trigger pulse to T initiates the timing cycle, The Trigger Input (T) activates the li me-Base Generator,
enables the counter and sets the counter outputs LOW, The time-base generator generates timing pulses with a period T = 1 RxC x ' These clock
pulses are counted by the 8-stage Binary Counter, The timing sequence is completed when a positive-going pulse is applied to MR,
Once triggered, the circuit is Immune from additional trigger inputs until the timing cycle is completed or a Master Reset is applied, If both the
Master Reset and Trigger Inputs are activated simultaneously, the Trigger Input takes precedence,
Figure 1 gives the timing sequence of output waveforms at various circuit terminats, subsequent to a Trigger Input. When the circuit is in a

Master Reset state, both the time-base and the counter sections are disabled and atl the counter outputs are in a high impedance OF F state.
In most timing applications, one or more of the counter outputs are connected to the Master Reset terminal with S1 closed (Figure 2), The
circuit starts timing when a Trigger Input is applied and automaticaHy resets itself to complete the timing cycle when a programmed count is
completed, If none of the counter outputs are connected back to the Master Reset terminal (switch S1 open), the circuit operates in an astable
or free-running mode, following a Trigger Input,
Important Operating Information
•

Ground connection is pin 9.

•

Master Reset sets all outputs to a high Impedance OFF state,

•

Trigger sets all outputs LOW,

•

lime-base TBO can be disabled by bringing the Rx/Cx Input LOW via a pull-down reSistor,

•

Normal lime-base Output (TBO) is a negative-going pulse greater than 500 ns,

•

Master Reset stops the time-base generator.

•

Data outputs

•

For use with external clock, minimum clock pulse amplitude should be 0,7 VDD, with greater than 1 ILS pulse duration,

° °
1 ,,' ,

128 sink 1,6 mA current with VOL':;; 0,4 V;

I n _____________ ---.. t

TRIGGER
INPUT

1.-111111111111111111111111

TIME BASE
OUTPUT

~J,-

tmnn.rLnn.nnnru _
h..n.n..n.n..n._
h Cl I I Cl_

h
h

t

DATA
OUTPUTS

t

0,

0,

TRIGGER

R
MASTER

RESET
INPUT

..rL
t

1_.
_t

04

o-+-......................-+-+-O--....,r--OUTPUT

DB

1T

W

:;

Tp-+j

;:::

...

I-

oJLJL
I--TS-j

0.1 pF

I~~~~-l

0
~

12
5.1 k

±12

w

±8

'a:"

±4

"Z

MOD

Z

~
:>

..

•

\

'" '"
2

4

"'- .....

......
10

12

RATIO OF TIME·BASE PERIOO TO
SYNC-PULSE PERIOO -IT/T.I

Fig. 3 Operation with External Sync. Signal

Fig. 4 Tvpical Pull·in Range for Harmonic Synchronization

7-239

FAIRCHILD CMOS. 4722B
VDD

VDD

VOD

R,

c,
R5

-=MOD

Rx/Cx
INPUT
47228

4722B

0,
cC
MASTER
RESET

........._+_1............- - _ + - - OUTPUT

INPUT --+---Ir------------+--~....,.tv_~-~+R2

Fig.5 Cascaded Operation for Long Delays

VDD

VOD

R,

VDO

R3

R4

"1

c,

J

TRIGGER
INPUT

J1...
MASTER
RESET
INPUT

J"L

I

I
LT

MOD

Rx/ex
47228

VREG

- , - MR

r-

TBO 0, 020408 01'b320640128

47228

cC

rllllll'l

I

MOD

Rx/ex

T

-

MR

TBO

0,

02

04

08

VREG

-

016 064
032
0128

1
OUTPUT

~

-I
Fig. 6

TO

I-

Low Power Operation of Cascaded Timers

Regulator Output (V REG )
The Regulator Output (V REG is used internally to drive the counter and the control logic. This terminal can also be used as a supply to addi·
tional 47228 circuits when several timer circuits are cascaded (see Figure 6) to minimize power dissipation. For circuit operation with an external clock, V REG can be used as the VOO input terminal to power down the Internal time base and reduce power dissipation. When supply
voltages less than 4.5 V are used with the internal time·base, V REG should be shorted to VOO'
MONOSTABLE OPERATION
Precision Timing
In precision timing applications, the 47228 is used in its monostable or self-resetting mode. The generalized circuit connection for this application is shown in Figure 2. The output is normally OFF and goes LOW following a Trigger Input. It remains LOW for the time duration,
TO' and then returns to the OFF state. The duration of the timing cycle TO is given as:

where T = RxCx is the time-base period as set by th~ choic~ of timing components at Rx/ex and N is an integer in the range of 1 ~ N ~ 255 as
determined by the combination of counter outputs 0, ... 128 - connected to the output bus.

°

7·240

FAIRCHILD CMOS. 4722B

° °

Counter-Output Programming

The Data Outputs, 1 ... 128 , are open·drain type stages and can be shorted together to a common pull-up resistor to form a wired-OR
connection; the combined output will be LOW as long as anyone of the outPuts is LOW. The time delays associated with each Data Output
can be added together. This is done by simply shorting the outputs together to form a common output bus as shown in Figure 2. For example,
if only pin 6 Is connected to the output and the rest left open, the total duration of the timing cycle, TO' is 32 T. Similarly, if pins 1,5, and 6
are shorted to the output bus, the total time delay is TO = (1 + 16 + 32) T = 49 T. In this manner, by proper choice of counter terminals connected to the output bus, the timing cycle can be programmed to be 1 T';; TO';; 255 T.
Ultra-Long Time-Delay Application
Two 4722Bs can be cascaded as shown In Figure 5to generate extremely long time delays. Total timing cycle of two cascaded units can be programmed from TO = 256 RxCx to TO = 65.536 RxCx in 256 discrete steps by selectively shorting one or more of the Data Outputs from Unit 2
to the output bus. In this application, the Master Reset and the Trigger Inputs of both units are tied together and the Unit 2 time base generator is disabled. Normally, the output is OFF when the system is reset. On triggering, the output goes LOW where it remains for a total of
(256) 2 or 65.536 cycles of the time-base oscillator.
In cascaded operation, the time-base generator of Unit 2 can be powered down to reduce power consumption by using the circuit connection of
Figure 6. In this case, the V DD terminal of Unit 2 is left open, and the second unit is powered from the V REG Output of Unit 1 by connecting

the V REG (pins 15) of both units together.
ASTABLE OPERATION
The 4722B can be operated in its astable or free-running mode by dlsonnecting the Master Reset Input from the Data Outputs. Two typical
circuits are shown in Figure 7 and 8. The circuit in Figure 7 operates in its free-running mode with external trigger and reset signals. It starts
counting and timing following a Trigger Input until an external Master Reset pulse is applied. Upon application of a positive-going reset signal
to M R, the circuit reverts back to its Master Reset state. This circuit is essentially the same as that of Figure 2 with the feedback switch S1 open.
The circuit of Figure 8 is designed for continuous operation. It self-triggers automaticatly when the power supply is turned on, and continues
to operate in its free-running mode indefinitely. in astable or free-running operation; each of the counter outputs can be used individually as
synchronized Oscillators, or they can be interconnected to generate complex pulse patterns.
Binary Pattern Generation

In astable operation, as shown in Figure 7, the output of the 4722B appears as a complex pulse pattern. The waveform of the output pulse
train can be determined directly from the timing diagram of Figure 1, which shows the phase relations between the counter outputs. Figures 9
and 10 show some of the complex pulse patterns that can be generated. The pulse pattern repeats itself at a rate equal to the period of the
highest counter bit connected to the common output bus. The minimum pulse width contained in the pulse train is determined by the lowest
counter bit connected to the output.
VOD

r-------------------~-----oVOD

VOD

R3

C,

TRIGGER
INPUT

SL

Rx/ex

MOD

T
T
MASTER
RESET
INPUT

c,

47229

VREG

SL

<-......................4

Fig. 7 Operation with External Trigger and Master Reset Inputs

Fig. 8

Free-Running or Continuous Operation

A. 2 PIN PATTERNS

JLJLJUUl
JUUlfL..JUlJlJL
+jT\- H3T
-IT!- t-- ST -i-- -+j
7T

T'R,C,
PINS 1 AND 2 SHORTED

B. 3 PIN PATTERN

~~------~~~-1'""'.>-----21T---~.1

3TH+ST+j

PINS 1. 3. AND S SHORTED
C. 4 PIN PATTERN

Fig. 9 Binary Pulse Patterns Obtained by Shorting Various Counter Outputs

7-241

.....1 - ' - - - 4 - t - - - OUTPUT

•

FAIRCHILD CMOS. 4722B

Voo

Von

VOD = Prn 16

Vss

:: Pin 9

47228

MR

",
--l:~I-

",C, WAVEFORM

TIME BASE OUTPUT

0,

OUTPUT

rYYYYYn/ /fYYYYYYYl
I I I I I I 1/ /

IIIIIIII

1LfUlJ// ~

",

",

JlSL//--1UL
I_

256 RxCx

R,

R,

Fig. 10 Continuous Free·run Operation Examples of Output

7·242

.

..

I

FAIRCHILD CMOS. 4722B
OPERATION WITH EXTERNAL CLOCK
The 47228 can be operated with an external clock or time base by disabling the internal time~base generator and applying the external clock
input to TBO. The recommended circuit connection for this application is shown in Figure 11. The internal time base is de-activated by connecting a resistor from RxCx to ground. The counters are triggered on the negative-going edges of the external clock pulse.

FREQUENCY SYNTHESIZER
The programmable counter section of the 47228 can be used to generate 255 discrete frequencies from a given Time-Base Output setting using
the circuit connection of Figure-12. The circuit output is a positive pulse train with a pulse width equal to T, and a period equal to (N + 1) T
where N is the programmed count in t~e counter. The modulus N is the total count corresponding to the Data Outputs connected to the output
bus. For example. if pins 1. 3, and 4 are connected together to the output bus. the total count is N = 1 + 4 + 8 = 13, and the period of the
output waveform is equal to (N + 1) Tor 14 T. In this manner, 255 different frequencies can be synthesized from a given time-base setting.

'DO

'co

IL
IL
EXTERNAL
CLOCK

rU1h.rL
S1 OPEN: ASTABLE OPERATION
S1 CLOSED: MONOSTABLE
T (N-l)

Fig. 11

Operation with External Clock

Fig. 12 Frequency Synthesis from Internal Time-Base

REFERENCE
INPUT. fR

VDD

Rx

lC

x

L

VDD

R4

5.1 k

MOO

Rx/Cx

T
R,

4722B

VREG

OUTPUT

.IL...rL

-ttJ
TO

Fig. 13 Frequency Synthesis by Harmonic Locking to an External Reference

7-243

FAIRCHILD CMOS. 4722B
SYNTHESIS WITH HARMONIC LOCKING
The harmonic synchronizing feature of the time base can be used to generate a wide number of discrete frequencies from a given input reference frequency. The circuit connection for this application is shown in FIgure 13 (see Figures 3 and 4 for external sync waveform and harmonic
capture range). If the time base is synchronized to Imlth harmonic of input frequency where 1 .;; m .;; 10, the frequency fO of the output
waveform in Figure 13 is related to the input reference frequency fR as

where m is the harmonic number, and N is the programmed counter modulus. For a range of 1 .;; N .;; 255, the circuit of Figure 13 can produce
2550 different frequencies from a singfe fixed reference.

The circuit of Figure 13 can be used to generate frequencies which are not harmonically related to a reference input. For example, by selecting the external RxCx to set m = 10 and setting N = 5, a 100 Hz output frequency synchronized to 60 Hz power line frequency can be obtained.

STAIRCASE GENERATOR
The 47228 Programmable TImer/Counter can be interconnected with an external operational amplifier and a precision resistor ladder to form
a staircase generator as shown in Figure 14. Under Master Reset condition, the output is LOW. When a Trigger is applied, the op amp output
goes HIGH and generates a negative~going staircase of 256 equat steps. The time duration of each step is equal to the time~base period T. The
staircase can be stopped at any level by applying a disable signal to TBO, through a steering diode, as shown in Figure 14. The count is stopped
when TBO is clamped.

TRIGGER

..n..

:rL
yLE
~

DISABLE

N
M

Fig.14

..I1..

~

co

~

<:t

~

I'll

a:

Staircase Generator

"2

STROBE
INPUT

V,N
ANALOG INPUT----+--------C-....:.c----i

S

Q

40438

L----------------------iR

Q

BISTABLE LATCH

Fig. 15 Digital Sample and Hold Circuit

7-244

FAIRCHILD CMOS. 4722B
DIGITAL SAMPLE AND HOLD
Figure 15 shows a digital sample and hold circuit using the 4722B. Circuit operation is similar to the staircase generator described in the previous
section. When a strobe input Is appUed, the RxCx row~pass network between the Master Reset and the Trigger Inputs resets the timer, then
triggers it. This strobe input also sets the output of the bistable latch to a HIGH stage and activates the counter.
The circuit generates a staircase voltage at the op amp output. When the level of the staircase reaches that of the analog input to be sampled,
the comparator changes state, activates the bistable latch and stops the count. At this point, the voltage level at the op amp output corresponds
to the sampled analog input. Once the input is sampled, it is held until the next strobe signal.
ANALOG-TO-OIGITAL CONVERTER
Figure 16 shows a simple B-bit AID converter system using the 4722B. Circuit operation is very similar to that of the digital sample and hold
system of Figure 15. In the case of AID conversion, the digital output is obtained in parallel format from the binary-counter outputs with the
output at pin 8 corresponding to the most significant bit (MSB).
DIGITAL TACHOMETER TIME BASE
A digital tachometer reqUires a time-base generator to supply two pulse outputs at specific intervals, e_g., every second. The first pulse is a command (load) to transfer the accumulated counts in the counter section into latches (memory); the second resets the counter to zero. A simple
adjustable time base, accurate to approximately ±O.5%, can be implemented using the circuit in Figure 17.

VDD

c,

~l

I

INPUT

MOD

Ax/ex

r

I

STROBE

R,

C,

.pI----

4722B

MR
TBO

a,
02

04

Os

VREG

-

0'6
064
032
0128

R,

~ ~ ~
128R

j

I

64 R
32R

'6R
R3

ADJUST

-

+

2R
R

r---

•
R

-

~

II
~

Fig. 16.

VDD

DIGITAL OUTPUTS

4R

.""~~
OP AMP

ANALOG
INPUT

SR

Y.CAlE

VDD

BISTABLE

LATCH

jcr-Analog-to·Digital Converter

VDD

c,

TIMING DIAGRAM

(.,

R5

(b,

«,
Voo ::: Pin 16
Vss

.--_ _ _ TRANSFER

ENABLE

::: Pin 9

RESET

4023B

Fig. 17

Simple Time Generator for a Digital Tachometer

7-245

47238
DUAL 4-BIT ADDRESSABLE LATCH
DESCRIPTION - The 47238 is a Dual 4-8it Addressable Latch with common control inputs; these
include two Address Inputs (AO, A1), an active LOW Enable Input (E) and an active HIGH Clear Input
(CL). Each latch has a Data Input (D) and four Outputs (00-03).

LOGIC SYMBOL

When the Enable (E) and Clear (CL) Inputs are HIGH, al.l Outputs (00-03) are .hOW. Dual4-channel
demultiplexing occurs when the Clear Input (CL) is HIGH and the Enable Input (E) is LOW.
When the Clear (CL) and Enable fE) inputs are LOW, the selected Output (00-03),~etermined by the
Address Inputs (AO, A1), follows the Data Input (0). When the Enable Input (ELgoes HIGH, the
contents of the latch are stored. When operating in the addressable latch mode (E ~ CL ~ LOW),

changing more than one bit of the address (AO, A1) coul~ impose a transient wrong address.
Therefore, this should only be done while in the memory mode (E

~

HIGH, CL

~

LOW).

Voo = Pin 16
VSS = Pin 8

•
•
•
•
•
•

CONNECTION DIAGRAM
DIP (TOP VIEW)

SERIAL-TO·PARALLEL CAPABILITY
OUTPUT FROM EACH STORAGE BIT IS AVAILABLE
RANDOM (ADDRESSABLE) DATA ENTRY
ACTIVE HIGH DECODING OR DEMUL TlPLEXING CAPABILITY
EASI L Y EXPANDABLE
ACTIVE HIGH COMMON CLEAR

PIN NAMES
AO,A1
D a, Db

Address Inputs
Data Inputs

E

Enable Input (Active LOW)
Clear Input (Active HIGH)
Parallel Latch Outputs

CL
00a- 0 3a, °Ob- 0 3b

NOTE:

The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual In~line Package.

LOGIC DIAGRAM

Voo
VSS

= Pin
= Pin

16
8

0= Pin Numbers
7-246

FAIRCHILD CMOS • 4723B
MODE SELECTION

E

MODE

CL

L

L

Addressable Latch

H

L

Memory

L

H

Dual 4-Channel Demultiplexer

H

H

Clear

H = HIGH Level
L = LOW Level

TRUTH TABLE
CL

E

D

AO

A1

00

H

H

X

X

X

L

H

L

L

L

L

L

H

L

H

L

L

H

H

L

L

H

L

L

H

L

H

H

L

L

H

L

L

L

H

H

L

H

L

H

L

L

H

L

L
L

MODE

02

03

L

L

L

Clear

L

L

L

Demultiplex

L

L

L

L

L

L

H

L

L

L

L

L

L

H

L

L

H

L

H

H

L

L

L

L

H

H

H

L

L

L

H

H

X

X

X

ON-1

ON-1

°N-1

ON-1

Memory

L

L

L

L

L

°N-1

°N-1

°N-1

Addressable

L

L

H

L

L

H

ON-1

Latch

L

L

H

L

ON-1

ON-1
L

°N-1

L

°N-1

ON-1

L

L

H

H

L

°N-1

H

L

L

L

H

°N_1

ON-1

°N-1
L

°N-1

L
L

L

H

L

H

ON-1

°N-1

H

L

L

L

H

H

ON-1

°N-1

°N-1

ON-1
L

L

L

H

H

H

ON-1

°N-1

°N-1

H

01

°N-1

•

L
LOW Level
H
HIGH Level
X
Don't Care
ON-1 = State before the positive
transition of the Enable Input

DC CHARACTERISTICS: VDD as shown, VSS

=0 V

(See Note 1)
LIMITS

SYMBOL

PARAMETER

VDD - 5 V
MIN

Quiescent
Power

100

Supply
Current

XC
XM

TYP

VDD -10 V

MAX

MIN

TYP

UNITS

VDD -15 V

MAX

MIN

TYP

20

40

80

150

300

600

5

10

20

150

300

pOD

Notes on following page.

7-247

TEMP

TEST CONDITIGr,S

MAX
JJ.A
JJ.A

MIN,25°C
MAX

All inputs at

MIN,25°C

o Vor VDD

MAX

FAIRCHILD CMOS • 4723B
AC CHARACTERISTICS AND SET·UP REOUIREMENTS: VDD as shown, VSS ~ 0 V, TA ~ 25°C (See Note 2)
LIMITS
SYMBOL

PARAMETER

VDD
MIN

tpLH
tpHL
tPLH

Propagation Delay, E to On
Propagation Delay, D to On

tpHL

~5

VDD~10V

V

TYP

MAX

110
110
95
95

MIN

TYP

MAX

225

50

225

50

200
200

VDD
MIN

~

15V

UNITS

TYP

MAX

100

35

80

100

35

80

45

85

30

68

45

85

30

68

tpLH

Propagation Delay,

120

250

55

100

40

80

tpHL

Address to On

120

250

55

100

40

80

tpHL

Propagation Delay, CL to On

95

190

45

85

30

68

75

135

40

70

25

45

75

135

40

70

25

45

tTLH

Output Transition Time

tTHL
ts

Set·Up Time, D to E

50

30

30

10

24

30

15

30

15

24

5
10

90

30

35

10

28

5

0

-5

5

0

4

0

th

Hold Time, D to E

ts

Set·Up Time, Address to E

th

Hold Time, Address to E

-

TEST CONDITIONS

ns
ns
ns
ns
ns

CL~50pF,

RL

~

200 kn

Input Transition
Times';; 20 ns

ns
ns

twE

Minimum E Pulse Width

70

50

35

20

28

15

ns

twCL

Minimum CL Pulse Width

70

50

35

20

28

15

ns

NOTES:
1. Additional DC Characteristics are listed in this section under 40008 Series CMOS Family Characteristics.
2. Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.

SWITCHING WAVEFORMS

NOTES:
1. Set-up and Hold Times are shown as positive values but may
be specified as negative values.
2. The Address to Enable Set-up Time is the time before the
HIGH-ta-LOW Enable transition that the Address must be
stable so that the correct latch is addressed and the other
latches are not affected.

~

/50%

CL _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _....

~

MINIMUM PULSE WIDTH FOR E AND CL AND SET·UP
AND HOLD TIMES, 0 TO E AND An TO E

7·248

FAIRCHILD CMOS. 472GIB

TYPICAL ELECTRICAL CHARACTERISTICS

PROPAGATION DELAY, D TO
an' VERSUS
LOAD CAPACITANCE

POWER DISSIPATION
VERSUS FREOUENCY
1000

180

TA1.1jJ c

TA

I

L.U
15V ~

VOO

~~
~

~~

""

VOl

~

60

~

±

20

20

3

I'

40

-

60

'" '\0\1
tp\..\,\,\lOOI

;;;.-

_

f..--"!:: _,sV

tPLI-I' 'tf'I-IL' '100

80

100

120

1-

140

PROPAGATION DELAY, EO TO
an' VERSUS
LOAD CAPACITANCE

PROPAGATION DELAY, D TO
an' VERSUS TEMPERATURE
120

I I
I

./

V

~ 120

~

P >--

~

~

~

I

a

~

i'o

w~v

I' 40

", '\0\1

'tp\'\\.~

CL - LOAD CAPACITANCE - pF

160

80

/'

60

20

140

!f

80

.I.~

w\.~'

INPUT FREQUENCY - Hz

IW, 180

:. 100

V
V

V

~ 40

Cl"'15pF - Cl = 50pF - -

g

t

~
~

ri

U

"o

~ 120

::::

0

~-

,/

:l

TA = 25 C

o

./

0100

I 220
0"
200

~

-.l(P*'

""'~

~ 140

V

240

o
z

D

o

V

""

2S C

cJ

~

~~~

~~

I'>i

=

I 160

.,.- .......- ~

;..-

.. 20

f.=

160

_,oVtpl-lL' VOD

I

30

J
~

20

3

10

1'-

o

I'

'tf'Lti' tpHL' \100 '" ltN

60

Cl

100

>'
~ 80

I .J:;v

tpLH' Voo - ,\0'11

40

',0

'" 10\1

H,\ILI--

t PL

=-

-60 -40

tpLl-i. tpHL'

-20

0

20

40

60

~OD "'I 15\1 r-

80

100 120

TA -- AMBIENT TEMPERATURE - QC

Cl - LOAD CAPACITANCE - pF

7-249

160

140

47248
8-BIT ADDRESSABLE LATCH
DESCRIPTION - The 4724B is an 8-Bit Add~ssable Latch with three Address Inputs (A(j-A21. a
Data Input (01. an active LOW Enable Input (EI. an active HIGH Clear Input (CLi and eight Parallel
latch Outputs (QO-Q71.

LOGIC SYMBOL
14

13

1

2

3

When the Enable (EI and the Clear (CLi Inputs are HIGH. all Outputs (QO-Q71 are LOW. Eightchannel demultiplexing or active HIGH 1-of-8 decoding with output enable operation occurs when

the Clear Input (CLI is HIGH and the Enable Input (EI is LOW.
When the Clear (CLI and Enable (1':) Inputs are LOW. the selected Output (QO-Q7Ijdetermined by the
address Inputs AO-A21 follows the Data Input (01. When the Enable Input (EI goes HIGH. the
contents of the latch are stored. When operating in the addressable latch mode (1': ~ CL ~ LOWI.
changing more than one bit of the address (AO-A2) co~ld impose a transient wrong address. Therefore,
this should only be done while in the memory mode (E ~ HIGH. CL ~ LOWI.
•
•
•
•
•
•

SERIAL-TO-PARALLEL CAPABILITY
EIGHT BITS OF STORAGE WITH THE OUTPUT OF EACH BIT AVAILABLE
RANDOM (ADDRESSABLEI DATA ENTRY
ACTIVE HIGH DEMUL TIPLEXING OR DECODING CAPABI LlTY
EASI L Y EXPANDABLE
COMMON ACTIVE HIGH CLEAR

4724B

15

4

5

6

Voo
VSS

7

9

10

11

12

= Pin
:=:

16
Pin 8

CONNECTION DIAGRAM
DIP (TOP VIEW)
16
15

PIN NAMES
AO-A2

o
E
CL
QO-Q7

14

Address Inputs
Data Input
Enable Input (Active LOWI
Clear I nput (Active H IG H)
Parallel Latch Outputs

13
12

11
10

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual In-line Package.

LOGIC DIAGRAM
CL

~@

7-250

V DO "" Pin 16
VSS = Pin 8

o

= Pin Numbers

FAIRCHILD CMOS • 4724B

MODE SELECTION
E

CL

L

L

Addressable Latch

H

L

Memory

MODE

L

H

Active HIGH 8-Channel Demultiplexer

H

H

Clear

L

=

LOW Level

H

=

HIGH Level

TRUTH TABLE
PRESENT OUTPUT STATES
CL

E

D

AO

A1

A2

H

H

X

X

X

X

H

L

L

L

L

H

L

H

L

L

H

L

L

H

L

L

L

H

L

H

H

L

L

L

H

L

H

H

H

H

L

L

H

X

X

X

X

L

L

L

L

L

L

QN-1
L

L

L

H

L

L

L

H

L

L

L

H

L

L

L

L

H

H

L

MODE

QO

Q1

Q2

Q3

Q4

Q5

Q6

Q7

L

L

L

L

L

L

L

L

CLEAR

L

L

L

L

L

L

L

L

L

DEMULTIPLEX

L

H

L

L

L

L

L

L

L

L

L

L

L

L

L

L

H

L

L

L

L

L

L

L

L

L

L

L

L

H

QN-1

QN-1

QN-1

QN-1

QN-1

QN-1
L

L

QN-1

H

QN-1

L

L

L

H

H

H

QN-1

L

L

H

H

H

H

QN-1

•
•
•

MEMORY
ADDRESSABLE
LATCH

~

QN-1

•

•
•

QN-1

L

QN-1

H

•

L = LOW Level

H

=

HIGH Level

X

=

Don't Care

QN-1 = State Before the Positive Transition of the Enable Input

DC CHARACTERISTICS: VDD as shown, VSS = 0 V ISee Note 1)
LIMITS
SYMBOL

PARAMETER
MIN
Quiescent

Power

IDD

Supply

Current

XC
XM

VDD-10V

VDD - 5 V
TYP

MAX

MIN

TYP

UNITS

VDD-15V

MAX

MIN

TYP

20

40

80

150

300

600

5

10

20

150

300

BOO

Notes on following page.

7-251

TEMP

TEST CONDITIONS

MAX
p.A
p.A

MIN,25°C
MAX

All inputs at

MIN,25°C

o Vor VDD

MAX

FAIRCHILD CMOS • 47248
AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VDD as shown, VSS = 0 V, T A = 25°C (See Note 2)
LIMITS
SYMBOL

PARAMETER

MIN

-

tPlH

Propagation Delay, E to Q n

tpHl
tplH

Propagation Delay, D to Q n

tpHl

VDD=10V

VDD = 5 V
TYP

MAX

MIN

TYP

MAX

UNITS

VDD = 15V
MIN

TYP

MAX

110

225

50

100

35

80

110

225

50

100

35

80

95

200

45

85

30

68

95

200

45

85

30

68

tplH

Propagation Delay,

120

250

55

100

40

80

tPHl

Address to Q n

120

250

55

100

40

80

tPHl

Propagation Delay, Cl to Q n

tTlH

Output Transition Time

tTHl

95

190

45

85

30

68

75

135

40

70

25

45

75

135

40

70

25

45

ts

Set-Up Time, D to E

50

30

30

10

24

5

th

Hold Time, D to E

30

15

30

15

24

10

ts

Set-Up Time, Address to E

90

30

35

10

28

5

th

Hold Time, Address to E

0

-5

5

0

4

0

-

-

TEST CONDITIONS

ns
ns
ns
ns
ns

Cl=50pF,
Rl=200k.l1
J nput Transition

Times';;;;; 20 ns
ns
ns

twE

Minimum E Pulse Width

70

50

35

20

28

15

ns

twCl

Minimum Cl Pulse Width

70

50

35

20

28

15

ns

NOTES:

1.
2.

Additional DC Characteristics are listed in this section under 40008 Series CMOS Family Characteristics.
Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.

SWITCHING WAVEFORMS

NOTES:

1. Set-up and Hold Times are shown as positive values but may
2.

be specified as negative values.
The Address to Enable Set-up Time is the time before the HIGHto~LOW Enable transition that the Address must be stable so
that "the correct latch is addressed and the other latches are
not affected.

MINIMUM PULSE WIDTH FOR E AND Cl
AND'sE.T-UP AND HOLD TIMES, 0 TO E AND An TO

E

7-252

FAIRCHILD CMOS. 4724B

TYPICAL ELECTRICAL CHARACTERISTICS

PROPAGATION DELAY, DTO
an, VERSUS
LOAD CAPACITANCE

POWER DISSIPATION
VERSUS FREOUENCY
1000

180

TA'o'JJ C

I

1

<5

~

g 140
o
>-'

~~ ~

~~

V~

~~
;..-

"",I-'

~
~

"o~

103

;:::::::

1>
20

107

I

~ 200
IW, 180

~

ill

160

" 100
Joo 1-

PROPAGATION DELAY, D TO
an' VERSUS TEMPERATURE

w>(-.\/

"oz 140

~

120

I I

TA = 25'''C
I 220

..-,:;:::; ;:::::::

40
CL

PROPAGATION DELAY, E TO
an' VERSUS
LOAD CAPACITANCE

0<

./"
'" '\0\1

INPUT FREQUENCY - Hz

240

I.~

~;..--

w\.,~

W'r\\..'~

0

"''5

106

V

./"

"'_ 20

CL""5pF-CL=50pF - -

!~

80

~ 40

104

V

V

it

liDni
I

./

120

~010 0

v:
I-'

~o<>

,.-?-y

1 160

IVOO'" lQV
Voo" 15

TA = 25"C

~

:5

10

1>

o

~

-60 -40

_ '\0'11

tpLH' tpHL' Voo "'115\/

-20

0

20

40

60

80

7-253

I--

100 120

TA _. AMBIENT TEMPERATURE _

CL - LOAD CAPACITANCE - pF

.'""-

v.5:::r---

°c

140

4725B/4725BX
64-81T (16 x 4) RANDOM ACCESS MEMORY
WITH 3-STATE OUTPUTS
DESCRIPTION - The 4725B/4725BX is a 64-Bit Random Access Memory with 3-State Outputs
organized as 16 words by four bits with four Data Inputs (00-03), four Address Inputs (AO-A3),
an active LOW Write Enable Input (WE), an active LOW Chip Select Input (CS) and four active LOW
3-State Outputs (GO-Q3)Information on the fou", Data Inputs (00-03) is written into the memory location selected by the
Address Inputs (AO-A3) when both the Chip Sel~ct..!.nput (Cs) and the Write Enable Input (WE) are
LOW_ Under these conditions, the Outputs (00-03) are held in a high impedance OFF state_
Information is read from the memory location selected by the Address Inputs (AO-A3) while the Chip
Select Input (CS) is LOW and the Write Enable Input (WE) is HIGH_ The Outputs (00-03) are the
complement of the information written into the memory. When the Chip Select Input (CS) is HIGH,
all Outputs (00-03) are held in the high impedance OFF state. This allows other 3-State outputs to be
wired together in a bus arrangement. The 4725B/A725BX offers fully static operation. Th.e 4725B is
specified to operate over a power supply voltage range of 4.5 to 12.5V. The 4725BX is specified to
operate over a power supply voltage range of 3 to 15V.
•
•
•
•
•
•

3-STATE OUTPUTS
ORGANIZATION - 16 WORDS X 4 BITS
ON·CHIP DECODING
INVERTED DATA OUTPUT
FULLY STATIC OPERATION
TYPICAL HOLDING VOLTAGE OF 1.5V

LOGIC SYMBOL

4

6 10 12

AO
15

A,

'4

A2

13

A3

4725B/4725BX

5

7

9 11

CONNECTION DIAGRAM
DIP (TOP VIEW)

MODE SELECTION
CS

WE

MODE

OUTPUTS

L

L

High Impedance

L

H

Outputs are Complement of
Data Written into Location

H

X

High Impedance

Write

Read
Inhibit

LOGIC DIAGRAM
12

@cs---q:>---'-+""""t'='~>-t""t-r"'-----,
(DWE---ql~------~~H+--~t-~---,

10

Voo"" Pin 16
VSS = Pin 8
ADDRESS
DECODER

...
...
...
•••

NOTE:
16X4
ARRAY
MEMORY
CELL

= Pin

outs ,(Connection

Diagram)

as the

Dual In-line Package.

PIN NAMES
CS
Chip Select Input (Active
LOW)
Ii'iIl:
Write Enable Input (Active
LOW)
Data Inputs
00- 0 3
Address Inputs
AO-A3
3-State Outputs (Active
00-Q3
LOW)

Voo - Pin 16
VSS - Pin 8

o

The F latpak version has the same pin-

Number

7-254

FAIRCHILD CMOS • 4725B/4725BX
DC CHARACTERISTICS: VDD as shown, VSS

~

0 V (See Note 11
LIMITS

SYMBOL

PARAMETER

VDD
MIN

Current HIGH

Current LOW

MIN

TYP

MAX

MIN

TYP

Quiescent

12
0.4

XM

MAX

J1A

MIN,25°C

-0.4
20

40

80

300

600

5

10

20

150

300

600

to

VOD,

Cs ~

VDD

MIN,25°C
MAX

J1A

MIN,25°C

Output Returned

Cs ~

to VSS,

VOD

MAX

- 12
150

Output Returned

MAX

-1.6

XM

Current

TEST CONDITIONS

MIN,25°C

12
-12

XC

Supply

TEMP

MAX
1.6

XM

Power

IDD

MAX

UNITS

VDD-15V

VDD-l0V

XC

Output OFF
IOZL

TYP

V

XC

Output OFF
IOZH

~5

MIN, 25°C
MAX

J1A

MIN,25°C

All inputs at

oV

or VDD

MAX

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VOD as shown, VSS ~ 0 V, TA ~ 25°C (See Note 21
LIMITS
SYMBOL

PARAMETER

VOD
MIN
-

~

VDD~10V

5 V

TYP

MAX

MIN

TYP

MAX

VDD ~ 15 V
MIN

UNITS

TYP

MAX

READ MODE
tPLH

Propagation Delay,

250

500

98

196

65

130

tpHL

Address to Output

250

500

98

196

65

130

55

110

24

50

18

36

66

135

30

60

22

44

53

100

66

28

56

60

120

?3
30

60

23

46

65

130

30

60

25

50

75

150

35

70

25

50

tpZH

Enable Time,

tpZL
tpHZ

Cs to

,

Output

Disable Time, CS to Output

tPLZ
tTLH

Output Transition Time

tTHL

ns

TEST CONDITIONS

CL ~50pF,
RL ~ 200 kn.
I nput Transition

Times
ns
ns

~

20 ns

RL ~ 1 kn. to VSS
RL ~ 1 kn. to VDD
RL~l

kn.toVSS

RL ~ 1 kn. to VDD
ns

WRITE MODE
tpZH

Enable Time, WE to Output

tpZL
tpHZ

Disable Time, WE to Output

tPLZ

-

-

69

138

28

56

20

40

83

166

35

70

24

48

60

120

26

52

18

36

72

144

32

64

24

48

twWE

Minimum WE Pulse Width

160

79

72

36

52

26

ts

Set-Up Time, Dn to WE

170

85

80

39

60

30

24

12

12

6

7

3

31)0

150

160

80

120

60

0

-40

0

-20

30

-15

3UO

150

160

80

120

60

80

40

40

20

30

15

th

Hold Time, Dn to WE

ts

Set-Up Time, Address to WE

th

Hold Time, Address to WE

ts

Set-Up Time, CS to WE

th

Hold Time,

Cs to WE

Notes on following page

7-255

ns
ns

ns
ns
ns

ns

RL

~

1 kn. to VSS

RL ~ 1 kn. to VDD
RL~

1 kn. to VSS

RL ~ 1 kn. to VDD

•

FAIRCHILD CMOS • 4725B/4725BX
NOTES:
1. Additional DC Characteristics are listed in this section under 40008 Series CMOS Family Characteristics.

2. Propagation Delays and Output Transition Times are graphically described in this section under 4000B Series CMOS Family Characteristics.
3,

All Set-Up (t s ) and Hold (th) times are measured with minimum Write Enable Pulse Width (twWE).

SWITCHING WAVEFORMS

READ MODE

90%

CS TO OUTPUT ENABLE AND DISABLE TIMES

WRITE MODE

-}
+
tpHZ

OUTPUT

90%

50%

50%

tpZH

HIGH Z

'- ::2".!:: :::~E

r-

HIGH Z
10%

10%

"OFF" STATE

WE TO OUTPUT ENABLE AND DISABLE TIMES

MINIMUM WE PULSE WIDTH AND SET-UP AND HOLD TIMES,
On TO WE. An TO WE. AND CS TO WE
Note: Set-up and Hold Times are shown as positive values but
may be specified as negative values.

7-256

90%

47278
7-STAGE COUNTER
DESCRIPTION - The 4727B is a 7-Stage,Frequency Counter especially useful for frequency synthesis

LOGIC SYMBOL

in musical applications. The device is designed to generate, from a primary chromatic scale, each of the
twelve flats, sharps, and naturals comprising each chromatic scale of the seven additional octaves in the

musical spectrum. Twelve 4727B devices are required to generate the entire musical spectrum from a
primary scale.

CPo

00

14

The 4727B consists of a pair of 2-Bit Counters, with Clock Inputs (CPO and CP2) and Parallel Outputs
(QO and Q1, Q2 and Q3), available, and three 1-bit counters, also with Clock Inputs (CP4, CP5, and
CP6) and Parallel Outputs (Q4, Q5' and Q6) available. Each counter advances on a LOW-to-HIGH
transition at the appropriate Clock Input.

CP2

0,

13

02

12

CP4

4727B

CPs

03

11

CPS

04

10

aS

•
•
•

REPEATS A PRIMARY MUSICAL NOTE OR HALF NOTE IN SEVEN OCTAVES
CLOCK INPUT EDGE - TRIGGERED ON THE LOW-TO-HIGH TRANSITION
BUFFERED OUTPUTS AVAILABLE FROM ALL SEVEN STAGES

Oa
voo "PIN 7
VSS"PIN1

CONNECTION DIAGRAM
DIP (TOP VIEW)
PIN NAMES
CPO-CP6

CLOCK INPUTS (L--H TRIGGERED)

14
13

PARALLEL OUTPUTS

12
11
10

NOTE:
The F l;:Itpak version has the same
pinouts (Connection Diagram) as the
Dual In-Line Package.

BLOCK DIAGRAM

o CPo ---£>0-01
CD CP2--[>O_____________-'
Q0 CP4--[>O------------------------------------------'
o CP5--[)o------------------------------------------------'
0CP6---{)<~-----------------------------------------------------~
V DD = PIN 7
VSS= PIN 1
= PIN NUMBER

o

7-257

•

FAIRCHILD CMOS. 4727B
=0

DC CHARACTERISTICS: V DD as shown, VSS

V (See Note 1)
LIMITS

SYMBOL

PARAMETER

V DD = 5 V
MIN

Output

High

IOH

Current

IOL

TYP MAX

V DD =15V

TYP MAX

MIN

MIN

-0.3

-0.84

-1.8

-0.25

-0.7

-1.5

-0.2

-0.56

-1.1

Output

0.64

1.6

4.2

Low

0.51

1.3

3.4

Current

0.36

0.9

Quiescent
XC

Power

IDD

V DD =10V

Supply
XM

Current

TEMP

UNITS

TYP MAX
VOUT =4.5 VFor
VDD=5V.

MIN

VOUT = 9.5 V For
VDD=10V.

25° C

mA

MAX

VOUT = 13.5 V
For VDD = 15 V.

MIN

2.4

MAX

40

80

150

300

600

5

10

20

300

600

=0

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: V DD as shown, VSS

Inputs at

VOUT = 0.4V
VSSorVDD
for VDD = 5V
Per the
VOUT =0.5V
Logic
for VDD = 10 V
Function or
VOUT = 1.5 V
for VCC = 15 V Truth Table

25°C

mA

20

150

TEST CONDITIONS

MIN,25°C
IJ.A

MAX
MIN,25°C

IJ.A

All Inputs at V DD Or VSS

MAX

V, TA = 25°C (See Note 2)

LIMITS
SYMBOL

PARAMETER

VDD = 5 V
MIN

VDD=10V

TYP

MAX

MIN

TYP

MAX

UNITS

VDD=15V
MIN

TYP

TEST CONDITIONS

MAX

tpLH

Propagation Delay,

225

500

90

250

75

200

tpHL

CP n to QO, Q2, Q4, Q5 or Q6

225

500

90

250

75

200

tpLH

Propagation Delay,

365

1000

130

500

100

400

tpHL

CP n to Ql or Q3

365

1000

130

500

100

400

tTLH

Output Transition

70

500

40

250

30

200

tTHL

Times

70

500

40

250

30

200

TwCP

Min Clock Pulse Width

ns

ns

CL = 50 pF
RL = 200 kn

125

125

65

100

50

ns

2

4

4

8

5

10

MHz

(Note 3)

Input Transition

Times

250

Input Count Frequency

fMAX

ns

~

20 ns

NOTES:

1. Additional DC characteristics are listed In this section under "40008 Series CMOS Family Characteristics,"
2. Propagation Delays and Output Trans'itlon Times are graphically described In this section under "4000B Series CMOS Family
Characteristics, "
3. For f MAX input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.

SWITCHING WAVEFORMS
~twCP--'"

CPo

J
tpLH

"50%

j

~

tpHL

,

/50%

00, Q2, Q4, 05 or 06

\

11'50%

\

50%

~

,

..

50%

\.

\.

1/fmax

,'/,,0%

•

\50%

-.~'~

-.'~}
50%

°1 orQ3

PROPAGATION DELAY, CP to Qn, MINIMUM CLOCK PULSE WIDTH
AND MAXIMUM FREQUENCY

7-258

50%

4731B/4731BX
QUAD 64-81T STATIC SHIFT REGISTER

DESCRIPTION - The 4731 B/4731 BX is a Quad 64-Bit Shift Register each with separate Serial Oata
Inputs (OA-OO), Clock Inputs (CPA-CPO) and Oata Outputs (Q63A-Q630) from the 64th register

LOGIC SYMBOL

position.
Information present on the Serial Data Inputs is shifted into the first register position and all the data
in the register is shifted one position to the right on a HIGH-ta-LOW transition of the Clock Inputs
(CPA-CPO).
Low impedance outputs are provided for direct interface to TTL. The 47318 is specified to operate
over a power supply v,oltage range of 4.5 V to 12.5 V, the 4731 BX is specified to operate over a power
supply voltage range of 3 V to 15 V.
•
•
•
•
•

FREQUENCIES UP TO 8 MHz AT VDD = 10 V
SERIAL-TO-SERIAL DATA TRANSFER
SEPARATE CLOCK INPUTS, DATA INPUTS AND
FULLY BUFFERED OUTPUTS FOR EACH REGISTER
DIRECT INTERFACE TO TTL
14-PIN PACKAGE

11
10

12

13

60

PIN NAMES

C

OA-OO

Serial Oata Inputs

CPA-CPO

Clock Input (H->L Edge-Triggered)

~3A-~30

Buffered Outputs from the 64th Register Position

5

0ri3C

1

eP e

00
°630
CPo

VDD
VSS

Pin 14
Pin 7

CONNECTION DIAGRAMS
DIP (TOP VIEW)

LOGIC DIAGRAM
1/4 OF A 4731B/4731BX

14
13

a

12

a

a

t1

FFO

FFl

FF3

FF'

10

FLATPAK (TOP VIEW)
16

a

a

a

15
FF60

FF61

FF62

FF63

14
13
063

@ocG)ocC2)oc 0

12

11

VDO= Pin 14

10

VSS = Pin 7
= Pin Number

o

7-259

•

FAIRCHILD CMOS • 4731B/4731BX
DC CHARACTERISTICS: VOO as shown, VSS = .0 V (See Note 1)
LIMITS
SYMBOL

PARAMETER

Quiescent

Power
Supply

100

Current

VOO =5 V
MIN TYP MAX

TYP

MIN

25

XM

75'

TYP

MIN

MAX

1.0.0
75.0·

XC

UNITS

VOO-15V

VOO=IDV

TEMP

TEST CONDITIONS

MAX

2.0.0

4.0.0

15.0.0
5.0
15.0.0

3.0.0.0
1.0.0
3.0.0.0

MIN,25°C

jJ,A
jJ,A

MAX

All inputs.at

MIN,25°C

DVorVOD

MAX

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VOO as shown, VSS = .0 V, T A = 25°C (See Note 2)
LIMITS
SYMBOL

PARAMETER

MIN
tPLH

Propagation Delay,

tPHL
tTLH

CP to Q63

Output Transition Time

tTHL
twCP

CP Minimum Pulse Width

ts

Set-Up Time 0 to CP

th

Hold Time 0 to

3.0.0
1.0.0
1.0.0

CP

Max. Input Clock Frequency
fMAX

(Note 3)

VOO=IDV

VDD = 5 V

1.5

TYP

MAX

19.0
19.0

MIN

TYP

MAX

45.0
45.0

95

45

135

30

3D
1.0.0
-2.0

9.0

2.0.0
2.0.0
7.0
5.0

95

30
-12

35

15.0
4.0
4.0

12

12.0
4.0
4.0

4

3

8

4

5.0

UNITS

VOD = 15V
MIN

TYP

TEST CONDITIONS

MAX

65

16.0

65

160

2.0
2.0
4.0
-7

45
35

ns
ns
ns
ns

11

CL =5DpF,
RL=2DDkn
Input Transition

Times';; 2.0 ns

MHz

14

NOTES:
1. Additional DC Characteristics are listed in this section uncO·· 4000B Series CMOS Family Characteristics.
2. Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.

3.
4.

For f MAX , input rise .. and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.

It is recommended that input rise and fall times to the Clock Input be less than 15 IJ.s at VOO

=

5 V, 4 p,s at VOO == 10 V, and 3 j.Ls at

VOO=15V.

SWITCHING WAVEFORMS

I--lwCP-

CP

u~=-~~d
Is

th

~p~
j ---1~

On

MINIMUM CLOCK PULSE WIDTH
AND SET·UP AND HOLD TIMES, D TO

CP

NOTE:
1. Set-up and Hold Times are shown as positive values but may be specified as negative.values.

7-26.0

47418
4 x 4 CROSS POI NT SWITCH
DESCRIPTION - The 47418 is a 4 X 4 CrosspoLnt Switch consisting of a
and 16 independent bi·directiona~ analog switches arranged in a four by four
such that any
analog switch or any combination of anatog switches may be ON or OFF at anyone time providing
a multitude of anatog input/output switching combinations.
The device has four Address Inputs (A O-A3 1. a Data Input (D), an Enable Input (E) and eight independent analog Input/Outputs (Y O-Y 3 and ZO-Z3)' When the Enable Input (E) is HIGH, the selected
Output (00-015) of the 16-81t Addressable Latch (determined by the Address Inputs, AO-A3) follows the Data Input (D) thus turning the selected analog switch ON or OFF. With the Data Input (D)
HIGH, anyone of the 16 analog switches may be Individually turned ON by first applying the appropriate Address Inputs (AO-A3 ) and then taking the Enable Input (E) HIGH. With the Data Input (D)
LOW, anyone of the 16 switches may be individually turned OFF by first applying the appropriate
Address Inputs (Ao-A3 ) and then taking the Enable Input (E) HIGH. The Enable Input (E) may
remain HIGH as long as the Address Inputs (AO-A3 ) are stable. However, to prevent erroneous switch
selection the Enable Input (E) must be LOW whenever the Address Inputs (Ao-A3 ) are changed.
Atthough onty one switch ata time may be turned ON or OFF, any number or combination of switches
may be ON or OFF at anyone time.

LOGIC SYMBOL
911213

4741B

Zo

15

Z,
Z2

14
10

Z3

11

V DD = Pin 16

VSS = Pin 8

CONNECTION DIAGRAM
DIP (TOP VIEW)
16

•
•
•
•

15

LOW ON RESISTANCE-TYPICALLY 85U at V DD = 10V
ON-CHIP ADDRESS DECODER AND CONTROL LATCHES
INPUT SIGNAL FREQUENCIES UP TO 10 MHz
ANALOG OR DIGITAL CROSSPOINT SWITCH

14
13
12
11

PIN NAMES
Y O-Y 3

ZO-Z3
AO-A3

o
E

10

Analog Input/Outputs
Analog Input/Outputs
Address Inputs
Data Input
Enable Input

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram)
the
Dual In-Line Package.

as

7-261

•

FAIRCHILD CMOS. 47418
BLOCK DIAGRAM

~--~--~-+---+---4_+--_+--~~20

..----------t------I---'

@)

0

10
VOO - POWER SUPPLY VOLTAGE - V

VIN - INPUT VOLTAGE - V

TYPICAL
TRANSFER CHARACTERISTICS

GUARANTEED TRIP
POINT RANGE

VDD __________________-,~-----------

V,. -----------f-\/-lr---AcI--¥\----------INPUT
VOLTAGE

Vss

-'------'----+-------------'C--------'-

OUTPUT
VOLTAGE

vss-------~-----...J

LOW POWER OSCILLATOR

TYPICAL APPLICATION

voo-------------------

R

"~'om
J

c

v ss

----+-+-+--I-+---VIN vs

1/6 OF A 400148

vo0=tftfl
_

t2 ---

_t1_
VSS

NOTE:

The equations assume that t 1 + t2 ~ tpLH + tpH L'

7-264

VOUT vs

tinlC

400858/74C85/54C85
4-81T MAGNITUDE COMPARATOR
DESCRIPTION - The 40085B is a 4-Bit Magnitude Comparator which compares two 4-bit words
(A, B), each word having four Parallel Inputs 1AO-A3,BO-B3); A3,B3 being the most significant inputs.
Operation is not restricted to binary codes, the device will work with any monotonic code. Three
Outputs are provided: "A greater than B" IOA>B), "A less than B" IOAB, IAB = L, IA=B = H. For serial (ripple) expansion, the 0A>B, 0AB. 'AB, OAB, IAB
°A~4-~~

0AB

13
12
11

AO~""'1-D~~~~------il-r~

10

VOO
80

'A'8

@

=

Pin 16

VSS = Pin B
o = Pin Number

o

~<>-_ _ _ _ _ _ _~~~a..)-----I><>-----o~ °A'8

7-265

NOTE:
The F latpak version has the same
pinouts (Connection Diagram) as the
Dual In-line Package.

•

FAIRCHILD CMOS • 40085B/74C85/54C85
TRUTH TABLE
CASCADING
INPUTS

COMPARING INPUTS

OUTPUTS

Aa.Ba

A2.B2

A,.B,

AO.BO

IA>B

IAB

°AB3

X

X

X

X

X

X

H

l

l

A3B2

X

X

X

X

X

H

l

l

A3=B3

A2B,

X

X

X

X

H

l

l

A3=B3

A2=B2

A,BO

X

X

X

H

l

l

A3=B3

A2=B2

A1=B1

AO'

~ 100
'-"
«

tpHL' VoO '" 10 V

!-50

tpU-l. VoO '"

~5 V

iHL,Vt40

60

80

~

I - r-

-15V

I

100

~

"oz

~ 10 \'

120

140

---

"

.,olv_

WLH'VO~

tpr\L' VoO '" 10:';V

-15 V

1PLI' 'PHI' 00 1

20

CL - LOAD CAPACITANCE - pF

"00

50

-

160

-

~

W\\\..'

~",VOo·I'-

~

tPLH,' "00

20

250

I

r5

" 150

~

a:

60

TA'" 25 C

~O\)""

"is 100

..~

40

300
TA'" 25°e

~

20

PROPAGATION DELAY
In TO On VERSUS
LOAD CAPACITANCE

300
~
I

>-' 150

0

TA - AMBIENT TEMPERATURE _

PROPAGATION DELAY
An OR Bn TO On VERSUS
LOAD CAPACITANCE

a:a 200

I

o
TA - AMBIENT TEMPERATURE _

a:

\J 0",,'0 V
0

tPLH' tpH\..' VOD '" 15 V

20

-60 -40 -20

"
.i

-\V\"'""

...... ........

100

"~
~

0

o

0
f2

,.~~r"'"

l-

e
-: 120

80

~~~

0140

.......

....

..-

I 160

r- f--- / w\..~,wy.p

>

"z
"i=
'-"
"
"is

I

- - C L " 15pF
Cl "'50pF

PROPAGATION DELAY
An OR Bn TO On.
VERSUS TEMPERATURE

:to

V

..... V'

~~ vi<

INPUT FREQUENCY

~

~

"

40

60

80

lOa

120

CL - LOAD CAPACITANCE - pF

7-267

140

160

•

FAIRCHILD CMOS • 40085B/74C85/54C85
APPLICATIONS

A>'
A8
L - IAB
°A8

t--

8 19 -

IAB
400858

°A<..B

#1

L-

-

-

°A=B r-NC

IA=B

INPUTS

AlO All A12 A13 BlO Bll B12 B13

AS A6 A7 Aa BS B6 B7 Ba

f I" I I f I i

r

AO Al A2 A3 80 Bl B2 B3

A,-

',-

,

A

r

IA>B
iAB
°AB
°A>B

',-

IAB

B14 -

IAB

'---

°A<6

,--

°A=B I-NC

I

I

AO Al A2 A3 BO
IA>B
IA8
°A---{

lA

2l-,...;..;.------I

2A
4l------+--I

S }-...;;3;;.,A'--_ _-+_--I

4 l-.;;;2;..;A'--_ _-+_-I

>---{

6 l-..;;.3A'-'-_ _ _+-_-I ~~--(

12}-~----~--~

15}---=--OI

>------'
= Pin Numbers

== Pin Numbers

7·269

FAIRCHILD CMOS • 400978 • 400988
DC CHARACTERISTICS: VOO as shown, VSS = 0 V (See Note 1)
LIMITS
SYMBOL

PARAMETER

VOO = 5 V

VOO=10V

UNITS

VOO=15V

MIN TYP MAX MIN TYP MAX

MIN

TEMP

TEST CONDITIONS

TYP MAX
VOUT=4.5 V for VOO=5 V

IOH

Output HIGH

-1.0

-2.0

-3.2

Current

-0.7

-1.4

-2.2

VOUT = 9.5 V for VOO = 10 V

MIN,25"C

mA

VOUT = 14.5 V for VOO = 15 V

MAX

Inputs at VSS or VOO
Per Logic Function

VOUT = 0.4 V for VOO = 5 V

IOL

Output LOW

2.5

6.25

11.25

Current

1.8

4.5

8.25

VOUT = 0.5 V for VOO = 10 V

MIN,25"C

mA

VOUT = 0.5 V for VOO = 15 V

MAX

Inputs at VSS or VOO
Per Logic Function

Output OFF
IOZH

Current HIGH

Output OFF
IOZL

Current LOW
Quiescent

12

Supply

MAX

/lA

MAX

12

XC

MIN, 25"C

-12
-0.4

XM

MAX

/lA

8

16

30

60

120

1

2

4

30

60

120

Output Returned to VSS,

MIN,25"C EOn = VOO

-12
4

Output Returned to VOO,

MIN,25"C EOn = VOO

-1.6

XM

Current

0.4

XM

XC

Power

100

MIN,25°C

1.6

XC

MAX
MIN,25"C
MAX

/lA

MIN,25"C

All Inputs at 0 V or VOO

MAX

AC CHARACTERISTICS AND SET·UP REQUIREMENTS: VOO as shown, VSS = 0 V, TA = 25"C, 40097B only (See Note 2)
LIMITS
SYMBOL

PARAMETER

VOO = 5 V
MIN

tPLH

Propagation Delay

tpHL

Data to Output

I

TYP

VOO=10V

MAX

MIN

TYP

MAX

UNITS

VOO=15V
MIN

TYP

65

100

25

40

20

32

80

100

28

40

20

32

70

110

35

55

29

44

tpZL

95

150

40

65

30

52

tpHZ

40

65

31

55

29

44

tPLZ

60

95

35

55

30

44

tTLH

40

65

25

40

15

30

30

60

15

30

15

30

tpZH

Output Enable Time

Output Disable Time
Output Transition Time

tTHL
Notes on following page.

7·270

TEST CONDITIONS

MAX
ns
ns
ns
ns

CL = 50 pF,
RL = 200 k>l
(RL = 1 k>l to VSS)
(RL = 1 k>l to VOO)
(RL = 1 k>l to VSS)
(RL = 1 k>l to VOO)
: I nput Transition

Times .-;;;; 20 ns

FAIRCHILD CMOS • 400978 • 400988
AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VDD as shown, VSS = 0 V, TA = 25"C, 40098B only (See Note 2)
LIMITS
PARAMETER

SYMBOL

VOO=10V

VDD = 5 V
MIN

TYP

MAX

MIN

TYP

UNITS

VOO=15V

MAX

MIN

TYP

65

120

30

55

30

44

85

155

35

65

30

52

70

110

35

55

29

44

tPZL

95

170

40

60

30

48

tpHZ

40

70

31

55

29

44

60

105

35

55

30

44

40

65

25

40

15

30

30

60

15

30

15

30

tPLH

Propagation Delay, Data to Output

tPHL
tpZH

Output Enable Time
Outside Disable Time

tPLZ
tTLH

Output Transition Time

tTHL

TEST CONDITIONS

MAX
CL = 50 pF,

ns

RL=200kD.
(RL = 1 krl to VSS)

ns

(RL = 1 krl to VOO)
(RL = 1 kD. to VSS)

ns

(RL = 1 kD. to VOO)
1nput Transition

ns

Times

< 20 ns

NOTES:

1.

Additional DC Characteristics are listed in this section under 40008 Series CMOS Family Characteristics.

2.

Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.

TYPICAL ELECTRICAL CHARACTERISTICS

~1000
~ 100

400988
PROPAGATION OELAY VERSUS
LOAD CAPACITANCE

I

II,
"

~

10

ffi

1.0

Z

010- 1
;::

"

!!:10-2

-;
:Il
~W3

~10-4

0.

400978/400988
P-CHANNEL DRAIN CHARACTERISTICS

T~ ~ 2~"bl

;2

0.

400978/400988
POWER DISSIPATION VERSUS
FREQUENCY

102

I

!

I

: Ii

'

V.~~ = 1~ ,V

I

~

e.:~

~

IV

P:rq: 1" I ~ i
:11
:1.:
--~
.... ~~~ ~i1'
III
....
VOO = 5 V

JJ
.....'"
i!

~;'11

H-voo
I!

11-

II

VG~ - dATE IT~± VG~

I.

/

-!~L- 15 pF

CL

= 50 pF

10 4
INPUT FREQUENCY - H,

V

f--:..--'

I

10 7

~

1-

I

-20

E
I

I-

~30 ~

a:

-40~

(,)

-50z

;;:

/

/
-6

-4

70

~ 60

~ 50
0.

o

40

~ 20

o

VDS - DRAIN TO SOURCE VOLTAGE - V

7-271

o
Z
o

-70 ;".

25°C

-2

90

w 80

-60 ~

o

=

;

100

a:

80 TA

-16 -14 -12 -10 -8

~

-10"

VI

r--- r--tGsLo'v

~ i~ vi '!

I!

1

= 5 V

SOURCE VOLTAGE - V

o

··90

~ 30

--- --- -- tk- -

I
VOO

=

I
5

V~

-7

t-- '\..

t----

-- ~

(~L

C-

,7

Voo ·15 V

10
00

''1LH

~

Voo - 10 V,"",

r--

0.

~
!-

~L_

TA'-:; 25°C

20

40

60

tPLH

"'-'PHL_

I

I
,

80 100 120 140 160

CL - LOAD CAPACITANCE - pF

•

FAIRCHILD CMOS • 400978 • 400988
TYPICAL ELECTRICAL CHARACTERISTICS (Cont'd)

40098B

40098B

40098B

N,CHANNEL DRAIN CHARACTERISTICS

PROPAGATION DELAY VERSUS
TEMPERATURE

OUTPUT TRANSITION TIME
VERSUS LOAD CAPACITANCE

160

120

15V-

VGS

/

E
I

~
I

TA::: 25°C

« 140
~ 100

z

a:

60

o

I 40
Z

E!

20

w

70

~

60

~

a:

B 80
;;:

80

C>

11/

g:
:E

r- -IVO~ ~ ~."; ~

30

1-

~

8

6

10

12

14

~

16

c
I

90

~

80

w

~
;:
iii

40

~

~::J

o

30
20

~

VOO

ff-

40

f-

::J

30

I

20

10"VV

.?-

0

/\ V

\""'j
VOO

20 40 60 80100120140

20

'f-'

..... V

tPHL

TA - AMBIENT TEMPERATURE - °C

1-

V

~'\

40

60

*
tTLH

'y- V

I

o

/

/'

-. f~

tTHL15 V'(

~

80 100 120 140 160

CL - LOAD CAPACITANCE - pF

4oo97B

40097B

PROPAGATION DELAY VERSUS
TEMPERATURE

PROPAGATION OELAY VERSUS
LOAD CAPACITANCE

~

VOO-l0V

v\

bY -"
Voo
40

V

'\ rY
/ IvV

-<
y

V
1-.....

.....,:,..-.::

..........

20

~ '5 V

L

I

o

tTHL

o
~

~

C>

~

1 '"""

---

CL~15

o

~

....

60
50
40

-- to";;
f.- rf--

30

-' 20

~

80 100 120140 160

10

o

I~

·t7

:r

!
=5

~ 10 V

80

tpHL

~

70

~

60

~OOI-

li V

-60-40-200

;:

5 V

-

TA

;

----~-

VOO

90

I

I I
f.--\

L-k -

I

'IHL

pF

70

Z

;7 "\

~ 15 vi/

60

>

:3w

ALH

!

80

I

/'

V60

60

f-

-+
tPLH

t,iY

50

VOO - 5 V

40097B

70

50

15

«
a:

tTLH/

/I

OUTPUT TRANSITION TIME
VERSUS LOAD CAPACITANCE
TA "" 25°C

z
«

~

-60 40 20 0

VOS - ORAIN TO SOURCE VOLTAGE - V

o

VOO

, 10

5 V

60

::J
0-

J

;r

20

70

;:
iii

z

tPHL

rl

z

0

tPL~-

I

TA "" 25°C

80

;:

VOO~5~8

I-

o

VGS GATE TO
SOURCE VOLTAGE - V

4

50

w

~

.ktL _ltPL~-

~

---- f.-~

~ 40

VGS-l0V

II
IV
'V f--iiGS.~

--

90

t~

CL~15pF

5
o

I

f-

Z

90

~ 50

~
f

tPLH1.
/'1 tPHl

U:I

~ 20
~
=5 10

trHll-

20406080100120140

S-

00

TA - AMBIENT TEMPERATURE - °C

CL - LOAO CAPACITANCE - pF

25°C

V~O ~15

VI-""

V09~10V-

/

::: ~
"'" ~

--

VOO

~

15 V

40
~

60

EOn

~tPHZ

OUTPUT

EOn
:V,:tPZH

HIGH Z
"OFF" STATE

90%
'.....

-----

,----

~
10%

10""

OUTPUT

OUTPUT ENABLE TIME
(tpzHI AND OUTPUT DISABLE TIME (tpHZ)

-11--

tPZl

~90%

HIGH Z
"OFF" STATE

\

~

OUTPUT ENABLE TIME
(tPZL) AND OUTPUT DISABLE TIME (tPLZ)

7-272

, - tPHL
tpLH

LOAO CAPACITANCE - pF

t:Z_ _ _

1'/

I
"

~-

80 100 120 140 160

·50%

50%

I

I
20
CL

50%

V

-"tPLH

~L

SWITCHING WAVEFORMS

50%

*

.....-

V

yV
-.....- tI V V V

40
30

I

\ } tPLH

~

401618/74CI61/54CI61
401638/74CI63/54CI63
4-81T SYNCHRONOUS COUNTERS

DESCRIPTION - The 401618 and the 401638 are fully synchronous edge-triggered 4-8it 8inary
Counters_ Each device has a Clock Input (CP); four synchronous Parallel Data Inputs (PO-P3); three
synchronous Mode Control Inputs, Parallel Enable (i>"E\ Count Enable Parallel (CEP) and Count
Enable trickle (CET); 8uffered Outputs from all four bit positions (00-03); and a Terminal Count
Output (TCl- The 401638 has an additional synchronous Mode Control Input, Synchronous Reset
(SRl- Alternately, the 40161 8 has an overriding asynchronous Master Reset (MRl-

LOGIC SYMBOL
3

10

5

6

401618

10

Operation is fully synchronous except for Master Reset on the 401618 and occurs on the LOW-toHIGH transition of the Clock Input (CPl- When the Parallel Enable Input (PE) is LOW, the next LOWto-HIGH transition of the Clock !.'Put (CP) loads data into the counter from Parallel Inputs (PO-P3lWhen the Parallel Enable Input (PE) is HIGH, the next LOW-to-HIGH transition of the Clock Input
(CP) advances the counter to its next state only if both Count Enable Inputs (CEP and CET) are
HIGH when the state of the counter is fifteen (00 = 01 = 02 = 03 = HIGH) for the 401618 and
401638 and the Count Enable Trickle Input (CET) is HIGH_ For the 401638 a LOW on the Synchronous Reset Input (SR) sets all Outputs (00-03 and TC) LOW on the next LOW-to-HIGH transition of
the Clock Input (CP) independent of the state of all other synchronous Mode Control Inputs (CEP,
CET, PEl- For the 40161 8, a LOW on the overriding asynchronous Master Reset (MR) sets all outputs
(00-03 and TC) LOW, independent of the state of all other inputs.

4

14

13

12

11

3

4

5

6

GET

40163B

Te

15

TC

15

ep
5R

These devices perform multistage synchronous counting without additional components by using a
carry look-ahead counting technique.
14

The 401618, and 401638 are edge-triggered; therefore, the synchronous Mode Control Input (CEP,
CET, PE for the 401618 and CEP, CET, PE, SR for the 401638) must be stable only during the set-up
time before the LOW-to-HIGH transition of the Clock Input (CPlThe 401618 and 401638 are direct replacements for the 74C161/54C161 and 74C163/54C163
respectively.

VDD

= PIN

13

12

16, VSS

11

= PIN 8

40161B
CONNECTION DIAGRAM
DIP (TOP VIEW)
16
15

•
•
•
•
•
•

14

12 MHz TYPICAL COUNT FREQUENCY AT V DD = 10 V
DECODED TERMINAL COUNT
FULLY SYNCHRONOUS COUNTING AND PARALLEL ENTRY
SYNCHRONOUS (40163B) OR ASYNCHRONOUS (40161B) RESET
BUILT-IN CARRY CIRCUITRY
FULLY EDGE-TRIGGERED

13

12
11
10

PIN NAMES

Pi

Parallel Enable Input (Active LOW)

PO-P 3
CEP

Parallel Inputs

40163B
CONNECTION DIAGRAM
DIP
VIEW)

rtop

Count Enable Parallel Input

16

CET

Count Enable Trickle Input

CP

Clock Input (L- HEdge-Triggered)

15

MR

Master Reset Input (Active LOW) for the 401608/401618 Only

14

SR

Synchronous Reset Input (Active LOW) for the 401628/401638 Only

0 0 -03

Parallel Outputs

TC

Terminal Count Output

13

12
11

SELECTOR GUIDE
10

RESET

MODULUS
81NARY

Asynchronous

401618

Synchronous

401638

NOTE:
The FlatpCilk version has the same
pinouts (Connection Diagram) as the
Dual In~ljne Package.

7-273

•

FAIRCHILD CMOS. 40161B/74C161/54C161. 40163B/74C163/54C163

SYNCHRONOUS MODE SELECTION

SYNCHRONOUS MODE SELECTION

401618

401638

PE

CEP

CET

MODE

SR

PE

CEP

CET

L

X

X

Preset

H

L

X

X

MODE

Preset

H

L

X

No Change

H

H

L

X

No Change

H

X

L

No Change

H

H

X

L

No Change

H

H

H

Count

H

H

H

H

Count

L

X

X

X

Reset

MR = HIGH

TERMINAL COUNT GENERATION

401618/401638
CET

(00 • 01 " 02 • 03)

TC

L

L

L

L

H

L

H

L

L

H

H

H

TC = CET • 00 • 01 • 02 • 03 (401618/401638)

STATE DIAGRAM

401618.401638

7-274

H = HIGH Level
L = LOW Level

X = Don't Care

FAIRCHILD CMOS. 40161B/74C161/54C161. 40163B/74C163/54C163
40161B/40163B LOGIC DIAGRAM
The 40161 Band 40163B binary synchronous counters are similar.

VDD
Vss

o

7-275

PIN 16
8
PIN NUMBERS

PIN

FAIRCHILD CMOS. 40161B/74C161/54C161. 40163B/74C163/54C163
DC CHARACTERISTICS: VDD as shown, VSS = 0 V (See Note 1)
LIMITS
SYMBOL

PARAMETER

VDD

MIN
Quiescent

TYP

XC

Power

100

=5 V

Supply

XM

Current

VDD=10V

MAX

MIN

TYP

UNITS

VDD=15V

MAX

MIN

TYP

20

40

80

150

300

600

5

10

20

150

300

600

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VDD as shown, VSS

= 0 V,

TEMP

TEST CONDITIONS

MAX

TA

MIN,25'C

).tA
).tA

= 25'C

MAX

All inputs at

MIN, 25'C

OVor VDD

MAX

(See Note 2)

LIMITS
SYMBOL

PARAMETER

VDD

MIN
tpLH

Propagation Delay, CP to Q

tpHL
tpLH

Propagation Delay. CP to TC

tpHL
tPLH
tpHL
tTLH

Propagation Delay, CET to TC
Output Transition Time

tTHL

=5 V

TYP

MAX

VDD

MIN

= 10 V
MAX

MIN

TYP

MAX

120

220

55

105

40

84

120

220

55

105

38

84

155

285

70

130

45

104

155

285

70

130

40

104

95

165

40

80

27

64

95
60

165
135

55
35

95
70

36
25

76
45

70

135

30

70

23

45

twCP

CP Minimum Pulse Width

90

50

40

20

32

15

ts

Set-Up Time, Data to CP

70

35

35

18

28

13

th

Hold Time, Data to CP

0

-30

0

-15

0

-10

ts

Set-Up Time, PE to CP

110

60

60

30

48

20

th

Hold Time, PE to CP

-10

-57

-5

-28

-4

-18

ts

Set-Up Time, CEP, CET to CP

200

115

95

50

76

35

th

Hold Time, CEP, CET to CP

-20

-110

-10

-48

-8

-32

fMAX

Input Count Frequency

3

6

7

12

8

14

-

UNITS

VDD=15V

TYP

ns
ns
ns

TEST CONDITIONS

CL
RL

= 50 pF,
= 200 kn

I nput Transition

Times

~

20 ns

ns
ns
ns
ns
ns
MHz

(Note 3)

NOTES:

1.

Additional DC Characteristics are listed in this section under 4000B Series CMOS Family Characteristics.

2.
3.

Propagation Delays and Output Transition Times are graphically described in this section under 4000B Series CMOS Family Characteristics.
For fMAX, input rise and fall times are greater than or equal to 5 ns and tess than or equal to 20 ns.
It is recommended that input rise and fatl times to the Clock Input be less than 15 J.is at VDD "" 5 V, 4 /Js at VDD = 10 V, and 3 J.is at
VDD ~ 15 V.

4.

7-276

FAIRCHILD CMOS. 40161B/74C161/54C161 .40163B/74C163/54C163
TYPICAL ELECTRICAL CHARACTERISTICS
POWER DISSIPATION
;:
VERSUS FREQUENCY
El000~'"~~Tr'-nTr;-rnT-rTTrro

~100

TA02r1

~

~10

....

~

ffil.0

c..

.... ~

>=

:;3. VI;:::

:%

~ 10-2 H:;!S!%.......,,1$~~---t1++--t-V+-0t10+o-+--5+V-t+f---l

~

102

70r~~~t--t--+-+-+--+--+-t-1

~

50t-+--r-+-+--+--+-+t-*--r-1

Q.

CL-15 pF_

;:10-4~~~-u~~~~_C~L~o~5~0~p~F~___~-

~6~0~-~40~-2~0~0~2~0~40~6~0~8~0~1~0~0~12~0~140

t

107

103
104
105
106
INPUT FREQUENCY - Hz

...... 1--"'"

......-r/

z
o

~ 40t--t--r-+-+--~~OD~1~
-f-~OD ~ 15V
I 30 _r-cJ 20
l2 101--+-+---+-+--+-+--1,--+-+--1

VOO - 5 V

::l 3 :% . . .;IIl + +
I -j
c 1 0- !>"b~~~-ttH-t-t+t-+:++lI~
~

....~Q*".""'q-t-+--+----j

~ 60t--t--r-+-+--+--+-+-+---r-1
o

..

.... ~

~10-1~+H-+~~~V~~~~~~t#~

ffi

V

I....

>100~+--t--r-+-+~-~~~~~~~

:3 90
~ 80

VDDol0V~~~~~~~
VDO ° 10 V
~ ~~

Q.

CL ° 15 pF

I

II I

vDD ° 15 V
VDD ° 15V

'"

PROPAGATION DELAY

~110~,V_E_RrS_U,S_T_ETM_P,E_R_ATT_U-rR_E,-~-,

TA - AMBIENT TEMPERATURE - °C

INPUT COUNT FREQUENCY
VERSUS TEMPERATURE

PROPAGATION DELAY
~ 140 VERSUS LOAD CAPACITANCE

I

~ 120

TA ° 25°C

I~~y"'"

.... O~O*""'/=--+_+----1

_V7

iil

°100r--+~~~t--+-+---+-+----1

~

V

~ 8o1--+-+-I--+-+----+-+-~
o
~ 60
VOO-l0~
o

g:
I

~

VOoo15 V

40
20r--+--t--t--+-+---+-+----1

>-

~6~0~-~4~0~-~2~0~0~2f.0~4~0~60~8~0~1~0~0~1~20~1~40

0 '=0----:2:!:0,.--4~0,,---::6l;:O---;8!-:;0:--:1~O""O--:l,,\2"'O--;l,-:4"'0:-::-:!.160
CL - LOAD CAPACITANCE - pF

t

TA - AMBIENT TEMPERATURE - °C

SWITCHING DIAGRAMS

CLOCK (CP) TO OUTPUT (Q)
PROPAGATION DELAYS AND MINIMUM
CLOCK PULSE WIDTH

CP--,,~~
':::i r-- 'PLH~ t=o

CP

CONDITIONS: PE

= MR =

PE

=

S'R

CEP

= CEP

= CET
= CET

50%

'PLH-i

~50%

for 40161 Band
for 401638.

CLOCK (CP) TO TERMINAL COUNT (TC)
PROPAGATION DELAYS

= H
=

H

CONDITIONS:

t=.-.=i r--'PHL
See

'=--

the

Terminal

Count

Generation Table PE = CEP = CET = MR =
H for 401618 and fiE ~ CEP ~ CET ~ SR ~ H
for 401638.

7-277

F\50%
'~8~

CET

50%

TC---'50%·

COUNT ENABLE TRICKLE INPUT (CET)
TO TERMINAL COUNT OUTPUT (TC)
PROPAGATION DELAYS

TC~50%
CONDITIONS:

See

~

the

Generation Table. CP =
for 401618 and CP ~
for 401638.

Terminal

PE =
fiE ~

CEP

=

CEP ~

Count

MR =
SA ~

H

H

FAIRCHILD CMOS. 40161B/74C161/54C161 • 40163B/74C163/54C163
SWITCHING DIAGRAMS (Continued)

40163B
SET·UP TIMES (ts) AND HOLD TIMES (th )
FOR PARALLEL DATA INPUTS (PO~P3)'

SET·UP TIMES (ts ) AND HOLD...IIMES (th)
FOR SYNCHRONOUS RESET (SR).

SET·UP TIMES (ts ) AND HOLD TIMES (th)
FOR PARALLEL ENABLE INPUT PE.

CP

CP
ts(U

SR

0

PE

\

CONDITIONS:

PE

o_~

-~/

/

CONDITIONS: FiE = L, MR = H for
40161 Band PE = L, SF! = H for
40163B.

= L. PO'P 3 = H.

CONDITIONS: MR = H for 40161 B
and SR = H for 401638.

40161B
SET·UP TIMES (~) AND HOLD TIMES (t h )
FOR COUNT ENABLE INPUTS (CEP AND
CET).

MASTER RESET (MR) TO OUTPUT (Q)
DELAY. MASTER RESET PULSE WIDTH,
MASTER RESET RECOVERY TIME, AND
MASTER RESET TO TERMINAL COUNT
(TC) DELAY.

CP
t 5(H)

th(H}

"7":r+r+-rl~~~:"\

CEP
t 5(H)

CP

th(H)

"7":r+,.....-rl~~"T"t"T""~,,M"'M"'n

CET

o

TC

CONDITIONS:
P 3 = H.

PE =

L and Po

=

P1

=

P2

=

CONDITIONS: PE
MR = H for 40160BI
40161 Band PE = SR = H for 40162BI
40163B.

NOTE:

1. Set-.up Times (ts ) and Hold Times (t h ) are shown as positive values, but may be specified as negative values.

7·278

401748/7 4C17 4/54C174
HEX D FLIP-FLOP

DESCRIPTION - The 40174B is a Hex Edge-Triggered 0 Flip-Flop with six Data Inputs (00-05), a
Clock Input (CP) an overriding asynchronous Master Reset (MR), and six Buffered Outputs (00-05l.

LOGIC SYMBOL
3

4

6

11

13 14

2

5

7

10

12 15

Information on the Data Inputs (DO-D5) is transferred to the Buffered Outputs (00-05) on the
LOW-to-HIGH transition of the Clock Input (CP) if the Master Reset Input (MR) is HIGH_ When
LOW, the Master Reset Input (MR) resets all flip-flops (00-05 = LOW) independent of the Clock (CP)
and Data Inputs (DO-D5!- The 40174B is a direct replacement for the 74C174i54C174_

VOO
VSS

•
•
•
•

= Pin 16
= Pin 8

CONNECTION DIAGRAM
DIP (TOP VI EW)

TYPICAL CLOCK FREQUENCY OF 16 MHz AT VDD = 10 V
COMMON CLOCK TRIGGERED ON LOW-TO-HIGH TRANSITION
COMMON ACTIVE LOW MASTER RESET
FULLY EDGE-TRIGGERED CLOCK INPUT

16
15
14

12

10

PIN NAMES
NOTE:

Data Inputs
Clock Input (L->H Edge-Triggered)
Master Reset I nput (Active LOW)
Buffered Outputs from the Flip-Flops

DO-D5
CP
MR
00-0 5

The F latpak version has the same
pinouts (Connection Diagram) as the
Dual In~line Package.

LOGIC DIAGRAM

MR~~)<~r-----~---;-;----~~---+-t-----4-----r-r----~----+-+-----~----r-r---~

(2)

CP

0
Q,@)

Voo

= Pin

VSS

= Pin 8

o

=

16

Pin Numbers

7-279

FAIRCHILD CMOS • 40174B/74C174/54C174
DC CHARACTERISTICS: VDD as shown, VSS ~ 0 V (See Note 1)
LIMITS
SYMBOL

VDD ~5 V

PARAMETER
MIN
Quiescent
Power

IDD

Supply
Current

TYP

XC
XM

VDD

MAX

~

VOD ~ 15 V

10 V

TYP

MIN

MAX

MIN

TYP

TEMP

UNITS

TEST CONDITIONS

MAX

20

40

80

150

300

600

5

10

20

150

300

600

MIN,25°C

/1A
/1A

MAX

All inputs at

MIN,25°G

o V or VDD

MAX

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VDD as shown, VSS ~ 0 V, TA ~ 25°C (See Note 2)
LIMITS
PARAMETER

SYMBOl-

VDD
MIN

tPLH

Propagation Delay, CP to On

tpHL
tpHL
tTLH

Propagation Delay, MR to On

Output Transition Time

~

5 V

VDD

TYP

MAX

70
70

~

VDD~15V

10 V

TYP

MAX

115

35

115

35

MIN

MIN

UNITS

TYP

MAX

60

25

48

60

25

48

80

125

40

65

25

52

65

135

35

70

15

45

65

135

35

70

15

45

TEST CONDITIONS

ns
ns
ns

tTHL
twCP(L)

Minimum Clock Pulse Width

45

25

20

10

16

8

ns

twMR(L)

Minimum MR Pulse Width

55

35

35

20

28

15

ns

tree

MR Recovery Time

25

6

13

5

11

2

ns

ts

Set-Up Time, Dn to CP

5

1

5

1

4

0

th

Hold Time, Dn to CP

20

10

10

2

8

1

fMAX

Max. Clock Frequency (Note 3)

5

9

8

16

9

19

CL~50pF,

RL

~200

k.(1

I nput Transition

Times

~

20 ns

ns
MHz

NOTES,
1. Additional DC Characteristics are I isted in this section under 40008 Series CMOS Family Characteristics.
2. Propagation Delays and Output Transition Times are graphically described in this section under 4000B Series CMOS Family Characteristics.
3, For f MAX , input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.
4. It is recommended that input rise and fall times to the Clock Input be less than 15 J.l,s at VOO = 5 V, 4JJs at VOO = 10 V, and 3/J.s at
VDD~15V.

7-280

FAIRCHILD CMOS • 40174B/74C174/54C174
lYPICAL ELECTRICAL CHARACTERISTICS

==

E1000

CLOCK FREQUENCY
VERSUS
POWER SUPPLY VOLTAGE

TYPICAL POWER DISSIPATION
VERSUS CLOCK FREQUENCY

tuJ .~ II

20

TI 1~I 2~ot

..
~ 100
~~ ..
IJ6~ ~ 1IJ~"
~
..' p..'
10
:
.~ ;:;' ",V
IJblD ~ 1IJI~" :
..' ..'
ffi... 1.0
:;;.
.I?
Z
..' .;"
.'
010-1
.~
~
..' ~: .~;;: VDD = 5 V
2 .'
I

(J

~ 10-

i5 10- 3
a:
w

~ 10- 4

...

80

z

70

~

60

o

Cl

50

...a:

30

:o
I

a
~

...

(J

"

.;V
1~

1~

40

w
:::>
0
w
a:

o

(J

9

1~

/

/

o

o

1~

10

5

15

VDD - POWER SUPPLY VOLTAGE - V

PROPAGATION DELAY
VERSUS TEMPERATURE

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

i(! 110

.,.'0/ ~

;

w

o
z

. . . .V

o

V

&

..-

- -- r- lffT
l- f -

-20

20

60

100

70
60

aI

~

v ..

~

50
40

. . v_

30

~

20

(J

10

...

140

~'o~ V

80

C3

g:

"I)I)

/'

90

i=

:o

V

TA = 25°C

I 100

. . . .V

-60

5

(J

~~

10

II

...:.:

~

20

/

10

CLOCK FREQUENCY - Hz

CL= 15 pF

,/

1/

>-

Z

CL = 50 pF······
1~

.......V

15

(J

IIII I
CL-15 pF-

90

w

o

~

1~

i(! 100

;

I

~

VI

TA =1 25oC
CL = 15 pF

N

J:
::!;

o

TA - AM81ENT TEMPERATURE - °C

20

-

_ 10"
,,~

/

40

"oO~'

r-s"- f-

r-"

60

80 100 120 140 160

CL - LOAD CAPACITANCE - pF

SWITCHING WAVEFORM

CP

On

MR

MINIMUM PULSE WIDTHS FOR CP AND MR, MR
RECOVERY TIME, AND SET·UP AND HOLD TIMES, On TO CP
NOTE: Set-up and Hold Times are shown as positive values but may be specified as negative values

7-281

40175B/74C175/54C175
QUAD 0 FLI P-FLOP

DESCRIPTION - The 40175B is a Quad Edge-Triggered D Flip-Flop with four Data Inputs (Do-D3), a
Clock Input (CP) an overriding asynchronous Master Reset (MR), four Buffered Outputs (QO-Q3) and
four Complementary Buffered Outputs (00-031.

LOGIC SYMBOL
4

Information on the Data Inputs (DO-D3) is transferred to Outputs (Qo-Q3) on the LOW-to-HIGH
Transition of the Clock Input (CP) if the Master Reset Input (MR) is HIGH. When LOW, the Master
Reset Input (MR) resets all flip-flops (QO-Q3 = LOW, 00-03 = HIGH), independent of the Clock (CP)
and Data (DO-D3) Inputs.
•
•
•
•
•

40175B

3

2

6

7

11

10 14 15

V DO

= Pin

16

Vss

= Pin

8

CONNECTION DIAGRAM
DIP (TOP VIEW)

PIN NAMES
Data Inputs
Clock Input (L-.H Edge-Triggered)
Master Reset Input (Active LOW)
Buffered Outputs from the Flip-Flops
Complimentary Buffered Outputs from the Flip-Flops

QO-0 3
00-0 3

12 13

CP

TYPICAL CLOCK FREQUENCY OF 16 MHz AT VDD = 10 V
COMMON CLOCK TRIGGERED ON LOW-TO-HIGH TRANSITION
COMMON ACTIVE LOW MASTER RESET
TRUE AND COMPLEMENTARY OUTPUTS AVAILABLE
FULLY EDGE·TRIGGERED CLOCK INPUT

DO-D3
CP
MR

5

16
15

14
13

12
11

10

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as the
Dual In-line Package.

LOGIC DIAGRAM
DO

02

o

@

Q

Q

Q

Q

CP

MR~~.:>o-~-----4------~~~~----~-----+--~-+----~~----+---~+-----~

0)

cP~~C>o-~------------t-~~~-----------+--~~------------+---~

®

VDO

VSS

o

= Pin
= Pin
= Pin

16

8
Number

Qo

Q2

7-282

FAIRCHILD CMOS • 40175B/74C175/54C175
DC CHARACTERISTICS: VDD as shown, VSS ~ 0 V (See Note 1)
LIMITS
SYMBOL

PARAMETER

VDD - 5 V
MIN

Quiescent

Power
IDD

Supply

Current

TYP

VDD-10V

MAX

XC
XM

TYP

MIN

MIN

TYP

TEMP

UNITS

VDD -15 V

MAX

TEST CONDITIONS

MAX

20

40

80

150

300

600

5

10

20

150

300

600

MIN,25°C
I'A
I'A

MAX

All inputs at

MIN,25°C

o Vor VDD

MAX

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VDD as shown, VSS ~ 0 V, T A ~ 25°C (See Note 2)
LIMITS
SYMBOL

PARAMETER

MIN
tpLH
tpHL

VDD~10V

VDD - 5 V

-

Propagation Delay, CP to Qn or Q n

TYP

MAX

MIN

TYP

MAX

VDD
MIN

~

15V

UNITS

TYP

MAX
60

70

190

35

75

25

70

190

35

75

25

60

tpLH

Propagation Delay,

80

200

40

70

25

56

tPHL

MR to Q n or On

80

200

40

70

25

56

65

135

35

75

15

45

65

135

35

75

15

45

tTLH

Output Transition Time

tTHL
twCP(L)

Minimum Clock Pulse Width

80

25

45

10

36

8

twMR(L)

Minimum MR Pulse Width

MR Recovery Time

60
0

35
-50

30
0

20
-25

24

tree

15
-15

ts

Set-Up Time, Dn to CP

45

20

20

7

16

3

th

Hold Time, Dn to CP

10

-10

5

-5

4

-3

fMAX

Max_ Clock Frequency (Note 3)

4

9

10

16

12

19

0

TEST CONDITIONS

ns
ns
ns
ns

CL

~

50 pF,

RL

~

200 kn

Input Transition

ns
Times
-ns

~

20 ns

ns
MHz

NOTES:

1.
2.
3.
4.

Additional DC Characteristics are listed in this section under 4000B Series CMOS FamilY Characteristics.
Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.
For fMAX, input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.
It is recommended that input rise and fall times to the Clock I nput be less than 15 fJ,s at V DD = 5 V. 4 MS at VDD ::= 10 V. and 3 }.ls at
VDO~15V.

SWITCHING WAVEFORMS

CP

Dn

0-''''
.....-twMFi----..

MR

50%

:0%

MINIMUM PULSE WIDTHS FOR CP AND MR,
MR RECOVERY TIME, AND SET-UP AND HOLD TIMES, On TO CP
Note: Set-up and Hold Times are shown as positive values but may be specified as negative values.

7-283

FAIRCHILD CMOS • 40175B/74C175/54C175
TYPICAL ELECTRICAL CHARACTERISTICS

POWER DISSIPATION
VERSUS FREQUENCY

INPUT FREQUENCY - Hz

PROPAGATION DELAY, CP TO
Q n OR Qn, VERSUS
LOAD CAPACITANCE
I
~

0

E
I

140

"'0

120

0°

...0
~

"~"

40

~

I-'
I-

~

80

60

~

70

>--

"
0"
i=

80

~

u

u

CL'" 15 pF

90

6

...0

100

,:

~

100

la°

TA = 25'C

16

PROPAGATION DELAY,
CP TO Q n OR Qn'
VERSUS TEMPERATURE

60

"i=0"
""~

40

I

20

~

50

I-- - _ ".,."V
,.;!';;.,.......

30

V 0'"

I-

~

0
0

20

40

140

160

,ov

~~,
tpU-I' tpHL' Voo '" 16\1

~

20

...... 1---'"

,oo·~
~

10

I

,

40

60

o
-60 -40

20

20

80

100 120

TA - AMBIENT TEMPERATURE _

CL - LOADCAPAClTANCE - pF

7-284

°c

140

40193B/54/74C193
4-BIT UP/DOWN BINARY COUNTER
DESCRIPTION - The 40193B is a 4-Bit Synchronous Up/Down Binary Counter. Both operate the
same except for the count sequence. Both counters have a Count Up Clock Input (CPU), a Count
Down Clock Input (CPO), an asynchronous Parallel Load Input (PD, four Parallel Data Inputs (PO-P3),
an overriding asynchronous Master Reset (MR), four Counter Outputs (QO-Q3), a Terminal Count Up
(Carry) Output (TCu) and a Terminal Count Down (Borrow) Output (TCj)!.

LOGIC SYMBOL
11

When the Master Reset Input (MR) is LOW and the Parallel Load Input (Pl.) is HIGH, the Counter
Outputs change state on the LOW-to-HIGH transition of either Clock Input. However, for correct
counting, both Clock Inputs cannot be LOW simultaneously. With the Master Reset Input (MR) LOW,
information on the Parallel Data Inputs (PO-P3) is loaded into the counter when the Parallel Load
Input (Pi) is LOW and stored in the counter when the Parallel Load Input (Pl.) goes HIGH, independent of Clock Inputs (CPU, CPO!. When HIGH, the Master Reset (MR) resets the counter independent
of all other input conditions. See equations below for Terminal Count Outputs (TCU, TCD).

15

1

10

12
40193B

14

3

2

6

•

TYPICAL COUNT FREQUENCY OF 8 MHz AT VDD = 10 V

Voo

•
•
•
•

SYNCHRONOUS OPERATION
INTERNAL CASCADING CIRCUITRY PROVIDED
ACTIVE LOW PARALLEL LOAD
ACTIVE HIGH ASYNCHRONOUS MASTER RESET

VSS = Pin 8

PIN NAMES
PL

QO-0 3
TCU
TCD

<=

7

Pin 16

CONNECTION DIAGRAM
DIP (TOP VIEW)

Parallel Load Input (Active LOW)
Parallel Data Inputs
Count Up Clock Pulse Input (L->H Edge-Triggered)
Count Down Clock Pulse Input (L->H Edge-Triggered)
Master Reset I nput (Asynchronous)
Buffered Counter Outputs
Buffered Terminal Count Up (Carry) Output (Active LOW)
Buffered Terminal Count Down (Borrow) Output (Active LOW)

PO-P3
CPU
CPO
MR

9

16
15
14
13

12
11

MODE SELECTION

10

MR

PL

CPU

CPO

MODE

H

X

X

X

Reset (Asyn.)

L

L

X

X

Preset (Asyn.)

L

H

H

H

No Change

L

H

H

Count Up

L

H

S
H

s·

NOTE:
L "" LOW Level
H = HIGH Level
X = 'Don't Care
S = Positive-Going Clock Pulse Edge

Count Down

40193B STATE DIAGRAM

40193B LOGIC EQUATIONS FOR TERMINAL COUNT
Count Up _ _ __

TCU

Count Down ........ -- .... ---

TCD

00 • 01
00 • Q1

• 02. 03 • CPU
• 02 • Q3 • CPO

7-285

The F latpak version has the same
pinouts (Connection Diagram) as the
Dual I n-line Package.

FAIRCHILD CMOS • 40193B/54/74C193
LOGIC DIAGRAMS

401938

CPD~~4~~
4

(DOWN COUNTl

1-__~l1k:========:l====~!E========:3~==:f~~~~~~~~~~~~ Teo

______

(BORROW
OUTPUT)

MR~~~--~~----~~----------~---+~----------~----~~--------~

@

(CLEAR)@

00

CD

0,

@

02

Voo = Pin 16
VSS = Pin 8
= Pin Number

o

7-286

FAI RCHI LD CMOS • 40193B/54/74C193
DC CHARACTERISTICS: VDD as shown, VSS = 0 V (See Note 11
LIMITS
SYMBOL

PARAMETER
MIN
Quiescent

IDD

Supply
Current

TYP

XC

Power

VDD = 10V

VDD= 5 V

XM

MAX

MIN

TYP

MIN

TYP

TEMP

UNITS

VDD=15V

MAX

TEST CONDITIONS

MAX

20

40

80

150

300

600

5

10

20

150

300

600

MIN,25°C

/lA
/lA

MAX

All inputs at

MIN,25°C

o V or VDD

MAX

AC CHARACTERISTICS AND SET-UP REQUIREMENTS: VDD as shown, VSS = 0 V, TA = 25°C (See Note 21
LIMITS
SYMBOL

PARAMETER

VDD =5 V
MIN

tpLH
tPHL
tpLH

Propagation Delay, CPU to Q n
Propagation Delay, CPD to On

tpHL

VDD = 10V

TYP

MAX

245
245

MIN

UNITS

VDD= 15 V
TYP

MAX

210

70

175

210

70

175

105

210

70

175

105

210

70

175

TYP

MAX

490

105

490

105

245

490

245

490

MIN

130

260

60

120

40

96

tPHL

130

260

60

120

40

96

tpLH

145

290

60

120

40

96

tPLH

tpHL
tpHL

Propagation Delay, CPU to TCU
Propagation Delay, CPD to TCD
Propagation Delay, MR to Q n
Propagation Delay, MR to

tPLH
tPLH

TCU or TCD
Propagation Delay,

tPHL
tTLH

PL to Q n

Output Transition Time

tTHL

ns
ns
ns
ns

145

290

60

120

40

96

270

540

120

240

80

192

ns

370

740

170

340

105

270

ns

270

540

110

220

70

175

270

540

110

220

70

175

55

135

30

75

20

45

55

135

30

75

20

45

ns

Min. CPU or CPD Pulse Width

170

85

75

30

60

20

ns

Minimum MR Pulse Width

180

60

80

30

64

20

ns

twPL

Minimum PL Pulse Width

150

75

85

25

52

20

ns

tree

MR Recovery Time

150

75

65

30

52

20

ns

tree

PL Recovery Time

150

75

65

30

52

20

ns

ts

Set-Up Time, Pn to PL

170

85

75

30

60

20

th

Hold Time, Pn to PL
Input Count Frequency (Note 31

0

-83

0

-28

0

-19

2

4

4

8

5

12

7-287

Input Transition

Times < 20 ns

twMR

Notes on following page.

CL = 50 pF,
RL = 200 k!1

ns

twCP

fMAX

TEST CONDITIONS

ns
MHz

FAIRCHILD CMOS • 401938/54/74C193
NOTES:

1.
2.

Additional DC Characteristics are listed in this section under 40008 Series CMOS Family Characteristics.
Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.

3,

For fMAX, input rise and fall times are greater than or equal to 5 ns and -less than or equal to 20 ns.

4.

It is recommended that input rise and fall times to the Clock Input be less than 151-ls at VOO

=

5 V, 4}Js at VOo'= 10 V, and 3}.ls at

VDD~15V.

SWITCHING WAVEFORMS

RECOVERY TIMES FOR PI. AND MR.
MINIMUM PULSE WIDTHS FOR CPU. CPO.
MR AND SET-UP AND HOLD TIMES Pn TO

Pi: AND

Pi:

NOTE: Set-up and Hold Times are shown as positive values but may be specified as negative values.

7-288

401948
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT R

DESCRIPTION - The 401948 is a 4-Bit Bidirectional Shift Register with two Mode Control Inputs
(SO, S1), a Clock Input (CP), a Serial Data Shift Left Input (DSL), a Serial Data Shift Rig~lnput
(DSR), four Parallel Data Inputs (PO-P3), an overriding asynchronous Master Reset Input (MR) and
four Buffered Parallel Outputs (a0-03).
When LOW, the Master Reset Input (MR) resets all stages and forces all Outputs (00-03) LOW,
overriding all other input conditions. When the Master Reset Input (MR) is HIGH, the operating mode
is controlled by the two Mode Control I nputs (SO, S1) as shown in the Truth Table. Serial and parallel
operation is edge-triggered on the LOW-to-HIGH transition of the Clock Input (CP). The inputs at
which the data is to be entered and the Mode Control I nputs (SO, S1) must be stable for a set-up time
before the LOW-to-HIGH transition of the Clock Input CP).

LOGIC SYMBOL
3

5,

10

4

5

7

401948

CP MR

11

15 14 13

Voo
VSS

•
•
•
•
•

6

=:

12

Pin 16
Pin 8

CONNECTION DIAGRAM
DIP (TOP VIEW)

TYPICAL SHIFT FREQUENCY OF 14 MHz AT VDD = 10 V
ASYNCHRONOUS MASTER RESET
HOLD (DO NOTHING) MODE
FULLY SYNCHRONOUS SERIAL OR PARALLEL DATA TRANSFERS
POSITIVE EDGE-TRIGGERED CLOCK

PIN NAMES
Mode Control Inputs
Parallel Data Inputs
Serial (Shift Right) Data Input
Serial (Shift Left) Data Input
Clock Input (L-+H Edge-Triggered)
Master Reset I nput (Active LOW)
Parallel Outputs

SO,S1
PO-P3
DSR
DSL
CP
MR
00-0 3

NOTE:
The

Flatpak version has the same

pinouts (Connection Diagram) as the
Dual I n-line Package.

LOGIC DIAGRAM

P,
(0

DSR

CD
=------,

Voo

Pin 16

VSS

Pin

o

8

CP~O-----------+---1----r------~---+---+-------+---i--~r-----~
MAG)

7-289

•

FAIRCHILD CMOS • 401948
TRUTH TABLE

INPUTS (MR = H)

OPERATING
MODE

SI

Hold
Shift Left
Shift Right
Parallel Load

So

OUTPUTS AT tn+l

DSR

DSL

PO,Pl,P2,P3

00

01

02

03
03

L

L

X

X

X

00

01

02

H

L

X

L

X

01

02

03

L

H

L

X

H

X

01

02

03

H

L

H

L

X

X

L

00

01

02

L

H

H

X

X

H

00

01

02

H

H

X

X

L

L

L

L

L

H

H

X

X

H

H

H

H

H

H

HIGH Voltage Level

x

L

LOW Voltage Level

(t n +1)

=

Don't Care

=

Indicates state after next LOW-ta-HIGH clock transition.

DC CHARACTERISTICS: VDD as shown, VSS eo 0 V (See Note 1)
LIMITS
SYMBOL

PARAMETER

VDD=5V
MIN

Quiescent

XC

Power

IDD

TYP

Supply

XM

Current

VDD = 10 V

MAX

TYP

MIN

UNITS

VDD=15V

MAX

MIN

'TYP

TEMP

TEST CONDITIONS

MAX

20

40

80

150

300

600

5

1.0

20

150

300

600

MIN,25°C

IJ,A
IJ,A

MAX

All inputs at

MIN,25°C

o V or VDD

MAX

AC CHARACTERISTICS AND SET·UP REQUIREMENTS: VDD as shown, VSS = 0 V, TA = 25°C (See Note 2)
LIMITS
SYMBOL

PARAMETER

VDD = 5 V
MIN

tPLH

Propagation Delay, CP to

tPHL
tPHL
tTHL

a

Propagation Delay, MR to

a

Output Transition Time

tTLH
ts

Set·Up Time,

80

TYP

VDD=10V

MAX

MIN

TYP

MAX

TYP

MAX

100

180

45

80

35

64

100

180

45

80

35

64

100

180

45

80

35

64

75

135

40

70

25

45

75

135

40

70

25

45

40

40

20

32

Hold Time,

a

-10

a

-5

a

-5

ns

ns
CL=50pF,
ns

Set·Up Time, S to CP

th

Hold Time, S to CP

twCPiL)

Minimum Clock Pulse Width

twMR(L)

Minimum MR Pulse Width

2.0

Times';; 20 ns

1.0.0

6.0

5.0

3.0

4.0

a

-10

a

-5

a

-5

1.0.0

6.0

60

35

48

25

ns

75

4.0

45

25

36

15

ns

-

RL = 200 kn
Input Transition

Pa·P3, DSL, DSR to CP
ts

TEST CONDITIONS

ns

15

PO·P3, DSL, DSR to CP
th

UNITS

VDD = 15V
MIN

ns

tree

Recovery Time for MR

18.0

1.0.0

9.0

5.0

72

35

ns

fMAX

Maximum CP Frequency iNote 3)

4.5

9

9

14

1.0

16

MHz

NOTES:
1. Additional DC Characteristics are listed in this section under 4000B Series CMOS Family Characteristics.
2. Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.
3, For fMAX, input rise and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.
4. It is recommended that input' rise and fall times to the Clock Input be less than 15 IJs at VOO = 5 V, 4IJs at VOO = 10 V, and 3 j..ts at
VDD = 15 V.

7·290

FAIRCHILD CMOS • 401948
TYPICAL ELECTRICAL CHARACTERISTICS

POWER DISSIPATION
VERSUS FREQUENCY

3:
E 1000

I
w

TII~12~od

flll·1 I

100

(!)

;2
o
~

10

"

1.0

W

I

~~6l1~ V':

.~

::!

I....

1111

I

s

~

.~; ...

~A?=15V,,,

1111

PROPAGATION DELAY
VERSUS TEMPERATURE

~.

...

:.... -;;

Z

Ii:

10- 4
102

103

104

160

S

140

~

120

Z

100

(!)

80

~

~
~

I

cf

e
0-

o

20

.
S

60

CL = 15 pF..........

5

10

~

~1~V

10

0
-60

-20

20

60

100

140

-

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

180

TA = 25°C

160
140
120

~

100

~

80

If

60

'100=6'1

VDD = 10'1

I

. . . . 1"-- -

20

'100= 10'1

40

~

o

......."'-......

f-'

60

~
(!)

'\

40

~ f-'

TA - AMBIENT TEMPERATURE - °C

\ '\.

o

cf

c

\

o

30

'I9!t~-

Hz

\

0-

"
0-

\'CL = 50 pF

o

~
o

50

o

TA = 25°C

I

~

e

PROPAGATION DELAY
VERSUS POWER SUPPLY VOLTAGE

11

70

107

105

INPUT FREQUENCY -

z
o

I

~

3:

80

0-

ls~

CL= 15 pF

90

w

o

'1-..
~ .. ···V
o 10-1
...
~ .... /
P-VDD = 5 V
~ 10- 2
~~
iii
....... /...
'"o 10- 3 V
III
....
CL -15 pF-"w
V
CL = 50 pF········
0-

100

cf

e
0-

o

15

Voo - POWER SUPPLY VOLTAGE - V

40
VDO

20

0

o

w

15 V

T I

~

~

~

1001W1~1~

Cl - LOAD CAPACITANCE - pF

7-291

•

FAIRCHILD CMOS • 401948
SWITCHING TIME WAVEFORMS
The shaded areas indicate when the input is permitted to change for predictable output performance.

MR
CLOCK
50%

OUTPUT

CLOCK

OUTPUT

MASTER RESET PULSE WIDTH.
MASTER RESET TO OUTPUT DELAY AND
MASTER RESET TO CLOCK RECOVERY TIME

CLOCK TO OUTPUT DELAYS
CLOCK PULSE WIDTH

OTHER CONDITIONS:

S,

~

L, MR

~

I

H, So

~

H

OTHER CONDITIONS:

SO, S,
Po

~

P,

H
~

P2

~

P3

~

H

,-----------

S1

OUTPUT'

~

-.JI

~""" _ _

' . . . _-.Jr

SET-UP (ts ) AND HOLD (th) TIME FOR SERIAL
DATA (DSR. DSL) AND PARALLEL DATA (PO. Pl. P2. P3)
OTHER CONDITIONS:

MR

~

SET-UP (t s) AND HOLD (th) TIME FOR S INPUT

H

OTHER CONDITIONS:

* DSR Set-up Time Affects 00 Only
DSL Set-up Time Affects 03 Only

7-292

MR

~

H

401958/74CI95/54CI95
4-81T UNIVERSAL SHIFT REGIST
DESCRIPTION - The 40195B is a fully synchronous edge-triggered 4-Bit Shift
Input (CP), four synchronous Parallel Data Inputs (PO-P3), two synchronous Se
ta Inputs (J, K),
a synchronous Mode Control Input (PE), Buffered_Outputs from all four bit positions (°0-°3), a
Buffere~nverted Output from the last bit position (03) and an overriding asynchronous Master Reset
Input (MRI.
Operation is synchronous (except for Master Reset) and is ed~triggered on the LOW-to-HIGH
transition of the Clock Input (CPl. When the Mode Control Input (PE) is LOW, a LOW-to-HIGH clock
transition loads data into the register from Parallel Data Inputs (PO-P3l. When the Mode Control Input
(PE) is HIGH, a LOW-to-HIGH clock transition shifts data into the first register position from the
Serial Data Inputs (J, K), and shifts all the data in the register one position to the right_ D-type entry is
obtained by tying the two Serial Data Inputs (J, K) together_ A LOW on the Master Reset Input (MR)
resets all four bit positions (00-03 = LOW, 03 = HIGH) independent of all other input conditions.
The 40195B is a direct replacement for the 74Cf95/54C195.
•
•
•
•
•
•

TYPICAL SHIFT FREQUENCY OF 14 MHz AT VOD = 10 V
ASYNCHRONOUS MASTER RESET
J, K INPUTS TO THE FIRST STAGE
FULLY SYNCHRONOUS SERIAL OR PARALLEL DATA TRANSFERS
COMPLEMENTARY OUTPUT FROM THE LAST STAGE
POSITIVE EDGE-TRIGGERED CLOCK

PIN NAMES
PE
PO-P3

J

K
CP
MR
°0-0 3
03

LOGIC SYMBOL

9

4

5

6

7

&
PE
10

CP

401959

11

°3

3-0 K
MR

Y

15 14

VOD
VSS

13 12

Pin 16

Pin

8

Parallel Enable Input (Active LOW)
Parallel Data Inputs
First Stage J Input (Active HIGH)
First Stage K Input (Active LOW)
Clock Input (L ~ HEdge-Triggered)
Master Reset I nput (Active LOW)
Parallel Outputs
Complementary Last Stage Output

LOGIC DIAGRAM

CONNECTION DIAGRAM
DIP (TOP VIEW)

16
15

14
13

12
11

10

NOTE:
The F latpak version has the same
pinouts (Connection Diagram) as the
Dual I n-line Package.

VOO=Pin16

VSS

o

=

=

Pin 8
Pin Numbers

7-293

FAIRCHILD CMOS • 40195B/74C195/54C195
TRUTH TABLE
OPERATING MODE

Shift Mode

Parallel Entry Mode

H
L
X

PE

J

H

.

INPUTS (MR = H)

OUTPUTS AT tnH

K

Po

PI

P2

P3

QO

Ql

Q2

Q3

Q3

L

L

X

X

X

X

L

00

Ql

Q2

02

H

L

H

X

X

X

X

QO

QO

Ql

Q2

02

H

H

L

X

X

X

X

QO

QO

Ql

Q2

02

H

H

H

X

X

X

X

H

QO

Ql

Q2

Q2

L

X

X

L

L

L

L

L

.L

L

L

H

L

X

X

H

H

H

H

H

H

H

H

L

-

-

HIGH Voltage Level
LOW Voltage Level
Don't Care

(t n +1) "" Indicates state after next LOW to HIGH clock transition.

DC CHARACTERISTICS: VDD as shown, VSS = 0 V (See Note 1)
LIMITS
SYMBOL

PARAMETER
MIN
Quiescent

TYP

MAX

Supply

UNITS

VDD=15V

MAX

MIN

TYP

40

80

300

600

10

20

5
150

300

TEMP

TEST CONDITIONS

MAX

20

XM

Current

TYP

MIN

150

XC

Power
IDD

VDD=10V

VDD =5 V

600

MIN,25°C
IlA

MAX

All inputs at

MIN,25°C

o V or VDD

IlA

MAX

AC CHARACTERISTICS AND SET·UP REQUIREMENTS: VDD as shown, VSS = 0 V, TA = 25°C (See Note 2)
LIMITS
SYMBOL

PARAMETER

VDD =5 V
MIN

tpLH
tpHL

Propagation Delay, CP to Q n or 03

TYP

VDD = 10 V

MAX

MIN

TYP

MAX

UNITS

VDD = 15V
MIN

TYP

MAX

100

180

45

80

35

64

100

180

45

80

35

64

ns

tPHL

Propagation Delay, MR to Q3

100

180

45

80

35

64

ns

tPHL

Propagation Delay, MR to Q n

100

180

45

80

35

64

ns

75

135

40

70

25

45

75

135

40

70

25

45

tTHL

Output Transition Time

tTLH
ts

Set·Up Time, J, K, PO·P3 to CP

th

Hold Time, J, K, PO·P3 to CP

ts

Set·Up Time, PE to CP

th

Hold Time, PE to CP

twCP(L)

Minimum Clock Pulse Width

twMR(L)

Minimum MR Pulse Width

tree
fMAX

ns

80

40

40

20

32

15

0

-10

0

-5

0

-5

100

60

50

30

40

20

0

-10

0

-5

0

-5

100

60

60

35

48

25

ns

75

40

45

25

~·,3

15

ns

Recovery Time for MR

180

100

90

50

72

35

ns

Maximum CP Frequency (Note 3)

4.5

9

9

14

10

16

MHz

-

-

TEST CONDITIONS

ns
ns

CL=50pF,
RL ~ 200 kS1
Input Transition

Times

~

20 ns

NOTES:

1.
2.
3.
4.

Additional DC Characteristics are listed in this section under 40008 Series CMOS FamilY Characteristics.
Propagation Delays and Output Transition Times are graphically described in this section under 40008 Series CMOS Family Characteristics.
For fMAX, input rise-and fall times are greater than or equal to 5 ns and less than or equal to 20 ns.
It is recommended that input rise and fall times to the Clock Input be less than 15}Js at VOO = 5 V, 4}Js at VOO = 10 V, and 3 fJs at

VDD=15V.

7-294

FAIRCHILD CMOS • 40195B/74C195/54C195
TYPICAL ELECTRICAL CHARACTERISTICS

POWER DISSIPATION
VERSUS FREOUENCY

3:
E 1000

/1~12~od

I

w

Cl

~

U

~

a:

w
0.

fill

100

I I

~~~ ll lriU '\

1.0

iii
15

'"a:
w

3:

~

~
~~.

..'
~:. .... 1/

10- 3

.~

... ~;r.:

Z

10- 2

J

"*····V.. .

~

~":
..

~<
....

100

...w~
o
z

90

~

60

o

"'V

'

Cl

.,'1/

~
o

'

VOD

~

a:

5V

0.

ao

III
CL-15pF-

~

CL~50pF········

10- 4
102

c

II

IIII WI? ~ 1~ V,'t'--

10

o 10-1

~

II IIII

104

105

80

70

--

30
20
10

o

160

>

140

~

140

w

~

120

z
o

100

Cl

80

~

60

:5
;::


"DO

I - ~~V

TA - AMBIENT TEMPERATURE - °C

~

160

"g£.;';:'-

50

-60

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

c

--

40

INPUT FREQUENCY - Hz

~

~D~

15 pF

~

f-

0.

107

106

CL

....

U

103

PROPAGATION DELAY
VERSUS TEMPERATURE

~

o

5

10

15

VDD - POWER SUPPLY VOLTAGE - V

7·295

FAIRCHILD CMOS • 40195B/74C195/54C195
SWITCHING TIME WAVEFORMS
The shaded areas indicate when the input is permitted to change for predictable output performance.

CLOCK TO OUTPUT DELAYS
AND CLOCK PULSE WIDTH

MASTER RESET PULSE WIDTH,
MASTER RESET TO OUTPUT DELAY AND
MASTER RESET TO CLOCK RECOVERY TIME

r

50%

')M1LI---t--'"c-l,-_ _ __

CLOCK
CLOCK

__________JI
---";"'-'""t

50%

•

I- 'PHL-I

OUTPUT
OUTPUT

OTHER CONDITIONS:

J

= PE = MR = HIGH

K=

50%

OTHER CONDITIONS:

PE

L&W

Po

SET-UP (9 AND HOLD (th) TIME FOR SERIAL
DATA (J & K) AND PARALLEL DATA (PO, P1, P2, P3)

/

= LOW
= P1 = P2 = P3 = HIGH

SET-UP (ts ) AND HOLD (th) TIME FOR PE INPUT

, ___--II
I

LOAD PARALLEL DATA

OUTPUT _ _ _ _ _

I

':><____

I

LOAC SERIAL DATA
SHIFT RIGHT

.JX

0_,_,_P'_ _

0,"

OUTPUP - - - - . .

OTHER CONDITIONS:

OTHER CONDITIONS:

MR = HIGH
 VIN ;> VCC

V

10UT- 0

V

lOUT

V

lOUT - 0

= -0.2

mA

VSS + 0.4

V

+1.0

p.A

oV

20

p.A

VIH - VCC or VSS

2.0

mA

f

-1.0

V

2.0

7-298

7

pF

10

pF

lOUT - 2.0 mA
;> VOUT;> VCC

= 1 MHz

cs -

VIH

FAIRCHILD CMOS. 65088/65188
AC WAVEFORMS
Conditions;

Vee

=5

V ± 10%

CL ~ 50 pF (One TTL Load)

TA
Input Level:

= _25 0 C to

LOW

~

HIGH
t r , tf

+85 0 C

VIL

~

VIH

= 20

Measurement Reference to 1/2

ns

Vee

A. READ CYCLE

B. WRITE CYCLE

Cs'

/

/

\

Aa-A,

~
*0

~

I N input is reference to HIG H-to~LOW edge of WE,

Cs

(CS1)'

CS2. CS3, which ever switches first.

7-299

•

_A_P_P_L_IC_A_T_I_O_N_S_I_N_F_O_R_M_A_T_I_O_N_ _--,_ _ __

APPLICATIONS INFORMATION CONTENTS

CMOS INTERFACE CIRCUITS .......................................................
MOS to LED Segments & Digit Drivers .............................................
High Voltage, High Current Darlington Drivers ......................................
One-shot Multivibrator .............................................................
Voltage Comparator ...............................................................
Power Supply Regulator ...........................................................
MOS to LED Digit Driver ...........................................................
CMOS to 7-Segment LED Display ..................................................

8-5
8-7
8-7
8-8
8-8
8-8
8-9
8-9

CMOS OSCILLATORS CiRCUiTS .................................................... 8-10
APPLICATION OF THE 47028 ....................................................... 8-20
USING THE 47038 FIFO ............................................................. 8-28
MICROPROGRAMMING WITH PROCESSOR ORIENTED MACROLOGIC .............. 8-39

•
8-3

INTERFACE CIRCUITS FOR CMOS

Fairchild manufactures one of the broadest varieties of Integrated Circuits in the world. In an effort to aid the designer in his
search for compatible interface alternatives, listed below are a number of circuits manufactured by different divisions of
Fairchild Semiconductor and easily compatible with the Fairchild line of Isoplanar CMOS.
Fairchild F54LSXX/74LSXX LOW POWER SCHOTTKY TTL
(Reference: Fairchild Low Power Schottky Data Book and Fairchild Low Power Schottky Designer's Guide)
When Multi - TTL drive capability is required, the CMOS 4049B and 4050B Hex Buffers can be used to drive two standard
TTL Loads with typical delay of 45 ns (VDD = 5 V). These devices, because of the deletion of the VDD input diode, allow
High Voltage CMOS to 5 Volt TTL translation. For higher performance and additional drive capability each of the following
Fairchild Low Power Schottky devices may be used as interface/logic translating elements with capability of driving up to five
standard TTL Loads. Although the Low Power Schottky devices must be operated from a 5 V TTL supply, they can accept
input voltages up to 15 V, allowing direct interface with CMOS operated up to 15 V.
F54LS00/74 LSOO
F54LS02/74LS02
F54LS04/74LS04
F54LS08/74LS08
F54 LS09/74 LS09
F54LS10/74LS10
F54LSll/74LSll

F54LS85/74LS85
F54LS86/74LS86
F54LS89/74LS89
F54LS95/74LS95B
F54LSl 07 /74LSl 07
F54LS125/74LS125
F54LS126/74LS126

F54LS13/74LS13
F54LS14/74LS14
F54LS15/74LS15
F54LS20/74LS20
F54LS21/74LS21
F54LS27/74LS27
F54LS28/74LS28
F54LS30/74LS30
F54LS32/74LS32
F54 LS33/74 LS33
F54LS37/74LS37
F54 LS38/74 LS38
F54 LS40/74 LS40
F54LS42/74LS42
F54LS47/74LS47
F54LS48/74LS48
F54LS49/74LS49
F54LS51/74LS51
F54LS54/74LS54
F54LS55/74LS55
F54LS73/74LS73
F54 LS75/74 LS75
F54LS76/74LS76
F54LS77 /74LS77
F54LS78/74LS78
F54 LS83/74 LS83A

F54LS132/74LS132
F54LS133/74LS133
F54LS136/74LS136
F54LS138/74LS138
F54LS139/74LS139
F54LS145/74LS145
F54LS151/74LS151
F54LS152/74LS152
F54LS153/74LS153
F54LS155/74LS155
F54LS157/74LS157
F54LS158/74LS158
F54LS160/74LS160
F54LS161/74LS161
F54LS162/74LS162
F54LS163/74LS163
F54LS164/74LS164
F54LS165/74LS165
F54LS168/74LS168
F54LS169/74LS169
F54LS170/74LS170
F54LS173/74LS173
F54LS174/74LS174
F54LS175/74LS175
F54LS181/74LS181
F54LS182/74LS182

F54LS189/74LS189
F54LS190/74LS190
F54LS191/74LS191
F54LS192/74LS192
F54LS193/74LS193
F54LS194/74LS194
F54LS195/74LS195
F54LS196/74LS196*
F54LS197/74LS197*
F54LS240/74LS240
F54LS241/74LS241
F!\4LS242/74LS242
F54LS243/74LS243
F54LS244/74LS244
F54LS245/74LS245
F54LS247/74LS247
F54LS248/74LS248
F54LS249/74LS249
F54LS251/74LS251
F54LS253/74LS253
F54 LS256/74LS256
F54LS257/74LS257
F54LS258/74 LS258
F54LS259/74LS259
F54LS260/74LS260
F54LS266/74LS266
F54LS273/74LS273
F54LS279/74LS279
F54LS283/74LS283
F54LS289/74LS289
F54 LS295/74 LS295A
F54LS298/74LS298
F54LS299/74LS299
F54LS323/74LS323

*Except For Clock Inputs.

8-5

F54 LS352/74 LS352
F54LS353/74LS353
F54 LS365/74 LS365
F54 LS366/74 LS366
F54LS367/74LS367
F54LS368/74LS368
F54LS373/74LS373
F54LS374/74LS374
F54LS375/74LS375
F54LS377 /74 LS377
F54LS378/74LS378
F54LS379/74 LS379
F54LS386/74LS386
F54LS395/74LS395
F54LS398/74LS398
F54 LS399/74 LS399
F54LS502/74LS502
F54LS540/74LS540
F54LS541/74LS541
F54LS568/74LS568
F54 LS569/74LS569
F54LS573/74LS573
F54LS574/74LS574
F54LS670/74LS670

•

Fairchild Low Power Schottky devices also incorporate a unique Schottky Diode in series with the collector of the output
transistor. This diode allows the output to be pulled substantially higher than Vcc. Although the Low Power Schottky devices
must be operated from a 5 V TTL supply, a simple external pullup resistor between the LS output and the CMOS VDD
power supply will allow direct interface between Low Power Schottky Logic (VCC ~ 5 V) and high voltage CMOS logic, up
to VDD ~ 10V. With the exception of the F74LSOO, F74LS02, F74LS04, F74LS10, F74LSll, F74LS20, and the F74LS32,
each of the devices listed above will perform the low voltage to high voltage translation.

FAIRCHILD LOW POWER SCHOTTKY
2-lnput NAND Gate

Vee
1100

24k

A G--....- K

OUTPUT

8-6

75491 • 75492

9665 • 9667 • 9668

MaS TO LED SEGMENT
AND DIGIT DRIVERS

HIGH VOLTAGE
HIGH CURRENT
DARLINGTON DRIVERS

(Reference: Fairchild Linear Integrated Circuits Data Book)

(Reference: Fairchild 9665 • 9666 • 9667 • 9668 Data Sheet)

The 75491 and 75491 A, LED Quad Segment Digit Drivers interface
MOS signals to common cathode LED displays. High output curre.nt

The 9665, 9667 and 9668 are comprised of seven high voltage, high
current "pn Darlington Transistor pairs. All units feature common

capability makes the devices ideal in time multiplex systems using
segment address or digit scan method of driving LEOs to minimize the

emitter, open collector outputs. To maximize their effectiveness, these
units contain suppression diodes for inductive loads and appropriate
emmiter-base resistors for leakage.

number of drivers required.

The 75492 and 75492A Hex LED/Lamp Drivers convert MOS signals to
high output currents for LED display digit select or lamp select. The
high output current capability makes the devices ideal in time multiplex

systems using segment address or digit

SCan

The 9665 is a general purpose array which may be used with DTL,
TTL, PMOS, CMOS, etc. Input current limiting is done by connecting

an appropriate discrete resistor to each input.

method of driving LEDs to
The 9667 has a series base resistor to each Darlington pair, thus allowing operation directly with TTL or 'CMOS operating at supply voltages
of 5 V.

minimize the number of drivers required.

75491 • 75491A
• 50 mA SOURCE OR SINK CAPABILITY
• LOW INPUT CURRENTS FOR CMOS COMPATIBILITY
• LOW STANDBY POWER
• FOUR HIGH GAIN DARLINGTON CIRCUITS
• 10 V and 20 V OPERATION

The 9668 has an appropriate input resistor to allow direct operation
from CMOS or PMOS outputs operating from supply voltages of 6 to 15
V.
•
•
•
•
•
•

75492 • 75492A
• 250 mA SINK CAPABILITY
• CMOS COMPATIBLE INPUTS
• LOW STANDBY POWER
• SIX HIGH GAIN DARLINGTON CIRCUITS
• 10 V AND 20 V OPERATION

9665 • 9667 • 9668
CONNECTION DIAGRAM
(TOP VIEW)

75491 • 75491A
CONNECTION DIAGRAM
(TOP VIEW)

IN A

IN 0

OUT A

OUT D

OUT A

OUT D

VDD (GND)

SEVEN HIGH GAIN DARLINGTON TRANSISTOR PAIRS
HIGH OUTPUT VOLTAGE (VCE = 50 V)
HIGH OUTPUT CURRENT (lC ,,350 rnA)
CMOS COMPATIBLE INPUTS
SUPPRESSION DIODES FOR INDUCTIVE LOADS
2 WATT PLASTIC DIP PACKAGE ON COPPER PIN FRAME

Vee

IN A

OUT A
OUT B

OUT B

OUTe

IN B

OUT B

OUT C

IN e

OUT C

IN e

IN D

OUT D

IN E

OUT E

IN F

OUT F

IN B

75492 • 75492A
CONNECTION DIAGRAM
(TOP VIEW)

IN G
GNO

OUT A

IN A

OUT B

OUT F

IN B

IN F

FDO (GND)

Vee

IN e

IN E

OUTe

OUT E

OUT 0

IN 0

8-7

COMMON

•

96L02

J.lA775

LOW POWER DUAL
ONE-SHOT MUL TIVIBRATOR

QUAD COMPARATOR
VOLTAGE COMPARATOR

Retriggerable Resettable Monostable Multivibrator
(Reference: Fairchild Low Power TTL Book)

(Reference: Fairchild p.A775 Data Sheet)
I n a CMOS system it may be necessary to detect differences between
two voltage levels and convert to logic levels_ The p.A775 Quad
Comparator is capable of operating over the CMOS power supply range.

The 96L02 is pin and function compatible with the F4528 Dual
Monostable and exhibits improved stability and speed. It is usable in
5 V CMOS systems.
•
•
•
•
•
•

TYPICAL POWER DISSIPATION OF 25 mW/ONE SHOT
50 ns TYPICAL PROPAGATION DELAY
RETRIGGERABLE 0 TO 100% DUTY CYCLE
FAIRCHILD 4000B COMPATIBLE INPUTS
OPTIONAL RETRIGGER LOCK-OUT CAPABILITY
PULSE WIDTH COMPENSATED FOR VCC AND
TEMPERATURE VARIATIONS

•

RESETTABLE

These comparators have a unique characteristic in that the input
common mode voltage range includes 9rou nd, even though operated
from a single power supply voltage. Applications include limit
comparators, simple analog to digital converters; pulse, squarewave and
time delay generators and wide range V CO.

•
•
•
•
•
•
•

96L02 LOGIC AND CONNECTION DIAGRAM
DIP (TOP VIEW)

SINGLE SUPPLY OPERATION-+2.0 V TO +36 V
COMPARES VOLTAGES NEAR GROUND POTENTIAL
LOW CURRENT DRAIN-700 p.A TYPICAL
COMPATIBLE WITH ALL FORMS OF CMOS
LOW INPUT BIAS CURRENT -25 nA TYPICAL
LOW INPUT OFFSET CURRENT -25 nA
LOW OFFSET VOLTAGE-5 mV MAX
LOGIC AND CONNECTION DIAGRAM
DIP (TOP VIEW)
OUTPUT 2

OUTPUT 3

OUTPUT 1

OUTPUT 4

v+

'"

2"

GND

INPUT 1-

INPUT 4+

INPUT 1+

INPUT 4-

INPUT 2-

INPUT 3+

INPUT 2+

INPUT 3-

POWER SUPPLY REGULATOR
p.A78MG 4-Terminal Regulator
(Reference: Fairchild p.A78 MG • p.A79 MG Data Sheet)
This single compact regulator with its SOO mA capability is sufficient
for all but the very largest CMOS systems. The adjustable output
voltage feature allows fine tuning of system speed power product .
• Leads for external timing

•
•
•
•
•
•

OUTPUT CURRENT IN EXCESS OF 0.5 A
POSITIVE OUTPUT VOLTAGE 5 TO 30 V
INTERNAL THERMAL OVERLOAD PROTECTION
INTERNAL SHORT CIRCUIT CURRENT PROTECTION
OUTPUT SAFE AREA PROTECTION
POWER MINI DUAL IN-LINE PACKAGE
p.A78 MGCONNECTION DIAGRAM
DIP (TOP VIEW)

INPUO'
OUTPUT

2

4

COMMON

3

CONTROL

NOTE: Heat sink tabs connected to common

!

8-8

9664

9374

MOS TO LED DIGIT DRIVER

DECODER/DRIVER/LATCH
CMOS TO 7-SEGMENT
LED DISPLAY

(Reference: Fairchild 9664 Data Sheet)

(Reference: Fairchild 9374 Data Sheet)

This driver is ideal for cfriving high current devices such as LEOs, relays
and lamps. High input impedance allows direct drive from Fairchild
4000B CMOS devices; however, there is some degradation in logic level
at the CMOS output. The 9664 is specified to 10 V operation, the
9664A to 20 V.

This bipolar device contains latches for storage, a 7·se9ment decoder
and 15 rnA constant current drivers. The 9374 must operate at 5 V; its
inputs are also limited to 5 V.

•
•
•
•
•

•
•
•

150 rnA SINK CAPABILITY
CMOS COMPATIBLE INPUTS
VERY LOW STANOBY POWER
SIX HIGH GAIN DARLINGTON CIRCUITS
10 AND 20 V OPERATION

•
•
•

9664/9664A LOGIC AND CONNECTION IDIAGRAM
DIP (TOP VIEW)

FAIRCHILD 4000B SERIES COMPATIBLE INPUTS
HIGH SPEED INPUT LATCHES FOR DATA STORAGE
15 rnA CONSTANT CURRENT SINK CAPABILITY TO
DIRECTLY DRIVE COMMON ANODE LED DISPLAYS
INCREASES INCANDESCENT DISPLAY LIFE
DATA INPUT LOADING ESSENTIALLY ZERO
WHEN LATCH DISABLED
AUTOMATIC RIPPLE BLANKING FOR SUPPRESSION OF
LEADING EDGE ZEROS AND/OR TRAILING EDGE ZEROS
9374
LOGIC SYMBOL

OUTPUT 1

INPUT 1

OUTPUT 2

OUTPUT 6

INPUT 2
V DO (GND)

INPUT 3

INPUT 6

vce

712635

INPUT 5

OUTPUT 3

OUTPUT 5

OUTPUT 4

INPUT 4

4 13 12 11 10 9 15 14

Vee

Pin 16

GND

Pin

8

9374
CONNECTION DIAGRAM
DIP (TOP VIEW)

,.
15
14
13
12
11
10

8-9

•

CMOS OSCI LLATORS

This application note describes several square-wave oscillator circuits implemented with standard CMOS
gates. I n each case, appropriate timing equations, simplifying assumptions, and advantages and disadvantages
are listed.
In general, because of the characteristically high input impedance of CMOS logic elements, more cost
effective oscillators can be constructed offering relatively large timing constants without large capacitors.
I n addition, the CMOS oscillator offers:
•
•
•
•
•

Very low power dissipation
Operation over a wide power supply voltage range of 3 to 15 volts
Operation over a frequency range of less than 1 Hz to over 23 MHz
Easy interface to other logic families
Relatively good stability with respect to variations in power supply voltage and operating temperature
range

Generally, the use of buffered CMOS gates in oscillator applications is not recommended. Problems occur
because of excessive gain through the buffered element (in excessive of 106 ) compounded by the slow edge
rates, characteristic of the oscillator circuit. Ringing at the thresholds is very likely, creating false clocks in
the system. This problem is, of course, overcome with the Schmitt Trigger and its associated hysteresis.
Fairchild recommends the 4007UB, 4069UB, 40014B, 40938 and 4583B for all oscillator applications. For
simplication, all applications in this note will be implemented using the 4069UB and 400148.
Before describing any specific oscillator circuits and in an effort to clear some confusion and a few misconceptions, Figure 1 illustrates the basic logical oscillator. Any odd number of inverting logic elements will
oscillate naturally when connected in a ring as shown in Figure 1. This is easily seen by treating the inverters
as ideal switches or inverters exhibiting finite propagation delays and ideal switching characteristics. The
basic result is that a HIGH logic level chases itself around the ring. In this case the frequency of oscillation
is dependent upon the total propagation delay through the ring and is given by:

f

=

where:

f = frequency of oscillation (Hz)
n = number of inverting gates in the ring
T p = propagation delay per gate (seconds)

FIGURE 1. ANY ODD NUMBER OF INVERTING GATES WILL ALWAYS OSCILLATE

8-10

The practicality of such a circuit is limited by the fact that the frequency of oscillation is dependent upon
T p and therefore limited to a few specific values determined by T p' Furthermore, stability of such a circuit
is heavily dependent upon T p's variation with temperature, power supply voltage and output loading.
Figure 2 illustrates expected variations in propagation delay for the 4069UB.

PROPAGATION DELAY
VERSUS TEMPERATURE
35

PROPAGATION DELAY
VERSUS LOAD CAPACITANCE

II
CL = 15 pF
120r--+--r-+--r--+--r-+--t-~--i

30

~'00~-+-~-+--r--+-~-+--+-~~~
I

~

c: 25
I

>

«

>

«

=5\/

-'
LU 20

tl'I-IL \/DO___
_~O=::"\/__

0
Z

0

i= 15

«
C)
«
0..
0

10

-=~J,
_tPI-IL V OO- 1O \

-'

_.

~--

~

~

o

~ 60r--+--r-+--r--2~~~~
C)

tpLH VDD = 10 V
I
l
..I.

«
0..

/J

cc

80~-+-~-+--r--+-~

z

~ 40r--+--r~~~r--1--7
0..

0..

5

\1

tl'LI-I

VDO= 15V

tpHL VDD = 15 V

o
-60

r

I I I

-20
20
60
100
TA - AMBIENT TEMPERATURE _DC

120
160
80
40
CL ... LOAD CAPACITANCE - pF

140

200

FIGURE 2. PROPAGATION DELAY VERSUS TEMPERATURE, LOAD CAPACITANCE AND POWER
SUPPLY VOLTAGE FOR THE 4069UB

The Logical RC Oscillator
To overcome the disadvantages of the logical oscillator it is necessary to add other circuit elements that
increase loop delay and thus reduce the effect of T p variation on frequency. This increase in loop delay
necessarily reduces the upper frequency limit for a given configuration, but lends the more important
advantages of frequency predictability and stability.
Figure 3 illustrates a useful three gate oscillator incorporating a resistor capacitor network which does,
in effect, slow the natural frequency of the ring oscillator and, assuming that the RC time constant is large
enough, minimizes any effects of propagation delay and thus any dependence upon temperature, load
capacitance, or operating voltage. With this in mind, it is assumed, hereafter in the analysis, that the logic
elements are ideal, exhibiting negligible propagation delay. if very high oscillation frequencies are required,
this assumption may not be valid.

4069U B

4069U B

4069U B

V2~--.--VOUT

t:Lr
v,

FIGURE 3. A THREE GATE RC OSCILLATOR

8-11

•.

I
II
II

V1

VSSJl_--

II

VTN - VDDtf - - II
VDD

-

-

I

II

d

V2

d

tr - - -

-

II

II

Vss

~

- --

II
V D D # - ' - - 1 + - - -....

II

II

VOUT

V

I!_-..LL

s ..

S II

II 11

~ 1--

I
13
--.,,...

I

VTP ~ POSITIVE-GOING THRESHOLD VOLTAGE
VTN ~ NEGATIVE-GOING THRESHOLD VOLTAGE

11-12 --l.~ 14 ~
FIGURE 4. VOLTAGE WAVEFORMS FOR THE RC OSCILLATOR

As a means of determining a timing equation, Figure 4 illustrates the voltage waveforms at specific points
in the oscillator circuit. As shown, the voltage waveform at V 1 does, for short intervals of time, extend
outside the power supply rails. These excursions are clipped at V 2 by the standard input protection diodes
found on all Fairchild CMOS logic inputs (Figure 5). At this point another simplifying assumption is made;
input protection diodes D1 and D2 exhibit ideal characteristics. Since this assumption tends to have little
overall effect on the voltage waveforms, the error is acceptably small.

VDD

200n
NOMINAL
INPUT

C>---'''''I\r-41..-...-

TO LOG I C
TRANSISTORS
D1

VSS
FIGURE 5. INPUT PROTECTION CIRCUIT

From Figure 4, the time period T for one cycle is:

Once again, input protection diodes conduct only during t1 and t3. Similarly, except for input leakage
current, Resistor R2 conducts only during t1 and t3' Since input impedance is generally very large (> 106 n)
compared to typical values for R 1 and R2, input leakage Gurrents are negligible and it is assumed they can
be ignored. For resistor values greater than a few megohms, this may not be valid (note 1).

8-12

From basic electronics, the timing equation for exponential decay of an RC network (Figure 6) is.

t = -RC In (vIVO)

[ In (

VOO
)
VOO + VTP

+

In (

VOO
2VOO - VTN

)~+
~

In (VTN) + I (VTP))
VOO
n VOO

VOLTAGE

Vo
t

= -RC

In (vlV 0 1

v

SLOPE

= -1/RC

FIGURE 6. TIMING FOR THE EXPONENTIAL DECAY OF AN RC NETWORK

For those who prefer their timing equations not to be cluttered with details, several simplifying assumptions
can be made. First, it is assumed that negative and positive threshold voltages are equal (VTN = VTP).
This is a fairly safe assumption since standard gates will generally exhibit very little hysteresis « 200 mV).
Of course, this assumption is not valid for Schmitt Triggers.
The timing equation simplifies to:

+

in (

8-13

VOO
)]+2111 ( VT
-) \
2VOO - VT
VOO

f

Next, it is assumed that CMOS is the ideal logic family with ideal transfer characteristics and thus, VT =
VOO/2. As will be shown later, this can be a very misleading assumption. Nevertheless:
T "'" 2R,C [

OA05 R2
R, + R2

+ 0.693

]

and:
f "'"

Furthermore:
If R, = R2, f "" 0.559/R,C
If R, » R2, f "'" 0.722/R,C
If R, «R2, f "'" OA55/R,C
The last assumption is a very attractive one, greatly simplifying the timing equations, but can create correlation problems between paper calculations and actual results. CMOS is not, generally, an ideal logic family
exhibiting ideal transfer characteristics and, in fact, guaranteed threshold limits allow variations in the
timing equation constants which are much greater than those created by variations in R2/R, as implied
above.
Standard guarantees for CMOS circuits allow the actual switching threshold to lie in range from roughly
30% of VOO to 70% of VOO (VI H = 0.7 VOO and VI L = 0.3 VOO). If, in fact, actual thresholds are not
near 0.5 VOO the above simplifications can be grossly invalid. As a means of illustration, simplified timing
equations have bt:en generated assuming that VT = 0.7 VOO and VT = 0.3 VOO' The results are shown in
Figure 7. Also shown are the results of actual tests performed on the 4069UB with manufacturing date
codes from over three years of production. Actual data implies that more accurate timing equations for
the 4069UB would be:
ForR,=R2,
f","OA82/R,Cj
ForR,='OR2, f"'"0.580/R1C
For1OR,=R2, f","0.368/R,C

With expected error = ±5%

1.4 ....~-::-::-:~..,..-----r-----r------,
TA = 25°C
Voo = 10 V
1.7 I----+-~.-----_t_-----+---__I

f-

z

1.0

t----+---~rl_-----t---____i

69UB

...!069UB

~ R2

VOUT

C=¢

FIGURE 9. A TWO GATE RC OSCILLATOR MAY NOT OSCILLATE FOR
SOME VALUES OF CAPACITANCE

The Schmitt Trigger Oscillator
Where gate count is a critical factor, Figure 10 shows an Oscillator constructed from a single Inverting
Schmitt Trigger. This circuit consumes only 1/6 of a package allowing the other five inverters to be utilized
elsewhere in the system. It should be noted that the single stage oscillator is only practical where substantial
hysteresis is provided by the logic element (i.e., Schmitt Triggers). It should, also, be noted that switching
thresholds of the Schmitt Trigger are not as insensitive to variations in the power supply voltage. This
circuit is best in those applications with relaxed requirements on frequency stability or where power
supply voltages are well regulated.

8-15

v,,~o",
I

c

400148

FIGURE 10. ASIMPLE SCHMITT TRIGGER OSCILLATOR

VDD- -

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

--

VOUT

-

I

I
I
VSS-t -

-

- ....._

I

I

I

I

I
I
~ l1-t-- 12+-\

I

1

......

I

I

1

VTN = NEGATING·GOING THRESHOLD VOLTAGE
VTP = POSITIVE·GOING THRESHOLD VOLTAGE

I

FIGURE 11. VOLTAGE WAVEFORMS FOR THE SINGLE SCHMITT TRIGGER
OSCILLATOR

Figure 11 illustrates the voltage waveforms on the input and output pins of the Schmitt Trigger. Assuming
that t1 + t2» tpLH + tpH L the time period T for one cycle is:

T "'" t1 + t2
Where: t1

~ -RC In

t2

~ -RC In

or:

T~-RC

or:

T~RC

(VDD - VTP )
VDD - VTN
(VTN )
VTP

r,n (VTN)+ In (VDD - VTP).]
VTP
VDD - VTN

L'

[In (VTP) + In (VDD - VTN ) ]
VTN
\ VDD - VTP

8-16

To simplify the equation, we can assume from the 400148 data sheet that at VDD = 10 V, VTN = 6.8 V
and VTP = 3.2 V, typically.
Thus:

T"" 1.5 RC

or:

f"" 0.667/RC

Once again, from Figure 12, it can be determined that the simplification above may not be valid because
of possible variations in actual thresholds within the guaranteed worst case limits versus the typical thresholds assumed above.

1.4

ASSUMING MINIMUM HY~TERESISI "" 0.20

Joo

'x

1.2

f-

z

1.0
ASSUMING TYPICAL HYSTERESIS
"" 0.44 Voo AT Voo = 5 V
"" 0.36 Voo AT Voo = 10 V
"" 0.33 Voo AT Voo = 15 V

<{

til

~ 0.8

(.)

Cl
Z

-

~

~ 0.6

i=

/

I
><: 0.4

",

?

0.2
ASSUMING MAXIMUM HYSTERESIS"" 0.72 vorf

0.0

o

1

J

I

.1

l

5
10
Voo - POWER SUPPLY VOLTAGE - VOLTS

15

FIGURE 12. TIMING CONSTANT VERSUS POWER
SUPPLY VOLTAGE ASSUMING VARIOUS
HYSTERESIS LEVELS FOR THE 40014B

8ased on actual test data performed on 400148 devices with a variety of manufacturing date codes, the
following equation was determined:
f "" 0.631/RC
and:

For R = 1 Kn to 1 Mn
C = 10 ~F to 100 pF

with expected error"" ±1 0%

8-17

•

The Gated Oscillator
Often the designer will have a need to enable or disable the free running oscillator at will. This is easily
accomplished by adding a diode to the RC Oscillator circuit as shown in Figure 13. In one direction the
diode provides an active HIGH Enable input and in the other an active LOW Enable input. With proper
selection of the RC components, power dissipation in the disabled state can be minimized.

R
ACTIVE LOW-t>t-ENABLE
"

--14-''/

bo...

OR"

ACTIVE HIGH
ENABLE

ACTIVE LOW-t>t-ENABLE
,

.,

OR)
ACTIVE H I G H - - I 4 - " /
ENABLE

y-

_ .... C

VOUT

~OO14B

I~UB

f"

t>:UB

fo

r

~VOUT

FIGURE 13. GATED OSCILLATORS

A CMOS Crystal Oscillator
For. those applications requiring extreme stability of the oscillation frequency, a CMOS Crystal Oscillator
circuit is shown in Figure 14. Actual resistor and capacitor component values are determined by the desired
output frequency and characteristics of the crystal employed. Any odd number of inverting gates may be
used in the circuit. However, maximum operating frequency will be limited by total propagation delay
through the oscillator ring.

4069UB

CRYSTAL

o

FIGURE 14. A CMOS CRYSTAL OSCILLATOR

8-18

Finally, in applications demanding such stringent stability, it is not uncommon for the designer, for reasons
of both accuracy and cost, to select highest possible operating frequency. The result is an often critical
tradeoff between tolerable power dissipation and acceptable accuracy. For the circuit of Figure 14, as
operating frequency is increased by a factor of ten, power dissipation will also approximately increase by a
factor of ten. Only the designer can acceptably resolve this tradeoff.
Summary
Simple CMOS inverting gates provide an attractive solution to oscillator applications providing better
stability (especially at low frequency), very low power dissipation, wide operating power supply voltage
range and relatively easy interface to other logic families.
This note has offered several alternative designs for CMOS oscillators each with its own advantages, disadvantages and simplifying assumptions. F rom the information presented herein, the designer has the capabi lity
of selecting the circuit and the characteristic tradeoffs best suited to his specific application.
Note 1. As a general rule, assuming worst case data sheet limits, input leakage current will have approximately a 10% affect upon the timing
equation when R1 = 1.5 Mn at VOO = 15 V,10 Mn at VDO = 10V and 5 Mn at VOO = 5 V.

•
8-19

APPLICATION OF THE 4702B,
PROGRAMMABLE BIT-RATE GENERATOR

The industry standard Universal Asynchronous Receiver/Transmitter (UART), an MOS/LSI subsystem, has
had a considerable impact on data-communication system design. Not only has the UART dramatically
reduced chip counts and increased reliability, etc., but it has also provided an incentive to integrate the
remaining support functions.

One such subsystem is the 47026 programmable bit-rate generator, designed to provide the necessary clocking signals to operate asynchronous transmitter and receiver circuits. Several standardized signaling rates are
used for start-stop communication depending on the transmission medium and other system requirements.
The equipment must be capable of generating all the necessary frequencies and provide a way to select the
desired one. In the past, this required several SSI/MSI circuits. Now, the 47026 can perform the task more
easily and economically.

The 47026 provides anyone of the 13 common bit rates on a selectable basis using an on-board oscillator
and an external crystal; it also is expandable for multichannel applications. In its most general form, multichannel clocking requires that any of the possible frequencies must be available on any channel. Expansion
up to eight channels is accomplished without device duplication. In multiple-device systems, there is no need
to use a crystal with every device. Figure 1 shows the block diagram of the 47026 which consists of the
following major parts:
•
•
•
•
•

Oscillator and associated gating
Scan counter
Count chains
I nitialization circuit
MUltiplexer and output storage

Oscillator and Associated Gating
The oscillator circuit together with an external crystal generates the master timing. A 2.4576 MHz crystal
provides 16 times the frequency of the baud values marked; for example, 9600 baud corresponds to 153.6
kHz. If the External Clock Enable (ECp) is HIGH, the oscillator output signal drives the count chain. On
the other hand, if it is LOW, the External Clock (CP) signal is enabled and is then the timing source. The
External Clock input also participates in the device initialization scheme. The master timing signal, either
from the external source or the local oscillator, is available on the Clock Output pin (CO). This signal can
be used to drive other 47026's in a multiple device system, thus eliminating the need to provide more than
one crystal.
8-20

Scan Counter
The master timing drives a 3-bit binary scan counter which, in turn, drives the remaining counter chains on
the chip. The scan counter allows expansion to eight channels as described later. The prescaling feature of
this counter provides another benefit, i.e., it moves the input frequency to 2.4576 MHz which is ideal for
low-cost crystals. If it were not for the scan counter, the 47028 would require a more expensive crystal of
about 300 kHz.
Count Chains
The scan counter output drives an 8-bit binary counter which provides the frequencies corresponding to
9600, 4800, 2400, 1200, 600, 300, 150 and 75 baud. The 1800-baud signal is generated by dividing 9600
by 16/3. The 110 and 134.5 baud signals are approximated by dividing 2400 by 22 and 18 respectively.
Dividing 1200 by 6 gives the 200 baud signal, while 50 baud is generated by dividing 200 baud by 4. All
division factors except 16/3 are even; thus, all outputs except 1800 baud have a 50% duty cycle.
The actual division by 16/3 is achieved by using a sequence of integers 5 and 6 such that cumulative error
after every three cycles is zero. This scheme, in conjunction with the divide by 16 performed in the UART,
achieves good timing accuracy demanded by high speed communication equipment. Calculations indicate
that the maximum distortion introduced does not exceed 0.78% regardless of the number of elements in a
character.
Initialization Circuit
This circuit generates a Master Reset signal to initialize the flip-flops on the 47028 to a known state. If the
External Clock Enable (ECp) is LOW, the local oscillator output is inhibited and timing is derived from the
External Clock (CP). The first positive half cycle of the External Clock is used to generate the Master Reset
and all succeeding clock signals. are used for timing. This initialization scheme allows software-controlled
diagnosis for fault isolation.

OSCILLATOR

ECp
CP

SCAN
COUNTER

•

COUNTER NETWORK

1--;::===}-<1

INITIALIZATION

CIRCUIT

r==tt====!~'3(3001

'-:===---1 14 (1501
15(110)

Fig. 1. 4702B Block Diagram
8-21

MUltiplexer and Output Storage
All the desired outputs from the count chains are fed as data inputs to a multiplexer. The select inputs for
this mUltiplexer are brought out as Rate Select input (SO - S3). Table 1 shows the correspondence between
this code and the resulting frequency. The multiplexer output is fed as data input to a resynchronizing
flip·flop that is clocked by the leading edge of the mastertiming.
If only single-channel applications of the 4702B were considered, the output flip-flop would be unnecessary.
In multichannel applications, however, the Rate Select inputs change as a function of the Scan Counter
output (00 - 02). The resynchronizing flip-flop assures a fixed timing relationship between 00 - 02 and
the Bit Rate output (Z).
Three important features should be noted from Table 1. First, two of the select codes specify Multiplexed
Input (1M) signal as the data source to the multiplexer. The user can feed a signal into this input, however,
the primary intent was to feed a static logic level to achieve a "zero baud" situation. Secondly, the codes
corresponding to 110, 150,300, 1200 and 2400 baud each have a maximum of only one LOW level. These
are the most commonly used rates in contemporary data terminals. Thus the rate select mechanism on these
terminals need only be a single-pole 5-position switch with the common terminal grounded. Thirdly, 2400
baud is select by two different codes so that the whole spectrum of modern communication rates will
have a HIGH code in the most significant bit position.
Typical Applications
In those applications where the Rate Select inputs are static levels, operation of the 4702B is rather straightforward. The multiplexer connects the specified counter output to the data input of the output flip-flop.
Because the flip-flop is clocked by the master timing, its output reflects the selected frequency.
Single-Channel Bit-Rate Generator
Figure 2 shows the simplest of all 4702B applications. This circuit provides one of five possible bit rates as
determined by the setting of the 5-position switch. The generated frequencies correspond to 110, 150,300,
1200, and 2400 baud depending on the switch setting. For many low cost terminal applications, these five
selectable bit rates are adequate. The 4702B is not only intended for single-channel but also for multichannel operation, as illustrated in the following applications.

53
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

52
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

51
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

50
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

OUTPUT RATE IZI
MULTIPLEXED INPUT OM)
MULTIPLEXED INPUT IiMI
50 BAUD
75 BAUD
134.5 BAUD
200 BAUD
600 BAUD
2400 BAUD
9600 BAUD
4800 BAUD
1800 BAUD
1200 BAUD
2400 BAUD
300 BAUD
150 BAUD
110 BAUD

10

I

~

SP5T SWITCH

2r~
31 1 4

CplM 80 5 ,52 5 3
ECp

47028

_~'X
Ox
co 00 0 ,°2
2t~~:T~~'
CIRCUIT

Z

I I I I I
OUTPUT

Fig. 2. Switch Selectable Bit-Rate
Generator Configuration Providing 5 Bit Rates

Table 1. Truth Table for Rate Select Inputs
8-22

Multichannel Bit-Rate Generation
Figure 3 illustrates a fully programmable 8-channel bit-rate generator system. Two 4 x 4 register file devices
(9LS170) can be loaded with information (rate select codes from Table 1) relating to the desired frequency
on a per-channel basis. For clarity, circuits for writing into the files are not shown.
The least significant Scan Counter outputs (00,01) control the Read Address of the 9LS170s while the
most significant output (02) controls the Read Enable (RE) inputs. Thus, as the counter advances, file
locations are read out sequentially. The Scan Counter outputs are also the Address inputs for the 93L34
addressable latch. The Bit Rate output (Z) of the 4702B is the Data input to the 93L34 while the Clock
Output is the Enable input.
To understand the operation, consider the instant when the Scan Counter outputs become Zero (00 - 02
= LOW). The same clock that incremented this counter to Zero also clocked the counter output, corresponding to the selected frequency for channel 7 into the output flip-flop, and disabled the 93L34 latch via
the Clock Output (CO), thus preventing any change in the latch outputs while the Scan Counter outputs
and the Bit Rate output (Z) are changing.
During the second half of the clock cycle, when the Clock Output (CO) is LOW, the counter output representing the selected frequency for channel 7 is loaded into the 93L34 latch and.is locked up on the 00
output.

1
~
2.4576 MHz
CRYSTAL __
CIRCUIT

I
A,

I
AD

RE

74lS17Q

1

00 0 ,°2 Q3

III

--co=

CplM So 5,5253
ECp

4702

'x
Ox
co

OOQ,Q2

~,o"

Z

.-

Q7 CHANNEL 6

9lS04

D

L-

A,

I
AD

HE

CHANNEL 5

05

CHANNEl4
CHANNEL 3
CHANNEL 2

0,

93L34 Q3
E

I

06

02
0,
00

I

CL

CHANNEL 1
CHANNEL 0
CHANNel 7

10-

~j'r

74LS170

°0 0 ,02 0 3

II~

Fig. 3. A Fully Programmable 8·Channel Bit-Rate Generator System
8-23

•

The Scan Counter outputs (00 - 02), which represent the selected channel, are used to interrogate the
register file to determine the assigned bit rate for channel O. The stored code for channel 0 is routed to the
Rate Select inputs (SO - S3) to select the appropriate internal frequency, so that during the next LOW-toHIGH clock transition, the state of this internal signal is clocked into the output flip-flop. Thus, each
channel is sequentially interrogated and the 93L34 latch is updated at least once during each half cycle
of the highest output frequency (9600 baud).
By connecting the Scan Counter output 02 to the Multiplexed input (1M) a similar technique can be used
to implement a system with a maximum output frequency of 19,200 baud, however, the number of channels must be limited to four. This ensures that the output will be interrogated and updated at least once
during each half cycle of the highest output frequency (19,200 baud).
Jumper Programmable 8-Channel Bit-Rate Generator

In systems where channel-speed assignments remain relatively fixed, software-controlled channel assignment
is not necessary or practical. It may be simpler to program with "jumpers" at appropriate places in the
system. See Figure 4.

93134

I

lrEE~~~~~~fl~~

AO
:;

CHANNEL 6

~~

CHANNEl 5

as

~~:~~~~:

°4
2
03 CHANNEL 1

°2
Q,

CHANNEL a
CHANNel 7

00

CLIo---93LOl

Fig. 4. Jumper Programmable 8-Channel Bit-Rate Generator
8-24

In the jumper programmable 8-channel bit-rate generator, the scan counter outputs (00 - 02) are fed as
Address inputs to a 93L01 decoder and a 93L34 addressable latch. The decoder outputs drive the diode
clusters which contain four diodes for each channel. All four diode cathodes in a cluster are connected
together to a decoder output; the anodes of corresponding diodes in every cluster are connected together to
the appropriate Rate Select inputs of the 4702B. Presence of a diode results in a LOW on the particular
4702B input; when a diode is absent, a HIGH results. As the scan counter advances, the decoder outputs
activate the desired bit-rate code for that channel. The 93L34 synchronously demultiplexes the 4702B
output (Z) and reconstructs the specified bit rates at its output.
32 Times Frequency Bit Rates

The 4702B is designed to generate all the common communication bit rates at actual frequencies of 16
times the selected bit rate. The 16 times frequency is sufficient to operate UARTs. However, some recent
LSI devices intended as UART replacements require 32 times frequency on their clock inputs. This note
describes an elegant scheme to achieve this without a corresponding increase of the crystal frequency.
Figure 5 illustrates a fully programmable 8-channel system. Two 9LS170 devices are used to store the
channel frequency selection information. These devices can be loaded with information on a per channel
basis. For clarity, circuitry for writing into these devices is not drawn. The least significant SCAN counter
outputs (00 and 01) of the 4702B are used as the read address inputs of the 9LS170s. The most significant
bit (02) is used to control the read enable (R E) inputs of the 9LS170s. The 00 - 02 outputs of the
4702B are also the inputs to a 9LS138 decoder. The clock output (CO) of the 4702B is used to control one
enable input (E 1) of the 9LS138. The CO output is also the clock input (CP) for the 9LS 164 shift register.
The Z output of the 4702B is the data input (A) to the 9LS164. The Z output of the 4702B is also tied
into an exclusive NOR gate (4077B) as one input. The second input to the exclusive· NOR gate is the 07
output of the 9LS164. The output of the exclusive NOR gate controls the second enable input (E2) of the
9LS138. The outputs (00 - 07) of the 9LS138 are the desired output clock signals.

To understand the operation of this circuit, consider the LOW-to-H IGH transition of the CO output of the
4702B when the SCAN counter outputs change from "7" (HHH) to "0" (LLL). From this transition to
the next LOW-to-H IG H transition of the CO, the Z output of the 4702B reflects the state of the channel 7
counter output. The 00 - 02 outputs of the 4702B are LOW and hence information for channel 0 will be
available on the 9 LS 170 outputs. The So - S3 inputs of the 4702B are connected to the 9 LS 170 outputs.
On the LOW-to-HIGH transition of the CO output channel 0 counter will be clocked to the Z output.
This transition also clocks the 9LS164. The SCAN counter also increments on this transition and will
point to channel 1. As the clocking continues, 9LS170 locations will be read out sequentially and information will be shifted into the 9LS164. After eight clock transitions the previous channel 7 output will be at
the 07 output of the 9LS164, and the current channel 7 output will be on the Z output of the 4702B. The
output of the exclusive NOR gate will be LOW if the inputs differ; i.e. whenever the channel 7 output is to
make a transition the output of the exclusive NOR gate will be LOW. The CO output is connected to the
E2 input of the 93LS138 and during the. negative half cycle of the clock the 0 0 output of the 9LS138
will be LOW. The 4702B internal counters generate 16 times the selected bit rate. The exclusive NOR gate
is generating a signal whenever the selected counter is making a transition. This scheme will result in 32
times the selected bit rate. As the clocking continues each channel is serially appearing on the 07 output
of the 9LS164 and will be compared with the corresponding current channel output. The 9LS138 will
then represent the appropriate frequency at its output as shown in Figure 5.

Clock Expansion
The basic 4702B can be expanded to a maximum of eight channels. In applications where more than eight
channels are needed, the 4702B must be duplicated. The device is designed with a clock-expansion feature;
therefore only one crystal is required to operate all the channels.
The most economical expansion scheme provides one 4702B with a crystal and all other devices derive their
timing from this master. The device wiring is such that the External Clock Enable input and Ix input of all
but the master device feeds into the External Clock input of all the other devices. The Clock output of each
device is connected to its associated 93L34 Enable input as before. An alternative scheme is shown in
Figure 6.
8-25

•

I

..c::. 1
--,

2.4S76 MHz
CRYSTAL CIRCUIT VOO

1/6 OF A
4069UB

~

r11

1
RE

I

I

r-

AO 74LS170
Al
Oo 01 02 03

~~

r~·I

W

_

1M

S3 S2 Sl

So

ECp
IX
4702B
Ox

~

Cp Co

00 01 02

Z

07
06

p- CH6

E2

Os

p- CH4

E3

04

-C El

03

1/4 OF
A 4077B

74LS138

dDo-c

Z
m

I

-

RE
AO

L - - Al

74LS170

00 01

-

p- CH3
p- CH2

A2

02

p- CHl

Al

01

p- CHO

AO

0 0 p - CH7

.-

Q2 Q~

1

_

0"- CHS

L..-

A

-

B

74LS164

_.

CpNR

Go Ql 0 2 03 04 Qs 06 Q7

Y I I I I I I I L. ."*.-..
Fig. 5. A Fully Programmable 32 Times Frequency Bit Rate Generator System

The advantage of this scheme is that it can be conveniently used to implement the software external clock
feature mentioned previously. Imagine that the External Clock Enable (ECp) inputs of all the 4702B's in
the system are c~ntrolled by the output of a flip-flop (mode) and the External Clock inputs (CP) of all the
devices are tied .'together and software driven, possibly by operating another flip-flop. During normal
operation, the mode control is HIGH, thus selecting the crystal oscillator for timing. Also, the external
Clock input of each device is held LOW. When the External Clock Enable goes LOW, in preparation for the
diagnostic mode, all devices receive their timing from the External Clock input. When this input goes HIGH
for the first time, all devices generate an internal Master Reset signal clearing their counter chains. The next
HIGH-to-LOW transition sets the internal control flip-flop and thus terminates the Reset; all counters are
free to start counting in response to the External Clock signal.

I I I I I
EXTERNAL CLOCK

MODE CONTROL

CplM So 5, 52 53

~CP

47028

~;x
_~...

CO 00Q,02

2.4576 MH,
CRYSTAL CIRCUIT

I

Z

I I I I

I I I I I
+---+--ol'cp
~ IX
-

o~o

47026
000,°2

Z

I I I I I

Fig. 6. Tandem Clock Expansion Scheme

8-27

•

USING THE 47038 FIFO
The First-I n First-Out (FI FO) memory is read/write memory which automatically stacks the words in the
same order as they were entered and makes them available at the output in the same sequence, thus its
name first-in first-out.
Description
The 47038 FIFO is a 16 x 4 parallel/serial memory consisting of the following (Figure 1).
• An input register with parallel and serial data inputs as well as control inputs and outputs for input
handshaking and expansion.
• A 4-bit wide, 14-word deep fall-through stack with self-contained control logic.
• An output register with parallel and serial data outputs, control inputs and outputs for output handshaking and expansion.
Parallel data is entered into the input register by using DO through D3 as data inputs and Parallel Load (pL)
as the strobe. A HIGH at the PL input operates the direct set and clear inputs of the input-register flip-flops.
The quiescent state of the PL input is LOW.
To enter data serially, DS is used as the data input and CPSI as the clock. The input register responds to
the H IGH-to-LOW clock transition and the quiescent state of the CPSI input is LOW. For the CPSI to effect
shifting, the Input Expand Serial (IES) input must be LOW.
Whenever the input register receives four data bits whether by serial or parallel entry, the status output
signal, Input Register Full (I R F), goes LOW. If the Transfer to Stack (TTS) input is activated with a LOW
pulse, data from the input register is transferred into the first stack location (provided it is empty). As soon
as data is transferred, the control logic attempts to initialize the input register so that it can accept another
word; however, the initialization is postponed until the PL input is LOW. The device is designed so that the
TRF output can be connected to the TTS input. Thus, when a data word is received by the input register, it
automatically enters the stack and falls through toward the output, pausing only as needed for an "empty"
location.
Normally, the Output Register Empty (ORE) is LOW, indicating that the output register does not contain
valid data. As soon as a data word arrives in the register, the ORE output goes HIGH, indicating the presence
of valid data. If the Output Enable (EO) input is LOW, the 3-state buffers are enabled and data is available
on the 00 through 03 outputs.
Data can be extracted either serially or in parallel. The Os is used for serial data output and CPSO for the
clock input. The Os output is also available through a 3-state buffer; however its enabling is controlled
internally. Output register shifting occurs on the HIGH-to-LOW transition of the CPSO whose quiescent
state is LOW. As soon as the last data bit is shifted out, the ORE output goes LOW, indicating that the
output register is empty.
The quiescent state of the TOS input is LOW. A H IGH-to-LOW transition on this input causes new data to
be loaded from the stack into the output register (provided data is available). The 0 R E output can be
connected to the TOS input so that as soon as the last bit is shifted out, new data is automatically demanded.
The quiescent state of the TOP input is HIGH and a LOW-to-HIGH transition causes new data to be loaded
into the output register. Moreover, a HIGH level on the TOP input causes the ORE to go LOW. The TOP
input can be connected to the EO input so that the output data can be enabled when EO is LOW. When the
output is disabled, new data is automatically demanded. It should be noted that the TOS input does not
affect the 0 R E output.
The FIFO is initialized by a LOW signal on the Master Reset (M R). This causes the status outputs, IRF and
ORE, to assume an empty state; i.e., IRF is then HIGH and ORE LOW. It is important to remember that
the MR does not clear all the data flip-flops; it only initializes the control. Specifically, the 00 - 03 outputs
are not affected by the Master Reset.
8-28

IRF

@

Voo
VSS

o

= Pin
= Pin

24

@@@@

12

= Pin Numbers,

DO - D3

Parallel Data Inputs

DS
PL

Serial Data Input
Parallel Load Input

CPSI

Serial Input Clock Input (HIGH-toLOW Triggered)

CPSO

Serial Output Clock Input (HIGH-to-LOW Triggered)

IES

Serial Input Enable (Active LOW)

TTS

Transfer to Stack Input (Active LOW)

TOS

Transfer Out Serial Input (Active LOW)

TOP

Transfer Out Parallel Input

OES

Serial Output Enable Input (Active LOW)

EO

Output Enable Input (Active LOW)

MR

Master Reset Input (Active LOW)

iRF

Input Register Full Output (Active LOW)

ORE

Output Register Empty Output (Active LOW)

00- 03

Parallel Data Outputs

Os

Serial Data Output

Fig. 1. 4703B Block Diagram

8-29

Expansion
The 4703B can be vertically expanded to store more words or horizontally expanded to store longer
words (in multiples of four bits) without external logic. Also, the expansion scheme fully preserves the
parallel/serial data features. To illustrate the expansion connections, a F I Fa array consisting of eight
devices is shown in Figure 2. If there are m devices in a row and n rows, the array provides (15n + 1)
words of storage with 4m bits in each word. The reduction in storage to (15n + 1) words instead of 16n is
quite common in such expansion (see explanation at end of this section). Data is entered into devices 1
through 4 and extracted from devices 5 through 8.
The DS inputs of the first four devices are bussed together and serial data is entered on this line. The CPSI
inputs are also connected together for clocking the serial data. The I ES input of device 1 is connected to
ground, while the I ES inputs of devices 2, 3 and 4 are each connected to the fRF output of the preceding
device. The TRF output of device 4 feeds into the TTS inputs of all four devices.
After initialization by a LOW level on the MR input, the IRF outputs of all four devices are HIGH. Under
these conditions, only device 1 responds to the CPSI because its I ES input is LOW. The first four clock
pulses shift four data bits into the device 1 input register; its I RF output then becomes LOW. The first data
bit is located in a flip-flip corresponding to the DO input of device 1. Control logic inhibits the CPSI from
further affecting this device.

rl0-30-20-,-00------0-,-06-05-04 PARALLEL DATA

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Fig. 2. 31 x 16 FIFO Array

8-30

Because the IES input of device 2 is now LOW, the clock starts shifting data into the input register of
device 2. On the eighth clock pulse, the TRF output of device 2 goes LOW and disables shifting of device 2.
This process continues on devices 3 and 4. Therefore, on the 16th clock pulse, the iRF output of device 4
becomes LOW and activates the TTS inputs of all devices. The stack control logic in each device responds
by transferring data into each stack from the respective input register, and the input registers are initialized.
Thus the I R F outputs of all devices become HIGH once again. An automatic priority scheme assures that
ifthe IRF output of device 4 is HIGH, the input registers of all four devices have been initialized. The timing
diagram for 16 bits of serial entry into the array is shown in Figure 3.
Parallel entry into the array is made with a HIGH level on the PL inputs. The same conditions prevail in the
input section that exist after the 16th clock pulse in the serial entry mode. The stack controls do not
initialize the input registers until the PL inputs are LOW to assure proper device operation.
Data loaded into the stacks eventually arrives at the output registers of the first four devices. Normally, the
ORE outputs are LOW due to initialization; however, as soon as data is loaded into each output register, the
ORE goes HIGH. An automatic priority scheme, similar to the one for data entry, also exists at the output.
Thus a HI G H level on the 0 R E output of device 4 guarantees that val id data is present in all the output
registers.
The 0 RE output of device 4 is connected to the P L inputs of devices 5 through 8, as well as to the TOS
inputs of the first four devices. It should be noted that if serial extraction from the output is not desired,
the TOS inp~ts can be connected to ground instead. The EO inputs of the first four devices are connected
to ground; thus the contents of an output register are available on the appropriate outputs.
The HIGH level on the ORE outputs of device 4 activates the PL inputs of devices 5 - 8, thus forcing the
data outputs from each device in the first row into the input register of the corresponding device in the
second row. The iRF output of device 8 is connected to the TOP inputs of devices 1 - 4 and to the TTS
inputs of devices 5 - 8. Because the PL inputs are HIGH, the IRF outputs of devices 5 - 8 are LOW,
therefore establishing a LOW on the TOP inputs of devices 1 - 4. This causes the ORE of devices 1 - 4 to

,

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4

5

6

7

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STORED IN
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Fig. 3. Serial Data Entry for FIFO Array
8-31

12

1'3

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14

STORED IN
DEVICE 4

I~

•

go LOW and hence the PL inputs to devices 5 - 8. Furthermore, the LOW on the fRF output of device 8
also activates the TTS inputs of devices 5 - 8, thus initiating a fall-through action. The stack controls in
devices 5 - 8 initialize their respective registers and the TRF outputs go HIGH. An automatic priority
scheme is iso present at the inputs of devices 5 - 8. The H IG H on the iRF output of device 8 restores the
TOP inputs of devices 1 - 4 to the quiescent state.
If the stacks of devices 5 - 8 are full, activating the TTS inputs by the LOW I R F output of device 8 would
not initiate a data transfer from the input registers. The fRF output of device 8 would remain LOW until
the data can be successfully transferred into the stacks. Thus, as long as devices 5 - 8 are holding 16 words,
the I RF output of device 8 remains LOW. This also holds the TOP inputs of devices 1 - 4 LOW. As long as
they remain LOW, data cannot be loaded into the output registers from the stacks because a LOW-to-H IG H
transition at the TOP inputs is needed to demand new data. Under these circumstances, devices 1 - 4
temporarily lose the ability to use their output registers and hence can hold only 15 words. As a reSUlt, the
two rows have a storage capacity of 31 words instead of 32; and, for the general case, the storage capacity
of an n-row array is (15n + 1) instead of 16n.
The data loaded into the stacks eventually arrives at the output registers of devices 5 - 8, at which time
the ORE outputs go HIGH from the LOW state originally initialized by the MR input. The automatic
priority scheme is still in effect, and the data from the output can be extracted either in serial or parallel
format.
The Os outputs of devices 5 - 8, each available through a 3-state buffer, are connected together and the
serial data output from the array appears on this line. The epso inputs are also connected together and the
line driven by the output clock. When there is no valid data in the output register, Os is disabled and is
therefore in a high impedance state.
The OES input of device 5 is connected to ground and device 6, 7 and 8 each receive its OES input from
the preceding device. As soon as data arrives in the output registers of devices 5 - 8, the ORE outputs go
HIGH and the 3-state buffer of device 5 is enabled so that its Os output becomes identical to its 00 output.
The Os outputs of devices 5 - 8 are in a high impedance state. The clock on the epso input shifts the
device 5 output register and data is shifted out in the same bit order as entered at the array input. After the
fourth clcok pulse, the ORE output of device 5 goes LOW and its Os output is disabled into the high
impedance state.
The ORE output of device 5 establishes a LOW on the OES input of device 6. This enables its Os output
buffer and a signal, corresponding to that of the 00 output, appears on the serial output line. Device 6 now
responds to the clock inputs and, after shifting the data out, its Os output goes into a high impedance
mode. The LOW on the ORE output of device 6 enables device 7. This process continues until the last data
bit has been shifted out of device 8, at which time its ORE output goes LOW. This activates theTaS inputs
of devices 5 - 8 and new data can then be loaded from the stack when available. The timing diagram for
16 bits of serial data extraction is shown in Figure 4.
Data can be extracted from the array in parallel by activating the TOP inputs of devices 5 - 8 LOW. New
data is loaded into the output registers on the LOW-to-HIGH transition of this input. The TOP and EO
inputs can be connected together so that data can be automatically extracted.
Automatic Priority Scheme
Most conventional FIFO designs provide status signals analogous to the ill and ORE outputs. However,
when these devices are operated in arrays, unit-to-unit delay variations require external gating to avoid
transient false-status indications. This is commonly referred to as composite-status signal generation. The
design of the 4703B FIFO eliminates this problem. An automatic priority feature is built in to assure that
a slow device will automatically predominate, irrespective of location in the array.
In Figure 3, devices 1 and 5 are defined as "row masters". Devices 2, 3 and 4 are "slaves" to device 1
while devices 6, 7 and 8 are slaves to device 5. The row master is established by sensing the IES input during
the period when the MR input is LOW. Because of the initialization, the iRF outputs of all devices are
HIGH for a short time after the HIGH-to-LOW transition of the MR input. Thus IES inputs of all devices
except 1 and 5 are HIGH. This condition is sensed by the device logic to establish the row mastership.
8-32

(PSO

I
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'O~

DEVICE 5

I

ORE
I
I

,
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k--

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'0--+-1

DEVICE 6

I
I

aRE

,

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I

I
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k--

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to+---------!

DEVICE 7

I
I
k------

L...-------r---I:I

ORE

DEVICE' 8, TO-S ALL DEVICES

I

I

I

I

Po----t

t---

ORE~~~~~~~----------------------------------------~~

DEVICE 5

DEVICE 6

DEVICE 7

DEVICE 8

Fig. 4. Serial Data Extraction for FI FO Array

All devices in any given row transfer data from their input registers into the corresponding stacks
simultaneously. However, no slave can initialize its input register until its IES input goes HIGH. Thus
initialization starts with the row master and eventually ends at the last slave in the row.
A similar situation occurs at the output registers of all devices in a row. They are loaded simultaneously
from corresponding stacks; however, the ORE ouput of a slave cannot go HIGH until its OES input is
HIGH. Thus the row master is the first to indicate a HIGH on its ORE and eventually the slaves will follow.
It should be pointed out that this automatic priority scheme reduces the maximum operation speed of the
array. If speed is essential, the master-slave hierarchy can be replaced by the traditional composite-status
signal-generation scheme, which requires external gating.
Other Expansion Schemes
The expansion scheme illustrated in Figure 3 is quite simple and straightforward. It does not require any
external support logic to achieve the desired expansion and retains all the serial/parallel features. However,
these advantages are not without sacrifice-one storage location is eliminated at the interface between
rows-and the n-row array has a storage capacity of 15n + 1 instead of 16n words. Moreover, the automatic
priority scheme results in a ripple action from row master to the last slave in that row for the status signaling.
This reduces the maximum operation frequency of an array and the inherent speed of the individual devices
is not fully utilized.
The 4703B F IFa, because of its versatility, can be used to overcome both above disadvantages with minimum external logic. A vertically expended array, consisting of three FIFOs, yields 16n words of storage
for an n-row array (Figure 5). After initialization by a LOW level on the MR inputs, the fRF outputs of
all three devices are HIGH and the ORE outputs LOW. The AN D gates (4081 B) at the row interface are
thus disabled. The PL inputs of devices 2 and 3 are LOW. Now, if the input register of device 1 receives four
bits of data, then fRF output goes LOW. This activates the TTS input and the data falls through into the
output register of device 1 and the ORE output becomes HIGH. Since the TRF output of device 2 is HIGH
from initialization, the AND gate between devices 1 and 2 is enabled and the PL input of device 2 becomes
HIGH. Data from device 1 is loaded into the input register of device 2 causing the fRF output of device 2
8-33

•
:

PARALLEL DATA IN

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Pl\RAC~!61

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47038
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Fig. 5. Expansion without Sacrificing a Storage Location at the Interface
8-34

to go LOW. Moreover, a HIGH level on the PL input of device 2 results in a LOW level on the TOP input of
device 1. As a result, the ORE output of device 1 also becomes LOW. Either way, the AN D gate is disabled
and the PL input of device 2 goes LOW and the TOP input of device 1 becomes HIGH.
The LOW level on the IR F output of device 2 activates its TTS input and initiates a fall-through action; the
data appears at the output register. Because the TOP input of device 1 is HIGH, new data arrives at the
device 2 output register. When data appears at the output of device 2, the AN D gate at the interface of
devices 2 and 3 is enabled. Bya similar action described above, device 3 takes the data word into its input
register and passes it on to the output. Thus, if 16 words are loaded at the input to the array, the 1st word
is located in the output and the 16th word is in the input register of device 3. Device 3 is full now and its
I RF output remains LOW until data is extracted. This LOW level disables the AN D gate between devices 2
and 3 and hence any arrival of new data into the output register of device 2 does not activate the PL input
of device 3. As new data is received, it is arranged in devices 1 and 2 so that the 17th data word falls into
the device 2 output register and the 48th word remains in the input register of device 1. Forty-eight data
words fill all devices in the array. Under these conditions, the status output is as follows: the I RF outputs
of devices 1, 2 and 3 are LOW and the 0 R E outputs of devices 1, 2 and 3 HI G H.
The data extraction takes place when the TOP input of device 3 is activated; normally it is HIGH. To
extract data, TOP is made LOW and then HIGH. When the TOP input is LOW, the ORE of device 3 goes
LOW. When TOP is returned HIGH, data is demanded from the stack.
The internal control in device 3 loads the second data word into the output register and the OR E goes
HIGH. The internal control also initiates a fall-through action in device 3. Thus, the 16th data word that
was located in the input register is transferred into the device 3 stack and the input register is initialized.
Thus, the fRF output of device 3 becomes HIGH.
The 17th data word is located in the output register of device 2, hence the ORE output is HIGH. When the
output of device 3 becomes HIGH, the AND gate at the interface causes the PL input of device 3 to go
HIGH and the TOP input of device 2 LOW. The 17th data word then goes into the input register of device
3. The internal control of device 2 initiates fall-through action so that the 18th word falls into the output
and the 32nd word is transferred into the stack. This results in a HIGH at the TFfF output of device 2.
Similar action takes place between devices 1 and 2 with the net result that all data has fallen one location
creating a vacancy in the input register of device 1. It is now clear that this FIFO array has a 48-word
capacity without affecting the serial/parallel data feature at the input or the output. It can then be concluded that if an array of n rows is constructed using the proposed scheme, the effective storage capacity
of the FIFO is 16n words.

TRF

The array of Figure 6 has all the features and yet operates at a higher speed than the array shown in
Figure 2. Whenever the TRF output of device 1 is HIGH, the IES inputs of devices 2, 3 and 4 are also
HIGH. Therefore, when the array is initialized by a LOW level on the MR inputs, device 1 is the row master
and devices 2, 3 and 4 are the slaves. I n the second row of devices, the I R Fs and IESs are interconnected so
that device 5 is also a row master and devices 6, 7 and 8 are slaves.
When serial data is entered into the array, device 1 receives the first four bits of data. Devices 2, 3 and 4 do
not respond to the clock since all three I ES inputs are HIGH. After the 4th bit, the TRF output of device 1
is LOW. This disables device 1 from responding to the clock and enables device 1 so that the next four bits
are entered into device 2. Devices 3 and 4 remain disabled by a HIGH level on the IES inputs. After the 8th
bit, the iRF of device 2 becomes LOW, thus disabling device 2 and enabling device 3. After the 12th bit,
the 1RF output of device 3 is LOW and thus device 4 is enabled. After the 16th bit, the IRF output of
device 4 is LOW. So far, the serial data entry into this array is identical to that for the array in Figure 2.
The LOW level on the IRF output of device 4 activates the TTS inputs of all 4 devices, causing the transfer
of data into the stacks. Although all devices transfer data into the stack simultaneously, device 1 (row
master) is the first to initialize its input register. Since devices 2,3 and 4 are slaves, they need a HIGH on
their IES inputs for input-register initialization. As soon as the fRF output of device 1 goes HIGH due to
initialization, the IES inputs of devices 2,3 and 4 become HIGH and their input registers are initialized
simultaneously. This is in contrast to Figure 2 where device 3 has to wait for device 2 to initialize, etc.
The ripple action of input initialization has been overcome by simple gating. The fRF outputs of devices 1,
8-35

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8-36

2, 3 and 4 are fed into 4-input AND gates (4082B) to generate the composite input status. To obtain an
indication that the input register of the array is empty, the input register of each device in the first row
should be empty.
The ORE and OES interconnections for the second row are essentially similar to the input section. This
gating at the output section eliminates the rippling effect of the output status indication. If the gating
arrangement used in Figure 5 is incorporated into the array of Figure 6, the result is a 32 word x 16-bit
FIFO network.
As shown in Figure 8, higher FIFO speeds may also be attained by adding one 4518B and implementing
a multiplexed expansion scheme. Figure 7 shows the conventional horizontally expanded 8-bit array with
16 words of storage.
Serial data is entered using the DS as the data input and CPSI as the clock input. Shifting takes place on the
HIGH-to-LOW transition of the CPSI input. When the first four bits of data are entered into device 1, its
IRF output goes LOW indicating that its input register is full. The LOW on the IRF output of device 1
enables device 2 and disables device 1. Device 2 will shift the next four data bits into its input register.
When the input register of device 2 is full, its iRF output goes LOW. The LOW on the iRF output of device
2 activates the TTS inputs of both devices. Thus, data from the input registers of both devices is loaded into
their respective stacks simultaneously. The control logic in each device then initializes its input register in
preparation to accept more incoming data.
In Figure 7, device 1 is called the row master and is privileged to initialize its input register first. This results
in a HIGH on its iRF output. Device 2 (slave) senses this and allows its iRF to go HIGH. This master/slave
scheme is built into the 4703B so that device to device speed variations do not cause transient false status
indications. However, this is effectively a ripple action and limits the ultimate operating speed of the array.
A multiplexing scheme is proposed that achieves much higher operating speeds.

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c

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47038
DEVICE

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01

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TTS

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DES

-4_

I
375(953)
NOM.

NOTES:
All dimensions in inches (bold) and
millimeters (parantheses)
Pins are intended for insertion in hole rows
on .300" (7.620) centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal
your practice for .020 inch (O.50S)
diameter pin
Pins are alloy 42
Package weight is 0.9 gram
Package material is silicone

98

~~:~I:g

NOTES:
All dimensions in inches (bold) and
millimeters (parentheses)
Pins are alloy 42
Pins are intended for insertion in hole rows
on .300" (7.620) centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal
your practice for .020 inch (0.508)
diameter pin
"'The .0371.027 1.940/.686) dimension does
not apply to the corner pins
Package weight is 0.9 gram

'Fnmn·,6

(0381)

MAX

I 110

100(2540)-----\

--~-

II

i_I
150(381011

NOM

II

+-1

090

II *o~~
II 020(0508)
0271r-

--j i

(2794)
(2286)

-j

STANDOFF
WIDTH

16-Pin Plastic Dual In-Line

200 (5 080)

\

1010125)

310(787) .i02 0I51)
290(737)

200Ir:I~~ .. "t~

Plo"

(~~)

r

045 (114)

016(0406)

10.940)
(0.686)

STANDOFF
WIDTH

9-18

Olli2a)
009 (23)

PACKAGE OUTLINES
18-Pin Plastic Dual In-Line

9M

:::: ;:r'..
."0,2'.114)

I

24-Pin Plastic Dual In-Line

-----1

.045 (1.143) R
.035 (.BS9)

.560 (14 224)

.540113716)

I..

.083 (2.10Bf
.073 {1.854)

.200

(5080)

1.260 (32.004)

·r···DI~2--'2.0"'496)
~I

:\~{ !~ ~ ::~~ ..,
L j

9N

r

I

.890 (22.606)

13

2.

_I

.030 .085

~- .065
(1 651)
.045(1143}

I

-

L

.090 (2.286)

.065(1.651)

( 762)(2159)

.020 .076

~I··TYP

~"_"'-jic-5_)+!---l==-

.165 (4.191)

"'5'j'"~~?'~

1

. 149 13.784'ifor--=-.='r-1=-=-,=,..-,=rFr"""R-cl

''''''H

J
1', ,

"

.~- (2794)

,

~~)I !

!!

l~ ~i~~)I..J.l10l
(2~9~)

.060 (1.270

.'35 (3 429)
.115(2921)---j

I

__ It -~~~'l'G

I

~:090 ~.027(.686)-j~.016(.406)
110

(2.286)

:0161
(.406) (2.28S)

~I

.037 (.940)

.020 (.508)

STANDOFF

WIDTH

NOTES:
All dimensions in inches (bold) and
millimeters (parentheses)
Pins are intended for insertion in hole rows
on .600" (15.24) centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal
your practice for .020 inch (0.50S)
diameter pin
Pins are alloy 42

NOTES:
All dimensions in inches (bold) and
millimeters (parentheses)
Pins are intended for insertion in hole rows
on .300" (7.620) centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal
your practice for .020 inch (0.50S)
diameter pin
Pins are alloy 42

24-Pin Plastic Dual In-Line

9U
r - - - , . 2 0 0 (30.480)-----1

11\1\1\/

MAX.

H'\f\1\

I
NOTES:
All dimensions in inches (bold) and
millimeters (parentheses)
Pins are intended for insertion in hole rows
on .400" (10.16) centers
They are purposely shipped with "positive"
misalignment to facilitate insertion
Board-drilling dimensions should equal
your practice for .020 inch (0.50S)
diameter pin
Pins are alloy 42

.165 (4.191)
.145 (3.683)

t

r;;;:;:;:::;;::;;:::;;:;;;::;;;::::;;:;;:::;~

(O.508~

+=mtMMf~
~. -r :~~~NG

.135 (3.429) I
.115(2.921)-1

.110
(2.794)

.037 (.940)
.027(.686)

.090

STANDOFF

(2.286)

WIDTH

h'

II

.020

.020 (.508)

-11--. 016 (.406)

9-19

•

FAIRCHILD FIELD SALES OFFICES,
SALES REPRESENTATIVES AND
DISTRIBUTOR LOCATIONS

Fairchild
Semiconductor

Franchised
Distributors

United States and
Canada

Alabama
Hallmark ElectroniCs
4900 Bradford Drtve
Huntsville. Alabama 35807
Tel: 205-837-8700 TWX: 810-726-2187

Wyle Distribution Group
9525 Chesapeake
$an Diego. California 92123
Tel. 714-565-9171 TWX: 910-335-1590

Hamllton/Avnet ElectroniCS
6700 Interstate 85 Access Road, SUite lE
Norcross, Georgia 30071
Tel: 404-448-0800
Telex' None- use HAMAVLECB DAL 73-0511
(Regional Hq In Dallas, Texasl

Hamilton/Avnet Electronics
4692 Commercial Drive
HuntslIllIe. Alabama 35805
Tel: 205-837-7210
Telex None- use HAMAVLECB DAL 73-0511
(Regional Hq In Dallas, Texas)
Arizona
Hamllton/Avnet ElectroniCs
505 S. Madison Dnve
Tempe. Anzona 85281
Tel: 602-275-7851 TWX: 910-951-1535
Klerulff ElectrOnics
4134 East Wood Street
Phoenix. Arizona 85040
Tel: 602-243-4101
Wyle Distribution Group
8155 North 24th Ave
Phoenix, Arizona 85021
Tel: 602-249-2232 TWX' 910-951-4282
California
Avnet Electronics
350 McCormick Avenue
Costa Mesa. Cahfornia 92626
Tel: 714-754-6111 (Orange County)
213-558-2345 (Los Angeles)
TWX: 910-595-1928
Bell Industries
ElectroniC Distributor Division
1161 N. Fair Oaks Avenue
Sunnyvale. California 94086
Tel: 408-734-8570 TWX: 910-339-9378
Wyle Distribution Group
3000 Bowers Avenue
Santa Clara, Callforma 95051
Tel: 408-727-2500 TWX: 910-338-0541
Hamilton Electro Sales
3170 Pullman Avenue
Costa Mesa, California 92636
Tel: 714-979-6864
Hamilton Electro Sales
10912 W. Washington Blvd
Culver.City, California 90230
Tel: 213-558-2121 TWX: 910-340-6364
Hamllton/Avnet Electronics
1175 Bordeaux Drive
Sunnyvale, California 94086
Tel: 408-743-3355 TWX: 910-379-6486
Hamilton/Avnet Electronics
4545. Vlewridge Avenue
San Diego, California 92123
Tel: 714-571-7527
Telex: HAMAVELEC SOG 69-5415
Anthem Electronics
1020 Stewart Drive
P.O. Box 9085
Sunnyvale, California 94086
Tel: 408-738-1111
Anthem Electronics, Inc.
4040 Sorrento Valley Blvd
San Dr.ego, California 92121
Tel: 71.4-279-5200
Anthem Electronics, Inc.
2661 Dow Avenue
Tustin, California 926S0
Tel: 714-730-8000
Wyle Electronics
124 Maryland Street
~El SegundO, California 90245
Tel: 213-322-8100 TWX: 910-348-7111
Wyle Distributor Group
17872 Cowan Avenue
Irvine, California 92714
Tel: 714-641-1600
Tetex: 610-595-1572
"Serlech LaboratOries
2120 Main Street, Suite 190
Huntington Beach, California 92647
Tel: 714-960-1403

Colorado
Bell Industries
8155 West 48th Avenue
Wheatndge. Colorado 80033
Tel 303-424-1985 TWX. 910-938-0393

Arrow Electronics
2121 South Hudson
Denver. Colorado 80222
Tel: 303-758-2100
Wyle Dlstrlbullon Group
6777 E. 50th Avenue
Commerce City. Colorado 80022
Tel. 303-287-9611 TWX: 910-936-0770
Hamliton/Avnet Electronics
8765 E. Orchard Rd SUite 708
Englewood. Colorado 801 "
Tel 303-740-1000 TWX: 910-935-0787
Connecticut
Arrow Electronics, Inc.
t2 Beaumont Road
Walhngford, Connecticut 06492
Tel: 203-265-7741 TWX: 203-265-7741
Hamllton/Avnet ElectroniCS
Commerce Dnve. Commerce Park
Danbury. Connecticut 06810
Tel: 203-797·2800
TWX None - use 710-897-1405
IReglonal HQ. in MI Laurel. N.J)
Harvey Electronics
112 Main Street
Norwalk, Connecticut 06851
Tel: 203-853-1515
Schweber Electronics
Finance Drive
Commerce Industrial Park
Danbury, Connecticut 06810
Tel: 203-792-3500

Illinois
Hallmark Electron,cs. Inc
1177 Industrial Dnve
Bensenville. ltllnois 60106
Tel' 312-860-3800
Hamilton/Avnet Electronics
3901 N. 25th Avenue
Schiller Park. Illinois 60176
Tel: 312-678-6310 TWX: 910-227-0060
Kierulff Electronics
1536 Landmeler Aoad
Elk Groye Village. Illinois 60007
Tel. 312-640-0200 TWX: 910-227-3166
Schweber Electronics, Inc
1275 Brummel Avenue
Elk Grove Village, illinoIs 60007
Tel: 312-593-2740 TWX: 910-222-3453
Semiconductor SpeCialists, Inc.
(mailing address)
O'Hare International Airport
P.O. Box 66125
Chicago, Illinois 60666
(shipping address)
195 Spangler Avenue
Elmhurst Industrial Park
Elmhurst, Illinois 60126
Tel: 312-279-1000 TWX: 910-254-0169
Indiana
Graham Electronics Supply, Inc.
133 S. Pennsylvama St.
IndianapoliS, Indiana 46204
Tel: 317-634-8486 TWX: 810-341-3481
Pioneer Indiana ElectroniCS, Inc
6408 Castle Place Drive
IndianapoliS, Indiana 46250
Tel: 317-849-7300 TWX: 810-260-1794

Florida
Arrow Electronics
1001 Northwest 62nd Street
Suite 402
Ft. Lauderdale, Florida 33309
Tel: 305-776-7790

Kansas
Hallmark Electronics, Inc.
11870 W. 91 sl Street
Shawnee MiSSion, Kansas 66214
Tel: 913-888-4746

Arrow Electronics
115 Palm Bay Road N.W
SUite 10 Bldg. #200
Palm Bay, Florida 32905
Tel: 305-725-1408

Hamilton/Avnet Electronics
9219 GUlvira Road
Overland Park, Kansas 66215
Tel: 913-888-8900
Telex: None - use HAMAVLECB DAL 73-0511
(Regional HQ. 10 Dallas, Texas)

Hallmark Electronics
1671 W. McNab Road
Ft. Lauderdale, Florida 33309
Tel: 305-971-9280 TWX: 510-956-3092
Hallmark Electronics
7233 Lake Ellenor Drive
Orlando, FlOrida 32809
Tel: 305-855-4020 TWX: 810-850-0183
Hamilton/Avnet Electronics
6800 NW. 20th Avenue
Ft. Lauderdale, FlOrida 33309
Tel: 305-971-2900 TWX: 510-954-9808
Hamllton/Avnet Electronics
3197 Tech Drive, North
SI. Petersburg, FlOrida 33702
Tel: 813-576-3930

Louisiana
Sterling Electronics Corp.
4613 Fairfield
Metairie, LOUisiana 70002
Tel: 504-887-7610
Telex: STERLE LEC MRIE 58-328
Maryland
Hallmark Electronics, Inc
6655 Amberton Drive
Baltimore, Maryland 21227
Tel: 301-796-9300
Hamilton/Avnet Electronics
(mailing addressl
Friendship International Airport
P.D Box 8647
Baltimore, Maryland 21240

Schweber Electronics
2830 North 28th Terrace
Hollywood, Flonda 33020
Tel: 305-927-0511 TWX: 510-954-0304

(shipping address)
7235 Standard Drive
Hanover. Maryland 21076
Tel: 301-796-5000 TWX: 710-862-1861
Telex: HAMAVLECA HNVE 87-968

Georgia
Arrow Electronics
2979 Pacific Dflve
Norcross, Georgia 30071
Tet: 404-449-8252
Telex: 810-766-0439

Pioneer Washington Electronics, Inc.
9100 GaIther Road
Gaithersburg, Maryland 20760
Tel: 301-948-0710 TWX: 710-828-9784

"ThiS distributor carries Fairchild die products only.

10-3

Schweber Electronics
9218 Gaither Road
Gaithersburg, Maryland 20760
Tel: 301-840-5900 TWX: 710-828-0536

II

Fairchild
Semiconductor

Franchised
Distributors

United States and
Canada

Massachusetts
Arrow Electronics. Inc
960 Commerce Way
Woburn, Massachusetts 01801
Tel: 617-933-8130 TWX. 710-393-6770

New Jersey
Hallmark ElectroniCS Inc
Springdale Business Center
2091 Springdale Road
Cherry Hili New Jersey 08003
Tel 609-424-0880

Harvey Electronics
rmallmg address'
P
Box 1208
Bmghampton New York 13902
IShlPPlng address'
1911 Vestal Parkway East
Vestal New York 13850
Tel 607-748-8211

Arrow ElectroniCS

85 Wells Avenue
Newton Centre, Massachusetts 02159
Tel. 617-964-4000

Harnllton/Avnet Electronics
10 Industrial Road
Fairfield, New Jersey 07006

Tel: 201-575-3390 TWX 710-994-5787
Gerber Electronics
128 Carnegie Row
Norwood, Massachusetts 02026
Tel: 617-329-2400
Hamifton/Avnet ElectroniCS
50 Tower .Offlce Park
Woburn, Massachusetts 01801
Te!: 617-273-7500 TWX: 710-393-0382
Harvey Electronics
44 Hartwell Avenue
lexington, Massachusetts 02173
Tel: 617-861-9200 TWX: 710-326-6617
Schweber Electronics
25 Wiggins Avenu~
Bedford, Massachusetts 01730
Tel: 617-275-5100
··Serlech LaboratOries
1 PeabOdy Street
Salem, Massachusetts 01970
Tel. 617-745-2450
Michigan
Hamllton/Avnet ElectroniCS
32487 Schoolcraft
livonia, Michigan 48150
Tel: 313-522-4700 TWX: 810-242-8775

Pioneer/Detroit
13485 Stamford
Livonia, Michigan 48150
Tel: 313-525-1800
R-M Electronics
4310 Roger B. Chaffee
Wyoming, Michigan 49508
Tel: 616-531-9300
Schweber ElectrOniCS
33540·SchOolcraft
LiYonia, Michigan 48150
Tel: 313-525-8100
Arrow ElectroniCS
3921 Varsity Drive
Ann Arbor, Michigan 48104
Tel: 313-971-8220
Minnesota
Arrow Electronics
5230 West 73rd Street
Edina, Minnesota 55435
Tel: 612-830-1800

Hamilton/Avnet Electronics
7449 Cahill Road
Edina, Minnesota 55435
Tel: 612-941-3801
TWX: None-use 910-227-0060
(Regional Hq. in Chicago, IIU
Schweber Electronics
7402 Washington Ayenue S
Eden Prairie, Minnesota 55344
Tel: 612-941-5280
Missouri
Hallmark Electronics, Inc.
13789 Rider Trail
Earth City, Missouri 63045
Tel: 314-291-5350

Hamilton/Avnet Electronics
13743 Shoreline Ct., East
Earth City, Missouri 63045
Tel: 314-344-1200 TWX: 910-762-0684

'Minority Distnbutor

Hamllton/Avnet Electronics
#1 Keystone Avenue
Cherry HIli, New Jersey 08003
Tel. 609-424-0100 TWX: 710-940-0262
Schweber Electronics
18 Madison Road
Fairfield, New Jersey 07006
Tel: 201-227-7880 TWX: 710-480-4733
Sterling ElectroniCS
774 Pfeiffer Blvd
Perth Amboy, N.J. 08861
Tel' 201-442-8000 Telex' 138-679
Wilshire Electronics
102 G8IIher Drive
MI. laurel, N.J. 08057
Tel: 215-627-1920
Wilshire Electronics
1111 Paulison Avenue
Clifton, N.J. 07015
Tel: 201-365-2600 TWX' 710-989-7052
New Mexico
Bell Industries
11728 Linn Avenue N.E
Albuquerque, New MexIco 87123
Tel: 505-292-2700 TWX: 910-989-0625

Hamilton/A'-met Electronics
2450 Byalor DrIVe S.E
Albuquerque, New MexIco 87119
Tel: 505-765-1500
TWX: None - use 910-379-6486
(Regional Hq. in Mt. View, Ca.l

a

Rochester RadiO Supply Co Inc
140 W Mam Street
IP O. Box 19711 Rochester New York 14603
Tel 716-454-7800
Schweber ElectroniCS
Jericho Turnpike
Westbury, l ! New York 11590
Tel 516-334-7474 TWX 510-222-3660
Jaco ElectroniCS, Inc
145 Oser Avenue
Hauppauge. II New York 11787
Tel. 516-273-1234 TWX. 510-227-6232
Summit Distributors, Inc
916 Main Street
Buffalo. New York 14202
Tel 716-884-3450 TWX 710-522-1692
North Carolina
Arrow ElectroniCs
938 Burke Street
Winston Salem, North Carolma 27102
Tel' 919-725-8711 TWX 510-922-4765

Hamllton/Avnet
2803 Industflal Oflve
Raleigh. North Carolina 27609
Tel. 919-829-8030
Hallmark ElectroniCS
1208 Front Street, Bldg. K
Raleigh, North Carolina 27609
Tel' 919-823-4465 TWX' 510-928-1831
Resco
Highway 70 West
Rural Route 8, P.O Box 116-B
Raleigh, North Carolma 27612
Tel: 919-781-5700

New York
Arrow Electronics
900 Broadhollow Road
Farmingdale, New York 11735
Tel: 516-694-6800

Pioneer/Carolina ElectroniCs
103 Industrial Drive
Greensboro, North Carohna 27406
Tel. 919-273-4441

Arrow ElectroniCS
20 Oser Avenue
Ha,J~pauge, New York 11787
Tel: 516-231-1000

Ohio
Arrow ElectroniCs
7620 McEwen Road
Centerville. Ohio 45459
Tel. 513-435-5563

'Cadence Electronics
40-17 Oser Avenue
Hauppauge, New York 11787
Tel: 516-231-6722
Arrow Electronics
P.O. Box 370
7705 Maltlage Drive
LiYerpool, New York 13088
Tel: 315-652-1000
TWX: 710-545-0230
Components Plus, Inc.
40 Oser Avenue
Hauppauge, U., New York 11767
Tel: 516-231-9200 TWX: 510-227-9869
Hamllton/Avnet Electronics
167 Clay Road
Rochester, New York 14623
Tel: 716-442-7820
TWX: None- use 710-332-1201
(Regional Hq. in Burlington, MaJ
Hamilton/Avnet ElectronIcs
16 Corporate Circle
E. Syracuse, New York 13057
Tel: 315-437-2642 TWX: 710-541-0959
Hamilton/Avne! Electronics
5 Hub Drive
Melville, New York 11746
Tel: 516-454-6000 TWX: 510-224-6166

--This distributor carries Fairchild die products only.

10-4

Hamilton/Avnet Electronics
4588 Emery Industrial Parkway
Cleveland, Ohio 44128
Tel' 216-831-3500
TWX: None - use 910-227-0060
!Regional Hq. in Chicago, 111.1
Hamllton/Avnet ElectronIcs
954 Senate Drwe
Dayton, Ohio 45459
Tel: 513-433-0610 TWX: 810-450-2531
PIoneer/Cleveland
4800 E. 131st Street
Cleveland, OhIo 44105
Tel: 216-587-3600
Pioneer/Dayton
1900 Troy Street
Dayton. Ohio 45404
Tel 513-236-9900 TWX 810-459-1622
Schweber Electronics
23880 Commerce Park Road
Beachwood, Ohio 44122
Tel: 216-464-2970 TWX: 810-427-9441
Arrow Electronics
6238 Cochran Road
Solon, Ohio 44139
Tel: 216-248-3990 TWX: 810-427-9409

Fairchild
Semiconductor

Franchised
Distributors

United States and
Canada

Ohio

Hamllton/Avnet Electronics
3939 Ann Arbor
Houston, Texas 77042
Tel: 713-780-1771
Telex: HAMAVLECB HOU 76-2589

Cam Gard Supply Ltd.
15 Mount Royal Blvd.
Mpncton. New BrunSWIck, E1C 8N6, Canada
Tel: 506-855-2200

Arrow Electronics
(mailing address)
P,O. Box 37826
Cincinnati, Ohio 45222
(shipping addressl
10 Knollcrest Drive
Reading. Ohio 45237
Tel: 513.;.76'~5432 TWX: 810-461-2670

HaUmark Electronics
6969 Worthington-Galena Road
Worthington. Ohio 43085

Oklahoma

Schweber Electronics, Inc
14177 Proton Road
Dallas, Texas 75240
Tel: 214-661-5010 TWX: 910-860-5493
Schweber Electronics, Inc
7420 Harwin Drive
Houston, Texas 77036
Tel: 713-784-3600 TWX: 910-881-1109

Hallmark Electronics

5460 S. 103rd East Avenue
Tulsa, Oklahoma 74145
Tel: 918-835-8458 TWX: 910-845-2290
Radio Inc. Industrial Electronics
1000 S. Main
Tulsa, OklahOma 74119
Tel: 918~587~9'23

Pennsylvania
Pioneer/Delaware Valley Electronics
261 Gibraltar Road
Horsham, Pennsylvania 19044
Tel: 215-674-4000 TWX: 510-665-6778
Pioneer Electronics, Inc.
560 Alpha Drive
Pittsburgh, Pennsylvania 15238
Tel: 412-782-2300 TWX: 710-795-3122
Schweber Electronics
101 Rock Road
Horsham, Pennsylvania 19044
Tel: 215-441-0600
Arrow Electronics
4297 Greensburgh Pike
Suite 3114
Pittsburgh, Pennsylvania 15221
Tel: 412-351-4000

South Carolina
Dixie Electronics, Inc.
P.O. Box 408 (Zip Code 29202)
1900 Barnwell Street
Columbia, South Carolina 29201
Tel: 803-779-5332

T ....
Allied Electronics
401 E. 8th Street
Fort Worth, Texas 76102
Tel: 817-336-5401
Arrow Electronics
13715 Gamma Road
Dallas, Texas 75234
Tet: 2~4-386-75oo TWX: 910-860-5377
Hallmark Electronics Corp.
10109 McKalla Place Suite F
Austin, Texas 78758
Tel: 512-837-2814
Hallmark Electronics
11333 Pagemill Drive
Dallas, Texas 75243
Tel: 214-234-7300 TWX: 910-867-4721
Hallmark Electronics, Inc.
8000 Westglen
Houston, Texas 77063
Tel: 713~781-6100
Hamilton/Avnet Electronics
10508A Boyer Boulevard
Austin, Texas 78758
Tel: 512-837-8911
Hamilton/Avnet Electronics
4445 Sigma Road
Dallas, Texas 75240
Tel: 214-661-8661
Telex: HAMAVLECB DAL 73-0511

Sterling Electronics
4201 Southwest Freeway
Houston, Texas 77027
Tel: 713~627~9800 TWX: 901~881~5042
Telex: STELECO HOUA 77~5299

Utah
Century Electronics
3639 W. 2150 South
Salt lake City, Utah 84120
Tel: 801-972-6969 TWX: 910-925-5686
Hamilton/Avnet Electronics
1585 W. 2100 South
Salt Lake City, Utah 84119
Tel: 801-972-2800
TWX: None ~ use 910-379-6486
(Regional Hq. in Mt. View, CaJ
Washington
Hamilton/Avnet Electronics
14212 N.E. 21st Street
Bellevue, Washington 98005
Tel: 206-746-8750 TWX: 910-443-2449
Wyle Distribution Group
1750 132nd Avenue N.E.
Bellevue, Washington 98005
Tel: 206-453-8300 TWX: 910-444-1379
Radar Electronic Co., Inc
168 Western Avenue W.
Seattle, Washington 98119
Tel: 206-282-2511 TWX: 910-444-2052

Wisconsin
HamiltonlAvnet Electronics
2975 Moorland Road
New Berlin, Wisconsin 53151
Tel: 414-784-4510 TWX: 910-262-1182
Marsh Electronics, Inc.
1563 South 100th Street
Milwaukee, Wisconsin 53214
Tel: 414-475-6000 TWX: 910-262-3321

Canada
Cam Gard Supply ltd.
640 42nd Avenue S.E.
Calgary, Alberta, T2G W6, Canada
Tel: 403-287-0520 Telex: 03-822811
Cam Gard Supply ltd.
16236 116th Avenue
Edmonton, Alberta T5M 3V4, Canada
Tel: 403-453-6691 Telex: 03-72960
Cam Gard Supply Ltd.
4910 52nd Street
Red Deer, Alberta, T4N 2C8, Canada
Tel: 403-346-2088
Cam Gard Supply Ltd.
825 Notre Dame Drive
Kamloops, British Columbia, V2C 5N8, Canada
Tel: 604-372~3338
Cam Gard Supply Ltd.
1777 Ellice Avenue
Winnepeg, Manitoba, R3H OW5, Canada
Tel: 204-786-8401 Telex: 07-57622
Cam Gard Supply Ltd.
Rookwood Avenue
Fredericton, New Brunswick, E3B 4Y9, Canada
TeJ: 506-455-8891

10-5

Cam Gard Supply Ltd.
3065 Robie Street
Halifax, Nova Scotia, B3K 4P6. Canada
Tel: 902-454-8581 Telex: 01-921528
Cam Gard Supply Ltd.
1303 Scarth Street
Regina, Saskatchewan, S4R 2E7, Canada
Tel: 306-525-1317 Telex: 07-12667
Cam Gard Supply Ltd
1501 Ontario Avenue
Saskatoon. Saskatchewan, S7K 1S7, Canada
Tel: 306-652-6424 Telex: 07-42825
Electro Sonic Industrial Salas
(Torontol Ltd.
1100 Gordon Baker Rd.
W(lIowdale, Ontario, M2H 3B3, Canada
Tel: 416-494-1666
Telex: ESSCO TOR 06-22030
Future Electronics Inc.
Baxter Center
1050 Baxter Road
Ottawa, Ontario, K2C 3P2, Canada
Tel: 613-82Q-.9471
Future Electronics Inc
4800 Dufferin Street
Downsview, Ontario. M3H 5S8, Canada
Tel: 416-663-5563
Future Electronics Corporation
5647 Ferrier Street
Montreal, Quebec, H4P 2K5, Canada
Tel: 514-731-7441
Hamilton/Avnet International
(Canada) Ltd.
3688 Nashua Drive, Units 6 & H
Mississauga, Ontario, l4V lM5, Canada
Tel: 416-677-7432 TWX: 610-492-8867
Hamilton/Avnet International
(Canada) Ltd.
1735 Courtwood Crescent
Ottawa, Ontario, K1 Z 5L9, Canada
Tel: 613-226-1700
Hamilton/Avnet International
ICanada) Ltd
2670 Sabourin Street
SI. Laurent, Quebeo, .H4S 1M2, Canada
Tel: 514-331-6443 TWX: 610-421-3731
R.A.E. Industrial Electronics, Ltd.
3455 Gardner Court
Burnaby, British Columbia Z5G 4J7
Tel: 604-291-8866 TWX: 610-929-3065
Telex: RAE-VCR 04-54550
Semad Electronics Ltd.
620 Meloche Avenue
Dorval, Quebec, H9P 2P4, Canada
Tel: 604-2998-866 TWX: 610-422-3048
Semad Electronics Ltd
105 Brisbane Avenue
Downsview, OntariO, M3J 2K6, Canada
Tel: 416-663-5670 TWX: 610-492-2510
Semad Electronics Ltd.
1485 Laperriere Avenue
Ottawa, Ontario, K1Z 7S8, Canada
Tel: 613-722-6571 TWX: 610-562-8966

II

Fairchild
Semiconductor

Sales
Representatives

United States and
Canada

Alabama
Cartwright & Bean, Inc.
2400 Bob Wallace Ave" Suite 201
Huntsville, Alabama 35805
Tel" 205~533-3509

Nevada

Texas
Technical Marketing
3320 Wiley Post Road
Carrollton, Texas 75006
Tel: 214-387-3601 TWX: 910-860-5158

California
Celtee Company
1a009 Sky Park Circle Suite B
Irvine, California 92705
Tel: 714-557-5021 TWX: 910-595-2512

New Jersey
BGR AssocIates
3001 Greentree Executive Campus
Marlton, New Jersey 08053
Tel: 609-428-2440

Technical Marketing, Inc.
9027 North Gate Blvd
Suite 140
Austin, Texas 78758

Celtee Company
7867 Convoy Court, Suite 312
San Diego, California 92111
Tel: 714-279-7961 TWX: 910-335-1512

Lorac Sales, Inc.
1200 Route 23 North
Butler, New Jersey 07405
Tel: 201-492-1050 TWX: 710-988-5846

Technical Marketing
6430 Hillcrofl, Suite 104
Houston, Texas 77036
Tel' 713-777-9228

Magna Sales, Inc.
3333 Bowers Avenue
Suite 295
Santa Clara, California 95051
Tel: 408-727-8753 TWX: 910-338-0241

New York
Lorac Sales, Inc.
550 Old Country Road, Room 410
Hicksville, New York 11801
Tel: 516-681-8746 TWX: 510-224-6480

Utah
Simpson Associates, Inc.
7324 South 1300 East, Suite 350
Midvale, Utah 84047
Tel: 801-566-3691
TWX: 910-925-4031

Colorado
Simpson Associates, Inc
2552 Ridge Road
Littleton, Colorado 80120
Tel: 303-794-8381 TWX: 910-935-0719

Tri-Tech Electronics, Inc.
3215 E. Main Street
Endwell, New York 13760
Tel: 807-754-1094 TWX: 510-252-0891

Connectlcul
Phoenix Sales Company
389 Main Street
Ridgefield, Connecticut 06877
TeJ: 203-438-9644 TWX. 710-467-0662
Florida
Lectromech, Inc
399 Whooping Loop
Altamonte Springs, Florida 32701
Tel: 305-831-1577 TWX: 510-959-6063

Lectromech, Inc.
2280 U.S. Highway 19 North
Suite 155, Building K
Clearwater, Florida 33515
Tel: 813-797-1212
TWX: 510-959-6030
Lectromech, Inc.
17 East Hibiscus Blvd.
Suite A-2
Melbourne, Florida 32901
Tel: 305-725-1950
TWX: 510-959-6063
Lectromech, Inc.
1350 S. Powerline Road, Suite 104
Pompano Beach, Florida 33060
Tel: 305-974-6780 TWX: 510-954-9793
Georgia
Cartwright & Bean, Inc
P.O. Box 52846 (Zip Code 303551
3198 Cain's Hill Place, N.w.
Atlanta, Georgia 30305
Tel: 404-233-2939 TWX: 810-751-3220
illinois
Micro Sales, Inc.
2258-8 Landmeir Road
Elk Grove Village, Illinois 60007
Tel: 312-956-1000 TWX: 910-222-1833
Maryland
Delta HI ASSOCIates
1000 Century Plaza Suite 224
Columbia, Maryland 21044
Tel: 301-730-4700 TWX: 710-826-9654
Massachusetts
Spectrum ASSOCiates, Inc.
109 Highland Avenue
Needham, Massachusetts 02192
Tel: 617-444~8600 TWX: 710-325-6665
Minnesota
PSI Company
5315 W. 74th Street
Edina, Minnesota 55435
Tel: 612-835-1777 TWX: 910-576-3483
Mississippi
Cartwright & Bean, Inc.
P.O. Box 16728
5150 Keele Street
Jackson, Mississippi 39206
Tel: 601-981-1368
Twx: 810-751-3220

Magna Sales
4560 Wagon Wheel Road
Carson City, Nevada 89701
Tel: 702-883-1471

Tri-Tech Electronics, Ino.
590 Perinton Hills Office Park
Fairport, New York 14450
Tel' 716-223-5720
TWX: 510-253-6356
Tri-Tech Electronics, Inc.
6836 E. Genesee Street
Fayetteville, New York 13066
Tel: 315-446-2881 TWX' 710-541-0604
Tri- Tech Electronics, Inc
19 Davis Avenue
Poughkeepsie, New York 12603
Tel: 914-473-3880
TWX: 510-253-6356
North Carolina
Cartwright & Sean, Inc
1165 Commercial Ave.
Charlotte, North Carolina 28205
Tel: 704-377-5673

Cartwright & Bean, Inc.
P.O. Box 18465
3948 Browning Place
Raleigh, North CarOlina 27619
Tel: 919-781-6560
Ohio
The Lyons Corporation
4812 Frederick Road, Suite 101
Dayton, Ohio 45414
Tel: 513-278-0714
TWX: 810-459-1803

The lyons Corporation
6151 Wilson Mills Road, Suite 101
Highland Heights, Ohio 44143
Tel: 216-461-8288
TWX: 810-459-1803
Oklahoma
Technical Marketing
9717 E. 42nd Street, Suite 221
Tulsa, Oklahoma 74145
Tel: 918-622-5984
Oregon
Magna Sales, Inc.
8285 S.W. Nimbus Ave., Suite 138
Beaverton, Oregon 97005
Tel: 503-641-7045
TWX: 910-467-8742
Tennessee
Cartwright & Bean, Inc.
P.O. Box 4760
560 S. Cooper Street
Memphis, Tennessee 38104
Tel: 901-276-4442
TWX: 810-751-3220

Cartwright & Bean, Inc.
8705 Unicorn Drive
Suite B120
Knoxville, Tennessee 37923
Tel: 615-693-7450
TWX: 810-751-3220

10-6

Tel: 512-835-0064

Washington
Magna Sales, Inc.
Benaroya Business Park
Building 3, Suite 115
300-12Oth Avenue, N.E.
Bellevue, Washington 98004
Tel: 206-455-3190
Wisconsin
Larsen Associates
10855 West Potter Road
Wauwatosa, Wisconsin 53226
Tel: 414-258-0529 TWX: 910-262-3160
Canada
R.N. Longman Sales, Inc. (L.S.U
1715 Meyerside Drive
Suite 1
Mississauga, Ontario, L5T 1 C5 Canada
Tel: 416-677-8100 TWX: 610-492-8976

R.N. Longman Sales, Inc. (L.S.U
16891 Hymus Blvd.
Kirkland, Quebec
H9H 3L4 Canada
Tel: 514-694-3911
TWX: 610-422-3028

Fairchild
Semiconductor

Sales
Offices

Alabama
Hunts.... ille Office
500 Wynn Drive
Suite 511
Huntsville, Alabama 35805
Tel: 205-837-8960

Minnesota

Arizona
Phoenix Office
4414 N. 19th Avenue, Suite G
Phoenix 85015
Tel: 602-264-4948 TWX: 910-951-1544

C.llfornl.
Los Angeles Office"
Crocker Bank Bldg.
15760 Ventura Blvd., Suite 1027
Encino 91436
Tel: 213-990-9800 TWX: 910-495-1776

United States and
Canada

MinneapOlis Office"

4570 West 77th Street Room 356
Minneapolis 55435

Tel 612-835-3322 TWX' 910-576-2944

New Jer.ey
Wayne Office"
560 Valley Road. Suite 1
Wayne 07490
Tel: 201-696-7070 TWX: 710-988-5(J46

New Mexico
Alburquerque Office
North Building
2900 Louisiana N.E. South G2
Alburquerque 87110
Tel: 505-884-5601 TWX: 910-379-6435

New York
Santa Ana Office'
1570 Brookhollow Drive
Suite 206
Santa Ana 92705
Tel: 714-557-7350 TWX: 910-595-1109
Santa Clara Office'
3333 Bowers Avenue, Suite 299
Santa Clara 95051
Tel: 408-987-9530 TWX: 910-338-0241

Florida
Ft. Lauderdale Office
Executive Plaza, Suite 300-B
1001 Northwest 62nd Street
FI. Lauderdale 33309
Tet: 305-771-0320 TWX: 510-955-4098
Orlando Office·
Crane's Roost Office Park
399 Whooping Loop
Altamonte Springs 32701
Tel: 305-834-7000 TWX: 810-850-0152

IIlInol.
Chicago Office
60 Gould Center
The East Tower, Suite 710
Rolling Meadows 60008
Tel: 312-640-1000

Indiana
Ft. Wayne Office
2118 Inwood Drive. Suite 111
Ft. Wayne 46815
Tel: 219-483-6453 TWX: 810-332-1507
Indianapolis Office
7202 N. Shadeland Castle Point
Room 205
Indianapolis 46250
Tel: 317-849-5412 TWX: 810-260-1793

Kan...
Kansas City Office
8609 West 110th Street, Suite 209
Overland Park 66210
Tel: 913-649-3974

Maryland
Columbia Office·
1000 Century Plaza, Suite 225
Columbia 21044
Tel: 301-730-1510 TWX: 710-826-9654

Melville Office
275 Broadhollow Road, Suite 219
Melville 11747
Tel: 516-293-2900 TWX: 510-224-6480
Poughkeepsie Office
19 Davis Avenue
Poughkeepsie 12603
Tel: 914-473-5730 'TWX: 510-248-0030
Fairport Office
260 Perinton Hills Office Park
Fai rport 14450
Tel: 716-223-7700
North Carolina
Raleigh Office
3301 Executive Drive, Suite 204
Raleigh 27609
Tel: 919-876-0096

Ohio
Dayton Office
4812 Frederick Road, Suite 105
Dayton 45414
Tel: 513-278-8278 TWX: 810-459-1803

Oregon
Fairchild Semiconductor
8285 SW. Nimbus Avenue, Suite 138
Beaverton. Oregon 97005
Tel: 503-641-7871 TWX: 910-467-7842

Penn.ylvanla
Philadelphia Office·
2500 Office Center
2500 Maryland Road
Willow Grove 19090
Tel: 215-657-2711

Tex ..
Austin Office
9027 North Gate Blvd., SUite 124
Austin 78758
Tel: 512-837-8931
Dallas Office
13771 N. Central Expressway, Suite 809
Dallas 75243 •
Tel: 214-234-3391 TWX: 910-867-4757
Houston Office
6430 Hillcroft, Suite 102
Houston 77081
Tel: 713-771-3547 TWX: 910-881-8278

M....chu.etts
Boston Office·
888 Worcester Street
Wellesley Hills 02181
Tel: 617-237-3400 TWX: 710-348-0424

Michigan

Canada
Toronto Regional Office
Fairchild Semiconductor
1590 Matheson Blvd., Unit 26
Mississauga, Ontario L4W lJ1, Canada
Tel: 416-625-7070 TWX: 610-492-4311

Detroit Office·
21999 Farmington Road
Farmington Hills 48024
Tel: 313-478-7400 TWX: 810-242-2973

·Field Application Engineer

10-7

II

Fairchild
Semiconductor

Sales
Offices

Australia
Fairchild Australia Ply Ltd
Branch Office Third Floor
F,A.1. insurance Building
619 Pacific Highway
St. Leonards 2065
New South Wales, Australia
Tel: (02)-439-5911
Telex: AA2D053

Mexico
Fairchild Mexlcana S,A
Blvd. Adolofo Lopez Maleos No 163
MexIco 19, D,F
Tel: 905-563-5411 Telex 017-71-038

Austria and Eastern Europe
Fairchild Electronics

International

Scandinavia
Fairchild Semiconductor AS
Svartengsgatan 6
$-11620 Stockholm
Sweden
Tel: 8-449255 Telex 17759

A-10l0 Wien
Schwedenplatz 2

Tel: 0222 635821 Telex: 75096
Benelux
Fairchild Semiconductor
Paradijslaan 39
Eindhoven, Holland
Tel: 00-31-40-446909 Telex: 00-1451024
Brazil
J'=airchild Semicondutores Uda
Caixa Postal 30407
Rua Alagoas, 663
01242 Sao Paulo, Brazil
Tel: 66 9092 Telex: 011-23831
Cable: FAIRLEC
A

France
Fairchild Camera & Instrument S.A
121, Avenue d'italie
75013 Paris, France
Tet: 331-584-55 66
Telex: 0042 200614 or 260937
Germany
Fairchild Camera and Instrument !Deutschland)
Oaimlerstr 15
8046 Garching Hochbruck
Munich, Germany
Tel: (89) 320031 Telex: 52 4831 fair d
Fairchild Camera and Instrument
!Deutschland) GmBH
Oeltzenstrasse 15
3000 Hannover
W. Germany
Tel: 0511 17844 Telex: 09 22922

Singapore
Fairchild Semiconductor Ply Ltd
No. 11, Lorang 3
Toa payOh
Singapore 12
Tel: 531-066 Telex: FAIRSIN-RS 21376
Taiwan
Fairchild Semiconductor (Taiwan) Ltd
Hsietsu Bldg., Room 502
47 Chung Shan North Road
Sec. 3 Taipei, Taiwan
Tel: 573205 thru 573207
United Kingdom
Fairchild Camera and Instrument (UK) Ltd.
Semiconductor Division
230 High Street
Potters Bar
Hertfordshire EN6 5BU
England
Tel: 0707 51111 Telex: 262835
Fairchild Semiconductor Ltd
17 Victoria Street
Craigshill
Livingston
West Lothian, Scotland - EH54 SBG
Tel: Livingston 0506 :32891 Telex: 72629
GEC-Fairchild Ltd
Chester High Road
Neston
South Wirral L64 3UE
Cheshire. England
Tel: 051-336-3975 Telex. 629701

Fairchild Camera and Instrument !Deutschland)
Postrstrasse 37
7251 Leonberg
W. Germany
Tel: 07152 41026 Telex: 07 245711
Hong Kong
Fairchild Semiconductor (HKl Ltd
135 Hoi Bun Road
Kwun Tong
Kowloon, Hong Kong
Tet: K·89Q271 Telex: HKG·531
Italy
Fairchild Semiconduttori, S.PA
Via Flamenia Vecchia 653
00191 Roma, Italy
Tel: 06 327 4006 Telex: 63046 (FAIR ROM)
~airchiJd Semiconduttori S.P.A.
Via Aosellini, 12
20124 Milano, Italy
Tel: 02
74 51 Telex: 36522

a aa

Japan
Fairchild Japan Corporation
Pola Bldg.
1-15-21, Shibuya
Shibuya-Ku, Tokyo 150
Japan
Tel: 03 400 8361 Telex: 242173
Fairchild Japan Corporation
Yotsubashi Chuo Bldg.
'·4-26, Shin machi,
Nishi-Ku, Osaka 550, Japan
Tel: 06-541-6138/9
Korea
Fairchild Semikor Ltd
K2 219-6 Gad 80ng Dong
Young Dung Po-Ku
Seoul 15D-06, 'Korea
Tel: 85-0067 Telex: FAtRKOR 22705
(mai.ling address)
Central P.O. Box 2806

10-8



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