1977_NEC_Microcomputer_Catalog 1977 NEC Microcomputer Catalog

User Manual: 1977_NEC_Microcomputer_Catalog

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CATALOG

CONTENTS
1. Numerical Index

2.
3.
4.
5.
6.

7.
8.
9.
10.

Memories
Index
Selection Guide
Alternate Source Guide

II

EI

Random Access Memories (RAMs)
Dynamic
Static
Read Only Memories (ROMs)
Electrically Eraseable (EEPROMs)
Field Programmable (PROMs)
Mask Programmable (ROMs)
ROM Ordering Information
New Memory Products
RAMs
EPROMs

•

Microcomputers
Index
Selection Guide
Alternate Source Guide
t-tCOM-4 Microcomputers
t-tCOM-8 Microcomputers
Processors
Peripherals
New Products

••

•

New Microcomputer Families
Reference Section
Representatives and Distributors
t-tCOM-8 Microcomputer Program Card
Process Flow Chart

I

NUMERICAL INDEX
PRODUCT

PAGE

tAPD371 ....••••••.•..•.•.••.•..•.•••.•. 17!i
J.!PD372 •••.•••.••..•••.•.•..••.•..• : ..• 182

tAPD379 •..•.•..•.••.•.•••••.••••••....• 189
J.!PB403 •..•.•••••..••.•••••••.•••.•••.• 96
J.!PB405 ..•.••••••.•.•. '.' .••••.••.••••••• 100
J.!PB406 .••••••••••.•...••.••••.•••••••• 104
~B408 •..••.••.•••.•••••••••••.••••••. 126
J.!PD410 ••.••.••••.•••..•.••.•••.••••••. 54

tAPD411 •.•..•...••.••.•••••••••..•.•••.

9

J.!PD411A •••••••••••••••.•.••.•••• , ••••. 16
J.!PD411-M .••..•.•.••.••••••••••••.•.•.•. 24

tAPD414 ..••••.••..•••••.••.••.•.•.•.••.. 29
J.!PD414A .•.••• " .•...••.•••••.•....•.•• 123

tAPD416 .••••••..•.••.•••.•..•.••••..•.• 37
J.!PD418
J.!PB425
J.!PB426
J.!PB427
J.!PB428
J.!PD454

.•••..•.••.•..••••••••••.•••••.•• 40
•.•..••.••••••••••..•.••.•.••••• 100
..•...•.••.•.•.•••••.•••••.••••• 104
•.••••.•.•.•••••••••.••.•••••••• 126
••••..••.••.••.••.•••••.•••.•••• 126
••••••••••••••.••.•.•••••••••••• 82
tAPD458 •••••.••.•.•••••••.•..•••••••••• 88
tAPD464 •..••.•••••.•.•.••••••.••.•••..• 108
tAPD546 •••••.••.••..••••.•••.•••••••••• 133

tAPD547 .••.••.•..•••••••..•••••••••.••. 134
J.!PD548 ••.••••••.•.•••.••••.•••••.•.••• 133
J.!PD55O •.••••.••.••.•.•••••••.•••••••••134
tAPD555 ..•.••.••.•••.••..••.•••.•••.•••• 136
J.!PD556 ..••••.•••••..••.•••• ; .••••••••• 136
J.!PD758 ..•..••.•.•..•••••..••..••..•• ~ .196
J.!PD764 ..••••.••.•.•..•.••••••.••..•••.200
tAPD2101AL •.•••••••••.••.•.•....•••.••• 58
J.!PD:2102AL .•••••.•.•••••.••.•••••....•. 63
tAPD2111AL ••.•..•••••• , ..••.••••••• , .•• 67
J.!PD2114 .••••••••••••••.••••••.•.••.•.. 124
J.!PB2205 ............................... 52
J.!PD2308 •••..•••••••••.•••.•.•••••••••• 112
tAPD2316A .•..••••• , ., •. " •••••••• '.' •••• 115
tAPD2316E •••••••••••••.•••.•••••••••••• 127
J.!PD2332 •••••••••••.•••.••••••••.•.••.• 119
J.!PB2400 ••.••.•••••.•••••••.•••.•.•.•.• 124
tAPB2401 ••.•••••••.••••.•••.••..••••.••. 124

PRODUCT

PAGE

J.!PD2716 ..••.••..•...•••••.•••.•.•••••• 127
tAPB2901 •••••••.•.••.••.........•.••••.251
tAPB2902 •••••..•••.•.••••••.••.••...•.•251
J.!PB2905 ...............................251
tAPB2906 •••••...••..•.••••••••.••.••..•251
tAPB2907 ••.••.••••••..••.•••.•.•••.•..•251
tAPB2909 •...•.•.•••..•..•••.•.•.•••••••251
tAPB2911 ••••••••••••.••.•..•...•.......251
tAPB2915 •.•...••..••.•••.••••••••••.•••251
tAPB2916 .••.•••••••••••••.•..•••••••..•251
tAPB2917 ....••••••.......•••...•.••••..251
tAPB2918 .•••••• , ••.•.•••.•.•••.•..••.•• 251
tAPD4104 •...••....••.•..•••.•.••.....•• 125
tAPD510,1 ..•..••.••......•.....•...••...• 72
tLPD5101 L .•....• , ....•.•.....•••.•••..• 77
tAPD6508 •..•.•••.••.•..•.••.•••••.•.•.• 123
J.!PD8035 •.•..•••.••••.••...•••.•.••••••. 250
tAPD8048 •..•••...•••••••.••••.•••.••••.250
tAPD8080A ••.•.•••..•....••..••••••••••• 151
tAPD8080AF .......•.••••..•.•••••.•.•.••137
tAPD8085 .••..••••.•..•••••.•.••..•••••.248
tAPD8155 •.••.••.••..•••.••.••.•••.•••••248
tAPD8156 ••.•••..•••.••....•••..••••..••248
tAPB8212 .••••••••••••.••.•.•••••..••••• 205
J.!PB8214 .••••••..•.•..•..•.....•.•••.•.159
J.!PB8216 .•....•...••..••.....••••••••..211
tAPB8224 .••••••••••••..••••.•.•.•.••••. 165
J.!PB8226 ••.•..••..•.•..•.•••.•....••••.. 211
tAPB8228 .••.••••.•.•..•.•••••••..•••••. 170
tAPB8238 ••••••••••••..•••..••.••••••••• 170
tAPD8251 •••.•••.••.•..•.•..•..•..••.••• 215
J.!PD8253 ••••...... , ............•...••••246
tAPD8255 ••••••••••••..••••..•.••.•••.•. 231
tAPD8255A •.••..•••.••.•••.•.•.••.•.•••• 246
J.!PD8257 •...••.••.•.•.••.••.•••.•..••••238'
J.!PD8259 .•.•..••.•••.••••••••••••.•••••247
J.!PD8355 ••.•.••••...••.••.•..•••••.••.• 249
J.!PD8748 .•.•..........•.•.......•••••..250
tAPD8755 •.•..•..••••••.•....••..•..•..•249
J.!PDZ-80 •...•...•••..•.•.•••.•.•.••.•..• 251

3

MEMORY INDEX
RANDOM ACCESS MEMORIES '.
Dynamic RAMs
PAGE
,
~PD411. , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9
~PD411A ............................................. 16
~PD411-M ............................................ 24
~PD414 .............................................. 29
~PD416 .............................................. 37
~PD418 ..................•........................... 46
Static Bipolar RAMs
~PB2205 ............................................. 52
Static MOS RAMs
~PD410 ..............................................
~PD2101AL ., .........................................
~PD:?102AL ......... , . " ..............................
~PD2111AL ...................................... , ....
JIPD5101 .............................................
~PD5101 L ............................................

54
58
63
67
72
77

REAP ONLY MEMORIES
Electrically Erasable Programmable ROMs
~PD454 .. , .' .......................................... 82
~PD458 .............................................. 88
Field Programmable ROMs
~PB403 ...... ,....................................... 96
~PB405/425 ........................................... 100
~PB406/426 ........... , ...... , ........................ 104
Mask

Programm~ble ROMs
~PD464 ..............................................108
~PD2308 ........ , .................................... 112
~PD2316A ............................................ 115
~PD2332 .................................•........... 119

ROM Ordering Information ................................... 122

NEW PRODUCTS
RAMs
~PD414A ............................................. 123
~PD6508 ............................................. 123
~PD2114 ............................................. 124
~PB2400/2401 ......................................... 124
~PD4104 ............ '................................. 125
PROMs
JIPB408/428 .......................•................... 126
~PB427 .........•.................................... 126
~PD2716 ............................................. 127
~PP2316E ............................................ 127

5

'I

MEMORY SELECTION GUIDE

DEVICE

TECHNOLOGY

SIZE

ACCESS TIME

CYCLE

SUPPLY I
PACKAGE
VOLTAGES MATERIAL PINS

DYNAMIC RANDOM ACCESS MEMORIES
IiPD411
IlPD411-4
IlPD411A
IlPD411M
IlPD418
IlPD414
IlPD414A (F)
IlPD41,6

4K x
4K x
4K x
4K x
4K x
4K x
4K x
16Kx

TS
TS
TS'
TS
TS
TS
TS
TS

NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS

IlPD2101AL
IlPD2102AL
IlPD2111AL
IlPD5101
IlPD5101 L
IlPB2205
IlPD41 0
IlPB2400 (F)
IlPB2401 (F)
IlPD4104 IF)
IlPD2114 (F)
IlPD6508 (F)

256 x 4 TS
1Kx 1 TS
256 x 4 TS
256x4 TS
256x4 TS
1K x 1 OC
4K x 1 TS
4K x 1 OC
4K x 1 TS
4K x 1 TS
1K x 4 TS
1K x 1 TS

NMOS
NMOS
NMOS
CMOS
CMOS
Bipolar
NMOS
Bipolar
Bipolar
NMOS
NMOS
CMOS

1
1
1
1
1
1
1
1

150 ns
135 ns
200ns
200 ns
200 ns
200 ns
150 ns
150 ns

380 ns
320 ns
400 ns
400 ns
400 ns
375 ns
320 ns
375 ns

+12. +5.-5
+15. +5.-5
+12. +5.-5
+12. +5.-5
+12. -5
+12.+5.-5
+12. +5.-5
+12. +5.-5

Cerdip
' Cerdip
Plastic
Cerdip
C/P
,C/P
C/P
C/P

22
22
22
22
18
16
16
16

+5
+5
+5
+5
+5
+0
+12. +5,-5
+5
+5
+5 '
+5
+5

Plastic
Plastic
Plastic
Plastic
Plastic
Cerdip
Cerdip
Cerdip
Cerdip
C/P
C/P
C/P ,

22
16
18
22
22
16
22
18
18
18
18
16

C/P
Cerdip
C/P
C/P
C/P

24
24
24
24
24

Cerdip
Gerdip
Cerdip
Cerdip
Cerdip
Cerdip
Cerdip
Cerdip
Cerdip
Cerdip
Cerdip

16
24
24
18
18
24
24
24
24
24
28

STATIC RANDOM ACCESS MEMORIES
250 ns
250 ns
250 ns
800 ns
450 ns
50 ns
100 ns
50 ns
50 ns
200 ns
300 ns
200 ns

250 ns
,250 ns
250 ns
800 ns
450 ns
50 ns
'220 ns
50 ns
50 ns
3,10 ns
300 ns
200 ns

MASK PROGRAMMED READ ONLY MEMORIES
IlPD464
IlPD2308
IlPD2316A
IlPD2316E (F)
IlPD2332

256 x 8 TS
1Kx8TS
2Kx 8 TS
2Kx 8 TS
4Kx 8 TS

NMOS
NMOS
NMOS
NMOS
NMOS

450
450
450
450
450

ns
ns
ns
ns
ns

450 ns
450ns
450ns
450ns
450 ns

+12.+5
+12, +5.-5
+5
+5
+5

FIELD PROGRAMMABLE READ ONLY MEMORIES
IlPB403
IlPB405
IlPB425
IlPB406
IlPB426
IlPB408 (F)
IlPB428 (F)
IlPB427 (F)
IlPD2716 (F)
IlPD454
,IlPD458 (F) Future Product
* Re~d Mode

6

256x 4 OC
512x 8 OC
512x8 TS
1K x 4 OC
1K x 4 TS
1K,x80C
1Kx 8 TS
1Kx8 TS
2Kx 8 TS
256 x 8 TS
1Kx8TS

Bipolar
Bipolar
Bipolar
Bipolar
Bipolar
Bipolar
Bipolar
Bipolar
NMOS
NMOS
NMOS.

60ns
70 ns
70 ns
70 ns
70ns
85 ns
85 ns
120 ns
450 ns
800 ns
450 ns

60 ns
70 ns
70 ns
70 ns
70 ns
120 ns
120 ns
120 ns
450 ns
800 ns
450 ns

+5
+5
+5
+5
+5
+5
+5
+5
+5
+12.-5*
+12,-5*

,

MEMORY ALTERNATE SOURCE GUIDE
MANUFACTURER
AMO

PART NUMBER

DESCRIPTION

AM21(11

256 x4 SRAM
1024 xl SAAM

AM2101

Harris

"PD2102AL

PART NUMBER

DESCRIPTION

HPROM·l024A
HM6501

256 x4 PROM
256 x 4 SRAM

jlPB403
I'P05101

256 x 4 SRAM

"P02111A(

HM650B

1024 xl SRAM

256 xl SRAM

HM7610

256 x4 PROM

AM27LSOI

256 xl SRAM

,.PB22OO/"PB2202
,.PB2206

HM7640
HM7641

512 x 8 PROM

,,1>6405

512 x8 PROM

HM7642
HM7643

1024,,4 PROM

I'PB425
I'P6406

1024 x 4 PROM

I'P8426

1024 x 8
2048 x8

"P02308
jlP02316

AM27560
AM27581

i6 x 4

SRAM

,.PB2OB9/,.PB2289

256 x4 ,i>RO~

"PB403

1024 x 8 ,PROM
1024 x 8 PROM

"P84OB
jlP8428

AM3101

16 x 4 SRAM

jlP820e9

Sn7489

16x4 SRAM

,,1>82089

260B
2616

I'P82289

IM5501

ROM
16 x4 SRAM

"P0418
"P0411/1'P0411A

IM550B

1024 xl SRAM

Sn74S289

16x4 SRAM

AM9050

4096 x 1 DRAM

AM9060
AM9101

4096 x 1 DRAM
256 x4 SRAM

"Intersil

IM5523A
IM5533A

ROM

"P06508
/lPB403

I'P82089/1'P82269
I'P82205

AM9102

1024 xi SRAM

"P02102AL

IM560~

256 x 1 SRAM
256 x 1 SRAM
256 x4 PROM

9107

4096 x 1 D~AM

,.P0411/I'P0411 A

IM5605

512 x8 PROM

,.P02111AL

iM5625

512 x 8 PROM

,.P8425

IM6506A

1024 x 1 SRAM

"P065Os
,I'P0414

AM9111

256 x4 SRAM

"P02101AL

AM9206

1024x8

ROM

"P023OB

AM9216

2048 x 8

ROM

"P02316E

7005

4096 x 1 DRAM
4096 x 1 DRAM

,.P0410

7027
7101

4200

4096 xl SRAM

4402

4096 xl SRAM

,.P041 0

R03-8316A

2048 x 8

RoM

I'P02316A

R03-83168

2048 x 8

ROM

I'P02316A

"P82200/I'P82202
1'1>82206
jlP8403
,.P6405

,.P0414A

256 x4 SRAM

I'P02101AL

7111

256 x4 SRAM

,.P02111AL

7114

1024 ~4SAAM

7116
'7270

16384 x 1 DRAM

,.P0416

4096 x 1 DRAM

I'P0418

I'P02114

2101L
2102

256,,4 SRAM
1024 x 1 SRAM

,.P02101AL

7271A

4096 x 1 DRAM

I'PC>418

,.P02102AL

7280/A

I'P0411/,.P0411 A

3506

1024 x 8

I'P023OB
I'P02101AL
,.P0414A
,.P0414

IM7552

4096 x 1 DRAM
512 xl SRAM
256 x4 SRAM
1024 x 1 SAAM
4096 x 1 DRAM

,.1>02101AL
,.P02102AL
I'P0414/,.P0414A

4096 x 1 DRAM

I'P0411/,.P0411A

3538
FM4027

ROM
256 x4 SRAM
4096 x 1 DRAM
4096 x 1 DRAM

,.P02102AL

,.P0416

2101
2102
2104

16x4 SRAM
256 x 1 SRAM

,.P82069

2107

JiP82206

2111

256 x4 SRAM

,.P82205
,.P8403

2114

1024 x4 SRAM

93417

1024 x 1 SRAM
256 x 4 PROM

2116

16384 x 1 DRAM

93438

512 x 8 PROM

,.PB405

230B

1024 x 8

ROM

,.P02308

93448
93452

512 x II PROM
1024 x 4 PROM

I'P8425

2316A

2048 x 8

ROM

I'P02316A

,.P8406

2316E,

2048 x8

ROM

93453

1024 x 4' PROM

I'P8426

3101A

M82114

1024 x 4 SRAM

I'P02114

3106

256 xl SRAM

I'P82200/l'P82202

M87/l54

1024 x 4 PROM

3601

2si; x 1 PROM

I'P8403

3604

512 x 8 PROM

/lP8405

3605

1024 x4 PROM

I'P8406

4096
F16K
7489
93411
93415

16364 x 1 DRAM

Inl·1

16x4 SRAM
256 x 1 SRAM

3107
Fujitsu

NEC
REPLACEMENT

AM2111

AM27LS10

Fairchild

,.P02101AL

MANUFACTURER

AM27LSoO
AM27LS02

EM&MSemi

NEC
REPLACEMENT

M87057

256 x 4 PROM

"P8426
I'P8403

M87059

1024 x 4 PROM

)iP8406

MBB101

256 x4 SRAM

M88107

4096 x 1 DRAM

M88111

256 x 4 SRAM

MBB116

I'PD2111,AL
I'P02114
,.P0416

,.PD2316E
"P82069/,.P82289
,.P82206

I'P02101AL

3608

1024 x8 PAOM

I'P84OB

1'I>0411/1'P0411A

3624

512 x 8 PROM

I'P8426

"P02111AL

3625

1024 x

4 PROM

,.P8426

6384 x lORAM

I'P0416

3628

1024 x 8 PROM

I'P6428

M88224

4096 x 1 DRAM

I'P0414

4316A

2048 x8

M88227

4096 x 1 DRAM

I'P0414A

51.01

M8830B

1024 x 8

MBM93415

1024 x 1 SRAM

"P023OB
I'P82205

8101A
8102A
8111A

1024 xl SRAM

830B

1024 x 8

ROM

"P02111AL
,.P023OB

8316A

2048 x 8

ROM

I'P02316A

ROM

256 x
,

ROM

4 SRAM

256 x4 SRAM
1

256 x 4 SRAM

I'P02316A
I'P05101
"P02101AL
I'P02102AL

7

MEMORY ALTERNATE SOURCE GUIDE
MANUFACTURER
MMI

PART
NUMBER

Motorola

PART
NUMBER

DESCRIPTIDN

NEC
REPLACEMENT

256 x 1 PROM

"PB403

2101

256 x 4 SRAM

512 x B PROM

I'PB405

2102

1024 x I SRAM

"PD2101AL

6341

512 x 8 PROM

"P8425

2111

256 x 4 SRAM

.. P02111AL

6348

512 x 8 PROM

"PB405

2316

6349

512 x 8 PROM

I'PB425

2601

6352

1024 x 4 PROM

"PB406

2608

, 1024 x 4 PROM

2611

256 x 4 SRAM

2680

>'

Signetics

2048 x 8

ROM

256 x 4 SRAM
1024 x 8

ROM

"P02'10IAL

.. PD2316
.. P02101Al
"PD2308
"PD2111AL

6380

1024 x 8 PROM

"PB426
I'PB408

4096)( 1 DRAM

IoIPD411/IJPD411 A

6381

1024 x 8 PROM

"PB428

N3101A

16x4 SRAM

.. PB2089' .. PSn89

6530

256 xl SRAM

"PB2208

74S89

16 x4 SRAM

6531

256 x 1 SRAM

"PB2200/"PBn02

745200

256 xl 5RAM

.. PBnOO

6560

16 x 4 SRAM

"PB2089/"PB2289

74S201

256 x 1 SRAM

74S301

256 x 1 SRAM

"PR2200
.. PBn02

.. PB2089' .. PSn89

MK30000

1024 x8

ROM

2048 x 8

ROM

I'PD2308 ,
I'PD2316A

82S07

MK31000

N82S10

256 x 1 SRAM
256 x 1 5RAM

.. PBn06

MK32000

4096 x 8

ROM

I'PD2332

82S16

256 x 1 SRAM

.. PB2106

MK34000

2048 x 8

ROM

I'PD2316E

82S17

256 x 1 SRAM

.. PB2200/ .. PR2101

MK4027

4096 x 1 DRAM

I'PD414A

82S26

256 x 4 PROM

"PB403

MK4102

1024 xl SRAM

"PD2102AL

N82S115

512 x 8 PROM

~PB4:?b

MK4104

4096 x 1 SRAM

"PD4104

825126

256 x 4 PROM

.. PB403

MK4116

16384 x 1 DRAM

"PD416

N82S136

1024 x 4 PROM

N82S137

1024 x 4 PROM

"PB406
.. PB426

512 x 8 PROM
512 x 8 PROM

.. PB405
,uPB4:?f>

1024 x 1 SRAM
256 x 4 'SRAM

..PD2102AL
.. PD2111AL

82S140
82S141

MCM6604

4096 x 1 DRAM

"PD414

N93415A

MCM6616

16384 x 1 DRAM

"PD416

MCM2102
MCM2111

MCM68317

256 x 4 SRAM
2048 x 8

ROM'

,uPB220!)

TMS2101

256 x 4 SRAM

"PD2101AL

"PD2316E

TMS2102

1024)( 1 SRAM

.. PD2102AL

"PD2111AL

T,I,

1024 x 1 SRAM

.. PBn06

MCM7640

512 x 8 PROM

4096 x 1 DRAM

.. PD414A

512 x 8 PROM

"PB405
..PB425

TMS4027

MCM7641

TMS4033

1024 xl SRAM

..PD2102AL

MCM7642

1024 x 4 PROM

"PB406

TM54034

1024 x 1 SRAM

"PD2102AL

MCM7643

1024 x 4 PROM

"PB426

TMS4039

256 x 4 SRAM

.. PD2101AL

TMS4042

256 x 4 SRAM

256 x 4 SRAM

"PD2101AL

TMS4050

4096 ,x 1 DRAM

.. PD418

1024 xl SRAM

"PD2102AL

TMS4051

4096 x 1 DRAM

256 x 4 SRAM

"PD2111AL

TMS4060

4096 x 1 DRAM

"PD418
.. PD411/.. PD411 A

16384 x 1 DR'AM

MM2101
MM2102A
MM2111
MM2316A

2048 x 8

.. PD2316A

TMS4116

MM4280

4096 x 1 DRAM

"PD411M

TMS4732

ROM

4096 x 8

ROM

512 x 8 PROM

MM5280A

4096 x 1 DRAM

"PD411/"PD411A

SN74S44

MM5281

4096 x 1 DRAM

SN7489

OM 7489

16x4 SRAM

"PD411/..PQ411A
"PB2089/.. PB2289

SN74S201

156 x 1 SRAM

MM74S289

16x4SRAM

"PB2089/..PB2289

SN74S289

16 x4 SRAM

16x4SRAM

"PD2111AI

.. PD416
.. PD2332
"p8425
.. P82089/ .. PBnR9
.. PBnOO
.. PB2089/.. PB2189
.. PB2;'00/.. PB2102

DM74S387

256 x 4 PROM

..PB403

SN74S301

256 xl SRAM

DM74S572

1024 x 4 PROM

.. PB406

SN74S,314

1024 x 1 SRAM

.. PBn05

DM74S573

1024 x 4 PROM

..PB426

SN74S387

256 x 4 PROM

.. PB403

MM74C920
DM7535

256 x 4 SRAM
256 x 4 PROM

..PD5101

SN74S475

512 x 8 PROM

..PB405

DM7574

256 x 4 PROM

"PB403
.. PB403

DM77S295

512 x 8 PROM

..PB405

DM77S296

512 x 8 PROM

..PB425

1024 x 1 SRAM

"PB2205

DM93415

8

MANUFACTURER

6340

MCM68111

National

NEC
REPLACEMENT

6300

6353

Mostek

DESCRIPTIDN

Ilcro!ll::iilli'i!iimillli~,illiltil!:!i'il'l::lIi,!

JLPD411·E
JLPD411
JL PD411·1
/LPD411·2
fLPD411·3
fLPD411.4

FULLY DECODED RANDOM ACCESS MEMORY
D ESC RI PTI 0 N

The MPD41 t Family consists of six4096 words by 1 bit dynam ic N-channel MOS
RAMs_ They are designed for memory applications where very low cost and large bit
storage are important design objectives. The MPD411 Family is designed using dynamic
circuitry which reduces the standby power dissipation.
Reading information from the memory is a non-destructive. Refreshing is easily
accomplished by performing one read cycle on each of the 64 row addresses. Each
row address must be refreshed every two milliseconds. The memory is refreshed
whether Chip Select is a logic high or a logic low.

F EATU RES

All of these products are guaranteed for operation over the 0 to 70° C temperature
range.
Important features of the MPD411 family are:
• Low Standby Power
• 4096 words x 1 bit Organization
• A single low-capacitance high level clock input with solid ±1 volt margins.
• Inactive Power/0.3 mW (Typ.)
• Power Supply: +12, +5, - 5V
• Easy System Interface
• TTL Compatible (Except CE)
• Address Registers on the Chip
• Simple Memory Expansion by Chip Select
• Three State Output and TTL Compatible
• 22 pin Ceramic Dual-in-Line Package
• Replacement for INTEL'S 21078, TI'S 4060 and Equivalent Devices.
• 4 Performance Ranges:
ACCESS TIME

PIN CONFIGURATION

RIW CYCLE

RMWCYCLE

REFRESH TIME

/lPD411-E

350 ns

SOO ns

960 ns

1 ms

/lPD411

300 ns

470 ns

650 ns

2 ms

/lPD411-1

250 ns

470 ns

640 ns

2 ms

/lPD411-2

200 ns

400 ns

520 ns

2 ms

/lPD411-3

150 ns

3S0 ns

470 ns

2 ms

/lPD411-4

135 ns

320 ns

320 ns

2 ms

VBB

vss

A9

AS

AlO

A7

All

A6

cs
DIN
DOUT
AO

Address Inputs

AO' A5

Refresh Addresses

CE

Chip Enable

CS

Chip Select

DIN

Data Input

CE

DOUT
WE

Write Enable

NC

VDD

Power 1+12VI

VDD

MPD
411

PIN NAMES
AO' All

A5

Al

A4

A2

A3

VCC

WE

Da,ta Output

VCC

Power 1+5VI

VSS

Ground

VBB
NC

No Connection

Power 1-5V)

Rev/2

9

f'PD411
CE Chip Enable
A single external clock input is required. All read, write, refresh and read-modify-write
operations tak\! place when chip enable input is high. When the chip enable is low, the
memory is in the low power standby mode. No read/write operations can take place
because the chip is automatically precharging.

FUNCTIONAL DESCRIPTION

CS Chip Select
The chip select terminal affects the data in, data out and read/write inputs. The data
input and data output terminals are enabled when chip select is low. The chip select
input must be low on or before the rising edge of the chip enable and can be driven
from standard TTL circuits. A register for the chip select input is provided on the chip
to reduce overhead and simplify system design.
.
WE Write Enable
The read or write mode is selected through the write enable input. A logic high on the
WE input selects the read mode and a logic low selects the write mode. The WE
terminal can be driven from standard TTL circuits. The data inpl!t is disabled when the
read mode is selected.
AO-A"

Addresses

All addresses must be stable on or before the rising edge of the chip enable pulse. All
address inputs can be driven from standard TTL circuits. Address registers are provided on the chip to reduce overhead and simplify system design.
0,,,, Data Input
Data is written during a write or read-modify-write cycle while the chip enable is high.
The dina in terminal can be driven from standard TTL circuits. There is no register on
the data in terminal.
DQUT Data Output
The three state output buffer provides direct TTL compatibility with a fan-out of two
TTL gates. The output is in the high-impedance (floating) state when the chip enable
is Iqw or when the Chip Select input is high. Data output is inverted from data in.
Refresh
Refresh must be performed every two milliseconds by cycling through the 64 addresses
of the lower-order-address inputs AO through A5 or by addressing every row within any
2*-millisecond period. Addressing any row refreshes all 64 bits in that row.
The chip does not need to be selected during the refresh. If the chip is refreshed during
a write mode, the chip select must be high.
*,uPD411-E

= 1 millisecond

AO
Al
A2
A3
A4
A5

refresh period.

ROW
DECODE
AND
BVFFER
REGISTER

~VDD

MEMORY
ARRAY
64 X 64

64

-aVCC
--0 VSS
-aVBB

CE
DIN
WE
CS

DOUT

10

A8

A6
A7

A10
Ag All

BLOCK DIAGRAM

JL PD411
ABSOLUTE MAXIMUM
RATINGS*

IlPD411-4

IlPD411 FAMILY
(EXCEPT 411-4)

... oOe to +70o e

Operating Temperature.
Storage Temperature
All Output Voltages ..
All Input Voltages ...
Supply Voltage VDD ..
Supply Voltage Vee
Power Dissipation ...

0,"

·20

.c,

l/

"

I-

I
"~
SPEC LIMIT: .2"t,2.4V
I
I

20

4

~

V

1/ V

I...' •
•

V

V V

10

l'..

V

,,'.",\G v

.... 30

..9

........

·10

v

SPEC LIMIT: 3.2mA,O.4V

I

I

l-

I

5

VOHIVI
vOO-vBB
1000
14

13

lti'<'Y

~w- .....r- VI-

§

'<'

~,v-<;~6"

100

v'

!

"'.: ,E>

""t--..~J~

u.

"'
!f

I

10

11

1~C.

~.' 'c.

10

. / 10-".....(·3.

f"'..,

GUARANTEEIl
OPERATING REGION

·5

·6

SPE~ LI~l':

10-"
k: 17'
k: I.·7

"

f'.

t--.. ~

rms
60

·B

VBB(VI

POWER CONSUMPTION

Power consumption = V DD x IDDAV + VBB x IBB'
Typical power dissiptionfor each product is shown below,

roW (TVP.)

CONDITIONS

IlPD411-E

350

Ta = 25" C, tcy = 800ns, tCE = 380ns

IlPD411

450

Ta = 25° C, tCY = 470ns, teE = 300ns

Il PD411-1

450

Ta = 25° C, tcy = 470ns; tCE = 260ns

IlPD411-2

450

Ta =.25° C, tey = 400ns, tCE = 230ns

IlPD411-3

550

Ta = 25° C, tey = 380ns, tCE ~ 210ns

IlPD411-4

660

Ta =25° C, tey = 32Ons, teE = 200ns

See above curves for power dissi pation versus eycle time.

14

fLPD411

200

100

300

400

500

CURRENT WAVEFORMS
CE(V)

ICE (rnA)

120

~----~---------------------i~-----------,~----

80
100 (rnA)

40
100QN

0

40
20
IBB (rnA)

0

·20
·40

PACKAGE OUTLINE
Il PD4110

~
..
J

H

'

(~rJIJ
,

I

T:

,I~

I I

I

I ,

: :

•

I

:

. ,i. T ~ ~ J,U .1

G

M

c

ITEM

MILLIMETERS

INCHES

A
B

27.43 MAX
1.27 MAX
2.54 ± 0.1
0.4210.1
25.4 ±0.3
1.5 + 0.2
3.5 + 0.3
3.7 ±0.3
4.2 MAX
5.08 MAX
10.16±0.15
9.1 + 0.2
0.25 ± 0.05

1.079 MAX
0.05 MAX
O.lQ
0.016
1.0.
0.059
0.138
0.145
0.165 MAX
0.200 MAX
0.400
0.358
0.009

C

0
E;
F
G

H
I

J
K
L

M

SP411-8·77-GY-CAT

15

pPD411A-E
pPD411A
pPD411A-1
pPD411A-2
4096 BIT DYNAMIC RAMS
The IlPD411A Family consists of four 4096 words by 1. bit dynamic N-channel MOS
RAMs. They are designed for memory applications where very low cost and large bit
storage are important design objectives. The ~PD411 A Family is designed using
dynamic circuitry which reduces the standby power dissipation.

DESCRIPTION

Reading information from the memory is non-destructive. Refreshing is easily
accomplished by performing one read cycle on each of the 64 row addresses. Each
row address must be refreshed every two milliseconds. The memory is refre'shed whether
Chip Select is a logic high or a logic low.

"

~"

FEATURES

•

Low Standby Power

•

4096 words x 1 bit Organization

~i;

•

~,1.~

•

A single low-capacitance high level clock input with solid ±1 volt margins.

Inactive Power 0.7 mW (Typ.)

.' Power Supply +12, +5, -5V
•

Easy System Interface

•

TTL Compatible (Except CE)

•

Address Registers on the Chip

•

Simple Memory Expaosion by Chip Select

•

Three State Output and TTL Compatible

•

22 pin Plastic Dual-in-Line Package

•

Replacement for INTEL's 21078, Tl's 4060 and Equivalent Devices.

•

4 Performance Ranges:

ACCESS TIME R/WCYCLE ~MWCYCLE REFRESH TIME
I'PD411A·E
I'PD411A
I'PD411A·l
I'PD411A·2

350 ns
300 ns
250ns
200ns

800 ns
470n5

430 ns
400 ns

960ns
650ns
600 ns
520 ns

1 ms
2ms'

2ms
2ms

PIN NAMES

VSS

AlO

A7

AO·A11
AO·A5
CE

A6

CS

As

Ag
3

A11

Address Inputs
Refresh Addresses
Chip Enable

CE

DOUT
WE

Chip Select
Data Input
Data Output
Write Enable

DOUT

NC

AO

Power (+12VJ
Power (+5VJ

As

VOD
VCC

A1

A4

VSS
VBB
NC

Ground
(Powe; -5VJ

CS

~PD

DIN

16

411A

VDD

A2

10

A3

VCC

11

WE

DIN

No Connection

P'IN CONFIGURATION

fLPD411A
FUNCTIONAL
DESCRIPTION

CE Chip Enable
A single external clock input is required. All read, writll, refresh and read·modify-write
operations take place when chip enable input is high. When the chip enable is low, the
memory is in the low power standby mode: No read/write operations can take place
because the chip is automatically precharging.
CS. Chip Select
The chip select terminal affects the data in, data out and read/write inputs. The data
input and data output terminals are enabled when chip select is low. The chip select
input must be low on or before the rising edge of the chip enable and can be driven
from standard TTL circuits. A register for the chip select input is provided on the chip
to reduce overhead and simplify system design.
/
WE Write Enable
The read or write mode is sehictedthrough the write enable input. A logic high on the
WE input selects the read mode and a logic low selects the write mode. the WE
terminal can be driven from standard TTL cirellits. The data input is disabled when the
read mode is selected.
Ao~A11

Addresses

All addresses must be stable on or before the rising edge of the chip enable pulse. All
address inputs can be driven from standard TTL circuits. Address registers are pro·
vided on the chip to reduce overhead and simplify system design.
DIN Data Input
Data is written during a write or read·modify-write cycle while the chip enable is high.
The data in terminal can be driven from standard TTL circuits. There is no register on
the data in terrninal.
DOUT Data Output
The three state output buffer provides direct TTL compatibility with a fan-out of two
TTL gates. The output is in the high-impedance (floating) state when the chip enable
is low or when the Chip Select input is high. Data output is inverted from data in.
Refresh
Refresh must be performed every two milliseconds by cy.cling through the 64 addresses
of thelower-order-address inputs AO through A5 or by addressing every row within any
2* -mill isecond period. Addressing any row refreshes all 64 bits in that row.
The chip does not need to be selected during the refresh. If the chip is refreshed during
a write mode, the chip select must be high.
'"PD411A-E = 1 millisecond refresh period.

BLOCK DIAGRAM
AO

----0

AlO--_'"
A2 o--_~

CELL MATRIX

A30--_--I
A4 o--_~
A5

64 x'54

voo

- - - - . 0 vcc
--:--evss
---evee

o--_~

.---0 Cs
" ' - - 0 WE

TIMING
CE

0---1

GENERATOR

1/0

17

~PD411A
Operating Temperature ••••••••••••••••••.••••••••••••• OOG to +70o e
StoragfilTemperature .•••••..•••••••••.••• ~ ••••••••• -55°eto+150oe
Output Voltage
+20 to -0.3 Vo!~
All Input Voltages
+20 to -0.3 Volts
SUPRIV Voltage VDD
+~O to -0.3 Volts
Supply Voltage Vee
~ .+20 to -0.3 Volts
Supply Voltage VsS
+20 to -0.3 Volts
Pow~r Dissipation ••.••..••.••••.•••.••..• ~ .••.••••'. • • • • •. 1.0W

5

mA
mA
mA
mA

qycle Time = 800 ns
Cycle Time = 470 ns
Cycle Time = 430 ns
Cycle Time = 400 ns

100.

ItA

10

ItA

Ta=:?6 C

Average VOO Current
IIPD411A·E
1ll'0411A
IIPD411A-l
IIPD411A·2

IOO~V

IOOAV
100AV

VBB Supply Current (2)

IIlB

5

VCC ~upplV Current
during CE o,ff Cl>

ICC OfF

0.01

Input Low Voltage

VIL

-1.0

Input High Voltllll'!

VIH

CE Input Low Voltage

VILC

-1.0

CE Inpllt High Voltage

VIHC

VOO- 1

Output Low Voltage

VOL

0

Output High Voltage

~OH

2.4

Notes:

2.4

Vqo

CE, = VILC or B = VIH

0.6

V

VCC+ 1

V

O.~

V

VOO+l

V

0.40

V

IOL = 3.2 mA

V

IOH =-2.0mA

Vec
,.



-

+-IAH_

AODRESSSTABLE

,.~

'1.

r--tw-;-twp

ICW

DIN CAN CHANGE

=H'ici,;:i==

---I-IMPEDANCE

Notes:

1

tll[
~

DIN STABLE

'CO_
I,INDEFINED

"'\.(1)

$

H

L

- -

V,L

~

I

VIH
DIN CAN
CHANGE

~

-1:,-;;--=
IMP~I;:NCE

lAce

For refresh cycle. row and column addresses must be stable tAC and
remain stable for entire tAH period.

~

VOO - 2V is the reference level for measuring timing of CEo

CI>

Vss + 2V is the refer8n~e level for measuring timing of CEo

@

VIHMIN is lh~ reference level for measuring timing of the addresses,

CS, WE and DIN.
~

(2)

20

•

VILMAX is the reference level for measuring timing of the addresses.

ClI, WE and D,IN.
IISS + 2.0V I~ the reference level for measuring timing of DOUT.
VSs + D.aV is the refeiance level for mBBsuring timing of iiOUT.
, . riIuIt be it VIH unlll end of teo·

VIL

CAN CHANGE

0'0

·20

30

SPEC LlM'T. ·l2"t. 2.4~

10

,./

~

./

I

./

V~
[7 1/

20

~

V

.<,.~9.%c..

_0

"

·10

.(,

C>

""'- :--.
1
,

I--

[7

/'

vV'

.

[Z

SPEC LIMIT: 3.2mA,O.4V

I-

V OH (VI

VOO- Vea

14

13

~¥y

=~L
t

10

11

/'

10

SPE

,.~ '7'
~-

TLI!:tT. i m,
I
I

Vl7

./
·3

·4

·5

.,

20

60 •

·s

V BS (V)

POWE R CONSUMPTION
Power consumption =VDD x IDDAV

+ VBB

x IBB

Typical power dissipation for each product is shown below.

mW (TYP.)

CONDITIONS
T a = 25°C, tcy = 800 ns, tCE = 380 ns

J,lPD411A-E

300mW

J,lPD411A

460mW

T --_"'I

A5

1---oOCS
1---0 WE

TIMING
CE

ABSOLUTE MAXIMUM
RATINGS*

0-----1

GENERATOR

I/O

. -40°C to +85°C 

Vee Supply Current
during CE off

<:il

ICc OFF

Input Low Voltage

VIL

-1.0

0.6

V

VIH

2.6

VCC + 1

V

CE Input low Voltage

VILC

-1.0

0.6

V

CE Input High Voltage

VIHC

V OO - 1

Output Low Voltage

VOL

0

Output High Voltage

VOH

204

Time Between Refresh

tREF

VOO

CE

= VILC

to VIHC MAX

= 25'C

or CS = VIH

VOO + 1

V

0040

V

IOL

= 3.2 mA

V

IOH

= -2.0 mA

VCC

to VIH MAX

ms

2

~ Typical values are for T a:::: 25°C and nominal power supply voltages.
:2

The IBB current is the sum of all leakage currents.

3

During CE on

Vee supply current is dependent on output loading.

~

H

5

lee

Input High Voltage

Notes:

TEST CONDITIONS

UNIT

10

100 OFF

during CE on

DC CHARACTERISTICS

"ss = OV

.ILI

Output Leakage Current
for High Impedance State ILO

during CE off

± 5%.

A

~

'.

+

~~~

+

~
J~rIJ
I. T ~c~J,U .1
-t [,-".
"
I

T ::

I

I

'

::
: :

I

'

:

.

G

B

ITEM

MILLIMETERS

INCHES

A
B

27.43 Max.
1.27 Max.
2.54 + 0.1
0.42 ± 0.1
25.4 ± 0.3
1.5 + 0.2
3.5 ± 0.3
3.7 ± 0.3
4.2 Max.
5.08 Max.
10.16±0.15
9.1 ± 0.2
0.25 ± 0.05

1.079 Max.
0.05 Max.
0.10
0.016
1.0
0.059
0.13!!
0.145
0.165 Max.
0.200 Max.
0.400
0.358
0.009

C

0
E
F

G
H
I

J
K

L
M

26

PACKAGE OUTLINE
/lPD411-MD

JLPD411.M
READ CYCLE

AC CHARACTERISTICS
Ta '" -40"C to +85"C,

Voo '" 12V ± 5%, Vae '" 5V ± 5%, Vsa '" -5V ± 5%, Vss "'OV. unless otherwise noted.
LIMITS

PARAMETER

SYMBOL

"PD41'-M
MIN

Time Between Refresh

tREF

Address to CE Set Up Time

'AC

0

Address Hold Time
CE Off Time
CE Transition Time

'AH

'T

'50
130
0

CE Off to Output High
Impedance State

'CF

Cycle Time

'CY

CE on Time

'CE

CE Output Delay

'CO

Access Time

fAce

ce to WE

'CC

'WL

WE to CE on

'WC

CS Hold Time

tCSH

CS Set Up Time

'csc

MAX

~PD4"-1M

MIN

MAX

2

40

0

130

470
300

3000

UNIT

TEST CONDITIONS

MAX

2

2
0
150
130
0

ms

40

0
150
130
0

40

ns

0

130

0

130

ns

CL '" 50 pF

430
260

400
230

ns

3000

3000
180
200

ns

Load'" 'TTL GatA
Vref '" 2.0 or 0.8 Volts

280
300
40
0
150
0

ItPD41'-2M
MIN

230
250
40

ns
ns
ns

40
0
150
0

0
150
0

tT =- tr "'- tf '" 20 ns

ns
ns
ns
ns
ns
ns

WRITE CYCLE
Ta

=-40"C to +85a C, VOD

'" 12V ± 5%,

Vee

'=

5V ± 5%, VSS '" -5V ± 5%, VSS '" OV"unlessotherwise noted.
LIMITS

PARAMETER

SYMBOL

I'PD411-M
MIN

Cycle Time

Time Between Refresh
Address to CE Set Up Time
Address Hold Ttme

'CY
tREF

470

'AC
tAH

0
150
130
0

MAX

",P0411-1M
MIN

MAX

",P0411·2M
MIN

400

430
2

2

UNIT

TEST CONDITIONS

MAX
ns

2
0
150
130

ms

40

0
150
130
0

"0

0

40

ns

ns
ns

CE Off Time

'cc

CE Transition Time

'T

CE Off to Output High
Impedance State

'CF

0

130

0

130

0

130

ns

CE on Time

'CE

3000

ns

Load" 1TTL Gate

ns

V ref"" 2.0 or 0.8 Volts

CE to WE

'CW

230
150
230
0
40
150

3000

'W

260
180
260
0
40
180
0
150

3000

WEtoCEoff

300
180
300

DIN to WE Set Up

CD

'OW

DIN Hold Time

'OH

WE Pulse Width

CS Set"Up Time

'WP
tcsc

CS Hold Time

tCSH

Note:

CD

0
40
180
0
150

ns
tT '" tr '" tf" 20 ns
CL '" SOpF

ns
ns
ns
ns
ns

0
150

ns

If WE is low before CE goes high then DIN must be valid when CE goes high.

READ-MODIFY-WRITE CYCLE
Ta '" -40°C to +8SoC. VDD '" 12V ± 5%, VCC '" 5V ± 5%, Vee = -5V ± 5%, VSS '" OV,unless otherwise noted.
LIMITS
PARAMETER

SYMBOL

~PD411-M

MIN
Read·Modify-Write fAMW)
Cycle Time

tAwe

Time Between Refresh

tREF

MAX

~D411·1M

MIN

600

650
2

Address to CE Set Up Time

'AC

Address Hold Time

'AH

CE Off Time

'cc

CE Transition Time

'T

0

CE Off to Output High
Impedance State

'CF

CE Width During RMW

40

0

130

tCRW

480

3000

WEtoCEon

'WC

WEtoCEoff

'w

WE Pulse Width

'WP

0
180
180
0
40

'OW

DIN Hold Time

'OH

CE to Output Delay

'CO
tACC

Acce" Time
CE on Time
es Set Up Time

'CE
tesc

CS Hold Time

tCSH

CE toWE

'cw

0
150
130

480
0
150
480

280
300
3000

/JP0411-2M
MIN

UNIT

TEST CONDITIONS

MAX

520
2

0
150
130
0

OIN to WE Set Up

MAX

ns

2

ms

40

0
150
130
0

40

ns

0

130

0

130

ns

430
0
180
180
0
40

3000

350

3000

ns

tT '" tr '" tf '" 20 ns

ns

CL=50pF

430
0

150
430

ns
ns
ns

0,
150
150
0
40
230
250
3000

350
0
150
350

ns

load= 1TTL Gate

ns

Vref = 2.0 or 0.8 Volts

ns
ns

180
200
3000

ns
ns
ns
ns
ns
ns

27

READ AND REFRESH CYCLE

fL PD411·M



«a>

A4
:t.

AS

DOUT

0)

!;;i

4096 BIT
STORAGE ARRAY

-'0

I-a:

~VBB

iiiID

-VOD
_VCC

_Vss
CLOCK
GENERATOR NO.1

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . oOe to +70o e
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +150o e
All Output Voltages  tRCL (max). If tRCl + tT < tRCl (max). 60 + tRCl (max) - tRCl - tT ns min.
Operation within the tRCl (m~) limit insures that tRAC (max) can be met tRCl (max) is specified as a reference point only;,~
if tACL is greater than the specified tRCL (max) limit,. then access time is. controlled exclusively by tCAC·
VIHC (min) or VIH (min) and Vil (max) are reference levels for measuring timing of input Signals. Also. transition times are
measured between VIHC or VIH and VIL·
These parameters are referenced to CAS leading edge in random write cycles and to WRffi leading edge in delayed write or
read·modify·write cycles.
tCWD and tRWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only:
If tCWO + tT <; tcwo (min), the data out latch will contain high level data.
If tcWD;-

-J.~/
-{,/

..J
0..
0..

::>

(fJ

/

Ci

X

«
:;;

/

;'.

20 mA

0

4.0

250

I,

Z

::>
u

......

300

40 mA

f-

a:
a:

'"

0:

:2'

~

250

375

~/

10 mA

/

/

CYCLE RATE (MHz) ~ 10 3 /tRC (ns)
0

FIGURE 1

o

Maximum ambient temperature versus cycle
rate for extended frequency operation. Ta
(max) for operation at cycling rates greater
than 2.66 MHz (tCYC < 375 ns) is
determined by T a (max) rOC] ~ 70 - 9.0 x
(cycle rate [MHz] ~2.66).

50 mA

~

.E

FIGURE 2

CYCLE TIME tpc (ns)

500 400 375 300

50 mA

~

40 mA

.E
f-

a:
a:

a:
a:

Z
w

30mA

::>
SPEC LIMIT

0..
0..

""~

/'

20mA

:2'

""

",,'

10 mA

SPEC LIMIT

0..
0..

::>

...0

(fJ

20 mA

,'I'? _

0

"'"

X

«
:;;

",,'

0

10 mA

....

-

---- -- --

1----- -

0

o

1.0

2.0

3.0

CYCLE RATE (MHz) ~ 10 3 /tRC (ns)

FIGURE 3
Maximum 1003 versus cycle rate for device
operation at extended frequencie's.

40

30 mA

>..J

"",/ "

0
0

X

250 225 200

40 mA

()

"'" "'"

~-{~

M

«

300

400

w

>..J
::>

500

Z

()

(fJ

1000
I I I

250

f-

::>

4.0

3.0

Maximum 1001 versus cycle rate for device
operation at extended frequencies.

CYCLE TIME tRC (ns)
1000
I LI I

2.0

1.0

CYCLE RATE (MHz) ~ 10 3 /tRC (nsl

4.0

o

1.0

2.0

3.0

4.0

5.0
\

CYCLE RATE (MHz) ~ 103 /tpC (nsl

FIGURE 4
Maxi mu m 1004 versus cycle rate for device
operation in page mode.

fLPD416
AC CHARACTERISTICS

Ta =O°C to +70oC,VOO=+12Vt 10% VCC=+5V±10% VSB:a-5Vt10% VSS·OV
LIMITS
PARAMETER

SYMBOL

Random read or write
evcle time

tRC

IlPD416~1

pPD416

MIN

MAX

MIN

"'04'6-3

..,04'&-2

MAX

MIN

MAX

MIN

430

375

375

n.

®
®
®®

250

200

150

n.
n.
n.

200

170

135

100

n.

@®

0

50

0

40

n.

(Ii

50

3

35

n.

®

32,000

'50

32,000

n.
n.
n.
n.
n.

®

tRWC

510

430

375

375

Page mode cycle time

tpc

330

280

225

170

Access time from

tRAC

RAS
CAS

300

teAc

Output b\Jffer
tum-qff delay

tOFF

0

80

0'

70

Transition time (rise
and fall)

tr

3

50

3

50

3

~ precharge time

tRP

200

~ pulse width

tRAS

300

32,000

260

32,000'

200

,00

120

170

RAS hold time

tASH

200

CAS, pulse width

teAs

200

10,000

170

10,000

'35

10,000

'00
,00

10,000

i'fASto CAScIol",

tACO

40

100

35

85

25

65

20

50

teRP

-20

-20

-20

n.

tASR

0

0

0

0

n.

tRAH

40

35

25

20

n.

170

'35

time
CA"StoRAS

TEST
CONDITIONS

510

Read-writs cycle time

Access time from

UNIT

MAX

-20

I,.j

precharge time
Row  tACO (max).
@ Measured VoAth a I.oed equivalent to 2 TTL loads and 100 pF.
(2) :~~I~. (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage

®

Operation w,lthin the tRCD (max) limit ensures that tRAC (max) can be met. tACO (max) is specified .s a. reference
point only. if tRCD is greater than the specified tRCD (max) limit. then access time is controlled exclUSively by teAC·

® These para~te" are referenced to CAS leading edge in early .....ite cvclesand to WRITE leading edge In d~layed write or
read-modify-write cycles.

41

jLPD416
TIMING WAVEFORMS

ADDRESSES

--__________________________ O'ENI ________________________________

READ-W~ITE/READ-MODIFY-WRITE

CYCLE

~-----------------------'RWC------------------------~

V 1HC_

---{l::===.:;-====:r---

V IHC-

---4jf::=:j~::::;=j---t-----

RAS

V,L

VIH_
ADDRESSES

42

JLPD416
TIMING WAVEFORMS
(CONT.)

"RAS·ONL Y" REFRESH CYCLE

VtHC~

ADDRESSES

--------------------------OPEN----------------------________
Note: CAS" V 1HC'

'WAiTE" Don't Care

II

PAGE MODE READ CYCLE

AAS

V 1HC _
V IL_

V 1HC_

CAS

V tL _

V 1H _
AODRESSES V

IL-

V OH _
DOUT

WAITE

VOL _

V 1HC__

V 1L _

PAGE MODE WRITE CYCLE

AAS

CAS

V IL _

V 1l _

V 1H _
ADDRESSES

V 1L _

WRITE
ViL_

V 1H _

D'N

V 1L_

43

fL PD41 6
The 14 address bits required to decode 1 of 16,384 bit locations are multiplexed onto
the 7 address pins and then latched on the chip with the use of the Row Address
Strobe (RAS), arid the Column Address Strobe (CAS). The 7 bit row address is first
applied and RAS is then brought low. After the RAS hold time has elapsed, the 7 bit
column address is applied and CAS is brought low. Since the column address is not
needed internally until a time of tCRD MAX after the row address, this multiplexing
operation imposes no penalty on access time as long as CAS is applied no later than
tCRD MAX. If this time is exceeded, access time will be defined from CAS instead of

ADDRESSING

RAS.

For a write operation, the input data is latched on the chip by the negative going
edge of WRITE or CAS, whichever occurs .later. If WRITE is active before CAS, this
i$ an "early WRITE" cycle and data out will remain in the high impedance state
throughout the cycle. For a READ, WRITE, OR READ·MODIFY·WRITE cycle, the
data output will contain the data in the. selected cell after the access time. Data out
will assume the high impedance state anytime that CAS goes high.

DATA I/O

The page mode feature allows the IlPD416 to be read or written at multiple column
addresses for the same row address. This is accomplished by maintaining a low on RAS
and strobing the new column addresses with CAS. This eliminates the setup and hold
timesfor the row address resulting in faster operation.

PAGE MODE

Refresh of the memory matrix is accomplished by performing a memory cycle at each
of the 128 row addresses every 2 milliseconds or less. Because data out is not latched,
"RAS only" cycles can be used for simple refreshing operation.

REFRESH

Either RAS and/or CAS can be decoded for chip select function. Unselected chip
outputs will remain in the high impedance state.

CH IPSE LECTION

44

JLPD416

---A.--~

11-4-..

PACKAGE OUTLINE

J.LPD416C/D

~------------E----------~

.IlPD416C
(Plastic)
ITEM

MILliMETERS

INCHES

A

19.4 MAX.

0.76 MAX.

B

0.81

0.03

C

2.54

0.10
0.02

D

0.5

E

17.78

0.70

F

1.3

0.051

G

2.54 MIN.

0.10MIN.

H

0.5MIN.

0.02 MIN .

.

--

--~--

I

4.05 MAX.

J

4.55 MAX.

0.18 MAX.

K

7.62

0.30

L

6.4

M

0.25

0.16 MAX.

0.25
+0.10
-0.05

0.01

l

HlJ~~-E

M

IlPD416D
(Ceramic)
ITEM

MILLIMETERS

INCHES·

A

20.5 M~X.

0.81 MAX.

B

1.36

0.05

C

2.54

0.10

D

0.5

0.02

E

17.78

0.70

F

1.3

0.051

G

3.5 MIN.

0.14MIN.

H

0.5MIN.

0.02 MIN.

I

4.6 MAX.

0.18 MAX.

J

5.1 MAX.

0.20 MAX.

K

7.6

0.30

L

7.3

0.29

M

0.27

0.01

SP416-8-77-GY-CAT

45

Ilero~\jlil~1

fL PD4 18
fL PD41 8-1
fLPD418-2

.1
! III ~ill",
·1111·1:lllli

4096 BIT DYNAMIC MOS RANDOM
ACCESS MEMORY
The .uPD418 series is composed of high speed, dynamic, 4096 words x 1 bit, N channel,
MOS, random access memories.

D ESCR I PT I ON

All inputs, except the clock (chip enable), are fully TTL compatible and require no
pull-up resistors. The low capacitance of the address and control inputs precludes the
need for specialized drivers. The data input and output are multiplexed to facilitate
compatibility with a common bus system.
The .uPD418 has only one clock (chip enable), to simplify system design. The low
capacitance clock input requires a positive voltage (+12 volts) which can be driven
by a variety of widely available drivers.

FEATURES

•

4096 words x 1 bit Organization

•

High Memory Density - 18 Pin Cerdip and Plastic Package

•

10% Supply Margins

•

Multiplexed Data Input/Output

•

High Speed Access, Low Power Dissipation (370 mW Max)

•

Full TTL Compatibility on All Inputs (except CE)

•

Resistors for Address Inputs Provided on Chip

•

Open Drain Output Buffer

•

Single Low Capacitance Clock (CE)

•

Power Supply +12V, -5V

•

Replacement for TI's 4050 and Equivalent Devices

• 3 Performance Ranges:

IJPD418D
IJPD418D-1
IJPD418D-2

ACCESS TIME

R/W CYCLE

RMW CYCLE

POWER (TYP)

300 ns
250 ns
200 ns

470 ns
430 ns
400 ns

650 ns
610 ns
580 ns

200 mIN
200mW
200 mW

Vss

vss

I/O

Al1

PIN CONFIGURATION
PIN NAMES

AO

A10

AO-All

Address Input

Al

Ag

AO-AS
R/W

Read/Write Control

Refresh Address

A2

AS

I/O

Input/Output Terminal

R/W

A7

CE

Chip Enable (Clock)

CE

A6

VOO

Power Supply (+12V)

A3

AS

A4

Voo

VSS

Power Supply (-SV)

VSS

Ground

Rev!l
46

fLPD418

A.
A,
BLOCK D·IAGRAM A,
A,

.

A,

R/W

A6
A,

110

A6
A.
AlO
A11

CE

Operating Temperature . . . . . . . . . . . . . . . . . • . . . . . . . . . . • . . • poC to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . -55°C to +1 50°C
All Output Voltages  TYPlca! values are for Ta '" 26°C and nominal power supp.l~ volt. . .

47

fL PD41 8

READ CYCLE
Ta ~

Voo" +12V ± 10%, Vas ~ -5V + 10%, Vss~ OV unlE1ss otherwise noted

efc 10 7efe,

~P0418

LIMITS
pPD418-1

AC CHARACTERIS:fICS
J.l.PD418-2

SVMBOL MIN. MAX. MIN. MAX. MIN. MAX. UNIT

PARAMETER
Refresh Time

!ref.

Redd Cycle Time

tc(rdl

470

Pulse Width,
CEHi!tl

tVi(CEH)

300

Pulse Width,
CE Low

tw{CEL)

130

2
430
4000

260

TEST CONDITIONS

m,

400
4000

130

230

4000

"

130

CE RiseTime

trICE)

40

40

40

GE Fall Time

'fleE)

40

40

40

Address Setup

tsu(ad)

"'

"

Time
',0

Read Setup Time

Isu(rd)

Address Hold

th{ad)

150
40

150

150

Time
40

40

Read Hold Time

thIrd)

Access Time
From Address

ta(ad)

300

25Q

200

"

Access Time
FromCE

ta(CE}

280

230

180

"

Propagation Delay

tPLH

40

40

40

"'

Time, Low to High
Level Output
FromCE

CL - 5Op F, RL '" 2.2 kH.to 5.5V

load'" 1 TTL Gate, trICE) '" 20 ns

CL = SOpF, RL '" 2.2 kf! to 5.5V

Load'" 1 TTL Gate

WRITE CYCLE
Ta '"

ifc

to 70°C, VOO '" +12V ± 10%,

Vaa '" -5V

±

10%, VSS '" OV unless otherwise ooted.

liMITS
.uPD418
PARAMETER

SYMBOL

MIN.

.uPD418·1

.uPD418·2

MAX. MIN. MAX. MIN.

MAX.

Refresh Time

tref,

WnteCycle

tc~wrl

470

Pulse Width,
CE High

tw~CEH)

300

Pulse Width,
CE Low

tw~CEL)

130

Write Pulse
Width

twtwr)

180

CE Rise Time

trtCE}

40

40

40

CE Fall Time

tf(CE)

40.

40

40

Address Setup
Time

tsutadJ

Data Setup
Time

tsutda)

150

150

150

Write Pulse
Setup Time

tsutwr)

200

200

200

CE High to
Write Delay
Time(Z! (S)

tdtCEH·wr)

Data Hold
Time

th(da)

Address Hold
Time

thtad}

Write Hotd
Timetf) ®

th(Wr)

T"',

430
4000

260

UNIT

TEST CONDITIONS

400
4000

130

230

4000

130

180

180

40

40

40

40
150

150
40

150
40

40

READ·MODIFY·WRITE CYCLE
Ta

m

O°C to 70"C, VOO ~ +12V '" 10%, Vee ~

SV'" 10%, VSS

c

OV uoless otherwise ooted.

LIMITS
,uP0418
PARAMETER

,uP0418·'

,uPD418·2

SYMBOL MIN. MAX. MIN. MAX. MIN. MAx' UNIT

2

TEST CONDITIONS

m,

Refresh Time

Iref.

Read Modify
Write Cycle
Time

tc!RMW)

650

Pu\seWidth,
CE High

twtCEH)

480

Pulse Width,
CE Low

twtCEl)

130

Write Pulse
Width

twtwr)

180

CE Rise Time

trlCEl

40

40

40

ru

CE Fall Time

tf(CEI

40

40

40

os

Write Pulse
Setup Time

tsu(wrl

Address Setup
Time

tsu(ad)

ReadPul$e
Setup Time

tsu\rd)

250

200

os

Cl = 50p F, RL" 2.2 kn to 5 5V
Load'" 1 TTL Gate, tr(CE)= 2005

230

180

os

CL = SOpF, RL '" 2.2 kH to S.SV
Load'" 1 n,LGate

560

610

4000

440

4000

180

200

200

ISO

150

410.

200

150

tsu(de}

Data Hold Time

thida)

40

40

40

Address Hold
Time

th(ad}

lS0

150

150

tslsd)

300

"

180

Oata Setup Time

Acces~Time

4000

130

130

From Address
Access Time
FromCE

48

latCE)

JLPD418

READ CYCLE
1 - - - - - - - - - - t c1rdl- - - - - - - - - - \
twICEHI-----i

TIMING WAVEFORMS

c
E

~

tw(CEL) = 130 ns CONSTANT
10

tw(CEH) = 230 ns CONSTANT

o~------------~~----~--------------~------~
SOO ns
1 "s
10

"S

100 ns

CYCLE TIME

SP418·8·77·GY·CAT

51

JLPB2205
1024·81T BiPolAR tTL RAM
The!"JEC pPB2205 integrated circuits are high-speed Open-Collector TTL interface,
1024-bit Random Access Memories.
1024 Words x 1 Bit Organization (Fully Decoded)
TTL Interface
Fast Access Time - 50 ns maX.
Power Consumption - 500 mW typo
A Chip Select Input for Memory Expansion
Open-Collector Output
Ceramic 16-Lead Pual-in-Line Package
Compatibility with Fairchild's "93415" and Equivalent Devices

•
•
•
•
•
•
•
•

Cs

Vee

AO

DIN

A1

WE

A2

Ag

A3

AS

A4

Aj

DOUT

A6

GND

A5

CHIP
SELECT

DESC R I PT 10 N

FEATURES

PIN CONFIGURATION

WRITE
ENABLE

OPERATION

0

0

WRITE

0

1

READ

1

X

HOLD

OUTPUT

FUNCTION TABLE

1
Non-Inverted Data
Written in Memory

1

X - High or Low.

'""i------A

ITEM
A

52

MILLIMETERS
19.9MAX

------I

INCHES
0.784 MAX

B

1.06

0.042

C

2.54

0.10

0

0.46

E

17.78

~

0.10

0.018

!

0.004

0.70

F

I .•

G

2.54 MIN

O.10MIN

H

0.5 MIN

O.019MIN

I

4.58 MAX

0.181 MAX

J

0.059

5.08 MAX

0.20 MAX

K

7.62

0.30

L

6.4

M

0.25

0.2£1

~ ~:~~

0.0098

~ ~:~~~:

PACKAGE OUTLINE
tlPB2205D

JLPB2205
ABSOLUTE MAXIMUM Operating Temperature.
Storage Temperature.
RAT1NGS*
Output Voltage. . .
Input Voltage. . . .
Supply Voltage VCC
Output Current. . .

. -25°C to +75°C
-65°C to +150°C
-0.5 to +5.5 Volts
-0.5 to +5.5 Volts
. -0.5 to +7 Volts
. . . . . . . 50 mA

.
.
.
.

COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
'Ta = 2S'C

DC CHARACTER ISTICS

Ta = O"C to 75°C; VCC =4.75 to 5.25V
PARAMETER

SYMBOL

CD

,

LIMITS
MIN

TYP

MAX

2.0

Input High Voltage

VIH

Input Low Voltage

VIL

Input High Current

IIH

Input Low Current

-IlL

0.40

"A
mA

Output Low Voltage

VOL

0.50

V

Output High Current

IOH

Input Clamp Voltage

-VIC

Power Supply Current

ICC

Note:

CD

TEST CONDITIONS

UNIT
V

0.8
40

100
1.3
100 155

V
VI~2.7V

VI=O.4V
IOL

~

16mA

VOH = 5.25V

"A
V

-11=12mA
All input except WE grounded.

mA

Guaranteed with transverse airflow exceeding 400 linear F.P.M. and two minute warm-up,
Typical thermal resistance values of the package are:
0JA (Junction to Ambient! = 50" CfW (at 400 F.P.M, airflow!
0JA (Junction to Ambient! = 70° C/W (Free Air!
Under free air condition, ambient temperature is guaranteed O°C to 65°C.

Ta = O°C to 75"C; VCC = 4.75 to 5.25V

AC CHARACTERISTICS
PARAMETER

SYMBOL

LIMITS
MIN

TYP

MAX

UNIT

Read

Address,Access

tAA

10

50

ns

Access

CS Access

tACS

5

30

ns

Time

CS Recovery

tRCS

30

ns

tw

60

ns

Write Pulse Width Time
Write

Address Set-Up

twSA

25

ns

Set-Up

Data-In Set-Up

twSD

5

ns

Time

CS Set-Up

twscs

5

ns

Write

Address Hold

twHA

5

ns

Hold

Data-In Hold

tWHD

5

ns

Time

CS Hold

twHCS

5

ns

Write Disable Time

two

40

ns

Write Recovery Time

tWR

40

ns

Notes:

G)
@
@

Output Load - Fig. 1. Capacitances CL in
Fig. 1 including jig and scope.
Input Waveform - OV for "0" level and 3.0V
for "1" level. less than 10 ns for both rise and
fall time.
Measurement Reference - 1.5V for both
inputs and output.

'vee:
'J(J():'

Cl
I

H.'

-L

-Y-;"

pi

')OUT

(lOU: '

117

TIMING WAVEFORMS

READ MODE

Figure 1
WRITE MODE

.. ~--'I',

--....J]\--'--1-----'-+--..../I'---

SP220S-8-77-G Y -CAT

53

,uPD410
JLPD410·1
JL PD410·2

NEe IlnClmputer1i,IRC.
4096 BIT HIGH SPEED STATIC
MOS RANDOM ACCESS MEMORY
The /lPD410 is a very high speed 4K bit static random access memory. It is organized
as 4096 words by 1 bit per word and fabricated using N channel silicon gate MOS
technology.

OESCR I PTION

All signals to the device are TTL compatible except for Chip Enable which is standard
+12 Volt MaS l e v e L '
Circuit operation starts with the rising edge of CEo Data is latched and valid until
falling edge of CEo Address and Chip Select signals are latched on-chip to simplify
system timing requirements.

•
•
•
•
•
•
•
•
•
•
•
•
•

4096 Words x 1 Bit Organization
Fully Decoded
TTL Compatible (except CEI
High Speed-Access Time: 100 ns max.
Cycle Time: 220 ns min.
Static Operation - No Refresh Required
Standby Power: 75 mW max.
'Active Power: 470 mW typo
Supply Voltages: VDD = +12V, VCC = +5V, VBB = -5V
Address Registers on the Chip
Three State Output
Standard 22 Pin Ceramic Dual-in-Line Package
Pin Compatible with /lPD411 and Other 4K Dynamic RAMs

Vss
Ag

Vss

A10

A7

A"

A6

Cs
DIN
DOUT

/lPD
410

VDD
CE
(NC)

AO

A5

Al

A4

A2

A3
WE

VCC

54

AS

FEATURES

PIN CONFIGURATION

ILPD410
BLOCK DIAGRAM

AD
A1
A2
A3
A4

ROW
DECODER
AND

MEMORY

ARRAY
64 x 64

BUFFER
REGISTER

A5

CE

DIN
WE

cs
Dour

ABSOLUTE MAXIMUM
RATINGS*

Operating Temperature, . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . O°C to +70°C
Stora~e Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _65°C to +150°C
CD
All Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 to +20 Volts I
All I~put Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 to +20 VoltsCD
Supply Voltage VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 to +20 VoltsCD
Supply Voltage VCC . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. -0.3 to +20 VoltsCD
Supply Voltage VSS . . . . . . . . . . . , . . . . . . . . . . . . . . . . . .. -0.3 to +20 VoltsCD
Power Dissipation .... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.0W
Note: CD Relative to VBB
COMMENT: Strflss above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the oPerational sections of this specification is not
implied. Exposure to absolute maximum rating conditions forextellded periods may affect device
reliability,

*Ta·co 25°C

DC CHARACTER ISTICS

Ta

'=

O°C to 70 b C; VDO =- 12V ± 5%; VCC
PAllAMETER

Input Leakage Current

SYMBOL

=

5V ±5%; VBS '" -5V ± 5%; VSS '" OV
LIMITS

MIN

TYPeD

MAX

UNIT
~A

10

III

TEST·
CONDITIONS
VIN

VILMIN

to V,H MAX
CE Input Leakage Current

ILC

10

~A

VIN - vlLC MIN
to VIHC MAX

Output Leakage Current

ILO

10

~A

q§ '=' V,Le or
CS ~ VIH
Vo = OV to 5.25V

VOO Supply Current

IOOOFF

200

~A

CE -

during CE off

VOO Supply Current

~~ C!;: on ____ .. __ .

Average VOO Current
r-------~-

IODON

rnA

CE'VIHC

IODAV

60

mA

Cycle Timemin

f---IBB

Vee Supply Current
during CE off

IceOFF

100
15

~A

-

rnA

~

•. VILcor

CS· VIH

Ave:rage Vee Current

ICCAV

I nput Low Voltage

VIL

Input High Voltage

~':I

CE Input Low Voltage

...:'!LC

21
0.6

V

2.4

VCC+ 1

V

VDD-l

Output Low Voltage

VOL

0

Output High Voltage

VOH

2.4

Note: CDTypi~al values are for T a

=

rnA

-1.0
-1.0

rc"E Input High Voltage .-~ ...:'IHC
.

60

----j--

VaB Supply Current

~-

-1'.ov to

0.6V

t-:c---':-.----- 1-----

DOUT :.... No load

0.6

V

VOO+l

V

0.4

V

IOL

V

IOH - 2.0 rnA

VCC

3.2mA

25"C and nominal supply vo!ta~es.

CAPACITANCE
Ta' O°C to 70°C; VDD = 12V ± 5%; VCC' 5V ± 5%; VBB = -5V ± 5%; VSS = OV
I.IMITS
PARAMETliR

SYMBOL

Address Capacitance

CAD

MIN

CS Capacitance

CCS
DIN Capacitance
.
CIN
.
~------ 1--Dour Capacitan".':.- ~_l,JL
WE Capacitance
CWE
CE Capacitance

CCE

j----

1--

ryp

MAX

UNIT

TEST
CONO!TlONS

4

6

pF

VIN = VSS

4

pF

VIN = VSS

8

6
10

pF

V1N - VSS

5

7

pF

VOUT cVSS

8

10

pf

VIN·· VSS

18

27

pf

VIN = VSS

55

JLPD410
Ta '" O°C to 70°C; VDO"=' 12V

;!-

5%; VCC -= 5V

I
PARAMETER

I

r

LIMITS

I

410

SYMBOL

MIN

AC CHARACTERISTICS

5%; VaB = -5V ± 5%; VSS = OV (410-2: Ta '" DoC to55°CI

:!.

410-1

I TVP I MAX I MIN I

TVP

410-2

UNIT

I MAX I MIN I TVP I MAX I

TEST
CONDITIONS

READ, WRITE AND REAO·MODlFY·WRITE

Address to CE
Set Up Time
Address Hold
Time

tAH

90

70

50

CE Off Time

tcc

190

140

90

330

CE Transition
Time

CE off to Output
High Impedance
State

'CF

Cycle Time

'CY

440

CE on Time

'CE

230

CE Output
Delay

'co

190

140

90

Access
Time

IACC

200

150

100

READ

2000

20

20

'CV

440

330

tCE

230

tw

130

CE toWE

tWL

WE to CE on

'WC

Cycle Time
CE on Time

220
2000

170

2000

110

Load'" 50 pF + ITTL,
Ref -= 2.0 or O.BV
tACC"'·tAC
+tCO+tT

20
WRITE

WE to CE off

~_W~

2000

170

220
2000

100

__ ~~~cw,~~~~_1~3~0~__~____~'0~0~___

tT '" 10 ns

110

2000

70

4 ____~~70~~__~__+-~-+____________~

D,N to WE
Set Up

tow

D,N Hold Time

'DH

60

40

20

WE

Pulse
Width

'WP

130

100

70

Read·ModifyWrite (RMW)
Cycle Time

tRWC

560

350

READ·MODIFY-WRITE

420

2000

260

280

170

CE Width
During RMW

tCRW

WE to CE on

'wc

WE to CE off

'w

130

100

70

WE Pulse

'WP

130

100

70

2000

tT = 10 ns

2000

c-=.-"-----

Width
DIN to WE

~-----

tDW
-~-.--~--

40

60

20

DIN Hold
Time

tDH

CE to Output
Delay

'CO

190

140

90

tACC

200

150

100

Access Time

Load:. 50 pF + lTTL,
Ref'" 2.0 or O.BV
fACe = tAC
+tCO+tT

f7---K----j

PACKAGE OUTLINE

If----- L =nj I

R[

--;

ITEM

MILLIMETERS

INCHES

A

27.43 Max.
1.27 Max.
2.54 ± 0.1
0.42±0.1
25.4 ± 0.3
1.5 + 0.2
3.5 ± 0.3
3.7 ± 0.3
4.2 Max.
5.08 Max.
10.16 ± 0.15
9.1 + 0.2
0.25 ± 0.05

1.079 Max.
0.05 Max.
0.10
0.016
1.0
0.059
0.138
0.145
0.165 Max.
0.200 Max.
0.400
0.358
0.009

B
C
D
E
F

G
H
I
J
K
L
M

56

0 _150

I-IPD410D

-M

ILPD410

READ CYCLE

TIMING WAVEFORMS
CE

ADDRESS
ANDCS

DOUT

WRITE CYCLE

CE

ADDRESS
AND

CS

----------+_---i~----~~--+_+_--------------+_------

VIL
VIH

DIN CAN CHANGE
---------¥'-------------+_--~~~--------+_------VIL

HIGH~::::~I-----~----------r_--~

VOH

UNDEFINED

IMPEDANCE

t------ VOL

------~---------+--~.

READ·MODIFY·WRITE CYCLE

CE

ADDRE:SS

ANDCs

WE

DIN CAN CHANGE

-------11""'--------;----+ - - - - Notes:

,:1)

Von -

c?)

VSS + 2V is the reference level for measuring timing of CE.

Q)

VOL

2V ~s the reference level for measuring timing of CE.

VIHMIN

CS. WE
@

--

IS the reference level for measuring timing of the addresses,
and DIN.

V,LMAX is the reference level for measuring t1mrn.g of the addresses,

C$,

WE

and DIN

®
©

V5S + 2.0V

IS

the reference level for measuring timing of DOUT.

VSS + O.8V

IS

the reference level for mea~urlng timing of DOUT.

(j)

WE must be at V,H

until end of

tCO.

SP410·8·77·GY·CAT

57

J.L PD2101AL

JI. PD2101AL-2

J.L PD2101AL-4

1024 BIT (256 x 4) StATIC MOS RAM
WITH SEPARATE 1/0
The /lPD2101ALC is a 266 word by 4 bit static random access memory requiring no
clocks or refreshing. I!features high speed, low cost, and simplicity of interfacing.

DESCRIPTION

It is directly TTL cqmpatible in all respects; inputs, oUtputs, and a single +5V supply.
Two chip·enables allow easy selection of an individual package when output~ are
OR.tied. An output disable is provided so that data inputs and outputs can be tied for
common I/O systems. The output disable function eliminates the need for bidirectional
logic in a common I/O system. Output data is the same polarity as input data, and
readout is non-destructive.

p:'

r:
~;

The pPD2101ALC family of devices offers access times from 450 ns to 250 ns with a
typical standby mode power dissipation bf only 36 roW.
The use of NEC's N-channel silicon gate MOS process, with its excellent protection from
contamination, permits the use of a low cost 22 pin plastic package in providing a high
performance, high reliability MOS circuit at a most cost effective price level. The
/lPD2i01ALC is pin-compatible with the /lPD5101C CMOS static RAM.
•

256 x 4 Organizations t.o Meet Needs for Small System Memories

•

Access Time - 250 to 450 nsec max

•

Directly TTL Compatible - All Inputs and Output

•

Static MOS - No Clocks or Refreshing Req~ired

•

Simple Memory Expansion - CHip Enable Input

•

Low Standby Power - 36 mW typo

•

Low Cost Packaging - 22 Pin p·iastic Dual-ln·Line Configuration

•

Low Operating Power

FEATURES

• Three-State Output - OR-Tie Capability
• Output Disable Provided for Ease of Us~ in Common Data Bus Systems

A2

2

21

A4

A1

3

20

R/W

AO

4

19

eE1

18

00

17

CE2

AS

S

A6

6

A7

7

004

GNO

8

01 4

oi 1
00 1

bl 2

58

PIN CONFIGURATION

vee

A3

/lPD
2101AL

9

ri° 3

10

DI3

11

b0 2

PIN NAMES
DATA INPUT

01 1-01 4

AO-;A7

ADDRESS INPUTS

R/W

READ/WRITE INPUT

GE,

CHIP ENABLE'

CE2

CHIP ENABLE 2

OD

OUTPUT DISABLE

00,-004
VCC

DATA OUTPUT
POWER "5VI

OPERATION MODES
OUTPUT

GEl
0
0

CE2

,
,

Others

00

0

,

CHIP

MODE
Data Out

Selectpd
High

No-Selected

Impedance

JLPD2101AL
BLOCK DIAGRAM

AO
MEMORY
CELL
MATRIX
(256 x 4)

Al
A2
A3
A4
R!W
011
01 2
01 3

..J

°

-x:
1-0:
-x: Iz
'°0

Y-SELECTOR

:::)w

001

~u.

002

:::):::)

003

I-u.

oeo

C,)

01 4

1-0:

004

Y-OECOOER

eel
CE2
00

ABSOLUTE MAXIMUM
RATINGS*

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10°C to +70o,C
Storage Temperature . . . . . . . . . . . . . . . . . . . ; ....... ~ ..... -65°C to +125°C
AIIOutputVoltages ......... , . . . . . . . . . . . . . . . . . • . . . . . . . -0:5to+7Volts
All Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7 Volts
Supply Voltage Vce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7 Volts
COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device' at these or any
ottier conditions above those indicated in the operational sections of th is specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

*Ta = 25°e

DC CHARACTERISTICS

Ta = -10°C to +70°C. VCC = +5V ± 5%
LIMITS
PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

VIH

+2.0

VCC

V

Input Low Voltage

VIL

-0.5

+0.8

V

Output High Voltage

VOH

+2.4

Input High voltage

TEST CONDITIONS

V

IOH=-100jlA

VOL

+0.4

V

IOL= +2.1 mA

Input Leakage Current
High

ILiH

+10

jlA

VI = VCC

Input Leakage Current
Low

IUL

-10

jlA

VI =OV

Output Leakage
Current High

ILOH

+10

jlA

Output Leakage
Current Low

ILOL

-10

jlA

. Vo = +0.4V

Power Supply Current

ICCl

+60

mA

VI = +5.25V

Output Low Voltage

Vo = +2.4V to VCC
'CEl ':' +2.0V
CEl = +2.0V

16=OmA
Ta = +25°C
Power Supply Current

ICC2

+70

mA

VI = +5.25V
lo=OmA
Ta = -10°C to +70°C

59

l~:
,:1
~

JLPD2101Al

READ CYCLE
Ta = _10°C to +70°C, vcc = +5V ± 5%

AC CHARACTERISTICS

LIMITS
PARAMETER

SYMBOL

2101AL

2101AL·4

2101AL·2

MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX.

ns

250

350

450

UNIT

Read Cycle Time

tRC

Access Time

tA

450

350

250

ns

Chip Enable to
Output

tco

180

150

130

ns

Output Disable
to Output

too

150

130

120

ns

Data Output to
High Z State

tDF'

0

100

ns

Previous Read
Data Valid After
Change of Address

tOH

40

130

0

115

0

40

40

ns

'tDF is with respect to the trailing edge of GEl, CE2, or 00, whichever occurs first.

°

°

Ta : -10 C to +70 C, VCC: +5V ± 5%

WRITE CYCLE
LIMITS

PARAMETER

SYMBOL

Write Cycle Time

2101AL

2101AL·4

2101AL·2

MIN. TYP. MAX. MIN. TVP. MAX. MIN. TVP. MAX.

UNIT

twc

450

350

250

ns

Write Delay

tAW

20

20

20

ns

Chip Enable to
Write

tcw

180

150

130

ns

Data Setup Time

tow

180

150

130

ns

Data Hold Time

tDH

0

0

0

ns

Write Pulse Width

twp

160

130

120

ns

Write Recovery

tWR

0

0

0

ns

(Jutput Disable
Setup

tDS

20

20

10

ns

Note: 00 is a logical 1 for common I/O and "don't care" for separate I/O operation.

PARAMETER
V CC in Standby

SYMBOL
VPD

LIMITS
MIN. TvplD MAX.
1.5

UNIT

TEST CONDITIONS

V

2.0

V

VPD

V

2,OV " VPD " 5.25V

GEl Bias in Standby

VCES

Standby Current Drain

IpDl

24

36

mA

Alllnputs-VPDl -1.5V

Standby Current Drain

IpD2

30

45

mA

All Inputs: VPD2 : 2.0V

Chip Deselect to
Standby Time

tcP.

0

ns

Standby Recovery
Time

tR

tRe€'

ns

Notes:

0

STANDBY
CHARACTERISTICS

1.5V " VPD

< 2.0V

Typical values are for Ta : 25° C and nominal supply voltage.

G:> tR: tRC (Read Cycle Time).

PARAMETER

SYMBOL

Input Capacitance

CIN

Output Capacitance

COUT

-

60

LIMITS
MIN. TYP.

MAX.

,UNIT

TEST CONDITIONS

8

pf

VI :OV

12

pf

VO: OV

CAPACITANCE

READ CYCLE

,..".PD2101AL
TIMIN~

WAVEFORMS

AOORESS~______________________~

CE2

00
(COMMON 110)
DATA - OUT __

Notes:

CD

00 should be tied low for separate I/O operatio~.

@

R/W is high for read operation.

WRITE CYCLE

twc
ADDRESS __JP____________________-J~-

CE2
OD
(COMMON 110)

Note: 00 is a logical 1 for common 110 and "don't care" for separate 110 operation.

STANDBY WAVEFORMS

STANDBY MODE

Vcc

CE

OV

-

-- -- - - Notes:

-

CD

4.75V

@

2.0V

®

l.~V

-- -

AC CONDITIONS Input Pulse Levels ...... , ... , ........ : ................ +O,8V to +2.0V
OF TEST Input Pulse Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 20 ns
Timing Measurement Reference L~!Vel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5V
Output Load. . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . .. 1 TTL + 100 pF
61

/-LPD2101AL
ICC VSTa

TYPICAL OPERATING
CHARACTERISTICS ,

10~~~--~~~f,,---!~~~--jL--~
-40
-20
0
20
40
60
80
ICC VS Vee

VCC(V)

I..

A------

PACKAGE OUTLINE
IlPD2101ALC

~~~---E--------~

ITEM

M1LLlMETERS

INCHES

A

28.0 MAX.

1.10MAX.

. c

1.4 MAX

0.025

2."
0."

0.02

2~4

1.00

1.40

0.056

2.54 MIN.

'I

O.10MIN.

o.SMIN.

O.D2MIN.

4.7 MAX.

O.IeMAX.

5.2 MAX.

M

0.10

Q.20MAX.

10.16

Q'O

U

0.33

0.26 to.l0
0.06

0.01 +0.004
0.002

SP2101-8-77-GY-CAT

62

JLPD2102AL

JL PD21 02AL·2
JL PD21 02AL·4
1024 BIT FULLY DECdcED STATIC
MOS RANDOM ACCESS MEMORY
DESCRIPTION

The tlPD2102AL is a 1024 words by one bit static Random 'Access Memory requiring
no clocks or refreshing. A family of devices with maximum access times ranging from
250 ns to 450 ns meet the requirements of microcomputer memory applications where
speed, low cost and easy interfacing are prime des'ign objectives.
All tlPD2102AL inputs and outputs are TTL compatible. A single chip-enable (CE) pin
is provided for selection of an individual device in systems with OR-tied outputs.
Output data is the same polarity as input data and is nondestructively read out. Only a
single +5 volt supply is reCfliired. In standby mode, with the supply lowered to 1.5
volts, power dissipation is reduced to 42 mW max.
The tlPD2102AL famiiy is fabricai:ed using NEC's N-channel MOS silicon gate process,
providing excellent contamination protection. This process permits the use of a low cost
plastic package (16 pin) and enables high performance, highly reliable MOS circuits to
be produced.

FEATURES. AccessTime-tlPD2102AL-2-250nsMax

•
•
•
•
•
•
•
•
•
•

tlPD2102AL - 350 ns Max
tlPD2102AL-4 - 450 ns Max
Single +5 Volts Supply Voltage
Directly TTL Compatible - All Inputs and Output
Static MOS - No Clocks or Refreshihg Required
Low Power - Typically 150 mW
LoiN Standby Power - 42 mW max
Three-State Output - OR·TIE Capability
Simple Memory Expansion - Chip Enable Input
Fully Decoded - On Chip Address Decode
Inputs Protected - All Inputs have Protection against Static Charge
Low Cost Packaging - 16 Pin Plastic Dual-In-Line Configuration

PIN CONFIGURATION
A6

16

A7

A5

15

As

R/W

14

Ag

Al

13
"PO
52102AL12

CE

A2
A3

DOUT

11

DIN

A4

7

10

VCC

AO

S

9

GND

PIN NAMES
AO- Ag

Add ress inputs

R/W

ReadIWrite

CE

Chip Enable

VCC

Power (+5V)

63

,",PD2102AL
BLOCK DIAGRAM

--------® Vee

------

VPD

< +2.0V,

All Inputs. VpD1 ~ +1.5
All Inputs, VpD2

~

+2.0V

~~-------+----+-~~~--~-+-------------

65

,.,. PD2102AL
STANDBY MODE

STANDBY MODE
TIMING WAVEFORM

vcc · - - - - - - . , .

CE

- - - --- ----

ov-- - - -



ns

LOW VCC
DATA RETENTION
CHARACTER ISTICS

JLPD5101-E
TIMING WAVEFORMS

READ CYCLE

ADDRESS

GE1

00

®

(COMMON I/O)

OUT

WRITE CYCLE

twc
ADDRESS
tCW1
eE1

CE2
tCW2

00
(COMMON I/O)@

tDH

DATA
IN

DATA IN
STABLE
tow
twp

R/W

Notes:

G)
@
@

Typical values are for Ta = 2SoC and nominal supply voltage.
OD may be tied low for separate I/O operation.
During the write cycle, 00 is "high" for common I/O and
"don't care" for separate I/O operation,

LOW Vee DATA RETENTION
SUPPL Y VOLT AGE (Veel

QV------ - - - - - - - - - -

Notes: ~

4.75V

2

V CCDR

3

V 1H
O.2V

4

75

J.L PD51 01·E
VOH - 'OH nal

TYPICAL OPERATING
CHARACTERISTICS

5V

.:;
I

o

>

10
Vee (Vi

IOH (mAl

tA - Vee ITal
--

700

LOAD

~

ITTL

100 pF

4

600

\\

500

-

:'

\

400 - -

"" --

~~
~

-.........:

30 a
200

+80

e

+25

e

~

L
VCC(VI

IOL (rnAI

'ceDR - Ta

70 a

Til - 25 e
Vee 5V

60a
50a
-

:"

40

Ov-

_f-- ~

-

'-----10

eE2

.....-

1

Ic--- -.lee

+O.2V

.....-

o to Vee

V,

",

'}-J

~'';;T
,cc~

~

30a
0.0 1
20a

100

200

300

400

10

500

20

30

40

50

60

70

Td ( CI

Ie- ~ --j~

PACKAGE OUTLINE

~

-IJ--~

~PD5101C-E

'\

0-15--1

;--

ITEM

MILLIMETERS

INCHES

A
B

28.0 Max.
1.4 M,lX.
2.54
0.50 0,10
25.4
1.40
2.54 M+n.
0.5 Min,
4.7 MdX.
5.2 M;p.:
10.16

1.10 M'))('
0.025 Mc+x
0.10
002 0.004

8.5

033

C

0
F

G
H

K

M

0.25

+0.10
0 05

1.0
0.055
0.10 Min
0.02 Min
0.18 MdX.
0.20 M,\x
0.40

001

+0004
0.002

SP5101-8-77-GY-CAT

76

jLPD5101 L

JL PD5101 L·1
1024 BIT (256x4) STATIC CMOS RAM
DESCRIPTION

The MPD5101L and t.!PD5101L-l are very low power 1024 bit (256 words by 4 bits)
static CMOS Random Access Memories. They meet the low power requirements of
battery operated systems and can be used to ensure non-volatility of data in systems
using battery backup power.
All inputs and outputs of the MPD5101 Land MPD5101 L-l are TTL compatible. Two
chip enables (CE 1, CE2) are provided, with the devices being selected when CE 1 is
low and CE2 is high. The devices can be placed in standby mode, drawing 10 pA
maximum, by drilling eEl high and inhibiting all address and control line transitions.
The standby mode can also be selected unconditionally by driving CE2 low.
The MPD5101L and MPD5101L-l have separate input and output lines. They can be
used in common I/O bus systems through the use of the OD (OUtput Disable) pin
and OR-tying the input/output pins. Output data is the same polarity as input data
and is noridestructively read out. Read mode is selected by placing a high on the
R/W pin. Either device is guaranteed to retain data with the poWer supply voltage as
low as 2.0 volts. Normal operation requires a single +5 volt supply.
The MPD5101 Land MPD5101 L-l are fabricated using NEC's silicon gate com ple,mentary MOS (CMOS) process.

FEATURES

• Directly TTL Compatible - All Inputs and Outputs
• Three-State Output
•

Access Time - 650 ns (MPD5101L); 450 ns (MPD5101L-l)

• Single +5V Power Supply
• CE2 Controls Unconditional Standby Mode
• Available in a 22-pin Dual-in-Line Package

PIN CONFIGURATION

A3

22

Vcc

A2

2

21

A4

Al

3

20

R/W

Ao

4

19

CE,

18

00

RIW

ReadIWrite Input

17

CE2

CE1. CE2

Chip Enables

A5

5

A6

6

Il PD
5101L

A7

7

16

0°4

GNO

8

15

01 4

DI,

9

14

0°3

00,

'0

13

01 3

01 2

11

12

0°2

PIN NAMES
011- 01 4

Data Input

AO~A7

Address Inputs

00

Output Disable

DO, - 004

Data Output

VCC

Power (+5VI

77

f'PD5101 L

22 Vee
8

GND

ROW

BLOCK DIAGRAM

DECODERS
CEll ARRAY
32 ROWS

J2COLUMNS

00

18

Operating Temperature.
Storage Temperature
.
Voltage On Any Pin With
Power Supply Voltage. .

..............
..............
Respect to Ground.
..............

.
.
.
.

.
.
.
.

....
....
-0.3
. ...

....
. . ..
Volts
. ..

.. oOe to +70 o e
-40°C to +125°e
to Vee +0.3 Volts
-0.3 to +7.0 Volts

ABSOLUTE MAXIMUM
RATlNGS*

COMMENT:
Stresses above those listed under .. Absol~te Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional operation of the device
at these or at any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
*Ta =25,oC
Ta = O°C to 70°C; VCC = +5V ± 5%, unless otherwise specified.

DC CHARACTERISTICS

LIMITS
PARAMETER

SYMBOL

MIN TYPG)

MAX

UNIT

TEST CONDITIONS

I nput High Leakage

ILlH®

1

p.A

I nput Low Leakage

ILlL(2)

-1

p.A

VIN = OV

Output High Leakage

ILOH0

1

p.A

CE1 = 2.2V, VOUT = VCC

Output Low Leakage

ILOL®

-1

p.A

CE1 ~ 2.2V, VOUT = O.OV

Operating Current

ICC1

22

mA

Operating Current

ICC2

27

mA

Standby Current

ICCL@

10

p.A

Input Low Voltage

VIL

-0.3

0.65

V

2.2

VCC
0.4

V

VIN = VCC

V IN = VCC Except CE1
.;;0.65V, Outputs Open
VIN = 2.2V Except CE1
.;;0.65V, Outputs Open
VIN = 0 to 5.25V
CE2';; 0.2V

Input High Voltage

VIH

Output Low Voltage

VOL

V

IOL =2.0 mA

Output High Voltage

VOH1

2.4

V

IOH =-1.0 mA

Output High Voltage

VOH2

3.5

V

IOH = -100 p.A

Notes:

CD

Typical values at Ta = 25°C and nominal supply voltage.

@

Current through all inputs and outputs included in ICCL.

CAPACITANCE

LIMITS
PARAMETER
Input Capacitance

TYP

MAX

UNIT

CIN

4

8

pF

VIN

COUT

8

12

pF

VOUT

SYMBOL

MIN

TEST CONDITIONS
OV

(All Input Pinsl
Output

Capacitance

78

OV

p,PD5101L
READ CYCLE

AC CHARACTERISTICS
Ta

=

DoC to 70C e; Vee -= 5V±5%, unless otherwise specified
LIMITS

PARAMETER

5101L

SYMBOL
MIN

Read Cycle

5101L-l

TYP MAX

650

'RC

MIN

UNIT

TEST CONDITIONS

TYP MAl<

ns

450

Input pulse amplitude:
0.65 to 2.2 Volts

Access Time

'A

650

450

ns

C!1ip Enable (CE,)
to Output

'COl

600

400

ns

I nput rise and fall
times: 20 ns

Chip Enable (CE2)
to Output

'CO2

700

500

ns

Timing measurement

'00

350

250

ns

Output Disable to
Output

reference level:

1.5 Volt
Output load: ITTL

Data Output to
High Z State
Previous Read Data
Valid with Respect

a

'OF

a

tOHl

a

a

ns

'OH2

a

a

ns

150

130

ns

Gate and CL

= 100 pF

to Address Change

Previous .Read Data
Valid with Respect
to Chip Enable

WRITE CYCLE
Ta

=

O°C to 70o e; Vee

= 5V±5%,

unless otherwise specified
LIMITS

PARAMETER

5101L

5101L-l

MIN

TYP MAX MIN

Write Cycle

'WC

650

450

Write Delay

'AW

150

130

Chip Enable (CE,)
to Write

'CWI

550

350

Chip Enable (CE2)
to Write

UNIT

ns
ns
ns

Input pulse amplitude:
0,65 to 2.2 Volts

Timing measurement
reference" level:
1.5 Volt

tCW2

550

350

ns

'OW

400

250

ns
ns
ns
ns

Data Hold

'OH

100

50

Write Pulse

'WP

400

250

Write Recovery

'WR

50

50

'OS

150

130

TEST CONDITIONS

TYP MAX

pata Setup

Qutput Disable Setup

LOWVCC DATA RETENTION
CHARACTERISTICS

SYMBOL

Input rise and fall
times: 20 ns

Output load: ITTL
Gate and CL
100 pF

:=

Ta=0°Cto70"C
LIMITS
SYMBOL

MIN

VCC for Data
Retention

VCCDR

+2.0

Data Retent ion
Current

ICCDR

Chip Deselect
Setup Time

tCDR

Chip Deselect
Hold Time

tR

PARAMETER

Note:

TYP

MAX

UNIT
V

+10

/lA

TEST CONDITIONS
CE2 <;; +O-2V
VCCDR

= +2.0V

CE2 <;; +0.2V
0

ns

tRCG)

ns

,

84

'Vco(IS)

Program

Read

PIN DEFINITION

MILLIMETERS

INCHES

32.5 MAX

t.28 MAX
0.09

B

2.28'

C

2.54

0.1

0

0.5±0.1

0.02 ± 0.004

e

27.94

1.1

F

1.20MIN

0.047 MIN

G

3.2MIN

0.126 MIN

H

1.0 MIN

0.04 MIN

I

4.2 MAX

0.165 MAX
0.205 MAX

J

S.2MAX·

K

15.24

0.6

L

13.9

.0.55

M

0.3O±0.1

0.012± 0.004

PACKAGE OUTLINE
IlPD454D

p.PD454
READ OPERATION
DC CHARACTERISTICS

Ta = -10 to +70°C, VDD = +12V ± 5%, VCC = +5V ± 5%,
VBB = PG = VCL = VCG = Vss = OV
PARAMETER

LIMITS

SYMBOL
MIN

Input High

VIH

3.0

Input Low
Voltage

VIL

0

Output High
Voltage

VOH

3.5

Output Low'
Voltage

VOL

I nput Leakage
Current High

lLiH

I nput Leakage

' ILiL

TYP

MAX

UNIT

VCC

V

0.7

V

TEST
CONDITIONS

Volta~e

V

IOH = -2.0 mA

V

IOL = 1.7 mA

+10

p.A

VI = +3.0V

-10

p.A

VI = +0.7V

0.5

Current Low

AC CHARACTERISTICS

Output Leakage
Current High

ILOH

+100

p.A

CS'= "1"
Vo = 3.5V

Output Leakage
Current Low

ILOL

-10

p.A

CS= "1" '

VDD Supply
Current

IDD

VCC Supply
Current

ICC

Vo = O.4V
mA

20
0.3

mA

with no load

Ta = -10 to +70°C, VDD = +12V ± 5%, Vcc = +5V ± 5%,
VBB = PG = VCL = VCG = Vss = OV
LIMITS

PARAMETER

SYMBOL

Access Time

tACC

800

ns

tCD(on)

200

ns

CS to Output
Off Delay

tCD(off)

0

200

ns

Output Hold
Time

tOH

0

CS to Output
On Delay

MIN

TYP'

UNIT
MAX

TEST
CONDITIONS

1 TTL + 100 pF

ns

TIMING WAVEFORMS

85

f'PD454
,Before the I-IPD454 is programmed the device must be erased. All bit locations
must contain a zero (0)., The I-IPD454 programming procedure is word by word
one word at a time.

-

T a - 25P C + 2°C Voo - VCC = VSS = VCl = OV.

CS =

Either HIGH or lOW level.

LIMITS
PARAMETER

SYMBOL
MIN

TYP

MAX

yee

V

0.7

V

-2.1

V

26

27

V

26

27

V

VIH

3.0

Input low
Voltage

Vil

0

Supply Voltage

VaB

-1.9

-2.0

Supply Voltage

PG

25

Supply Voltage

VCG

25

Supply Current

laa

-8

mA

Su pply Current
(PG)

IG

+25

mA

Su pply Current

ICG

DC CHARACTERISTICS

TEST
CONDITIONS ,

UNIT

Input High
Voltage

PROGRAMMING
OPERATION

through RCG

(Vaa)

+10

/.IA

(VCG)

T a = 25°e +- 2°e VOO = Vee = VSS = Vel = OV. es = Either HIGH or lOW level.
PARAMETER

SYMBOL

liMITS
MIN

TYJ!

MAX

UNIT

Address Setup
Time

tA'im

10

/.Is

Address Hold
Time

tAHW

19

/.IS

tww

20

Write Data W.idth
Vaa Setup Time

Tas

1.0

Vaa Hold Time

TaH

1.0

PG. V CG Setup
Time

TpS

10

100

ms

AC CHARACTERISTICS

TEST
CONDITIPNS

per one word

/.Is
/.IS
/.Is

TIMING WAVEFORMS

~--------

~~-----"'I '----{'~-- - - - ---~

- - - - "l"Write

---

\.........

86

JLPD454
ERASURE OPERATION*
DC CHARACTERISTICS

Ta = 25°C ± 2°C, VDD = VCC = PG = OV, VSS = OV
CS, AO - A7 and DO - D7 = Either HIGH or lOW level, or non-connected
PARAMETER

SYMBOL

Supply Voltage

VBB

Supply Voltage

LIMITS
MIN

TYP

-4.75

-5.0

UNIT
MAX
-5.25

TEST
CONDITIONS
,

V

Vel

+35

+36

+37

V

through RCl

Supply Voltage

VCG

-39

-40

-41

V

through RCG

Supply Current
(VBB)

IBB

-235

mA

Swpply Current
(Vel)

ICl

-235

mA

Initial peak
cu rrent. S~e
tim ing chart.

Supply Current
(VCG)

ICG

-20

pA

Ta = 25°C ± 2°C, VDD = Vec = PG = OV, VSS = OV
CS, AO - A7 and DO - D7 = Either HIGH or lOW level, or non-connected

AC CHARACTERISTICS

LIMITS
PARAMETER

SYMBOL

MtN,

TYP

UNIT

MAX
60

Clear Time

TCl

VBB Setup Time

TBS

0

ps

VBB Hold Time

T~H

0

ps

VCG Setup Time

TCS

1.0

J.1s

V CG Hold Time

TCH

1.0

ps

TEST
CONDITIONS

sec

TIMING WAVEFORMS

35V
~------TCL----~

_ _ _ _ _ _ _ _-'~ - - Peak = +235 mA max.

ISS

V""---

Peak

= -235 mA max.

Note: The supply currents IBB and ICl diminish to almost zero within TCl.,

*Erasure operation clears all 2048 bits to logic "0" simultaneously.
SP4S4-8-77-GY-CAT

87

NEe Ilir8Clmputers,lDG.

Jl.PD458

FULLY DECODE.D 8192 BIT ELECTRICALLY
ERASABLE AND PROGRAMMABLE
READ ONLY MEMORY
The pPD458 is an Electrically Erasable and Reprogrammable Read Only
Memory (EEPROM), organized as 1024 words by 8 bits.

DESCR IPTION

The pPD458 is fabricated with N-channel MOS technology and is
packaged in a 28 pin ceramic DIP.

• Electrically Erasable ~nd Reprogrammable

.FEATURES

• Fully Decoded, 1024 Words x 8 Bits Organization
• Access Time - 450 ns max.
• Fast Programming and Erasure Speed
• Simple Worst-case Verification of Programmed Data and Erasure

~.;;~';., '.:~ '~.M: ~:~~i~~~~~~~~~~:tible
1,- .'
. . • .<;.i.:i.::

:

for Read and Programming Operation
Thr.State Output, OR-Tie Capability

• I\!-Channel MOS
• Two Power Supplies, +12V and +5V for Read
• 28 Pin Ceramic DIP
A7

vcc

Ae

AS
Ag

A5

NC

A4
A3
A2
A,
AO
0,

PIN CONFIGURATION

as
pIID
-458

Vee
NC

Os

02

07
06

03

05

Vss
VCG
Vee

04

VCL
PG
NC: Np Connection

Rev/1 -

#J.PD458

o ()

BLOCK DIAGRAM

• •
Cs

0

()

.•

........

I/O SUFFER

SUFFER

• •

.•

,

AO 0

0
0

V·DECODER

...

•
•
•

V·SElECTOR
)

''-'

• •••• •
0

.-

..."'"

..... VCG

0

X-DECODER

........

•
•

' 64x128
PROM CEll
MATRIX
(1024Wx 8s1

•
•
•

.Ag

....

... VCl
....

111 1

VDD

Vcc

Vss

Vss

ABSOLUTE MAXIMUM Operating Temperature •..•..............•..•..••••.• -10°Cto+70°C
RATINGS* Storage Temperature ..••....••.........•.••..•.....
-40°C to +125°C
.
Q)

All Output Voltages ......................••.. .... - 0.3 to +11 Volts
All Input Voltages ..............•..•...•.•...•.•. -0;3 to +11 Volts (!)
Supply Voltage VDD ...........•..•........... ' .•. -0.3 to +15 Volts(!)
Supply Voltage VCC .................••.•.•..•...• -0.3 to +7 Volts(!)
.
.
@
Supply Voltage VBB .......•..........•.•....•..•.•.•.Vss to -7
. Volts
(i)@
Supply Voltage PG .............•....•.....•...• -0.3 to +30 Volts
Supply Voltage VCL ............................. -0.3 to +43 VolfsCD ~
Supply V\>ltage VCG .••...............•......••• -44 to +30 VoIU@()
Notes:



(

1

Power Supply

and CS

2 are low.

. . . . . . . . . . . . . . . . ' ..... -10°C to +70 o e
. . . . . . . . . . . . . . . . . -400 eto+125°e
-0.3 to +7 Volts
-0.3 to + 7 Volts
•

•

•

Supply Voltage Vee' . . . . . . . . . . . . .

•

•

~.

•

•

•

•

•

•

•

•

•

•

•

•

••

. . . . . . . . . . . . . ..

-0.3 to +15 Volts
-0.3 to +7 Volts

COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

109

J.L PD464
DC CHARACTERISTICS

Ta =-10°C to +70°C; V DD = +12V ± 5%; VCC = +5V ± 5%; VSS = OV
LIMITS

PARAMETER

SYMBOL

TYP.

MIN.

MAX.

Input High Voltage

V IH

+2.4

VCC

Input Low Voltage

V IL

-0.3

+ 0.7

Output High Voltage

V OH

+3.5
0.5

UNIT TEST CONDITIONS

V
V
V

10H = -1.0 mA

V

10l = +1.7 mA

Output Low Voltage

VOL

Input leakage Current High

ILiH

+10

IlA

VI = +2.4V

= +0.7V

ILil

-10

IlA

VI

Output Leakage Current High

ILOH

+10

IlA

Vo

Output Leakage Current Low

ILOL

-10

IlA

VO=+O.4V

V DD Supply Current

IDD

35

55

mA

V CC Supply Current

ICC

20

30

mA

± 5%; VSS

= OV

Input leakage Current low

Ta = -1Qoe to +70'C; V DD
PARAMETER

= +12V

± 5%; VCC

SYMBOL

= +5V

I-_-TL~IM;;,;;..IT;,,;;ST-_-f
MIN.

Ta

TYP.

= +3.5V

CAPACIT ANCE
UNIT TEST CONDITIONS

MAX.

Input Capacitance

6

15

pF

f

= 1 MHz

Output Capacitance

8

15

pF

f

= 1

MHz

= -1Qoe to +70°C; V DD = +12V ± 5%;V ec = +5V ± 5%; VSS = OV
PARAMETER

LIMITS

SYMBOL
MIN.

TYP.

MAX.

AC CHARACTERISTICS
UNIT TEST CONDITIONS

Access Time

tAce

450

ns

CS to Output On Delay
CS to Output Off Delay

tCD (on)

250

ns

tCD (off)

250

ns

Output H'old Time

tOH

0
20

1 TTL + 100pF

ns

TIMING WAVEFORM

110

P. PD464
PACKAGE OUTLINE
, IlPD464C/D

===A==="I: If }--:. ~~~
,-------j-I

~_-!::-

J

If i

d!:L '

F_~_'-t.I' t

G.

'

M,

,

0-15"

_ _ _ _------=-'

\-

IlPD464C (Plastic)
ITEM

INCHES

MILLlIYIETERS

A

33 MAX

1.3MAX

B

=1.53

0.1

C

2.54

0.1

0

Q.5 ± 0.1

0.02± 0.004

E

27.94

1.1

F

1.5

0.059

)

G

2.54 MIN

0.1 MIN

H

0.5 MIN

O.O;!MIN

I

5.22 MAX

,O.2!)5 MAX

J

5.72 MAX

0.~25MAX

K

15.24

0.6

L

ip

0.52

M

025 +0.10
.
-0.05

+0.004
0.01 -0.0019

~-----------------,~---------------'~I

IlPD464D (Ceramic)
ITEM

MILLIMETERS

'INCHES

A

32.5 MAX

1.2BMAX

B

2.28

0.09

C

2.54

0.1

0

0.5 ± 0.1

0.02 ± 0.004

E

27.94

1.1

F

1.20 MIN

0.047 MIN

G

3.2MIN

0.126 MIN

H

1.0MIN

0.04 MIN

I

4.2 MAX

0.165 MAX

J

5.2 MAX

0.205 MAX

K

15.24

0.6

L

13.9

' 0.55

M

0.30 ± 0.1

0.012 ± 0.004
SP464-8-77-GY-CAT

111

JLPD2308
FULLY DECODED 8192 BIT MASK
PROGRAMMABLE READ ONLY MEMORY
The NECj.lPD2308 is a high speed 8,192 bit mask programmable Read Only Memory
organ ized as 1024 words by 8 bits. The j.lPD2308 is fabricated with N-channel MOS
technology.

DESCRIPTION

Two Chip Selects are provided - CSl which is negative true, and CS2/CS2 which may
be programmed either negative or positive true at the mask level.

FEATURES

1024 Words by 8 bits Organization
Fast Access - 450 ns max
Two Chip Select Inputs for Easy Memory Expansion
TTL Compatible - All Inputs and Outputs
Three State Output - OR-Tie Capability
Fully Decoded
Standard Power Supplies - +12V, ±5V
24 Pin Plastic or Ceramic Dual-in-Line Package
Pin Compatible with INTEL 8308

•
•
•
•
•
•
•
•
•

A7

24

VCC
AS

A6

2

23

A5

3

22

A9

A4

4

21

Vss

A3

5

20

CS1

A2

6

j.lPD
2308

19

Voo

18

CS2/CS2

17

Os

A1

7

AO

S

°1

9

16

07

°2

10

15

06

03
VSS

112

12

14

°5

13

°4

PIN CONFIGURATION

PIN NAMES
AO-Ag
CS1
CS2/CS 2
°1-0S

Address Inputs
Chip Select 1
Chip Select 2
Data Outputs

.

''''.+

r~

JLPD2308
BLOCK DIAGRAM

c:
w

AO
A1
A2
A3

01

0
0

c:
w

Y·SELECTOR

u

02
03
04
05
06
07
08

L1..
L1..

W

0

:::l

>-

aJ

I-

------

:::l
Q..

I:::l

0

A4
c:
w

A5
A6

MEMORY CELL
MATRIX
1024 x 8

0
0

A7

u
w

AS

X

0

CS
BUFFER

Ag

ABSOLUTE MAXIMUM
RATINGS*

Operating Temperature . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . -10°Cto +70°C
Storage Temperature . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125~C
All Input Voltages. . . . . .
. . . . . . . . . . . . . . . . . . . . . . . -1 to +7 Volts 

r

A4

::>
"~

A5

'"ill
a:
a
a

A6

«

A7
AS
Ag
AlO

-wOe to +70°C
.. -65°C to +125°C
-0.5 to +7.0 Volts CD

Operating Temperature
Storage Temperature ..' ...
Supply Voltage On Any Pin
Note:

CD With

ABSOLUTE MAXIMUM
RATINGS*

Respect to Ground

COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

DC CHARACTERISTICS

=+5V ± 5% unless otherwise specified

Ta = -10°C to +70°C; Vee

LIMITS
PARAMETER

SYMBOL

Input Load Current

MIN.

TYP.

The 80 instructions of the "COM-43 are designed to perform controller
oriented functions and for efficient use of the program memory space.
These 80 instructions include a number of multi-function instructions,
powerfun/O instructions including single bit manipulation, and testand-skip instructions for conditional processing.

•
•
•
•
•
•
•
•

Stand alone 4-bit microcomputer for control applications
80 powerful instructions capable of: binary addition; decimal
addition and subtraction; and logical operations
'10 "sec instruction cycle
2000 x 8-bit program memory (ROMI
96 x 4-bit data memory (RAMI
35 input/output lines consisting of: two 4-bit input ports, two
4-bit input/output ports, four 4-bit output ports, one 3-bit
output port. All capable of both single bit manipulation and
4-bit parallel processing
,
3-level stack
Six 4-bit working reiJisters
Hardware ,interrupt including enable/disable capability
On-chip programmable interval timer
'
On-chip clock generator
Open drain, TTL compatible outputs
Single supply, -10V PMOS technology
'42 pin plastic dual-in-line package

BLOCK DIAG~AM IlCQM-43 (IlPD546C)

EI
133

tLCOM-45
DESC;RIPTION

DESCRIPTION

The !,COM-44 (Part No. !,PD547C) is a4-bit parallel microcomputer that is ideally suited for a wide range of low cost,
general purpose controller applications.

The !'COM-45 (Part No.!'PD550C) is a single chip microcomputer designed for extremely low cost, general purpose
controller/consumer/ appliance applications.

The !,PD546C contains all the functional blocks needed for a low
cost, stand alone, high volume controller. These blocks include:
a 4-bit parallel ALU; 1 K by 8-bit ROM for program storage; 64
by 4-bit RAM for data storage; 35 input/output lines; interrupt
, capability and an on-board clock generator.

The !,PD550C contains all the system blocks necessary to build an
inexpensive, yet fully functional controller. The blocks include:
a 4-bit parallel ALU; 640 by 8-bit ROM for program storage;
32 by 4-bit RAM for data storage; 21 input/output lines; interrupt
capability and an on-board clock generator.

The 58 instructions of the !,COM-44 are designed to perform
controller oriented functions and for efficient use of the program
memory space. These 58 instructions include a number of multifunctional instructions, powerful I/O instructions including
single bit manipulation, and test-and-skip instructions for
conditional processing.

The 58 instructions of the !'COM-45 are designed to perform
controller oriented functions and for efficient use of the program
memory space. These 58 instructions include a number of multifunctional instructions, powerful I/O instructions including single
bit manipulation, and test-and-skip instructions for conditional
processing.

The !,COM-,44 is ideally suited for consumerlindustrial controller
functions because of its extensive I/O, on-board ROM/RAM
space and its powerful instruction set.

The I'COM-45 opens up entire new areas of controller applications
because of its extremely low cost and powerfu I functions.

FEATURES
•
•
•
•
•
•

•
•
•
•
•

Stand alone 4-bit microcomputer for control applications
58 powerful instructions capable of:
Binary addition; decimal addition and subtraction;
and logical operations
10 !,sec instruction cycle
1000 x 8-bit program memory (ROM)
64 x 4-bit data memory (RAM)
35 Input/Outputlines consisting of:
Two 4-bit input ports
Two 4-bit input/output ports
Four 4-bit output ports
One 3-bit output port
All capable of both single bit manipulation and 4-bit
parallel processing
Single level stack
On-chip clock generator
Open drain, TTL compatible outputs
Single supply, -lOV PMOS technology
42 pin plastic dual-in-line package

BLOCK DIAGRAM tLCOM-44 (tLPD547C)

:1

134

FEATURES
•
•
•
•
•
•

•
•
•
•
•

Stand alone 4-bit microcomputer for consumer/control
applications
58 powerful instructions capable of:
Binary addition; decimal addition and subtraction;
• and logical operations
10 !'sec instruction cycle
640 x 8-bit program memory (ROM)
32 x 4-bit data memory (RAM)
21 Input/Output lines consistin.g of:
One 4-bit input port
Two 4-bit input/output ports
Two 4-bit output ports
One l-bit output port
All capable of both single bit manipulation and 4-bit
parallel processing
Single level stack
On-chip clock generator
Open drain, TTL compatible outputs capable of -35V
Single Supply, -lOV PMOS technology
28 pin plastic dual-in-line Package

BLOCK DIAGRAM tLCOM-45 (/lPD550C)

pCOM-43/44/45 PIN CONFIGURATIONSCL,....--o--,--.r-------O='-CLO
pcc
VGGI-'OV)
pc,
PC2
PC3

PIN NAMES

PB3
PB2
PB,
PBO
PA3
P,A2
PA,
PAO
PI2

1Tirf
RES
PDO
PO,
PD2
PD3
PEO
PE,
PE2
PE3
PFo
PF,
PF2
PF3
TESt
IOV) GND

pi,

PIO
PH3
PH2
PH,
PHO
PG3
PG2
PG,
PGo

CLa-CL,

External Clock Source

Pea-Pe3
INT

Input/Output Port C

RES

Reset

PD2
PD3
PEo
PE,
PE2
PE3
VssIOV} . .'-'-_ _ _-.:~

Input

POO-!,D3

Input/Output Port 0

PEO-:-PE3

Output Port E

PFO-PF3
TEST

Output Port F

PGa-PG3

OUlput Port G

PHa-PH3

Output Port H

PIO:-PI3

Output Port I

PAa-PA3

Input PortA

PBa-PB3

Input Port B

CLO

PO,

lnter~uPt

Input for Testing,
(Normallv GND)

PIN NAMES

VGGI-'OV)
RES

CLa-CL,

External Clock Source

iN'f

PC", Pe3

Input/Output Port C

PA3
,PA2
PA,

PDa-PO :!

Inp,ut/Output Port 0

PEa-PE3

Output Port E

PFO-PF3

Output Port F

PGo

Output Port G

PAO
pGo
PF3
PF:i
PF,
PFo
TEST

PAa-PA3

Input PortA

INT

Interrupt Inin.it

RES

Reset

pCOM-43/44/45 INSTRUCTION SETS
(j)

®

CLA

,

C~A

DEC
CLe
STC

'xC'
~",,'

~.

'QeM
AD

1/7.-3

,
,

1/2-3

J:

,\

ADS
ADe
OA~

DAS
EXL
LI
S

Acc<-IAcCH

Borrow

skip if Borrow

XMI

LDZ

+t

DED

-INO

; :,1('''':-:;;::'':;' , """"1-'

TAL
TLA

1/2-3

1/2-3

LDI

C-'
.~CIootC'1

!lOPii-o

,
,
,
,

1/2-3

'Carry

_:liilOPll-o, "

®

,

Acc<-iAccI+IIDPIi
skip if Carrv
ACC.C-1ACC)+[IDPI) +ICI
skip If carry
Acc.C-IACC)+[IOPI) +(CI

•
,

DPL.....(OPL)+1
skip if (QPL}=O

IOPL)1=()

1/2-3

,

1/1-3

1/2-3

OP+-1S-IO

OJ

DPW-O
DPL-13 12 1, 10
1/2-3

OPL-IOPLI-\
skip if IDPLI=F

'~DPll=F

llz-]

OPe-IOPL)+1
, ( , if 1DPll=O

(OPll.iO

OPL-IAce'
AcC-tDPLI

carry
,'l.~I:lP~1

TMS
TAB
eMS

IDPLI'"F

·S.. :

1/2-3

,
'::

, Are' .h

I f1(f,
I'PlF
IOPL'''F

,

eM
CI
CLI

r

"1/2-3
1/2-3

IOP.B1 801l-'
[IDP.8t 80 Il +-O
s!tipif HOP.B,BO))-1
skip if (A(:cIB,Bo"-1
skip if IAeelB, BaH
.. [IOP.B1 Bo lI

"

•

eAL

2

_if

....... , ~If . . . .

1'· :11:-''''.4
12-3

0/,-4
0/,'4

skip if Ace =
P
skip if IAccl=13121110
skip if IDPL'''131211Ip

PC-PaP:zP,PoOO

Acc~

IAcc'-13 12 I,lo
IDPLI=13 1211 10

STACK+-{PC)

2'

PC-P'0-Po

RT

PC+-(STACK'

RTS

3-4

SThl

:2"

,2

SEO
REO
SPO
RPO

,

TPA

1

..

'~",I!!'-'
.....1ffTMflF'""
PORT
PORT
PORT
PORT

0/,..

skip If IPORT IOLL.B, Boll

=,

,

Unconditional
-;.""

,IITMM·..1

E IB ... Bol-1
E IB1BOI+-O
tOPL.8, BOI-1
(OPL.8,BOI-o

skip if (PoRT A 18,8011-1

1/2-3

IA
IP
NOP

Ncn.s:

PC-ISTAC~I

PC-IPC)+1.2

"TM"'"f-t.oO ."

tf'J.~.

oeo

2' '"," ,fU\Q 18,801i' -,,'

2 '

STACK-(PCI

OE
OP'
IIDP.9,BoIi ,
IAcelS, BoU-1
IAceIB,BoH
,-[IOP.8, BO)]

liNT F/f)=l

PC<:-Pm-Po

CZP

TPO

1

INT F/F+-O

Ic)-'

PCs.,.o..... Aa A2A 'AoOG

ITM .• ,

5MB
RM9

skip if liNT F/FI=l

INnF f-1
INnFI!+O

I(DPlIO()

IIDPII-~

XD

TIT

®

@
skip if lel=1

~I, '

OPL+-(O~L)+l

Carry

Ace-IIDPII
Ace-I IDP1 )
DPH-tOPHI¥OM, MO
(Aecl.... ((DPI)

@
1/2-3

skip if IDPLI=O

ACC-(~CC)+10

IAccl"'((DPI
DPH-IDPHI'II'OM1 MO
IAce}

ACc+-1ACcI

INM .1"

~.

(j)

Acc--O,

CIA
INC

®

@

@

1

IPORT AlB; BOU
=1

(PORT (OPL.
O,~I·'

PORT E-IACCI
PORT IOPLI-IAccl
PORT C.D-17-IO
Aec-1PORT AI
ACe- PORT DPLII
No Operation



Glock Input

J.LCOM-42 INSTRUCTION SET

H)'7M2M1MO

IDPL)-S
or

DPL~IDPL)+l

IDPL)=O

IACC)-lDPJ

IDPL)-F

DPH~IDPH)'7M2M1MO

or

IAcel

SF2

1

F2~1

=13 1211 10
K4=1

RF3

1

F3<-O
F3~1

SF3

1

PC<-ITR ),PS-O

RF4

1

F4<-O

PCS-4~PS-4

SF4

1

F4~1

PC3"()~P3..()VIACC)

RF5

1

F5<-O

PCS-O~PS,,()

SF5

1

F5~1

lSTACKJ~IPC)

RFS

1

FS<-O '
F6+-1

'

PC~ 1OOOPSPSP 4P3P2P 1Po

SFS

1

PC~lSTACKJ

RF7

1

F7<-O

PC-lSTACKJ

SF7

1

F7~1

PC~IPC)+l

RFS

1

FS<-O

LI

1

ACC~13121110

EIA

1

Enable IA port

SFS

1

Fa+- 1

LDI

1

DP~IS-IO

DIA

1

'Disable tA port

RF9

1

Fg<-O

IND

1/2

DPL ~IDPL)+l

IDPL)-S or

EIB

1

Enable 1B port

SF9

1

Fg~l

IDPL)=O

DIB

1

Disable 18 port

RFO

1

FO<-O

DED

1/2

DPL~IDPL)-l

OIU

1

U7_0-17-O

SFO

1

FO~l

R7_0~IQ7"())

NOP

1

No Operation

DPL~IPPL)-l

IDPL)=7

IDPL)-F or
IDPL)=7

XDP

1

IDPI-IDP')

ERO

1

Enable R- port

ZAG

1

OOODPL~IDP)

DRO

1

Disable R port

DEVELOPMENT TOOLS

Notes:

2_
INTE
DBIN

Wf!
SYNC
VCC

4
5
6
7
8
9
10 "PO
118080AF
12
13
14,
15
16
17

18
19
20

,

A11
A14
A13
A12
A15
A9
A8
A7
A6
A5
A4
A3
VDD
A2
A1
AO
WAIT
READY
/1/>1
HLDA

:i

Rev/1
137

J.4PD8080AF
The JlPD8080AF contains six.8-bit data registers, an 8-bit accumulator, four testable
flag bits, and an 8-bit parallel binary arithmetic unit. The JlPD8080AF also provides
decim~1 arithmetic capability and it includes 16-bit arithmetic and immediate Qperators
which greatly simplify memory address calculations, and high speed arithmetic
operations.

FUNCTIONAL
DESCRIPTION

The JlPD8080AF utilizes a 16-bit address bus to directly address 64K bytes of
memory, is fully TTL compatible (1.9 mAl, and utilizes the following addressing
modes: Direct; Register; Register Indirect; and Immediate.
The JlPQ8080AF has a stack architecture wherein any portion of the external memory
can be used as a last in/first out (LI FO) stack to store/retrieve the contents of the
accumulator, the flags, or any of the data registers.
The JlPD8080AF also contains a 16-bit stack pointer to control the addressing of this
external stack. One of the major advantages of the stack is that multiple level inter·
rupts can easily be handled since complete system status can be saved when an interrupt occurs and then restored after the interrupt is complete. Another maior advantage
is that almost unlimited subroutine nesting is possible.
\
This processor is c!esigned to greatly simplify system design. Se'parate 16-line address
and 8-line bidirectional data busses are employed to allow direct interface to memories
and I/O ports. Control signals, requiring no c!ecoding, are provided directly by the
processor. All busses, including the control bus, are TTL compatible.
Communication on both the address lines and the data lines can be interlocked by
using the HOLD input. When the Hold Acknowledge (HLDA) signal is issued by the
processor, its operation is suspended and the address and data lines are forced to be in
the FLOATING state. This permits other devices, such as direct memory access channels (DMA), to be connected to the address and data busses. '
. The JlPD8080AF has the capability to accept a multiple byte instruction upon an interrupt. This means that a CALL instruction can be inserted so that any address in the
memory can be the starting location for an interrupt program. This allows the assignment of a separate location for each interrupt operation, and as a result no polling is
required to determine which operation is to be performed.
NEC Qffersthree versions of the JlPD8080AF. These processors have all the features
of the JlPD8080AF except the clock frequency ranges from 2.0 MHz to 3.0 MHz.
These units meet the performance requirements of a variety of systems while maintaining software and hardware compatibility with other 8080A devices.
.,8 0-15 (THREE STATE)

AI _
LATCH

BUFFER

a INlDECREIlENTER
PC '(161
SP (t6)

TilliNG 8 CONTROL
STATE CNTR

!18I*
LI8I

W(I)-

'CYCLE CNTR

"181

DECODER

"CO

FLAG REGISTER
BIT 7- S:SIGN
BIT 6 - Z:Z£RO

*TEMPORARY REGISTER
. DBO-7 (THREE STATE)

BIT 5- O:ALWAYS·O·
81T4- ACY:AU)(ILIARY CARRY

81 T 3- O:ALWIlYS·O·
BIT 2-P:PARITY
BIT I -l:ALW~YS "I·
BIT 0 - CY:CARRY

1~8

BLOCK DIAGRAM

JLPD8080AF
PIN IDENTIFICATION

PIN
NO"

SYMBOL

NAME

FUNCTION

,

I,
25-27,
29-40

AI5-AO

Address Bus
(output threestate)

The address bus is usad to addre.. memory'(up to 64K S-bit words)
or specify the I/O device number (up to 256 input and 256 output
devices). AO is the least significant bit.

2

VSS

Ground (input)

Ground

3-10

07- DO

Data Bus (input/
output three-state)

The bidirectional data bus communicates between'the processor,

,

memory, a,nd 1/0 devices for instruotions and data transfers. During 8ach sync time, the data bus contains a status word that

describes the current machine cycle. DO is the least significant bit.
11

VBB

VBB Supply Voltage
(input).

-5V± 5%

12

RESET

Reset (input)·

If the RESET signal is activated, the program counter is cleared.
After RESET, the program starts at location 0 in memory. The
INrE and HLDA flip·flops are also reset. The flags, accumulator,

stack pointer, and registers are not cleared. (Note: Externai synChronization is not required for the RESET input signal which
must be active for a minimum of 3 clock periods.)
13

HOLD

14

INT

Hold (input)

HOLD requests the processor to enter the HOLO state. The HOLD
state allows an external devico to gain control of the IIPD8080AF
address and data buses as. soon as theIlPD8080AF has completed
its pse of these. buses for the current machine cycle. It is recognized under the following conditions:
0
The processor is in the HALT state.
0
The processor is in the 1'2 or TW stage and the READY Signal
is active.
As a result of entering the HOLD state, the ADDRESS 8US
(A15 - AO) and DATA BUS (D7 - DO) are in their high impedance state. The processor indicates its state on the. HOLD
ACKNOWLEDGE (HLDA) pill.

Inter~upt Request

The IIPD8080AF recognizes an interrupt request on this line at
the end of the current instruction or while halted" If the
IIPD8OS0AF is in the HOLD state, or if the Interrupt Emible
flip-flop is reset, it will not honor the reqaest.

(input)

15

Phase Two (input)

Phase two of processor clock.

Interrupt Enable
(output)

INTE indicates the content of the internal interrupt enable flipflop. This flip-flop is set by the Enable (EI) or reset by the
Disable (DI) interrupt instructions and inhibits interrupts from
being accepted by the processor when it is reset. INTE is aut...
matically reset (disabling further interrupts) during T 1 of the
instruction fetch cycle (M 1) when an interrupt is accepted and
is also reset by the RESET signal.

DBIN

Data Bus In
(output)

D81~ indicates that the data bus is in the input mode. This
Signal is used to enable the gating of data onto theIlPD8080AF

18

WR

Write (output)

WR is used for memory WRITE or 110 output control. The data
on the data bus is valid while the WR signal is active (WR = 0).

19

SYNC

Synchronizing Signal

The SYNC signal indicates the beginning of each machine cycle.

16



(.)

...

~

::>

'"
0.5L----'-----'------'
+75
+50
+25

o

AMBIENT TEMPERATURE eel

Notes:

 VIH internal active pull-up resistors will
be switched onto the data bus.
Minus (-) designates current flow out of the device.
AI supply/ATa = -0,45%fc.

CAPACITANCE

Ta = 25°C, VCC = Voo = VSS = OV, VBB = -5V.
LIMITS
PARAMETER

Cq,

I nput Capacitance

CIN
COUT

Output Capacitance

140

SYMSOL

Clock Capacitance

MIN TYP MAX
17
6
10

25
10
20

UNIT TEST CONDITIONS
pF
pF
pF

Ie = 1 MHz
Unmeasured Pins
Returned to VSS

JLPD8080AF
PROCESSOR STATE
TRANSITION DIAGRAM

I
I

I

:@
I

I HOLD
I MODE

I

I
I

L--~n.._--a-

- _.J

RESET HLTA

Notes:

I'·

INtE F/F IS RESET IF INTERNAL INT F/F;S SET.
INTERNAL INT F/F IS RESET IF INTE F/F IS RESET.
IF REQUIRED, T4 AND TS ARE COMPLETED SIMULTANEOUSLY
WiTH ENTERING HOLD STATE.

141

JLPD8080AF
Ta = O°C to +70°C, VDD = +12V ± 5%, VCC

= +5V

± 5%, VBB = -5V ± 5%, VSS = OV, unless otherwise

specified.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Clock Period

tCY'@

0.48

2.0

IISec

Clock Rise and Fall Time

t r , tf

0

50

nsec

1 Pulse Width

tl

60

nsec

2 Pulse Width

t2

220

Delay 1 to 2

tDl

0

nsec
nsec

Delay 2 to 1

tD2

70

nsec

Delay 1 to2 Leading Edges

tD3

80

Address Output Delay From 2

tDA @

200

nsec
nsec

220

nsec

120

nsec

140

nsec

tDF

nsec

Data Output Delay From 2

too @

Signal Output Delay From 1,
or 2 (SYNC, iNA, WAIT,
HLDA)

tDC @

DBIN Delay From 2

tDF @

Delay for Input Bus to Enter
Input Mode

tDI

Data Setup Time During 4J1 and
DBIN

tDSl

30

nsec

Data Setup Time to 2 During
DBIN

tDS2

150

nsec

Data Hold Time From 2 During
DBIN

25

2
READY Setup Time During 2

tRS

120

nsec

nsec

HOLD Setup Time to 2

tHS

140

nsec

Its

120

nsec

Hold Time from 2 (READY,
INT, HOLD)

tH

0

nsec

Delay to Float During Hold
(Address and Data Bus)

tFD

Address Stable Prior to WR

tAW@

Output Data Stable Prior to WR

tDW@

Output Data Stable From WR

two

Address Stable from WR

tWA

120

!6>

0
®

H LOA to Float Delay

tHF

iNA to Float Delay

tWF

Address Hold Time after DBIN
during HLDA

tAH @

Notes:

2 + t2 + tf2 + tD2 + trl
TYPICAL
~

,.
"

OUTPUT DELAY VS.
CAPACITANCE

0

+10

..J

W

"
".
" tCY Min.

~

+20

/

/

'-,. SPEC

o

+50

.6. CAPACIT ANCE (pf)
(CACTUAL - CSPEC)

142

TEST CONDITIONS

nsec
200

I NT Setup Time During 2
(During 1 in Halt Mode)

0

AC CHARACTERISTICS
~PD8080AF

LIMITS

+100

JLPD'O~OA'F
AC CHARACTERISTICS

'Ta = etc to +7etC. VDD = +12V ± 6%. VCC = +5V ± 5%; VBB· -6V ± 5%. Vss = OV. unl ... oth.rwise
specified.

#,PD8080AF-2

LIMITS
PARAMETER
Clock Period
Clock Rise and Fa~ Time
<1>1 Pulse Width
<1>2 Pulse Width
Delay'1 to <1>2
Delay <1>2 to <1>1
Delay <1>1 to <1>2 teading Edges
Address Output Delay From <1>2
Data Output Delay From <1>2
Sigrial Output Delay From <1>1.
or <1>2 (~YNC. WR. WA!T.
HLDA)
DBIN D.lay Frqm <1>2

SYMBOL

MIN

tCY@

0.3B
0
60
175
0
70
70

tr,tf

'<1>1
'<1>2
tDl
tD2
tD3,
tOA@
too@

tDC@
tDF@

25

TVP

MAX

UNIT

2.0
50

jlsec

TEST CONDITIONS

"sec
nsec

175
200

"sec
"sec
"sec
nsec
nsec
nsec

120
140

nsec
nsec

tDF

nsec

CL

= 100 pF

CL

=50 pF

Delay for' Input Bus tQ Enter

Input

Mo~

tDI

2,Durinp
DBIN
pata Hold Time From <1>2 During
DS'IN
INTE Output Delay From <1>2
READY Setup Time During <1>2
HOLD Setup Tim. to <1>2
INT,Setup Time During <1>2
(for all mo~.)
Hold Time from <1>2 (READY.
INT. HOLD)
Delay to Float During Hold
iAddress and Oat, Bu.)
Address Stable Prior to WR
Output Data Stable Prior to WR
OutPllt Data Stable From WI'{
Address Stable from wl!!
HLOA to Float Delay
I
WI'{ to Float Delay
Address Hold Time after DBIN
during HLpA

tDSl

20

nsec

tDS2

130

nsec

 CSPEC. subtract 0.3 n'/I!F (from modified delay! if
CL < CSPEC.
'

143

JLPD8080AF
To - O"c to +70°C. VOO - +12V ± 5%. Vca- +5V ± 5%. Vaa - -5V ± 5%. Vss ~ OV. unle .. otherwise
specified.
.,
.
LIMITS
PARAMETER
Clock Period
Clock Rise end Fall Time
1/>1 Pulse Width
1/>2 Pulse Width
Delav 1/>1 to 1/>2
Delay 1/>2 to I/> 1
Delay (/>1 to 1/>2 Leading Edges
Address Output Delay From 1/>2
Data Output Delay From 1/>2
Signal Output Delay From 1/>1.
or 1/>2 (SYNC.
WAIT.
HLOA)

SYMBOL

MIl\!

tCY@
t r , tf

0.32
0
50

tI/>l
tl/>2
tOl
t02
t03

TYP

MAX

UNIT

2.0
25

/Lsec
nsec

"sec
nsec

141\
0
60
60

nsec

nsec

tOA~
too®

150
180

nsec
nsec
nsec

110
130

nsec
nsec

tOF

nsec

m.

OBIN Delay From 1/>2
Delay for Input Bus to Enter
Input Mode
Data Setup Time During 1/>1 and
OBIN
Data Setup Time to 1/>2 During
OBIN
Data Hold Time From 1/>2 During
OBIN
I NTE Output Delay From 1/>2
READY Setup Time During 1/>2
HOLD Setup Time to 1/>2
INT Setup Time During 1/>2
(for all modes)
Hold Time from 1/>2 (READY.
INT. HOLD)
Delay to Float During Hold
(Address and Data !Ius)
Address Stable Prior to WR
Output Data Stable Prior to WR
Output Data Stable From WR
Address Stable from WR
HLQA to Float Delay
WA to Float Delay
Address Hold Time after PBIN
during HLOA
Note. Continued:

®

toc ®
tOF ®
tOI

tOSl

10

nsee

tOS2

120

nsec .

tOH
tiE ~
tRS
tHS

CD
120

nsec
nsec
nsec
nsec

tiS

100

nsec

tH

0

nsec

@

144

90

120

tAW ®
tow ®
two (!)

®

®
2 -IOns.

AC CHARACTERISTICS

J,LPD8080AF-1 .

1:
TIMING WAVEFORMS

""a

® ®

C

CO

'., 'cy~
W

.,

~

1-'0:)1
,S

--1'0"-

-r\

-'.'~
~

A

Q

r~
II

I

I~

f\

1(\

(\
J-----,

c---'l

'0,

(\""------

~ I . ~--+--'

Jr-----..

t-:i

-"o ___________

°1-0 0
SYNC

D8IN

Wli

'H~II~crt II

II

c~j t ~lt!

READY

:

U'Or

I

INT~I~

I[
----I

II

HLDA

j

t--tHF ~

I

to:.l;:J,"""_-;r-___

1

._ _ _ _ _ _ _ _ _ _~._t':H-_.II-_ _
-:l~----

INTE

. Notes:

1 • SYNC of each machine cycle, a status word that identifies the
type of machine cycle is availatJle on the data bus.
Execution times and machine cycles used for each type of instruction are shown
below.
INSTRUCTION

MACHINE CYCLES EXECUTED

CD SPW3 ® SPW3 ®
CD PCR3 @ PCR3 @
PCR5G) SPR3 0 SPR3 0

RST X and PUSH RP

PCRS

All CALL Instructions

PCRS

All Conditional
RETURN Instructions
RET Instructions

PCR4

XTHL

PCR.!

DAD RP

Fl;

INR
INX RP, OCR R;
DCX RP; PCH L;
MOV R, R; SPHL

(i)

cb

SPR3

@

11
SPW3® SPW3 ®

11/17

5/11

SPF'l3

@

10

0 SPR3 (9 SPW3 ®
PCF'l4 CD pcx3 ® PCX3 ®
pcFlIiCD
SPR3

CD PCRS @

CLOCK TiMES
(MIN/MAXI

SPW5 ®

10

5

10

All JUMP Instructions
and LXI RP

PCR4

POP RP

PCM

10

LOA

PCR4

13

PCR3@

STA

CD SPR3 0 SPR3 0
CD PCR3 ® PCR3 @ BBR3 @
PCR4 CD PCR3 @ PCR3 @ BBW3 @

LHLD

PCR4

16

@ BBW3 @

16

LDAX B

CD PCR3 @ PCR3 @
CD BCW3 @
PCR4 CD DEW3 @
PCR4 CD BCR3 @

LDAX 0

PCR4 G) DER3 @

MOV R, M; ADD M;
ADC M; SUB M; SB B M;
ANA M; XRAM;
ORAM;CMPM

PCR4 G) HLR3

INR M and OCR M

PCR4

MVIM

PCR4 G) PCR3

MVI R; ADI; ACI; SUI;
SBI; ANI; XRI; ORI; CPI

PCR4 G) PCR3 @

STAX B

7
7
7
7

@

CD HLR3 @
@

7

HLW3
HLW3

®

10

®

10

7

@

MOV M,R

PCR4 G) HLW3

EI; 01 ADD R;
ADC R; SUB R;
SBB R; ANA R; XRA R;
ORA R; CMP R; RLC;
RRC; RAL; RAR;
DAA; CMA; STC;
CMC; Nap; XCHG

PCR4G)

OUT

PCR4 G) PCR3

IN

PCR4 G) PCR3 @

HLT

PCR4

xx Y Z.

BBW3

PCR4

STAX 0

pT

13

CD PCR3 @ PCRJ @ BBR3 @ BBR3 @

PCR4

SHLD

7
4

@

ABW3
ABR3

CD PCX3 ®

0
®

10
10

l
-"

7

Machi ... Cycle Symbol Definition

®~
... Status we. rd defining type of m.achine

Number of cl.ocks for this machine cycle
f"_'_W~'M",
R "" Read cycle - data Into processor

W

'" Write cycle - data OUt of processor

X '" No data transfer
PC
Program Counter used as address

=

XX

HL
DE

Sp
BS

AS

Registers Hand L used as address
Registers Band C used 8S address
Registers 0 and E used as address

Stack Pointer used as address
Byte 2 and 3 used as address
Byte 2 used: as address

Underlined (XXYZ@» Indicates machine cycle is executed if condition is True.

148

18

INSTRUCTION CYCLE
TIMES

JLPD8080AF
STATUS INFORMATION
DEFINITION

DEFINITION

DATA BUS BIT

SYMBOLS

CD

00

Acknowledge signal for INTERRUPT
request. Signal should be used to gate
a restart or CALL instruction onto
the data bus when OBIN is active.

WO

01

Indicates that the operation in the
current machine cycle will be a
WRITE memory or OUTPUT function
(WO = 0). Otherwise, a REAO
memory or INPUT operation will be
executed.

STACK

02

Indlcates that the address bus holds
the pushdown stack address from the
Stack Pointer.

HLTA

03

Acknowledge signal for HALT
instruction.

OUT

04

Indicates that the address bus contains
the address of an output device and
the data bus will contai n the output
data when WR is active.

M1

05

Provides a signal to indicate that the
CPU is in the fetch cycle for the first
byte of an instruction.

06

Indicates that the address bus contains
the address of aninput.device and the
input data should be placed on the data
bus when OBIN is active.

07

Oesignates that the data bus will be
used for memory read data.

INTA

10 ~

~A

VSS" V,N" Vce

Clock'Leakage

ICL

>10 ~

~A

VSS" VCLOCK" VOO

Data Bus Leakage
in Input Mode

IOL (j)

+10 ~
-10

MA
MA'

VIN:: VCC
VIN '" Vss + 0.45V

Address and Data Bus
Leakage During HOLD

IFL

::~ ~

MA

VAOOR/OATA - VCC
VAOOR/OATA' VSS + O.45V

Notes:

152

CD

There are no internal pull-up resistors on the inputs.

@

Minus (-) designates current flow out of the device.

JLPD8080A
CAPACITANCE

Ta = 25°C; VCC = VOO;' OV; VBB = -5V
LIMITS
PARAMETER

SYMBOL

Clock Capacitance
Input Capacitance
Output Capacitance

MIN

TYP

MAX

UNIT

TEST CONDITIONS

17

25
10
20

pF
pF
pF

fc =1 MHz
Unmeasured Pins
Returned to VSS

C

50

25

'H,
'FO
'AW

'ow

OutPUt Data Stable Prior to WR
Output Data Stable j:rom wrt
Address Stable Front
HLoA to Float Oelay

twn

wn

twA
'HF 2
twF 2
'AIf@

I WR to Float Delay
Addrep Hold Time After OBIN During HLoA

ns

140

ns
n.
n.
ns
n.
ns
ns
n.
ns
ns
n.
ns
n.
n.
ns
n.
n.
ns

200
120
140
120
0

Hold Time F,om .2 (AEAOY, INT, HOLD)
Address Stable PrioHO W1!I

120

30
5
50

'240

Oaley to Floet Ouring Hold IAddress and Data Bus)

220

ns
ns
ns
ns
ns
ns
n.
ns

'OF

tHS

AC CHARACTERISTICS

TEST CONOITIONS

~s

200

tRS¢"
~IS

UNIT

MAX

2 + tct>2 + tfct>2 + t02 + trct>1

> tCY Min.

TYPICAL..:l. OUTPUT DELAY VS . .:l. CAPACITANCE

.... +20

..:
~

+10

..J

w

o

55

0
-10

0_20
 CSPEC, subtract 0.3 ns/pF (from modified
delay) if CL < CSPEC.
1110 restric1ions.

®

tAW - 2 tCY - t03 - trct>2 -140
tD3 ..; trct>2 '"' 170
If not HLDA, two = twA = t03 + trct>2 + 10 ns. If HLOA, two = tWA = twF.

@

tHF

@

twl= - t03 + trct>2 - 10 ns.

 tow = tCY -

154

=t03 + trct>2 -

50 ns.

1:

TIMING WAVEFORMS @ @

--;r'-~V

.

.

~
~'o3+1

A,e-Ae

~

~.

--

r

1. ___

-~

-..

'0,

1--

"

-

.f!;'N

--

.~

DBlN

'oc

"-

..\.

,tAW

-~

~--

I- ---l'wA

1-'00--1

'oHI-

~ 1--- r-'ow

'0'24

-

....--.. '.0 I-

--- -- r--_
- ----- --

__.1

- --- -- - 1---..J'wo
DATA OUT

-

~

'oc./-

1
1-'0....

----------------------

. ,-

. (2)1
- tRI~
-

.. - --

WAIT

'ocHOLD

..

'H~
(2)1 X

' :..::.:r
1

'1-

---

I-tAH

-- +-V.F_

I-- 'oc

'oc~

1-'•• -0

1

- r0

L.X

'H ..

~ ~,=-

HLDA

•

I

I

1--'-' ......

o
CIa
o

..JL.-

I

1-'0.-1
~'"

CIa

Jr--\

-- --- ---- --- --

--- -----:- --.,.
-+.: : - toS1,-r- ~
7

....--

10-----0

.

-'oA--l

SYNC

READY

------

F\

~

'02 l-

--'00""1
.~

D,-Oa

1111

Jf\

\

J~

\.

'V
C

-.. '0, I-

-

.NT

-

I

'oc I--

X0 II,

-

"'~I~
....
WR

~ ~-~------------...

,

 This timing diagram shows timing relationships only; it does not represent any specific machine cycle.

e> Timing measurements are made at the following reference voltages: CLOCK "1" =B.OV, "0" = 1.0V;
INPUTS ".1" = 3.0V; "0" =O.BV; OUTPUTS ";I" =2.0V, '~O" =O.BV.

J .-_~-.,;;;-::.

,J.'PD8080A
INSTRUCTION SET TABLE
FLAGS'

MNEMONIC'

D1DoDsD4p:' D2 D,
MOVE
MOVd..

MOVM..
MOVd,M
MVld,DB

MYI M.DB

Clook
Cycl.1

INSTRUCTION CODE'

DESCRIPTION

""118r

Mow rlgilter to
Mow regIa.r to memory
Mow memory to ........r
Mowltnrnldlmtoregl.1IIf
Mow Immediate to memory

••
••• ••

d
1
d
d
1

1
1
1

d
1
d
d
1

d

•
•
d
d

••• •••
••

Increment register
Decrement register

IHRM

InQ'emen'memory

DCRM

Decrement memory

d
d
1

d
d
1

1
1
1

1

1

•

1
1
1

1

1

1

ADe,

SUB.
sse.

ANA.

XRA.
ORAl
CMP.

1

Addregil"" toA
Add register to A wid!
""Y

1
1

Subtract register from A
Subtract .......r from A
with borrow
AND fllllitter with A
ExcluliveORregil1lr
with A
OR regilterwith A
Compare register with A

1
1
1
1
1

• ••
•• •• • •
•• • • •,
••• • •
0

1

1

1

1
1
1
1

1

1
1

1

I.I.

··· ··· ···
·· ·· ··
··· ··· ··· •
4
4
4

4
4

4
4

AW - MEMORY TO ACCUMULATOR
ADDM
ADCM
SUBM
seaM
A~AM

XRA M
ORAM
CMPM

, •• •• • •
•• •
,••
• ••
•• • •
•
1

Addmtmorv to A
Add memorV to A witfl
ICIIrrv
s.btr.ct I"MtI'I()ry from A
Subtract m.-nory from A
witfl borrow
AND men::aory with A
EJlclu"VI OR mllmory
witflA
OR memory with A
Compere memory with A

0

1

1

1

1

1

1

1
1
1

1
1
1

1
1

1

1

1
1

1
1

1

1
1

1
1

1

1
1
1

1
1
1

1

•

••

••
•••

1
1
1
1
1
1
1
1

ALU - IMMEDIATE TO ACCUMULATOR

ADIDB
ACI D8
SUI D8
sel DB

1

1

1
Subtract Immediate from A 1

1
1

Add Immediate to A
Add Immediate to A with

....,

ANI OS
XRI08'

Subtract immadi8tll from
A with borrow
AND Inmadilltll with A
EJCdu.ive OR immediate

1
1

1
1

ORI08
'CPI08

"''''A
OR Immediate with A
Camperllimmedlate with A

1
1
1

1
1
1

•••
•• • •
•••
••
1

1

1

1
1

1

1
1

1

1

1

1
1

1

1

1
1
1

1
1
1

1

1
1
1

1

1

1

•

••

••
••
•

1
1
1
1
1
1
1
1

ALU-ROTATE

RLC
RRC
RAL
RAR

Rotate A taft. MBa to
Clrfy(8.bitl
Rofate A right. LSa to
ICIIrry(B-bltl
ROIIte A left through
cerrv 19-bit)
R018te A r~t through
any (9-bitl

•••••
••••
••• •
•••

Jump uncondldonal
Jump on not ZIIro
Jump on UfO
Jump on no CIIrry
Jump on carry
Jump on paritv odd
Jump on parity even
Jwnp on positive
Jump on minua

1
1

1

1

1

4

1

1

1

1

4

1

1

1

4

1

1

1

1

4

1
1

JUMP
JMPADDR
JNZ ADDR
JZADDR
JNCADOR
JCADDR
JPOADDR
JPEADDR
"ADDR
JMADDR

I.I.I.
I.
I.I.I.I.
I.

• ••
, •• ••• • •• ••
•• • •• ••• , •••
•, • •• ••
• •
,,•• •
, , •• •• • •• ••
• • ••
, , • •• • ••• •••
• • ••
,,
,,•• ••
, ,, •• •• • •• •• • "
, • , • •• •• ••
, •• • •• •• ••
• •• •• ••

1
1
1
1
1
1

1
1
1
1

1

1

1

1
1
1
1

1
1
1
1
1

1

1

1

1

1

1

1
1

1

1
1
1

1

CALL

CALLADDR
CNZADDR
CZADDR
CNCADDR
CCADDR
CPOADDR
CPEAODR
CPADDR
CMADDR

Call Unconditional
Call on not zero
Calion taro
Call-on noCllny
Cell'onCllt'ry
Call on parltv odd
Call on paritv even
Cellonpae!tlw
Call on minus

1

1

1

1
1
1

1
1
1

1

1

1

1
1

1
1
1
1

1

1

1
1

1

1
1
1
1
1
1
1
1
1

1

LXts,ole

1
1
1

ALU - REGISTER TO ACCUMULATOR

ADD,

DESCRIPTION

11

LXI 0,016
LXI H,016

. Load Immediate regilta'
pair Be
l.oed Immediate regi••r
pairOE
Loed immediate regilter

156

Retum
Return on not taro
Retumon zero
Retum on no CIIrry
Retum on ceny
Return on paritv odd
Retum on paritv even
Return on politi",
Return on mlnUil

1

1

1

1

1
1
1
1

1
1
1
1

..

···· ····....
· ··· ..
····...·.
·.
•

0

•

0
0

·····.·.
··.. ··
· . ·· ··
·· ·· ···
··.·· ····
···.·· ······
··..···
·· .····· ·
•

..

11/17

11117

1

1

0

1

1
1

1

1

1
1

1

1

··
·
·

1

1
1

5/"
5/"
5/"
5/"
5/"
5/"
5/"
5/"

I.I.
I.I.

PUSH
PUSH B

Push register pair Be

on stack
Pu.... regilter peir DE

1

1

PUSH 0

onttack
Push register pair HL
on Itack
Push A and flap on flack

1

1

PUSH H
PUSHPSW

1

1

1

1

•••
• •
• ••
1

1
1

1

1
1
1
1

•
•
••

1
1
1
1

POP
POpa

Pop rat1ltel' pair Be
off 'tack

POPD

Pop 'llgiitar pair DE

POPPSW

offltack
Pop register pelr L
offltack
Pop A and flags off .tack

DADB
DADO
OAOH
DADSP

Add BC to HL
AdelDE to HL
Add HLto HL
Add Stack Pointer to HL

INXB
INXD
INXH
INX SP

Incretnllnt BC
IncrementOE
IncrllfTlllntHL
Increment Stack Pointar

DCXB
DCXD
DCXH
OCXSP

Decrement BC
Dtcremant DE
Decrement HL
Decrement Steck Pointer

STAXa
STAXD
LDAXB
LDAXD

Stor. A at ADDR
Store A lit ADDR
Load A at ADDR
Load A at AODR

POPH

H

1

1

1

1

1
1

1
1

"
"
""

I.
I.I. ... ·

•••••
• • • • ,.
, •• •• •• ,
1

1
1

1

1

0

1

DOUBLE ADD

•• • •• •
•• •• •
0

1

1
1

1

1
1
1
1

•• •
•• ••
0

1
1
1
1

1

1

···
·

""
""

INCREMENT REGISTER PAIR

--

•• •• •• • •• ••
•• •• • •• ••
1
1

1

1

1

1

1

1
1

1
1

1
1

1
1

1

1

•
••
5

DECREMENT REGISTER PAIR

0
0
0

1

1

Load immediate Steck
Poln_

0
0
0

1

1

•• •• •• •
•• •• •
1
1

1

1

1

1

1
1

••
••

1

•
•
5
5

REGISTER INDIRECT
In 8
In 0
in a
in D

• •• •• • •• ••
•• •• •• • ••
1

0

1

1
1

1
1

1
1

••
••

1
1
1
1

••
••

13
13
'16
16

DIRECT

•• ••
••
• •• •• • •••

STAADDR
Stare A direct
LDAADDR
Load A direct
SHLOADDR Store HLdirect
LHLOADDR Load HLdirect

1
1
1
1

0

1
1

1

1

1
1
1
1

MOVE REGISTER PAIR

XCHG
XTHL
SPHL
PCHL

EJCChange DE and HL
regl.... pal,.
EXchange top of steck
and HL
HL to Stack Pointer
HLto Program
Counter

1

1

1

1

1

1

1

1
1

1

1

1

• •
• • •• •
• ••
1

1

1

Input
Output
Enebteinterruptl
Ditable interrupts
R......

1

1
1

1
1

1
1
1
1
1

•

1

11

1

4

1

1

•

.'

•• • •
• ••
1

1

1
1
1
1

A

A

A

1

1

1

INPUT/OUTPUT

INA
DUTA
EI
DI
ROTA

1

1

1

1
1
1
1
1

1
1
1
1
1

1
1
1
1

1
1
1
1

1
1
1
1

1

1

11/17

11/17
11117
11/17
11/17
11117

1

1

Do

•••••••

••• •••
•• ••••
••
•••

pairHL
LXI8P,D18-

I.I.
4

' 4

"

MISCELLANEOUS

CMA

Camp_mentA

STC
CMC
DAA
NOP
HLT

Sol.....,
Compl,mant carry
Declntel adjust A
Na-operation
Halt

RETURN

RET
RNZ
RZ
RNC
RC
RPO
RPE
RP
RM

t5 ffi i 15~

Qock
Cycles' ill N ..

INSTRUCTION CODE I

LOAD REGISTER PAIR

·· ·· ••·· I.•
1
1
1

~,.

MNEMONIC'

D7Do D5 D4D:iDaDl

•• •
•• ••• • •
d
d

it ~
li5~~~

i

'FLAGS 4

,.

Do

INCAEMENTIOECREMENT
tHRd
DCRd

~

~

•• •
•• •• •
1
1

1

1
1

1

•• •• • •• •• • • •
•
• •

NOTES:
I Op..and Symbol. UIId
A • 8-bft
or eJlpraesion
1-lOUrceregilter
d = dllltination regmer
PSW .. Proceaor &taws Word
SP - Stack Poin..r
08 - &-bit deta quantltv.IIJlpreulon. or •
constant. alweVI B2 of inltrucdon
016 -tB-bit ct,tequantfty. expl'llllkmyor
constant. alwayl 8382 of inttruction
ADOR .. 1&-bit Mamorv eddrest exprnsion

add,..

1

1

1

1

1

•

4
4
4
4

1

.. . ·
1

tv

2dddarSH-OOOB-OOt C-010D-01t El00H-10t L-l10Memory-111 A.
:lTwopolliblllc:yde.im.. (5/11) indicate
Inttructlon cyd. dependent on condition
fl ....
flag affected
= flag not affected

• • Ie

0" flag raut
l-flagset

JLPD808()A
INSTRUCTION SET
The instruction set includes arithmetic and logical operators with direct, register, indirect, and immediate addressing modes. These
.
instructions operate exactly like the "PDS080AF except as noted.
In addition to the four testable flags, the "PDSOSOA has two more flags (ACY, SUS) that are not directly testable. Th4W are used for
m",ltlple precision arithmetic operations, particularly with t~e DAA instruction. The Auxiliary Carry flag is set if the last ins.truction
resulted i·n a carry or a borrow from bit 3 into bit 4; otherwise it is resef. The Subtract flag is set if the last instruction resulted in a
subtract operation being performed; it is reset if an add operati!)n was ~rformed. Also, arithmetic flags ar~ not affected by logical
instructions.
'
,,
.

DATA AND INSTRUCTION FORMATS
D~ta in the I'P08OS0A is stored as S-bit binary integers. All data/instruction transfers ·to the system data bus are in the following format:

I~I~I~I~I~I~I~I~I
MSB

DATA WORD

LSB

Instructions are ohe, two, or three bytes long. Multiple byte instructions must be stored in successive locations of program memory.
The address of the first byt~ is used as the address of the instruction.
One Byte Instructions

107106105104103102101
I_DO.I OP CODE
.
"
.
.
.
.
.
Two Byte Instructions
I071 061 051 04 103102101 IDO I OP CODE
107106105104103.102101 1DO 1OPERAND
Three Byte Instructions

•

TYPICAL INSTRUCTIONS

Register to ·regist~r. memory

r~fer8nce.

arithm,tic o~ logi~a~
rotate. "turn, pUSh, POP. eriable.

or disable inter'rupt instructions
Immediate mode or 1/0 inst'ru~·
tions
Jump, can or direct load and"
store instruction$
.

1071 061 051 04.1 031021 011DO 1OP CODE
1071 061 05104 103102101 IDO I LOW ADDRESS OR OPERAND 1
1071 06105104103102101 IDO I HIGH ADDRESSOR OPERAND 2
INSTRUCTION CYCLE TIMES

One to five machine cycles (M1 - Ms) ~re required to execut~ an instrflct!on. Each machine cycle involves the transfer of an instruction
. or data byte into the processor or a transfer of a data byte out of the processor (the sole exception being the double add instruction). The
first one, two or three machine cycles obtain the instruction from the memory or an interrupting I/O controller. The re';'aining cycles are
used to execute the instruction. Each machine cycle requires fr~m three to five clock times (T1 - TS). During tP1 SYNC of each machine
cycle, a status mrd that identifies
.
. . the type of machine cycle is
"- available on the
, data bus.
,

,

Execution times and machine cycles used for each type of instruction are shown below.
INSTRUCTION

MACHINE CYCLES'ExeCUTED
PeRS

AnCALLlnstructior\S

PCRS

AlIRETlnstruc:tlonl

PCRS 1 SPA3 -4 SPR3 •

XTHL

PeR5

CD SPA3 <9 SPW3

PCRS

CD

PeR4

CD PCR3 @

CD PeR3

2 PCR3@ SPW3

®

SPW3 5

SPW3@

PCHL
All JUMP Instructions

POPRP

CD SPR3 @ SPR3@
CD PCR3@ PeR3 @ 88R3 0
CD PCR3 0 PeR3 ® BSW3 ®
PCR4 CD PCR3 @ PeR3 ® BSR3 ® BSR3 (i)
PCR4 
PCR4 CD SCR3 
SBe R; ANA R; XRA R;
ORA R; CMP R; ALC;

®

PCR.

LOA

STA
LHLD

PCR3

pcR4

11/17

5/11

5 SP~3 •

DADRP

and LXIRP

(MIN/MAX)

CD SPW3 ® SPW3@

RST X I1Id PUSH RP

INR R; INX RP,
DCR R; DCX RP;

CLOCK TIMES

3

3

I

"

,.
,.
,.
13

13

1T

"-,,iN Cye" Symbol Definition

:1"". ,...

xx y z @)...tStillUSworddefininttvpeofm.ehine

T

,.,.

XXlHL

Number ofseloek,
for this
mechin. eye'. ...... Wo.d
"".".
R' "R.1d cycl. - d.t. into ",,«enD'
W '" Write cycl. - data out ot protestOr
)( = No d.te 'tr.n,fer
PC .. Pro••m Counter uMCI . . .dd,...

DE
ac

SP
BB
AB

1,1_ ...

R8(tIttlirs H .nd L
dd,....
R.gister, B end C uled . . .dd,_
Registers 0 .nd E uled . . .ddress
$tIIC'k POintllr used • •~,",
Byte 2 .nd 3 used . . .ddress

Bv"!- 2 uHCf .. ~r...

Uf1\:I_UnedCXXYZ@l i~diC_ m.chin. cycle i' IPecuMd if condition" Jr .....

CD

A'Re: AAL; RAft;

DAA; CMA; STC;
CMC; NOP; XCHG. SPHL

OUT

PCR.

'N

~R4

HLT

PCR'

CD PeA3 ® A8W3 B

tc
INTERRUPT
FLIP-FLOP

PRIORITY
COMPARATOR

Q~--~--------------~

tc
INTE
ClK

INTERRUPT
DISABLE
FLIP-FLOP

7 }---------------------------------'
6 } - - - - -______________________________

~

General
The J-lPB8214 is an LSI device designed to simplify the circuitry required to
implement an interrupt driven microcomputer system_ Up to eight interrupting
devices can be connected to a J-lPB8214, which will assign priority to incoming
interrupt requests and accept the highest_ It will also compare the priority of the
highest incoming request with the priority of the interrupt being serviced. If the
serviced interrupt has a higher priority, the incoming request will not be accepted.
A system with more than eight interrupting devices can be implemented by interconnecting additional J-lPB8214s. In order to facilitate this expansion, control
signals are provided for cascading the controllers so that there is a priority established among the controllers. In addition, the interrupt and vector information
outputs are open collector_
Priority Encoder and Request Latch
The priority encoder portion of the J-lPB8214 accepts up to eight active low
interrupt requests (RO-R7). The circuit assigns priority to the incoming requests,
with R7 having the highest priority and RO the lowest. If two or more requests,
occur simultaneously, the ).tPB8214 accepts the one having the highest priority.
Once an incoming interrupt request is accepted, it is stored by the request latch a'nd
a three·bit code is output. As shown in the following table, the outputs, (AO-A2)
are the complement of the request level .(modulo 8) and directly correspond to the
bit pattern required to generate the one byte RESTART (RST)instrc.uction1>
recognized by an 8080A. Simultaneously with the AO-A2 outputs, a system
interrupt request (INT) is output by the J-lPB8214. It should be noted that incoming
interrupt requests that are not accepted are not latched and must remain as an
input to the J-lPB8214 in order to be serviced.
160

FUNCTIONAL
DESCRIPTION

,.,. PB821'4
FUNCTIONAL
DESCRIPTION
(CONT.)

RESTART GENERATION TABLE
D7

D6

D5

D4

D3

D2

Dl

DO

RST

1

1

A2

Al

AO

1

1

1

RO

7

1

1

1

1

1

1

1

1

Iii

6

1

1

1

1

0

1

1

1

1

PRIORITY
REQUEST
LOWEST

I

R2

5

1

1

1

1

1

4

1

1

1

0
0

1

liJ

0

1

1

1

R4

3

1

1

0

1

1

1

1

1

R5

2

1

1

0

1

0

1

1

1

R6

1

1

1

1

1

1

O·

1

1

0
0

1

R7

0
0

0

1

1

1

HIGHEST
'CAUTION,

RST 0 will vector the program counter to location 0 (zero) and
invoke the same routine as the "RESET" input to B080A.

Current Status Register
The current status register is designed to prevent an incoming interrupt requeSt from
overriding the servicing of an interrupt with higher priority. Via software, the priority
level of the interrupt being serviced by the microprocessor is written into the current
status register on BO...:.B2' The bit pattern written should be the complement of the
interrupt level.
The interrupt level currently being serviced is written into the current status register
. by driving ECS (Enable Current Status) low. The tlPB8214 will only accept interrupts
with a higher priority than the value contained by the current status register. Note
that the programmer is free to use the current status register for other than as above.
Other levels may be written into it. The comparison may be completely disabled by
driving SGS (Status Group Select) low when ECS is driven low. This will cause the
tlPB8214 to accept incoming interrupts only on the basis of their priority to each
other.
Priority Comparator
The priority comparator circuitry compares the level of the interrupt accepted by the
priority encoder and request latch with the contents of the current status register.
If the incoming request has a priority level higher than that of the current status
register, the INT output is enabled. Note that this comparison can be disabled by
loading the current status register with SGS=O.
Expansion Control Signals
A microcomputer design may often require more than eight different interrupts. The
tlPB8214 is designed so that interrupt system expansion is easily performed via the
use of three signals: ETLG (Enable This Level Group); ENLG (Enable Next Level
Group); and ELR (Enable Level Read). A high input to ETLG indicates that the
tlPB8214 may accept an interrupt. In a typical system, the ENLG output from one
tlPB8214 is connected to the ETLG input of another tlPB8214, etc. The ETLG of
the tlPB8214 with the highest priority is tied high. This configuration sets up
priority among the cascaded tlPB8214's. The EN LG output will be high for any
device that does not have an interrupt pending, thereby allowing a device with lower
priority to accept interrupts. The ELR input is basically a chip enable and allows
hardware or software to selectively disable/enable individual tlPB8214's. A low on
the ELR input enables the device.

161

",PB8214
Interrupt Control Circuitry
The j.lPB8214 contains two flip-flops and several gates which determine whether an
accepted interrupt request to the j.lPB8214 will generate a system interrupt to the
8080A. A condition gate drives the 0 input of the interrupt flip-flop whenever an
interrupt request has been completely accepted. This requires that: the ETlG
(Enable This level Group) and INTE (Interrupt Enable) inputs to the j.lPB8214 are
high; the ElR input is low; the incoming request must be of a higher priority than
,the contents of the current status register; and the j.lPB8214 must have been enabled
to accept interrupt requests by the clearing of the interrupt disable flip-flop.

FUNC.TIONAL
DESCRIPTION
(CONT.)

Once the condition gate drives the 0 input of the interrupt flip-flop high, a system
interrupt (INT) to the 8080A is generated on the next rising edge of the ClK input
to the j.lPB8214. This elK input is typically connected to the 1;2 (TTL) output of an
8224 so that 8080A set-up time specifications are met. When INT is generated, it
sets the interrupt disable flip-flop so that no additional system interrupts will be
generated until it is reset. it is reset by driving ECS (Enable Current Status) low
thereby writing into the current status register.
It should be noted that the open collector INT output from the j.lPB8214 is active
for only one clock period and thus must be externally latched for inputting to the
8080A. Also, because the INT output is open collector, when j.lPB8214's are
cascaded, an INT output from anyone will set all of the interrupt disable flipflops in the array. Each j.lPB8214's interrupt disable flip-flop must then be
cleared individually in order to generate subsequent system interrupts.

TYPICAL IlPB8214
CIRCUITRY

';"60

~B1

"--+82

ENABLE
'-------'-< SGS
CURRENT _ _!:-'23:,qECS
STATUS
~EL~R~__~
IFROM,I/O PORT DECODERI
Y11
GND

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . O°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125°C
All Output and Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7 Volts
All Input Voltages . . . . . . . . . . . _ . . . . . . . . . . . . . _ ...... -1.0 to +5.5 Volts
Output Currents .. _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions ~bove those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

162

ABSOLUTE MAXIMUM
RATINGS*

p.PB8214
DC CHARACTERISTICS

Ta = oOe to +7ooe. vee = 5V ± 5%
PARAMETER

SYMBOL

Input Clamp Voltage (all inputs)
Input Forward Current: ETLG input
all other inputs
Input Reverse Current: ETLG input
all other inputs
Input LOW Vol,tage: all inputs
Input HIGH Voltage: all inputs
Power Supply Current
Output LOW Voltage: all outputs
OutPUt HIGH Voltage: ENLG output
Short Ci"rcuit Output Current: ENLG output
Output Leakage CUrrent: rRT and P;u A2

CAPACITANCE

®

LIMITS
TYP.(j)

Vc
IF

'.15
-.08

IR
VIL
VIH
ICC
VOL
VOH
lOS
ICEX

UNIT

MAX.
-1.0
-0.5
-0.25
80
40
0.8

2.0
90
2.4
-20

.3
3.0
35

TEST CONDITIONS

V
mA
mA
/JA
/JA
V
V
mA
V
V
rnA

130
.45
-55
100

IC=-5mA
VF-0.45V
VR=5.25V
VCc=5.0V
VCC=5.0V

C2>
10L=lOmA
10H= lmA
VOs=OV. VCC-5.0V
VCEX=5.25V

/lA

Ta= 25°C
PARAMETER

AC CHARACTERISTICS

MIN.

SYMBOL

MIN.

LIMITS
TYP.Q)

MAX.

TEST CONDITIONS

UNIT

Input Capacitance

CIN

5

10

pF

VBIAS=2.5V

Output Capacitance

COUT

7

12

pF

VCC=5V
f=1mHz

Ta = oOe to +7ooe. Vee = +5V ± 5%
PARAMETER

SYMBOL

MIN.

LIMITS
TYP.(j) ,MAX.

UNIT

TEST CONDITIONS

ICY
tpw

80

50

ns

Input p'ulse

25

15

ns

amplitude: 2.5 Volts

tlSS
tlSH

16
20

12
10

ns
ns

ETlG Setup Time to ClK

tETCS®
tETCH®

ns
ns

ECS Setup Time to eo<:
ECS Hold Time After ClK
ECS Setup Time to ClK
ECS Hold Time After ClK

tECCS®
tECCH@
tECRS@
tECRH@

25
20
80

12

ETlG Hold Time After ClK

ECS Setup Time to ClK
ECS Hold Time After ClK

tECSS®
tECSH®
tDCS®
tDCH®
tRCS@
tRCH@

elK Cycle Time

CLR. ECS.

INT Pulse Width
INTE Setup Time to ClK
INTE Hold Time after ClK

SGS and

BO-B2 Setup Time to 1:0<
SGS and BO-B2 Hold Time After ClK
RO-R7 Setup Time to ClK
RO-R7 Hold Time After ClK
TNl Setup Time to ClK
ClK to INT PropagatiQn Delay
RO-R7 Setup Time to INT
RO-R7 Hold Time After INT
RO-R7 to AO-A2 Propagation Delay·
ElR to AO-A2 Propagation Delay
ECS to AO-A2 Propagation Delay
ETlG to Ao-A2 Propagation Delay
SGS and Bo-B2 Setup Time to ECS

tiCS'
tCI
tRIS®
tRIH@

10
50

ns
ns

70

ns

70

ns
ns

50

ns
ns
ns

Speed measurements
taken at the 1.5 Volts

ns

levels.

0
110
0
75
0
70
0
90
0
. 55
10
35

Output loading of

55
·35
15
0

tECA
tETA

ns

35

70

ns
ns

15

tREN

10
45

ElTG to EN lG Propagation Delay

tETEN

20

ECS to ENlG Propagation Delay
ECS to ENlG Propagation belay

tECRN
tECSN

85
35

Sll"S" and Bo-"B2 Hold Time After J:CS
lfo-l!7 to ENlG Propagation Delay

Notes:

Typical values are for T a==25° C.

ns
ns
100
65
.120

10

15 mA and 30 pF.

ns
ns

40
.100
15

tDECS®
tDECH@

25

20
BO

tRA
'tELA

Input riSe and fall

times: 5 ns between
rand 2 Volts

ns
ns

ns
70
25

ns
ns

90

ns
ns

55

\

VCC=5.0V

BO-B2. SGS. ClK. RO-R4 grounded. all other inputs and all outputs
open.
This parameter is periodically sampled and not 100% tested.
Required for proper operation if INTE is enabled during next clock pulse.
These times are not required for proper operation but for desired
change in interruPt flip-flop.
Required for new request or status to be properly loaded.

163

J:LPB8214
~
____ - - - 1

--------..,.-- -- ---

---,l _____ J\
1
---------_J~----'1\...""--"",,\~---

t'RCH

tRCS

...
ETLG

_-----

--

tAIS

tAIH

I

"\

'--------..,.-

--------Xex----- ----------tETes

INTE

TIMING WAVEFORMS

r

----------

tETCHI

e
------c~ tx=x
-J

'\ r----J

tDecs

tISS~ 1--1

"\

ItDEC~

I'-

I

'0,

,

toes

--

------- ---L tECSS

J

t::H

tECSHJ

I,

,I

~ ItECRH

tECRS

teces

tP\\I

'ISH

tEecH

tCY

W

W

~lttP\\l

tCI

tiCS

r-----"\
__________ ...1

-- ----- --- ------- ---- --- -- ---- ------,
tRA

tECSN

*--'!'

tETA

---- -------

tELA

tECA

-- --- --

w=1'----

I - - - tP

r- --- --- -------'
tETEN

-'I
I

tREN

J

~---------

-----------------,.1"'-___________________ _

ENLG _ _ _ _ _ _ _ _ _ _ _ _ _

Vee

~T~::
TEST CIRCUIT

PACKAGE OUTLINE
ILPB8214C

ITEM

MILLIMETERS
33MAX.

2.53
2.54

D.S±Oo'
27.94

I.'

H

I
J
K

3.2 MtN.
0.5 MIN.
5.22 MAX.
5.72 MAX.

15.24
1~2

M

o.25±Q.l

INCHES

t.28
O.t
0,
.02± 0.004

l.t
0.059
0.125 MI~.
0.02 MIN.
P.205MA .
O.2~5 AX.
0••
0.52
0.01 ± 0.004

SP8214-2-77-GN-CAT

164

me.

fLPB8224

CLOCK GENERATOR AND DRIVER FOR
8080A
PROCESSORS ' .
. .
.
,

DI:SCR IPTION

The IAPB8224 is a single chip clock generator and driver for 8080A processors.
The clock frequency is determined by a user speCified crysta! and is capable of
meeting i:he timing requirements of the entire 8080A family of processors. MOS
and TTl- level clock outputs are generated.
Additional logic circuitry of the IAPB8224 provides signals ,for power-up re.set. an
advance status strobe and properly synchronizes the ready signal to the processor.
This greatly reduces the number of chips ne!!ded for 8080A systems.
The IAPB8224 is fabricated using

fEATURES

NEC'~ Schottky

bipolar process.

• Crystal Controlled Clocks
•
•
•
•
•

Oscillator Output for External Timing
MOS Level Clocks for 8080A Processor
TTL Level Clock for DMA Activities
Power-up Reset for 8080A Processor
Ready Synchronization

• Advanoed Status Strobe
• ~educes System Package Count
• Available in 16-pin Cerdip and Plastic Packages

PIN CONFIGURATION

RESET

.REsiN

PIN NAMES

VCC
XTAL 1

RDYIN

XTAL2

READY

TANK

SYNC

/

OSC

RESIN

Reset Input

RESET

Reset Output

RpYIN

R8Jldy Input

ReADY
SYNC

ReadY Output

<1>1

1

STSTB

<1>2

GND

} processor
Clocks

2 (TTL)

oi>2 CLK
(TTL Levell

Vcc

+5V

VDD
GND

+12V
OV

REV/1

165

Clock Generator
The clock generator circuitry consists of a crystal controlled oscillator and a
divide-by-nine counter. The crystal frequency is a function of the 8080A
processor speed .and is basically nine times the processor frequency. i.e.:
Crystal frequency

p.PB8224
FUNCTIONAL DESeR IPTION

=~

tCY
where tCY is the 8080A processor clock period.
A series resonant fundamental mode crystal is normally used and is connected
across input pins XTAL 1 and XTAL2. If an oyertone mode crystal is used. an
additional LC network. AC coupled to ground. must be connected to the
TANK input of the PPB8224 as shown in the following figure.
LC_(1~2
r----- -."I FOR
-OVERTONE
2ii1")
CRYSTALS ONLY

I
I

L

I

I

I

I

I

I

1'1

°1

I

r-

I

I
I

_,3-10pF

I

I-

L-

-

IIONLY NEEOED
- " ABOVE 10 MHz)

I

.... ------- .. 13

14

15

A~~A~TAL111

The formula for the LC network is:
LC

=(~r

where F is the desired frequency,of oscillation.
The output of the ,oscillator is input to the divide-by-nine counter. It is also
buffered and brought out on the OSC pin. allowing this stable. crystal controlled
source to be used for derivation of other system timing signals. The divide-bynine counter generates the two non-overlapping processor clocks. C/li and 1/12.
which are buffered and at MOS levels. a TTL level C/l2 and internal timing signals.
The C/l1 and C/l2 high level outputs are generated in a 2-5-2 digital pattern. with C/l1
being high for two oscillator periods. cP2 being high for five oscillator periods. and then
neither being high for two oscillator periods. The tTL level cP2.cP2 (TTL). is normally used
for DMA activities by gating the external device onto the 8080A bus once a Hold
Acknowledge (HLo'A) has been issued.
Additional Logic
In addition to the clock generator circuitry. the PPB8224 contains additional logic
to aid the system designer in the proper timing of several interface signals.
The ffifB signal indicates. at the earliest possible moment; when the status
signals output from the 8080A processor are stable on the data bus. STSTB is
designed to connect directly to the PPB8228 System Controller and automatically
resets the IJPB8228 during power-on Reset.
The RESIN input to the IJPB8224 is used to automatically generate a RESET
signal to the 80~A during power initialization. The slow rise of the power
supply voltage in an external RC network is sensed by an internal Schmitt
Trigger. The output of the Schmitt Trigger is gated to generate an 8080A compatible RESET. An active low manual switch may also be attached to the RC '
circuit for manual system reset.
The RDYIN input to the IJPB8224 accepts an asynchronous "wait request"
and generates a READY output to the 8080A that is fully synchronized to
meet the 8080A timing requirements.
166

ILPB8224
BLOCK DIAGRAM

ABSOLUTE MAXIMUM
RATINGS*

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . o°c to +70°C
Storage Temperature . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6SoC to +150°C
All Output Voltages (TTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.5 to +7 Volts
All Output Voltages (MOS) . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0 to +13.5 Volts
All Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5 to +7 Volts
Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7 Volts
Supply Voltage VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +13.5 Volts
Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 rnA
COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or

any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device

reliability.
*Ta= 2SoC

DC CHARACTERISTICS

Ta"

tfc to

+looe; vee" +SV t5%; voo" +12V ±5%

PARAMETER

SYMBOL

LIMITS

MIN

TV.

UNIT

TEST CONDITIONS

MAX

mA

VF '" QA5V

"A

VR" 5.25V

'F

-0.25

Input Leakage Current

'R

10

Input Forward 'Clamp Voltage

Ve

1.0

v

Ie'" -5 mA

Input "low" Voltage

Vil

O.S

V

Vee'" 5.0V

Input "High" Voltage

V'H

V

Reset Input

InPtn Current Loading

2.6
2.0

RESIN Input Hysterests

VIH-Vll

Output "low" Vohage

All Other Inputs

0.25

Vee'" 5.0V

VOl

0.45

V

($1, $2), Ready, Reset,

mrs

IOL '" 2.5mA
0.45

V

All Other Inputs
IOl'" 15mA

OutPut "High" VOltage

VOH

.,.",

9.'

REAOY, RESET

IOH '" -1001lA

3.6

All Other Outputs

'se CD

Output Short Circuit Current

2.'
-10

-60

V

IOH '" -l00IlA

V

IOH =-1 mA

mA

IAlilow Voltage Outputs Only 1
Power Supply Current
P~r

Note:

Ta

Supply Current

Va -OV
Vee

'ee

115

'DO

15

=

5.0V

mA
mA

2 Pulse Width

t$2

5tCY

I'/Jl to ¢2 Delay

t01

¢2

t~

411 Delay

9

UNIT

TYP

2tCY

tPl to ¢2 Delay

t03

2tCY
-g-

411 and CP2 Rise Time

tR

9

AC CHARACTERISTICS

-35n5
0

t02

TEST CONDITIONS

MAX

ns
CL = 20 pF to 50'pF

-14n5
2tCY

9

+20n5

20
20

cPl and ifJ2 Fall Time

tF

$2 to $2 (TTL! Delay

tOq,2

-5

+15

ns

$2 TTL, CL - '30 pF

R1 =300!!
R2 = GOO!!
1>2 to STSTB Delay

toss

GtCY
-g- -30n5

STST8 Pulse Width

tpw

tCY

RDYIN Setup Time

tORS

to

9

After STSB

tORH

4tCY
-g-

READY Qr RESET

tOR

4tCY

9

to tP2 Delay

ns

-1505

STSTB. Cl = 15 pF

4tCY
50n5- -g-

S'TSTB

RDYIN Hold Time

GtCY
9

R1 = 21<

ns

R2 = 4K

Ready and Reset
ns

-25ns

Cl=10pF
R1 =.2K
R2 = 4K

Crystal Frequency

fClK

Maximum Oscillati'ng

fMAX

MHz

.JL.
tCY
27

MHz

Frequency

CD tev represents the processor clock period

Note:

vcc

INPUT

~

R1

'

J.

Cl
GND

A2

=

GND

TEST CIRCUIT
IR

1--;-:-;:--;-:------ICy------------I

t,;2----f't----ID2
i"

':'2 (TTLl _ _ _ _ _ _ _ _ _ _ _

SYNC
(FROM PROCESSORI

1-------'055-1------1-~---tDAH---'--l

RDYIN OR

R"ESiN

READY

----------------~~

'DR

RESET

Voltage Measurement Points: ¢1, ¢2 Logic "0" = 1.0V, Logic "1" = 8.0V.
All other signals measured at 1.5V.
168

TIMING WAVEFORMS

p.PB8224
CRYSTAL REQUI REMENTS

.. 0.005% at OOC-70°C
Series (Fundamental)  4 Kn, R2 = oofi,
Cl = 25 pF. For all o1her outputs:
Rt = soon, R2 = 1 Kn, CL = 100 pF.

A,

OUTPUT
PIN

.

~:LND

,~::o

TEST CIRCUIT

TIMING WAVEFORMS

PROCESSOR DATA

BUS=====t~t::~=t===================:

DB IN ------~f-f---1

HLDA~

___

~

=

__f-f-__+ __

+ __-t

INTA.liOR. MEMA'-------k\.f-__

DURING HLDA

SYSTEM

J

-I"'""I.~-'-...,....,J ....--~----------~ ---~-

BUS DURING REAO:'" _______ _

+1'--+"f'--

-- ----

PROCESSOR BUSOUAING READ --..... - - - - - - -

'WR

'DC

,..PB823B iiOWor M"EM'W
PROCESSOR

BUS DURI NG WRITE

SYSTEM BUS

DURING WRITE _ _ _ _ _ _ _ _ _
BUSEN

_

'l
-I'

y>--~-----'E

r-- -=i 'E I-

-Il>--.. . --- -- - --- ---

SYSTEM.BusouTPuTS-----------....----""41_ _ _

VOLTAGE MEASUREMENT POINTS: °0.°7 (when outputs) Log,e "0"" O.BV, Logic "1 ... 3.0V. All other signals measured
at 1.5V.

173

P, PB8228/8238 .
STATUS WORD CHART

j.lPD8080A

j.lPB8228/8238

~-----------A----------

__

PACKAGE OUTLINE

~

~PB8228/82380
M

o· -15"

INCHES

ITEM

MILLIMETERS

A

36.c;tMAX.

1A2MAX.

1.6 MAX.

0.59 MAX •

2."

0.1

•
D

0.60 :1:0.1
33.0

0.02 :to.OO4

1.30

F

1.27

0.05

G

3.2MIN.

O.13MIN.

H

1.•

0.07

I

3.3 MAX.

0.13 MAX.

5.2 MAX.

0.20 MAX.

M

15.'

0.60

13..

0,55

0.30:1:0.1

0.012

:I:

0.004

SP822818238·1·77-GN·CAT

174

NEe Ilcracomplders,IOC.

#,PD371

MAG,NETIC TAPE CASSETTEI CARTRIDGE
CONTROLLER
DESCRIPTION

The NEC IlPD371 is a high performance N-Chan!'!el !-SI tape cassette/cartridll!'
controller designed to interflil::e between mosl cassette or cartridge tape qrive~ and
most microprocessors or minicomputers.
The IlPD371 converts 8-bit parallel data into serial phase encoded data to be written on
tape and converts phase encoded data read from tape into 8-bit para!lel data, calculates
the CRC duril')g write operations, verifies the eRe during rea!i operations, informS the
proce~or program when to send data bytes during write operatio!,!s and when to read
bytes duri~g read operations, converts-tape drive status signals into rellister bit levels
which may be read by the processor program apd converts software commands into
signllis wl1ich may be understood by the hlpe drivels):
'
T~e IlPD3.71 read and write data paths are compl~tely separa~e to allow read-after-write
data Verification.

The IlPD371 places no fimitation on the selection of tape speed since the IlPD371
maximum data transfer rate is considerably faster than that of the fastes~ cassette or
cartridge drive.
.

FEATURES

• Compatible with ANSI, ECMA and ISO standard
•
•
•
•
•
•
•

PIN CONFIGURATION

Also compatible with most either standards
Hardware CRC generatiQn apd verificatipn
Read-after-write capabil!ty
Hi~ sp~ed file search
Multiple drive capability
May read or write on one drive while rewinding or file searching on another
Mjlximum Data Transfer nite pf ~75K bits/sec equivalent to 468 IPS at 800 ~PI

MBH
VDD

AWL
Vcc.
RS"
WCK
DO
C1

0 87

DB6
DB5
QB4
DB3

wa

D~2

DB1
OBI,)
W/R

OS
RSo
RS1
RS:i
DT
UA
RWI
RWo
¢1
VBB

Il PD
371

GAP
SG
RD(-)
RD(+I
MK1
MKo
S1
C3
C2
S2
S3
REO
¢2
VSS

175

~PD371

o°c to +70°C ABSOLUTE MAXIMUM
. -40°C to +125°C RATINGS*
. " -1 to +8 Volts G)
-1 to +8 Volts CD
-1 to +16 Volts CD
-1 to +16 Volts CD
-1 to +8 Volts CD
.. -10 to 0 Volts

Operating Temperature
Storage Temperature.
All Output Voltages
All Input Voltages ..
Clock Voltages . . . .
Supply Voltage VDD
Supply Voltage VCC .
Supply Voltage VBB .

COMMENT: Stress above those listed under" Absolute Maximum Ratings" may cause permanent
damage to the device. This is a Stress rating only and functional operation of the device at these or
any other conditions above ,those indicated'in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
'Ta

= 25°C

Note:

Ta

CD

VBB

= -5V

= 0_70°C

± 5%. All voltages measured with respect to GNO.

VOO

= +12V±5%

PARAMETER

VCC

SYMBOL

+5V±5% VBB

-5V±5% VSS=OV

LIMITS
MIN

Input High Voltage

VIH

+3.0

Input Low Voltage

VIL

0

Output High Voltage

VOH

+3.5

Output Low Voltage

VOL

Clock Input High Voltage

VOH

+9

Clock Input Low Voltage

VOL

0

Input Leakage Current
Input
OBO - OB7
Leakage All Except OBO Current DB] (-25K
Internal Pull·upsl

TYP

MAX
VCC
+O.B

UNIT

TEST CONDITIONS

V
'V
V

IOH=-l rnA

+0.4

V

IOL - +1.7 rnA

VDO
+0.65

V

ILiH

+10

I1A

VI - +3.0V

ILiL

-10

I1A

VI

rnA

VI = +O.4V
Vo = +9.0V

-1.0

ILiL 2

V

= +O.BV

Clock Input Leakage Current

ILOH

+20

I1A

Clock Input Leakage Current

ILOL

-20

I1A

Vo - +0.65V

Output Leakage Current

ILOH

+10

I1A

Vo

Output Leakage Current

ILOL

-10

I1A
rnA

Vo - +O.4V

-2

rnA

Power Supply Current (VOOI

100

+20

Power Supply Current (VCCI

ICC

+30

Power Supply Current (VBSI

ISS

Ta

=

25°C, VOD

=

VCC

PARAMETER

VSS

=

OV, VSB

=

= +3.5V

rnA

-5V

CAPACITANCE

LIMITS

SYMSOL
MIN

176

DC CHARACTERISTICS

TYP

MAX

UNIT

TEST CONDITIONS

= 1 MHz. All

Clock Capacitance

Co

35

pF

fc

Input Capacitance

CIN

10

pF

except measuring pin

Output Capacitance

COUT

20

pF

are grounded.

pins

J.,LPD371
AC CHARACTERISTICS·

Ta = 0 - 70°C, VDD = +12V.± 5%, VCC = +5V ± 5%, VBB = -5V ± 5%, VSS' = CU
LIMITS

PARAMETER

SYMBOL

Clock Period

tey

Clock Rise and Fall Times

t" tf

MIN

TYP

MAX

UNIT

4BO

5000

ns

0

50

ns

TEST CONDITIONS

1 Pulse Width

t1

60

ns

2 Pulse Width

t2

220

ns

1 to 2 Delay

tD1

0

ns

2 to 1 Delay
Delay 1 to 2 Lead Edges

tD2

70

ns

tD3

BO

Data Out Delay from 1

tOD1

4BO

ns

Data Out Delay from 1

tOD2

260

ns

1TTL & CL = 30 pF

RS O - RS2 to Output Delay

tACC1

300

ns

1TTL&CL=30pF

DS, W/R to Output Delay

tACC2

200

ns

1TTL & CL - 30 pF

DBO - DB7 to 2 Setup
Time

tlS1

250

tlS2
DS, W/R to 2 Setup Time ~IS3
-Input Hold Time from 2
tlH

350

ns

HiD

ns

3D

ns

ns
1TTL&CL=30pF

ns

RS O - RS2 to 2 Setup
Time

TIMING WAVEFORMS

~-----------tCY----------~

1
1/1·2

23

WCK detarmin .. theWflIT~ DATA IWD, pi~ 36) transfor r .... WCKsho~ld
have a period 01 0.5T.
'
.
OT Is a pulse provided by the "P0371 to be used in the generation of thl thr...
~ad timing sign~1s - SG, ~O, and GAP. OT occun at eac,h data transition In
the data read from tape.
The internal read data sample gate Is closed following .ch data transition and
is reopened by a positiv. tr.ansition at SG O.7ST ",sec
each OT pulse.
A positive transition should be made at 00 whenever a DT pulse stream ceases
for a period of 1.5T ,",sec. A positive tra",,,itio!'1 shQ!Jld be made at GAP when~
ever a DT pulse 'stream ce. . . for a period of 4T ,",sec.

.ter

1/11 and 1/12 ora MOS IaVei 112V) clock pul ... The timing 01 4>1 and 4>2 ilohown
in tho Timing Diagram.
WRITE DATA
36

I

WD

,

I

Phase ancodaf data to

b8 written on tape leaves th~' "P0371 at pin 36.

TAPE DRIVE COMMAND
AND STATUS
37

Cl

27

C2

2B

Cs

29
26
25

SI

C1, C2 and C3 are general purpose tape drive commands.
C1. C2 and C3 are!Ntt ~,..d reset by the software manipulation of bits 5. 6 and 7,
respectively. in Write Regi~r~. Since C1. C2 and C3 are defined by software.
they may be configured for any purpQse. Typal usas for Clo C2 and C3 are
WRITE ENABLE. FORWARD and REVER§E.

S1. S2 and S3 are gen..,1 purpose tape dri~ status inputs. Their logic 1""ls
are indlcotad by bits 3. 4 and 7 01 Road Roglster 1. respectively. Typical tope
drivo ..atus signals are WRITE PERMIT. CASSETTE IN PLACE and SIDE.
The "PD371 can ~dapt to any taPl4rlve status signal set with a slight change

S2
S3

in software.
DUAL TAPE DRIVE SYSTEM
COMMAND AND STATUS
17

UA

19

RWO

Rewind 0

Rewind Commanc;t for prive O~

lp

RWI

Rlllf!lnd 1

Rewind Command for Driw 1.

30

MKo

Markor a

EOT/B9T statui irol1) Doive O.

31

MKI

Marker 1

EDT/BOT st..u,lrom Drive 1.

~2

RDI·h

Road

A positive pulse from the tape drive at ~ch positive transition in the read data.

Unit

Select. Drive a v.tlen low and Drive 1 when high.

Address

READ DATA

O..aH)
33

Rtiad
Data 1-1

RDI-!

A positive pulse from the tape driVe at each negat!V8 transition In the read data.

MISCELLANEOUS
1
42

I MBIi
I AWL

I
I

MBH must be lied t~ the Vee liSV) supply.
AWL is a logic low output under ali" normal operating cqndltlons of the "PD371.

..

PO\'! ER SUPPlY VOLTAGES
2

VDD

41

VCC

22

.VSS

21

N~te:

178

VBB

+12V
iSV

Ground
-5V

CD Refer to diagram on foll~lng page.

p,PD371
PIN IDENTI FICATION
(CONT.)

PROCEsSoR INTERFACE

TAPE DRIVE INTERFACE

Rese,

REGISTER
.
SELECT

{

40

Register Write/Read Select 11
'.
12
Register Data. Strobe
13
Register Select 0

COMMANDS

14

Register Select 1
Register Select 2 15

RST

Write Data

Drive Command 1

RSO

Drive Command 2

RS,

Drive Command 3

A~2

REO

Drive Status 1
TAPE DRIVE
COMMAND
ANOSTATUS

Drive Status 2
Drive Status 3

Data Bus 0

DATA BUS

TO
TAPE DRIVE

,

W/R
OS

S,
InterruPt Request

}

DBO

Data Bus 1

OB,

Data Bus 2

DB2

Data Bus 3

DB3

Data Bus 4

P B4

Data Bus 5

DB5

Data Bus 6

086

Data Bus 7

DB7

Drive Address, (1/01

",,0371

Rewind Co"mmaRd Drive 0

RW,

Rewind Command Drive 1

Drive 0 EOT/aOT Sta'tus
Drive 1 EOT IBOT Status

Read Dat8

RO(+)

Positive Transjfions

RDI-)

Read Data
Negative Transitions

DO

MIlH

Must be High 1+5VI

SG

AWL

Alwavs Low

WCK

FROM
}

TAPE DRIVE

}

MISe

GAP

TIMING

Data Transition

DT

.2.'

.'

MOS
LEVEL
CLOCKS

02

Voo

Vee Vss' Vas

. +12V +5V

ov

-5V

PACKAGE OUTLINE
pPD371

ITEM'
A

MILLIMETERS
53.5 MAX

INCHES
2.1 MAX

B

1.35

0.05

·C

2.54

0.10

D

50.80

F

1.27

G

2.54 MAX

0.10MIN

H

1.0MIN

0.04 MIN

I

4.2 MAX

0.17 MAX

J

5.2 MAX

0.21 MAX

2.0
0.05

K

15.24

L

13.50

0.53

M

0.3

0.012

0.60

179

#PD371,
From the point of view of the processorj:Jrogram, the /lPD371niakes the tape drive
(or multiple drive system) appear as ten addressable registers; The program cootrols
the drivels) and transmits data to be written on tape by manipulating bits. in the six
/lPD371 Write Registers. The prograrh senses the statUs df tHe dril(ets) and reads data
stored on tape by reading bits from the four /lPD371 Read Registers.

BIT NUMBERS

REGISTER AODRESS

I-_---y--,.--! REGISTER !---;-.-....,,...---.r---,...--r---r--.,.-----!
NAME

o

7

WRITE REGiSTERS

'

,

0

0

0

0

0

0

,0

WRo

I RST I MBL I s~sl WMEIWCR I It

WR,

I

WRRI RRB I X

IWMOI GNT

I

RRE I RRO IGREI GROI X

I

I

WR2
,

0

WR3

I

C31

C2

II I II I I
C,

RRI

RW

X

X

X

ADDRESSABLE INTERNAL
REGISTERS

ILPD371
ADDRESSABLE
INTERNAL REGISTER
BIT
IDENTIFICATiON

BIT

SYMBOL

NAME

BIT

SYMBOL

WRITE REGiStER 6

WRITE REGISTER 0
0

GNT

Gap Noise Tolerance

1

WMD

Write Mode Disable

2

-

3

WCR

WriteCRC

4

WME

Write Mode Enable

5

SRS

Status Reset

MBL

Must Be Low

7

RST

0
1 -7

UA

-

Not used

6'

Reset

NAME

Unit Address
Not used

READ REGISTER 0
0

RRO

Read Request

1

WRO

Write Request
Gap Request,

2

GRO

3

RDF

Read Flag

4

C3

Command 3

WRITE REGISTER 1

5

-

Not used

6

C2
AWL

Command 2

0
1

GRD

Gap Request Disable

7

AWH

Always High

2

GRE

Gap Request Enable
Read Request Disable

3,

RRD

4

RRE

5

-

Read Request Enable
Not used

6

RRR

Read Request Reset

7

WRR

Write Request Reset

WRITE·REGIStER 2
0-7

WDOWD7

Write Buffer 'Register

READ REGISTER 1
0

UA

Unit Address

1

C1

Command 1

2

RW

Rewind

3

Sl

Status 1

4

S2
MKF

Status 2

5

6

MK

Marker

7

S3

Status 3

WRITE REGISTER 3
0

-

Not used

1

-

Not used

2

RW

Rewind

4

RRI

Rewind Reset Inhibit

5

C1

Command One

6

C2

Command Two

7

C3

Command Three

WRITE REGISTER 4

-

-

Not used

WRITE REGISTER 5
0

-

-

Not used

2

-

Not used

3

RMD

4

RME

5

-

7

RDORD7

Read Buffer Register

READ REGISTER j
0

NAR

Noise After Record

1

NBR

Noise Before Record
Command Overruh

2

COR

3

DOE

Drop Out Error

4

CRE

CRC Error

5

REC

Record Detection

6

GPF

Gap Flag

7

WD

Write Data

Not used

1

6

Marker Flag

READ RE(3ISTER 2
0-7

Not used

3

Always Low

Read Mode Disable
Read Mode Enable
Not used
Not used
Not used

SP371-8-77-GN-CAT

181

"";"
~

,

NEe .CrlComputeMl,IHG.

,.,.PD372

FLOPPY DISK CONTROLLER
The ~PD372D is a single LSI floppy disk controller chip which contains the circuitry
to read, write, track seek, load and unload the head, generate and detect CRC
characters, and perform all other floppy disk operations. It is completely compatible
with the IBM, Minifloppy*TM, hard sector, and other formats and controls up to
4 floppy disk drives. The ~PD372D may be interfaced directly to a host processor;
or to a. controller processor first, which in turn is interfaced to the host. These
processors do not necessarily have to be of the 8080A type.

DESCR IPTION

Data transfers to and from the ~PD3720 are done through addressable internal
regiSters. These internal regsiters allow a large variety of system architectures to be
configured; they provide status information on the drive, as well as perform dl!ta
transfers between the drive and the processor.
The ~P03720 issues interrupts to .the processor upon detection of an address mark
and then when each subsequent data byte is available during either reading or writing.
An 8·bit bi-directional data bus and 5 register select lines provide access to the 9
internal registers' contents. An internal interval timer is.provided which facilitates
performing such drive timing functions as: stepping rate, head settling time, track
settling time, etc.
*TMShugart Associates.

r

• Compatible with IBM 3740 format
• Also compatible with other formats including Minifloppy and hard sector
• Controls up to four floppy disk drives
• Can perform overlap seeks
• Input and output TTL compatible (except for cJ>1 and cj>2)
• Interfaces to most microprocessors including 8080A
• Standard power supplies (+12V, +5V and -5V)
• Controls most floppy disk drives including:
ORBIS 74, 76/77
CALCOMP 140, 142
CDC BR803
PER SCI 70, 75
INNOVEX 210, 410
REMEX RFS 7400
PERTEC F0400
SHUGART SA400 (Minifloppy)
POTTER 004740
WANGCO 82 (Minifloppy)
SHUGART SA900, SA800
GSI M0050 (Minifloppy)
GSI110

FEATURES

·RST
W/R

PIN CONFIGURATION

os
RS2
RS,
RSo
lOX

WFT
TOO
RCK
RD
RVA
·WCK
RVB
CKS
AWL
REO
WD
HLD
VSS
VBS

<>2
<"

VDD
Vcc
DB7
Oils

DB5
DB4
DB3
DB2
DB,
DBa
UAo
UA,
UBO
UB,
50S
SID
WE
WFR
LCT

Rev/2
182

JLPD372
ABSOLUTE MAXIMUM
RATINGS*

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . oOe to +70 o e
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40·e to +125°e
All Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0 to +8 VoltsH

+9

VOO

V

Low Level Clock
Voltage

VL

0

+0.8

V

High Level Input
Leakage Current

IUH

+10

/lA

VI

Low Level Input
Leakage Current

IUL

-10

/lA

VI = +0.8V

High Level Clock
Leakage Current

ILH

+10

/lA

V = +9.0V

Low Level Clock
Leakage Current

ILL

-10

/lA

V =+0.8V

High Level Output
Lea kage Cu rrent

I LOH

+10

p.A

Vo = +3.5V

Low Level Output
Leakage Current

I LOL

-10

/lA

Vo = +O.5V

High Level Clock
Voltage

I

Power Supply
Current (V OO )

100

+20

mA

Power Supply
Current (V CC)

ICC

+23

mA

Power Supply
Current (V SS'

ISS

Notes:

-2

CD

CKS, REO, UA O' UA 1, US O.-UB 1, OBO-08 7 .

(i)

WO, HLO, LCT, WE, WFR, SOS, SID.

= +3.0V

mA

183

,u.PD372
Ta

=0

= +12V

-70°C, VDD

±5%, VCC

= +5V

±5%, VSS

= -5V

±5%, VSS

= OV

AC CHARACTERISTICS

LIMITS
PARAMETER

SVMBOL

Clock Period

tcy

MAX

UNIT

480

2000

ns

0

50

ns

MIN

TVP

TEST CONDITIONS

Clock Rise and Fall Times

tr,tf

91 Pulse Width

t91

60

92 Pulse Width

t92

90

ns

01 to 02 Delav

tD1

0

ns

02 to 01 Delav

tD2

70

ns

Delav 01 to 02 Leading Edges

tD3

100

Data Out Delav from 01

TODI

90

ns

1 TTL and Ci

30 pF

Data Out Delay

tOD2

200

ns

1 TTL and Ci

30 pF

@
~

from 02

ns

ns

200

ns

2 TTL and Ci - 50 pF

tOD3

120

ns

2 TTL and Ci = 50 pF

Data Out Delay from
DS' W/R· RS 2

tOD4

200

ns

Data Setup Time to cPl

tiS 1

150

ns

Data Setup Time to c;.>2

tlS 2

120

ns

10

ns

WD Delav Time

Data Hold Time Irom 1>1
Data Hold Time from

1>2

WD pulse width

tWD

Input pulse width



"HI
tlH2

(j)

tw

10
tD3-40

ns
tD3

tCy+150

HLD, LCT, WFR, WE, SOS, SID.
IDX, RVA, RVB, RST, WFT, TOO' WCK, RCK.

01

02

INPUT

1

OUTPUT

WD

08 0 - 7
INPUT

RS2
W/R
DS

OUTPUT

DBa_ 7

os c.WIR . RS 2
Notes:

G)

~ IDX, RYjI,

RYB, RST, WFT, TOO, WCK, RCK.

2 CKS, WFR, SOS, SID, REO, HLD, UA Q, 1, UB\,>,I' WE, LCT.

3 RSo. RS 1 input must not make level transition within tlS1 and
tl H 1 times, or register contents may be modified.

o

The logic condition which places J.lPD372 information on DBO_7

is OS· W/R . RS2_ Care must be taken to insure that this cO,nditian
is not met inadvertently if OS, W/R and RS 2 are allowed to change
state asynchronously.

184

ns

CKS. AWL, REQ, UA O' UA I • US O' UBI'

I-----'cy-----I

OUTPUT

ns

TIMING WAVEFORMS

J.LPD372
READ CLOCK (RCK) AND
READ DATA (RD)
REQUIRED BY IlPD372

I

-200ns----1

o
Il-'s
21-'s
31-'s
4ilS
5ilS
61-'s
Mi;sing
Early
.., I---..:.....--....;.;.;...,'-!-''---~--, ~--:-..,~--..:.....---I r-U
L..':
U"4-tJ
L.J

I

Raw Data
from Floppy
Drive

I

I

I

I

I

(Pin 101 RCK

(Pinl1)RD

-mOO:
---I--:S ~CY -150 ns

L--.x

RD must be Stable

?:2 tCY + 100 ns

Notes:

(j)

tCY

=

<1>1 Clock Period

@Tl?:tCy+160 ns

@

PIN IDENTIFICATION

PIN
NO.

SYMBOL

NAME_

1

RST

Reset

2

W/R

Register Writel
Read Select

3

DS

Data Strobe

4-6

RS<;,>
RSI
RS2

R~gister Select

7

IDX

Index

T2::::tCY + 160 ns

INPUTI
OUTPU,T CONNECTION

Processor

8

WFT

Write Fault

TOO

Track 00

10

RCK

Read Clock

II,

RD

Read Data

12

RYA

Ready A

13

WCK

Write Clock

14

RYB

Ready B

15

CKS

Clock States

16

AWL

Always Low

W/R = 1 implies,DB O_7 data written
into pP0372 registers
080-7 Write an~ read strobe

Internal Register Select
Pulse Signal that indicates start of
Disk track

Input

9

FUNCTION
Initializes internal registers, counters
and'F/Fs

Write Fault Signal

FDD

Indicates that Head is positioned on
Track 00

Indicates that FDD A is Ready
Processor
FDD

Indicates that FOD B iS,Ready

Always a logic zero
Processor

Interrupt Request

17

REO

Request

18

WD

Write Data

Serial Write Data (Clock & Data
Bitsl

19

HLD

Head Load

Command wh ich cau'ses R /W head

22

LG;r

Low Current

Command to lower write current
for inner tracks

23

WFR

Write Fault Reset

24

WE

Write Enable

25

SID

Step In or Direction

R/w head step control

26

SOS

Step Out or Step

RiW head step control

to contact disk

Output

27-30 UAO. UA,
UBO. UBI

FDD Select

31-38 DBO-7

Data Bus

FDD

Signal to reset write fault latch

FDD Unit Select

Input/

Processor

Bi·directional data bus

OutP~t

185

J.LPD372
PROCESSOR INTERFACE

DISK DRIVE INTERFA.CE

Reset

Write Data

PIN IDENTIFICATION
(CaNT.)

) TO
DISK DRIVE

Head Load
Register Write/Read Select
REGISTER
SELECT

{

.

COMMANDS

Low Current

Write Fauit Reset

Register Data Storage
Register Select 2
Aegister select 1

Write Current Enable
Step In Or Direction
Step Out Or Step

Register Select 0

DISK DRIVE
COMMANDS

Disk Drive B1 Select
Disk Drive BO Select
Interrupt Request

Disk Drive Al Select
Disk Drive AO Select

Data

Bus 0

I'PD372

Data Bus 1
Data 8us

Read Clock

2

Read Data

}

FROM
DISK DRIVE

Data Bus 3

DATA BUS

Data Bus 4
Index

Data Bus 5
Data Bus 6

Write Fault

Data Bus 7

Track Zero

Disk Drh~e A Ready
Disk Drive BReady

}

DISK DRIVE
STATUS

Write Clock
TIMING {

<1>1

Clock Status

<1>2

Always Low

GNO-5V +5V +12V

PACKAGE OUTLINE
IlPD372D

ITEM

MILLIMETERS

A

53.5 MAX

INCHES
2.1 MAX

B

1.35

0.05

C

2.54

0.10

0

50.80

F

1.27

2.0
0.05

G

·2.54 MAX

0.10 MIN

H

1.0MIN

0.04 MIN

I

4.2 MAX

0.17 MAX

J

5.2 MAX

0.21 MAX

K

15.24

0.60

L

13.50

0.53

M

0.3

0.012

186

j.LPD372
INTERNAL REGISTER IDENTIFICATION
BIT

FU,NCTION

NAME

SYMBOL

WRITE REGISTER 0
0
1
2
3
4
5
6
7

WFR
LCT
HLD

MBL
RST

Not Used
Write Fault Reset
Low Current
Head Load
Not Used
Not Used
Must Be Low
Reset

Resets Pin 23 to Zero
Sets Pin 22, Should be Zero for TR KS > 43
Sets Pin 19, Loading FDD He.d

Software Reset,-S-ame-e-ffect ast>1n

-r

CBS

WRITE REGISTER 1
Device Select Pin 30
Unit AO Select
Device Select Pin 29
Unit A 1 Select
Strobe for Enabling UAO and OA 1 to be Loaded
Unit A Strobe
Enables Clock Pulse~ to be Written
Clock Bit 3
Enables Clocl~ Pulse #4 to be Written
Clock Bit4
Enables Clock Pulse #5 to be Written
Clock Bit 5
Not Used
Enables Clock Bits to be Loaded
Clock Bit Strobe

0
1
2
3
4
5
6
7

WDO
WDl
WD2
WD3
WD4
WD5
WD6
WD7

Write
Write
Write
Write
Write
Write
Write
Write

0
1
2.
3
4
5
6
7

CCW
CCG
WER
IXS
WES
STT
WCS
RCS

WRITE REGISTER 3
One During R/W, Zero for CRC Reset
Cyclic Check Words
Starts CRC Generator in Write Mode
Cyclic Check Generator Start
Resets Pin 24 to Zero
Write Enable Reset
Enable Index Hole Detection
Index Start
Sets Pin 24 to One
Write Enable Set
. Enables Read and Write Operations to Occur
Start
Write Clock Selected
Write Clock Set
Read Clock Selected
Read Clock Set

0
1
2
3
4
5
6
7

UBO
UB1
UBS

0
1
2
3
4
5
6
7

UAO
UA1
UAS
CB~

CB4
CB!i

WRITE REGISTER 2

SOS
SID
STS

0-7
0
1
2
3
4
5
6
7

DRR
IRR
TRR

Data
Data
Data
Data
Data
Data
Data
Data

Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7

WRITE REGISTER 4
Device Select Pin 28
Unit BO Select
Device Select Pin 27
Unit B1 Select
Strobe for Enabling UBO, UB 1 to be Loaded
Unit B Strobe
Not Used
Not Used
Sets Pin 26 to One
Step Out or Step
Sets Pin 25 to One
Step In or Direction
Enables sas and SID to be Loaded
Step Strobe
WRITE REGISTER 5
This Register Not Used
I
WRITE REGISTER 6
Resets DRQ (RRO Bit 0)
Data Register Reset
Resets IRQ (RRO Bit 1)
Index Request Reset
Resets TRQ (RRO Bit 2)
Timer Request Reset
Not Used
Not Used
Not Used
Not Used
Not Used

187

jJ.PD372
INTERNAL REGISTER IDENTI FICATION (CONT.)
BIT

SYMBOL

I

NAME
~EAD

FUNCTION

REGISTER 0

0

DRO

Data Request

Read Data Byte from RR2 or Write Data Byte
intoWR2

1
2
3
4
5
a
7

IRO
TRO
ERR

Index Request
Timer Reauest
Error
Drive BO Selected
Drive B1 Selected
Drive BReady
Alwa'{S High

Set by Physical Index Pulse
Set by Every 512th Write CLK Pulse
Logical OR ofWFT + RYA + COR

0
1
2
3
4
5
a
7

UAO
UAt
WFT
RYA
COR
DER
TOO_
WRT

Drive AO Selected
Drive A 1 Selected
Write Fault
Drive A Ready
Command Overrun
Data Error
Track Zero
Write Mode

0
1
2
3
4
5
a
7

ROO
RDl
RD2
RD3
RD4
RD!i
RDa
flD7

Read
Read
Read
Read
Read
Read
Read
Read

UBO
UBl
RYB
ALH

Ready Signal from Pin 14
Always Contains a Logical One

READ REGISTER 1

Indicates Status of Pin 8
Indicates Status of Pin 12
Processor Did Not Respond in Time to a DRO
CRC Error During Read
Indicates Status of Pin 9
Indicates which Clock WCK or RCK has been
Selected

READ REGISTER 2
Data
Data
Data
Data
Data
Data
Data
Data

Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit a
Bit 7

ADDRESSABLE
INTERNAL REGISTERS

Data is transferred to the J.lPD372's internal addressable registers by signals W/R
(Write=1, Read=O), DS (Data Strobe) and RSO-RS2 (Register Select 0, 1 and 2).
Timing constraints for these signals are shown in the Timing Diagram. Diagram below
shows register allocations and functional content.
REGISTER ADDRESS

I

I

REGISTER
NAME

W/R RS21 RSl RSO

BIT NUMBERS

I I I
7

I

S

6

4

I

3

I

2

I

1

I

0

I

WRITE REGISTERS

0

0

0

0
0

0

0

WRo

RST

MBL

X

X

HLD

LCT

WFR

X

WRl

CBS

X

CBS

CB4

CB3

UAS

UAl

UAo

WD6

WDs

WD4

WD3

WD2

WDl

WDo

WCS

STT

WES

TXS

WER

CCG

CCW

STS

SID

SOS

X

X

UBS

UBl

UBo

X

x

x

x

X

TRR

IRR

DRR

WR2
WR3

0

0

WR4

0

WR6

I
I
I
I

WD7
RCS

I
I

READ REGISTERS

0

0

0

0

0

0

0

0

0

RRO
RRl

0

RR2

I
I

ALH

WRT

I

RD7

I
I

'RYB

UBl

UBo

ERR

TRO

IRO

I

DRO

TOO

DER

COR

RYA

WFT

UAl

I

UAo

RD6

RDS

RD4

RD3

RD2

RDl

I

ROO

x

188

=

NOT USED

I
I
I
SP372·8·77·GN·CAT

~PD379

SYNCHRONOUS

RECEIVERlTR~N$MITTER

DESCRIPTION

FEATUftES

The IlPD379 Synchronous ReceiverlTransmitter inn MOS LSI monolithic circuit that'
performs all the receiving and transmitting functions associated with Basic and High
Level Data Link Control Procedures. This circuit is fabriC{lted using N-channel AL-Gate
MOS technology, allowing all inputs and outputs to be directly TTL compatible. The
operation mode, baud rate and synchronous character are changeable through the use
of external control. The IlPD379 i~ PQckaged in a 42 pin .Dual-in-line ceramic package.

•

Suitable for Synchronous Basic and High Level Data Link Control Procedures
(BiSync or SOLC)

•

Full or Half Duplex Operation

• Fully Double Buffered Transmit and Receive
•

Directly TTL Compatible

• Three-State Data Outputs
• Programmable Sync Word
•

Detection/R!ljection of Flag, Aport and Idle Patterns

• Zero Insertion and Rejection
•

Indication of qverrun and Underrun !=rrors

.• 800K Bits/~ec Operating Speed

PIN CONFIGURATION

NC

IIIC

VDD

Vcc

CS

MRL

1m'

MS,

mm

~S2

rei

RC
RI

'i'OiI.

~/~

CFR
ABTR
SVIIIR/IOLR

ROa
R07

~YNC/TrJS

IlPD

379

fiDe

TOil

T\>7
T'?e
TOs

R05
R04

T04
T03
T02

R03
R02
RO,

TOt
T~
SVNT/ABTT

DR
OE

TCB~

V,,

GND
IIIC: NO CONNECTION

Rev/1
189

,",PD379

Basic Sync Mode Transmission
The Sync character may be 16 in hexadecimal or it may be set to any other pattern
in the Closed Mode. When the mode control register is loaded with MS1 = high and
MS2 = low, the ~PD379 enters the Basic Sync mode from the Closed Mode. The Sync
character is. continuously transmitted until a transmission data character is loaded.
After a data character is loaded, it is serialized and transmitted out from the TO
(Transmitter Output) line. If an underrun occurs, Sync character(s) are again trans·
mitted automatically until the next data character is loaded. Transmission data is sent
out from LSB (TD1) first to MSB (TDS) last on the TO line.
Basic Sync Mode Receive
The RI (Receiver Input) line first searches for Sync characters. Once an S-bit Sync
character has been detected, the following received bits are treated as data characters
and outputted on lines R01 - RDS in parallel.
When device operation is started, the receiver section should be first brought into
Closed mode or should be reset in order to ensure synchronization.
SOLC Mode Transmission
Until a data character is loaded, the Flag pattern (7E in hexadecimal) is automatically
transmitted continuously. After a data character is loaded, it is serialized and transmitted out from LSB (TD1) to MSB (TDS) on the TO line, In transmitting data
characters, a dummy bit 0 is automatically inserted immediately following five (5)
successive 1's. This is called Zero-Insertion and is performed in order to maintain
synchronization with the.receiver and to avoid duplication of Flag pattern in data
characters. (Zero-Insertion may be prohibited optionally with the ZIP command, if
necessary.. ) If an underrun occurs while data characters are being transmitted, an Abort
pattern (I"F in hexadecimal) and then a Flag pattern are automatically transmitted.
After th·at, the Flag pattern is again automatically transmitted until the next data
character is loaded.
If a low level is placed on the CFT (Closing Flag Transmit) line while a data character
is being transmitted, a Closing Flag will be transmitted immediately following transmission of the current data character.
SOLC Mode Receive
First, the Flag pattern is searched for on the R I line. Once a Flag pattern is detected,
inserted zero's are rejected from all the following characters except Flag, Abort (7 to
14 successive 1's) and Idle (15 successive 1's) patterns, and then deserialized and output on the RD1 - RDS lines in parallel.
If an overrun occurs, all the following data inputs are neglected and the
back to the first stage to search for the next Flag pattern.

~PD379

goes

Closed Mode
When .there is a change of mode, it must pass through the closed mode. In the closed
mode, the following input signals may be used:
CS, SYNC, TcEi[, MS1, MS2, MRL, TD1 - TDS
After leaving the closed mode, Sync characters are transmitted synchronously with the
rising edge of TC. The receiver operates synchronously with the fall ing edge of RC,
after RR = 1.
The following timing diagram shows how mode changes may be accomplished.

CLOSED

MODE

BASIC
SYNC

MODE

190

CLOSED

MODE

SOLe
MODE

FUNCTIONAL
DESCRIPTION

jLPD379
BLOCK DIAGRAM
SVNCflIP

iiil'lIIC"I'
mil
SVNT/AeTT

TeBe

TC

TO

MRL

~~,...-....- . ,

MSI
M~

+12 V

o-~~

_______

r-!-

+sV ~

ov~

_sV ...,!L.

o INPUT
-0 OUTPUT

• • CONTROLLED BY
THE SINPUT

CFR

ABSOLUTE MAXIMUM
RATINGS*

AlTA SVNAI DR OE
IDLR

Temperature Under Bias . . . . . . . . . . " . . . . . . . . . . . . . . . O°C to +700 e
SJorage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +125°C
All Output Voltages . . . . . . . . . . . . . . . . . . . . '.. , . . . . . . OV to +8.ov0
All Input Voltages . . . . . . . " . . . . . . . . . . . . . . . . . . . . . . OV to +8.0V 0
Supply Vol tag. Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OV to +8.0V 0
Supply Voltage Voo . . . . . . . . . . . . . . . . . . . . . . . . . . . . ov to +16.0V 0
Supply Voltage VBB . . . . . . . . . . . . " . . . . . . . . . . . . . . . .
10.0V to OV
COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational seCtions of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliabilitY.

-Ta = 2SoC

Note: (j) VBB

AC CHARACTERISTICS

Ta

=-

5 ± 5%

=O°C to +70°C,VOD = 12V ±5%, VCC = SV ± 5%, VBB = -SV ± 5%

PARAMETER
Clock Frequency

SYMBOL
fc

LIMITS
MIN

TYP

MAX

800

DC

UNIT
KHz

TEST CONDITIONS
TC, RC
TC,RC

250

ns

MRL

250

ns

TCBL

250

ns

SNTR/CFT

250

ns

ZIP

400

ns

iffi

ns

ORR

!SET UP

250
250

Hold Time

tHoLD

150

Rise Time

tt

150

ns

Fall Time

tf

150

ns

Pulse Width

Setup Time

tpw

ns
ns

Pulse Intenjal

tcc

Output Delay

tpdl

180

270

ns

CL

Time

tpd2
N

410

600

ns

1 TIL Load

Fan Out

ns

100

1

= 20 pf

Standard TIL Load

*50% Duty Cycle

191

J'PD379
PIN IDENTIFICATION

FUNCTION

PI~

NO.

I

BASIC SYNC MODE

SYMBOL

SOLCMODE

NC

No Connection

VOO

+12V Power Supply

~

R'II'
ORR
RC

Chip Select - When "1", the following inputs are disabled and the outputs are put Into the high
impedince state: (Input Disabled) FiR, 6i!iR, SYNC/ZiP, S'N'i"R/eFT','i'CBt, MAL; (Output-H'gh
ImPectance) CFR, ABTR, SYNR/IOLR, RD, - RDS, DR, OE, TCBE, CVNT/ABTT
Receiver Reset - Receiver portion is reset with a "0" and operation is stopped
~D1 -RD8----"~ ..
CFR, ABTR. SYNR/IDLR, AR, OE - - -'- "0"
Data Received Reset - Resets OR flag to ';0"
Receive):, Cloc·k - Receiver clock input. Trailing edge of clcx;:k is located in the center of receiver input

.

.~

'0

,

.

RI

Receiver Irlput

CFR

(Normally "0"1

Closing Flag Received - Goes hlltt whenever a Flag
has been received during data reception. Goes low
on the rising edge of DR or OE comman!=ls

ABTR

("0" Constant)

Abort Received - Become" "'" when 7 - 14 con·
tinuous "'''5 are received, after receiving the flag.
Goes low on the rising edge of 0 R or OE commands.

SVNR

Sync Character Received - Goes high when syn·
chronization has occurred, or whenever the con·
tents of the Sync Character Buffer and the contents
of the Receiver Character Buffer coincide. Goes
Io'w when DR goes high and the RD, - RDs out:
puts are different from the Sync Character.

Idle Pattern Received - Becomas "'" Iidiel when
it receives 15 consecutive ","5. Goes low on the
rising edge of DR or OE outputs.

loLR

11-1S

ROS-RD,

19

DR

Received data serial input

Receiver Data OutPUts - Received character OUtput terminal (RD, :LSB RDa:MSB)
Data Received - Goes J,igh when thll received character has been transferred from the Receiver Shift
Register to the Receiver Buffer Register

DRdda-;~0~;hi;'fo7thefir; ~n;-Cha;;t; --lORd;S"~';;;-hilt1f07Ra;'-Ab-;~;-ldi;P~:-inPUt. It is reset when ORR is driven low.
tems. It is reset when (1) I5R'R = "0", (2) On the
rising edge of OE, (3)SeYen 171 Sl;Iccessive "1"s
have been received,
20

OE

21

Va9

22

VSS

23

TCBE

Overrun Error - OE - "'" shows that DR was still high when the received character is moved from the
receiving shift register to the receiving bJffer register
OEis-;;.;tiTDRi;i~-;"--;~;;';'~7h;;~Ttis!e;t;;therisi;;g~-;ofDR-- - - - - is transfelTed from the Receiver Shift Register to
the Receiver Buffer Register
-5V Power Supply

Ground
Transmitter Character Buffer Register EmptY TCB E '"' "1" when the transmitter character buffer is
_______________ _
!!,!l~;...

iti"s-;';t-;"-;'"'7"i1)TCBL:'7.i).':-I2I Whe~CFr-:"0" In the data transmission mode, (3) One-half
bit before ABTT goes high.

TCBE is ,reset when TCBL is driven low

24

SYNT
ABTT

25

TO

26 - 33

TDl -T08

34

SYN~

ZIP

35

SNTR
CFT

SYNC Character Tralsmit - SYNT - "1" when a
synchronous character is being transmitted. It is
re.t when: (1) §'iiffi!!i. co "0", 121 when transmission of data commences
Transmitter OutPUt - Transmitter data OUtput. TO

Abort Pattern Transmit - ABTT - "'" when an
Abort Pattern is being transmitted

= "1",

in the closed mode.

Transmitter Data Inpub - Transmitter character input. (TD1 = LSB, TOa '" MSB)
SYNC Character - In the Clo.d Mode, the SYNC
line is used to select a SYNC character to be loaded
into the SYNC Character Buffer. The selected
SYNC character is loaded into the bUffer on the
rising edge of TCBL and is selected as follows:
(1) When SYNC = "0", the character placed on the
T01 - TOB inputs is loaded, (2) When SYNC =
"''',16 Hexadecimal is loaded.
SYNC Character Transmit Reset - When SNTR is
driven low, SYNT is reset to "0".

I Zero Insertion ~ohiblt - When ZIP Is driven
I low, zero-insertion will be prohibited for all subseJ quent data characters until a Closing'Flag or an
I Abort Pattern is transmitted.

I

I
I
Closing Flag Transmit - During,transmission, CFT

I low causes the following operations to occur:

I (,) TCBE OutPUt is reset to "0", (2) The Closing
I Flag will be transmitted after the end of transmission
of the current data character,

36

31

TC

38
39

Transmitter Charactet Buffer Load - (') In the closed Mode: the SYNC Character Buffer is loaded on the
rising edge of fCBt.. If the SYNC input is low, the buffer is loaded with the data on the TO, - TO~uts;
if SYNC Is high, the buffer is loaded with (16) Hex. (2) In the Basic SYNC or SoLC Modes: When TCBL
is driven low la) TCBE is reset to "0" and Ib) the data character on the T01 - ToS inputs is loaded into
the Transmitter Character Buffer. The loaded cnaracter is latched on the rising edge of TciiL.
Transmitter Clock - Clock input for transmission.
Mode Select 2
Mode Select 1
Used to select one of three modes.
MSl

MS2

T

L

L

H

MODE

Closed""'MOde"'
Closed Mode
H
Basic Synchronous Mode
H
H
SOLC Synchronous Mode
In the closed mode TO and RO, - RDS are high, all other outputs ara low.
40

MRL

41

VCC

42

NC

192

Mode Control Register Load - When MRL is low, the operational mode is selected by the current status
of MS, and MS2. When MRL goes high, the operational mode is latched based upon the status of MS1
and MS2.
+5V Power Supply
No Connection

·JLPD379
TIMING WAVEFORMS

.

MODESELECT

MODE

MS,

Closed
Basic Sync
SOLC

0
1
1

MS2

MRL

o or 1 "LS
1
1

L-r

Lr

CHip SELECT

OUT

IN'

Should be stabla.

Unit:nsec

TRANSMITTER SECTION
TC

TO

SVNT

TCSE

A8TT

SYNC

'---'---ItHOLD

"

Unit: nNe

193

JLPD379
RECEIVER SECTION
RC

TIMING WAVEFORMS
(CONT.)

DR

RD,---+~j----------~~-r--------k

RD.I __

-+~

__________

~~-r

________

~

A8TR
IOLR

CFR

DE

S""R

RD,
RD. -----+---'1
I

A8T~~C~~
SVNR/IDloR

-----+-..1

Ta=cf'Cto+7cf'C. Voo= 12V +5%, Vee= 5V ±5%, VBe = ~V± 5%

DC CHARACTERISTICS

limits
Parameter

Symbol Min

Input High Voltage
Input Low Voltage
Output Leakage Current

VIH
VIL
IOL

Output High Voltage
Output Low Voltage
Input Low Current
V DO Supply Current
Vee Supply Current
VBB Supply Current

VOH
VOL
IlL

Fan-out

Typ

Max

Unit
V

3.0

Test Conditions
With Built·in

-20
3.5

100

Icc
IBB
N

15
40
-0.2

0.4
-1.4
20
65
-2.0

rnA
rnA
Standard TTL Load

CAPACITANCE
Parameter
Input Capacitance

Output Capacitance

Symbol Min
CI
COUT

Max

Unit

20
20

pf
pf

Test Conditions
f = 1 MHz
f = 1 Hz

PACKAGE OUTLINE
J.lPD379D

ITEM

MILLIMETERS

A

53.S MAX

1.35

0.05

2.54

0.10

50.80

2.0

1.27

0.05

2.54 MAX

0.10 MIN

1.0MIN

0.04 MIN

4.2 MAX

0.17 MAX

5.2 MAX

0.21 MAX

15.24

M

194

INCHES

2.1 MAX

0.60

13.50

0.53

0.3

0.012

JLPD379
TRANSMITTER STATE DIAGRAM

BASIC
SYNC

DATA

MODE

UNDER RUN

II...,~·"·

..., ......",.. It-

~~~iDd

________ .1_,. .

·0'·,

---

""'M~_
I

r

I

I MS, .....•

I

I

MS, .....•

I

I

I

)

I

/

Ir - -

- --,;-;;;;
- . \.Aii.·'O"

.

RECEIVER STATE DIAGRAM

-~,

~_

. .

"\HR_'."..

•

sN,,~~

DATA

BASIC
SYNC
MODE

I

______1--1-1 ~,~·O"

I ;;;...;.:'_....;.0"_ _ __

,MS,."O"

...

~\IC~-~-----L--- _J
~ - -.'-

..., ......,.. //- - - - T J

,.'.:'0"

I.,....0..

.'iiii.",,·,

........ ,

1.,-''0''

I

I""~""

1
AR-o....
. DATA,

I
I
I

SDLC
MODE

J

/
I

\

I
I

~~"-'
CD SEYEN SUCCESSIVE "'" 's RECEIVED

C!J "CY' RECEIVED AFTER 7-14 IUCCE.IVE ", .. 's.
® OVER ,5IUCCI.IVE ••, .... RECEIVED.

I
I
I

.J
SP379-8-77-GN-CAT

195

P. PD758

PRINTER CONTROLLER
The pPD758 is a digital LSI device desigl'!ed to control SEI KO 101 Series drum-type
impact printers. It can be used with either single or double printer systems_ The
pPD758, ideally sllit~dfor 10\l\l,cost Electronic Cash Register (ECR} systems, frees the
processor from direct control of the printer and simplifies the peripheral circuitry.

DESCRIPTION

Using a few of the possible 18 instructions, the controlling processor need only load
the pPD758 with the characters to be printed, and issue the appropriate print
instruotion_ ThElPPD768 then assumes control of the printer, keeping track of the.
printer drum position and generating hammer drive signals at the approproate time.
The pPp758 also has separate output drives that are under software control. These
an~ typically u~ed to drive the STAMP input to the printer and to provide discrete
drives for BUZZER and CASH BOX functions of the ECR system.
•

Usable with SEIKO 101 Series Printers (CR1P1T[dl, EP101S} and equivalents

FEATURES

• ,ECR Printer and Line Feed Control Capability
• 18 Powerful Instructions
• Controls up to 18 columns
• Controls up to 16 characters
• Input/Output TTL Compatible
• I\I-Ch MOS
• 42 Pin Plastic DIP
• Power Supplies, +12V, +5V and -5V

DB3
DB2
DBl

1>

DBa

HDl

MA

HD2
HD3
HD4
HD5
HP6
Hoi
HD8
HDg

VDD (+12V)
Vee (+5V)

D/I

R/W

Cs
Rp
Tp
JRU
FFD
JFQ
RFD
RPR
JPR
SMP
BUZ
eBX
(OV) vss
(-5V) VBB

19~

pPD
758

HD10
HDll
HD12
HD13
HD14
HD15
HD16
HD17
HD18

PIN CONFIGURATION

,.,. PD758
BLOCK DIAGRAM

APA
JPR
AFD
JFD
JAU
FFD
SPM
BUS
eBX

11
ABSOLUTE MAXIMUM
,
RATINGS*

Cs, 0/1, R!W

08 0 _ 3

Operating Temperature ...... '..
. -10°Cto+70°C
Storage Temperature . .. . . . . .
-40°C, to +125°C
All Input and Output Voltages ...... .
-1 to,+7 Volts H

+3.0

Low Level Clock
Voltage

VL

-O.S

High Level Inp~t
Leakage Current

ILiH

+10

)J.~

VI

= +3.0V

Low Level Input
Leakage Current

ILIL

-10

)J.A

VI

= +O.8V

High Level Output
Lea kage Cu rrent

ILOH

+10

J.iA

Vo

= +3.5V

Low Level Output
Leakage Current

ILOL

-10

)J.A

Vo

= +O.SV

-300

)J.A

VSS

+O.S
VCC
+0.8

V

V

Supply Current

ISS

Supply Current

IDD

17

rnA

Supply Current

ICC

27

rnA

= -S.2SV

197

fL PD758
Ta

= -10

o

to +70 e, VDD

= +12V

PARAMETER

±5%, Vee

SYMBOL

= +5V

MIN.

± 5%, VSS

= OV,

LIMITS
TYP.
MAX.

VBB

= -5V

UNIT

± 5%

CAPACITANCE

TEST
CONDITIONS

Input Capacitance

C IN

10

pF

f

Output Capacitance

COUT

10

pF

f

= 1 MHz
= 1 MHz

TIMING WAVEFORMS
CLOCK { 4>

D/I, R/W
(cs.
DBO - DB3, i'iii11

INPUT

I

DBO

OUTPUT

JRU, FFD, JFD. RFD, RPR,
JPR, SMP, BUZ, CBX,
HD1 - HD18

tA2~ 3.5V
______~.

.•
~~0.~5V~-------

l
TP

INPUT
(FROM PRINTERi

'

Rp

Ta

= -10 to +70°C,

VDD

PARAMETER

= +12V

SYMBOL

Clock Rise and Fall
Time

t r , tf

Clock Pulse Width

,tq,W

Output Delay Time

± 5%, Vec

MIN.

= +5V

± 5%, VSS

LIMITS
TYP. MAX.
50

0.45

2.0

= OV,

VBB

UNIT

± 5%

TEST
CONDITIONS

ns
MS

tA1

430

ns

U'L& CL = 100 pF

tA2

700

ns

U ' L & CL = 100 pF

Input Setup Time

tiS

400

ns

40

ns

Input Hold Time

tlH

Pulse Width for Tp
Input

tpw

2

clock period

Rp Input Setup
Time

tps

0

clock period

Rp Input HoldTime

tpH

3

clock period

198

= -5V

AC CHARACTERISTICS

P. PD758
INSTRUCTION TABLE

INST.
NO.

OPERATION

BUSY

D/I

R/W

1

CHECK bBa FOR BUSY
FLAG STATUS

BFCD

X@

2

STORE DATA (dddd) INTO
BUFFER REGISTER

a

a
a

3a
3b
3c
3d

1
1
1

NO OPERATION

DB
3

2

1

0

a

x

x

X

BF

1

d@

d

d

d

x
a

X

a

X
X
X

b

x
x
X
a

a

1
1
1

1
1
1
1

1

x
1

a

4

PRINT BUFFER REGISTER
CONTENTS TO JOURNAL

a

1

1

a

a

a

1

5

PRINT BUFFER R~GISTER
CONTENTS TO RECEIPT

a

1

1

a

a

1

a

6

PRINT BUFFER REGISTER
CONTENTS TO JOURNAL AND
RECEIPT

a

1

1

1

1

FAST FEED AND STAMP RECEIPT

a

1

1

0
a

a

7

1

a

a

8

PRINT STORED DATA ONTO
JOURNAL AND FEED ONE LINE

a

1

1

a

1

a

1

9

PR INT STORED DATA ONTO
RECEIPT AND FEED ONE LINE

a

·1

1

a

1

1

a

10'

PRINT STORED DATA ONTO
RECEIPT AND JOURNAL AND
FEED BOTH ONE LINE

a

1

1

a

1

1

1

r1'

DRIVE CASH BOX OUTPUT

X

1

1

1

a

a

a

12

DRivE BUZZER OUTPUT FOR
FOUR CHARACTER PERioDS

X

1

1

1

a

a

1

13

RESET BUZZER OUTPUT

X

1

1

1

P

1

a

14

DRIVE BUZZER OUTPUT UNTIL
RESET

15

DRIVE STAMP OUTPUT

16

FEED JOURNAL ONE LINE

17
18

X

1

1

1

a

1

1

1

1

1

1

a

FEED RECEIPT ONE LINE

a
a
a

FEED BOTH RECEIPT AND
JOURNAL ONE LINE

a

1

1

1

1

a
a

1

1

1

1

1

a

1

1

1

1

1

1

1

Notes: CD BF = Busy Flag
G1) X = Don't Care
@
d = Data

PAckAGE OUTLINE
J,lPD758C

~MnmmMmWnnr~i~'Jl::Z- B -

- C -

-FE

- - D

ITEM

MILLIMETERS

A

56.0 MAX

INCHES
2.2 MAX

B

2.6 MAX

0.1 MAX

C

2.54

0.1

0.5 ± 0.1

0.02 ± 0.004

D
E

50.8

F

1.5

2.0
0.059

G

3.2 MIN

0.126 MIN

H
I

0.5 MIN

0.02 MIN

5.22 MAX

0.20 MAX

J

5.72 MAX

0.22 MAX

K

15.24

0.6

L
M

13.2
0.3± 0.1

0.52
0.01 ± 0.004

SP758-8-77-GN-CAT

199

JLPD764

PRINTER CONTROLLER
The /lPD764 is a digital LSI device designed to control SEIKO CR-330 or M-310 rolling
contact printers_ The /lPD764, which is ideally suited for low-cost Electronic Cash Register
(ECR) systems, frees the processorfrom direct control of the printer and simplifies the
peripheral circuitry_

DESCRIPTION

The processor need only load the /lPD764 with the characters to be printed and issue the
appropriate print command. The /lPD764 then assumes control of the printer - positioning
the print wheels, initiating the rolling contact print process, feeding paper and feeding
ribbon.automatically without further processor intervention.
•
•
•
•
•
•
•
•
•
•

Compatible with SEI KO CR-330 and M-310 Printers.
Simple Interface to 4-Bit, 8-Bit and 16-Bit Microprocessors.
23 Powerful Instructions.
4-Bit Data Bus for Print Data and Instruction Inputs.
16 Digit Data Buffer.
16 Trigger Magnet Drive Outputs' for theM-310 and 10 for the CR-330.
Single Phase Clock Input. 300, 400 or 500 kHz Selectable.
Input/Output and Clock TTL Compatible.
N-Channel MO!:;.
Single +5V Power Supply.

Vcc

TM6
TM7

TM5
TM4
TM3
TM2
TMl

™S
TMg

'0 ITM">!

™O
OBO
OBl
OB2
OB3

/lPD

764

q,
JP
RP
10 1
100
CS

Rll
RiO
JSo
JSl

00
01
GNO

200

ST
TP
SS
RESET
MO

WM

R/W

Note:

Pl (TMll)
P2 (™12)
P3 (TM13)
P4 (™14)
P5 (™15)
RR
.


«0

iJu

R/W
cs

TP

TIMER
CIRCUIT
(II)

IDO
10 1
RESET

¢

WM RiO JSO RP
RR
ST Rll' JSl JP
Note:



ns

I

AC CHARACTERISTICS

and 30 pF
Test Load

R1 = 300n/10Kn; R2 = 600n/1 Kn

~ R1

= 300n;

R2

= 600n

r1

Vee

TO
D.U.T

CD

J.

30 pF

.".

R
1

R
2

TEST CIRCUIT
Note:

CD

Including Jig and Probe Capacitance

1.5V

X---- - -- - - - 'I....'.5V
I-;:='PW=::-r-'H~'----

_ _ _ _ _ _ ....1.
ST • •,

OS,

OUTPUT

,svl

.052

\ ' sv

________ ~~w~X,~~--------------

I
~
----_~_'Ej9?-------~~:;L
________ 0/\
~
_ _ _ _'_.,.-Jv

OUTPUT

TIMING WAVEFORMS

'_v_-:--__

r--------'.5--V\·

'pw

------j

/'v

~'c==;j

_______________\~,.'v____

DO

"5V'X--- - -----Y,.5V

------o/~'SET

L

STB or iSS, .OS2

OUTPUT

'H===:j'-----

'5V\~_ _

______ ~P~t.:- ---------

__

ST.

"

~~'_.S_v_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
~tpw

--

1.5V

Note:

208

CD

Alternative Test Load

.sv

LOH

,4
!

VOL

p.PB8212
CAPACITANCE

--+---.

"'---0 DB2

DI2
D02

D 1.3 0---1--1

>-+--.,

...--<>

DI3
DB3
D0 3

CS
DIEN o - - - * - - - - - J

212

~--4H'-----OCS

DIEN

D1EN

os

RESULT

0

0

01 ;Dll

1

0

0

1

1

1

DB" DO
)Hi9h Impedance

JJ. P88216/8226
ABSOLUTE MAXIMUM
RATINGS*

Operating Temperature .. . .
Storage Temperature (Cerdip)

. ... o°c to '70°C
-65°C to +150°C

(Plastic) . . . . . . . . . . . . . . . . . . . . . . . . .
All Output and Supply Voltages
·
All Input Voltages.
·
Output Currents
·

. -0.5 to +7 Volts
-1.3 to +5.5 Volts
. . . . . . . 125 mA

-65°C to+125°C

COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability .

DC CHARACTERISTICS
SYMBOL

PARAMETER

LIMITS
MIN

TYP

CD

MAX

UNIT

TEST CONDITIONS

IF 1

-0.5

rnA

VF

0.45

Input Load Current All
Other Inputs

IF2

-0.25'

rnA

VF

0.45

Input Leakage Curren,!
OlEN. CS

IRl

20

~A

VR -- 5.25V

Input Leakage Current
Dllnputs

IR2

10

~A

VR

Input Forward Voltage

Vc

-1.3

Input Load Current

OlEN.

CS

V

C

525V

IC' -5 rnA

Clamp
Input "Low" Voltage

VIL

Input "High" Voltage

VIH

Output Leakage Current DO
(3-$late)
08

IJl

Power Supply Current

8216
8226

V

10

20
100

pA

lee
lee

130
120

rnA
rnA

Vo

O,45f5.25V

=

15 rnA
25 rnA

0.45

V

DO Outputs IOL
DB Outputs 10L

8216

VOL2

0.6

V

DB Outputs 10L ' 55 rnA

8226

VOL2

0.6

V

DB Outputs 10H

50 rnA

Output "High" Voltage

VOHl

3.65

V

DO Outputs IOH --

1 rnA

Output "High" Voltage

VOH2

2.4

V

DB Outputs IOH

10mA

Output Short Circuit
Current

lOS

Note:

CAPACITANCE

V

VOLl

Output "Low" Voltage
Output "Low" Voltage

0.95
2.0

(j) TYPical values are for Ta

=

-15
·30

25°e, Vee

=

··65
--120

SYMBOL

Input Capacitance

CIN

Output Capacitance

COUTl

Output Capacita.nce

COUT2

Notes:

CD

DO Outputs Vo OV
DB Outputs Vee - 5.0V

5.0V.

"
«
...J
w
0
I-

+10

0

/

:J
0-

I-

24Kn

:J
0
<1

-10

-20
-100

~

L

['SPEC

/"
-50

o

+50

+100

A CAPACITANCE (pF)

Figure 1.

Typical A Output
Delay Versus A Capacitance (pF)
TEST LOAD CIRCUIT

218

p.PD8251
TIMING WAVEFORMS
ClIl,~-----'''- - - - - - '- -

-- --

-----~--------~------~--------~--

tAW

~READ----:-~~~~----------------------~=r~;:~~______~

:to

WRiTE - - - - - - - - - - ' "

'W_C_~-J~--------------

TXE,6fR,RTS _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

BSR,CTS-----------~y~t::---'C-R-_:i--'7---------------------------------

-F

READ

I

READ AND WRITE TIMING

TXC.

I'XBAUDI~L==='TPW-==
-----+d
1=-:=_='_TPD=-=~~::..-.--~'6TXCPERIODS
~
.

T,;C 116x BAUDI

f-'DTX

'

TxD ----~_

..

TRANSMITTER CLOCK AND DATA

RxCIIXB:~:,~~==::'SRX==~+~.:=:=:!'H~RX~'~~-_--__
-INTERNAL
PULSE RxD
SAMPLING

~I------'RPW

---=t---i
---1:
-=~~========~~~~======~n~~~~~~~~~~~~~~~~~
:I.-I.o___- - - - ' R P D

- - - -..

START BIT

R;c (16x BAUO)

.. L-----------

INTERNAL
SAMPLING ______________~I_,,_-------------PULSE

RECEIVER CLOCK AND DATA
RxD

START BIT

DATA BITS

'RX

RXRDY _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

~~

r------'TX1f='-_____

~----------------------------------------------,

TXEMPTY~

~

Tx ROY

WRi'Ti
WRM1A':--.REK'I'N'
GSYTSETART SWITR.ITE 2DnAdTBAYSTIETS
TXD
lQ~I"'r.:!
•

I-

l~

il

I""U
WR ITE 3rd BYTe

(PARITY BIT1STOPl BIT 'START S I T . -

1st DATA BYTe

•

I"

2nd DATA BYTE

TxRDY AND RxRDY TIMING (ASYNC MODE)

RxD

AST BI
!JS

F - C . RESET BY

SVNDET
IOUTPUn-----------------------------------.!.

SOFTWARE
COMMAND

INTERNAL SYNC DETECT

~--,L____j---~~I----J~~L----~--~

~~I~~-~rE~S---U"----------

_______
SYNDET _
_~
(INPUT)
RxD :

'K

=======::. : : jl======~~~=::c=======::J1

..
1-:-,-'- - - - - - 1 s t DATA BYTE------~.I

EXTERNAL SYNC DETECT

Note:

2

~

(TTL)

J

DATA BUS

/).
8

(

CIO

-CS

V
07 - DO

RD

WR

RESET

CLK

8251

221

J.L PD8251
The Receiver Buffer accepts serial data input at the RxD pin and converts the data
from serial to parallel format. Bits orcharacters required for the specific communica·
tion technique in use are checked and then an eight-bit "assembled" character is
readied for the processor. For communication techniques which require less than
eight bits, the IlPD8251 sets the extra bits to "zero."

PIN IDENTIFICATION

PIN
NO.

I

SYMBOL

NAME

Receiver Control Logic

FUNCTION
This block manages a.ll activities related to
incoming data.

14

RxRDY

Receiver Ready

The Receiver Ready output indicates that the
Receiver Buffer is ready with an "assembled"
character for input to the processor. For Polled
operation, the processor can check RxRDY
using a Status Read or RxRDY can be can·
nected to the processor interrupt structure.
Note that reading the character to the pro·
cessor automatically resets RxRDY.

25

RxC

Receiver Clock

3

RxD

Receiver Data

SYNDET

Sync Detect

The Receiver Clock is the rate at which the
incoming character is received. In the Asynchronous mode, the RxC f~!liluency may be 1,16
or 64 times the actual Baud Rate but in the
Synchronous mode the RxC frequency .must
equal the Baud Rate. Two bits in the mode
instruction select Asynchronous at 1x, 16x or
64x or Synchronous operation at 1 x the Baud
Rate.
Unlike TxC, data is sampled by the ILPD8251
on the rising edge of RxC.
A composite serial data stream is received by
the Receiver Control Logic on this pin.
Th'e SYNC Detect pin is only used in the
Synchronous mode. The ILPD8251 may be programmed through the Mode Instruction to
operate in either the internal or external Sync
mode and SYNDET then functions as an output
or input respectively. In the internal Sync mode,
the SYNDET output will go to a "one" when
the ILPD8251 has located the SYNC character
in the Receive mode. If double SYNC
character (bi-sync) operation has been programmed, SYNDET will go to "one" in the
middle of the last bit of the second SYNC
character. SYNDET is automatically reset to
"zero" upon a Status Read or RESET. In the
external SYNC mode, a "zero" to "one" tra~sition on the SYNDET input will cause the
ILPD8251 to start aSsembling data character
on the next falling edge of R'XC. The length of
the SYNDET input should be at least one RxC
period, but may be removed once the
ILPD8251 is in SYNC.

C4

oa

PCo
PC, '
PC2
PC3
PBo
PB,
PB2

07

PIN NAMES
OJ-DO
RESET
CS
RD
WR
AO.A,
PA7'PAO
PB,J'BO
PC,·pCo
VCC
GND

Data Bus (Bt-Directional!
Reset Input

Chip Select
Read Input
Write Input

Port Address

PortA (Bit)
PortB (Bid
Port C (Bid
+5 Volts
o Volts

vcc
pa7
PBa
PBS
PB4
PB3
(

Rev/1
231

,p.PD8255
· General
FUNCTIONAL DESCRIPTION
The UPDS255 Programmable Peripheral Interface (PPIl is designed for use in 8080A
microprocessor systems. Peripheral equipment can be effectively and efficiently
interfaced to the SOSOA data and control busses with the jJPDS255. The IlPDS255 is
functionally configured to be programmed by system software to avoid external logic
for peripheral interfaces.
Data Bus Buffer
The 3·state, bidirectional, eight bit Data Bus Buffer (00-07) of the IlPDS255 can be
directly interfaced to the S080A system Data Bus (00.07). The Data Bus Buffer is
controlled by execution of 'IN and OUT instructions by the 80S0A. Control Words
and Stat!-'s information are also transmitted via the Data Bus Buffer.
ReadlWrite and Control Logic
This block manages all of the internal and external transfers of Data, Control and
Status. Through this block, the processor Address and Control busses can control the
peripheral interfaces.
Chip Select. CS, pin 6
A Logic Low, VIL, on this input enables the IlPDS255 for communication with the
8080A.
'
RD, pin 5
Read,
,
.
A Logic Low, VIL, on this input enables the IlPDS255 to send Data or Status to the
processor via the Data Bus Buffer.
Write, WR, pin 36
A Logic Low, VIL, on this input enables the Data Bus Buffer to receive Data or
Control Words from the processor.
Port Select 0, AO, pin 9
Port Select 1, A1, pin 8
These two inputs are used in conjunction with CS, RD, andiiiiR to control the selection of one of three ports on the Control Word Register. AO and A 1 are usually
connected to AO and At of the processor Address Bus.
Reset, pin 35
A Logic High, VIH, on this input clears the Control Register and sets ports A, B, and
C to the input mode, The input latches in ports A, B, and C are not cleared.
Group I and Group II Controls
Through an OUT instruction in System Software from the processor, a control word
is transmitted to the IlPDS255. Information such as "MODE," "BJt SET," and "Bit
RESET" is used to initialize the functional configuration of each I/O port.

m

accepts "commands" from the ReadlWrite Control Logic and
Each group (I and
"control words" from the internal data bus and in turn controls its associated I/O
ports.
Group I - Port A and upper Port C (PC7·PC4)
Group II - Port B and lower ~ort C (PC3-PCo)
While the Control Word Register can be written into, the contents can not be read
back to the processor.
P~ts A. B, and C
The three S-bit I/O ports (A, B, and C) in the IlPDS255 can all be configured to meet
a wide variety of functional requirements through system software. The effectiveness
and flexibility of the IlPD8255 is further enhanced by special features unique to each
of the ports.
Port A '= An S-bit data output latch/buffer and data input latch.
Port B =An S·bit data input/output latch/buffer and an S-bit data input
.
buffer.
Port C =An'S.bit OUtput latch/buffer and a data input buffer (input not
latched).
Port C may be divided into two !ndependent 4 bit control and status ports for use
with Ports A& B.

232

p.PD8255
POWER

BLOCK DIAGRAM

j,~+5V

SUPPllEST_GND

I/O
PA,-PA g

I/O

F'C,-PC..'
BI-OIRECTIONAL DATA

au

D'.DoC=::::)ll~R

1<:=:::=======::>1
I/O
PCs-Peo

ii6

W-

.

I/O

A,

PB,-PBo

RBET

I!I

ABSOLUTE MAXIMUM
RAnNGS*

Operating Temperature ...•...•••••..•....•.•.. '. . . . . .. O°C to +70°C
Storage Temperature .•........•..••...•...•...•••.. -65°C to +125°C
All Output Voltages 

TAFC

150

n.

@

(S2)

Rd~ or Wr (Ext» Oalay from
Wr~ Delay from st (S3)

st (S2) and

Rdt Delay from U (Sl, SI) and
Wrf Oalay from st (S4)
RdorWr (Active) from8f (Sl)
Rd or Wr (Float) from

st

(SI)

Ad Width (S2-51 or SI)

TRWM

Wr Width (S3-S4)

,

n.

@

ns

@
..@.

TWWM

2TCY+
Te.-5O
TCy-50

Wr (Exd Width (S2-S4)

TWWME

2TCY-50

ris

READY Sat Up Time to Sf (S3, Sw)

TRS

30

ns

READY Hold Time from Sf (S3, Sw)

TAH

20

ns

Notes:

,

I

••

Load = 1 TTL
Load = 1 TTL + 50pF
3 Load = 1, TTl, + (RL = 3.3K), VOH - 3.3V
4 Tracking Specification
5 ATAK <50ns
6 ATOCL < 50 ns
7 ATOCT < 50 ns

241

:

".~, '''i~;·''·:·.

:

,~':...

~

TIMING WAVEFORMS'
DMA (MASTER) MODE

~CONSECUTIVE CYCLES AND BURST MODE SEQUENCE
51

.

SI

I so I

SI

S2

I

S3

I

I _SI I

S4

52

I

S3

I

or .

.

54

I

~:>;tl-~~~~~'-"~~

'..

CLOCK
Tas
DR00-3

'1RO

- t-

-

TDO

-

"'FAAB ..
AD°o-1
iLOWER ADR) ___ ..:
DATAo_7
T FADB .....
(UPPER ADA) ____

~

TSTL_

~

rTAFDB

"TAK

TFAC-IJ~:.

_____
EMRDIIIO RD ___ ......
___
M ,MWRIIIO WR

•

.....

~TSTT

r

I"

T AH ..

-f.--

~

ADDSTB_
DACK0-3

r::.
l;j:

TfL-o

----'I
TRS

!. .

..

I"

--

_ASM

..:::I

-J..

1;: rt

TRH

-0

·~~ ~:=~j~~·~~:d~~T~:~K~·
~
__

.

------4)-

_~

I

.-

.

F:---~T AFC
---r-----fJ.-

~::~~
t===:\

I

51

S2

I

S3~
.... ~

-I
AEL

__ T

_

.54'

I

SI

51

I

51·

CLOCK

Tas

--------- DR00-3
HRO

HS

-""'-----

I-

-

--.-----------

HLOA

--- ILOWERADR)
ADDO·7

--------<=:>-- ----- ----------

DATAo_7
(UPPER ADR)

-------- ADRSTB
----- 5AcK0-3

I-"TDBC

-I
-I

,

I--TAHR

r--------

\.

I---TAHW

\..=H-. -------- TAd
~

J

--- MEMRo/i7O'FiD

-----

MEMWR/I/O WR

,
--_tl~----------Lt===:\::::~-----------------------J{~:::::::::::::,~--------TCIMARK
ts
'\

_____

I

f\.-r\.-.r\.J\.

- --

TWWM

'\

___

50

AEN

'L~-

I-TWWME

TAK .....

I

~THS

r-TAEA

..

~TRWM"""

r--TDCT T DCL

SI

~ t...J\...ru

..

---4"

----)
~-t !"-TASC
j-TDCT

I

T

~r-TAFAB~

~TAHS

I!-;A:-----

7:

READY ___

TCiMARK____

TAET

-0

AEN

SI

--

- ,-___.f

Ie-

T AEL _

I

S4

t-

TOH

THS=:J ....
HlDA

TDo-o

NOT READY SEQUENCE~

tS---CONTROL OVERRIDE SEOUENCE

SI~

JL

t--

--j.t--TRS

READY

1:

'V

C

co
~

UI

......

"'" P08257
DMA OPERATION

Internally the 8257 contains six different states (SO, S1, S2, S3, S4 and SWI. the
duration of each state is determined by the input clock. In the idle state,(S1), no DMA
operation is being executed. A DMA cycle is started upon receipt of one or more DMA
Requests (DRQn), then the 8257 enters the SO state. During state SO a Hold Request
(HRQ) is sent to the 8080 and the 8257 waits in SO until the 8080 issues aHold
Acknowledge (HLDA) back. During SO, DMA Requests are sampled and DMA priority
is resolved (based upon either the fixed or priority scheme). After receipt of HLDA, the
DMA Acknowledge line (DACK n ) with the highest priority is driven low selecting that
particular peripheral for the DMA cycle. The DMA Request line (DRQn) must remain
high until either a DMA Acknowledge (DACK n ) or both DACK n and TC (Terminal
Count) occur, indicating the end of a bl~ck or sector transfer (burst m()de).
The DMA cycle consists of four internal states; S1, S2, S3 and S4. If the access time
oT the memory or I/O device is not fast enough to return a Ready command to the
8257 after it reaches state S3, then a Wait state is initiated (SW). One or more than
one Wait state occurs until a Ready signal is received, and the 8257 is allowed to go
into state S4. Either the extended write option or the DMA Verify mode may
eliminate any Wait state.
If the 8257 should lose control of the system bus (i.e., HLDA goes low) then the
current DMA cycle is completed, the device goes into the S1 state, and n6 more
DMA cycles occur until the bus is reacquired. Ready setup time (tRS), write setup
time (tDW), read data access time (tRD) and HLDA setlip time (tas) should all be
carefully observed during the handshaking mode between the 8257 and the 8080.
During DMAwrite cycles, the I/O Read (I/O R) output is generated at the beginni~g
of state 52 and the Memory Write (MEMW) output is generated at the beginning of
53. During DMA read cycles, the Memory Read (MEMR) output is generated at the
beginning of state S2 and the I/O Write (I/O W) goes low at the beginning of state 53.
No Read or Write control signals are generated during DMA verify cycles.

DMA OPERATION
STATE DIAGRAM

RESET

••

•

Notes:

 V OUT > GND + 0.45V

CAPACITANCE

Ta = 25°C; VCC = GND= OV
LIMITS

UNIT

TEST CONDITIONS

PARAMETER

SYMBOL

Input Capacitance.

CIN

10

pF

fc = 1 MHz

CliO

20

pF

Unmeasured pins
retu roed to G N0

I/O Capacitance

MIN.

TYP.

MAX.

PACKAGE OUTLINE

ITEM

MILLIMETERS

. INCHES

A

51.5 MAX

2.028 MAX

B

1.62

0.064

C

2.54 ± 0.1

0.10± 0.0Q4

0

0.5± 0.1

0.019 ± 0.004

E

48.26

G

1.2MIN
2.54 MIN

1.9
0.047 MIN
0.10MIN

H

0.5MIN

0.019 MIN

1
J

5.22 MAX

0.206 MAX
0.225 MAX

K

5.72 MAX
15.24

L

13.2

0.520

F

M

0.25+ 0. 1
- 0.05

0.600
+ 0.004
0.010 _ 0.002

SP8257-8· 77-GN·CAT

245

~OO~[~~ ~ ~illOOW
j£PD8253
PROGRAMMABL.E INT'ERVAL TIMER
DESCRIPTION
The NEC /lPD8253 is a fully programmable, multi-mode, 16-bit counter/timer_ It is designed as a general purpose device capable
of interfacing directly to an 8080 microprocessor system as an array of I/O ports. The /lPD8253 can generate accurate time
delays under the control of system software. It contains three independent 16-bit counters which can be clocked at rates from
OCto 2 MHz.

FEATURES

PIN CONFIGURATION

• Three Independent 16-Bit Counters

D7

•

DC to 2 MHz

D6

•

Programmable Counter Modes

24

Vee

23

WR

22

RD

D4

4

21

cs

D3

5

20

Al

6

D5

•

Count Binary or BCD

•

Single +5V Supply

D2

•

24 Pin Dual-In-Line Package

D1

• +5V NMOS Technology

2

DO

8

elK 0

9

aUTO

10

IlPD

19

AO

8253

18

elK 2

17

DUT2
GATE 2

elK 1

GATE 0

GATE 1

GND

aUTl

12

~OO~[~~~~illOOW
j£PD8255A
PROGRAMMABLE PERIPHERAL INTERFACE
DESCRIPTION
The NEC /lPD8255A is a programmable peripheral interface device having 24 programmable I/O pins. It is directly compatible
with the 8080 microprocessor system, and normally. no extra logic is required to interface to the 8080A. The system software
can individually program each of the 24 I/O pins into two groups of twelve for the three major modes of operation.

FEATURES
•

Completely TTL Compatible

'. Fully Compatible with NEC /lP Families
•

Direct Bit Set/Reset Capabilities Easing Control
Application Interface

• 40 Pin Dual-In-Line Package
•

Reduces System Package Count

•

Capabilities to Drive Darlington Pairs

246

PIN CONFIGURATION
PA,
PA2
PA,
PAo

PA.
PA5
PAS
PA,

RD

WR

cs

GND
A,
AO
PC,
PCs
PC5
PC.
PCo
PC,

RESET

,.

DO
0,
02
0,
D.
05

Os
0,
VCC
PB,
PBS
PB5
PB,
PB,

~OO~[~~~~illOOW
JLPD8~59

PROGRAMMABLE INTERRUPT CONTROLLER
DESCRIPTION
The NEC J,LPD8259 is a programmable interrupt controller which can handle up to eight vectored priority interrupts in an 8080
microprocessor system. It can be cascaded to extend the vectored priority interrupt capability to 64 without extra circuitry. It is
system software programmable with a selection of priority algorithms avail4116 816/452-3900
DiplomatiSt. Louis Inc. '
St. Louis MO 63144 314/645-8550

New Jersey
'Harvey Electrq!'ll;s
Fairfield NJ 07~ 201/227·1262
Dlplomat/IPC Corp.
, '
Totowa NJ 07512 201/785-1830
DiplomatflPC Corp.
Mount Laurel NJ 08054 609/~34-!l080
New Maxico.
century Electron Ics
Albuquerque NM87123 505/2112-2700
Sterling Electronics
Albuquerque NM 87107 505134~1

New York
Harvey Electronics
Woodbury NY 11797 511?/921 ,87!l~
Diplomat Electronic, Corp.
Woodbury NY 11797 516/921-9373
Summit Distributors. Inc. ,
Bllffalo NY 14202716/804-3450
Summit Elec. of Roch&star, InC.
Rochester NY 14623 711?/442-3494
Zeus Components'
Elmsford NY 10523 91~/592-412O

t.Iortli Carolina
Rasco/Ralalgh
Raleigh NC 21068 919/832-2077
Ohio
Samiconduc;tor Specialists, Inc;.
Dayton 0,", 45414 513/27(i-9455
,Pennsylvania
, Almo Electronics Corp.
Philadelphia PA 19114 215/698-4000
SemlcOoductor Specialists, II1llo
Plttlb4rgh PA 1523B 412/781-81;20

.

'

Taxas
Semiconductor Specl"lists, Inc.
DallaS TX 75220 214/358-5211
Sterilng Electronics.
Dallal! 1X 75229 21,4/357-913'
Sterltflg Electro"i~ "
:. :
HOUlton, TX n02? 713/623-61100

UtaI1'
Century Electronics

Salt Lake City UT 84119 B01/972-6969
Dlplorriat/Alta· Land, Inc.
Selt La~e City UT 84115 801/486-7227
VIrginia
Technico, Inc.
flOanoke VA 24019 7~1563-4975
Washington
Bell Industries
Be!levueWA 98005 206/747-1515
Sterling 'Electronics '
Seenlll W(>. '98108' 206/762-9100

WiJeonsin

SemlconduC!:or Spe~allsts, Inc.
MIlWa'lketWI53226414/257.1330

CANADIAN DISTRIBUTORS
Ontario
Samlepnquctor Specialists, Inc.
Malton, Ontario 4161678-1444
I'u,tura Electronics Corp.
Ottawa, Ontario K1P 5G4 613/232-7757
F.utu!'_ E;lliC:1ronlcs Corp.
.
Rexdale, O!'tarlo 416/~7.782O
Quebet; ,
F'Itu", Ell!CtrOnlcs Corp.
MOntreal, Quebec H41." 2K5 1514/735·5775

I

253

THE pCOM':8 MICROCOMPUTEl{ PROGRAM CARD
This program card provides a concise 'summary of the information necessary for

The only mnemonics and machine codes not actually in the matrices are those for Jump,
Cali, and Return. These entries are listed in separate >tables to the right of the matrices.

programming and operating a JlCOM-B microcomputer system. The full set of 78 instructions is explained in terms of:

Several abbreviations and symbols Ire used on this card as defined below.

• Source/Destination Operations
•

source of data for instruction (vertical)

Assembly Language Mnemonics
d

• Effect on Status Flags
• I nstruction Machine Codes

:: destination of data for instruction (horizontal)

82

•
•

Program Counter Control Instructions
Increment/Decrement Instructions
Shift Instructions
• Restart Instructions
• Special Instructions
• Assembly Language Format

second byte of instruction

8382

second and third bytes of instruction, 82 is least significant byte

( )

contents of register, or register pair as designated by item(s) in parenthesis

(1

contents of memory as addressed by items in brackets

PSW

Program Status Word

SP
The operator of a ~COM·8 can readily determine not only what the IlCOM·8 does,
but all possible sources and destinations of data, the assembly language mnemonics,
the machine codes which implement the instructions, simply by noting the matrix
intersection entri". For example, the intersection of source "{HL)" and destination
"s ~ LReg" in the upper matrix incorporates the mnemonics MOV d,M. This means that
the contents of the memory addressed by the HL register pair can be moved to the L Reg
(the d in the mnemonic represents any of the possible destinations-in this case the
L register). Similarly, the same intersection in the lower matrix contains the entry
"6E," the machine code. for implementing this instruction.

Stack Pointer

PC

Program Counter

Cy

Carry Flag

EXPX

Expression with value limited to the number of bits indicated by X

D8

a·bit data quantity, expression, or constant, always 82 of instruction

D16

16-bit data quantity, expression, or constant, always 8382 of instruction

ADDR

16-bit memory address
'~COM isa trademark of NEe.

NUMERICAL LISTING OF I'COM·8 MACHINE CODES
00

07

NOP
LXI
STAX
INX
INR
OCR
MVI
RLC

08
09

DAD

01
02
03

04
05

06

OA
DB

DC
00

DE
OF
10
11
12

13
14
15
I.

17
18
19
lA
lB
lC
10
IE

IF
20
21
22
23
24
25
2B
27
2.
2.
2A
2B
2C
20
2E
2F

LOAX
DCX
INR
OCR
MVI
RRC
LXI
STAX

,NX
INR
OCR
MVI
RAL
DAD

lOAX
OCX
INR
OCR
MVI
RAR

30

B,016
B
B
B
B
8,08

31
32

33
34
35
3.

37
B
B
B
C
C
C,D8

0,016
0
0
0
0
0,08

0
0
0
E
E
E,08

38
39
3A
3.
3C
30

3E
3F
40
41
42
43
44
45
4.
47
4B
49
4A
4B
4C
40
4E
4F

50
LXI
SI;4LO
INX
INR
OCR
MVI
DAA
DAD
LHt.D

ocx

INR
OCR
MVI
CMA

H,DI6
AOOR
H
H
H
H,DS

H

AOOR
H
L
L

L,08

51
52

53
54
55

56
57
58
59
SA
5B
5C
50

5E
SF

LXI
STA
INX
INR
OCR
MVI
STC

SP,016
AOOR
SP
M
M
M,D8

DAD
LOA
OCX
INR
OCR
MVI
CMe
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOY
MOV
MOV
MOV
MOV
MOV
MOV

SP

60
61
62
63

64
65

66
67
6B

ADOR
SP
A
A

A,08
a,B
B,C
B.O
B.E
B,H
B,L
B,M
B,A
C,B
C.C
C,O
C,E
C,H
C,L
C.M
C,A
O,B
O,C

69
6A
6B

6C
60
6E
.F
70
71

72
73
74
75
7.
77
7B
79
7A
7B
7C
70
7E
7F

.,

eo

0,0

82

O.E
O,H
O,L
O,M
O,A
E,B
E,C
E,O
E,E
E,H
E,L
E.M
E.A

83
64
B5

66
87
BB

B9
6A
8B

BC

eo
8E
8F

HEX ASCII TABLE
0
1
0 NULL
DL' ESCAPE

254 ,

Dct 1

1

START HDG

2
3

START TEXT

DCt 2

END TEXT

DCt 3

4
5
6
7

END TRANS

MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV

MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
HLT
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
ADO
ADO
ADO
ADO
ADO
ADO
ADD
ADO
AOC
AOC
AOC
AOC
AOC
AOC
AOC
AOC

H,B '
H.C
H,O
H,E
H,H
H,L
H,M
H,A
L,B
L,C
L,O
L,E
L,H
L,L
L,M
LA
M,B
M,C
M,O
M,E
M,H
M,L
M,A
A,B
A,C
A,D
A,E
A,H
A,L
A,M
A,A
8
C
0
E
H
L
M
A
0
C
0
E
H
L
M
A

90
91
92
93

94
95

96
97
9B
99
9A
9B
9C
90
9E
9F
AD
AI
A2
A3
A4
AS
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
BO
Bl
.2
B3
B4
B5
B6
B7
BO
B9
BA
BB
BC
00
BE
BF

SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SB.
SBB
SB.
SBB
SBB
SBB
SB.
SB.
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
XRA
XRA
XRA
XRA
XRA
XRA
XRA
XRA
ORA
ORA
ORA
ORA
ORA
ORA
ORA
ORA
CMP
CMP

CMP ..
CMP
CMP
CMP
CMP
CMP

•

C
0
E
H
L
M
A
B
C
0
E
H

l
M
A
B
C
0
E
H
L
M
A
B
C
0
E
H
L
M
A
B
C
0
E
H
L
M
A
B
C
0
E
H
L
M
A

CO
Cl
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CO
CE
CF
DO
01
02
03
04
05
06
07
08
09
DA
DB
DC
00
DE

RNZ
POP
JNZ
JMP
CNZ
PUSH
AOI
RST
RZ
RET
JZ

FO
B

F1

AODR
ADOR
ADOA

F2

B
DB
0

CZ

ADDA

CALL

AOOR
DB
1

ACI
RST
RNC
POP
JNC
OUT
CNC
PUSH
SUI
RST
RC
JC
IN
CC

08
AODR

or
EO

E1
E3
E4
E5
E6
E7
EB
E9
EA
E.
EC
ED

D.

EE
EF

XRI
RST

DB

5

3

4

6

7

@

P

1

A

0

a

Q

p

..

2

8

R

b

r

3
4

C

S

c

s

DCt 4 (STOP)

#
$

D

T

d

t

ENOUIRY

NEG ACK

%

U

SYNC IDLE

&

5
6
7

E

ACK

F

V

f

v
w

.

u

BELL

END TRANS 8LK

G

W

8

BACKSPACE

CANCEL

(

8

H

X

9
h

9

HORIZ TAB

END MEDIUM

)

9

I

Y

;

A

LINE FEED

SUBSTITUTE

J

Z

j

,

B

VERT TAB

ESCAPE

;

K

I

k

(

C

FORM FEED

FILE SEP

<

L

\

)

:

D

RHURN

GROUPSEP

M

)

m

}

E

SHIFT OUT

RECDRDSEP

F

SHIFT IN

UNITSEP

'PATA LINK. tDEVICE CONTROL

N

?

0

-

-

08
7

AODR·

a

>

ADOR

CPI
RST

0
DB
2

I

I

FF

ADD A

EI
CM

ADO A

2

=

"

ADD A
PSW
DB
6

0
AOOA
08

SP

+

F4
F5
F6
F7
F8
F9
FA
FB
FC
FO

PSW
AOOR

SBI
DB
'3
RST
RPO
POP
H
JPO
AOOR
XTHL
CPO
AOOR
PUSH H
ANI
RST
4
RPE
PCHL
JPE
AOOR
XCHG
CPE
ADOR

E2

5

F3

RP
POP
JP
01
CP
PUSH
ORI
RST
RM
SPHL
JM

n
0

x
V

-

DEL,ETE

To form a code
f or any character
on the chart, first
Iocate the character.
The most significant
h ex digit of the code
;s the column num·
ber at the top, and
t he least significant
digit is the row
number at the left.
Example:
The code for A:::: 41
, =2A

NEe 11 com-8 mnemonics 0ma.cbine codes
CARRY FLAG

BIT 0

•

•

•

•

0 0

0 •

• • • •

c.

1

~fict of Operations on Status Flags:

~P=A~R~I~T=Y~F~L~A~G__~B~IT~2~~~~~~r·~·~·~·~·~·~·~·~-+-+-+-+-+-+-i-.+-~~~~+-.~~~~~~.i •
~Z;;,E;;,R",0"",F;:;LA..;,G"-__-"B,,IT~6~~~~~~r·~·+·~·+·+·~·~·~-+-+-+-+-+-+-i-.+-~~~+-+-.~~~~~~.i
t-S:::I::::G:::N:.:F.:L;:;A:::G:....-,...,B:.IT,7:...,H~m~mli·r+i·m·ir·m·~·~·;;r·i!?;t-mr,.ifi;t-;'ii:lm.;;·t-++++~·~:"'::-L:::-I:::':::.i::·~
Bold Face _

C .. U

Q

...

I~

...

:&''''

1#

«

01(

=~~nic,

)~

:,..

Letters are

b b

F~ ~~STRUCT~ONS3!
d:.~r
l ~

Q

%

~ ~ ~~~

8s

i

~

:EG.!.!.-Y9
LU a: ... ... > > a:

A"ect~,

= Cleared.

NOTE
~th Function and Assembly Language

~ ~ 6 6 ~ ~ :;? ::"':":t Sho:~ lor I~struc~io",. ~. :
Used for
&: ~ l
~ :J 1. ! ~ 'to .!. 1. .!. t u iii .. r;: ~ ~
.!. ~ ffi : : :: ~ ~ Byte: of I~:ru:tio~trl:~)n._ ~O:tent I~f
Instruction
« U 0 W :t: =. !!. «
~!!. t !. e 0 ~ ~ ~ ~ ~ ~ ~ ~ 8; g ~ ! ~ ~ ~ ffi ~ ~morv as Addre~ by xx. M "" [HL).
~
t t ! ~ ~ ! ! t + :. ~ ~ -: ~ ~ 5 ! t t ~ ! ft t t t ! ! ! !. ~ ~ g;J,
:E CJ R ~ Register. RP = Register Pair., A =
~:....____+;;.L..;;;.L..;;;.L;;;.L;;;.L;;;.L;;;J...T.;+TTT;;+,;;+,;+,.=+=+=+=..t.;:.t;=+=-+=-+=-+=-+..::.;--=-+..:.tffi e. !: a:
~ ~ Logic AND, V Logic OR, Y .. Exclusive
----a:u
OR
'
B2t-_ _
M_V_I_d,_B,.;2_·-r~~'F~riilTiiir~+=~T=~T=5+..a...,li""l
fr-°"UI;;jTj;JBr=2+++++-++;ii ~ ~!i;
!
~ .
A
IA Regl
k'~~....t-t-STA BaB2 I-'f--H-f~ :5 ~ t U ~
OtHER MNEMONICS
B
u IBRegl
STAXd
I!''' I!'
0:: ~ a:

.. co
ID

0

C

C

0(


C '!$ «
f-I-HHH-t-t-+-+-+-++-1£ ~ i u
~ ~ ~ ~ ~ ~ ~ iii ~
§ - a~

d..

Q

·bi

..

~ ~

e
~

I!!;:
C 0
0 II:

MOV d,M

I

• NO OPERATION
• ENABLE INTERRUPT
• DISABLE INTERRUPT
-HALT
• EXCHANGE ITOP OF STACK I
WITH IHLI
RSTX- RESTART, X - 0-7

(:II-~""=+~Lo:lA~X:;..:.t-:t~t::t-:t-:t-:t-::t-:t-:t-:t-:t-:t-:t!2~-';-B~YqT~E~OP~E]R~A~T~iii~N!lSL[-J:r+-l_--:a::-;;;:-;;;;;;;;;;!CMA

B

o

IB2
IBaB21
BaB2
pop STACK
psw

B

... IN B2 I
:! LOA BaB2

I

lJ.iII :IiIII
:

~_

IHLReg)
ISP)

110.

B
C

o
E

H
L

101
B

o

EW

Regl
Regl
Reg)
Reg)
Reg)
Regl
Regl

7F 47 4F
7B 4C 48
794149
7~ 42 4A
7B~ 4B
7C 44 4C
7 45 40

57 5F 67
77 B7
979 A7
B7
02121J3 32
50 58 60 BB 70 80 BII ~O ~ At ~I BI BE
51 58 6158 71 81 8! 9·1191 AlIA! Bi B9 .
52~~ 82M 72 8211J1 ~2~ A
B2
53 5B83
7383
3
A
54 50 64 6C 74 B4 Be "" lie A4 II(: 8< al
55
B6
75 B5
95

·CoMPLEMENTACCUMULATOR

,.,..,.-:-PC~R~E;:;G::.iIST::-===E~R,..:CO~N~T~R:::O:,:;L;,:M~N=EM~O:N:.:;I:.::CS:::-_.,
.l.I. UNCONDITIONAL JUMP. IJMPI

.3tiI. UNCONDITioNAL CALL ICALLI
3 . UNCONDITIONAL RETURN'·IRET)

.....

ili I-'1XC~H"'iG!.fP~-I .
I
~
~lt

~ ..

PCHl

~~~~~re~~~aa~~~~~~

IA
IB
IC
10
IE
IH
IL

LXI d,B B
pop d

I,

IBC Regl HH--+-+-t-+-H-f-+-++-+-H--+-+_lil"SHLOI-I¥

o

A

I ~HLo Bali
I 'i+I I

i

IAF Reg)

H

SP

I.BYTE OPERimONS

SPHL-

• CONDITIONAL JMP IJXX), CALL ICXX), RET !lXX)
CARRY BIT PARITY BIT ZElie! BIT SIGN ,SIT
0110101010
XX
C
NC
PE
po I Z
NZ
M P
PCHL' IHL) ~ PC REGISTER
lor

SPECIAL INSTRUCTIONS

~~P

I~~ ~: I~~~

:
F3,
CMA 2F
XTHL
PROGRAM COUNTER CONTROL
JMP
C3
CALL CD
~ET
JNZ
C2
CNZ
C4
RNZ
CZ
CC
RZ
J~
CA
JNC
02
RNC
CNC
,,4
~Un45~58~BB
BB
6
RC
JC
oA
CC
DC
(BCI OA
~4J~0 "!l.A~o~S
.• JPO
E2
CPO E4
RPO
(DEI 11\
2·BYTE 0 EF AT 0 ~
IB2 ~
JPE
EA
CPE
EC
RPE
(B3 B21 E3A+-t--t--f-+-HH-t-+-f--t--f--f-+-HI--tI-+-+-+-t--+--f-+-"'~"""A-t--i JP
F2
cP
F4
RP
JIo1
FA
CIo1
FC
RM
01.

:; I

E3.
INSTRUCTIONS
C9
RST 0 C7
CO
RST 1 CF
RST 2 07
CB
00
RST 3 OF
08
R5T 4 E7
EO
RST 5 EF
E8
RST 6 F7
FO
RST 7 FF
F8
PCHL E9

B3B2r:~~~=t=t~~~t=~~~=t=t~~t=~~;r~jE~01~1~1~2~1~'~~I~N~C~R~EM~EN~Tr/~D~E~C~R~E~M~E~NTT~.~SH~I~F~T~I~NiSTrR~U~C~T~I~O~N~S

POP STACK I!ill
Fl Cl 01 El
IAF Regl'-t-I-I-I-HH-t-t-+-++++++++-+-t-+-f.F=5f-I-I-I-H~ IINNRR AB 3C
04
B
IBC Reg) r
'"
o
IDE Reg'
C 5 , . , INR C OC
1-t-1-f-I-HH-t-t-+-+++++++;-+.",....,rf.o3-+-+-~E'=t:~'3INR 0 14
H
IHL Reg)I-t-t-I-t-HH-t-t-+-++++++++-t29'E:.:9t-fE",5t-l-fE",Bt-HE3 INR E lC
SP
15PI
INR H 24
1-_________.:;.ASS=E=M;B;L::.y:"...:L:.:A;::N.:.:G;:U;:.:A;::G::;E:",:F.,:O:.:R~M:::A~T=-----_ _ _ _ _ _-IINR L 2C
PSEUDO INSTRUCTIONS
INR M 34

OCR A 3D
OC~ B 05
OCR C· OD
OCR 0 15
OCR E 10
OCR H 25
OCR L 20
OCR M 35

'psw

SYMBOL MNEMONIC
EXP
ORG
EXP16
OS
EXP 16

Optional
Optional

Required

ROqui.....
Optional
OPtional

Optional

Optional
R_i .....
Optional
Optional

COWotENTS
. Sets location Counter to value of EXP 16

Adds value of EXP 16 to Location Counter
EXP 16
Ptrm. .ntly assignsvllue of EXP'." to "SYMBOL~' specified by user
1050
SET
EXP 16
Temporwily aignsvalue of EXP 16 to "SYMBOL" specified by user
105
DB
EXP 8, EXP 8,... Assigns 'ingle-byte value of expressiOQ{s) toconsecutivememorylbCations
720
OW
EXP 16, EXP 16• ... Assigns double-byte valu. of expression(s) to consecutive memory locatiOns
720
IF
EXP 16
Assembles statements between IF and ENOIF when valui of EXP 16 rF 0
11011B
ENolF Terminates conditional If assembly
001108
MACRO PI, P2
Assigns sta10ment between MACRO and ENoM to "SYMBOL" specifi~
END".
Termin• • MACRO assignments
'TEST'
END
Indicates end of source program
'A' 'B'
EaU

STANDARD SETS
A
SET 7

CONSTANTS
OBoH
lAH

I

INX
INX
INX
INX
oCX
OCX
OCX
oCX

He.

B

SET

0

DKimal

C
o
E

SET
SET
SET

1
2
3

Octal

H

SET

4

L
M
SP
PSW

SET
SET
SET
SET

5
6
6
8

I
I
I

Bino .

I

ASCII

ry

B 03
0 13
H 23
SP33
B OB
0 18
H 2B
SP3B

RLC
RRC
RAL
RAR

07
OF
17
IF

OPERATORS
1,1
",I, MOD, SHL, SHR
+, -

NOT
AND
OR,XOR

255

. Manufacturing
'Operation . .

NEe Quality Assurance
Procedures
One of the important factors
contributing to the final quality of
our memory and microcomputer
components is the attention
given to the parts during the
manufacturing process. All
Production Operations in NEG
follow the procedures of MIL
Standard 883A. Of particular
importance to the reliability
program are three areas that
demonstrate NEG's commitment
to the production of components
of the highest quality.

Visual
Inspection
Method
2010.2 Condo B

I. Burn-In - .AII memory and
microcomputer products are
dynamically burned in at an
ambient temperature sufficient to
bring the junction to a temperature
of 150 °G. The duration of the
burn-in is periodically adjusted
to reflect the production history
and experience Of NEG with each
product. 100% of all NEG memory
and microcomputer products
receive an operational burn-in
stress.
II. Electrical Test - Memory and
microcomputer testing at NEG is
not considered a statistical game
where the device is subjected to a
series of pseudo random address
and data patterns. Not only is this
unnecessarily time consuming,
but it does not effectively
eliminate weak or defective parts.
NEG's test procedures are based
on the internal physical and
electrical organization of each
device and are designed to
provide the maximum electrical .
margin for solid board operation.
For further information on
NEG's testing procedures see your
local NEG representative.
III. After completion of all
100% test operations, production
lots are held in storage
until completion of two groups
of extended sample testing: an
operating life test and a series
of environmental tests. Upon
successful completion of
these tests, the parts are released
from storage and sent to final
Q.A. testing.

256

I
I
I

I

+I
I

I
I

!

'-----~---
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