1977_National_CMOS_Databook 1977 National CMOS Databook

User Manual: 1977_National_CMOS_Databook

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CMOS
INTEGRATED
CIRCUITS

~
Introduction
74C is a CMOS pin for pin, function for function,
equivalent to the 7400 TTLP family. This new
concept in CMOS was designed with the engineer
in mind. Strict design' rules were adhered to in the
input and output' characteristics, such as making
all outputs capable of sinking 360 J.J.A (two LPT2L
loads) and specifying all AC parameters at 50 pF.
loads. These consistent design rules will simplify
system design by giving the engin.eer realistic and
workable parameters. The engineer can take full
advantage of his knowledge of the 7400 line and
utilize the design tricks he has learned.
For those designs that require 400 Series, National
manufactu res these circuits.

© National

Semiconductor Corporation

2900 Semiconductor Drive, Santa Clara, California 95051
(408) 737-5000(TWX (910) 339-9240

Manufactured under one or more of the following U.S. patents: 3083262, 3189758, 3231797,
3303356, 3317671,3323071, 3381071, 3408542, 3421025, 3426423, 3440498, 3518750,
3519897, 3557431, 3560765, 3566218, 3571630, 3575609, 3579059, 3593069, 3597640,
3607469, 3617859, 3631312, 3633052, 3638131, 3648071, 3651565, 3693248.

National does not assume any responsibility for use of any circuitry described; no circuit
patent licenses are Implied, and National reserves the right, at any time without notice, to
change said circuitry.

2

~ Numerical Index and Table of Contents

,

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
CMOS Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Specs 'for "B" Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
54C/74C Power Consumption Characteristics Guide . . . . . . . . . . . . . . . . . . . . . . . . . . 12
CMOS Cross Reference Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

74C DATA SHEETS IN NUMERICAL ORDER
MM54COO/MM74COO Quad 2-lnput NAND Gate .... ~ . . . . . . . . . . . . . . . . . . . . . . 1-3
MM54C02/MM74C02 Quad 2-lnput NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
MM54C04/MM74C04 Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1·3
MM54C08/MM74C08 Quad 2·lnput AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
MM54Cl0/MM74Cl0 Triple 3-lnput NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
MM54C14/MM74C14 Hex Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
MM54C20/MM74C20 Dual 4-lnput NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
MM54C30/MM74C30 8-lnput NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
MM54C32/MM74C32 Quad l-Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
MM54C42/MM74C42 BCD-to-Decimal Decoder . . . . . . . . . . . . . . . . . : ......... 1-18
MM54C48/MM74C48 BCD-to-7 Segment Decoder . . . . . . . . . . ' . . . . . . . . . . . . . . . . 1-20
MM54C73/MM74C73 Dual J-K Flip-Flops withClear . . . . . . . . . . . . . . . . . . . . . . . . 1-24
MM54C74/MM74C74 Dual D Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27
MM54C76/MM74C76 Dual J-K Flip-Flops with Clear and Preset .. ',' . . . . . . . . . . . . 1-24
MM54C83/MM74C83 4-Bit Binary Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30
MM54C85/MM74C85 4-Bit Magnitude Comparator .......................... 1-34
MM54C86/MM74C86 Quad 2-lnput EXCLUSIVE-OR Gate . . . . . . . . . . . . . . . . . . . . 1-7
MM54C89/MM74C89 64-Bit TRI-STATE® Random Access Read/Write Memory ..... 1-37
MM54C90/MM74C90 4-Bit Decade Counter . . . . . . . . . . . . . . . . . . ; . . . . . . . . . . . 1-42
MM54C93/MM74C93 4-Bit Binary Counter ....... .' . . . . . . . . . . . . . . . . . . . . . . 1-42
MM54C95/MM74C95 4-Bit Right-Shift/Left-Shift Register . . . . . . . . . . . . . . . . . . . . 1-46
MM54Cl07/MM74Cl07 Dual J-K Flip-Flops with Clear . . . . . . . . . . . . . . . . . . . . . . 1-24
MM54C150/MM74C150 16-Line to l-Line Multiplexer. . . . . . . . . . . . . . . . . . . . . . . 1-48
MM54C151/MM74C151 8-Channel Digital Multiplexer . . . . . . . . . . . . . . . . . . . . . . . 1-53
MM54C154/MM74C154 4-Line to 16-Line Decoder/Demultiplexer . . . . . . . . . . . . . . . 1-56
MM54C157/MM74C157 Quad 2-lnput Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . 1-59
MM54C160/MM74C160 Decade Counter with Asynchronous Clear .......... ~ ... 1-61
. MM54C161 /MM74C161 Binary Counter with Asynchronous Clear . . . . . . . . . . . . . . . 1-61
MM54C162/MM74C162 Decade Counter with Synchronous Clear . . . . . . . . . . . . . . . 1-61
MM54C163/MM74C163 Binary Counter with Synchronous Clear . . . . . . . . . . . . . . . . 1-61
MM54C164/MM74C164 8-Bit Parallel-Out Serial Shift Register . . . . . . . . . . . . . . . . . 1-65
MM54C165/MM74C165 Parallel-Load 8-Bit Shift Register . . . . . . . . . . . . . . . . . . . . 1-68
MM54C173/MM74C173 TRI-STATE® Quad D Flip-Flop. '. . . . . . . . . . . . . . . . . . . . 1-72
MM54C174/MM74C174 Hex' D Flip-Flop . . . . . . . . . . . . . . : . . . . . . . . . . . . . . . . 1-75
MM54C175/MM74C175 Ouad D Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-78
MM54C192/MM74C192 Synchronous 4-Bit Up/Down Decade Counter . . . . . . . . . . . . 1-81
MM54C193iMM74C193 Synchronous 4-Bit Up/Down Binary Counter . . . . . . . . . . . . 1-81
MM54C195/MM74C195 4-Bit Register . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . 1-84
MM54C200/MM74C200 256-Bit TRI-STATE® Random Access Read/Write Memory ... 1-87
MM54C221/MM74C221 Dual Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . 1-92
MM54C373/MM 74C373 Octal Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-95
MM54C374/MM74C374 Octal D-Type Flip:Flop . . . . . . . . . . . . . _ . . . . . . . . . . . . . 1-95
MM54C901/MM74C901 Hex Inverting TTL Buffer . . . . . . . . . . . . . . . . . . . . . . . . . 1-97
MM54C902/MM74C902 Hex Non-Inverting TTL Buf,fer . . . . . . . . . . . . . . . . . . . . . . 1-97
MM54C903/MM 74C903 Hex I nverting CMOS Buffer . . . . . . . . . . . . . . . . . . . . . . . . 1-97

3

Numerical Index and Table of Contents·
74C DATA SHEETS IN NUMERICAL ORDER (cent.)
MM54C904/MM74C904 Hex Non-Inverting CMOS Buffer . . . . . . . . . . . . . . . . . . . . . 1-97
MM54C905/MM74C90512-Bit Successive Approximation Register . . . . . . . . . . . . . 1-101
MM54C906/MM74C906 Hex Open Drain N-Channel Buffer . . . . . . . . . . . . . . . . . . 1-106
MM54C907/MM74C907 Hex Open Drain P-Channel Buffer . . . . . . . . . . . . . . . . . . . 1-106
MM74C908 Dual CMOS 30 Volt Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-109
MM54C909/MM74C909 Quad Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-113
MM54C910/MM74C9l0 256-Bit TRI-STAT!=® Random Access Read/Write Memory .. 1-118
MM74C911 Display Controller . . . . . . . . . . ' .... ; . . . . . . . . . . . . . . . . . . . . . . . 1-122
MM74C912 Display Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-122
MM74C913 Display Controller. . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . 1-122
MM54C914/MM74C9l4 Hex Schmitt Trigger with Extended Input Voltage . . . . . . . . 1-125
MM54C915/MM74C9l5 7-Segment-to-BCD Converter . . . . . . . . . . . . . . . . . . . . . . 1-128
MM74C918 Dual CMOS 30 Volt Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-109
MM54C920/MM74C920 1024-Bit Static Silicon Gate CMOS RAM . . . . . . . . . . . . . . 1-132
MM54C921/MM74C921 1024-Bit Static Silicon Gate CMOS RAM . . . . . . . . . . . . . . 1-132
MM54C922/MM74C922 16-Key Encoder .... : .. '. . . . . . . . . . . . . . . . . . . . . . . . 1-136
MM54C923/MM74C923 20-Key Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-136
MM74C925 4-Digit Counter with Multiplexed 7-Segment Output Driver ....... _ .. 1-141
MM74C926 4-Digit Cou nter with Multiplexed 7-Segment Output Driver . . . . . . . . . . 1-141
MM74C927 4-Digit Counter with Multiplexed 7-Segment Output Driver . . . . . . . . . . 1-141
MM74C928 4-Digit Counter with Multiplexed 7-Segment Output Driver . . . . . . . . . . 1-141
MM54C929/MM74C929 1024-Bit Static Silicon Gate CMOS RAM . . . . . . . . . . . . . . 1-145
MM54C930/MM74C930 1024-Bit Static Silicon Gate CMOS RAM . . . . . . . . . . . . . . 1-145
MM74C935/MM74C935-1 (ADD3500/ADD3501) 3Y:z-Digit DVM with Multiplexed
7- Segment Output . . . . . . . . . . . . . . . . . . . . . . . . . . ,' . . . . . . . . . . . . . . . 1-149
MM74C936 3~-Digit DVM with Multiplexed 7-Segment Output . . . . . . . . . . . . . . . . 1-158
MM74C937 3Y:z-Digit DVM with Multiplexed BCD Output . . . . . . . . . . . . . . . . . . . 1-158
MM74C938 3~-Digit DVM with Multiplexed BCD Output . . . . . . . . . . . . . . . . . . . 1-158
MM74C948 CMOS 8:Bit A/D Converter with 16-Channel Analog Multiplexer ....... 1-159
MM74C949 CMOS 8-Bit A/D Converter with 8-Channel Analog Multiplexer ........ 1-159
MM74C950 CMOS 8-Bit A/D Converter with 8-Channel Analog Multiplexer and
Sample and Hold ... _ . . . . . . . . . . .' ......... '. . . . . . . . . . . . . . . . . . . . . . . 1-159
MM70C95/MM80C95 TRI-STATE® Hex Buffers . . . . . . . . . . . . . . . . . . . . . . . . . 1-162
MM70C96/MM80C96 TRI-STATE® Hex Inverters . . . . . . . . . . . . . . . . . . . . . . . . 1-162
MM70C97/MM80C97 TRI-STATE® Hex Buffers . . . . . . . . . . . . . . . . . . . . . . . . . 1-162
MM70C98/MM80C98 TRI-STATE® Hex Inverters ... " . . . . . . . . . . . . . . . . . '... 1-162
MM72C19/MM82C19 TRI-STATE® 16-Line to 1-Line Multiplexer.. . . . . . . . . . . . . . . 1-48
MM78C29/MM88C29 Quad Single-Ended Line Driver . . . . . . . . . . . . . . . . . . . . . . 1-167
MM78C30/MM88C30 Dual Differential Line Driver . . . . . . . . . . . . . . . . _ ....... 1-167

CD4000-DATA SHEETS IN NUMERICAL ORDER
CD4000M/CD4000C Dual 3-lnput NOR Gate Plus Inverter . . . . . . . . . . . . . . . . . . . . 2-3
CD4001M/CD4001C Quadruple 2-lnput NOR Gate .......... " . . . . . . . . . . . . . . 2-6
CD4001MB/CD4001BC Quad 2-lnput NOR Buffered B Series Gate . . . . . . . . . . . . . . 2-9
CD4002M/CD4002C Dual4-lnput NOR Gate . . . . . . . . . . . . . . . . ' . . . . . . . . " .... 2-14
CD4006M/CD4006C l8-Stage Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . .2-16
CD4007M/CD4007C Dual Complementary Pair Plus Inverter ..' . . . . . . . . . . . . . . . . . 2-19
CD4008BM/CD4008BC 4-Bit Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-22
CD4909M/CD4009C Hex Buffer (I nverting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-25
CD401 OM/CD401 OC Hex Buffer (Non-I nverting) . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
CD4011 M/CD4011 C Quad 2-1 nput NAN D Buffered B Series Gate . . . . . . . . . . . . . . . 2-27
C;;D4011 BM/CD4011 BC Quad 2-1 nput NAN D Buffered B Series Gate . . . . . . . . . . . . . 2-9
CD4012M/CD4012C Dual4-lnput NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-27
CD4013BM/CD4013BC Dual D Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-29
CD4014M/CD4014C a-Stage Static Shift Register ....... : . . . . . . . . . . . . . . . . . . 2-34
CD4015M/CD4015C Dual 4-Bit Static Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-37
CD4016M/CD4016C Quad Bilateral Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-41

4

Numerical Index and Table of 'Contents
CD4000 DATA SHEETS IN NUMERICAL ORDER (cont.l
CD4017BM/CD4017BC Decade Counter/Divider with 10 Decoded Outputs ......... 2-45
CD4018BM/CD4018BC Presettable Divide-by-N Counter . . . . . . . . . . . . . . . . . . . . .2-50
CD401 9BM/CD401 9BC Quad AN D-OR Select Gate . . . . . . . . . . . . . . . . . . . . . . . . .2-54
CD4020BM/CD4020BC 14-Stage Ripple-Carry Binary Counter/Divider . . . . . . . . . . . . 2-57
CD4021 M/CD4021 C 8·Stage Static Shift Register • . . . . . . . . . . . . . . . . . . . . . . . . . 2-62,
CD4022BM/CD4022BC Divide-by-8 Counter/Divider with 8 Decoded Outputs ....... 2-45
CD4023M/CD4023C Triple 3·lnput NAND Gate, . . . . . . . . . . ' . . . . . . . . . . . . . . . . 2-27
CD4023BM/CD4023BC Triple 3-lnput NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . .2-65
CD4024BM/CD4024BC 7·Stage Ripple·Carry Binary Counter/Divider . . . . . . . . . . . . . 2-69
CD4025M/CD4025C Triple 3·lnput NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-72
CD4025BM/CD4025BC Triple 3-lnput NOR Gate. ',' . . . . . . . . . . . . . . . . . . ' ..... 2·65
CD4027BM/CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset ........ 2-75
CD4028BM/CD4028BC BCD·to·Decimal Decoder . . . . . . . . . . , . . . . . . . . . . . . . . . 2-79
CD4029BM/CD4029BC Presettable Binary/Decade Up/Down Counter . . . . . . . . . . . . 2·82
CD4030M/CD4030C Quad EXCLUSIVE-OR Gate. . . . . . . . . . . . . . . . . . . . . . . . . . 2·88
CD4031BM/CD4031BC 64-Stage Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . 2·91
CD4034BM/CD4034BC S·Stage TRI-STATE® Bidirectional Parallel/Serial
Input/Output Bus Register . . . . . . . . . . . . . . . . . . . . . ' . . . . . . . . . . . . . . . . . . 2·95
CD4035BM/CD4035BC 4·Bit Parallel·ln/Parallel-Out Shift Register . . . . . . . . . . . . . 2·103
CD4040BM/CD4040BC 14-Stage Ripple Carry Binary Counters . . . . . . . . . . . . . . . . . 2-57
CD4041 M/CD4041 C Quad True Complement Buffer ........................ 2·107
CD4042BM/CD4042BC Quad Clocked 0 Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
CD4043M/CD4043C Quad TRI-STATE® NOR R/S Latches . . . . . . . . . . . . . . . . . . 2-115
CD4044M/CD4044C Quad TRI·STATE® NAND R/S Latches . . . . . . . . . . . . . . . . . 2·115
CD4046BM/CD4046BC Micropower Phase-Locked Loop . . . . . . . . . . . . . . . . . . . . 2'·119
CD4047BM/CD4047BC Low Power Monostable/Astable Multivibrator . . . . . . . . . . . 2·126
CD4048BM/CD404SBC TRI-STATE® Expandable S·Function 8-lnput Gate ....... 2·131
CD4049BM/CD4049BC Hex Inverting Buffer . . . . • . . . . . . . . . . . . . . . . . . . . . . . 2·137
CD4050BM/CD4050BC Hex Non-Inverting Buffer. . . . . . . . . . . '.' . . . . . . . . . . . . 2·137
CD4051BM/CD4051 BC Analog Multiplexers/Demultiplexers . . . . . . . . . . . . . . . . . . 2-142
CD4052BM/CD4052BC Analog Multiplexers/Demultiplexers . . . . . . . . . . . . . . . . . . 2·142
CD4053BM/CD4053BC Analog Multiplexers/Demultiplexers.' .. , . . . . . . . . . . . . . . 2·142
CD4060BM/CD4060BC 12-Stage Ripple Carry Binary Counters . . . . . . . . . . . . . . . . . 2-57
CD4066BM/CD4066BC Quad Bilateral Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-150
CD4069M/CD4069C Inverter Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-156
CD4070BM/CD4070BC Quad 2-lnput EXCLUSIVE-OR Gate . . . . . . . . . . . . . . . . . 2·160
CD4Q71 BM/CD4071 BC Quad 2·1 nput OR Buffered B Series Gate . . . . . . . . . . . . . . 2-164
CD4073BM/CD4073BC Double Buffered Triple 3-lnput NAND Gate . . . . . . . . . . . . 2·169
CD4075BM/CD4075BC Double Buffered Triple 3-lnput NOR Gate .•........... 2-169
CD4076BM/CD4076BC TRI-STATE®Quad 0 Flip·Flop . '. . . . . . . . . . . . . . . . . . . 2·173
CD4081BM/CD4081BC Quad 2·lnput AND Buffered B Series Gate . . . . . . . . . . . . . 2·164
C'D40S9BM/CD40S9BC Binary Rate Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . 2·177
CD4093BM/CD4093BC Quad 2-lnput NAND Schmitt Trigger . . . . . . . . . . . . . . . . . 1-184
CD4099BM/CD4099BC 8·Bit Addressable Latches .... , . . . . . . . . . . . . . . . . . . . 2·227
CD401 06BM/CD401 06BC Hex Schmitt T~igger . . . . . . . . . . . . . . . . . . . . . . . . . . 2·189
CD40160BM/CD40160BC Decade Counter with Asynchronous Clear . . . . . . . . . . . . 2·193
CD40161 BM/CD40161 BC Binary Counter with Asynchronous Clear . . . . . . . . . . . . 2-193
CD40162BM/CD40162BC Decade Counter with Synchronous Clear . . . . . . . . . . . . . 2-193
CD40163BM/CD40163BC Binary Counter with Synchronous Clear . . . . . . . . . . . . . 2-193
CD40174BM/CD40174BC Hex 0 Flip·Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19S
CD40175BM/CD40175BC,Quad 0 Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-198
CD401 92BM/CD401 92BC Synchronous 4-Bit l:Jp/Down Decade Counter ......... 2·201
CD401 93BM/CD401 92BC Synchronous 4·B it Up/Down Binary Counter .......... 2-201
CD451 OBM/CD451 OBC BC 0 Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . 2-206
CD4511 BM/CD4511 BC BCD-to-7 Segment Latch Decoder/Driver . . . . . . . . . . . . . . 2·213
CD4516BM/CD4516BC Binary Up/Down Counter . . . . . . . . . . . . , ... "........ 2·206
CD4518BM/CD4518BC Dual Synchronous Up Counter .. " . . . . . . . . . . . . . . . . . . 2·218

5

Numerical Index. and Table of Contents

CD4000 DATA SHEETS IN NUMERICAL ORDER (cont.)
CD4519BM/CD4519BC 4-Bit AN D/OR Selector . . . . . . . . . . . . . . . . . . . . . . . . . . 2-223
CD4520BM/CD4520BC Dual Synchronous Up'Counter . . . . . . . . . . . . . ',' ...... 2-218
CD4527BM/CD4527BC BCD Rate Multipli~r . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-177
CD4723BM/CD4723BCDuaI4-Bit Addressable Latch ......... _ . . . . . . . . . . . . 2-227
CD4724BM/CD4724BC 8-Bit Addressable Latch ...... '..... _ .... _ ......... 2-227

CMOS COMPATIBLE BIPOLAR INTERFACE CIRCUITS
DS1630lE>S3630 Hex CMOS Compatible Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
DS1631/DS3631 Dual Peripheral Driver ...... " . . . . . . . . . . . . . . . . . . . . . . . . 3-6
DS 1632/DS3632 Dual Peripheral Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
DS 1633/DS3633 Dual Peripheral Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
DS 1634/DS3634 Dual Peripheral Driver . . . . . . . . . . . . . . . . . . '.............. 3-6
DS1686/DS3686 Positive Voltage Relay Driver . . . . . . . . . . . . . . '. . . . . . . . . . . . . . 3-12
DS1687/DS3687 Negative Voltage Relay Driver .: . . . . . . . . . . . . . . . . . . . . . . . . .3-14
DS78C20/DS88C20 Dual Compatible Differential Line Receiver . . . . . . . . . . . . . . . . 3-16
ADC0800P (MM4357B/MM5357B) 8-Bit A/D Converter . . . . . . . . . . . . . . . . . . . . .3-19
LM 146/LM246/LM346 Programmable Quad Operational Ampl ifier . . . . . . . . . . . . . . 3-25
LM 195/LM295/LM395 Ultra Reliable Power Transistors . . . . . . . . . . . . . . . . . . . . .3-27

CMOS CONSUMER PRODUCTS
MM5369 Programmable Oscillator Divider . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . 4-3
MM5393 Push Button Telephone Dialer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
MM5395 Touch Tone® Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
MM53100 Programmable TV Timer . . . . . . . . . . . '. . . . . . . . . . . . . . . . . . . . . . . .4·14
• MM53104 TV Game Clock Generator ... " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4·19
MM53105 Programmable TV Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-14
MM55104 Phase Lock Loop Frequency Synthesizer ...... ; ..... : . . . . . . . . . . . .4-22
MM55106 Phase Lock Loop Frequency Synthesizer ........ , . . . . . . . . . . . . . . . .4-22
MM55114 Phase Lock Loop Frequency Synthesizer. .. ; .... ; . . . . . . . . . . . . . . . .4·22
MM55116 Phase Lock Loop Frequency Synthesizer ........ , . . . . . . . . . . . . . . . .4-22
MM5840 TV Channel and Time Circuit ....... : . . . . . . . . . . . . . . . . . . . . . . . . .4-26
MM5841 TV Channel and Time Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-31
MM58106 Digital Clock and TV Display Circuit . . . . . . . . . . . ' . . . . . . . . . . . . . . . .4·35
High Reliability CMOS . . . . . . . . . . . . . ; ... , . . . . . . . . . . . . . . . . . . . . . . . . . .4-39
, A+ Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : . . . . . . . . . . . . .4·42
B+ Program ... ~ . . . . . . . . . . . . . . . . . . . . . . . . . ; . . . . . . . . . . . . . . . . . . . . .4-44

APPLICATION NOTES/BRIEFS
AN-77, CMOS, The Ideal Logic Family . . . . . . . . . . . . . . . . . '.. : . . . . . . . . . . . . . 5-3
AN-88,CMOS Linear Applications . . . . . . . . . . . . . . ; . . . . . . . . . . . . . . . . . . . . .5·11
AN·90, 54C/74C Family Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-14
AN·118, CMOS Oscillators . . . . . . . . . . . . . . . .' . . . . . . . . . . . . . . . . . . . . . . . . .5-20
AN-138, Using the CMOS Dual Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . .5-24
AN·140, CMOS Schmitt Trigger - A Uniquely Versatile Design Component . . . . . . . . . 5-30
AN-165, Dual Polarity 3V,-Digit DVM Realized with Simple CMOS Interface ........ 5-36
AN-l77, Designing with MM74C908/MM74C918 Dual High Voltage CMOS Drivers .... 5-38
DB·5, Keyboard Programmable Divide·by-N Counter with Symmetrical Output ...... 5-50
MB-18, MM54C/MM74C VoltageTranslation/Buffering . . . . . . . . . . . . . . . . . . . . . .5-50

ORDERING INFORMATION & PHYSICAL DIMENSIONS
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6·3
CMOS Packages . . . . . . . . . . . . . . . . . . . . '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

6

n

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CMOS GUide.

en
c

G')

C

m

GATES

GATES (cont.)

MM54COO/MM74COO Quad 2-lnput NAND Gate

CD4075BM/CD4075BC Double Buffered Triple 3-lnput
NOR Gate

MM54C02/MM74C02 Quad 2-lnput NOR Gate
MM54C04/MM74C04 Hex Inverter

CD4081BM/CD4081BC Quad 2-lnput AND Buffered B
Series Gate

MM54C08/MM74C08 Quad 2-lnput AND Gate

CD4519BM/CD4519BC 4-Bit AND/OR Selector

MM54C10/MM74C10Triple 3-lnput NAND Gate

BUFFERS

MM54C20/MM74C20 Dual 4-lnput NAND Gate

MM54C901/MM74C901 Hex Inverting TTL Buffer

MM54C30/MM74C30 8-.lnput NAND Gate

MM54C902/MM74C902 Hex Non-Inverting TTL Buffer

MM54C32/MM74C32 Quad 2-lnput OR Gate

MM54C903/MM74C903 Hex Inverting PMOS Buffer

MM54C86/MM74C86 Quad 2-lnput EXCLUSIVE-OR
Gate

MM54C904/MM74C904 Hex Non-Inverting PMOS
Buffer
.

CD4000M/CD4000C Dual 3-lnput NOR Gate Plus
Inverter

MM54C906/MM74C906 Hex Open Drain N-Channel
Buffer

CD4001M/CD4001C Quadruple 2-lnput NOR Gate

MM54C907/MM74C907 Hex Open Drain P-Channel
Buffer

CD4001 BM/CD4001 BC Quad 2-lnput NOR Buffered B
Series Gate

MM74C908 Dual CMOS 30 Volt Driver

CD4002M/CD4002C Dual 4-lnput NOR Gate

MM74C918 Dual CMOS 30 Volt Driver

CD4007M/CD4007C Dual Complementary Pair Plus
Inverter

MM70C95/MM80C95 TRI-STATE@ Hex Buffers

CD4011M/CD4011C Quad 2-lnput NAND Buffered B
Series Gate

MM70C96/MM80C96 TRj-STATE® Hex Inverters
MM70C97/MM80C97 TRI-STATE® Hex Buffers

CD4011 BM/CD4011 BC Quad 2-1 nput NAN D Buffered
B Series Gate

MM70C98/MM80C98 TRI-STATE® Hex Inverters

CD4012M/CD4012C Dual 4-lnput NAND Gate

MM78C29/MM88C29 Quad Single-Ended Line Driver

CD4019BM/CD4019BC Quad AND-OR Select'Gate

MM78C30/MM88C30 Dual Differential Line Driver

CD4023M/CD4023C Triple 3-lnput NAND Gate

CD4009M/CD4009C Hex Buffer (Inverting)

CD4023BM/CD4023BC Triple 3-lnput NAND Gate

CD4010M/CD4010C Hex Buffer (Non-Inverting)

CD4025M/CD4025C Triple 3-lnput NOR Gate

CD4041 M/CD4041C Quad True/Complement Buffer

CD4025BM/CD4025BC Triple 3-lnput NOR Gate

CD4049BM/CD4049BCHex Inverting Buffer

CD4030M/CD4030C Quad EXCLUSIVE-OR Gate

CD4050BM/CD4050BC Hex Non-Inverting Buffer

CD4048BM/CD4048BC TR I-STATE@ Expandable
8-Functio'n 8-lnput Gate

DS1630/DS3630 Hex CMOS Compatible Buffer

CD4069M/CD4069C Inverter Circuits

DS78C20/DS88C20 Dual Compatible Differential Line
Receiver

CD4070BM/CD4070BC Quad 2-lnput EXCLUSIVE-OR
Gate

LM 195/LM295/LM395 Ultra Reliable Power Transistors

CD4071BM/CD4071BC Quad 2-lnput OR Buffered B
Series Gate

FLIP-FLOPS
MM54C73/MM74C73 Dual J-K Flip-Flops with Clear

CD4073BM/CD4073BC Double Buffered Triple 3-lnput
NAND Gate

MM54C74/MM74C74 Dual D Flip-Flop

7

CMOS Guide

F LlP·FLOPS (cent.)

COUNTERS (cent.)

MM54C76/MM74C76 Dual J-K Flip-Flops with Clear
and Preset

MM54C193/MM74C193 Synchronous 4-Bit Up/Down
Binary Counter

MM54Cl07/MM74Cl07 Dual J-K Flip-Flops with Clear

MM74C925 4-Digit Counter with MUltiplexed 7-Segment
Output Driver

MM54C173/MM74C173 TRI-STATE@QuadDFlip-Flop

MM74C926 4-Digit Counter with Multiplexed 7-Segment
Output Driver

MM54C174/MM74C174 Hex D Flip-Flop
MM54C175/MM74C175 Quad D Flip-Flop

MM74C927 4-Digit Counter with Multiplexed 7-Segment
Output Driver

MM54C373/MM74C373 Octal Latch

MM74C928 4-Digit Counter with Multiplexed 7-Segment
Output Driver

MM54C374/MM74C374 Octal D-Type Flip-Flop
CD4013BM/CD4013BC Dual D Flip-Flop
CD4027BM/CD4027BC Dual J-K Master/Slave Flip-Flop

CD4017BM/CD4017BC Decade Counter/Divider with
10 Decoded Outputs

with Set and Reset

CD4018BM/CD4018BC Presettable Divide-by-N Counter

CD4042BM/CD4042BC Quad Clocked D Latch

CD4020BM/CD4020BC 14-Stage Ripple-Carry Binary
Counter/Divider

CD4043M/CD4043C Quad TRI-STATE@NOR R/S
Latches

CD4022BM/CD4022BC Divide-by-8 Counter/Divider
with 8 Decoded Outputs

CD4044M/CD4044C Quad TRI-STATE@NAND R/S
Latches .

CD4024BM/CD4024BC 7-Stage Ripple-Carry Binary
. Counter/Divider

CD4076BM/CD4076BC TRI-STATE@Quad D Flip-Flop

CD4029BM/CD4029BC Presettable Binary/Decade
Up/Down Counter

CD4099BM/CD4099BC 8-8 it Addressable Latches

CD4040BM/CD4040BC 14-Stage Ripple Carry Binary
Counters

CD40174BM/CD40174BC Hex D Flip-Flop
CD40175BM/CD4017,5BC Quad D Flip-Flop

CD4060BM/CD4060BC 12-Stage Ripple Carry Binary
Counters

CD4723BM/CD4723BC Dual 4-Bit Addressable Latch
CD4724BM/CD4724BC 8-Bit Addressable Latches

CD40160BM/CD40160BC.Decade Counter with
Asynchronous Clear

COUNTERS

CD40161BM/CD40161BC Binary Counter with
Asynchronous Clear

MM54C90/MM74C90 4-Bit Decade Counter
MM54C93/MM74C93 4-Bit Binary Counter

CD40162BM/CD40162BC Decade Counter with
Synchronous Clear

MM54C160/MM74C160 Decade Counter with
Asynchronous Clear

CD40163BM/CD40163BC Binary Counter with
Synchronous Clear

MM54C161/MM74C161 Binary Counter with
Asynchronous Clear

CD40192BM/CD40192BC Synchronous 4-Bit Up/Down
Decade Counter, .

MM54C162/MM74C162 Decade Counter with
Synchronous Clear
.

CD40193BM/CD40193BC Synchronous 4-Bit Up/Down
Binary Counter

MM54C163/MM74C163 Binary Counter with
Synchronous Clear

CD451 OBM/CD451 aBC BCD Up/Down Counter
CD4516BM/CD4516BC Binary Up/Down Counter

MM54C192/MM74C192 Synchronous 4-Bit Up/Down
Decade Counter

CD4518BM/CD4518BC Dual Synchronous Up Counter

8

n

s::
o
en

CMOS Guide

G')

c

C

m

COUNTERS (cont.)

DECODER-S/MUL TlPLEXERS (cont.)

CD4520BM/CD4520BC Dual Synchronous Up Counter

CD4052BM/CD4052BC Analog Multiplexers/
Demultiplexers

MM5369 Programmable Oscillator Divider
CD4053BM/CD4053BC Analog Multiplexers/
Demultiplexers -

SHIFT REGISTERS

CD4066BM/CD4066BC Quad Bilateral Switch

MM54C95/MM74C95 4-Bit Right Shift Left Shift Register
CD4511BM/CD4511BC BCD-to-7 Segment Latch
Decoder/Driver

MM54C164/MM74C164 8-Bit Parallel-Out Serial Shift
Register
MM54C165/MM74C165 Parallel-Load 8-Bit Shift
Register

MEMORIES

CD4006M/CD4006C l8-Stage Static Shift Register

MM54C89/MM74C89 64-BitTRI-STATE@Random
Acce_ss Read/Write Memory

CD40l4M/CD40l4C 8-Stage Static Shift Register

MM54C200/MM74C200 256-Bit TRI-STATE@ Random
Access ReadlWrite Memory

CD40l5M/CD4015C Dual 4-Bit Static Register

MM54CD10/MM74CD10 25(3-[3 it TRI-STATE(I<) Random
Access Read/Write Memory

CD4021M/CD4021C 8-Stage Static Shift Register
CD4031BM/CD4031BC 64-Stage Static Shift Register

- MM54C920/MM74C920 1024-Bit Static Silicon Gate
CMOS RAM

CD4034BM/CD4034BC 8-Stage TRI-STATE@
Bidirectional Parallel/Serial Input/Output Bus Register

MM54C921/MM74C921 1024-Bit Static Silicon Gate
CMOS RAM

CD4035BM/CD4035BC 4-Bit Parallel-I n/Parallel-Out
Shift Register

MM54C929/MM74C929 1024-Bit Static Silicon Gate
CMOS RAM
MM54C930/MM74C930 1024-Bit Static Silicon Gate
CMOS RAM

DECODERS/MUL TIPLEXERS
MM54C42/MM74C42 BCD-to-Decimal Decoder

ARi"THMETIC FUNCTIONS

MM54C48/MM74C48 BCD-to-7 Segment Decoder
MM54C83/MM74C83 4-Bit Binary Full Adder
MM54C150/MM74C150 16-Line to l-Line Multiplexer
MM54C85/MM74C85 4-Bit Magnitude Comparator
MM54C15l/MM74C151 8-Channel Digital Multiplexer
CD4008BM/CD4008BC 4-Bit Full Adder
MM54C154/MM74C154 4-Line to l6-Line Decoder/
Demultiplexer
r

SPECIAL FUNCTIONS
MM54C157/MM74C157 Quad 2-lnput Multiplexer
MM54C14/MM74C14 Hex Schmitt Trigger
MM54C922/MM74C922 16-Key Encoder
MM54C221/MM74C221 Dual Monostable Multivibrator
MM54C923/MM74C923 20-Key Encoder
MM54C909/MM74C909 Quad Comparator
MM74C19/MM82C19 TRI-STATE@16-Line to l-Line
Multiplexer

- MM74C911 Display Controller

CD40l6M/CD4016C Quad Bilateral Switch

, MM74C912 Display Controller

CD4028BM/CD4028BC BCD-t6-Decimal Decoder

MM74C913 Display Controller

CD4051BM/CD4051BC Analog Multiplexers/
Demultiplexers

MM54C914/MM74C914 Hex Schmitt Trigger with
Extended Input Voltage

9

CMOS Guide

SPECIAL FUNCTIONS (cont.)

SPECIAL FUNCTIONS (cont.)

MM54C915/MM74C915 7-Segment-to-BCD Converter

LM 146/LM246/LM346 Programmable Quad Operational
Amplifier

MM74C935/MM74C935-1 (ADD3500/ADD3501)
3y:!-Digit DVM with Multiplexed 7-Segment Output

MM5393 Push Button Telephone Dialer

MM74C936 3%-Digit DVM with Multiplexed 7-Segment
Output

MM5395 Touch Tone® Generator
MM53100 Programmable TV Timer

MM74C937 3Y:!-Digit DVM with Multiplexed BCD
Output

MM531D,4 TV Game Clock Generator
MM53105 Programmable TV Timer

MM74C938 3%-Digit DVM with Multiplexed BCD
Output

MM55104 Phase Lock Loop Frequency Synthesizer

CD4046BM/CD4046BC Micropower Phase-Locked Loop

MM55106 Phase Lock Loop Frequency Synthesizer

CD4047BM/CD4047BC Low Power Monostable/Astable
Multivibrator

MM55114 Phase Lock Loop Frequency Synthesizer

CD4089BM/CD4089BC Binary Rate Multiplier

MM55116 Phase ~ock Loop Frequency Synthesizer

CD4093BM/CD4093BC Quad 2-lnput NAND Schmitt
Triggcr
'

MM5840 TV Channel and Time Circuit
MM5841 TV Channel and Time Circuit

CD401 OGBM/CD401 06BC Hcx Schmitt Trigger

MM58106 Digital Clock and TV Display Circuit

CD4527BM/CD4527BC BCD Rilte Multiplier

A-TO-D CONVERTERS

DS1631/DS3631 Dual Peripheral Driver

MM74C948 CMOS 8-Bit A/D Converter with 16-Channel
Analog Multiplexer

OS 1632/DS3632 Dual Peripheral Driver
DS1633/DS3633 Dual Peripheral Driver

MM74C949 CMOS 8-Bit A/D Converter with 8-Channel
Analog Multiplexer

OS 1634/DS3634 Dual Peripheral Driver
DS1686/DS3686 Positive. Voltage Relay Driver

MM74C950 CMOS 8-Bit A/D Converter with 8-Channel
Analog Multiplexer and Sample and Hold

DS1687/DS3687 Negative Voltage Relay Driver

ADC0800P (MM4357B/MM5357B) 8-Bit A/D Converter

10

tn

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Specifications for

~~B"

"0

Series

m

n

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n

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o

National Semiconductor complies with the CMOS "B" Series specification as called out in JEOEC Standard No. 13A. All parts called out as "B"
are double buffered and will meet as a minimum the electrical parameters listed in table A. As agreed upon. in the JEOEC Spec. products called
out as UB are not double buffered but meet table A specifications with the exception of VI L and VI H. which will be 20% and BO%. respectively.
of VOO. The 54C/74C family meets or exceeds the "B"/"UB" specifications as given in table A but are not marked "B"/"UB."

Z

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Limits
Temp
Range

Parameter

100

Quiescent
Device Current
GATES

VIL

Input Low
Voltage

- Conditions

Min

Typ

Max

THIGH*
Min
Max

Units

VI = VSS or VOO

0.25
0.5
1.0

0.25
0.5
1.0

7.5
15
30

/JAdc

1.0
2.0
4.0

7.5
15
30

/lAdc

Mil

Comm

5
10
15

All valid input combinations

1.0
2.0
4.0

Mil

5
10
15

VI = VSS or VOO

1.0
2.0
4.0

1.0
2.0
4.0

30
60
120

/JAdc

Comm

5
10
15

All valid input combinations

4.0
B.O
16.0

4.0
8.0
16.0

30
60
120

/lAdc

Mil

5
10
15

VI = VSS or VOO

5
10
20

5
10
20

150
300
600

jlAdc

Comm

5
10
15

All valid input combinations

20
40
80

20
40
80

150
300
600

!JAdc

All

'5
10
15

VI = VSS or VOO
1101 < l/JA

0.05,
0.05
0.05

0.05
0.05
0.05

0.05
0.05
0.05

5
10
15

VI = VSS or VOO
1101 < l/lA

5
10
15

VO= 0.5Vor 4.5V. 1101 < l/JA
VO= 1.0Vor9.0V. 1101 < l/JA
Va = 1.5Vor 13.5V.1I01 < 1 /JA

MSI

High-Level
VOH Output Voltage

+25°C

TLOW·
Min
Max

5
10
15

BUFFERS.
FLIP-FLOPS

Low:Level
VOL Output Voltage

VOO
(Vdc) .

All-

All

-

,4.95
9.95
14.95

4.95
9.95
14.95
1.5
3.0
4.0

4.95
9.95
14.95
1.5
3.0
4.0

Vdc

.---Vdc

Vdc

._--

VIH

Input High
Voltage

All

5
10
15

Va = 0.5Vor4.5V. 1101 < 1 /JA
Va = 1.0 V or 9.0V. 1101< l/JA
Va = 1.5Vor 13.5V.1101 < l/JA

3.5
7.0
11.0

3.5
7.0
11.0

3.5
7.0
11.0

10L

Output Low
(Sink) Current

Mil

5
10
15

Va = 0.4 V. V I = 0 V or 5 V
Va = 0.5V. VI = OVor 10V
Va = 1.5V. VI = OVor 15V

0.64
1.6
4.2

0.51
1.3
3.4

0.36
0.9
2.4

Comm

5
10
15

Va = O".4V. VI- OVor5V
Va = 0.5V. VI a OVor 10V
Va = 1.5V. VI - OVor 15V

0.52
1.3
3.6

0.44
1.1
3.0

0.36
0.9
2.4

mAdc

Mil

5
10
15

VO=4.6V.VI-OVor5V·
Va = 9.5V. VI - OVor 10V
Va = 13.5V. VI - 0 Vor 15V

-0.25
-0.62
-loB'

-0.2
-0.5
-1.5

-0.14
-0.35
-1.1

mAdc

Comm

5
10
15

VO=4.6V.VI-OVor5V
Va = 9.5V. VI - OV or 10V
Va = 13.5V. VI- OVor 15V

-0.2
-0.5
-1.4

-0.16
-0.4
-1.2

-0.12
-0.3
-1.0

mAdc

10H

Output High
(Source) Current

II

Input Current .

Mil
Comm

J5
15

VI=OVor15V
VI=OVor15V

CI

Input
Capacitance
per Unit Load

All

--

Any Input
... _- .-

±0.1
±0.3

±0.1
±0.3
7.5

-

Note: For current flow the convention is positivu for current flowing into the device and negative flowing out of the device.
*TLOW • -55°C for Military Temp Range device, -40'C for Commercial Temp Range device.
·THIGH a +125°C for Military Temp Range dovlcCl, IIl&"C for Commercial Temp Rango device.

11

Vdc

---mAdc

11.0
11.0

m

tn

._-1.5
3.0
4.0

tn
m
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/JAdc
/JAdc
pF

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C!'
CI)'

(.)

~
~

rx:

~

54C/74C Power Consumption
Characteristics G,uide
Typical characteristics T A = 25°C.

(.)
~

a:

~

J:

(.)

Z

0

i=
Q.
:E
:::J

CI)

Z

0

(.)

rx:

W

~

0

Q.

(.)

r:t

"

(.)
~

in

=
= 5.0V

(Note ~)

W

I-

tpd (ns)
CL 50 pF

cPo
(pF)

DEVICE TYPE/PRODUCT DESCRIPTION

MM54COO/MM74COO Quad 2·lnput NAND Gate
MM54C02/MM74C02 Quad 2·lnput NOR Gate
MM54C04/MM 74C04 Hex Inverter
MM54C08/MM74C08 Quad 2·lnput AND Gate
MM54Cl OfMM74Cl 0 Triple 3-lnput NAND Gate
MM54C14/MM74C14 Hex Schmitt Trigger
MM54C20/MM74C20 Dual 4-lnput NAND Gate
MM54C30/MM74C30 a·lnput NAND Gate
MM54C32/MM74C32 Quad 2·lnput OR Gate
MM54C42/MM74C42 BCD·to·Decimal Decoder
MM54C48/MM74C48 BCD·to·7 Segment Decoder
MM54C73/MM74C73 Dual J·K Flip-Flop
MM54C74/MM74C74 Dual 0 Flip-Flop
MM54C76/MM74C76 Dual J·K Flip·Flop
MM54C83/MM74C83 4·Bit Binary Full Adder
MM54C85/MM74C85 4-Bit Magnitude Comparator
MM54C86/MM74C86 Quad 2-lnput EXCLUSIVE·OR Gate
MM54C89/MM74C89 64-bit.tRI·STATE® Random Access Memory
MM54C90fMM74C90 4-Bit Decade Counter
MM54C93/MM74C93 4·Bit Binary Counter
MM54C95/MM74C95 4·Bit R-SfL·S Register
MM54Cl07/MM74Cl07 Dual J-K Flip·Flop
MM54C150fMM74C150 16:1 Multiplexer
MM54C151 /MM74C 151 8-Channel Digital Multiplexer
MM54C 154/MM 74C 154 4: 16 DecoderlDemultiplexer
MM54C157/MM74C157 Quad 2-lnput Multiplexer
MM54C160/MM74C160 Sync Decade Counter
MM54C161/MM74C161 Sync 4·Bit Binary Counter
MM54C162/MM74C 162 Sync Dec
4.05
:;

~

0.5

I

a::

10'

10'

to'

~

TOTAL POWER· Vee' x , x (Cpo. Cl

).

Vee

to

5.0

FREQUENCY (Hz)

VIN (0)

15

4.50V

Vee - POWER SUPPL Y VOL TAGE (V)

tpd I

IlEAKAGE

I

'
Cl

2.5
1.5

1.45
0.45

I

I

to'

3.05

(C - 501 pF"

"c

l>;;" • tpdl

Vee

.
Cl "50 pF

For complete explanation on use ot curves see application note AN-gO, 54C174C Family Characteristics.

12

10V

15V

(')

~

:XJ

Cross Reference Guide

o

(J)
(J)

:XJ

m
"T1
m
:XJ

m
Z

(')

m

G')
National
MM74COO
MM74C02
MM74C04
MM74C08
MM74C10
MM74C14
MM74C20
MM74C30
MM74C32

RCA

CD4069

CD40106

MM74C42
MM74C48
MM74C73
MM74C74
MM74C76
MM74C83
MM74C85
MM74C86
MM74C89
MM74C90

MM74C164
MM74C165
MM74C173
MM74C174
MM74C175
MM74C192
MM74C193
MM74C195
MM74C200
MM74C221

HD74COO
HD74C02
HD74C04
HD74C08
HD74C10
HD74C14
HD74C20
HD74C30
HD74C32
HD74C42
HD74C48
HD74C73
HD74C74
HD74C76

{CD4030
CD4070B

MM74C93
MM74C95
MM74C107
MM74C151
MM74C154
MM74C157
MM74C160
MM74C161
MM74C162
MM74C163

Harris

\

CD4076

CD40192
CD40193

MM74COO
MM74C02
MM74C04

340014

MM74C73
MM74C74
MM74C76

MC14507

MM74C95

MM74C157
MM74C160
MM74C161
MM74C162
MM74C163

HD74C164
HD74C165
HD74C173
HD74C174
HD74C175

MM74C164

HD74C192
HD74C193
HD74C195
HD74C200
HD74C221

MM74C192
MM74C193
MM74C195

MM74C173

MC14160
MC14161
MC14162
MC14163

TP4360
TP4361
TP4362
TP4363

F340160
F340161
F340162
F340163

MC14076
MC14174
MC14175

F340174
F340175

MC14192
MC14193
MC14195

F340192
F340193
F340195

MC14503

F340097
F340098

HD80C95
HD80C98

13

c:

m

--

MM74C42

HD74C157
HD74C160
HD74C161
HD74C162
HD74C163

HD74C906
HD74C907

Fairchild

C

MC14584

MM74C151
MM74C154

MM74C906
MM74C907
MM74C908
MM74C918
MM80C95

TI

MM74C20

HD74C95
HD74C107
HD74C151
HD74C154

HD74C901
HD74C902
HD74C903
HD74C904

Motorola

MM74C10

HD74C83
HD74C85
HD74C86
HD74C89

MM74C901
MM74C902
MM74C903
MM74C904
MM74C905

MM80C97
MM80C98
MM88C29
MM88C30

Teledyne

MM54COO/MM74COO quad two-input NAN D gate
MM54C02/MM74C02 quad two-input NOR gate
MM54C04/MM74C04 hex inverter
MM54C10/MM74C10 triple three-input NAND gate
MM54C20/MM74C20 dual four-input NAND gate
general description

features

These logic gates employ complementary MOS
(CMOS) to achieve wide power supply operating
range, low power consumption, high noise immunity and sy~metric controlled rise and fall
times. With features such as this the 54C/74C
logic family is close to ideal for use in d,igital
systems. Function and pin out compatibility with
series 54/74 devices minimizes design time for
those designers already familiar with the standard
54/74 logic family.

•

Wide supply voltage range

•

Guaranteed noise margin

•

High noise immunity

•

Low power
consumption

All inputs are protected from damage due to
static discharge by diode clamps to Vee and GND.

•

3.0V to 15V
1.0V
0.45 Vee typo

10 nW/package typo
fan out of 2
driving 74L

Low power
TTL compatibility

connection diagrams

MM54COO/MM74COO

MM54C02/MM74C02

MM54C04/MM74C04

TOP VIEW

TOP VIEW

TOP VIEW

MM54C10/MM74C10

MM54C20/MM74C20

TOP VIEW

1·3

absolute maximum ratings

(Note 1)

Voltage at Any.Pin
Operating Temperature Range
54C
74C
Storage Temperature Range
Operating Vee Range
Maximum Vee Voltage
Package Dissipation
Lead Temperature (Soldering, 10 seconds)

-0.3V to Vee + 0.3V
-55°C to +125°C
0
-40 C to +85° C
-65°C to +150°C
3.0V to 15V
18V
500 mW
300°C

dc electrical characteristics
Min/max limits apply across the guaranteed temperature range unless otherwise noted.
PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

CMOS TO CMOS
Logical "I" Input Voltage (V IN III)

Vee; 5.0V
Vee; 10V

Logical "0" Input Voltage (VINIOI)

Vee; 5.0V
Vee; 10V

Logical ''1'' Output Voltage (V o.UTi1I )

Vee ~ 5.0V, 10. ; -101lA
Vee; 10V, 10. '" -10pA

Logical "0" Output Voltage (V o.UT (01)

Vee; 5,OV, 10. ; +10pA
Vee; 10V, 10. ; +10pA

'V
V

3.5
8.0
1.5
2.0

Logical "I" Input Current {liN Ill)

Vee; 15V, V IN

= 15V

Logical "0" Input Current (IINIQ))

Vee; ,15V, V IN

= OV

Supply Current {Ieel

Vee; 15V

V
V

4.5
9,0
0,5

0,005
-1.0

V
V

1.0

V
V

1.0

/JA

-0.005
0.01

/JA
,15

/JA

LOW POWER TO CMOS
Logical "I" Input Voltage (V INIIl )

54C, Vee ; 4.5V
74C, Vee ; 4,75V

Logical "0" I nput Voltage {V IN loll

54C, Vee ; 4.5V
74C, Vee; 4.75V

Logical "I" Output Voltage (Vo.UTlll)

54C, Vee = 4.5V, 10 ; -10/JA
74C, Vee; 4.75V, 10 ; -10/JA

Logical "0" Output Voltage {VouTloil

54C, Vee = 4,5V, 10 = +1 011 A
74C, Vee; 4,75V, 10 ; +101lA

V
V

Vee -1.5
Vee -1.5
0.8
0,8

V
V
V
V

4.4
4.4
0.4
0.4

V
V

CMOS TO LOW POWER
Logical "I" Input Voltage (V INlll )

54C, Vee; 4.5V
74C, Vee; 4.75V

Logical "0" Input Voltage (VINIQ))

54C, Vee; 4.5V
74C, Vee; 4.75V

Logical "I" Output Voltage (VOUTlll)

54C, Vee; 4,5V, 10 = -360/JA
74C, Vee; 4,75V, 10. ; -360/JA

Logical "0" Output Voltage (Vo.UTIOI)

54C, Vee = 4,5V, 10 = 360llA
74C, Vee = 4,75, 10. ='360/JA

V
V

4.0
4.0
1.0
1,0

V
V
V
V

2.4
2.4
0.4
0.4

V
V

OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet)
Output Source Current (I So.UReE)

Vee = 5,OV, VINIOI ; OV
TA = 25°C, V o.UT ; OV

Output Source Current (ISo.UReE)

Vee = 10V, VINIOI
T A ; 25°C, V o.UT

Output Sink Current (ISINK)

OV

mA

-8.0

mA

= OV

Vee; 5,OV, V INIII = 5,OV
T A = 25°C, V o.UT

Output Sink Current (ISINK)

=

-1.75

1.75

mA

8.0

mA

= Vee

Vee; 10V, VINIII = 10V
T A = 25°C, V o.UT' = Vee

1·4

ac electrical characteristics
TA

=25°C, C L =50 pF, unless otherwise specified.
PARAMETER

CONDITIONS

MIN

UNITS

TYP

MAX

Vcc - 5.0V
Vcc .- .'OV

50
30

gO
60

Input Capacitance (C IN )

(Note 2)

6.0

pF

Power Dissipation Capacitance (Cpo)

(Note 3) Per Gate or Inverter

12

pF

Propagation Delay Time to Logical
"'" or "0" (t pd )

Vcc - 5.0V
Vce - 10V

60
35

Input Capacitance (C IN )

(Note 2)

7.0

pF

Power Dissipation Capacitance (Cpo)

(Note 3) Per Gate

18

pF

Propagation Delay Time to Logical
"I" or "0" (tpd)

Vcc - 5.0V
Vcc - 10V

70
40

Input Capacitance (C IN )

(Note 2)

Power Dissipation Capacitance (Cpo)

(Note 3) Per Gate

MM54COO/MM74COO, MM54C02/MM74C02, MM54C04/MM74C04
Propagation Delay Time to Logical
"'" or "0" (tpd)

ns
ns

MM54C10/MM74C10
ns
ns

100
70

MM54C20/MM74C20
ns
ns

115
80

g

pF

30

pF

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The
table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: CpO determines the no load ac power consumption of any CMOS device. For complete explanation see 54C174C
Family Characteristics application note - AN-90

typical performance characteristics
Power Dissipation vs Frequency
MM54COO/MM74COO,
MM54C02/MM74C02,
MM54C04/MM74C04

(

Guaranteed Noise Margin
Over Temperature vs VCC

Gate Transfer Characteristics
IS

10

2
5.0

Vee =15V-

~

r
4.05
3.05

Vee' 5.0V

1.45
0.45

III
1'1.1

5.0

-

4.S0V

IS

10
VIN (V)

->-

.

>=
~

i

40
20
0

........

-~

J
-~ -I
CL(~

--

-I

>=

~;L.!iOPF

.-. 2.5

ill
Q

40

g

3D

..J.......r

20

-1-"'-

l-

-

1
1

-50 -25 0 25 50 75 100 125
AMBIENT TEMPERATURE (OC)

z

0

>=
~

i

CL = 50 pF...... V

..... 1-'"

CL =15pF_ I-'" ~

10

~

102 I

11111111 r1J.ffiJ1(""

1-5

Tii"iit ~~c·.l!ti~,.
Vcc·SOY

Yl

10

iJ'IUjf'"

Yl

1111

1111

IDS
10·
10'
INPUT FREQUENCY (Hz)

10 7

Propagation Delay Time vs
Load Capacitance
MM54COO/MM74COO,
MM54C02/MM74C02,
MM54C04/MM74C04
150

~
>=
>-

g

.I[
TA"25°C _
-Vee = 3.0V fr~EE ACTESTCIRCUIT
-

:/

j,.;'

100

Vee'5i~t-

z:

.....LJ I ~

0

>=
~

i

50

....

20

J.
-SO -25 0 25 50 75 100 125
AMBIENT TEMPERATURE (OC)

'l1

Ct.-!iOPF,RI

10 3

I

0

-

103~'t""'FIIIIIII
Vcc·1OV

a:

!

t- ~EE ;~~~ST CIRCUIT

-

Vcc I~I~IOV

15V

10V

-

~

1.5

!

>-

_,

CL = 50 pF

z
0

1

I

0

50

t-- ~EE ;~'~~ST CI RC UIT

60

10'

Propagation Delay vs
Ambient Temperature
MM54COO/MM74COO,
MM54C02/MM74C02,
MM54C04/MM74C04

100

g

""

OTHER DEVICES IS GIVEN
BVP.-tCt.+C,oltVcc!'1

Vee

Propagation Delay vs
Ambient Temperature
MM54COO/MM74COO,
MM54C02/MM74C02,
MM54C04/MM74C04

BO

w
z

~~

E~O~E2:'gISSIPATION FOR

w

a:

GUARANTEED OUTPUT "0" LEVEL
VOUT (O)@ INPUTS =VIN (I)
(0) ___

10'
§"
.3

~

~
VIN

Ii\
11:
I

0

GUARANTEED DUTPU~ 13.5
VOUT (II @INPUTS=V IN (0)
12.5

- - - TA =125 C
--TA=-55C

Vee =10V

+

:J

>°

15V

.,...

0

20

Vee=I~~

...

~I

~5V
J 111

100
50
CL - LOAD CAPACITANCE (pF)

ISO

typical performance characteristics (con't)
Propagation Delay Time vs
Load Capacitance

Propagation Delay Time vs
Load Capacitance

MM54C 1O/MM7 4C 10

MM54C20/MM74C20
]

~

150

f-++-+--ill'~TA' 25°C

_
SEE AC TEST CIRCUIT;;

A /I

;:
>

g
5
i
J

..., Vee =J.OV

I DO

~

50

Cl

-

100

1-+-+-'H-+-1H-~H-+-1-+--+-I
- Vee' 5.0V -J.,.A-+-+-+-+-+-+--l
f-++~=-"9I'-+-+ yeT =~ ... ~'"

50

1-+-+-f.-::±.~F-.-r+-..-l-I""-Hi:;;,j..-I""'Iq...+-J
I-+'''I''....
~-+-+ ref =,I5,V

150

50
Cl

LOAD CAPACITANCE (pF)

-

switching time waveforms and ac test circuits

CMOS to CMOS

NOTE: DELAYS MEASURED WITH INPUT I" It S; 20 ns.

1-6

100

LOAD CAPACITANCE (pF)

150

MM54C08/MM74C08 quad 2-input AND gate
MM54C86/MM74C86 quad 2-input EXCLUSIVE-OR gate

general description

features

Employing complementary MOS (CMOS)transistors to achieve wide power supply operating range,
low power consumption and high noise margin
these gates provide basic functions used in the
implementation of digital integrated circuit systems.
The Nand P-channel enchancement mode transistors provide a symmetrical circuit with output
swing essentially equal to the supply voltage. No
dc power other than that caused by leakage
current is consumed during static condition. All
inputs are protected from damage due to static
discharge by diode clamps to Vee and GND.

• Wide supply voltage range

3.0V to l5V

• Guaranteed noise margin

1.OV

• High noise immunity

0.45 Vee typ

• Low power
TTL compatibility
•

fan out of 2
driving 74L

Low power consumption

10 nW /package typ

• The MM54C86/MM74C86 follows the MM54L86
/MM74L86 pinout

connection diagrams
MM54C86/MM74C86

MM54C08/MM74C08
Vee

U

18

IA

lB

lA

lY

- -1B

IY

GND
TOP VIEW

TDPVIEW

truth tables
MM54C08/MM74C08

INPUTS

MM54C86/MM74C86

INPUTS

OUTPUT

OUTPUTS

A

B

Y

A

B

'y

L
L
H
H

L
H
L
H

L
L
L
H

L
L

L
H

L
H

H = High Level

L= Low Level

'·7

H

L

H

H

H
L

absolute maximum ratings

(Note 1)

Voltage at 'Any Pin
Operating Temperature Range
MMS4C08, MMS4C86
MM74C08, MM74C86
Storage Temperature Range
Package Dissipation
Operating Vcc Range
Absolute Maximum. Vcc
Lead Temperature (Soldering, 10 seconds)

-D,3V to Vcc +0.3V
-SSoC to +12SoC
-40° C to +8So C
-6SoC to +lS0°C
SOOmW
3.0V to lSV
18V
300°C

,

dc electrica I characteristics
Min/max,limits apply across temperature range, unless otherwise noted.
PARAMETER

CONDITIONS

. MIN

TYP

MAX

UNITS

CMOS TO CMOS
3.5
B.O

Logical "1" Input Voltage (VIN(ld

Vee = 5.0V
Vee = 10V

Logical "0" Input Voltage (VIN(O)

Vee = 5.0V
Vee = 10V

Logical '".' Output Voltage
(V OUT (1)

Vee = 5.0V,10 =-10pA
Vee = 10V,I 0 =-10pA

"a" Output Voltage

Vee = 5.0V, 10 = +1 OpA
Vee = 10V, 10 = +10pA

Logical

(VOUT(O)

V
V
1.5
2.0

Logical "1" Input Current (1IN(ll)

Vee = 15V, VIN = 15V

Logieal"O"lnput Current (IIN(O)

Vee =15V, VIN

Supply Current (Ieel.

Vee = 15V

4.5
9.0

'V
V
0.5
1.0
0.005

= OV

V
V

-1.0

1.0

-0.005
0.Q1

V
V
pA
pA

15

pA

".

CMOS/LPTTlINTERFACE
Logical "1" Input Voltage (VIN(l)

Logical

"a"

Input Voltage (VIN(QI)

54C, Vee = 4.5V
74C, Vce = 4.75V

Vee -1.5
Vee - 1.5

V
V

54C, Vec = 4.5V
74C, Vee = 4.75V

O.B
O.B·

Logical "1" Output Voltage
(V OUT (lI)

54C, Vee = 4.5V, 10 = -360pA
74C, Vcc = 4.75V, 10 = -360pA

Logical "a" Output Voltage
(VOUT(O)

54C, Vee
74C. Vee

2.4
2.4

V
V
V
V

= 4.5V, 10 = +360pA
= 4. 75V, 10 = +360pA

0.4
0.4

V
V

OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet)
Vee = 5.0V, V OUT
TA = 25°C

= OV

-1.75

Output Source Current (ISOURCE)'
(P·Channel)

Vee = 10V, VOUT
TA = 25°C

= OV

-B.O

Output Sink Current (I SINK )
(N·Channel)

Vee = 5.0V, V OUT
TA = 25°C

Output Sink Current (lSINK)
(N·Channel)

Vee = 10V, VOUT
TA = 25°C

Output Source Current (lsouReE>
. (P·Channel)

= Vec
= Vcc

1·8

-'

-3.3

rnA

-15

rnA

1.75

3.6

rnA

B.O

16

rnA

ac electrical characteristics
(MM54C08/MM74C08) T A

= 25°C, C L = 50 pF, unless otherwise specified.'
CONDITIONS

PARAMETER

MIN

TVP

MAX

UNITS

Propagation Delay Time to Logical
"I" or "0" (t pd )

Vcc ·5,OV
Vec ·l0V

80
40

Input Capacitance (C IN )

Note 2

5.0

pF

Power Dissipation Capacitance (C pd )

Note 3 Per Gate

14

pF

140

ns
ns

70

ac electrical characteristics
(MM54C86/MM74C,86) T A

= 25°C, CL = 50 pF, unless otherwise
CONDITIONS

PARAMETER

MIN

Vcc ·5,OV
Vee· 'OV

Propagation Delay Time to Logical
"'" or "0"

specified

(I pd )

TVP

MAX

110
50

'85
90

UNITS
ns
ns

Input Capacitance (C IN )

Note 2

5.0

pF

Power Dissi pation Capacitance (C pd )

Note 3 Per Gate

20

pF

Note 1: ., Absolute Maximum' Ratings" are those values beyond which the safety of the device cannot be guaranteed.
Except for "Operating Range" they are not meant to imply that the devices should be operated at these limits. The table
of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: CpO determines the no load ac power consumption of any CMOS device. For complete'explanation see 54C/74C
Family Characteristics application note, AN-gO.

.

typical performance cha racteristics
Propagation Delay Time vs
Load Capacitance
MM54COB/MM74COB

-

150)

:;

0::

z

i

i-'"
r-1--

~

0::

~

i

Vee = 15V

e-e-

I L
50
100
CL -LOAD CAPACITANCE (pF)

~

-

Vee = 10V

50

1--'1"""

..IVee = 15V

f-'-

I

J.
150

-

0

150

100

50

LOAD CAPACITANCE

ac test circuit

(pF)

switching time waveforms

""~'OO'
_.

......

e-f-e-

0

;;

...j....oT-

0

0

100

z

~ ....

.Y1

Vee = 5.0V -

o::

>

g

'" Vee = 5,QV

Vee=l~r--

50

I

./

.vr

:;

.Yf

......

TA = 25 C

-

SEE AC TEST CIRCU',!..7~
y-

100

0

~

150

~TA=25C
Vc;'· J.OV

>

g

Propagation Delay Time vs
Load Capacitance
MM54CB6/MM74C86

T

Vee

-

r-~
,ga%
50%

VIN

---t

[--tpd'

Vee
OUT

NOTE: DelAYS MEASURED WITH INPUT t,. tf = 20 ns

V

1·9

-If

'J--5a%

la%

la%
OV-----'

CL =50 PF

---j

:--'50%
OV

tpdO

50%

MM54C14/MM74C14 hex schmitt trigger

general description

features

The MM54C14/MM74C14 Hex Schmitt Trigger is a
monolithic complementary MOS (CMOS) integrated
circuit constructed with Nand P-channel enhancement
transistors. The positive and negative going threshold
voltages. V T + and V T -. show low variation with respect
to temperature (typ 0.0005V C at Vee = 10Vl. and
hysteresis. V T + - VT 0.2 Vee is gU,aranteed.

•

Wide supply voltage range

•

High noise immunity

•

Low power
TTL compatibility

All inputs are protected from damage due to static
discharge by diode clamps to Vee and GND.

•

Hysteresis

2:

t

Vee

GNo

1·10

0.70 Vee typ
fan out of 2
driving 74L
0.4 Vee typ
0.2 Vee guaranteed

I

connection diagram

TOP VIEW

3.0V to 15V

absolute maximum ratings
Voltage at Any Pin
Operating Temperature Range
MM54C14
MM74C14
Storage Temperature Range

Package Dissipation
Operati ng Vee Range
Absolute Maximum Vee
Lead Temperature (Soldering, 10 seconds)

-o.3V to Vee + 0.3V
-55°C to +125°C
-40°C to +85°C
-u5°C to +150°C

dc electrical characteristics

500mW
3.0V to 15V
18V
300°C

Min/max limits apply across temperature range, unless otherwise noted.

CONDITIONS

PARAMETER

MIN

TYP

MAX

UNITS

CMOS TO CMOS
VT+ Positive Going Threshold
Voltage
VT - Negative Going Threshold
Voltage
Hysteresis (VT+ - V T -)

Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee

3.0
6.0
9.0
0.7
1.4
2.1
1.0
2.0
3.0

= 5V
= 10V
= 15V
= 5V
= 10V
= 15V
= 5V
= 10V
= 15V

Logical "1" Output Voltage
(V OUT (1»)

Vee = 5V, 10 = -10pA
Vee = 10V, 10 = -10pA

Logical "0" Output Voltage
(VOUT(O»)

Vee = 5V, 10 = +10pA
Vee = 10V, 10 = +10pA

Logical "1" Input Current
(lIN (1))

Vee = 15V, V IN = 15V

Logical "0" Input Current
(lIN(O»)

\(ee = 15V, V IN = OV

Supply Current (Icc)

Vee
Vee
Vee
Vee

3.6
6.8
10.0
1.4
3.2
5.0
2.2
3.6
5.0

4.3
8.6
12.9
2.0
4.0
6.0
3.6
7.2
10.8

0.005

V
V
V

0.5
1.0

V
V

1.0

pA
pA

-0.005
0.05
20
200
600

= 15V, V IN = OV/15V
= 5V, V IN = 2.5V (Note 4)
= 10V, V IN = 5V (Note 4)
= 15V, V IN =7.5V (Note4)

V
V

V
V

4.5
9.0

-1.0

V
V

15

pA
pA
pA
pA

CMOS/LPTTL INTERFACE
Logical "1" Input Voltage
(V IN (1»)

Vee = 5V

Logical "0" Input Voltage
(VIN(O»)

Vee = 5V

Logical "1" Output Voltage
(V OUT (1»)

54C, Vee = 4.5V, 10 = -360pA
74C, Vee = 4.75V, 10 = -360pA

Logical "0" Output Voltage

54C, Vee = 4.5V, 10 =·360pA
74C, Vee = 4.75V, 10 = 360pA

(VOUT(O»)

V

4.3
0.7

V
V
V

2.4
2.4
0.4
0.4

V
V

OUTPUT DRIVE (See 54C174C Family Characte'ristics Data Sheet)

\

Output Source Current
(lsouReE) (P·Channel)

Vee = 5V, V OUT = OV, T A = 25°C

-1.75

-3.3

rnA

Output Source Current
(lsouReE) .(P·Channel)

Vee = 10V, V OUT = OV, T A = 25°C

-8.0

-15

rnA

Output Sink Current (lSINK)
(N·Channel)

Vee = 5V, V OUT = Vee,
T A =25°C

1.75

3.6

rnA

Output Sink Current (lSINK)
(N·Channel)

Vee = 10V, V OUT = Vee,
T A =25°C

8.0

16

rnA

1·11

~

U

ac electrical characteristics

rt

:E
:E
.........

MIN

CONDITIONS

PARAMETER

TYP

MAX

220
80

400
200

UNITS
ns
ns

~

Propagation Delay from Input·
to Output (tpdO or tpd 1 )

Vee = 5V
Vee = 10

'lit

Input Capacitance

Any Input (Note 2)

5.0

pF

Power Dissipation Capacitance
(C PD )

(Note 3) Per Gate

20

pF

U
Ln

:E
~

Note1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: CPO determines the no load ac power consumption of any CMOS device. For complete explanation see 54C174C Family Characteristics
application note, AN-90.
Note 4: Only one of the six inputs is at 1/2 VCC, the others are either at VCC or GND.

typical application
Low Power Oscillator
Vee - - - - - - - - - - - -

V1N

YS

I

I

11~AC\n~

vec~

VT •

~t2~

12 ~ RC ~n yee - VT _
Vee - VT.

,

~

~tl~

o

1

----,,,.----,
AC 1n VT• (Vee - VT.l
VT_ (Vee - VT.)

.. _,_
1.7 RC

Note: The equations assume t, + t2

»tpdO

VOUT

vs

t

+ tpd1

typical performance characteristics
Typical Transfer Characteristics

~

~

>

VT•

15

20

..

Vee

Guaranteed Trip Point Range
INPUT
VOLTAGE

Vr _

15

.

10

i

5
4.3
3.0
2.0
0.7
0

~

DV

c:(

10

~
>

>-

:::>
">:::>
c:>

10

15

INPUT VOLTAGE (V)

20

Vee

OUTPUT
VOLTAGE

10

15
DV

Vee (V)

Note: For more information on output drive characteristics, power dissipation, and propagation delays, seeAN·90.

1-12

MM54C30/MM74C30 a-input NAND gate
general description

features

The logic gate employs complementary MOS
(CMOS) to achieve wide power supply operating
range, low power consumption and h.i9h noise
immunity. Function and pin out compatibility
with series 54/74 devices minimizes design time
for those designers familiar with the standard
54/74 logic family.

• Wide supply voltage range
• Guaranteed noise margin
•

High noise immunity

All inputs are protected from damage due to
static discharge by diode clamps to Vee and GND.

•

Low power
TTL compatibility

logic and connection diagrams
11
12---,._"

OUTPUT

vee

1,4 . ' 113

12

11

110

19

1

2

3

4

5

6

ls

L

»
P

GND
TOP VIEW

1·13

3.0V to 15V
1.0V
0.45 Vee typ
fan out of 2
driving 74L

absolute maximum ratings

(Note 1)

Voltage at Any Pin
Operating Temperature Range
MM54C30
MM74C30
Storage Temperature Range
Package Dissipation
Operating Vee Range
Absolute Maximum Vee
Lead Temperature (Soldering, 10 seconds)

-o.3V to Vee + 0.3V
-55°C to +125°C
-40° C to +85° C
-65°C to +150°C
500mW
3.0V to 15V
18V
300°C

'.

dc electrical characteristics
Min/max limits apply across temperature range, unless otherwise noted.
PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

CMOS TO CMOS
3.5
8.0

Logical "1" Input Voltage (V IN (ld

Vee = 5.0V
Vee = 10V

Logical "0" Input Voltage (VIN(O))

Vee = 5.0V
Vee = 10V

Logical "1" Output Voltage (V OUT (l))

Vee = 5.0V, 10 = -1 Oil A
Vee = 10V, 10 = -1 Oil A

Logical "0" Output Voltage (VOUT(O))

Vee = 5.0V, 10 = +1 Oil A
Vee = 10V, 10 = +lOIlA

V
V
1.5
2.0

Logical "1" Input Current (lIN(1))

Vee = 15V, V IN =15V

Logical "0" Input Current (11N(Od

Vee = 15V, V IN = OV

Supply Current (Ieel

Vee = 15V

V
V

4.5
9.0

0.005
-1.0

V
V

0.5
1.0

V
V

1.0

IlA

-0.005
0.01

IlA
15

IlA

CMOS/LPTTL INTERFACE
Logical "1" Input Voltage (V IN (ld

54C, Vee = 4.5V
74C, Vee = 4.75V

Logical "0" Input Voltage (V IN (0))

54C, Vee = 4.5V
74C, Vee=4.75V

Logical "1" Output Voltage (V OUT (l))

54C, Vee = 4.5V, 10 = -3601lA
74C, Vee = 4.75V, 10 = -3601lA

Logical "0" Output Voltage (VOUT(O))

54C, Vee = 4.5V, 10 = 360llA
74C, Vee = 4.75V, 10 = 360pA

V ee -l.5
V ee -l.5

V
V
0.8
0.8

V
V
V
V

2.4
2.4
0.4
0.4

V
V

OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet)
Output Source Current ([SOURCE)
(P·Channel)

Vee = 5.0V, V OUT = OV,
T A = 25°C

-1.75

-3.3

mA

Output Source Current (ISOUReE)
(P·Channel)

Vee = 10V, V OUT = OV,
T A =25°C

-8.0

-15

rnA

Output Sink Current (lSINK)
(N·Channel)

Vee ='5.0V, V OUT = Vee,
T A =25°C

1.75

3.6

rnA

Output Sink Current (I SINK )'
(N',Channel)

Vee = 10V, V OUT = Vee,
TA = 25°C

8.0

,16

rnA

1-14

ac electrical characteristics
PARAMETER

= 25°C, C L = 50 pF, unless otherwise specified.

TA

CONDITIONS

MIN

= 5.0V
= 10V

TVP

IYIAX

125
55

180

UNITS
ns
ns

Propagation Delay Time to Logical" 1"
or "0" (tpd)

Vee
Vee

Input Capacitance (C IN )

(Note 2)

4.0

pF

Power Dissipation Capacitance (C pd )

(Note 3) Per Gate

26

pF

gO

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The
table of "Electri.cal Characteristics" provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: CpO determines the no load ac power consumption of any CMOS device. For complete explanation see 54C174C
Family Characteristics application note, AN·90.

typical performance characteristics
Propagation Delay Time vs
Load Capacitance

I

I

J

I I

J.
50
Cl

-

switching time waveforms

OV _ _ _-'...;.,I"J

Ipdo---l (

-- F-pdl

VOUT

OV _ _ _ _ _5_O_%_\_ _ _ _- . J

150

ac test circuit

V, ..

Vee

100

LOAD CAPACITANCE (pF)

'50%

NOTE: DELAYS MEASURED WITH INPUT I" If • 20 ns.

1·15

MM54C32/MM74C32 quad 2-input OR gate

general description

features

Employing complementary)MOS (CMOS) transistors to
achieve low power and high noise margin, these gates
provide the basic functions used in the implementation
of digital integrated circuit systems. The Nand P-channel
enhancement mode transistors provide a symmetrical
circuit with output swings essentially equal to the supply
voltage. This results in high noise immunity over a wide
supply voltage range. No dc power other than that
caused by leakage current is consumed during static
conditions. All inputs are protected against static discharge damage.

•

Wide supply voltage range

•

Guaranteed noise margin

•

High noise immunity

•

Low power TTL
compatibility

vee

GND

1·16

1.0V
0.45 Vee typ
fan out of 2
driving 74L

connection diagram

TOPVIEW

3.0V to 15V

absolute maximum ratings
Voltage at Any Pin
Operating Temperature Range
MM54C32
MM74C32
Storage Temperature Range

(Note 1)

-o.3V to Vee +O.3V

Package Dissipation
Operating V cc Range
Absolute Maximum Vee
Lead Temperature (Soldering, 10 seconds)

-55°C to +125°C
-40°C to +85°C
-65°C to +150°C

de elect rica I c ha racteristics

500mW
3.0V to 15V
18V
300°C

Minimax limits apply across temperature range, unless otherwise noted.
CONDITIONS

PARAMETER

MIN

TYP

MAX

UNITS

CMOS TO CMOS
Logical "I" Input Voltage (V IN (l))

Vee = 5.0V
Vee = 10V

Logical "0" Input Voltage (VIN(O))

Vee = 5.0V
Vee = 10V

= 5.0V.
= 10V.
= 5.0V.

3.5
8.0

V
V

, .5
2.0

=-lOtJA
= -10tJA
= lOtJA

Logical "I" Output Voltage (V OUT (1))

Vee
Vee

Logical "0" Output Voltage (VouT(od

Vee
10
Vee = 10V. 10 = 10tJA

10
10

4.5
9.0

V
V

0.5

'.0

= 15V. V IN = 15V

V
V

0.005

'.0

V
V

Logical "1" Input Current (lIN(l))

Vee

Logical "0" Input Current (lIN(od

Vee = 15V. V IN = OV

Supply Current (Icc!

Vee

= 15V

Logical "'" Input Voltage (V IN (1))
MM54C32
MM74C32

Vee
Vee

= 4.5V

V

= 4.75V

V

Logical "0" Input Voltage (VIN(O))
MM54C32
MM74C32

Vec = 4.5V
Vee = 4.75V

Logical"," Output Voltage (V OUT (l))
MM54C32
MM74C32

Vee = 4.5V. 10
Vee = 4.75V. 10

Logical "0" Output Voltage (VOUT(O))
MM54C32
MM74C32

Vee
Vee

-1.0

-0.005
0.05

tJA
tJA

.'5

tJA

eMOS/LPTTL INTERFACE

= 4.5V.
= 4.75V.

0.8
0.8

=-360tJA
= -360tJA

2.4
2.4

V
V

V
V

10 = 360tJA
10 = 360tJA

0.4
0.4

V

V

OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet)
Output Source Current (lSOURCE)
(P·Channel)

Vee = 5.0V. V OUT
TA = 25°C

Output Source Current (lsouReE)
(P·Channel)

Vee = 'OV. V OUT = OV
TA = 25°C

Output Sink Current (I SIN K)
(N·Channel)

Vee = 5.0V. V OUT
T A = 25°C

Output Sink Current (I SIN K
(N·Channel)

Vee = 'OV. V OUT = Vee
TA = 25°C

)

ac electrical characteristics

TA

= OV

= Vee

-1.75

-3.3

rnA

-8.0

-15

rnA

1.75

3.6

rnA

8.0

16

rnA

= 25°C, C L = 50 pF, unless otherwise specified.
CONDITIONS

TYP

MAX

UNITS

Vee = 5V
Vee = 'OV

80
35

150
70

ns
ns

Input Capacitance (C IN )

Any Input (Note 2)

5

pF

Power Dissipation Capacitance (C pd )

Per Gate (Note 3)

15

pF

PARAMETER
Prooagation Delay Time to Logical "I"
(t pd l) or "0" (tpdo)

MIN

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: CPD determines the no load ac power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics
application note, AN-90.

1-17

MM54C42/MM74C42 BCD tO'decimal decoder
general description
.• Low power
• Medium speed operation

The MM54C42/MM74C42 one-of-ten decoder is a
monolithic
complementary
MOS
(CMOS)
integrated circuit constructed with N- and
P-channel enhancement transistors. This decoder
produces a logical "0" at the output corresponding
to a four bit binary input from zero to nine, and a
logical "'" at the other outputs. For binary inputs
from ten to fifteen all outputs are logical"'''.

with 10V Vee

applications

features

•
•
•
•

Automotive
Data terminals
Instrumentation
Medical electronics

•
•

Supply voltage range
Tenth power TTL
compatible

3V to 15V
drive 2 LPTTL loads

•
•
•

Alarm systems
Industrial electronics
Remote metering

•

High noise immunity

0.45 Vee (typ.)

•

Computers

schematic diagram

connection diagram

L"

14

1

"

truth table

11

INPUTS

,

10

DeB A

o
o
o
o
o

0
0
0
0
1
0 1
0 1
0 1
1 o
1 o
1 o
1 o
1 1
1 1
1 1
I 1

~

n
1

1l

l

50 nW (typ.)
10 MHz (typ.)

. , . 'I'
1-'8

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

OUTPUTS

o
o

I 23456789

1
1 0
11
1 1
1 1
1 1
11
11
11
11
11
11
11
11
11
11

11
11
o1
1 0
1 1
11
11
11
11
11
11
11
11
1 1
11
11

1 11 1 11
111 1 11
111 1 11
1 1 1 1 1 1
o 1 1 1 11
1 0 1 1 11
1 1 0 1 11
11 1 0 1 1
111 1 0 1
1111 1 0
1 11 1 11
1 11 111
111 111
111 11 1
1 1 1 11 1
1 1 1 11 1

absolute maximum ratings
Voltage at Any Pin (Note 1)
Operating Temperature MM54C42
MM74C42
Maximum Vee Voltage

Storage Temperature
Package Dissipation
Operating Vee Range
LeadTemperature (Soldering, 10 sec)

-0.3V to Vee +0.3V
_55°C to +125°C
-40°C to +B5°C
lBV

-65°C to +150°C
500mW
3Vto15V
300°C

electrical cha racteristics MiniMax limits apply across temperature range unless otherwise specified
PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

CMOS TO CMOS
Logical "1" Input Voltage

VIN(1)

Logical "0" I nput Voltage

VINIO)

Logical "1" Output Voltage VOUTI1)
Logical "0" Output Voltage VOUTIOI
Logical "1" Input Current

IINI11

Logical "0" Input Current

IINIO)

Supply Current

ICC

= 5.0V
= 10.0V
Vee = 5.0V
Vee = 10.0V
Vee = 5.0V, 10 = -10 pA
Vee = 10.0V, 10 = -10pA
Vee = 5.0V,lo = +10pA
Vee = 1O.0V, 10 = +10pA
Vee = 15.0V, VIN = 15V
Vee = 15.0V, VIN = OV
Vee = 15.0V

Vee
Vee

Input Capacitance

Any Input

Propogation Delay Time to a
Logical "0" or Logical "1"

Vee = 5.0V, CL = 50 pF, T A = 25°C
Vee = 10.0V, CL = 50 pF, TA = 25°C

3.5
B

V
V
1.5
2

4.5
9.0

V
V
V
V

0.5
1
1
-1

V
V
pA
pA

0.05

300

5
200
90

pA
pF

300
140

ns
ns

CMOS TO TENTH POWER
INTERFACE

= 4.5V
= 4.75V
Vee = 4.5V
Vee = 4.75V
Vee = 4.5V, 10 = -360pA
Vee = 4.75V, 10 = -360pA
Vee = 4.5V, 10 = 360pA
Vee = 4.75V, 10 = 360pA

Logical "1" Input Voltage

V INI11

54C, Vee
74C, Vee

Logical "0" Input Voltage

VINIOI

54C,
74C,

Logical "1" Output Voltage 'VO UTllI

54C,
74C,

Logical "0" Output Voltage

54C,
74C,

VOUTIOI

V

Vee - 1.5
O.B
2.4

V
V

0.4

V

OUTPUT DRIVE (See 54CI14C Family Characteristics Data Sheet)

-

Output Source Current (lSOURCE)

Vee = 5.0V, VIN(O) = OV
TA = 25°C, V OUT = OV

-1.75

mA

Output Source Current (lSOURCE)

Vee = 10V, VIN(O) = OV
T A = 25°C, V OUT = OV

-B.O

mA

Output Sink Current (I SINK )

Vee = 5.0V, V IN (1) = 5.0V
TA = 25°C, V OUT = Vee

1.75

mA

Output Sink Current (lslNd

Vee = 10V, V IN (1) = 10V
TA = 25°C, V OUT = Vee

B.O

mA

Note 1: This device should not be connected to circuits with the power on because high transient voltages may cause
permanent damage.

1·19

MM54C48/MM74C48 BCO-to-7 ~egment decoder
general description

features

The MM54C48/MM74C48 BCD-to-7 segment decoder
is a monolithic complementary MOS (CMOS) integrated
circuit constructed with N- and P-channel enhancement
transistors. Seven NAN D gates and one driver are connected in pairs to make binary-coded decimal (BCD)
data and its complement available to the seven decoding
AND-OR-INVERT gates. The remaining NAND gate and
three input buffers provide test blanking input/rippleblanking output, and ripple-blanking inputs.

•
•
•

Wide supply voltage range
Guaranteed noise margin
High noise immunity

•

Low power
TTL compatibility

•
•

High current sourcing output (up to 50 mA)
Ripple blanking for leading or trailing zeros (optional)

•

Lamp test provision

3.0V to 15V
1.0V
0.45 Vee typ
fan out of2
driving 74L

connection diagram

OUTPUTS
Vee

L6

"

15

14

13

10

11

12

-

-

1

9

2

----......-..INPUTS

3
LAMP
TEST

4

8

7

6

5

R8
R8
OUTPUTI INPUT
BLANKING
INPUT

o

1

GND

A

~

INPUTS

TOP VIEW

10

11

12

13

Numerical Designations
and Resultant Displays

Segment Identification

1-20

14

15

absolute maximum ratings

~
~

(Note 11

Voltage at Any Pin

CJ1

-o.3V to Vee + 0.3V

~

Operating Temperature Range

0

MM54C48

-55°C to +125°C

MM74C48

-40° C to +85° C

~

CO

.........

~
~

-65°C to +150°C

Storage Temperature Range
Package Dissipation

500mW

~

3.0V to 15V

Operating Vee Range
Absolute Maximum Vee

18V
300°C

Lead Temperature (Soldering, 10 seconds I

0

~

CO

dc electrical cha racteristics
I

Min/max limits apply across temperature range, unless otherwise noted.
PARAMETER

CONDITIONS

MIN

TVP

MAX

UNITS

CMOS TO CMOS
Logical "1" Input Voltage (V IN (1))

Vee
Vee

= 5.0V
= 10V

Logical "0" Input Voltage (VIN(O))

Vee
Vee

= 5.0V
= 10V

Logical "1" Output Voltage (VOUT(l))
(RB Output Only)

Vee
Vee

= 5.0V,10 = -10J.lA
= 10V, 10 = -10J.lA

Logical "0" Output Voltage (VOUT(O))

Vee
Vee

= 5.0V,
= 10V,

10
10

Logical "1" Input Current (1IN(l))

Vee

= 15V,

V IN

= 15V

Logical "0" Input Current (IIN(O))

Vee

= 15V,

V IN

= OV

Supply Current (Ieel

Vee

= 15V

3.5
8.0

V
V
1.5
2.0

4.5
g.O

V
V

= +10J.lA
= +10J.lA
0.005
-1.0

V
V

0.5
1.0

V
V

1.0

J.lA

-0.005
0.05

J.lA
300

J.lA

CMOS/LPTTL INTERFACE
Logical ':1" Input Voltage (V IN (1))

54C, Vee
74C, Vee

= 4.5V
= 4.75V

Logical "0" Input Voltage (VIN(O))

54C, Vee
74C, Vee

= 4.5V
= 4.75V

Logical "1" Output Voltage (V OUT (1))
(RB Output Only)

54C, Vee
74C, Vee

= 4.5V,
= 4.75V,

10
10

= -50J.lA
= -501lA

Logical "0" Output Voltage (VOUT(O))

54C, Vee
74C, Vee

= 4.5V,
= 4.75V,

10
10

= 360llA
= 360J.lA

V ee -1.5
V ee -1.5

V
V
0.8
0.8

2.4
2.4

V
V
V
V

0.4
0.4

V
V

OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet)
V OUT
V OUT

= O.4V

-0.80

= O.5V

-4,0

Vee = 5.0V,
TA = 25°C

V OUT

= Vee

1.75

3.6

mA

Output Sink Current (I SIN K)
(N·Channel)

Vee = 10V,
TA = 25°C

V OUT

= Vee

8.0

16

mA

Output Source Current
(NPN Bipolar)

Vee
Vee
Vee
Vee

= 5.0V,
= 5.0V,
= lOV,
= 10V,

V OUT
V OUT
V OUT
V OUT

= 3.4
= 3.0
= 8.4
= 8.0

-20

-50
-65
-50
-65

mA
mA
mA
mA

Output Source Current (lsou ReE)
(P-Channel) (RB Output Only)

Vee
Vee

Output Sink Current (lsINKl
(N·Chimnel)

= 4.75V,
= 10V,

-20

mA
mA

Note 1~ "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: CpO determines the no load ac power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics
application note, AN·90.

1-21

ac electrical characteristics
PARAMETER

TA

= 25°C, C L = 50 pF, unless otherwise specified.
MIN

TVP

MAX

UNITS

Propagation Delay to a "1" or "0" on
Segment Outputs from Data Inputs

Vee = 5.0V
Vee = 10V

CONDITIONS

450
160

1500
500

ns
ns

Propagation Delay to a "0" on
Segment Outputs from RB Input

Vee = 5.0V
Vee = 10V

500
180

1600 .
550

ns
ns

Propagation Delay to a "0" on
Segment Outputs from Blanking Input

Vee = 5.0V
Vee = 10V

350
140

1200
450

ns
ns

Propagation Delay to a "1" on
Segment Outputs from Lamp Test

Vee = 5.0V
Vee = 10V

450
160

1500
500

ns
ns

Propagation Delay to a "1" on R B
Output from RB Input

Vee = 5.0V
Vee = 10V

'600
250

2000
800

ns
ns

Propagation Delay to a "0" on RB
Output from RBlnput

Vee = 5.0V
Vee = 10V

140
50

450
150

ns
ns

typical applications
Typical Connection Utilizing the Ripple-Blanking Feature

Blanking Input Connection Diagram

Vee

I=h-.'BI·

r?~J.

-+-t>o---i ....

1 MM74C9D6

L---l

(When RBO/SI is forced low, all segment outputs Ire off
regardless of the state of any other input condition)

TO DISPLAY READOUTS
(Fintthr...ugnwillbllnkle.dingzera•• the'aurth
st.gewill nal bl.nk zerosl

Light Emitting Diode (LED) Readout
Vee

Vee

COMMON
ANODE LEO

COMMON
CATHODE LEO

1-22

typical applications (con't)
Incandescent Readout

Fluorescent Readout
Vee

Vee

DIRECT
(lOW BRIGHTNESS)

UA filament pr.,warm rfsistor is recommended to reduce filament
thermal shock Ind incrllse th •• ffectivlcold ruistlnceofth.
filament.

Gas Discharge Readout

Liquid Crystal (LCI Readout

Direct de drive of Le's not recommended for life of LC readouts.

truth table
DECIMAL
OR
FUNCTION

INPUTS
LT

RBI

D

C

L
L
l

H

H

1

H

2

H

X
X
X

0

3

H

4

H

L
l

L
H

H

H

H

L

H

H

l

l

L

L
l

l
H

H

H

H

L

H

H

L

H

H

H

H

H

H

l

L

H

H

H

H

L

l

H

H

L

L

H

L

l
H

H

L
H

L

H

H

l

H

H

L

H

H

l

H

L

L

H

H

H

H

H

H

H

H

H

H

H

L

L

L

l

H

H

8

H

X
X
X
X

H

L

X
X
X
X

13

H
H

15

H

I
1

\

L

L

H

H

H

H

H

H

H

l

l

H

H

H

H

H

L

L

H

H

H

L

H

L

H

L

L

H

H

L

H

H

L

H

H

H

L

l
L

H

H

L

L

H

H

H

L

L

H

L

H

L

L

L

H

H

H

L

L

H

H

H

H

H

L

L

L

L

L
H

L

3

H

4

H

H

L

H

H

H

H

H

L

H

L

L

L

H

L
H

H

H

H

H

H

L

L

L

L

L

X

81

X

X

X

H

L

L

L

L

L

L

L

L
L

L

R81

L

L

L
L

LT

L

X

X

X

X

X

H

H

H

H

H

H

X

H

H

L

14

H

g

l

X

H

H

I

H

H

H

H

d

L

7

12

H

b

l

H

11

NOTE

H

H

H

.

L

5

H

OUTPUTS

c

L
.L

6

9

.

A

X
X
X

10

BI/RBOf
B

X

L

L

L

H

2

H = high level, L = low level, X = (rrelevant
Note 1: The blanking input (BI) must be open when output functions 0-15 are desired. The ripple-blanking input (RBI) must be high, if blanking
o'f a decimal zero is not desired.

Note 2: When a low logic level is applied directly to the blanking input (BI), all segment outputs are low regardless of the level of any other input.
Note 3: When ripple-blanking input (RBI) and inputs A, B, C, and D are at a low level with the lamp-test input high, all segment outputs go low
and the ripple-blanking output (RBO) goes to a low level (response condition),
Note 4: When the blanking input!ripple-blanking output (BI/RBO) is open and a low is applied to the lamp-test input, all segment outputs are high.
tOne BI/RBO is wire-AND logic serving as blanking input (BI) andlor ripple-blanking output (RBOI.

1-23

MM54C73/MM74C73 dual J-K flip-flops with clear
MM54C76/MM74C76 dual J-K flip-flops
with clear and preset
MM54C107/MM74C107 dual J-K flip-flops with clear
general description
•
•
•

. These dual J-K flip - flops are' monolithic
complementary MOS (CMOS) integrated circu'its
constructed with N- and P-channel enhancement
transistors. Each flip-flop has independent J, K,
clock and clear inputs and Q and Q outputs. The
MM54C76/MM74C76 flip flops also include preset
inputs and are supplied in 16 pinpackages. These
flip flops are edge sensitive to the clock input and
change state on the negative going transition of the
clock pulses. Clear or preset is independent of the
clock and is accomplished by a low level on the
respective input.

applications
•
•
•
•
•
•
•
•

features .
3V to 15V .
drive 2 LPTTL loads

• Supply voltage range
• Tenth 'power TTL
compatible

0.45V cc (typ)
50 nW'(typ)
10 MHz (typ)
with 10V supply

High noise immunity
Low power
Medium speed operation

Automotive
Data terminals
Instrumentation
Medi.cal electronics
Alarm systems
I ndustrial electronics
Remote metering
Computers

logic and connection diagrams

Transmission Gate

iillttm
fi

CL

T

f

MM54C73/MM74C73 and MM54C107/MM74C107
v"

IN'UT,,,onCTIOH+TOINTEJIIllAL
FOR ALL IN'UTS

tl.

CIRCUITRY

Cl-

ClDCK~
MM54C76/MM74C76

1------.

J• ..!,'

CUAR ... Z

v"
CLOCK.'

u 0."

Q.

If 0 ...

o. '

'

!leND

18 Ie.

I

I

0,

110

I

110
10'\/'I(W

Nole: A logic "0" on cl.ar sets QIO logic "0."

MM54C73/MM74C73

NOle: A logic "a" on clear sets Q 10 logic "a."

MM54C107/MM74C107

1-24

Nole 1: A logic "0" on cl." .ets Q 10 • logic "a..
NOle2: A logic "0" on preselsets Qto a logic "1."

MM54C76/MM74C76

~
~

absolute maximum ratings
Voltage at any pin (Note 1)
Operating Temperature MM54CXX

-Q.3V to Vee +O.3V
-55°C to 125°C

MM74CXX

-40°C to +85°C

Storage Temperature

U"I
~

-65°C to 150°C

n
--..

18V

......

500mW
300°C

~
~

Maximum Vee Voltage
Package Dissipation
Lead Temperature (Soldering, 10 sec)

Co\)

--..

+3V to 15V

Operating Vee Range

~

n
--..

electrical characteristics
PARAMETERS

CONDITIONS

MIN

TYP

MAX

UNITS

Co\)

V
V

~
~

CMOS TO CMOS
Logical "1" Input Voltage VINlll
Logical

"a"

Input Voltage VINIOI

Vee = 5.0V
Vee = 10.0V

3.5
8

Vee = 5.0V
Vee = 10.0V

1.5
2.0
4.5
9.0

V
V

Logical "1" Output Voltage VOUTll)

Vee = 5.0V
Vee = 1O.0V

Logical "0" Output Voltage VOUTIO)

Vee = 5.0V
Vee = 10.0V

0.5
1.0

V
V

Logical "1" Input Current IINll)

Vee = 15:0V

1.0

p.A

60

p.A

V
V

Logical "0" Input Current IINIO)

Vee = 15.0V

Supply Current lee

Vee = 15.0V

-1.0
0.050

Input Capacitance

Any Input

5

Propagation Delay Time to a Logical "a"
tpdO or Logical "1" tpdl From Clock to
Q ora

Vee = 5.0V. CL = 50 pF. TA = 25"C
Vee = 10.0V. CL = 50 pF, TA = 25°C

180
70

300
110

ns
ns

Propagation Delay Time to a Logical "0"
From Preset or Clear

Vee = 5.0V. CL = 50 pF, TA = 25°e
Vee = 10.0V, CL = 50 pF, r A = 25°C

200
80

300
130

m
ns

Propagation Delay Time to a Logical "1"
From Preset or Clear

Vee = 5.0V, CL = 50 pF, TA = 25°C
Vee = 10.V, CL = 50 pF, TA =,25°C

200
80

300
130

ns
ns

Time Prior to Clock Pulse That Data Must
be Present, tSETUP

Vee = 5.0V, CL = SO pF, T A = 2SoC
Vee = 10V, CL = 50 pF, TA = 25°C

110
45

17S
70

ns

Time After Clock Pulse That J and K
Must be Held

Vee = 5.0V, CL = 50 pF, T A = 25°C
Vee = 10.0V, CL = SO pF, T A = 2SoC

-40
-20

0
0

m

Minimum Clock Pulse Width
,
tWL = tWH

Vee = S.OV, CL = 50 pF, TA = 25°C
Vee = 10.0V, CL = 50 pF, TA = 25°C

120
50

190
80

ns
ns

Minimum Preset and Clear Pulse Width

Vee = 5.0V, CL ~ 50 pF, T A = 25°e
Vee = 10.0V, CL = 50 pF, T A = 25°C

90
40

130
60

ns
ns

Maximum Toggle Frequency

Vee = 5.0V, CL = 50 pF, T A =2SoC
Vee = 10.0V, CL = SO pF, T A = 25°C

Clock Pulse Rise and Fall Time

Vee = 5.0V, CL = 50 pF, TA = 25°C
Vee = 10.0V, CL = SO pF, T A = 25°C

2.S
7.0

p.A

pF

ns

ns

MHz
MHz

4.0
11.0
15
5

p.s
p.s

LOW POWER TTL TO CMOS INTERFACE
Logical "1" Input Voltage V INI1 )
Logical "0" Input Votlage V INIO)

54C, Vee = 4.SV
74C, Vee = 4.75V

V

V ee -lo5

54C, Vee = 4.5V

0.8

V

74C, Vee = 4.75V

Logic,L "1" Output Voltage VOUTll)

54C, Vee = 4.5V, 10 = -360p.A
74C, Vee = 4.75V, 10 = -360p.A

Logical "0" Output Voltage VOUTIO)

54C, Vee = 4.SV, 10 = 360p.A
74C, Vee = 4.75V, 10 = 360p.A

2.4

V
0.4

V

OUTPUT DRIVE (See 54Cn4C Family Characteristics Data Sheet)
Output Source Current (I~ouReE)

Vee = 5.0V, V INIO) = OV
.TA;: 25°C, V OUT = OV

-1.75

mA

Output Source Current (lsouReE)

Vee = 10V, V INIO ) =.OV
T A = 25°C, V OUT ~ OV

-B.O

mA

Output Sink Current (lSINK)

Vee = 5.0V, V IN(1 ) = 5.0V
TA = 25°C, V OUT = Vee

1.75

mA

Output Si~k Current (lSINK)

Vee = 10V, V INllI .= 10V
TA = 25°C, V OUT = Vee

8.0

mA

Note 1: This device should not be connected to circuits with the power on because high transient voltages may cause
permanent damage.
1·25

U"I
~

n
--..

0)

......
~
~

--..
~

n

--..
0)

~
~

U"I
~

....0n

"3:

......

3:

"n....
~

0

"

truth table

ac test circuit
Vee Vee

tn

tn

J

K

0
0
1

0
1
0

1

1

an . an

tn+l

Preset

Clear

a
an

0

0

0

0

0

1

1

0

0

1

0

0

1

1

1

1

'an

'an

On

= bit ti me before clock

'No change in' output from
previous state.

pulse.

tn+l = bit time after clock pulse.

typical applications
Ripple Binary Counters
C~~~~~~

74C Compatibility

+ ______---,

_ _ _ _ _ _- ._ _ _ _ _ _ _

Vee

CLOCK

-------_-------------1
Guaranteed Noise Margin as a
Function of VCC

Shift Registers

15V . . . - - - - - - - - - - - ,

13.5
12.5

C L O C K - - - - - - . - - - - - - +_ _ _ _ _----I

4.05
3.05

4.50V

10V
Vee

switching time waveforms
CMOS to CMOS

CLOCK

. Ov-----~~~----JorK

Jor K
OV

Vee

Qodi

ov
Vee

aora.
ov
t,:t.t f :E2Dns

1·26

15V

MM54C74/MM74C74 dual D flip-flop
general description
The 'MM54C74/MM74C74 dual D flip flop is a
monolithic
complementary
MOS
(CMOS)
integrated circuit constructed with N- and
P-channel enhancement transistors. Each flip flop
has independent data, preset, clear and clock
inputs and Q and Q outputs. The logic level
present at the data input is transferred to the'
output during the positive going transition of the
clock pulse. Preset or clear is independent of. the
clock and accomplished by a low level at the
preset or clear input.

•
•
•

Supply voltage range
Tenth power TTL compatible

0.45 Vee (typ)
50 nW (typ)
10 MHz (typ)
with 10V supply

,applications
•
•
•
•
•
•
•
•

features
•
•

High noise immunity
Low power
Medium speed operation

3V to 15V
drive 2LPT2 L
loads

Automotive
Data terminals
Instrumentation
Medical electronics
Alarm system
Industrial electronics
RemQte metering
Computers

logic and connection diagrams

DATA

n

mm

CL

ClOCK~

\

cr

CL

T

-I I--~ALLP'CHANNElSUISTRATES

v"

CQNNECTEOTOV cc

INPUTPROTECTION+'TDINTERNALCIRCUIT

-I

I::;
t-

FOR All INPUTS

ALLNCHANNElSUISTRATES

CO.NECTEDTO •• D

truth table

Preset

Clear

an

0

0

0

an
0

0

1

1

0

1

0

0

1

1

1

"an

"On

"No change in output from
previous state,
TOPVIEW

Nota: Alogic"O" on clear sets Oto logic "0,"
Alogic"O" onpre.et.etsOtologic"I,"

1-27

absolute maximum ratings
Voltage at any pin (Note 1)
Operating temperature MM54C74

-0.3V to Vee + 0.3V
_55°C to 125°C

MM74C74

-40° C to +85 C

0

Storage temperature

-65°C to 150°C

Maximum Vee Vo"itage

18V
500mW
300°C

Package dissipation
Lead temperdture (Soldering, 10 sec)
Operating Vee range

+3V to +15V

electrical characteristics
Min/Max limits apply across temperature range unless otherwise specified.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

CMOS TO CMOS
Logical "1" Input Voltage V 'N(1 )

Vee = 5.0V
Vee = 10.0V

Logical "0" Input Voltage V,NCO)

Vee = 5.0V
Vee = 10.0V

Logical "1" Output Voltage V OUTlll

Vee = 5.0V
Vee= 10.0V

Logical "0" Output Voltage VOUTCO)

Vee = 5.0V
Vee = 10.OV

V
V

3.5
8.0
1.5
2.0
4.5
9.0

V
V
V
V

0.5
1.0

V
V

1.0

JlA

Logical "1" Input Current I'NC1)

Vee = 15.0V

Logical "0" Input Current I,NCO)

Vee= 15.0V

Supply Current lee

Vee = 15.0V

0.05

Input Capacitance

Any Input

5.0

Propagation Delay Time to a Logical
"0" tpdQ or L~gical "1" tpd1 from
clock to Q or Q

Vee = 5.0V, C L = 50 pF, TA = 25°C
Vee = 10.0V, CL = 50 pF, T A = 25°C

180
70

300
110

ns
ns

Propagation Delay Time to a Logical
"0" from Preset or Clear

Vee = 5.0V, C L = 50 pF, TA = 25°C
Vee = 10.0V, CL'= 50 pF, T A = 25°C

180
70

300
110

ns
ns

Propagation Delay Time to a Logical
"1" from Preset or Clear

Vee = 5.0V, C L = 50 pF, TA = 25°C
Vee = 10.0V, CL = 50'pF, T A = 25°C

250
100

400
150

ns
ns

Time Prior to Clock Pulse That Data
Must be Present tSETUP

Vee = 5.0V, C L = 50 pF, TA = 25°C
Vee = 10.0V, CL = 50 pF, T A = 25°C

Time After Clock Pulse That Data
Must be Held

Vee = 5,OV, C L = 50 pF,T A = 25°C
Vee = 10.0V, CL = 50 pF, T A = 25°C

-20

Minimum Clock Pulse Width'
(t WL = tWHI

Vee= 5.0V, C L = 50 pF, TA = 25°C
Vee = 10'0!c::L= 50 pF, T A = 2:oC

Minimum Preset and Clear Pulse
Width

V ee =5.0V C L =50pF,T A =25 C
Vee = 10.OV, CL = 50 pF, T A = 25°C

Maximum Clock Rise and Fall
Time
Maximum Clock Frequency

Vee = 5.0V, C L = 50 pF
Vee = 10.0V, CL = 50 pF
Vcc = 5.0 V, CL = 50pF, TA = 25°C
V CC • 10.0V, C - 50 pF, T A • 25°C
L

-1.0

100
40

JlA
JlA
pF

ns
ns

50
20

a
a

ns
ns

100
40

250
100

ns
ns

100
40

160
70

ns
ns

-8.0

15,0
5.0
2.0
5.0

60

JlS
JlS
MHz
MHz

3.5
8.0

LOW POWER TTL/CMOS INTERFACE
Logi~al

"1" Input Voltage V ,N(1 )

54C, Vee':' 4.5V
74C, Vee = 4,75V

Logical "0" Input Voltage V,NCO)

54C, Vee = 4.75V
74C, Vee = 4.75V

Logical "1" Output Voltage V OUT(1 )

54C, Vee = 4.5V, 10 = - 360 JlA
74C, Vee = 4.75V, 10 = - 360JlA

Logical "0" Output Voltage VOUTCO}

Vee - 1.5
0.8
2.4

V
0.4

54C, Vec = 4.50V, 10 = 360 JlA
74C, Vee = 4.75V, 10 = 360JlA

V

V

OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet)
, Output Source Current (ISOURCE)

Vee = 5.0V, V'NCO} =OV
TA = 25°C, V OUT = OV

-1.75

rnA

Output Source Current (lSOURCE)

Vee = 10V, V'NCO} = OV
TA = 25°C, V OUT = OV

-8.0

rnA

Output Sink Current (lslNd

Vee· 5.0V, V INI1 )= 5.0V
TA = 25°C, V OUT = Vee

1.75

rnA

Output Sink Current (I SINK )

Vee' = 10V, V ,NC1 } = 10V
TA = 25°C, VOUT= Vee

8.0

mA

Note 1: These devices should not be connected under power on conditions.

1-28

switching time waveforms
CMOS to CMOS

Vee--------~~~------------

CLOCK
OV--......;.~

Vee
DATA

DATA

OV
Vee

o odl:

50%
OV
Vee

Oodi
OV
I,'~'

20 ns

ac test circuit

"PUT~"TA
INPUT.

CLOCK

typical applications
Ripple Counter (Divide by 2n)

Shift Register

o
0:

Guaranteed Noise Margin as a
Function of VCC

74C Compatibility
15V

'"
....
~

>

!::

'4.05

c.>

~ 3.05

1.45
0.45
4.50V

10V
Vee

1·29

15V

MM54C83/MM74C83 4-bit binary full adder
general description

features

The MM54C83/MM74C83 4-bit binary full adder performs the addition of two 4-bit binary numbers. A carry
input (Co) is included and the. sum (~) outputs are provided for each bit and the resultant carry (C 4 ) is obtained from the fourth bit. Since the carry-ripple-time is
the limiting delay in the addition of a long word length,
carry look-ahead circuitry has been included in the
design to minimize this delay. Also, the logic levels of
the input and output, including the carry, are in their
true form. Thus the end-around carry is accomplished
without the need for level inversion.

•

Wide supply voltage range

•

Guaranteed noise margin

•

High noise immunity

•

Low power
TTL compatibility

•

Fast carry ripple (Co to C4 )

•

Fast summing (~IN to ~ouT)125 ns typ @V ee = 10V
and CL = 50 pF

3V to 15V

lV
0.45 Vee typ
fan out of 2
driving 74L
50 ns typ @V ee = 10V
and CL = 50 pF

logic diagram
~
~

J

-- -'"
/
C. (14)

B. (16)

£

"
J

-

- "\.

~.

~

D-

I

~.(15)

.--

-

J
B, (4)

A,(3)

-

1£:;

.1"

~.

-

--/

~
8. (7)

A 2 (B)

~

~
--=r:[)

.1'-.--'
~,

D-

~D-

H-J - L
8,(11)

--=rr:)Tr?

~,

(2)

~2(6)

,

J
--

A,(ID)
Co (13)

1·30. ,

I

~D-

~, (9)

absolute maximum ratings

3:
!:

(Note 1)

U1

Voltage at Any Pin
Operating Temperature Range
MM54C83
MM74C83
Storage Temperature Range
Package Dissipation
Operating Vee Rang'e
Absolute Maximum Vee
Lead Temperature (Soldering, 10 seconds)

~

-0.3V to Vee + 0.3V

(")

00
W

-55°C to +125°C
-40°C to +85°C
-65°C to +150°C
500mW
3V to 15V
18V
300°C

.......

!:
!:

-...
~
(")

00
W

dc electrical characteristics

\

Min/max limits apply across temperature range, unless otherwise noted.
PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

CMOS TO CMOS
~~gical "1" Input Voltage (V IN (l))

Vee = 5.0V
Vee = 10V

Logical "0" Input Voltage (V IN (0))

Vee = 5.0V
Vee = 10V

Logical "1" Output Voltage (V OUT (l))

Vee = 5.0V, 10 = -10J.lA
Vee = 10V, 10 = -10J.lA

Logical "0" Output Voltage (VOUT(O))

3.5
8.0
1.5
2.0
4.5
9.0

Vee = 5.0V, 10 = +10J.lA
Vee = 10V, 10

V
V

=

+10J.lA

Logical "1" Input Current (lIN(1))

Vee = 15V, V IN = 15V

Logical "0" Input Current (IIN(O))

Vee = 15V, V IN

Supply Current (lee)

Vee = 15V

=

OV

-1.0

V
V
V
V

-

0.5
1.0

0.005

1.0

-0.005
0.05

V
V
pA
pA

300

pA

CMOS/LPTTL INTERFACE
Logical "1" Input Voltage (V IN (l))

54C, Vee = 4.5V
74C, Vee = 4.75V

Logical "0" Input Voltage (VIN(O))

54C, Vee = 4.5V
74C, Vee = 4.75V

Logical" 1" Output Voltage (V OU T(1))

54C, Vee = 4.5V, 10 = -360pA
74C, Vee = 4.75V, 10 = -360pA

Logical "0" Output Voltage (VOUT(O))

54C, Vee = 4.5V, 10 = 360pA
74C, Vee = 4.75V, 10 = 360pA

V
V

Vee - 1.5
Vee - 1.5
0.8
'0.8

V
V
V
V

2.4
2.4
0.4
0.4

V
V

OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet)
Output Source Current (lsouReE)
(P·Channel)

Vee = 5.0V, V OUT = OV
TA = 25°C

Output Source Current (lsouReE)
(p·Channel)

Vee = 10V, V OUT
TA = 25°C

Output Sink Current (lSINK)
(N·Channel)

Vee = 5.0V, V OIJT = Vee
TA = 25°C

Output Sink Current (I SINK )
(N·Channel)

Vee = 10V, V OUT = Vee
T A = 25°C

= OV

-1.75

-3.3

mA

-8.0

-15

mA

1.75

3.6

mA

8.0

16

mA

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be 'Operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: CPD determines the no load ac power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics
application note, AN·90.

1-31

('t)

co
.(,)'

ac electrical characteristics

~

TA

TYP

MAX

= 5.0V
= 10V

120
50

200
80

ns
ns

Vee
Vee

= 5.0V
= 10V

250
90

450
150

ns
ns

Propagation Delay from Co to Sum Outputs
(tpoo or tpo,)

Vee
Vee

= 5.0V
= 10V

350
125

550
200

':Is
ns

Propagation Delay from Sum Inputs
to Sum Outputs (tpoo or tpOl)

Vee
Vee

= 5.QV
= 10V

300
110

550
180

ns
ns

Input Capacitance

Any rnput (Note 2)

5.0

pF

Power Dissipation Capacitance (Cpo)

Per Package (Note 3)

120

pF

Propagation Delay from Co to C4 (tpoo or tpOl)

Vee
Vee

CO·

Propagation Delay from Sum Inputs to C4
(tpoo or tpo,)

it)

('t)

:e
:e

unless otherwise specified.

switching time waveforms

connection diagram
B4

~4

16

co

C4
15

MIN

CONDITIONS

PARAMETER

:e
:e
........
(,)
~

= 25°C, C L = 50 pF,

14

13

T

Bl

Al
11

12

~,

10

9

INPUT
L--

I-

-

f-

50%
're{~
~;'~
OV

---j

'5

1-20n.

500/,

100/,

rtp",
~'.'
.'~=§'.~
.
I--t, - l--tf
900/,

OUTPUT

2
A3

83

10%

Inputs must be tied to appropriate logic level.

r

4

3

~3

50%

50%
100/,

OV

1
A4

[--20ns

-

7

6
~2

Vee

B2

8

A2

truth table
OUTPUT

c~:~
-

~

INPUT

WHEN
C2-L

~COH~~
WHEN
C2=H

~~~~IX.I~I~IY,IX.I~

H

L

L

L

L

L

L

L

H

L

L

H

L

L

L

H

L

L

L

H

L

L

H

L

L

H

L

L

L

H

L

H

H

L

L

L

H

L

H

H

L

L

L

H

L

L

H

L

H

H

L

H

L

H

L

H

H

L

L

L

H

L

H

H

L

H

H

L

L

L

H

H

H

H

L

L

L

H

H

L

H

L

L

L

H

L

H

L

H

H

L

H

L

L

H

H

H

L

L

L

H

L

H

L

H

H

H

L

L

L

H

H

H

L

H

L

L

H

H

L

H

L

L

H

H

L

L

H

H

L

H

H

L

H

H

Ii

L

H

L

H

H

L

H

H

H

H

L

H

L

H'

H

H

H

H

L

H

H

H

H

H

H

= high

level, L

= low level

\

Note: Input conditions at A3, A2, 82 and CO are used to determine outputs El ahd E2 and the
value of the internal carry C2. The values at C2, A3, 83, A4, and 84 are then used to determine
outputs E3, E4, and C4.
. '

·1·32

,

UNITS

typical applications

-=
LSB

I

Co

A (BIT I)
B (BIT I)

A,

A(BIT2)

A,

B (BIT 2)

B,

A (BIT 3)

A,

B(BIT J)

B,

CaN (BIT 1) - - - - - . ,

A (BIT 1)

A,

B (BIT 1)

B,

~

(BIT I)

~

(BIT2)

~

(BIT 3)

~

(BIT4)

~

(BIT 5)

~,

~

(BIT6)

~3

~

(BIT7)

~4

~(BITB)

B,

MM54CBJ
OR
MM74CBJ

~IBIT tI

A,
COUT

A(BIT4)

A.

B (BIT 4)

B.

A(BIT5)

A,

B (BIT 5)

B,

(BIT2)

B,

----

A,

B,
A (BIT 2)

A.
!:IBIT21

B (BIT 2)

B.

CaUT

A(BIT 6)

A,

B (BIT 6)

8,

A (BIT 7)

A,

8 (BIT 7)

B, ,

A (BIT 8)

A.

8 (BIT 8)

B.

(BIT 2)

MSB

I

MM54CBJ
OR
MM74C83

C.

COUT (C.)
(TO NEXT PACKAGE)

APPLICATION

CASCADING

Connect the MM54C83/MM74C83 in the following
manner to implement a dual single bit full adder.

Connect the MM54C83/MM74C83 in the following
manner to'implement full adders with more than 4 bits.

1-33

it)

co
u
~

I'

:E
:E
.......
it)

co
u
~

it)

:E
:E

MM54C85/MM74C85 4-bit mag.nitude comparator
general description
have a high level voltage (V 1N (1)) applied to the
A=B input and low level voltages (V 1N (od applied
to A>B and ~B, AB, AB, AB, AB

CASCAOING
INPUTS

. AB

A3> B3

x
x

X

x
x
x
x
x

AB

H

x

X
X

X

x
x

A3

=

63

A2> 62

x

X

A3

A2< 62

x

X

A2" 62

AI >61

A3

= 63
= 63
= 63

= B3

A2

= 62
= B2

Al < Bl

A3
A3

A2 = B2

AI" 131

AD

< BO

X

X

A3

A2

= B2
= B2
= B2
= B2
= B2
= B2
= B2
= B2

Al = Bl

AD = BO

H

L

A3< B3

A3

= B3
= B3
A3 = B3
A3 = B3
A3 = B3
A3 = B3
A3 = B3
A3 = 83
A3 = 83

A2

A2
A2
A2
A2
A2
A2
A2

Al

= Bl

OUTPUTS

CASCADING INPUTS

A3.B3

x
X
AD> BO

X

L
H

H

L
H

X

X
X

AO--H-Hf---i:±±±~

STROBE --i:>O--Hr-Hf--+t+t---------'

'·52

3:
3:

U1
.fa

....
U1
....
........

(")

MM54C151/MM74C151 8 channel digital multiplexer

3:
3:

general description
• . Tenth power TTL
compatible

The MM54C151/MM74C151 multiplexer is a
monolithic
complementary
MOS
(CMOS)
integrated circuit constructed with N- and
P-channel enhancement transistors.
This data selector/multiplexer contains on-chip
binary decoding. Two outputs provide true (output Y) and complement (output W) data. A logical
"1" on the strobe input forces W to a logical "1"
and Y to a logical "D."
.

features
Supply voltage range

•

High noise immunity

•

Low power

D.45 Vee typ
5D nW typ

applications

All inputs are protected against electrostatic
effects.

•

drive 2 LPTTL loads

3V to 15V

•
•

Automotive
Data terminals

•
•

Instrumentation
Medical electronics

•

Alarm systems

•
•

Industrial electronics
Remote metering

•

Computers

logic and connection diagrams
D.o-----;:::===t.....,
D,o----+--1f=~---I-......

Input Protection For All Inputs

D,
DATA
INPUTS

OUTPUT(W)

D.
D.
D.

.
DATA.

SELECT

INPUT~"~

"RMINALl"~

[

c.

1-53

TO INTERNAL CIRCUIT

"

.fa
(")
....U1.
....

abso'lute maximum ratings
-0.3V to V cc +0.3V

Voltage at Any Pin (Note 1)
MM54C151
Operating Temperature

-55°C to +125°C

MM74C151

-40°C to +85°C

Storage Temperature

-65°C to +150°C

Maximum Vee Voltage
Package Dissipation
Operating Vee Range
Lead Temperature (Soldering, 10 see)

18V·
500mW
3V to 15V
300°C

electrical characteristics
Min/Max limits apply across temperature range across otherwise specified
PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

CMOS TO CMOS
Logical "1" Input Voltage

VINIl)

Vee = 5.0V
Vee = 10.0V

Logical "0" Input Voltage

VIN(O)

Vee = 5.0V
Vee = 10.0V

Logical "1" Output Voltage

V OUT (l)

Vee = 5.0V, 10 = -10J..lA
Vee = 10.0V, 10 = - 10 J..IA

Logical "0" Output Voltage VOUT(O)
\

3.5
8

V
V
1.5
2

4.5
9

V
V
0.5
1

Vee = 5.0V, 10 = +10 J..IA
Vee= 10.0V, 10 = +10J..lA

Logical "1" Input Current

IIN(l)

Vee = 15.0V, VIN = 15V

.Logical "0" Input Current

IIN(O)

Vee = 15.0V, VIN = OV

Supply Current

lee

Vee = 15.0V

V
V

V
V

1

J..IA

300

J..IA

-1

J..IA
0.05

Input Capacitance

Any Input

Propagation Delay Time to a
Logical "0" or Logical "1" from
Data to Y

Vee = 5.0V, CL = 50 pF, T A = 25°C
Vee = 10.0V, CL = 50 pF, T A = 25°C

170
80

270
130

ns
ns

Propagation Delay Time to a
Logical "0" or Logical "1" from
Datato W

Vee = 5.0V, C L = 50 pF, T A = 25°C
Vee: 1O.0V, CL : 50 pF, T A = 25°C

200
90

300
140

ns
ns

Propagation Delay Time to a
Logical "0" or Logical "1" from
Strobe or Data Select to Y

Vee: 5.0V, CL = 50 pF, T A = 25°C
Vee = 1O.0V, CL: 50 pF, TA: 25°C

240
110

360
170

ns
ns

5

pF

CMOS TO TENTH POWER
INTERFACE
Logical "1" Input Voltage

VIN(l)

54C, Vee = 4.5V
74C, Vee = 4.75V

Logical "0" Input Voltage

VIN(O)

54C, Vee = 4.5V
74C, Vee: 4.75V

V

Vee - 1.5
0.8

Logical "1" Output Voltage VO UT (l)

. 54C, Vee: 4,5V, 10 = -360J..lA
74C, Vee = 4.75V, 10 = -360J..lA

Logical "0" Output Voltage VOUT(O)

54C, Vee = 4.5V, 10 = 360 J..IA
74C, Vee = 4.75V, 10 = 360J..lA

2.4

V
V

0.4

V

OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sh'eet)

Sourc~ Current (lsouRce)

Vcc = 5.0V; VIN(O) = OV
T A = 25°C, V OUT = OV

-1.75

mA

Output Source Current (lsouRce)

Vee: 10V, VIN(O): OV
T A: 2Soc, V OUT = OV

-8.0

mA

Output Sink Current (lSINK)

Vec: 5.0V, V IN (1) = 5.0V
T A = 25°C, V OUT = Vee

1.75

mA

Output Sink Current (lSINK)

Vee: 10V, V IN (1): 10V
T A = 25°C, V OUT = Vee

8.0

rnA

Output

Note 1: This device should not be connected under power on conditions.

1-54

switching time waveforms

CMOS to CMOS (tpd1 & tpdol

OUTPUT(Wlyee~O%
50%

OY
tpdt

tpdQ

Vee
OUTPUT (VI

Ov---4--~1~----------~
Vee---jl- .r~-------

___"",,"

DATA INPUT
DATA SElECT
STROBE
OV

t"I,-20nl

ac test circuit
Vee

OUTPUT (WI

~CL050PF

TCL050PF

truth table
OUTPUTS

INPUTS

C

B

A

STROBE

00

0,

02

03

04

05

D6

07

y

X

X

X

1

X

X

X

X

X

X

X

X

0

1

0

0

0

0

0

X

X

X

X

X

X

X

~

1
0

W

0

0

0

0

1

X

X

X

X

X

X

X

1

0

0

1

0

X

0

X

X

X

X

X

X

0

1

0

0

1

0

X

1

X

X

X

X

X

X

1

0

0

1

0

0

X

X

0

X

X

X

X

X

0

1

0

1

0

0

X

X

1

X

X

X

X

X

1

0

0

1

1

0

X

X

X

0

X

X

X

X

0

1

0

1

1

0

X

X

X

1

X

X

X

X

1

0

1

0

0

0

X

X

X

X

0

X

X

X

0

1

1

0

0

0

X

X

X

X

1

X

X

X

1

0

1

0

1

0

X

X

X

X

X

0

X

X

0

1

1

0

1

0

X

X

X

X

X

1

X

X

1

0

1

1

0

0

X

X

X

X

X

X

0

X

0

1

1

1

0

0

X

X

X

X

X

X

1

X

1

0

1

1

1

0

X

X

X

X

X

X

X

0

0

1

1

1

1

0

X

X

X

X

X

X

X

1

1

0

1·55

- MM54C154/I\.1M74C154 4-line to 16-line
decoder/de mu I.tiplexe r
general description
The MM54C154/MM74C154 one of sixteen decoder is a .monolithic complementary MOS (CMOS)
integrated circuit constructed with Nand P-channel
enhancement transistors. The device is provided
with two strobe inputs, both of which must be
in the logical "0" state for normal operation. If
either strobe input is in the logical" 1" state, all
16 outputs will go to the logical "1" state.

•

Tenth power TTL
compatible

drive 2 LPTTL
loads

•

High noise margin

1V guaranteed

Ii High noise immunity

0.45 Vee typ

applications
To use the product as a demultiplexer, one of the
strobe inputs serves as a data input terminal,
while the other strobe input must be maintained
in the logical "0" state. The information will then
be transmitted to the selected output as determined by the 4-line input address.

features
•

Supply voltage range

3V to 15V

•

Automotive

•

Data terminals

•

Instrumentation

•

Medical electronics

•

Alarm systems

•

Industrial electronics

•

Remote metering

•

Computers

logic and connection diagrams

Vee

~AA--'"

INPUT PROTECTION
TO INTERNAL
FDRALLINPUTS !yy~ CIRCUITRY

OUTPUTS
INPUTS

OUTPUTS
TOP VIEW

1-56

absolute maximum ratings
Voltage at Any Pin (Note 1)
Operating Temperature Range
MM54C154
MM74C154
Storage Temperature Range
Maximum Vee Voltage

-o.3V to Vee +0.3V
-55°C to +125°C
-AO°C to +85°C
-65°C to +150°C

l8V
500mW
+3V to +15V
300°C

Package Dissipation
Operating Range, Vee
. Lead Temperature (Soldering, 10 sec)

electrical characteristics
(Min/max limits apply across temperature range unless otherwise specified.)
PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

CMOS TO CMOS
3.5
8

Logical "I" Input Voltage (V IN (1))

Vce = 5V
Vce = 10V

Logical "0" Input Voltage (VIN(O))

Vee = 5V
Vce = 10 V

Logical "I" Output Voltage (V OUT (1))

Vee = 5V. 10 = -10,uA
Vee = 10V. 10 = -10IJA

Logical "0" Output Voltage (VOUT(O))

Vee = 5V. 10 = +lOIJA
Vee = 10V. 10 = +lOIJA

V
V
1.5
2

Logical "I" Input Current (lIN(1))

Vee = 15V. V IN = 15V

Logical "0" Input Current (lIN(O))

Vce = 15V. V IN = OV

Supply Current (Ieel

Vee = 15V

4.5

V
V

9
0.5
1
0.005
-1

V
V

1

IJA

300

IJA

-0.005
0.05

V
V

IJA

Input Capacitance

Any Input

Propagation Delay to a Logical "0" From
Any Input to Any Output (t pdO )

Vee = 5V. CL = 50 pF. TA = 25°C
Vee = 10V. CL = 50 pF. TA = 25°C

275
100

400
200

ns
ns

Propagation Delay to a Logical "0" From
Gl or G2 to Any Output (tPdO)

Vee
Vee

= 5V. CL = 50 pF. TA = 25°C
= 10V. CL ,,; 50 pF. TA = 25°C

275
100

400
200

ns
ns

Propagation Delay to a Logical "I" From
Any Input to Any Output (t pdl )

Vee = 5V. CL = 50 pF. TA = 25°C
Vee = 10V. CL = 50 pF. TA = 25°C

265
100

400
200

ns
ns

Propagation Delay to a Logical "I" From
Gl or G2 to Any Output (t pdl)

Vee
Vee

= 5V. CL = 50 pF. T A = 25°C
= 10V. CL = 50 pF. TA = 25°C

265
100

400
200

ns
ns

5

pF

LOW POWER TTL/CMOS INTERFACE
. Logical "I" Input Voltage (V IN(l))

54C
74C

Vee = 4.5
Vee = 4.75

Logical "0" Input Voltage (VIN(O))

54C
74C

Vee
Vee

Logical "I" Output Voltage (VOUT(l))

54C
74C

Vee = 4.5V. 10 = -100IJA
Vee = 4.75V. 10 = -100IJA

Logical "0" Output Voltage (VOUTIO))

54C
74C

Vee
Vee

V

Vee -1.5

= 4.5
= 4.75

0.8

V

2.4

= 4.5V •.10 = 360IJA
= 4.75V. 10 = 360IJA

V

0.4

V

OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet)
Output Source Current (lSOURCE)

Vcc = 5.0V. VINIO) = OV
T A = 25°C. V OUT = OV

-1.75

mA

Output Source Current (ISOURCE)

Vcc = 10V. V INIO ) = OV
T A = 25°C. V OUT = OV

-8.0

mA

Output Sink Current (I SINK )

= 5.0V. V IN (l) = 5.0V
= 25°C. V OUT = Vcc
Vcc = 10V. V IN(1 ) ~ 10V
TA = 25°C. V OUT = Vcc
Vec

1.75

mA

8.0

mA

TA
Output Sink Current (lSINK)

Note 1: This device should not be connected to circuits with the power on because high transient voltages may cause
permanent damage.

1-57

switching time waveforms

~
'·'f '~~ ::c
vee

A, B, COR D

SO%

e

j ,mr·· :1'::r.:::

50%

OV

ANY DUTPUT

50%

" ""

5

Vee - - - - -

SO%

SO%

ANY OUTPUT
~

Vee

50%

-

~

t,

Guaranteed Noise Margin as a
Function of Vee
lSV

r-------------,
13.S
12.S

4.05
3.05
2.S
1.5

10V

4.50V

lSV

Vee

truth table

INPUTS

Gl G2
L
L
L

L
L.

OUTPUTS

0

C

B

A

0

1

2

3

4

5

6

7

8

9

10

11

12

13

L
L
L

L
L
L

L
L

L

L

H

H

H

H

H

H

H

H

H

H

H

H

H 'H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

L

L

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

L

H

L

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

L

L
.H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

L

H

H

H

H·

H

H

H

H

H

H

H
L
L
H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H'

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H
H

H
H
H

H

H
L
H

H

H

H
H
L
H

H

H

L

L
L

L
L

L
L

L
L

L
L

L
L
L

L

L

H

L

L
L

L
L
L
L

H
H

L
L

H

L

H

H

L
L

H

H

H
L
L

H

H

L
L
L
L
L

H
H

L

14

15

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H
H

H

H

H
H

H

H

H
'H

H
L

H

H

L

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

X

X

X

X

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

X

X

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

X

X
X·

X

H

x

X

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

x = "Don't Care" Condition

"·58

=t, =20 ns

MM54C157/MM74C157 quad 2-input multiplexers
general description
These multiplexers are monolithic complementary
MOS (CMOS) integrated circuits constructed with
Nand P channel enhancement transistors. They
consist of four 2-input mUltiplexers with a common select and enable inputs. When the enable
input is at logical "0" the four outputs assume
the values as selected from the inputs. When the
enable input is at logical "1" the outputs assume
logical "0." Select decoding is 'done internally
resulting in a single select input only.

•

Low power

•

Tenth power TTL compatible

50 nW (typ)
drive 2 LPTTL
loads

features
•
•

Supply voltage range
High noise immunity

3V to 15V
0.45 Vee typ

schematic and connection diagrams

truth table
V"

INPUTPROTECTlDN+rOINTERNAL
FOR ALL INPUTS
CIRCUITRY

ENABLE

SELECT

A

B

OUTPUT Y

1

X

X

X

a
a
a
a

a
a

a

x
x

a
a

1

x
x

Guaranteed Noise Margin as a
Function of Vcc
15V
13.5
12.5

1

1

1

a

a

1

1

4.05
3.05

IV~'N~IO§I~~~~~~~

1.45 ~

0.45 ' - -_ _ _L -_ _---l

74L Compatibility

'-59

4.50V

10V
Vee

15V

2.5
1.5

absolute maximum ratings
Voltage at Any Pin (Note 11
Operating Temperature
MM54C157
MM74C157
Maximum Vee Voltage

-O.JV to Vee to O.JV
-5SoC to 125°C
-40°C to +85°C
18V

e lectr ica I cha racteristics

_65°C to 150°C
500 nW
300°C
+JV to 15V

Storage Temperature

Package Dissipation
Lead Temperature (Soldering, 10 secl
Operating Vee Range

MinIMax limits apply across temperature range unless otherwise specified.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

CMOS TO CMOS
Logical "1" Input Voltage V 'NI 1)

Vee = 5.0V
Vee = 10.0V

Logical "0" Input Voltage V,NIOI

Vee = 5.0V
Vee = 10.0V

Logical "1" Output Voltage V OUTI 1)

Vee = 5.0V
Vee = 10.0V

Logical "0" Output Voltage VOUTIOI

Vee = 5.0V
Vee = 10.0V

Logical "1" Input Current I'NI1)

Vee = 15.0V

Logical "0" Input Current I'NIOI

Vee = 15.0V

v

3.5

8

V

1.5
2.0
4.5
9.0

V

V
0.5
1.0
0.005

-1.0

V
V

1.0

-0.005

V·
V

IJA
IJA

Supply Current Icc

Vee = 15.0V

0.050

Input Capacitance

Any Input

5

Propagation Delay from Data to Output
(t pdO or tpdtl

Vee ~ 5.0V CL = 50 pF, T A = 25°C
Vee=10.0V CL =50pF;T A =25°C

150
70

250
110

ns
ns

Propagation Delay from Select to
Output (tpdo or tpd,l

Vee = 5.0V CL = 50 pF, TA =.25°C
Vee = 10.0V CL = 50 pF, T A = 25°C

180
80

300
130

ns
ns

Propagation Delay from Enable to
Output (tpdol

Vee = 5.0V CL = 50 pF, TA = 25°C
Vee = 10.0V CL = 50 pF, TA = 25°C

180
80

30'0
130 .

ns
ns

60

IJA
pF

CMOS TO TENTH POWER INTERFACE
Logical "1" Input Voltage V 'NI11

54C
74C

Vee = 4.5V
V ee =4.75V

Logical "0" Input Voltage V,NIOI

54C
74C

Vee = 4.5V
Vee = 4.75V

54C

Vee = 4.5V, 10 = - 360IJA
Vee = 4.75V, 10 = - 360IJA

Logical "1" Output Voltage VOUTI'I
Logical "0" Output Voltage VOUTIOI

74C
54C

74C

v

Vee - 1.5
0.8

V

2.4

Vee = 4.5V, 10 = 360 IJA
Vee = 4.75V, 10 = 360 IJA

V

0.4

·V

OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet)

ov

Output Source Current (ISOURCE)

VCC = 5.0V, V,NIOI =
T A = 25°C, V OUT = OV

-1.75

rnA

Output Source Current (ISOURCE)

Vcc = 10V, V,NIOI = OV
T A = 25°C, V OUT = OV

-8.0

rnA

Output Sink Current (ISINK)

Vcc = 5.0V, V 'NI11 = 5.0V
T A = 25°C, V OUT = Vcc

1.75

rnA

Output Sink Current (I SINK )

Vcc = 10V, V'NI'I = 10V
T A = 25°C, V OUT = Vcc

8.0

rnA

Note 1: This device should not be connected to circuits with the power on because high transient voltage may cause .permanent
damage.

1·60

MM54C160/MM74C160 decade counter
with asynchronous clear
MM54C161/MM74C161 binary counter
with asynchronous clear
MM54Ci62/'MM74C162 decade counter
with synchronous clear
MM54C163/MM74C16'3 binary counter
with synchronous clear
general description
These (synchronous presettable up) counters are'
monolithic complementary MOS (CMOS) inte·
grated circuits constructed with Nand P channel
enhancement mode transistors. They feature an
internal carry lookahead for fast counting schemes
and for cascading packages without additional
gating.

Counting is enabled when both count enable in·
puts are high. Input T is fed forward to also enable
the carry out. The carry output is a positive pulse
with a duration approximately equal to the posi·
tive portion of Q A and can be used to enable suc·
cessive cascaded stages. ,Logic transitions at the en·
able P or T inputs can occur when the clock is high
or low.

features

A low level at the load input disables counting and
causes the outputs to agree with the data input
after the next positive clock edge. The clear func·
tion for the C162 and C163 is synchronous and a
low level at the clear input sets all four outputs
low after the next positive clock edge. The clear
function for the C160 and C161 is asynchronous
and a low level at the clear input sets all four
outputs low regardless of the state of the clock.

lV guaranteed
• High noise margin
0.45 'v cc typ
• High noise immunity
drives 2 LPTTL loads
• Tenth power TTL
compatible
• Wide supply voltage range
3V to 15V
• Internal look·ahead for fast counting scemes
• Carry output for N·bit cascading
• Load control line
• Synchronously programmable

connection diagram

.. -.

"'

U

tlt--Vee

151-~:;~~

CLOCO-2
".- I

"1-0.

IN._ •

III-a.

IN c - 5

"I-Ilo
111- 0D

1No-I
H~AIlE:'_

)

111 r-ENAIlET

G,O-I

'I-LO.O

TO' VIEW

logic waveforms
C161, ... C163 Binary Counters

C160, ... C162 Decade Counters
CL ...

I....Jr-----------

L'A'~

L"'~

{

IN.~L....-

_ _ _ _ _ _ __

IN,~L....-

_ _ _ _ _ _ __

IN,~'__

"'.. ""L..Jr---------I•• r - ! L -_ _ _ _ _ _ __
IN, _ _ _ _ _ _ _ _ _ _ __
IN,r-!L-_ _ _ _ _ _ __

_ _ _ _ _ _ _ __

IN, _ _ _ _ _ _ _ _ _ _ __

"or-!L....-_ _ _ _ _ _ __

(N".U'

EHAlLI'

,

ENABLEY

H~A'lE

CL'C'~

ClOCI(

..

,.~

0.

"""LLJ'"I

~

o.~

I
___________

Ilo~

'o~

'o~

~~L....-

tAARV

J

I

r:''-;-,-,-,-,-,-,-

CARIIY

1·61

0

Il

It

r : ' L , - ,- ,- ,- ,- , - , -

absolute maximum ratings

I

Voltage At Any Pin (Note 1)
-0.3V to V~e + 0.3V
Operating Temperature MM54C160i1/2/3 _55°C to +125°C
MM74C160/1/2/3
_40°C to +85°C
Storage Temperature
_65°C to +150°C

l8V
500mW
+3V to +15V
300"C

Maximum Vee Voltage
Package Dissipation
Operating Vee Range
Lead Temperature (Soldering. 10 sec.)

electrical characteristics
Min/Max limits apply across temperature range unless otherwise specified.

Logical "0" Input Voltage VIN(O)
Logical "1" Output Voltage V OUT (l)
Logical "0" Output Voltage VOUT(O)
Logical "l"lnput Current IIN(l)
Logical "O"lnput Current IIN(OI
Supply Current lee
I nput Capacitance
Propagation Delay Time from Clock to
Q tpdO or tpdl
Propagation Delay Time from Clock to
Carry Out tpdO or tpdl
Propagation Delay Time from TEnable
to Carry Out tpdO or tpdl
Propagation Time from Clear to Q tpdO
(C160 andC161 only)
Time Prior to Clock that Data or Load
Must be Present tSETUP
Time Prior to Clock that Enable P or T
Must be Present tSETUP
Time Prior to Clock that Clear Must
be Present tSETUP (162, 163 only)
Minimum Clock Pulses Width
tWL or tWH
Maximum Clock Rise or Fall Time
Maximum Clock Frequency

MIN

CONDITIONS

PARAMETER
CMOS to CMOS
Logical "1" Input Voltage V IN (l)

Vee
Vee
Vee
• Vee

1.S
2.0

=
=
=
=

SV
10V
SV, 10 ~ -10/iA
10V, 10 = -10/iA
= SV, 10 = +10/iA'
= 10V, 10 = +10/iA
= lSV, V IN = lSV
= lSV, V IN = OV

4.5
9.0
O.S
1.0
-1.0
~

Vec=lSV
Any Input
Vee = SV, C L
Vee = 10V, C L
Vee = SV, C L
Vee = 10V, C L
Vee = 5V, C L
Vee =; 10V, C L

MAX

3.5
8.0

Vce = SV
Vee = 10V
Vee
Vee
Vee
Vee

TYP

= SOpF, T A =
= SOpF, T A =
=; SOpF, T A=;
= 50pF, T A =
= 50pF, T A =
=; SOpF, T A=;

2Soc
2SoC.
2SoC
25°C
25°C
2SoC

Vee =
Vee =
V ee '=
Vee =
Vee =
Vee =

SV, C L = SOpF, T A = 2SoC
10V, C L = SOpF, T A = 2SoC
SV, C L = SOpF, T A = 2SoC
10V, C L = SOpF, T A = 2SoC
SV, C L = SOpF, T A = 2SoC
10V, C L = SOpF, T A = 25°C
Vee = SV, C L = SOpF. T A '= 25°C
Vee = 10V, C L = SOpF,T A'" 2SoC
Vee = SV, C L '" SOpF, T A = 2SoC'
Vee = 10V, C L = 50pF. T A = 2SoC
Vee = SV, C L = SOpF, T A = 2SoC
Vee'" 10V, CL = SOpF, T A = 25°C
Ve~ = SV, C L = SOpF, T A = 2SoC
Vee =10V, C L = SOpF, T A = 2Soc

O.OOS
-O.OOS
O.OS
S
2S0
100
290
120
180
70
190
80
120
30
170
70
120
50
90
35

2.0
S.5

1.0
300
400
160
4S0
190
290
120
300
lS0

280
120
190
80
170
70
15
S.O

3.0
8.S

UNITS
V
V
V
V
V
V
V·
V
/iA
/i A
/i A
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

/is
ps
MHz
MHz

CMOS/LPTTL INTERFACE
Logical "1" Input Voltage S4C
74C
Logical "0" I nput Voltage S4C
74C
Logical "1" Output Voltage S4C
74C
Logical "0" Output Voltage S4C
74C

Vee = 4.5V
Vee = 4.7SV
Vee = 4.SV
Vee'" 4.7SV
Vee'" 4.SV, 10 '" ~360/iA
Vee = 4.7SV; 10 =; -:-360/iA

V ec -1.S
Vee- 1. S

V
V
0.8
0.8

2.4
2.4

V
V
0.4
0.4

Vee'" 4.SV, 10'" +360/iA
Vee = 4.7SV, 10 '" +360/iA

V
V

V
V

OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet)
. Output Source Current ISOURCE
Output Source Current IsouReE
Output Sink Current ISINK
Output Sink Current ISINK

Vee = 5V, VIN(O) '" OV,
V OUT '" OV, T A'" 2Soc
Vee'" 10V, VIN(O) = OV,
V OUT '" OV, T A = 2SoC
Vee'" 5V, V IN (1) '" 5V,
V OUT = Vee, T A'" 2SoC
Vcc = 10V, V IN (l) = 10V,
V OUT = Vce, T A = 2SoC

Note 1: This device should not be connected during power on conditions.

1·62

1.75

rnA

8.0

rnA

1.75

rnA

8.0

rnA

logic diagrams
MM74C160, MM74C162; Clear is Synchronous for the MM74C162

CARRY
OUTPUT

CLEAR
CLOCK

LOAD

ENABLE P

ENABLET~'------------------------------------"'"

MM74C161, MM74C163; Clear is Synchrono~s for the MM74C163

CARRY
OUTPUT
CLEAR

CLOCK

LOAD

ENABLE P

ENABLET~""-'-----------------------------------I

1·63

switching time waveforms
CLEAR

LOAD

INPUT

ENABLEP
OR T

CLOCK

OUTPUT

tpdCLEARforC16DandC161 only

Note 1: All input pulses are from generators having the following character istics: t,=1, =
20 ns PRR::; 1 MHz dutV cvcle::; 50%, ZOUT '" SOl!.
Note 2: All times are measured from 50% to 50%.

cascading packages
+v
+V

CDUNT-t.....- - - - - - -. . .- - - - - - -. . .- - - - - -

MM54C164/MM74C164
8-bit parallel-o~Jt serial shift register
general description
The MM54C164iMM74C164 shift registers are a
monolithic
complementary
MOS
(CMOS)
integrated circuit constructed with N- and
P-channel enhancement transistors. These 8-bit
shift registers have gated serial inputs and clear.
. Each register bit is a D-type master/slave flip flop.
A high-level input enables the other input which
will then determine the state of the flip flop.

-

High noise immunity

-

Low power

-

Medium speed operation

Data is serially shifted in and out of the 8-bit
register during the positive going transition of
clock pUlse. Clear is independent cif the clock and
accomplished by a low level at the clear input.
All inputs are protected agai nst electrostatic effects.

-

Data terminals

-

Instrumentation

-

Medical electronics

-

Alarm systems

-

Industrial electronics·

-

Remote metering

-

Computers

Supply voltage range
Tenth power TTL compatible

50 nW typ
8.0 MHz typ
with 10V supply

applications

features
-

0.45 Vee typ

3V to 15V
drive 2 LPTTL
loads

block diagram

CLOCK

truth table

connection diagram

Serial Inputs A and B
OUTPUT

tn

tn+1

A

B

1

1
1

0
1

0

1-65

INPUTS

0
0

QA

1

0
0
0

absolute maximum ratings
Voltage at Any Pin (Note 1)
-0.3 V to Vee + 0.3 V
Operating Temperature MM54C164 -55°C to +125°C
MM74C164 _40°C to +85°C
Storage Temperature
-65°C.to +150°C

Maximum Vec Voltage
18V
Package Dissipation
500 mW
Operating Vec Range
+3 V to + 15 V
Lead Temperature' (Soldering, 10 seconds)
300°C

electrical characteristics
Minimax limits apply

acro~s

temperature range unless otherwise specified.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

CMOS TO CMOS
Logical "1" Input Voltage V INllI

Vee = 5.0V
Vee = 10.0V

Logical "0" Input Voltage VINIOI

Vee=5.0V.
Vee = 1O.0V .

Logical "1" Output Voltage VOUTllI

Vee=5.0V, 10 = -10MA
Vee = 10.0V,10 = -10MA

Logical "0" OutputVoltage VOUTIOI

Vee=5.0V, 10 = -10MA
Vee = 10.0V, 10 '= -10MA

Logical "l"lnput Current IINllI

Vee = 15.0V, V IN = 15V

Logical "0" Input Current IINIOI

Vee = 15.0V, V IN = OV

I

3.5
8

1.5
2

V
V
V
V

4.5
9.0
0.5
1
0.005
-1

V
V

1

-0.005.

V
V
MA
MA

Supply Current Icc

Vee = 15.0V

0.05

I nput Capacitance

Any Input

5

Propagation Delay Time to a Logical "0" or
a Logical "1" from Clock to Q

Vee=5.0V, C lt = 50 pF, T A = 25°C
Vee = 10.0V, C L = 50pF, T A = 25°C

Propagation Delay Time to a Logical "0" from
Clear to Q

Vee=5.0V, C L = 50pF, T A = 25°C
Vee = 10.0V, C L = 50pF, TA = 25°C

Time Prior to Clock Pulse that Data Must be
Present tSETUP

Vee = 5.0V, C L = 50pF, T A = 25°C
Vee = 10.0V, C L = 50pF, TA = 25°C

Time After Clock Pulse that Data Must be
Held

Vee=5.0V, C L ~ 50pF, T A = 25°C
Vee = 10.0V, C L = 50pF, T A = 25°C

Maximum Clock Frequency

Vee=5.0V, C L = 50pF, T A = 25°C
Vee = 10.0V, C L = 50pF, TA = 25°C

Minimum Clear Pulse Width

Vee = 5.0V, C L = 50pF, T A = 25°C
Vee = 10.0V, C L = 50pF, TA = 25°C

Maximum Clock Rise and Fall Time

Vee = 5,OV, C L = 50pF, T A = 25°C
Vee = 10.0V, C L = 50pF, T A = 25°C

15
5

MS
MS

Logical "l"lnput V~ltage VINlll

54C: Vee = 4.5V
74C: Vee = 4.75 V

Vee - 1.5

V

Logical "0" Input Voltage VINIOI

54C: Vee = 4.5V
74C: V ee =4.75V

Logical "1" Output Voltage VOUTlll

54C: Vee = 4.5 V, 10 = -360MA
74C: Vee = 4.75V, 10 = -360MA

Logical "0" Output Voltage VOUTIOI'

54C: Vee = 4.5 V, 10 = 360MA
74C: Vee = 4.75 V, 10 = 360MA

200
80

300

MA

230
90

310
120

ns
ns

280
110

380
150

ns
ns

pF

110
30

ns
ns

0
0,

0
0

ns
ns

2
5.5

3
8

MHz
MHz

150
55

250
90

ns
ns

CMOS TO TENTH POWER INTERFACE

0.8

2.4

V

V

,
0.4

V

OUTPUT DRIVE (See 54C174C Family-Characteristics Data Sheet)
Output Source Current (lsouReE)

Vee = 5.0V, VINIOI = OV
T A = 25°C, VOUT=OV

-1.75

mA

Output Source Current (lsouReE)

Vee = 10V, VINIOI = OV
T A = 25°C, Vou-r=OV

-8.0

mA

Output Sink Current (lSINK)

Vee = 5.0V, VINlll = 5.0V
T A = 25°C, V OUT = Vee

1.75

mA

Output Sink Current (lslt'JK)

Vec = 10V, VINlll = 10V
T A =25°C, VouT=Vee

8.0

mA

Note 1: T~ese devices should not be connected under power on conditions.

1·66

ac test circuit
INPUTS {

CLOCK

switching time waveforms

u

CLIAR~

::::~~ {._+-__

....1

0,

==,-'--___----,-_____-Jr---L.Il~---=:'
~L...-!I----0,::'
r--,
==,
n'-_____
0,

0,

' - 1_ _ _ _ _

o.

nJAA

tlJAA

TTL to CMOS

CMOS to CMOS

4.0V---+-J,------CLOCK

OV---..II
4.0V-+-1;:n.7"'-+-~

OATA

OATA

DV
Vee

Vee
l.SV
OV
Vee
DV
t,=t,"20ns

typical applications
Guaranteed Noise Margin as a Function of VCC
15V

74C Compatibility
Vee

4.05
3.05

1.45
0.45
4.50V

10V
Vee

1-67

15V

MM54C165/MM74C165 parallel-load 8-bit shift register
general description
long as the shift/load input is high. When taken
low, data at the parallel inputs is loaded directly
into the register independent of the state of
the clock.

The MM54C165/MM74C165 is an 8-bit serial shift
register which shifts data from Q A to Q H when
clocked. Parallel inputs to each stage are enabled by
a low level at the shift/load input. Also included
is a gated clock input and a complementary output
from the eighth-bit.

features

. Clocking is accomplished through a 2-input NORgate pern:itting one input to be used as a clockinhibit function. Holding either· of the clock inputs
high inhibits clocking, and holding either clock
input low with the shift/load input high enables
the otller clock input. Data transfer occurs on the
positive edge of the clock. The clock inhibit i.nput
should be changed to a high level only while the
clock input is high. Parallel loading is inhibited as

•

Wide supply voltage range

., Guaranteed noise margin
•

High noise immunity

•

Low power
TTL compatibility

•

Direct overriding load

•
•

Gated clock inputs
Fully static operation

connection diagram
PARAllEL INPUTS

SHIFTI
LOAD

CLOCK

OUTPUT
PARAllEl INPUTS

0"

block diagram
CLOCK
CLOCK INHIBIT

S/L

X>-----+Sii
~Lo_--~----~~----~~----_1------~------~------~--------_,
Siio---+_-.----~~--~r-~--~--~--_+--._--~~~--+__1--__,
SERIAL
INPUT

10

PARALLEL INPUTS

1-68

3.0V to 15V
1.0V
0:45 Vee typ
fan out of 2
driving 74L

absolute maximum ratings

(Note 1)

Voltage at Any Pin
Operating Temperature Range
MM54C165
MM74C165
Storage Temperature Range
Package Dissipation
Operating Vee Range
Absolute Maximum Vee
Lead Temperature (Soldering, 10 seconds)

-o.3V to Vee +O.3V
-55°C \0 +125°C
-40°C to +85°C
-65°C to +150°C
500mW
3.0V to l5V
laV
300°C

dc electrical characteristics
Minimax Iimits apply across' temperature range, unless otherwise noted.
PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

CMOS TO CMOS
Logical "'" Input Voltage (V IN (1))

Vee = 5.0V
Vee = 10V

"a" Input Voltage

Vee = 5.0V
Vee = 10V

Logical

(V IN 101)

Logical "'" Output Voltage (VOUTI1))
Logical

"a" Output Voltage

(VOUTIOI)

Logical "," Input Current (1INI1))
Logical

"a"

Input Current (lINIO))

Supply Current (Icc)

V
V

3.5
8.0
1.5
2.0

Vee = 5.0V, 10
Vee = 'OV, 10

= -10pA
= -10pA

V

4.5
9.0

V

Vee = 5.0V, 10 = +10pA
Vee = 'OV, 10 =+10pA
Vee = 15Y, VIN
Vee

= 15V,

0.5
1.0

= 15V

VIN = OV

0.005
-1.0

'.0

V
V
pA
pA

"0.005
0.05

Vee=15V

V
V

300

pA

CMOS/LPTTL INTERFACE
Logical "1" Input Voltage (V INI1 ))
Logical

"a"

Input Voltage (V INIO ))

54C, Vee = 4.5V
74C, Vee = 4.75V

Vec 1.5
V ee -l.5

V
V

54C, Vee = 4.5V
74C, Vee = 4.75V

0.8
0.8

Logical "'" Output Voltage (VOUTI1d

54C, Vee = 4.5V, 10 = -360pA
74C, Vee = 4.75V, 10 = -360pA

Logical "0" Output Voltage (V OUTlOI )

54C, Vee = 4.5V, 10 = 360pA
74C, Vee = 4.75V, 10 = 360pA

V
V
V
V

2.4
2.4
0.4
0.4

V
V

OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet)
Output Source Current (lsouReE)
(P·Channel)

Vee = 5.0V, V OUT = OV,
TA = 25°C

-1.75

-3.3

rnA

Output Source ~urrent (lsouReE)
(P·Channel)

Vee = 10V, VbUT = OV,
TA = 25°C

-8.0

-15

rnA

Output Sink Current (lSINK)
(N·Channel)

Vee = 5.0V, V OUT
TA = 25°C

= Vee,

1.75

3.6

rnA

Output Sink Current (I SINK )
(N·Channel)

Vee = 10V, V OUT
TA = 25°C

= Vee,

8.0

16

rnA

1-69

Il)

CD

U
~

ac electrical characteristics

T

A =

25°C, CL

=

50 pF, unless otherwise specified.

r--

~

PARAMETER

........

Propagation Delay Time to aLogical "0"

CONDITIONS

MIN

TYP

MAX

Vee; 5.0V
Vee; 'OV

200
80

400
200

ns
ns

Vee; 5.0V
Vee; 'OV

200
80

400
200

ns
ns

~.

Il)

CD

(tpdO), or Logical "'" (t pdl). from Clock
or Load to Q or 0

"""
U

Propagation Delay Time to a Logical "0"

Il)

(tpdO). or Logical "'" (tpd1 ). from H to
QorO

~

~
~

-

UNITS

Clock Inhibit Set-up Time

Vee; 5.0V
Vee; 10V

150
60

75
30

ns
ns

Serial Input Set-up Time

Vee; 5.0V
Vee; 10V

50
30

25
15

ns
ns

Serial Input Hold Time

Vex; ; 5.0V
Vee; 10V

50
30

0
0

ns
ns

P(lrallel Input Set-up Time

Vee; 5.0V
Vee; 10V

150
60

75
30

ns
ns

Parallel Input Hold Time

Vee; 5.0V
Vee; 10V

50
30

0
0

ns
ns

Minimum Clock Pulse Width

Vee; 5.0V
Vee; 10V

70
30

200
100

ns
ns

Minimum Load Pulse Width

Vee; 5.0V
Vee; 10V

85
30

180
90

ns
ns

Maximum Clock Frequency

Vee; 5.0V
Vee ~ 10V

6.0
12

2.5
5.0

MHz
MHz

Maximum Clock Rise and Fall Time

Vee =5.0V
Vee; 10V

Input Capacitance (C IN )

(Note 2)

5.0

pF

Power Dissipation Capacitance (C pd )

(Note 3)

65

pF

10
5.0

/1s
/1S

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The
table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.

-

'.

Note 3: Cpd determines the no Joad ac power consumption of any CMOS device. For complete explanation see 54C/74C
Family Characteristics application note, AN-90_

switching time waveforms
-

Vee ---- CLOCK
INHIBIT

CLOCK

0.5 Vee
OV
Vee
D. 5Vcc
OV
Vee

SERIAL
INPUT

- r:)

=======-__-_-__==~
-----

tWICLOCKI-

-----------

0.5 Vee
OV

F&H
INPUTS

0.5

Vee,

SHIFTI
LOAD

0.5

Vee
Vee
OV

Vee
OV-

~--..'SEt

J

Fk_'l"lleLoeKI

,
-

r-

tHOLD -

'HOLrl,. .-+-_-I_'SET--t-- tw ILOADI

----'f------,.---=1
........ 1
/

-I----J
-

QH

X-.

,'l

'''--/

_I",.

0.5~::-h

_

~---........

~

' - - - - -_
_
t'II·
_ _ _ _ tpdQ

OV
_ _ tpd1

Vec---'--r-\.

OH . 0.5 Vee
OV

~

1--'""

\
~

_ _ _- J

Note A: The remaining silt data and the serial input are low.
NoteB: Prior to test, high level data is loaded into H input.

'·70

"---

L-..I

truth table
INPUTS
SHIFTI
LOAD

PARALLEL

CLOCK
INHIBIT

CLOCK

INTERNAL
OUTPUTS

SERIAL
A ... H

OA

OUTPUT

°B

OH

L

X

X

X

a. .. h

a

b

h

H

L

L

X

X

GAO

Gao

OHO

L

t
t
t

H

X

H
H

L

H

H

H

OAn

QGn

L

X

L

GAn

QGn

X

X

GAO

Gao

OHO

X =- irrelevant
I ~ transition from VIN(Ol to VIN(1)
a ... h = the level at data inputs A thru H
0AO. 0BO. 0HO ~ the level of 0A. 0B or QH. before the indicated input conditions were established
0An. OSn ~ the level of 0A Or Os before the most recent I transition of the clock

logic waveforms
CLOCK
CLOCK INHIBIT

+-_____________

SERIAL INPUT _ _..;....._ _
SHIFT/LOAD

OATA

OUTPUT

0..

I

~INHI8IT

LOAD

- - - - - - SERIAL SHIFT - - - - - - - - - -

.

1·71

MM54C173/MM74C173 TRI-STATE® quad 0 flip-flop
general description
The MM54C173/MM74C173 TRI·STATE quad D
flip flop is a monolithic complementary MOS
(CMOS) integrated circuit constructed with N
and P·channel enhancement tra'nsistors. The four
D type flip flops operate synchronously from a
common clock. The TRI·STATE output allows the
device to be used in bus organized systems. The
outputs are placed in the TRI·STATE mode when
either of the two output disable pins are in the
logic "1" level. The input disable allows the flip
flop to remain in their present states without
disrupting the clock. If either of the two input
disables are taken to a logic "1" level, the Q
outputs are fed back to the inputs and in this
manner the fl ip flops do not change state.

•

features
Supply voltage range

0.45' Vcc typ

•

High noise immunity

•

Low power

•

Medium speed operation

•

High impedance TRI·STATE

•

Input disabled without gating the clock

applications

Clearing is enabled by taking the input to a logic
"1" level. Clocking occurs on the positive going
transition.

•

Drive 2 LPTTL
loads

Tenth power TTL
compatibie

3V to 15V

•

Automotive

•

Data terminals

•

Instrumentation

•

Medical electronics

•

Alarm systems

•

Industrial electronics

•

Remote metering

•

Computers

logic and connection diagrams

DATAINPur{
OISAILE

Vee

tun

INPUT
A

INPUT

INPUT

C

D

OUTPUT (IUTPUT DUTPUT OUTPUT DunUT OUTPUT

OISAILEDISA,LE

1-72

A

•

C

0

OATA

DATA

INPUT

INPUT

DISAILEDISAILE

CP

absolute maximum ratings
Voltage at Any Pin (Note 1)
Operating Temperature
MM54C173
MM74C173
Storage Temperature
Maximum Vee Voltage
Package Dissipation
Operating Vee Range
Lead Temperature (Soldering, 10 sec)

-0.3 to Vee +O.3V
-55°C to +125°C
-40°C to +85°C
-B5°C to +150°C
18V
500mW
+3V to +15V
300°C

electrical characteristics
Min/max limits apply across temperature range unless otherwise specified.
PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

CMOS TO CMOS
Logical "'" Input Voltage VIN(I)

Vee = 5.0V
Vee = 'O.OV

Logical "0" Input Voltage VIN(O)

Vee = 5.0V
Vee = 'O.OV

Logical "'" Output Voltage VOUT(I)

Vee = 5.0V
Vee c 10.0V

Logical "0" Output yoltage VOUT(O)

Vee = 5.0V
Vee = 10.0V

Logical "'" Input Current IIN(I)

Vee = 15.0V

3.5
8
1.5
2
4.5

V
V
V
V

9
0.5
1

0.005
-1

Logical "0" Input Current IIN(O)

V
V

1

V
V
IJ.A

-0.005

IJ.A
IJ.A
IJ.A

Output Current in High Impedance State

_
Va = '5V
Vee - 15V, Va = OV

0.001
0.001

Supply Current lee

Vee = lSV

0.05

Input Capacitance

Any Input

S

Propagation Delay Time to a Logical "a" (t pdO )
or Logical"'" (tPdl ) From Clock to Output

Vee = 5.0V, CL = 50 pF, t A = 25°C
Vee = 10.0V, CL = 50 pF, T A = 25°C

220
80

400
200

ns
ns

Input Data Setup Time, ts DATA

Vee = 5.0V, CL = 50 pF, TA = 25°C
Vee = 10.0V, CL = 50 pF, TA = 2SoC

40
15

80
30

ns
ns

Input Data Hold Time, tH DATA

Vee = 5.0V,C L =50pF, TA =2SoC
Vee = 10.0V, CL = 50 pF, TA = 25°C

0
0

0
0

ns
ns

Input Disable Setup Time, ts DISS

Vee = S.OV, CL = 50 pF, TA = 2SoC
Vee = 10.0V, CL = SO pF, T A = 25°C

100
" 35

200
70

ns
ns

Input Disable Hold Time, tH DISS

Vee = S.OV, CL = 50 pF, TA = 25°C
Vee = 10.0V, CL = 50 pF, TA = 2SoC

0
0

a

ns
ns

Delay From Output Disable to High Impedance
State (From Logical "I" or Logical "a" Level).
t lH , tOH

Vee = 5.0V, C L = 5pF, T A = 25°C
RL = 10k
Vee= 10.0V, C L = 5pF, TA = 25°C
RL = 10k

170
70

340
140

. Delay From Output Disable to Logical "I"
Level, tH I (From High Impedance State)

Vee = 5.0V, C L = 50 pF, TA = 25°C
Vee = 10.0V, CL = 50·pF, TA = 25°C

170
70

340
140

ns
ns

Delay From Output Disable to Logical "a"
Level, tHO (From High Impedance State)

Vee = 5.0V, CL = 50 pF, TA = 25°C
Vee = 10.0V, CL = SO pF, TA = 25°C

170
70

340
140

ns
ns

Propagation Delay From Clear to Output tpdR

Vee = 5.0V, CL = 50 pF, T A = 25°C
Vee = 10.OV, CL = 50 pF, T A = 25°C

240
90

490
180

ns

Maximum Clock Frequency

Vee = 5.0V, CL = 50 pF, TA = 25°C
Vee = 10.OV, CL = 50 pF, TA = 25°C

Minimum Clear Pulse Width

Vee = 5.0V, CL = 50 pF, TA = 25°C
Vee = H).OV, CL = 50 pF,"T A = 25°C

Maximum Clock Rise and Fall Time

Vee = 5.0V, CL = 50 pF
Vee = 10.OV, CL = 50 pF

-

,

Note 1: These devices should not be connected under "Power On" conditions.

1·73

3.0
7

4.0
12
150
70

10
5

300

IJ.A
pF

0

ns
ns

MHz

ns
IJ.S
IJ.S

electrical characteristics (con't)
CONDITIONS

PARAMETER

TYP

MIN

MAX

UNITS

LOW POWER TTL/CMOS INTERFACE
Logical"'" Input Voltage V IN (l)

54C, Vee = 4.5V
74C, Vee = 4.75V

Logical "0': Input Voltage VIN(O)

54C, Vee = 4.5V
74C, Vee = 4.75V

Logical "'" Output Voltage V OU T(l)

54C, Vee = 4.5V, 10 = -360pA
74C, Vee = 4.75V, 10 = -360pA

Logical "0" Output Voltage VOUT(O)

54C:V ee = 4.5V, 10 = 360J..[A
74C, Vee = 4.75V, 10 = 360J..[A

Propagation Delay Time to a Logical "0", tpdO

V

.8

V

2.4

.4

Vee = 5.0V, CL = 50 pF, T A = 25°C

or Logical "'" tpdl From Clock

V

500

V

ns

OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet)
Output Source Current (ISOURCE)

Vee = 5.0V, V'NIO) = OV
T A = 25°C, V OUT = OV

-1.75

mA

Output Source Current (ISOURCE)

Vec = 'OV, V,~(O) = OV
T A = 25°C, V OUT = OV

-8.0

rnA

Output Sink Current (lSINK)

Vce = 5.0V, V IN(1 ) = 5.0V
T A = 25°C, V OUT = Vcc

1.75

rnA

Output Sink Current (lSINK)

Vcc= 'OV, V 'N (1) = 10V
TA = 25°C, V OUT = Vcc

8.0

rnA

·truth table
Truth Table (Both Output Disables Low)
tn+1
DATA INPUT DISABLE

DATA
INPUT

Logic" 1" on One or Both Inputs
Logic "0" on' Both Inputs
Logic "0" on Both Inputs

X
1
0

OUTPUT

an
1
0

switching time waveforms

,1(.:\'
',_Jj

CLEAR

SO%

~

' - - - - - : - - - - - - - - - - - - - - - -_ __

SO%

r-l

gl~!~~~ --+--"-D-'SS-1'1

----i

DATA

INPUT

I

SO%

SO%

SO%

r

I, D'SS --j

~IHOISS

--+------+-1-.....
Is DATA

_~

------

I

~tHDISS

--rT

ASO%

I SO%

SO% __

~

Is D:TA

)
SO%

OY, --~r--IHDATA ~-~ r--:-'HDATA

SO%
CLOCK
OATA

--+------'
~

I

"--1

Ipd.

OUTPUT
\SO%
~

SO%

10%

r-- --

t
I

Ipd'

!

_ _ _ _ _ _ _ _ _ _ _ _ _ _- J

1·74

SOy,

SO%

SOY,

. -

I ...

--

'

SO%

MM54C174/MM74C174 hex 0 flip-flop
general description

features

The MM54C174/MM74C174 hex 0 flip-flop is a
monolithic complementary MOS (CMOS) integrated
circuit constructed with N- and P-channel enhancement transistors. All have a direct clear input.
Information at the 0 inputs meeting the setup time
requirements is transferred to the Q outputs on the ,
positive-going edge of the clock pulse. Clear is
independent of clock and accomplished by a low
level at the clear input_ All inputs are protected by
diodes to Vee and GND.

• Wide supply voltage range

3.0V to 15V

1.0V

• Guaranteed ,noise margin
•

High noise immunity

•

Low power
TTL compatibility

0.45 Vee typ
fan out of 2
driving 74L

logic diagram
DATA

Cl

IT

Ci

Cl

mtmt

ClEAR---------4------I

truth table

connection diagram

OUTPUT

INPUTS

CLEAR

1Q

10

20

2Q

3D

3Q

GNO

TOP VIEW

'-75

a

CLEAR

CLOCK

0

L

x

x

L

H

t
t

H

H

H

L

L

H'

L

X

a

absolute maximum ratings

(Note 1)

Voltage at Any Pin
Operating Temperature Range
MM54C174
MM74C174
Storage Temperature Range
Package Dissipation
Operating Vee Range
Absolute Maximum Vee
Lead Temperature (Soldering, 10 seconds)

-o.3V to Vee +0.3V
-55°C to +125°C
-40°C to +85°C
-65°C to +150°C
500 mW
3.0V to 15V
18V
300°C

dc electrical characteristics
Min/max limits apply across temperature range, unless otherwise noted.
PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

CMOS TO CMOS

Logi~al"l" Input Voitage (V INI 1))

Vee
Vee

= 5.0V

Logical "0" Input Voltage (V INIO ))

Vee
Vee

= 5.0V
= 10V

Logical "1" Output Voltage (VOUTll))

Vee = 5.0V, 10 = -101lA
Vee = 10V, 10=- lOIlA

Logical "0" Output Voltage (VOUTIO))

Vee = 5.0V, 10 = + lOll A
Vee = 10V, 10 = +1 Oil A

Logical "1" Input Current (lINI1))

Vee=15V,

Logical "0" Input Current (IIN(OI)

Vee

~

Supply Current (Icc)

Vee

= 15V

~

V
V

3.5
8.0

10V

1.5
2.0

V
V

4.5
9.0

0.005

V IN = 15V
-1.0

15V, V IN = OV

V
V

0.5
1.0

V
V

1.0

IlA

-0.005
0.05

IlA
300

IlA

CMOS/LPTTL INTERFACE
V
V

V ee -1.5
V ce -1.5

Logical "1" Input Voltage (V IN (l))

54C, Vee=4.5V
74C, Vee = 4.75V

Logical "0" Input Voltage (VIN(oil

54C, Vee = 4.5V
74C, Vee = 4.75V

Logical "1" Output Voltage (VOUTll))

54C, Vce =4.5V, 10 = -3601lA
74C, Vee = 4.75V, 10 = -3601lA

Logical "0" Output Voltage (VOUT(OI)

54C, Vee '= 4.5V, 10
74C, Vee = 4.75V, 10

0.8
0.8
2.4
2.4

V
V

'.

= 360llA
= 360llA

0.4
0.4

V
V
V
V

OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet)
Output Source Current (lsouReE)
(P·Channel)

Vec = 5.0V, V OUT
T A =25°C

= OV,

-1.75

-3.3

rnA

Output Source Current (lsouReE)
(P·Chan nel)

Vee = 10V, V OUT
T A = 25°C

= OV,

-8.0

-15

rnA

Output Sink Current (lSINd
(N·Channel)

Vee = 5.0V, V OUT
TA = 25°C

Output Sink Current (I SINK )
(N·Channel)

Vee = 10V, V OUT
T A = 25°C

-

= Vee,
= Vee,

1-76

1.75

3.6

rnA

8.0

16

rnA

ac electrical characteristics

TA

= 25

D

C, C L

s:
s:
U1

= 50 pF, unless otherwise specified.

~

('")
PARAMETER

CONDITIONS

TVP

MIN

MAX

UNITS

Propagation Delay Time to a Logical
"0" (tpdo) or Logical "1" (t pd1 )
from Clock to Q

Vee = 5.0V
Vee = 10V

150
70

300
110

ns
ns

Propagation Delay Time to a Logical
"0" from Clear

Vee = 5.0V
Vee = 10V

110
50

300
110

ns
ns

Time Prior to Clock Pulse that Data
Must be Present (tsETUP)

Vee = 5.0V
Vee = 10V

75
25

Time After Clock Pulse that Data
Must be Held.(tHoLo)

Vee = 5.0V
Vee = 10V

75
25

Minimum Clock Pulse Width

ns
ns
-10
-5

0
0

ns
ns

Vee = 5.0V
Vee = 10V

50
35

250
100

ns
ns

Minimum Clear Pulse Width

Vee = 5.0V
Vee = 10V

65
35

140
70

ns

Maximum Clock Rise (lnd Fall Time

Vee = 5.0V
Vee = 10V

15
5.0

>1200
>1200

Maximum Clock Frequency

Vee = 5.0V
Vee = 10V

2.0
5.0

6.5
12

MHz
MHz

Input Capacitance (C IN

Clear Input (Note 2)
Any Other Input

11
5.0

pF
pF

Per Package (Note 3)

95

pF

)

Power Dissipation Capacitance (C pd )

ns
J.(s
J.(s

Note 1: "Absolute Maximum'Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except
for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The
table of "Electrical Characteristics" provides conditions for actual device operation.
'
Note 2: Capacitance is guaranteed by periodic testing.
'Note 3: Cpd determines the no load ae power consumption of any CMOS device. For complete explanation see 54C/74C
Family Characteristics application note, AN·90.

switching time waveforms

ac test circuit

CMOS to CMOS

--j',

CLOCK

OV _ _....;.;10;;,.;%-"\

DATA

r-

vee ----I-J'"=::------, .1F.90%
vee:J(:
--j" ~:%
50%
OV 'O%

50%

1~1_0%_ _ __

'SETUP'

: 'SETUP 0

ee 9Oii\l __

tHOLD 1

_I

'HOLD 0

II

V

DATA

.

I~O~

ov --j,,~

Vee

INPUT- DATA

9;.it,'
50%
.

INPUT -

O%

~

50'10
10%

--i"
f--

t pd'-/50%

ov

Vee -----+----"""
f--'pdO-\sO%
OV----------,--t,-tt- 2Dns

1-77

CLOCK

~
~

.........

s:
3:
......
~

~

~

MM54C175/MM74C175 quad D flip-flop

general description
The MM54C175/MM74C175 consists of four positiveedge-triggered Ootype flip-flops implemented with monolithic CMOS technology. Both true and complemented
outputs from each flip-flop are externally available. All
four flip-flops are controlled by a common clock and a
common clear. Information at the 0 inputs meeting the
set-up time requirements is transferred to the Q outputs
on the positive going edge of the clock pulse. The clearing
operation, enabled by a negative pulse at Clear input,
clears all four Q OUtputs to logical "0" and Cl-s to'
logical "1."

All inputs are protected from static discharge by diode
clamps to Vee and GNO.

features
•
•
•

Wide 5u pp iy voltage range
Guaranteed noise margin
High noise immunity

•

Low power
TIL compatibility

3.0V to 15V
1.0V
0.45 Vee typ
fan out of2
driving 74L

connection diagram and truth table
Vee

4Q

4ii

40

30

3ii

3Q

CLOCK

Each Flip-Flop

OUTPUTS

INPUTS

H
L
X

t

Q

X

L

H

H

H

L

L

L

H

H

X

NC

NC

L

X

NC

NC

CLOCK

0

L

X

H
H
H
H

t
t

=
=
=
=
NC =

TOP VIEW

Q

CLEAR

High level
Low level
Irrelevant
Transition from low to high level
No change

logic diagrams
Cl

I}-'
u

CLEAR

TYPICAL ONE OF FOUR

'-78

absolute maximum ratings
Voltage at Any Pin
Operating Temperature Range
MM54C175
, MM74C175
Storage Temperature Range
Package Dissipation
Operating Vee Range
Absolute Maximum Vee
Lead Temperature (Soldering, 10 seconds)

dc electrical characteristics

(Note 1)
-Q.3V to Vee +0.3V
-55°C to +125°C
-40°C to +B5°C
-u5°C to +150°C
500mW
3.0V to 15V
lBV
300°C

Min/max limits apply across temperature range, unless otherwise noted.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

.CMOS TO CMOS
Logical "1" Input Voltage (V IN (l))

Vee
Vee

= 5.0V
= 10V

Logical "0" Input Voltage (VIN(O))

Vee
Vee

= 5.0V
= 10V

Logical "1" Output Voltage (V OUT (l))

Vee
Vee

= 5.0V,
= 10V,

'0
10

= -10pA
= -10pA

Logical "0" Output Voltage (VOUT(O))

Vee
Vee

= 5.0V,
= 10V,

'0
10

= 10pA
= 10pA

Logical "1" Input Current (1IN(ll)

Vee

= 15V,

V IN

= 15V

Logical "0" Input Current (IIN(O))

Vee

= 15V,

V IN

= OV

Supply Current (Ieel

Vee

= 15V

Logical "1" Input Voltage (V IN (l))
MM54C175
MM74C175

Vee
'Vee

= 4.5V
= 4.75V

Logical "0" Input Voltage (VIN(O))
MM54C175
MM74C175

Vee
Vee

= 4.5V
= 4.75V

Logical "1" Output Voltage (V OUT (l))
MM54C175
MM74C175

Vee
Vee

= 4.5V,
= 4.75V,

Logical "0" Output Voltage (VOUT(O))
MM54C175
MM74C175

Vee = 4.5V, 10
Vce= 4.75V, '0

V
V

3.5
B.O
1.5
2.0
4.5
9.0

V
V

0.005
-1.0

V
V

0.5
1.0

V
V

1.0

pA

-0.005
0.05

pA
300

pA

CMOS/LPTTL INTERFACE

V ee -l.5
V ee -l.5

V
V

O.B
O.B

'0
10

= -360pA
= -360pA,

V
V
V
V

2.4
2.4

= 360pA
= 360pA

0.4
0.4

V
V

OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet)
Output Source Current (lsouReE)
(P·Channel)

Vee = 5.0V; V OUT
T A = 25°C

= OV

-1.75

-3.3

mA

Output Source Current (lsouReE)
(P-Channel)

Vee = 10V, V OUT
T A = 25°C

= OV

-B.O

-15

mA

Output Sink Current (l sINK )
(N-Channel)

Vce = 5.0V, V OUT
T A = 25°C

= Vee

1.75

3.6

mA

Output Sink Current (ISINd
(N-Channel)

Vee = lOV, V OUT
T A = 25°C

= Vee

B.O

16

mA

1·79

It)

8
it

::E
::E

ac electrical characteristics

= 25°C, C L = 50

TA

pF, unless otherwise specified.
MIN

CONDITIONS

PARAMETER

TYP

MAX

UNITS

"""

Propagation Delay Time to a Logical
"0" (tpdo) or Logical "1" (t pd 1) from
Clock to Q or Q

Vee
Vee

= 5.0V
= 10V

190
75

300
110

ns
ns

It)

~

Propagation Delay Time to a Logical
"0" from Clear to Q

Vee
Vee

= 5.0V
= 10V

180
70

300
110

ns
ns

::E
::E

Propagation Delay Time to a Logical
"1" from Clear to Q

Vee
Vee

= 5.0V
= 10V

230
90

400
150

ns
ns

Time Prior to Clock Pulse that Data
~ust be Present (tSET-UP)

Vee
Vee

= 5.0V
= 10V

Time after Clock Pulse that Data
must be Held (tHOLO)

Vee
Vee

= 5.0V
= 10V

Minimum Clock Pulse Width

Vee
Vee

= 5.0V
= 10V

Minimum Clear Pulse Width

Vee
Vee

= 5.0V
= 1o.V

Maximum Clock Rise Time

Vee
Vee

= 5.0V
= 10V

15
5.0

450
125

ps
ps

Maximum Clock Fall Time

Vee
Vee

= 5.0V
= 10V

15
5.0

50
50

ps
ps

Maximum Clock Frequency

Vee
Vee

= 5.0V
= 10V

2.0.
5.D.

3.5
10

MHz
MHz

Input Capacitance (C IN )

Clear Input (Note 2)
Other Input

10
5.0

pF
pF

Power Dissipation Capacitance (C pd )

Per Package (Note 3)

130

pF

It)

8

100
40

45
16

ns
ns

a
a

ns
ns

130
45

250
100

ns
ns

120
45

250
100

ns
ns

-11
-4

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
.
Note 2: Capacitance.is guaranteed by periodic testing.
Note 3: CPO determines the no load ac power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics
application note, AN-gO.

switching time waveforms
CMOS to CMOS

vee----t-..r-::::::-----CLOCK

ov--....:.::.:.::..rl
Vee -II-~=-+--::::::-i
DATA

DATA

ov -I1-1~-1-..:.::.::~
Vee -"'-----+------,...[lOR II

50%

OV----+----J
vee----t----"'[lOR Ii
oV----------~-

1-80

MM54C192/MM74C192 synchronous
4-bit up/down decade counter
MM54C193/MM74C193 synchronous
4-bit up/down binary counter
general description
counters also have carry and borrow outputs so
that they can be cascaded using no external
circuitry.

These up/down counters are monolithic complementary MOS (CMOS) integrated circuits_ The
MM54C192 and MM74C192 are BCD counters_
While the MM54C193 and MM74C193 are binary
'counters.

features

Counting \Jp and counting down is performed by
two count inputs, one being held high while the
other is clocked. The outputs change on the positive going transition of this clock.
These counters feature preset inputs that are set
when load is a logical "a" and a clear which forces
all outputs to "a" when it is at logical "1." The

•

High noise margin

1 V guaranteed

•

Tenth power
TTL compatible

drive 2 LPTTL
loads

•

Wide supply range

•

Carry and borrow outputs for N-bit cascading

•

Asynchronous clear

•

High noise immunity

3V to 15V

0.45 Vee typ

connection diagram
OUTPUTS
, -INPUTS
--, ,--,
Vee

o~A

CLEAR
14

1~

116

BORROW CARRY
13

INPUTS
LOAD

DATA
C

11

10

12

r-

r--

2

1
DATA
B
INPUT

9

D.

4

1

COUNT
DOWN

D.

~

OUTPUTS

5
COUNT
UP

7

6

Dc

Do

I!'
GND

~

\

OUTPUTS
INPUTS
TOPVIEW

cascading packages
Guaranteed Noise Margin as.
A Function of Vee

LOAD
DATA INPUTS

I~V

DATA INPUTS

13.5
12.5

UP
CLOCK

UP
TO NEXT
STAGE

DOWN
. CLOCK

4.0~

3.05

DOWN

V,N(O)

2.5
1.5

1.4~

0.45
OUTPUTS

4.50V

OUTPUTS

10V
Vee

CLEAR

1-81

15V

absolute maximum ratings
Voltage at Any Pin (Note 1 )
-o.3V to Vee + 0.3V
Operating Temperature Range
MM54C192, MM54C193
-55°C to +125°C
MM74C192, MM74C193
-40"C to +85"C
Storage Temperature Range
-65°C to +150°C

electrical characteristics

Maximum Vee Voltage
Package Dissipation
Operating Vee Range
Lead Temperature (Soldering, 10 sec)

(Min/max limits apply across temperature range unless otherwise specified.)
CONDITIONS

PARAMETER

1BV
500mW

MIN

TVP

MAX

UNITS

CMOS TO MOS
Logical "1" Input Voltage IV,Nll,)

Vcc=5V
Vee = 10V

Logical "0" Input Voltage IV,N,OI)

Vee = 5V
Vee = 10V

Logical"'" Output Voltage IVOUTll,)

Vee = 5V, 10 - -lOliA
Vee = 10V. 10 = ·lOJ.1A

Logical "0" Output Voltage IV OUT 1011

Vee = 5V. 10 = tl0J.1A
Vee = 10V, 10 = +lOJ.1A

Logical "1" Input Current II'Nllll

Vee = 15V, V ,N = 15V

Logical "0" Input Current II'N 1011

Vee = 15V. V ,N = OV

V
V

3.5

8
1.5

2
4.5

V
0.5

0,005

10

300

Vee = 5V, C L = 50 pF. TA - 25"C
V ee ,= 10V, C L = 50 pF, TA = 25°C

250
100

400
160

Propagation Delay Time to Borrow
From Count Down (tpdo 01 t",,, I

Vee = 5V, C L = 50 pF, TA = 25C
V ee -l0V.C L =50pF, T A =25C

120
50

200
80

Propagation Delay Time to Carry
From Count Up ItpdO 01 tp

;::

~

0.2

I

cc
u
u

~

0

1.0

u

0.8

~

~

90% 01 units
95% o~units
98% 01 units

,,

0.6

,

0.4
0.2

*

5

.;!

I-

u

I- "

;iE ~
cc>

w.lT"
5

OUTPUT PULSE WIDTH (Tw, %)

Figure 4

Typical Variation in Output
Pulse Width vs Temperature

Typical Power Dissipation
per Package

2.0

II

1.5

~

I"'"

L

z

;::
;t
400
~~

.....

PULSE WIDTH = 1000~s

1.0

500

0

';'V

NDTE: POWER SHOWN IS MEASURED
WITH BOTH ONE·SHDTS SWITCHIN~
TOGETHER, Ar D ~EXT = lOOk

V"F-

/

C.§.

0.5

cc..,

01-

~

~::

:Jet
Q> -0.5
~;'

;j~

.~tee.i~r

Figure 3

~et
..,w

.... '"

Vee = 5V

I~Vee:l0V

I
I

-5 -2 0 2

OUTPUT PULSE WIDTH (Tw, %)

~g:
~~

0% Point pulse width:
At Vee = 5V,
At Vee = 10V,
At Vee = ·15V,

tr\

>

;::

1\

-5 -2 0 2

:;
z

Percentage 01 units within ±4%:
At Vee = 5V,
At Vee = 10V,
At Vee = 15V,

TA = 25°C
REXT = 10k
CEXT = O.I~F

Z

REXT .= 10k H-++H-t-+H-i
CEXT = 1000 pF -++-+-+-++-f-+4 0% Point pulse width:
At Vee = 5V, Tw = 10.6~s
1.0
At Vee = 10V, Tw = 10~s
0.8 K-+-+-t-t--tll-+ftt-+-tVee = 5V r- At Vee = 15V, Tw = 9.8~s

-

-1.D

~~ -1.5
-55

~I
I I

i'oo..

~

r-

25

W'",

300

~~

200

etCo.
ucc

~~
I

rE

'"

Vee=15VV

/

/
100

/

/

IL _I-"'"

Vee =10V

f..-f-

I.- ~I

I Vee =5V

50

125

TA - AMBIENT TEMPERATURE eC)

OUTPUT DUTY CYCLE (%)

switching time waveforms

Vee--~~

A INPUT

. Vee ----+------~_.I
BINPUT

Vee----+-----------r---~~

CLEAR

Vee ----+---+.r-----~

Vee - - - - - - - .

'·94

I100

Tw = 1020~s
Tw = 1000~s
Tw = 98211s

Percentageolunitswithin±4%:
At Vee = 5V, 95% 01 units
At Vee = 10V, 97% 01 units
At Vee = 15V, 98% 01 units

Advance Information

MM74C373 octal latch
MM74C374 octal D-type flip-flop
general description
The MM74C373 and MM74C374 are integrated, comple·
mentary MaS (CMOS), 8·bit storage elements with
TRI·STATE@outputs. These outputs have been specially
designed to drive highly capacitive loads, such as one
might find when driving a bus, and to have a fan·out
of 1 when driving standard TTL. When a high logic level
is applied to the OUTPUT DISABLE input, all outputs
go to a high impedance state, regardless of what signals
are present at the other inputs and the state of the
storage elements.
The MM74C373 is an 8·bit latch. When LATCH ENABLE
is high the Q outputs will follow the D inputs. When
LATCH ENABLE goes low, data at the D inputs, which
" meets the setup and hold time reguirements, will be
retained at the outputs until LATCH ENABLE returns
high again.
The MM74C374 is an 8·bit, D·type,positive·edge trig,
gered flip·flop. Data at the D inputs, meeting the setup
and hold time requirements, is transferred to the Q
outputs on positive·going transitions of the CLOC K
input.

Both the MM74C373 and the MM74C374 are being
assembled in the new 20·pin dual·in·line package with
0.300" pin centers.

features
• Wide supply voltage range

3.0V to 15V

•

High noise immunity

0.45 Vee typ

•

Low power consumption
fan·out of 1 driving
standard TTL

• TTL compatibility
•

Bus driving capability

• TRI·STATE@outputs
•

Eight storage elements in one package

• Single CLOCK/LATCH
DISABLE control inputs
•

ENABLE

and

OUTPUT

20·pin dual·in·line package with 0.300" centers takes
half the board space of a 24'pin package

connection diagrams

OUTPUT

OUTPUT

VCC

DISABLE
01

08

01

01-+--+-4

H--~,;,..-08

ol-~--H

02 --+---+-4

1-+---+--07

'02-+---H

02

07

03

06

03-+--+-4

H---+;;"'06

04-~--+-4

1-f--~~05

08

1-f---+;""'-07
07

02

06
1-+--+--06

03-+--H

1-f--~~05

as

04

VCC

OISABLE

as

04

GNO

CLOCK

GNO

MM74C374

MM74C37;3
TOP VIEW

,1·95

truth tables
MM74C374

MM74C373
OUTPUT
DISABLE

LATCH
ENABLE

D

Q

OUTPUT
DISABLE

L

H

H

H

L

L

H

L

L

L

L

X

H

X

X

CLOCK

D

Q

-...r
-...r

H

H

L

L

L

Q

L

L

X

Q

Hi-Z

H

X

X

Hi-Z

L = low logic level
H = high logic level
X = irrelevant
~= low to high logic level transition
Q = preexisting output level
Hi-Z = high impedance output state

logic diagrams
1 OF 6 lATCHES

"---I»--4>JD

VCC

00

OUTPUT
DISABLE

T
MM74C373

1 OF 6 FLIP-FLOPS

Vee _

"Q

t Ci ........ t

r-.....

Cl

ClOCK~

D

OUTPUT
DISABLE

-t>o-Lt>J
.

00
.

Cl

i

T
MM74C374

1-96

MM54C901/MM74C901 hex inverting TTL buffer
MM54C902/MM74C902 hex non-inverting TTL buffer
MM54C903/MM74C903 hex inverting PMOS buffer
MM54C904/MM74C904 hex non-inverting PMOS buffer
general description

features

These hex buffers employ complementary MOS
to achieve wide supply operating range, low power
consumption, high noise immunity. These buffers
provide direct interface from PMOS into CMOS
or TTL and direct interface from CMOS to TTL
or CMOS operating at a reduced Vee supply. For
specific applications see MOS Brief 18 in the back
of this catalog.

• Wide supply vo!tage range

3.0V to 15V

• Guaranteed noise margin
•

1.0V

High noise immunity

.• TTL compatibility

0.45 Vee typ
fan out of 2 driving
standard TTL

connection and logic diagrams
MM54C901/MM74C901
MM54C903/MM74C903

MM54C902/MM74C902
MM54C904/MM74C904

Vee

GNO

GNO

TOPVIEW

TorVIEW

MM54C903/MM74C903
PMOS to TTL or CMOS Inverting Buffer

MM54C901/MM74C901
CMOS to TTL Inverting Buffer

MM54C904/MM74C904
PMOS to TTL or CMOS Buffer

MM54C902/MM74C902
CMOS to TTL Buffer

. . .f rEP rJJ 14~

."~~~)-'"~

~ ~

1·97

absolute maximum ratings

(Note 1)

Voltage at Any Output Pin
-o.3V to Vee +0.3V
Voltage at Any Input Pin
MM54C901/MM74C901
-o.3V to +15V
M M54C902/M M 74C902
-o.3V to +15V
MM54C903/MM74C903
Vee -17V to Vee +0.3V
M M54C904/M M7 4C904
Vee -17V to Vee +0.3V
Operatin9 Temperature Range
MM54C901, MM54C902, MM54C903, MM54C904-55°C to +125°C'
MM74C901~ MM74C902, MM74C903, MM74C904 -40°C to +S5°C
-65°C to +150°C
Storage Temperature Range
Package Dissipation
500 mW
Operating Vee Range
I
3.0V to 15V
Absolute Maximum Vee
lav
Lead Temperature (Soldering, 10 seconds)
300°C

dee leetriea I eha raeteristies
MinImax limits apply across temperature range, unless otherwise noted.
PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

CMOS TO CMOS
Logical "1" Input Voltage (V IN (ll) .

Vee = 5.0V
Vee = 10V

Logical "0" Input Voltage (VIN(O))

Vee = 5.0V
Vee = 10V

Logical "1" Output Voltage (V OUT (l))

Vee = 5.0V, 10 = -1 Oil A
Vee = 10V, 10 = -lOIlA

Logical "0" Output Voltage (VOUT(O))

Vee = 5.0V, 10 = +lOIlA
Vee = 10V, 10 ='+lOIlA

V
V

3.5
S.O
1.5
2.0

Logical "1" Input Current (1IN(l))

Vee = 15V, VIN = 15V

Logical "0" In~ut Current (1IN(o)1

Vee = 15V, VIN = OV

Supply Current (I eel

Vee=15V

V
V
V

4.5
9.0
0.5
1.0
0.005
-1.0

V

1.0

-0.005
0.05

V
V

pA
IlA

15

IlA

TTL TO CMOS
Logical "1" Input Voltage (V IN (l))

54C, Vee = 4.5V
74C, Vee = 4.75V

Logical "0" Input Voltage (VIN(Q))

54C, Vee = 4.5V
74C, Vee =4.75V

V
V

VeC1.5
V ee -l.5
O.S
O.S

V
V

CMOS TO TTL
Logical "1" Input Voltage (V IN (lI)
MM54C901, MM54C903
. MM54C902, MM54C904
MM74C901, MM74C903
MM74C902, MM74C904

Vee
Vee
Vee
Vee

= 4.5V
=,4.5V
= 4.75
= 4.75

Logical "0" Input Voltage (VIN(O))
MM54C901, MM54C903
MM54C902, MM54C904
MM74C901, MM74C903
MM74C902, MM74C904

Vee
Vee
Vee
Vce

= 4.5V
= 4.5V
= 4.75
= 4.75

Logical "1" Output Voltage (V OUTllI )
Logical "0" Output Voltage (VOUT(O))
MM54C901, MM54C903
MM54C902, MM54C904
MM74C901, MM74C903
MM74C902, MM74C904

54C, Vee
74C, Vee
Vee
Vee
Vee
Vee

= 4.5V,

V
V

4.0
V ee -l.5
4.25
V ee ·-1.5

V
V

1.0
1.5
1.0
1.5
10 = -SOOIlA
10 = -SOOpA

= 4.75V,

2.4
2.4

= 4.5V, 10 = 2.6 mA
= 4.5V, 10 = 3.2 mA
= 4.75V, 10 = 2.6 mA
= 4.75V, 10 = 3.2 mA

V

V
V
V

V
V

0.4
0.4
0.4
0.4

V
V
V
V

OUTPUT DRIVE (MM54C901/MM74C901, MM54C903/MM74C903) (See 54C/74C Family Characteristics Data Sheet)
Output Source Current (lsouReE)
(P·Channel)

Vee = 5.0V, V OUT = OV
T A = 25°C, VIN = OV

-5.0

mA

Output Source Current (IsouReE)
(p·Channel)

Vee = '-OV, V OUT = OV
T A = 25°C; VIN = OV

-20

mA

Output Sink Current (lSINK)
(N·Channel)

Vee = 5.0V, V OUT = Vee
TA = 25°C, VIN = Vee

Output Sink Current (lSINK)
IN·Channel)

Vee = 5.0V, V OUT = O.4V
TA. = 25°C, V IN = Vee

1-98

mA
3.S

mA

~
~

dc electrical characteristics (con't)

U1
~

CONDITIONS

PARAMETER

MIN

TVP

MAX

n
CD

UNITS

0~

OUTPUT DRIVE (MM54C902/MM74C902, MM54C904/MM74C904 (See 54C/74C Family Characteristics Data Sheet)

........

Output Source Current (lsouRCE)
(P·Channel)

Vce = 5.OV, V OUT = OV
TA =25°C, V ,N =Vee

-5.0

mA

Output Source Current (lsouReE)
(p·Channel)

Vee = 10V, V OUT = OV
T A = 25°C, V,~ = Vee

-20

mA

.....

Output Sink Current (lslNd
(N·Channel)

Vee = 5.0V, V OUT = Vee
TA = 25°C, Y'N = OV

mA

n
CD

Output Sink Current (I SINK )
(N·Channel)

Vee = 5.0V, V OUT = 0.4V
TA = 25°C, Y'N = OV

ac electrical characteristics

TA

3.8

~

0~

mA

~
~

= 25°C, CL = 50 pF, unless otherwise specified.
CONDITIONS

PARAMETER

~
~

TVP

MIN

U1

MAX

~

n
CD

UNITS

MM54C901/MM74C901, MM54C903/MM74C903

0

Input Capacitance (C ,N )

Any Input. (Note 2)

14

Power Dissipation Capacity (C pd )

(Note 3) Per Buffer

30

Propagation Delay Time to a Logical "1" (t pd l1l1

Vee = 5.0V
Vee = 10V

38

Vce = 5.0V
Vee = 10V

Propagation Delay Time to a Logical

"a"

(tpdIO) 1

22

ns
ns

21
13

35
20

ns

~
~

.....
~

n
CD

ns

-

Input Capacitance (C 'N 1

Any Input (Note 21

5.0

Power Dissipation Capacity (C pd )

(Note 31 Per Buffer

50

Propagation Delay Time to a Logical "1" (tpdl1l1

Vcc = 5.0V
Vce = 10V

57
27

90
40

ns

Propagation Delay Time to a Logical "0" (tpdIO) 1

Vcc = 5.0V
Vcc = 10V

54
25

90
40

ns
ns

Notl 2: Capacitance is guaranteed by periodic testing.

0
N

pF
pF

ns

~
~

U1

~

n

CD

0

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. E'xcept
for "Operating Range" 'they are not meant to imply that. the devices should be operated at these limits. The table of
"Electrical Characteristics" provides conditions for actual device operation.

W
........

~
~

I

.....

Note 3: CpD determines the no load ac power consumption of any CMOS device. For complete explanation see 54C/74C
Family Characteristics application' note, AN·90.

~

n
CD

typical applications

Vee

0

CMOS to TTL or CMOS at a Lower VCC

PMOS to CMOS or TTL Interface

1-T

TTL
OR

CMOS

-: 1r-CMOS~. C~~S

V,"2

"--Tl \' "--T~-----4-------+~----~----~

I

-=- ~IMM&4C901/MM7'C901
-

MMS4C9QlIMM14C90JOr\
... SOC904/IIM74C904

W

~I ~L,

Vee.

eNO

:snv

........

pF
70
30

MM54C902/MM74C902, MM54C904/MM74C904

NOTE: Vee +VOD
Vcc:S15V

N

pF

NOTE: Vee1 ,:;;V CCl

ac test circuit and sw~tching time waveforms
CMOS to CMOS

~M&4C902/MM74C902

"\

~
~

U1
~

n

CD

0

~

........

3:
3:
.....
~

n

CD

0

Vee

V'"
DV

Vee

Nota: Delays measured with input t,. tt

=20

ns.
OV

1·99

~

typical performance characteristics
Typical Propagation Delay to a
Logical "1" for the MM54C901/
MM74C901 and MM54C903/
MM74C903

Typical Propagation Delay to a
Logical "0" for the MM54C901/ .
MM74C901 and MM54C903/
MM74C903
100
90
80
70
.-;;;

.s

j

60
50
40

.,,/

20

.~

10
0

-

/

225

.I ...~~ 1 - ~o(7

200
175

I I

]

I~-

.,,/

30

250

I I
I I 7"'~
I,,~
~I
j

1/00

't'

150

/V'

125

/

100

, 1/

75

~ i"""-Joo=10~~

50

YOOI: 'jV_~

25

~

~~

o

w

Voo ·15V

~ ~ ~100IWMol~I~200

CL (pF)

CL (pF)

Typical Propagation Delay to a
Logical "0" for the MM54C902/
MM74C902 and MM54C904/
MM74C904
250

I

225

;'1.01/

Typical Propagation Delay to a
Logical "1" for the MM54C902/
MM74C902 and MM54C904/
MM74C904
250

i.-~i""""

225
200

~~~
~~

175

N

o

en
o

;:!:
~
~

175

150

150

~

]

125

125

j

100

j.

75

Voo =5.0V

50

Voo",0 V

25

~
;;;;

O'

o 20 40 60 80 100120140 160 180200

200

~
V~

....
I-r- H,<::'~/
I-r- 40 00+/
./

,/

100
75

-

~

50
25

Veo ·15V

o

r-

-v~e~

,..... ,,~
~

Voo .'5~-

~

p
t--

o 2040 60 80 100120140160180 200

o 20 40 60 80 100120140160180200
CL (pF)

CL (pF)

........
N

o

en

o

lilt

11)

~
~

...

o
en
o

;:!:

~
~

...

........

o

en

o

lilt

11)

~
~

1-100

MM54C905/MM74C905 12-bit successive approximation register
general description
The MM54C905/MM74C905 CMOS 12·bit successive
approximation register contains all the digit control and
storage necessary for successive approximation analog·
to·digital conversion. Because of the unique capability
of CMOS to switch to each supply rail without any offset
voltage, . it can also be used in digital systems as the
control and storage element in repetitive routines.

0.45 Vee typ
fan out of 2
driving 74L

• High noise immunity
•

Low power TTL
compatibility

• Provision for register. extension or truncation
• Operates in STARTISTOP or continuous conversion
mode

features
• Wide supply voltage range

1.0V

• Guaranteed noise margin

• Drive ladder switches directly. For 10 bits or less
with 50k/l00k R/2R ladder network

3.0V to 15V

connection diagram

vCC

T
24

Ul1

Nt

23

22

Qll

21

Ql0

Q9

Q8

19

20

Q7

18

17

Q8

16

tP

Nt

15

14

-

13

-

/
11 .1.12

10

/

CC

DO

I

QO

Ql

Q2

Q3

Q4

Q5

Nt

GND

truth table
TIME

10
11
12
13

14

INPUTS

OUTPUTS

o

DO

all

010

09

08

07

06

05

04

03

02

01

00

X

x

x

X

X

X

X

X

X

X

X

X

X

X

X

H

H

H

H'

H

H

H

H

H

H

H

CC

011

H

X

010
09
08
07
06
05
04
03
02
01
DO
X
X
X

H

011

011

H

H

H

H

H

H

H
H

H

H

H

H

H

010

011

010

L

H

H

H

H

H

H

H

·H

H

H

H

09

011

010

09

H

H

H

H

H

H

H

H

H

H

011

010

09

L

H

H

H

H

H

H

H

H

011

010

09

L

H

H

H

H

H

H

H

011'

010

09

07
07

H

H

H

H

H

H

011

010

09

L

H

H

H

H

H

011

010

09

H

H

H

H

011

010

09

L

H

H

H

011

010

011

010

H

08
07
06
05
04
03
02
01
DO

011

010

X

X

011

X

H

H
H
H

H
H
H

H

X

H

07
07
07
07

010

09
09
09
09

08
OS
08
08
08
08
08
08
08
08

NC

NC

NC

H • High level
L ,. Low level

X ... Don't care
NC .. No change

1·101

07

06
06
06
06
06
06
06
06

05
05
05
05
05
05
05

NC

NC

NC

07
07

04
04
04
04
04
04

03
03
03
03
03

02
02
02
02

NC

NC

NC

H

H

01

L

H

01

DO

L

01

DO

L

NC

NC

NC

absolute maximum ratings
Voltage at Any Pin
Operating Temperature Range
MM54C905
MM74C905
Storage Temperature Range
Package Dissipation
Operati ng Vee Range
Absolute Maximum Vee
Lead Temperature (Soldering, 10 seconds)

de eleetriea I eha raeteristies
PARAMETER

(Note 1)
-o.3V to Vee +0.3V
-55°C to +125°C
-40°C to +85°C
~5°C to +150°C
.500 mW
3.0V to 15V

lav
300°C
Min/max limits apply across temperature range, unless otherwise noted.
CONDITIONS

MIN

TYP

MAX

UNITS

CMOS TO CMOS
Logical "1" Input Voltage (V IN (1))

Vee = 5.0V
Vee = 10V

Logical "0" Input Voltage (VIN(O))

Vee = 5.0V ,
Vee = 10V

Logical "1" Output Voltage (V OU T(l))

Vee = 5.0V, to = -101lA
Vee = 10V, to = -101lA

Logical "0" Output Voltage (VOUT(O))

Vee = 5.0V, 10 = 10llA
Vee = 10V, 10 = 10llA

Logical "1" Input Current (1IN(l))

Vee = 15V, V IN = 15V

Logical "0" Input Current (IINIO))

Vee = 15V, V IN = OV

Supply Current (Ieel

Vee = 15V

V
V

3.5
8.0
1.5
2.0

V
V

4.5
9.0

0.005
-1.0

V
V

0.5
1.0

V
V

1.0

Il A

-0.005
0.05

Il A
300

Il A

CMOS/LPTTL INTERFACE
Logical ·"1" Input Voltage (V IN11 ))
MM54C905
MM74C905

Vee = 4.5V
Vee = 4.75V

Logical "0" Input Voltage (VIN10))
MM54C905
MM74C905

Vee = 4.5V
Vee = 4.75V

Logical "1" Output Voltage (V OUTI 1))
MM54C905
MM74C905

Vee = 4.5V, 10 = -3601lA
Vee = 4.75V, 10 = -3601lA

Logical "0" Output Voltage (VOUT(O))
MM54C905
MM74C905

Vee = 4.5V, 10 = 360llA
Vee = 4.75V, 10 = 360llA

Vee -1.5

V
V

V ee -l.5
0.8
0.8

V
V

V
V

2.4
2.4

0.4
0.4

V
V

OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet)
Output Source Current (lsouReE)
(P·Channel)
Output Source Current (lsouReE)
(P·Channel)

Vee = 5..: 0V , V OUT
T A = 25°C

= OV

'. Vee = 10V, V OUT ; OV
T A =25°C

-1.75

-3.3

mA

-8.0

.,..15

mA

Output Sink Current (l sINK )
(N·Channel)

Vee = 5.0V, V OUT
T A =25°C

= Vee

1.75

3.6

mA

Output Sink Current (lSIN K)
(N·Channel)

Vee = 10V, V OUT
T A =25°C

= Vee

8.0

16

mA

011-00 Outputs

Vee = 10V ±5%
V OUT = Vee - 0.3V
T A = 25°C

150

Vee = 10V ±5%
V OUT = 0.3V
TA = 25°C

80

RsouReE

RSINK

1-102

.350

230

ac electrical characteristics

TA

= 25°C, CL = 50 pF, unless otherwise specified.
MIN

CONDITIONS

PARAMETER

TYP

MAX

200
80

350
150

UNITS
ns
ns

325
125

ns
ns

350
150

ns
ns

350
0.50

ns

Propagation Delay Time From Clock
Input To Outputs (00-011) (tpd(Q))

Vee
Vee

= 5.0V
= 10V

Propagation Delay Time From Clock
Input To Do (tpd(OO))

Vee
Vee

= 5.0V
= 10V

180
70

Propagation Delay Time From Register
Enable (E) To Output (011) (tpd(E))

Vee
Vee

= 5.0V
= 10V

190
75

Propagation Delay Time From Clock
To CC (tpd(CC))'

Vee
Vce

= 5.0V
= 10V

190
75

Data Input Set· Up Time (t05)

Vce
Vee

= 5.0V
= 10V

80
30

ns

Start Input Set· Up Time (t55)

Vee
Vee

= 5.0V
= 10V

80
30

ns
ns

Minimum Clock Pulse Width (tPWL, tpWH)

Vee = 5.0V
Vec = 10V

Maximum Clock Rise and Fall Time (t r , tf)

Vee
Vec

= 5.0V
= lOV

Maximum Clock Frequency (f MAX )

Vee
Vee

= 5.0V
= 10V

,

250
100

.

ns
ns

125
50

ns
ns

ps
ps

15
5
2

4

5

10

MHz
MHz

Clock Input Capacitance (C eLK )

Clock Input (Note 2)

10

pF

Input Capacitance (C IN )

Any Other Input (Note 2)

5

pF

Power Dissipation Capacitance (Cpo)

(Note 3)

100

pF

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Ch%>'7~~

OJ

ri

o

£

200

200

O'---'--'--'---.J._L.-"--'--'----'

o

-55 -35 -15

-55-35-15525456585105125

5

25 45

65 85 105 125

TA - AM81ENT TEMPERATURE (OC)

TA - AM81 ENT TEMPERATURE ("C)

• These points are guaranteed by automatic testing.

• These points are guaranteed by automatic testing .

1·103

timing diagram

all

:::-l-J.________________--.:. .___________

010~
09

::.:J

os=::J
:::.:J
06::.==J .
==.:.J
=----.J
:::.:J
::::.:J

LJ

07

LJ

05

LJ

04

OJ

LJ

Q2

01~

oo==:J

LJ

cc~

Do

switching time waveforms

Vee

Vee - - - " ' "

--t~xr-

Vee------i--"'"

+-_ _ __

, -_ _ _ _

011
0------

Vee------f---,..-----+--"
010

Vee--:-------------+---r---..,.--_+_~

Do
-tpd

Vee - - - - - - - -r

Vee
011

---------.

{.~l

l..,"{\.....--_
1·104

USER NOTES FOR A/D CONVERSION
The register can be used with either current switches
that require a 'low voltage level to turn the switch ON or
current switches that require a high voltage level to turn
the switch ON. If current switches are used which turn
ON with a low logic level, the resulting digit outPllt from
the register is active low. That is, a logic "1" is represented
as a low voltage level. If current switches are used which
turn ON with a high logic level, the' resulting digit
output is active high. A logic "1" is represented as a high
voltage level.

range +1/2 LSB and using the complement of the MSB
011 as the sign bit.
If the register is truncated and operated in the contino
uous conversion mode, a lock·up condition may occur
on power-ON. This situation can be overcome by making
the START input the "OR" function of CC and the
appropriate register 0l:ltput.
The register, by suitable selection of register ladder
network, can be used to perform either binary or
BCD conversion.

For a maximum error of ±1 /2 LSB, the comparator must
be biased. If current switches that require a high voltage
level to turn ON are used, the comparator should be
biased +1/2 LSB and if the current switches require a
low logic level to turn ON, then the comparator must be
biased -1/2 LSB.

The register outputs can drive the 10 bits or less with
50k/l00k R/2R ladder network directly for Vce = 10V
or higher. In order to drive the 12-bit 50k/l00k ladder
network and have the ±1/2 LSB resolution, the
MM54C902/MM74C902 or MM54C904/MM74C904 is
used as buffers, three buffers for MSB (011), two buffers
for 010, and one buffer for 09.

Tlie register can be used to perform 2's complement
conversion by offsetting the comparator one half full

typical applications
12-Bit Successive Approximation A-to·D Converter, Operating in Continuous
Mode, Drives the 50k/100k Ladder Network Directly
12·Bit Successive Approximation A·to·D Converter
Operating in Continuous a·Bit Truncated Mode

V.,,·' OV----,
r

Vee

CLD CK

MMS4C902
IMMJ4C902
ORMMS4C9114
/MMJ4C9Q4

0

~

00

Do

ce

MMS4C90SIMMJ4C905

':'

C.

all

010

09

01

OJ

06

as

01

QJ

02

01

SERIAL
DATA
OUT

j"'' ' '

I~ 7e~ 71

DATA OUT

r-- ;=.

100.

lOOk

...

'0'
R·lRUDDER
R-SOI<

100'

RIR LADDER

ANALOG IN'UT--'~--I

' - - ~4MM54C909'
50.
ANALOG IN'U T

V

definition of terms
CP: Register clock input.
CC: Conversion complete-this output remains at
V OUT (1) during a conversion and goes to Vo UT(O) when
conversion is complete.
D: Serial data input-connected to comparator output in
A-to-D applications.
E: Register enable-this input is used to expand the
length of the register. When E is at V IN (1) 011 is forced
to VOUT (1L and inhibits conversion. When not used for
expansion E must be connected to VIN(O) (GND).
011: True register MSB output.

011: Co'inplement of register MSB output.
Oi

Ii = 0 to 11): Register outputs.

s:

Start input-holding start input at VIN(O) for at least

one clock period will initiate a conversion by setting
MSB (011) at VOUT(O) and all other output (010-00)
at V OUT (1)' If set-up time requirements are met, a conversion may be initiated by holding start input at VIN(O)
for less than one clock period.

DO: Serial data output-D input delayed by one clock
period.

1·105

~~
~
~
~

S
~

MM54C906/MM74C906 hex open drain N-channel buffers
MM54C907/MM74C907 hex open drain P-channel buffers

~

it)

~
~

general description

features

These buffers employ monolithic CMOS technology
in achieving open drain outputs. The MM54C906/
MM74C906 consists of six inverters driving six N-channel
devices; and the MM54C907/MM74C907 consists of six
inverters driving six P-channel devices. The open drain
feature of these buffers makes level shifting or wire
AND and wire OR functions by just the addition of
pull-up or pull-down resistors. All inputs are protected
from static discharge by diode clamps to Vee and to
ground.

•

Wide supply voltage range

•

Guaranteed noise margin

3.0V to 15V
1.0V
0.45 Vee typ

•

High noise immunity

•

High current sourcing and sinking open drain outputs

connection diagram

Vee

GND

logic diagrams
Vee

~OUTPUT

..," ---t>o-1

""'~9

.

MM54C906/MM74C906

d
LOUTPUT

MM54C907/MM74C907

1·106

absolute maximum ratings
Voltage at Any Input Pin
Voltage at Any Output Pin
MM54C906/MM74C906
MM54C907/M M7 4C907
Operating Temperature Range
MMS4C906/MM54C907
MM74C906/MM74C907
Storage Temperature Range
Package Dissipation
Operating Vec Range
Absolute Maximum Vee
Lead Temperature (Soldering, '10 seconds)

(Note, 1)

-{).3V to V cc + O.3V
-{).3V to+18V
Vee - 18V to Vee + 0.3V
-5SoC to +12SoC
-40°C to +85°C
--6SoC to +150°C
SOOmW
3.0V to lSV

1IN
300°C

dc electrical characteristics
PARAMETER

Min/max limits apply across temperature range, unless otherwise noted.
CONDITIONS

MIN

TYP

MAX

UNITS

CMOS TO CMOS
Logical "1" Input Voltage (V INO ))

Vec = 5.0V
Vee = 10V

Logical "0" Input Voltage (V INIO ))

Vee = S.OV
Vee = 10V

Logical "1" Input Current (1INIl))

Vee =15V, V IN = lSV

Logical "0" Input Current (1INlo))

Vee = lSV, V IN = OV

Supply Current (Ieel

Ve~ = 15V, Output Open

V
V

3.5
B.O

V
V

l.S
2.0
O.OOS
-1.0

1.0

J.lA

-{).OOS

J.lA

O.OS

lS

J.lA

Output Leakage
MM54C906

Vee = 4.SV,
Vee = 4.SV,

V IN = V ee -1.S
V OUT = 18V

O.OOS

5

J.lA

MM74C906

Vee = 4.75V, V IN = V ee -1.S
Vee = 4.7SV, V OUT = 18V

O.OOS

S

J.lA

MMS4C907

Vee = 4.SV,
Vee = 4.SV,

O.OOS

S

J.lA

O.OOS

S

MM74C907

V IN = 1.OV + 0.1 Vee
V OUT = V ee -18V
Vee =4.7SV, V IN '= 1.0V+0.l Vee
Vee = 4.7SV, V OUT = V ee -18V

J.lA
\

CMOS/LPTTL INTERFACE
Logical "1" Input Voltage (V INI 1))

S4C, Vee = 4.SV
74C, Vee = 4.7SV

Logical "0" Input VoJtage (VIN(O))

S4C, Vee = 4.SV
74C, Vee = 4.7SV

V ee -1.S
V ee -1.S

V
V
O.B
O.B

V
V

OUTPUT DRIVE CURRENT
MMS4C906

MM74C906

MMS4C907

MM74C907

MMS4C906/MM74C906

MMS4C907/MM74C907

V IN = 1.OV + 0.1 Vee
V OUT = O.SV
V OUT = 1.0V

2.1
4.2

B
12

rnA
rnA

Vee = ft.7SV, V IN = 1.OV + 0.1 Vee
Vee = 4.7SV, V OUT = O.SV
Vee = 4.7SV, V OUT = l'.OV

2.1
4.2

8
12

rnA
rnA

V IN = V ee -1.S
V OUT = Vee-{)·SV
V OUT = V ee -1.0V

-l.OS
-2.1

-1.S
-3.0

rnA
rnA

Vee = 4.7SV, V IN = Vee-l.S
Vee = 4.7SV, V OUT = Vee-{)·SV
Vee = 4.7SV, V OUT = V ee -1.0V

-LOS
-2.1

-l.S
-3.0

rnA
rnA

V IN = 2.0V
V OUT =O.SV
V OUT = 1.0V

4.2
8.4

-20
-30

rnA
rnA

V IN = S.OV
V OUT = 9.SV
V OUT = 9.0V

-2.1

-4.2

-4.0
-S.O

rnA
rnA

Vee = 4.SV,
Vee = 4.SV,
Vee = 4.~V,

Vee = 4.SV,
Vee = 4.SV,
Vee = 4.SV,

Vee
Vee
Vee
Vee
Vee
Vee

= 10V,
= 10V,
= 10V,
= 10V,
= 10V,
= 10V,

1-107

ac electrica-l characteristics
PARAMETER

T A= 25°C, CL

=

50 pF, unless otherwise specified.
MIN

CONDITIONS

TYP

MAX

UNITS

,

Propagation Delay to a Logical "0"
(tpdo)
MM54C906/MM74C906

Vee
Vee

MM54C907/MM74C907

Vee
Vee

= 5V,
= 10V,
= 5V.
= 10V.

R = 10k
R = 10k
(Note 4)
(Note 4)

150
75

ns
ns

150 + 0.7 RC
75 + 0.7 RC

ns
ns

= 5V.
= 10V
= 5V.
= 10V.

(Note 4)
(Note 4)

150 + 0.7 RC
75 + 0.7 RC

ns
ns -

R = 10k
R = 10k

150
75

Propagation Delay to a Logical "1"
(tpd1 )MM54C906/MM74C906

Vee
Vee

Mrvi54C907/MM74C907

Vee
Vee

ns
ns

Input Capacity (C IN )

(Note 2)

5

pF

Output Capacity (C OUT )

(Note 2)

20

pF

Power Dissipation Capacity (C pd )

(Note 3) Per Buffer

30

pF

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Capacitance is guranteed by periodic testing.
Note 3: CPD determines the no load ac power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics
application note. AN-90. (Assumes outputs are open.)
Note 4: "C" used in calculating propagation includes output load capacity (CLl plus device output capacity (COUT).
Temp~rature

typical applications
Wire OR Gate

Wire AND Gate

vee
vee

f· A+B

Note: Can bl Ixtended to more than 2 inputs.

Note: Can be extended to more than 2 inpuu.

CMOS or TTL to CMOS at a Higher VCC

CMOS or TTL to PMOS Interface

Vee + Voo $ tBV
Vee $ t5V

1-108

MM74C908/MM74C918 dual CMOS 30 volt driver

general description
The MM74C908 and' MM74C918 are general purpose
dual high voltage drivers, each capable of sourcing a
minimum of 250 mA at VOUT = Vee - 3V, and
Tj = +65°C.

CMOS drivers are useful in interfacing normal CMOS
voltage levels to driving relays, regulators, lamps, etc.

features

The MM74C90S and MM74C91S consist of two CMOS
NAND gates driving an emitter follower darlington
output to achieve high current drive and high voltage
capabilities. In the "OFF" state the outputs can with·
stand a maximum of -30V across the device. These

•
•
•
•

a Wide supply voltage range

High
Low
High
High

noise immunity
output "ON" resistance
voltage
current

connection diagrams
MM74C908
vee

VOUT

B

VOUTA

GND

TOP VIEW

MM74C918

TOP VIEW

1-109

3V to 1SV
0.45 Vee (typ)
sn (typ)
-30V
250mA

absolute maximum ratings

(Note 1)

Voltage at Any Input Pin
Voltage at Any Output Pin
Operating Temperature Range

-o.3V to Vee +0.3V
32V

MM74C908/MM74C918
~40°C to +85°C
Operating Vee Range
3V to 18V
Absolute Maximum Vee
19V
ISOURCE
500 mA
Storage Temperature Range
-65°C to +150°C
Lead Temperature (Soldering, 10 seconds)
300°C
. Package Dissipation
Refer to Maximum Power Dissipation vs
Ambient Temperature Graph

dc electrical characteristics
PARAMETER

Min/max limits apply across temperature range, unless otherwise noted.
CONDITIONS

UNITS

CMOS TO CMOS
Logical "1" Input Voltage (V ,N (1))

Vec'C 5V
Vee = lOV

Logical "0" Input Voltage (V 'NIO ))

Vee
Vee

= 5V
= 10V

Logical "1" Input Current (I'Nll))

Vee

= 15V, Y'N = 15V

V
V

3.5
8
1.5
2
0.005

Logical "0" Input Current (I'Nlo))

Vee

Supply Current (Ieel

Vee

= 15V, Y'N = OV
= 15V, Outputs Open

Output "OFF" Voltage

Y'N

=

Vee

= 4.75V

Vee

= 4.75V

Vee, lOUT

-1
Circuit

1

/lA

15

/lA

30

V

-{l.005
0.05

= -200/lA

V
V

/lA

CMOS/LPTTL INTERFACE
Logical "1" Input Voltage (V ,N
MM74C908/MM74C918

(1))

Logical "0" Input Voltage (V ,N
MM74C908/MM74C918

(0))

V ee -l.5

V
0.8

V

OUTPUT DRIVE
Output Voltage (V OUT )

lOUT = -300 rnA, Vee ~ 5V, T j
lOUT = -250 rnA, Vee ~ 5V, T j
lOUT = -175 rnA, Vee ~ 5V, T j

= 25°C
= 65°C
= .150°C

Output Resistance (RON)

lOUT = -300 rnA, Vee ~ 5V, T j
lOUT = -250 rnA, Vee ~ 5V, T j
lOUT =-175 rnA, Vee ~ 5V, T j

= 25°C
= 65°C
= 150°C

V ee -2.7
V ee -3.0
V ec -3.15

Output Resistance Temperature
Coefficient
Thermal Resistance (8 jA)
MM74C908
MM74C918

(Note 3)
(Note 3)

V ee -1.8
V ee -l.9
V ee -2.0

V
V
V

6
7.5
10

9
12
18

0.55

0.80

%/"C

100
45

110
55

°C/W
°C/W

TYP

MAX

UNITS

150
65

300
120

2
4

10
20

n

n
n

ac electrical characteristics
PARAMETER

CONDITIONS

Propagation Delay to a Logic "1"
(t pd l )

Vee = 5V, RL
Vee = 10V, RL

Propagation Delay to a Logic "0"
(tpdO)

Vee
Vee

Input Capacitance (C ,N )

(Note 2)

= 5V,
= 10V,

RL
RL

= 50n,
= 50n,

CL = 50 pF, TA
CL = 50 pF, TA

MIN

= 25°C
= 25°C

= 50n, C L = 50 pF, T A = 25°C
= 50n, C L = 50 pF, T A = 25"C

5.0

n~

ns
(..IS'

/lS

pF

Note 1: "Absolute Maximum Ratings" are. those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: IIjA measured in free air with device soldered into printed circuit board.

1·110

typical performance characteristics

Maximum Power Dissipation
vs Ambient Temperature

Maximum Vee - VOUT
vs lOUT

Typical lOUT vs Typical VOUT

~

..s

2400

!:i

2200
2000

~
~

......
I

1800

Q 1600

ffi

~

1400
1200

~ 1000
:Ii 800

~

~

~
::i

~

1"""1"""

I
........

J

;;;

I

,,

..s....

MM74C91~t 1-1-1,
(55·CIW)

I

600 1-1400 - I 200
100

I I

I-f-o.l

" ...... ........

1 (I10·CIW)1
MM74C90,8
1

i

f-f-I-

I
r'\.1

<..:>

a:

::>

I'C

0

I

'"
t::>

1

::>

~

II I I I

t-

0

I
::l

I

500

300
275
250
225
200

L

'"

25

50

1.0

1.5

2.0

2.5

3.0

TYPICAL V OUT (V)

MAXIMUM Vee - VOUT (V)

Typical lOUT vs Typical VOUT

0

~

~

;;;

350

..s

1/

300
250

::l

/

200
150

I
II

100
50

j

500

/

400

::l

.I

550

450

Vee = 5V
TI = 65·C

/

400

V

350

0

300
250

t-

/

450

~

~

-

200

/

150
50

~

V

L

V
Vee = 5V
Tj = 150·CI-

/

100

1

0

5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0

5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0
TYPICAL VOUT (V)

TYPICAL VOUT (V)

ac test circuit

switch ing time waveforms

Vee

r---

Vee-----t-+--------.i

I

INPUT~
I

-

5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0

3.5

Typical lOUT vs Typical VOUT

..s....

Vee =5V
Tj = 25·C

150

I

500

;;;

1/

250
200

100

0

TA - AMBIENT TEMPERATURE (·C)

I

300

~
;;:
....>

Tj "65·C- I---

I

350

..s
j

/

150
125
100
75
50

400

;;;

/'

175

0 10 20 30 40 50 60 70 80 90100 110 120

I

450

INPUT
MM74C908
OR MM74C918

0.5 Vee

0.5 Vee

OV----J.

I
IL ____'-..J~"'---"'- OUTPUT
Cl
50 pF

OUTPUT
OV-------~-------'

I,

1-111

=If =20 ns

power considerations
Calculating Output "ON" Resistance (RL

(6b)

> 18m

Tj =

The output "ON" resistance, RON, is a function of the
junction temperature, T j , and is given by:
RON

=9

(T j - 25) (0.008) + 9

(1 )

TA + 7.28 jA [lOA 2 (Duty Cycle A ) +los2 (Duty Cycles))

---~---:=--------.:..:...,:-------

1 - 0.072 8jA [loA 2 (Duty CycleA) + los2 (Duty Cycles))

Equations (11. (41. and (6b) can be used in an iterative
method to determine the output current, output resistance and junction temperature.
Vee

and T j is give~ by:
Tj

=T A + POAV

9jA ,

where TA = ambient temperature, 9jA =, thermal resistance, and POAV is the average power dissipated within
the device. POAV consists of normal CMOS power
terms (due to leakage currents, internal capacitance,
switching, etc.) which are insignificant when compared
to the power dissipated in the outputs. Thus, the output
power term defines the allowable limits of operation and
includes both outputs, A and B_ Po is given by:
2

Po ::: lOA

RON + lOB

;----1---- 1

!)- ~"..

(2)

2

RON,

(3)

OUTPUT A -

~!

L. I- - --:...---

.J

~OUTPUT B

For example,let Vee = 15V, RLA = lOOn, RLB = loon,
V L = OV, T A = 25°C, 9jA = 110°CIW, Duty CycleA =
50%, Duty Cycles ::: 75%.
Assuming RON"' lln, then:

where 10 is the output current, given by:
15
11 + 100

(4)

V L is the load voltage.
lOB

135.1 mA,

135.1 mA

The average power dissipation, POA v' is a function of
the duty cycle:
and

P OAV

"=

lOA 2 RON (Duty CycleA) +

(5)

Tj =

TA +7.2 OjA [I OA 2 (DutyCycleA)+los 2 (Duty Cycles))

~----=----:...-...,:--------=------=~

1 -0.072 OjA [loA 2 (Duty CycleA) + los2 (Duty Cycles)]

lOB 2 RON (Duty CycleB)
where the duty cycle is the % tim'e in the current source
state. Substituting equations (1) and (5) into (2) yields:
(6a)
T j = T A + 9 jA [9 (T j - 25) (0.008) + 9]
[lOA 2 (Duty CycleA) + IOB2 (Du~y Cycles)]

25 + (7.2) (110) [(0.1351)2 (0.5) + (0,1351)2 (0.75))
j
T = 1- (0.072) (110) [(0.1351)2 (0.5) + (0.1351)2 (0.75))

and RON::: 9 (T j - 25) (0.008) + 9:::
9 (52.6 - 25) (0.008) + 9 ::: 11 n

simpl ifying:

applications
(See AN-177 for applications.)

1-112

MM54C909/MM74C909 quad comparator
general description

features

The MM54C909/MM74C909 contains four independent
voltage comparators designed to operate from standard
54C/74C power ~upplies. The output allows current
sinking only thus the wire OR function is possible using
a common resistor pull up.

• Wide supply voltage range
• TTL compatibility
•

3.0V to 15V

fan out of 1
driving 74
Icc = 800pA typ
at Vee = 5.0 Voe
250 nA max
±50 nA max
±5.0 mV max
OV to V ee -1.5V

Low power consumption

• Low input bias current
• Low input offset current
• Low input offset voltage
• Large common mode
input voltage range
• Large differential input
voltage range

Not only does the MM54C909/MM74C909 function as
a comparator for analog inputs but also has many appli·
cations as a voltage translator and buffer when interfacing
the 54C/74C family to other logic systems.

Vce

connection diagram

OUTPUT l

OUTPUT 4

OUTPUT 2 OUTPUT 1

GND

v'

INPUT 4+

INPUT 4-

INPUT 3+

INPUT 3-

INPUT 1-

INPUT l'

INPUT 2-

INPUT 2'

TOP VIEW

typical applications (v+ = 5.0 Voe )

v'

+s.ovoc

S.lk
lOOk

CMOS/TTL to MOS Logic Converter

Ground Referenced Thermocouple
in Single Supply System

1·113

absolute maximum ratings
Voltage at Any Pin
Operating Temperature Range
MM54C909
MM74C909
Storage Temperature Range
Package Dissipation (Notes 2 and 3)
Operati ng Vee Range
Absolute Maximum Vee
Input Current (V IN < -o.3V) (Note 4)
Lead Temperature (Soldering, 10 seconds)

(Note 1)
-o.3V to Vee + O.3V
-55°C to+125°C
-40°C to +85°C
-65°C to +150°C
500mW
3.0V to 15V
18V
50mA
300°C

dc electrical characteristics
Min/max limits apply across temperature range, unless otherwise noted. (Vee
PARAMETER

CONDITIONS

= +5.0 V DC)
MIN

TYP

Input Offset Voltage (Note 9)
T A = 25°C
Input Bias Current
(IIN(+) or IINH) (Note 5)

T A = 25°C, With Output in
Linear Range

Input Offset Current
(IIN(+) -IINH)

T A = 25°C

Input Common Mode Voltage
(Note 6)

T A ='25°C

±2
25
I

±5

/

MAX
±9
±5

mV
mV

250
400

nA
nA

±150
±50

nA
nA

Vcc -2
Vcc -1.5

0
0

UNITS

2000

V
V

Supply Current (Icel

TA=25°C.R L =00
On All Outputs

800

Voltage Gain

TA=25°C.RL~15kn

200

V/mV

3.2

mA

IJA

OUTPUT DRIVE (See 54C/74G Family Characteristics Data Sheet)
Output Sink Current (I SIN K)
MM54C909
MM74C909

Vcc = 4.50V
Vcc = 4.75V. VOUT = O.4V

1.6

VINH ~ 1.0 Voc
V IN (+) =OVoc
Output Leakage Current

V IN (+) ~ 1.0 Voc. VINH = 0 Voc.
VOUT = 15 Voc
V IN (+) ~ 1.0 Voc. V INH = 0 Voc.
VOUT = 5 Voc. TA = 25°C

Differential Input Voltage (Note 8)

All VIN's ~ 0 Voc

1
0.1

IJA
nA

15

V

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: For operating at high temperatures. the MM74C909 must be derated based on +125°C maximum junction temperature and a thermal
resistance of +175°C/W which applies to the device soldered in a printed circuit board, operating in a still air ambient. The MM54C909 must be
derated based on a +150°C maximum junction temperature. The low bias dissipation and the ON·OFF characteristic of the outputs keeps the chip
dissipation very small (Pd < 100 mW), provided the output sink current is within specified limits.
Note 3: Short circuits fro; the output to V+ can cause excessive heating and eventual destruction. The maximum output current is approximately
20 mA independent of the magnitude of V+.
.
Note 4: This input current will only exist when the voltage at any of the input leads is driven negative. There is a lateral NPN parasitic transistor
action on the IC chip. The transistor action can cause the output voltages of the comparators to go to the vi-. voltage level (or to ground for a large
overdrive) for the time duration that an input is driven negative. This is not destructive and normal output states will reestablish when the input
voltage, which was negative. again returns to a value greater than -o.3V.
Note 5: The direction of the input current is out of the IC. This current is essentially constant, independent of the state of the output so no loading
change exists on the reference or input lines.
Note 6: The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3V. The upper end of
the common·mode voltage range is V+ - 1.5V, but either or both inputs can go to +15V without damage.
Note 7: The response time specified is for a 100 mV input step with 5.0 mV overdrive. For larger overdrive signals 300 ns can be obtained. see
typical performance characteristics section.
Note 8: The positive excursions of the input can equal VCC supply voltage level, and if the other input voltage remains within the common-mode
voltage range, the comparator will provide a proper output state. The low input voltage state must not be less than -o.3V.
Note 9: At output switch pa'int, Vo :-·1.4 Voe, RS = on with V+ from 5 VOC to 30 VOC and over the full input common mode range (OVOC)
to V+ ±1.5 VOC).
.

ac electrical cha racteristics

RL = 5.1 kD, V RL = 5.0 V DC, unless otherwise specifie.d.
CONDITIONS

PARAMETER
V 1N

Large Signal Response Time

;

TYP

MIN

TTL Swing

MAX

UNITS

300

ns

1.3

ps

VAEF;l.4VDc
Response Time

TA

= 25°C

typical performance characteristics
Response Time for Various
Input Overdrives - Negative
Transition

Response Time for Various
Input Overdrives - Positive
Transition

~~2:.

0>

>-

.....

6.0

~

~.... -

.....

0

0

~>

~>

5.0
4.0
3.0
2.0

,I

I

20mvj-

4

5.0 mV = INPUT OVERDRIVE

1/.1111-

H~

....

-

,. ~~":. . =_
~-'

100mV

1.0
~.

;:: >
;;.§

~ ~

~>

100 1--1--f----11--1f----+
50

0 '---'-----'-----'----.l..-.l..-.l..--'-----'----"------J
0.5

0.5

1.5
TIME (MseC)

1.0

1.5

2.0

TIME (MseC)

application hints
The MM54C909/MM74C909 is a high gain, wide band·
width device; which, like most comparators, can easily
asci Ilate if the output lead is inadvertently allowed to
capacitively couple to the inputs via stray capacitance.
This shows up only during the output voltage transition
intervals as the comparator changes states. Power supply
bypassing is not required to solve this problem. Standard
PC board layout is helpful as it reduces stray input·
output coupling. Reducing the input resistors to < 10 kD
reduces ,the feedback signal levels and finally, adding
even a small amount (1 to 10 mY) of positive feedback
(hysteresis) causes such a rapid transition that oscilla·
tions due to stray feedback are not possible. Simply
socketing the I/C and attaching resistors to the pins will
cause input·output oscillations during the small transi·
tion intervals unless hysteresis is used. If the input
signal is a pulse waveform, with relatively fast rise and
fall times, hysteresis is not required.

It is usually unnecessary to use a bypass capacitor across
the power supply line.
The differential input voltage may be larger than' V+
without damaging the device. Protection should be pro·
vided to prevent the input voltages from going negative
more than -0.3 V DC (at 25°C). An input clamp diode
and input resistor can be used as shown in the applica'
tions section.
Many outputs can be tied together to provide an output
OR'ing function. An output "pull·up" resistor can be
connected to any available power supply voltage within
the permitted supply voltage range and there is no
restriction on this voltage due to the magnitude of the
voltage which is applied to the V+. terminal of the
MM54C909/MM74C909 package. The output can also
be used as a simple SPST switch to ground (when a
"pull·up" resistor is not used). The amount of current
which the output device can sink is limited by the drive
available (which is independent of V+) and the gain of
the output device. When the maximum current limit
is reached (approximately 16 mAL the output transistor
will come out of saturation and the output voltage will
rise very rapidly.

All pins of any unused comparators should be grounded.
The bias network of the MM54C909/MM74C909 estab·
lishes an Icc current which is independent of the
magnitude of the power supply voltage over the range of
from 3.0V to 15V.

typical applications. (con't) (v+

=

5.0 VDcl
+5.0 voc

v·

v'

+VRE'o-----I

10k

,

Basic Comparator

Driving CMOS

1·115

Non·1 nverting Comparator with Hysteresis

typical applications (con't) (v+ ~

5.0 Voe)

+5.0 Vric

+5 Voe

100

Driving TTL

r - - -.....- -......-

S.OV

100
+5.0 Voe

Note: For inverting buffer reverse input connection.

5V Logic to CMOS Operating at VCC

"* 5V

+VREF2

100

'V ,N

+5.0 Voc

0------1

3k

> ....--oVo
1M

P

1M

1M
+VREF 1

100

Inverting Comparator with Hysteresis
Visible Voltage Indicator
R2
lOOk

Rl
lOOk

lN914
TRIP POINT = -vee Rl
R2

Note: For non·inverting buffer reverse input connection.

Hi Voltage Inverting PMOS to CMOS or TTL

1-116

3V--4....+-0 OUTPUT 1

T

OUTPUT 2

SOk
V'/2

V-· -30 Voc
-250 mVoc < Ve < -50 Voe
700 Hz < fa < 100 kHz

Two·Decade High·Frequency VCO

V'

Rl
1M

01
lN914

R2
lOOk

02
lN914

1Sk
VIS Voe )

5.1k

-r

10k

4.Jk

80pF

6"~~'
'tot,

500

t2

lN914

Va

200

1M
-15 Voc

':'

o-.JVVv-tH
1M

':'

':'

1M
1M

*For large ratios of Rl/R2,
01 tan be omitted.

Pulse Generator

Remote Temperature Sensing

1-117

MM54C910/MM74C910256-bit TRI-STATE®
random access read/write memory
general description
Read Operation: Data is nondestructively read from a
memory location by an address operation with write
enable held high.

The MM54C910/MM74C910 is a 64 word by 4 bit
random access memory. Inputs consist of six address
lines, four data input lines, a write enable, and a
memory enable line. The six address lines are internally
decoded to select one of 64 word locations. An internal
address register, latches the address information on the
positive to negative transition of memory enable. The
TRI-STATE outputs allow for easy memory expansion.

Outputs are in the TRI-STATE (Hi-Z) condition when
the device is writing or disabled.

features

Address Operation: Address inputs must be stable (tSA)
prior to the positive to negative transition of memory
enable, and (tHA) after the positive to negative transition
of memory enable. The address register holds the
information and stable ad~ress inputs are not needed at
any other time.
Write Operation: Data is written into memory at the
selected address if write enable goes'low while memory
enable is low. Write enable must be held low for tiNE
and data must remain stable tHO after write' enable
returns high.

•
•
•
•
•

Supply voltage range
High noise immunity
TTL compatible fan out
Input address r~gister
Low power consumption

•
•
•

Fast access time
TRI-STATE outputs
High voltage inputs

3V to S.5V
0.45 Vee typ
1 TTL load
250 nW/package typ
(chip enabled or disabled)
250 ns typ at 5V

logic and connection diagrams
D INI

D DUT1 D IN2

D DUTZ D INl

D DUll D IN4

D DUT4

Input Protection
Vee

Dual-I n-line Package
IVI!lTE'MEMlfif'I'
Yeo

0 DUll

olNl

olN4 0 oUT4 n n u rom

AC

10

ooUl2

ooUTI

o.
ToPYIEW

1·118

GNo

absolute maximum ratings

s:
s:

operating conditions

(Note 1)

U'1
~

.(")
Voltage At Any Output Pin
-o.3V to VCC +0.3V
-o.3V to +15V
Voltage At Any Input Pin
Package Dissipation
500 mW
Operating Vee Range
3.0V to 5.5V
Standby Vee Range
1.5V to 5.5V
Absolute Maximum Vee
6.0V •
Lead Temperature (Soldering, 10 seconds)
300°C

Supply Voltage (VCC)
MM54C910
MM74C910
Temperature (T A)
MM54C910
MM74C910

MIN

MAX

UNITS

4.5
4.75

5.5
5.25

V
V

+125
+85

°c
°c

--55
-40

CD
-'

0

"-

s:
s:"-oJ
~

(")

CD

-'

0

dc electrical characteristics

MM54C91 0/MM74C91 0

(Min/max limits apply across the temperature and power supply range indicated).
PARAMETER
V IN (!)

Logical "1" Input Voltage

Full Range

VIN(O)

Logical

"a" Input Voltage

Full Range

IIN(11

Logical "1" Input Current

IIN(O)

Logical

V OUT (1)

Logical "1" Output Voltage

Logical

VOUT(O)

Icc

MIN

CONDITIONS

VIN

= 15V
= 5V

VIN

= OV

VIN

"a" Input Current

"a" Output Voltage

10
10

= 1.6mA

Output Current in High

Vo

Impedence State

Vo

Supply Current

Vee

ac electrical characteristics
T A = 25°C. Vee = 5V. C L = 50 pF

MAX

UNITS

V ee -1.5

V
0.8

-1

= -150pA
= -400pA

10

TYP

V

0.005

2

pA

0.005

1

pA

-0.005

pA

V ee -0.5

V

2.4

V
V

0.4

= 5V
= OV

0.005
-1

1

pA

300

pA

-0.005

= 5V

0.05

pA

MM54C910/MM74C910

PARAMETER

MIN

TYP

MAX

UNITS

250

500

ns

180

360

tAee

Access Time from Address

tpo

Propagation Delay from

tSA

Address Input Set·Up Time

140

70

ns

tHA

Address I nput Hold Time

20

10

ns

ME

ns

tME

Memory Enable Pulse Width

200

100

ns

tME

Memory Enable Pulse Width

400

200

ns

tso

Data Input Set·Up Time

a

tHO

Data Input Hold Time

30

15

LwE

Write Enable Pulse Width

140

70

t'H. tOH

Delay to TRI·STATE (Note 4)

ns

100

ns
ns
200

ns

CAPACITANCE
CIN

Input Capacity

COUT

Output Capacity

Cpo

Power Dissipation Capacity (Note 3)

Any Input (Note 2)

Any Output (Note 2)

1-119

5

pF

9

pF

350

pF

....

0

m
(.)
~

.....

ac electrical characteristics (con't)
c L = 50 pF

::!
::!
........

MM54C910
T A = -55°C to +125°C
Vee =4.5V to 5.5V

PARAMETER

....
m

0

(.)
~

Ln

::!
::!

MAX

MIN
tAcc

Access Time from Address

tpOl, tpoo

Propagation Delay from

"

ME

MM74C910
T A =-4Q.°C to +85°C
Vee = 4.75V to 5.25V
MIN

UNITS

MAX

860

'700

660

540

ns
ns

tSA

Address Input Set·Up Time

200

tHA

Address Input Hold Time

20

20

ns

tME

Memory Enable Pulse Width

280

260

ns

tME

Memory Enable Pulse Width

750

600

ns

tso

Data Input Set·Up Time

0

0

ns

tHO

Data Input Hold Time

50

50

ns

Write Enable Pulse Width

200

180

,tw£:

Delay to TRI·STATE (Note 4)

t ,H , tOH

160

ns

ns
200

200

ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at" these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Capacitance is" guaranteed by periodic testing.
Note 3: Cpd determines the no load ac power consumption for any CMOS device. For complete explanation see 54C/74C Family Characteristics
application note, AN·90.
Note 4: See ac test circuit for t1 H, tOH.

typical performance characteristics

truth table

Typical Access Time vs Ambient
Temperatura
450
4CC f - - 1-350

]

...:Ii

300

~

200

;::
"<

I-~t-

f--

-p~

....

~~

4,5~ ~

..... ~

250

~ ....

6~ ~

r,,1E

\"JE

L
L
H

.... .... ~~

.... ,. .... '5,5V
~

ISO

"""

100

HH-+-I-+-+-HH4-1--l

H

OPERATION

OUTPUTS

L

Write

TRI·STATE

H

Read

Data

L
H'

Inhibit, Store

TRI·STATE

Inhibit, Store

TRI·STATE

50 ~H-+-r~+-HH-+-r-l

o L-,J........--'--L.....I......I-.L...J........--L-L......
-55

-25

5

35

65

95

125

FREE AIR TEMPERATURE ('C)

ac test circuits
All Other AC Tests

t1H

}.,

-

002

v

...l-"c

f

Al

l

T
...l-C

*"

l

i't"
i't"

003

004
001
L---

RL "10k
Cl "'10pF

1·120

-L'
T' ~l'
t" l'

s:
s:
en

time waveforms

~

Write Cycle

n

(See Note 1)

CD

...&

o

Vee

~

"'-

ADDRESS

~
n

.

s:
s:

INPUT

CD

...&

o
Vee
DATA

OUT

ft

__

Modify Write Cycle
Read (See Note 1)

tOH

ME

1'' .

VCC
O

p;~-","

Vec
DATA DUT

-r

o

.,

D.1Vcc

ME
VCOc

~1"
DATA DUT

Vcc

o

d"'€t"

vcc

---TRISTATE

Advance Information

MM74C911 display controller
MM74C912 display controller
MM74C913 display controller
general information

features

The display controller serves as an interface element
between the bare machine and the controlled display.
The display controller normally receives input data
and digit address information and then controls a sevensegment display, providing direct segme,nt drive and
internal multiplexing of all digits. The display controller
provides a random access to the master portion of an
internal register selected by an address operation.
Normally an internal oscillator will sequentially address
the slave portion of the internal registers; however, it is
also possible for the user to randomly address the slave
portion of the internal registers via the digit lines by use
of the digit liD control pin. The display controller will
be capable of both segment and digit expansion, extending its use to alphanumeric 16-segment displays or 12digit calculator stick displays.

•

Direct segment drive (40 mA min) Tri-Statable

•

Random access to master portion of internal register
by address lines (internally decoded)

• Sequential access to slave portion of internal registers
by an internal oscillator
•

Random access to slave portion of internal registers
by digit lines and digit liD control pin

•

Addressed like a 2102

• Sufficient digit dead time to multiplex gas discharge
displays (varies with model)

applications
•

Electronic pinball machine

•

Microprocessor display buffer

• Clock system for large institution
• Airport arrival and departure display system

models

• Silent hospital paging system

•

6-digit version: 7x 16 ROM controlled by 4 data bits

•

Personalized message receiver

2-digit version: 8-segment outputs controlled by 8
data inputs

•

Microprocessor latch element with ROM

•

Microprocessor latch element

•

circuit description
The display controller will be a CMOS circuit constructed on the buffed guard band process, limiting it to fivevolt operation. The segment outputs will have an NPN
source transistor and an N-channel sink transistor. The
segment outputs can be tri-stated by use of the output
enable (DE) pin. The digit liD port is controlled by the
digit I/O pin (DID). Used as an output the digit lines
are sequentially strobed by the internal oscillator and
the data multiplex to the segment outputs. Used as an
. input only one digit line at a time can be high. Data
. information from the selected digit appears at the
segment output. The internal oscillator is inhibited. The'
register being addressed by the input address and input
data is completely independent of the register being
addressed by the digit input and segment- output information. The digit output drive will be a standard B series
specification.
Three versions of the Display Controller will exist. The
MM74C911 will multiplex four digits' with 8 bits of
input information and comes in a 28-pin package. The
MM74C912 will multiplex six' digits with ROM information with the ROM addressed by 4 data bits. The

decimal point input does not address the ROM and goes
directly to the output. The MM74C912 is capable of
digit expansion. The MM74C911 is capable of both digit
and segment expansion. A third version, the MM74C913,
will be identical to the MM74C912 except that the
decimal point input and output and the digit and segment tri-state controls will be omitted. The MM74C912
will be housed in a 24-pin package and is intended for
the electronic pinball market .
Two input protection diodes will be present at all inputs .
The diode to Vee may be. omitted via a simple metal
option.
Data is written into the internal registers by first bringing chip enable (CE) low. Address information is not
latched by CE, so address information can change
before or after CE is low. Address information must be
stable tSA nanoseconds before write enable goes low.
Data is written into the addressed register when both
- CE and WE are low. Data should be stable tSD nanoseconds before the rising edge of WE. Chip enable and
WE may simultaneously return high.

1-122

3:
3:
-...J

electrical characteristics
'CONDITIONS

PARAMETER
Vee

MIN

TYP

4.5

Supply Voltage

5.5

3.0

Standby Voltage

5.5

Vee - 2.0

V IN (1)

0.8

VIN(O)
los

MAX

V ee '= 5V, Va = 3.4 V, T) = 150°C

Segment Output Current

Vee = 5 V, Va = 1.75 V, T j = 150°C

IsouReE Digit
/

ISINK

40

80

-2

-1

UNITS
V
V
V

3:
3:

V
mA
mA

tSA

200

ns

tso

Data Setup Time

400

ns

twe

Write Cycle (ts A + tso

600

ns

too

Digit On Time

400

ps

tID

Interdigit Blanking

50

ps

waveforms
STABLE ADDRESS
\ /
STABLE ADDRESS
\ V
____\V_ _ _
_ _ __JJ\
___
_ _ __JJI\
___
J~

~--------~C--------~·~I

CE----+_

If

J
i-1SA-

~r

[~

\~

IV
_ _ _ _ _ _ _ _J

~t

DATA CAN

\V
J~

_ _CHANGE
_ _ _- J

DATA STABLE

\V
11\

~_ _ _ _ _ _ _ J

/

'J

'~
_ _ _ _ _ _ _ _ _ _ _ _J

I----ISO---------+I

DATA
IN

-...J
~

n

....

CD
N
........

3:

All Outputs = 2 LP TTL

~---------~~

....
....CD

........

Address Setup Time

ADDRESS

~

n

-ISD_

DATA CAN
CHANGE

\ /

1\

DATA STABLE

WAVEFORMS MM74C911/MM74C912/MM74C913

1·123

\

I

J\

DATA CAN
CHANGE

s:
~

n
CD

....

W

....Men

block diagram

0

~
,....
:E
:E
........

N
....
en

0

~
,....
:E
:E
........

WE
KI
K2

CE

DE

....
....

en
(.)
~
,....

:E
~

9

9

Op

Op

01
02

~---*----- DID
MM74C911

WE--------------~

ADDRESS
DECODE
'OMIT THESE PINS FOR 24·PIN
PACKAGE (MM74C9131

• OMIT
(9131

......- - - l i E

g

op

J..---t---010
• OMIT
(9131

MM74C912/MM74C913 BLOCK DIAGRAMS

1·124

MM54C914/MM74C914 hex schmitt trigger with extended input voltage

general description

features

The MM54C914/MM74C914 is a monolithic CMOS Hex
Schmitt trigger with special input protection scheme.
This scheme allows the input voltage levels to exceed
Vee or ground by at least 10V (Vee - 25V to GND +
25 V), and is valuable for appl ications involving voltage
level shifting or mismatched power supplies.

•

Hysteresis

•

Special input protection

•

Wide supply voltage range

The positive and negative-going threshold voltages, VT+
and V T -, show low variation with respect to temperature
(typ 0.0005 v;oC at Vee = 10V). And the hysteresis,
VT+ - VT - ~ 0.2 Vee is guaranteed.

•

High noise immunity

•

Low power TTL
compatibility

0.4 Vee typ
0.2 Vee guaranteed

connection diagram
Vee

GNO
TOP VIEW

Special Input Protection
Vee

INPUT

--M,----t-+

BV·35V

1-125

TO GATE

Extended Input
Voltage Range
3.0V to 15V
0.70 Vee typ
fan out of 2
driving 74L

absolute maximum ratings
Voltage at Any Input Pin
Voltage at Any Other Pin
Operating Temperature Range
MM54C914
MM74C914

Vee - 25V to GND + 25V

-65°C to +150°C
Stor.age Temperature Range
500mW
Package Dissipation
3.0V to 15V
Operating Vee Range
18V
Absolute Maximum Vee
300°C
Lead Temperature (Soldering, 10 seconds)

-{).3V to Vee +0.3V
-55°C to +125°C
-40° C to +85° C

dc electrical characteristics

Minimax limits apply across temperature range, unless otherwise noted.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

CMOS TO CMOS
VT+ Positive Going Thres~old
Voltage
V T - Negative Going Threshold
Voltage
Hysteresis (VT+ - V T-)

Vee
Vee
Vee
Vee
Ve~
Vee
Vee
Vee
Vee

= 5V
= 10V
= 15V
= 5V
= 10V
= 15V
= 5V
= 10V
= 15V

3.0.
6.0
9.0
0.7
1.4
2.1
1.0
2.0
3.0

Logical "1" Output Voltage
(V OUT (1))

Vee = 5V, 10 = -10pA
Vee= 10V, 10 = -10pA

Logical "0" Output Voltage
(VOUT(O))

Ve~ = 5V, 10 = +10pA

Logical "1" Input Current
(lIN(1))
Logical
(II,N(O))

"a ..

Input Current

Supply Current (IcC!

3.6
6.8
10.0
1.4
3.2
5.0
2.2
3.6
5.0

Vee
Vee
Vee
Vee

= 15V,
= 5V,
= 10V,
= 15V,

VIN
VIN
VIN
V LN

-100.0

= -10V!25V
= 2.5V (Note 4)
= 5V (Note 4)
= 7.5V (Note 4)

V
V

V
V

V
V

0.005

Vee = 15V, VIN '" 25V

V
V

V

4.5
9.0

Vee' = lOV, 10 = +10pA

Vee = 15V, VIN = -10V

4.3
8.6
12.9
2.0
4.0
6.0
3.6
7.2
10.8

0.5
1.0

V
V

5.0

pA
pA

-0.005
0.05
20
200
600

300

pA
pA
pA
pA

CMOS/LPTTL INTERFACE
Logical "1" Input Voltage
(V IN (1))

Vee = 5V

Logical "0" Input Voltage
(VIN(O))

Vee = 5V

Logical "1" Output Voltage
(V OUT (1))

54C, Vee = 4.5V, 10 = -360pA
74C, Vee = 4.75V, 10 = -360pA

Logical "0" Output Voltage
(VOUT(O))

54C, Vee = 4.5V, 10 = 360pA
74C, Vee = 4.75V, 10 = 360pA

4.3

V

0.7
2.4
2.4

V

V
V

0.4
0.4

V
V

OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet)
Output Source Current
(lsouReE) (P·Channel),

Vee = 5V, V OUT = OV, T A = 25°C

-1.75

-3.3

mA

Output Source Current
(lsouReE) (P·Channel)

Vee = 10V, V OUT = OV, T A = 25°C

-8.0

-15

mA

Output Sink Current (I SINK )
(N·Channel)

Vee = 5V, V OUT = Vee,
TA = 25°C

1.75

3.6

mA

Output Sink Current (lSINK)
(N·Channel)

Vee = 10V, V OUT
TA = 25°C

8.0

16

mA

= Vee,
1·126

ac electrical characteristics

T A = 25°C, C L

PARAMETER

= 50 pF, unless otherwise specified.
MIN

CONDITIONS

TYP

MAX
400
200

UNITS
ns
ns

Propagation Delay from Input
to Output (t pd 0 or tpd 1 )

Vee = 5V
Vee = 10

220
80

Input Capacitance

Any Input (Note 2)

5.0

!-IF

Power Dissipation Capacitance
(Cpo)

(Note 3) Per Gate

20

pF

-

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: CpO determines the no load ac power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics
application note. AN·90.
Note 4: Only one input is at 1/2 VCC. the others are either at VCC or GNO.

typical application

GNO 1
Note: VCC1 > VCC2
GNO 1 < GNO 2

GNO 2

typical performance characteristics

Typical Transfer Characteristics

Guaranteed Trip Point Range

20
~

Vee = 15V
15

~

~

>

15

Vr_

Vr •

~

vee

MM54C14 -55'C TO +125'C
MM74C14 -40'C TO +85'C
·MINIMUM HYSTERESIS
SPREAO (= 0.2 Veel

Vr •
INPUT
VOL TAGE
Vr

10

'"to

~

10

I-

::>

>

I-

l-

::>

:::I
0

."

15
10
INPUT VO LTAG E (V)

20

OV

5
4.3

Vee

3.0

2.0
0.7
0

10
Vee (V)

15

OUTPUT
VOL TAGE

ov

1·127

MM54C915/M M74C915 7-segment-to- BC D converter
general description
The MM54C915/MM74C915 is a monolithic complementary MOS (CMOS) integrated circuit, constructed
with Nand P-channel enhancement-mode transistors_
This circuit accepts 7-segment information and converts
it into BCD information. The true state of the Segment
inputs can be selected by use of the Invert/Non-invert
control pin. A logical "0" on the Invert/Non-invert
control pin selects active high true decoding at the
Segment inputs. A logical "1" on the Invert/Non-invert
control pin selects active low true decoding at the
Segment inputs. In addition to 4 TTL compatible BCD
outputs, an Error output and Minus output are available. The Error output goes to an active "1" whenever a
non-standard 7 -segment code appears at the Segment
inputs. The BCD outputs are forced into a TR I-STATE®
condition when an error is detected.· This allqws the
user to program his own error code by tying the BCD
outputs to VCC or Ground via high value resistors
(- 500k). The BCD outputs may also be forced into
TRI-STATE by a logical "1" on output enable (OE).

The Minus output goes to a logical "1" whenever a
minus code is detected arid is useful as a microprocessor
interrupt. The BCD outputs are in a flow-though
condition when Latch Enable (LE) is at a logical "0",
and latched when LE is at a logical "1 ". The inputs will
not clamp signals to the positive supply, allowing simple
level translation from MOS to TTL.

features
•
•
•
•
.•
•
•
•

Wide supply range
High noise immunity
TTL compatible fan out
-Selectable active true inputs
TRI-STATE outputs
On-chip latch
Error output
Minus output

logic and connection diagrams
~---~ .......' - - - " MINUS

SEGMENT
INPUTS
C2 Z

02 3

.-H.----1 ----'--'---" ERROR

t----o=
SEGMENT INPUTS
INVERT MINUS
• \ CONTROL OUT

Vce

17

118

16

15

14

13

02 4

LE

12

...--

1

C 22

11

10

~

2

3

4

'--_ _ _---g~,
SEGMENT INPUTS

5

E~~~R
TOP VIEW

1-128

6

li1

7

8

A 20

82 1

P

GNO

3V-15V
0.45 VCC typ

1 TTL load

absolute maximum ratings
0

Storage Temperature Range
-65°C to +150 e
Package Dissipation
500mW
Operating VCC Range
3V to 15V
18V
Maximum Vce
0
Lead Temperature, (Soldering, 10 se~onds)
300 e

Voltage at Any Output
Vcc - 0.3V to Vce + 0.3V
Voltage at Any Input
Vcc - 0.3V to 18V
Operating Temperature Range
-55°e to +125°C
MM54C915
-40° C to +85° C
MM74C915

dc electrical characteristics

CONDITIONS

MIN

TYP

MAX

UNITS

CMOS TO CMOS
VIN(1)

VIN(O)

Logical "1" Input Voltage

Logical "0" Input Yoltage

VCC = 5V

3.3

4.5

V

VCC = 10V

8

9

V

VCC= 15V

12.5

13.5
0.5

1.5

V

VCC = 10V

1

2

V

VCC = 15V

1.5

2.5

V

0.005

1

Logical "1" Input Current

VIN = 15V

Logical "0" I nput Current

VIN = OV

VOUT(l)

Logical "1" Output Voltage

10 = 10llA

Logical "0" Output Voltage

-1

-0.005

IlA
IlA

VCC = 5V

4.5

V

VCC = 10V

9

V

VCC = 15V

13.5

V

VCC = 5V

0.5

V

VCC = 10V

1

V

10 = 10JJA

VCC
Supply Current

V

VCC = 5V

IIN(O)

ICC

= 15V

V

1.5
0.25

VCC = 5V

0.75

rnA

= 10V

0.75

1.75

rnA

VCC = 15V

1.00

2.25

rnA

VCC

CMO~TTLINTERFACE

VIN(1)

VIN(O)

VOUT(1)

VOUT(O)

Logical "1" Input Voltage
MM54C915

VCC = 4.5V

MM74C915

VCC

= 4.75V

MM54C915

VCC

= 4.5V

MM74C915

VCe = 4.75V

VCC- 1.7

V

VCC-1.7

V

Logical "0" Input Voltage

Logical "1" Output Voltage

V

0.8

V

10 = -360JJA

= 4.5V

MM54C915

VCC

MM74C915

VCC = 4.75V

Logical "0" Output Voltage

0.8

2.4

V

2.4

V

10 = 1.6 rnA

MM54C915

VCC = 4.5V

MM74C915

VCC

= 4.75V

0.4

V

0.4

V

OUTPUT DRIVE
ISOURCE

ISINK

....
U1

(D

........

s:
s:
(")

....

(D

U1

IIN(l)

VOUT(O)

U1

~

(")

~

Min/max limits apply across temperature range unless otherwise noted.

PARAMETER

s:
s:

Output Source Current

TA = 25°C, Vo

P·Channel

(Note 2)

Output Sink Current

= OV,

VCC = 5V

-1.75

-3.3

rnA

VCC = 10V

-8

-15

rnA

VCC = 15V

-15

-25

rnA

rnA

T A = 25°C. Vo

= VCC

(Note 2)

N·Channel

5

8

VCC = 10V

20

30

rriA

= 15V

30

50

rnA

VCC

-

VCC

= 5V

1·129

ac electrical characteristics

TA = 25°C
CONDITIONS

PARAMETER
tpdO. tpdl

tOH. tl H

Propagation Delay Time to

eL = 50 pF

Logical "0" or a Logical "1"

Vee = 5V
Vee = 10V
Vee = 15V

UNITS

500

1000

ns

300

600

ns

300

600

ns

R L = 10k. CL = lOp F

Vee = 5V
Vee = lOV

110

200

ns

75

130

ns

Vee = 15V

60

110

ns

Propagation Delay Time From
Logical "0" or Logical "1"

tH

MAX

Logical "0" or Logical "1"

High Impedance State to a

ts

TYP

Propagation Delay Time From
into High Impedance State

tHO. tH1

MIN

Input Data Set·Up Time

• RL= 10k.eL=50pF

Vee =,5V
Vee = 10V

150

250

ns

80

140

ns

Vee = 15V

70

125

ns

eL = 50 pF

Input Data Hold Time

Vee = 5V
Vee = 10V

500

1000

ns

300

600

ns

Vee = 15V

300

600

ns

ns

eL = 50 pF

Vee = 5V
Vee = 10V

-150

0

-100

0

ns

Vee = 15V

-100

0

ns

7.5

pF

elN

Input Capacitance

Any Input. (Note 3)

5

eOUT

TR I·STATE Output eapaci·

Any Output. (Note 3)

10

pF

tance
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
'
Note 2: These specifications apply to transient operation. It is not meant to imply that the device should be operated at these limits in sustained
operation.
Note 3: Capacitance is guaranteed by periodic testing.

truth table

CHARACTER
AT SEGMENT
INPUTS

23

22

21

2°

0

0

0

0

0

0

0
0
0
0
1

0

~

BCD OUTPUTS
D
C
B
A

~

0

2

0

3

0

~~

0

!t'o'

dl

b
b

1

n

0
0
0
0

0
0
0

0

0
1
0
(j

1

1

0
0
0

0
0
0

x

x

x

All other input

X

X

X

X

combinations

X

X

X

X

9
g

0

.1

X = represents TRI·STATE condition

1·130

NON·BCD
OUTPUTS
ERROR
MINUS

0
0
0
0
0
0
0
0
0
0
.0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0

X

0
0

SEGMENT IDENTIFICATION

f~~~b
,~:~,
d

typical applications
Multiplex 7-Segment to Straight BCD

SEG
INPUTS

SEGMENT INFORMATION
LSI PART
W/MUL TlPLEXEO
7·SEGMENT
INFORMATION

OUTP~~~

STRAIGHT BCO

MM54C915

t - - - - -.....

LATCH
ENABLE

n OIGIT LINES

~
DIGIT
SELECT

Memory Expension from 7-Segment Outputs

LSI PART
W/MUL TlPLEXEO
7·SEGMENT
INFORMATION

SEGMENT INFORMATION

SEG
INPUTS
MM54C915
LATCH
ENABLE

~----t~1

START--+
STOP

WE

2"
2nm X 4
RAM

COUNTER

2m
COUNTER

1-131

MINUS

.....-----P ERROR

MM54C920/MM74C920, MM54C921/MM74C921
1024-bit static silicon gate CMOS RAMs
general description
features
The MM54C920/MM74C920 256 x 4 random access
read/write memory is manufactured using silicon gate
CMOS technology. Data output is the same polarity as
data input. Internal latches store address inputs, CES
and data output. This RAM is specifically designed to
operate from standard 54/74 TTL power supplies.
All inputs and outputs are TTL compatible.

•

Fast access-250 ns max

•

TRI-STATE outputs

The MM54C921/MM74C921
is identical to the
MM54C920/MM74C920, except data inputs· are
internally connected to data outputs; the number
of package leads thereby is reduced to 18.

•

low power

•

On·chip registers

•

Single +5V supply

•

D~ta retained with Vee as low as 2V

functional description
The functional description will reference the logic
diagram of the MM54C920/MM74C920 shown in
Figure 1. Input addresses and CES are clocked into
the input latches by the falling edge of STROBE. Input
setup and hold times must be observed on these signals
(see timing diagrams). The true and complement address
information is fed to the row and column decoders
which access the selected 4·bit memory word.

Complete. address decoding as well as two chip select
functions, CEl and CES, and TRI-STATE® outputs
allow easy expansion with a minimum of external components. Versatility plus high speed and low power
make these RAMs ideal elementS for use in micro·
processor, minicomputer as well as main· frame memory
applications.

logic and connection diagrams
AD

32

Al
A2

32

X

x

8

8

32
X

8

AJ
A4

011

------.,1----+1
------.,1----+1
013 ------.,1----+1

DO 1

012

DO 2

014

004

003

------.,1-----+1

m

AOORESS REGISTER
AND INVERTERS

m

AS

A6

AJ

FIGURE 1. MM54C920/MM74C920 Logic Diagram
Dual-in·Line-Package

vcc
22

A4

m

WE
21

20

19

Sf
18

m
17

004
16

014
15

Dual·in-Line·Package
003
14

013
13

'-

1
A3

2
A2

3
Al

5

4
AD

AS

6
A6

J

18

12

8

AJ. GNO

9
011

10

A4

11

WE
16

-

-

MM54C920/MMJ4C920

-

. vcc

002

en
15

~

14

en
13

01/04

01/03

01/02

12

11

10

-

MM54C921/MM74C921

r--

11

1
A3

DO 1 012

1-132

3

2
A2

Al

4
AD

5
A5

6
A6

J
AJ

8

9

GNO

01101

functional description (con't)
fall after STROBE has fanen without affecting access
time.

The addressed word (4 bits) is fed to four sense amplifiers through the column decoders_ The information
from the sense amplifiers is retai'ned in the output
register when STROBE rises: The register drives the
TRI-STATE output buffers.

The outputs are in a high impedance state when the
chip is not selected (CES or CEl high) or when writing
(WE low). Note that the information stored in the output latches will be changed whenever STROBE falls,
regardless of the logic states of WE, CE lor CES.

Chip select inputs, CE land CES, have identical functions
except that CES (Chip Enable Stored) is clocked into a
latch on the falling edge of STROBE; CEl (Chip Enable
Level) is not.

The timing diagrams in Figures 2, 3, and 4 define the
read, write, and output enable/disable parameters
respectively.

Note that setup and hold times must be observed on
CES_ Because CEl is not clocked by STROBE, it may

absolute maximum ratings
Supply Voltage, Vee
Voltage at Any Pin
Operating Temperature Range
MM54C920, MM54C921
MM74C920, M~74C921
Storage Temperature Range

7V
-O.3V to Vee + O.3V
-55°C to +125°C
-40°C to +85°C
-65°C to +150°C

dc electrical characteristics
PARAMETER

VCC

= 5V ±10%, T A = Operating

Range
MM74C920, MM74C921

MM54C920, MM54C921

CONDITIONS

MIN

TYP

logical "I" Input Voltage

o

logical "0" Input Voltage

=-1.0 mA .

MAX

MIN

Vee

V ee -2.0

O.B

UNITS

TYP

MAX

V

o

V

O.B

V OH1

logical "1" Output Voltage

IOH

V OH2

logical "I" Output Voltage

lOUT

=0

Vall

logical "0" Output Voltage

10L =

2.0 mA

0.4

0.4

V

V OL2

logical "0" Output Voltage

lOUT

=0

0.01

'0.01

V

Input leakage

OV:S VIN :S Vee

-1.0

0.001

1.0

-1.0

0.001

1.0

pA

10

Output leakage

OV:S Va :S Vee. CEl = Vee

-1.0

0.001

1.0

-1.0

0.001

1.0

pA

Icc

Supply Current

VIN

0.1

10

0.1

10

pA

Input Capacitance

(Note 1)

4

7

4

Output Capacitance

(Note 1)

6

9

6

9

pF

Data Input/Output Capacitance

MM54C921 /MM74C921 Only

B

12

B

12

pF

Vee for Data Retention

CEl

Co

V OR

= Vee.

2.4

V

2.4

V

=OV

Va

= Vce

2.0

pF

V

2.0

Nota 1: Capacitance is guaranteed by periodic testing.

ac electrical characteristics

VCC = 5V ±10%, TA = Operating Range
MM54C920. MM54C921

PARAMETER

TYP

MIN
TTL Interface (V IH = Vee - 2.0V. V IL

= O.BV.

Input tRISE

= tFALL

MM74C920, MM74C921
MAX

= 5 ns. load

MIN

UNITS
TYP

MAX

= 1 TTL Gate + 50 pF)

te

Cycle Time

tAee

Access Time From Address

120

275

120

250

ns

tAes

Access Time From Strobe

110

250

110

225

ns

tAS

Address Setup Time

25

10

25

10

tAH

Address Hold Time

25

15

25

15

ns

tOE

Output Enable Time

60

150

60

130

ns

too

Output Disable Time

60

150

60

130

tST-

Sf Pulse Width

tST
twp

290

(Negative)

120

150

60

ST Pulse Width (Positive)

140

60

Write Pulse Width (Negative)

150

80

tDS

Data Setup Time

100

40

tOH

Data Hold Time

60

25

255

ns

. ns

ns

60

ns

125

60

ns

130

80

ns

90

40

ns

60

25

ns

130

1-133

120

switching time waveforms

IST-----i
IST---~

1ST

AO-Al

--.V--~

~~r_JI~-----------------------

~~--~--I~I~.H~-----------------------------­

m

"--r---

I~------I.CS__,__-------I

1--10, -

1-------DOUT

----- -- --- ---

Iwp-----i

i.cc - - - - - - - - - 11 , - - - -

1,----------

TRI·STATE-------------

(10'

D'N _ _ _ _ _ _ _ _ _ _

FIGURE 2. Read Cycle (WE = VIH)

FIGURE 3. Write Cycle

FIGURE 4. Output

Enabl~/Disable

typical performance characteristics
Access Time vs Ambient
Temperature

Access Time vs Power Supply
Voltage

400 ,..,-.,---,.--,------.----..."

Minimum Write Pulse Width
vs Ambient Temperature

300

200

Data-In Setup Time vs
Ambient Temperature
125

r-Mr----.---.-----,---..,..,

TA .125°C
250
300
200

.]

~

!

200

]

"-........

150

""'- r--- I---

100
100
50

o

o
25

85

125

3

4.5

3.5

TA (OC)

85

5.5

125

25

Minimum ST Pulse Width
(Positive)'vs Ambient
Temperature

Data In Hold Time vs
Ambient Temperature

200 ,..,--,---..,.--r-----.,----.,....,

100

85

125

TA (OC)

Vee (V)

40

75

Address Hold Time vs
Ambient Temperature
,...,-..,.---,..--r-----.,----........

30

Address Setup Time vs
Ambient Temperature
,..,...-,---..,.--r------r---.......

30
.."

1

50

J

25

20

10

-55-40

0

25
TA (OC)

85

125

-55 -40

0

25

85

125

o

25
TA (OC)

TA (OC)

1·134

85

125

o

25
TA (OC)

85

125

typical performance characteristics (con't)

200

Dynamic Current vs Power
Supply Voltage
IDYN = (Curve Valuel
(Operating Freql-i- 1 MHz

Minimum Sf Pulse Width
(Negativel vs Ambient
Temperature

Output Enable Time vs
Ambient Temperature
rT-r---r~------r---~

200

r-T--.-----r~------r---.,....,

TA
""

~

./

.§

...

-

o

100 H-,*~~~~~~~~~

""~

~ 100

~ 25"C

2.5

V

1.5

V

V

V

>-

~

-55 -40

125

0

25

o

125

85

0.5

3

TA lOCI

-20

40
Vee

Vee' 5V
-11.5

~

.§

I

30

-10
~

-1.5
-5
-2.5

o~
5

. . . . V J..........: k::: ~ ~

I

4.5

4

Ft:t:

10

3

2.5

VOUT (VI

2

1.5

o
1

-I--

.-1-"

-

i// 1./ Io'T A = 125'C

IIV

TA = 125·'C

I I
3.5

//

15

5.5

Test Limit MM54C920, MM54C921

TA =25'C

/j...-....

/

20

~

~

. . . .V

25 i---I - - 1--.

= 5V

.-L

TA =-55'C

TA =-55'C

:I

0

35

I I
I I

-15
-12.5

4.5

Vee (VI

Output Sink Current vs .
Output Voltage

Output Source Current vs
Output Voltage

3.5

W
o

0.5

Test Limit MM74C920, MM74C921
1

1.5

2

2.5

V OUT (V)

1·135

3

3.5

4

M

~~
:E

.......
M

~

(J

MM54C922/MM74C922 16 key encoder
MM54C923/MM74C92320 key encoder

~
Lt)

:E
:E
general description
These CMOS key encoders provide all the necessary
logic to fully encode an array of SPST switches. The
keyboard scan can be implemented by either an external
clock or external capacitor. These encoders also ha~e onchip pull·up devices which permit switches with up to
50 kD on resistance to be used. No diodes in the switch
array are needed to eliminate ghost switches. The
internal debounce circuit needs only a single external
capacitor and can be defeated by omitting the capacitor.
A Data Available output goes to a high level when a
valid keyboard entry has been made. The Data Available
output returns to a low level when the entered key is
released, even if another key is depressed. The Data
Available will return high to indicate acceptance of the
new key after a normal. debounce period; this two key
roll over is provided between any two switches.

provide for easy expansion and bus operation and are
LPTTL compatible.

features
•

50 kD maximum switch on resistance

•

On or off chip clock

•

On chip row pull-up devices

•

2 key roll-over

•

Keybounce elimination with single capacitor

•

Last key register at outputs

•

TRI-STATE outputs LPTTL compatible

•

Wide supply range

•

Low power consumption

An internal register remembers the last key pressed
even after the key is released. The TRI-STATE® outputs

3V to 15V

connection diagrams

Dual·1 n·Line Package

18

ROW VI

Dual·1 n·Line Package

ROW VI

20 Vee

RDWV2

19 DATA OUT A

Vee

ROW V2
ROW Vl

OATA OUT B

ROW V4

DATA OUT C

OSCILLATOR

DATA OUT 0

ROW V3
ROW V4
ROW V5
OSCILLATOR

OUtpUt ENABLE

KEVBDUNCE MASK
COLUMN X4
COLUMN Xl

COLUMN XI
10 COLUMN X2

GND

14 OUTPUT ENABLE

KEVBOUNCE MASK

DATA AVAILABLE

COLUMN X4

13 OATA'AVAILABLE

COLUMN X3

12 COLUMN XI

'GNO 10

11 COLUMN X2

TOP VIEW
TOPVIEW

Order Number MM54C922N
or MM74C922N

Order Number MM54C923N
or MM74C923N

See Package 20

See Package 20A

1-136

~

's:

absolute maximum ratings
Voltage at Any Pin
Operating Temperature Range
MMS4C922, MMS4C923
MM74C922, MM74C923
Storage Temperature Range

Package Dissipation
Operating VCC Range
VCC
Lead Temperature (Soldering, 10 seconds)

VCC - O.3V to VCC + O.3V
-SSoC to +12SoC
-:-40°C to +8SoC
--6SoC to +1S0°C

SOOmW
3V to 1SV
18V
300°C

U1

~

(")
(D

N
N

........

dc electrical characteristics
PARAMETER

~

~
.....,

Minimax limits apply across temperature range unless otherwise noted
CONDITIONS

MIN

TYP

MAX

UNITS

VT+

Positive·Going Threshold Voltage at

:

VIN(1)

VIN(O)

Irp

IIN~0.7mA

3

3.6

4.3

V

Vee = 10V, liN ~ 1.4 mA

6

6.B

8.6

V

Vee=15V, liN ~2.1 mA

9

10

12.9

V

VCC = 5V,

Osc and KBM Inputs

VT-

Negative·Going Threshold Voltage at

Vee = 5V,

IIN~0.7mA

0.7

1.4

2

V

Osc and KBM Inputs

Vee = 10V, liN ~ 1.4 mA

1.4

3.2

4

V

Vee=15V, IIN~2.1mA\

2.1

5

6

V

3.5

4.5

V

N

8

9

V

........

Vee=15V,

12.5

Logical "0" Input Voltage, Except

Vee = 5V,

0.5

1.5

Osc and KBM Inputs

Vee = 10V,

1

2

V

Vee = 15V,

1.5

2.5

V

.(")

N
W

Row Pull·Up Current at Y1, Y2, Y3,

Vee = 5V,

Y4 and Y5 Inputs

Vee = 10V

V I N=0.1 vee

13.5

-5

J.lA

-10

-20

J.lA

-22

-45

J.lA
V

Vee = 10V, 10 = -10J.lA

9

V

Vee=15V, 10 = -10J.lA

13.5

Vee = 5V,

V

10 = 10J.lA

0.5

V

1

V

1.5

V

500

1400

.Q

Vee = 10V, Vo = 1V

300

700

.Q

Vee=15V, VO=1.5V

200

500

0.55

1.1

Vee = 5V,

X 1, X2, X3 and X4 Outputs

Logical "1" Input Current at

V

4.5

10 = -10J.lA

Vee = 5V,

Column "ON" Resistance at

Supply Current

V

-2

Vee=15V, 10= 10J.lA
Va = 0.5V

Osc at OV

Vee = 5V,

.Q

mA

Vee = 10V

1.1

1.9

mA

Vee = 15V

1.7

2.6

mA

Vee=15V, VIN=15V

0.005·

1.0

J.lA

Output Enable
Logical "0" Input Current at

Vee = 15V, VIN = OV

-1.0

--{l.005

J.lA

Output Enable
CMOS/LPTTL INTERFACE
VIN(1)

VIN(O)

~

(")
(D

Vee = 10V,

Vee = 10V, 10 = 10J.lA

IIN(OI

U1

Vee = SV,

VOUT(O) Logical "0" Output Voltage

IIN(1)

~
~

Logical "1" Input Voltage, Except

Vee = 15V

ICC

N
N

Osc and KBM Inputs

VOUT(1) Logical "1" Out'put Voltage

Ron

~

(")
(D

CMOS TO CMOS

V

Logical "1" Input Voltage, Except

54e, Vee = 4.5V

Vee-1.5

Osc and KBM Inputs

74e, Vee = 4.75V

Vee-1.5

Logical "0" Input VoHage, Except

54e,.Vee = 4.5V

0.8

Osc and KBM Inputs

74e, Vee = 4.75V

0.8

VOUT(1) Logical "1" Output Voltage

54C, Vce = 4.5V,

V
V
V

2.4

V

2.4

V

10 = -360JlA
74C, VCC = 4.75V,
10 = -360JlA
VOUT(O) Logical "0" Output Voltage

54C, Vce = 4.5V,

0.4

V

0.4

V

10 = -360JlA
74C, Vec = 4.75V,
10 = -360JlA

1-137

W

~

3:
.....,
~

(D

.dc electrical

charact~ristics

(can't)

PARAMETER

CONDITIONS

TYP

MIN

MAX

UNITS

OUTPUT DRIVE (See 54C174C Family Characteristics Data Sheetl
'ISOURCEOutput Source Current (P·Channel)

ISOURCE Output Source Current (P·Channel)

VCC = 5V, VOUT = OV,
TA = 25°C

-1.75

-3.3

mA

VCC = 10V, VOUT = OV"

-8

-15

mA

1.75

3.6

mA

8

16

mA

MIN

TYP

TA= 25°C
Output Sink Current (N·Channel)

ISINK

VCC:= 5V, VOUT = VCC,
TA = 25°C

Output Sink Current (N·Channel)

ISINK

VCC = 10V, VOUT = VCC,
I
TA = 25°C

N

N

en
CJ

ac electrical characteristics

r:!:

........
N
N

CONDITIONS

PARAMETER

~

~.

TA = 25°C

tpdO,tpd1

en

Propagation Delay Time to

I.t)

tOH,t lH

~
~
tHO,tHl

UNITS

CL = 50 pF, (Figure 1)

Logical "0" or Logical "1"

VCC = 5V

60

150

ns

from D.A.

VCC = 10V

35

80

ns

VCC = 15V

25

60

ns

CJ
~

MAX

Propagation Delay Time from

·RL = 10k, CL = 5 pF, (Figure 2)
RL'= 10k

Logical "0" or Logical "1"

VCC = 5V

80

200

ns

into High Impedance State

VCC = 10V CL = 10 pF

65

150

ns

VCC= 15V

50

110

ns

ns

Propagation Delay Time from

RL = 10k, CL = 50 pF, (Figure 2)

High Impedance State to a

VCC = 5V

100

250

Logical "0" or Logical "1"

VCC = 10V CL = 50 pF

55

125

ns

VCC = 15V

40

90

ns

7.5

pF

RL = 10k

CIN

Input Capacitance

Any Input, (Note 2)

5

COUT

TR I·ST A TE Output Capacitance

Any Output, (Note 2)

10

-

pF

Note 1: "Absolute Maximum .Ratings". are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.

switching time waveforms

=ve:-~
Vee
ANY OTHER
KEY

-=:.j
vee---+---c_=c_=_=-=_=_

---+--., ..

f-tOH

~RI.STATE®

DATA OUT

--,

0.1 Vee

Vee-----t-r----""""
DATA
AVAILABLE
Vee---r----

~~r:~~
Vee---_
DATA
OUTPUT

0.5 Vee

o
Vee

DATA OUT

O-----·'-------J

IH

~

0.1 Vee

~

. .

, 0--------

T1 '" T2 '" RC, T3 '" 0.7 RC where R "" 10k and C is external
capacitor at KBM input.
FIGURE 2

- FIGURE 1

1·138

.

_ _ J,!.R,!!TATE®

s:
s:U1

block diagram

~

10k

n

DATA
AVAILABLE

CD
N
N

.......

S:'

s:

"""".
~

n
CD

N
N·

s:
s:
U1

no 4 DECODER
ACTIVE LOW OUTPUTS
X4

X3

X2

XI

Vee

KEY
DETECT

~

n

INTERNAL

CD
N
Co\)

.......
SPST
SWITCH

s:
s:

ENCODING
LOGIC
AND
2-KEY
ROLL OVER

_~-.r-

~

n""""
CD
N

Co\)
KEY
ARRAY

MSB

truth table
SWITCH
POSITION

~

YI.XI

Yl.X2

YI.X3 Yl.X4 Y2.Xl

Y2.X2 Y2.X3 Y2.X4

Y3.Xl

10
11
Y3.X2 Y3.X3 Y3.X4

12
Y4.Xl

13
14
15
16
Y4.X2 Y4.X3 Y4.X4 Y5*.Xl

11
YS*.X2

A

T
A

o
~

0
E*

*Omit for MM54C922/MM74C922

typical performance characteristics
Typical Ron vs VOUT at Any
X Output

Typical Irp vs VIN at Any
Y Input

;;

.;:,
0Z

a:
a:

::>
u

30

.--------r-----,-...-----,

I vce =3V

25

1----+---+ Vee =15V

L

I
I
I

20
15

::>
::>

10 1---1'----::1;.--"'""'1 Vee

=

I

10V

~

----

15

.-"

10V

10
Your (V)

1-139

=25°e

5V

/

'/
10

TA

15V

15

18
YS*.X3

19
YS*.X4

typical performance characteristics (con't)
Typical Debounce Period
vsCKBM

Typical FSCAN vs COSC'
10k _ _
c
z
o

u

~ 0.1.~1
~ t=

lk
x

""

~

I

100

0.01

~~IIMII~I;

10

0.1

10

100

COSC (~F)

typical applications
Synchronous Data Entry Onto Bus (MM74C922)

Synchronous Handshake (MM74C922)

MM74C922

T

10C

.""J:""_ 1DC
MM74C922

~-...fX4;~

DATA AVAILABLE
(INVITATION)

Outputs are enabled when valid entry is made and
go into TRI-STATE when key is released.

Asynchronous Data Entry Onto Bus (MM74C922)

T_

10C

MM74C922

r-----~--~~x;4IK~BMM--l

1----.

TO DATA BUS

I--~t-. DATA AVAILABLE

1/674C04

Outputs are in TRI-STATE until key is pressed, then data is placed on bus .
. When key is released, outputs return to TR I-STATE.
Note 3: The keyboard may be synchronously scanned by omitting the capacitor at osc. and driving osc. directly if the system clock
rate is lower than 10 kHz.

'·140

MM74C925, MM74C926, MM74C927, MM74C928
4-digit counters with multiplexed 7-segment output drivers
general description
These CMOS counters consist of a 4-digit counter, an
internal output latch, NPN output sourcing drivers for
a 7-segment display, and an internal multiplexing
circuitry with four multiplexing outputs. The multiplexing circuit has its own free-running oscillator,
and requires no external clock. The counters advance
on negative edge of clock. A high signal on the Reset
input will reset the counter to zero, and reset the carryout low. A low sigrial on the ,Latch Enable input will
latch the number in the counters into the internal output latches. A high signal on Display Select input will
select the number in the counter to be displayed; a low
level signal on the Display Select will select the number
in t.he output latch to be displayed.
The MM74C925 is a 4-decade counter and has Latch
Enable, Clock and Reset inputs.
The MM74C926. is like the MM74C925 except that it
has a display select and a carry-out used for cascading
counters. The, carry-out signal goes high at 6000,
goes back low at 0000.
'
The MM74C927 is like the MM74C926 except the
second most significant digit divides by 6 rather than 10.
Thus, if the clock input frequency is 10 Hz, the display
would read tenths of seconds and minutes (i.e., 9:59.9).
The MM74C928 is like the MM74C926 except the most
significant digit divides by 2 rather than 10 and the

carry-out. is an overflow indicator which is high at
2000, and it goes back low only when the counter is
reset. Thus, this is a 3 1/2-digit counter.

features
• Wide supply voltage range
3V to 6V
• Guarapteed noise margin
1V
• High noise immunity
0.45 Vee typ
• High segment sourcing current
40 mA
@ Vee - 1.6V, Vee = 5V
• Internal multiplexing circuitry

design considerations
Segment resistors are desirable to minimize power
dissipation and chip heating. The DM75492 serves as a
good digit driver when it is desired to drive bright
displays. When using this driver with a 5V supply at
room temperature, the display can be driven without
segment resistors to full illumination. The user must use
caution in this mode however, to prevent overheating of
the device by using too high a supply voltage or by
operating at high ambient temperatures.
The input protection circuitry consists of a seri,es resistor,
and a diode to ground. Thus input signals exceeding
Vce will not be clamped. This input signal should not be
allowed to exceed 15V.

connection diagrams
Dual-I n-Line Package
MM74C925
Vee

Dual-In-Line Package
MM74C926, MM74C927 and MM74C928

RESET

CLOCK

Dour

COUT

LATCH

AOUT

BOUT

GND

ENABLE
TOPVIEW

CARRY
OUT RESET

Vee

D

LATCH DISPLAY
ENABLE SELECT
TOPVIEW

CLOCK

DOUT

COUT

AOUT

BOUT

GND

functional description
Reset

Asynchronous, active high

Display Select

High, displays output of counter
Low, displays output of latch

Latch Enable

High, flow through condition
Low, latch condition

Clock

Negative edge sensitive

Segment Output

Digit Output

Carry-out
1-141

Current sourcing. with 80 mA @
VOUT = Vee - 1.6V typical.
Also, sink capability = 2 LTTL
loads
Current sou~cing with 1 mA @
VOUT = 1. 75V. Also, sink capability = 2 LTTL loads
2 LTTL loads. See carry-out
waveforms.

\.

. absolute maximum ratings

(Note 1)

Voltage at Any Output Pin
Gnd - O.3V to Vee+O.3V
Voltage at Any Input Pin
. Gnd - O.3V to +15V
-40°C to +85°C
Operating Temperature Range (T A) "
-65°C to +150°C
Storage Temperature Range
Package Dissipation
Refer to PO(MAX) vs T A Graph
Operating Vee Range
3V to 6V
6.5V
Vee
300°C
Lead Temperature (Soldering, 10 seconds)

dc electrical characteristics

Minimax limits apply at -40°C -::; Tj

PARAMETER

-::;

CONDITIONS

+85°C, unless otherwise noted.
MIN

TYP

MAX

UNITS

CMOS TO CMOS
V ,N(1 )

Logical "1" Input Voltage

Vee = 5.0V

V,NIO)

Logical "0" Input Voltage

Ve~ = 5.0V

V OUT (1)

Logical "1" Output Voltage

Vee = 5.0V, 10 = -10,uA

3.5

V
1.5

V
V

4.5

(Carry·out and Digit Output
Only)
V OUTlO;

Logical "0" Output Voltage

Vee = 5.0V, 10 = 10,uA

I'N(1)

Logical "1" Input Current

Vee = 5.0V, V ,N = 15V

I'NIO)

Logical "0" Input Current

Vee = 5.0V, V ,N = OV

lee

Supply Current

Vee = 5.0V, Outputs Open Circuit,

0.005
-1.0

0.5

V

1.0

,uA

-0.005
20

J..IA
1000

,uA

V ,N = OV or 5V
CMOS/LPTTL INTERFACE

V'~(1)

Logical "1" Input Voltage

Vee = 4.75V

.V 'NIO)

Logical "0" Input Voltage

Vee =4.75V

Logical "1" Output Voltage

Vee =4.75V,

(Carry-Out and Digit

10 = -360,uA

VOUT(1)

V ee -l.5

V
0.8

V
V

2.4

Output Only)
VOUTIO)

Logical "0" Output Voltage

Vee = 4.75V,

0.4

V

10 = 360,uA
OUTPUT DRIVE
V OUT

Output Voltage (Segment
Sourcing Output)

RON

Output Resistance (Segment

lOUT = -65 mA, Vee = 5V, T j = 25°C
lOUT = -40 mA, Vee = 5V
lOUT

= -65 mA, Vee

lOUT

= -40 mA,

Sourcing ,?utput)

{ T = 100°C
T; = 150°C"

Vee -l.6
V ec -2

= 5V, T j = 25°C

Vee = 5V

V ee -l.3

V

V ee -l.2
V ee -l.4

V
V

35

50

n
n
n

0.6

0.8

%tc

20
30

{ T j = 100:C
T j = 150 C

Output Resistance (Segment

40

Output) Temperature Coefficient
ISOURCE

Out~iut Source Current

Vee = 4.75V, V OUT = 1.75V, T j = 150°C

-1

-2

mA

Vee = 5V, V OUT = OV, T j = 25°C

-1.75

-3.3

mA

1.75

3.6

mA

(Digit Output)
ISOURCE

Output Source Current
(Carry·out)

ISINK

Output Sink Current

Vee = 5V, V OUT = Vee, T j = 25°C

(Ali Outputs)

8 jA

Thermal Resistance

MM74C925

(Note 4)

MM74C926, MM74C927, MM74c928

75

100

°C/W

70

90

°C!W

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides
conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3:. CPD determines the no load ac power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics
application note, AN-gO.
Note 4: (JjA measured in free-air with device soldered"into printed circuit board.

1-142

ac electrical characteristics

T J = 25°C, C L = 50 pF, unless otherwise specified

PARAMETER

f MAX

CONDITIONS

Maximum Clock Frequency

t"tl

Maximum Clock Rise or Fall Time

tWR

Reset Pulse Width

tsET(eK,LE)

2

4

Square Wave Clock

T j = 100°C

1.5

3

Vee = 5.0V

Clock to Latch Enable Set·Up Time

Vee = 5.0V

Reset to Latch Enable Set'Up Time

UNITS
MHz
MHz

Vee = 5.0V

ps

T j = 25°C

250

100

ns

T j = 100°C

320

125

ns

T j = 25°C

250

100

ns

Tj.= 100°C

320

125

ns

T j = 25°C

2500

1250

ns

T j = 100°C

3200

1600

ns

u

Vee = 5.0V

Wait Time
tSET(R,LE)

MAX

15

Vee = 5.0V

Latch Enable to Reset

tLR

TYP

T j = 25°C

Vee = 5.0V

Latch Enable Pulse Width

tWLE

MIN

Vee = 5.0V,

T j = 25 C

0

-100

ns

T j = 100°C

0

-100

ns
ns

T j = 25°C

320

160

T j = 100°C

400

200

ns

f MUX

Multiplexing Output Frequency

Vee = 5.0V

1000

Hz

CIN

Input Capacitance

Any Input (Note 2)

5

pF

typical performance characteristics
Typical Segment Current vs
Output Voltage

§
.5.2200

~ 2000

....::>
~

....
~

~
j

..
~

~

lBOO
~ 1600

BO

60 I---H-~F----';

--+---1

40

~-~F-~-~-~-

20

~-,~-~-~-~~
5.0

4.0

3.0

2.0

~

1400

~ 1200

~ 1000

~

I
I

I I
I I

~

BOO

~
~

600
400

~

200

....
z
a:
a:

::>

MM74C926/MM74C927/MM74C928

!

l'

..

CI

~

a:

....

:>

0

20

40

60

80

TA -AM8IENTTEMPERATURE (OC)

100

~

10

20

30

40

50

60

70

SEGMENT RESISTOR (n)

Note. VD = Voltage across digit
driver.

logic and block diagrams
MM74C925

0.:.:+--....---4...---....---.

15

....
z

1"-

MM74C925

0_ 40 -20

Vour'(V)

RESET

.5.

I I I
III

::;;

~

1.0

Typical Average Segment
Current vs Segment Resistor
Value

Maximum Power Dissipation
vs Ambient Temperature

MM74C926
Vee

I....------r~

Vee

1....- - - - - 4 ! ! . ( ) C L D C K

CLOCK

DISPLAY
SELECT
LATCH

LATCH
ENABLE

E~ABLE

AOUT

AOUT

BOUT

BOUT

·C OUT

COUT
Doul
, GND

DOUl

GND

MM74C927
RESET ~:..J--""---4"'---""--'"

MM74C928
Vee

ClOCK

RESET
CARRY·
OUT

DISPLAY
SELECT
LATCH
ENABLE

DISPLAY
SELECT

AOUT

AOUT

LATCH
ENABLE

BOUT

BOUT

COUT
DOUl

COUT
DOUT

GND

GND

1-143

Vee

1....- - - - - 4 ! ! . ( )

CLOCK

Segment Output Driver

Input Protection

Vee

Vee

INPUT'"'-----'~AS

BV

~l~

OUTPUT

~7V

CD

N

0)
Segment Identification

Common Cathode LED Display

U

~

::I I_I
I' I ::I _1
I_I
I 11I- I1::1 1:;1
I 1_1 _1

I"

,
=, ,=,

~
~

lti
N

0)

a

u

f/glll
el=lc
d

r:t
2

~

switching time wavefonnsInput Waveforms

I

CLOCK

. r--l
r-l
r
--.J . L..J
L-J
tSETleKLEIi-1

Carry-Out Waveforms

Multiplexing Output Waveforms

I

AOUT~"---_----II
1-7/32T-1 ~1/J2T

I

BOUT

LATCH
ENABLE

----~~

I

CLOCK.J'l.J1

MM74C926
CARRY·OUT

nL....--_

COUT
RESET

DOUT

1-144

MM74C927
CARRY·OUT

fl-f1-

.------,

---1

COUNT

~--------------

n

L-

COUNT

5999-6000
9999-0000
.------,

----l

'-

COUNT

COUNT

5599-6000

9599-0000

MM54C929/MM74C929. MM54C930/MM74C930
1024-bit static silicon gate CMOS RAMs
general description

features

The MM54C929/MM74C929 and the MM54C930/
MM74C930 1024 x 1 random access read/write memories
are manufactured using silicon gate CMOS technology.
These RAMs are specifically designed to operate from
standard 54/74 TTL power supplies; all inputs and
outputs are TTL compatible. Data output is the same
polarity as data input. Internal latches store ~address
inputs and data output. Chip select input CS1 serves
as a chip strobe, controlling address and data latching.
The Data-In and Data-Out terminals can be tied together
for common I/O applications. Complete address decoding,
3-chip select functions (MM54C930/MM74C930) and
TR I-ST ATE® output allow easy memory expansion and
organization. The MM54C929/MM74C92~ff~from
the MM54C930/MM74C930 only in that CS1, CS2 and
CS3 are internally connected together, providing a'single
chip-select input.

•
•
•

Fast access-250 ns max
TRI-STATE outputs
Low power-1 0 pA max standby

•
•
•
•
•

On-chip registers
Single 5V supply
Inputs and output TTL compatible
Data retained with VCC as low as 2V
Can be operated common I/O

Versatility, high speed, and low power make these RAMs
ideal elements for use in many microprocessor minicomputer and main frame memory applications.

function~1

description

Address inputs are clocked into the input latches by the
falling edge of chip strobe CS1; set-up and hold times
must be observed on these input signals (see timing diagram). The true and complement address information is
fed to the row and column decoders which select one of
the 1024-bit locations. The addressed bit is fed, via a
sense amplifier, .to the output register and TRI-STATE
buffer. The information is latched into the output
register on the rising edge of ch ip strobe CS1. The out,
put is in a high impedance state when the c~is not
selected (CS2 or CS3 high) or when writing (WE low).
Output buffer control is independent of chip strobe CS1.

block and connectiort diagrams
AD
Al
AZ
AJ
A4

DI-----I----+I

DD

FIGURE 1
Dual-I n-Line Package

Dual-In-Line Package
WE

AS

Ai

AI

A6

m

AS

DI

WE

A9

AS

A7

A6

AS
10

MMS4CSJO/MM74C9JD
IDZ4 X I

MMS4C9Z9/MM74C9Z9
ID24XI

l:S

AD

Al

AZ

AJ

A4

DD

m

GND

1·145

ill

AD

Al

AZ

AJ

A4

DD

GND

absolute maximum ratings
Supply Voltage, VCC
Voltage at Any Pin
Storage Temperature Range

7V
-o.3V to VCC + 0.3V
--v5°C to +150°C

dc electrical characteristics
PARAMETER

Operating Temperature Range
MM54C929, MM54C930
MM74C929, MM74C930

-55°C to +125°C
-40°C to +B5°C

Vee = 5V ±10%, TA = Operating Range
MM74C929, MM74C930

MM54C929, MM54C930

CONDITIONS

MIN

TYP

MAX

MIN
VCe- 2 .O

Logical "1" Input Voltage

VCe- 2 .O

VCC

Logical "0" Input Voltage

o

O.B

MAX

TYP

UNITS

VCC

V

O.B

V

o

2.4

2.4

V

VCe-O.Ol

VCe-O.Ol

V

VOHl

Logical "1" Output Voltage

101;1 = -1 mA

VOH2

Logical "l,,'Output Voltage

lOUT = 0

VOL 1

Logical "0" Output Voltage

10L = 2 rnA

0.4

0.4

V

VOL2

Logical "0" Output Voltage

lOUT = 0

0.01

0.01

V

IlL

Input Leakage

OV ~ VIN ~ VCC

IC

Output Leakage

OV

ICC

Supply Current

VIN = VCC, Vo = OV

~

Vo

~

VCC,

~S2

or CS3 = VCC

-1.0.

0.001

1.0

-1.0

0.001

1.0

-1.0

0.001

1.0

-1.0

0.001

1.0

Il A

0.5
0.25

100

0.5
0.25
4

10

Il A

VIN = VCC = 2V, Vo = OV, at 25°C
VIN = VCC = 2V, Vo = OV, at 125°C

VDR

Il A

Il A
Il A

Input Capacitance

(Note 1)

4

7

4

7

pF

Output Capacitance

(Note 1)

6

9

6

9

pF

Chip Select Capacitance

(Notes 1 and 2)

7

10

7

10

pF

VCC for Data Retention

CS2mCS3=CS1=VCC

'2.0

2:0

V

Note 1: Capacitance maximum is guaranteed by periodic testing.
Note 2: MM54C929/MM74C929.

ac electrical characteristics

Vee = 5V ±10%, TA = Operating Range
MM54C929, MM54C930

PARAMETER

MIN

TYP

MM74C929, MM74C930 '
MAX

MIN

TTL Interface (VIH = VCC - 2V, VIL = O.SV,lnput tRISE = tFALL = 5 ns, Load = 1 TTL Gate + 50 pF)

TYP

MAX

UNITS

,

tc

Cycle Time

tACC

Access Time From Address

105

265

105

240

ns

tACSl

Access Time From CSl

100

250

100

225

ns

290

135

255

ns

135

ns

tAS

Address Set-Up Time

15

5

15

5

tAH

Address Hold Time

50

20

50

20

tOE

Output Enable Time

60

150

60

130

ns

tOD

Output Disable Time

60

150

BO

130

ns

tCS1,
(Note 3)

CS1 Pulse Width (Negative)

150

75

130

75

tCSl

CS1 Pulse Width (Positive)

140

60

125

60

twp

Write Pulse Width (Negative)

150

BO

130

BO

ns

tDS

Data Set-Up Time

150

75

140

75

ns

tDH

Data Hold Time

o

-30

ns

o

-30

ns

ns

Typical'''' Nominal at 25°C
Note 3: Greater than minimum CS1 pulse width must be used when reading data from the MM54C929/MM74C929 to ensure that output TRISTATING does not occur before data becomes valid. Writing has no such limitation.

truth tables
MM54C930/MM74C930

MM54C929/MM74C929

CS

,

WE

01

X

X

X

o
o
o

o
o
o
X

,

= Don't care

FUNCTION
Output in Hi-Z State

x

1

X

X

Output in.Hi-Z State

X

X

1

o

Write "0," Output in Hi-Z State

X

X

X

,

Write "'," Output in Hi-Z State

X

Read Data, Output Enabled

o
o
o

o
o

o
o
o

1-146

o

01

FUNCTION

X
X

X

Output in Hi-Z State

X

Output in Hi-Z State

o
o
o

X

Output in Hi-Z St'ate

o

Write "0," Output in Hi-Z State

1

Write "'," Output in Hi-Z State

1

X

Read Data, Output E~abled

switching time waveforms
rn

rn

AD-AI

AO-A9

ill AND

-J'I'-~-JI~

-+______________

______

m

1-----'ACS1-----1
I------'ACC------Ir-----DDUT -

-

-

-

-

-

-

TRI·STATE·... -

-

-

-

-

-

DATA OUT VALID

*Greater than minimum CS1 pulse width must be used when
reading data from the MM54C929/MM74C929 to ensure that
output TRI-STATING does not occur before data becomes valid.
Writing has no such limitation.
FIGURE 2. Read Cycle (WE

=VIH)

DOUT -

-

FIGURE 3. Write Cycle

DATA OUT VALID

-TRI·STATE"- - -

FIGURE 4. Output Enable/Disable

typical performance characteristics
Access Time vs Ambient
Temperature
400

Access Time vs Power Supply
Voltage

r-r-.,..--""-~---r---n

Data-In Set-Up Time vs
Ambient Temperature

Minimum Write Pulse Width
vs Ambient Temperature
200

300

200 r-r--r---r--r------,----,.,

TA =25"C
250
300 H-+--+--+----+--~

.,..

" --

150
100
50

85

125

3

3.5

1-+"7~~~~~~~~nti

-55-40

60

H-+--+--+-----+---H

20

o

~">0."'-~

~

~"'-~

,,"
,,"

~

0.~

V~~' 4

'"

:!-

//;

,," "

~~
~? ;~W~·'

~

8S

85

~
~:VcC'l~~~~

40

~~'\..~~ ~~c' 5,5V~~
-55-40

25

125

.TA I'C)

o

-10
25
TA I'C)

1·147

125

Address Set-Up Time vs
Ambient Temperature

Address Hold Time vs
Ambient Temperature

150

~~

0

TA I'C)

30

50

125

125

80 n-~-~~----r--n

v.;~

85

85

200

~ 100

-25

25
TA I'CI

Minimum CSI Pulse
Width (Positive) vs
Ambient Temperature

25 n-~-~-r-----r--n

25

o

5,5

4.5
VCC IV)

Data-In Hold Time vs
Ambient Temperature

o

100
o

o
25
TA 1°C)

i5

-

""- .......

o-

I

ID2

FRED OUT

ID3
104
DIGIT 8LANK

i--+

~

COMPARATOR
TIMING

-

,---l----,

GND -VSS
DIGITAL VCC

Y

Sf

Sg

DIGIT I (LSD)
DIGIT2
DIGIT 3
DIGIT 4 (MSD)

r--f---

OVERFLDW
CONY COMPLETE
SIGN

100

~~

.....-L...c
D

ANALOG Vc C
VFILTER

rl.-:-L,

1

"

I

r- -

-

VREF

SWI

+ ...... ,

t::("
: ::
~
I

-VIN

So

IOVERFLOW
ROM

......

,

~

D
L-..-

L~--1

MM74C935 3%·Digit DVM Block Diagram

1·151

c
w
U1
o

~
So

~~

H>oH>o-

83f--

03f--

s,

-t>o-

-.,'

C2f-021--

H>o-

»c

SW2

ANALOG GND

5
Ln

M

C
C

~
o
o

Ln

M

C

C

~

theory of operation
A schematic for the analog loop is shown in figure 1.
The output of SW 1 is either at V REF or zero volts,
depending on the state of the D flip-flop. ~f a is at a
high level V OUT = V REF' and if a is at a low level V OUT
= OV. This voltage is then applied to the low pass filter
comprised of R 1 and C1. The output of this filter, V FB,
is connected to the negative input of the comparator,
where it is compared to the analog input voltage, V IN .
The output of the comparator is connected to the D
input of the D flip~flop. Information is then transferred
from the D input to the a and a outputs on the positive
edge of clock. This loop forms an oscillator whose duty
cycle is precisely related to the analog input voltage, V IN'

The lowpass filter will pass the DC value and then:

Since the closed loop system will always force V FB to
equal V IN, we can then say that:

or
(duty cycle)

An example will demonstrate this relationship. Assume
,the input voltage is equal to 0.500V. If the a output of
the D flip-flop is high then V OUT will equal V REF
(2,000V) and V FB will charge toward 2V with a time
, constant equal to R,C,. At some time V FB will exceed
0.500V and the comparator output will switch to OV.
At the next clock rising edge thea output of the D flip. flop will. switch to ground, causing V OUT to switch to
OV. At this time V FB will start discharging toward OV
with a time constant R,C,. When V FB is less than O.5V
the comparator output will switch high. On the rising
edge of the next clock the a output of the D flip-flop
will switch high and the process will repeat. There exists
at the output of SW1 a square wave pulse train with
positive amplitude V REF and negative amplitude OV.

The duty cycle is logically ANDed with the input
frequency fiN' The resultant frequency f equals:
f = (duty cycle) x (clock)

Frequency f is accumulated by counter no. 1 fora time
determined by counter no. 2. The count contained in
counter no. 1 is then:
(count)

=

(duty cycle) x (clock)
(clock)/N

(clock)/N

The DC value of this pulse train is:
V OUT

=

TON
V REF ( - - )
. TON+TOFF

= VREF(dutycycle)
On the MM74C935 N

= 2000.

schematic diagram

COUNTER NO.1 (+N)

RESET

L-------lCOUNTER NO. 2(+2N)

VIN= VFB = VREF x (duty cycle)
f = (duty cycle) x fiN
Count in Counter No.1
.

=

_f_ = (duty cycle) x fiN
flN/N
flN/N

=

Figure 1. Analog Loop Schematic
Pulse Modulation AID Converter

1-152

~xN
VREF

general information
The timing diagram, shown in figure 2, gives operation
for the free running mode. Free running operation is
obtained by connecting the Start Conversion input to
logic "1" (Vee!. In this mode the analog input is continuously converted and the display is updated at a rate
equal to 64,512 xl/fiN'

Internally the MM74C935 is" always continuously
converting the analog voltage present at its inputs. The
Start Conversion input is used to control the transfer
of information from the internal counter to the display
latch.

The rising edge of the Conversion Complete output
indicates that new information has been transferred
from the internal counter to the display latch. This
information will remain in the display latch until the
next low·to·high transition of the Conversion Complete
output. A logic "1" will be maintained on the Conversion
Complete output for a time equal to 64 xl/fiN'

An RS latch on the Start Conversion input allows a
broad range of input pulse widths to be used on this
signal. As shown in figure 3, the Conversion" Complete
output goes to a logic "0" on the rising edge of the
. Start Conversion pulse and goes to a logic "1" some time
later when the new conversion is transferred from the
internal counter to the display latch. Since the Start
Conversion pulse can occur at any time during the
conversion cycle, the amount of time from Start Con·
version to Conversion Complete will vary. The maximum
time is 64,512 x l/flN and the minimum time is
256 x 1/fIN'
"

Figure 3 gives the operation using the Start Conversion
input. It is important to note that the Start Conversion
input and Conversion Complete output do not influence
the actual analog-to-digital conversion in any way.

~
C

C

w
U1

o

,o

l>
C
C

w
U1
o

-=
timing waveforms
fiN

t"I:f-----------

1Ul

CONVERSION CYCLE
(INTERNAL SIGNAL)

64,512 x 1/fIN ----------t"~1

64.00Ox 1/f'N

!

-I

r--

I

1..---1

1------------ 64,256 x l/flN --------;~Ir-+i I

.......

r- 64/f lN

I

n..___

CONVERSION 1_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~...

COMPLETE

t

NEW
CONVERSION

CONVERSION
ENDS

I

STArTS

Timing Diagram MM74C935
Figure 2. Conversion cycle for free running operation

1-153

5
I.t)

M

o
o

~
o
oI.t)
M

,0

o

~

U

CONVERSION CYCLE ..- - . . . ; . . - - - - - -....
(INTERNAL SIGNAill

START

n

r-,

CONVERSION~I_ _ _--,

i

u

.-.

..._ _ _ _..1_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

.

CONVERSION
r------~
COMPLETE - - - - - - _ ...- - - - - - - - -

Figure 3. Conversion Cycle Operating with Start Conversion Input

applications
SYSTEM DESIGN CONSIDERATIONS
Perhaps the most important thing to consider when
designing a system using the MM74C935 is power supply
noise on the Vee and ground lines. Because a single
power supply is used and currents in the 300mA range
are being switched, good circuit layout techniques cannot be overemphasized. Great care has been exercised in
the design of the MM74C935 to minimize these problems
but poor printed circuit layout can negate these features.

most important characteristic of transients on the V cc
line is the duration of the transient and not its amplitude.
Figure 4 shows a DPM system which converts OV to
1.999V operating from a non-isolated power supply.
In this configuration the sign output could be + (logic
"1 ") or - (logic "0") and it should be ignored. Higher
voltages could be converted by placing a fixed divider
on the input; lower voltages could be converted by
placing a fixed divider on the feedback, as shown in
figure 6.

Figures 4, 5, and 6 show schematics of DVM systems.
An attempt has been made to show, on these schematics,
the proper distribution for ground and V cc. To help
isolate digital and analog portions of the circuit, the
_analog V cc and ground have been separated from the
digital Vcc and ground. Care must be taken to eliminate
high current from flowing in the analog V cc and ground
wires. The most effective method of accomplishing this
is to use a single ground point and a single V cc point
where all wires are brought together. In addition to this
the conductors must be of sufficient size to prevent
significant voltage drops.

Figures 5 and 6 show systems operating with an isolated
supply, that wi" convert positive and negative inputs.
60 Hz common mode input becomes a problem in this
configuration and a transformer with an electrostatic
shield between primary and secondary windings is shown.
The necessity for using a shielded transformer depends
on the performance requirements and the actual application.
The filter capacitors connected to V FB (pin 14) and
V FLT (pin 11) should be low leakage. In the application
examples shown every 1.0nA of leakage current wi"
cause 0.1 mV error (1.0x 1O- 9 A x 100kn = 0.1 mV).
If the leakage current in both capacitors is exactly the
same, no error wi" result since the source impedances
driving them are matched.

To prevent switching noise from causing jitter problems,
a voltage regulator with good high frequency response
is necessary. The LM309 and the LM340-5 voltage
regulators both function well and are shown in figures
4, 5, and 6. Adding more filtering than is shown wi" in
general increase the jitter rather than decrease it. The

1-154

RAOI-4l

.....

~

1
3iomX

:>

,

ILM309

LM03~O.5

t-

TTr

~

1\

POWERGNO>---------------------~~--_+--~--~----~I7I~~~----~-J

....

....

1\

1\

"i.

1" "

IVss

•

r-

~~~--~------------+----------

.:...
U1
U1

~
I

I

~

~

28

18 .

11
c'"

;z

<

Z

::c

I

ZZMr2

L__

:

__J

§

g

~

~

8

z
'"
c

lOOk

MM74C935

~

n

GND
SIGNAL

o

.IDJUST
OFFSET (5)

<

.~

z

~

<

<

Z

....

z

en

~

n ....

~

~~ §~

'"
'"
11

<

a.

n

II
I"~~,,!,"
~---==d-~====--=
918

Fill

3

1

<
n

IZ

II

-I!

IO"F
IOVDC

(3)

lOOk

T

OV~~:»------------------------------------------------------------______~----~

+1.999 V

NOTES:

I. All RESISTORS '4 VlATT ± 5% UNLESS OTHERWISE
SPECIFIED.
4.~=R3±Z5l!
Z. All CAPACITORS .10'10.
3. LOW LEAKAGE CAPACITOR REnUIRED.
5. OFFSET ADJUST REOUIRED FOR MM14C9l5·1 ONLY.

Figme 4. 3%-Digit DPM, +1.999 Volts Full Scale

(L09EOOV/009EOOV)· L-9E6:lvLII\I 11\1/9 E63vLII\I 11\1

MM74C935/MM74C935-1 (ADD35001 ADD3501)

2]1
MM74C935

NOTES:
1. ALL RESISTORS %WATT. 5% UNLESS OTHERWISE
2.

~LELC~~!~~ITORS .10'''.

3. LOW LEAKAGE CAPACITOR REOUIREO.

Figure 5. 3Y>·Digit DPM, ± 1.999 Volts Full Scale

4.

R~~R~2 = R3 ± 25n

5. OffSET AOJUST REOUIRED FOR MM74C935·1 ONLY

RADa -4J

U1

......

MM74C935
GUARD:

VI')

NOTES:
1. SPECIFIED.
ALL RESIST ORS ~ WATT! 5% UNLESS
2. ALL CAPAC ITO
OTHERWISE
3. LOW LEAKAGE

~~;~D';'.

CITOR REOUIRED.

RI + R2 • RJ! 25n
4. ..!!!!!Z..
5. OFFSET ADJUST REQUIRED FOR MM74C9J5-1 ONLY.

VI-)

Figure 6.

3~-Digit

DVM, Four Decade. ±0.2 V. ±2 V. ±20 V and ±200 V Full Scale

(L09£00V1005£00V) L-5£6~vLII\III\I/5£6~vLII\III\I

co
M
en

Advance Information

CJ

~

~
~

~

en

CJ

~
~

~

cD

~

MM74C936 3%-digit DVM with multiplexed 7-segment output
MM74C937 3%-digit DVM with multiplexed BCD output
MM74C938 3%-digit DVM with multiplexed BCD outpu~

CJ

~

~
~

general description
The MM74C935 family of monolithic DVM circuits is
manufactured using standard complementary MOS
(CMOS) technology. A pulse modulation analog-to·
digital conversion. technique is used and requires no
external precision components. In addition, this technique allows the use of a reference voltage that is the
same polarity as the input voltage.

A start conversion input and a conversion complete
output are included on all 4 versions of this product.

features

One 5V (TTL) power supply is required. Operating
with an isolated supply allows the conversion of positive
as well. as negative voltages. The sign of the input voltage
is automatically determined and output on the sign pin.
If the power supply is not isolated, only one polarity of
voltage may be converted.

• Operates from single 5V supply

The conversion rate is set by an internal oscillator. The
frequency of the oscillator can be set by an external
RC network or the oscillator can be driven from an
external frequency source. When using the external RC
network, a square wave output is available. It is important to note that great care has been ·taken to synchronize digit multiplexing with the AID conversion timing
to eliminate noise due to power supply transients.

• BCD versions easily interfaced to microprocessors or
other digital systems

The MM74C936 has been designed to drive 7-segment
multiplexed LED displays directly with the aid of
external digit buffers and segment resistors. Under
condition of overrange, the overflow output will go
high and the display will read +OFL or -OFL, depending
on whether the input voltage is positive or negative. In
addition to this, the most significant digit is blanked
When zero.
The MM74C937 and MM74C938 have been designed to
output multiplexed BCD digits and are intended for use
with microprocessors and other digital systems. BCD
digits are output on demand via 2 Dig;"t Select (DSO,
DS1) inputs. Digit Select inputs are latched by a low·tohigh transition on the Digit Latch Enable (OLE) input
and will remain latched as long as OLE remains high.

• Converts OV to ± 1.999V or OV to ±3.999V
• Multiplexed 7-segment or BCD outputs
• Drives segments directly
• No external precision component necessary

• Medium speed - 200 mslconversion
• All inputs and outputs TTL compatible'
• Internal clock set with
externally

RC netwo"rk or driven

• No offset adjust required
• Overrange indicated by +OF!- and -OF L disp"lay
reading

applications
• Low cost digital power supply readouts
• . Low cost digital multimeters
• Low cost digital panel meters
• Eliminate analog multiplexing by using remote AID
converters
• Convert analog transducers (temperature, pressure,
displacement, etc.) to digital transducers

1-158

Advanced Information

MM74C948 CMOS 8-bit AID converter with 16-channel analog multiplexer
MM74C949 CMOS 8-bit AID converter with a-channel analog multiplexer
MM74C950 CMOS 8-bit AID converter with 8-channel analog multiplexer
and sample and hold

general description
selected channel is. compared to the voltage' at the'
appropriate tap of the voltage divider, selected by the
analog switch tree. At the end of conversion, the 8-bit
true binary word corresponding to the unknown voltage
is latched into the 8-bit latch with Tri-State output.

The MM74C948/MM74C949/MM74C950 is a monolithic 8-bit A/D converter employing CMOS technology.
It contains a multi-channel analog multiplexer, a high
input impedance comparator, successive approximation
registers, control logic, voltage divider, analog switch
tree, and an 8-bit latch with Tri-State outputs. A reference voltage is applied across the voltage divider, which
has 256 resistors in series, and 256 taps (formed at
each resistor junction) are connected to the top side of
the analog switch tree; the bottom end of the analog
switch tree is connected to the input of the comparator. Conversion is performed using successive approximation technique, where the unknown voltage from the

features
•

Supply Range, V ee - Vss

•

Reference Voltage REF(+)
REFH
Tri-State Output with
TTL Compatibility

•
•

4.5V to 5.5V
Vee
Vss
drive 1 TTL load

Monotonicity

connection diagrams
IN3
IN4
IN5
IN6
IN7
IN8
IN9
IN10
INll
IN12
IN13
IN14
E.D.C.
IN15
COMMON
ClK
START
VCC
COMPARATOR IN
+REF

IN3
IN4
IN5
IN6
IN7
SIH
E.O.C.
OD
TRI·STATE
CLK
vCC
+REF
VSS
Oc

28

MM74C950

10
11
12
13
14
15
16
17
18
19
20

40
39
28
37

IN2
INI
INO
EXPANSION CONTROL

36

ADD.A
ADD. B
ADD. C
ADD. D
A.L.E.
OH
OG
OF
OE
OD

MM74C948

,Uc
Os
OA
-REF
TRI·STATE
21

IN2
INI
INO
ADD.A
ADD. B
ADD. C
START

VSS

28
27

IN3
IN4
IN5
IN6
IN7
START
E.O.C.
00
TRI·STATE
CLK

°H
°G
OF
OE
OA
-REF
OB

MM74C949

VCC
+REF
VSS
Oc

1-159

14

IN2
INI
INO
ADD.A
ADD.B
ADD. C
A.L.E.
OH
OG
OF
OE
OA
' -REF
OB

definition of terms
Start: When "start" goes high it resets the SAR. Conversion begins when '~start" goes low. If "start" is
reinitiated during conversion the conversion sequence
starts over.

Outputs: OA is LSB, QH is MSB.
Address: ADD A is LSB, ADD 0 is MSB.
Expansion Control: Active low. It disables internal
muJtiplexedanalog channels.

For MM74C950, the "start" will also function as Address
Latch Enable and Expansion Control, and the converter
will be at sample mode when it is "high."

Clock: Connection to external clock.
Tri-State Control: Logic state, when it is "high," TriState when it is "low."

E.O.C.: "High" when conversion is completed, "low"
during conversion.

Comparator In: Signal input to the comparator.

Address Latch Enable: Active at "low to high" transition.

Common: The common node of 'the multiplexed analog
channels.

Note 1: For MM74C950 only, StH is the pin where the comparator IN and common are connected together internally.

block diagram

,START

COMPARATOR IN

CLOCK

COMMON

ENO OF CONVERSION

16 ANALOG INPUTS

16 CHANNELS
MULTIPLEXING
, ANALOG
SWITCHES

ADDRESS
OECODER
ADDRESS LATCH ENABLE
EXPANSION CONTROL

REF-

1-160

TRI·
STATE
CONTROL

black diagrams (cant.)

CONTROLS FROM S.A.R.
I

+REF

.

TO
COMPARATOR
INPUT

256R :

-REF

RESISTOR LADDER AND SWITCH TREE

switching time wavefarryls

VCC
CLOCK
START
ALE

VSS

~~--------------~((~------------­
~----------------~C2~-------------

VCC

x:::x-----~r
I-

VSS

I-STABLE1

ADDRESS

VCC

_

STABLE

VSS
VSS
VCC

VCC

INPUTS

VSS
TRI-STATE
CONTROL

--------------------~l~
1""~

11-----

E.O.C.

64 CLOCK PULSES

TRI-STATE

OUTPUTS

-

-

-

It

~ - - . - - - - - - ~2-

1-161

VCC
VSS

I
-----II.~ OUTPUT VALID
",,1-

,._ _ _

-<

,•

X___

VCC
VSS
VCC

Vss

co

0)

CJ

o

CO

:!
:!
.......
CO

0)

CJ

o

.....
:!
:!
CD

0)

CJ

o

co
:!
:!
.......
CD

0)

CJ

o

.....
:!
:!
r'
0')

CJ

MM70C95/MM80C95,MM70C97/MM80C97 TRI-STATE® hex buffers
MM70C96/MM80C96,MM70C98/MM80C98 TRI-STATE® hex inverters

general description
Inputs are protected from damage due to static discharge
by diode clamps to V cc and GND.

These gates are monolithic complementary MOS
(CMOS) integrated circuits constructed with Nand Pchannel enhancement mode transistors. The MM70C95/
MM80C95 and the MM70C97/MM80C97 convert
CMOS or TTL outputs to TRI-STATE outputs with
no logic' inversion, the MM70C96/MM80C96 and the
MM70C98/MM80C98 provide the logical opposite of
the input signal. The MM70C95/MM80C95 and the
MM70C96/MM80C96 have common TRI-STATE controls for all six devices. The MM70C97/MM80C97 and the
MM70C98/MM80C98 have two TRI-STATE controls;
one' for two devices and one for the other four devices.

connection diagrams

features
•
•

Wide supply voltage range
Guaranteed noise margin

•

High noise immunity
TTL compatible

II

3.0V to 15V
1.0V
0.45 Vee (typ)
Drive 1 TTL Load

applications
•

Typical propagation delay
into 150 pF load is 40 ns

Bus drivers

(Dual-In-Line and Flat Packages)

o

CO

::2!:

:!

MM70C95/MM80C95
Vee

MM70C96/MM8OC96

OIS,

IN,

OUT.

IN,

OUT,

IN,

OUT,

Vee

DIS 2

IN,.

IN,

OUT,

IN,

OUT 2

IN,

OUT,

GNO

DIS,

IN,

OUT,

OUT.

INs

OUT,

IN,

OUT,

IN,

OUT,

IN,

OUT,

GNO

OUT,

.......

.....

0)

CJ

o

.....
:!
:!

OIS,

TOPVIEW

TOPVIEW

MM7OC97/MM80C97
Vee

DIS,

IN,

OUT.

OIS,

IN,

OUT,

IN,

MM70C98/MM80C98

IN,

OUT.

IN,

OUT,

IN,

OUT,

OUT,

Vee

0lS2

IN,

OUT,

GNO

OIS,

IN,

OUT,

IN,

TOPVIEW

IN,

OUT,

IN,

OUT 2

IN,

OUT,

TOPVIEW

1-162

GNO

absolute maximum ratings
\

3:
3:

(Note 1)

......

0

(")

Voltage at Any Pin
Operating Temperature Range
MM70CXX
MM80CXX

(D

0.3V to Vee + 0.3V

(J"I

"-

3:
3:

-55°C to +125°C
0
-40 Cto +85°C

00

Storage Temperature Range
Package Dissipation
Power Supply Voltage (Vee)
Lead Temperature (Soldering, 10 seconds)

0

-65°C to +150°C
500mW
18V
300°C

(")
(D
(J"I

3:
3:
......
0

dc electrical characteristics

(")

Minimax limits apply across temperature range unless otherwise specified.

(D

......

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

CMOS TO CMOS
V IN (,)

Logical "1" Input Voltage

Vee = 5.0V

3.5

Vee = 10V

B.O

VIN(O)

Logical "0" Input Voltage

V OUT (,)

Logical "1" Output Voltage

VOUT(O)

Logical "0" Output Voltage

Vee = 5.0V

IIN(')

Logical "1" I nput Current

Vee=15V

Logical "0" Input Current
Output Current in High Impedance State

4.5

Vee = 10V

9.0
0.5

0.005
-1.0

Vee = 15V, Vo = 15V
Vee = 15V, Vo = OV

Icc

Supply Current

Jl.A

2.0

Vee = 5.0V

Vee = 10V

lOUT

1.0

1.5

Vee = 5.0V
Vee = 10V

IIN(O)

1.0

v
v
v
v
v
v
v
v

-D.005
0.005

-1.0

-0.005
0,01

Vee = 15V

Jl.A
1.0

Jl.A
Jl.A

15

Jl.A

TTL INTERFACE
V IN (1)

VIN(O)

V OUT (,)

VOUT(O)

Logical "1" Input Voltage

Logical "0" Input. Voltage

Logical "1" Output Voltage

Logical "0" Output Voltage

Output Source Current

IsouReE

Output Source Current

MM70C

Vee = 4.5V, 10 = -1.6 rnA

2.4

MMBOC

Vee = 4.75V, 10 = -1.6 rnA

2.4

MM70C

Vee = 4.5V, 10 = 1.6 rnA

0.4

v
v
v
v
v
v
v

MMBOC

Vee =4.75V, 10 = 1.6mA

0.4

v

V ee -l.5
V ec -l.5

MM70C

Vee = 4.5V

MMBOC

Vee = 4.75V

MM70C

Vee = 4.5V

O.B

MMBOC

Vee = 4.75V

O.B

Vee = 5.0V, V IN (,) = 5.0V
TA

= 25°C, YOUT

-4.35

rnA

-20

rnA

= OV

Vee = 10V, V IN (,) = 10V

Output Sink Current

Vee = 5.0V, VIN(O) = OV

4.35

rnA

20

rnA

TA = 25°C. V OUT = Vee
ISINK

Output Sink Current

00

0

('")
(D

~......

s:
s:......
0

('")
(D

en

"-

s:

s:00
0

Vee

= 10V, VIN

= OV

TA = 25°C, V OUT = Vee
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. ~xeept for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: CpO determines the no load ac power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics
application note, AN-90.

1-163

(D

en

s:
s:......

0

('")
(D

00

"-

s:
s:
00
0

('")
(D

TA = 25°C, V OUT = OV
ISINK

3:
3:

('")

. OUTPUT DRIVE CURRENT
IsouReE

"-

CO

ac electrical characteristics

T A = 25°C, CL = 50 pF, unless otherwise noted
CONDITIONS

PARAMETER
I nput Capacitance

COUT

Output Capacitance T R I·ST A TE

Cpo

Power Dissipation Capacity

tpdO

Propagation Delay Time to a Logical "0"

tpdl

or Logical "1" From Data Input to Output

MM70C96/MM80C96, MM70C98/MM80C98

pF

Any Output (Note 2)

11.0

pF

(Note 3)

60

pF

Vee

= 5V

60

100

ns

Vee

= 10V
= 5V
= 10V

25

40

ns

70

150

ns

35

75

ns

Vee
Vee

Propagation Delay Time to a Logical "0"

tpdl

or Logical "1" From Data Input to Output
MM70C95/MM80C95, MM70C97/MM80C97
MM70C96/MM80C96, MM70C98/MM80C98

= 5V,
= 10V,

Delay From Disable Input to High Impedance

tOH

State, (From Logical "1" or Logical "0")

= 150pF
= 150 pF
= 150pF
= 150pF

85

160

ns

80

ns

95

210

ns

45

110

ns

80

135

ns

50

90

ns

Vee = 5V

100

180

ns

= 10V
Vee = 5V

70

125

ns

70

125

ns

Vee = 10V

50

90

ns

Vee = 5V

90

170

ns

Vee = 10V

70

125

ns

120

200

ns

Vee = 5V,

Cl
Cl

= 10V, Cl
Rl = 10k,C l = 5 pF

Vee
tlH,

Cl

40

Vee
Vee

MM70C95/MMSOC95

\

Vee = 5V
Vee

MM70C96/MM80C96

= 10V

Vee
MM70<;97/MM80C97
MM70C9S/MMSOC98

tHl,

Delay From Disable Input to Logical "1" Level

tHO

(From High Impedance State)

Rl

= 10k, Cl

= 50 pF

'.

MM70C95/MM80C95

Vee = 5V

MM70C97/MM80C97
MM70C98/MM80C98

= 10V

50

90

ns

Vee = 5V

130

225

ns

Vee = 10V

60

110

ns

Vet = 5V

95

175

ns

Vee = 10V

40

80

ns

Vee = 5V

1.20

200

ns

Vee.= 10V

50

90

ns

Vee
MM70C96/MM80C96

truth tables
MM70C96/MM80C96

MM7OC95/MM80C95

DISABLE
DIS1

0
0

INPUT
DIS 2

0
·0

0

1

1
1

0
1

INPUT
0
1
X
X
X

OUTPUT
0
1
H·z
H-z
H-z

DISABLE
DIS1

INPUT
DIS2

INPUT

0
0
0

0

0

1

0

0

1
1

0
1

1
X
X
X

MM70C97/MM80C97

DISABLE
DIS4

INPUT
018 2

0
0

0
0
1
X

X
1

UNITS'

.'

M M 70C95/M M80C95, M M 70C97 1M Mso'C97

tpdO

MAX.

5.0

. Any Input (Note 2)

CIN

I

TYP

MIN

H-z
H-z
H-z

MM7OC98/MM8OC98

INPUT

OUTPUT

0

0
1
H-z *
H-z**

1
X
X

1

OUTPUT

DISABLE
DIS 4

INPUT
DIS2

0
0

0
0
1
X

X
1

*Output 5-6 only
"Output 1-4' only
X = Irrelevant

1-164

INPUT

OUTPUT

0
1
X

1
0
H-z*
H-z**

X

s:
s:
......

typical performance characteristics
Propagation Delay
Load Capacitance
150

r

Vee' 3.0~

]

,

>

g

1 1

i

II 1 II

~

Vee~

~

~

to>

I

-n
~

-

0.50

s:
s:

ex)

1\
\

~

~

LAo
Q

o

(")

U1

...

to-

s:
s:......

1'-1-

~

:1

150

100

U)
0.25

LAo

1 1 Vee '15V - - r 50

CL

~

-_....

Vee -10V ....

.J

U1

.......

·'TA' . ~5JC I
I.. It • 20 ns

CI

II

50

g;

U)

Z

~

...

J

~

0.75

w

J

~

(")

Power Supply Voltage

TA • 25'C
SEE AC TEST CIRCUIT

100

o

~tpd/pF VI

VI

10

5.0

LOAD CAPACITANCE (pF)

15

o

Vee -POWER SUPPLY VOLTAGE (V)

(")

U)

......

.......
N-Channel Output Drive

@

25°C

P·Channel Output Drive

100
90

,

80
70

<
.s

I

50

"z

~

20
10

o

<
.s

Vee ·l0V

j

~

J

40
30

I

,

1..1

~~ ~·15VI

o

r-

-20

LI

60

s:
s:

25°C

Ve~ ='5V ~

-10

Vee '15V

@

Ve~ .',dv

-30

1-1--1--'

-40

""

I

ex)

~~

o

"

~......

(")

U)

s:

~

-50

J:H1-

-60
-70

s:

~~

......

o

(")

-80
2

4

6

8

10

12

14

16

16

14

VOUT (V)

12

10

8

6

4

2

U)
C')

0

.......

Vee;" VOUT (V)

s:
s:

schematic diagrams

ex)

o

MM70C95/MMBOC95 TRI·STATE

MM70C96/MM80C96 TRI·STATE

ONE Of SIX DEVICES

INiI

-=--=-~+-I...... --.,~

o--_-+-r-..r_.

-f'-L

CONTROLS FOR ALL
SIX DEVICES
DISII

15

J

,

~

n-""-..--.....

DISIZ

Vee

IL _ _ _ _ _ _

I
I
~

r------"l

I

II
I

U)

ONE OF SIX DEVICES

r------"l

I

(")

I

I

IN/I o-----+~
3

00'11

oISiI

111

",'.;.,.".L.-.r-.....

J
Vee

J

1

DISlZo-.,....._'
15

~

I

s:
s:
......

I
II

3

OOPII

.......

s:
s:

I

IL _ _ _ _ _ _ ..J

L -_ _ _ _ _ ..J

o

(")
U)
ex)

ex)

o

(")

U)
ex)

MM70C97/MMBOC97 TR I·STATE

MM70C9B/MMBOC9B TRI-STATE

ONE OF TWO/FOUR DEVICES

ONE OF TWO/fOUR DEVICES

r------"l

I

INII

-=-~+-I,-+ --.,~

0--_--+-,...:....
..'[._.
__

-f'-L

r--OISlZ

I

IL _ _ _ _ _ _ I
~

I

IL

J
Vee

J

r------"l

I

I

I
I
I

~ II

I

0-----.. . .
2

INII
3

-1

DISl2

IL _ _ _ _ _ _
1-165

J
J

00'/1

_ _ _ _':"
_ _ ..J

Vee

I

~

I

I
I
I

1I

IL _ _ _ _ _ _ ..J

3

o OPII

co

~

o
co

ac test circuits and switching time wavefonns

~
~

.........

CMOS to CMOS

tpdO. tpdl

co

en
U

o
,....
~
~
CD

Vee

D.9

D.9

Y,N

V'"~VOO'

en

0.1

~~

CL = 50 pF

'CJ

T'

o

co

0.1

DV

Vee

~
~

~}

50%

VOUT

50%

DV

.........

CD

en

CJ

o
,....
~
~

Vee

I N P U T - Q - " - r T OUTPUT

"""'-1'·" J

-1

0.5 Vee

DISABLE

OV

",,'" ':

t'H

C,·5.'

~'.5

-=t:=t

OUTPUT

0.5 Vee
OV----,---,--

DV - - - -_ _--.:;:_ _

I.C)

en'

CJ

o
co

tOH and tHO

.........
I.C)

en

CJ

o
,....
:E
~

tOH

""'" ~
T
INPUT

~

tHO

Vee

Vee

Vee

DISABLE

DISABLE

OV

DV

Vee

Vee

OUTPUT

tHO

C,· 5.'
OUTPUT

-,

OV

0.1 Vee

Note: Delays measured with input t., It :::; 20 ns

1-166

.

Vee - - - - - + - , - -

Vee ---~
OUTPUT

~
~

Vro

OUTPUT

OV

MM78C29/MM88C29 quad single ended line driver
MM78C30/MM88C30 dual differential line driver
general description
The MM78C30/MM88C30 is a dual differential line
driver that also performs the dual four-input NAND or
dual four-input AND function_ The absence of a clamp
diode to Vee in the input protection circuitry allows a
CMOS user to interface systems operati ng at different
voltage levels_ Thus, a CMOS digital signal source can
operate at aVec voltage greater than the Vcc voltage
of the MM78C30 line driver. The differential output of
the MM78C30/MM88C30 eliminates ground·loop errors.

typ, the device can be used to drive lamps, relays,
solenoids, and clock lines, besides driving data lines.

The MM78C29/MM88C29 is a non-inverting single-wire
transmission line driver with a similar input protection
circuit. And since the output ON resistance is a low 20n

•

features
• Wide supply voltage range

3.0V

High noise immunity

to

15V

0.45 Vee typ

• . Low output ON resistance

20n typ

logic and connection diagrams
112 MM78C30/MM88C30
Vee

INPUT 1

1/4 MM78C29/MM88C29

INPUT 2
INPUT 3

Vee

INPUT 4

AND
OUTPUT

INPUT
OUTPUT

NAND
OUTPUT

MM78C30/MM88C30

MM78C29/MM88C29
Vee

1,4

NC

NC

13

12

11

IN,

10

OUT,

OUT.

9

B

1
NC

Vee

}'14

2

3
NC

13

12

11

IN..

10

BAND
OUT

4

5

6

17

IN,

OUT,

OUT,

GNO

1

2

J

4

TOP VIEW

1-167

8

f--

1Nu

TOP VIEW

BNANO
OUT

9

-

to-

IN,

IN",

IN,.

5
A AND
OUT

6

A NAND
OUT

}

GNO

o

M
CJ

CO
CO

:E
:E
......
o

M

CJ

~
:E
:E

absolute maximum ratings
Voltage at Any Pin
Operating Temperature Range
MM78C29/MM78C30
MM88C29/MM88C30
Storage Temperature Range
Package Dissipation
Operating Vee Range

Absolute Maximum Vee
Average Current at Vee and Ground
Average Curre.nt at Output
MM78C30/MM88C30
MM78C29/MM88C29
Maximum Junction Temperature, T j
Lead Temperature (Soldering, 10 seconds)

-55°C to +125°C
-40°C to +85°C
-65°C to +150°C
500mW
3.0V to 15V

dc electrical characteristics
PARAMETER

(Note.1)

-o.3V to +16V

18V
100mA
50mA
25mA
150°C
300°C

Min/max limits apply across temperature range, unless otherwise noted.
CONDITIONS

MIN

TYP

MAX

. UNITS

CMOS TO CMOS
3.5
8.0

Logical "1" Input Voltage (V IN (1))

Vee = 5.OV
Vee = lOV

Logical "0" Input Voltage (VIN(O))

Vee = 5.OV
Vee = 10V

Logical "1" Input Current (lIN(1))

Vee = 15V, VIN = 15V

Logical "0" Input Current (lIN(O))

Vee = 15V, VIN = OV

Supply Current (Icc)

Vee = 15V

V
V

0.005
. -1.0

1.5
2.0

V
V

1.0

J.l.A

-0.005
0.05

J.l.A
100

J.l.A

OUTPUT DRIVE
Output Source Current
MM78C29/MM78C30

MM88C29/MM88C30

MM78C29/MM88C29
MM78C30/MM88C30
Output Sink Current
MM78C29/MM78C30

MM88C29/MM88C30

Output Source Resistance
MM78C29/MM78C30

MM88C29/MM88C30 .

V OUT = Vee -1.6V,
Vee ~ 4.5V, T j = 25°C
T j = 125°C

-57
-32

-80
-50

mA
mA

V OUT = Vee -1.6V,
Vee '2:: 4.75V, T j = 25°C
T j = 85°C

-47
-32

-80
-60

mA
mA

-2

-20

mA

V OUT = OAV, Vee = 4.50V
T j = 25°C
T j = 125°C

11
8

20
14

V OUT = OAV, Vee = lOV
T j = 25°C
T j = 125°C

22
16

40

V OUT = OAV, Vee = 4.75V
T j = 25°C
T J = 85°C

9.5
8

22
18

mA
mA

V OUT = OAV, Vee = 10V
T j = 25°C
T j = 85°C

19
15.5

40

mA
mA

V OUT = Vee- 0.8V
Vee> 4.5V

mA
mA
mA
mA

28

33

V OUT = Vee -1.6V,
Vee ~ 4.5V, T j = 25°C
T j = 125°C

20
32

28
50

V OUT = Vee -.l.6V,
Vee ~ 4.75V, TI = 25°C
T j = 85°C

20
27

34
50

1·168

n

n
f2

n

~

dc electrical char'lcteristics (con't)
PARAMETER
Output Sink Resistance
MM78C29/MM78C30

MM88C29/MM88C30

CONDITIONS

MIN

20
28

36
50

n
n

V OUT = O.4V, Vee = 10V
T j = 25°C
T j =125°C

10
14

18
25

n
n

V OUT = O.4V, Vee = 4.75V
T j = 25°C
T j = 85°C

18
22

41
50

n
n

V OUT = O.4V, Vee = 10V
T j = 25°C
T j = 85°C

10
12

21
26

I

n
n
%/oC

0.55
0.40

%tc

100

°C/W

150

°C/W

T A = 25°C, C L = 50 pF
CONDITIONS

MIN

TYP

MAX

UNITS

80
35
110
50

200
100
350
150

ns
ns
ns
ns

(See Figure 2)

Vee
Vee
Vee
Vee

= 5V
= lOV
= 5V
= 10V

Power Dissipation Capacitance (Cpo)
M M 78C29/M M88C29
MM78C30/MM88C30

(Note 3)
(Note 3)

150
200

pF
pF

Input Capacitance (C IN )
MM78C29/MM88C29
MM78C30/MM88C30

(Note 2)
(Note 2)

5.0
5.0

pF
pF

Differential Propagation Delay Time
to Logical "1" or "a ..
MM78C30/MM88C30
-,

co

(")

.........

~
~

CO
CO

(")

N
CD

~

~
.....

CO

(")

W
0

.........

PARAMETER

MM78C30/MM88C30

UNITS

V OUT =O.4V, Vee =4.5V
T j = 25°C
T j = 125°C

Thermal Resistance,OjA
MM78C29/MM78C30
(D-Package)
MM88C29/MM88C30
(N·Package)

Propagation Delay Time to Logical "1"
or "0" (t pd )
MM78C29/MM88C29

MAX

N
CD

Output Resistance Temperature
Coefficient
Source
Sink

ac electrical characteristics

TYP

3:
.....

lOOn,

RL =
C L = 5000 pF
(See Figure 1)
Vee = 5V
Vee = 10V

400
150

ns
ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: CPD determines the no load ac power" consumption of any CMOS device. For complete explanation see" 54C174C Family Characteristics
application note, AN-90.

1-169

~
~

CO
OJ
(")

W
0

o

M

CJ

typical performance characteristics

CO
CO

:E
:E
.........

!

115

CO

g

105

":E:E

MM78C29/MM88C29

Typical Propagation Delay vs
Load Capacitance

Typical Propagation Delay vs
Load Capacitance

125

0'
M,

CJ

MM78C29/MM88C29

g:

75

>-

g

~

z

~

Tj -25'C , Vee -10V

65

!

~

95
85

~

~

>-

;g
;::
:;,
~

10

~

Tj - 25"C
Vee - 5V

M

~pd'

]

1/

50
45

~

40

/
/

35

/

/'

l/

>-

g'

....... 1--'"

~

z
Q

-~f-

;::

:;

~

~

3D
400'

600

800

LOAD CAPACITANCE, Cl

140

~

" f--r-

..........'pdO

130

/V'

'/

110
100
90

~

200

...,.

i...o'"
~

Ipd'

120

~

I

150

/'"

55

;::

:;

,~

160

f-r~ ~~:::

60

Q

Ipd~

MM78C30/MM88C30
Typical Propagation Delay vs
Load Capacitance

1000

200

400

600

BOD

LOAD CAPACITANCE, Cl

(pF)

200

1000

400

600

800

LOAD CAPACITANCE, Cl

(pF)

1000

(pF)

MM78C30/MM88C30

Typical Propagation Delay vs
Load Capacitance

Typical Sink Current vs
Output Voltage

90

500
Tj

85

!

80

g

15

>z

Q

,

~

65

~

60
55
50

V

/'"

,. .......

;/

~=-

/ VI/
400

300

5

200

~

600

LOAD CAPACITANCE, Cl

800

Vee -IOV

oS 400

--

./

I-

"0

300

/

5

'1

~

"
~" ~V;::5V

1000

'/

~ Vee - 5V

200
100

V

I I I
I I
I I

;'

I I

10

12

14

8

TYPICAL VOUT (V)

(pF)

"1 I I

~

Vee -10V f-

J~

Veel=I~t1'

TJ - 25'C_,.-

SOD

J

~
E

100

~

200

400

j

600

ve -15V

I..-

25'C

,I

10

;::

:;

~"".> ~~

-

Typical Source Current vs
Output Voltage

ac test circuits
Vee

'n~,~'

~

.1
t2
VIN~

DV
VA-V.

FIGURE 1.

Vee

Vee
14

AND
OUTPUT

","u{

1/4 MM18CZ9

OUTPUT

ICl

-=

-=
FIGURE 2.

1-170

10

12

TYPICAL Vee-VOUT (V)

14

typical applications
Digital Data Transmission
Cl
O.OI~F

(NOTE 1)
Vee

LINE DRIVER AND RECEIVER (NOTE 31

OUTPUT

Note1: Exact value depends on line length.
Note2: Optional to control response time.
Nole 3: Vee 10 4.5V 10 5.5V for Ihe OS7820.

STR{) BE

Vee
Vee

' ',,[

OUTPUT

-=

Vee
Vee

SINGlE·WIRE TRANSMISSION LINE (NOTE II
14

INPUT

1/SMM78C291
MM88C29

OUTPUT
OUTPUT

-=

Note I: Vee is JVto 15V
':"

Typical Data Rate vs Transmission Line Length
10,000

~

...

~TA=25"C

"c:r~~f

1000

v.

~;J~

~

;:

100

~c ~

~

l

10

100

~

1000

LENGTH OF TRANSMISSION LINE (FT)

Note1: The transmission line used was #22 guage unshielded twisted pair
(40k terminalion).

Note 2: The turves generated assume that both drivers are driving equal .
lines, and that the maximum power is 500 mW/package.

1·171

(")

C

~

o
o
o

,s:
(")

C

~

o
o
o

(")

CD4000M/CD4000C dual 3-input NOR gate plus inverter

general description

features

The CD4000M/CD4000C is a monolithic complementary
MOS (CMOS) dual 2-input NOR gate plus an inverter.
N- and P-channel enhancement mode transistors provide
a symmetrical circuit with output swings essentially
equal to the supply voltage. This results in high noise
immunity over a wide supply vOlta'ge range. No dc
power other than that caused by leakage current is
consumed during static conditions. All inputs are protected against static discharge and latching conditions.

•

Wide supply voltage range

•

Low power

•

High noise immunity

3.0V to 15 V

10 nW (typical)

0.45 V DD typical

schematic and connection diagrams
Voo
14

3

11

r---.-----------------oo

Ao---------------~~r_----.

12

4

r---+_----~~--------oE

Bo---------~------+_~

13

5

r---+_----~~----~--oF

Co--e------~------+_~

I!NC

2~NC

7

Vss

6

H

8

9

G

10

L

K

Vss

Voo
14

NC

13

Vss

A

2-3

u

0
0
0

~

C

U
.......

:E

0
0
0

~

C

absolute maximum ratings

(Note 1)

Voltage at Any Pin
V55 -0.3 V to VOO + 0.3 V
Operating Temperature Range
-55°C to +125°C
CD4000M
_40°C to +B5°C
CD4000C
-65°C to +150°C
Storage Temperature Range
"Package Dissipation
500mW
Operating Voo Range
V 55 + 3 V to V 55 + 15 V
300°C
Lead Temperature (Soldering, 10 seconds)

"

U

dc electrical characteristics-CD4000M (Note 2)
_55°C
CONDITIONS

PARAMETER

MIN

-

MAX

+25°C
MIN

TVP

+125"C
MAX

MIN

Voo = 5V
Voo = 10V

0.05
0.1

0.05
0.1

3
6

VOL Low Level Output Voltage Voo = 5 V
Voo= 10V

0.05
0.05

0.05
0.05

0.05
0.05

Quiescent Device Current

100

VOH High Level Output Voltage Voo = 5V
Voo= 10V

UNITS

MAX

I1A
pA
V
V

4.95
9.95

4.95
9.95

4.95
9.95

V
V

VNL Noise Immunity (Note 3)

Voo=5V, Vo = l.4V or 3.6V
Voo = lOV, Vo ~ 2.BV or 7.2V

1.5
3.0

1.5
3.0

1.4
2.9

V
V

VNH Noise Immunity (Note 3)

Voo=5V, Vo = l.4V or 3.6V
Voo = 10V, Vo = 2.8V or 7.2V

1.4
2.9

1.5
3.0

1.5
3.0

V
V

ION

Low Level Output Current Voo~5V, VO=O.4V
Voo = 10V, Vo = 0.5V

0.5
1.1

0.4
0.9

0.28
0.65

mA
mA

lop

High Level Output Current Voo=5V, Vo = 2.5V
Voo=10V,VO=9.5V

-0.62
-0.62

-0.5
-0.5

-0.35
-0.35

mA
mA

liN

Input Current

-1.0

Voo = 15V, VIN = OV
Voo = 15V, VIN = 15V

-0.1

-10. 5

10- 5

1.0

-1.0

I1A
pA

1.0

0.1

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Tempera"ture Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical
Characteristics" provides conditions for actual device operation.
Note 2: VSS = OV unless otherwise specified.
'
Note 3: For the NOR gates VNH and VNL are tested at each input while ali other inputs are at V5S.
Note 4: CpO determines the no load AC power consumption of any CMOS device. For explanation see 54C174C Family Characteristics
application note, AN·90.

ac electrical characteristics- CD4000M
PARAMETER

T A = +25°C, C L = 15 pF, unless otherwise specified.
CONDITIONS

MIN

TVP

MAX

UNITS

tpHL

Propagation Delay Time, High to Low Level

Voo = 5 V
Voo=10V

40
20

50
40

ns
ns

tpLH

Propagation Delay Time, Low to High Level

Voo = 5 V
Voo= 10V

50
25

95
45

ns
ns

tTHL

Transition Time, High to Low Level

Voo = 5V
Voo = 10V

50
20

125
70

ns
ns

tTLH

Transition Time, Low to High Level

Voo = 5 V
Voo = 10\1

70
35

175
75

ns
ns

CI

I nput Capacitance

Any Input

5

pF

CPO

Power Dissipation Capacitance

(Note 4)

35

pF

2·4

(")
~c

electrical characteristics- C4000C

C

(Note 2)

,J::a.
_40°C

PARAMETER
100

Quiescent Device Current

CONDITIONS

MIN

VOO = 5 V
VOO= 10V

VOL Low Level Output Voltage Voo = 5V
Voo=10V

MAX

+25°C
MIN

TYP

+85°C
MAX

MIN

MAX

0.5
5

0.5
5

15
30

0.05
0.05

0.05
0.05

0.05
0.05

UNITS
pA
pA
V
V

VOH High Level Output Voltage Voo = 5 V
Voo= 10V

4.95
9.95

4.95
9.95

4.95
9.95

V
V

V NL Noise Immunity (Note 3)

Voo=5V, Vo = 1.4 V or 3.6V
Voo= 10V,VO=2.8Vor7.2V

1.5
3.0

1.5
3.0

1.4
2.9

V
V

Vo = 1.4 V or 3.6 V

1.4
2.9

1.5
3.0

1.5
3.0

V
V

VNH Noise Immunity (Note 3)

Voo=5V,

":00 = 10V, Vo = 2.8V or 7.2 V

ION

Low Level Output Current Voo=5V, Vo=O.4V
VOO = 10V, v.o = 0.5V

0.35
0.72

0.3
0.6

0.24
0.48

mA
mA

lop

High Level Output Current Voo=5V, VO=2.5V
Voo = 10V, Vo = 9.5V

-0.35
-0.3

-0.3
-0.25

-0.24
-0.2

mA
mA

I'N

Input Current

-0.3

Voo = 15V, V'N = OV
Voo = 15V, V'N = 15V

ac electrical characteristics- CD4000C

-0.3
0.3

_10- 5
10- 5

-1.0
0.1

pA
1.0

J1A

T A = +25°C, C L = 15 pF, unless otherwise specified.
CONDITIONS

PARAMETER

MIN

TYP

MAX

UNITS

Voo = 5 V
Voo= 10V

40
20

80
55

ns
ns

Propagation Delay Time, Low to High Level

Voo = 5V
Voo=10V

50
25

120
65

ns
ns

tTHL

Transition Time, High to Low Level

Voo = 5 V
Voo=10V

50
20

200
115

ns
ns

tTLH

Transition Time, Low to High Level

Voo = 5 V
Voo = 10V

70
35

300
. 125

ns
ns

C,

I nput Capacitance

Any Input

5

pF

CPO

Power Dissipation Capacitance

(Note 4)

35

pF

tpHL

Propagation Delay Time, High to Low Level

tPLH

-.

"

\

'.

2·5

o
o
o

s:
"C

(")

,J::a.

o
o
o

(")

CD4001M/CD4001C quadruple 2-input NOR gate

general description
The CD4001 M/CD4001 C is a monolithic complementary MOS' (CMOS) quadruple two-input NOR gate
integrated circuit. Nand P-channel enhancement mode
transistors provide a symmetrical circuit with output
swings essentially equal to 'the supply voltage. This
,results in high noise immunity over a wide supply
voltage range. No dc power other than that caused by
leakage current is consumed during static conditions.

All inputs are protected against static discharge and
latching conditions.

features
• Wide supply voltage range
• Low powe'r
• High noise immunity

3Vto 15V
10 nW (typ)
0.45 V DO (typ)

schematic and connection diagrams

Voo

Voo

11

I

P

I

P

J

A+'8=X

v.
TOPVIEW

Vss

2-6

(')

C

absolute maximum ratings

~

o

g

Voltage at Any Pin (Note 1)
Vss - 0.3V to V DD + 0.3V
Operating Temperature Range
-55°C to +125°C
CD4001M
-40°C to +85°C
CD4001C
-65°C to +150°C
Storage Temperature Range
Package Dissipation
500mW
Operating V DO Range
Vss + 3.0V to Vss + 15V
Lead Temperature (Soldering, 10 seconds)
300°C

dc electrical characteristics

3:

.........

(')

C

~

o
o
....
(')

CD4001M
LIMITS

PARAMETER

-55°C

CONDITIONS
MIN

TYP

25°C
MAX

MIN

l25°C

TYP

MAX

MIN

TYP

UNITS
MAX

Quiescent Device
Current (I L )

Voo = 5V
Voo = 10V

0.05
0.1

0.001
0.001

0.05
0.1

3
S

p.A
p.A

Quiescent Device Dissi·
pation/Package (Po)

Voo = 5V
Voo = 10V

0.25
1

0.005
0.01

0.25
1

15
SO

p.W
p.W

Output Voltage Low
Level (VOL)

Voo = 5V, VI = V oo , 10 = OA
Voo = 10V. VI = Voo: 10 = OA

0.01
0.01

0
0

0.01
0.01

0.05
0.05

Output Voltage High
Level (V OH )

Voo = 5V, VI
Voo = lOV, VI

Noise Immunity
(V NL ) (Allinputs)

Voo = 5V, Vo = 3.SV, 10 = OA
Voo = 10V, Vo = 7.2V,lo = OA

Noise Immunity
(V NH ) (All Inputs)

Voo
Voo

= 5V, Vo = 0.95V,
= 10V, Vo = 2.9V,

Output Drive Current
N-Channel (IoN)
Output Drive Current
P-Channel (loP)

= Vss ,
= Vss ,

= OA
= OA

V
V

4.99
9.99

4.99
9.99

5
10

4.95
9.95

V
V

1.5
3

1.5
3

2.25
4.5

1.4
2.9

V
V

= OA
= OA

1.4
2.9

1.5
3

2.25
4.5

1.5
3

V
V

Voo
Voo

= 5V, Vo = O.4V, VI = Voo
= 10V, Vo = 0.5V, VI = Voo

0.5
1.1

0.40
0.9

1
2.5

0.28
0.S5

mA
mA

Voo
Voo

= 5V, Vo = 2.5V,
= 10V, Vo = 9.5V,

--{l.35
--{l.35

mA
mA

10
10

10
10

= Vss
= Vss

VI
VI

--{l.5
--{l.5

--{l.S2
--{l.S2

Input Current (Id

-2
-1
10

dc electrical characteristics

pA

CD4001 C
LIMITS

PARAMETER

-40°C

CONDITIONS
MIN

TYP

25°C
MAX

MIN

85°C

TYP

MAX

MIN

TYP

UNITS
MAX

Quiescent Device
Current (I L)

Voo
Voo

= 5V
= 10V

0.5
5

0.005
0.005

0.5
5

15
30

p.A
p.A

Quiescent Device Dissipat ion/Package (Po)

Voo
Voo

= 5V
= 10V

2.5
50

0.025
0.05

2.5
50

75
300

p.W
p.W

Output Voltage Low
Level (VOL)

Voo = 5V, VI
Voo = lOV, VI

0.01
0.01

0
0

0.01
0.01

0.05
0.05

Output Voltage High
Level (V OH )

Voo = 5V, VI = Vss , 10 =OA
Voo = 10V, VI = Vss,lo =OA

4.99
9.99

4.99
9.99

5
10

4.95
9.95

V
V

Noise Immunity
(VNd (All Inputs)

Voo = 5V, Vo
Voo = 10V, Vo

1.5
3

1.5
3

2.25
4.5

1.4
2.9

V
V

Noise Immunity
(V NH ) (All Inputs)

Voo = 5V, Vo = 0.95V, 10
Voo = 10V, Vo = 2.9V, 10

1.4
2.9

1.5
3

2.25
4.5

1.5
3

V
V

Output Drive Current
N-Channel (IoN)

Voo = 5V, Vo = O.4V, VI
Voo = 10V, Vo = 0.5V, VI

0.35
0.72

0.3
O.S

1
2.5

0.24
0.48

mA
mA

Output Drive Current
P-Channel (loP)

Voo
Voo

--{l.24
--{l.2

mA
mA

= V oo ,
= V oo ,

= 3.SV,
= 7.2V,

10
10

10
10

= OA
= OA

= OA
= OA
= OA
= OA

= Voo
= Voo

= 5V, Vo = 2.5V, VI = Vss
= 10V, Vo = 9.5V, VI = Vss

--{l.35
--{l.3

--{l.3
--{l.25

Input Current (II)

-2
-1

V
V

10.

Note 1: This device should not be connected to circuits with the power on because high transient voltages may cause permanent damage.

2-7

pA

o

o
~

ac electrical characteristics CD4001M
T A = 25°C and CL = 15 pF and input rise and fall times = 20 ns. Typical temperature coefficient for all values of V 00

= 0.3%tC.

Q

o

PARAMETER

CONDITIONS

oo

Propagation Delay Time High
to Low Level (t PH L)

Voo = 5V
Voo = 10V

35
25

50
40

ns
ns

Q

Propagation Delay Time Low
to High Level (tPLH)

Voo = 5V
Voo =10V

35
25

65
40

ns
ns

Transition Time High to Low
Level (tTHd

Voo = 5V
Voo = 10V

65
35

125
70

ns
ns

Transition Time Low to High
Level (tTLH)

Voo = 5V
Voo = 10V

65
35

175
75

ns
ns

Input Capacitance (C I )

Any Input

5

":!
~

o

ac electrical characteristics

MIN

TYP

MAX

UNITS

pF

CD4001C

T A = 25°C and CL = 15 pF and input rise and fall times = 20 ns. Typical temperature coefficient for all value~ of V 00 = 0.3%tC.

TYP

MAX

UNITS

Voo = 5V
Voo = 10V

35
25

80
55

ns
ns

Propagation Delay Time Low
to High Level (tPLH)

Voo = 5V
Voo = 10V

35
25

120
65

ns
ns

Transition Time High to Low
Level (tTHd

Voo = 5V
Voo = 10V

65
35

200
115

ns
ns

Transition Time Low to High
Level (tTLH)

Voo = 5V
Voo = 10V

65
35

300
125

ns
ns

Input Capacitance (C I )

Any Input

5

PARAMETER

CONDITIONS

Propagation Delay Time High
to Low Level (tPHL)

2-8

MIN

pF

n

o

~

o
o

to

~

........

n

CD4001BM/CD4001BC quad 2-input NOR buffered B series gate
CD4011BM/CD4011BC quad 2-input NAND buffered B series gate
features
general description

c

~

o

These quad gates are monolithic complementary MOS
(CMOS) integrated circuits constructed with N- and
P-channel enhancement mode transistors. They have
equal source and sink current capabilities and conform
to standard B series output drive. The devices also have
buffered outputs which improve transfer characteristics
by providing very high gain.

•

All inputs are protected against static discharge with
diodes to VDD and VSS.

• Maximum input leakage lpA at 15V over full temperature range

Lovy power TTL compatability. fan out of 2 driving
74 L or 1 driving 74 LS

• 5V-l0V-15V parametric ratings
• Symmetrical output characteristics

to

n

B'

Vss
1/4 of device shown

J =A +B
Logical" 1" = High
Logical "0" = Low

Vss
TOP VIEW

*AII inputs protected by standard CMOS
protection circuit.

CD4011 BC/CD4011 BM
Dual-In-Line and Flat Package
Voo
11

2(6.9.13)

1/4 of device shown

Vss
TOP VIEW

*AII inputs protected by standard CMOS
protection circuit.

2-9

n
c

-

Voo

J = A' B
Logical "1" = High
Logical "0" = Low

~

........
~

CD4001 BC/CD4001 BM
Dual-In-Line and Flat Package

ri'""
f."

o

Voo

2 (6.9. 13)

to

f>
n
c
~
9
to

schematic and connection diagrams

A'

o

(,J

...co

absolute maximum ratings

operating conditions

(Notes 1 and 2)

0

~

C

(,J

........

~

...
CO

I

Voltage at Any Pin
-o.SV to VOO + O.SV
Package Dissipation
SOOmW
VOO Range
-o.S VDC to +18 VOC
Storage Temperature
-65°C to +lS0°C
Lead Temperature (Soldering, 10 seconds)
300°C

Operating VOO Range
Operating Temperature Range
C04001 BM, CD4011 BM
C04001BC,C04011BC

3 VOC to lS VOC
-SSoC to +12SoC
-40° C to +8So C

0

~

C

(,J

ci

...
CO
0

~

dc electrica I

~haracteristics CD4001 8M, CD4011 8M (Note 2)

C

(,J

........

...

CO
0
0

100

Quiescent Oevice'Current

~

C

(,J

-Ssoc

PARAMETER

~

VOL

Low Level Output Voltage

CONDITIONS

MIN

0.25

7.5

fJ.A

0.005

0.50

15

fJ.A

VOO = 15V

1.0

0.006

1.0

30

fJ.A

VOO" 5V )

0.05

0

0.05

0.05

V

0.05

0

0.05

0.05

V

0

0.05

0.05

V

1101<

lJ.lA

O.OS

VOO" 5V )

110 1<

lJ.lA

VOO = SV,

.

4.95

4.95

5

4.95

V

9.9S

9.95

10

9.95

V

14.95

14.95

15

14.95

1.5

Vo = 4.SV

IOL

Low Level Output Current

liN

Input Current

3.0

3.0

V

4.0

4.0

V
V

Vo = O.SV

3.5

3.5

3

3.5

7.0

7.0

6

7.0

V

VOO = lSV, Vo = 1.5V

11.0

11.0

11.0

V

Vo = OAV

0.64

O.Sl

0.88

0.36

mA

1.6

1.3

2.25

0.9

mA

VOO = 5V,

VOO = 5V,

4.2

304

8.8

2.4

mA

--0.64

-O.Sl

-0.88

-0.36

rnA

VOO = 10V, Vo = 9.5V

-1.6

-1.3

-2.25

-0.9

rnA

VOO = 15V, Vo = 13.5V

-4.2

-3.4

-8.8

-2.4

mA

VOO = 15V, Vo = 1.SV
High Level Output Current

V

VOO = 10V, Vo = 1.0V

VOO = 10V, Vo = O.SV

IOH

4

4.0

V
1.5

1.5

3.0

= 10V, Vo = 9.0V

VQO = 15V, Vo = 13.5V
High Level Input Voltage

UNITS

MAX

0.004

VOO

VIH

MIN

0.50

VOO=15V
Low Level Input Voltage

+12S"C
MAX

0.25

VOO = 10V

VIL

TYP

VOO = 10V

VOO = 15V
High Level Output Voltage

MIN

VDO = 5V

VOO = 10V

VOH

+2SoC

MAX

VOO = ?V,

Vo = 4.6V

VOO = 15V, VIN = OV
VOO = 15V, VIN = 15V

-0.10

-10- 5

--0.10

-1.0

J.lA

0.10

10-5

0.10

1.0

fJ.A

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation;
Note 2: All voltages measured with respect to VSS unless othelWise specified.

2-10

n
dc electrical characteristics
PARAMETER

100

VOL

Low Level Output Voltage

VOO
High Level Output Voltage

VOO'5V
Voo
VOO

VIL

VIH

Low Level Input

Vo~tage

High Level Input Voltage

VOO

VOO
VOO
VOO

IOH

High Level Output Current·

VOO
VOO
VOO

'IN

Input Current

VOO
VOO

MIN

TYP

1

= 5V,
= 10V,
= 15V,
= 5V,
= 10V,
= 15V,
= 5V,
= 10V,
= 15V,
= 15V,
= 15V,

0.004

110 1< l,uA

MIN

1

MAX

UNITS

7.5

IJ.A

2

0.005

2

15

IJ.A

0.006

4

30

IJ.A

0

0.05

0.05

V

0.05

0

0.05

0.05

V

0.05

0

0.05

0.05

V

4.95

4.95

5

4.95

V

9.95

9.95

10

9.95

V

14.95

14.95

15

14.95

V

= 4.SV
Vo = 9.0V
Vo = 13.5V
Vo

= O.SV
= 1.0V
Vo = 1.5V
Vo = O.4V
Vo = O.SV
Vo = 1.5V
Vo = 4.6V
Vo = 9.5V
Vo = 13.5V

+85"C
MAX

4
0.05

1101< lJ1A

= 5V,
VDO = lOV,
VOO = 15V,

VOO
Low Level Output Current

= 10V
= 15V

1

VOO

VOO

IOL

= 10V
= 15V

c

+2S C

MAX
1

= SV
VOO = 10V
VOO = lSV
Voo

VOH

MIN

VDO

VOO'5V

~

-40°C

CONDITIONS

Quiescent Device Current

C

CD4001BC, CD4011BC (Note 2)

1.5

2

1.5

1.5

V

3.0

4

3.0

3.0

V

4.0

6

4.0

4.0

V

Vo

3.5

3.5

3

3.5

V

Vo

7.0

7.0

6

7.0

V

11.0

11.0

9

11.0

V

0.52

0.44

0.88

0.36

rnA

1.3

1.1

2.25

0.9

rnA

3.6

3.0

8.8

2.4

rnA

-0.52

-0.44

-0.88

-0.36

rnA

-1.3

-1.1

-2.25

-0.9

rnA

-3.6

-3.0

-8.8

-2.4

rnA

VIN
VIN

= OV
= 15V

-0.30

-10- 5

-0.30

-1.0

J1A

0.30

10-5

0.30

1.0

J1A

ac electrical characteristics CD4001 BC, CD4001 BM
T A = 25°C, Input tr; tf = 20 ITS. CL = 50 pF, R L = 200k. Typical temperature coefficient is 0.3%fc.
PARAMETER
tpHL

tPLH

tTHL,tTLH

Propagation Oelay Time, High·to·Low Level

Propagation Delay Time, Low·to·High Level

Transition Time

CONDITIONS

TYP

MAX

= 5V
VOO = 10V
VOO = 15V

120

250

ns

50

100

ns

35

70

ns

110

250

ns

50

100

ns

VOO

= 5V
VOO = 10V
VOO = 15V
VOO

UNITS

35

'7.0

ns

= 5V
VOO = 10V
VOO = 15V

90

200

ns

50

100

ns

40

80

ns

7.5

VOO

CIN

Average Input Capacitance

Any Input

5

CPO

Power Dissipation Capacity

Any Gate

14

2-11

pF
pF

0
0
aJ

3:
n

........

C

~

0
0
aJ

51
n
C

~

0

::t
aJ

3:
........
n
C

~

0

aJ

n·

(.)

al

5

ac electrical characteristics

CD4011BC, CD4011BM

T A = 25°C, Input tr; tf = 20 ns. CL = 50 pF, R L = 200k. Typical Temperature Coefficient is 0.3%fc.

~

c
(.)

CONDITIO!,!S

TYP

MAX

VDD = 5V

120

250

ns

al

VDD = 10V

50

100

ns

$=

VDD=15V

35

70

ns

VDD = 5V

85

250

ns

VDD = 10V

40

100

ns

VDD = 15V

30

70

ns

VDD = 5V

90

200

ns

VDD = 10V

50

100

ns

VDD=15V

40

80

ns

7.5

pF

PARAMETER

........

~

Propagation Delay, High-to-Low Level

tpHL

o

~

c(.)

Propagation Delay, Low-to-High

tpLH

Lev~1

ci
al

.o
o

tTHL, tTLH

Transition 'Time

~

c

(.)

........

CIN

Average Input Capacitance

Any Input

5

al
.o
o

CPD

Power Dissipation Capacity

Any Gate

14

~

UNITS

pF

~

c

(.)

typical performance characteristics
20'
~

'"

~
>

I-

:::>

J

VOO =15V

15

I
Veo =10V

10

,

0
0

~

V,

Veo =5V

5

>

l

~

)00

J

l:::l
0

0

20
C04011B
Tr 25'C

15

'"

~>

~,
vss-rr'

I-

10

:::>
:::>
0

,

5

0

l'

>

0
20

C04011B
Tr =25'C

.l
VOO =10V

Voo

0

-I

20
~

I

~

~
VSS~'

I-

C04001B
Tr =25C

15

J

Voo

I

Voo =10V

10

114

-

v,£?j-v o

:::l

t:::l
0

,

'0 -

"'vss- r;

Voo =5V

5

~ID

0

>

I'

15
10
5
VI -INPUT VOLTAGE (V)
ONE INPUT ONLY'

0

20

-

'\

0

5
10
15
VI -INPUT VOLTAGE (V)
BOTH INPUTS

.I

Voo =15V

'"

\

V I , : Vo

.I
Veo =5V

l-

2'0 -

5
10
15
VI-INPUT VOLTAGE (V)
ONE INPUT ONLY

.l

Veo =15V

20

\

FIGURE 2. Typical Transfe~
'Characteristics

FIGURE 1. Typical Transfer
Cha racteristics

20
~

...
'"
~
>

I
,

c

>

C04001B
Tt =25'C

J
Voo =15V
J
VOO =10V

15
10

0

~;;;

I' TTl

vor

~,: Vo

5~

¥

VSS

JOO

FIGURE 4. Typical Transfel
Characteristics

~;

~~
0

400

C04011B
TA =25C
CL =50 pF

I

JOO

... w

q: ::;;
~~

\

~:3
, ...

0

~
~g:£

\

5~ 200

ii: >-

~
20

."
0

C04001B
TA=25'C
CL =50 pF

~c 100

('

10
5
15
V,-,NPUT VOLTAGE (V)
BOTH INPUTS

400

0:":
......

Jo

_

0

~
q:

v;

5

~

FIGURE 3. Typical Transfer
Characteristics

5
10
15
Voo - SUPPL YVOLTAGE (V)
FIGURE 5

2·12

20

'w

~c

~

200

~

100
0

tpHL

tPI~ b..

0

~

10
15
5
Voo -SUPPLY VOLTAGE (V)

FIGURE 6

20

("')

C

typical performance characteristics (cont).
200

o:W

~~

CD4001 ~

CD40018
TA ·2SoC

;]:

~~

~~
"-",
><
I- "-

0-

I

~~

VOD.:;::.-

6~

J--- l.--

9

C040118
TA-25'C

3:~

TA'25~C

150

0>

:!c

~

o

200

m

s:

150

'":" I-

"c

'" >
'" <

~g

100

("')

100

< z

~ CI

VOD"10V _

-----

SO

,0

~g:

25

100

75

50

I---

I'" .

-~~

VOD"15V

o
o
..&
m

so

"-

i

25

~

>: ~
1-<

0
75

50

FIGURE 7

100

75

c

~

FIGURE 9

FIGURE B

51
("')

CL - LOAD CAPACITANCE (pF)

CL - LOAD CAPACITANCE (pF)

CL - LOAD CAPACITANCE (pF)

SO

25

0

100

9

..&

2DO

m

~g

t r • tf - 20 ns
TA' 2S'C

j

",w

"':; 150

xi=

~~

00

~z

Z

;:

1.5

1

U

0

~

50

~

10

I\

(See Application Note AN·90
Propagation Delay)

0.5

0:

a
0

2S

50

I

100

75

0

=
~

~~:~~:: '-~

B 1.0

100

5~

~~
to..

s:

2.0

4

2

0

100

~

(")

(J

I~
:E

N

o

o

~

CD4002M/CD4002C dual 4-input NOR gate

(J

general description
These NOR gates are monolithic complementary
MOS (CMOS) integrated circuits. The Nand P
channel enhancement mode transistors provide a
symmetrical circuit with output swings essentially
equal to the supply voltage. This results in high
noise immunity over a wide supply voltage range.
No DC power other than that caused by leakagecurrent is consumed during static conditions. All
inputs are protected against static discharge· and
latching conditions.

•
•

• Automotive
•. Data terminals

features
3V to 15V

Wide supply voltage range

0.45 V DO (typical)

applications

r

•

10 nW (typical)

Low power
High noise immunity

•

Instrumentation

•

Medical electronics

•
•

Alarm system
Industrial controls

•

Remote metering

•

Computers

schematic and connection diagrams

Vee

A,

NC

NC

TOPVIEW

Vss

2·14

Vss

(")

C

absolute maximum ratings

~

o
o

Voltage at Any. Pin (Note 1)
Vss - O.3V to Vss + 15.5V
-55°C to +125°C
Operating Temperature Range CD40XXM
-40°C to +85°C
CD40XXC
-65°C to +150°C
Storage Temperature Range
500mW
Package Dissipation
300°C
Lead Temperature (Soldering, 10 seconds)
Vss + 3V to Vss + 15V
Operating V DO Range

N

3:

........
(")

C

~

o
o

N

(")

electrica I characte ristics
LIMITS
CHARACTERISTICS

TEST
CONDITIONS
VOLTS

_55°C

+25°C

Vee MIN MAX MIN

Vo

CD4002C

CD4002M
_40°C

+125°C

+25°C

TYP MAX MIN MAX MIN MAX MIN

TYP

+85°C

UNITS

MAX MIN MAX

Quiescent Device
Current (lL)

5
10

0.5
0.1

0.001 0.05
0.001 0.1

3
6

0.5
5

0.005 0.5
0:005 5

15
30

pA
pA

Quiescent Device
Dissipation/Package (P~)

5
10

0.25
1

0.005 0.25
0.01
1

15
60

2.5
50

0.025 2.5
0.05 50

75
300

pW.
pW

Output Voltage
Low Level (VOL)

5
10

0.01
0.01

0
0

0.05
0.05

0.01
0.01

0
0

0.05
0.05

V
V

High Level (V OH )
Noise Immunity (V NI )
(All Inputs)
(V NH )
Output Drive Current
N-Channel (IoN)

0.01
0.01

0.01
0.01

5
10

4.99
9.99

4.99 5
9.99 10

4.95
9.95

4.99
9.99

4.99
9.99

5
10

4.95
9.95

V
V

>3.5
>7.0

5
10

1.5
3

1.5
3

2.25
4.5

1.4
2.9

1.5
3

1.5
3

2.25
4.5

1.4
2.9

V
V

<1.5
<3.0

5
10

1.4
2.9

1.5
3

2.25
4.5

1.5
3

1.4
2.9

1.5
3

2.25
4.5

1.5
3

V
V

0.5
1.1

0.40
0.9

0.28
0.65

0.35

0.3
0.6

1
2.5

0.24
0.48

mA
mA

-0.35
-0.35

-0.35
-0.3

-0.24
-0.2

mA
mA

V, = Voo

~::

5
10

V,=VSs

~:~

5
-0.62
10 -0.62

P-Channel (loP)

-0.5
-0.5

I nput Current (I,)

0.72

-0.3 -2
-0.25 -1

10

pA

10

Note 1: This device should not be connected to circuits with the power on because hi9h transient voltage may cause permanent
damage_

LIMITS
CHARACTERISTICS

TEST
CONDITIONS
Veo
(VOLTS)

MIN

TYP

UNITS

CD4002C

CD4002M
MAX

MIN

TYP

MAX

35

80

35

50

Low·to·High Level (tPLH)

10

-

-

25

40

-

25

55

High-to-Low Level (tPHL)

5

-

35

50

-

35

120

10

-

25

40

-

25

65

Propagation Delay Time:

Transition. Time:
Low·to·High Level (tTLH)
High·to·Low Level (tTHL)

Input CapaCItance (C,I

5

5

-

65

125

10

35

70

10

-

Any Input

-

5

5

65 .
35

2·15

175
75

-

65

200

35

115

65

300

35

125

5

-

ns

ns

ns

ns
pF

CJ
CD

o
~

c

CJ

........

:E

CD

o
o

~

c

CJ

CD4006M/CD4006C 18-stage static shift register
general description
The CD4006M/CD4006C la-stage static shift register
is comprised of four separate shift register sections,
two sections of four stages and two sections of five
stages. Each section has an independent data input.
Outputs are available at the-fourth stage and the fifth
stage of each section. A common clock signal is used for
all stages. Data is shifted to the next stage on the
,negative-going transition of the clock. Through appropriate connections of inputs and' outputs, multiple
register sections of 4, 5, a and 9 stages or single register
section of 10, 12, 13, 14, 16, 17, and 18 stages can be
implemented usin~ one packag~.

Wi,de supply voltage range
High noise immunity
Low clock input capacitance

Medium speed operation

•
•

Low power
Fully static operation

10 MHz typ
with Vee = 10V

applications
•
•
•
•
•
•
•
•

features
•
•
•

•

3.0V to 15V
0.45 Vee typ
6 pF typ

Automotive
Data terminals
Instrumentation
Medical electronics
Alarm system
Industry control
Remote metering
Computers

logic diagrams
DATA

-{:>o--

DATA

r

-{>o-

OUTPUT
IF 4TH OR
5TH STAGE

·1-,
TIt-I'

I
TO NEXT STAGE
0+1

-HII .!.

FROM
PREVIOUS
STAGE
lOR DATA
IF 1ST STAGE)

Cl

r-

~

CI

ClDCK~Cl

connection diagram

truth table

0

CL~

0+1

0

L-

0

1

L-

1

X

~

NC

x=
~

Don't care

= Level change

NC = No change
DATA 1

I

L...."f.....l

NC

CLOCK

DATA 2

DATA J

DATA4

v,s

TOP VIEW

2-16

o

c

absolute maximum rati ngs

~

Voltage at Any Pin (Note 1)
Operating Temperature Range

Vss - 0.3V to V DD + O.3V

·0

-55°C to +125°C
-40°C to +85°C
-65°C to +150°C
500mW
Vss + 3.0V to Vss + 15V
300°C

3:
........
o

o

0)

CD4006M
CD4006C

Storage Temperature Range
Package Dissipation
Operating VDD Range
Lead Temperature (Soldering, 10 seconds)

C·
~

o
o

0)

o

dc electrical characteristics

CD4006M
LIMITS

PARAMETER

--55"C

CONDITIONS
MIN

TYP

25"C
MAX

MIN

125°C

TYP

MAX

MIN

TYP

UNITS
MAX

Quiescent Device
Current (I L)

Voo ~ 5.0V
Voo ~ 10V

0.5
1.0

0.01
0.01

0.5
1.0

30
60

J.lA
J-IA

Quiescent Device Dissi·
pation/Package (Po)

Voo
Voo

= 5.0V
= 10V

2.5
10

0.05
0.1

2.5
10

150
600

J.lW
/-lW

Output Voltage Low
Level (VOL)

Voo ~ 5.0V
Voo ~ 10V

0.01
0.Q1

a
a

0.01
0.01

0.05
0.05

V
V

Output Voltage High
Level (V OH )

Voo
Voo

4.99
9.99

5
10

Noise Immunity
(V!'U-) (All Inputs)

Voo = 5.0V
Voo = 10V

1.5
3.0

1.5
3.0

Noise Immunity
(V NH ) (All Inputs)

Voo ~ 5.0V
Voo = 10V

1.4
2.9

1.5
3.0

Output Drive Current
N·Channel (IoN)

Voo = 5.0V, Vo = 0.5V
Voo = 10V, Vo =0.5V

0.155
0.31

0.125
0.25

Output Drive Current
P·Channel (loP)

Voo = 5.0V, Vo = 4.5V
Voo = 10V, Vo =9.5V

-{).125
-{).25

Input Current (II)

Any Input

= 5.0V
~

4.99
9.99

10V

-{).1
-{).2

-

4.95
9.95

V
V

2.25
4.5

1.4
2.9

V
V

2.25
4.5

1.5
3.0

V
V

,0.25
0.5

0.085
0.175

-{).15
-{).3

mA
mA

-{).07
-{).14

mA
mA
pA

10

dc electrical characteristics

CD4006C
LIMITS

PARAMETER

-40°C

CONDITIONS
MIN

TYP

25
MAX

MIN

u

c

8SoC
MIN

TYP

UNITS
MAX

TYP

MAX

5
10

0.03
0.05

5
10

70
140

J-IA
J.lA
J-IW
}J.W

Quiescent Device
Current (I L)

Voo= 5.0V
Voo = lOV

Quiescent Device Dissi·
pation/Package (~o)

Voo
Voo

= 5.0V
= 10V

25
100

0.15
0.5

25
100

350
1400 .

Output Voltage Low
Level (VOL)

Voo = 5.0V
Voo = 10V

0.01
0.01

0
0

0.01
0.01

0.05
0.05

Output Voltage High
Level (V OH )

Voo
Voo

= 5:0V
= 10V

4.99
9.99

4.99
9.99

5
10

4.95
9.95

V
V

Noise Immunity
(V N L) (All Inputs)

Voo
Voo

= 5.0V
= 10V

1.5
3

1.5
3

2.25
4.5

1.4
2.9

V
V

Noise Immunity
(V NH ) (All Inputs)

V oo =5.0V
Voo = 10V

1.4
2.9

1.5
3

2.25
4.5

1.5
3

V
V

Output Drive Current
N·Channel (ioN)

Voo = 5.0V, Vo
Voo = 10V, Vo

0.072
0.15

0.06
0.125

0.25
0.5

0.048
0.10

Output Drive Current
P·Channel (loP)

Voo = 5.0V, Vo = 4.5V
Voo :' 10V, Vo = 9.5V

Input Current (Id

Any Input

= 0.5V
= 0.5V

-0.06
-0.12

-0.05
-0.1

-{).15
-{).3

-0.04
-0.08

10

Note 1: This device should not be connected to circuits with power on because high transient voltages may cause permanent damage.

2-17

V
V

mA
mA
mA
mA
pA

(.)

CD

o
o

ac electrical characteristics
CD4006M at T A = 25°C and C L = 15 pF. \ Typical temperature coefficient for all values of V DD = O.3%/oC.

~

c

LIMITS

(.)

"'~"
CD

o
o

~

c
(.)

PARAMETER

CONDITIONS

MIN

T.YP

MAX

UNITS

Propagation Delay Time (tPLH = tpHd

V OD '" 5.0V
V DD = 10V

180
80

400
200

ns
ns

Transition Time (t TLH = tTH L)

V DD
V DD

= 5.0V
= 10V

150
60

400
200

ns
ns

Minimum Clock Pulse Width
(TwL=T wH )

V DD
V DD

= 5.0V
= 10V

100
50

500
200

ns
ns

Clock Rise and Fall Time
(t rCI =tfCtl*

V DD
V DD

= 5.0V
= 10V

15
5

/1S

Set·Up Time

V DD
V DD

= 5.0V
= 10V

80
40

ns
ns

Maximum Clock Frequency (f el )

V DD
V DD

= 5.0V
= 10V

Input Capacitance (C I )

Data Input
Clock Input

ac electrical characteristics

50
25
1
2.5

.

/1S

MHz
MHz

5
10

pF
pF

5
6

CD4006C
LIMITS

PARAMETER

CONDITIONS'

UNITS

TYP

MAX

V DD = 5.0V
VDD = 10V

180
80

500
250

ns
ns'

V DD = 5.0V
V DD = 10V

150
60

400
250

ns
ns

Minimum Clock Pulse Width
(TWH =T wL )

V DD = 5.0V,
V DD = 10V

100
50

830
250

ns
ns

Clock Ri~e and Fall Time
(trCI = tfCtl*

V DD = 5.0V
V DD = lOV

Set·Up Time

V DD = 5.0V
V DD = lOV

Maximum Clock Frequency (fed

V DD = 5.0V
V DD = lOV

I nput Capacitance (C I )

bata Input

Propagation Delay Time (t pLH = t pH L)
Transition Time (t TLH

= t THL )

MIN

.15
5
50
.25
5
10

0.6
2

/1S
/1S

ns
ns

100
50

MHz
MHz

5
6

Clock Input

*If more than one unit is cascaded trCI should be made less than or equal to the sum of the fixed propagation delay time at 15 pF and the
transition time of the output stage for the estimated capacitive load.

switching time waveforms

-I'~-

_11'1_
CLOCK

voe:,J(:0%
V 10%
50%

v::
DATA

ss

50%

~!, ~ -j 1~'TlH
10%:kf0;,o%

----+--+tSETUP

-I---

50% \

-I

_'--'IS-ET-UP--

90%:~'
50% ~10_%_ _ __

£.90%
10%/! ~IUO'%

OUTPUT Vee
Vss

10%

IWH - - IWL -

'.

v

90%,
50%

tpLH

-

t,=tf=20ns

2-18

_ ~ ~I ~ITHL
It

90%
50%

10%

pF
pF

(')

C

~

o

9
3:

.........
(')

C

~

o
o
.....

CD4007M/CD4007C dual complementary pair plus inverter

(')

general description

features

The CD4007M/CD4007C consists of three complementary pairs of N-channel and P-channel enhancement'mode
MOS transistors suitable for series/shunt applications.
All inputs are protected from static discharge by diode
clamps to Voo and Vss.

•

Wide supply voltage range

•

High noise immunity

3.0V to 15V
0.45 Vce typ

For proper operation the voltages at all pins must be
constrained to be between Vss - 0.3V and Voo + 0.3V
at all times.

ac test circu its

Voo

.J14.11

.

IP

' '"' H""""'
1;.9 J
10

\

12

I

N

15 pF

Voo

Voo

.J14.2

H

1
3

'''O'
\

.

I

.J14

N

1;.4

1 5

i

J

lP

,,,",' IT""""'

P,

"""O'

15pF

, Order Number CD4007CJ
or CD4007MJ

Order Number CD4007MD

See Package 1
Order Number CD4007MF

See Pac kage 16

Sa,e Package 4

Order Number CD4007CN

See Package 22

2-19

B.13

I

N

1;

'J

15pF

(.)

so
~

c

(.)

":E

S
o
~

C

(.)

absolute maximum ratings

(Note 1)

Voltage at Any Pin
Operating Temperature Range
CD4007M
CD4007C
Storage Temperature Range
Package Dissipation
Operating Voo Range
Lead Temperature (Soldering, 10 seconds)

Vss - 0.3V to Voo + 0.3V
-55°C to +125°C
-40°C to +85°C
--65°C to +150°C
500 mW
Vss + 3.0V to Vss + 15V
300°C

dc electrical characteristics

CD4007M
LIMITS

PARAMETER

-55°C

CONDITIONS
MIN

Quiescent Device
Current (I L )

V DD
V DD

Quiescent Device Dissipation/Package (Po)

V DD
Voo

Output Voltage Low
Level (VOL)

V DO
V Do

= 5V
= 10V
= 5V
= 10V
= 5V
= 10V

Output Voltage High
Level (V OH )

Voo
V OD

= 5V
= 10V

Noise Immunity
(V NL ) (All Inputs)

Voo
Voo

Noise Immunity
(V NH ) (All Inputs)

V DO
Voo

Output Drive Curre!")t
N·Channel (lDN)

= 5V. Va
= 10V, Vo
= 5V, Vo
= 10V, Va
= 5V, Vo

Output Drive Current
P-Channel (I D P)

TYP

25°C
MAX

MIN

TYP

125°C
MAX

0.05
0.1

. 0.001
0.001

0.05
0.1

0.25
1

0.005
0.01

0.01
0.01

0

o-

MIN

TYP

UNITS
MAX
3
6

J.l.A
J.l.A

0.25
1

15
60

J.l.W
J.l.W

0.01
0.01

0.05
0.05

""'-

V
V

4.99
9.99

4.99
9.99

5
10

4.95
9.95

V
V

= 7.2V

1.5
3

1.5
3

2.25
4.5

1.4
2.9

V
V

= 0.95V
= 2.9V

1.4,
2.9

1.5
3

2.25
4.5

1.5
3

V
V

V DO
V OD = 10V, Yo

= O.4V, VI = Voo
= 0.5V, VI = Voo

0.75
1.6

0.6
1.3

1
2.5

0.4
0.95

mA
mA

V DD = 5V, Vo
V DD = 10V, Vo

= 2.5V, VI = Vss
= 9.5V, VI = Vss

-1.75
-1.35

-1.4
-1.1

-4
-2.5

-1
--0.75

mA
mA

= 3.6V

pA

10

Input Current (II)

dc electrical characteristics

CD4007C
LIMITS

PARAMETER

-40°C

CONDITIONS
MIN

TYP

25°C
MAX

MIN

85°C

TYP

MAX

MIN

TYP

UNITS
MAX

Quiescent Device
Current (I L )

V DO = 5V
V DO = 10V

0.5
1

0.005
0.005

0.5
1

15
30

J.l.A
J.l.A

Quiescent Device Dissipat ion/Package (P D)

Voo
V DO

= 5V
= 10V

2.5
10

0.025
0.05

2.5
10

75
300

I1W
I1W

Output Voltage Low.
Level (VOL)

Voo
Voo

= 5V
= 10V

0.01
0.01

0
0

0.01
0,01

0.05
0.05

Output'Voltage High
Level (V OH )

V DO
V DO

= 5V
= 10V

Noise Immunity
(VNd (All. Inputs)

4.99
9.99

4.99
9.99

Voo = 5V, Vo = 3.6V
V DO = 10V, Vo = 7.2V

1.5
3

1.5
3

Noise Immunity
(V NH ) (All Inputs) .

V DO = 5V, Vo = 0.95V
V DD = 10V, Va = 2.9V

1.4
2,9

Output Drive Current
N-Channel (IoN)

V DO = 5V, Vo
V OD = 10V, Vo

0.35
1.2

Output Drive Current
P-Channel (loP)

V OD = 5V. Va = 2.5V. VI
V DO = 10V. Vo = 9.5V. VI

= O.4V, VI = Voo

= 0.5V, VI = V OD
= Vss
= Vss

-1.3
-{J.65

Input Current (Id

4.95
9.95

V
V

2.25
4.5

1.4
2.9

V
V

1.5
3

2.25
4.5

1,5
3

V
V

0.3
1

1
2.5

0,24
0.8

mA
mA

-1.1
-{J.55

-4
-2.5

-(J.9
-{J.45

mA
mA

5
·10

10

Note 1: This device should not be connected to circuits with the power on because high transient voltages may cause permanent damage .

.

2-20

V
V

pA

o
ac electrical characteristics
TA

= 25°C and

CL

= 15 pF

c

CD4007M

~

o

= 20 ns. Typical

and input rise and fall times

temperature coefficient for all values of Voo

= 0.3%tC.

S

s:

.......
CONDITIONS

Propagation Delay Time (tPLH = tPH L)

Voo = 5V
Voo = 10V

35
20

60
40

ns
ns

Transition Time (t TLH = t THL )

Voo = 5V
Voo = 10V

50
30

75
40

ns
ns

Input' Capacitance (C I )

Any Input

5

ac electrical characteristics

MIN

TYP

MAX

UNITS

PARAMETER

pF

CD4007C

T A = 25°C and C L = 15 pF and input rise and fall times = 20 ns. Typical temperature coefficient for all values of V DO = 0.3%tC.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Propagation Delay Time (t PLH = tpH L)

Voo = 5V
Voo = 10V

35
20

75
50

ns
ns

Transition Time (t TLH = tTHL)

Voo = 5V
Voo = 10V

50
30

100
50

ns
ns

Input Capacitance (C I )

Any Input

5

switching time wc;lveforms

_I_I,
OD

INPUT V

-If

~I

---jt--:Jto5~~I~~%--':':905::":'~"1~
10%

~1~0'~Y,

:-- - : :
DO

''"'[,

-

'PLH

90%

50~%

OUTPUT

_ _ _ __

Ij
-

90%

li~Y

v~-----~-~-----~
'THl

~

tr

I-

= tf = 20 OS

2-21

'TlH

-I

I-

pF

o
c

~

o

S
o

(.)

£Xl

QO

o
o

lid"
Q

(.)
.........

:E
£Xl

CD4008BM/CD4008BC 4-bit full adder

QO

o
o

general description

features

The CD4008B types consist of four full-adder stages with
fast look-ahead carry provision from stage to stage.
Circuitry is included to provide a fast "parallel-carryout" bit to permit high-speed operation in arithmetic
sections using several CD4008B's. C04008B inputs
include the four sets of bits to be added, A 1 to A4
and B 1 to B4, in addition to the "Carry In" bit from a
previous section. CD4008B outputs include the four
sum bits, Sl and S4, in addition to the high-speed
"parallel-carry-out" which may be utilized at a succeeding C04008B section.

• Wide supply voltage range
• High noise immunity
• Low power TTL compabitility

lid"

Q
(.)

3V to 15V
0.45 VOO typ
fan out of 2
driving 74L
or 1 driving 74LS

• 4 sum outputs plus parallel look-ahead carry-output
• Quiescent current specified to 15V
• Maximum input leakage of lilA at 15V (full package
temperature range)

All inputs are protected from damage due to static
discharge by diode clamps to VDO and Gnd.

block diagram
HIGH SPEED
PAR. CARRY

I - - - - - Q Co (CARRY OUT)

1
B4 0-:-,; , 5-+-+-+--t--+-+-+--Ht---.t

54

A40-:---+-+--~r;-+-+~--~

BlO-=--+-i-HH-+.....----.,

Sl

AlO-=-+-+-~~~------.1

B2a---+-+--~~~-----.1

52

A2~--+-+--~~-------.1

Bl O";'--+-Ht----------~

51

AlO";'--~._-------.1

CI (CARRY INI

cr--.....- - - - - - - - - - - '

connection diagram
Dual-In-Line and

truth table
~Iat

Package

16

A4
Bl

15 B4

Al

14 Co (CARRY OUTI

B2

S4

A2

Sl

Bl
Al
9

VSS

Ai

Bi

Ci

CO

SUM

0

0

0

0

0

1

0

0

0

1

0

1

0

0

1
0

Voo

CI (CARRY INI

TOPVIEW

2-22

1

1

0

1

0

0

1

0

1

1

0

1

1

0

0

1

1

1

0

1

1

1

1

1

(")

absolute maximum ratings

recommended operating conditions

C

(Notes 1 and 2)

(Note 2)

o

--{l.5 to +18 VOC
VOO de Supply Voltage
'VIN Input Voltage
--{l.5 to VOO +0.5 VOC
-65°C to +150°C
TS Storage Temperature Range
500mW
Po Package Oissipation
300°C
T L Lead Temperature (Soldering, 10 seconds)

VOO de Supply Voltage
VIN Input Voltage
T A Operating Temperature Range
C04008BM
CD4008BC

3to15VOC

o to VOO VOC
-55°C to +125°C
-40°C to +85°C

~

o

00
OJ

s:

........
(")

C

dc electrical characteristics

~

o
o

CD4008BM (Note 2)
-55°C

100

VOL

VOH

VIL

Quiescent Oevice Current

Low Level Output Voltage

High Level Output Voltage

Low Level Input Voltage

MIN

High Level Input Voltage

10H

Low Level Output Current

High Level Output Current

I nput Current

150

pA

300

pA

VOO = lSV

20

1.0

20

600

pA

11013.5
;;;>7.0

5
10

1.5
3

1.5
3

<:.25
LL5

1.4
2.9

1.5
3

1.5
3

2.25
4.5

1.4
2.9

V
V

(V NH )

";;1.5
";;3.0

5
10

1.4
2.9

1.5
3

:2.25
4.5

1.5
3

1.4
2.9

1.5
3

2.25
4.5

1.5
3

V

0.5
0.5

5
10

0.31
0.63

0.25
0.5

0.5
0.6

0.175
0.35

0.145
0.3

0.12
0.25

0.5
0.6

0.95
0.2

mA
rnA

4.5
9.5

5
-0.31
10 -0.75

-0.25
-0.6

-0.5
-1.2

-0.175
-0.4

-0.145
-0.35

0.095
-0.24

mA
mA

Output Drive Current
N·Channel (IoN)
P·Channel (loP)
Input Current (I,)

ac

-0.12 -0.5
-0.3 -1.2
10 .

10

electric~1

characteristics

pA

@)T A = 25 °c an~ C L = 15pF

Typical Temperature Coefficient for all valuflS of Voo= 0.3%/° C
LIMITS
CHARACTERISTICS

TEST
CONr)ITIONS

Vee

CD40XXM

UNITS

CD40XXC

MIN

TYP

MAX

MIN

TYP

MAX

Propagation Delay Time:
Low·to·High Level It pLH )

5

-

50

75

-

50

100

10

-

25

40

..

25

50

High·to Low Level It PHL )

5

-

50

75

50

100

10

25

40

25

50

5

-

75

100

-

75

125

10

-

40

60

-

40

75

5

-

75

125

150

75

-

75

50

50

100

('VOLTS)

Transition Time:
Low·to·High Level ItTLH)
High·to·Low Level ItTHd

10
Input Capacitance IC,)

Any Input

5

2·28

-

5

-

V

ns

ns

ns

ns

pF

(")

C

~

o
....
w
OJ

~

.........
(")

C

CD4013BM/CD4013BC dual D flip~flop

~

....ow

general description

OJ

(")

The CD4013B dual D flip-flop is a monolithic complementary MOS (CMOS) integrated circuit constructed
with Nand P channel enhancement transistors. Each
flip-flop has independent data, set, reset, and clock
inputs and "Q" and "0" outputs. These devices can be
used for shift register applications, and by connecting
"0" output to the data input, for counter and toggle
applications. The logic level present at the "D" input is
transferred to the Q output during the positive-going
transition Qf the clock pulse. Setting or resetting is independent of the clock and is accomplished by a high
level on the set or reset line respectively.

•

Low power TTL compatibility

applications
•

Automotive

•

Data terminals

•

Instrumentation

•

Medical electronics

•

Alarm system

features

•

Industrial electronics

•
•

3.0V to 15V

•

Remote metering

0.45 VDD typ

•

Computers

Wide supply voltage range
High noise immunity

connection diagram

Dual-In-line and Flat Package

il2

02

VOD

1,4

13

CLOCK 2

RESET 2

19

lD

II

12

DATA 2

SET 2

8

LI

I

I
F/F

F/F

2

1

I
==t
1

QI

1 I
4

3

12
ill

CLOCK 1

6

17

SET 1

VSS

5

RESET 1

DATA 1

TOP VIEW

truth table

a

elt

0

R

S

a

f
.r

0

0

0

1

I

0
0

1

0

'"\....

x

0

0
0

a

x

x

1

0

0

1

x

x

0

1

I

0

x

x

1

1

1

1

No change
t = Level change
x = Don't care case

2-29

a

fan out of 2
driving 74L
or 1 driving 74LS

(.)

m

M

absolute maximum ratings

recommended operating conditions

(Notes 1 and 2)

(Note 2)

voo de Supply Voltage
-0.5 to +18 VOC
VIN Input Voltage
-0.5 to VOO +0.5 VOC
TS Storage Temperature Range
-65°C to +150°C
Po Package Dissipation
500mW
TL Lead Temperature (Soldering, 10 seconds)
300°C

Voo de Supply Voltage
VIN Input Voltage
T A Operating Temperature Range
C04013BM
C04013BC

~

o

~

c
(.)

.......
~

m

M

+3 to +15 VOC
Oto VOO VOC
-55°C to +125°C
--40° C to +85° C

~

~
C

dc electrical characteristics

CD4013BM (Note 2)

(.)
-5SoC
PARAMETER

VOL

VOH

VIL

Quiescent Device Current

Low Level Output Voltage

High Level Output Voltage

Low Level Input Voltage

\

10L

High Level Input Voltage

Low Level Output Current

High Level Output Current

Input Current

1.0

30

J-LA

60

J-LA

.VOO = 15V

4.0

4.0

120

J-LA

VOO = SV

0.05

0.05

O.OS

V

VOO = 10V

0.05

0.05

0.05

V

VOO = 15V

O.OS

0.05

O.OS

V

1101< 1.0J-LA

1101< 1.0J-LA
VOO = SV

4.95

4.9S

4.95

V

VOO = 10V

9.9S

9.95

9.95

V

VOO = 15V

14.95

14.95

14.95

V

1101< 1.0pA
Vo = 0.5V or 4.5V

1.5

1.5

1.5

V

VOO= 10V, VO= 1.0Vor9.0V

3.0

3.0

3.0

V

VOO = 15V, Vo = 1.5Vor 13.5V

4.0

4.0

4.0

V

IIOI<1.0pA
VOO = 5V, Vo = 0.5V or 4.5V

3.5

3.5

3.5

VOO = 10V, Vo = 1.0Vor9.0V

7.0

7.0

7.0

V

VOO = 15V, Vo = 1.5Vor 13.5V

11.0

11.0

11.0

V

VOO = 5V, Vo = O.4V

0.64

0.51

0.88

0.36

rnA

VOO = 10V, Vo = 0.5V

1.6

1.3

2.25

0.9

rnA

4.2

3.4

8.8

2.4

rnA

'-0.51

-0.88

rnA

VOO = 10V, Va = 9.5V

-1.6

-1.3

-2.25

-0.36
-0.9

= 15V, Vo = 13.5V
VOO = 15V, V,N = OV
VOO = 15V, V,N = 15V

-4.2

-3.4

-8.8

-2.4

Vo = 4.6V

-10- 5
10-5

-0.1
0.1

VOO = 5V

= 10V

VOO = 15V

High Level Output Voltage

pA

0.1

1.0

pA

25°C

85°C
UNITS

MAX

MIN

TVP

MAX

MIN

MAX

4.0

4.0

30

8.0

8.0

60

J-LA
pA

16.0

16.0

120

pA

VOO = 5V

0.05

0.05

0.05

V

VOO = 10V

0.05

0.05

0.05

V

VOO = lSV

0.05

0.05

0.05

V

IIOI<1.0pA
VOO = 5V

= 10V

VOO = 15V
Low Level Input Voltage

-1.0

1101<1.0pA

VOO

V,L

rnA

-0.1

CONDITIONS

VOO

VOH

rnA

CD4013BC (Note 2)
-40°C

Low Level Output Voltage

V

-0.64

VOO = 5V,

MIN

VOL

.MAX

2.0

PARAMETER

Quiescent Device Current

MIN

1.0

dc electrical characteristics

100

MAX

2.0

VOO
liN

MIN

TVP

VOO = 10V

VOO = 15V, Vo = 1.5V
10H

MAX

VOO = 5V

Voci = 5V,

V,H

12SoC
UNITS

MIN
100

2SOC

CONDITIONS

4.95

4.95

4.95

V

9.95

9.95

9.95

V

14.95

14.95

14.95

V

IIOI<1.0pA

=0.5V or 4.5V

1.5

1.5

1.5

V

VDO = 10V, Vo = 1.0Vor 9.0V

3.0

3.0

3.0

V

VOO = 15V, Vo = 1.5Vor 13.5V

4.0

4.0

4.0

V

VOO = 5V, Vo

2·30

n

dc electrical characteristics (can't)

C

CD4013BC (Note 2)

~

0
.....

W
ttJ

/

--40°C
PARAMETER

UNITS

laH

liN

Low Level Output Current

High Level Output Current

Input Current

MAX

MIN

TVP

MAX

MIN

MAX

= 5V, Va = 0.5V or 4.5V
VDD = IOV, Va = 1.0V or 9.0V
VDD = 15V, Va = 1.5Vor 13.5V
VDD = 5V, Va = O.4V
VDD = 10V, Va = 0.5V
VDD = 15V, Va = 1.5V
VDD = 5V, Va = 4.6V
VDD = 10V, Vo = 9.5V
VDD = 15V, Vo = 13.5V
VDD = 15V, VIN = OV
VDD = 15V, VIN = 15V

3.5

3.5

3.5

V

7.0

7.0

7.0

V

11.0

11.0

11.0

V

0.52

0.44

0.88

0.36

mA

1.3

1.1

2.25

0.9

mA

3.6

3.0

8.8

2.4

mA

-D. 52

-D.44

-D.88

-D.36

mA

-1.3

-1.1

-2.25

-D.9

mA

-3.0

-8.8

-3.6

-10- 5
10-5

-D.3
0.3

-2.4

mA

-D.3

-1.0

IJ.A

0.3

1.0

IJ.A

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed, they are not meant to imply
that the devices should be operated at these limits. The table of "Recommended Operating Conditions" and "Electrical Characteristics" provides
conditions for actual device operation.
Note 2:

VSS = OV unless otherwise specified.

ac electrical characteristics

PARAMETER

TA

= 25°C,

CL

= 50 pF, ~~:.?OO~unless otherwise specified.

CONDITIONS

MIN

TYP

MAX

VDD

200

400

ns

VDD

80

160

ns

65

130

ns

100

200

ns

50

100

ns

40

80

ns

UNITS

CLOCK OPERATION
tpHL. or

Propagation Delay Time

tPLH

tTHL, or

Transition Time

tTLH

tWL.or

Minimum Clock Pulse Width

tWH

tRCL, tFCL Maximum Clock Rise and Fall Time

tsu

fCL

Minimum Set·Up Time

Maximum Clock Frequency

= 5V
= 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDb = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V

. 2.5

100

200

ns

40

180

ns

32

65

ns

15

IJ.S

10

J.ls

5

J.ls

20

40

ns

15

30

ns

12

25

.5

ns
MHz

6.2

12.5

MHz

7.6

15.5

MHz

SET AND RESET OPERATION
tPHL(R),

Propagation Delay Time

tPLH(S)

= 5V

150

300

ns

VDD = 10V

65

130

ns

= 15V
VDD = 5V
VDD = 10V
VDD = 15V

45

90

ns

90

180

ns

40

80

ns

25

50

ns

Any Input

5

7.5

pF

VDD
VDD

!WH(R),

Minimum Set and Reset

tWH(S)

Pulse Width

CIN

Average Input Capacitance

s:

........

n
C

1101< 1.0pA

High Level I nput Voltage

VDD

laL

85°C

CONDITIONS
MIN

VIH

25°C

2·31

~

0
.....

W

n

C

U

al

M

schematic diagram

"'"
~

C
U

"~

al
M

5

SETo----.----------------------------------------------~
MASTER SECTION
SLAVE SECTION

~

c
u

CL

RESET o-______________.......______
CL_______---'

VDO

VOD

CLOCK

0------.

d

H :r
e.

1
Vss

CL

1
Vss

/

ALL P·SUBSTRATES

All .""TRATES

(1 ~ )
r-

CONNECTED TO VOD

qE

I CONNECTED TO Vss

2·32

(")

1~9ic

o

diagram

~

9

w

OJ

s:

.........

SETa---------~--------------------------------------~

(").

Ci

MASTEn SECTION

o

SLAVE SECTION

~

o
w

CL

~

TG

OJ

(")

OATA
CL

CL

RESETo------------------4~--------------~

cL

BUFFERED OUTPUTS

CL

Q

CL

switching time waveforms

VDD--------+--~------------~

CLOCK vss------;..;.;.;..I1

DATA
DATA VDD

VDD--------~~--------_4--~,_------------

Q

DR ii Vss

----------+----_------01'
tTHL

QORiiVOD----------+-----------~

Vss------------------------~~------------

(.)

~

o

~

Q

(.)

........

:E

.~

o

~

Q

(.)

CD4014M/CD4014C 8-stage static shift regi!;ter
general description
featun~s
~he

CD4014M/CD4014C is an 8-stage parallel input/
serial output shift register. A parallel/serial control
input enables individual "jam" inputs to each of 8stages. Q outputs are available from the sixth, seven'th
and eighth stages.

• Synchronous operation
• Wide supply voltage range
• High noise immunity
• Medium speed operation
clock rate .:It Voo - Vss = 10V
• Fully static operation

When the parallel/serial control input. is in the logical
"0" state, data is serially shifted into the register
synchronously with the positive transition of the clock.
When the parallel/serial control input is in the logical
"1" state, data is jammed into each stage of the register synchronously with the. positive transition of the
clock ..

. logic diagram

•

3.0V to 15V .
0.45 Vee typ
5 MHz typ

Low power

applications
•

Parallel to serial conversion

•

General purpose register

-PARALLEL
INPUT

PARALLEL 9
SERIAL
CONTROL

SERIAL 11
INPUT

CLOCK

..

10

TERMINAL NO. 16· Voo
TERMINAL NO.8· GNO

truth. table

connection diagram
PAR
IN

aUF
OUT

Voo

SER
IN

01
15

116

14

13

12

II

CLK

PARI
SER
CO NT

10

CL·

9

l-

2

I

3

08

4

5

6

1

PAR
IN

8UF
OUT

8UF
OUT

PI n

a1
(INTERNAL)

an

1

0

0

0

0

1

1

0

1

0

../

X

1

0

1

0

1

../

X

1

1

1

1

1

../

0

0

X

X

0

On 1

../

1

0

X

X

1

On 1

"-

X

X

X

X

01

On

LEVEL CHANGE

8
1

06

Pl1

x
x

• =

8

PARALLEL!
SERIAL
CONTROL

../

../

r--

SERIAL
INPUT

v..
PAR IN
TOP VIEW

2··34

X = DON'T CARE CASE

NO

CHANGE

(')

absolute maximum ratings

C

(Note 1)

-s:
~

o

Voltage at Any Pin
Vss - 0.3V to Voo + 0.3V
Operating Temperature Range
-55°C to +125°C
CD4014M
-40°C to +85°C
CD4014C
-65°C to +150°C
Storage Temperature Range
Package Dissipation
500 mW
Operating Voo Range
Vss + 3V to Vss + 15V
300°C
Lead Temperature (Soldering, 10 seconds)

dc electrical characteristics

~

........
(')

C

~

o

~

(')

CD4014M
LIMITS

PARAMETERS

-55°C

CONDITIONS

25°C

UNITS

125°C

TYP

MAX

Quiescent Device Current (I L )

V 00 = 5V
Voo= lOV

5
10

0.5
1

5
10

300
600

I1A
I1A

Quiesc~nt

Device Dissipation
Package (Po)

V 00 = 5V
Voo=10V

25
100

2.5
10

25
100

1,500
6,000

I1W
I1W

Output Voltage
Low·Level (VOL)

V oo =.5V
Voo= 10V

0.01
0.01

0
0

0.01
0.01

0.05
0.05

Output Voltage
High-Level (V CH )

V 00 = 5V
Voo=lOV

4.99
9.99

4.99
9.99

5
10

4.95
9.95

V
V

Noise Immunity
(All Inputs) (V NL )

Vo=O.BV, Voo = 5V
Vo = lV, Voo = 10V

1.5
3

1.5
3

2.25
4.5

1.4
2.9

V
V

Noise Immunity
(All Inputs) (V NH )

Vo
Vo

= 4.2V, Voo = 5V
= 9V, Voo = lOV

1.4
2.9

1.5
3

2.25
4.5

1.5
3

V
V

Output Drive Current
N-Channel (IoN)

Vo = 0.5V, Voo
Vo = 0.5V, Voo

5V
lOV

0.15
0.31

0.12
0.25

0.3
0.5

0.OB5
0.175

mA
mA

Output Drive Current
P·Channel (loP)

Vo = 4.5V, Voo = 5V
Vo = 9.5V, Voo = lOV

-0.1
-0.25

-O.OB
-0.20

-0.16
-0.44

-0.055
-0.14

mA
mA

MIN

=
~

TYP

MAX

MIN

Input Current (II)

MIN

TYP

MAX

V
V

pA

10

dc electrical cha racteristics

CD4014C
LIMITS

PARAMETERS

-40°C

CONDITIONS

85°C

25°C
MAX

Voo = 5V
Voo = 10V

50
100

0.5
1

50
100

700
1,400

I1A

Quiescent Devi,ce Dissipation
Package (Po)

Voo = 5V
Voo = 10V

250
1,000

2.5

10

250
1,000

3,500
14,000

I1W
I1W

Output Voltage
Low-Level (VOL)

Voo = 5V

0.01
0.01

0
0

0.01
0.01

0.05
0.05

TYP

. VbD~10V

MAX

MIN

TYP

MAX

TYP

Quiescent Device Current (Id

MIN

MIN

UNITS

I1A

V
V

Output Voltage
High-Level (V OH )

Voo = 5V
Voo = 10V

4.99
9.99

4.99
9.99

5
10

4.95
9.95

V
V

Noise Immunity
(All Inputs) (V NL )

Vo = 0.8V, Voo = 5V
Vo= lV,
Voo=10V

1.5
3

1.5
3

2.25
4.5

1.4
2.9

V
V

Noise Immunity
(All Inputs) (V NH )

Vo = 4.2V, Voo = 5V
Vo = 9V,
Voo = 10V.

1.4
2.9

1.5
3

2.25
4.5

1.5
3

V
V

Output Drive Current
N-Channel (IoN)

V o =0.5V, Voo = 5V
Vo = 0.5V, Voo = 10V

0.072
0.12

0.06
0.1

0.3
0.5

0.05
0.08

mA
mA

Output Drive Current
P-Channel (loP)

Vo = 4.5V, Voo = 5V
Vo = 9_5V, Voo = 10V

-0.04
-0.08

mA
mA

-0.05
-0.1

-0.06
-0.12

Input Current (II)

-0.16
-0.44

pA

10

2-35

-

(.)
~
....

ac electrical characteristics

CD4014M

0

~

LIMITS

C

PARAMETERS

(.)

'":E
~
....
0

,~

C

(.)

CONDITIONS

UNITS
MIN

TYP

MAX

Propagation Delay Time (t PH l. t PLH )

Voo = 5V
V OD = 10V

300
100

750
225

ns

Transition Time (tTHl. tTlH)

Voo = 5V
Voo = 10V

150
75

300
125

ns
ns

Minimum Clock Pulse Width (t Wl • t WH )

Voo = 5V
Voo = 10V

200
100

500
175

ns

Minimum High Level Parallel/Serial Control Pulse Width

Voo = 5V
Voo = 10V

200
100

500
175

ns

15
15

f..Ls
f..Ls

350
80

ns
ns

(tWH(P/S))
Clock Rise Time (t,Cl) qr Clock Fall Tim~ (t ICl )

Voo = 5V
Voo = lOV.

Set·up Time

Voo = 5V
Voo = 10V

Maximum Clock Frequency (f cl )

Voo = 5V
Voo = 10V

Input Capacitance (C I ) (Note 2)

Any Input

100
50
1
3

2.5
5

ns

ns

ns

MHz
MHz
pF

5

(

ac electrical characteristics

CD4014C
LIMITS

PARAMETERS

CONDITIONS

UNITS
MIN

TYP

MAX

Propagation Delay Time (t PHl • t PLH )

Voo = 5V
Voo = 10V

300
100

1,000
300

ns
ns

Transition Time (t THl • tTlH)

Voo = 5V
V OD - 10V

150
75

400
150

ns

Minimum Clock Pulse Width' (t Wl • t WH )

Voo = 5V
Voo = 10V

200
100

830
200

ns
ns

Minimum High Level Parallel/Serial Control Pulse Width
(tWH(P/S))

Voo = 5V
Voo = 10V

200
100

830
200

ns
ns

Clock Rise Time (t,Cl) or Clock Fall Time (tICl)

Voo ;, 5V
Voo = 10V

15
15

f..LS
f..LS

Set·up Time

Voo = 5V
Voo = 10V

500
100

ns
ns

Maximum Clock Frequency (f cl )

Voo = 5V
Voo = 10V

Input Capacitance (C,) (Note 2)

Any Input

100
50

0.6
2.5

2.5
5
5

ns

MHz
MHz
pF

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of-the device cannot be guaranteed. Except for "Operating Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for
actual device operation.
Note 2: Capacitance is gUilranteed by periodic testing.

2-36

n

c

~

o

U1

~

"'-

n
c

CD4015M/CD4015C dual 4-bit static register

~

o

general description

features

The CD4015M/CD4015C consist of two identical, independent, .4-stage serial-input/parallel-outputregisters.
Each register has independent "Clock" and" Reset" inputs as well as a single serial "Data" input. "0" outputs
are available from each of the four stages on both
registers. All register stages are D-type, master-slave
flip-flops. The logic level present at the data input is
transferred into the first register stage and shifted over
one stage at each positive-going clock transition. Resetting of all stages is accomplished by a high level on the
reset line. Register expansion to 8 stages using one
CD4015M/CD4015C package, or to more than 8 stages
using additional CD4015M/CD4015C is possible. All
inputs are protected from static discharge by diode
clamps to V DO and Vss.

•

Wide supply voltage range

•

High noise immunity

U1

3.0V to 15V
0.45 Vee typ ,
9 MHz (typ) clock rate
at Voo - Vss = 10V

•

Medium speed
operation

•

Fully static operation

applications
•

Serial-input/parallel-output data queueing

• Serial to parallel data conversion
•

General purpose register

connection diagram and truth table
Voo

DATA.

RESET.

R

a1

an

0

0

0

°n-1

1

0

1

°n-1

X

0

01

On

X

1

0

0

CL&

D

.../
-f

'X

Level change.
X Don't care case.

&

CLOCK.

Q4q

ol",

Q2A

01...

RESET...

DATAA,

Vss

logic diagrams

2-37

(No change)

n

(.)

-

it)

o

~

c

(.)

........

~

-

absolute maximum ratings

(Note 1)
-65°C to +150°C
Storage Temperature Range
_Package Dissipation
500mW
Operating Voo - Vss Range
3.0V to 15V
300°C
Lead T'C!mperature (Soldering, 10 seconds)

Voltage at Any Pin
Vss -O.3V to Voo + O.3V
Operating Temperature Range
-55°C to +125°C
CD4015M
-40°C to +85°C
CD4015C

it)

o

~

dc electrical characteristics

CD4015M

c

LIMITS

(.)

-SSoc

CONDITIONS

PARAMETER

MIN

TYP

2SoC
MAX

MIN

12SoC

TYP

MAX

MIN

TYP

UNITS
MAX

Quiescent Device
Current (I L )

Vaa
Vaa

= 5V
= 10V

5
10

0.5
1

5
10

300
600

J1A
J1A

Quiescent Device Dissipation/Package (Po)

Vao
Voo

= 5V
= 10V

25
100

2.5
10

25
100'

1500
6000

J1W
pW

Output Voltage Low
Level (VOL)

Voo
Voo

= 5V
= 10V

0.01
0.01

0
0

0.01
0.01

0.05
0.05

Output Voltage High
Level (V OH )

Voo
Voo

= 5V
= 10V

4.99
9.99

4.99
9.99

5
10

4.95
9.95

Noise Immunity (Any
Input) (V NL )

Voo
Voo

= 5V, Vo = O.BV
= 10V, Vo = 1.0V

1.5
3

1.5
3

2.25
4.5

1.4
2.9

Noise Immunity (Any
Input) (V NH)

Voo
Vaa

= 5V, Va = 4.2V
= 10V, Va ~ 9.0V

1.4
2.9

1.5

3

2.25
4.5

1.5
3

Output Drive Current
N-Channel (IoN)

Voo
Voo

= 5V, Va = 0.5V
= 10V, Va = 0.5V

0.15
0.31

0.12
0.25

0.3
0.5

0.OB5
0.175

mA
mA

Output Drive Current
P-Channel (loP)

Voa = 5V, Va = 4.5V
Voo = 10V, Va = 9.5V

-0.1
-0.25

-o.OB
-0.20

-0.055
-0.14

mA
mA

-0.16
-0.44

V
V

-

dc electrical characteristics

V
V
V
V

pA

. 10

I nput Current (II)

V
V

CD4015C
LIMITS

PARAMETER

-40°C

CONDITIONS
MIN

Quiescent Device
. Current (I L )

Voo = 5V
Voo = 10V

TYP

85°C

25°C
MAX

TYP

MAX

50
100

0.5
1

50
100
250
1000

MIN

Quiescent Device Dissipation/Package (Po)

Voo
Voo

= 5V
= 10V

250
1000

2.5
10

Output Voltage Low
Level (VOL)

Voo
Voo

= 5V
= 10V

0.01
0.01

0
0

Output Voltage High
Level (V aH )

Voo
Voo

= '5V
= 10V

Noise Immunity (Any
Input (V NL )

MIN

\

. 0.01

TYP

UNITS
MAX
700
1400

)1A
J1A

3500
14000

)1W
J1W

0.05
0.05

0.01

V
V

4.99
9.99

4.99
9.99

5
10

4.95
9.95

V
V

Voo = 5V, Va = O.BV
Voo = 10V, Va = 1.0V

1.5
3

1.5
3

2.25
4.5

1.4
2.9

V
V

Noise Immunity (Any
Input (V NH )

Voo = 5V, Va = 4.2V
Voo = 10V, Va = 9.0V

1.4
2.9 .

1.5
3

2.25
4.5

1.5

3

V
V

Output Drive Current
N-Channel (IoN)

Voo
Voo

= 5V,
= 10V,

0.072
0.12

0.06
0.1

0.3
0.5

0.05
0.08

mA
mA

Output Drive Current
P-Channel (loP)

Voo
Voo

= 5V, Va = 4.5V
= 10V, Va = 9.5V

-0.04
-0.08

mA
mA

Va
Va

= 0.5V
= 0.5V

-0.06
-0.12

-0.05
-0.1

-0.16
-0.44
10

Input Current (Id

pA

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for
actual device operation.

2-38

(')

ac electrical characteristics

C

CD4015M

~

I

LIMITS
PARAMETER

CONDITIONS

MIN

TVP

MAX

UNITS

...o
U1

3:

........

CLOCKED OPERATION

(')

C

Propagation Delay Time (tPHl. tPLH)

Voo
Voo

= 5V
= 10V

250
100

750
225

ns
ns

o

Transition Time .(tTHl. tTlH)

Voo
Voo

= 5V
= 10V

150
75

300
125

ns
ns

(')

Minimum Clock Pulse Width (t Wl • t WH )

Voo
Voo

= 5V
= 10V

100
50

500
175

ns
ns

Clock Rise and Fall Time (t,Cl. tlCl)

Voo
Voo

= 5V
= 10V

15
15

J.1s

Set·Up Time

Voo
Voo

= 5V
= 10V

350
80

ns
ns

Maximum Clock Frequency (f cl )

Voo
Voo

= 5V
= 10V

50
25
1
3

Input Capacitance (C I )

IlS

4
9

MHz
MHz

5

pF

RESET OPERATION
Propagation Delay Time (tp~l (Rl)

Voo
Voo

= 5V
= 10V

200
100

750
225

ns
ns

Minimum Set and Reset Pulse Widths
(tWH(RI)

Voo
Voo

= 5V
= 10V

150
100

500
175

ns
ns

I

ac electrical characteristics

CD4015C
LIMITS

PARAMETER

CONDITIONS

MIN

TVP

MAX

UNITS

CLOCKED OPERATION
Propagation Delay Time (tPHl. tPLH)

Voo
Voo

= 5V
= 10V

250
100

1000
300

ns
ns

Transition Time (t THl • t TlH )

Voo
Voo

= 5V
= 10V

150
75

400
150

ns
ns

Minimum Clock Pulse Width (t Wl • t WH )

Voo
Voo

= 5V
= 10V

100
50

830
200

ns
ns

Clock Rise and Fall Time

Voo
Voo

= 5V
= 10V

15
15

J.1s

Set· Up Time

Voo
Voo

= 5V
= 10V

500
100

ns
ns

Maximum Clock Frequency (f cl )

Voo
Voo

= 5V
= 10V

Input Capacitance (C I )'

50
25
0.6
2.5

4
9

IlS

MHz
MHz

\

pF

5

RESET OPERATION
Propagati.on Delay Time (tpHl(RI)

Voo
Voo

= 5V
= 10V

200
100

1000
300

ns
ns

Minimum Set and Reset Pulse Widths
(tWH(RI)

Voo
Voo

= 5V
= 10V

150
100

830
200

ns
ns

2-39

~

...
U1

(.)

....
Lt)

o

schematic diagram

qo

-0

(.)

'":E
....

Lt)

o

qo

o

(.)

2-40

(')

C

~

o
....

0)

3:

........
(')

C

~

CD4016M/CD4016C quad bilateral switch

....o

0)

general description

(')

The CD4016M/CD4016C is a quad bilateral switch
which utilizes P-channel and N-channel complementary MOS (CMOS) circuits to provide an
extremely high "OFF" resistance and low "ON"
resistance switch. The switch will pass signals in
either direction and is extremely useful in digital,
switching.

•

features

applications

•

Extremely low le'akage

Transmits frequencies up
to 10 MHz

•

3V to 15V

Analog signal switching/multiplexing

•

Wide supply voltage range

•

High noise immunity

0.45 V cc typo

•

Signal gating

•

Wide range of digital
and analog levels

±7.5 VPEAK

•

Squelch control

•

Chopper

•

Low "ON" resistance

•
•

•

300n typo
Voo - Vss = 15V

Matched switch
characteristics

.0.RON = 40n typo

High "ON/OFF" output
voltage ratio
High degree of linearity

Vis = 5 Vp-p
Voo - Vss = 10V
.
RL = 10 kn

•

Modulator

•

Demodulator

•

Commutating switch

65 dB typo

•

Digita! signal switching/multiplexing

@ f is =, 10 kHz
RL = 10k

•

CMOS logic implementation

•

Analog to digital/digital to analog conversion

.5% distortion typo
@ fis = 1 kHz

•

Digital control of frequency, impedance, phase,
and analog-signal gain
'

schematic and connection diagrams
Voo

"CONTROL
Voo J1VOLTAGE (Vel

U"O-"'-.

5"0-",-.

Vss

INPUT SIGNALS (VIS)
TERMINAL NO •• t. 4, B.ll

IN

~

~~

OUTPUT SIGNALS (Vos)
TERMINAL NOS, 2. 3, 9. 10

r-r:

OUT

OUT

OUT

Note 1: All sw;tch P·channel substrates Ife internally connected to terminal No. 14.
Note 2: Alilwitch N·channel substrates Ire internallv connected to terminal No.7.

Signal·level range: Vss

cona

Normal operation: Control·linebiasing,
switch ON Vc 'T'

=Voo , switch OFF Vc

"0'"

Vss

Order Number CD4016MD
See Package 1

OUTPUTA l
oUTPuTa

< VIS> Voo

Order Number CD4016MF
See Package 4
Order Number CD4016CJ or CD4016MJ
See Package 16
Order Number CD4016CN
See Package 22

l

5

2-41

to)

CD
~

oqo
c·

to)

........

absolute maximum ratings
Voltage at Any Pin (Note 1)
Operating Temperature Range CD4016M
CD4016C
CHARACTERISTIC

~

o
qo

c

SYMBOL

1-_ _ _ _- r_ _L:.:I:.:.:M::..;IT~S_

TEST CONDITIONS

0

0

_55 C
MIN
Quiescent Dissipation
per Package
All Switches "OFF"

to)

All Switches "ON"

Vss
Ve
Vis=VOS

Threshold Voltage
N-Channel
P-Channel

MAX

MIN

VOLTS
APPLIED
+10
GND
+10

TERMINALS
14
7
5,6,12,13
1-4,8-11

V DD

TYP

25 C

VOLTS
APPLIED
+10
GND
GND.
~ +10
::; +10

TERMINALS
14
7
5,6,12,13
1,4,8,11
2,3,9,10

_65°C to +150°C
500mW
300°C
Vss + 3V to Vss + 15V

Storage Temperature Range
Package Dissipation
Lead Temperature (Soldering, 10 seconds)
Operating V DD Range

electrical characteristics CD4016M

~

CD

V55 - O.3V to V55 + 15.5 V
-55°C to +125°C
-40°C to +85°C

TYP

_ _ _ r - - - - _ _ l UNITS
0
125 C

MAX

MIN

TYP

MAX

0.1

300

pW

0.1

300

pW

< +10

VTHN

~::=1~~~lOv,or15V

1.7

1.5

1.3

VTHP

~::=l~~,~OV, or 15V

-1.7

-1.5

-1.3

SIGNAL INPUTS (V~) AND OUTPUTS (V o,)

+7.5V

-7.5V

+7.5V

120

360

200

400

300

600

-7.51/

120

360

200

400

300

600

'0.25V

130

775

280

850

470

1230

+5V
+5V

-5V

"ON" Resistance
+.15V

!::. "ON" Resistance
Between Any 2
of 4 Switches

Sine Wave Response

RL = 10 kll
f" = 1 kHz

• (Distortion)

Input or Output

Leakage-Switch "OFF"
(Effective "OFF"
Resistance)

250

660

400

960

600

250

660

400

960

325

18'10

580

2000

900

2600

t15V

120

360

200

400

300

600

+0.25V

120

360

200

400

300

9.3V

150

775

300

850

490

1230

+10V

130

600

250

660

400

960

+0.25V

130

600

250

660

400

960

5.6V

300

lB70

560

2000

880

2600

OV

+7.5V

-7.5V

+5V

-5V

!5V

15

+5V

-5V

5V(p-p)

0.4

± 7.5V

10

+7.5V

-7.5V

+5V

-5V

V"
+7.5V
-7.5V
+5V
-5V

~100

pA

~100

Note 2
Note 2

125
125

nA

20 Log lO

~

40

MHz

1.25

MHz

0_9

MHz

= -3dB

V;, = 5V(p-p) V DD = +5V, Ve = Vss = -5V
20 Log lO

Crosstalk Between dny 2
of the 4 switches
(Frequency at -50 dB)

RL = 1 kn
V,,(A) =
5V(p·p)

Input

~

= -50 dB

V"

VetA) = Vo~ = +5V
Ve(B) = Vss = -5V
20 Log ,O

~i~i

= -50 dB

V OD = +5V, Ve = Vss" -5V

Output

Cos

4

Feedthrough

CIOS

0.2

Signal Output

%

(Nott~ 3)

Ve" Vss

RL = 1 kll

Feedthrough
Switch "OFF"

Propagation Delay
Signal I nput to

600

Ve = V DD = +5V, Vss = -5V

Switch "ON"
(Sine Wave Input)

CONTROL

600

130

;o.25V

+10V

V OD

Frequency Response-

Capacitance

OV

130

-5V

"

Ve = V DD = +10V, Vss = GND, C L = 15 pF
V;, = 10V (square wave)
= 20 ns (input signal)

pF

10

tr:::: tf

(Vel
V DD - Vss = 15V, 10V, 5V
I,s = 10pA

Switch Threshold Voltage

07

2.9

0.5

Vo~ - Vss = 10V

Input Current

Ve ~

"'DD -

1.5
±10

Vss

Control Input to

Signal Output
Turn "ON"
PropagatIon Delay
Maximum Allowilble
Control Input
Repetition Rate

0.2

2.4

V

pA
pF

Average Input Capacitance
Crosstalk -

2.7

V DD - V ss '" 10V
Ve = 10V

RL

= 10 kn

50

mV

(square wave)
trc = tfc =

20 ns

V,,< 10V. C L = 15 pF

20

V DO = 10V, Vss = GND, RL = 1 kn
C L = 15 pF
Ve = 10V (square wave)
tr = tf =

10

MHz

20 ns

Note 1: The device should not be connected to circuits with the power on,

2·42

Note 2: ±10 x 10.3 ,

Note 3: Symmetrical about OV,

(")

electrical characteristics
CHARACTERISTIC

C

CD4016C

SYMBOL

~

TEST CONDITIONS
MIN
TEAMINALS
14
7
5,6,12,13
1,4,8,11
2,3,9,10

VOLTS
APPLIED
+10
GND
GND
:::: +10
:::: +10

TEAMINALS
14
7
5,6,12,13
1-4,8-11

VOLTS
APPLIED
+10
GND
+10
:::: +10

Quiescent Dissipation

per Package
Voo
Vss
Vc

All Switches "OFF"

PT

V"
VOl

Voo
Vss
Vc

All Switches "ON"

VIS=

Threshold Voltage
N·Channel
P·Channel

Vas

LIMITS
2SoC

-40°C
TYP

MAX MIN

TYP

UNITS

8SoC
MAX

MIN TYP

MAX

(")

C

S

0.1

S

80

Il W

(")

0.1

S

los = 10 IlA
Voo = SV, 10V, or 15V

1.7

VTHP

los = 10llA
Voo = 5V, 10V, or 15V

-1.7

1

5

80

IlW

1.5

1.3

V

-l.S

-1.3

V

SIGNAL INPUTS (Vis) AND OUTPUTS (V o,)
Vc = Voo

Vss

V"
+7.5V

130

370

200

400

260

520

+7.5V

-7.5V

-7.5V

130

370

200

400

260

520

±0.25V

160

790

280

850

400

1080

250

+SV
-5V

"ON" Aesistance

AON

AL

=

10k!)
+15V

OV

+10V

6 "ON" Aesistance
Between Any 2
of 4 Switches
A L =10kn
f" = 1 kHz

Sine Wave Response

(Distortion)
I nput Or Output
Leakage-Switch "0 F F"
(Effective "OFF"
Aesistance)

610

660

340

840

150

610

250. 660

340

840

±0.2SV

370

1900

580

2000

770

2380

+15V

130

370

200

400

260

520

+0.25V

130

370

200

400

260

520

9.3V

180

790

300

850

400

1080
840

+10V

150

610

250

660

340

+0.25V

150

610

250

660

340

2380

5.6V

350

1900

560

2000

750

2380

-7.5V

±7.5V

10

+5V

-5V

±5V

15

+5V

-5V

5V(p-p)

0.4

n

n

n

n

n

%

INote 31

Voo

Vc = Vss

+7.5V

-7.5V

V"
+7.5V
-7.5V
+5V
-5V

-5V
Vc

AL=lkr2

150

-5V

+7.5V

+5V

Frequency AesponseSwitch "ON"
(Sine Wave Input)

'OV'

±100
±100
(Note 2
(Note 2

pA
125
125

nA

= Voo = +5V, Vss = -5V

20L09,o~=-3dB

40

MHz

1.25

MHz

0.9

MHz

ViS = 5V(p-p) Voo = +5V, Vc = Vss = -5V
Feedthrough
Switch "OFF"

20 Log lO VOl = -50 dB
V"

Crosstalk Between any 2
of the 4 switches
(Frequency at -50 dB)
Capacitance

AL = 1 kr2
V,,(A) =
5V(p-p)

Input
OutpuT
Feedthrough

Propagation Delay
Signal I nput to
Signal Output

VelA) = Voo = +5V
Ve(B) = Vss
20 Log,o

Voo = +5V, Ve = Vss

=

~:;~i

=

=

-5V

-50dB

-5V
pF

Cos
. C,OS

0.2
Vc = Voo = +10V, Vss = GND, CL = 15 pF
V" = 10V (square wave)
= t,:= 20 ns (input signal)

10

tr

CONTROL (Vc)
Switch Threshold Voltage

V" < Voo

Voo - Vss
liS = 10llA

=

15V, 10V, 5V

0.5

Voo - Vss = 10V
Ve ~ Voo - Vss

Input Current

1.5
±10

2.7

V

pA
pF

Average Input Capacitance
Crosstalk Control Input to
Signal Output

Voo - Vss = 10V
Ve = 10V
(square wavel

50

Turn "ON"
Propagation Delay

t,t,. ~ ttc

Maximum Allowable
Control Input
Aepetition Rate

Voo 10V, Vss = GND, AL =
C L = 15 pF
Vc ---10V (squar. wave)
I, - tf:= 20 ns

= 20

ns

V,,< 10V, CL = 15 pF

mV

20

nn
10

Note 1: The device should not be connected to circuits with the power on.

2-43

~

o
....

en

VTHN

+5V

o
....
en
s:
.......

Note 2: ±10 x 10-3 .

MHz

Note 3: Symmetrical about OV.

(.)
CD

...

0

~

C

(.)

.......
.-

typical ON resistance characteristics

~-

...

CD

0

CHARACTERISTIC·

Vee
(V)

~

C

(.)

SUPPLY
CONDITIONS

RON

+15

RON (max.)

+15

RON

+10

RON (max.)

+10

RON
RON (max.!

Vss
(V)

(m

(m

V's
(V)

200

+15

200

'+15

200

+5
-7.5

RON (max.!

+7.S

-7.5

+5

-S

+5

-5

RON

+2.5

-2.5

RON (max.)

+2.5

-2.5

RL - 100 kn
VALUE
(rl)

Vis
(V)

ISO

+15

200

300

+11

300

+9.3

320

+9.2

290

+10

250

+10

240

+10

300

250

500

+7.4

560

+5.6

610

+5.5

S60

+5

470

+5

450

+5

600

+7.5

RON (max.!

VALUE

290

+5

RL ~.10kn

V's
(V)

VALUE

200

RON

RON

LOAD CONDITIONS
RL -I kn

5S0

800
+2.7

1.7k

+4.2

7k

+2.9

33k

200

+7.5

200

+7.5

ISO

+7.5

200

-7.5

200

-7.5

ISO

-7.S
±0.25

290

±0.25

280

±25

400

260

+5

250

+5

240

+S

310

-5

2S0

-S

240

-S
±0.25

600

±0.25

580

±0.25

760

590

,+2.5

450

+2.5

490

+2.5

720

-2.5

520

-2.5

520

-2.5

±0.25

300k

±0.25

S70k

±0.25

232k

*Variation from a perfect switch: RON

2·44

~

0.11.

CD4017BM/CD4017BC decade counter/divider with 10 decoded outputs
CD4022BM/CD4022BC divide-by-8 counter/divider with 8 decoded outputs
general description

features

The CD4017BM/CD4017BC is a 5-stage divide-by-l0
Johnson counter with 10 decoded outputs and a carry
out bit.

•

Wide supply voltage range

•

High noise immunity

•

Low power
TTL compatibility

•

Medium speed operation

•
•

Low power
Fully static operation

The CD4022BM/CD4022BC is a 4-stage divide-by-8
Johnson counter with 8 decoded outputs and a carryout bit.
These counters are cleared to their zero count by a
logical "1" on their reset line. These counters are advanced on the positive edge of the clock signal when the
clock enable signal is in the logical "0" state.
The configuration of the CD4017BM/CD4017BC and
CD4022BM/CD4022BC permits medium speed operation
and assures a hazar-d free counting sequence. The 10/8
decoded outputs are normally in the logical "0" state
and go to the logical "1" state only at their respective
time slot. Each decoded output remains high for 1 full
clock cycle. The carry-out signal completes a full cycle
for every 10/8 clock input cycles and is used as a ripple
carry signal to any succeedi~g stages.

3.0V to 15V
0.45 VDO typ
fan out of2
driving 74L
or 1 driving
74LS
5.0 MHz typ
with 10V VDD
10,uW typ

applications
•
•
•

Automotive
Instrumentation
Medical electronics

•
•
•

Alarm systems
Industrial electronics
Remote metering

connection diagrams

CD4017B

CD4022B

Dual-In-Line and Flat Package

16

DECODED OUTPUT "5"

15

DECODEO OUTPUT "I"

14

DECODED OUTPUT "0"

Dual-In-Line and Flat Package

VDD

DECODED OUTPUT "1~

RESET

DECODED OUTPUT "0"

16
15

VDD
RESET

CLOCK

DECODED OUTPUT ''2''

DECODED OUTPUT "2"

CLOCK ENABLE

DECODED OUTPUT ''SH

CLOCK ENABLE

DECODED OUTPUT "6"

CARRY·OUT

DECODED OUTPUT "6"

CARRY.{)UT

DECODED OUTPUT "7"

DECODED OUTPUT "9"

NC

DECODED OUTPUT "3"

DECODED OUTPUT "4"

DECODED OUTPUT "3"

DECODED OUTPUT "."

vss

vss

TOP VIEW

CLOCK

DECODED OUTPUT "4"
DECODED OUTPUT '7"
NC

TOP VIEW

2-45

(.)

m

absolute' maximum ratings

recommended operating conditions

o

(Notes 1 and 2)

(Note 2)

c

voo dc Supply Voltage
-o.S to +18 VOC
VIN Input Voltage
-o.S to VOO +O.S VOC
c
-6SoC to +IS0 C
TS Storage Temperature Range
Po Package Oissipation
SOOmW
TL Lead Temperature (Soldering, 10 seconds)
300°C

VOO dc Supply Voltage
VIN Input Voltage
T A Operating Temperature Range
C040178M, C04022BM
C04017BC,C04022BC

N
N

~

(.)

.......

:E

m

+3 to +IS VOC
to VOO VOC

o

-SSoC to + 12SoC
-40°C to +8SoC

N
N

o

~

c

(.)

ci

m

dc electrical ch a racte ristics

~

o

PARAMETER

~

c

.(.)

m

-55°C

. CONDITIONS

100

Quiescent Oevice Current

VOL

Low Level Output Voltage

S

= 5V
= 10V
VOO = 15V

c

(.)
VOH

High Level Output Voltage

Low Level Input Voltage

10L

10H

High Level Input Voltage

Low Level Output Current

High Level Output Current

MAX

UNITS

0.3

5

150

0.5

10

300

IJ.A

20

1.0

20

600

IJ.A

IJ.A

1101< 1. OIJ. A
VOO

0.05

0

0.05

0.05

V

VOO

0.05

0

0.05

0.05

V

0.05

0

0.05

0.05

V

1101< 1.01J.A
VOO

4.95

4.95

5

4.95

VOO

9.95

9.95

10

9.95

V

14.95

14.95

15

14.95

V

V

IIOI<1.0IlA
VOO

1.5

1.5

1.5

V

VOO

3.0

3.0

3.0

V

4.0

4.0

4.0

V

1101< 1.0llA

= 5V, Vo = 0.5V or 4.5V
= 10V, Vo = 1.0Vor 9.0V
VOO = 15V, Vo = 1.5Vor 13.5V
VOO = 5V, Vo = O.4V
VOO = 10V, Vo = 0.5V
VOO = 15V, Vo =-1.5V
VOO = 5V, Vo = 4.6V

VOO

3.5

3.5

3.5

V

VOO

7.0

7.0

7.0

V

VOO = 10V, Vo

= 9.5V

= 13.5V
VOO = 15V, VIN = OV
VOO = 15V, VIN = 15V

Input Current

MIN

5

VOO'= 15V, Vo

liN

MAX

10

= 5V, Vo = 0.5V or 4.5V
= 10V, Vo = 1.OV or 9.0V
VOO = 15V, Vo = 1.5Vor 13.5V

VIH

TYP

VOO

= 5V
= 10V
VOO = 15V

VIL

MIN

VOO

= 5V
= 10V
VOO = 15V

~

125°C

25°C
MAX

MIN

.......
~
l"'-

CD4017BM, CD4022BM (Note 2)

11.0

11.0

11.0

V

0.64

0.51

0.88

0.36

rnA

1.6

1.3

2.25

0.9

rnA

4.2

3.4

8.8

2.4

rnA

--

J::"

./

;:::

;3

50

V ........

~:::
60

80

(X)

El 250

MM~4C08/MM74COB

2-53

aS for decade counter configuration.

u

co

en
.-

o

'd'
C

U

.......
~
CO

en

5'd'

C
U'

CD4019BM/CD4019BC quad AN~-OR select gate
general description

features

The CD4019BM/CD4019BC is a complementary MOS
qu~d AND-OR select gate. Low power and high noise
margin over a wide voltage range is possible through
implementation of Nand P-channel enhancement mode
transistors. These complementary MOS (CMOS) transistors provide the building blocks for the 4 "ANO-OR
select" gate configurations, each consisting of two
2-input AND gates driving a single 2-input OR gate.
Selection is accomplished by control bits KA and KB.
All inputs are protected against static discharge damage.

•
•

Wide supply voltage range
High noise immunity

•

Low power TTL
compatibility

3V to 15V
0.45 VDD typ
fan out of2
driving 74L
or 1 driving 74LS

applications
•
•
•
•

AND-OR select gating
Shift-right/shift-Ieft fegisters
True/complement selection
AND/OR/EXCLUSIVE-OR selection

connection diagram
Dual-In-Line and Flat Package

B3

B2

A1

TOPV1EW

schematic diagram
Voo

KBo--I-+--+-t--.

Schematic diagram for 1 of 4 identical stages

2-54

B1

Vss

absolute maximum ratings

recommended operating conditions

(Notes 1 and 2)

(Note 2)

-0.5 to +18V
Voo Supply Voltage
-0.5 to Vo'O + 0.5V
VIN Input Voltage
-65°C to +150°C
TS Storage Temperature Range
Po Package Dissipation
500mW
TL Lead Temperature (Soldering, 10 seconds)
300°C

Voo Supply Voltage
VIN Input Voltage
T A Operating Temperature Range
C04019BM
C04019BC

dc electrical characteristics

CONDITIONS
.MIN

100

VOL

Quiescent Oevice Current

Low Level Output Voltage

= 5V
= 10V
VOO = 15V

High Level Output Voltage

VIH

Low Level Input Voltage

High Level Input Voltage

10H

High Level Output Current

UNITS

MAX

5

150

J.lA

0.05

10

300

J.lA

20

0.07

20

600

J.lA

VOO

0.05

0

0.05

0.05

V

VOO

0.05

0

0.05

0.05

V

0.05

0

0.05

0.05

V

1101< lJ.lA

1101< 1 pA
VOO

4.95

4.95

5

4.95

V

VOO

9.95

9.95

10

9.95

V

Vo

= 5V,
= 10V,
= 15V,

Vo

= SV,
VOO = 10V,
VOO = lSV,

Vo

VOO

VOO

VOO

= SV,

VOO
VOO

14.95

14.95

= 0.5V or 4.5V
Vo = 1V or 9V
Vo = 1.5V or 13.5V

= 5V,
VOO = 10V,
VOO = 15V,
VOO

= 0.5V or 4.5V
Vo = lV or 9V
Vo = 1.5V or 13.SV
= O.4V
Vo = O.SV
Vo = l.SV
= 4.6V
Vo = 9.5V
V.O

= 10V.
VOO = lSV. Vo = 13.SV
Input Current

MIN

0.03

VOO

liN

125°C
MAX

10

VOO
10L

TVP

5

VOO

Low Level Output Current

MIN

VOO

= 5V .
= 10V
VOO = 15V
VIL

25°C

MAX

VOO

= 5V
= 10V
VOO = 15V

VOH

-55°C to +125°C
-40° C to +85° C

CD4019BM (Note 2)
-55°C

PARAMETER

3 to 15V

o to Voo V

= lSV.VIN = OV
= 15V, VIN = lSV

2

3.0

4

4.0

6

V
1.5

V

3.0

3.0

V

4.0

4.0

V

3.S

3

3.S

V

7.0

7.0

6

7.0

V

11.0

11.0

9

11.0

V

0.64

O.Sl -

1

0.36

mA

1.6

1.3

2.S

0.9

mA

4.2

3.4

10

2.4

mA

-0.25

-0.2

-0.4

-0.14

mA

-0.62

-o:S

-1.0

-o.3S

mA

-1.8

-1.5

-3.0

-1.1 .

0.10

2·55

14.95
1.5

3.S

-0.10

~

15

1.5

-10- 5
lO-S

mA

-0.10

-1.0

0.10

1.0

J.lA
pA

U

al

en

dc electrical characteristics

CD4019BC (Note 2)

5

~

o
u
.........
:!

100

Quiescent Oevice Current

al

en

5
~
o

Low Level Output Voltage

VOL

u

VOH

High Level Output Voltage

Low Level Input Voltage

VIL

VIH

High Lever Input Voltage

MIN

Low Level Output Current

IOH

High Level Output Current

Input Current

liN

MIN

UNITS

MAX

0.03

20

HiO

}J.A

0.05

40

300

pA

VOO = 15V

80

0.07

80

600

}J.A

IIOIo and cJ>o of CD4060BM/CD4060BC.

2-58

ac electrical characteristics

CD4060BM/CD4060BC TA ~ 25° C, CL 50pF, R L = 200k, tr = tf =20ns, unless otherwise noted.

PARAMETER

C

TYP

MAX

Voo = 5V
Voo=10V
Voo = 15V

550
250
200

1300
525
400

ns
ns
ns

Interstage Propagation Delay Time
from On to On+1

Voo = 5V
Voo = 10V
Voo = 15V

150
60
45

330
125
90

ns
ns
ns

t THL , tTLH

Transition Time

Voo ~ 5V
Voo = 10V
Voo=15V

100
50
40

200
100
80

ns
ns
ns

t WL ' tWH

Minimum Clock Pulse Width

Voo = 5V
Voo=10V
Voo=15V

170
65
50

500
170
125

ns
ns
ns

Voo = 5V
Voo = 10V
Voo = 15V

-

no limit
no limit
no limit

ns
ns
ns

Propagation Delay Time to 0 4

t pH L4, tpLH4

tpHL, tpLH

Maximum Clock Rise and Fall Time

t rCL ' tlCL

Maximum Clock Frequency

tCL

Reset Propagation Delay

tpHL(R)

Minimum Reset Pulse Width

tWH(R)

CONDITIONS

Voo = 5V
Voo = 10V
Voo = 15V

MIN

1
3
4

3
8
10

UNITS

MHz
MHz
MHz

n

c

~

o
o

N

OJ

s:

.........

n

c

~

o
N
o
OJ
p
n

c

~

o
~
o
OJ

s:

.........

n

c

~

o
~
o

Voo = 5V
Voo = 10V
Voo=15V

200
100
80

450
210
170

ns
ns
ns

Voo = 5V
Voo = 10V
Voo = 15V

200
100
80

450
210
170

ns
ns
ns

7.5

pF

o
en
o

pF

s:

Cln

Average Input Capacitance

Any Input
(Note 1)

5

Cpd

Power Dissipation Capacitance

(Note 2)

50

OJ

p

n

c

~

OJ

.........

n

c

Note 1: Capacitance guaranteed by periodic testing.
Note 2: Cpd determines the no-load etc_

~

o
en
o
OJ
n

t

2-59

u

m

0

dc electrical characteristics

CD40XXBC (Note 2)

CD

_40°C

0

C
U
.......
~

m

CONDITIONS

PARAMETER

~

100

Quiescent Device Current

MIN

MAX

Voo = 5V
Voo = 10V
Voo = 15V

20
110
80
0.05
0.05
0.05

+8SoC

+25°C
MIN

TYP

MAX

0
0
0

MIN

MAX

UNITS

20
110
80

300
600

pA
p.A
pA

0.05
0.05
0.05

0.05
0.05
0.05

V
V
V

150

VOL

Low Level Output Voltage

Voo = 5V
Voo = 10V
Vo'o = 15V

V OH

High Level Output Voltage

Voo = 5V
Voo = 10V
Voo =; 15V

V IL

Low Level Input Voltage

Voo = 5V, V 0 = 0.5V or 4.5V
Voo = 10V, Vo = 1.0V or 9.0V
Voo = 15V, Vo = 1.5V or 13.5V

~

V IH

High Level Input Voltage

"m~

Voo = 5V, V 0 = 0.5V or 4.5V
Voo = 10V, Vo = 1.0V or 9.0V
Voo = 15V, Vo = 1.5V or 13.5V

3.5
7.0
11.0

3.5
7.0
11.0

3
6
9

3.5
7.0
11.0

V
V
V

IOL

Low Level Output Current
(See Note 3)

Voo=5V, Vo=O.4V
Voo = 10V, Vo = 0.5V
Voo = l~V, Vo = 1.5V

0.52
1.3
3.6

0.44
1.1
3.0

0.88
2.25
8.8

0.36
0.9
2.4

mA
mA
mA

~

IOH'

High Level Output Current
(See Note 3)

Voo = 5V, Vo = 4.6V
Voo = 10V, Vo = 9.5V
V oo ", 15V, Vo = 13.5V

-0.44 -0.88
--1.1
-2.25
-3.6 -8.8

-0.36
-0.9
-2.4

mA
mA
mA

U'

liN

Input Current

Voo = 15V, V IN = OV
Voo = 15V, V IN = 15V

0

CD

0

~

C
U

cJ
m

0

~

0

C
U

0

~

0

C
U

m

0

N

ac electrical characteristics

0

4.95
9.95
14.95

4.95 5
9.95 10
14.95 15

4.95
9.95
14.95
1.5
3.0
4.0

-0.52
-1.3
-3.6

1.5
3.0
4.0

1.5
3.0
4.0

2
4
6

-10. 5 -0.30
10- 5
0.30

-0.30
0.30

V
V
V

-1.0
1.0

V
V
V

pA
pA

CD4040BM/CD4040BC TA = 2SOC,CL = SOpF,RL = 200k, tr=tf= 20ns, unless otherwise noted.
TYP

MAX

C
U

t pHL1 , t pLH1

Propagation Delay Time to 0 1

Voo = 5V
Voo = 10V
Voo = 15V

250
100
75

550
210
150

ns
ns
ns

0

tPHL' t pLH

Interstage Propagation Delay Time
from Q n to Q n + 1

Voo = 5V
Voo = 10V
Voo = 15V

150
60
45

330
125
90

ns
ns
ns

t THL , tTLH

Transition Time

Voo = 5V
Voo = 10V
Voo = 15V

100
50
40

200
100
80

ns
ns
ns

t WL , tWH

Minimum Clock Pulse Width

Voo = 5V
Voo = 10V
Voo = 15V

125
50
40

335
125
100

ns
ns
ns

t rCL ' tfCL

Maximum Clock Rise and Fall Time

Voo = 5V
Voo = 10V
Voo = 15V

-

no limit
no limit
no limit

PARAMETER

~

"m~
N

0

~

C
U

fCL

tpHL(R)

Maximum Clock Frequency

Reset Propagation Delay

CONDITIONS

Voo = 5V
Voo = 10V
Voo = 15V

MIN

1.5

4
5

UNITS

ns
ns
ns'
MHz
MHz
MHz

4
10
12

Voo = 5V
Voo = 10V
Voo= 15V

200
100
80

450
210
170

ns
ns
ns

tWH(R)

Minimum Reset Pulse Width

Voo = 5V
Voo = 10V
Voo =- 15V

200
100
80

450
210
170

ns
ns
ns

Cin

Average I nput Capacitance

Any Input
(Note 1)

5

7.5

pF

C pd

Power Dissipation Capacitance

(Note 2)

50

Note 1: Capacitance guaranteed by periodic testing.
Note 2: Cpd determines the no·loadetc.

2-60

pF

n

c

schematic diagram

~

o

N

o

OJ

~
"-

n

c

~

o

N

o

OJ

r>

0- Vss

n

c

E!J. Vee

~

o
~
o

OJ
~

CD4020BM/CD4020BC Schematic Diagram

"-

n

c

~

o
~
o
OJ

r>
n

RESET

c

~

[!]

~ vss

o

-Voe

o
en
o
OJ
~

"-

n

c

~

CD4040BM/CD4_040BC Schematic Diagram

El . Vss
G ~ Vee
CD4060BM/CD4060BC Schematic Diagram

2-61

o
cn
o
OJ
n

...o

N

o

~

C

o
:E
N
o

CD4021M/CD4021C 8-stage static shift register

C

general description

features

The CD4021 M/CD4021 C is an 8-stage parallel input/
serial output shift register_A parallel/serial control
input enables individual "jam" inputs to each of 8stages. Q outputs are available from the sixth, seventh
and eighth stages.

•

Asynchronous parallel or synchronous serial operation.

•

Wide supply voltage range

"...
~

o

3.0V to 15V
0.45 Vee typ
5 MHz typ

• High noise immunity
.• Medium speed operation
clock rate at Voo - Vss = 10V
•

When the parallel/serial control input is in the logical
"0" state, data is serially shifted into. the register
synchronously with the positive transition of the clock.
When the parallel/serial control is in the logical "1"
state, data is "jammed" into each stage of the register
asynchronously with the clock.

Fully static operation

applications
•

Parallel to serial data conversion

•

General purpose register

logic diagram
PARALLEL
INPUT·l
7

PARAllEl! 9
SERIAL O-.....---D~-CONTROL

......-+----,

.....-+---......-+-.....+-...

~.-~----4.-~---

SERIAL 11
INPUT

Vee =TERMINAL 16
Vss = TERMINAL 8

connection diagram

PAR
IN

aUF
OUT

Vee

/16

SER
IN'

07

IS

14

13

truth table

12

11

eLK

PAR!
SER
CONT

10

CL

1

2

06
aUF
OUT

J

4

08
aUF
OUT

S

6

7

PI 1

PI n

01
(INTERNAL)

On

I

X

1

a

0

0

X

X

1

0

1

0

1

X

X

1

1

0

1

0

0

X

X

1

1

1

1

1

.../

0
1

0
0

X
X

X
X

0
1

On 1
anI

X

0

X

X

01

On

.f

A

PARALLEL!
SERIAL
CONTROL

X

"-

8
PAR
IN

SERIAL
INPUT

9

-

roo-

A

=

LEVEL CHANGE

8

1

PAR IN

TOPVIEW

2-62

x = DON'T CARE CASE

NO
CHANGE

(')

absolute maximum ratings

(Note 1)

C

~

o

Voltage at Any Pin
Vss - 0.3V to Voo + 0.3V
Operating Temperature Range
-55°C to +125°C
CD4021M
-40°C to +85°C
CD4021C
-65°C to +150°C
Storage Temperature Range
Package Dissipation
500 mW
Operating Voo Range
Vss + 3V to Vss + 15V
300°C
Lead Temperature (Soldering, 10 seconds)

dc electrical characteristics

~

s:

........
(')

C

~

o

N

.....a
(')

CD4021M
LIMITS

I

PARAMETERS

25°C

-55°C

CONDITIONS

125°C

TYP

MAX

V 00 = 5V
Voo= lOV

5
10

0.5
1

5

Quiescent Device Dissipation
Package (Po)

V 00 = 5V
Voo= 10V

25
100

Output Voltage
Low·Level (VOL)

Voo=5V
Voo= 10V

0.01
0.01

Output Voltage
High·Level (V OH)

Voo = 5V
Voo = 10V

4.99
9.99

4.99
9.99

5
10

4.95
9.95

V
V

Noise Immunity
(All Inputs) (V NL )

Vo=O.BV, Voo = 5V
Vo = lV, Voo = 10V

1.5
3

1.5
3

2.25
4.5

1.4
2.9

V
V

Noise Immunity
(All Inputs) (V NH )

Va = 4.2V, Voo = 5V
Va = 9V,
Voo = 10V

1.4
2.9

1.5
3

2.25
4.5

1.5
3

V
V

Output Drive Current
N·Channel (IoN)

Va = 0.5V, Voo = SV·
Va = 0.5V, Voo = 10V

0.15
0.31

0.12
,0.25

0.3
O.S

0.OB5
0.175

mA
mA

Output Drive Current
P·Channel (loP)

Va = 4.5V, Voo = 5V
Va = 9.5V, Voo= 10V

-0.1
-0.25

-O.OB
-0.20

-0.16
-0.44

-0.055
-0.14

mA
mA

MIN
Quiescent Device Current (I L)

TYP

MAX

MIN

Input Current (II)

MIN

TYP

UNITS
MAX

10

300
600

p.A
p.A

2.5
10

25
100

1,500
6,000

p.W
p.W

0
0

0.01
0.01

0.05
0.05

pA

10

dc electrical 'characteristics

V
V

CD4021C
LIMITS

PARAMETERS

-40"C

CONDITIONS
MIN

TYP

25°C
MAX

MIN

85°C

TYP

MAX

MIN

TYP

UNITS
MAX

Quiescent Device Current (I L)

Voo = 5V
Voo = 10V

50
100

0.5
1

50
100

700
1,400

p.A
p.A

Quie'scent Device Dissipation
Package (Po)

Voo = 5V
Voo = 10V

250
1,000

2.5
10

250
1,000

3,500
14,000

p.W
p.W

Output Voltage
Low·Level (VOL)

Voo = SV'
Voo = 10V

0.01
0.01

0
0

0.01
0.01

0.05
0.05

Output Voltage
High·Level (V OH )

Voo = 5V
Voo = 10V

4.99
9.99

4.99
9.99

5
10

4.95
9.95

V
V

Noise Immunity
(All Inputs) (V NL )

Vo=O.BV, Voo = 5V
Vo = lV,
Voo = 10V

1.5
3

1.5
3

2.25
4.5

V
V

Noise Immunity
(All Inputs) (V NH )

Vo = 4.2V, Voo = 5V
Vo = 9V,
Voo = 10V

1.4
2.9

1.5
3

2.25
4.5

1.4
2.9
I
1.5
3

Output Drive Current
N·Channel (IoN)

Vo = 0.5V, Voo = 5V
Vo = 0.5V, Voo = 10V

0.072'
0.12

0.06
0.1

0.3
0.5

0.05
O.OB

mA
mA

Output Drive Current
P·Channel (loP)

Vo = 4.5V, Voo = 5V
Vo = 9.5V, Voo = 10V

-0.04
-o.OB

mA
mA

-0.06
-0.12

-0.05
-0.1

-0.16
-0.44

10

Input Current (II)

2-63

V
V

V
V

pA

...

(.)

N

o

ac electrical characteristics

CD4021M

~

PARAMETERS -

TYP

MAX

(.)

Propagation Delay Time (tPHL. tPLH)

Voo '" 5V
Voo = 10V

300
100

750
225

ns
ns

Transition Time (tTH L. tTLH)

Voo = 5V
Voo = 10V

150
75

300
125

ns
ns

Minimum Clock Pulse Width (t WL • t WH )

Voo = 5V
Voo = 10V

200
100

500
175

ns
ns

Minimu'm High Level Parallel/Serial Control Pulse Width

Voo = 5V
Voo = 10V

200
100

500
175

ns

15
15

IlS
IlS

350
80

ns
ns

Q

"...Z
N

CONDITIONS

o

~

Q

(.)
·(tWH(P/S))
Clock Rise Time (t,CL) or Clock Fall Time (tIeL)

Voo = 5V
Voo = 10V

Set-up Time

Voo = 5V
Voo = 10V

Maximum Clock Frequency (fed

Voo = 5V
Voo = 10V

Input Capacitance (Cd (Note 2)

ac electrical characteristics

MIN

-

100
50
1

3

Any Input

2.5
5

UNITS

ns

MHz
MHz
pF

5

CD4021C

PARAMETERS
Propagation Delay Time (tPHL. t PLH )

CONDITIONS
Voo
Voo

=5V
= 10V
= 5V

Transition Time (tTHL. tTlH)

Voo
Voo = 10V

Minimum Clock Pulse Width (t WL • t WH )

Voo
Voo

Minimum High Level Parallel/Serial Control Pulse Width
(tWH(P/Sd

Voo
Voo

MIN

= 5V

= 10V

=5V
= 10V

Clock Rise Time (t,ed or Clock Fall Time (tIel)

Voo = 5V
Voo = 10V

Set-up Time

Voo ~ 5V
Voo = 10V

Maximum Clock Frequency (fed

Voo = 5V
Voo = 10V

Input Capacitance (C I ) (Note 2)

Any Input

TYP

MAX

300
100

1.000
300

ns
ns

150
75

400
150

ns
ns

200
100

830
200

ns
ns

200
100

830
200

ns
ns

15
15

IlS
IlS

500
100

ns
ns

100
50
0.6
2.5

2.5
5
5

UNITS

MHz
MHz
pF

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides
conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.

2·64

(")

c

~

o

N
W

c:J

s:
........
(")

C

~

o

CD4023BM/CD4023BC triple 3 input NAND gate
CD4025BM/CD4025BC t!iple 3 input NOR gate

N
W

c:J

51
(")
c
~

o

general description

features

These triple gates are monolithic complementary MOS
(CMOS) integrated circuits constructed with N- and
P-channel enhancement mode transistors. They have
equal source and sink current capabilities and conform
to standard B series output drive. The devices also have
buffered outputs which improve transfer characteristics
by providing very high gain. All inputs are protected
against static discharge with diodes to VO D and Vss.

• Wide supply voltage range

3.0V to 15V

•

High noise immunity

0.45 Voo typ

•

Low power
TTL compatibility

•

N

U'1

fan out of
2 driving 74L
or 1 driving 74LS

lD

11

lD

Vss

Vss

CD4023BM/CD4023BM .
TOP VIEW

CD4025BM/CD4025BC
TOP VIEW

2-65

C

~

o

c:J

Maximum input leakC!ge 1 pA at 15 V over full
temperature range

connection diagrams

11

(")

N
U'1

5 V - 10 V - 15 V parametric ratings

• Symmetrical output characteristics
•

c:J

s:
........

(")

()

£Xl
It)

N
0

~

C
U

........

~

£Xl
It)

N
.0

absolute maximum 'ratings

recommended operating conditions (Note 2)

(Notes 1 and 2)

VOD. DC Supply Voltage
-0.5 Voc to +18 Voc
-0.5 Voc to Voo + 0.5 VOC
VIN Input Voltage
. -65°C to +150°C
Storage Temperature Range
Ts
Package Dissipation.
500mW
Po
Lead Temperature (soldering, 10 seconds) 300°C
TL

dc electrical characteristics PARAMETER

~

Voo DC Supply Voltage
+5 Voc to +15 Voc
VIN Input Voltage
OVOC to Voo VOC
Operating Temperature Range
TA
CD4023BM, CD4025BM
-55°C to +125°C
CD4023BC,CD4025BC
-40°C to +85°C

CD4023BM, CD4025BM (Note 2)
_55°C

CONDITIONS

MIN

C

()

N
0

~

C

()

........

~

+125°C

TYP

MAX

MiN

MAX

UNITS

0.25
0.5
1.0

0.004
0.005
0.006

0.25
0.5
1.0

7.5
15
30

p.A
p.A
p.A

VOL Low Level Output Voltage VOO = 5V
Voo = 10V
V DD =15V

0.05
0.05
0.05,

0
0
0

0.05
0.05
0.05

0.05
0.05
0.05

V
·V
V

Quiescent Device Current

VOH High Level Output Voltage VOO = 5V
VDD = 10V
V DD = 15V

£Xl
M

V il

Low Level Input Voltage

~

VIH

High Level Input Voltage

N
0

C

+25°C
MIN

VO D = 5V
VDD = 10V
VO D = 15V

100

ci

£Xl
M

MAX

()

I
I

4.95
9.95
14.95

VOO = 5V, Vo = 4.5V
VOO = 10V, Vo = 9.0V 1101
Voo = 15V, Vo = 13.5V

< lp.A

V DD = 5V. Vo = 0.5V
VOO = 10V, Vo = 1.0V
V DO = 15V, Vo = 1.5V

< lp.A

1101

4.95
9.95
14.95
1.5
3.0
4.0

4.95
9.95
14.95

5
10
15
2
4
6

1.5
3.0
4.0

V
V
V
1.5
3.0
4.0

V
V
V

3.5
7.0
11.0

3.5
7.0
11.0

3
6
9

3.5
7.0
11.0

V
V
V

10l

Low Level Output Current VOD=5V. Vo = 0.4 V
V DO = 10V, Vo = 0.5V
VD!:i= 15V, VO= 1.5V

0.64
1.6
4.2

0.51
1.3
3.4

0.88
2.2
8

0.36
0.90
2.4

rnA
rnA
rnA

IOH

High Level Output Current V DD = 5V. Va = 4.6V
VOO = 10V. Vo = 9.5V
VDo = 15V, Vo = 13.5V

-0.64
-1.6
-4.2

-0.51
-1.3
-3.4

-0.88
-2.2·
-8

.:.0.36
-0.90
-2.4

rnA
rnA
rnA

liN

Input Curren~

-0.10
0.10

VDo = 15V, VIN = OV
V DO = 15V. VIN = 15V

-10- 5
10-5

-0.10
0.10

Notes on following page.

schematic diagram

1/3.Device Shown
"ALL INPUTS PROTECTED
BY STANDARD CMOS INPUT
PROTECTION CIRCUIT.

CD4023BC/CD4023BM

2·66

-1.0
1.0

p.A
p.A

n
dc electrical characteristics -

C

CD4023BC, CD4025BC (Note 2)

~

_40°C
PARAMETER
100

CONDITIONS

Quiescent Device Current

MIN

10L

laH

liN

MIN

TYP

Low Level Input Voltage

0.05
0.05
0.05
4.95
9.95
14.95

Voo=5V, V O =0.5V}
Voo = 10V, Vo = 1.0V 1101 < 1 JlA
Voo = 15V, Vo = 1.5V

Low Level Output Current Voo=5V, Vo = 0.4 V
Voo = 10V, Va = 0.5V
Voo = 15V, Va ~ 1.5V
High Level Output Current Voo=5V, Vo = 4.6V
Voo= 10V,Vo=9.5V
Voo = 15V, Va = 13.5V .
I nput Current

0
0
0
4.95
9.95
14.95

1.5
3.0
4.0

Voo=5V, V O =4.5V}
Voo=10V,Vo=9.0V 1I01--'" OUTPUT

0" ) TO NEXT

L-_ _ _ _ _ _ _ _ _ _ _

~-----

__

Input Logic

STAGE
_+~

2·69

Flip·flop logic (1 of 7 identical stages).

~

OJ

n

U

al

absolute maximum ratings

recommended operating conditions

N
0

(Notes 1 and 2)

(Note 2)

VOO de Supply Voltage
-0.5 to +18 VOC
VIN Input Voltage
-0.5 to VOO +0.5 VOC
-65°C to +150°C
TS Storage Temperature Range
Po Package Dissipation
500mW
TL Lead Temperature (Soldering, 10 seconds)
300°C

VOO de Supply Voltage
VIN Input Voltage
T A Operating Temperature Range
C04024BM
C04024BC

~

~

e

U

"al~

+3 to +15 VOC
Oto VOO VOC
-55°C to +125°C
--40° C to +85° C

~

N
0

id-

e

u

dc electrical characteristics

CD4024BM (Note 2)
-5SoC

PARAMETER
Quiescent Oevice Current

VOO
VOO
VOO

VOL

Low Level Output Voltage

MAX

= SV
= 10V
= lSV

High Level Output Voltage

Low Level Output Current

liN

High Level Output Current

Input Current

0.3

lS0

pA

10

O.S

10

300

pA

20

0.7

20

600

pA

0.05

0.05

0

0.05

0.05

V

0.05

0

0.05

0.05

V

= SV

4.95

4.95

4.9S

V

9.95

9.95

10

9.95

V

14.95

14.95

15

14.95

V

1I01

-1.0

0.3

1.0

JJ.A
1J,A

20 ns, unless otherwise specified

CONDITIONS

PARAMETER

mA

-0.3

UNITS

CLOCKED OPERATION
tpHL or tPLH

tPHL or tpLH

tpHL or tPLH

Propagation Oelay Time

VOO = 5V

200

400

to Q Outputs

VOO = 10V

85

170

ns

VOO

= 15V

,70

140

ns

Propagation Delay Time

VOO

= 5V

320

640

ns

to Carry Output

VOO = 10V

135

270

ns

VOO

= 15V

110

220

ns

VOO

= 5V,

285

570

ns

Propagation Oelay Time
to Carry Output

CL=15pF

120

240

ns

95

190

ns

VOO = 5V

100

200

ns

= 10V
VOO = 15V

50

100

ns

40

80

ns

160

320

ns

70

135

ns

55

110

VOO = 10V, CL
VOO = 15V, CL

tTHL or tTLH Transition Time/Q or
Carry Output

tWH ortWL

Minimum Clock Pulse
Width

trCL or !tCL

Maximum Clock Rise and
Fall Time

VOO

= 5V
VOO = 10V
VOO = 15V
VOO

VOO

fCL

Minimum Set-Up Time

Maximum Clock Frequency

= 5V

VOO = 10V
VOO

tsu

= 15 pF
= 15 pF

ns

= 15V

ns

15

1J,s

10

1J,s

5

1J,S

Voo = 5V

180

360

ns

VOO = 10V

70

140

ns

VOO

= 15V

55

110

VOO

= 5V

1.5

3.1

VOO = 10V

3.7

7.4

VOO=15V

4.5

9

ns
MHz

-

MHz
MHz

GIN

Average Input Capacitance

Any Input

5

CPO

Power Oissipation Capaci-

Per Package, (Note 3)

65

Propagation Oelay Time

Voo = 5V
VDD = 10V

?85
115

570

to Q Output

230

ns

VDO = 15V

95

195

ns

7.5

pF
pF

tance
PRESET ENABLE OPERATION
tpHL or tPLH

',2-84

ns

n

C

ac electrical characteristics (con't)
TA

= 25°C, CL = 50 pF, trCL = tfCL =

~

0

N
CD

20 ns, unless otherwise specified

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

tpHL or tPLH

tWH

tREM

to Carry Output

VOO = 5V

400

BOO

ns

VOO = 10V

165

330

ns

VOO = 15V

135

270

ns

Minimum Preset Enable'

VOO = 5V

80

160

ns

Pulse Width

VOO = 10V

30

60

ns

VOO = 15V

25

50

ns

Minimum Preset Enable

VOO = 5V

150

300

ns

Removal Time

VOO=10V'

60

120

ns

VOO = 15V·

50

100

ns

CARRY INPUT OPERATION
tpHL or tpLH

Propagation Oelay Time

VOO = 5V

265

530

ns

to Carry Output

VOO = 10V

110

220

ns

Propagation Oelay Time

VOO = 5V.

VOO = 15V
tpHL. tpLH

to Carry Output

CL = 15 pF

90

180

ns

200

400

ns

VOO = 10V. CL = 15 pF

85

170

ns

VOO = 15V. CL= 15 pF

70

140

ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of
"Electrical Characteristics" provides conditions for actual device operation.
Note 2: VSS = OV unless otherwise specified.
Note 3: 'CPD determines the no load ac power consumption of any CMOS device. For complete explanation, see 54C/74C Family
Characteristics application note, AN-gO.

connection diagram
Dual-I n-Line Package
JAM INPUTS

\

J4

J2

I

JAM INPUTS

CARRY
IN

TOP VIEW

2-85

BINARY/
UP/DDWN DECADE

02
11

5

4
Jl

\

12

13

3

2
04

J3

14

15

1

I

03

CLOCK

PRESET
ENABLE

........

n

PRESET ENABLE OPERATION (con't)
Propagation Oelay Time

tXJ
~

6
01

10

7
CARRY
OUT

9

8

1
VSS

C

~

0

N
CD

tXJ

n

o
en

m

N

o

Decade Mode
logic waveforms
CLOCK
~~~~~~~~~~~~~~~~~~~~~~

lilt

CARRY IN

o

UP/DOWN

r----"

C

1...-- f - -

L

..........

~

m

en

BINARY/
DECADE
PRESET
ENABLE

h- f---

h

N

o

lilt

C

o

Jl

-----

J2
JJ

J4

ILr

~ 1,.- L

02

II

II

OJ

II

01

.--

r"--

f--

~ r ~l rrL

II
2

1

,,,--

..--

r--~

J

4

5

IY

8

..-l..-

II

1,..-- f - -

lr II..-I - -

II
8

1

6

1

5

6

2

J

4

17U 9

0

1

6

Binary Mode

CLOCK

n-ILILIL~~~~ILIL~ILIL~IL~~~~~~ ~ n.
Ir--

CARRY IN

1"-- ~
II

UP/DOWN
BINARY/
DECADE
PRESET
ENABLE

'h

h

,

J1

J2
J3
J4

01

02

1..--

f--

1"--

r- ~ -

r--

l....-

Ir-- r--

II

f--

~

r--

r-I...-

"--

~

'"-

r- ~

'r--

~

r-

2

1

lr

rrr-

II

04
CARRY OUT
COUNT

~

r-- r--

1"--r -

OJ

s

6

7

B

9

10

11

12

13

14

IL~
15

9

8

1

6

5

4

J

o'La'r

switching time waveforms
Voo -----I-:b::--="CLOCK

VSS

50%
--IWH-VOO---+----------~r_--,--------~--------_+------------­
JAM
INPUT

VSS --+----------------1f---'

Voo---+---------,r----1f-----~
B/O OR
50%

uto
VSS

_-+_________..J

ISU

VOD

o OUTPUT

50%

VSS ---+--+,.~--------~r---"~I

2-86

>--

,....-t--

II

04

0

.r--

II

II

CARRY OUT
COUNT

r

>--

15

1

n
C

cascading packages

~

Parallel Clocking

0

UP/DOWN

N
CD
OJ

PRESET
ENABLE

s:

.......
co

co

TO NEXT
STAGE

-=

n

C

~

0

N
CD
OJ

CLOCK
BINARV!
DECADE

n

Ripple Clocking
UPJOOIIIN
PRESET
ENABLE

utO
CI

TO NEXT
STAGE

CO

-=
CLOCK
BINARV/
DECADE

2·87

(.)

o('I)

o
qo
C

(.)

.......

:E

o

('I)

oqo

c

(.)

CD4030M/CD4030C quad EXCLUSIVE-OR gate
general description,

applications

These EXCLUSIVE-OR gates are monolithic Complementary MOS (CMOS) integrated circuits constructed with Nand P-channel enhancement mode
transistors: All inputs are protected against static
discharge with diodes to Voo and Vss -

II

Automotive

II

Data terminals

II

Instrumentation

II

Medical electronics

II

Industrial controls

II

Remote metering

II

Computers

features
II
II
II

II

Wide supply voltage range
3.0V to 15V
Low power
100 nW (typ)
Medium speed
tpHL = tpLH =40 ns (typ)
operation
at C L = 15 pF. 10V supply
High noise immunity
0.45 Vee (typ)

schematic diagram

connection diagram
voo
12

11

TOP VIEW

2-88

lD

o
c

~

absolute maximum ratings

o
w
o

Voltage at Any Pin (Note 1)
Vss - 0.3V to Vss + 15.5V
Operating Temperature Range
-55°C to +125°C
CD4030M
-40°C to +85°C
CD4030C
-65°C to +150°C
Storage Temperature Range
Package Dissipation
500 mW
Operating V DO Range
Vss + 3.0V to Vss + 15V
Lead Temperature (Soldering. 10 seconds)
300°C

dc electrical characteristics

~
......

o
c

~

o
w
o

o

CD4030M
LIMITS

PARAMETER

CONDITIONS
MIN

_55°C
TYP

MAX

MIN

25°C
TYP

MAX

MIN

125°C
TYP

UNITS
MAX

Quiescent Device
Current IlL I

Voo = 5.0V
Voo = 10V

0.5
1.0

0.005
0.01

0.5
1.0

30
60

iJ. A
iJ.A

Quiescent Device Dissi·
pation Package (Po I

Voo = 5.0V
Voo = 10V

2.5
10

0.025
0.1

2.5

10

150
600

iJ. W
iJ.W

Output Voltage Low
Level Nod

Voo = 5.0V
voo = 10V

0.Q1
0.01

a
a

0.01
0.01

0.05
0.05

V
V

Output Voltage High
Level (V OH )

Voo = 5.0V
Voo = 10V

4.99
9.99

4.99
9.99

5.0
10

4.95
9.95

V
V

Noise Immunity
(All Inputs) (V NL )

Voo = 5.0V
Voo=IOV

1.5
3.0

1.5
3.0

2.25
4.5

1.4
2.9

V
V

Noise Immunity
(All Inputsl(V NH )

V OD = 5.0V
VoD=IOV

1.4
2.9

1.5
3.0

2.25
4.5

1.5
3.0

V
V'

Output Drive Current
N·Channel (IoN)

Voo = 5.0V
VOD = 10V

0.75
1.5

0.6
1.2

1.2
2.4

0.45
0.9

mA
mA

Output Drive Current
P·Channel (10 PI

V OD = 5.0V
Voo = 10V

-{lAS
-0.95

-{l.6

'-0.21
-0.45

mA
mA

Input Current (Id

V, =OVorV, =Voo

dc electrical characteristics

'"

-0.3
-0.65

-1.3

pA

10

CD4030C .
LIMITS

PARAMETER

-40°C

CONDITIONS
MIN

TYP

85°C

25°C
MAX

MIN

TYP

MAX

MIN

TYP

UNITS
MAX

Quiescent Device
Current ilL I

Voo = 5.0V
Voo = 10V

5.0
10

0.05
0.1

5.0
10

70
140

pA
pA

Quiescent Device Dissi·
pation Packdge (Po)

Voo = 5.0V
Voo = 10V

25
100

0.25
1.0

25
100

350
1,400

pW
pW

Output Voltage Low
Level (VOL)

V OD = 5.0V
V OD = 10V

0.01
0.01

0
0

0.01
0.01

0.05
0.05

Output Voltage High
Level (V OH )

Voo = 5.0V
Voo = 10V

4,,99
9.99

4.99
9.99

5.0
10

4.95
9.95

V
V

Noise Immunity
(Alllnputsl(VNd

Voo ~ 5.0V
Voo = 10V

1.5
3.0

1.5
3.0

2.25
4.5

1.4
2.9

V
V

Noise Immunity
(All l~putsI(VNH)

Voo = 5.0V
Voo = 10V

1.4
2.9

1.5
3.0

2.25
4.5

1.5
3.0

V
V

Output Drive Current
N·Channel (IoN I

Voo = 5.0
Voo = 10V

0.35
0.7

0.3
0.6

1.2
2.4

0.25
0.5

mA
mA

Output. Drive Current
P·Channel (loP)

Voo = 5.0V
Voo = 10V

-0.21
-0.45

-0.15
-0.32

-{l.6
-1.3

-{l.12
-0.25

mA
mA

Input Current (ld

V, =OVorV, =Voo

10

V
V

pA

Noto 1: This device should not be connected to circuits with power on because high transient voltages may cause permanent
damage.

2-89

(.)

ao

lilt
C
(.)

.......
~

o
('t)
o
'It
C

ac electrical characteristics

CD4030M

at T A = 25°C, Vss = OV, and C L = 15 pF. Typical temperature coefficient for all values of V DO = 0.3%fc.
LIMITS
PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Propagation Delay Time (tpHd

Voo = 5.0V
Voo = 10V

100
40

200
100

ns
ns

Propagation Delay Time (t pLH )

Voo = 5.0V
Voo = 10V

100
40

200
100

ns
ns

Transition Time High to Low
Level (tTHL)

Voo = 5.0V
Voo = 10V

70
25

150
75

ns
ns

Transition Time Low to High
Level (tTLH)

Voo = 5.0V
Voo = 10V

80
30

150
75

ns
ns

Input Capacitance (C I )

VI =OVorV I =V'oo

5.0

(.)

ac electrical characteristics

pF

CD4030C

LIMITS

CONDITIONS

PARAMETER

MIN

UNITS

TYP

MAX

Propagation Delay Time (tPHd

Voq = 5.0V
Voo = 10V

100
40

300
150

ns
ns

Propagation Delay Time (tPLH)

Voo = 5.0V
Voo = lOV

100
40

300
150

ns
ns

Transition Time High to Low
Level (t TH L)

Voo = 5.0V
Voo = 10V

70
25

300
150

ns

Transition Time Low to High
Level (tT LH )

Voo = 5.0V
Voo = 10V

80
30

300
150

ns
ns

Input Capacitance (C I )

VI =OVorV I =Voo

5.0

truth table

(For One of Four Identical Gates)

A

B

J

0

0

0

1

0

1

0

1

1

1

1

0

Where:

"1"
"0"

= High Level
= Low Level

2-90

ns

pF

n

c

~

o

CAl
OJ

~

.......

n

CD4031BM /CD403IBC 64 stage static shift register

c

~

general description

o

features

The CD4031BM/CD4031BC is an integrated, complementary MOS (CMOS), 64-stage, fully static shift
register. Two data inputs, DATA IN and RECIRCULATE
IN, and a MODE CONTROL input are provided. Data at
the DATA input (when MODE CONTROL is LOW) or
data at the RECIRCULATE input (when MODE
CONTROL is HIGH), which meets the setup and hold
time requirements, is entered into the first stage of the
register and is shifted one stage at each positive transition of the CLOCK.

• Wide supply voltage range

3.0V to 15V

• High noise immunity

0.45 Voo typ

Data output is available in both true and complement
forms from the 64th stage. Both the DATA OUT (Q)
and DATA OUT (Q) outputs are fully buffered.

• Single phase clocking requirements

fan out of
2 driving 74L or
1 driving 74LS

• Low power
TTL compatibility
• Fully static operation

(typical

The CLOCK input of the CD4031BM/CD4031BC is
fully buffered, and presents only a standard input load
capacitance. However, a DELAYED CLOCK OUTPUT
(CL o ) has been provided to allow reduced clock drive
fan-out and transition time requirements when cascading
packages.

DC to 8MHz
V 00 = 10 V)

5 pF (typ)
input capacitance

• Fully buffered clock input

a·

@

Delayed clock output for reduced clock drive requirements

• Fully buffered outputs
• High Current Sinking Capability,
Q Output
@ Voo

1.6 mA

= 5V and 25°C

logic and connection diagrams
r--------------------------~l

DATA IN

1

I

I

MODE
CONTROL

I

...........

~""".... ~"._-

DATA OUT (0)

1
I
I

RECIRCULATE
IN

1

IL _____________ ONE STAGE

(21~

~

.

__________ JI

~CL

CLOCKIN~Ci
.
Ci

CL

--1-

--1-

-lII--Iif--r --r
CL

Ci

T

T
RECIRCULATE IN

VOO

CLOCK IN

DATA IN

NC

NC

NC

NC

NC

NC

DATA OUT 10)
DATA

NC

ililT (i'i)

MODE CONTROL

m~~~DUT (CLo)

Vss

2-91

~

DE LAVED CLOCK
OUT (CLo)

CAl
OJ

n

U

m

absolute maximum ratings

o

V OD
VIN
TS
Po
TL

M

~

c

U

.........

~

recommended operating conditions

(Notes 1 & 2)

-0.5 V to +18 V
Supply Voltage
-0.5 V to Voo + 0.5 V
Input Voltage
_65°C to +150°C
Storage Temperature Range
500mW
Package Dissipation
\
300°C
Lead Temperature (Soldering, 10 seconds)

Voo Supply Voltage
VIN Input Voltage
T A Operating Temperature Range
CD4031BM
CD4031BC

(Note 2)

+3Vto+15V
OV to Voo
_55°C to +125°C
_40°C to +85°C

m

M
o

~

c

dc electrical characteristics (Note 2) CD4031 BM

U'
PARAMETER
100

_55°C

Quiescent Device Current

10
20

VO H High Level Output Voltage Voo = 5 V } .
Voo = 10V VIH = Voo, VIL = OV, ilol
Voo = 15V
Low Level Input Voltage

VIH

High Level Input Voltage

+125°C

0.01 '5
0.01
10
0.02 20

5

Voo = 5 V
Voo = 10V
Voo = 15V

0.05
0.05
0.05

VOL Low Level Output Voltage VO O =5V}
Voo = 10V VIH = Voo, VIL = OV,IIOI < llJ.A
Voo,,15V
.

VIL

+25°C

1---...,.---+--..---...,.---+--..----1 UNITS
MIN MAX MIN TYP MAX MIN MAX

CONDITIONS

Voo=5V. VO=0.5vor4.5V}
Voo = 10V, Vo = 1.0V or 9.0V
1101
Voo = 15V, Vo = 1.5Vor 13.5V

< (IJ.A

4.95
9.95
14.95

0

pA
pA
pA

0.05
0.05
0.05

V
V
V

4.95
9.95
14.95

4.95 5
9.95 10
14.95 15
1.5
3.0
4.0

< 1 pA

0.05
0.05
0.05

0

6

150
300
600

2.25
4.5
6.75

1.5
3.0
4.0

V
V
V
1.5
3.0
4.0

V

V
V

3.5
7.0
lui

3.5
7.0
11.0

2.75
5.5
8.25

3.5
7.0
11.0

10L

Low Level Output Current, Voo=5V, VO=O.4V
Q Output
VoO=10V,Vo=0.5V }VIH = Voo
VIL = OV
Voo = 15V. Vo = 1.5 V

2.3
5.1
10.5

1.9
4.2
8.8

3.8
8.4
17

1.3
2.8
6.1

mA
mA
mA

10L

Low Level Output Current, Voo = 5V, Vo = 0.4 V
Q and CLo Outputs
Voo = 10V, Vo = 0.5V }VIH= Voo
VIL = OV
Voo = 15V, Vo = 1.5V

0.64
1.6
4.2

0.51
1.3
3.4

0.88
2.25
8.8

0.36
0.9
2.4

mAO
mA
mA

10H

High Level Output Current. Voo=5V, VO=4.6V}V =V
All Outputs
Voo=10V,Vo=9.5V
IH_ DO
VIL-OV
V oo =15V,Vo=13.5V

-0.64
-1.6
-4.2

-0.51 -0.88
-1.3 -2.25
-3.4 -8.8

-0.36
-0.9
-2.4

mA
mA
mA

liN

Input Current

Voo=5V, Vo=0.5vor4.5V}
Voo=10V,Vo=1.0V,or9.0V
Ilol

_ - - - - ' \
1......

~1

1 2 - - - - - J..

...

1 - - - - - - - - - - - 1 1 . 12 , - - - - - - - - -...

.-

I~fl 12~1

'WHEN '\*12. tw IS PROPORTIONAL TO THE PHASE OF 1\ WITH RESPECT TO 12

SHIFT LEFT OUTPUT
"A" ENABLE

r:>p'-

SHI FT LEFTI
SHIF T RIGHT

-

SHIF T RIGHT
INPUT

':"

REG.I
C04034B

AlE I

~ ~'~"r~ Jr~

r.--~~4 034B
G.2

~ AIS
~CL

AlB I

-!-:~

B

I

~ PIS

PIS

CL

AISPA RALlEl
ENTRY

rtrtirtrtrt~

SHIFT ;;-G HT
OUTPUT

L..,. SI

~ AlS

CLOCK

AE I

B

SI

L....-+

-

- : . . - - "A" PARALLEL DATA

~

PIS

AlB I

B
~

~

~

~

~

~

-!-:~

~

B
~

~

~

~

~

SHIFT LEFT'
INPUT
. . - AIS

~

C
A

A/EI_

A·PARALLEL DATA

-B

~SI

VD~£

PIS

AlE 1 -

r

PIS

REG.l
C040l4B

AIS

A·PARALLEL DATA

SI

-

B

_

8

REG.4
CD4034B

VDDL AlS

r - - CL

~

AlBI_

B PARALLEL DATA

_B

L{t t t. t t t t t
A "High" ("Low") on the Shift Left/Shift Right input
allows serial data on the Shift Left Input (Shift Right
Input) to enter the register on the positive transition
of the clock signal. A "high" on the "A" Enable Input
disables the "A" parallel data lines on Registers 1 and 2
and enables the "A" data lines on Registers 3 and 4

AlBI-

B PARALLEL DATA

4t tt t t f f· t

and allows parallel data into Registers 1 and 2. Other
logic schemes may be used in place of registers 3 and 4
for parallel loading.
When parallel inputs are not used Registers 3 and 4 and
associated logic are not required.

* Shift left input must be disabled during parallel entry.
Shift Right/Shift Left with Parallel Inputs

2-101

CL

(.)

to

~

truth tables

M

o

"A" ENABLE

PIS

AlB

AIS

MODE

Q

0

0

0

X

Serial

Synchronous Serial data input, A· and B·Paraliel data outputs disabled.

(.)

0

0

1

X

Serial

Synchronous Serial data input, B·Paraliel data output.

0

1

0

0

Parallel

0

1

0

1

Parallel

B Asynchronous Parallel data inputs, A·Paraliel data outputs disabled.

0

1

1

0

Parallel

A·Paraliel data inputs disabled, B·Paraliel data outputs, synchronous data recirculation.

~

........

~
to
~

M

OPERATION·

B Synchronous Parallel data inputs, A·Paraliel data outputs disabled.

o

0

1

1

1

Parallel

Q

1

0

0

X

Serial

Synchronous Serial data input, A·Paraliel data output.

1

0

1

X

Serial

Synchronous Serial data input, B·Paraliel data output.

1

1

0

0

Parallel

1

1

0

1

Parallel

B Asynchronous Parallel data input, A·Paraliel data output.

1

1

1

0

Parallel

A Synchronous Parallel data input, B·Paraliel data output.

1

1

1

1

Parallel

A Asynchronous Parallel data input, B·Paraliel data output.

~

(.)

A·Parallel· data inputs disabled, B·Paraliel data outputs, asynchronous data recirculation.

B Synchronous Parallel data input, A·Paraliel data output.

X = Don't Care

* For synchronous operation

(serial mode or when A/S

= 0 in

parallel model, outputs change state at positive transition of the clock.

2-102

(")

'0
~

o

w
U1

to

s:

.......

CD4035BM/CD4035BC 4-bit parallel-in/parallel-out shift register
general description
features
The C04035B 4·bit parallel·in/parallel·out shift register
is a monolithic complementary MOS (CMOS) integrated
circuit constructed with P and N·channel enhancement
mode transistors. This shift register is a 4·stage clocked
serial register having provisions for synchronous parallel
inputs to each stage and serial inputs to the first stage
via JK logic. Register stages 2, 3, and 4 are coupled in a'
serial "0" flip·flop configuration when the register is in
the serial mode (parallel/serial control low).

Wide supply voltage range

•

High noise immunity

•

Low power
TTL compatibility

•
•

o

0.45 VOO typ
fan out of 2
driving 74L
or 1 driving 74LS

to

4·stage clocked shift operation
Synchronous parallel entry on all 4 stages

• JK inputs on first

In the parallel or serial mode information is transferred
on positive clock transitions.
When the true/complement control is "high," the true
contents of the register are available at the output ter·
minals. When the true/complement control is "low",
the outputs are the complements of the data in the regis·
ter. The true/complement control functions asynchro·
nously with respect to the clock signal.

stage
true/complement

Asynchronous
outputs

•
•

Reset control
Static flip·flop, operation; master/slave configura·
tion

•
•

Buffered outputs '
Low·power dissipation

•

High speed

control

on

all

5 pW typ (ceramic)
to 5 MHz

applications

input logic is provided on the first stage serial
input to minimize logic requirements particularly in
counting and sequence·generation applications. With JK
inputs connected together, the first stage becomes a '
"0" flip·flop. An asynchronous common reset is also
provided.

•
•
•
•

Automotive
Oata terminals
Instrumentation
Medical electronics

•
•

Alarm systems
Industrial controls

•

Remote metering

•

Computers

logic diagram
PARAllEL
INPUT -1
9
PARAllEL 7
SERIAL O - - - - i ;>O---+..............---.......
CONTAO L(PIS)

---+P-....- -......- - -......-.-:---~---+.............,......--.

J

4

o---+-0-<:1

.:>-----......- - - + - - - -.......---+-----*-'---+------1

2

TRUE/CO~~~i 0 - - - < : I .:>-----------H--------1+-------_+-----------.

?
Ql

PIS = 0 = serial mode
TIC =1 = true outputs
*TG = transmission gate
1

Input to output is:
a) A bidirectional low impedance when control input 1 is low
and control input 2 is high.
b) An open circuit when control input 1 is high and control input 2 is low.

2-103

~

3V to 15V

•
Parallel entry via the "0" line of each register stage is
permitted only when the parallel/serial control is "high."

JK

•

(")

o

w
U1

(")

u.
m

absolute maximum ratings

M

-o.S to +18V
VOO de Supply Voltage
-O.S to VOO + O.SV
VIN Input Voltage
~s"C to +lS0°C
TS Storage Temperature Range
Po Package Oissipation
SOOmW
T L Lead Temperature (Soldering, 10 seconds)
300°C

it)

o

~

c

,u

~

r:a

operating conditions (Note 2)

(Note 1 and 2)

dc electrical characteristics

VOO de Supply Voltage
VIN Input Voltage
T A Operating Temperature Range
C0403SBM
C0403SBC

-5SoC
PARAMETER

o

~

c

100

Quiescent Device Current

.u
VOL

VOH

VIL

Low Level Output Voltage

High Level Output Voltage

Low Level Input Voltage

CONDITIONS

High Level Input Voltage

150

pA

300

pA

VOO = 15V

20

1.0

20

600

pA

1101 < 1.0 pA
VOO = 5 V

0.05

0

0.05

0.05

V

VOO=10V

0.05

0

0.05

0.05

V

VOO = 15V

0.05

0

0.05

0.05

V

1101 < 1.0pA
VOO = SV

4.95

4.95

5

4.95

V

VOO = 10V

9.95

9.95

10

9.95

V

VOO = 15V

14.95

14.95

15

14.95

V

1101 < 1.0pA

= 0.5V or 4.5V
= 1.0V or 9.0V
Vo = 1.5V or 13.5V

VOO = 5V,

Va

1.5

1.5

1.5

V

VOO = 10V,

Vo

3.0

3.0

3.0

V

4.0

4.0

4.0

V

1101 < 1.0 pA

= 5V,
= 10V,
= 15V,

VOO = 5V,

= 10V,
= 15V,

VDO = 5V,

VOD

= 10V,
= lSV,

dc electrica I cha racteristics

= O.5V or 4.5V

3.5

3.5

3.5

V

Vo = 1.0V or 9.0V

7.0

7.0

7.0

V

Vo
Vo

= 1.5V or

11.0

11.0

= O.4V
Vo = 0.5V
Vo = 1.5V

13.5V

0.64

0.51

Vo = 4.6V

-0.25

= 9.5V
Vo = 13.5V

-0.62
-1.8

Vo

VOO = lSV,

Vo

Low Level Output Voltage

1.3

2.25

0.9

rnA

8.8

2.4

rnA

-0.2

0.36

-0.14

rnA

-0.5

0.9

-0.35

rnA

-1.5

-3.5

High Level Output Voltage

Low Level Input Voltage

-lO- S

-0.1

-1.0

pA

0.1

10-5

0.1

1.0

pA

MIN

= 5V

8SoC

25°C
MIN

TVP

MAX

MIN

MAX

UNITS

20

O.S

20

150

pA

1.0

40

300

pA

= 15V

80

5.0

80

600

pA.

VOO = 5V

O.OS

0

0.05

0.05

V

= 10V
VOO = 15V

O.OS

0

0.05

O.OS

V

O.OS

0

0.05

O.OS

V

1101<1 f1A

1I01
u

20
18
16
14
12
10

z

AM81ENT TEMPERATURE
TA ' 25°C

.......

.... i-"""

A'Sv
r--

;;{

Typical Source Current
Characteristics

-

-20
-18
-16
<
.§
-14
z
a: '-12
a:
::> -10
u
z
-8

...

-.

") ~1~

!/ V

:5

~

JV

1

.E

o Ir$o

1

.E

~ ~5V

/

8

4

10

12

14

-6
-4

Vos - ORAIN TO SOURCE VOLTAGE (V)·

..,.'"

~5J_ -

/

L

.I.

V

/ ~v
~

o ~ f-'"
o -2 -4

16

A

V V

-2

'I

2

AMBIENTTEMPERATURE
TA • 25°C

i

5V

-6 -8 -10 -12 -14 -16

Vos - ORAIN TO SOURCE VOLTAGE (V)

Typical Transition Time
vsCL

Typical Propagation Delay
]: 250 Time vs CL

250

w

:;

:s

f=

~

200 1-----t---+----1-7I<---t---I

~ 200

150 1-----t----JiC----f----t----I

~

100

i

z
c

f=

~
~

...
1

I--~'t_-+---f--__",......"'--:I

j
"

100

1

50

j

J:

5

150 r---t---t---V-'---t---I

f=

~

o

"J:

o

20
CL

-

40

60

80

J

100

LOAO CAPACITANCE (pF)

o ~-~--~--~--~--~

o

20

40

60

80

CL -LOAO CAPACITANCE (pF)

2·118

100

(")

C

~

o

~

en
CO

s:
........

CD4046BM/CD4046BC micropower phase-locked loop

(")

C

~

general description

o
The source follower output of the VeOIN (demodulator
Out) is used with an external resistor of 10 kn or.more.
The INHIBIT input. when high. disables the veo and
source follower to minimize standby power consumption. The zener diode is provided for power supply
regulation if necessary.

The eD4046B micropower phase-locked loop (PLL)
consists of a low power. linear. voltage-controlled oscillator (VeO), a source follower. zener diode. and two
phase comparators. The two phase comparators have a
common signal input and a common comparator input.
The signal input can be directly coupled for a large
voltage. signal. or capacitively coupled to the self-biasing
amplifier at the signal input for a small voltage signal.

a

features

Phase comparator I. an exclusive OR gate. provides a
digital error signal (phase compo lOut) and maintains
0
90 ph lise shifts at the veo center fr~quency,,' Between
signal input and comparator input (both' at 50% duty
cycle), it may lock onto the signal input frequencies
that are close to harmonics of the veo center frequency.

•

Wide supply voltage range-3V to 18V

•

Low dynamic power consumption-70 /lW (typ) at
fo = 10 kHz. VDD = 5V

•
•

veo frequency-1.3 MHz (typ) at VDD'= 10V
Low frequency drift with temperature-0.06%/oe
at VDD = 10V
.. High veo linearity.:...1% (typ)

Phase comparator II is an edge-controlled digital memory
network. It provides a digital error signal (phase compo II
Out) and lock-in signal (phase pulses) to indicate a
0
locked condition and maintains a 0 phase shift between
signal input and comparator input.

applications
•. FM demodulator and modulator
•

Frequency synthesis and multiplication

• Frequencydiscrimination
• Data synchronization and conditioning
a Voltage-to-frequency conversion

The linear voltage-controlled oscillator (VeO) produces
a:1 output signal (VeO Out) whose frequency is determined by the voltage at the veOIN input. and the
capacitor and resistors connected to pin e1 A. e1 B.
R1 and R2.

•

Tone decoding

•

FSK modulation

•

Motor speed control

block and connection diagrams
SIGNAL
IN

Voo

16

Duai-in-Line Package
2 PHASE CoMP lOUT

r--

PHASE PULSES

d

13
PHASE CoMP lOUT

PHASE CoMP II OUT
PHASE PULSES

16
Voo

15

COMPARATOR IN

SIGNAL IN

VCO OUT

PHASE COMP II OUT

R2

INHIBIT

Rl

Cl

DEMODULATOR OUT

CIB
VSS

+-JVV ~o.:.l:.j21-1
R2

Vss

ZENER

VSS

INHIBITO-;~-"'---..J

VSS

ZENER

FIGURE 1

2·119

9

VCO IN

~

en

CO

(")

absolute. maximum ratings

recommended operating conditions

(Notes 1 and 2)

(Note 2)

VDD DC Supply Voltage
--0.5 to +18 V DC
VIN Input Voltage
--0.5 to VDD + 0.5 VDC
TS Storage Temperature Range
-65°C to +150°C
Po Package Dissipation
500mW
TL Lead Temperature (Soldering, 10 seconds)
300°C

VDD DC Supply Voltage
VIN Input Voltage
T A Operating Temperature Range
C04046BM
CD4046BC

3 to 15 VDC
Oto VOOVOC
-55°C to +125°C
-40°C to +85°C

I
dc electrical characteristics

100

VOL

VOH

Quiescent Oevice Current

·Low Level OU,tput Voltage

High Level Output Voltage

~5°C

CONDITIONS

PARAMETER

MIN

VIH

High Level Input Voltage

IOH

High Level Output Current

20

0.015

VOO = 5V

0.05

0

VOO = 10V

0.05

0

0.05

0.05

V

VOO=15V

0.05

0

0.05

0.05

V

VOO = 5V

= 10V

Input Capacitance
Total Power

~issipation

150

J.1A

10

300

pA

20

600

J.1.A

0.05

0.05

V

4.95

4.95

5

4.95

V

9.95

9.95

10

9.95

V

14.95

= 0.5V or 4.5V

14.95

15

14.95

V

2.25

VOO ='10V Vo=lVor9V

3.0

4.5

3.0

3.0

V

VOO: 15V. VO: 1.5V or 13.5V

4.0

6.25

4.0

4.0

V

VOO

= 5V,
= 10V,

Vo

5

1.5

VOO = 5V,

VOO: 5V,

1.5

1.5

V

VO: 0.5V or 4.5V

3.5

3.5

2.75

3.5

V

VO: 1V or 9V

7.0

7.0

5.5

7.0

V

Va: O.4V

11.0

11.0

8.25

11.0

V

0.64

0.51

0.88

0.36

rnA

Voo: 10V, Vo : 0.5V

1.6

1.3

2.25

0.9

rnA

Voo: 15V, Vo

= 1.5V

4.2

3,4

8.8

2.4

mA

VOO: 5V,

= 4.6V

-0.64

-0.51

-0.88

-0.36

mA

~1.6

-1.3

-2.25

-0.9

rnA

-4.2

-3.4

-8.8'

-2.4 "

rnA

= 10V,
= 15V,

Va

Va: 9.5V
Va

= 13.5V

All Inputs Except Signal Input

= 15V,

VIN: OV

\fOO: 15V, VIN

PT .

UNITS

VOO = 15V

VOO

CIN

MAX

0.005
0'.01

Voo
Input Current

MIN

10

.VOO

liN

MAX.

5

VOO: 15V, VO: 1.5V or 13.5V
Low Level Output Current

TVP

VOO = 10V

VOO

IOL

MIN

Inhibit = VOO, Signal In = VOO

VOO = 15V
Low Level Input Voltage.

125°C

25°C

MAX

VDO = 5V

VOO

VIL

I

CD4046BM (Note 2)

= 15'1

-0.1

-10- 5

-0.1

-1.0

/.1 A

0.1

10-5

0.1

1.0

J.1A

Any I nput, (Note 3)
fo: 10kHz, R1
R2:

00,

VCalN

7.5

pF

= 1 MD,
= Voo/2
rnW

VOO: 5V

0.07

VOO: 10V

0.6

rnW

VOO: 15V

2.4

mW

2-120

I

n
dc electrical characteristics

c

CD4046BC (Note, 2)

~

IDD

VOL

VOH

VIL

VIH

Quiescent Device Current

Low Level Output Voltage

High Level Output Voltage

Low Level Input Voltage

High Level Input Voltage

CONDITIONS

MIN

Low Level Output Current

liN

Input Current

MAX

MIN

MAX

UNITS

20

O.OOS

20,

lS0

J.l.A

40

0.01

40

300

J.l.A

VOO = lSV

80

O.Q1S

80

600

J.l.A

VDO = SV

O.OS

0

O.OS

O.OS

VDD = 10V

O.OS

0

0.05

O.OS

V

VDD = lSV

O.OS

0

O.OS

O.OS

V

V

5

4.95

9:95

10

9.95

V

14.95

15

14.95

V

VDD = SV'

4.9S

4.95

VOD = 10V

9.95

VDD = 15V

14.9S

V

V

l.S

2.25

1.5

1.5

VDD = 10V VO= lVor9V

3.0

4.S

3.0

3.0

V

VDD = 15V. Vo = l.SV or 13.5V

4.0

6.25

4.0

4.0

V

VDO = 5V,

VOD = 5V,

Vo = O.SV or 4.5V

Vo = O.SV or 4.5V

VOD

= 15V,

Vo

= l.SV or

VDO

= 5V,

Vo = O.4V

13.5V

= 5V,
VDO = 10V,
VOD = 15V,

VDD

= 1.SV

V

3.S

3.5

2.75

3.5

7.0

7.0

5.S

7.0

V

11.0

11.0

8.25

11.0

V

0.52

0.44

0.88

0.36

mA

1.3

1.1

2.25

0.9

mA
mA

3.6

3.0

8.8

2.4

Vo = 4.6V

-0.S2

-0.44

-0:S8

-0.36

mA

Vo = 9.SV

-1.3

-1.1

-2.25

-0.9

mA

Vo = 13.5V

-3.6

-3.0

-8.8

-2.4

mA

All Inputs Except Signal Input

= OV
= 15V, VIN = 15V

-0.3

VOD = 15V, VIN
VOO
CIN

Input Capacitance

Any Input, (Note 3)

PT

Total Power Oissipation

fo= 10kHz, Rl
R2

=

00,

VCOIN

0.3

-10- 5
10-5

-0.3

-1.0

J.l.A

0.3

1.0

J.l.A

7.5

pF

= 1 M!1,
= VOO/2
mW

VOO = 5V

0.07

VOO = 10V

0.6

mW

= 15V

2.4

mW

VOO

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed, they are not meant to imply
that the devices should be operated at these limits. The table of "Recommended Operating Conditions" and "Electrical Characteristics" provides
conditions for actual device operation.
Note 2: VSS = OV unless otherwise specified.
Note 3: Capacitance is guaranteed by periodic testing.

2·121

~

en

OJ

VDD = 10V

VDO = 15V, Vo
High Level Output Current

TVP

Inhibit = VDD, Signal In = VOO

VDD = 10V, Vo = O.SV

IOH

MIN

VDD = SV

VDD = 10V, Vo = lV or 9V

IOL

MAX

8SoC

2SoC

-40°C
PARAMETER

o

s:

.........

n
c

~

o
~
en
OJ

n

ac electrical characteristics

CD4046BM/CD4046BC (CL

I

PARAMETER
VCO SECTION
fMAX Maximum Operating Frequency

I

CONDITIONS

= 50 pF, TA = 25°C)
MIN

I

TYP

I

MAX

I

UNITS

Cl = 50 pF, Rl = 10 kH, R2 = 00,
VCOIN = VOO
VOO = 5V

0.4

0.8

MHz

VOO = 10V

0.6

1.2

MHz

VOO = 15V

1.0

1.6

MHz

VCOIN = 2.5V ±0.3V,

Linearity

Rl~10kn,VOO=5V

1

%

VCOIN = 5V ±2.5V,
Rl ~ 400 k!1, VOO = 10V

\

1

%

VCOIN = 7.5V ±5V,
Rl ~ 1 M!1, VOO = 15V
Temperature-Frequency Stability
No Frequency Offset, fMIN = 0

Frequency Offset, fMIN

'* 0

VCOIN Input Resistance (VCOIN)

VCO Output Outy Cycle

1

R2 = 00
VOO = 5V

0.12-0.24

%fC-

VOO = 10V

0.04-0.08

%/oC

VOO = 15V

0.015-0.03

%/"C

= 5V
VOO = 10V
VOO = 15V

0.06-0.12

%/"C

VOO

tTHL,

YCO Output Transition Time

0.05-0.1

%/"C

0.03-0.06

%/"C

106

MH

VOO

10 6
10 6

MH

VOO = 5V

50

= 10V
VOO = 15V

50

%

50

%

= 5V
= 10V
VOO = 15V

,

VOO

VOO

VOO
VOO

tTLH

%

%fC ex l/f. VOO

= 5V
= 10V

VOO=15V·

MH
%

90

200

ns

50

100

ns

45

80

ns

PHASE COMPARATORS SECTION
RIN

Input Resistance
Signal Input

= 5V

1

3

MH

0.2·

0.7

Mn

0.1

0.3

MH
MH

VOO = 10V

10 6
106

VOO = 15V

10 6

MH

VOO

VOO = 10V
VOO
Comparator Input

AC-Coupled Signal Input Voltage
Sensitivity

VOO

= 15V
= 5V

Mn

CSERIES = 1000 pF,
f = 50 kHz
200

400

mV

= 10V

400

800

mV

VOO = 15V

700

1400

mV

RS ~ 10 kH, VOO = 5V

1.50

2.2

V

RS ~ 10 kn, VOO = lOV .

1.50

2.2

V

RS ~ 50 kH, VDO = 15V

L50

2.2

V

VOO = 5V
VOO

DEMODULATOR OUTPUT
Offset Yoltage (VCOIN-VOEM)

linearity

RS> 50 krl
VCOIN = 2.5 ±0.3V, VOO = 5V

0.1

%

VCOIN = 5 ±2.5V, VOO = 10V

0.6

%

VCOIN = 7.5 ±5V, VOO = 15V

0.8

%

ZENER DIOOE
Vz

Zener Oiode Voltage
C04046BM

IZ = 50J1A

CD4046BC
RZ

Zener Oynamic Resistance

6.7

7_0

7.3

6_3

7.0

7.7

100

IZ = 1 mA

2-122

V
V
H

phase comparator state diagrams
PHASE COMPARATOR I

I

INPUT STATE
COMPARATOR
IN

~

>0

SIGNAL
IN

I

PHASE COMP lOUT

I

D

1

PHASE COMPARATOR II
INPUT STATE

yiN

COMPARA,TOR

SIGNAL
IN

TRI·STATE®

PHASE COMP II OUT
PHASE PULSES

FIGURE 2

typical waveforms
PHASE COMPARATOR I

SIGNAL IN

COMPARATOR IN

PHASE COMP lOUT
VCOIN
(LOW PASS FILTER OUTPUT)

FIGURE 3. Typical Waveform Employin'g Phase Comparator I in Locked Condition
PHASE COMPARATOR II

SIGNALIN

VOD~
VSS

COMPARATOR IN
PHASE PULSES

PHASE CaMP II OUT

VOH
VOL

-r---1 . I I
-----J
L.........J
L...

VOH - - - , . - - - - - . . - - VOL----U
U
VOH
VOL

r L - - - - -L.r-----J

VCOINVOH~
(LOW PASS FILTER OUTPUT)

VOL-

FIGURE 4. Typical Waveform Employing Phase Comparator II in Locked Condition

2-123

typical performance characteristics

Typical Center Frequency vs
C1 for R1 = 10 k11, 100 k11
and 1 M11

Typical Frequency Offset vs
. C1 for R2" 10 k11, 100 k11
and 1 M11

Typical fMAX/fMIN vs

R2/R1

107

g

106

~

~ lOS,

~
a:

4
10
103

I-

~

10

~"

10 1

2

10 1

1

1
10- 5 10-4 10-3 10- 2 10- 1 1

10- 5 10-4 10- 3 10- 2 10-1 1
10 10 2
Cl - VCO TIMING CAPACITOR (pF)

Cl - VCO TIMING

FIGURE 5a

Typical veo Power Dissipation
at Center Frequency vs R1
~

Typical veo Power Dissipation
at fMIN vs R2

TA = Z5'C
VCOIN· Voo/Z, RZ = 00
INHIBIT'VsS

10 7

0

10 6

i;:j

1QS --;;;;:;i:l = 50 pF

C
a:

~

0

u

~;~ .Cl = 1 pF

10 4

I

0

~
~

1Q3

10. 2

~
~

~

106

~

...

a:

103

SUPPL V
VOLTAGE
VOO·15V
101i

10 2

5V

u

104

~

8

00

a:

a:

5V,=ff

TA=25'C

C

C

10V=ff

_'.

~~ == VCOIN' Voo/2, Rl • R2'

>=

~ 105

SUPPL V
VOLTAGE
Voo =15V

Typical Source Fo"ower
Power Dissipation vs RS

§"
.;;;

TA·25'C
VCOIN'VSS

107

~

>

...

R2IRI

FIGURE 5c

loB

z

~

lDZ

(pF)

FIGURE 5b

10 8

.;;;

10.

C~PACITOR

>
I

c

SUPPL V
VOLTAGE
Voo·15V

~

w
a:

10~:~
5V

10

:>

.,0

10

10

10 2

10

10

103

FIGURE 6a

1

I

104

10

...
0

R2 (kn)

Rl (kll)

RS- (kn)

FIGURE 6c

FIGURE 6b

Typical VCO Linearity vs
.'
R1 and C1
10 3
TA·25'C

TA' 25"C
VOO =15V, veolN' 7.5V ±5V. R2 = 00

V~O:,I,~V',V~O,I~,= ~V ~2:~~, ~2 7

00

10 2

g
>
I-

a:

~

r= % LINEARITV = 10 - 1(5V)
f-- . ... .
r-r-Cl' 50 p~ ~

10.

10 2

x 100

g

10

>
I-

F=~:fr·Oo.PF
f::
0.001 pF

f- 0jOlinpFI

10 •
0.1
10- 1

a:

~

I'-.~

f(2.5V) + f(7.5V)
2

:::;

I"l:
1' ......

=

% LINEAR lTV = 10 - 1(7.5V)
10

= ......

_ _ CI- 50pF

10

i=l:k'OO

pF
~
0.001 pF
r- O.OI,O.lpF

10 =
0.1
10-1

10

.....

IIII I I

~

.....

f(2.5V) + 1(12.5V)
2
10
Rl (kn)

Rl (kn)

FIGURE 7
Note. To obtain approximate total power dissipation of PLL system for no-signal input: Phase Comparator I, Po (Total)
Po (RS); Phase Comparator II, Po (Total) = Po (fMIN).

2-124

= Po

(fo) + Po (fMIN) +

design information
In addition to the given design information, refer to

This information is a guide for approximating the value
of external components for the CD4046B in a phaselocked-loop system. The selected external components
must be within the following ran!les: R 1, R2 ~ 10 kD.,
RS ~ 10 kD, C1 ~ 50 pF.

Figure 5 for R1, R2 and C1 component selections.

USING PHASE COMPARATOR I.
CHARACTERISTICS

VCO WITHOUT OFFSET
R2

USING PHASE COMPARATOR II

= ""

R2

"

l'L

""-

VCO WITH OFFSET

~ 00

'''0 ""rL ''''0
'0---

VCO Frequency

VCO WITHOUT OFFSET

VCO WITH OFFSET

-------'-

',---

--------

'MAX

2fL

'.

~

T
. . 2fL

-- I------L

'MIN

2'L

I

'MIN

'M!N

VoolZ

For No Signal Input

veo INPUT VOLTAGE

VCO in PLL system will adjust to center frequency, fa

Vee lZ
Vee
VCO INPUT VOLTAGE

. VOOIZ
Voo
VCO INPUT VOLTAGE

V~o

VoolZ

Voo

VCO INPUT VOLTAGE

VCO in PLL system will adjust to lowest operating frequency,
fmin

2 fL = full VCO frequency ranse

Frequency Lock Range, 2 fL

2 fL = f max - fmin
Frequency Capture Range, 2fC

RJ

IN~OUT

2fC'" -

C2

r1° RJ

C2

T-=

1~
--

1['

r1

Loop Filter Component

fC = fL
RJ

Selection

"t""'
-:;re2
R4

For 2 fC, see Rd.

Phase Angle Between Signal

90" at center frequency (fa), approximating 0° and

and Comparator

180 at ends of lock range (2 fL)

Always 0° in lock

0

Locks on Harmonics of

Yes

No

High

Low

Center Frequency
Signal Input Noise
Rejection
-Given: fa

-Given: fa and fL

-Use fa with Figure 5a to

-Calculate fmin from

determine R 1 and Cl

the equation

the equation
fmin

= fa -

fL

-Use fmin with Figure 5b
to determine R2 and Cl
VCO Component Selection
~-

-Given: f max
-Calculate fa from

-Calculate f max
fmin

fo=~
2

-Use fa with Figure 5a to
determine R 1 and Cl

from the equation
f max = fa + fL
fa - fL
fmin

-Us~

with Figure 5c
min
to determine ratio R2/
R1 to obtain Rl

REF. G.S. Moschytz, "Miniaturized RC Filters Using Phase-Locked Loop", BSTJ, May, 1965.
Floyd Gardner, "Phaselock Techniques," John Wiley & Sons, 1966.

2-125

-Given: fmin and f max
-Use fmin with Figure 5b to
determine R2 and C1
-Calculate f max
fmin
-Use ftax with Figure 5c
min
to determine ratio R2/R1
to obtain R1

CD4.~t47BM/CD4047BC low power monostable/astable multivibrator

general description
C04047B is capable of operating in either the monostable
or astable mode. It requires an external capacitor
(between pins 1 and 3) and an external resistor (between
pins 2.and 3) to determine the output pulse width in
the monostable mode, and the output frequency in the
astable mode:

•

True and complemented buffered outputs

•

Only one external Rand C required

MONOSTABlE MUl TIVIBRATOR FEATURES

Astable operation is enabled by a high level on the
astable input or low level on the astable input. The
output frequency (at 50% duty cycle) at Q and
outputs is determined by the timing components.
A frequency twice that of Q is available at the Oscillator
Output; a 50% duty cycle is not guaranteed.

a

•
•

Positive or negative-edge trigger
Output pulse width independent of trigger pulse
duration

•
•

Retriggerable option for pulse width e~pansion
Long pulse widths possible using small RC components by means of external counter provision

•

Fast recovery time essentially independent of pulse
width

•

Pulse-width accuracy maintained
approaching 100%

at duty cycles

Monostable operation is obtained when the device is
triggered by low-to-high transition at + triggger input
or high-to-Iow transition at - trigger input. The device
can be retriggered by applying a simultaneous low-to. high transition to both ~he + trigger and retrigger inp~ts.

•

Free-running or gatable operating modes

A high level on Reset input resets the outputs Q to low,
to high.

•
•
•

50% duty cycle
Oscillator output available
Good astable frequency stability
typical frequency
±2% + 0.03%fC @
deviation
100 kHz
±0.5% + 0.015%fC @
10 kHz
(circuits trimmed to frequency
VOO = 10V ±10%)

ASTABLE MUl TIVIBRATOR FEATURES

a

features
•

Wide supply voltage range

•

High noise immunity

•

Low power TTL
compatibility

3V to l5V
0.45 VOO typ
fan out of 2
driving 74L
or driving 74LS

applications

SPECIAL FEATURES
•

Low power consumption: special CMOS oscillator
configuration

•

Monostable
operation

(one-shot)

or

astable

(free-running)

•

Frequency discriminators

•
•
•
•

Timing circuits
Time-delay applications
Envelope detection
Frequency multiplication

•

Frequency division

block and connection diagrams

R-------,

r-----I

J
RC
COMMON

TIMING

Dual-In-Line and Flat Package

.

14 VOO
ASTABLE

- TRIGGER

C
TIMING

13
I+---~;o RETRIGGER

LOW
POWER
ASTABLE
MULTIVIBRATOR

+ TRIGGER

VOD~

9

~~-----------------~
2-126

EXTERNAL
RESET

VSS

TOPVIEW

OSC OUT

absolute maximum ratings

recommended operating conditions

(Notes 1 and 2)

(Note 2)

Voo de Supply Voltage
. -0.5 to +18VOC
VIN Input Voltage
-0.5 to VOO + 0.5VOC
.
--65°Cto+150°C
TS Storage Temperature Range
500 mW .
Po Package Oissipation
300°C
TL Lead Temperature (Solde~ing. 10 seconds)

Voo de Supply Voltage
VIN Input Voltage
T A Operating Temperature Range
C04047BM
C04047BC

dc electrical characteristics
PARAMETER
100

VOL

VOH

Quiescent Oevice Current

Low Level Output Voltage

High Level Output Voltage

CD4047BM

VIH

Low Level Input Voltage

High Levei Input Voltage

-55°C

CONOITIONS

MIN

liN

High Level Output Current

Input Current

Low Level Output Voltage

MAX

UNITS

160

pA

10

300

pA

VOO = 15V

20

20

600

IlA

1101< lilA
VOO = 5V

0.05

0.05

V

0.05

a
a

0.05

VOO = 10V

0.05

0.05

V

VOO = 15V

0.05

0

0.05

0.05

V

1101< lilA
VOO = 5V

4.95

4.95

5

4.95

V

VOO = 10V

9.95

9.95

10

9.95

V

14.95

14.95

V

14.95

2.25

VOO = 10V. Vo = 1V or 9V

3.0

4.5

3.0

3.0

V

VOO = 15V. Vo = 1.5V or 13.5V

4.0

6.75

4.0

4.0

V

VOO = 5V.

= 10V.
= 15V,

VOO = 5V.

Vo = 0.5V or 4.5V

15

1.5

VOO = 5V.

1.5

1.5

V

Vo = 0.5V or 4.5V

3.5

3.5

2.75

3.5

V

= 1V or 9V

7.0

7.0

5.5

7.0

V

Vo

Vo = 1.5V or 13.5V

11.0

11.0

8.25

11.0

V

Vo = O.4V

0.64

0.51

0.88

0.36

mA
mA

= 10V.
= 15V.

= 0.5V

1.6

1.3

2.25

0.9

VOO

Vo = 1.5V

4.2

3.4

8.8

2.4

mA

VOO

= 5V.

Vo = 4.6V

-0.64

-0.51

-0.88

-0.36

mA

VOO = 10V. Vo = 9.5V

-1.6

-1.3

-2.25

-0.9

mA

VOO = 15V. Vo = 13.5V

-4.2

-3.4

-8.8

-2.4

Vo

VOO = 15V. VIN = OV

-0.1

VOO = 15V. VIN = 15V

0.1

-10- 5
10-5

mA

-Q.l

-1.0

IlA

0.1

1.0

IlA

CD4047BC (Note 2)
. 25°C

-40°C

VOL

MIN

5

PARAMETER
Quiescent Oevice Current

MAX

10

de electrical characteristics

100

TYP

5

VOO

10H

MIN

VOO = 5V

VOO
Low Level Output Current

125°C

25°C

MAX

VOO = 10V

VOO

10L

-55°C to +125°C
-40°C to +85°C

(Note 2)

VOO=15V
VIL

3 to 15VOC

o to VOOVOC

CONDITIONS

MIN

MAX

MIN

TYP

85
MAX

MIN

u

c
MAX

UNITS

20

20

150

IlA

VOO

= 10V

40

40

300

VOO

=

15V

80

80

600

IlA
pA

VOO = 5V

1101< 1 IlA
VOO = 5V
VOO
VOO

= 10V
= 15V
2·127

0.05

0

0.05

0.05

0.05

0

0.05

0.05

V

0.05

0

0.05

0.05

V

V

(.)

co

~

dc electrical characteristics

o

-40°C

V
C

(.)

,.........
~
m
~
o
.q-

(Continued) CD4047BC (Note 2)

CONDITIONS

PARAMETER
VOH

VIL

High Level Output Voltage

Low Level Input Voltage

c

(.)
VIH

IOL

10H

High Level Input Voltage

Low Level Output Current

High Level Output Current

MIN

85°C

TYP

MAX

UNITS

MIN

MAX

1101< 1 pA
4.95-

4.95

5

4.95

VOO = 10V

9.95

9.95

10

9.95

V

VOO = 15V

14.95

14.95

15

14.95

V

V

VOO = 5V, Va = 0.5V or 4.5V

1.5

2.25

1.5

1.5

VOO = 10V, Va = IV or 9V

3.0

4.5

3.0

3.0

V

VOO = 15V, Va = 1.5V or 13.5V

4.0

6.75

4.0

4.0

V

V

3.5

3.5

2.75

3.5

V

VOO = 10V, Va = IV or 9V

7.0

7.0

5.5

7.0

V

VOO = 15V, Va = 1.5V or 13.5V

11.0

11.0

8.25

11.0

V

0.52

0.44

0.88

0.36

rnA

VOO = 5V,

VOO = 5V,

Va = 0.5V or 4.5V

Vo = O.4V

VOO = 10V, Va = 0.5V

1.3

1.1

2.25

0.9

rnA

Voo = 15V, Va = 1.5V

3.6

3.0

8.8

2.4

rnA

-{l.52

-{l.44

-{l.88

-{l.36

rnA

-1.3

-1.1

-2.25

-{l.9

rnA

-3.0

-8.8

VOO = 5V,
VOO

Input Current

MIN

VOO = 5V

Vo = 4.6V

VOO = 10V, Vo = 9.5V

liN

25°C

MAX

= 1'5V,

Va

= 13.5V

-3.6

VOO = 15V, VIN:" OV
VOO = 15V, VIN

= 15V

-2.4

rnA

-0.3

-10- 5

-{l.3

-1.0

pA

0.3

10-5

0.3

1.0

/1A

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed, they are not meant to imply
that the devices should be operated at these limits. The table of "Recommended Operating Conditions" and "Electrical Characteristics" provides
conditions for actual device operation.
Note 2: VSS = OV unless otherwise specified.

ac electrical characteristics CD4047B
T A = 25°C, CL = 50 pF, R L = 200k, Input tr = tf = 20 ns, unless otherwise specified.
PARAMETER
tPHL, tPLH

CONDITIONS

Propagation Delay Tim? Astable,
Astable to Osc Out

tPHL, tPLH

tPHL, tpLH

Astable, Astable to 0,

5

+ Trigger, - Trigger to Q.

5

TYP

MAX

= 5V
VOO = 10V
VOO = 15V

200

400

ns

100

200

ns

80

160

ns

Voo = 5V

550

900

ns

VOO

VOO =.IOV

250

500

ns

200

400

ns

Voo;= 5V

700

1200

ns

= 10V
= 15V

300

600

ns

240

480

ns

= 5V
VOO = 10V
VOO = 15V

300

600

ns

175

300

ns

150

250

ns

Voo = 5V

300

600

ns

VOO = 10V

125

250

ns

VOO

= 15V

100

200

ns

Voo

= 5V
= 10V

100

200

ns

50

100

ns

VDD = 15V

40

80

ns

VDO

tPHL, tpLH

tTHL. tTLH

+ Trigger, Retrigger to Q,

Reset to Q,

5

5

Transition Time Q,

5, asc Out

Voo

VOO

tWL,tWH

Minimum Input Pulse Duration

Any Input
VOO = 5V

500

1000

ns

= 10V

200

400

ns

VOO=15V

160

320

ns

15

ps
/1S

VOO

tRCL, tFCL

= 5V

+ Trigger, Retrigger, Rise and

VOO

Fall Time

VOO = 10V

5

= 15V

5

/1S

7.5

pF

VOO
CIN

UNITS

VOD = 15V

VOO

tPHL, tPLH

MIN

Average Input Capacitance

Any Input

2-128

5

logic diagram

ASTABLE ~----I ")>0------,

AmID

0-;.---...::;..----....,

+ TRIGGER 0.;;......- : : - - - - - ,
- TRIGGER

OSC OUT

VSS

EKT RESET

'Special input protection circuit to permit larger input-voltage swings

truth table

TERMINAL CONNECTIONS
FUNCTION

INPUT PULSE
TOVOO

TOVSS

OUTPUT PULSE
FROM

TYPICAL OUTPUT
PERIOD OR
PULSE WIDTH

TO

Astable Multivibrator
Free-Running

4,5,6,14 7,8,9,12

True Gating

4, 6, 14

7,8,9,12

5

10,11,13

Complement Gating

6,14

5,7,8,9,12

4

10,11,13

Positive-Edge Trigger

4,14

5,6,7,9,12

8

10,11

Negative-Edge Trigger

4,8,14

5,7,9,12

6

10,11

Retriggerable

4,14

5,6,7,9

8,12

10,11

External Countdown*

14

5,6,7,8,9,12

(See'Figure)

(See Figure)

10,11,13

tA(10, 11)
tA(13)

=4.40 RC

= 2.20 RC

Monostable Multivibrator

Note: External resistor between terminals 2 and 3. External capacitor between terminals 1 and 3.

* Typical

Implementation of External Countdown Option

2-129

tM(10, 11)

= 2.48 RC

(See Figure)

u

OJ

~
o
v
c
u
........
:2
OJ

~

o

v
c

u

typical performance characteristics

,

:.!

....
=>
0

u
0
0

""
c(

15

~\

_\ ~- r- -- ~A .125·~-

\BI

10

10

c;
a:
0

c(

a:
=>

\

"

......~

I'--..

0

\.B ,

I'\.. 1""'......

-5

"

0

10

f-+-

i

-

~I'-o..

~

10

...

>
u

....\

f-f-

c(

~

:I:

E

....
;:
'"

...

..

10

fa,O:

R

22k

10 pF

A

B

100 kHz
10 kHz

22k
220k

100 pF
100 pF

C

220k
202M

1000 pF
1000 pF

C

D
E

220k
202M

1000 pF

15

a:
~ . 10

I"'"

>
u

!

>
u

c(

-5

:I:

....

-5

~

-10

~

c(

~

C

10 pF
100 pF
100pF
1000 pF

Typical Q and 0: Pulse Width
Accuracy vs Temperature
Monostable Mode Operation
I~,

0"",
a:
o

o

7/.15
60/.15
550/.15
5.5 ms

R

22k
22k
220k'

g

....
=>

~10

o

tM
2/.1s

B

Typical a, Q and Osc Out
Period Accuracy vs Temperature
Astable Mode Operation

i

15

VOO -SUPPlVVOlTAGE (V)

1000 kHz

E 100 Hz

,-

I'\..

A

D 1 kHz

,i"-

~~

-5

VOO - SUPPl V VOLTAGE (V)

C

"......1\

~ '\\

=>

15

.125°~--

A

a:

1\

I\. \

fA

"1\\

15

'"z
c::l

u
u

'"

g
Ic::l
c(

I\.ri\.
?' ......

>
u

c(

Typical a, Q, Pulse Width,
Accuracy vs Supply Voltage
Monostable Mode Operation

Typical a, Q, Osc Out Period
Accuracy vs Supply Voltage
(Astable Mode Operation)

-10

.
=>

-65 -35

-5

25

55

85

115 145

-65 -35 -5 25 55

TA - AMBIENT TEMPERATURE ('C)

fa, 0:
A 1000 kHz

c

R

22k

10 pF

85 115 145

TA - TEMPERATURE (OC)

A

tM

R

22k

10 pF

C

B

100 kHz

22k

100 pF

B

2/.1s
7/.1s

10 kHz

220k

100 pF

C

60/.ls

22k
220k

100 pF

C

D 1 kHz-

220k

1000 pF

D

550/.ls

220k

1000 pF

100 pF

timing diagrams
Astable Mode

Monostable Mode

OSCOUT~

+TRIGGER

.Jllo......___. . . n
. . .____

OSCOUT~

L
Retrigger Mode
+TRIGGER
RETRIGGEO

11
11
.
----I L....-.J L - - .

OSCOUT~

n

c.;:a.
o

~
0)

tXJ

s:
.......
n

CD4048BM/CD4048BC TRI-STATE®
expandable 8-function 8-input gate

c.;:a.
o.;:a.

general description
The CD4048BM/CD4048BC is a programmable 8-input
gate. Three binary control lines Ka , Kb and Kc determine the 8 different logic functions of the gate. These
functions are ()R, NOR, AND, NAND, OR/AND, OR/
NAND, AND/OR and AND/NOR_ A fourth input,
Kd, is a TRI-STATE control. When Kd is high, the
output is enabled; when Kd is low, the output is a high
impedance. This feature enables the user to connect
the device to a common bus line. The Expand input
permits the user to increase the number of gate inputs.
For example, two 8-input CD4048's can be cascaded
into a .16-input multifunction gate. When the Expand

input is not used, it should be connected to VSS. All
inputs are buffered and protected against electrostatic effects.

features
•

Wide supply voltage range

•
•
•

f-!igh
High
TTL
V CC

•

Many logic functions in one package

3V to 15V

0.45 VDD typ
noise immunity
sink and source current capability
compatibility-drives 1 standard TTL load at
= 5V, over full temperature range

logic diagram

VOO

."~.
VDD = (16)
VSS = (8)

connection diagram

Dual-In-Line and Flat Package
FUNCTION CONTROL

Ls

~
15

14

13

12

11

t-

r-

1

OU;PUT

9

10

2

3

4

5

S

1

TRI~~ATE

'-'H_ _~.--_ _ _ _
E;

FUN~~IDN

CONTROL

INPUTS

CONTROL

TOP VIEW

2-131

8

1

Vss

•

00
tXJ

n

absolute maximum ratings

recommended operating conditions

(Notes 1 and 2)

(Note 2)

-O.SV to +18V
VDD Supply Voltage
VIN Input Voltage
-o.SV to VDD + O.SV
-6SoC to +1S0°C
TS Storage Temperature Range
SOOmW
PD Package Dissipation
300°C
TL Lead Temperature, (Soldering, 10 seconds)

VDD Supply Voltage
VIN Input Voltage
T A Operating Temperature Range
CD4048BM
CD404SBC

dc electrical characteristics

IDO

VOL

CONDITIONS

Quiescent Device Current

Low Level Output Voltage

MIN

10Z

liN

5.0

lS0

10

300

Il A
fJ.A

VDO = lSV

20

0.01

20

600

fJ.A

O.OS

0

O.OS

0.05

V

0.05

0

0.05

0.05

V

0.05

0

0.05

0.05

V

1101 < 1 fJ.A, VIH = VDO, VIL= OV

High Level Output Voltage

-

1101 < lilA, VIH = VOO, VIL = OV
VOO = 5V

4.95

4.95

5

4.95

V

VOO = 10V

9.95
14.95

9.95
14.95

10

9.95
14.9S

V

Low Level Input Voltage

High Level Input Voltage

High Level Output Current

1.5

2.25

1.5

1.5

V

4.5

3.0

3.0

V

VOO = 15V, Va = 1.5V or 13.5V

4.0

6.75

4.0

4.0

V

3.S

3.S

2.75

3.5

V

7.0.
11.0

7.0

S.S

7.0

V

11.0

S.2S

11.0

V

VIH = VOO, VIL = OV
VOO= 5V, Va = O.4V

2.8

2.3

4.0

1.6

rnA

VOO = 10V, Va = 0.5V

6.4

5.2

11

3.6

rnA

VOO = lSV, Va = 1.SV

14

·ll.S

23

S.O

rnA

= VOO, VIL = OV
VOO = 5V, Va = 4.6V
VOO = 10V, Va = 9.SV
VOO = 1SV, Va = 13.SV

-2.S

-2.3

-4.0

-1.6

rnA

-£.4
-14

-S.2

-11

-3.6

rnA

-11.5

-23

-S.O

VIH

TRI·STATE Leakage

VOO = 1SV. Va = OV

Current

VOO

= lSV, Va =

lSV

0.2

Input Current

VOO

= lSV, VIN = OV

-0.1

PARAMETER

-0.2

0.1

-2

fJ.A

0.002

0.2

2

Il A

-lO- S
10-5

-0.1

-1.0

0.1

1.0

Il A
Il A

8Soc

2SOC

-40°C
MIN

MAX

MIN

TYP

MAX

MIN

MAX

UNITS

VOO

= 5V

20

150

pA

= 10V

20
40

0.01

VOO

0.01

40

300

fJ.A

VOO = lSV

SO

0.01

SO

600

fJ.A

O.OS

0

0.05

0.05

V

0.05
0.05.

0
0

O.OS

0.05

V

0.05

0.05

V

\

Low Level Output Voltage

rnA

-0.002 -0.2

CD4048BC (Note 2)

CONDITIONS

Quiescent Oevice Current

V

3.0

1101< lilA
VOO = 5V, Va = 0.5V or 4.SV
VOO = 10V, Va = 1V or 9V

Low Level Output Current

15

1101<11lA
VOO = 5V, Va = 0.5V or 4.5V
VOO = 10V, Va = lV or 9V

dc electrical characteristics

VOL

UNITS

0.Q1

VOO = lSV. VIN = lSV

100

MAX

MIN

0.01

VOO = lSV, Va = 1.SV or 13.SV

10H

MAX

10

VOO = 15V

10L

12SoC

TYP

5.0

VOO = 15V

VIH

MIN

VDD = SV

VOO = 10V

VIL

2SOC

MAX

VDO = 10V

VOO = SV

VOH

-5S0C to +12SoC
-40° C to +SSo C

CD4048BM (Note 2)
-5SoC

PARAMETER

3V to lSV
OV to VDD

1101 < lilA. VIH
VOO
VOO

= VOO. VIL = OV

= SV

= 10V
VOO = 1SV
2·132

de electrical characteristics

(Continued)

CD4048BC (Note 2)
-40"C

CONDITIONS

PARAMETER
VOH

High Level Output Voltage

1101 < 1 /l.A., VIH

= VOO,

MIN
VIL

VOO = 1OV.
VOO
VIL

Low Level Input Voltage

VOO

= 15V
= 5V,
= 10V,

VOO = 15V,
High Level Input Voltage

Low Level Output Current

IOH

ITL

liN

High Level Output Current

MAX

4.95

4.95

5

4.95

V

9.95

9.95

10

9.95

V

14.95

14.95

15

14.95

V

= 0.5V or 4.5V
= 1V or av
Va = 1.5V or 13.5V
Va

1.5

2.25

1.5

1.5

V

3.0

4.5

3.0

3.0

V

4.0

6.75

4.0

4.0

V

= 0.5V or 4.5V
= 1V or av
Va = 1.5V or 13.5V

V

VOD

Vo

3.5

3.5

2.75

3.5

VOO

Va

7.0

7.0

5.5

7.0

V

l1.(i

11.0

8.25

11.0

V

2.3

2.0

4.0

1.6

mA

5.2

4.5

11

3.6

mA

11.5

9.8

23

8.0

mA

= VOD, VIL = OV
= 5V, Va = OAV
VOO = 10V, Va = O.5V
VOD = 15V, Vo = 1.5V
VIH

= VOO, VIL = OV
VOO = 5V, Va = 4.6V
VOO = 10V, Va = 9.5V
VOO = 15V, Va = 13.5V
VIH

Current

=-15V,
VOD = 15V,

Input Current

VOO

TRI·STATE Leakage

UNITS
MIN

Vo

VOD
\

85°C
MAX

1101<1/lA

= 5V,
= 10V,
VOO = 15V,

IOL

TYP

1101<111A
VOO

VIH

MIN

= OV

= 5V

VOO

25"C

MAX

VOO

VOO

-2.3

-2.0

-4.0

-1.6

mA

-5.2

-4.5

-11'

-3.6

mA

-9.8

-23

-8.0

mA

-0.6

-0.005

-0.6

-2

JiA

0.6

0.005

0.6

2

/lA

-0.3

-10- 5
10-5

-0.3

-1.0

JiA

0.3

1.0

JiA

-11.5

= OV
Va = 15V
Va

I

= 15V, VIN = OV
= 15V, VIN = 15V

0.3

Noto 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply
that the devices should be operated at these limits. The tables of "Recommended Operating Conditions" and "Electrical Characteristics" provide
conditions for octual device operation.
Nota 2: VSS = OV unless otherwise specified.

ac electrical characteristics

TA = 25°C, CL = 50 pF, RL =200krl., and tr = tf = 20 ns, unlessotherwise specified.

PARAMETER
tPHL, tpLH

tPLZ, t PHZ

Propagation Oelay Time

Propagation Delay Time, Kd to
High Impedance (From Active
Low or High Level)

tPZL, t PZH

tTHL, tTLH

Propogation Delay Time, Kd to

CONDITIONS

= 5V
VOO = 10V
VOD = 15V
VOO

= 1.0kU
VDD = 5V
VDO = 10V
VOD = 15V

MIN

TYP

MAX

UNITS

425

850

ns

200

400

ns

160

320

ns

175

350

ns

125

250

ns

100

200

ns

RL

RL

= 1.0kU

Active High or Low Level

VOO = 5V

225

450

ns

(From High Impedance)

VOO = 10V

100

200

ns

VOO = 15V

70

140

ns

VOD = 5V

100

200

ns

50

100

ns

40

80

ns

5

7.5

pF

22.5

pF

Output Transition Time

VOD

= 10V

VOO = 15V
CIN

Input Capacitance

COUT

Tristate output

,

Any Input

Capacitance

2-133

(,)

al

to

truth table

~

OUTPUT
FUNCTION

o

~

c

CONTROL INPUTS
Kc
Kd
Ka
Kb

BOOLEAN
EXPRESSION

0
0
0

0
0
1
1
0

J=A·S·C·D·E-F·G·H

0
1
1

AND/NOR

J = (A • S • C • D) + (E • F - G ·H)

1

AND/OR

J = (A • S • C • D) + (E • F • G • H)

NOR

J=A+S+C+D+E+F+G+H

OR

J=A+S+C+D+E¥F+G+H

OR/AND

J = (A + S + C + D) - (E + F + G + H)

OR/NAND

J = (A + S + C + D) • (E + F + G + H)

al

AND

J=A·S·C·D·E·F"G·H

~

o

NAND

c

(,)

.......
~

to
~

Hi-Z

(,)

-

0
1

1

0
1
'1

0
1
0
1
0
1

X

X

X

UNUSED
INPUTS

1-

VSS

1
1

VSS

1
1

VSS

VSS
VDD

1

VDD

1

VDD

1
0

VDD
X

,

Positive logic: 0 = low level. 1 = high level. X = Irrelevant. EXPAND Input tied to VSS-

ac test circuits and switching time waveforms
Logic Propagation Delay Time Tests
VOD
VOO
16

------,L

..l!~~--"'\

INPUT
OV

INPUTS
VOO------------~~__--~

OUTPUT J
OV-----~

ITHL

TRI-STATE Propagation Delay Time Tests
VOO
VOO
OV-----+~~---

TAl-STATE
CONTROL
OUTPUT J

VOD

TRI,STATE K
CONTROL d

OUTPUT J

typical performance characteristics
Propagation Delay vs Load
Capactiance

->

Output Transition Time vs
Load Capacitance

~

600

;::

g
z

400

~

300

~

200

-

0

2:

o

;::

;::

I~
~

300

::;

500

~o

200
VCC·5V

100

I

:z:

100

-'

!:"

~

0

0

50

100

150

!:"

200

CL - LOAD CAPACITANCE hiF)

o

~

o

__

~

____- L____L -__

50

100

150

CL -LOAD CAPACITANCE (pF)

2-134

~

200

n

c

basic logic configurations

~

NOR

A~
B

B

C

C

o

0

",..1

A~

~

CO

m

B

.
'

s:

C

D

A l s

",..1 . '

.,

o

NAND

OR

",..1·

= 001

l:

'

101

"cn

~

o

~

CO

m

AND

OR/AND

OR/NAND

E X P A N D - - - - - : - - : - - - -....

EXPAND---------~

= 010

= 100

=

AND/OR

all

AND/NOR

EXPAND

EXPAND

= 111

= 110

actual circuit configurations
NOR

OR

D

0

EXPAND

EXPAND

NAND

EXPAND

E

KaKbKc

= 000

AND

EXPAND

-------1

EXPAND

= 100

= 001

= 101

OR/AND

OR/NAND

-------1

EXPAND-------I

= 010

AND/OR

= all

AND/NOR

EXPAND-------I

EXPAND-------I

= 111

= 110

2·135

n

(.)

en
co
~
o

truth table for EXPAND feature
COMBINED
OUTPUT
FUNCTION

~

c

(.)
........

NOR
OR
AND
NAND
OR/AND
OR/NAND
AND/NOR
AND/OR

~

en
co
~
o
~

c

(.)

FUNCTION
NEEDED AT
EXPAND INPUT
OR
OR
NAND
NAND
NOR
NOR
AND
AND

OUTPUT BOOLEAN
EXPRESSION

J
J
J
J
J
J
J
J

= (A + B + C + D + E + F + G + H) + (EXP)
= (A + B + C + D + E + F + G + H) + (EXP)
= (ABCDEFGH) • (EXP)
= (ABCDEFGH) • (t)W)
= (A + B + C + D) • (E + F + G + H) • (EXP)
= (A + B + C T D) • (10 + F + G + H) • ('E'5{l!)
= (ABeD) + (EFGH) + (EXP)
= (ABCD) + (EFGH) + (EXP)

Note. Positive logic is assumed. (EXP) represents the logic level present at the EXPAND input.

typical applications of EXPAN D feature
16-lnput NOR Gate

Voo

OUTPUT

12-lnput 'OR/AND Gate

Voo

OUTPUT

voo

XI
Xl
Xl
X4

Output = (A + B + C + D) • (E +
G + H) • (X1 + X2 + X3 + X4) F

A1 + 81 + Cl + D1 + El + F1 + Gl +
A1 + A2 + B2 + C2 + D2 + E2 + F2 + G2 + A2

Output

2-136

+

n
c

~

o

~

c.o

s:

.......

n

c

CD4049M/CD4049 C hex inverting buffer
CD4050BM/CD4050BC hex non-inverting buffer

~

o

~

general description

features

These hex buffers are monolithic complementary MOS
(CMOS) integrated circuits constructed with Nand
P-channel enhancement mode transistors. These devices
feature logic· level conversion using only one supply
voltage (VOO). The input-signal high level (VIH) can
exceed the VOO supply voltage when these devices are
used for logic level conversions. These devices are
intended for use as hex buffers, CMOS to OTL/TTL
converters, or as CMOS current drivers, and at VOO =
5V, they can drive directly two OTL/TTL loads over
the full operating temperature range.

3V to 15V
• Wide supply voltage range
• Oirect drive to 2 TTL loads at 5V over full temperature range
• High source and sink current capability
• Special input protection permits input voltages greater
'
than VOO

c.o

•
•
•
•

CMOS
CMOS
CMOS
CMOS

n

hex inverter/buffer
to OTL/TTL hex converter
current "sink" or "source" driver
high-to-Iow logic level converter

c

~

o
CJ'I
o
OJ

16

15

voo

G=A

n

CD4049M/CD4049C

CD4050BM/CD4050BC

Dual-In-Line and Flat Package

NC
14

A

K=E

13

~

o
CJ'I
o

OJ

Dual-In-Line and Flat Package

l=F

n
c

s:
.......

applications

connection diagrams

NC

p

J = IT
11

12

H=B

I

=c

NC

10

16

Vss

Voo

TOP VIEW

l=F

NC
14

15

G= A

A

K=E

13

12

H=B

TOP VIEW

schematic diagrams
CD4049M/CD4049C

CD4050BM/CD4050BC

1 of 6 Identical Units

1 of 6 Identical Units

2-137

J= 0
11

1= C

10

Vss

U

m

o
LO
o
~

c

u
.........

:a:m

o

absolute maximum ratings

recommended operating conditions

(Notes 1 and 2)

(Note 2)

VDD Supply Voltage
-o.5V to +18V
VIN Input Voltage
-o.5V to +18V
V.oUT Voltage at Any .output Pin
-o.5V to VDD + 0.5V
TS Storage Temperature Range
--65°C to +150°C
Po Package Dissipation
500mW
TL Lead Temperature (Soldering, 10 seconds)
300°C

VDD Supply Voltage
VIN Input Voltage
V.oUT Voltage at Any Qutput Pin
, T A .operating Temperature Range
CD4049M, CD4050BM
CD4049C;CD4050BC

dc electrical cha racte ristics

(Note 2)

3V to 15V
OV to 15V
to VDD

o

-55°C to +125°C
--40° C to +85° C

LO

~

o

~

c

u
cj
en

CD4049M, CD4050BM

~

o

~

c

u

.........

:a:

100

Quiescent Oevice Current

~

VOl

Low Level Output Voltage

~

25°C

CONDITIONS
MIN

en

o

-55°C

PARAMETER

VOO

= 5V
= 10V
= 15V

VIH

= VOO,

VOO
VOO

MAX

MIN

TYP

125°C
MAX

MIN

MAX

UNITS

1.0

0.01

1.0

30

IlA

2.0

0.01

2.0

60

IlA

4.0

0.03

4.0

120

IlA

0.05

a
a

0.05

0.05

V

0.05

0.05

V

0.05

0.05

V

= 0,

VIL

1101<11lA

c

VOO

= 5V
= 10V
= 15V

VIH

= VOO,

VOO

u

VOO

VOH

High Level Output Voltage

0.05
0.05

= 0,

VIL

1101<11lA
VOO
Von
VOO
VIL

Low Level Input Voltage

1101<11lA

IC04050BM Only)

VOO
VOO
VOO

VIL

Low Level Input Voltage
IC04049UBM Only)

VOO
VOO

1101<11lA

IC04050BM Only)

VOO
VOO

High Level Input Voltage
IC04049UBM Only)

VOO
VOO

10H

liN

Vo
Vo

9.95

10

9.95

V

14.95

14.95

15

14.95

V

= 0.5V
= lV
= 1.5V

= 5V,
= 10V,
= 15V,

Vo
Vo
Vo

Vo
Va
Va

= 4.5V
= 9V
= 13.5V
= 4.5V
= 9V
= 13.5V

= 5V,
= 10V,
= 15V,

Va
Va
Va

= 0.5V
= lV
= 1.5V

= VOO, VIL = OV
= 5V, Va = O.4V
VOO = 10V, Va = 0.5V
VOO = 15V, Va = UV

Low Level Output Current

VIH

INote 3)

VOO

= VOO, VIL = OV
= 5V, Va = 4.6V
VOO = 10V, Va = 9.5V
VOO = 15V, Va = 13.5V

High Level Output Current

VIH

INote 3)

VOO

Input Current

Vo

4.95

4.95

V

1.5

2.25

1.5

1.5

V

3.0

4.5

3.0

3.0

V

4.0

6.75

4.0

4.0

V

1.0

1.5

1.0

1.0

V

2.0

2.5

2.0

2.0

V

3.0

3.5

3.0

3.0

V

3.5

3.5

2.75

3.5

V

7.0

7.0

5.5

7.0

V

11.0

11.0

8.25

11.0

V

V

110 1< lilA
VOO

10L

= 5V,
= 10V,
= 15V,

High Level Input Voltage

VOO

VIH

= 5V,
= 10V,
= 15V,

4.95
9.95

1101< lilA
VDO

VIH

= 5V
= lOV
= 15V

VOO

=

15V, VIN

VOO

= 15V,

VIN

4.0

4.0

3.5

4.0

8.0

8.0

7.5

8.0

V

12.0

12.0

11.5

12.0

V

mA

5.6

4.6

12

9.8

12

3.2
6.8

mA

35

29

40

20

mA

-1.3

-1.1

-1.6

-0.72

mA

-2.6

-2.2

-3.6

-1.5

mA

-8.0

-7.2

-12

-5.0

= OV
= 15V

-0.1
0.1

-10- 5
10-5

mA

-0.1

-1.0

IlA

0.1

1.0

IlA

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply
that the devices should be operated at these limits. The table of "Recommended .operating Conditions" and "Electrical Characteristics" provides
conditions for actual device operation.
Note 2: VSS

= OV

unless otherwise specified.

Note 3: These are peak output current capabilities. Continuous output current is rated at 12 mA maximum. The output current should not be
allowed to exceed this value for extended periods of time.

2·138

dc electrical characteristics

n

c

CD4049C, CD4050BC (Note 2)

~

o

~

(D
25"C

-40"C
PARAMETER
IDD

VOL

Quiescent Device Current

Low Level Output Voltage

CONDITIONS

MIN ..

MAX

MIN

TYP

85°C
MAX

MIN

MAX

UNITS

VDD = 5V

4

0.03

4.0

30

/lA

VDD = 10V

8

0.05

8.0

60

/lA

VDD = 15V

16

0.07

16.0

120

/lA

0

0.05

0.05

V

VDD = 10V

0.05
0.05 .

0

0.05

0.05

V

VDD = 15V

0.05

0

0.05

0.05

V

VIH = VDD, VIL = OV,
VDD = 5V

4.95

4.95

5

4.95

V

VDD = 10V

9.95

9.95

10

9.95

V

14.95

VDD=15V
Low Level Input Voltage
(CD4050BC Only)

VIL

VIH

VIH

10L

liN

1.5

V

VDD = 10V, Vo = IV

3.0

4.5

3.0

3.0

VDD = 15V, Vo = 1.5V

4.0

6.75'

4.0

4.0

V
V'

VDD, = 5V,

Vo = 0.5V

1.0

1.5

1.0

'1.0

V

VDD = 10V, Vo = 9V

2.0

2.5

2.0

2.0

V

VDD = 15V, Vo = 13.5V

3.0

3.5

3.0

3.0

V

High Level Input Voltage

1101< l/lA

(CD4050BC Only)

VDD = 5V,

(Note 3)

10H

1.5

(CD4049UBC Only)

Low Level Output Current

Vo = 4.5V

3.5

3.5

2.75

3.5

V

VDD = 10V, Vo = 9V

7.0

7.0

5.5

7.0

V

VDD = 15V, VO = 13.5V

11.0

11.0

8.25

11.0

V

110 1< 1/l1\
VDD = 5V, Vo = 0.5V

4.0

4.0

3.5'

4.0

V

VDD = 10V, Vo = IV

8.0

8.0

7.5

8.0

V

VDD = 15V, Vo = 1.5V

12.0

12.0

11.5

12.0

V

Vo = 4.5V

VIH = VDD, VIL = OV
Vo = O.4V

4.6

4.0

5

3.2

mA

VDD = 10V, Vo = 0.5V

9.8

8.5

12

6.8

mA

VDD = 15V, Vo = 1.5V

29

25

40

20

mA

Vo = 4.6V

-1.0

-0.9

-1.6

-D. 72

mA

VDD = 10V, Vo = 9.5V

-2.1

-1.9

-3.6

-1.5

mA

-5

VDD = 5V,

High Level Output Current

VIH = VDD, VIL = OV

(Note 3)

VDD = 5V,

Input Current

V

2.25

1I01<1/lA

(CD404!)UBC Only)

14.95

15

1.5

Low Level Input Voltage

High Level Input Voltage

14.95

IIOI

bx 0 R by

LOGIC
LEVEL
CONVERSION

U1
N

tJJ
~

........

n

c

OUT/IN
ex OR ey

~

o

U1
N

tJJ

r>

INH

n

c

~

o

Vss

U1
tAl

CD4053BM/CD4053BC

tJJ
~

........

n

c

~

o

U1
tAl

tJJ

n
INPUT STATES
INHIBIT
0
0

C

B

"ON" CHANNELS
A

a a a
a 0 1

CD4052B CD4053B

CD4051B

a

- - - - - f-----:-

1

ox, OY

ex, bx, ax

lX,lY

ex, bx, ay
CX,hY,ax

0

0

1

0

2

2X,2Y

0

a

I

1

3

3X,3Y

0

1

0

0

0

1

0

1

5

0

1

1

.

4

0

6

0

1

1

1

1

II

cy, bx, ay
cy, by, ax

7
NONE

* Don't C~te condition,

2-147

cX,bY,ay
, cy,hx,ax

cy, by, ay

I

NONE

NONE

U
£Xl
M

switching time waveforms

In

o

~

c

u

""'~

£Xl
M

In

o

~

.--tf

tr

c

ADDRESS
INPUTS
A,B or C

u

ci

'£Xl
N

In

VDO

~

VDS

o

~tPLH

VDD

1"---I

--"1
1

c

50%

u

I
I
I

""'~

VDD

1

1
1

,

SIGNAL INPUT TO SIGNAL OUTPUT

£Xl

I
I

Vas

N

In

1
1

o

~

ADDRESS TO SIGNAL OUTPUT

c

u

ci

£Xl
....
In

o

~

c

VDD

u

""'~

£Xl
In

....

IN/OUT or
OUT/IN

o

r'50 PF

~

c

u

VDD

VDD

1Krl

a

OUT/IN or
IN/OUT

IN/OUT or
OUT/IN

r

90%

tpZL
VDD

50PF
Vas

0

2·148

--.

(")

C

special considerations

~

tional switch must not exceed 0.6 V at TAO:;;; 25°C, or
0.4 V atT A> 25°C (calculated from RON values shown).
No V 00 current will flow through R L if the switch
current flows into OUT/IN pin.

In certain applications the external load-resistpr current
may include both Voo and signal-line components. To
avoid drawing V oo . current when, switch current flows
into IN/OUT pin, the voltage drop across the bidirec-

o

U1
~
Cl

s:

........
(")

C

typical performance characteristics

~

o

"ON" Resistance vs Signal
Voltage for T A ~ 2SoC

g

400

-

350

...J-

300

~

250

400
-

t! 1

u

VEEI.15J

t;
~

P 150
zzU::

~

I-"

~

(")

c
~
o

'300

:i

250

~

200

~

150

T~=~

o
0

-8

u

z

~

-6

J

300

~

5

o

0

TA = +125'C

'rl=~

~I

100
50

i t::t

t;
~

I-"

~

......

51

1-"-\

~

I

250

/~ "",l\.

200

1/

150

1'1

-8

IIIII

2-149

s:

TA=+25'C

l\.~ I.U50~

........
(")

C

~

o

IIIII

-6

-4 -2

a

SUPPLY VOLTAGE (V,s)(V)

SIGNAL VOLTAGE (V's) (V)

U1
CN
Cl

-11111

a
-4 -2

~

o

I AI I I I

50

o

(")

c

IIIII

100

TA = -55'C
-8 -6

U1
N
Cl

TA = +125"C

..... 1-"

300

:i

z

z

~

-2

350

u

250

150

-4

400

350

~

(")

C

"ON" Resistance as a
Function of Temperature for
VOO - VEE = SV

400

200

'" -~

SIGNAL VOLTAGE (V's) (V)

"ON" Resistance as a
Function of Temperature for
VOO - VEE = 10V

J...

s:

........

TA = -55'C

SIGNAL VOLTAGE (V's) (V)

-

...

50

o
-4 -2

.......... ..

TA=~

100

Vee - VEE '15V

-8 -6

U1
N
Cl

t;

~

"-

51

•

350

u

VL~=loy

I

100
50

J-

"
L

200

U1
~
Cl

"ON" Resistance as a
Function of Temperature for
VOO - VEE = lSV

6

8

U1
CN
Cl

(")

(J

I~
(J

"~

m

CD
CD

o

~

C

(J

CD4066BM/CD4066BC quad bilateral switch

general description
The CD4066BM/CD4066BC is a quad bilateral switch
intended for the transmission or mUltiplexing of analog
or digital signals. It is pin·for·pin compatible with
CD4016BM/CD4016BC, but has a much lower "ON"
resistance, and "ON" resistance is relatively constant
over the input·signal range.

•

Extremely low "OFF" switch leakage
0.1 nA typ
@ VDD - VSS = 1Oy,
TA = 25°C

•

Extremely high control input
impedance

•

features

•

Low crosstalk between switches
-50 dB typ
@ fis = 0.9 MHz, R L = 1 kn
40 MHz typ
Frequency response, switch "ON"

3V to 15V

•
•
•

Wide supply voltage range
High noise immunity
Wide range of digital and
analog switching

•
•

Bon typ
"ON" resistance for 15V operation
Matched "ON" resistance over
ARON = 5n typ
15V signal input
"ON" resistance flat over peak-to-peak signal range

•
•
•

1012n typ

applications

0.45 VDD typ

•

±7.5 VPEAK

•
•
•
•

High "ON"/"OFF" output voltage ratio
65 dB typ
@ fis = 10 kHz, R L = 10 kn
High degree of linearity
< 0.4% distortion typ
@ fis = 1 kHz, Vis = 5 Vp-p;
VDD - VSS = 10V, RL = 10 kn

Analog signal switching/multiplexing
• Signal gating
• Squelch control
• Chopper
• Modulator/Demodulator
• Commutating switch
Digital sign'al switching/multiplexing
CMOS logic implementation
Analog·to-digital/digital-to·analog conversion
Digital control of frequency, impedance, phase,
and analog-signal gain

schematic and connection diagrams
Dual-I n·Line Package

IN/OUT

IN/OUT

OUT/IN
IN/OUT

IN/OUT
CONTROL--i>

OUT/IN
CONTROL C

OUT/IN

vss

IN/OUT

TOPVIEW

2-150

(")

absolute maximum ratings

operating conditions

C

(Notes 1 and 2)

(Note 2)

-o.5V to +18V
VDD Supply Voltage
VIN Input Voltage
-o.5V to VDD + 0.5V
TS Storage Temperature Range
-65°C to +150°C
PD Package Dissipation
500mW
T L Lead Temperature (Soldering. 10 seconds)
300°C

VDD Supply Voltage
VIN Input Voltage
T A Operating Temperature Range
CD4066BM
CD4066BC

o
en
en

~

3V to 15V
OV to VDD
-55°C to +125°C
-40° C to +85° C

OJ

~

.......
(")

C

~

o

en
en
OJ

(")

dc electrical characteristics

CD4066BM (Note 2)
-55°C

PARAMETER

CONDITIONS
MIN

IDD

Quiescent Device Current

MAX

125°C

25°C
MIN

TVP

UNITS
MAX

MIN

MAX

VDD

0.25

0.01

0.25

7.5

/lA

VDD

0.5

0.01

0.5

15

/lA

1.0

0.01

1.0

30

/lA

= 5V
= 10V
VDD = 15V

SIGNAL INPUTS AND OUTPUTS
RON

6RON

"ON" Resistance

RL

= 10 kn

Vc

= VDD

Vis
-7.5V to +7.5V

15V

OV

OV to 15V

5V

-5V

-5V to +5V

10V

OV

OV to 10V

2.5V

-2.5V

-2.5V to +2.5V

5V

OV

OV to 5V

7.5V.

VSS
-7.5V

Vis
-7.5V to +7.5V

15V

OV

OV to 15V

5V

-5V

-5V to +5V

10V

OV

OV to 10V

RL

Between Any 2 of 4

Vc ~ VDD

Input or Output Leakage

VDD
7.5V

Switch "OFF"

220

80

280

320

n

400

120

500

550

n

3000

270

5000

5500

n

= 10 kS2

6"ON" Resistance
Switches

IOFF

7.5V

VSS
":'7.5V

Vc = VSS
-7.5V
-5V

5V

5

n

10

n

Vis
±7.5V

Vas
OV

±50

±0.1

±50

±500

nA

±5V

OV

±50

±0.1

±50

±500

nA

CONTROL INPUTS
VIL

Low Level Input Voltage

= VDD. Vas = VSS. lis ~ 10 /lA
= 5V
VDD = 10V
VDD = 15V
Vis

VIH

liN

High Level Input Voltage

Input Current

V

1.5

2.25

1.5

1.5

3.0

4.5

3.0

3.0

V

4.0

6.75

4.0

4.0

V

VDD

3.5

2.75

3.5

VDD

7.0

5.5

7.0

3.5
'7.0

V

VDD

= 5V
= 10V
VDD = 15V

8.25

11.0

VDD - VSS
VDD ~ Vis

2: VSS

VDD ~ Vc

>- VSS

±10-5

±0.1

= 15V

11.0

11.0

±1.0

±0.1

V
V
/lA

~

dc electrical characteristics

CD4066BC (Note 2)
-40°C

PARAMETER

CONDITIONS

MIN

I

IDD

Quiescent Device Current

85°C

25°C
MIN

TVP

MAX

MIN

MAX

UNITS

VDD ~ 5V

1.0

0.01

1.0

7.5

/lA

= 10V
VDD = 15V

2.0

0.01

2.0

15

/lA

4.0

0.01

4.0

30

/lA

VDD

.

MAX

2·151

(.)

co

CD
CD

dc electrical characteristics

o

~

PARAMETER

(.)

SIGNAL INPUTS AND OUTPUTS

c

.........

~

RON

"ON" Resistance

(Continued) CD4066BC (Note 2)

RL=10kn
VC= VDD
7.5V

CO
CD
CD

VSS
-7.5V

Vis
-7.5V to +7.5V

15V

OV

OV to 15V

5V

-5V

-5V to +5V

10V

OV

OV to 10V

2.5V

-2.5V

-2.5V to +2.5V

5V

OV

OV to 5V

VSS
-7.5V

Vis
-7.5V to +7.5V

15V

OV

OV to 15V

5V

-5V

-EN to +5V

10V

OV

OV to 10V

VOD
7.5V

Vc = VSS

o

~

c(.)
6RON

6"ON" Resistance

RL = 10 kn

Between Any 2 of 4

Vc = VDD
7.5V

Switches

IOFF

UNITS

CONDITIONS

Input or Output Leakage
Switch "OFF"

5V

250

80

280

300

n

450

120

500

520

n

3500

270

5000

5200

n

5

n

10

n

-7.5V

Vis
±7.5V

Vos
OV

±50

±0.1

±50

±200

nA

-5V

±5V

OV

±50

±0.1

±50

±200

nA

,V

CONTROL INPUTS
VIL

Low Level Input Voltage

Vis

=

VOO, Vos

= VSS,

lis:::; 10 IJ.A

= 5V
VDD = 10V
VDD = 15V

1.5

2.25

1.5

1.5

3.0

4.5

3.0

3.0

V

4.0

6.75

4.0

4.0

V
V

VDD

VIH

High Level Input Voltage

VOD
VDD
VDD

liN

Input Current

= 5V
= 10V
= 15V

VDD - VSS

3.5

2.75

3.5

3.5

7.0

5.5

7.0

7.0

V

11.0

8.25

11.0

11.0

V

= 15V

±0.3

±10- 5

±0.3

±1.0

IJ.A

VDD::::: Vis::::: VSS
VDD::::: VC::::: VSS

ac electrical characteristics

T A = 25°C, tr = tf = 20 ns and VSS = OV unless otherwise specified
TYP

MAX

VDD = 5V

25

55

ns

= 10V
VDD = 15V

15

35

ns

10

25

ns

PARAMETER
tPHL, tpLH

CONDITIONS

Propagation Delay Time Signal

Vc

Input to Signal Output

= VDD,

CL

MIN

= 50 pF, (Figure

1)

VDD

tPZH, tpZL

tpHZ, tpLZ

UNITS

= 10 kn, CL = 50 pF, (Figures 2

Propagation Delay Time Control

RL

Input to Signal Output High

and ;1)

Impedance to Logical Level

VDD

90

180

ns

VDD

40

80

ns

30

60

ns

= 5V
= 10V
VDD = 15V
= 10 kn, CL = 5 pF,

Propagation Delay Time Control

RL

Input to Signal Output Logical

and 3)

Level to High Impedance

VDD

= 5V
= 10V
VDD = 15V

90

180

ns

VDD

60

120

ns

55

110

ns

= VDD = 5V, VSS = -5V,
RL = 10 kn, Vis = 5 Vp-p, f =

0.4

%

40

MHz

Sine Wave Distortion

(Figures 2

Vc

1 kHz,

(Figure 4)

= VDD

Frequency Response-Switch

Vc

"ON" (Frequency at -3 dB)

RL = 1 H2, Vis

= -5V,
= 5 Vp-p,

= 5V, VSS

20 L0910 VoslVis = -3 dB, (Figure 4)

2-152

n
ac electrical characteristics
T A = 25°C. tr

=

tf

=

c

(Continued)

~

o
en
en

20 ns and VSS = OV unless otherwise specified
CONDITIONS

PARAMETER
Feedthrough - Switch "OFF"

Voo

(Frequency at -50 dB)

RL

TYP

MIN

= 5V, Vc = VSS = -5V,

MAX

UNITS
MHz

1.25

c

= VC(1) = 5V; VSS = VC(2) = -5V,
R L = 1 kn, Vis(A) = 5 Vp·p, 20 Lo91O'
Vos(2)Nis(1) = -50 dB,

MHz

0.9

Voo

Switch (Frequency at -50 dB)

VOO

Signal Output

RIN

= 10V,

to

= 10 kn,
= 1 kn, VCC = 10V Square Wave.
RL

400

mVp·p

(Figure 6)

=I

kn. CL = 50 pF, (Figure 7)

Maximum Control Input

RL

Frequency (I at Vos ,;

= 5V
VOO = 10V
VOO = 15V
VOO

1/2 VOO p. p )

6.0

MHz

8.0

MHz

8.5

MHz

8

pF

Signal Output Capacitance

8

pF

Cios

Feedthrough Capacitance

0.5

CIN

Control I nput Capacitance

5

Signal Input Capacitance

Cis
COS

pF
7.5

pF

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not
meant to imply that the devices should be operated at these limits. The tables of "Recommended Operating Conditions" and "Electrical
Characteristics" provide conditions for actual device operation.
Note 2: VSS = OV unless otherwise specified.
Note 3: These devices should not be connected to circuits with the power "ON".
Note 4: In all cases. there is approximately 5 pF of probe and jig capacitance on the output; however. this capacitance is included in
CL wherever it is specified.

ac test circuits and switching time waveforms
Vee

vee~r90%
'I

v's

50%
10%

OV

Vee
Ves

-

~'PLH

~'PHL

/50%

OV----.J
FIGURE 1. tpHL. tpLH Propagation Delay Time Signal Input to Signal Output

tpZH
Vee

Voe

Vc

10k

':'

Vc
ov

Ves
RL

ov
VOH

VeH
Vos

Vos
OV

OV

':'

FIGURE 2. tpZH. tpHZ Propagati~n Delay Time Control to Signal Output
tpZL

tpLZ

vee

Vc

voe

RL

Vc

10k

Voo
Vc

OV
V,s·OV

':'

OV

Vos

':'

J

CL

Voe

Vee
Vos

Vos
vOL

FIGURE 3. tPZL. tpLZ Propagation Delay Time Control to Signal Output

2·153

~

o

en
en

(Figure 5)

Crosstalk: Control Input to

.........

n

= 1 kn, Vis = 5 Vp·p, 20 Lo91O,
= -50 dB, (Figure 4)

VosNis
Crosstalk Between Any Two

to

s:

VOL

n

ac test circuits and switching time waveforms

(Continued)

E

L'\

25V_

VIS

1

nv

~

-2.5V--t---···-·-~----

I

\J
"-./

1/1----

-5V

Vc

= VOO for distortion

Vc

= VSS for·feedthrough test

and frequency response tests

FIGURE 4. Sine Wave Distortion, Frequency Response and Feedthrough

VC(1) = VOO - - ' - - - - ,

INIOUT

S~I~~H4ES OUT/INt-~~-VOS(1)
VSS

-5V

5V
VC(2) = VSS - - - - - - ,

Voo
VIS(2) = OV

IN/OUT

S~I~~H4ES OUT/INt-~'--VOS(2)

-5V

FIGURE 5. Crosstalk Between Any Two Switches

10V

VC----.......,

VOO---·

IN/OUT

S~I~~~ES

OUT/IN I--~'-- Vas

VSS

RIN

lk
Vas

-----'l'v-F=

FIGURE 6. Crosstalk: Control Input to Signal Output

VC-----,

IN/OUT S~I~~:ES OUT/IN t - -....---~.-- Vas
Vss

T

CL
50

PF
Vas

FIGURE 7. Maximum Control Input Frequency

2·154

t
t

CROSSTALK

o

typical performance characteristics

"ON" Resistance as a Function
of Temperature for
Voe - VSS = 15V

"ON" Resistance vs Signal
Voltage for T A = 25°C

-

~

400 r-T-'-T"""T""--T"""T""--T"""T...,---rr...,---,

400

300

z

~

250

~

200

~

150

z
z

g

u

u

~ 250

VOO - VSS = 5V;

I,

Ii

100

~

100

UJ..Hi.

~

50
-4

-2

0

-8

2

300

300

200
150

~
TA = +125'C

~I=~

100

f--1i H:

50

0

"ON" Resistance as a Function
of Temperature for
'
Vee - VSS = 5V
400

~

-2

"ON" Resistance as a Function
of Temperature for
Vee - VSS = 10V
~ 350

~

-4

SIGNAL VOLTAGE (VIS) (V)

400

250

-6

SIGNAL VOL TAGE (VIS) (V)

350

z
~

TA=+~

50 I-=!'
,
o TA = -55C

VOO - VSS = 15V
-6

200 H-I-H-+-H-+-H-+-+-+-+-+-I

~1501~

~O~=~O~

II

-8

~

300 H-I-H-+-H-+-H-+-+-+-+-+-I

II n

I

u

L,;

~~

1--"
v1--\'1

TA = -55 C

150

::t:

u

-6

-4

fl
1111
IIV

J

1111

TA = +25'C

'IT I=IJ;lc
I

i III

11111

50

11111

o
-8

-2

TA = +125 C

~
1/11

100

o
-8

200

~

,IIII.~

vl-'

250

~

z
z
«

-6

-4 -2
SUPPL Y VOLTAGE (VIS) (V)

SIGNAL VOLTAGE (VIS) (V)

special considerations
avoid drawing VOO current when switch current flows
into terminals 1, 4, 8 or 11, the voltage drop across the
bidirectional switch must not exceedO.6V at T A:::; 25°C,
or OAV at T A > 25°C (calculated from RON" values
shown).

In applications where separate power sources are used
to drive VOO and the signal input, the V DO current
capability should exceed VOO/RL (RL = effective
external load of the 4 C04066BM/C04066BC bilateral
switches). This provision avoids any permanent current
flow or clamp action on the VOO supply when power is
applied or removed from C04066BM/C04066BC.

No VOO current will flow through RL if the swi.tch
current flows into terminals 2,3,9 or 10.

In certain applications, the external load·resistor current
may include both VOO and signal-line components. To

2-155

o
en
en
OJ

s:

~ 350

350

c.;a.

........

o
c.;a.

o
en
en
OJ
o

CD4069M/CD4069C inverter ·circuits
general description
The CD40698 consists of six inverter circuits and is
manufactured using complementary MOS (CMOS)
to achieve wide power supply operating range, low
power consumption, high noise immunity and symmetric controlled rise and fall times.

All inputs are protected from damage due to static
discharge by diode clamps to VDD and VSS.

fea'tures
3V to 15V

• Wide supply voltage range
This device is intended for all general purpose inverter
applications where the special characteristics of the
MM74C901, MM74C903, MM74C907 and CD4049A.
Hex Inverter/Buffers are not required. In those applications requiring larger noise immunity the MM74C14 or
MM74C914 Hex Schmitt Trigger is suggested.

0.45 VDD typ
fan out of 2
driving 74L
or 1 driving
74LS

•

High noise immunity

•

Low power
TTL compatibility .

•

Equivalent to MM54C04/MM74C04

schematic and connection diagrams
Dual-I n-Line Package
VDD

........_a

r------~--

VIN

o--.JVV'v-....-

....

14

VDD

13

12

11

10

VOUT

L . - - - - -........-o Vss
vss
TOP VIEW

. ac test circuit and switching time waveforms

VDD.---+-ir-__-......,~
INPUT

Vss
VDD----::~

OUTPUT

Vss ----+-.~~---~
I,

2-156

=If =20 ns

(")

absolute maximum ratings

recommended operating conditions

C

(Notes 1 and 2)

(Note 2)

o0)

Voo de Supply Voltage
-{J.5 to +18 VOC
VIN Input Voltage
-{J.5 to VOO +0.5 VOC
TS Storage Temperature Range
-65°C to +150°C
Po Pae~age Dissipation
TL Lead Temperature (Soldering, 10 seconds)

Voo dc Supply Voltage
VIN Input Voltage
T A Operating Temperature Range
C04069M
C04069C

~

CD
3 to 15 VOC
Oto VOO VOC
-55°C to' +126°C
-40° C to +85°C

s:

........
(")

C

~

o0)
CD
(")

dc electrical characteristics
CD4069M

(Note 2)
-55°C

PARAMETER
IDD

VOL

VOH

Quiescent Device Current

Low Level Output Voltage

High Level Output Voltage

CONDITIONS

Low Level Input Voltage

High Level Input Voltage

IOL

IOH

liN

High Level Output Current

Input Current

TYP

MAX

MIN

MAX

UNITS
pA

0.25

0.25

7.5

0.5

0.5

15

pA

VDD = 15V

1.0

1.0

30

pA

IIOI

5,0

VOO"15V

~

:""

In

'~U,

IIII
I'J.L

YlIJorull"
10

40
3D

z

0

;::
~

i

(")

20

-50 -25 0 25 50 75 100 125
INPUT FREQUENCY (Hz)

50

20

ISO

, I
5jE Ai TEi T ciRC,IT

oS
w

:;

;::

,/

>-

g

.......r-'

_ CL =50 pF

--

-p..-<115P~

--I-"'"

AMBIENT TEMPERATURE (OC)

Propagation Dalay Time
vs Load Capacitance '

V~O .'10V'

.II TA=25 C _
r-VOO =3V :1TSEEACTESTCIRCUIT
/
0

Joci=:~

/

100

z

i-'11111

0

~

50

I

20

i

10

VOO'~

..." ......

~'L

~;I~V

,I

~

-50 -25 0

20

25 50 75 100 125

50

,I ,I ,I

100

CL -LOAD CAPACITANCE (pF)

AMBIENT TEMPERATURE (OC)

2·159

(")

C

(D

40

11111

Propagation Delay vs
Ambient Temperature

g

i

,,:::fm\

(D

s:
-,......
0')

15

VIN (V)

->-

;::
~

~,L' IS';;

0')

0

0

',U

0

~

60

z

.Y1111

1111'

1111
111

VOO" 5V
SEe AC TEST CIRCUIT

80

>-

g

S,~F

VOO" 5V

5,0

!

, 111111 Yl JJruK

~CI''''F

I-

"""

~

Propagation Delay vs
Ambient Temperatura

150

(.)

m
o
.....
o
~

c

(.)
.........

~

m
o

S

CD4070BM/CD4070BC quad 2-input EXCLUSIVE-OR gate

~

c

(.)

general description

features

Employing complementary MOS (CMOS) transistors
to achieve wide power supply operating range, low
power consumption and high noise margin this gate
provides basic functions used in the implementation of
digital integrated circuit systems. The Nand P-channel
enhancement mode transistors provide a symmetrical
circuit with output swing essentially equal to the supply
voltage. No dc power other than that caused by leakage
current is consumed during static condition. All inputs
are protected from damage due to static discharge by
diode clamps to VDD and VSS.

•
•

Wide supply voltage range
High noise immunity

•

Low power
TTL compatibility

•
•

Pin compatible to CD4030A
Equivalent to MM54C86/MM74C86 and MC14507B

3V to 15V
0.45 VDD typ
fan out of 2
driving 74L
or 1 driving
74LS

connection diagram
Dual·1 n·Line Package
voo

L=E0F

B'

J=A0B

vss

K=c0o

typical performance characteristics

truth table

Propagation Delay Time
vs Load Capacitance
150

-:;g

y

TA =25"C

Y1"

t...-

;::
>

g

100

INPUTS

voo = 5.0V

....

:2
0

;::
~

i

-f- f-f- voo = 10V
50

>--f-'"'
..1-1---

L..-~

L..-~

I---

Voo=15V f-

I

I I

~

50

100

150

LOAO CAPACITANCE (pF)

2·160

OUTPUTS

A

B

Y

L

L

L

L

H

H

H

L

H

H

H

L

absolute maximum ratings

recommended operating conditions

(Notes 1 and 2)

(Note 2)

Voo DC Supply Voltage
-

V'~T

I-

~

f-----r-r--+t-

J

I-

:::l

5V

10

o

v'~rvo

>

VI -INPUT VOLTAGE (V)
BOTH INPUTS

FIGURE 1. Typical Transfer
Characteristics

FIGURE 2. Typical Transfer
Characteristics

C04071B

TIA

VOO = 15V

=25

,~

400

~
C(

'"

>

I-

10

=50 pF

25C

- - -___-+--1-

v'~T-- vo-

I-

:::l

VOO' 5V

o

I

o

5

f~1--+-+--,

'vssi'

'I'D

-

o
10

15

20

VI -INPUT VOLTAGE (V)
ONE INPUT ONLY

FIGURE 3. ~ypical Transfer
Characteristics

C040B1B
TA = 25°C
CL = 50 pF

407 1
TA = 25'C
300 f - - - 4 - - - + - - CL

=

I

....-----,.----,---c'bc-- - B----'

;:::

C

t

Voo

VOO'10V

o

20

VI -ltJPUT VOLTAGE (V)
ONE INPUT ONLY

I

'15

I-

I"
o "--__...........--I.iL-_L-_...J
15

C040718
T

VOO'15V

C(

>

10

20

~

:::l

vS~~~o_

Voo" 5V

I

o

20

15

10h -

VOO'10V
10

:::l

==1=:-~:~_'"...L-f,1'_0---,voo

I

o

>

'"

I-

~­

VOO'10V

>

I-

.J

20

C040818

VOO'15V Tt'25 C
15 J----+-----rr--oI-----l

VOO'15V

_

~]

C(

I-

o
>

"'-w

5~

I:::l

I-

Ci:>;::~

o

_~ ~
~

:::l

I

o
>

10

15

VI -INPUT VOLTAGE (V)
BOHIINPUTS '

FIGURE 4. Typical Transfer

20

\

200 J---\-+--+-----'J-------1
\

"':2
!::! >=

~~

I~

100 J----4.:---+----iJ-------1
I'---..?HL & tPLH

0'-----'----'---'------'
10
20
o
15
VOO -SUPPLY VOLTAGE (V)

FIGURE S

Character ist ics

2-167'

200

~ clOD

pHL
f--_-4I""t_ _ + -_ _J--_--l

tPI~-""'~====_=

0'------'----'---'------'
5

10

15

VOO - SUPPL Y VOLTAGE (V)

I

FIGURE 6

20

(.)

~

typical performance characteristics (can't)

CX)

o

'lit

C

(.)
........

~

CQ

Cii
o
'lit

C

'"

IoU

"'~
x ...

~5:

S

.....

'"0

o

.....

IoU

0

(.)

5-

cJ

",a:
~Q.

m
o

200

200

'"

I

0

IoU

~]
",IoU

I

150

"'::;;

i:i=

0>

0",

.....
.....

>

<0:
"-

1

0

.....

100

0

~~
........
10
",a:
g.0-

50

~g:

VDD = 15V

'"

~i=

j::
<0:

"-",

VDD = 10V

50

~~

100

::3 ~
_

150

~~

~ ~
=:0

100

<0:

~ ~

CD40718
TA = 25°C·

~~

150

i=

"-

200

.~ !

CD40718
TA = 25 C

~]

50

0

~

0

'lit

25

. 75

50

100

25

75

50

C(- LOAD CAPACITANCE (pF)

FIGURE 7

FIGURE 8

C

(.)

50

25

100

CL - LOAD CAPACITANCE (pF)

75

100

CL - LOAD CAPACITANCE (pF)

FIGURE9

........

~

m
~

o

-d'

C

(.)
200
5:~
~:;

6~

2.0
CD40818
TA = 25"C

150

u

:

::1:

100

;3

<0: Z

~ E

..... <0:

~i

50

0.5

~

co.

0

25

50

I

100

75

o

'"

co.
~

CL -LOAD CAPACITANCE (pF)

2

4

170

~

I'\..

a:
0

190

:;

>=
~

CD40718
C040818 1--'(See Application Note AN·90
Propagation Delay)

\

0

~
.....
0

> .....
I'"

1.0

"'

~

\

c::;

:3
~

1.5

z
~

":- .....
'" >
~

tr = tf= 20 ns
TA = 25°C

]

6

ttitt-

CD40718
CD40818

150

/"

130
110

Y

90

<0:
u

70

~I

50

./

..,..,.-

V
./' ~
Y ..........::.

30

.~ ~

8 10 12 14 16 18 20

....-

50

25

75

100

CL -LOAD CAPACITANCE (pF)

VOD - POWER SUPPLY (V)

FIGURE 10

L

FIGURE 11

FIGURE 12

.; ~

ct

38
34

Z

30

§

26

.s.....
~
;;;

22
18

;3

14

~
I

10
6

2

o

ct

.s

I

VD~=~5V

/'r"

cr:

!I

:::>
0

_r- -VDO=10V

<0:

/1/

'rl~;;;;VOD=5Jo

2

4

6

~

I-- C040718

I

:r

CO 408l8
l

'"

8 10 12 14 16 18 20
VOUT (V)

~CCI='5~~ ~
/

10
14
18

-

-VCC=10V

~'/
I

V

If

/

22

I

.24

V

28

l,..oo'~

32
36

VCC=15V
20 18 16 14 12 10

8

6

4

2

0

VCC - VOUT (V)

FIGURE 13

FIGURE 14

/

2-168

CD4073BM/CD4073BCdouble buffered triple 3-input NAND gate
CD4075BM/CD4075BC double buffered triple 3-input NOR gate

general description

features

These triple gates are monolithic complementary MOS
(CMOS) integrated circuits constructed with N- and
P-channel enhancement mode transistors. They have
equal source and sink current capabilities and conform
to standard B series output drive. The devices also have
buffered outputs which improve transfer characteristics
by providing very high gain. All inputs are protected
against static discharge with diodes to Voo and Vss.

• Wide supply voltage range

3.0V to 15V

• High noise immunity

0.45 Voo typ
fan out of
2 driving 74L
o~ 1 driving 74LS

• Low power
TTL compatibility
• 5 V - 10 V - 15 V parametric ratings
• Symmetrical output characteristics

• Maximum input leakage l}1A at 15 V over full
temperature range

connection diagrams

Voo

Voo

Vss
CD4075B Triple 3·lnput OR Gate

CD4073 Triple 3·lnput AND Gate

TOP VIEW

TOP VIEW

2·169

absolute maximum ratings
Voo
VIN
Ts
Po
TL

recommended operating conditions

(Notes 1 and 2)

(Note 2)
.
Voo DC Supply Voltage
+5 VOC to +15 Voc
V 1N Input Voltage
OVoc to Voo Voc
T A Operating Temperature Range
-55°C to +125°C
CD4073BM/CD4075BM
-40°C to +85°C
CD4073BC/CD4075BC

DC Supply Voltage
-0.5Vocto+18VoC
Input Voltage
-0.5VoctoVoo+0.5VoC
Storage Temperature Range
_65°C to +150°C
Package Dissipation
500 mW
Lead Temperature (soldering, 10 seconds) 300°C

dc electrical characteristics-

CD4073BM/CD4075BM (Note 2)

100

CONDITIONS

Quiescent Device Current

MIN

Voo = 5 V
Voo = 10V
Voo= 15V

VOL Low Level Output Voltage V OO =5V}
Voo = 10V 1101 < 1 JiA
Voo= 15V

V ,L

Low Level Input Voltage

0.25
0.5
1.0

0.004
0.005
0.006'

0.25
0.5
1.0

7.5
15
30

0.05
O.OS
0.05

o
o
o

0.05
0.05
0.05

0.05
0.05
0.05

4.95
9.95
14.95

MAX

2

1.5
3.0
4.0

4

6

UNITS
JiA
JiA
JiA
V
V
V

4.95
9.95
14.95

5
10
15

1.5
3.0
4.0

V 00 = 5 V, Va = 0.5 V }
Voo = 10V, Va = 1.0V 1101 < 1 JiA
Voo = 15V, Va = 1.5V

MIN

V
V
V
V
V
V

1.5
3.0
4.0

3.5
7.0
11.0

3
6
9

3.5
7.0
11.0

V
V
V

Low Level Output Current Voo = 5 V, Va = 0.4 V
Voo = 10V, Va = 0.5V
Voo = 15V, Va = 1.5V

0.64
1.6
4.2

0.51
1.3

'0.88

0.36
0.90
2.4

rnA
rnA
rnA

High Level Output Current Voo=5V, Vo=4.6V
Voo = 10V, Va = 9.5V
Voo= 15V, Vo= 13.5V

-0.64
-1.6
-4.2

High Level Input Voltage

10L

liN

MAX

MIN

3.5
7.0
11.0 .

V ,H

10H

TYP

MAX

4.95
9.95
14.95

V OH High Level Output Voltage V OO=5V}
Voo=10V 1I011 Impedance State

tPZH, tPZL Propagation Delay From Output
Disable to Logical "1" Level or
Logical

"a" level (From High Imped·

VDD

= 5V. 'Rl

=

1.0k

170

VDD = 10V. Rl 1.0k

70

140

. ns

VDO=15V.RL 1.Ok

56

·115

ns

VDD = 5V,

170

340

ns

VDD = 10V, RL = 1.Ok

70

140

ns

VDD = 15V, RL = 1.0k

56

115

ns

VDO = 5V

100

200

ns

VDD = 10V

50

100

ns

VDD = 15V

40

80

ns

RL = 1.0k

ance State)
tTHL or

Transition Time

tTLH

fCl

rv1Jximum Clock Frequency

VDD = 5V
VDD

= 10V

tWH

tRCL. tFCL Maximum Clock Rise and Fall Time

CIN

CPD
COUT

4.0

MHz

12.0

MHz

8.75

15.0

MHz

VDD = 5V

150

ns

VDD = 10V

70

ns

VDO = 15V

56

ns

VDD = 15V
Minimum C'lear Pulse Width

3.0
7.0

VDD = 5V

10

VDD = 10V

5

/lS

VDD=15V

2

JJS

JJs

Data Inputs (A, B. C, D)

3

7.5

pF

Other Inputs

6

15

pF

Power Dissipation Capacity

All Four Flip·Flops. (Note 3)

100

TRI-STATE® Output Capacitonce

Any Output

15

pF

Average Input Capacitance

pF

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply
that the devices should be operated at these limits. The table of "Recommended Operating Conditions" and "Electrical Characteristics" provides
conditions for actual device operation.
Note 2: VSS = OV unless otherwise specified.
Note 3: CPD determines the no load ac power consumption of any CMOS device. For complete explanation. see 54C/74C Family Characteristics
applicdtion note, AN-gO.

2·175

r,;..

:'

ac test circuits and switching time waveforms
tpLZ and

tpHZ and tpZH

~PZL

Voo
INPUT-"Q::

OISABLE

1.

~

INPUT

DISABLE

--Q--±-

loOk

T

"

OUTPUT

CL

tpHZ

,::_J:.o:, .

VOD------

VOO--------~r-------------

DISABLE

DISABLE

OV

L

OV

tpZH

1--_
_---

10_%.J~

VOL _______________

tpZL
VOO-----------~

"~'''':~v.'''---

DISABLE
OV

VOO

OUTPUT

OUTPUT

10%

~:"\'

VOL------------------~~·------

CLEAR

I~~~~ ---+---------.,--.,--1----.....

CLOCK

IPLZ

I

OUTPUT

'''~,

OV-----

------~

VOD

90%

OUTPUT

/50%

---+---------.1

OU~~~ ----~t..1

2-176

(")

C

~

o

CO

CD

to

S
........
(")

CD4089BM/CD4089BC binary rate multiplier
CD4527BM/CD4527BC BCD rate multiplier

C

~

o

CO

CD

to

general description

51

features

The CD4089B is a 4·bit binary rate multiplier that
'provides an output pulse rate which is the input clock
pulse rate multiplied by 1/16 times the binary input
number. For. example, if 5 is the binary input number,
there will be 5 output pulses for every 16 clock pulses.
The CD4527B is a 4·bit BCD rate multiplier that pro·
vides an output pulse rate which is the input clock pulse
rate multiplied by 1/10 times the BCD input number.
For example, if 5 is the BCD input number, there will
be 5 output pulses for every 10 clock pulses.
These devices may be used to perform arithmetic opera·
tions including multiplication and division, AID and DIA
conversion and frequency division.

•

Wide supply voltage range

•

High noise immunity

•

Low power TTL
compatibility

3V to 15V

'D.45 VDD typ
fan out of 2
driving 74L
or 1 driving 74LS

•

STROBE for inhibiting and enal?ling outputs

C

•

INHIBIT IN and CASCADE inputs for cascade opera·
tion

N

•

Complementary output

•
•

CLEAR and SET inputs
"g" or "15" output and INHIBIT OUT output

16 VDD

C

C

B

D

A
CLEAR

OUT

CASCADE

OUT

CASCADE

OUT

INHIBIT IN

OUT

INHIBIT IN

INHIBIT OUT

INHIBIT OUT

STROBE

VSS

CLOCK

STROBE
CLOCK

VSS

TOP VIEW

TOP VIEW

2·177

(")
~

U1

to

"g"

SET TO "g"

........

-...J

CD4527B
Dual·ln-Line and Flat Package

CLEAR

S

Internally synchronous 4-bit counter
Output clocked on the negative·going edge of clock

"15"

SET TO "15"

~

to

•

CD4089B
Dual.ln.Line and Flat Package

A

~

U1

•

connection diagrams

D

(")

c

(")

(.)

co
.....

absolute maximum ratings

recommend ed operating conditions

N

(Notes 1 and 2)

(Note 2)

~

-0.5 to +18V
VDD Supply Voltage
VIN Input Voltage
-0.5 to VDD + 0.5V
TS Storage Temperature Range
--65°C to :+-150°C
Po Package Dissipation
500mW
300°C
TL Lead Temperature (Soldering, 10 seconds)

VDD Supply Voltage
VIN Input Voltage
T A Operating Temperature Range
CD4089BM, CD4527BM
CD4089BC,CD4527BC

I.t)

C

(.)

"-

:?!
co
.....

N

dc electrical characteristics

3 to 15 V
Oto VDDV
-55°C to +125°C
-40°C to +85°C

CD4089BM, CD4527BM (Note 2)

I.t)

~

-55°C

PARAMETER

C

CONDITIONS

MIN

(.)

ci
co

100

'CO

VOL

Quiescent Device Current

0')

o

Low Level Output Voltage

~

c

(.)

"-

:?!

VOH

High Level Output Voltage

25°C

MAX

MIN

TYP

125°C
MAX

MIN

MAX

UNITS

VOO = 5V

5

5

150

VOO = 10V

10

10

300

/lA

VOO = 15V

20

20

600

/lA

0,05

0.05

V

0.05

0.05

V

0.05

0.05

V

/lA

1101:::; l/lA
VOO = 5V

0.05

VOO = 10V

0.05

VOO = 15V

0.05

a
a
a

1101:::; l/lA
VOO = 5V

4.95

4.95

5

4.95

0')

VOO = 10V

9 ..95

9.95

10

9.95

V

CO

VOO = 15V

14.95

14.95

15

14.95

V

CO

o

~

VIL

Low Level Input Voltage

c

(.)
VIH

High Lev'el Input Voltage

1.5

1.5

1.5

VOO = 10V, Va = 1V or 9V

3.0

3.0

3.0

V

VOO = 15V, Va", 1.5V or 13.5V

4.0

·4.0

4.0

V

Voo = 5V,

VOO = 5V,

Vo = 0.5V or 4.5V

Vo = 0.5V or 4.5V

VOO = 10V, Va = lV or 9V

IOH

liN

Low Level Output Current

High Level Output Current

Input Current

.VOO = 5V,

Va = O.4V

3.5

3.5

V

7.0

7.0

7.0

V

11.0

11.0

0.64

0.51

VOL

VOH

Low Level Output Voltage

High Level Output Voltage

1.6

1.3

2.25

0.9

mA

3.4

8.8

2.4

mA

-0.64

-0.51

-0.88,

-0.36

mA

VOO = 10V, Va = 9.5V

-1.6

-1.3

-2.25

-0.9

mA

VOO= 15V, VO= 13.5V

-4.2

-3.4

-8.8

-2.4

VOO = 5V,

Va = 4.6V

VOO = 15V, VIN = OV

-10- 5

-0.1

-1.0

/lA

0.1

10-5

0.1

1.0

/lA

-40°C
CONDITIONS

MIN

IOL

High Level Input Voltage

Low Level Output Current

MIN

.TYP

MAX

MIN

MAX

UNITS

VOO = 5V

20

20

150

/lA

40

40

300

/lA

VOO = 15V

80

80

600

/lA

1101:::;1/lA
VOO = 5V

0,05

VOO = 10V

0.05

VOO = 15V

0.05

a
a
a

0.05

0.05

V

0.05

0.05

V

0.05

0.05

V

1101:::; l/lA
.-

4.95

4.95

5

4.95

V

9.95

9.95

10

9.95

V

14.95

14.95

15

14.95

VOO = 15V

VIH

85°C

25°C

MAX

VOO = 10V

VOO =5V .

Low Level Input Voltage

mA

-0.1

CD4089BC, CD4527BC (Note 2)

VOO = 10V

VIL

mA

4.2

.

Quiescent Oevice Current

V

0.36

VOO = 15V, Va = 1.5V

dc electrical characteristics

IDO

,11.0
0.88

VOO = 10V, Va = 0.5V

. VOO = 15V, VIN = 15V

PARAMETER

V

3.5

VOO = 15V, Va = 1.5V or 13.5V
IOL

V

Va = 0.5V or 4.5V

V

1.5

1.5

1.5

VOD= 10V, VO= lVor9V

3.0

3.0

3.0

V

VOO = 15V, Va = 1.5Vor 13.5V

4.0

4.0

4.0

V

VOO = 5V,

Von = 5V,

Vo = 0.5V or 4.5V

V

3.5

3.5

3.5

VOO = 10V, Va = lV or 9V

7.0

7.0

7.0

V

VOO= 15V, VO= 1.5Vor 13.5V

11.0

11.0

11.0

V

0.52

0.44

0.88

0.36

mA

VOO = 10V, Va = 0.5V

1.3

1.1

2.25

0.9

mA

VOo= 15V, VO= 1.5V

3.6

3.0

8.8

2.4

mA

VOO = 5V,

Vo = O.4V

V

2·178

(")

dc electrical characteristics

-40°C
PARAMETER
IOH

CONDITIONS

High Level'Output Current

VOO; 5V,

Va

VOO; 10V, Va
VOO
Input Current

liN

= 15V,

Va

Voo; 15V, VIN
VOO

C

(Continued) CD40S9BC, CD4527BC (Note 2)

= 15V,

VIN

MIN

= 4.6V
= 9.5V
= 13.5V

MAX

85°C
UNITS

MIN

TYP

-0.52

-0.44

-0.88

-0.36

mA

-1.3

-1.1

-2.2S

-0.9

mA

-3.6

= OV
=

~

25°C

-3.0
-0.3
0.3

15V

MAX

MIN

to

mA

.........
(")

-1.0

JJ.A

C

0.3

1.0

JJ.A

-2.4

tPLH, tpHL

tPLH, tPHL

to

CONDITIONS

Propagation Delay Time,

VOO; 5V

Clock to Out or Out

VOO

Propagation Delay Time,
Clock to EOUT

tPLH, tPHL

tPLH, tpHL

ns

VOO; lSV

60

120

ns

300

600

ns

.120

240

ns

75

150

ns

OJ
.........
(")

VOO

= 5V

VOO; 10V

= lSV

280

560

ns

100

200

ns

VOO; 15V

70

140

ns

C

Propagation Delay Time,

VOO

SOO

1100

ns

Set or Clear to Out or Out

VOO; 10V

200

400

ns

VOO; 15V

150

300

ns

U1
N
.......
OJ

Propagation Delay Time,

VOO; 5V

100

200

ns

Cascade to Out

VOO; 10V

50

100

ns

= 15V

35

70

ns

220

440

ns

85

170

ns

65

130

ns

100

200

ns

= 10V

50

100

ns.

VOO;15V

40

80

ns

250

500

ns
ns

= 5V

Propagation Delay Time,

VOO; 5V

Strobe to Out

VOO

Transition Time, All Outputs

Minimum Clock Pulse Width

= 10V
= 15V

VOO; 5V

VOO

= 5V

100

200

VOO

= 15V

70

140

VOO

2

1

VOO

= 5V
= 10V
= 15V

VOO

= SV

Minimum Set or Clear
Pulse Width

Set Removal Time

Inhibit In Set·Up Time

ns
MHz

S

2.5

MHz

7

3.5

MHz

5

JJ.s

VOO; 10V

1.S

f.lS

VOO; 15V

1.0

f.lS

VOO = 5V

15

JJ.s

= 10V
VOO = 15V
VOO = 5V
VOO = 10V
VOO = lSV
VOO = 5V
VOO = 10V
VOO = 15V

15

JJ.s

VOO

tSET·iJp

15

JJ.s

125

250

ns

50

100

ns

25

55

ns

0

ns

-20

0

ns

-10

0

ns

-45

VOO '" 5V
VOO = 10V

175

350

ns

60

120

ns

= 15V

45

90

ns

CI

Average Input Capacitance

Any Input

5

7.5

pF

CPO

Power Dissipation Capacitance

Per Package, (Note 3)

80

VOO

pF

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply
that the devices should be operated at t~ese limits. The table of "Recommended Operating Conditions" and "Electrical Characteristics" provides
conditions for actual device'operation.
Note 2: VSS

= OV

~

VDO; 5V

Maximum Clock Fall Time

tREM

.......

VOO; 10V

Maximum Clock Rise Time

tW(S,R)

~

U1
N

Propagation Delay Time,

VOO

If

(")

C

Clock to "9" or "15"

Maximum Clock Frequency

tr

ns

OJ

P

170

VOO; 10V

fCL

UNITS

3S0

VOO

tW(CL)

MAX

175

VOD
tTLH, tTHL

TYP

85

VOO
tPLH, tpHL

MIN

= 10V

VOO
tPLH, tpHL

~

0

co

ac electrical characteristics
PARAMETER

OJ

~

-0.3

-8.8
-10- 5
10- 5

MAX

0
CO

unless otherwise specified.

Note 3: CPO determines the no load ac power consumption of any CMOS device. For complete explanation, see 54C/74C Family Characteristics
application note, AN-90.

2-179

~

(")

truth tables
CD4089B
Binary Rate Multiplier
NUMBER OF PULSES OR
OUTPUT LOGIC LEVEL
(HOR L)

INPUTS

D

C

B

A

0
0
0
0
0
0
0
0

0
0
0
0
1
1
1
1
0

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X

1

O·

0

1
1
1
1
1
1
1
X
X
X
1
0

X

0
1
1
0
0
1
1
X
X'
X

X
'X

X
X

X
X

X

X

X

X

0
0
1
1
1
1
X
X

X

X

No. of
C':lock Pulses
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16

Inhln
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
00

Strobe
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0

Cascade

Clear

Set

0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0

Pin 6
Out

L

Pin 5

Out

Pin 7
Inh Out

Pin 1
"15"

H
1
2
3
4
5
6

1
1
1
1
1
1
1
1
1
1
1
1
1
1
7
7
1
1
8
8
1
1
1
1
9
9
10
10
1
1
11
11
1
1
12
12
1
1
13
13
1
1
14
14
1
1
15
15
1
1
Depends on internal state of counter
H
L
1
1
H
1
1
*
16
16
H
L
H
H
L
L
H
H
L
L
1
2
3
4
5
6

*Output same as the first 16 lines of this truth table (depending on values of A, B, C, D)

CD4527B
BCD Rate Multiplier
NUMBER OF PULSES OR
OUTPUT LOGIC LEVEL
(H OR L)

INPUTS

D

C

B

A

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0

0
1
0
1

X
X

X
X
X
X
X
X

X
1
0
X

0
1
1
0
0
1

1
X
X
X
X
X
X

No. of
Clock Pulses

X

10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10 .

X

10

0
1
0
1
0
1
0
1
0
1
0
1
X
X
X
X

Inhln

Strobe

Cascade

Clear

Set

0
0
0
·0

0
0
0
0

0
0
0
0
0
0
0
0
0
0

0
0
0
0

0
0
0
0

0
0

0

0
0
0
0
0
0
0
0

0

0

0

0
0
0
0
0
0
0

0
0
0
0
0
0

0

0
0

0
0
0
1
0
0
0

0
0
0

0

0
0

0

0
1
0
0

0
0
0
0
0
0
0
0
1
0,
0
0

0
0
0

0
0
1
1
0

*Output same as the first 16 lines of this truth table (depending on values of A, B, C, D)

2·180

0
0
0
0
0

0
0
0
0
0
0
0
0
0

0
1

Pin 6
Out

L

Pin 5

Out
H
1
2
3
4
5

Pin 7
Inh Out

Pin 1

"9"

1
1
1
1
1
2
1
1
3
1
1
4
1
1
1
1
5
6
6
1
1
1
7
7
1
1
8
8
1
1
1
9
9
1
1
8
8
1
1
9
9
1
1
8
8
1
1
9
9
1
1
8
8
1
1
9
9
Depends on internal state of counter
1
H
1
L
1
H
1
L
H
10
10
H
H
L
L
H
H
L
L

*

logic waveforms
CD4089B
Binary Rate Multiplier

CLOCK
OUTI~~~~)

___________________________________________________________________________

___________________________________
________________________ ___________________
______ ________ ________
______________
--DL......_________
~______~rl~_________

0001 __________________________~rl~

0010 __________~fl~

o0

1 1

o 1 00
o1 0

~rl~

~fl~

~rl~

~rl~

.J

1

o1

1 0

o1

1 1

1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1

1 1 0 0
1 1 0 1

1110

1111
INHIBIT OUT

CD4527B
BCD Rate Multiplier

CLOCK

OUT (0 C B A)
o0 0 0

o0

0 1

o0

1 0

00 1,1

o1

0 0

o1

1 0

o1

1 1

rl·

n

n
n----1l

n

1 0 0 0

1 0 0 1

LJ

INHIBIT OUT

2-181

logic diagrams

CD4089B
Binary Rate Multiplier

CLOCK

~

CLEAR 13

.

SYNCHRONOUS
HIT BINARY
COUNTER

SETTO"IS"~

"IS"

Voo = pin 16
VSS = pin 8

a.-_"",-~.

INHIBIT IN

Q,

---------------------J

..:1~11o--_ _ _ _

INHIBIT OUT

CD4527B
BCD Rate Multiplier
STROBE

CASCADE

SYNCHRONOUS
4 BIT DECADE
COUNTER

Voo = pin 16
VSS

= pin

8

I

o.--_~

fic--""'-~

::~,:"''''""'.

INHIBITIN~Io----------------------~
II

2-182

cascading packages
MOST SIGNIFICANT
DIGIT

LEAST SIGNIFICANT
D1GIT

OUT

CLOCK

II~H

OUT

001'

juF

OUT

CLOCK INH OUT

CASC
INH IN

"IS"

ST
CLEAR

SET

CLOCK o-+---------~

~ ~ ~)
256

/5 +
,-16
256

Two CD4089B's cascaded in the "add" mode with a pre,et number of 89

MOST SIGNIFICANT
OIGIT

LEAST SIGNIFICANT
DIGIT

our
,0
CLOCK

INH CUT

CAS~

INH I;J

"1S"

ST
CLH~R

CLOCK

S~T

0-+-----------'

Two CD4089B's cascaded in the "multiply" mode with a preset number of 98

MOST SiGNIFICANT
DIGIT

7
( 16

14
x16

~

98)
.
256

LEAST SIGNIFICANT
DIGIT

OUT

our
CLOCK

INH OUT

CASC
INH IN

"g"

ST
CLEAR

CLOCK

SET

0-..-----------'

Two CD4527B's cascaded in the ':add" mode with a preset number of 27
.
MOST SIGNIFICANT
DIGIT

(~

10

+'100

27 )
100

LEAST SIGNIFICANT
DIGIT

OUT

OUT
CLOCK

INH OUT

CASC
INH IN

"9"

ST
CLEAR

CLOCK

SET

0-+----------'

9
Two CD4527B's c(lscaded in the "multiply" mode with a preset number of 27 '(- 3 x 10
10

2-183

27 )
100

u

i~
u

........

~

a'.'I
M

~

CD4093BM/CD4093BC quad 2-input NAND Schmitt trigger

~

C
U

general description
The CD4093B consists of four Schmitt-trigger circl,lits.
Each circuit functions as a,2-input NAND gate with
Schmitt-trigger action on both inputs. The gate switches
at different points for positive and negative-going signals.
The difference between the positive (VT +) and the
negative voltage (VT-) is defined as hysteresis voltage
(VH)·

• No limit on input rise and fall time
• Standard B-series output drive
• Hysteresis voltage (any input) T A = 25°C
VH
Typical
VOO= 5V
VOO = 10V
VOO

All outputs have equal source and sink currents and
conform to standard B-series output drive (see Static
Electrical Characteristics).

15V
VH

applications

features

•
•
•
•
•

3V to 15V
• Wide supply voltage range
• Schmitt-trigger on each input with no external
components
• Noise immunity greater than 50%
• Equal source and sink currents

Wave and pulse shapers
High-noise-environment systems
Monostable multivibrators
Astable multivibrators
NANO logic

connection diagram
Dual-In-Line Package

voo

=

Guaranteed

M

Vss

2-184

=

1.5V

VH

= 2.2V

VH

=

=

2.7V

0.1 VOO

(")

absolute maximum ratings

recommended operating conditions

C

(Notes 1 and 2)

(Note 2)

o

DC Supply Voltage (VOO)
-0.5 to +18 VOC
Input Voltage (VI N)
-0.5 to VOO +0.5 VOC
Storage Temperature Range ITS)
-65°C to +150°C
Package Dissipation (PO)
Lead Temperature (Soldering, 10 seconds) (TL)

Voo de Supply Voltage
VIN Input Voltage
T A Operating Temperature Range
C04093BM
C04093BC

~

CD

3to15VOC
Oto VOO VOC
-55°C to +125°C
-40° C to +85° C

W
CO

s:
'"C
(")
~

o

CD
W

CO

dc electrical characteristics

PARAMETER
100

VOL

VOH

VT-

Quiescent Oevice Current

Low Level Output Voltage

High Level Output Voltage

Negative'Going Threshold Voltage
(Any Input)

CD4093BM

MIN

10H

liN

MIN

TVP

125 C
MAX

MIN

0.25

7.5

0.5

0.5

15.0

p.A

VOO=15V

1.0

1.0

30.0

p.A

VOO = 5V

0.05

0

0.05

0.05

V

VOO = 10V

0.05

0

0.05

0.05

V

VOO = 15V

0.05

0

0.05

0.05

V

VIN = VSS, 1101< lp.A
VOO = 5V

4.95

4.95

5

4.95

V

VOO = 10V

9.95

9.95

10

9.95

V

VOO = 15V

14.95

14.95

15

14.95

V

1101< lp.A
VOO = 5V, Vo = 4.5V

(Any Input)

VOO = 5V,

Vo = 0.5V

1.3

2.25

1.5

1.8

2.25

1.5

2.3

V

2.85

4.5

3.0

4.1

4.5

3.0

4.65

V

4.35

6.75

4.5

6.3

6.75

4.5

6.9

V

3.5

3.65

2.75

3.3

3.5

2.65

3.5

V

7.0

7.15

5.5

6.2

7.0

5.35

7.0

V

VOO = 15V, Vo = 1.5V

10.5

10.65

8.25

9.0

10.5

8.1

Hysteresis (VT+ - VT-)

VOD = SV

O.S

2.35

0.5

1.5

2.0

0.35

(Any Input)

VOO = 10V

1.0

4.30

1.0

2.2

4.0

VOO = 15V

1.5

6.30

1.5

2.7

6.0

Input Current

p.A

YIN = VOO, 110 1< lp.A

1101< lp.A

High Level Output Current

UNITS

0.25

Positive·Going Threshold Voltage

Low Level Output Current

MAX

VOO = 10V

VOO = 10V, Vo = lV

IOL

MAX

VDO = 5V

VOO = 15V, Vo = 13.5V

VH

u

2SoC

-55"C

CONDITIONS

-VOO = 10V, Vo = 9V

VT+

(")

(Note 2)

.VIN=VOO
VOO = 5V, Vo = OAV

0.64

0.51

0.88

VOO = 10V, VO= 0.5V

1.6

1.3

2.25

VOO = lSV, Vo = 1.SV

4.2

304

8.8

I

10.5

V

. 2.0

V

0.70

4.0

V

1.20

6.0

V

0.36

mA

0.9

mA

204

mA

,

VIN= VSS
VOO = 5V, Vo = 4.6V

-0.64

-0.88

-0.36

mA

VOO = 10V, Vo = 9.5V

-1.6

-1.3

-2.25

-0.9

mA

VOO = 15V, Vo = 13.5V

-4.2

-3.4

-8.8

-2.4

0.51

-0.1

VOO = T5V, VIN = OV

0.1

VOO = 15V, VIN = 15V

-10- 5
10-5

mA

-0.1

-1.0

p.A

0.1

1.0

p.A

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply
that the devices should be operated at these limits. The table of "Recommended Operating Conditions" and "Elect'rical Characteristics" provides
conditions for actual device operation.
Note 2: VSS = OV unless otherwise specified.

2·185

(.)

.m

(V')
0')

dc electrical characteristics

CD4093BC (Note 2)

0

~

C
.......

PARAMETER

MIN

~

IDO

Quiescent Oevice Current

(V')
0')

0

VOL

Low Level Output Voltage

~

C

(.)
VOH

VT-

High Level Output Voltage

Negative·Going Threshold Voltage

VT+

Positive-Going Threshold Voltage

VH

10L

liN

p.A

15.0

p.A

4.0

4.0

30.0

p.A

= VDD, 1101 < lp.A
VDD = 5V
VDD = 10V
VDD = 15V
VIN

= VSS, 110 1< lp.A
VOD = 5V
VDD = 10V
VDD = 15V

0.05

0

0.05

0.05

V

0.05

0

0.05

0.05

V

0.05

0

0.05

0.05

V

VIN

4.95

4.95

4.95

V

9.95

9.95

10

9.95

V

14.95

14.95

15

14.95

V

1101< lilA
VDD

1.3

2.25

1.5

1.8

2.25

1.5

2.30

V

VDD

2.85

4.5

3.0

4.1

4.5

3.0

4.65

V

4.35

6.75

4.5

6.3

6.75

4.5

6.9

V

VDD

3.5

3.6

2.75

3.3

3.5

2.65

3.5

V

VDD = 10V, Vo

7.0

7.15

5.5

6.2

7.0

5.35

7.0

V

10.5

10.65

8.25

9.0

10.5

8.1

10.5

V

0.5

2.35

0.5

1.5

2.0

0.35

~.O

V

1.0

4.3

1.0

2.2

4.0

0.70

4.0

V

1.5

6.3

1.5

2.7

6.0

1.20

6.0

V

1101< lilA

VDD

= 5V
= 10V
= 15V

VIN

= VDD

VDD

VDD ~ 5V,

0.52

0.44

0.88

0.36

VDD

1.3

1.1

2.25

0.9

,mA

3.6

3.0

8.8

2.4

mA

mA

= VSS
VDD = 5V, Vo = 4.6V
VDD = 10V, Vo = 9.5V
VDD = 15V, Vo ,;, 13.5V

mA

VIN

VDD
VDD

ac electrica I cha racteristics

PARAMETER
Propagation Delay Time

-0.44

-0.88

-0.36

-1.1

-2.25,

-0.9

mA

-3.6

-8.0

-8.8

-2.4

mA

-0.3

-10- 5

-D.3

-1.0

p.A

0.3

10-5

0.3

1.0

p.A

T A =. 25°C, Input t r , tf = 20 ns, CL = 50 pF, R L = 200k, unless otherwise specified.

CONDITIONS
VDD
VDO

Transition Time

-0.52
-1.3

= 15V, VIN = OV
= 15V, VIN = 15V

VDD

tTHL, tTLH

UNITS

7.5

(Any Input)

Input Current

MAX

1.0

VDD

High Level Output Current

MIN

2.0

Vo = O.4V
= 10V, Vo = 0.5V
VDD = 15V, Vo = 1.5V
10H

MAX

1.0

Hysteresis (VT+ - VT-)

Low Level Output Current

TYP

2.0

= 5V, Vo = 0.5V
= 1V
IYDD = 15V, Vo = 1.5V

(Any Input)

MIN

= 10V
VDD = 15V

= 5V, Vo = 4.5V
= 10V, Vo = 9V
VDD = 15V, Vo = 13.5V

(Any Input)

MAX

VDD ~ 5V
VDD

m

+85°C

25°C

-40°C

CONDITIONS

(.)

VDO
VDO
VDO

= 5V
= 10V
= 15V
= 5V
= 10V
= 15V

MIN

TYP

MAX

UNITS

300

600

ns

120

300

ns

80

240

ns

90

200

ns

50

100

ns

40

80

ns

Average Input Capacitance

5.0

7.5

pF

Power Dissipation Capacitance

24

2·186

pF

n

c

typical applications

~

o

CONTROL

pv
~

Gated Oscillator

w

OJ

s:

OUT

'-

VOO

R

I

(D

n

c

CONTROL

~

o

Ov----------------

C

(D

w

VOO----------------,

OJ

VT+-----VT- - - - - - - - - - t - - v

Assume t1 + t2

»

OV-------------T-----------------

tpHL + tpLH then:

to = RC Qn [VOOIVT-l

Voo--------------~--~
VOUT
OV---------------t--

:I~~~

(VT+)(Voo - VT-)
RC Qn

(VT-)(VOO - VT+)

Gated One-Shot

(a) Negative-Edge Triggered

VIN~

(b) Positive-Edge Triggered

--I I--

2-187

1= RC

~n (VOOIVT-)

n

U
m

M

typical performance characteristics

en

~.

Typical Transfer
Characteristics

C
U

15

........

~

~

M

~
>

m

~

u

40

I

I

VOO

=5V

~I~
en

~ =1 25
A I I

I I I

GUARANTEED MAXIMUM

D-VOUT
V'N*

*ANVINPUrT

I

I

10

30

r--.r--..,

I--- .
20 f-

~

voo

VT- VT+

I
I

,b I I I

I-

I-f-

H-tVT- VT.

~

c

g

10

C(

~

Guaranteed Hysteresis vs Vee
50

VT-- VT. I-f- I-~

f- VOO'10V

'"

o

=15V_

I I I I

...

en

I-VOO

I I I

1 I I
~~~
III

I I I

10

GUARANTEED MINIMUM

I I I

15

Voo (V)

Guaranteed Trigger Threshold
Voltage vs Vee

~

11
10

t

Guaranteed Hysteresis vs Vee

GUARANTEED HVSTERESIS-IVT.I IVTI
~:4.0;;B~IC0409JBC

'- TA

!~V~'N'I~iiVO~UT~~~~§gJ
>

1

Voo

8

S:Y-

=25'C .I .'.

-1-+-

100'.

:/""1
1
./

L/

VT-

V

(MAX)
./
(0.4 Vo~

~p

~

I -~

"- '(MIN) l -

I..- 1---

(0.1 VOO)-

~

10

15

10

INPUT VOLTAGE (V)

10

15

Voo (V)

15

VOO (V)

!nput and output characteristics
Output Characteristic

Input Characteristic

VOO

~
OHJl

VOL

VIHJL
VOL

"'U..

L

"'U.

LOAO

DRIVER

"t'''''''

V

Vss

= VOH -

VOO

VIN

VIN

~VOUT

T

OV

Voo

50PF
VOUT

OV

2-188

= VT+ (MIN)
= Vee

VIL(MAX) ~ Vee - VILIMAX)

ac test circuits and switching time waveforms

VOO

REGION

LOGIC "0" OUTPUT
REGION

VNML = VIH(MIN) - VOL ~ VIH(MIN)
VNMH

"",'o,,:r~ .

~#////#a

- VT-(MAX)

(")

C

~

o
o
en

...A

txJ

s:
........

CD40106BM/CD40106BC hex Schmitt trigger
general description

(")

C

~

features

o

...A

The C040106B Hex Schmitt Trigger is a monolithic
complementary MOS (CMOS) integrated circuit constructed with Nand P-channel enhancement transistors_
The positive and negative-going threshold voltages,
VT+ and VT _, show low variation with respect to
temperature (typ 0_0005VtC at VOO = 10VL and
hysteresis, VT+ - VT _ ~ 0_2 VOO is guaranteed.

All inputs are protected from damage due to static
discharge by diode clamps to VOO and VSS-

•

Wide supply voltage range

•

High noise immunity

•

Low power
TTL compatibility

•

Hysteresis

•

Equivalent to MM54C14/MM74C14
Equiva.lent to MC14584B

III

3V to 15V
0.7 VOO typ
fan out of 2
driving 74L
or 1 driving
74LS
0.4 VOO typ
0_2 VOD' guaranteed

schemati~ diagram

connection diagram

switching time waveforms

Dual-In-Line Package
Voo

voo ----t--:r-__--=_~
INPUT

vss

OUTPUT

I,: I,: 20 n.s

Vss
TOPVIEW

2-189

o

en
txJ

(")

(,)

r:o

absolute maximum ratings

recommended .operating conditions

ot-

(Notes 1 and 2)

(Note 2)

VOD dc Supply Voltage
~.S to +18 VOC
VIN Input Voltage
~.S to VOp +O.S VOC
-BSoC to +1S0°C
TS Storage Temperature Range'
Po Package Oissipation
SOOmW
TL Lead Temperature (Soldering, 10 seconds)
300°C

VOO dc Supply Voltage
VIN Input Voltage
T A Operating Temperature Range
C040106BM
C040106BC

«>
O

~

C
(,)
.......
~

r:o

«>

3i01SVOC
Oto VOO VOC
-5SoC to +125°C
-40° C to +85 0 C

otO

~

C

(,).

dc electrical characteristics

CD40106BM (Note 2)

-5S0C
PARAMETER
100

VOL

VOH

Quiescent Device Cu~rent

Low Level Output Voltage

High Level Output Voltage

CONOITIONS

10L

10H

liN

High Level Output Current

Input Current

UNITS

30
60

/lA

Voo = 15V

4.0

4.0

120

/lA

VOO = 5V

0.05

0.05

0.05

V

VOO = lOV

0.05

0.05

0.05

V

VOO = 15V

0.05

0.05

0.05

V

/lA

1101<1/lA

-

1101<1/lA
4.95
9.95

4.95
9.95 '

14.95

VOO = 10V, Va = 9V

L,ow Level Output Current

MAX

1.0

Voltage

Hysteresis (VT+ - VT-)

MIN

2.0

VOO = 15V

VH

125°C
MAX

1.0

VOO = 5V,

Voltage

TYP

2.0

Negative·Going Threshold

Positi".e-Going Threshold

MIN

VOO = 5V

VOO = 10V

Vn

2SoC

MAX

VOO = 10V

VOO = 5V

VT-

MIN

Va = 4.5V

5
10

4.95

V
V

9.95

14.95

15

0.7

2.0

0.7

1.4

2.0

0.7

2.0

V

1.4

4.0

1.4

3.2

4.0

1.4

4.0

V

14.95

V

VOO= 15V, VO= 13.5V

2.1

6.0

2.1

5.0

6.0

2.1

6.0

V

VOO = 5V,

3.0

4.3

3.0

3.6

4.3

3.0

4.3

V

VOO = 10V, Va = lV

6.0

8.6

6.0

6.8

8.6

6.0

8.6

V

VOO = 15V, Va = 1.5V

9.0

12.9

9.0

10.0

12.9

9.0

12.9

V

VOO = 5V

1.0

3.6

1.0

1.0

3.6

V

2.0

7.2
10.8

2.0
3.0

V

3.0

7.2
10.8

7.2

VOO = 15V

2.0
3.0

2.2
3,6

3.6

VOO = 10V

10.8

V

VOO = 5V,

Va = 0.5V

5.0

0.64

0.51

0.88

0.36

VOO = 10V, Va = 0.5V

1.6

1.3

2.25

0.9

mA

VOO = 15V, Va = 1.5V

4.2

3.4

8.8

2.4

mA

-:-0.64
-1.6

-0.51

-0.88

-0.36

mA

VOO = 10V, Va = 9.5V

-4.2

-2.25
-8.8

-0.9

VOO = 15V, Va = 13.5V

-1.3
-3.4

mA
mA

VOO = 5V,

VO=O.4V

Va

~

4.6V

mA

-2.4

VOO = 15V, VIN = OV

-0.10

-10- 5

-0.10

-1.0

~(A

VOO = 15V, VIN = 15V

0.10

10-5

0.10

1.0

tJ.A

Note 1: "Absolute Maximum Ratings" are those values beyond which .the safety of the device cannot be guaranteed. They are not meant to imply
that the devices should be operated at these limits. The table of "Recommended Operating Conditions" and "Electrical Characteristics" provides
conditions fC~ 3ct~al dev[ce operation.
Note 2: VSS = OV unless otherwise specified.
Note 3: CPD determines the no' load ac power consumption of any CMOS device. For complete explanation, see 54C/74C Family Characteristics
application note-AN-90.

2·190

(")

dc electrical characteristics

C

CD40105BC (Note 2)

~

UNITS

o
o0')

s:

~

CONDITIONS

MIN

-.
IDD

Quiescent Jell:'::. Current

VOD

10V

'.';jlj

Lov,' Level Output Voltage

High Level Output Voltage

.
VT-

VTt

10L

liN

IlA

8.0

8.0

60

IlA

16.0

16.0

120

IlA

0.05

0.05

V

V u [)' 15V

0.0:>

0.05

0.05

V

110 1< lilA

= 5V
= 10V
VOO = 15V

VOO

4.95

4.95

5

4.95

VOO

9.95

9.95

10

9.95

V

14.95

14.95

15

14.95

V

VOO

=

15V, '10

Positive-Going Threshold

\/00

~,

5V,

Voltage

VO" 4.5V

2.0

0.7

1.4

2.0

0.7

2.0

1.4

4.0

1.4

3.L

I 4.0
6.0

1.4

4.0

V

I 2.1

6.0

V

3.0

4.3

V

~

13.5V

2.1

6.0

2.1

5.0

Va

~

0.5V

3.0

4.3

:.0

3.6

4.3

VOO = 10V, Va

~

lV

6.0

8.6

C.O

c.t

8.6

1.5\/

9.0

12.9

laO

12.9

15V,

VO~

VOO = 5V

V

0.7

-9(\

I

1.0

3.6

1.e

2.2

VOO

~

10V

2.0

7.2

2.0

3.6

VDI)

= 15V

3.0

10.8

3.0

5.0

VOO

= 5V, Va = O.4V

I

I 3.0

V

8.6

V

9.0

12.9

V

3.6

1.0

3.6

V

7.2

2.0

7.2

V

10.8

3.0

10.8

V

0.52

0.44

0.88

0.36

Voo = 10V, Va = 0.5V

1.3

1.1

2.25

0.9

mA

= 15V, Vo = 1.5V

3.6

3.0

8.8

2.4

mA
mA

mA

-0.52

-0.44

-0.88

-0.36

VOO = 10V, Va = 9.5V

-1.3

-1.1

-2.25

-0.9

mA

VOO = 15V, Vo = 13.5V

-3.6.

-3.0

-8.8

-2.4

mA

VOO = 5V,

VOO

Vo = 4.6V

= 15V, VIN = OV

VOO = 15V, VIN = 15V

ac electrical characteristics
PARAMETER
Propagation Delay Time From
Input To Output

tTHL or tTLH

30

0.05

= 10V, Va = 9V

tpHL or tpLH

4.0

'v'IJl) -- 10V

VOO -= 5V,

I nput Current

4.0

V

VOO

High Level Output Current

MAX

0.05

VOO
10H

MIN

0.05

Negative·Going Threshold

Low Level Output Current

MAX

0.05

Voltage

Hysterp.sis (VT+ - VT-)

TVP

Transition Time

OJ

........
('")

C

~

5V

VOO~

VH

MIN

+8S0C

;lnl <. 11lA
Vul)

VOH

MAX

i

= 5V

'/LJU ·15V

VOL

2SoC

-40°C

PARAMETER

-0.30

-10- 5

-0.30

-1.0

IlA

0.30

10-5

0.30

1.0

IlA

T A = 25°C, CL = 50 pF, R L = 200k, tr and tf = 20 ns, unless otherwise specified.

CONDITIONS

MIN

TVP

MAX

UNITS

= 5V
VOO = 10V

220

400

80

200

ns

VOO = 15V

70

160

ns

= 5V
= 10V

100

200

ns

50

100

ns

VOO

VOO
VOO

ns

VOP = 15V

40

80

ns

CIN

Average Input Capacitance

Any Input

5

7.5

pF

CPO

Power Dissipation Capacitance

Any Gate (Note 3)

14

2-191

pF'

o

~

o

0')

OJ

(")

typical applications
Low Power Oscillator

VOO-----------

VT+

t1"" RCQn-VTVOO - VT-

t2 "" RC Qn - - - - -

f "" - - - - - - - - VT+ (VOO- VT-)

RC Qn - - - - - - VT - (VOO - VT+)

voo~
~. t2---

Note: The equations assume
~1 + t2 » tpHL + tpLH

~tl~

o

typical performance characteristics
VOO-

Typical Transfer
Characteristics

Guaranteed
Trip Point Range

vT+INPUT
VOLTAGE

15

20

VT-

'~

11
10

«

OV

I0

>

10

VOO

l-

S
4.3
,3.0
2.0
0.7
0

~

10

15

INPUT VOLTAGE (V)

20

OUTPUT
VOLTAGE

10

11

VooIV)

OV

\

2-192

VOUT

vs

t

•

n
c

~

o

m

o

°txJ

~

..........

n

CD40160BM/CD40160BC
CD40161BM/CD40161BC
CD40162BM/CD40162BC
CD40163BM/CD40163BC

decade counter with asynchronous clear
binary counter with asynchronous clear
decade counter with synchronous clear
binary counter with synchronous clear

c

~

o

m

o

txJ

n

n

c

general description

-~

o

can be used to enable successive cascaded stages. Logic
transitions at the enable P or T inputs can occur when
the clock is high or low.

These (synchronous presettable up) counters are monolithic complementary MOS (CMOS) integrated circuits
constructed with Nand P-channel enhancement mode
transistors. They feature an internal carry look-ahead for
fast counting schemes and for cascading packages without additional gating.

m
txJ

~

..........

features
3V to 15V
0.45 VOO typ
fan out of 2
driving 74L
or 1 driving 74LS
Internal look-ahead for fast counting schemes
Carry output for N-bit cascading
Load control line
Synchronously programmable
Equivalent to MC14160B, MC14161B, MC14162B,
MC14163B
Equivalent to MM74C160, MM74C161, MM74C162,
MM74C163

• Wide supply voltage range
• High noise immunity
• Low power TTL
compatibility

A low level at the load input disables counting and
causes the outputs to agree with the data input after
the next positive clock edge. The clear function for
the C040162B and C040163B is synchronous and a
low level at the clear input sets all four outputs low
after the next positive clock edge. The clear function
for the C040160B and CD40161 B is asynchronous
and a low level at the clear input sets all four outputs
low, regardless of the state of the clock.

•
•
•
•
•

Counting is enabled when both count enable inputs are
high. Input T is fed forward to also enable the carry out.
The carry output is a positive pulse with a duration
approximately equal to the positive portion of QA and

•

n
c

~

9
0)

txJ

n

n

c

~

o

m
N
txJ

s:

..........

n

c

~

o
m

N
txJ

connection diagram

51
Dual-I n-Line Package

CLEAR -

1

U

n

c

~

.,!!. VOO

o

a;

~ RIPPLE
CARRY

W
txJ

.1.
INB .!
INC .l.

~QA

........

6
iNO-

~Qo

CLOCK

.2.

INA

VSS

~QB
~QC

-

~ ENABLE T

7
ENABLE P -

~LOAO

..!
TOP VIEW

2-193

~

n

c

~

o

0)

W
txJ

n

CJ
al

M
CD

.-

0

~

C

CJ

.........

~

absolute maximum ratings

recommended operating 'conditions

(Notes 1 and 2)

(Note 2)

voo dc Supply Voltage
-0.5 to +18 VOC
VIN Input Voltage
-0.5 to VOO +0.5 VOC
TS Storage Temperature Range
-{l5°C to +150°C
Po Package Dissipation
500mW
TL Lead Temperature (Soldering, 10 seconds)
300°C

Voo dc Supply Voltage
VIN Input Voltage
T A Operating Temperature Range
C040XXXBM
C040XXXBC

3 to 15 VOC

o to VOO VOC
-55°C to +125°C
-40° C to +85° C

al

M
CD

.-

dc electrical characteristics

CD40160BM, CD401G1BM, CD40162BM, CD40163BM (Note 2)

0

~

PARAMETER

C

MIN

CJ

ci

100

Quiescent Device Current

CJ

~

VOH

High Level Output Voltage

al

N
CD

.~

C

VIL

Low Level Input Voltage

IlA

20

20

600

IlA

= 5V
= 10V

0.05

0.05

0.05

V

0.05

0.05

0.05

V

VOO=15V

0.05

0.05

0.05

V'

IIOI---

1

1 1 1

ABC

p-- DOWN
CLEAR DA

DB

0
CARRY

f>--

BORROW

f>--

UP

Dc

00

,I I I I,

,I 1 I I,

OUTPUTS

OUTPUTS

CLEAR--+-------~.--------

2-201

fan out of 2
driving 74L
or 1 driving 74LS

MM54C192/MM74C192
and MM54C193/MM74C193

All inputs are protected against damage due to static
discharge by clamps to VDD and VSS.

INPUTS

3V to 15V

TO NEXT
STAGE

o

m

absolute maximum ratings

recommended operating conditions

en

(Notes 1 and 2)

(Note 2)

Voo d~ Supply Voltage
-{l.Sto+ 18VOC
VIN Input Voltage
-{l.S to Voo + O.S VOC
45SoC to +lS0°C
TS Storage Temperature Range
SOOmW
Po Package Dissipation
TL Lead Temperature, (Soldering, 10 seconds)
300°C

Voo dc Supply Voltage
VIN Input Voltage
T A Operating Temperature Range
C040192BM, C040193BM
C040192BC; CD40193BC

M

5~
c

0,
........

~

m
en

-

dc electrical characteristics

o
cJ

100

M

c

m
N

VOL

Quiescent Oevice Current

Low Level Output Voltage

en

5

~

c

High Level Output Voltage

o

VIL

Low Level Input Voltage

2SoC
MAX

MIN

MIN

TYP

12SoC
MAX

MIN

MAX

5

5

150

VOO = 10V

10,

10

300

I1A

VOO = 15V

20

20

600

I1A

VOO = 5V

0.05 \

0.05

0.05

V

0.05

0.05

0.05

V

0.05

0.05

0.05

4.95

4.95

4.95

V

VOO = 10V

9.95

9.95

9.95

V

VOO = 15V

14.95

14.95

14.95

VOO

= 5V,

Vo = 0.5V or 4.5V

V

1.5

1.5

1.5

V
V

3.0

3.0

3.0

en

VOO = 15V, Vo = 1.5Vor 13.5V

4.0

'4.0

4.0

o

VIH

IOL

High Level Input Voltage

Low Level Output Current ,

VOO = 5V,

Va = O.5V or 4.5V

3.5

3.'5

VOO= 10V, VO= lVor9V

7.0

7.0

7.0

V

VOO = 15V, Va = 1.5V or 13.5V

11.0

11.0

11.0

V

0.64

0.51

0.88

0.36

mA

1.6

1.3

2.25

0.9

mA
mA

VOO

= 5V,

Va = 0.4V

VOO = 15V, Va = 1.5V
High Level Output Current

VOO = 5V,

Va = 4.6V

VOO = 10V, Va = 9.5V
VOO
liN

Input Current

= 15V,

Va = 13.5V

= 15V,

4.2

3.4

8.8

2.4

-0.51 '

-0.88

-0.36

mA

-1.6

-1.3

-2.25

-0.9
-2.4

mA

-4.2 .

-3.4

-0.1

-1.0

I1A

0.1

10-5

0.1

1.0

I1A

(Note 2) CD40192BC,CD40193BC
2SOC

-40 C

CONOITIONS

MIN
Quiescent Oevice Current

Low Level Output Voltage

VIL

High Level Output Voltage

Low Level Input Voltage

JOL

Low Level Output Current

liN

High Level Output Current

Input Current

MIN

MAX

UNITS

20

lS0
300

IJA

isv

80

80

600

IJA

VOO; 5V

0,05

0.05

0.05

V

·VOO; IOV

0.05

0.05

0.05

V

0,05

0.05

0.05

I1A

V

VOO = 5V

4.95

4.95

4.95

V

VOO = 10V

9.95

9.95

9.95

V

VOO; 15V

14.95

14.95

14.95

VOO = 5V,

Va = 0.5V or 4.5V

,

V

1.5

1.S

1.5

V

3.0

3.0

3.0

V

4.0

4.0

4.0

V

VOO = SV. Va = O,SV or 4.5V
VOO; 10V, Va ~ lVor 9V

3.S

3.5

3.5

7.0

7.0

7.0

V

VOO = 15V, Va = 1.SV or 13.SV

11.0

11.0

11.0

V

VOO = SV, Va; O.4V
Voo,,; 10V, Vo = O,SV

0.S2
1.3 .

0.44

0.88

0.36

mA

1.1

2.2S

0.9

mA

VOO = lSV, Va; 1.5V
IOH

8S"C
MAX

40

VOO = lSV. Va = 1.SVor 13.SV
High Level Input Voltage

TYP

20

VOO = 10V, Va = lVor 9V

VIH

MIN

40

VOO; 15V
VOH

MAX

VOO = SV
VOO; 10V
VOO;

VOL

mA

-10- 5

U

PARAMETER

-8.8

-0.1

VIN = 15V

dc electrical characteristics

V

-0.64

VOO = 15V, VIN = OV
VOO

100

V

3.5

VOO = 10V, Va = 0.5V

IOH

V

VOO = 5V

VOO = 10V, Vo = lVor 9V

5
~
c

I1A

VOO = 10V

m

N

UNITS

VOO = SV

VOO = 15V
VOH

........

~

CONDITIONS

PARAMETER

~

-SSoC to +12SoC
-40°C to +8SoC

(Note 2) CD40192BM, CD40193BM
~soC

o

3to1SVOC

o to Voo VOC

VOD

~

5V,

Va = 4.6V

V

3,6

3.0

8.8

2.4

mA

-o.S2

-{l.44

-{l.88

-{l,36

mA
mA

VOO; 10V. Va

~

9.SV

-1.3

-1.1

-2.25

-0.9

VDO = 1SV. Va

c

13.SV

-3.6

-3.0

-8.8

-2.4

VOO = 1SV, VIN

~

OV

-0.3

VOO = 1SV. VIN

=

lSV

0.3

2-202

-10- S
lO- S

mA

-0.3

-1.0

0.3

1.0

IJA
IJA

("')

ac electrical characteristics

T A = 25°C, CL = 50 pF, RL = 200Kn, tr = tr = 20ns, unless otherwise specified.

PARAMETER
tPLH
or

CONDITIONS

tpHL

tpLH
or

tRCL
or

400

ns

100

160

ns

VOO = 15V

80

130

ns

,s:

Propagation Delay Time From Count Up

VOO = 5V

120

200

ns

C

To Carry

VOO = 10V

50

80

ns

tlA(H

tWL

CIN

~

VOO=15V

40

65

ns

Propagation Delay Time From Count

VOO = 5V

.120

200

ns

OJ

Down To Borrow

VOO = 10V

50

80

ns

VOO = 15V

40

65

ns
ns

Time Prior To Load That Data Must

VOO = 5V

100

160

Be Present

VOO=10V

30

50

ns

VOO=15V

25

40

ns

Propagation Delay Time From Clear

VOO = 5V

130

220

ns

To Q

VOO=10V.

60

100

ns

VOO = 15V

50

80

ns

Propagation Delay Time From Load

VOO = 5V

300

480

ns

To Q

VOO = 10V

120

190

ns

Von = 15V

95

150

ns

VOO = 5V

100

200

ns

VOO = 10V

50

100

ns

40

80

Output Transition Time

VOO=15V
Maximum Count Frequency

VOO = 5V

Maximum Count Rise Or Fall Time

Minimum Count Pulse Width

Minimum Clear Pulse Width

Minimum Load Pulse Width

Average Input Capacitance

2.5

ns

4

MHz

VOO = 10V

6

10

MHz

VOO = 15V

7.5

12.5

MHz

VOO = 5V

15

j1S

, VOO = 10V

5

j1S

VOO = 15V

2

j1S

VOO = 5V

120

200

VOO = 10V

35

80

ns
ns

VOO=15V

28

65

ns

VOO = 5V

300

480

ns

VOO = 10V

120

190

ns

VOO = 15V

95

150

ns

VOO = 5V

100

160

ns

VOO = 10V

40

65

ns

VOO = 15V

32

55

ns

Load and Data

.5

7.5

pF

10

15

pF,

Inputs (A,B,C,O)
I

Count Up, Count
Down and Clear

CPO

("')

9CD

tfCL
tWH,tWL

N
OJ

250

tTHL
fCL

~

o
....
CD

VOO = 10V

tPHL
tTLH
or

UNITS

VOO = 5V

tpHL
tsu

MAX

Propagation Delay Time From Count Up

tpHL
tPLH
or

TYP

Or Count Down To Q

tpHL
tPLH
or

MIN

C

Power Dissipation Capacity

(Note 3)

100

pF

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply
that the devices should be operated at these limits. The table of "Recommended Operating Conditions" and "Electrical Characteristics" provides
conditions for actual device operation.
.
Note 2: VSS = OV unless otherwise specified.
Note 3: CPO determines the no load ac power consumption of any CMOS device. For complete explanation, see 54C/74C Family Characteristics
application note, AN·90.

2·203

N

P
("')
c
~
9
CD
tAl
OJ

,s:

("')

C

~

9

CD
tAl
OJ
("')

(.)

a::I
M

schematic diagrams

0)

5

~

c

(.)
........

:aa::I

M

....

0)

o

~

c(.)
(j
a::I
N

0)

5~
c(.)

.......

:aa::I
N

0)

5~
C

VooU

a

rvss

(.)
CD4019~BM/CD40192BC Synchronous 4-Bit Up/Down Decade Counter

CIN
10

. vooU

DC
6

B

rvss
CD401.93BM/CD40193BC Synchronous 4-Bit Up/Down Binary Counter

2-204

timing diagrams
CLEAR---fl~

____________________________________________

LOAO

A

_______________ _
.....-+-+--+-;----------------~

8 --+-1---+--11 -

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

---

-

-

~---------------­
I

DATA

r-+--I---+--.

-

~---~-----------I

1

~----------------

:

COUNT - - t - + - + + - - - .
UP
COUNT--t-+-++-~---------~~

DOWN

0A=-1
OB=_
OUTPUTS
_
I
OC _ _

1

I

00: _ ...
, -t--+-+--+....

CARRY
BORROW
SE~UENCE

ILLUSTRATED

CLEAR

PRESET

Sequence:
1. Clear outputs to zero.
2. Load (preset) to BCD seven.
3. Count up to eight, nine, carry. zero, one and two.
4. Count down to one, zero, borrow, nine, eight and seven.
CD40192BM/CD40192BC

---fl!-_____________________________

CLEAR
LOAD

DATA[::--+-i---+--!~ ~ ~ ~ ~ ~ ~ ~ ~ =~ ~ ~ ~ ~ ~ ~

r-t-t--I-i----------------'--

r-t-t--I-il

-

-- - - --- - ----- --- - - _.- -

-- -

---- ---

CO UNT - - + - t - - - H - - - .
UP
COUNT--+-r-+-+--t--------+---.
DOWN

0A--I

OB-

:-1

OUTPUTS

OC _ _

1

I

OD=-_

CARRY
BORROW

13
SEQUENCE
IllUSTRATED

CLEAR

PRESET

14

15
0
COUNT UP

15
14
COUNT DOWN

13

Sequence:
1. Clear outputs to zero.
2. Load (preset) to binary thirteen.
3. Count up to fourteen, fifteen, carry, zero, one and two.
4. Co~nt down to one, zero, borrow, fifteen, fourteen and thirteen.
CD40193BM/CD40193BC

2-205

(.)

m

CD

L t)

~

C

(.),
........

m

CD4510BM/CD4510BC BCD up/down counter
CD4516BM/CD4516BC binary up/down counter

L t)

general description

~

CD
~

C

(.)

cJ

m

o

L t)

~

C

(.)

........

~
CO

-

o

L t)

-.::t

C'

(.)

All inputs are protected against static discharge by diode
clamps to both VOO and VSS.

The C04510BM/C04510BC and C04516BM/C04516BC
are monolithic CMOS up/down counters which count
in BCD and binary, respectively.
The counters count up when the up/down'input is at
logical "1" and vise versa. A logical "1" preset enable
signal allows information at the parallel inputs to preset
the counters to any state asynchronously with the clock.
The counters are advanced one count at the positivegoing edge of the clock if the carry in, preset enable,
and reset inputs are at logical "0". Advancement is
inhibited when any of these three inputs are at logical
"1 ". The carry out signal is normally at logical "1"
state and goes to logical "0" when the counter reaches
its maximum count in the "up" mode or its minimum
count in the "down" mode, provided the carry input is
at logical "0" state. The counters are cleared asynchronously by applying a logical "1" voltage level at the
reset input.

features
•

Wide supply voltage range

•

High noise immunity

•

Low power TTL
comp__.--1

7 CARRY
OUT

VOO·16
VSS·,

6 . 01

11

14

02

OJ

*Flip·fIOp toggles at the positive·going edge of clock (e) if Toggle Enable
(TEl is at logical "1" and Preset Enable (PEl is at logical "0"
FIGURE 2. CD4516

2-211

2

Q4

U

£Q

....

CD

logic waveforms

Jl)

CD4510BM/CD4510BC

~

c

u
:!

CLOCK

.......

CARRY IN

£Q

UP/DOWN

CD
....

RESET

Jl)

~

c

u

o
£Q

o....

PRESET
ENABLE

rL n-ru rt. ru rt. n-n-rL L L ILn-rLILrL n-rL rL L IL rt. rL nIrl

I
r~

;

-,

n

Jl

J2
J3

Jl)

~

J4

u
.......
:!

01

c

al

o
....
Jl)

~

c

u

Ir--

-

~

r- fL

r--

L

'r-- 1

r--

~

fL

r-L

Ir--

fL r- L
~

02

II

03
04

II

II

II

I

CARRY OUT
COUNT

0

1

2

3

4

5

6

7

B

IY

B

r-

r-:'"--

,,--- ---.

II

I

II

I'I

7

6

5

n

Ir-- --.

IL

1,4

3

2

1

0

'0 ~

9

""'"-

-

7

6

0

CD4516BM/CD4516BC
CLOCK

n-n... rL n... rLrLrL n... rLrLrLrLrLilJLiLrLrLrLrLrLrLrLrL
!I

CARRY IN

I

UP/DOWN

r-

RESET
PRESET
ENABLE

-,

Jl

J2
J3

I

J4
01

02

~~

Ir--

1'---

'--

r- ~r- r- ~~

Ir-I~

"--

II

~

II

r-"--

II

~

Ir--

~

II

r

rL -

h

n.-

II

rL -

II

03

n.-

04
CARRY OUT
COUNT

5

6

7

B

9

10

11

12

13

14

L15

9

2·212

B

7

6

5

4

3

2

I

1

0

LJ
0

15

0

(")

C

~

~

...
(J1

to

s:

"(")
C
~

CD4511BM/CD4511BC BCD-to-7 segment late hid ecod erI drive r

...
(J1

to

general description

features

The CD4511 BM/CD4511 BC BCD·to·seven segment latch/
decoder/ driver is constructed with complementary MOS
(CMOS) enhancement mode devices and NPN bipolar
output drivers in a single monolithic structure. The circuit
provides the functions of a 4·bit storage latch. an 8421
BCD·to·seven segment decoder. and an output drive
capability. Lamp test (L Tl. blanking (BI). and latch
enable (LE) inputs are used to test the display. to
turn·off or pulse modulate the brightness of the display.
and to store a BCD code. respectively. It can be used
with seven·segment light emitting diodes (LED). incan·
descent. fluorescent. gas discharge. or liquid crystal
readouts either directly or indirectly.

•
•

Low logic circuit power dissipation

•
•
•
•

Latch storage of code

•
•
•

(")

High current sourcing outputs (up to 25 rnA)

Blanking input
Lamp test provision
Readout blanking on all illegal input combinations
Lamp intensity modulation capability
Time share (multiplexing) facility
Equivalent to Motorola MC14511

Applications include instrument (e.g .• counter. DVM.
etc.) display driver. computer/calculator display driver.
cockpit display driver. and various clock. watch. and
timer uses.

truth table

connection diagram

U

B...!..

INPUTS

~Voo

~t

c.2..
[j.2.
_

r!!-g

4

BI-

r!!-.

LE.1.

r!!-b

O..!.

I-- •

A..!...

~d

vss..!

r!-.

11

TOPVIEW

Display

IL71 Ilc 1.:lIL/lslbl lal91
1

0

1

2

1
I

3

4

5

6

7

B

OUTPUTS

LE

61

LT

D

C

6

A

a

b

c

d

e

f

9

DISPLAY

X

X

0

X

X

X

X

1

1

1

1

1

1

1

8

X

0

1

X

X

X

X

0

0

0

0

0

0
0
0
0
0
0
0
0
0
0
0
0

1

1

0
0

1

1

1

1

1

1

0

1

1

0

0

0
0
0

0

1

1

1

1

0

1

1

0

1

1

1

1

0
0
0
0

0

1

1

1

1

1

1

1

1

1

0

0

1

1

1

1
1

0

1

1

1

l'

0

1

1

1

1

1

1

1

0
1

0
0

0
0
0

1

0
1

0
1

1

0
0
0
0
0
0
0
0

0
1

1

1

1

1

1

0

0

1

1

1

1

1

1

0

1

1

1

,I

0

0
0
0
0
0
0

0
0
0

1

1

1

1

1

1

1

0
0
0
0

1

1

1

1

0

1

1

1

0

1

1

1

0

1

1

1

1

1

1

1

X

X

1

1

0
0

0

0

1

0
0

1

1

1

0

0
0

1

1

0

X

X

1

0

0
0
0

1

1

1

4

1

1

1

1

1

0

0

0

0

5
6
7

1

1

1

0

0
0
0
0
0

0
0

0
0

0
0
0
0
0
0
0

1

0
0
0

o

0
'0

0

0

X·Don'tcare
-Depends upon the BCD coda applied during the

.

'/-:-/b
·f 1·
d

2·213

1

1

0
0
0
0

9

Segment Identification

1

2
3

1

a to 1 transition of LE.

8
9

absolute maximum ratings

recommended operating conditions

(Notes 1 and 2)

(Note 2)

VDD dc Supply Voltage
-O.SV to +18V
VIN Input Voltage
-o.5V to VDD +0.5V
TS Storage Temperature Range
-65°C to +150°C
PD Package Dissipation
500mW
TL Lead Temperature (Soldering, 10 seconds)
300°C

VDD dc Supply Voltage
VIN Input Voltage
T A Operating Temperature Range
CD4510BM, CD4S16BM
CD4510BC, CD4516BC

d c electrical characteristics

+ 12SoC

+2S0C

CONDITIONS
MIN

Output Volt6g:::
Logical "0"
Level (V OUT)

Voo = 5V
Voo ='lOV
VOO = 15V

Output Voltage
Logical "1"
Level (V OUT)

,Voo=5V
Voo = 10V
Voo = 15V

-55°C to +125°C
0
-40° C to +85 C

CD4511BM
-5S0C

PARAMETER

3V to 15V ,
Oto VDD

TYP

MAX

MIN

0.01
0.01

TYP

MAX

MIN

0.01
0.01

0
0
0

TYP

MAX
0.05
0.05

UNITS
V
V
V

4.1
9.1

4.1
9.1

4.57
9.58
14.59

4.1
9.1

V
V
V

Noise Immunity
(VNLJ

Voo = 5V, V OUT ~ 3.5V
Voo = 10V, V OUT ~ 7V
Voo = 15V, V OUT ~ 10.5V

1.5
3.0

1.5
3.0

2.25
4.5
6.75

1.4
2.9

V
V
V

Noise Immunity
(V NH )

Voo = 5V, VOUT:S; 1.5V
Voo = 10V, VOUT:S; 3V
Voo = 15V, VOUT:S; 4.5V

1.4
2.9

1.5
3.0

2.25
4.5
6.75

1.5
3.0

V
V
V

Output (Source)
Drive Voltage
(V OH )

Voo = 5V,
Voo = 5V,
Voo = 5V,
V oo ,=5V,
Voo = 5V,
Voo = 5V,

IOH=OmA
IOH = 5 mA
IOH = 10mA
IOH = 15 mA
IOH = 20 mA
IOH = 25 mA

4.1

4.57
4.24
4.12
3.94
3,75
3.54

V
V
V
V
V
V

= 10V, IOH = 0 mA
= 10V, IOH = 5 mA
= 10V, IOH = 10 mA
= 10V, IOH = 15 mA
= 10V, IOH = 20 mA
= 10V, IOH = 25 mA

9.1

9.58
9.26
9.17
9.04
8.9
8.75

V
V
V
V
V
V

14.59
14.27
14.18
14.07
13.95
13.8

V
V
V
V
V
V

Voo
Voo
Voo
Voo
Voo
Voo

3.9
3.4

9.0
8.6

Voo = 15V, IOH = 0 mA
Voo = i5V, le:lH = 5 mA
Voo = 15V, IOH = 10 mA
Voo = 15V, IOH = 15 mA
Voo = 15V, IOH = 20 mA
Voo = 15V, IOH = 25 mA
Output (Sink)
Drive Voltage
(Iod

Voo
Voo
Voo

= 5V, V~L = OAV
= 10V, VOL = 0.5V
= 15V, VOL = 1.5V

0.5
1.1

0.4
0.9

,.

Input Current
(lIN)

0.78
2.0
7.8

0.28
0.65

10

pA

Note 1: Devices should not be connected with power on.

-

."

2-214

mA
mA
mA

(")

dc electrical ch aracteri stics

C

CD4511 Be

~

........U1
CD

-40°C
PARAMETER

CONDITIONS

MIN

= 5V
= 10V

MAX

MIN

0.01
0.01

Output Voltage
Logical "0"
Level (V OUT )

V DD
V DD
V DD

'"

15V

Output Voltage
Logical "1"
Level (V OUT )

V DD
V DD
V DD

'"'

5V

= 10V
= 15V

Noise Immunity
(V NL )

V DD = 5V, V OUT
V DD = 10V, V OUT
V DD = 15V, V OUT

Noise Immunity
(V NH )

V DD = 5V, V OUT ::; 1.5V
V DD = 10V, V OUT ::; 3V
V DD = 15V, V OUT ::; 4.5V

Output (Source)
Drive Voltage
(V OH )

V DD
V DD
V DD
V DD
V DD
V DD

= 5V,
= 5V,
= 5V,
= 5V,
=·5V,
= 5V,

V DD
V DD
V DD
V DD
V DD
V DD

=
=
=
=
=
=

V DD
V DD
V DD
V DD
V DD
V DD

=
=
=
=
=
=

Output (Sink)
Drive Voltage
(I OL )

TYP

+85°C

+25°C
TYP
0
0
0

MAX

MIN

TYP

0.01
0.01

MAX
0.05
0.05

UNITS

(")

V
V
V

4.1
9.1

4.1
9.1

4.57
9.58
14.59

4.1
9.1

V
V
V

1.5
3.0

1.5
3.0

2.25
4.5
6.75

1.4
2.9

V
V
V

1.4
2.9

1.5
3.0

2.25
4.5
6.75

1.5
3.0

V
V
V

IOH = 0 mA
IOH ~ 5 mA
IOH=10mA
IOH=15mA
IOH = 20 mA
IOH = 25 mA

4.1

4.57
4.24
4.12
3.94
3.75
3.54

V

10V,
10V,
10V,
10V,
10V,
10V,

IOH· = 0 mA
IOH = 5 mA
IOH=10mA
IOH = 15 mA
IOH = 20 mA
IOH = 25 mA

9.1

9.58
9.26
9.17
9.04
8.9
8.75

V
V
V
V
V
V

15V,
15V,
15V,
15V,
15V,
15V,

IOH
IOH
IOH
IOH
IOH
IOH

14.59
14.27
14.18
14.07
13.95
13.8

V
V
V
V
V
V

~

~
~

3.5V
7V
10.5V

3.6
2.8

8.75
8.1

= 0 mA
= 5 mA
= 10 mA
= 15 mA
= 20 mA
= 25 mA

Voo = 5V, VOL = 0.4V
V DD = 10V, VOL = 0.5V
V DD = 15V, VOL = 1.5V

0.2
0.5

0.23
0.6

0.78
2.0
7.8
10

Input Current
(liN)

/

2-215

V
V
V
V
V

0.16
0.4

3:
.......

mA
mA
mA
pA

C

~

....
....
CD
U1

(")

(.)

~

u;

III:t
C
Q

ac electrical characteristics
T A = 25°C and C L

= 15 pF, typical

temperature coefficient for all values of V DO

PARAMETER

~

9""
9""

MIN

(.)

TYP

Input Capacitance (C IN )

VIN ~ 0

5.0

Output Rise Time (t,) (Figure ta)

Voo ~ 5.0V
Voo ~ 10V
Voo ~·15V

30·
17
15

Output Fall Time (tt) (Figure ta)

Voo ~ 5.0V
Voo ~ 10V
Voo ~ 15V

1000
1000
1000

Turn·Off Delay Time (Data) (tPLH)
(Figure ta)

Voo ~ 5.0V
Voo ~ 10V
Voo ~ 15V

640
250
175

Turn·On Delay Time (Data) (tPH L)
(Figure Ta)

VOO ~ 5.0V
Voo ~ 10V
Voo ~ 15V

720
290
195

Turn·Off Delay Time (Blank) (t PLH )
(Figure Ta)

Voo ~ 5.0V
Voo ~ lOV
Voo = 15V

Turn·On Delay Time (Blank) (t PHL )
(Figure Ta)

Voo
Voo
Voo

In

III:t
C

CD4511BC

CONDITIONS

.........

m

= O.3%/oC

CD4511BM
MAX

MIN

TYP

UNITS
MAX

5.0
175
75

30
17
15

pF

200
110

1000
1000
1000

ns
ns
ns
ns
ns
ns

640
250
175

2250
900

ns
ns
ns

1500
600

720
290
195

2250
900

ns
ns
ns

320
130
100

1000
400

320
130
100

1500
600

ns
ns
ns

= 5.0V
= 10V
= 15V

485
200
160

1000
400

485
200
160

1500
600

ns
ns
ns

Turn·Off Delay Time (Lamp
Test) (tPHLl (Figure Ta)

Voo = 5.0V
Voo = lOV
Voo = 15V

290
125
85

625
250

290
125
85

940
375

ns
ns
ns

Turn·On Delay Time (Lamp Test)
(t PHL ) (Figure Ta)

Voo 5.0V
Voo = 10V
Voo = 15V

=

290
120
90

625
250

290
120
90

940
375

ns
ns
ns

Setup Time (tsETUP) (Figure Tb)

Voo
Voo
Voo

= 5.0V
= 10V
= 15V

180
76

Hold Time (tHoLO) (Figure tbl

Voo
Voo
Voo

= 5.0V
= 10V
= 15V

0
0

Minimum Latch Enable Pulse
Width (PW LE I (Figure Te)

\/

v

-

DO -

Voo
Voo

~

,.." I

1500
600~

270
114

90
38
20

90
38

--90
-38
-20

..l.U'II

;JLU

= 10V
= 15V

220

26u
110
65

780
330

switching time waveforms
(a)

Voo
INPUT

DV
Voo
OUTPUT

DV

(b)

Voo
LE

DV

DATA INPUT

Ic)

,

Voo

,

FOR SETUP

________--J/~_.!~ .!0!..ll__

OUTPUT

DV

20ns

20ns
Voo
LE
(STROBED)

DV

FIGURE 1.

2-216

90
38
20

ns
ns
ns

-90
-38
-20

ns
ns
ns

260
110
65

ns
ns
ns

typical applications
light Emitting Diode (LED) Readout

Voo

Voo

,

COMMON
CATHODE LEO

COMMON
ANOOE LEO

Fluorescent Readout

I ncandescent Readout

Voo

Voo

DIRECT
(LOW BRIGHTNESS)

··A filament pre-warm resistor is recommended to reduce hlament
therrnalshockand increase the effective cold resistance of the
filament.

Vss OR APPROPRIATE
':" VOLTAGE BELOW Vss.

liquid Crystal (LC) Readout

Gas Discharge Readout

Voo

APPROPRIATE
VOLTAGE

Direct de drive of le's not recommended for life of LC readouts.

2·217

(.)

m

o

N

I.t)

~

C

(.)
.........

~

m

o
N

CD4518BM/CD4518BC, CD4520BM/CD4520BC
dual synchronous up counters

'

I.t)

~

C

general description

(.)
(.)~

m

00

orI.t)

,~

C

(.)
.........

~
CO
00

orI.t)

The CD4518BM/CD4518BC dual BCD counter and the
CD4520BM/CD4520BC dual binary counter are implemented with complementary MaS (CMOS) circuits
constructed with Nand P-channel enhancement mode
transistors ..

line. All inputs are protected against static discharge by
diode clamps to both VDD and VSS.

features

Each counter consists of two identical, independent,
synchronous, 4-stage counters. The counter stages are
toggle flip-flops which increment on either the positive·.
edge of CLOCK or negative·edyt: of ENABLE, simplifying
cascading of multiple stages. Each counter can be
asynchronously cleared by a high level on the RESET

Wide supply voltage range

•

High noise immunity'

•

Low power TTL
compatibility

•

6 MHz counting rate (typ) at VDD = 10V

0.45 VDD typ
fan out of 2
driving 74L
or 1 driving 74LS

~

C

(.)

truth table
CLOCK

ENABLE

RESET

ACTION

1

0

Increment counter

0

~

0

I ncrement counter

"-

X

0

No change

0

No change

J

'X

J

J
1

0

0

No change

\...

0

No change

X

1

01 thru 04

X
X

= Don·t

=0

Care

connection diagram
Dual·ln·Line and Flat Package

VDD

16

G4

RESET

15

GJ

12

ENABLE

11

CLOCK

10

COUNTER 1

C

CLOCK

ENABLE

G1

G2

14

R

R

COUNTER 2

G2

GJ

TOP VIEW

2-218

3V to 15V

•

G4

RESET

VSS

n
absolute maximum ratings

recommended operating conditions

(Notes 1 and 2)

(Note 2)

-o.5V to +18V
voo Supply Voltage
VIN Input Voltage
-o.5V to VOO + O.5V
4i5°C to +150°C
TS Storage Temperature Range
Po Package Dissipation
500mW
TL Lead Temperature (Soldering, 10 seconds)
300°C

Voo Supply Voltage
VIN Input Voltage
T A Operating Temperature Range
C045l8BM, C04520BM
C045l8BC,C04520BC

CJ

~

(J1
....10

CO
3V to l5V
OV to VOO

OJ

~

.........
-55°C to +125°C
-40°C to +85°C

n
C

~

(J1
....10

dc electrical characteristics

CO

CD4518BM, CD4520BM (Note 2)

OJ

-55"C
PARAMETER
100

VOL

VOH

VIL

VIH

Quiescent Device Current

Low Level Output Voltage

High Level Output Voltage

Low Level Input Voltage

High Level Input Voltage

CONDITIONS

10L

10H

liN

VOH

High Level Output Voltage

C

(J1

N

VOO = l5V

20

0.01

20

600

IJA

110 1< llJA, VIH : VOO, VIL: OV
VOD: 5V

0.05

0

0.05

0.05

V

VDD = 10V

0.05

0

0.05

0.05

V

VDD=15V

0.05

0

0.05

0.05

V

VDD = 5V

4.95

4.95

4.95

V

VDD = 10V

9.95

9.95

10

9.95

V

VDD = l5V

14.95

14.95

15

14.95

V

1101< llJA
VDD: 5V, Va = 0.5V or 4.5V

1.5

2.25

1.5

1.5

V

VDD = 10V, Va : lV or 9V

3.0

4.5

3.0

3.0

V

VDD: 15V, Va: 1.5Vor 13.5V

4.0

6.75

4.0

4.0

V

1101< llJA
3.5

3.5

2.75

3.5

V

VDD: lOV, Va = lV or 9V

7.0

7.0

5.5

7.0

V

VDD = l5V, Va = 1.5V or 13.5V

11.0

11.0

8.25

11.0

V

VIH = VDD, VIL = OV
0.64

0.51

0.88

0.36

rnA

VDD = 10V, Va: 0.5V

1.6

1.3

2.25

0.9

rnA

VDD = 15V, Va: 1.5V

4.2

3.4

8.8

2.1l

rnA

VIH : VDD, VIL: OV
-0.64

-0.51

-0.88

-0.36

rn'A

VDD: 10V, Va = 9.5V

-1.6

-1.3

-2.25

-0.9

rnA

VDD = 15V, Va: 13.5V

-4.2

-3.4

-8.8

Va = 4.6V

VDD = 15V, VIN: OV

rnA

'-2.4

-0.1

-10- 5

-0.1

-1.0

IJA

0.1

10 5

0.1

1.0

IJA

CD4518BC,CD4520BC (Note 2)

CONDITIONS

MIN

85°C

25°C

MAX

MIN

TYP

MAX

MIN

UNITS

MAX

VDD = 5V

20

0.01

20

150

VDO = 10V

40

0.01

40

300

IJA

VOD=15V

80

0.01

80

600

IlA

IlA

1101 < 1 IlA, VIH = VDD, VIL = OV
VDD = 5V

0.05

0

0.05

0.05

V

VDD = 10V

0.05

0

0.05

0.05

V

VDD = l5V

.0.05

0

0.05

0.05

V

1101 < 1 IlA, VIH = VDD, VIL = OV
VDD = 5V

4.95

4.95

4.95

V

VOD = 10V

9.95

9.95

10

9.95

V

VDD = 15V

14.95

14.95

15

14.95

V

2·219

0

OJ
~

.........

n
C

~

(J1

1101 < llJA, VIH = VDD, VIL = OV

Va = O.4V

~

IJA
IJA

Va : 0.5V or 4.5V

n

150
300

-40°C

Low Level Output Voltage

MAX

10

PARAMETER

VOL

UNITS
MIN

0.01

dc electrical characteristics

Quiescent Device Current

MAX

10

VDD = 15V, VIN = 15V

100

TYP

VOO = 10V

VDD=5V,

Input Current

MIN

P

l25"C

0.01

VDD = 5V,

High Level Output Current

MAX

VOO = 5V

VDD : 5V,

Low Level Output Current

MIN

25'C

N

0
OJ

n

(.)

r::a

o

dc electrical characteristics

(Continued) CD4518BC, CD4520BC (Note 2)

N

-40°C

Lt)

C

(.)

VIL

Low Level Input Voltage

........

= 5V.
= 10V.
VOO = 15V.

Lt)

VOO

VIH

High Level Input Voltage

~

(.)

U
r::a

10L

Low Level Output Current

~

C

(.)

10H

High Level Output Current

~

al
00
~

Lt)

= 5V.

Input Current

~

MIN

UNITS
MAX

= 0.5V or 4.5V
= lV or 9V
Va = 1.5V or 13.5V

1.5

2.25

1.5

1.5

Va

3.0

4.5

3.0

. 3.0

4.0

6.75

4.0

4.0

V
V.'
V

= 0.5V or 4.5V

3.5

2.75

3.5

V

7.0

7.0

5.5

7.0

V

VOO = 15V. Va = 1.5Vor 13.5V

11.0

11.0

8.25

11.0

V

mA

Va

VIH = VO~. VIL = OV
0.52

0.44

0.88

0.36

Voo = 10V. Va = 0.5V

1.3

1.1

2.25

0.9

mA

= 1.5V

3.6

3.0

8.8

2.4

mA

Vo = O.4V

VIH

= VO~.
= 5V.

VIL = OV
Va = 4.6V

Voo = 10V. Va = 9.5V

liN

MAX

3.5

Voo

........

TYP

Va

VOO = 15V. Vo

~

MIN

VOO = 10V. Va = lV or 9V

Voo = 5V.

00

85°C

25°C

MAX

1101< 1 /J.A
VOO

C

MIN

1101< 1 /J.A
VOO

~

al
'0
N

CONDITIONS

PARAMETER

~

VOO

= 15V,

Vo

= 13.5V

VOO

= 15V.

VIN = O\l

VOO

=

-0.52

-0.44

-0.88

-0.36

mA

-1.3

-1.1

-2.25

-0,9

mA

-3.6

-3.0

-8.8

-2.4

-10- 5
10-5

-0.3
0.3

15V. VIN = 15V

mA

-0.3

-1.0

/J.A

0.3

1.0

/J.A

C

(.)

ac electrical characteristics

T A = 25°C, CL = 50 pF, RL =200kn, tr = tf = 20 ns, unless otherwi~e specified.
TYP

MAX

VDO = 5V

325

650

VOO = 10V

110

225

ns

85

170

ns

PARAMETER
tPHL. tPLH

tPHL

tTHL. tTLH

Propagation Oelay Time, Clock .... Q

Propagation Oelay Time Reset .... Q

Transition Time

CONDITIONS

VOO

= 15V

VDD

= 5V

MIN

220

560

ns

90

230

ns

VOO

= 15V

65

160

ns

VOO

= 5V

100

200

ns

50

100

' ns

40

80

VOO = 15V

tWL.tWH

Maximum Clock Input Frequency

Minimum Clock Pulse Width

VOO = 5V

1.5

VOO = 10V

3,0

6

MHz

4.0

8

MHz

VOO

= 5V
= 10V

Von = 15V
Maximum Clock or Enable Rise
and Fall Time

tWH, tWL

tWH

Minimum Enable Pulse Width

Minimum Reset Pulse Width

ns
MHz

3

VOO = 15V

VOO

tRCL. tFCL

ns

VOO = 10V

VOO = 10V

fCL

UNITS

= 5V

100

200

ns

50

100

ns

35

70

ns

15

/J.s

VOO = 10V

10

/J.s

VOO = 15V

5

VOO

/J.s
ns

VOO = 5V

125

250

VOO = 10V

55

110

ns

VOO = 15V

40

80

ns

VOO = 5V

180

375

ns

VOO = 10V

80

160

ns

= 15V

65

130

ns

7.5

pF

VOO
CIN

Input Capacitance

Any Input

5

CPO

Power Oissipation Capacity

Either Counter, (Note 3)

50

pF

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply
that the devices should be operated at these limits. The tables of "Recommended Operating Conditions" and "Electrical Characteristics" provide
conditions for actual device operation.
Note 2: VSS = OV unless otherwise specified:
Note 3: CPO determines the no load ac power consumption of a CMOS device. For a complete explanation, see "54C/74C Family Characteristics,"
application note AN·90.

2·220

n
c

logic diagrams

~

U1

.....

(X)

OJ

~

'-

Decade Counter (CD4518B) 1/2 Device Shown

02

01

OJ

04

n
c

~

U1
.....
(X)

RESET

OJ

f>

n
c

~

U1

N
0

OJ

ENABLE

s:
'-

o-----r-.. . .

n
c

CLOCK

~

U1

N
0

OJ

n

Binary Counter (CD4520B) 1/2 Device Shown

02

01

RESET

ENABLE

0-~----1

CLOCK

2·221

03

04

timing diagram

11 I

2

I

3

I

4

I

5

I

6

I.

7

I

8

i

9

I

0

CLOCK
ENABLE
RESET

C04518B[:~~
03

-+--+---+--'

04 ___-!---+---+--+--+_+--_+_~

C0452DB [

:~
03

-+----'

_+--+---+--..1

04 _+---+---+--+--+_+--_+_~

switching time waveforms

Voo

--+--V----.I

CLOCK
INPUT

ENABLE
INPUT

Vss
Voo --,...+-----+----=-.i.
VSS

_--+_ _ _-+-_ _

Voo

---+----+----+----t----+--"~

VSS

--+-----l----+-----I---..Ti

RESET
INPUT

~:!j_"L.-.rl

o
OUTPUT

2·222

6

7

CD4519BM/CD4519BC 4-bit AND/OR selector
general description

features

The CD4519B is a monolithic complementary MOS
(CMOS) integrated circuit constructed with Nand
P-channel enhancement mode transistors. Depending
on the condition of the control inputs, this part provides
three functions in one package: a 4-bit AND/OR
selector, a quad 2-channel Data Selector, or a Quad
Exclusive-NOR Gate. The device outputs have equal
source and sink current capabilities and conform to the
standard B series output drive and supply voltage ratings.

• Wide supply voltage range
• High noise immunity
• Low power
TTL compatibility

• 5V-l0V-15V parametric ratings
• Symmetrical output characteristics
• Maximum input leakage It.tA at 15V over full
temperature range
• Second source of Motorola MC14519

logic diagram
CONTROL {A
INPUTS
B

Z
OUTPUT

, DATA [X
INPUTS

v o----+-+-L..,

TO THREE REMAINING
SECTIONS

connection diagram
Dual·ln·Line Package
VOO

X3

1,6

Z2

Z3
IS

13

14

zo

ZI
11

12

9

10

r-

r-

I
V3

3

2

X2

V2

S

4

XI

3V to 15V
0.45 VDD typ
fan out of 2
driving 74L
or 1 driving 74LS

VI

II

7

6

VO

XO

VSS

TOPVIEW

truth table
CONTROL INPUTS
A
B

OUTPUT
Zn

0

0

0

0

1

1

·0

1

1

Yn
Xn
Xn

2-223

0

Yn

(,)

CO

en
'I"""

It)

~

Q

(,)
........

~

CO

absolute maximum ratings

recommended operating conditions

(Notes 1 and 2)

(Note 2)

VDD de Supply Voltage
-0.5 to +18 VDC
VIN Input Voltage
-0.5 to VDD +0.5 VDC
-65°C to +150°C
TS Storage Temperature Range
500mW
PD Package Dissipation
300°C
TL Lead Temperature (Soldering, 10 seconds)

VDD de Supply Voltage
VIN Input Voltage
T IA Operating Temperature Range
CD4519BM·
CD4519BC

3 to 15 VDC

o to VDD VDC
-55°C to +125°C
-40° C to +85° C

en
'I"""

It)

~

Q

dc electrical characteristics

CD45198M (Note 2)

(,)
PARAMETER
100

VOL

VOH

Quiescent Oevice Current

Low Level Output Voltage

High Level Output Voltage

MIN

VIH

, Low Level Input Voltage

High Level Input Voltage

Low Level Output Current

High Level Output Current

VOL

VOH

Quiescent Oevice Current

Low Level Output Voltage

High Level Output Voltage

UNITS

1

30

pA

2

60

pA

VOO = 15V

4

0.007

4

120

pA

VOO = 5V

0.05

0

0.05

0.05

V

VOO = 10V

0.05

0

0.05

0.05

V

VOO = 15V

0.05

0

0.05

0.05

V

1101
(")

c

~
N

~

200

400

ns

75

150

ns

50

100

ns

.........
(")

C

200

400

ns

80

160

ns

60

120

ns

175

350

ns

80

160

ns

65

130

ns

225

450

ns

100

200

ns

75

150

ns

100

200

ns

50

100

ns

40

80

ns

OJ

s:

~

N

~

OJ

r>
.(")

c

~

o

CD
CD
OJ

s:

.........

(")

200

ns

100

ns

C

40

80

ns

o

VOO

= 5V
= 10V
= 15V

= 5V
= 10V
VOO = 15V

200

400

ns

100

200

ns

65

125

ns

(")

VOO

75

150

ns

VOO

40

75

ns

25

50

ns

= 5V
= 10V
= 15V

40

80

ns

20

40

ns

15

30

ns

= 5V
= 10V
= 15V

60

120

ns

VOO
VOO

= 5V
= 10V
VOO = 15V

VOO

VOO

VOO

= 5V

30

60

ns

25

50

ns

-15

50

ns

0

30

ns

0

20

ns

-50

15

ns

VOO = lOV

-20

10

ns

= 15V

-15

5

ns

Per Package (Note 3)
Any Input

pF

100
5

2-229

~

CD
CD
OJ

pF
C'N
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply
that the devices should be operated at these limits. The table of "Recommended Operating Conditions" and "Electrical Characteristics" provides
conditions for actual device operation.
Note 2: VSS = OV unless otherwise specified.
Note 3: Oynamic power dissipation (PO) is given by: Po = (CPO + Cl) VCC 2 f + PO; where CL = load capacitance; f = frequency of operation;
for further details, see application note AN-90, "54C/74C Family Characteristics".
Input Capacitance

~

N
W
OJ

100

VOO
Power Dissipation Capacitance

-2.4

-10- 5
10- 5

C

50

VOO

CPO

mA

= 5V
= 10V
VOO = 15V

VOO

tH

2.4
-0.36

s:

.........
(")

VOO

VOO

tsu

8.8

N
W
OJ

VOO

VOO

tH

mA
mA

-0.88

0.30

VOO

Minimum Hold Time Data to E

0.9

3.0

-0.30

VOO = 5V

VOO

tsu

MAX

-0.44
-1.1

-3.6

Propagation Delay Enable to

VOO

tWH

MIN
0.36

0.88
2.25

3.6

-1.3

Output

VOO

tWH,tWl

MAX

TYP

UNITS

-0.52

= 5V
VOO = 10V
VOO = 15V

VOO

tWH,tWL

1.1

VOO

VOO
tTHl, tTlH

1.3

CONDITIONS

VOO
tPLH, tPHL

MIN

~

85°C

T A = 25°C, CL = 50 pF, R L = 200k, Input tr = tf = 20 ns, unless otherwise specified

VOO
tpHL

MAX

0.44

= 15V,.V,N = OV
VOO = 15V, Y,N = 15V

PARAMETER

tPLH, tPHL

25°C

0.52

VOO

ac electrica I characteristics
tPlH, tPHL

MIN

= O.4V
Vo = 0.5V
Vo = 1.5V
Vo = 4.6V
Vo = 9.5V
Vo = 13.5V
Vo

C

(Note 2)

7.5

U
£Xl
en
en

o

logic diagrams
CD4723B

lid'

C
U

.........

~

£Xl

en
en

o

lid'

C
U

c.5

£Xl
lid'
N

t;;:

C
U

.........

~

al
lid'

~C
U

c.5
£Xl

M
N

......

lid'

C
U

.........

~

£Xl
M

N

t;;:
C
U

2-230

logic diagrams

(Continued)
CD4724B, CD4099B

A2

2-231

switching time waveforms
~-------~H--------~

AO,Al,AZ

DATA

CLEAR

00

01

2·232

c

~

C)
(,J

o

"c

~
(,J
C)
(,J

OS1630/0S3630 hex CMOS compatible buffer
general description
features
The OS 1630/0S3630 is a high current buffer intended
for use with CMOS circuits interfacing with peripherals
requiring high drive cur.rents. The OS1630/0S3630
features low quiescent power consumption (typically
50,uW) as well as high·speed driving of capacitive loads
such as large MOS memories. The design of the OS 1630/
OS3630 is such that Vee current
spikes
commonly
found in standard CMOS circuits cannot occur, thereby,
reducing the total transient and average power when
operating at high frequencies.

o

•

H igh·speed capacitive driver

•

Wide supply voltage range

II

Input/output CMOS compatibility

•

No internal transient Vee current spikes

•

50pW typical standby power

•

Fan out of 10 standard TTL loads

equivalent schematic and connection diagrams
Dual·1 n·Line Package
Vee

Vee

14

INPUT

C>-...I\IVv-.---w..".........-O

OUT 6

IN 6

13

12

IN 1

OUT 2

OUT 5

IN 5

11

10

IN 2

OUT 3

OUT 4

IN 4

IN 3

GNO

OUTPUT

OUT 1

TOP VIEW

Order Number DS163OJ, DS3630J
or DS3630N

typical applications
+5V

+5V

t5V

74C
CMOS
FAMILY

74C
CMOS
053630

FAMILY

~~
LINE

CMOS To Transmission Line Interface

CMOS to TTL Interface

V+

74C
CMOS
FAMILY

CMOS To CMOS Interface

LED Driver
·Specifications may change.

3-3

o

M
CD
M

absolute maximum ratings

operating conditions

(Note 1)

(J)

o

MIN

.........

o

M
CD
~

en

o

Supply Voltage
Input Voltage
Output Voltage
Lead Temperature (Soldering. 10 secondsl

l6V
l6V
16V
300°C

Temperature (TAl
051630
053630

MAX

3

15

--55
0

+125
+70

Supply Voltage (VCCl

UNITS
V

-

°c
°c

dc electrical characteristics

(Notes 2 and3)

PARAMETER
IINH

V!N = Vee. lOUT = -400pA
V 1N' = Vee - 2.0V. lOUT = 16 mA

IINL

Logical "0" Input Current

V OH Logical "1" Output Voltage

V 1N = O.4V. lOUT = 16 mA

V 1N = OV. lOUT =.400pA
V 1N = OV. lOUT"' 16 mA
V 1N = O.4V. lOUT = 16 mA

ac electrical characteristics

Vee

PARAMETER
tpdO Propagation Delay to a Logical "0"

tpdl

Propagation Delay to a Logical "1"

= 5.0V. T A

TYP

MAX

UNITS
pA

DS1630

90

200

DS3630

90

200

pA

DS1630

0.5

3.2

mA

DS3630

0.5

DS1630

-0.15

DS3630

V ee -150

1.5

mA

-1

mA

-800

pA

V ce -1
V ee -0.9

Vee-D·75

V

DS3630

V ee -0.75

V

DS1630

V ee -2.5

V ee -2.0

V

DS3630

V ee -2.5

V ee -2.0

V

DS1630
V 1N = Vee. lOUT = -400pA
V 1N = Vee -O.4V. lOUT = 16 mA

VOL Logical "0" Output Voltage

MIN

CONDITIONS

LogicaL"l" Input Current

DS1630

0.75

1

V

DS3630

0.75

0..9

V

DS1630

0.95

1.3

V

DS3630

0.95

1.3

V

DS1630

1.2

1.6

V

DS3630

1.2

1.5

V

= 25°C unless otherwise specified

CONDITIONS

MIN

UNITS

TYP

MAX

C L = 50 pF

30

45

ns

C L = 250 pF

40

60

ns

C L = 500 pF

50

75

ns

C L = 50 pF

15

25

ns

C L = 250 pF

35

50

ns

C L = 500 pF

5.0

75

ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified minimax limits apply across the -SSoC to +125°C temperature ra~ge for the 051630 and across the aOc to
o
+70 e range for the 053630. All typicals are given for Vce = S.OV and T A = 2Soe.
Note 3: All currents into device pins shown as positive. out of device pins as negative. all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.

3-4

c

rn

typical performance characteristics

~

en

w

VOH vs Temperature,
VOH Active vs Temperature

VIN = VCC
D.]

0.4

:= lour'· ~001'~

1.6

. 'V'N

lOUT

1.1

>

~

...
0

0.5
0.6
0.1

:!

0.8

5

0.9

>

..,

,....

.-

u

:>

-

..,

~...

'"
0

:>

a

:>

1.0

=

~ Ve~

0'.4
= 16 rnA _

800

'"
......

~

>

2.1

......

2.2

......
.......

'"

680

'"

600

2.3
1.1
-55 -]5 -15 5

VOL

25 45 65 85 105 125

-55 -35 -15 5

VI

25 45 65 85 105 125

-55 -35 -15 5

TEMPERATURE (OC).

Temperature

tpdo

VI

25 45 65 85 105 125

TEMPERATURE 1°C)

Load Capacitance

Propagation Delay

10
1.6
1.5

Y,N = OV
-16 rnA

'OUT'

60

>-

:J

0

>

j.

1.2
1.1
1.0

~

-

.......

0.9
-55 -]5 -15 5

..,

.....

/

20

25 45 65 85 105 125

;;

......

i

200

300

400

500

I- Vee

/

/

10

V
o

V

."

40

>=

i
200

300

400

11

13

= 5V

lpdO

;;

1/

100

->0

/

/

20

lpd,

r- CL = 250 pF

50

g

/

40

'il

]

-

Vee (V)

Vee =5.0V
I-TA =25'C

30

..........

lpdQ

Propagation Delay
vs Temperature

50

-j

.........

- -

LOAD CAPACITANCE (pF)

tpd1 vs Load Capacitance
60

35

30
100

..........

>=

I"

o

~

0

/1"

TEMPERATURE rC)

I ....

40

."

,/1'

40

30

g

'/

V ......

./

Vce

]

50

1.3

VI

CL =250pFTA =25'C -

45

f- Vee = 5.0V
TA = 25 C

1.4

~

'"

560

TEMPERATURE ( C)

.......

-

I-""

i"'"

30

-

-55 -35 -15 5

500

.......

.-

lpd,_

.......

-

25 45 65 85 105 125

TEMPERATURE rC)

LOAD CAPACITANCE (pF)

ac test circuit and switching time waveforms

INPUT

V'

V'NH---!~=---i
INPUT

OV
OUTPUT

V~----~-,----~
OUTPUT
VOL - - - + '

Cl includes probe and jigcapacilance

Pulse Generator characteristics: PRR" 1.0 MHz, PW ., 500 ns,
V1N

3-5

•

Oto Vee

c

rn

w
en

o

I'..

640

.......

........

w

720

§

I'"

=

= 400pA-

Y,N = OV

760

>

2.0

lOUT

'"

840

......

1.8
1.9

o

VOL vs Temperature
880

.f - tf < 10 ns,

15

CI)

Q)

'C

Q)

CJ)
~

M

(C

M

CJ)

C

""~

M

(C
~

CJ)

C

OS1631/0S3631, OS1632/0.S3632, OS1633/0S3633, OS1634/0S3634
CMOS dual peripheral drivers
general description
The OS1631 series of dual peripheral drivers was
designed to be a universal set of interface components
for CMOS circuits.
-

high impedance OFF state with the same breakdown
levels as when Vee wasapp"lied.
Pin-outs are the same as the respective logic functions
found in the following popular series of circuits:
OS75451, OS75461, OS3611. This feature allows direct
conversion of present systems to the OM74C CMOS
family and OS1631 series circuits with great power
savings.

Eachcircuit has CMOS compatible inputs with thresholds
that track as a function of Vee (approximately 1/2 Vee!.
The inputs are PNPs providing the high impedance
necessary for interfacing with CMOS.
Outputs have high voltage capability, minimum breakdown voltage is 56V at' 2501lA.

The OS1631 series is also TTL/OTL compatible at
- Vee = 5V.

The outputs are Darlington connected transistors. This
allows high current operation (300 mA max) at low
internal Vee current levels since I base drive for the
output transistor is obtained from the load in proportion to the required loading conditions. This is essential
in order to minimize loading on the CMOS logic supply.

features

Typical Vee = 5V power is 28 mW with both outputs
ON. Vee operating range is 4.5V to 15V.
The circuit also features output transistor protection if
the Vee supply is lost by forcing the output into the

schematic diagram

•
•
•

CMOS compatible" inputs
TTL/OTL compatible inputs
High impedance inputs

•
•
•

High output voltage breakdown
56V min
High output current capability
300 mA max
Same pin-outs and logic functions as OS75451,
OS75461 and OS3611 series circuits

•

Low Vee power dissipation (28 mW both outputs
"ON" at 5V)

(Equivalent Circuit)

--------4I.--....

~vcc

r - -....

INPUT

OUTPUT

I

LOGIC
AND LEVEL
TRANSLATION
ELEMENTS

I

"L __ ..J

1/2 of circuit shawn
GND

SEE CONNECTION DIAGRAMS FOR ORDERING INFORMATION

3-6

PNP's

absolute maximum ratings

c

operating conditions

(Note 1)

MIN
5upply Voltage
16V
Voltage at Inputs
-D.3V to V CC +O.3V
Output Voltage
56V
5torage Temperature Range
-65°C to +150°C
Lead Temperature (50Idering: 10 seconds)
300°C

UNITS

053631/0536321
0536331053634

4.5

15

V

4.75

15

V

+125

°c

-55

c

en

w
en

w
en
n>
..,

0

+70

en

°c

(Notes 2 and 3)
CONDITIONS

MIN

TYP

MAX

UNITS

All Circuits
V IH

Logical "1" I nput Voltage

Vec
(Figure 1)

Vec
V IL

Logical "0" Input Voltage

Logical "1" Input Current

IlL

Logical "0" Input Current

V OH

Output Breakdown Voltage

VOL

Output Low Voltage.

= 15V

3.5

2.5

V

8.0

5

V

12.5

7.5

Vee = 5V
(Figure 1)

IIH

= 5V

Vec = 10V

Vee = 15V. V IN

1.5

V

Vee = 10V

5.5

2.0

V

Vec = 15V

7.5

2.5

(Figure2)

= 15V,

J..lA

-50

J..lA

-200

J..lA

65

V

IOL = 100 mA

0.9

V

= 300 mA

1.1

V

IOH = 250J..lA, (Figure 1)

Vee = Min, (Figure 1)

V

0.1

V IN = O.4V, (Figure 3) Vee = 5V
Vee = 15V
Vee

V

2.5

= 15V,

IOL

56

OS1631/0S3631
leclOi

Supply Currents

leell)

tpdl

V IN = OV, (Figure 4)

Propagation to "I"

Vee = 5V

Output.Low

7

mA

Vee = 15V

Both Orivers

14

mA

Vee = 5V, V IN = 5V

Output High

2

mA

7.5

mA

T A = 25°C. CL = 15pF, R L =50n. V L = 10V,

200

ns

Vee = 5.0V, T A = 25°C, C L = 15 pF, RL = 50n, V L = 10V,

150

ns

(Figure 4)

Vee

= 5.0V,

Vec = 15V, V IN = 15V Both Drivers

(Figure 5)

tpdO

Propagation to "0"

(Figure 5)

OS 1632/0S3632
leelo)

5upply Currents

. leell)

tpdl

(Figure 4)

V IN
Propagation to "1"

= OV, (Figure 4)

~ 5V, V IN = 5V
Output Low
Vee = 15V, V IN = 15V

8

mA

18

mA

Vee = 5V

2.5

mA

9

mA

Vee

Output High

Vee ='lSV

Vee = S.OV, T A = 25°C, C L = lSpF, RL = son, V L = 10V,

lS0

ns

lS0

ns

(Figure 5)

tpdO

Propagation to "0"

Vee = S.OV, T A = 2Soc, CL = lS pF, RL = 50n, V L = 10V,
(Figure 5)

OS 1633/0S3633
leelo)

Supply Currents

leell!

tpdl

V IN = OV, (Figure 4)

(Figure 4)

Propagation to "1"

7.S

mA

Vee = lSV

16'

mA

Vee = SV, V IN = SV

2

mA

7.2

mA

Vee

= 5V

Vee = lSV, V IN

Output Low

= 15V

Output High

Vee = S.OV, T A = 2Soc, C L =lSpF, RL = son, V L = 10V,

200

ns

150

ns

(Figure 5)

tpdO

Propagation to "0"

Vee = S.OV, T A = 2Soc, C L = lS pF, RL
(Figure 5)

3·7

= son,

VL

= 10V,

en
w

en

(ii'

053631/053632/
053633/053634

PARAMETER

--

........

5upply Voltage, VCC
051631/051632/
051633/051634

Temperature, T A
051631/0516321
051633/051634

electrical characteristics

MAX

en

G)

·c
G)

electrical characteristics (con't)

tn

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS,

OS 1634/0S3634
lee(o)

Supply Currents

leelll

tpdl

Vee = 5V, VIN = 5V
Vee = 15V, VIN = 15V Output Low

(Figure 4)

VIN = OV, (Figure 4)
Propagation to "1"

Propagation to "0"

Vee = 5V
Vee = 15V

Output High

7.5

rnA

18

rnA

3

rnA

11

rnA

Vee = 5.0V, TA = 25°C, CL = 15 pF, RL = 50n, V L = 10V,
(Figure 5)

150

ns

Vee=5.0V, T A =25°C, CL =15pF, R L =50n, V L =10V,

150

ns

(Figure 5)

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified min/max limits apply across the -55°C to +125°C temperature range for the OS1631. OS1632, OS1633 and
OS1634 and across the O°C to +70°C range for the OS3631, OS3632. OS3633 and OS3634. All typical values are for TA = 25°C.
Note 3: All currents into device pins shown as positive. out of device pins as negative. all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.

test circuits

J;oor

VIH,~,SEE'nr''':"''
'fEST
TABLE

V,L

UNDER

B TEST

TEST
, -!-TABLE
'"

~IOL

VOL

~

, l-=- i-=-

-=INPUT
UNDER
TEST

OTHER
INPUT

LM3611

V 1H
V 1L

V 1H
V '
ec

IOH
10L

V OH '

LM3612

V 1H
V 1L

Y 1H
Y ec

10L
IOH

VOL
V OH

LM3613

V 1H
V 1L

GND
V 1L

10H
IOL

V OH
VOL

LM3614

V 1H
V 1L

GND
V 1L

IOL
10H

VOL
V OH

CIRCUIT

OUTPUT
APPLY

Nole: Each input is tested separately.
FIGURE 1. VIH. VIL. VOH. VOL

Vee

~
_=::::.:. :........:A~.!.Br--JL-...,

V,HO:

IIH

B.A

CIRCUIT
UNDER

TEST

-~
Each input Is tested seplrltely.

FIGURE 2. IIH

3·8

y

~OPEN

MEASURE

VOL

...c
...

en
0)
w

test circuits (con't) and switching time waveforms

........

c

Vee
Vee

OPEN

~B,A

OPEN

;:.11t:'~ J i

Vee

n.....r-tA

I

VO~B
I

I

I

L-----IJ

'::' GNO

BothglteuntesUdsimultaneouslv.
Note A: Elch input is tested separate1v.
Not. B: When testing OSI633 .nd OSI634 input not under test is goound,d. FOlall
other circuits it isat Vee.

FIGURE 4. ICC

FIGURE 3. IlL

INPUT

S.OV

10V

.1-,
OSI631
001632

RL

•

50

Vee" SV

"'-""-0
PULSE
GENERATOR
(NOTE II

GNO
OSI633
OSI634

~
OV

S.OV
INPUT
OSI631
OSI633
OV-----+~~------------------------~~

1---------------O.s"S -----------I~
::;'5.0n5
s.OV----+-+-1~-:---------------------:::::"\I

INPUT
OSI632
OSI634

OV

VOH --------""':"::::"\0

OUTPUT

VOL----------~--~~-------------~----------~

NOli I: Th. pul .. genlllto. hllth. following chlll.toristics: PRR' 500 kHz, ZOUT" 5011.
Nal.l: CL includllprob'lndjigClp.citlnc •.

FIGURE 5. Switching Times.

3-9

OUTPUT

en
w
0)

...w

connection diagrams, truth tables and ordering information

.....
('t)

DS1631

DS1632

Metal Can Package

-Metal Can Package

<0

Vee

('t)

Vee

en
.....
('t)

c

.........

<0
.....
c

en

GNO

GNO
TOP VIEW

TOP VIEW

(Ptn41Selectrically connected to the case.)

(Pin4iselectricallyconnectedtothecase.)

Order Number DS1631H/DS3631H

Order Number DS1632H/DS3632H

Dual·1 n·Line Package
Vee

82

A2

X2

Al

81

Xl

GNO

Dual·ln'·Line Package

Al

82

A2

X2

81

Xl

GNO

TOPVIEW

TOP VIEW

Order Number 3631N

Order Number DS3632N

Dual·1 n·Line Package
Vee

82

NC

Al

81

NC

Dual·1 n·Line Package

NC

NC

A2

X2

Vee

82

NC

NC

NC

Xl

GNO

Al

81

NC

NC

NC

A2

X2

NC

NC

Xl

GNO

TOP VIEW

TOP VIEW

Order Number DS1631J/DS3631J

Order Number DS1632J/DS3632J

Positive logic: AB=X

Positive logic: AB=X

A

B

OUTPUT X

A

B

OUTPUT X

0

0

0

0

0

1

1

0

0

1

0

0

1

0

0

1

1

1

1

1

1

3-10

,-

1
1

0

connection diagrams, truth tables and ordering information
DS1633

DS1634

Metal Can Package

Metal Can Package

Vee

Vee

A2

GND

GNO

TOPVIEW

TOPVIEW

jP11I 4 IS electrically cOllnected to the case.)

(Pin4

Order Number DS1633H/DS3633H

electrically connected to the case.)

Order Number DS1634H/DS3634H

Dual-I n-Line Package

Dual-I n-Line Package

Vee

82

A2

X2

Vee

82

A2

X2

Al

81

Xl

GND

Al

81

Xl

GNO

TOPVIEW

TOPVIEW

Order Number DS3633N

Order Number DS3634N

Dual-I n-Line Package

Al

IS

B2

NC

Bl

NC

Dual-I n-Line Package

NC

NC

A2

X2

NC

NC

Xl

GNO

Al

NC

Bl

NC

NC

TOP VIEW

Xl

TOP VIEW

Order Number DSI633J/DS3633J

Order Number DSI634J/DS3634J

Positive logic: A + B = X

Positive logic:

A+B = X

B

OUTPUT X

A

B

OUTPUT X

A

0

0

0

0

0

1

1

0

1

1

0

0

0

1

1

0

1

0

1

1

1

.1

1

0

3-11

CD
00
CD
M
tIJ

C

.......
CD
00
CD
~
tIJ

C

OS1686/0S3686 positive voltage relay driver
general description
current levels-base drive for the output transistor is
obtained from the load in proportion to the required
loading conditions. Typical Vee power with both
outputs "ON" is 90 mW.

The OS1686/0S3686 is a high voltage/current positive
,voltage relay driver having many features not available
in present relay drivers.
PNP inputs provide both TTL/OTL compatibility and
high input impedance for low input loading.

The circuit also features output transistor protection if
the Vee supply is lost by forcing the output into the
high impedance "OFF" state with the same breakdown
levels as when Vee was applied.

Output leakage is specified over temperature at an output voltage of 54V. Minimum output breakdown (ac/
latch breakdown) is specified over temperature at 5 mAo
This clearly defines the actual breakdown of the device
since the circuit has incorporated in it an ,inter'nal
reference which does not allow output breakdown
latching found in existing relay drivers. Additionally.
this internal reference circuit feature will eliminate the
need in most cases of an external clamping (inductive
transient voltage protection) diode. When the output is
turned "OFF" by input logic conditions the resulting
inductive voltage transient seen at the output is detected
by an internal zener reference. The reference then
momentarily activates the output transistor long enough
so that the relay energy is discharged. This feature
eliminates the need of external circuit protection components and insures output transistor protection.

features

The outputs are Darlington connected transistors. which
allow high current ,operation at low internal Vee

•
•
•

TTL/DTLlCMOS compatible inputs
High impedance inputs (PNP's)
High output voltage breakdown (65V typ)

•

High output current capability (300 mA max)

•

Internal prote'ction circuit eliminates need for output
protection diode in most applications

•
•

Output breakdown protection if Vee supply is lost
Low Vee power dissipation (90 roW (typ) both
outputs "ON")
.

•

Voltage and current levels compatible for use in
telephone relay applications _

connection diagrams
Metal Can Package

Dual-I n-Line Package

Vec

Dual-I n-Line Package
VCC

82

NC

Al

81

NC

NC

, NC

A2

X2

NC

NC

Xl

GND

GND
TDPVIEW

Pin 4 is in electrical c(;mtact with the case

Al

81

Xl

GNO

TOP VIEW

Order Number DS1686H or DS3686H

TDPVIEW

Order Number DS3686N

schematic diagram

Order Number DS1686J or DS3686J

truth table
Positive logic: AS

~

X

A

B

OUTPUT X

0

0

1

1

0

0

1

1
1

1

1

0

~-'-----4~'() OUTPUT

INPUT A

INPUT 8 0 - - + - - I

ZENER
EQUIVALENT

Logic "0" output "ON"
Logic "1" output "OFF"

~--'---~--~------4--oGND

3-12

..
c

absolute maximum ratings

en

operating conditions

(Note 1)

C)

CO
SUJ)J)ly Volt,lge
InJ)lIt Voltage
OutJ)ut VoltJge
Storage Temperature RJnge
Lead Temperature (Soldering, 10 seconds)

7V
15V
56V
65'Cto+150"C
300"C

electrical cha racteristics

MAX

UNITS

4.5
4.75

5.5
5.25

V
V

-55
0

MIN

CONDITIONS

TYP

MAX

UNITS

0.01

40

J1A

2.0

IIH

Logical "I" Input Current

VIL

Logical "0" I nput Voltage

IlL

Logical .. a" Input Current

VCC

= Max,

VCD

Input Clamp Voltage

VCC

= 5V,

VOH

Output Breakdown

VCC

= Max,

VIN = OV, lOUT

IOH

Output Leakage

VCC

= Max,

VIN

VOL

Output "ON" Voltage

VCC = Max, VIN = 5.5V

VIN = OAV

D
ICLAMP = -12 rnA, TA = 25 C

VIN = 2V

Supply Current (Both Drivers)

ICC(O)

Supply Current (Both Drivers)

tpdO

Propagation Delay to a

Logic~1

= OV,

= 5 rnA

VOUT

lOUT = 100J1A

VCC = Min,

ICC(I}

+125
+70

DC
DC

(Notes 2 and 3)

PARAMETER

lOUT = 300J1A

= 54V

VCC = Max, VIN
"0"

= 3V,

V

-250

J1A

-1.0

--1.5

65

V
V

250

0.85

1.1

V

DS3686

0.85

1.0

V

051686

0.95

1.3

V

053686

0.95

1.2

V

2.0

4.0

rnA

18.0

28

rnA

Outputs Open

= 10V, RL = 50n,
VCC = 5.0V

(Output Turn "ON")

TA

Propagation Delay to a Logical "I"

CL = 15 pF, VL = 10V, RL = 50n,

(Output Turn "OFF")

TA

= 25"C,

0.8
-60

0.5

CL = 15 pF, VL

= 25°C,

56

V

DS1686

VCC = Max, VIN = OV, Outputs Open

J1A

50

ns

1.0

J1S

VCC ~ 5.0V

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits_ The table of "Electrical
Characteristics" provides conditions for actual device operation.
D
'Note 2: Unless otherwise specified min/max limits apply across the -55°C to +125 C temperature range for the OS1686 and across the
D
O°C to +70 C range for the OS3686. All typicals are given for VCC = 5.0V and TAco 25°C_
Note 3: All currents into' device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise
noted. All values shown as max or min on absolute value basis.

ac test circuit and switching time 'waveforms
Vl'lDV

PULSE
GENERATOR
(NOTE 11

I

L
I-LT-=

SD

Rl

CIRCUIT
UNDER
TEST

lV

L-_-,-_....J

~

'

Cl'lSPf
INOTE 21

Note 1: The pulse generator has the following characteristics:
PRR = 1 MHz, 50% duty cycle, ZOUT ~ 50n, tr = tf ~ 10 ns.
Note 2: CL includes probe and jig capacitance.

3·13

c

en
CAl

C)

Temperature, T A
051686
OS3686

Logical 'I" Input Voltage

C)

"-

Supply Voltage, VCC
051686
OS3686

VIH

tpctl

MIN

CO
C)

'"co

<.0
M

CJ)

C

,

........

'"co
<.0
~

CJ)

C

051687/053687 negative voltage relay driver
general description

\

allow high current operation at low internal Vee
current levels-base drive for the output transistor is
obtained from the load in proportion to the required
loading conditions. Typical Vee power with both
outputs "ON" is 90 mW.

The OS1687/DS3687 is a high voltage/current negative
voltage relay driver having many features not available
in present relay drivers.
PNP inputs provide both TTL/DTL compatibility and
high input impedance for low input loading.

The circuit also features output transistor protection if
the Vee supply is lost by forcing the output into the
high impedance "OFF" state with the same breakdown
levels as when Vee was applied.

Output leakage is specified over temperature at an out·
put voltage of -54V. Minimum output breakdown (ac/
latch breakdown) is specified over temperature at -5 mAo
This clearly defines the actual breakdown of the device
since the circuit has incorporated in it an internal
reference which does not allow output breakdown
latching found in existing relay drivers. Additionally,
this internal reference circuit feature will eliminate the
need in most cases of an external clamping (inductive
transient voltage protection) diode. When the output is
turned "OF F" by input logic conditions the resulting
inductive voltage transient seen at the output is detected
by an internal zener reference. The reference then
momentarily activates the output transistor long enough
so that the relay energy is discharged. This feature
eliminates the need of external circuit protection com·
ponents and insures output transistor protection.

features
•
•

TTL/DTL/eMOS compatible inputs
High impedance inputs (PNP's)

•
•

High output voltage breakdown (-65V typ)
High output current capability (300 mA max)

•

Internal protection circuit eliminates need for output
protection diode in most applications
Output breakdown protection if Vee supply is lost

•

• ,Low Vee power dissipation (90 mW (typ) both
outputs "ON")
•

The outputs are Darlington connected transistors, which

connection diagrams

Voltage and current levels compatible for use in
telephone r.elay applications

Dual·1 n-Line Package

Metal Can Package

Vcc

82

AI

81

A2

Dual-I n-L ine Package

X2

vcc

GND
TOPVIEW

Pin 4 is in electrical contact with the case
Order Number DS1687H
or DS3687H

OND

AI

81

NC

TOPVIEW

Order Number DS3687N

Order Number DS1687J
or DS3687J

'schematic diagram

truth table

r---.--------o Vcc

Positive'logic:
INPUT A

INPUT B

----+--~~ODUTPUT

50 pF*

= tf:::; 10 ns
PRR = 1 MHz
tr

*Includes probe and jig capacitance

2.5V

J

DIFF
INPUT
-2.5V

Vee
STROBE
INPUT
OV

OUTPUT

3·18

:t>
C

(")

o00
o

o

"'C

ADC0800P(MM4357B/MM5357B) 8-bit AID converter
general description
features
The ADC0800P is an 8-bit monolithic A/D converter
using P-channel ion-implanted MOS technology. It
contains a high input impedance comparator, 256
series resistors and analog switches, control logic and
output latches. Conversion is performed using a successive approximation technique where the unknown
analog voltage is compared to the resistor tie points
using analog switches. When the appropriate tie point
voltage matches the unknown voltage, conversion is
complete and the digital outputs contain an 8-bit complementary
binary word corresponding to the
unknown. The binary output is TR I-ST ATE® to permit
bussing on common data lines.
The ADC0800PD is specified over -55°C to +125°C
and the ADC0800PCN is specified over O°C to +70°C.

•
•
•
•
•
•

Low cost
±5V, 10V input ranges
No missing codes -High input impedance
Ratiometric conversion
TRI-STATE outputs

•
•

Fast
Contains output latches

•
•

TTL'compatible
Supply voltages

•

Resolution

•
•
•

Linearity
Conversion speed
Clock range

5, -12, Gnd
8 bits
±1 LSB/±1/2 LSB
40 clock periods
50 to 800 kHz

connection diagram
Dual-In-Line Package
VOO

18

2- 5
11

LSB

2- 6 .

VREF

16

15

2-)
14

2- B

VIN

12

Il

CLOCK

VSS

10

11

'--

t--

r--

t--

1

2

3

4

5

2- 4

2- 3

2-2

2-- 1

R,
NETWRK

MSB

)

6
STRT
CONV

OUTPUT
ENABLE

B

9

VGG

EOC

TOP VIEW

typical applications
+15V

.5V-+--......,

OV

OV

-12V CLOCK

-12V

lB
OUTPUT ENABLE

AOCOBOOP

SC

CLOCK

11

)

OUTPUT ENABLE
SC
EOC

EOC

3k

-12V

High Accuracy Connection

General Connection

3-19

absolute maximum ratings
Supply Voltage (VDD)
Supply Voltage (VGG)
Voltage at Any Input
Storage Temperature

Operating Temperature
ADC0800PD
ADC0800PCN
Lead Temperature (Soldering, 10 seconds)

VSS- 22V
VSS- 22V
VSS + 0.3V to VSS - 22V
150°C

electrical characteristics
These specifications apply for VSS = 5V

±5%, VGG = -12V ±5%, and VDD
and over O°C to +70°C for the ADC0800PCN unless otherwise specified.
PARAMETER
Non·Linearity

= OV;

CONDITIONS

-55° C to +125° C
O°C to +70°C
300°C

over ±55°C to +125°C for the ADC0800P

MIN

TYP

MAX

UNITS

T A = 25°C. (Notes 3 and 4)

±1

LSB

(Notes 3 and 4)

±2

LSB

0-

Total Unadjusted Error

(Note 3)

±2

LSB

o

....Differential Non-Linearity

(Nott! 3)

±1/2

LSB

o

±2

o

00

Zero Error (Not Adjusted)

(Note 3)

CJ

Zero Error Temperature Coefficient

(Note 1)


o

ADCOSOOP

VREF

IS

100
R2

VIN 1%)

R1 and R2 change the
effective input range by
....._ _ _ _..... 1V/10 kn
14k

-12V

Level Shifted Zero and Full Scale for Transducers
+ISV

10.OOV

Sk
0.1%

.15V -12V

Sk
0.1%

5k
0.1%

ADCDSOOP
Sk
0.1%

Ground Referenced Input Signal

3-23

-m
It)

""'"
M

block diagram

It)

~

:E
m
It)
""'"
M

........

~

:E
:E
Q.

0

0
CO

0

(,)

C


z

0

~

1

....

.

~

0

0.5

n

10

'

1.0

1.5

=+25'C

I

I

:
0

0.4

O.B

1.2

v+ = 35V

~
t.::I

~>

I

\

I
YI V+=10V

\

20

....
....
~

TA = +25"C

16
12
B.O

~

0

4.0

I

\

COllECTOR CURRENT (A)

~-TA

20
TA = 25C

~ ~ -"""(>-

,

:

Response Time

' ,I

....

>

1.0

20

JT A = -55'C

rr-T

I
I

BASE EMITTER VOL TAGE (V)

Response Time
40

-

-O.B -0.4

85 105 125

TEMPERATURE ( C)

2.5

0.5

-1.0

.3

COllECTOR VOLTAGE (V)

~

I

CD
CJ'I

COLLECTOR CURRENT (A)

Base Emitter Voltago

1.2

0

i
0.4

1.4

0.8

~

TA ' +125"C,

COLlECTOR·EMITTER VOLTAGE (V)

>

....

1.2

0.8

35

1.0

~

~"

I

iii

1

~

:;

TA I, -WC

~

c(

s:W

-:}....>('"
~
~

~-

0.4

5.0

Quiescent Current

i

a:
a:

1.6

u

en

2.8

<"

TA ,+125°C

<"
....
z

.3

r-

= +25 JC

2.0

~

.........

L

TO·3
2.0

COLlECTOR·EMITTER VOLTAGE (V)

..s

2.4

1.5

CD
U1

Bias Current

2.5

1.0
TIME

3-29

2.0
(~s)

3.0

0.4
TIME

0.8
(~S)

1.2

40

typical performance characteristics (con't)
36V Transfer Function

10V Transfer Function
2.0 ,......:...,....--.--,---.---.--.,.-.....,....----,

~

1.6

1.2

~
z
a:
a:

z

UJ

1.2

0.8

J

TA=+125j

:::>

u

a:

a:

B 0.8
e

~ A = 1+25o J

I

I

I-

I-

~

I

V~ = 3~V

~+--t--t-l----A-::t,t=::t=~

II

e

I-

u

UJ

0.4

u

I

II II

7

e

0.4 ~+--+--I+-I+-I-+

I

~I

TA =

-wc

J

j) )
0.4

1.2

0.8

0.4

1.6

:£

~TA=+25°C
~ f= 50 kHz

3.0

T)+;1,,1
~ -200

....

~ -100

UJ

u

V

z

I
g

1.0

0.3

1=

g~

-

III -I
m P~ASE

lli;#v
.,.

Ie = 1.0A

~

15

Gi
-20

T

""z
We
a:
u

0.1
0.01

0.1

1.0

~

-10

wet

===~

IF = O.lA

lT~~~O.;A

~~

r=

/

1.6

1.2

Small Signal Frequency
Response

Transconductance
10

0.8

BASE·EMITTER VOLTAGE (V)

BASE·EMITTER VOLTAGE (V)

10

lOOk

COLLECTOR CURRENT (AI

1.0M

10M

FREOUENCY (Hz)

schematic diagram
COLLECTOR

03
6.3V

04
6.3V

R22

0.1

EMITTER

3-30

BASE

R21
3D

typical applications
C4

r-------------4~--.15V

A,

10k

As

10k
INPUT -'V\,."......-

.......;~

'--''V'II'''''''"....- -...-

..... OUTPUT

AJ
470
'SOLID TANTALUM

.....--------~~---15V
C5"

~1.0~F

1.0 Amp Voltage Follower

Rl
5.0k"

-

....- -....-.15V

...- -......--EMITTER

BASE-""',..,.......- - f
OUTPUT

500pF"
02
LM195

01

LM195

.....--+--COLLECTOR
"PROTECTS AGAINST EXCESSIVE BASE DRIVE
"NEEDED FOR STABILITY

Time Delay

Power PNP

1~~-""'----------'

v'

30V~""'----------------'

AI,

510k
R2
.........- - - - - - - - - - - + - O U T P U T

150k

Rl
1.5k
01

LM195
01

1003

R3
47k

lN914

1.0 MHz Oscillator

BULB

1.0 Amp Lamp Flasher

3·31

typical applications (con't)

l -..._____-

__

-O~~:~T

1.0A

R2
2.4k

L-----________~~-----VtSOLIO TANTALUM

1.0 Amp Negative Regulator
V,N
36V

1.0 Amp Positive Voltage Regulator

---~....- +

OUTPUT

Ql
LM195

Rl
lOOk

--~------'---V-

Optically Isolated Power Transistor

Fast Optically Isolated Switch

--4I~-40V

Rl
40

ORIVE'

'DRIVE VOLTAGE OV TO;: 1.0V ::;42V

CMOS or TTL Lamp Interface

Two Terminal Current Limiter

3·32

40V Switch

r.s:
..a

to

typical applications (con't)

U1

.......

r-

s:N

Rs

VOUT

Y'N

01
5.0V

to

U1

02
LM195

.......
r-

s:W

01

Cl

to

50pF

6.0V Shunt Regulator with Crowbar

U1

Two Terminal 100 mA Current Regulator

12V

...--4.....-J\JIIAr-....- OUTPUT

02
LM195

Ul
LM195

.---~..- OUTPUT

T· RIC
R2" 3Rl

TURN ON ' 350 mV
TURN OFF, 200 mV

R2~82k

Low Level Power Switch
Power One-Shot

---+--+15V
Rl
5.0k"

Cl

01
LM195

INPUT

-1

H .....v..I'v-+f

01
LM195

OUTPUT

+
R2
200k

!---t--OUTPUT

R4
30
50W
--+---15V

"NEED FOR STABILITY

. High Input Impedance AC Emitter Follower

Emitter Follower

- -....- V +
Rl
5.0k

01
LM195

INPUT "".-'\fV\I""'4~1-f

OUTPUT

V"PREVENTS STORAGE WITH FAST FALL
T1ME S~UARE WAVE DRIVE

Fast Follower

3·33

typical applications (con 't)
R,
lOOk

R2

'0'

OUTPUT

RS

RI

10k

10k

-15V

Power OpAmp
v·

36V-1>--------..,

Rl

zoo
R9
01

lGO

l',.,,33

3.9V

"SIXTY TURNS VYOUNO ON ARNOLD TYPE A 0830812 CORE

"FOURDEVICESINPAAAllEl

tSOLIO TANTALUM

6.0 Amp Variable Output Switching Regulator

3-34

MM5369,17-stage programmable oscillator/divider

general description

features

The MM5369 is a CMOS integrated circuit with 17
binary divider stages that can be used to· generate a
precise 60 Hz reference from commonly available high
frequency quartz crystals. An internal pulse is generated
by mask programming the combinations of stages 1
through 4, 16 and 17 to set or reset the individual stages.
The programmable number the circuit will divide by can
vary from 10000 to 98000. The MM5369 is advanced
one count on the positive transition of each clock pulse.
Two buffered outputs are available: the crystal fre·
quency for tuning purposes and the 17th stage 60 Hz
output. Mask options are available for use with com·
monly available,. low cost, high frequency crystals.·
Therefore, th is design can be "customized" by special
order to design specific programmable divider limits
whereby the maximum divide·by can be 98,000 and
the minimum divide-by can be 10,000. The MM5369 is
available in an 8-lead dual-in-line epoxy package.

•

Crystal Oscillator

•

Two buffered outputs
Output 1 cyrstal frequ~ncy
Output 2 full division

connection diagram

•

High speed (4 MHz at V DD = 10)

•

Wide supply range 3-15V

•
•
•

Low Power
Fully static operation
8 lead dual-in-line package

•

Low current

Standard MM5369N Only
•

3.58 MHz (color TV oscillator) input fr.equency

•

60 Hz output frequency

block diagram

Dual-In-Line Package
TURNER
OUTPUT DSC OUT DSC IN

Voo

Is

6

1

5
DSC OUT

2

1
DIVIDER

(60 Hz)
OUTPUT

DIVIDER
OUTPUT

r-

r-

Vss

J
Nc

14

FIGURE 2_

Nc

TOP VIEW

FIGURE 1.
Order Number MM5369N

See Package 17

4-3

absolute maximum ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Package Dissipation
Maximum V ccVoltage
Operating V cc Range
Lead Temperature (Soldering, 10 seconds)

-0.3V to Vee +0.3V
O°C to +70°C
-65°C to +150°C
500mW
16V
3V to 15V
300°C

electrical characteristics
T A within operating temperature range, Vss = GND, 3V

PARAMETER

~

Voo::;: 15V unless otherwise specified.

MIN

CONDITIONS

Quiescent Current Drain

TYP

Voo=15V

MAX

UNITS

10

I1A

2.5

.mA

Operating Current Drain

Voo= 10V, fiN = 4.19 MHz

Frequency of Oscillation

Voo=10V

DC

4.5

MHz

Voo= 6V

DC

2

MHz

Output Current Levels

1.2

Voo=10V
VOUT = 5V

Logical "1" Source
Logical

"a" Sink

500

I1A

500

I1A

~

Output Voltage Levels

Voo= 10V

10 = 10 I1A
Logical "1"

V

9.0

Logical "0"

1.0

V

functional description
A connection diagram for the MM5369 is shown in
Figure 1 and a block diagram is shown in Figure 2.

DIVIDER
A pulse is generated when divider stages 1 through 4, 16
and 17 are in the correct state. By mask options, this
pulse is used to set or reset individual stages of the
counter, thus varying the modulus of the counter from
10000 to 98000. Figure 4 shows the relationship
between the duty cycle and the programmed modulus.

TIME BASE
A precision time base is provided by the interconnection
of a 3,579,545 Hz quartz crystal and the RC network
shown in Figure 3 together with the CMOS inverter/
amplifier provided between the OSC IN and. the OSC
OUT terminals. Resistor R 1 is necessary to bias the
inverter for class A amplifier operation. Capacitors Cl
and C2 in series provide the parallel load capacitance
required for precise tuning of the quartz crystal.

OUTPUTS
The Tuner Output is a buffered output at the crystal
oscillator frequency. This output is provided so that the
crystal frequency can be obtained without disturbing the
crystal oscillator. The Divide Output is the input frequency divided by the mask programmed number. Both
outputs are push-pull outputs. A typical application of
the MM5369 is shown in Figure 5.
.

The network shown provides> 100 ppm tuning range
when used with standard crystals trimmed for C L · =
12 pF. Tuning to better than ±2 ppm is easily obtainable.

4-4

s:

s:

functional description (cont.)

U1

w
en

to

110
100
90

-OSCOUT

~

..
'"
>
0

:;
Ci

C2
30pF

VOO OR Vss

80
70
60
50

,

1

r-"SJAND~RD" ~M53~9N- ~

~

..... 10'

-~

40
3D
20
10

V

~

0
I0

2~

3D

40

-

........

50

~.
,,/

60

70

DUTY CYCLE (%)

FIGURE 3. Crystal Oscillator Network

FIGURE 4. Plot of Divide·By Vs Duty Cycle

FIGURE 5. Clock Radio Circuit with Battery Back·Up

2.5
2.0

E 1.5

~

!::!

g

1.0

b=

==lI

26.815 ---J-o--- 32.184
COUNTS
COUNTS
1-------59.659COUNTS-------1

0.5

MHz

FIGURE 6. Typical Current Drain Vs Oscillator Frequency

FIGURE 7. Output Waveform for Standard MM5369

*To be selected based on xtal used

4·5

MM5393 push button telephone dialer
general description

features

. The MM5393 is a monolithic metal gate CMOS integrated
circuit which provides all logic required to convert a
push button input to
series of pulses suitable for
simulating a telephone dial. Storage is provided for 21
digits, therefore, the information is retained after the
call is completed and the number is available for redial.
Entering a new number simply overrides the previous
one. An interdigital pause can be externally selected
as either 415 ms or 830 ms. A muting output is suppHed
to mute receiver noise during outpulsing, and a 600 Hz
tone is activated every time a key is depressed.

a

connection diagram

iii

21-digit storage

•

Selectable interdigital pause

•

Redial of last number

•
•

600 Hz tone
Line powered operation

Dual-In-Line Package
18

K4

03

17 02

Kl

16

K2

15

K3

14

HOOK SWITCH

01

lOP SelECT
'
TON.

13

OSC 1

VOO
12

OSC2

Vss

11 MUTE

OSC 3

10

DIAL PULSE

NC

TOP VIEW

Order Number MM5393N
See Package 20

block diagram
voo

VSS

r----------------l---l----------,
I

I

Kl
K2

READ
LOGIC

21 X4RAM

KJ

I
I
I

K4

--------

I
I

01
02

OUTPULSING
LOGIC

DECODER

I
I
I
I

OJ

--------

I

READ AND WRITE
CONTROL COUNTERS

MAIN CONTROL
LOGIC

I
I
I

I

HO~KSWITCH- lOP DETECT

-MUTE-60iiH,TO";E- -

-

-

-

SELECT

-

-

.

-

-

-

-- -

T-T - T

_.J

OSC 1 OSC2

4-6

OSC 3

!ITAI
PUm

absolute maximum ratings
Voltage at Any Pin
VSS - 0.3V to VOO -l- O.3V
-30°C to +65°C
Operating Temperature Range
-40°C to +70°C
Storage Temperature Range
6V max
VDO - VSS
Lead Temperature (Soldering, 10 secondsl
300°C

electrical characteristics
PARAMETER

TA within operating temperature range, Vss
CONDITIONS

=

Gnd, 2V:::; VOO:::; 5.5V

MIN

TYP

MAX

UNITS

Input Voltage Levels
Logical "1"

VOO-G·25

Logical "0"

VSS

Output Current Levels
Oial Pulse
Logical "1"
Logical "0"
Mute
Logical "1"
-Logical "0"
Tone
Logical "1"
Logical "0"
01,02,03
Logical "1"
Logical "0"

V

VOD
VSS+0.25

150

V

pA
pA

VOD = 3V, VOUT = VOO - 0.5
VOD = 3V, VOUT = VSS + 0.5

150

VOO = 3V, VOUT =VOO -'0.5

100

VOD = 3V, VOUT = VSS + 0.5

100

VOO = 3V, VOUT = VOO - 0.5

10

pA

VOD = 3V, VOUT = VSS + 0.5

10

pA

VOO = 3V, VOUT = VOO - 0.5
VOO = 3V, VOUT = VSS + 0.5

20
150

pA
pA

pA
pA

functional description
KEYPAD DATA INPUTS

The time base for the MM5393, is an RC controlled
oscillator nominally tuned to 20 kHz. This is successively divided to provide timing signals for the various
counters. The keyboard inputs, K l-K4, in conjunction
with the scan counter outputs, 01-03, indicate the
presence of a particular key depression. If only one
key is detected for 5 ms, the decoded key will be loaded
into the RAM. The push button inputs are accepted at
an asynchronous rate, loaded into a first-in-first-out
memory, and outpu I~ing of the correct number of
pulses begins immediately after the first digit is entered.
After the first digit has been completed, outpulsing will
cease unless another key has been entered. This allows
use in a PBX system to ensure receipt of a. dial tone
before entering the remainder of the number_ If the call
was not successful, it can be redialed at a later time by
pressing the redial key (#1. If an access code is required
as in a PBX system, it can be entered, the dial tone can
be established, then the redial key can be pushed. Only
one key can be 'entered before pushing the redial key
because after the second key entry, the memory is
erased. A block diagram of the MM5393 is shown in

Keypad closures cause the connection of 2 of 7 switch
contacts arranged as a matrix (shown' in Figure 21Key closures are protected from contact bounce for
5 ms.

IMPULSING MARK-TO-SPACE RATIO
The mark-to-space ratio is 1.6: 1 (61.5% to 38.5%1.

IMPULSING OUTPUT
The number of pulses will correspond to the input
digit. For example, key 5 will generate 5 pulses. The
outpulsing rate is 10Hz, and it can be varied by
adjusting the frequency of the oscillator. Because it is
intended to drive a transistor buffer, the outpulsing data
is inverted. Oigits are separated by an interdigital pause
which is pin programmable for either 415 ms or 830 ms.

Figure 1.

4-7

I

switching time waveforms
KEYBOARO SCAN
01--u

u

02

uI---

03

~ 150 ~s

U-

--I

KEY CLOSURE (3) - - - - . . ,

NTEROIGITAL PAUS~

~

1--100 ms-I

415 ms OR 830 ms
(PIN PROGRAMMABLE)

Note. All times are based on a 20 kHz oscillator.
FIGURE 1

keypad matrix
I

!/

~

l./

Kl

!/

~

~.

K2

!./

!/

1/

KJ

0./

=,/

01

02

K4

03

FIGURE 2

typical application

Proposed Interface

PHONE LINE

10M*

25k *
0.11 ~F

*

[
K4

Vss
HOOKSWITCH
OETECTOR

*Components added to existing network

PHONE LINE

FIGURE3

4-8

MM5395 TOUCH TONE® generator
.~

general description
The MM5395 is an integrated circuit that can provide
all tone frequency pilirs required for the TOUCH
TONE® telephone dialing system. The output frequen·
cies are generated by programmably dividing the
frequency of the on-chip crystal-controlled oscillator;
thus, accurate output· frequencies can be obtained
without tuning. The only external compcnent needed
for the oscillator is an inexpensive 3.579545 MHz
crystill.
The device has four row and four column inputs. Inputs
to the device can either be in a 2-out-of-8 code format
from a keyboard, or by BCD signals to the row inputs.
The device is fabricated using our low voltage CMOS
process so that it may be powered directly from the
telephone line.

Interfilce with single contact low-cost keypad option
Multi·key lockout with single tone capability

•

On·chip high bandilnd low band tone generators and
mixer

•
•

High bilnd pre-emphilsis
Low hilrmonic distortion

•

Accurate tone frequencies

•

Open emitter, emitter follower output

•
•

Mute switch output
Ciln be powered directly from the telephone line

functiona I descri ption
The functionill block diagram of MM5395 is shown in
Figure 1. The device can be operated in Keypad Interface Mode or Signal Interface Mode (BCD into row
input) depending on the logical level at "Control"
input. In either mode, the MM5395 will digitally syn:
thesize the high and/or low band sine waves when valid
signals are applied to row or column inputs. The sum of
the two sine waves is then provided at the "Tone
Output." The base of the output NPN transistor is
brought out ("F I LTE R") for easy filtering. Operational
functional features are summarized in tables.

The MM5395 is designed to be used in a wide variety of
tone signaling ilnd data transmission applications.

features
• 3V to 5V supply
• On-chip 3.579545 MHz crystal·controlled oscillator
•

•
•

Interface with stilndard telephone keypad

block diagram

PROGRAMMABLE DIVIDER
46
42·

33
34
DD

[3f;

CONTROL
XMIT

\

MIXER

R1
R2
R3
R4

KEYBOARD
lOGIC
PROGRAMMABLE DIVIDER
CONTROL
lOGIC

C1
C2
C3
C4
1..-_ _ _ _ _ _ _ _ _........_ _...... MUTE

FIGURE 1

4-9

TONE
OUTPUT
FILTER

absolute maximum ratings
Voltage at Any Pin
Operating Temperature Range
Storage Temperature Range
VDD - VSS
Lead Temperature (Soldering, 10 seconds)

VSS- 0.3V to VOD + 0.3V
-40°C to +70°C
-65°C to +150°C
6V
300°C

electrica I cha racteristics
T A within operating temperature, ~V ~ VDD - VSS ~ 5V, unless otherwise specified.
PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

VIN = VSS

100

400

kn

. VIN= VDD

WO

400

kS2

VIN ='VSS

100

400

VIN = VDD

100

400

kn
kn

Logical "1"

VDD-D·25

Logical!' 0"

VSS

VDD
VSS+0.25

Input Pull·Up Resistor

Column Inputs

@

Input Pull-Down Resistor
Internal Resistor

@

@

"Xmit",

Row Inputs

To VDD (Option A)
To VSS (Option B)
Input Voltage Levels

Output Voltage Swings

@

"TON E

OUTPUT"

V
V

VDD - VSS = 3.0V.
RL> 500n

Low Band Only

820

High Band Only

1000
RL ~ 500n,

Harmonic Distortion

mVp-p
mVp-p
-20

dB

No External Filtering
Tone Frequency Deviation

1.0

Operating Frequency

3.579545

%
MHz

Key-Down Debounce Time

7

11.35

ms

Key-Up Debounce Time

4

7.15

ms

Power Dissipation

30

VDD - VSS = 6V.

mW

RL = 500n
Output Current Level

@

"MUTE"

VDD - VSS =3.0V

Logical" 1"

VOUT = VDD - 0.2V

Logical "0"

VOUT = VSS + 0.5V

20
. 2.0

..

functional description

(Continued)

TABLE I. Interface Mode Control

CONTROL

XMIT

o

Open

1

o

1

1

INTERFACE MODE

Keypad
Idle
}BCD Signal
Send tones e.g. MM5393

4·10

Il A
mA

functional description

s:
s:

(Continued)

(J1

w

CD
(J1

TABLE. II. Keypad Interface
(a). Functional Truth Table

ROW

)

HIGH BAND

LOW BAND

COLUMN

NOlle

None

DC

DC

Olle

One

fL

tH

None

Olle

DC

fH

One

None

DC

Two or more

None

fL
DC

Two or more

One

'DC

ttl

DC

None

Two or more

DC

DC

One

Two or more

tL

DC

(b). Output Frequencies

INPUTS

DESIRED

ACTUAL

FREQUENCIES

FREQUENCY

fL (Hz)

PERCENT
DEVIATION

(Hz)

fH (Hz)

R1

697

-

699.1

0.306

R2

770

-

766.2

-D.497

R3

852-

-

847.4

-D.536

R4

941

-

948.0

0.741

C1

-

1209

1215.9

0.569

C2

-

1336

1331.7'

-D.324

C3

-

1477

1471.9

-D.35

1633

1645.0

C4

0.736

TABLE. III. Functional Truth Table for Signal Interface

C1

XMIT

C2

R1

R2

R3

R4

FREQUENCIES
GENERATED
fL (Hz)
fH (Hz)

0

X

X

X

X

X

X

DC

DC

1

Open

Open

0

0

0

0

941

1336

1

Open

Open

0

0

0

1

697

1209

1

Open

Open

0

0

1

0

697

1336

1

Open

Open

0

0

1

1

697

1477

1

Open

Open

0

1

0

0

770

1209

1

Open

Op(:n

0

1

0

1

770

1336

1

Open

Open

0

1

1

0

770

1477

1

Open

Open

0

1

1

1

852

1209

1

Open

Open

1

0

0

0

852

1336

1

Open

Open

1

0

0

1

852

1477

1

0

Open

fL

DC

1

Open

0

DC

fH

1

0

0

DC'

DC

Valid BCD Inputs

4·11

typical applications
Standard Telephone Keypad

Ct

Voo

C2
Cl
C4
Rt

R2

RL

TONE
OUTPUT

C,
Rl
FILTER

200

CONTROL

Vss
OSC OUT
ROW

Vss

COLUMN

TERMINALS

Single Contact Keypad

RINGEBX

Ct

Voo

5.tk

C2
Cl
C4
Rt

R2

Rl
MUTE

./

~

~
I

ROW

I

...;;./

R4

c,
OSC OUT
CTRL Vss

COLUMN

4·12

200

connection diagram
Dual-In-Line Package

Vss
OSC

IN

NC

MUTE
C4
C3

Cl

C2

TOP VIEW

Order Number MM5395N

See Package 20

4-13

MM53100, MM53105 programmable TV timers
general description

features

The MM53100 and MM53105 programmable TV timers
are monolithic CMOS integrated circuits utilizing P and
N-channel low threshold enhancement devices. These
circuits contain all the logic to give a 4 or 6-digit, 24hour display from a 50 or 60 Hz input, and control the
"ON" time of the TV. The duration of the viewing
period is '5, 10, 20 or 30 mins, selected by 2 input
pins. Manual "ON" and "OFF" inputs are also provided.
The MM53100 and MM53105 have ultra-low power
dissipation in the stand-by mode and are ideally suit'ed
to crystal controlled battery-operated systems. The
MM53100 is designed for an optimum interface in
TVs with a positive common reference voltage (e.g.,
+18V). The MM53105 is designed for an optimum
interface for TVs with a OV reference voltage. Both are
packaged in a 24-lead dual-in-line epoxy package.

• 50 or 60 Hz operation
• 24-hour display format
• Programmable TV on time'
• Selectable view time
• Ultra-low power dissipation
• All counters resettable
• Low voltage operation
• Elimination of illegal time display at turn-on
• Daily repeat or non-repeating operating
• Fool-proof safety features
• Compatible with MM5840 or MM5841 display circuits'

applications
•
•

TV time display
Remote TV "ON"/"OFF" switch

•
•

Computer clock
Time data-logging systems

block diagram
50160 Hz
SELECT

SET
MINUTES

HOLD

SET
HOURS

Dz
D~~~~~~

_ _ _ _ _ _ _ _ _ _ _ _....

MAN "ON"
MAN"OFF"-'
STANDBV-.
MULTIPLEXED
BCD alPs

FIGURE 1_ MM53100, MM53105 Block Diagram

4·14

t--------.

TV "ON" alP

t--------+ AUTO "ON" alP
t - - - - - - - - + VIEW PERIOD alP

absolute maximum ratings

(MM53100) (VOO common voltage reference)

Supply Voltage (Voo - VSS)
Voltage at 50/60 Hz Select and Period
Select Inputs
Current Into or Out of Any Other Input

6V
VSS - 0.3V to VOO + 0.3V

electrical characteristics

~
~

U1

...
Co\)

0

?

100 f.lA max

~
~

(MM53100) T A = 25°C, Voo = 4.5V, VSS = OV unless otherwise specified.

...

U1

PARAMETER

MIN

CONOITIONS

Supply Voltage

TYP

2.8

Supply Current

VOO = 4.5V

10

MAX

UNITS

5.0

V

25

f.lA

Input Logic Levels
50/60 Hz Input,

~igit

Select

Inputs, Oisplay Select, "ON",
"OFF", Time Setting Control,
Standby Control
Logic "1"

VOO-0.5

Logic "0"

(Note 1)

VOO

V

VSS+0.5

V

50/60 Hz Select, Period Select
(X, Y)

Logic "1"

VOO-0.5

VOO

V

Logic "0"

VSS

VSS+0.5

V

0.5

2.0

f.lS

Oisplay Select Input Oelay
Output Logic Levels
BCO Outputs

External Resistor, 15

kn

to

VOO - 12V, CL = 15 pF
Logit "1"

VOO-0.8

V

Logic,"O"

VOO-11.2

V

Note 1: If input voltages go more negative than VSS, the input current must be limited to a maximum of 100 jJA by the use of external series
resistors. No resistors are required on the OX, Oy, Oz inputs when interfacing with the MM5840.

absolute maximum ratings

(MM53105) (VSS common voltage reference)

Supply V91tage (VOO - VSS)
Voltage at 50/60 Hz Select and Period Select Inputs
Voltage at Any Other Pin

electrical characteristics
PARAMETER

6V
VSS + 6V
VSS + 13V

(MM53105) TA = 25°C, VOO = 4.5V, VSS = OV unless otherwise specified.
CONDITIONS

Supply Voltage

MIN

TYP

Supply Current

10

VOO = 4.5V

MAX
5.0

2.8

UNITS

V

25

pA

Input Logic Levels
50/60 Hz Input,

~igit

Select

Inputs, "ON", "OFF", Oisplay
Select, Time Setting Controls,
Standby Control
Logic "1"

VOO-D·5

13

V

Logic "0"

VSS

VSS+0.5

V

V

50/60 Hz Select, Period Select
(X, Y)

Logic "1"

VOO-0.5

VOO

Logic "0"

VSS
0.5

VSS+0.5

V

2.0

ps

Oisplay Select Input Oelay

4·15

Co\)

0

U1

electrical characteristics

(Continued) (MM53105) TA

PARAMETER

= 25°C,

CONDITIONS

VDD

= 4.5V,
MIN

VSS = OV unless otherwise specified.
TYP

MAX

UNITS

Output Logic Levels
External Resistor 15 H2 to 12V,

BCD Outputs

CL = 15pF
Logic "1"

11.2

Logic "0"

V
0.8

V

TV "ON" Output, Auto
"ON" Output. View Period
Output
Logic "1"

Loaded 2.7 kil to VSS

0.5

mA

Logic "0"

Loaded 2.7 kil to VDD

1.0

mA

Note 1: Input voltages to go .:nore positive than VOO.

functional. description
50 or 60 Hz Select Input: This input programs the
prescale counter to divide by either 50 or 60 to obtain a
1 pps time base. The counter is programmed for 60 Hz
operation by connecting this input to VDD. An internal
1 Mil pull-down resistor is common to this pin; simply
leaving this input unconnected programs the clock for
50 Hz operation.

A block diagram of the MM53100, MM53105 TV timers
is shown in Figure 1. A connection diagram is shown in
Figure 2. Unless otherwise indicated, the following
discussions are based on Figure 1. Figures 5a and 5b
illustrate the system configuration for a crystal controlled
TV display system using both circuits.
Dual-In-Line Package, Top View
VDD

--!.

u

24

f--

Ox

BCD 8.2.

~Dy

BCD4..2.

~DZ

BCD2

-!

21
f-- 50/60 Hz SELECT

BCD 1

.2.

20
--- 50/60 Hz DRIVE

STANDBY...!.

.!.!.. HOLD

..

~ SET HRS

7

ENABLE -'-

~~~~~~ ...!
PE~:~~ ...J.
AUTO "ON"

.!2... SET MINS

r1!- DISPLAY CONTROL

Display: This input controls the display and timesetting operation. It has an internal 1 Mil pull-down
resistor to VSS. When taken to Logic "0" or in open
circuit condition, the real time is displayed and the Set
Hours and Set Minutes inputs operate the real time
counters. When taken to logic "1", the "ON" time is
displayed and the time-setting inputs operate on the
"ON" counters.

~ MAN "OFF"

..!.!!.

~ MAN "ON"

PERIOD 11
SELECT xPERIOD
SELECT Y

Time Setting Inputs: Inputs to set hours and set minutes
as well as hold input, are provided. Internal 1 Mil
pull-down resistors provide the normal timekeeping
function. Switching any 1 of these inputs (1 at a time)
to "1" results in the desired time setting function. Set
Hours advances hours information at 1 hour/second and
Set Minutes advances minutes information at 1 minute!
second, without rollover into the hours counter. Set
Minutes also resets the seconds counter to O. The hold
input stops the clock to the minutes counter and resets
the seconds counter. Activating Set Minutes and Set
Hours simultaneously resets the displayed counters
to alia's.

.E. L...-_ _ _ _ _ _- '~VSS
FIGURE 2.

Orde.r Number MM53100N or MM53105N
See Package 22

Digital Select Inputs (OX, Dy, DZ): These 3 inputs are
used to determine which digit will be displayed. Table IA
shows the code for each digit. Seconds will be displayed
as "00" when the "ON" time is being displayed.

50 or 60 Hz Drive: This input is applied to a Schmitt
trigger shaping circuit which allows use of a filtered
sinewave input. A simple RC filter should be used to
remove possible line voltage transients that could either
cause the clock to gain time or damage the device. The
input should swing between VSS and VDD. The shaper
output drives a counter chain which performs the timekeeping function.

Enable: This input has an internal resistor to VSS.
When taken to logic "1", this input disables the programmed "ON" time for the TV output.
Period Select Inputs (X, V): These inputs have pulldown resistors to VSS. They determine the view period,
i.e., 5, 10, 20 or 30 mins. Table IB shows the Period
Select Code.

Alternatively, in a crystal controlled battery operated
system, an oscillator and prescaler such as the MM53107
could be used as a time base.
4·16

functional description

(Continued)
period, a signal on the manual "ON" input will prevent
the automatic switch·off.

Standby Control Input: This input has an internal
resistor to Vss. Its function is to sense when the line
generated 12V supply is turned off and to then disable
the outputs. In the TV, th is input should be connected
to the 12V supply.

Manual "OF F" input will always reset the output to a
logic "1" state.
Auto "ON" TV Output: An 1 or c/>2

=Yl =VCC
=GND
VCC = 15V

VOL

Output Low Level, c/>1 or c/>2

VCC=15V

ICC

Quiescent Current
Operating Current

VCC

Output Sink Current, c/>1 or c/>2

VCC = 15V, Vo = 1.5V

PARAMETER
TR

MAX
600

15
14.95

= 15V, Vo = 13.5V

Output Source Current, c/>1 or c/>2

IOL

VCC

TYP

= 15V, CL = 15 pF, all
CONDITIONS

UNITS
J1.A
mA
V

0.05

IOH

ac electrical characteristics

MIN

Xl
Yl

-7.0

V
mA

11.0

mA

limits apply across te!f1perature.
MIN

Rise Time of c/>1 or c/>2

TYP

MAX

15

30

ns

UNITS

TF

Fall Time of c/>1 or c/>2

15

30

ns

TPW,c/> 1+

Positive Pulse Width of c/>1

410

455

510

ns

TPW,c/>l-

Negative Pulse Width of c/>1

470

520

570

ns

TPW,c/>2+

Positive Pulse Width of c/>2

510

570

600

ns

TPW,c/>2-

Negative Pulse Width of. c/>2

380

410

470

ns

TW,c/>2-

Effective Negative Pulse Width

405

440

ns

of c/>2
TdLl

c/>1 Overlapping c/>2 Time

-13

5

ns

TdL2

c/>2 Overlapping c/>1 Time

-2

10

ns

Vall

c/>1 Cross-Overc/>2 Voltage

VCe-1.0

VCC

V

VOL2

c/>2 Cross-Over c/>1 Voltage

VCC-2.0

VCe-O. B

V

Note 1: "Absolute Maximum Ratings" are those values beyond which t'he safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.

4-20

timing diagram

X1
X2

.......

~1

..J

~2

1 ..._---'

'---_

L

ac test circuit

2k

T2-

~

5V--.
OV

-

• 1

.

T1-

MM53104N

T1 = 145 ns
T2 = 135 ns
tr = tf = 20 ns
CL = 15 pF including scope probe and all stray capacitances.
Note: When the MM53104 is used with the MM57100
and LM1889, the 4.5 MHz oscillator in the MM53104
is not needed and thus pin 3 should be grounded.

switching time waveforms

PULSE
GENERATOR

~1

Vee -----,,1

~'IIF
Tpw~1--'1 t-o,----TPW,~2O.5V

~ GND

I','

1--------TPW:¢2+
Note: tr

= tf = 20 ns

TW,~2-------~
Tpw,~1+---------I

4·21

MM55104, MM55106, MM55114, MM55116 PLL frequency synthesizer
general description
frequency, and qNCO provides a low level voltage (sinks
current) when the VCO frequency is higher than the
lock frequency. The qNCO output goes to a high impedance (TRI·STATE@) condition under lock conditions,
and the lock detector output LD goes to a high state
under lock conditions.

The MM55104 and MM55106 devices. contain phase
locked loop circuits useful for frequency synthesizer
applications in C.B. transceivers. The devices operate
off a single power supply and contain an oscillator,
a 2 10 or 211 divider chain, a binary input programmable
divider, and phase detector circuitry. The devices may
be used in double I.F. or single I.F. systems. The
MM55104, MM55114, MM55106 and MM55116, use a
10.24 MHz or 5.12 MHz quartz crystal to determine the
reference frequency. The MM55106 and MM55116 have
an output pin which provides a 5.12 MHz signal, which
may be tripled for use as a reference oscillator frequency
in two crystal systems. Also, the MM55106 provides an
additional input to the programmable divider which
allows 29 - 1 division of thf:l input frequency (FIN).
The inputs to the programmable divider are standard
binary signals. Selection ofa channel is accomplished by
mechanical switches or by external electronic programming of the programmable divider.

features
• Single power supply
• Low power CMOS technology
• Binary input channel select code
• 5 kHz or 10kHz output from oscillator divide
• 5.12 MHz output (MM55106 and MM55116 only)

The -------t::
>----=---125

HORIZONTAL
POSITION
AOJ.

TIMEOUT MONOSTABLE

...- - - - f >

;J---~ 26

POSITION
NC

27

NC

28

I-~....-'V~_.AOJ.
+12V

NC
OIGIT SELECT +12V FOR 8 DIGIT
GNO FOR 5 OIGIT
MOOE CONTROL +12V:NODRFC::~~!~:ENLOOT~~~

>-----.....
>-_________--'
4-29

o
~

typical applications (Continued)

11)

~
~

TV Channel and Time Display Interfacing MM53100
12V
VDU

VDD

I

60 Hz

mil

20

~

VDD
20M

MM53107
HOLD

3V

mlz

3 ml4

...1...

2 mil

SET HRS

24
23
22

SErMINS

Ox
Dy
DZ

9V
MANUAL TV "ON"

MANUAL TV "OFF"
MM53IDO'
OISPLAYSELECT
12V
ENABLE
12V

STANDBY
50160H,
SElECT

PERIOD
SElECT X

NORMALLY
HARD WIRED
FOR EACH
APPLICATION

PERIOD
SElECT Y

TV"ON"
OUTPUT
21

AUTO "ON"
OUTPUT

11

VIEW PERIOO
PULSE OUTPUT
12
13

9V

VSS
IV

VDD
6.Sk
15
VIDEO
OUTPUT

":"

llfiIlov
18 t-:::":::':'--+-""""4~J,I"""~~--<12V
HORIZ.

Uk

JUl

":"
19

CHANNEl
UNITS

TENS
"gm

[

r
t

VERT.

22
23
24

18 I---~~"'ot-....., HORIZONTAL
I'OSITION

25

17

28

21

t--4-,y.,7Ir.... A~J.
t - - - -........M--. VERTICAL
I'OSITIDN

Z7

20

1--4-~'Iv-""" ADJ.

21

+12V

I

DIGIT SElECT 12V FOR .·DIGIT
GND FOR 5·DIGIT
MODE CDNTRDl12V FOR CHAIINEl AND TIME
GND FOR CHANNEl ONL Y

Note. For interfacing with MM53105. refer to MM53105 specifications.

4-30

MM5841 TV channel number and time readout circuit
general description
The M M5841 TV Channel Number and Time Readout
Circuit is a monolithic metal gate CMOS integrated
circuit, which generates a display of channel number
and time readouts on the television screen.

A 7·segment decoder is used to decode either channel
inputs or time which is stored temporarily in the channel
number buffers or 4 bit latches, respectively, depending
on the time slot of the display. Each digit of time is
stored in a 4·bit latch while it is being decoded and
displayed, and the next digit enters the latch whi Ie the
horizontal sweep is between digits.

This chip includes all the logic required to provide two
modes of operation, namely channel number, or channel
number and time displays.

,I

A time slot decoder is employed to decode the appro·
priate time slot and the digit to be displayed. It
generates a video output signal that modulates the sweep
of the television tube for the display on the screen.

In addition, it can have a five (hour tens, hour units,
colon, minute tens, and minute units) or eight digit
(hour tens, hour units, colon, minute tens, minute units,
colon, second tens, and second units) display, depending
on the digit select input logic level.

, features
This chip serves as a display generator between
BCD channel inputs, the clock chip (MM5318) and
television set. The position of the display on the
screen can be controlled by adjusting the external
time constants.

the
the
TV
RC

functional description
The channel numbe~ and time readout circuit operates'
with a 4 MHz input clock. Counters are incorporated in
the chip, operated by the input clock to keep track of
the time slots of the display. '

•

12 or 24 hour operation (controlled by clock chip)

•
•

5 or 8 digit display
Channel number leading zero blanking

•
•

Single power supply
Channel number only or channel number and time
display

functions
•

The position of the display is controlled by adjusting the
external RC time constants of the horizontal and
vertical monostable multivibrators.

•

8 digit mode is selected by a logic "1" at digit select
input
Channel number and time mode is selected by a
logic "1" at mode input

connection diagram
Dual·1 n·Line Package
CHANNEL TENS
~
(2)
(1)

(4)

CHANNEL UNITS
(8)

(4)

(2)

(1)

Rv

Cv VERT HORIZ CH

TOPVIEW

Order Number MM5841 N

See Package 23

4·31

RH

VIDEO
OUT

absolute maximum ratings
Supply Voltage (V oo - V ss )
Voltage at Any Pin
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)

-O.3V to +15V
Vss - O.3V to Von + O.3V
O°C to +70°C
-55°C to +150°C
300°C

electrical characteristics
Voo = 12V, Vss = OV, unless otherwise specified.
PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Power Supply Voltage
Voo

Vss = 0

11

12

Power Supply Current

14
800

Input Voltage Levels
Time, Oscillator, Digit Select,
and Mode Inputs
Logical Low
Logical High

V
/1A

V ss --D·3
Voo-O.5

Vss
Voo

Vss+0.9
Voo+0.3

V
V

Channel Inputs
Logical Low
Logical High

V ss --D·3
Voo-0.5

V oo -5

V oo -4.5
Voo+0.3

V
V

Horizontal and Vertical Inputs
Logical Low
Logical High

Vss--D·3
V oo --D·5

V oo -5

V oo -4.5
Voo+0.3

V
V

Input Frequency
Oscillator
Horizontal
Vertical

One·Shot Output Pulse Duration
Horizontal
Vertical
Output Drive
Video Output
Logical Low
Logical High
Oscillator Inhibit Output
Logical Low
Logical High

Voo

1

4
15.75
60

4.5

Vss-0.3
Voo-0.5

Vss
Voo

Vss+0.9
Voo+0.3

V
V

50
13

/1S
ms

Pulse Width = 14/1s
Pulse Width = 1 ms

Output Voltage Levels
Oscillator Inhibit, Digit Address
and Video Outputs
Logical LoW
Logical High

Voo

15
1.5

MHz
. kHz
Hz

Vss + 1.0V
Voo -1.0V

1-11
1

rnA
rnA

Output Forced Up to Voo - 4.5V
Vaa - 1.0V

1-21
0.2

rnA
rnA

External RC
0.1
0.001
50
100

CVERTICAL
CHORIZONTAL
RVEFlTlCAL
RHORIZONTAL
Propagation Delay
Oscillator Inhibit Output

/1F
/1F
kn pot
kn pot

2

clock
pulses

Input Leakage

1

pA

Input Capacitance

5

pF

From I nput Clock to Oscillator
Inhibit Output

4-32

block diagram
HORIZONTAL
PULSE

VERTICAL
PULSE

CHANNEL

TIME

4MHz
CLOCK

OIGIT AOORESS
OUTPUTS

OSC INHIBIT
OUT

VIDEO OUT

timing diagram
1-1---,---------16.7 ms------------11

,

I~----------ILI
U

VERTICAL-'
RETRACE

VERTICAL--:-"1
XAOJUSTABLE
TIMEOUT
~

u

HORIZ, RETRACE

U

!f-------63,5"S---------I!

'--__:+_-'
---'!=== ~15"s ---LI______________
~------------------~/I~----~

HORIZ, TIME
OUT

ADJUSTABLE

asc INHIBIT______________

nnn

CLOCK
4MHz _ _ _ _ _ _ _ _ _ _ _ _ _IUUI______

nn__________________

~IUI

nnn_____________
IUUI

VIOEO
OUTPUT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
CHARACTER
DlSPLAYEO

typical applications
-I......---.-..----.--~V+

r-l

J+

14
RETRACEU
INPUT

I

I
INPUT
CONFIGURATION
FOR CHANNEL
INPUTS A~O
CONTROL INPUTS

}

{

OUTPUT
CONFIGURATION
FOR OSC INHIBIT,
VIDEO OUTPUT,
OIGIT SELECT

RETRACE
INPUT

V2

I

I
Horizontul and Vertical One-Shot Circuit

4·33

typical applications (con't)
0.01

+12V

t

BCD 1

15
19

14
S.8k

BCD 2
BCD 4

18
MM5318

2

15

BCD 8

VIDEO
OUTPUT

':"

JUUl ov

10

18

~----I--""...JW\r-""'_--<
HDRIZ.

+12V

S.8k

JlJ1~

____==~____~~

12

':"

13

19
MM5841

VERT.
VERTICAL
RETRACE

""""" ~
CHANNEl
UNITS

'""'"
TENS

[~

[:
4

':"

22
23
16

24 ,
25

17

26

21

27

20

VERTICAL
POSITION
AOJ.

28
+12V

8'
DIGIT SELECT +d~~ ~~~: ~:~:~ ~

HORIZONTAL
POSITION
AOJ.

____.....J

MODE CONTROL +12VriNO; FCOHRA~~!~:~lD OT~~~ ~_ _ _ _ _ _ _ _ _...J

TV Channel and Time Display

4·34

MM58106 digital clock and TV display circuit

general description

features

The MM58106 is a monolithic CMOS integrated circuit
which generates a display of channel number and time
on the television screen. The circuit can either display
channel number (2-83) or program number (1-16).
Time display can be 4 or 6-digit, in either 12 or 24-hour
mode. Timekeeping is controlled from a 50 Hz or
60 Hz input. The position of the display on the TV
screen is controlled by adjusting the external RC time
constants.

•
•
'.
•
•
•

Single chip clock and display
12 or 24·hour operation
5 or a-digit time display
Channel or program number display
50/60 Hz operation
Channel and time display on channel change

The circuit is packaged in a 28-lead dual-in-line epoxy
package.

\

connection diagram

block diagram

HORIZONTAL
PULSE

VERTICAL
PULSE

EDGE
DETECT

CHANNELS
(8)

SET

SET

Dual·ln·Line Package

HR HOLD MIN

21 VERT

RV
12/%4HR

27 DIGIT SEl

Cv

21 DSC INHIBIT

vOD
CTI
CHIPROG SEL
CUI
VIDEO OUT
VSS
CU4

CTI 12

cn

17 12/%4 HR

13

15 HOLD

CUI 14
OSCILLATOR
INHIBIT

VIDEO
OUT

11 EDGE DETECT

TOP VIEW

FIGURE 2

FIGURE 1

Order Number MM58106N

See Package 23

, 4-35

.

absolute maximum ratings
Supply Voltage (VOO - VSS)

5.5V

Voltage at Any Pin

VSS - O.3V to +5.5V
O°C to +70°C

Operating Temperature
Storage Temperature

-55°C to +150°C

Lead Temperature (Soldering, 10 seconds)

electrical characteristics

300°C

Voo = 5V,

vss = OV, unless otherwise specified

PARAMETER

CONOITIONS

Power Supply Voltage, VOO

MIN
4.75

VSS= 0

TYP

MAX

5

5.25

V

800

J.lA

Power Supply Current

UNITS

Input Voltage Levels
Channel Inputs
Logical Low

VSS-o·3

VOO-5

VOO-4.5

V

Logical High

VOO-o·3

VOO

VOO+0.3

V

Logical Low

VSS-o·3

VOO-5

VOD-4.5

V

Logical High

VOD-o·3

VDD

VDO+0.3

V

VSS-0.3

'!SS
Open

VSS+0.3

V

Horizontal and Vertical Inputs

Set Mins, Set Hours, Hold, 12/24·Hour

Internal Pull·Up Resistor to

Select, 50160 Hz Select, Channell

VDO (600k Min)

Program Select
Logical Low
Logical High
All Others
Logical Low

VSS-0.3

VSS

VSS+0.3

V

Logical High

VDD-o·3

VDD

VOD+0.3

V

Input Frequency
4 MHz Clock

1

4

Horizontal

Pulse Width = 14 J.lS

15.75

Vertical

Pulse Width = 1 ms

60

4.5

MHz
kHz
Hz

Output Voltage Levels
Oscillator Inhibit and Video Output
Logical Low

VSS-o·3

VSS

VSS+0.9

V

Logical High

VDD-o·5

VDD

VDD+O.3

V

One-Shot Output Pulse Ouration
Horizontal

50

J.lS

Vertical

13

ms

Output Drive
Video Output
Logical Low

VSS + lV

Logical High

VOO-1V

H)

mA

1

mA

(-2·)

mA

Oscillator Inhibit Output
Logical Low

Output Forced Up to VOD-4.5V

Logical High

VOO-1V

0.2

rnA

External RC
CVERTICAL

0.1

CHORIZONTAL

0.001

RVERTICAL

J.lF
J.lF

100

\

kn pot
kn pot

100

RHORIZONTAL
Propagation Delay Oscillator Inhibit

From Input Clock to Oscillator

Output

Inhibit Output

2

clock pulses

Input Leakage

1

p.A

Input Capacitance

5

Edge Oetect Pulse Duration

C = 2 JlF., R = 1 Mn -

4-36

2

pF
sec

func~ional

~
~

description

U1

A block diagram of the MM5Bl06 TV timer is shown in
Figure 1. A connection diagram is shown in Figure 2.
Unless otherwise indicated, the following discuss.ions are
based on Figure 1.

Display Control: The channel number and time display
circuits operate from the 4 MHz input clock frequency.
The horizontal and vertical position of the display is
controlled by adjusting the external RC time constants
(RH, CH, RV, CV);

50 or 60 Hz Input: This input has a shaping circuit
which allows using a filtered sinewave input. A simple
RC filter such as shown in Figure 4 should be used to
remove possible line voltage transients that could either
cause the clock to gain time or damage the device.
The input should swing between VSS and VDD. The
shaper output drives a counter chain which performs
the timekeeping function.

These monostables are triggered by the horizontal and
vertical retrace signals as shown in the timing diagram in
Figure 3 ..
A 7-segment decoder is used to decode either channel
inputs or time. Also a time slot decoder is employed to
decode the appropriate time slot and the digit to be
displayed. It generates a video output signal that can
modulate the sweep of the television tube for the onscreen display.

Alternatively, in a crystal controlled battery operated
system, an oscillator and prescaler circuit such as the
MM5369 could be used as a timebase.
50 or 60 Hz Select Input: This input programs the
prescale counter to divide by either 50 or 60 to obtain
a 1 pps timebase. The counter is programmed for 60 Hz
operation by connecting this input to VSS. An internal
1 Mil pull-up resistor is common to this pin; simply
leaving this input unconnected programs the clock for
50 Hz operation.

Channel/Program Number Select: This control pin has
a pull-up resistor to VDD and, with the input open,
the chip will accept a binary plus 1 code on the CU1 to
CUB inputs and display the program number. For
example, an input code of 0000 will indicate channel 1
and 1111 will indicate channel 16.

Time Setting Inputs: Inputs to sethours and set minutes
as well as a hold input, are provided. Inter~al 1 Mil
pull-up resistors provide the normal timekeeping function. Switching anyone of these inputs (one at a time)
to "0" results in the desired time setting function.
Set Hours advances hourS' information at 1 hour per
second, and Set Minutes advances minutes information
at one minute per second, without roll over into the
hours counter. The hold input stops the clock to the
minutes counter and resets the seconds counter.

With this input at "0", inputs CU1 to CUB and CTl to
CT8 will accept BCD inputs for channel units and
channel tens respectively, and display channels 2-83.
Edge Detect: On program change, the time and number
will be displayed for a period depending on the external
capacitor and resistor connected to the Edge Detect pin
(Figure 4).

r·~-------16.1 ms---------11

~~~~~~____u~------------------------~f.f---1.-U
VERTICAL - - - ,
TIME OUT

4

~

HOR~i~~~~~ ----.....,U

f

~

~-----63.6ps------i1

1-1

HOR~~~~6~~------"L-.J

f~

11-________

OSCI~~~J~~ ____________~I
f---16
Ci~~~

pi ---j

_______.......Jrum..:..:.:.::.. . . ._______________
nnn

VIOEO OUTPUT
CHARACTER
IUUI
DISPLAYED - - - - - - - - - - - - - - - - ----------

/2:·L/3: 57

FIGURE 3. Timing Diagram

4·37

....
o

CO

en

typical applications
5V

1M

!lO/GO Hz S VIIIII-W'v-<'-''''''''-'--!

TO TV
VIDEO OUTPUT
CIRCUIT

..f!!olllOV
O;.::U.:.;.TP.::.UT:....._ _....._ _ _

SV

Z3 t--t-......-'VVV......
FROM TV

! - -.......JVVV-HORIZONTAL
RETRACE

Uk

MM511D6

28

FROM TV

t - -.....-'VVV-VERTICAL
RETRACE

\

DIS'LAY
oFF

l

CHANNEL { ;
UNITS
4

Z4t---......-II~....,

10

'8

CHANNEL { ;
TENS
4
I

DIGITSELECT
5V-10IGITS
GNO-~ DIGITS

'ROGRAM/CHANNEL SELECT
5V-PROGRAMS (EUROPEAN)
GND-CHANNELS

5V

FIGURE 4.

J'

RETRACE
INPUT

I
INPUT
CONFIGURATION
FOR CHANNEL
INPUTS AND
CONTROL INPUTS

{

Vl---U,,~

OUTPUT
CONFIGURATION
FOR OSC INHI8IT.
VIDEO OUTPUT,
DIGITSELECT

}
-

U

I

~

V-

FIGURE 5. Horizontal and Vertical One-Shot Circuit

4·38

HIGH RELIABiLITY CMOS
For years, National's products have been acknowledged
as among the most reliable available. It is only natural,
therefore, that National should be committed to the
Military/Aerospace semiconductor market, where reliability is of paramount importance. In the forefront of
our Hi-Rei product line, our CMOS devices (both 4000
series and 54C series) are available with a wide range of
screening options tailored to meet all levels of user
needs. In addition. to the basic flows shown on the
following pages (and ANY of our Mil-grade CMOS
devices can be screened to any of those flows), we
also offer Rad-hardened CMOS (lx10 6 rads SO, SEM
acceptance, and numerous other special tests. Regardless
of your screening needs, whether you have designed
around A series, 8 series, or 54C, we have what you
need. And, since we can meet those needs with standard
flows, we 'can 'meet them economically. We can also
offer these devices, at the ch ip level, for use in hybrid
circuits, with screening on a sample basis, if required.

National offers the following screening options (detailed
in the following tables):

1. Hermetic devices
a. Class 8 (as defined by Method 5004 of Mil-Std883). We offer both 38510 class 8 flow (which
includes read-and-record) and -8838 (which has
only go-no-go screening). These flows are ideal
for systems where retrievability and replaceability
is not a vital consideration, but where a failu re
rate of less than 0.001%/1000 hours is desirable.
b. Class A (as defined by Method 5004 of Mil-Std883). We offer both the conventional -883A flow
and a flow equivalent to that called out by the
CMOS Mil-M-38510 detail specifications (that is,
three burn-ins, with read-and-record). These flows
should be used for manned space flight, nonretrievable hardware, or any other systems where
failure rates of less than 0.01%/10 6 hours are
ess~ntial.

2. Commercial (molded) devices
a. A+, designed for the user of commercial products
who would like the additional assurance of a 100%
burn-in at extremely low added cost.
b. 8+, which affords the user, for only pennies per
unit, a 90% reduction in failure rate.

JAN (1)

JAN Processed (1)

883B

3 TEMP DC &
25°C AC SCREEN
PER SLASH SHEET

3 TEMP DC &
25°C AC SCREEN
PER SLASH SHEET

3 TEMP DC &
25°C AC SCREEN
PER NSC RETS (2)

TABLE 2. Class B Burn-in Flows

Noto 1: JAN is a registered trademark and can be used only to indicate parts processed 100% to the requirements of Mil-M-3851 0 and
the applicable detail specification. JAN-processed material meets all of the requirements of the applica~le slash sheet, except that parts
are assembled in our offshore facility. The applicable part marking would be as follows:
JAN
"" 27014 JM38510/05603BCB 7650 U.S.A.
JAN-proc
"" 27014 CD4020AJ/05603BCB 7650 U.S.A.
Note 2: The RETS (an acronym for REL Electrical Test Specification) is a one-page document which translates into data sheet format
the contents of our standard test tapes, RETSs are available from our sales office.
Noto 3: Post burn-in read-and-record is required only when post burn-in electrical testing is not performed within 24 hours of the
. completion of burn-in.

RADIATION HARDNESS
(AS REQUIRED)

SEM
(AS REQUIRED)

STD
PRODUCT

SHIP

CONTINUOUS
OP LIFE
MONITORING
BY RELIABILITY
ASSURANCE
DEPT

QUALITY CONF'ORMANCE
(AS REOUIRED)
(SEE TABLE 4)

25°C DC TO
0.65%
AQL
ESTERNAL VISUAL

SHIP

SHIP
TABLE 1. Product Flows

Note 4: On the class A flows, SEM is performed, and a certificate of conformance is provided certifying to the wafer lot acceptance
requirements of Mil-Std-883 Method 5007. Class A flows may be obtained without SEM upon special request.

4-40

JAN Processed (5)

883A

R&R
PER SIS

[]

STATIC I BURN·IN
24 HRS
R&R PER SIS
to CALCULATION
STATIC II BURN·IN
24 HRS

10%
POA

R&R PER SIS
to CALCULATION

BURN·IN
240 HRS

DYNAMIC BURN·IN
240 HRS

0

R&R PER SIS
t. CALC 5% PDA

3 TEMP DC
SCREEN PLUS
AC AT 25°C
TO RETS

"3TEMPDC
SCREEN PLUS
AC AT 25°C
TO SLASH SHEET

TABLE 3. Class A Flows
Note 5: For the class A flows, inspection lot formation is on a metallization run basis.

Accepted
Criteria

Group B - every 6 weeks per generic familylpackage type combination
Subgroup 1

Physical Dimensions per Method 2016

2 units/O rejects

Subgroup 2

Resistance to Solvents per Method 2015
I nternal Visual & Mechanical per Method 2014
Bond Strength per Method 2011, Condition D

3 units/O rejects
1 unit/O rejects
25 bonds/1 reject

Subgroup 3

Solderability per Method 2003

15 leadslO rejects

Group C - every 90 days per generic family
Subgroup 1

Operating Life per Method 1005 (1000 hrsI125°C)
Electrical End Points

Subgroup 2

Temp Cycle, Method 1010, Condition C, 10 cycles
Constant Acceleration, Method 2001, Condition E
Fine and Gross Leak per Method 1014
Electrical End Points

77 units/l reject

j

15 ,units/O rejects

Group 0 - every 6 months per package type
Subgroup 1

Physical Dimensions per Method 2016

15 units/O rejects

Subgroup 2

Lead Integrity per Method 2004, Condition B2
Fine and Gross Leak per Method 1014

15 units/O rejects

Subgroup 3

Thermal Shock per Method 1011B, 15 cycles
Temp Cycle per Method 1010C, 100 cycles
Moisture Resistance per Method 1004
Fine and Gross Leak per Method 1014
Visual Examination per Method 1010
Electrical End Points

Subgroup 4

Subgroup 5

} ""'''il "'00'

Mechanical Shock per Method 2002, Condition D
Vibration Variable Frequency per Method 2007, Condition A
Constant Acceleration per Method 2001, Condition E
Fine & Gross Leak per Method 1014
Visual Examination
Electrical End Points
Salt Atmosphere per Method 1009,
Visual Examination

~ondition

A

TABLE 4. Quality Conformance Testing, Class A or B

4-41

} 15 ,,""' ",."

A+ PROGRAM
A+ Program: A comprehensive program that utilizes
National's experience gained from participation in the
many Military/Aerospace programs.
A program that not only assures high quality but also
increases the reliability of molded integrated circuits.
The A+ program is intended for users who cannot
perform incoming inspection of ICs or does not wish
to do so, yet needs significantly better than usual
incoming quality and higher reliability levels for his
standard integrated circuit.
.
Users who specify A+ processed parts will find that the
program:
•

Eliminates incoming electrical inspection.

•

Eliminates the need for, and thus the added cost of,
independent testing laboratories.

•

Reduces the cost of reworking assembly boards.

•

Reduces field failures.

•

Reduces equipment down time.

•

Reduces the need for excess inventories due to yield
loss incurred as a result of processing performed at
independent testing laboratories.

The A+ Program Saves You Money
It' is widely accepted fact that down-time of equipment
is costly not only in lost hours of machine usage but also
costly in the repair and maintenance cycle. One of the
added advantages of the A+ program is the burn-in
screen, which is one of the most effective screening
procedures in the semiconductor industry. Failure rates
as a result of the burn-in can be decreased many times.
The objective of burn-in is to stress the device much
higher than it would be stressed during normal usage.
Reliability vs_ Quality
The words "reliability" and "quality" are often used
interchangeably, as though they connoted identical
facets of a product's merit. But reliability and quality
are different, and IC users must understand the essential
difference between the two concepts in order to evaluate
properly the various vendors' programs for products
improvement that are generally available, and National's
A+ program in particular.
The concept of quality gives us information about the
population and faulty IC devices among good devices,
and generally relates to the number of faulty devices
that arrive at a user's plant. But looked at in another
way, quality can instead relate to the number of faulty
ICs that escape detection at the IC vendor's plant.
It is the function of a vendor's Quality Control arm to
monitor the degree of success of that vendor in reducing
the number of faulty ICs that escape detection_ Quality
Control does this by testing the outgoing parts on a
sampled basis. The Acceptable Quality Level (AQL) in

turn determ ines the stringency of the sampling. As the
AQL decreases it becomes more difficult for defective
parts to esc,ape detection, thus the quality of the shipped
parts increases.
The concept of reliability, on the other hand, refers
to how well a part that is initially good will withstand
its environment. Reliability is measured by the percentage of parts that fail in a given period of time.
Thus the difference between quality and reliability
means the ICs of high quality may, in fact, be of low
reliability, while those of low quality may be of high
reliability.
Improving the Reliability of Shipped Parts
The most important factor that affects a part's reliability
is its construction: the materials used and the method
by which they are assembled ..
Reliability cannot be tested into a part. Still, there are
tests and procedures that an IC vendor can implement
which will subject the IC to stresses in excess of those
that it will endure in actual use, and which will eliminate marginal, short-life parts.
I n any test of reliability the weaker parts will normally
fail first. Further, stress tests will accelerate, or shorten,
the time of failure of the weak parts. Because the
stress tests cause weak parts to fail prior to shipment to
the user, the population of shipped parts will in fact
demonstrate a higher reliability in use.
National~s

A+ Program

National has combined the successful B+ program with
the Military/Aerospace processing~ specifications and
provides the A+ program as the best practical approach
to maximum quality and reliability on molded devices.
The following flow chart shows how we do. it step by
step.
SEM
Randomly
production
analysis.

selected wafers are taken
regularly and subjected to

from
SEM

Epoxy B Seal
At National, all molded semiconductors. including
ICs. have been built by this process for some time
now_ All processing steps. inspections and QC
monitoring are designed to provide highly reliable
products. (A reliability report is available that
gives. in detail. the background of Epoxy B, the
reason for its selection at National. and reliability
data that proves its success.)
Six Hour, 150°C Bake
This stress places the die bond and all wire bonds
into a combined tensile and shear stress mode, and

helps eliminate
connections.

marginal

bonds and electrical

Five Temperature Cycles (OOC to 100°C)
Exercising the circuits over 100°C temperature
range further stresses the bonds and generally
eliminates any marginal bonds missed during" the
bake.
Electrical Testing
Every device will be tested at 25°C for functional
and DC parameters.
Burn-in Test
Devices are stressed at maximum operating conditions to eliminate marginal devices. Test is performed per Mil-Std-883A Method 1015_'_
High Temperature (100°C) Functional Electrical
Test
A high temperature test with voltages applied
places the die under the most severe stress possible.
The test is actually performed at 100°C - 30°C
higher than the commercial ambient limit. All
devices are thoroughly exercised at the 100°C
ambient.
DC Functional and Parametric Tests
These room-temperature functional and parametric tests are the normal, final tests through
which all National products pass_
Tighter-than-Normal OC Inspection Plans
Most vendors sample inspect outgoing parts to a
0.65% AOL Some even" use a looser 1% AOL.
When you specify the A+ program, however, not
only do we sample your parts to a 0.28% AOL
for all data-sheet DC parameters, but they receive
0.14% AOL for functionality as well. Now functional failures - not parameter shifts beyond spec
- cause most system failures_ Thus, the five-times
to seven-times tightening of the sampling procedure
(from 0.65% to 0_14% AOL) gives a substantially
higher quality to your A+ parts. And you can rely
on the integrity of your received I Cs without
incoming tests at your facility.
Ship Parts

Here are the OC sampling plans used in our A+ test
program:
TEST

TEMPERATURE

AOL

Electrical Functionality
Parametric, DC
Major Mechanical
Minor Mechanical

25°C
25°C
25°C
25°C

0.14%
0.28%
0.25%
1%

4-43

8+ PROGRAM
B+ Program: a comprehensive program that assures high
quality and high reliability of molded integrated circuits.

In any test for reliability the weaker parts will normally
fail first. Further, stress tests will accelerate, or shorten,
the time to failure of the weak parts. Because the stress
tests cause weak parts to fail prior to shipment to the
user, the population of shipped parts will in facg demonstrate a higher reliability in use.

The B+ program improves both the quality and the
reliability of National's digital, linear, and CMOS Epoxy
B integrated circuit product's. It is intended for the
manufacturing user who cannot perform incoming
inspection of his ICs, or does not wish to do so, yet
needs significantly-better-than-usual incoming quality
and reliability levels for his standard ICs.

Quality Improvement
When an IC vendor specifies 100 percent final testing
of his parts then, in theory, every shipped part should
be a good part. However, in any population of massproduced items there does exist some small percentage
of defective parts.

Integrated circuit users who specify B+ processed parts
will find that the program:
•

Eliminates incoming electrical inspection

•

Elimin<;ltes the need for, and thus the costs of, independent testing laboratories

•

Reduces the costof reworking assembled/boards

•

Reduces field failures

•

Reduces equipment downtime

One of the best ways to reduce the number of such
faulty parts is, simply, to retest the parts prior to shipment. Thus, if there is a one percent change that a bad
part will escape detection initially, retesting the parts
reduces that probability to only 0.01 percent. (A comparable tightening of the OC group's sampled-test plan
ensures the maintenance of the improved quality level.)

Reliability Saves You Money

National's B+ Program Gets It All Together

With the increased population of integrated circuits in
modern electronic systems has come an increased
concern with IC failures In such systems.

We've stated that the B+ program improves both the
quality and the reliability of National's molded integrated circuits, and pointed out the difference between
those two concepts. Now, how do we bring them
together? The answer is in the B+ program ,processing,
which is a continuum of stress and double testing.
With the exception of the final OC inspection, which is
sampled, all steps' of the B+ process are performed on
100 percent of the program parts. The following flow
chart shows how we do it, step by st~p;

And rightly so, for at least two reasons.
First of all, the effect of component reliability on
system reliability can be quite dramatic. For example,
suppose that you, as a system manufacturer, were to.
choose an IC that is 99 percent reliable. You would find
that if your system used only 70 such ICs, the overall
reliability of the system:s IC portion would be only
50 percent. I n other words, only one out of two of your
systems would operate. The result? A system very costly
to produce and probably very difficult to sell.

Epoxy B Processing for All Molded Parts
At National, all molded semiconductors, including
ICs, have been built by this process for some time
now. All processing steps, inspections and OC
monitoring are designed to provide highly reliable
products. [A reliability report is available that
gives, in detail, ,the background of Epoxy B, the
reason for its selection at National and reliability
data that proves its success.)

Secondly, whether the system is large or small you
cannot afford to be hounded by the spectre of un,necessary maintenance costs. Not only because labor,
repair and rework costs have risen - and promise to
continue to rise - but also because field replacement
may be prohibitively expensive. If you' ship a system
that contains a marginally-performing IC, an IC that
later fails in the field, the cost of replacement may be
- literally - hundreds of times more than the cost of
the failed IC itself.

Six Hour, 150 e Bake
This stress places the die bond and all wire bonds
into a combined tensile and shear stress mode,
and help~ eliminate marginal bonds and electrical
connections.
0

Improving the' Reliability of Shipped Parts
The most important factor that affects a part's reliability
is its construction: the materials used and the method
by which they are assembled.

Five Temperature Cycles (0° C to 100° e)
Exercising the circuits over a 1aaoc temperature
range further stresses the bonds and generally
eliminates any marginal bonds missed during the
bake.

,Now, it's true that reliability cannot be tested into a
part. Still, there are tests and procedures that an IC
vendor can implement, which will subject the IC to
stresses in excess of those that it will endure in. actual
use, and which will eliminate most marginal, short-life
parts.

0

High Temperature (100 e) Functional Electrical
Test
A high-temperature test such as this with voltages

4-44

:I:
C')

:I:

applied places the die under the most severe stress
possible. The test is actually performed at 100°C
- 30°C higher than the commercial ambient limit.
All devices are thoroughly exercised at the 100°C
ambient. [Even though Epoxy B processing has
virtually eliminated thermal intermittents, we
perform this test to ensure againnt even the
remote possibility of such a problem. Remember,
the emphasis in the B+ program is on the elimina·
tion of those marginallY'performing devices that
would otherwise lower field reliability of the
parts.]

::a

m
.-

~

to

"

.~
(")
s:

0

rn

DC Functional and Parametric Tests
These room-temperature functional and parametric
tests are the normal, final tests through which all
National products pass.
Tighter-than-Normal QC Inspection Plans
Most vendors sample inspect outgoing parts to a
0.65% AOL. Some use even
looser 1% AOL.
When you specify the B+ program, however, not
only do we sample your parts to a 0.28% AOL for
all data·sheet DC parameters, but they receive a
0.14% AOL for functionality as well. Now, functional failures - not parameter shifts beyond spec
- cause most system failures. Thus, the five-times
to seven-times tightening of the sampling procedure
(from 0.65-1% to 14% AOL) gives a substantially
higher quality to your B+ parts. And you can rely
on the integrity of your received ICs without
incoming tests at your facility.

a

Ship 'Parts

Here are the OC sampling plans used in our B+ test
program:
TEST

TEMPERATURE

AOL

Electrical Functionality
Parametric, DC
Parametric, DC
Parametric, AC
Major Mechanical
Minor· Mechanical

25°C
25°C
100°C
25°C

0.14%
0.25%
1%
1%
0.25%
1%

4·45

l>

Stephen Calebotta
National Semiconductor

2I
......
......
(")

3:

o
en
-t

:J:

m

CMOS, THE IDEAL LOGIC FAMILY

C

m

l>
rr-

o

INTRODUCTION

G')

(")

lower. The power supplies in a CMOS system will
be cheaper since they can be made smaller and with
less regulation. Because of lower currents, the
power supply distribution system can be simpler
and therefore, cheaper. Fans and other cooling
equipment are not needed due to the lower dissi·
pation. Because of longer rise and fall times, the
transmission of digital signals becomes simpler
making transmission techniques less expensive.
Finally, there is no technical reason why CMOS
prices cannot approach present day TTL prices as
sales volume and manufacturing experience in·
crease. So, an engineer about to start a new design
should compare the system level cost of using
CMOS or some other logic family. He may find
that, even at today's prices, CMOS is the most
economical choice.

Let's talk about the characteristics of an ideal logic
family. It should dissipate no power, have zero
propagation delay, controlled rise and fall times,
and have noise immunity equal to 50% of the
logic swing.
Well, that ideal logic family is here - almost.
The properties of CMOS (complementary MOS)
be~in to approach these ideal characteristics.
First, CMOS dissipates low pow~r. Typically, the
static power dissipation is 10 nW per gate which is
due to the flow of leakage currents. The active
power depends on power supply voltage, frequency,
output load and input rise time, but typically, gate
dissipation at 1 MHz with a 50 pF load is less than
10mW.
Second, the propagation delays through CMOS are
short, though not quite zero. Depending on power
supply voltage, the delay through a typical gate is
on the order of 25 to 50 ns.

National is building two lines of CMOS. The first
is a number of parts of the CD4000A series. The
second is the 54C/74C series which National
introduced and which will become the industry
standard in the near future.

Third, rise and fall times are controlled, tending
to be ramps rather than step functions. Typically,
rise and fall times tend to be 20 to 40% longer
than the propagation delays.

The 54C/74C line consists of CMOS parts which
are pin and functional equivalents of many of the
most popular. parts in the 7400 TTL series. This
line is typically 50% faster than the 4000A series
and sinks 50% more current. For ease of design, it
is spec'd at TTL levels as well as CMOS levels;and
. there are two temperature ranges available: 54C,
-55°C to +125°C or 74C, -40°C to +85°C. Table 1
compares the port parameters of the 54C174C
CMOS line to those of the 54L/74L low power
TTL line.

Last, but not least, the noise immunity approaches
50%, being typically 45% of the full logic swing.
Besides the fact that it approaches the characteris·
tics of an ideal logic family and besides the obvious
low power battery applications, why should de·
signers choose CMOS for new systems? The answer
is cost.
On a component basis, CMOS is still more expen·
sive than TTL. However, system level cost may be

TABLE 1. Comparison of 54L/74L Low Power TTL and 54C/74C CMOS Port Parameters.

FAMILY

Vee

54L174L
54C!74C
54C/74C

10

V IL

IlL

MAX

MAX

0.7

0.18mA

VIH
MIN

IIH
2.4V

MAX

2.0

10ilA

0.3

VOL

VOH
MIN

IOL
2.0mA

IOH

IpdQ
TYP

TYP

tpdl

Polss/GATE
STATIC

POiss/GATE
1 MHz, 50 pF LOAD

2.4

100IJA

31

35

lmW

2.25 mW

0.8

3.5

0.4

"3601lA

2.4

"lOOIlA

60

45

0.00001 mW

1.25mW

2.0

8.0

1.0

""lOIlA

9.0

""lOIlA

25

30

0.00003 mW

5mW

* Assumes interfacing to low power TTL.
* * Assumes interfacing to CMOS.

&-3

."

l>

s:
r-

oo(

~
~



...:::>
...:::>

'-'

~VOUT

V ,N

30

'"

0

B

J:::
·z
 2V T ). Each time the circuit switches, a current
momentarily flows from Vee to Ground through
both output transistors. Since the threshold voltages
of the transistors do not change with increasing
Vee, the input voltage range through which the
upper and lower transistors are conducting simultaneously increases as Vee increases. At the same
time, the higher Vee provides higher V GS voltdges
which also increase the magnitude of the los
currents. Incidently, if the rise time of the input
signal was zero, there would' be no current flow
from Vee to Ground through the circuit. This
current flows because the input signal has a finite
rise time and, therefore, the input voltage spends a
finite amount of time passing through the region
where both transistors conduct simultaneously.
Obviously, input rise and fall times should be kept
to a minimulT,1 to minimize VI power dissipation.

f

~

I

V,IrIIIVDlTS)

(c)

(d)

FIGURE 2-4. ,Transfer Characteristics vs VCC.

Considering the subject of noise in a CMOS system,
we must discuss at least two specs: noise immunity
and noise margin.
National's CMOS circuits have a typical noise
immunity of 0.45 Vee. This means that a spurious
input which is 0.45 Vee or less away from Vee or
Ground typically will not propagate through the
system as an erroneous logic level. This does not
mean that no signal at all will appear at the output
of the first circuit. In fact, there will be an output
signal as a result of the spurious input, but it will
be reduced in amplitude. As 'this signal propagates
through the system, it will be attenuated even
more by each circuit it passes through until it
finally disappears. Typically, it will not change any
signal to the opposite logic level. I n a typical
flip flop, a 0.45 Vee spurious pulse on the clock
line would not cause the flop to change' state.

Let's look at the transfer characteristics, Figure 2-4,
as they vary with Vee. For the purposes of this
discussion we will assume that both transistors in
our basic inverter have identical but complementary
characteristics and threshold voltages. Assume the
threshold voltages, VT , to be 2V. If Vee is less
than the threshold voltage of 2V, neither transistor
can ever be turned on and the circuit cannot
operate. If Vee is equal to the threshold voltage
exactly then we are on the curve Figure 2-4a.
We appear to have 100% hysteresis. However, it is
not truly hysteresis since both output transistors
are off and the output voltage is being held on the
. gate capacitances of succeeding circuits. If Vee is
somewhere .between one and two threshold voltages (Figure 2-4b), then we have diminishing
amounts of "hysteresis" as we approach Vee equal
to 2V T (Figure 2-4c). At Vee equal to two thresholds we have no "hysteresis" and no current flow
through both the upper and lower transistors during·switching. As Vee exceeds two thresholds the

National also guarantees that .its CMOS circuits
have a 1 V DC noise margin over the full power
supply range and temperature range and with any
combination of inputs. This is simply a variation of
the noise immunity spec only now a specific set of
input and output voltages have been selected and
guaranteed. Stated verbally, the spec says that for
the output of a circuit to be within 0.1 Vee volts
of a proper logic level (V ce or Ground), the input

5-5

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can be as much as 0.1 Vee plus 1 V away from
power supply rail. Shown graphically we have:
lSV , . - - - - - - - - - - . . ,

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If we were going to tie the unused inputs to a
logic level, inputs A & B would have to be tied to
Vee to enable the other inputs to function. That
would turn on the lower A and B transistors and
turn off the upper A and B transistors. At most,
only two of the upper transistors could ever be
turned on. However, if inputs A and B were tied
to input C, the input capaCitance would triple, but
each time C went low, the upper A, Band C
transistors would turn on, tripling the available
source current. If input D was low also, all four of
the upper transistors would be on.

4.S0V

15V

10V
Vee

FIGURE 2-5. Guaranteed CMOS DC Margin Over
Temperature as a Function of VCC'
CMOS Guarantees lV.

This is similar in nature to the standard TTL noise
margin spec which is 0.4V.

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FIGURE 3-1. MM74C20 Four Input NAND Gate.
4.5

5.0

So, tying unused ,NAND gate inputs to Vee
(Ground for NOR gates) will enable them, but
tying unused inputs to other used inputs guarantees
an increase in source current in the case of NAND
gates (sink current in the case of NOR gates).
There is no increase in drive possible through the
series transistors. By using this approach, a multiple
input gate could be used to drive a heavy current
load such as a lamp or a relay.

5.5

Vee

FIGURE 2-6. Guaranteed TTL DC Margin Over
Temperature as a Function of VCC.
TTL Guarantees O.4V.

For a complete picture of V OUT vs V IN refer to
the transfer characteristic curves in Figure 2-4.

Parallel gates: depending on the type of gate, tying
inputs together guarantees an increase in either
source or sink current but not botn. To guarantee
an increase in both currents, a number of gates
must be paralleled as in Figure 3-2. This insures
that there are a number of parallel combinations
of the series string of transistors (Figure 3-1),
thereby increasing drive in that direction also.

SYSTEM CONSIDERATIONS
This section describes how to handle many of the
situations that arise in normal system design such
as unused inputs, paralleling circuits for extra
drive, databussing, 'power considerations and inter·
faces to other logic families.
Unused inputs: simply stated, unused inputs should
not be left open. Because of the very high impedance (~1012n), a floating input may drift back
and forth between a "0" and "1" creati ng some
very intriguing system problems. All unused inputs
should be tied' to Vee, Ground or ariother used
input. The choice is not completely arbitrary,
however, since there will be an effect on the
output drive capability of the circuit in question.
Take, for example, a four input NAND gate being
used as a two input gate. Th~ internal structure is
shown in Figure 3-1. Let inputs A & B be the
unused inputs.

OR

FIGURE 3-2. Paralleling Gates or Inverters Increases
'Output Drive in Both Directions.

, Data bussing: there are essentially two ways to do
this. First, connect ordinary CMOS parts to. a bus
using transfer gates (part no. CD4016C). Second,

5·6

rise time is long, power dissipation increases since
the current path is established for the entire period
that the input signal is passing through the region
between the threshold voltages of the upper and
lower transistors. Theoretically, if the rise time
were zero, no current path would be established
and the VI power would be zero. However, with a
finite rise time there is always some current flow
and this current flow increases rapidly with power
supply voltage.

and the preferred way, is to use parts specifically
designed with a CMOS equivalent of a TR I-STATE®
output.
Power supply filtering: since CMOS can operate
over a large range of power supply voltages (3V
to 15V), the filtering necessary is minimal. The
minimum power supply voltage required will be
determined by the maximum frequency of operation of the fastest element in the system (usually
only a very small portion of any system operates
at maximum frequency). The filtering should be
designed to keep the power supply voltage somewhere between this minimum voltage and the
maximum rated voltage the parts can tolerate.
However, if power dissipation is to be kept to a
minimum, the power supply voltage should be
kept as low as possible while still meeting all speed
requirements.

Just a thought about rise time and power dissipation. If a circuit is used to drive many loads, its
output rise time will suffer. This will result in an
increase in VI power dissipation in every"device
being driven by that circuit (but not in the drive
circuit itself). If power consumption is critical, it
may be necessary to improve the rise time of that
circuit by buffering or by dividing the loads ill
order -to reduce overall power consumption.
So, to summarize the effects of power supply
voltage, input voltage, input rise time a"d output
load capacitance on system power dissipation, we
can say the following:

Minimizing system power dissipation: to minimize
power consumption in a given system, it should be
run at the minimum speed to do the job with the
lowest possible power supply voltage. AC and- DC
transient power consumption both increase with
frequency and power supply voltage. The AC
power is described as CV 2 f power. This is the
power -dissi pated in a driver driving a capacitive
load. Obviously, AC power consumption increases
directly with frequency and as the square of the
power supply. It also increases with capacitive load,
but this is usually defined by the system and is not
alterable. The DC power is the VI power dissipated
during switching. In any CMOS device during
switching, there is a momentary current path from
the power supply to ground, (when Vee> 2V T )
Figure 3-3.
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,_ Power supply voltage: CV2f power dissipation
increases as the square of power supply voltage.
VI power dissipation increases approximately
as the square of the power supply voltage.
2_ Input voltage level: VI power dissipation increases if the input voltage lies somewhere
between Ground plus a threshold voltage and
Vee minus a threshold voltage. The highest
power dissipation occurs when V IN is at 1/2
Vee. CV2f dissipation is unaffected.
3_ Input rise time: VI power dissipation increases
with longer rise times since the DC current path
through the device is established for a longer
period. The CV2f power is unaffected by slow

-

input rise times.
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4_ Output load capacitance: the CV2f power dissi-.
pated in a circuit increases directly with load
capacitance. VI power in a circuit is unaffected
by its output load capacitance. However, increasing output load capacitance will slow
down the output rise time of a circuit which in
turn will affect the VI power dissipation in the
devices it is driving.

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VI POWER IS GIVEN BY:
PVI ' Vee x"2 I MAx x RISE TIME TO PERIOD RATIO
RISE TIME TO
PERIOD RATIO

Vee - ZV T
IRISE +I'All
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tTOTAL

WHERE - '-

• FREOUENCY

INTERFACES TO OTHER LOGIC TYPES

tTOTA.L

There are two main ideas behind all of the following interfaces to CMOS. First, CMOS outputs
should satisfy the current and voltage requirements
of the other family's inputs. Second, and probably
most important, the other family's outputs should
swing as near as possible to the full voltage range
of the CMOS power supplies.

PVI • liZ (Vee - 2V T ) lee MAX (tRISE +I'Ald FRED.

FIGURE 3-3_ DC Transient Power.

The maximum amplitude of the current is a rapidly
increasing function of the input voltage which in
turn is a direct function of the power supply
Voltage. See Figure 2-4d.

P-Channel MOS: there are a number of things to
watch for when interfacing CMOS and P-MOS. The
first is the power supply set. Most of the more
popular P-MOS parts are specified with 17 to 24V
power supplies while the maximum power supply
voltage for CMOS is 15V. Another problem

The actual amount of VI power dissipated by the
system is determined by three things: power supply
voltage, frequency and input signal rise time. A
very important factor is the input rise time. If the

5-7

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is that unlike CMOS, the output swing of a push·
pull P·MOS output is significantly less than the
power supply voltage across it. P·MOS swings from
very close to its more positive supply (V ss ) to
quite a few volts above its more negative supply
(Vee). So, even if P·MOS uses a 15V or lower
power supply set, its output swing will not go low
enough for a reliable interface to CMOS. There are
a number of ways to solve this problem depending
on the configuration of the system. We will discuss
two solutions for systems that are built totally
with MOS and one solution for systems that
include bipolar logic.

outputs. The CMOS can still drive P-MOS directly
and now the P·MOS can drive .CMOS with no
pull·down resistors. The other restrictions are that
the total voltage across the CMOS is less than 15V
and that the bias supply can handle the current
requirements of all the CMOS. This approach is
useful if the P-MOS supply must be greater than
15V and the CMOS current requirement is low
enough to be done easily with a small discrete
component regulator.
If the system has bipolar logic, it will usually
have at least two power supplies. In th is case, the
CMOS is run off the bipolar supply and it interfaces Clirectly to P·MOS, Figure 3-6.

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FIGURE 3·4. A One Power Supply System Built
Entirely of CMOS and P·MOS.
Run the CMOS Irom the bipolar supply and interlece directly to P·MOS

First, MOS only. P·MOS and CMOS using the
same power supply of less than 15V, Figure 3-4.

FIGURE 3-6. A System With CMOS, P·MOS and Bipolar
Logic.

In this configuration CMOS drives P·MOS directly.
However, P-MOS cannot drive CMOS directly be·
cause of its output will not pull down close enough
to the lower power supply rail. R pD (R pull down)
is added to eachP-MOS output to pull it all the
way down to the lower rail. Its value is selected
such that it is small enough to give the desired
F,lC time constant when pulling down but not so
small that the P-MOS output cannot pull it
virtually all the way up to the upper power supply
rail when it needs to. This approach will work with
push·pull as well as. open drain P-MOS outputs.

N-Channel MOS: interfacing to N·MOS is somewhat simpler than interfacing to P·MOS although
similar problems exist. First, N·MOS requires
lower power supplies than P-MOS, being in the
range of 5V to 12V. This is directly compatible
with CMOS. Second, N-MOS logic levels range·
from slightly above the lower power supply rail to
about 1 to 2V below the upper rail.
At the higher power supply voltages, N·MOS and
CMOS can be interfaced directly since the N-MOS
high logic level wi II be only about 10 to 20 percent
below the upper rail. However, at lower supply
voltages the N·MOS output level will be down 20
to 40 percent below the upper rail and something
may have to be done to raise it. The simplest solution is to add pull up resistors on the N-MOS
outputs as shown in Figure 3-7.

An'other approach in a purely MOS system is to
build a cheap zener supply to bias up the lower
power supply rail of CMOS, Figure 3·5.

Use a bias supply to reduce the voltage

aCTDSS

the CMOS

to match the logic swing 01 the P·MOS. Make sura the
r.. ulting voltag. leross the CMOS is less than 15V.
Both operate off same supply with pull up rasistors optional from
N-MOS to CMOS.

FIGURE 3-5. A P·MOS and CMOS System Where The
P-MOS Supply is Greater Than 15V.

FIGURE 3·7. A System With CMOS and N·MOS Only.

In this configuration the P-MOS supply is selected
to satisfy the P-MOS voltage requirement. The bias
supply voltage is selected to reduce the total
voltage across the CMOS (and therefore its logic
swing) to match the minimum swing of the P-MOS

TTL, LPTTL, OTL: two questions arise when
interfacing bipolar logic families to CMOS. First,
is the bipolar family's logic "1" output voltage high
enough to drive CMOS directly?

5-8

The LPTTL input current is small enough to allow
CMOS to drive two loads directly. Normal power
TTL input currents are ten times higher than
those in LPTTL and consequently the CMOS output voltage will be well above the input logic "0"
maximum of 0.8V. However, by carefully examining the CMOS output specs we will find that a two
input NOR gate can drive one TTL load, albeit
somewhat marginally. For example, the logical
"0" output voltage for both an 'MM74COO and
MM74C02 over temperature is specified at OAV
sinking 360j.1A (about 420j.1A at 25°C) with an
input voltage of 4.0V and a Vee of 4.75V. Both
schematics are shown in Figure 3-9.

TTL, LPTTL, and DTL can drive 74C series CMOS
directly over the commercial temperature range
without external pull up resistors. However, TTL
and LPTTL cannot drive 4000 series CMOS directly
(DTL can) since 4000 series specs do not guarantee
that a direct interface with no pull up resistors will
operate properly.
DTL and LPTTL manufactured by National (NS
LPTTL pulls up one diode drop higher than the
LPTTL of other vendors) will also drive 74C
directly over the entire military temperature range.
LPTTL manufactured by other vendors and standard TTL will drive 74C directly over most of the
mil temperature range. However, the TTL logic
"1" drops to a somewhat marginal level toward the
lower end of the mil temperature range and a pull
up resistor is recommended.

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According to the curve of DC margin vs Vee for
CMOS in Figure 2-5, if the CMOS sees an input
voltage greater than Vee - 1.5V (Vee = 5V). the
output is guaranteed to be less than 0.5V from
Ground. The next CMOS element will amplify
this 0.5V level to the proper logic levels of Vee or
Ground. The standard TTL logic "1" spec is a Va UT
min. of 2.4V sourcing a current of 400j.1A. This
is an extremely conservative spec since a TTL
output will only approach a one level of 2AV
under the extreme worst case conditions of lowest
temperature, high input voltage (0.8V). highest
possible leakage 'currents (into succeeding TTL
devices). and Vee at the lowest allowable (Vee =
4.5V).

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FIGURE 3-9a. MM74COO_

Under nominal conditions (25°C, V 1N = OAV,
nominal leakage currents into CMOS and Vee =
5V) a TTL logic "1" will be more like Vee - 2V o ,
or Vee - 1.2V. Varying only temperature, the
output will change by two times -2mV per °c, or
-4 mV per uc. Vee - 1.2V i~ more than enough
to drive CMOS reliably without the use of a pull
up resistor.
If the system is such that the TTL logic "1" output
can drop below Vee - 1.5V, use a pull up resistor
to improve the logic "1" voltage into the CMOS.

FIGURE 3-9b. MM74C02.

Both parts have the same current sinking spec but
their structures are different. What this means is
that either of th"e lower transistors in the MM74C02
can sink the same current as the tWQ lower series
transistors in the MM74COO. Both MM74C02
transistors together can sink twice the specified
current for a given output voltage. If we allow the
output voltage to go to 0.8V, then a MM74C02
can sink four times 360j.1A, or 1.4~ mA which is
nearly 1.6 mAo Actually, 1.6 mA is the maximum

Pull up resistor, Rpu. is needed only at the lower end of the Mil
temperature range.

FIGURE 3-8. TTL to CMOS Interface.

The second question is, can CMOS sink the bipolar
input current and not exceed the maximum value
of the bipolar logic zero input voltage? The logic
"1" input is no problem.

5-9

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spec for the TTL input current and most' TTL
parts run at about 1 mAo Also, 360.uA is the
minimum CMOS sink current spec, the parts will
really sink somewhere between 360 and 540}-lA
(between 2 and 3 LPTTL input loads). The 360,uA
sink current is specified with an input voltage of
4.0V. With an input voltage of 5.0V, the sink
current will be about 560,uA over temperature,
making it even easier to drive TTL. At room
temperature with an i'nput voltage of 5V, a CMOS
output can sink about 800,uA. A 2 input NOR
gate, therefore, will sink about 1.6 mA with a V OUT
of about O.4V if both NOR gate inputs are at 5V.

can be used to drive a normal TTL load in lieu of a
special buffer. However, the designer must be
willing to sacrifice some noise immunity over
temperature to do so.

TIMING CONSIDERATIONS IN CMOS MSls
There is one more thing to be said in closing. All
the flip-flops used in CMOS designs are genuinely
edge s'ensitive. This means that the J-K flip-flops
do not "ones catch" and that some of the timing
restrictions that applied to the control lines on
MSI functions in TTL have been relaxed in the
74C series.

The main point of this discussion is that a common
2 input CMOS NOR gate such as an MM74C02

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5-10

Gene Taatjes
JULY 1973

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PNP and NPN bipolar transistors have been used
for many years in "complementary" type of
amplifier circuits. Now, with the arrival of CMOS
technology, complementary P·channel/N·channel
MOS transistors are available in monolithic form.
The 'MM74C04 incorporates a P·channel MOS
transistor and an N·channel MaS transistor
connected in complementary fashion to function
as an inverter.

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FIGURE 2. A 74CMOS Invertor Biased for Linear Mode
Operation.

The power supply current is constant during
dynam ic operation since the inverter is biased for
Class A operation. When the input signal swings
near the supply, the output signal will become
distorted because the P·N channel devices are
driven into the non·linear regions of their transfer
characteristics. If the input signal approaches the
supply voltages, the p. or N·channel transistors'
become saturated and supply current is reduced to
essentially zero and the device behaves like the
classical digital inverter.

Due to the symmetry of the p. and N·channel
transistors, negative feedback around the comple·
mentary pair will cause the pair to self bias itself
to approximately 1/2 of the supply voltage.
Figure 1 shows an idealized voltage transfer
characteristic curve of the CMOS inverter con·
nected with negative feedback. Under these
conditions the inverter is biased for operation
about the midpoint in the linear segment on the
steep transition of the voltage transfer character·
istic as shown in Figure 1.

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CMOS LINEAR APPLICATIONS

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INPUT VOLTAGE - V,.

FIGURE 3. Voltage Transfer Characteristics for an
Inverter Connected as a Linear Amplifier.

INPUT VOLTAGE - VIN

Figure 3 shows typical voltage characteristics of
each inverter at several values of the Vee. The
shape of these transfer curves are relatively
constant with temperature. Temperature affects
for the self biased inverter with supply voltage is
shown in Figure 4. When the amplifier is operating
at 3 volts, the supply current changes drastically as
a function of supply voltage because the MOS
transistors are operating in the proximity of their
gate-source threshold voltages.

FIGURE 1. Idealized Voltage Transfer Characteristics of
an MM74C04 Inverter.

Under AC conditions, a positive going input will
cause the output to swing negative and a negative
going input will have an inverse effect. Figure 2
shows 1/6 of a MM74C04 inverter package
connected as an AC amplifier.

5·11

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Post Amplifier for Op Amps.

~

A standard' operational amplifier used with a
CMOS inverter for a Post Amplifier has several
advantages. The operational amplifier essentially
sees no load condition since the input impedance
to the inverter is very high. Secondly. the CMOS
inverters will swing to within millivolts of either
supply. This gives the designer the advantage of
operating the operational amplifier under no load
conditions yet having the full supply swing
capability on the output. Shown in Figure 7 is the
LM4250 micropower Op Amp used with a 74C04
inverter for increased output capability while
maintaining the low power advantage of both
devices.

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TEMPERATURE

FIGURE 4. Normalized Amplifier Supply Current Versus
Ambient Temperature Characteristics.

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Figure 5 shows typical curves of voltage gain as a
function of operating frequency for various supply
voltages.
Output voltages can swing within millivolts of the
supplies with either a single. or dual supply.

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40

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10

FIGURE 7. MM74C04 Inverter Used as a Post Amplifier
for a' Battery Operated Op Amp.
1.0

10

10'

10'
OPERATING FREQUENCY - Hz

FIGURE 5. Typical Voltage Gain Versus Frequency
Characteristics for Amplifier Shown in Figure 2.

The MM74C04 can also be used with single supply
amplifier such as the LM324. With the circuit
shown in Figure 8, the open loop gain is approxi·
mately 160 dB. The LM324 has 4 amplifiers in a
package and the MM74C04 has 6 amplifiers per
package.

APPLICATIONS
+12V

Cascading Amplifiers for Higher Gain.
By cascading the basic amplifier' block shown in
Figure 2·a high gain amplifier can be achieved. The
gain will be multiplied by the number of stages
used. If more than one inverter is used inside the
feedback loop (as in Figure 6) a higher open loop
gain is achieved which results in more accurate
closed loop gains.

V,.

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10Mn

FIGURE 8. Single Supply Amplifier Using' a CMOS
Cascade Post Amplifier with the LM324.

CMOS inverters can be paralleled for increased
power to drive higher current loads, Loads of
5.0 mA per inverter can be expected under AC
conditions.

FIGURE 6. Three CMOS Inverters Used as an X10 AC
Amplifier.

Other 74C devices can be used to provi~e greater
complementary current outputs. The MM74COO
'NAND Gate will provide approximately 10 mA

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from the Vee supply while the MM74C02 will
supply approximately 10 mA from the negative
supply. Shown in Figure 9 is an operational
amplifier using a CMOS power post amplifier to
provide greater than 40 mA complementary
currents.

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Phase Shift
Oscillator Using MM74C04

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Integrator Using
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Square Wave Oscillator

FIGURE 9. MM74COO and MM74C02 Used as a Post
Amplifier to Provide Increased Current Drive.

+VCCR

Other Applications.

INPUT

Shown in Figure 10 is a variety of applications
utilizing CMOS devices. Shown is a linear phase
shift oscillator 'and an integrator which use the
CMOS devices in the linear mode as well as a few
circu it ideas for clocks and one shots.

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One Shot

Conclusion
'Careful study of CMOS characteristics show that
CMOS devices used in a system design can be used
for linear building blocks as well as digital blocks,
Staircase Generator

Utilization of these new devices will decrease
package count and reduce supply requirements.
The circuit designer now can do both digital and
linear designs with the same type of device.

FIGURE 10. Variety of Circuit Ideas Using CMOS
Devices.

5·13

Thomas P. Redfern
National Semiconductor

54C/74C FAMILY CHARACTERISTICS
INTRODUCTION
the fact that 54C/74C has the same function and
pin·out as standard series 54L/74L will make the
application of CMOS to digital systems very
straightforward.

The purpose of this 54C/74C Family Character·
istics application note is to set down, in one place,
all those characteristics which are common to the
devices in the MM54C/MM74C logic family. The
characteristics which can De considered to apply
are:

OUTPUT CHARACTERISTICS

1. Output voltage·current characteristics

2. Noise characteristics

Figure 1 and Figure 2 show typical output drain
characteristics for the basic inverter used in the
54C/74C family. For more detailed information on
the operation of the basic inverter the reader is
directed to application note AN·77, "CMOS, The
Ideal Logic Family." Although more complex
gates, and MSI devices, may be composed of
combinations of parallel and series transistors the
considerations that govern the output character·
istics of the basic inverter apply to these more
complex structures as well.

3. Power consumption

o

~

z

«

4. Propagation delay (speed)
5. Temperature characteristics
With a good understanding of the above charac·
teristics the designer will have the necessary tools
to optimize his system. An attempt will be made
to present the information in as simple a· manner
as possible to facilitate its use. This coupled with

VDS (VI
-5.0

-4.0

-3.0

-2.0

-1.0

o·

5.0
4.0

;(
.§.

II

-1.0
GUARANTEED TEST POINT
los .: 1.75 mA

3.0

~---;.-t--'k

v~~S= ~v50V .

2.0

+-,,!=~-l---l--t--""1

GUARANTEED TEST POINT
IDS': 1.75mA
Pk-I--'1... -1<--1 VDS '" 5.0V
Y'N = 5.0V

1.0

1.0

2.0

3.0

4.0

-2.0

If

-3.0

~

-4.0

5.0

1.0

VDS . VauT IVI

2.0

3.0

4.0

5.0

VauT (VI

(A) Typical Output Sink Characteristic
(N-Channell

(81 Typical Output Source Characteristic
(P-Channel)
FIGURE 1
Vos (V)

-10
20
16

;(
.§.

.P

6:F"
~~ '\..-f-

8.0

4.0

~rf
j

""~~

1

\250

......

4.0

6.0

1\,

Iias l 

5.0V

4.05

~ 3.05

V IN

Vee = lOV

= 10V

V IN = OV

2.5
1.5

Iiosl ?8.0 mA

los? 8.0 mA
Vos? lOV

IVosl? 10V
4.50V

·IOV

lSV

vee

Note that each device data sheet guarantees these
points in the table of electrical characteristics.

FIGURE 4. Guaranteed Noise Margin Over Temperature
vsVCC

The output characteristics can be used to determ ine
the output voltage for any load condition. Figures
, and 2 show load lines for resistive loads to Vee
for sink currents and to GND for source currents.
The intersections of this load line with the drain
characteristic in question gives the output voltage.
For example at Vee = 5.0V, V OUT = 1.5V (typ)
with a load of 500n to ground.

Noise immunity is an important device character·
istic. However, noise margin is of more use to the
designer because it very simply defines the amount
of noise a system can tolerate under any circum·
stances and still maintain the integrity of logic
levels.
Any noise specification to be complete must
define how measurements are to be made. Figure 5
indicates two extreme cases; driving all inputs
simultaneously and driving one input at a time.
Both conditions must be included because each
represents one worst case extreme.

These figures also show the guaranteed points for
driving two 54L/74L standard loads. As can be
seen there is typically ample margin at Vee = 5.0V.
In the case where the 54C/74C device is driving
another CMOS device the load line is coincident
with the los = 0 axis and the output will then
typically switch to either Vee or ground.

vee

NOISE CHARACTERISTICS
VOUT

Definition of Terms

VOUT

•

Noise Immunity: The noise immunity of a logic
element is that voltage which applied to the input
will cause the output to change its output state.

(AI

Noise Margin: The noise margin of a logic element
is the difference between the guaranteed logical
"'" ("0") level output voltage and the guaranteed
logical "'" ("0") level input voltage.

vee

VOUT

The transfer characteristic of Figure 3 shows
typical noise immunity and guaranteed noise
margin for a 54C/74C device operating at Vee =
, OV. The typical noise immunity does not change
with voltage and is 45% of Vee.
·VOUT • VaUlt !IMIN. VOUTIOIMAX

VN

10.

'

ALLOWABLE NOISE VOLTAGE cl.OV

(81
·'D"l(VElIrIQIUIU.RGIN·

~
::>
~.

V'NIIIIM4.-'J OUT10I ,"' ••

8.0

T'LIVELIIIOIUMAAGIN'

FIGURE 5. Noise Margin Test Circuits

VOUllII",,,,,-V"'!II.MII"

6.0

To guarantee a noise margin of '.OV, all 54C/74C
devices are tested under both conditions. It is
important to note that this guarantees that every
node within a, system can have '.OV of noise, in
logic "'" or logic "0" state, without malfunction·
ing. This could not be guaranteed without testing
for both conditions in Figure 5.

4.0

2.0

2.0

4.0

6.0

8.0

10

V IN (V)

FIGURE 3. Tvpical Transfer Characteristic

5·15

cD
o

POWER CONSUMPTION

The procedure for obtaining Cpo is to measure
the no load power at Vee = 10V vs frequency and
calculate the value of Cpo which corresponds to
the measured power consumption. This value of
Cpo is given on each 54C/74C data sheet and
with equation (1) the computation of power
consumption is straightforward.

There are four sources of power consumption in
CMOS devices: (1) leakage current (2) transient
power due to load capacitance(3) transient power
due to internal capacitance and (4) transient power
due to current spiking during switching.
The first, leakage current, is the easiest to calculate,
and is simply the leakage current times Vee. The
data sheet for each specific device specifies this
leakage current.

To simplify the task even further Figure 6 gives a
graph of normalized power vs frequency for dif·
ferent power supply voltages. To obtain actual
power consumption find the normalized powerfor
a particular Vee and frequency, then multiply
by Cpo + C L •

The second, transient power due to load capacitance, can be derived from the fact that the energy
stored on a capacitor is 1/2 CV2. Therefore e~ery
time the load capacitance is charged or discharged
this amount of energy must be provided by the
CMOS device. The energy per cycle is then
2 [(1/2) CV ee 2] = CV ee 2. Energy perunit time,
or power, is then CV ee 2 f, where C is the load
, capacitance and f is the frequency.

o

en
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-d:

The third, transient power due to internal capacitance takes exactly the same form as the load
capacitance. Every device has some internal nodal
capacitance which must be charged and discharged.
This then represents another power term which
must be considered.
FIGURE 6. Normalized Typical Power Consumption
vs Frequency

The fourth, transient power due to switching
current, is caused by the fact that whenever a
CMOS device goes through a transition, with
Vce ~ 2 V T , there is a time when both N-channel
and P·channel devices are both conducting. An
expression for this current is derived in application
note AN· 77. The expression is:

As an example let's find the total power consump·
tion for an MM 74COO operating at f = 100 kHz,
Vee = 10V and C L = 50 pF. From the curve,
normalized power per gate equals 1 OpW/pF. From
the data sheet Cpo = 12 pF; therefore, actual
power per gate is:
power
gate

where:

lO/lW

- - X (12pF + 50pF)
pF

0.62 mW

=- - -

no. of gates
power
total power = - - - - X - - +
package
gate

V T = threshold voltage
leC(MAX) = peak non'capacitive current
during switching

= 4 X 0.62 mW

f = frequency

gate

ILEAKAGE

X Vee

+ O.D1/lA X 10V == 2.48 mW

Up to this point the discussion of power con·
sumption has been limited to simple gate functions.
Power consumption for an MSI function is more
complex but the same technique just derived
applies. To demonstrate the technique let's compute the total power consumption of a MM 74C 161,
four bit binary counter, at Vee = 10V, f = 1 MHz
and C L = 50 pF on each output.

Note that this expression, I ike the capacitive power
term is directly proportional to frequency. If the
PV1 term is combined with the term arising from
the internal capacitance, a capacitance Cpo may
be defined which closely approximates the no load
power consumption fo~ a CMOS device when used
in the following expression:

The no load power is still given by P (no load) =
Cpo V ee 2 f. This demonstrates the usefulness
of the concept of the internal capacitance, Cpo,
Even through the circuit is very complex. and has
many nodes charging and discharging at various
rates, all of the effects can be easily lumped into
one easy to use term, Cpo.
' .

Power (no load) = Cpo V ee 2 f
The total power consumption is then simplified
to:
Total Power = (C PD + CLl V ee 2 f+ ILEAK Vee (1)

5·16

»
z

Calculation of transient power due to load capacitance is a little more complex since each output
is switched at one half the rate of the previous
output: Taking this into account the complete
expression for power consumption is:

i

cD

1.5

.....

~.

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en
~
n

1.0

0

~

t-

0

~

0.5

~

n

a:

'1-

I

no load
power

output
power of
1st stage

3rd stage

~

2nd stage

4th stage
& carry
output

..

T

5.0

FIGURE 7. Typical Propagation Delay per pF of Load
Capacitance vs Power Supply

leakage
term

This reduces to:

the propagation delay for zero load capacitance is
not zero and depends on the internal structure of
each device, an offset term must be added that is
unique to a particular device type. Since each
data sheet gives propagation delay for 50 pF the
actual delay for different loads can be computed
with the aid of the following equation:

= (Cpo + Cd

V ee 2 f + IL Vee

From the data sheet Cpo = 90 pF and I L
Using Figure 6 total power is then:

= (C -

tpd..

I

CL

= (90 pF + 50 pF)
X 10V

J:

»
:Jl
»
~

m

:Jl

50) pF X

Atpd
-;;F
+ tpd

::!

I

=C

CL

n

= 50 pF

= 0.05J1A.
where:

PTOTAL

~
n

CJ)

\

PTOTAL

"»~

15

10

Vee - POWER SUPPLY VOL lAGE (V)

100J1.W
X - - + 0.05 X 10-6
pF

C = Actual load capacitance

== 14 mW

This demonstrates that with more complex devices
the concept of Cpo greatly simplifies the calcula·
tion of total power consumption. It becomes an
easy task to compute power for different voltages
and frequencies by use of Figure 6 and the
equations above.

PROPAGATION DELAY
Propagation delay for all 54C/74C devices is
guaranteed with a load of 50 pF and input rise
and fall times of 20 ns. A 50 pF load was chosen,
instead .of 15 pF as in the 4000 series, because it
is representative of loads commonly seen in CMOS
systems. A good rule of thumb, in designing with
CMOS, is to assume 10 pF of interwiring capacitance. Operating at the specified propagation
delay would allow 5 pF fanout for the 4000
series while 54C/74C has a fanout of 40 pF. A
fanout of 5 pF (one gate input) is all but useless,
and specified propagation delay would most prob·
ably not be realized in an actual system.
Operating at loads other. than 50 pF poses a
problem since propagation is a function of load
capacitance. To simplify the problem Figure 7
has been generated and gives the slope of the
propagation delay vs load' capacitance line (At pd /
pF)" as a function of power supply voltage. Because

propagation delay with 50 pF
load, (specified on each de·
vice data sheet)

Atpd

Value obtained from Figure 7.

pF
As an example let's compute the propagation
delay for an MM74COO driving 15 pF load and
operating with a Vee = 5.0V. The equation
gives:

tpd

I

.

ns
= (15- 50) pF X 0.57- + 50 ns

pF

C L = 15 pF

=-20 ns + 50 ns = 30 ns
The same formula and curves may be applied to
more complex devices. For example the propagation delay from data to output for an MM74C157
6perating at Vee = 10V and C L = 100 pF is:
tpd

I'
= (100 - 50) 0.29 ns + 70 ns
C L =100pF
= 14.5 + 70

== 85 ns

CJ)

It is significant to note that this equation and
Figure 7 apply to all 54C174C devices. This is true
because of the close match in drive characteristics
of every device including MSI functions, i.e., the
slope of the propagation delay vs load capacitance
line at a given voltage is typically equal for all
devices. The only exception is high fan-out buffers
which have a smaller .:ltpd/pF.

Vee = 5.0V to Vee = 10V gives a 40% det:rease
in propagation delay and goif)g from Vee = 10V
to Vee = 15V only decreases propagation delay
by 25%. Clearly for Vee> 10V a small increase
in speed is gained by a disproportionate increase
in power. Conversely, for small decreases in power
below' Vee = 5.0V large increases in propagation
delay result.

Another point to consider in the design of a
CMOS system is the affect of power supply
voltage on propagation delay. Figure 8 shows
propagation delay as a function of Vee and
propagation delay times power consumption vs
Vee for an MM74COO operating with 50 pF load
at f = 100 kHz.
i"

Obviously it is optimum to use the lowest voltage
consistent with system speed requirements. However in general it can be seen from Figure 8 that
the best speed power performance will be obtained
in the Vee = 5.0V to Vee = 10Vrange.

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<

300

TA "25"C
t. "11"20 os

150

>-

TEMPERATURE CHARACTERISTICS

~

50

~

e

Since the tpd can be entirely attributed to rise
and fall time, the temperature dependance of
tpd is a function of the rate at which the output
load capacitance can be charged and discharged.
This in turn is a' function of the sink/source
current which was shown above to vary as -0.3%
per degree centigrade. Consequ'ently we can say
that tpd varies as -0.3% per degree centigrade ..
Actual measurements of tpd with temperature
verifies this number.

"

0

I

c

c:

J.

5.0

10

....
~

15

Vee (V)

!

FIGURE 8. Speed Power Product and Propagation Delay
vsVCC

Above Vee = 5.0V note the speed power product
curve approaches a straight line. However the
tpd curve starts to "flatten out." Going from
5.0

~

.s
..9

V

.....

h~"""

J

TA • +70'C

<

t--

.s
-

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II

1.0

2,0

3.0

4.0

-2.0

-3.0

A

/.r

I I I

-1.0

TA • +125'C I--

'1/,/'"

2.0

Vee· S.OV

h • O'C.=I--

I

/>'V

3.0

1.0

~55'>~1-

Vee' 5.0V
TA '+25'C,

4.0

I I

./'4

..... 1-" ~~

T. = +12S'C

"....~~

~'+70'C

rr;:-.

1,...--::::;'"/

+25'C

-4.0

S·~~

-5.0

I I I

,....../

h .-55'~

5,0

1.0

2.0

3.0

4.0

5.0

V OU T<11 (V)

VOUTIOI (V)

(AI Typical Output Drain Characteristic
(N-Channell

(BI Typical Output Drain Characteristic
(P-Channel)
FIGURE 9

20

Vee -10V

~

.s

L

I

<

o

..9 '-12

4.0

&.0

8,0

~

-16

-20
10

VOUTIOI (V)

/~
V~P'I
~~J

I I
I

.~

TA'+~-

V/
....-::VV

TA'. +10't........ / . /
7,.":+25'C1-

I
2.8

-8.0

.s

I

2,0

~

I I I

-4.0

U// / , . - TA • +125'C
I/JV 't::+25iCT
rJ
I
J
I

~ 8.0

,

Vee = 10V

TA '_~'C

/.V; I-"t""" l
lTA "+70'C
Ib txf-

12

4,0

i--

TA ".O'C ~

16

~

M

TA=-55'C

o

2.0

4.0

'/
6.0

8.0

10

VOUTIlI (V)

(AI Typical Output Drain Characteristic
(N-Ct1annell

(BI Typical Output Drain Characteristic
(P-Channell
FIGURE 10

5-18

l>

:z
I

15

10

:
-:i2

indicates that they are almost independent of
temperJture. The transfer characteristic is not
dependent on temperature because although both
the N·channel and P·channel device characteristics
change with temperature these changes track each
other closely. The proof of th is tracking is the
temperature independance of the transfer charac·
teristics. Noise margin and maximum/minimum
logic levels will then not be dependent on
temperature.

±td-~"'Hf'

-IH-IH-t-+-++-H--i

5.0

Vee· 5.0V

1

m--R~.j.-'-H\\\-+-+++-+-H
5.0

10

15

As discussed previously power consumption is a
function of CpD, C L , Vee, f and ILEAKAGE. All
of these terms are essentially constant with tem·
perature except I LEAKAGE. However, the leakage
current specified on each 54C/74C device applies
Jcross the entir~' temperature range and therefore
represents a worst case limit.

FI GURE 11. Typical Gate Transfer Characteristics

The drain characteristics of Figure 9 and 10 show
considerable variation with temperature. Examina·
tion of the transfer characteristics of Figure 11

5·19

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Mike Watts
National Semiconductor

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2I

by the graphs in Figure 2. In order to build a usefully
stable oscillator it is necessary to add passive elements
that determine oscillation frequency and minimize the
effect of CMOS characteristics.

This is not a practical oscillator, of course, but it does
illustrate the maximum frequency at which such an
oscillator will run. All that must be done to make this a
useful oscillator is to slow it down to the desired
frequency. Methods of doing this are described later.

Ei5

of gate packages can be often used. The duty cycle will
be close to 50% and will oscillate at a frequency that
is given by the following expression.

1
f=

------ =

2x3x 17x 10-9

9.8 MHz

0.405 R2
R1 + R2

+ 0.693

)

Another form of this expression is:

f= - - - - - - - - - - - - - - - 2C (0.405 Req + 0.693 R 1 )

Lab work indicates this is low and that something closer
to 16 MHz can be expected. This reflects the conserva·
tive nature 'of the curves in Figure 2.

Where:

Since this frequency is directly controlled by propaga·
tion delays, it will vary a great deal with temperature,
supply voltage, and any external loading, as indicated

100

g

Propagation Delay vs
Ambient Temperature

Propagation Delay Time vs
Load Capacitance

MM54COO/MM74COO.
MM54C02/MM74C02.
MM54C04/MM74C04

MM54COO/MM74COO.
MM54C02. MM74C02.
MM54C04/MM74C04

MM54COO/MM74COO.
MM54C02. MM74C02.
MM54C04/MM74C04

~

i

-I-- CL1"J pF

.L-~

20

->-

I

1
C I. 50 pF
L~

GO
40

50

vc~· 5.0V
-SEE AC TEST CIRCUIT

80

~

R1 R2
R1 + R2

=

Propagation Delay vs
Ambient Temperature

>-

g

Req

~l -

~

g

40

z

0

~ I-"

I
I

;:::
~

i

,/
CL

30

'

50 pF....... ........

J....--r
CL -15 pF

20

-:g

- ~H ;~~~ST C,IRCUIT

--~

--

10

;:::

>-

g
z

LLJ

vcc=5i~

V

0

I

L

100

;:::

I

/! TA ·25°C
I-Vcc = l.OV ltft--SEE AC TESTCIRCUIT
-

50

L.-'

-50 -25 0

25 50 15 100 125

r-"""
20

III

vcc=I~F"'

)....oI-1"'J]

~

20

~

~15V
UJJ

J.

I
-50 -25 0 25 50 75 100 125

150

100

50

AMBIENT TEMPERATURE (OC)

AMBIENT TEMPERATURE (OC)

CL -LOAD CAPACITANCE (pF)

(a)

(b)

(c)

FIGURE 2. Propagation Delay for 74C Gates

5·21

n

r-

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en

FIGURE 3. Three Gate Oscilaltor

~--

en

:lJ

V

AI

v,

2 R1 C (

o

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aUT

c

A2

Assume the supply voltage is 10V. Since only one input
is driven by each inverter, the load capacitance on each
inverter is at most Olbout 8 pF. Examine the curve in
Figure 2c that is drawn for Vee = 10V and extrapolate
it down to 8 pF.We see that the curve predicts 03
propagation delay of about 17 ns. We can then calculate
the frequency of oscillation for three inverters using the
expression mentioned above. Thus:

s:

o

Figure 3 illustrates a useful oscillator made with three
inverters. Actually, any inverting CMOS gate or combina·
tion of gates could be used. This means left over portions

An eXOlmple may be instructive.

(X)

n

en

STABLE RC OSCILLATOR
To determine the frequency of oscillation, it is necessary
to examine the propagation delay of the inverters.
CMOS propagation delay depends on supply voltage and
load capacitance. Several curves for propagation delay
for National's 74C line of CMOS gates are reproduced
in Figure 2. From these, the natural frequency of
oscillation of an odd number of gates can be determined.

........

150

en
a:
o

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()

0.559

f~-­

IfRl=R2=R

RC

CI'J

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o
:iE
()
ClO
~

'7
Z

«

Figure 5b, which obviously will not oscillate. This
illustrates that there is some value of Cl that will not
force the network to oscillate. The real difference
between this two gate oscillator and the three gate
oscillator is that the former must be forced to oscillate
by the capacitor while the three gate network will
always oscillate willingly and is simply slowed down by
the. capacitor. The three gate network will always
oscillate, regardless of the value of Cl but the two gate
oscillator will not oscillate when Cl is small.

The following three special cases may be useful.

If R2

If R2

0.455

»> Rl

f~-­

RC

«< Rl

f~

0.722
RC

MM74C04

Figure 4 illustrates the approximate output waveform
and the voltage V 1 at the charging node.

. MM74C04

MM74C04

MM74C04

3/2Vee

(al

Vee

(bl

FIGURE 5. Less Than Perfect Oscillator

V,
112 Vee

GND

The only advantage the two gate oscillator has over the
three gate oscillator is that it uses one less inverter.
This mayor may not be a real concern, depending on the
gate count in each user's specific application. However,
the next section offers a real minimum parts count

-1/2 Vee

oscill~tor.

Vee
VOUT

A SINGLE SCHMITT TRIGGER MAKES
AN OSCI LLATOR

OV

Figure 6 illustrates an oscillator made from a single
Schmitt trigger. Since the MM74C14 is a hex Schmitt
trigger, this oscillator consumes only one sixth of a
package. The remaining 5 gates can be used either as
ordinary inverters like the MM74C04 or their- Schmitt
trigger characteristics can be used to advantage in the
normal manner. Assuming these five inverters can be used
elsewhere in the system, Figure 6 must represent the
ultimate in low gate count oscillators.

FIGURE 4. Waveforms for Oscillator in Figure 3

Note that the voltage V2 will be clamped by input
diodes when V 1 is greater than Vee or more negative
than ground~ During tt}is portion· of the cycle current
will flow through R2. At all other times the only current
through R2 is a very minimal leakage term. Note also
that as soon as V 1 passes through threshold (about 50%
of supply) and the input to the last inverter begins to
change, V 1 will also change in a direction that reinforces
the switching action; i.e., providing positive feedback.
This further enhances the stability and predictability of
the network.
This 'oscillator is fairly insensitive to power supply
variations due largely to the threshold tracking close to
50% of the supply voltage. Just how stable it is will be
determined by the frequency of oscillation; the lower
the frequency the more stability and vice versa. This is
because propagation delay and the effect of threshold
shifts comprise a smaller portion of the overall period.
Stability wiil also be enhanced if Rl is made' large
enough to swamp any variations in the CMOS output
resistance.

FIGURE 6. Schmitt Trigger Oscillator

Voltage V 1 is depicted in Figure 7 and changes between
the two thresholds· of the Schmitt trigger. If these
thresholds were constant percentages of Vee over the
supply voltage range, the oscillator would be insensitive
to variations in Vee. However, this is not the case. The
thresholds of. the Schmitt trigger vary enough to make
the oscillator exhibit a good deal of sensitivity to Vee.

TWO GATE OSCILLATOR WILL NOT
NECESSARILY OSCILLATE

Applications that do not 'require extreme stability or
that have access to well regulated supplies ·shoul.d not
be bothered by this sensitivity to Vee. Variations in
threshold can be expected to run as high as four or five
percent when Vee varies from 5V to 15V.

A popular oscillator is shown in Figure 5a. The only
undesirable feature of this oscillator is that it may not
oscillate. This is readily demonstrated by letting the value
of C go to zero. The network then degenerates into

5·22

that can be obtained. Obviously, the fewer inverters
that are used, the higher the maximum possible frequency.

Vee
VOUT

~

00

GND
Vee
VTH

»
z
(")

CONCLUSIONS

f--~--+--+---+---l--+

A large number of oscillator applications can be imple·
mented with the extremely simple, reliable, inexpensive
and versatile CMOS oscillators described in this note.
These oscillators consume very little power compared
to most other approaches. Each of the oscillators
requires less than one full package of CMOS inverters of
the MM74C04 variety. Frequently such an oscillator can
be built using leftover gates of the MM74COO, MM74C02,
MM74C10 variety. Stability superior to that easily
attainable with TTL - oscillators is readily attained,
particularly at lower frequencies. These oscillators are
so versatile, easy to build, and inexpensive that they
should find their way into many diverse designs.

VTL
GNDf--~-~--+---+---l--+

FIGURE 7. Waveforms for Schmitt Trigger Oscillator
In Figure 6

A CMOS Crystal Oscillator

Figure 8 illustrates a crystal oscillator that uses only
one CMOS inverter as the active element. Any odd
number of inverters may be used, but the total propaga·
tion delay through the ring limits the highest frequency

FIGURE 8. Crystal Oscillator

5·23

s:o

en

o

en
(")
r-

E
o
::J:J

en

Thomas P. Redfern
National ~ Semiconductor

USING THE CMOS'~DUALM6NOSTABLE MULTIVIBRATOR
INTRODUCTION

To trigger the one-shot the CLR input must be high.
The gating: G, on the comparator is designed such that
-.the comparator output is high when the one-shot is in
its stable state_ With the CLR input high the clear input
to FF is disabled allowing the flip-flop to respond to the
A' or B input. A _negative transition on A or a positive
-transition on B sets O-toa high state. This in turn gates
Nl OFF, and N2and the comparator ON.

The MM54C221/MM74C221 is a dLal CMOS monostable
multivibrator. Each one-shot has three inputs (A, Band
CLR) and two outputs (0 and 0). The output pulse
width is set by an external RC network.
The A and B inputs trigger an output pulse on a negative
or positive input transition respectively. The CLR input
when low resets the one:shcii. One-e trig-gered the AandB
inputs have no further control on '·the output.

,Gating -N2- ON establishes a reference of 0.63 Vee on
. the comparator's positive input.· Since the voltage on
C EXT can not change instantaneously V1 = OV at this
time. The comparator then will maintain its one level on
the output. Gating Nl. OFF allows C EXT to start,~harging
through R EXT toward Vee exponentially.

THEORY OF OPERATION
Figure l' sh~ws' that in its stable state, the one-shot
clamps CEX~ to ground by' turning Nl ON and ho'ids
the positive comparator input at Vee by turning N2
OF F~ The prefix N is usedto denote N-channel transistors_

Assuming a perfect comparator (zero. offset and infinite
gain) when the voltage on C EXT , Vl, equals 0_63 Vee
the comparator output will go from a high state to a
low state resetting 0 to a low state. Figure 2 is a timing
diagram summarizing this sequence of events.

The signal,':G, gatingN2 OFF also gates the comparator
OFF thereby keeping the internal power dissipation to
an absolute minimum. The only power dissipation when
in th'e stabi~ st~te is that 'generated by the current
through R EXT . The bulk "of this dissipation is in R EXT
since the voltage drop across ,N1 is v'ery smailfor norlTlal
ranges of R EXT'.
.
-

This diagram is idealized by assuming zero rise and fall
times and zero propagation delay but it shows the basic operation of the one-shot. Also shown is the' effect of
taking the CLR input low. Whenever CLR goes low FF

Vee

- -- Vee

,

0

16

R·

GNDo-~,-~~~~----~~--~

B _
Vee

'. ~ '. .

." FfGUR E 1; Monostable MultivibratorLogic Diagram;

5·24"; .

CLR

:

_ _ _ _ _ _ _ I'- __ .1I

COMPARATOR
OUTPUT

FIGURE 2. OneoShot Timing Diagram

is reset independent of all other inputs. Figure 2 also
shows that once triggered, the output is independent of
any transitions on B (or A) until the cycle is complete.

because the leakage and ON impedance of transistor N1
have a minimal effect on accuracy with this value of
resistance.

The output pulse width is determined by the following
equation:

Two values of CexT were chosen, 1000 pF and a.l#lF.
These values give pulse widths' of 1a~s and 1aoops with
REXT = 10 kil ..

Vl :;V cc (1-e-T/AEXTcEXT)=0.63Vcc

(1 )

Flgures 3 and 4 show the resulting distributions of pulse

(2)

Because propagation de/~y$, at the same power supply
voltage, ar:e the same independent of pulse wldth, the
shorter the pulse wldth the more the accuracy is

widths at 25~ for various power supply voltages.

Solving for t gives:
T = REXT CEXT In (1/0.37) = REXT CEXT

...

TA =25 C
RUT '10k I I
CUT' 1000 pF

u

A word of caution should be given in regards to the
ground connection of the external capacitor (C EXT )'
It should always be connected as shown in Figure 1 to
pin 14 or 6 and never to pin 8. This is· important
because of the parasitic resistor R*. Because of the large
discharge current through R*, if the capacitor is connected to pin 8, a four layer diode action can result
causing the circuit to latch and possibly damage itself.

~

\5

tl

0

...~
...::>z

oa

u

Vee' 5V
Vee' I OV. Vee =15V

:;l 0.6

:;

...>
0:

0.2

ACCURACY

At Vee = 5V,
At Vee' lOV,
At Vee' 15V.

Tw - 10.&"1
Tw -10,,1 .
Tw' 9.1;,s

,.,.:.nt.ge of unitl within' 4%:
At Vee' 5V,
At Vee' lOV,
At Vee = 15V.

0.4

g

90'10 of unilS
95% of unitl
98% Olunitl

!I
5

2 0 2

5

OUTPUT PULSE WIDTH (Tw• II)

There are many factors which influence the accuracy of
the one-shot. The most important are: .
a.
b.
c.
d,
e.
f.
g.
h.
i.

0% Poinl pulse width:

1.0

FIGURE 3. Typical Pulse Width Distribution for 10J.ls Pulse.

Comparator input offset
Comparator gain
Comparator time delay
Voltage divider Rl, R2
Delays in logic elements
ON impedance 9f Nl and N2
Leakage of N1
Leakage of CEXT
Magnitude of RexT and CEXT

u

TA • 25 C
REXT ·10k
tEXT' '.lpF

...z

§
:;

...

c.>

D.'

~....

0.'

0:

0.2

~
>

~

The characteristics of CExTand REXT are, of course,
not determined by the characteristics of the one-shot.
In order to establish the accuracy of the one-shot, devices
were tested using an external resistance of 10 kil and
various capacitors, A resistance of 10 kil was chosen

a::

all pulse width:

1.0

AI Vee - SV.
At Vee - lOV.
AI Vee'

If

nv.

'I

Tv< • 1020,,1
Tw' 1000"s
Tw' IIIZi'1

Perunllg. of unitswilhin '4%:

'.4

..

I

Vee' 5V
~Vee -10V
.liVee -15V

E

AI Vee' iV.
AI Vee' lOV.
AI Vee = 15V,

8S% of units
'7% of units
91% of unill

III

-5 -2 0 Z 5

OUTPUT PULSE WIDTH (Tw• II)

FIGURE 4. Typical Pulse Width Distribution for 1000J.lI Pulse.

5-25

affected by propagation .delay. Figures 3 and 4 clearly
show this effect. As pointed out in application. note
AN·90, 54C174C Family Characteristics, propagation
delay is a function of Vee. Figure 3, (Pulse Width =
laps) shows, much greater variation with Vee than
Figure 4 (Pulse Width 1000J./s). This same information
is shown in Figures 5 and 6 in a different format. In

Figure 7 shows typical power dissipation vs Vee
operating both sides of the one·shot at 50% duty cycle.
Also shown in the same figure is typical minimum pulse
width vs Vee. The minimum pulse width is a strong
function of ihternal propagation delays. It is obvious
from these two curves tha t increasing V cc beyond 10 V
will not appreciably improve inaccuracy due to propa·
gation delay but will greatly increase power dissipation.

=

.

~
~

~

~

g

~ ~~

I""'-'l:

•

'10!'s.
10 kn
1000 pF

~ V.l:~

r~'r.-

No(

iw
~

Accuracy is also a function of temperature. To determine
the magnitude of its effects the one·shot was tested at
temperature with the external resistance and capacitance
maintained at 25°C. The resulting variation is shown in
Figures 8 and 9.

_25OC~

:T,

V/JK.I:IX

ffi
;:

..i •.

REXT
CEXT

L'l'/lo.

17,.,.,.

I"'oG

-2

,

N

-4

r/. ~
I:j// -'l:

// V7:
1"0'0"-':: CL

....
....

~g

Vee (V)

0
0:
0:

""'"

W

~I:'L

:z:

....

oC(

-2

"-

-4

'"

~

*'~eg

15

.... "
iE ~
"'>
0 ....

,

800

~

1,\

t 600

~~
::!!

~r-..

~ I~

I"""- t-IL

)(

~i

o

125

V l-

100
75

50
25

~
j....ooi'
5

175
150

V

200

;;:

~

J

1/

"

•

;~ 400
:;;

1/

225
200

T""

1.5

~V

PULSE WIDTH = 1000J.ls

1.0
0.5

r--""

;:3

:lC(
9> -0.5

~-

~u

-,,,,

5~
~~

-1.0

F-l!V

1""+00

-t5
-55

t-

,....

25

125

TA - AMBIENT TEMPERATURE ( CI

FIGURE 9. Typical Pulse Width Error vs
Temperature (PW = 1000/-ls).

Up to this point the external timing resistor, R EXT , has
been held fixed at 10 kn. In actual applications other
values may be necessary to achieve the desired pulse
width. The question then arises as to what effect this
will have on accuracy .

....
-<

250

rc)

2.0

~C(

The minimum error can be obtained by operating at
the maximum V co A price must be paid for this and
this price is, of course, increased power dissipation.

.'25c~

125

25

WW

these figures the percent deviation from the average
pulse width at 10V Vee is shown vs Vee. In addition
to the average value the 10% and 90% points are shown.
These percentage points refer. to the statistical distribution of pulse width error. As an example, at Vee = 10V
for 10J./s pulse width, 90% of the devices have errors of
less than +1.7% and 10% have errors less than -2.1 %.
In other words, 80% have errors between +1.7% and
-2.1%.

t

-li

FIGURE 8. Typical Pulse Width Error vs
Temperature (PW = 10J..Ls).

....
U

I-f-

r-r-

1,..0

TA - AMBIENT TEMPERATURE

V//'7;
-~ ~-'l:
, T - 1'0'<:'-<::

1000

15V

-55

Vee (V)

~~

-4

;;:

FIGURE 6. Typical Percentage Deviation from
Vee =10V Value vs Vee (PW = 1000J..Ls).

~~

-,u

r-t-~

1.-,"",

fUr.

10

w"

-2

~~

-6

oS

"'w
"''''
C('"
UN

//

'"-'

10~

3:>

Puise Width ' 1000!'s
REXT -10 k!!--+CEXT = 0.1
:A • 25'C_f--+90%-

=10!,s

I

"' ....

.::::t:

'"

PULSE WIDTH

~ I~

FIGURE 5. Typical Percentage Deviation from
Vee· 1dv Value vs Vee (PW =10J..Ls).

~

'"'"

~~

15

10

iw

1-1- I-!-~v

0

-6

~~

Vee

0 l>
~ ...

~~

:Ill>

~~

Zn
0') ""

_--..---41---

==~m
'"

~~

vlt)

CEXT

~~
~~

L - -. .----4~_ov

_....
~~

FIGURE 10.

3 :z:

10

15

~~

As REXT becomes larger and larger the leakage current
on t"ransistor Nl becomes an ever increasing problem.
The equivalent circuit for this leakage is shown in
Figure 10.
.

vee (VI

FIGURE-7. Typical Minimum Pulse Width and
Power Dissipation vs Vee.

5-26

l>
v(t) is given by:

As before, when v(t)
Solving for tL gives:

We have just defined the limitation on the maximum size
of AEXT ' There is a corresponding limit on the minimum size that REXT can a~sume. This is brought about
because of the finite ON impedance of N1. As REXT is
made smaller and smaller the amount of voltage across
N1 becomes significant. The voltage across Nl is:

0.63 Vee, the output will reset.

=

(4)

. The output pulse width is defined by:

=

PW Error

tL - T
T

v (to) = (Vee - VN1 ) (1 - e-to/REXT eEXT)
+ V N1 = 0.63 Vee

x 100%

Solving for to gives:

PW Error

"
"

II

1.0

>-

V

F7 7'

~

V

0.01
0.001

_

Vc e - 15V
1111111

0.01

to

REXT CEXT Qn (1/0.37)

10.0

~

z

11111111

0.1

0

0

1.0

>::::>

ILEAKAGE X REX. (V)

1.0

0

c:
0
c:
c:

FIGUFIE 11. Percentage Pulse Width Error Due to Leakage.

::t:

>0

0.1

~

To demonstrate the usefulness of Figure 11 an example
will be most helpful. Let us assume that N1 has a
leakage of 250 x 10-9 amps, CEXT has leakage of
150 x 10-9 amps, output pulse width = 0.1 seconds and
Vee = 5V. What REXT CEXT should be used to
guarantee an error due to leakage of less than· S%.

::::>

0.01

< 3S0

lOOk

1M

FIGUR E 12. Percentage Pulse Width ErJor
Due to Finite rON of Transistor N1 vs REXT.

the 50n curve in Figure 12, REXT must be greater than
10 kn to maintain this accuracy. At Vee = 10V, REXT
must be greater than 5 kn as can be seen from the 2Sn
curve in Figure 12.

Then:

< 0.14/(250 + lS0)

10k

REX. (!!)

From Figure 11 we see that to meet these conditions
R EXT IL < 0.14V.

REXT

L-.L..J..J.JJ.IIllI-.-1...l..U.llW..3

This function is plotted in Figure 12 for rON of son,
25n and 16.7n. These are the typical values of rON for
a Vee of SV,.10V and lSV respectively.

/

0

c:
c:
c:

o
~

REXT CEXT Qn(1/0.37)

0

::::>.

-

0.37 Vee

/

Vee = 5V

o
z

x 100%

Vee - VN1)

10.0

C')

3:
oen

3:

REXT CEXT Qn ( - - - -

g
IIIII

T

G')

l>

Substituting Equations 2 and 4 gives:

PW Error is plotted in Figure 11 for Vee =: 5, 10 and
15V. As expected, decreasing Vee causes PW Error to
increase with fixed IL' Nqte that the leakage current,
although here assumed to flow through Nl, is general
and could also be interpreted as leakage through CEXT '
See MM54C221 /MM74C221 data sheet for leakage limits.

Cl

=

en
z

r-

Pulse Width Error is then:
to -T

CO

c:

c
c:

to = REXT CEXT Qn (Vee - VN1)
0.37 Vee

Substituting Equations 2 and 3 gives:

I

-I
:::J:
m

(3)

Using T as defined in Equation 2 the pulse width error is:

Z

....
W

!:i
<:
O'J
:::tI

-~

o

:::tI

TYPICAL APPLICATIONS
Vee

Basic One·Shot Oscillator

Vee
114MM14C3Z
OUTPUT

I/ZMM74C2Z1
QZ

I/2MM74C73

..

ft·~-+-+

~~r-~x~

________________________

~

....._ _....1

Retriggerable One-8hot

Vee' 3Y 'DISV

RS

RZ

RI

IV

FREQUENCY TO DC CONVERTEA
Yooc • Vee • RI • CI • f

LEVEl DETECTDII
Y~ • I FOR f > 1141((113 + R411AI • ,CIlI
Yo -I 'DR f < A41((R3 + R411AI • CIlI

Frequency Magnitude Comparator

5-28

l>

TYPICAL APPLICATIONS (Continued)

i'l

:2
I

~

eN
CX)

Vee

C

en
:2

G')

-t

::J:
m·.
(")

S:.
• f

&

Vlfr~jR1 . C1 . Vee

o

en

o

' M .,

I/IRI· CI' 2· RS· C2)

c

~

r

s:

Voe' RI· CI . I Vee

o

GNO----------~--~------------~~------------~
Linear

:2

veo

o

en

VI--~------------------------·----------------------------------------------~

l>
tJl

r"""---~-----._-v~e

C.I;.F

SICk

Vee

I·

:

. An,alog r.,hilt;Plier/Divider
I

-t

'

,

J.

5-29

I

·r

m

.-2

Gerald Buurma
National Semiconductor

w
2

o
Q.
~

o
(".)
2

CMOS SCHMITT TRIGGER
A UNIQUELY VERSATILE DESIGN' COMPONENT

(!)
C/)

INTRODUCTION

ANALYZING THE CMOS SCHMITT

The Schmitt trigger has found many applications in
numerous circuits, both analog and digital. The versa·
tility of a TTL Schmitt is hampered by its narrow
supply range, limited interface capability, low input
impedance and unbalanced output characteristics. The
Schmitt trigger could be built from discrete devices to
satisfy a particular parameter, but this is a careful an'd
sometimes time-consuming design.

The input of the Schmitt trigger goes through a standard
input protection and is tied to the gates of four stacked
devices. The upper two are P-channel and the lower two
are N-channel. Transistors P3 and N3 are operating in the
source follower mode and introduce hysteresis by
feeding back the output voltage, out', to two different
points in the stack_

W

C
W
...J

~

C/)

a:
w

>
~
w

:::>

o
2

:::>

«

I
a:
w

(!)
(!)

The CMOS Schmitt trigger, which comes six to a
package, uses CMOS characteristics to optimize design
ahd advance into areas where TTL could not go. These
areas include: interfacing with op amps and transmission
lines, which operate from large split supplies, logic level
conversion, linear operation, and special designs relying
on a CMOS characteristic. The .CMOS Schmitt trigger
has the following advantages:
•
•

.-a:
~

•

~

::I:
U
C/)
C/)

o

~

u

•

When the input is at OV. transistors P1 and P2 are ON,
and N1. N2 and P3 are OFF. Since out' is high, N3 is
ON and acting as a source follower, the drain of N 1,
which is the source of N2, is at Vee-V TH . If the input
voltage is ramped up to one threshold above ground
.transistor N1 begins to turn ON, N1 and N3 both being
ON form a voltage divider netw9rk biasing the source of
N2 at roughly half the supply. When the input is a
threshold above 1/2 Vee, N2 begins to turn ON and
regenerative switching is abo'ut to take over. Any more
voltage on the input causes out' to drop. When out' drops,
the source of N3 follows its gate, which is out', the
influence of N3 in the voltage divider with N1 rapidly
diminishes, bringing .out' down further yet. Meanwhile
P3 has started to turn ON, its gate being brought low by
the rapidly dropping out'. P3 turning ON brings the
source of P2 low and turns P2 OFF. With P2 OFF, out'
crashes down. The snapping action is'due to greater than
unity loop gain through the stack caused by positive
feedback through the source follower transistors. When
the input is brought low again an identical process occurs
in the ·upper portion of the stack and the snapping
action takes place when the lower threshold is reached.

High impedance input (10'2n typical)
Balanced input and output characteristics
• Thresholds are typically symmetrical to 1/2 Vee
• Outputs source and sink equal curr~nts
• Outputs drive to supply rails
Positive and negative-going thresholds show low
variation with respect to temperature
Wide supply range (3-15V), split supplies possible

• . Low ··'Power consumption, even during transitions
•

High noise immunity, 0.70 Vee typical

Applications demonstrating how each of these characteristics can become a design advantage will be given
later in the application note.

o

-«2
~

Vee

Vee

L

J

I

Vee

P1

J

--f I

:h:q

P6

our

1NPUT

OUTPUT

I P4

I N2

y;;~
I N1

Vee

1

1FI~URE

I N4

1. CMOS Schmitt Trigger'

.5-30

Out' is fed into the inverter formed by P4 and N4;
another inverter bui It with very small devices, P5 and
N5, forms a latch which stabilizes out'. The output is
an inverting buffer capable of sinking 360,uA or two
LPTTL loads.

typically 3.6V of threshold difference, enough hysteresis
to overcome almost any spurious signal on the input.
A comparator is often used to recover information sent
down an unbalanced transmission line. The threshold of
the comparator is placed at one half the signal amplitude
(See Figure 4b). This is doen to prevent slicing level
distortion. If a 4,us wide signal is sent down a transmission
line a 4,us wide' signal should be received or signal distortion occurs. If the comparator has a threshold above half
the signal amplitude, then positive pulses sent are shorter
and negative pulses are lengthened (See Figure 4c). This
is called slicing level distortion. The Schmitt trigger does
have a positive offset, VT+, but it also has a negative
offset VT -. In CMOS these offsets are approximately
symmetrical to half the signal level so a 4,us wide pulse
sent is also recovered (see Figure 4d). The recovered
pulse. is delayed in time but the length is not changed,
so noise immunity is achieved and signal distortion is not
introduced because of threshold offsets.

The typical transfer characteristics are shown in Figure
2; the guaranteed trip point range is shown in Figure 3.

WHAT HYSTERESIS CAN DO FOR YOUR
Hysteresis is the difference in response due to the direction of input change. A noisy signal that traverses the
threshold of a comparator can cause multiple transitions
at the Olltput, if the response time of the comparator is
less than the time between spurious effects. A Schmitt
trigger has two thresholds: any spurious effects must be
greater than the threshold difference to cause multiple
transitions. With a CMOS Schmitt at Vee = 10V there is

»
z
I

-'
~

o

n
3:

oen

en

n
:I:
3:

=1
-f
::XI
G)
G)

m
::XI

L

»
c

z

zo
?:

Vee = 15V

m

15

!<

Vr_

<:>

~>
...
...

oC
<
m

10

::>

::XI

en

::>
0

~

10

INPUT

VOLT~GE

r=

m

20

15

(V)

C

FIGURE 2. Typical CMOS Transfer Characteristics
for Three Different Supply Voltages.

t

m

en

G)

z
n
o
3:
VT •

A~~~~TAULOE

i

FIGURE 3. Guaranteed Trip Point Range.

VTH

1-:-o1'IJ.I----'\I\-'---'IP.

vr -

a) Received signal from transmission
line with thresholds at different
amplitudes.

"'0

o

Z
m
Z

-f
1 LEVEL

b) Recovered signal from comparator
with threshold VYH has multiple
tranSitions.

oLEVEL

c) Recovered signal hom comparator
with POSitiV8 offset on threshold. Vr ...
positive pulse shorten, negative pulse
lengthen.

1 LEVEL

oLEVEL

dl Recovered ,ignal with CMOS Schmitt
trigger, Vr • and VT • Restores true
waveform.
Recovered signal from Schmitt is Sime

1 LEVEL

oLEVEL

widthlscomparlto,withthreshold.t
VyH.lnd is only delayed in timl.

o

1

Z

3

4

5

6

1

8

910

TIME (",I

FIGURE 4. CMOS Schmitt Trigger Ignores Noise

5-31

IZ

w

Z

oc..

Vee

~

o

veeJUlJ

(.)

z

BIASPOINT- -

-

-

-

-

-

-

(!)

en
w

Vss

c

W
..oJ

., Capacitor impedancl.t lowest opera tin, frequency should be much less than RIIA = 1/2 R.

~

Vee

en
a:

w

>
~

.. ~:::

,

w
::>

"z
::>

+
Vss

b) By using split supply (11.5 10 ±1.5) direct inlerl,,! il.chieved.

. FIGURE 5. Sine to Square Wave Converter with Symmetrical Level Detection.

«
a:

w

(!)

S2
a:

l-

t:

~
:I:
(.)

en
en
o

JV\.I\
NVVv

SUlJ

~

(.)

o

FIGURE 6. Diode Dump Tach Accepts any Input Waveform.

lilt


~

w
::>

o
z

::>
cd:

I

a:

w
Co!'
Co!'

a:

I-

The circUIt In Figure 9b is a differential Iine receiver
that recovers balanced transmitted data but ignores
unbalanced signals by latching up. If both circuits of
Figure 9 were used together, the error detector could
signal the transmitter to stop transmission and the fine
receiver would remember the last valid information bit'
when unbalanced signals persisted on the line. When
balanced signals are restored, the receiver can pick up
where it left off.

CMOS can be linear over a wide voltage range if proper
consideration is paid to the biasing of the inputs. Figure
11 shows a simple VCO made with a CMOS inverter,
acting as an integrator, and a CMOS Schmitt, acting as a
comparator with hysteresis. The inverter integrates the
positive difference between its threshold and the input
voltage V IN' The inverter output ramps up until the
positive threshold of the Schmitt trigger is reached. At
that time, the Schmitt trigger output goes low, turning
on the transistor through Rs and 'speeding up capacitor
Cs. Hysteresis keeps the output low until the integrating
capacitor C is discharged through RD. Resistor Ro
should be kept much smaller than RC to keep reset time
negligible. The output frequency is given by

The standard voltage range for CMOS inputs is Vee
+0:3V and ground -0.3V. This is because the input pro·
tection network is diode clamped to the supply rails. Any
input exceeding the supply rails either sources or sinks
a large amount of current through these diodes. Many
times an input voltage range exceeding this is desirable;
for example, transmission lines often operate from ±12V
and op amps from ±15V. A solution to this problem is
found in the MM74C914. This new device has an uncommon input protection that allows the Input signal to go
to 25V above ground, and 25V below Vee. This means
that the Schmitt trigger in the sine to square wave
converter, in Figure 5b, could be powered by ±1.5V
supplies and still be directly compatible with an op amp
powered by ±15V supplies.

V TH
(V T +

-

-

VIN
V T -) Ree·

The frequericy dependence With control voltage is given
by the derivative with respect to VIN So,

-1

A standard input protection circuit and the n~w input
protection are shown in Figure 10. The diodes shown
have a 35V breakdown. The input voltage can go positive
until reverse biased' 02 breaks down through forward
bias 03, which is 35V above ground. The input voltage
can go negative until reverse biased 01 breaks down
through forward, bias 02, which is 35V below Vee.
Adequate input fJrotection. against static charge is still
maintained.

where the minus sign indicates that the output frequency
increases as the input is brought further below the inverter
threshold. The maximum output frequency occurs when
VIN is at ground and the frequency will decrease as VIN
is raised up and will finally stop oscillating at the
inverter threshold, approximately 0.55 Vee.

1=

~
::t.

(.)

Vee

en
en

Vee
01

o

~

(.)

o

01
NORMAL
CMOS
INPUT
PROTECTION

~

02

CMOS
INPUT

200

MM74C914
INPUT
PROTECTION

02

CMOS
INPUT

200

'7

03

Z

-=

cd:

':"
.)
b)

FIGURE 10. Input Protection 'Diodes, in a) Normally Limit the I~put Voltage Swing to 0.3V above Vee and 0.3V
below Ground. In b) D2 or D1 is Reverse Biased Allowing Input Swings of 25V above Ground or 25V below VCC.

fo=·~

IVr. - vr ) RcC

Re
V,.o-~Nw--+---I

116MM74C04
Os V'N

S 112 Vee
Ro

FIGURE 11. Linear CMOS (Voltage Controlled Oscillator)

5-34

The 'pulses from the VCO output are quite narrow
because the reset time is much smaller than the integration time. Pulse stretching comes quite naturally to a
Schmitt trigger. A one-shot or pulse stretcher made with
an inverter and Schmitt trigger is shown in Figure 12.
A positive pulse 'coming into the inverter causes its
output to go low, discharging the capacitor through the
diode Dl. The capacitor is rapidly discharged, so the
Schmitt input is brought low and the output goes
positive. Check the size of the capacitor to make sure
that inverter can fully discharge the capacitor in the
input pulse time, or

ISINK INVERTER>

C

~V =

The Schmitt trigger, built from discrete parts, is a careful
, and sometimes time·consuming design. When introduced
in integrated TTL, a few years ago, many circuit designers
had renewed interest because it was ,a building block
part. The input characteristics of TTL often make biasing
of. the trigger input difficult. The outputs don't source
as much as they sink, so multivibrators don't have 50%
duty cycle, and a limited supply range hampers interfacing with non 5V parts.
The CMOS Schmitt has a very high input impedance with
thresholds approximately symmetrical to one half the
supply. A high voltage input is available. The outputs
sink and source equal currents and pull directly to the
supply rails.

~V + ~V

~T

where
width.

THE SCHMITT SOLUTION

R

Vcc for CMOS, and

~T

is the input pulse

A wide threshold range, wide supply range, high noise
immunity, low power consumption, and low board
space make the CMOS Schmitt a uniquely versatile
part.

For very narrow pulses, under 100 ns, the capacitor can
be omitted and a large resistor will charge up the CMOS
gate capacitance just like a capacitor.

l>
Z
I
~

~

o

n

s:o

CJ)
CJ)

n

:I:

s:
~

-4
jJ

G')
G')

m
jJ

I

l>

c
Z

Use the Schmitt trigger for signal conditioning, restoration of levels, discriminating noisy signals, level detecting
with hysteresis, level conversion between logic families,
and many other useful functions.

When the inverter input returns to zero, the blocking
diode prev~nts the inverter from charging the capacitor
and the resistor must charge it from its supply. When
the input voltage of the Schmitt reaches VT+' the
Schmitt output will go low sometime after the input
pulse has gone low.

The CMOS Schmitt is one step ciosl)r to making design
limited only by the imagination of the designer.

m

!<

<
m
jJ
CJ)

~

rm
C
m

Vee

1/6 MM14C14

1/6MM14C04

o
C

CJ)

01

~>---~I~--~----~~
I .....

G')

z

n
o

T = RC ~n (Vee - VB') BE SURE THAT
Vee - VT+

'SINKINV'AT'A'

C Vee +
t

~
A

FIGURE 12. Pulse Stretcher. A CMOS Inverter Discharges a Capacitor,
a Blocking Diode allows Charging through R only. Schmitt Trigger
Output goes Low after the RC Delay.

5-35

s:""C
o
Z

m

Z

-4

~

JULY 1976

't:

Gerald Buurma
National Semiconductor Corp.

n:J

!

,5
t/J

o

~

(.)
Q)

Q.

E

'Ci)

.c
...,
'~
"'C
Q)

,~

cti
Q)

...

~.

~

dual polarity 3%-digit DVM realized with simple CMOS interface

,~
CO)

:s
I

~

M

~

'i:
n:J

'0

c.

block integrator becomes a positive integrator for posi·
tive voltage inputs or a negative integrator for negative
voltage inputs. This way a single reference serves as a
standard for either polarity voltage at the analog input.

Two powerful building blocks, the LF11300 dual slope
analog building block and the MM74C928 CMOS 3%·
decade counter with 7-segment outputs, are easily mated
with a simple CMOS interface to produce an auto·zero,
auto·polarity 3%·digit DVM.

These preparations occur at the beginning of every
conversion cycle, and all control signals are non·over·
lapped by one gate delay by the control logic so that
stored offset voltages are not disturbed.

The LF11300 has a very high impedance FET input and
internal circuitry for automatic offset correction and
polarity determ ination. Only a single 2·volt reference is
needed for both positive and negative full-scale readings
of 1999.
The MM74C928 is a 3%·decade counter that directly
drives an LED display with multiplex 7 segment information. The multiplexing circuit has its own free running oscillator and requires, no external clock. The i'nterface circuitry provides non·overlapping control signals
to the LF11300 for polarity determination and offset
correction for every conversion cycle, and also provides
clock and display update control signals to the
MM74C928.
A conversion cycle is begun by a positive edge on fl ipflop D 1: additional transitions do not affect this input
. until the Conversion Complete signal is received at the
end of the cycle. Schmitt Trigger S1 generates 10ms
pulses wh ich are converted into control signals by the
Logic circuitry.

The rest of the conversion cycle is a standard dual slope
conversion where the unknown is integrated for 2000
counts and the reference is integrated until the internal
comparator indicates a zero crossing of the integrated
voltage.
The comparator going low generates a serie~ of control
pulses to the MM74C928. The first control pulse latches
the count into an internal register. The second control
pulse resets the interface logic for a new cycle, and the
last pulse indicates the end of conversion.
For continuous operation, end of conversion can be tied
to start conversion and the display will update itself
. at the end of each conversion cycle.
If too large a voltage is present at the analog input or
if the external leads are switched in the middle of a
conversion cycle, the counter overflows and an overflow
light indicates this condition. The overflow light will
remain on until a valid conversion has been obtained.

Each conversion cycle is preceded by offset correction,
polarity determination, another offset correction, and a
ramp unknown signal into the LF11300. The offset
correction signals allow the analog building block to
store any internal offsets in its integrator and compara·
tor on an external capacitor. The LF 1.1300 uses this
stored offset voltage to automatically zero the display
when no voltage is present at the analog input. The
polarity determination signal samples the input voltage
and the comparator output of the LF11300 indicates to
the control logic whether to switch in ramp unknown
minus or ramp unknown plus. The analog building

All circuitry is automatically reset when power comes on
and waits until a conversion start signal unless used in
the continuous conversion mode.
The complete circuit of nine packages and external
components including a temperature compensated refer·
ence can be built on a 3 x 5-inch piece of vector board.
The analog circuit excluding reference requires only
1.5mA from each 12.5 V battery and the digital circuit
requires approximately 40mA from the 6V supply.
5-36

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O.OI"F (POLYSTYRENE)
Bl ' B2' 12.5V NICAO
01

13

VCC
START
CONVERSION

CDNV~~~lg~

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R

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......

3 ~UAL 0 C04013 0106
1 QUAD NAND MM74COO Al A4
1 QUAD NOR MM74C02 01·04
1 HEX SCHMITT MM74C14 51·56
1 HEX DIGIT DRIVER OS75492 001
1 MM74C928
lLFI1300

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10k
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02
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POSITIVE POLARITY

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FIGURE 1.3% Digit Voltmeter

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Designing with MM74C908,
MM74C918 Dual High
Voltage CMOS Drivers

National Semiconductor
Application Note .177
Jen-yen Huang
March 1977

INTRODUCTION
By combining the merits of both CMOS and bipola~
technologies on a single silicon chip, the MM74C908,
MM74C918 provides the following distinguished features as general purpose high voltage drivers.

•

•

Wide supply voltage range (3V to 18V)

•
•
•

High noise immunity (typ 0.45 Vccl
High input impedance (typ 1012n)
Extremely low standby power consumption (typ
750 nW at 15V)
Low output "ON" resistance (typ an)
High output drive capability (lOUT ~ 250 rnA at
VOUT = VCC - 3V, and Tj = 65°C)
High output "OFF" voltage (typ 56V at 200 /.lA)

•
•
•

Among these, the first 4 are typical and unique characteristics of CMOS technology which are fully utilized in this circuit to achieve all the design advantages in a typical CMOS system.
The high .output currents and low "ON" resistance
are achieved through the use of an NPN Darlington
pair at the output stage.

The circuitry for each of the 2 identical sections is
shown in Figure 1.
With both inputs sitting at logical "1" level, the
output of the inverter is also at logical "1", which
prevents the P-channel transistor from being turned
"ON"; therefore, the output is in its "OFF" state.
Only a small amount of leakage current can flow.
On the other hand, when one or both of the inputs
is at logical "0" level, the output of the inverter is
also at logical "0", which turns on the P-channel transistor and, hence, the Darlington pair.
POWER CONSIDERATION
. To assure junction temperature of 150°C or less, the
on-chip power consumption must be limited to within
the power handling capability of the packages. In
Figure 2, the maximum power dissipation on-chip
is shown as a function of ambient temperature for
both MM74C908 and MM74C918. These curves are
generated from (1) at Tj = Tj(MAX) = 150°C.
Tj = T A + PD 8jA

The MM74C908 is housed in an 8-lead epoxy dualin-line package, which can dissipate at least 1.14W.
The higher power version, MM74C918, comes in a
14-lead epoxy dual-in-line package, 'v'I(ith power capability up toa minimum of 2.27W.

(1 )

where Tj = junction temperature
T A = ambient temperature
PD = power dissipation
8jA = thermal resistance between junction and
ambient

~

Vee

:2

3000

I
I

o

~ 2600

D.

INPUT 1

~

2200

INPUT 2 ..r---" __ ~

ffi

1800

C

........

M~74e~1~ II
"

(IIJA = 55°e!W)

I'.

==

~
:: 1400

'" ,

:I

~ 1000 ~-

c:(

::
I

~
::

VOUT

~

I III
I III

"

1' .....

600 tMM74e9D8~
t-(IJJA = 11oo e/W)
200

0

~

roo..

r'\.

I""'-~,

......

I JII I

0 10

30

50

70

90 110

,

130 150

TA - AMBIENT TEMPERATURE (Oe)
FIGURE 1

FIGURE 2. Maximum Power Dissipation
Ambient Temperature

'5-38·

VI

A general application circuit for
MM74C918 is as shown in Figure 3.

the

l>

DESIGN TECHNIQUE

MM74C908,

...~2
I

In a typical design, R L must be chosen to satisfy the
load requirement (e:g., a minimum current to turn
on a relay) and at the same time, the power consumed
in the driver package must be kept below its maximum
power handling capability.

Vee

C

en
en
tE'
::::J

:l'

To minimize the design effort, a graphical technique is
developed, which combines all the parameters in one
plot, which can be used efficiently to obtain an optimal
design.
VOUTO

VOUTA

Assume T A = 25°C and that both sections of the
MM74e908 in Figure 3 are operating under identical
conditions. The maximum allowable package dissipation
is:

CC

~

;:;"

:r

s:
s:

.....,J
~

n

CD

o

CO

Po = 2

FIGURE 3

(Vee - VOUT) x lOUT
(6)

1
= - (150 - TA)

110

For both sections A and B;
Vee - VL
lOUT = - - - RON + RL

o

where Tj = 150 e, (JjA
the data sheet.

The device "ON" resistance,' RON, is a function of
junction temperature, Tj. The worst-case RON as a
function of Tj is given in (3).

=

POA + POB

= 120UTA '

'

=

o

110 e/W are used in (1) per

Po =

:r

(Vee - VOUT) x lOUT = 0.57W

For any given RL a load line (7) can be superimposed
on Figure 4.

1
1
lOUT = (Vee - VL) - (Vee - VOUT)
RL
RL

= lOon,

(7)

The slope of this load line is -l/RL a!1d it intersects
with the vertical and horizontal axes at l/R L (Vee VL) and Vee - VL respectively.

Assume:
RON = 12.28n
By (2):
10
lOUT A =

IOUTB

=

12.28 + 100

Given Vee and VL, a minimum RL can be obtained by
drawing the load line tangent to the constant power
curve. In Figure 4, at Vee - VL = 5V the line intersects lOUT axis at lOUT;: 450 mAo Thus, RL(MIN) =
5V/450 mA ;: 11.1n. Any RL value below this will
move the intersecting point up and cause a section of the
load line to extend into the shaded region. Therefore,
0
the junction temperature can exceed Tj(MAX) = 150 e
in the worst case if the circuit operates on such a section
of the load line.

0.089A

10
12.28 + 50

0.161A

By (4):

Po

= (0.089)2

, 12.28 + (0.161)2, 12.28

= 0.41W

By (1):
Tj = 70.5°e

Whether this situation will occur or not is determined'
by both the value of Vee - VL and the RON range of
the drivers.

And by (3):
RON

= 12.2Sn
5-39

::r::

tE'

(4)

Given RLA 'and RLB, (1), (2), (3), (4) can be used to
calculate PO, Tj, etc. through iteration.

CO

c:
e!.

A constant power curve Po = 0.57W can then be plotted
as shown in Figure 4. The circuit must operate below
this curve. Any voltage-current combination beyond it
(in the shaded region) will not guarantee Tj to be lower
o
than 150 e.
'

RON + 120UTB • RON

For example, let VL = OV, Vee = 10V, RLA
o
RLB = 50n, T A = 25°C, (JjA = 110 e/W.

...n
C

Thus, the maximum power allowed in each section is:

(3)

The total power dissipation in the device also consists of
normal CMOS power terms (due to leakage current.
internal capacitance, switching etc.) which are insignificant compared to the power dissipated at the output
stages. Thus, the output power term defines the allowable
limits of operation and is given by:

Po

.....,J
~

= 1.14W

CD

(2)

RON = 9 [1 + 0.008 (Tj - 25)]

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s:

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en

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700 1--~~~~~-+--+-+-+--t--+--t--+-+-+--t--1f--t---+-+-+-;

600

\----i'--¥\~~~_+__+_+_+__t_I__l__t_+_+_t__+__t_+__t___!
~~

MM7ie90

10
vee - vOUT (V)

FIGURE 4

By (3), at Tj = 150°C RON (MAX) = 18n, this is a
straight line* passing through the origin with a slope of
IOUT/(VCC - VOUT) = 1/18 mho and intersects the
load line at point A. Similarly, point Band C can be
found for typical (-10n) and minimum -(-5Q) RON
at Tj = 150°C.

3. Most importantly, a guarantee that the circuit will be
operating in the safe region, (Tj ~ 150° e).
For different ambient temperatures or for different
power considerations, Figure 4 can be applied by properly scaling the lOUT axis. (Note that lOUT ex: Tj - T A
and lOUT ex: PO).

For Vee - VL = 5V, the tangent point falls between A
and C. Hence, R L ~ 11.1 n calculated above must be
satisfied; otherwise, part of the load line within the
specified RON range will extend into the shaded region
and therefore, Tj ~ 150°C may occur.

550
~

500

"<

.§.

/

450
400
350

~
E 300

For VCC - VL = 10V, however, a section of the load
line can go beyond the Po = 0.57W curve without
affecting the safe operation of the circuit. By inspection
of Figure 4, the reason is clear-the load line extends
into the shaded region only outside of the specified
RON range (to the right of point A'). Within the RON
ran'ge, the load line lies below the Po = 0.57W curve,
thus, a safe operation.

-'

250

a::
>
....

200
150

;3

'V
V
1/
I

100
50

o

l7

/

V
Vee=5V _
Tj = 150°C

If
o 0.5 1 1.5 2 2.5 3 3.5 4 4.5' 5
Vee - VOUT (V)

To a first approximation**, the section of the load line.
between A and C is the operating range for the circuit at
Vee - VL = 5V and RL = 1l.1n. Hence, the available
current and voltage ranges for this circuit are 310 mA ~
lOUT ~ 172 mA and 3.4V ~ VOUT ~ 1.9V, respectively.

FIGURE 5. Typical lOUT vs Typical VOUT
*Strictly speaking, RON is a non-linear function of lOUT. A
0
typical RON characteristic at Tj = 150 C is shown in Figure 5.
The non·linear characteristic near the origin is due to the fact
that the output NPN transistor is not saturated. As soon as
saturation is reached (lOUT - 150 mAl the curve becomes a
straight line which extrapolates back to the origin. For practi·
cal design purposes, it is sufficient to consider RON as a linear
function of lOUT.

Thus, by simply drawing no more than 3 straight lines,
one obtains all of the following immediately:

1. . All the necessary design information (e.g., minimum
RL, minimum available lOUT and VOUT, etc.)
2. Operating characteristics of the circuit as a whole,
including the effect of different RON values due to
process variations, thus, a better insight into the
circuit operation.

**Note that as the operating point on the load line moves away
from the PD = 0.57W curve, (away from the tangent point in
this case), the actual junction temperature drops. Therefore, at
point A, for example, the device is actually running cooler than
0
Tj = 150 C, even in the worst case. Hence, RON value drops
below 18.11 and the actual operating point is slightly different
from A.
I,

5-40

To further simplify the design, a family of such curves
has been generated as shown in Figure 6. Each of these
curves corresponds to a particular TA and Po (per driver)
as indicated, and similar to the Po = O.S7W curve in
Figure 4, is generated from (6) by using appropriate T A
values. The application of these curves is illustrated as
follows:

The RL(MIN) given in (8) may not be a true
minimum if the tangent point does not fall inside
the specified RON region. The actual RL(MIN)
can be obtained as shown in Figure 7. The calculations and results are given in Table II.

Example 1
1. In Figure 3, assume that the two drivers in the
MM74e908 package are to operate under identical
conditions. Find minimum RL at T A = 2Soe, 4Soe,
6Soe and 8Soe for both Vee - VL = SV and VecVL = 10V.

Note that the RL(MIN) values in Table II are
lower than those given by (8). This corresponds to
the section on each of the 4 load lines in Figure 7
which extends beyond the power limit curve at
each associated temperature. However, this section
on each load line is outside the specified RON
range. Within the RON range, load lines are below
the power limits; therefore, safe operation is
guaranteed.

Then plot RL(MIN) vs T A.
a) Vee-VL=SV
By constructing the load lines tangent to the
curves for T A = 25°C, 45°C, 65°C and 8S oe,
RL(MIN) for each case can be obtained through
the vertical coordinate for the intersection points
as shown in Figure 6. These are calculated in
Table I.

The RL(MIN) vs T A plot is as shown in Figure 8.

All the curves generated so far are restricted to
Po :::; O.S7W due to our simplifying assumption
that both drivers are operating identically. In
Figure 9 a few more curves are added to account
for the 'general situation in which only the restriction POA + POB ~ 1.14W is required, (i.e., POA
can be different from POB). Application of
Figure 9 is illustrated as follows:

Note that the same resu Its (within graphical error)
can be obtained analytically by letting dR LI
dRON = O. It can be shown that
(Vee - VL)2
R L(MIN) =
(8)
4X (Max Power Per Driver)

TABLE I.
TA
IOUT@ 01, 2, 3, 4 (mA)

5
RL(MIN)

= IOUT@ 01,2,3,4

(.11)

25°C
450

45°C
375

65°C
310

85°C
240

11.1

13.3

16.1

20.8

25°C
261

4SoC
230

65°C
197

85°C
166

38.3

43.5

50.8

60.2

TABLE II.
TA
lOUT @ 01,2,3,4 (mA)

10
RL(MIN) = lOUT @ 01,2,3,4

(.11)

5·41

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700

~

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600

en

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~

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500

,L-

Po = D.57W

\\ !,....--'

Po = D.4BW

_U k

Po = D.39W

300

\.+ ~
~ 1\1\1
~ '\ l\'
N ~ ~\

:E
:E
........

200

K r-.... 1\~ ,',

0

100

:::l

C

Po = 0.3W

::)

.E
400

00

"""

0)

U

~

I"

03
.......

t'--.. ~ ~ ~
..........

00,
0)

/"

,//"

~ ~ ts: ~
[> ~ ~ ~ ~ t-

.......... V"

U

/RON = lB

~

~ ~ r~

/V

~

r-.

./

VTA =25

u

e
TA = 45°e
u
TA=65 e
/~ TA = BS'!:

-::::::

&.

I

~

:E
:E

10

11

12

13

14

15

10

11

12

13

14

15

Vee - VOUT(V)

J:

FIGURE 6

~

'§

en
,5

1000

'en
c

900

s::
C')

Q)

BOO

J::
'7

2:

700

«

\
l\

600

\\

v Po = 0.57W

"

/'

vPO = 0.4BW

,\\ \/' v Po = 0.39W

~

-;. 500

lV k
\1 \\
\ .\.'
\ \' .\

Po = 0.3W

::)

.E
400

300
01
200

--

~ t-- ~ ~ ~ ~
t-~ ......

100

/V
o
o

V,RON= 18

\\ l\'~

V

,/

/"

/"

V

.
~ S ~~~
r-t-_
~
~
~ ~ ~ ~ -..;;;
~J
::,v

- -t--

VI

/JJ

TA=25°e
TA=45°e

tTA=65°e

LJ . TA - 85°e

II

-rF--...........

Vee - VOUT (V)

FIGURE 7

5-42

»
2:

~

FIGURE 8

1000

Example 2
Since PDA + PDB -::; 0.9 + O.lS < 1.14W

In Figure 3, assume that driver A has to deliver 200 mA
to its load while driver B needs only 100 mAo Design
ALA and ALB for VCC - VL = 5V.

ALA = 7.1n
ALB = 33.3n

By inspection of Figure 4, units with high AON values
will not be able to deliver 200 mAo However, since
section B does not need the same amount of drive, we
can reduce the power consumed in this section to compensate for the higher power (> 0.57W) required in
section A_

satisfy all the requirements in this problem.
The design in Example 2 illustrated the simple and
straight-forward use of the curves' and the result
meets all the problem requirements. However. it
should be noted that there is not much design margin
left for tolerance iri resistances and other circuit
parameters. The reason is obvious-we are pushing at
the power limit of the MM74C90S package-and the
solutions are simple:

The design procedure follows:
Section A
1. Draw a load line intersecting AON = lSn line at
lOUT =-200 mAo
2. This load line intersects the lOUT axis at lOUT =
710 mA and is tangent to PDA "" 0.9W curve, thus
ALA ~ 5V!710 mA = 7.ln ~ill guarantee both
PDA -::; 0.9W·and IOUTA ~ 200 mA.

a) Increase VCC supply
b) Use the higher power package MM74C91S.
The design for higher VCC is identical to that in
Example 2 and will no.: be repeated here.
For the 14-lead higher power (2.27W) MM74C91S,
8jA = 55°CIW, this is exactly half that of the S-Iead
MM74C90S. Therefore, by scaling the lOUT axis by
a factor of 2, the same family of curves in Figure 9
can be applied directly. This is shown in Figure 10.
(Note that the slope of the AON = lSn line has been
adjusted to the new scale).

Section B
1. Draw a load line intersecting AON = lSn line at
lOUT = 100 mA.
2. Similar to (2) above, it is seen immediately that
RLB ~ 5V/150 mA = 33.3n will guarantee lOUTS ~
100 mA and PDB -::; O.laW.

2000
1900
1800
1700

r-~-+--r-~~~~+-~-4--~4--+--r-~-+~~+-~~--+-~-4--~~~--+-~-+--~

~v"

f-

W-

Po = 2.27W

~H-~PO~2W~r-+--r-4--+--r~--r--r-+--r-~-+--r-+--+-4--+-~~~+-~-4--4
1
I
Po = 1.73W

1600 1f=±=- Po =1.45W -r-~-+~I--t-=-+-4--+-~-4--+--+--+--t-4--+-r-4---+-l-+--+~
1500 I-tffi~[:l~t~IF Po =1.27W_I-+--+--+--I-+--+-4-f-,...+-+~-+--+--+~-+-~-+-I-+--I---l
\-U!! I Po =1.14W
1400
'~I =j Po';' 0.95w-+--1~+--r-4-+--t-~-+--r-r-r-~-+-r-+--+-I-+-+~I-+-.....j

1300 1--fH.H\'N~\ ~ Po = 0.77W+-4__+--+--+-+-4--+-r-+-+~f-+-~~'--+-+-I--+-+-4-+--l
\
~\ - Po ='0.59W
1200 I-tt+\t\\--Yl-HI
\f...-t-=r--r-+-+--+--+-+--+--+--4-I-+-+-+-+--+--+--+---I.--I-t--+-+-+---1
< 1100 r-~~~~~-r--1r-+--r-1-+--t-~--r--r-+--r-~-+--1I-+--r--1r-+--+-I-+-+-I-+--l
1000
\
po' = 0.15w -+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+--1
_5 900
1\ \ I\);~ _Po =0.36W_+--+-+--+--+--+--+-+--f_I--t-+-+-+--+--+-+--J.--I_I--~
l\JQJ' Po =0.27W
800
\ \) ('\ ~ ~ Po =0.18w-t--t--t--+-t-1-\--t---+-+--t--t--t--+-+--f-I--+-+-+-+--I
700
k'\ ~ \
\-"
.L.. TA=25"e +--+-I-+--+--+---j-+--+--+---jf-+--+--4-+---+--+~-+--l
'~kx I\.
TA =40"e
TA =70'e
600
~~~l)(I\.'\
~K~ =55"e Vr:: TA =80'e -t----f-,-.-+--+-+--1--1-+-+-+-+-+--+--+--+--4
500
I I ~ TA =87'e-+-~~+--+~"':-+-~-!--+-+-4-+-+~-+--l
"'~Xr~1:\."~~['..~ ~./ ITA =97'e RON =18 -.-=.:!::~-+-+--f--f---1f--!--+--+--.j.-+---l
400
lXl\\l'.~~~~K~~~E=::
I TA=107°e
300 f-~~Vk-"""'=--1"~~~od>~
[h A=117°C +.-t--I-+-4-+-+-4-+-~-+--l
I\~~:--~~I'.: ~r-.r-t- YATA =125°C
200 t ~~r--.;::>oo
~~
~~TA =130°C-+--+-+-+--+--+--+--+--lI--+--I--l
100
t-J-""~ 1- TA=135°C +-4-+--r~-+-~-!-+--+--+--l
_~~
I TA=140"e

t

1\'1\

l\1

" l'

I

\

I\. "'k.-L
t\.:

I

o

o

10
Vee - VOUT (VI
FIGURE 10

5-44

11

12

13

14

15

Since POA + POB ~ 1.14 + 0.4 = 1.8W, while the
package is capable of delivering 2.27W, both RLA
and RLB can be lower than the above values sest
standard resistance values:

By drawing the same load lines, it is found that:
RLA == 5V /710 mA = 7. H2
guarantees POA ~ 0.9W
and

RLA = 20n
RLB = 43n

RLB == 5V/150 mA = 33.3n
guarantees POB ~ 0.18W

For 5% tolerance in these values,
POA + POB ~ 1.08W
19n ~ RLA ~ 21n
40.85n ~ R LB ~ 45.15n

which is way below the maximum power 2.27W
available. Therefore, both R LA and R LB can be
lowered to account for tolerance in the resistors. Consider specifically the following example:

Thus:
IOUTA(MIN) ~

Example 3

10V
18n +21n

256.4 mA> 250 mA

10V

Assume driver A, B of the MM74C918 have to deliver
250 mA and 150 mA, respectively, to its load. Design
RLA and RLB at VCC - VL = 10V.

IOUTB(MIN) ~

Driver A

10V
) 2
POA(MAX) <
'
- ( 18n + 19n

1. In Figure 11, draw the load line intersecting RON =
18n at lOUT = 250 mA.
2. This load line intersects the lOUT axis at 450 mAo
Thus, by inspection RLA == 10V/450 mA == 22.2n
guarantees POA ~ 1.14W.

POB(MAX)

18n +45.15n

- 158.3 mA > 150 mA

10V
) 2
- ( 18n + 40.85n

<

'

. 18n = 1.31W
.

lSn
,

POA(MAX) + POB(MAX) ~ 1.31 + 0.52
Driver B

= 9.52W

< 2.27W

Therefore:

1. Draw the load line intersecting RON = 18n at
lOUT = 150 mAo
2. This load line intersects the lOUT axis at 210 mAo
Thus, by inspection RLB == 10V/210 mA = 47.6n
guarantees POB ~ O.4W.

RLA = 20n (1.5W, 5%)
RLB = 43n (lW, 5%)
will guarantee satisfactory performance of the circuit.

2000
1900

1100

r--I

1600 t1500 t1400
1300

1

8

Vee - VOUT (V)

FIGURE,11

5·45

10

11

12

13

14

15

APPLICATIONS
Like most other drivers, the MM74C908, MM74C918
can be used to drive relays, lamps, speakers, etc. These
are shown in Figure 12. (To suppress transient spikes at
turn·off, a diode as shown as Figure 12a is recommended
at the relay coil or any other inductive load.)

15V, power dissipation per package is .typically 750 nW
when the outputs are not drawing' current. Thus, the
drivers can be sitting out on Iine (a telephone line, for
example) drawing essentially zero current until actio
vated-an ideal feature for many applications.

However, th!! MM74C908, MM74C918 offers a unique
CMOS feature that is not available in drivers from other
logic families-extr"emely low standby power. At VCC =

The dual feature and the NAND function of the driver
design can also be used to advantage as shown in the
following applications:

------,

I
I
I
I
I

IN1
IN2\J"'"-""'L_'"

FIGURE 12a. Relay Driver

IN1
INZ

-.r---....._"

------,
I
I
I
I
I

FIGURE 12b. Lamp Driver

I
I
I
IL

------,
I
I
I
I
I
_ _ _ ~M~O~M~1~

__

FIGURE 12c. Speaker Driver

5-46

In Figure 13, the 2 drivers in the package are connected
as a Schmitt trigger oscillator, where Rl and R2 are used
to generate hysteresis. R3 and C are the inverting feed·
back timing elements and R4 is the pull·down load for
the first driver. Because of its current capability, the

Vcc
R2
20M

circuit can be used to drive an array of LEOs or lamps.
If resistor R4 is replaced by an LED (plus a current
limiting resistor), the circuit becomes a double flasher
with the 2 LEOs flashing out of phase. This is shown in
Figure 14.

=5V

- --,
I
I
I
I
RI

I
I

7.5M

L __ _

MM74C908, MM74C918

RJ
240k
R4
2k

FIGURE 13. High Drive Oscillator/Flasher

VCC

=5V

20M

- --,
I
I
I

I
I
7.5M

I
IL

___

~4~,~4~

I
I
I

__ _

240k

FIGURE 14. Out of Phase Double Flasher

5-47

the falling VO. and then start discharging. Then, both
VI and Vo discharge until VI hits the trip point, VT,
again. when the driver is turned "ON", charging up Va
and subsequently VI to complete a cycle.

Another oscillator circuit using only 1/2 of the package
and 4 passive components is shown in Figure 15. Assume
V I is sl ightly below the input trip point, the driver is .
"ON" and charging both Va and VI until VI reaches the
trip point, VT, when ... the driver starts to turn "OFF".
Va can be made much higher than VI at this instance by
adjusting the component values such that RfCf
(RONIIRL)CL. Since Va is higher than VI, VI is still
going up, although the driver is "OFF" and Va is
ramping down. The rising VI will eventually equal to

»

Vee

This oscillator is ideal for low cost applications like the
l·package siren shown in Figure 16, where 1 oscillator
is used as a VCO while the other is generating the voltage
ramp to vary the frequency at the VCO output.

=10V

---I

I

I
I

I
I

>

I
VI . .----------~~~------------~------~
RI

el

240k

(b)

TO,OlfJ F

(a)

FIGURE 15. Single Driver Oscillator

Vee

=10V

-------,

r--·----·----

I

I

I
I

I
I
I

I
IL

I
I

___

~7~8.~::~?~

__ _

680k

24k

FIGURE 16. Low Cost Siren

5-48

output drive and input NAND features are required.
One such example is given in Figure 17.

The NAND functions at the input can also be used to
,reduce package count in applications where both high

L __

-------1/2 MM74C908, MM74C918

-----,

I
I
I
I

Ro---"""""'iL--~

I
I
I
IL

I
_ _ _ 1~7~~7~8_, _ _

FIGURE 17. High Drive RS Latch

5-4,9

APRIL 1976
Gerald Buurma
National Semiconductor Corp.

Keyboard programmable divide-by-N counter with symmetrical output

...

(1)
~

c
j
o
(J

z

k
I

(1)

"0

'>
::s
::cCO
(1)

A CMOS key encoder combines with a couple of Dual D
flip-flops and an exclusive OR package to form a simple
but versatile programmable divider. The input frequency
can be divided by any number n between 1 and 16 by
simply pressing the appropriate key. The counter output
is symmetrical for both odd and even divisors.

This circuit is useful for simple frequency synthesis or as
an oscilloscope triggering unit where the displayed signal
is applied to the counter input and the external trigger of
the oscilloscope is connected to the counter output. The
trigger signal is then some submultiple of displayed
signal which often results in a more stable trace. Different
divisors can be easily keyed in as the input signal varies.

E
E

...

CO

C')

e
Q.

"ECO

MM74C74

MM74C74

.8

~

~

13
OE ........---OO

1-'; n .;;; 16

4x 4 ARRAY
OF SPST
SWITCHES

13

10

11

14

15

16

Simply press the key and the input frequency is divided by that number. The output frequency is symmetrical for odd
and even divisors. Use it for simple frequency synthesis or as a keyboard controlled oscilloscope triggering unit.

5-50

c
When the output is a "zero" or the encoder is in Tri-State,
due to the feedback signal, the clock signal from one flipflop to the next is the same phase. For every n/2 input
time period, the counter output and feedback change
state. Whenever the feedback signal changes state, all
flip-flops programmed with a "one" by the encoder
change their phases; this effectively adds a clock pulse to
that stage of the counter. The addition of clock pulses to
the 2 0 , 2 1 , 22 or 2 3 stages allows us to divide by any
number between 1 and 16. Since the feedback changes
state every n/2 input time period, the output frequency
is symmetrical. for any divisor.

The key encoder scans the key array wh ich is set up so
the key labeled "16" is in the matrix position which
causes "0" to be encoded, the key labeled" 15" causes
"1" to be encoded, and so on until we find that the key
position labeled "1" causes a binary "15," or all ones, at
the output of the encoder. The key arrangement converts
a key position so that any number n from 1 to 16 is
encoded as 16 - n at the encoder output. For example, if
the key labeled 5 is pressed the binary number 1011 = 11
appears at the encoder output. The MM74C922 key
encoder scans the keys, detects, debounces, and encodes
any entry. An internal register remembers the last key
pressed and presents it to the Tri-State® outputs.

OJ
I
CJ1

~

(t)

'<

C'"

o
Il)

..,

C.
"C

..,
..,

o

<.C

Il)

The unit operates over the standard CMOS supply range
of 3 to 15 volts and has a typical upper frequency limit
of one megacycle with a 10 volt supply.

The input to the exclusive OR is a "zero" when the
respective encoder output is a "zero" or when the feedback signal from the last counter stage forces the encoder
outputs into Tri-State. When in Tri-State the pull down
resistors feed a "zero" into the exclusive OR inputs.
When the output is an active "one," the clock signal from
one flip-flop to the next is inverted by the exclusive ORs.

3

3Il)

C'"

REFERENCE

~

1. M. V. Subba Rao, "Programmable Divide by n
Counter Provides Symmetrical Outputs for all
Divisors," Electronic Design, no. 2, January 19, 1976,
p.82.

c.

~:

c.

cp

C'"

~

2!
(")

o
c:

::::s

~

..,

(t)

5-51

.~.

John Jorgensen
Thomas P. Redfern
National Semiconductor

MM54C/MM74C VOLTAGE TRANSLATION/BUFFERING

INTRODUCTION
A new series of MM54C/MM74C buffers has been designed
to interface systems operating at different voltage levels.
In addition to performing voltage translation, the
MM54C901/MM74C901 through MM54C904/MM74C904
hex buffers can drive two standard TT L loads at
Vee = 5V. This is an increase of ten times over the two
LpTTL loads that the standard MM54C/MM74C gate can
drive. These new devices greatly increase the flexibility
of the MM54C/MM74C family when interfacing to other
logic systems.

(+5VI
Vee

FIGURE 1.

PMOS TO CMOS INTERFACE
Since most PMOS outputs normally can pull more nega·
, tive than ground, the conventional CMOS input diode
clamp from input to ground poses problems. The least
of these is increased power consumption. Even though
the output would be clamped at one diode drop (-G.6V),
all the current that flows comes from the PMOS negative
supply. For TTL compatible PMOS this is -12V. A PMOS
output designed to drive one TTL load will typically sink
5 mAo The total power· per TTL output is then
5 mA x 12V = 60 mW. The second problem is more'
serious. Currents of 5 mA or greater from a CMOS
input clamp diode can cause four·layer diode action on
the CMOS device. This, at best, will totally disrupt
·normal circuit operation and, at worst, will cause
catastrophic failure.
'

Vee
(+5VI

------J1+~SlNK
'-'"""l
-OmA
TYPICAL PMOS TTL
PUSH·PULL OUTPUT

~,

,

V~o"

HZVI

,

I

I

MM74C903/MM74C904

FIGURE 2.

To overcome this problem the MM74C903 and
MM74C904 have been designed with a clamp diode from
inputs to Vee only. This single diode provides adequate
static discharge protection and, at the same time, allows
voltages of up to -17V on any input. Since there is
essentially no current without the diode, both the high
power dissipation and latch up problems are eliminated.

CMOS

GND

To demonstrate the above characteristics, Figures 1, 2,
and 3 show typical TTL compatible PMOS circuits
NOTE: Vee + Voo S 17V
Vee S15V

driving standard CMOS with two clamp diodes, TTL
compatible PMOS driving MM74C903/MM74C904, and
the TTL compatible .PMOS to CMOS system interface,
respectively.

!

MM54C903iM:4C903
MM54C904iMM74C9Q4

iI'

FIGURE 3. PMOS to CMOS or TTL Interface

5·52

Figure 5. With this diode removed the current being
sourced goes from about 10 mA to the leakage current
of the reverse biased input diode.

CMOS TO CMOS OR TTL INTERFACE
When a CMOS system which is operating at Vee = 10V
must provide signals to a CMOS system whose Vee = 5V.
a problem similar to that found in PMOS-to-CMOS interface occurs. That is. current would flow through the
upper input diode of the device operating at the lower
Vee. This current could be in excess of 10 mA on a
typical 74C device. as shown in Figure 4. Again. this will
cause increased power as well as possible four layer diode
action.

Since the MM74C901 and MM74C902 are capable of
driving two standard TTL loads with only normal input
levels. the output can be used to directly drive TTL. With
the example shown. the inputs of the MM74C901 are in
excess of 5V. Therefore. they can drive more than two
TTL loads. In this case the device would drive four loads
with V1N = 10V.1f the MM74C902 were used. the output
drive would not increase with increased input voltage.
This is because the gate of the output n-channel device is
always being driven by an internal inverter whose output
equals that of Vee of the device.
The example used was for systems of Vee = 10V on one
system and Vee = 5V on the second. but the MM74C901
and MM74C902 are capable of using any combination of
supplies up to 15V and greater than 3V. as long as Vee 1
is greater than or equal to Vee2 and grounds are
common. Figure 6 diagrams this configuration.

STD CMOS
"Vee - 5V

I

00

s:
s:C1I
~
("')

........

s:
s:.....a

~
("')

<
o

!:4
»
G')
m

....
::0
l>
2
r-

FIGURE 4.

en

Vee
(tIOV)

j

s:tJl

~

o
2

J

L..... \.
IsouAeE
,...~

........

tJl

C
NOTE: Vee, ;ZVCC2

CMOS
"Vee -IOV

"T1
"T1

m

::0

MM74C901/MM74C902
Ii' Vee - 5V

FIGURE 6. CMOS to TTL or CMOS at a Lower VCC

2

G')

FIGURE 5.

Using the MM74C901 or MM74C902 will eliminate this
problem. This occurs simply because these parts are
designed with the upper diode removed. as shown in

The inputs on these devices are adequately protected
with the single diode. but. as with all MOS devices.
normal care in handling should be observed.

5-53

/

I

~

o

:D

Ordering Information

C

m
:D

Z

C)

'.

Z

"'T1

o

:D

MM74C Series'

~

Order
Number

Package

Temperature
Range,

MM74CXXN
MM74CXXJ
MM54CXXJ
MM54CXXD
MM54CXXW
MM80CXXN
MM80CXXJ
MM70CXXJ
MM70CXXD
MM70CXXW

Molded DIP (N)
Cavity DIP (J)
Cavity DIP (J)
Cavity DIP (D)
Cavity Flat Pack (W)
Mdlded DIP (N)
Cavity DIP (J)
Cavity DIP (J)
Cavity DIP (D)
Cavity Flat Pack (W)

-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-40°C to +85°C
_40°C to +85°C
-55°C to + 125°C
-55°C to +125°C
-55°C to +125°C

I

,

CD4000 Series
Order
Number

RCA Equivalent
Designation

Package

Temperature
Range

CD40XXCN
CD40XXCJ
CD40XXMJ
CD40XXMD
CD40XXMW
CD40XXBCN
CD40XXBCJ
CD40XXBMJ
CD40XXBMD
CD40XXBMW
*CD45XXCN
*CD45XXCJ
*CD45XXMJ
*CD45XXMD
*CD45XXMW

CD40XXAE
CD40XXAY
CD40XXAF
CD40XXAD
CD40XXAK
CD40XXBE
CD40XXBY
CD40XXBF
CD40XXBD
CD40XXBK
CD45XXBE
CD45XXBY
CD45XXBF
CD45XXBD
CD45XXBK

Molded DIP (N)
Cavity DIP (J)
Cavity DIP (J)
Cavity DIP (D)
Cavity Flat Pack (W)
Molded DIP (N)
Cavity DIP (J)
Cavity DIP (J)
Cavity DIP (D)
Cavity Flat Pack (W)
Molded DIP (N)
Cavity DIP (J)
Cavity DIP (J)
Cavity DIP (D)
Cavity Flat Pack (W)

-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-40°C to +85°C
_40°C to +85°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
_40°C to +85°C
-40°C to +85°C
-55°C to +125°C
_55°C to +125°C
_55°C to +125°C

*Equivalent to Motorola MC145XX Series.

6-3

~.

oz

,CMOS Packages
All dimensions expressed as

.il~.ches .
ml Imeters

I

It

0211
(1.5&91

~~~~~~~~~~~x

-1 r r- U,.31"----j
~

O.OW

R

I--f!izi --l
REf

G.tIS
t....1)

'~::::::"~(WjMAX
.L-.
O.OtS-o.oea

IO~I1-02OJI'0.100 ,0.OtO
I'.W .02W)

I
-l

I

I-

-11-

o.m-o.olS

0.125

IG.SM-O.311)

13.115)

TVP

MIN

2G-Lead Hermetic Dual-In-Line Package (D)

1.400

f------(:::)-------il
..

1
~~~T.TT.TT.T~~T.T~~~~~~Z)
0.530

28-Lead Hermetic Dual-In-Line Package (D)

4G-Lead Hermetic Dual-In-Line Package (D)

6-4

(")

s:o

(J)

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»"
C)

a.D2S

UI.:!~

m
(J)

1l.11l-L1211 I.....) GLASS
D.210-0.120

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0.211-1.321

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0.161

1.200

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D300

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REF

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0.10010.010

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18-Lead Hermetic Dual-In-Line Package (J)

I

0.600

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0.025

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11.524-2.5401

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. 14-Lead Hermetic Dual-In-Line Package (J)

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TV'

14-Lead Hermetic Flat-Package (W)

6-7

16-Lead Hermetic Flat Package (W)

Notes



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