1977_National_FET_Databook 1977 National FET Databook
User Manual: 1977_National_FET_Databook
Open the PDF directly: View PDF 
.
Page Count: 290
| Download | |
| Open PDF In Browser | View PDF |
FET
DATABOOK
Introduction
FET Selector Guides
Process Characteristics
Preferred Parts Data Sheets
Analog Switches
Applications
Physical Dimensions
© National Semiconductor Corporation
2900
Semiconductor
Dr,ive,
Santa
Manufactured under one or more of the following U.S. patents:
Clara,' California
95051,
3083262,
3381071,
3519897,
3579059,
3633052,
(408) 737-5000/TWX (910) 339-9240
National does not assume any responsibility for use of any circuitry
described; no circuit patent licenses are implied, and National
reserves the right, at any time without notice, to change said circuitry.
2
3189758,
3408542,
3557431,
3593069,
3638131,
32317!P,
3421025,
3560765,
3597640,
3648071,
3303356,
3426423,
3566218,
3607469,
3651565,
3317671,
3440498,
3571630,
3617859,
3693248.
3323071,
3518750,
3575609,
3631312,
Table of Contents
Section 1-lntroduction
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
How To Use This Catalog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F ET Parts List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
,FET Cross Reference Guide .................................. '"
Analog Switch Cross Reference Guide............................ "
Section 2-FET
Selec~or
1-3
1-3
1-4
1-5
1-13
1-21
Guides
Choose the Proper F ET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FET Application Guide. . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .
Important Parameters by Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FET Process Comparison Curves .................................
Selection Guide .... ,., ........................ : . . . . . . . . . . . . . . . . .
Switches, and Choppers, N-Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RF, VHF, UHF Amplifiers, N-Channel ...........................
Low Frequency-Low Noise Amplifiers, N-Channel . . . . . . . . . . . . . . . ..
Ultra Low Input Current Amplifiers, N-Channel. . . . . . . . . . . . . . . . . . ..
General Purpose Amplifiers, N-Channel. ..........................
General Purpose Duals, N-Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Low Frequency--Low Noise Duals, N-Channel ... , ., .. , .... , ., .....
Wide Band-Low Noise Duals, N-Channel . . . . . . . . . . . . . . . . . . . . . . . ..
High CMRR Duals, N-Channel. .................................
Ultra Low Leakage Duals, N-Channel . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Switches, P-Channel .............................. : ......... ,
Amplifiers, P-Channel . . . . . . . .. ... ..........................
Pro Electron FETs (European) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2-3
2-4
2-6
2-7
2-9
2-9
2-11
2-12
2-13
2-13
2-15
2-17
2-17
2-18
2-18
2-19
2-19
2-20
Section 3-Process Characteristics
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Process 50 N-Channel JFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Process 51 N-Channel JFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Process 52 N-Channel JFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Process 53 N-Channel J F ET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Process 55 N-Channel JFET .....................................
Process 58 N-Channel JFET .....................................
Process 83 N-Channel JFET .....................................
Process 84 N-Channel JFET ... , ............... , ., ....... , .......
Process 86* Monolithic Dual JFET ............................... ,
Process 88 P-Channel JFET ................. ;. . . . . . . . . . . . . . . . . . ..
Process 89 P-Channel J F ET .. '....... , ........................... ,
Process 90 N-Channel JFET . . . . . ... . . . . . . . . . . . . . .. . . . . . . . . . . . . . ..
Process 92 N-C~annel Junction Match. . .. .,. .....................
Process 93 N-Channel JFET .....................................
Process 94 N-Channel JFET ........ '. . . . . . . . . . . . . . . . . . . . . . . . . ... ..
Process 95 N-Channel JFET .......... ' ........................... '
Process 96, N-Channel JFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
,Process 98* N-Channel JFET ....' .. " .... " .......................
*Process in development
3
3-2
3-3
3-6
3-8
3-10
3-12
3-14
3-16
3-18
3-20.
3-21
3-23
3-25
3-27
3-29
3-31
3-33
3-35
3-37
Table of Contents
(Continued)
Section 4-Preferred Parts Data Sheets
2N3684-87/PN3684-87 N-Channel JFETs. . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3954-55/2N3954A-55A N-Channel Monolithic-oual JFETs. . . . . . . . . ..
2N3956-58 N-Channel Monolithic Dual JFETs ... _. . . . . . . . . . . . . . . . . . .
2N4091-93/PN4091-93 N-Channel JFETs.'. >. . . . . . . . . . . . . . . . . . . . . . ..
2N4117-19/2N4117 A-19A N~Channel JFETs ........... _.... _. . . . . ..
2N4338-41 N-Channel JFETs ................. _..... , ....... , . . ..
2N4391-3/PN4391-3 N-Channel JFETs ... _. , . . . . . . . . . . . . . . . . . . . . . . .
2N4416/2N4416A N-Channel JFETs ..... , ........................
2N4856-61/PN4856-61 N-Channel JFETs...........................
2N5114-16 P-Channel JFETs ....................................
2N5196-99 N-Channel Monolithic Dual JFETs .......................
2N5245-47 N-Channel JFETs .. _.... , .............................
2N 5358-60 N-Channel J PETs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5361-64 N-Channel JFETs ....................... , ............
2N5397, 2N5398 N-Channel JFETs ...............................
2N5432-34 N-Channel JFETs ...... '..............................
2N5457-59 N-Channel JFETs ....................................
2N5460-62 P-Channel JFETs ........... '. . . . . . . . . . . . . . . . . . .. . . . ..
2N5484-86 N-Channel JFETs ....................................
2N5515-24 N-Channel Monolithic Dual JFETs. . . . . . . . . . . . . . . . . . . . . ..
2N5545-47 N-Channel Monolithic Dual JFETs .. .'. . . . . . . . . . . . . . . . . . ..
2N5564-66/NPD5564-66 N-Channel Monolithic Dual JFETs ...... ' ......
2N5638-40 N-ChanneIJFETs ... , ..... , ..........................
2N5902-09 N-Channel Monolithic Dual'JFETs ............ ". . . . . . . . ..
2N5911, 2N5912 N-Channel Monolithic Dual JFETs .................
2N5949-53 N-Channel JFETs . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . ..
2N6483-85 N-Channel Monolithic Dual JFETs. . . . . . . . . . . . . . . . . . . . . ..
J108-10 N-Channel JFETs ... : ............................. '......
J111-13N-ChanneIJFETs........................................
J174-77 P-Channel JFETs ................................ : ......
J201-03 N-Channel JFETs ...............
J210-12 N-Channel JFETs.......................... ~ ............
J270, J271 P-Channel JFETs............ , ,'. . . . . . . . . . . . . . . . . . . . . ..
J300 N-Channel JFET ....... , ......... ': ........................
J304, J305 N-Channel JFETs .............................. _. . . ..
J308-1O N-Channel JFETs .......... _............................
NDF9401-10 N-Channel Monolithic Cascode DuaIJFETs...............
NF5101-03/PF5101-03 N-Channel JFETs......... '.. , .............. ,
NPD8301-03 N-Channel Monolithic Dual JFETs ......................
U308-10 N-Channel JFETs . " ........ .' .. '.................. " . . . ..
i: ....................
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4·18
4-19
4-20
4-21
4-22
4-23
4-24
4-25
4-26
4-27
4-28
4-29
4-30
4-31
4-32
4-33
4-34
4-35
4-36
4-37
4-38
4-39
4-40
4-41
4-42,
Section 5-Analog' Switches
Analog Switches Selection Guide: ..... '. . .. . . . . . . . . . . . . . . . . . . . . . . .
Definition of Terms ................. ,. . . .. . .. . . . . . . . . . . . . . . . . ..
AH0014/AH0014C DPDT MOS Analog Switch ...... , . . . . . . . . . .. . . . .
AH0015/AH0015C Quad SPST MOS Analog Switch ................ "
AH0019/AH0019C Dual DPST-TTL/DTL Compatible MOS Analog Switch.
, AH0120 Series Analog Switches .. , .... '......... ' ..... : . : .. ; .. :. . ..
AH0130 Series Analog Switches ............ ; .... ; . . . . . . . . . . . . . . ..
AH0140 Series Analog Switches ............... '. . . . . . . . .. . . . . . . . ..
4
5-3
5-4
5-5
5-5
5-5
5-8
5-8
5-8
Table of Contents
(Continued)
Section 5-Analog Switches
(Continued)
AH0150 Series Analog Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0160 Series Analog Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Af:"J2114/AH2114C DPST Analog Switch ...........................
AH5009 Series Monolithic Analog Current Switches. . . . . . . . . . . . . . . . . ..
AM181 Series Monolithic' N-Channel High Speed Switch with Drivers. . . ..
AM2009/AM2009C 6-Channel MOS Multiplex Switch ..... , ...........
AM3705/AM3705C 8-Channel MOS Analog MUltiplexer ...............
AM9709 Series Monolithic Analog Current Switches. .. ..............
AM97C09 Series Monolithic Analog Current Switches. . . . . . . . . . . . . . . ..
CD4007M/CD4007C Dual Complementary Pair Plus Inverter. . . . . . . . . . ..
CD4016M/CD4016C Quad Bilateral Switch. . . . . . . . . . . . . . . . . . . . . . . ..
CD4051M/CD4051C Single 8-Channel Analog MultiplexerlDemultiplexer ..
CD4052M/CD4052C Dual 4-Channel Analog Multiplexer/Demultiplexer. ..
CD4053M/CD4053C Triple 2-Channel Analog Multiplexer/Demultiplexer..
CD4066M/CD4066C Quad Bilateral Switch. . . . . . . . . . . . . . . . . . . . . . . ..
LF11201/LF12201/LF13201 4 Normally Closed Switches .............
LFl1202/LF12202/LF132024 Normally Open Switches ..............
LFl1331/LF12331!LF13331 4 Normally Open Switches with Disable ....
LF11332/LF 12332/LF 133324 Normally Closed Switches with Disable. ..
LFl1333/LF12333/LF13333 2 Normally Closed, 2 Normally Open
Switches with Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LF11508/LF12508/LF13508 8-Channel Analog Multiplexer ............
LF 11509/LF12509/LF13509 4-Channel Differential Analog Multiplexer..
MM450/MM550 MOS Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM451/MM551 MOS Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM452/MM552 MOS Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM454/MM544 4-Channel Commutator. . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM455/MM555 MOS Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM4504/MM5504 6-Channel MOS Multiplex Switch. . . . . . . . . . . . . . . . ..
5-8
5-8
5-15
5-31
5-17
5-26
5-28
5-31
5-31
5-41
5-44
5-48
5-48
5-48
5-54
5-60
5-60
5-60
5-60
5-60
5-70
5-70
5-85
5-85
5-85
5-89
5-85
5-26
Section 6-Applications
FET Application Guide ........................ ; .. .. . . . . . . . . . . . .
Monolithic Dual FETs vs 2-Chip Dual FETs ..... : . . . . . . . . . . . . . . . . . . .
Why Use Cascode Dual F ETs? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Simple VHF Analog Switches ....................................
Noise of Sources .......................................' . . . . . ..
The Noise Figure Fallacy ........................................
Low Noise FET Amplifiers ......................................
The Low Noise JFET -The Noise Problem Solver. . . . . . . . . . . . . . . . . . . ..
FET Circuit Applications ..................................... "
A Novel FET Micropower Voltage Regulator ........................
A Linear Multiple Gain Controlled Amplifier. . . . . . . . . . . . . . . . . . . . . . ..
Binary/BCD'Gain Programmed Amplifiers ..........................
FET Curve Tracer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
JFET Glossary of Symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
6-3
6-4
6-8
6-10
6-12
6-15
6-17
6-20
6-26
6-37
6-39
6-47
6-50
6-52
Section 7 -Physical Dimensions
Package I nformatioll. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
7-3
.-o-.
~
Introduction
Co
C
(')
This is National Semiconductor's first Field Effect
Transistor/Analog Switches Data Book. It is the
direct result of the designer's desire to have a
complete, concise, up to date handbook for discrete FETs and FET analog switches.
a product must offer the latest technology, the
best performance, excellent deliverability and
competitive prices. These preferred parts should be
considered first in all applications.
C)"
~
Q)
~
If you are a first·time user of FETs and FET analog
switches, you will find this catalog invaluable in
making your selection. Old hands will appreciate
the concise selector guides and accurate process
curves. Whatever your experience, you will find
National's Sales Representatives, Field Application Engineers and Factory Personnel willing and
able to help with any application problems or
questions.
There are over 1000 Junction FETs and analog
switches available from at least 8 major suppliers
and many smaller ones. In order to ease the de·
signer's task, National has selected approximately
350 types as representative of a product that
reflects the best available current technology.
Certain of these products have been designated
preferred parts. To qualify as a preferred part,
Co
"C
a
Co
..a-_.
c
(')
"C
CD
Product Profile
Field Effect Transistors. National offers 17 J F ET
processes which cover the full range of possible
products. Devices with leakage currents as low as
0.1 pA are available along with devices suitable
for operation at VHF frequencies. Low noise FETs
for audio and subaudio applications are available
along with the industry's broadest line of monolithic dual FETs. National invented the monolithic
dual JFET and consistently wins praise for consis·
tent performance to the tightest offset and drift
specifications. National's cascade dual JFETs
(Process 84, 94) offer superior CM R R and low
leakage currents even at extended voltages. '
industry usage increased, National developed the
BI-FETTM technology and other monolithic FET
structures which have become the industry standard ,for analog ,switches. The preferred parts
shown in this data book utilize these processes.
Most are function, pin and specification compatible
with earlier products available in the market place.
High Reliability Product. National Semiconductor
is committed to supplying the military/aerospace
markets with the highest quality product available.
Presently, National is qualified to supply 85% of
all FETs on the MIL-S-19500 QPL-more than any
other supplier. Our capability covers a wide range
of standard and special testing and processing to
levels as specified in MIL-S-19500, MIL-STD-750,
MI L-STD-883, MI L-M·38510. Contact your local
representative or regional office for information
concerning your specific requirements.
Analog Switches. National Semiconductor has for
many years supplied a full line of analog switches
which served the designer's needs for high quality,
competitively priced products. Recognizing the
need for improved reliability and lower cost as
1-3
C)
-
.2
ca
ca
How to Use This Catalog
U
tn
..c
t-
The Field Effect Transistor/Analog Switch Data
Book, is divided into 7 sections. The following
information is contained in each.
The following suggested procedure will help you
find the device you need .
Part Number Known: Go to section 1. If alternate type found in cross reference guide, then
compare alternate specification in section 2 against
desired part type for compatibility.
G)
tn
::l
.s
~
o
:::J:
Section 1 Alpha-numeric parts lists and cross
reference gu ides
Section 2 FET selector guides including
complete guide by 'application to ali
part types offered by National. This
is the complete guide to National
FET specifications and is indexed in
Section 1. Preferred parts are shown
with gray overprinting.
Section 3 FET process characteristics giving
complete information on all processes, including all parts manufactured
from a particular process by package
type.
Section 4 FET preferred parts data sheets.
Section 5 Analog switch selector .guides and
data sheets.
Section 6 Applications notes on FETs and
analog switches.
Section i Physical Dimensions
a
Specification Known: Refer to "FET Process
Comparison Chart" in section 2 to find the most
compatible' process. Then turn to the specific
process in section :3 for a listing of specific device
. type numbers available in that process. Take
special note of preferred part types. Full data
sheets are available in section 4.
Application Known: For FETs, turn to "Choose
the Proper FET" and "FET Application Guide" in
section 2. Refer also to "Important Parameters by
Application" as needed. Once a process is selected,
refer to section 3 and to the proper preferred part
type. For analog switches, refer to section 5 "Analog Switch Selector Guide".
.
. None of the Above: Contact local representative
or regional office for assistance.
1-4
."
m
FET Parts List
~
"'0
DEVICE
PROCESS/PACKAGE
SELECTION
GUIDE
PREFERRED PARTS
DATA SHEET
PROCESS PAGE
• 2N2608
2N2609
2N3069
2N3070
2N3329
2N3330
89/11
88/11
52/02
52/02
89/23
89/23
2-19
2-19
2-13
2-13
2-19
2-19
3-23
3-21
3-8
3-8
3-23
3-23
2N3331
2N3332
2N3368
2N3369
2N3370
2N3382
89/23
89/23
52/02
52/02
52/02
88/23
2-19
2-19
2-13
2-13
2-13
2-19
3-23
3-23
3-1;3
3-8
3-8
3-21
2N3384
2N3386
2N3436
2N3437
2N3438
2N3458
88/23
88/23
55/02
55/02
55/02
52/02
2-19
2-19
2-13
2-13
2-13
2-13
3-21
3-21
3-12
3-12
3-12
3-8
2N3459
2N3460
2N3684
2N3685
2N3686
2N3687
52/02
52/02
52/25
52/25
52/25
52/25
2-13
2-13
2-13
2-13
2-13
2-13
3-8
3-8
3-8
3-8
3-8
3-8
2N3819
2N3821
2N3822
• 2N3823
2N3824
2N3921
50/74
55/25
55/25
50/25
55/25
83/12
2-11
2-13
2-13
2-11
2-9
2-15
2N3922
2N3954
2N3954A
2N3955
2N3955A
2N3956 .
83/12
83/12
83/12
83/12
83/12
83/12
2-15
2-15
2-15
2-15
2-15
2-15
2N3957
2N3958
2N3966
2N3967
2N3967A
2N3968
83/12
83/12
50/25
52/25
52/25
52/25
2-15
2-15
2-9
2-13
2-13
2-13
2N3968A
2N3969
2f'J3969A
2N3970
2N3971
2N3972
52/25
52/25
52/25
51/02
51/02
51/02
2-13
2-.13
2-13
2-9
2-9
2-9
• Denotes JAN Qual ified type
1-5
4-3
4-3
4-3
4-3
3-3
3-12
3-12
3-3
3-12
3-16
4-4
4-4
4-4
4-4
4-5
4-5
4-5
3-16
3-16
3-16
3-16
3-16
3-16
3-16
3-16
3-,3
3-8
3-8
3-8
3-8
3-8
3-8
3-6
·3-6
3-6
-
m
~
en
C
en
FET Parts List
(Continued)
tn
~
co
0.
IW
LL.
PROCESS/PACKAGE
SELECTION
GUIDE
2N3993
2N3993A
2N3994
2N3994A
2N4084
2N4085
88/23
88/23
88/23
88/23
83/12
83/12
2·19
2·19
2·19
2·19
2·15
2·15
• 2N4091
• 2N4092
• 2N4093
2N4117
2N4117A
2N4118
51/02
51/02
51/02
53/25
53/25
53/25
2·9
2·9
2·13
2·13
2·13
2N4118A
2N4119
2N4119A
2N4220
2N4220A
2N4221
53/25
53/25
53/25
55/25
55/25
55/25
2·13
2·13
2·13
2·14
2·14·
2·14
2N4221A
2N4222
2N4222A
2N4223
2N4224
2N4338
55/25
55/25
55/25
50/25
50/25
52/02
2·14
2·14
2·14
2·11
2·11
2·14
2N4339
2N4340
2N4341
2N4381
2N4382
2N4391
52/02
52/02
52/02
89/11
88/11
51/02
2·14
2·14
2·14
2·19
2·19
2·9
2N4392
2N4393
2N4416
• 2N4416A
• 2N4856
2N4856A
51/02
51/02
50/25
50/25
51/02
51/02
2·9
2·9
2·11
2·11
2·9
2·9
• 2N4857
2N4857A
• 2N4858
2N4858A
• 2N4859
2N4859A
51/02
51/02
51/02
51/02
51/02
51/02
2·9
2·9
2·9
2·9
2·9
2·9
• 2N4860
2N4860A
• 2N4861
2N4861A
2N5018
2N5019
51/02
51/02
51/02
51/02
88/11
88/11
2·9
2·9
2·9
2·9
2·19
2·19
DEVICE
PREFERRED PARTS
DATA SHEET
PROCESS PAGE
3·21
3·21
3·21
3·21
3·16
3·16
4·6
4·6
4·6
2~9
4·7
4·7
4·7
4·8
4·8
4·8
4·8
4·9
4·9
4·9
,4·10
4·10
4·11
-
4·11
4·11
3·6
3·6
3·6
3·10
3·10
3·10
3·10
3·10
3·10
3·12
3·12
3·12
3·12
3·12
3'12
3·3 .
3·3
3·8
3·8
3·8
3·8
3·23
3·21
3·6
3·6
3·6
.3·3
3·3
3·6
3·6
3·6
3·6
3·6
3·6
3·6
3·6
3·6
3·6
3·6 .
3·6
3·21
3·21
• Denotes JAN qualified type
'·6
,
FET Parts List
."
m
(Continued)
-I
SELECTION
GUIDE
2N5020
2N5021
2N5045
2N5046
2N5047
2N5078
89/11
89/11
83/12
83/12
83/12
50/25
2-20
2-20
2-16
2-16
2-16
2-11
3-23
3-23
3-16
3-16
3-16
3-3
2N5103
2N5104
2N5105
• 2N5114
• 2N5115
• 2N5116
2N5196
2N5197
2N5198
2N5199
2N5245
2N5246
50/25
50/25
50/25
88/11
88/11
88/11
2-14
2-14
2-14
2-19
2-19
2-19
4-12
4-12
4-12
3-3
3-3
3-3
3-21
3-21
3-21
83/12
83/12
83/12
83/12
90/77
90/77
2-16
2-16
2-16
2-16
2-11
2-11
4-13
4-13
4-13
4-13
4-14
4-14
3-16
3-16
3-16
3-16
3-25
3-25
2N5247
2N5248
2N5358
2N5359
2N5360
2N5361
90/77
50/74
55/25
55/25
55/25
55/25
2-11
2-11
2-14
2-14
2-14
2-14
4-14
3-25
3-3
3-12
3-12
3-12
3-12
2N5362
2N5363
2N5364
2N5397
2N5398
2N5432
55/25
55/25 .
55/25
90/25
90/25
58/07
2N5433
2N5434
2N5452
2N5453
2N5454
2N5457
58/07
58/07
83/12
83/12
83/12
55/72
2-9
2-9
2-16
2-16
2-16
2-14
4-18
4-18
4-19
3-14
3-14
3-16
3-16
3-16
3-12
2N5458
2N5459
2N5460
2N5461
2N5462
2N5484
55/72
55/72
89/71
89/71
89/71
50/72
2-14
2-14
2-20
2-20
2-20
2-11
4-19
4-19
4-20
4-20
4-20
4-21
3-12
3-12
3-23
3-23
3-23
3-3
2N5485
2N5486
2N5515
2N5516
2N5517
2N5518
50/72
50/72
95/12
95/12
95/12
95/12
, 2-11
4-21
4-21
3-3
3-3
3-33
3-33
3-33
3-33
.2-14
2-14
2-14
2-11
2-1'1
2-9
2-11
2-17
2-17
2-17
2-17
• Denotes JAN qualified type
1·7
PREFERRED PARTS
DATA SHEET
"'C
PROCESS/PACKAGE
DEVICE
4-15
4-15
4-15
4-16
4-16
4-16
4-16
4-17
4-18
PROCESS PAGE
3-12
3-12
3-12
3-25
3-25
3-14
-c:
...
I»
en
!!1.
FET Parts List
(Continued)
SELECTION
GUIDE
DEVICE
PROCESS/PACKAGE
. 2N5519
2N5520
2N5521
2N5522
2N5523
2N5524
95/12
95/12
95/12
95/12
95/12
95/12
2N5545
2N5546
2N5547
2N5555
2N5556
2N5557
*83/12
*83/12
*83/12
50/72
50/25
50/25
2-16
2-16
2-16
2-9
2-14
2-14
2N5558
2N5561
2N5562
2N5563
2N5564
2N5565
50/25
t98/12
t98/12
t98/12
96/12
96/12
2-14
2-16
2-16
.2-16
2-17
2-17
2N5566
2N5638
2N5639
2N5640
2N5653
2N5654
96/12
51/72
51/72
51/72
51/72
51/72
2-17
2-10
2-10
2-10
2-10
2-10,
50/72
50/72
50/72
84/24
84/24
.84/24
2-11 '
2-11
2-11
2-18
2-18
2-18
2N5668
2N5659
2N5670 '
2N5902
2N5903
2N5904
2-17
2-17
2-17
2-17
2-17
2-17 '
•
2N5905
2N5906
2N5907
2N5908
2N5909
2N5911
84/24
84/24
84/24
84/24
84/24
93/24
2N5912
2N5949
2N5950
2N5951
2N5952
93/24
50/77
50/77
50/77
50/77
50/77
2-17
2-11
2-11
2-11:
2-11
2-11
95/12
95/12
95/12
50/77
50/77
50/77
2-17
2-17
2-17
2-20
2-20
2-20
2N595~
,
2N6483
2N6484
2N6485
BC264A
BC264B
BC264C
PREFERRED PARTS
DATA SHEET
4-24
4-24
4-24
4-25
4-25
4-25
t Process in development
1-8
:
3-16
3-16
3-16
3-3
3-3
3-3
3-3
3-37
3-37
3-37
3-35 .
3-35
3-35
3-6
3-6
3-6,'
3-6
3-6'
3-3
3-3
3-3
3-18
3-18
3-18
2-18
2-18
2-18
2-18
2-18
2-17
* JAN qualification pending, Consult factory,
3-33
3-33
3-33·,
3-33
3-33
3-33
4-22
4-22
4-22
4-22
4-22
4-23
4-23
4-23
PROCESS PAGE
4-26
4-26
4-26
4-26
4-27
I
3-18
3-18
3-18
3-18
3-18
3:29
4-27
3-29
3-3
3-3
3-3
3-3
3-3
4-29
4-29
4-29
3-33
3-33
3-33
3-3
3-3
3-3
FET Parts List
."
m
(Continued)
-t
"'0
BC264D
BF244A
BF244B
BF244C
BF245A
BF245B
50/77
50/74
50/74
50/74
50/77
50/77
2-20
2-20
2-20
2-20
2-20
2-20
3-3
3-3
3-3
3-3
3-3
3-3
BF245C
BF246A
BF246B
BF246C
BF247A
BF247B
50/77
51/74
51/74
51/74
51/77
51/77
2-20
2-20
2-20
2-20
2-20
2-20
3-3
3-6
3-6
3-6
3-6
3-6
BF247C
BF256A
BF256B
BF256C
J108
J109.
51/77
50/77
50/77
50/77
58/72
58/72
2-20
2-20
2-20
2-20
2-10
2-10
3-6
3-3
3-3
3·3
3-14
3-14
J110
J 111
J112
J113
J114
J174
58/72
51/72
51/72
51/72
90/72
88/74
2-10
2-10
2-10
'2-10
2-10
2-19
4-30
4-31
4-31
4-31
4-32
3-14
3-6
3-6
3-6
3-25
3-21
J175
J176
J177
J201
J202
J203
88/74
88/74
88/74
52/72
52/72
52/72
2-19
2-19
2-19
2-14
2-14
2-14
4-32
4-32
4-32
4-33
4-33
4-33
3-21
3-21
·3-21
3-8
. 3-8
3-8
J210
J211
J212
J270
J271
J300
90/72
90/72
90/72
88/74
88/74
90/72
2-14
2-14
2-14
2-20
2-20
2-11
4-34
4-34
4-34
4-35
4-35
4-36
3-25
3-25
3-25
3-21
3-21
3-25
J304
J305
J308
J309
J310
J401
50/72
50/72
92/72.
92/72
92/72
t98/60
2-11
2-11
2-11
2-11
2-11
2-16
4-37
4-37
3-3
3-3
3-27
3-27
3-27
3-37
J402
J403
J404
J405
J406
J410
t98/60
t98/60
t98/60
t98/60
t98/60
83/60
2-16
2-16
2-16
2-16
2-16
2-16
tProcess in development
1-9
PREFERRED PARTS
DATA SHEET
4-30
4-30
4-38
4-38
-
...
Q)
PROCESS/PACKAGE
SELECTION
GUIDE
DEVICE
PROCESS PAGE
3-37
3-37
3-37
3-37
3-37
3-16
en
C
(J)
t /)
::i
FET Parts List
(Continued)
,
t/)
~
co
PROCESS/PACKAGE
SELECTION
GUIDE
J411
J412
MPF102
MPF103
MPF104
MPF105
83/60
83/60
50/72
55/72
55/72
55/72
2-16
2-16
2-f2
. 2-14
2-14
2-14
3-16
3-16
3-3
3-12
3-12
3-12
MPF106
MPF107
MPF 108
MPF109
MPF111
MPF112
50/72
50/72
'55/72
55/72
50/72
55/72
2-12
2-12
' 2-12
2-14
2-15
2-15
3-3
3-3
3-12
3-12
3-3
3-12
NDF9401
, NDF9402
NDF9403
NDF9404
NDF9405
NDF9406
94/24
94/24
94/24
94/24
94/24
94/12
2-18
2-18
2-18
2-18
2-18
2-18
4-39
3-31
3-31
3-31
3-31
3-31
3-31
NDF9407
NDF9408
NDF9409
NDF9410
NF5101
NF5102
94/12
94/12
94/12
94/12
51/25
51/25
2-18
2-18
.2-18
2-18
2-12
2-12
4-39
4-39
4-39
4-39
4-40
4-40
3-31
3-31
3-31
3-31
3-6
3-6
NF5103
NPD5564
NPD5565
NPD5566
NPD8301
NPD8302
51/25
96/67
96/67
96/67
83/67
83/67
2-12
2-17
2-17 .
2-17
2-16
2-16
4-40
4-24
4-24
4-24
4-41
4-41
3-6
3-35
3-35
3-35
3-16
3-16
NPD8303
NPD9B01
NPD9802
NPD9803
Pl086E
P1087E
83/67
t98/67
t98/67
t98/67
88/71
88/71
2-16
2-16·
2-16
2-16
2-19
2-19
4-41
3-16
PF5101
PF5102
PF5103
PN3684
,PN3685
PN3686
51/72
51/72
51/72
52/72
52/72
52/72
2-12
2-12
2-12
2-15
2-15
2-15
4-40
4-40
4-40
4-3
4:3
4-3
3-6
3-6
3-6
3-8.
3-8
3-8
PN3687
. PN4091
PN4092
PN4093
PN4220
PN4221
52/72
51/72
51/72
51/72
55/72
55/72
2-15
2-10
2-10
2-10
2-15
2-15
4-3
4-6
4-6.
4-6
3-8
3-6
3-6
3-6
3-12
3-12
DEVICE
Q.
tW
LL
,
I
tProcess in development
1-10
PREFERRED PARTS
DATA SHEET
'
,
PROCESS PAGE
3-21
3-21
FET Parts List
DEVICE
."
m
(Continued)
PROCESS/PACKAGE
-I
SELECTION
GUIDE
PREFERRED PARTS
DATA SHEET
PROCESS PAGE
PN4222
PN4223
, PN4224
PN4302
PN4303
PN4304
55/72
50/72
50/72
52/72
52/72
52/72
2-15
2-12
2-12
2-15
2-15
2-15
3-12
3-3
3-3
3-8
3-8
3-8
PN4342
PN4343
PN4360
PN4391
PN4392
PN4393
89/71
88/71
89/71
51/72
51/72
51/72
2-20
2-20
2-20
2-10
2-10
2-10
3-23
3-21
3-23
3-6
3-6
3-6
PN4416
PN4856
PN4857
PN4858
PN4859
PN4860
50/72
51/72
51/72
51/72
51/72
51/72
2-12
2-10
2-10
2-10
2-10
2-10
PN4861
PN5033
PN5163
TIS58
TIS59
TIS73
51/72
89/71
50/72
50/74
50/74
51/77
2-10
2-20
2-15
2-15
2-15
2-10
3-6
3-23
3-3
3-3
3-3
3-6
TIS74
TIS75
U1897E
U1898E
U1899E
U231
51/77
51/77
51/72
51/72
51/72
83/12
2'10
2-10
2-10
2-10
2-10
2-16
3-6
3-6
3-6
3-6
3-6
3-16
U232
U233
U234
U235
U257
U300
83/12
83/12
83/12
83/12
93/24
88/11
2-16
2-16
2-16
2-16
2-17
2-20
3-16
3-16
3-16
3-16
3-29
3-21
U30l
U304
U305
U306
U308
U309
88/11
88/11
88/11
88/11
92/07
92/07
2-20
2-19
2-19
2-19
2-12
2-12
3-21
3-21
3-21
3-21
3-27
3-27
U3l0
U312
U320
U321
U322
U401
92/07
90/07
58/09
58/09
58/09
t98/12
2-12
2-12
2-12
2-12
2-12
2-16
tProcess in development
1-11
4-9
4-9
4-9
4-11
4-11
4-11
4-42
4-42
""C
3-3
3-6
3-6
3-6
3-6
3-6
3-27
3-25
3-14
3-14
3-14
3-37
...
Q)
en
r_.
en
....
t/)
:.:::l
.......
FET
Part~
List
(Continued)
t/)
ca
DEVICE
. PROCESS/PACKAGE
SELECTION
GUIDE
U402
U403
U404
U405
U406
U421
t98/12
t98/12
t98/12
t98/12
t98/12
t86/24
2-16
2-16
2-16
2-16
2-16
2-18
8-37
3-37
3-37
3-37
3-37
3-20
t86/24
t86/24
t86/24
t86/24
t86/24
92/24
92/24
2-18
2-18
2-18
2-182-18
2-17
2-17
3-20
3-20
3-20
3-20
3-20
3-27
3-27
D.
IW
LL
,
U422
U423
U424
U425
U426
U430
U431
PREFERRED PARTS
PROCESS PAGE
DATA SHEET
tProcess in development
-
1·12
Co.
'TI
JFET Cross Reference Guide
m
This guide contains cross reference information to
more than 850 Junction FETs, including many
obsolete or otherwise unavailable types. Every
effort has been made to recommend a replacement
FET which will plug into an existing socket and
work as well as the part it replaces. Let the replacement code be your guide. If you do not find a
particular part in this guide and you know its
specification, you should refer to "How To Use
This Catalog" in this section.
INDUSTRY TYPE
NUMBER
2N3329
2N3330
2N3331
2N3332
2N3365
2N3366
2N3367
2N3368
2N3369
2N3370
2N3376
2N3378
2N3380
2N3382
2N3384
2N3386
2N3436
2N3437
2N3438
2N3452
2N3453
2N3454
2N3455
2N3456
2N3457
2N3458
2N3459
2N3460
2N3574
2N3575
2N3578
2N3684
2N3684A
2N3685
2N3685A
2N3686
2N3686A
2N3687
'. 2N3687A
2N3819
2N3820
2N3821
2N3822
2N3823
2N3824
2N3909
2N3909A
2N3921
2N3922
2N3954
2N3954A
2N3955
2N3955A
2N3956
2N3957
2N3958
2N3966
REPLACEMENT CODE
*
Identical specification and pin configuration
e
Equal or better specification, identical pin
configuration
II
Similar specification acceptable for all but the
most critical applications, similar pin configuration
CF Consult Factory or Local Sales Representative,
available on special order
N
No equivalent process
INDUSTRY TYPE
NUMBER
REPLACEMENT
CODE
,2N2386
2N2386A
2N2497
2N2498
2N2499
2N2500
2N2606
2N2607
2N2608
2N2609
2N2841
2N2842
2N2843
2N2844
2N3066
2N3067
2N3068
2N3069
2N3070
2N3071
2N3084
2N3085
2N3086
2N3087
2N3088
2N3088A
2N3089
2N3089A
2N3277
2N3278
2N3328
•
•
•
•
•
•
NATIONAL
PART
NUMBER
2N2608
'. 2N4381
2N5021
.2N5021
2N4381
2N4381
N
N
2N2608
2N2609
N
N
•
•
•
•
•
II
•
•
II
•
•
•
•N
2N5020
2N5020
2N4340
2N4338
2N4338
2N3069
2N3070
2N3071
2N4340
2N4340
2N4340
2N4340
2N4339
2N4339
2N4339
2N4339
N
0
2N3330
1·13
REPLACEMENT
CODE
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
NATIONAL
PART
NUMBER
. 2N3329
2N3330
2N3331
2N3332
2N4340
2N4338
2N4338
2N3368
2N3369
2N3370
2N3329
2N3330
2N3331
2N3382
2N3384
2N3386
2N3436
2N3437
2N3438
2N.3685
2N4118
2N4119
2N3685
2N4118
2N4119
2N3458
2N3459
2N3460
2N3329
2N3329
2N2608
2N3684
2N3684
2N3685
2N3685
2N3686
2N3686
·2N3687
2N3687
2N3819
2N3820
2N3821
2N3822
2N3823
2N3824
2N3331
2N3331
2N3921
2N3922
2N3954
2N3954A
2N3955
2N3955A
2N3956
2N3957
2N3958
2N3966
-f
...
()
0
t/)
t/)
-
:tJ
CD
CD
CD
...
:::I
(')
CD·
C)
C
a:CD
Q)
"
~5
~
Q)
g
..
....
Q)
'0)
Q)
a::
CI),
CI)
e
0
....UJ
..,LL
JFET Cross Reference Guide
INDUSTRY TYPE ' " REPLACEMENT '
N,UMBER
CODE
" 2N3967
2N3967A
': 2N3968
' 2N3968A
2N3969
"2N3969A
llN3970
' ,2N3971
2N3972
2N3993
2N3993A
2N3994
2N3994A
2N4082
"2N4083 '
2N4084
, 21'\14085
.2N4091
• 2N4092
2N4093
2N4117
, 2N4117A
2N4118
2N4118A
2N4119
2N4119A
'2N4139
, 2N4220
2N4220A
'2N4221
2N4221A
2N4222
2N4222A
, 2N4223
2N4224
2N4302
:2N4303 '
,2N4304
2N4,338
2N4339
2N4:340
2N4341
' .. 2N4342
2N4343
,2N4360
2N4381
2N4382
2N4391
2N4392
2N4393
2N4i416
.2N4416A
2N4417
,2N4445
'2N4446
2N4447
2N4448
(Continued)
NATIC;>N~L
INDUSTRY TYPE
NUMBER
PART
NUMBER
2N3967
',,2N3967A
2N3968
2N3968A
2N3969
2N3969A
2N3970
2N3971
' 2N3972
2N3993
2N3993A
2N3994
2N3994A
2N4856
2N4856A
2N4857
2N4857A
2N4858 '
2N4858A
2N4859
2N4859A
2N4860
2N4860A
2N4861
2N4861A
21\14867
2N4867A
'2N4868
2N4868A"
2N4869
2N4869A
2N4881
2N4882
2N4883
2N4884
2N4885
2N4886
:2N4977
2N4918
2N4979
2N5018
2N5019
2N5020
2N5021
2N5033
2N5045
2N5046
2N5047
2N5078
2N5103
2N5104
2N5105
2N5114
2-N5115
2N5116
2N5163
2N5196
2N5197
2N5198
.·2N5199
" 2N5245
2N5246
" 2N5247
' 2N5248
2N5265
'.2N5266
2N5267
2N5268
2N5269
2N5270
CF
CF
*.
CF
•
•
•
'•.
•
•
2N4084
2N4085
2N4091
2N4092
,2N4093
2N4117
2N4117A
2N4118
2N4118A
2N4119
2N4119A
2N4220
2N4220A'
,2N4221
2N4221A
·2N4222
2N4222A
2N4223
2N4224
PN4302
PN4303
PN4304
2N4338
2N4339
,2N4340
2N4341
PN4342
PN4343
PN4360
2N4381
2N4382
2N4391
2N4392
2N4393
2N4416
2N4416A
N
•
•
•
•
2N5432
2N5433
2N5432
2N5433
1',14
REPLACEMENT
CODE
.,
'
NATIONAL
PART
NUMBER
2N4856
2N4856A
2N4857
2N4857A
2N4858
2N4858A'
2N4859
2N4859A
2N4860
2N4860A
2N4861
2N4861A
CF
CF
CF
CF
CF
CF
~
N
N
N
N
N
•
•
•
•
CF
CF
CF
CF
CF
CF
:,,2N5432
2N5433
2N5434
2N5018
' 2N5019
2N5020
2N5021
' PN5033
2N5045
2N5046
: 2N5047
,2N5078
2N5103
2N5104
2N5105
2N51'14
' '~N5115
2N5116
'2N5163
2N5196
' 2N5197
2N5198
,2N5199
2N5245
2N5246
2N5247
2N5248
~
JFET Cross Reference Guide
INDUSTRY TYPE
NUMBER
2N5277
2N5278
2N5358
2N5359
2N5360
2N5361
2N5362
2N5363
2N5364
2N5391
2N5392
2N5393
2N5394
2N5395
2N5396
2N5397
2N5398
2N5432
2N5433
2N5434
2N5452
2N5453
2N5454
2N5457
2N5458
2N5459
2N5460
2N5461
2N5462
2N5463
2N5464
2N5465
2N5471
2N5472
2N5473
2N5474
2N5475
2N5476
2N5484
2N5485
2N5486
2N5515
2N5516
2N5517
2N5518
2N5519
2N5520
2N5521
2N5522
2N5523
2N5524
2N5543
2N5544
2N5545
2N5546
2N5547
2N5549
REPLACEMENT
CODE
NATIONAL
PART
NUMBER
INDUSTRY TYPE
NUMBER
N
N
2N5555
2N5556
2N5557
2N5558
2N5561
2N5562
2N5563
2N5564
2N5565
2N5566
2N5638
2N5639
2N5640
2N5647
2N5648
2N5649
2N5653
2N5654
2N5668
2N5669
2N5670
2N5902
2N5903
2N5904
2N5905
2N5906
2N5907
2N5908
2N5909
2N5911
2N5912
2N5949
2N5950
2N5951
2N5952
2N5953
2N6449
2N6450
2N6451
2N6452
2N6453
2N6454
.2N6483
2N6484
2N6485
A5T6449
A5T6450
AD3954
AD3954A
AD3955
AD3955A
AD3956
AD3957
AD3958
AD5905
AD5906
AD5907
2N5358
2N5359
2N5360
2N5361
2N5362
2N5363
2N5364
CF
CF
CF
CF
CF
CF
2N5397
2N5398
2N5432
2N5433
2N5434
2N5452
2N5453
2N5454
2N5457
2N5458
2N5459
2N5460
2N5461
2N5462
N
N
N
•
•
•
•
•
•
·
2N5020
2N5020
2N5020
2N5020
2N5020
2N5020
2N5484
2N5485
2N5486
2N5515
2N5516
2N5517
2N5518
2N5519
2N5520
2N5521
2N5522
2N5523
2N5524
N
N
·
•
."
(Continued)
2N5545
2N5546
2N5547
2N5397
1-15
m
REPLACEMENT
CODE
•
•
•
n
...
2N5555
2N5556
2N5557
2N5558
2N5561
2N5562
2N5563
2N5564
2N5565
2N5566
2N5638
2N5639
2N5640
2N3686
2N3686
2N3685
2N5653
2N5654
2N5668
2N5669
,2N5670
2N5902
2N5903
2N5904
2N5905
2N5906
2N5907
2N5908
2N5909
2N5911
2N5912
2N5949
2N5950
2N5951
2N5952
2N5953
en
en
:0
N
N
CF
CF
CF
CF
2N6483
2N6484
2N6485
N
N
•
•
•
•
•
•
•
•
•
•
-f
NATIONAL
PART
NUMBER
2N3954
2N3954A
2N3955
2N3955A
2N3956
2N3957
2N3958
2N5905
2N5906
2N5907
0
-...
CD
CD
CD
:s
n
CD
G')
_.
C
Q.
CD
Q)
:2
JFET Cross Reference Guide
"
INDUSTRY TYPE
NUMBER
::l
Q)
(,)
c::
Q)
10.
Q)
Q)
a::
t/)
t/)
o
10.
U
IW
LL
"")
AD5908
AD5909
AD830
AD831
AD832
AD833
AD833A
AD835
AD836
AD.837
AD838
AD839
AD840
AD841
AD842
AD845
AD846
BF244A
BF244B
BF244C
BF245A
BF245B
BF245C
BF246A
BF246B
BF246C
BF247A
BF247B
BF247C
BF256A
BF256B
BF256C
BF264A
BF264B
BF264C
BF264D
C4l3N
C68l
C681A
C683
C683A
C685
C685A
CM640
CM641
CM642
CM643
CM644
CM645
CM646
CM647
CP640
CP643
CP650
CP651
CP652
CP653
REPLACEMENT
CODE
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
(Continued)
NATIONAL
PART
NUMBER
INDUSTRY TYPE
NUMBER
2N5908
2N5909
2N5906
2N5907
2N5908
2N5909
2N5909
NDF9407
NDF9408
ND'F9408
NDF9409
NDF9410
2N5520
2N552l
2N5523
2N5911
2N59l2
BF244A
BF244B
BF244C
BF245A
BF245B
BF245C
BF246A
BF246B
BF246C
BF247A
BF247B
BF247C
BF256A
BF256B
BF256C
BF264A
BF264B
BF264C
BF264D
2N4859
2N4338
2N4338
2N4339
2N4339
2N4220
2N4220
2N439l
2N4391
2N4392
2N439l
2N4393
2N4392
2N4392
El00
El0l
El02
E103
E105
E106
E107
E108
E109
EllO
Elll
El12
El13
El14
E174
E175
E176
El77
E20l
E202
E203
E2l0
E2ll
E2l2
E230
E23l
E232
E270
E27l
E300
E304
E305
E308
E309
, E3l0
E3ll
E3l2
E400
E40l
E402
E4l0
E4ll
E4l2
E420
E42l
FE0654A
FE0654B
FE3819
FE5245
FE5246
FE5247
FE5457
FE5458
FE5459
FE5484
FE5485
FE5486
•
•
•
•
•
•
•
U322
2N439l
U322
U320
U322
U320
1,16
REPLACEMENT
CODE
•
•
•
•
NATIONAL
PART
NUMBER
J202
J20l
J202
J203
N
N
N
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
J108
J109
JllO
Jlll
Jl12
J113
J114
J174
J175
J176
Jl77
J20l
J202
J203
J2l0
J211
J212
. PN3685
PN3684
PN368
J270
J271
J300
J304
J305
J308
J309
J310
J309
J310
CF
CF
CF
CF
CF
CF
•
•
•
•
•
•
•
•
•
•
•
•
•
•
U257'
U257
PN4416
PN4303
2N3819
2N5245
2N5246
2N5247
2N5457
2N5458
2N5459
2N5484
2N5485
2N5486
JFET Cross Reference Guide
INDUSTRY TYPE
NUMBER
FM1100A
FM1101A
FM1102A
FM1103A
FM1104A
FM105A
FM1106A
FM1107A
FM1108A
FM1109A
FM1110A
FM1111A
FM3954
FM3954A
FM3955
FM3955A
FM3956
FM3957
FM3958
FT0654A
FT06548
FT0654C
FT3820
IMF3954
IMF3954A
IMF3955
IMF3955A
IMF3956
IMF3957
IMF3958
IT100
IT101
IT108
IT109
ITE3066
ITE3067
ITE3068
ITE4117
ITE4118
ITE4119
ITE4338
ITE4339
ITE4340
ITE4341
ITE4391
ITE4392
ITE4393
ITE4416
ITE4867
ITE4868
ITE4869
J108
J109
J110
J111
J112
J113
REPLACEMENT
CODE
a
a
..
..
..
...•
..
..
..
..
..
II
II
•..
..
•.
..
...
...
....
...
.
•
..
II
•
•
•.
...
•
•
•
•
•
•
Ii
•
•
•
c...
m
(Continued)
NATIONAL
PART
NUMBER
INDUSTRY TYPE
NUMBER
2N5906
2N5906
2N5907
2N5908
2N5909
NDF9401
NDF9401
NDF9402
NDF9403
NDF9405
2N3957
2N3958
2N3954
2N3954A
2N3955
2N3955A
2N3956
2N3957
2N3958
2N3824
2N3824
2N4221
2N3820
2N3954
2N3954A
2N3955
2N3955A
2N3956
2N3957
2N3958
2N5115
2N5116
2N5486
2N5397
2N4340
2N4338
2N4338
2N4117
2N4118
2N4119
2N4338
2N4339
2N4340
2N4391
PN4391
PN4392
PN4393
PN4416
PN3686
PN3685
PN3684
J108
J109
, J110
J111
J112
J113
J114
J174
J175
J176
J177
J201
J202
J203
J270
J271
J300
J304
J305
J401
J402
J403
J404
J405
J406
J410
J411
J412
J1401
J1402
J1403
J1404
J1405
J1406
KE3684
KE3685
KE3686
KE3970
KE3971
KE3972
KE4091
KE4092
KE4093
KE4220
KE4221
KE4222
KE4223
KE4224
KE4391
KE4392
KE4393
KE4416
KE4856
KE4857
KE4858
KE4859
KE4860
KE4861
KE5103
KE5104
KE5105
MFE2000
MFE2001
1-17
REPLACEMENT
CODE
..
..
..
II
"
•..
..
..
•..
..
..
..
..
..
..
It
It
..
•..
..
..
..
..
..•
'"
NATIONAL
PART
NUMBER
J114
J174
J175
J176
J177
J201
J202
J203
J270
J271
J300
J304
J305
J401
J402
J403
J404
J405
J406
J410
J411
J412
J1401
J1402
J1403
J1404
J1405
J1406
PN3684
PN3685
PN3686
PN4391
PN4392
PN4393
PN4091
PN4092
PN4093
PN4220
PN4221
PN4222
PN4223
PN4224
PN4391
PN4392
PN4393
PN4416
PN4856
PN4857
PN4858
PN4859
PN4860
PN4861
2N5952
2N5953
PN4416
2N4416
2N4416
"-t
("')
(3
C/)
C/)
-
:tJ
CD
CD
CD
..,
::I
n
CD,
C)
_.
r::
a.
CD
cu
'C
..::l
CJ
CU
(.)
·C
...CU
CU
CU
a:
en
en
...
0
0
tW
...,
U.
JFET Cross Reference Guide
INDUSTRY TYPE
NUMBER
MFE2004
MFE2005
MFE2006 .
MFE2007
MFE2008
MFE2009
MFE2010
MFE2011
MFE2012
MFE2093
MFE2094
MFE2095
MFE2133
MFE4007
MFE4008
MFE4009
MFE4010
MFE4011
MFE4012
MPF102
MPF103
MPF104
MPF105
MPF106
MPF107
MPF108
MPF109
MPF111
MPF11i
MPF161
MPF256
MPF820
MPF970
MPF971
MPF4391
MPF4392
MPF4393'
NDF9401
NDF9402
NDF9403
NDF9404
NDF9405
NDF9406
NDF9407
NDF9408
NDF9409
NDF9410,
NF500
NF501
NF506
NF510
NF520
NF521
NF522
NF523
NF530
NF531
REPLACEMENT
CODE'
•
•
•
•
•
•
•
•
•
•
'.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
..•
•
•
•
•
•
•
(Continued)
NATIONAL
PART
NUMBER
INDUSTRY TYPE
.NUMBER
REPLACEMENT
CODE
2N4393
2N4392
2N4391
2N4857
2N4391
2N4856
2N4856
2N5433
2N5433
2N3687
2N3686
2N3685
2N4392
2N2608
2N2608
2N3329
2N3330
2N3330
2N3331
MPF102
MPF103
MPF104
MPF105
MPF106
MPF107
MPF108
MPF109
MPF111
MPF112
2N5461
J211
J309
P1086E
P1087E
PN4391
PN4392
PN4393
NDF9401
NDF9402
NDF9403
NDF9404
NDF9405
NDF9406
NDF9407
NDF9408
NDF9409
NDF9410
2N4224
2N4224
2N3823
. 2N4092
2N4224
2N4220
2N4224
2N4220
2N3822
2N3821
NF532
NF533
NF580
NF581
NF582
NF583
NF584
NF585
NF4302
NF4303
NF4304
NF4445
NF4446
NF4447
NF4448
NF5101
NF5102
NF5103
NF5163
NF5457
NF5458
NF5459
NF5485
NF5486
NF5555
NF5638
NF5639
NF5640
NF5653
NF5654
NPD5564
NPD5565
NPD5566
NPD8301
NPD8302
NPD8303
NPD9801
NPD9802
NPD9803
P1069E
P1086E
P1087E
P1117E
P1118E
P1119E
PF510
PF511
PF5101
PF5102
PF5103
PN3684
PN3685
PN3686
PN3687
PN4091
PN4092
PN4093
•
•
•
•
•
•
•
•
1·18
•
•
•
•
•
•
•
..
•
•
•
•
•
•
•
•
•
•
•
NATIONAL
PART
NUMBER
2N3822
2N3821
2N5432
2N5432
2N5434
2N5434
2N5432
2N5433
PN4302
PN4303
PN4304
2N5432
2N5433
2N5432
2N5433
NF5101
NF5102
NF5103
2N5163
, 2N5457
2N5458
2N5459
2N5485
2N5486
2N5555
2N5638
2N5639
2N5640
2N5653
2N5654
.NPD5564
NPD5565
NPD5566
NPD8301
.NPD8302
r NPD8303
NPD9801
NPD9802
NPD9803
P1086E
P1087E
CF
CF
CF
•
•
PN4392
PN4392
PF5101
PF5102
PF5103
PN3684
PN3685
PN3686
PN3687
PN4091
PN4092
PN4093
JFET Cross Reference Guide
INDUSTRY TYPE
NUMBER
PN4220
PN4221
PN4222
PN4223
PN4224
PN4302
PN4303
PN4304
PN4342
PN4343
PN4360
PN4391
PN4392
PN4393
PN4416
PN4856
PN4857
PN4858
PN4859
PN4860
PN4861
PN5033
PN5163
SU2078
SU2079
SU2080
SU2081
SU2098
SU2098A
SU2098B
SU2099
SU2099A
SU2365
SU2365A
SU2366
SU2366A
SU2367
SU2367A
SU2368
SU2368A
SU2369
SU2369A
SU2410
SU2411
SU2412
TD5452
TD5453
TD5454
TD5902
TD5902A
TD5903
TD5903A
TD5904
TD5904A
TD5905
TD5905A
TD5906
REPLACEMENT
CODE
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
II
•
•
'.••
•
•
•
•
•
•
•
•
•
c..
'TI
m
(Continued)
NATIONAL
PART
NUMBER
PN4220
. PN4221
PN4222
PN4223
PN4224
PN4302
PN4303
PN4304
PN4342
PN4343
PN4360
PN4391
PN4392
PN4393
, PN4416
PN4856
PN4857
PN4858
PN4859
PN4860
PN4861
PN5033
PN5163
2N3955
2N3956
2N3954
2N3954
2N3954A
2N3955A
2N3955A
U401
U401
U402
U402
U403
U403
U404
U404
U'405
U405
U424
U425
U426
2N5452
2N5453
2N5454
2N5902
2N5902
2N5903
2N5903
2N5904
2N5904
2N5905
2N590!)
2N5906
1-19
INDUSTRY TYPE
NUMBER
REPLACEMENT
CODE
TD5906A
TD5907
TD5907A
TD5908
TD5908A
TD5909
TD5909A
TD5911
TD5911A
TD5912
TD5912A
TIS25
TIS26
TlS27
TlS34
TIS41
TIS42
TIS58
TIS59
TIS68
TIS69
TIS70
TIS73
TIS74
TIS75
TIS78
TIS79
TIS88A
U110
Ul12
Ul14
U133
U146
. U147
U148
U149
U168
U182
U183
U184
U197
U198
U199
U200
U201
U202
U231
U232
U233
U234
U235
U240
U241
U242
U243
U244
U248
•
•
•
•
•
•
•
•
•
•
•
NATIONAL
PART
NUMBER
2N5906
2N5907
2N5907
2N5908
2N5908
2N5909
2N5909
2N5911
2N5911
2N5912
2N5912
•
•
2N5486
2N4859
PN4392
TIS58
TIS59
N
TIS73
TIS74
TIS75
N
N
•
..•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
CJ)
:::c
(t)
..,
( t)
(t)
~
o
(t)
G')
a.
(t)
N
N
•
•
•
•
•
oCJ)
r::
N
N
N
•
-I
n
..,
2N5486
2N5020
2N4381
2N5020
2N5020
2N5020
2N5020
2N2608
2N2609
2N2608
2N4857
2N3823
2N4416
2N4338
2N4340
2N4341
2N4393
2N4392
2N4391
U231
U232
U233
U234
U235
2N5432
2N5433
2N5432
2N5433
N
2N5902
G)
:2
j
CJ
G)
CJ
C
-G)
G)
G)
a:
(/)
(/)
0
0
ILIJ
..,
u..
JFET Cross Reference Guide
INDUSTRY TYPE
NUMBER
U248A
U249
U249A
U250'
U250A
U251
U251A
U252
U253
U254
U255
U256
U257
U266
U280
U281
U282
U283
U284
U285
U290
U291
U300
U301
U304
U305
U306
U308
U309
U310
1I311
U312
U320
U321
U322
U328
U329
U330
U331
U350
U401
U402
U403
U404
U405
U406
U421
U422
U423
U424
U425
U426
U430
U431
U1714
U1715
U1837E
REPLACEMENT
CODE
•
N
•
•
•
•
•
•
N
(Continued)·
NATIONAL
PART
NUMBER
INDUSTRY TYPE
NUMBER
U1897E
U1898E
U1899E·
U1994E
U2047
UC155
UC200
UC201
UC210
UC220
UC241
UC250
UC251
UC400
UC401
UC410
UC420
UC588
UC703
UC705
UC707
UC714
UC734
UC734E
UC755
UC756
UC805
UC807
UC814
UC851
UC854
UC855
UC2J39
UC2147
UC2148
UC2149
VCR2N
VCR3P
VCR4N
VCR5P
VCR7N
2N5906
2N5903
2N5907
2N5904
2N5908
2N5905
2N5909
2N5911
2N5912
2N4859
2N4860
2N4861
U257
2N3954
2N3954
2N3955
2N3955
2N3956
2N3957
N
"
•
•
•
•
U300
U301
2N5114
2N5116
2N5117
U308
U309
U310
U311
U312
U320
U321
U322
N
N
N
N
•N
•
U350
U401
U402
U403
U404
U405
U406
U421
U422
U423
U424
U425
U426
U430
U431
2N4340
2N5486
1-20
REPLACEMENT
CODE
••
•
•
•
"
"
"
"
"
"
•
•
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
CF
NATIONAL
PART
NUMBER
U1897E
U1898E
U1899E
PN4416
PN4416
2N4416
2N4393
2N4416
2N3822
2N4220
2N3822
2N4391
2N4392
2N2609
2N5019
2N2609
2N3329
2N4416
2N3822
2N3824
2N4391
2N4416
2N4416
PN4416
2N4391
2N4224
2N3331
2N4861
2N3331
2N2608
CF
CF
CF
CF
CF
"
"
"
"
"
2N4092
2N5115
2N4341
2N3331
2N4119
DEVICE
NUMBER
TVPE/RONIV AIVS
NATIONAL
PIN-FOR-PIN
FUNCTIONAL
EQUIVALENT
DEVICE
NUMBER
NATIONAL
PIN-FOR-PIN
TVPE/RONIV AIVS
FUNCTIONAL
EQUIVALENT
Analog Devices
AD7516
4-SPST/28011/±7.5V/i 7.5V
CD4066
Fairchild
F4016
F4051
F4052
F4053
F4066
4 SPST/800I1h7.5V/±7.5V
8-Ch. MUX/28011/±7.5V/±7.5V
4-Ch. MUX/280n/±7.5V/±7.5V
3-SPDT/28011h7 .5V I± 7 .5V
4-SPST/28011h 7 .5V I± 7 .5V
CD4016
CD4051
CD4052
CD4053
CD4066
Harris
HD4051
HD4052
HD4053
HD4066
8-Ch MUX/280n/±7.5V/±7.5V
4-Ch MUX/28011/±7.5V/±7.5V
3 SPDT/28011/±7.5V/±7.5V
4-SPST/28011/± 7.5V I± 7.5V
CD4051
CD4052
CD4053
CD4066
Intersil
DGlll
DG112
,;"
DGl16
DGl18
DG126/DG426
DG 129/DG429
DG133/DG433
DG 134/DG434
DG139/DG439
DG140/DG440
DG141IDG441
DG142IDG442
DG143/DG443
DG 144/DG444
DG145/DG445
DG146/DG446
DG151/DG451
DG152/DG452
DG153/DG453
DG 154/DG454
DG161/D·G461
DG 162/DG462
DG 163/DG463
DG164/DG464
DGl72
2-SPST /1 00-450n/± 1OV 1-20V,
10V,5V
2-SPST/l 00-45011/± 1OV 1-20V,
10V,5V
4-SPST/l 00-450n/± 1OV/-20V,
10V,5V
4-SPST/l 00-450·W± 1OV 1-70V,
10V,5V
2-DPST/8011/± 10V/-18V,12V
2-DPST/30W± 10V1-18V ,12V
2-SPST/30W±10V/-1BV,12V
2-SPST/80n/± 1OV 1-18V ,12V
DPDT/30n/±10v/±15V
2-DPST/l0fl./±lOVH8V,12V
2-SPST/l0fl./±10V/-18V,12V
DPDT180nl± 1OV 1-18V,12V
SPDT/80fl.1±10V/-18V,12V
SPDT/30fl./±10V/-18V,12V
2-DPST/l0W±10V/-18V,12V
SPDT 11 011/± 10V1-18V ,12V
2-SPST/1511/± 7:5V I± 15V
2-SPST/50W±7.5V 1±15V
2-DPST/l0fl./±7.5V/± 15V
2-DPST/50W±7.5V/±15V
SPDT/15f1./± 7.5V/± 15V
SPDT/50fl./±7.5,!1±15V
DPDT/15W±7.5V/i 15V
DPDT/50fl./±7.5V/±15V
4-SPST/200-600W±10V/-20V, 10V, 5V
AM182
AM182
AHOO15
AHOO15
AH0126
AH0129
AH0133
AH0134
AH0139
AH0140
AH0141
AH0142
AH0143
AH0144
AH0145
AH0146
AH0151
AH0152
AH0153
AH0154
AH0161
AH0162
AI:l0163
AH0164
DG181
DG182
DG184
DG185
DG187
DG188
DG190
DG191
IH5001
IH5002
IH5003
IH5004
IH5005
IH5006
IH5007
IH5009
IH5010
IH5011
IH5012
IH5013
IH5014
IH5015
IH5016
MM450/MM550
MM451/MM551
MM452/MM552
MM455/MM555
DG50B
DG509
IH5060
IH5070
2-SPST/30n/-7 .5V ,15V I± 15V ,5V
2-SPSTI7511/-1 OV,15V/± 15V,5V
2-DPST/30n/-7.5V, 15V/± 15V,5V
2-DPSTI75l!/-1 OV,15V/± 15V,5V
SPDT 130n/-7.5V,15V I± 15V ,5V
SPDT 175n/-l0V ,15V I± 15V,5V
2-SPDT/30n/-7 .5V,15V/± 15V ,5V
2-SPDTI75n/-l0V,15V/i 15V,5V
SPST/30n/±8V/-18V,12V
SPST/5011/±8V 1-18V,12V
2-SPST/30n/± 10V/-18V,12V
2-SPST/5011/± 10V/-18V,12V
2-SPST/l On/± 10V/-18V,12V
2-SPST130n/± 1OV 1-18V,12V
2-SPST/8011/± 1OV 1-18V ,12V
4-Ch. MUX/l00n/±0.2V
4-Ch. Mux/150n/±0.2V
4-SPST 11 00n/±0.2V
4-SPST/15011/±0.2V
3-SPST 11 OOI1/±O.2V
.3-SPST/150n/±0.2V
3-SPST/l0011/±0.2V
3-SPST/150W±0.2V
2-DPDT 1200-600n/± 1OV
4-Ch. MUX/200-600n/±10V
4-SPST1200-600111 ± 1OV
3-SPST1200-600W ± 1OV
8-Ch. MUX/450W'I±15V
4-Ch. Diff. MUX/45011/' I± 15V
16-Ch. MUX/400W'I±15V
8-Ch. Dill. MUX/400n/'1±15V
AM181
AM182
AM184
AM185
AM187
AM188
AM190
AM191
1/2AH0133
1/2AH0133
AH0133
AH0134
AH0141
AH0133
AH0134
AH5009/AM9709
AH501 01 AM9710
AH5011/AM9711
AH5012/AM9712
AH5013
AH5014
AH5015
AH5016
MM450/MM550
MM451/MM551
MM452/MM552
MM455/MM555
LFl1508
LFl1509
LFl1506
LFl1507
Motorola
4-SPST 1400n/±7 .5V I± 7 .5V
8-Ch. MUX/280l!/±7.5Vh7.5V
4·Ch. MUX/28011/!7.5V/±7.5V
3-SPDT/28011h 7.5V I± 7.5V
4-SPDT/280n/i 7.5V/± 7.5V
4-Ch. MUX/270fl/±7.5Vh7.5V
MC14016
MC14051
MC14052
MC14053
MC14066
MC14529
CD4016
CD4051
CD4052
CD4053
CD4066
CD4051
AHOO15
*Denotes items which have a maximum analog voltage of ±15V. the National equivalent devices have ±10V maximum analog voltage.
-
------
ap!n~ a~UaJalal:l SSOJ:> lI~I!MS
601eU,",
Analog Switch Cross Reference Guide
DEVICE
NUMBER
RCA
CD4016
C04051
C04052
C04053
C04066
Siliconix
OG111·
,;"
'"
DG126
OG129
DG133
OG134
DG139
OG140
OG141
OG142
OG143
DG144
DG145
DG146
OG15l
OG152
OG153
OG154
DG161
DG162
OG163
OG164
OGl72
OG173
OG181
OG182
DG184
OG185
OG187
DG188
DG190
TVPE/RONIV AIVS
NATIONAL
PIN-FOR·PIN
4-SPST/S50W±7.5V/±7.5V
S-Ch. MUX/2S0W±7.5VI!7.5V
4-Ch. MUX/2S0n!±7.5V/'7.5V
3-SPOT/2S0n/±7.5V/' 7.5V
4-SPST/2S0n/-7".5V/'7.5V
CD4016
C04051
C04052
CD4053
C04066
2-SPST /1 00~450n/± 1OV /-20V,
-10V, -5V
2-0PST/SOH/± 1OV /-lSV,12V
2-D PST /30n/'l OV /-lSV, 12V
2-SPST/30H/± 10V/-1SV, 12V
2-SPST/80l1/± 10V/-18V,12V
DPDT/30n/± 10VI ±15V
2,OPST!10nl ± 10V/-1SV, 12V
2-SPST/l0n/±10V! 18V,12V
OPDT/SOH/±10V/-1SV,12V
SPDT/SOW ± 10V/-18V, 12V
SPDT/30l1/± lOV/-18V,12V
2-0PST/l on/± 1OV/·-18V, 12V
SPDT/l0n/ ± 10V/-1SV, 12V
2-SPST/15n/±7.5V/± l5V
2-SPST/50fl/±7.5V/±15V
2-0PST/l on/± 7 .5V I~ 15V
2-0PST/50n/±7.5V/±15V
SPOT/15n/±7 .5VI ± 15V
SPDT/50n/±7.5V/±15V
OPOT/15H/±7.5V/± 15V
OPDT/50Sl/·± 7 .5i11' 15V
4-SPST 1200-600n/± 1OV /-20V,
10V,5V
DPDT 1150-500W ± 1OV /-20V
10V,5V
2-SPST/30n/-7.5V,15VI ± 15V,5V
2-SPST/75n/--l OV, 15V/ ±15V,5V
2-0PST/30Sl/7.5V,15V/± 15V,5V
2-0PST/75H/-l OV, 15V/±15V,5V
SPOT/30W-7 .5V, 15V/± 15V,5V
SPOT/75H/-l0V,15V/±15V,5V
2-SPOT/30H/-7.5V,15V/,15V,5V
AM01S2
FUNCTIONAL
EQUIVALENT
DG191
DG201
OG501
OG511
DG506
OG507
DG50S
OG509
DGM122
AH0126
AH0129
AH0133
AH0134
AH0139
AH0140
AH0141
AH0142
AH0143
AH0144
AH0145
AH0146
AH015l
AH0152
AH0153
AH0154
AH0161
AH0162
AH0163
AH0164
S1455/S1555
AM181
AM182
AM184
AM1S5
AM187
AM188
AM190
TVPE/RONIV AIVS
NATIONAL
PIN-FOR-PIN
2-SPDT/75n/-10V, 15VI! 15V,5V
4-SPST/100n/'/ ± 15V
S-Ch. MUX/200-S00n;'_5V/-15V,5V
4-Ch. Dill. MUX/200-700n/±10V/
-20V,10V
16-Ch. MUX/400n/'1-15V
S-Ch. Di{f. MUX/400rw/± 15V
S-Ch. MUX/400n/'/±15V
4-Ch. Dllt. MUX/400n/'!±15V
2-0PST/l 00-500n/± 1OV 1-20V,
10V,5V
3-SPST/200-600n/± 1OV /-20V,
10V,5V
AM0191
LFl1201
4-SPST/400nh_7 .5V/±7 .5V
C04016
C·D4051
FUNCTIONAL
EQUIVALENT
AM3705
MM454/MM554
LFl1506
LFl1507
LF1150S
LFl1509
AHOO19
MM455/MM555
Salitron
CM4016
CM40S1
CM4052
CM405·3.
CM4116
8-Ch. Mux/2S0nI±7.5Vh7.5V
4-Ch. MUX/280n/±7.5VI±7.5V
3-SPDT/2S0n/± 7 .5V /± 7 .5V
4-SPST/soon/±7 .5V/±7 .5V
C04052
CD4053
C04016
Teledyne-Crystalonics
AHOO15
AHOO14
DEVICE
NUMBER
CAG-l0
CAG-13
CAG-14
CAG-21
CAG-22
CAG-23
CAG-24
CAG-27-10
CAG-30
CAG-42
CAG-45
CAG-48
CD4066
CS4R
SPST/50fl/-l0VAV/±15V,5V
2-SPST/50fl/± 10V/--18V,15V
SPST/50n/-l0V,5V!± l5V,5V
2-DPST 130n/-6V, 1OV 1-18V, 15V
2-SPST /30n/--6V, 1OV 1-18V, 15V
2-SPST 150n/± 1OV 1-18V, 15V
2-SPST/30n/-6V,1 OV 1-1SV, 15V
2-SPST/l OW--6V, 1OV /-18V, 15V
SPST/60nl ± 10V/± 15V,5V
2-SPST/60n/± 1OV 1-18V, 15V
2-SPST/60n/ ± 1OV /-18V, 15V
2-SPST/60H/± 10V/-18V, 15V
4-SPST/280n/f 7.5V / ± 7 .5V
2-DPST/15n/± 10V/-18V,15V
1/2AM182
AH0134
1/2AM0182
AH0129
AH0133
AH0134
AH0133
AH0141
1/2AM182
AH0134
AH0134
AH0134
CD4066
AH0140
Texas Instruments
TF40i6
TF4051
TF4052
TF4053
4-SPST 1400H1±7.5VI± 7.5V
8-Ch. MUX/280n/± 7.5V/±7.5V
4-Ch. MUX/280H/'7.5V/± 7.5V
3-SPOT/280fl/'l.5V/±7.5V
C04016
CD4051
CD4052
C04053
""
o
:::T
Choose The Proper FET
National Semiconductor utilizes 17 different FET geometries to cover, without compromise, the full spectrum
of applications. Specific part number characteristics are summarized into application areas further on within
this section. In addition, this section includes process comparison charts which graphically indicate the typical
values of a given parameter for all geometries under identical test conditions. Detailed data on each process,
along with a list of all part numbers manufactured from each process, is to be found in Section 3.
To further simplify the selection procedure, the F ET Family Tree is included for quick identification. After·
narrowing down the process types, it is suggested that the process sheets and ~pecific part number characteristics be consulted.
.
FET FAMILY TREE
N-CHANNEL SINGLES
P-CHANNEL SINGLES
N-CHANNEL DUALS
I
I
I
GENERAL PURPOSE AMP
P50 .- g" 3-7 mmhos
IDss 1-20 rnA
P52 - g" 0.5-3 mmhos
IDss 0.1-10 rnA
P55 - g.s 0.8-5 mmhos
IDss 0.5-17 rnA
I
GENERAL PURPOSE AMP
GENERAL PURPOSE
P88 - 9,,4-17 mmhos
loss 5-90 rnA
P89 - 9" 1-4 mmhos
IDSS 0.3-20 rnA
P8J -IG 3 pA@20V
9" 0.85 mmho @0.2 rnA
P94 - IG 1 pA@35V
CMRR 125 dB
I
I
RF/VHF/UHF
P50 - Gps 12 dB@400MHz
~5.5 mmhos
P90 - Gpt 11 dB@450MHz
%Bmmhos
P92 - Gpg 12 dB @450 MHz
g" 19 mmhos
SWITCH/CHOPPER
P88 - 'DS 50-200 ohms
ID(oFFI 50 pA
P89 - 'cis 450 ohms
ID(oFFI 20 pA
ULTRA-LOW INPUT CUR
P84 - 1 pA@25V
gls 175 J.lmho
P86 - IG 0.1 pA
9fs 500 J.lmho
I
I
ULTRA-LOW LEAKAGE AMP
WIDE BAN D-LDW NOISE
P50 - IGSS 5 pA @20V
%3-7 mmhos
P53 - IGss·0.3 pA@2oV
9" 0.08-0.3 mmhos
P93 -
~
6 mmhos @5 rnA
Cis 4.2 pF
P96 - 9,,9 mmhos@2mA
Cis 10 pF
I.
I
LOW FRED-LOW NOISE AMP
LOW FRED-LOW NOISE
P50 - en 8 nV/$.@ 10 Hz
Cis 3 pF
P51 - en 6 nV/,jFiZ@ 10 Hz
~20 mmhos
P95 - en 8 nVl$.@ 10 Hz
g" 1-4 mmhos
P96 - en 7 nV/y'Hz@ 10 Hz
~ 10-22 mmhos
I
SWITCH/CHOPPER
P50 - 'DS 100-500 ohms
ID(oFFI5 pA
P51 - 'os 20-100 ohms
ID(oFFI 15 pA
P58 - 'DS 3-20 ohms
ID(oFFI 50 pA
All values are typical
2-3
o
oCh
CD
-I
:::T
CD
."
a
"C
...
CD
cu
"C FET Application Guide
.::J
"o
C
National Sem iconductor manufactures a broad line of silicon Junction Field Effect Transistors (JF ETs).
National's JFETs provide excellent performance in many areas such as RF amplifiers, analog switching, low
input current amplifiers, low noise high impedance amplifiers and outstanding matched duals for operational
amplifiers input applications.
:;;
CO
.~
Q.
c.
100 MHz
;:';q:
co
I
~~
;;
N
50
51
52
53
S
P
Low Noise Amp (10Hz enl
S
Low Noise Amp> 50 MHz
P
P
I I
"''''
~:!
zz
N
N
::l
"'N
83
84
86
P
P
NIn
1,1
....
Z z' zz
N
'"
N
'"
55
I
N
z
N
58
I
I
~'"
N
S
P
S
S
P
P
P
S
S
0
::l
I
;:.;
P
S
P
P
P
P
P
P
P
P
Low Leakage Diode.
P
P
P
Dill/Angle Ended Inp, Stag.
P
Voltage Variabl,e Resistor
P
P
Hybrid Chips
P
Analog/Digital Switch
P
Multiplexing
Choppers
ico
0
0
0
!:l
0
I
'"co
z'"
N
~.
'"z
It>
In,
In
N
::l
z
.'"
N
....
'"'"'"z
N
Z
N
N
88
89
90,
92
93
94
95
P
P
P
P
S
S
P
P
P
o~
"'In
zz
ai
I
co
0
N
!:l
o·
i
'"
'"
0
I'"
;;;
It>
P
P
P
P
P
P
P
P
0
IL
c
I
~
'"z
z
'"""I
'"z
96
98
'"I
;!;
10
It>
N
P
P
P
P
P
P
P
P
S
P
P
P
Electrometer Preamp
Oscillator
Z
N
..
I
..
0
P
Microvolt Amplifier
P
In
0
S
P
Active Filter
N
'"I
'"In
P
Dual Diff Pair
AGe Amplifier
0::
'"I
'"
'"'"z
~~
~
0
.'"'"
.
N' '"
Iq:
'"co
Z
ail
ZZ
P
P
Z
N
'" o..
General Purpose Amplifier
N
N
W
....
I
I
",' co
ZZ
Z
....
In
In,
In
N'
'" o..
100 Hz
High Frequency Mixer
z
N
:;;:
N
,.!.
N
In
coco
Low Current Amplifier
Low Freq Ampli
I
co
P
P
P
P
S
P
S
P
'S
P
P
P
P
S
P
P
P
P
P
S
S
P
P
P
S
P
P
P
P
P
P
P
P
P
S
P
P
P
P
P
P
S
S
P
Nixie Drivers
P
Reed Relay Replacement
Sub pA Dual Dill Pair
P
Sample-Hold
P
P
S
Buffer Interface to CMOS
Matched Switch
P
S
P
P
P
P
S
P
HF;:: 400 MHz Prime
P
Current Limiter
Current Source
P - Prime Choice
,
P
P
S
P
S
S - Secondary (Alternatel Choice
I
2-4
S'
,P
S
P
P
FET Application Guide
."
m
(Continued)
-I
»
'C
"C
-
-,
ADVANTAGES OF USING FIELD-EFFECT TRANSISTORS
APPLICATION
ADVANTAGES
FINAL ASSEMBLY WHERE USED
DC Amplifiers
High Zin
Low drift duals
Low noise
Transducers, military guidance
systems, control systems, temp
indicators, multi meters
Low frequency
amplifiers
Small coupling capacitors
Low noise, distortion
High input impedance
Sound detection, microphones,
inductive transducers, hearing aids,
high impedance transducers
Operational
amplifiers
Summing point essentially
zero. Low device noise.
Less loading of transducers
Control systems, potted op amps,
test equipment, medical electronics
Medium and high
frequency
amplifiers
Low cross modulation
Low device noise
Simplified circuitry
FM tuners, communication received
scope inputs, most instrumentation
equipment, high impedance inputs
Mixers - 100 MHz
and up
Low mixing noise
Low cross modulation
FM tuners, communication receivers
Oscillators
Low drift
Transmitters, receivers, organ
Logic gates
Vi,rtually infinite fan in
Simplified circuitry
Zero storage time
Symmetrical
Guidance controls, computer market
mini military teaching aids, traffic
control, telemetry
Choppers
Zero offset
Low leakage currents
Simplified circuitry
Eliminates input transformers
Op amp modules guidance controls
instrumentation equipment
AD Converters
Multiplex switching
(arrays) and sample hold
Improved isolation of input
and output. Zero offset.
Symmetrical. Low resistance
Simplified circuitry
Control system, DVM's and any readout equipment, medical electronics
Relay contact
replacement
Solid state reliability
Zero offset, High isolation
Symmetrical
No inductive spring
No contact bounce
High repetition rate
Test equipment, airborne equipment
instrumentation market
Voltage variable
resistor
Symmetrical
Solid state reliability
Functions as variable resistor.
Low noise. High isolation
Improved resolution
Organ, tone controls, control ckts to
input operational amplifiers
Current limiters
Sources
Two lead simplicity
Wide selecti on range
Low voltage operation
Hybrid circuits, amplifiers, power supply
protection, timing ckts, voltage
regulators
2-5
(')
Q)
0'
::l
C)
s::::
a:
(I)
..
c
o Important· Parameters by Application
CO
;~
-0.
0.
«
~
.c
LISTED IN APPROXIMATE ORDER OF IMPORTANCE
...
tJ)
SQ)
E
...COCO
-...
0.
c
S
o
0.
E
~
Low
Frequency
Amplifier
Source
Follower
Yfs
Yfs
Electrometer
Amplifier
IG
Low
Drift
Amplifier
IOZ
Low
Noise
Amplifier
High
Frequency
Amplifier
Oscillator
en
Re(Yfs)
Yfs'
Differential
Amplifier
IVGS1-VGS21
Analog
and
Digital
Switch
ROS(ON)
AIVGS1-VGS21
lOSS
IG
Yfs
Yfs @ IOZ
Re(Yis)
IG
10(off)
lOSS
AT
VGS(offl
C rss
10Z
VGS@IOZ
in
NF
C rss
Ciss
C rss
Ciss
en
IG
Yfs
C rss
Ciss
IIG1- IG21
IG
Ciss
C rss
lOSS
90S
BVGSS
lOSS
Re(yos)
VGS(off)
Yfs
VGS(off)
en
VGS(off)
BVGSS
VGS(off)
lOSS
BVGSS
Yfsl/Yfs2
BVGSS
BVGSS
VGS(off)
IYosl-Yos21
CMRR
VGS(off)
,
2-6
."
m
FET Process Comparison Curves
-t
Dual FET Drain Saturation Current vs
Cutoff Vol tage
C[
.§.
I2
...
2
0
i=
cC
a::
50 I-TA =25°C
i-
10
5
J
I
,
I I
0.5
I
""
~
~P03
0.1
(")
CD
w
(J)
a::
a::
=>
en
...
• P83/P04
5
~
a::
=>
'C
lcC
/
2
cc
I
/
0.5
a::
c
100
c
50
~
0.1
-1 -2 -3 -4 -5 -6 -7 -8 -0 -10
VGSfOFFI - GATE·SOURCE CUTOFF VOLTAGE (V)
Single FET Transconductance vs Cutoff
Voltage
...
...=>
2
cC
I-
10
~
C
:;;io'"
2
...
0
a::
l-
~
...w
I
P03
...=>
I: P83/P~4
~
C
2
P05
...en
0.5
a::
l-
)"
oil!
'"
~
~ :::: P50(N)
P55(N)
TA = 25°C
C = CASCODE
I2
w
a::
a::
=>
...
P031
100
50
cC
::.:
cC,
...
w
lf~
10
5
..""
w
lcC
c:J
, I
~P96= ~83=
I /
w
c:J
/
"~05:
~ ",.. ~-
0.5
PB4(C)
~
I
~
0.1
o
5
~P80(P)
-
P53(N)
VGSfOFFI - GATE·SOURCE CUTOFF VOLTAGE (V)
Dual FET Gate Leakage Current vs
Draln·Gate Voltage
.e-
POo(N)
-1 -2 -3 -4 -5 -6 -7 -8 -9 -10
VGSfOFFI - GATE-SOURCE CUTOFF VOLTAGE (V)
1000
500
P02(N) I P88(P)
0.1
-1 -2 -3 -4 -5 -6 -7 -8 -0 -10
C[
J P51(N)
......
,
I
P8,4
10
15
20
25
30
VDG - DRAIN·GATE VOLTAGE (V)
2·7
o
35
o
C
<
CD
en
I
P52(N)
2
cC
oil!
---
~~
".
0
0.5
0.1
10
5,
2
cC
'I-
I
'"
50
.§.
V"
en
2
cC
--
5
--
Q
.c
E
poJ
uS'
:l
100
=TA =125oC
.§.
w
I-+--t-"...q..-+---l-i-+--+-~
I
-1 -2 -3 -4 -5 -6 -7 -8 -0 -10
...
Q)
en
Dual FET Transconductance ,vs Cutoff
Voltage
.c
o
o
3
10
2
o
VGSfOFFI - GATE·SOURCE CUTOFF VOLTAGE (V)
Q
a
I2
.,P84
0
!l"I
.E
, """"
P05
P06
-
L
lcC
en
cca::
,
~
=>
2
-0
100
w
a::
a::
=>
Single FET Drain Saturation Current vs
Cutoff Voltage
FET Process Comparison Curves
(Continued)
Single FET Gate Leakage Current vs
Drain-Gate Voltage
<
..s-
1000
500
P50(N)t:_P51 !1in - -P53(N)
I
P90(N) II I
I-
...a:z
a:
:::;)
...
cc
::.:
cc
...
.......
!;:
Cl:I
1
~
L
100
50 i - P92(N
l
CoO
Cl:I
ON Resistance vs Cutoff Voltage
1
0.5
0.1
P89(P
~
o
5
., V"
10
~88(P)
'"rnw
100
:2
50
a:
"'
CI
CoO
20
25
CI
~
10
cca:
5
:2
30
CI
1
.?
35
...
o
~
z
cc
a:
j
""'"
N·Channel
P·Channel
Dual N·Channel
Quad P·Ch.nnel
~
P58(N)
-1 -2 -3 -4 -5 -6 -7 -8 -9 -10
10
a:
a:
1
0.5
...
II,
~89
:2
P52/
CI
i=
cc
0:
:::;)
l-
0.5
0.1
0.05
'"
:2
cc
:5
0.1
0.05
0.01
j
II j
cc
I
0.01
D.5 1
J55r
10
5
:::;)
5
5 lD
50 lDD
~t
alas
~
Selection Guide
~
N-Chaonel FETs
GENERAL PURPPSE AMPS (Continued)
BVGSS
-BVGDO
Ca..
Style
(VI
Min
2N4220
TO·72
30
2N4220A
TO-72
30
2N4221
TO-72
30
2N4221A
TO-72
2N4222
TO-72
Transistor
Type
2N4222A
.:~
TO-72
I
@
IG
IGSS
lOGO
(nAI @ VOG
(VI
(nAI
Min
15
4
15
.1
0.5
15
4
15
.1
0,5
0.1
15
6
15
10
0.1
15
30
10
0.1
15
30
10
Max
IV)
10
0.1
10
0.1
10
30
2N4339
,TO-IS,
TO-IS
2N4340
: To-is
50
50
50
~9tl
TQ-18,
Jill
2N5103
TO-72
25
2N5104
TO-72
2N5105
:~535s,
0.1
15
~
~.
~,
0.1
;"~
0.1
~
{I.!
,~'
0.1
15
25
0,1
':-' I,: ', i s3s9'
TO·72
25
TO-72,
-2'1~1 '
T0-72
TO- 72
~
fN!i362'
i ,:iN~'
Tp.n
TO-12
TO-12
Mil}
0.1 ,"
I'
N
10
15
6
15
o
2
15
10
15
6
15
2
15
.1
6
15
15
20
15
6
15
o
o
2
15
15
.1
6
15
15
20
15
6
15
0
2
15
15
.1
15
15
15
40
15
6
15
0
2
15
15
6
15
0
Ii; . . 0
3'
a
i5
3
3
15
15
.0
'0
15
o
o
15
.1
5
15
JOO
0.2
2.5
0.6
.0.8,
15."
0.5
4
15
15
0.5
4
15
2
0.1
15
0.5
4
15
5
40
40
40
40
0;1
',20
0.5:,
3
0.1'
,20
tie
4'
(>.1
20
0.8
40
40
6.1
'
1
'100
'Hio'
4',1~
"20'2.5'
16
ioo
{}'5,
8
15
10
,,15
10
,2
e
:.}/i. ,,:,,0"
4
2N5557
TO·72
30
0.1
15
0.8
2N555S
TO-72
0.1
15
6
l-0:.92
-ro..92
T0-92
40
,,-40
0.1 '
0;'1',
,:
1.5
"'hOi'- '
30
"40 \ '
~Z
!~-::.<
:zo,
2.t)
25
I' 1"0.1 '
,16
7
T;"'
'15:
15
2,J;
"
6
15
15
15
'r
15
2;;
Ul,
,15
3
16
';1.'
I
3.5
5
't'
,!~
15
(I
,15
7.
15
0.
o
o
o
15
15
7.5
10
15'
100
100
15
15,
15
15
':;3
15
.. :' 1&;"
3,8
2.7
6.5
5
15
2
5
2
9
15 ,1.5
4,
",,151.
5,5
;f.!
10, . '·16'
15
10
Hi
8
6
'Ill,
20
il;
'6
,.: ,
:zo"is"
40
15
15,
40'
50
50
50
15':
15
15
15
,15,
SO
1!1.
15
,5
2.0
5.0
15
1.5
6,5
15
20
15
6
15
4
10
15
1.5
6.5
15
20
15
6
",}5
i ':,'
.• 4:a ...' hi., l
TO·92
25
15
15
TO-92
25
15 ,
15
MPF105
TO-92
25
MPF109
TO·92
25
6 " ',15 '" ,I
15
15
10
"2
"1'
16
,16
~:zo
~:-'
:/5'':"~,,,:',::
15..0
2
::~ .• :
'66' ,.02;'
100
10
50
25
50
10
50
50
25
25
',15100:55:is'
i i l l S .:.
100
56'
0
iI5·.
loti
563,
o
o
115
100
56
55
56
66
2!;
IS
.0
3
15
0
,3
15
0
3
' .. ,1,6
15
15
0
3
'::'r
15
2
:/,
0
is
50
15
50
15
15
50
15
15
15
75
15
15
I 0.8
68 . ,; . 10110
,16
15
15
'E,,~!3 '~:~J.;,
i5
15
24
~5
.02
15
5.5
0.5
25
3
5
15
25
55
55
o
,0
25
55
°
15
16
100
25
55
15
15
4
"5
100
25
55
::':: C.'I': <·m"~E?::·''':'
.:zoo
1.5
115
55
2
,16,
15
100
Pkg.
No.
,2
1;2;0
9
"51
115
No.
Process
0
lfu7.o..
t5
15
,HI
o
(Hz)
°
111 '7.0 ..,i2j) iI/;,
!Ii'
0'
Max
15
0
0
~aO .IS '. is
'.0
200" 1 . 5 . t 5 " S ' 0,
.' 15.4.0 '; . 1211 .
,IS,
~~)@ Freq
'15,
16
15
2
2
15
15
0,
15
o
o
o
o
o
o
15
15
.0
6.
5
6
20
::' ,~~.' :;:
111'
15,
6
15
MPF104
0.2
I}
15
6,,5
MPF103
I
15.
7
L5
0.1
, 15
"
15
0.1
4,
,7
16
100
15
'. lO;P· ,~." .)0'.,4,0211,
3
,50
15
15
18
2
15
'~
15
8
1.4" '4.2
H;;,
'
2.5
25
15,
9
40
5
0.5
·,21'
15"
15
15
.15,
15
T~
10 11
S
G.6,i.s'15
1~' 0.5
Blii
0.2
1'10;1
'0.&
,9,
··Il)
1,8
2A'
'~5:: ;'·l:'<;: ,t ':L::~:~E:
, :.
0:1' ;"
1,
15-
"6
15
TOO2,
15
15
3
0.1
J2t,t,
6
15
0.6,
.Ii;
WO'
30
• J21,2.-
6
i5
TO-72
T0-92
2.5
"~
6.1,
en
VGS
(VI
15
'15,:,,1.3
" l'
I
15
,,'.2 ,.-3.8
0.1
IV)
Vos
(VI
4
HlO,
10
Max
(pFI @
Max
4
100' ,0.5
U
3
(VI
VGS
(VI
15
15,
(
2
Max
Crss
Ciss
(pF-l@ VOS
15
2N5556
,-?to':
IV)
Goss
(#mhol@VoS
3
;:'::i:' LH
,~
.i203, "
Max
Gfs
Immhol
@VOS
Min
Max
IV)
15"
,:;:,;;:':
:;~',.:
lOSS
(mAl
@ VOS
10
Max
I~A)
I
~
Vp
@ 'VOS
IVI
:,'2,
1,1.!;:
50
25
15
0
35
10
50
25
15
0
".2i: .'0
:z(}
" 15
0
o
:0',
15
15
a.
15
15
o
o
>1.5
.1.6
12,
10
o
o
°
n
35
,11;
, '15,
16.
.1
0
, 12', . "in' .'
12"
0
",\l"
2!;
72
3
15
3
15
o
o
:~::::~. E',1 ::
rt.ll,
,flO
tlO. ,
. tlO
11<,... ,,~: :'n
lk
90' '12,
It..' ; ,90
'" 12
1!,-.'
1lO
, '72,
55
115
1000
72
55
72
55
72
55. I 72
..." ....... '" ...
~'GENERAL
Transistor
Case
Style
Type
MPF",
MPF"2
~
U1
BVGSS
BVGOO
(VI @ IG
Min
(J,tAJ
IGSS
lOGO
(nAI @ VOG
Max
(VI
Vp
@ VOS
tV)
'0 1'00
10
0.5
10
'0
'0
I '00
10
0.5
'0
'0
:iii~12
3?
10
10
PN4222
TO·92
30
10
PN4302
TO·92
30
PN4303
TO·92
30 .
10
PN4304
TO·92
30
10
PN5163
TO·92
25
TlS58
TO·92
25
TlS59
TO·92
25
10
.'1>:.51_
I
~J.!~.
20
15
20
25
2.5.
.20
3.S.·20
10.4 . 1.2
.t:.4()·t.
20
5020
25
. 20'
4
4
20
'<0
2Q
I
2
20
10
20
4
20
20
,{l.S
. :tfL.4
}Q
'5
15
20
10
5
'5
20
15
0.4
15
0.5
8
15
15
1000
20
15
20
2.5
ea..
Style
2N3921
TD-711
TO·71
':~~H~;. PJe~~21 I~:;~~I
IV)
10
10
TO.7! 10
10
2N4082
(J~):
Max
'5
15
20
o· 1
0'1
1.2
.2
Freq
(Hzl
o .1.2
o~L:. ...!.2.
20
.0
'ISo· .21>
~
20
~
0
1$0
20
150
20
~L
. .!5!!.. _. ?Q
'5
o
15
0
'5
'5
15
0
40
15
'5
o
o
20
50
20
20
'5
20
0
0
100
3
20
0
3
20
0
10
20
20
50
20
20
15
20
20
50
20
20
1
1. 2.5
40
'5
15
200
15
6
25
'5
1.3
15
'5
1.3
15
;;0...11:,ro.
-,.0;, :iJ'
Of.
Go..
/.lmhos
Min
Max
tumho)
CMRR
Vgs
IdBI
IV}
Min
Min Max
Vp
lOSS
IV)
(mA)
Max
I
G"
Immho}
Max
o
o
Process
No.
Pkg.
No.
50
72
cc~t~·,
li:I:;..."1 ::
55
72
1000
52
72
100
1000
52
72
125
1000
52
72
1000
50
72
12
15
6.
15
2mA
15
2mA
50
74
15
2mA
15
2mA
50
74
3
G on
'GSS
CiSlO
Crss
BV
lJ.!mho}
(pAJ@lVOG
Max
(VI
IpF)
Max
IpF)
Max
Iv)
'n
(nV/v'HzI @I
Min
Max
700
700
5.0
5.0
25
250 1'500
250
1500
10
100 I 300
5.0
See 2N3954·6 as an Improved replacement
25
100
I 300
5.0
See 2N3954·6 as an Improved replacement
200
5.0
10
(pAl
Mu
100'
(to,
200
,,0:.1' .' a. 200
IS
·rO·71: "': 200
.20
,I t:O;1.1L220
..
<
1000
Output Admittance
~
1.0
~
500
f - FREQUENCY IMHz)
Output Admittance
1
./
V
Vos '" 15V
Vas =0
ICS)
0.1
"3
o(")
COMMON SOURCE
I- Vas =0
J
...
."
/
0.01
1000
100
200
1\
500
f ~ FREQUENCY IMHz)
f - FREQUENCY IMHz)
3-5
1000
,..
It)
en
en
Q)
(.)
...
c.;
0
~
Process 51 N-Channel JFET
0.021
10.533)
DESCRIPTION
0.0038
Process 51' is designed primarily for electronic
switching applications such as low ON resistance analog switching. It features excellent Ciss
ROSION) time constaM. The inherent zero offset
voltage and low leakage current make these devices .
excellent for chopper stabilized amplifiers, sample
and hold circuits, and reset switches. Low feedthrough capacitance ·also allows them to handle
video signals to 100 MHz.
GATE IS ALSO 8ACKSIDE CONTACT
CHARACTERISTIC
PARAMETER
TEST CONDITIONS
Gate-Source Breakdown
Voltage
BV GSS
VOS=OV, IG =-Ip.A
Zero Gate Voltage
Drain Current
loss
Vos = 20V, V GS = 0
Pulse Test
Reverse Gate Leakage
IGSS
V GS = -20V, Vos = 0
"ON" Resistance
ros
Vos = 100 mV, V GS = 0
Forward Transconductance
gfs
VOG = 15V, 10 =2mA
Pinch Off Voltage
VGS(OFF)
Vos = 20V, 10 = 1 nA
Drain "OFF" Current
101<;lFF)
Vos = 20V, V GS = -10V
Feedback Capacitance
Crss ,
VOG = 15V,I 0 = 5mA,f= 1 MHz
Input Capacitance
Ci5S
Vos = 15V,I o = 5 mA, f= 1 MHz
MIN
. TYP
-30
-50
5.0
20
MAX
V
65
170
mA
-15
-200
pA
35
100
n
8.5
-0.5
UNITS
-4.5
15
3.5
12
mmhos
-9.0
200
4.0
16
6_0
V
pA
pF
pF
Noise Voltage
en
VOG = 15V, 10 = 1 mA,f= IOQHz
Turn·On Time
ton
Voo = 10V, io = 6_6 mA
12
20
ns
Turn·Off Time
totl
Voo = 10V, 10 = 6.6 mA
40
80
ns
nV/v'Hz
This process is available in the following device
types. *Denotes preferred parts.
TO-IS (CASE 02)
2N3970
2N3971
2N3972
*2N4091
*2N4092
'2N4093
*2N4391
*2N4392
*2N4393
f2N4856
2N4856A
*2N4857
2N4857A
*2N4858
2N4858A
2N4859
2N4859A
2N4860
2N4860A
2N4861
2N4861A
TO-72 (CASE 25)
*NF5101
*NF5102
*NF5103
TO-92 (CASE 72)
*2N5638
*2N5639
*2N5640
2N5653
2N5654
• JIll
*J112
*J113
'PF5101
*PF5102
'PF5103
*PN4091 .
*PN4092
'PN4093
"PN4391
*PN4392
*PN4393
*PN4856
*PN4857
*PN4858
*PN4859
*PN4860
'PN4861
U1897E
U1898EU1899E
TO-92 (CASE 74)
BF246A
BF246B
BF246C
3-6
TO-92 (CASE 77)
BF247A
BF247B
BF247C
TIS73
TIS74
TIS75
QUALIFIED PER MIL-S-l9500
2N4091 JAN, JANTX, JANTXV
2N4092 JAN, JANTX, JANTXV
2N4093 JAN, JANTX, JANTXV
2N4856 JAN, JANTX, JANTXV
2N4857 JAN, JANTX JANTXV
2N4858 JAN, JANTX, JANTXV
2N4859 JAN, JANTX, JANTXV
2N4860 JAN, JANTX: JANTXV
2N4861 JAN, JANTX, JANTXV
"'C
a
Process 51
(')
CD
Transfer Characteristics
Transfer Characteristics
1
~
~
"
~.§.
g
,
'os
50
50
B~
2
22
ii
~~
0,
,.
~
~
z
~,
E~
.E
U1
...A.
100
100
j:-;
:i-e
12
CJ)
CJ)
Common Drain-Source
Characteristics
Parameter Interactions
~
".!!
Z
2
Q
20
I-+ttI+---;>'F++Pkt+H "
10
10
Z
B.D
~
~
~
2
~m: ~.E,
6.D
4.D
2.0
j'"
-0.5
VGS -GATE·SOURCE VOLTAGE (V!
-1.0
Transfer Characteristics
3D
-2
-1
-1,5
-10
-5
6.4
VGSIOFFI - GATE CUTOFF VOLTAGE (V)
Vas - GATE·SOURCE VOLTAGE (V)
.00
7
~
l;;
E
.!!
~
!.
20 ~~~~~~~~~d
I
,
10
-0.5
-3.0
-2.0
VGS - GATE'SOURCE VOLTAGE (V)
Vas - GATE·SOURCE VOLTAGE (V)
Transconductance ys Drain
Current
~
I
~ lOeil!U,1
:!
;,
VGSIOFFI= 1.4V
~
~
"
VGS(OFFI = -3V
'/
D.l
'0 - DRAIN CURRENT (mAl
D.l L...JOLLoLJ.1lJ.......u.J..WJII-.J....I.I.J.J'WI
1D
0.01
D.'
1·0
50
2.0 r-H--+--t:7!''+-r+~
I.D '-=::....L-L--L.--L.--L.'-L..L..I
o
100
0.01
0.6
0.8
1.0
~
TA "'+125"C
~
~,
I.D.l1-'j'j"'
1D
C.lVes =0)
C. IV[)5= 20)-
J
'OIOFFI
J
'--Ic·rrttri
TA _+25 C
D
-I""
B.D
10
"
1.0
-4.0
J2
24
-80
-12
-16
-20
VGS - GATE·SoURCE VOLTAGE (pF)
VaG IVosl- DRAIN·GATE (SOURCE) VOLTAGE (V)
Noise Voltage vs Current
0.4
Capacitance vs Voltage
O.2mA
J
0.2
IVGSIVGSCOFFII- NORMALIZED GATE·
TO·SOURCE VOLTAGE (V)
'.D
.i
10 -DRAIN CURRENT (mAl
Noise Voltage vs
Frequency
20
5.D
10
'00
10
j
I
1111
10
.00
D.'
III
~
5.0
20
leakage Current vs
Voltage
.00
2
:;
2.0
E'=~'2=;:':=;'EEEl3I
50 r-~~~-r-+-r~~
10 - DRAIN CURRENT (mAl
Output Conductance vs
Drain Current
I
§
L-ILWII...L1illlL--L...L.LJ1..l.WJ
1.0
-1.5
-1
2.0
~ ~~~~~~~~~~~
~
~ 10 r--r~~~~~r+--~
~.
-1.0
1.6
:::
VGSIOFFI
TVP"'-7.0V
&
1.2
Normalized Drain
Resistance vs Bias
Voltage
Resistance vs Drain
Current
Transfer Characteristics
,--r--,---,-...,...--,---,-,
0.9
Ves - ORAIN·SOURCE VOLTAGE (V)
Turn-On Switching
Turn-Off Switching
25 r-'-r-~~~------,
]:
~
,.-=-
Voo=3.0V
t, APPROX.lo INDEPENDENT
VGSIOFFI--12V
TA = 25°C
100
~
20
"~
15
r-r-~~-+-+-r4-+~
5.0
r-t--H""'I2'ioo;;;:!-->f<.+-+-i
9
".
I.D
LJ.1illWLLlllJJllL...L
0.01
D.l
I.D
D~~-L~~-L~~
10
I-FREQUENCY 1kHz)
"D
o
ID - DRAIN CURRENT (rnA)
-2.0
-4.0
-6.0
-8.0
-10
VGSIOFFI - GATE-5oURCE CUTOFF VOLTAGE (VI
3-7
=
2
~
~
.
~
"•
]
~
:i
"
60
"
2D
D
D
2.D
4.D
6.D
B.D
'0 - DRAIN CURRENT (mA)
1D
Process 52 N-Channel JFET
DESCRIPTION
0.017
1 - - - - - (0.43Z)---""--;Oooj
Process 5i is designed primarily for low level audio and
general purpose applications. These devices 'provide
excellent performance as input stages for piezo electric
transducers or other high impedance signal sources.
Their high output impedance and high voltage breakdown lend them to high gain audio and video amplifier
applications. Source and drain are interchangeable.
0.0038
GATE IS ALSO 8ACKSIDE CONTACT
CHARACTERISTIC
Gate-Source Breakdown
CONDITIONS
PARAMETER
BVGSS
Vas = OV, IG=-1!lA
MIN
TYP
-40
-70
MAX
UNITS
V
Voltage
Drain Saturation Current
lOSS
Vas = 20V, VGS = OV
0.2
1.5
12
rnA
Forward Transconductance
9fs
Vas = 20V, VGS = OV
1.0
2.5
5.0
mmhci
Forward Transconductance
9fs
Vas = 20V, 10 = 2OO!lA
IGSS
VGS = -30V, Vas =
ov
ros
Vas = 100 mY, VGS
= OV
Reverse Gate Leakage Current
Orain ON Resistance
Gate Cutoff Voltage
VGS(OFF),Vp
VOS= 15V, 10= 1 nA
Output Conductance
90S
VaG = 15V, 10 = 2OO!lA
700
!lmho
-10
250
-0.3
400
1.0
pA
2000
-8.0
2.0
Feedback Capacitance
Crss
VaG = 15V, VGS = OV, f = 1 MHz
1.3
1.8
Ciss
VaG = 15V, VGS = OV, f = 1 MHz
5
6
Noise Voltage
en
VaG = 15V, 10 = 200 !lA, f = 100 Hz
10
TO-1S (CASE 02)
TO-72 (CASE 25)
TO-92 (CASE 72)
2N3069
2N3070
2N3071
2N3368
2N3369
2N3370
2N3458
2N3459
2N3460
*2N4338
*2N4339
*2N4340
*2N4341
*2N3684
*2N3685
*2N3686
*2N3687
2N3967
2N3967A
2N3968
2N3968A
2N3969
2N3969A
* J201
* J202
*J203
*PN3684
*PN3685
*PN3686
*PN3687
*PN4302
'PN4303
*PN4304
3-8
V
!lmho
I nput Capacitance
This process is available in the following device, types.
*Denotes preferred parts.
n
pF
pF
nV/..;Hi.
Process 52
...
"tJ
o
(')
(1)
Transfer Characteristics
TYPVGS(OFF)' -1.BV
TA' 25"C
VGS(OFF)' -2.BV
H r l - - t - - j , / T A = -55"C
TA·· 25"C'
It--->,f_g,,--""+: TA'·
I
10 ~1-+-+-+-+--t-++-+-;
""~'-T-+-VGS(OFF)' -1.8V
I TA'-55"C
1\--4~4<==-+:TA ~ 25"C'
TA ~
I I
/
I
VGS' -0.25V
1//'
moe
VGS' -0.5V
VGS· -0.75V
h~
VGS - -1V
VGS - -"25V
~
-1
-2
-1
-3
-2
-3
-4
-5
VGS - GATE·SOURCE VOLTAGE (V)
VGS - GATE·SOURCE VOLTAGE (V)
Transfer Characteristics
en
I\)
vL.L
r-
m"e
I
en
en
Common Drain-Source
Characteristics
Transfer Characteristics
VOS - DRAIN-SOURCE VOLTAGE (V)
Parameter Interactions
Transfer Characteristics
10
ros-
.,
0.5
~
Ifrot
C>
i
O.Z
I
0.1
0.1
-3
Output Conductance vs Drain
Current
Transconductance vs Drain
Current
TA'25"C
f= 1 kHz
50
5V
'"
"8
C>
.,w
""t;
iiia:
15
5V
10
VGS(OFF) ·-3 .7V~
,;.on
./
VGS(OFF)' -2V
";;:g;
I
15V
20V
I
"'"
1 ./
10V
15V
10\~
I-
~
I=<
0.1
10
10 - ORAIN CURRENT (mA)
.."
V
0.01
V
V GS(O FF) = -2V
/'
200
I I
VDS::: 100 mV
VGS = OV
100
-75
10
0.1
-25
Z5
75
125
Capacitance vs Voltage
10
TA=25"C
VOS= 15V'
"'"
I-
~
10
:3
.,.
I
C>
"I
c;.,~
of
0.1
i=
f ' 1MH
-.,
w
0.01
175
TA - AMBIENT TEMPERATURE ("C)
Leakage Current vs Voltage
oS
w
!:;
C>
>
w
!2
V
/'
10 - DRAIN CURRENT (mA)
Noise Voltage vs Frequency
10
V
i:'
100
~~
VGS(OFF) = -1.5V
500
~
VGS(OFF) = -"6V"!'
0.1
2
lk
VOS - 15V
TA' 25"C
f= 1 kHz
w
"~
0.5
Channel Resistance vs
Temperature
10
100
O.Z
VGS(OFF) - GATE CUTOFF VOLTAGE (V)
VGS - GATE·SOURCE VOLTAGE (V)
VGS - GATE·SOURCE VOLTAGE (V)
I.,
. 1
10
f - FREQUENCY (kH')
;;;
0.1
""
~
~
-2
l>
O.Z
Q
lOSS. 9fs@Vos::: 15V
VGS:::OPULSEO
ros@1mA.VGS"'O
VGS(OFFI @VDS::: 15V
ID==1 nA
l-
-1
I
~
'n ....-1r
"
co
~
r--
;:::
C;~ (V~s ~ 15~)
n-t
'{.:::tof'
.11
-2
100
VOG - ORAIN·GATE VOLTAGE (V)
3-9
-4
-
OV)
Cm (VOS = 5Vr
-6
-B
-10
VGS - GATE-SOURCE VOLTAGE (V)
~
l>
~
2:
('I)
it)
Process 53 N-Channel JFET
~
..
U)
U)
CI)
CJ
0
Q.
DESCRIPTION
0.D03
Process 53 is designed primarily for low current
DC and audio applications. These devices provide
excellent performance as input stages for sub pi co·
amp instrumentation or any high impedance signal
sources.
GATE IS BACKSIDE CONTACT
CHARACTERISTIC.
PARAMETER
TEST CONDITIONS
Gate·Source Breakdown
Voltage
BVos~
Vos = OV, 10 = -lp.A
Zero Gate Voltage
Drain Current
loss
Vos = 10V, Vos = 0
Forward Trans·
conductance
9fs
Vos = 10V, Vos = 0
Forward Trans·
conductance
gfs
Voo = 15V, 10 = 50p.A
Reverse Gate Leakage
loss
Vos =.-20V, Vos
MIN
TYP
'-40
MAX
UNITS
-60
0.02
V
0.25
80
1.0
250
mA
350
p.mho
p.mho '
120
=: 0
-10
-0.3
Pinch Off Voltage
VOS(OFF)
Vos= 10V, 10 = 1 nA
Feedback Capacitance
Crss
Voo = 15V, Vos = 0, f = 1 MHz
~2.2
-0.5
pA
V
-6.0
0.85
pF
1.0
Input Capacitance
Ciss
Vos = 15V, Vos ~O, f= 1 MHz
2.0
2.5
pF
Output Conductance
gas
Voo = 10V, 10 = 50 p.A
0.9
5.0
p.mhos
Noise Voltage
en
Voo = 10V, 10 = 50p.A,
45
150
nV/y'Hz
f=100Hz
Leakage Current vs
Voltago
Parameter Interactions
This process is available in
the following device types.
* Denotes preferred parts.
TO-72 (CASE 25)
2N4117
*2N4117A
2N4118
*2N4118A
2N4119
*2N4119A
100
1000
_1
loss
500
50
""'
-"'"
1- 20
"'I:;
""
"'",
100
z'"
50
"'.,
~~
:;:~
.,,,,
"'''
II-
.
~ I
-
~
~~
5.0
Bh.loss@Vos-l0V, VGS - 0
roo @)V~ '"100 mY. Vas" 0
VG:illOFFI Ii Vos '" 10V,ID '" 1.DnA
10
-0,1
-0,5 -1.0
-5,0 -10
V.SIDFFI - GATE CUTOFF VOLTAGE (VI
3-10
I
-loss
13'"
'"
d
"1
'"
"'"
§"
10
~
"'
.,"~
1,0
I-
100
;'
2
10 ·30 DR 100"A
.!>
'ill
!i:
"z
10
'os
.. 1000
~
5I
1,0
j'
,j
0,1
5,0
10
15
20
VDG - DRAIN,GATE VOLTAGE (V)
25
Process 53
"0
a
(')
(I)
Transfer Characteristics
100
C
90
80
-~
....
10
:5
60
~
SO
~
40
30
I
.P
20
10
ffi
ffi
oS
....
....
~_
~
..
"o:c~
VaslOFFI '" -0.15V
~V
,~ v.~
-0.2
c
.. ISO
~
.....
~ 200
~: :~:~~C_ ,.-
I
IS!' =-SS'C- : -
""~
-0.4
-0.6
-0.8
.P
.
-0.2
~ 2S0
3
HH--+++++-+-H
.. 200
1-t""1.+:;!"-
~
-0.6
-I
-1.4
s
..
2S0
~
200
"
~
...
~
·3
"
150
200 ~ts::;
c
100
o:c
....
I
¥
r--.. /"
~ ~k?'
l5z
..~
1-'N'l"'ooA-""'"",
l!:
-0.6
-O.B
-I
0.4
::!
60
j
TVP VasloFFI ,. -a.8V
TA =+25 C
20
.'"
....
..
t=..
..
..e
VGS e -D.2V
VGS = -O.JV
Z.O
J.O
co
EF.,~
EI~~~
1.0
~~,
-1.0
5.0
'rr
0.1
w
§
I V
20V
."
I
:4
C. (V DS = 10V) t:::: t::::
J. (Jos = 10V)
1.0
O.S
.:!
t - - TA = 25°C
f= 1.0 kHz
0.1
1.0
0.1
0.01
S.O
"c
....
~.
[7i'- . l'Y
I
4.0
.
.VDQ:'5.UV
-1.0
10 - DRAIN CURRENT (rnA)
TransconductancB
vs Drain Current
Uk
SOD ==YGSlOFFI - -l.6V
~:;
-VGSIOFF ,. -1.8V
"~
SOD
VDO = lOV
BW= 6.0 HZ@f=IOHz.IOOHz
=O.2i@f;'I.OkHz
.5 200
w
'"~
100
I I
100
co
co
>
SO
!!!co
co:c
VOG
=10V
rn1
I
.Ii
I
of
z
10
0.01
0.1
1
10 = lo.A
SO
z
20
l:err[
10
0.01 0.03 0.1
1.0
10 - DRAIN CURRENT (rnA)
0.51.0 2.0
...
10
f - FREQUENCY (kHz)
3-11
-8.0
-12
-16
VGS - GATE·SOURCE VOLTAGE (V)
Noise Voltage vs
Frequency
Uk
~
....
-3.0
f-0.1-1.0MHz
~
v.. - ORAIN-SOURCE VOLTAGE (V)
1....
...e
J
-z.O
.10
....
Ji
1.0
,
t\
Capacitance vs Voltage
10
co
Vos = -D.4V
V•• ' -D.S
~
VGS - GATE·SOURCE VOLTAGE IV)
E
I I I
I
-1.0
3
~GsLoL I-
V
po;;
Output Conductance
Vos=-O.IV
40
1.6
vs Drain Current
Q
80
1.2
VG;- GATEoSOURCE VOLTAGE (V)
100
C
O.B
~VGSlOFFI = -I.BV
1\
~
di
-11.4
KT
V..-r TA, = +I,2S'C,
TA = -S5°C
~TA=+2S'C
N2:5!\TA = +12S'C
~v
I
Common DrainaSource
Characteristics
.P
JOO
t;
100
-1.0
VGSIOFFI = l.6V
TA '" -55°C
A "'+25°C
Vos '" 10V
S
C
c
-3.0
Transfer Characteristics
400
co
~l!!""~~~-+~
-z.O .
-1.0
VGS - GATE·SOURCE VOLTAGE (V)
Iri"<+-+-+/
Vos - GATEoSOURCE VOLTAGE (V)
~
0.2
r-r-.--r-.--,.....,,.....,.....,-,
~
3
eE
I""OI::-+-..p.r<+-
-11.2
z
I-"Id-'I.-'k-j-t-+-+--t--1
-I.B
.Ii
......
~
...
OA
en
w
.P
JOO . .
I
3
t.--'t--If-±==l
Transfer Characteristics
.-r-r-r-.--r-.--.--,.....,.....,
.. ISO
co
~ 100
0.6
VGS - GATE·SOURCE VOLTAGE (V)
Transfer Characteristics
..~
I
SO I-NIiI--l"~-+-+-t---"I-H
-I
300
.
.--r-...,.-,.--r-...,.-.-..---,
";;:o:c
100
Vos - GATEoSOURCE VOLTAGE (V)
s
O.B
VOSIOFFI=-lV
TA' -S5·C
TA = 2S'C
TA -12S·C
... ~;
... 1"41
I'
3
t/)
t/)
Transfer Characteristics
Transfer Characteristics
SO 100
-20
U')
U')
Process 55 N-Channel JFET
U)
U)
Q)
u
e
DESCRIPTION
0.
Process 55 is a general purpose low level audio
amplifier and switching transistor. Wafer process·
ing is similar to process 52 but process 55 uses a
larger geometry. This results in,higher Y Is , loss,
and capacitance and lower ROS(ON). It is useful
for audio and video frequency amplifiers and RF
amplifiers under 50 MHz. It may also be used for
analog switching applications.
GATE IS BACKSIDE CDNTACT
CHARACTERISTIC
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Gate·Source Breakdown
Voltage
BV GSS
Vos = OV, IG =-lj1A
Zero Gate Voltage
Drain Current
loss
Vos
= 20V, VGS = 0
0.5
5.0
20
mA
Forward Trans·
conductance·
gfs
Vos = 20V, VGS = 0
2.0
4.5
7.0
mmho
Forward Trans·
conductance
gfs
VOG = 15V, 10 = 200j1A
Reverse Gate Leakage
IGSS
VGS =-30V, Vos =0
"ON" Resistance
-40
-70
V
1200
-10
-100
pA
250
600
n
-2.0
-8.0
V
pF
ros
Vos = 100 mV, VGS =0'
Pinch Off Voltage
VGS(OFF)
Vos = 20V, 10 ,= 1 nA
Feedback Capacitance
Crss
VOG = 15V, VGS =O,f= 1 MHz
1.5
2.0
Input Capacitance
Ciss
Vos = 15V, V GS = 0, f = 1 MHz
6.0
7.0
Output Conductance
gos
VOG = 15V, 10 = 200j1A
2
Noise Voltage
en
VOG = 15V, 10 = 200pA, f= 100 Hz
10
'
This process is available in the following device
types. * Denotes preferred parts.
TO·18 (CASE 021
2N3436
2N3437
2N3438
*2N5361
*2N5362
*2N5363
*2N5364
TO·72 (CASE 251
TO·92 (CASE 721
2N3821
2N3822
2N3824
2N4220
2N4220A
2N4221
2N4221A
2N4222
2N4222A
*2N5358
*2N5359
*2N5360.
*2N5457
*2N5458
*2N5459
MPF103
MPF104
MPF105
MPF108
MPF109
MPFl12
PN4220
PN4221
PN4222
3·12
140
j1mhos
--0.5
pF
pmhos
nV/y'Hz
.Process 55
"0
a
(')
10
1
16
TA
~
J
G,U25V--
II ".
Vas = -o.sv
V .....
:§
I
VGS = -0.75V-
hV
It
.E
-2
-3
-1
VGS - GATE·SOURCE VOLTAGE {VI
-2
-3
-4
VGs:::t -1.25V
VOS - DRAIN·SDURCE VDLTAGE (VI
Parameter Interaction
Transfer Characteristics
roo@lo=O.SmA, VGS = OV
VGSIOFFI@Vos=15V,10 = 1 nA
u
Z
~
./
"~"
~I
-
-'
".
;Ii
I
iii
Transconductance vs Drain
Current
5V
TA • 25"C
1-1 kHz
~DG = ~V
VGS~FFI '-3.7V
Wv
~
r-V
~~:~~~II~ill
,=
Vos = 15V
TA =25"C
1 kHz
i
~
iii
0:
~or
..'"
-I100
I
.ll
I
10
0.1
Vos::l100m,vGS = DV
10
-75
-25
10 - DRAIN CURRENT (mAl
25
75
125
175
TA - AMBIENT TEMPERATURE ("CI
Leakage Current vs Voltage
Capacitance vs Voltage
10
''''1 MHz
...
"-
u
'"
w
co
~
;:;
10
10=100.A
!<
co
10"'1 mA
II
I
III~I
10
I - FREQUENCY (kHz!
J
TA = 25"C
~
100
-
j
j
III
1~L-L-L-L-L-~~~~
o
, 10
20
30
40
V.. - DRAIN·GATE VDLTAGE (VI
3-13
50
l"-
I'-. t-...
I
10
I'
\
5
...
>
0.1
~I--< 'J;~ - f .. I--:: ~~o••,=~·
0:
T A = 25"C
Vos =15V
1
0.01
~ --::15-
- f - ~~S\Off'-.. .-'J,.. '&\J"""",
;;:
Noise Vollage vs
Frequency
.'
-10
-5
1"
10
~
:s
..'"
1.:
10 - DRAIN CURRENT {mAl
10D
0.1
lk
S
I;;
10V
15V
" " VaSIOFP) '" -1.6V
~
_,I
Channel Resistance vs
Temperature
1'51t
20V
~
./
10
"
VGS'IOFF) - GATE' CUTOFF VOLTAGE (V)
VG, - GATE·SOURCE VOLTAGE (VI
Output Conductance vs
Drain Current
~
i
g.
-2
VGS - GATE·SOURCE VOLTAGE {VI
1
o
CiSI (Vos = 15V)
r- ~LtL
crll (Vos" 1SV)
-2
-4
-6
-8
go
,.~
111_
E
"
ill
"zI
10
g., loss@Vo,=15V. VGS - OV \~
J...
~
c--
VGs--IVI r--
-5
VGS - GATE-SDURCE VDLTAGE (VI
Transfer Characteristics
en
en
I
=25"~ - - ~GS ~oJ- f - -
12
z
;;:
-1
t/)
t/)
TYP VGSIOFFI = -1.8V
I++-+-++~
ffi
~
CD
Common Drain-Source
Characteristics
Transfer Characteristics
Transfer Characteristics
-10
VGS - GATE-SDURCE VDLTAGE (VI
~
~
co
It)
Process 58 N-Channel JFET
tn
tn
G)
(J
...o
DESCRIPTION'
Q.
Process 58 was developed for analog or digital
switching applications where very low rOSION) is
mandatory. Switching times are very fast and
ROSION) Ci •• time constant is low. The 6n typical
on resistance is very useful in precision multiplex
systems where switch resistance must be held to an
absolute minimum. With ros increasing only
0.7%/oC, accuracy is retained over a wide temperature excursion.
~----------I:~:I-'----------~
GATE IS BACKSIDE CDNTACT
CHARACTERISTIC
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Gate-Source Breakdown
Voltage
BV GSS
Vos ;OV, IG ;-lIJ.A
-25
-30
Zero Gate Voltage
Drain Current
loss
Vos ; 5V, V GS ; 0
Pulse Test
100
400
1000
mA
Reverse Gate Leakage
IGSS
V GS ; -15V, Vos =
-50
-500
pA
"ON" Resistance
ros
0
Vos = 100 mY, V GS = 0
Pinch Off Voltage
VGSIOFF)
Vos = 5V, 10 = 3 nA
Drain "OFF" Current
10IOFF)
Vos = 5V, V GS = -10V
3.0
-0.5
V
'6.0
20
-5.0
-12
0.05
n
V
20
nA
Feedback Capacitance
Crss
VOG = 15V, 10 =2mA,f= 1 MHz
12
25
,pF
Input ,Capacitance
Ciss
VOG ; 15V, 10 = 2' mA, f = 1 MHz
25
50
pF
Forward Transconductance
gfs
VOG = 10V, 10 = 2 mA
10
mmhos
Output Conductance
go.
VOG = 10V, 10 = 2 mA
, 100
IJ.nihos
Noise Voltage
en
VOG = 15V, 10 = 2 mA, f = 100 Hz
This process is available in the following device
types. *Denotes preferred parts.
TO-39 (CASE 09)
U320
U3;21
U322
TO-52 (CASE 07)
*2N5432
*2N5433
, *2N5434
TO-92 (CASE 72)
*Jl08
*Jl09
* Jll0
3-14
6.0
nV/..;Hz
Process 58
..."tJ
o
n
(I)
Common Drain·Source
Characteristics
..
.!l
100
VGs=DV.
so
~
;;:
.E
:±
""
lh IL~
20
V/ ~TA =+25°C
~IJ 1/
-I-
"z
.e!1i
1.2
1.6
i.:
l'
10
;;:
5.0
.!l
iii
0:
50
~
.
z
;;:
20
I
.E
l
10
J'
- --=
3.0
2.0
~ +125°C
;;
!1i0:
"
i.:
l'
10
;;:
5.0
i:l
z
....
3'
z
~-
...
100
~
!1i0:
50
....
N
4.0
-55°C~
+25"C
I
VGST'inr
1.0
'0 - DRAIN CURRENT ImA)
1
20
....
iii
'os
VGS
rOSb '"
O:lon~
II
VGSIOFFI
...~
'"~
:::;
10
0:
5.0
.!!
2.0
...~
:;:
Z
I
'"
./
1.0
0.1
I
j
1--.....
0.2
5.0
0.4
O.S
0.6
1.0
.E
10
5.0
1VosIVGSIOFFII- NORMALIZED GATE·
Ves - DRAIN·SOURCE VOLTAGE (V)
100
10
1.0
Leakage Current vs
Voltage
VGS(OFF) @SY, 10,l.lA
."'"
.
+lm' •
+25"C
g;
10
-5.0 -10
-0.5 -1.0
00
VG~'O':' ~ ~~W
"t;;
~
1.0
1.0
"
01
VGS =0
50
Z
~
1.0
-D.l
"z
-O.IV
-O.2V
-O.3V --DAV --D.5V
V
0:
...
Normalized Drain
Resistance vs Bias
Voltage
I
I
Vas = OV
:§
VGSIO'" - GATE CUTOFF VOLTAGE (VI
TA =+2S"C
TYP VGSIOFFI = -D.7V
30
..
100 c
~
50
....
fI
,.
:0
loss
Common Drain..source
Characteristics
40
100
:0
Ves - DRAIN-50URCE VOLTAGE (V)
..
500
~.1
co
I
2.0
1000
loss Ii! Vos • 5.0V, VGS • 0 PULSED
roo@Yos =100 mY, VGS '" 0
VGSIOFFI@Vos=5.0V,lo=3.0nA
50
0:
-5.0V - TVP VOSIOFFI = -S.OV
O.S
...
z
-4.0V
I
!rJ ~
OA
100
:§
0:
40
0:
co
I
./
'/1/
If. V
60
~
z
I ~ I~OV P'
11
....
z
II If ~.oL
en
en
"ON" Resistance vs
Drain Current
Parameter Interactions
15
20
25
VOG - DRAIN·GATE VOLTAGE (VI
To·SoURCE VOLTAGE (V)
Output Conductance vs
Drain Current
Transconductance vs
Drain Current
100
YOG = 10V
TA '" +25"C
I.!l
...
l-l.okHz
~
.
z
100
TA = _55°C ;::
TA = +25°C :;;
TA =+125°C..,
~
~
...
"'"
.~
...>
~
"z
=>
co
Noise Voltage vs
Frequency
~:;:
10
I;!
z
"....I
t----7I'~+ftttH--+TA = +25°C
foo 1.0 kHz
1.0
0.1
1.0
0.1
10
10 - DRAIN CURRENT (mA)
....
-'"
Z
f
i" ....
10
5
--
-.l
:g
!!!;::
I = lo,J\'r-.
II I
"
-12
-16
VGS - GATE-50URCE VOLTAGE (VI
-20
-2.0
-4.0
-6.0
-B.o
-10
VGSIO'" - GATE-5oURCE CUTOFF VOLTAGE (VI
3-15
I100
10
Switching Turn~On
Time vs Drain Current
~.I3o~A - f ...... f..J.. l ' r - .
4.0
2.0
-S.O
....
I, j'jmlt
1.0
0.01 0.03 0.1
0.51.02.0
1- FREnUENCY (kHz)
I
6.0
I
~Io =1.OmA
5.0
50
=>
....
"4.•
-4.0
10
VDo =1.5V
VasloFFI = -12V
TA '" +25"C
0:
o
of
'" -5.0V
1.0
S.O
'"~
=1= =C~(VDS-O)
I
1.0
10
i====
r=
L-
I I
II
'"I
10
Cs (Ves = 5.0V)
II
Switching Turn·On vs
Gate·Source Voltage.
1.0MHz
\,r--;;:::
u
"~
1=0.1
VDG '" 10V
BW= 6.0 Hz@I-loHz,looHz
-0.21@12:1.okHz
'0 - DRAIN CURRENT (mA)
Capacitance vs Voltage
100
~
C;
VGSIOFFI '" -l.GV
VGSlO '" = -3.oV
iii
1.0
~ T1VGSII~rFI
~
0:
50
]
40
TA - 25°C
Voo =1.SV
VGS!OFFJ" -12V
!!!;::
3D
~
g;
....
20
,S;
10
I,
\ I
I
I
I
I
I
L
VGSIOFFI = -8.5~_
~ 1...- VGSIO'FI - -5.5V
r-.o?"'- VGSlO'"
"
I
5.0
= -3.5V-
:-....~
10
15
20
'0 - DRAIN CURRENT (mA)
25
(W)
ex)
t/)
fI)
G)
(.)
...0
~
Process 83 N-Channel JFET
0.022
10.559)
DESCRIPTION
c.
Process 83 is a monolithic dual JFET with a diode
isolated substrate. It is intended for operational
amplifier input buffer applications. Processing
results in low input bias current and virtually un·
measureable offset current. Likewise matching characteristics are virtually independent of. operating
current and voltage, providing design flexibility.
Most GP 2N types are sorted from this family.
CHARACTERISTIC
TEST CONDITIONS
PARAMETER
MIN
TYP
MAX
UNITS
Gate·Source Breakdown
Voltage
BV GSS
Vos = OV, IG = -lilA
Zero Gate Voltage
01 ain Current
loss"
Vos = 15V, V GS = 0
0.5
2.5
8.0
mA
Forward Trans·
conductance
gfs
Vos = 15V, V GS = 0
1.0
2.5
5.0·
mmho
Pinch Off Voltage
VGS(OFF)
Vos = 15V, 10 = 1 nA
-0.5
-2.0
Gate Current
IG
VOG = 20V, 10 = 0.2 mA
Forward Trans·
cohductance
1If.
VOG = 15V, 10 = 0.2 mA
Output Conductance
gos
VOG = 15V, 10 =0.2mA
"ON" Resistance
ros
Vos = 100 mV, V GS = 0
en
VOG = 15V, 10 = 0.2 mA
f= 100 Hz
Differential Match
IVGS1·VGS21
VOG = 15V, 10 = 0.2 mA
Differential Match
dVGS1 ·2
VOG = 15V, 10 = 0.2 mA
Common Mode
Rejection
CMRR
VOG "7 15V, 10 = 0.2 mA
Feedback Capacitance
Cr.
VOG = 15V, 10 = 0.2 mA,
f = 1 MHz
1.0
1.2
pF
Input Capacitance
Cis
VOG = 15V, 10 = 0.2 mA,
f·= 1 MHz
3.4
4.0
pF
Noise Voltage
This process is available in the following device types. * Denotes preferred parts.
TO·71 (CASE 12)
2N3921
2N3922
*2N3954
*2N3954A
*2N3955
*2N3955A
*2N3956
*2N3957
*2N3958
2N4084
2N4085
2N5045
2N5046
8·Pin MiniDIP (CASE 60)
2N5047
*2N5196
*2N5197
*2N5198
*2N5199
2N5452
2N5453.
2N5454
*2N5545
*2N5546
*2N5547
U231
U232
U233
U234
U235
J410
J411
J412
8-Pin MiniDIP (CASE 67)
*NPD8301
*NPDB302
*NPDB303
3·16
-50
-70
3.0
600
V
-4.5
V
50
pA
850
1.0
Ilmhos
5.0
10
7.0
10
80
Ilmhos
n
450
50
nV/~
25
mV
50
IlV/oC
95
dB
Process 83
...
"'tJ
on
(I)
Common Drain-Source
Characteristics
Transfer Characteristics
1
i
z
~
""'-"AH':':'----;::";:---r-+-I
i
3.'
2.0
~
2
20
,
~
-0.5
-1.0
-1.5
-2.0
I-H-+-+-v~sJovl-
~8
1-t--:i>'9~--F';;-'1'.3",Vt-H--i
~<
-~~~
a
1.0
2.0
30
40
-0.1
Z., ""~i-ld"ZJo....r-"t-++-I
~
1.0
~
I-'Nlr-f-+--+-+-"1'-~rt--j
o
-0.5
-1.0'
-1.5
....2.0
-2.5
Ves - GATE·SOURCE VO~TAGE IV)
~
~,
,
16
24
J2
40
10
5
"
§,
4
1., W-.Ll-.w..u...w..u..J....LLW
0.01
'.1
1.'
I"
1.DL-UJu.wIl-UJu,wL-WJUlllU
1.,
10
0.01
0.1
10
!~! ~I CI"~IV!~ _!15~V!I'=!~!I
C,l.l lnV Gt.ll
i"-
o
-4.0
-8.0
-15
5:
""
110
!
"Ii!z
'8,
,....
>~
TIGHT
:;;6
~
~
5
I.D
0.01
0.1
1~
TIGHi-
6~
Q
T
10
~~
MED
;;<
_0
10
0.01
-20
90
1.0
10 - DRAIN CURRENT (rnA)
III
t--
l~
II
10
.
20V
1"""H-l.
III
III
80
~
001
CMRR '" 20 IDg .l.Vec
.1VGS12
0.1
Ip - DRAIN CURRENT ImAI
3-17
I
0.1
10 - DRAIN CURRENT (mAl
.l.VOG = IOV
100
a
MED
:::-5
H~
n
LOOSE
III
z
Q
10
-16
VOG .. lSV
TA .. +Z5 C
CMRR vs Drain Current
VOG "'15V
~T" +25"C TO +125"C
"'-55"CTO+25"C
LOOSE
~O'
-12
IOD
VGS - GATE·SOURCE VOLTAGE IV)
iJifferential Drift
~;!
Differential Offset
C.(Vos =15VI
1.'
10 - DRAIN CURRENT (mAl
100
<'0>
,-3
10 - DRAIN CURRENT {mAl
I=l=S:
l00~~
.J
~
0.1 Ll-lllllJJL-LlJ.llllil-WJJ.J.J.LW
10
0.01
0.1
1.0
1000
'-0.1-1.0MH,
"z
f - FREQUENCY (kHz)
100
Capacitance vs Voltage
VCG-15V
',"
BW-6.0Hzi'f:l0Hz,10DHI
"
"V
fZF zov
Ie - DRAIN CURRENT (IIA)
Noise Voltage vs Current
"O.2f~f~I.0kHz
+175
5.0
lTI'r-iT Hii
t--
-IGSS
0.1
B.O
+125
'75
~~
ov
1.0
0
'25
Transconductance
vs Drain Current
'i!
v~GI. 50V
10
100
TA -+25"C
II
-25
TA - AMBIENT TEMPERATURE rCI
.§
Voo - DRAIN·GATE VOLTAGE IVI
Noise Voltage vs Frequency
'"
~
VGS(OFF1= -J.OV
VGS(OFF1= -J.DVJ,.j.
~ li;;i;II~~
.2
o
~
0.1
-75
l'"I.DkHl
I'!
~
po
§
4.0
i;!
1--1-
0.5
~,
2
10k
Uk
~
z
Output Conductance
vs Drain Current
z
@
0.1
VGSIOFFI=-O.~
1.0
-10
-1.0
1" 1-'110-Y"'!-..t-c"'~A=r"--r--l ~ ~~~~~IIII
W
VGSIOFFI = 1.1V
VGS(OFff - GATE CUTOFF VOLTAGE (VI
Leakage Current vs
. Voltage
!
Ves "100mV
VGs"'O
50
Z ~
~ ~z
~
I
'.1
Vos - DRAIN SOURCE VOLTAGE (VI
Transfer Characteristics
5.' "'-'--"""T""T...,....,.-r--r-..,.-,
1.'
'"
5.0
0)
"
"
i!
>
r~ess
1.'
Q~
, ~litt~"'~9~V~9j
-2.5
1Ih~
Ci~
1.2V
-1.5V
1.0
~C:s::F7;~: ~~o~;;
z<
~~
" a,
!It.,loss@VDs : ISV, VGS =- 0 PULSED
ID "'I.0nA,
~z
~
VGs - GATE·SOURCE VOLTAGE (VI
1
1~
-06V
,
1--cI="--t''it-'doo+
1.0
.E
,
"
ii
4.0
3.'
Parameter Interactions
,
en
en
Channel Resistance
vs Temperature
'-'
1.0
-.:t
co
Process 84 N-Channel JFET
U)
U)
Q)
CJ
o...
DESCRIPTION
0.
Process 84 is a monolithic dual JFET with a diode
isolated substrate. It is designed for the most
critical operational amplifier input stages or elec·
trometer single ended preamp. Ideal for medical
applications and instrumentation inputs where
subpicoamp . inputs are important. Device design
considered high CMRR, subpicoampleakage over
wide input swings, low capacitance, and tight
match over wide current range ..
CHARACTERISTIC
MIN
TYP
Gate-5ource Breakdown Voltage
PARAMETER
BV Gss
Vos = OV, IG = -1 IlA
CONDITIONS
-40
-60
MAX
UNITS
Drain Saturation Current
loss
Vos = 15V, VGS = OV
20
300
1000
IlA
V
Forward Transconductance
g15
Vos = 15V, VGS ':' OV
90
180
300
IlV
Forward Transconductance
.g15
Vos = 15V, 10 =3OIlA
50
120
1'50
IlV
Gate·Cutoff Voltage
VGS(OFF)
Vos = 15V, 10 = 1 nA
0.5
2
4.5
Reverse Gate Leakage Current
IGSS
·Vos = OV, VGS = -20V
V
5
pA
Gate Leakage Current
IG
VOG = 10V, 10 = 30llA
0.5
3
pA
Feedback Capacitance
C....
Vos = 15V, VGS =O,f= lMHz
0.3
0.4
pF
2
3
pF
50
Input Capacitance
COs
Vos = 15V, VGS = 0, f=l MHz
Noise Voltage
en
Vos = 15V, 10 = 30IlA, f= 1 kHz
30
Noise Voltage
en
Vos = 15V, 10 = 301lA, f= 10 Hz
180
Vos '" 10V, 10 = 30llA
0.1
0.2
IlV
Vos = 10V, 10 = 30llA
12
25
mV
50
IlVrC
OutP~t Conductance
go,
Differential Gate-5ource Voltage
.IVGsl-VGszl
Differential Gate-Source
Voltage Drift
av GS1 - Z
Vos = 10V, 10 = 30llA
10
Common-Mode Rejection
Ratio
CMRR
Vos = 10V, 10 = 30llA
112
nV/$>
dB
This process is available in the following device types. * Denotes preferred parts.
TO-78 (CASE 24)
.2N5902
2N5903
2N5904
2N5905
*2N5906
*2N5907
*2N5908
*2N5909
Leakage Current vs
Parameter Interactions
Voltage and Drain Current
lk
lk ~~~~~~~33IEffi
h.IOSS@Vos=15V,Vos=OV
VGSlOFFI@Vos"'SV,lo=l nA
F.Et
loss
~
...
1ii
a:
TA j'25·C _
100
B
....
~
..,
~
10
TA"85°C
_ I DI " 30 f'00 pA
-
ID -30pA-=
~
TA
'
c-
25·C
)D '30"(' _
I
.!:
10 L-...J.....I..JL.W.wJ_...J...-1..J.J.LLW
0.1
10
'==
;§lID =lDOpA", 51
ID=100I-lA~
~
0.1
10
20
30
40
50
50 70
VaG - DRAIN GATE VOLTAGE (V)
VO$'O'FI - VOLTAGE GATHO.sOURCE (V)
3·18
nV/$>
Process 84
Common Drain-Source
Characteristics
Transfer Characteristics
360
~
....
ill
'"~
"~
VaS(OFFI-1.2Y
20 30 50
100
100
F
10V
VGSIOFFJ "'-1
15V 15V
1M
200
,~
10
Uill
30 50
100
200
1 rnA
10 - DRAIN CURRENT ",AI
Capacitance vs Voltage
w
w
'"
~
t-!! Hz,
'"'"
5
100 Hz
:3
1 kHz
"J
100
i 'rIii ~
:1:
I
100
1 kHz
10kHz
.1
~kHz.:;:::: 100kHz
of
O
10
U
'"
~~
~O
30
1'71
_;;~
....
N"
TIGHT
:>ffi
l-
.6.T '" 25°& to 125"&
, = -55'C to
2~0,~
;,
IIII
100
10 - DRAIN CURRENT "'AI
'"
lk
'"
110
w
"
"
8'"
I
6T l25!c to 125'C
= -55"C to 2~0,~
'"
1
10
120
50
100
10 - DRAIN CURRENT '"AI
3-19
115
"
'!' 105
~Q
II
""
0
= TIGHT
~w
125
~
J
II
MED
ID
't::
Iii~
1
I.
.... 3
0
MED
12
16
20
24
CMRR vs Drain Current
0;
:s
Voa -15V
w
=>-
r-
(V es = 15V)
VG' - GATE·SDURCE VOLTAGE {VI'
Differential Drift
"U
&RSS
o
100
30
100
Voa = 15V
I-""
I'<;
10 - DRAIN CURRENT "'AI
Differential Offset
20
0.4
0.3
0.2
0.1
10
100 kHz
1-
&In (V es " 15V)
U
I
100
10
~
10V
10
~
.,
"''''
5V
"'"
--I
- H I)
~
.",
VaslOFFI '" -2V
U
w
5S
70
5V
w
10
I - FREQUENCY (kHzl
aU
S'~
I.,
~
I
:>
10
60
~
~
100
111 0
50
Veo = 15V
I
.... w
Vea =15V
f = 1 kHz
~
'e=30,uA
10
40
- DRA'IN GATE VOLTAGE (VI
Output Conductance vs
Drai n Current
Noise Voltage vs
Current
~
w'"
vo•
10 - DRAIN CURRENT '"AI
I
""of
20 ' 30
10
,g
Vea = 15V
'"
~~
Q~
TA.= 25°&
Ik
~w
8=
"''''
I
j
:==>
10
lk
~
--
~
10
1.75
Noise Voltage vs
Frequency
~
w
....
"
Vo, - GATE-50URCE VOLTAGE IVI
:>
F
t:--
TA '25°CI>
TA = 125°C 1
300
~ 200
- '"
I',
TA = 85°&
10
lk
VGS(OFF) -&~
TA '" -55°&
500
w
~
TA =25°&
"-I
I-
'"~
Transconductance vs
Drain Current
VGSIOFF)"'2V
240
'"'"
Ves - DRAIN SDUkCE VOLTAGE (VI
360
w
u
......
100
w
0
0_ _
'"
'"'"13
""
TA =125°C
ill
1.25 1.5 1.75
Transfer Characteristics
300
2k
lk
0.2
0.25 0.5 0.75
Va, - GATE·TO·SOURCE VOLTAGE (VI
S
!....
1 rnA
il'"
I
roo- AVOG = 10-20V
I '"1-J-- "V o"
.r, b
100
95
90
= 3-10V
....
1
CMRR =20 Log
.6.Veo
AVOS1,z
85
10
,20
30
40 50 60
10 - DRAIN CURRENT ",AI
80 100
(0
co
tn
tn
. Process
86
Monolithic Dual JFET
CI)
(,)
....o
DESCRIPTION
Q.
Process 86 is a monolithic dual JFET with a diode
isolated substrate. It is intended for critical amplifier
input stages requiring low noise, sub picoamp bias
currents and high gain. Exacting process control results
in consistent parameter distribution with tight match
.and low drift.
This process is available in the following device types.
"Denotes preferred parts.
TO-78 (CASE 24)
U421
U422
U423
U424
U425
U426
PROCESS IN DEVELOPMENT
3-20
Process 88 P-Channel JFET
."
a
(')
CD
en
en
Q)
Q)
DESCRIPTION
0.021
------(0.533)-----1
Process· 88 is designed primarily for electronic
switching applications where a P channel device is
desirable. Inherent zero offset voltage, low leak·
age and low ROS(ON) Ciss time constant make this
device excellent for low level analog switching,
sample and hold circuits and chopper stabilized
amplifiers. This device is the complement to
Process 51.
GATE IS BACKSIDE CONTACT
CHARACTERISTIC
PARAMETER
TEST CONDITIONS
MIN
TYP
30
40
MAX.
Gate·Source Breakdown
Voltage
BV GSS
Vo~
Zero Gate Voltage
Drain Current
loss
Vos ;-15V, VGS;O
-5.0
-30
--90
Forward Trans·
conductance
gls
Vos ;-15V, VGS;O
4.0
13
17
Forward Trans·
conductance
gls
VOG ;-15V,1 0 ;-2 rnA
3.5
Gate Leakage
0.05
; OV, IG ; 1 p.A
IGSS
V GS ; 20V, Vos ; 0
"ON" Resistance
rOS
Vos ; -100 mV, V GS ; 0
Pinch Off Voltage
VGS(OFF)
Vos ;-15V, 10 ;-1 nA
brain "OFF" Current
10(oFF)
Vos ; -15V,
Feedback Capacitance
Crss
VOG ;-15V,1 0 =.-2 rnA, f = 1 MHz
Input Capacitance
Ciss
Vos = -15V, 10 = -2 rnA, f; 1 MHz
Output Conductance
gas
VOG ;-15V, 10 =-2mA
Noise Voltage
en
VOG = -15V, 10 = -2 rnA, f·= 100 Hz
VGS ;
50
0.5
10V
This process is available in the following device
types. *Denotes preferred parts.
TO·1S (CASE 11)
TO·72 (CASE 23)
TO·92 (CASE 74) .
2N2609
2N4382
2N5018
2N5019
*2N5114
*2N5115
*2N5116
U300
U301
U304
U305
U306
2N3382
2N3384
2N3386
2N3993
2N3993A
2N3994
2N3994A
* J174
*J175
*J176
* Jl77
* J270
*J271
TO·92 (CASE 71)
Pl086E
Pl087E
PN4343
QUALIFIED PER MIL·S·19500
*2N5114JAN, JANTX, JANTXV
*2N5115JAN, JANTX, JANTXV
*2N5116JAN, JANTX, JANTXV
3·21
80
5.0
-0.05
4.0
V
rnA
mmhos
mmhos
1.0
200
10
-10
5.0
14
15
100
300
20
UNITS
nA
n
V
nA
pF
pF
/lmhos
nV/VHz
co
co
Proc,ess 88
f/)
f/)
Q)
Common Drain..sourc.
u
Transfer Characteristics
e
Characteristics
Parameter Interactions
.
-20
100
-"g
-....••,,~
Q,;
50
loss ~
"'.,
.,U
§e
u"
~
0:2
!!!"
"'"
"U
I~
_i§:li....
0:"
C
10
•
-16
r:;: 7 ....
~ +I.BV
0:
1l
1,..0
~ -8.0,
ros 0 Vas" -100 mY. Vos .. a
VCSIOFFl@lVos = -15V,lo = -1.DpA
I I
a;
L
"~ -4.0
s.. loss @vDs =-15V, Vos = 0 PULSED
~io==
-JGs!OV
a: -12
5.0
1,..0 ....
Y
~
i/ ~
S
~s.
I
TA" 25"C
TYP VOS'DFFI ·4.5V
~ II- 1-'+Z,OV
~., ~
....
1-....
+3.0V +~V
+2.5V.
1.0
2.0
3.0
1.0
4.0
Ves - GATE-50URCE VOLTAGE (vi
2.0
5.0
-1.0 -2.0 -3,0 -4.0 -5.0
Vas - DRAIN·SOURCE VOLTAGE (VI
V.SlDFFI - GATE CUTOFF VOLTAGE (VI
Channel Resistance vs
Temperature
Leakage Current VI
Transfer Characteristics .
Voltage
1000
I
.,u
VOSIOFFI = 4.5V
.,Su
I-"'.t--t-+-= TA = -55'C
12
..
k:-+"'!!!,......;-= fA = +25"C
TA=+125"C
e
6 '.0 ....
"""-P"d?
0.5
is
I'
VOG
f~ 1.0 kH:,,,
0.1
-lI.1
-10
-1.0
"
-10
YDO
.,u
f-O.1-1.DMHz
50
1.0
0.01 0.03 O.t
-100
I I
!:
~
:3
..
I
10
c.tl= 15vk
5.0
c" (Vos " -16VI:=
g
.J
4.0
8.0
12
16
ili0:
20
10
0:
5.0
..
.~ 2.0
1.0
20
rOSb=
10pA
'os
1- Vas
"
~
c
"'"I
IIII
1.0
~VGS'OFFlII5V,
50
In
VaslOFFI
./
I- 1--"1-""
0.2
0.4
0.6
0.8
1.0
IVosIVGSlDFFlI ~ NORMALIZED GATET0-50URCE VOLTAGE (V)
V•• - GAT£'sOURCE VOLTAGE (VI'
3-22
0.51.02.0
10
f - FREQUENCY (kHz)
100
z
c
-15V
• O.2fllf;o,I.OkH.
Resistance va
Bias Voltage
100
•
aw- 6.0 H.@1=10H',100H.
J'
-15V
10 - DRAIN CURRENT (mAl
l;1
c
~=-o.2mA
lo"&·OmA
I
.~::,
I
I.
CapaCitance vs Voltage
.,.e
+115
;0
Normalized Drain
~
+125
50
.,
oS
co
ITA =+25°C
TA =+I25°C
6;!!
l-
.i
~~
OSIOFF) .. I.OV
fA" -55°C
c0:
"I
+15
100
VOSIOFFI .. 2.5Y
TA = 25°C
5.0
l:j
100
+25
Noise Voltage vs
Frequency
Drain CUrrent
!.,
-25
TA -AMBIENT TEMPERATURE rCI
Transconductance vs
_ 1000
~
f- VDSlDFFI " 2.5V
r-,
4.0 f--~"Io?1~+~~-+-l
I
~
z
i.
P
I.
~
Vas = -IOOmV
vos =0
In
ili0:
II
TA• -55"C
~-+..,..n
fA = +25"'C
""'d-""dci!'
10'-3.o~
VDo "-15V
8W' 6.0 HzliIl= 10 Hz. 100 Hz
• 0.2I1iI1;;' 1.0 kHz
1.0
0.01 0.03 0.1
0.51.02.0
10
. 1- FREQUENCY (kHz)
10 - DRAIN CURRENT (rnA)
..:
-
0.1
1lI
.e
10
r'- k r>
0.5
'"
6
z
I
£
~I
4
VI
100
I
..
5.0~ """-
Noise Voltage
Frequency
0.5
....
"
-5.0
TA -AMBIENTTEMPERA,[URE ('C)
"....cc
~
1.0
,~
w
1.0
-4.0
= t.OV ......
VOSIOFFI "".BV
VOSfOFF) ..
-75
-3~
5.0
"z
-3.0
V"" -0
VOSfOFFI
(vI'
10
.sw
H - ,...1-+-Z.O
I
~
"+25°C
Voo - DRAIN·GATE VOLTAGE
E
0.6V
0.8Vt-,I.oV- I.ZV
g;
loss
~'lo=0.1-1.0mA
VGS - GATE·SOURCE VOLTAGE (V)
~
I- r-r-
Vos = -10DmV
5.0
"
~
TA =+85°C~_~GSS
0.1
i-"'"
o.4V
10
w
'"~
o.ZV
....
Channel Resistance
Temperature
100
~
3.0
,
/'
Vas:< OV
Vos - DRAIN-SOURCE VOLTAGE (V)
Voltage
!
Z.O
I
-1.0
Leakage Current vs
1.0
TY~VosloFFI"'·8V
VOSIOFFI.- GATE CUTOFF VOLTAGE (V)
Transfer Characteristics
I
TA = Z6'C
«
.s....
10
5.0
1.0
-Z.O
a
"
~
h
a:
a:
~
;;:
g;
Common Drain-80urce
Characteristics
Parameter Interactions
Zo
50100
Process 90 N-Channel JFET
...
."
o(")
(1)
rn
en
to
DESCRIPTION
o
Process 90 is designed for VHF/UHF mixer/
amplifier and applications where Process 50 is not
adequate. Has sufficient gain and low noise, common gate configuration at 450 MHz, for. sensitive
receivers. The high transconductance and square
law characteristics insures low crossmodulation
and intermodulation distortions. Common·gate
operation simplifies circuitry. Consider Process
92 for even higher performance:
GATE IS ALSO BACKSIDE CONTACT
CHARACTERISTIC
PARAMETER
TEST CONDITIONS
MIN
TYP
-20
-30
MAX
UNITS
Gate-Source Breakdown
Voltage
BV GSS
Vos=OV, IG =-lIJ.A
Zero Gate Voltage
Drain Current
loss
Vos = 10V, V GS = 0
3
18
40
mA
Forward Transconductance
gts
Vos = 10V, V GS =0
5.5
8.0
10
mmhos
Forward Trans·
conductance
gts
Vos = 10V, 10 = 5 mA
4.5
5.8
Reverse Gate Current
IGSS
V GS = -15V, Vos = 0
"ON" Resistance
ros
Vos = 100 mV, V GS = 0
Pinch Off Voltage
V
mmhos
-5.0
-100
pA
n
90
-1.5
-3.5
-6_0
V
45
100
IJ.mhos
VGS(OFF)
Vos = 10V, 10 = 1 nA
Output Conductance
gos
VOG = 10V, 10 = 5 mA
Feedback Capacitance
Crs
VOG = 10V, 10 =!'i mA
1.0
1.2
pF
4.0
5.0
pF
Input Capacitance
Cis
VOG = 10V, 10 = 5 mA
Noise Voltage
en
VOG = 10V, 10 = 5mA,f= 100 Hz
13
Noise Figure
NF
VOG = 10V, 10 = 5 mA, f = 450 MHz
3.0
nV/yHz
.dB .
Power Gain
Gpg (CG)
VOG = 10V, 10 = 5 mA, f = 450 MHz
11
dB
This process is available in the following device types. * Denotes preferred parts.
TO-52 (CASE 07)
TO-72 (CASE 25)
TO-92 (CASE 72)
TO-92 (CASE 77)
U312
*2N5397
2(\15398
Jl14
*J210
* J211
*J212
* J300
*2N5245
*2N5246
*2N5247
Common Drain-Source
Characteristics
50
1
40
~
a:
30
....
i:l
~
Transconductance vs
Drain Current
Parameter Interactions
100
1-1-+-+--1-+-+-1
!Its,loss@Vos"'"10V, Vas'" 0 PULSED
rDS@:VDS =100mV, VGS = 0
VOSIOFFI @Vas =10V,l o =1.0nA
500
ia:1i
100
50
'20
5.0
..='"
,ll
1.0
4.8
?
I
l10MB
3.0
l.
a:
L
Vas - DRAIN-50URCE VOLTAGE (V)
S
'""'
~'"
IV
,;;:;..
f--f--+--+--+-:,J;;
10
1000
10
-0.1
-1.0
-5.0 -10
VaslOFFI -GATE CUTOFF VOLTAGE (V)
3-25
a
~
.§
"'u
'"~
i5
"
=
!;l
5.0
5°C
~TA=-55°C
TA -+2
TA, =+1 25°C
VGSIOFFI '" -2 .5V
~
1.0
P'
VOSIOFFl =
5.5V
0.5
'"
'"a:
....
Voo
z
10V
In·om'
I
iii
0.1
0.1
.1.0
ID - DRAIN CURRENT (rnA)
10
o
0)
Process 90
tn
tn
G)
(,)
e
COMMON SOURCE
a.
Leakage Current vs
Voltage
Transfer Characteristics
3'r-~~~-r-r-r-r'-,
~
30
I:
z
~
~
S.O
i
~
""".=f"'-""'<."I::t
HI,"b.
J
'DO
V
1.0
tODD
100
~
10
I11.0 / '
i.
;
.
Forward Transadmittance
10
",
= ..
.i1.
~
fR
~
-b,
I
I
100
f - fREQUENCY (kHz)
..
1
1j
!JOG "'Iav
ID"lamA
(CSI
F====
'DO
1000
f - FREQUENCY (MHz)
Forward Transadmittance
,1.!
,oa
100
f - fREQUE,.CY IMHz)
1000
t - FREQUENCY (MHz)
Output Conductance
vs Drain Current
Capacitance vs Voltage
1D
l
100
::
~~~~~~~n-4-'
VGS
0.1
;
T,It.=+2!i"C
6.0
I-
" "
15
b:-V~~"'0V-VGS(OFF)"-41fE'V
I TA "-5S·C
'.0
~,
'.0
VOG "10V
10""OmA
(CG\
~,
I
VDO - DRAIN..oATE VOLTAGE (V)
[""0.....
i8
z
J
100
I
~
"1
TA =+25·C
12~~-r~--~~~-'
"
I.D
!i,
Transfer Characteristics
10
I
VOG"'OV
10 =IDmA
(CS)
1;
~,
,;,
-j
l.!
Input Admittance
ID
1j
Vas - GATE-SDUACE VOLTAGE IV)
1.
Input Admittance
lot
~
15 H"d'~'+:::J10
!
~
1i
COMMON GATE
1g
1.0
VDG=lDV
ID "'IOmA
(CGI
0.1
IDOD
SOD
100
f - fREQUENCY (MHz)
Output Admittance
Output Admittance
ID
10
VcG =10V
i8
J
I
D.1WWW.....L....,L,--L-...L...L...L.....J
Jt"O,,-1.OMHt
-4.0
-I.D
-11
-16
VGS -GATE-50URCE VOL lAGE tVI
J
0.1
'--_J£V--,---J....J....J'-l...L.L.J
'00
10.
-20
10 - DRAIN' CURRENT (mAl
I
.......-1'b.
1.0
I}
J
.j
ID""OmA
ICGI
l!
C.iVos "S.OYI
1000
J
r---- ... xID.1)
y
K
0.1
100
. f - FREQUENCY (MHz!
Reverse Transadmittance
Reverse Transadmittanca
1
.!
VOG -10V
ID=lDmA
Its)
./
I.D
VOG "lDV
10=IOmA
(CGI
1j
~
.....Y'
I
III
-=-... r...
1
'"~
J
f - FREQUENCY (MHzl
3-26
IDOD
...
0.1
~,
-to
..D
IDDD
'DO
f - fREQUENCY (MHt)
D."
""""
100
-b
\1/
'DO
f - FREQUENCY (MKt!
.~,
~I
"DO
Process 92 N-Channel Junction Match
...
"tJ
o
(")
CD
en
en
CO
DESCRIPTION
N
Process 92 is designed for VHF/UHF amplifier,
oscillator, and mixer applications. As a common
gate amplifier, 16 dB at 100 MHz and 12 dB at
450 MHz can be realized. Worst case 75 ohm
input impedance provides ideal input match.
GATE IS ALSO BACKSIDE CONTACT
CHARACTERISTIC
TEST CONDITIONS
PARAMETER
Gate-Source Breakdown
Voltage
BV GSS
Vos =OV, IG =-1 iJ.A
Zero Gate Voltage
Drain Current
loss
Vos = 10V, V GS = 0, Pulsed
Forward Trimsconductance
gfs
Vos = 10V, V GS = 0, Pulsed
Forward Transconductance
gfs
VOG = 10V, 10 = 10 mA
Reverse Gate Current
IGSS
V GS =-15V, Vos = 0
MIN
TYP
-20
-30
10
3B
MAX
V
80
19
10
UNITS
mA
mmhos
13
18
mmhos
-15
-100
pA
35
45
80
n
-1.5
-4.0
-6.5
160
250
iJ.mhos
VOG = 10V, 10 = 10mA, f= 1 MHz
2.0
2.5
pF
VOG = 10V, 10 = 10 mA, f = 1 MHz
4.1
5.0
en
VOG = 10V, 10 = 10 mA, f = 100 Hz
6.0
nV/YHz
Noise Figure
NF
VOG = 10V, 10 = 10 mA,
f =450 MHz
3.0
dB
Power Gain
Gpg
VOG = 10V, 10 = 10 mA,
f=450 MHz
12
dB
"ON" Resistance
'ros
Vos = 100 mV, V GS = 0
Pinch Off Voltage
VGS(OFF)
Vos = 10V, 10 = 1 nA
Output Conductance
gas
VOG = 10V, 10 = 10 mA
Feedback Capacitance
Cgd
Input Capacitance
Cgs
Noise Voltage
V
pF
This process is available in the following device types. 'Denotes preferred parts.
TO-52 (CASE 07)
TO-99 (CASE 24)
TO-92 (CASE 72)
U308
'U309
'U310
U430
U431
J308
*J309
• J310
Transconductance vs
Parameter Interactions
Leakage Current vs Voltaga
Drain Current
1i 0k F~~~~~••~~
IDD
T. -25°C
w
i..
l!i
VOG '" IOV
f-lkHz
i.s
I
1.0k
w
lD 1==
ii
'"
....
~
I
of
1
~ ~~ii'rrIT=-r
~1
VaSIOFFI- GATE CUTOff VOLTAGE IV)
~100111
IVGSIOFF' • -2.8V
10 - DRAIN CURRENT (mA)
3-27
.:;
10
10
I
j
.2
1.0 0
10
5.0
15
20
25
VOQ - DRAIN·GATE VOLTAGE IV)
C\I
(J)
Process 92
tn
tn
Q)
Q.
.....
....
40
.!
ill
.!
3D
z
20
I
10
.'"
;;:
.Ii
Voo .. tOV
10 = 10mA
50
(CG)
40
ill
'"
'"
i:l
Input Admittance
Transfer Characteristics
Transfer Characteristics
U
...o
=
'"'"
".
..'"
20
.Ii
10
;;:
~
g..
3D
,.,
I
b~
"
0
-2
-1
0
-3
-2
-1
-5
-4
-3
Ves -GATE-SoURCE VOLTAGE
lies - GATE-SoURCE VOLTAGE (VI
Transfer Characteristics
-6
Transfer Characteristics
-a
i
.!
~
z"
<
g
.
-a
i
25
.!
20
"z
~
;;;
15
~z
10
I!:
<
.Ii
-2
-1
-3
Characteristics
.!
ill
'"
'"
i:l
z
..'"
;;:
I- TA '
40
30
1,
I
I
~
~
.
5
J
'-
C.. (V D•• IOVI- l - I-
~
'j(vi's -10)
"<
I
crn i
I-.
J
j
."
o
-2
-4
-6
1000
~
B /
~
20V
5
....
1
I
1.0
10
J
0\00
~
>
-8
-10
I
I II
b:,\
lo=1.0mA
~
;;
I
·Vo. - GATE-SOURCE VOLTAGE (VI
VOG '" 10V
ID ::I1DmA
(CGI
'O.21@1;'1.0kHz
I
1000
500
, - FREQUENCY (MHz)
Reverse Transadmittance
t:: VDG'loV
I
10
b...
V-
1.0
11Dv' 20V
VeTF1"I-lkt/ ·15V
~~V
(CG)
""
loV.
VeG = 5.0V
VeG "'tOV
ID '"10mA
f:: BW =6.0 Hz@I·loHz. 100 Hz
~
".;
lOV
1
~
5
I-
~
'it+- l- t- ,...
5
SOD
Output Admittance
10
Noise Voltage vs Frequency
..., "" ~ i" .'::r-±
... f;;
y.
~
100
ID - DRAIN CURRENT (mA)
100
~
1
15V
10
Capacitance vs Voltage
;:!
V
1.0
~
.!
0.1
10
~
FF
I
5.0
1.0
2.0
3.0
4.0
Ves - DRAIN·SOURCE VOLTAGE (V)
~
'1
L
~
I - FREQUENCY (MHzl
5.0
= 100
o
.,.
-6
TA =+25°C
f= 100kHz
8
5
2.0V
I/'~ -a.BV -1.2V -1.6V
~
o
-5
1000
~
-0.4V
10
-4
-3
"
v!'ov r- =;;;
20
I
.Ii
J
25°C
-2
Drain Current
t- VGSIOFFI =-2.7
-Ik,
10
Output Conductance vs
Common Drain-Source
.....
10 -1DmA
VGS - GATE-SOURCE VOLTAGE (VI
Vos - GATE·SOURCE VOLTAGE (V)
50
VaG = lOV
(CG)
~
I
-1
Forward Transadmittanca
~
<
...'"
1000
100
~
~.
~
<
500
I - FREQUENCY (MHz)
!Vi
Ir-ll~iA
I
1.0
0.01 0.03 0.1
0.5 2.0
10
I - FREQUENCY IkHzl
3-28
50 100
'1
II
0.1
100
-11
500
, -.FREOUENCY (MHzl
1000
Process 93 N-Channel JFET
0.023
1-------10.5841-----1
CD
(C
DESCRIPTION
W
Process 93 is a monolithic dual JFET with a diode
isolated substrate. It i5 intended for wide band,
low noise, single ended video amplifier input
stages, and high slew rate op amps. Monolithic
structure eliminates thermal transient errors, and
provides freedom to pick operating current and
voltage.
PARAMETER
TEST CONDITIONS
Gate·Source Breakdown
Voltage
BV GSS
Vos
~
OV, IG
Zero Gate Voltage
Drain Current
loss
Vos
~
10V, V GS
~
0, Pulsed
Forward Trans·
conductance
gfs
Vos
~
10V, V GS
~
0, Pulsed
Forward Trans·
conductance
gfs
VOG
~
10V, 10
90S
VOG
~.10V,
Output Conductance
. Pinch Off Voltage
~-1I1A
10
VGSIOFFI
Vos
~
10V, 10
~
5 mA
~
5 mA
~
"ON" Resistance
ros
Vos
~
100 mV, V GS
IG
VOG
~
10V, 10
Noise Voltage
.e n
~
~
MIN
TYP
-25
-30
3.0
18
5.0
6.0
-1.5
-3.5
50
0
10
10V, 10
~
Differential Match
IVGS1·VGS21
VOG
5 mA
Differential Match
LlV GS1 . 2
VOG "'10V, 10 ~5mA
Common Mode
Rejection
CMRR
VOG
~
10V, 10
~
5 mA
Feedback Capacitance
Crs
VOG
~
10V, 10
~
5 mA, f
Cis
VOG
~
10V, 10
~
5 mA,
40
10
mmhos
100
I1mhos
-6.0
n
pA
9.0
30
nV/y'HZ
9.0
30
mV
40
I1V / °c
15
90
dB
~
1 MHz
1.0
1.2
pF
f~
1 MHz
4.2
5.0
pF
*2N5911
*2N5912
U257
Transconductance
vs Drain Current
Parameter Interactions
...
~S
z~
Ik
100
loss
. 50
0:.
0:-
= ..
.,,'
ZZ
~e
<=
0:"
=z
....
......
10
,/
~
~.
,/
~"
<"
:!~
<0:
500
I
'OS
50
O:~
IIts,IDss@Ves-l0V,Vos=nV,PULSED
ros@lo=l mA, VGs=OV
VGSIOFFI @Vos '" 10V,Io '" 1 nA
•
.r'"
-I
-3
-5
10
.."
.
.
fll
r-- VGSIOFFI =
05
~
~
~
3V
...tR'Il1
Z
<
ci
100
"I
1
-;
'l!
SI
,."
z
"z
V GSIDFF) = -4.7V
~
,.~
Z
<
0:
~
~
Voa =10V
TA "'25 b C
f= 1 kHz
1
.ii
§
10
0.1
10
0.1
-10
10 - DRAIN CURRENT ImAI
V.stOFF} - GATE CUTOFF VOLTAGE IVI
3·29
V
100
This process is available in the following device types. * Denotes preferred parts.
05_
mA
mmhos
TO·78 (CASE 24)
;:
UNITS
V
100
5 mA
VOG ~ 10V, 10 ~ 5 mA, f ~ 100 Hz'
~
MAX
8.0
1 nA
Gate Current
Input Capacitance
o
n
tJ)
tJ)
0.0038
CHARACTERISTIC
...
"'0
C")
(7)
Process 93
UI
UI
CI,)
(,)
e
Q.
Transfer Characteristics
Common DrainoSource
Characteristics
Trander Characteristics
50
....1
~
..
....~
40
18
"...
30
i:l
20
1
5..
.§
12 ""'~~-t--+-+-+-t
;;:
..
..
~
g;
"~
;;:
l1i
CI
I
I
.E
-2
-1
!
10
.E
-3
-I
Transfer Characteristics
12.5
I
"i
"i!
.
10
~
....
~
10
~
e..
..
..:=
7.5
CI
2.5
I
k:::--hf-~""'vf:"'"
FFI-
10
...
'"coI
2.5 f----1HH--+----I1~+---1
4.0~
:;s.OV
l.K /'5J.~
-I
1.0
.~..
..
co
~~
~co
10
>'"
6.0
Iii!
-5
-4
'"of
I
T1· 25°C
1.0
I. - DRAIN CURRENT (';'AI
10
1.0
0.01 0.03 0.1
..
§
"z
·5
f
0.5
.
2.0
10
0.1
1.0
'. - DRAIN CURRENT (mAl
1= =1=
CM (V .. -IDYl
===
o
-B.O
-1&
0.1
50 100
110
'"
100
~
90
co
fi
.!!l
MID
CI
CI
'0 - DRAIN CURRENT (mAl
lU11i1
1111111
I I
I I
6Voo-1OV-15Y
H-I-I,;
-
:II!
3·30
-20
-r-. 6l'j·lji·i1;-~~
..
lH11J1
.."'"
I IIIIIIII I
LOOSE.':'
1.0
-12
CMRR vs Drain Current
BO
L
:II!
:II!
co
I
= -SSOC TO +25°C
0.1
-4.0
vo• - GATE·SOURCE VOLTAGE (VI
VDG = 10V
6T = 25°C to +125°C
10
-
J
TIGHT
1.0
f= =
C.. (V•.• I
1.0
I
-
11111
25
J
lO
:!!.
TI~,~T
1.0
c,. (V... 10VI
:5
CI
ii~
~
20
......-
Differential Drift
MED
IS
Capacitance vs Voltage
100
LOOSE
10
5.0
f - FREOUENCY (kHz)
V.. -IOV
TA' 25"C
.....
0
V.. - DRAIN·GATE VOLTAGE (VI
Vo.=I&V'111 III
OW-&.O H.@f-IoH•• IOOH.
=O.2i@f;;'I.OkH.
f= 1.0 kHz
~
TA = +Z5"C
1.0
-&
ID ~5.0mA
w
Differenti.1 Offsat
iii>
-3
~OJ~~,
10
iii
100
&0
'-I.ss~
I
10
>
20V
'1
-2
..s
:
-
ID"1.~mA
10
j
.i
~>
,/ Y
III
7 ~ i fu
5
Noisa Voltage YS Frequencv
-
0.1
l~
-'oss,=
I•• 11O!A
100
. ov
~
.....
'0mA
'y'jOmA
Vos - GATE-50URCE VOLTAGE (V)
---: '£-2.DV
,..--J Voo • 5.0V
~
-'50
Vol~age
TA "'+85°C
-3
Vas
"i!
.3
5.0
FP.:"
7.5
Output Conductance
vs Drain Current
..."':!! -E
Leakage Current vs
I
100
4.0
,.....~7.""--:=-~,......---,""'"
V.s - GATE-SOURCE VOLTAGE (V)
J!
3.0.
v.. - DRA1N·SOURCE VOLTAGE (VI
.ii
-I
CI
2-D
1.0
. -6
~
.ii
..~
..8'"
-5
GATE-50URCE VOLTAGE (VI
8
~
"i
-4
l°it__
20
CI
8
!
-3
30
Transfer Characteristics
12.5
.§
-2
v.s -
Vas - GATE·SOURCE VOLTAGE (VI
4of-+-+-+-++-+-+
:II!
10
"
CMRR 20 log
70
II
.bVoo
AVGS1 -2
60
0.1
1.0
I. - DRAIN CURRENT (mAl
10
Process 94 N-Channel JFET
"tJ
an
CD
fJ)
fJ)
I
..
1--"
10.914)
0.0038
PARAMETER
~
Process 94 is a monolithic dual JFET. It is strictly
intended for ope~ational amplifier input buffer
applications. Special processing results in extremely low input bias current and virtually
unmeasureable offset current. It is important to
note that the <5 pico ampere bias current is
measured at 35 volts. Typical CM R R is 125 dB.
Performance superior to electrometer tubes can
be readily achieved with low offset voltage and
almost zero long term drift.
10.096~-
CHARACTER ISTIC
co
DESCRIPTION
0.036
TEST CONDITIONS
TYP
MIN
MAX
UNITS
Gate-Source Breakdown
Voltage
BV GSS
VOS
Zero Gate Voltage
Drain Current
loss
VOS ~ 15V, VGS = 0
0.5
3.0
Forward Transconductance
gf.
VOS ~ 15V, VGS = 0
1.5
3.5
7.0
mmho
Forward Transconductance
gf.
VOG = 15V, 10 = 0.2 rnA
0.9
1.2
1.S
mmhos
-0.5
-2.0
-6.0
V
15
pA
~
OV, IG
~
-1 p.A
-70
-40
V
rnA
10
Pinch Off Voltage
VGSIOFF)
VOS = 15V, 10 = 1 nA
Gate Current
IG
VOG = 35V, 10 = 0.20 rnA
1.0
Feedback Cap'acitance
Cr..
0.01
Input Capacitance
Cis.
Noise Voltage
en
= 15V, VGS = 0, f = 1 MHz
VOS = 15V, VGS = 0, f = 1 MHz
VOG = 15V, 10 = 0.2 rnA, f = 10 Hz
Output Conductance
go.
VOG = 15V, 10 = 0.2 rnA
<0.1
Differential Match
IVGS1-VGS21
VOG = 15V, 10 = 0.2 rnA
5.0
25
mV
Differential Match
.c.V GSI -2
VOG
= 15V, 10 =0.2 rnA
6.0
50
p.V/"C
Common Mode
Rejection
CMRR
VOG = 15V, 10 = 0.2 rnA
VOS
This process is available in
the following device types.
* Denotes preferred parts.
TO-71 (CASE 12)
*NDF9406
*NDF9407
*NDF940S
*NDF9409
*NDF9410
.§~
ffi
/
e
~~
..,
:t~
NDF9401
NDF9402
NDF9403
NDF9404
NDF9405
10
5.0
IL
.... z
Z u
TO-78 (CASE 24)
mimi
4.0
~JDSS
1.0
0.5
",
Co:
....
_H
'", loss @VD.= 20V, vo• = 0 PULSED
VGSIOFF) @I VDS '" 20V.lo =1.0 nA
0.1
-0.1
-5.0 -10
-0.5 -1.0
V.5IO 'FI - GATE·SOURCE VOLTAGE IV)
3-31
pF
5.0
12
pF
50
nV/y'Hz
p.mhos
dB
125
Common Drain-Source
Characteristics
Parameter Interactions
1
C.!
0.02
5.0
!
5
J
40f-r-r-r-~~r-r-r-r;
.
§
3.0
il!!i
2.0
,
.E
T.=25"C
v•• '.o~
TVP V.5I."'" -2.5V:::'" _~
~
V
I_o!v
.
L-
<:;:
/l/
V
-o.9V
//
v:. ",
.. _
1.0
-UV
I
'" o iii~"~~J;t;~-;1.5EVJ;~~;t~~'1·18t~~
o
1.0
2.0
3.0
4.0
Vas - ORAIN-80URCE VOLTAGE IV)
5.0
v
en
o
Process 94
o
~
CI)
e ..
Q.
oS
5.0
Vas -
ill
'"'"
'"'"z
a
"'",
.E
~
(\
Z.O
1.0
TA = _55°C
TA '+Z&"C
TA ' +IZ.5'C
'I\~
3.0
/~
o
~C
o
-loss
rr-
s,
./ ~'155'f l
-1.0
-Z.O
-U
TA:s +25"
j
-Z.5
1.0 0
vo• - GATE·SDURCE VOLTAGE (VI
10
.;;; ~
'"
Z
40
~
EIO
1.0
8
S
~
,
I
.~.~ -1.0V
OV
1/
C>
.i
lW
15V
0.1
50
0.1
1.0
10
I. - DRAIN CURRENT (mAt
Voo - DRAIN·GATE VOLTAGE (VI
Transconductance vs
Drain Current
Transfer Characteristics
"'-3 .OV
Voo' 5.0V
'"~
-1.0='
30
VGS(OFFI
w
~ ~~~·.J.l~
ZO
f· 1.0kH,
i
10 "0.1-1.0mA
k-ioss To~I-1.0mA
10
j
~I
-0.5
10
a
TA = +85"
V
Output Conductance vs
Drain Current
10k
TA = +t25"C
VostoFFI = "':'.DV
TA " +125"C
TA =+2S"C
~
.~ V
~
zov
v!"O~f) ! -Z!5V r-
1\1\
4.0
I-
Leakage Current vs
Voltage
Transfer Characteristics
(.)
Capacitance vs
Voltage
10
1
!
~
~
_
~
~
;i!!
,
I-
ia
I--''k''f--r--t--~:s~o~;~o~ -Z.5V
4.0
3.0
TA =+25"C
I-"",:::'-~-+-TA =+125"C
5.0
.So
w
'"
'"
Z
~
!I.::-+--'~'F-''k-+ VdS(O;FI.';
-1.0V
TA ' -55'C
2.0 ~d-""k:::B!...,..,f--''CFTA'+Z5'C
·TA =+125"C
§~z
1
0.5 . 0 M . I I I I
,
;Ii
-0.5
vo• -
-1.0
-1.5
-2.0
0.1 L......u.LUJJ.l1-....L-LLLWlL---'-..........:uJJ
1.0
0.01
0.1
10
-Z.5
GATE·SOURCE VOLTAGE (VI
~50
LU.
'"~
10
5.0
of
2.0
"z,
0.1
o
-4.0
i
\
f D.l l-l iOMr'
-B.O
-12
-16
-ZO
Vo• - GATE·SDURCE VOLTAGE (VI
Noise Voltage vs
Current
Differential Offset
100
VaG "15V
::tS
t;.!
BW' 6.0 H,@f'10H,.100H,
0.2f II! f;' 1.0 kH,
I
20
g
"'
~
0.5
10 - DRAIN CURRENT (mAl
Noise Voltage vs
Frequency
100
1.0
.
'"
-
~ c. (Vas I. 011
l-
i;
I-
;Ii
~
"
§,
4
;i!!
1.0 1-t-'lW---+-+-+--N~++--I
5- f- c. (Vas' 15Vi ±
r- -I. Co. (Vo.1
5.0
'"
w
w"'
LOOSE
"''''
w"
10 = 0.03 rnA
10 0.2 mA
lo=1.0mA
=
I
~
Voo '" 15V
TA'25'C
50
tt!::
Ei~
'"'
...>g
e'"'"
MED
10
TlGHT-
5.0
'''''
~~
;''''
1.0
0.01 0.03 0.1
I
1.0
0.5 1 2.0
10
50 100
f - FREQUENCY (kH,1
I. - DRAIN CURRENT (mAl
10 - DRAIN CURRENT (mAl
CMRR vs Drain Current
Differential Drift
..'"......
"'-
100
w
"'"
w>
,:$
"Nt;
,-!!:..
m
VDG -15V
AT-+25'CTD+1Z5't
- -55'C TO +25'C
:s
15
..~
~~E
~3
",-,
w
""
"z
""
10
~w
MED
>ffi
~Q
TIGHT
D
3.'
I
VG"O"~~
.£
4.'
2
0"
~, I.'
.§
E
VG"O"":-~
.§
5.'
E
VGS"ov
2.'
Transconductance
Characteristics
..
. ,.
!
-0.2V
Vas - GATUOURCE VOLTAGE (VI
VGS - GATE-80URCE VOLTAGE (VI
Transconductance
Characteristics
~~pa:::~OFFl = -uv I
10
.E
MI.
-0,'
3.'
z
!, ,.
MAX,+
',2
1
a.'
i1l ,.
TA "+25'C
TA ~+125'C
I I I I I
VGSIOFF'''' -1.oV
TA "-SS"e
TA "+2S'C
TA =+12S·C
u
1l •.a~
Z
~,
Common Drain-Source
Characteristics
Transfer Characteristics
Transfer Characteristics
u
',t
ID - ORAIN CURRENT (mAl
t,O
E
1--:-
Process 96 N-Channel JFET
(')
0.037
CD
10.940)
,
O.OOla
en
en
CO
~
lo.omi --
V"#/////h~f8~
DESCRIPTION
~
/ i l 7/~.-/.
07////~~
TEST CONDITIONS
PARAMETER
0)
Process 96 is a monolithic dual JFET with a diode
isolated substrate. It is intended for wide band, low
noise, single ended video amplifier input stages.
Also ideal for matched voltage variable resistor
applications over 60 dB tracking range.
10.0965) 10.610)
CHARACTERISTIC
MIN
TYP
MAX
UNITS
Gate-Source Breakdown
Voltage
BV GSS
Vos =OV, IG =-1 jJ.A
Zero Gate Voltage
Drain Current
loss
Vos = 15V, VGS = 0
5.0
15
30
mA
Forward Transconductance
gfs
Vos = 15V, VGS = 0
9.0
18
30
mmhos
Forward Transconductance
gf.
VOG = 15V, 10 = 2mA
7.5
-55
--40
V
9.0
mmhos
Output Conductance
go.
VOG = 15V, 10 = 2 mA
15
45
Pinch Off Voltage
VGSIOFF)
Vos = 15V, 10 = 1 nA
-1.8
-3.0
"ON" Resistance
rOS
Vos = 100 mV, VGS = 0
Gate Current
IGSS
VGS =-20V, Vos = 0
-8.0
Gate Current
IG
VOG = 15V, 10 = 2 rnA
15
Noise Voltage
en
VOG = 15V, 1"0 = 2 rnA, f = 100 Hz
4.5
Feedback Capacitance
Cr.
VOG
'= 15V, 10 =2 rnA, f= 1 MHz
2.5
35
70
jJ.mhos
V
120
n
-100
pA
pA
200
10
nV/YHZ
pF
3.0
I nput Capacitance
C's
VOG = 15V, 10 = 2 rnA, f= 1 MHz
12
pF
Differential Voltage
IVGS1-VGS21
VOG = 15V, 10 = 2 rnA
8.0
25
mV
Differential Voltage
t;,.V GS
VOG = 15V, 10 = 2 mA
9.0
50
jJ.V/oC
CMRR
VOG = 15V, 10 = 2 mA
, Common Mode
Rejection
10
76
95
dB
This process is available in the following device types. "Denotes preferred parts.
TO-71 (CASE 12)
8-Pin DIP (CASE 67)
*2N5564
"2N5565
*2N5566
*NPD5564
*NPD5565
*NPD5566
Transconductance vs Drain
Current
Para(l18ter Interactions
g
...,..
I
Z
cl
'1
100 .,
III
..
1
-1
-2
!!i
~
§
=1 nA
-5
-10
Vas""FI - GATE CUTOFF VOLTAGE IV)
10
Leakage Current vs Voltage
100
lk
ros@IO=t'mA ;
VGSIOFFJ @ VOl -15V, 10
...o""CJ
-=
Veo =15V
IoS
,=T. 1=25·C
kHz
~
~B ~~~SIP~-I~o~~
w
u
""~
""fl
~~~~m~
~i== == I•• 0.2 mA
EE~I.=2.omA·
"'
....
- 10k
.... Uk F-.TA. =+85'"C
~
10
VGSIOFFI
~
"....
I
j
.;:
1
.1
1
I. - DRAIN CURRENT ImA)
3·35
-1.=0.2mA
~~~III',!~~~~"~'~2§.0~m~A
~. tOO ~
=-2.3V
~
a:
10
.2
10
1.0
~~~
/
-loss
~ ....
f=~'~26·C
o
8.D-
16
24
32
VDG - DRAIN·GATE VOLTAGE IV)
40
co
en
f/)
en
Q)
Process 96
(J
Transfer CharacteristicS
2
Common Drain-Source
Characteristics
Transfer Characteristics
10
0.
"....
15
'"~
10
"....
.§
.§
~
."='",
~
a:
~~;'::'~OF"'-15V tVas - 0
..... -rl
8.0
I
'"
.E
.E
=1:=
II
II
~ r- VasI = -O.4V
l- e- J.s ! _DI6V i
6.0
1j.
z 4.0
.g;,
I
IVosl.JI.2J.=
2.0
Vas = -a.8V
=-1.
0
1.0
0
-1.5
-1
-0.5
Vo. - GATE·SOURCE VOLTAGE (III
2.0
3.0
4.0
5.0
Vos - DRAIN·SOURCE VOLTAGE (VI
Vo. - GATE-SOURCE VOLTAGE (VI
Output Conductance vs
Transfer Characteristics
I
Drain Current
Transfer Characteristics
30
.§
u
'"
z
'"~
20
~
....
'"'",
10
a
z
a
I'"
100
I
z
10
~LZ .~
~
5.0
VGSIOFFJ -
T.- 25"C
.= 1.0 kHz
50
I--
j~~ !C-l~V
8
.,
1;
..
1l
V.SlOi"
-l.OV
i I\~V
I III
l/
1.0
0.1
V.s - GATE·SOURCE VOLTAGE (VI
5.UV:
VDG "'5.OV .
0.5
1.0
5.0
10
10 - DRAIN CURRENT (mAl
Vo• - GATE·SOURCE VOLTAGE (VI
Noise Voltage vs
Noise Voltage vs Frequency
Current
=VO• '15V
~
:s
....
'"a 10
co
'"
!:;
V-
1'1.0 kHz
.=
Ilm~I\~'
0.01
20
'"
=
10
~
5.0
=
",f-,
....
I-10kHz
1.0
'"co
>
~
_
50
!:;
a
z
,
~>
0.1
1.0
10 - DRAIN CURRENT (mAl
"'>
~~
~~
~
, ...
-u
10
~=>
'5.0
=>
"'l""f-+.J.
I I
II
0.51.02.0
r-
"'-'
co",
r-r-.
~!;;
8'"
:s
z
a
~
'""'a
.
...
jIGHT~
j6
II~
1.0
0.1
1.0
10 - DRAIN CURRENT (mAl
-4.0
..
MEOI
I
ffi
TIGHT
i~
......
10
.J
100
...
>
.... .;1
II~ED
':
'"....
~,
4
10 ·D.2mA._
u
N",
>a
50
u
'"
z
Differential Drift·
...
1.0 MHz
f·O.1
~
I - FREQUENCY (kHzl
L~bsE
....
~-'
-a
100
il
1.0
0.01 0.03 0.1
10
VDO = 15V
TA '" 2S"C
50
·D.2f@f~1.0kHz
ID'" 2.DmA
2.0
Differential Offset
100
VOG =15V
BW= 6.0 Hz @If:. 10 Hz. 100 Hz
oS
f= 10 Hz
I'" 100Hz
>
-'-
Capacitance tIs Voltage
100
100
10
CMRR YS Drain Current
110
r--
.
H~~I~ 10 _ 1 2 0 J -
·100
90
·a
z
a
80
8,
70
'"
5'"
60
'0.1
"Vo•• 5.0 -10V""""
1.0
ID - DRAIN CURRENT (mA)
10
Process 98 N-Channel JFET
."
a
(')
CD
fJ)
DESCRIPTION
Process 98 is a high gain, general purpose, monolithic
dual JFET with a diode isolated substrate. It is intended
for amplifier input stages requiring high gain, low noise
and low offset drift over temperature. Strict processing
controls result in low input bias currents and virtually
immeasurable offset currents. Matching characteristics
are essentially independent of operating current and
voltage.
This process is available in the following device types.
'Denotes preferred parts.
TO-71 (CASE 12)
2N5561
2N5562
2N5563
U401
U402
U403
U404
U405
U406
a-Pin DIP (CASE·GO)
J401
J402
J403
J404
J405·
J406
PROCESS IN DEVELOPMENT
3-37
en
CO
(X)
Process·52
~
JFETs
2N3684-87/PN3684-87 N-Channel
General Description
TO·72 2N Series
~:=;:'
"'' ' ' Los"
H
o1l5-0 liS
The 2N3684/PN3684 thru 2N3687/PN3687 series of
N·channel JFETs is characterized for general purpose
sm~1I signal amplifier applications requiring low noise
and tightly specified IDSS ranges.
{4445-49U!
~
J... o 0 0
(:::~:~~) -1 ~
Absolute Maximum Ratings
(25°C)
0100
(25401
0050
(4311-53341
(1.2701
I;J~,
1-:- ~:~-t!;j
(~,~I
~
0036-004&
0021-0041
I0914-1168JYZYiiJi'i=i'iii1
DOlO
PIN
1
2
FET
S
0
3
4
G
"'tJN
ZZ
Ww
mm
Case
OlOl
(0762)
""
--
mm
TO·92 PN Series
0175-0.115
-50 V
Gate·Drain or Gate·Source Voltage (Note 2)
Gate Current or Drain Current.
50mA
Total. Device Dissipation
(Derate 2 mWfC to 175°C)
350mW
Storage Temperature Range
-65°C to +200°C
2N Series
-65°C to +150°C
PN Series
Lead Temperature (1/16" froll) case
300°C
for 10 seconds)
Electrical Characteristics
PARAMETER
IGSS
BVGSS
~,..... ~
Breakdown
0003_00\3
'-}".
--l
SOITY"
oOIS_O on
R)ttJ~
3
01)45-0055
(Z.159_Z,41J,R
PIN
1
2
~
FET
G
S
0
oI14S_0 055
11,143-1.391)
a045-O.Q55
(1.14l-1.3'911
(25°C unless otherwise noted)
2N3684!
PN3684
MIN
MAX
VGS = -30V Vos = 0
.
2N3685!
PN3685
MIN
MAX
0.1
-0.5
I
i I5O• C
IG = -1 p.A. VOS = a
-50
Gate-Source Cutoff
Voltage
VOS= 20V, 10= 1 nA
-2
Saturation Drain Current
VOS = 20V, VGS =
Voltage
1p £""
-L . .".R
~
(DAD6-GU31
DIA HOU (TV',
CONOITIONS
Gate Reverse Current
Gate~Source
140445_-.&191
2N3686!
PN3686
MAX
MIN
0.1
-0.5
0.1
-0.5
-50
2N3687/
PN3687
MAX
MIN
-0.1
-0.5
UNITS
nA
p.A
-50
-50
V
VGSloff)
lOSS
Drain·Source ON
a
2.5
VOS = OV, VGS = 0, INote 1)
'OSlon)
Resistance
9fs
Common-Source Forward
Transconductance, (Note 3)
gas
Common-Source Output
Conductance
Crss
Common-Source Reverse
Transfer Capacitance
Ciss
Common-Source Input
Capacitance
en
Equivalent Short-Circuit
Input Spot Noise Voltage
VOS = 10V, VGS =
NF
Noise Figure
VOS = IOV, VGS = 0,
Agen = 10M, BW = 6 Hz
-5
7.5
-1
1
600
2000
3000
-3.5
3
-0.6
0.4
'2500
1.2
-{l.3
-1.2
0.1
0.5
1200
800
1500
-2
1000
2000
2400
500
rnA
n
1500
p.rnho
VOS = 20V, VGS =
a
50
25
10
5
1.2
1.2 .
1.2
1.2
4
4
4
4.
f= 20 Hz
0.15
0.15
0.15
0.15
f= 100 Hz
0.5
0.5
0.5
0.5
f= 1 kHz
pF
a
Note 1: Not JEOEC registered data.
Note 2: Due to symmetrical geometry, these units may be operated with source and drain leads interchanged.
Note 3: Pulse test duration: 2 ms.
4·3
p.V
v'Hz
dB
Process 83
~.
2N3954-55/2N3954A-55A N-Channel Monolithic Dual JFETs
General Description
TO-71
R='
'~='Qltr
The 2N3954 thru 2N3955/A series of N-channel
monolithic dual JFETs is designed for low to medium
frequency differential amplifier applications requiring
low noise, high common-mode rejection, and very
tight match.
0.11&-0.195
J..--
Absolute Maximum Ratings (25°C)
Gate-Drain or Gate-Source Voltage
-50V
Gate-to-Gate Voltage
±50V
50mA
Gate Current
250mW
To~al Device Dissipation 85°C (Each Side)
(Both Sides)
500ritw
Case Temperature
Power Derating (Each Side)
2.86 mWtC
4.3mWfC
(Both Sides)
Storage Temperature Range
-65°C to +200o C
Lead Temperature (1/16" from case
300°C
for 10 seconds)
Electrical Characteristics
0.170-0.210
•
mom
.500
PIN
FET (121
(~i~·l
1
2
3
5
6
7
S1
01
G1
S2
02
G2
(:;::~~:l ~ ~ (:~::l
.MAX
0.100
(2.5401
0.050
(1.270)
~
-
,P"2: 3 '
45"
~
•.036-0.846
,
-1°'
7+-0:1
/.:'<~_/
•.028-<1.04.
(0.9'4-1.'88IYZ'Y(0.7I1-1~191
(25°C unless otherwise noted)
.'
CONDITIONS
PARAMETER
IGSS
BVGSS
Gate Reverse Current
Gate-Source Breakdown
Voltage
Gate-Source Cutoff
VGSloffl
Voltage
Gate·Source Forward
VGSlfi
Voltage
VGS' -30V•.
VOS'O
-50
VDS' 20V.ID· 1 nA
-1.0
VOS= 20V
IG
Gate Operating Current
VOS= 20V.
10= 200~
Current
gos
Conductance
Ciss
Common-Source Input
Capacitance
C'"
Common-Source Reverse
Transfer Capacitance
Cdgo
NF
Drain-Gate Capacitance
•Common Source SPOt
Noise Figure
IIG1-IG21
Differential Gate
Current
IOSS1/10SS2
Drain Saturation Current
Ratio
IVGS1-VGS21
Differential Gate·Source
Voltage
Gate-Source Differential
AIVGS1-VGS21 Voltage Change with
Temperature
!lfs1 /9fs2
Transconductance Ratio
10=50~A
10 = 200~A
f= 200 MHz
VOS" 20V.
VGS=O
-{l.5
-4.5
-1.0
2N3955
MIN
MAX
100
-500
-50
·-4.5
-1.0
2N3955A
MIN
MAX
-100
-500
UNITS
pA
nA
-50
-4.5
-1.0
-4.5
10=200~
-{l.5
-50
250
-4.2
-4.0
-{l.4
-50
-250
-4.2
-4.0
-50
250
pA
nA
mA
5.0
0.6
5.0
0.5
5.0
0.5
5.0
3000
1000
1000
3000
1000
,1000
3000
1000
1000
3000
f= 1 kHz
.umho
35
35
35
35
4.0
4.0
4.0
4.0
1.2
1.2
1.2
1.2
1.5
1.5
1.5
1.5
f= 100Hz
0.5
0.5
0.5
0.5
dB
T= 125°C
10
10
10
10
nA
VOS-20V;VGS=0
VOS· 20V.
10 - 200~A
-4.2
-4.0
2.0
1000
1000
f= 1 MHz
VOS" 20V.
-{l.5
2.0
0.5
VOG·10V.
IS=O
VOS· 20V.
VGS·O.
RG"IOM[l
-4.2
-4.0
2.0
-50
250
TA"25'C
i= 1 kHz
Transconductance
Common-Source Output
-SO
2.0
VOS' 20V. VGS = 0
Common-Source Forward
Ills
2N3954A
MIN
MAX
100
-500
V
VOS·O.IG= 1 mA
Gate·Source Voltage
Saturation Drain
TA=12SoC
VOS' O.IG" -1 ~A
VGS
IDSS
I
2N3954
MIN
MAX
100
-500
0.95
T"" 2SoC to -5SoC
T'" 2SoC to 125°C
f .. , kHz
0.97
4-4
1.0
0.95
1.0
0.95
1.0
0.95
1.0
5.0
5.0
10.0
5.0
O.B
1.0
0.4
0.5
2.0
2.5
1.2
1.5
1.0
0.97
1.0
0.97
1.0
0.95
pF
1.0
mV
~
Process 83
2N3956-58 N-Channel Monolithic Dual
,
JFETs
General Description
TO-71
The 2N39S6 thru 2N39S8 series of N-channel monolithic
dual JFETs is designed for low to medium frequency
differential amplifier applications requiring tight match,
low noise and high common-mode rejection.
Absolute Maximum Ratings
"":: "'
0.175-0.195
PARAMETER
IG5S
BVGSS
Gate Reverse Current
Gate-Source' Breakdown
Voltage
(2S0C)
VGS = -30V. VOS = 0
Gate-Source Voltage
Vos= 20V, 10 = 50llA
VOS= 20V, 10 = 200jlA
IG.
Gate Operating Current
VOS= 20V, 10 = 200jlA
lOSS
Saturation Drain Current
VOS = 20V, VGS ='0
edgo
NF
IIG1-IG21
. 10551/10552
IVGS1-VGS21
-- -
0.036-0.046
45"
/." ...... _ /
~
0.D28-0.048
fO.914-1.168Iy,zYCO.711-1.2191
TA=150°C
2N3956
MIN
MAX
100
-500
-0.5
TA= 125°~
Common-Source Output
2N3957
MIN
MAX
100
-500
-1.0
-4.5
2.0
-4.2
-4.0
-4.2
-4.0
-4.2
-4.0
pA
-50
-250
-250
-250
nA
rni><
0.5
5.0
3000
1000
3000
1000
3000
1000
1000
pmho
35
35
35
4.0
4.0
4.0
1.2
1.2
1.2
1.5
1.5
1.5
0.5
VOS = 20V, VGS = 0
Common-Source Reverse
f= 1 MHz
Transfer Capacitance
Drain-Gate Capacitance
VOG = 10V, IS = 0
Common-Source Spot
VOS = 20V, VGS = 0,
RG = 10 Mfl
1= 100 Hz
0.5
0.5
VOS = 20V, 10 = 200 jlA
T = 125'(;
10
10
0.95
VOS = 20V, VGS = 0
Differential Gate-Source
Voltage
Transconductance Ratio
-0.5
V
-50
5.0
Capacitance
Differential Change With
nA
-50
0.5
1= 1 kHz
pA
-4.5
2.0
5.0
Common-Source Input
Saturation Drain Current
Ratio
-1.0
2.0
-0.5
UNITS
-50
-50
-4.5
2N3958
MIN
MAX
100
-500
0.5
1000
Current
(J1
(X)
(,0'2 J "\ \
1000
Noise Figure
CD
1,/,'''/
1= 200 MHz
Differential Gate Reverse
Z
~
FET (12)
51
01
Gl
52
02
G2
-0';+;'0-
1= 1 kHz
Temperature
91.1/91.2
3
5
6
7
0.100
12.540)
Common-Source Forward
Conductance
0.03D
(0.762)
MAX
--
Transconductance
Gate-Source Voltage
1(2'\
(X)
-0'+'0-
45. ~,,'{4!/
10.91.-1.I 68IYZYI0.111-1.2191
0.036-0.046
255°C
~
]>
0.028-0.048
N
_.
Z
~
~
N
Electrical Characteristics
PARAMETER
IGSS
Gate Reverse Current
2N4117 Series Only
~
,
CONOITIONS
VGS = -20V, VDS =
a
a
150a C
2N4117!
2N4117A
MIN
MAX
-10
-25
IGSS
Gate Reverse Current
2N4117 A Series Only
VGS = -20V. VDS =
BVGSS
Gate-Source Breakdown Voltage
IG = -1 /lA, VDS = 0
-40
VGS(off)
Gate-Source Cutoff Voltage
VDS = 10V, 10 = 1 nA
-0.6
Saturation Drain Current
VDS = 10V, VGS = 0
IDSS
150a C
Common-Source Forward
9fs
Transconductance
2N4118!
2N4118A
MIN
MAX
-10
-25
2N4119!
2N4119A
MIN
MAX
-10
-25
Common-Source Output
Co~ductance
UNITS
pA
nA
-1
-1
-1
pA
-2.5
-2.5
-2.5
nA
-40
-40
-1.8
-1
-3
-2
-6
0.03
0.09
0.08
0.24
0.20
0.60
70
210
80
250
100
330
f = 1 kHz
90S
V
rnA
/lmho
3
5
10
3
3
3
1.5
1.5
1.5
VDS = 10V, VGS = 0
Common-Source Input
Ciss
Capacitance
pF
f= 1 MHz
Crss
Common-Source Reverse
Transfer Capacitance
4-7
Z
(25°C unless otherwise noted)
CO
»
ra
Process 52
2N4338-41 N-ChannelJFETs
,
General Description
TO·1S 2N Series
tjr~'
.,,=~
The 2N4338 thru 2N4341 series of N·channel JFETs is
characterized for low to medium frequency' amplifier
applications. Tight selections of VGS(off). IDSS. 9fs
results in consistent characteristics in all applications.'
Absolute Maximum Ratings
Gate·Drain or Gate·Source Voltage
Gate Current
Total Device Dissipation. T A = 25°C
(Derate 2 mWtC to +175°C)
Storage Temperature Range
Maximum Operating Temperature
Lead Temperature (1/16" from case
for 10 seconds)
0,115-0.195
o0 0
(~::!:=:::~:) -f f--
~
300°C
0.Q36-0.046
CONDITIONS
I
IG=-Ip.A,VOS=O·
-50
VOS= 15V.IO=0.Ip.A
-0.3
Drain Cutoff Current
VOS= 15V
VGS= ( )
lOSS
Saturati~n
150·C
VOS= 15V. VGS= 0
0.2
Ciss
Crss
NF
600
-0.1
-0.1
-0.1
-50
UNITS
nA
p.A
-50
-1
-0.6
0.6
-1.8
-1
0.05
(-5)
-3
-2
0.05
(-5)
-6
0.07
(-10)
nA
(V)
rnA
0.5
1.5
1.2
3.6
3
9'
1800
800
2400
1300
3000
2000
4000
.umho
f = 1 kHz
VOS= O. VGS= 0
Common-Source Input
VOS' 15V, VGS = 0
5
15
30
60
2500
1700
1500
BOO
7
7
7
7
f= 1 MHz
Common-Source Reverse
n
, pF
I
Transfer Capacitance
Noise Figure
-0.1
VOS = 15V. VGS = 0
Conductance
Capacitance
2N4341
MIN
MAX
"
Transconductance
Resistance
2N4340
MIN
MAX
-0.1
0.05
(-5)
Common-Source Forward
Drain-Source ON
Y'D.71'-1l191
V
ID(off)
rd.
'<
V
-50
Gate-Source Breakdown
Voltage
Common-Source Output
D
-'I
2N4339
MIN
MAX
-0.1
BVGSS
90.
G
,V 3O,
,0/
45"
/."~~
~
0.028-0.048
2N4338
MAX
MIN
-0.1
-0.1
VGS = -30V, VOS = 0
9f.
3
(25°C unless otherwise specified)
Gate Reverse Current
Drain Current
FET
S
0,100
IGSS
Voltage
(:::::,
PIN
1
2
i2.5i01
0.050
11.270)
-65°C to +200°C
175°C
PARAMETER
Gate-Source Cutoff
'~i~Dl
MAX
ID.914-,.1681
VGS(off)
0.110-0.210
0.500
(25°C)
-50V
50mA
300mW
Electrical Characteristics
iT
.
VOS·15V. VGS= 0 .
Rgen = 1M. BW = 200 Hz
f= 1 kHz
3
3
3
1
1
1
3
1
..
4·8
dB
~
Process 51
2N4391-3/PN4391-3 N-Channel JFETs
General Description
R···'
TO-IS 2N Series
0209_02JO
The 2N4391/PN4391 thru 2N4393/PN4393 series of
N-channel JFETs is characterized by low ON resistance,
moderate capacitance and low noise. Applications
include low ON resistance, high speed switches and high
gain, low noise amplifiers.
Absolute Maximum Ratings
0175-0195
r:~~:=~~~~) ~ ~
~_m'_
~
~1~~ "'"'"
-(OD16-D3l0)A
3'<;<' ---.
~.
0085-0095
I
I~)R
..
01)45-0055
11143_13911
"tJ
(25°C unless otherwise noted)
CONDITIONS
VGS" -20V: VDS"
IG "-1
~A,
VDS"
a
I
2N Series
PN Series
150'C
a
2N4391/
PN4391
MIN
MAX
100
1
200
2N4392/
PN4392
MIN
MAX
100
1
200
2N4393/
PN4393
MIN
MAX
100
1
200
-40
-40
-40
PNSeries
VDS" 20V
VGS" -lV
100
1
200
PN Series
150'C
VGS" -12V
150°C
Gate-Source Forward Voltage
IG" 1 rnA, VDS" O. INote 21
VGSloff)
Gate-Source Cutoff Voltage
VDS" 20V, ID" 1 nA
IDSS
Saturation Drain Current
VDS" 20V, VGS" O. INote 11
VDSlonl
Drain-Source ON Voltage
VGS"O
Static Drain-Source ON Resistance
VGS"V,ID" 1 rnA
rds(on)
Drain-Source ON Resistance
VGS" V, ID"
CISS
Common-Source Input Capacitance
VDS" 20V. VGS" a
td
Turn ON Delay Time
t,
Rise Time
toff
Turn OFF Delay Time
tf
fall Time
VDS"
a
50
a
PULSE~DP
nA
1
-2
25
-5
75
1
-...<>:-
.
51
SAS~~~:G
4-12
.
51
Input Pulse
Rise time < 1 ns
Fall time < 1 ns
Pulse width = 100 ns
Repetition rate:;;: 1 MHz
Sampling Scope
Rise time = 0.4 ns
Input resistance = 10 M,o
Input capacitance = 1.5 pF
Process 83
~
2N5196-99 N-Channel Monolithic Dual JFETs
General Description
TO-7l
0.209-0.230
The 2N5196 thru 2N5199 se~ies of N-channel monolithic
dual JFETs is designed for low to medium frequency
differential amplifiers requiring low leakage and tight
match.
Absolute Maximum Ratings
pr~'
'''":·::::::'·~·:'r
L
0.175-0.195
(25°C)
Electrical Characteristics
0.DI6-D.01'
_11--
-
l~i~DI
--
0.036-0046
\/.:
.s»
MAX
PIN
1
2
3
5
6
7
FET {121
SI
Dl
Gl
S2
D2
G2
N
Z
~
CO
CO
(25°C unless otherwise noted)
CONOITIONS
MIN·
MAX
-25
-50
BVGSS
Gate-Source Breakdown Voltage
IG = -1 )lAo VOS= 0
-50
VOS=20V.10=lnA
.'
-0.7
-4
-0.2
-3.8
IG
Gate Operating Current
...10
CO
(0.762)
VGS = -30V. VOS = 0
Gate-Source Voltag~
(J1
0.028-0.048
IO,!I14-1]68IYZYIO.111-1.2191
Gate Reverse Current
Gate-Source Cutoff Voltage
Z
\~76dJ
/." .... _ /
IGSS
VGSlolfl
N
, P'2] '''\ ,
-1)',+:'0-
,
45
0.03D
10.406-0.483)
PARAMETER
VGS
0.100
!2.540)
(1.270)
0.'00
!Ilom_
Gate-Drain or Gate-Source Voltage
-50V
Gate Current
50mA
Device Dissipation (Each Side), T A = 85°C
(Derate 2.56 mWfC)
250mW
Total Device Dissipation, T A = 85° C
(Derate 4.3 mWfC)
500mW
Storage Temperature Range
--65°C to +200°C
Lead Temperature (1/16" from case
300°C
for 10 seconds)
-
DDsa
0.170-0.210
150°C
VOG = 20V,I0 = 200)lA
125'C
-15
pA
15
nA
lOSS
Saturation Drain Current
VOS = 20V, VGS = O,lNote 11
0.7
7
Gammon-Source Forward Transconductance
VOS = 20V, VGS = 0, INote 11
1000
4000
9fs
Common-Source Forward Transconductance
VOG = 20V, 10 = 200 pA, INote 11
90'
Comman-Source O~tput Conductance
VOS= 20V, VGS= 0
50
90'
Common-Source Output Conductance
VOG = 20V,I0 = 200)lA
4
Ciss
Common-Source Input Capacitance
Crss
Common-Source Reverse Transfer Capacitance
NF
Spot NoiSe Figure
en
Equivalent Input Noise Voltage
700
mA
1600
6
1= 1 MHz
nA
V
9f,
1= I kHz
UNITS
pA
pmho
pF
2
f= 100Hz,
VOS = 20V, VGS = 0
0.5
RG = 10 Mrl
f = 1 kHz
dB
0.020
)lV
v'HZ
Matching Characteristics
PARAMETER
2N5196
MIN
MAX
CONDITIONS
2N5197
MIN
MAX
2N5198
MIN
MAX
2N5199
MIN
MAX
IIG1-IG21
Differential Gate Current
VOG = 20V,
10 = 200)lA
10SSl
IOSS2
Saturation Drain Current
Ratio
VOS=20V,VGS=OV,
INote 11
0.95
1
0.95
1
0.95
1
0.95
1
~
91,2
T'ransconductance Ratio.
(Note 11
1 = 1 kHz
0.97
1
0.97
1
0.95"
1
0.95
I
IVGS1-VGS21
Differential Gate-Source Voltage
AIVGS1-VGS21
AT
,Gate-Source Differential Voltage
Change with Temperature.
INote 21
190,1-90.21
Differential Output Conductance
VOG = 20V,
10 = 200)lA
5
125°C
TA = 25°C,
T8 = 125°C
TA = _55°C,
TB = 25°C
1= 1 kHz
Note 1: Pulse te.t required, pulse width = 300 IlS, duty cycle $ 3%.
Note 2: Measured at end points, T A and TB'
4-13
5
5
5
5
5
10
15
5
10
20
40
5
10
2q
40
1
1
1
1
UNITS
nA
mV
)lvtc
,
~mho
,
.....
~
N
it)
Z
N
.~
Process 90
,
,
...
co 2N5245-47 N-Channel JFETs
~
N
U')
Z
N
...
it)
~
General Description
TO-92
The 2N5245 thru 2N5247 series of N-channel JFETs is
designed for common-source or common-gate VHF/UHF
amplifier, mixer and oscillator applications to 400 MHz.
N
Absolute Maximum Ratings
Z
Drain-Gate Voltage
Source Gate Voltage
Drain Current
Forward Gate Current
Total Device Dissipation @ 25°C
(Derate above 25°C)
Operating Junction Temperature
Range
Storage Temperature Range
Lead Temperature (1/16" from case
for 10 seconds)
It)
N
BVGSS
Gate-Source Breakdown
Voltage
fUM'
'yj l
0.180
14.572)
(2.540)
.J:M'.
(0.635\
0.014-0.016
(O.l56-0A06)
3 LEADS
--II-
---llO.01&
D.150-D.11D
(3.810-4.512)
.D:.liL.
W"'"''
~
(Dolan
1 LEADS
OIAPrN CIRCLE
,~,
PIN
1
-65°C to +150°C
-65°C to +150°C
FET
D
S
G
2
3
300°C
(25°C unless otherwise noted)
PARAMETER
Gate Reverse Current
~
30V
30V
30mA
50mA
360mW
2.88mWfC
Electrical Characteristics
IGSS
0.160
2N5245
MIN
MAX
CONDITIONS
VGS = -20V, VDS = 0
I
TA = 100°C
IG = -1 !lA, VOS = 0
-30
VOS= 15V,IO = 10 nA
-1
2N5246
MIN
MAX
2N5247
MIN
MAX
-1
-1
-1
-500
-500
-500
-30
UNITS
nA
-30
V
VGS(off)
lOSS
Gate-Source Cutoff
Voltage
Saturation Drain Current
VOS = 15V,YGS = 0, (Note 1)
Common-Source Forward
9f,
Transconductance
--6
--0.5
-4
-1.5
-8
rnA
5
15
1.5
7
8
24
4.5
7.5
3.0
6.0
4.5
8.0
mmho
70
.um})o
f= 1 kHz
Common-Source Output
90'
50
Conductance
Common-Source Forward
Re(Yf,)
Transconductance
Common-Source Output
Re(yo,)
Conductance
f= 400 MHz
,
VOS = 1SV, VGS = 0
4.0
SO
4.0
2.5
mmho
f= 100MHz
75
75
100
f= 400 MHz
100
100
150
f=100MHz
100
100
100
4.S
4.5
4.5
pmho
Common-Source Input
Re(Vi')
Conductance
Common-Source Input
Ciss
Capacitance
,
f= 1 MHz
C rss
NF
Common-Source Reverse
1
Transfer Capacitance
VOS= lSV,lD = SmA, RG = 1 krl
f= 100 MHz
2
2
2
VOS= 15V,IO = 5 rnA, RG = 1 krl
f= 400 MHz
4
4
4
Common-Source Power
VOS= lSV,lo=5rnA, RG= 1 krl
f= 100 MHz
18
18
18
Gain
VOS= 15V,lo=5mA, RG= 1 krl
f = 400 MHz
10
10
10
Noise Figure
pF
1
1
dB
Gp'
Note 1: Pulse Test PW 300 I1S, duty cycle
s: 3%.
4-14
Process 55
~
N
Z
CIt
General Description
Absolute Maximum Ratings
Fr'"'·~iQ:r
0.175-0.195
(25°C)
(:~~:=:!~~) ~ ~
300mW
2mWtC
-65°C to +200°C
-65°C to +175°C
5
FET
PIN
1
2
3
4
"
I~i~ol
(::~!:l
MAX
CIt
W
0)
o
S
0
G
Case
--
, / 2' ' \
-<:11+'01,:(./1
M W
Z'>.
45"
300°C
0.036-0.046
(O.914--1.,68I
) ' ...... _/
Y
O.OlS-D.D4B
(0.111-1.219)
(25°C unless otherwise noted)
CONDITIONS
2N5358
MIN
MAX
VDS = 0, VGS = -20V
VGS(offi
Gate-Source Cutoff Voltage
VDS= 15V, ID= 100nA
-0.5
BVGSS
Gate-Source Breakdown Voltage
VDS=0,IG=-10IlA
-40
T= 150°C
2N5359
MIN
MAX
2N5360
MIN
MAX
UNITS
-100
-100
-100
pA
-100
-100
-100
nA
-3.0
-O.B
-4.0
-0.8
-4.0
V
IDSS
Saturation Drain Current
VDS= 15V, VGS= 0, (Note 11
VGS
Gate-Source Voltage
VDS = 15V, ID = (Note 21
Common-Source Forward
Transconductance
Common-Source Forward
Transadmittance
Common-Source Output
Crss
Z
0.100
12.540)
0.050
(1.2701
Gate Reverse Current
90ss
N
11°.
IGSS
IYlsl
!D
0.110-0.210
o0 0
-40V
10mA
Electrical Characteristics
91s
W
U1
TO-72
0.209-02l0
The 2N5358 thru 2N5360 series of N·channel JFETs is
characterized for general purpose audio and R F ampli·
fiers requiring tightly specified IDSS ranges.
PARAMETER
VDS = 15V, VGS =
-40
-40
0.5
1.0
0.8
1.6
1.5
3.0
-0.3
-1.5
-0.4
-2.0
-0.5
-2.5
1= 1 kHz
1000
1=100MHz
BOO
1= 1 kHz
Conductance
_Common-Source Reverse Transfer
3000
1200
3600
900
1400
rnA'
V
4200
1400
Ilrnho
10
10
20
2
2
2
6
6
6
2.5
2.5
2.5
a
Capacitance
1= 1 MHz
pF
Common-Source Input
C;ss
NF
Capacitance
Noise Figure
Z
CIt
W
CIt
CO
-
2N5358-60 N-ChannelJFETs
Gate·Drain or Gate·Source Voltage
Gate Current
Total Device Dissipation
(25°C Free·Air Temperature)·
Power Derating (to +175°C)
Storage Temperat!Jre Range
Operating Temperature Range
Lead Temperature (1/16" from case
for 10 seconds)
N
I = 100 Hz.
RG = 1 M!1
Note 1: Pulse test duration = 300 I's. Duty cvcle :::; 3%.
Note 2: I D test conditions for Test 5: 2N5358 = 50 I'A; 2N5359 = 80 I'A; 2N5360 = 150 IJA.
4-15
dB
~
co
Cf)
Process 55
II)
Z
N
~
co
Cf)
2N5361-64 N-Channel JFETs
II)
General Description
'Z
N
TO·72
N
The 2N5361 thru 2N5364 series of N·channel JFETs is
characterized for general purpose audio and R F amplifiers requiring tightly specified IDSS ranges.
Cf)
II)
Absolute Maximum Ratings
co
0.175-0.195 hfl:;~'::0~;~;~
","=;]nltr
. m
'(25°C)
0.500
o0 0
Z
N
...
'P'"
co
Cf)
II)
Z
N
300mW
VGS(olf)
Gate-Source Cutoff
Voltage
/"
Voltage
2N5361
MIN
MAX
-100
100
CONDITIONS
VOS - 0 VGS - -20V I
•
IT-150"C
VOS = 15V, 10 - 100 nA
-1.0 .
VOS - 0, IG - -101lA
::-40
VOS - 15V, VGS - 0, (Note 1)
VOS
~
15V, ID - (Note 2)
Common-Source Forward
T ransconduct~nce
Common-Source Forward
Transadmittance
Common-Source Output
Crss
-6.0
2N5362
MIN
MAX
_100
100
-2.0
~7.0
2N5363
MIN
MAX
-100
100
-2.5
VDS - 15V. VGS - 0
-40
-8.0
-40
2.5
5.0
4.0
8.0
7.0
-1.0
-5.0
-1.3
-5.0
-2.0
I- 1 kHz
1500
I- 100 MHz
1700
I- 1 kHz
Common-Source Reverse
Transf~r
0.028-0.048
2N5364
MIN
MAX
-100
100
-2.5
Capacitance
Common-Source Input
Capacitance
NF
Noise Figure
pA
nA
-8.0
4500
2000
5500
1900
-40
14.0
-6.0
2500
6000
2100
9.0
-2.0
2700
18.0
-6.0
mA
V
6500
2206
Jlmho
20
40
40
60
2
2
2
2
6
6
6
6
2.5
2.5
2.5
2.5
pF
I- 1 MHi
Ciss
UNITS
V
Gate-Source Voltage
Conduptance
0'
...... -
(25°C unless otherwise noted)
Saturation Drain Current
90ss
~
~,<-<4
IO.914-I.16SIY,{"YIO.711_I.'''1
loSS
Vis
-
,'/1'\
0.036-0,046-, •
VGS
9ls
FET
S
0
G
Case
-0'7l--'045'
Gate-Source Breakdown
BVGSS
0.100
(2.540)
0.050
11.270)
-6SoC to +200°C
-65°C to +175°C
PARAMETER
IGSS
(::~~:,
MAX
2mWfC
Electrical Characteristics
Gate Reverse Current
(~::!:=:::!~) ~ ~
-40V
10mA
Gate·Drain or Gate-Source Voltage
Gate Current
Total Device Dissipation
(25"C' Free·Air Temperature)
Power Derating (to +175°C)
Storage Temperature Range
Operating Temperature Range
Lead Temperature (1/16" from case'
• for 10 seconds)
PIN
1
2
3
4
l1~i~OI
I- 100Hz,
RG - 1 Mn
Note 1: Pulse test duration = 300/.ls.
Note 2: 10 test conditions for Test 6: 2N5361 - 250 IlA; 2N5362 - 400 /.IA; 2N5363 - 700 IlA; 2N5364 - 900 IJA.
4-16
dB
~
Process 90
2N5397, 2N5398 N-Channel JFETs
General Description
TO·72
D.211!l-02:!O
Ar'~'
' '"::::"1:
u
l
11o.s
The 2N5397 thru 2N5398 series of N·channel JFETs is
designed for VHF/UHF common·source or common·
gate amplifiers, mixers and oscillators.
Absolute Maximum Ratings
):'"r
0.17S-0.1D5
(25°C)
0.170-0.210
00
Gate·Drain or Gate·Source Voltage
Gate Current
Total Device Dissipation
(Derate 1. 7 mWfC)
Storage Temperature Range
Lead Temperature (1/16" from case
for 10 seconds)
(:::~:=:::~~I ~ ~
-25V
10mA
300mW
-65°C t~ +200°C
0.030
(0,762)
MAX
4
0.100
(2,540)
0050
11.270)
PIN
1
2
3
-~:
ODD
FET
S
D
G
Case
-- -
1(2'-\
-9'+-'01,/,,/,
300°C
45"
0.03&-0.046
M
/." ...... _ /
0.028-0.048
(O.914-1.168IYZ'Y(D.7~1-1.219)
Electrical Characteristics
(25°C unless otherwise noted)
2N5397
MIN
MAX
CONOITIONS
PARAMETER
,
2N5398
MIN
MAX
-0.1
-0.1
nA
-0.1
-0.1
/1A
Gate Reverse Current
VGS = -15V, VOS = 0
BVGSS
Gate·Source Breakdown Voltage
VOS=O,IG= -l)1A
-25
VGSloff)
Gate·Source Cutoff Voltage
VOS= 10V,ID= 1 nA
-1.0
-6.0
-1.0
-6.0
IDSS
Saturation Drain Current
VDS = 10V, VDS =
10
30
5
40
VGS(f)
Gate·Source Forward Voltage
VDS = 0, IG = 1 rnA
Common·Source Forward
VDS= 10V,ID= lOrnA
Transconductance, (Note 1)
VDS - 10V, VGS -
Common·Source Output
VDS = 10V, ID = 10 rnA
IGSS
9fs
gas
Ciss
9iss
goss
Conductance
VDS - lOY. VGS -
Gps
Transfer
Capacitance
Common·Source Input Capacitance
a
a
VOG
= 10V,
a
5500
VOS - 10V, VGS -
VDG = lOV, 10 = 10 rnA
Conductance
VDS - 10V, VGS -
400
1.2
1.3
pF
f= 1 MHz
5.0
5.5
VOS - 10V, VGS -
2000
3000
400
a
VOG = 10V, 10 = 10 rnA
500
f=450MHz
5500
5000
Common·Source, Spot Noise
dB
3.5
Figure (Neutralized)
Note 1: Pulse test duration
=
10,000
15
(Neutralized)
VOG = 10V, ID = 10 rnA
NF
/1 mho
9000
a
Common·Source Power Gain
10,000
)1mho
a
Conductance .
V
200
VOS = 10V, VGS = 0
Common·Source Output
rnA
10,000
f = 1 kHz
10 = 10 rnA
VDG = 10V, 10 = 10 rnA
Forward
6000
a
Common·Source Input
Transconductance, (Note 1)
1
1
VDS = 10V, ID = 10 rnA
VDS - 10V, VGS -
Common~Source
9fs
-25
V
Common~Source ~everse
Crss
150°C
UNITS
2 ms.
4·17
~
Process '58
2N5432-34 N-Channel JFETs
General Description
TO-52
The 2N5432 thru 2N5434 series of N-channel JFETs is
designed for analog switch applications requiring very
low ON resistance.
Absolute Maximum Ratings
(5.309-5.8421
!--
0.100
o."~_~
12.5401
(1.270)
FET (07)
S
0
G
2
3
4S
/
/1
:\,.-_/
0.028-0.048
(0.711-1.2191
V,{",,;;:-
(25°C unless otherwise noted)
PARAMETER
CONDITIONS
IGSS
Gate Reverse Current
VGS=-15V VOs=O
BVGSS
Gate-Source Breakdown Voltage
IG=-l/1A,VOS=O
,
II 150·C
2N5432
MIN
MAX
-200
2N5433
MIN
MAX
-200
2N5434
MAX
MIN
-200
-200
-200
-200
nA
200
pA
200
nA
-25
IOlof!)
Drain Cutoff Current
VOS=5V,VGS=-10VI150~C
VGSlof!)
Gate·Source Cutoff Voltage
VOS=5V,10=3nA
lOSS
Saturation Drain Current
VOS = 15V, VGS = 0, (Note 2)
Static Drain-Source ON Resistance
PIN
1
"/,.+,
"'
2 "-
\,
1D.914-t.I68I
Drain-Source ON Voltage
11Z.701
MAX
.0.036-0.046
VOS(on)'
0.500
o0 a
(:::~:=:!!~J -t ~ (::~!~J
Q
rOS(on)
0.115-8.150
PLANl
J.
::·:;'·g~r
(25°C)
Reverse Gate-Drain or Gate-Source Voltage
-25V
Gate Current
100mA
Drain Current
400mA
Total Device Dissipation at 25°C
Free-Air Temperature, (Note 1)
300mW
Storage Temperature Range
-65°C to +200°C
Lead Temperature (1/16" from case
for 10 seconds)
300°C
Electrical Characteristics
Fn1~."'
~
-25
200
200
-9
1'00
150
2
-3
f = 1 kHz
Drain-Source ON Resistance
Ciss
Common-Source Input Capacitance
Crss
Common-Source Reverse Transfer
Capacitance
td
Turn ON Oelay Time
tr
Rise Time
VOO = 1.5V, VGS(on) = 0,
toff
Turn OFF Oelay Time
VGS(of!) = -12V, 10(on) = 10 mA
tf
Fall Time
VGS=O,IO=O
-1
V
V
-4
mA
30
5
7
10
50
70
100
VGS=O,10=10mA
rdslon)
pA
-25
200
200
-10
-4
UNITS
5
7
10
30
30
30
15
15
15
4
4
4
1
1
1
6
6
6
n
mV
pF
f= 1 MHz
VOS=O,VGS=-10V
n
ns
30
·30
30
Note 1: Oerate linearly at the rate of 2.3 mWf'C.
Note 2: Pulse test required pulse width 300 "S, duty cycle::; 3%.
VDD
R
YDD-VOS(ON}
l=~
.~~Your
v,.
f:,o
so
s
-=
4-18
Input Pulse
Rise time = 0.25 ns
Fall time = 0.15 ns
Pulse width = 200 ns
Pu Ise rate = 550 pps
Sampling Scope
Rise time = 0.4 ns
Input resistapce = 10M
Input Capacitance = 1.5 pF
Process 55
~
•
2N5457-59 N-Channel JFETs
General Description
TO-92
0.175-0.185
(4.445-4.699)
The 2N5457 thru 2N5459 series of N-channel JF ETs is
designed for general purpose smail-signal amplifier
and moderate ON resistance analog switch applications_
~i
~'''''1~~ .-
Absolute Maximum Ratings
Drain-Source Voltage
Drain-Gate Voltage
Source-Gate Voltage
Total Device Dissipation at 25°C
(Derate above 25°C)
Operating Junction Temperature
. Storage Temperature Range
Lead Temperature (1/16" from case
for 10 seconds)
Electrical Characteristics
PARAMETER
IGSS
Gate Reverse Current
Voltage
Gate-Source Cutoff
VGS(affl
lOSS
Voltage
Saturation Drain
Current
0.594
0.00l-0.013
(0.OIG-0.J3O} R
" (TVP}
-if~-~'
0.085-0.095. R
(2.159-2.413)
L--.l
, I'1 ~
0.045-0.055
(1.143-1.391)
11.143-1.3971
0.045-0.055
(1.143-1.391)
-
.
300°C
PIN
FET
1
2
3
G
S
D
'.
(25°C unless otherwise noted)
CONOITIONS
VGS' -15V VOS'
,
a IITA •
IG' -101lA, VOS'
a
MIN
100°C
-25
2N5457
TYP
MAX
-0.01 -1.0
200
MIN
-25
-60
2N5458
TYP
MAX
-0.01 -1.0
200
-60
MIN
-25
2N5459
TYP
0.01
MAX
1.0
200
VOS'15V, VGS' 0, (Nate 11
Transconductance
-0.5
-6.0
-1.0
-7.0
-2.0
-S.O
1.0
5.0
2.0
9.0
4.0
16
1,000
5,000
1,500
5.500
2,000
6,000
Conductance
Common-Source Input
10
50
15
50
20
50
4.5
7.0
4.5
7.0
4.5
7.0
1.0
3.0
1.0
3.0
1.0
3.0
0.04
3.0
0.04
3.0
0.04
3.0
VOS' 15V, VGS' 0
Capacitance
pF
1'1 MHz
Crss
Common-Source Reverse
Transfer Capacitance
NF
Noise Figure
mA
pmho
Common-Source Output
Ciss
nA
-60
1'1 kHz
90S
UNITS
V
VOS' 15V,IO' 10 nA
Common·Source Forward
91s
.
~
(OA06-D.4831
OIA HOLE (TVPI
25V
25V
25V
310mW
2.82mWfC
135°C
-65°C to +150°C
Gate-Source Breakdown
BVGSS
LEADS TO FIT INTO
1p
VOS - 15V, VGS - 0,
RG'l Mil,
NBW'l Hz
1'1 kHz
Note 1: Pulse test PW:S; 630 ms; duty cycle $. 10%.
4-19
dS
....
CO
~
11')
Z
N
oCO
~
11')
Z
N
~
Process 89
2NS460-62 P-Channel JFETs
General Description
TO-92
0.175-0.185
(4.445-4.6991
The 2N5460 thru 2N5462 series of P-channel JFETs is
designed for general purpose amplifier applications_
Absolute Maximum Ratings
Gate-Drain or Gate-Sou~ce Voltage
Gate Current
Total Device Dissipation
Storage Temperature Range
Lead Temperature (1/16" from case
for 10 seconds)
(25°C)
,.0.""'.
40V
10mA
310mW
--65°C to +150°C
~i
1;;:'
""·'' 1"--1
300°C
(~0.016-0.3301 R
~
RJ1Y~
~
(OA06-D.483)
DlA HOLE (TYPI
0.003-0.013
I
sa (TVP)
0.085-0.095
R
(Z.tSS-ZAt3)
0.045-0.055
(1.143-1.391J
---
0.045-0.055
(1.143-1.3971
0.045-0.055
(1.143-1.397)
PIN
1
2
3.
Electrical Characteristics
(25°C unless otherwise specified)
PARAMETER
IGSS
Gate Reverse Current
Gate-Source Breakdown
BVGSS
Voltage
FET
G
5
D
2N5460
MIN
MAX
CONDITIONS
VGS=20V,VDS=0
I
I
180°C
2N5461
MIN
MAX
2N5462
MIN
MAX
UNITS
5
5
5
nA
I
I
I
/lA
IG = 10/lA, VDS= 0
40
VDS= -15V,ID = 0.1 /lA
0.75
6.0
0.5
4.0
40
40
V
Gate-Sou ree Cutoff
VGS(off)
Voltage
ID = -0.1 rnA
VGS
Gate-Source Voltage
VDS= -15V
ID = -0.2 rnA
1.0
7.5
0.8
4.5
.
ID - -0.4 rnA
IDSS
Saturation Drain Current
VDS = 15V, VGS = 0
Common-Source Forward
9fg
Transconductance, (Note 3)
VDS=-15V,VGS=0
Cjss
Crss
NF
Common-Source Input
Capacitance
en
Transfer Capacitance
Noise Figure
Equivalent Input Noise
Rgen = 1M, BW = 1 Hz
6.0
V
5.0
2.0
9.0
4.0
16
1000
4000
1500
4000
2000
6000
.
75
75
75
7.0
7.0
7.0
2.0
2.0
2.0
2.5
2.5
2.5
115
115
115
pF
f=100Hz
Voltage
4·20
rnA
/lrnho
f= 1 MHz
Common-Source Reverse
VDS= -15V, VGS= 0,
1.5
f= I kHz
Conductance
VDS=-15V,VGS=0
9.0
1.0
Common-Source Output
gos
1.8
dB
nV
v'HZ
Process 50
~
2N5484-86 N-ChannelJFETs
General Description
TO·92
The 2N5484 thru 2N5486 series of N·channel JFETs is
designed for VHF/UHF amplifier, mixer and oscillator
appl ications.
Absolute Maximum Ratings
Drain·Gate Voltage
Source Gate Voltage
Drain Current
Forward Gate Current
Total Device Dissipation @ 25°C
. (Derate above 25°C)
Operating Junction Temperature
Range
Storage Temperature Range
Lead Temperature (1/16" from case
for 10 seconds)
(25°C)
25V
25V
30mA
10mA
310mW
2.82 mWfC
BVGSS
Gate-Source Breakdown
Voltage
, , ., , 1~i""'"
lEADS TO miNTO
DllDH~~E~~~~:
1r-
~~
i')
0.003-0.013
,(i,.,,,.,.,,,,R
f
Z
(II
~
(X)
CJ)
SOITvP)
0.594
,. . .,.".,Wt--·,,,!,,,·
I
--R
t~
12.15!1-Z.4111
11.143-1.391)
(1.143-1.3911
'01145-0055
~l
PIN
,
30boc
1
2
FET
G
S
3
0
(25°C unless otherwise noted)
PARAMETER
Gate Reverse Current
14.445-4.6591
-65°C to +150°C
-£5°C to +150°C
Electrical Characteristics
IGSS
nUS-O.IRS
2N5484
MAX
MIN
-1.0
CONOITIONS
VGS = -20V, VDS = 0
-200
TA=100°C
2N5485
MIN
MAX
-1.0
-200
-25
2N5486
MIN
MAX
-1.0
-200
IG = -1 !lA, VOS = 0
-25
-0.3
-3.0
-0.5
-4.0
-2.0
-6.0
1.0
5.0
4.0
10
8.0
20
3000
6000
3500
7000
4000
8000
UNITS
nA
-25
V
VGS(off)
Gate-Source Cutoff
Voltage
VOS = 15V, ID = 10 nA
lOSS
Saturation Drain Current
VOS = 15V, VGS = 0, (Note 1)
Common-Source Forward
915
Transconductance
rnA
f= 1 kHz
90'
Re(Yf,)
Re(yo,)
Common-Source Output
Conductance
Common-Source Forward
f=100MHz
Transconductance
f= 400 MHz
Common-Source Output
f=100MHz
Conductance
Common-Source Input
Re(Yis)
C;ss
C rss
50
2500
3000
Conductance
.umhos
f= 100MHz
f= 1 MHz
Transfer Capacitance
Common-Source Output
Capacitance
NF
Noise Figure
100
1000
1000
5.0
5.0
5.0
1.0
1.0
1.0
'2.0
2.0
2.0
2.5
3.0
2.5
2.5
2.0
4.0
2.0
4.0
f= 400 MHz
Capacitance
Coss
100
100
Common-Source Input
Common-Source Reverse
VOS= 15V, VGS=O, RG= 1 Mil
VDS= 15V, ID = 1 rnA, RG = 1 kll
VDS = 15V, 10 = 4 rnA, RG = 1 kll
3500
75
f = 400 MHz
VDS= 15V, VGS=O
75
60
f= 1 kHz
f=100MHz
f= 400 MHz
pF
dB
Gp,
Common-Source Power
Gain
VOS = 15V, 10 = 1 rnA
VOS= 15V, ID = 4 rnA
Noto 1: Pulse test pulse width 300 !l', duty cycle::; 3%.
f= 100 MHz
f=400MHz
16
25
18
10
30
20
18
30
10
20
~
Process 95
2N5515-24 N-Channel Monolithic Dual JFETs
General Description
R=
-:=i'~J
The 2N5515 thru 2N5524 series of N-channel rnonolithic
dual JFETs is designed for low to medium' frequency
differential amplifiers requiring very low noise and
high common-mode rejection.
Absolute Maximum Ratings
~
(25°C)
-40V
50mA
Electrical Characteristics
~
mom
Gate-Drain or Gate-Source Voltage
Gate Current
DeviCe Dissipation (Each Side), TA = 85°C
(Derate 2 mWtC)
250mW
Total Device Dissipation, T A = 85°C
(Derate 3 mWtC)
375mW
Storage Temperature Range
-65°C to +150°C
Lead Temperature (1/16" from case
300°C
for 10 seconds)
TO-71
PIN
.....
..,
~~~
0,030
UI405-D483)
llI.llZ)
0050
0.108
12.540)
'~i~'1
5
6
7
(1.110)
~
45"
003&-004&
';\2
FET (12)
S1
01
Gl
S2
02
G2
1
2
3
,
~~t.:)/.x ...... _ /
oD28-D IMI
~)YZytQ.l1I-1.Z1!1J
(25°C unless otherwise noted)
PARAMETER
CONDITIONS
MIN
MAX
pA
-250
nA
IGSS
BVGSS
Gate-Source Breakdown Voltage
IG = -1 p.A, VOS= 0
-40
VGS!offl
Gate-Source Cutoff Voltage
VOS'" 20V,IO'" 1 nA
-{l.7
-4
VGS
Gate-Source Voltage
-{l.2
-3.8
IG
Gate Operating Current
lOSS
Saturation Drain Current
VOS::: 20V, VGS '" 0, (Note 1)
Common-Source Forward
VOS'" 20V. VGS = 0,
9fs
Transconductance
(Note 1)
Common-Source Forward
Transconductance
VaG'" 29V, 10'" 200pA,
(Note 11
90S
~mmon-Source Output Conductance
VDS'" 20V. VGS '" a
VOG '" 20V, Ie '" 200p.A
VGS = -30V, Vos = 0
150'C
VOG = 20V, 10 '" 200pA
9Is
-100
V
pA
-100
nA
0.5
7.5
mA
1000
4000
500
1000
125°C
f= 1 kHz
UNITS
-250
Gate Reverse Current
Jlmho
10
,
90S
Common-Source Output Conductance
Ciss
Common-Source Input Capacitance
Cr55
Common-Source Reverse Transfer
Capacitance
VOS' 20V. VGS' 0
f'" 1 MHz.
'n
Equivalent Input Noise Voltage
VDG '" 20V,Ia '" 200.uA
,
2N5515-2N5519
f'" 10 Hz 2N5520-2N5524
30
15
f- 1 kHz
10
25
pF
5
nV
YHz
Matching Characteristics
PARAMETER
IIG1· IG21
lOSS,
IOSS2
Differential Gate
Current
Saturation Drain
Current RatiO
IVGS1-VGS21 _
Oifferentlal GateSource Voltage
alvGS1,VGS21
aT
Gate-Source Voltage
DifferentIal Drift,
(Notel)
2N5515,
2N5520
MIN
MAX
CONDITIONS
VaG'" 20V, 10= 200.uA
Vas'"
125'C
20V, VGS= 0, (Note 11
10
0.95
9fsl
9f52
'.
Conductance
Transconductance
Ratio, (Note 1)
,I
VaG'" 20V,IO::: 200.uA
':C J;'./D.fJZ8-Cl.04B
VZYIO.111-1.Z19J
300°C
for 10 seconds)
Electrical Characteristics
(2S0C unless otherwise noted)
PARAMETER
CONDITIONS
MIN
MAX
-200
200
I
IGSS
Gate Reverse Curtent
VGS = -30V, VDS = 0
SVGSS
Gate-Source Breakdown Voltage
IG = -I pA, VOS = 0
-50
VGS(off)
Gate-Source Cutoff Voltage
VOS= 20V, 10 = I nA
-0.7
-4
VGS
Gate-Source Voltage
-0.2
-3.8
IG
Gate Operating Current
150°C
I
VOG = 20V, 10 = 200.pA
I
125°C
V
-100
-100
pA
nA
rnA
lOSS
Saturation Drain Current
VOS = 20V, VGS = 0, (Note 1)
0.5
7.5
9fs
Common-Source Forward Transconductance
VOS = 20V, VGS = 0, (Note I)
1000
4000
500
1500
9f,
Common-Source Forward Transconductance'
VOG = 20V, 10 = 200pA, INote 1)
90'
Common-So~rce Output Conductance
VOS = 20V, VGS = 0
90'
Common-Sou,rce Output Conductance
VOG = 20V, 10 = 200pA
()
en
Common-Source Reverse Transfer
/pmIm
10
1
Common-Source Input Capacitan~e
Ciss
Crss
f= 1 kHz
UNITS
pA
nA
20
VOS = 20V, VGS = 0
f= 1 MHz
VOS = 20V, 10 = 200 pA
f= 100 Hz
f = 10 Hz
!
3.5
pF
5
10
nV
'11Hz
Capacitance
Equivalent Input Noise Voltage
Matching Characteristics
PARAMETER
CONDITIONS
IIG1-IG21
Differential Gate Current
VOG = 20V,
IO=200pA
10SSl
IOSS2
Saturation Drain Current Ratio
VOS = 20V, VGS = 0,
(Note 1)
91,1
91,2
Transconductance Ratio, (Note 1)
IVGSI-VGS21
Differential Gate-Source Voltage
L>IVGS1-VGS21
L>T
Gate-Source Differential Voltage
Change with Temperature,
(Note 2)
190,1-90,21
Differential Output Conductance
CMRR
Common-Mode Reject Ratio
125"C
f= 1 kHz
VDG = 20V,
10 = 200pA
2N6483
MIN
MAX
10
0.95
0.95
TA = 25°C,
TB = 125°C
TA = _55°C,
TS = 25°C
10
10
1.0
0.95
1.0
0.95
1.0
1.0
0.95
1.0
0.95
1.0
50
10
15
5
10
25
5
10
25
0.1
100
4·29
2N6485
MIN
MAX
UNITS
nA
rnV
pvl'c
1= 1 kHz
Not. 1: Pulse test required, pulse width 300 ps, duty cycle:::; 3%.
Note 2: Mea,ured at end points, TA and Ta,
2N6484
MIN
MAX
0.1
100
0.1
100
jJmho
dB
\
o,..
..,,..
ar
o
,..
..,
ex)
o,..
..,
Process 58
~
J1 08-1 0 N-ChannelJFETs
General Description
TO-92
0.115-0.185
(4.445-4.699)
The J108 thru J110 series of N-channel JFETs is designed
for analog switch applications requiring very low ON
resistance_
Absolute Maximum Ratings
Gate-Drain or Gate-Source Voltage
Gate Current
Total Device Dissipation
(25°C Free-Air Temperature)
Power Derating (to +125°C)
Storage Temperature Range
Operating Temperature Range
Lead Temperature (1/16" from case
for 10 seconds)
(25°C)
-25V
50mA
~l'"''
--1
0.003-0.013
·/iO.076-0.3301'
SOITYP)
,
.JJj;,
~
(0.406-0.4831
DlA HOLE (TVP)
350mW
3.5 mWfC
-55°C t'o +150°C
-55°C to +150°C
Electrical Characteristics
0085-0095
.
(2:,59-2:413) R
I
0.045-0,055
11.143-1.397)
0:045-0.055
(1.143-1.397)
0.045-0.055
11.143-1.397)
300°C
PIN
1
FET
G
2
S
3
D
(25°C unless otherwise noted)
CONDITIONS
PARAMETER
"."""'~ ~i
1fi
MIN
IGSS
Gate Reverse Current
VOS - 0, VGS - -15V, (Note 1)
VGS(oll)
Gate-Source Cutoff Voltage
VOS' 5V.IO·1 pA
-3
BVGSS
Gate-Source Breakdown Voltage
VOS"O,IG' -1 pA
-25
Jl08
TYP
MAX
3
MIN
-10
-2
Jl09
TYP
MAX
3
MIN
-6
-{l.5
Jl10
TYP
MAX
3
V
-25
-25
40
BO
10
mA
lOSS
Saturation Drain Current
VOS' 15V, VGS' 0, (Note 21
Drain Cutoff Current
VOS' 5V, VGS' -10V, (Note 11
3
3
3
'OS(onl
Drain Source ON Resistance
Vos:5 O.tv, VGS - 0
8
12
18
Cdg(offl
Drain Gate OFF CapacItance
15
15
15
Csg(off)
Source
15
15
15
Cdg(onl
+
Drain Gate Plus Source Gate
85
85
85
VOS' 0, VGS' -10V
OFF Capacitance
nA
n
pF
f'l MHz
VOS' \(GS' 0
ON Capacitance
nA
-4
10(011)
Gat~
UNITS
Csg(onJ
td(onJ
Turn ON Delay Time
t,
Rise Time
td(offl
Turn OFF
tf
Fall Time
De~ay
Time
Switching Time Test Conditions
VOO
VGS
RL
Jl0B
1.5V
-12V
150n
Jl09
1.5V
-7V
'Jll0
1.5V
-5V
150n
150n
4
1
1
1
6
6
6
30
30
30
ns
Note 1: Approximately doubles for every 10°C increase in TA.
Note 2: Pulse test duration = 300 p.s, duty cycle:5 3%.
,
4-30
4
4
Process 51
~
c...
.....
.....
...N
J111-13 N-Channel JFETs
General Description
TO-92
0.175-0.185
(4.44S-4.6991
The Jlll thru Jl13 series of N-channel JFETs is designed
for analog switch applications requiring low ON resistance
and moderate capacitance_
Absolute Maximum Ratings
Gate-Drain or Gate-Source Voltage
Gate Current
Total Device Dissipation
(25°C Free-Air Temperature)
Power Derating (to +125°C)
Storage Temperature Range
Operating Temperature Range
L~ad Temperature (1/16" from case
for 10 seconds)
~ro,"~ ~i
(25°C)
-35V
50mA
(O.406-DA8ll
OIA HOLE (TVP)
"""
.
PARAMETER
IGSS
Gate Reverse Current
VGS(oll) Gate-Source Cutoff Voltage
~
")W'~
0.085-0.095 R
12.159-2AI31
0.045-0.055
{1.143-1.3911
0.045-0.055
~)
0.045-0.055
(1.143-1.391)
300°C
PIN
1
FET
2
S
0
3
Electrical Characteristics
0,003-0.013
I/iO.016-0.3301"
5D (TVP)
~
""-, --1
350mW
3.5mWtC
-55°C to +150°C
-55°C to +150°C
1f::-
G
(25°C unless otherwise noted)
CONOITIONS
J111
TYP
MIN
VOS' 0, VGS' -15V, (Note 1)
VOS' 5V, 10 • 1 JlA
-3
-35
BVGSS
Gate-Source Breakdown Voltage
VOS' 0, IG • -1 JlA
MAX
1
MIN
-10
-1
J112
TYP
MAX
1
MIN
-5.
-0.5
J113
TYP
MAX
1
UNITS
nA
-3
V
-35
-35
rnA
lOSS
Saturation Drain Current
VOS' 15V, VGS' 0, (Note 2)
10(011)
Drain Cutoff Current
VOS' 5V, VGS' -10V, INote 1)
1
1
1
nA
'OS(on)
Drain Source ON Resistance
VOSSO.lV, VGS'O
30
50
100
n
Cdg(off)
Oraln Gate OFF Capacitance
5
5
5
C.g(o")
Source Gate OFF Capacitance
5
5
5
28
28
28
Cdg(on)
+
C.g(on)
2
5
20
VOS' 0, VGS' -10V
pF
1'1 MHz
Drain Gate PI.us Source Gate
ON Capacitance
td(on)
Turn ON Delay Time
t,
Rise Time
td(o'"
Turn OFF Delay Time
II
Fall Time
VOS'VGS'O
Switching Time Test Conditions
VOO lOV
VGS -12V
800n
RL
10V
-7V
1600n
10V
-5V
3200n
Note 1: Approximately doubles for every lOoe increase in T A.
Note 2: Pulse test duration = 300 1'5, duty cycle::; 3%.
4-31
,
7
7
7
6
6
6
20
20
20
15
15
15
n'
.....
.........
..,
uf
..,.........
.,;
..,.........
~ ..
Process 88
,
,
J174-77 P-Channel JFETs
,
General Description
TO·92
0.175-0.185
(4.445-4.699)
The J174 thru J177 series ofP·channel JFETs is designed
for low ON resistance analog switch applications .
..;
.....
r;
Absolute Maximum Ratings
". , ,., .1~i
(25°C)
Gate·Drain or Gate·Source Voltage, (Note 1)
30V
Gate Current
50mA
Total Device Dissipation
(25°C Free·Air Temperature)
350mW
Power Derating (to +125°C)
3:5 mWfC
-55°C to +150°C
Storage Temperature Range
Operating Temperature Range
-55°C to +150°C
Lead Temperature (1/16" from case
for 10 seconds)
300°C
..
0.016_0.019
(0.406-0.483)
DlA tlOLE (TYP)
~~
,
(15.0881
~
PARAMETER
IGSS
VGS(offJ
BVGSS
-
Gate Reverse Current
Gate-Source Cutoff
Voltage
Gate-Source Breakdown
Voltage
CONOITIONS
PIN
1
2
(.-...,
VOS " 0, IG = 1 pA
C,g(offJ
Cdg(onj
+
Csg(onj
... ~/
td(on)
Turn ON Delay Time
"'dlofl)
Rise Time
Turn OFF Delay Time
'I
Fall Time
1
0.045-0.055 .
---
.
11.143-1.397)
.,
FET
S
G
0
MIN
'10
3
J17S
TYP
MAX. MIN
1
6
J176
TYP
1
MAX
1
4
J177
TYP
MIN
o.a
MAx
1
(
UNITS
,,_ nA
2.25
V
30
30
30
..
-20
-1O!J
-1
VDS$O.1V,VGS=O
-';0
-7)
,--,'
-1
85
~
.J
-'2,
-25.
~.
-1.5
-20
"
-1
-1
. 250
5.5
..
300
~
mA
nA
n'
5:5,
5.5
5.5
5.5
5.5
5.5
5.5
VOS ~ VGS = 0
40
40
40
40
SwitchIng TIme Test Conditions
J174
Jl77
J175
J176
-10V -6V
-6V
-6V
VDD
air
6V
3V
VGS(ofl) 12V
560n 12kn 5.6kn 10kn
RL
2
5
15
20
5
10
20
25
5
10
15
20
10
20
20
25
Capacitance
Drain Gate Plus Source
Gate ON Cap~citance
MAX
1
30
VDS = -15V, VGS= 10V, (Not. 21
Drain Gate OFF
Source Gate OFF
Capacitance
J174
TYP
5
VOS=:;-15V,lp = -10 nA
Saturation Drain Current VOS = -15V, '-'GS = 0, (Not. 3)
Cdg(off)
3
0.045-0.055
(1.143-1.397)
MIN
Drain Cutoff Current
Resistance
r
:~!'
R
(1.143-1.391)
VOS - 0, VGS - 20V, (Note 2)
IOloffJ
Drain Source ON
"
(25°C unless otherwise noted)
lOSS
rOS{on)
.
0.085-0.095
~-
0.003-0.013
'l/iO.016-0."" R
SO (TYP)
(Z.159-Z.4tJ)"
.3
Electrical Characteristics
1p'
,
VDS = 0, VGS = 10V
f:: 1 MHz
Note 1: Geometry is symmetrical. Units may be operated with source and drain leads interchanged.
Note 2: Approximately dOUbles for every 10°C increase in TA.
Note 3: Pulse test duration = 300 IlS; duty cycle $. 3%.
pF
n,
~
~
Process 52
J201-03 N~Channel JFETs
General Description
TO·92
11.115-0.185
(4.445-4.699J
The J201 thru J203 series of N·channel JFETs is designed
for low to medium frequency amplifiers requiring low
input current and input noise voltage.
Absolute Maximum Ratings
". ,.,",~~~··l"'··
~i
(25°C) .
Electrical Characteristics
PARAMETER
IGSS
CONDITIONS
Voltage
0.085-0.095
12.159-2.413)
3 f 1 0.045-0,055
R)tlY;+
R
--(1.143-1.397)
0.045-0.055
(1.143-L3971
0.045-0.055
11.143-1397)
PIN
MIN
J201
TYP
1
FET
G
2
S
3
D
MAX
MIN
J202
TYP
MAX
-100
VOS - 0, VGS - -20V, INote 2)
Gate Reverse Current
~
(25°C unless otherwise noted)
Gate-Source Cutoff
VGS(off)
--1
0.003-0.013
"/iO.076-0., OI R
SO (TYP)
~
(0.406-0.483)
DlA HOLE (TVP)
Gate·Drain or Gate·Source Voltage, (Note 1)
-40V
Gate Current
50mA
Total Device Dissipation
(25°C Free·Jliir Temperature)
350mW
Power Derating (to +125°C)
3.5mWtC
Storage Temperature Range
-55°C to +150°C'
Operating Temperature Range
-55°C to +150°C
Lead Temperature (1/16" from case
for 10 seconds)
300°C
1p
VDS = 20V, 10 = 10 nA
-0.3
VOS=O,IG=-lIlA
-40
-1.5
MIN
J203
TYP
-4.0
-0.8
MAX
-100
-100
-2.0
UNITS
pA
-10.0
V
BVGSS
Gate·Sourc,e Breakdown
Voltage
lOSS
Saturation Drain Current
liDS = 20V, VGS = 0, (Note 3)
IG
Gate Current
VOG = 20V, ID = 'OSS(MIN)
-40
-40
1.0
0.2
4.5
0.9
-35
4.0
20
-35
-35
rnA
pA
Common-Source Forward
91s
Transconductance,
500
(Note 3)
Ilrnho
Common-Source Output
90S
Conductance
1
3.5
10
5
5
5
2
2
2
10
10
10
VOS = 20V, VGS = 0
Common-Source Input
Giss
1500
1000
1= 1 kHz
Capacitance
1= 1 MHz
Crss
Common-Source Reverse
Tran;fer Capacitance
en
Equivalent Short-Circuit
Input Noise Voltage
pF
VOS = lOV, VGS = 0 1= 1 kHz
Note 1: Geometrv is symmetrical. Units may be operated with source and drain leads interchanged.
Note 2: Approximately doubles for every 10° C increase in T A.
Note 3: Pulse test duration
=
2 ms.
4·33
nV
,;Hz
N
o.....
......
o...
N
-:t
N
-:t
~
Process 90
•
J210-12 N-Channel JFETs
,
General Description
TO-92
0.175-0.185
(4.445-4.699)
The J210 thru J212 series of N-channel JFETs is characterized for low to medium frequency amplifiers requiring
high transconductance and low input capacitance_
Absolute Maximum Ratings
Gate-Drain or Gate-Source Voltage
Gate Cu rrent
Total Device Dissipation
(25°C Free-Air Temperature)
Power Derating (to +125°C)
Storage Temperature Range
Operating Temperature Range.
Lead Temperature (1/16" from case
for 10 seconds)
,
OIA HOLE (TYP)
~'"'
0.003-0.013
iO.076-0."01 R
RJ1Y~
0.085-0.095 R
(2.159-2.413)
0.045-0.055
11.143-1.391)
11.143-1.3971
350mW
3.5 mWfC
-55°C to +150°C
-55°C to +150°C
0.045-0.055
(1.143-1.391)
PIN
1
2
3
300°C
FET
G
S
0
(25°C unless otherwise noted)
CONDITIONS
MIN
IGSS
Gate Reverse Current
VOS' O. VGS" -15V. (Note 11
VGS(olf)
Gate-Source Cutoff Voltage
VOS·15V.IO -1 nA
-1
BVGSS
Gate-Source Breakdown Voltage
VOS' O.IG· -lpA
-25
lOSS
Saturation Drain Current
VOS' 15V. VGS" O. (Note 21
IG
Gate Current
VOG' 10V. 10' 1 rnA
9f,
JI
,'(TV'I
0'Dl6-0,0"1~~ ~
115.0881
(0.406-0.4831
-25V
lOrnA
Electrical Characteristics
PARAMETER
~,,,,,,~~l
(25°C)
1~
J210
TYP
MAX
100
-3
MIN
-2.5
2
15
4000
Transconductance. (Note 2)
MAX
100
-4.5
J212
MIN. ,yp.
-4
20
7
40
7000
12000
,umho
Common-Source Output
Ciss
Crss
en
Capacitance
Common-Source Reverse
5.0
VOS' 15V. VGS' 0
Equivalent Short-Circuit Input
5.0
200
5.0
pF
f'l MHz
Transfer Capacitance
Noise Voltage
200
150
Conductance
Common-Source Input
rnA
pA
f· 1 kHz
90'
pA
V
-10
12000
7000
UNITS
-6
15
-10
12000
MAX
100
-25
-25
-10
Common-Source Forward
J211
TYP
f: 1 kHz
Note 1: Approximately doubles for every 10°C increase in TA.
Note 2: Pulse test dUration = 2 ms.
4-34
1.5
1.5
1.5
10
10
10
nV
v'Hz
~
Process 88
J270, J271 P-Channel JFETs
General Description
TO-92
""'
0.175-0.185
The J270 thru J271 series of P-channel JFETs is characterized for low to medium frequency small-signal amplifiers which require high transconductance and low
input noise voltage_
Absolute Maximum Ratings
(4.445-4.699)
'"""'"~, ~ .f
ol~Oi~~E~T~~l
0.D45-0055
(1.14]-1.397)
PIN
1
2
3
CONDITIONS
MIN
G;;tte Reverse Current
VDS = 0, VGS = 20V, (Note 2)
VDS = -15V, ID = -1 nA
0_5
BVGSS
Gate~Source Breakdown Voltage
VDS = 0, IG =,1 IlA
30
IDSS
Saturation Drain Current
VDS = -15V, VGS = 0, (Note 3)
IG
Gate CUrrent
VDG = -15V, ID = IDSS(MIN)
Common-Source Forward
J270
TYP
FET
S
G
D
MAX
MIN
J271
TYP
2_0
-2
-15
-50
8000
18000
= 1 kHz
Ilrnho
SOD
200
VDS
Common-Source Input
rnA
pA
60
15000
pA
V
-6
15
UNITS
4_5
1.5
30
Common-Source Output
Conductance
MAX
200
200
6000
Transconductance, (Note 3)
f
= -15V, VGS = 0
Capacitance
20
20
5
5
10
10
f= 1 MHz
en
-r
.0.045-0.055
(1.143-1.]91)
0_045-0.055
Gate-Source Cutoff Voltage
Crss
21
I
(1.143-1.397)
IGSS
Ciss
0.035-0.095
(Z.159-ZAll) R
----.l...
VGS(off)
gos
J
I
(25°C unless otherwise noted)
PARAMETER
9fs
OOOl-O.O13
iQ.076-0_3J01"
5°{TVPl~
~l"~"
---I
(25°C)
Gate-Drain or Gate-Source Voltage, (Note 1)
30V
-50mA
Gate Current
Total Device Dissipation
(25°C Free-Air Temperature)
350mW
Power Derating (to +125°C)
3_5mWfC
-55°C to +150°C
Storage Temperature Range
-55°C to +150°C
Operating Temperature Range
Lead Temperature (1/16" from case
300°C
for 10 seconds)
Electrical Characteristics
1p
Common-Source Reverse
Transfer Capacitance
= -10V,
Equivalent Short-Circuit
VDS
Input Noise Voltage
ID = IDSS(MIN)
f= 1 kHz
pF
Note 1: Geometry is symmetrical. Units may be operated with source and drain leads interchanged.
Note 2: Approximately doubles for every 10°C increase in TA.
Note 3: Pulse test duration = 2 ms.
4-35
....IJ':L
-JHz
Process 90
~
J300 N-ChannelJFET
Gen~ral
Description
TO-92
The J300 N-channel \ JFET is designed for VHF/UHF
common-source or common-gate amplifier, oscillator
and mixer applications.
Absolute Maximum Ratings
(25°C)
Gate-Drain or Gate-Source Voltage
-2pV
Gate Current
10mA
Total Device Dissipation
(25°C Free-Air Temperature)
0.175-0.185
(4.445-4.6991
"'. '"~. ~i
--I
'"'~"I"-
D1A HOLE (TYP)
-55°C to +150°C
Operating Temperature Rang.e
-55°C to +150°C
300°C
Electrical Characteristics
(25°C unless otherwise noted)
Gate Reverse Current
MIN
Gate-Source Cutoff Voltage
VOS= 10V,IO= 1 nA
Gate-Source Breakdow,:, Voltage
VOS= O,IG = -lilA
-25
lOSS
Saturation Drain Current .
VOS = 10V, VGS = 0, (Note 21
VGS(t)
Gate-Source Forward Voltage
IG = 1 rnA, VOS = 0
-
gos
Common-Source Output Transconductance
Ciss
Common-Source Input Capacitance
Common-Source Reverse Transfer Capacitance
Common-Source Output Capacitance
IVlsl
Common-Source Forward Transadmittance
IVlgl
Common-Gate Forward Transadmittance
GIg
Common-Gate Power Gain
NF
Noise Figure (Single Sid~bandl
pA
. -6
30
6
1
rnA
V
9000
4500
VOG=10V,lo=5rnA
UNITS
V
Common-Source Forward Transconductance,
(Note 21
MAX
-500
VGS(off)
Coss
J300
TYP
VGS= -15V, VOS= O. (Note 1)
\
BVGSS
Crss
,
FET
G
S
0
-1
gts
0.045-0.055
(1.143-1.391)
---
-
CONDITIONS
PARAMETER
IGSS
RJIY.-r
0.OB5-0.o95
---R
{2.159-2.4131
PIN
1
2
3
Lead Temperature (1/16" from case
for 10 seconds)
t:
0.045-0.055
(1.143-1.391)
0.045-0.055
(1.143-1.391)
350mW
Storage Temperature Range
0.003-0.013
,,/iO.0J6-0.J301 R
S"ITYPI
---1
(0.406-0.483)
3.5mWfC
Power Derating (to +125°C)
1fi
1= 1 kHz
Ilrnho
200
VOG = 10V, 10 = 5 rnA
f = 1 MHz
3.5
5.5
0.8
1.7
pF
1.5
VOG = 15V,IO = 5 rnA
I = 100 MHz
1= 450 MHz
6200
6000
1= 100 MHz
6000
5500
1= 450 MHz
17
1= 100 MHz, (Note 3)
Nota 1: Approximately doubles for every 10°C increase in TA.
Note 2: Pulse test duration = 2 ms.
Nota·3: Typical values for performance at 100 MHz in a common-gate circuit operating 3 dB bandwidth is 2 MHz.
4-36
2
Ilrnho
dB
Process 50
~
c..
CIJ
"
o
CII
General Description
TO-92
The J304 thru J305 N-channel JFETs are designed for
low input capacitance VHF amplifier, oscillator and
mixer applications_
Absolute Maximum Ratings
0.115-0.185
14.445-4699)
_." " . ffi
(25°C)
-30V
IOmA
'.'16·'·01'1~~ ~
/1'.""
l
10.406-0483)
0085-0.095
12.159_2.413)R
t045.O
,"
-..,
f": -T
0045-D05&
11.143-1.3911
~C1.14J-1391)
0045-0.1155
(1.143-1.391)
PIN
1
2
3
300°C
FET
G
S
0
(25°C unless otherwise noted)
CONDITIONS
'.
MIN
J304
TYP
MAX
MIN
J305
TYP
-100
IGSS
Gate Reverse Current
VOS = 0, VGS = -20V, (Note 1)
VGS(off)
Gate Source Cutoff Voltage
VOS= 15V, 10 = 1 nA
-2
BVGSS
Gate Source Breakdown Voltage
VOS= 0, IG = -1 IlA
-30
lOSS
Saturation Drain Current
VOS = 15V, VGS = 0, (Note 2)
-6
MAX
-100
Ciss
Crss
Coss
9ls
goss
Transconductance, (Note 2)
-30
5
15
1
4500
7500
3000
8
Cammon-Source Input
9iss
biss
Gps
50
COlJlmon-Source Reverse
1= 1 MHz
Transfer Capacitance
Common-Source Output
Capaci tanee
3.0
3.0
0.8
0.8
1.0
1.0
Cammon-Source Forward
1= 100MHz
Transconductance
1= 400 MHz
4200
Common-Source Output
I~ 100MHz
60
Conductance
1= 400 MHz
80
1= 100MHL
800
3600
Common-Source Input
1= 100 MHz
80
Conductance
1= 400 MHz
800
Common-Source Input
1= 100MHz
2000
Susceptance
f = 400 MHz
7500
1= 100 MHz
20
Gain
VOS = 15V, VGS = 0
VOS=15V,lo=5mA
pF
3000
1- 400 MHz
Common-Source Power
50
VOS = 15V, VGS = 0
Capacitance
Susceptance
mA
Ilmho
Common-Source Output
Transconductance
Common-Source Output
boss
pA
-3
-0.5
1= 1 kHz
gas
UNITS
V
Common-Source Forward
9ls
0.003-01113
-1~'
""'.0"""
1'·(TVPl~
DIAHOLE/TVP)
350mW
3.5mWtC
-55°C to +150°C
-55°C to +150°C
Electrical Characteristics
PARAMETER
1= 400 MHz
11
1= 100 MHz
1.7
1=400MHz
3.8
60
800
Ilmho
80
2000
dB
NF
Noise Figure
(Single Sideband)
CIJ
o
~
J304, J305 N-Channel JFETs
Gate-Drain or Gate-Source Voltage
Gate Current
Total Device Dissipation
(25°C Free-Air Temperature)
Power Derating (to +125°C)
Storage Temperature Range
Operating Temperature Range
Lead Temperature (1/16" from case
for 10 seconds) ,
c..
VOS = 15V, 10 = 5 mA,
RG ='1 kS'l
Note 1: Approximately doubles for every 10°C increase in TANote 2: Pulse test duration = 2 ms.
4-37
o
.....
..,
('I)
or
o('I)
..,..
CO
o('I)
...,
~
Process 92
J308-10 N-Channel JFETs
General Description
TO-92
The J308 thru J310 series of N-channel JFETs is designed
for VHF amplifier, oscillator and mixer applicatlons_
Absolute Maximum. Ratings
Drain-Gate Voltage
Source-Gate Voltage
Forward Gate Current
Total Device Dissipation @ 25° C
(Derate above 25°C)
Storage Temperature Range
Operating Junction Temperature
Range
Lead Temperature (1/16" from case
for 10 seconds)
Electrical Characteristics
PARAMETER
Gate-Source Breakdown
BVGSS
IGSS
Voltage
Gate Reverse Current
Gate-Source Cutoff
VGS(offl
Voltage
Saturation Drain
lOSS
Current
Gate-Source Forward
VGS(fJ
Voltage
25V
25V
10mA
350mW
3.5mWfC
-55°C to +150°C
(4.445-4.69gr
,. . .""-ffi
1
'-'''-DO''
lD.4116-t).483}
DlAHOLE(TVP)
300°C
CONDITIONS
MIN
VDS=O,IG=-I~A
VGS = -15V, VOS = 0
J30B
TYP
G
S
3
D
MIN
J309
TYP
MAX
MIN
J310
TYP
MAX
-25
UNITS
V
-1.0
-1,0
-1.0
nA
1.0
1.0
1.0
p.A
-1.0
-4.0
-2.0
-6.5
V
VGS = 0, VOS = 10V,
(Note II
12
60
12
30
24
60
mA
1.0
.VOS= 0, IG = 1 mA
BOOO
20000
1.0
20000
10000
V
lBOOO
200
~mhos
Transconductance
Conductance
13000
13000·
12000
150
100
150
1.8
2.5
I.B
2.5
1.8
2.5
4.3
5.0
4.3
5,0
4.3
5.0
pF
f= 1 MHz
Gate-Source
Capacitance
VOS = 10V, 10 = 10 mA
BOOO
150
200
Capaci~ance
1.0
f = 1 kHz
f= 100 Hz
Ttansconductance
Common-Gate Input
Re(Y;gl
FET
1
2
-6.5
Common-Source Forward
Re(Yfsl
0.045-0.055
-(1.14]-1.3911
-1.0
Output Conductance
Input Noise Voltage
PIN
-25
T = 125°C
Transconductance
Equivalent Short-Circuit
rI
VOS=10V,ID=lnA
VGS= -lOV, VDS= a
en
MAX
-25
Gate-Drain
Cgs
l
(25° C unless otherwise noted) .
Common-Gate Output
Cgd
..JdY;r-
0.045-11,[155
-55°C to +150°C
VOS = 10V, 10 = 10 mA
90g
0.oa5-o.o9S
i~l
•
\1.143-1.391)
Common-Gate Forward
9fg
SOITY')
~ ~~
115.'881
~D45_"55
Common-Source
gos
1pI/i::::=~:::I'
{l.143-1.391}
Common-Source Forward
gls
0.175-0.185
Conductance
10
10
10
12
12
12
12
12
12
0.7
0.7
0.5
0.25
0.25
0.25
16
16
16
1.5
1.5
1.5
..BY.
v'Hz
mmho
Common:Source Input
Re{Visl
Conductance
VDS = 10V, ID = 10 mA
f= 100MHz
Common-Source Output
Re(Vos)
Gpg
NF
Conductance
Common-Gate Power
Gain
NOIse Figure
Note 1; Pulse test PW 300 p.s, duty cycle::;; 3%.
4-38
dB
~
Process 94
General Description
-:~:=:~::!-
i~~
CJn~itiD!l)
"i11
ii"i"ii=iii9]L~~
MIN
Absolute Maximum Ratings
(25°C)
-50V
10mA
Gate-Drain or Gate-Source Voltage
Gate Current
Device Dissipation (Each Side), TA ~ 85°C
250mW
(Derate 2 mWfC)
Total Device Dissipation, T A ~ 85°C
(Derate 3 mWfC)
375mW
-65°C to +200°C
Storage Temperature Range
Lead Temperature (1/16" from case
for 10 seconds)
300°C
Electrical Characteristics
5
,':G:rt!:
-<
OQ2g-a045~'1~
...
''11;-.-1
---
(O1l1-,,4l1
0021-0034
~m~-----L~OR
IIAX
~'~~ ~ ~~
"""
"'""""~~,~'"
-If-(:::=::~~)
1---
FET
1
--
D 1&5_0
,,,.,
PIN
,,~
iiOiO)
osoo_ t~~t
--
2
D
3
4
5
S
7
8
G
Case
5
D
G
Sub
TO-71 NDF94D6-NDF941D 5erie.
...
1Ar::::~'
~
~
"145"
nUD
mnm
1~:~=::~~I-1 f-- ~)
".
UlS-OC46
~I
~
PIN
FET
1
51
2
D1
iZiiii
ii2iii
'''''~':~~Qtl~'
-~~4-~J
/." ....
;/
-
3
5
6
7
OIlZ'_~1I41
~IVZ'1!~1
G1
52
D2
G2
(25°C unless otherwise noted)
PARAMETER
CONDITIONS
IGSS
Gate Reverse Current
VGS = -30V, VDS = 0
SVGSS
Gate-Source Breakdown Voltage
IG = -1 "A_ VDS = 0
VGS(offl
Gate-Source Cutoff Voltage
VDS = 20V. ID = 1"A
IG
Gate Operating Current
VOG
MIN
I
I
150 e
0
UNITS
MAX
-10
pA
-25
nA
-50
V
=
0.5
I
I
35V, 10:: 20Q-IJA
Saturation Dram Current
VDS = 20V. VGS
Common-Source Forward
VDG = 20V, ID
Transconductance
=
0, (Note 1)
= 200 "A.
4.0
-5
pA
-10
nA
0.5
10
mA
900
2000
125°e
(Note 11
f= 1 kHz
Common·Source Output
VDG = 20V. ID
'os
Conductance
Ciss
Common-Source Input Capacitance
IJmho
= 200 "A
1
6
pF
f= 1 MHz
VDS = 20V. VGS = a
Common-Source Reverse Transfer
Crss
0.1
Capacitance
Equivalent Input
'n
N~lse
Voltage
VDG = 20V. ID
= 200"A
f = 10 Hz
...!!Y.
30
,jH",
Matching Characteristics
PARAMETER
IIG1-1G21
CONDITIONS
Differential Gate
VDG- 20V,
Current
ID=200"A
IDSSl
Saturation Dram
IOSS2
Current Ratio
NDF9401.
NDF9406
MIN
MAX
125°e
VDS= 20V, VGS=O,(Noto 11
0.95
Source Voltage
TA = 25°e,
Gate-Source Voltage
l>IVGS1-VGS21.
AT
.
TS = 125°e
.
Differential Drift,
(Note lJ
VDG = 20V.
ID
= 200 "A
1
NDF9403.
NDF940B
MIN
MAX
1
1
0.95
1
NDF9404.
NDF9409
MIN
MAX
0.95
1
NDF9405,
NDF9410
MIN
MAX
1
0.95
1
1
0.90
UNITS
nA
1
5
5
10
15
25
5
10
10
10
25
5
10
10
10
25
0.1
0.1
0.1
0.1
0.1
mV
"Vre
55°e,
TA
TS = 25°e
Differential Output
19os1 -gos21
NDF9402.
NDF9407
MIN
MAX
1
Differential Gate-
IVGS1-VGS21
Conductance
.u mho
f: 1 kHz
~
Transconductance
9fs2
Ratio, (Note lJ
CMRR
\
0.97
Common-Mode
VDD = 1O-20V.
Rejection Ratio
10:: 200,uA, (Note 2)
Note 1: Pulse test required, pulse width
Note 2:
CMRR
-n-n
~.~
TO-99 NDF94Dl-NDF94D5 Serie.
The NDF9401 thru NDF9410 series of N-channel monolithic cascode duals is designed for broadband low noise
differential amplifier applications requiring tight match,
low capacitance, and very high common-mode rejection_
IDSS
CC
COCO
~~
00
NDF9401-10 N-Channel Monolithic Cascode Dual JFETs
'fs
zz
= 300 IlS, duty
1
120
0.97
120
cycle:::::; 3%.
= 20 10910 l>VDD/l>IVG51-VG521, (l>VDD = 10V).
4-39
1
0.95
110
1
0.95
110
1
0.90
100
1
dS
M
o
,..
It)
LL
Q.
N
...
o,..
It)
LL
Q.
,......
o
,..
It)
LL
Q.
.......
M
o,..
It)
LL
Z
N
...
o,..
It)
LL
Z
,..
o
,..
It)
~
NF5101-03/PF5101-03 N-Channel JFE;Ts
General Description
TO·92
The NF5101·3 (TO·72) and PF5101·3 (TO·92) are
N·channel silicon Junction Field·Effect .Transistors
designed for ultra·low noise preamplifier applications,
particularly hydrophones, particle detectors, high quality
mic/phono!tape, video, vidicon and I·R sensor' preampli·
fiers.
TO·72
a 115-0.ns
*": .
-.-l
. ··m,'' ' ~
(0406-11483]
Absol~te
Maximum Ratings
1
40V
40V
10mA
310mW
2.82mWfC
-65to+150°C
0115-0195
0170-0210
"AT,:::,5::'''''Q~'NJ
-.L
"It
~'MIN
MAX
UtH-I.m/
0.045-0.055
OIDG
-\1.143_1.391)
.P~
'
IV,,,,
/
~
0045-0055
12IS9_2.4I3J R
il.mi
""
(1211»
0003-0.1113
,ji."
..",,,·
.t
1~S"lTYPJ
11085-0.095
05DO
DDnO.DlU
u'"''''
f:~:=:;;~I-t l- (O.lUI
.
~
01145-0055
I
Drain·Gate Voltage
Reverse Gate·Source Voltage
Forward Gate Current
Device D'issipation @25~C>
Derate Above 25° C
Operating Temperature Range
Lead Temperature (1/16" from case
for 10 seconds)
Frr0209-0230
14.445-4.&9111
OIA HOLE (TV!'I
15' ~~~t-;J
~
0.028-01148
I0914-1168JYZYI0111_1.219J
11.143-1.3911
300°C
Electrical Characteristics
PARAMETER
BV Gss
Gate-Source Breakdown
10 = 1/1A, Vos =OV
PF/NF5102
PF/NF5101
CONOITIONS
MIN
TYP
MAX
MIN
TYP
PF/NF5103
MAX
TYP
MAX
UNITS
40
40
40
MIN
V
Voltage
LL
Z
Process 51
IGSS
Gate Reverse Current
Vas = -15V, TA = 25°C
Vos =
VGS(OFF)
Gate-Source Cutoff
qv
TA = 125°C
0.2
0.2
0.2
nA
0.5
0.5
0.5
IJA
V
Vos = 15V, 10 = 1 nA
0.5
1.1
0.7
.1.6
1.2
2.7.
Vos = 15V, V GS = OV,
Pulsed 300IJs ::; 2%
1.0
12
4.0
20
10
40
Voltage
loss
g"
Saturation Drain Current
Common-Source
Transconductance
gos
Voa=15V
10 = 0.5 rnA
3.5
5
10 ~ 2 rnA
3.5
5
3.5
4.5 .
7.5
9
7.5
9
rnA
mmho
mmho
Voa = 15V, 10 = 0.5 mA
5
25
5
25
5
25
).
Quad SPST
200·600
'200
"200
'200
'200
'200
'250
'250
"250
'250
"250
260 '
B50
"100
"100
'150
·150
"3D
'75
200·600
flO
±10
±10
flO
±10
±10
flO
±10
±10
±10
±10
±7.5
f7.5
15mA
lOrnA
SmA
3mA
±7.5
±10
±10
PART
NUMBER
LOGIC
INPUT
AH01411DG141
AHOI33/DGI33
AH0134/DG134
AH01511DG151
AHOI52/DGI52
AM1BI/DG1BI
AM 1B2/DG 1 B2
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Vs
(VI
TYP
-lB. 12
-lB. 12
-lB. 12
f15
±15
f15.5
±lS.5
tON/tOFF
TYP
O.B/l.l~'
0.5/0.9",
0.5/0.9~,
0.BI1.1~'
0.5/0.9~,
180/150 ns
300/150 ns
RON
Inl
SPOT
10
30
BO
15
50
ioo
"30
"75
AH5015
AH5016
MM455/MM555
AHOO15
LF11201
LFl1202
LF11331
LF11332
LF11333
LF13201
LF13202
LF13331
LF13332
LF13333
CD4066
CD4016
AH5011/AM9711
AM97Cli
AH5012/AM9712
AM97C12
AM193
AMI94
MM452/MM552
15VTTL
TTL
PMOS
-20,10,5
TTL
±15
TTL
±15
TTL
±1S
TTL
±tS
TTL
±tS
TTL
TTL
±15
,15
TTL
TTL
±15
TTL
±15
TTL
±15
CMOS ::!:7.5
CMOS ±7.5
15V TTL
CMOS
TTL
CMOS
±15.5
TTL
±15.5
TTL
PMOS
150/300 ns
150/300 n,
100/400 ns
90/500 ns
90/500 ns
901500 ns
90/500 ns
90/500 ns
90/500 ns
90/ElDO ns
90/500 n, .
90/500 ns
90/500 ns
150/300 ns
150/300 ns
150/300 ns
150/300 ns
1801150ns
3001150 ns
150/300 ns
PART
NUMBER
LOGIC
INPUT
TTL
TTL
TTL
TTL
TTL
±7.5
AH0146/DG146
AHOI44/DGI44
AH0143/DG143
AH01611DG161
AHOI62/DGI62
AH2114(Sw.11
(Sw.21
AM1B7/DG1B7
ilO
VAil
(VI
Vs
(VI
TVP
tON/tOFF
TVP
±7.5
±7.5
"9
TriploSPDT
2BO
±7.5
-lB. 12
-18.12
-IB,12
f15
VAil
(VI
PART
NUMBER
Vs
(VI
TVP
LOGIC
INPUT
tON/tOFF
TVP
±15
15VTTL ±15
AM188/DG188
TTL
TTL
±15,5
AM190/DG190
AM1911DG191
TTL
TTL
±tS,5
±1S,5
±tS,5
CD4053
CMOS
±7.5
±7.5
±10
AH0140IDG140
AHOI29/DGI29
AHOI26/DGI26
AHOI53/DGI53
AH01S4/DGI54
AHOO19
AMI B4/DG 1B4
AM165/DG185
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
-18,12
-18,12
-18,12
±15
±15
-20,10,5
±15.5
::!:15.5
±10
±10
±10
±7.5
17.5
flO
AHOI45/DGI45
AHOI39/DGI39
AHOI42/DG 142
AHOI63/DG 163
AH0164/DG164
AHOO14
TTL
TTL
TTL
TTL
TTL
TTL
-IB,12
-18.12
-18,12
±15
=15
-20,10,5
0.B/1.1",
0.5/0.9~,
0.5/0.9",
O.B/l.l",
0.5/0.9",
35/600 ns
1.2Jls/50 ns
180/150 ns
3001150 ns
lBO/150 ns
3001150 ns
Dual DPST
DPDT
10
30
80
15
50
200·600
Inl
MULTIPLEXERS
flO
:!:10
flO
Dual SPOT
"3D
±7.5
"75
±10
10
30
BO
15
50
200·600
"30
"75
RON
±10
±10
±10
±7.5
=7.5
::;10
Notes:
RON max@TA = 25"C
VAll = maximum voltage or current to be safely switched
Part number = basic number/alternate number (j.e., AM181/DG181). May be ordered by either number.
* Preferred devices
0.BI1.1~,
O.5/0.9J.Ls
0.5/0.9",
0.BI1.1"s
0.5/0.9~,
100/400 ns
1801150 ns
300/150 ns
0.8/1.1ps
0.5/0.9ps
0.5/0.9}J.s
O.8/1.1J.Ls
0.5/0.9I1s
350/400 ns
2·Channel Differential
±lO
200·600
MM450/MM550
PMOS
15VTTL
TTL
150/300 n,
150/300 ns
150/300 ns
150/300 ns
150/300 ns
150/300 n5
3·Channel
"100
"150
4-Channel
*100
"100
"150
·,50
200·600
lSmA
AH5013
5mA
AH5014
lSmA
lOrnA
5mA
3mA
AH5009/AM9709
AM97C09
AH501 0/ AM971 0
±10
MM4511MM551
15VTTL
CMOS
TTL
CMOS
PMOS
CD4052
MM454/MM554
LF11509
CMOS ±7.5
PMOS -24,12
±15
TTL
4·Channel Differential
260
±7.5
200·600
±10
"350
12,-15
AM97Cl0
1I0.7P'
6-Channel
250·1500
50mA
AM2009/MM45041
MM5504
TTL
,
a·Channel
250400
"350
±5
12,-15
AM3705
LF1150B
TTL
TTL
-15,5
±15
1/0.7P'
a·Channel Differential
"350
12,-15
LF11507
TTL
±15
1/0.7P'
16·Channel
"350
LF11506
TTL
±15
1/0.2I1S
12,-15
I
I
!
ap!nD UO!IOalas S9l101!MS 60leU"
Definition of Terms
Driver Leakage Current: The sum' of the currents into
the source and drain switch terminals, with both held·
at the same specified voltage.
Switch Leakage Current: The current seen when a
specified voltage is applied between drain and source
of a channel that is logically turned off.
Switch 'iON" Resistance: The equivalent resistance
from source to drain, tested by forcing a specified
current and measuring the resultant voltage ~rop.
Logic "1" Input Voltage: The voltage level which is
guaranteed to be interpreted by the device as a logical
"true" signal.
Logic "0" Input Voltage: The voltage level which is
guaranteed to be interpreted by the device as' a logical
'''false'' s i g n a l . '
.
Switch Turn, "OFF" Time: The interval between the
time that the logiC input passes through the threshold
voltage 'and the time that the output goes'to a specified
voltage.level in the test circuit.
Logic Input Slew Rate: "Fhe voltage difference between
the logic "1" and logic "0" states divided by the transi·,
tion time.
Switch Turn "ON" Time: The interval between the time
that the logic input passes through the threshold voltage
and the time that the output goes to 90% of its final
value in the specified test circuit.
5·4
~
AH0014/AH0014C* DPDT, AH0015/AH0015C Quad SPST,
AH00191 AH0019C* Dual DPST-TTl/OTl Compatible
MOS Analog Switches
General Description
This series of TTLlDTL compatible MOS analog
switches feature high speed with internal level
shifting and driving. The package contains two
monolithic integrated circu it chips: the MOS ana·
log chip is similar to, the MM450 type which
consists of four MOS analog switch transistors;
the second chip is a bipolar I.C. gate and level
shifter. The series is available in both hermetic
dual·in·line package and flatpack.
Fully compatible with DTL or TTL logic
II
Includes gating and level shifting
These switches are particularly suited for use
in both military and industrial applications such
as commutators in data acquisition systems, multi·
plexers, AID and D/A converters, long time
constant integrators, sample and hold circu its,
modulators/demodulators, and other analog signal
switching applications. For information on other
National analog switches and analog interface ele·
ments, see listing on last page.
Features
Large analog voltage switching
±10V
Fast switching speed
500ns
a Operation over wide range of power supplies
II
The AH0014, AH0015 and AH0019 are specified
for operation over the _55°C to +125°C military
temperature range, The AH0014C, AH0015C and
AHOOl9C are specified for operation over' the
_25°C to +85°C temperature range.
II
III
II
Low ON resistance
.. High OFF resistance
Block and Connection Diagrams
Order Number AH0014F or AH0014CF
See Package 23
QuadSPST
A~Al~G
Order Number AH0014D or AH0014CD
See Package 14
Dual DPST
r--------,
11:
.~~!~~
.r--------i
"'L"G~~'~ALOG
'"I\~IOUTI
~~:;\OG
~~A\~~~:~:~OG
.N.~~~~:~:~DD
"'LDG~I::I
I."
I
I
ANA\:;+
."~;~;
l 1: I:
~:~aG
I
,"
~~:~OG
l:~~l_;~"",,__,.::~_~.,_,~
..
,
, L-T-T-T-:F-J
IAAAAE~;
lo,"e'LDtlcl
•I
LD"nLO~ICl
Note< Alllogtc mpLlfS shown al logIc "1."
II
Order Number AH0015D or AH0015CD
See Package 15
82
DIP "d FI","k, All
shown at logic "1."
Order Number AH0019F or AH0019CF
See Package 23
Order Number AH0019D or AH0019CD
See Package 14
Typical Applications
Reset Stabilized Amplifier
·PreviouslV called NHO,OI4/NHOOI4C and NH0019/NHOOI9C
5·5
I"" m,,"
*
o
0')-
8:r::
~
'"
,....
8
:r::
0')
Absolute Maximum Ratings
Vee Supply Voltage
v- Supply Voltage
v+ Supply Voltage
v+ IV- Voltage Differential
Logic Input Voltage
Storage Temperature Range
Operating Temperature Range
AH0014, AH0015, AH0019
AH0014C, AHoo15C, AH0019C
Lead Temperature (Soldering, 10 sec)
7.0V
-30V
+30V
40V
5.5V
_65°C to +150°C .
. _55°C to +125°C .
-25°C to +85°C
300°C
~
o
Electrica.1 Characteristics
(Notes 1 and 2)
U')
o
o
PARAMETER
CONDITIONS
MIN
:r::
Logical "I" Input Voltage
Vee = 4.5V
Logical "0" Input Voltage
Vee = 4.5V
U')
'"
,....
o
o:r::
Logical "I" Input Current
Vee = 5.5V
Logical "I" Input Current
Vee = 5.5V
V ,N = 5.5V
Logical "0" Input Current
Vee = 5.5V
V ,N = O.4V
Power Supply Current Logical "I"
Input - each gate (Note 3)
Vee = 5.5V
V ,N
Power Supply Current Logical "0"
Input - each gate (Note 3)
AHOOl4, AHOOl4C
AHOOl5, AHOOl5C
AHOOl9, AHOOl9C
Vee = 5.5V
V ,N = OV
.Analog Switch ON Resistance - each gate
V ,N (Analog) = +10V
V ,N (Analog) = -IOV
~
~
o*
~
,....
o
o
:r::
~
~
8
:r::
~
AHOOl4C, AHOOl5C, AHOOl9C
Analog Switch Output Leakage
Current - each output (Note 4)
AH0014, AHOOl5, AHOOl9
AHOOl4C, AH0015C, AHOOl9C
MAX
2.0
V ,N = 2.4V
= 4.5V
I
UNITS
V
0.8
V
5
/lA
I
mA
0.2
0.4
mA
0.85
1.6
mA
1.5
0.22
0.22
3.0
0.41
0.41
mA
mA
mA
75
150
Analog Switch OFF Resistance
Analog Switch Input Leakage Currenteach input (Note 4)
AHOOl4, AH0015, AHOO19
TYP
200
600
n
n
.n
10"
V ,N = -10V
TA = 25°C
TA = 125°C
25
25
200
200
pA
nA
TA = 25°C
T A =70°C
0.1
30
10
100
nA
nA
40
40
400
400
pA
nA
0.05
4
10
50
nA
nA
V OUT = -10V
TA = 25°C
TA = 125°C
TA = 25°C
TA = 70°C
Analog Input (Drain) Capacitance
1 MHz
@
Zero Bias
8
10
pF
Output Source Capacitance
1 MHz
@
Zero Bias
11
13
pF
Analog Turn·OFF Time - tOFF
See test circuit; T A = 25°C
400
500
ns
Analog Turn·ON Time - tON
See test circuit; T A
350
100
100
425
150
150
ns
ns
ns
<:::
25°C
AHOOl4, AHOO14C
AH0015, AHOO15C
AH0019, AHOOl9C
Note 1: MinImax limits apply across the guaranteed temperature range of _55°C to +12SoC for
AH0014. AHOOIS. AHOO19 and -2S"C to +8S"C for AHOO14C. AHOOISC. AH0019C. V", -20V.
V+ = +10V and an analog test current of 1 rnA unless otherwise specified.
Note2: All typical values are measured at TA::: 25Q C with Vee = 5.0V. V+ '" +10V, V~ '" -22V.
Note 3: Current measured IS drawn from Vee supply.
Note 4: All analog switch pms except measurement pm are tied to V+,
5·6
l>
Analog Switch Characteristics
RON
V5
Temperature
125
VIN
""w
u
z
~
:1l
'"
i.
F
15
50
~
--
-
V"
./
!
100
u
15
""w
z
~
25
25"
65°
I'
IL
225
/
w
u
z
~
25
~
150
F
125
_IS"
25"
65"
'" IOV
«
CHANNEL "ON" - CHANNEL "ON"V-'-20V - -V-o-OV
-
w
-z
'"~
~
;'"
10
25
::!
::t
-25
0
ANALOG
,..
CIt
........
-55"C
I-
Schematic (Single Driver Gate
'"
o
o....
:!i
ANALOG VIN (V)
.,...'~.
"
::t
v-· -22V
V'· B.OV
125"C
co
co
::;
~
-50
+10
0 +2 +4 +6 +8 +10
l>
IDS"
Vee" 5.0V
+5
0
'"
-15
I
-10 -B -6 -4 -2
65"
+10
co
>
w
>
a;
w
5
w
'"
::t
o
,..
,
,
"~
,
,
'"
o
....o,r:.
o
*
AMBIENT TEMPERATURE I"CI
Leakage vs VIN (Channel "OFF")
50
20
Vl/
100 ""'"
_55"
IDS"
IL
V
AMBIENT TEMPERATURE rCI
CIN vsVIN
v~
115
i.
AMBIENT TEMPERATURE I"CI
l>
::t
:§
50
0
_55"
IDS"
~
v,~. ~ou,l. -I~V
~ 200.
z
F
0
_55°C . _IS"
-
-
~
9
RON vs Temperature
V~N • ~ou,l. oJ
=V OUT '" +,I ov
100
o
RON vs Temperature
125
]
::t
(Note 2)
-5
-10
-15
-20
-25
9
CO
o
*
U)
Q)
'i:
Q)
U)
oCD
,..
o
J:
:t:
Absolute Maximum Ratings
. High
9
Medium
Level
Level
Total Supply Voltage (V+ - V-I
Analog Signal Voltage (V+ - V A or V A - V-I
36V
30V
34V
25V
Positive Supply Voltage to Reference (V+ - VAl
Negative Supply Voltage to Reference (V A - V-I
25V
22V
25V
±6V
25V
22V
25V
±6V
N
",0
»
9
:t
Positive Supply Voltage to Input (V+ - VINI
Input Voltage to Reference (V IN - VAl
±6V
±6V
Differential Input Voltage (V IN - V IN2 )
30mA
30mA
Input Current, Any Terminal
Power Dissipation
See Curve
_55°C to +125°C
Operating Temperature Range
AH0100 Series
_25°C to +85°C
AH0100C Series
_65°C to +150°C
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
300°C
Electrical Characteristics
Logic "'"
Input Current
SYMBOL
DUAL
DPST
DUAL
SPST
DPDT
IDIFFI
CONDITIONS
IIN(OFFI
All Circuits
Note 2
All CIrcuits
One Driver ON Note 2
,
Negative Supply
Current Switch ON
I-'ON)
All CirCUits
One Driver ON Note 2
Reference Input
(EnaDle) ON Current
IRIONI
All CirCUits
One Dnver ON Note 2
'+'OFF}
All Circuits
POSitive Supply
Current SWitch OFF
LIMITS
v+ = 12.0V. V-::::: -lB.OV. V R ::: o\.OV
Note 2
'''(ON)
V 1N1
"'
V 1N2 == 0
av
TA
"
25'C
T.
0
25°C
TA ~ 25°C
"
25°C
SWitch ON Resistance
rds(ONI
AH0126
AH0134
AH0142
AH0143
Vo'" tOV
10 =. 1 mA
Over Temp. Range
SWitch ON Resistance
rdslONI
AH0129
AH0133
AH0139
AH0144
Vo = lOV
10:: 1 mA
Over Temp. Range
SWitch ON Resistance
rds(ONI
AH0140
AH0141
AH0145
AH0146
Vo" 10V
IF":: 1 mA
Over Temp. Range
, Driver Leakage Current
All CIrcuIts
(10 + 'SION
Switch Leakage
'SIOFF) OR
Current
IOIOFFI
SWitch Leakage
Current
ISIOFFIOR
SWitch Turn-ON Time
tON
,
Vo=Vs=-lOV
AH0126
AH0129
AH0134
AH0133
AH0142
AH0139
AH0143
AH0144
Vas:= ±20V
AH0140
AH0141
AH0145
AH0146,
V os " ±20V
AH0126
AH0129
AH0134
AH0133
AH0142
AH0139
AH0143
AHOl44
'OIOFFI
SWitch Turn·ON Time
tON
AH0140
AH0141
AH0145
AH0146
SWitch Turn·OFF Time
tOFF
AH0126
AH0129
AH0134
AH0133
AH0142
AH0139
AH0143
AH0144
,Switch Turn-OFF Time
V IN1 ::: V IN2 " O.8V
tOFF
AH0140
AH0141
AH0145
AH0146
rnA
rnA
-1.0
-1.B
2.0
",A
rnA
-1.0
-1.4
1.6
rnA
rnA
1.0
10
25
~A
-1.0
-10
-25
~A
-1.0
-10
-25
~A
45
BO
150
25
30
. 60
B
10
20
n
n
n
n
n
n
1
100
nA
nA
1
100
nA
nA
Over Temp. Range
TA
"
25°C
Over Temp Range
T A =2SQ C
TA '" 2SoC
TA ·2jioC
' TA= 2SoC
Over Temp. Range
TA '" 2SoC
.01
0.8
Over Temp. Range
TA= 2SoC
4
Over Temp. Range
~A
~A
~A
~A
nA
10
1.0
~A
See Test Circuit
T A ::= 2SoC
0.5
0.8
~s
See Test Circuit
T A,=2SQ C
VA:=±IOV
O.B
1.0
~s
See Test Circuit
TA= 2SoC
0.9
1.6
~s
See Test Circu It
TA= 2SoC
VA'" ±10V
1.1
2.5
~$
VA = ±10V
VA = tl0V
Not8 1: Unless' otherwise specified these limits apply for -55°C to +12SoC for the AH0100 series
and -25°C to +85°C for the AH0100C series. All typical values are for T A = 25°C.
Note 2: For the DPST and Dual DPST, the ON condition IS for VIN '= 2.SV; the OFF condition
is for VIN = O.8V. For the differential switches and SWI and 2 ON, VIN2 = 2.SV, V,Nl = 3.0V,
For SW3 and 4 ON, VIN2 = 2.5V, VINI = 2.0V.
5·9
3.0
3.3
Over Temp Range
TA ·25°C
~A
2.2
Over Temp Range.
TA
~A
~A
Over Temp Range
TA '" 2SoC
60
120
o......
(J1
MAX
.1
2.0
Over Temp. Range
IA(OFFJ
All CirCUits
01
Over Temp. Range
Reference Input
(Enable) OFF Current
V IN1 '" V IN2 ~ O.BV
2.0
TA "'2SoC
I-(OFFI
All Circuits
TYP
Over Temp. Rangp
Negative Supply
Current SWitch OFF
:
l>
:t
UNITS
SPOT
IDIFFI
All CircUits
Positive Supply Current
Switch ON
~
...o
'INION)
Logic "0"
Input Current
»
9
:t
for "HIGH LEVEL" Switches (Note 11
DEVICE TYPE
PARAMETER
til
P
9
J>
:r.:
o......
0')
o
(f)
...arCD
en
rJ).
CD
".:
CD
U)
o
CO
o
~
Electrical Characteristics
:J:
2,5V). The V A terminal can be driven from most
TTL and DTL gates.
A. Voltage Considerations
In general, the AH0100 series is compatible with
most DTL, TTL, and RTL logic families. The ONinput threshold is determined by the VBE of the
input transistor plus the VI of the diode in the
emitter leg, plus I x R,. plus VA. At room
temperature and V A ~ OV, the nominal ON threshold is: 0.7V+0. 7V+0.2V, ~ 1.6V.Over temperature
and manufacturing tolerances, the threshold may
be as high as 2.5V and as low as o.av. The rules
for proper operation are:
V IN - VA
~
3. DIFFERENTIAL INPUT CONSIDERATIONS
The differential switch driver is essentially a differential amplifier. The input requirements for proper
operation are:
iVIN1 - VIN2i2:0.3V
2.5V All switches ON
2.5 -:::: (V IN1 or V IN2 ) - VA -:::: 5V
V IN - VA::; o.av All switches OFF
~
The differential driver may be furnished by a DC
level as shown below. The level may be derived
from a voltage divider to V· or the 5V Vee of
the DTL logic. In order to assure proper operation,
the divider should be "stiff" with respect to IIN2'
Bypassing Rl with a 0.1 /IF disc capacitor will
prevent degradation of tON and tOFF'
o
:I:
«
o
('t)
,....
o
.,
~
:I:
«
o
N
,....
o
:I:
«
B. Input Current Considerations
IIN(ON), the current drawn by the driver with
VIN ~ 2.5V is typically 20 /lA at 25°C and is guar·
anteed less than 120 /lA over temperature.' DTL,
such as the DM930 series can supply 180 /lA at
logic "1" voltages in excess of 2.5V. TTL output
levels are comparable at 400 /lA. The DTL and
TTL can drive the AH0100 series directly. However, at low temperature, QC noise margin in the "
logic "1" state is eroded with DTL. A pull·up resistor of ·10 kn is recommended when using DTL'
over military femperature range.
Alternatively, the differential driver may be driven
from a TTL flip-flop or inverter.
'" ~-~
O"'M'~
v...
-
---
~
If more than one driver is to be driven by a DM930
series (6K) gate, an external pull-up resistor should
be added. The value is given by:
Rp
~
,
11
N _ 1 for N > 2
~
value of the pull-up resistor in kn
N ~ numb~r of drivers.
C. Input Slew Rate
The slew rate of the logic input must be in excess
of 0.3V l/ls in order to assure proper operation of
the analog switch. DTL, TTL, and RTL output
rise tim,es are far in excess of the minimum slew
rate requirements. Discrete logic designs, however,
should include consideration of input rise time.
'2. ENABLE CONTROL
The application of a positive signal at
-:::
y-
v, ••
1160"';"'1)4
-
--~
-=-
-r
Connection of almA current source between V A
and V- will allow operation over a ±10V common
mode range. Differential input voltage must be less
than the 6V breakdown, and input threshold of
2.5V and 300mV differential overdrive still prevail.
where:
Rp
-
~'"
'---
~he
VA
5·12
4. ANALOG VOLTAGE CONSIDERATIONS
The rules for operating the AH0100 series at
supply voltages other than those specified essen·
tially breakdown into OFF and ON considerations.
The OFF considerations are dictated by the maxi·
mum negative swing of the analog signal and the
pinch off of the. JFET switch. In the OFF state,
the gate of the FET is at V- + Vee + VSAT or
about 1.0V above the V- potential. The maximum
Vp of the FET switches is 7V. The most negative
analog voltage, V A, sWing which can be accomo·
dated for any given supply voltage is:
Iv A 1<:: IV-I- Vp
-
VA <:: V+ - 2.0V or V+
?:. VA + 2.0V
For the standard high level switches, V A = 12 2.0V = +10V.
5. SWITCHING TRANSIENTS
Due to charge stored in the gate-to-source and
gate-to-drain capacitances of the FET switch, transients may appear in the output during switching.
This is particularly true during the OFF to ON
transition. The magnitude and duration of the
transient may be minimized by making source
and load impedance levels as small as practical.
Vee - VSAT or
Iv AI~IV-I-8.0 or IV-I~IV AI+8.0V
For the standard high level switches, VA <1- 181
·+8 = -lOV. The value for V+ is dictated-by the
maximum positive swing of the analog input voltage. Essentially the collector to base junction of
the turn-on PNP must remain reversed biased for
all positive value of analog input voltage. The base
of the PNP is at V+ - VSAT - Vee or V+ - 1.0V.
The PNP's collector base junction should have at
least 1.0V reverse bias. Hence, the most positive
analog voltage swing which may be accommodated
for a given value of V+ is:
Furthermore, transients may be minimized by
operating the switches in the differential mode;
i.e., the charge delivered to the load during the
ON to OFF transition is, to a large extent, can·celled by the OF F to ON transition.
Typical Applications
Programmable One Amp Power Supply
lE~O
ADJ~T
VOUT - (! Polarity) lC (BCD Code) II V~EF
~
nlIOTl~CDIt.lPun
lOUT - 2A peak, lA contmuous
VOUT Range - ,.12V
Full Scale AcqulsLtlon T,me-8/J5
Four to Ten Bit 0 to A Converter (4 Bits Shown)
A~AlO~
OUTPUT
'"'"
SettmgTlme:l.us
Accuracy: 0.2%
*Note: All reslstonareO.l%
5-13
en
G)
";:
Typical Applications
(Continued)
G)
Four Channel Differential Transducer Commutator
U)
~
o
•F'U---'
a1'. I,
n,iUlSDUClll
...
{
,
11101
~O--+:~IC-'++--""'-+"'i
r' ",,",p-.,.;(.I:
I,
o
o
...-r. I.
.1
,,1/
1llgllHltlll{ 00------"''-0'" .
~
:r:
nA
100
-10
-200
-250
-250
10
20
(X)
~
~
»
)lA
s:
....
ns
9'
Voltage Low
IINH
Input Current. Input
'ON
Turn "ON" Time
tOFF
Turn "OFF" Time
VIN = SV
Voltage High
0)
ISO
180
See Switching Time Test Circuit
130
Vec = lSV, VEE
Drain-Source
=-15V, VL ': 5V, VR = 0
IS = -10 mA, VIN = O.BV
Vo =-10V
150
MAX LIMITS
TEST CONDITIONS, UNLESS NOTED:
PARAMETER
'OSION)
AM182
AM282
UNITS
-55°C
25°C
125'C
-20°C
25'C
85°C
75
75
100
100
100
150
1
100
5
100
n
"ON" Resistance
IS(OFF)
Source "OFF"
Vs = 10V, Vo = -lOV,
Leakage Current
Vee = IOV, VEE = -20V
Drain "OFF"
IOIOFF)
VIN = 2V
Leakage Current
Channel "ON"
ID(ON) + IS(ON)
s:
-'"
VIN = O.BV·
Vs = lOV, Vo = -10V
I
100
5
100
VD=10V,VS= 10V,
Vee = 10V, VEE = -20V
I
100
5
100
VD - 10V, Vs - -WV
1
100
5
100
-2
-200
-250
-250
10
20
»
s:
....
0)'
~
nA
VO=VS=-10V
-10
-200
-250
-250
10
20
Leakage Current
Input Current, Input
IINL
-250
VIN =0
-250
Voltage Low
I nput Current. Input
IINH
VIN
)lA
=5V
Voltage High
tDN
Turn "ON" Time
tOFF
Turn "OFF" Time
250
300
130
150
ns
See Switching Time Test Circuit
PARAMETER
CS(OFF)
Source "OFF" Capacitance
CO(OFF)
Drain "OFF" Capacitance
COlON) + eSION)
Channel "ON" Capacitance
ICC
Positive Supply Current·
"OFF" Isolation
lEE
Negative Supply CUrrent
IL
Logic Supply Current
IR
Reference SupplV Current
ICC
Positive Supply Current
TEST CONDITIONS, UNLESS NDTEO:
VCC
=15V, VEE = -15V, VL = SV, VR =0
t= 1 MHz
RL = 75
MAX LIMITS
AM181, AM182
-5S'C
2S'C
VS=-5V,IO=0
9 Typical, {Note 1)
VD=-5V.IS=0
6 Typical, (Note 1)
VO=VS=O
14 Typical, (Note 1)
0.1
-5
='
UNITS
pF
CD
en
0.1
-5
0, All Channels "ON"
4.5
-2
4.5
-2
rnA
lEE
Negative Supply Current
IL
logic Supply Current
IR
Reference SupplV Current
0.1
-5
Both VIN
='
0.1
-5
5V. All Channels "OFF"
4.5
-2
Note 1: Typical values are for Design Aid only. not guaranteed and not subject to production testing.
5-19
4.5
-2
CJ)
CD
::!.
> 60 dB at 10 MHz Typical, (Note 11
n
Both VIN
AM281, AM282
I
12SoC I-20°C 25°C 185°C
Electrical Characteristics AM184/ AM284, AM185/AM285
dc parameters are 100% tested at 25°C; ac parameters, high and low temperatures, and tON, tOFF are sampled to ensure
conformance with specifications.
PARAMETER
Drain-Source
'os ION)
TEST CONDITIONS, UNLESS NOTED:
. VCC = 15V, VEE = -15V, VL • 5V, VR. = 0
IS=-lO mA, VIN = 2V Vo =-7.5V
MAX LIMITS
AMI84
-55·C 25·C
30
125·C
-20·C
AM284
25·C
85·C
UNITS
30
60
50
50
75
1
100
S
100
n
ON Resistance
ISIOFF)
oCJ)
,..
Source OFF
Vs = 10V, VO' -lOV,
leakage Current
VCC = 10V, VEe = -20V
Vs = 7.5V, Vo
Drain OFF
10IOFF)
:::i
6q dB at 10 MHz Typical. (Note 1)
n
0.1
-4
Boih Y,N = SV, AJI Channels "ON"
4.5
-2
0.1
-4
4.5
-2
Current
,
ns
mA
0.1
0.1
-5.5
-5.5
Both Y,N = 0, All Channels "OFF"
4.5
-2
Current
Note 1: Typical values are for Design Aid only, not guaranteed and not subject to production testing.
5·20
4.5
-2
Electrical Characteristics AM187/AM287, AM188/AM288
dc parameters are 100%' tested at 25°C; ac parameters, high' and low temperatures, and tON, tOFF are sampled to ensure
conformance with specifications.
MAX LIMITS
TEST 'CONDITIONS. UNLESS NOTED,
PARAMETER
AM187
VCC" lSV. VEE" -lSV. VL" SV. VR" 0
Drain-Source
'OSION}
"ON" Resistance
IS'" -10 rnA, V,N '" 2V, Ch. 1 "ON:',
VIN" O,BV. Ch, 2 '"ON'"
Source "OFF"
ISIOFF}
L.eakage Current
IOION}
+ ISloN}
IINl
12S"C
-20"C
2S"C
8S"C
30
30
60
SO
50
75
1
100
5
100
Vs - 7,SV. Vo - -7,5V
1
100
5
100
= 10V. Vs = -10V.
1
100
5
100
1
100
5
100
-2
-200
-2S0
-2S0
10
20
Vo
Leakage Current
VCC = lOV. VEE = -20V
Vo - 7,SV. Vs = 7,SV
VIN = 2V. Ch, 1 '"ON'"
Leakage Current
VIN = O.BV, Ch 2 '"ON'"
Input Current. Input
VIN = 0
11
VCC" 10V. VEE = -20V
Dram "OFF"
Channel "ON"
UNITS
2S"C
VS" 10V, VO" -10V.
VIN" 2V. Ch, 2 '"OFF'"
VIN = O.BV. Ch, 1 '"OFF'"
IDIOFF}
VO" -7,5V
AM287
-5S"C
Vo = VS" -7,SV
-2S0
-2S0
-10
-200
-250
-250
10
20
nA
VOltilgc Low
pA
Input Current, Input
'INH
VIN =5V
Voltage High
tON
Turn "ON" Time
tOFF
Turn "OFF" Time
150
180
130
lS0
n,
See SWitching Time Test CirCUit
MAX LIMITS
TEST CONDITIONS. UNLESS NOTED,
PARAMETER
AM1BB
Vee = 15V. VEE"" -15V, VL "'" 5V. VR "" 0
fOS(ONI
ISloFF}
Draln·Source
IS'" -10 rnA. Y,N "" a.BV, eh. 2
"ON" ReSistance
'"ON'". VIN = 2V, Ch, 1 '"ON'"
Source "pFF"
Vs = 10V. Vo = -10V.
Leakage Current
VCC" lOV. VEE = -20V
Drain "OFf"
IO(OFF}
Vo "-10V
+ ISloN}
IINL
25°C
125°C
7S
7S
lS0
1
UNITS
-20"C
2S"C
B5°C
100
100
150
100
S
100
VIN = O.BV. Ch, 1 '"OFF'"
VS-l0V.VO-
1
100
5
100
VIN = 2V. Ch, 2 '"OFF'"
Vo = 10V, Vs = -tOY.
VCC = lOV, VEE = -20V
1
100
5
100
Vo - lOV, VS-
1
100
5
100
-2
-200
-250
-250
10
20
• Leakage Current
IO(oN}
AM2BB
-5S"C
Channel "ON"
Y,N = 2V, eh. 1 "ON"
Leakage Current
VIN·· a 8V. Ch, 2 '"ON'"
[nput Current, Input
VIN=O
10V
lOV
VO=VS=-10V
-2S0
-250
-10
-200
-250
-2S0
10
20
11
nA
Voltage Low
[nput Current, Input
IINH
VIN
= SV
"p.A
,
Voltage High
tON
Turn "ON" Time
tOFF
Turn "OFF" Time
250
300
130
150
n,
See SWitching Time Test CircUit
MAX LIMITS
TEST CONDITIONS, UNLESS NOTED:
PARAMETER
VeC" lSV, VEE" -15V, VL" 5V. VR = a
CS(OFF}
Source "OFF" Capacitance
COloFF}
Drain "OFF" Capacitance
COlON}
+ CSloN}
f= 1 MHz
Channel "ON" Capacitance
"OFF" IsolatIOn
ICC
POSitive Supply Current
lEE
Negative Supply Current
Il
LogiC Supply Current
IR
Reference Supply Current
ICC
POSitive Supply Current
AM187, AM188
-5S"C
2S"C
I
AM2B7, AM2BB
I 12S"C L-20"C L25"C
Vs " -5V, 10 = a
9 TYPical, (Note 1)
Vo = 5V, IS= a
6 TYPical, (Note 1)
VO=VS=O
14 Typical, (Note 1)
pF
> 60 dB at 10 MHz Typical, (Note
Rl" 7SI1
0,1
-3
VIN" O. Ch, 2 "ON'", Ch, t '"OFF'"
3,2
-2
U~ITS
Bs"e
1)
0,1
-3
3,2
-2
rnA
lEE
Negative Supply Current
IL
Logic Supply Current
IR
Reference Supply Current
0.1
-3
0,1
-3
VIN = 5V, Ch. 2 '"OFF'", Ch, 1 '"ON'"
3,2
-2
Note 1: Typical values are for Design Aid only, not guaranteed and not subject to production testing.
5·21
3.2
-2
tn
Q)
'':
Q)
CJ)
Electrical Characteristics AM1901 AM 290, AM1911 AM291
dc parameters are
100%
tested at
25°C;
'OSION)
ISIOFF)
,...
co
CO
,...
~
tance
"ON", Y,N =O.BV. Gh. 3and 4 "ON"
IOION) + ISION)
IINL
12SoC
-20°C
AM290
2SoC
8S"C
30
60
SO
50
75
1
100
S
100
AM190
--55°C 2S"C
= -lSV, VL = SV, VR = 0
Drain-Source
Vo =-7.SV
30
Source OFF
Vs = 10V, Vo = ~10V,
Leakage Current
VCC = 10V, \lEE = -20V
Drain OFF
leakage Current
IOIOFF)
:E
60 dB at 10 MHz Typical, (Note 1)
RL = 75 n
0.1
-S
VIN = 0, Ch. 3 and 4 "ON", Ch. 1 and 2 "OFF"
4.5
-2
0.1
-5
4.S
-2
Current
rnA
ICC
lEE
IL
IR
Positive Supply Current
0.1
-
Negative Supply Current
' Logic Supply Current
VIN
= 5V, Ch. 3 and 4
"OFF", Ch. 1 and 2 "ON"
'.
Reference Supply
Current
Note 1: Typical values are for Design Aid only, not guaranteed and not subject to production testing.
"
5-22
-5
4.5
-2
0.1
-5
4.5
-2
Typical Performance Characteristics
Vcc = 15V, VEE = --:15V, VL = 5V, VR = 0 unless otherwise noted.
Typical delay, rise, fall, settling
times, and switching transients in
this circuit.
Capacitance vs Vo or Vs
rOSION) vs Vo and
Temperature
~ 1~~
t=
20
'"'
z
Vs -VA IMAXI
80
10 [-ID"'-lOmA
_
60
50
0:
Z
40 1-200 SERIE~
i
f'
~
30
~
z
20
;;:
~
~
..... ~ ~~IES
:...-
-
~
~
O
~
16
14
~
'"'z
;::
<:;
12
.- C~IONI, + COIONI
10
:1:
:3,
I
25 45 65 85 105 125
T - TEMPERATURE lOCI
140
~
o!-
110
'ON (Voo±1.5~
100
V
90
80
70
V
4
6
8 10
If RGEN, RL or CL is increased
there will be proportional in·
creases in rise and/or fall RC times.
IOIOFF) vs Temperature
VCC -IOV
VEE = -20V
Vl"5V.VR o OV
VO" -IOV
VS"IOV
1/
120
2
Vo OR Vs - DRAIN OR SOURCE VOLTAGE (VI
./
130
I
-10 -8 -6 -4 -2 0
150
~
CSIOFFI
I-- C~(o~FI
-35 -15 5
Switching Time vs Vo and
Temperature
]
I
I"'-- r-
g;
,
~ 1~55
VINl O.BV
V,NH = 2.0V
t= lMH.
18
0
,
./
V
~
t=
~
TEST LIMITS
• 100 SERIES
• 200 SERIES
V,OFF IVo 0 ±1.5VI_
~
~~
:i"c
I
'".,,
1.0
c
c
60
;>
j
lOGIC INPUT
-2
20
t- t- 1-100 SERIES I"
15
0.1
~
50
-55 -35 -15 5 25 45 65 85 105 125
~
~
g
~
~
o
~
'"'
0.01
10
....
25
0
65
45
85
105
125
J
1\
I-fL
VGEN olOV \
-5
~
T _ TEMPERATURE lOCI
T - TEMPERATURE rCI
11
I
liN vs VIN and Temperature
20
;;:
16
I-
14
3
:il
0:
0:
B
~
VINl =OV
VINH = 5V
18
fL
Supply Current vs Temperature
c
>
r--.
I..,.....
I
I-- I-- t-IINH
j--..
....
"'""
I--
I-
Il
-lEE
-IINl
~
o
~
r- t-
10
~
I
~~~
'":;'"
I-
~
0
~
12
I-
-2
VGEN 5V' \.
r- 1-1-
",
c
tT-
-l-
-IR
c
>
1/\
0
-2 t-t-VGEN=O
2
LI
II
-2
ICC
25 45 65 85 105 125
T - TEMPERATURE lOCI
-55 -35 -15 5 25 45 65 85 105 125
-6
T - TEMPERATURE rei
-8
I-'"
U
-4
-55 -35 -15 5
11 I-'"
-4
I-
(J)
CD
VGEN = -5V
""'iI
CO'
10
C/)
UOFF" Isolation vs
Frequency
Equivalent "OFF" Circuit
100
90
a;
:a
~
;=
::;
!?l
:::
f'
80
.....
60
50
30
20
10
L
~
I
I/VGEN -10V0
0.4
10
40
-5
-10
-15
VCC = 15V
VEE = -15V
VR=O
Vl = 5V
Rlo 75<>
I-VINI~~~I~lti'l
t - FREQUENCY IHzl
5·23
0.8
1.2
1.6
rn
Q)
'':;
Q)
U)
Switching Time Test Circuit
state output wit~ switch "ON". Feedthrough via gate
capacitance may result in spikes at leading and trailing
edge of output wayeform.
Switch output waveform shown for VS = constan t with
logic input waveform as shown. Note that Vs may be +
or - as per switching time test circuit. Va is the steady
0;
,....
:i
LOGIC
INPUT
Ir<10ns
tf<10 ns
6..-i-<>-...._ ....-OvO SWITCH
-- fl.o SOURCE
>--
"
1:
..
>--
-1::
.
-
f--
,
,
,
. . 1: .
Order Number
AM2009F or AM2009CF
MM4504F or MM5540F
Order Number
AM2009D or AM2009CD
I'IIM4504D or MMS504D
See Package 23
See Package 14.
Typical Applications
ANALOG INPUTS
ANALOG
OUTPUT
ANALOG
DUTPUT
TTL
INPUTS
32 Channel MUX
TTL Compatible 6 Channel MUX
5-26
(V aULK ~ OV)
Absolute Mcmimum Ratings
-30V
-35V
10.3V
50mA
0.1 rnA
Voltage on Any Source or Drain
Voltage on Any Gate
Positive Voltage on Any Pin
Source or Drain Curr~nt
Gate Current (forward direction ot zener clamp)
Electrical Characteristics
Total Power Dissipation (at T A '" 25 C1 Cl
Power Dissipation - CJch gate circuit
Operating Temperature Rang2 AM2009
AM2009C
Storage Temperature Range
Lead Temperature (Solderrng. 10 sec)
900mW
150mW
-55°C to +12SoC
- 2SoC to +8SoC
_65°C to +150°C
3000 t
(Note 1)
LIMITS
PARAMETER
CONDITIONS
UNITS
MIN
TVP
MAX
Threshold Voltage
Vas = Vas. IDs': -lilA
DC ON ReSIStance
V GS = -20V, IDs = -100pA,
TA = 25°C
150
250
n
DC ON ReSIStance
V GS = -lOV, V SB = -20V,
los = -100pA, TA = 25°C
500
1250
DC ON ReSlStJncc
V GS = -20V,l os
n
n
DC ON Resistance
Vas
= -lOV,
-1.0
-3.0
= -100pA
325
VSB = -20V,
Le~kaye
Input Leakage
Output Leakage
VGS
= -20V,
VGS
'"
Note 2
-20V. Note 2, TA ~ 2SOC
100
Vos = -20V. Note 2
Vas:= -20V, Note 2, TA "25°C
100
VSD
-:=
-20V, Note 2
Vso = -20V, Note 2, TA = 25"C
= -10.uA,
n
1500
los" -100pA
Gate
V
Gdte Bulk Bleakdown
Voltage
lOB
Source-Dram Breakdown
Voltage
Iso = -10pA''V GD = 0,
Note 2
Drain-Source Breakdown
Voltage
los = -10pA, V GS
Note 2
Note 2
-::
10
pA
pA
1.0
pA
pA
3.0
pA
pA
500
-35
V
-30
V
D.
V
-30
Transconductance
4000
mhos
Gate Capacitance
Note 3, f -,: 1 MHz
4.7
8
pF
Input Capacitance
Note 3, f = 1 MHz
4.6
8
pF
Output Capacrtance
Note 3, f :;. 1 MHz
20
pF
16
Note 1: Ratings apply over the specified temperature range and VBULK -= 0, unless otherwise specified.
Note 2: All other pins grounded_
Note 3: Capacitance measured on dual-in-line package between pin under measurement to all other pins. Capacitances are
guaranteed by design.
Typical Performance Characteristics
"ON" Resistance vs Gate-toSource Voltage
Input Leakage Current vs
Temperature
"ON" Resistance vs T
Temperature
'DO , - , . - , - , . - , - , . . - - - ,
I--JUS"-IOO.uA+-~
__ _
1",:25'C
600 1
i-
5011
Ves'" +20V
400
a:
300
'DO
f-
r------
1.1D,I1110
l
IIA
i
~::::~~vr~~rI
VIlS=DV=r~
I
I''&!y'/
I
«
~
«
F!""':==:::t=0- J . L
'00
-30
-25
-20
-15
-III
-5
TEMPERATURE 1 CI
5-27
.-
.-
111110
-
IDE
L
IO'
o
0
.-
--.:
"
50
15
11111
TEMPERATURE I'CI
125
AM370S/ AM370SC a-Channel MOS Analog Multiplexer
General Description
The AM3705/AM3705C is an eight-channel MaS
analog multiplex switch .. TTL compatible logic
inputs that require no level. shifting or input
pull-up resistors and operation over a wide range
of supply voltages is obtained by constructing the
device with low threshold P-channel enhancement
MaS technology. To simplify external logic requirements, a one-of-eight decoder and an output
enable are included in the device.
•
•
•
The AM3705/AM3705C is designed as a low cost
analog mUltiplex switch to fulfill a wide variety of
data acquisition and data distribution applications
including cross-point switChing, MUX front ends
for AID converters, process controllers, automatic
test gear, programmable power supplies and other
military or industrial instrumentation applications.
Important design features include:
a
•
..
•
..
Low ON resistance - 150Q
Input gate protection
Low leakage currents - 0.5 nA
TTL/DTL compatible input logic levels
O~eration from standard +5V and -15V supplies
Wide analog voltage range - ±5V
'
One-of-eight decoder on chip
Output enable control
The AM3705 is specified for operation over the
_55°C to +125°C military temperature range. The
AM3705C is specified for operation over the _25°C
to +85°C temperature range.
Schematic and Connection Diagrams
Dual-In-Line Package
DE
1
v~
,
,." "
"
14
OUT 3
"
V~ 4
12
5, •
"
Voo
5,
5, ,
11
~
'"
",
s,
s,.
5,
Order Number
AM3705D or AM3705CD
See Package 15
AM3705F or AM3705CF
See Package 24
'--------.".,,',,-------
Block Diagram
Truth Table
(MIL-STD-80BB)
CHANNEL
LOGIC INPUTS
CHANNElNOS
Lbbbbbbb
OOATAOUTPUT
" "
DE
ON
L
H
L
H
L
H
L
H
L
L
H
H
L
L
H
H
"
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
L
5,
5,
5,
S,
5,
5,
5,
S,
. OFF-
Typical Application
Buffered S-Channel Multiplex, Sample and Hold
2'
z·
.....'" \
OUTPUT
ENABLE
INPUTI
- - - - - - - - ·8othVsslinesaremternativ
connected; either one or
LOGIC INPUT
both mav be used.
5-28
---
Analog Signal Ringe - O.5V .
AcquisitionTime-25ns
Dllft Rite - 0.5 mVislC
Ape'ltuf! Tima - 250 ns
Absolute Maximum Ratings
Posltl\le Voltage on Any Pin (Note 1)
Negative Voltage on Any Pin (Note 1)
Source to Drain Current
+0.3V
-3SV
±30mA
to.l mA
SOOmW
-SS"C to +12S"C
-2S"C to +8S"C
-6S"C to +lS0"C
30a"C
logic Input Current
Power Dissipation (Note 2)
Operating Temperature Range AM370S
AM370SC
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Electrical Characteristics
PARAMETER
(Note 3)
SYMBOL
CONDITIONS
MIN
100 iJ,A
ON Resistance
RON
V'N = Vss; lOUT =
ON ReSistance
RON
V'N = -5V; lOUT = -100 IIA
ON ReSistance
AM370S
AM3705C
RON
ON ReSistance
RON
V'N = +5V; Voo = -15V;
lOUT = 100iJ,A
ON ReSistance
RON
VIN
ON ReSistance
RON
OFF Resistance
ROFF
Ou~put
Leakage Current
AM3705
AM3705C
I LO
I LO
I LO
Vss - V OUT == 15V
Vss - V OUT = 15V. TA = 125°C
V
V OUT =- 15V, TA == lOoe
Data Input Leakage Current
'LOI
Vss - V'N = lSV
VSS-V'N = 15V;TA = 12S"C
VSS-V'N = lSV;TA =70"C
AM370S
AM370SC
'LOI
:=
=:.
UNITS
80
2S0
160
400
n
n
400
400
n
n
+12SoC
+70°C
100
n
lOUT = -1001lA
150
n
V'N = -5V; Voo = -15V;
lOUT = -100 iJ,A
250
n
n
=
av,
Voo
-lSV,
=
10 10
0.5
150
35
ss -
0.1
2S
O.S
Logic Input Leakage Current
AM370S
AM370SC
ILl
ILl
ILl
VSS-VloQlcln=
15V
VSs-VLog!Cln=
15V;T A = 12SoC
Vss -
15V; TA
Logic I nput LOW Level
V'L
Vss = +S.OV
Logic Input LOW Level
Logic Input HIGH Level
Log'c Inpul HIGH Level
Channel Switching Time-Positive
V'L
V'H
V'H
t+
Channel Switching Time-Negative
I
-
MAX
V'N = -SV; lOUT = -100iJ,A
TA
TA
'LOI
LIMITS
TYP
VLoQlc In =
= 70
0
.001
.05
.05
e
O.S
Voo
3.0
Vss - 2.0
Vss = +S.OV
10
500
SOO
nA
nA
nA
3.0
SOO
SOO
nA
nA
nA
1
10
IIA
iJ,A
10
IIA
1.0
Vss - 4.0
3.5
Vss + 0.3
V
V
V
V
1SWitch Jng Time
300
ns
J T,es~ Circuit
600
ns
1=1 kHz
62
dB
Cdb
Vss - V OUT = 0; I = 1 MHz
3S
pF
Data Input Capacitance
C'"
Vss - Vo,p = 0; I = 1 MHz
Logic Input Capacitance
Cog
Vss -
Power Dissipation
Po
Voo = -31V, .vss
Channel Separation
Output
C~pacitance
VL091c In
pF
6.0
= 0; f = 1 MHz
6.0
= OV
12S
pF
175
mW
Note 1: All voltages relerenced to VSS ..
Note 2: Ratings applies for ambient temperatures to +2SoC, derate linearly at 3 mWfC for ambient temperatures above +25°C.
Not. 3: Specifications apply for TA = 2S"C, -24V::; VDD::; -20V, and +S.OV::; VSS::; +7.0V; unless otherwise specified
(all voltages are referenced to ground),
.
5·29
Typical Performance Characteristics
ON Resistance 05 Analog
Input Voltage
300
~JEh!OIlT
250
ON Resistance vs
Ambient Temperature
Voo:=: -20V
_ Vss=+7V
T4 =+25°C
lOUT = -100 $AA
200
TESTPOiNT~
i"'o
ro-
100
'-
50
o
, IJ ,
400
Voo::: -20V
Vss =+7V
350
lOUT "'-1 00 "A
NT
c:
-3
-1 0 +1
+3
+5
~o 150
11
50
-15 -50 -25
+7
'" 100
"
i'"ir,7
100
0
25
50
lOUT "'-10DIJA
"
200
V1NPUT :=: -5V
"2200
o
II: 150
-
50
I
-[
\.
\.
"' ........
I- VOl'll '"
""",....,,::--.,
+5·rV
~oUT'f'OV-
J
I
VOUT " -S.OV-
-
r---
o
15 100 125
-10
.-20
-15
TEMPERATURE 1°C)
iNPUT IVI
TA • 25'C
vss:=: +5V
250
Tfr
o
-5
\
~lIU
300
_ 250
IIII
~ 150
rf
ON Resistanc. vs VDD
Supply Voltage
-25
Voo SUPPl V IVI
Switching Time Test Circuit
Output Le~kage Current vs
Ambient Temperature
"
=ftv_.:---
10'
VOUT - Vss '" 15V
~
TEST POINTS
"""
./
.~
./
~..,.,,"
"
25
50
15
100
c
125
TEMPERATURE rei
Typical Applications
(Continued)
Differential Input MUX
16-Channel Commutator
'~·'I
IHltfnTll
VoltigeGain"2DO
Ddferentiallnput Resistance'" 1D1on
CMRR'" 100 dB
Input Current = 0.5 nA
SoChannel Demultiplexer with Sample and Hold
Wide Input Range Analog Switch
..·..,1
IMMI
An.log Input RI. - 25V .
Slaw Ratti - 5 VlJ.'S
5-30
»
~
3!:
CD
.....
o
~
AM9709, AM97C09, AH5009 Series
Monolithic Analog Current Switches
»
3!:
General Description
A versatile family of monolithic JFET analog switches
designed to economically fulfill a wide variety of multi·
plexing and analog switching applications.
Even numbered switches may be driven directly from
standard 5V logic, whereas the odd numbered switches
are intended for applications utilizing 10V or 15V logic.
The monolithic construction guarantees tight resistance
match and track.
The AM97C09 series is specifically intended to be driven
from CMOS providing the best performance at lowest
cost.
CD
.....
• Active filters
• Signal multiplexers/demultiplexers
• Multiple channel AGC
• Quad compressors/expanders
• Choppers/demodulators
• Programmable gain amplifiers
• High impedance voltage buffer
• Sample and hold
~
Features
o
(")
o
»
:t:
(J1
o
• Inte'rfaces with standard TTL and CMOS
2 ohms
• On·resistance match
100 ohms
• Low "ON" resistance
50 pA
• Very low leakage
±10V peak
• Large analog signal range
150 ns
• High switching speed
80 dB
• Excellent isolation between
channels
at 1 kHz
Applications
• AD/DA converters
• Micropower converters
• I ndustrial controllers
• Position controllers
• Data acquisition
Connection Diagrams
Dual-in-Line Package
Dual-In-L)ne Package
14
16
Il
"
12
14
11
Il
10
12
11
10
TOP VIEW
TOP VIEW
Order Number AM9709CN, AM9710CN, AM97C09CN,
AM97C10CN, AH5009CN, AH5010CN, AH5013CN
or AH5014CN
'
See Package 21
Order Number AM9711CN, AM9712CN, AM97C09CN,
AM97C10CN, AHS011CN, AHS012CN, AHS01SCN
or AHSD16CN
See Package 22
Functional and Schematic Diagrams
MUX Switches
(4·Channel Version Shown)
SPST Switches
(Quad Version Shown)
(Additional type on other pages)
MUX Switches
(4·Channel Version Shown)
SPST Switches
(Quad Version Shown)
COMPENSATING FET
3
DIS
o----ifI"
'"---01
I
2~--'"
, o----ifI"I '"---0.
3*o---1r--'
,*o---1r--'
5'o-~~-'"
5*o--1~--'
1D'o-~~-'"
12*o-~~-'"
7 0---..1
11~"---O9
I
10o---..J
14 o----a';.A.....-....o16
15o- __ .J
*Note: All diode cathodes are internally connected
to the substrate.
ll*o-__
12*o-__~-'"
14
COMMON QRAINS
5·31
~--'
UNCOMMITTED DRAINS
CD
en
...
CD
Cir
CJ)
Absolute Maximum Ratings
/
Input Voltage
AM9709-12CN, AH5009-'24CN
AM97C09-12CN
Positive Analog Signal Voltage
Negative Analog Signal Voltage
Diode Current
D(ain Current
Power Dissipation
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
30V
25V
30V
-15V
10mA
30mA
500mW
-25° C to +85° C
--65°C to +150°C
300°C
,
Electrical Characteristics
AM9709, AM97C09, AH5009
(Notes 1 and 2)
,SV TTL
PARAMETER
AM9710CN
AM9712CN
CONOITIONS
TYP
IGsx
Input Current "OFF"
V GD - l1V, V SD = 0.7V
0.01
TA = 8SoC
'GSX
Input Current "OFF"
'OfOFF)
Leakage Current "OFF"
IO{OFrI
leakage Current "OFF"
MAX
2
SVTTL
SV-10VCMOS
AHS010-16
(EVEN SERI ES)
AM97C10CN
AM9712CN
TYP
MAX
0.01
0.2
100
TYP
nA
nA
0,01
TA =8S'C
0.01
0.2
0.01
10
0.2
10
V SD = 0.7V, V GS = 4.3V
V GO
d.av,
Is
= 1 mA
TA = 8S'C
IG(ON)
Leakage Current "ON"
V GD =OV, Is =2mA
0.13
TA = 8SoC
'GfON)
Leakage Current "ON"
V GD =OV, Is =-2mA
"0.1
T.A = 8S'C
rOS(ON)
rOS(ON)
Drain-Source Resistance
Drain-Source Resistance
V GS = 0.3SV. Is = 2 mA
TA = +8S'C
90
1
0.08
1
200
200
S
1000
10
10
10
100
20
100
·1 SO
90
240
VOIODE
Forward Diode Drop
ID =O.SmA
rostoN)
Match
V GS = 0, I D = 1 mA
TON
Turn "ON" Time
TOFF
Turn "OFF" Time
CT
Cross Talk
0.08
0.13
0.10
2
nA
100
nA
1
nA
200
nA
S
nA
10
/J A
10
nA
20
/JA
lS0
240
V GS = OV, Is = 2 mA
TA = 8SoC
90
lS0
240
0.8
4
20
See ae Test Circuit
lS0
SOO
lS0
SOO
See ae Test Circu it
300
SOO
300
SOO
See ae "(est Circuit
120
Note 1: 'Test conditions 2SoC unless otherwise noted.
Note 2: "OFF" and "ON" notation refers to the conduction state of the FET switch.
5·32
SO
120
nA
nA
0.01
0.08
nA
nA
TA = 8S'C
Leakage Current "ON"
2
100
V SD = 0.7V, V GS =:i.8V
TA =8SoC
IGfON )
MAX
10
V GD = lSV, V SD = 0.7V
UNITS
n
n
n
n
0.8
V
20
n
lS0
SOO
ns
300
500
4
120
ns
dB
Electrical Characteristics
»
3:
(Continued)
CO
~
PARAMETER
CONDITIONS
lSV TTL
lSVTTL
10-lSV CMOS
AM9709CN
AM9711CN
AHS009-1S
(ODD SERIESI
AM97C09CN
AM97CllCN
TYP
'GSX
Input Current "OFF"
V GO = llV, Vso =0.7V
0.01
T A = 85°C
MAX
2
UNITS
TYP
MAX
0.01
0.2
nA
10
nA
100
TYP
o
MAX
IGSX
Input Current "OFF"
V GO = lSV, Vso = 0.7V
TA = 8SoC
0.01
2
nA
100
nA
IOIOFF)
Leakage Current "OFF"
Vso = 0.7V, VGS = 9.3V
TA =8SoC
0.01
2
nA
100
nA
IOIOFF)
Leakage Current "OFF"
Vso = 0.7V, VGS = 1O.3V
TA = 8SoC
0.01
2
0.01
10
nA
o
100
100
'CHON)
Leakage Current "ON"
V GO =OV,l s =2mA
0.07
2
2
1
2
'OSION}
Drain-Source Resistance
VGS = OV,ls = 2 rnA
TA = 8SoC
rOSIONI
Drain-Source Resistance
VGs=1.SV,ls=2mA
TA = 8SoC
VOIODE
Forward Diode Drop
10 = O.SmA
rOSION)
Match
Vas = 0, 10 = 1 rnA
O.OS
O.S
S
100
2
20
O.S
100
nA
0.07
2
nA
1
IlA
O.OS
S
nA
2
IlA
100
160
100
60
160
100
160
SO
10
0.8
V
10
U
ns
TON
Turn "ON" Time
See ae Test Circuit
lS0
SOO
lS0
SOD
lS0
SOO
TOFF
Turn "OFF" Time
See ae Test Circuit
300
SOD
300
SOO
300
SOD
CT
Cross Talk
See ae Test Circuit
120
5-33
120
n
n
n
n
2
0.8
2
-
0.04
60
60
»
.::::t
O.S
V GO = OV,ls =-2mA
TA =8SoC
o
JD
nA
0.04
leakage Current "ON"
~
(')
nA
V GO =OV,l s = 1 rnA
TA = 8SoC
'GCON)
CO
10
Leakage Current "ON"
TA = 8SoC
»
3:
0.2
I GION ]
0.04
...CO
120
ns
d8
(J1
o
CO
en
CD
...i'
en
en
Q)
'':
Schematic Diagrams and Pin Connections
Q)
Four Channel
CJ)
AM97C09CN (ROS(ON) s' lOOn, lO-l5V CMOS)
AM97ClOCN (ROS(ON) S l50n, 5-l0V CMOS)
AM9709CN, AH5009CN (ROS(ON)
loon, l5V TTL)
AM97lOCN, AH50l0CN (ROS(ON) S l50n, 5V TTL) ,
m
o
oU')
AM97CllCN (ROS(ON) S loon, lO-15V CMOS)
AM97C12CN (ROS(ON) S l50n, 5-l0V CMOS)
AM9711CN,AH50llCN (ROS(ON) S loon, l5V,TTL)
AM97l2CN, AH50l2CN (ROS(ON) S l50n, 5V TTL)
s
:I:
«
11
11<>~~_.,
10
12 <>-....1------'
<>-~'-----'
14
12
<>-~'-----'
O---t----,
131<>---i~-----J
l4,Pin OIP
l6·Pin OIP
Three-Channel
AH50l3CN (ROS(ON) S lOOn, l5V TTL)
AH50l4CN (ROS(ON) S l50n, 5V TTL)
AH50l5CN (ROS(ON) S loon, l5V TTL)
AH5016CN (ROS(ON) S 150n, 5V TTL)
,--_+-011
11
10 0 - -...- - - - - '
O---<~-.,
12 0 - -...- - - - - '
14·Pin OIP
l6·Pin OIP
Test Circuits and Switching Time Waveforms
Cross Talk Test Circuit
ac Test Circuit
10k
Your
Your
(C l :;lDpF)
5·34
16
»
:s:
Typical Performance Characteristics
Parameter Interaction
1000
"''''
~~
200
k:~
.,,,
100
",,,,
-g~P
loss
')<"'"
10
~
:<
~~
.,
II
10
Z
./
lk
Q
.!l
10
5~11~
100
po """"
~~CMI
50
10105
hu'o,~~
t-- ~
-
25
35
45
55
65
75
85
25
35
TEMPERATURE I"CI
GATE SOURCE CUTOFF VOLTAGE IVI
45
55
65
75
85
TEMPERATURE ("CI
Leakage Current vs
Drain~Gate Voltage
Cross Talk, CT vs Frequency
100
TA =.2S"C
ID:::-2m~
;I -60
....
ii!
-50
~ -40
-3D
-20
-10
~
o
en
...
1.0
100
10k
lk
1M
lOOk
o
'"
-D.l rnA
~~~!OFFI"'1.5VII
10
15
Voltage
'<
....
oS
~
~
'"~
-15
-10
c
-5
-1.0
-10
DRAIN CURRENT {mAl
Normalized Drain
Resistance vs Bias
Drain Current vs Bias
-20
I
-0.1
25
20
DRAIN·GATE VOLTAGE IVI
FREQUENCY IHd
-25
~ VGSIOFFI =2V
1 1 1
5.0
ar
rn
10
J...J:::::E:::: :.r- ~ss.'=
10
Voltage
100
1\
\
w
Vos" -loV_
z"
f= 1 kHz
TA "25 C -
\
50
"'"
20
i1i
11
\1\
VGSIOFFI@-10V,-10,uA
'"
I;;
rOSb
-
'os
1-
VGS
VaslofFl
W
N
..'"g;
:::l
'\
~ 1\
\. \. '\.
~
'"
1.0
10
5.0
'"
I
"........ ::--...
2.0
,ll
2.0
1.0
3.0
~
0.2
GATE·SOURCE.VOLTAGE IVI
..... "
0.4
./
0.6
0.8
1.0,
IVas/VaSIOFF)l- NORMALIZED GATE·
TO·SOURCE· VOLTAGE IVI
Applications Information
Theory of Operation
(AM97Cl0), open collector 15V TTL (AM9709), and
1O-15V CMOS (AM97C09).
The AM/AH series of analog switches are primarily
intended for operation in current mode switch applica·
tions; Le., the drains of the FET switch are held at or
near ground by operating into the summing junction of
an operational amplifier. Limiting the drain voltage to
under a few hundred millivolts eliminates the need for a
special gate driver, allowing the switches to be driven
directly by standard TTL (AM9710), 5V-l0V CMOS
Two basic switch configurations are available: multiple
independent switches (N by SPST) and multiple pole
switches used for multiplexing (NPST-MUX). The MUX
versions such as the AM9709 offer comm'on drains and
include a series 'FET operated at VGS ; OV. The additional FET is placed in feedback path in order to
compensate for the "ON" resistance of the switch FET
as shown in Figure 1.
5-35
»
::J:
CD
10 " lmA_
1 1
~
CD
TA • 25"C
VOG:: -5V
f::; 1 kHz
t; -80
--
......
U1
:!!
>i -70
»
:s:
CD
o
Transconductance vs
Drain Current
1000
CD
'"
o
o
10
o
o
25
100
-120
-110
-100
iii -90
~~
15 I--
./
100
'"'"
1.0
1.0
Vas
w
125
[ ~'"
'os
V
20
.-
-
10 =-t rnA
.e-
.,~ j
'"
~ 1ll"'
;:: '"
'"
13
......
vs Temperature
150
~
,.....'"
g,,@VeS = -15V. VGs:: OV PULSED
w -
u'"
'"........E
"'-
vs Temperature
10k
VGSIOFFI@VOS:::-15V, 10 =-1 nA
res@lo=-lmA.VGs=OV
-
CD
On Resi~tance, rOSIONI
Leakage Current, IOiOFFI
Applications Information
(Continued)
The closed·loop gain of Figure 1 is:
In a typical application, VA might = ±10V, Aa" = 0.1%,
O°C ~ T A ~ 85~C. The criterion of equation (2b)
predicts:
R2 + 'OS(ON)Q2
AVCL
For R 1
rOS'ON)
between
accuracy
Rl + 'OS(ON)Ol
10V
"" R2, gain accuracy is determined by the
match between 01 and 02. Typical match
01 and 02 is 4 ohms resulting in a gain
of 0.05% (for Rl = R2 = 10 kQ).
5 kQ
20 mA
10
For R1 = 5k, Is ~ 1 OV 15k or 2 mAo The electrical
characteristics guarantee an IG(O"') ~ lilA at 85°C for
the AM9710. Per the criterion of equation (2a):
Noise Immunity
The switches with the source diodes grounded exhibit
improved noise immunity for positive analog signals in
the "OFF" state. With V ,N = 15V and the VA = 10V,
the source of 01 is clamped to about 0.7V by the diode
(V GS = 14.3V) ensuring that ac signals imposed on the
10V will not gate the FET "ON."
(10V)(10- 3 )
Rl(MIN) ~
1 x 10-£
~ 10 kQ
Since equation (2a) predicts a higher value, the 10k
resistor should be used ..
Selection of Gain Setting Resistors
The "OFF" condition of the FET also affects gain
accuracy. As shown in Figure'3, the leakage across 02,
10(OFFI represents a finite error in the current arriving
at the summing junction of the op amp,
Since the AM/AH series of analog switches are operated
current mode, it is generally advisable to make the signal
current as large as possible. However, current through
the F ET switch tends to forward bias the source to gate
junction and the signal shunting diode resulting' in
leakage through these junctions. As shown in Figure 2,
IG(ON) represellts a finite error in the current reaching
the summing junction·of the op amp.
Accordingly:
VA(MINI Ao
Rl(MAx) ~
(N) 10(OFF)
Secondly, the rOS(ON) of the FET begins to "round" as
Is approaches loss. A practical rule of thumb is to
maintain Is at less than 1/10 of loss,
Where:
Combining the criteria from the above discussion yields:
Rl(MIN) ~
VA(MAX) Ao
(2a)
IG(ON)
VA(MIN)
Minimum value for the analog
input signal
A,
Desired accuracy
N
Number of channels
10(OFF)
"OFF" leakage of a given FET
switch
or:
~
VA(MAX)
As an example, if N = 10, Ao = 0.1%, and IO(OFF)
~ 10 nA at 85°C for the AM9709, Rl(MAx) is:
(2b)
10ss/1O
whichever is worse.
Where:
R1(MAXI
VA(MAX)
Peak amplitude of the analog
input signal
AD
Desired accuracy
IG(ON)
Leakage at a given Is
loss
Saturation current of the FET
switch
"k
10k
Lastly, the foregoing discussion has ignored resistor
tolerances, input bias current and offset voltage of the
op amp-all of which should be considered in setting the
overall gain accuracy of the circuit .
AI
A2
(10)(10 x 10~)
Selection of R2, of course, depends on the gain desired
and for unity gain R 1 = R2,
._ 20 mA
ANI~~~~ VA 0--'\11"'",...-.....- - - ,
~
VA
FIGURE 1. Use of Compensation FET
=
+10V
o--JVl.R'/V-o-.....--i+
FIGURE 2. On Leakage Current, 'G(ON)
5·36
A2
Applications Information
l>
(Continued)
i:
both cases, t(OFF) is improved for lower values of REXT
and the expense of power dissipation in the low state.
TTL Compatibility
Two input logic drive versions of AMI AH series are
available: the even numbered part types are specified to
be driven from standard 5V·TTL logic and the odd
numbered types from 15V open co1lector TTL.
......
o
YJ
CMOS Compatibility
The cost effective AM97C09 series of switches is
optimized for CMOS drive without resistor pull·up. The
AM97Cl0's and AM97C12's are specified for 5V-l0V
operation while the AM97C09's and AM97Cll's are
specified for 1OV-15V operation.
Standard TTL gates pull·up to about 3.5V (no load).
In order to ensure turn·off of the even numbered switches
such as AM971O, a pull·up resistor, R EXT , of at least
10 kn should be placed between the 5V Vee and the
gate output as showri in Figure 4.
CD
Definition of Terms
l>
i:
CO
......
o
o
CD
~
The terms referred to in the electrical characteristics
tables are as defined in Figure 6.
Likewise, the open·collector, high voltage TTL outputs
should use a pull·up resistor as shown in Figure 5. In
l>
::r:
(11
o
o
CD
en
CD
....
.,
CD'
en
FIGURE 3.
ANALOG
INPUT (VAl
r--------, .,y
I
I
I
I
I
I
RUT
ANALOG
OUTPUT
12k
TO
10k)
I
I
I
I
I
__ I
L::!.~~_....::_..::.J
FIGURE 4. Interfacing with +5V TTL
+5VOR+15V
ANALOG
INPUT (VA)
r------"l
I
I
I
I
I
I
I
I
I
I
+15V
ANALOG
OUTPUT
REXT
(2kTD
10k)
-
-
r-l-o--+--o--_...I
I
I
I
I
__ I
LOGIC
INPUT
tV",)
l.!:~..t.!!:...G~ __-_~...J
FIGURE 5. Interfacing with +15V Open Collector TTL
5·37
tn
CI)
'':;:
Applications Information
(Continued)
COMPENSATING
ELEMENT
RDSIONI
CI)
tn
0)
o
oit)
R,
R,
SHUNT .----
ELEMENT
l:
':""-_-C
g
.....
0)
I
:i
,..
11
--AM9709iAMsiio--
I
I
I
I
VDD
OUT
Normal opeultion: Control-hne billing,
. switch ON Vc "I" '" VDD. switch OFf Vc "0" = VIIS
Dual-In-Line and Flat Package
Order Number CD4016MD
See Package 14
Order Number CD4016MF
See Package 23
Order Number CD4016CJ or CD4016MJ
See Package 18
.
Order Number CD4016CN
See Package 21
5-44
0
Absolute Maximum Ratings
Operating Temperature Range
CD4016M
GD4016C
Electrical Characteristics
-65°C to +-150°C
Storage Temperature Rang!'
Vss -O.3V to Vss t15.5V
-5S<>C to +'25~C
-40 g C to +8S"C
Volt.Jge at Any Pm (Note 11
Package
DI~Slpatlon
500mW
300·C
VS5 i3V to Vss +15V
Lead Temperature (Soiderillg, 10 secl
Operating VDO Range
CD4016M
LIMITS
CHARACTERISTIC
250fC
-5S"C
TEST CONDITIONS
SYMBOL
MIN TVP MAX MIN
Quiescent OI5Slpatlon
per Package
5,6,12,13
1,4.8, 11
V"
0.1
GND
~ +10
~.j.l0
. 2.3,9,10
V,.
UNITS
MIN TVP MAX
pW
300
TERMINALS
14
Threshold Voltage
N-Channel
P-Channel
,,0
0.1
5,6,12,13
GND
+10
1-4. a-I'
-:::; +10
pW
300
VTHN
~D~: =1~~~'0V. or ,lSV
1.7
1.5
1.3
V
VTHP
~O:o'" =-~~.JJ.'~V, or 15V
-1.7
-1.5
-1.3
V
SIGN'AL INPUTS (VII! AND OUTPUTS (VOl)
V.
Vc'" Voo
Vss
+7.5V
-75V
+7 SV
-7.SV
to 2SV
t5V:
+5V
"ON" Resistance
-5V
-5V
±O 2SV
RON
RL'" lOkQ
+15V
OV
+15V
+O.25V
9.3V
+10V
OV
+10V
Sine Wave Response
RL'" lQkn
fll'" 1 kHz
10,stortlon) .
Input or Output
Leakage-Switch "OFF"
(Effective "OFF"
Resistance)
360
360
775
130
130
600
600
325
120
120
150
1870
+025V
200
200
280
250
250
580
200
200
300
360
360
775
600
250
250
560
600
1870
400
300
400
850
660
660
300
470
400
400
2000
900
2600 .
300
600
600
400
400
850
300
490
400
660
660
400
BBO
2000
600
600
Sl
1230
960
960
n
n
1230
960
960
n
2600
+-7.5V
-7.5V
±75V
10
+5V
-5V
±5V
15
+5V
-5V
5V(p·p)
0.4
%
=100
±100
pA
n
(Note 31
Vee
Vc '" Vss
V"
+7.5V
-7.SV
+7.5V
-7.5V
-5V
+5V
-5V
+5V
Frequency ResponseSWItch "ON"
(Sme Wave Input)
120
120
130
130
130
300
56V
/),,"ON" Resist3nce
Between Any 2
of 4 Switches
(Note 21 125
nA
INote21 125
Vc '" Voo "'·+5V. Vss '" -5V
RL'" 1 kn
20 Log 1o
MH,
40
~ "-3dB
VIS '" SV(p·p) Voo '" +5V, Ve
Feedthrough
Switch "OFF"
Vss" -5V
=
125
20 Log 10 VO! '" -50 dB
V"
Crosstalk Between any 2
of the 4 sWitches
(Frequency at -50 dBI
Capacitance
RL'" 1 kn
V"IAI"
5V(p-p)
vetA! = Voo = t5V
VeIB) = Vss" -5V
20 l0910
~:(~J'
0.9
= -50 dB
Input
C"
Output
Ces
4
Feedthrough
C,OS
02
Propagation Delay
Signal Input to
Signal Output
Voo '" +5V. Ve'" Vss
Vc
=>.
=
-5V
Voo '" +10V, Vss '" GNO, CL
'"
pF
15 pF
10
VIS '" 10V (square wave)
I,:: It" 20 ns (input signal)
CONTROL (Ve)
V,,$;V OD
Switch Threshold Voltage
'is" 10j.tA
Voo - Vss '" 10V
Vc: 25°C (calculated from RON values shown).
No V DD current will flow through RL if the switch
current Hows into "Out/In" pin.
In certain applications the'external load-resistor current
may include both V DD and signal-line components. To
avoid drawing V DD current when switch current flows
into "I n/Out" pin, the voltage drop across the bidirec-
Truth Table
"ON" CHANNELS
INPUT STATES
INHIBIT
C
B
A
CD40S1A
CD40S2A
CD40S3A
0
0
0
0
0
OX.OV
ex. bx, ax
0
0
0
I
I
IX. IV
0
I
2X.2Y
ex, bx, ay
ex, by, ax
I
0
1
2
0
0
'0
3
3X.3Y
0
I
0
0
4
0
I
0
1
5
0
1
I
0
0
...
6
7
1
I
I
I
ex, by. ay
r::r{. bx, ax
cy, bx, ay
CV,by.ax
cv,bY,ay
NONE
·Oon't Care condition
5·51
NONE
NONE
o~
it)
Schematic Diagrams
o
'CD4051M/CD4051C
~
c
y..
o
.......
.
,
• , , , "
,
v"
::E
~
'O!!-
o
,O!!-
it)
~
c
L-...cD--r-'
~
-q:::r ~
BINARY
TO
10f8
OECODER
LEVEL
o
o!-
'--
cJ
N
0!-
r---
it)
L.....rn, --r-'
~
LOGIC
.........
'" r' t".' .......
CHANNELIN.IOUT
CONVERSION
"lc"""'
--r-'
WITH
INHIBIT
-gfr
-t::!p-t::!p-
o
~
c
~
1·
g
v"
::E
N
CD4052M/CD4052C
it)
kCHANNElSINf1]UT
~
C
o
'J
cJ
,...
2
v"
it)
~
"
C
o
.......
BINARY
TO
lOGIC
10ft
DEcaOER
LEVEl
CONVERSION
WITH
INKIBIT
::E
,...
it)
~
v"
VCHANNElSlNIQUT
C
o
CD4053M/CD4053C
.
BINARyrQ
tOFZ
DECODER
WITHINfflBIT
10
LOGIC
,
LEVEL
CONVEIISION
..
,
5·52
COMMON
OUT/IN
o
c
Typical Performance Characteristics
~
"ON
"ON" Resistance vs Signal
Voltage for TA = 2SoC
S
n
o
Resistance as a
(II
Function of Temperature for
VOO - VEE = lSV
.....
400
~~
350
1
350
H+H-t-I+-t-I++-l+H-j
lDD
~
JOO
H++-++-H--I--H--H+-H-I
2:
250
~
200
-
~
~
Voo - Vee'" SV
~
150
.....
100
lii
50
~~oy
150
-8 -6
-4 -2
0
TA '"
-8
-6
350
w
u
300
'"l;:;"
250
~
200
Z
150
~
100
?
w
'"'"
~
50
-55~C
-4
-2
o
0
c
SIGNAL VOLTAGE IV"IIV)
~
nON n Resistance as a
"ON" Resistance as a
Function of Temperature for
VOO-VEE=lDV
Function of Temperature for
VOO-VEE = SV
400
400
1
!!;
$')
TA=+~
o
SIGNAL VOLTAGE IV,,) IV)
:s
U1
.....
TA=~
100
50
o
-
~~
2.
~
~
a:
TA "+125C
1(1 t:r1
TA "',-55"C
0
-8 -6 -4 -2
1\
250
200
o
c
III II
~
.~ 1.~J5'~
o
-8 -6
4
N
s:
TA '" +25°C
50
2
U1
TA = +t25"C
JOO
100
-4 -2
IAI III
o
IIIII
IIIII
$')
0
SUPPL Y VOLTAGE IV,,) IVI
SIGNAL VOLTAGE IV,,) IV)
o
IIIII
350
~ 150
TA"~'C
c
~
i.
?
lJ..U..+'H.
Veo - VEE '" 15V
o
o
~
200
a:
a:
~
250
s:
........
6
U1
N
8
o
c~
o
U1
CA)
s:
........
o
c
~
o
U1
CA)
o
5-53
o
m
CO
CO
~
o
~
Q
m
CO
CO
CD4066BM/CD4066BC Quad Bilateral Switch
o
~
c
\
o
?
i
General Description
The, CD4066BM/CD4066BC is a quad bilateral switch
intended for the transmission or multiplexing of analog
or digital signals. It is pin·for·pin compatible with
CD4016BM/CD4016BC, but has a much lower "ON"
resistance, and "ON" resistance is relatively constant
over the input·signal range.
•
Extermely low "OFF" switch leakage
0.1 nA typ
@ VDD - VSS = 10V,
TA=25°C
• Extremely high'control input
1012!1 typ
impedance
• Low crosstalk between switches'
-50 dB typ
@ fis = 0.9 MHz, RL = 1 k!1
40 MHz typ
• Frequency response, switch "ON"
Features
Applications
3V to 15V
• Wide supply voltage range
0.45 VDD typ
• High noise immunity
• Wide range of digital and
±7.5 VPEAK
analog switching
80!1typ
• "ON" resistance for 15V operation
£lRPN = 5!1 typ
• Matched "ON" resistance over
i 5V signal input
• "ON" resistance flat over peak-to-peak signal range .
• 'High "ON"/"OFF" outpui: voltage ratio
65 dB typ
, @ fis = 10 kHz, RL = 10 k!1
< 0.4% distortion typ
• High degree of linearity
@ fis = 1 kHz, Vis = 5 Vp·p,
VDD - VSS = 10V, RL = 10 kn
• Analog signal switching/multiplexing
~ Signal gating'
• Squelch cont'rol
• Chopper
• Modulator/Demodulator
• Com mutating switch
• Digital signal switching/multiplexing
• CMOS logic implementation
• Analog-to·digital/digital-to-analog conversion
• Digital control of frequency, impedance, phase,
and analog-signal gain
Schematic and Connection Diagrams
Dual-In-Line and Flat Package
INIOUT
IN/OUT
CONTROL
CONTROL C
-=+--,
Vss
OUlliN
INIOUl
\
TOP VIEW
Order Number CD4066BMD
See Package 14
Order Number CD4066BMF
See Package 23
Order Number CD4066BCJ or CD4066BMJ
See Package 18
Order Number CD4066BCN
See Package 21
5-54
Absolute Maximum Ratings
Operating Conditions
(Notes 1 and 2)
(Note 2)
- 25°C (calculated from RON values
shown).
No VDD current will flow through RL if the switch
current flows into terminals 2, 3, 9 or 10.
In certain applications, the external load-resistor current
may include both VDD and signal-line components. To
5-59
fn
Q)
't;:
Q)
tJ)
N
o Quad SPST JFET Analog Switches
N
,.. LF11331/LF12331/LF13331 4 normally open switches with disable
,..
4 normally closed switches with disable
BI·FET Technology
LL.
...I
LF11332/LF12332/LF13332
LF11333/LF12333/LF13333
2 normally closed switches and 2 normally open switches with disable
o
LF11201/LF12201/LF 13201
4 normally closed switches
LF11202/LF12202/LF13202
4 normally open switches
,..
,..
N
u:
...I
'"
~
~
~
,..
u:
...I
N
~
~
,..
u:
...I
General Description
These devices are a monolith ic combination of bipolar
and JFET technology producing the industry's first
one chip quad JFET switch. A unique circuit technique
is employed to maintain a constant resistance over the
analog voltage range of ±10V. The input is designed to
operate from minimum TTL levels, and switch operation
also ensures a break·before·make action.
• Small signal analog signals to 50 MHz
• Break·before·make action
tOFF
~
-80
2.0
4.0
r--.
f-
-10
60
IOFF
50
100
1M
ISO
-2.~
-6.0
2.0
6.0
10
Supply Current
r:::--=:-,--,--,--,
<" BoO
3D
4fl!!lil-miIM:;;,;,;.:,.;:m-H!lIIt"ttt1IIIII
.§
10,000
~
....
>
2.0 HtHtitil-tHtllilH-tt1I!I--H1i':':..w"!'!-;:~
fi
1.0
H+1lIIf--!+l!IIIH-tt1I!H14-
10
100
loOk
10M
lOOk
OFF LEAKAGE CONDITIONS
Vs = -tIDV, Vo = -IOV
ON LEAKAGE CONDITIONS
Vs "V D = +IDV
~.'0,0 0 ;i~'''Oi''';-~i;
~
ISION )
I
-100
1.0M
1
0.4
5.0
10
20
15
~
0.2
~
y
50
""
~
02
•.0
~
4.0
h~b_F---+-==""'::=-l
~
50
100
150
10
-6.0
2.0
2.0
6.0
IOU
~t+CD!ONt
CjlOFFl
r
./
r--
COIOFFI
-6.0
-2.0
Vcc::: 15\1
VEE:; -15V
2.0
6.0
10
VA (VOLTS)
Logical ul"lnput Bias Current
'0
i.OTE 6\
4' -16
.§
1-
"
0
~
150
:::-
Maximum Accurate Analog
~
50
C'D
en
VA (VOLTS)
;;;
'2
~
:i
-3
-6
c(
-8.0
-4./J
1M
10M
100M
-100
'"'" """
·50
50
5-63
'"...."
'"'"
....
"z
y
r---.
Vee::: 15V
VEE =-15V
YIN =+5.0V
VA =oV
8.0
6.'
i\
\
~
100
TEMPERATURE (ac)
FREOUENCY (Hz!
:<
4.0
.......... ~
I-
2.0
o
150
N
~.
-10
Current vs Temperature
r
"T1
......
......
CD
2.0
10
r
:2
......
N
o.....
oi\)
en
0.4
50
:s
TEMpERATURE I C)
150
8.0
z
;:
~
o
o
100
Switch Capacitances
+ lolON)
J
20
sa
50
TEMPERATURE (' C)
-20
-
2.0 I--~F""'i--+=;;;±=--I
-loa
25
....z
100
r--. t:---..
4.0 f-~kc-+--+---F""--J
10
Small Signal Response
Vee l!iV
VEE::: l!iV
f--f'"-...,.+--+--+---i
OL---L_-'-_.l----'_-'
o
TEMPERATURE ( [;1
Occurs
-100
~
6.0
Switch Lea'(age Current
Slew Rate of Analog Voltage
Above Which Signal Loading
NEGATIVE (lEd_
r v""c-c"'."'15"'v-:,V,..,,-.:-_-:''''5V,-......,'''''''''''',.
FREQUENCY (Hz)
80
....
SUPPl Y VOL TAGE (. VI
10
10k
.§
,-
2.0
Switch Leakage Currents
100,000
HtHtitil-tHtllilH-tttlI-H-ttII-tttIlll-Htfuill
i
~
40
FREQUENCY (Hz)
4.0
w
W
...N
VA (VOLTS)
REFE1RENCE t l
SupplV Current
!
100
I
6.0
~
y
TEMPERATURE ( C)
40
r--~N
200
C-
8.0
o
-50
.
JOD
10
.§
:s
400
60
~
SupplV Current
20°EE:§ffJ
....
g
!Ii
Vee = l!iV
VEE '" -ISV
VA =VEE +5.QV
;;;
2 6001--:;;.-1"'-----t
-'
~
~
ALL SWITCHES OFF
800
.
r
:2
......
1
10
-20 ,---.--,-rnrmr--'--'-T""I"T"Tm
1000
i
- 50% INPUT PULSE TO 90%
~r--- ;r--.~
OUTPUTPULSE
ANALOG CURR,ENT (mAl
Crosstalk and "OFF" Isolation
vs Frequency Using Test Circuit
of Figure 5
Switching Times
~
+Vcc = 1!iV. -V£E "-ISV
TIME MEASURED FROM
400
o
VA (VOLTS)
1200
V
500
40
1--+-+-+-+-+-+-+-+-+--1
120
v
~A '0
40
"
--
160
mA-
120
J
_
vV
Break-Beforo-Make Action
f
240
-100
-so
50
TEMPERATURE
100
rei
150
tn
CD
'i:
CD
tn
N
oN
'P"
u:..J
'P"
o
N
'P"
'P"
LL
..J
C")
C")
C")
'P"
u:..J
'P"
C")
C")
Application Hints
GENERAL INFORMATION
LEAKAGE CURRENTS
The drain and source leakage currents, in both the ON
and·the OFF states of each switch, are typically less than
1 nA at 25°C and less than 100 nA at 125°C. As shown
in the typical curves, these leakage currents are dependent on power supply voltages, analog voltage, analog current and the source to drain voltage.
These devices are monolithic quad JFET analog switches
with "ON" resistances which are essentially independent
of analog'voltage or analog current. The leakage currents
are typically less than 1 nA at 25°C in both the "OFF"
and "ON" switch states and introduce negligible errors
in most applications. Each switch is controlled by minimum TTL logic levels at its input and is designed to turn
"OFF" faster than it will turn "ON." This prevents two
analog sources from being transiently connected together
during switching. The switches were designed for applications which require break-before-make action, no
analog current loss, medium speed switching times and
moderate analog currents.
DELAY TIMES
The delay time OFF (t OH ) is essentially independent of
both the analog voltage and temperature. The delay time
ON (tON) will decrease as either (Vee - V A) decreases
or the temperature decreases.
POWER SUPPLIES
The voltage between the positive supply (Veel and
either the negative supply (Vee) or the reference supply
(V A) can be as much as 36V. To accommodate variations in input logic reference voltages, VA can range
from VEE to (V ee -4.5V). Care should be taken to
ensure that the power supply leads for the device never
become reversed in polarity or that the device is never
inadvertantly installed backwards in a test socket. If one
of these conditions occurs, the supplies would zener an
interal diode to an unlimited current; and result in a
destroyed device.
Because these analog switches are JFET rather than
CMOS, they do not require special handling.
LOGIC INPUTS
The logic input (IN), of each switch, is referenced to two
,forward diode drops (1.4V at 25°C) from the reference
supply (V A) which makes it compatible with DTL, RTL,
and TTL logic families. For normal operation, the logic
"0" voltage can range from O.BV to -4.0V with respect
to VA and the logic "1" voltage can range from 2.0V to
6.0V with respect to VA, provided V IN is not greater
than (Vee - 2.5V). If the input voltage is greater than
(Vee - 2.5V), the input current will increase. If the
input voltage exceeds 6.0V or -4.0V with respect to
VA' a resistor in series with the input should be used to
limit the input current to less than 1001lA.
SWITCHING TRANSIENTI'
When a switch is turned OFF or ON, transients will
appear at the load due to the internal transient voltage at
the gate of the switch JFET being coupled to the drain
and source by the junction capacitances of the JFET.
The magnitude of these transients is dependent on the
load. A lower value RL produces a lower transient volt·
age. A negative transient occurs during the delay time
ON, while a positive transient occurs during the delay
time OFF. These transients are relatively small when
compared to faster switch families.
'P"
u:..J
ANALOG VOLTAGE AND CURRENT
Analog Voltage
Each switch has a constant "ON" resistance (RON) for
analog voltages from (VEE + 5V) to (Vee - 5V). For
analog voltages greater than (Vee - 5V), the switch will
remain ON independent of the logic input voltage. For
analog voltages less than (VEE + 5V), the ON resistance
, of the switch will increase. Although the switch will not
operate normally when the analog voltage is out of the
previously mentioned range, the source voltage can go to
either (VEE + 36V) or (Vee + 6V), whichever is more
positive, and can go as negative as VeE without destruction. The drain (D) voltage can also go to either
(VEE + 36V) or (Vee + 6V), whichever is more positive, and can go as negative as (Vee - 36V) without
destruction.
DISABLE NODE
This !lode can be used, as shown in Figure 5, to turn all
the switches in the unit off independent of logic inputs.
Normally, the node floats freely at an internal diode
drop ("" 0.7V) above V A' When the external transistor in
Figure 5 is sa.turated, the node is pulled very close to V A
and the unit is disabled. Typically, the current from the
node will be less than 1 mAo This feature is not available on the LFl1201 or LFl1202 series.
tV ee
r-----
.l
I
I
I
Analog Current
With the source (S) positive with respect to the drain
(D), the RON is constant for low analog curren't~, but
will increase at higher currents (>5 mAl when the FET
enters the saturation region. However, if the drain is
positive with respect to the source and a small analog
current loss at high analog currents (Note 6) is tolerable,
a low RON can be maintained for analog currents greater
than 5 mA at 25°C.
v"
I
I ->- __ .
I,
I
I
I
DISA."
'Ok
I,JL_-= ___ _
FIGURE 5. Disable Function
5-64
1
VD1s.toBtE >
IV
Typical Applications
Programmable Inverting Non-Inverting Operational Amplifier
r---:;;-;;;;----,
~
141
15
lOOk
~~~~~~~~
I"
I
"I
"...;-I----+';;.......
~:..+--o Your
JOpF
9.1k
r
3!
..a.
N
oI\)
en
CD
...
CD'
t/)
Programmable Gain Operational Amplifier
r---;;,-;;;----,
15
14
10k
'M
V'N
laDk
I
I.
SOOk
li-t.ttJ
GAIN SELECT
5-65
>--+---0
VOUT
Ty plcal
"
. at"Ions
Applic
(Continued)
r ____~ultiPlexer
MultiplexerlMixer
"Ok r----~~l
I
l' ~5
111
1
~.IIIO
"Ok
ii'I
.1
1 I
~Il
"Ok
1
~,
lOOk
1
l'
I
1
I ,II
Z
Ltt-t1J
- - 0 ANALOG
OUTPUT
ANALO~
INPUTS
I:--+-
0.--o
5-66
Typical Applications
..........
...
."
(Continued)
W
W
Chopper Channel Amplifier
~
....
......
o
...
."
N
....
~
::2
",1
Self-Zeroing Operational Amplifier
N
o
N
en
CD
..,
(D'
en
I
I,
I
I
I
I
ZERO
INPUTS
5·67
16
J
o
VOUT
Ty plcal
.
Applications
(Continued)
Programmable
Integrator
. with R
2k
r-'W"'""--r----~
.e,set and Hold
n
N
o
N
,..
5,..
oN
,--'
V" u---'l.""-
SElEC~~
SELECT
. RESET
o-4--c>-
o--!!f--t>--
,I ~
ANDHOlD~
INTEGRATE
I
L~3~
Staircase Transfe
.
-=
0 perational Amplifier
14 r - LF"m--, r Function
15
Rl
"I
VOUT
:~:tl I
L~t~)
I
v,
PIN10F
lF11331
5-68
v,
v,
v,
,-----------------------------------------------------, r
Typical Applications (Continued)'
::!2
...I.
DSB Modulator-Demodulator
~
~
...I.
~
L\:r v,.
r
."
...I.
...I.
N
o
...I.
~
r
::!2
...I.
N
o
N
en
CD
...(5'
r/)
5·69
0)
oIt)
('I)
,..
u..
BI·FET Technology
..J
0; LF1150S/LF1250S/LF1350S
o 8-Ch~nnel' Anaiog Multiplexer
It)
N
LF11509/LF12509/LF13509
4-Charinel ,Differential.Analog Multiplexer
..J
General Description
u::
0;
o
It)
,..
u::
..J
~
(X)
o
It)
('I)
u::
..J
........
(X)
o
It)
N
u::
..J
en
o
It)
The LF 11508/LF 12508/LF 13508 is an 8·channel
analog multiplexer which connects the output to 1 of
the 8 analog inputs depending on .the state of a 3·bit
binary address. An enable control allows disconnecting
the output, thereby providing a package select function. '
connect a pair of independent analog inputs to one of
any 4 pairs of independent analog outputs. The device
has all the features of the LF 11508 series and should be
used whenever differential analog inputs are required.
Features
This device is fabricated with National's BI-FET technology which provides ion-implanted JFETs for the
analog switch on the same chip as the bipolar decode
and switch drive circuitry. This technology makes
possible low constant "ON" resistance with analog
input voltage variations. This device does not suffer·
from latch-up problems 'or static charge blow-out
problems associated with similar CMOS parts. The
digital, inputs are designed to operate from both TTL
and CMOS levels while always providing a definite
break-before-make action.
• JFET switches rather than CMOS
• No static discharge blow-out problem
• No SCR latch-up problems
• Analog signal range 11 V, -15V
• Constant "ON" resistance for analog signals between
-,llV and 11V
• "ON" resistance 380 n typ
• Digital inputs compatible with TTL and CMOS
• Output enable control
• Bre~k-before-make action: tOFF = 0.2 !-Is; tON
2 !-IS typ
The LF11509/LF12509/LF13509 i5 a 4-channel differential analog multiplexer. A 2-bit binary address will
Functional Diagrams and Truth Tables
,..
LF11508/LF12508/LF13508
EN
u::
..J
AI
A2
AD
-vEE
EN
A2
AI
AO
H
L
L
L
L
H
H
L
H
GND
H
H
L
L
H
H
H
H
vee
S8
S7
56
55
S4
53
52
51
·D
H
H
H
H
L
L
H
H
L
X
X
SWITCH
ON
L
H
51
52
53
54
55
56
57
58
X
NONE
H
L
H
L
H
LFI1509/LFI2509/LF13509
EN
AI
EN
AI
L
X
X
None
GND
H
H
H
H
L
L
L
51
S2
53
54
Vee
Ds
S4S,
S3S
S2S
SIS
S4A
53A
S2A
SIA
DA
5-70
SWITCH
PAIR ON
-VEE
H
H
AO
H
L
H
r
...
::2
en
o
Absolute Maximum Ratings
LF1150B,
LFl1509
Positive Supply - Negative Supply (Vee - Veel
Positive Analog Input Voltage (Note .1 I
Negative Analog Input Voltage (Note 1 I
Positive Digital Input Voltage
Negative Digital Input Voltage
Analog Switch Current
IISI
LF1350B,
LF13509
LF1250B,
LF12509
36V
36V
36V
Vee
-Vee
Vee
-Vee
Vee
-Vee
Vee
-5V
Vee
-5V
Vee
-SV
< 10mA
IISI
< lamA
IISI
~
...r
."
N
en
o
0)
< lamA
Power Dissipation (PO at 2Soe) and Thermal
.......
Resistance (OjAI, (Note 2)
Molded DIP (NI
Cavity DIP (01
Po
OjA
-
-
500mW
l50°C/W
Po
900mW
100o C/W
900mW
100oe/W
900mW
150°C
110°C
°jA
Maximum Junction Temperature (TjMAX)
Operating Temperature Range
-55°C::; TA
-
S. +125°C
-25°C
.-65°C to +150oe
300·e
Storage Temperature Range
Lead Temperature (Soldering,'50 secondsl
r
w
en
o
.!»
::2
l00°C/W
100°C
S. TA S. +B5°C
OOe:5, TA
S. +70°C
.-65·e to +150oe
.-65°C to +lS0°C
300·C
300°C
r
...
Electrical Characteristics
::2
en
o
(Note 3)
CD
.......
r
SYMBOL
PARAMETER
LF11S08, LF11S09
CONDITIONS
RON
"RON
~RON
with Analog Voltage
VOUT = OV. IS = 100 ~A
-10V
ISIOFF)
IO(OFF)
IOION)
500
380
650
750
500
850
n
n
TA = 2SoC
0.01
1
0.01
1
%
.......
20
100
20
ISO
n
::2
1
SO
5
nA
10
0.09
SO
nA
20
nA
25
500
0.6
500
nA
20
nA
500
nA
MAX
MIN
TYP
MAX
RON Match Between Switches
VOUT =
0\;. IS = 100~A
TA = 2SoC
TA = 25°C
Source Current in "OFF"
Switch "OFF". Vs = 11. Vo = -II,
Condition
INote 4)
Drain Current in "OFF"
SWitch "OFF". Vs = 11. Vo = -11.
(Note 4)
TA = 25°C
ConditIOn
Leakage Current in "ON"
Switch "ON" Vo = liV. INote 4)
TA = 25°C
10
10
Condition
35
500
1
V,NH
Digital "1" Input Voltage
VINL
Digital "0" Input Voltage
IINL
Digital "0" Input Current
VIN = 0.7V
TA = 2SoC
I.S
IINL(EN)
Digital "0" Enable Current
VEN = 0.7V
TA = 25°C
1.2
tTRAN
Switching Time of Multiplexer
(Figure I). (Note 5)
TA = 2SoC
2.0
tOPEN
Break-Before-Make
(Figure 3)
TA = 25°C
1.6
tON(EN)
Enable Delay "ON"
(Figure 2)
TA = 2S"C
tOFFIEN)
Enable Delay "OFF"
(Figure 2)
TA = 2S"C
ISO(OFF)
"OFF" Isolation
INote 6)
TA = 25°C
-66
-66
dB
CT
Crosstalk
LF 11509 Series. INote 6)
TA = 2SoC
-,66
-£6
dB
CSIOFF)
Source Capacitance ("OFF")
Switch "OFF". VOUT = OV.
TA = 25°C
2.2
2.2
pF
TA'= 2SoC
11.4
11.4
pF
2.0
2.0
V
0.7
20
0.7
1.S
40
20
1.2
40
3
30
V
~A
40
~A
30
~A
40
p.A
1.8
~s
1.6
Jl.s
1.6
1.6
~s
0.2
0.2
~s
VS=OV
CO(OFF)
Dram Capacitance ("OFF")
Switch "OFF". VOUT = OV.
VS= OV
ICC
lEE
Positive Supply Current
Negative Supply Current
All Digital Inputs Grounded
TA = 25°C
TA = 2S"C
All Digital Inputs Grounded
5-71
N
3BO
TYP
Swing
RON Match
::2
600
TA = 25°C
S VOUT S +10V.IS = 100~A
UNITS
en
o
MIN
"ON" Resistance
LF12S08, LF12S09,
LF1350B, LF13509
7.4
10
7.4
12
rnA
9.2
13
7.9
IS
rnA
2.7
4.S
2.7
2.9
S.5
2.B
5
6
rnA
rnA
CD
r
w
en
o
CD
0)
o
it)
Notes
C"')
li:
....I
0;
oit)
N
li:
....I
Note 1: If the anelog input voltage exceeds 'thislimit, the input current should be limited to less than 10 mAo
Note 2: The maximum power dissipation for these devices must be derated at elevated temperatures and is dictated by TjMAX, 8jA, and the
ambient temperature, TA' The maximum available power dissipation at any temperature is PD= (TjMAX - TAl/8jA or the 25"C PDMAX, which·
ever is less.
Note 3: These specifications apply for Vs = ±15V and over the absolute maximum operating temperature range (TL S; TAS; THl unless otherwise
noted.
Note 4: Conditions applied to leakage tests insure worse case leakages. Exceeding 11 V on the analog' input may cause an "OFF" 'channel to
turn "ON".
'
Nota 5: Lots are sample tested to this parameter. The measurement conditions of Figure 1 insure worse case transition time.
Note 6: "OFF" isolation is measured with all switches "OFF" and d~iving a source. Crosstalk is measured with a pair of switches "ON", driving
channel A and measuring channel B. R'L = 200, CL = 7 pF, Vs = 3 Vrms, f = 500 kHz.
0;
o
it)
"t"t-
LL.
Connection Diagrams
....I
...
CO
oit)
C"')
5.......
Dual·ln·Line Package
Al
GND
AZ
116
15
Vee
55
13
14
Dual·ln·Line Package
56
57
11
12
Al
58
10
9
GND
Vee
15
1.6
14
518
5Z8
12
13
538
S48
11
DB
10
9
co
oit)
N
li:
....I
-
r--
-
l-
.......
co
oit)
li:
2
1
"tAD
EN
3
5
4
51
7
6
5Z
53
2
I
18
54
D
AD
3
EN
5
6
7
52A
53A
54A
TOP VIEW
TDPVIEW
....I
4
.51A
Order Numbers LF11508D, LF1250BD,
LFI350BD or LF1350BN
See Packages 17 and 22
Order Numbers LFI1509D, LF12509D,
LF13509D or LFI3509N
See Packages 17 and 22
AC Test·Circuits and Switching Time Waveforms
15V
Vce
SI
0---..,
52-S1 .....
LF1150B
LOGIC
INPUT
10M":"
T
VSl
10 pF
-15V
FIGURE 1. Transition Time
5·72
18
AC Test Circuits and Switching Time Waveforms
r-
:]
(Continued)
'..L
15V
U'I
..
..
o
0)
Vee
.......
Sl
Lfl150B S2-SB~>--,
VoUT
."
..L
ENABLE
INPUT
-15V
':' J
N
U'I
o
0)
lOPF
.......
FIGURE 2. Enable Time.
,5V
3!
w
loV
Vee
U'I
o0)
EN
A2
,..........-C....... A'
~
AD
INPUT
DRIVE
-15V
3V-~
ovJ
'---
FIGURE 3. Break·Before·Make
Transition Times and Transients
VA=5V
VIN
VIN
>
~
GNO
GNO
Vo
Vo
1 "S/DIV
VA = -5V
GNO
GNO
VIN
>
>
~
~.
VA=-10V
Test Circuit
GNO
15V
Vee
EN
>
~.
A2
Al
7
Sl
LFl150B
SB
AD
10M
-15V
5-73
,
-
T
lOPF
0)
o
it)
Typical' Performance Characteristics
u::
..J
Oi
o
it)
C\I
800
400
360
Sz
z
0
0:
Vcc; 15V
VEE" -15V
lA"O
TA' 25'C
320
Oi
...
u::
..J
200
100
100
4
6
-55 -35 -15 5
8 10
25 45 65 85 105 125
TEMPERATURE eel
Switch Leakage
Currents
100
~
loloNI
ISIOFF)
,
IOIOFFI
~
..
~
~
B
w
co
ISIOFFI
-0.1
;'"
C\I
10
15
~
1.5
15
-55
"5~
35
65
95
125
"OFF" Isolation and
CrosStalk
-30
A
VJC"5t
I-- VEE = -15V
0~
1.-
-25
TEMPERATURE I'CI
Enable Delay Times
(Figure 2)
(Figures1,and 3)
2.5
10
-5
ANALOG VOLTAGE (VI
Switching Times
. vc1c
-VEE "-15V
-"''is(OFFI
0.01
-15 -10
ANALOG VOLTAGE (VI
3.5
~
0.1
10
-15 . -10 . -5
!
IO(ONI
ffi
IO(ONI
r-,.-IOIOFFI
-10
it)
10
~
-1
...
u::
-1
ANALOG INPUT CURRENT (mAl
IOIOr FI
u::
..J
CO
'"
o
0
-2
1000
~
o
it)
+~
Currents
! 0.1
E
8
400
a:~ 300
Switch Leakage
VCC =15V
-VEE=-15V
TA =25"C
'"
CO
..J
2
10
CO
M
i"""
S
200
Switch Leakage
Currents
...
oit)
.... ....
ANALOG INPUT VOLTAGE (VI
u::
..J
~
o
300
-10 -8 -6 --4 -2 0
o
it)
300
500
~
500
400
TA" 25'e
.Vee "15V
VEE" -15V
600
Vce =15V
600 I-VEE = -15V
o
.. 340
u::
..J
100
t-l~ = ioo"~
700
380
S
"'ON" Resistance
"ON" Resistance
"ON" Resistance
M
I'
- trR~N ~
~V to!~N
:;;;...-
tON
/
--40
EV
-50
V
~
-.
-60
z
0
5
V
fil
-10
-80
-90
tOFFEN-
0.5
-100
-110
-55
35
-25
65
95
125
-55
-25
TEMPERATURE rCI
35
[\.
Vce "15V
VEE" -15V VLOGIC'· ov
!\ '\
_\ "Not
'-..
10k
9
zz
-
..5"
z
"'
-ISUPPLY
""'- t-o
35
65
TEMPERATURE I'CI
95
125
1t
-
;3
. I
1
1
o
-55 -25
35
65
TEMPERATURE I'CI
5-74
10M
Switch Capacitances
~lpPLY
""-
1M
24
I
....... 1-0.,
8
lOOk
FREQUENCY (Hz!
""'-
'EN
-25
126
Supply Currants
10
-55
95
TEMPERATURE rCI
Bias Currents
r-,.
65
20
18
16
14
12
10
·8
COlON I
COIOFFI
CSIOFFI
o
95
125
-12 -10--11 -6 --4 -2 0 2 4 6 8 10 12
ANALOG VOLTAGE (VI
r-
Application Hints
The LF 11508 series is an 8-.channel analog multiplexer
which allows the connection of a single load to 1 of 8
different analog inputs. These multiplexers incorporate
JF ETs in a switch configuration which insures a constant
"ON" resistance over the analog voltage range of the
device. Four TTL compatible inputs are provided; a
3-bit binary decode to select a particular channel and an
enable input used as a package select. The switches
operate with a break-before-make action preventing the
temporary connection of 2 analog inputs' during
switching. Because these multiplexers are fabricated with
the BI-FET process rather than CMOS, they do not
require special handling.
to the source voltage without limiting the drain current
to less than 10 mAo
LEAKAGE CURRENTS
Leakage currents will remain within the specified value
as long as the drain and source remain within the specified analog voltage range. As the switch terminals exceed
the positive analog voltage range "ON" and "OFF"
leakage currents increase. The "ON" leakage increases
due to an internal clamp required by the switch structure. The "OFF" leakage increases because the gate to
source reverse bias has been decreased to the point
where the switch becomes active. Leakage currents vary
slightly with analog voltage . and will approximately
double for every 10°C rise in temperature.
The LF 11509 series is a 4-channel differential multiplexer which allows two loads to be connected to 1 of
4 different pairs of analog inputs. The LF11509 series
also has all the features of the LF 11508.
SWITCHING TIMES AND TRANSIENTS
These multiplexers 'operate with a break-before-make
switch action. The turn off time is much faster than
the turn, on time to guarantee this feature over the f~1I
range of analog input voltage and temperature. Switching
transients are introduced when a switch is turned "OFF".
The amplitude of these transients may be reduced by
increasing the load capacitance or decreasing the load
resistance. The actual charge transfer in the transient
may be reduced by operating on reduced power supplies. Examples of switching times and transients are
shown in the typical characteristic curves. The enable
function switching times are specified separately from
switch-to-switch transition times and may be thought
of as package-to-package transition times.
The "ON" resistance, RON, of the analog switches is
constant over a wide input range from positive (V cd
supply to negative (-VEE) supply.
The analog input should not exceed either positive or
negative supply without limiting the current to less
than 10 mA; otherwise the multiplexer may get damaged.
For proper operation, however, the positive analog
voltage should be kept equal to or less than VCC - 4V
as this will increase the switch leakage in both "ON"
and "OFF" state and itmay also cause a.false turn "ON"
of a normally "OFF" switch. This limit applies over the
full temperature range.
LOGIC INPUTS AND ENABLE INPUT
The maximum allowable switch "ON" voltage (the drop
across the switch in the "ON" condition) is ±O.4V oiler
temperature. If this number is to exceed the input
current should be limited to 10 mA.
Switch selection in the LF 11508 series is accomplished
by using a 3-bit binary decode while the LFl1509 series
uses a 2-bit decode. These binary logic inputs are compatible with both TTL and CMOS logic voltage levels.
The maximum positive voltage applied to these inputs
may exceed VCC but should not exceed -VEE + 36V.
The maximum negative voltage should not be less than
4V below ground as this will cause an internal device to
zener and all the switches will turn "ON".
The "ON.'\ resistance of the multiplexing switches
varies slightly with analog current because they are
JFETs running at OV gate. to source. The JFET characteristics shown in Figure 4. indicates how RON tends
to vary with current. A lower RON is possible when
the source voltage is negative with respect to the drain
voltage because the JFET becomes enhanced. Caution
should be used when operating in this mode as this
may forward-bias an internal transistor and cause high
currents to flow in the switches. Thus, the drain voltage
should never be greater than 0.4V positive with respect
As shown in the schematic diagram, the logic low bias
current will flow until the PNP input is raised above the
3 diode reference. ('" 2.1 V). Above this voltage the input
device becomes reverse biased and the input current
drops. to the leakage of the reverse biased junction
«O.l·/-IA).
-p
s
-.'"
a:
1.2
3.6
1.8
~
!!'
0
,;'
,D.4
"L~ V
Vso
_
u..
0;
o
at)
N
u:....I
.......
0)
oat)
(Continued)
-15V
10M
S2
S3
s.
1k
sj ",","'--<:1-"'1'>0_
S2
sj
S4
,,....
u:....I
AD
L ____ _
At
5Vo-~------------------,
AO
Al
~
en
oat)
C'?
u:
,....I
.......
CLOCK
,en
MSB
o
at)
5V
N
u:....I
14
DIGITAL
OUT
r-----------~CLK
.......
Q
112 MM74C74
en
o
at)
2"
10k.
,....
LSB
u:....I
O.llJf
*
•
•
fCLOCK max = 200 kHz
The LF352 instrumentation amplifier is auto zeroed during offset correction cvcle of the LF13300 AID
•
The system accuracy will mostly depend on the instrumentation amplifier gain linearity
FIGURE 120.4-Channel Differential Multiplexer with Auto Zeroed Instrumentation Amplifier and 12-Bit AID Converter
DC
PO
J--'-'==--I'I
RR ________~r-l~
______
n
I
~rl~
______
I
~rL
n
r
~___.....r
P~~;~ IL.______...
AO ________________.....
PO: Polarity Oetection
OC: Offset Correction
R R: Ramp Reference
For more details, see LF13300 data sheet
. • , ________________________________-..1
ENABLE
..J
AV IS1-Sj)
u
\..f.,
U
\..f.
AvIS3- Sj)
L
\
FIGURE 12b. System Timing Diagram for Differential MUX
5-82
Schematic Diagrams
5-83
LF1150S/LF1250S/LF1350S,LF11509/LF12509/LF13509
DA
52A
...
C/)
53•
52.
S1B
DB
o
':T
CD
3
=:
III
~O-
o
-----,.--~.~~.~------
C
u:o~~~
iii'
co...
III
3
UI
c=;
o
~
013
:;'
cen
eo
EN
':'
en
~
A'
-VEE
GND
LF11509/LF12509/LF13509
MM450/MM550, MM451/MM_551,
MM452/MM552, MM455/MM555 MOS Analog Switches
General Description
•
•
The MM450, and MM550 series each contain
four p channel MOS enhancement mode transistors, built on a single monolithic chip. The four
transistors are arranged as follows:
MM450, MM550
•
Dual Differential
Switch
Four Channel
Switch
Four MOS Transis·
tor Package
Three MOS Transistor Package
MM451, MM551
MM452, MM552
MM455, MM555
Large Analog Input Swing
±1O Volts
Low Supply Voltage
VBU LK = +10 Volts
VGG = -20 Volts
-10V
150n
Low ON Resistance VIN
+10V
75n
V IN
200 pA@25°C
Low Leakage Current
•
• Input Gate Protection
• Zero Offset Voltage
Each gate input is protected from static charge
build-up by the incorporation of zener diode protective devices connected between the gate input
and device bulk.
These devices are useful 'in many airborne and
ground support systems requiring multiplexing,
analog transmission, and numerous signal routing
applications. The use of low threshold transistors
(VTH = 2 volts) permits operations with large analog input swings (± 10 volts) at low gate voltages
(-20 volts). Significant features, then, include:
The MM450, MM451, MM452 and MM455 are
specified for operation over the _55°C to +125°C
military temperature range. The MM550, MM551,
MM552 and MM555 are specified for operation
over the -25°C to +70°C temperature range.
Schematic and Connection Diagrams
Dual·ln·Line and Flat Package
Note 1: Pms1 ~nd8tDnnettedtocaseand
dev,cebulk,DramandSoufcemaybemtelchanged.
MM452F, MMS52F.
Note 2: MM452D and MM552D (dual-m-Ime p'ckages)
have same pm connections a& MM452F and MM552F
shown above.
Order Number MM452F or MM552F
See Package 23
Order Number MM452D or MM552D
See Package 14
Metal Can Package
Metal Can Package
Metal Can Package
To,viEW
OUTPUT
ISaURel)
IULK
lUll
Note: Pm 5 connected to Clse and device bulk.
Notl:Pm5connectedtocaseanddevice
bulk. Dram and Source may be IOterchanged.
Order Number MM450H or MM550H
See Package 1
Order Number MM455H or MM555H
Sae Package 1
Note: Pm 5 connetted to case and devite bulk.
Order Number MM451 H or MM551 H
See Package 1
Typical Applications
EQUIVALENT
rr
I
I
I
TOGGLE
INPUT
......
o--i-+--+--4I~-t-+--t
o--t-...-+---t-..I
DPDT Analog Switch
5-85
I
_J
IL ______ _
SWITCH #1
OUTPUT
I
I
SWITCH #2
OUTPUT
Absolute Maximum Ratings
MM450, MM451 , MM452, MM455
Gate Voltage (VGG)
Bulk Voltage (VBULK)
Analog Input (VIN)
Power Dissipation
Operating Temperature
Storage Temperature
MM550, MM551, MM552, MM555
+10Vto-30V
+10V
+10Vto-20V
200mW
_25° C to 70° C
--65° C to +150° C
+10V to-30V
+10V
'+10V to -20V
200mW
-5SoC to +12SoC
--6SoC to +150°C
Electrical Characteristics
STATIC CHARACTERISTICSTNote
1)
PARAMETER
CONDITION
Analog Input Voltage
Threshold Voltage (V GS(T»
VOG = 0, 10 = 1 IlA
ON Resistance
V IN = -10V
ON Resistance
OF F Resistance
Gate Leakage Current (I Gsa)
Input (Drain) Leakage Current
MM450, MM451, MM452, MM455
MIN
Output (Source) Leakage Current
MM450, MM451, MM452, MM455
Output (Source) Leakage Current
MM450
MM451
" ,
MM452, MM455
MM450, MM451, MM452, MM455
----....
~,'
Output (So'urce) Leaka~e Current
MM550
\
MM551
MM552, MM555
UNITS
V
150
600
V IN = Vs.s
75
200
V GS = -25V, Vas = 0, T A = 25°C
10 10
20
n
n
n
1.0
"
2.2
V.
pA
nA
.025
.002
.025
100
1.0
1.0
Il A
TA = 25°C
TA = 70°C
0.1
.030
100
1.0
nA
IlA
TA = 25°C
.040
100
nA
TA
TA
TA
TA
,
MAX
±10
3.0
T A = 25°C
T A =85°C
TA = 125°C
Input (Drain) Leakage Current
MM550, MM551, MM552, MM555
TYP
= 85°C
= 85°C
= 85°C
= 12!i°C
,
-
TA = 70°C
,,1"'A"'- 70°C
;'1 TA = 70°C
ilIA
1.0
1.0
1.0
1.0
IlA
IlA
J.l.A
IlA
1.0
1.0
1.0
IlA
IlA
IlA
\
DYNAMIC CHARACTERISTI<;:S
Vos = -10V, 10 = 10 mA
f = 1 kHz
Large Signal Transconductance
pmhos
CAPACITANCE CHARACTERISTICS (Note 2)
PARAMETER
DEVICE TYPE
Analog Input (Drain) Capacitance (C oa )
ALL
Output (Source) Capacitance (Csa )
MM450,
MM451,
MM452,
MM455,
MM450,
MM451,
MM452,
MM455,
Gate Input Capacitance (C Ga )
Gate to Output Capacitance (C Gs )
'.
MIN
TYP
MAX
UNITS
8
10
pF
MM550
MM551
MM552
MM555
11
20
7.5
7.5
14
24
11
11
pF
pF
pF
pF
MM550
MM551
MM552
MM555
10
5,5
5,5
5.5
13
8
9
9
pF
pF
pF
pF
3.0
5
pF
ALL
Note 1: The resistance specifications apply for -55°C S; T AS; + 85°C, VGG ~ -20V, V auLK ~
. +10V. and a test current of 1 rnA. Leakage current is measured with all pins held at ground except
the pin being measured which is biased at -25V.
Note 2: All capacitance measurements are made at 0 volts bias,at 1 MHz.
5-86
Typical Dynamic Input Characteristics
ITA = 2SoC Unless Otherwise Noted)
CONDITION I:
ANALOG INPUT VOLTAGE
AT +10 VOLTS
Dynamic Ron
10.000
VSB '" +tOV
10 r-::'-....,."c--:7""""~="T7TTm
1=
1
T
V,.
V
+ I O V u r OU'
J
~
1000
==
~TAo-SSOC __
"
TA 02S"C 'rTA08S"C -
c
a:
;;::.
~
100
V••
'--
VB8 '" +lDV
. VIN "+lDV
10
+8
-16
-8
-22
-0.6
-02
CONDITION 2:
ANALOG INPUT VOLTAGE
ATOVOLTS
Ron vs VGG
10.000
V8s +10V
1, vou,
ovur
V,.
T
r----r-T""C-....",,-~
TA '"-2S"C
I
+7 ~TA' -SS"C
c
rE
~
100
10
o
-4
-8
.... ::::::
-16
-\2
10 LA~~-J-J~~~~-J
+0.6
+1.0
-1.0 -0.6 -02
+02
-20
'V,. (V)
V•• (VI
CONDITION 3:
ANALOG INPUT VOLTAGE
AT -10 VOLTS
.~namiCRon
10
100.000
Vsa =+lOV
VIN = -lOY
I
c
rE
~
1000
T.08SoC ~
t7='T. '2S"C
-SSOC- :
WT..
= ,
F~•• o-It
;:;;2:
10
-1.0
100
-16
-18
-17
-20
-19
J•• 10 _116V
I
-
.::F.;tio
4'
rt
I
I
-0.6
-4S :-IV.! •
, . -13.5
~ -35
-1.S
-10
-'12
VaG IV)
-16
-20
-20
VDS
~
-
6.0
a:
4.0
to
-60
~
-80
-100
DRAIN TO SOURCE VOLTAGE - VOL TS
5-87
V•• 0 -20V-
-02
+0.2
--
--
+D.6
-2~V
+1.0
I
rV.s ;OV'
I
I
I
:- .....
-40
8.0
3z
;;:
-6
-4.S
-5
I
VaG'" -lBV
VaG" -19V-
ill
a:
",.. :!.-r-
-20
J
DS ;
t-
~~
~ -15
-
Vas '" OV
I:::::::::=:
~~
~ -3D
z -25
~
~15VI;::: :::::.~
~;;;.
~ I!iE: -~
Drain Current vs
Gate To Source Voltage
10
--f:'F--
-40
-lOY
t:.V1N (VI
Typical Drain Characteristics
t-
'"
I
VaG (V)
-so
VOUT
I I
,-
-
V••
I
Vas'" ·,OV
Y,N o-IOV
8
10.000
-8
+1.0
~T. '8S0~~
1000
V••
-4
+0.6
Dynamic Ron
10
8
=+tOY
E
r= =v,. oOV
Yas
+02
.1V1N «V)
V•• (V)
2.0
It'
-1.0
-2.0
"
-3.0
-4.0
-S.o
V., - GATE TO SOURCE VOLTAGE - VOLTS
Typical Input Capacitance Characteristics
MM450. MM550
MM451. MM551
C IN vs V IN
CINVS V IN
Va." +10
VG~' ~20V
;;:
.!!
J
FV•• --l0V
10
[
1
-10
-6
VOG
'
-"
J
+iov
+2
.~GG
•
_I -~GG
i-jOY
.... ~
VaG:: -lOV
I
10
VaG"
f= f= ;:::
VB.;:: .10V
50
40
30
20
.....
-20V.
J
ov
10
VGG
i
VGG:' +10V
-I-
III
-2
CINvSV IN
==t=F=f Vas" +1DV
~
'== F=
VGG " OV
='" f""'
50
40
30
20
~
MM452. MM552. MM455. MM555
"
VGG
IF != ::::;
-10V
..
ov
+&
+to
-10
-6
-2
. +2
Y'N (VI
Typical Applications
+6
+10
-10
t
i
~
.~
-6
-2
oo l" l V
+2
+6
+10
Y'N (V)
(Continued)
f""M"M45t"-------i
. - - -_ _...,1
...----..':
1
VIDEO
OUTPUT :r1
VIDEO
INPUT:::1
1
VIDEO
VIDEO
INPUT =1
OUTPUT
I
OUTPUT #2
I
I
_J
TOGGLE
INPUT
4--Channel Multiplexer·
DPST High-Frequency Switch
*ExpansionlO Ihe number of data mput lines is
PD5S1b1ebV using multiple level setlesswitches
aliDWingthesamedecodegateslobeusedfor
all lower rank decodmg.
5-88
INTELlIGENCE
MM454/MM554 4-Channel Commutator
General Description
The MM454/MM554 is a 4·channel analog com·
mutator capable of switching four analog input
channels sequentially onto an output line. The
device is constructed on a single silicon chip using
MaS P Channel enhancement transistors; it contains all the digital circuitry necessary to sequen·
tially turn ON the four, analog switch transistors
permitting multiplexing of the' analog input data.
The device features:
• All Channel Blanking input provided
"! Reset capability provided
• Low ON Resistance
In addition, the MM454/MM554 can easily be
applied where submultiplexing is required since a
4: 1 clock countdown signal is provided which can
drive the clock input of subsequent MM454/MM554
units.
±10V
500 kHz
200 pA
50nA
• High Analog Voltage Handling
• High Commutating Rate
• Low Leakage Current (T A : 25° C)
(T A : 85°C)
200n
The MM454 is specified for operation over the
-55°C to +125°C military temperature range. The
MM554 is specified for operation over the _25°C
to +70°C temperature range.
Schematic and Connection Diagrams
ANALOG
INPUTS
4
ANALOG
OUTPUT
CLOCK
INPUT
OUTPUT
4:1
COUNTDOWN
-------......J
RESET'---....
Flat Package
NOCONNECTlON-'-;::===L_..JC==::::;""- v••
1-_____-'-+""_ QUlPUT4 I COUNTDOWN
CLOCK INPUT
.-_____+,,'-"0 1 ANALOG INPUT
RESET
L.JJr----t"- NO 2 ANALOG INPUT
All tHANNElBLANltlNG
NO J ANALOG IN'ut
NO 4ANALQGLNPUT
v,,-!._ _ _....I
L.._ _-'-_ANAlOGOUJPUT
Note: Pm 1 connected 10 case and to device bulk. Nominal Operating Voltages: VaG'" -2.4V;
VDO =OV; Vss = +12V, Reset Bias =+12V IOV fOf Rent), all channel blanking bias'"
+12V (DVforblankmg)
Order Number MM454F or MM554F
See Package ,23
5·89
Absolute Maximum Ratings
(Note 1)
+10V to -30V
+10V
+10V to -2QV
200mW
-55°C to +125°C
-25°C to +70°C
-65°C to +150°C
Gate Voltage (V GG)
Bulk Voltage (Vss )
Analog Input (V IN )
Power Dissipation
Operating Temperature MM454
MM554
Storage Temperature
Static Characteristics
(Note 2)
CONDITION
PARAMETER
Analog Input Voltage
ON Resistance
ON Resistance
OF F Resistance
Analog Input Leakage Current
Y'N
MIN
= -lOY
170
90
10 '0
.050
.006
.0001
.030
0.100
30
.0001
.030
Y'N = Vss
MM454
MM454
MM554
MM554
Analog Output Leakage 'Current MM454
MM454
MM554
MM554
V ss Supply Current Drain
VGG Supply Current Drain
TYP
T A = 25°C
TA = 85°C
TA = 25°C
TA = 70°C
TA = 25°C
TA = 85°C
TA = 25°C
T A = 70°C
Vss = +12V
VGG = -24V
3.8
2.4
MAX
±10
600
200
100
1.0
100
1.0
100
1.0
100
1.0
5.5
3.5
UNITS
V
n
n
n
nA
IJA
nA
IJA
nA
IJA
nA
IJA
mA
mA
Capacitance Characteristics
PARAMETER
CONDITION
Analog Input Capacitance Channel OFF
Analog Input Capacitance Channel ON
Analog Output Capacitance
Clock Input
Reset Input
Blanking Input
Clock Characteristics
MIN
=0
liN = 0
liN = a
Vel = +12V
VRESET = +12V
VBlANK = +12V
liN
TYP
MAX
UNIT
4
6
pF
20
24
pF
20
24
pF
2.0
pF·
2.0
pF
2.0
pF
(Note 3)
PARAMETER
CONDITION
Clock Input (HIGH)(')
MIN
TYP
Vss - 2
Clock Input (LOW)
-5
Clock Input Rise Time (POS GOING)
0
UNIT
Vss
V
+5
V
20
IJsec
No requirement
Clock Input Fall Time (NEG GOING)
Countdown Output (POS) V OH
Vss -2
Countdown Output (NEG) Val
Vss
0
Maximum Commutation Rate
0.5
+10.0
Vss
+12
.
Note 4: Logic input voltage must not be more positive than VSS.
5-90
V
V
MHz
2.0
Note 1: Maximum ratings are limiting values above which the device may be damaged. All voltages
referenced to VDD = O.
.
Note 2: These specifications apply over the indicated operating temperature range for VGG = -24V,
VDD = OV, VSS = +12V, VRESET = +12V, VBLANK = +12V. ON resistance measurea at 1 mA,
OFF resistance and leakage measured with all analog inputs and output common. Capacitance measured
at 1 MHz.
Note 3: Operating conditions in Note 2 apply. VSS to VDD IOV) voltage is applied to counting and
gating circuits. VGG is required only for analog switch biasing. All logic inputs are high resistance and
are essentially capacitive.
MAX
+14
V
Typical Performance Characteristics
RON vs Analog Voltage
...
"z
In
'"
3D
260
Voo =-oV
~:~L:K_;;~2V
220
iiia:
~l
"='";, 140
!::a:
f'
i!i
"'"
'"
'"
"
I
1A '" +85"&
'l. I
"-lET.....
"""-j.,
100
J
TA - +25"C
.:r--
TA - _55°C
Z
28
26
24
22
20
lB
16
14
12
10
_
Vr' i+ 12V . -
1\
lBO
-
f- f-
r--.
r--r--.
I"-
I I I
60
-10 -8 -6 -4 -2
r-r- I- JHA~NEt "O~" t-:; io-"r--
..-
B
....
r-
CHANNEL "OFF;;';"~
6
4
2
o
-10 -8 -6 -4 -2
0 +2 +4 +6 +8 +10
V," ANALOG INPUT VOLTAGE IV)
Minus V,N (max) vi; VGG
Plus V,N (maxI vs "BULK
v
14
13
~
12
?
~
~
,:
11
10
+9
V
+9
V
V
V
0 +2 +4 +6 +8 +10
V," ANALOG INPUT VOLTAGE IV)
-3~
-2B
-24 l - TA
" +85~C
1A =+25°C_
~ -16
0
,:
W
IA!
-20
-12
~
¥F r--T
A :
-55"C-
I2:i
-8
-4
o
10
11
12
13
14
V," MAXIMUM POSITIVE GOING
ANALOG EXCURSION IV)
o
-2 -4 -6 -8 -10 -12 -14 -16 -18 -20
V," MAXIMUM NEGATIVE
ANALOG EXCURSION IR," -I KllI iv)
Timing Diagram
CLOCK 0
IN 1
CH3
O~:
~:
___.....r l...___......n'--__-"'n'--__......rL
n
n
n
r
OUTPUT
"0"
COUNTDOWN "I"
NOTE: "0" LEVEL: +12V
"I" LEVEL' OV IGNU)
5·91
FEY Application Guide
National Semiconductor manufactures a broad line of
silicon Junction Field Effect Transistors (JF ETs).
National's JFETs provide excellent performance in many
areas such as RF amplifiers, analog switching, low input
current amplifiers, ultra low noise amplifiers and outstanding matched duals for operational amplifiers
input applications_
The following chart is a guide to enable the user to
determine what parameters are important in each
application_
APPLICATIO!,!S AND THEIR PARAMETERS
LISTED IN APPROXIMATE ORDER OF
IMPORTANCE
LOW
FREQUENCY
AMPLIFIER
SOURCE
FOLLOWER
ELECTROMETER
AMPLIFIERS
LOW DRIFT
AMPLIFIER
LOW
NOISE
AMPLIFIER
HIGH
FREQUENCY
AMPLIFIER
OSCILLATOR
DIFFERENTIAL
AMPLIFIER
IOZ
YI,@loZ
en
Re(Y!s)
Yls
IVGS1-VGS21
IG. in
Re(Yis)
lOSS
AIVGS1-VGS21
IOZ
en
VGS@IOZ
YI,
NF
IG
lOSS
90S
BVGSS
VGS(OFF)
Crss
Re(Yos)
Crss
Ciss
Yls
Yls
IG
lOSS
IG
Yls
VGS(OFF)
erss
Ciss
lOSS
ANALOG AND
DIGITAL
SWITCHING
'OS(ON)
IO(OFF)
AT
Ciss
Crss
en
VGSIOFF)
lOSS
BVGSS
BVGSS
VGSIOFF)
IIG1- IG21
Ciss
Crss
VGS(OFF)
IG
VGS(OFF)
BVGSS
Yls
BVGSS
Yfsl /Yfs2
IYosl-Yos21
CMRR
VGSIOFF)
JFET Parameter Relationships
10 = loSS
(1 _
2
VGS
)
VGS(OFF)
2 lOSS
VGS(OFF) = - 9fso
Variation, of drain current with gate bias.
Square low transfer
characteristic.
Gate-source cutoff voltage in terms of lOSS
and 9fso.
Gate-source vol~age .
( ( 10)112) terms
of operatmg cur-
VGS=VGS(OFF) 1- __
lOSS
In
rent '0. lOSS.
VGS(OFF)·
9fso = K
lOSS
VGS(OFF)
and
Transconductance
at
zero gate voltage in
terms of lOSS and
VGS(off). K =
to
2.5. Typically 2 for Nchannel JFETs.
9fs = 9fso v'IO/'OSS
Variation in transconductance with drain
current.
1
ros"" 9fs
Relationship between
ros and 9fs in the triode
region (Le.. VOS <
VGS(OFF)·
ros(o)
ros "" ---=-;::..:.:"-----VGS
1 - ----'=-=--VGS(OFF)
Variation of drain resistance with gate bias in
terms zero bi as resistance
(roso)
and
VGS(OFF)·
K VGS(OFF)2
Variation of drain reros"" 10SS(VGS(OFF) -VGS) sistance in terms of
VGS. and VGS(OFF)
K = 0.5 - 0.9
lOSS·
1.1
rOST"" ros
VGS)
9fs = 9fso ( 1VGS(OFF)
Variation in transconductance with gate bias.
@
25°C '(1 +
0.007 (t.T))
6-3
Variation of ON resistance as a function of
temperature.
o
IW
LL
-:sCO
Monolithic Dual FETs vs
2-Chip Dual FETs
National Semiconductor
February 1977
C
.8.c
o
I
N
en
>
ffiLL
-:sCO
C
.~
.c
~,
oc
o
::i
INTRODUCTION
Recent development of a monolithic dual field effect
transistor offers ·distinct cost and design advantages to
the dual FET user. In this article, we have pointed out
these advantages on the basis of a comparison'that was
made between this monolithic structure and the 2-chip
dual. Finally, a typical application for this FET is
presented and evaluated.
3. Non-linear temperature tracking performance between
the manufacturer specified end point temperatures.
Recent development by National of a complete family
of dual monolithic junction FETs has virtually eliminated
these shortcomings. National's family of duals include
general purpose dual process 83 (2N3954 family, etc.),
ultra low leakage dual process 84 (2N5902 family),
wideband RF dual process \13 (2N5911 family) instrumentation dual cascode process 94 (NDF9400 family),
low noise dual process 95 (2N5515 family), and wideband chopper switch dual process 96 (2N5564 family).
While some other companies now manufacture a monolithic dual g.p. FETsimiiar to process 83, National is
the only "all monolithic" dual manufacturer. These
devices (illustrated in Figures 1a and 1b) consist of 2
diffused isolated junction F ETs ..
GENERAL
Most dual junction field effect transistors that are available today are the 2-chip variety, These devices are
costly to manufacture since 2 FET dice must be found
whose electrical characteristics match ~nder a certain set
of bias conditions. Finding the matched pair is accomplished by collecting data on a large number of dice and,
with the help of a computer, selecting 2 devices with
identical characteristics, The result is a device that
exhibits excellent end point temperature characteristics
as long as the device is .operated at the manuf~cturer
specified bias conditions, If the device is operated at
bias levels that deviate too much from the specified
conditions, the user runs the risk of poor temperature
performance. In addition, even if the device is biased
at the specified drain current operating point, there
still is no guarantee that the device will be well behaved
between the temperature end points.
Since these devices are a monolithic stnlcture, no dice
matching is required. The FETs that make up the chip
either match or they don't. Units that do not match
are eliminated at the wafer sorting stage. Units that do
match and exhibit good temperature tracking characteristics at a specified drain current also exhibit good
temperature tracking characteristics at other current
levels. These devices display a linear differential gatesource voltage relationship to temperature. This is very
important to the operational amplifier manufacturer
since it allows him to temperature compensate the dual
FET, or his entire amplifier circuit for that matter, such
that temperature coefficient approaching 0 I1V fc can
be achieved. Since the 2 FETs that constitute the
monolithic structure are isolated'by a diffusion, they can
be operated at different potentials without device
interaction. ,
The dual FET manufacturer and user alike would like
to have a device that exhibits none of the above shortcomings. They are:
1. High price because of the device selection process.
2. Poor temperatu're tracking characteristics at currents
other than those specified by the manufacturer.
. DRAIN 1
GATE 1
DRAIN 2
GATE 2
GATE 1
GATE 2
SDURCE 1
SDURCE 2
SUBSTRATE
(CASE)
FIGURE 1a. Typical National Monolithic Dual FET Cross-Section
(Processes 83, 84, 93, 94, 95 and 961
6-4
FIGURE 1b. Process 83 Equivalent Schematic
FET TEMPERATURE CHARACTERISTICS
Figure 2 illustrates. the gate-source voltage temperature
dependence of the 2N3954 (process 83) monolithic
FET for various values of drain current. All junction
FETs, whether they are monolithic or single unit construction, display similar characteristics. It becomes,
evident, upon examination of this curve, that a very
slight change in drain current results in a substantial
change in the gate to source voltage (VGS) temperature
coefficient.
biased at a 200 /lA drain current level. The curve in
will change the VGS temperature coefficient 4.8 /lV /
°e. The fact the VGS temperature coefficient can be
predictably changed by slight variation in the drain
current implies that the differential gate-source voltage
temperature coefficient can be adjusted to 0 /lV fe by
a change in drain current. A 2-chip dual FET can also be
temperature compensated in this same manner provided
the differential VGS temperature coefficient i's constant
at all temperatures. The temperature coefficient of the
2-chip system, however, is generally not constant over
the specified operating temperature range, therefore
/
o
200
400
BOO
FIGURE 2. Gate-Source Voltage Temper.
atura Coefficient vs Drain Current (Single
Devicel
<
en
NI
o
~
-"
"C
C
C
-
Q)
1.5
..
",-
~
0.5
>
>
1.5
2.5
, 2
101 = 500 "A
vOG = 20V
I-''''F'''-f--f-
E
I,/J
:; -0.5
>
-1.0
/
~
-1.0
-1.5
V~
Vi
"II
VOG = 20V
101 = 500.."A
-2.0
-75 -50 -25 0 25 50 75 100 125150
TEMPERATURE I'C)
FIGURE 7. Differential Gate-Source
Voltage vs Temperature for the Sa"ma
2-Chip Dual FET in Figure 5, Only the
Drain Current is 500 IJA
-ca
::::I
C
Co
.c
(J
I
N
en
>
~
-ca
LL
Note that the monolithic dual exhibits good .Il.VGS
temperature characteristics (TC "" 15 IJ.V fC) while the
2·chip dual has a temperatur.e coefficient greater than
50 IJ.vtC. The data displayed in Figures 4-7 is for 2
specific devices; however, it is representative of the data
accumulated on a number of process 83 and 2·chip
dual FETs.
of the device. The ,.Il.VGS error will disappear once the
devices are again in thermal equilibrium. The time for
the 2·chip dual FET to reach thermal equilibrium, after
a thermal transient, is considerable since the .FET chips
making up the 2·chip dual are located some distance
apart. On the other hand, the monolithic structure
recovers from thermal transients very rapidly because
the 2 FETs, constituting the chip, are in intimate contact.
Another point that warrants discussion is the fast
thermal transient response of the monolithic dual FET.
This type device is generally employed as the input
stage for an operational amplifier; therefore, it may be
subjected to electrical overload such as input voltage
transients. This condition causes l'side of the dual FET
to dissipate. more power than the other, which in turn
results in a temperature differential between the 2 sides
APPLICATIONS
A typical operational amplifier application is illustrated
in Figure 8. This circuit employs the 2N3954 monolithic
dual FET. as the input device. The drain current level
is set by FET 02 and resistor RX. FET 02 is a 2N5457.
This device exhibits a 0 TC drain current operating point
16V
R3 TEMPERATURE
500
COEFFICIENT
ZOT
AOJ
::::I
C
.~
.c
OUTPUT
-o
~
c
o
:E
RX
Z5ppmfC
SELECT RX FOR
ZV DROP ACROSS Rl
-15V
Note 1: 'The temperature coefficient can typically be adjusted
(by R3 and R41 to less than 5
from _25°C to +85°C.
,..vrc
Note 2: The common-mode rejection ratio is typically greater
than 100 dB for input voltage swings of 5V.
FIGURE 8. Low Temperature Coefficient Operational Amplifier
15V±1%
V,No---.....,
500
0.1%
-15V ±1%
FIGURE9
6·6 .
at about 400 /lAo In. addition, the Q2-RX combination
exhibits an output impedance typically greater than
10 Mn. This characteristic, coupled with the high
output impedance of the 1M F3954, contribute to a
CMRR of greater than 100 dB for this amplifier. Input
offset voltage can be adjusted to 0 with R4. This control
exhibits sensitivity of 2 mV Iturn. The temperature
coefficient Can be compensated by R3 with an approximate sensitivity of 5 /lV fClturn. The temperature performance of a typical amplifier of this type is illustrated
in Figure 10.
2.5
~w
'"~
This, of course, makes the monolithic dual less expensive
then its 2-chip counterpart. And finallY, the monolithic
dual' FET maintains excellent tracking characteristics
when the device is subjected to thermal transients or
momentary voltage overloads. This is not the case with
the 2-chip dual since these devices are thermally isolated
from one another.
5pvrc
LIMITS
~
co
0.5
l;
-0.5
*
l\:-...
Note 1:
~
I- tI- i=""
t- t- ~
> -1.5
-50 -25
0
25
50
15 100 125 150
CONCLUSION
The junction isolated dual monol ithic junction F ET does
exhibit a more linear ~VGS temperature relationship
than does the 2-chip dual FET. In addition, the monolithic structure exhibits good temperature tracking
-
;:;:
=r
n'
cc
-
Q)
rtI
-I
I
(')
(TC)l = IAVGS(TO) - AVGS(Tl)1
TO-Tl
x 106 p.vtc
IAVGS(TH) - AVGS(TO)I
(TC)H =
2:
"C
TEMPERATURE rCI
FIGURE 10. Input Offset Voltage vs
Temperature
::s
o
I\)
Definition of temperature coefficient:
I
-1.0
==
o
en
<
en
1.5
co
>
!;;
~
characteristics at drain currents other than the specified
ID. This is generally not the case for the 2-chip system.
Since all National duals are monolithic structures, the
cumbersome process of matching individual dice is not
required.
x 106 1'VtC
TH-TO
Where TO = 25°C
TH - High temperature limit (TH = 85 or 125°C)
TL - Low temperature limit
AVGS(TO) in the differential gate·source offset voltage
at TO (volts)
AVGS(TH) - Differential gate-source ollset voltage at TH
AV GS(T l) - Differential gate-source offset voltage at T l
C
C
-
Q)
-co
Why Use Cascode
National Semiconductor
FET Brief 2
Mike Turner
March 1977
National Semiconductor's cascode dual JFET is a
unique structure in which each half of a monolithic dual
is actually 2 FETs connected in cascode. Figure 1a and
1b show the comparison. The advantages of a cascode
structure are low dynamic leakage (lG) and greatly
improved common·mode rejection ratio. National's
processes 84 and 94 use the cascode configuration.
Table I compares popular junction dual devices available
in the marketplace.
Dual FETs?
=
C
CI)
"C
oCJ
o'"
CO
CI)
'"
::J
It is important to remember that IG is a dynamic charac·
teristic. The data supplied by major FET suppliers
clearly shows the effect of operating voltage and current
on IG and the considerable difference between IG and
the static parameter IGSS .
~
.r:.
3=
02
01
Figure 2 explores the differences between cascode devices
such as NDF9406-NDF9409 and a triode configured
2N5196. It is easily seen that severe gate current modu·
lation will result in triode devices with even relatively
small change in VDG. Gate current variations will cause
variations in offset bias currents, offset voltage and
common·mode rejection. This is especially true in high
impedance circuits where gate impedances are not
matched.
G2
Gl
~Sl
S2
FIGURE la. Cascode Configuration
lk
_D~~2_,
GI
~
:
.:
L _ _ _ -.I
.
~
T~IOOE 2~51961
100
I-
iii
a:
G2
a:
...
10
::0
/
w
I-
<>:
'"I
51 S2
0.1
the cascode FET device offers a significant improvement in gain/input current ratio when compared to
standard FET triodes_ Specifically, the NDF9406 series
devices are specified at IG < 5 pA under operating
conditions, and they exhibit operating 9fs of 1200 Jlmho
typical. This compares favorably with non·cascode duals
exhibiting 3-10 times the IG.
CATOET9406
I--"
E
FIGURE lb. Triode Configuration
o
/
10
20
50
The second major advantage of the cascode configuration is improved common-mode rejection ratio. The
input FETs are effectively shielded from large changes in
operating point by the drain load FETs.
TABLE I
BV
40
FIGURE 2. Typical Gate Current vs
Orain·Gate Voltage @ 10 = 200 IlA
Furthermore, the NDF9406 series will maintain this
low input current over a common-mode input range of
up to ±15V, while triode devices are limited to approximately ±5V for the sar;ne performance.
DEVICE SERIES
3D
VDG - DRAIN-GATE VOLTAGE IV)
2N3954-2N3958
>50V
IGVOG/10
<50 pA @ 20V/200 IlA
915 10
1000@200IlA*
2N5196-2N5199
>50V
<15 pA@20V/200IlA
>700@200IlA
NDF9406-NDF9409
>50V
<5 pA @ 35V 1200 IlA
>950@200IlA
*Limits not specified on the published data sheet.
6-8
=E
Figure 3 compares CMRR of a monolithic triode dual
The inherent matching of all devices because of monolithic construction further reduces the effects of
common-mode signals_
FET (National P831 with a cascade structure (National
P941_
::::T
'<
c:
en
CD
()
Q)
.
!g
en
n
110
1111
dVOG = 10V-20V
Q
;:::
~
100
w
80
'"'-'r
70
;:::
Q
Q
a:
w
.
120
::;;
Q
'-'
II:
II:
60
'-'
0.01
0.1
90
r
a:
a:
::;;
1.0
I I
c
I
."
~G=5_0V- 10V
100
::;;
dVDG
CMRR = 20 log dVGSI-2
CMRR = 20 log
d~VDG
I
0.1
'D - DRAIN CURRENT (rnA)
'D - DRAIN CURRENT (rnA)
FIGURE 3a_ Triode Construction
FIGURE 3b. Cascode Construction
-
Q)
!:!l
en
I I"" lIiSl-~
80
0.01
6-9
C
I
110
Q
~
CD
I
Q
Q
::;;
oCo
I
dVOG = 10V-20V
Ul
::;;
~
130
~
·'l~~G=~
90
..'"
Q
IITT -;-t-.U
Ul
II:
.
!
II
.~
1.D
en
CI)
.c ·Simple VHF"
oS Analog Switches
National Semiconductor
FET Brief 1
Mike Turner
February 1977
'i
U)
Ol
o
cac
Simple JFET switches like those in Figure 1 will toggle
at rates to about 10 MHz and switch analog signals with
frequencies to above 100 MHz. They accomplish this by
resolving in the gate-driver design the contradictory
performance goals that· even the best switching transis·
tors cannot meet.
X
CI)
VOUT
R2
Q.
.E
,-
U)
proper gate driver. The drive circuit should have a low
impedance when the JFET is turned OFF and a high
impedance when the JFET is turned ON. The low·
impedance path is needed to prevent analo'g-signal
feedthrough and. the high impedance to minimize
signal attenuation through the driver while the JFET
is conducting. A well:designed driver can do both.
The relationships among JFET. and driver characteristics
can be sorted out with the help of Figure 2, which sliows.
a typical series-pass switch and the equivalent circuits
of the JFET in its ON and OFF conditions. A JFET
operates best as a series-pass switch when the ON condition allows RON and shunt capacitance to be low, and
series-pass capacitance to be high. But in the OFF
condition, it should exhibit low series-pass mipacitance
and high series'pass resistance (ROFF). The JFET will
. have these characteristics when properly matched to
the driver.
v-o-_-....-I
8.
Series-Pass Switch
rlr'--OVOUT
a. Series·Pass JFET Switch"
SOUR"CE
RON
ORAIN
°'ic.T¥O
...""f\r-Ov+
9
dg
GATE
b.JFETOn
v-o-~----~~
ROFF
'"~"!
b. With JFET Gate Diode
FIGURE 1. High-Frequencv JFET Switching Circuits
To switch high-frequency signals, the JFET should have
low ON impedance, rds(on) or RON, and low input
capacitance, Ciss. The switch's RC time constant is
established by these 2 parameters, and they also indicate
the bandwidth capability. JFETs have been developed
that come close to being ideal, but unfortunately the
real-world nature of semiconductor devices makes it
impossible to achieve optimum values of both parameters in the same device. Low RON calls for a physically
large JFET. On the other hand, the very low capacitance
needed for fast toggle rates implies small size.
C,g
r
§"~.
Cdg
GATE
c. JFET Off
Cdg
drain-gate capacitance
Cgc
Csg
source..gate capacitance
gate-channel distributed capacitance
drain..source capacitance
Cds
ON impedance
RON
ROFF= OFF impedance
At a casual glance, gate drive impedance does not appear
very important. However, the JFET device conflict
between RON and Ciss may be overcome by using the
FIGURE 2. Series·Pass Switch and JFET Equivalent Circuits
6-10
or exceed RS in parallel with R L, but then the toggle
rate would be kept down by the very high drive
impedance.
Getting down to a low RON when the gate is turned ON
is no problem. A JFET such as the 2N4391 has a maxi·
mum RON of 30.0 (see rds(on) in Table I). However, the,
parallel capacitance in the signal path can become fairly
high-about 15 pF when drain, source and gate have the
same potential (VOS = VGS = 0). The simple answer to
this dilemma is to drive the gate with a high AC impe·
dance when the switch is closed. The shunt capacitance
will be in series with a high impedance. Virtually all of
the signal will then go through the JFET, the path of
least resistance, rather than through the gate·to·ground
connection.
We prefer the circuits in Figure 1, which are fairly fast
and not tricky. When NPN transistor Q2 is in saturation,
Ql is biased OFF through a low·impedance path. The
diode is slightly forward·biased and exhibits high capa·
citance. When Q2 turns OFF, 01's cathode is driven
positive by R 1. Now the diode is reverse·biased and
exhibits high impedance and low capacitance. The·
charge that was stored on 01 discharges into the gate
of Ql, allowing the JFET to be turned ON. Because
there is no good discharge path available to the charge
stored on Ql 's gate, the gate will "follow" any signal
swing in the analog input voltage. Adding R2 will
ensure that the gate follows the signal even during OC
conditions. Remember, however, that the R2/Csg time
constant will effect switching time and gate·source
signal tracking.
Next problem. When the switch is OFF, high·frequency
attenuation is the name of the game. It is depended
upon to prevent the signal at the input from reaching the
output. The J F ET channel is, for all practical purposes,
an-open circuit because ROFF of a quaiity JFET is over
10 12.0 although this decreases as frequency goes up.
However, capacitive feedthrough is the most significant
route across the switch. From Figure 2c,
Oon't expect just any diode to work well; 01's capa·
citance is critical and should match that of the JFET
. (COl = CQ1). One good way of making sure that the
JFET and the diode are well mated is to use the same
type of JFET for both. The gate lead is 1 electrode of
the diode and the drain and source leads are simply
tied together to form the other electrode. The circuit in
Figure Ib was optimized in this way.
CsgCdg
CFEEOTHROUGH = Cds + --=--=Csg + Cdg
Feedthrough capacitance can be significant if the gate is
not operated at AC ground. Minimizing the right·hand
term by operating the gate at AC ground allows Cds to
become the pacing. factor. If the gate is grounded, Cds
will be approximately 0.2 pF. In other words, the
effective ROFF of the switch depends directly on
circuit design, not the JFET.
Excellent high·frequency series switches can be made
with 2N4091, 2N4092 and 2N4093 JFETs. RC time
constants are short because of their low rds(on) and
capacitance, and leakage is low. The 2N4391, 2N4392
and 2N4393 series is even better, having only 100 pA
leakage and lower Ciss. Even though the 2N4416 is
classed as an RF amplifier, it is also listed in Table I to
illustrate that many of our other JFETs can solve
spedal switching problems. This one does well in circuits
requiring very low capacitance and leakage. Although
the RON of an RF transistor is not specified, it can be
estimated as rds(on) == 0.85/Yfs, which is typically
170n for the 2N4416.
Now to put these principles to work. The best high·
frequency switch is an N·channel JFET. Its gate should
be biased positive from a high·impedance source for
turn·on and biased negative through a low·impedance path
for turn·off. Orivingthe switch ON through an RF choke
sounds tempting, but it would be difficult to avoid
resonances and oscillation bursts during some switching
conditions. OC resistances could be increased to equal
TABLE I. JFETs for High·Frequency Analog Signal Switching
Crss
OR
CDGO
(MAX)
rds(onl
(MAXI
ton
(MAX)
toff
(MAX)
16pF
16pF
16pF
5 pF
5pF
5 pF
30n
50n
BOn
25 ns
35 ns
60 ns
40 ns
60 ns
Bans
0.1 nA
0.1 nA
0.1 nA
14 pF
14pF
14pF
3.5pF
3.5pF
3.5pF
30n
60n
loon
15 ns
15 ns
15 ns
20 ns
35 ns
50 ns
0.1 nA
0.1 nA
4 pF
4 pF
O.BpF
O.BpF
170n'
170n'
BVGSS
OR
BVDGO
(MAXI
IGSS
(MAXI
Ciss
(MAXI
2N4091
2N4092
2N4093
40V
40V
40V
0.2 nA
0.2nA
0.2nA
2N4391
2N4392
2N4393
40V
40V
40V
2N4416
2N4416A
30V
35V
TYPE
NO.
*This value is not specified in RF amplifier JFETs; 170n is typical
6·11
en
_.
3
CD
'C
<
::J:
."
»
:::I
Q)
5'
CQ
en
~
g:
::r
CD
til
~
E Noise of Sources
National Semiconductor
John'Maxwell
February 1977
::::s
o
til
'0
CD
.!a
o
Z
INTRODUCTION
The elimination or minimization of noise is one of the
most perplexing problems facing engineers today.
Many preamplifiers and ,components come with outstanding noise specifications, only to disappoint the
user.' The problem is the difference between specification and appl ication, as the amplifiers are specified
under ideal conditions not the real conditions, (i.e.,
a transducer connected to the input). Many times the
transducer noise.' is as' large or even greater thaI) the
amplifier noise, degrading the signal to noise ratio.
Before amplifier or component noise can 'be considered,
familiarity with the source noise is essential:
Rapidly changing network impedance' and amplifier
gain equalization combine to complicate the issue .
The total source noise in a non-ideal case can be calculated by breaking the noise spectrum into several small
bands where the noise (Re(Z)) is nearly white and
calculating the noise of each band_ The total source
noise is the RMS sum of the noise in each of the bands,
Nt-N n·
REVIEW OF NOISE BASICS
The expression does not take amplifier gain equalization
(like R IAA) into account, which will change the character of the noise at the amplifier output. By reflecting
the gain equalization to the amplifier input and normalizing the gain to 0 dB at 1 kHz, the equalized source
noise may then be calculated.
There are 3 types of transducers: resistive, capacitive and
inductive. The noise of a passive network is thermal
noise, generated by the real part of the complex impedance, as given by Nyquist's relation:
2
V,n
4kTRe(Z) Af
V n2
Mean square noise voltage (V2)
2 2
2 2
2' 2 1/2
VEa = (IA ll V N1 + IA21 V N2 + - - - + IAn I VNnl
(41
(1)
Where VEQ =, equalized source noise (/lV) and
IAn I = magnitude of the equalized gain at the center of
'
each noise band (VIV).
Boltzmann's consta~t (1.38x 1'0-23 VAStK)
Absolute tel'(lperature (0 K)
,
Real part of complex impedance (n)
Noise bandwidth (Hz)
k
T
Re(Z)
Af
SOURCE NOISE
Models are needed for capacitive and inductive systems
such that noise calculations can be made. Namely, the
real part of the impedance needs to be determined.
The noise may be represented as a spectral density
(V 2 /Hz) or more commonly in /lV/y'Hz or nV/y'Hz
and is given by:
A lumped model of a capacitive source, such as condenser
or electret microphone, consists of the microphone and
stray capacitance shunted by a load resistance.
(2)
lk
W
'"<.....
I-
co
>
W
'"2:>:
c~
I-
-
2>
We
.....
<
>
:;
Z
Re(ZI + JIM(ZI
Re(ZI =
R
1 + w2R2C2
100
,,;
IZI
10
=
(
(5)
R2
\ 1/2
1 + w2R2C'i.J
FIGURE 2. Lumpad Model of a Capacitive Microphone
CI
W
It should be noted that for any particular microphone, '
the noise of the network «C m + CS )//RU is reduced
by increasing R L because Re(Z) (the real part of the
impedance) is inversely proportional to ,R L. (see equation 5).
I
:;
1
I-'
tOO
I
lk
10k
lOOk
'1M
RESISTANCE (n)
The inductive source (phono cartridges and tape heads)
is more complex to analyze because it has a much more
complex model. The simplified lumped model of a phono
cartridge or tape head consists of a series inductance
and resistance shunted by a small capacitor. Each phono
cartridge or tape head has a recommended load con-
FIGURE 1. Thermal Noise Voltage vs Resistance
The total noise voltage in a frequency band can be
readily calculated if it is white noise (i.e.; Re(Z) is frequency independent). This is not the case for.capacitive
or inductive sources or most real world noise problems.
6-12
sisting of a specified shunt resistance and capacitance.
A model for the inductive source and preamp input
network is shown in Figure 3.
-------, r-----I
I
I
I
I
Cc
I
I
_______
~
L ______ _
INDUCTIVE
SOURCE
SPECIFIED
LOAD
This circuit is quite formidable to 'analyze and needs
further simplication. Through the use of Q equations.
a series L-R is transformed to a parallel L-R.
=>
LS
=
Q
Rp Rp =,
Lp
=
(I)
The electret or condenser microphone noise (Re(Z)) is
reduced when the load r~sistance is increased. This is.
cine of the cases when a larger resistance means lower
noise. not more noise.
FIGURE 3. Phono Cartridge or Tape Head
and Preamp Input Network
RS
Calculations of electret microphone noise wi,th various
loads and R IAA equalized phono cartridge noise is done
using equations (1 )-(7). Center frequencies and frequency
bands must be chosen first. Values of the lumped circuit components calculated and noise calculated for
each band. then summed for the total noise. Octave
bandwidths starting at 25 Hz will be adequate ·for
approximating the noise.
In this example. the microphone capacitance is 10 pF
loaded with 5 pF of amplifier and stray capacitance.
Two resistive loads will be used to illustrate the effect
R L has on the microphone noise. R L1 = 1Gll (10 9 ).
RL2 = 10Gll (10 10 ). It is assumed that there is no
gain equalization in the amplifiers that follow. The
noise calculations are summarized in Table I.
I
RC
o
RA
CA
I
The second example is the calculation of the R IAA
equalized noise of an ADC 27,phono cartridge loaded
with CA = 250 pF and RA = 47k. The cartridge constants are Rs = 1.13k and Ls = 0.75H (C c may be
neglected). The noise calculations are summarized in
Table II for this example.
(6)
wL.
:. (~:~~)
R.
•
The RIAA equalized noise of the ADC 27 phono
cartridge and preamp input network was 0.73 J1V for the
audio band. Typical high quality preamps have noise
voltages less than 1 J1V. resulting in a 3 dB or more loss
in system SIN ratio when the cartridge noise is added to
the preamp noise (in an RMS fashion).
02
Simplifying the input network to:
CONCLUSIONS
C
Zero noise sources and amplifiers do not exist. Specifying amplifier noise under ideal conditions will only
lead to ideal specifications. not a measure of actual
performance. Methods of SIN ratio measurement should
be used that reflect the tr~e performance instead of
hollow specifications.
R
L
C
REFERENCES
1. Fraim. F. and Murphy. P.• "Miniature Electret Microphones". J. Audio Eng. So .• Vol. 18. pp.511-517.
lOct.1970)
FIGURE 4_ Simplified Inductive Source Network
Re(Z)
(RXL - RXC)2 + Xt, X~
2. Hallgren. B. I.. "On the Noise Performance of a
Magnetic Phonograph Pickup". J. Audio Eng. Soc.•
Vol. 23. pp. 546-552. (Sep. 1975)
(7)
RXLXC
Z
«RXL - RXc)2
3. Fristoe. H.T .• "The Use of Q Equations to Solve
Complex Electrical Networks". Engineering Research
Bulletin. Oklahoma State University. 1964.
+xt X~)1/2
WL ,
4. Korn. G.A.' and T.M.; "Basic Tables iJl Electrical
Engineering". McGraw-Hili. New York. New York.
1965.
1/wC
The tools are now available to calculate the noise of a
variety of transducers and see how this unspecified noise
affects amplifier (SIN) performance.
5. Maxwell. J .• "Hold Noise Down with JFETs". Electronic Design. Vol. 24. pp. 146-152. (Feb. 16. 1976).
6-13
z
EXAMPLES
iii'
o.....
(J)
o
c
n
(I)
(f)
Noise of Sources
TABLE I. Summary of Electret Microphone Calculations
I Range (Hz)
I Center (Hz)
ISw (Hz)
lor RL = lGn
Re(Z) (n)
IZI(m
enz (nV/YHz)
Vnz IItV)
V~z (j.lV2)
~
25-50
37.5
25
50-1'00
75
50
100-200
150
100
200-400
300
200
400-800
600
400
800-1600
1200
BOO
1600-3200
2400
1600
3200-6400
4BOO
3200
9600-12.8k
9600
6400
12.Bk-20k
16.400
7.200
74.2M
272M
1100
5.5
30.2
19.6M
140M
560
3.96
15.7
4.9BM
70.6M
280
2.8
7.84
1.25M
35.4M
140
1.98
3.92
0.31M
17.7M
71
1.42
2.0
7Bk
8.8M
36
1.02
1.04
19k
4.4M
18
0.72
0.52
4.9k
2.2M
9
0.51
0.26
1.22k
1.lM
4.5
0.36
0.13
420
650
2.8
0.24
0.06
8M
283M
320
1.6
2.56
2M
141M
180
1.3
1.62
0.5M
70.8M
90
0.9
0.81
125k
'35.4M
45
0.64
0.41
31.3k
17.7M
23
0.46
0.21
7.8k
8.8M
11.4
0.32
0.103
2k
4.4M
5.B
0.232
,0.054
500
2.2M
2.9
0.16
0.025
122
1.IM
1.4
0.112
0.013
42
6,50k
0.84
0.07
0.005
25-50
37.5
25
0.156
0.0244
1.0244
42
1.16k
31.5
1.13k
7.42k
17M
l.l1k
1.12k
4.24
21.2
449.4
63.0
28.3k
50-100
75
50
0.313
0.098
1.09B
11.24
1.24k
8.43
1.21k
3.97k
B.48M
1.11k
1.15k
4.24
30
900
29.5
26.6k
100-200
150
100
0.625
0.391
1.391
3.56
1.57k
2.67
1.52k
2.52k
4.24M
1.11k
1.3k
4.24
42.4
179B
10.7
19.2k
3.2k-6.4k
4800
3200
20
400
401
1.0
454k
0.75 .
42.6k
22.6k
0.133M
12.4k
24.4k
14:2
B03
645k
0.154
99.3k
6.4k-12.8k
9600
6400
40
1600
1601
1.0
1.8M
0.75
45.Bk
45.2k
66.3k
41.5k
43.6k
26
20BO
4.33M
0.043
186k
12.Bk-20k
16.4k
7.2k
(I:V~z) 1/2~ 7.9j.1V
RL = 10Gn
Re(Z) (m
IZI(m
enz (nV /v'Hz)
Vnz (j.lV)
V~z (j.lV2)
(I:V~z) 1/2 ~ 2.4 j.lV
--
~
""
--------
TABLE II. Summary 01 Phono Cartridge Calculations
I Range (Hz)
I Center (Hz)'
18w (Hz)
Q=(wL,;lR s)
Q2
1 +Q2
1 + Q2/Q2
Rp(m
Lp (H)
RpllR (m
XL(m
Xc (n)
Re(Z) (m
IZI(m
enz (oV /YHz)
VN (nV)
V~ (oV2)
A2
A2V~ (nV2)
(:!:V~) 1/2 = 3 JlV unequalized noise
(:!:IAn 12V~) 112 = 0.73 JlV RIAA equalized noise
200-400
300
200
1.25
1.56
2.56
1.64
2.9k
1.23
2.74k
2.32k
2.12M
1.15k
l.77k
4.31
61
3721
3.85
13.2k
400-800
600
400
2.5
6.25
7.25
1.16
B.2k
0.87
7k
3.2Bk
1.06M
1.26k
2.97k
4.51
90.2
8136
1.66
13.5k
800-1.6k
1200
BOO
5
25
26
1.04
29.4k
0.78
lB.lk
5.BBk
O.53M
1.73k
5.59k
5.29
149.6
22.4k
0.85
19k
1.6k-3.2k
2400
1600
10
100
101
1.01
114k
0.76
32.9k
11.45k
O.265M
3.86k
l1.7k
7.9
316
99.9k
0.49
4B.9k
68.4
4678.6
4679.6
1.0
5.29M
0.75
46.6k
77.2k
38.Bk
34k
40.1k
23.5
1994
3.9BM
0.019
76k
-t
:::T
National Semiconductor
John Maxwell
February 1977
The Noise Figure Fallacy
CD
Z
o
iii'
CD
"TI
with the spectral density given by e~
Noise Figure (NF) can be one of the most misleading
. specifications confronting the engineer today. Noise
Figure is defined as the ratio of total output noise power
to the output noise power of the source.
-
enR = (V~/Af)
1/2
(3)
CD
"TI
lk
NF = 10 Log
Total output noise power
(1)
400
A minimum NF exists for any amplifier, but is usually
far removed from the actual operating conditions. This is
where the problem begins. Lowering the NF doesn't
always lower the noise which is what the engineer is
really interested in. NF only gives the designer insight
into the ratio of the amplifier noise to the source noise,
not the input noise of the amplifier or the signal to
noise ratio.
.
100
Output noise power of the source
~:>
.s
ex:
c
."
-Q)
Q)
(')
'<
40
./
V
10
4
./
Amplifier noise performance is adequately described by
modeling the noise sources as a series voltage generator
at]d a shunt current generator with a series voltage
generator for the source resistance noise.
I
'"
100
Ik
10k
lOOk
1M
RESISTANCE (n)
FIGURE 2. Thermal Noise vs Resistance
Using the model of Figure 1, an expression of noise
figure in terms of the noise generators can be developed.
The. noise power of the source can be found by using
Nyquist's relation.
e~t = e~A + e~A + i~A A~
ant = total input noise voltage (nV l..jHzl
enA = amplifier noise voltage (nV/..jHzl
-
inA
=
V~
Source Noise Power = - R2
amplifier noise current (pA/.JHZJ
"nA =, source resistance thermal noise (nV l..jHzl
<"
FIGURE 1. Simiplified Amplifier Noise Model
__
e~RM
(4)
R2
with the total output noise power at the input of the
amplifier of:
The ampl1fier noise data is found on vendor data sheets
in the form of en and in vs frequency for bipolar transis·
tors and en vs .frequency for FETs and FET amplifiers.
e~RAf e~AM
.
Total nOIse power = ~ + ~ + i~A R2 M (-5)
Current noise depends on amplifier input bias current
which is only a few picoamps for FETs and is therefore
negligible. However, bipolar transistor amplifiers have
bias currents into the microamp range where current
noise is significant.
Yielding
NF = 10 Log
(6)
The thermal noise of the source resistance is given by
Nyquist's relation.
V2R
v~
Noise figure has a minimum that occurs at an optimum
source resistance Ropt.
4kTRAf
(2)
2
VR
mean square noise voltage (V 2 )
k
Boltzmann COllstant
(1.38 x 10-23 VASfK)
T
absolute temperature (0 K)
R
resistance (n)
Af
noise bandwidth (Hz)
enA
Ropt= -.InA
(7)
Arti.fically changing the source' resistance for minimum
NF will generally increase the circuit noise as demonstrated by the following example.
6-15
cS'
c
~r-------------------------------------------------------------,
CJ
.!
~
~
:::s
m
i!
Q)
source resistance (not affecting gain). The other case will
only have the transducer connected to the input.
Example:
An amplifier is needed to boost the signal from a
resistive transducer.
We will neglect the noise of the feedback resistors and
determine the input noise and N F for both configurations using equations (1 )-(6).
Amplifier requirements
Case A, minimum NF
Av= 100
f = 10 Hz to 10 kHz
Transducer = 10 kn
Total input noise Vn = ent (At)
NF= 0.06dB
.~
o
z
Q)
= 14/N
Case B, minimum noise
Amplifier-LF356
Noise data, en = 12 nV!YHz @ 1 kHz
in = 0.Q1 pA/YHz @ 1 kHz
Vn = 1. 7 11 V
NF = 3 dB
..c
I-
1/2
Noise figure is only a measurement of the amplifier
noise relative to the source noise. The example used
was radical, but it illustrated a very important point.
Resistance should never be added in series with the
source to improve the NF. The NF will improve but the
input noise will suffer, degrading performance. Total
input noise should always be considered allowing
problem sources to be identified and minimized to meet
the.~ystem's specific noise requirements.
The optimum source resistance for the amplifiar is
found to be 12M (using equation (7)). Using Figure 2,
the noise of the transducer is 12 nV!YHz and the noise
of the optimum source resistance is 140 nV!YHz.
Using the non·inverting amplifier configuration, we'll
view the effect of Ropt. In one case, resistance will be
added to the source to equal the amplifier optimum
1
T
a. Minimum NF
b. Minimum Noise
FIGURE 3. 2 Amplifier Solutio,:1S
6-16
ro
National Semiconductor
John Maxwell
March 1977
Low Noise FET Amplifiers
~
Z
o
Ur
C'D
."
INTRODUCTION
Dis!;rete JFETs reign supreme as low noise amplifiers.
JFETs are virtually free from the problems of current
noise, popcorn noise and limited bandwidth which
plague bipolar transistors and bipolar input op amps.
current to voltage .( I/V) amplifier, circumventing the
limited load resistor.
CD'
Cil
Vo
Vi 0-..........
AV =_
12
gmRd
1 +gmRs
10
"iii
~
w
a:
=
'"u::
.
a. Single FET Stage
w
en
4
V+
o
Ik
O.lk
lOOk
10k
SOURCE RESISTANCE (n)
FIGURE 1. Bipolar and JFET Transistor Noise Comparison
Vo
Vi
Ik
400
~A3140
........
~ 100 ii.,LM141
>
.:.
40
~.
.......
I
If
10
4
--
PF5102
10
........
100
b. FET with IN Amplifier
LF356
FIGURE 3. FET Gain Stages
~
-,
OR NP05565
lk
10k
lOOk
FREOUENCY (Hz)
FIGURE 2. Discrete JFET and Op Amp Noise Comparison
l>
3
"2::;;
Unfortunately, JFETs are cumbersome to use because of
low gain and the need of extensive biasing networks.
However, monolithic op amps are cheap and easy to
use but suffer from poor noise performance. By combining JFETs with an op amp yields single and differen·
tial input amplifiers that have the best of both worlds;
low noise, high gain and ease of use.
0
!!I
In the FET/op amp configuration, the FET AC drain
current is shunted to the op amp virtual ground and
through its feedback resistor, bypassing the FET drain
,resistor, Rd. The drain resistor is used to bias the FET
in a linear region with the feedback resistor, Rf, used
to set the gain.
The main problem with JFETs is that the voltage gain is
limited by the size of the load resistance which is limited
by the power supply voltage and the FET operating
current. The voltage gain can be increased by combining
the JFET (a transconductance amplifier) with an op amp
Biasing problems associated with lot and device to device
parameter variations are minimized by biasing the source
through a large resistor to the negative supply of the op
amp. A portion of the source resistor should be unbypassed to minimize gain variations between FETs.
6·17
!Q)
!E
Q.
E
",-oVo
Vio-.....~
-15V
,a. Single-Ended
240k
15V
7.5k
Vilc~~__~_____N_P~D5~5_65
100
100
__________
~
>-..-oVo
7.5k
AV '" -500
-15V
b. Differential Input
FIGURE 4. High Gain FET/Op Amp AC Amplifiers
6-18
The single ended and differential input amplifier input
noise (FET noise current is negligible) is given by the
RMS sum of the noise generators.
low distortion or balanced inputs are of paramount
importance.
The noise of the op amp and the FET drain resistor is
reduced by the gain of the FET portion of the amplifier
9m Rd
. The noise of the feedback resistor has little
1 + gmRs
effect on the noise but in conjunction with the drain
resistor, it can have a dramatic effect on the total circuit
noise. The drain resistor is the input leg of an inverting
amplifier with the op amp and the feedba~k resistor.
This amplifier has a gain of -Rf/Rd which boosts the
op amp noise, limiting the size of Rf to about 390k.
Differential Input:
Practical low noise, high gain AC amplifiers can be built
using a low noise JFET and just about any op 'amp.
The op amp needs to meet the slew rate and bandwidth
requirements of the ci.rcuit, eliminating selected low
noise op amps or complex discrete amplifiers.
with
ent =
enf =
enA=
inA =
ens =
enR=
gm
R
total input noise voltage (nV /yHZ)
FET noise voltage (nV/yHZ)
op amp noise voltage (nV/yHZ)
op amp noise current (pA/yHZ)
source resistor 'thermal noise (nV/yHZ)
drain and feedback (Rd//Rf) resistor thermal
noise (nV/yHZ)
FET transconductance at the FET operating
current (mmho)
parallel resistance of Rd and Rf (n)
A note of caution is in order for the op amp noise.
Virtually any JFET input or bipolar input op amp can
be used without trouble, but MOSFET input op amps
should be avoided. MOSFET llf noise is one or more
orders of magnitude greater than discrete JFETs, JFET '
op amps or bipolar input op amps. MOSFETs have
llf corner frequencies (where the noise power rises as
1If) starting as high as 100 kHz. The other forms of
amplifiers have lff corner frequencies of 1 kHz and less.
Quite a difference.
The differential configuration has higher noise and lower
gain than the single-ended version, but is useful when,
1k
400
~::.s
100
40
/'
a:
~c
V
10
4
,
1
100
..;lk
10k
lOOk
1M
RESISTANCE (n)
FIGURE 5. Thermal Noise vs Resistance
>-4.....0vo
FIGURE 6. Single-Ended Noiso Model
6-19
ro
:e
z
o
ui'
(1)
."
~
»
3
-
"C
::;:
CD'
U;
..
CD
l:
o
en
E
.!!
.c
o
a..
.
CD
.'"oz
CD
.c
I
....
tiLL
-,
CD
~
.o
The Lo.w Noise JFETThe Noise Problem Solver
National Semiconductor
Application Note 151
John Maxwell
January 1976
The most versatile low noise active device available to
the'designer today is the Junction Field-Effect Transistor
(JFET). JFETs are virtually free.of the problems which
have plagued bipolar transistors-limited bandwidth,
popcorn noise, a complex design procedure to optimize
noise performance. In addition, JFETs offer low distortion and very high dynamic .range.
The noise of.a resistor may be represented as a spectral
density (V2 /Hz) or more commonly In p.V1v'Hz or
nV/v'Hz and i!t given by:
. Most· designers think of JFETs for very high' source
impedances. However, modern devices offer the designer
performance improvements over bipolar transistors in
NF for all but lowest impedance «500n) sources and
even'then may provide improved performance if popcorn
noise, bandwidth or circuit component noise is a
consideration (see Figure 1).
(2)
. It is sometimes more convenient to represent thermal
noise as noise current instead of a noise voltage. One
needs only to consider the Norton equivalent yielding a
noise current density.
.."
.
=-
z
10
~
§
"'0:
-J
ii:
~
..
~.s.
:;
co
'"
.c
....
'"........
O.lk
It
iiin
=
..
~
.....
RESISTANCE Ill)
The second basic form of noise, shot noise, is due to the'
randomness of current flow (discrete charge particles) in
semiconductor P-N junctions.
mA
10k
:;-i!=
FIGURE 2. Thermal Noise Voltage
and Current Densities' vs Resistance.
IPF51D2)
ID~l
'"=
<:
~~
.t!.;:;
10
I
N·CHANNELJFET
o
100
:f
./
.........
.\,
10
ffi
~
Q)
;i;
;:~
ffi>
I2N93D!
Ic ·111
PH.
12N5OI1)
le- lmA
100
co
.ow
..
o
1000
!:;
Em!
'-1kHz
-;- aw-211O Hz
(3)
"'
Therefore, the purpose of this article is to review low
noise design procedures and indicate the simplicity of
designing high performance low noise amplifiers with
'Iow cost JFETs .
12
e nR = (4 RkT) 1/2
R
inR
i2
lOOk
(4)
2 qlocM
SOURCE RESISTANCE In)
FIGURE 1. Bipolar and JFET Transistor
N,oise Comparison
Mean square noise current
Charge of an electron (1.6 x 10-19 AS)
loc = de current flowing through the junction (A)
M = Noise bandwidth (Hz)
I
q
REVIEW OF BASICS
Before guidelines are established for designing low noise
JFET amplifiers, a method of noise characterization
must be chosen. Designers are confronted with a multitude of different noise parameters such as Noise
Figure (NFl. noise voltage and current densities, noise
temperature, noise resistance, etc. Designers are primarily
concerned with signal to noise (SIN) ratios preferring
noise voltage, (en) and current (in) density.
As with thermal noise, shot noise may be represented
as a current density (A 2 fHz) or pA/YHZ.
(5)
It should be noted that both 'thermal noise and shot
noise are "white" noise sources, i.e., frequency indepen- dent.
Noise generally manifests itself in three forms: thermal
noise, shot noise and flicker or "l/f" noise. Thermal
noise arises from thermal agitation o~ electrons in a
conductor and is given by Nyquist's relation:
~
. '\, Vi
V~ = 4k TR.:lf
V~
k
T
R
.:If
(1 )
mean square noise voltage
Boltzmann constant
(1.38 x 10-23 VASfK)
Absolute temperature (" KI
Resistance in ohms
Noise bandwidth (Hz)
10
100
Ik
10k
GATE LEAKAGE IpA)
FIGURE 3. Current Noise vs Gate Leakage Current
6-20
-t
=r
CD
6) Stage gain
7) Power supply voltage and current limitations
8) Circuit configuration, single or dual device
The third basic noise source confronting designers is
flicker or "l/f" noise whose density is roughly inversely
proportional to frequency starting at about 1 kHz in
both JFETs and bipolar transistors and increasing as
frequency is decreased. Through careful processing,
flicker noise in JFETs has been reduced to' levels
nearly insignificant to the designer. Flicker noise in
JFETs is primarily a noise voltage and is source independent. Flicker noise in bipolar transistors is a function
of base and leakage currents increasing with increased
source impedance or operating currents.
ro
The design procedure is dependent on the type of
source and each case must be considered separately.
Resistive sources will be considered first because they
are the least restrictive for the preamplifier.
(ii'
CD
c...
Resistive Sources
Preamplifiers for resistive sources are typically. voltage
amplifiers requiring a fixed input resistance and capacitance consistent with the maximum frequency of interest
and source resistance. In most cases a resistor of the
desired value connected between the gate and ground
will satisfy the input resistance requirement leaving the
maximum input capacitance as' the major concern.
A simple noise model of a JFET or any amplifying device
may be constructed using a thermal and shot noise
source which would adequately describe its noise performance allowing signal to noise ratios to be calculated
directly.
:e
zo
."
!!II
-t
=r
CD
Z
The maximum amplifier input capac,itance is a function
of the JFET source resistor, input resistance, source
capacitance and maximum frequency. The maximum
allowable input capacitance will be used in eliminating
unsuitable JFET geometrics and optimizing the circuit
configuration. Sometimes the JFET geometry (or type)
with the lowest noise may also have an input capacitance
that makes it unsuitable. The JFET input capacitance
should be considered before noise in high source
resistance, wideband amplifier designs.
FIGURE 4. Simple JFET Noise Model
The input noise per unit bandwidth at some frequency
may be calculated from the mean square sum of the
noise sources (assuming the JFET noise sources are
uncorrelated or independent of one another).
Cin
gm RD )
1 +gm Rs
== Crs ( 1 + - - - -
+
.
Cgs
1 +gm Rs
(9)
(6)
(7)
Practically, noise sources are not frequency independent
except resistor noise with no dc bias. The total input
noise for the nonideal case may be calculated by
breaking the spectrum up into several small bands
and calculating the noise in each band where the noise
sources are nearly' frequency independent. The total
input noise would then be the RMS sum of the noise in
each of th~ bands Nl ... Nn.
=
(V~1 + V~2 + ... V~n)I/2
(ii'
CD
."
'"'I
o
-
0"
CD
3
en
o
<"
CD
,'"'I
The total noise in the same bandwidth At, where the
noise sou'rces are independent of frequency, is simply:
VNOISE
o
FIGURE 5. A Typical Resistive Sourc.
JFET Amplifier
(8)
If low input capacitance is required, a cascode config·
uration minimizes input capacitance and still allows high
gain within a device type. The casco de configuration
can also be used to reduce the voltage across a device,
reducing device heating (for high current operation) and
gate leakage currents when source impedances are very
high.
THE DESIGN PROCESS
The final circuit configuration and suitable JFET will be
determined qy the external circuit constraints.
1) Minimum signal to noise ratio (maximum amplifier
noise)
2) 'Type and magnitude of source impedance (resistive
or reactive),
3) Amplifier input impedance requirements
4) Bandwidth and maximum frequency of interest
5) Maximum operating temperature
Once the basic circuit configuration has been decided
upon or dictated by gain, bandwidth and power supply
limitations, the final JFET selection will be on noise.
Redrawing the amplifier in Figure 4 with all of the noise
sources, the total amplifier noise per unit bandwidth can
be found.
6-21
'-
CI)
-o
>
from the signal source. Assuming the gate resistor, Rg, is
so large as to not load the capacitive source, the input
noise voltage is:
C/)
E
Q)
:co
where G = Cs + Gin
''-
'0..
.~
o
Z
Amplifier with Noise Sources
·2
2]
2 + enf
2 +e 2 + -e~D
e nt = [ enig
- 2 +I n (R/IR g )
ns
,
Av
,
Q)
.c
....
....WI
LL
where:
e~f
e~s
The noise voltage of the JFET
The noise at the drain (thermal noise of
the load plus the second stage noise)
i~ (RiIlRg)2
o
..J
Q)
When the source and input capacitance are matched, the
final JFET geometry will be selected on two criteria: the
noise voltage, en, and the current noise from the gate
leakage, IG(ON), to optimize the signal to noise ratio. As
in the resistive source case, the circuit configuration and
JFET selection is an iterative process using all of the
external circuit constraints and device parameters and
limitations.
The noise of the source resistor Rs
e~D
CI)
-~
(10)
The noise of the parallel connection of
Ri and Rg
Av 2
Z
(14)
1/2
e~i9
""")
tn
.o
with an input signal of
FIGURE 6. A Typical Resistive Source JFET
Q)
The current noise contribution of the
JFET
Inductive Sources
Amplifiers designed for inductive sources (including
transformers) require fixed input resistances (as in the
resistive source case) and controlled input capacitance
(as in the capacitive source case). The input noise per
unit bandwidth will rise with increasing frequency to a
maximum value at resonance of the inductive source and
the input capacitance or when the shunt resistance of the
inductor is larger than the input resistance of the
amplifier.
When the amplifier is operated at room temperature and
moderate drain voltages, the current noise term is
usually negligible with source resistances as high as
10 Mn. Depending on the voltage gain of the stage, the
drain circuit noise may be negligible, simplifying the
input noise expression.
.c
....
(11 )
The final JFET selection will be based on the noise
requirements from the maximum allowable noise VMAX '
LUMPE-D Fer INPUT
r-------I
(12)
Depending on VMAX and e~f the source resistor may
have to be bypassed to ground to eliminate noise of the
bias resistor.
.J L ______' ___ _
Capacitive Sources
FIGURE 8. JFET Amplifier with an
Inductive Source
Preamplifiers for capacitive sources are primarily current
amplifiers requiring very high input resistance and
controlled input capacitance to match the source capaci·
tance.
The inductive source amplifier is the most difficult to
analyze due to the complex input impedance. The
input noise per unit bandwidth is given by:
LUMPED JFET INPUT
r---------
e~t - e~f + (i~f)( IZ in
I
where
12)
+ 4 kT (Re (Zln)),
(15)
Z = XCIN IIR g
and Zin = Z//(lL + Rd
L ________ _
Usually the current noise of the JFET is negligible,
simplifying the expression a little, but not much. The
optimization process for inductive sources is very com·
plex and it will require the spectrum to be' broken up
into several small bands to arrive at a final design. Gener·
ally, a JFET with a minimum noise voltage will be the
proper choice.
FIGURE 7. JFET Preamplifier with a
Capacitive Source
The source capacitance should equal the sum of the
preamplifier input capacitance and the stray capacitance
for maximum frequency response and power transfer
6·22
Transformers may be used with JFET amplifiers to
minimize noise with very low source impedances.
Transformers have both drawbacks and advantages and
both must be examined before a transformer design is
chosen. Poor frequency response, susceptibility to mech·
anical and magnetic pickup and thermal noise head the
list of disadvantages to be weighed against two very
important advantages. First, the noise voltage is trans·
formed by the turns ratio N; second, the resistance is
transformed by N 2. These can be used to advantage by
matching very low values of source resistance to a
relatively noisy amplifier and still maintaining a. good
signal to noise ratio, i.e., the total noise at the source
assuming an ideal transformer is
SUMMARY
Low noise amplifier design concepts have been intro·
duced for the three basic types of sources. Basic
parameters (C;n, en, gm) were discussed that affect
both circuit configuration and JFET type. There is no
universal low noise JFET or circuit configuration that
solves all problems. Each low noise amplifier design is
different and must be considered within its own frame·
work of performance requirements.
(16)
C.D. Motchenbacher and F.C. Fitchen, '.'Low Noise
Electronic Design," John Wiley & Sons, 1973.
....
:::r
(1)
r-
o
:e
z
o
_.
UJ
REFERENCES
CD
A. Van der Ziel, "Noise," Prentice·Hall, 1954.
c..
Richard S.C. Cobbold, "Theory and Applications of
Field·Effect Transistors," John Wiley & Sons, 1970.
'TI
!:!I
....:::rI
CD
_.
Z
o
UJ
SOME PRACTICAL LOW NOISE JFET INPUT CIRCUITS
CD
...o
C"
C-D
."
+15V
3
1.Sk
en
o
<"
CD
...
-15V
Usable Bandwidth 1 MHz:
a) Wide Sand, Low Input Capacitance, Very Low Noise Preamplifier
+1SV
+,5V
R,
R,
AV5l!-~{Rd
,m
+1SV - va - Vbe
HE;;
IID+lel
\
-15V
10 MHz bandwidth with He '" lk
ID ;; SmA forgm of 10mmho
b) Low Noise, Very Low Input Capacitance Video Amplifier
6·23
...
Q)
>
APPENDIX A
'0
(/)
E
Q)
:t.i
...o
0Q)
.~
Important National JFET Process Parameter Guide
Test Conditions Vos
= 15V. 10 = 1 mA (V GS =OV)*
PROCESS
e n @10Hz
(nV/0k1
en @ 1 kHz
(nV/0k1
50
15
5
51
55
5
10
92
B3
en @ 100 kHz
(nV/0k1
gls
(mmhol
2.5
3
Q)
3
1.3
7
4
2.5
10
4
1.5
2.4
4.5
.c
~
I
10
50
5
15
2.5
9
2
0.2
t:i
LL
5
4
2.5
2
2.5
1.5
1.3
7
2
3.5
..,
94
95
10
10
Q)
96
5
3
.~
93
15
7
,
CGS
(pFI
0.7
2.5
2 pA
10V 10pA
15V 1 nA
30
3
!!.
2
2
4
4
5
0.1
1-2
1
0.01
0.01
2.5'
15
3.5
15
3
9
1
3.2
5
10V 20pA
15V
84'
CGO
(pFI
5V
o
z
IG(ON)
(pAl
1 nA
30
10V 20pA
o
15V
2
4
1 nA
z
~
o
..J
Q)
.c
~
National JFET Process Low Noise Amplifier Guide
PROCESS
!j0
Low Noise Application
51 .
92
83
84
Single JFET
Resistive Ultra· Low
en < 5 nV/$.@
10 Hz
X
Resistive Low Freq
<20 kHz
X
Resistive Wideband
< 10 MHz
X
Resistive Wide Band
> 10 M.Hz
X
Resistive Very High
Rs >10Mf2
X
Capacitive Low C
<10pF
X
Capacitive High C
>20pF
Inductive
55
X
93
94
95
Dual JFET
, ,
X
X
X
X
X
X
X
X
X
X
X
X
X
X
6-24
X
X
X
X'
X
X
X
X
X
X
X
X
·X
96
X
X
X
X
X
X
X
X
X
APPENDIX B
::r
eD
~
NOISE PARAMETER CONVERSION
Nois~
-I
lk
~
r-
w
'"!:;'"
.,:>
Figure (N F) to an Effective en
100
o
=e
w
~
~
It is more convenient to present noise data for bipolar
transistors in the form of contours of constant noise
figure at a fixed frequency or plots of noise figure
versus frequency at a fixed source resistance due to
large values of noise current (in). Noise figure must be
converted to an effective noise voltage (enE) for com·
parisions to be made between a BJT and a J F ET or for
signal to raise ratio calculations.
o
:>
~
SOURCE RESISTANCE
en
CD
c..
(nl
"TI
FIGURE 81. Effective Noise Voltage (enE)
m
vs Noise Figure and Source Resistance (RS)
-I
I
Noise Resistance
By definition:
NF; 10 log
z
10
w
Total Output Noise Power
The effective noise voltage density (en) and noise current
density (in) are found directly by referring to Figure 1,
and reading the values for the corresponding resistances.
(B1)
Output Noise Power of the Source
From equations 1 and 2, one finds the source noise
power to be
(1 )
inR
(82)
Source Noise Power
=
(4
RKT) '/2
(3)
Z
o
Ci)'
eD
""0
C"
CD
JFET Current Noise
At low frequencies the current noise and voltage noise
sources are uncorrelated in JF ETs with the current noise
being pure shot noise due to gate leakage currents.
As frequency is increased, the current noise also increases
starting at frequencies as low as 50 kHz in some high
capacitance device types.
e~f Llf
+ ---+
Rs
(83)
It has been suggested and experimentally verified that the
noise current at high frequencies is due to increased gate
input conductance.
The noise figure (NF) can now be expressed in terms of
'the noise source generators, enR, enf and inf allowing,
an expression to convert noise figure (NF) to an
effective noise voltage (enE).
~+
eD
o
APPENDIXC
Referring, to Figure 4, the total output noise power at
the input of the amplifier would be:
NF = 10 log
::r
~
for some source resistance Rs.
Total Output Noise Power
-I
i~ = 4 KT[Re (y"f'
(C1)
Re (Y,,) is available on high frequency JFET data
sheet as the real portion of the common source input
admittance parameters. In effect the channel noise is
coupling to the gate circuit through the source·gate and
drain gate capacitances. Hence low capacitance devices
exhibit lower values of noise current at high frequencies
than- do high capacitance devices.
(B4)
yielding
(B5)
6-25
3
en
o
-<
CD
~
National Semiconductor
Application Note 32
April 1977
FET Circuit Applications
IW
LL
,----""1>--Ov+
10M
OUTPUT
INPUT
t -__-
0-.---;
10M
..... PN3684
...----4--0 OUTPUT
.,
INPUT
SAMPLE
.., r
o-....",.,..+--...- .....+-. PN3686
15V SAMPLE
HOLD
L-J __15V
Sample and Hold With Offset Adjustinent
JFET AC Coupled Integrator
This circuit utilizes the "p·amp" technique to achieve
very high voltage gain. Using Cl in the circuit as a Miller
integrator, or capacitance multiplier, allows this simple
circuit to handle very long time constants.
The 2N4393 JFET was selected because of its low
IGSS «100 pAl, very low ID(OFF) «100 pAl and low
pinchoff voltage. Leakages of this level put the burden
of circuit performance on clean, solder-resin free, low
leakage circuit layout.
lOV
10k
HI'
12M
+ SUPPLY
0.00
't'
RINC:~ I
Gos· 5 ~mhD5 MAX
CINS:0.25pF
.12N54B5
....,.2N3904
10M
10k
....-
,
.....---oVOUT
0j'l'
OUTPUT
II
1.
Low Power Regulator Reference
1k
Ultra·High ZIN AC Unity Gain Amplifier
This simple reference circuit provides a stable voltage
reference almost totally free of supply voltage hash.
Typical power supply rejection exceeds 100 dB.
Nothing is left to chance in reducing input capacitance.
The 2N5485, which has low capacitance in the first
place, is operated as a source follower with bootstrapped
gate bias resistor and drain.
6-26
"TI
m
-t
o
SHUNT
PEAKING COIL
lOV "'-.......rY"Y'Y"\_
:::;~
v'
(')
RL
C
l.9k
::;:
RFC
~Oll-P_f....- - 0 OUTPUT
CRYSTAL c:::J
10M
FET Cascode Video Amplifier
JFET Pierce Crystal Oscillator
The F ET cascade video amplifier features very low input
loading and reduction of feedback to almost zero. The
2N5485 is used because of its low capacitance and high
Yfs. Bandwidth of this amplifier is limited by RL and
. '
load capacitance.
The JFET Pierce crystal oscillator allows a wide fre·
quency range of crystals to be used without circuit
modification. Since the JFET gate does not load the
crystal, good Q is maintained, thus insuring good fre·
quency stability.
2M
O.SV
51
10M
S2C
S28
IV
Off
8M
SV
1M
1M
10V
BOOk
3.3M
I.
SOV
lOOk
100\1
aOk
500\1
10k
IOOV
S2A
10k
FETVM-FET Voltmeter
which is impractical with most vacuum tubes. The low
leakage, low noise NPD8303 is an ideal device for
this application.
This FETVM replaces the function of the VTVM while
at the same time ridding the instrument of the usual
line cord. In addition, drift rates are far superior to
vacuum tube circuits allowing a O.5V full-scale range
6-27
0
C
0
~
'"
CO
-.S:!
Q.
Q.
c(
D.Ol,uF
~NPUTo---f
10k
D.033,uF
~
'::"
:::s
'::"
CJ
10k
a..
U
>-"_-oO"TP"T
10k
~
W
U.
lOOk
D.OD33p.f
D.OD33,uF
HI-FI Tone Control Circuit (High Z Input)
The 2N5458 JFET provides tbe function of a high input
impedance and low noise characteristics to buffer an op
amp-operated feedback type tone control circuit.
• Fe
. 12Vo-_....._..T T'W·T''-_p--1I''"''"_ _ _ _ _ _
, BVPASS
+-J
r
---,
I
I
I
I
I
'Fe
I
r
I
I
'.
I
I
I
I
I
I
AGe
100 MHz Converter
The 2N4416 JFET will provide noise figures of less than
3 dB and power gain of greater than 20 dB. The JFET's
outstanding low crossmodulation and low intermodula'tion distortion provides an ideal characteristic for an
input stage. The output feeds into an LM171 used as a
balanced mixer. This configuration greatly reduces L.O ..
radiation both into the antenna and into the IF strip
and also reduces RF signal feedthrough.
6-28
."
!!l
o-...
RS
DIFFERENTIAL o--"Yv.-~"'"
INSTRUMENT
RS
INPUT o-"V'VV-~.,
OUTPUT
n
c
~
»
I
,,/
"C
"C
-n-
-
TOGGLE
DRIVE
- - - TO ADDITIONAL
_ _ _ MULTIPLEX STAGES
O)
o-:s
(J)
RS
0----1\11,..,.---....1
INPUT 0----1\11,..,.-------'
DIFFERENTIAL
INSTRUMENT
RS - scaling resistors
Differential Analog Switch
ranges (-25°C to +125°C), this makes it an unusual but
ideal ,choice for an accurate multiplexer. This close
tracking greatly reduces errors due to common-mode
,signals.
The NP05566 monolithic dual is used in a differential
multiplexer application where ROS(ON) should be
closely matched. Since ROS(ON) for the monolithic
dual tracks at better than ±1% over wide temperature
lk
.----,\M,.....-Q15V
10k
0,01/.1F
aDk
~OUTPUT
.O.01pF
'4k
INPUTlOr--....-....,~.,
D.004/JF
':'
B'Ok
lk
+
470
33Dk
Ik
t - - - - - - - - - 4.....ty\I\r-o-15V
i+
'..L"
50IJF
Magnetic Pickup Phono Preamplifier
This preamplifier provides proper loading to a reluctance
phono cartridge. It provides approximately 35 dB of
gain at 1 kl:iz (2.2 mV input for 100 mV output), it
features S + N/N ratio of better than -70 dB (referenced
to 10 mV input at 1 kHz) and has a dynamic range of
84 dB (referenced to 1 kHz). The feedback provides for
RIAA equalization.
6-29
tn
c
.2
....co
(.)
5V
H2
HI
-.-c.c.
Y,N 0--'1,.,..,---+---1
OUTPUT
80 dB @ 100 MHz
Insertion loss ~ 6 dB
-IOV
High Frequency Switch
The 2N4391 provides a low ON resistance of 30n and a
high OFF impedance «0.2 pF) when OFF. With proper
layout and an "ideal" switch, the performance stated
above can be readily achieved.
6-30
'TI
m
.....
o
RI
n
c
::.
10k
10=
VIN
R1
VIN
10="'"i'i1
vVIN~OV
VIN >OV.
Precision Current Sink
Precision CUrrent Source
The 2N5457 and PN2222 bipolar serve as voltage
isolation devices between the output and the current
sensing resistor, R1. The LM 101 provides a large amount
of loop gain to assure that the circuit acts as a current
source. For small values of current «1 mAl, the
PN2222 and 10k resistor may be eliminated with the
output appearing at !he source of the 2N5457.
The 2N5457 JFET and PN2222 bipolar have inherently
high output impedance. Using Rl as a current sensing
resistor to provide feedback to the LM 101 op amp
provides a large amount of loop gain for negative feedback to enhance the true current sink nature of this
circuit. For small current values, the 10k resistor and
PN2222 may be eliminated if the source of the JFET
is connected to R 1.
OUTPUTo-....-----~p_----_;
v·
INPut
3DV
FROM
r l ) + - - - - -......r.!:"'-r~~VIDEO
r1 r-'5VISAMPLE)
-J L.J -15V (HOLD)
DETECTOR
*Polycarbonate dielectric capacitor
JFET-Bipolar Cascade Circuit
Low Drift Sample and Hold
The JFETs, 01 and 02, provide complete buffering to
Cl, the sample and hold capacitor. During sample, 01
is turned ON and provides a path, rds(ON), for charging
Cl. During hold, 01 is turned OFF, thus leaving 01
ID(OFF) «100 pAl and 02 IGSS «100 pAl as the
only discharge paths. 02 serves a buffering function so
feedback to the LM101 and output current are supplied
from its source.
The JFET-bipolar cascode circuit will provide full video
output for the CRT cathode drive. Gain is about 90.
The cascode configuration eliminates Miller capacitance
problems with the 2N4091 JFET, thus allowing direct
drive from the video detector. An m derived filter using
stray capacitance and a variable inductor prevents
4.5 MHz sound frequency from being amplified by the
video amplifier.
6-31
en
c
0
~
ca
2.2'"
-
.~
0.
0.
...., rW
-
15V ON
-15V OFF
111914
C>----.--l~--__,
«
.:::J-
1N914
~
0
Ijj
OUTPUT
u..
JFET Sample and Hold Circuit
Peak output yoltage
V p '" V z +.1V
Wien Bridge Sine Wave Oscillator
2N5457, thus varying its channel resistance and, hence,
loop gain.
The major problem in producing a low distortion,
constant amplitude sine wave is getting the amplifier
loop gain just right. By using the 2N5457 JF ET as a
voltage variable resistor in the amplifier feedback loop,
this can be easily achieved. The LM103 zener diode
provides the voltage reference for the peak sine wave
ampl itude; th is is rectified and fed to the gate 9f the
The logic voltage is applied simultaneously to the sample
and hold JFETs. By matching input impedance and feedback resistance and capacitance, errors due to rds(ON)
of the JFETs is minimized.
r----1""""-oy.
100
1k
Vour
....---4~-oVOUT
-=
High Impedance Low Capacitance Wideband Buffer
vOUT'"
R2
AI
vlN
High Impedance Low Capacitanca Amplifier
This compound series·feedback circuit provides high
input impedance and stable, wide·band gain for general
purpose video amplifier ·applications.
The 2N5485 features low input capacitance which
makes this compound series·feedback buffer a wide·band
unity gain amplifier.
6·32
'T1
. . - - _. . ._ _ _ _ _ _. . ._ _ _ _ _ _. . .-<>12V
IBV
2.2k
4.1k
~
Q
n
Uk
6.8M
c_.
...---...- -.....- -...._<> OUTPUT
V1No--t-~,...,
l>
'C
'C
2N5484
1M
1M
1M
.4.1k
4.7k
o to 360
Stable Low Frequency Crystal Oscillator
0
Phase Shifter
Each stage provides QO to 1800 phase shift. By ganging
the 2 stages, 00 to 3600 phase shift is achieved. The J202
JFETs are ideal since they do not load the phase shift
networks.
This Colpitts-Crystal oscillator is ideal for low frequency
crystal oscillator circuits. Excellent stability is assured
because the 2N5484 JFET circuit loading does not vary
with temperature.
ANALOG
INPUT
1
VOUT
,
10k
',ANALOG
I INPUT
,
I
OTL
ITL
,
INPUT
CONTROL
,
,
I
2N4860
IN914
10k
L _________ ...J
DS7800
VOLTAGE
TRANSLATOR
ADDITIONAL STAGES
IF REQUIRED
OTL-TTL Controlled Buffered Analog Switch
This analog switch uses the 2N4860 JFET for its 25n
rON and low leakage. The LM102 serves as a voltage
buffer. This ~ircuit can be adapted to a dual trace oscil-
loscope chopper. The 057800 monolithic IC provides
adequate switch drive controlled by OTLiTTL logic
levels.
20 MHz oscillator values
Cl '" 700 pF
C2 = 75 pF
VOO= 16V
Ll = 1.31'H
L2 = lOT 3/8" dia 3/4" long
10= 1 rnA
20 MHz oscillator performance
Low distortion 20 MHz osc
2nd harmonic - 60 dB
3rd harmonic> -70 dB
47pF
Low Distortion Oscillator
The 2N5485 JF ET is capable of oscillating in a circuit
where harmonic distortion is very low. The JFET
local oscillator is excellent when a low harmonic content
. is required for a good mixer circuit.
6-33
_.
g
O·
::::J
en
U)
c
o
:;:::;
CO
.~
0.
0.
-
T--::I1""-19 J OUTPUT
ON
10
OFF -20
:tr--
1N914
FROM OS7800
100pF
High Toggle Rate High Frequency Analog SwitCh
This
drive
OFF
ideal
commutator circuit provides low impedance gate
to the PN4091 analog switch for both ON and.
drive conditions. This circuit also approaches the
gate drive conditions for high frequency signal
6·34
handling by providing a low AC impedance for OFF
drive and high AC impedance for ON drive to the
PN4091.
\
."
m
-I
...n_
2N4091 JFETS
n.
,..--....- O I •• UT 1
1M
,-------,
c
I
;:::;:
l>
INPUT2
01L
TTL
INPUTS
"C
"C
1M
Cr
Q)
L _____ -.-I1
....
o-.
INPUTJ
DS7BOD
VOLTAGE TRANSLATOR
1M
,------,
I
1
::::J
en
I
I
01L
TTL
INPUTS
hNPUT4
I
I
I
1M
I
I
L _____ ...JI
OUTPUT
057800
VOLTAGE TRANSLATOR
4-Channel Commutator
This 4-channel commutator uses the 2N4091 to achieve
low channel ON resistance «30n) and low OFF current
leakage. The DS7800 voltage translator is a monolithic,
device which provides from 10V to -20V gate drive to
the JFETs while at the same time providing DTL/TTL
logic compatability.
RS
DIFFERE~J~n~ o-...".R"'./Iv-....- - - - - - - - - - ,
PN4392
>--~OVOUT
r
"SCALING"
RESISTORS
DIFFERENTIAL
j
1k
R2
INPUT
PN4J92
HI
-ISV
~
ADDITIONAL
CHANNELS
FROM OS7800
.
,,-10V
VOL lAGE TRANSLATOR ~
L- -20V
Wide Band Differential Multiplexer
This design allows high frequency signal handling and
high toggle rates simultaneously. Toggle rates up to
1 MHz and MHz signals are possible with this circuit.
6·35
In
c
.,
.2
1a
0.1
POSITIVE
1%
INPUT o-_~JVVIt_p--o() TO LOAD
VOLTAGE
.~
Q.
c.
ne Control Circuit
0.05% with an SIN ratio of over 85 d8. The tone controls allow 18 dB of cut and boost; the amplifier has a
lV output for 100 mV input at maximum level.
This preamp and tone control uses the JFET to its
best advantage; as a low noise high input impedance
device. All device parameters" are non-critical. yet the
circuit achieves harmonic distortion levels of less than
6·36
National Semiconductor
John Maxwell
February 1977
A Novel FET Micropower
Voltage Regulator
l>
Z
o
<
-
CD
."
Many systems require a stable voltage supply to maintain
constant performance. When these systems are battery·
operated, a regulator is needed to stabilize the system
voltage as the battery decays with time. Unfortunately,
IC voltage regulators require several milliamps of
quiescent current, making them impractical for micro·
power applications. Zener diodes may also be impractical
because of short term peak current requirements of the
system. This could require additional buffering or high
standby currents, but both increase the battery drain.
An inexpensive micropower voltage regulator is needed
to fill the gap between IC regulators (high quiescent
current) and zener diodes (high standby current).
The emitter-base breakdown voltage of 03 is used as
a reference (-7.2V) in conjunction with 02 to form a
shunt regulator. The shunt current drives a current
mirror, 04-05, which creates the gate drive voltage of
the pass FET: The value of the shunt current is determined by R3 and the VGS of the pass FET (lR3 '"
ISHUNT). High load currents will reduce the shunt
current because the FET VGS is lower. Temperature
stability is achieved by cancelling the drift of 02 and
03's VBE (--2 mVfC/trimsistor) with the BVEB
drift of 03 (- 3 mV tC) resulting in a negative drift at
the base of 02, and the output, of 1 mV tC.
Selection of the FET requires some care. Ideally, the
FET lOSS needs to be greater than the load current at
all temperatures (loss has a temperature coefficient of
--0.7%tC) and the breakdown voltage should be
greater than the maximum input voltage. Practically,
the FET lOSS needs to be much larger than the maxi·
mum load current. Linear operation requires the FET's
drain to gate voltage (VOG) to be greater than the
pinchotf voltage Vp. By operating the F ET at currents
much less than lOSS, the gate to source voltage (VGS)
will be close to Vp (VGS = Vp (1-(l0/10SS)'/2))
allowing small drain to source voltages (VOS). For
linear operation:
Instead of the tranditional bipolar approach, the
regulator shown in Figure 1 uses a JFET as the series
pass element. This offers several advantages: first, no
pre-regulation is needed for the pass element as with an
NPN because the drive comes from the regulated-output.
Next, the gate·source is isolated from the line via the
drain, thus offering excellent line regulation. This is not
the case with PNP pass. elements, where the emitter is
the input. Finally, and possibly the most important
feature for micropower regulators" is FETs require no
current drive.
'
VIN
IVOGI> IVpl
VOG = VOS - VGS
It should be noted that N FET's can be paralleled for
higher load current requirements without matching the
devices.
Rl
2.2M
Actual performance of the regulator is quite good. With
a 10V typical output, the line regulation is within
±0.05% for a range of VIN-VOUT of 0.3V to 10V.
The load regulation is 0.2% with a load range of 10 J.lA
to 10 mA (Zo'" IOn) and the temperature stability is
-O.Ol%tC (-1 mVtC). The output voltage can be
easily trimmed by adding a pot at the Rl R202BASE
junction to eliminate BVEB variations or to make the
output adjustable over a limited range. Also, the temperature stability can be improved by replacing 03 with an
8.2V zener diode, because its temperature drift (- 4 mV 1
°C) would nearly match the combined VBE drift of
02 and 04. The regulator is good enough to be used as
a reference in low accuracy (6-7-bit) or limited temp·
erature range applications if current drain is important.
R2
10M
VOUT
I
I
I
106
I
I
IL ____________
.
J
Output Voltage
R1
R1
VOUT= VeE (2+ R2)+ eVEB (1 + R2)
REFERENCES
Drift
1·. "Voltage Regulator Handbook", National Semiconductor Corporation, May 1975.
aVOUT = aVeE
aT
aT
Quiescent Current
(2+~) + aevEB
R2
~
aT
(1 + ~ )
R2
4 p.A
FIGURE 1. Micropower Regulator
2. "Zener Oiode Handbook", Motorola, Inc., May 1967.
. 3. Williams, P., "O.C. Voltage-Reference Circuits with
Minimum Input-Output Oifferentials", Proc. IEEE
pp. 1280-1281, Oecember, 1969.
6-37
!:!I
3:
cr
a
"C
o
~...
o<
Sf
co
CD
::D
CD
co
c
iii'
S'
...
0.1
g
'2
c
1=
IL = 10llA
0
I;
..:
..
G)
~
o
a.
e
.~
:E
~
W
LL
Ci)
:;:
'"c
'"to
..:
-0.1
!:i -0.2
c'
>
I-
~, ':"0.3
f
I
1/
I-
=
c
V
0.1
10
-
2:
c
1=
0
10
VIN = 10.BV
TA = 25° TO 85°e
g
0
..:
:;:
'"c
-10
i'
1L =10mA
.,-0.1
to
oS
....
c
I-
-20
-10
"'t....
'"
..:
3'
oS
-0.2
-20
...= -0.3
-30
>
I-
VO(TYP) = 10. IV
VIN(TYP) = 10.BV
TA = 25°C
-30
I-
=
c
-40
-0.4
-0.4
-40
0.01
10
0.1
0.1
INPUT·OUTPUT DIFFERENTIAL
VOLTAGE (VIN-Vour)
It - LOAD CURRENT (mA)
FIGURE 2. Line 'Regulation vs Input·Output Differential
FIGURE 3. Load Regulation
>
o
z
«
20
0.2
~
g
I'
2:
C
~
:;:
~ -0.2
w
to
~
o
" "~
.
-0.4
,
o
r'lmyc
-20
~lo.'mA
-40
>
~
I-
=
:=
=
o
-0.6
IL =10mA
~
-O.B
3'
oS
-60
-80
25
45
65
85
,TEMPERATURE (OC)
FIGURE 4. Temperature Stability
6·38
10
A Linear Multiple Gain
Controlled Amplifier
»
_.
National Semiconductor
Application Note 129
Jim Sherwin
August 1975
r-
s::
c
;::;
_.
-
"C
INTRODUCTION
( I)
A linear control function over three decades of gain can
be achieved with a FET in the feedback path of a noninverting amplifier. Besides the ultimate simplicity of the
circuit, multiple tracking gain control circuits can be
constructed with dual op amps and monolithic dual
FET's or, quad op amps and mO!1olithic quad FET's.
Such circuits could even be integrated with ion-implanted
FET's on single or mUltiple monolithic op amp chips.
The gain control range may 'be designed for less than 2 to
1 or higher than 1000: 1, but input voltage levels are
limited by acceptable levels of distortion. Bandwidth is
dependent on maximum gain and unity gain bandwidth
of the op amp used. The gain co.ntrol circuit is especially
suitable for volume expansion applications.
GAIN CONTROL WITH FETS
The FET has long been· used as a voltage controlled
resistor (VCR), often as the shunt arm in the series-shunt
attenuator of Figure 1. Advantages of the FET as a VC'R
are that:
1. The control signal is al most perfectly isolated from
the controlled signal path, and
Examination of the FET drain characteristics in Figure 2
will reveal the essential non·linearity of rd at high
signal levels, especially as VGS approaches V p. This nonlinear region must be avoided in order to achieve
tolerable distortion levels. One obvious way is to limit
Vos to small values when rd is high as suggested by
Figures 2c and 2d, another is to utilize FET's with high
Vp as suggested by reference to Figures 2b and 2d
C)
OJ
::l
oo
::l
~
The reciprocal relationship of rd and VGS is an
advantage, as it is precisely that which allows the linear
control of gain in the circuit to be described. The avail. ability of matched monolithic dual FET's such as the
NSC 2N3958 (watch out for the matched pairs as their
resistance match close to Vp may not be as good as that
of the monolithic versions) make available low cost duals
with very closely matched resistance characteristics over
the full control range. There are even some monolithic
quads available (such as the AM9709 series). The final
problem of the produ'ction range of Vp can be much
improved with ion-implant diffusion techniques whereby
lot variation in Vp may be held to within a few tenths
of one volt.
The gain control circuit is that of an ordinary noninverting op amp with feedback. The uSUiil circuit is
modified in Figure 3a to include a FET as controlled
resistor. The gain function is normal except that rd
replaces R2 in the usual form.
2. The resistance can be made to vary over an almost
infinite max/min ratio.
Rl
Av = 1 +-rd
(1)
,Now rd can be equated to a ~ontrol voltage Vc as follows:
FIGURE 1. Voltage Controlled FET Attenuator
(2)
Disadvantages are that:
1. The FET behaves as a linear resistance only for small
values of source-drain voltage Vos,
Where:
2. ,Non-linearity (of resistance) increases as the control
voltage VGS approaches cut-off voltage Vp when
the resistance is maximum,
(3)
3. The relationship of resistance rd to VGS is reciprocal rather than direct linear,
Where:
4. VCR multiples with matched resistance characteristics
over their full control range have been extremely
difficult to obtain at any kind of reasonable price, and
The gain function is thus seen to be linear with Vc.
Rl Vc
Av=l+- ro Vp
5. Production spread in Vp requires separate bias set and
gain set on each circuit.
6-39
(4)
o
(D
Q.
»
3
-_.
"C
::!:
(I)
~
...
CI)
!E
Q.
E
l
FIGURE 3. FET/Op Amp Gain Control Circuit
1200
1000
Rl'300k
Vp =3.7V
Vp ''''2.6V
1000
2N4869
800
2N3958
800
~H2'3kt/
.: &00
30k
400
I~
1/
600
V
>
V
100~.
100
10
C
=
Emil
CD
...
Q)
3:
c
10
10
~.D
100
~
MONOLITHIC QUAD P·CHANNEL
0.1
1.0
vo· IV, - Ves] (V)
2.5
2.D
1.5
1.0
"C
CD
0.5
VGs(V)
FIGURE 6. Control·Gain
Match For Dual FET
~
FIGURE 7. Monolithic Quad
Q)
Gain Control Tracking
=
o
.=
..
o
n
'.
'.
-CD
Q.
>
3
~
(bJ fAST CONTROL MODIFICATION
FIGURE 8. Circuit to Reduce Distortion
Several variable-gain circuits can be made to track when
monolithic multiple FEr's are used as the control
elements with matched feedback resistors. A monolithic
.FET dual (NSC 2N3958) used in two identical control
circuits shows remarkable tracking over the entire control
range, even when VGS is near Vp where variations would
be expected to be most apparel1t. The plots appear in
Figure 6, Similar performance for a quad gain control
using a monolithic P-channel quad FET (AM97C09 or
AM9709) is shown in Figure 7.
At Vc = 0, the gain reduces to unity; and at Vc = Vp,
the gain increases to 1 + R1fr0 which may be as high as
1000 or so. If it is desired to limit the minimum gain to
some value greater than unity, another resistor R2 may
be added as in Figure3b. Then the gain equation becomes:
Rl
Av = 1 + - - - - , - - - R2 ro (VpIVd
R2+ro (VpIVd
Rl [R2+r o (VplVdl
=1+--------R2 ro(VplVd
Av =
Rl
Rl Vc
R2
ro Vp
1+--+--
...(1)'
"C
la' ~ FEEDBACK TO GATE
DISTORTION
Reference to Figure 2 will show that the FET acts as a
linear resistance only for relatively.small values of drainsource voltage, in either polarity. This is particularly
apparent for positive VDS (for N-channel FET) and VGS
approaching Vp. The difference between Figures 2c and
2d indicates that the maximum allowed applied signal
will be greater for high Vp as compared with low Vp.
(5)
In either case, the gain function is linear with Vc.
The circuits of Figure 3 do indeed show a linear gain
versus control voltage as plotted in Figure 4 for several
values of minimum gain. There is some non-linearity
near minimum gain which appears in all curves. This is
certainly' due to a non-ideal characteristic of the FET
caused by finite contact and bulk resistance at source
and drain. Figure 5 shows a similar control curve for a
FET with longer channel in which the controlled channel
resistance'is a greater part of the total resistance than
that of the short channel device of Figure 4. For those
applications requiring a more precisely linear control of
gain, the long channel devices will be preferable.
It is possible to improve the linearity characteristics
somewhat by applying a part of the Vos in series with
the control voltage applied as VGS. The. circuit to
accomplish this is that shown in Figure 8. It happens that
about half of Vos applied to the gate provides the
greatest improvement for small signals. The addition of
two resistors and one capacitor as in Figure 8a is all that
is required. The capacitor simply blocks the control
voltage from the FET drain and the op amp input.
Figure 8b shows the a~dition' of an emitter follower to
6·41
...
G)
!E
Q.
E
prevent abrupt changes in Vc from coupling to the op
amp. Figure 9 shows' the improved linearity of the drain
characteristics as compared to Figure 2. The improvement
is also seen in the distortion versus input signal plots of
Figures 10:"'13. Note particularly that the distortion at
any value of Vc is primarily a function of input signal
(which equals the feedback signal applied to the FET
drain at the inverting input). Some modification is made
to this direct relationship if an R2 is shunted across the
FET as in Figure 3b. Measured distortion at low signal
level is the result of noise rather than of signal distortion.
Maximum gain is limited to about 100 in these plots so
as to avoid the region of lower SIN. The noise is that of
the op amp input stage and the signal source resistance
plus the contribution of the FET which is essentially
the thermal noise of rd'
is quite low except as limited by maximum output
voltage~ Note that the maximum ein is restricted by output saturation. The LM318 is used in the example only
to achieve wideband response at maximum gain. The
amplifier input voltage must be restricted to about
8 mVrms at maximum gain when the SIN will be about
60 dB over a 10 kHz bandwidth.
e,'$;8~:V
RMS
---1~
o-....
1-- r ;r-~""'-15V
.-L O•01
BANDWIDTH AND CONTROL TIME CONSTANT
1M.
T.M
f l~ r
To this short list might be added a number o~ others,
including applications in noise reduction and quad sound
techniques.
The gain'controlled amplifier of Figure 14 has a gain
range of 1-1000, a maximum output level of 8.5 Vrms,
and a bandwidth of better than 20 kHz at maximum
gain. The FET used has high Vp for maximum freedom
from distortion. Figures 15 and 16 show the gain
function and constant distortion contour lines. Note
that the gain control curve is non-linear near unity gain
because the PN4091 is a short channel FET. Distortion
Noise considerations could be important in this method
of gain control, as the signal is amplified rather than
attenuated. To realize the function of a 40 dB variable
attenuator, it is necessary to install a fixed attenuator at
the amplifier input and perhaps also at the output. This
will reduce the minimum signal level to millivolts, thus a
low noise amplifier is de~irable. The LM381 dual lownoise ac coupled amplifier could be used in a 40 dB
1. Remote or multichannel gain control
2. Volume expansion
·3. Volume compression/limiting
1000
BOO
600
400
200
r-r-,-,.-,.--,--r--r-'T"'T""
1000
-t =IB.ZJ-t--t-t-+-+-+~7I
J
100
V
;;
I
0.1%
oS
AZ = 300 /.
!
I
y/
I/A-
FEEDBACK ~
Av -1-1000
vp 'H.ZV.
PN4091
~
PN40191 I
10
~
fA
D.06%TH~~
3k
I I I
1
-10 -9 -B -7 -6 -5 -4 -3 -Z -1
-9 -B -1 -6 -5 -4-3 -2 -1
0
Vo. (V)
VGs.{V)
FIGURE 15. Gain For Circuit
of Figure 14 .
FIGURE 16. Distortion For
Circuit of Figura 14
6-43
-
'C
CD
G)
D)
---...
o
·2kforgain"'-IDO
··LMJOIA fnr gam = 1-100
A more practical circuit might employ a gain range of
1-100. Then the amplifier c~uld be a LM301A and
still achieve a 10 kHz bandpass at maximum gain. The
input signal could, accordingly, be increased to 80 mVrms
for a SIN of 80 dB. This performance can be extended
to dual and quad control circuits with tracking gain
functions, but watch the bandwidth as required at maximum gain. Any of the several dual op amps could be
used with the 2N3958 (monolithic dual from NSC), or
the LM324 quad op amp can be used in limited gain
times bandwidth applications with a quad monolithic
FET. Figure 17 shows all details of an ac coupled tracking
quad gain 'control with 40 dB range. Gain varies over
1-100 range, bandwidth is' 10 kHz minimum, SIN
is better than 70 dB with 4.3 Vrms maximum output. Figure 7 shows the gain curve and matching
characteristics.
Three obvious applications present themselves; they are:
D)
o
PN4391
FIGURE 14. Amplifier With Gain Range = 1-1000
APPLICATIONS
CD
...
::l
20k"
'-4-
The circuit bandwidth is the closed loop bandwidth of
the op amp used at the (instantaneous) set gain. The gain
control time constant is that of the input circuit to the
FET (dependent on the value of R in Figure 8) limited'
by the slew rate of the 9P amp. The FET itself reacts
practically instantly, producing a step change in feedback
ratio. Control time constant is thus a few microseconds
at most.
c:::l
0
::l
o
CD
0-
J>
3
-Si
'C
...
CD
...
r-"7,OY---'
I
I
CI)
!E
-Co
"S;tVRMS~
A'
R4
E
«
R2
AI
"C
-...
.S!
-
.".
0-:1
0
AI
C
0
(.)
C
.CO
.".
~
CJ
AI
CI)
Q.
E
::l
:E
A'
A.
.".
o-j
...CO
R2
AI
.".
CI)
c
:J
CI
«
r
I
R"IM
AI "ZUII
RZ-5k
R3-24011
R4-,Uk
R5=IOk
Cl =D.OIJlF
CZ"'J/.F
I
L_~'~_.J
A.
GAIN CONTROL
q.
C2
..Ok
+zov
FIGURE 11. Quad Gain Control
BeaUT
',,",,
'.
.".
"Drl/2lM34I
FIGURE 18. Volume Expander/Compressor Block Diagram
FIGURE 19. Full Wave Linear Precision Peak Detector
6·44
audio attenuator to realize SIN about 100 dB or in a
60 dB attenuato,r to realize 80 d8 SIN. Improvements
in SIN can be made by reducing system bandwidth in
fixed or low frequency operation. Minimum noise is also
achieved by using the minimum practical amplifier
source resistance. Values as low as 1 kn are advantageous.
halt cycle (full-wave detector). Tile detector should,
therefore, be a full·wave precision linear peak detector
with low internal impedance; the requirements can be
met with the circuit of Figure 19.
The expander circuit shown in Figure 20 will perform as
desired. The gain control function is plotted in Figure 21;
distortion is below 0.1% at all levels. Resistors R3 and
R4 are added in order to modify the linear control curve
to the desired log curve. Note that the input signal is
attenuated prior to amplification in order to reduce
distortion and maintain an overall gain of approximately
o dB at midrange of expansion. The noise with the
LM124 over a 20 kHz bandwidth is, of course, a function
of signal; but the maximum signal to noise ratio is 80 dB.
. The circuit could be adapted to stereo or quad sound
as in Figures 22-23. Questions for individual design
concern the method of control. Whether to expand all
channels together, and whether to derive the control
signals individually from each channel, a summation
from 2 to 4 channels, or from a single channel (assuming
that high level from any channel indicates high levels
from all channels). Note that the FET is biased OFF
(minimum gain) for low signals, and increasing signals
progressively bias the FET ON (maximum gain).
The effect of temperature will be to change the gain
according to the temperature sensitivity of the FET.
This effect can be reduced by using a silicon resistor for
the feedback resistor, R1. If the FET were to be
integrated onto the op amp chip, an attempt should be
made to include R1 on the chip as well.
The application to a volume expander circuit is of
interest as the control is linear, the required control
range is only about 1:4, and the input signal "is small
for the low gain condition when distortion would other·
wise be most apparent. The elements of a volume
expander are indicated in Figure 18. The gain controlled
amplifier need only exhibit a 12 dB "variation in gain,
being lowest for small signals. The slope of gain versus
control should be linear, more specificallY the slope
of (log) gain in dB versus (log) signal in dB should
be linear. A practical range is 12 dB gain change over a
30 dB input signal range. The peak detector should be
linear down to very small signals, exhibit a fast attack or
charge time of a millisecond or less, a discharge time
constant of about 2 seconds, and operate on the first
The volume compression circuit is a logical mate to the
expander. The only difference would be that the FET is
initially biased ON ·(maximum gain) for low signals, and
•zov
'.
1O'
1M
1M
.10Y
1M
1M
, -tl0V
......._ _ _ _ _ _ _ _...._+< ;VSETT0I10V-Vp)
FIGURE 20. Volume Expander Circuit
6·45
s:
c
_.
;:;:
"C
CD
C)
Q)
:::l
n
o
-.-..
:::l
o
(1)
Q.
l>
3
-:::;:
iii'
...
"C
...
!E
-'
,c.
Q)
....
E
.;~~:~ 0-.--------+1
CO
c
m
RS
20
Va = -VIN RF [GI 20 + G2 2-1 + 133 2-2 + G4 2-3 + 1/16 (G5 20 ; G6 2- 1 + G7 2-2 + G8 2-3 )J
R
(1/10 for BCD)
FIGURE 3. 8·Bit Multiplying DIA Using Cascaded 4·Bit Sections
Practical Iimitations in using monolithic current mode
analog switches need ·consideration. Resistor values and
tolerance impacted by switch resistance is minimized by
increasing resistor values without regard, but limits
bandwidth and creates leakage errors at elevated temper·
atures. Using resistors that are too small, increase switch
resistance errors. Current saturation (increased switch
resistance) occurs when the switch current approaches
the FET saturation current, IDSS. High cl!rrents also
Binary weighting requires a 1/16 current split for the
second switch quad while ·BCD weighting requires a
1/10 split.
There are 2 basic switch configurations available that
are optimized for a variety of logic drives: TTL or CMOS
Multiple independent switches (4 by SPST) and a 4·
channel multiplex version with a series compensation
FET.
6-48
~
:::J
...I»
cause IG(ON), current lost through the gate, as the
diode and FET source to gate diode become forward
biased. An input resistor value of 10k limits the switch
current to less than 2 mA minimizing both leakage and
switch resistance problems. For example, the gain
accuracy at unity gain using the compensation FET is
less than 0.05% with R = R F = 10k.
The current shunt resistor used in cascading switches
should be kept small to. minimize the voltage drop,
keeping the FET drains near ground. Values of RS
should be less than lOOn (20 typ).
This works out to be ±0.2% for the B-bit binary unit.
Errors in the feedback resistor directly affect the output
of the converter. The most significant resistor, R,
contributes 1/2 full-scale, reducing its error contribution
by a factor of 2. The same is true for the rest of the
resistors with contributions of .1/4, l/B, etc. Using a
resistor tolerance of 0.1% for the feedback resistor,
0.2% for the 2 most significant resistors (R, 2R), 0.5%
. for the 3rd and 1% for the 4th and 5th switches allows
5% resistors to be used in the 6th, 7th and Bth switch
positions.
'<
........
tD
n
o
C)
I»
5'
"tJ
a
Ul
Resistor tolerance will be determined by converter
resolution, i.e., the number if bits (N). For example,
an B·bit· binary D/A converter will have 2N_l or 255
steps (99 for BCD) or different gains. The resolution or
smallest step is (least significant bit) 1/2 N of the full·
scale value (0.0039). Typical accuracy specifications
for D/A converters are stated as 1 LSB or ±1/2 LSB.
Using the above information, 4-bit or· more binary/BCD
gain programmable amplifiers can be built with large
signal handling capability, few parts and easily adjustable
gain or attenuation. Figure 3 shows a practical B-bit
binary/BCD GPA with gains of 0.996 (binary) with
R F = 5k and 0~99 (BCD) with RF = Bk. For other gains,
only the feedback resistor need be changed.
Q;
3
3
CD
c.
»
3
"2~
2
CD'
22
% error = [ Ef2 + (ER)2 + (E2R)2 + - - - + (€nR)2]112
2i1
Cil
(2)
or
[ 2 (0.2)2
(0.2) 2
( 5 )
% error = (0.1) +
+
+ - - - + 256
2
4
2]1/2 =
Ef = tolerance of feedback resistor
€R = tolerance of most significant resistor
En R = tolerance of Nth resistor
6-49
~0.1 9B%
National'Semicondl\ctor
John Maxwell
February 1977
FET Curve Tracer
Junction field·effect transistors (JFETs), unlike ):Jipolar
transistors, do not easily lena themselves to analytic
solutions of bias networks. By their very nature, JFETs
are voltage controlled devices. Gate to source voltage
(control voltage VGS) variations' of several volts can
exist within a given part type at the same operating
conditions, causing the problem. Multiple suppliers and
inadequate or non·existent data sheet curves compound
the problem further; requiring 'data from the suppliers
or the use of a curve tracer.
fO
J
I
/
./
o
-2.5
-2
V
-1.5'
-1
-0.5
VGS (V)
A simple curve tracer, used with any oscilloscope, can be
built using a quad op amp and a handful of parts. The
circuit displays drain current versus' gate voltage for both
P and N·channel JFETs at a constant drain voltage.
FIGURE 1. Typical N·Channel FET Transfer Curve
The circuit consists of an op amp current to voltage·
(IN) amplifier with a positive or negative gate sweep
f.
t rnA/V
200
5mA/V
f5V
10k
10
VERTICAL
HORIZONTAL
O.5V/ms
10'
O.lpF
A1-A4 01-02 02*
03*
1SDk
f5V
fk
,
~fO
499
't.fO
f5V
-15V
150
*1W NPN, PNP
-15V
FIGURE 2. FET Curve Tracer
6·50
LM324
1N914
92PU01
92PU51
."
voltage. The IN amplifier uses 1/4 of the quad op amp
and 3 switch able feedback resistors for drain current
scaling: lk for 1 mAN, 200n for 5 mAN and 100n
for 10 mAN. An NPN-PNP emitter-follower buffer is
used with the IN amplifier to handle high FET curr~nts
(to 100 mAIo A unity gain inverting amplifier is used
for proper drain current polarity.
horizontal input is used for the gate voltage. The horizontal sweep can be used if no horizontal input is
available where a sweep rate of 0.5 ms/cm corresponds
to 0.5V /ms, allowing the curve tracer to be used with
any oscilloscope.
'r-----O' RESET
~
()
..,c::
<
CD
..,-I
The gate sweep generator consists of 2 parts, a linear
ramp generator with a reset and a window comparator.
The ramp generator is an op amp with a capacitor in
its feedback loop. The sweep rate is set by a constant
current supplied to the capacitor through a resistor tied
to either the plus or minus voltage supply.
Q)
0.1 j.lF
n
CD
..,
150k
±1~~o-,"",M~"""
vo
:l:1V/ms
The positive (P-channel) ramp mode uses the positive
reference on the plus input of the comparator with the
ramp connected to the minus input. The comparator
output stays high (15V) pinching the FET OFF until the
input exceeds the reference (10V). At that point, the
output snaps to the negative supply, turning the FET
switch ON, discharging the capacitor. The reference
voltage at the plus input is set near ground using the
51 k input resistor, 02 and 68k feedback resistor when
the comparator output is in the low state. When the
capacitor is discharged, the comparator resets, restarting
the ramp.
FIGURE 3. Linear Ramp Generator
20 , - - - - - - , , - - - - - - ,
~
>
10
A negative sweep is more difficult to generate using the
same comparator. The reference (-10V) is on the
minus input with the ramp connected to the plus input.
As with the positive sweep, the comparator output is
high until the negative sweep exceeds the reference.
The difference is that the reference cannot be set to
ground for the reset sweep but to a negative voltage
such that when the ramp is at OV the comparator resets.
The function of Q2.is to short R1, changing the reference voltage from -10V to -6V.
I---~-:;.r-----:.!
10
20
TIME 1m,}
FIGURE 4. Positive SWeep,
In both cases, the sweep time is 10 ms. The resistor
attenuator on the FET gate terminal divides the voltage
in half, yielding a sweep rate of 0.5V /ms with a maximum gate voltage of ±5V. This should be adequate for
m,?st F ETs used as amplifiers but if additional gate
voltage is required, the attenuator can be switched out.
~
-10
>
The circuit is limited to displaying only the FET transfer
characteristic 10 vs VGS, but this is the curve most
needed by designers. It gives insight into parameter
variations of bias circuits and it can be used to observe
temperature effects on the FET. The' oscilloscope
vertical input is used for the drain current and the
-20 ' - - - - - - ' - - - - - ' - - '
10
20
o
TIME 1m,}
FIGURE 5. Negative SWeep
6-51
J!l
.8
JFET Glossary of Symbols
E
~
(J)
'0
DC PARAMETERS
BVoGO(V)
or.BVGOO
Drain-Gate Breakdown Voltage with Source OpenCircuited
The breakdown voltage of the drain-gate junction,
measured at a specified current with the source
open-circuited.
BVSGO(V)
or BVGSO
Source-Gate Breakdown
Open-Circuited
Voltage
with
Drain
The breakdown voltage of the source-gate junction,
measured at a specified current, with the drain
open-circuited.
BVGSS (V)
or BV, Y(BR)GSS
Voltage with Drain-
Source-Gate Breakdown
Source Shorted
The breakdown voltage of the source-gate and
drain-gat' junctions, measured at a specified
current with the drain-source shorted.
lOGO (pA)
or IGOO
Orain-Gate Leakage Current, Source Open-Circuited
The leakage current of the drain·gate junction,
measured at a specified voltage, with the source
.
open·circuited.
10 (pA)
or 10(ON)
10(OFF) (pA)
Drain ON Current
The drain current, measured at a specified drain·
source voltage and gate·source voltage.
Drain Cutoff Current
The drain cutoff current, measured at a specified
drain·source voltage and gate·source voltage.
lOSS (mA)
Drain Saturation Current
IDSS
The drain current, measured at a specified drainsource voltage with the source shorted to the gate
(VGS= 0)
'G(pA)
.or IG(ON)
Gate Leakage Current with Drain Current Flowing
The gate leakage current, measured at a specified
drain current and drain·gate voltage.
IGSS (pA)
Gate-Source Reverse Leakage Current with Drain·
Source Shorted
\
The gate·source reverse leakage current measured
at a specified gate·source voltage.
6·52
~
D
+
~VDS
c..
ISGO (pA)
or IGSO
Source-Gate Reverse Leakage Current with Drain
Open-Circuited
or rds. ROS.
rOS(ON)
VOS(ON) (mV)
C')
0'
en
en
Drain-Source ON Resistance
...
Q)
'<
The drain-source ON resistance, measured at a
specified gate-source voltage and drain current.
o
en
Drain-Source ON Voltage
'<
Vos
The drain-source ON voltage, measure~ at a specified gate-source voltage and drain current.
VGS(V)
orVGS(ON).
VG
!!l
~
~VSG
The leakage current of the source-gate junction,
measured at a specified voltage, with the drain
open-circuited.
ros(·Q)
."
ISGO
'05=
ID
3
C"
o
Operating Gate-Source Voltage
en
The gate-source voltage, measured at a specified
drain current and drain-source voltage.
Vas
VGS
VGS(F) (V)
Forward Gate-Source Voltage
The 'forward gate-source voltage, measured at
specified current.
VGS(OFF) (V)
orVp
Gate-Source Cutoff (Pinch-Off) Voltage
The gate-source cutoff voltage, measured at a
specified drain current and drain-source voltage.
-10
VOS
SMALL SIGNAL PARAMETERS
Ciss (pF)
or Ciss. Cgss
Common-Source Input Capacitance
The common-source input capacitance me9sured
between the gate and source with the drain A-C
shorted to the source at specified drain-source and
gate-source voltages.
Cos s (pF)
or Cos. Cdss
Common-Source' Output Capacitance
The common-source output capacitance, measured
between the drain and source with the source
A-C shorted to the gate at specified drain-source
and gate-source voltages.
6-53
Vos
Crss (pF)
or Crs. Cdg
ens
The common-source reverse transfer capacitance,
measured between the drain and gate at specified
drain-source and gate source voltages.
~
en (nV/v'Hz)
or en. Vn• En
Equivalent Input Noise Voltage
The equivalent input noise voltage per unit bandwidth, measured with the input A-C shorted to
the source at a specified operating condition.
"
T
VOS
~
$.n
S .
./
IW
LL
:!;~.
~) RIl:
'1
.2
..,
Goff
[S
) ,I,Vi:4+
o
CO
UJ
UJ
""""""'RFC
Common-Source Reverse Transfer Capacitance
9fg (mV)
or Vfg
Common- Gate Forward Transconductance
The common-gate forward transconductance with
the output A-C shorted. This is a complex quantity (9fg + ibfg).
9fs (mV)
or 9m. Vfs.
RelVfsl
9iss (/LV)
or Vis
,
m
vGS '"
G
Yf =10
9 vGS
Common-Source Forward Transconductance
The common source forward transconductance
with the output A-C shorted. This is a complex
quantity (9fs + ibfs)'
Yfs= -10
.
vGS
The common-source input conductance with the
output A-C., shorted. This is a complex quantity
(9is + ibis)'
vos=o
VOs=O
W
G
S
IGYis= VGS
goss (/LV)
or Vos
I
.
/
vof'=o
Lffi
o
.
. G S
. /
10
Yos= vos
vos
I
vGs=o
G pg (dB)
Common-Gate Power Gain
The common-gate power gain is the ratio of output power to input power.
Gp = 10 10910
GPS (dB).
Common-Source Power Gain
~
PI'
The common-source power gain is the ratio of output power to input power.
in (pA/y'HZ)
Equivalent Input Nojse Current
The equivalent input noise current measured with
the input open-circuited under specified operating
conditions.
n
G
S .
in
6·54
10
10
Common-Source Output ~onductance
The common source output conductance with the
input A-C.. shorted. This is a complex quantity
(gos + ibos)'
10
I
I
/
'" vGS
Common-Source Input Conductance
/
I
vos
NF (dB)
c:..
"TI
m
Spot Noise Figure
Noise figure = 10 109'10 F were F is noise factor
which is the ratio of the total output noise power
to the output noise power. of the source. Measured
at specified operating conditions and source resistance.
Total Output Noise Power
-4
Source Output Noise Power
C)
F = -::---=-----,,:-:--=---
0'
tJ)
tJ)
Q)
COMMON-SOURCE SWITCHING PARAMETERS
~
In the following, drive circuit conditions and drain
circuit conditions must be specified. The transition
times of the input must be negligible compared to
the measured times.
VOD
c>--wv-...-u vDUT
o
en
'<
!d(ON)
3
o
Turn-On Delay Time
C"
The time interval during turn-on from the point
when the input pulse at ttie gate reaches 10% of its'
full amplitude to the point when the drain pulse
changes from 0 to ,10% of its maximum amplitude.
'ii)
IDION) = VDD-VDSION)
Rise Time
RL
The time interval during turn-on in which the
drain current pulse changes from 10% to 90% of
its maximum amplitude.
!d(OFF)
Turn-Off Delay Time
100
f-:=r:::+~
90 I--
The time interval during turn-off from the point
when the turn-off pulse at the gate changes from
100% to 90% of its full amplitude to the time
when the drain current has changed from 100% to
90% of its maximum amplitude.
\ tf
ID(ON) (II)
Fall Time
The time interval during turn-off in which the
drain current pulse decreases from 90% to 10% of
its maximum amplitude.
DUAL FET PARAMETERS
BVG1 G2 (V)
or BVG1-2
Gate to Gate Breakdown Voltage
The breakdown voltage of the gate to gate junctions, measured at a specified current.
Gl
~
SUB
G2
CMRR (dB)
orCMR
Common-Mode Rejection Ratio
The common-mode rejection ratio is the ratio of
the change in differential gate voltage with a
change in the drain to gate voltage.
CMRR = 20 1091O AVDG
AVos
6-55
U)
'0
.c
E
>en
9151-2 (%)
or 9fs1/91s2
Common-Source Forward Transconductance Ratio
(Match)
,
The transconductance ratio = 9fsl/9fs2 x 100 (%)
measured at,specified drain-gate voltage and drain
current.
~
0
...CO
>-
\
goss 1-2 (/.IV)
or gosl-2
U)
U)
Output conductance match = Igos1-gos21 measured
at specified drain-gate voltage and drain current.
.2
e,:,
~
W
..,LL
Common-Source Output Conductance (Match)
IOSSl-2 (%)
or IOSl-2.
IOSS1/IOSS2
IG1-2(pA)
Drain Saturation Current Ratio (Match)
The drain saturation current ratio = IDSS1/
IDSS2 x 100% measured at specified drain-source
voltages.
Differential Gate Leakage Current
Differential gate leakage current = IIG1-IG21
measured at specified drain-gate voltage and drain
current.
IG1. G2 (pA)
Gate to ,Gate Reverse Leakage Current
The gate to gate reverse leakage measured at a
specified voltage monolithic dual with diode isolation shown.
IG1.G2
G1
SUB
G2
VGS1-2 (mV)
or Q.VGS. Vos.
IVGS1-VGS21
Q.VGS1-2 (/.IvtC)
or Q.\VGS1VGS21/Q.T
Q.Vos/Q.T
Differential Gate-Source Voltage
The differential gate-source voltage. measured at a
specified drain-gate voltage and drain current.
Differential Gate-Source Voltage Drift
The differential gate-source voltage drift is the
change in the differential' gate-source voltage with
a . change 'in device temperature at' a specified
operating condition.
Q.Vos = !(VGS1-VGS2)IT1 - (VGS1-VGS2)IT2!
Q.T
Tl-T2
6-56
VG1.G2
Physical Dimensions
All dimensions expressed as
"'0
(mi:~i:::erS)
::r
~----------------------------~------~----~--------------------~~
(i'
0.545-0.555
r
0.lI5-o.ll5
0.490
U2.45)
MIN
L~
---1.
I:::::)J~ ~ ~ ~ ~
~:~~:)
MAX
l
MAX
~
0.500t
.
(12.'00~~ ~
-,
3
CD
:::I
O::!:.Olo
~
~ ~
en
0'
:::I
en
(0.559-0.162)
-ll-~
10.406-0A8l)
0.120-0.160
Il.048-4.064)
DIA
~~
Q)
I
0.148-0.181
Il.159-4.591)
olA
0.165-0.185
(4.191-4.699)
c
Ul.B4l-14.091)-----!
OIA
r-~J
~---------+~(8.001-8.509)
(0.l81-0.48l)
DIA 10 LEADS
0.595-0.605
(15.113-15.361)
OIA
-'-----"r-
0.026-0.0l6
l
Package 1
lD·Lead TO·S Metal Can Package IHI (Low Profile)
NS Package Number H1DA
I
0.545-0.555
(1l.84l-14.091)·
DIA
•
I
Package 2
l2·Lead TO·S Metal Can Package (G)
NS Package Number H12B
0.178-11.191
~:r
T
0.500-0.560
R
(:~::=:!~:)
0.188-0.210 •
mn:::1n1tr
m
~
0.500
(~j~O)
ODD
0.022-0.0l0
(0.559-0.762)
0.016-0.019
(0.406-0.48l)
u,~~9~~~
-II--
O.OlO
10.762)
MAX
(DAOB-DA83)
DIA 12LEADS
Package 3
l2·Lead TO·S Metal Can Package (G)
(AH2ll4/ AH2ll4C .only)
NS Package Number H12C
PIN
FET N(02)
1
s
FET P (11)
S
2
D
G.
3
G
D
Package 4
3·Lead TO·1S (02, 11) Metal Can Package
NS Package Number HD3D
7·3
t/)
c
.2
U)
c
G)
.-E
c
-co
.~
U)
~
.c
0.
,-$§~i
Q
(:::::=:::~~)
"
0.178-0.195
1
-L-
51:::11::.953)
~PLANE
o0 0
-II--
~~" ~
0.016-0.019
10.406-0.4831"
I-
0.016-0.019 ~
(0.406-0.483)
0.045
(1.143)
(3.607-4.039)
PLAN~
SEATING
0.500
~)
R
g 51
0.Z09-0.Z19
lI5.309_5.563)
0.14Z-0.159
0.500
I1Z.70)
0.030
10.76ZI
MAX
MAX
~
PIN
FET
1
S
D
G
2
3
Package 5
3·Lead TO.J9 (09) Metal Can Package (H) (High Profile)
NS Packaga Number H03G
R
0.016-0.019
10.406-0.483)
-II--
2-
S
D
3
G
H (~:~~!=~~~!I
. ,,:::;]nltT~
m
o
I:~::=:~!:I
0.188-0.Z10
W
mom
FET(07)
1
Package 6
3·Lead TO·52 (07) Metal Can Package
NS Package Number'H03J
. ,,:,~:;" InltT'
0.178-0.191
PIN
0.178-0.191
0.500
0.500
l~i~OI
00
0.030
(0.76ZI
MAX
0.016-0.019
(0.406-0.4831
-II--
(~i10I
0.030
(0.76Z)
MAX
0.100
PIN
FET
1
2
S1
D1
Gl
S2
D2
G2
3
5
6
7
Package 7
6·Lead TO·71 (12) Metal Can Packaga
NS Package Number H06A
PIN
FET P(23)
FET N(25)
1
S
2
G
S
D
3
D
G
Package B
4·Lead TO·72 (23,25) Metal Can Packaga (HI
NS Packaga Number H04C
7·4
0.175-0.185
'~""'= ~110.5g~1 ~ ~(15.0881
HOLE
MAX
CD
:::I
--1
0.045-0.055
0.045-0.055
11.143-1.3971
0.003-0.013
(0.076-0.3301
---R
0.085-0.095
(2.159-2.4131
---R
PIN
FET
1
2
3
51
Dl
Gl
4
Case
5
52
D2
G2
6
7
~~rmr
+=-
~
jMAX
0.025
(0.6351
MIN
-
2
D
S
5
G
3
5
D
D
Package 10
3-Lead TO-92 (71, 72, 741 Plastic Package
NS Package Number Z03A
:-j
~
(2.5401
0.180
74
FET case 71 and 72 are interchangeable without compromise in performance except some RF application
atVHF
0.160
(4.0641
(4 5721
72
G
PIN 71
1
G
Package 9
6-Lead TO-7S (241 Metal Can Package (HI
NS Package Number H06B
rl
r"::41
I· 0.160
(4.5721
0I:~
(4.5721
0.100
12.5401
,:h ."=1
-1
MIN
0.014-0.016
II
0.150-0.1BO
II 0.015
(0.356-0.4061-11-(3.810-4.5721
--11-- (0.3811
3LEADS
0.100
3 LEADS
--t 1-'0' NO (2.5401
I,
DIA 'PIN CIRCLE
0.014-0.016
II
~
II 0.015
(0.356-0A06I-11-(3.810-4.5721
--11--(0.3811
3 LEADS
.t!l!!L
3 LEADS
--t@f'0'NOM(2'5401
I
DIA PIN CIRCLE
3~'
3,2 .... 1
PIN
1
D
2
3
5
PIN 71
72
G
D
5
G
5
D
1
2
FET
3
74
5
G
D
G
TO-1S lead form available on special order or standard
on some products converted from TO-106 package.
Package 11
3-Lead TO-92 (77) Plastic Package
NS Package Number Z030
Package 12
3-Lead TO-92 (TO-1S Lead Forml Plastic Package
NS Package Number Z03E
7-5
S?
3
(J).
o·
:::I
(J)
en
c
o
'en.
cQ)
E
(:::::~:::)
~
L~~
OIA
0.165-0.185
0.315-0.335
(8.001-8.509)
DIA
(4.191-4.699)
C
'i
(J
0.500
0.035
(0889)
(12.70)
MIN
MAX
----r INSULATOR
L-~
~~ ~ ~~
t
(1.016)
MAX
-II- 0.016-0.019
'~
PIN
FET
1
2
51
D1
G1
3
4
5
6
(0.406-0.483)
.c
Q.
7
8
Package 13
B-Lead TO-99 (24 Alternate) Metal Can Package·(H)
NS Package Number HOSB
C ,:~i~)~
mml-.14
1:1
12
11
ii1
0.280
(7.112)
MAX
'-r.-r-m--r;-r--r.r-TiT"l'1iT'T;r'---L
rUl
0.31'0
(7.874)
".;~~
0.008-0.012
(0.203-0.305)
.
0.325 +0.025
I-~~,
f8.255 +0.635\
-0.381/
~
T ,·
0.165
(4.191)
MAX
0.037-0.050
,
0.050'0.010
~)
J
1L
p~0.045'O.015
,43 ±0.381)
-lL
o.015-0.o19
(0_381-0A83)
0_100'0_010
(2.540 ,0_254)
0.125
(3_175)
MIN
Package 14
14-Lead Cavity DIP (D)
NS Package Number D14A
r
IF
'0.310
(7_874)
---j
!!!!II
BMAX
+0_025
~_325-D_OI~
fU55 +0.635\, '
I
-D.3811
0_020,0_010
(0_508 ,0_254)
0_008:~~~~N~
llf'!!:"~!5!!!~E=~~~~
(0203-0.305)
0_100±0_010---l
12_540 ±0_254),
'---0_015--11_019
(0.381-0_483)
JI--
Package 15
16-Lead Cavity DIP (D)
NS Package Number D16A
7-6
(3_175)
MIN
Case
52
D2
G2
5ub
"tJ
:::r
'<
(J)
o·
-c_.
OJ
17.5691
MAX
~~r.r~~~,~--L
3
0.054
0.485
R
I I
'i~~21 ~
I~I&'~~~I I:::~~=:::::I
Jmvvvw
0.008-0.015
(0.203-0.3811
0.300
I-- (7.6201--1
L
Ijr--
0.050 '0.010
(1.270,0.2541
I
0.100 '0.010
MIN
(2.540 '0.2541
Package 16.
14-Lead Side·Brazed Cavity DIP (D)
NS Package Number D14E
PIN NO.1
IOENT~
f---,,~~--jI
I
.
JIj L
MAX
dl:r
MAX
nr-r-~=;::;=;=;::;=;:::;=~
R~
I I
0.300
r-,7.620)
0.008-0.015
(0.203-0.3811
--i
0.050,0.010'
(1.270 '0.2541
r-
REF
.
.
0.015-0. 023
10.381-0.5841
.JL
I
0.125
(3.1151
0.100,0.010
MIN
Package 17
16·Lead Side·Brazed Cavity DIP (D)
NS Package Number D16C
0.785
•
I
o.llo
.'7.874)
r-~~~~~~~~~~~~ ~t:~
0.025
0.291
(7.3911
MAX
~~~~~~~~--L
0.160
0.290-0.320
0.200
Fii'¥t~'J
(0.203-0.3051
'--~--l
(9.119,0.635)
~
12.5401
MAX BOTH ENOS
I
J
r-
Package 18
14·Lead Cavity DIP (J)
NS Package Number J14A
7·7
.
---..LI:::~:=:::::I
(2.540 ,0.2541
10.6351
RAO
(J)
ci':::l
(J)
0.015-0.023
0.125
(0.381-0.5841-11-- (3.1151
REF
CD
:::l
U)
C
0.785
o
t:-:
'(j)
&
0.025
(0.635)
RAO
'C
'Q)
E
15
(l9.939)~
MAX
14
13
12
11
10
9
0.310
--rr MAX GLASS
(7.874)
0.291
(7.391)
MAX
~r.n~orn~o.nT~
c
-,-B
1
0.160
0.290-0.320
0.200
(5.080)
MAX 0.020-0.070
GLASS
SEALANT
~(4'164)
!~Tn"
~~~~'J' 'j L
~
.c
0.
--I
0.385 +0.025'
(9.779 ±0.635) f--
0.050
(I~~~
0.018 ±0.002
(0.457 ±0.051)
~
--II--
0.125
(3.175)
MIN
O.loo±O.Olo
(2.540 ±0.254)
Package 19
16-Lead Cavity DIP (J)
NS Package Number J16A
0,400
0.092
. (2.337)
OIA
NOM
PIN NO. llNOENT
PIN
(6.350 ±O.lm
0.045
(1.143)
TYP
0.030
(0.762)
0.300-0.320
bffi..;~;=r.rI--.l
19:-..,IJJ
I
I
]:.
(0.229-0.381)
0.045 ±0.015
(1.143 '0.381)
' 032 +0.025'
. 5 -0.015
(8255 +0.635)
-0.381
2
7
Sl
01
G1
S2
02
G2
8
NC
0.100
(2.540)
TYP
Package 20
S-Lead Molded Mini,DIP (60.67) (N)
NS Package Number NOSA
0.092
(2.337)
OIA NOM
PIN NO.1 INDENT
0.300-0.320
0.030
C::~~I "j'
!~
-+.
0.009-0.015
I
,
0.040
•
I
Jt
0.130 ±0.005
MAX
fJ-U- L
(0.229-0.381)
0.075 ±0.015
(1.905 ±0.381)
0.020
.
~l-
~
0.325 ~:~~:
~y~O)
18 255 +0.635)
~.
-0.381
Package 21
14-Lead Molded DIP (N)
NS Package Number N14A
7-8
67
NC Sl
3
4
5
6
0.130 ±0.005
60
.i
(0.508)
0.018 ±0.003 0.125 MIN
(0.457 ±0.076) (~~~5)
01
NC
G1
S2
02
NC
G2
0.870
(22.098)~
MAX
13
•
12
11
10
9
t0.250 ,0.005
~rr=TIflf,Ff.rr=F.T~~~~(~0.127)
0.030
W
___
.0.300-0.320
(
(0.762)
MAX
"S"
•7.620-8.128)._
~
I
i -~
I.
0.325+0.025 '
~
I
........
0.065
tJr:=:r-----!!!~.LLiL
0.009-0.015
~
~I~
--I _
(0.229-0.381!
0.075'0.015
(1.905
,0.381)
-f.
O.t
0.125 (0.508)
0.01UtO.003
(8.255 +0.635)
--lJ.381
(0.457;0.076)
(3.175) MIN
MIN
Package 22
N1S-Lead Molded DIP (N)
5 Package Number N1SA
0.275
~
0.004-0.006
.
1
0.080
(2.032)
MAX
IIII
(0.102-0.152)til+
(~~:)J
.
GLASS,
(SnUARE)
1II.H--
~1
(0.254-0.635)
.
0.050 '0.005
(1.270,0.127)
"~,,l
PIN NO.1
10ENT
8
,,.
1--
.:
]'"''
0.750-0.770
~~ 0.015-0.019
(0.508-1.016)
(0.381-0.483)
Package 23
14-Lead Flat Package (F)
NS Package Number F14A
0.390
f--(9.906j~
0.080
-j I-- (2.032)
0.004-0.006
(0.102-0.152)
I I
-r1rr-
0.007-0.018
_ (0.178-0.457)-
MAX
MAX GLASS
Il-- --1I f-
0.050 '0.005
(1.270'0.127)
II
PIN NO. 1
11111514131211109
IDENT'-......I
,.
1-~~
(0.508-1.016)
T
0.275
. (6.985)
23.567·UI
0.880-0.900
(22.352-22.860)
---l '--
t
0.015-0.019
(0.381-0.483)
Package 24
~~-Lead Flat Package (F)
Package Number F16A
7-9
\
.
The Data
Bookshelf:
Tools For
The Design
Engineer
National Semiconductor's Data Bookshelf
is a compendium' of information about a
product line unmatched in its breadth in
the industry. The fifteen independent
volumes that comprise the Bookshelf over 5000 pages - describe in excess of
6000 solid-state devices; devices that
span the entire spectrum of
semiconductor processes, and that range
from the simplest of discrete transistors
to microprocessors - those
most-sophisticated marvels of modern
integrated-circuit technology.
Active and passive devices and circuits;
hybrid and monolithic structures; discrete
and integrated components ... Complete
electrical and mechanical specifications;
charts, graphs, and tables; test circuits
and waveforms; design and application
information : .. Whatever you need you'll
find in the designer's ultimate reference
source - National Semiconductor's Data
Bookshelf.
Ordering
Information
All orders must be prepaid. Domestic
orders must be accompanied by a check
or a money order made payable to
National Semiconductor Corp.; orders
destined for shipment outside of the U.S.
must be accompanied by U.S. funds.
Orders will be shipped by postage-paid
Third Class mail. Please allow
approximately 6-8 weeks for domestic
delivery, longer for delivery outside of the
U.S.
_~National
a
Semiconductor
DATA BOOKSHELF ORDER FORM.
Please send me the volumes of the National Semiconductor DATA BOOKSHELF that I have.selected
below. I have enclosed a check or money order for the total amount of the order, made payable to
National Semiconductor Corporation.
Name_~
___________
~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Street Address,_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
City _ _ _ _ _ _ _ _ _ _ _ State/Country _ _ _ _ _ _ _ _ _ _ Zip _ _ _ _ __
_ _ _ copies@$4.00,AudioHandbook, 4/76 ..................................... Total $,_-,-_
_ _ _ copies@$3.00,CMOS Databook, 3/75 ..................................... Total "",$_ __
_ _ _ copies@$4.00,lnterface Databook, 10/75............................ ~ ... Total $,_ __
_ _ _ copies@$4.00,linearApplications,Vol. 1,2/73 ....................... Total $,_ __
_ _ _ copies@$4.00,linearApplications,Vol. II, 7/76 ...................... Total $ _ - _ _ _ copies@$4.00,linear Databook, 6/76 ...................................... Total $,_ __
_ _ _ copies@$3.00,Memory Databook, 1/76................................... Total $,_ __
_ _ _ copies@$5.00,PACEDesigner'sGuide, 1977 ........................ Total
.p..$_ __
_ _ _ copies@$4.00,MOS/LSI Databook, 1977 ................................ Total $,_ __
_ _ _ copies @ $5.00, 8080A Microprocessor
System Design Manual, 3/77 ........................... Total $ _ __
_ _ _ copies @ $5.00, PACE Microprocessor Assembly
Language Programming Manual, 1/77 ............ Total $_ __
_ _ _ copies @ $5.00, PACE Microprocessor System
Design Manual, 3/77 ........................................ Total "",$_ __
_ _ _ copies @ $3.00, Power Transistor Databook, 1977 ................... Total $_ __
_ _ _ copies @ $5.00, SC/MP Microprocessor
Applications Handbook, 1977 .......................... Total $-,-,_ _
-'--_ _ copies @ $5.00, SC/MP Microprocessor Assembly
Language Programming Manual. ..................... Total .p..$_ __
-,--_ _ copies @ $3.00, Special Function Databook, 4/76...................... Total $_ __
_ _,-copies@$4.00,TTLDatabook, 2/76......................................... Total $,_ __
_ _ _ copies@$3.00,VoltageRegulator Handbook, 5/75: ................. Total • "",$_ __
Subtotal $
(California Residents Add 6% Sales Tax*) $
Grand Total $
MAIL TO:
NATIONAL SEMICONDUCTOR CORP., c/o MIKE SMITH
P. O. BOX 60876, SUNNYVALE, CA. 94088
Postage will be !!!lId by National Semiconductor Corp. Plaaae allow 6-8 _ka for delivery•
.*(San Francisco Bay Area Residents Add 6V2% Sales Tax)
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19 Create Date : 2017:06:17 09:57:50-08:00 Modify Date : 2017:06:17 10:13:37-07:00 Metadata Date : 2017:06:17 10:13:37-07:00 Producer : Adobe Acrobat 9.0 Paper Capture Plug-in Format : application/pdf Document ID : uuid:d607b9d5-324c-2144-b77c-db1a90de63cb Instance ID : uuid:278efba0-d964-fc4a-8652-8976761423a7 Page Layout : SinglePage Page Mode : UseNone Page Count : 290EXIF Metadata provided by EXIF.tools