1977_National_MOS_LSI_Databook 1977 National MOS LSI Databook
User Manual: 1977_National_MOS_LSI_Databook
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Edge Index
by Product Family
Clocks
Counters/Timers
Electronic Organ Circuits
. TV C'ircuits
Analog to Digital (A/D) Converters
Communications/CB Radio- ~ircuits
Watches
Calculators
Controller Oriented Processor Systems (COPS)
III
g
BJI
D
GIl
a
fJI
g
g
Keyboard Encoder Circuits
.ID)
Interface Drivers
iii
Displays
If)
Clock Modules
m
Custom MaS/LSI
III
Table of Contents
Edge Index by Product Family, , , , , , , , , , , , , , , .,' , , , , , , , , , , , , , " , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,
Alpha-Numerical Index, , , , _ , , , , , , , , , , , , , , , , , _ , , , , , , , _ , , , , , , _ , , , , . , , , , , , , , , . , , , , , , , :. ' , , ,
1
6
CLOCKS - SECTION 1
MM5309 Digital Clock, , , , . , , , , , , , , . , , , .. , , , , . , , , , , , , , , , ,
MM5311 Digital Clock, , , , , , , , , , , , , . , , , , , , , , , , , , , , , , , , , , ,
MM5312 Digital Clock. , , , " , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,
MM5313 Digital Clock, , , , . , . , , , , , , , , , , , , , , , , , , . , , , .. , , , ,
MM5314 Digital Clock, , , , . , , , , , '.' , , , , , , , , , , , , , , , " , , , , , ,
MM5315 Digital Clock, , , , ., , , , " , , , , " , , , , , , , , , , " , , , , , ,
MM5316 Digital Alarm Clock, , , , , , , , , , , , , , , , , . , , , , , , , , , , , ,
MM5318 TV Digital Clock, . , , , , , , , , , , , , , , , , , , , , , , , . , , , , , ,
MM5370 Digital Alarm Clock, , , , , , , , , , , , , , , , , , , , . , , , . , , , , ,
MM5371 Digital Alarm Clock. , , , , , . , , , , , , , , , , , , , , , , , . : , , , ,
MM5375XX Series Clocks, , , , , , , , " , , , , , , , , , , , , , , , , , , , , , , , ,
MM5376XX Series Clocks, , , , , , , , , , , , , , , , , , , , , , , , . , , , , , , , ,
MM5377 Auto Clock, ,', , . , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,
MM5378 Auto Clock, , , , , , , , , , , • ' . , , , , , , , , , , , , , , , , , , , . , ,
MM5379 Auto Clock, , , , , , .. , , , , , .. , , , , , , , , , . , , , , , , , , , , ,
MM5382 Digital Calendar Clock Radio Circuit, . , , , , , , . , , , , , , , , . ,
MM5383 Digital Calendar Clock Radio Circuit, , , , , , , , , , , , , , , , , , ,
MM5384 LED Display Digital Clock Radio Circuit, , , , , , , , , , , , . '. , ,
MM5385 Digital Alarm Clock .. , , , , . , , , , , , . , , , , . , , , , , . , , , . ,
MM5386 Digital Alarm Clock , . , , , , . , , , , , , . , , , , , , , , , , , , , , ,",
MM5387 AA Digital Alarm Clock, . , , , , , , , , , , , , , , , . , , , , , , , . , ,
MM5396 Digital Alarm Clock , , , , , , , , , , , , , , , , , , . , , , , , , , , , , ,
MM5397 Digital Alarm Clock , , , , , , , , , , , , , , , , , , . , , , , , , , , . , ,
MM5402 Digital Alarm Clock, , , , , , . , , , , , , , , , , , . , , , , , , , , .. ,
MM5405 Digital Alarm Clock, , , , , .. , , , , , . , , , , , , , , , , , , , , . , ,
MM53108 Digital Alarm Clock, , , , , , , , , , , , , , , , , , , , , , , , , , , .. ,
AI'J-143 Using National Clock Integrated Circuits in Timer Applications
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1-2·
1-2
1-2
1-2
1-2
1-2
1-9
4-2
1-14
1-14
1·21
1·27
1-33
1-38
1-38
1-43
1-43
1-50
1-56
1-56
1·62
1·56
1-56
1-68
1-68
1-62
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2-2
2-7
2-10
2-20
2-23
2-33
COUNTERS/TIMERS - SECTION 2
MM5307 Baud Rate Generator/Programmable Divider,
MM5369 17-Stage Programmable Oscillator/Divider, , ,
MM5865 Universal Timer, , , , .. , , , , , , , , , , , , , ,
MM53107 17-Stage Oscillator/Divider, , , , . , , , , , , ,
AN-168 MM5865 Universal Timer Applications, , , , , ,
AN-169 A 4·Digit, 7-Function Stopwatch/Timer, , , , ,
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ELECTHONIC ORGAN CIRCUITS - SECTION 3
MM5554
MM5555
MM5556
MM5559
MM5823
MM5824
Frequency Divider, , , , , , , . , .
Chromatic Frequency Generator,
Chromatic Frequency Generator,
Serial-to-Parallel Converter, , , , ,
Frequency Divider, , . , , , , , , ,
Frequency Divider, , , . , , , , , ,
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3-2
3-4
3-4
3·6
3-8
3-8
ELECTRONIC ORGAN CIRCUITS - SECTION 3 (Continued)
MMs832
MM5833
MM5837
MM5871
MM5891
Chromatic F=requency Generator .............. ~ . . . . . . . .
Chromatic Frequency qenerator . . . . . . . . . . . . . . . . . . . . . . .
Digital Noise Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rhythm Pattern Generator. . . . . . . . . . . . . . . . . . . . . . . . . . .
MOS Top Octane Frequency Generator. . . . . . . . . . . . . . . . . .
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3·11
3-11
3-14
3-16
3-19
TV CIRCUITS - SECTION 4
LM1889* TV Video Modulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .
MM5318 TV Digital Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5320 TV Camera Sync Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . •
MM5321 TV Camera Sync Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5322 Color Bar Generator Chip ........ :. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5840 TV Channel Number (16 Channels) and Time Display Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5841 TV Channel Number and Time Readout Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM53100 TV Game Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM531 04 * TV Game Clock Generator. . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM53105 Programmable TV Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM57100* TV Game Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM58106 Digital Clock and TV Display Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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.. 4-48
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4-2
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4-6
.. 4-12
.. 4-18
.. 4-23
.. 4-28
.. ,4-32
.. 4-50
.. 4-32
.. 4-37
.. 4-53
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5-2
5·23
5-30
5-36
5-44
MM5303 Universal Fully Asynchronous Receiver/Transmitter . . . . . . . . . . . . . . . . . . '. . . . . . . . . . . . . . . . . . . .
MM5393 Push Button Telephone Dialer. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .
MM5395 TOUCH-TONE® Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM55104 PLL Frequency Synthesizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM55106' PLL Frequency Synthesizer. . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM55108 PLL Frequency Synthesizer with Receive/Transmit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM55110 PLL Frequency Synthesizer with Receive/Transmit Mode. . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .
MM55114 PLL Frequency Synthesizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM55116 PLL Frequency Synthesizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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6-2
6-8
6-11
6-16
6-16
6-20
6-20
6-16
6-16
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7-2
7-6
7-12
7-6
7-13
7-13
7-12
7-20
7-12
7-27
7-32
7-40
7-40
7-40
ANALOG TO DIGITAL (A/D) CONVERTERS - SECTION 5
LF13300 Integrating A/D Analog Building Block . . . . . . . . . . . . . . . . . . . . . . ; . . . . . . .
MM53304 1/2-Digit Panel Meter Logic Block. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .
MM5863 12-Bit Binary A/D Building Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '.
AN-155 Digital Voltmeters and the MM5330 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-156 Specifying A/D and 0/ A Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .
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COMMLiNICATIONS/C.B. RADIO CIRCUITS - SECTION 6
WATCHES - SECTION 7
MM5B29 LED Watch Circuit ........ : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5860 LED Watch Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM587'9 RC Circuit ... , . . . . . . . . . . . . . .'. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM'5880 LED Watch Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5885 Direct Drive LED Watch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5886 Direct Drive LED Watch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . •. . . . . . . . . . . . . . . . .
MM5889 RC Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5890 LCD Chronograph Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5899 BC Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM58104 Direct Drive LED Watch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '.
MM58115 Digitally Tuned, Direct Drive, 6-Function LED Watch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM58117 LCD Watch Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM581'18 LCD Watch Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM58119 LCD Watch Circuit. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .
*TV Game Kit #SK 1115 includes this circuit
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TOUCH-TONE® is a Registered Trademark of Bell Telephone
3
WATCHES - SECTION 7 (Continued)
MM58120
MM58127
MM58128
MM58129
MM58130
MM58601
MM58801
LCD Watch Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . :
LCD Watch Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .'. . . . . . . . . .
LCD Watch Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LCD Watch Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LCD Watch Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Two Time Zone LED Watch Circuit. _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . ..
Two Time Zone LED Watch Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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7-40
7·47
7·47
7-47
7-47.
7-6
7-6
CALCULATORS - SECTION 8
MM5734 8-Function, Accumulating Memory Calculator ... , . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .
MM5737 8-Digit, 4-Function, Floating Decimal Point Calculator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .
MM5758 Scientific Calculator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " . . ..
MM5760 Slide Rule Calculator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5762 Financial Calculator. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5763 Statistical Calculator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " ...... " . . . . . . . . . . . .. . . . . . . . . . ..
MM5764 Conversion Calculator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5765 Calculator Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . ',' . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5766 Calculator Programmer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .. . . . . . ..
MM5767 Slide Rule Calculator. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5777 6-Digit, 4-Function, Floating Decimal Point Calculator. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5780 Educational Toy Calculator. . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5791 7-Function, Accumulating Memory Calculator .... .'. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5794 7-Function, Accumulating Memory, Vacuum Fluorescent Display Calculator . . . . . . . . . . . . . . . . . . . . . . . .
MM5795 7-Function, Accumulating Memory, Vacuum Fluorescent Display Calculator . . . . . . . . . . . . . . . . . . . . . . .'.
MM57103 Scientific Calculator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM57104 Scientific Calculator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ~ .......
MM57123 Financial Calculator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM57135 Scientific Calculator ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . .-. . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM57136 RPN Scientific Calculator Control ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .'.
AN-112 Calculator Chip Makes a Counter . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . • . . . . . . ..
AN-119 Calculator Learns to KeepTime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AN-149 Handheld Calculator Battery Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " .....
AN-176 Using Standard National Calculators in Industrial and Microprocessor Applications . . . . . . . . . . . . . . . . . . . .
8-2
8-8
8-14
8-26
8-35
8-46
8-56
8-66
8-76
8-80
8-84
8-90
8-96
8-105
8-114
8-123
8-132
8-141
8-153
8-157
8-163
8-169
8-177
8-181
CONTROLLER ORIENTED PROCESSOR SYSTEMS (COPS) - SECTION 9
National's Controller Oriented Processor Systems . . . . . . . . . . . . . . . '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5781 Controller Oriented Processor System ..... ',' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . .
MM5782 Controller Oriented Processor System . . . . . . . . . . . . . . . . . . . . .' . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5785 RAM Interface Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . ','
MM5788 Printer Interf~ce Chip . . . . . . . . . . . . . . . . . . . . ',' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5799 Controller Orrented Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " .. ' .... .
MM57109 Number Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , .•.........
MM57126 COPS Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM57140 Controller Oriented Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-2
9-3
9-3
9-15
9-21
9-27
9-39
9-40
9-46
KEYBOARD ENCODER CIRCUITS -SECTION 10
MM5740 90-Key Keyboard Encoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . ..
MM5745 78-Key Keyboard Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,
MM5746 78-Key Keyboard Encoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM54C922/MM74C922 16-Key Encoder . . . . . . . . . . . . . . . . . . . . . . . . : . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54C923/MM74C923 20-Key Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , ... ' ....
AN-128 Microprocessor Mates with MOS/LSI Keyboard Encoder ...... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-139 MOS Encoder Plus PROM Yield Quick Turnaround Keyboard Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
10-2
10-10
10·10
10-16
,10-16
10-21
10-27
INTERFACE DRIVERS - SECTION 11
Display Driver Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CD4511BM/CD4511BC BCD·to·7·Segment Latch/Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS7664/DS8664 14·Digit Decoder/Driver with Low Battery Indicator . . . . . . . . . . . . . . . . . . . . . : . . . . . . . . . . .
DS8665 14·Digit Decoder/Driver (Hi·Drive) . '.' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8666 14·Digit Decoder/Driver (P.O.S.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : . . . . . . . . . . .
DS8692 Printing Calculator I nterface Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8693 Printing Calculator Interface Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8694 Printing Calculator Interface Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8867 8·Segment Driver; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . .
DS8868 12·Digit Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8871 Saturating LED Cathode Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8872 Saturating LED Cathode Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8873 Saturating LED Cathode Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8874 9·Digit Shift Input LED Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8877 6·Digit LEO Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8892 Programmable Hex LED Digit Driver'. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8977 Saturating LED Cathode Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS75491 MOS·to·LED Quad Segment Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . . . . . . . . .
DS75492 MOS·to·LED Hex Digit Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .' . . . . . . . . . . . . . . . . . .
DS75493 Quad LED Segment Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54C48/MM74C48 BCD·to·7·Segment Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54C915/MM74C915 7·Segment·to·BCD Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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11·2
11·4
11·9
11·12
11·15
11·18
11·18
11·18
11·25
11·27
11·29
11·29
11·29
11·31
11·33
11·35
11·29
11·37
11·37
11·40
11-42
11·46
NSA 1100 Series 0.100 Inch 9·Digit LED Display. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
NSA 12980.110 Inch 9·Digit LED Display. . . . . .. .. . . . . .. . . . . . . . . . . . . . .. . . . .. . . .. . . . . . . . . . . . ..
NSA 51201/8 Inch 12·Digit LED Display. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
NSA 51401/8 Inch 14·Digit LED Display . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . .
NSB 59170.5 Inch 5·Digit Numeric Display . . . . . . . . . . .' . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . _ ..
NSB 59210.5 Inch 5··DigitNumeric Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .'
NSB 59220.5 Inch 5·bigit Numeric Display . . . . . . . . . . '.. '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Multi·Digit LED Numeric Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AN·170 Mounting Techniques for Multidigit LED Numeric Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
12·2
12·6
12·8
12·10
12·12
12·12
12·12
12· 14
12·22
DISPLAYS - SECTION 12
CLOCK MODULES - SECTION 13
MA 1002
MA1003
MA 1010
MA1012
MA1013
LED Display Digital Electronic Clock Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. '13·2
12 VDC Automotive/Instrument Clock Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
13·8
LED Display Digital Electronic Clock Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13·11
LED Display Digital Electronic Clock Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13·17
LED Display Digital Electronic Clock Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13·23
CUSTOM MOS/LSI - SECTION 14
Custom MaS at National . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
14·2
ORDERING INFORMATION/PHYSICAL DIMENSIONS
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Definition of Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
A·1
A·2
,A·8
Manufactured under one or more of the following U.S. patents: 3083262, 3189758, 3231797, 3303356, 3317671, 3323071. 3381071, 3408542, 3421025, 3426423, 3440498, 3518750,3519897, 3557431, 3560765,
3566218,3571630,3575609,3579059,3593069, 3597640,3607469, 3617859, 3631312, 3633052, 3638131, 3648071, 3651565, 3693248.
National does not assume any responsibility for use of any circuitry described; no circuit patent licenses are implied; and National reserves the right, at any time without notice, to change said circuitry.
5
Alpha-Numerical Index
CD4511 BC BCP-to~ 7 -Segment Latch/Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
CD4511 BM BCD-to-7-Segment Latch/Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
DS7664 14-Digit Decoder/Driver with Low Battery Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .' .... . 11-9
DS8664 14-Digit Decoder/Driver with Low Battery Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
DS8665 14-Digit Decoder/Driver (Hi-Drive) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
DS8666 14-Digit Decoder/Driver (P.O.S.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
DS8692 Printing Calculator Interface Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ; . . . . . . . . . . . . 11-18
DS8693 Printing Calculator Interface Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18
DS8694 Printing Calculator Interface Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ' ........ . 11-18
DS8867 8-Segment Driver .. ~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ' ...... .' .. 11-25
DS8868 12-Digit Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " .......... . 11-27
DS8871 Saturating LED Cathode Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29
DS8872 Saturating LED Cathode Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '. . . . . . . . . . . . . . . . . . . . . . . . 11-29
DS8873 Saturating LED Cathode Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29
DS8874 9-Digit Shift Input LED Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-31
DS8877 6-Digit LED Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , ......... . 11-33
DS8892 Programmable Hex LED Digit Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .' .. . 11-35
DS8977 Saturating LED Cathode Driver . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29
DS75491 MOS-to-LED Quad Segment Driver . . . . . . . . . . . : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-37
DS75492 MOS-to-LED Hex Digit Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-37
DS75493 Quad LED Segment Driver. . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-40
5-2
LF13300 Integrating AID Analog Building Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM1889 TV Video Modulator . . . . . . . . . . : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-48
MA 1002 LED Display Digital Electronic Clock Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
MA1003 12 VDC Automotive/Instrument Clock Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
MA1010 LED Display Digital Electronic Clock Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
MA 1012 LED Display Digital Electronic Clock Module ...... " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17
MA1013 LED Display Digital Electronic Clock Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-23
6-2
MM5303 Universal Fully Asynchronous Receiver/Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ' .... .
MM5307 Baud Rate Generator/Programmable Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . , 2-2
,1-2
MM5309 Digital Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . " . . . . . . . . . . . . . . . . .
1-2
MM5311 Digital Clock . . . . . . . . . . .'., . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-2
MM5312 Digital Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-2
MM5313 Digital Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . .
1-2
MM5314 Digital Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-2
MM5315 Digital Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-9
MM5316 Digital Alarm Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . . .
4-2
MM5318 TV Digital Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5320 TV Camera Sync Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , 4-6
MM5321 TV Camera Sync Generator . . . . . . . . . . . . . . . . . . ' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
MM5322 Color Bar Generator Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
MM53304 1/2-Digit Panel Meter Logic Block . . . . . . . . . . . . . . . . . . . . . . . . . . '. . . . . . . . . . . . . . . . . . . . . . . . . 5-23
2-7
MM5369 17-Stage Programmable Oscillator/Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5370 Digital Alarm Clock' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .' .... . 1-14
MM5371 Digital Alarm Clock ........ " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
MM5375XX Series Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
MM5376XX Series Clocks .... ;' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . 1-27
MM5377 Auto Clock . . . . . . . . . . . . . . : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-33
MM5378 Auto Clock . . . . . . . . . . . . . . . . . . . . . . ' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-38
MM5379 Auto Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .' ... . 1-38
MM5382 Digital Calendar Clock Radio Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43
6
MM5383 Digital Calendar Clock Radio Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5384 LED Display Digital Clock Radio Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5385 Digital Alarm Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5386 Digital Alarm Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '. . . . . . . . . . . . . . . . . . . . . . .
MM5387 AA Digital Alarm Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5393 Push Button Telephone Dialer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ~ . . . . . . . . . . . . . . . . . . . .
MM5395 TOUCH·TONE@ Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ' . . . . . . . . . . . . . .
MM5396 D(,gital Alarm Clock
MM5397 Digital Alarm Clock
MM5402 Digital Alarm Clock
MM5405 Digital Alarm Clock
MM5554 Frequency Divider. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5555 Chromatic Frequency Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ; . .
MM5556 Chromatic Frequency Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5559 Serial·to·Paraliel Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5734 8·Function, Accumulating Memory Calculator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5737 8·Digit, 4·Function, Floating Decimal Point Calculator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5740 90·Key Keyboard Encoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5745 78·Key Keyboard Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5746 78·Key Keyboard Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5758 Scientific Calculator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ",' . . . . . . . . . . . . . . ..
MM5760 Slide Rule Calculator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5762 Financial Calculator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5763 Statistical Calculator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5764 Conversion Calculator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5765 Calculator Programmer .. '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5766 Calculator Programmer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5767 Slide Rule Calculator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5777 6·Digit, 4·Function, Floating Decimal Point Calculator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .'.
MM5780 Educational Toy Calculator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : . . . . . . . . . . . . . . . . . . . . ..
MM5781 Controller Oriented Processor System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . . . . . . . . . .
MM5782 Controller Oriented Processor System . . . . . . . . . . . . '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5785 RAM Interface Chip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . ..
MM5788 Printer Interface Chip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . ..
MM5791 7·Function, Accumulating Memory Calculator . . . . . . . . . . . . . . . : . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5794 7·Function, Accumulating Memory, Vacuum Fluorescent Display Calculator. . . . . . . . . . . . . . . . . . . . . . ..
MM5795 7·Function, Accumulating Memory, Vacuum Fluorescent Display Calculator Circuit ..... , . . . . . . . . . . . . .
MM5799 Controller Oriented Processor. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5823 Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5824 Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5829 LED Watch Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . • . .
MM5832 Chromatic Frequency Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5833 Chromatic Frequency Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5837 Digital Noise Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5840 TV Channel Number (16 Channels) and Time Display Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5841 TV Channel Number and Time Readout Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5860 LED Watch Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '.' ...... , . . . . . . . . . . . .
MM5863 12·Bit Binary AID Building Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5865 Universal Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5871 Rhythm Pattern Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5879 RC Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5880 LED Watch Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5885 Direct Drive LED Watch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5886 Direct Drive LED Watch. . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5889 RC Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5890 LCD Chronograph Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . ..
MM5891 MOS Top Octane Frequency Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM5899 RC Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM53100 Programmable TV Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM53104 TV Game Clock Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
TOUCH·TONE@ is a Registered Trademark of Bell Telephone
7
1·43
1·50
1·56
1·56
1·62
. 6·8
6·11
1·56
1·56
1·68
1·68
3·2
3-4
3·4
3·6
8·2
8·8
10·2
10·10
10·10
8·14
8·26
8·35
8·46
8·56
8·66
8·76
8·80
8·84
8·90
9·3
9·3
9·15
9·21
8·96
8·105
8·114
9·27
3·8
3·8
7·2
3·11
3·11
3·14
4·23
4·28
7·6
5·30
2·10
3·16
7·12
7·6
7·13
7·13
7·12
7·20
3·19
7·12
4·32
4·50
MM53105 Programmable TV Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM53107 17-Stage Oscillator/Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : . . . . . . . . . . . . . . . . . ..
MM53108 Digital Alarm Clock . . . . . . . . . . . . . . . . . . ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM54C48 BCD-to-7-Segment Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM55104 PLL Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . .
MM55106 PLL Frequency Synthesizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM55108 PLL Frequency Synthesizer with Receive/Transmit Mode. . . . . • . . . . . . . . . . . .. . . . . . . . . . . . . . . . ..
MM55110 PLL Frequency Synthesizer with Receive/Transmit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .' . ..
MM55114 PLL Frequency Synthesizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM55116 PLL Frequency Synthesizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM57100 TV Game Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM57103 Scientific Calculator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM57104 Scientific Calculator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ~ . . . . . . . . . . . . . . . . . . . . . . . .
MM57109 Number Processing Unit. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
MM57123 Financial Calculator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ',' . . . . . . . . . . . . .
MM57126 COPS Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM57135 Scientific Calculator ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . ~ . _ ..
MM57136 RPN Scientific Calculator Control ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM57140 Controller Oriented Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM58104 Direct Drive LED Watch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,
MM58106 Digital Clock and TV Display Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM58115 Digitally Tuned, Direct Drive, 6-Function LED Watch . . . . . . . . . . . . . . .'. . . . . . . . . . . . . . . . . . . . . ..
MM58117 LCD Watch Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ; . . . . . . ..
MM58118 LCD Watch Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . . . . _ . . . . . . . . . . . . . . .. . ..
MM58119 LCD Watch Circuit ...... ',' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ; . . .. . . . . . . . . . ..
MM58120 LCD Watch Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . ; . . . . . . . . . . . . . . . . . . '. . . . . . . . ... . . . ..
MM58127 LCD Watch Circuit . . . . . . . . . . . . . . . . . . . . .' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : . . . ..
MM58128 LCD Watch Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . ',' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ; . ..
MM58129 LCD Watch Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM58130 LCD Watch Circuit ...... : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM58601 Two Time Zone LED Watch Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM58801 Two Time Zone LED Watch Circuit. , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .' . . . .
MM74C48 BCD-to-7-Segment Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM54C915 7-Segment-to-BCD Converter . . . . . . . . . . . . . . . . '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .' . . . . . . . . . . . .
MM54C922 16-Key Encoder ..... .
MM54C923 20-Key Encoder . . . . . . . . . . . . ; . '. . . . . . . . . . . . . . . . . . . . .' . . . . . . . . . . . . . . . . . . . . ',' .....
MM74C915 7-SegmenHo-BCD Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . ..
MM74C922 16-Key Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM74C923 20-Key Encoder . . . . . . . . . . . . . ; .......... ',' . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . ..
NSA 1100 Series,O.100 Inch 9-Digit LED Display ..... " ........ " ........ '- . . . . . . . . . . . . . . . . . . " ..
NSA 12980.110 Inch 9-Digit LED Display. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . ..
NSA 51201/8 Inch 12-Digit LED Display. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
NSA 51401/8 Inch 14-Digit LED Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ;' . . . . . . . . . . . . . . . . . . . ;.
NSB 5917 0.5 Inch 5-Digit Numeric Display .. ; .. ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NSB 59210.5 Inch 5-Digit Numeric Display ... ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NSB 5922 0.5 Inch 5-Digit Numeric Display . . . . . . . . . . . . . . '.... ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NSN Series Multi-Digit LED Numeric Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ ......
8
4-32
2-20
1-62
11-42
, 6-16
6-16
6-20
6-20
6-16
6-16
4-37
8-123
8-132
9-39
8-141
9-40
8-153
8-157
9-46
7-27
4-53
7-32
7-40
7-40
7-40
7-40
7-47
7-47
7-47
7-47
7-6
7-6
11-42
11-46
10-16
10-16
11-46
10-16
10-16
12-2
12-6
12-8
12-10
12-12
12-12
12-12
12-14,
Clocks
For additional application information,
see AN-143 at the end of this section.
MM5309, MM5311, MM5312, MM5313,
MM5314, MM5315 digital clocks
general description
These digital clocks are monolithic MOS integrated
circuits utilizing P-channel low-threshold, enhancement
mode and ion implanted. depletion mode devices. The
devices provide all the logic required to build several
types of clocks. Two display modes (4 or 6-digits)
facilitate end-product designs of varied. sophistication.
The circuits interface to LED and gas discharge displays
with minimal additional components, and require only
a single power supply. The timekeeping function
operates from either a 50 or 60 Hz input, and the display format may be either 12 hours (with leading-zero
blanking) or 24 hours. Outputs consist of multiplexed
display drives (BCD and 7-segment) and digit enables.
The devices operate over a power supply range of 11 V
to 19V and 00 not require a regulated supply. These
clocks are packaged in dual-in-line packages.
•
Leading-zero blanking (12-hour format)
•
7-segment outputs
•
Single power supply
•
Fast and slow set controls
•
Internal multiplex oscillator
•
For features of individual clocks, see Table I
applications
•
Desk clocks
features
•
Automobile clocks
•
50 or 60 Hz operation
•
Industrial clocks
•
12 or 24-hour displayformat
•
Interval Timers
TABLEI.
FEATURES
MM5309
MM5311
MM5312
MM5313
BCD Outputs
X
X
X
X
4/6-Digit Display Mode
X
X
X
X
X
X
X
X
X
Hold Count Control
1 Hz Output
X
Output Enable Control
X
Reset
X
connection diagrams
MM5315
X
X
X
X
X
(Dual-In-Line Packages)
Voti....!
Rlil..l
~~~T~~~~~~~ ffii4..1
~OUTPUT ENABLE
vo02
~ 4/6 DIGIT SELECT
MULTlPLEX~O{::~
~ MUX TIMING
INEG~~~VE~ { ROZ..!
MM5309
c~
~:110
~Hl0
INEG~~~~~
~MUXTIMING
~ Mlj
BC1iZ..!
DIGIT
• ...!
~~~:~~S
:..2
~SS110
d""::
r-
OUTPUTS
• ..!.!!
~ 50160 Hz INPUT
,.!.!
~FASTS~T
~Ml0
~Hl
MM5311
c~
HI.' 0
~SI
d-"
~S10
• .!!l
~50160 Hz INPUT
50160 Hz SELECT
.!!.FASTSET
..!.!.SLOWSET
~HOLO
..!.!L-_ _ _ _--I>1l vss
TOPVIEW
TOPVIEW
Order Number MM5309N
Order Number MM5311 N
See Package 23
See Package 23
1-2
DIGIT
~~~:~~S
OUTPUTS
12/24 HOUR SELECT.ll
50160 Hz SELECT .!!I..-_ _ _ _---Ifl!.vss
~
MULTIPLEXED
lSEGMENT
[ ,.11
g.E
~SLOWSET
~ RE·SET
12124 HOUR SELECT.ll
~ 4/6 DIGIT SELECr
mil..1
MULTIPLEXED
1 SEGMENT
g.E
,1! OUTPUT ENABLE
BCD OUTPUTS
~Mlj
mil[O:~
b..2
MM5314
absolute maximum ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
VSS + 0.3 to VSS -,20V
-25°C to +70°C
-65°C to +150°C
300°C
electrical characteristics TA within operating range, VSS = llV to 19V, VDD
CONDITIONS
PARAMETER
Power Supply Voltage
VSS (VDD
Power Supply Current
VSS
= 14V,
TYP
MIN
= OV)
= OV, unless otherwise specified.
MAX
11
V
10
mA
60k
Hz
(No Output Loads)
50/60 Hz Input Frequency
dc
50 or 60
UNITS
19
Logical High Level
VSS-l
Logical Low Level
VDD
Multiplex Frequency
Determined by External R & C
All Logic Inputs
Driven by External Timebase
Logical High Level
Internal Depletion Device to VSS
VSS
V
VDD
VSS-l0
V
1.0
60
kHz
60
kHz
VSS-l
VSS
VDD
VDD
VSS
VSS-l0
0.100
VSS
dc
Logical Low Level
V
V
BCD and 7-Segment Outputs
Logical High Level
Loaded 2 kS"t to VDD
2.0
Loaded 100 S"t to VSS
5.0
Logical Low Level
20
' 0.01
mA
.-- source
mA source
0.3
mA source
25
mA sink
Digital Enable Outputs
Logical High Level
Logical Low Level
Connection diagrams (Continued) Dual-In-Line Packages (Top Views)
roo...!
(NEGATIVE
TRUE)'
li BCDB
BCD 2 2.
VDD...!
~VDD
BCili.1
MULTIPLEXED
BCD OUTPUTS
(NEGATIVE
TRUE)
E. MUX TIMING
~.,
.o.!
~Ml0
b...l
,OO!
MULTIPLEXED
7SEGMENT
DUTPUTS
}
.!!. HI
BCD
• .J.
,..!
.!!. 60/S0 Hz INPUT
g.!!!.
50/S0 Hz SELECT
MUL TlPLEXED
7SEGMENT
DUTPUTS
r
VDD
. MULTIPLEXED
7SEGMENT
OUTPUTS
..!!FASTSET
.!L SLOW SET
.!!VSS
~·'I
,.l.
p.!!. HI
do!.
r!! Hl0
,..!.
g.J.
~ 1 PPS OUTPUT
..1! so/so Hz INPUT
..;..;;.
Order Number MM5313N
See Package 23
VDO...!.
MULTIPLEXED
BCD OUTPUTS
(NEGATIVE
TRUE)
DIGIT
ENABLE
OUTPUTS
r!lS10
r!! 50/60 Hz INPUT
.!E.
50/60 Hz SELECT
..!.!.
rli FAST SET
r!! SLOW SET
VSS
.!!
~HOLD
{::::2
1!MUX TIMING
1!Mlj
'
BCD 2..!
BCD 1...1
1! Ml0
1! HI
DIGIT
6
• ...::.
23
=Hl0
ENABLE
OUTPUTS
MULTIPLEXED:~
r!!SI
12124 HR SELECT
l!4/S DIGIT SELECT
~2.
,!.!.Ml0
MM5314
.
.!!. HDLD
~ MUX TIMING
.2.
BSI
so/so Hz SELECT.!!
~ 4/6 DIGIT SELECT
3
DIGIT
ENABLE
OUTPUTS
11 S10
12124 HR SELECT.!l
2-
b.!.
MM5313
'9
d....;.
10
..!lvSS
1.. .
.-
~Hl
.!l Hl0
.!! SLOW SET
Order Number MM5312N
See Package 22
OUTPUT ENABLE
~"'j
~M1D
,.!!
g.E.
. .!!FAST SET
..!.!.
..!l
42
b..1.
:.J.
l!.1 PPS OUTPUT
1! MUX TIMING
BCD Z""!
BCD 1...1
MM531Z
.!!.Hl0
l!4/s DIGITSELECT
r~
DIGIT
ENABLE
OUTPUTS
d.2
12/24 HR SELECT
UlUl
ww
~~
UlN
50/60 Hz Input Voltage
"m'"","
BCD OUTPUTS
~~
~~
MM5315
~::O
7 SEGMENT
d ....;.
~ 50/S0 Hz INPUT
OUTPUTS
• ..!.!!
.!!. FAST SET
,.!!
g.E.
12/24 HR SELECT .!l
.!!.SLDWSET
50/60 Hz SELECT
[
l!.HOLD
.!!. RESET
.!!L-._ _ _ _--.l.!!VSS
Order Number MM5315N
See Pac~age 23
Order Number MM5314N
See Package 22
1-3
.
II
functional description
A block diagram of the MM5309 digital clock is shown
in Figure 1. MM5311, MM5312, MM5313, MM5314
and MM5315 clocks are bonding options of MM5309
clock. Table I shows the pin-outs for these clocks.
50 or 60 Hz Input: This input is applied to a Schmitt
Trigger shaping circuit which provides approximately
5V of hysteresis and allows using a filtered sinewave
input. A simple RC filter such as shown in Figure 10
should be used to remove possible line voltage transients
that cauld either cause the clack to. gain time ar damage
the device. The shaper output drives a caunter chain
which perfarms the timekeeping functian.
50 or 60 Hz Select Input: This input pragrams the'
prescale counter to. divide by either 50 ar 60 to. obtain a
1 Hz timebase. The caunter is programmed for 60 Hz
operation by connecting this input to. VDD. An internal
depletian device is comman to. this pin; simply leaving
this input uncannected programs the clock far 50 Hz
aperation. As shawn in Figure 1, the prescale co.unter
provides both 1 Hz and 10Hz signals, which can be
brought out as bonding aptions.
which is driven by a multiplex oscillator. The ascillator
and external timing companents set the frequency of
the multiplexing functian iand, as controlled by the 4 ar
6-digit select input, the divider determines whether data
will be output for 4 or 6 digits_ A zero-blanking circuit
suppresses the zero. that would otherwise sometimes
appear in the tens-of-hours display; blanking is effective
only in the 12-hour format. The multiplexer addresses
also become the display digit-enable outputs. The multiplexer outputs are applied to a decoder which is used
to address a programmable (code converting) ROM.
This'ROM generates the final output codes, i.e., BCD
and 7-segment. The sequential output order is from
digit 6 (unit seconds) through digit 1 (tens of hours).
Multiplex Timing Input: The multiplex oscillator is
shown in Figure 2. Adding an external resistor and
capacitor to this circuit via the multiplex timing input
(as shown in Figure 4a) produces a relaxation oscillator.
The waveform at this input is a quasi-sawtooth that is
squared by the shaping action of the Schmitt Trigger in
Figure 2. Figure 3 provides guidelines for selecting the
external components relative to desired multiplex
frequency.
Time Setting Inputs: Both fast and slow setting inputs,
as well as a hald input, are provided. Internal depletion
devices provide the narmal timekeeping function.
Switching any af these inputs (one at a time) to VDD
results in the desired time setting function.
Figure 4 also illustrates two methods of synchronizing
the multiplex oscillator- to an external timebase. The
external RC timing components may be omitted and
this input may be driven by an external timebase; the
required logic levels are the same as 50 or 60 Hz input.
The three gates in the counter chain (Figure 1) are
used for setting time. During normal operatian; gate A
connects the shaper output to a prescale counter (-;-50
or -;-60); gates Band C cascade the remaining counters.
Gate A is used to inhibit the input to. the counters for
the duration of slow, fast or hold time-setting input
activity. Gate B is used to. connect the shaper output
directly to a secands caunter (-;-60), the condition for
slaw advance. Likewise, gate C connects the shaper
output directly to. a minutes counter (-;-60) for fast
advance_
Reset: Applying VDD to this input resets the counters
to 0:00:00.00 in 12-hour format and 00:00:00.00 in
24-hour formats leaving the input unconnected (internal
cmpletion pull-up) selects normal operation.
Fast set then, advances hours infarmation at one hour
per secand and slow set' advances minutes informatian
at one minute per second.
12 or 24-Hour Select Input: This input is used to program the hours counter to. divide by either 12 ar 24,
thereby providing the desired display format. The
12-hour display farmat is selected by cannecting this
input to VDD; leaving the input uncannected (internal
depletian device) selects the 24-hour format.
Output MUltiplexer Operation: The seconds, minutes,
and haurs counters continuously reflect the time of day.
Outputs from each caunter' (indicative of bath units
and tens of seconds, minutes, and hours) are timedivision multiplexed to provide digit-sequential access
to the time data. Thus, instead af requiring 42 leads to
intercannect a 6-digit clock and its display (7 segments
per digit), ai/ly 13 output leads are required. The multiplexer is addressed by a multiplex divider decoder,
4 or 6-Digit Select Input: Like the other control inputs,
this input is provided with an internal depletion pull-up
device. With no input connection the clock outputs data
for a 4-digit display. Applying VDD to this input provides a 6-digit display. '
Output Enable Input: With this pin unconnected the
BCD and 7-segment outputs are enabled (via an internal
depletion pull-up). Switching VDD to this input inhibits
these outputs. (Not applicable to MM5312, MM5313,
and MM5315 clacks.)
Output Circuits: Figure 5a illustrates the circuit used
for the BCD and 7-segment outputs. Figure 5b shows
the digit enable output circuit. Figure 6 illustrates
interfacing these outputs to standard and low power
TTl. Figures 7 and 8 illustrate methods of interfacing
these outputs to common anode and comman cathode
LED displays, respectively. A method of interfacing
these clocks to gas discharge display tubes is shown in
Figure 9. When driving gas discharge displays which
enclose more than one digit in a common gas envelope,
it is necessary to inhibit the segment drive voltage(s)
during inter-digit transitions. Figure 9 also illustrates a
method of generating a voltage for application to the
output enable input to accomplish the required interdigit blanking.
functional description
5~~~~~;0-
(Continued)
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _....
~------------~IOHz
HOLOo-------------------,
~~~--------~~IHz
SLOW SET 0 - - - - - - - - - - " ' - - + - - - " "
FAST SET o - - - - - - - - J - - + - - - + - - - - - - + - - ,
RESETo--------J--+---+---~._---;_-~~--~...-~~-_,
VSSo---.}
VDD C>---+ AS REC'D
~---------_o~~!~~~
MULTIPLEXED
BCTi 0 UTPUTS
4/:E~I~~~
MULTIPLEXED
7-SEGMENT
OUTPUTS
0---------_
L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _"'- DIGIT ENABLE
MUL TlPLEX
TIMING
OUTPUT
1-----------------------------..,. . .
OUTPUTS
FIGURE 1. MM5309 Digital Clock Block Diagram
VOO----~J_-
50/60 PPS
OUTPUT OR
X>.....- ... MULTIPLEX
50/60 Hz
INPUT OR
MULTIPLEX - - - - - - - '
TIMING
COMPONENTS
OSCILLATOR
OUTPUT
lOOk
~.
....
r
:I:
VSS
>
z
I
I
I
I
I
I
I
I
I~-----O<
r11
I
vss
10k ~-F:r.
I
K
~
><
~
Ik
.~
::;:
~V~~ = OV
R '2.2~~
100
0.0001
0.001
C - CAPACITANCE
0.01
(~F)
0.1
WITH R = 220k
I
VSS
L~I.
::>
"A
1- _ _ ':""" _ _ ...1
~
Dotted components added to shaping
circuit to form multiplex oscillator
*Effectively
FIGURE 2.50/60 Hz Shaping Circuit/Multiplex Oscillator
FIGURE 3. Multiplex Timing Component Selection Guide
functional description
(Continued)
Vss
MM5309
VOO
FIGURE 4a. Relaxation Oscillator
Vss
Vss
Cl
C2
EXTERNAL ~
.
TIME
BASE
MM5309
MM5309
. (INPUT OR OUTPUT)
VOO
VOO
FIGURE 4b. External Time Base
FIGURE 4c. External Clock
Note. Free running frequency should be set to run slightly lower than system frequency
over temperature. External time base may be inputor output.
* R=100k.
FIGURE 4. Synchronizing or Triggering Multiplex Oscillators
vss
.
VSS
~vss
.-f}--1 .
vOO
vss
OIGIT ENABLE
OUTPUT
.
_
7-SEGMENT BCO OR lpPS
OUTPUT
(OPEN ORAIN)
600
VOO
FIGURE 5a '
vOO
FIGURE 5b
FIGURE 5. Output Circuits
'·6
functional description
(Continue.d)
MOS to Low Power TTL Interface
MOS to TTL Interface
VSS' 5V
VSS
ANY GATES
VSS' 5V
ANY TTL GATE
VCC' 5V
ss
SS
(11(11
ww
MM5l09
~~
(111\)
VOO
VOO = -12V
For VSS = 5, VOO = 12, R = 10k
For VSS = 5, VOO = -12, R = 7.5k
Note. ~igit select will drive TTL directly when
5, -12 supplies are used.
For VSS = 10 to 17V, VOO.= Gnd, R = 3k
FIGURE 6. Interfacing TTL
VSS--. . .----------tl~--
VSS--. . .---------~~--
VSS
TYPICAL 1 - - - - - - - - 1
SEGMENT
OUTPUT
VSS
TYPICAL 1 - - - - - - - - - 1
DIGIT
ENABLE
OUTPUT
I
'+\ ~~;~~~~ANOOE)
MM5l09
TYPICAL LEO
A
J
MM5l09
I
SUCH AS
NSN71L. OR
EIlUIV.
TYPICAL
TYPICAL
2k
SEGMENT I - - -......""~,....-t
OUTPUT ....I"""L..
TYPICAL LEO
SEGMENTS
(COMMON·CATHOOE)
SUCH ~S NSN74R.
OR EIlUIV.
EN~~~~ 1--.....,-.-------1
OUTPUT
vOO
........
5.1k
VOO--~----------4~----
(Vss VOOI/2 VF 1.5V
Vss - VOO VF 0.6V
RL = - - - - - - - NOFI
RL
Where R L as in k.l1
And VF = forward drop of LED
0.6V "" voltage drop of transistors
N = number of digits in display
IF = required average LED current
Where RL is in k.l1
And VF = forward drop of LED
0.9V .. voltage drop of transistors
N = number of digits in display
IF = required average LED current
= -------NOFI
*Transistors may be replaced by OM75491, OM75492,
OM8861, OM8863 or equivalent segment/digit drivers.
FIGURE 7. Interfacing Common Anode LED Displays
FIGURE 8. Interfacing Common Cathode LED Displays
1·7
functional description
(Continued)
(OV)
TYPICAL
DIGIT
ENABLE
OUTPUT
~
TYPICAL
SEGMENT
MM5J09
TYPICAL
SEGMENT
OUTPUT
MULTIPLEX
TIMING
INPUT
OUTPUT
ENABLE
..JI.....
O.OOS
(X7)
J9k
4.7k
VDD
(-15V)
MUL TIPLEX TIMING AND
INTER·DIGIT BLANKING
-JSV
-12SV
. FIGURE 9. Interface Panaplex 11* Neon Display Tube
*TM of Burroughs Corp .
OV
lN914
lOOk
AC IN
15
Vss
27
4/6
---mICiUl
01 2S
ANODE I
02 24
2NS086
(X4)
OJ 2J
0422
•
DRIVER
I
I
OJ
ONLY
MMSJ09
.
14
28
26
6
b c
7 8
SEG
d e
f
9
9 10 11 12
II
I" ,.,
0.02
2DOV
lOOk
TvPiCAil
CATHODE I
DRIVER
2NJ9D4
J90 pF
-lSV - - - . - -....- - . - - _ . - - -....
INTER·DIGIT BLANKING CIRCUIT
lN914
I
I
I
lN914
47k
22k
-=)~
, -JSV--~------------------__- -....-~+------~----~-~---4---4~
-105V------------------------------~-----_4~-----~---~---
FIGURE 10. MM5309 Driving Gas Discharge Display. Typical Applications
Clocks
MM5316 digital alarm clock
general description
The MM5316 digital alarm clock is a monolithic MOS
integrated circuit utilizing P-channel low-threshold,
enhancement mode and ion-implanted depletion mode
devices. It provides all the logic required to build several
types of clocks and timers. Four display modes (time,
seconds, alarm and sleep) are provided to optimize
circuit utility_ The circuit interfaces directly with 7segment fluorescent tubes, and requires only a single
power supply. The timekeeping function operates
from either a 50 or 6'0 Hz input: and the display format may be either 12 hours (with leading-zero blanking and AM/PM indication) or 24 hours. Outputs
consist of display drives, sleep (e.g., timed radio turn
off). and alarm enable. Power failure indication is
provided to inform the user that incorrect time is
being displayed. Setting the time cancels this indication. The device operates over a power supply range
of 8-29V and does not require a regulated supply.
The MM5316 is packaged in a 40-lead dual-in-line
package.
50 or 60 Hz operation'
Single power supply
•
Low power dissipation (36 r[1W at 9V)
•
12 or 24-hour display format
AM/PM outputs
}
.-.
12-hour format
Leadlng-zerQ blanking
•
24-hour alarm setting
•
All counters are resettable
•
Fast and slow set controls
•
Power failure indication
•
Blanking/brightness control capability
•
Elimination of illegal time display at turn on
•
Direct interface to fluorescent tubes
•
•
9-minute snooze alarm
Presettable 59-m inute sleep timer
applications
features
•
•
•
•
•
•
Alarm clocks
Desk clocks
•
Clock radios
•
Automobile clocks
•
•
Stopwatches
Industrial clocks
•
•
Portable clocks
Photography timers
•
Industrial timers
•
•
Appliance timers
Sequential controllers
block and connection diagrams
OUTPUT
COMMON
SOURCE
0---------------____---,
23
1212~E~~~~ o-:.;38~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___.
Dual-In-Line Package
40
AM OUTPUT
PM OUT
10HRS- b&<
HRS-I
HRS -g
36
HRS -.
3&
HRS- b
AL~~~ +"'--_ __.
ALARM
OFF
TO HRS
DIGIT
SNOOZE
SLEEP
OUT
TO 10'S
OF MINS
DIGIT
SLEEP DIS
0------------------+1
-+I
ALA~~ O-,-31~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _
SECO~~
TOMINS
DIGIT
HRS-<
SLOW SET IN
HRS-.
SECONDS DISPLAY IN
10MINS-I
ALARM DISPLAY IN
10MINS-g
SLEEP DISPLAY IN
10MINS-.&d
10MINS-b
10MINS-.
MINS -I
MINS-g
MINS-b
BLANKING 0-'-3;...1_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _+1 BLANKiNG
DETECTOR
INPUT
33
MINS-<
SLOWSET~
ALARM OFF IN
16
25
11
24
18
23
19
22
20
21
TOP VIEW
34
FASTSET~
28
Order Number MM5316N
29
See Package 24
VSS~
VOO~
FIGURE 1.
FIGURE 2.
1·9
Hz SELECT
FAST SET IN
MINS-.
0-:;32:....,,-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _-+1
~0/60
50/60 Hz IN
HRS - d
10MINS-<
16-22
BLANKING IN
ALARM OUT
SNOOZE IN
OUT COMMON SOURCE
MINS-<
MINS-d
absolute maximum ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
VSS + 0.3 to VSS - 30V
-25°C to +70°C
-65°C to +150°C
300°C
electrical characte,'istics
T A within operating range, VSS
= 21 V to +29V, VOO = OV,
PARAMETER
Power Supply Voltage
Power Supply Current
unless otherwise specified.
CONDITIONS
VSS (VOO = OV)
MIN
TYP
MAX
29
21
UNITS
V
No Output Loads
VSS = 8V
4
mA
VSS = 29V
5
mA
Counter Operation Voltage
8
50/60 Hz Input Frequency Voltage
dc
Logical High Level
VSS-l
Logical Low Level
VOO
50 or 60
VSS
VOO
29 .
V
10k
Hz
VSS
V
VOO+1
V
Blanking Input Voltage
Logical High Level
VSS-1.5
VSS
VSS
V
Logical Low Level
VOO
VOO
VSS-4
V
All Other Input Voltages
Logical High Level
Logical Low Level
Internal Oepletion Oevice to VOO
Power Failure Oetect Voltage
(VSS Voltage)
Output Currents, 1 Hz Oisplay
VSS = 21V to 29V,
VSS-l
VSS
VSS
V
VOO
VOO
VOO+2
V
20
V
10
Output Common = VSS
Logical High Level
VOH = VSS - 2V
Logical Low Level, Leakage
VOL=VOO
1500
J1A
1
J1A
10's of Hours (b & cl. 1 O's of Minutes
(a & d)
Logical High Level
VOH = VSS - 2V
Logical Low Level, Leakage
VOL = VOO
pA
1000·
1
pA
All Other Display, Alarm and Sleep Outputs
Logical High Level
VOH = VSS '- 2V
Logical Low Level, Leakage
VOL = VDO
pA
500
1
1·10
pA
functional description
A block diagram of the MM5316 digital alarm clock is
shown in Figure 1. The various display modes provided
by this clock are listed in Table I. The functions of the
setting controls are listed in Table II. Figure 2 is a
connection diagram. The following discussions are based
o,n FiflUre 1.
fluorescent tube displays, VSS or a display, brightness
control voltage is permanently connected to this pin.
Since the brightness of a fluorescent tube display is
dependent on the anode (segment) Voltage, applying a
variable voltage to pin 23 results in a display brightness
control. This control is shown in Figure 6.
50 or 60 Hz Input (pin 35): A shaping circuit (Figure 3)
is provided to square the 50 or 60 Hz input. This circuit
allows use of a filtered sinewave input. The circuit is a
Schmitt Trigger that is designed to provide about 6V of
hysteresis. A simple RC filter, such as shown in Figure 6,
should be used to remove possible line-voltage transients
that could either cause the clock to gain time or damage
t~e device. The shaper output drives a counter chain
which performs the timekeeping function.
12 or 24-Hour Select Input (pin 38): By leaving this pin
unconnected, the outputs for the most-significant
display digit (10's of hours) are programmed to provide
a 12-hour display format. An internal depletion pull
down device is again provided. Connecting this pin
to VSS programs the 24-hour display format. Segment connections for 10's of hours in 24-hour mode
are shown in Figure 5b.
Power Fail Indication: If the power to the integrated
circuit drops indicating a momentary ac power failure
and possible loss of clock, the power fail latch is set.
The power failure indication consists of a flashing of the
AM or PM indicator at a 1 Hz rate. A fast or slow set
input resets an internal power failure latch and returns
the display to normal. In the 24-hour format, the power
failure indication consists of flashing segments "c" and
"f" for times less than 10 hours, and of a flash ing
segment "c" for times equal to or greater than 10 hours
but less than 20 hours; and a flashing segment "g"for
times equal to or greater than 2.0 hours.
50 or 60 Hz Select Input (pin 36): A programmable
prescale counter divides the input line frequency by
~ither 50 or 60 to obtain a 1 Hz time base. This counter
is programmed to divide by 60 simply by leaving pin 36
unconnected; pull-down to VOO is provided by an
internal depletion device. Operation at 50 Hz is programmed by connecting pin 36 to VSS.
Display Mode Sel~ct Inputs (pins 30-32): In the
absence of any of these three inputs, the display drivers
present, time-of-day information to the appropriate
display digits. Internal pull-down depletion devices allow
use of simple SPST switches to select the display mode.
If more than one mode is selected, the priorities are as
noted in Table I. Alternate display modes are selected
by, applying· VSS to the appropriate pin. As shown in
Figure 1 the code converters receive time, seconds, alarm
and sleep information from appropriate points in the
clock circuitry. The display mode select inputs control
the gating of the desired data to the code converter
'inputs and ultimately (via output drivers) to the display
'
digits.
Alarm Operation and Output (pin 25): The alarm
comparator (Figure 1) senses coincidence between the
alarm counters (the alarm setting) and the time counters
(real time). The comparator output is used to set a latch
in the alarm and sleep circuits. The latch output enables
the alarm output driver (Figure 4), the MM5316 output
that is used to control the external alarm sound generator. The alarm latch remains set for 59 minutes, during
which the alarm will therefore sound if the latch output
is not temporarily inhibited by another latch set by the
snooze alarm input (pin 24) or reset by the alarm "OFF"
input (pin 26). If power fail occurs and power comes
back up, the alarm output will be in high impedance
state.
Time Setting Inputs (pins 33 and 34)': Both fast ana
slow setting inputs are provided. These inputs are
applied either singly or in combination to obtain the
control functions listed in Table II. Again, internal
pull-down depletion devices are provided; application of
VSS to these pins effects the control functions. Note
that the .control functions proper are dependent on the
selected display mode. For example, a hold-time control
function is obtained by selecting seconds display and
actuating the slow set input. As another example, the
clock time may be reset to 12:00:00 AM, in the 12-hour
format (00:00:00 in the 24-hour format). by selecting
seconds display and actuating both slow and fast set
inputs.
Snooze Alarm Input (pin 24): Momentarily connecting
pin 24 to VSS inhibits the alarm output for between 8
and 9 minutes, after which the alarm will again be
sounded. This input is pulled-down to VOO by an
internal depletion device. The snooze alarm feature may
be repeatedly used during the 59 minutes in which the
alarm latch remains set.
Alarm "OFF" Input (pin 26): Momentarily connecting
pin 26 to VSS resets the alarm latch and thereby silences
. the alarm. This input is also returned to VOO by an
internal depletion device. The momentary alarm "OFF"
input also readies the alarm latch for the next comparator output, and the alarm will automatically sound again
in 24 hours (or at a new alarm setting). If it is desired
to silence the alarm for a day or more, the alarm "OFF"
input should remain at VSS.
'
Blanking Control Input (pin 37): Connecting this
Sch!TIitt Trigger input to VOO places all display drivers
in a non-conducting, high-impedance state, thereby
inhibiting the display, (see Figures 3 and 4). Conversely,
VSS applied to this input enables the display.
Output Corr-rnon Source Connection (pin 23): All
disp'lay output drivers are open-drain devices with all
$Ol/rces common to pin 23 (Figure 4). When using
Sleep Timer and Output (pin 27): The sleep output
at pin 27 can be used to turn off a radio after a
1-11
functional description
(Continued)
and the sleep output current drive is removed, thereby
turning off the radio. The turn off may also be
manually controlled (at any time in the countdown) by
a momentary VSS connection to the snooze, input
(pin 24). The output circuitry is the same as the other
outputs (Figure 4).
desired time interval of up to 59 minutes. The time
interval is chosen by selecting the sleep display mode
(Table I) and setting the desired time interval (Table II).
This automatically results in a current-source output
via pin 27, which can be used to turn on a radio
(or other appliance). When the sleep counter, which
counts downwards, reaches 00 minutes, a latch is reset
Voo
50/60 HZ
B~N:~~I~~ >-"--1
50/60 Hz
JC)-"-. BLANKING
OUTPUT OR
INPUT
SIGNAL
VSS
FIGURE 3. 50/60 Hz or Blanking Input Shaping Circuit
*OUTPUT'COMMON SOURCE BUS (PIN 23)
il(OATA)~~
---i
BLANKING
(FROM
SHAPER)
OUTPUT
,(OPEN ORAIN)
VSS
*Alarm and sleep output sources are connected to VSS:
blanking is not applied to these outputs.
FIGURE 4. Output Circuit
PIN 39
1 Hz
PIN 40
PM
PIN 1
AM
PIN 1
AM
PIN 2
NC
b&c
(a) 12-Hour Display Format
(b) 24-Hour Display Format
FIGURE 5. Wiring 'Ten's-of-Hours Digit
1·12
PIN 40
PM
PIN 2
b&c
functional description
(Continued)
TABLE I. MM5316 Display Modes
*SELECTED
DISPLA Y MODE
DIGIT NO.1
DIGIT NO.2
DIGIT NO. 3
DIGIT NO.4
1D's of Hours & AM/PM
Hours
10's of Minutes
Minutes
Seconds Display
Blanked
Minutes
1D's of Seconds
Seconds
Alarm Display
1D's of Hours & AM/PM
Hours
1D's of Minutes
Minutes
Sleep Display
Blanked
Blanked
10's of Minutes
Minutes
Time Display
* If more than one display mode input is applied, the display priorities are in the order of Sleep (overrides all others), Alarm,
Seconds, Time (no other mode selected).
'
ill
TABLE II. MM5316 Setting Control, Functions
CONTROL
INPUT
SELECTED
DISPLAY MODE
CONTROL FUNCTION
*Time
Slow
Fast
Both
Minutes Advance at 2 Hz Rate
Minutes Advance at 60 Hz Rate
Minutes Advance at 60 Hz Rate
Alarm
Slow
Fast
Both
Both
Alarm
Alarm
Alarm
Alarm
Seconds
Slow
Fast
Both
Both
Input to Entire Time Counter is Inhibited (Hold)
Seconds and 1D's of Seconds Reset to Zero Without
a Carry to Minutes
Time Resets to 12:00:00 AM (12·hour format)
Time Resets to 00:00:00 (24·hour format)
Slow
Fast
Both
Substracts Count at 2 Hz
Substracts Count at 60 Hz
Substracts Count at 60 Hz
Sleep
Minutes Advance at 2 Hz Rate
Minutes Advance at 60 Hz Rate
Resets to 12:00 AM (12·hour format)
Resets to 00:00 (24·hour format)
*When setting time sleep minutes will decrement at rate of time counter, until the sleep counter reaches 00 minutes
(sleep counter will not recycle).
typical application
Figure 6 is a schematic diagram of a general purpose alarm clock using the MM5316 and a
3
1156~~~
fluor~scent
tube display.
BRIGHTNESS
CONTROL
...--.+_>---'...,..-.......,vss
IBV lOOk
[tl
Z1k
OUTPUT COMMON
SOURCE
~~--+---+----l50/60 Hz INPUT
ALARM
DRIVE
MMSJI6
Z1k
~--....-+-..-~--lVOD
r
I
I
I
L___
t,L. .o:,;~·rcz-.:;l;:.:O':;: S: . .OF-:H" OU_R_S- =.:;.: . ;. . ;-i-UN_IT-iH~O_UR;S+T- rI.;.O.S_O. .:F~M. :.IN_UT.:;.E. .:;S-T- i-;-;.UN_IT_M;-IN_U_TET-S+SL;~- ,~
IHOURS
I FOR
I Z4·HR
_ ___ J MODE
FIGURE 6. Schematic
1·13
SLEEP
DRIVE
Clocks
MM5370, MM5371 digital alarm clocks
general description
The MM5370 and MM5371 digital alarm clocks are
monolithic MOS integrated circuits utilizing P-channel
low-threshold, enhancement mode and ion-implanted
depletion mode devices. They provide all the logic
required to build several types of clocks an.d timers.
Three display modes (time, alarm and sleep) are provided to optimize circuit utility. The circuits interface
simply with 7-segment gas discharge displays. The
timekeeping function operates from either a 60 Hz
(MM5370) or 50 Hz (MM5371) input, and the display
format may be. ~jther12 hours (with leading-zero
blanking and AM/PM indication) or 24 hours. Outputs
consist of display drives, alarm enable and sleep (e.g.,
timed radio turn off). Power failure indication is
provided to inform the user that incorrect time is being
displayed. Setting the time cancels, this indication.
These clocks are packaged in 28-pin dual-in-Iine packages.
•
•
•
•
•
•
Single power supply
Low power dissipation
12 or 24-hour display format
•
Colon drive output
•
•
Presettable 59-minute sleep timer
9-minute snooze timer
applications
•
•
•
•
•
•
features
•
•
•
•
•
AM/PM drive output in 12-hour format
Leadi,ng-zero blanking in 12-hour format
24-hour alarm setting
All counters are resettable
Fast and slow set controls
Power fail indication
Blinking colon-12-hour or 24-hour mode
Blinking AM/PM indicators-12-hour only
Brightness control capability
Simple interface to gas discharge display
Alarm clocks
Desk clocks
Clock/radios
Automobile clocks
Industrial clocks
Appl iance timers
connection diagram
Dual-In-Line Package
28
SNOOZE
INPUT
ALARM
OUTPUT
HOURS
2
27 10 HO URS
ALARM
OFF INPUT
SLEEP
OUTPUT
I
10MINUTES
4
DIGIT
ANODE·DRIVE
OUTPUTS
MINUTES
vSS
VDD
Order Number MM5370N
or MM5371N
See Package 23
SLEEP
DISPLAY
ALARM
DISPLAY
MM5370
OR
MM5371
MULTIPLEXED
7·SEGMENT
OUTPUTS
RESET
SLOW
, SET
FAST
SET
LINE
FREQUENCY INPUT
COLON
OUTPUT
12124·HOUR
SELECT
AM/PM
OUTPUT
MULTIPLEX
TIMING INPUT
BRIGHTNESS
CONTROL INPUT
TOP VIEW
1·14
3:.
3:
absolute maximum ratings
(l'1
Voltage at Any Pin~~
Voltage at Any Disp ay Output Pin
Operating Temperature
Storage Temperature
Le~d Temperature (Soldering, 10 seconds)
W
VSS + 0.3V to VSS - 29V
VSS + 0.3V to VSS - 55V
-25°C to +70°C
-65°C to +150°C
300°C
.....
0
s:
s:
(l'1
electrical characteristics
PARAMETER
T A within operating range, VSS = OV, V DD = -21 V to -29V unless otherwise specified.
CONDITIONS
MIN
TYP
MAX
W
.....
....
UNITS
Power Supply Voltage
Fun·ctioning Clock
I
No Output Loads
Outputs Driving Display
Power Supply Current
-8.0
-25
-21
No Output Loads, (See "Power
-29
V
-29
V
5.0
mA
Supply" Section)
60 Hz (or 50 Hz) Input Frequency
MM5370
dc
30k
Hz
MM5371
dc
30k
Hz
60 Hz (or 50 Hz) Input Voltage
Logical High Level
VSS-1.0
VSS
VSS
V
Logical Low Level
VDD
VDD
VDD+1
V
VSS
VSS-4.0
V
VSS
VDD+2.0
V
Brightness Control Voltage
Logical High Level
VSS-2.0
VSS
Logical Low Level
VDD
'{DD
V
All Other Input Voltages
Logical High Level
Logical Low Level
Multiplex Frequency
Internal Depletion Load to VDD
VSS-1.0
VSS
VDD
VDD
V
Determined by Ext. RC
500
60k
Hz
Driven by Ext. Time Base
dc
60k
Hz
-8.0
V
.\-3.0
Power Failure Detect Voltage
(VDD Voltage)
Output Currents
VDD = -21 V to -29V, VSS = OV
Digit Anode Outputs
Logica High Level, ("ON")
VOH = VSS - 5V
Logical Low Level, ("OFF")
VOL = VSS - 45V
8.0
mA
40
/-LA
Segment Cathode Outputs
Logical High Level, ("OFF")
VOH=VSS-5V
Logical Low Level, ("ON ")
VOL = VSS - 45V
mA
2.0
10
/-LA
Alarm and Sleep Outputs
Logical High Level, ("ON")
VOH=VSS-2V
Logical Low Level, ("OFF")
VOL = VDD + 2V
1.5
mA
-10
functiona I description
functions of the clocks (proper counting, etc.) except
output drive capabilities. In order to ensure proper
output levels and breakdown voltages it is necessary to
provide supply voltages between -21V and -29V. At
some point between -7V and -3V, the power fail
latch becomes "set". All counters will then hold their
count at least 0.5V below this point. This ensures power
failure indication before any count is lost. For proper
power failure indication, power supply rise time should
not exceed 10 V/ms, since faster rise times may be
faster than propagation delays within the latch circuitry.
A block diagram of the MM5370 and MM5371 clocks is
shown in Figure 1. The various display modes provided
by these clocks are listed in Table I. The functions of the
controls are listed in Table II. A connection diagram for
these devices is shown on page 1. Unless indicated other·
wise, the following discussions are based on Figure ,.
Power Supply: Even though these clocks do not require
a regulated supply, and operate over a wide voltage
range, certain factors should be remembered. Power
supply voltages between -8V and ·-21V will provide all
1·15
/-LA
III
functional description
(Continued)
frequency of the multiplexing func_n. Each digit
anode is sequentially enabled for a time equal to the
period of one cycle ofthe multiplex oscillator frequency.
Line Frequency Input (pin 12): A shaping circuit is
provided to square the 60 Hz (MM5370) or 50 Hz
(MM5371) input., This circuit allows use of a sinewave
input. The Schmitt Trigger shaper (Figure 2) is designed
to provide approximately 6V of hysteresis. A simple RC
filter, such as shown in Figure 8,' should be used to
remove possible line·voltage transients that could cause
the clock to gain time o'r damage the device. The shaper
output drives a counter chain which performs the timekeeping function. A prescale counter divides the line
input frequency to obtain a 1 pps timebase.
When driving gas discharge displays which enclose more
than one digit in a common gas envelope, it is necessary
to either (1) inhibit the segment drive voltage(s) for a
short time' during inter-digit transitions, or (2) avoid
physically adjacent. inter-digit transitions. The MM5370
and MM5371 clocks utilize an interlaced output sequence
to eliminate the need for inter·digit blanking circuitry
and to prevent display arcing problems. The digit
sequence is: (1) digit no. 1 (ten's of hours), (2) digit
no. 3 (ten's of minutes), (3) blank for one digit time,
(4) digit no. 2 (unit hours), (5) digit no. 4 (unit minutes), (6) blank for one digit time, etc. The two blanking
intervals are provided to recharge level-translating
capacitors located in the display segment drive lines
(see Figure 8). Both segment data and digit enables are
blanked. Figure 3 is a ,timing diagram which illustrates
output timing.
Display Mode Select Inputs (pins 7 and 8): In the
absence of, either of these inputs, the display drivers
output time·of-day information to the display. Internal
,pull·down (to VDD) depletion loads allow use of simple
SPST switches for connecting these inputs to VSS,
thereby selecting alternate display modes. If more than
one mode is simultaneously selected, the priorities are
are noted in Table I. As shown in Figure 1 the multiplexed code converter receives time, alarm and sleep
information from appropriate points in the clock
circuitry. The display mode select inputs control the
gating of the desired data to the multiplexed code
converter inputs and ultimately (via output drivers)
to the display.
MUltiplex Timing Input (pin 14): The multiplex oscillator is shown in Figure 4. Adding an external resistor
and capacitor to this circuit via the mUltiplex timing
input produces a relaxation oscillator. The waveform at
this input is a quasi-sawtooth that is squared by the
shaping action of the Schmitt Trigger in Figure 4. Figure
5 provides guidelines for selecting the external components relative to the desired multiplex frequency.
Figure 6 illustrates a method of synchronizing or driving
the multiplex oscillator with an external timebase. The
external RC timing components may be omitted and
this input driven by an external timebase; the required
logic levels are the same as the 60 Hz or 50 Hz input.
Time Setting Inputs (pins 10 and 11): Both fast and
slow setting inputs are provided. These inputs are
applied either singly or In combination to obtain the
control functions listed in Table II. Again, internal
pull-down depletion loads are provided; application of
VSS to these pins effects the control functions. Note
that the control functions proper are determined by the
selected display mode. An optional hold-time control
function can be obtained as shown in Figure 8.
Output Circuits: All display output drivers are opendrain devices with sources common to VSS (pin 5),
see Figure 7. Figure 8 illustrates interfacing the clock'
outputs and a gas discharge display.
Reset Input (pin 9): Applying VSS tO,this input results
in resetting the timekeeping function' of the clock;
a pull-down depletion load is provided at this input I
Time is reset to 12:00 AM in the 12-hour format,
or 00:00 in the 24-hour format. See Table II.
Brightness Control Input (pin 15): Since display brightness is a function of cathode segment current, a capability of interrupting this current for a variable percentage of the digit interval results in a brightness
control. Connecting this Schmitt Trigger input (see
Figure 2) to VDD places all cathode segm'ent drive
voltages at the high level, thereby inhibiting the display.
Conversely, VSS applied to this input enables the
cathode segment drives. The Schmitt Trigger shaper
provides approximately 1V of hysteresis, which facilitates using a waveform such as a sawtooth with a variable
slope (or variabledc component) to effect the shaper
output duty cycle and, therefore, the display brightness.
The control waveform should, be derived from the multiplex frequency; a circuit is included in Figure 8.
12 or 24-Hour Select Input (pin 13): By lE)aving this
pin unconnected, the clock is programmed to provide
a 12-hour display format. This format provides for
zero-blanking the most significant display digit (ten's of
hours). An internal pull-down depletion load "is again
provided; connecting this pin to VSS' programs the
24-hour display fprmat. (See Figure 8).
Output Multiplexer Operation: Depending upon the
selected display mode (see Table I), outputs from the
appropriate internal counter are time division multiplexed to provide digit-sequential access to the data.
Thus, instead of requiring 28 leads to interconnect a
4-digit clock and its display (7 -segments per digit),
only 11 output leads are required. Note that the
MM5370 and MM5371 actually provide 13 outputs
(4-digit anode drive outputs plus 9 "segment" cathode
drive outputs). The two additional "segment" drives
are provided to accommodate displays which feature a
colon and/or AM/PM indication. (See sections on
pin 16 and pin 17). The multiplexed code converter and
output drivers are controlled by a multiplex oscillator.
The oscillator and external timing components'set the
Alarm Operation and Output (pin 2): An alarm com·
parator (see Figure 1) senses coincidence between the
alarm counters (the alarm setting) and the time counters
(real time). The comparator output isused to set a latch
in the alarm and sleep circuits. This latch enables the
alarm output driver (see Figure 7), the output of which
is used to control the external alarm sound generator.
The alarm latch remains set for 59 minutes, during
which the alarm will sound if the latch output is' not
1-16
functional description
(Continued)
sleep display mode (see Table I) and setting the desired
time interval (see Table II). This automatically results
in a current-source output via pin 4 which. can be used
to turn on a radio. When the sleep counter, which
counts downwards, reaches 00 minutes a latch is reset
and the sleep output drive current is removed, thereby
turning off the radio. This turn off also may be manually
controlled (at any time in the count-down) by a momentary VSS connection to the snooze input (pin 1). This
input is also returned to VDD by a depletion load. The
output circuitry is the same as the alarm output (see
Figure 7).
temporarily inhibited by another latch set by the snooze
input (pin 1) or reset by the alarm "OF F" input (pin 3).
Alarm time setting and resetting are outlined in Table II.
When initially powered, alarm is in "OFF" state.
Alarm "OFF" Input (pin 3): Momentarily connecting
this pin to VSS resets the alarm latch and thereby
silences the alarm. This input is also returned to VDD
by an internal depletion load. The momentary alarm
"OFF" input also readies the alarm latch for the next
alarm comparator output; the alarm will sound again in
24 hours (or at a new alarm setting). If it is desired to
silence the alarm for a day or more, the alarm input
should remain at VSS.
Snooze Timer Input (pin 1): Momentarily connecting
this pin to VSS inhibits the alarm output for between
8 and 9 minutes, after which the alarm will again be
sounded. This input is pulled to VDD by an internal
depletion load. The snooze feature may be repeatedly
used during the 59 minutes in which the alarm latch
remains set.
AM/PM Cathode Output (pin 16): Current with this
writing, gas-discharge clock displays are available with
two types of AM/PM indications, (1) AM and PM
indicators common to digits 3 and 4 respectively; and
(2) a PM only indication common to digit 1_ Figure 3
illustrates an AM/PM cathode drive output that is compatible with both display types. Note that this same
output also provides a non-blinking (steady) colon drive
common to digit two. Power failure is shown by turning
off this output at a 1 Hz rate.
Sleep Timer and Output (pin 4): The sleep output at
pin 4 can be used to turn off a radio (or other
appliance) after. a desired time interval of up to 59
minutes. The time interval is chosen by selecting the
Colon Cathode Output (pin 17): As an optional indication of clock operation, some users may prefer to
display a 1. Hz activity_As shown in Figure 3, a cathode
drive output is provided to facilitate a blinking colon.
.J
'
VSS
0--+
VDD 0--+
MULTIPLEX
TIMING O-----------i~
INPUT
12/2~EHL~~~
LINE
FREQUENCY
INPUT
MULTIPLEX
OSCILLATOR
0-------------------------------.
~DO:::RS
0----+1
)
DIGIT ANODE
DRIVE OUTPUTS
lD MINS
MINS
ALARM
OUTPUT ...- - - - - . . . . ,
ALARM 0-------,
AMIPM
OFF
COLON
INPUT
}
)
ALARM
DISPLAY
o---_________..:...______________--.J
SLEEP
DISPLAY
o--------------------...;.--------.....J
BRIGHTNESS
CONTROL O-----------i~
INPUT
SHAPING
CIRCUIT
FIGURE 1. MM5370 and MM5371 Digital Alarm Clock, Block Diagram
1-17
AUXILIARY
CATHODE DRIVE
OUTPUTS
MULTIPLEXED
7·SEGMENT
CATHODE DRIVE
OUTPUTS
III
...
,...
M
it)
functional description
(Continued)
~
:E
~
TABLE I. MM5370 and MM5371 Display Modes
M
it)
:E
:2
*SELECTED
DISPLA Y MODE
DIGIT NO.1
DIGIT NO.2
DIGIT NO.3
DIGIT NO.4
Time
Alarm
Sleep
10's of Hours
10's of Hours
Blanked**
Unit Hours
Unit Hours
Blanked
10's of Minutes
10's of Minutes
10's of Minutes
Unit Minutes
Unit Minutes
Unit Minutes
I
* If
more than one display mode input is :applied, the display priorities are in the order of Sleep (overrides all others), Alarrii,
Seconds, Time (no other mode selected).
"
* * F segment is lit in 12-hour disP"lay mode_ This may be eliminated by using circuit shown in Figure 9.
(~I
Table II. MM5370 and MM5371 Setting Control Functions
SELECTED
DISPLA Y MODE
CONTROL
INPUT
Time*
Slow
Fast
Both
Reset
Reset
Minutes Advance at 2 Hz Rate
Minutes Advance at 60 Hz Rate
Minutes Advance at60 Hz Rate
Time Resets to 12:00 AM (12-hour format)
Time Resets to 00:00 (24-hour format)
Alarm
Slow
Fast
Both
Both
Alarm
Alarm
Alarm
Alarm
Sleep
Slow
Fast
Both
Subtracts Count at 2 Hz Rate
Subtracts Count at 60 Hz Rate
Subtracts Count at 60 Hz Rate
CONTROL FUNCTION
Minutes Advance at 2 Hz Rate
Minutes Advance at 60 Hz Rate
Resets to 12:00 AM (12-hour format)
Resets to 00:00 (24-hour format)
*When setting time sleep minutes will decrement at rate of time counter, until the sleep counter reaches
00 minutes (sleep counter will not recycle).
vss
LINE
FREQUENCY
8RII~~~~E~~
SHAPEO LINE
0----4..........
X>-"'--1~ ~~E~~I~~CT~ESS
CONTROL
INPUT
CONTROL SIGNAL
VOD
FIGURE 2. 60 Hz (or 50 Hz) Input (or Brightness Control Input) Shaping Circuit
1-18
functional description
MULTIPLEX
TIMING
INPUT
s:
s:
U1
(Continued)
eN
-...J
o
I
I
n
II
DIGITNO.l
10'S OF HOURS
DIGIT NO. 3
10·SOFMINS.
I
l
r 11---
I
'~I----------------~'
I
II
~
~
I
I
I
I
r I11.-.__________--;
~
U~II~I~~~R~ I
n
I
~I--~I--------~
I
I
I
~I;I~ ~I~S~ I
I
~--------~
_ _ _1L
I
~--~--------------~
ANY
SEGMENT
AMII'M
CATHODES
I
NON·BlINKING .
COLON DRIVE
I
~l'HZBlINKING
COLON DRIVE
COLON
CATHOOES
COLON
I
: COLON :
L ___ ..1
FIGURE 3. Output Timing Diagram
VSS
ExTERNAL...Lc
TIMING
COMPONENTS
MULTIPLEX
TIMING INPUT
I
"'-0-...-1
OSCillATOR
OUTPUT
1.000.000
~
F
5 100.000 15
:c
~
~
~~
VOO
""
~
::;
Iil!:
voo=-a.DvR
VOO=-2IV
~I
10.000
r-
VOO =
-29V~
1000
VOO
~
;=
~
UlL
100
10 pF
1111
100 pF
11111
1000 pF
O.DI~F
O.I~F
CAPACIT ANCE C (WITH R=IDDk)
VSS
FIGURE 5. Multiplex Timing Component
Selection Guide (Typical Only)
FIGURE 4. Multiplex Oscillator Circuit
.._---+-----
VSS-....._ _........
Note 1: For synchronizing, free running period
should be set to run slightly longer than exter·
nal timebase over temperature.
Note 2: For driving, timing capacitor should
be deleted.
EXTERNAL
TIMEBASE
Voo-------4I.....- - -...- - - - - -
FIGURE 6. Synchronizing or Driving Multiplex Oscillator
1·19
functional description
(Continued)
Vss
"M"'«
n (DATA)
ALARM DR
SLEEP OUTPUT
VOO
(OPEN DRAIN)
TYPICAL DIGIT
DR SEGMENT
OUTPUT
FIGURE 7. Output Circuits
VSS
~
O.OT5~F
°t/
:~ 1,
5
VSS
VOD
55k
J.
en
T2k
TOOk
MUX TIMING
BRIGHTNESS CO NT.
~ VSS
~o-
FAST SET
~o-
RESET
~o-
ALARM DISPLAY
ALARM OFF
~o-
SNOOZE
60Hz
IN
,,+,~,~
!
" .r
TOOk
.
TOOk (X4)
~o-
~
} CONTROLS TO
ALARM ANDIDR
RADIO CIRCUITS
SLEEP
~o-
0-
.
ALARM
SLOW SET
~
MM53)0
M
10M
SLEEP DISPLAY
H
10H
T2/24 HOURS
10H
VDD
.
>
LINE FREn.
b
c
d
.
I
9
AMI
PM COLON
.
>
H~""
II
II
TOk
II
II
VSS
II
II
II
II
VSS= OV
VOO = -2TV TO -29V
II
II
>
.
b
c
d
.
I
9
AMI
PM COLON
TM(x9)
II
II
-T50
t.
-190
II
II
4.7k
II
II
0.05"F
T50V
(xg)
rv
. . . .... .. ..,. ., t~ IrF-":.. . ,~~ F-
...;
'-...; '-..;
..;
~-
F-
\
VSS
20k(x9)
FIGURE 8. Recommended Application
'·20
M
II
II
~
-40V t. -45V
TOM
H
GAS DISCHARGE
DISPLAY
-41I
2N5 08)
,. TN9T4
(xTO)
......
~I-
ZZk
820
Clocks
s:
s:
U'1
W
-..J
U'1
X
X
en
(t)
~.
(t)
en
MM5375XX series clocks
general description
MM5375XX series clock is a monolithic MOS integrated
circuit utilizing P-channel low threshold enhancementmode and ion-implanted depletion-mode devices_ It
provides all the logic required to give a 4 or 6-digit
12-hour or 24-hour display from a 50 or 60 Hz input_
An auxiliary counter allows various options. Available
options have been listed under features. Power failure
indication is provided to inform the user that incorrect
time is being displayed. Setting time cancels this indication. MM5375XX is available in a 24-lead dual-in-line
epoxy package.
•
•
•
•
•
•
•
•
application
•
•
•
•
•
•
•
features
•
•
•
•
•
III
Brightness control capability
No illegal time display at turn-on
Simple interface to gas discharge displays and LED's
Internal digit multiplex oscillator
Leading zero blanking
Activity indicator
4 to 6-digit operation
Available options t
Single power supply
Low power dissipation
All counters resettable
Fast and slow set controls
Power failure indication
Alarm clocks
Desk clocks
Automobile clocks
Industrial clocks
Date clocks
Minute timer clocks
Seconds timer clocks
available options table t
connection diagram
Dual-in-Line Package
~
r"~
10MIN
OIGIT
23
2-
10m} DIGIT
OUTPUTS
~lSEC
FEATURE
FUNCTION
Input Frequency
60 Hz
50 Hz
10HRS
~
r2!r1!-
VOO
.l.
~
AUX COUNTER DIS
..!.
~B
Alarm Signal
Tone
..!..
~C
Alarm Output
Modulated at 2 Hz
OUTPUTS.
J
1 HR ...;...
ALARM "OFF"
8TH SEG OUT
Time Display
12-Hour
24-Hour
BRIGHTNESS CON
Auxiliary Counter
Alarm Counter
Date Counter
MUXOSC
..!.
r!!-A
SLOW SET
.2..
~D
FASTSET
.!!!.
..!;.E
ALARM OUTPUT
60 Hz INPUT
.!!..
..!!.F
VSS
.2l..
..!!.G
Minute Timer
Second Timer
*
DC Level
Not Modu lated
SEGMENT
OUTPUTS
Alarm at Power Failure
"ON"
"OFF"
Segment Output Polarity
VSS for Display
VOD for Display
AM or PM Indication
"OFF" During Time Display
Displayed at All Times
8th Segment Blanked
Yes
During Alarm Display
No
*Tone is 1/6 multiplex frequency
TOPVIEW
Order Number MM5375XXN
See Package 22
1-21
AC
OPTION NAME
AO
AG
AE
AH
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
·········
· · · · · · · · ··
···· ···
·· ·· ··
· ··
··
· ··
··
·
·· ·· · · · · · ·
· ···
··
· ·
AA
AB
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
AI
AJ
N/A
N/A
N/A
N/A
(/)
CD
'':
absolute maximum ratings
en
Voltage at Any Pin
Voltage at Any Display Output Pin
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
CD
X
X
Ln
"
M
Ln
~
~
VSS + 0.3V to VSS - 30V
VSS + 0.3V to VSS - 55V
-25"C to +70°C
-65°C to +150°C
300°C
;
,-,
-
--
~.,
..
".
.'
electrical characteristics
T A within operating range, VSS
= OV, VDD = -21 V to -29V unless otherwise specified.
CONDITIONS
PARAMETER
Power Supply Voltage (VDD)
Power Supply Current
MIN
TVP
MAX
UNITS
Excluding Outputs
-S.O
-29
V
Outputs Driving Displays
-21
-29
V
Excluding Outputs
8.0
mA
60 Hz Input
Frequency
~ogical
High
Logical Low
Brightness Control Range
% of Digit Time
Multiplex Oscillator Frequency Input
Determined by External_ Rand C,
DC
50/60
30k
Hz
VSS-l.0
VSS
V
VDD
VDD
VSS
VDD+l.0
0
95
%
DC
30
kHz
V
(Figure 2)
Determined by External Rand C,
(Figure 2)
All Other Input Voltages
Logical High Level
VSS-l.0
VSS
Logical Low Level
VDD
VDD
Power Failure Detect Voltage
- Output Current
Digit Select Outputs
Logical High, Source
Logical Low, Leakage
-1.0
(VDD Voltage)
VDD
VSS
VOH
VOL
VSS
VDD+2.0
V
-8.0
V
V
= -21V to -29V
= OV
= VSS - 5V
= VSS - 45V
rnA
8.0
40
fJ.A
Segment Outputs
Logical High, Source
Logical Low, Leakage
= VSS- 5V
VOL = VSS - 45V
I
VOH
mA
2.0
10
fJ.A
Alarm Output
Logical High, Source
VOH
= VSS- 2V
1.5
mA
Logical Low, Sink
VOL
= VDD + 2V
1
fJ.A
functional description
A block diagram of the MM5375XX series of clocks
is shown in Figure 1. The display modes are listed in
Table I. The functions of the setting controls are listed
in Table II. The following discussions are based on
supply. Activating Fast Set (pin 10) causes the minutes
counter to advance at a 60 Hz rate, thus clocking the
hours counter at a rate of 1 hour per second. Slow Set
(pin 9) advances the minutes counter at a rate of 2 minutes per second. Activating either Fast Set or Slow Set
resets the seconds counter to zero. When Fast Set and
Slow Set are activated simultaneously, all counters are
reset to 12:00 p.m. and remain in that count until Slow
Set is deactivated. The 2 time setting inputs affect only
the counters that are displayed (either the timekeeping
counters or the alarm counters).
Figure 1.
60 Hz Input (Pin 11): A shaping circuit is provided to
square the 60 Hz input (50 Hz optional). This circuit
allows use of a filtered sinewave input. The circuit is a
Schmitt trigger that is designed to provide about 3V of
hysteresis. The shaper output drives a counter chain
which performs the timekeeping function.
8-Segment Test (Pin 24): For testing purposes, all
S-segment output lines may be activated by connecting
pin 24 (S10 digit output) to VSS.
Time Setting Inputs (Pins 9 and 10): The time setting
control functions are affected by the application of VSS
to these 2 pins, which are internally pulled to the power
1-22
;
functional description
(Continued)
Brightness Control (Pin 21): In LED applications,
brightness of the display may be varied by use of an
external time constant. This time constant is used in the
integrated circuit to control the pulse width or duty
cycle of the 6-digit enable outputs, (Figure 2). In gas
discharge applications, connect as shown in Figure 3.
the real time matches with the alarm time, the alarm
comparator sets the alarm latch. This latch activates the
alarm output (pin 8). The alarm will remain activated
until the alarm "OFF" input is connected to VSS
temporarily. This readies the alarm latch for next comparison. To deactivate the alarm output for more than
24 hours, the alarm "OFF" input is held at VSS for
that long. When the alarm output is active, connecting
pin 6 to VSS will interrupt the alarm signal for 6 to 8
minutes (snooze function).
Activity Indication (Pin 23): When all 6 digits are being·
used, it is not necessary to blink the colon to indicate
operation of the clock, because the seconds digits provide this information. When only 4 digits are in use, the
Sl digit (pin 23) may be connected to VSS. In this case,
the colon flashes at a 1 Hz rate.
Auxiliary Counter: Date Counter Optiori: In this option,
the auxiliary counter is programmed and used as a
month and day counter. The day counter counts up to
31 days and increments the month counter. The day
counter rolls over from 31 to 1. The month counter
counts up to 12 and rolls over to 1. The date counter
can be displayed by connecting date display (pin 6) to
VSS. The effects' of Fast and Slow Set controls are
shown in Table II. In this option, do not Lise the alarm
output (pin 8).
Multiplex Frequency (Pin 20): Applying an external
time constant to this pin allows the multiplex frequency
to be adjusted, (Figure 2).
Power Failure Indication: If the power to the integrated
circuit drops, indicating a momentary ac power failure
and possible loss of clock, the AM or PM and colon indicator will flash at a 2 Hz rate. If power drops completely,
the clock will reset itself (on resumption of power) to a
legal state, and the AM or PM and colon indicators will
flash at a 2 Hz rate. In addition to the flashing AM or
PM and colon indicator, if a power failure occurs when
alarm "OFF" (pin 7) is at VDD (logical "0"), the alarm
output will be activated (non-activated optional). A
logical "1" (VSS) on pin 7 will deactivate the alarm
signal.
Auxiliary Counter: Timer Option: In this option, the
auxiliary counter is programmed and used as a timer
counter. When the display pin 6 is connected to VSS,
the elapsed time from the previous setting is displayed.
The following sequence describes the use of the product
as a minute (or seconds) timer.
1. Hold display pin 6 at VSS.
2. Hold both Fast and Slow Set controls at VSS.
Note: This will reset the timer counter to 12:00 in
12-hour mode and 00:00 in 24-hour mode.
8-Segment Outputs (Pins 13-19 and 22): These outputs
contain multiplexed information for the display of
7-segment numerical readouts. The 8th segment is for
the activation of AM/PM and colon(s) as included in the
gas discharge displays for which these outputs are
designed.
3. Release both the Fast and Slow Set controls simultaneously.
Note: The timer counter starts counting minutes
(or seconds).
4. If it is required to monitor elapsed time continuously,
retain the display pin 6 at VSS. Otherwise, release
pin 6.
4-Digit Operation: Connect pin 23 to VSS.
Digit Enable Outputs (Pin 1-;-4, 23 and 24): These
outputs are used to select the 6 digits and are synchronized with the segment outputs. If pin 23 is
grounded, segment outputs will be blanked during the
scanning of the seconds digits.
5. Elapsed time can be displayed any time by holdin'g
pin 6 at VSS.
In this option, the clock can be used for up to 12 hours
(12 minutes in seconds timer) of elapsed time in 12-hour
mode and 24 hours (24 minutes in seconds timer) of
elapsed time in 24-hour mode. The effect of Fast and
Slow Set controls are listed in Table II. In these options,
do not use the alarm output (pin 8).
Auxiliary Counter: Alarm Counter Option: In this
option, the auxiliary counter is programmed and used as
an alarm counter. Pin 6 serves as both alarm display and
snooze input pin. Alarm counter is displayed when pin 6
is held at VSS. Alarm setting (Table II) is done using
alarm display, Fast Set (pin 10) and Slow Set (pin 9).
If the alarm "OFF" input (pin 7) is open and whenever
Accuracy of Elapsed Time: Elapsed time
time ± 1 minute (or second).
= displayed
TABLE I. Display Modes
SELECTED
DISPLA Y MODE
DIGIT NO.1
DIGIT NO.2
DIGIT NO.3
DIGIT NO.4
DIGIT NO.5
DIGIT NO.6
Units Seconds
Time Display
10's of Hours
Units Hours
10's of Minutes
Units Minutes
10's of Seconds
Alarm Display
10's of Hours
Units Hours
10's of Minutes
Units Minutes
<
><
I!)
SELECTED DISPLAY
MODE
~
I!)
Time Display
~
~
Alarm Display
Date Display
Minute Timer Display
Second Timer Display
MULTIPLEX
TIMING
INPUT
50/60 Hz
CONTROL
INPUT.
CONTROL FUNCTION
Slow
Minutes advance at 2.0 Hz rate and seconds are
held at a reset (00) condition
Fast
Minutes advance at 60 Hz rate and seconds are
held at a reset (00) condition
Both
Time resets to 12:00:00 p.m. (12-hour mode)
or 00:00:00 (24-hour mode)
Slow
Alarm minutes advance at a 2.0 Hz rate
Fast
Alarm minutes advance at a 60 Hz rate
Both
Alarm resets to 12:00 p.m. (12-hour mode)
or 00:00 (24-hour mode)
Slow
Date advances at a 2.0 Hz rate
Fast
Date advances at a 60 Hz rate
Both
Date
Slow
Mi,nutes (auxiiiary counter) advance at a
2_0 Hz rate
Fast
Minutes {auxiliary counter) 'advance at a
60 Hz rate
Both
Timer counter resets to 12 :00 (12-Hour mode)
or 00:00 (24-hour mode)
Slow
Seconds {auxiliary counted advance at a
2.0 Hz rate
Fast
Seconds (auxiliary
60 Hz rate
Both
Timer counter resets to 12:00 (12-hour mode)
or 00:00 (24-hour mode)
count~r
resets to 12 :00
cou~ter)
advance at a
MULTIPLEX
OSCILLATOR
SELECT
50/60 H,
INPUT
SLOW SET
0---+
FAST SET
0---+
ALARM
OUTPUT
ALARM OFF
INPUT
MUL TIPLEXEO
COOE
CONVERTER
AND
OUTPUT
ORIVERS
'j
e
AUXILIARY
COUNTER
OISPLAY
:
8th
BRIGHTNESS
CONTROL
INPUT
O~------------------~~I
PULSEWIDTH
MOOULATOR CIRCUIT
FIGURE 1. Block Diagram
1-24
MULTIPLEXED
7SEGMENT
CATHODE
ORIVE OUTPUTS
functional description
(Continued)
VOO
,.
BRIGHTNESS CONTROL
INPUT OR MU. TlPLEX
FREQUENCY INPUT
j
SOk
T
VSS
FIGURE 2
r!-
20k
~
150k
I
°r~
III
200
VSS
....
VSS
-Q"
U"
-
"'V'
"-"
"'V'
"
VD a ....
50/60 Hz
IN~
lOOk
I
I?
10k
RESET
FAST SET
~
ALARM SET (AND DROWSE)
U'
ALARM OFF
n
T
SLOW SET
U'
4
o.OI
BRIGHTNESS
MUX. TIMING
ALARM
OUT
VOO
MMS37SAA
VOO
10H
.
LINE
FREIl.
I.
AMIPM
COLON
b
c
d
e
f
9
II
II
lOOk (X6)
H
10M
, ,I
IDS
M
GAS DISCHARGE DISPLAY
c
b
d
e
AM/PM
9 COLON
f
1.0MX7
II
II
II
l r
,
VSS
=
II
II
II
II
OV
VOO = -21V to -29V
II
II
II
II
0.05"F
@150V(X8)
-40VT 0
-50 V
II
II
~~ ~
20k (XB)
..
..
1.0"F/150V
VSS
0---1
1
I
FIGURE 3. Typical Application
LINE
FREIlUENCY
INPUT
SHAPED
LINE
FREIlUENCY
FIGURE 4. 50 or 60 Hz Shaping Circuit
1·25
f-
,~ ~ r ,.. ., ~
f-
10M
~
..
lN914(XB)
-,o"T
Note . LED interface - common cathode LED's (NSN74R) can
be in terfaced with MM5375AB by using two OM75491 segment
drive rs, one OM75492 digit driver, eight 150.11, 1.0W resistors
and a 10V power supply.
~
,.
33k
...AAA
I'"
,,,.. ~
4.7k
820
...r.
150VTO
-190V
functional description
(Continued)
MULTIPLEX
TIMING INPUT
BRIGHTNESS
CONTROL
INPUT
DIGIT NO.6
UNIT SECS.
DIGIT NO.4
UNIT MINS.
DIGIT NO.2
UNIT HOURS
1-+-+--+------1
DIGIT NO.5
10'S OF SECS.
1-+-+--+---------....
DIGIT NO.3
10'S OF MINS.
DIGIT NO.1
10'S OF HOURS
1-+--+-_-+__________________....
ANY
SEGMENT
8TH
SEGMENT
1-+-+--+--,
FIGURE 5. Output Timing Diagram
'·26
Clocks
MM5376XX series clocks
general description
MM5376XX series clock is a monolithic MOS integrated
circuit utilizing P-channel, low threshold, enhancementmode and ion-implanted depletion-mode devices_ It
provides all the logic required to give a 4 or 6-digit
12-hour or 24-hour display from a 50 or 60 Hz input.
An auxiliary counter allows various options. Available
options have been listed under features. Power failure
indication is provided to inform the user that incorrect
time is being displayed. Setting time cancels this indication. MM5376XX is available in a 24-lead dual-in-line
epoxy package.
•
•
•
•
•
•
•
•
features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
application
50 or 60 Hz operation
Single power supply
Low power dissipation
All counters resettable
Fast and slow set controls
Power failure indication
connection diagram
r"~
28
} DIGIT
~10SEC
27
r
3
BIRGHTNESS CON
..!.
~
MUXOSC
~B
~C
ALARM OUT....2.
.!2.A
...!.!!.
,!!oo
SLOW SET
2!.. NC
FAST SET..!!
50/60 Hz IN....!!.
.!!..E
50/60 HZSEL....!l
2!..F
VSS..!!
~G
Alarm Counter
Date Counter
~
ALARM "OFF"-1.
12-Hour
24-Hour
Auxiliary Counter
10 HRS...l
VOO
50 Hz
Time Display
~NC
AUX COUNTER OISP...!..
60 Hz
OUTPUTS
1SEC
~8THSEG OUT
~
NC ...;;.
FUNCTION
FEATURE
Input Frequency
10MIN..l
1 HR
Alarm clocks
Desk clocks"
Automobile clocks
Industrial clocks
Two time zone clocks
Date clocks
Minute timer clocks
S~conds time r clocks
available options tablet
Dual-In-Line Package
DIGIT
OUTPUTS
Brightness control capability
No illegal time display at turn-on
Simple interface to gas discharge displays and LED's
Internal digit multiplex oscillator
Leading zero blanking
Activity indicator
4 to 6-digit operation
Available options t
Minute Timer
Second Timer
Alarm Signal
Tone*
DC Level
Alarm Output
Modulated at 2 Hz
Not Modulated
SEGMENT
OUTPUTS
Alarm at Power Failure
"ON"
"OFF"
Segment Output Polarity
VSS for Display
VDD for Display
AM or PM Indication
"OFF" During
Time Display
Displayed at
TOP VIEW
Note 1: 50 Hz input at pin 12 connect pin 13 to V DO.
Note 2: 60 Hz input at pin 12 connect pin 13 to V 55.
All Times
8th Segment 81anked
Yes
During Alarm Display
No
*Tone is '16 multiplex frequency
Order Number MM5376XXN
See Package 23
1-27
OPTION NAME
AA
AB
AD
AE
AG
AH
·· ·· ·· ·· ·· ··
······
·· ··
··
·· ·
·· ·
·· ·
·· ·· · ." · ·
· ··
·· ·
N/A
N/A
N/A
N/A
N/A
N/A
N/A N/A
N/A" N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
II
absolute maximum ratings
Voltage at Any Pin
Voltage at Any Display Output Pin
Operating Temperature
Storage Temperature
Lead Tenipe~ature (Soldering, 10 seconds)
VSS + 0.3V to VSS - 30V
VSS + 0.3V to VSS - 55V
-25°C to +70°C
-65°C to +150°C
300°C
electrical characteristics
T A within operating range, VSS
= OV,
VDD
= -BV to -29V unless otherwise specified.
CONOITIONS
PARAMETER
Power Supply Current
MIN
TYP
MAX
8.0
mA
DC
60/50
10k
Hz
Excluding Outputs
50/60 Hz Input Frequency
Logic High
VSS-l.0
Logic Low
VOD
Brightness Control Range % of
Determined by External Rand C
Digit Time
(Figure 2)
Multiplex Oscillator Frequency Input
Determined by External Rand C
UNITS
VSS
V
VSS-15.0
V
0
95
%
OC
10
kHz
(Figure 2)
All Other Input Voltages
Logic High Level
VSS-l.0
Logic Low Level
-1.0
Power Failure Detect Voltage
(VOD Voltage)
Output Current Levels
VDD = -21V to -29V
Digit Select Outputs
Vss
Vss
V
VOD
VSS-15.0
V
-8.0
V
VSS = OV
Logic High, Source
VOH = VSS - 5.0V
Logic Low, Leakage
VOL
= VSS -
mA
8.0
40
45V
J.lA
Segment Outputs
Logic High, Source
VOH = VSS - 5.0V
Logic Low, Leakage
VOL = VSS - 45V
mA
2.0
10
J.lA
Alarm Output
Logic High, Source
VOH = VSS - 2.0V
1.5
mA
Logic Low, Sink
VOL
= VOD + 2.0V
1.0
J.lA
functional description
A block diagram of the MM5376XX series of alarm
clocks is shown in Figure 1. The two display modes are
listed in Table I. The functions of the setting controls
are listed in Table II. The following discussions are
based on Figure 1.
allows use of a filtered sinewave input. The circuit is a
Schmitt trigger that is designed to provide about 3.0V
of hysteresis. The shaper output drives a counter chain
which performs the timekeeping function.
50 or 60 Hz Select (Pin 13): 50 or 60 Hz input at pin
12 is selected by pin 13. 50 Hz operation is selected by
connecting pin 13 to VOD (pin 6) and 60 Hz operation
is selected by connecting pin 13 to VSS (pin 14).
50 or 60 Hz Input (Pin 12): A shaping circuit is pro:
vided to square the 50 or 60 Hz input. This circuit
1-28
functional description
(Continued)
Time Setting Inputs (Pins 10 and 11): The time setting
control functions are affected by the application of VSS
to these two pins, which are internally pulled to the
power supply. Activating Fast Set (pin 11) causes the
minutes counter to advance at 50 or 60 Hz rate, thus
clocking the hours counter at a rate of one hour per
second. Slow Set (pin 10) advances the minutes counter
at a rate of 2 minutes per second. Activating either Fast
Set or Slow Set resets the seconds counter to zero. When
Fast Set and Slow Set are activated simultaneously, all
counters are reset to 12:00 p.m. and remain in that
count until Slow Set is deactivated. The two time setting
inputs affect only the counters that are displayed (either
the timekeeping counters or the alarm counters).
completely, the clock will reset itself (on resumption of
power) to a legal state, and the AM or PM and colon
indicators will flash at a 2.0 Hz rate. In addition to the
flashing AM or PM and colon indicator, if a power
failure occurs when alarm "OFF" (pin 8) is at VDD
(logic "0"), the alarm output will be activated (nonactivated optional). A logic "1" (VSS) on pin 8 will
deactivate the alarm signal.
8-Segment Outputs (Pins 15-17, 19-22 and 26): These
outputs contain multiplexed information for the display
of 7-segment numerical readouts. The eighth segment
is for the activation of AM/PM and colon(s) as included
in the gas discharge displays for which these outputs are
designed.
8- Segment Test (Pin 28): For testing purposes, all 8segment output lines may be activated by connecting
pin 24 (S10 digit output) to VSS.
4-Digit Operation: Connect pin 23 to VSS.
Digit Enable Outputs (Pins 1-3, 5, 27 and 28): These
outputs are used to select the 6 digits and are synchronized with the segment outputs. If pin 27 is grounded,
segment outputs will be blanked during the scanning of
the seconds digits.
Brightness Control (Pin 24): In LED applications,
brightness of the display may be varied by use of an
external time constant. This time constant is used in the
integrated circuit to control the pulse width or duty
cycle of the 6-digit enable outputs (Figure 2). In
gas discharge applications, connect as shown in Figure 3.
Auxiliary Counter, Alarm Counter Option: In this
option, the auxiliary counter is programmed and used as
an alarm counter. Pin 7 serves as both alarm display and
snooze input pin. Alarm counter is displayed when
pin 7 is held at VSS. Alarm setting (Table II) is
done using Alarm Display, Fast Set (pin 11) and Slow
Set (pin 10). If the alarm "OFF" input (pin 8) is open
and whenever the real time matches with the alarm time,
the alarm comparator sets the alarm latch. This latch
activates the alarm output (pin 9). The alarm will
remain activated until the alarm "OF F" input is connected to VSS temporarily. This readies the alarm
latch for next comparison. To deactivate the alarm
output for more than 24 hours, the alarm "OFF" input
is held at VSS for that long. When the alarm output is
active, connecting pin 7 to VSS will interrupt the alarm
signal for 6 to 8 minutes (snooze function).
Activity Indication (Pin 27): When all 6 digits are being
used, it is not necessary to blink the colon to indicate
operation of the clock, because the seconds digits
provide this information. When only 4 digits are in use,
the Sl digit (pin 27) may be connected to VSS. In this
case, the colon flashes at a 1.0 Hz rate.
Multiplex Frequency (Pin 23): Applying an external
time constant to this pin allows the multiplex frequency
to be adjusted. See Figure 2.
Power Failure Indication: If the power to the integrated
circuit drops, indicating a momentary -ac power failure
and possible loss of clock, the AM or PM and colon
indicator will flash at a 2.0 Hz rate. If power drops
TABLE I. Display Modes
SELECTED
DISPLAY MODE
DIGIT NO.1
DIGIT NO.2
DIGIT NO.3
DIGIT NO.4
DIGIT NO.5
DIGIT NO.6
Time Display
10's of Hours
Units Hours
10's of Minutes
Units Minutes
1O's of Seconds
Units Seconds
Alarm Display
1O's of Hours
Units Hours
1O's of Minutes
Units Minutes
Date Display
Month
Month
Date
Date
Minute Timer Display
10's of Hours
Units Hours
10's of Minutes
Units Minutes
q;,
q;,
Second Timer Display
10's of Minutes
Units Minutes
10's of Seconds
Units Seconds
rt>
1-29
q;,
q;,
01
functional description
(Continued)
TABLE II. Setting Control Functions
SELECTED DISPLAY
MODE
Time Display
Alarm Display
Date Display
Minute Timer Display
CONTROL
INPUT
CONTROL FUNCTION
Slow
Minutes advance at' 2.0 Hz rate and seconds are
held at a reset tOO) condition
Fast
Minutes advance at 60 Hz rate and seconds are
held at a reset tOO) condition
Both
Time resets to 12:00:00 p.m. (12·hour mode)
or 00:00:00 (24-hour mode)
Slow
Alarm minutes advance at a 2.0 Hz rate
Fast
Alarm minutes advance at a 60 Hz rate
Both
Alarm resets to 12:00 p.m. (12-hour mode)
or 00:00 (24-hour mode)
Slow
Date advances at a 2.0 Hz rate
Fast
Date advances at a 60 Hz rate
Both
Date counter resets to 12:00
Slow
Minutes (auxiliary counter) advance at a
2.0 Hz rate
Fast
I
Second Timer Display
Minutes (auxiliary counter) advance at' a
60 Hz rate
Both
Timer counter resets to 12:00 (12-Hour mode)
or 00:00 (24-hour mode)
Slow
Seconds (auxiliary counter) advance at a
2.0 Hz rate
Fast
Seconds (auxiliary counter) advance at a
60 Hz rate
Both
Timer counter resets to 12:00 (12-hour mode)
or 00:00 (24-hour mode)
VSS
0-+
VOD
0-+
MULTIPLEX
TIMING
INPUT
50/60H.
SELECT
MULTIPLEX
OSCILLATOR
50/60 H.
INPUT
SLOW SET
0---+
10',HRS
~::MINS
FAST SET
0---+
MINS.
ALARM
OUTPUT
MULTIPLEXED
CODE
CONVERTER
AND
OUTPUT
DRIVERS
SECONDS
'j
,
:
AUXILIARY
COUNTER
DISPLAY
8th
0---------------------.,
~~G~~E
ORIVE
10', SECONOS OUTPUTS
ALARM OFF
INPUT
BRIGHTNESS
CONTROL
INPUT
J
PULSEWIDTH
MODULATOR CIRCUIT
FIGURE 1. Block Diagram
1-30
MULTIPLEXED
7SEGMENT
CATHODE
ORIVE OUTPUTS
functiona I descri ption
s:
s:
0'1
(Continued)
W
-...J
VOO
BRIGHTNESS CONTROL
INPUT OR MULTIPLEX
FREOUENCY INPUT
en
j
X
X
SOk
en
(l)
..,
(ii'
T
(/)
VSS
FIGURE 2
1-
20k
lS0k
[~
°r~
II
200
VSS
,,
-
VSS
BRIGHTNESS
MUX. TIMING
I
V'
SLOW SET
"1.J'
V"
FAST SET
"'V'
V'
ALARM SET (AND DROWSE)
"'V"
V"
ALARM OFF
"'V'
ALARM
OUT
f?
10k
RESET
VOO
MMS316AA
,
0,
-,
lN914
o.OlT~
50/60 Hz IN'
lOOk
SO/60 H
z'"
VOO
10H
.
I.
AM/PM
COLON
LINE
FREO.
b
c
d
e
f
g
H
10M
M
IDS
, ,I
GAS DISCHARGE DISPLAY
c
b
e
d
AM/PM
g COLON
f
lOOk (X6)
1.0MX1
II
II
SELEC T'
I
II
J
II
II
II
II
II
II
VSS = OV
VOO = -21V to -29V
II
II
II
II
J L
II
O.OS~F
U
@lS0V(X8)
-40VT 0
-50 V
., ,.
f-
., ,.
~ ,.
f-
,
., , ., ., ~
F-
10M
.,~
lN914 (X8)
20k (X8)
...
Note . LEO interface - common cathode LEO's (NSN74R) can
be in terfaced with MM5376AB by using two OM75491 segment
drive rs, one OM75492 digit driver, eight 150.11., 1.0W resistors
and a 10V power supply.
1.0~F/lS0V
VSS
0----1
1
I
FIGURE 3. Typical Application
LINE
FREQUENCY
INPUT
SHAPED
LINE
FREQUENCY
FIGURE 4. 50 or 60 Hz Shaping Circuit
1-31
33k
~-lS0VTO
4.1k
r
' ' ' '1
820
-190V
functional description
(Continued)
MULTIPLEX
TIMING INPUT
BRIGHTNESS
CONTROL
INPUT
DIGIT NO.6
UNIT SECS.
DIGIT NO.4
UNIT MINS.
f--+-+--+.....
OIGIT NO.2
UNIT HOURS I--+-+---+-----~
OIGIT NO.5
IO'S OF SECS.
1--+-+-_-+-_________..1
DIGIT NO.3
IO'S OF MINS.
1--+-+-_+_____________......
DIGIT NO. I
IO'SOF HOURS
1-+-+-_+_________________---1
ANY
SEGMENT
8TH
SEGMENT
1-+--+---+--....
FIGURE 5. Output Timing Diagram
1-32
Clocks
MM5377 auto clock
general description
The MM5377 Auto Clock is a monolithic MOS integrated
circuit utilizing P-channel low-threshold, enhancement
mode and ion-implanted depletion mode devices. The
circuit interface~ directly with liquid crystal 4 digit
displays and fluorescent tubes. The display format is
12 hours with leading-zero blanking and colon indication.
A voltage sensitive output is provided that drives an
energy storage network wh ich performs as a voltage
doubler/regulator. The circuit uses a 2 MHz crystal
oscillator as the reference time base and is packaged in
a 40 lead dual-in-line package.
II
II
II
II
II
II
II
II
Leading zero blanking
Hours and minutes set controls
Crystal tuner output
Voltage doubler control output
Elimination of illegal time display at turn-on
Direct interface to liquid crystal display
Direct interface to fluorescent tubes
Low standby power dissipation
applications
features
II
II
II
II
Crystal controlled oscillator (2.097152 MHz)
12 hour display format
Colon output
II
II
II
Automobile clocks
Desk clocks
Portable clocks
High accuracy clocks
block and connection diagrams
Dual-ln.Line Package
Fosi;l2
40
LX BACKPLANE
39
10 HOURS
38
HOURS AI
31
HOURS FI
36
HOURS GI
35
HOURS EI
34
HOURS 01
33
HOURSCI
32
HOURS Bl
31
COLON
30
10 MINUTES A2
29
10 MINUTES F2
28
10 MINUTES G2
10 MINUTES E2
26
10 MINUTES 02
IGNITION 0 - - . IGNITION
AMP.
25
10 MINUTES C2
24
10MINUTES82
23
MINUTES F3
MINUTES G3
MINUTESE3
22
20
il
TOPVIEW
Vsso-Voo 0 - - -
VGOO--
HOURS
SEGMENTS
10'SMIN
SEGMENTS
MINUTES
SEGMENTS
Order Number 5377N
See Package 24
FIGURE 2.
FIGURE 1.
1-33
IGNITION INPUT
SET HOURS
Voo
SET MINUTES
MOOE SELECT
TIME TEST INPUT
OSC 1
OSC2
Fas<;/2
VOLTAGE CONVERTER
CONTROL
Voo
CONVERTER ORIVE
NC
Vss
VOL TAGE MONITOR
NC
MINUTES 03
MINUTES C3
MINUTES B3
MINUTES A3
II
absolute maximum ratings
Voltage at V GG Pin
Voltage at Any Pin
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Vss + 0.3V to Vss - 30V
Vss + 0.3V to Vss - 24V
-40°C to +85°C
-65°C to +150°C
300°C
electrical characteristics
TA within operating range, Vss = +9V to +20V, Voo = OV, VGG = -1OV, unless otherwise specified.
PARAMETER
MIN
CONDITIONS
Power Supply Voltage (V ss )
O~tPuts
and OSC Operational
8
Power Supply Voltage (V GG )
Outputs and OSC Operational
-6
TYP
18
-8
MAX
UNITS
20
V
-10
V
I
Power Supply Voltage (V ss )
No Loss of Time Memory
5
18
20
V
Power Supply Voltage (V ss )
Ignition Open
7
9
20
V
Power Supply Voltage (V GG )
Ignition Open
Power Supply Current (Iss)
Ignition Open
Input Frequency
OSC 1
Frequency of Outputs
\
V
0
1
DC
Liquid Crystal Display
fiN = 2.097152 MHz
3
5
2.097152
2.1
mA
MHz
Hz
32
OUTPUT CURRENTS
Display Segments
Source Current
Sink Current
Vss = +18V
V OUT = Vss - lV
V OUT = Vss -17V
200
200
/lA
/lA
Display Colon and 10's Hours
Source Current
Sink Current
Vss = +18V
V OUT = Vss -1V
V OUT = Vss -17V
400
400
/lA
/lA
Display Backplane
Source Current
Sink Current
Vss = +18V
V OUT = Vss - 1.2V
V OUT = Vss - 16.8V
4
4
mA
mA
Convertor Drive Output
Source Current
Sink Current
Vss = +10V
V OUT = Vss - 6V
V OUT = Vss - 8V
500
100
/lA
/lA
FOSC/2 Source Current
. Vss = +18V
V OUT = Vss - 2V
200
/lA
Voltage Monitor
Source Current
Trip Point
Zener = 16V
17
1-34
100
18
19
/lA
V
functional description
Ignition Input (Pin 40)
A block diagram of the MM5377 auto clock is shown in
Figure 1. A connection diagram is shown in Figure 2.
Unless otherwise indicated, the following discussions are
based on Figure 1.
The Ignition Input enables setting of the clock using the
set hour or set minute inputs, and enables the drive to
the display and the voltage doubler. When the input is
at a voltage greater than 50 percent of the Vss supply
the time set, display and voltage doubler are enabled.
When the input is open circuited or at V DD, the time set,
display and voltage doubler are disabled. The display
outputs and backplane drive are held to V DD when the
display is disabled. This input does not affect the accuracy of the time keeping logic in any manner.
Oscillator 1 (Pin 34) and Oscillator 2 (Pin 33)
A quartz crystal, resonant at 2.019752 MHz, two
capacitors and one resistor, together with the internal
MOS circuits form a crystal controlled oscillator as
shown in Figure 3. Varying one of the capacitors
allows precise frequency setting. For test purposes, OSC
1 is the input and OSC 2 is the output of an inverting
amplifier.
Voltage Converter Control (Pin 31)
The Voltage Converter Control input enables the voltage
doubler to operate regardless of the state of the ignition
input when it is at V DD' When the input is open
circuited or at Vss , the voltage doubler is controlled by
the ignition input.
FOSC/2 (Pin 32)
FOSC/2 is the output of the first divide-by-two stage.
This output allows frequency tuning of the crystal
oscillator without adding any additional capacitance to
the oscillator circuit_
Output Circuits
Set Hours (Pin 39) and Set Minutes (Pin 37)
The Converter Drive output and all display outputs are
push-pull stages with. sources common to V 55 (Pill 27)
and drains common to V DD (Pin 38) as shown in
Figure 5. FOSC/2 output is a open-drain stage with the
source common to Vssas shown in Figure 6. Figure 8
illustrates the interfacing between the clock and a liquid
crystal display and the clock and fluorescent tubes.
When driving fluorescent tubes, V GG can be connected
to V DD .
Set Hours will advance the. hours at a 1 Hz rate when
the input is held at V DD . While setting hours, the minute's
counter may also advance the hours count. Set Minutes
will advance the minutes at a 1 Hz rate, hold the internal
seconds counter reset and cause the colon to blink at
1 Hz rate when the input is held at V DD. Depressing
both switches at the same time shall cause the clock to
initiate a hold and not advance until the switches are
released.
Converter Drive (Pin 29) and Voltage Monitor (Pin 26)
Mode .Select (Pin 36)
Mode Select determines the shape of the output wave.
form as shown in Figure 4. With the input open or at
V D D, the output wave form is a 32 Hz square wave.
Segments to be energized have the 32 Hz square wave
0
180 out of phase with respect to the backplane 32 Hz
square wave. Segments not to be energized have their
outputs in phase with the backplane, output. With the
mode select input at Vss , the outputs are at a constant
level. Segments to be energized are at V ss, and segments
not to be energized are at V DD •
The Converter Drive output oscillates at 65.636 kHz.
The duty cycle of the wave depends on the state of the
Voltage Monitor input pin as shown in Figure 7. With
Vss on the input pin, the duty cycle of the output wave
is 50%, which enables the voltage doubler. Once the
input pin is a few volts above the zener breakdown
voltage of its' zener diode (Figure 8), the duty cycle of
the output is 0% or held at V DD, which disables the
voltage doubler. Therefore, the duty cycle of the output
wave form varies from 50% to 0% as the voltage at the
voltage monitor input pin varies. Therefore, the voltage
to the chip is regulated about 2V above the zener breakdown voltage.
Time Test'lnput (Pin 35)
Time Test Input causes the circuit to cycle through a
12 hour period using an internal clock of 65536 Hz
instead of 1 Hz to increment the seconds counter when
the input is at Vss. The input also causes the mode of
the outputs to change from 32 Hz square wave to
constant levels.
Colon Output (Pin 10)
The colon output indicates the clock is counting by
blinking at a 1/2 Hz rate. When setting minutes, the
colon blinks at 1 Hz rate.
1-35
(I
,....
,....
M
LC')
typical applications
~
~
v,s
MOS CIRCUIT
TO
r-4~"'-' DlVIOER
CIRCUITS
FIGURE 3. Crystal Oscillator
LX BACKPLANE V,,(32 Hz SQUAREWAVEI
MODESELECT
V,,-------------------~------------------
ON SEGMENT
OFF SEGMENT
V"
FIGURE 4. Output Timing DiagraM
Q (DATAl
---il >0----.-----1------.., I
(PUSH·PULLI
TYPICAL
SEGMENT
FIGURE 5. Push·Pull Output Circuit
QWATAI-FtVSS
'"
.
(DPEN DRAINI
" ~"'
Fosc/2
FIGURE 6. Open Drain Output Circuit
'·36
typical applications (con't)
VOLTAGE
MONITOR
IGNITION
INPUT
VSS~
--.A-
voo ---=-=LO:.:G:.:IC..:.ON::..:E~_--=::,_:--_ _ _
VSS~
Voo
CONVERTER DRIVE
OUTPUT (65 kHll
FIGURE 7. Operation of Converter Drive
II
LlOUID CRYSTAL DISPLAY
OR
FLUORESCENT TUBES
MM5317
~
~URS
2mH
BATTERY
_+_-I
O-:+....J-y--'rY""'-....
1---41---+111--"
27V
GNDo-----~~-4~----~-----~~--~----~
IGNITION
o----------------------"IMr---------------...I
lOOk
Sl OPEN LC DISPLAY
Sl CLOSED FT DISPLAY
FIGURE 8. Typical Application
'-37
Clocks
MM5378, MM5379 auto clocks
general description
The MM5378 and the MM5379 auto clocks are
monolithic MOS integrated circuits utilizing P-channel
low-threshold, enhancement mode and ion-implanted
depletion mode devices_ The MM5378 circuit interfaces
with vacuum fluorescent 4-digit displays. The MM5379
circuit interfaces with gas-discharge 4-digit displays.
The display format is 12 hours with leading-zero
blanking and colon indication. The time keeping
function operates from a 2 MHz crystal controlled or
externally appl ied source.
• Leading-zero blanking
• Hours and minutes set controls,
• Brightness control capability
• No illegal time display at turn-on
• Simple interface to vacuum fluorescent and gas
discharge displays
'. Low standby power dissipation
applications
features
• Automobile clocks
• Desk clocks
• Portable clocks
• High accuracy clocks
• Crystal-controlled oscillator (2.097152 MHz)
• 12-hour display format
• Blinking colon output
connection diagram
Dual-In-Line Package
b, 1
MULTIPLEXEO
SEGMENT
OUTPUTS {
2
:: : } MULTIPLEXE'D
C
•
3
16 f
OSC 2
~~;~~~~
15
COLON
9
MM5378 OR
MM5379
14
SWITCH IN
13 VDD
OSC 1
BRIGHTNESS' 7
INPUT
12 H1 } DIGIT ENABLE
11
DIGIT ENABLE {M1 B
OUTPUTS
M10 9
10
H10
OUTPUTS
VSS
TOPVIEW
Order'Number MM5378N
or MM5379N
See Package 20
block diagram
M1
M1D
H1
H10
9
COLON
BRIGHTNESS
INPUT
VSSo-.
FIGURE 1.
1·38 .
absolute maximum ratings
Voltage at Any Pin
Voltage at Any Display Output or
Switch Input Pin (MM5379 Only)
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
electrical characteristics
VSS + 0.3V to VSS - 25V
VSS + 0.3V to VSS - 55V
-40°C to +85°C
-65°C to +150°C
300°C
T A within operating range, VSS = 9V to 20V, VDD = OV, unless otherwise specified.
PARAMETER
Power Supply Voltage (VSS)
CONDITIONS
MIN
TYP
MAX
Outputs and Osc. Operational
9
Power Supply Voltage (VSS)
No Loss of Time Memory
5
25
Power Supply Current (ISS)
No Output Loads
1
5
dc
Input Frequency IOsc. 1 or Osc. 2)
Oscillator Input Voltage
Logical High Level
UNITS
20
2.097152
2.1
V
V
mA
MHz
(Note 1)
VSS-1.5
Logical Low Level
VSS
VSS-5.5
V
VSS
V
V
V
Switch In Voltage (MM5378)
Logical High Level
Internal Depletion Device to
Logical Low Level
VSS
VSS-1.5
. VSS
VDD
VSS~5
Switch In Voltage (MM5379)
Logical High Level
Logical Low Level
Internal Depletion Device to
VSS-5
V
VSS
V
VSS-25
VSS
Output Currents (MM5378)
Digit Outputs
Logical High Level
Logical Low Level
mA
8.0
VOH = VSS - 1V
40
VOL = VDD
J.l.A
Segment Outputs
Logical High Level
VOH = VSS - 1V
Logical Low Level
VOL = VDD
mA
2.0
p,A
10
Output Currents (MM5379)
Digit Anode Outputs
Logical High Level
Logical Low Level
Segment Cathode Outputs
Logical High Level
Logical Low Level
mA
8.0
VOH=VSS-5V
40
VOL = VSS - 45V
VOH=VSS-5V
VOL = VSS - 45V
J.l.A
mA
2.0
10
J.l.A
Note 1: These are the input levels required if an external oscillator input is preferred, using Osc. 2 (pin 5) as the input while holding Osc. 1 (pin 6)
to VSS.
'.
functional description
A block diagram of the MM5378 and the MM5379
auto clocks is shown in Figure 1. Connection diagrams
for these devices are shown on the' front page. Unless
otherwise indicated, the following discussions are based
on Figure 1.
Time Setting: Tim!! setting is accomplished via the
switch input pin. If this input is a logic high during the
M1 digit time, the minutes counter will advance at a
2 Hz rate with no carry to hours counter and will also
cause seconds counter to reset. If the switch input is a
logic high during the M10 digit time, the hours counter
will advance at a 2 Hz rate, minutes and seconds counter
will continue in real time. If the switch input is a logic
high during H 1 digit time, seconds, minutes, and hours
counters will reset to 12:00:00. If this input is a logic
high during Hl0 digit time, a test m.ode will exist in
which the minutes counter will advance at a 65.536 kHz
rate with carry to hours counter (see Figure 3). An
Crystal Oscillator: A quartz crystal, resonant at
2.097152 MHz, two capacitors and one resistor, together
with the internal MOS circuits form a crystal-controlled
oscillator as shown in Figure 2. Varying one of the
capacitors allows precise frequency setting. For test
purposes, Osc. 1 is the input and Osc. 2 is the output
of an inverting amplifier.
1-39
ill
functional description
(Continued)
voltage(s) for a short time during inter·digit transitions,
or (2) avoid physical adjacent inter-digit transitions.
The MM5379 auto clock utilizes an interlaced output
sequence and inter·digit blanking circuitry to prevent
display arcing problems. The digit sequence is: (1) digit
no.4 (unit minutes), (2) digit no. 2 (unit hours), (3) digit
no.3 (ten's of minutes), (4) digit no. 1 (ten's of hours),
etc. Blanking intervals are provided to' recharge level·
translating capacitors located in the display segment
drive lines (Figure 6). Both segment data and digit
enables are blanked. Figure 4 is a timing diagram which
illustrates output timing for the MM5379. Figure 5 is a
timing diagram which illustrates output timing for
the MM5378.
VSS
MDS CIRCUIT
-+
..----41~.....
TO
DIVIDER
CIRCUITS
FIGURE 2. Crystal Oscillator
internal pull·up resistor to VSS provides normal time·
keeping.
Brightness Control: Since display brightness is a func·
tion of cathode segment current, a capability of interrupting this current for a variable percentage of the
digit interval results in a brightness control. Depending
on the magnitude of the voltage applied, the digit
"ON" time will vary from 0% t01 00% of its possible
period. in 8 1/3% increments. This is illustrated in
Figures 4 and 5.
Output Multiplex Operation: Outputs from the appro·
priate internal counter are time division multiplexed at
a 2048 Hz rate. The MM5378 and MM5379 provide
12 outputs (4 digit·anode drive outputs plus 8 segmentcathode drive outputs). The additional "segment" drive
is provided to accommodate displays which feature a
colon. The colon output is switched at a 1/i Hz rate to
provide a blinking colon as a short-time indication that
the clock is operating.
"
Output Circuits: All display output drivers, both digit
and segment outputs, are open·drain enhancement
devices (Figure 6). Thus, all outputs are capable of
sourcing currents while external pull-downs are required
to sink currents. Figure 7 illustrates method of interfacing these outputs to gas discharge displays,
When driving vacuum fluorescent displays which enclose
more than one digit in a common gas envelope, it is
necessary to either (1) inhibit the segment drive
r;,-l11..-_____.....;.___
DIGIT ENABLE
UNITMINS-1 ''''
DIGIT ENABLE _ _ _ _...~L._ _ _ _ _ __
UNIT HOURS
HI
!
!
...____
!r;Q1
MIU !
DIGIT ENABLE _ _ _ _ _ _ _...
TEN'SMINS
r;,;l
1 n 'u L -
DIGIT ENABLE _ _ _ _ _ _ _ _ _ _
TEN'S HOURS
SELECTED MODE
SWITCH IN VH - r
WAVEFORM VL - 1
i
1
FUNCTION
• • • • • • SET MINUTES • • • • • •
MINUTES COUNTER ADVANCES AT 2 Hz RATE.
HOURS COUNTER UNAFFECTED. COLON HELD "ON ".
• •••••: •• RESET' • • • • • • •
TIME SET AND HELD AT 12:00:00.
COLON HELD "ON ".
• • • • • • • SET HOURS • • • • • •
_____
IL
HOURS COUNTER ADVANCES AT 2 Hz RATE.
MINUTES COUNTER UNAFFECTED. COLON BLINKING.
• • • • • • • • TEST' • • • • • • •
MINUTES COUNTER ADVANCES AT 65.536 kHz RATE WITH COMPLETE
CARRY. COLON HELD "ON" AT 65.536 kHz RATE.
SWITCH IN VH~
MORE THAN ONE
WAVEFORM VL
• • • • • • • REAL TIME' ••• ~ •
NORMAL TIME KEEPING.
COLON BLINKING.
vH
SWITCH IN
WAVEFORM VL
• • • • • • • REAL TIME • • • • • •
NORMAL TIME KEEPING.
COLON BLINKING.
• • • • • • • • RESET' • • • • • •
TIME SET AND HELD AT 12:00:00.
COLON HELD "ON ".
SWlTclllN VH
WAVEFORM VL
SWITCH IN
WAVEFORM
VH
VL
-
1--488JJS
I
f- 366JJs
I
f--122JJs
SWITCH IN VH
WAVEFORM
VL
SWITCH IN
WAVEFORM
HELO AT VH
I
"
VH
VL
HELO AT VL
FIGURE 3. MM5378, MM5379 Setting Control Functions
1-40
functional description
s:
s:CJ1
(Continued)
eN
"-J
CO
DIGIT NO.1
UNIT MINS
VSS
s:
s:CJ1
VSS
to
V-
DIGIT NO.2
UNIT HOURS
VSS
. V-
DIGIT NO.3
TEN'S MINS
VSS
VSS
V-
DIGIT NO.4
TEN'S HOURS
V-
eN
VSS
1
ON BRIGHT
100%
VSS
33.3%
BRIGHT
ON
ON
VSS-
ON
-- '00"
ON
ON
v-
BRIGHT
100%
33.3%
BRIGHT
ON
ON
'00"
BRIGHT
COLON
33.3%
BRIGHT
ON
V-
I!
ON BRIGHT
VSS
V-
!
ANY
SEGMENT
33.3%
BRIGHT
ON
FIGURE 4. MM5379 Output Timing Diagram
FIGURE 5. MM5378 Output Timing Diagram
MM5378
MM5379
VSS
VSS
n (DATA)
n (DATA)
TYPICAL DIGIT
o----1~OR SEGMENT
(OPEN DRAIN)
OUTPUT
TYPICAL DIGIT
o---i'" OR SEGMENT
(DPEN DRAIN)
FIGURE 6, Output Circuits
1-41
"-J
OUTPUT
ii
functional description
(Continued)
nor2.097152 MHz
22M
-A
- .
sl2t.
LAMP
VOLTAGE
T~
--11-::!:- I
lOOk
BRIGHTNESS 7
10
~1"F~
27V ~
35V_T
~6
300k
SET
MIN.
S 14 SWITCH IN
OSC2
8
Ml
5
OSC 1
VSS
MID
13
VO~
HI
MM5379
150
112W
HID
-;:-
.
3
IN4 003~~
c
b
1
d
2
18
.
17
16
15
-iIy6
1
9
12
11
g COLON
f
SET
HOURS
Iy
4
. ,f I
lOOk
+0 -
II
II
II
II
>
c
d
f
., .I
g COLON
II
820k
II
820k
1M
/I
1M
1M
II
II
1M
II
10M
0.05,)
150V
15k
b
II
II
~
.
GAS OISCHARGE DISPLAY
1M
II
NO
.
MID
HI
II
II
BAT TERY
I
I
HID
I
,
,.,
."
~~ ~ ~~ "-- ~~ ~~ ~~ ... -'..... 1
Vss - 45V
IG NITION
+
IN4003
1liio....i
......
.
10
.A
~-L
OOI"F
T
r---
.,
~
1
.:L
.11:T
......
3 .....
......
I"F~
~
FIGURE 7. Typical Application for MM5379
;-42
820
~
MI
"'1
IN914
2N5081
4.7k
VSS-180V
22k
Clocks
MM5382, MM5383 digital calendar clock radio circuits
general description
The MM5382 and MM5383 digital calendar clock
circuits provide the timing, control, and interface
circuitry for a minimum-cost, solid state, digital clock
radio_
•
Leading zero blanking
•
•
~4-hour alarm setting
The timekeeping function operates in either a 12-hour
or a 24-hour mode. The MM5382 is the 12-hour version,
and has a month-date format;the MM5383 is the 24-hour
version, and has a date-month format.
•
Brightness control
•
Date display (4 year calendar)
Outputs consist of a presettable 59-minute sleep timer
(e.g_, a timed radio turn-offl and an alarm tone. A power
failure indication warns the user that the time displayed
may be in error.
Other features include: alarm display; brightness control;
24-hour 'alarm set; PM indication; fast and slow set
controls; and a 9-minute snooze alarm. (The MM5383
has an alarm "ON" indicator.) Both circuits provide
open drain outputs for the direct drive of LED displays
to 15 mAo
Power failure indication (the word "OFF" is displayed
in MM5382 and all "ON" digits blink in MM5383
•
Presettable 59-minute sleep timer
•
Alarm display
•
Fast and slow set sleep and alarm
•
9 minute snooze alarm
•
Blinking colon
•
Alarm "ON" indication (MM5382 only)
•
Alarm tone output
•
No illegal time or date display at turn-on
II
applications
•
features
Alarm clock
•
Desk clock
•
Clock radios
•
Stop watch
•
50 or 60 Hz operation
•
Industrial clock
•
12 hour, month-date (MM5382) or 24 hour, datemonth (MM5383) display
•
Portable clock
•
PM indication (MM5382)
•
•
Timer
Sequential controllers
connection diagrams
Dual·1 n-Line Package
Dual-I n-Line Package
10 HRS -,
NC
10 HRS-g
PM
NC
HR -,
10 HRS-,
HR -,
BRIGHTNESS REF. OUTPUT
HR - d
10 HRS- b
HR - d
ALARM OUTPUT
HR -c
BRIGHTNESS REF. OUTPUT
HR -c
SLEEP OUTPUT
ALARM OUTPUT
• 50/60 Hz ORIVE
SLEEP OUTPUT
50/60 HzSELECT
HR -,
50/60 Hz ORIVE
VSS
HR -I
50/60 Hz SELECT
VOO
OATE OISPLAY/AOVANCE
ALARM ON/OFF
ALARM OISPLAY. SET/SNOOZE
SEOUENCE/SLEEP OISPLAY
11
10MINS -I
14
21
26
25
MIN -b
MIN -9
11
24
18
23
19
22
20
21
HR -I
MM5383
VOO 12
OATE OISPLAY/AOVANCE
13
ALARM ON/OFF 14
10MINS -.
13
BRIGHTNESS REF. INPUT 15
16
MIN -,
10MINS - b
12
ALARM "ON' INDICATOR
MIN -I
COLON
MM5382
HR -,
10
VSS 11
10MINS-g
ALARM OISPLAY. SET/SNOOZE
10 MINS -,
SEOUENCE/SLEEP OISPLAY
10MINS- d
BRIGHTNESS REF. INPUT
10MINS -c
MIN -I
MIN -,
MIN -,
MIN - d
MIN - b
MIN -c
MIN-g
30
29
28
16
11
18
19
20
TOPVIEW
TOP VIEW
Order Number MM5383N
See Package 24
FIGURE 1
1·43
10MINS -,
10 MINS-I
21 10 MINS- 9
26
10MINS -,
25
10 MINS-d
24
10MINS -c
23
MIN-e
22
MIN -d
21
MIN -c
15
Order Number MM5382N
See Package 24
COLON
10MINS-b
absolute maximum ratings'
N
ex)
M
Lt)
~
~
VOltage at Any Pin except Segment,
VSS +0.3V to VSS -28V
Colon, and PM
Voltage at Segment, Colon, and PM
VSS +0.3V to VSS -1 OV
-25°C to +70°C
Operating Temperature
-65°C to +150°C
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
300°C
Maximum Power Dissipation
1 Watt
Electrical Characteristics
T A within Operating Range
VSS = +18V to +26V, VDD = OV,
with specified output drive
unless otherwise specified
Functional Clock Voltage
VSS = +8V to +26V, VDD = 0
(No output drive spec)
electrical characteristics
PARAMETER
Power Supply Current
CONDITIONS
MIN
TYP
MAX
UNITS
No output levels
VSS = 8V
4
mA
VSS = 26V
5
mA
50/60 Hz Input
Frequency
Voltage
DC
50 or 60
30k
Hz
VSS =18V
Logical High Level
VSS-l
VSS
VSS
Logical Low Level
VDD
VDD
VDD+l
VSS-l
VSS-3
VSS
Float
VSS-6
V
VDD
VDD
VDD+2
V
VSS-l
VSS
Switch Input Voltages
(Date, Sequence, Alarm
Enable, Alarm Display)
Logical High Level
Logical Low Level (1)
Nominal Floating Level
Logical Low Level (2)
VSS
All Other Input Voltages
Logical High Level
Logical Low Level
Internal Depletion Load
VSS
VSS-15
to VDD
Power Failure Detect Voltages
(VSS Voltage)
Output Currents:
VSS = 18V to 26V, VDO = OV
1.0
8.0
V
All Segments and Colon
Logical High Level, Source
VOH = VSS -2V
Logical Low Level, Leakage
VOL =VSS -10V
15
mA
10
J.1A
PM Indicator and Alarm Indicator
Logical High Level, Source
VOH = VSS -2V
Logical Low Level, Leakage
VOH = VSS -10V
15
mA
10
J.1A
Alarm and Sleep Outputs
Logical High Level, Source
VOH = VSS -2V
2
mA
Logical Low Level, Sink
VOH = VSS-15V
500
J.1A
VSS = 18V to 26V
400
Alarm Output Tone
2000
Hz
830
mW
Frequency Modulated with 2 Hz
Total Power Dissipation
VSS = 26V, VDD = OV
lOUT (25 Segments) = 15 mA
T = 70°C
VOUT = VSS -2V
1-44
block diagram
SLEEP
OUT
SO/60Hz
SELECT
!
Vsso-VDDo--
PM
ALARM DISPLAY.
SET DR SNOOlE
DIGIT 4
SEQUENCE OR
SLEEP DISPLAY
COLON
DATE DISPLAY
OR ADVANCE
DIGIT 1
DIGIT3
DIGIT 2
ALARM
INDICATOR
LED
LED
CURRENT
REF
CONTROL OUTPUT
ALARM TONE
OUTPUT
FIGURE 2.
TABLE I. Display Modes and Setting Control Functions
FUNCTION
DATE DISPLAY/
ADVANCE
STEP
ALARM DISPLAY SET/SNOOZE
SEQUENCE/SLEEP
DISPLAY
Display Time
1
Float
Float
Float
Set Time
1
Float
Float
Momentary connect to VDD
for each step of setting time
2
VDD
Float
Float
1
Float
Connect to VDD
Float
and calendar
Display Alarm
for
< 2 seconds
Set Alarm:
2 Hz Rate
1
Float
Connect to VDD
Float
for> 2 seconds
60 Hz Rate
2
VDD
VDD
Float
1
Float
Float
Connect to VSS for
seconds
2 Hz Rate
1
Float
Float
Hold VSS for> 2 seconds
(Advances at 2 Hz Rate)
60 Hz Rate
2
VDD (Advances at 60 Hz Rate)
Float·
VSS
Display Sleep
<2
Set Sleep:
\
functional description
Connection diagrams for the MM5382 and the MM5383
Digital Clock Radio Circuits are shown in Figure 1.
A block diagram of these devices is shown in Figure 2.
,Unless otherwise indicated, the following discussions
are based on Figure 2. Figure 3 shows the general
purpose alarm clock and procedure to set the time,
month, day, alarm and sleep counters. Table I shows
the display modes and setting control functions.
50 or 60 Hz Select Input: A programmable prescale
counter divides the input line frequency by either 50 or
60 to obtain a 1 Hz base. This counter is programmed
to divide by 60 simply by leaving the pin unconnected; a
pull-down to VDD is provided by an internal resistor.
Operation at 50 Hz is programmed by connecting this
input to VSS.
50 or 60 Hz Drive: A shaping circuit is provided to
square the 50 or 60 Hz input. This circuit allows use of a
filtered sinewave input. The circuit is a Schmitt trigger
that is designed to provide about 4 V of hysteresis. A
simple RC filter should be used to remove possible linevoltage transients that could either cause the clock to
gain time or damage the device. The input should swing
between VSS and VDD. The shaper output drives a
counter chain which performs the timekeeping function.
Alarm Operation: The internal alarm comparator senses
coincidence between' the alarm counters (the alarm
setting) and the time counters (real time). The comparator
output is used to set a latch in the alarm and sleep circuits. The alarm latch remains set for 59 minutes during
which time the alarm or radio will· sound if the latch
outputs are not temporarily inhibited by another latch
set by the snooze input or reset by the alarm "OFF"
input.
1-45
M
ex)
M
LO
:2
:2
N
ex)
M
LO
:2
:2
functional description
(Continued)
Alarm ON/OFF/RADIO Input: Momentarily leaving this
input unconnected resets the alarm latch and thereby
silences the alarm. This input is also used to determine
if the alarm or the sleep output will be enabled when the
alarm latch is set. By connecting the input pin to VDD,
both the alarm output and the sleep output (radio) are
enabled when the alarm latch is set. If the input pin is
connected to VSS, only the sleep output (radio) is
enabled when the alarm latch is set. Momentarily leaving
this pin unconnected also readies the alarm latch for the
next comparator output, hence, the alarm will auto·
matically sound again in 24 hours (or at a new alarm
setting). If it is desired to silence the alarm for a day or
more, the Alarm ON/OFF Radio input pin should remain unconnected.
Alarm Output: The alarm output signal is a tone of from
400 Hz to 2000 Hz, which is gated on and off at a
2 Hz rate.
Alarm DisplaY,Set/Snooze: Momentarily connecting this
pin to VDD when the alarm and sleep outputs are disabled displays the alarm setting for 1.5 to 2 seconds. The
display shows the hours and minutes of the alarm setting,
a constant colon and a PM indication if the clock is in
the 12 hour mode. If the input pin is held to VDD for
longer than 2 seconds, the minutes of the alarm counter
start to advance at a 2 Hz rate. To increase the rate that
the alarm counter is set at, also connect the Date/
Advance input pin to VDD. The minutes of the alarm
counter will now advance at a 60 Hz rate. By momentarily connecting the input pin to VDD when the alarm
or sleep output is enabled, snooze is enabled for 8 or 9
minutes. Snooze inhibits the alarm output for between
8 and 9 minutes, after which the alarm output is enabled
again. Snooze has no effect on the sleep output. The
snooze feature may be repeatedly used during the 59
minutes in which the alarm latch remains set. Momentarily connecting this input pin to VDD when the clock
is in the power failure mode stops all power failure
indications and displays alarm. If this pin is connected to
VSS and date advance pin is connected to VSS, the clock
is in a test mode. All outputs are enabled and time and
alarm are set to 12:00 AM, the date is set to the 12th
month and the 1st day, and the sleep counter is set to
00 minutes. If the Alarm Display, Set/Snooze is at VSS,
all outputs and inputs are disabled except 50/60 Hz
Select and 50/60 Hz Drive.
increase - the rate at which the sleep counter is decremented, also connect the Date/Advance pin to VDD.
The sleep counter will now decrement at a 60 Hz rate.
Momentarily connecting the Sequence pin to VDD steps
the clock through' its set modes. There are 6 states; they
are real time, set hours, set minutes, set month (12 hour
model. set day (12 hour model. and the holding state.
When real time is displayed, a momentary connection
to VDD advances the clock to the set hours state. In this
state, hours are displayed, minutes are blanked, the colon
is constant, and an A or P is displayed in the unit minutes
position if the clock is in the 12 hour mode. To set
. hours, the Date/Advance pin is connected to V DD. The
next time the Sequence pin is connected to VDD, the
clock is advanced to the set minutes state. In this state,
the minutes are displayed, the hours are blank, the colon
is constant and the PM indication is displayed if the
clock is in the 12 hour mode and set for PM. The next
. state the clock advances to is the set left state. In the
12 hour mode, this is a month set state. For the 24 hour
mode, this is a day set state. In this state, the left two
digits of the display are shown, the colon and the right
two digits of the display are blank. The next state the
clock advances 'to is the set right state. In this state,
the day in the 12 hour mode or month in the 24 hour
mode is displayed in the right two digits of the display.
PMOOT
•
~~~ ~c=J~
~:~ ~:~
0
COLON
2
1
MM5382
MM5383
0
~~~ ~~~
~:~ ~:~
3
4
HOURS
MINUTES
MONTH
OATE
DATE
MONTH
~ ~c=J~
0
~ ~~~
0
0
0
Sleep Timer and Output: The sleep output can be used
to turn off a radio after a desired interval of up to 59
minutes. The time interval is chosen by selecting the
sleep display mode and setting the desired time interval.
This automatically results in a current-source output,
which can be u'sed to turn on a radio (or other appliance).
When the sleep counter, which counts downwards, reaches
00 minutes, a latch is reset and the sleep output current
drive is removed, thereby turning off the radio. This
turn-off may also be manually controlled (at any time in
the countdown) by a momentary VDD connection to
the Alarm Display, Set/Snooze input.
~ c=J~
~ ~c=J~
0
Sequence/Sleep Display and Set: If left open, time or
the counter to be set is displayed. Momentarily connecting this pin to VSS displays the sleep counter for
1.5 to 2 seconds. If after 2 seconds the pin is still at VSS,
the sleep counter will decrement at a 2 Hz rate. To
~ ~~~
0
~~~
~c=J~
~c=J~ ~:~
~ ~
sETMINUTES
SET MONTH
MM5382
~ ~:
SET DATE
MM5383
~c=J~
~ ~:
~~~ n:~
~
.~
Time and Date Display Format in 'Set' Mode
1-46
SET HOURS
SET DATE
MM5382
SET MONTH
MM5383
HOLD
functional description
(Continued)
The left two digits and colon are blank. The next transition on the Sequence input displays real time if the
minutes were not set. If the minutes counter was set,
the next state the clock advances to is the holding state.
In this state the time and the colon are blinking at a
2 Hz rate and held to the set time. To leave the holding
state, the Sequence Input is connected to VDD momentarily. If the clock remains in any state except the
holding state for more than 10 seconds without being
set, the clock will automatically advance to real time or
the holding state if minutes were set.
Alarm Indication Output: Whenever the alarm is enabled,
the Alarm Indicator output is turned on. It is used to
indicate to the user that the alarm has been set.
PM Output: The PM Output is available only in the
MM5382. This output is enabled only when time or
alarm are displayed.
Power Failure Indication: If the power to the integrated
circuit drops, indicating a momentary ac power failure
and possible loss of the correct time, in the MM5382
the word 'OFF' is displayed blinking at a 2 Hz rate, in
the MM5383 all the 'ON' segments blink at 2 Hz rate
and the colon is blank. Momentarily connecting the
Alarm Display Set/Snooze input to VDD displays first
the alarm for 1.5 to 2 seconds and then real time. In
addition, if the alarm was "ON" the Alarm "ON/OFF"
input should also be momentarily connected to VDD.
Note: Time set mode should not be initiated while in
alarm or sleep display 2 second time out. Time set mode
should be sequenced only when the clock displays real
time.'
Date/Advance Input: If left open, this input has no
effect on the clock. Momentarily connecting this pin t'o
VDD displays' the date for 1.5 to 2 seconds if the clock
was not in a set state. If after 2 seconds the input pin is
still at VDD, the date remains displayed until the input
pin is released. If the Date/Advance pin is connected to
VDD when the clock i~ in a set mode, the counter displayed will advance at a 2 Hz rate until the pin is' released.
Connecting this input pin to VDD when the sleep counter
or the alarm counter is displayed advances the displayed
counter at a 60 Hz rate. If the Date/Advance pin is connected to VSS, ,the seconds counter is bypassed and
minutes counter advances at a 1 Hz rate.
LED CURRENT CONTROL INPUT AND
REFERENCE, OUTPUT
Pin (15) MM5382, pin (16) MM5383 controls the gate
voltage at all the display outputs and the reference device.
The output drives can be disabled by connecting pin 15
MM5382, 16 MM5383 to VSS. This wire-OR capability
allows the display to be used for other functions (e.g.,
temperature). The output current can be controlled two
ways; 1) driving the output in saturated mode; 2) driving
the output in linear mode. (Refer to Figures 4 and 5.)
1. The reference device pins (4, 15) MM6382 (5, 16)
MM5383 are connected as diodes and an external
resistor'is used to set the desired current in these
diodes (see Figure 4). The segment drivers of all
digits are connected as current mirrors. The drain
Colon: The colon output blinks at a 1 Hz rate in the run
mode. It is constant during set hours and minutes, and
alarm display. The colon is blank for date display. 'The
colon blinks at a 2 Hz rate in the holding state.
10SECONOS
(AOVANCE FLOATING)
10SECONOS
(AOVANCE flOATING)
10 SECONOS
(AOVANCE FLOATING)
10 SECONOS
(AOVANCE flOATING)
10SECONOS
(AOVANCE flOATING)
"AOVANCE"
AT vilo
SETS AT
2 Hz RATE
10SECONOS
(AOVANCE flOATING)
10SECONOS
(AOVANCE FLOATIN'G)
10SECONOS
(AOVANCE flOATING)
NO
NO
SEQUENCE
SEQUENCE
Time and Date Set Flow Chart
Time and Date Set Flow Chart
MM5383, 24-Hour Mode
MM5382, 12-Hour Mode
1-47
"AOVANCE"
AT VOO
SETS AT
2 Hz RATE
s:
s:CJ1
W
CO
N
s:
s:
CJ1
w
CO
W
functional description (Continued)
voltage V1 of the segment drivers is selected such
that these. devices operate in saturation mode.
Since the drain current variation in saturation
mode operation of the MaS device is relatively
constant, the segment drive current does not vary
significantly, even though V1 is increased con·
siderably. However, as the voltage across the output
buffers increases, average power dissipation also
increases linearly. This technique of current control
is recommended to be used only with low current
LEOs (1-7 mAl.
Clock Set Up Procedure: (MM5382)
1. Connect 110V supply.
2. Blinking 'OFF' displayed.
3. Momentarily connect alarm display set/snooze pin
(13) to VOO which removes "OFF" and displays
first the alarm for 1.5 to 2 seconds, then real time.
4. Momentarily connect alarm "ON/OFF" to VSS.
5. Wait till the colon starts blinking. (Approximately
2 seconds.)
6. Time setting
a. Momentarily connect sequence pin (14) to VOO
display shows hour and AM or PM. Connect
advance pin (111 to VOO to advance hour.
b. Connect pin (14) momentarily to VOO display
shows minutes, connect pin (11) to VOO and
set minutes.
C. Connect pin (14) momentarily to VOO display
shows month, connect pin '(11) to VOO and
set month.
d. Connect pin (14) momentarily to VOO display
shows date, connect pin (11) to VOO and set
date.
e. Connect pin (14) momentarily to VOO and the
real time is displayed at2 Hz rate.
f. Connect pin (14) momentarily to VOO again
and real time is displayed continuously.
. 7. Alarm setting
a. Connect alarm display pin (13) to VOD and
hold it for more than 2 seconds .. Alarm minutes
will advance at slow rate.
b. Connecting pin (11) and pin (13) to VOO
simultaneously will advance the alarm time at a
fast rate.
C. Set the desired alarm time.
8. Sleep time setting
a. Connect, sleep display, pin (14) to VSS and
hold it for more than 2 seconds. Sleep time will
decrement at slow rate.
b. Connecting pin (11) and pin (14) to VOO
simultaneously will decrement the sleep time at
a fast rate.
C. Set the desired sleep time.
9. Connect pin 12 to VOO to activate alarm.
2. The high current drive requirement of large LED
displays can be accomplished by operating the
segment drivers in the linear mode. The circuit
for·· high current LED drivers is shown in Figure 5.
The reference output device is used in series with
a reference LED, diode and current setting resistor.,
A high beta PNP transistor provides the current
drive for all the segments. A reference voltage' V3
is 'developed which compensates for variations in
MaS process parameters and the variations in the
voltage drop across the LED. The resistor ~ets the
current in the reference LED which sets the
referen'cevoltage V3 which in turn sets the current
in the LEOs equal to resistor current minus the
base current of the transistor. Variation in second
supply voltage does not vary the LED currents so
long as the PNP transistor is kept operating in the
linear mode. Full wave rectified power supply
without any filtering can be used as a second
supply voltage V2. The LED brightness can be
varied by using a variable resisto'r.
Figure 6 shows a LED drive circuit which uses a single
resistor. The resistor controls the total current flowing
through all the segments. Brightness shall vary depending
on number of segments that are "ON" at that time.
Radio Frequency Interference: All display outputs include circuitry to slow up the switching transition time
to minimize radio frequency interference.
Note: Time and date setting must be done only in the
real time display mode.
)
\
".
FIGURE 3. Calendar Alarm Clock Using the MM5382 and a LED Display
'-48
.....
functional description
s
sCJ'I
·
(Continued)
eN
CO
N
VOO
s
sCJ'I
12
;;(
..s
OUTPUT
DRIVER
OPERATING
""LS
Vss------~~---r------~
10
CO
i...
eN
""
!
-Vl
CONTROL
LOGIC
eN
....!:."
FIGURE 4(a). Low Current LED Drive Control Circuit (1-7 rnA)
-3
-5
-7
-9
-11
VI (V)
FIGURE 4(b). Segment Current vs VI
(VDD at -18V) (Typical Output Characteristics)
Voo
OUTPUT
DRIVER
OPERATING
IRE FERENCE
LED" IR -lbOl
""~
-Vl
20
o
Vss
VSS
o
-5
-10
-15
-20
-25
-30
VOO (V) (REFERENCED TO VSS)
VSS
FIGURE 5(a). High Current LED Drive Current Circuits (7-15 rnA)
FIGURE 5(b). RON vs VDD (VDS at -1V)
(Typical Output Characteristics)
VLEO SUPPL Y
CURRENT
R LIMITING
RESISTOR
VOO
lfs:~
vss
LOG IC
100 I--jr---t-~----::~-+---+-~'l-l
r-V-/
/
L
V
r----IIN,\
I.
v,,-1.r:: ~~ -
t
\
voo
I 1-
Vee
VSS
VSS
FIGURE 6. Simple LED Drive Circuit
FIGURE 7. liN vs VIN (Typical
Input Depletion Load Characteristics)
'-49
Clocks
MM5384 LED display digital clock radio circuit
general description
The MM5384 digital clock radio circuit is a monolithic
MOS integrated circuit utilizing P-channel low-threshold,
enhancement mode and ion-implanted depletion mode
devices. It provides all the logic required to build several
types of clocks and timers. Four display modes (time,
seconds, alarm and sleep) are provided to optimize
circuit utility. The circuit interfaces directly with 3 1/2
digit 7-segment LED displays. The timekeeping function
operates from either a 50 or 60 Hz input, and the
display format is 12 hours (with leading-zero blanking
and AM/PM indication) or 24 hours. Outputs consist of
display drivers, sleep (e.g., timed radio turn-offl. and
alarm enable. Po'wer failure indication is provided to
inform the user that incorrect time is being displayed.
Setting the time cancels this indication. The device
operates over a power supply range of 8-26V and does
not require a regulated supply. The MM5384 is packaged
in a 40 lead dual-in-line package.
•
50 or 60 Hz operation
Single power supply
•
12 or 24 hour display format
24-hour alarm setting
•
•
•
•
All counters are resettable
Fast and slow set controls
Power failure indication
Blanking/brightness control capability
•
•
Dir~ct interface to 0.5" LED displays
•
•
9-minute snooze alarm
Presettable 59-m inute sleep timer
Elimination of illegal time display at turn-on
applications
•
Alarm clocks
•
Desk clocks
• Clock radios
• Automobile clocks
• Stopwatches
• Industrial clocks
features
•
•
•
•
\,
., AM/PM outputs
, } 12-hour format
• Leading-zero blanking
Portable clocks
Photography timers
•
Industrial timers
•
•
Appliance timers
Sequential controllers
block and connection diagrams
c~~~g~ 0-:;18::-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-,
SOURCE
1212:EHL~~~
0...::--------------------.
Dual-I n-Line Package
50/60 HZ
INPUT
PM OUT
COLON (I H,)
12124 HR SELECT
BLANKING IN
50/60 H,SELECT
50/60 H,IN
AL~~~
FAST SET IN
.,:.:'6:..-_--.
SLOW SET IN
ALARM
OFF
TO HRS
DIGIT
SNOOZE
SEes OISPLAY IN
ALARM DISPLAY IN
MM5384
TO 10'S
OF MINS
plGIT
10MINS-b
10MINS-e
ALARM OFF IN
10MINS-c
ALARM OUT
19-25
SLEEPOIS ~,;",-.----------------~
ALA~~
o-:-'o::-________________
~
SECOND~~ O-"g-----------------~
BLANKING
INPUT
4
B
TO MINS
DIGIT
OUT COMMON SOURCE
MINS-c
MINS-d
BLANKiNG
DETECTOR
SLDWSET~
MINS-f
SNOOZE IN
19
MINS--b
20
MINS-.
TOP VIEW
FAST SET
02---.
Order Number MM5384N
VSS
o-!-!-.
See Package 24
12
VDD~
FIGURE 1.
FIGURE 2
1-50
absolute maximum ratings
Voltage at Any Pin Except Segment Outputs
Voltage at Segment Outputs
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
VSS + 0.3 to VSS - 30V
VSS + 0.3 to VSS -15V
-25°C to +70°C
-65°C to +150°C
300°C
electrical characteristics
T A within operating range, VSS
=
24V to 26V, VDD
PARAMETER
Power Supply Voltage
Power Supply Current
50/60 Hz Input Frequency Voltage
=
OV, unless otherwise specified.
CONDITIONS
MIN
TYP
MAX
UNITS
Output Driving Display
24
26
V
Functional Clock
8
26
V
No Output Loads
VSS
VSS
= 8V
= 26V
VSS
= 8V to 26V
dc
·50 or 60
Logical High Level
VSS-1
VSS
Logical Low Level
VDD
VDD
50/60 Hz Input Leakage
4
mA
5
mA
10k
Hz
VSS
VDD+2
V
V
10
J.lA
Blanking Input Voltage
Logical High Level
Logical Low Level
VSS-1
VDD
VSS
VDD
Blanking Input Leakage
VSS
VSS-5
10
V
V
J.lA
All Other Input Voltages
Logical High Level
Logical Low Level
Power Failure Detect Voltage
Internal Depletion Device to VDD
(VSS Voltage). (Note 2)
Count Operating Voltage
Hold Count Voltage
(Note 2)
Output Current Levels
VSS = 24V to 26V,
Output Common = VSS
vss-i
VSS
VDD
VDD
VSS
VSS-6
V
V
1
8
V
8
26
V
26
V
10's of Hours (b & cl. 10's of
Minutes (a & d)
Logical High Level, Source
Logical Low Level, Leakage
1 Hz Display
Logical High Level, Source
Logical Low Level, Leakage
VDH = VSS -7V
VOL = VSS - 14V
10
VOH = VSS-7
VOL = VSS ~ 14
15
VOH=VSS-7V
VOL = VSS - 14V
5
mA
10
J.lA
mA
10
J.lA
All Other Displays
Logical High Level, Source
Logical Low Level, Leakage
Alarm and Sleep Outputs
mA
10
J.lA
VSS = 24V
Logical High, Source
VOH = VSS - 2
500
J.lA
Logical Low; Sink
VOL=VDD+2
1
J.lA
Note 1: Segment Output Current must be limited to 6 mA maximum by user; power dissipation must be limited to 900 mW at 70°C and 1.2W
at 25°C.
Note 2: Power fail detect voltage is 0.25V or more above the hold count voltage. The power fail latch trips into power fail mode at least O.25V
above the voltage at which data stored in the time latch is lost.
1·51
01
functional description
A block diagram of the MM5384 digital clock radio
circuit is shown in Figure 1. The various display modes
provided by this clock are listed in Table I. The
functions of the setting controls are listed in Tabie II.
Figure 2 is a connection diagram. The following dis·
cussions are based on Figure 1.
(Figure 4). Common source pin should be connected
to VSS.
12 or 24-Hour Select Input: By leaving this pin unconnected, the outputs for the most-significant display digit
(1 D's of hours) are programmed to provide a 12-hour
display format. An internal pull-down depletion device
is again provided. Connecting this pin to VSS programs
the 24-hour display format. See Figure 6 for 24-hour
appl ication.
50 or 60 Hz Input: A shaping circuit (Figure 3) is pro·
vided to square the 50 or 60 Hz input. This circuit
allows use of a filtered sinewave input. The circuit is a
Schmitt trigger that is designed to provide about 6V of
hysteresis. A simple RC filter such as shown in Figure 5,
is recommended in order to remove possible line-voltage
transients that could either cause the clock to gain time
or damage the device. The shaper output drives a counter
chain which performs the timekeeping function.
Power Fail Indication: If the power to the integrated
circuit drops, indicating a momentary ac power failure
and possible loss of clock, the AM or PM indicator will
flash at 1 Hz rate. A fast or slow set input resets an internal power failure latch and returns the display to normal.
50 or 60 Hz Select Inputs: A programmable prescale
counter divides the input .Iine frequency by either
50 or 60 to obtain a 1 Hz time base. This counter is
programmed to divide by 60 simply by leaving 50/60 Hz
select unconnected; pull-down to VOO is provided by an
internal depletion device. Operation at 50 Hz is programmed by connecting 50/60 Hz select to VSS.
Alarm Operation and Output: The alarm comparator
(Figure 1) senses coincidence between the alarm counters (the alarm setting) and the time counters (real
time). The comparator output is used to set a latch in
the alarm and sleep circuits. The latch output enables
the alarm output driver (Figure 4), the MM5384 output
that is used to control the external alarm sound generator. The alarm latch remains set for 59 minutes, during
which the alar~ will therefore sound if the latch output
is not temporarily inhibited by another latch set by the
snooze alarm input or reset by the alarm off input.
Display Mode Select Inputs: In the absence of any of
these three inputs, the display drivers present time-ofday information to the appropriate display digits. Internal pull-down depletion devices allow use of simple
SPST switches to select the display mode. If more than
one mode is selected, the priorities are as noted in
Table I. Alternate display modes are selected by applying
VSS to the appropriate pin. As shown in Figure 1 the
code converters receive time, seconds, alarm and sleep
information from appropriate points in the clock
circuitry. The display 'mode select inputs control the
gating of the desired data to the code converter inputs
and ultimately (via output drivers) to the display digits.
Snooze Alarm Input: Momentarily connecting snooze to
VSS inhibits the alarm output for between 8 and 9
minutes, after which the alarm will again be sounded.
This input is pulled-down to VOO by an internal depletion device. The snooze alarm feature may.be repeatedly
used during the 59 minutes in which the alarm latch
remains set.
Alarm Off Input: Momentarily connecting alarm off to
VSS resets the alarm latch and thereby silences the
alarm. This input is also returned to VOO by an internal
depletion device. The momentary alarm off input also
readies the alarm latch for the next comparator output;
and the alarm will automatically sound again in 24 hours
(or at a new alarm setting). If it is desired to silence the
alarm for a day or more, the alarm off input should
remain at VSS.
Time Setting Inputs: Both fast and slow setting inputs
are provided. These inputs are applied either singly or in
combination to obtain the control functions listed in
Table II. Again, internal pull-down depletion devices are
provided; application of VSS to these pins affects the
control .functions. Note that the control functions proper are dependent on the selected display mode. For
example, a hold-time control function is obtained by
selecting seconds display and actuating the slow set
input. As another example, the clock time may be reset
to 12:00:00 AM, by selecting seconds display and actuating both slow and fast set inputs.
Sleep Timer and Output: The sleep output at pin 14 can
be used to turn off a radio after a desired time interval
of up to 59 minutes. The time interval is chosen by
selecting the sleep display mode. (Table I) and setting
the desired time interval (Table II). This automatically
results in a current-source outputvia pin 14, which can
be' used to turn on a radio (or other appliance). When
the sleep counter, which counts downwards, reaches 00
minutes, a latch is rese.t and the sleep output current
drive is removed, thereby turning off the radio. This
turn-off may also be manually controlled (at any time in
the countdown) by a momentary VSS connection to the
Snooze input. The output circuitry is the same as the
other outputs (Figure 4).
Blanking Control Inputs: Connecting this Schmitt
Trigger input to VOO places all display drivers in a nonconducting, high-impedance state, thereby inhibiting the
display. See Figures 3 and 4. Conversely VSS applied to
this input enables the display. This input does not 'have
internal pull-down device.
Output Common Source Connection: All display output
drivers are open-drain devices with all sources common
1-52
functional description
(Continued)
VOO
50/60 HZ
BILN:~JI~~ -"---I
50/60 Hz
)C)-....-~~I~~JNOGR
SIGNAL
INPUT
Vss
FIGURE 3.50/60 or Blanking Input Shaping Circuits
VSS
*OUTPUT COMMON SOURCE BUS (PIN 18)
ii(OATA)=?~
---i
BLANKING
(FROM
SHAPER)
r----4~-O UTPUT
OUTPUT
(OPEN DRAIN)
,
VSS
FIGURE 4a. Segment Outputs
FIGURE 4b. Alarm and Sleep Outputs
TABLE I. MM5384 Display Modes
·SELECTED
DISPLAY MODE
DIGIT NO.1
DIGIT NO.2
DIGIT NO. 3
DIGITNO.4
Time Display
10's of Hours & AMIPM
Hours
10's of Minutes
Minutes
Seconds Display
Blanked
Minutes
10's of Seconds
Seconds
Alarm Display
10's of Hours & AMIPM
Hours
10's of Minutes
Minutes
Sleep Display
Blanked
Blanked
10's of Minutes
Minutes
*If more than one display mode input is applied, the display priorities are in the order of Sleep (overrides all others), Alarm, Seconds, Time (no other mode selected).
'·53
~
00
M
Ln
functional description
(Continued)
~
~
TABLE II. MM5384 Setting Control Functions
SELECTED
DISPLA Y MODE
CONTROL
INPUT
CONTROL FUNCTION
"Time
Slow
Fast
Both
Minutes Advance at 2 Hz Rate
Minutes Advance at 60 Hz Rate
Minutes Advance at 60 Hz Rate
Alarm
Slow
Fast
Both
Both
Alarm
Alarm
Alarm
Alarm
Seconds
Slow
Fast
Both
Both
Input to Entire Time Counter is Inhibited (Hold)
Seconds and 10's of Seconds Reset to Zero Without
a Carry to Minutes
Time Resets to 12:00:00 AM (12-hour format)
Time Resets to 00:00:00 (24-hour format)
Slow
Fast
Both
Substracts Count at 2 Hz
Substracts Count at 60 Hz
Substracts Count at 60 Hz
Sleep
Minutes Advance at 2 Hz Rate
Minutes Advance at 60 Hz Rate
Resets to 12:00 AM (12-hour format)
Resets to 00:00 (24-hour format)
*When setting time sleep minutes will decrement at rate of time counter, until the
sleep counter reaches 00 minutes (sleep counter will not recycle).
BLANKING
VSS
1------.-.;.,
OUTPUT COMMON SOURCE
27k
MM5384
UNIT HOURS
VOO 10'S OF HOURS
1D'S OF MINUTES
UNIT MINUTES
i
1 Hz PM AM
Uk
VOO
PM
AM
--d
LEO DISPLAY
COMMON CATHOOE
r2
--;--l
1 OJOOIPNP)
~~~~------~~---"
r:::;o::J
VLEO
SUPPLY
I
I
I OPTION 1
I
IL _______
VOO
J1
2
I
I
I
I.1OPTION 2
I ~22M
I
~__ . . . __ JI
IL_.:.
FIGURE 5. A Schematic Diagram of a General Purpose Alarm Clock
(12-Hour Mode) using the MM5384 and a 3 1/2-Digit LED Display
1-54
. .
1 ___ ,
functional description. (Continued)
PM
...+-~""--o-r-o- c.S.
AM
Switch A must be ganged with
Sleep display switch as shown.
1 Hz
10 HR b & c
SLEEP
DISPLAY
FIGURE 6. 24-Hour Operation: 10's of Hours Digit Connections
III
1-55
Clocks
MM5385, MM5386, MM5396, MM5397 digital alarm clocks
general description
features
The MM5385, MM5386, MM5396 and MM5397 digital
alarm clocks are monolithic MOS integrated circuits
utilizihg P-channel low-threshold, enhancement mode
and ion-implanted depletion mode devices_ MM5385 or
MM5396 and MM5386 or MM5397 have display formats
of 12 hours and 24 hours respectively, with 24-hour
alarm display capability_ They provide all the logic
required to build several types of clocks and timers.
Four display modes (time, seconds, alarm and sleep)
are provided to optimize circuit utility. The circuit
interfaces directly with 7-segment light emitting diodes
and requires two power supplies. The timekeeping
function operates from either a 50 or 60 Hz input.
MM5385 or MM5396 displays 12 hours with colon
flashing at a one second rate and a PM indication.
MM5386 or MM5397 displays 24 hours with leading
zero blanking. Outputs consist of display drives, sleep
(e.g., timed radio turn off), and alarm enable. Power
failure indication is provided to inform the user that
incorrect time is being displayed. 'The power failure
indication consists of flashing of all the "ON" digits at
a 1 Hz r'ate. Setti ng the time cancels this indication.
The device operates over a power supply range of
18-26V and LED supply voltage of 4-7V.
•
50 or 60 Hz operation
•
Low power dissipation
•
PM outputs in 12·hour format with a colon flashing
at a one second rate ((MM5385 and MM5396 only)
•
Leading zero blanking
•
24-hour alarm setting
•
All counters are resettable
•
Fast and slow set controls
•
Power failure indication
•
•
•
Blanking/brightness control capability
Direct interface to light emitting diode (LED) with
forward current of 3-15 mA
I ndividual drivers for each segment of each digit
•
9-minute snooze alarm
•
Presettable 59-minute sleep timer
•
Radio frequency interference eliminating slow up
circuitry at the outputs
•
Available in standard (MM5385, MM5386) or reverse
lead-bend version (MM5396, MM5397)
applications
•
The MM5396 and MM5397 are reverse lead-bend versions
(mirror image) of the MM5385, MM5386 (respectively)
ideally suited to facilitate PC board layouts when
designing an "L" shaped 'Clock "module" (vertical
display, horizontal component board); the MM5385,
MM5386 are better suited for applications where the
display and IC are mounted on a PC board in the ,same
plane. All four versions are supplied in a 40-lead dual-inline package.
Alarm clocks
•
Desk clocks
•
Clock radios
•
•
Stopwatches
Industrial clocks
•
•
Portable clocks
Photography timers
•
Industrial timers
'. Appliance timers
•
Sequential controllers
1 Hz
block diagram
12 HOUR 24HOUR
PINNING PINNING
31381
135)
ALARM OUT +-=~----,
ALARM OFF
COLON
b4
COLON
c4
PM
d4
c4
e4
b4
g4
0-:.;;'::';':-"",,,,-
TO HRS
DIGIT
SNOOZEI
ALARM DISPLAY
SLEEP 0 UT +,-+,"-'----1
TO 10'S
OF MINS
DIGIT
SLEEP DISI
SECONDS
LEO
.4
6
50160 HZ
INPUT
11
130)
20-26
115-211
~~~~~~[ ~
LED REFERENCE ~
OUTPUT
101311
Note. MM5396, MM5397 pin connections shown in parenthesis (xx).
SLOWSET~
FASTSET~
VSS~
121291
VDO~
TO MINS
DIGIT
FIGURE 1
1-56
absolute maximum ratings
Voltage at Any Pin
Voltage at Any Output Pin
Operating Temperature
Storage Temperature
Power Dissipation
Lead Temperature (Soldering, 10 seconds)
VSS + 0.3 to VSS - 28V
VSS + 0.3 to VSS - 7.5V
-25°C to +70°C
-u5°C to +150°C
1W
300°C
electrica I characteristics
T A within operating range, Vss = 18V to 26V, VDD = OV, unless otherwise specified.
PARAMETER
Power Supply Voltage (VSS)
Power Supply Current
CONDITIONS
TYP
MAX
UNITS
Output Driving Display
18
26
V
Functional Clock
8
26
V
No Output Loads, VSS = 26V
50/60 Hz Input Frequency Voltage
Logical High Level
. Logical Low Level
All Other Input Voltages
MIN
dc
VSS-l
VDD
50 or 60
5
mA
10k
Hz
V
VSS
VDD+1
V
(Note 2)
Except Sleep/Seconds Display
Logical High Level
Logical Low Level
VSS-1
Internal Depletion
VDD
VSS
VDD+7
V
V
7.5
V
Device to VDD
Power Failure Detect Voltage
(VSS Voltage) (Note 1)
Output Currents
VSS ~ 18V to 26V,
VDD = OV. Current Measured
in Individual Segment Driver
with 0 Current in Remaining
Segment Driver. LED Current
Control Connected to VDD
All Segment Drivers
Logical High Level
VOH = VSS - 2
Logical Low Level
VOL = VSS - 6
mA
15
10
J.1A
Alarm and Sleep Outputs
Logical High Level
Logical Low Level
LED Reference Output
VOH = VSS -2V
500
J.1A
VOL = VDD + 2
J.1A
LED Current Control
Connected to V DD,
VSS = 18V, All Segment
Driver 0 Current
Logical High Level
VOH = VSS - 2
Logical Low Level
VOL = VSS - 6
mA
15
10
J.1A
Note 1: The power·fail detect voltage is 0.5V or more above the hold count voltage. The power·fail latch trips into the power·fail mode at least
0.5V above the voltage at which data stored in the time latch is lost.
Note 2: Sleep/seconds display (pin 11 on MM5385 and MM5386, pin 30 on MM5396 and MM5397). Connect pin to VSS for Sleep display.
Conf!ect pin to VOO for Seconds display. Leave pin open for normal time display.
1·57
functional description
A block diagram of the MM5385, MM5386( MM5396
and MM5397 digital alarm clock is shown in Figure 1.
The various display/setting modes are listed in Table I
and Table II shows the setting control functions. The
following description is based on Figure 1; for simpl ification, pin numbers in the text are shown only for
the MM5385 and MM5386, but pin connections for the
MM5396 and MM5397 may be cross-referenced from the
diagrams in Figure 2.
in Figure 1 the code converters receive time, alarm and
sleep information from appropriate points in the clock
circuitry. The display mode select inputs control' the
gating of the desired data to the code converter inputs
and ultimately (via output drivers) to the display digits.
Time Setting Inputs (pins 9 and 10): Both fast and slow
setting inputs are provided. These inputs are applied either
singly or in combination to obtain the control functions
listed in Table II. Again, internal depletion loads to VOO
are provided, application of VSS to these pins affects
the control functions. Note that the control functions
proper are dependent on the selected display mode.
For example, a hold-time control function is obtained
by selecting secorlds display and actuating the slow set
input. As another example, the clock time may be reset
to 12:00:00 AM (midnight), in the 12-hour format
(0:00:00 in the 24-hour format), by selecting seconds
display and actuating both slow and fast set inputs.
50 or 60 Hz Input (pin 8): A shaping circuit (Figure 3)
is provided to square the 50 or 60 Hz input. This circuit
allows use of a filteredsinewave input. The circuit is a
Schmitt Trigger that is designed to provide about 6V of
hysteresis. A simple RC filter, such as shown in Figure 7,
should be used to remove possible line-voltage transients that could either cause the clock to gain time or
damage the device. The input should swing between
VSS and VOO. The shaper output drives a counter
chain which performs the timekeeping function.
Alarm Operation and Output (pin 16); The alarm comparator (Figure 1) senses coincidence between the alarm
counters (the alarm setting) and the time counters
(real time). The comparator output is used to set a latch
in the alarm and sleep circuits. The latch output enables
the open· dra(n alarm output driver to control the
external alarm sound generator. The alarm latch remains
set for 59 minutes, during which the alarm will therefore
sound if the latch output is not temporarily inhibited
by another latch set by the snooze alarm input (pin 17)
or reset by the alarm "OFF" input (pin 15).
50 or 60 Hz Select Input (pin 7): A programmable
prescale counter divides the input line frequency by
either 50 or 60 to obtain a 1 pps time base. This counter
is programmed, to divide by 60 simply by leaving pin 7
unconnected; pull-down to VOO is provided by an
internal depletion load. Operation at 50 Hz is programmed by connecting pin 7 to VSS.
Display Mode Select I nputs (pins 11 and 17): I n the
absence of any of these two inputs (i.e., pin open),
the display drivers present time-of-day information to
the appropriate display digits. Snooze/alarm display
input has an internal pull-down depletion load to VOD.
Sleep/seconds display input has an internal voltage
control which allows this input to assume three input
states. The sleep time can be displayed by connecting
pin 11 to VSS and seconds can be displayed by connecting pin 11 to VOO, and if pin 11 is left open,
normal time is displayed. If more than one mode is
selected, the priorities are as noted in Table I. As shown
24HR
Snooze/Alarm Display (pin 17): Momentarily connecting
pin 17 to VSS inhibits the alarm output for between
8 and 9 minutes after which the alarm will again be
sounded and display alarm time. This input is pulleddown to VOO by an internal depletion load. The snooze
alarm feature may be repeatedly used during the 59
minutes in which the alarm latch remains are set; connecting pin ,17 to VSS displays alarm time.
12 HR
lOs HR
lOs HR
10, HR
10,HR
b4
HR f3
HR f3
e4
HR g3
HR g3
10,HR .4
PM
HR .3
HF .3
10, HR d4
COLON
HR b3
HR b3
10, HR.4
COLON
HR d3
HR d3
1 Hz
HR e3
HR e3
50/60 Hz SELECT
HR .3
HR e3
10,HR g4
50/60 Hz INPUT
FAST SET
SLOW SET
10
31
MM5385 -12 HOUR
MM5386 -24 HOUR
SLEEP/SEC OISPLAY
VDD
28
Vss
27
SLEEP OUTPUT
26
ALARM "OFF"
25
ALARM 0 UTPUT
SNOOZE ANO ALARM OISPLAY
LEO CUR CONTROL
LEO REF OUTPUT
MINel
30
' 29
18
19
20
21
10MINSf2
10MINSf2
10MINSg2
10MINSg2
10MINSa2
10MINS.2
10MINSd2
10 MINS d2
10MINSb2
10MINSb2
10MINS.2
10MINS e2
10MINSe2
10 MINSe2
40
39
38
12 HR
24 HR
b4
10,HR
10sHR
e4
10sHR
10, HR
PM
37 COLON
36
COLON
35
1 Hz
34
50/60 Hz SELECT
IViIN fl
ALARM "OFF"
MIN gl
MIN gl
ALARM OUTPUT
MINaI
MIN bl
MINbl
MINel
MIN.l
MINdl
MINdl
TOP VIEW
SNOOZE AND ALARM DISPLAY
LED CUR CONTROL
22
21 LED REF OUTPUT
MIN el
TOPVIEW
Order Number MM5385N or MM5386N
Order Number MM5396N or MM5397N
See Package 24
See Package 24
FIGURE 2
1-58
10, HR g4
MM5396 - 12 HOUR
MM5397 - 24 HOUR
MINfl
MINaI
10, HR d4
10, HR e4
33 50/60 Hz INPUT
32
FAST SET
31
10
11
10, HR.4
functional description
(Continued)
Alarm "OFF" Input (pin 15): Momentarily connecting
pin 15 to VSS resets the alarm latch and thereby silences
the alarm. This input is also returned to VOO by an
internal depletion load. The momentary alarm "OFF"
input also readies the alarm latch for the next comparator
output, and the alarm will automatically sound again in
24 hours (or at a new alarm setting). If it is desired to
silence the alarm for a day or more, the alarm "OFF"
input should remain at VSS.
14, which can be used to turn on a radio (or other
appliance). When the sleep counter, which counts downwards, reaches 00 minutes, a latch is reset and the sleep
output drive is removed, thereby turning off the radio.
This turn off may also be manually controlled (at any
time in the countdown) by a momentary VSS connection to the snooze input (pin 17).
Segment Outputs (pins 1-6 and 20-40): All segment
outputs are open drain devices with all sources connected to VSS. Each segment output may source direct
current of 15 mA at 2Von the output device. Figure 5(b)
shows the output resistance (RON) of segment driver
with respect to VOO.
Vee
Power Failure Indications: Power failure indication is
shown by the flashing of all "ON" digits at 1 Hz rate.
A fast or slow set input resets an internal power failure
latch and returns the display to normal. The power
failure latch trips into the power failure mode prior
to the loss of data stored in the time latches. When
powered up, alarm and sleep outputs will be in the
"OFF" state. In order to assure guaranteed power
fail indication, power supply rise time should not exceed
10 V/ms.
SO/60PPS
OUTPUT
Vss
FIGURE 3. 50/60 Hz Input Shaping Circuits
LED CURRENT CONTROL INPUT AND REFERENCE
OUTPUT (PINS 19 AND 18)
Sleep Timer and Output (pin 14): The sleep output at
pin 14 can be used to turn off a radio after a desired
time interval of up to 59 minutes. The time interval is
chosen by selecting the sleep display mode (Table I)
and setting the desired time interval (Table Ill. This
automatically results in a current-source output via pin
Pin 18 controls the gate voltage at all the display outputs
and the reference device. The output drivers can be
disabled by connecting pin 18 to VSS. This wire-OR
capability allows the display to be used for other func. tions (e.g., temperature, radio frequency wavelength).
TABLE I. MM5385, MM5386, MM5396, MM5397 Display Modes
·SELECTED
DISPLA Y MODE
DIGIT NO. 1
DIGITNO.2
DIGIT NO.3
DIGIT NO. 4
Time Display
10's of Hours & AM/PM
Hours
10's of Minutes
Minutes
Seconds Display
Blanked
Minutes
10's of Seconds
Seconds
Alarm Display
lO's of Hours & AM/PM
Hours
lO's of Minutes
Minutes
Sleep Display
Blanked
Blanked
10's of Minutes
Minutes
*If more than one display m';,de input is applied, the display priorities are in the order of Sleep (overrides
all others), Alarm, Seconds, Time (no other mode selected!.
TABLE II. MM5385, MM5386, MM5396, MM5397 Setting Control Functions
SELECTED
DISPLA Y MODE
CONTROL
INPUT
CONTROL FUNCTION
*Time
Slow
Fast
Both
Minutes Advance at 2 Hz Rate
Minutes Advance at 60 Hz Rate
Minutes Advance at 60 Hz Rate
Alarm
Slow
Fast
Both
Both
Alarm
Alarm
Alarm
Alarm
Seconds
Slow
Fast
Both
Both
Input to Entire Time Counter is Inhibited (Hold)
Seconds and 10's of Seconds Reset to Zero Without
a Carry to Minutes
Time Resets to 12:00:00 AM (Midnight) (MM5385, MM5396)
Time Resets to 0:00:00 (MM5386, MM5397)
Slow
Fast
Both
Subtracts Count at 2 Hz
Subtracts Count at 60 Hz
Subtracts Count at 60 Hz
Sleep
Minutes Advance at 2 Hz Rate
Minutes Advance at 60 Hz Rate
Resets to 12:00 AM (Midnight) (MM5385, MM5396)
Resets to 0:00 (MM5386, MM5397)
*When setting time sleep minutes will decrement at rate of time counter, until the sleep
counter reaches 00 minutes (sleep counter will not recycle).
1·59
functional description
(Continued)
The output current can be controlled two ways:
1) d~iving the output in saturated mode; 2) driving
the outPiJt.in linear mode. (Refer to Figures 4 and 5).
2) The high current drive requirement of large LED
displays can be accomplished by operating the segment
drivers in the linear mode. The circuit for high current
LED drivers is shown in Figure 5. The reference output
device is used in series with a reference LED, diode and
current setting resistor. A high beta PNP transistor
provides the current drive for all the segments. A reference voltage V3 is developed which compensates for
variations in MOS process parameter and the variations
in the voltage drop across the LED. The resistor sets the
current in the reference LED which sets the reference
voltage V3. This in turn sets the current in the LEDs
equal to resistor current less the base current of the
transistor. Variation in second supply voltage does not
vary the LED currents so long as the PNP transistor is
kept operating in the linear mode. Full wave rectified
power supply without any filtering can be used as a
second supply voltage V2. The LED brightness can be
varied by using a variable resistor.
1) The reference device (pins 18 and 19) is connected
as a diode, and an external resistor is used to set the
desired current in this diode (see Figure 4). The segment drivers of all digits are connected as current
mirrors. The drain voltage V1 of the segment drivers
is selected such that these devices operate in saturation
mode. Since the drain current variation in saturation
mode operation of the MOS device is relatively
constant, the segment drive current does not vary
significantly, even though V1 is increased considerably.
However, as the voltage across the output buffers
increases, average power dissipation also increases
linearly. This technique of current control is recommended to be used only with low current LEDs
(1-7 mAl.
12
VLED SUPPLY
DC DR-.:::::A:A:T
OUTPUT
DRIVER
OPERATING
,u.lt=
18
-+-_......J
-V1
V S S - - -......
C(
.§.
10
.;!-
i
!-
2:
I
CONTROL
LOGIC
-3
-5
-9
-7
-11
v, (V)
FIGURE 4(a). Low Current LED Drive Control Circuit (1-7 mAl
FIGURE 4(b). Segment Current vs VI
(VDD at -18V) (Typical Output Characteristics)
VDO
120
'REFERENCE
oLEO -IR -lbQ1
OU1;PUT
DRIVER
OPERATING
----~V3
SEGMENT
LEOS
18
PINS 1-6 AND.
20~
Vss
VSS
.
".rt=
-V1
100
q 10.7 mA,
80
S
~
12.5 rnA
,,~
60
16.6?,A
P'N'-SAND2D-4a,
~
40
~ ...
SEGMENT ....
DR'VER -20
rnA
20
o
o
-5
-10
-15
-20
-25
-30
VDD (V) (REFERENCED TO VSS)
Vss
FIGURE 5(a). High Current LED Drive Control Circuit (7-15 mAl
1-60
FIGURE 5(b). RON vs VDD (VDS at -lV)
(Typical Output Characteristics)
functional description
(Continued)
Radio Frequency Interference: All display outputs
include circuitry to slow up the switching transition
time to minjmize radio frequency interference.
Figure 6 shows a LED drive circuit which uses a single
resistor. The resistor controls the total current flowing
through all the segments. Brightness shall vary depending
on number of segments that are on at that time.
VLEO SUPPLY
CURRENT
,:lOO
~'~ :~:~ \~.:~
100
/
I
20-40
.
--I
t
VSS
o
CONTROL
LOGIC
Vss
V
I
/
V'
11:IN~9~D:.2.5~ _ _
1:":
V'NT I
v
r:;g
I
,00,
-
Voo
,
Vss
VDD
Vss
-
II
VIN IV)
FIGURE 6. Simple LED Drive Circuit
FIGURE 7. liN vs VIN (Typical
Input Depletion Load Characteristics)
VOO
ALARM
DRIVE
~14-.....---;_I--1>--1 Vo 0
LEO CURRENT
CONTROL
SLEEP
DRIVE
1:3
6u:J
VOO
10'S Of HOURS
UNIT HOURS
10'S Of MINUTES
UNIT MINUTES
FIGURE 8. General Purpose Alarm Clock Using the MM5385 or MM5396 and LED Display
1·61
Clocks
MM5387AA, MM53108 digital alarm clocks
general description
features
The MM5387AA, MM53108 digital alarm clocks are
monolithic MaS integrated circuits utilizing P-channel
low-threshold, enhancement mode and ion·implanted
depletion mode devices. They provide all the logic
required to build several types of clocks and timers
with up to four display modes, (time, seconds, alarm
and sleep) to maximize circuit utility, but are specifically intended for clock-radio applications. Both devices
will directly-drive 7-segment LED displays in either a
12 hour format (3% digits) with lead·zero blanking,
AM/PM indication and flashing colon, or 24 hour
format (4 digits) through hard-wire pin selection; the
timekeeping function operates from either a 50 or
60 Hz input, also through pin selection. Outputs consist
of display drivers, sleep (e.g., timed radio turn-off), and
alarm enable. A power-fail indication mode is provided
to inform the user of incorrect time display by flashing
all "ON" digits at a 1 Hz rate, and is cancelled by
simply resetting time. The device operates over a supply
range of 24-26V which does not require regulation.
•
•
•
50 or 60 Hz operation
Single power supply
12 or ?4 hour display format
•
•
•
•
•
•
•
AM/PM outputs
}
12 hour format
Leading-zero blanking
24-hour alarm setting
All counters are resettable
Fast and slow set controls
Power failure indication
Elimination of illegal time display at turn "ON"
•
•
•
•
Direct interface to LED displays
9-minute snooze alarm
Presettable 59-minute sleep timer
Available in standard (MM5387 AA) or mirror image
(MM53108) pin-out
applications
The MM53108 is electrically identical to the
MM5387AA, but with mirror·image pin-out to facilitate
PC board layout when designing a "module" where the
LED display and MaS chip are mounted on the same
side; the MM5387 AA is more suited for "L" shaped
module designs (vertical LED display, horizontal component board). Both devices are supplied in a 40-lead
dual-in-line package.
•
•
•
•
Alarm clocks
Desk clocks
Clock radios
Automobile clocks
•
•
Stopwatches
Industrial clocks
II
Portable clocks
•
•
•
•
Photography timers
Industrial timers
Appliance timers
Sequential controllers
block diagram
C~~r,;g~ ~23;,.:;(1~8)_ _ _ _ _ _ _ _-,--_ _ _ _ _ _ _ _ _ _ _ _- - ,
SOURCE
lZ12~EHL~~~ ~J8;,,;,{3;:.)_ _ _ _ _ _ _ _ _-,--_ _ _ _ _ _ _ _ _ _...,
50/1i0 HZ
INPUT
ALARM OUT "":;~----.
ALARM OFF o-=;;",:,:,;.:......~
TO HRS
DIGIT
SNOOZE
SLEEP 0 UT .--"'-'----'
TO 10'S
OF MINS
DIGIT
SLEEP OIS 0-=:..:.:..:.:......------------------_+
ALARM OIS
SECONOS DIS
3
-------------------+1
0-:,;.;1(:.;,;10:.:.,)
0-:3;;.2(~9)_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __+I
NC 0
16-22
(19-25)
TOMINS
DIGIT
31(4)
33(8)
SLOWSET~
FAST SET
34 (1)
<>---'-'---+
28(13)
Vss~
29(12)
VDO~
Note. MM53108 pin connections shown in parenthesis
FIGURE 1
'·62
absolute maximum ratings
Voltage at Any Pin Except Segment Outputs
Voltage at Segment Outputs
Operati ng Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
VSS + 0.3 to VSS - 30V
VSS + 0.3 to VSS - 15V
-25°C to +70°C
-65°C to +150°C
300°C
electrical characteristics
T A within operating range, VSS == 24V-26V, VDD == OV, unless otherwise specified.
PARAMETER
Power Supply Voltage
Power Supply Current
CONDITIONS
MIN
TYP
MAX
UNITS
Output Driving Display
24
26
V
Functional Clock
8
26
V
No Output Loads
VSS == 8V
4
mA
VSS == 26V
5
mA
50/60 Hz Input
Frequency Voltage
dc
50 or 60
Logical High Level
VSS-l
VSS
Logical Low Level
VDD
VDD
VSS == 8V to 26V
Input Leakage
10k
Hz
V
VSS
V
VDD+2
100
pA
All Other Input Voltages
Logical High Level
Logical Low Level
Power Failure Detect Voltage
Internal Depletion Load to VDD
(VSS Voltage). (Note 2)
Count Operating Voltage
VSS
VSS
V
VDD
VDD
VSS-6
V
1
7.5
V
8
26
V
26
V
(Note 2)
Hold Count Voltage
Output Current Levels
VSS-l
VSS == 24V to 26V,
. Output Common == VSS
10's of Hours (b & c), 10's of Minutes
(a & d)
Logical High Level, Source
VOH == VSS -4V
Logical Low Level, Leakage
VOL == VSS - 14V
mA
16
pA
10
1 Hz Display
Logical High Level, Source
VOH == VSS- 4
Logical Low Level, Leakage
VOL == VSS -14
24
rnA
10
pA
(Note 1)
mA
10
pA
All Other Displays
Logical High Level, Source
VOH == VSS - 4V
Logical Low Level, Leakage
VOL == VSS -:- 14V
Alarm and Sleep Outputs
8
VSS == 24V
Logical High, Source
VOH == VSS - 2
500
pA
Logical Low, Sink
VOL:= VSS - 2
1
pA
0
Note 1: Segment output current must be limited to 11 rnA maximum by user; power dissipation must be limited to 900 mW at 70 e and 1.2W
at 25°e.
Note 2: The power-fail detect voltage is O.5V or more above the hold count voltage. The power-fail latch trips into power-fail mode at least O.5V
above the voltage at which data stored in the time latch is lost.
1-63
II
functional description
gating of the desired data to the code converter inputs
and ultimately (via output drivers) to the display digits.
A block diagram of the MM5387AA, MM53108 digital
clock radio circuit is shown in Figure 1. The various
display setting modes are listed in Table I, and Table II
shows the setting control functions. The following
description is based on Figure 1 and refers to both
devices as they are electrically identical.
Time Setting Inputs: Both fast and slow setting inputs
are provided. These inputs are applied either singly or
in combination to obtain the control functions listed in
Table II. Again, internal depletion pull-down devices
are provided; application of VSS to these pins affects
the control functions. Note that the control functions
proper are dependent on the selected display mode.
For example, a hold-time control function is obtained
by selecting seconds display and actuating the slow set
input. As another example, the clock time may be reset
to 12:00:00 AM, by selecting seconds display and actuating both slow and fast set inputs.
50 or 60 Hz Input: A shaping circuit (Figure 3) is provided to square the 50 or 60 Hz input. This circuit
allows use of a filtered sinewave input. The circuit is a
Schmitt trigger that is designed to provide about 6V of
hysteresis. A simple RC filter such as shown in Figure 7,
should be used to remove possible line-voltage tran. sients that could either cause the clock to gain time or
damage the device. The shaper output drives a counter
chain which performs the timekeeping function.
Output Common Source Connection: All display output drivers are open-drain devices with all sources
common (Figure 4a). The common source pin should
be connected to VSS.
50 or 60 Hz Select Input: A programmable prescale
counter divides the input line frequency by either
50 or 60 to obtain a 1 Hz time base. This counter is
programmed to divide by 60 simply by leaving 50/
60 Hz select unconnected; pull-down to VDD is provided by an internal depletion load. Operation at 50 Hz
is programmed by connecting 50/60 Hz select to VSS.
12 or 24 Hour Select Input: By leaving this pin unconnected, the outputs for the most-significant display
digit (1 a's of hours) are programmed to provide a
12·hour display format. An internal depletion pulldown device is again provided. Connecting this pin to
VSS programs the 24-hour display format. Segment
connections for 10's of Hours in 24-hour mode are
shown in Figure 6.
Display Mode Select Inputs: In the absence of any of
these three inputs, the display drivers present time-ofday information to the appropriate display digits.
Internal depletion pull-down devices allow use of simple
SPST switches to select the display mode. If more than
one mode is selected, the priorities are as noted in
Table I. Alternate display modes are selected by applying VSS to the appropriate pin. As shown in Figure 1
the code converters receive time, seconds, alarm and
sleep information from appropriate points in th~ clock
circuitry. The display mode select inputs control the
Power Fail Indication: If the power to the integrated
circuit drops, indicating a momentary ac' power failure
and possible loss of clock, all "ON" segments will
flash at· 1 Hz rate. A fast or slow set input resets an
internal power failure latch and returns the display to
normal.
connection diagrams
Dual-ln·Line Package
Dual·1 n·Line Package
PM OUTPUT
AM OUTPUT
10HRS-b&c
HRS -f
12/24 HR SELECT
HRS -g
NC
HRS -a
50/60 Hz SelECT
HRS -b
50/60 Hz INPUT
HRS - d
HRS-c
HRS -e
40
PM OUTPUT
COLON (1 Hz)
AM OUTPUT
10HRS-b&c
COLON (1 Hz)
12/24 HR SELECT
HRS -f
NC
HRS -g
HRS-l
50/60 Hz SE LE CT
50/60 Hz INPUT
HRS -b
FAST SET INPUT
FAST SET INPUT
HRS -d
SLOW SET INPUT
SLOW SET INPUT
HRS -c
SECOND DISPLAY INPUT
SECOND DISPLAY INPUT
HRS -e
10MINS-f
ALARM DISPLAY INPUT
ALARM DISPLAY INPUT
10MINS-f
10MINS-g
SLEEP DISPLAY INPUT
SLEEP DISPLAY INPUT
10MINS -g
10MINS-a\!td
Voo
Voo
10MINS-a&d
10MINS-b
VSS
vss
10MINS-b
10MINS-e
SLEEP OUTPUT
SLEEP OUTPUT
10MINS-e
10MINS-c
ALARM "OFF"INPUT
ALARM "OFF" INPUT
10MINS-c
MINS -f
ALARM OUTPUT
ALARM OUTPUT
MINS -I
MINS -g
SNOOZE INPUT
SNOOZE INPUT
MINS-g
OUTPUT COMMON SOURCE
MINS-a
MINS-a
MINS -b
MINS -e
OUTPUT COMMON SOURCE
19
20
MINS-c
MINS -c
MINS-b
MINS -d
MINS -d
MINS-e
TOP VIEW
TOP VIEW
Order Number MM5387 AAN
See Package 24
Order Number MM53108N
See Package 24
FIGURE 2(a). MM5387AA
FIGURE 2(b). MM53108 (Mirror Image Pin·Out)
1-64
functional description
s
sU1
(Continued)
Alarm Operation and Output: The alarm comparator
(Figure 1) senses coincidence between the alarm counters (the alarm setting) and the time counters (real time).
The comparator output is used to set a latch in the
alarm and sleep circuits. The latch output enables the
alarm output driver (Figure 4b) which is used to
control the external alarm sound generator. The alarm'
latch remains set for 59 minutes, during which the alarm
will therefore sound if the latch output is not temporarily inhibited by another latch set by the snooze alarm
input or reset by the alarm "OFF" input.
silences the alarm. This input is also returned to VOO by
an internal depletion device. The momentary alarm
"OFF" input also readies the alarm latch for the next
comparator output, and the alarm will automatically
sound again in 24 hours (or at a new alarm setting).
If it is desired to silence the alarm for a day or more,
the alarm "OFF" input should remain at VSS.
Sleep Timer and Output: The sleep output can be used
to turn "OFF" a radio after a desired time interval of up
to 59 minutes. The time interval is chosen by selecting
the sleep display mode, (Table I) and setting the desired
time interval (Table II). This automatically results in a
current-source output which can be used to turn "ON" a
radio (or other appliance). When the sleep counter,
which counts downwards, reaches 00 minutes, a latch
is reset and the sleep output current drive is removed,
thereby turning "OFF" the radio. This turn "OFF"
may also be manually controlled (at any time in the
countdown) by a momentary VSS connection to the
Snooze input. The output circuitry is the same as the
other outputs (Figure 4b).
Snooze Alarm Input: Momentarily connecting snooze
to VSS inhibits the alarm output for between 8 and 9
minutes, after which the alarm will again be sounded.
This input is pulled-down to Vbo by an internal depletion device. The snooze alarm feature may be repeatedly
used during the 59 minutes in which the alarm latch
remains set.
Alarm "OFF" Input: Momentarily connecting alarm
"OFF" to VSS resets the alarm latch and thereby
voo
VSS
FIGURE 3. 50/60 Hz Input Shaping Circuit
vss
ALARM,OR SLEEP
FljoM
COMPARATOR
,
COMMON SOURCE BUS
~
VSS
~
>--i
OUTPUT
>-f
,
OUTPUT
(OPEN DRAIN)
Voo
FIGURE 4(b). Alarm and Sleep Outputs
FIGURE 4(a). Segment Outputs
1-65
W
to
-..J
l>
l>
S
S
U1
W
-'
o
to
functional description
(Continued)
TABLE I. MM5387AA, MM53~08 Display Modes
*SELECTED
DISPLA Y MODE
DIGIT NO. 1
DIGIT NO.3
DIGIT NO. 2
DIGIT NO.4
Time Display
10's of Hours & AM/PM
Hours
10's of Minutes
Minutes
Seconds Display
Blanked
Minutes
10's of Seconds
Seconds
Alarm Display
10's of Hours & AM/PM
Hours
10's of Minutes
Minutes
Sleep Display
Blanked
Blanked
10's of Minutes
Minutes
* If more than one display mode input is applied, the display priorities are in the order of Sleep (overrides
all others), Alarm, Seconds, Time (no other mode selected)'
TABLE II. MM5387AA, MM53108 Setting Control Functions
CONTROL
INPUT
SELECTED
DISPLA Y MODE
CONTROL FUNCTION
*Time
Slow
Fast
Both
Minutes Advance at 2 Hz Rate
Minutes Advance at 60 Hz Rate
Minutes Advance at 60 Hz Rate
Alarm
Slow
Fast
Both
Both
Alarm
Alarm
Alarm
Alarm
Seconds
Slow
Fast
Both
Both
Sleep
Slow
Fast
Both
Minutes Advance at 2 Hz Rate
Minutes Advance at 60 Hz Rate
Resets to 12:00 AM (Midnight) (12·Hour Format)
Resets to 00:00 (24·Hour Format)
Input to Entire Time Counter is Inhibited (Hold)
'Seconds and 10's of Seconds Reset to Zero Without
a Carry to Minutes
Time Resets to 12:00:00 AM (Midnight) (12-Hour Format)
Time Resets to 00:00:00 (24-Hour Format)
Subtracts Count at 2 Hz
Subtracts Count at 60 Hz
Subtracts Count at 60 Hz
*When setting time sleep minutes will decrement at rate of time counter, until the sleep
counter reaches 00 minutes (sleep counter will not recycle).
10
./
1-~~SD==2:V
/
1
/'
/
I2:
AM
a:
a:
:::>
u
I-
:::>
I-
/
:::>
o
,I
I
/
/
o /
o'
OUTPUT (DRAIN) VOLTAGE BELOW VSS
Switch A must be ganged with Sleep display as shown.
FIGURE 5. Typical Output Current
Characteristics of MM5387AA, MM53108'
FIGURE 6. 24-Hour Operation:
10's of Hours Digit Connections
'·66
.typical applications
Figure 7 is a schematic diagram of a general purpose alarm clock circuit (12-hour model using the MM5387 AA or
MM53108 and a 3 1/2-digit LED display.
27k
ALARM
DRIVE
UNIT HOURS
VDO 10'S OF HOURS
10'S OF MINUTES
UNIT MINUTES
II
4.7k
VOO
PM
AM
--d
LEO DISPLAY
COMMON CATHOPE
r - --;--1
l
2
~+&~~------~~---"
ovo
VLEO
SUPPLY
BRICGOH;:ig~
I
I
I OPTION I
I
IL _______
VOO
JI
FIGURE 7
'·67
'-~-1
I
I
2
I
I
~220"F
I
I .
I OPTION 2
I.
~
L_.:.
_____ JI
Clocks
MM5402, MM5405 digital alarm clocks
general description
features
The MM5402, MM5405 digital alarm clocks are monolithic MaS integrated circuits utilizing N-channel
low-threshold, enhancement mode and ion-implanted
depletion mode devices. They provide all the logic
required to build several types of clocks and timers
with up to four display modes (time, seconds, alarm
and sleep) to maximize circuit utility, but are specifically intended for clock-radio applications. Both devices
. will directly-drive 7-segment LED displays in either a
12-hour format (3 1/2 digits). with lead-zero blanking,
AM/PM indication and flashing colon, or 24-hour
format (4 digits) through hard-wire pin selection; the
timekeeping function operates from either a 50 or
60 Hz input, also through pin selection. Outputs consist
of display drivers, sleep (e.g., timed radio turn-off), and
alarm enable. A power-fail indication mode is provided
to inform the user of. incorrect time display by flashing
all "ON" digits at a 1 Hz rate, and is cancelled by
simply resetting time. The device operates over a supply
range of 7V-llV which does not require regulation.
The MM5405 is electrically identical to the MM5402,
but with mirror-image pin-out to facilitate PC board
layout When designing a "module" where the LED
display and MaS chip are mounted on the same .side;
the MM5402 is more suited for "L" shaped module
designs (vertical LED display, horizontal component
board). Both devices are supplied in a 40-lead dual-inline package.
• 50 or 60 HZ operation
• Single power supply
• 12 or 24 hour display format
•
•
•
•
•
•
•
•
•
•
•
AM/PM outputs
}
.
.
12 hour format
Leading-zero blanking
24-hour alarm setting
All counters are resettable
Fast and slow set controls
Power failure indication
Elimination of illegal time display at turn "ON"
Direct interface to LED displays
9-minute snooze alarm
Presettable 59-minute sleep timer
Available in standard (MM5402) or mirror-image
(MM5405) pin-out
applications
•
•
•
•
•
•
•
•
•
•
•
Alarm clocks
Desk clocks
Clock radios
Automobile clocks
Stopwatches
Industrial clocks
Portable clocks
Photography timers
Industrial timers
Appliance timers
Sequential controllers
block diagram
C~~~~~ 0--'23..;.(1..;81_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - .
12/2~EHL~~~
38:...::(3:;,,1_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- ,
0-.:.:
50/60 HZ
INPUT
ALARM OUT
+'0;..:.;,;;;'-------.
ALARM 0 FF 0-:;':";':';"---..,
TO HRS
DIGIT
SNOOZE
SLEEP OUT +=;;"':':'~......I
TO 10'S
OF MINS
DIGIT
SLEEP DIS o-=.:..:..:..:!....-------------------~
3
0-.:.:..;1(",10.:..;1
0-.:3:,;2(:;;.:91_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
ALARM DIS
SECONDS DIS
----------+----------+1
37(41
NC 0
33(81
SL OW SET C>--'-'---+
34 (71
FAST SET C>--'-'---+
28(131
VSS~
29(121
16-22
TO MINS
DIGIT
(19.-251
Note. MM5405 pin connections shown in parenthesis.
VOO~
FIGURE 1
1·681.';1
I
absolute maximum ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
electrical characteristics
~
(Note 1)
=
CONDITIONS
TYP
MAX
11
9
11
7
UNITS
V
V
No Output Loads
VDO = 7V
4
mA
VDD= llV
5
mA
50/60 Hz Input
Frequency
VDD = 7V to 11 V
Logical Low Level
Logical High Level
dc
50 or 60
10k
Hz
VSS
VDD-3
VSS
VSS+0.5
V
VDD
VDD
100
Input Leakage
V
JlA
All Other Input Voltages
Logical Low Level
Logical High Level
Power Failure Detect Voltage
(VOD Voltage), (Note 2)
Hold Count Voltage
VSS+0.5
VDD
V
1
5
V
7
11
V
(Note 2)
11
V
VDD=11V
Logical High, Source
VOH = VSS + 2
Logical Low, Sink
VOL = VSS + 2
Output Current Levels
V
VSS
VDD
VSS
VDD-3
Internal Depletion Load to VDD
Count Operating Voltage
Alarm and Sleep Outputs
-,
1
JlA
5
mA
VDD = 9V to llV
Output Common = VSS
Common Anode
(Figure 5a)
10'5 of Hours (b & cl. 10'5 of Minutes
(a & d)
Logical High Level, Leakage
VOH = VDD
Logical Low Level, Sink
VOL = VSS + 2V
10
JlA
mA
10
JlA
mA
10
JlA
mA
24
1 Hz Display
Logical High Level, Leakage
VOH = VDD
Logical Low Level, Sink
VOL = VSS + 2V
36
All Other Segment Displays
Logical High Level, Leakage
VOH = VDD
Logical Low Level, Sink
= VSS + 2V
VDD = 9V to l1V
Output Common = VSS + 4
Output Current Levels
Common Cath<;>de
12
VOL
(Note 1)
(Figure 5b)
10's of Hours (b & cl. 10's of Minutes
(a & d)
= VSS + 1.5V
Logical High Level, Source
VOH
Logical Low Level, Leakage
VOL = VSS
20
mA
10
JlA
1 Hz Display
Logical High Level, Source
VOH = VSS + 1.5V
Logical Low Level, Leakage
VOL
30
= VSS
mA
10
JlA
All Other Segment Displays
Logical High Level, Source
VOH = VSS + 1.5V
Logical Low Level, Leakage
VOL = VSS
~
o
~
~
7V to llV, VSS';' av, unless otherwise specified.
MIN
Output Driving Display
Functional Clock
Power Supply Current
300°C
Note 1
N
TA within operating range. Voo
PARAMETER
Power Supply Voltage
Lead Temperature (Soldering, 10 seconds)
Segment Output Current
VSS to VSS +12V
-25"C to +70"C
-65°C to +150°C
s:CJ1
mA
10
10
JlA
Note 1: Segment output current must be limited to 15 rnA maximum by user; power diSSipation must be limited to 900 mW at 70° C and 1.2W
at 25°C.
Note 2: The power-fail .detect voltage is 0.25V or more above the hold count voltage. The power-fail latch trips into power-fail mode at least
0.25V above the voltage at which data stored in the time latch is lost.
Note 3: Power supply voltage should not exceed a maximum voltage of 12V under any circumstances, such as during plug in, power up, display
"ON"/"OFF", or power supply ripple. OOin,g so runs the risk of permanently damaging the device.
'-69,"
I
CJ1
~
o
CJ1
functional description
A block diagram of the MM5402, MM5405 digital
clock radio circuit is shown in Figure 1. The various
display setting modes are listed in Table I, and Table II
shows the setting control functions. The following
description is based on Figure 1 and refers to both
devices as they are electrically identical.
Time Setting Inputs: Both fast and slow setting inputs
are provided. These inputs are applied either singly or
in combination to obtain the control functions listed in
Table II. Again, internal depletion pull-up devices
are provided; application of VSS to these pins affects
the control functions. Note that the control functions
proper are dependent on the selected display mode.
For example, a hold·time control function is obtained
by selecting seconds display and actuating the slow set
input. As another example, the clock time may be reset
to 12:00:00 AM, by selecting seconds display and actuating both slow and fast set inputs.
50 or 60 Hz Input: A shaping circuit (Figure 3) is pro·
vided to square the 50 or 60 Hz input. This circuit
allows use of a filtered sinewave input. The circuit is a
Schmitt trigger that is designed to provide about 0.8V
hysteresis. A simple RC filter such as shown in Figure 7,
should be used to remove possible line-voltage transients
that could either cause the clock to gain time or damage
the device. The shaper output drives a counter chain
which performs the timekeeping function.
Output Common: All display output drivers are open
drain devices with all the sources connected to output
common pin. This pin can be used as a common source
or a common drain. When used as a common source,
this pin is connected to VSS and when used as a common drain, this pin is connected to VOO. This allows
the use of either common anode or common cathode
LED's for displays. Figure 5 shows these connections.
50 or 60 Hz Select Input: A programmable prescale
counter divides the input line frequency by either
50 or 60 to obtain a 1 Hz time base. This counter is
programmed to divide by 60 simply by leaving 50/
60 Hz select unconnected; pull-Up to VOO is provided by an internal depletion load. Operation at 50 Hz
is programmed by connecting 50/60 Hz select to VSS.
12 or 24 Hour Select Input: By leaving this pin unconnected, the outputs for the most-significant display
digit (10's of hours) are programmed to provide a
12-hour display format. An internal depletion pullup device is again provided. Connecting this pin to'
VSS programs the 24-hour display format. Segment
connections for 10's of hours in 24-hour mode are
shown in Figure 6.
Display Mode Select Inputs: In the absence ot" any of
these three inputs, the display drivers present time-ofday information to the appropriate display digits.
Internal depletion pull-up devices allow use of simple
SPST switches to select the display mode. If more than
one mode is selected, the priorities are as noted in
Table I. Alternate display modes are selected by applying VSS to the appropriate pin. As shown in Figure 1
the code converters receive time, seconds, alarm and
sleep information from appropriate points in the clock
circuitry. The display mode select inputs control the
gating of the desired data to the code converter inputs
and ultimately (via output drivers) to the display digits.
connection diagrams
Power Fail Indication: If the power to the integrated
circuit drops, indicating a momentary ac power failure
and possible loss of clock, all "ON" segments will
flash at 1 Hz rate. A fast or slow set input resets an
internal power failure latch and returns the display to
normal.
(Top Views)
Dual-I n·Line Package
Dual-I n·Line Package
AM OUTPUT
PM OUTPUT
10 HAS -b & c
HAS -I
12/24 HA SELECT
HAS,a
10 HA b (24-HA)
HAS -"
50/60 Hz SELECT
HAS -b
50/60 Hz INPUT
HAS -d
FAST SET INPUT
AM OUTPUT
PM OUTPUT
COLON (I Hz)
10HRS-b&c
COLON (1 Hz)
HRS -I
12124 HR SELECT
HRS -g
10 HR b (24-HR)
HRS-l
50/60 Hz SELECT
50/60 Hz INPUT
HAS - b
FAST SET INPUT
HRS -d
HAS-c
SLOW SET INPUT
SLOW SET INPUT
HRS - c
HAS-.
SECOND DISPLAY INPUT
SECOND DISPLAY INPUT
HRS -.
10MINS-I
ALAAM DISPLAY INPUT
ALARM DISPLAY INPUT
10MINS-I
10MINS-g
SLEEP DISPLAY INPUT
SLEEP DISPLAY INPUT
10MINS-g
10 MINS -" & d
VDD
VDD
10MINS-a&d
10MINS-b
VSS
vSS
10MINS-b
10MINS-a
SLEEP OUTPUT
SLEEP OUTPUT
10MINS-e
10MINS-c
ALAAM "OFF"INPUT
ALARM "OFF"INPUT
10MINS-c
MINS-I
ALAAM OUTPUT
ALAAM OUTPUT
MINS -I
MINS-g
SNOOZE INPUT
SNOOZE INPUT
MINS-g
MINS-a
OUTPUT COMMClN
MINS -b
MINS-e
OUTPUT COMMON
MINS -a
MINS-c
MINS -c
MINS -b
MINS -d
MINS -d
MINS -.
Order Number MM5402N
See Package 24
Order Number MM5405N
See Package 24
FIGURE 2(a). MM5402
FIGURE 2(b). MM5405 (Mirror-Image Pin-Out)
'-70
functional description
(Continued)
Alarm Operation and Output: The alarm comparator
(Figure 1) senses coincidence between the alarm counters (the alarm setting) and the time counters (real time).
The comparator output is used to set a latch in the
alarm and sleep circuits. The latch output enables the
alarm output driver (Figure 4b) which is used to
conUol the external alarm sound generator. The alarm
latch remains set for 59 minutes, during which the alarm
will therefore sound if the latch output is not temporarily inhibited by another latch set by the snooze alarm
input or reset by the alarm "OFF" input.
silences the alarm. This input is also·returned to VOO by
an internal depletion device. The momentary alarm
"OFF" input also readies the alarm latch for the next
comparator output, and the alarm will automatically
sound again in 24 hours (or at a new alarm setting).
If it is desired to silence the alarm for a day or more,
the alarm "OFF" input should remain at VSS.
Sleep Timer and Output: The sleep output can be used
to turn "OFF" a radio after a desired time interval of up
to 59 minutes. The time interval is chosen by selecting
the sleep display mode, (Table I) and setting the desired
time interval (Table II). This automatically results, in a
current sink output which can be used to turn "ON" a
radio (or other appliance). When the sleep counter,
which counts downwards, reaches 00 minutes, a latch
is reset and the sleep output current drive is' removed,
thereby turning "OFF" the radio. This turn "OFF"
may also be manually controlled (at any time in the
countdown) by a momentary VSS connection to the
Snooze input. The output circuitry is the same as the
other outputs (Figure 4b)_
Snooze Alarm Input: Momentarily connecting snooze
to VSS inhibits the alarm output for between 8 and 9
minutes, after which the alarm will again be sounded.
This input is pulled-up to VOO by an internal depletion device. The snooze alarm feature may be repeatedly
used during the 59 minutes in which the alarm latch
remains set.
Alarm "OFF" Input: Momentarily connecting alarm
"OFF" to VSS resets the alarm latch and thereby
VOO
vss
FIGURE 3. 50/60 Hz Input Shaping Circuit
VSS
OUTPUT COMMON BUS
~
.......------.~OUTPUT
ALARM OR SLEEP
FROM
COMPARATOR
~
>--I
OUTPUT
(OPEN ORAIN)
VOO
FIGURE 4(a)_ Segment Outputs
'FIGURE 4(b). Alarm and Sleep Outputs
1-71
LO
~
functional description
(Continued)
LO
2
2
TABLE I. MM5402, MM5405 Display Modes
*SELECTED
DISPLA Y MODE
DIGIT NO.1
DIGIT NO.2
DIGIT NO.3
DIGIT NO.4
Time Display
10's of Hours & AM/PM
Hours
10's of Minutes
Minutes
Seconds Display'
Blanked
Minutes
1O's of Seconds
Seconds
Alarm Display
10's of Hours & AM/PM
Hours
10's of Minutes
Minutes
Sleep Display
Blanked
Blanked
10's of Minutes
Minutes
* If more than one display mode input is applied, the display priorities are in the order of Sleep (overrides
all others), Alarm, Seconds, Time (no other mode selected).
TABLE II. MM5402, MM5405 Setting Control Functions
SELECTED
DISPLA Y MODE
CONTROL
INPUT
CONTROL FUNCTION
*Time
Slow
Fast
Both
Minutes Advance at 2 Hz Rate
Minutes Advance at 60 Hz Rate
Minutes Advance at 60 Hz Rate
Alarm
Slow
Fast
Both
Both
Alarm
Alarm
Alarm
Alarm
Seconds
Slow
Fast
Both
Both
Input to Entire Time Counter is Inhibited (Hold)
Seconds and 10's of Seconds Reset to Zero Without
a Carry to Minutes
Time Resets to 12:00:00 AM (Midnight) (, 2·Hour Format)
Time Resets to 00:00:00 (24-Hour Format)
Slow
Fast
Both
Subtracts Count at 2 Hz
Subtracts Count at 60 Hz
Subtracts Count at 60 Hz
Sleep
Minutes Advance at 2 Hz Rate
Minutes Advance at 60 Hz Rate
Resets to 12:00 AM (Midnight) (, 2·Hour Format)
Resets to 00:00 (24·Hour Format)
*When setting time sleep minutes will decrement at rate of time counter, until the sleep counter
reaches 00 minutes (sleep counter will not recycle).
-
10 HR b (24 HR)
Voo
AM
--+--4~
--I
1 Hz
PM
1
10 HR
b&c
FIGURE 5(a). Common
Anode Application
FIGURE 5(b). Common
Cathode Application
1-72
FIGURE 6. 24-Hour Operation:
10's of Hours Digit Connections
typical applications
Figure 7 is a schematic diagram of a general purpose alarm clock circuit (12-hour model using the MM5402 or MM5405
and a 3 1/2-digit LED display_
s
sCJ'I
+:ao
o
N
s
sCJ'I
+:ao
o
CJ'I
, - - - -....-1 VSS
OUTPUT COMMON
..._ _- - - 1 ~~~~/'
MMS402 OR MMS40S
VOO
PM
il~O il~ il~O
bO
0:=0 0:=0 0:=
cD
AM
COLON
d
COMMON ANODE
r, -
2
--;--l
~~~~------~r+---"
0:::0
VLEO
SUPPL Y
I
I
I OPTION 1
I
IL _______
Voo
JI
FIGURE 7
1-7~
d
--d
-----I
1---+-,
LEO DISPLAY
1
---1
I·
2
I..
I
I
T
220pF
I
II
L_.:. _____ JI
OPTION 2
Clocks
USING NATIONAL CLOCK INTEGRATED CIRCUITS IN TIMER APPLICATIONS
INTRODUCTION
The following is a description of a technique which
allows the use of the National MM5309, MM5311,
MM5312 and MM5315 clock integrated circuits as
timers in industrial and consumer applications. What
will be presented is the basic technique along with some
simple circuitry and applications.
An easier method is to. use one or more demultiplexed
BCD lines as control waveforms whose edges determine
timer data. In Figure 1 we examine the l·bit of the BCD
data of the units second time.
From this 'waveform we observe a one second wide pulse
every two seconds. If we look at the 4-bit of the 10
minutes digit we find a pulse which is 20 minutes wide
and occurs once each hour.
BASIC TECHNIQUE
When first approaching the problem of using clock chips
for timers, the most obvious technique is to attempt to
compare the display data with preset BCD numbers.
Because of the multiplexing and number of data bits
this technique, while possible, is unwieldy and requires a
large number of components.
Figure 3 is a chart showing the various pulses and their
widths for all digits and the useful BCD lines.
UNIT SECOND
DIGIT TIME
BCD 1
FIGURE 1. 1 Second Pulse Every 2 Seconds
10 MINITE DIGIT
TIME
BCD 1
I
U
L
f - - - 4 0 M I N - + 2 0 MIN-j
FIGURE 2.20 Minute Pulse Every Hour
1-74
BCD
PULSE RATE
PULSE WIDTH
BCD
1 Sec Digit
1
2
4
8
1 every 2 sec
1 sec*
1 every 10 sec
1 every 10 sec
4 sec
2 sec
1 every 2 min
1
2
4
8
1 min*
1
4 min
2 min
4
8
Units Hrs Digit (12 Hr Model
1
2
4
8
1 every 2 hrs
1 hr*
1 every 12 hrs
1 every 12 hrs
4 hrs
4 hrs
1 every 12 hrs
1 every 12 hrs
1 every 12 hrs
10 sec*
20 sec
20 sec
1 every 20 min
1 every hr
1 every hr
10 min*
20 min
20 min
Units Hrs Digit (24 Hr Model
1
2
4
8
10 Hrs Digit (12 Hr Model
1
2
4
8
1 every 20 sec
1 every min
1 every min
10 Min Digit
2
1 every 10 min
1 every 10 min
PULSE WIDTH
10 Sec Digit
1 Min Digit
1
2
4
8
PULSE RATE
1 every 2 hrs
1 hr*
10 Hrs Digit (24 Hr Model
1
2
9 hrs
9 hrs
9 hrs
1 every 24 h rs
1 every 24 hrs
10 hrs
4 hrs
*Square waves
FIGURE 3
SIMPLE DEMULTIPLEXING
MORE COMPLEX APPLICATIONS
In the simple case where, for example, a four hour wide
pulse each day is desired, perhaps to turn on lights in the
evening, a simple demultiplexing scheme using one diode
is shown in Figure 4. When power is applied, the internal
multiplex circuitry will strobe each digit until the digit
with the diode connected is accessed. This digit will
sink the multiplex charging current and stop the multiplex scanning. Thus, the BCD outputs now present the
data from the selected digit. The waveforms as previously
discussed are presented at the BCD lines. Note that these
pulses are negative true for all BCD outputs.
Where it is desired to maintain the display, or in more
complex timing of the "10 seconds every two hours"
variety, external demultiplexing shown in Figure 6 can
be used. In this figure the BCD lines are demultiplexed
with MM74C74 flip·flops. Examining the waveforms of
these circuits we see two edges which allow the 10
. second each two hours timing. These are differentiated
by the NAND and INVERTERS and the first edge sets
and the second resets the S- R fl ip-fl op. The output of the
flip-flop is ten seconds wide every two hours. Byexamining the edges of the Figure 3 entries any combination
of timings can be obtained with the circuit of Figure 6.
An advantage of this type of timer over mechanical
types is the elimination of line power drop outs. The
circuit shown in Figure 5 will maintain timing to within
a few percent during periods of power line failure, but
automatically return to the 60 Hz line for timing as soon
as power is restored.
LOW FREQUENCY WAVEFORM GENERATION
The asterisked BCD lines in Figure 3 are those waveforms which are symmetric. By the use of the simple
diode demultiplexing scheme previously discussed we
1-75
Vss
0.01
MUX
....---4_-1 TIMING
INPUT
lOOk
}
DIGIT
LINE
BCD LINES
FOR SELECTED
DIGIT
Voo
FIGURE 4
lN914
11=
RElAY
OUTPUT
ENABLE
Vss
. MM5J09
1M
lOOk
SET TO
60 Hz
WITH LINE
UNCONNECTED
FIGURE 5. Fail-Safe Automatic Lights Timer. Four Hours Each 24 Hours
circuits. Because of the vast number of timing applications possible,this can in no way be looked at as the
limit of clock-timer circuits. Use of the Reset on the
MM5309 and MM5315 or the use of clocks in conjunction
with programmable counters such as the MM74C161
allows other possibilities to meet specific applications.
Also the clock chips themselves can run on frequen'cies
other than 50 or 60 Hz (actually from de to 10 kHz)
which can allow scaling of the waveforms presented in
Figure 3 to different timing rates.
easily obtain square waves with periods of two seconds,
two minutes, twenty minutes and two hours. In other
cases, where the waveforms are asymmetric, a simple
flip-flop can square, while dividing by two, these waveforms producing other low frequency square waves as
long as one per two days.
SUMMARY
We have shown some simple low cost timer and waveform
generating examples using National clock integrated
1-76
BCOI---4~~
1/2MM14C14
10k
A
MM14C04
OUT
ill
~----------~------------~~
aAJr----J
_ __
.-1
2HRSWIOE-------
as
--l
OUT
!--10SECWIDE
n
Jr----J
I~R-E-SU-L-TA-N-T-l0-S-E-CE-V-E-RY-2-H-R-S------------~1l
FIGURE 6. More Universal Demultiplexing Technique
1-77
Counters/Timers
MM5307 baud rate generator/programmable divider
general description
The National Semiconductor MM5307 baud rate
generator/programmable divider is a MaS/LSI P-channel
enhancement mode device. A master clock for the device
is generated either externally or by an on-chip crystal
oscillator (Note 4). An internal ROM controls a divider
circuit which produces the output frequency. Logic
levels on the four control pins select between sixteen
output frequencies. The frequencies are chosen from
the following possible divisors: 2N, for 3
N
2048;
2N + 1 and 2N + 0.5 for 4 -:; N -:; 2048. AI~o on-; of the
sixteen frequencies may be gated from the external
frequency input. The MM5307 AA is supplied with the
divisors shown in Table I.
< <
•
External frequency input pin
•
Internal. ROM allows generation of other frequencies
on order
•
Bipolar compatibility
•
0.01 % accuracy (typ) exclusive of crystal
•
1 M Hz master clock frequency
applications
features
•
DAR/T clocks
II
On-chip crystal oscillator
•
System clocks
•
Choice of 16 output frequencies from 1 crystal
•
Electrically programmable counters
schematic and connection diagrams
A
ROM
Dual·1 n-Line Package
EXTERNAL FREO.
NC
PROGRAMMABLE
OIVIDER
RESET
OUTPUT
r
"-------l
¢1
¢2
--«
________
L.
OUTPUT
vss
EXT.
FREO.
EXTERNAL
CLOCK
5
CRYSTAL
"">---.....
EXTERNAL
CLOCK
90 UT
CRYSTAL
>r---+'
TOP VIEW
Order Number MM5307N
See Package 18
\
2-2
absolute maximum ratings
Voltage at Any Pin With Respect to VSS
+O.3V to VSS - 20V
700mW
o
-65°C to +150
o
DoC to +70
Power Dissipation
e
e
Storage Temperature Range
Operating Temperature
Lead Temperature (Soldering, 10 seconds)
300°C
dc electrical characteristics
T A within operating range, VSS = 5V ±5%, V GG = -12V ±5%, unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
All Inputs (Except Crystal Pins)
VIH
Logical High Level
VSS--l.5
VSS+0.3
V
VIL
Logical Low Level
VSS-18
VSS-4.2
V
Leakage
VIN
= -10V,
TA
= 25°C,
0.5
/1A
7.0
pF
All Other Pins GND
Capacitance
VIN
= OV, f = 1 MHz,
All Other Pins GND, (Note 1)
40%
External Clock Duty Cycle
Capacitance Measured Across
f
= 1 MHz,
60%
(Note 3)
5.0
pF
VSS-4.6
V
Crystal Pins
Output Levels
= -0.5
= 1.6 mA
VOH
Logical High Level
ISOURCE
VOL
Logical Low Level
ISINK
IGG
Power Supply Current
f
PARAMETER
CONDITIONS
MIN
0.01
CL = 50 pF, (Note 2)
tRD
Reset Delay Time
f
RpW
Reset Pulse Width
tOD
Output Delay From Reset
TYP
MAX
UNITS
1.0
MHz
16
= Master Clock Frequency
T
= Output Period
0.5T-l/f
/1S
500 + 4/f
ns
500 + 4/f
ns
ns
500 + 4/f
± l/f
mA
unless otherwise specified.
Access Time
Output Duty Cycle = 0.5T
V
VSS
35
Master Frequency
tA
VSS-2.6
= 1 MHz
ac electrical characteristics
= 5V ±5%, V GG = -12V ±5%,
T A within operating range Vss
mA
O.5T+l/f
f = Master Frequency
Note 1: Capacitance is guaranteed by periodic measurement.
Note 2: Access time is defined as the time from a change in control inputs (A, B, C, D) to a stable output frequency. Access time is a function of
frequency. The following formula may be used to calculate maximum access time for any master frequency: T A = 2.8Jls + llf x 13, f is in MHz.
Note 3: The MM5307 is designed to operate with a 1 MHz parallel resonant crystal. When ordering the crystal a value of load capacitance (Cl)
must be specified. This is the capacitance "seen" by the crystal when it is operating in the circuit. The value of Cl should match the capacitance
measured at the crystal frequency across the crystal input pins on the MM5307. Any mismatch will be reflected as a very small error in the
operating frequency. To achieve maximum accuracy, it may be necessary to add a small trimmer capacitor across the terminals.
Note 4: If the crystal oscillator is used Pin 5 (external clock) is connected to VSS. If an external clock is used Pin 7 is connected to VSS.
2·3
control table
Input Freq: 921.6 kHz Master Clock
NOMINAL BAUD RATES
CONTROL PINS
(OUT~UT
FREQUENCY/16)
A
B
C
D
AA
AB
FAG
0
0
0
a
0
1
1
0
1
0
1
50
75
110
134.5
150
300
600
900
1200
1800
2400
3600
4800
7200
9600
50
200
110
134.5
150
300
600
900
1200
1800
2400
3600
4800
75
9600
50
75
110
134.5
150
300
600
1050
1200
45.5
2400
56.9
4800
66.7
9600
" 0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
a
0
0
a
1
1
1
1
a
a
1
1
0
0
1
1
0
0
1
1
0
a
1
0
1
0
.1
0
1
a
1
a
1
a
DIVISOR
FORAA
1152
768
524
428.5
384
192
96
64
48
32
24
16
12
8
6
EXTERNAL FREQ
Positive Logic: 1 = VH
O=VL
typical appliGations
Internal Oscillator
External Clock
EXT FREU--+--~
EXT
FREQ---'-~
NC
14 100 ppm tuning range
when used with standard crystals trimmed for C L =
12pF. Tuning to better.than ±2ppm is easily obtainable.
2-8
functional description (cant.)
OSCIN-
-------
110
100
90
-OSCOUT
)(
RI
20M
>
'"c
*:::::1k
0
:;:
Q
C2
30pF
VOO OR VSS
80
70
60
50
1
if
t-"S~AND~RD" ~M53~9N- ~ I----/
L'"
V
40
30
20
10
V
-~
0
10
I
FIGURE 3. Crystal Oscillator Network
20
30
-
40
V
[Z
I---"
50
60
FIGURE 4. Plot of Divide·By Vs Duty Cycle
FIGURE 5. Clock Radio Circuit with Battery Back·Up
2.5
2.0
E 1.5
.-J
!::!
0
0
1.0
~
26875
I
I
32.784
I
COUNTS - - I - - - - - COUNTS - - -
f-o-~-----59.659COUNTS-------1·
0.5
MHz
FIGURE 6. Typical Current Drain Vs Oscillator Frequency
70
DUTY CYCLE (%1
FIGURE 7. Output Waveform for Standard MM5369
*To be selected based on xtal used
2-9
CO'unters/Timers
For additional application information, see
AN-168 and AN-169 at the end of this section.
MM5865 universal timer
general description
features
The MM5865 Universal Timer is a monolithic MOS
integrated circuit utilizing P-channel low-threshold,
enhancement mode and ion-implanted depletion mode
devices. The chip contains all the logic required to
control the two 4-digit counters, blank leading zeros,
compare the two counters and to cascade with another
MM5865. Input pins start, stop, reset and set the
counters, determine which of the 7 functions is performed, the resolution of the display (0.01 sec, 0.1 sec,
1 sec, or external clock) and what modulo the counters
divide by. Outputs include the comparator output,'
multiplexed BCD outputs and digit enables. The BCD
outputs interface directly with MM14511, a BCD to
, 7-segment decoder, which interfaces with a LED display.
The digit enable outputs of 2 cascaded. MM5865's
interface directly with a DM8863 LED 8-digit driver.
A 058877 or 0575492 Hex Digit Driver may be used
with a single MM5865. The digit enable outputs interface directly with a DM8863; a LED digit driver. The
7 functions include start-stop with total elapsed time,
start-stop with accumulative event time, split, sequential
with total elapsed time, rally with total elapsed time,
program up count and program down count. The circuit
uses a 32.8 kHz crystal or an external clock and is
packaged in a 40-lead dual-in-line package.
'applications
•
•
Stop watch
Kitchen timer
•
•
Oven timer
Event timer/counter
•
•
•
Rally timer
Navigational timer
Industrial timer/counter
•
Function 1: Standard Start-Stop with total elapsed
time memory
•
Function 2:'Standard Start-Stop with total acc'umulative event time
•
Function
memory
•
F,unction 4: Standard split
•
Function 5: Rally with total elapsed time memory
II
Function 6: Programmable
upon command
•
II
Function 7: Programmable down count
Comparator output
101
Crystal controlled oscillator (32.8 kHz)
3: Sequential
up
•
External clock input (option)
•
Provides external clock
total
count.
Repeatable
•
Select resolution
Select count up or down
•
Select modulo 6 or 10 for digits 2, 3 and 4
iii
Blanking between digits
II
Leading-zero blanking
•
Multiplex rate output
time
•
External multiplex rate input (option)
II
Can be cascaded
•
Waiting state indicator
•
II
Simple interface to LED display
Elimination of illegal time display at turn-on
•
Wide power supply range 7V-20V
Dual-I n-Line Package
PROGRAM
DIGITS 1-4
CONTROL
ClOUT
DIVIDE
SCALER
DIVIDE SCALER I
40 Vss
DIVIDE SCALERZ
39 PROGRAM OIGIT 1/
31 LATCH CONTROL
PROGRAM DIGIT Z
DIVIOESCALER 1
FUNCTIONS
1-1
COMPARATOR ENAIlE
CONTROL
CIIN-
elapsed
•
block and connection diagrams
BCD
OUTPUTS
CONTROL
LOGIC
PRDGRAMDIGIT3
36 PROGRAM DIGIT 4/
FUNCTION I
35
34
FUNCTlDNZ
DIGIT
OUTPUTS
CON~~~~_
RESET_
STARTISTDP_
FINAL EVENT--+
CONTROL
CZ OUT
COMP~:~~~-L....._-r-_---'
-+_--I
MULTlP~~~ _ _ _ _
FUNCTlDNl
~OA~~~DGL Sgl~E
CONTROL ClOUT
FUNCTION 4
BCD I
FUNCTION 5
BCDZ
FUNCTION 8
BCD4
FUNCTION 1
FINAL EVENT STOP/ IZ
COMPARATOR OUT 13
RESET
STARTISTOP 14
15
CLOCK IN/OUT
RESOLUTION SElECT I
MULTIPLEXIN-----1I---t-L_ _-.l
RESOLUTION SElECT Z
BLANKING
Vss_
V
with
_
OSC IN
OD
OSC OUT
I~~~~~ ------<>-------i
CONTROL CZIN
Z3 MULTIPLEX IN
ZZ
MULTIPLEX OUT
ZI
19
ZO
Voo
BLANKING
TOP VIEW
Order Number MM5865N
See Package 24
RESOLUTION..:I-----------I
SELECT..:.Z_ _ _ _ _ _ _ _ _ _ _ _- '
FIGURE 2.
FIGURE 1.
2-10
absolute maximum ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Vss + 0.3V to Vss - 25V
-25°C to +70°C
-65°C to +150°C
300°C
electrical characteristics
T A within operating range, 7V -::; Vss -::; 20V, Voo = OV, unless otherwise specified.
PARAMETER
100
CONDITIONS
MIN
TYP
7
15
mA
dc
32.8
80
kHz
Power Supply Current
Input Frequency at OSC IN
Multiplex Frequency
UNITS
dc
0.4
80
kHz
dc
0.8
10
kHz
Vss = 7V
dc
0.1
10
kHz
Vss = 10V
dc
100
kHz
Voo
Vss-l
V oo +l
V
Vss
V
}VSS210V
Blanking Frequency
Clock Frequency
MAX
Input Levels
Input Logic Low
Internal Resistor
Input Logic High
-lOOk to Voo
OUTPUT CURRENTS
Digit and BCD Outputs
Source Current
Sink Current
Blanking Output
Source Current
Sink Current
Multiplex Output
Source Current
Sink Current
Clock Output
Source Current
Sink Current
Control Cl, C2 Outputs
Source Current
Contr~Cl,C2lnpuu
Sink Current
Comparator Output
Source Current
Sink Current
Waiting State Indicator
Source Current
Sink Current
= 7V
= Vss -2V
V OUT = Vss - 6.3V
1
mA
1
IlA
= 7V
= Vss V OUT = Vss -
2V
1
mA
6.3V
1
Il A
= 7V
= Vss V OUT = Vss -
2.5V
500
IlA
6.3V
8
IlA
= 7V
= Vss -4V
V OUT = Vss - 6.3V
10
IlA
5
IlA
500
IlA
8
Il A
1
mA
1
IlA
2V
1
mA
6.3V
1
IlA
Vss
V OUT
Vss
V OUT
Vss
V OUT
Vss
V OUT
= 7V
= Vss - 2.5V
Vss = 7V
V 1N = Vss - 6.3V
Vss = 7V
V OUT = Vss - 2V
V OUT = Vss - 6.3V
Vss
V OUT
= 7V
V OUT = Vss V OUT = Vss VS$
2-11
functional description
A block diagram of the MM5865 Universal Timer is
shown in Figure 1. A connection diagram is shown in
Figure 2. Unless otherwise indicated, the following
discussions are based on Figure 1.
Voo to Vss switches the display from counter 2.10
counter 1. Repetitive Start·Stop transitions switch the
display between counter 2 and counter 1.
Function 1
Function 2
In Function 1, counters 1 and 2 count up beginning
with a transition on the Start·Stop pin from V DO to
Vss. Counter 2 is shown counting. A second transition
from Voo to Vss on the Start·Stop pin inhibits the
clock pulses to counter 2, stores and displays the con·
tents of counter 2. Counter 1 continues to count. The
third transition from Voo to Vss on the Start·Stop
pin resets counter 2, enables clock pulses to counter 2
and· displays counter 2 counting. Subsequent Start·
Stop transitions repeat this sequence, all this time
counter 1 continues to count. At the conclusion of
the last event to be timed, a Final Event Stop transition
from Voo to Vss inhibits the clock to both counters
and displays counter 2. A Start·Stop transition from
In Function 2, counter 1 and 2 count up beginning with
a transition on the Start·Stop pin. Counter 2 is displayed
counting. A second transition on the Start·Stop pin
inhibits the clock pulses to both counter 1 and counter
2, stores and displays the contents of counter 2. The
third transition on the Start·Stop pin resets counter 2,
enables the clock to both counters and displays counter
2 counting.· Subseque'nt Start·Stop transitions repeat
this sequence. At the conclusion of the last event to be
timed, a Final Event Stop transition. inhibits the clock
to both counters and displays counter 2. A Start·Stop
transition switches the display from counter 2 to
counter 1. Repetitive Start·Stop transitions switch the
display between counter 2 and counter 1.
POWER·ON
RESET
fORCESTO--+
THIS STATE
r------..;~
fiNAL
EVENT
STOP
NO
NO
YES
'--------'
NO
Flow Chart for Function 2
Flow Chart for Function 1
2-12
functional description (con't)
Function 3
Function 4
In Function 3, counter 1 and 2 count up beginning with
a transition on the Start·Stop pin. Counter 2 is displayed
counting. A second transition on the Start·Stop pin
stores and displays the contents of counter 2, resets
counter 2, and initiates a new up·count in counter 2;
however, the new up·count is not displayed. Counter 1
continues to count. A transition on the Latch Control
pin will display counter 2 counting until another transi·
tion on the Start·Stop pin. A Final Event Stop transition
inhibits the clock pulses to both counters 1 and 2 and
displays the contents of counter 2. A Start·Stop transi·
tion after the Final Event transition switches the display
from counter 2 to counter 1. Repetitive Start·Sto"p
transitions switch the display between counter 2 and
counter 1.
In Function 4, counter 2 counts up beginning with a
transition on the Start·Stop pin. Counter 2 is displayed
counting. A second transition on the Start·Stop pin
stores and displays the contents of counter 2. Subse·
quent Start·Stop transitions update the display. of
counter 2. A transition on the Latch Control pin will
display counter 2 counting until a transition on the
Start·Stop pin. A Final Event Stop transition inhibits the
clock pulses to counter 2 and displays the contents of
counter 2.
POWERON
Flow Chart for Function 3
Flow Chart for Function 4
2·13
functional description (con't)
Function 5
Function 6
In Function 5, counter 1 and 2 count up beginning with
a transition on the Start-Stop pin. Counter 2 is displayed
counting. A second transition on the Start-Stop pin
inhibits the clock pulses to counter 2, and the contents
of counter 2 are displayed. Counter 1 continues counting. The third Start-Stop transition enables the clock
pulses to counter 2 and counter 2 is displayed counting.
Subsequent Start-Stop transitions repeat this sequence,
all the time counter 1 continues counting. At the conclusion of the last event to be timed, a Final Event Stop
inhibits the clock pulses to both counters 1 and 2, and
displays counter 2. A Start-Stop transition switches
the display from counter 2 to counter 1. Repetitive
Start-Stop transitions switch the display between counter
2 and counter 1.
In Function 6, counter 1 is displayed at power-on or
reset. Counter 1 is set to a specific count by Program
Digit 1-4 pins. Then the comparator is enabled. Counter
2 is displayed counting up beginning with a transition
on the Start-Stop pin. When counter 2 is coincident with
counter 1, the clock pulses to counter 2 are inhibited,
the contents of counter 2 are displayed and the Comparator Output is enabled. Upon the transition of Reset,
,counter 1 is again displayed with the time that was set,
and the Comparator Output is disabled. Counter 1 can
be reprogrammed by the Program Digit 1-4 pins if
desired. A Start-Stop transition repeats the sequence.
If the Comparator Output pin is connected to the
Reset pin, Automatic Reset will occur; however,this
connection must be broken during digit programming.
POWER-ON
'---------'
NO
Flow Chart for Function 5
Flow Chart for Function 6
2-14
s:
s
functional description (can't)
(J'1
CO
Function 7
en
(J'1
Stop to affect the counters, it must be held to V ss,
a logic one. Logic zero results when the pin is tied to
V DO or left floating (internal pull-Up to V DO).
In Function 7, counter 1 is displayed all the time.
Counter 1 is set to a specific count by Program Digit
1-4 pins. Then the comparator and Control C1 In
are enabled. Pin 4 and pin 35 must be floating or con·
nected to V DO during digit programming. Counter 1
counts down from the set count beginning with a
transition on the Start-Stop pin. When counter 1 counts
down to zero, the clock pulses to counter 1 are inhibited and the comparator Output is enabled. This is not
repeatable without setting a new count into counter 1.
The comparator and Control C1 In must be inhibited
and a reset pulse must occur before the new count
may be entered.
Final Event Stop/Comparator Output
This pin is used to indicate to the circuit that no more
events will be timed or counted. Final Event Stop affects
the circuit when it is held to Vss. There is an internal
pull-Up to V DD • This pin is also an output pin, Vss
indicates comparison between the two counters.
Divide Scale Inputs
.,.
These three inputs are used to determine whether the
counters will count in Modulo 6 or Modulo 10. Table I
shows the code for which digit will count in Modulo 6
or Modulo 10. A logic one is when the pin is held to
Vss. When the pin is tied to V DD or left floating (inter-'
nal pull-up to V DO), a logic zero results.
TABLE I. Divide Scaler Code
DIVIDE
SCALER
COUNTER 1
COUNTER 2
1
2
3
D4
D3
D2
D1
D4
D3
D2
D1
0
0
0
10
10
10
10
10
10
10
10
1
0
0
6
10
10
10
6
10
10
0
1
0
10
6
10
10
10
10
6
10
10
1
1
0
10
10
6
10
10
10
6
10
0
0
1
10
10
10
10
10
10
10
10
1
0
1
10
10
10
10
6
10
10
10
0
1
1
10
10
10
10
10
6
10
10
1
1
1
10
10
10
10
10
10
6
10
Comparator Enable
This input enables the comparator. To enable the comparator, the pin is held to Vss or logic one. To disable
the comparator, the pin is tied to V DD or left floating
(internal pull-up to V DO).
Resolution Select Inputs
L..-_ _
~_--'
These two inputs are used to select the frequency of the
clock pulses to the counters, Table II shows the code for
each frequency. A logic one is when the pin is held to
Vss. A logic zero results when the pin is tied to V DD or
left floating (internal pull-up to V DD).
NO
Flow Chart for Function 7
Reset
TABLE II. Resolution Select Code
This input will reset all logic and counters in Functions
1-5 and Function 7. In Function 6, Reset will reset
logic but not counter 1. Reset is internally pulled to
V DD , or a logic zero. For a reset to occur, the Reset pin
must be held to Vss , a logic one.
RESOLUTION
SELECT
1
2
Start-Stop
This input is used to control the counters. How it affects
the counters is explained in each function. For Start2·15
0
0
0
1
1
1
0
1
FREQUENCY
OF CLOCK TO
COUNTERS
DISPLAY
RESOLUTION
100 Hz
10 Hz
0.01 sec
0.1 sec
1 Hz
External
1 sec
functional description (con 't)
Clock In/Out
plex Output pin is four times the internal multiplex
rate. To use the MUltiplex Output pin, the Multiplex
Input pin must be tied to Voo. The Multiplex Input
must b~ used if the oscillator pins are not used. If the
Multiplex Input pin is used, OSC IN, OSC OUT and the
blanking output are not used.
This pin is either an input or output depending on the
code at the Resolution Select inputs. If the pin is used as
an output pin, it will output the clock frequency the
Resolution Select inputs have selected. When used as an
input, an external clock is used to clock the counters.
Control C1, C2 In and Control C1, C2 Out
Blanking Output
These four input pins are used to cascade two chips
together. When the Control C1 In pin is floating (internal pull·up to V oo ) or tied to V oo , the clock pulses to
counter 1 are inhibited. When Control C1 In is at Vss ,
counter 1 is enabled. Control ClOut is at Vss when
counter 1 is at it s maximum count, and it is floating
at all other times. The Control C1 In pin must be
floating (or connected to V DO) while digit programming in Function 7. Control C2 pins operate on counter
2 in a similar manner.
This output is used to blank the display at the beginning
and end of each digit time to allow for internal delay
between two cascaded chips, see Figure 3. The display
is blanked when the Blanking Output is at V DO.
i------1Dms-----+-+_
DIGITI Vss
CHIP 1 Voo
DIGIT 1
CHIP2
DIGIT2
CHIP 1
DIGIT2
CHIP2
_______~r_lL________________~1
DIGIT 3
CHIP 1
____________
DIGIT 3
CHIP2
______________~r_l~_______________
DIGIT 4
CHIP 1
______________~r_l~__________
~r_lL
===
Program Digits 1-4
_________________
These four input pins are used to program or set any
count desired in counter 1 in Functions 6 and 7. When
Program Digit 1 is at Vss, the least significant digit of
counter 1 advances at a 2.5 Hz rate. There is no carryover from digit to digit. Program Digit l.has no effect if
tied to V DO or left floating (internal pull-up to V DO).
Only one Program Digit input may be held to Vss at'
a time.
""'''~
CHIP2
BLANKING Vss
OUTPUT Voo
~
1.25ms
Program Digit 1/Latch Control
1
~LL
o.03ms:
r
This input has two functions; besides setting a count in
digit 1 of counter 1 in Functions 6 or 7, it also affects
Functions 3 and 4. In Functions 3 and 4, this input
allows the display to show counter 2 counting as described in FU.nctions 3 and 4.
D122ms
FIGURE 3. Blanking Output
Oscillator In and Out
Program Digit 4/Waiting State Indicator
A quartz crystal, resonant at 32.8 kHz, two capacitors
and one resistor, together with the internal MOS circuits
form a crystal controlled oscillator as shown in Figure 4.
Varying one of the capacitors allows precise frequency
settings. For test purposes, OSC IN is the input and OSC
OUT is the output of an inverting amplifier.
This input besides setting a count in digit 4 of counter 1
in Functions 6 and 7, also indicates that the chip has
been reset and is in the stand-by mode at power-on. In
Functions 1-5, the Waiting State Indicator is at Vss
until a Start-Stop transition has occured .. Once a StartStop transition has occured, the output remains at Voo.
Vss
Leading Zero Blanking
In Functions 1-5, leading zeros are blanked for both
counters 1 and 2. In Functions 6 and 7, counter 2 has
leading zero blanking. At power-on, the display is blank
in Functions 1--5, and all zeros are displayed in Func·
tions 6 and 7.
Output Circuits
FIGURE 4. Crystal Oscillator
Multiplex Input and Output
The Multiplex Input pin allows an external multiplex
rate to be used in the chip. The multiplex rate inside the'
chip is one fourth the MUltiplex Input and Multiplex
Output rate. When using the Multiplex Input .pin, the
Multiplex Output pin must be tied to Vss. The Multi-
2-16
For BCD and Digit Outputs, Vss is a logic one. Figure 5
illustrates the circuit used for all outputs except for
Control C1, C2'Out. The Control C1, C2 Out circuit is
illustrated in Figure 6. Figure 7 illustrates the simple
interface needed for an 8-digit stop-watch. Figure 8
illustrates the MM5865 being used to count how many
events occur in a specified time. Figure 9 shows the
MM5865 as a simple industrial counter when the input
clock is a constant frequency above 400 Hz.
functional description (can't)
a(DATA)~~VSS
~
",",,,,o---(>---1~"
OUTPUT
PAD
~CONTRDLCI
OUTPUT
VDD
FIGURE 5. Output Circuit
.
.
I
9
,---b
,.-c
,.-d
.--
FIGURE 6. Control ClOut Circuit
.II]
II
II. II: :'
I
I.
[
:II
I
:II
It
J] lr
J
[
"ll
:1:
I
II
I]:
l] ~~.=~
I] IL.-JU
I:.
J
:1]
D.P.
L
150
(1)
,---9
n16
MM14511
~
tJ
DM8863
I
L
10
n18
I
500
I
I
I
(1
8
I
9
2N3904
I
GND
40
30
II
+10V 0 - - - -
I
121
4°LlI
MM5865
I I
11
1101
I
30
I I
20
1
1
1
I I
1101
L-
~---(/
2
3
4
5
---L.,FINAL
EVENT
f---o
f---o
---L., RESE T
---L., ST ART!
STOP
~2-J
I
DISPLAY
INHIBIT
11121
MM5865
FUNCTION 1
~
1
LATCH
~
rCONTROL
~
6-25pF-
~~r
~25PFT
I
FIGURE 7. Stop Watch Application
2·17
Di,pl.vread,12h 34m 56.18,
Maximum tim. 99h 59m 99,
Decimal point indicates waiting state
I
II
120
LO
(0
(Xl
functional description (con 't)
LO
~
~
EVENT
TIME
.
I
9
~ ~~~ ~~~ rr----9ab
~ ~~
r--'
b
~ ~~~ ~~~
-c
r-d
-e
~ :~
r-r-- c
r-- d
r--.
J~,
LL
150
(7)
116
I
9
MMI4511
L
1
1118
,I
OMB863
I
8
fo10
I
9
11
I-
r
I
I
PROGRAM
DIGIT
---L- 4
~---L-3
~
~o--1..-1
GNO
~I
I
+10V 0 - -
If
30
I
J
1
I
40
ZI
140"
II
I
I
MM5865
1
I I I I I
I
101
I
30
Ilzl
MM5865
"ll
ZO
111
I II I II
1101
f-f---
I
~COMP
~
f--o--1..- RESET
~
--L START/STOP
EVENT
(CLOCK IN)
,-Display 15 events have occured in 1 minute
Maximum.venl,99.999.999
Maximum Time 99m 59s
ZOM
6-Z5pF -::
HO~
F
Z5 PF
T
FIGURE 8. Application of MM5865 to Count Events in a Specified Time
2-18
1
I I Izo
functional description (con't)
.
.
1
9
;---b
r----- c
r-- d
~ c=J~ =~
~ ~: :~
~=~
150
(7)
I
1 18111111111
9
116
MM14511
.....- 1~
_-.J 1
f-U8
9
'I
'-----
GNO
<10V
1401
I I
III I
Itlr-t-k-
30
MM5865
111
CLOCK
I I I I I
1
I 1I
10
I
~(
L/,
I
OM8863
I
I I
120
1
RESET
Oisplav readsa count 01 1234
Maximum count 9999
START/STOP
FIGURE 9. Industrial Cou~ter
2·19
I
Counters/Timers
MM53107 17-stage oscillator/divider
general description
features
The MM53107 is a low threshold voltage CMOS
integrated circuit with 17 binary divider stages that can
be used to generate a precise 60 Hz reference from a
2.097152 MHz quartz crystal. An internal pulse is
generated by the combinations of stages 1-4, 16 and
17 to set or reset the individual stages. The number
the circuit will divide by is 34,952. The MM53107 is
advanced one count on the positive transition of each
clock pulse. One buffered output is available: the 17th
stage 60 Hz output. The MM53107 is available in an
8-lead dual-in-line epoxy package.
•
•
Divides by 34,952
Input frequency-2.097152 MHz
•
Output frequency-60 Hz
•
Crystal oscillator
•
High speed (2 MHz at VDD = 2.5V)
•
Wide supply range 2-6V
•
Low power (0.5 mW
•
Fully static operation
•
8-lead dual-in-line package
block and connection diagrams
@
2 MHz/2.5V)
Dual-In-Line Package
VDD
NC
DSC OUT OSC IN
DIVIDER
OUTPUT
MM53107
t
VDD
FIGURE 1
DIVIDER
VSS
NC
NC
(60 Hz)
OUTPUT
TOP VIEW
FIGURE 2
typical performance characteristics
Order Number MM53107N
See Package 17
Typical Current Drain vs
Oscillator Frequency
600
550
u
I-
ct
~
.3
c
c
500
450
400
350
300
250
200
150
100
.50
0
'VDD (V)
2·20
absolute maximum ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Package Dissipation
Maximum VCC Voltage
Operating VCC Range
Lead Temperature (Soldering, 10 seconds)
-o.3V to VCC + 0.3V
O°C to +70°C
-65°C to +150°C
:.500 mW
6V
2.5V to 6V
. 300°C
electrical characteristics
T A within operating temperature range, VSS = Gnd, 2.5V":; VDD":; 6V unless otherwise specified.
PARAMETER
MIN
CONDITIONS
Quiescent Current Drain
VDD=6V
Operating Current Drain
VDD= 2.5V, fiN = 2.1 MHz
Frequency of Oscillation
VDD=6V
dc
dc
Logical "1 .. Source
VDD = 4V,
100
Logical "0. " Sink
VOUT = 2V
100
VDD=6V
10 = 10 /1A
5.0
VDD=2.4V
Output Current Levels
Output Voltage Levels
Logical "1"
Logical "0"
functional description
A connection diagram for the MM53107 is shown in
The. network shown provides> 100 ppm tuning range
when used with standard crystals trimmed for CL =
12 pF. Tuning to better than ±2 ppm is easily obtainable.
Figure 2 and a block diagram is shown in Figure 1.
DIVIDER
A pulse is generated when divider stages 1-4, 16 and 17
are in the correct state. This pulse is used to set or reset
individual stages of th.e counter, the modulus of the
counter is 34,952.
TIME BASE
A precision time base is provided by the interconnection
of a 2,097,152 Hz quartz crystal and the RC network
shown in Figure 3 together. with the CMOS inverter/
amplifier provided between the Osc In and the Osc Out
termi nals. Resistor R 1 is necessary to bias the inverter
for class A amplifier operation. Capacitors Cl and C2
in series provide the parallel load capacitance required
for precise tuning of the quartz crystal.
OSCIN- - - -
-
-- -
-
-
OUTPUT
The Divide Output is the input frequency divided by
34,952. The output is a push-pull output. A typical
application of the MM53107 is shown in Figure 5.
- - -:- -OSCOUT
""
Rl
20M
e - - - - - tJ
-~ Cl
-r-
5-36 pF
1
',lk
2.168
--11 : : :
1...._ _ _ _ _
32_.78_4_ _ _
0 I~--...~
T
2.0~7.152IHZ
CL
:
=
12 pF
- - C2
30 pF
VDDDRVSS~.----------------------~
*To be selected
. based on the crystal used
FIGURE 3. Crystal Oscillator Network
FIGURE 4. Duty Cycle
2-21
functional description
(Continued)
12V
VOO
VOO
8
60 Hz
20
VOO
20M
--1...
MM53107
--+
HOLO
19
....L
3V
Ox
--+ 18
SET HRS
241+~--------:"-.,
231+0~y_ _ _ _ _ _ _ _- - ,
--1...
L...-_ _ _ _ _ _ _ _ _-.VSS
221..,.O-"Z_ _ _ _ _ _ _- - ,
SETMINS
17
MANUAL TV "ON"·
14
MANUAL TV "OFF"
15
DISPLAYSELECT
16
9V
MM53100
12V
ENABLE
STANDBY
12V
TV"ON"
OUTPUT
50/60 Hz
""O---"S.;.;EL;.;;.EC;;.;.T---\ 21
AUTO "ON"
OUTPUT
PERIOD
"'<>....;.;SE..;.;LE;.;,CT.;.;X~ 11
NORMALL Y
HARO WIREO
FOR EACH
APPLICATION
VIEW PERIOD
PULSE OUTPUT
PERIOD
SELECT Y
"""0-"';;;';';;';;'--112
13
9V
VSS
9V
Note. VSS of MM53107 and
MM53100 are common.
VDD
6.Bk
15
I---'lMr--I
VIOEO
OUTPUT
..nnn..
18
0:OV
r--------,
12V
HORIZ.
6.8k
J1J1 r-----...,..,.,.,.=,-----....;.;;.;~12
13
MM5840
.,,""""
).'
19 "'V""E""RT'"".- -.....- - ,
2k
~:18
CHANNEL
UNITS
{
~
>------t 22
> - - - - - - \ 23
>------\24
1 6 1 - - - - - - 4 . . -.........- - . HORIZONTAL
POSITION
>-----125
17
20
CHANNEL [ :
TENS
:======:::
4 >------1
1--4-JVt.'fv--e ADJ.
t-.... VERTICAL
I---~~. .
POSITION
21
I -....._~'V-.... ADJ.
28
12V
.
DIGIT SELECT
8>------1
G1~~ ~g~ ~:g:~:~
> -_ _ _
..
~:.:----r-
MODE CONTROL12V ;~; FCOH:~~!~:~~ OT~~~ > -_ _ _ _ _ _ _ _- - '
FIGURE 5. Typical Application TV Channel and Time Display
e_'
,
2.22
Counters/Timers
MM5865 Universallimer Applications
introduction
A single chip universal counter and timer is now available
from National Semiconductor Corporation through
distributors of their products.
Therefore, one or two MM5865s along with two other
integrated circuits and a 4- or 8-digit display may be
used in the following applications:
The MM5865 universal timer contains, in one 40'pin
package, two 4-digit count.ers, oscillator, 18-stage divider,
multiplexer, and all the logic required to control the
counters, blank leading zeros, compare the two counters,
program one of the counters, and cascade two MM5865
integrated circuits.
1. Photographic enlarger timer, with each digit individually programmable
2. Stopwatch
3, General purpose timer
4. Event timer/counter
5. Rally timer
The MM5865 provides input pins for seven modes of
timing and/or counting operations. When the chip is
used as a timer, two input pins may be programmed to
provide a display resolution of 0.01 second, 0.1 second,
1 second, or external clock. In addition, the modulo by
which the counters divide may be programmed using
three divide scaler input pins.
6. Navigational timer
7. Industrial timer/counter
The MM5865 may also be used as a frequency counter,
or it may be used as the time reference of a larger
frequency counter. The maximum oscillator frequency
of the MM5865 is 80kHz; the maximum clock input
frequency is 100kHz.
The outputs include the comparator output, multiplexed
BCD segment oUtputs, ·and digit enable. The BCD segment outputs interface directly with the MM 14511
(CD4511), a BCD to 7-segment latch/decoder/driver
which interfaces with an LED display. The digit enable
outputs of cascaded MM5865s interface directly with a
DS8863 (DM8863), an MOS to LED 8·digit driver. A
single MM5865 interfaces directly with a DS8877 or
DS75492 6-digit driver.
how the MM5865 operates
As can be assumed from the brief description above, the
MM5865 is a very powerful :integrated circuit, capable
of many appl ications. Therefore, in order to fully stimulate the imagination of readers, its repertoire will be
presented in detail.
When a suitable crystal is used with the MM5865 oscillator, the counters of a single chip (or those of two chips
cascaded) may ,be used as timers with the following
functions:
2. Counter 2: Start-Stop timing
Counter 1: Total accumulated time
A block diagram of the MM5865 universal timer is shown
in Figure 1, and the connection diagram is shown in
Figure 2. As nearly as possible, all technical t~rms in the
following discussion conform to definitions presented
in the Radio Shack Dictionary of Electronics, edited by
Rudolf F. Graf.
3. Counter 2: Sequential event timing
Counter 1: Total elapsed time
Multiplexer
1. Counter 2: Start-Stop timing
Counter 1: Total elapsed time
Because of the internal multiplexer, only one BCD to
7-segment latch/decoder/driver need be used to interface one or two MM5865s to a suitable display. The
multiplexer may be controlled in three ways.
4. Counter 2: Split-timing with total elapsed time
Counter 1: Not actively used
5. Counter 2: Total accumulated time
Counter 1: Total elapsed time
An externally generated multiplex frequency may be
applied. to the Multiplex Input pin of the MM5865. An
external clock is then applied to the Clock Input pin.
(For example, an LM555C may be used as a square-wave
oscillator to provide the necessary input to pin 23.)
6. Counter 2': Up counter
Counter 1: Programmable counter
7. Counter 2: Programmable down counter
Counter 1: Not actively used
2-23
PROGRAM
OIGITS 1-4
CONTROL ClOUT
OIVIOE
SCALER
FUNCTIONS
1-7 .
CONTRO L Cl IN
BCO OUTPUTS
CONTROL
LOGIC
BUFFER
OIGIT OUTPUTS
CONTROL C2 IN
RESET
START/STOP
FINAL EVENT
COMPARATOR ENABLE
CONTROL C2 OUT
MULTIPLEX OUT ...- - - - -......--1
MULTIPLEX IN _ _ _ _ _ _+-~~I
OSCIL·
LATOR
MU LTlPLEXER
1 ' - - 4 OSCIN
~
L -_ _- - '
CLOCK IN/OUT
OSCOUT
BLANKING
RESOLUTION
SELECT ..:.._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..J
F.igure 1. Internal block diagram of the MM5865 Universal Timer.
DIVIDE SCALER 1
DIVIDE SCALER 2
DIVIDE SCALER J
CDMPARATDR ENABLE
FUNCTlDN 1
FUNCTIDN2
FUNCTlDN J
FUNCTlDN 4
FUNCTlDN 5
FUNCTlDN 6
FUNCTlDN 1
FINAL EVENT STDP/CDMPARATOR OUT
RESET
START/STOP
CLOCK IN/OUT
RESOLUTION SELECT 1
RESOLUTION SELECT 2
BLANKING
OSC IN
CSC OUT
When an external multiplex rate is applied to the Multiplex Input pin, the Multiplex Output pin must be connected to Vss, and the Oscillator In, Oscillator Out, and
Blanking pins should be floating. The multiplex rate
inside the chip is one fourth the frequency applied to
the Multiplex Input pin. In this mode of operation two
MM5865s may not be cascaded. In fact, to make use of
the Multiplex Output pin, the Mul~iplex Input pin must
be connected to Voo. The frequency at the Multiple'x
Output pin is the' same as that applied to the Multiplex
Input pin.
VSS
PROGRAM DIGIT I/LATCH CONTROL/LSD
PROGRAM DIGIT2
PROGRAM DIGITJ
PROGRAM DIGIT 4iWAITING STATE/MSD
CONTROL CllN
CONTROL ClOUT
m!t~
lSEGMENTS
BCD B
DIGIT I/LSDMM5B65/N
OIGIT 2
OIGITJ
OIGIT4/MSD
CONTROL C2 OUT
CONTROL C21N
MULTIPLEX IN'
MULTIPLEX OUT
VOD
The multiplexer may also be controlled by using internal
MOS circuits to form a crystal controlled oscillator. To
form the oscillator a crystal, two cClpacitors, and one
resistor must be added externally. One of the capacitors
. should be variable to allow precise frequency settings.
When these external components are connected to the
Oscillator Input and Oscillator Output pins, the Multiplex input pin must be connected to Voo.
When the input clock is at a COIl stant frequency above
400Hz the Multiplex Input pin may be connected to the
Clock Input pin. In this mode of operation the input
clock which is being counted is also used as the externally generated multiplex frequency. The multiplex
rate inside the chip will be one fourth the clock input
frequency as described above.
Figure 2. MM5865 connection diagram.
2-24
»
:2
Oscillator
Control Logic
Figure 3 shows how external components may be
connected to the Oscillator Input and Output pins. A
frequency counter used to adjust the frequency of the
oscillator may be connected to the Oscillator Output pin
through a 50pF capacitor.
The block labeled "Control Logic" con~ains the logic
required to select one of the seven functions, reset all
logic and counters, start and stop the counters, indicate
that a final event has occurred, and display counter 2 in
Functions 3 and 4.
The selection of a function is accompl ished by connecting one of the seven function pins to Vss; the other six
function pins are left fl~ating.
Vss
The Reset Input will reset all logic and counters in
Functions 1 - 5 and Function 7. In Function 6, Reset
will reset logic and counter 2, but not counter 1. For
reset to occur the Reset pin must be momentarily
connected to Vss. Internal control logic provides poweron reset, however, to insure proper power-on resetting
of all logic and the counters a lOflF, 3.5V Solid Tantalum
Capacitor (Allied #852-5680) should be used across the
Vss - Voo power busses.
~----~--~"TO
OIVIOER
CIRCUITS
VOO
In Function 6, the Reset Input pin may be connected
to the Comparator Output pin in order to automatically
reset logic and counter 2. When this connection is made,
a Start/Stop transition is all that is needed to repeat the
up count of counter 2.
INTERNAL
Figure 3. Crystal oscillator connections.
The Start/Stop Input is used to control the counters by
momentarily connecting pin 14 to Vss. The manner in
which this input affects the counters during the execution of each function will be explained as the descriptions of the functions are given.
Divider
The divider stages produce the blanking output by
dividing the oscillator input frequency by 41. This
output is used to blank the display at the beginning and
end of ea'ch digit time to allow for internal delay between
two cascaded chips. The display is blanked when the
Blanking Output is at Voo.
The Final Event Stop/Comparator Output pin is used to
indicate to the circuit that no more events will be timed
or counted. Final Event Stop affects the circuit when it
is momentarily connected to Vss. When this pin is used
as the comparator output, a VSS level at the pin indicates
comparison between the two counters.
The divider stages then divide the blanking output by 2
to generate the Multiplex Output. The frequency which
appears at the Multiplex Output pin is further reduced in
frequency by the divider stages so that the Resolution
Sclect pins may be used to program the resolution of the
display. Table I shows how these two inputs are used to
select the frequency ot'the internal clock pulses to be
applied to the two counters. The frequencies and display
resolutions for an oscillator frequency of 32.8kHz are
Additional Control Logic
The three Divide Scaler inputs permit the counters to
be programmed to count in Modulo 6 or Modulo 10.
Table /I sh~ws the possible codes which may be applied
to the Divide Scaler pins. A zero indicates that the pin
is left floating (or connected to Voo); a one indicates
that the pin is connected to VSS'
given.
Table I. Resolution Select Code. A zero indicates that the pin is
left floating (or connected to VDD); a one indicates that the pin
is connected to VSS. Note that when an external clock is applied
to pin 15, pins 16 and 17 must be connected to VSS.
Resolution Select
Pin 16
Pin 17
0
0
1
1
0
1
0
1
Table II. Divide Scaler Code
Counter 1
1
Pin
2
3
4
Digit
3
2
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
Frequency of
Display Resolution
Clock to Counters
100Hz
10Hz
1 Hz
External
0.01 sec
0.1 sec
1
sec
-
The Clock Input/Output pin is either an input or an output depending on the code at the Resolution Select input
pins. If the pin is used as' an output it will output the
clock frequency selected by the program applied to pins
16 and 17. When it is used as an input an external clock
must be used to clock the counters.
Modulo
Divide
Scalers
Counter 2
Digit
2
4
3
18 10 10 10
6 10 10 10
10
10
10
10
10
10
10
10
10
10
6
10
10
10
10
10
6
10
10 6
10 10 10
10
10
10
10
10
10
10
10
10
1
6
10
10
6
10
10
1
10 10
10
10
6
10
10
6 10
10
6
10
10
10
10
10
10
10
A zero indicates that the pin is left floating (or connected to
VOO};,a one indicates that the pin is connected to Vss.
2-25
For example, if the Resolution Select pins are programmed to give a 1 second display resolution (code "10") in
a stopwatch application, and if the Divide Scaler code is
"110," then the maximum possible count for both
counters 1 and 2 would be 9959 (99 min, 59 sec). This
means that the unit minutes display will advance by one
digit every 60 seconds.
function switch is switched to function 7), the comparator must be disabled by 1) disconnecting the Comparator
Enable pin from IVSS, and 2) momentarily connecting
the Reset pin to Vss; this must be done before the digits
are programmed. This is necessary, of course, because
connecting the Reset pin to'Vss after digit programming
will simply reset counter 1 to "0000." In function 6, a
Reset transition after digit programming does not reset
counter 1 to "0000."
Connecting pin 4 to V ss' enables the comparator. In
functions 1 -.5 the Comparator Enable pin must be left
floating (or connected to Voo). In function 6 the
Comparator Enable pin must be connected to Vss after
digit programming; if the Comparator Enable pin is connected to Vss (comparator enabled) at power on, the
Reset pin must be momentarily connected to Vss before
a Start/Stop transition will begin the counter 2 count-up.
In addition, the Control Cl In pin (pin 35) must be
floating (or connected to Voo) during digit programming
in function 7. After digit programming, the Control Cl
In pin must be connected to VSS before the count-down
begins. A DPDT, Center "OFF" switch connected as
shown in Figure 4, may be used to control both the
Comparator Enable pin and the Control Cl In pin. In
one position the DPDT switch connects the Control Cl
In pin to Vss for functions 1 - 5. Digit programming may
be accomplished in function 7 by placing the switch in
the Center "OFF" position. In the third position both
the Comparator Enable and the COl1trol Cl In pins are
connected to Vss for functions 6 and 7.
In function 7, if the Comparator Enable pin is floating
(or connected to Voo) when power is applied to the
chip, or when the function switch is switched to function 7, the Comparator Enable pin must be connected to
Vss after digit programming as in function 6; however,
in function 7, if the Comparator Enable pin is connected
to Vss (comparator enabled) at power on (or when the
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Figure 4. Stopwatch/Timer application showing the
described in the text.
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S10
c~nnections
FINAL
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MANUAL
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for a single MM5865. Two cascaded MM5865s may also be used, as
2·26
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Pins 36 - 39, the Program Digit 1 - 4 pins, are used to
program a desired count into counter 1 when using
functions 6 and 7. When any of the four Program Digit
pins are connected toVss, the display digit of counter 1
associated with that pin advances at a 2.5 Hz rate (assuming the oscillator frequency is 32.8kHz). The Program
Digit 1 pin advances the least significant digit of counter
1; the Program Digit 4 pin advances the most significant
digit. There is no carryover from digit to digit, and only
one Program Digit Input may be connected to Vss at
a time.
must be provided if every digit of the display is to be
programmable. In addition, another switch would have
to be provided to break the pin 39 connection between
the two chips in functions 6 and 7. Of course, all of the
switching action could be provided by one ganged
rotary switcfl if desired; even the function 6 Reset to
Comparator Out connection could be. accomplished if
the proper switch were used.
Electrical Characteristics
The maximum supply voltage which may be connected
between Vss and V DD (VOD = OV) is 20V. National
specifies that the minimum voltage. at which the chip
will operate is 7V; however, some chips will operate well
down to Vss = 5V. With a 9V transistor battery used as
the power supply, and display inhibited, the power
supply current will be approximately 7mA to 15mA for
a one-chip stopwatch.
The Program Digit 1 pin also functions as a counter 2
latch control in functions 3 and 4. In functions 3 and 4,
momentarily connecting the Program Digit 1/Latch
Control pin to VSS permits the display to show counter
2 counting.
The Program Digit 4 pin also serves two purposes; in
functions 1 - 5 this pin indicates that the chip has been
reset and is in the standby mode at power-on. Visual
indication of ' this condition may be accomplished by
connecting a transistor between the Program Digit 4/
Waiting State Indicator pin and the Segment DP Anode
of a multiplexed display. With the transistor connected
as shown in Figure 4, the Waiting State Indicator pin will
be at V SS at power-on until a Start/Stop transition
occurs. After a Start/Stop transition occurs, the Waiting
State Indicator pin will remain at Voo until power is
removed from the chip.
The maximum input frequency at the oscillator is 80kHz;
however, the oscillator and dividers are designed for stopwatch appl ications using a 32.8 kHz crystal. (A
32.768kHz crystal, available from Quest Electronics,
P.O. Box 4430 E, Santa Clara, CA 95054, may be used
without much loss in accuracy.)
Drivers must be provided for the Digit and BCD Outputs.
Two MM5865s interface directly with the MM14511'
Segment Driver and the pS8863 Digit Driver. A DS8877
or DS75492 Hex Digit Driver may be used with a single
MM5865.
Leading Zero Blanking
The Seven Functions
In functions 1 - 5, leading zeros are blanked for both
'Counters. In functions 6 and 7, counter 2 has leading
zero blanking but counter 1 does not. At power-on the
display is blank (or all decimal points if the Waiting
State Indicator pin is used) in functions 1 - 5; all zeros
are displayed in functions 6 and 7.
The one-chip circuit shown in Figure 4 indicates all
connections necessary to employ the MM5865 as a 4digit stopwatch/timer. The seven available functions will
be described using this figure, in which ·the desired
function is selected by switching S5. When necessary,
refer also to Figures 1 th rough 3.
Control C1, C2 In and Control C1, C2 Out
These four pins are used to cascade two chips together.
In this mode of operation the primary MM5865, which
is directly controlled by the crystal oscillator, connects
to another MM5865 in the following manner: the
Control C1 In pin of the primary chip is connected
to Vss except during digit programming in function 7;
the Control C1 Out pin connects to the Control C1 In
pin of the other MM5865; the Control C2 In pin of the
primary chip is connected to Vss; the Control C2 Out
pin connects to the Control C2 In pin of the other
MM5865; the Control C1 Out and the Control C2 Out
pins of the second chip are left floating.
Function 1
In function 1, at power-on (S1 closed) four decimal
points are visible on the display, indicating that the
counters have been reset, but not necessarily all logic.
If the Comparator Enable pin is connected to Vss (S3
in Function 6 - 7 position) at power-on, a Start/Stop
transition (obtained by momentarily closing S12) will
cause the decimal points to disappear from the display;
however, the chip will not begin counting. First it is
necessary to place S3 in the Functions 1 - 5 position,
then to reset the logic (by momentarily closing S11).
Once all logic is reset (either by applying power with S3
in the Functions 1 - 5 position or by the method discussed above), a Start/Stop transition will cause both
counters to begin counting up. The up-count of counter
2 is displayed, the least significant digit advancing at a
1 Hz rate. A second Start/Stop transition inhibits the
clock pulses to counter 2 and stores and displays the
contents of counter 2; however, counter 1 continues to
count. A third Start/Stop transition resets counter 2,
enables clock pulses to counter 2 and, again, displays
counter 2 counting up. Subsequent Start/Stop transitions repeat this sequence. Counter 1 continues to
count, from the time of the first Start/Stop transition,
until the occurrence of a Final Event Stop transition
(obtained by momentarily closing SlO). A Final Event
When the Control C1 In pin is floating (or connected
to Vool. the clock pulses to counter 1 are inhibited_
When the Control C1 In pin is connected to VSS, counter
1 is enabled. Control C1 Out'is at Vss when counter 1 is
at its maximum count, and it is floating at all other
times. The Control C2 pins affect counter 2 in a similar
manner.
Other possible connections between the two chips are:
1) all function pins connected together, 2) pins 12, 13,
14, and 15 connected together, 3) all BCD pins connected together, and 4) pins 39 connected together in
functions 1 - 5 only.
When two MM5865s are cascaded as described above,
eight momentary switches or individual electrical signals
2-27
en
CO
Stop transition inhibits the clock pulses to both counters
and displays counter 2. After this Final Event Stop
transition has occurred, a Start/Stop transition switches
the display from counter 2 to counter 1. Each subsequent Start/Stop transition alternately displays one of
the counters.
transition stores and displays the contents of counter 2.
Subsequent Start/Stop transitions update the display of
counter 2. A Latch Control transition will display
counting until the occurrence of a Start/Stop transition.
This Start/Stop transition, following the Latch Control
transition, does not reset counter 2 as it does in function
3. Rather, counter 2 continues to count up. A Final
Event Stop transition inhibits' the clock pulses to
counter 2 and displays the contents of counter 2. A
Reset transition at any time resets counter 2 to "0000."
To summarize, in function 1 both counters start counting
up with an initial Start/Stop transition. Counter 1
continues to count (recording total elapsed time) until
a Final Event Stop transition. Counter 2 (alternately)
starts, then stops counting with each Start/Stop transition (timing as many intervals as desired!. until a Final
Event Stop transition. Any time a Reset transition
occurs both counters are reset to "0000" and the display
blanks.
Function 5
Again, in function 5 the power-on conditions are the
same as those in functions 1 - 4. Once all logic is reset a
Start/Stop transition causes both counters to begin
counting up. Counter 2 is displayed counting. A second
transition on the Start/Stop pin inhibits the clock pulses
to counter 2, and the contents of counter 2 are displayed. Counter 1 continues to count. A third Start/
Stop transition enables the clock pulses to counter 2;
counter 2 resumes counting where it left off, and counter
2 is displayed counting.
Function 2
The only difference between functions 1 nnd 2 is thnt in
function 2, whenever a Start/Stop transition inhibits the
clock pulses to counter 2, the clock pulses to counter 1
are also inhibited. Start/Stop transitions which reset
counter 2 and enable clock pulses to counter 2 also
enable clock pulses to counter 1; counter 1 does not
reset, however. The up-count in counter 1 resumes at the
stored count; therefore, counter 1 records total accumulated time.
Subsequent Start/Stop transitions repeat this sequence
with counter 1 counting continuously. A Finnl Event
Stop transition inhibits the clock pulses to both counters
and displays counter 2. A Start/Stop transition switches
the display from counter 2 to counter 1. Repetitive
Start/Stop . transitions switch the display between
counter 2 and counter 1. A Reset transition at any time
resets both counters to "0000."
Function 3
In function :3 the power-on conditions are the same as
those in functions 1 and 2 .. Once all logic,is reset a Start/
Stop transition causes both counters to begin counting
up Counter 2 is displayed counting. A second Start/Stop
transition stores and displays the contents of counter 2,
resets counter 2, and initiates a new up-count. However,
the new up-count is not displayed. Counter 1 continues
to count. The initial count remains displayed until a
third Start/Stop transition. This third Start/Stop transition and subsequent Start/Stop transitions repeat the
sequence described above, indicating the length of time
between successive Start/Stop transitions.
Function 6
At power-on in function 6, counter 1 is displayed with
"0000." If the comparator is enabled (S3 in the
Function 6 - 7 position) at power on, a Reset transition
(obtained by momentarily closing S11) is necessary
before a Start/Stop transition can begin the counter 2
count-up.
Counter 1 is prog'rammed to the desired count by
holding each of the four Digit Programming Switches
Closed in turn. The comparator must then be enabled by"
placing S3 in the Function 6 - 7 position (unless it was
already enabled at power-on). Counter 2 is displayed
counting up beginning with a Start/Stop transition.
When counter 2 is coincident with counter 1, the clock
pulses to counter 2 are inhibited, the contents of
counter 2 are displayed, and the Comparator Output is
enabled. A Reset transition after the counter 2/counter 1
coincidence disables the Comparator Output and
displays counter 1 with the programmed time. The Reset
transition can be obtained either by momentarily'
closing S11 or by connecting the reset Input pin to the
Comparator Output pin after Digit Programming so that
logic and counter 2 are reset automatically whenever
counter 2 is coincident with counter 1.
The occurrence of a Latch Control transition (obtained
by momentarily closing S5) any time after the second
Start/Stop transition will cause counter 2 to be displayed
while counting. The count will continue to be displayed
until a Start/Stop transition. This Start/Stop transition
also stores and displays the contents of counter 2 and
then resets counter 2. As before, counter 1 continues to
count, but counter 2 begins a new count.
A Final Event Stop transition inhibits the clock pulses
to both counters and displays the contents of counter 2.
A Start/Stop transition occurring after the Final Event
Stop transition switches the display from counter 2 to
counter 1. Repetitive Start/Stop transitions switch the
display between counter 2 and counter 1. Any time a
Reset transition occurs, both counters are reset to
"0000" and the display blanks.
After each Reset transition, subsequent Start/Stop
transitions repeat the sequence. Counter 1 may be- reprogrammed after any Reset transition, if desired. If a
Reset transition occurs while counter 2 is counting up,
the clock pulses to counter 2 are inhibited, counter 2
is reset, and counter 1 is displayed with the programmed
time.
Function 4
In function 4 the power-on conditions are the same as
those in functions 1 - 3. Once all logic is reset 8 Start/
Stop transition causes counter 2 to begin up-counting.
Counter 2 is displayed counting. A second Start/Stop
2-28
»
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~
output drive capability of 25mA. The DS8863 is an
8-digit driver; each driver is capable of sinking up to
75mA. The MM14511 may be operated at supply
voltages up to 15 V; however, the DS8863 cannot be
operated with supply voltage greater than 10V. For
operation with supplies up to 18V, the DS8963 is a
direct replacement for the DS8863.
If a Start/Stop transition occurs while counter 2 is
counting up, the clock pulses to counter 2 are inhibited
and counter 1 is displayed with the programmed time.
With the next Start/Stop transition, counter 2 resumes
counting where it was stopped.
If the Reset Input pin is not connected to the
Comparator Output pin and if a Final Event Stop tran·
sition occurs while counter 2 is counting up, the clock
pulses to counter 2 are inhibited and the contents of
counter 2 are displayed. The next Start/Stop transition
displays counter 1 with the programmed time. Repetitive Start/Stop transitions switch the display between
counter 2 and counter 1. A Reset transition followed by
a Start/Stop transition starts the counter 2 up-count
sequence again.
The NSA398 is a 9-digit common cathode LED numeric
display with a 1/8-inch character height. Eight inputs
are provided for selection of the appropriate segments
and decimals (anodes) and nine inputs for digit
(cathodes) selection. The anodes are internally interconnected for multiplexing. The NSA398 has a red
faceplate which provides excellent visual contrast and
ease of visibility over a wide angle. Figure 5 shows the
physical dimensions and pin connections of the NSA398.
In function 6, and also in function 7, the digit which is
preprogrammed to count in Modulo 6 cannot, of course,
be programmed to a digit greater than 5.
Function 7
practical applications of the
stopwatch/timer
In function 7 counter 1 is displayed with "0000" at
power-on. If S3 is in the Function 6 - 7 position at
power-on, it must be placed in the "OFF" position;
then S11 must be momentarily closed. Counter 1 is
set to a specific count by holding each of the four Digit
Programming Switches closed in turn; then the
Comparator must be enabled by placing S3 in the
Function 6 - 7 position.
Now that the basic operation of the MM5865 has been
presented, it is possible to examinfl practical applications
of the seven function universal timer shown in Figure 4.
This timer, as shown, has a maximum timing capability
of 99 minutes, 59 seconds. If another MM5865 is added
to the circuit, this timing capability may be extended to
99 hours, 59 minutes, 99.99 seconds. For very accurate
timing, the crystal should be cut to oscillate at 32.8 kHz,
and the oscillator frequency should be precisely tuned
to 32.8 kHz.
Counter 1 counts down from the se.t count beginning
with a Start/Stop transition. When counter 1 counts
down to zero the clock pulses to counter 1 are inhibited
and the Comparator Output is enabled. This is not
repeatable without a new count 'being entered into
counter 1, A Final Event transition halts the counter 1
down-count, and subsequent Start/Stop transitions have
no effect on counter 1 or counter 2. A Reset transition
resets counter 1 to "0000."
When the stopwatch/timer is being used to time any
event, the display should be disabled with S2 as much
as possible so that battery power will be conserved.
Function 1 may be used to time two events occurring
simultaneously in the following manner. A driver often
travels from his home to a city some hours away. On the
way· he passes a small town about halfway between his
home and the city. He wishes to know how. long it takes
him to travel from his home to the small town, how long
it takes to travel from the town to the city, and finally,
how long it .takes him to travel from his home to the
city.
Peripheral
The other components shown in Figure 4 consist of
input/output interfaces between the user and the
MM5865. The crystal used in this stopwatch/timer
circuit is a watch crystal cut to oscillate at 32.768kHz.
(A 32.8kHz crystal would be best.) This means that the
blanking frequency is 799.2 Hz, the multiplex frequency
is 399.6 Hz, and the clock frequency to the counters is
0.99902Hz.
At the beginning of the trip the driver presses the Start/
Stop switch. The display begins to record the time
accumulating in counter 2. As he passes through the
small town he presses the Start/Stop switch again and
records the traveling time from his home to the town.
Then he presses the Start/Stop switch again. As he
arrives at the city he presses the Final Event Stop switch
and records the time shown in the display as being the
travel ing time from the town to the city. He then
presses the Start/Stop switch and sees in the display the
traveling time from his home to the city.
The oscillator frequency may be adjusted by connecting
a counter to pin 20 of the MM5865 through a 50pF
capacitor and then varying the capacitance of C3. Any
attempt to alter the values of R 1, C2, or C3 will probably
fail; that is, the oscillator will probably not oscillate.
Most of the switches which control the MM5865 are
momentary push-buttons which are available from many
sources. The function switch, however, is a very small
8-position switch in a TO-5 package; it is available from
James Electronics, P.O. Box 822, Belmont, CA 94002.
Function 2 may be used to record the total accumulated
time of several events while each event is being timed
individually. For example, a television repairman spends
his day ordering parts, talking to customers, and repairing televisions on the bench. He wants to record the time
he spends repairing each set so that customers may be
properly billed, and he wishes to record his total bench
time for the day.
The 2N4400 (a 2N3904 can also be used) drives the
decimal point anode of the display and is itself driven
by the Waiting State output of the MM5865.
The MM14511 provides the functions of a 4-bit storage
latch, an 8421 BCD-to-seven segment decoder, and an
2-29
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PIN CONNECTIONS
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DIGIT 1 CATHODE
SEGMENT C ANODE
DIGIT 2 CATHODE
SEGMENT DP ANODE
DIGIT 3 CATHODE
SEGMENT A ANODE
DIGIT 4 CATHODE
SEGMENT E ANODE
9 DIGIT 5 CATHODE
10 SEGMENT 0 ANODE
11 DIGIT 6 CATHODE
12 SEGMENT G ANODE
13 DIGIT 7 CATHODE
14 SEGMENT B ANODE
15 DIGIT 8 CATHODE
16 SEGMENT F ANODE
17 DIGIT 9 CATHODE
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Figure 5. Physical dimensions and pin connections of the NSA398.
At the beginning and end of every bench job he presses
the Start/Stop switch to record the time for each job. At
the end of his day he presses the Final Event Stop switch,
then the Start/Stop switch to record his total bench
time.
With function 4, the total time of an event may be
accumulated, and the display may be updated while
counter 2 is accumulating the total time. For example,
a long distance runner desires to pace himself over a 5mi Ie run. As he starts out he presses the Start/Stop
switch. Then, as he passes known checkpoints, he presses
the Start/Stop switch to update the display and note the
time of arrival at each check point. At the end of the 5mile run he presses the Final Event Stop switch to
record the total time for the run.
As an example of a function 3 application, consider an
assembly line position at which a worker must fasten
three parts to a piece of equipment. A supervisor wishes
to record the time it takes the worker to fasten each part
and the amount of time the equipment spends at this
position.
Function 5 may be used to record both total accumulated time and total elapsed time. As an example of an
appl ication of function 5, consider a pilot who wants to
record total flying time as well as total trip time.
As the worker receives the piece of equipment, the
supervisor presses the Start/Stop switch. The display
begins counting up. As the worker finishes with the
first part, the supervisor presses the Start/Stop switch.
This time will remain in the display until the next Start/
Stop transition; the supervisor therefore has a chance to
record the first event time.
As the pilot starts out he presses the Start/Stop switch.
He then presses the Start/Stop switch each time he lands
and each time he resumes flying. At the end of his trip
he presses the Final Event Stop switch and records total
flying time. He then presses the Start/Stop switch to
record total trip time.
As the worker finishes wit~ the second part, the supervisor presses the Start/Stop switch again and records the
time of the second event. After the worker finishes with
the third part the supervisor presses the Final Event
Stop switch. The display will show the third event time.
The supervisor can then press the Start/Stop switch to
record the total time this worker handled the equipment.
With p;oper interfacing, function 6 can be used as an
enlarger timer. A photographer programs the desired
printing time into the display with the Digit Programming
switches, closes the Comparator' Enable switch; and
closes the Automatic Reset switch. For each print he
2-30
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Figure 6. The MM5865 used in a simple counting circuit.
simply presses the Start/Stop switch to turn on the
enlarger for the desired length of time.
The 74COO in this circuit debounces the switch used as a
clock, S3. An LM555 is used to provide a multiplexer
input frequency of 233 Hz.
It is not necessary to enable the display while operating
the timer. The display must be enabled only to program
counter 1. The Reset switch may be pressed at any time
to turn off the enlarger. The enlarger may be turned on
for adjusting negatives by pressing the Start/Stop switch
without enabling the comparator.
The MM5865 is operating in function 5, and displays the
up-count of counter 2. After an initial Start/Stop transition, each closure of the manual switch advances the
displayed digits by one count. A Reset transition resets
counter 2 to "0000."
With pro·per interfacing, function 7 may be used as a
down-count timer for many applications, including
cooking and washing. The desired time is simply programmed into counter 2, the comparator is enabled,
and then the Start/Stop switch is pressed. Counter 2 will
count down to zero and turn off the appliance.
conclusion
.~
The emphasis of this presentation has been on the
general timing and programmable capabilities of the
MM5865 rather than on specific applications. Because
so many functions are available in one package, it is
possible to use the MM5865 as a general purpose chip,
adding another MM5865 when it is necessary. In most
applications only one or several of the seven functions
need be used; however, because of its general purpose
nature, the MM5865 lends itself well to the concept of
quantity purchasing.
A few applications (some for which two MM5865s are
required) have been presented to illustrate the utility
of the MM5865. The Stopwatch/Timer discussed above
is but one general application for which the MM5865
may be used.
Figure 6 shows a simple manual counting circuit in
which the MM5865 is used to count the closures of a
manual switch. Of course, the manual clock could be
replaced by electrical pulses.
2-31
A final note: Unless the start pulse is externally synchronized to the clock (available at pin 15 of the MM5865, if
the internal oscillator is used), the amount of time which
will elapse between the arrival of the start pulse at pin 14
of the MM5865 and the appearance of the first digit in
the display will not be equal to the programmed display
resolution_ It is possible to develop a start pulse that is
synchronized to the clock using an MM74C221 Dual
Monostable Multivibrator as shown in Figure 20. The
time constant of R 1 - C1 should be equal to the display
resolution, the time constant of R2 - C2 should be less
than the programmed display resolution, and the time
constant of R3 - C3 should be less than the time constant
of R2-C2.
VSS
START SWITCH
1
16
TO
R2
PIN 14
OF
MM5865
R1
FROM
PIN 15
OF
MM5866
Voo
Figure 21. Start-Pulse Synchronizer. Time constant of R1 - C1 =
display resolution. Time constant of, R2 - C2 < display resolution.
Time constant of R3 - C3 < time constant of R2 - C2.
2-32
Counters/Timers
A 4-Digit, 7-Function Stopwatch/Timer
introduction
4. Counter 2: Split-timing with total elapsed time
Counter 1 : Not actively used
This construction article is the second of a series which
is to concentrate on applications of the MM5865 universal timer_ The first article, "MM5865 Universal
Timer Applications," presented in detail the programmable and functional characteristics of the MM5865_
5. Counter 2: Total accumulated time
Counter 1 : Total elapsed time
G. Counter 2: Up counter
Counter 1 : Programmable counter
This second article illustrates the construction and use
of a 4-digit, 7-function stopwatch/timer in which the
display resolution and counter modulo may be programmed with printed circuit board jumper wires_
7. Counter 2: Programmable down counter
Counter 1: Not actively used
Other than switches, all compo'nents of the stopwatch/
timer are mounted on a glass-epoxy or glass-polyester
board which is laminated with l-ounce copper foil on
one side. The board is mounted in the attractive instrument/clock case available from James Electronics.
operation
The switches which control the operation of the stopwatch/timer are visible on top of the case shown in the
photographs of Figures la and lb. Each switch is
indicated in the schematic drawing of Figure 2.
This instrument/clock case has provisions for the display,
precut holes for four calculator-type switches, and a
precut line cord hole. In addition, the case is sold with
a red display bezel, four rubber feet, and a flip-top to
conceal the four switches which may be assembled in
the precut holes.
In Figure la, the switch in the rear right hand corner of
the case is a 7-position rotary Function Switch (F). At
·the front of the case the switches are, from left to right,
. Digit 4 Programming Switch (04), Digit 3 Programming
Switch (03), Comparator Switch (C), Digit 2 Programming Switch (02), and Digit 1 Programming (01)/
Latch Control (LC) Switch. Digit 1 is the least significant
digit (LSD); Digit 4 is the most significant digit (MSD).
A display resolution of 1 second, 0.1 second, or 0.01
second may be programmed by on-board jumpers or a
suitable switch. Furthermore, the counters may be
programmed to count in modulo 6 or modulo 10.
When used as a photographic enlarger timer or ilS iln
appliance timer, each digit is individually programmable
with one of four pushbutton switches. The comparator
output of the timer may be coupled to an enlarger/
appliance control circuit that can be permanently
mounted to the enlarger or appliance.
There are four switches under a center flip-cover. These
are shown in Figure lb. From left to right they are
Final Event Switch (FE), Reset Switch (R), Start/Stop
Switch (SS), and Automatic Reset Enable Switch (ARE)_
The ARE switch is used only in function 6; it must be
OFF for all other functions. The C switch has three
positions: Comparator/Count Enable (CCE), used for
functions 6 and 7; Program Enable (PE), used for
function 7; and Count Enable (CE), used for functions
1 through 5. The Dl/LC switch is a dual purpose switch;
for functions 3 and 4 it serves as the latch control switch,
and for functions 6 and 7 it serves as the Digit 1 programming switch. There is no ON-OFF switch. Power is
applied to the stopwatch/timer by plugging the line cord
into a 120 VAC/60 Hz outlet.
Applications for the stopwatch/timer include, but are
not limited to, the following:
•
Laboratory reaction and interval timer
•
Photographic enlarger and chemical processing timer
• Stopwatch
•
Event timer
•
Appliance timer
A simple listing of possible applications for the timer
does not adequately describe the enormous power of
the instrument. A tabulation of the seven functions
which includes a break-out of the functions performed
simultaneously by counters 1 and 2 of the MM5865 is
much more revealing, and is presented below:
Table I is a tabulation of the abbreviations used for the
switches and the functions to which they apply. If the F
switch is set to any of the stop Watch functions (1
through 5) when power is initially applied to the
stopwatch/timer, the display will remain blank. See
"MM58G5 Universal Timer Applications" for information
on using pin 39 as a power on indicator.
1. Counter 2: Start-stop timing
Counter 1: Total elapsed time
To operate the stopwatch/timer in any of the stopwatch
functions, rotate the .. F switch to one of the stopwatch
function positions, place the ARE switch in the OFF
position, place the C switch in the CE position, and press
the R switch.
'
2. Counter 2: Start-stop timing
Counter 1: Total accumulated time
3. Counter 2: Sequential event timing
Counter 1 : Total elapsed time
2-33
(b)
(a)
(c)
Figure 1. External Ph~tographs of Stopwatch/Timer. a) View of Function Switch, Comparator Switch, and Digit Programming Switches.
b) With flip·cover raised, four additional switches are seen. The flip·cover is designed so that a press of the closed cover closes the Start/
Stop Switch. c) A miniature jack is mounted at the rear of the case so that a cable may be run to the appliance control box.
VSS
40
24
Von
C4
ENABLE
19
DISPLAY CONTROL
(OPTIONAL)
20
16
S12
R
23
Tl
12
~--_II
21
C2
13
150"
1 R
2 R
JR
10
5 R
6 R
1R
12
13
14
11
12
DISPLAY
-
S
1-----112
1-----113
1-----114
~-----I1S
35
14
MTI
GATE
39
MT2
38
31
TRIAC
36
Figure 2. Schematic Diagram of the 4·Digit, 7·Function Stopwatch/Timer. As drawn, the display resolution is 1 second. A SPST switch
may be included betwep.n pin 16 of IC2 and VSS to provide a display resolution of 0.01 second or 1 second. Another option, shown in
the figure,.is the Display Control Switch, which may be used to inhibit the display.
Table I. Switch Abbreviations
--~-~-~---
-----~----~--
Abbreviation
Switch
ARE
C
D1
D2
D3
D4
F
FE
LC
R
SS
Automatic Reset Enable
Comparator
LSD Programming
Digit 2 Programming
Digit 3 Programming
MSD Programming
Function
Final Event
Latch Control
Reset
Start/Stop
2-34
I
Functions
6
1- 7
6, 7
6, 7
6, 7
6, 7
1- 7
1-5
3, 4
1- 7
1- 7
l>
2
Table II. Resolution Select Code. A zero indicates that the pin
is left floating (or connected to VDD); a one indicates th~t the
pin is connected to VSS. Note that when an external clock is
applied to pin 15, pins 16 and 17 must be connected to VSS.
made. The operation of each function is detailed in the
first article of this series.
To operate the timer in function 6, rotate the F switch
to function 6, place the C switch in the CCE position,
and press the R switch. The display will show four zeros
when the R switch is pressed.
--~~------
Resolution Select
Pin 16
Pin 17
0
0
1
1
0
1
0
1
Frequency of
Display Resolution
Clock to Counters
The count·up time is programmed into the timer by
pressing 01 through 04, one switch at a time, until the
desired count·up time appears in the display.
0.01 sec
0.1 sec
sec
1
100Hz
10Hz
1 Hz
External
-
After digit programming, pltlce the ARE switch in the
ON position if automatic resetting is desired. The initial
press of the SS switch will cause the display to blunk,
then to indicate the count-up to the programmed time.
During the up-count the CA3059 will be enabled,
allowing the appliance to be turned on. When the count·
up reaches the programmed time, the comparator output
will go from 0 volts to 8.4 volts. At this time the CA3059
will be inhibited, and the appliance will turn off.
Pressing the R switch any time after the digits huve been
pfogrammed causes the comparator and counter 2 to
reset. Switching the C switch to OFF causes the com·
parator output pin to go to Voo as long as it is OFF.
If the C switch is again placed in the CCE position
(before the R switch is pressed), the comparator output
pin will go back to VSS. Of course, any time the FE
switch is pressed the comparator output will go to VSS.
Table III. Divide Scaler Code
--~
Divide
Scalers
Modulo
~----~----
-----
----.------~
Counter 2
Counter 1
-- - -
---------- ---
1
Pin
2
3
4
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
10
6
10
10
10
10
10
10
Digit
3
2
10
10
6
10
10
10
10
10
10
10
10
6
10
10
10
10
1
4
10
10
10
10
10
10
10
10
10
6
10
10
10
6
10
10
Digit
2
3
10 10
10 10
6 10
10 . 6
10' 10
10
6
10
1
10
10
10
10
10
10 10
10
10
If the ARE switch is ON, the count-up sequence may be
repeated by pressing the SS switch again. Nothing need
be changed untjl it is necessary to reprogram the digits.
When reprogramming is necessary, simply chan~le the
time shown in the display to the new time, with the
ARE switch in the OFF position, using the digit programming switches. Then press the SS switch to start the upcount. If the ARE switch is OFF, it is necessary to press
the reset before starting a new count-up.
6 10
A zero indicates that the pin is left floating (or connected to
Voo); a one indicates thul the pin is connected to VSS'
Press the SS switch to initiate a sequence of timing
series. Press the SS switch again to end a serial (functions
1,2,3, 5) and simultaneously initiate a new serial while
freezing the display (function 3), or to freeze the display
during a continuous count sequence (function 4).
To operate the timer in function 7, rotate the F switch
to function 7, place the ARE switch in the OFF position,
place the C switch in the PE position, and press the R
switch. The count-down time is programmed into the
timer by pressing 01 through 04, one switch at a time,
until the desired count-down time appears in the display.
The C switch must then be placed in the CCE position.
Press the SS switch a third time to initiate a new timing
serial (functions 1, 2, 3, 5) or to update the display
during a continuous count sequence (function 4).
Subsequent presses of the SS switch will repeat the
action described above.
Press the LC switch to display a continuing, undisplayed
count (functions 3 and 4). Press the FE switch to end a
sequence. A final press of the SS switch at the end of a
sequence is required to display total elapsed time
(functions 1,3,5) or total accumulated time (function 2).
Subsequent presses of the SS switch after the end of a
sequence simply repeat the display of the final serial
time, then the total elapsed or total accumulated time.
I
The operations which may be performed in each function
are shown in the flow charts of Figures 3 through 8.
The first line of type in each PROCESS rectangle indicates a' switch or the display upon which an action may
be performed. The second line of type indicates the
pcsition in which the switch must be placed or the
action to be performed. The parallelograms ill the flow
. charts indicate points at which a DECISION must be
Pressing the SS switch will cause counter 1 to begin its
down-count from the programmed time to "0000" and
will cause the CA3059 to be enubled, turning on the
appliance as in function 6. When counter 1 reaches
"0000" the CA3059 will be inhibited, turning tlie
appliance off. The down-count is displayed, and may be
halted at any time by pressing the FE switch; the downcount may not be resumed. Pressing the R switch any
time after digit programming will reset counter 1.
When using function 7, the comparator must be disabled
and the R switch must be pressed before digit program·
mingo Then the comparator must be enabled. This is
unlike function 6, in which digit programming is allowed
at any time, regardless of the state of the comparator.
In addition, the ARE switch must not be used in
function 7 .
2-35
I
~
en
CD
Figure 3. Functions 1 and 2. Pressing START/STOP after FINAL EVENT has been pressed gives Total Elapsed Time in Function 1,
Total Accumulated Time in Function 2.
Figure 4. Function 3. Pressing START/STOP after FINAL EVENT has been pressed gi~e~ Total Accumulated Time.
2-36
l>
:2
I
-10
0')
to
Figure 5. Function 4.
Figure 6. Function 5.
2·37
interfacing the stopwatch/timer
with an appliance circuit
There are many ways to interface the comparator output
with an appliance control circuit. One method of interfacing the MM5865 with an appliance control circuit is
shown encl~sedin dotted lines in Figure 2. Figure 2 is
the schematic diagram of the stopwatch/timer.
The 74CD2 has been included as the interfacing element
between the comparator output pin and the trigger
circuit of a triac. Figure 9 is a detailed schematic of the
74CD2 connections which form a NOR latch.
)()..:.;......- - . OUTPUT
COMP OUTPUT
PIN 12 OF MM5865
START/STOP
PIN 14 OF MM5865
Figure 9. Detail of the 74C02 NOR Latch. The latch interfaces
the MM5865 to the CA3059.
Figure 7. Function 6.
The appliance control circuit does not cause R F I because
the t;iac is triggered by a zero·voltage switch. Triac
firing can be inhibited by the application of a positive
(up to 10V) voltage to pin 1 of the CA3059.
When power is initially applied to the stopwatch/timer
the Sand R inputs of the latch are both "D." When the
R switch is pressed, the output of the latch will go to
Vss, inhibiting the CA3D59 pulses to the triac.
When the SS switch is pressed (after digit programming)
the output of the latch will go to Voo and the CA3059
will be enabled, turning on the appliance. As the pro·
grammed time is reached by counter 2 of the MM5865
(function 6), or as counter 1 reaches "DDDD"(function 7),
the comparator output will go to VSS, the output of the
latch will go to V ss , and the CA3D59 will be inhibited,
turning off the appliance.
The inhibit level provided by the latch may be removed
from the CA3D59 by opening the Appliance Enable
Switch. This allows the appliance to be turned on tOr
adjustments. For example, when the timer is used ~ith
an enlarger, the Appliance Enable Switch permits
enabling of the enlarger lamp for focusing and mag·
nification adjustments.
The output of the latch is connected to the appliance
control circuit via a tape recorder cable which plugs into
a jack mounted at the rear of the stopwatch/timer case
and a jack mounted on the appliance control circuit
housing. Th'e housing for the appliance control circuit
should also have a socket into which the appliance may
be plugged, unless a direct connection is desired.
Figure 8. Function 7.
2-38
»
2
As shown in Figure 2, the appliance control circuit
consists of a triac and its trigger circuit. When the
CA3059 zero voltage switch is enabled, the trigger
circuit applies a brief gate signal to the triac for every
alternation of the AC line voltage. After the triac is
turned on by the gate signal, it remains on for the
complete half cycle until the zero-crossing point is
reached at the end of the alternation. The appl iance
receives the full AC line voltage under these conditions.
If the exposure time, the amount of light, and the
development time are exactly correct, trace resolution is
usually not a problem. However, it is difficult to compute
and control these variables without performing many
experiments. The inspection method described above
can save many boards which otherwise would be lost
because of trace resolution defects.
In addition to the care which must be given to the PC
board during the etching process, excessive solder should
be avoided when soldering to the pads. In case of difficulty with timer operation during thecheckout procedure,
suspect the board immediately.
If the NOR latch inhibits the trigger circuit while the
triac is conducting, the triac cuts off when the line
voltage approaches zero. It remains off until another
gate signal is applied. Therefore, the NOR latch controls
the AC input to the appliance.
Furthermore, no thought should be given to the idea of
not using sockets for the integrated circuits. James
Electronics has four socket styles. All are adequate
except the wire wrap sockets. (The diameter of the wire
wrap leads is too large.) However, it is easier to insert
and remove ICs from the standard tin and gold sockets.
With the heat sink specified the triac can safely handle
appliances rated up to 100 watts (0.83 Amp). For
greater appliance loads a larger heat sink should be used.
The specified triac is able to handle appl iance loads up
to 10 Amps. Of course, the fuse must be larg~ enough to
handle the current drawn by the appliance. Use a fast
blow fuse if possible.
The drilling guides shown in Figure 10 indicate all drill
sizes for the parts shown in the parts list. Every effort
has been made to allow the board to accommodate a
variety of components. For this reason, there are extra
pads and punch guides on the drilling guides. Refer also
to the component layouts shown in Figure 11. The
boards may be prepared using the Xl positives. shown in
Figure 12.
construction
The printed circuit board was designed specifically for
the James Electronics' instrument/clock case only after
assurance that the company has a permanent source for
the cases; however, the board may be mounted in any.
case o.f sufficient size.
The bottom half. of the James case should be prepared
for the board by removing the 6 plastic pegs at the front
of the case if they are present. The pegs may be removed
by grasping them in the jaws of a long-nose pliers and
shaking them from side to side while pulling on the
pliers.
Because the layout of the PC board requires that some
traces be proximate, the board must be inspected while
it is being etched. During these inspections proper
resolution of the traces is maintained, if necessary, by
rinsing the board in water and carefully scraping the
photoresist from any copper which forms a short circuit
between adjacent traces. The scraping is done best with
an X·Acto blade. Etching should be continued with
frequent inspections.
The earphone socket should be drilled out from the
outside of the bottom half of the case with a 31/64-inch
drill bit. This will allow a 7-function rotary switch to be
mounted in the right hand (facing the display) corner of
the rear section of the top half of the case. When doing
this, first press the bit to the 3/8-inch hole in the bottom
half of the case, then turn on the drill. The bit should
slice the earphone socket off with 4 or 5 turns of the
chuck.
FIG. lOA
o
60
0
"
_~ORlll-4HOlES
FIG. lOB
~650
' - 60
b
/1/16
16 HOLES
~60D
:
' - 60
16 HOLES
65
'-60
/
91/16/
1I:5H~~'g - 7
~
64 "
/ ' 64
J
54
60~
65
'I.
60'\.
"-
J
'--
64
J65 6~
,,~
70
'/
70 -
65 ~
,,60
,\65
65~
64-60~
:~
~65
[1/16'/
1/16 "-
/'
' - 64
64
64'~
J/16 DRill
65.-----.,~60
../..
1
1/16
/'
2 liOLES
1 16
/ . "
' - 1/16
1/16", .
/
65./~
"-
60
/'
60../16
64 . . /
64
"
-~
"'-
•
0
1/16 ' \ ,
...
/
"
'"
64
o
64
' - - 65
0
Figure 10. Drilling Guides for the Printed Circuit Boards. a) Drill ~izes and hole locations for the Stopwatch/Timer PC board_ b) Drill
sizes and hole locations for the appliance control circuit. Dimensions'are in inches.
,
2·39
.
p--~ ~
;:~ c.:::: 0
C7 o~CD
~ [J.~, ~GO:.~.p;,
•
o-DD-""""
0
s= "
+0
~
C6
0
=
a:
~I
~II
- 0
o
.
0
1'-
.,,_0,\
(b)
I
F;,m, 11 p'
I.)
Control
PC b oard.
rmted(ACircuit
Boa r d Com
pp,o,;m",'v
4/5 size
pon,n,
shown).
Loyo"" .
.
.
,I
Layout for the
Stopwatch/T"Imer PC board . b) Layout f
.
0'
Oh, Appo;,n"
(b)
.'
IA
.. Po,";'"
'0'
Figure 12
.
,(a)
.
.
•
., for th e Appliance C .
oSltlve for th e Stopwatch/Timer. b) PoSltlve
size the
shown).
ppr.oxlmately 4/5'
Printed C·IrCUlt
.. Boards. a) P ..
2.40
on"o' ,;"";,.
The center portion of the top half of the case has been
designed for a switch assembly composed of three pushbutton switches and one slide switch_ The assembly is
made of calculator-type switches and a flex-circuit;
however, James Electronics provides neither the switches
nor the flex-circuit.
Figure 13a shows the layout of the flex-circuit; Figure
131J is a view of the flex-circuit after it has been folded
over the thin plastic insulator which is shown in Figure
13e. The insul3tor must be oriented so th3t the circular
cutouts 31-e between the two sets of four copper hexagons. The copper trace through each hex3gon forms one
cont3ct of 3 SPST switch.
,....< - - - - - - - - - - - - - - 1 1 . 6 .. - - - - - - - - - - - - - . ,
~ij-:t:' <{, 50 ohms
2'. Across Cl, with VOM on X1K scale and common
The final checkout is a repetition of the operational
checks using the flow diagrams. Each option at each
decision point in every flow diagram should be exercised.
probe to V oo , > 5k ohms, after Cl charges
3. Across R 1
< 15 ohms
4. Across C2 > 100 ohms
resolution and accuracy
5. Across the appliance control circuit line plug >10k
ohms
If a crystal is used for the time base of the stopwatch/
timer, the accuracy of the displayed count will, of
course, depend upon the particular crystal ~used. In
addition, because the MM5865 begins to count on the
leading edge of the start/stop pulse, the width of this
pulse becomes important when the event time is very
short.
If these, values of resistance cannot be found at the
points indicated, check the PC boards for opens or shorts
as necessary. Then, with a VOM connected across C2,
apply power to the stopwatch/timer; the VOM should
read slightly more than 1 vblt. Increase the resistance of
R 1 until the VOM reads 8.4 volts. SI ightly under 8.4 volts
is better than slightly over. Pressing the reset switch
should cause "0000" to appear on the display, unless the
display al ready reads "0000."
For example, when coupling the timer to an appliance,
if the width of the start/stop pulse is longer than the
event time, the appliance will not turn off at the end of
the programmed time.
If the display is blank or indicates only one or two
zeroes,' the oscillator is probably not oscillating. Rotate
C3, 360 degrees if necessary, while observing the display;
If _the display still fails to respond properly, check the
voltage at pin 20 of the MM5865; it is very close to 6
volts when the oscillator is functioning.
This is why C5 and R4 have been included. Together
they insure that the. start/stop pulse will not be longer
than 0.01 second. This pulse width should be adequate
for most users. C5 and R4 may be omitted if the length
2-44
of time the start/stop switch is to be held closed will
always be less than any timed event. When C5 and R4
are omitted, the SS switch simply connects to VSS.
As to crystal accuracy, the stopwatchltimer will lose
0.001 sec/sec if a 32.768kHz crystal is used instead of a
32.8 kHz crystal. This should be insignificant for most
users.
Also, the display resolutions which may be programmed
by on board jumper wires will be adequate for most
. users. Figure 2 illustrates the connections to the MM5865
which will cause the display to read in tens of minutes,
minutes, tens of seconds, and seconds.
will elapse between the arrival of the start pulse at pin 14
of the MM5865 and the appearance of the first digit in
the display will not be equal to the programmed display
resolution. It is possible to develop a start pulse that is
synchronized to the clock using an MM74C221 Dual
Monostable Multivibrator as shown in Figure 20. The
time constant of R 1 - C1 should be equal to the display
resolution, the time constant of R2 - C2 should be less
than the programmed display resolution,. and the time
constant of R3 - C3 should be less than the time constant
of R2-C2.
Vss
When it becomes desirable to achieve a display resolution
which allows the timing of events that are hours in
length, it is necessary to provide the MM5865 with an
external time base. This may be done by cascading two
MM5865s or by using a simple timing circuit builtaround
an LM555 timer or a digital clock. Figure 19 shows how
an MM5315 digital clock may be used as a time base for
the MM5865. The MM5315 itself uses the line frequency
as a time base. The MM5315 is shown as it would be
connected for a 60 Hz line frequency.
16
II
TO
PIN 14
OF
MM5865
J
FROM
PIN 1.S
OF
MM5865
When an external time base is provided for the MM5865
in this manner,' an external multiplexer must also be
provided. The oscillator formed with the 74C14 supplies
the desired multiplex frequency as shown in Figure 19.
R2
RI
VDO
A final note: Unless the start pulse is externally synchro·
nized to the clock (available at pin 15 of the MM5865, if
the internal oscillator is used). the amount of time which
Figure 20. Start·Pulse Synchronizer. Time constant of R 1 - C1 =
display resolution. Time constant of R2 - C2 < display resolution.
Time constant of R3 -C3 < time constant of R2 - C2.
_ - - - - - - - - - - - - - - - AC
~-----,--------------------~~----_'-------'~-VSS
----------~~~~-+----------------~.-~--~--~---.---+---VOO
R2
R3
02
C2
27~~~--------~
01
)
TO PIN 23 OF
IC2
TO PIN 15 OF IC2
TO PIN 4 OF IC6
Rl
20k!!, YOW, 5% RESISTOR
R2
220k!!, %W, 5% RESISTOR
R3
lOOk!!, %W, 5% RESISTOR
Cl
O.I~F CAPACITOR
C2· C4 O.OI~F CAPACITOR
01
lN4002 DIODE
02
8.2V ZENER DIODE
Figure 19. Using an MM5315 Digital Clock and an External Multiplexer to Provide an External Time Base for the MM5865 to Generate
a Display Resolution of 1 Minute.
2-45
PARTS LIST
Rl
R2
R3
R4
R5
R6
R7
RS
Cl
C2
C3
C4
C5
C6
C7
01,02
Tl
ICl
IC2
IC3
IC4
IC5
IC6
IC7
5kn trimpot
240n, Yt.W, 5% resistor
20Mn, Yt.W, 5% resistor
1 Mn, Yt.W, 5% resistor
100kn, Yt.W, 5% resistor
5.1 kn, Yt.W, 5% resistor
4.7kn, v..W, 5% resistor
10kn, lW, 5% resistor
470 - 1OOOm F, 25 V capacitor
10mF, 25WV o c solid tantalum capacitor
6 - 25pF variable capacitor. Sprague OT,.,8
4 - 30pF may be used.
25 - 27pF, disc ce~amic capacitor
0.01 m F disc ceramic capacitor
100mF, 25WVoc capacitor
0.05mF, 200WVoc capacitor
IN4003
10- 16.5 V AC @ 300mA ~ransformer
LM317T voltage regulator
MM5865 universal timer
. CD14511 decoder/driver/latch
OS8877 or OS75492 digit driver
RA07 - 150 resistor array
74C02 quad 2·input NOR gate
CA3059 zero voltage switch
NSB5411
------
I"~
HEPRl723
1 A fast or normal blow fuse
32.8 kHz crystal (32.768 kHz can be substi·
tuted. Timer will lose about 35 sec in 11 hr
20min of use.)
Sl,S3,S5 SPST, NO, momentary pushbutton switches;
part of flex-circuit switch assembly.
SPST slide switch; part of flex·circuit switch
S2
assembly.
S4
OPOT, ceriter OFF toggle switch
S6-S9
SPST, NO, momentary pushbutton switches
S10
7 - 12 position rotary switch - Centralab
PS-l0l or Alcoswitch MRC·l-l0.
Sll
SPST toggle switch
S12
SPOT toggle switch (optional)
~isplay
National Semiconductor NSB5411 4-digit
multiplexed display.
Heat Sink TO·220 heat sink. Two needed.
Misc.
16 display mounting pins (strip of 16 pins);
1 case; Clock/Instrument (available from
James Electronics); 1 flex·circuit; 1 flexcircuit insulator; 2 Tinnerman nuts, #6;
fuseholder; appliance control box, #LMB
C.R.-234; 115V AC chassis mounting socket;
miniature jacks; phone cable (shielded); IC
sockets.
Triac
Fl
XTAL
4 FULL DIGITS
3.00"------.!.,
RED FACE PLATE
••
FRONT VIEW
SIDE VIEW
PIN CONNECTIONS
ANODE G -PIN
ANODE F -PIN
ANOOE E -PIN
ANODE 0 -PIN
ANODE A -PIN
ANODE C -PIN
ANODE B -PIN
ANODE AM/PM INDICATOR -PIN
1
2
3
4
5
6
7
8
PIN 16PIN 15PIN 14PIN 13PIN 12PIN 11PIN 10PIN 9-
ANODe COLON TOP
CATHODE 5
CATHODE 4
CATHODE 2 AND 3
CATHODE 1 AND AM/PM
LlGHTSENSDR
LIGHT SENSOR
ANODE COLON BOTTOM
SEGMENT
DESIGNATION
Figure 21. Dimensions and Pin Connections for the National Semiconductor Corp. NSB5411 4·Digit, Multiplexed Display. Mounting
holes fora photocell are included on the display board.
2-46
I
~.
Electronic Organ Circuits
MM5554 frequency divider
genera I description
The MM5554 frequency divider provides six stages
of binary division to produce six octave-related
outputs of an electronic musical instrument tone
generator. Each divider stage consists of an asynchronous,De-coupled flip-flop. The six stages are
internally connected in cascades of one, two, and
three fl ip-flops. Each fI ip-flop drives a push-pull
output buffer, which provides low output impedance in both logic states. Two of the internal
cascades also provide trigger outputs for use in
cascading the divider stages. The timing diagram
shown results from connecting the same input
trigger to all three inputs.
chromatic frequency generator; output characteristics and power supply requirements are compatible. The MM5554 is packaged In a 14-lead
dual-in-line package.
features
•
0 to 500 kHz toggle frequency
•
1-, 2-, 3-stage partitioning
applications
The MM5554 complements the MM5555/MM5556
•
Electronic organs
•
Electronic music synthesizers
•
Musical instrument tuners
logic and connection diagra":1s
Typical Organ Tone Generator
2.126MHr
> - - - - - - -....- - - - - - - - - - ,
-21V>-----......--+--------------.-I---+--------.
TRIGGER INPUT
~~:g~::~~
GENERATOR
12Mf~~:~Ll
FREQUENCY
DIVIDERS
IS OUTPUT fRUUENCIUTO
t-------+---------,
CHROMATIC
FREQUENCY
GENERATOR
15 OUTPUT FREDU(NCIESTO
KEYSWlTCHINGCIRCUITRY
output details (2.12608-MHz input)
MM5555
NOTE
DIVISOR
MM5556
OUTPUT
FREQUENCY
E.T.S:
FREQUENCY
CENT
ERROR
C8
508
4185.20
4186.01
-0.326
C9
254
8370.39
837202
-0326
B8
269
7903.64
7902.13
'0.321
.0.295
A =8
285
7459.93
7458.62
AS
302
7040.00
7040.00
G =8
320
6644.00
6644.88
G8
. 319
627162
6271.93
NOTE
-0.221
-0082
3-4
DIVISOR
OUTPUT
FREQUENCY
E.T.S.
FREQUENCY
CENT
ERROR
F =8
359
592223
5919.91
'0.658
F8
380.5
5587.60
558765
-0017
E8
403
5275.63
5274.04
'0.507
0=8
427
4979.11
4978.03
'0364
08
452.5
4698.52
4698.64
-0.042
C =8
479.5
443395
4434.92
-0.368
s:
s:U1
absolute maximum ratings
Clock Generator Voltage (V GG)
Logic Supply V~ltage (V oo )
Buffer Supply Voltage (V ss)
Trigger Input Voltage (V IT )
Power Dissipation (Po)
Storage Temperature (Ts)
Operating Temperature (T A)
i
U1
U1
U1
0.3V to -33V
0.3V to -25V
0.3V to -18V
0.3V to -18V
800mW
-55° C to +100° C
O°C to +70°C
r
electrical characteristics
T A within operating range (V GG = -27V ±2V, Voo = -14V ±1 V, Vss = -10V. ±0.5VI. unless otherwise noted.
PARAMETER
SYMBOL
MAX
MIN
TYP
7.0
2126.08
Trigger Input
Frequency
UNITS
2200
Capacitance
kHz
7.0
Rise and Fall Times
(10% to 90% at 2.2 MHz)
pF/pkg
30
Pulse Width (at -5.0V)
pw
Logical Low Level
-16
1
(T=-)
0.6T
O.4T
fiT
o
0.3
V
-10
-8.0
V
-2.0
Logical High Level
ns
Leakage Current
1.0
Buffer Outputs: (loaded 20 kD to
ground and, 20 kD to V ss,
TA ~ 25°C)
Logical High Level
/lA
o
-1.0
V
-8.0
Logical Low Level
V
C8 Duty Cycle
50
%
C #8 thru C9 Duty Cycle
30
%
Supply Currents: (no output loads,
TA = 25°C) .
Clock Generator SLipply
IGG
Logic Supply { MM5555
MM5556
Buffer, Supply
100
100
.. 1.5
mA
3.5
34
40.
25
16
22
Iss
mA
mA
/lA
typical performance characteristics
I DO vs Ambient Temperature T A
100 vs VDD
=2.2 MHz
V'TL =-12V
fIT
42
ct
oS
c
c
--t--_
-25 < VGG < -3~
Vee -; -15V- .
38
34
1"--__
3D
26
MM5556
MM5555
22
18
-10
o
10
20
3D
40
50
60
70
-12
TA - TEMPERATURE (OC)
-13
-14
Voo (V)·
3·5
-15
-16
g
Electronic, Organ Circuits
MM5559 serial-to-parallel converter
general description
applications
The MM5559 serial-to-parallel converter provides 33 bits
of conversion .in a single package. A serial output facilitates cascading these devices to provide larger conversions.
•
Matrix displays and printers
•
Musical instrument keyboard/tone generator interface
controllers
features
•
33 Parallel outputs
•
•
Serial output
DC-to-250 kHz operation
log ic and connection diagrams
Dual-In-Line Package
40
VGG
CLK
SERIAL
DATA
OUTPUT
VDD
VSS
DATA IN
DATA OUT
BIT 1
TRANSFER ENABLE
BI12
BIT 33
BIT32
(~t~ -+'......---11--------4......
TYPICAL
OUTPUT
I
Vo EXTERNAL
LOAD,
~I
(Vss-~~v'l--+ X
,--- .... ---'
BIT 4
BIT 31
BIT 5
BIT30
BIT6
BIT29
BIT7
BIT 28
BITS
BIT27
BIT 9
BIT 26
BIT 10
BIT25
BIT 11
BIT 24
BIT 12
BIT 23
BIT 13
BIT22
BIT 15
BIT 20
BI121
OUTPUT LOAO
REFERENCE
VOLTAGE
(VSS TO VSS-30V)
'BIT 16
21
BIT 17
33-Bit Serial-to-Parallel Converter
TOP VIEW
Order N.umber MM5559N
See Package 24
timing diagram
CLOCK
,
OATA IN
DATA OUT
(SERIAL)
TR~ !~ ~
lld_P._K-':_IP_d_P___________
__________
DATA OUT
(PARALLEL) ____________________- J
3-6
BIT 19
BIT 18
s
s
absolute' maximum ratings
Voltage At Any Pin
Voltage At Any Output Pin
Operating Temperature
-55°C to +100°C
300°C
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
VSS + 0.3 to VSS - 25V
VSS + 0.3 to VSS - 33V
o°c to +70°C
(J'1
(J'1
(J'1
CJ:)
dc electrical characteristics
TA within operating range, Vss = OV, VDD = -10V, ±10%, VGG = -20V ±10%, output load reference voltage =
OV to -30V (via external load resistor)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Data Input Voltages
Logic High Level
VSS-2.2
VSS
V
Logic Low Level
VSS-ll
VSS-7
V
Logic High Level
VSS-1.0
VSS-ll
VSS
VSS-B.6
V
Logic Low Level
Clock and Transfer Enable Input Voltages
V
pF
Input Capacitance
7
Input Leakage Current
10
IlA
250
kHz
o
Duty Cycle = 50%
Clock Input Frequency
Rise and Fall Times
0.2
VSS-2.2 through VSS-B.6
IlS
Transfer Enable Input
Pulse Width
Time at VSS-B.6
1.6
IlS
0.2
Rise and Fall. Times
IlS
Parallel Outputs
Output Voltage
10 = 2 rnA
Leakage Current
T A = 25°C, Vo = VSS-30
V
VSS-2
10
IlA
Serial Output Voltages
Logical High Level
Loaded 56 kit to VDD
VSS-2
VSS
V
Logical Low Level
Loaded 560 kit to VSS
VDD
VSS-B
V
Power Supply Currents
Drain Supply, 100
(Note 1)
Gate Supply, IGG
7.5
10
Il)A
20
rnA
Note 1: The magnitude of IGG is modulated by the parallel output data; the current is inversely proportional to the number of outputs
that are higr (sourcing current). The tYPi~al value of 7.5 rnA is representative of an altern.atin g l's and O's output pattern.'
ac electrical characteristics
PARAMETER
tds
Data Setup Time
TYP
CONDITIONS
MIN
MAX
UNITS
Referenced from VSS - 7 on Data In
0.4
Ils
to VSS - B.6 on Clock In
tdh
Data Hold Time
ttd
Transfer Delay
tw
Transfer Strobe Width
Referenced from VSS - B.6
0.2
IlS
0.6
IlS
1.6
IlS
Propagation Delay
tpds
tpdp
Serial
Parallel
High·to-Low (VSS to VDD)
3.0
IlS
Low-to-High
1.2
IlS
Low-to-High with 10 kU Load
1.2
IlS
3·7
DI
Electronic Organ Circuits
MM5823, M.M5824 frequency dividers
general description
These frequency dividers 'provide six stages of binary
division to produce six octave-related outputs of an
electronic musical instrument tone generator. Each
divider stage consists of an asynchronous, dc-coupled
flip-flop .
The MM5823 and MM5824 complement the MM5832,
MM5833 and MM5555, MM5556 chromatic frequency
generators; output characteristics and power supply
requirements are compatible. The MM5823 and MM5824
are packaged in a 14-lead dual-in-line package.
. The six .stages of the MM5823 are internally connected
in cascades of two, one, one, and two flip-flops. Each
flip-flop drives a push-pull output buffer which provides
very low output impedance in both logic states.
features
• a to
•
The six stages .of the MM5824 are internally connected
in cascades of. one, two and three flip-flops. Each flip-'
flop drives a push-pull output buffer which provides very
low output impedance in both logic states. Two of the
internal cascades also provide trigger outputs for use in
cascading the divider stages.
100 kHz toggle frequency
1,2,3 or 2,1, 1,2 stage partitioning
applications
• Electronic ~rgans
• Electronic music synthesizers
•. Musical instrument tuners
The timing diagram shown results from connecting the
same input trigger to all three inputs.
connection diagrams
Dual-I n-Line Package
VOO
Dual-I n-Line Package
14 OUTPUT 28
VOG
OUTPUT lB
INPUT 1
TRIGGER
OUT.2
INPUT 2
INPUT 2
2
13 OUTPUT 2A
12 OUTPUT 1
TRIGGER 4
OUT. 1
INPUT3
NC
INPUT 4
OUTPUT 4A
10 OUTPUT 38
INPUT 3
OUTPUT 3A
Vee
Vss
Voo
TOPVIEW
11 OUTPUT 3C
INPUT 1
MM5B24
Vss
TOP VIEW
Order Number MM5823N
Order Number MM5824N
See Package 18 "
See Package 18
3-8
s
sCJ1
absolute maximum ratings
CO
N
W
Logic Supply Voltage (V GG)
Buffer Supply Voltage (V oo )
Trigger Input Voltage (V IT )
Power Dissipation (Po)
Storage Temperature (Ts)
Operating Temperature (T A)
s
sCJ1
0.3V to -30V
0.3V to -18V
O.3V to -25V
250 mW
-55°C to +150°C
O°C to +70°C
CO
N
~
electrical characteristics
T A within operating range (V GG
= -27
±1 V, Voo
PARAMETER
= -11.5 ±0.5V,
MIN
Vss
= OV). unless otherwise noted.
TYP
MAX
UNITS
Inputs:
Frequency (fiT)
100
DC
Rise and Fall Times (10% to 90%) (t r , tf)
kHz
25
Pulse Width (at 90%) (pw)
2
Logical High Level (V ITH )
-2.0
Logical Low Level (V ITL )
Leakage Current @ V ITL = -18V (IITL)
-18
IlS
IlS
Vss
-10
0.3
V
-8.0
V
1.0
Il A
Trigger Outputs: (loaded 10M ohm
to ground, T A = 25°C)
Logical High Level (V OTH)
V ss -1.5
Logical Low Level (V OTL )
,-18
V
Vss
-10
V
"
Outputs: (loaded 10k ohm to ground
and 10k ohm to V oo , T A = 25°C)
Logical High Level (V OH )
Logical Low Level (VOL)
-0.3
-0.5
Voo+0.5
Voo+0.3
V
V
Supply Currents: (No output loads, T A = 25°C) ,
Logic Supply (I GG )
2.0
Buffer Supply (1 00 )
3·9
8.0
mA
20
IlA
typical application
2000024 MHz
TRIGGER INPUT
-27V'"
-14V
-10V
T
I I,
5
76
4
3
T
2
I I, I
1
7
6
MM5833
~
5
4
3
2
1
CHROMATIC
FREQUENCY
GENERATOR
MM5832
8
9 10 11 12 13 14
I
I , I I I
I I I I , I I
I I I I
I I I I
I I I I I
I I I I I
8
9 10 11 12 13 14
I
I
\
T09 AOOol
MM5824
T
J
I I
7
6
5
J
no,
4
3
2
1
7
6
MM5824
8
~iitlll
5 4
01
4
3
2
1
3 . C ~2 08
8
7
12 (TOTAL)
MM5824
FREQUENCY
DIVIDERS
MM5824
9 10 11 12 13 14
7 6
5
9 1011121314
7
6
5
4
8
3 02
C8
85 OUTPUT FREQUENCIES TO
KEYSWITCHING CIRCUITRY
Typical Organ Ton~ Generator
timing diagram
TRIGGER
INPUT
OUTPUT
OUTPUT
11..-__. . .
L
OUTPUT - - ,..._ _ _ _ _ _.......
3-10
I
5
n
I
4
3
2
1
MM5824
~ i itlll
':"
6
L
9 10 11 12 13 14
rlilill
-=
7
6
5
4
3
2
C9
Electronic Organ Circu.its
s
s
CJ'I
00
eN
eN
MM5832, MM5833 chromatic frequency generator
general description
The National Semiconductor M'M5832, MM5833 chromatic frequency generator is an MOS/LSI frequency
synthesizer designed to generate musical frequendes.
The circuits provide thirteen semi·tone outputs, fully'
spanning the equal tempered octave. The divisors have
been carefully selected to offer excellent tuning accu·
racy. Output characteristics are fully compatible with
the MM5554, MM5823 and MM5824 Frequency Dividers.
The MM5832 or MM5833 is packaged in a 14-lead dualin-line package.
•
7 kHz to 2.1 MHz input frequency
•
Maximum error of 1.16 cent
applications
•
Celeste tone generator
•
Electronic music synthesizers
features
• . Organ tone generators
• Single-phase squarewave input
•
Chorus tone generators
connection diagrams
Dual·1 n-Line Package
14
GND
Dual·1 n-Line Package
C8
GND
·Used only for testing. Pin 4 is
normally grounded.
MM5812
MM5833
G8
TOPVIEW
TOP VIEW
Order Number MM5832N
Order Number MM5833N
See Package 18
See Package 18
". -,. 3-11
absolute
min~imum
ratings
. Clock Generator Voltage (V ~G)
,Logic Supply Voltage (V oo )
Buffer Supply Voltage (V BB )
Tri~1ger Input Voltage (V 1T )
Power Dissipation (Po)
Storage Temperature (T s)
Operating Temperature (T A)
Vss
Vss
Vss
Vss
+ 0.3V to Vss - 33V
+ 0.3V to Vss --: 25V
+ 0.3V to Vss - lSV
+ 0.3V to Vss - lSV
SOO mW
-55°C to +100°C
O°C to +70°C
electrical characteristics
TA within operating range (V GG == -27V ±2V, Vcio == -14V ±1 V, V BB == -10V ±0.5V, Vss == OV), unless otherwise noted.
PARAMETER
TYP
MIN
Trigger Input
Frequency (fiT)
2000.24
7.0
UNITS
MAX
kHz
2100
Capacitance (CIT)
7.0
pF/pkg
Rise and Fall Times (t" td
(10% to 90% at 2.1 MHz)
30
ns
Pulse Width (at -5.0V) (pw)
+0.3
Logical Low Level (V ITL)
-16
(T == l/f IT )
V
0.6T
O.4T
Logical High Level (V ITH )
o
-2.0
-S.O
V
1.0
J1A
0
-S.O
V
V
Leakage Current (IITL)
Buffer Outputs:' (loaded 20 kSl to
ground and 20 kSl to V BB, T A == 25° C)
-2.0
Logical High Level (V OH )
Logical Low Level (VOL)
, V BB
CS Duty Cycle
50
C =8 thru C9 Duty Cycle
30
%
%
I
Supply Currents: (no output loads,
T A == 25°C)
Clock Generator Supply (I GG )
1.5
3.5
mA
Logic Supply (1 00 )
16
34
mA
25
J1A
Buffer Supply (I BB )
typical performance characteristics
100 vs Ambient
Temperature T A
100 vs VOO
50
fiT
50
=2.1 MHz
fiT = 2.1 MHz
c-- Vlll =-12V
46 I - Vlll =-12V
46
42 -
;;t
42 I- -25 <;; VGG <;; -30 -+--+--+----1
Voo" -15V
38
.s
34
30
.......
;;t
-+--+--+----1
I I I I
38
~::
MJ58321MM5833 r--
_
-25 <;; VGG <;; -30
TA '= 25"C
I I .1 I
,V
221--+--+--1--+--+-+-+----1
V '"
26
221~,l
18
18
26
~~~+~~--~~~~
I
~~~~~~--~~~
-10
0
10
20
30
40
50
60
70
MM58321MM583
"1 I I I
-12
-13
-14
Voo (V)
TA - TEMPERATURE ("C)
3·12
-15
-16
J
typical application
2.00024MH.
TRIGGER INPUT > - - - - - - - - - + - - - - - - - - - - - .
-27V>--------.---+--------+--f--------------.
-14V >-------4J~---t-------..,
CHROMATIC
fREQUENCY
GENERATOR
MM5824
121TOTALI
MM5824
fREQUENCY
OIVloERS
MM5824
MM5824
C8
85 OUTPUT fREQUENCIES TO
KEYSWITCHING CIRCUITRY
Typical Organ Tone Generator
output details
(2.00024 MHz input)
MM5832
DIVISOR
OUTPUT
FREQUENCY
E.T.S.
FREQUENCY
CENT.
ERROR
C8
478
4184.61
4186.01
-0.565
C9
239
8369.21
8372.02
-0.565.
88
253
7906.09
7902.13
0.842
A#8
268
7463.58
7458.62
1.119
A8
284
7043.10
7040.00
0.740
C#8
301
6645.32
6644.88
0.112
G8
319
6270.34
6271.93
-0.424
E.T.S.
FREQUENCY
CENT.
ERROR
NOTE
MM5833
NOTE
DIVISOR
OUTPUT
FREQUENCY
F #8
338
5917.87
5919.91
-0.580
F8
358
5587.26
5587.65
-0.117
E8
379
5277.68
5274.04
1.160
D#8
402
4975.72
4978.03
-0.780
D8
426
4695.40
4698.64
-1.159
C#8
451
4435.12
4434.92
0.076
3·13
C9
Electronic Organ Circuits
MM5837 digital noise ;source
general description
The MM5837 digital noise source is an MOS/MSI
pseudo·random sequence generator, designed to produce
a broadband white noise signal for audio applications.
Unlike traditional semiconductor junction noise sources,
. the MM5837 provides very uniform noise quality and
output amplitude. The shift register starts at a random
non·zero state when power is applied. The circuit is
packaged in an 8·lead Epoxy·S mini·DIP.
•
Eliminates noise preamps
•
Self-contained oscillator
•
Single component insertion
applications
features
•
Uniform noise amplitude
•
Uniform noise quality
•
Electronic
generators
musical
rhythm
instrument
•
Music synthesizer white and pink noise generators
•
Room acoustics testing/equalization
logic and connection diagrams
Dual·1 n·Line Package
Voo
NC
OUTPUT
OUTPUT
Vss
VGG
Voo
TOP VIEW
Order Number MM5837N
See Package 17
3·14
sound
absolute maximum ratings
Optional Gate Supply Voltage, V GG
Logic Supply Voltage, Voo
Storage Temperature, Ts
Operating Temperature, T A
Lead Temperature (Soldering, 10 seconds)
Vss - 33V to Vss + 0.3V
Vss - 25V to Vss + 0.3V
-55°C to +100°C
O°C to +70°C
300°C
electrica I characteristics
TA within operating range, Vss = OV, Voo = -14V ±1.0V, VGG = -27V ±2V, unless otherwise noted.
PARAMETER
Output (Loaded 20 kn to Vss
and 20 kn to V OD
Logical "1" Level
Logical "0" Level
Logical "0" Level
CONDITIONS
MIN
TYP
MAX
UNITS
TA = 25°C
Vss -1.5
VGG = -14V ±1V
Voo
Voo
Vss
V oo +1.5
V oo +3.5
No Output Load
3
8
V
V
V
Supply Currents
100
IGG
7
mA
mA
Half Power Point
24
56
kHz
Cycle Time
1.1
2.4
Sec
".'
-
I
I
3·15
Electronic Organ Circuits
M M 5871 rhythm pattern generator
general description
The MM5871 rhythm pattern generator is an MaS/LSI
circuit, fabricated with P-channel enhancement-mode
and ion-implanted, depletion~mode devices. The PLA
implementation is programmed to produce 6 rhythm
patterns which may be combined in any manner and
provide 5 instrument-trigger outputs. Trigger output
pulse width is determined by an external RC network,
(Figure 1). A similar network, including a potentiometer,
determines tempo of the on-chip oscillator. This circuit
is packaged in a 16-pin Epoxy-B DIP, (Figure 2). Figure
3 illustrates the standard pattern coding. Figure 4 is a
programming worksheet for ordering custom patterns.
fe'atures
•
•
5 trigger outputs
•
Flexible supply voltages
•
Low power dissipation
standard patterns
•
•
Waltz (3/4)
Swing (3/4)
•
CountrylWestern (3/4)
•
March (4/4)
•
•
Latin (4/4)
Rock (4/4)
applications
On-chip tempo oscillator
•
Variable output pulse width
•
Electronic organs
•
6 rhythm patterns
•
Portable rhythm boxes
block and connection diagrams
VSS_~-----4~~~)
~~MAINING,
CIRCUITS
--+-_
VOo----~--_I_-___4....
_I_...
BASS
DRUM
WOOO
BLOCK
SWING
BONGO
ORUM
C/W
WALTZ
BRUSH
CYMBAL
LATIN
ROCK
SNARE
NOISE
MARCH
FIGURE 1.
Dual-In-Line Package
16 SWING IE)
IS
TEMPO CONTROL
14 WALTZ 101
PULSE WIOTH CONTROL
VOO
~
TIME (
ROCK IC)
Order Number MM5871 N
See Package 19
12 BRUSH NOISE
11 BONGO ORUM
6
10 WOOO BLOCK
LATIN IBI
9
MARCH IA)
TOP VIEW
FIGURE 2.
BASS ORUM
:ATTERN SELECT
INPUTS
13 SNARE NOISE)
VSS
P:TTERN
SELECT
INPUTS
]3
-,TIME
COUNTRYIWESTERN IFI
TRIGGER
OUTPUTS
s:
s:
CJ1
absolute maximum ratings
Suppiy Voltages
MIN
MAX
-33
-22
-18
-55
0
0.3
0.3
0.3
100
70
300
VGG
VOO
Input Voltage
Storage Temperature
TS
Operating Temperature
TA
Lead Temperature (Soldering, 10 seconds)
co
UNITS
-..J
~
V
V
V
°c
°c
°c
electrical characteristics
T A within operating range, VSS == OV, VOO == -14 V ±2V, VGG == -27V ±2V, unless otherwise noted.
CONDITIONS
PARAMETER
Tempo Control Input
MIN
Minimum Tempo
R to VOO == 1.1 MD
Maximum Tempo
R to VOO == 120 kD (Note 1)
Pulse Width Control Input
TYP
MAX
UNITS
C to VSS. == 0.0056 J-LF
bps
'5:.2.7
'227
bps
ms
C to VSS == 0.0056 J-LF
Rto VOO == 100 kD, (Note 1)
2
3
4
VSS-0.75
VSS
VSS+0.3
Select Inputs
Logic High Level
(Active Level)
Input Current
VIH == VSS
0.2
Logic Low Level
VOO
VOO
VOO+0.75
V
mA
V
Trigger Outputs
Logic High Level
(Active Level) (w/20k to VOO)
Leakage Current
VOL == VOO, (Note 2)
Supply Currents
VSS-0.37
VSS+0.3
-10
V
J-LA
(No Output Loads)
100
20
mA
IGG
5
mA
Note 1: Both the Tempo Control and Pulse Width Control inputs utilize external RC networks to determine tempo and strobe pulse width. Additionally. these parameters are affected by the VSS - VOO voltage. Therefore, for these tests the RC values apply to VSS - VOO ~ -14 ±0.5 volts.
Note 2: ' All trigger outputs are open-drain transistors. The active output level is therefore high, and the off condition is high impedance as indicated
by the specified leakage current.
3-17
MM5871
Device: MM5871
Customer:
Pattern: AA (Standard),
DEVICE PIN
16
15
14
6
Note 1: In this chart, "X" represents the presence of a gate in the spot.
Note 2: "X" = 1; negative logic.
FIGURE 3. Standard Pattern Coding
'C;-J
~
Device: MM5871
Customer:
Pattern:
DEVICE PIN
16
15
14
Note 1: Combination counts of 5 on 3/4 time are not programmable, i.e" no gates in "555" section.
Note 2: In this chart, "X" represents the presence of a gate in the spot.
Note 3: "X" = 1; negative logic.
FIGURE 4. Programming Worksh'eet For Ordering Custom Patterns'
6
8
Electronic' Organ Circuits
MM5891 MOS top octave frequency generator
general description
Voo
The MM5891 top octave frequency generator is an
MOS/LSI frequency synthesizer designed to generate
musical frequencies. The circuit provides 13 semitone
outputs, which encompass the equal tempered octave.
The divisor set approximates the 12V2 semitone interval
to an accuracy of ± 1.16 cent.
pins. Chip layout also isolates the clock and output
buffer areas. Additionally, the outputs are slew-limited
to reduce R F spectral content of the output signals.
features
Low threshold voltage enhancement-mode and depletionmode devices are' utilized; the MM5891 therefore
operates from a single, wide range
power supply.
Power dissipation is less than 600 mW. The circuit is
packaged in the 16-pin Epoxy B dual-in-line package.
Potential RFI emission of the input clock is minimized
by positioning the clock input between the VSS and
block diagram
•
Single power supply
•
Broad supply voltage operating range
•
Low power dissipation
•
High output drive capability
MM5891AA-50% output duty cycle
MM5891AB-30% output duty cycle
connection diagram
Dual-In-Line Package
o--.D8
16
VSS
15
CLOCK
14
voe
13
-0451
~478
-;-239
-;-253
~268
2.00024 MHz
CLOCK
-0426
-0402
D-+A8
-;-379
-;-319
-;-358
-;-338
TOP VIEW
Order Number MM5891 N
See Package 19
OUTPUT
DRIVERS
3-19
absolute maximum
r~tings
recommended operating conditions
(O°c
Voltage on Any Pin Relative to VSS
Operating Temperature (Ambient)
Storage Temperature (Ambient)
electrical characteristics
+0.3V to -20V
O°C to +50°C
-40°C to +100°C
Supply Voltag.e (VSS)
Supply Voltage (VOO)
o°c ~ T A ~ 50°C; Vss
= 0, VOO = -11
PARAMETER
VIH
Input Clock. High
VIL
Input Clock. Low
:s; T A:S; 50°C)
TYP
0
Input Clock Frequency
Input Clock Rise and Fall Times. 10% to 90%
0
-11.0
100
MAX
-1.0
VOO+1.0
fl
MAX
o
UNITS
V
-16.0
V
to -16V unless otherwise specified
MIN
tr. tf
MIN
VOO
2000.240
2500
30
UNITS
V
V
kHz
ns
at 2.5.MHz
ns
Input Clock "ON" and "OFF" Times at 2.5 MHz
200
CI
I nput Capacitance
5
VOL
Output, Low at 0.70 mA
VOO+1.5
VOO
VOH
Output. High at 0.75 mA
VSS-1.0
NSS
V
t ro • tfo
Output Rise and Fall Times. 500 pF Load
2500
ns'
tON
Output Duty Cycle
tON. tOFF
100
250
10
pF
V
MM5891AA
50
%
MM5891AB--: (Pin 16.50%)
30
%
Supply Current
24
3·20
37
mA
switch ing time waveform
VSS--------~--------~--------~-------------------
V I H - - -__
10%
VIL
-----=-t.:..:...~---.IJ
typical performance characteristics
ISINK vs VOUT
ISOURCE vsVOUT
-18
-16
-4
-14
-12
-3
t--t--t-=f,..,......."""'~ZR-~~
~ -10
o
:>
I-
::::>
0
-8
:>
-2
-6
-4
-1
-2
o
o
o
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
o
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
SINK CURRENT FROM CHIP (VSS)
SINK CURRENT TO CHIP (Voo)
output loading
Output Loading tro Test
Output Loading tfo Test
-16
-16
Voo
Voo
20k
MM5891
VSS
.....-
20.75k
...J\,IV\J- -16 .
MM5891
Vss
T500PF
3·21
TV Circuits
MM5318 TV digital clock
general description
features
The MM5~18 digital clock is a monolithic MOS
integrated circuit utilizing P-channel low-threshold,
enhancement mode devices. The circuit contains all the
logic required to give a 4 or 6-digit, 12 or 24-hour display from a 50 or 60 Hz input. The digit select inputs
enable an external digital system to select wh ich digit
will be available at the BCD and 7-segment outputs.
An example of this is a television receiver. By using the
MM5318 with a MM5841 in a television receiver, the
time of day can be displayed with the TV channel
selected on the TV screen. The MM5841 determines
what digit it requires from the MM5318, where on the
screen it will be displayed and presents the inform"ation
to the TV receiver., The MM5318 is packaged in a 28lead dual-in-line package.
• 'II 12 or 24 hour operation
•
50 or 60 Hz input
•
4 or 6-digit display
•
BCD outputs
•
Digit select inputs
•
Leading zero blanking in 12-hour mode
•
High output currents for simplified display interfacing
•
Single power supply
applications
•
TV time display
•
Computer real time clock
block and connection diagrams
HOLO
SLOW
12124 HOUR
SelECT
FAST
50/60 Hz
INPUT
MULTIPLEXED
mOUTPUTS
OX
DY
OZ
'--_ _..r--y
MULTIPLEXED
7·SEGMENT
OUTPUTS
DIGIT ENABLE
OUTPUTS
FIGURE 1. Block Diagram
Dual-I n-Line Package
VDD
BCOl
MULTIPLEXEO
BCD OUTPUTS
(NEGATIVE
TRUE)
DZ
2
DY
} ,'On
SELECT
LINES
{
Brif4
OX
8Cif2
MI
BCii1
MID
HI
HID
SI
MULTIPLEXED
7SEGMENT
OUTPUTS
12124 HOUR SelECT
50/60 Hz SelECT
TOP Vltw
FIGURE 2. Connection Diagram
4-2
DIGIT
ENABLE
OUTPUTS
Order Number MM5318N
See Package 23
absolute maximum ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
electrical characteristics
PARAMETER
Power Supply Current
VSS + 0.3V to VSS - 20V
O°C to +70°C
-65°C to + 150°C
300°C
TA within operating range, VDD = OV, VSS = 14V ±10%, unless otherwise'specified.
CONDITIONS
MIN
VSS = 14V (No External Output Loads
TVP
4
MAX
UNITS
30
mA
All BCD Outputs at Logical "1")
50/60 Hz Input Frequency
dc
50 or 60
60k
Hz
VSS-2
-2
VSS
VSS
4
V
VDD
2000
ns
50/60 Hz Input Voltage
Logic "1"
Logic "0"
Digit Select Input Delay
All Logic Inputs
Logic "1"
400
V
Internal 20k, Resistor to VSS
(Except Digit Select Inputs)
Logic "0"
VSS-l
VSS
VSS
V
-2
VDD
4
V
BCD Outputs
Logic "1"
Output Voltage at VSS ..:: 2
2
10
mA source
Logic "0"
0.01 mA Sink
VDD
0.3
V
7-Segment Outputs
Output Voltage at VSS - 2
Logic "1"
2
Logic "0"
20
mA source
0.01
mA leakage
VSS
15
mA sink
Digit Enable Outputs
Logic "1"
0.1 mA Source
Logic "0"
Output Voltage at VSS - 2
VSS-0.3
5
V
functional description
A block diagram of the MM5318 digital clock is shown
in Figure 1. A connection diagram is shown in Figure 2.
Unless otherwise indicated, the following discussions are
based on Figure 1.
Switching any of these inputs (one at a time) to VDD
results in the desired time setting function. Fast set
advances hours information at one hour per second and
slow set advances minutes information at one minute per
second. The Hold Input stops the clock to the prescale
counter.
50 or 60 Hz Drive: This input is applied to a Schmitt
Trigger shaping circuit which provides approximately
5V of hysteresis and allows using a filtered sinewave
input. A simple RC filter such as shown in Figure 6
should be used to remove possible line voltage transients
that could either cause the clock to gain time or damage
the device. The shaper output drives a counter chain
which performs the timekeeping function.
12 or 24 Hour Select Input: This input is used to
program the hours counter to divide by either 12 or 24,
thereby providing the desired display format. The 12hour display format is selected by connecting this input
to VDD; leaving the input unconnected (internal 20 kn
pull-up) selects the 24-hour format.
Digital Select Inputs (OX, DV, DZ): These three inputs
are used to determine what digit will be displayed, Table
I shows the code for each digit. A logic "1" is when the
pin is held to VSS. When the pin is tied to VDD, a logic
"0" results.
50 or 60 Hz Select Input; This input programs the
prescale counter to diili'dEi by either 50 or 60 to obtain
a 1 Hz timebase. The counter is programmed for 60 Hz
operation by connecting this input to VDD. An internal
20k pull-up resistor is common to this pin; simply leaving
this input unconnected programs the clock for 50 Hz
operation.
Output Circuits: Figure 3 illustrates the circuit used for
the BCD outputs. Figure 4 shows the circuit used for the
7-segment outputs. The digit enables output circuit is
shown in Figure 5. Figures 6 and 7 illustrate typical
applications for the MM5318.
Time Setting Inputs: Both fast and slow setting inputs,
as well as a hold input, are provided. Internal 20 'kn
pull-up resistors provide the normal timekeeping function.
4·3
co
M
Ln
functional description
(Continued)
~
~
TABLE I. Digit Select Code
DIGIT
SELECT
LINES
DIGIT DISPLAYED
S1
S10
*
M1
M10
*
H1 H10
DX
1
0
0
1
1
0
0
1
DY
1
1
0
0
0
0
1
1
DZ
0
0
0
.0
1
1
1
1
*Output blanked
output circuits
"+t~'" , " ' +
VSS
n
~S
I
VDD
3k
VDD
L7.SEGMENT
(OPEN DRAIN)
OUTPUT
VDD
FIGURE 3. BCD Output Circuit
FIGURE 4. 7·Segment Output Circuit
FIGURE 5. Digit Enable Output Circuit
typical applications
+12V
+12V
VIDEO
OUTPUT
FASTSETE~
SLOW SET
HOLO
-----\
--1-.
ovJLJL
-----116
H~""'I\r-'" VERTICAL RETRACE
HORIZONTAL r--....t-...- - f
POSITION
ADJ ......JI,/,'I(I'v. . .-\
F==--------------JlJL
VERTICAL ....-M.........;;.;;.~
POSITION
ADJ .....
~
1V.%rv-...
DIGIT SELECT
DM74COO
~-----+':":12::-:V-::'F:::OR~8:-:D~IG~IT:------'"
GND FOR 5 DIGIT
----..I
MODE CONTROL .....---~+1~2V~F~O~R~C:':'HA:-:N::-:N":":EL~A:-::N~O-:::TI::-:M~E
GND FOR CHANNEL ONLY
FIGURE 6. TV Channel and Time Display
4-4
typical applications
(Continued)
AC INPUT
+14V
lOOk
lN914
19
MM5318
....----414
....----413
Voo
OV
FIGURE 7. Typical Application
4·5
-TV Circuits
MM5320 TV camera sync generator
general description
features
The MM5320 TV camera sync generator is an
MOS, P-channel enhancement -mode, LSI chip
designed to supply the basic sync functions for
either color or monochrome 525 line/60 Hz
interlaced camera and video recorder applications.
Required power supplies are +5V and -12V, or
any other combination resulting in Vss - 17V. All
inputs and outputs are TTL compatible without
the use of external components.
.. Multi-function gen lock input provides flexible control of multiple camera installations
•
16 lead dual-in·line- package
•
Conventional +5V, -12V power supplies
•
Uses 2.04545 MHz or 1.260 M Hz input reference
Fi-eld -indexing provided for VTR applicat-ions
•
•
Color burst gate and sync allow stable color
operation
logic and connection diagrams
HORIZOR~~~~
0-------4--------.
COLOR BURST
GATE OUT
CLOCK
HORIZONTAL
DRIVE OUT
INPUT
COLOR BURST
SYNC OUT
DIVIDER
CONTROL
COMPOSITE
SYNC OUT
COMPOSITE
BLANK OUT
RESET
CONTROL
VERTICAL
RESET
VERTICAL
DRIVE OUT
FIElD
INDEX
Dual-I n-Line Package
16
VGG
DIVIDER CONTROL
COMPSYNCOUTPUT
HzORIVE
CLOCK INPUT
COMPBLANKING
COtORBURSTSVNC
VERT RESET
12
COLOR BURST G~TE
10
NC
VERT DRIVE
RESET CONTROL
FIElD INDEX
Vss
TOPVIEW
Order Number MM5320N
See Package 19
4-6
s:
s:U1
absolute maximum ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Lead Temperature (Soldering. 10 seconds)
CN
Vss + 0.3 to Vss - 22
oOe to +70 o e
o
-65°C to +150 e
300°C
N
o
dc electrical characteristics
T A within operating temperature range Vss = +5.0V ±5%. VGG = -12V ±5%. unless otherwise stated.
PAR~METER
CONDITIONS
MIN
Input Levels
Logical High Level (V IH )
Logical Low Level (V IL )
TYP
Vss - 1.5
Vss - 18
MAX
UNITS
Vss + 0.3
Vss - 4.2
V
V
Input Leakage
V 1N = -10V, T A = 25°C,
All Other Pins GND
0.01
0.5
/lA
Input Capacitance
V IN = OV, f = 1.0 MHz,
All Other Pins GND (Note 1)
3.5
6.0
pF
Clock Input Leakage
V IN = -10V, T A = 25°C,
All Other Pins GND
0.5
/lA
Clock Input Capacitance
V 1N = OV, f = 1.0 MHz,
All Other Pins GND (Note 1)
3.5
6.0
pF
Vss - 11
Vss
0.4
Vss - 9.0
V
V
V
Output Levels
Logical High Level (V OH )
Logical Low Level (Vod
Logical Low Level (Vod
Power Supply Current (IGG)
ISOURCE = -0.5 mA
ISINK = 1.6 mA
MOS Load
2.4
Vss -12.5
TA = +25°C, VGG = -12V
q,pw = 235 ns, Vss = +5.0V
Input Clock Frequency = 2.04545 MHz
24
36
mA
ac electrical characteristics
T A within operating temperature range Vss = +5.0V ±5%. V GG = -12V ±5%. unless otherwise stated.
PARAMETER
Input Clock Pulse Width (q,pw)
Input Clock Pulse Width (q,pw)
CONDITIONS
UNITS
MIN
TYP
MAX
190
235
280
Input Clock Frequency = 1.26 MHz
(Note 3)
520
545
570
Within 400 ns after the Falling Edge of
Master Clock (Figure 5)
Rise and Fall Time = 20 ns
500
600
800
ns
500
500
750
750
ns
ns
600
700
ns
Input Clock Frequency
q,t" q,t, = 20 ns
= 2.04545 MHz
q,t, = q,t, = 20 ns
Horizontal Reset Pulse Width
Output Propagation Delay (t pd )
Logical'High Level (V OH )
Logical Low Level (Vod
Field Index Pulse Width
Capacitance at the Output
(Figure 5)
= 15 pF
Within 400 ns after the Falling Edge of
Master Clock (Figure 5) (Note 2)
Rise and Fall Time = 20 ns
500
Note 1: Capacitance is guaranteed by periodic testing.
Note 2: Field index output available only for master clock of 1.26 MHz.
Note 3: If field index is not required the clock pulse width is 300 ns ~ PW ~ 570 ns
4·7
II
o
N
M
It).
functional description
~
~
EXTERNAL CONTROL LEVELS
Horizontal Reset occurs for Logic "0," this resets
the.horizontal counter to a state shown in Figures
2 and 3.
serration pulse (eleven 0.5H tim'e intervals from
leading edge of Vertical Blanking). Refer to the
reset table above. The horizontal divider will
always be reset to a position which is 8 input clock
pulses from the leading edge of the serration gate
in the horizontal timing scheme (Figure 2 and 3).
The generator is reset to the odd field (field one).
The Field Index output pulse occurs onc~ each
odd field at the leading edge of Vertical Blanking.'
It can be used to reset, or "gen-Iock," similar sync
generator chips by connecting it to their Vertical
and Horizontal Reset inputs.
Vertical Reset occurs for Logic "0," th is resets the
vertical counter to a state determined by reset
control input as shown below:
RESET I
CONTROL INPUT
PERMITS THE VERTICAL
COUNTER TO RESET TO THE:
o
V'H. (V ss )
V'L' (V GG )
th count
11 th count
Logic "0" = V IL
Logic "1" = V IH
OUTPUTS
Divide select input'" V IL , (V GG ) for master clock
frequency of 1.26 MHz. "
The generator supplies the following standard output functions: Horizontal Drive Out, Vertical
Divide select input'" V I H, (V ss) for master clock
frequency of ?04545 MHz.
'Drive Out, Composite 'Blanking Out, Composite
Sync Out and the Color Burst Gate.
INPUTS
In addition, Field Index and Color Burst Sync
outputs are provided. The Field Index identifies
the odd field, or field one, by occurring for two
'clock periods at the leading edge of Vertical Blanking in that field. Thus, its rate is 30 Hz. As de. scribed 'above, it can also be used to "gen-Iock"
other sync generator 'ch ips.
The u'ser may select either of two input clock
frequencies by properly programming the Divider
Control pin. In one case the input frequency is
2.04545 MHz; which is 14.318180 MHz divided
by seven. The other is eighty times the horizontal
frequency, or 1.260 MHz. The divider control will
be programmed by connecting it to V IH (V ss ) and
V 1L , (V GG ) respectively.
The Color Burst Sync output signal occurs at half
the horizontal rate with the same timing as the
Color Burst Gate output. It may be used to sync
the color burst as it will have the same delay
characteristics as the other outputs (including, of
.course, the Color Burst Gate) - the color burst
sync is present during the vertical interval.
There are separate Vertical and Horizontal Reset
inputs which allow directly resetting the appropriate divider(s) by a control pulse generated by
external means. Both horizontal and vertical divid-,
ers may be reset simultaneously by connecting
the Vertical and Horizontal Reset pins together
and driving them with the same reset signal. Actual
resetting of the vertical divider is to either of two
states, depenqing upon the state of, the Reset
Control- input; to zero, or to the fifth vertical
Differences in phasing between outputs are minimized by the use of identical push-pull output
buffers clocked by the internal clock.
typical performance characteristics
Typical IGG vs Power Supply
Voltage (VSS - VGG)
TypicallGG vs Temperature
34
32
flI
30
;{
28
E
26
CLOCK FREQUENCY = 2.04545 MHz
28 -T =25°C
A
r- ¢pw = 235 ns
.I
r- Vss = 5.0V
I
r-,vGG = -12V
CLOCK FREQUENCY = 2.04545 MHz
TA =25°C
¢pw = 235 ns
Vss = 5.0V
VGG = 12V
;{
I'
E
24
""
24
I
I
I
22
V
~
V
/
I
I
I --l
20
20
,
.~
I
_.1'
18
-50
-25
25
50
75
100
16.15
17
Vss - VGG IV)
AM81ENT TEMPERATURE 1°C)
4-8
I
17.85
I
HORIZOONR~~~::
r±;H,
r 111 1TI T1 rl-I TTTTl TT III r1-1 11' 1-]-1 111 nl T'
r-,
1"I
en
~
n
...
':r
:s
COLOR BURST
GATE
+5
OV
COLOR BURST +5
SYNC OV
, I I T - ----T I-nIT In lTI 11 T--~-- - -- Il' '-I
to
...
3CI)
, , , , , ,-, --I -, 11- r--li'T l-'-l-r , -,
1
~
Q)
<
CI)
~
VERTICAL
DRIVE
+5
OV
,..
9H
I
I
I
..
!
I
:
I
I
I
\"
I
I ..
~I
FIELD
INDEX
COMPOSITE
BLANKING
+5
OV
+5
OV
262,5H
I..
..
~
9H
_
I
I
I
I
I
I
I
I
o...
3
en
525H
I I I I r"
21H
..
-+- -+- ----+- --+3H
3H
SER·
r1L..-_~~_ _
--t-
3H
EDUALI,
3H --+-3H
EQUALI·
-+-
3H----t--
EDUALI·
COMPOSITE +5
SYNC
OV
llllJ--·---------,~
----j
H/2
!-FIGURE 1.
III
oZ E911\111\1
switching time waveforms (con't)
.--~.-
.. 13T.",.1011H
HORIZONTAL DRIVE
~-------
12T. >.1694H . - - - . - - - .
HORIZONTAL BLANKING
COLOR
BURST GATE
FIGURE 2. Horizontal Timing Master Clock = 2.04545 MHz
EQUALIZATION GATE
==j
i
6T. - O.OISH
F
HORIZONTAL SYNC
-----1
.:lr-------------
BT.'O.lH
HORIZONTAL
DRIVE
I
I
BACK PORCH
6T.'0.0ISH
I
I""'~__ _ _ _ _ _ __
14T.-O.l1SH
3T.' O.OlISH
FIGURE 3. Horizontal Timing Master Clock' = 1.26 MHz
t--
IH PERIOD
l1 .S\HZ· 0.03115 ...
1I1f1
~~_ _~_ _ _ _ _ _ _ _ _V~E~RT~IC~AL~B~LA=N=KI~NG~_ _ _ _ _ _ _ _ _ _~~~
ZlH
l:--=::3H - -
-
+
3H
-+----3H
EQUALIZATION GATE
~ERRATION GATE
3H
VERTICAL DRIVE 110 HORIZONTAL SYNC INHIBIT
9H
MASTER CLOCK PERIOD
(ONCE EACH 000 FIELD)
FIELD INDEX
FIGURE 4. Vertical Timing
4·10
==:::=r-
s:
s:U1
switching time waveforms (con't)
W
N
o
MASlERCLOCK
V~---+------~r-----------OUTPUT
IV" - gVI---+------J~~..;.;.;-------+Vss
RESET PULSE
FIGURE 5.
typical application
'SV
v~
HORIZ
RESET
l·vu.nICAl
RESET
13
MMS32D
I
COMPOSITE
SYNC INPUT
DIVIDE
SelECT
VGG
TTL
-12V
L _ ~ND..J
TTL Interface
4-11
TV Circuits
MM5321 TV
c~mera
sync generator
general description
features
The MM5321 TV camera sync generator is aMOS,
P-channel enhancement mode, LSI chip designed to
supply the basic sync functions for either color or
monochrome 525 line/60 Hz interlaced camera and
,video recorder applications. Required power supplies
are +5V and -12V, or any other combination resulting
in VSS - 17V. All inputs and outputs are TTL compatible without the use of external components. Military
and commercial temperature ranges are available.
• Multi-function gen lock input provides flexible control of mUltiple camera installations
• 16-lead dual-in-line package
• Conventional +5V, -12V power supplies
•
Uses 2.04545 MHz or 1.260 MHz input reference
•
Field indexing provided for VTR applications
• Color burst gate and sync allow stable color operation
logic and connection diagrams
HORIZONTAL RESET
CONTROL
HORIZONTAL
0------------....,
COLOR BURST
GATE OUT
O-------i>-------,
RESET
CLOCK
HORIZONTAL
INPUT
DRIVE OUT
COLOR BURST
SYNCOUT
DIVIDER
CONTROL
COMPOSITE
SYNC OUT
COMPOSITE
BLANK OUT
VERTICAL
RESET
CONTROL
VERTICAL
RESET
VERTICAL
DRIVE OUT
1
FiElD
INDEX
Vss
Dual-In-Line Package
vGG
16
DIVIDER CONTROL
15
Hz DRIVE
CLOCK INPUT
14
COMP BLANKING
Hz RESET
13
COLOR BURST SYNC
VERT RESET
12
COLOR BURST GATE
11
VERT ORIVE
10
OPEN
VERTICAL RESET
CONTROL
HORIZONTAL RESET
CONTROL
COMP SYNC OUTPUT
VERT INDEX
VSS
TOPVIEW
Order Number MM5321 N
See Package 19
4-12
s:
s:U1
absolute maximum ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
W
N
VSS + 0.3 to VSS - 22
DoC to +70°C
-65°C to +150°C
300°C
dc electrical characteristics
T A within operating temperature range Vss = 5V ±5%, V GG = -12V ±5%, unless otherwise stated.
CONDITIONS
PARAMETER
MIN
MAX
UNITS
Input Levels
VIH
Logical High Level
VSS-1.5
Vss+0.3
V
VIL
Logical Low Level
VSS-18
VSS-4.2
V
VIN = -10V, T A = 25°C,
Input Leakage
0.5
/lA
6
pF
0.5
/lA
6
pF
All Other Pins GND
I nput Capacitance
VIN=OV,f=l MHz,
All Other Pins GND, (Note 1)
Clock Input Leakage
VIN = -10V, T A = 25°C,
All Other Pins GND
Clock Input Capacitance
VIN = OV, f = 1 MHz,
All Other Pins GND, (Note 1)
Output Levels
VOH
Logical High Level
ISOURCE = -0.5 mA
VOL
Logical Low Level
ISINK = 1.6 mA
MOS Load
IGG
Power S'upply Current
2.4
VSS
0.4
V
VSS-12.5
VSS-9
V
TA = 25°C, VGG = -12V,
36
V
mA
¢PW = 235 ns, VSS = 5V.
Input Clock Frequency =
2.04545 MHz
ac electrical characteristics
T A within operating temperature range VSS
= 5V ±5%, V GG = -12V ±5%, unless otherwise stated.
PARAMETER
¢PW
-Input Clock Pulse Width
CONDITIONS
MIN
MAX
UNITS
=
190
280
ns
300
570
ns
500
800
ns
Input Clock Frequency
2.04545 MHz, ¢t r , ¢tf = 20 ns
Input Clock Frequency = 1.26 MHz,
¢t r = ¢tf = 20 ns
Horizontal Reset Pulse Width
Within 400 ns after the Falling Edge
of Master Clock, (Figure 5)
Rise and Fall Time= 20 ns
tpd
Output Propagation Delay
VOH
Logical High Level
Capacitance at the Output = 15 pF
750
ns
VOL
Logical Low Level
(Figure 5)
750
ns
Note 1: Capacitance is guaranteed by periodic testing.
4-13
II
....
N
M
Ln
~
~
functional description
EXTERNAL CONTROL LEVELS
eously by connecting the Vertical and Horizontal Reset
pins together and driving them with the same reset
signal. Actual resetting of the vertical divider is to
either of two states, depending upon the state of the
Vertical Reset Control input; to zero, or to the fifth
vertical serration pulse (eleven 0.5H time intervals from
leading edge of Vertical Blanking). Refer to the reset
table. The horizontal' divider will always be reset to a
position which is 8 input clock pulses from the leading
edge of the. serration gate in the horizontal timing
scheme (Figures 2 and 3). The generator is reset to the
odd field (field one). The Field Index output pulse
occurs once each odd field at the leading edge ot Vertical
Blanking. It can be used to reset, or "gen·lock," similar
sync generator chips by connecting it to their Vertical
and Horizontal Reset inputs. The Horizontal Reset
Control selects Horizontal Reset to the start or center
of a line.
Horizontal Reset occurs for Logic "0." This resets the
horizontal counter to a state shown in Figures 2 and 3.
Vertical Reset occurs for Logic "0." This resets the
vertical counter to a state determined by reset control
input as shown below:
VERTICAL RESET
PERMITS THE VERTICAL
CONTROL INPUT
COUNTER TO RESET TO THE:
VIH. (VSS)
Oth count
VIL. (VGG)
11th count
HORIZONTAL RESET
RESETS THE HORIZONTAL
CONTROL INPUT
DIVIDER TO:
VIH
Beginning of line
VIL
Center of line
OUTPUTS
Logic "0" = VIL
The generator supplies the following standard output
functions: Horizontal Drive Out, Vertical Drive Out,
Composite Blanking Out, Composite Sync Out and the
Color Burst Gate.
Logic "1' = VIH
Divide select input = VIL, (VGG) for master clock
frequency of 1.26 MHz.
Divide select input = VIH, (VSS) for master clock
frequency of 2.04545 MHz.
In addition, Field Index and Color Burst Sync outputs
are provided. The Field Index identifies the odd field,
or field one, by occurring for two clock periods at the
leading edge of Vertical Blanking in that field. Thus, its
rate is 30 Hz. As described above, it can also be used to
"gen-Iock" other sync generator chips.
INPUTS
The user may select either of two input clock frequencies
by properly programming the Divider Control pin. In
one case the input frequency is 2.04545 MHz, which is
14.31818 MHz divided by seven. The other is eighty
times the horiz'ontal frequency, or 1.26 MHz. The
divider control will be programmed by connecting it to
VIH (VSS) and VIL. (VGG) respectively.
The Color Burst Sync output signal occurs at half the
horizontal rate with the same timing as the Color Burst
Gate output. It may be used to sync the color burst as
it will have the same delay characteristics as the other
outputs (including, of course, the Color Burst Gate) the color burst sync is present during the vertical interval.
There are separate Vertical and Horizontal Reset inputs
which allow directly resetting the appropriate divider(s)
by a control pulse generated by external means. Both
horizontal and vertical dividers may be reset simultan-
Differ~nces in phasing between outputs are minimized
by the use of identical push-pull output buffers clocked
by the internal clock.
typical performance characteristics
Typical IGG its Power Supply
Voltage (VSS - VGG)
Typical IGG vs Temperature
34
32
~ CLOCK FREQUENCY = 2,04545 MHz
30
~
~
28
TA=25°C
¢PW = 235 ns
Vss = 5V
VGG = 12V
28
CLOCK FREQUENCY = 2,04545 MHz
-TA=25°C
/
-pw=235 ns
J
-VSS=5V
I
r-VGG = -12V
/
I
26
I
24
/
J
I
22
20
V
1/
I
I
/
I
I
I
I
20
18
-50
-25
25
50
75
100
16
16.15
17
VSS - VGG (V)
AMBIENT TEMPERATURE (OC)
4-14
I
17.85
18
switching time waveforms
HORIZOo~~e~::
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
-r-11Ir-T"I"""T'"I""""I"'-1r-T"II"""T'"I""""I"'-1rO.0629H
4
LL-........::,==~I=-:--~--l
SERRATISGATE
f--
FRONT PORCH' l TA' O.02l1H
------+I--~....;5TA'.O.OlB6HEQUALIZATION
GATE
t
10TA~O.0774
._.
j
HORIZONTAL SYNC
HORIZONTAL DRIVE
22 TA ~ O.1694H
HORIZONTAL BLANKING
- - 5 TA ~ O.OlB6H
COLOR
BURST GATE
FIGURE 2. Horizontal Timing Master Clock
4-15
= 2.04545 MHz
SER·
RATION
EQUAlI·
ZATION
~vTrrn~"""T'"-r-~r--
or-
N
~
switching time waveforms
~
~
(Continued)
o
-i
"I rTB~
1
1.Z60MH,=
H
iii = 0.794",
COLOR BURST GATE
- lTB ~ 0.0375H
FIGURE 3. Horizontal Timing Master Clock = 1.26 MHz
1
r31.5kH,
=O,~3175sec
ZH PERIOD
18lf
~~____________________~VE~R~TI~CA~L~BL~A~NK~IN~G__________________~,~
ZlH
t--:--- ---:=F
3H
+==:-3H---j-
3H
EQUALIlATION GATE
SERRATION GATE
3H
'VERTICAL DRIVE & HORIZONTAL SYNC INHIBIT
9H
MASTER CLOCK PERIOD
(ONCE EACH 000 FIELD)
FIELD INDEX
FIGURE 4. Vertical Timing
Display
VSS
MASTER CLOCK
OV--f",,",",",",",,1
Vss--II----""""'\ ~--.---OUTPUT
IVSS-9V)---+---.....I~:::....:.;.;..----
VSS
RESET PULSE
FIGURE 5.
FIGURE 6. Horizontal Reset Characteristics
typical application
IV VSS
HORIZ
RESET
16
15
14
RESET
13
I
COMPOSITE
SYNC iNPUT
MMI321
12
11
HORIZ
RESET
CONT
OIVIDE
SELECT
TTL
L -
TTL Interface
}GNO.J
TV Circuits
MM5322 color bar generator chip
general description
features
The MM5322 Color Bar Generator Chip is a complete
dot-bar and color hue generation system in a single
monolithic P-channel MOS integrated circuit_ The chip
divides an internal oscillator (crystal controlled) frequency to provide the various timing, synchronization,
and video information required in the alignment of color
television receivers. A composite video output is provided for complete black and white dot-bar operation.
It consists of all synchronization, blanking, and video
information requi red for a fairly standard set of dot,
bar, an_d cross hatch screen patterns. In ,addition a
separate output for precise gating of 3.56 MHz color
bursts is provided. For servicing ease an oscilloscope
trigger is provided on either the horizontal blanking or
vertical synchronization time slots.
typical application
SW7
~
1+>
• Oscilloscope trigger
• Composite video output signal
• Crystal controlled oscillator
• Multi pie screen patterns
• Variable dot size
applications
• Battery or bench powered test instruments
• Manufacturing test sets
• Built in test capability
Typical Color Bar Generator Circuit
"POWER" INDICATOR
\ I/
~I
LEO
OSCILLOSCOPE
TRIGGER '
OUTPUT
INOTE 4)
Ov+
=NSL5D23
9V BATTERIES
~
• Battery operation
. +
SWl
INOTE 1)
. - - -.....-----_.-~ 0 - -
"*5 F
P
v·
62pF
f)""7----ts-----1r;--r-;-2
13il-----+-.......I
22M
I::J
~
378 kHz
10pF
NPO
INOTE 3)
470
1.5k
COLOR
LEVEL
>---Jl,fl/'v----~t-....- t 19
BCD 1
BCD 2
BCD 4
BCD 8
15
....L18
FASTSETF....LSLOW SET
11
MM5318
....LHOLD
16
14
6.8k
15
VIDEO
OUTPUT
·DX
26
21
28
DY
':"
JUUl ov
10
9
DZ
18
I-=___-----+---...--"",...,..~t-----<
HORIZ.
13
6.8k
112
':"
13
19
MM5840
"'''''''''~
VERT.
2k
--.f---,
16 \ - - - - - - -....
11
1--_4....~~........
HO AIZONTAL
POSITION
ADJ.
TIMEOUT MONOSTABLE
21 I---------+--.I--~
.-------~ ~------_426
NC
21
NC
2B
20
1----4I~.JV""'--.
VERTICAL
POSITION
ADJ.
+12V
NC
DIGIT SELECT +12V FOR 8 DIGIT
GND FOR 5 DI GIT
MODE CONTROL +12VciNODRFCOH:~~!~::~ OT~~~
>------------'
>-_________________--1
4-26
+12V
typical applications
(Continued)
TV Channel and Time Display Interfacing MM53100
12V
VDD
1
60 Hz
roll
20
ITO 2
!lUi 4
3
!lUi B
vDD
...I-
2
HOLO
3V
24
SET HRS
23
VSS
22
SETM1NS
Ox
DV
Dz
9V
MANUAL TV "ON"
...L
15
MANUAL TV "OFF"
D1SPLAVSELECT
...L
MM53100
16
12V
...L
ENABLE
....L
12V
STANDBV
50160 Hz
SELECT
TV"ON"
OUTPUT
21
10
PERIOO
SELECT X
NORMALL V
HARO WIREO
FOR EACH
APPLICATION
PERIOO
SELECT V
AUTO "ON"
OUTPUT
11
VIEW PERIOD
PULSE OUTPUT
12
13
Vss
9V
9V
TO TV VIOEO
OUTPUT CIRCUIT
6.Bk
15
VIDEO
OUTPUT
':"
JUUL
lB
JUl
12V
HORIZ.
':"
TO TV VIDEO GATING
CIRCUIT
ov
6.8k
12
':"
13
19
MM5840
VERT.
VERTICAL
RETRACE
'''''''"'')
CHANNEL
UNITS
{~
,""'n
{;
TENS
4
':"
22
23
24
16
25
17
26
21
27
20
HORIZONTAL
POSITION
AOJ.
VERTICAL
POSITION
AOJ.
2B
+12V
8
OIGIT SELECTG'~~ :~= :~:~:i
MODE CONTROL 12Vri~: FCOH:~~!~::LOOT~~~
>-____~
>-________---.1
Note. For interfacing with MM53105, refer to MM53105 specifications.
4·27
TV Circuits
MMq841 TV. channel number and time readout 'circuit
genetal description
The MM5841 TV Channel Number and Time Readout
Circuit is a monolithic metal gate CMOS integrated
circuit, which generates a display of channel number
and time readou'ts on the television screen.
A 7 ·segment decoder is used to decode either channel
inputs or time which is stored temporarily in the channel
number buffers or 4 bit latches, respectively, depending
on the time slot of the display. Each digit of time is
stored in a 4·bit latch while it is being decoded and
displayed, and the next digit enters the latch whi Ie the
horizontal sweep is between digits.
This chip includes all the logic required to prov.ide two
modes of operation, namely channel number, or channel
number and time displays.
.
A time slot decoder is employed to decode the appro·
priate time slot and the digit to be displayed. It
generates a video output signal that modulates the sweep
of the television tube for the display on the screen.
In addition, it can have a five (hour tens, hour units,
colon, minute. tens, and minute units) or eight· digit
(hour tens, hour units, colon, minute tens, minute units,
colon, second tens, and second units) display, depending
on the digit select input logic level.
features
This chip serves as a-' display, generator between
BCD channel inputs, the clock chip (MM5318) and
television set. The position of the display on the
screen can be controlled by adjusting the external
time constants.
the
the
TV
RC
•
•
•
•
•
functional description
The channel number and time readout circuit operates
with a 4 MHz input clock. Counters are incorporated in
the chip, operated by the input clock to keep track of
the time slots of the display.
12 or 24 hour operation (controlled by clock chip)
5 or 8 digit display
Channel number leading zero blanking
Single power supply
Channel number only or channel number and time
display
functions
• 8 digit mode is selected by a logic "1" at digit select
input
• Channel number and time mode is selected by a
logic "1" at mode input
The' position of the display is controlled by adjusting the
external RC time constants of the horizontal and
vertical monostable multivibrators.
connection diagram
Dual·1 n·Line Package
CHANNEL TENS
CHANNEL UNITS
~
(4)
(2)
(1)
(8)
(4)
(2)
(1)
Rv
Cv . VERT HORIZ CH
TOP VIEW
Order Number MM5841N
See Package 23
4·28
RH
VIDEO
OUT
absolute maximum ratings
Supply Voltage (V oo - Vss )
Voltage at Any Pin
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
-0.3V to +15V
Vss - 0.3V to Voo + 0.3V
O°C to +70°C
-55°C to +150°C
300°C
electrical characteristics
Voo
= 12V,
Vss
= OV,
unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply Voltage
Voo
11
Vss = 0
12
14
800
Power Supply Current
Input Voltage Levels
Time, Oscillator, Digit Select,
and Mode Inputs
Logical Low
Logical High
V
/lA
V ss --o·3
Voo-0.5
Vss
Voo
Vss+0.9
Voo+0.3
V
V
Channel Inputs
Logical Low
Logical High
V ss --o·3
V oo -0 .. 5
V oo:-5
V oo -4.5
Voo
Voo+0.3
V
V
Horizontal and Vertical Inputs
Logical Low
Logical High
V ss --o·3
V oD --o·5
V oo -5
V oo -4.5
Voo
Voo+0.3
Input Frequency
Oscillator
Horizontal
Vertical
1
Pulse Width = 14/ls
Pulse Width = 1 ms
Output Voltage Levels
Oscillator Inhibit, Digit Address
and Video Outputs
Logical Low
Logical High
Vss-0.3
Voo-0.5
One·Shot .Output Pulse Duration
Horizontal
Vertical
Output Drive
Video Output
Logical Low
Logical High
Oscillator Inhibit Output
Logical Low
Logical High
4
15.75,
60
Vss
Voo
15
1.5
4.5
V
V
MHz
kHz
Hz
Vss+0.9
Voo+0.3
V
V
50
13
ms
/lS
Vss + 1.0V
Voo - 1.0V
1-11
1
mA
mA
Output Forced Up to Voo - 4.5V
Voo - 1.0V
f-21
0.2
mA
mA
External RC
0.1
0.001
50
100
CVERTICAL
CHORIZONTAL
RVERTICAL
RHORI'ZONTAL
Propagation Delay
Oscillator Inhibit Output
/IF
/IF
kD pot
kD pot
2
clock
pulses
Input Leakage
1
/lA
Input Capacitance
5
pF
From Input Clock to Oscillator
Inhibit Output
4-29
block diagram
HORIZONTAL
PULSE
VERTICAL
PULSE
CHANNEl
TIME
4MHz
CLOCK
DIGIT ADDRESS
OUTPUTS
MODE
OSC INHIBIT
OUT
VIDEO OUT
timing diagram
~----------16.7mS------------j1
1--1
VERTCAL-----'
RETRACE
1..----------------------...... ~ r -
U
U
VERTICAl-----'
j"=ADJUSTABLE
TIMEOUT
~
----'u
U
HORIZ. RETRACE
i_I
If-~---~---63.5~S----------i1
r----------~!~l---~
:+_....1 ADJUSTABLE
HORIZ. TIME
OUT
1.-_ _
I
OSC INHIBIT_ _ _ _ _ _.......\ - - - ""15~s--- ....._ _ _ _ _ _ __
CLOCK
4MHz _ _ _ _ _ _ _ _ _ _ _ _
nnn
~IUUI~
_____nn _____________________
IUI~
nnn
VIDEO
OUTPUT '_____________________________.....l
1..-_______________________
CHARACTER
DISPLAYED
typical app lications
------e-----~e-------~------~~--~14-V+
J+
. {I
INPUT
CONFIGURATION
FOR CHANNEl
INPUTS AND
CONTROL INPUTS
OUTPUT
. } CONFIGURATION
FOR OSC INHIBIT,
VIDEO OUTPUT,
DIGIT SELECT'
RETRACE~
INPUT
RETRACE
INPUT
V2
I
I
Horizontal and Vertical One-Shot Circuit
4-30
typical applications (con't)
0.01
lOOk
'12V
-P
112~~:S; >--""'{\r----t~...-t 19
15
BCD
.4
3
2
17 MM5318
26
16
27
28
14
1
6.8k
BCi'i2
15
BCi'i4
BCO 8
OX
OY
VIOEO
OUTPUT
..1lfUl ov
10
OZ
18
-=
I-:-:-:=--+-...
.....Jw'v-.....---< +12V
HORIZ.
13
6.Bk
12
13
-=
19
MM5841
VERT.
VERTICAL
RETRACE
"'' ' '"' l
CHANNEL
UNITS
[
-=
22
23
16
24
25
17
26
,"",n
[ ;
TENS
27
4
28
21
20
HORIZONTAL
POSITION
AOJ.
VERTICAL
POSITION
AOJ.
+12V
If
DIGIT SELECT
+ri~~ ~~: ~ ~:~:~
MODE CONTROL +12V:NOORFCOH:~~!~:~LO OT~~~
>-____--1
>-_________....
TV Channel and Time Display
4·31
a
TV Circuits
MM53100, MM53105 programmable TV 'timers
general description
features
The MM53100 and MM53105 programmdble TV timers
are monolithic CMOS integrated circuits utilizing P and
N-channel low threshold enhancement devices. These
circuits contain all the logic to give a 4 or 6-digit, 24hour display from a 50 or 60 Hz input, and control the
"ON" time of the TV. The duration of the viewing
period is 5, 10, 20 or 30 mins, selected by 2 input
pins_ Manual "ON" and "OF F" inputs are also provided.
The MM53100 and MM53105 have ultra-low power
dissipation in the stand-by mode and are ideally suited
to crystal controlled battery-operated systems. The
MM53100 is designed for an optimum interface in
TVs with a positive common reference voltage (e.g.,
+18V). The MM53105 is designed for an optimum
interface for TVs with a OV reference voltage. Both are
packaged in a 24-lead dual-in-line epoxy package.
•
•
•
•
•
•
•
•
•
•
•
50 or 60 Hz operation
24-hour display format
,Programmable TV on time
Selectable view time
Ultra-low power dissipation
All countersresettable
Low voltage operation
Elimination of illegal time display at turn-on
Daily repeat or non-repeating operating
Fool-proof safety features
Compatible with MM5840 or MM5841 display circuits
applications
• TV time display
• Remote TV "ON"/"OFF" switch
• Computer clock
• Time data-logging systems
block diagram
50/60 Hz
SELECT
HaLO
SET
SET
MINUTES
HOURS
Oz
D~~i~~~ ------------.. . .
ENABLE
---+
---+
STANOBY ---+
MAN "ON"
MAN "OFF"
CONTROL LOGIC ~--~---... TV "ON" alP
AND
alP BUFFERS
AUTP "ON" alP
MUL TlPLEXED
BCD DIPS
F=IGURE 1. MM53100, MM53105 Block Diagram
4-32
VIEW PERIOD alP
absolute maximum ratings
(MM53100) (VDD common voltage reference)
Supply Voltage (VDD - Vss)
Voltage at 50/60 Hz Select and Period
Select Inputs
Current Into or Out of Any Other Input
6V
VSS - 0.3V to VDD + 0.3V
electrical characteristics
s:
s:
CJ1
W
~
0
0
100 /1A max
(MM53100) T A
PARAMETER
= 25°C,
VDD
= 4.5V,
VSS
= OV
MIN
CONDITIONS
TVP
2.8
Supply Voltage
Supply Current
s:
s:
CJ1
unless otherwise specified.
10
VDD = 4.5V
MAX.
UNITS
5.0
V
25
/1A
W
~
0
CJ1
Input Logic Levels
50/60 Hz Input, Digit Select
Inputs, Display Select, "ON",
"OFF", Time Setting Control,
Standby Control
Logic "1"
Logic
VDD-0.5
"a"
VDD
V
VSS+0.5
V
VDD-0.5
VDD
V
VSS
VSS+0.5
V
0.5
2.0
/1S
(Note 1)
50/60 Hz Select, Period Select
(X, V)
Logic "1"
Logic
"a"
Display Select Input Delay
Output Logic Levels
External Resistor, 15 kU to
BCD Outputs
VDD - 12V, CL = 15 pF
Logic "1"
Logic
V
VDD-0.8
"a"
VDD-11.2
V
Note 1: If input voltages go more negative than V 55, the input current must be limited to a maximum of 100 pA by the use of external series
resistors. No resistors are required on the OX, Oy, Oz inputs when interfacing with the MM5840.
absolute maximum ratings
(MM53105) (VSS common voltage reference)
Supply Voltage (VDD - VSS)
Voltage at 50/60 Hz Select and Period Select Inputs
Voltage at Any Other Pin
electrical characteristics
PARAMETER
6V
VSS + 6V
VSS + 13V
(MM53105) TA
= 25°C,
VDD
CONDITIONS
Supply Voltage
Supply Current
= 4.5V,
VSS
= OV
unless otherwise specified.
MIN
TVP
5.0
2.8
VDD = 4.5V
MAX
10
UNITS
V
25
/1A
Input Logic Levels
50/60 Hz Input, Digit Select
Inputs, "ON", "OFF", Display
Select, Time Setting Controls,
Standby Control
Logic "1"
VDD-0.5
13
V
Logic "0"
VSS
VSS+p·5
V
VDD-0.5
VDD
V
VSS
0.5
VSS+0.5
V
2.0
/1S
50/60 Hz Select, Period Select
(X, V)
Logic "1"
Logic
"a"
Display Select Input Delay
4-33
HI
electrical characteristics
(Continued) (MM53105) T A
PARAMETER
= 25°C,
CONDITIONS
VOO
= 4.5V,
MIN
VSS
= OV
TYP
unless otherwise
MAX
~pecified.
UNITS
Output Logic Levels
BCD Outputs
External Resistor 15 kQ to 12V,
CL = 15pF
Logic "1"
11.2
Logic "0"
V
V
0.8
TV "ON" Output, Auto
"ON" Output, View Period
Output
Logic "1"
Loaded 2.7 kQ to VSS
0.5
mA
Logic "0"
Loaded 2.7 kQ to VOO
1.0
mA
Note 1: Input voltages to go more positive than VOD.
functional description
A block diagram of the MM53100, MM53105 TV timers
is shown in Figure 1. A connection diagram is shown in
Figure 2. Unless otherwise indicated, the following
discussions are based on Figure 1. Figures 5a and 5b
illustrate the system configuration for a crystal controlled
TV display system using both circuits.
50 or 60 Hz Select Input: This input programs the
prescale counter to divide by either 50 or 60 to obtain a
1 pps time base. The counter is programmed for 60 Hz
operation by connecting this input to VOO. An internal
1 MQ pull-down resistor is common to this pin; simply
leaving this input unconnected programs the clock for
50 Hz operation.
Dual-In-Line Package, Top View
VDD
.....!.
U
24
-OX
BCD 8...1.
.31.. Dy
8CD 4.2-
.E. DZ
BCD2~
21
50/60 Hz SELECT
BCD 1.2.
20
50/60 Hz DRIVE
STANDBY
7
2!.. SET HRS
TV"ON"
8
OUTPUT -
22.. SET MINS
PE~:~~ -!
AUTO "ON"
'
2!.. HOLD
-2.
ENABLE -
Time Setting Inputs: Inputs to set hours and set minutes
as well as hold input, are provided. Internal 1 MQ
pull-down resistors provide the normal timekeeping
function. Switching any 1. of these inputs (1 at a time)
to "1" results in the desired time setting function. Set
Hours advances hours information at 1 hour/second and
Set Minutes advances minutes information at 1 minute/
second, without roll over into the hours counter. Set
Minutes also resets the seconds counter to O. The hold
input stops the clock to the minutes counter and resets
the seconds counter. Activating Set Minutes and Set
Hours simultaneously resets the displayed counters
to all a's.
Display: This input controls the display and timesetting operation. It has an internal 1 MQ pull-down
resistor'to VSS. When taken to Logic "a" or in open
circuit condition, the real time is displayed and the Set
Hours and Set Minutes inputs operate the real time
counters. When taken to logic "1 ", the "ON;' time is
displayed and the time-setting inputs operate on the
"ON" counters.
2!.. DISPLAY CONTROL
.!l.. MAN "OFF"
..!.!!.
PERIOD 11
SElECT X -
~
PERIOD 12
SELECT Y -
13
MAN "ON"
-VSS
FIGURE 2.
Order Number MM53100N or MM53105N
I
See Pa~kage 22
Digital Select Inputs (OX, Dy, OZ): These 3 inputs are
used to determine which digit will be displayed. Table IA
shows the code for each digit. Seconds will be displayed
as
when the "ON" time is being displayed.
50 or 60 Hz Orive: This input is applied to a Schmitt
trigger shaping circuit which allows use of a filtered
sinewave input. A simple RC filter should be used to
remove possible line voltage transients that could either
cause' the clock to gain time or damage the device. The
input should swing between VSS and VOO. The shaper
output drives a counter chain which performs the timekeeping function.
"qo"
Enable: This input has an internal resistor to VSS.
When taken to logic "1", this input disables the programmed "ON" time for the TV output.
Period Select Inputs (X, V): These inputs have pulldown resistors to VSS. They determine the view period,
i.e., 5, la, 20 or 30 mins. Table IB shows the Period
Select Code.
Alternatively, in a crystal controlled battery operated
system, an oscillator and prescaler such as the MM53107
could be used as a time base.
4-34
functional description
(Continued')
period, a signal on the manual "ON" input will prevent
the automatic switch-off.
Standby Control Input: This input has an internal
resistor to Vss. Its function is to sense when the line
generated 12V supply is turned off and to then disable
the outputs. In the TV, th is input should be connected
to the 12V supply.
Manual "OFF" input will always reset the output to a
logic "1" state.
Auto "ON" TV Output: An additional output is provided to indicate that the TV is "ON" in the automatic
mode of operation. This· output goes to a logic "0"
for the duration of the auto "ON" time. Manual "ON"
switches this output back to a logic "1".
Manual "ON" Input: This input has an internal resistor
to VSS. When taken to logic "1", this input turns the
TV output to the "0" state. It is designed to have
typically 0.75 second debounce time to prevent maloperation.
Manual "OFF"
to VSS. When
TV output to
typically 0.75
operation.
View Period Indicator: This output normally is a
logic "1". When the TV switches on at the programmed
time, this output transmits a 1 Hz waveform for the
duration of the selected view period. Hence, it can be
used to indicate that the TV is switched on for a limited
period only by means of a flashing on-screen and/or
off-screen display. The output will permanently return
to "1" at the end of the viewing period or when a valid
manual "ON" cij- "OFF" input signal is received during
the view period.
Input: This input has an internal resistor
taken to logic "1", this input turns the
the "1" state. It is designed to have
second debounce time to prevent mal-
TV "ON" Output: Figure 3
inverter output circuit used.
illustrates the CMOS
BCD Outputs: Figure 4 illustrates the open drain output
circuits used, a) MM53100, b) MM53105.
In the manual mode of operation, the manual "ON"
input sets this output to "0", the manual "OFF" input
resets this output to "1". The manual "ON" input
inhibits the auto "ON" output.
With the use of the external respective pull-Up and pulldown resistors, these outputs are designed to be compatible with the MM5840 and MM5841 TV display
circuits.
In the programmable mode, this output goes to "a"
when the programmed "ON" time coincides with the
real time (unless enable = 1). The output will then
stay at "a" for the selected period of 5, 10, 20 or 30
minutes before returning to "1" state. During this
Note. Case (a) for common VDD, case (b) for common
VSS when used with the MM5840.
TABLE IA. Digit Select Code
DIGIT DISPLAYED
DIGIT SELECT
LINES
Sl
S10
*
M1
M10
*
H1
Ox
Oy
1
0
0
1
1
0
0
H10
1
1
1
0
0
0
0
1
1
Oz
0
0
0
0
1
1
1
1
TABLE lB. Period Select Code
VIEW PERIOD
PROGRAMMED
PERIOD SELECT
INPUTS
X
0
0
1
1
VDD
VDD
Y
0
1
0
1
5 mins
10 mins
20 mins
30mins
---4..-----4..-
VPDS
DIP
DIP
DIP
+
Vss
FIGURE 3. CMOS Output (TV
"ON", Auto "ON", Indicator)
FIGURE 4a. BCD Outputs, MM53100
4-35
VSS
FIGURE 4b. BCD Outputs, MM53105
3:
3:
(J1
w
....
o
o
3:
3:
(J1
....w
o
(J1
functional description
(Continued)
50160 Hz
SElECT
lBV
lBV
o
o
~
...-"",..,...----TVVIOEOOIPCCT (lBV)
UELL
BATTERY
M
lBV.r
lSV
50160 Hz
MMS3l07
PRE·SCAlER
lBV
Il)
~
~
6V
HORIZ
t--t--+--"''''''-......--:--- lBV fROM TV
t - - -.....-'lM,-- HORIZ RETRACE
Ox
6V
Oy
MM~840
VERT
Oz
VERT RETRACE
OSC INH---.
6V
CLOCK
S6:s~~~~ - - - .
: ) eo,,,,,, '"'""
MOOE-.
TV "ON" DIP
A'UTO "ON" DiP
CHANNEl
liPS
FIGURE'5a. Typical System Diagram, MM53100
50160 Hz
SELECT
HEll
BATTERY
3V
l2V
l2V
3V
2 CELL . r
BATTERY
TV VIDEO alP CCT
50160 Hz
MMS3l07
PRE SCALER
BCDl
3V
HOLD
i-
stQ2
':'
HORIZ
l2V
SETM
HORIZ RETRACE
SET H
Ox
':'
Oy
MMSB40
MAN "ON"
VERT
DZ
VERT RETRACE
MAN "Off"
OSC INH---.
':'
DISPLAY SELECT
CLOCK
:=) "'' ' ' '"'""
s6:s~~~~ - - - .
ENABLE
MOOE-.
PERIOD SELECT
TV "ON" OIP
AUTO "ON" OIP
':'
VIEW
PERIO~
DIP
CHANNEL
I/PS
FIGURE 5b. Typical System Diagram, MM53105
4-36
TV Circuits
Note, SKll15 kit includes: MM57100N,
MM53104N and LM1889N
MM57100 TV game circuit,
general description
The MM57100 TV Game Chip provides all of the logic
necessary to generate backgrounds, paddles, ball and
digital scoring for three games: Hockey, Tennis and
Handball. All games are in color and have sound. The
MM57100 was designed for low system cost and is
aimed at the high volume consumer marketplace. It
generates all the necessary timing (sync, blanking and
burst) to interface to a standard TV receiver, and inter·
faces directly to the antenna terminals of a TV with
the addition of a chroma, audio and R F modulator.
If mounted directly into a receiver, much of this circuitry
can be eliminated. The chip requires the true and
complement clocks of 1.0227 MHz (3.579545 MHz 73.5). Figure 1 shows a block diagram of a complete
TV Game System.
paddle, it bounces off the object under the rule that the
angle of incidence is equal to the angle of reflection.
Regardless of the angle that the ball is traveling as it
hits the front of the player paddles, it will reflect as a
function of which segment it hits.
The score is automatically blanked when the ball is put
into play. It remains blanked until a miss is recorded
and it is then properly incremented and displayed. The
game is completed when one of the players reaches 15
points. At this time, the score remains on and the serve
is inhibited until the Game Reset is depressed. Both the
Game Reset and Game Select inputs are debounced for
16.5 ms.
The video output signal contains horizontal and vertical
blanking, horizontal and vertical sync and the black and
white information necessary to generate the picture
on a TV receive( through the antenna input. The picture
is not interlaced. Chroma outputs provide the color
and burst information and are properly timed with the
video.
The paddles for the games are controlled by two external
RC networks. Rand C provides for full screen movement
by developing a time delay of about 16.5 ms. For
Hockey and Tennis, each of the player paddles can be
made to be either large, medium or small in size, thus
allowing for handicapping. The size of a player paddle
is modified by moving the paddle to either the top or
bottom boundary and depressing the game reset button.
In Handball, the players can modify the paddles as
described above, but both players' must 'use the same
size paddle.
features
•
Three games: Hockey, Tennis and Handball
• All games in full color
• Ball speed doubles after fourth hit
• Segmented paddles for automatic ball spin
Single player "practice," can be created by connecting
the two player paddle input lines on the MM57100 to a
single external RC network .. Single player operation can
be achieved for all three games. Thus the MM57100
can actually play six games-three single player games
and three dual player games.
The player paddles are divided into nine different areas
that define eight angles at which the ball will reflect
upon incidence. The top-most area of the player paddle
will reflect the ball with the most upward direction,
the areas towards the bottom will reflect the- ball with
the most downward direction. And the very bottom of
the paddle will cause the ball to go up at a sharp angle,
simulating a "wood" or handle shot. The areas in between
will give reflections with less of an angle. There are two
areas in the center of the player paddle which will make
the ball have zero vertical velocity. The player paddles
are transparent in one direction so 'that in Hockey the
ball can rebound off the back wall and pass through the
defensive player paddle. The machine paddles in Hockey
are also transparent in one direction.
•
•
Adjustable paddle size/han9icapped play
Automatic digital scoring
•
•
•
Sound
Serve from paddles
Designed to interface with a minimum effort 'to a
standard television receiver
connection diagram
RIGHT PADDLE.....!.
LEFT PADDLE.2..
TEST..2.
VOD...!.
'-../
(DIP Top View)
.!!. GAME SELECT
~~:~iL~ES~~~/
~POWER
.!!..NC
AUDIO~
~NC
VIDEO...!.
r!2- NC
CHROMA A..!
.!2. NC
,.
,!.!!... NC
The ball is always served by the player who won the
last point. The serve comes about 1.6 seconds from the
time of the score and it is served from the paddle. This
allows for a more realistic situation: the server can
"place" his shot. After four player paddle hits, the ball
speeds up to twice the initial velocity. Each time the ball
strikes an object, a signal is generated at the audio
output for the duration of the frame and one more full
frame. When the ball strikes the boundaries or a machine
CHROMA B...!
VBIAS B.2.!!.
~NC
15
I-- ¢I
NC2!.
Vss .2L
Order Number MM571 OON
See Package 22
4·37
"ON"
r - - ' \ M -.....-""tRIGHT
500k
"']I033"F
':'
23 RESET
VIDEO
I!--------IJ-r---"--,
AUDIO ~-----,
o-_ _..:;.24:..fSELECT
MM57100N
VIDEO GAME
..--'lM.-......-..:.j lEFT
500k
-9V
FIGURE 1. Video Game System Diagram
GAME DESCRIPTION
Tennis
Since each player has four men who can return the
puck, the play is very fast. To make it even more difficult, a point can only be made when the puck slips
through either player's goal - a small opening located
directly in the middle of the side walls. Since only a
small portion of the left and right walls is used for
scoring, the puck can essentially rebound off all four
walls. Scoring is the same as in tennis - first player to
reach 15 is the winner. The score is yellow.
Tennis consists of a green court with a blue border,
a yellow net, orange paddles and a light green ball.
It is played by two players who, th'rough the use of their
individual controllers, can vertically raise or lower their
paddles. Play starts when the machine automatically
serves the ball cross court. This can be from either the
left or the right. The player who is served must hit the
ball back to his opponent, who must then return it.
Handball
As the volley begins, the speed of the ball increases once,
making it more difficult to return. The speed change
occurs on the fourth hit. When either player misses the
ball, a point is scored for his opponent and the next
serve comes to him after a wait of 1.6 seconds. To
increase the play value, the ball can bounce off both
the top and bottom walls. In addition, before the play
begins, each player can choose a large, medium or small
paddle, depending on his playing skill. The paddles
are sectioned, giving a "spin" effect tothe ball.
I
The score, which is yellow, is automatically displayed in
large, easy-to-read numerals_ The score appears when
the ball is missed and remains on until the ball is served.
Play ends when the first player reaches 15 points. At the
end of the game, the score remains on until the game
is reset.
Handball consists of a brown court, two paddles - one
blue and one orange, and a yellow ball. It plays identical
to tennis except only one player plays at a time and
both are on the same side of the court, playing against
the opposite wall. After the ball is served, the serving
player disappears from the screen and the other player's
paddle appears. He must hit it, or he loses the point and
the other player serves again. If he hits it, his paddle
disappears and the other paddle comes on the screen.
The other player must return it to the wall. The object
of the game is to keep the ball in play by continuously
hittil'")g it to the back court wall. The ball can be reflected
off three sides - the top, bottom and right wall. The
first player to score 15 is the winner. The score colors
match the paddle colors - one blue and one orange.
Hockey
SUMMARY
Hockey consists of a blue playing field which is surrounded by yellow walls, two yellow player-controlled
goalies, six light yellow machine-controlled forwards
and a light bl.ue hockey puck.
Table 1 describes how the game will appear on a standard
25" TV. The actual appearance will vary somewhat
from set to set as a function of color control settings,
fine tuning, overscan, etc. Table 2 and Figure 10 define
the Chroma Outputs and the approximate color they
generate.
Hockey, while similar to tennis, is a much faster and
more exciting game. Each player controls only his
goalie, who. moves in a vertical motion. In addition,
each player has three forward men who also move
vertically. These men are not under player control but
move up, and down, as a group, automatically. As in
tennis, the opening serve comes cross court and can
come to either player. Further serves are to the player
who has just lost a point.
SYSTEM CONFIGURATION
Figure 2 is a detailed schematic of how the MM57100
TV Game Chip would appear in a completed system,
including the MM53104 clock generator and the LM1889
channel modulator.
4-38
43 pF
3.579545 MHz
-15V 0
~--••~IDI~--4.~----~
••
NC
2.2k
r
O01
.
I
5.1k
16
-NC
~RIGHT
To.o33
---L-o
PADDLE
CLKt*
CLK 13
MM57100N
VIDEO
GAME
231GAME
RESET
';'
TEST
CHROMAB~8
3k
-15VO-VV\'.,..-4......
VBIAS B 10
v~::':E
241 GAME
",~PADDLE
T
o.033
VGG
114
•
0.01
Q
R·Y
B·Y
0
VIDEOt----------
LEFT
LM1889N
MODULATOR
-15V
171
----------f
~."
';'
CHROMA A
O~-----t SELECT
6.8M
MM53104N
CLDCK DRIVER
BIAS
'-""H -
151 AUDIO IN
~100
VDD
Vss
PON
22
112
2k
1.0
43 pFI
H1V~?E_O IN
.J:o>
tv
to
11
...
• • • • • • • •
I I
I
';'
.....
I.
--0.01
75
0-15V
0-9V
-=
I
I
~IIE}~~·
-~';'
o!J~ . II C~N p~T
SL00216
15VOLT
REGULATOR
';'
T
VESTIGIA!.
SIDEBAND
FILTER*
';'
I
~
*Model CTI55B Surface Acoustic Wave Output Modulation Filter.
(Crystal Technology Inc., 2510 Old Middlefield Way, Mountain View, Calif. 94043).
I
-
FIGURE 2. Schematic Diagram
m
DPDTTHROW
SLIDE
LONG
SWITCH
}
""
_
No".. All capacitors. inn JlF_
,
All resistors
In
•
'CENTRALAB Model 2 ULTRALIFE
potentiometer or equivalent.
00 LL 911\111\1
dc electrical characteristics
0°C:STA:S75°C
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Supply Voltages
VSS - V,OO
14.25'::; VSS - VGG:S 15.75
8.5
9
9.5
V
VSS - VGG
8.5'::; VSS - VOO .::; 9.5
14.25
15
15.75
V
Operating Supply Current
100
VOO = VSS - !;l.5V
35
mA
'IGG
VGG = VSS -15.75V
15
mA
Osc. Input Levels, cpl,
cp2
(Figure 3)
VIH
Logical High Level
VIL
Logical Low Level
"
Chroma A Output Levels
CL = 50 pF, IOC = 0,
(Figure 4)
8.5'::; VSS - VOO .::; 9.5,
VSS-0.5
VSS
V
VGG
VGG+0.5
V
(Typical values are for
VSS - VOO = 9V). All voltages
specified with respect to VOO
VAl
Al = 0.465 x (VSS -. VOO)
3.95
ROAl
Output Impedance
900
VAO
AO = 0.298 x (VSS - VOO)
ROAO
Output Impedance
2.53
2.68
'790
1.82
ABURST = 0.238 x
VABURST
4.,18
1.93
4.42
V
2060
S1
2.83
V
2060
S1
2.04
V
2030
S1
(VSS - VOO)
ROABURST
VA3
Output Impedance
710.0
A3 = 0.134 x (VSS - VOO)
1.13
ROA3
Output Impedance
520.0
Chroma B. Output Levels
(Figure 4)
1.2
1.27
V
2100
S1
CL=50pF,IOC=O,
8.5:S VSS - VDO .::; 9.5. (Typical
. values are for VSS - VOO = 9V).
All voltages specified with respect
to VOO
VBl
Bl = 0.465 x (VSS - VOO)
3.95
ROBl
Output Impedance
900
VBO
BO = 0.298 x (VSS - VOO)
2.53
ROBO
Output Impedance
790
VB3
B3 = 0.134 x (VSS - VOO)
1.13
ROB3
Output Impedance
520
Chroma A Bias and Chroma B
Bias Output Levels
4.18
2.68
1.2
4.42
V
2060
S1
2.83
V
2060
S1
1.27
V
2100,
S1
CL = 50 pF, IOC = 0,
8.5'::; VSS - VOO'::; 9.5. (Typical
values are for VSS - VOO = 9V).
All voltages specified with respect
to VOO
VBIASA, VBIASB = 0.298 (VSS - VOO)
2.53
RO~IASA, ROBIASB
790
Chroma and Chroma Bias Output
Offset Voltages
2.68
2.83
V
2060
'S1
CL =50 pF, !IOCI'::; 50pA,
IICHROMA - IBIASI~ 5pA,
IICHROMAA - ICHROMABI.::; 5J1A
10
VOS
4AO
50
mV
s:
s:U1
......
~
PARAMETER
Video Output Levels (Figure 5)
MIN
CONOITIONS
CL
8.5
= 50 pF,
= Vss -
IDC
TVP
MAX
UNITS
= 0,
VDD S; 9.5. All voltages
specified with respect to VDD.(Typical
values are for VSS - VDD
= 9V)
VSVNC
VSVNC
= 0.444 x
3.77
ROSYNC
(VSS - VDD)
Output Resistance
906
VSLANK
VSLANK
(VSS -
ROSLANK
VOARK
= 0.333 x
VDD) = 0.75 x
VSVNC
Output Resistance
RODARK
VSVNC
Output. Resistance
VLlGHT
VLlGHT
(VSS -
2.06
V
2080
n
3
3.18
V
2080
n
2.30
V
2030
n
1.41
V
2040
n
2.18
726
= 0.148 x
VDO) = 0.383 x
1.26
VSVNC
Output Resistance
Audio Output Level (Figure 6)
4.22
835
= 0.242 x
VDD) = 0.545 x
VOARK
(VSS -
ROLlGHT
2.83
4
1.33
556
RLOAD = lOOk, CLOAO
= 20 pF
V
VDO
VOUT
Output Resistance to VDO
RO"ON"
"ON" Resistance
VOL S; VDD +0.5
RO"OFF"
"OF F" Resistance
VOH
1.0
2 VDD + 3.0
50
COUT
5
kn
500
kn.
5
pF
Reset, Test and Game Select
Input Levels
VIH
Logical High Level
VSS-l.5
VIL
Logical Low Level
VDD
Paddle 1 and Paddle 2
V
VSS
VDD+2.5
V
VDD+O.4
V
VSS
V
VDD+0.5
V
VSS
V
8.5 S; VSS - VDD S; 9.5
Input Levels (Figure 7)
Vpl
VOH
Input Trip Level
VOD-O.4
Logical High Output Reset
RLOAD = 15 kn to VGG,
Level
CLOAD
= O.lpF,
R LOAD
= 180k, 10%,
= lpF, 10%
VDO
VSS-2.5
10%
Power "ON" Clear Input
Levels (Figure 8) See Note 6
VCLR
Input Trip Level
CLOAD
VOH
Logical High Output
VDD -0.5
VSS-2.5
VDO
Reset Level
en
Noise Levels on Chroma A,
8.5 S; VSS,- VDD S;9.5,
Chroma B, and Video Outputs
14.25 S; VSS - VGG S; 15.75,
CLOAD
= 50 pF,
-200
200
mV
IllS; 50pA
Note 1: Chroma A, Chroma B and the Chroma bias output leve!s are specified for dc current = O. Typical dc loading conditions are 30~A or less.
The resistor network in Figure 9(a) can be used to determine the shift and interaction in outputs for dc load conditions.
Note 2: Video output levels are specified for dc current = O. Any other loading conditions will influence the output levels and the resistor network
in Figure 9(b) can be used to calculate output levels. Typical dc currents are 30~A or less.
Note 3: All diffused resistors have a ±30% tolerance, and tracking of tolerance can be assumed.
Note 4: All MOS switch impedances include all variations, i.e., due to process, and supply variations, tracking of MOS switch impedances can
be assumed.
Note 5: Tracking of diffused resistor tolerances and MOS device tolerances cannot be assumed.
Note 6: Power On Clear input pin is reset by the MM57100 to the VOH level near the end of the internal Power On Clear cycle. as shown in Figure 8.
4-41
o
o
ac electrical characteristics
(Doc to +70°C, except where otherwise noted)
PARAMETER
CONDITIONS
MIN
Osc Inputs, rp1 and rp2 Input
TYP
MAX
1.0227
UNITS
MHz
Frequency (Figure 3)
Rise and Fall Times
t r , tf
40
tdL 1
trp
10
0.9778
ns
ns
J.1s
tpwl
00405
tpw2
0.380
VOLl
VSS-1.0
VSS-0.5
VSS
V
VOL2
VSS-2.0
VSS-l.0
VSS
V
Chroma A and Chroma B Output
J.1s
J.1s
CL = 50 pF, IOC S; 50J.1A
Timing (Figure 4)
trA
tfA
175
225
ns
175
225
ns
trB
175
225
ns
tfB
175
225
ns
tSCB
450
trCB
tfCB
175
ns
175
ns
ns
tCLl
0
ns
tCL2
0
ns
tBURST
2900
ns
Video Output Timing (Figure 5)
CLOAO=50pF,IIOCIS;50J.1A
trv
tfv
250
500
ns
250
500
ns
trS
250
500
ns
tfS
250
500
ns
trL
150
225
ns
tfL
150
225
tbp
5
tSYNC
tfp
4.5
4.9
J.1s
1
1.25
J.1S
0.97
tVIDEO
tBLANK
10.5
Audio C.Jtput Timing
(Figure 6)
fa
Output Frequency
11
ns
J.1S
J.1S
11.9
J.1S
rpl, rp2 inputs = 1.0227 MHz,
CLOAO
= 20 pF
491
IIOC IS; 50J.1A
Hz
Audio Tone Duration
tON
18.55
tOFF
t ra , tfa
CLOAO = 20 pF,
30.25
ms
15
J.1s
10
J.1S
REXT = 120k to VSS
tha
1
ms
tpwa
2.037
ms
= O.lJ.1F + 10%,
Player Paddle Timing
CLOAO
(Figure 7)
RLOAO;? 15 kr2 (to VGG)
tpH
Paddle High (25H)
tpL
Paddle Low (215H)
1.58
tRP
Power "ON" Clear Timing
(Figure 8)
RC> 138 ms, R
= 180k,
ms
13.7
ms
l.2
ms
10%;
C = lJ1F, 10%
tdcl
60
tpOWER
ms
30
4-42
ms
I
s:
s:
(J1
....,
o
~
o
¢1
fq,1 ~ 1.022727 MHz !2B Hz
¢2
VIH-Vil
FIGURE 3. Input Clock Waveforms
HOCKEY BORDERS VIDEO
Al------;
ISCB
CHROMAA
AO-------~---------~,I
ABURST-----4--------~~·~-~
VDD
A3-----'
CHROMA A
If A
IrA
Bl------o
CHROMAB
BO-------~-------~----------------------~~~-------------~I~------
VDD
B3------'
CHROMA B
FIGURE 4. Video-Chroma Timing
4-43
TIME
I
LINE 262
*
SOTTOMOF
~
THROUGH
LINE 3
LINEI
H-I--H
H-I
YSYNc~PICTURE
I
YSLANKYBLACK
YWHITE -
=t
LINES 4 THROUGH LINE 6 - -
--1 ~H
. ~s II
45
THROUGH
L1r~E 20
LINE7
~45
=r
- - - L I N E 21
~
TOPOF
PICTURE
I ' ~s
H ~ 63.557J.ls
Note: Interlaced scan and
equalization pulses are not used.
FIGURE 5(a). Video Output Waveform
IrS
YSYNC --------------1fj-:::~~~
VBLANK - - - - - - - - - - ' - - - - = 9 = 0 % 7 , I"'"'f 10%
90%
10%
tYIDEO
VBLACK --------I~
VWHITE
90%
-------......1
90%
10%
IrL
tfL
FIGURE 5(b). Composite Video Timing and Levels
1--63.557~S
BOTTOM OF PICTURE
(FRAME n)
---1
BOTTOM OF PICTURE
(FRAME n + 1)
I
I
HIT\
YI6EO~_~n ---,:,\~n,--.--L~
.........
'l----------,ON
AUDIO
LINE 22
H
,
~ U U U U U U U U U
HIT CAN OCCUR FROM HORIZONTAL
LINES 48TO 232
f-----------lpW.-----------1
VOH-------------r--------------,
90%
10%
VOL-------------------JI
f-------
~IDFF
nnnnnnnnnr--
------------~~
Ih.---~_1
FIGURE 6. Audio Output Timing
4-44
PLAYER PADDLE
VIOEO
LINE 1
~~~~
I
VIDEO
VOH------~
PLAYER
PADDLE
INPUT
__- - - - + ____
90%
Vpl
:::::::::t
VIL----~ 10%
----'
START OF LINE 21
(TOP OF PICTURE)
BOTTOM OF
PICTURE
VGG
Vss -------+-_+_
h:1:
VOH------PLAYER
PADDLE
INPUT
SOOk
10%
0.22"F
S
%
--------t'-
TIMING CIRCUIT
VGG
i-----tPL-----j
PLAYER PADDLE INPUT TIMING
FIGURE 7. Player Paddle Inputs
.
V-
~L
VDD.VGG
tpOWER
_ _ _ _ _ _ _ _ _ __
VDMAX
':<.-1'1-1-
"t-d'f- - - . - - - VOH
I . -_
tdel
POWER "ON"
, CLEAR INPUT
.
Velr .
~.
.
(b) Slow Power Supply Edges
(a) Fast Power Supply Edges
FIGURE 8. Power "ON" Clear Input Timing
CHROMA B
BIAS OUTPUT
VSS
CHROMA A
BIAS OUTPUT
SYNC
2.Sk
J..
VIDEO
OUTPUT
O.Sk
CHROMA A
OUTPUT
CHROMA B
OUTPUT
13Sn-7BOn
0.41k
0.4Jk
16011-1JOOll
0.6k
0.67k
VDD
VDD
(a)
(b)
FIGURE 9. Chroma and Video Output Networks (See Notes on Page 4-41)
4-45
TABLE I. Game Colors and Size on a 25" TV
"-
CHROMA
OUTPUT
ELEMENT
VIDEO
OUTPUT
APPR.
COLOR
APPR. SIZE
COMMENTS
Tennis Background
A1BO
Light
Blue
Tennis Field
AOB3
Dark
Cyan
13.2 x 16.8 inches 2
Tennis Ball
AOB3
Light
Cyan
Tennis Score
A3BO
Light
Yellow
0.5 x 0.5 inches 2
4 x 5 inches 2
Tennis Net
A3BO
Light
Yellow
0.5 x 13.2 inches 2
Tennis Left Player
A3Bl
Light
Orange
3 sizes
2.4, 1.2 or 0.6 inches x 0.5 inches
independent of other paddle
Tennis Right Player
A3Bl
Light
Orange
3 sizes
2.4,1.2 or 0.6 inches x 0.5 inches
independent of other paddle
Handball Background
A3BO
Light
Yellow
Handball Field
A3BO
Dark
Yellow
Handball Ball
A3BO
Light
Yellow
Blanked during play
13.2 x 16.8 inches 2
Handball Left Score
A3Bl
Light
Orange
0.5 x 0.5 inches 2
4 x 5 inches 2
Handball Right Score
A1BO
Light
Blue
4 x 5 inches 2
Blanked during play
Handball Left Player
A3Bl
Light
Orange
3 sizes
2.4, 1.2 or 0.6 x 0.5 inches,
same as other paddle
Handball Right Player
A1BO
Light
Blue
3 sizes
2.4, 1.2 or 0.6 x 0.5 inches,
same as other paddle
Hockey Background
A1BO
Dark
Blue
Hockey Field
A1BO
Dark
Blue
Hockey Border
A3BO
Light
Yellow
Blanked during play
13.2 x 16.8 inches 2
Hockey Puck
A1BO'
Light
Blue
0.5 x 0.5 inches 2
Hockey Score
A3BO
Light
Yellow
4 x 5 inches 2
Blanked during play
Hockey Left Player
A3BO
Light
Yellow
3 sizes
2.4, 1.2 or 0.6 x 0.5 inches
independent of other paddle
Hockey Right Player
A3BO
Light
Yellow
3 sizes
2.4, 1.2 or 0.6 x 0.5' inches
independent of other paddle
Hockey Machine Forwards
A3BO
Light
Yellow
0.5 x 0.6 incties 2
Hockey Goals
A1BO
Ught
Blue
4.6 x 0.5 inches 2
TABLE II. Chroma Outputs vs Approximate Color
+B
•
A3Bl
-ORANGE
-A--__. -________
AOBl
-RED
A1Bl
-MAGENTA
~--------~~--+A
A3BO
-YEllOW
A1BO
-BLUE
A = Blue - Y
B = Red - Y
Y = Video
AOB3
-CYAN
A3B3
-GREEN
Hole in the Border
A1B3
-BLUE/CYAN
-8
FIGURE 10. Chroma Outputs/Color Phase Diagram
4-46
CHROMA A AND
CHROMA B OUTPUTS
APPROXIMATE COLOR
AO,BO
AO,Bl
AO,B3
A1, BO
Al, B1
A1, B3
A3, BO
A3,Bl
A3,B3
ABURST, BO
Light Gray
Red
Cyan
Blue
Magenta
Blue Cyan
Yellow
Orange
Green
Color Burst
DESIGN CONSIDERATION
PADDLE INPUTS
FOR
THE
PLAYER
TIMING AND LEVEL DEFINITIONS
Rise and fall times of 1 and r/>2 clock inputs.
Delay from the VSS - 1V point of the r/>2
positive transition to the VSS - lV point
of the r/>1 negative transition.
Clock cycle time.
Time from 50% point on negative edge of r/>2
to the 50% point on the negative edge of r/>1.
Pulse width of the 2 input, at the 50%
point.
Crossover point where 1 = r/>2 and r/>1 is on
VOL1
a negative transition.
Crossover point where 1 = r/>2 and 1 is on
VOl2
a positive transition.
Rise and fall times of .the chroma A and
trA, trB,
chroma B outputs.
tfA, tfB
Delay from start of sync pulse trailing edge
tSCB
to the start of the chroma A output color
burst leading edge.
trCB, tfCB Rise and fall times of the chroma A output
color burst pulse.
Chroma A output color burst pulse width.
tBURST
Delay from the start of a chroma output
tCL1
negative transition to the start of the VIDEO
output (luminance) transition.
Delay from the start of a chroma output
tCl2
positive transition to the start of the VIDEO
output (luminance) transition.
Rise and fall times of the V IDEO output
blanking pulse.
Rise and fall times of the VIDEO output
SYNC pulse.
Rise and fall times of the VIDEO output
luminance pulses.
Duration of the VIDEO output front porch
and back porch.
Duration of the VIDEO output SYNC pulse.
tSYNC
Duration of the VIDEO output luminance
tVIDEO
pulses.
tBlANK Duration of the VIDEO output blanking
pulse.
Duration of the AUDIO output "HIT"
tON
tone burst.
Delay from the end of the AUDIO output
tOFF
"H IT" tone burst to the start of the VIDEO
output blanking pulse.
Rise and fall times of the AUDIO output.
Width of the AUD 10 output tone pulse
positive level.
AU D 10 output tone cycle time
(t = l/fAUDIO)
Rise time of the PLAYER PADDLE inpu~ .
. Delay time from the top of the picture to
the highest player paddle position.
Delay time from the top of the picture to
the low~st player paddle position.
.
Delay from point where the power supplies
are within the operating spec to the point
where the power·on clear input level is less
than VClRI.
tpOWER Fall time of the power supply at turn-on,
to 95% point.
One horizontal scan line.
H
Calculations are based on an input waveform at the
"PLAYER PADDLE" input:
VIN
= VIH + (l_e- t/RC ) (VGG -
VIH)
A solution for t = RC is done, at the input trip point
where VIN = VTRIP = VDD ±O.4V, and t = td.
RC =
-td
In [VGG - VDD ±O.4V]
VGG - VIH
Over the design range of VDD, VGG and VII.. , the
denominator has a range
,
.
-1.187 < In(x) < -0.5864 where x
-
VGG - VDD ±O.4V
= -----.
VGG - VIH
The time delays required vary from a minimum of
tdT = 1.58 ms for the player paddle positioned at the
top of the screen, to a delay of tdB = 13.7 ms for the
player paddle ,positioned at the bottom of the screen.
For these time delays, the ranges of RC are:
(RCITMIN ~ 1.33 ms::;
+]::; (RCITMAX
[
In VGG - VOO _O.4V
= 2.69
ms
VGG - VIH
for the upper- paddle position and
(RC)BMIN
=
11.54 ms; (RC)BMAX
= 23.36 ms
for the lower paddle position.
Thus, the external RC network must guarantee a minimum RC of 1.33 ms or less and a maximum RC of
23.36 ms or greater.
Calculations of potentiometer resistance based on a
linear pot use the formula:
RO
Ox Rp
= ---
±Rp' l
Ofs
where:
RO is the potentiometer tap resistance
() is the angle of pot rotation beyond 0
Ofs is the full scale rotation of the pot, ±
tolerance
Rp is the full scale resistance of the pot, ±
tolerance
l is the Iinearity of the pot
Using RC = td, values of 0 can be calculated for the
required extremes using the expression:
This expression assumes prior selection of Rp, l, 0fs,
and C. This expression can be modified to calculate
Rp or C if there is any restriction on the upper limit
of O.
Mechanical variations, either in the potentiometer or
the control housing which affect pot rotation should
also be considered.
4-47
3:
3:.
U1
.....
o
~
o
en
00
00
....
TV Circuits
...I
Note. SKll15 kit includes: MM571 DON,
MM53104N and LM1889N
~
LM1889 TV video modulator
general description
features
The LM1889 is designed to interface audio, color
difference, and luminance signals to the antenna terminals of a TV receiver. It consists of a sound subcarrier
oscillator, chroma subcarrier oscillator, quadrature
chroma modulators, and R.F. oscillators and modulators
for two low-VHF channels.
•
DC channel switching
•
12V to 18V supply operation
•
Excellent oscillator stability
~
Low intermodulation products
•
5 Vp-p chroma reference signal
•
May be used to encode composite video
The LM1889 allows video information from VTR's,
games, test equipment, or similar sources to be displayed
on black and white or color TV receivers. When used
with the MM57100 and MM53104, a complete TV game
is formed.
.
block diagram
Dual:ln·Line Package
CHROMA __
1~______~
LEAO
18 CHROMA
~--------~----+--lAG
CHROMA 1--__--11-1_7 CHROMA OSC
OUTPUT
OSC
16 CHROMA
SUPPl Y
CHROMA 3
BIAS
1--____1-1_5 SO UN D
TANK
14 RF
GROUND
SUPPl Y
13 VIDEO
~--~----------+--DCREF
CH B {
TANK
6
\
CH A
OUTPUT
CHA {
TANK
8
10 CH B
OUTPUT
Order Number LM1889N
See Package 20
4-48
tentative electrical characteristics
(Applications circuit, V
= 15V)
TYP
Supply Voltage Range V14, V16
Total Supply Current 114 + 116
Common·Mode Input Range
Chroma Mod. V2, V3, V4
RF Mod. V12, V13
Oscillator Levels
Sound Osc V 15
Chroma Osc V 17
RF Osc V6, V7 or V8, V9
Ch'roma Modulator Conversion Gain
V130ut1V4-V3
V13 OutIV2 - V3
Residual Chroma Output, V13
V2 = V3 = V4
RF Modulator Conversion Gain
V10 or V111V12·V13
12-18 VOC
35 mAOC
4-10.5 VOC
3.5-11 VOC
3.5 Vp·p
5 Vp-p
300 mVp-p
0.6 Vp-pIVOC
0.6 Vp-plVoC
50 mVp-p
10 mVrmslVoc
typical application
l.57955MHz 9-l5pF
4lpF
*
lk
R·Y
INPUT
0
-=-
lk
1
II
18
5.1k
, * 4 l PF
11
3.58 MHz
OUTPUT
Jk"
-=-
16
CHROMA
DC REF
~,O.Ol"F
TO.OleF
10"H
15
B·Y
INPUT
AUDIO
14
lM1BB9N
-=240
CH 4
13
VIDEO
DC REF
22pF
12
2k
11
75
10
75
LUMA+ SYNC
CHSW
'J
0 001
. "F
+
15 Vae
~l"F
RF OUTPUT
4-49
TV Circuits
Note. SK 1115 kit includes: MM57100N,
MM53104N and LM1889N
MM53104 1V game clock generator
general description
The MM53104 is a monolithic CMOS clock generator
designed to generate the 2-phase non·overlapping clocks,
¢1 and ¢2, for the MM57100 TV game chip.
All pins are protected against static damages by diode'
clamps to both VCC and ground.
The MM53104 contains two independent oscillator
circuits that can either be driven by an e,:,ternal input
or be used as a Colpitts-type oscillator (e.g., crystal
oscillator). The first oSCillator (Xl, X2) is designed to
operate at 3.58 MHz and the output (X2) is fed internally
to a divide-by-3 1/2 counter to generate the 1.0227 MHz
¢1 and ¢2 outP\1ts required by the MM57100. The
second oscillator (Y1, Y2) is a completely independent
oscillator and is designed for a 4.5 MHz operation.
features
•
Directly drives MM57100
• Two on·chip oscillator circuits
•
connection diagram
Low power consumption 250 mW typ
@
15V
timing diagram
Dual·1 n·Line Package
X2
VCC
Xl
GND
Xl
MM53104N
X2
92
¢1
¢1
¢2
-.J
I
1
I
1....-______
L,
TOP VIEW
Order Number MM53104N
See Package 17
logic diagrams
Vcc
Xl
f
Vcc
X2
1M
lOOk
731/2
COUNTER
NON·
OVERLAPPING
CIRCUITRY
¢l
Yl
92
':"
1
Y2
f
-
':"
':"
4·50
absolute maximum ratings
(Note 1)
Voltage at Any Pin
-o.3V to VCC +0.3V
-o.3V to 16V
15V ±5%
O°C to +70°C
-65°C to +150°C
500mW
300°C
VCC
Recommended VCC
Operating Temperature Range
Storage Temperature Range
Package Dissipation '
Lead Temperature (Soldering, 10 seconds)
dc electrical characteristics
14.25V ~
PARAMETER
vcc:::;
15.75V
CONDITIONS
= Y1 = VCC
= GND
Ouiescen't Current
Xl
Operating Current
Y1
VOH
Output High Level, ¢1 or ¢2
VCC=15V
VOL
Output Low Level, ¢1 or ¢2
VCC= 15V
IOH
O,utput Source Current, ¢1 or ¢2
VCC
IOL
Output Sink Current, ¢1 or ¢2
VCC = 15V, Vo
ICC
ac electrical characteristics
MIN
= 15V,
TYP
MAX
600
V
0.05
= 13,5V
-7.0
= 1.5V
/lA
mA
15
14.95
Vo
UNITS
V
mA
mA
11.0
VCC = 15V, CL = 15 pF, all limits apply across temperature.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
TR
Rise Time of ¢1 or 92
15
30
ns
TF
Fall Time of ¢1 or 92
15
30
ns
TPW,¢l+
Positive Pulse Width of ¢1
410
455
510
ns
TPW,¢l-
Negative PlIlse Width of ¢1
470
520
570
ns
TPW,¢2+
Positive Pulse Width of ¢2
510
570
600
ns
TPW,¢2-
Negative Pulse Width of ¢2
380
410
470
ns
Effective Negative Pulse Width
405
440
TW,¢2-
ns
of ¢2
TdL1
¢1 Overlapping ¢2 Time
-13
5
ns
TdL2
¢2 Overlapping ¢1 Time
-2
10
ns
VOLl
¢1 Cross·Over ¢2 Voltage
VCC-LO
VCC
V
VOL2
¢2 Cross·Over ¢1 Voltage
VCC-2.0
VCe- 0 .8
V
Note 1: ;, Absolute Maximum Ratings" are those values beyond which. the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
ac test circuit
=f}F
T2 - -
4-.A.!kA
.........
5V-OV
-
Tt
Tt--
= 145 ns
t
u
.L...o+t5V
~ U
INPUT FROM PULSE
GENERATOR'-""1
O.OtI1 F
I
MM53t04N
r--3
6
o-!
5
T2 = 135 n s _
t r =tf=20ns
~
CL = 15 pF including scope probe and all stray capacitunces.
Note: When the MM53104 is used with the MM57100
and LM1889, the 4.5 MHz oscillator in the MM53104
is not needed and thus pin 3 should be grounded.
"4·51
OPEN
-
~C~
TO SCOPE
-::c....._ _ _ _ _--1
T
C
-::cL
TO SCOPE
0
~
$2
('t)
switching time waveforms
an
:E
:E
PULSE
GENERATOR
1 V C C - - - - - I
¢z GND
~---. ~pPW .~2': ~.I"""F:--D-.5V--TPW.2-------l
I.
.'i'
Note: tr = tf = 20 ns
.
.
4·52
TW.¢2-
1------TPW.¢1+------~
TV Circuits
MM58106 digital clock and TV display circuit
general description
features
The MM58106 is a monolithic CMOS integrated circuit
which generate's a display of channei number and time
on the television screen. The circuit can ei.ther display
channel number (2-83) or program number (1-16).
Time display can be 4 or 6-digit. in either 12 or 24-hour
mode. Timekeeping is controlled from a 50 Hz or
60 Hz input. The position of the display on the TV
screen is controlled by adjusting the external RC time
constants.
•
Single chip clock and display
•
12 or 24·hour operation
•
5 or 8·digit time display
•
Channel or program number display
•
•
50/60 Hz operation
Charnel and time display on channel change
The circuit is packaged in a 28·lead dual·in-iine epoxy
package.
block diagram
HORIZONTAL
PULSE
connection diagram
VERTICAL
PULSE
EDGE
OETECT
CHANNELS
(8)
SET
SET
HR HOLO MIN
Dual·1 n·Line Package
28
RV
12124 HR
27
Cv
26
VDD
25
CTI
23
CUI
VSS
21 50/60 H.INPUT
20 50/60SELECT
10
19
11
18 SETMIN
CTS 12
11 12124 HR
CT4
SET HR
CT2 13
16 HOLO
CU8 '4
15 EDGE DETECT
TOPVIEW
FIGURE 2
Order Number MM58106N
See Package 23
4·53
HOR
CU4
CU2
FIGURE 1
4MH. CLOCK
22 CH
VIOEO OUT
VIDEO
OUT
DIGIT SEL
OSC INHIBIT
24 RH
CH/PROG SEL
OSCILLATOR
INHIBIT
VERT
absolute maximum ratings
Supply Voltage (VOO - VSS)
Voltage at Any Pin
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
electrical characteristics
5.5V
VSS - O.3V to +5.5V
o
O°C to +70 C
-55°C to +150°C
300°C
Voo = 5V, VSS = OV, unless otherwise specified
PARAMETER
Power Supply Voltage, VOO
CONOITIONS
VSS= 0
MIN
TYP
MAX
4.75
5
5.25
Power Supply Current
800
UNITS
V
pA
Input Voltage Levels
Channel Inputs
Logical Low
VSS-D·3
VOO-5
VOO-4.5
V
Logical High
VOO-D.3
VOO
YoO+0.3
V
Logical Low
VSS-D·3
VOO-5
VOD-4.5
V
Logical High
VOD-D·3
VDD
VDD+0.3
V
VSS-0.3
VSS
Open
VSS+0.3
V
Horizontal and Vertical Inputs
Set Mins, Set Hours, Hold, 12/24·Hour
Internal Pull-Up Resistor to
Select, 50/60 Hz Sele.ct, Channell
VDD (600k Min)
Program Select
Logical Low
Logical High
All Others
Logical Low
VSS-0.3
VSS
VSS+0.3
V
Logical High
VDD-D·3
VDD
VDD+0.3
V
Input Frequency
4 MHz Clock
1
4
Horizontal
Pulse Width = 14 ps
15.75
Vertical
Pulse Width = 1 rns
60
4.5
MHz
kHz
Hz
Output Voltage Levels
Oscillator Inhibit and Video Output
Logical Low
VSS-D_3
VSS
VSS+0.9
V
Logical High
VDD-o·5
VDD
VDD+0.3
V
One-Shot o"utput Pulse Duration
Horizontal
50
ps
Vertical
13
ms
Output Drive
Video Output
Logical Low
VSS + lV
Logical High
VDD-.1V
(-1)
mA
1
mA
(-2)
mA
Oscillator Inhibit Output
Logical Low
Output Forced Up to VDD-4.5V
Logical High
VDD -lV
0.2 .
rnA
External RC
pF
CVERTICAL
0.1
CHORIZONTAL
0.001
RVERTICAL
100
kst pot
RHORIZONTAL
100
kst pot'
Propagation Delay Oscillator Inhibit
From Input Clock to Oscillator
Output
Inhibit Output
jJF
2
clock pulses
Input Leakage
1
pA
Input Capacitance
5
pF
Edge Detect Pulse Duration
C = 2 pF, R = 1 Mst
4-54
2
sec
functional description
A block diagram of the MM58106 TV timer is shown in
Figure 1. A connection diagram is shown in Figure 2.
Unless otherwise indicated, the following discussions are
based on Figure 1.
Display Control: The channel number and time display
circuits operate {rom the 4 MHz input clock frequency.
The horizontal and vertical position of the display is
controlled by adjusting the external RC time constants
(RH, CH, RV, Cvl.
50 or 60 Hz Input: This input has a shaping circuit
which allows using a filtered sinewave input. A simple
RC filter such as shown in Figure 4 should be used to
remove possible line voltage transients that could either
cause the clock to gain time or damage the device.
The input should swing between VSS and VDD. The
shaper output drives a counter chain which performs
the timekeeping function.
These monostables are triggered by the horizontal and
vertical retrace signals as shown in the timing diagram in
Figure 3.
A 7-segment decoder is used to decode either channel
inputs or time. Also a time slot decode r is employed to
decode the appropriate time slot and the digit to be
displayed. It generates a video output signal that can
modulate the sweep of the television tube for the onscreen display.
Alternatively, in a crystal controlled battery operated
system, an oscillator and prescaler circuit such as the
MM5369 could be used as a timebase.
50 or 60 Hz Select Input: This input programs the
prescale counter to divide by either 50 or 60 to obtain
. a 1 pps timebase. The counter is programmed for 60 Hz
operation by connecting this input to VSS. An internal
1 MD pull-up resistor is common to this pin; simply
leaving this input unconnected programs the clock for
50 Hz operation.
Channel/Program Number Select: This control pin has
a pull-up resistor to VDD and, with the input open,
the chip will accept a binary plus 1 code on the CU1 to
CU8 inputs and display the program number. For
example, an input code of 0000 will indicate channel 1
and 1111 will indicate channel 16.
Time Setting Inputs: lriputs to set hours and set minutes
as well as a hold input, are provided. Internal 1 MD
pull-up resistors provide the normal timekeeping function. Switching anyone of these inputs (one at a time)
to "0" results in the desired time setting function.
Set Hours advances hours information at 1 hour per
second, and Set Minutes advances minutes information
at one minute per second, without roll over into the
hours counter. The hold input stops the clock to the
minutes counter and resets the seconds counter.
With this input at "0", inputs CU1 to CU8 and CT1 to
CT8 will accept BCD inputs for channel units and
channel tens respectively, and display channels 2-83.
Edge Detect: On program change, the time and number
will be displayed for a period depending on the external
capacitor and resistor connected to the Edge Detect pin
(Figure 4).
I
I-0 - - - - - - - - - 1 6 . 7 m ' - - - - - - - - 1 1
VERTICAL - - - - , I r - - - - - - - - - - - - - - , { J . f - - - - i
RETRACE
U
U
r-
r-1
VERTICAL ----,
TIME OUT
Y'
HOR~~~~~~~ - - - -...U
f
0-------63.6115
f-I
r---u--
------11
HOR~~~~~~~----...~
f~
I
OSCILLATOR
INHIBIT _ _ _ _ _ _ _.....
L..
_ _ _ _ _ _ _ _ __
f---16 P'
---l
ruut.:.:..:.:.:L-________
C~~~~ _ _ _ _ _ _ _ _ _ _
nnn
VIDEO OUTPUT
CHARACTER
_
DISPLAYED _ _ _ _ _ _ _ _ _ _ _....J
_
....- - - - - - - - -
FIGURE 3. Timing Diagram
4-55
typical applications
5V
1M
50/60 Hz 5 VIm, --''\N\r-<'''-~'''---I21
50/60 Hz SELECT 5V-50 Hz
GND-60 Hz
r
TO TV
VIDEO OUTPUT
CIRCUIT
15
20
-.L
SET
JVohflOV
.HRS I9
0;.;.UT.;.;.P.;;..UT'--_ __ . - - - 5 V
r.
-= -.L
.r
SET
231--+-+--'VI1'Ir...J
MIN 18
-.L
FROMTV
!--_.-J\,J'I/'v-HDRIZONTAL
RETRACE
HOLD 16
6.8k
5V-24 HR, GND-12 HR
17
r------------''~-"'_i26
25
. MM58106
28
FROMTV
!--_.-J\,J'I/'v-VERTICAL
RETRACE
\
DISPLAY
OFF
l
CHANNEL {
UNITS
~
8
CHANNEL {
TENS
10
241---+-....>1-...,
14
22
4
~
13
4
11
B
12
DIGIT SELECT
5V-8 DIGITS
GND-5 DIGITS
PRDGRAMICHANNEL SELECT
5V-PROGRAMS (EUROPEAN)
GND-CHANNELS
5V
FIGURE 4.
--~~--~---_.---~~~...-V+
J+
RETRACE
INPUT
I
INPUT
CONFIGURATION
FOR CHANNEL
INPUTS AND
CONTR,DL INPUTS
}
.
{
U
Vl~
OUTPUT .
CONFIGURATION
FOR OSC INHIBIT,
VIDEO OUTPUT,
DIGIT SELECT
,,--vr-
I
I
FIGURE 5. Horizontal and Vertical One·Shot Circuit
4-56
o
o
Analog to Digital (A/D) Converters
M
M
ll:
=;::=
~
..oJ
.,"
..
IMPL,UT
"
,'."
.....
",
BI-FET Technology
LF13300 integrating AID analog building block
general description'
features
The LF13300 is the analog section of a precIsion
integrating analog to digital (A/D) system. JFET and
bipolar transistors (BI-FET) are combined on the same
chip to provide a high input impedance unity gain
buffer, comparator and integrator, along with 9 JFET
analog switches. The LF 13300 has sufficient accuracy
to construct up to a 4 1/2-digit Digital Panel Meter
(DPM) or up to 14-bit (plus sign) Data Acquisition
System and is specifically designed for use with either
the MM5330 BCD digital building block or the MM5863
12-bit binary building block.
•
Rugged JFETs allow blow-out free handling
•
High input impedance> 1000 MD.
•
•
Automatic offset correction
Analog circuitry can be physically and electrically
isolated from high noise digital circuits
•
Analog input range of ± 11 V with ±15V supplies
•
Wide power supply voltage range ±5V to ± 18V
•
•
TTL and CMOS compatible logic
Can interface directly with microprocessors
•
Versatile: can be used as a 12-bit plus sign binary
A/D, 4 1/2-digit, 3 3/4-digit and 3 1/2-digit Digital
Panel Meter (DPM)
.
•
Low cost
",
block and connection diagrams
OFFSET CORRECTION
CAPACITORS
ANALOG
GND
UNKNOWN
INPUT
REFERENCE
BUFFER
IAGI
IVxl
INPUT IVRI
OUT
OPAMP
IN'PUT
OPAMP
OUT
COC2
COCI
COC3
Dual-In-Line Package
POWER
SUPPlVGNO
1
v·
2
18 ANALOG
GNO
11 ANALOG
INPUT
16
COMPARATOR' J
VAEF
OUT
NEG RAMP
15aUFFER
OUT
140PAMP
IN
5
UNKNOWN
POlOET/POS 6
13 DPAMP
OUT
RAMPUNKNQWN
12
OfFSET 1
CORRECT
RAMP
COC2
8
11COCl
REFERENCE
OIGITAl 9
GNO
10
COC3
TOP VIEW
PQWERSUPPLV
GND (PSG)
v·
OPEN·COLLECTOR
COMPAAATOROUT
OFFSET
RAMP
DIGITAL
Order Number LF13300N
DEl/POS.
CORRECT
REFERENCE
OND(OG)
RAMP UNKNOWN
IPOIRU>I
lOCI
IRRI
See Package 20
NEGATIVE RAMP POLARITY
UNKNOWN (RU-)
ICOMPI
TOPVIEW
5-2
r-
::!2
absolute maximum ratings
w
w
Supply Voltage
. Power Dissipation (Note 1)
Operating Temperature Range
Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
electrical characteristics
PARAMETER
o
±18V
570 mW
O°C to +70°C
110°C
-£5°C to +150°C
300°C
o
(VS = ±15V, TA = 25°C, unless otherwise noted)
CONDITIONS
MIN
TYP
MAX
50
500
Analog Input Current, liN
Vx = 0, Currents into Pins 17 and 18,
Test Circuits 1 and 2
Analog Input Voltage Range
Vx adjusted until IIINi? 10 nA,
Test Circuits 1 and 2
Analog Input Resistance
Vx = OV, Test Circuits 1 and 2
1000
VR = 10V, Current into Pin 16,
100
Reference Input Currents, IR
±11
±12
UNITS
pA
V
Mn
1000
pA
Test Circuit 3
VR Adjusted until IIRI?:: 10 nA,
Test Circuit 3
Reference Input Resistance
VR = 10V, Test Circuit 3
Offset Correction Voltage, -VB
Test Circuit 4
Offset Correction Input Current, IOC
Test Circuit 5
200
Op Amp Slew Rate
Test Circuit 6
10
Vips
Op Amp Bandwidth
Test Circuit 7
3
MHz
Buffer Slew Rate
Test Circuit 9
25
VIps
Comparator Response Time
200 pV Input Step, 100 pV
Overdrive, Test Circuit 11
2.5
Comparator Output Saturation
VCC = 5V, RL = 2k,
O°C ~ T A ~ +70°C, Test Circuit 11
0.2
Voltage
11
Mn
500
-12
2.0
Logic "1" Input Voltage
. Logic "0" Input Voltage
0
V
Reference Input Voltage Range
All Switching Input Pins 5, 6, 7 and 8,
-5
V
2000
pA
ps
0.4
V
6
V
0.8
V
O~ TA ~ +70°C
2
Logic Input Current
Power Supply Voltage Range, ±VS
V R ~ V+ - 3V, V IN = OV
±VS is Variable
±4.75
±4
Power Supply Currents, ±IS
20
pA
±18
V
±11
mA
Note 1: For operating at elevated temperatures, the LF13300 in the DIP package must be derated based on the thermal resistance of 100° e/W
junction to ambient.
5·3
o
o
M
M
~
U.
-I
electrical characteristics
12·bit plus sign AID converter system characteristics. (LF13300 with MM5863). (Circuit configured as in Figure 1, VR
10.000V, O°C ~ TA ~ +70°C unless otherwise noted.)
PARAMETER
CONDITIONS
Resolution
= 5.000V, -10V
VR
~
TYP
MIN
MAX
Vx ~ +10V
UNITS
Bits·
14
Nonlinearity
±1/8
±1/2
LSB
Differential Nonlinearity
±1/8
±1/2
LSB
±1/2
±2
LSB
= ±10.000V, T A = 25°C
Ratiometric Gain Error
Vx
Gain Error Drift
Vx
= 10.000V
±1
ppmfC
Zero Reading Drift
Vx
= OV
±0.5
ppmfC
Analog Input Leakage Current
TA
= 25°C,
Vx
= OV
Analog Inl?ut Resistance
TA
= 25°C,
Vx
= OV
Reference Input Voltage Range
TA
= 25°C,
VR Varied
Reference Input Resistance
TA
= 25°C,
VR
Conversion Time
VIN
Analog Input Voltage Range
±12
±1.1
V
50
500
Mn
1000
12
0
Reference Input Leakage Current
100
15V Supply Currents
-15V Supply Currents
= 1O.000V
pA
1000
V
pA
Mn
500
= 10.000V, FC = 250 kHz
.
+
LF 13300, V Current
36
ms
4
11
mA.
LF 13300, V- Current,
27
44.8
mA
23
38.5
mA
MM5863 VGG Current
5V Supply Currents·
VIN
= OV, MM5863, VSS Current
Test Circuit 12
12-Bit AID Converter
ac test circuits
15V
5V
POWER GND
-15V
-=
V+
16
VR
+
REFERENCE INPUT
VOLTAGE
COMP
OUT
3
C01\1P
VR
18
ANALOG INPUT
VOLTAGE
VSS
PG
Vx
22
RU-
AG
17
Vx
1M
21
POIAU+
15
LFI3300
POL YPROPYL: {
CAPACITOR
POL!SER OUT
OR
OVERRANGE
MSB
211 MSB
2SB
PD!RU+
3SB
20
OC
ANALOG ONO
RU-
POL
19
RR
18
DG
4SB
OC
RR
MM5863
12·BIT BINARY
OUTPUTS
GNO
-=
DIGITAL
GND
COCI
20 LSB
COC3
28
SERIAL
CLK
START
CONVERSION
5-4
250kHz
CLK
PARALLEL
!SERIAL
DE !3
OUTPUT·
ENABLE
END OF
CONVERSION
r
:::!2
typical performance characteristics
w
w
o
o
Integration Time Constant
(RCI vs fCLK for Different
Reference Voltages, VR
Integrator Capacitance,
C Vs"fCLK for Different
Integrator Resistances, R
~
1
vs· '15V
vs- '15V
I."
.3
'"
i
·1111
0
I-
U
'"
0.1
~
'"
0
I-
!
0.01
I
0.001
R=IM.vR=10V
0.1
~
;:::
R=2M.VR=10V~
'"
~
1"\
l=.,.
vR - 4V !;8"",,,
0.01 ~
....
['.
III
I'
VR =2V
I."
....
ill
I
~
100
=
t.:J
IIII
10
" VR =;~I~
I'
I-
."
0
ffiR ~,~,OM. VR =10v~
IIIIIII
....
0.001
I
10
1M
100
1M
fCLK (kHz)
fCLK (kHz)
functional description
I
Polarity Determination (Figure 2)
The LF13300 goes through the following 5 states during
normal cycle: 1) Offset Correction; 2) 'Polarity Determination; 3) Initialization; 4) Ramp Unknown; 5) Ramp
Reference.
The simplified diagram of the LF13300 in the Polarity
Determ'ination state is shown in Figure 3. S5 and S3 are
closed during this period. S5 grounds the buffer input
and Vx (the unknown voltage) is applied through S3
to the non-inverting input of A 1. The equation that
describes the op amp output voltage is given in Figure 3.
When Vx is applied to A 1 at t1, the output of the
op amp slews to Vx and is integrated until t2, when
S3 opens and S4 closes. This causes VOUT to slew down
Offset Correction Description (Figure 1)
The Offset Correction scheme will drive the input of .
the comparator to its switching threshold when the
analog input is zero and the timing components, RC,
are bypassed.
by -Vx leaving
The Offset Correction input (OC) is driven high, closing
switches 54-59_
1 jt2 VXdt - VB' on the output
RC
.q
of the op amp. The comparator output goes high if
Vx > 0 and remains low if Vx -::; O.
The offset voltages are assigned as follows: V051 - the
input offset voltage of the buffer; V052 - the input
offset voltage of A 1; VOS3 - the input offset voltage of
A2; VOS4 - the input offset voltage of the comparator.
Initialization (Figure 1)
During initialization, the LF13300 is configured the
same way as it is in the Offset Correction state and the
op amp output is brought back to the Offset Correction
potential -VB'.
S5 grounds the input of the buffer so that its output
voltage is simply VOS1- S6 bypasses R to keep the
integration time constant, RC, from affecting the
circuit operation. S4 makes the total equivalent input
voltage to A1 be -VOS1 - VOS2. S7 puts the op amp
in a unity gain configuration with respect to the input
of A2_ 58 keeps the output voltage of the op amp at
-VB + VOS4 = -VB' (the Offset Correction potential)
since the comparator is placed inside the loop. C3
samples the output of the -VB generator_ The voltage
at the non-inverting input of A2 is -VB + VOS1 +
VOS2 + VOS3 + VOS4 = V1. Thus, the sum of the
offsei:s is stored on C1, and the differential voltage
across the comparator is zero.
Ramp Unknown (Figures 2 and 3)
In the Ramp Unknown state, if Vx ~ 0, S3 and S5 are
closed, as shown in Figure 2, and Vx is applied to the
+ input of the integrator. If Vx -::; 0 and the LF13300 is
connected as in Figure 3 with S2 and S4 closed. Vx is
now applied through the buffer to the - input of the
integrator. In either Ramp Unknown case, the op amp
output ramps in the positive direction and Vx is applied
to a high impedance JFET input.
5-5
o
g
functional description
(Continued)
(II)
lL
..J
Ramp Reference (Figure 4)
In this state, the LF13300 is configured with switches
or
Sl and S4 closed. The reference voltage, VR, a positive
voltage, is applied to the buffer input and the op amp
output ramps down until VOUT = -VB' where the
comparator will trip.
Since t4-t3 = 4096 clock periods and t5-t4 can be
measured in clock periods, VxIV R = X/2 12 , where X is
a digital. binary output representing an analog input
Vx with respect to VR.
If Vx and VR are assumed to be constant over their
respective integration periods, the integrals of Figure 7
are reduced to,
Vx (t4 -' t3)
V R (t5 - t4)
RC
RC
BUF OUT
R
OP AMP IN
-VB'
15
14
13
r-'---~
I
I
I
t
,
I
I
I
L
= -VB + VOS4
i
+
I
I
I
I
COMP OUT
OP AMP OUT
S8
VI
T,-I"
VR
Vx
=-VB + VOSI + VOS2 + VOS3 + VOS4
AG
18
COC2
FIGURE 1. Offset Correction Circuit
5-6
functional description
(Continued)
Vx dt: Ramp Unknown for VIN ~ 0
VOUT=
Vx dt: Polarity Determination
BUF OUT
R
OP AMP IN
OP AMP OUT
VOUT
r-----
I
COMP OUT
+
1
I
I
I
V2
V1
I
I
I
I
L -.IF
4.096V
lOOk
lOT
LM329
26
0.1 pF*
ISV
II
22
18
12
21
28
*
":" VAEF •
"::"
16
LFI3300
, F
TO. •
"::"
lOOk
"::"
20
MM5863
19
25
23
24
GIl
O.Ol,uF**
13
27
ANALOG
INPUT
300
17
SV
.2..
Vx "::"
"::"
5V
SV
5V
NS83881 DISPLAY
13
MSO
550
TSO
LSD
12
118058871
I
3.lk
"-IVV'v-O() SV
1/8058871
*Low leakage mylar
**Polypropylene
D.P. POSITIONING FOR
RANGES
800V
80V
15
Note 1: All diodes, 1 N914.
Note 2: All resistors 1/4W, 5% tolerance.
Note 3: Circuit drawn for 8V full scale operation input scaling not shown.
FIGURE 14.33/4 and 3 1/2-Digit DPM Schematic Diagram
5·13
o
o
typical applications
M
M
u:
(Continued)
3 3/4-Digit (±8191 Counts)/3 1/2-Digit (±1999 Counts)
DPM
..J
The DPM is able to operate from a single 15V power
supply with the aid of a dc-de converter. The LM555
generates the negative voltages required in the circuit
and also doubles as the clock. The combination of
Q1, R2, R3 and R4 forms a level shift to convert the
output swing of the LM555 to a OV-5V swing that is
compatible with the logic. The LM340-5 drops the
incoming ,15V to 5V for use by the logic circuits and
the LED display. .
.
o
In this circuit of Figure 14, the LF13300 and MM5863
interact as previously described. The CMOS counter
(MM74C926, MM74C928) is connected to count clock
pulses during the ramp reference cycle of the LF 13300.
The counts are latched into the display when the comparator output trips, (goes lowl. as shown in the timing
diagram Figure 15.
This circuit can be a 3 3/4·digit DPM if the MM74C926
is used or a 3 1/2-digit DPM if the MM74C928 is used.
These counters are pin compatible and physically interchangeable.
The RC network consisting of R 1 and C1 is a low pass
filter that prohibits the fast transients that occur on the
comparator output during Offset Correction from
loading any erroneous counts into the counter.
RAMP UNKNOWN FOR VIN
>0
OP AMP OUTPUT
PIN 13 (LFI3300)
'>.;n/'1
:$>
:j)
CaMP OUTPUT
PIN 3 (LF13300)
RR
(LF1~~~08)
liIT) EOC
PINS 3.23 (MM5863)
RESET
PIN13
(MM74C926)
_ _ _ _ _ _ _ _.......r--,~
n
n
V
y
________ill
....._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...
I~
~~~~---------uuuuuu
UUUUIf
(MM74C926)
MM5863 ClOCK
LATCH
ENABLE - - - - - - - - PIN
5 (MM74C926)
L
-.
- ..
I OISPLAYS NO. OF CLOCK PULSES
COUNTED WHEN CLOCK WAS
ENABLED
LJ
FIGURE 15. Timing Diagram for 3 3/4-Digit DVM
electrical charac'teristics
3 3/4·digits plus sign (±8191 counts) DPM'system characteristics.
(Circuit as in Figure 18, Vs = ±15V, VR = 4.096V, T = 25°C, unless otherwise noted).
A
PARAMETER
CONDITIONS
-8.2V ~ Vx ~ +8.2V
Resolution
MIN
TYP
MAX-
UNITS
Counts
16,382
VIN
= 4.000V
±1/8
±1/2
Counts
Ratiometric Gain Error
VIN
= 4.000V
±112
±2
Counts
Gain Error Drift
VIN
= 4.000V,
VIN
= OV
Nonlinearity
Zero Reading Drift
,
O°C ~ TA ::; +70°C
±11
Analog Input Voltage Range
Reference Input Voltage Range
Reference Varied
Analog Input Leakage Current
VIN
Conversion Time
ppmfC
±1
ppmfC
VIN
= OV
VIN
= 4.000V, fC = 125
V
±12
+12
0
= OV
Reference I,nput Leakage Current
Analog Input Resistance
±1
50
500
pA
100
1000
pA
MD
1000
5·14
kHz
V
74
ms
r-
typical a pp I·Ications
(Continued)
~
w
w
o
o
.. OPM (Shown 1/2 Size).
FIGURE 16 • PC Board for 3 3/4 and 3 1/2 -Digit
o
~
typical applications
(Continued)
('t)
lL
4 1/2-Digit (±19,999 Counts) DPM
....I
It may be obvious, however, that while we have
eliminated several of the basic dual slope circuits
disadvantages, we have created another-the number
of counts are no longer proportional to V IN but rather
to (VMAX-VIN). In fact, when we short VIN to ground
we are actually measuring our own 2.2000 VMAX-
The following circuit illustrates how a 4 112-digit DPM
can be realized using the LF 13300 and the MM5330.
The MM5330 is the display end control for this integrating system.
It contains the counters and latches together with a
mUltiplexing system to provide 4 digits of display with
one decoder/driver. It also provides a sign bit that is
valid during overrange and a ten thousand count digit
for a full display of ±19,999 counts. By eliminating
the right-most digits it may also be used as a 2 1/2 or
3 1/2-digit DPM_
What is done in the MM5330 is to code convert the
number of counts as shown in the count diagram. This
chart shows a code conversion starting at the time of a
reset. The· first 18,000 counts are the reference period
afte'r which time the integrator changes slope. If a comparator crossing is detected within the next 2000 counts,
a plusoverrange condition will occur at the display.
This condition results in a lit "+" sign, a lit "1" and 4
blanked right-most digits. A transfer a·t 20,000, however,
will create a reading of +1.9999, at 20,001 a reading of
19.998 and so on, until at 39,999 a reading of +0000
. would be displayed. A transfer occuring at 40,000
would cause a -0000 display and so on until 60,000
counts were entered, at which time a -1 with 4 blanked
digits would be displayed, indicating a minus overrange
condition.
The LF 13300 features automatic zeroing of all offset
voltages in its integrator, comparator and buffer amplifiers and, unlike conventional dual. slope techniques,
provides an input impedance> 1000 MD.
The waveform at the integrator output is shown in
Figure 18. At the rising edge of the ·reset pulse the
unknown input voltage is applied to the integrator for
a reference period of 18,000 clock periods. After this
reference period, the 4.0000V reference is applied to the
integrator and the counter is started. The reference
voltage is integrated until the comparator switches.
The display interface used is a TTL, 7-segment decoder/
driver and 4 2N4403 transistors. The ±1 digit is driven
directly by TTL. The clock-synchronous reset and
transfer functions prevent any cyclic digit variations
and present a blink-free, flicker-free display.
At this point, the accumulated counts are transferred
from the counters to the latches and zeroing begins
until the next reset pulse.
COMPARATOR
OUTPUT
RESET
PULSE
VOUT
dt
INTEGRATOR
OUTPUT
dVOUT
dt
= 2.2 -
RC
Vx
RC
-VB --'""--{OFFSET
CORRECT
RAMP
UNKNOWN
Note. Here the LF13300 always operates as an autozeroed, high input impedance inverting integrator;
bipolar input voltages are handled by offsetting the analog ground by 2.2V.
FIGURE 18_ Timing Diagram for 4 1/2-Digit DPM
5-16
r-
typical applications
::!2
(Continued)
w
w
2.2V
o
o
D.DI.f POLYPROPYLENE
OPTIONAL SWITCH
fOR ~Op~~~~
VARIOUS RANGES
FS
20D7
r
II
6
I
20 VFS
II
I
7
..
2VF
1l
L._~_
V
DIGITAL
GNO
~
ANALOG
GNO
~V
Inverters -+ MM74C14 Hex Schmitt Trigger (MOS)
Two letters (AA, BB .. .I NAND gates -+ MM74COO CMOS quad NAND gates
One letter (A, B... ) NAND gates -+ DM7400 TTL quad NAND gates
All resistors 1/4W. 5% unless otherwise noted.
All capaCitor values in jJF unless otherwise noted.
INDUCTIVE COMPONENTS U~XD21
MICROTRANPCTiAlI
TRANSFORMER
STAVER VI
HEATSINK
1I0V
60Hl
r-----.......
---"I~I~V
~ ~ ~ ~ 3 ~ : ~ ~ ~ ::: ;
f-----OIGIT I
!
~. 3 ~ ~ ~ ~ ~ ~ ~. ~ ~
I
First letter code:
A ...... anode
C ...... cathode
NSB5917 Display (Front View)
(Second letter code)
MSD ...... digit 2
SSD -+ digit 3
TSD -+ digit 4
LSD -+ digit 5
FIGURE 19. Schematic Diagram for 4 1/2-Digit DVM
5-17
o
o
M
typical applications.
(Continued)
M
z;:
Component Side Foil
-I
Bottom Side Foil
FIGURE 20. PC Board for 4 1/2:Digit DVM (Shown 1/2 Size)
5-18
r-
typical applications
::!2
(Continued)
w
w
o
o
FIGURE 21. Stuffing Diagram for 4 1I2-Digit DVM (Shown 1/2 Size)
ac test circuits
(Continued)
Test Circuit 2
Analog Input Characteristics Test with PD/RU+ High
Test Circuit 1
Analog Input Characteristics Test with RU - High
_ - - - - -....-18;....a., liN
S2
_,,(')( ).......417_1-1.;.;IN~D Vx
16
NCo-.....,l-~
-VS()o-+-~
r---------~--------++-+~-CVx
NCo---I-~
'4
L---------~~O NC
-VSo--...........t
' - - - - - + - - - - 0 NC
5V()o-+-~
5Vo--. .~
11
11
lF13300
lF13300
10
-0 -12V
I-...~-a -12V
..1;,;:0....____
5-19
0
0
(\')
...
(\')
LL
...I
ac test circuits
(Continued)
Test Circuit 3
Reference Input Characteristic Test with RR High
Test Circuit 4
-VB Voltage Measurement Test
18
17
Vs
Vs
NC
NC
-VS
-VS
, 3
16
LF13300
15
NC
NC
NC
NC
5V
NC
5V
10
10
-V&
-12V
':"
':"
Test Circuit 6
Op Amp Slew Rate Test
Test Circuit 5
Offset Correction Input Current. IOL Test
Vs
Vs
NC
NC
-Vs
-vs
5V:rL
-5V
5V
VOUT
10
IOC3
lac
10
-12V
20 pF
~
lF13300
-12V
':"
':"
Test Circuit 8
Open Loop Gain Test
Test Circuit 7
Frequency Response Test
Vs
Vs
NC
NC
-Vs
-vS
1
AVOL~
VOUT X 105
5V
5V
VIN
.........--<>VOUT
vOUT
lF13300
~
20 pF
10
10
':"
-12V
-12V
':"
':"
5·20
r-
ac test circuits
::!2
(Continued)
w
w
o
o
Test Circuit 9
Buffer Slew Rate Test
Sl
Vs
16
NC
10V=rL
INPUT
-10V
~VOUT
15
-VS
20 pF
NC
lOOk
':'
NC
LF13300
5V
10
-12V
Test Circuit 10
Buffer Voltage Gain Test
Sl
TANTALUM
CAPACITORS
VSn.-......-..!
15V
-15V
NCn--oI-~
-VS
0--+---1
VOUT
LF13300
AV
..1;.,;0...._-0
-12V
5-21
~ 1-
VOUT
1000 VIN
o
~
ac test circuits
(Continued)
M
li:
...J
Test Circuit 11
Comparator Response Time Test
LF13300
Vs~--+--""''''''
COMPARATOR~__~__~~
OUT
-Vs o--+-+-----4
5V ().-....-.f-....;;..j
t---"'--G -12V
10
-12 + 100 IN
-12V
--12-100IlV
=-I=E
1k
VIN
100 mV =:1~r=
-100 mV =a=J-
5·22
Analog to Digital (AID) Converters
For additional application information, see
AN-155 at the end of this section.
MM5330 4 1/2-digit panel meter logic block
general description
features
The MM5330 is a monolithic integrated circuit which
provides the logic circuitry to implement a 4-1/2 digit
panel meter. The MM5330 utilizes P-channel low threshold enhancement mode devices and ion-implanted
depletion mode devices_ All inputs and outputs are TTL
compatible with BCD output for direct interface with
. various display drivers.
•
•
•
•
•
•
dc to 400 kHz operation
TTL compatible inputs and outputs
BCD output code
Overrange blanking
Valid sign bit during overrange
Standard supply voltages; +5, -15V
connection and block diagrams
Dual-I n-Line Package
SSO
16
TSO
15
LSD
14
RESET TRANSFER CLOCK
13
12
11
INT
Voo
10
9
l.-
t-
r-
lOrder Number MM5330N
See Package 19
I
MSD
2
3
4
BCD
BCD
BCD
"I"
"2"
"4"
5
SGN
6
BCD
1
10k
8
Vss
"8"
TOP VIEW
RESET
CLOCK
TRANSfER
2.
2'
22
23
10k
SGN
LSD
5-23
TSD' SSD
MSD
o
M
M
absolute maximum ratings
Lt)
-~
~
Voltage at Any Pin
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Vss + 0.3V to Vss - 25V
O°C to +75°C
-40°C to +125°C
300°C
electrical characteristics
T A within operating range, Vss= 4.75V to 5.25V, V DO = -16.5V to -13.5V unless otherwise specified.
CONDITIONS
PARAMETER
Power Supply Voltage (V ss )
TYP
MAX
4.75
5
5.25
-16.5
Power SJpply Voltage (V DD)
Power Supply Current (Iss)
MIN
No Load
Input Frequency
dc
Reset or Transfer' Pulse Width
Vss = 5V, V DD = -15V
Inputs Driven by TTL or'Square Waves
Inputs Driven by TTL or Square Waves
3
-15
Clock Input Voltage Levels
Logic "1"
Logic "0"
Driven by Sinewave
Driven by Sinewave
V ss-o·5
V ss-25
All Other Outputs
Logic "1"
Logic "0"
V
-13.5
V
30
mA
400
kHz
ns
200
Input Voltage Levels
Logic "1"
Logic "0"
Output Current Levels
Digit Output State
Logic "1"
Logic "0"
-15
UNITS
Vss
= 5V,
5
0.8
V
V
Vss+0.3
V ss -4.5
V
V
V DD =-15V
Vo Forced To 4.75V
Vo Forced To 4.5V
100
-5
Vo Forced To 3V
Vo Forced To O.4V
100
-2
0.1
Delay From Digit Output to BCD Output
FUNCTIONAL DESCRIPTION
Counters: The MM5330' has four -;"10 counters, one
-;..4 counter, and one -;"2 for a count of 80,000 clock
pulses. A ripple carry is provided and all counter flipflops are synchronous with the negative transition of
the input clock. The last flip-flop in the divider chain
(-;..2 in the block diagram) triggers with the "0" to "1" ,
transition of the previous flip-flop. The count sequence
is ihown in the first column of the count diagram.
Reset: All counter stages are reset to "0" and the INT
flip-flop (driving the I NT output) is, set to "1" on the
first negative clock transition after a "0" is applied to
the Reset input. The internal reset is removed on the
first negative clock transition' after the internal reset
has occured and a "1" has been applied to the Reset
input. This timing provides an on-chip reset at least one
clock cycle wide and a one cycle delay to remove reset
before counting begins.
Transfer: Data in the counters is transferred to the
latches when the Transfer input is at "0." If the,
Transfer input is held low the state of the counters is
continuously displayed (see count diagram). Data will
cease to transfer to the latches on the first positive clock
5·24
-20
p.A
mA
p.A
mA
5
p.s
transition after the first negative clock transition after a
"1" is applied to the Transfer input. This provides a
transfer pulse at least one half clock cycle wide and a
half clock cycle delay to remove the transfer signal
before the counters change state.
INT: The integrate output is used ,to set the charge ti me
on a dual, slope integrator. INT is "1" from reset to the
18,000th clock pulse, then "0" until the next reset. The
dual slope integrator is the voltage monitoring part of
the external circuitry needed for a DPM. It charges a
capacitor at a rate proportional to the measured voltage
while INT is "1," then discharges at a rate proportional
to a fixed reference as shown in the dual slope diagram.
When the output of the integrator reaches OV a pulse is
generated and fed into the Transfer input of the chip.
As the dual slope diagram indicates, the number in the,
latches is proportional to the measured voltage.
Multiplexing: The modulo 4 multiplex counter is
triggered by the carry from the second decade counter,
making the multiplex rate one hundredth the counting
rate (4 kHz for a 400 kHz clock). The LSD, TSD, SSD
and MSD (least significant, third significant, second
significant and most significant digits) outputs indicate
by a low level which decade latch is displayed at the
BCD outputs.
'
-
FUNCTIONAL
D~SCRIPTION
(Continued)
sign digit, either plus or minus, and a ten·thousand
counts digit for full display of ±'9999. By eliminating
the right·most digits it may also be used as a 2·' /2 or
3·' /2 digit DVM chip.
Overrange Blanking and Sign: The data in the latch for
the 72 counter is used to detect an out·of·range voltage.
If this latch is "0" the BCD and 'Ok outputs are forced
to all '" 's" and the SGN output is inverted. When the
data in the overrange latch and the sign bit latch are "'"
the sign bit generates the 9's complement of the decade
latches and the complement of the 'Ok latch at the
respective outputs. When the overrange bit is "'" and
the sign bit is "0" true BCD of the decade latches and
the uncomplemented , Ok latch appear at the outputs.
The basic modified dual slope system for which the
MM5330 is designed, is shown in Figure 1. The integrator
is now used in a non·inverting mode and is biased to
integrate negatively for all voltages below V MAX ' Thus
if the maximum positive voltage at V1N is 1.9999V, then
VMAX would be set at 2.200V. In this way, all voltages
measured are below VMAX ' This eliminates the need for
reference switching and provides automatic polarity with
no additional components. Also, it can be shown that
the amplifier input bias currents which cause errors in
conventional dual slope systems are eliminated by merely
zeroing the display. Thus low bias current op amps are
not necessarily required unless a high input impedance is
desired at V 1N •
APPLICATIONS INFORMATION
The MM5330 is the display and control for a modified
dual slope system. It contains the counters and latches,
,together with a multiplexing system to provide 4 digits
of display with one decoder driver. It also provides a
count diagram
INTERNAL STATES
OUTPUTS WITH TRANSFER LOW
BCD
DECADE
OUTPUTS
DECADE
COUNTERS
o
o
o
BLANKING
ZONE
o
o
0
0
0
o
0
•
•
•9
09
o
o
o
•
•7
o
o
o
COMPLEMENT
OUTPUT
INTERVAL
o
0
2
•
•
•
o
o
•
8
•
9
0
9
0
o
•
•
•9
o}
o
POSITIVE
OVER RANGE
•
•
•9
1
0
o
•
•
•9
09
9
0
000
9
9
POSITIVE
VALUE
o
o
1
0
0
099
o
o
•
•
•0
•9,
o
•
•
•
•
9
0
DISPLAY
ZONE
9
0
1
9
o
o
NEGATIVE
OVER RANGE
o 0 0
9
000
r
t
J
5·25
9
o
o
•
•
•9
o
9
O}
0
00000
NEGATIVE
VALUE
0
•
•
•
o
•
•
•
•
o
0
C
o
0
, OUTPUT
BLANKED
•
1
o
•
•
•9
o
9
10000
o
BLANKING
ZONE
0
00
0
•
o
o
TRUE
OUTPUT
INTERVAL
0
0
0
000
•
•
•9
o
•
•
•
9
o
CONTINUOUS
COUNT
s:
s:
U1
W
W
o
parator crossing is detected within the next 2000
counts, a plus overrange condition will occur at the
display. This condition results in a lit "+" sign, a lit "1"
and four blanked rightmost digits. A transfer at 20,000
however: will create a reading of +1.9999, at 20,001 a
reading of 19.998 and so on, until at 39,999 a reading
of +0000 would be displayed. A transfer occuring at
40,000 W9uld cause a -0000 display and so on until
60,000 counts were entered at which time a -1 with
four blanked digits would be displayed indicating a
minus overrange condition.
APPLICATIONS INFORMATION (Continued)
Secondly, the use of a conventional op amp for a
comparator allows zeroing of all voltage offsets in both
the op amp and comparator. This is achieved by zeroing
the voltage on the capacitor through the use of the
comparator as part of a negative feedback loop. During
the zeroing period, the non-inverting input of the
integrator is at V REF • As this voltage is within the active
common·mode range of the integrator the loop will
respond by placing the integrator and comparator in the
active region. The voltage on the capacitor is no longer
equal to zero, but rather to a voltage which is the sum
of both the op amp and comparator offset voltages.
Because of the intrinsic nature of, an integrator, this
constant voltage remains throughout the integrating
cycle and serves to eliminate even large offset voltages.
A typical circuit for a low cost 4 1/2 digit DPM is
shown in Figure 2. The display interface used is a TTL,
7-segment decoder driver and four P-type transistors.
The ±1 digit is driven directly by CMOS. The clocksynchronous reset and transfer functions prevent any'
cyclic digit variations and present a blink-free, flickerfree display. CMOS analog switches are used as reference,
zero, and input switches and used also in the comparator
slew rate circuit.
The waveforms at the output of the integrator are as
shown. The voltage at A is the comparator threshold just
discussed. Simultaneously, with the opening of switch A,
VIN is connected to the input of the integrator via
switch B. The output then slews to V IN. Integr,ation then
begins for the reference period, after which time the
reference voltage is again applied to the input. The
output again slews the difference between V REF and
VIN and integrates for the .unknown period until the
comparator threshold is crossed. At this point, the
accumulated counts are transferred from the counters
to the latches and zeroing begins until the next
conversion interval.
A problem with all dual slope systems occurs when short
integrating times and high clock frequencies are used.
Because of the very slow rise time of the ramp into the
comparator, the output of the comparator will normally
ramp at approximately 1/10 of its actual slew rate.
Thus, a significant number of extra counts are displayed
due to the slow rate of rise of the comparator. A
technique to improve this consists of capacitor Cs and
analog switch four. An unstable positive loop is created
by this capacitor when the comparator comes out of
saturation. This causes the output ·to rise at its slew rate
to the comparator threshold. As soon as th is threshold
is reached the analog switch opens and zeroing is initiated
as previously discussed.
It may be obvious, however, that while we have
eliminated several of the basic dual slope circuits
disadvantages, we have created another-the number
of counts are no longer proportional to VIN but rather
to (VMAX-VIN)' In fact, when we short VIN to ground
we are actually measuring our own 2.2000 V MAX '
A simplified approach to performing the modified dual
slope function combines the MM5330 and the LFl1300
dual slope analog block as in Figure 3.' The LFl1300
provides the front analog circuitry required. This
includes a FET input amplifier, analog switches, integrator and comparator. The' LFl1300 provides auto
zero, > 1000 MD input impedance, and a ±10V analog
range.
What is done in the MM5330 is to code convert the
number of counts as shown in the count diagram. This
chart shows a code conversion starting at the time of a
reset. The first 18,000 counts are the reference period
after which time the integrator changes slope. If a com-
dual slope diagram
18'OOO~1
BLANKING ZONE
OURING INTEGRATION
I
I
rrI
I
I I
POSITIVE OVERRANGE
POSITIVE VALUES
NEGATIVE VALUES
Vx is the analog voltage
to be converted.
5-26
I
I NEGATIVE
: OVERRANGE
COMPARATOR
THRESHOlO _ _
A
TRANSFER
tV MAX
2.200V
FIGURE 1. Modified Dual Slope
0-199.99kn
TERMINALS
2.200V
lHOOIO
5.5V
OHMS
10k
t -......-J\;/'V\r-o
10k
INTEGRATE
-15V
+5V
r----'\M,-----o
+5V
4.IM
+5V
--1100~
12k
'---j._-I-_....
5%
RESET
I---~~---i ./<:>--+--111
SIGN
1--+-------....;..;;-15
~l"Fd
12I-T;.;.;R;.;.;AN.;.;.S_ _ _ _ _---'
MM5JJO
100!!
+5V
+5V
NSN7J
OM7446
RAOI-l00N
FIGURE 2. Typical Application low Cost 41/2 Digit Volt·Ohm Meter
5·27
typical applications
(Continued)
1.lV
I\V
-ISV
Q.0411,f
T
T
1':"
4 ':"
1\
DIJ
,I7'F
D.DI.F PDLYSTYRENE
Uk
6111
OPTIONAL SWITCH
FOR MOVING
VARIOUS
~!N~~~
2DDjFS
I
r
6
I
20 VFS
158
114
1
t
1..._:=_
2VF
Inverters ..... MM74C14 Hex Schmitt Trigger (MOS)
Two letters (AA, BB .. .I NAND gates ..... MM74COO CMOS quad NAND gates
One letter (A, B.. .I NAND gates ..... DM7400 TTL quad NAND gates
l ..... analog ground
..... digital ground
All resistors 1/4W, 5% unless otherwise noted.
All capacitor values in JLF unless otherwise noted.
INOUCTIVE COMPONENTS
U5XD1IMICROTRAN
PCT69]1 TRANSFORMER
6
IIDV
60HJ
...------.-....,-o15V
(Second letter code)
" - - - - - - - -......-o-15V
is
c
Ll
~ ~ ~ ~ ~ ~ ~ :
i------OIGIT 1
!
~
e
~ ~
e
~ ~ ~_~ ~ 5
I
NSB5917 Display (Front View)
First letter code:
A ..... anode
MSD ..... digit 2
C ..... cathode
SSD ..... digit 3
TSD ..... digit 4
LSD ..... digit 5 .
FIGURE 3. 4 1/2-Digit DVM
5-28
s:
s:
U1
timing diagrams
W.
W
4 1/2-Digit DPM
COMPARATOR
OUTPUT
RESET
PULSE
VOUT
dVOUT =2.2-4.0
dt
RC
INTEGRATOR
OUTPUT
dt
-VB .....-I!!:....--T'---""
OFFSET
CORRECT
RAMP
UNKNOWN
Note. Here the LF 13300 always operates
as an autozeroed. high input impedance
inverting integrator; bipolar input voltages are handled by offsetting the analog
ground by 2.2V.
5-29
o
Analog to Digital (AID) Converters
MM5863 12-bit binary AID building block
general description
features
The MM5863 is the digital controller for the LF13300D*
analog building block. Together they forman integrating
12·bit AID converter. The MM5863 proviaes all the
necessary control functions, plus features like auto
zeroing, polarity and overrange indication, .as well as
continuous conversion. The 12-bit plus sign parallel and
serial outputs are TRI-STATE® TTL level compatible.
The device also includes output latches to simplify
data bus interfacing.
•
•
•
12-bit binary output
Parallel or serial output
Parallel TRI-STATE output
•
•
•
•
•
Polarity indication
'.' ..
Overrange indication
Continuous conversion capability
100% overrange capability
5V, -15V power requirements
•
•
TTL compatible
Clock frequency to 500 kHz
*See LF13300D data sheet for more information
connection diagram
Dual-I n-Line Package
28 (P/S) PARALLEL/SERIAL
SELECT
(SCLK) SERIAL CLOCK
(SC) START CONVERSION
(CLK) INPUT CLOCK
(PD) POLARITY
DETECT
25 V
GG
(OE) OUTPUT ENABLE
(LSB) LEAST
SIGNIFICANT BIT
PARALLEL DATA
OUTPUT LINES
2- 12
2- 11
VSS
2- 10
(EO C) END OF
CONVERSION
2- 9
(RN) RAMP NEGATIVE
2- 8
(RP) RAMP POSITIVE
2- 7
(OC) OFFSET
CORRECTI.ON
2- 6
(RR) REFERENCE RAMP
2- 5
GND
2- 4
(POL/SDO) POLARITY/SERIAL
DATA OUTPUT
2-~
(OR) OVERRANGE
2-2
2- 1 (MSB) MOST
SIGNIFICANT BIT
TOP VIEW
Order Number MM5863N
See Package 23
5-30
absolute maximum ratings
5.25V
-16.5V
5.25V
O°C to +70°C
-40°C to +150°C
500 kHz
300°C
Supply Voltage (VSS)
Supply Voltage (VGG)
Voltage at Any Input
Operating Temperature
Storage Temperature
Clock Frequency
Lead Temperature (Soldering, 10 seconds)
electrical characteristics
VSS = 5V, VGG = -15V, o°c to +70°C, unless otherwise specified.
PARAMETER
CONDITIONS
Power Supply Voltage (VSS)
MIN
TVP
MAX
4.75
5.00
5.25
V
-16.5
V
-13.5
Power Supply Voltage (VGG)
-15.00
UNITS
Power Supply Current (ISS)
.28
mA
Power Supply Current (IGG)
34
mA
Logic "1" Input Voltage
3.4
Logic "0" Input Voltage
Logic "1" Output Voltage
VSS=4.75,IOH = 100J.1A
Logic "0" Output Voltage
VSS = 5.25, IOL = -1.6 mA
Width of EOC
Auto Cycle
V
V
3.8
"
V
0.4
Sec
5/f
Prop. Delay PD to EOC
Output Enable Time
V
0.8
4/f
OE to Any Data Output,
5/f+l J.1s
Sec
1.0
J.1s
2.4
J.1s
0.9
J.1s
2.2
J.1S
1.0
J.1s
SC = 1, PIS = 0
Output Disable Time
OE to Any Data Output,
SC = 1, PIS = 0
Output Enable Time
PIS to Any Data Output
Except Polarity, SC = 1,
OE=O
Output Disable Time
PIS to Any Data Output
Except Polarity, SC = 1,
OE=O
Output Enable Time
SC to Any Data Output,
OE = 0, PIS = 0
Output Disable Time
SC to Any Data Output,
2.4
OE = 0, PIS = 0
J.15
i
Prop. Delay Serial Clock
SCLK to POL/SDO
Conversion Time
Full Scale
Conversion Time
100%
Ov~rrange
5-31
0.6
J.1s
8966/f
Sec
13062/f
Sec
M
~
functional description
it)
~
OPERATION
~
The MM5863 is designed for use with the LF 13300
analog front end. Four control signals are supplied to '
the LF13300 and 1 control signal is required from the
LF 13300. The conversion cycle is composed of 5
distinct phases. They are: Phase I - Offset Correct;
Phase II - Polarity Detect; Phase III - Offset Correct;
Phase IV - Ramp Unknown; Phase V - Ramp Reference.
Phase I - Offset Correct (256 Clock Periods)
This phase is initiated by taking the Start Conversion
(SC) and the Output Enable (OE) lines to a logic "1 ".
At this time, Offset Correct (OC) will. be a logic "1 ".
The LF 13300 requires this phase to correct any intrinsic
offset voltage errors prior to the polarity detedt phase.
Phase II - Polarity Detect (256 Clock Periods) .
This phase is used to determine polarity of the analog
input. At the midpoint of this phase, PD from the
LF13300 is examined for polarity. If PD = logic "1",
then the input voltage is positive. If PD = logic "0", then
the input is negative. The Ramp Positive signal (RP)
will be a logic "1", and Offset Correct will be logic "0"
for the entire phase of 256 clock periods. The abov-e
operation is also necessary to determine which integrator
input (positive or negative) of the LF 13300 should be
used for proper AID conversion (see LF 13300 data
sheet).
"1". These 2 signals will never be at logic "1" simultaneously.
Phase V - Ramp Reference
This phase is a variable length phase depending on the
magnitude of the analog input voltage. During this time,
Ramp Reference (RR) will be in the logic "1" state.
When PD goes to a logic "0" state, or when the internal
counter reaches 100% of full scale (8192 clock periods),
the Ramp Reference (RR) signal goes to the logic "0"
state, the counter output is loaded into the output
register, and the End of Conversion, (EOC) signal goes
to a logic "1 ". The Polarity Bit will reflect whatever
value was determined during Phase II. The output
register will hold the data until a new conversion is
completed and new data is loaded into the register.
The OE line must be low in the logic "0" state and SC
must be high in the logic "1" state to enable the outputs.
DATA OUTPUTS,
80th serial and parallel outputs are available. In either
case, OE must be low and SC must be high to enable
the outputs. For parallel output, the PIS line must be
low in the logic "0" state. For serial outputs, the P /S
line must be high. In the serial mode, the data is shifted
out of the Polarity/Serial Output POL/SDO line and all
'other data -outputs are in the high impedance state.
Each Serial Clock (SCLK) will right shift the output
register one bit. Thus, 13 clock pulses are required to
fully shift out the data. The data will be shifted out in
the following order: Polarity, Overrange, MSB, 2SB,
3SB, ... , LSB. If OE and PIS are in the logic "0" state
and SC in the logic "1" state, all outputs will momentarily go to the logic "1" state for 1 clock period
immediately preceding EOC.
Phase III - Offset Correct (256 Clock Periods)
This phase is identical to Phase I and is used by the
LF13300 to eliminate any offsets induced as a result of
the Polarity Detect Phase. Offset Correct (OC) will be at
a logic "1 ".
Phase IV - Ramp Unknown (4096 Clock Periods)
CONTINUOUS CONVERT MODE
The unknown input voltage is integrated for a fixed
time during this phase. The result of the Phase II
Polarity Detect Cycle determines whether' RP or RN
will be at logic "1". If Phase II indicates a positive input,
the RP signal will be a logic "1 ". If phase II indicates a
negative input, Ramp Negative (RN) will be a logic
In this mode, the End of Conversion (EOC) output is
connected to the OE input. As long as SC is in the
logic "1" state, then each EOC will initiate a new conversion. The data outputs will be disabled for the first
5 clock cycles after EOC goes high.
truth table
INPUT
OE
PIS
100% Fu II Scale
0
0
Full Scale
0
0
SC
LSB
MSB
OVERRANGE
1
0
1
1
1
1
1
1
1
Zero
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Zero
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-Full Scale
0
0
0
. 1
-100% Full Scale
0
0
Any
-Any
Any
0
POLARITY
0
1
1
1
X
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
X
X
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z = High Impedance
X = Don't Care
5-32
0
0
0
1 = High
0= Low
0
Z
Serial Output
Z
timing diag rams
The following timing diagrams are shown for the MM5863 connected in the auto-cycle mode.
Positive Input
I
PIiASE I
OFFSET
CORRECT
PHASE II
POLARITY
DETECT
I
PHASE III
OFFSET
CORRECT
PHASE IV
RAMP
UNKNOWN
I
n.JLF
I
PHASE V
RAMP
REFERENCE
I
11/1
CLK
SC
--I
DC
I
256 Xl/I
~
256 Xl/I
____________
4096 Xl/I
256 Xl/I
RP
~r---
~8192Xl/1
RR
1--
PO
EOC (DE)
OUTPUT
fSiilL-______________________---1f5ii"L
>-r<
>-c
DATA FROM PREVIOUS CONVERSION
lT~RI-.S-TA-T-E-')----------------------
DATA,
Negative Input
~
256 Xl/I
256 Xl/I
OFFSET CORR
____________
25fi Xl/I
RP
4096 Xl/I
RN
RR
~r---
___________________........1 ::;B192X 1/1
1--
PO
EOC (DE)
rsiil&.._______________________f5ii"L
Serial Output
EOC (DE)
----1"1________________________________
I
SCLK
I
I
POL/SOD
II ! ~::
PIS
I
OVER RANGE
I
POLARITY
I~---------------------------------------------
-.-l
I
SERIAL OUTPUT
5·33
timing diagrams
(Continued)
Output Enable/Disable Time
DE OR PIS
TRI·STATE''''
DATA OUTPUT
DISABLE
DELAY
Serial Clock Delay
SClK
POL/SOD
Output Enable/Disable Time
SC
DATA
----+---<1
4.0
0.4
ENABlE __
DELAY
block diagram
Digital Control Integrated Circuit
VREF
!
+ I
VIN
CLOCK
GENERATOR
I
-It
I(ClK)
13-8IT
COUNTER
SERIAL CLOCK
BIPOLAR ANALOG
(SClK)
INTEGRATED CIRCUIT
lF13300 CONTAINING
OP AMP, SWITCHES,
POLARITY
COMPARATOR AND
DETECT (PD)
RELATED CIRCUITRY
4 LINES
,.....--+ INDICATION
OUTPUT
lATCHES
II-
--
(OR)
12 LINES
12·BIT
PARAllEL
OUTPUT
TRI·STATE@
BUFFERS
t
+
POLARITY
lATCH
l
I{
r+
}
r
+
A
OVERRANGE
OVERRANGE
DETECTOR
r+
I-
DATA
f-+ POLARITY/SERIAL
(POl/SDO)
t
SWITCH CONTROL
lOGIC
'f
END OF CONV. (EOC)
START CONV. (SC)
TRI·STATE
ENABlE
OUTPUT ENABLE (DE)
PARAllEL/SERIAL (P/S)
5·34
typical applications
33/4-3 1/2·0igit OPM
5.1
lNl004
15V
T
1O
"F
26
15V
22
7.5k
21
':"
20
LM329
':"
MM5863
19
25
-12V
23
27
300
17
':"
5V
5V
':"
5V
':"
':"
15
13
16
17
12
MM74C926
1
2
3
4
':"
11
10
.
.
NS83881 DISPLAY
MSD
SSD
TSD
LSD
300
b
c
DP
d
f
1/8 DS8871
9
....""',...,..-o5V
8
1/8 DS8871
800mV
r'
':"
15
Note 1: All diodes, 1 N914.
Note 2: All resistors 1/4W, 5% tolerance.
Note 3: Circuit drawn for 8V full scale operation input scaling not shown.
5·35
8V
2 D.P. POSITIDNING FDR
RANGES
800V
80V
Analog to Digital (AID) C~nverters
DIGITAL VOLTMETERS AND THE MM5330
INTRODUCTION
Polarity selection was made -by a front panel switch
which internally rearranged references and other circuitry.
The first of what could be called the modern digital
voltmeter began to appear in the early sixties. Prior to
that time a few laboratory types were available, but
they were plagued by inaccuracy, temperature drifts,
and other problems inherent in vacuum tube technology_
An example of today's use of the VCO technique is
shown in Figure 2. This is a low cost digital thermometer,
which, while not a DVM, still employs the basic components of the voltage-controlled oscillator system.
These are the high gain amplifiers contained in the
LM5700, thedc-to·frequency converter consisting of the
transistor source and LM555 timer, and the frequency·
to-dc converter consisting of the CMOS inverters and
reference voltage. This brings up a characteristic of
CMOS most useful in DVM's and other analog-todigital converters, the ability to switch directly to the
supply and ground without offsets. In this case the
fixed width negative-going pulses, when filtered, produce
a feedback voltage directly proportional to the number
of pulses-frequency-to-dc conversion.
One of the first successful, relatively low cost DMVS
was a gated voltage-controlled oscillator configuration.
The components of this technique consist of a high
gain amplifier, a dc-to-frequency converter, and a linear,
accurate frequency to-dc-converterdeveloped from the
reference voltage, which supplies the summing voltage
at the input node. The amplifiers used were of the
chopper stabil ized type, that is, the error voltage is
chopped to from an ac component which is amplified
by ac coupled amplifiers then reconverted to dc. The
choppers were made with light sensitive resistors, neon
bulbs and light pipes.
They were built as the only method possible to avoid
the drifts and offsets which were unavoidable in early
transistor technology. Obviously the low current op
amps so readily available today, are a significant advantange over these old systems.
The early counter storage display system previously
mentioned, is shown in Figure 3. Because the best
display available was the gaseous tube, no attempt was
made to blank displays during the counting period.
When the gate closed, the counters had reached a
certain count and these counts were displayed.
The gate voltage was developed from the 60 Hz line. A
problem which occurs when the gate, is asynchronous
with the frequency fed to the display counter, is also
shown in Figure 1. A beat frequency effect is developed
between the gate and the dc to frequency converter and
produces a cyclic one digit error. These early voltmeters
allowed this phenomenon to occur, today cyclic display
errors are unacceptable.
After the development of the integrated circuit, displays
took on a configuration as in Figure 4. Between the
counters and display, latches were placed to display'
previous data while new counts were accumulated. The
cost and pack count of this scheme made another
display technique popular, that of multiplexing.
A second display characteristic of these early voltmeters,
was to use the ripple counters as the display storage,
that is, the rippled counts would move through the
display until the gate closed and the final value would be
displayed. This was done primarily because of the number
of discrete devices required to perform counting and
latching. With the coming of integrated circuits, displays
were improved, latches were employed, and blink-free
displays were adopted.
Briefly, this technique consists of connecti ng, sequentially, each of the latches to a single decoder driver
which drove the display digit which corresponded to
that latch. When sequenced at a 50 Hz rate or greater, a
flicker-free display results. For this type of display
system, TRI·STATE® counter-latches were developed
(Figure 5). This technique is still used today in many
DVM's.
TO DISPLAY
COUNTERS
6 COUNTS
5 COUNTS
:::!JJ I I I I I 1l!J-
::!d11111lG:
FIGURE 1. Basic veo Scheme
5-36
»
2
.!.t.
U1
U1
LM555
VREF
TI~
GND
FIGURE 2. Typical VCO Circuit
FIGURE ,3. Early Display Configurat,ion
liN
GATE
FIGURE 4. Integrated Circuit Display
5-37
COUNTER
TRI·ST ATE'"
I NPUT
LATCH
r-
I I
I
I
r---
-
COUNTER
COUNTER
LATCH
LATCH
r-
1I
1 I
1
1
-
COUNTER
-
LATCH
I
I
T
I1
OECOOER
ORIVER
K
OISPLAY
~
K
DISPLAY
DISPLAY
1I
I
~.
DISPLAY
I
MULTIPLEX
CONTROL
FIGURE 5. Multiplexed Display
While multiplexing cuts display costs considerably, the
series connection of counters required to accumulate the
counts proportional to voltage, could not be multiplexed to do the very nature of VCO or dual slope
voltmeter schemes.
repeated for the next digit. At a repetition rate of 50 Hz
or greater, this produces a flicker-free, blink-free display.
As such the recirculating remainder system has but one
counter, one latch, and one decoder driver for as many
digits as are desired. Once again CMOS is used for its
capability to swing directly to the supply rail and controls the R-2R ladder directly from the reference voltage.
The recirculating remainder circuitry to be discussed
next is unique in that the data is both derived and
displayed on multiplexed, that is sequential digit basis'
(as seen in Figure 6.)
The technique used in the recirculating remainder
circuit is to subtract digit valued voltage steps from the
input voltage, until ten times the difference between
these two voltages is less than ten times the digit valued
steps. The number of voltage steps required is the
display data and the ten times the difference voltage
becomes the new voltage input for the next digit
conversion. An example is shown in Figure 7.
Some disadvantages of the system are the difficulties in
reading voltages of both polarities and an unusual sort
of error characteristic when slight ladder 'or reference
drifts occur. While both VCO and dual slope techniques
have gradual slope or linearity errors, the recirculating
,remainder errors are step-like in response to gradual input
voltage changes. Lastly, the update rate is fixed by
display flicker requirements and thus measurements of
noisy voltages cause an annoying inability to read the
last digits. It was however, an accurate low-cost technique
used successfully. in pre-LSI digital voltmeters.
An analog input of 6.903V is applied to the [(V IN V STEP ) x 10] amplifier. The 712 and decade counters
are clocked simultaneously until a (difference x 10) less
than V REF is detected by the comparator. At this time,
the dec,ade counter stops counting. In this example, the
decade counter ceases counting on a six during the digit
one period, thus a six is latched in the display. When the
digit period ends, both counters are reset' and the
(difference x 10) voltage is recirculated via the CMOS
switch and sample and hold capacitor to become the
digit two input voltage (9.03V). The process is then
The most widely used system for analog-to-digital
'conversion is the dual slope circuit. The basic dual slope
system appears in Figure 8. Assuming the integrator
output at zero when Vx is applied, the integrator
begins to ramp with an output voltage V = Ix tiC
where Ix = -V x/R. Simultaneously with the beginning
of this ramping, counts from an oscillator are fed into
the display counters. At some fixed time, usually
counter overflow, Vx would be disconnected and the
reference voltage connected to the resistor. The integrator now ramps at V = IREF tiC where IREF = VREF/R.
5-38
»
z
.!...
CJ1
CJ1
SWITCH C
D.P.2&4
Your
=(V ,N • VSTEP ) x 10
SWITCHD
*
9R
DECODE
DRIVE
LATCH
LATCH
DP2
DPJ
DP4
DPI
r------.. D.P. 1
r-----..
D.P.2
D.P. J
DIGITIZING PERIOD 4
CLK
FIGURE 6. Basic Recirculating Remainder System
90.30
Example:
(Voltage in
= 6.903V)
6.903
-6.000
6 1.000V steps-display 6
0.903 x 10 = 9.03
OUTPUT OF (V ,N - VsrEP ) X 10 AMP
9V
9.030
-9.000
0.03
OV
9 1.000V steps-display 9
x 10 = 0.3
0.300
---0.000
DIGITIZE
DIGIT 1
DIGITIZE
DIGIT 2
DIGITIZE
DIGIT 3
DIGITIZE
DIGIT4
DIGITIZE
DIGIT 1
DISPLAY
DIGIT4
DISPLAY
DIGIT 1
DISPLAY
DIGIT2
DISPLAY
DIGIT3
DISPLAY
DIGIT 4
SWITCHES
E&D
CLOSED
SWITCHES
A&C
CLOSED
SWITCHES
B&D
CLOSED
SWITCHES
A&C
CLOSED
SWITCHES
E&O
CLOSED
0.3
3.000
-3.000
FIGURE 7. Recirculating Remainder Waveforms
5·39
0 1.000V steps-display 0
x 10
=3
3 1.000V steps-display 3
Lt)
Lt)
'.I
Z
2
I
~
CJ1
CJ1
FIGURE 12. Typical A pp I'.cation MM5330
Analog to Digital (A/D) Converters
SPECIFYING AID AND DIA CONVERTERS
The specification or selection of analog-to-digital (A/D)
or digital-to-analog (0/ A) converters can be a chancey
thing unless th'e specifications are understood by the
person making the selection. Of course, you know you
want an accurate converter of specific resolution; but
how do you insure that you get what you want? For
example, 12 switches, 12 arbitrarily valued resistors, and
a reference will produce a 12-bit OAC exhibiting 12
quantum steps of output voltage. In all probability, the
user wants something better than the expected performance of such a OAC. Specifying a 12·bit OAC or an
AOC must be made with a full understanding of accuracy,
linearity, differential linearity, monotonicity, scale, gain,
offset, and hysteresis errors.
Accuracy is sometimes considered to be a non-specific
term when applied to D/ A or A/D converters. A linearity
spec is generally considered as more descriptive. An
accuracy specification describes the 'worst case deviation
of the DAC output voltage from a straight line drawn
between zero and full scale; it includes all errors. A
12-bit DAC could not have a conversion accuracy better.
than ±% LSB or ±1 part in 2 1:l+" (±0.0122% of full
scale due to finite resolution). This would be the case in
figure 1 if there were no errors. Actually, ±0.0122% FS
represents a deviation from 100% accuracy; therefore
accuracy' should be specified as 99.9878%. However,
convention would dictate 0.0122% as being an accuracy
spec rather than an inaccuracy (tolerance or error) spec.
This note explains the meanings of and the relationships
between the various specifications encountered in A/O
and D/ A converter descriptions. It is intended that the
meanings be presented in the simplest and clearest
practical terms. Included are transfer curves showing the
several types of errors discussed. Timing and control
signals and several binary codes are described 'as they
relate to A/D and O/A converters.
Accuracy as applied to an ADC would describe the
differe'nce between the actual input voltage and the fullscale weighted equivalent of the binary output code;
included are quantizing and all other errors. If a 12·bit
ADC is stated to be ±1 LSB accurate, this is equivalent
to ±0.0245% or twice the minimum possible quantizing
error of 0.0122%. An accuracy spec describes the
maximum sum of all errors including quantizing error,
but is rarely provided on data sheets as the several errors
are listed separately.
MEANING OF PERFORMANCE SPECS
Resolution describes the smallest standard incremental
change in output voltage of a OAC or the amount of
input voltage change required to increment the output of
an AOC between one code change and the next adjacent
code change. A converter with n switches can resolve 1
part in 2n. The least significant increment is then 2· n , or
one least significant bit (LSB). In contrast, the most
significant bit (MSB) carries a weight of 2-1. Resolution
applies to DACs and ADCs, and may be expressed in
percent of full scale or in binary bits. For example, an
AOC with 12-bit resolution could resolve 1 part in 212
(1 part in 4096) or 0.0245% of full scale. A converter
with 10V full scale could resolve a 2.45mV input change.
Likewise, a 12-bit DAC would exhibit an output voltage
change of 0.0245% of full scale when the binary input
code is incremented one binary bit (1 LSB). Resolution
is a design parameter rather than a performance specification; it says nothing about accuracy or linearity.
FS
010 011 100 101 110 111
DIGITAL CODE
FIGURE 1.
5-44
Linear DAC Transfe~ Curve Showing Minimum
Resolution Error and Best Possible Accuracy
l>
2
I
~
Quantizing Error is the maximum deviation from a
straight line transfer function of a perfect ADC. As, by
its very nature, an ADC quantizes the analog input into
a finite number of output codes, only an infinite
resolution ADC would exhibit zero quantizing error. A
perfect ADC, suitably offset V:z LSB at zero scale as
shown in figure 2, exhibits only ±V:z LSB maximum
output error. If not offset, the error will be +6 LSB as
shown in figure 3. For example, a perfect 12-bit ADC
will show a ±V:z LSB error of ±O.0122% while the
quantizing error of an 8-bit ADC is ±Y2 part in 2 8 or
±O.195% of full scale. Quantizing error is not strictly
applicable to a DAC; the equivalent effect is more
properly a resolution error.
U1
FS
//
/}
en
1 LSB
IDEAL SLOPE ""\ / / / /
...
...
/
:::>
/
/
:::>
/
c
/
/
'"c
/
~
c(
000 001 010 011 100 101 110 111
DIGITAL CODE
FIGURE 4.
linear,1 lSB Scale Error
111
110
Gain Error is essentially the same as scale error for an
ADC. In the case of a DAC with current and vo(tage
mode outputs, the current output could be to scale
while the voltage output could exhibit a gain error. The
amplifi"er feedback resistors would be trimmed to correct
the gain error.
101
c
S
100
~
011
t!i
cOlO
001
Offset Error (zero error) is the output voltage of a DAC
with zero code input, or it is the required mean value· of
input voltage of an ADC to set zero code out. (See
figure 5.) Offset error is usually caused by amplifier or
comparator input offset voltage or current; it can usually
be trimmed to zero with an offset zero adjust potentiometer external to the DAC or ADC. Offset error may be
expressed in % FS or in fractional LSB.
FS
ANALOG ·INPUT
FIGURE 2.
ADC Transfer Curve, Y:z lSB Offset at Zero
FS
111
/
/
110
101
~
100
~
011
t!i
cOlO
001
FS
ANALOG INPUT
FIGURE 3.
DIGITAL COOE
ADC Transfer Curve, No Offset
FIGURE 5.
Scale Error (full scale error) is the departure from design
output voltage of a DAC for a given input code, usually
full-scale code. (See figure 4.) In an ADC it is the departure of actual input voltage from design input voltage for
a full-scale output code. Scale errors can be caused by
errors in reference voltage, ladder resistor values, or
amplifier gain, et. al. (See Temperature Coefficient.)
Scale errors may be corrected by adjusting output
amplifier gain or reference voltage. If the transfer curve
resembles that of figure 7, a scale adjustment at % scale
could improve the overall ± accuracy compared to an
adjustment at full scale.
linear, Y:z lSB Offset Error
Hysteresis Error in an ADC causes the voltage at which a
code transition occurs to be dependent upon the direction
from which the transition is approached. This is usually
caused by hysteresis in the comparator inside an ADC.
Excessive hysteresis may be reduced by design; however,
some sl ight hysteresis is inevitable and may be objectionable in converters if hysteresis approaches V:z LSB.
Linearity, or, more accurately, non-linearity specifications describe the departure from a linear transfer curve
for either an ADC or a DAC. Linearity error does not
include quantizing, zero, or scale errors. Thus, a specifi-
5-45
co
Il)
'7
Z
«
cation of ±% LSB linearity implies error in flddition to
the. inherent ±% LSB quantizing or resolution error. In
reference to figure 2, showing no errors other than
quantizing error, a linearity error allows for one or more
of the steps being greater or less than the ideal shown.
Figure 6 shows a 3-bit DAC transfer curve with no more
than ±Y2 LSB non-linearity, yet one step shown is of zero
amplitude. This is within the specification, as the maximum deviation from the ideal straight line is ±1 LSB
(% LSB resolution error plus % LSB non-linearity). With
any linearity error, there is a differential non-linearity
(see below). A ±% LSB linearity spec guarantees
monotonicity (see below) and";;; ±1 LSB differential non- .
linearity (see below). In the example of figure 6, the
code transition from 100 to 101 is the worst possible
non-linearity, being the transition from 1 LSB high at
code 100 to 1 LSB low at 110. Any fractional nonlinearity beyond ±% LSB wilt allow for a non-monotonic
transfer curve. Figure 7 shows a typical non-linear curve;
non-linearity is 1% LSB yet the curve is smooth and
monotonic.
000 001 010 011 100 101 110 111
DIGITAL CDDE
FIGURE 6.
Differential Non-Linearity indicates the difference between actual analog voltage change and the ideal (1 LSB)
voltage change at any code change of a DAC. For
example, a DAC with a 1.5 LSB step at a code change
would be said to exhibit % LSB differential nonlinearity (see figures 6 and 7). Differential non-linearity
may be expressed in fractional bits or in % FS.
Differential linearity specs are just as important as linearity specs because the apparent quality of a converter
curve can be significantly affected by differential nonlinearity even though the linearity spec is good. Figure 6
shows a curve with a ±% LSB linearity and ±1 LSB
differential non-linearity while figure 7 shows a curve
with +1 % LSB linearity and ±% LSB differential nonlinearity. In many user applications, the curve of figure 7
would be preferred over that of figure 6 because the
curve is smoother. The differential non-linearity spec
describes the smoothness of a curve; therefore it is of
great importance to the user. A gross example of differential non-linearity is shown in figure 8 where the
linearity spec is ±1 LSB and the differential linearity
spec is ±2 LSB. The effect is to allow a transfer curve
with grossly degraded resolution; the normal 8-step curve
is reduced to 3 steps in figure 8. Similarly, a 16-step
curve (4-bit converter) with only 2 LSB differential nonlinearity could be reduced to 6 steps (a 2.6-bit converter?). The real message is, "Beware of, the specs."
Do not ignore or omit differential linearity characteristics on a converter unless the ~ linearity spec is tight
enough to guarantee the desired differential linearity. As
this characteristic is impractical to measure on a production basis, it is rarely, if ever, specified, and linearity is
the primary specified parameter. Differential non-linearity can always be as much as twice the non-linearity, but
no more.
±% LSB Non-Linearity (Implies 1 LSB Possible
Errorl. 1 LSB Differential Non-Linearity (Implies
Monotonicity)
FS
/
/
/
2lSBDIFF
,
FS
NON.~INEAR
....
:::>
....
:::>
)///
3 lSB
/
///
n-/-/.......-~t
c
JlSB
'"c
2 lSB DIFF
NON·lINEAR
0--.. . .--------
~
±Y:z
FIGURE 10.
LSB Non-Linear)
CAe Slew and Settling Time
bits are switched); These glitches are normally of
extremely short duration but could be of Y:z scale
amplitude. The current switching gl itches are generally
somewhat attenuated at the voltage output of the DAC
because the output amplifier is unable to slew at a very
high rate; they are, however, partially coupled around
the amplifier via the amplifier feedback network and
seen at the output. The output amplifier introduces
overshoot and some non-critically damped ringing which
may be minimized but not entirely eliminated except at
the expense of slew rate and settling time.
Settling Time is the elapsed time after a code transition
for DAC output to reach final value within specified
limits, usually ±Y:z LSB. (See also Conversion Rate below.)
Settling time is often listed along with a slew rate
specification; if so, it may not include slew time. If no
slew rate spec is included, the settling time spec must be
expected to include slew time. Settling time is usually
summed with slew time to obtain total elapsed time for
the output to settle to final value. Figure 10 delineates
that part of the total elapsed time which is considered to
be slew and that part which is settling time. It is
apparent from thi~ figure that the total time is greater
for a major than for a minor code change due to
amplifier slew limitations, but settling .time may also be
different depending upon amplifier· overload recovery
characteristics.
Temperature Coefficient of the various components of a
DAC or ADC can produce or increase any of the several
errors as the operating temperature varies. Zero scale
offset error can change due to the TC of the amplifier
and comparator input offset voltages and currents. Scale
error can occur due to shifts in the reference, changes in
ladder resistance or non-compensating RC product shifts
in dual-slope ADCs, changes in beta or reference current
in current switches, changes in amplifier bias current, or
drift in amplifier gain-set resistors. Linearity and monotonicity of the DAC can be affected by differential
temperature drifts of the ladder resistors and switches.
Overshoot, settling time, and slew rate can be affected
by temperature due to internal change in amplifier gain
and bandwidth. In short, every specification except
resolution and quantizing error can be affected' by
temperature changes.
Slew Rate is an inherent limitation of the output
amplifier in a DAC which limits the rate of change of
output voltage after code transitions. Slew rate is usually
anywhere from 0.2 to several hundred volts/~s. Delay in
reaching final value of DAC output voltage is the sum of
slew time and settling time as shown in figure 10.
Overshoot and Glitches occur whenever a code transition
occurs in a DAC. There are two causes. The current
output of a DAC contains switching glitches due. to
possible asynchronous switching of the bit currents
(expected to be worst at half-scale transition when all
5·47
Long-Term Drift, due mainly to resistor and semiconductor aging can affect all those characteristics which
temperature change can affect. Characteristics most
commonly affected are linearity, monotonicity, scale,
and offset. Scale change due to reference aging is usually
the most important change.
coded system. For example, a 12-bit BCD system has a
resolution of only 1 part in 1000 compared to 1 part in
,4096 for a binary system. This represents a loss in
, resolution of over 4:1.
Supply Rejection relates to the ability of a DAC or ADC
to maintain scale, offset, TC, slew rate, and linearity
when the supply voltage is varied. The reference must, of ,
course, remain constant unless considering a mUltiplying
DAC. Most affected are current sources (affecting
linearity and scale) and amplifiers or comparators
(affecting offset and slew rate). Supply rejection is
usually specified only as a % FS change at or near full
scale at 25° C.
Conversion Rate is the speed at which an ADC or DAC
can make repetitive data conversions. It is affected by
propagation delay in counting circuits, ladder switches
and comparators; ladder RC and amplifier settling times;
amplifier and comparator slew rates; and integrating time
of dual-slope converters. Conversion rate is specified as a
number o'f conversions per second, or conversion time is
specified as a number of microseconds to complete one
conversion (including the effects of settling time). Sometimes, conversion rate is specified for less than full
resolution, thus showing a misleading (high) rate.
Clock Rate is the minimum or maximum pulse rate at
which ADC counters may be driven. There is a fixed
relationship between the minimum conversion rate and
the clock rate depending upon the converter accuracy
and type. A1I factors which affect conversion rate of an
ADC limit the clock rate.
Offset Binary is a natural binary code except that it is
offset (usually % scale) in order to represent negative and
positive values. Maximum negative scale i~ represented to
be all "zeros" while maximum positive scale is represented
as all "ones." Zero scale (actually center scale) is then
represented as a leading "one" and all remaining "zeros."
The comparison with binary is shown in figure 11.
Twos Complement Binary is an alternate and more
widely used code to represent negative values. With this
code, zero and positive values are represented as in
natural binary while all negative values are represented
in a twos complement form. That is, the twos complement of a number represents a negative value so that
interface to a computer or microprocessor is simplified.
The twos complement is formed by complementing each
bit and then adding a 1; any overflow is neglected. The
decimal number -8 is represented in twos complement
as follows: start with binary code of decimal 8 (off
scale for ± representation in 4 bits so not a valid code in
the ± scale of 4 bits) which is 1000; complement it to
0111; add 0001 to get 1000. The comparison with offset
binary is shown in figure 11. Note that the offset binary
representation of the ± scale differs· from the twos
complement representation only in that the MSB. is
complemented. The conversion from offset binary to
twos complement only requires that the MSB be inverted.
111
Input Impedance. of an ADC describes the load placed
on the analog source.
110
101
c
Output Drive Capability describes the digital load driving
capability of an ADC or the analog load driving capacity
of a DAC; it is usually given as a current level or a voltage
output into a given load.
B 100
I-
~ 011
co 010
001
CODES
Y,
Yo
Several types of DAC input or 'ADC output codes are in
common use. Each has its advantages depending upon
the system interfacing the cqnverter. Most codes are
binary in form; each is described and compared below.
Natural Binary (or simply Binary) is the'usual 2 n code
with 2,4,8, 16, ... , 2 n progression. An input or output
, ANALOG SCALE
(a) Zl!ro to + Full-Scale
011 011 111
high or "1" is considered a signal, whereas a "0" is
considered an absence of signal. This is a positive true
binary signal. Zero scale is then all "zeros" while full
scale is all "ones."
010 010 110
001 001 101
000
000 100
100
Complementary Binary, (or Inverted Binary) is the
negative true binary system. It is identical to the binary
code except that all binary bits are inverted. Thus, zero
scale is all "ones" wtlile full scale is all "zeros."
-¥.
-%
101 111 011
110 110 010
111 101 001
Binary Coded Decimal (BCD) is the represel1tation of
decimal numbers in binary form. It is useful in ADC
systems intended to drive decimal displays. Its advantage
over decimal is that only 4 lines are needed to represent
10 digits. The disadvantage of coding DACs or ADCs in
BCD is that a full 4 bits could represent 16 digits while
only 10 are represented in BCD. The full-scale resolution
of a BCD coded system is less than that of a' binary
100 000
t t
I
'~OFFSET BINARY
TWOS COMPLEMENT BINARY
SIGN + MAGNITUOE
(b)
±
FIGURE 11.
5-48
Full-Scale
ADC Codes',
Sign Plus Magnitude coding ~ontains polarity information
in the MSB (MSB == 1 indicates a negative sign); all
other bits represent magnitude only. This code is compared to offset binary and twos complement in figure 11.
Note that one code is used up in providing a double
code for zero. Sign plus magnitude code is used in
certain instrument and audio systems; its advantage is
that only one bit need be changed for small scale changes
in the vicinity of zero, and plus and minus scales are
symmetrical. A DVM might be an example of its use.
data is valid. Typically, an EOC output can be connected
to an SC input to cause the ADC to operate in continuous conversion mode. In non-continuous conversion
systems, the SC signal is a command from the system to
the ADC. A DAC does not supply· an EOC signal.
Clock signals are required or must be generated within
an ADC to control counting or successive approximation
registers. The clock controls the conversion speed within
the limitations of the ADC. DACs do not require clock
signals.
CONTROL
CONCLUSION
Each ADC must accept and/or provide digital control
signals telling it and/or the external system what to do
and when to do it. Control signals should be compatible
with one or more types of logic in common use. Control
signal timing must be such that the converter or con·
nected system will accept the signals. Common control
signals are listed below.
Once the user has a working knowledge of DAC or ADC
characteristics and specifications, he should be able to
select a converter to suit a specific system ne~d. The
likelihood of overspecification, and therefore an un~
necessarily high cost, is likewise reduced. The user will
also be aware that specific parameters, test conditions,
test circuits, and even definitions may vary from
manufacturer to manufacturer. For practical production
reasons, parameters may not be tested in the same
manner for all converter types, even those suppl ied by
the same manufacturer. Using information in this note,
the user should, however, be able to soh out and understand those specifications (from any manufacturer)
pertinent to his needs.
Start Conversion (SC) is a digital signal to an ADC which
initiates a single conversion cycle. Typically, an SC signal
must be present at the fall (or rise) of the clock waveform
to initiate the cycle. A DAC needs no SC signal; however,
such could be provided to gate digital inputs to a DAC.
End of Conversion (EOC) is a digital signal from an ADC
which informs the external system that the digital output
5-49
Communications/CB Radio Circuits
MM5303 universal fully asynchronous receiver/transmitter
general description
The MM5303 is a fully asynchronous receiver/transmitter, fabricated with National's metal-gate, depletion load,
PMOS technology. All inputs and outputs are fully TTL
compatible, requiring no external resistors or level
shifting.
•
Fully externally programmable:
Word length
Parity mode
Numbkr of stop bits
•
Fully double buffered eliminating need for precise
synchronization
This device is a programmable interface between an
asynchronous serial data channel a"nd a parallel data
channel. The transmitter section converts parallel
data into a serial word which includes: start bit, data,
parity bit (if selected), and stop bit(s). The receiver
converts a serial word of the same format into a parallel one and automatically checks start bit, parity (if
selected), and stop bit(s).
•
Full or half_duplex operation
•
•
Direct TTL/DTL compatibility
Automatic data received/transmitted status generation
•
TRI-STATE outputs
•
Automatic start bit generation/verification
•
Internal pull-ups on all inputs
Both transm itter and receiver are doubly buffered; in
addition, received data out and status words may be
TR I-STATED, facilitating bus configurations.
a~plications
Status conditions are: transmission complete, Tx buffer
register empty, Rx data available, parity error, framing
error, and over-run error.
•
Peripherals
•
•
Terminals
Mini computers
•
Facsimile transmission
•
•
•
Modems
Concentrators
Asynchronous data multiplexers
•
Card and tape readers
•
Printers
Data sets
Controllers
Keyboard encoders
Remote data acquisition systems
Asynchronous data cassettes
The MM5303 is fully programmable. It <;,an operate
full or half duplex, transmitting and receiving simultaneously at different baud rates; wo~d length may be 5,
6, 7 or 8 bits; parity generation/checking may be even,
odd or inhibited; the number of stop bits may be either
1 or 2, with 1 1/2 bits when transmitting a 5 bit code.
•
Low power
•
•
•
•
•
High speed
•
features
connection diagram
Dual-In-Line Package,
40
VSS
TCP
VGG
POE
VOD
NDB 1
ROE
NDB 2
RO 8
NSB
RD 7
NPB
RD 6
CS
TO 8
RD 5
RD 4
RD J
TD 7
10
TD 6
RD 2
TD 5
RD 1
TD 4
RPE
TD J
RFE
TD 2
ROR
TD 1
SWE
TSO
TEOC
RCP
RDAR
RDA
RSI
19
22
20
21
TOP VIEW
6-2
lOs
TBMT
MR
Order Number MM5303N
See Package 24
absolute maximum ratings
Voltage at Any Pin
.Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
s:
s:U1
(Note 1)
Vss - 25V IV ss + O.3V*
o
-25°e to +70 e
-65°e to +150°C
W
o
W
0
300 e
*Outputs should not have more than Vss - 15V
dc electrical characteristics
T A within operating temperature range, V ss = 5V ±5%, Voo
PARAMETER
= OV, V GG
= -12V ±5% unless otherwise noted.
CONDITIONS
(Note 3)
MIN
TYP
MAX
UNITS
V ss -1.5
Vss+0.3
V
Voo
O.S
V
V IH
High Input Voltage Levels
V IL
Low Input Voltage Levels
V OH
High Output Voltage Levels
10H
= -'100,uA
VOL
Low Output Voltage Levels
10L
= 1.6 mA
0.4
V
IIH
High Level Input Current Levels
V IN
= Vss
10
,uA
IlL
Low Level Inp\1t Current Levels
V IN
= O.4V, Vss = 5.25V
1.6
mA
10L
Output Leakage Current Level
SWE
= ROE = V IH ,
V
2.4
-- --
-1
,uA
O~ V OUT ~5V
los
Output Short Circuit Current
V OUT
= OV, (Note 4)
25
mA
5
10
pF
10
20
pF
Level
C IN
Input Capacitance
All Inputs
COUT
(Note 2)
V IN
= V ss , f = 1 MHz
Output Capacitance
All Outputs
SWE
= ROE = V IH , f = 1 MHz
Iss
Power Supply Current
All Inputs at Vss
13
25
mA
IGG
Power Supply Current
All I nputs at V ss
6
15
mA
MAX
UNITS
ac electrical characteristics
at 25°e
PARAMETER
tpw
CONDITIONS
MIN
Clock Frequency
RCP, TCP
dc
Pulse Width
Clock
Master Reset
Control Strobe
Tx Data Strobe
Rx Data Available Reset
RCP, TCP
MR
CS
TDS
ROAR, (Note 5)
5
1
300
200
Coincidence Time
TYP
500
kHz
,us
,us
,us
ns
ns
TDS
CS
300
Input Set-Up Time
TD1-TDS
NPB, NSB, NOB, POE
0
0
ns
ns
tHO LO
Input Hold Time
TD1-TDS
NPB, NSB, NOB, POE.
300
0
ns
ns
tpdO
Output Propagation Delay to
Low State
ROE, SWE Enable to Outputs Low
500
ns
tpdl
Output Propagation Delay to
High State
ROE, SWE Enable to Outputs High
500
ns
tc
, tSET
ns
,us
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed .. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing_
Note 3: Positive true logic notation is used:
Logic "1" = most positive voltage level
Logic "0" = most negative voltage level
Note 4: Only one output should be shorted at a time_
Note 5: Refer to Receiver Timing diagram for detail.
6-3
GI
functional block diagrams
SWl' C>;-;----- 500n
Low Band Only
820
High Band Only
1000
Harmonic Distortion
mVp-p
mVp-p
-20
RL:::: 500n,
dB
No External Filtering
Tone Fn~quency Deviation
1.0
Operating Frequency
3.579545
Key-Down Debounce Time
7
Key-Up Debounce Time
4
, Power Dissipation
1·1.35
7.15
30
VDD - VSS = 6V,
%
MHz
ms
ms
mW
RL = 500n
Output Current Level
@
"MUTE"
VDD .- VSS = 3.0V
Logical" 1"
VOUT
"a"
VOUT
Logical
functional description
= VDD - 0.2V
= VSS + 0.5V
20
pA
2.0
mA
(Continued)
TABLE I. Interface Mode Control
CONTROL
o
XMIT
Open
o
INTERFACE MODE
Keypad
Idle
}BCD Signal
Send tones e.g. MM5393
6-12
functional description
(Continued)
TABLE II. Keypad Interface
(a). Functional Truth Table
COLUMN
ROW
HIGH BAND
LOW BAND
None
None
DC
DC
One
One
fL
fH
None
One
DC
fH
One
None
fL
DC
Two or more
None
DC
DC
Two or more
One
DC
fH
None
Two or more
DC
DC
One
Two or more
fL
DC
(b). Output Frequencies
INPUTS
DESIRED
ACTUAL
FREQUENCIES
FREQUENCY
fL (Hz)·
PERCENT
DEVIATION
(Hz)
fH (Hz)
R1
697
-
699.1
0.306
R2
770
-
766.2
-D.497
R3
852
-
847.4
-D.536
R4
941
-
948.0
0.741
C1
-
1209
1215.9
0.569
C2
-
1336
1331.7
-D.324
1477
1471.9
-D.35
1633
1645.0
C3
C4
0.736
TABLE III. Functional Truth Table for Signal Interface
XMIT
Cl
C2
Rl
R2
R3
R4
FREQUENCIES
GENERATED
fH (Hz)
fL (Hz)
0
X
X
X
X
X
X
DC
DC
1
Open
Open
0
0
0
0
941
1336
1
Open
Open
0
0
0
1
697
1209
1
Open
Open
0
0
1
0
697
1336
1
Open
Open
0
0
1
1
697
1477
1
Open
Open
0
1
0
0
770
1209
1
Open
Open
0
1
0
1
770
1336
1
Open
Open
0
1
1
0
770
1477
1
Open
Open
0
1
1
1
852
1209
1
Open
Open
1
0
0
0
852
1336
1
0
0
1
852
1477
fL
DC
DC
fH
DC
DC
1
Open
Open
1
0
Open
1
Open
0
1
0
0
Valid BCD Inputs
6-13
typical applications
Standard Telephone Keypad
Vee
Cl
C2
Cl
C4
Rl
R2
RL
TONE
OUTPUT
C,
Rl
FILTER
200
CONTROL
VSS
COLUMN
TERMINALS
Single Contact Keypad
RINGER-~
Cl
Vee
C2
Cl
C4
Rl
R2
"'--
Rl
MUTE
~
I
ROW
\
I..
-'"
J
TONE
OSC IN
c::J
' FILTER
OSC OUT
CTRL
VSS
COLUMN
6-14
connection diagram
Dual-In-Line Package
vss...2.
U
18
-VOO
17
OSC 2
IN'-
f- TONE
16
f- FILTER
NC..!
15
f-XMIT
OSC 4
·our-
14
f- CONTROL
5
MUTEC4.!
13
f-Rl
C3.2.
12
f-R2
Cl.!.
..!.!. R3
9
10
-R4
C2-
TOP VIEW
Order Number MM5395N
See Package 20
6-15
Communications/CB Radio Circuits
MM55104, MM55106, MM55114, MM55116 PLL frequency synthesizer
general description
The MM55104 and MM55106 devices contain phase
locked loop circuits useful for frequency synthesizer
applications in C.B. transceivers. The devices operate
off a single power supply and contain an oscillator,
a 2 10 or 211 divider chain, a binary input programmable
divider, and phase detector circuitry. The devices may
be used in double I.F. or single I.F. systems. The
MM55104, MM55114, MM55106 and MM55116, use a
10.24 MHz or 5.12 MHz quartz crystal to determine the
reference frequency. The MM55106 and MM55116 have
an output pin which provides a 5.12 MHz signal, which
may be tripled for use as a reference oscillator frequency
,in two crystal systems. Also, the MM55106 provides an
additional input to the programmable divider which
allows 29 - 1 division of the input frequency (F IN).
The inputs to the programmable divider are standard
binary signals. Selection of a channel is accomplished by
mechanical switches or by external electronic programming of the programmable divider.
frequency, and ¢VCO provides a low level voltage (sinks
current) when the VCO frequency is higher than the,
lock frequency. The ¢VCO output goes to a high impedance (TRI-STATE®) condition under lock conditions,
and the lock detector output LD goes to a high state
under lock conditions.
features
The rtNCO output provides a high level voltage (sources
current) when the VCO frequency is lower than the lock
•
Single power supply
•
•
Low power CMOS technology
Binary input channel select code
•
5 kHz or 10kHz output from oscillator divide
•
5.12 MHz output (MM55106 and MM55116 only)
•
•
On-chip oscillator
Pull-down resistors on programmable divider inputs
•
Low voltage operation-5V (MM55104, MM5510,6)
•
High voltage operation-BY (MM55114, MM55116)
block diagrams
OSC OUT
FRED SELECT
"1"= 10 kHz
"0"= 5 kHz
5
OSC
FRED SELECT
5.12 MHZ "I" = 10 kHz
OUT
"0"= 5 kHz
6
OSC OUT
¢VCO OUTPUT
6
oVCO OUTPUT
7
LOCK
7 DETECTOR
"1"lorlocked
"O"ID,funlocked
IN
FIN
LOCK
8 OETECTOR
"1"lorlocked
"0" lor unlocked
FIN
MM55104, MM55114
pin descriptions
MM55106, MM55116
truth table
Truth table for binary inputs to programmable divider.
PO-P8
FIN
OSCIN
OSC OUT
LD
¢VCO
FS '
5.12 MHz OUT
N
P8
P7
P6
P5
P4
P3
P2
P1
PO
1
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
0
511
1
1
1
1
1
1
1
1
1
Programmable divider inputs
Frequency input from VCO (mixed
down)
Oscillator amplifier input terminal
Oscillator amplifier output terminal
Lock detector
Output of phase detector f~r con'trol
of the'VeO
Frequency division select 10kHz or
5 kHz - "1" is 10 kHz; "0" is 5 kHz
OSC Frequency divided by 2 output
FOUT = FIN/N
1 = High voltage level, VOH
0= Low voltage level, VOL
X
= Don't care
6-16
absolute maximum ratings
Vee Max
MM55104, MM55106
MM55114, MM55116
Lead Temperature (Soldering, 10 seconds)
Vee + 0.3V to Gnd - 0.3V
Voltage at Any Pin
Operating Temperature Range
-30°C to +75°e
-40°C to +125°e
Storage Temperature Range
electrical characteristics
TA = 25°C
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage (Vee)
MM55104, MM55106
4.5
5.0
5.5
V
MM55114, MM55116
7.0
B.O
10.0
V
3
8
10
mA
16
mA
Supply Current (ICC)
Freq
@
Osc In = 10 MHz,
FIN = 2.5 MHz, All Other
I/O Pins Open, (Note 1)
@
MM55104, MM55106
Vee = 5V
MM55114, MM55116
Vee = BV
Logical "1" Input Voltage (VIN(l))
PO-PB, FS, FIN
(Vee-O.4V)
V
s:
s:
CJ1
CJ1
~
~
Logical "0" Input Voltage (VIN(O))
0')
PO-PB, FS, FIN
0.4
V
Logical "1" Output Voltage
5.12 MHz Out, LD
qNeO
10=0.5mA}
10 = OAmA
Osc Out
10 = 0.25mA
(Vee-0.5V )
V
Logical "0" Output Voltage
qNeO, 5.12 MHz Out, LD
10 = -O.5mA }
10 = -0.25mA
Osc Out
0.5
V
Logical "1" Input Current
FS (Pull-Up)
1.0
MM55104, MM55106} PO-PB
MM55114, MM55116 (Pull-Down)
Vee = 5V
5
20
50
Vee = 8V
10
40
100
1.0
pA
Vee = 5V
-10
-35
-100
pA
Vee = BV
-30
-120
-300
Logical "0" Input Current
. PO-P8 (Pull-Down)
MM55104, MM55106 }
MM55114, MM55116 FS (Pull-Up)
Toggle Frequency @ FIN
3
Oscillator Frequency @ Osc In
10.24
MHz
TRI-STATE Leakage @qNeO
1.0
connection diagrams
GND
PO
PI
(Dual-In-Line Packages, Top View)
P2
Pl
"6 "5 "4 "l "2
P4
111
P5
GND
P6
PO
PI
P2
Pl
P4
P5
P6
P7
~8 117 116 115 114 113 112 111 Ito
11019
,I'
Vcc
Order Number MM55104N or MM55114N
See Package 19
Y
fiN
jl
OSC
IN
.1
4
,1,5 .I.6
OSC 5,12
OUT MHz
OUT
fS
..e
oVCD
8
1
LD
9
1
P8
Order Number MM551 OGN or MM5511GN
See Package 20
6-17
pA
MHz
typical applications
INTRODUCTION TO FREQUENCY SYNTHESIS
problem; however, present technology limits the counting
speed of programmable dividers to something less than
5 MHz, ruling out the approach shown in Figure 1.
The components of. a frequency synthesizer are shown
in Figure 1. The voltage controlled oscillator produces
the desired output frequencies spaced fv Hz apart
according to the relation:
Two solutions to this problem are shown in Figure 2.
Frequency prescaling shown in Figure 2(a) reduces the
VCO frequency by M (a fixed number) to a frequency'
that can be divided by the programmable counter. The
reference frequency fr must also be reduced by M. In the
case of CB, if M = 10, fv = 26.965 MHz, the input to the
programmable divider will be 2.6965 MHz, and the
5 kHz reference frequency will be reduced to 500 Hz.
This poses problems in speed of response of the phase
locked loop.
The reference frequency, fr, must be equal to or less
than the (channel) spacing between the frequencies
being synthesized.
CHANNEL SELECT CODE
(OUTPUT) Iv
+-+------1
The second technique mixes the output frequency of
the VCO with a stable fixed frequency to obtain a
related reference frequency.
VCO
FIGURE 1. Basic Frequency Synthesizer
Although simple in concept, the circuit of Figure 1 has
certain difficulties. In CB, we are synthesizing the
following frequencies:
Ch 1
Ch 2
26.965
26.975
Ch 23
27.225
This technique has the advantage of allowing a 10kHz
reference frequency in the loop instead of 5 kHz.
Further complexity arises when one considers that the
synthesizer must also generate a local oscillator signal as
well as a transmitter input signal for the radio (Figure 3).
A system which provides these frequencies, as well as
the proper offset to allow the programmable divider to
operate within its limits is shown in the typical applications diagrams (Figure 4). The only departure from the
ideal situation shown in Figure 3 is that the first IF
frequency of 10.7 MHz must be changed to 10.695 MHz
(a change of 5 kHz).
Although the channel spacing is 10kHz, a reference
frequency of 5 kHz would be necessary due to the odd
5 kHz in the assigned channel. This in itself poses no
Iv
VCD
FI9URE 2(a). Frequency Prescaling
FIGURE 2(b). Frequency Offset
26.965
Y .-..
r-;;;'
~r;;;;J
~~
~
~
FIGURE 3. Signals Needed to Transmit and Receive Ch 1
6·18
s:
s:U1
typical applications (con't)
U1
.....
o
~
s:
s:U1
U1
.....
o
en
s:
s:U1
U1
.....
.....
~
11.80666 MHz
182Vco
'0,24 MHz
OUT
OUTPUT
8
LOCK
OETECTDR
"'" FOR
LOCKED
"0" FOR
UNLOCKED
GND
P' P2 P3 RX P4 P5 P6 PI P8
fTx
MM55108
fRE~UENCY
5,'2 MHz
OUT
SELECT
'0,24 MHz ","'0 kHz
OUT
"0" 5 kHz
FILTER
IN
FILTER
OUT
,WCD
OUTPUT
CRYSTAL 3
OSC IN
"
LOCK
OETECTOR
"'" FOR
LOCKEO
"0" FOR
UNLOCKEO
VCC
GND
PO P' P2 P3 RX P4 P5 P6 PI P8 P9
fTx
MM551,10
6-20
absolute maximum ratings
Voltage at Any Pin
VCC + 0.3V to Gnd - 0.3V
-30°C to +75°C
Operating Temperature Range
Storage Temperature
-40°C to +125°C
12V
Operating VCC
Lead Temperature (Soldering, 10 seconds)
300°C
electrical characteristics
T A = 25°C, VCC = 8V unless otherwise specified
PARAMETER
CONDITIONS
Supply Voltage (VCC)
Supply Current (I cel
MIN
TVP
4.5
Freq. at Osc.ln = 10.24 MHz
at fiN
= 2.5
4
MAX
UNITS
10
V
10
mA
MHz, All Other
I/O Pins Open
Logical "1" Input Voltage (VIN(l))
(VCC-o.4)
V
PO-P9, IS
Logical "0" Input Voltage (VIN(O))
0.4
V
PO-P9, IS
Logical "1" Output Voltage
10
= -0.5
mA
V
(VCC-o·5)
-
VCO, 10.24 MHz Out, 5.12 MHz Out,
Osc. Out, LD
Logical "0" Output Voltage
10
= 0.5
mA
0.5
V
VCO, 10.24 MHz Out, 5.12 MHz Out,
Osc. Out, LD
Logical "1" Input Current
Filter In (Pull-Up)
1
RX/TX (Pull-Up)
1
IlA
60
IlA
FS, PO-P9 (Pull-Down)
20
40
Il A
Logical "0" Input Current
Filter In (Pull-Up)
RS/TX (Pull-Up)
-60
FS, PO-P9 (Pull-Down)·
For ac Signal or
(VIN(l))
IlA
-180
IlA
MHz
1
Vp-p
V'
(VIN(O))
0.4
VOUT = Vec or Gnd
111
10.24
6-21
IlA
3
(VCC-o·4)
Oscillator Frf!quency at Osc. In
TRI-STATE Leakage at VCO
-1
1
Toggle Frequency at fiN
Input Signal at fiN (Maximum 3 MHz)
-120
V
MHz
Il A
o
..It)
connection diagrams
It)
Dual-In-Line P~ckage
Dual-I n-Line Package
:?!
:?!
GNO
Pl
P2
P3
OSC
IN
OSC
OUT
RX/Tx
P4
P5
P6
.VCO
LO
GNO
PO
Pl
P2
VCC
fiN
OSC
IN
OSC
OUT
P3
NC RxlTX P4
P5
P6
P7
pa
LO
P9
ex)
o
.It)
It)
:?!
:?!
5.12
10.24
MHz. MHz
pa
TOPVIEW
5.12 10.24
MHz MHz
FS
FIL
IN
FIL ¢VCO
OUT
TOPVIEW
Order Number MM55108N
See Package 20
Order Number MM5511 ON
See Package 22
pin descriptions
PO-P9
fIN
OSCIN
OSC OUT
LD
qNCO
FS
Programmable Divider Inputs
Frequency Input From VCO (Mixed down)
Oscillator Amplifier Input
Oscillator Amplifier Output
Lock Detector
Output of Phase Detector for Control of VCO
Frequency Division Select
"1" for 2 10 Division
"0" for 211. Division
5_12 MHz OUT
Buffered 5.12 MHz Output (Oscillator
Frequency -;. By 2)
10.24 MHz OUT
. Buffered 10.24 MHz Output (Oscillator
Frequency)
Filter Amplifier Input
Filter Amplifier Output
Receive/Transmit Input
"0" for Transmit Mode (-;. by (N+91))
FILTER IN I
FILTER OUT
RX/TX
typical applications
OPEN ~ RX
GNO ~ TX
2k
-1-
RXlTx , SWITCH
100pF
5pF
CHANNEL
SELECT
SWITCH
P4
13
14
P3
10k
MM5510B
15
P2
16
Pl
17
18
'--__-''IT
10pF
'--___-+-+ TX OUT
26.965-27.405 MHz
":"
lOOk
• VCC + av
0-+-----+---+--...---4--+--I--....-+-----t-----.....
L-------------+--------.....--:------+~~.~4M~~~~UT
'--______________-+
FIGURE 1. Single Crystal40-Channel Low Side Injection with MM55108 and LM1862
6-22
~I:~~~IXER
.
16.27 -16.71 MHz
typical applications
(Continued)
~
~
U1
5
BUffERED
10.24MH.
OUT
6
........U1
o
BUffERED
5.12MH.
OUT
OSCILLATOR DIVIDER
211
PROGRAMMAELE DIVIDER
2Ll
P8
PI
r6
P5
P4
RX
P3
fTX
18
SW
-1
GNO
10
11
12
13
14
15
16
17
VCC
SWOPEN ·RX \~
SW CLOSE' TX
CHANNEL
SELECT
SWITCH
182 < N < 270 where N = binary
number for programmable divider
FIGURE 2. MM55108 Single Crystal 40·Channel Low Side Injection
5
BUffERED
10.24MH.
OUT
6
BUffERED
5.12MH.
OUT
OSCILLATOR OIVIDER
211
PROGRAMMABLE DIVIDER
2Ll
PB
18
SW
SWOPEN
GND
PI
P6
P5
P4
Rx
fTx
10
11
12
13
14
P3
vcc
RX \~
SW CLOSE· Tx
-:1.
CHANNEl
SELECT
SWITCH
182 < N < 270 where N = binary
number for programmable divider
FIGURE 3. MM55108 Single Crystal 40·Channel High Side Injection
6·23
truth tables
co
o
Ln
Ln
TABLE I. Binary Inputs to Programmable Divider for MM55108
~
~
INPUTS
RX/TX
RX/TX
"1" OR "OPEN" "0" OR "CLOSED"
N
N
Channell
26
P6
25
P5
24
P4
23
P3
22
P2
Pl
0
21
1
92
0
0
0
0
0
0
0
93
0
0
0
0
0
0
0
1
4
95
0
0
0
0
0
0
1
0
182
273
0
1
0
1
1
0
1
1
270
361
1
0
0
0
0
1
1
1
510
601
1
1
1
1
1
1
1
1
Channel 40 ->
~
27
P7
2
->
1
28
P8
logical "1"
o ~ logical
"0"
TABLE II. Binary Inputs to Programmable Divider for MM55110
RX/Tx
RX/TX
"1" OR "OPEN" "0" OR "CLOSED"
N
N
I
Channell
->
Channel 40 ->
INPUTS
29
P9
28
P8
27
P7
26
P6
25
P5
P4
23
P3
24
22
P2
21
Pl
20
PO
1
92
0
0
0
0
0
0
0
0
0
X
2
93
0
0
0
0
0
0
0
0
1
0
3
94
0
0
0
0
0
0
0
0
1
1
182
273
0
0
1
0
1
1
0
1
1
0
270
361
0
1
0
0
0
0
1
1
·1
0
1023
1114
1
1
1
1
1
1
1
1
1
1
x
~
don't care
1
~
logical "1"
o = logical "0"
6-24
Watches
MM5829 LED watch circuit
general description
features
The MM5829 is a low threshold voltage, ion-implanted,
metal·gate CMOS integrated circuit that provides or controls
signals needed for a 3 1/2 digit LED watch. The
display format is 12 hours. The circuit time base is a
32768 Hz crystal controlled oscillator. This time base
frequency is successively divided to provide drive signals
for a multiplexed 7 s~gment LED display of either
HOURS-MINUTES or SECONDS upon demand. Outputs interface with currently. available standard bipolar
segment and digit driver integrated circuits. The device
operates from a single 2.4V to 5.0V supply. A STOP
MODE is provided such that an entire watch may be
placed in a powered down state with the oscillator
stopped when still connected to the battery. The
MM5829 is available in a 30-lead ceramic flat package or
as unpackaged die suitable for hybrid assembly.
•
all
32768 Hz crystal controlled operation
• i
•
•
r
Single 3V supply
Low power dissipation (151lW typ)
Seconds; minutes and hours operation
•
3 1/2 digit, 12 hour display format
•
Simple display/set controls
•
Power-down mode
•
Easy interface to standard bipolar IC's for display
drive
block diagram
chip pad layout
r
138MILS
I
OSET
o
DIGITS
OF
},,"
OSCOUT 0
DB
DE
20
40
10
MM5829
OA
132MILS
r
Voo 0
TIME
SEGMENTS
OG
1 Hz!
TEST
LAMP FRED TEST 4096 DSC IN
0
0
0
0
0
DC
Vss
DO
0
FIGURE 2.
connection diagram .
1.=======:=1
NC
NCC=====~
SET . - - - - - - ,
NC
NC~7?~~~~~~~~~NC
TIME
SEGMENTS
FIGURE 1.
DIGIT 3
SEGF
OIGIT 2
SEG A
0lGIT4
SEGB
OIGIT 1
SEG E
OSC OUT
SEGG
OSC IN
SEG C
NC
SEG 0
NC
NC
1 . -_ _- '
~======::J
LAMP
c::======::::J L':::======::::J
TDPVIEW
FIGURE 3.
7-2
4096Hz
TEST
1 HzlTEST
FREQ
s:
s:
absolute maximum ratings
Voltage at Any Pin
Operating Temperature Range
Storage Temperature Range
Dice
Packages
Voo '-'V ss
.
Lead Temperature (Soldering, 10 seconds)
(J'1
Vss-0.3V to Voo+0.3V
-5°C to + 70°C
CO
N
to
-25°C to +85°C
-55°C to +125°C
5V max
300°C
electrical .characteristics
T A within operating temperature range, Vss = GND, 2.4 ~ Voo ~ 4.0V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
= 25°C
Oscillator Start Voltage
TA
Input Voltage Level @'Time, Set.
Logical "1"
Logical "0"
Voo = 3.0V
MAX
UNITS
V
1/2 Voo
300 kU Pull-Down to Vss
Voo
V
V
Voo
Vss+0.25
V
V
Vss+0.25
V
V
Open
= 3.0V
Input Voltage Level @ Test Frequency
Logical "1"
Logical "0"
Voo
Input Voltage Level @ Lamp, Test
Logical "1"
Logical "0"
Voo = 3.0V
1 Mn Pull-Up to V DD
Voo-0.25
Vss
Open
Vss
Input Current @ Time and Set
VIN
= V oo , Sink Only,
Input Current @ Lamp and Test
VIN
= V ss , Source Only, Voo
Input Capacitance
f = 1.0 MHz, VIN = O.OV
All other:pads GND
Voo
= 3.0V
=
Output Voltage Level @ Segment Drivers
Logical "1"
Logical "0"
Voo = 2.4V, 'SOURCE :::: 10J.iA
Voo = 2.4V, ISINK :::: 300J1A
Output Voltage Level @ Digit Drivers
Logical "1"
Logical "0"
Voo
Voo
= 2.4V,
= 2.4V,
3.01/
'SOURCE :::: 840J.iA
ISINK :::: 20J.iA
Output Voltage Level @ 4096, 1 Hz
Logical "1"
Logical "0"
Voo = 3.0V
Supply Current (1 00 )
f = 32768 Hz, T A = 25°C
Voo = 3.0V, Unused Inputs Open,
Outputs Open
Supply Current
Stop Mode, T A = 25°C, Voo = 3.0V,
Unused Inputs Open, Outputs Open
(100)
TYP
2.7
Voo-0.2
Vss
V oo -l.3
Vss
Voo-0.2
ISOURCE :::: 10J1A
ISINK :::: 10J1A
Vss
-
5
10
pA
3
pA
5
pF
Voo
Vss+O.5
V.
V
V
Voo
Vss+0.2
V
V
Voo
Vss+0_2
V
V
10
pA
1
pA
functional description
A block diagram of the MM5829 digital watch chip 'is
shown in Figure 1. A chip pad layout is shown in Figure 2 and a package connection diagram in Figure 3.
quartz crystal, and (c) provide added phase shift for
good start-up and low voltage circuit performance.
Capacitors eland C2 in series prOvide the parallel load
capacitance required for precise tuning of the q~artz
crystal.
Time Base
The precision time base of the watch is provided by the
interconnection of a 3-2768 Hz quartz crystal and the
RC network shown in Figure 4 together with the CMOS
inverter/amplifier provided between the oscillator in and
oscillator out terminals. Resistor R 1 is necessary to bias
the inverter for class A amplifier operation. Resistor R 2
is required in order to (a) reduce the voltage sensitivity
of the network, (b) limit the power dissipation in the
The network shown provides >100 ppm tuning range
when used with standard X-Y flexure crystals trimmed
for C L = 12 pF. Tuning to better than ±2 ppm is easily
obtainable.
The 4096 Hz output or 1 Hz output can be used to
monitor the oscillator frequency during initial tuning
without disturbing the network itself.
7-3
functional description (con't)
Time Display
The HOURS-MINUTES/SECONDS Display feature is
controlled by a normally open switch connected to the
Time input as shown in Figure 6. A logic "1" applied
to the Time input will cause HOURS-MINUTES to be
displayed for not less than 1.5 seconds or more than 2.0
seconds. The hours digits can display values 1-12 while
the minutes digits can c\.isplay values 00-59. All zero
values are displayed for minutes and leading zero values
of hours are blanked. The character display font is
shown in Figure 5. Holding a logic "1" on the Time
input after the time-out of HOURS-MINUTES will cause
SECONDS to be displayed in digit positions 3 and 4
. ur\til' the Time input is opened. SECONDS will blink
while displayed. Each value is visible for 0.5 seconds and
blanked for 0.5 seconds. The SECONDS digits can display values 00-59. All zero values are displayed.
HOURS at a 1 Hz rate. The Seconds and Minutes
counters continue normal counting during this
condition.
SECONDS: With a logic "1" on the Time input, the
application of a logic "1" to the Set input will immediately reset the Seconds counter to 00 and allow a normal
seconds count from there.
MINUTES: A logic "1" applied to both the Time and
Set inputs will allow HOURS-MINUTES to be displayed
and will advance the MINUTES at a 1 Hz ra'te. A transition from 59 to 00 will not advance the Hours counter
in this condition.
CONTACT BOUNCE: Debounce circuitry is provided
on the Time and Set inputs to' remove any logic
uncertainty upon either closure or release of switches
providing switch bounce settles within 20 ms.
Display Multiplexing
Outputs from each counter are time·division multiplexed
to provide digit·sequential access to the time data. Thus,
instead of requiring 28 leads to interconnect a four digit
(7 segments/digit) watch, only 11 output leads are required. Figure 6 shows the interconnection of an LED
watch system. The four digit outputs of the MM5829 are
designed to interface with the bipolar DM8650 digit
driver chip. The seven segment outp~ts are designed to
interface with the bipolar DM8651 segment driver chip.
The four digits of the LED Display are mUltiplexed with
. a 25% duty cycle, 1024 Hz signal during Display. The
digit drivers are turned off for 1511s during change of
digits to allow the seven segments to change without
"ghosting" of the Display. When the MM5829, DM8650,
and DM8651 are used as shown in the typical application of Figure 6 the peak segment on currents are
typically 9 mAo The 0101 LED Display gives excellent
brightness under these drive conditions.
Oscillator Stop
The oscillator can be stopped in order to conserve
battery life during shipment of the watch. The oscillator
will stop if a logic "1" is momentarily applied to the
Time input and while HOURS-MINUTES are displayed
a logic "1" is momentarily applied to the Set input.
The Display is inactive during this mode. The oscillator
will start again when a logic "1" is applied to the Set
input .
Test Points
Four pins are provided for test purposes. A 4096 Hz
symmetrical signal is brought out for oscillator tuning.
The pin 1 Hz/Test Frequency is an input/output under
control of Test. With Test open, a 1 Hz output will
appear on the 1 Hz/Test Frequency pin. If Test is connected to a logic "0," the 1 Hz/Test Frequency becomes
an input and any .frequency connected to it will be
divided by the Seconds counter in place of the normal
1 Hz signal. This feature is provided to allow high speed
functional testing of the watch system. If lamp is connected to a logic "0," all segments will be forced to an
on condition under control of the normal 25% duty
cycle of the digit drivers. An internal pull-up resistor will
normally hold the lamp input to logic "1." ,
Time Setting
A normally open switch connected to the Set input is
used in conjunction with the Time switch to set hours,
minutes, and synchronize seconds.
HOURS: A logic "1 ,; applied to the Set input will cause
HOURS-MINUTES to be displayed and will advance
CMOS INVERTER
OSC IN
C2
5-36pF
Cl
45 pF
Voo OR Vss
Dc=JD
D c=JD c=JD Dc=JD
Dc=JD
0 -D= =0 ' V
c=JD ilc=JD ilc=JD
ilc=J il
::0 0=0
0 D=O ~D
ZERO
ONE
TWO
THREE
FOUR
FIVE
SIX
SEVEN
EIGHT
NINE
FIGURE 4. Crystal Oscillator Network
FIGURE 5. Character Display Foilt
7-4
functional description (con't)
r-~-I:D:~"-"'"
_~32168Hl_"-'
7r- CRYSTAL T
Vss
1
o~ Voo
OSC OUT
OSC IN
Voo -
Voo
MMS829
(CMOS)
Vss -
-=-
UV
-
1.5V
""'~:~
SET
f-o
T
""
Vss
Vss -
DIGIT DRIVER
DMB650
(BIPOLAR)
SEGMENT ORiVER
0'-18651
(BIPOLAR)
-Vss
l+A
l-..+
B
0101
LED
DISPLAY
~C
'-----I~ID
'-----.IE
L..-----.IF
G
FIGURE 6. Typical Application
7·5
.-
o
00
00
LO
~ ..
~
~
o
Watches
MM5860, MM58601, MM5880, MM58801
two time zone LED watch circuits
general description
features
00
00
LO
~
~
The MM5860/MM5880 is a low threshold voltage, ionimplanted, metal-gate CMOS integrated circuit that
provides or controls all signals needed for a 4-digit
LED watch. The display format is either 12 or 24
hours. The circuit time base is a 32,768 Hz crystal controlled oscillator. This time base is successively divided
to provide drive signals for a multiplexed 7-segment LED
display of Date·Month, Local Hours-Minutes, Zone
Hours·Minutes, or Seconds upon demand for the
MM5860 version. The MM5880 version will vary only in
the date display by displaying Month-Date. The
MM58X01 versions will blink the Month during the
date display. Outputs interface with currently available
standard bipolar segment and digit driver integrated
circuits. The device operates from a single 2.4-4.0V
supply. All versions are available as unpackaged die
suitable for hybrid assembly or in 40·lead dual·in-line
packages for evaluation purposes.
.o
c.o
00
LO
~
~
•
32,768 Hz crystal controlled operation
•
Single 3V supply
•
Low power dissipation (15J1W typical)
•
Seconds, Minutes, Local and Zone Hours, Date, and
Month display
•
4 year calendar
•
4·digit .. 12/24 hour display format
•
AM indication in 12·hour format
•
Simple display/set controls
•
Auto return from Set and Display mode
•
Easy interface to standard. bipolar IC's for display
drive
•
Display brightness control
block and connection diagrams
4 Hz/TEST FREQ
DSCDUT=t>l
DSC IN
........
~DIM
--,-'
LAMP
SET/DISP
CYCLE
ZDNE
01]
0-_.------1-....1
02
o--t----+r~---,
··DIGITS
4 Hz(nSTFREO
03
0----11----.1
04
o---ir---+L--.-_..l
CDLDN
NC
Nt
NC
Nt
SEGMENT 0
OSCOUT
SEGMENTC
0lGIT2
SEGMENTB
DIGITl
SEGMENT A
0lGIT4
SEGMENTF
27
VDO
NC
NC
I+--f--.....- - + - - - - - + - - - - ( ) 2 4 HR
NC
24HR
DIM
COLON
23
22
19
20
FIGURE 2.
SEGMENTS
FIGURE 1.
7·6
CYCLE
ZONE
TOPVIEW
o
SET/DISPLAY
26
NC
absolute maximum ratings
VSS - O.3V to VOO + O.3V
o
-5°C to +70 C
-25°C to +85°C
5V max
VOO - VSS
300°C
Lead Temperature (Soldering, 10 seconds)
Voltage at Any Pin
Operating Temperature Range
Storage Temperature Range
electrical characteristics
TA within operating temperature range, VSS = Gnd, 2.4V'::; Voo'::; 4V, unless otherwise noted.
CONDITIONS
PARAMETER
MIN
Oscillator Start Voltage
T A'" 25" C, Circuit of Figure 4
Input Voltage Levels at Cycle,
VDD = 3V
TYP
MAX
2.7
UNITS
V
Logical "1"
1/2 VDD
300k.Q Internal Pull-Down to VSS
VDD
V
Open
o
24 Hr.
~
Logical "1"
Logical "0"
Logical "1"
VDD-0.25
VDD
V
VSS
VSS+0.25
V
VSS+0.25
V
VSS+0.3
V
VDD-l.l
V
VDD = 3V
1 M.Q Internal Pull-Up to VDD
Logical "0"
Open
VSS
Input Voltage Levels at Dim
Display Duty Cycle = 21.875%
5 M.Q Pull-Down to VSS
VSS+0.9
Display Duty Cycle = 3.125%
VDD-0.5
Input Current at Cycle, Set/Display
VIN = VDD, Sink Only,
and Zone
VDD = 3V
Input Current at Lamp and Test
VIN = VSS, Source Only,
VDD
or
Open
Display Duty Cycle = 9.125%
Input Current of Dim
V
0.2
10
I1A
0.2
5
I1A
0.1
2
I1A
5
pF
= 3V
VIN = VDD, Sink Only,
VDD = 3V
Input Capacitance
f=lMHz,VIN=OV,
All Other Pads Gnd
Output Current Levels at Segment Drivers
= VDD
Logical "1," Source
VDD = 2.4V, VOUT
10
30
I1A
Logical "0," Sink
VDD = 2.4V, VOUT = VSS + 0.5V
300
600
I1A
Logical "1," Source
VDD = 2.4V, VOUT = VDD - 1.3V
840
1500
I1A
Logical "0," Sink
VDD = 2.4V, VOUT = VSS + 0.2V
10
30
I1A
- 0.2V
Output Current Levels at Digit Drivers
Output Current Levels at 4 Hz/Test Freq,
VDD = 3V
4096 Hz
Logical "1," Source
VOUT = VDD - 0.2V
10
I1A
Logical "0," Sink
VOUT = VSS + 0.2V
10
I1A
VDD = 2.4V, VOUT = lV
0.8
mA
Output Current Levels at Colon
Logical "0," Sink
Supply Current (IDD)
f = 32,768 Hz, T A = 25°C,
5
10
I1A
0.05
1
I1A
VDD = 3V, Unused Inputs Open,
Outputs Open
Supply Current (IDD)
~
~
CJ1
CO
CO
Input Voltage Levels at 4 HzITest Freq,
Input Voltage Levels at Lamp, Test
CJ1
CO
CO
o
Set/Display and Zone
Logical "0"
~
~
Oscillator Stopped, T A = 25°C,
VDD = 3V, Unused Inputs Open,
Outputs Open
I
7-7
functional description
o
to allow the segment decoding circuitry adequate time
to switch to the next digit's information. This eliminates
the possibility of "ghosting" information between digits.
When the MM5860/MM5880, DS8658 and DS8659 are
used in a typical application as shown in Figure 6 the
peak segment "ON" currents are typically 11 mAo
The NSC0101 LED display gives excellent brightness
under these drive conditions.
Unless otherwise specified, all references to the
MM58XO will also refer to the MM58X01. A block
diagram of the MM5860/MM5880 is shown in Figure 1.
The' connection diagram is shown in Figure 2 and the
chip pad layout in Figure 3.
CO
CO
04D96Hz
Lt)
TD'I
OOSCOUT
2
2
0
4 HllTEST
FRED
o
0
TEST
VssO
LAMP
00
co
OOSCIN
o
ED
SEGMENTS
o
GO
159MILS
1
BO
OIGITS
AD
01
FO
03
SET/DISPLAY 0
04
24 HR
OVODO
o
I•
to
co
Lt)
2
2
DIM
0
COLON
0
ZONE
0
CYCLE
0
·1
lBBMllS
d
FIGURE 3. Pad Layout
FIGURE 5. Character Display Font
Time Base: The precision time base of the watch is provided by connecting a crystal-controlled RC network to
the on-chip CMOS inverter/amplifier as shown in Figure
4. For proper operation, the network should be tuned
to 32,768 Hz. Resistor R 1 is used to bias the on-ch ip
inverter for class A amplifier operation. Resistor R2 is
used to (a) reduce the voltage sensitivity of the network;
(b) limit the power dissipation in the quartz crystal; and
(c) provide added phase shift for good start-up and low
voltage circuit performance. Capacitors Cl and C2 in
series provide the parallel load capacitance required for
precise tuning of the quartz crystal. The network shown
in Figure 4 provides greater than 100 ppm tuning range
when used with standard X-Y flexure quartz crystals
trimmed for CL = 12 pF. Tuning to better than 2 ppm
is easily obtainable.
DISPLAY CONTROL
The Time and Date display sequence is controlled by a
normally open switch connected to the Set/Display
input. With the display off, depressing the Set/Display
switch will activate the Local Hour: Minute display. This
display will remain on for 1.25 seconds ±0.125 seconds.
If the switch is still held in at the end of this time out,
Seconds will be displayed, blinking on for 0.25 seconds
and off for 0.75 seconds, until the SetIDisplay switch is
released. If, during the Hour:Minute display, the Set/
Display switch is released and depressed a second time
the date will be displayed as Date Month in the MM5860
version and as Month Date in the MM5880 version.
The Month will blink on for 0.25 seconds and off for
0.75 seconds in the MM58601 and the MM58801
versions and not blink in the MM5860 and the MM5880
versions. The display' will remain on for 1.25 seconds
and turn off automatically if the Set Display switch has
been released. Holding the Set/ Display switch in past
the- display time out will maintain the display until
the Set/Display switch is released. Zone Hour:Minute
can be displayed by depressing the Zone switch. This
display will also remain on for 1.25 seconds ±0.125
seconds. Holding the Zone switch depressed beyond'
this period will cause Seconds to be displayed until
the switch is released. The date information can not
be displayed using the Zone switch. Leading zeros are
blanked on the Month, Date and Hour displays.
TO COUNTERS
VSS
FIGURE 4. Oscillator RC Network
The 4096 Hz output or the 4 Hz output can be used to
monitor the oscillator frequency during initial tuning
without disturbing the network itself.
.
TIME SETTING
Display Multiplexing: The counter data selected to be
displayed is 'time-division multiplexed to provide digitsequential presentation to the LED display. This reduces
the number of outputs required to drive the 4-digit
display to 11 (7 segment drivers and four digit drivers).
The display font is shown in Figure 5. Figure- 6 is a
schematic diagram of a typical LED watch using the
MM5860/MM5880 watch chip. The digit outputs of the
MM5860/MM5880 are designed to interface with the
bipolar DS8658 digit driver chip and the segment driver
outputs will interface with the bipolar DS8659 segment
driver chip. The four digits of the LED display are
multiplexed with a 25% duty cycle, 1024 Hz signal
during the display period. The digit drivers are disabled for 32ps at the beginning of each digit enable time
The setting sequence is controlled by a normally open
switch connected to the Cycle input. Depressing the
Cycle switch will advance the watch to the next set
mode.
Set Hour Mode: With the watch in normal Run mode
and the display off, depressing the Cycle switch will
advance the watch to the Set Local Hour mode. In this
mode local hours will be displayed in digit positions 1
and 2 followed by the colon. The AM dot will be on
during AM time display. Depressing the Set/Display
switch will advance the Local Hour counter at a 2 Hz
rate. Depressing the Zone switch while in the Set Local,
Hour mode will cause zone hours information to replace
the local hours information in digit positions 1 and 2.
7-8
s
s
(J1
CO
0)
o
DMB658
VSS
s
s
(J1
CO
CO
, NSC
o
101
LED
s
s
(J1
CO
CO
o
(1) Anti-resonant quartz crystal, CL = 12 pF
FIGURE 6_ System Schematic
The colon and the AM dot will still be presented as in
the Local Hours display. The Zone Hour counter can
now be advanced at a 2 Hz rate by depressing the Set/
Display switch.
If none of the switches are depressed for 5.25 seconds
±0.125 seconds consecutively while in the Set Date
mode, the watch will automatically return to the Run
mode if the Minutes Counter was not set or will jump to
the Hold mode if the Minutes Counter was set. Depressing the Cycle switch while in the Set Date mode will
advance the watch to the Run mode if the Minutes
Counter was not set or will advance it to the Hold mode
if the Minutes Counter was set for the MM5880 version.
Depressing the Cycle switch while in the Set Date mode
of the MM5860 version will advance the watch to the
Set Month mode.
In either of the above Set Hour modes if no switches are
depressed for 5.25 seconds ±0.125 seconds consecutively, 'the watch will automatically return to the Run
mode. Depressing the Cycle switch while in the Set
Zone Hour mode will return the watch to the Run
mode~ Depressing it while in the Set Local Hour mode
will place the watch in the Set Minutes mode.
Set Month Mode: The Set Month mode will display the
month in digit positions 3 and 4 in the MM5860 ver~ion,
or in digit positions 1 and 2 in the MM5880 version,
with no colon displayed. Depressing the Set/Display
switch while in the Set Month mode will advance the
Month Counter at a 2 Hz rate.
Set Minutes Mode: The Set Minutes mode will display
minutes in digit positions 3 and 4 preceded by the colon.
Depressing the Set/D isplay switch while still holding
the Cycle switch in will enable the Hold flag but will not
allow advancement of the Minutes Counter. Depressing
the Set/Display switch after the Cycle switch has been
released will do the following:
If none of the switches are depressed for 5.25 seconds
±0.125 seconds consecutively while in the Set Month
mode, the watch will automatically return to the Run
mode if the Minutes Counter was not set or will jump
to the Hold mode if the Minutes Counter was set.
Depr~ssing the Cycle switch while in the Set Month
mode will advance the watch to the Run mode if the
Minutes Counter was not set or will advance it to the
Hold mode if the Minutes Counter was set for the
MM5860 version. Depressing the Cycle switch in the Set
Month mode of the MM5880 version will advance the
watch to the Set Date mode.
a. Reset and hold the Seconds Counter
b. Enable the Hold flag, and
c. Advance the Minutes Counter at a 2 Hz rate
If none of the switches are depressed for 5.25 seconds
±0.125 seconds consecutively while in the Set Minutes
mode, the watch will automatically return to the Run
Mode if minutes have not been set or will jump to the
Hold mode if minutes have been set. Depressing the
Cycle switch while in the Set Minutes mode will advance
the watch to the Set Date mode for the MM5860 version
or the Set Month mode for the MM5880 versio'n.
Hold Mode: In the Hold mode the Seconds Counter is
held at 00. Local Hour:Minute will blink on for 0.25
seconds and off for 0.75 seconds. Depressing the Cycle
switch while in the Hold mode will put the watch back
into the' Set Hour mode and then the counters can be
set as described previously. With the Hold mode still
activated, the watch will return to the Hold mode only.
Depressing the Set/Display switch while in the Hold
Set Date, Mode: The Set Date mode will display the Day
of Month in digit positions 1 and 2 in the MM5860
version, or in digit positions 3 and 4 in the MM5880
version, with no colon displayed. Depressing the Set/
Display switch while in the Set Date mode will advance
the Date Counter at a 2 Hz rate.
7-9
'o
CO
CO
10
mode will place the watch into the display Local Hour:
Minute mode ,and allow the Seconds Counter to begin
normal operation.
o
There is no roll·over of the next higher counter while a
counter is being set. For example, while the Minutes
Counter is set from 59 to 00 neither the Local Hour nor
the Zone Hour Counter will be advanced.
~
~
CO
CO
10
~
~
o
CD
CO
10
~
~
o
CD
CO
10
~
~
by the logical state of the "24 Hr" input. If the "24 Hr"
input is a logical "1" the watch will operate in the 24
hour mode. 'When the" 24 Hr" input is a logical "0"
the watch operates in 12 hour mode.
DIM INPUT
The Dim input is a three level input used to control
the display intensity of the watch. This input has a pull·
down to VSS to hold it normally at a logical "0."
Figure '7 isa state diagram showing the display and set
functions for both the MM5860 and the MM5880.
COLON OUTPUT
In this condition the display will normally be at maximum intensity. With the Dim input at 1/2 VDD' the display will be at approximately 1/2 of full intensity.
Placing the input at VDD will reduce the display intensity to approximately 1/8 of fuJI intensity. Figure 8
shows the switching threshold ranges for the three level
DIM input.
This output provides direct drive of the colon in the
LED display unit. Colon will sink current when activated. The colon output will be activated during the
display of either one of the hour ~ounters or the minute
counter or both.
CONTACT BOUNCE
Debounce circuitry is provided on the "Set/Display"
and "Cycle" inputs to remove any logic uncertainty
upon either closure or release of switches provided
switch bounce settles within 100 ms.
TEST POINTS
Four pads are provided for test purposes.
12/24 HOUR OPTION
4096 Hz: This pad outputs a 4096 Hz signal that can be
used for oscillatortuning.
12/24 hour mode operation of the watch is controlled
-
-
-
AUTOMATIC TIME OUT
CONTROLLED ROUTES
- - U S E R CONTROLLEO ROUTES
FIGURE 7. Control State Diagram MM5860 (MM58801
DISPLAY TIME/DIGIT
VIN = VOO
3.125%
VIN = VOO - O.5V
Threshold Region
VIN= VOO -1.1V
9.125%
VIN = VSS + O.9V
Threshold Region
VIN'" VSS + O.3V
21.875%
DISPLA Y CONDITION
Low Ambient Light Levels
Moderate Ambient Light Levels
High Ambient Light Levels
VIN = VSS
FIGURE 8. Counter Voltage Levels at Dim Input
7-10
TEST POINTS (CON'T)
4 Hz/Test Freq: This is an input/output pad under the
control of the "Test" input. When "Test" is at a logical
"0," the "4 Hz/Test Freq" pad becomes an input and
any frequency connected to it will replace the normal
internal 4 Hz signal. This feature is provided to allow
high speed functional testing of the watch system.
When "test" is open or at a logical ",", a 4 Hz output
will appear on the "4 Hz/Test Freq" pad.
Changing the Test input from a logical "'" to a logical
"0" will generate a reset pulse which will Set the internal
counters to , PM on January the first. The watch is now
in a known state for testing purposes.
Lamp: When the "Lamp" input is at a logical "0," all
segments of the display will be forced to an "ON"
condition under control of the normal 25% duty cycle
of the digit drivers. An internal pull-up resistor will
normally hold the "Lamp" input at a logical "'."
Testi This pad is used as an input to coritrol "4 Hz/
Test Freq." An internal pull-up resistor will normally
hold "Test" at a logical ."1."
~
~
CJ1
(X)
(X)
o
7-1'
Watches
MM5879, MM5889, MM5899 RC circuits
general description
absolute maximum ratings
The MM5879, MM5889, MM5899 are RC circuits
which may be used in watch' modules and other similar
applications. They are available in die form. All die
are pad·for-pad interchangeable, offering a range of
capacitance and resistance values.
Voltage at Any Pad
Operating Temperature
Storage Temperature
Vss + O.3V to VSS -20V
-5°C to +70°C
-65°C to +150°C
schematic diagram
RI
PART NUMBER
R2
R2
R1
MIN
MAX
MIN
MAX
CAP (Note 1)
MIN
MAX
MM5879
125k
235k
15M
30M
9 pF
13 pF
MM5889
250k
470k
15M
30M
45 pF
55 pF
MM5889AB
250k
470k
15M
30M
24 pF
36 pF
MM5899
250k
470k
15M
30M
14 pF
20 pF
Note 1: Capacitances ar~ measured' periodically only. Capacitance measured from
VSS to common.
chip pad layout
Vss
Vss
FIGURE 1.
7-12
Watches
MM5885, MM5886 direct drive LED watch
general description
The MM5885, MM5886 is a low threshold voltage,
ion-implanted, metal-gate. CMOS integrated circuit
that provides or controls all signals needed for a 4-digit
LED watch. The display format is 12 hours. The circuit
time base is a 32,768 Hz crystal controlled oscillator.
This time base frequency is successively divided to
provide drive signals for a multiplexed g-segment, alphanumeric LED display of DAY-DATE,HOURS-MINUTES
or SECONDS upon demand. A Month counter is
provided to control the count sequence of the Date
counter. The MM5885 uses one button to display while
the MM5886 uses two buttons for display purposes.
Outputs interface directly with an alphanumeric LE D
display. The device operates from a single 2.4V to 4.0V
supply. Both the MM5885 and MM5886 are available
as unpackaged die suitable for hybrid assembly or in
a 40-lead dual-in-I ine package for evaluation purposes.
• 32,768 Hz crystal controlled operation
•
Single 3V supply
•
Low power dissipation (15pW typ)
• Seconds, Minutes, Hours, Day-of-Week, Date and
Month operation
• 4 year calendar
• 4-digit, 12 hour display format
•
Simple display/set controls
•
Inertial switch input
• Alphanumeric display
•
Direct drive outputs
•
Display brightness control
•
AM/PM indication during set hours
features
•
Month indication during set month
•
• Test features
No external parts except the battery, LEDs and
crystal
• Single button display control (MM5885)
block diagram
4096Hz
0---......;......;--------.
CAP~
r - - - - - / - - O DIM
SET/DISP
CYCLE
DAY/DATE
HRIMIN
o>----......,r...!..--...!..-,
0>-----.1
0----.1
O>----......L_---.__-1
SEGMENTS
FIGURE 1.
7-13
absolute maximum ratings
Voltage at Any Pin
Operating Temperature Range
Storage Temperature Range
Voo - Vss
Lead Temperature (Soldering, 10 seconds)
Vss -0.3V to Voo + 0.3V
-5°C to +70°C
-25°C to +85°C
5V max
300°C
electrical characteristics
T A within operating temperature range, Vss
= GND, 2.4 ~ Voo
PARAMETER
~
4.0V, unless otherwise noted.
CONDITIONS
Oscillator Start Voltage
MIN
T A = 25°C
TYP
MAX
2.7
UNITS
V
Input Volt'ageLevels at Cycle,
Set/Display, Day/Date, Hour/Min
Logical "1"
300 kn Internal Pull·Down
1/2 Voo
Voo
V
Voo
V
to Vss
Logical "0"
Open
Input Voltage Levels at
4 Hz/Test Freq.
Logical" 1"
Voo-0.25
Logical "0"
Vss
Vss+0.25
V
Vss+0.25
V
Input Voltage .Levels at Lamp, Test
Logical" 1"
100 kn Internal Pull·Up
Open
to Voo
Logical "0"
Vss
Input,Voltage Levels at Dim,
5 Mn Pull-Down to Vss
Display Duty Cycle = 21_875%
Open
Vss+0.3
V
Display Duty Cycle = 9.125%
Vss+0.9
V oP -l.l
V
Display Duty Cycle = 3.125%
V oo -0.5
Voo
Input Current at Cycle, Set/Display,
Voo = 3.0V, V 1N = V oo ,
Day/Date, Hour/Min
Sink Only
Input Current at Lamp, Test
Voo = 3.0V, V 1N = V ss ,
V
30
50
p.A
30
50
p.A
5
pF
Source Only
I nput Capacitance
f=lMHz,V 1N =OV,
AllOther Pads GND
Output Current Levels at
Voo =2.7V
Segment Drivers
"ON" Source
V OUT = V 00
"OFF" Source
V OUT = Voo -l.lV .
Output Current Levels at
-
0.5V
7
10
15
mA
50
p.A
2
'mA
1
p.A
Voo = 2.7V
Digit Drivers
"ON" Sink
V OUT = V~s + 0.6V
"OFF" Sink
V OUT = 2.0V, All Digit Drivers Tied
50
70
in Parallel
Output Curr.ent Levels at
4 Hz/Test Freq., 4096 Hz
Logical "1" Source
V OUT = Voo -0.2V
10
p.A
Logical "0" Sink
V OUT = Vss + 0.2V
10
p.A
Operating Supply Current (1 00 )
f = 32,768 Hz, T./>. = 25°C,
5
10
p.A
0.05
1
p.A
Voo = 3V, Unused Inputs Open,
Outputs Open
Quiescent Supply Current
(100)
Osc In @Gnd, Voo
TA
= 25°C, Other
= 3V,
Inputs and
Outputs Open
7-14
functional description
A block diagram of the MM5885/MM5886 direct drive
digital watch is shown in Figure 1. The chip pad layout
is shown in Figure 2 and a package connection diagram
in Figure 3.
Display Control: The "Time" and "Date" display
sequence is controlled by normally open switches
connected to SET/DISPLAY, DAY/DATE (MM5886),
and HOUR/MINUTE (inertial switch) inputs. With the
display "OFF," depressing the SET/DISPLAY switch
will activate the HOUR·MINUTE display. This display
will remain "ON" for 1.25 seconds ±0.125 seconds.
If the switch is still held in at the end of this time out,
SECONDS will be displayed blinking "ON" for 0.25
seconds and "OFF" for 0.75 seconds until the SET/
DISPLAY switch is released. If, during the HOUR·
MINUTE display, the SET/DISPLAY switch is released
and depressed a second time, the date will be displayed
as DAY·DATE in the MM5885. The DAY· DATE display
will remain "ON" for 1.25 seconds ±0.125 seconds
and turn "OFF" automatically if the SET/DISPLAY
switch has been released. Holding the SET/DISPLAY
switch past the display time out will maintain the
·DAY·DATE display until the SET/DISPLAY switch
is released. In the MM5886, depressing the SET/
DISPLAY a second time has no effect. To display
DAY· DATE information in the MM5886, depress the
DAY/DATE switch. The DAY·DATE display will remain
"ON" for 1.25 seconds ±0.125 seconds. If the switch
is still held in at the end of this time out, the display
will remain until the DAY/DATE switch is released.
"Time" may also be displayed in both the MM5885 and
Time Base: The precIsion time base of the watch is
provided by the 32,768 Hz crystal controlled oscillator,
which consists of the quartz crystal, the CMOS inverter/
amplifier and the RC network shown in Figure 4.
Resistor R 1 is necessary to bias the inverter for class A
amplifier operation. Resistor R2 is required in order to
(a) reduce the voltage sensitivity of the network; (b)limit
the power dissipation in the quartz crystal; and (c) pro'
vide added phase shift for good start·up and low voltage
circuit performance. Capacitors C1 and Ceff in series
provide the parallel load capacitance required for precise
tuning of the quartz crystal. The network shown in
Figure 4 provides greater than 100 ppm tuning range
when used with standard X· Y flexure quartz crystal
trimmed for C L = 12 pF. Tuning to better than 2 ppm
is easily obtainable.
Cap: This pin is used with Oscillator Out to add more
capacitance to the oscillator RC network shown in
Figure 4.
159
15.5
0
05.5
153.51
I
39
DIGIT 2
13V
3B
NC
31.1
31
NC
NC
41.0
116.B
4.5 X 5.0
51.2
101.4
B5.9
161
MILS
40
SEGMENT I
DIG 2
(HII
=24
MM5885.MM58B6
(ALL PADS ARE 5.0 X 5.0 MINIMUM)
BO.1
61.1
4.5 SQUARE, TYP
NC
NC
NC
DIGIT 1
SEGMENT 0
vss
SEGMENT G
DIGIT 3
voo
DIGIT 4
SEGMENT B
4096 Hz
SEGMENT F
CAP
SEGMENT H
SEGMENT A
NC
NC
OSC IN
NC
LAMP
131.1
=16
OSC =15 =14=13
IN DIM 4 Hz TEST
=12 (NC)
HR/MIN
SET/OISPLAY
4 HzITEST
.B(NC)
LAMP
CYCLE
TEST
OAY/DATE (MM5BB6)
HR/MIN
=10
=9
(MODE) (DISPLAY)
CYCLE
SET
NC
NC
DIM
3B.l
=11 (NCI
DAY/DATE
SEGMENT C
NC
NC
DSC OUT
99.2
101.9-
SEGMENT E
15.2
TOP VIEW
155.5
161- ~-r-+~~r---------r---~--+---+---+------J--O
FIGURE 3. Connection Diagram
1
0
10.2
21.6
12.6
103.2
131.2
FIGURE 2. Pad Layout
:>0-....--.
CI
0(11
6-36 pF
Rl
10M
'X>-.....- .
TO COUNTERS
R2
200k
0(2)
Voo ORV ss
Rl
10M
C...
C••
Not.l: 32,768 HZlnti-rewnant
quanzc:ryst.I, CL -12 pF
TO COUNTERS
R2
200k
T
v..
31pF
T
T
8PF
BPF
VSS
v..
Note 1; 3Z.168 Hl tuning fOfk qu.rU cryrtll,C L -SpF
FIGURE 4(a). Oscillator RC Network for
Anti·Resonant Quartz Crystals
FIGURE 4(b). Oscillator RC Network
for Tuning Fork Quartz Crystals
7·15
functional description -(con't)
Set Minutes Mode: The Set Minutes mode will display
minutes in digit positions 3 and 4 preceded by the
colon. Depressing the SET/DISPLAY switch while
still holding in the Cycle switch will enable the hold
flag but will not allow advancement of the MINUTE
counter. Depressing the SET/DISPLAY switch after the
Cycle switch has been released resets and holds the
SECOND counter, enables the hold flag, and advances
the MINUTE counter at a 2 Hz rate. If neither switch
is depressed for 5.25 seconds ±O.125 seconds while
the watch is in the Set Minutes mode, the -watch will
automatically return to the Run mode if minutes have
not been set or will jump to the Hold mode if minutes
have been set. Depressing the Cycle switch while in the
Set Minutes mode will advance the watch to the Set
Day mode.
MM5886 by activating the HOUR/MINUTE input.
The HOUR/MINUTE input is used with an inertial
switch that is normally open. Closing the switch activates
the HOUR/MINUTE display. This display will remain
"ON" for 1.25 seconds ±O.125 seconds and then turn
"OF F" automatically.
Time Setting; The setting sequence is controlled by a
normally open switch connected to the Cycle input.
Depressing the Cycle switch will advance the watch to
the next set mode. Figure 5 is a flow diagram showing
the display and set functions' for both the MM5885
and the MM5886.
Set Hour Mode: With the watch in the normal Run mode
and the display "OFF," depressing the Cycle switch will
put the watch into the Set Hour mode. In this mode,
HOURS will be displayed in digit positions 1 and 2
followed by the colon. An A or a P will be displayed in
digit position 4 to indicate AM or PM, respectively.
Depressing the SET/DISPLAY switch will advance the
Hours counter at a 2 Hz rate. If neither the SET/
D ISP LA Y switch nor the Cycle switch are depressed
for 5.25 seconds ±O.125 seconds, the. watch will automatically return to the Run mode. Depressing the
Cycle switch while in the Set -Hours mode will advance
the watch to the Set Minutes mode.
Set Day Mode: The Set Day mode will display DAY-OFTHE-WEEK in digit positions 1 and 2. Depressing the
SET/DISPLAY switch while in the Set Day mode will
advance the DAY counter at a 2 Hz rate. If neither
switch has been depressed for 5.25 seconds ±O.125
seconds while in the Set Day mode, the watch will
automatically return to the Run mode if the hold flag
was not set or will jump to the Hold mode if the hold
flag was set. Depressing the Cycle switch while in-the Set
Day mode will advance the watch to the Set Date mode.
I
SID
~r-:I
'-----,;.:----'~
i
1:
*0
SET
~
MONTH
L-.~::---I
~_J
-
-
S/D-SET/DISPLAY
S/O 'SET/OISPLAY
H/M' HOUR/MINUTE
C- CYCLE
- • TIME-OUT ROUTE
H/M- HOUR/MINUTE
C =CVCLE
-
-
-
• TIME-OUT ROUTE
FIGURE 5(b). MM5886 Flow Diagram
FIGURE 5(a). MM5885 Flow Diagram
7-16
functional description (can't)
"ON" for 0.25 seconds and "OFF" for 0.75 seconds.
Depresssing the SET/DISPLAY switch will place the
watch in the display HOUR/MINUTE mode for 1.25
seconds ±O.125 seconds. Depressing the Cycle switch
while in the Hold mode will advance the watch to the
Set Hour mode. There is no roll-over of the next higher
counter while a counter is being set at a 2 Hz rate.
Set Date Mode: The Set Date mode will display DATE in
digit positions 3 and 4. Depressing the SET/DISPLAY
switch while in the Set Date mode will advance the
DATE counter at a 2 Hz rate. If neither the SET/
DISPLAY nor the Cycle switches have been depressed
for 5.25 seconds ±0.125 seconds while in the,. Set Date
mode, the watch will automatically return to the Run
Mode if the hold flag was not set or will jump to the
Hold mode if the hold flag was set. Depressing the
Cycle switch while in the Set Date mode will advance
the watch to the Set Month mode.
Month Counter: The MONTH counter provides "smart
Date" but is only displayed during the Set Month mode.
The DATE counter will count 28 days in February,
30 in April, June, September and November, and 31
in the remaining months.
Set Month Mode: The Set Month mode will display
MONTH in digit positions 3 and 4 and an "M" in digit
position 1. Depressing the SET/DISPLAY switch while
in the Set Month mode will advance the MONTH counter
at a 2 Hz rate. If neither the SET/DISPLAY'nor the
Cycle switches have been depressed for 5.25 seconds
±0.125 seconds while in the Set Month mode, the watch
will automatically return to the Run mode if the hold
flag was not set, or will advance to the Hold mode if
the hold flag was set. Depressing the Cycle switch while
in the Set Month mode will advance the watch to the
Hold mode if the hold flag was set; otherwise, the watch
will advance to the Run mode.
Contact Bounce: Debounce circuitry is provided on the
SET/DISPLAY, CYCLE, DAY/DATE and HOUR/
MINUTE inputs to remove any logic uncertainty upon
either closure or release of the switches. 20 ms debounce
protection is provided for SET/DISPLAY, CYCLE and
DAY/DATE inputs and 200 ms protection is provided
for the HOUR/MINUTE input.
Display Multiplexing: The counter data selected to be
displayed is time-division multiplexed to provide digitsequential presentation to the LED display. This reduces
Hold Mode: In the Hold mode the SECOND counter is
held at 00, and the HOUR-MINUTE display will blink
MINUTES (SECONDS)
HOURS
DAV
DATE (MONTH)
o Ou
o O~O
il~O
0
O~O
0
O~O
o
v
0
il~
:::0
0::::0
V
il~O
O~D
:::0 0::::0
o~ O~V
DaD
o 0'
o Du
o [60
::::0
~o
o
D~D
0
0::::0
V V
FIGURE 5(c). S~t Display Font
7-17'
SET HOURS
functional description (con't)
the number of outputs required to drive the 4-digit
display to thirteen (9-segment drivers and 4-digit drivers).
The display font is shown in Figure 6. Figure 8 is a
schematic diagram of a typical LED watch using the
MM5885 watch chip. The segment and digit drivers
are designed to interface directly with the LED display.
The four digits of the LED display are multiplexed
with a 23% duty cycle, 1024 Hz signal during the display
period. The digit drivers are disabled for 32psec at the
beginning of each digit enable time to allow the segment
decoding circuitry adequate time to switch to the next
digit's information. This eliminates the possibility of
"ghosting"information between digits.
Test Points: Four pads are provided for test purposes.
Dim Input: The Dim input is a 3-level input used to
control the display intensity of the watch. This input
has a pull-down to Vss to hold it normally at a logical
"0." In this condition, the display will normally be at
maximum intensity. With the Dim input at 1/2 V DD
the display will be at approximately 1/2 of full intensity.
Placing the input at V DO will reduce the display intensity to approximately 1/8 of full intensity. Figure 7
shows the switching threshold ranges for the 3-level
Dim input.
Test: This pad is used as an input to control the 4 Hz/
Test Freq pad. An internal pull-up resistor will normally
hold "Test" at a logical "1." Changing the Test input
from a logical "1" to a logical "0" will generate a reset
pulse which will set the internal counters to 1 AM on
Sunday, January the first. The watch is now in a known
state for testing.
4096 Hz: This pad outputs a 4096 Hz signal that can be
used for oscillator tuning.
4 Hz/Test Freq: This is an input/output pad under the
control of the Test input pad. When "Test" is at a logical
"0," the 4 Hz/Test Freq pad becomes an input and any
frequency connected to it will replace the normal.
internal 4 Hz signal. This feature is provided to allow
high speed functional testing of the watch system.
When "Test" is open or at a logical "1," a 4 Hz output
will appear on the 4 Hz/Test Freq pad.
Lamp: When the Lamp input is at a logical "0," all
segments of the display will be forced to an "ON"
condition under control of the normal 23% duty cycle
of the digit drivers. An internal pull-up resistor will
normally hold the Lamp input at a logical ~'1."
Colon Output: Colon information is present on the "h"
and "i" segment outputs during digit position 4.'
dJ
oo[bdJ ~V,
6 IlgrqUIJ
reo
o[b
bO
~6
=:JV
il=:J 0 0 OoOOlj
::060 o 0[b;0
SUNOAY
=:J
0
0
MONOAY
O=:JO
TUESOAY
oo O=:J
il 0 il=:J 0::0
O oc=J Oll
THURSOAY
o 0 o 0il=:J
WEONESOAY
O:J]
::OOu
il~
FRIOAY
SATUROAY
~ort:
A
FilJfOa
E~OC
FIGURE 6. Display Font
21.875% OUTY CYCLE
9.375% OUTY CYCLE
3.125%OUTYCYCLE
ill'-_________...:rL
9D'5~sj I~I~
-
3D.5~s
I
213.6~s__t--_r_-----976.5~s-----
DISPLAY TIME/DIGIT
DISPLAY CONDITION
Voo
3.125%
Low Ambient Light
Voo - O.5V
Threshold Region
Voo -l.lV
9.375%.
Vss + O.9V
Threshold Region
Vss + O.3V
21.875%
V1N
Moderate Ambient Light
High Ambient Light
Vss
FIGURE 7. Dim Input Levels
7·18
s:
s:
U1
functional description (con't)
Voo
I
VDD~
.....l-
1.5V
,.]:L,=
co
co
Vss
U1
I
s:
s:U1
SET/DISPLAY
co
co
CYCLE
500k,20%
Voo
BETA
240- 360
DIM
~~~
'-."~
NS IL
~
/1/
DSC IN
...L
0
-r-
~ OSC OUT
Voo OR
Vss
NSC 010 1
ilaO ilaO
Ogo DgO O:::D O:::D
il~O
f--
\
A
I
0
{'
0')
2 I--~ f--
SEGMENT ENABLE
CAP
Vss
NSC910 1
DIGIT
ENABLE
MM5885
il~O
B
C
E
0
F
G H
I
~
r--
r---
0
1
r
r
14
FIGURE 8(a). System Schematic for MM5885 LED Watch (Anti-Resonant Crystal!
Vo0+-:L
h
Vss
..-I
--
1.5V
-L
1.5V
-L
Voo
Vss
1
1
"'I""'''
CYCLE
DIGIT
MM5885
F
--c...-
ENABLE
OSC IN
osc OUT
SEGMENT ENABLE
I
\
A
NSC 910 1
NSC 010 1
ilaO flaO
o:lo o:lo
1
2
0
0
ilc=JO ilc=JO
B
C
0
E
F
G
H
1
f--
r-
I----
,
0::0 O::D
r
14
FIGURE 8(b). System Schematic for MM5885 LED Watch (Tuning Fork Crystal!
7-19
{'
2 I---~ ~
f--
o
0')
'co
Watches
LO
~
~
MM5890 LCD chronograph circuit
general description
features
The MM5890 is a low threshold voltage, ion implanted,
metal-gate CMOS integrated circuit that provides all
signals needed to drive an LCD watch of six digits plus
nine information segments. The circuit time base is a
32.768 kHz crystal controlled oscillator. This base
frequency is divided down to provige SECONDS, MINUTES, HOURS, DAY-OF-THE-WEEK, DATE and
MONTH information in the normal watch mode with
separate minutes, seconds, and hundredths of a second
available in the stopwatch mode. Time display can be
bonded to either 12 or 24 hour format. 51 phase controlled outputs are provided for direct drive of the
display. ,The 32 Hz output is used as the backplane
drive for normal operation and as a test frequency
input during testing. The MM5890 operates on a single
l.4V to 1.6V supply. An on-chip voltage multiplier is
used to provide 2 or 3 times the battery voltage to drive
the display. The MM5890 is available in die form suitable for hybrid assembly or mounted on a 68-lead
dual-in-line PCB assembly for test and evaluation
, purposes.
•
Direct continuous LCD drive capability
•
32.768 kHz crystal controlled operation
•
Single 1.5V battery operation
•. Voltage multiplier
•
Low power dissipation
•
6-digit plus 9 information segment display
•
Colon display
•
12 or 24 hour format
•
4 year calendar
•
Stopwatch with split operation
•
6-function w<;ltch
•
4 button sequential operation
block diagram
TEST
12 HR
47 SEGMENT DRIVE OUTPUTS
FIGURE 1.
7-20
CAP 1 CAP 2 CAPJ
VEE
absolute maximum ratings
Storage Temperature Rang~
VDD - VEE
VDD-VSS
Lead T~mperature (Soldering, 10 seconds)
Voltage at OSC IN, OSC OUT,
VDD + O.3V to VSS -O.3V
12 HR. SW Disable, Double, Triple
Set/Display, Cycle, Mode, Start/Stop
Voltage at Any Other Pin
VDD + O.3V to VEE - O.3V
Operating Temperature Range
-5°C to +70°C
-2S0C to +85°C
6.5V
3.0V
300°C
electrical characteristics
T A within operating range, VDD - VSS = 1.5V, VDD - VEE = 4.5V, VDD
PARAMETER
CONDITIONS
@
Ground unless otherwise noted.
MIN
TYP
MAX
UNITS
Oscillator Start Voltage
T A = 25°C, '(Note 1)
1.40
V
Oscillator Sustaining Voltage
T A =-5°C, (Note 1)
1.30
V
Input Voltage Levels
Set/Display, Cycle
Start/Stop. Mode
Logical "1"
Logical
"a"
V
VDD-D·25
Open
Internal Pull·Down to VSS
V
Test
Logical "1"
Logical
"a"
32 Hz/Backplane
V
VDD-D·25
Open
Internal Pull·Down to VEE
V
Test Input = VDD
Logical "1"
V
VDD-D·25
VEE+0.25
Logical "0"
V
12 HR, SW Disable
Logical "1"
V
VDD-D·25
Logical "0"
VSS+0.25
V
Input Current Levels
Set/Display, Cycle, Start/Stop,
30
VIN = VDD
50
pA
Mode, Test
I nput Capacitance
ill
f=l MHz,VIN=OV,
All Other Pads Gnd
OSC OUT
8
OSC Cap
37
pF
pF
5
All Others
pF
Output Current Levels
Segment Drivers
Logical "1" Source
VOUT = VDD - 0.2V,
2.0
pA
2.0
pA
200
pA'
200
pA
7.5
pA
(VDD - VEE =3V)
Logical "0" Sink
VOUT = VEE + 0.2V,
(VDD - VEE = 3V)
BP/32 Hz Output
Logical "1" Source
VOUT = VDO - 0.2V,
(VDD - VEE = 3V)
Logical
"a" Sink
VOUT = VEE + 0.2V,
(VDO - VEE = 3V)
Output Current Levels
Double, Triple
Logical "1," Source
VOUT = VDO - 0.25V,
Phase 2 < 1 ms
Logical "a," Sink
VOUT = VSS + 0.25V,
Phase 3
7·21
pA
electrical characteristics
(Continued)
PARAMETER
CONDITIONS
MIN
TYP
M,AX
UNITS
= VDD -
7.5
pA
20.0
pA
Cap 1
Logical "1," Source
VOUT
0.25V,
Phase 1
Logical "0," Sink
= VSS + 0.25V,
VOUT
r
Phase 2
Leakage
= VDD
VOUT
0.6
- 3.0V,
pA
Phase 3
Cap 2
Logical "0," Sink
= VSS + 0.25V,
VOUT
pA
35.0
Phase 1
Leakage
VOUT
= VEE + 1.5V,
0.6
pA
Phase 2
VEE
Logical "0," Sink
Cap 2
= VDD
250.0
- 4.2V,
pA
Phase 3
VOUT
Input Debounce
Cycle, Mode
= VDD -
3.95V
Test Input Open
120
260
ms
120
260
ms
Set ("1" to "0" Transition)
60
130
ms
Start/Stop
60
130
ms
3.0
6.0
pA
6.0
8.0
pA
Supply Current (I DD)
Osc. In Freq
= 32.768
Set ("0" to "1" Transition)
kHz
= 25°C, lEE = 1 pA,
= 32,768 Hz, VDD - VSS =
TA
Doubler Operation
f
Tripier Operation
1.6V, (Note 1)
= 25°C, C"" 0.047 pF,
= 1 pA, f = 32,768 Hz,
Supply Voltage (VEE)
TA
Doubler Operation
lEE
Tripier Operation
VDD - VSS = 1.5V,
2.5
V
3.8
V
(Figure 9), (Note 2)
Note 1: In oscillator network shown in Figure 4.
Note 2: External capacitors connected as shown in Figure 9.
functional description
can be used to monitor' the oscillator frequency during
initial trimming without disturbing the network itself.
A block diagram of the MM5890 chronograph chip is
shown in' Figure 1 with the chip pad layout shown
in Figure 2.
DISPLA Y CONTROL
Time Base: The precision time base of the chronograph
is provided by connecting a crystal controlled RC network to the on-chip CMOS inverter/amplifier as shown
in Figure 3. For proper operation the network should be
tuned to 32.768 kHz. Resistor R1 is used to bias the
on-chip inverter for class A amplifier operation. Resistor
R2 is used to: a) reduce the voltage sensitivity of the'
network; b) limit the power dissipation in the quartz
crystal; and c) provide added phase shift for good
start-up and low voltage operation. Capacitors C1 and
C2 in series provide the paralielload capacitance required
for precise tuning of the' quartz crystal. The network
shown in Figure 4 provides greater than 100 ppm
tuning range when used with standardX-Y flexure'
quartz crystals trimmed for CL = 13 pF. Tuning to
better than 2 ppm is easily obtainable. The 32 Hz output
7-22
Watch Mode: When used as a watch, the MM5890 has
tw~ display modes. The first mode displays the HOUR
in digit positions 1 and 2, the MINUTE in digit positions
3 and 4, the DATE in digit positions 5 and 6 and the
DAY-OF-THE-WEEK (Figure 5). The second mode will
display SECONDS in digit positions 5 and 6 instead of
the DATE. Depressing the Set/Display switch will change
the watch from one mode to the other:
Leading zero values of the DATE and HOU Rare
blanked. The circuit contains a 4 year calendar which
will automatically reset the Date Counter to 1 and
advance the Month Counter at the end of each month
(except for February in Leap Year). The character
display font is shown in Figure 6.
functional description
s:
s:U1
(Continued)
1l.5
34.5
16.6
101.3
124.l
140.l
156.l
CO
112.l TEST
CD
o
5.5
5.5
CAPZ
lU
11.1
21.1
40.8
081
51.8
OA2
lO.5
41.5
DF2
DB2
1l.6
o SPLIT
_'90_
MILS
14 .•
OSUN
15.1
OMON
MM5890
LCD CHRONOGRAPH
(ALL PADS ARE 5.0 X 5.0 MILS MINIMUMI
101.1
OTUES
COLON D
111.1
OWED
MONTH D
101.5
112.5
G30
12l.5
62.6
121.6
t
DTHUR
1l2.6
OFRI
180 .•
o SAT
161.1
Dos
112.6
OE5
195MILS
~
46.l
8.1
65.1
83.9
51.5
GZD
EzD
68.5
DzD
19.5
c2D
90.5
ElD
134.5
AllDlO
145.5
c3D
102.7
121.5
140.l
156.5
F40
161.5
G4D
118.5
E40
189.5
161.1
FIGURE 2. Chip Pad Layout
12 HR VSS
SW
REJ
STARTI
BPIl2
CYC STOP MODE TEST H.
IF
IG
IE
lC
2G
2E
20
2C COLON MONTH 3G
lE
lAllO 3C
4F
4G
4E
40
4C
·48
4A
lB
3F
6E
60
6C
50
5E
5G
NC
SF
SA
5B
5C
6G
6F
6A
68
MM5890
J4
VOD
CSC
CUT
OSC
IN
SET
VEE lA110 18
2F
2A
26 SPLIT SUN MCN TUE WED THU
FRI
SAT
FIGURE 3. Connection Diagram
.... --------------- --,
;'
(
M
0
CMOS
INVERTER
\
SECONDS, DATE, MONTH
STOPWATCH 11100 SECONDS
T
W
T
F
·s
U
E
H
R
A
foPz/
;'--~
/1-
fI
I~O~
5·J6pF
LAP
0:00:0
6060
,
FIGURE 4. Crystal Oscillator Network
HOURS
STOPWATCH
MINUTES
MON
0
0
COLON
0:00:0
6060
MINUTES
STOPWATCH
.. SECONDS
~---------------~
FIGURE 5. Display Format
7·23
/
I
o
en
00
functional description
(Continued)
U')
MINUTE: Depressing the Cycle switch while the watch
is in the Set Hour mode will put the watch in the Set
Minute mode with the MI NUTE information displayed
in digit positions 3 and 4. Depressing the Set/Display
switch will advance the MI NUTE counter at a 1 Hz rate
and activate the Hold mode.
~
~
DAY-OF-THE-WEEK: Depressing the Cycle switch
while the watch is in the Set Minute mode will place it
in the Set Day mode with the DAY-OF-THE-WEEK displayed. Depressing' the Set/Display switch will change
the DAY-OF-THE-WEEK at a 1 Hz rate until the switch
is released.
FIGURE 6. Display Font
DATE: Depressing the Cycle switch while the watch is
in the Set Day mode will advance it to the Set Date
mode with the DATE (day of the month) displayed in
digit positions 5 and 6. Depressing the Set/Display
switch while the watch is in the Set Date mode will
advance the DATE at a 1 Hz rate until the switch is
released.
Stopwatch Mode: Depressing the Mode Switch will
switch the watch from the normal watch mode to the
stopwatch mode. When used as' a stopwatch, the
MM5890 displays the stopwatch MINUTE in digit positions 1 and 2, the stopwatch SECOND in digit positions
3 and 4, and the stopwatch 1/100 SECOND in digit
positions 5 and 6. Depressing the Start/Stop Switch will
either start the stopwatch if it is not counting or stop
it if it is counting.
Month: Depressing the Cycle switch while the watch is
in the Set Date mode will advance it to the Set Month
mode with the Month displayed in digit positions 5 and
6 and the Month indicator "ON." Depressing the Set/
Display switch while in this mode will advance the
Month counter at a 1 Hz rate until the switch is released.
Depressing the Set switch will activate the Split Time
mode.. In this mode the watch will freeze the time
showing on the display at the instant the Set switch is
depressed. The stopwatch continues counting and the
colon will begin blinking at a 1 Hz rate to indicate the
continuing count. Depressing the Start/Stop switch will
stop or start the stopwatch counters. The colon will
remain "ON" in the Split Time mode if the stopwatch is
not counting. The Split indicator (refer to Figure 5) will
be "ON" during the Split Time mode. Depressing the
Set switch while the watch is in the Split Time mode
will return the accumulated time in the stopwatch to the
display and the Split indicator will turn "OFF."
Depressing the Cycle switch while the watch is in the
Set Month Mode will place the watch in the normal
display mode with HOUR, MINUTE, DATE, and DAYOF-THE-WEEK information displayed.
Hold: If the Hold mode was activated while in the Set
Minute mode the colon will not blink in the normal
time display but remain on continuously. The SECOND
counter is held at 00, forcing the watch to remain at the
displayed time. Depressing the Set/Display switch will
switch the watch to the alternate time display mode
(HOUR, MINUTE, SECOND, and DAY-OF-THE-WEEK)
and release the SECOND counter allowing normal
operation to begin. While in any of the Set modes,
advancing the selected counter will not cause a roll-over
of higher state counters. For example, advancing the
HOUR counter from 11 PM to 12 AM will not cause the
DATE or DAY-OF-THE-WEEK counters to advance.
Depressing the Set switch while the stopwatch is not
running and is not in the Split Time mode will clear the
stopwatch counters to a zero count. Depressing the
Mode switch while the stopwatch mode is active will
transfer the watch to the normal watch mode. This:
transfer will not affect the stopwatch function and the
stopwatch will continue performing the same function
until the stopwatch mode is again activated with the
mode switch.
A control state diagram for the MM5890is provided in
Figure 7.
Setting Control: A normally open switch connected to
the Cycle input is used in conjunction with the Set/
Display input to set the MONTH, DATE, DAY-OFTHE-WEEK, HOUR, MINUTE and synchronize the
SECON D information.
Contact Bounce: Debounce circuitry is provided on the
Set/Display, Cycle, Start/Stop, and Mode inputs to
remove any logic uncertainty upon either closure or
release of switches provided switch bounce settles
within 120 ms (Set/Display release bounce must settle
within 60 ms;)
HOUR: With the watch in the watch mode depressing
the Cycle switch will put the watch in the Set Hour
mode. The HOUR information will be in digit positions
1 and 2 with either an A or a P in digit position 4
indicating AM or PM. Wh'ile in this mode, depressing the
Set/Display switch will cause the HOUR counter to
advance at a 1 Hz rate until the switch is r"eleased.
12/24 Hour Option: 12/24 hour operation is controlled
by the logical state of the 12 HR pad. Connecting the
12 HR pad to a logical "1" will cause the watch to
operate in the 12 hour mode while connecting the
12 HR pad to a logical "0" will cause the watch to
operate in the 24 hour mode.
7-24
functional description
(Continued)
Segment Outputs: The Segment outputs are designed to
drive field-effect liquid crystal displays. Each display
segment has its own output which supplies the proper
32 Hz drive signal. By definition, the segment is "OFF"
when its drive signal is in phase with the Back Plane
drive signal (BP/32 Hz) and the segment is "ON" when
0
the drive signal is 180 out of phase with the Back Plane
drive signal (refer to Figure 8).
BP/32 Hz: This input/output pad is under control of
the Test input. When Test is open or at a logical "0,"
a 32 Hz signal is provided at BP/32 Hz which is used to
drive the backplane of the LCD unit or to monitor the
oscillator frequency. If Test is at a logical "'," the
BP/32 Hz pad is converted into an input and any frequency connected to it iNill replace the normal internal
,32 Hz signal. This feature allows high speed- testing of
all timekeeping and stopwatch counters.
SET
~
DISPLAY
DAY DATE
HOUR: MINUTE
I(CLE~
HDLD)
DISPLAY
DAY SECOND
HOUR: MINUTE
Ir.
CYCLE
~
DISPLAY HOUR
WITH A OR P
¢=:J
J
!.
SET
~
MOOE
ADVANCE
HOUR
DISPLAY SPLIT TIME
MINUTE: SECOND
1/100 SECOND
STOPWATCH
COUNTING
+- CYCLE
SET
DISPLAY MINUTE
~
+
ADVANCE
MINUTE
SET HOLD MODE
CYCLE
DISPLAY
DAY-OF-WEEK
SET
~
ADVANCE
DAY-OF-WEEK
+- CYCLE
SET
DISPLAY
DATE
1+-+
ADVANCE
DATE
+- CYCLE
""--
SET
DISPLAY
MONTH
~
ADVANCE
MONTH
FIGURE 7. Control State Diagram
VDD
BACKPLANE
SEGMENT
VEE
~1~·------------OFF----------~'-III-'~--------~ON----------~·~1
FIGURE 8. Phase Drive Signals
7-25
functional description
(Continued)
Test: This input is used to control the BP/32 Hz pad as
described above. When Test is at a logical "1" the
phase·control is disconnected from the segment drive
outputs and the segment information is referenced to a
logical "0" backplane. Switching the Test input from a
logical "0" to a logical "1" generates a reset pulse that
will reset the counters to Sunday. 1 AM on January the
first. All stopwatch counters will be set to 00 and the
watch will be· placed in the normal time display mode.
SW Disable: This input is used to control accessability
to the stopwatch functions. If SW Disable is at a logical
"0" the· Mode switch can be used to activate the stopwatch functions. If SW Disable is at a logical "1" the
Mode switch is inoperative and the stopwatch functions
are locked out.
5·36 pF
_---1/10--..........- - 0
50 pF TYP
32.768 kHz
asc
VOO OR VSS
-------tD-------asc
IN
OUT
OSC
CAP
Voo
12HR ......- - - - .
START/STOP
SET/DISPLAY
CYCLE
MOOE
I
DISPLAY
UNIT
DOUBLE
51
SEGMENT
OUTPUTS
------,
TRIPLE
MM5890
I
0.05J.LF I
I
I
___ ...J
0.05J.LF
VEE
0.05J.LF
VOO
BP
SW DISABLE
FIGURE 9. Typical Application
7-26
VSS
-"-
~0.05J.LF
CAP 1
CAP2
I
I
+
Watches
MM58104 direct drive LED watch
general description
features
The MM581 04 is a low threshold voltage, ion-implanted,
metal-gate CMOS integrated circuit that provides or
controls all signals needed for a 3 112 digit 3-function or
a 4-digit 4-function LEO watch. The display format is
12 hours. The circuit time base is a 32,768 Hz crystal
controlled oscillator. This time base frequency IS successively divided to provide drive signals for a multiplexed 7-segment LED display. Upon demand MM58104
will display HOURS-MINUTES or SECONDS when it
is used as a 3-function watch and will also display DATE
when it is used as a 4-function watch. The outputs will
directly drive a 7-segment LED display. The device
operates from a single 2.4 V to 4.0V supply. The
MM58104 is available as unpackaged die suitable for
hybrid assembly or in 40-lead dual-in-line packages
for evaluation purposes.
•
32,768 Hz crystal control oscillator
•
•
Single 3V supply
Low power dissipation (15pW typical)
•
3 1/2 digit (3-function) or 4-digit (4-function) option
•
12 hour display format
•
Simple display/set controls
•
Direct drive outputs for LED's
•
Display brightness control
•
On-chip oscillator bias network
functiona I descri ption
A block diagram of the MM58104 digital watch chip is
shown in Figure 1_ A chip pad layout is shown in
Figure 2 and package connection diagram in Figure 3.
block diagram
chip pad layout
1-----------146.oMILS-------57.3
102.95
1
80.15
I
0
SEGb
0
SEG,
125.75
I
136.5- OVOO 0
SEG g
I·
0
SEG,
20.95
41.15
I
10.65
I
1
'0
0lS4
0
0
DIS 3 SET
113.05- OSEGd
93.3- OSEG,
MM58104
DIMENSIONS TO
CENTER OF PADS
56.0-
o LAMP
48.6- OTEST
41.0- 04Hz
33.5- OCOLON
25.55- OOIM
16.75- 04096
VSS
DIG 2
SEGMENTS
DIG 1
o
0 DO
0
57.6
88.25
8.5
(Top View)
TEST 4 Hz! COLON DIM 4096
TEST
Hz
FREQ
DIG J
DIG 4'
OSC OSC
OUT IN
.0
0 0
----0-~~I~~------49~18~5,~1~6~5IJ~5--~~I~--~I~IJ~.75~1~1~30~I.7~5~1~
FIGURE 1.
connection diagram
6
CAP
OT
JCYCLE
NC
FIGURE 2.
2
1
~
Vss 'OUTY
3
4
CYCLE~
DIGITS
DIGITS
FIGURE 3.
7-27
CAP
OSC
OUT
NC
NC
OSC
IN
NC
NC
NC
123.25
140.25
,
absolute maximum ratings
Voltage at Any Pin
Operating Temperature Range
Storage Temperature Range
Voo-Vss
Lead Temperature (Soldering, 10 seconds)
Vss - 0.3V to Voo + 0.3V
-5°C to +70°C
-25°C to +85°C
5V max
300°C
electrical characteristics
T A within operating temperature range, Vss
= GND,2,4 ~ Voo
PARAMETER
~
4.0V, unless otherwise noted.
CONDITIONS
Oscillator Start Voltage
TA = 25°C
Input Voltage Levels @ Display 3,
Voo = 3.0V
MIN
TYP
MAX
UNITS
2.7
V
Display 4, Set
Logical "1"
1/2 Voo
Logical "0"
300 kn Internal
Input Voltage Levels @4 Hz/
Pull·Dow~
to Vss
Voo
V
Open
Voo = 3.0V
Test Freq, Dtcycl
Logical "1"
Voo-D·25
Voo
V
Logical "0"
Vss
Vss+0.25
V
Vss+0.25
V
Input Voltage Levels @ Lamp, Test
Logical "1"
Voo = 3.0V
Open
1 Mn Internal Pull·Up to Voo
Logical "0"
Vss
Input Current @ Display 3, Display 4, Set
V 1N = V oo , Sink Only, Voo = 3.0V
30
50
pA
Input Current @ Lamp and Test
V 1N = V ss , Source Only, Voo =3.0V
30
50
pA
15
mA
50
pA
Output Current Levels @ Segment Drivers
Voo = 2.7V
"ON" Source
V OUT = V DO
"OFF"
V OUT = Vss + 1.lV
Output Current Levels @ Digit Drivers
-
7
0.5V
10
Voo = 2.7V
"ON" Sink
V OUT = Vss + 0.6V
"OFF"
V OUT
= 2.0V,
50
mA
70
2
All Digit Drivers
Output Current Level @ COLON
"ON" Sink
"OFF"
,;
Output Current Levels @ 4096 Hz,
pA
\
Tied in Parallel
Voo = 2.7V
V OUT = V ss + 0.7V
V OUT = Voo -1.6V
mA
6
0.5
pA
Voo = 3.0V
4 Hz/Test Freq.
Logical "1," Source
V OUT = Voo - 0.5V
Logical "0," Sink
V OUT
Supply Current
(100)
= Vss
pA
10
+ 0.5V
pA
10
f = 32,768 Hz, T A = 25°C,
5
10
pA
0.05
1
pA
Voo = 3.0V, Unused Inputs Open,
Outputs Open
Supply Current (1 00 )
T A = 25°C, V ss , OSC IN & Dtcycl @ GND,
Voo = 3.0V, Unused Inputs Open,
Outputs Open
Input Capacitance
f = 1.0 MHz
OSCOUT
V 1N = O.OV
8
CAP
All Other Pads GND
37
All Others
Input Voltage Level @ DIM
pF
pF
5
Voo = 3.0V
pF
I
Positive·Going Threshold (V T +)
1.5
V
Negative·Going Threshold (V T _)
1.0
V
Vn - V T _ Hysteresis
0.5
Input Current @ DIM
V 1N = V ss , Voo = 3.0V, Source Only
7·28
"
V
0.3
pA
s:
s:U1
functional description (can't)
(X)
o
7-segment outputs of the MM58104 are designed to
interface directly with the NSC0101 LED display. The
four digits of the LED display are multiplexed with a
25% duty cycle, 1024 Hz signal during Display. The
digit drivers are turned off by the internally generated
inter-digit blanking signal during the change of digits to
allow the segments to change without "ghosting" of
the Display. When MM58104is used as shown in the
typical application of Figure 6, the segment on currents
are typically 9 mAo The NSC0101 LED Display gives
excellent brightness under these drive conditions_
Time Base: The precIsion time base of the watch is
provided by the interconnection of a 32,768 Hz quartz
crystal and the RC network shown in Figure 4 together.
with the CMOS inverter/amplifier provided between the
oscillator in and oscillator out terminals. Resistor R 1 is
necessary to bias the inverter for class A amplifier
operation. Resistor R2 is required in order to (a) reduce
the voltage sensitivity of the network; (b) limit the
power dissipation in the quartz crystal; and (c) provide
added phase shift for good start·up and low voltage
circuit performance. Capacitors C1, C2 and C3 provide
the parallel load capacitance required for precise tuning
of the quartz crystal. The RC network except the trim
capacitor C3 is integrated on-chip.
The switch inputs "Display 3" and "Display 4" of the
MM58104 are to be used for 3 and 4-function LED
watches, respectively. However, "Display 3" can be
connected -to an inertial switch for HOURS-MINUTES
Display in a 4-function watch_ In subsequent paragraphs,
the term "Display" will take the place of "Display 3"
and/or "Display 4," unless otherwise specified.
The network shown provides> 100 ppm tuning range
when used with standard X-Y flexure quartz crystals
trimmed for C L = 12 pF. Tuning to better than ±2 ppm
is easily obtainable.
The 4096 Hz output or 4 Hz output can be used to
monitor the oscillator frequency during initial tuning
without disturbing the network itself.
Time Display:
The DATE .and HOUR-MINUTES/
SECONDS displays are controlled by a normally open
switch connected to "Display" input as shown in Figure
6_ DATE or HOU R is displayed in digit positions 1 and
2. MINUTE or SECOND is displayed in digit positions
3 and 4. Colon output will be "ON" except when the
Display involves DATE. The two colon -dots are to be
connected in parallel with their anodes to V DO and
cathodes to the "COLON" output.
Display Multiplexing: Outputs from each counter are
time-division multiplexed to provide digit-sequential
access to the time data. Thus, instead of requiring 28
leads to interconnect a four digit (7 segments/digit)
watch, only 11 output leads are required. The character
display font and segment identification is shown in
Figure 5. Figure 6 shows the interconnection of a LED
watch system. The 4-digit outputs, colon output and the
Closure of the "Display" switch will cause HOURMINUTES to be displayed for 1.25 ±0.125 seconds.
Rl
10M
CMOS INVERTER
R2
200k
-LeI
BpF
I
l37
--
Vee Dr Vss
FIGURE 4. Crystal Oscillator Notwork
7-29
Vee
C2
CAP
-
P
F
~
~
o
00
functional description (con't)
Ln
~
~
Holding the "Display" switch closed after the time-out
of HOUR-MINUTES display will cause SECONDS to
be displayed until the "Display" switch is open_ SECONDS will blink while displayed_ Each value is visible
for, 0.25 second and blank for 0.75 second. HOURS
digits can display values 1-12with an AM indicator,
which is the F segment of digit 1_ Leading zero values'
of hours are blanked. MINUTES or SECONDS digits
can display values from 00 to 59. All zero values of
minutes or seconds are displayed.
continuously. Closure of the "Set" switch will then
advance DATE at a 2 H~ rate until the "Set" or both
switches are opened. Seconds, Minutes and Hours
counters continue normal counting during this condition.
HOURS: Closure of the "Set" switch will cause HOURSMINUTES to be displayed and will advance HOURS at a
2 Hz rate until the "Set" switch is opened. Seconds and
Minutes c'ounters continue norm'al counting during this
condition.
Closure of the "Display 4" switch twice before the
time-out of HOURS-MINUTES display will cause
DATE to be displayed for 1.25 ±0.125 seconds. Holding
the "Display" switch closed will continue DATE display
until the switch is open. Date digits can display values
from 1 to 31. Leading zero values of Date are blanked.
MINUTES:
Closure of both "Display" and "Set"
switches will cause HOURS-MINUTES to be displayed
and will advance MINUTES at a 2 Hz rate after both
switches have been closed for 0.75 to 1.0 seconds. When
the minutes count is correct, opening the "Set" switch
while keeping the "Display" switch closed will cause
HOURS·MINUTES to be displayed and Hold the watch.
HOURS-MINUTES will blink while displayed, visible
for 0.25 second and blan k for 0.75 second. The seconds
counter is reset and held at 00 during Minutes s~ttlng
or during the Hold Mode. All counters resume their
normal counting when both "Set" and "Display"
switches are opened. With the "Display" switch closed,
Time Setting: A normally open switch connected to
the "Set" input is used in conjunction with the "Display" switch to set date, ho~rs, minutes and synchronize
seconds.
DATE: Closure of the "Display 4" switch twice and
holding it closed will cause DATE to be displayed
ONE
ZERO
FIVE
SIX
TWO
THREE
FOUR
SEVEN
EIGHT
NINE
SEGMENT IOENTIFICATION
FIGURE 5. Character Display Font
7-30
functional description (con't)
a closure of the "Set" switch for less than 0.75 second
will reset the seconds counter to 00 without advancing
the minutes.
Test Points:
Four pads are provided for test purposes.
4096 Hz: is an output. A 4096 Hz symmetrical signal
is brought out for oscillator tuning.
There is no roll-over of the higher counters while the
lower time counters are being set. For example, while
setting Minutes a 59 to 00 transition will not advance
the Hours counter.
4 Hz/TEST FREO: is an input/output under the control
of "TEST," When "TEST" is open or at a logical "1," a
4 Hz signal will appear on the "4 Hz/TEST FREO
pad." If "TEST" is at a logical "0," the "4 Hz/TEST
F R EO pad" becomes an input and any frequency
connected to it will replace the normal internal 4 Hz
signal. This feature is provided to allow high speed
.functional testing of the watch system.
Contact Bounce: Debounce circuitry is provided on the
"Display" and "Set" inputs to remove any logic uncertainty upon either closure or release of switches provided
switch bounce settles within 20 ms.
Display Brightness Control: The display brightness is a
function of digit on-time which is a fraction of the digit
multiplexers. The digit on-time varies from 1/8 to 7/8
of the digit multiplexer in steps depending on the logical
levels of both "DIM" and "DTCYCL" inputs as shown
in Table I. The "DIM" input has an internal pull-up
resistor which will hold the open input at a logical
"1." The logical levels at the "DIM" input can be
established by a network as shown in Figure 6.
TEST: is an input. It is used to control "4 Hz/TEST
FREQ" as described above. An internal pull-up resistor
will normally hold the "TEST" input to a logical "1."
LAMP: is an input. When "LAMP" is at logical "0," all
segments will be forced to an "ON" condition under
control of the normal 25% duty cycle' of the digit
drivers. An internal pull-up resistor will normally hold
the "LAMP" input to a logical "1."
voo
NSIL
Beta 60- 90
(PHOTO·TRANSISTOR)
DISPLAY 4
MM58104
SET
O~~ 1----41.1
OTCYCL t---~.---- voo DR Vss
SEGMENTS
DIGITS
COLON 1-4
•
•
voo
NSC010l
LED DISPLAY
The DOT in the first digit is tied to segment bus "F."
It is used as the AM indicator.
FIGURE 6. Typical Application of MM581 04 in LED Digital Watch System
TABLE I. Display Brightness Control
DTCYCL
1
1
0
0
DIM
DIGIT ON-TIME
(Fraction of Digit Multiplexer)
7/8
2/8
4/8
1
0
1
0
1/8
7-31
Watches
MM58115 digitally tuned direct drive 6-function LED watch
general description
features
The MM5Bl15 is a low threshold voltage, ion-implanted,
metal-gate CMOS integrated circuit that provides or
controls all signals needed for a 4-digit, 6-function LED
watch. The display format is 12 hours. The circuit time
base is a 32,76B Hz crystal controlled oscillator. This
time base frequency is successively divided to provide
drive signals for a multiplexed 9-segment, alphanumeric
LED display of HOURS-MINUTES, DAY-DATE,
MONTH-DATE or SECONDS upon demand. A month
counter is provided to control the count sequence of
the Date counter. Inputs are also provided to digitally
tune the time base (Le., no tuner capacitor is required).
The MM5Bl15· uses one button for display purposes.
Both segment and digit outputs can be directly interfaced with 100 mil LED displays of the NSC9101 type.
Special circujtry is included to provide uniform digit'todigit brightness. The device operates from a single 2.4V
to 4 V supply. The MM5Bl15 is available as unpackaged
die suitable for hybrid assembly or in a 40-lead dual-inline package for evaluation purposes.
•
No external parts except the battery, LED display
and crystal
•
Single button display control
•
•
•
•
Direct drive outputs
Digital tune network
Uniform display brightness
32)6B Hz crystal controlled operation
• Single 3V supply
• Low power dissipation (1 0IlW typ)
Day-of-Wee,~,
•
Seconds, Minutes, Hours,
Month operation
•
•
4 year calendar
4-digit, 6-function, 12-hour display format
• Simple display/set controls
• . Alphanumeric display
•
Display brightness control
•
•
AM/PM indication during set hours
Month indication during set month
•
Test features
block diagram
CAP1~
CAP2
o-::L. T
r------It-....o ~UTY CYCLE CONTROL
T~
Vss~
VDD~
LAMP
0>----------+1
FIGURE 1.
7-32
Date and
absolute maximum ratings
Voltage at Any Pin
Operating Temperature Range
Storage Temperature Range
VSS - 0.3V to VOO + 0.3V
-5°C to+70°C
-25°C to +85°C
5V max
VOO - VSS
300°C
Lead Temperature (Soldering, 10 seconds)
electrical characteristics
T A within operating temperature range, VSS = Gnd, 2.4 ::; VOO ~ 4 V unless otherwise noted.
CONDITIONS
PARAMETER
TYP
MAX
2.7
TA = 25°C
Oscillator Start Voltage
MIN
UNITS
V
Input Voltage Levels at Cycle,
Set/Display, Hour/Min
100 kD Internal ~ull·Down
Logical "1"
Logical
"a"
1/2VDD
VDD
V
Open
to VSS
Input Voltage Levels at 4 Hz/
Test Frequency
Logical "1"
VOD-o·25
VOO
V
Logical "0"
VSS
VSS+0.25
V
VSS+0.25
V
Input Voltage Levels at Lamp, Test
Logical "1"
Logical
Open
100 kD Internal Pull·Up to VDO
"a"
VSS
Input Voltage Levels at Duty Cycle
Logical "1"
Logical
No Pull·Up (Must Be Bonded)
"a"
Input Voltage Levels at Dim
display duty cycle = 21.875%
@
A/D, Pl-P8
Logical "1"
Logical
V
Vss
V
Duty Cycle = VSS
5 MD Pull·Down to VSS
display duty cycle = 9.375%
Input Voltage Levels
VDD
Open
VSS+0.3'
VDD-o.5
V
VDD
V
VOD
V
10 MD. Internal Pull·Down to
VDD-o·25V
VSS
"a"
Open
Input Current at Cycle,Set/Oisplay,
VDD = 3V, VIN = VOD,
Hour/Min
Sink Only
Input Current at Lamp, Test
VDD = 3V, VIN = VSS,
30
50
/1 A
30
50
/1A
350
nA
Source Only
Input Curren.t
@
A/D, Pl, P2, P4, P8
VDD = 3V, VIN = VDD
Logical "1"
Logical
"a"
Input Capacitance
f = 1 MHz, VIN = OV, All Other
Pads Gnd
Osc. Out
8
pF
CAP 1
37
pF
CAP 2
15
All Others
Output Current Levels at Seg;"ent Orivers
pF
5
pF
VDD = 2.7V
"ON," Source
VOUT = VOO - 0.5V
"OFF," Leakage
VOUT= VOO -l.lV
7·33
7
10
15
mA
50
/1 A
fII
electrical characteristics
(Continued)
PARAMETER
CONDITIONS
Output Current Levels at ~igit OHvers
MIN
= 2.7V
VOUT = VSS + 0.6V
TYP
MAX
UNITS
Voo
"ON," Sink (6 or 7-segment display)
(S or 4-segment display)
so
If'Colon is "ON," Add 2 mA
(1,.2 or 3-segment display) to Digit 4 Sink Current
"OFF," Leakage
70
mA
60% of 6 or 7-segment current
46% of 6 or 7-segment current
VOUT = 2V, All Digit Drivers
2
J..tA
Tied in Parallel
Output Current Levels at 4 Hz/Test
Freq, 4096 Hz, 8 Sec .
. Logical "1," Source
Logical "0," Sink
Supply Current (100)
VOUT = VOO - 0.6V
10
VOUT = VSS + 0.6V
10
TA
= 2SoC, f = 32,768 Hz,
3.S
7
O.OS
1.S
Unused Inputs Open, Outputs
Open
Supply Current (100)
TA
= 2SoC, VSS, Osc.
In, Duty
Cycle Control at Gnd, VOO = 3V,
Unused Inputs Open, Outputs
Open
functional description
A block diagram of the MMS811S direct drive digital
watch is shown in Figure 1. The chip pad layout is
shown in Figure 2 and package connection diagram
in Figure 3.
load capacitance required for precise tuning of the
quartz crystal. The network shown in Figure 4 provides
greater than 100 ppm tuning range when used with
standard X-Y flexure quartz crystals trimmed for CL =
12 pF and a S-36 pF trim capacitor. If digital tuning
is used, the tuning range is· ±114 ppm and no trim
capacitor is required.
Time Base: The precIsion time base of the watch is
provided by the 32,768 Hz crystal controlled oscillator,
which consists of quartz crystal, a CMOS inverter/
amplifier and the RC network shown in Figure 4.
Resistor R 1 biases the inverter for class A amplifier
operation. Resistor R2 (a) reduces the voltage sensitivity
of the network; (b) limits the power dissipation in the
quartz crystal; and (c) provides added phase shift for
good start-up and low voltage circuit performance.
Capacitors Cl and CEFF in series provide the parallel
16.0
63.2
DIG I
DlG2
97.2
Cap 1: This pin is used with Oscillator Out to add more
capacitance to the oscillator RC network shown in
Figure 4.
Cap 2: This pin is used with Oscillator In to form the
RC network shown in Figure 4 if the digital tuning is
to be used.
130.0143.0
140.1
40
SEGMENT B
128.2
VSS
119.7
DIG 3
111.7
DIG 4
103.7
4096Hz
95.7
8SEC
87.3
PI
79.3
P2
----178.0----
47.1
AID
31.1
CAPI
CAP
I
DIM
OSC
IN
I
4 Hz
TEST
FRED
DT
CYCLE
I
9.7
SEGMENT A
SEGMENT 0
NC
NC
LAMP
NC
SET/DISPLAY
CYCLE
NC
SEGMENTC
HRiMlN
SEGMENT E
NC
OIGITZ
NC
61.1
DUTY CYCLE CONTROL
DIM
DIGITI
Vss
DIGIT 3
38.1
DIGI14'
CAPI
4096Hz
AID
BSECONDS
8 Hz
TEST
I
HRI
MIN
15.2
CYCLE
SET
126.6
137.6
PI
PI
P2
P4
LAMP
O-~I~-+-+-+-+~-------+~+---r--+--+---~ - 0
o
SEGMENTG
SEGMENT I
"j'
39.1
101.2
85.8
I
P8
DSC
OUT
VOD
MM58115
NOT TO SCALE
OIMENSIONS TO CENTER OF PADS
(ALL PADS ARE 5.0 X 5.0 MIL MINIMUM)
P4
67.3
117.0
SEGMENTF
SEGMENTH
VDD
TOP VIEW
FIGURE 3_ Connection Diagram
151.5
FIGURE 2_ Pad Layout
7-34
functional description
(Continued)
Display Control: The TIME and DATE display sequence
is controlled by normally open switches connected to
SET/DISPLAY, and HOUR/MINUTE (inertial switch)
inputs. With the display "OFF," depressing the SET/
DISPLAY switch will activate the HOUR-MINUTE
display. This display will remain "ON" for 1.25 seconds
±0.125 seconds. If the switch is still held in at the end
of this time out, SECONDS will be displayed blinking
"ON" for 0.25 seconds and "OFF" for 0.75 seconds
until the SET/DISPLAY switch is released. If during the
HOUR-MINUTE display, the SET/DISPLAY switch is
released and depressed a second time, the date will be
displayed as DAY-DATE. The DAY-DATE display will
remain "ON" for 1.25 seconds ±0.125 seconds and turn
"OFF" automatically if the SET/DISPLAY switch has
been released. Holding the SET/DISPLAY switch past
the display time out will cause the watch to display
MONTH-DATE information until the SET/DISPLAY
switch is released or until the SET/DISPLAY switch has
been depressed longer than 2.0 seconds 1:0.125 seconds.
If held longer than 2 seconds, the MONTH-DATE display will return to DAY-DATE display. MONTH-DATE
and DAY-DATE display will continue to alternate
until the SET/DISPLAY switch is released. DAYDATE will be displayed for 1.25 seconds and MONTHDATE will be displayed for 0.75 seconds before the
sequence starts to repeat. TIME may also be displayed
in the MM58115 by activating the HOUR/MINUTE
input. The HOUR/MINUTE input is used with an
inertial switch that is normally open. Closing the switch
activates the HOUR/MINUTE display. This display will
remain "ON" for 1.25 seconds ±0.125 seconds and then
turn "OFF" automatically.
Time Setting: The setting sequence is controlled by a
normally open switch connected to the Cycle Input.
Depressing the CYCLE switch will advance the watch to
the next set mode. Figure 5 is a flow diagram showing
the display and set functions for the MM58115.
Set Hour Mode: With the watch in the normal Run
mode and the display "OFF," depressing the CYCLE
switch will put the watch into the Set Hour Mode.
In this mode, HOURS wil'l be displayed in digit positions
1 and 2 followed by the colon. An A or a P will be
displayed in digit position 4 to indicate AM or PM,
respectively. Depressing the SET/DISPLAY switch will
advance the HOURS counter at a 2 Hz rate. If neither
the SET/DISPLAY switch nor the CYCLE switch are
r - - -.....;.;.;.~}-....~
depressed for 5.25 seconds ±0.125 seconds, the watch
will automatically return to the Run mode. Depressing
the CYCLE switch while in the Set Hours mode will
advance the watch to the Set Minutes mode.
Set Minutes Mode: The Set Minutes mode will display
minutes in digit positions 3 and 4 preceded by the colon.
Depressing the SET/DISPLAY switch while still holding
in the CYCLE switch will enable the hold flag but will
not allow advancement of the MIN UTE counter. Depressing the SET/DISPLAY switch after the CYCLE switch
has been released resets and holds the SECOND counter,
enables the hold flag, and advances the MINUTE
counter at a 2 Hz rate. If neither switch is depressed for
5.25 seconds ±0.125 seconds while the watch is in the
Set Minutes mode, the watch will automatically return
to the Run mode if minutes have not been set. Depressing
the CYCLE switch while in Set Minutes mode will
advance the watch to the Set Day Mode.
Set Day Mode: The Set Day mode will display DAYOF-THE-WEEK in digit positions 1, and 2. Depressing
the SET/DISPLAY switch while in the Set Day mode
will advance the DAY counter at a 2 Hz rate. If neither
switch has been depressed for 5.25 seconds ±0.125 secconds while in the Set Day mode, the watch will auto-matically return to the Run mode if the hold flag was
not set or will jump to the Hold mode if the hold flag
was'set. Depressing the CYCLE switch while in the Set
Day mode will advance the watch to the Set Date mode.
Set Date Mode: The Set Date mode will display DATE
in digit positions 3 and 4. Depressing the SET/DISPLAY
switch while in the Set Date mode will advance the
DATE counter at a 2 Hz rate. If neither the SET/
DISPLAY nor the CYCLE switches have been depressed
for 5.25 seconds ±0.125 seconds while in the Set Date
mode, the watch will automatically return to the Run
Mode if the hold flag was not set. Depressing the CYCLE
switch while in the Set Date mode will advance the
watch to the Set Month mode.
Set Month Mode: The Set Month mode will display
MONTH in digit positions 3 and 4 and an M in digit
position 1. Depressing the SET/DISPLAY switch while
in the Set Month mode will advance the MONTH counter
at'a 2 Hz rate. If neither the SET/DISPLAY nor the
cycle switches have been depressed for 5.25 seconds
±0.125 seconds while in the Set Month mode, the watch
-+ TO COUNTERS
~}-...
Cl
6-36 pF
....;.;.;..;..;.c>-....- i ">Q-..... TO COUNTERS
R1
200k
T
Note 1.32,768 Hz anti-resonant quartz crystal, CL = 12 pF
BPF
Vss
FIGURE 4(a)_ Oscillator RC Network
FIGURE 4(b). Oscillator RC Network If Digital Tuning is Used.
7-35
functional description
(Continued)
Contact Bounce: Debounce circuitry is provided on the
SET/DISPLAY, CYCLE, and HOUR/MINUTE inputs to
remove any logic uncertainty upon either closure or
release of the switches. 100 ms debounce protection is
provided for SET/DISPLAY and CYCLE inputs and
200 ms protection is provided for the HOUR/MINUTE
input.
will automatically return to the Run mode if the hold
flag' was not set, or will advance to the Hold mode if
the hold flag was set. Depressing the Cycle switch while
in the Set Month mode will advance the watch to the
Hold mode if the hold flag was set; otherwise, the watch
will advance to the Run mode.
Hold Mode: In the Hold mode the SECOND counter is
held at 00, and the HOUR-MINUTE display will blink
"ON" for 0.25 seconds and "OFF" for 0.75 seconds.
Depressing the SET/DISPLAY switch will place the
watch in the display HOUR/MINUTE mode for 1.25
seconds ±0.125 seconds. Depressi ng the Cycle switch
. while in the Hoid mode will advance the watch to the
Set Hour mode. There is no roll-over of the next higher
counter while a counter is being set at a 2 Hz rate.
Month
Date."
ruary,
and 31
Display MUltiplexing: The counter data selected to be
displayed is time-division multiplexed to provide digitsequential presentation to the LED display. This reduces
the number of outputs required to drive the 4-digit
display to thirteen (9-segment drivers and 4-digit drivers) .
The display font is shown in Figure .6. Figure 8 is a
schematic diagram of a typical LED watch using the
MM58115 watch, chip. The segment and digit drivers
are designed to interface directly with the LED display.
The four digits of the LED display are multiplexed with
a 23% duty cycle, 1024 Hz signal during the display
period. The digit drivers are disabled for 3211S at the
beginning of each digit enable time to allow the segment
Counter: The MONTH counter provides "smart
The DATE counter will count 28 days in Feb30 in April, June, September and November,
in the remaining months.
r+L-~~~~~L-~~
I
I
L~D -+
~--~--~
HOURS
OAY
COLON
~------~
MINUTES (SECONDS)
OATE (MONTH)
R ""'""
SET MINUTES
SET DAY
2B
SID = SET IOISPLA Y
-
-
HIM = HOURIMINUTE
C = CYCLE
=TIME·OUT ROUTE
Oil[]
SET DATE
SET MONTH
DD
HOLD
FIGURE 51b). Set Display Font
FIGURE 5lal. MM58115 Flow Diagram
7-36
functional description
(Continued)
decoding circuitry adequate time to switch to the next
digit's information. This eliminates the possibility of
"ghosting" information between digits.
Duty Cycle Control: The Duty Cycle Control Input is
used with the Dim Input to determine the intensity of
display. The dutY cycle range is shown in Figure 7.
Digital Tuning: To digitally tune the time base, A/D,
Pl, P2 P4 and P8 inputs are used. A/D input either
adds or deletes pulses into the counter chain. P1, P2,
P4 and P8 inputs determine the number of pulses to
be added or deleted from the counter chain in a specific
time period. Each pulse added or deleted "tunes" the
time base by 7.6 ppm. An 8-second output pad is
provided to easily check the time base frequency. When
A/D is open (internal pull-down to VSS) or at VSS,
pulses are deleted. If A/D is tied to VDD, pulses are
added into the counter chain. Pl, P2, P4 and P8 inputs
have internal pull·downs to VSS, which is a logical "D."
When these inputs are tied to VDD, they are at a logical
"1." Table I shows the tuning range for each input code.
If the Digital Tuning scheme is not used, leave all inputs
open.
Colon Output: Colon information is present on the
"h" and "i" segment outputs during digit position 4.
Dim Input: The Dim Input is a 2·level input. This input
has a pull-down to VSS to hold it normally at a logical
"0." In this condition with Duty Cycle Control at VSS
the display will normally, be at maximum intensity.
With the Dim input at VDD, the display will be at
3/7 of the full intensity. If the Dim input is at VDD
and the Duty Cycle Control input is at VSS; maximum
intensity will be 3/7 of full intensity. With the Dim
input at VDD, the display intensity will be reduced to
1/7 of' full intensity. Figure 7 shows the switching
threshold ranges for the Dim Input.
u2Eiil15b
/JOdJOdJOu
o O~O V 0=0
c..-=
o 0Dc=J
D o 0
D 0c=J0
D40fb
Dc=J 0 0 ODOOU
::OOc=JO o 0[60
SUNDAY
CO
D
TUESDAY
MONDAY
OJ
0V
O:JJ
c=J(l
O~O
c=JU
.
JL-~
FPo
.. FRIDAY
THURSDAY
SATURDAY
WEDNESDAY
,
A
Fil~DB
ED~Dc
FIGURE 6. Display Font
21.875% DUTY CYCLE
9.375% DUTY CYCLE
3.125% DUTY CYCLE
ill"--_________....Jrl
90'5~sj ~I~
-
I
30.5~s
213.6~s_t-~_I_----976.5~s----
\
DUTY CYCLE CONTROL
DIM INPUT
VSS
> VDD - D.5V
< VSS + D.3V
> VDD - D.5V
< VSS + D.3V
VDD
DlSPLA Y TIME/DIGIT
Low Ambient Light
21.875%
High Ambient Light
3.125%
Low Ambient Light
9.375%
High Ambient Light
FIGURE 7. Dim Input Levels
7-37
DISPLA Y CONDITION
9.375%
s:
s:CJ'1
CO
CJ'1
functional description
(Continued)
TABLE I. Digital Tuning Table
Test Points: Five pads are provided for test purposes.
8 Seconds: This output is used with A/D, Pl, P2, P4
and P8 to digitally tune the time base frequency.
P2
P4
P8
a
a
a
a
a
a
a
a a
a 7.63
a 15.26
a 22.89
a 30.52
a 38.15
a 45.78
a 53.41
1
4096 Hz: This pad outputs a 4096 Hz signal that can be
used for oscillator tuning.
4 Hz/Test Frequency: This is an input/output pad
under the control of the Test input pad. When "Test"
is at a logical "a," the 4 Hz/Test Freq pad becomes an
input and any frequency connected to it will replace
the normal internal 4 Hz signal. This feature is provided
to allow high speed functional· testing of the watch
system. When "Test" is open or at a logical "1," a 4 Hz
output will appear on the 4 Hz/Test Freq pad.
Test: This pad is used as an input to control the 4 Hz/
Test Freq pad. An internal pull·up resistor will normally
hold "Test" at a logical "1." Changing the Test input
from a logical "1" to a logical "a" will generate a reset
pulse which will set the internal counters to 1 AM on
Sunday, January the first. The watch is now in a known
state for testing.
M(ppm)
P1
a
1
1
1
a
1
a
a
a
1
1
1
1
1
a
a
a
a
1
a
a
a
a
1.
1
1
83.92
1
1
91.55
99.18
1
1
61.04
1
68.57
1
76.29
1
1
a
1
a
a
1
1
a
1
1
1
106.81
1
1
1
1
' 114.44
AID is 1 to add to frequency
AID is 0 to slow down frequency
Procedure: Monitor 4096 Hz output,
determine frequency shift desired,
bond AID, P1, P2, P4, P8 to the correct
code. 8 second pad will be at the correct
frequency.
Lamp: When the Lamp input is at a logical "a," all
segments of the display will be forced to an "ON"
condition under control of the normal 23% duty cycle
of the digit drivers. An internal pull·up resistor will
normally hold the Lamp input at a logical "1."
Vss
Voo~
h
- "''"' ' '
lSV
....1-
lSV
....1-
I
I
CYCLE
VSS
OUTY CYCLE CONTROL
SOOk <20%
VOO
~~r
NS IL
~
/(/
BETA
240-360
OIM
'-""~
VOO OR
VSS
iJ
SEGMENT ENABLE
~ OSC OUT
DD{) DoD
D~D D~D
1
0
\
CAP
J
NSC 9101
ENABLE
-r-
VSS
0
OIGIT
MM5B11S
O~C IN
ilc=JD ilc=JD
A
B
C
0
I-I-f---
0::0 0::0
r r
14
FIGURE 8(a). System Schematic for MM58115 LED Watch
7·38
E
F
G
H
I
{'
2
~
r--r--t--
functional description
(Continued)
V00+-:L
h
d
Vss
VOO
h
- """~'"
15V
--1-
15V
--1-
VSS
P4
-
CYCLE
j=
CAP 2
AID
DUTY CYCLE CONTROL
l=L __
NSC 9101
flaO flaO
ogo ogo
I
I'
0
fl~O
SEGMENT ENABLE
OSC OUT
I
CAP I
fl~O
\
E
F G H I
r--
-
0::0 0::0
r
\4
FIGURE 8Ib). System Schematic for MM58115 Digitally Tuned LED Watch
7·39
{'
2-
J-
4 -
A B C 0
0
DIGIT
ENABLE
MM5B115
OSC IN
Watches
en
..ex)
Ln
~
~
MM58117, MM58118, MM58119, MM58120 LCD watch circuits
general description
The fI.(IM58117, MM58118, MM58119, and MM58120
are low threshold voltage, ion implanted, metal-gate
CMOS integrated circuits that provide or control all
signals needed for a 3-1/2 digit LCD watch. The circuit
time base is a 32,768 Hz crystal controlled oscillator.
This time base frequency is counted down to provide
proper signals to display Hours-Minutes information
continuously with Month-Date or Seconds information
available upon demand. Time is displayed in 12 hour
format. 23 phase controlled outputs are available for
direct drive of a 3-1/2 digit liquid output display (LCD).
The 32 Hz output serves as the backplane drive for the
LCD. All four parts operate on a single 1.3-1.7V supply.
An on-chip voltage multiplier using external capacitors
is used to provide the drive voltage for the display.
The MM58117 and MM58118 have on-chip voltage
doublers which provide 2.5V minimum at 1,uA load
current. The MM58119 and MM58120 have on-chip
voltage triplers which provide 3.8V minimum at 1,uA
load current. Alternatively; the MM58117 and MM58119
provide a 256 Hz output pulse and the MM58118 and
MM58120 provide a 1024 Hz output pulse that can be
used to drive an inductive up-converter off chip. The
Regulate input can be used to suppress this output
. block diagram
pulse to regulate the voltage generated. The Regulate
pad is not present on the MM58117, MM58119 versions.
A Test input can be used to convert the 32 Hz output
into an input for testing the divider circuitry at a higher
frequency. All four parts are available as unpackaged
die suitable for hybrid assembly or in 40-lead dual-in-line
packages for evaluation purposes.
features
•
Direct 'Continuous LCD drive capability
•
•
32,768 Hz crystal controlled operation
Single 1.5V battery operation
•
Low power dissipation
•
3-1/2 digit, 12 hour display
•
•
4 year calendar
Seconds, Month, and Date display upon demand
•
Colon display
•
Simple 2 button sequential setting
•
•
Auto reset feature (MM58118 and MM58120)
On-chip' capacitive voltage mUltiplier
•
Regulated bipolar drive also available (MM58118,
MM58120)
32 Hz/BACKPLANE 110
TEST
VOLTAGE
MULTIPLIER
---OVOO
STOPo--4>--_--r...L---'--~f_--------+-----+_-----1
---OVSS
SET/DISPo-----.i
1-+-------'----t-------t-----t------oCOlON
..J
CYClEo----+L..,....._ _ _
nSEGMENT
OUTPUTS
FIGURE 1 .
7-40
absolute maximum ratings
Voltage at OSC IN, OSC OUT, 256/1024 Hz
Regulator., Set/Oisplay, Cycle, Stop, Phase 3
Voltage at Any Other Pin
Operating Temperature Range
Storage Temperature Range
VOO - VEE
VOO - VSS
Lead Temperature (Soldering, 10 seconds)
VOO+0.3y to VSS-D.3V
VOO+0.3V to VEE-D·3V
-5°C to +70°C
-25°C to +85°C
8.0V
3.0V
300°C
electrical characteristics
T A within operating range, VOO - VSS
= 1.5V, VOO
- VEE
= 4.5V
unless otherwise noted.
CONDITIONS
PARAMETER
MIN
TYP
MAX
UNITS
Oscillator Start Voltage
T A = 25°C, (Note 1)
1.4
V
Oscillator Sustaining Voltage
T A = _5°C, (Note 1)
1.3
V
Input Voltage Levels
Set/Oisplay, Cycle
VOO-0.25
Logical "1"
Logical "0"
VOO
Open
Internal Pull Oown to VSS
V
V
BP/32 Hz Input
Logical "1"
VOO-0.25
Logical "0"
VEE
VOD
VEE+0.25
V
Voo
V
V
Test, Stop
Logical "1"
Internal Pull Oown to VEE
VoO-0.25
V
Open
Logical "0"
Input Current Levels
Set/Oisplay, Cycle
VIN = VOO
Test
VIN = VOO
10.0
15 .
pA
Stop
VIN = VOO. VEE = VSS + 0.3V
0.5
pA
f= 1 MHz, VIN = OV
5
pF
I nput Capacitance
OSC IN,
0.2
J1A
All Other Pads GNO
Output Voltage Levels
Segment Orivers
Logical "1"
VOUT = VOO - 0.2V, VOO - VEE = 3V
4
J1A
Logical "0"
VOUT = VEE + 0.2V, VOO - VEE = 3V
4
J1A
Logical "1"
VOUT = VOO - 0.2V, VOO - VEE = 3V
VOUT = VEE + 0.2V, VOO - VEE = 3V
40
40
pA
Logical "0"
Logical "1"
VOUT = VOO - 0.2V, VOO - VSS = 1.5V
30
pA
Logical "0"
VOUT = VSS + 0.3V, VOO - VSS = 1.5V
300
pA
BP/32 Hz Output
J1A
256/1024 Hz
Output Current Levels
VOO - VSS = l.4V, VOO - VEE = 4.2V .
Phase 3
Logical "1," Source
VOUT = VOO - 0.25V, Phase 2 < 1.5 ms
7.5
pA
Logical "0," Sink
VOUT = VSS + 0.25V
35.0
pA
pA
CAP1
Phase 1, Source
VOUT = VOO - 0.25V
7.5
Phase 2, Sink
VOUT = VSS + 0.25V
20.0
Phase 3, Leakage
VOUT = VOO - 3.0V
J1A
0.6
pA
CAP2
Phase 1, Sink
VOUT = VSS + 0.25V
Phase 2, Leakage
VOUT = VEE + 1.5V
VEE
Phase 3, Sink
pA
35.0
0.6
CAP 2 = VOO - 4.2V,
250
VOUT = VOO - 3.95V
7-41
pA
pA
o
N
-
ex)
In
~
~
electrical characteristics
(Continued) TA within operating range, VOO - VSS
r
PARAMETER
Supply Current (lDD)
MIN
TYP
MAX
UNITS
3.0
5.0
. J.lA
6.0
8.0
J.lA
0.2
1.0
J.lA
VDD-O.4
VOD-l.l
V
13
17
= 25°C, lEE = lJ.1A, f = 32,768 Hz,
= 1.5V
A
Doubler Operation
= 1.5V, VOO - VEE = 4.5V unless otherwise noted.
. CONDITIONS
VDD
Tripier Operation
Voltage Regulator Input Current
= VDD = 25°C
VIN
TA
Voltage Regulator Switching
r
Threshold
256/1024 Hz Pulse Width
0.75} MM58118, MM58120
Only
J.ls
A = 2SoC, C = D.047.F,
Supply Voltage (VEE)
lEE
Doubler Operation
= lJ.1A, f = 32,768 Hz,
= 1.5V, (Figure 9),
VDD - VSS
Tripier Operation
(Note 1)
2.5
V
3.8
V
Note 1: I i1 oscillator network shown in Figure 4.
functional description
A block diagram of the Watch Chip is shown in Figure 1.
A chip pad layout is shown in Figure 2 and a package
The MM58117 and MM58118 contain an on·chip
voltage doubler for display drive and the MM48119 and
MM48120 contain an on-chip voltage tripler.
connection diagram in Figure 3.
169.5
147.1
118.7
90.3
61.9
61.9
42.2.
0
4F
3F 3A
2B 3G
---176MILS--34.S
02'S6Hz
43.8
OVEE
490
15.7
SETIDISPO
23.2
VssO
32.0
1
177MILS
73.8
o VEE
o DSC OUT
66.3
81.4
OOSCIN
88.4
OfHJmJ
100
OCAP2
I
o
0
'0
4AO 8.3
VDDO
45.2
VssO
52.5
STOP 0
'DEVICE NO. MM48117
MM48119
'ALL PADS ARE 4.5.4.5 MIL
EXCEPTVssls.O.4.SMIL)
'OIMENSIONS TO CENTER OF PAD
142.1
70.3
8.3
o
04A
2A 2F 2G
4F
13.704B
23.2
OSET/DISP
32.0
45.2
OVss
OVDD
::::
~ ~~~P
_--176MILS--_
1
lq24HzO
34.5
REGO
43.8
VEEO
17TLS
60.2
'DEVICE NO. MMS8118
MMS8120
'ALL PADS ARE 4.5.4.5 MILS
EXCEPTVSsI5.SMILS)
'DIMENSIONS TO CENTER OF PAD
8CAPI
145.4
OBPilZHz
TEST 0
137.2
CYCLED
146.2
'137.2
73.8
DSCIN 0
81.4
VEE 0
89.3
PimnO
146.2
o TEST
o CYCLE
66.3
OSC OUT 0
120.6
127.0
169.5
42.2
or'------~--_r~--~-+--~~--+-+_~
92.0
CAP20
115.3
CAP10
127.0
BP/32 Hz 0
145.4
4E 3C
3D 3E
COLON 2C
20 2E
18/1C
4C 40
DO
DO
DO
DO
0
DO
177,!-_r~--+-+---~~----+-I---!~--_r~, 177
176
0
170.9
142.5
114.0
72.9
41.8
17.9
17.9
114.0
41.8
FIGURE 2(a)
MM58117N, MM58119N
NC
2b
•
40
39
MM58118N, MM58120N
3g
31
31
3.
38
2.
142.5
FIGURE 2(b)
•
3b
21
49
29
41
NC
4.
256Hz
VEE
4.
4b
4b
SET/DISPLAY
SET/DISPLAY
CAPZ
TEST
CAP 1
CYCLE
TEST
CYCLE
32 Hz/BACK PLANE
4e
lb/le
4d
Z.
4.
2d
2e
21
COLON
3.
ZI
3.
TOP VIEW
TOPVIEW
FIGURE 3(a)
FIGURE3(b)
7-42
COLON
170.9
functional description
(Continued)
~ ~~~
Time Base: The precision time base of the watch is provided by connecting a crystal controlled RC network to
the on-chip CMOS inverter/amplifier as shown in Figure
4. For proper operation, the network should be tuned to
32,768 Hz. Resistor R 1 is used to bias the on-chip inverter for class A amplifier operation. Resistor R2 is
used to (a) reduce the voltage sensitivity of the network;
(b) limit the power dissipation in the quartz crystal; and
(c) provide added phase shift for good start-up and low
voltage circuit performance. Capacitors C 1 an.d C2 in
series provide the parallel load capacitance required for
precise tuning of the quartz crystal. The network shown
in Figure 4 provides greater than 100 ppm tuning range
when used with standard X-Y flexure quartz crystals
trimmed for C L = 13 pF. Tuning to better than 2 ppm is
easily obtainable.
~ ~:~
~
HOURS
MONTH
0
0
~~~ ~~~
~:~ ~:~
\
COLON
3
4,
MINUTES (SECONDS)
DATE
FIGURE 5. Time Display
Leading zero values of month, date, and hours are
blanked. The circuit contains a 4, year calendar which
will automatically reset the Date Counter to 1 and
advance the Month Counter at the end of each month
(except for February in Leap Year). The character display font is shown in Figure 6.
CMOS INVERTER
OSC IN
-~r-
- -
OSC OUT
----~>-AI
20M
R2
lOOk
T.
--CI
P
45 F
FIGURE 6. Character Display Font
' - - - - - - - - -..... voo OR Vss
SETTING CONTROL
FIGURE 4. Crystal Oscillator Network
The 256/1024 Hz output or the 32 Hz output can be
used to monitor the oscillator frequency during initial
tuning without disturbing the network itself.
A normally open switch connected to the Cycle input is
used in conjunction with the Set/Display switch to set
Month, Date, Hour, Minute, and synchronize Second
information.
DISPLAY CONTROL
MM58118, MM58120
The Hour:Minute, Month Date, and Second displays are
controlled by a normally open switch connected to the
Set/Display input. Month and Hour are displayed in digit
positions 1 and 2. Date, Minute, and Second are displayed in digit positions 3 and 4.
Hour: With the watch in the display mode, depressing
the Cycle switch will put the watch in the Set Hour
mode. In this mode the Hour will be displayed in digit
positions 1 and 2 followed by the colon and either an A
or a P (for AM or PM) displayed in digit position 4.
While in this mode depressing the Set/Display switch will
advance the Hour Counter at a 1 Hz rate until the Set/
Display switch is released.
The circuit will normally display Hour and Minute with
the colon flashing at a 1 Hz rate (Figure 5). Depressing
the Set/Display switch will cause Month and Date to be
displayed with no colon. The display will automatically
return to Hour and Minute display 2.25 ±0.25 seconds
after the Set/Display switch has been released. Depressing the Set/Display switch a second time while the
Month and Date are being displayed will cause the
Second to be displayed until the Set/Display switch is
again depressed, returning the display to Hour and
Minute.
Minute: Depressing the Cycle switch while the watch is
in the Set Hour mode will advance it to the Set Minute
mode. In this mode the Minute will be displayep in digit
positions 3 and 4 preceeded by the colon. Depressing the
Set/Display switch while still holding the Cycle s~itch in
will cause the Hold mode to be activated but will not
advance the Minute counter. Depressing the Set/Display
switch after the Cycle switch has been released will cause
the Hold mode to be activated and will advance the
Minute counter at a 1 Hz rate as long as the switch is
held in.
The MM58117 and MM58119 have an additional display
mode that can be used by depressing the Cycle switch
while the watch is in the first display mode described
above. The second display mode will alternately display
Hour:Minute and Month Date for a period of 2 seconds
each. Depressing the Set/Display switch will cause the
Second to be displayed. Depressing the Set/Display
switch again will return the watch to the second display
mode.
Month: Depressing the Cycle switch while the watch is
in the Set Minute mode will advance it to the Set Month
mode. In this mode the Month will be displayed in digit
positions 1 and 2 with no colon. Depressing the Set/
Display switch will cause the 'Month counter to be
advanced at a 1 Hz rate as long as the switch is held in.
7-43
functional description
(Continued)
MM58117, MM58119
Date: Depressing the Cycle switch while the watch is in
the Set Month mode will advance it to the Set Date
mode. In this mode the Date will be displayed in digit
positions 3 and 4 with no colon. Depressing the Set/
Display switch will cause the Date counter to be advanced
at a 1 Hz rate as long as the switch is held in.
The MM58117 and MM58119 setting procedure is
similar to that of the MM58118, except that the setting
sequence is as follows:
1. Set Month
Hold: If the Hold mode was activated while in the Set
Minute mode, depressing the Cycle switch while in the
Set Day mode will advance the watch to the Hold mode.
In this mode Hour:Minute will be displayed flashing at a
1 Hz rate. The Second counter will be held at 00.
Depressing the Set/Display switch will advance the
watch to the normal run mode with Month:Date dis·
played and release the Second counter to begin normal
operation. Depressing the Cycle switch will place the
watch in the Set Hour mode with the Hold mode still
activated. If the Hold mode was not activated while in
the Set Minute mode, depressing the Cycle switch while
in the Set Date mode will advance the watch to the Run
mode with Hour:Minute displayed.
2. Set Date
3. Set Hour
4. Set Minute/Hold
There is no 5.25 second time-out while in the setting
mode and the watch will stay in each set mode until it is
advanced to the next mode. The Cycle switch is used to
advance from the Set Minute state to the first display
state. The colon will blink on and off while time is
being displayed unless the Hold mode is activated,
forcing the colon to remain on continuously. During the
second display mode, the colon will remain on during
time display. Depressing the Set/Display switch while in
either one of the two display states will cause the Hold
mode to be cleared, allowing the watch to begin normal
operation.
While in any of the above set modes if no switches are
activated for 5.25 ± 0.25 continuous seconds the watch
will automatically jump to the Hold mode if it was activated in the Set Minutes mode or to the Run, mode if the
Hold mode was not activated. There is no roll over of
the next higher counter while a counter is being set. For
example, while in the Set Minute mode, advancing the
Minute counter from 59 to 00 will not advance the Hour
counter.
OISP
MONTH
DATE
f--.
_
Control state diagrams for the MM58117, MM58118,
MM58119 and the MM58120 are provided in Figure 7.
L-_ _ _.....
SET
HOUR
SET
DAY
-
-
-
... Automatic time-out routes
~Usercontrolledroutes
FIGURE 7(a). MM58118, MM58120 Control State Diagram
FIGURE 7(b). MM58117, MM58119 Control State Diagram
7-44
functional description
(Continued)
Stop I nput: This input pad has an internal resistor to
V EE holding it normally at a logical "0." A logical "1"
at stop will force all of the display segments "OF F"
and stop the oscillator, placing the watch in a static
mode to decrease power dissipation during extended
periods of storage.
coil or transformer, generates the higher voltage needed
for the display. A typical circuit is shown in Figure 9.
The output waveform is shown in Figure 10. The
MM58118, MM58120 provides a 1024 Hz output pulse
while the MM58117, MM58119 provides the 256 Hz
output pulse.
Contact Bounce: Debounce circuitry is provided on the
Set/Display and Cycle inputs to remove any logic
uncertainty upon either closure or release of switches
provided switch bounce settles within 20 ms.
Voltage Regulator: The Regulator input is used in conjunction with a zener diode to shut-off the 1024 Hz
output to regulate the level of the VEE supply voltage.
The Regulator input is provided on the MM58118 and
MM58120 only.
~
~
U1
Segment Outputs: The Segment outputs are designed
to drive field-effect liquid crystal displays. Each display
segment has its own output which furnishes the proper
32 Hz drive signal. By definition, the segment is "OFF"
when its drive signal is in phase with the display backplane signal (BP/32 Hz). The segment is "ON" when its
0
drive signal is 180 out of phase with the display'backplane signal. Typical output waveforms are shown in
Figure 8.
Test Pads: Two pads are provided for test purposes.
(X)
U)
BP/32 Hz: This input/output pad is under the control of
Test. When Test is open or at a logical "0," a 32 Hz
'signal is provided on BP/32 Hz which can be used to
drive the backplane of the LCD unit or to monitor the
oscillator frequency without affecting the oscillator circuitry. If Test is at a logical "1," the BP/32 Hz pad is
converted into an input and any frequency connected to
it will replace the normal internal 32 Hz signal. This
feature is provided to allow high speed advancement of
the internal counters for testing purposes.
Colon Output: The Colon output provides a 32 Hz
phase controlled signal identical to the segment outputs.
The colon will blink at a 1 Hz rate during time display
mode (except for display mode one with the Hold
mode activated, and display mode two in the MM58117,
MM58119) and remain on continuous while displaying
time (Hours or Minutes) during the setting operation.
Test: This input pad is used to control the BP/32 Hz pad
as described above. When the Test pad is at a logical "1,"
the phase-control is disconnected from the segment drive
outputs and the segment information will be referenced
to a logical "0" backplane. Switching the Test pad from
a logical "0" to a logical "1" generates a reset pulse that
will reset the watch counters to 1 AM on January the
first. This places the w~tch into a known state for testing
purpose.
VOLTAGE MULTIPLIER OUTPUTS:
256/1024 Hz: The 256/1024 Hz pad is provided to
drive a bipolar transistor which, in conjunction with a
VOO
COMMON
VOO
SEGMENT
1--- ---11-OFF
........
----ON---.. I
FIGURE 8. Common and Segment Output Signals
7-45
~
~
U1
....
N
(X)
o
functional description
(Continued)
20M
5-36 pF
en
.....
.....
CX)
It)
:E
:E
CX)
.....
.....
250k
OSC IN
. - - - - - - - - t PHASE 3
CAP 2
' - - - -....--tCAP 1
VEE
BACK PLANE
CX)
It)
SEGMENTS
:E
:E
~
~ ~:~
~c=J~
0
0
a
~c=J~
~~~
~:~ ~~~
3·1/2
DIGIT
LCD
2
1
~
COLON
HOURS
*(For
doubler, connect
single O.05J.1F capacitance
between Phase 3 and Cap 2)
MINUTES
(SECONDS)
"ON" CHIP TRIPLER
20M
5-36 pF
250k
VDD
VSS
DSC IN
REGULATE
SET/DISP
MM58118,
MM58120
ONLY
VEE
CYCLE
=!=d
VDD
VSS
256/1024 Hz
BACK PLANE
SEGMENTS'
---VDD
~
~ ~:~
~c=J~
1
0
0
~c=J~
a
m~~~~
~:~ ~~~
3·1/2
DIGIT
LCD
2
~
HOURS
COLON
MINUTES
(SECONDS)
"OFF" CHIP MUL TlPLIER
FIGURE 9. Typical Application of MM58117, MM58118, MM58119 and MM58120 in LCD Watch System
Vee
V~
----=u
-
u
151's
--±2I's
.
1024 Hz (MM58118, MM58120)
256 Hz (MM58117. MM58119)
FIGURE 10.1024 Hz Output
7-46
Watches
MM58127, MM58128, MM58129, MM58130 LCD watch circuits
general description
The MM58127, MM58128, MM58129, and MM58130
are low threshold voltage, ion implanted, metal-gate
CMOS integrated circuits that provide or control all
signals needed for a 3 1/2-digit LCD watch. The circuit
time base is a 32.168 Hz crystal controlled oscillator.
Oscillator RC network components are included on
the circuits_ The time base frequency is counted down to
provide proper signals to display Hours-Minutes information continuously with Month-qate or Seconds information available upon demand. Time is displayed in 12-hour
format. 23 phase controlled outputs are al/ailable for
direct drive of a 3 1/2-digit liquid output display (LCD).
The 32 Hz output serves as the backplane drive for the
LCD_ All 4 parts operate on a single 1.3-1.7V supply.
An on-chip voltage multiplier using external capacitors
is used to provide the drive voltage for the display.
All circuits have an on-chip voltage doublers which
provide 2_5V minimum at 1 p.A load current or voltage
triplers which provide 3.8V minimum at 1 p.A load
current. A Test input can be used to convert the 32 Hz
output into an input for testing the divider circuitry at
a higher frequency. AI14 parts are available as unpackaged
die suitable for hybrid assembly or in 40-lead dual-inline packages for evaluation purposes.
features
•
Direct continuous LCD drive capability
•
32.168 Hz crystal controlled operation
•
Single 1.5V battery operation
•
Low power dissipation
•
3 1/2-digit, 12 hour display
•
4 year calendar
•
Seconds, Month and Date display upon demand
•
Colon display
•
Simple 2 button sequential setting
•
On-chip oscillator RC network
•
On-chip capacitive voltage multiplier
block diagram
32 Hz/BACKPLANE I/O
TEST
VEE
TRIPLE
CAP2
VOLTAGE
MULTIPLIER
FOUT
0-----..,
- - -....OVoo
STOPo-~~-~I---'----"l----------+------+---J
- - -....oVSS
OSC IN
OSC OUT 0--_..1
SET/OISPo-----+i
1-4---------i------.j-----+------<) COLON
J
CYCLEo-----+Jl..,._ _ _ _
2HEGMENT
OUTPUTS
FIGURE 1
·7-47
o
-
M
00
Lt)
~
~
absolute maximum ratings
Voltage at Osc. In, Osc. Out, FOUT
Regulator, Set/Display, Cycle, Stop, Double, Triple
Voltage at Any Other Pin
Operating Temperature Range
Storage Temperature Range
VOO - VEE
VOO - VSS
Lead Temperature (Soldering, 10 seconds)
VOO+0.3V to VSS-o.3V
VOO+0.3V to VEE-o·3V
-5°C to +70°C
-25°C to +85°C
8.0V
3.0V
300°C
electrical characteristics
T A within operating range, Voo - VSS = 1.5V, Voo - VEE = 4.5V unless otherwise noted.
MIN
CONDITIONS
PARAMETER
TYP
MAX
UNITS
Oscillator Start Voltage
T A = 25°C, (Note')
,.4
V
Oscillator Sustaining Voltage
T A = _5°C, (Note')
1.3
V
Input Voltage Levels
Set/Display, Cycle
Logical "'"
Logical "0"
VDD-0.25
VDD
Open
Internal Pull Down to VSS
V
V
BP/32 Hz Input
VDD-0.25
Logical "'"
Logical "0"
VEE
VDD
VEE+0.25
V
VDD
V
V
Test, Stop
Logical "'"
Logical "0"
Internal Pull Down to VEE
VDD-0.25
Open
V
I nput Current Levels
Set/Display, Cycle
VIN = VDD
Test
VIN = VDD
Stop
Input Capacitance
Osc. In,
0.2
'0.0
/lA
VIN = VDD, VEE = VSS + 0.3V
'5
0.5
/lA
f='MHz,VIN=OV
5
pF
/lA
All Other Pads Gnd
Output Voltage Levels
Segment Drivers
Logical "'"
Logical "0"
VOUT = VDD - 0.2V, VDD - VEE = 3V
4
/lA
VOUT = VEE + 0.2V, VDD - VEE = 3V
4
/lA
VOUT = VDD - 0.2V, VDD - VEE = 3V
40
I1A
VOUT = VEE + 0.2V, VDD - VEE = 3V
40
/lA
,30
I1A
BP/32 Hz Output
Logical "'"
Logical "0"
FOUT
Logical "'"
Logical "0"
Output Current Levels
VOUT = VDD - 0.2V, VDD - VSS = '.5V
VOUT = VSS + 0.3V, VDD - VSS = '.5V
300
/lA
VDD - VSS = ,.4V, VDD - VEE = 4.2V
Double, Triple
Logical "'," Source
Logical "0," Sink
< '.5 ms
7.5
I1A
VOUT = VSS + 0.25V
35.0
I1A
Cap. 1
Phase 1, Sou rce
VOUT = VDD - 0.25V
7.5
I1A
Phase 2, Sink
VOUT = VSS + 0.25V
20.0
Phase 3, Leakage
VOUT = VDD - 3.0V
VOUT = V.DO - 0.25V, Phase 2
/lA
0.6
J1A
Cap. 2
Phase " Sink
Phase 2, Leakage
VEE
Phase 3, Sink
35.0
VOUT = VSS + 0.25V
eap. 2
=
J1A
0.6
VOUT = VEE + '.5V
250
VOO - 4.2V,
VOUT = VDD - 3.95V
7-48 ."
J1A
J1A
electrical characteristics
(Continued)
T A within operating range, VOO - VSS = 1.5V, VOO - VEE = 4.5V unless otherwise noted.
PARAMETER
MIN
CONDITIONS
Supply Current (I DD)
TYP
TA = :5°C. ' lEE = 1pA, f = 32,768 Hz,
{ VDD - 1.5V
.
Doubler Operation
Tripier Operation
256/1 024 Hz Pulse Width
MAX
UNITS
3.0
5.0
pA
4.0
7.0
pA
17
ps
13
TA = 25°C, C = 0.047pF,
. Supply Voltage (VEE)
= 1pA, f = 32,768 Hz,
lEE
Doubler Operation
{ VDD - VSS = 1.5V, (Figure 9),
(Note 1)
Tripier Operation
2.5
V
3.8
V
Note 1: In oscillator network shown in Figure 4.
functional description
A block diagram of the Watch Chip is shown in Figure 1.
A chip pad layout is shown in Figure 2 and a package
connection diagram in Figure 3.
20.8
31.8
42.8
53.8
84.4
95.4
106.4117.4128.4
The MM58127 and MM58128 contain an on-chip
voltage doubler for display drive and the MM58129 and
MM58130 contain an on-chip voltag~ tripler.
150.4139.4128.4111.4106.495.4
139.4150.4
151.0
158MILS
53.8
42.8
31.8
20.8
6.50
I
151.0
131.8
84.4
s:
s:
C1I
151.0
141.0
141.0
129.4
129.4
113.4
113.4
104.4
104.4
96.4
96.4
...10
131.8
o
- - - - 1 5 8 MILS - - - - 115.4
115.4
89.5
14.0
65.9
58.9
50.9
41.9
33.9
26.9
6.5
FIGURE 2(b)
FIGURE 2(a)
MM58128N, MM58130N
MM58127N, MM58129N
•
NC
2b
40
39
2.
21
2g
OSC CAP
VEE
OSC OUT
OSC IN
OOUBLE
TRIPLE
CAP2
CAP 1
lb/le
2.
2d
2e
COLON
31
31
3.
3.
313b
36
4g
35
41
34
4.
33
4b
J2
SET/OISPLAY
31
30 VSS
VOO
29
STOP
28
TEST
21
CYCLE
26
4e
25
4d
24 4•
23
3e
22
3d
21 •
3
FOUT
32Iiz/8ACKPLANE
3g
38
15
16
II
18
19
20
40
•
39
38
3b
31
4g
36
41
2b
2.
21
2g
35 fOUT
34
OSC CAP
33
32 VEE
OSC OUT
4.
4b
SET /OISPLA Y
9
VSS
VOO 10
11
VSS 12
STOP
13
TEST
14
CYCLE
15
4e
16
4d
11
4.
18
3e
19
3d
20
3.
OSC IN
OOUBLE
TRIPLE
CAP2
CAP 1
32 Hz/8ACK PLANE
lb/le
2.
2d
2e
COLON
TOPVIEW
TOP VIEW
FIGURE 3(a)
FIGURE 3(b)
7-49
39
CO
eN
151.0
o
(II)
.-
00
Ln
:?i
:?i
00
N
.00
Ln
:?i
:?i
functional description
(Continued)
,
Time Base: The precision time base of the watch is provided by connecting a crystal controlled RC network to
the on-chip CMOS inverter/amplifier as shown in Figure
4. For proper operation, the network should be tuned to
32,768 Hz. Resistor R 1 is used to bias the on-chip inverter for class A amplifier operation. Resistor R2 is
used to (a) reduce the voltage sensitivity of the network;
(b) limit the power dissipation in the quartz crystal; and
(c) provide added phase shift for good start-up and low
voltage circuit' performance. Capacitors C1 and C2 in
series provide the parallel load capacitance required for
precise tuning of the quartz crystal. The network shown
in Figure 4 provides greater than 100 ppm tuning range
when used with standard X-Y flexure quartz crystals
trimmed for C L = 13 pF. Tuning to better than 2 ppm is
easily obtainable.
~
HOURS
MONTH
\
COLON
3
4,
MINUTES (SECONOS)
DATE
FIGURE 5. Time Display
Leading zero values of month, date, and hours are
blanked. The circuit contains a 4 year calendar which
will automatically reset the Date Counter to 1 and
advance the Month Counter at the end of each month
(except for February in Leap Year). The character display font is shown in Figure 6.
r'
N
.00
Ln
:?i
:?i
FIGURE 6. Character Display Font
OSC IN
SETTING CONTROL
A normally open switch connected to the Cycle input is
used in conjunction with the Set/Display switch to set
Month, Date, Hour, Minute, and synchronize Second
information.
~2,768 Hz
CL=12pF
C2
5-36pF
VDD OR Vss
Month: Depressing the Cycle switch while the watch is
in the Alternating Display mode will advance it to the
Set Month mode. In this mode the Month will be displayed in digit positions 1 and 2 with no colon. Depressing the Set/Display switch will cause the Month counter
to be advanced at a 1 Hz rate as long as the switch is
held in.
FIGURE 4. Crystal Oscillator Network
The 256/1024 Hz output or the 32 Hz output can be
used to monitor the oscillator frequency during initial
~uning without disturbing the network itself.
DISPLAY CONTROL
Date: Depressing the Cycle switch while the watch is in
the Set Month mode will advance it to the Set Date
mode. In this mode the Date will be displayed in digit
positions,3 and 4 with no colon. Depressing the Set/
Display switch will cause the Date counter to be advanced
at a 1 Hz rate as long as the switch is held in.
The Hour:Minute, Month Date, and Second displays are
controlled by a normally open switch connected to the
Set/Display input. Month and Hour are displayed in digit
positions 1 and 2. Date, Minute, and Second are displayed in digit positions 3 and 4.
The circuit will normally display Hour and Minute with
the colon flashing at a 1 Hz rate (Figure 5). Depressing
the Set/Display switch will cause Month and Date to be
displayed with no colon. The display will automatically
·return to Hour and Minute display 2.25 ±0.25 seconds
after the Set/Display switch has been released. Depressing the Set/Display switch a second time while the
Month and Date are being displayed will cause the
Second to be displayed until the Set/Display switch is
again depressed, returning the display. to Hour and
Minute. An option is available to display Minutes unit
and Seconds in this mode.
Hour: With the watch in the Set Date mode, depressing
the Cycle switch will put the watch in the Set Hour
mode. In this mode the Hour will be displayed in digit
positions 1 and 2 followed by the colon and either an A
or a P' (for AM or PM) displayed in digit position 4.
While in this mode, depressing the Set/Display switch will
advance the· Hour Counter at a 1 Hz rate until the Set/
Display switch is released.
Minute: Depressing the cycle switch while the watch is
in the Set Hour mode will advance it to the Set Minute
mode. In this mode the Minute will be displayed in digit
positions 3 and 4 preceeded by the colon. Depressing the
Set/Display switch while still holding the Cycle SWitch in
will cause the Hold mode to be activated but will not
advance the Minute counter. Depressing the Set/Display
switch after the Cycle switch has been released will cause
the Hold mode to be activated and will advance the
Minute counter at a 1 Hz rate as long as the switch is
held in.
All versions have an additional display mode that can be
used by depressing the Cycle switch while the watch is
in the first display mode described above. The second
display mode will alternately display Hour:Minute and
Month Date for a period of 2 seconds each. Depressing
the Set/Display switch will cause the Second to be
displayed. Depressing the Set/Display switch again will
return the watch to the second display mode.
7-50
functional description
(Continued)
Hold: The Cycle switch is used to advance from the Set
Minute state to the first display state. The colon will
blink on and off while time is being displayed unless the
Hold mode is activated, forcing the colon to remain on
continuously. During the second display mode, the
colon will remain on during time display. Depressing the
Set/Display switch while in either one of the two display
states will cause the Hold mode to be cleared, allowing
the watch to begin normal operation.
Control state diagrams for the watch are provided in
Figure 7.
Colon Output: The Colon output provides a 32 Hz
phase controlled signal identical to the' segment outputs.
The colon will blink at a 1 Hz rate during time display
mode (except for display mode one with the Hold
mode activated, and display mode two in the MM58117,
MM58119) and remain on continuous while displaying
time (Hours or Minutes) during the setting operation.
TEST PADS
Three pads are provided for test purposes.
FOUT: The 256/1024 Hz pad is provided for oscillator
tuning.
Options are available for 1 or2 Hz setting rate. In addi·
tion, a further option allows a fast set at 4 times the
normal rate by pushing both Set/Display and then the
cycle switch.
Stop Input: This input pad has an internal resistor to
VEE holding it normally at a logical "0." A logical "1"
at stop will force all of the display segments "OF F"
and stop the oscillator, placing the watch in a static
mode to decrease power dissipation during extended
periods of storage.
Contact Bounce: Debounce circuitry is provided on the
Set/Display and Cycle inputs to remove any logic
uncertainty upon either closure or release of switches.
Segment Outputs: The Segment outputs are designed
to drive field·effect liquid crystal displays. Each display
segment has its own output which furnishes the proper
32 Hz drive signal. By definition, the segment is "OFF"
when its drive signal is in phase with the display back·
plane signal (BP/32 Hz). The segment is "ON" when its
0
drive signal is 180 out of phase with the display backplane signal. Typical output waveforms are shown in
Figure 8.
BP/32 Hz: This input/output pad is under the control of
Test. When Test is open or at a logical "0," a 32 Hz
signal is provided on BP/32 Hz which can be used to
dri,!e the backplane of the LCD unit or to monitor the
oscillator frequency without affecting the oscillator circuitry. If Test is at a logical "1," the BP/32 Hz pad is
converted into an input and any frequency connected to
it will replace the normal internal 32 Hz signal. This
feature is provided to allow high speed advancement of
the internal counters for testing purposes.
Test: This input pad is used to control the BP/32 Hz pad
as described above. When the Test pad is at a logical "1,"
the phase-control is disconnected from the segment drive
outputs and the segment information will be referenced
to a logical "0" backplane. Switching the Test pad from
a logical "0" to a logical "1" generates a reset pulse that
will reset the watch counters to 1 AM on January the
first. This places the watch into a known state for testing
purpose.
Options: Various mask options of the basic part type
are available as standard parts: These are described in
Table I. Other combinations of these options can also
be made upon special request.
VOO
COMMON
1---
-
-
OFF
-~-I~-~---
ON - - - - -
... Automatic Ilme·oul routes
----+- User controlled routes
FIGURE 7. Control State Diagram
FIGURE 8. Common and Segment Output Signals
, '7 -51
o
M
a;
functional description
(Continued)
it)
~
~
TABLE I. Standard Available Optio.ns
PART NO.
MOUNTING
FOUT
DEBOUNCE
FREQUENCY
SETTING
RATE
RUN 2
RATE
MIN/SEC
MM48127
Front
1024
8 Hz
2 Hz/8 Hz
1/4 Hz
Yes
MM48128
Back
MM48129
Front
256
16 Hz
MM48130
Back
1024
8 Hz
2 Hz/8 Hz
1/4 Hz
1
Tj ~~~ETEr~:~' I.
20M
250k
VDD
DSC IN
TRIPLE
CAP2
DSC DUT
SET/DISP
CYCLE
=td
CAP 1
VDD
VSS
JI/2·DIGIT
LCD
*(For doubler, connect single
0.05 j.LF capacitance between
double and Cap 2)
I
2
~
HOURS
COLON
MINUTES
(SECONDS)
"ON" CHIP TRIPLER
FIGURE 9. Typical Application in LCD Watch System
u
___
__ 15p5
VOO~
VSS
.
±2p5
1024 Hz (MM58128. MM58130)
256 Hz (MM58127. MM58129)
FIGURE 10. 1024 Hz Output
7-52
No
Yes
Calculators
MM5734 8-function accumulating memory calculator
general description
The single-chip MM5734 calculator was developed using
a metal-gate P-channel enhancement and depletion mode
MOS/LSI technology with a primary object of low endproduct cost. A complete calcu.lator as shown in Figure 1 .
requires only the MM5734 calculator chip, an X-V matrix
keyboard, an NSA 1198 or NSA 1298 LED display and a
9V battery.
The MM5734 is capable of decoding a keyboard matrix
as shown in Figure 1. Three possible models are shown
in Figure 2. Figure 2(c) illustrates a keyboard scheme
which includes all 8 functions with only 23 keys by
using a function key (F).
Keyboard decoding and key debounce circuitry, all
clocks and timing generators, power-on clear, and 7segment output display decoding are included on-chip,
and require no external components. Segments and digits
can usually be driven directly from the MM5734, as the
segments typically source 8 mA of peak current and the
digit drivers sink 20 mA min.
•
•
•
•
•
•
•
•
•
•
•
•
features
Leading zero suppression and a floating negative sign
allow convenient reading of the display and conserve
power. The MM5734 is capable of sensing a low battery
voltage and indicates this by displaying a decimal point
in digit eight. Up to 8-digits for positive' numbers and 7
for negative numbers Can be displayed, with the negative
sign displayed in the 8th position. Typical current drain
of a complete calculator displaying five "5's" is 25 mAo
8-digit, (7-negativel, capacity
8 functions (+, -, X, 7, X2, y'x, l/X, %)
Convenient algebraic notation
Fully protected accumulating memory (M+, M-)
Automatic constant independent of memory
Floating input/floating output
Power-on clear*
On-chip oscillator*
Direct 9V battery compatibility
Low system cost
Direct digit drive of LED display
Low cost X-V keyboard matrix
I
* Requires no external components
connection diagram
keyboard outline
Dual-I n-Line Package
04
28
05
F*
cs* %*
03
27
07
F*
X2* EX* 08
02
26
06
y'* M+* M-*
08
l/X* MR* MC* %* 06
01
09
K2
K3 - - . 7
22
K4 - - . 8
21
OSC - - . 9
20
Pin Description
l/X
K1-K4 Keyboard Inputs
vOO IN1,IN2 General Purpose Inputs
Programmable as
OSC
External Oscillator
01-09 Digit Outputs
Sa.
Segment Outputs
Sa-Sg
Sb
SOP
Decimal Point Segment
Output
NC
0
General Purpose Output
-9 Volts
SO
VDD
o Volts
VSS
Sg++10
19
IN1--.ll
18
sOP
12
17
Sf
13
16
vSS
14
15.-IN2
Sd
Se
TOP .VIEW
Order Number MM5734N
See Package 23
8-2
y'
X2
-;.* 07
.-
05
x
04
-
03
+
02
C
CF
K4
09
01
K3
K2
Kl
*Double Function Key
absolute maximum ratings
operating voltage range
Volume at Anv Pin Relative to VSS
VSS +0.3V to VSS -12V
(All Other Pins Connected to VSS)
O°c to +70°C
Ambient Operating Time
-65°C to +150°C
Ambient Storage Time
Lead Temperature (Soldering, 10 seconds)
300°C
6.5V
s Vss -
VDD
S 9.5V
dc electrical characteristics
100
Operating Supply Current
MIN
CONDITIONS
PARAMETER
TYP
MAX
15
S
VDD = VSS -9.5V, T A'" 25°C
UNITS
mA
Keyboard Scan Input Levels
CK1
K4
Logical High Level
VIH
Logical Low Level
VIL
Segment Output Current
VDD = Vss -6.5V
VSS-4.0
VSS
V
VDD = VSS -9.5V
VSS-4.0
VSS
V
VDD = Vss -6.5V, IlL":; -SOMA
Voo
VSS-6.0
V
VDD = Vss -9.5V, IlL":; --SOMA
Voo
VSS-6.3
V
VOUT = Vss -1.0V, Voo = Vss -6.5V
-2.5
mA
-S
VOUT = Vss -5.0V, VDO = Vss -S.OV
mA
-12
VOUT = Vss -6.5V, Voo = Vss -9.5V
mA
Digit Output Current
IOH.
Logical High Level
VOUT = Vss -2.0V. Voo = Vss -6.5V
IOL
Logical Low Level
VOUT = Vss -3.0V
Ready Output
-300
MA
20
mA
VOD = Vss -6.5V
VOH
Logical High Level
lOUT = -550MA
VOL
Logical Low Level
lOUT = 5MA
V
Vss-1.0
VDD+6.0
V
5
K
Keyboard Resistance
K1, K4
ac electrical characteristics
PARAMETER
CONDITIONS
MIN
Display Word Time
(Figure 3)
2.9
Display Digit Time
(Figure 3)
0.32
Interdigit Blanking Time (Segment
(Figure 3)
TYP
MAX
UNITS
15.4
ms
1.71
ms
ps
175
Outputs)
Ready Transition Times
High-to-Low
VDD = VSS -6.5V
20
ps
Low-to-High
CL = 50 pF
1
ps
Digit Output Transition Times
High-to-Low
CL = 100 pF
Low-to-High
Keyboard Inputs
CL = 25 pF
8
MS
3
ps
6
ps
High-to-Low Transition Time After Key Release
Key Bounce-Out Stability Time
11.7
61.7
(The ti me a keyboard input must be
continuously lower than the maximum
logical low level tei be accepted as a key
closure, or higher than the minimum
logical high level to be accepted as a
key release.)
Worst-Case Calculation Time
0.56
S·3
ms
D
functional description
The MM5734 is a calculator chip which contains five
data registers: (1) entry, (2) accumulator, (3) 2 working
and (4) memory, each consisting of 8 digits, sign, and
decimal point. The entry register is always displayed. It
contains digit entriesfrom the keyboard, and results of all
functions except M+ and M-. The accumulator is used in
all arithmetic functions and stores a copy of the entry
register on all results. This allows another number to be
entered without losing an intermediate result. Multiply
and divide requi res three registers to perform the function
and save the divisor, or mUltiplier. The working register
is provided to perform these functions in conjunction
with the entry and accumulator registers. A second
working register is used to store the constant in chain
operations while performing X2 or 1/X. This allows
chai n operation using X2, 1 IX and
The MM5734 performs the "+:' "-," "X" and
functions using algebraic notation. This requi res the use
of a mode register and a terminate flag. The mode
register directs the machine to the proper function (add,
subtract, mUltiply or divide) with each new key entry.
After the function has been performed, the key entered
is used to modify the mode register.
The terminate flag is set on "=" and sometimes on "%"
and "C." This signifies the end of the problem. The
MM5734 allows for full floating entries and intermediate
results.
.JX.
If the terminate flag is set"a "+," "-:' "X" or "-;.-" key
signals the beginning of a new problem. The number
being displayed is copied into the accumulator ,register
and the mode register assumes the mode of the key
entered. The terminate flag is always reset by the "+,"
"-:' "X" and "-;.-" keys.
The memory register is used only to store a number to be
used later. It is fully protected during all operations,
and is only modified by depressing a "MS:' "M+," or
"M-" key. Power·on clears all of the registers including
the memory register.
REr y
OP Sg Sf Se Sd Sc Sb Sa
I
Sa Sb Sc Sd Se Sf
VOO
K4
MM5734
K2
n-,-VSS
~
01 02 03 04 05 06 07 08 09
1
OPTIONAL
KEYS
lf ~
r--o;,
r
~
K3
Sg OP
NSA1198
09 08 07 06 05 04 03 02 01
"ON OFF"
~ ~....
--~....... 'oi:.......
~ ~ ~....... '0.:--....
~ ~ ~ ~
~ ~ '02-...... M .......
c
,
0
"
.......
=
....
FIGURE 1A. Complete Calculator Schematic
K4
K3
K2
Kl
K3
K4
p~::
~"
FIGURE 1(b). Optional Keys
K2
Kl
.........1-......::~-~.....-D9
FIGURE 1(c). Optional Keys
8-4 -
OPERATION IN THE ADD AND SUBTRACT MODE
Operation in the Multiply Mode
If the terminate flag is set. an "=" key will result in a
constant multiply operation. The number being displayed
is multiplied by the constant stored in the accumulator
register. The result is displayed in the entry register and
the accumulator and mode registers are not altered.
allowing for constant operation. Repeated depressions of
the "=" key can be used to raise a number to an integer
power. i.e .• "C." "C." "5.2." "X." "-" "-" "-"
computes 5.24 .
09
07
06
07
7
8
9
x
04
4
5
6
-
OJ
1
2
J
+
02
C
CF
0
=
01
The constant in multiplication. as well as in addition.
subtraction and division is the last number entered. For
the sequence: "C." "C." "3." "':'-." "4." "X." "2."
"=" the constant multiplier for future problems is 2.
If the terminate fl ag is not set. an "=" key wi II signal
the end of a problem. The number in the display will be
multi plied by the contents of the accumulator. and the
results will be displayed in the entry register. The number
previously in the entry register is stored in the accumulator register and the terminate flag is set.
FIGURE 2
If the terminate flag is set. an "=" key will result in a
constant add/subtract. The number in the accumulator
will be added to (or subtracted from) the number being
displayed. The result is right-justified and displayed in
the entry register. Accu mulator and mode registers are
not altered. allowing for constant operations.
If the terminate flag is not set. and a number has been
entered from the keyboard or memory register. a .. +.".
"-." "X" or ".:,-" key will result in a multiplication.
The number being displayed will be mUltiplied by the
number 'residing in the accumulator register. The result
will be copied into the accumulator and displayed in the
entry register. The mode register is updated as a function
of the key depressed.
If the terminate flag is not set and a number has been
entered from the keyboard. or memory register. a "+."
"-." "X" or. ".:,-" key will result in an addition or subtraction. The entry register will be added to or subtracted
from the accumulator and the new running total will be
displayed in the entry register and copied into the
accumulator register. The mode will be altered according
to which key is entered.
'
Operation of the "%" key while in multiply mode looks
exactly the same as an "=" key except the decimal point
of the display is shifted two positions to the left before
the mUltiplication takes place.
If the terminate flag is not set. and a number has not
been entered from the keyboard. or memory. a "'+."
"-." "X." ".:,-" key will only change the mode register
to the new key entry.
Operation in the Divide Mode
If the terminate flag is set. an "=" key will result in
constant divide operation. The number being displayed
is divided by the constant stored in the accumulator
register. The accumulator and mode registers are not
altered allowing for constant operations. Repeated depressions of the "=" key will result in repeated divisions
by the constant. Thus, it is possible to raise a number to
a negative power usi ng the sequence "C." "C." "1."
"-7." .. No .... "=." "=." etc.
If the terminate flag is not set •. an "=" key will add/
subtract the number being displayed to/from the number
in the accumulator register. The number being displayed
is transferred to the accumulator. and the result of the
operation is displayed in the entry register. The terminate
flag is set. conditioning the calculator for constant. add/
subtract operation. The number being displayed previous
to the '~=" key is stored in the accumulator as the
constant.
If the terminate flag is not set. an "=" key will signal
the end of a problem. The number in the accumulator
register will be divided by the number being displayed.
The result is transferred to the entry register and displayed. The terminate flag is set and the divisor is stored
in the accumulator register.
Operation of the "%" key in add/subtract mode. with
the terminate flag reset. will mUltiply the accumulator
by the last entry. divide the result by 100. and display it
in the entry register. The mode register remains as it
was in the add/subtract mode. All of the above is required to perform the percent add on or discount
problems. Depression of an "=" key after the "%" key
will either tax or discount the original number as a
function of the mode register and the last entry.
If the terminate flag is not set. a "+." "-." "X" or ".:,-"
key will result in a division. The number in the accumulator register will be divided by the number being
displayed. The results are displayed in the entry register.
and a copy of the result is stored in the accumulator. The
mode register is modified to reflect the latest key entry.
Operation of the "%" key in add/subtract mode. with
the terminate flag set. will shift the decimal point of the
number being displayed two places to the left and copy
it into the accumulator register. The mode is set to
mUltiply and the terminate flag remains set.
Operation of the "%" key while in divide mode looks
exactly the same as the "=" key except the decimal
point of the display is shifted two positions to the left
before division takes place.
8·5
Error Conditions
Function of Keys
If any of the operations mentioned above generates a
number larger than 99999999, an error wi II occur. An
errpr is indicated by displaying the 8 most significant
digits and sign with all 9 decimal points. The first depression of the "C" key will clear the error condition,
and all fegisters except the memory register.
Some of the keys operate differently when in the data or
number entry condition. The MM5734 switches to entry
condition when entering numbers and leaves this condi·
tion after most function keys. The following paragraphs
which discussed the action of "+," "-," "X," ":;." and
n%" keys and the examples given in later sections will
act in further explaining these actions.
It is not possible to generate an error during number entry.
The ninth and subsequent digits entered are ignored.
Clear Key, nCE/C"
While in the number entry condition, one depression
will clear the entry register to zero. The machine then
leaves the number entry state.
Leading Zero Suppression and Negative Sign
In order to conserve battery power, the MM5734 blanks
leading zeros on all numbers displayed. No more than 7
decimal digits are permitted. The MM5734 displays 8
digits for positive numbers, arid 7 digits negative, allowing
the 8-digit position for a negative sign. The negative
sign floats to the left of the most significant digit on
numbers containing less than 7 digits.
If the error condition is displayed, one depression will
clear the error, and all registers except the memory
register. The machine could not be in the number entry
condition with the error flag set.
If the error flag is not set and the machine is not in the
number entry condition, one depression of "CE/C" key
will clear the entry and accumulator registers. It also
places the machine in the add mode and sets the terminate
flag. The memory register remains unchanged.
. Power-On Condition
The MM5734 has an internal power-on clear circuit
which clears all registers to zero, places the mode to
add and sets the terminate flag. A zero and decimal
point are displayed.
Number Keys 0-9
Keyboard Bounce and Noise Rejection
If not in the number entry condition, a number key will
clear the display and then enter the value of the-key into
the LSD. The digits are drs played as they are entered
and the machine assumes the number entry cC?ndition.
The MM5734 is designed to interface with most low cost
keyboards, which are often the least desirable from a
false or mUltiple entry standpoint. A simple X-V keyboard matrix can be used with all the necessary decoding
accomplished within this MM5734.
If in the number entry condition, the entry register is
shifted left one position and the key depressed is entered
into the LSD. Digits entered after 8 digits positive, or 7
digits negative, will be ignored. Digits entered after 7
decimal digits are displayed will also be ignored.
A key closure is sensed by the calculator chip when one
of the key inputs, K 1, K2, K3, K4, is forced more
negative than the logical low level specified in ·the
electrical specifications. An internal. counter is started
as a result of the closure. The key operation begins after
11 word times if the key input is still at alogicallow.
level. As long as the key is held down (and the key input
remains low) no further entry is allowed. When the key
input changes to a logical high level, the internal counter
starts an 11 word timeout for key release. During both,
entry and release timeouts, the key inputs are sampled
during every display period for valid levels. If they are
found invalid, the counter is reset and the calculator
resumes scanning the keyboard.
Square Root Key
"vx"
The square root key extracts the square root of the
absolute value of the number being displayed in the
entry register.
The mode of the calculator remains unchanged. This
enables square root operations in the middle of chain
calculations. For example:
KEY DISPLAY
A
A
-vi VA
The "Ready" signal indicates calculator status. When the
calculator is in an "idle" state, the output is at a logical
high level (near VSS). When a key is closed, the internal
key entry timer is started. "Re~dy" remains high until the
timeout is completed and the key entry is accepted as
valid, then goes low. It remains at a logical low level
until the function initiated by the key is completed and
the key is released. The low-to-high transition indicates
the calculator has returned to an idle state and a new key
can be entered.
+
'B
-vi
8·6
..;A
B
VB
..;A+VB
KEY DISPLAY
KEY DISPLAY
A
A
11
X
B
A
+
B
5
VB
AVB
-vi
...r
6
11
11
, 5
16
4
6
11
9
9
-vi
3
8
Square
Depression of the "X 2 " key squares the number in the
display register, and displays the results. The mode of
the calculator remains unchanged. This enables square
operations in the middle of chain calculations.
mode of the calculator remains unchanged. This enables
inverse operations in the middle of chain calculations.
F Key (Function Key)
Depression of the "l/X" key takes the inverse of the
number in the display register and displays the results. The
The "F" key translates the following key depressed to
this code of the key below it, Figure 2, if it is a DOUBLE
FUNCTION KEY. If the CLEAR KEY is the following
key, the FUNCTION CONDITION is removed leaving
the calculator in its previous mode.
SQUARE PROBLEMS
INVERSE PROBLEMS
Inverse
KEYS
72
X2
7
CS
X2
+
8
X2
DISPLAY
7 2.
5184.
7.
-7.
49.
49.
8.
64.
1 13.
COMMENTS
Squares display
KEY
DISPLAY
5
l/X
4
l/X
5.
0.2
4.
0.25
COMMENTS
Takes inverse of display
Takes inverse
+
Squares minus numbers
Chain capabilities
8
l/X
Squares display (mode
unchanged)
Completes addition, terminates problems
8
0.125
0.375
8-7
Takes inverse (mode
unchanged)
Completes addition, terminates problem
Calculators
MM5737 calculator-8-digit, 4-function, floating decimal point
general description
The MM5737 single-chip calculator was developed using
a metal gate, P-channel, enhancement and depletion
mode MOS process with low end-product cost as the
primary objective_ A complete calculator, as shown in
Figure 1, requires only a keyboard, DMB864 digit driver,
nine digit LED display and a 9V battery with appropriate hardware_
The Ready output signal is used to indicate when the
calculator is performing an operation (Table I). It is
useful in testing of the device or when the MM5737 is
used as part of a larger system and is required to interface with other logic. (Another feature that is important
in such applications is the ability to reduce the key
debounce time from seven word times to four word times
by forcing the Digit 7 output high during Digit 9 time.)
Keyboard decoding and key debounce circuitry, all
clock and timing' generation and output 7-segment display decoding are all included on-chip and require no
external discrete components. LED segments can be
driven directly from the MM5737 as it typically sources
B.O mA of peak current. [Note: The typical duty
cycle of each digit is 0.111; average LE D segment
current is therefore approximately 0.111 (B.O mA). or
0.89 mAo Correspondingly, the worst-case average segment current is 0.111 (5.0 mA), or 0.555 mA.l The
ninth digit is used for the negative sign of an eight digit
number, and as an error indicator. Negative results less
than eight digits will have the negative sign displayed one
digit to the ieft of the most-significant·digit (MSD). The
DM8864 digit driver is capable of indicating a low
battery voltage condition by turning on the ninth digit
decimal point-which does not hinder the actual calculator operation.
features
Leading and trailing zero suppression allows convenient
reading of the right justified display and conserves
power. Battery life is estimated to b~ 10 to 20 hours,
depending on battery quality, operating schedule and
the average number of digits displayed.
•
Full 8·digit entry and display capacity
•
Four functions (+, -, x, 7)
•
Floating negative sign indicator is always displayed
one digit to left of MSD
•
Convenient algebraic key entry notation
•
Floating' point input and output
•
Chain operations
•
Direct 9V battery compatibility; low power
•
Direct intllrface to LED segments
•
No external components are required other than
display digit driver, keyboard and LED display for
complete calculator
•
Overflow and divide-by-zero error indication
•
Right justified, entry and results, with leading and
trailing zero suppression
connection diagram
Dual-I n-Line Package
READY..!..
24
r-DIGIT 4
9.2.
23
r-DIGIT 5
DIGIT
3
~DIGIT6
4
~DIGIT7
5
20
r-DIGIT 8
6
r!! KEY INPUT 31K3)
DIGIT1DIGIT2OIGIT3-
voo -
18
)-- KEY INPUT 21K2)
SEGMENTd..!..
8
~ KEY INPUT l1Kl)
SEGMENTb-
9
~SEGMENTe
,..!.'!..
)-- SEGMENT.
.!!.
)-- SEGMENT c
SEGMENTg-
SEGMENT
DECIMAL PT
15
14
13
)--N/C
vss.2.!.
\
TOPVIEW
8·8
'
Order Number MM5737N
See Package 22
~
~
absolute maximum ratings
Voltage at Any Pin Relative to Vss. (All
other pins connected to Vss ).
Ambient Operating Temperature
Ambient Storage Temperature
Lead Temperature (Soldering, 10. seconds)
CJ1
-..oJ
(.oJ
Vss + 0.3V to Vss - 12.0
, oOe to + 70°C
o
-55°C to +150 e
300°C
-..oJ
operating voltage range
6.5V ~ Vss - Voo ~ 9.5V
. (Vss always defined as most positive supply voltage.)
dc electrical characteristics
PARAMETER
Operating Supply Current (I DD)
Keyboard Scan Input Levels
(Kl, K2 and K3)
Logical High Level (V IH)
Logical Low Level (V IL )
Digit Output Levels (Note 1)
Logical High Level (V OH )
Logical Low Level (VOL)
Segment Output Current
(Sa through Sg and Decimal Point)
Ready Output Levels
Logical High Level (V oH )
~ogical Low Level (VOL)
CONDITIONS
MIN
V DD = Vss -9.5V
TA = 25°C
Vss -u.5V -:::; V DD -:::; Vss -9.5V
V DD = Vss -u.5V
V DD = Vss --9.5V
V ss -2.5
Vss -u.5V -:::; V DD -:::; Vss -9.5V
V DD =, Vss -U.SV
V DD = Vss --9.SV
V ss -l.5
T A = 25°C
V OUT = Vss -3.8V, V DD = Vss -6.5V
V OUT = Vss -S.OV, V DD = Vss -8.0V
V OUT = Vss -u.5V, V DD = Vss -9.SV
lOUT = -0.4 mA
lOUT = 10,uA
-S.O
TYP
MAX
UNITS
8.0
14.0
mA
V ss -5·0
V ss -6.0
V
V
V
V ss -6.0
V ss -7.0
V
V
V
-8.0
-10.0
-15.0
V ss -1.0
V DD +1.0
mA
mA
mA
V
V
Note 1: With digit connected through key to K·line and to DM8864.
ac electrical characteristics
PARAMETER
CONDITIONS
MIN
TYP
Word Time (Figure 2)
MAX
UNITS
0.63
Digit Time (Figure 2)
70
1.5
5.2
ms
170
580
,us
.
OJ
,'"
Interdigit Blanking Time (Figure 2)
4
,us
Digit Output Transition Times
(tRISE and tFALd
CLOAD = 100 pF
2
,us
Keyboard Inputs High to Low
Time After
Key Release
CLOAD
= 100 pF
4
,us
Transi~ion
Ready Output Propagation Time
(Figure 3)
Low to High Level (tPDH )
High to Low Level (tPDL )
C LOAD = 100 pF
CLOAD = 100 pF
60
0.06
140
0.5
480
1.5
,us
ms
Key Bounce·out Stability Time
(The time a keyboard input must be
continuously higher than the
minimum logical high level to be
accepted as a key closure, or can·
tinuously lower than the maximum
logical low level to be accepted as a
key release.)
4.2
10.5
35
ms
Calculation Time for
99999999.;. 1 = 99999999
90
220
760
ms
8·9
~\'~
I Kl
S. Sb Sc Sd S. SI S9 dp
K2
MM5737
---lK3 01 02 03 04 05 06 07 DB 09
~......
'07........
"'<>-:-......
~......
~
~.......
,.~
Voo
,-, CJ.'-, ,-, '-, ,-, '-, '-, ,-, ,-/
I
T
LV GNO Vee
INO
dp
S9
CI.
09
08
SI
S.
Sd
Sc
Sb
-
-_.....+
-
9V-=-
POWER
""o!-
\
L:J
OMB864
'o!.
~
......
~
NSA198I
C/.
CI.
CI.
CI.
CI.
CI.
CI.
07
06
05
04
03
02
01
~
'02-
s.
.......
""0=-
.......
'0=.
.......
9
.......
c
0
.......
. KEYBOARD
CALCULATOR CHIP
DISPLAY DRIVER
LED DISPLAY
FIGURE 1. Complete Calculator Schematic
TABLE I. Ready Signal Description
READY SIGNAL
CALCULATOR FUNCTION
Idle
READY is quiescently at a Logical High Level ("'V ss ).
Key Entry and Functional Operation
When a key is depressed, the bounce·out stability timer is initiated.
READY remains high until the bounce'out time is completed and the
key is entered, at which time it changes to a Logical Low Level ("'V DD)'
Key Release and Return to Idle
READY remains low until key release is debounced and the calculator
returns to the idle state. The low to high transition signals the return to
idle. (The display may lag the READY by up to eight word times.)
KEY INPUT BOUNCE AND NOISE REJECTION
The MM5737 galculator chip is designed to interface
with low cost keyboards, which are often the least
desirable from a noise and false entry standpoint.
or ringing has stopped and the stability time counter has
timed out. Noise that persists will inhibit key entry
indefinitely. Key release is timed in the same manner.
A key closure is sensed by the calculator chip when one·
of the Key Input Lines, Kl, K2 or K3 is forced more
positive than the Logical High Level specified in the Elec·
trical Specifications. At the instant of closure, an internal
"Key Bounce·out Stability Time" counter is started.
Any significant voltage perturbation occurring on the
switched key input during timeout will reset the timer.
Hence, a key is not accepted as a valid entry until noise
One of the popular types of low cost keyboards
available, the elastomeric conductor type, has a key
pressure versus contact resistance characteristic that can
generate continuous noise during "teasing" or low pres·
sure key depressions. The MM5737 defines a series
contact resistance up to 50 k!1 as a valid key closure,
providing an optimum interface to that type of keyboard
as well as more conventional types.
8·10
ERROR CONDITIONS
Decimal Point
In the event of an overflow, the MM5737 will display
an "E" in the leftmost digit and at least seven of the
significant digits of the answer. Division by zero results
in' an "E" with eight trailing zeroes. Once in an error
condition, all keys except the clear key are ignored.
First depression of this key in a number entry will enter
a decimal point in the LSD position of the display
register. Subsequent depressions of the decimal point
key before any function key will be ignored.
Add, Subtract, Multiply or Divide Keys
KEY OPERATIONS
First depression after a number entry will terminate tkle
entry, perform the previously recorded 0 peration, if
any, and record the function key depressed as the next
operation to be performed after another number entry.
Subsequent depressions of any function key, without an
interceding number or decimill point entry will supersede
the previous function as the next to be performed. After
an equal key, the displayed result of the equal operation
will be re-entered and the function key depressed will
become the next operation to be performed after a
number entry is followed by another function key
(including equal).
Clear Key
Operation after a number entry clears the entry and
displays a previous result. Second depression clears all
registers and displays a zero without decimal point in
the LSD. Operation after a function key (+, -, x, -;- or =)
clears all registers and displays a zero without decimal
point. Two depressions are always required after power
is applied.
.
,
Number Entries
First entry clears the display register and enters the
number into the least significant digit (LSD) of the
display register. Second through eighth entry shifts the
display register left one digit and enters the number into
the LSD. The ninth, and subsequent entries, are ignored
and no error condition is generated. Because only seven
positions are allowed to follow the decimal point, the
eighth and subsequent entries after a decimal point
entry are ignored.
Equal
First depression after a number entry will terminate the
entry, perform the previously recorded operation and
record the fact that an equal ,key has been depressed.
Depression after the add, subtract or divide keys, without an interceding number or decimal point entry, will
be ignored. After a multiply key, the number being
displayed will be squared.
WORO TIME
01
02
03
09
DECIMAL POINT
S.
Sb
S.
Sd
S.
SI
.
Sg
01
02
03
04
05
06
07
~::I I1
La'sCLI
1 L _7 7 _7.L
ACTUAL
DISPLAY:
09
•'
•
01
SEGMENT
DESIGNATION
'IT/b
·/~/c
d
FIGURE 2. Display Timing Diagram
8-11
r-..
r-..
M
Vss
I
DIGIT 9
L!)
~
~
Voo - - - '
J
10%
' " - - - - - - -.... io-J
Vss
/
DIGIT 1
, Voo
VSS
READY
Voo
10%
- r------r-
~
tPOH
VOHt90%
~!OL
--------~~~-------~I~
FIGURE 3. Ready Output Timing
sample problems
I.
Single Calculations
5 x 3.14 = 15.7
Key
Display
c
Comments
Two clears are required after power-up.
C
o
5
5
5
3
3.
3.1
3.14
15.7
x
3
1
4
II. Chain Calculations
A.
23.37 + 243.00 - 489.16 = -=-222.79
Key
Display
c
Comments
o
C
23.37
+
243
x
23.37
23.37
243
266.37
Function key completes previously recorded "+" operation.
266.37
Wrong "X" function key is updated to "-."
(Wrong Function Key)
489.17
C
489.16 .
B.
489.1 7
266.37
489.16
-222.79
Number entry error is cleared and corrected. Note the
floating negative sign.
Find square root of 169 using a modified Newton approximation method. Let N represent the squared number and_Xo
the initial estimate. The first approximation, X, , is
If
X,
Xo
X,
X2
X3
o
= (N/X + Xo )/2
is 15,
= (169/15 + 15)/2
= (169/X, +X,)/2
= '(169/X 2 + X 2 )/2, etc.
Key
C
C
169
15
+
15
2
169
13.13
Comments
Display
o
169
169
15
1 1.266666
15
26.266666
2
13.133333
169
169
. 13.13
Result is X,
Four digits are conveniently remembered
8-12
sample problems (con't)
II. Chain Calculations (continued)
Key
+
13.13
2
Display
Comments
1 2.87 1 287
13.13
26.001 287
2
1 3.000643
Result is X 2 , which is usually adequate. If more
accuracy is required, continue the iteration.
III. Auto Squaring.
A.
5.25 2 = 27.5625
Key
Display
c
o
C
5.25
B.
5.25
5
Comments
5.25
5.25
27.5625
Number in display register is squared.
= 3988.3798
Key
c
C
5.25
x
x
5.25
Display
Comments
o
5.25
5.25
27.5625
27.5625
759.69 1 4
759.69 1 4
5.25
3988.3798
·Auto square = 5.25 2
Auto square = 5.25 4
Result is 5.25 5
8·13
Calculators
MM5758 scientific calculator
general description
The single-chip MM5758 Scientific Calculator is another
MaS/LSI product from National Semiconductor using a
metal-gate, P-channel enhancement/depletion mode technology to achieve low system cost. A complete calculator
performs a wide range of complex scientific problems,
yet consists of .only the MM5758, two display driver ICs,
the' NSA5101 LED display, a keyboard and power
supply (Figure 1). No discrete components are required.
I
Iz
Iy
IT
Iy
Ix
IX
t
IZ
1m
1M
The contents of the storage register M are replaced with
the contents of the X-register by using the "STO" key.
The memory recall key, "RCL," copies M into register X
without disturbing the value of M. M is cleared automatically at power-on or by storing a zero. All registers
contain eight mantissa digits, two exponent digits and
the sign information for each.
An internal power-on clear circuit automatically clears
all registers, including the storage memory and fourregister operational stack, when power is initially applied
to the chip.
The MM5758 performs trigonometric, logarithmic,
exponentiation, power and square root functions simply
by pressing a key. It computes and displays numbers
over a range of ±9.9999999 x 1O±99. Afou r-register
operational stack simplifies computation of problems
with multi-nested terms and reverse polish entry notation
provides a logical and consistent method of keying in
even the most complex problems.
features
•
•
Enters, computes and displays numbers as large as
. ±9.9999999 x 10 99 and as small as ±lx 10~9
Complete slide-rule capability
• Arithmetic functions: +, -, x, 7, 1lx,
• Logarithmic functions: In x, log x, eX, lOx
Yx
The displayed output has an eight digit mantissa with
a two digit exponent; both the mantissa and exponent
display an additional sign digit. Sign information is
presented to the display by the calculator chip during a
single digit time, but the NSA5101 display physically
separates the two as shown in Figure 2.
All computed results greater than 99999999. or less
than 0.1 are automatically converted to scientific
notation. Trailing zero suppression of the - mantissa
allows convenient reading of the left justified display
and conserves power. The exponent digits are blanked
if no exponent is displayed. The most-significant-digit
of the exponent is not blanked, even if it is a zero, when
an exponent is being displayed. A low battery indication,
activated by sensing circuitry in the DS8868, is included
in the mantissa sign digit.
•
•
Power function: yx
Trigonometric functions: sin x, cos x, tan
arc sin x, arc cos x, arc tan x
•
Other functions:
Jr,
exchange, change sign
•
•
Reverse polish notation
Four-register operational stack with roll capability
•
Independent two key storage register
•
Floating point input and output
•
•
Power-on clear
Designed-in low system cost
•
Automatic display cutoff
sample keyboard
~~~~~
'LiJ~~~LiJ
~~~~~
A Ready output signal is used to indicate calculator
status. It is useful in providing synchronization information during testing and when the MM5758 is used with
other logic; e.g., with the MM5766 Programmer.
•••• i.1
Thirty-six keys are arranged within a four-by-eleven
matrix (Table 1 and Figure 2). Dual function keys are
not required.
• • • • iii]
• .... 1.1
...... 1.1
The user has access to five registers designated X, Y, Z,
T and M. X is the display and entry register and .the
bottom of a "push·up" operational stack that includes
registers Y, Z and T.
8-14
x,
absolute maximum ratings
operating voltage range
Voltage at Any Pin Relative to Vss Vss + 0.3V to Vss -12V
(All other pins connected to Vss)
Ambient Operating Temperature
O°C to +70°C
Ambient Storage Temperature
-55°C to +150°C
Lead Temperature (Soldering, 10 seconds)
300°C
7.2 V ~ Vss - V DD ~ 8.8V
Vss is always the most positive supply voltage ..
dc electrical characteristics
CONDITIONS
PARAMETER
Operating Supply Current (1 00 )
MIN
Voo = Vss -8.8V, T A = 25°C
12.0
Keyboard Scan Input Levels
(K1 through K41
Logical High Level
Logical Low Level
MAX
20.0
V ss -2.5
Display Reset Input Levels
Logical High Level
Logical Low Level
Encoded Digits Output Current
·(0 A through Do I
Logical High Level (loHI
Logical Low Level (loL I
TYP
Low Voltage Indicator Level (V 1H )
mA
V oo +1.5
V
V
V oo +1.5
V
V
V ss -1.5
V OUT = Voo + 1.0V
V OUT = Voo
UNITS
-0.5
-2.50
-50
Voo+2.8
Vss
mA
pA
V
(Digit DA must be forced to a V 1H
voltage level during the IDLE digit
time to cause Segment Sb to be turned
"ON" at digit time 01.
Segment and Decimal Point Output
Current (Sa through Sg. DPI
Logical High Level (JOH)
Logical Low Level (l oL )
Ready Output Levels
Logical High Level (V OH I
Logical Low Level (VOL I
-550
V OUT = Voo + 5.4V
V OUT = Voo + 1.5V
-10
~ss-1.0
lOUT = -0.4 mA
lOUT = 10/1 A
V oo +1.0
pA
pA
V
V
ac electrical characteristics
MIN
TYP
MAX
0.5
1.3
2.2
Digit Time (Figure 3)
42
108
183
/1S
Interdigit 81anking Time (Figure 3)
3.5
8.0
14.0
/1s
14.0
/1S
30
115
30
120
/15
/1S
15.4
ms
PARAMETER
CONDITIONS
Word Time (Figure 3)
Keyboard Scan Inputs (K1 through
K41 Low to High Transition Time
(during Interdigit 81anking Time).
(t POH )
Ready Output Propagation Time
(Figure 4)
Low to High Level (t pOH )
High to Low Level (t POL )
CLOAO =·100 pF
CLOAO = 100 pF
C LOAO = 100 pF
3.5
Key 80unce·out Stability Time.
(The time a keyboard sca~ input,
K1. K2, K3 or K4, must be continuo
ously connected to a digit to be
accepted as a key closure, or lower
than the maximum Logical Low
Level to be accepted as a key
9.1
UNITS
release.I(Figure 5)
Display Cutoff Time
(The time after the last val id key
closure at which all digits except
the most·significant·digit of the
mantissa will be blanked.)
second
50
Calculation Times
Square Root
LOG X or LN X
10 x or eX
0.50
0.85
1.00
1.80
1.30
1.40
0.85
yx
SIN X, COS X or TAN X
ARC SIN X or ARC COS X
ARC TAN X
8-15
0.90
1.50
1.75
3.10
2.20
2.40
1,50
second
second
second
second
second
second
second.
18)
1-' ,-, ,-, ,-, ,-, '-I ,-, 1-'
C'. CI. ,~,. CI. C'./~'. CI. I~'.
Ib).
'9)
01
02
03
04
05
06
09
010
011
012
1111
+
KEYBOARD
MATRIX
ISEE FIGURE 2
AND TABLE I)
FIGURE 1.
Block Diagram of Complete Handheld Scientific Calculator Using MM5758.
FROM 058867
SEGMENT DRIVER
.
'91
171
51
131
111
b
c
d
e
,
19
71 \
151
1
OP
9
NSA5101
KEYEOARO
MATRIX
01
1
02
2
03
3
04
4
05
6
07
06
8
10
08
12
09 010 011 012
14
18
20
21
~....... ~_.......
1
~
.....
......
Vss
10PTIONAL)
I
0
~
~O
~.......
~X
i'o2-......
~
"-
~N
......
"0-2
~N
......
~S
~
.....
......
.....
~L
.....
~....... ~
_.......
~c ~G
.......
......
~.....
~
......
~L ~'
~....... ~
.......
~
i'o2- ~.......
~
_
,
.
~
.... ~.....
~.
"o-!- ~ ~
......
......
.......
1
K,
---2.!.
DISPLAY
RESET
2
3
K,
KJ
......
9
4
K,
0.
DB
MM5758
Dc
Do
5
15
6
14
7
13
8
12
0.
01
8
02
7
03
6
04
5
05
4
2
J
06
07
08
D.
058868
Dc
00
FIGURE 2. Digits Interconnection Detail For Scientific Calculator.
8-16
1
09
18
011
17
012
SCALING OF DISPLAYED NUMBERS
AUTOMATIC DISPLAY CUTOFF
Computed results are displayed in either floating point
or scientific notation. Answers in the ra(lgebetween 0.1
and 99999999. are displayed in floating point format;
otherwise scientific notation is used. For example: 123.4
is displayed as written; whereas, 123.4 mi Ilion would
appear as 1.234 x 108 . The smallest magnitude displayed
is ± 1.0 x 10--99, and the largest ±9.9999999 x 10 99 .
Number entries are always displayed in the manner
entered until "ENT" is depressed, after which they
appear scaled.
If no key is depressed for approximately 50 seconds, an .
internal automatic display cutoff circuit will modify the
encoded digit output sequence sent to the DS8868
Decoder/Driver to be the blanking input code (Table II)
during all digit times except the most·significant of the
mantissa (02). Thus, in the cutoff power saving mode,
only one digit is displayed. The blanking code has been
selected to also be the minimum power case for the
DS8868.
Any of the 011 ("CS," "rr" or "TAN") keys will.restore
the display; to restore the display without modifying
the status of the calculator use the "CS" key twice, or
momentarily force the Display Reset high. The automatic display cutoff feature can be disabled by hardwiririg
the Display Reset pin to Vss.
KEYBOUNCE AND NOISE REJECTION
The MM5758 is designed to interface with most low-cost
keyboards, which are often the least desireable from a
false or multiple entry standpoint.
When a key closure is sensed by the calculator, an
internal timeout is started. Any voltage perturbations
of significant magnitude which occur on the Key Input
Lines (K 1, K2, K3 or K4) during the timeout will reset
the timer to zero. A key is accepted as valid after a
noise-free timeout period; noise that persists indefinitely
will inhibit key entry. Key releases are checked in the
same manner.
READY SIGNAL OPERATION
The Ready signal indicates calculator status. When the
calculator is in an "idle" state the output is at a Logical'
High Level (near V ss ). When a key is closed, the internal
key entry timer is started. Ready remains high until the
time-out is completed and the key entry is accepted as
valid, then goes low as indicated in Figures 4 and 5. It
remains at a Logical Low Level until the function
initiated by the key is completed and the key is released
and timed out. The low to high transition indicates the
calculator has returned to an idle state and a new key
can be entered.
The internal timeout period (Key Bounceout Stabil ity
Time) is normally seven word times. By forcing digit DB
to a Logical High State during Digit Timing State 012
time (Table Ill. the Stability Time is reduced to four
word times.
TABLE I. Keyboard Matrix
DIGIT TIMING STATES
SWITCH
INPUTS
D1
Kl
0
K2
+
D2
CS
K3
1f
K4
TAN
D3
D4
9
8
STO
l/X
SIN
D5
7
D7
D6
6
D8
D9
5
4
3
yX
.......
C
EN
RCL
ARC
ROL
LOG
y'
COS
Dll
D12
2
1
X
EEX
c·
LN
10'
TABLE II. Digits Timing State Truth Table
ENCODED DIGITS
Do Dc DB DA
H
H
L
L
H
H
H
H
L
H
H
H
H
L
H
H
L
H
L
H
H
L
H
L
H
H
L
H
L
H
H
L
L
L
H
H
H
H
H
L
L
L
L
H
H
L
L
L
L
L
L
L
ON
H
L
=.
Dl
D2
DECODED DIGIT STATES (DS8868)
D3 D4 D5 D6 D7 D8 D9
ON
ON
ON
OS8868 output buffer will sink
ON
ON
ON
ON
ON
ON
ON
ON
ON
2:
110 mA @ VOUT:::; OAV
= Logical High State (- VSS)
c::'
Dl0 Dll D12
Logical Low State (- VOO)
8-17
co
it)
to-
ENCODED
DIGIT
OUTPUTS
it)
~
~
D.
D.
Dc
Do
SEGMENTS
Sd
S.
Sf
S,
DECIMAL
POINT ..:...._'--....._...;...._'--....._...;...........1
r
ACTUAL OISPLAY:
.!
MANTISSA NEG
SIGN -S,
LOW BAnERY VOLTAGE INOICATOR
I,? 3 LI. 55 79 - 0 B
SEGMENT
OESIGNATION:
EXPONENT NEG
SIGN oS.
FIGURE 3. Display Timing Diagram
VOH
02SIGNAL
FROMOSB868
ANY OIGIT
SIGNAL CONNECTED
THROUGH KEY
TO K·LINE
READY
SIGNAL
FIGURE 4. Ready Timing
NEW KEY
IS DEPRESSED
I
KEY IS
RELEASED
!---7WDRDTMES----j
I
I
s~B~~~!---lI~~7WORDTlMES~
Illr"""'NDISE~
u
::Zgs~~~
"NOISE"/
,
CALCULATION
IS COMPLETED,
WHICHEVER IS
LONGER.
I - - . J~
.
JJ
REAOY
NE~~~~~~~LB;g:~~r::~J
NEX~ KEY CANj
MAY BE RELEASED.
BE ENTERED
FIGURE 5. Functional Description of Ready Signal and Key Entry.
ERROR INDICATION
TABLE III. Conditions for Error Indication
In the event of an operating error, the MM5758 will
display all zeros and decimal points. Improper operations
or calculations are summarized in Table III. All square
root computations are of the absolute value of X;
therefore, the square root of a negative number is not
considered an invalid operation.
FUNCTION
or l/X
yx
7
An error condition is reset by pressing "C." All registers
in the stack are lost and replaced with zeros. M is saved.
8·18
CONDITION (REGISTER X == Xl
IXI
~
0
y < O. X LOG Y > 99
eX
Ixl>230
lOx
IXI> 99
LOG X or LN X
X~O
SIN X, COS X, TAN X
ARC SIN X or ARC COS X
X90
Xl
ARC TAN X
X< 0
KEY OPERATIONS
Clear Key,
Enter Exponent Key, "EEX"
"c"
Clears X, pushes Y down to X, Z to Y, T to Z and places
a zero in T. Subsequent depressions perform the same·
operation; thus, four "C" depressions will clear a
completely full stack. If the display indicates an error
condition exists, the "C" key clears X, Y, Z and T.
Storage memory M is not affected by any "C" operation.
Number Entries
The first numeral of a number entry following any
function, other than "EN," raises the stack and T is lost.
Numerals are entered and displayed from left to right.
Following "EN" the first number entry is placed in X
without affecting the rest of the stack. Ninth and
subsequent entries of the mantissa are ignored; th ird
and subsequent entries of the exponent are entered as a
new least-significant-digit, and the previous most-significant-digit is lost.
Puts calculator in exponential entry mode. "EEX" must
be preceded by a number (mantissa), or it will be
ignored. A decimal point is an invalid entry that changes
X to zero.
Trigonometric Keys, "SIN," "COS," and "TAN"
Assumes the value of X is an angle in degrees and
computes the indicated trigonometric function, replacing
X with the result. Register T is replaced by a zero;
M, Z and Yare not affected. Following "ARC," the
trigonometric keys determine the angle represented by
the function in X, and replace X with that value in
degrees. T is replaced by a zero; M, Z and Yare unchanged.
Reciprocal Key, "l/X"
A non-zero value of X is replaced by its reciprocal.
Registers Y, Z, T and M are unaltered.
Square Root Key,
Decimal Point, "."
"VX"
The absolute value of X is replaced by its square root.
Registers Y, Z, T and M are not altered.
Places a decimal point on the right side of the leastsignificant-digit being displayed during entry of the
mantissa. It is invalid during exponent entry and clears
the X-register to zero (starting a new number entry).
logarithmic Keys, ''IN'' and "lOG".
Change Sign Key, "CS"
These keys replace the value of X by its natural or
common logarithm, respectively. Registers Z and T
become zero. Registers Y and M are not affected.
Changes the sign of X. In the exponent entry mode, it
changes the exponent sign. It does not terminate entry
ar]d therefore can be depressed at any time during the
entry mode. Multiple depressions are allowed.
Power Key, "y X "
Determines the value of Y raised to the power of X and
replaces X with that result. Registers Y, Z and T become
zero. M is not affected.
Enter Key, "EN"
Register T is lost, Y and Z are pushed up and X is copied
into Y.
Exponential Keys, "ex" and "10 x "
The constants 2.7182812 or 10.0 are raised to the
power of X, respectively, and placed in X. Register T
becomes zero; Y, Z and M are not affected.
THE FOUR FUNCTION KEYS, "+," "-," "x," and
Add key, "+"
Subtract key, "-"
Multiply key, "x"
Divide key, "-;.-"
Memory Keys, "STO" and "RCl"
The memory store key, "STO," copies the value of X
(including sign) into storage register M, without altering
the stack. The recall key, "RCl," transfers Z to T,
Y to Z and X to Y, then copies Minto X. Storage
register M is not changed and T is lost. Both "STO"
and "RCl" terminate an entry mode.
Pi Key,"rr"
Register T is lost; X, Y and Z are pushed up in the stack
and the constant 3.1415927 is placed in X.
Exchange Key, "+-+"
Roll Stack Key, "ROl"
Registers X and Y are exchanged; other registers are not
affected.
Repositions the data within. the operational stack by
transferring X to T, Y to X, Z to Y and T to Z. After
four successive depressions each of the four data positions has been viewed and returned to its original location.
Inverse Trigonometric Key, "ARC"
Preceding one of the three trigonometric keys, "SIN,"
"COS" or "TAN," it conditions the calculator to
determine the angle in degrees of the value in register X.
"ARC" followed by any key other than one of the
trigonometric keys will be ignored.
Range and Accuracy ·of Functions
The smallest magnitude that can be displayed is ±1 0-99
and the total range is ±9.9999999 x 10 99 . Table IV
summarizes range and accuracy of the MM5758 functions.
8·19
TABLE IV.
FUNCTION
RANGE
ACCURACY
+, -, x, 7, 1/X
± 1 x 10-99::; X::; ±9.9999999 x 1099
±1 in first non·zero digit from LSD
VX
1±1 x 10-99 1::; X ::; 1±9.9999·999 x 1099 1
±2 in first non·zero digit from LSD
1099
7 digits
X ::; +9.9999999 x 1099
7 digits
LOG X
0< X::; +9.9999999
LN X
o<
lOx
± 1 x 10-99 ::; X ::; +99
eX
±1 x 10-99::; X::; +230
yX
Y > 0, with X and Y values such that the
results will be +1 x 10-99::; X::;
X
5 digits
5 digits
I
5 digits
+9.9999999 x 1099
SIN, COS, TAN
0::; X::; +90
7 digits
ARC SIN, ARC COS
0::; X ::;+1
5 digits
ARC TAN
o ::; X ::; 9.9999999 x 1099
5 digits .
• Error in last useable digit is less than 5
Summary of Stack Operations
m. OJ. 0.'
OJ. 0.0 AFTER FUNCTION KEY
J.
· LOST
t~T
z - ,,----z
v ---.-/
r--
00
V
:----' C:~
=---.J
NUMBER
t
CD. 0.0.•
0'0
T
m. 8. 0
~
AFTER
OR FIRST NUMBER
• z
•
;
V
r=:~
NUMBER = - - . !
[§].§J.~.0.0.
~
•
T
•
Z
•
M
&
~.~. ~
FOLlOWEO BY
0 - - V - - LOST
t----A.-.T
.. z
•
;
Y
r=:~.
!(Xl=--.!
12:]
GJDQO
0 - - - -.....
t __
LOST
z ____ LOST
T
•
T
Z
•
•
Z
Y
'Y
V - - LOST
F:
~
v ___
.
Yx _ _ _ _.......
f (x.
8·20
. ,,'--T
'----z
z~
LO~T
'--- Y
x - - - - LOST
. rX
m
;t-M
vI - - - - - '
Summary of Stack Operations (can't)
@g
..
T
..
Z
~LOST
t--
..
Y
z ---' ,..---
z
y--./ ,---
Y
,---T
;~C:~
@J
~~6~: ~~:riJ::T ~EX THEN
CSX
•
T
•
Z
~
AFTER FUNCTION
Y
X
- - - - - -...-
..
M
- - - - - -...-M,
t~TZ
Y
x
X
..
X (EEX IS IGNORED)
~ AFTER NUMBER ENTRY
.. T
z
..
Z
III
Y
- - - - - -...-
..
M
X (REAOY FOR
EXPONENT)
M
@J,§1
ERROR CONOITION
D___
LOST
•
Y
•
y
t _
T
Z
•
§g
111
..
..
D----_.
r----- T
t --
z--LOST~ Z
Z __
'l--,
T
L- Z
•
Y - - LOST -------- Y
x-LOST
..
LOST
LOST
Y
F~
M
1 ( . ) - - - -.....'
SAMPLE PROBLEMS
Problem No.1 1.345 + 7120 - 14251
=
,
?
STACK REGISTERS
KEY ENTRY
POWER ON
4
ENTER
0
+
7
CLR
1
4
DISPLAY X
Z
Y
T
MEMORY M
o.
o
1
1.
1.3
1.34
1.345
1.345
1.345
Copy X in Y
o
Add X and Y
71
712
7120
7121.345
1
o
o·
o
COMMENTS
Power on clears all registers and
memory
7121.345
17 I
7121.345
Clear entry, pushes down stack
7121.345
14
142
1425
14251
-7129.655
7121.345
o
o
o
o
o
o
Subtract X from Y
Note: (t is not necessary to clear
calculator for the next problem.
8-21
ex)
Ln
r-..
Problem No.2
~
~
KEY ENTRY
(3.73
x 10-7 ) x (-15 x 1024 ) -;- 27357.3 =?
Ln
STACK REGISTERS
3-
7
3
EEX
7
CHS
ENTER
1
CHS
EEX
2
7
3
3
CLR
CLR
DISPLAY X
Y
3-
Z
-7129.655
3.
3.7
3.73
3.73
3.73
3.73
' 3.73
MEMORY M
.T
0
0
COMMENTS
The new number entry pushes the
answer of the last problem up in
the stack
0
Prepare for exponent entry
07
-07
-07
1
15
-15
-15
-15
-15
-5.595
2
27
273
2735
27357
27357.
27357.3
-2.0451579
-7129.655
O.
Change sign of exponent
-07
3.73
-7129:655
Change sign of mantissa
02
24
18
14
-7129.655
-5.595
-7129.655
18
Multiply X and Y
0
0
0
0
0
-7129.655
Divide Y by X
Clear Answer
Clear answer from problem 1
0
0
Note: This is not necessary. It is
done here to avoid confusion of
stack operation in the next problem.
(3 2
Problem No.3
JlO.3
KEY ENTRY
DISPLAY X
+ 42 )
(52
+ 62 )
STACK REGISTERS
10.3
ENTER
10.3
10.3
3
ENTER
ROLL
ROLL
ROLL
ROLL
3
3.
3.
10.3
O.
3.
9.
4
4.
16.
25.
257.5
5
5.
25.
4
ENTER
+
ENTER
6
ENTER
x
+
,,;x
6.
36.
61.
15707.5
125.32956
Y
0
COMMENTS
MEMORY M
T
Z
0
10.3
0
The "Roll" key can be used
to examine the stack. It is not
necessary for the solution.
10.3
10.3
0
3
10.3
9
4
9
10.3
0
257.5
5
257.5
25.
6
25
257.5
0
0
Register contents displayed:
10.3
0
Y
3
10.3
0
0
0
10.3
0
0
0
0
10.3
0
19. 3
9
10.3
0
0
0
257.5
0
257.5
25
257.5
0
Z
T
X
32
0
4?
(32 +4 2 )
10.3 (32 + 4 2 )
52
257.5
0
0
0
8-22
0
62
. (52 +6 2 )
10.3 (32 + 42 ) .5 2 + 62 )
",10.3 (32 + 4 2 ) (52 + 6 2 )
Problem No.4 1 +
2!1 X + 3!1 X 2
=?, X = -0.15
STACK REGISTERS
KEY ENTRY
1
ENTER
1.
Z
Y
DISPLAY X
0
1
125.32956
0
2!
2
.!
0.5
2!
X
0.15 CHS
-0.15
STO
-0.15
X
-7.5
+
X
125.32956
0.5
-0.15
125.32956
-02
0.925
2!
1+
125.32956
0
0.925
125.32956
3
0.925
125.32956
0
3.
2
X
6.
0.925
125.32956
.!
0.1666666
0.925
125.32956
0.1666666
0.925
125.32956
0.1666666
0.925
0.1666666
0.925
0
0
3!
-0.15
X
-0.15
ENTER
-0.15
2.25
-0.15
-02
X
3.7499985 -03
0.925
+
0.9287499
0
CLR
0
RCL
-0.15
Problem No.5
7T(21) = ?
KEY ENTRY
DISPLAY X
2. x
2!
ENTER
RCL
Store X for use later in the problem
~X
0
2
X
COMMENTS
MEMORY M
T
0
125.32956
-0.15
3!
X
Answer to last problem is lost here
X2
2. X2
3!
1
+ 2. x + 2. X2
2!
O.
0
-0.15
0
3!
Notice that the clear does not affect
the memory register. Memory is changed
only by storing another value or by power
off.
212 (n) = ?
STACK REGISTERS
Y
3.1415927
21
21
X
65.973446
21
21
-0.15
-0.15
-0.15
11(21)
0
65.973446
-0.15
65.973446
ENTER
21.
21
441.
65.973446
3.1415927
441
1385.4423
65.973446
COMMENTS
MEMORY M
-0.15
0
3.1415927
X
X
T
Z
-0.15
-0.15
0
65.973446
-0.15
-0.15
0
-0.15
Example using Exchange and Reciprocal keys.
Problem No.6
STACK REGISTERS
KEY ENTRY
DISPLAY X
z
Y
5
5
1385.4423
65.973446
ENTER
5.
5
1385.4423
1385.4423
65.973446
T
-0.15
'MEMORY M
COMMENTS
-0.15
65.973446
1
EXCH
5.
0.2
0.2
1385.4423
65.973446
0.2
0.2
1385.4423
65.973446
EXCH
0.2
0.2
1385.4423
65.973446
EXCH
0.2
0.2
1385.4423
65.973446
O.
1385.4423
65.973446
0
0.0.0.0.0.0.0.0.
o
0
0
0
0
.!
X
CLR
o.
8-23
Compare the answers obtained by
exchanging X and Y. In this case,
they are identical.
Compare by subtracting zero error
Divide by zero. Error clears all registers.
-0.15
After clearing an error, all registers are
zero. Memory is not disturbed.
Problem No. 7 Example using "1 Ox" and "LOG" keys
STACK REGISTERS
KEY ENTRY
DISPLAY X
1.2345678
1.2345678
STO
lOx
1.2345678
LOG
1.2345678
RCL
1.2345678
EXCH
1.2345678
EXCH
1.2345678
Y
Z
0
-0.15
0
1.2345678
Store original value
17.161995
1.2345678
Compare answer to original value
4
ENTER
COMMENTS
MEMORY M
T
0
1.2345678
4.
Fill the stack
4
1.2345678
3
ENTER
3.
2
2
ENTER
2.
4
4
1.2345678
lOx
10.
0
1.2345678
Notice that "T" is lost (same for 1Ox, eX)
1.2345678
Notice that "Z" and "T" are lost (same for
LOG, LN)
10.
ENTER
4.
3
3
ENTER
3.
3
10.
10
2
ENTER
2.
4
1
LOG
2.2
0
-07
0
Problem No.8 Example using "ex" and "LN" keys
STACK REGISTERS
KEY ENTRY
DISPLAY X
Y
8.7654321
8.7654321
STO
eX
8.7654321
LN
8.7654321
RCL
8.7654321
8.7654321
0.0
2.2
Z
2.2
COMMENTS
MEMORY M
T
-07
1.2345678
8.7654321
Store origi nal value
8.7654321
Compare answer to
original. Error is 0.0
6408.8309
0
-07
2.2
-07
0
0
2 10
Problem No.9
STACK REGISTERS
KEY ENTRY
DISPLAY X
Y
2
ENTER
2.
10
yx
10
Z
8.7654321
-07
2.2
COMMENTS
MEMORY M
T
8.7654321
8.7654321
8.7654321
1024.0037
0
Notice that "Y," "Z"
and "T" are lost
8.7654321
0
Problem No. 10 Trigonometric computations
STACK REGISTERS
KEY ENTRY
30
DISPLAY X
30
Y
1024.0037
T
Z
0
0
MEMORY M
8.7654321
COMMENTS
Enter X in degrees
SIN
0.5000002
Sine of 30° is computed
ARC
0.5000002
ARC sine is computed
SIN
2!iJ.999.556
4
4
29.999556
1024.0037
ENTER
4.
4
29.999556
1024.0037
3
3
3
4
29.999556
3
4
ENTER
3.
2
2
ENTER
2.
1
SIN
1.7452415 -02
2
4
4
1.7452415 -02
ENTER
4.
4
1.7452415 -02
0
8.7654321
3
8.7654321
2
8-24
Notice that "T" is lost (same for SIN,
. COS, TAN)
Problem No. 10 (con't)
STACK REGISTERS
KEY ENTRY
3
ENTER
2
ENTER
1
ARC
SIN
DISPLAY X
3
3.
2
2.
1
1.
89.999997
Y
MEMORY M
T
Z
3
4
1.7452415 --02
2
3
4
2
3
0
8.7654321
COMMENTS
Notice that "T" is lost (same for
ASIN, ACOS, ATAN)
Problem No. 11
STACK REGISTERS
KEY ENTRY
30
COS
ARC
COS
DISPLAY X
30
0.8660252
0.8660252
29.999569
Y
T
Z
MEMORYM
89.999997
2
3
0
8.7654321
89.999997
2
0
8.7654321
COMMENTS
Problem No. 12
STACK REGISTERS
KEY ENTRY
45
TAN
DISPLAY X
Y
T
Z
MEMORY M
45
0.9999991
29.999569
89.999997
2
0
8.7654321
45.000629
29.999569
89.999997
0
8.7654321
ARC
TAN
connection diagram
Dual·ln·Line Package
SWITCH
INPUT
LINES
~N/C
["~
.!!..V oo
KZ..!.
KJ..2
.!!.READY
4
K4-
ENCDDED
DIGIT
LINES
.!!..DISPLAY RESET
r~
~SEGMENTF
...!
.!!..SEGMENTB
Dc..2.
-SEGMENTG
Do...!
.!!...SEGMENT 0
D•
18
9
N/C-
~SEGMENTE
N/C..!2.
,!;.. SEGMENT A
11
N/C-
14
""""" DECIMAL POINT
13
IZ
-SEGMENTC
Vss TOPVIEW
Order Number MM5758N
See Package 22
I
8·25
COMMENTS
Calculators
MM5760 slide rule calculator
general description
features
The single-chip MM5760 Slide Rule Calculator was
developed using a metal-gate, P-channel enhancement
and depletion mode MaS/LSI technology with the
primary objective of low end-product cost. A complete
calculator as shown in Figure 1 require's only the
MM5760, a keyboard, DM8864 digit driver, NSA298
LED display and a 9V battery with appropriate hardware.
•
•
Full 8-digit entry and display capacity
Complete electronic slide rule capability
• Arithmetic functions: +, -, x, 7,
1/x, x 2
• Logarithmic functions: In x, log x, eX
• Trigonometric functions: sin x, cos x, tan 'x, arc
sin x, arc cos x, arc tan x
.;x,
•
Keyboard decoding and key debounce circuitry. all
clock and timing generation and 7-segment output display encoding are included on-chip and require no
external components. Segments can usually be driven
directly from the MM5760, as it typically sources about
8.5 mA of peak current. (Note; the typical duty cycle
of each digit is 0.104; average LED segment current is
therefore approximately 0.89 mA.) The left-most digit
is used for the negative sign or the decimal point of a
number less than unity.
An internal power-on clear circuit clears all registers,
including the memory, when Voo and Vss are initially
applied to the chip.
Trailing zero suppression allows convenient reading of
the left justified display, and conserves power. The
DM8864 digit driver is capable of sensing a low battery
voltage and providing a signal during Digit 9 time that
can be used to turn on one of the segments as an
indicator. Typical current drain of a complete calculator
displaying five "5's" is 30 mAo Automatic display cutoff
is included. If no key closure occurs for approximately
35 seconds, all numbers are blanked and all decimal
points displayed.
The Ready output signal is used to indicate calculator
status. It is useful in providing synchronization information during testing and when the MM5760 is used with
other logic or integrated circuits; e.g., with the MM5765
Programmer (Figure 3).
Thirty-two keys are arranged in a four-by-nine matrix
(Figure 1). I n addition to seven arithmetic functions
plus logarithmic, trigonometric and accumulating memory functions, the calculator is capable of calculating yX,
adding the square of X to memory, automatically
entering 7r and providing degrees/radian conversions.
The user has access to four registers designated X, Y, Z
and M. X is the display and entry register, and is the
bottom of a "push-up" stack that also includes registers
Y and Z:
Other functions: yX, 7r, change sign, exchange,
x 2 + memory -+ memory, radians to degrees,
degrees to radians
•
•
Three-register operational stack
Independent accumulating storage register with store,
recall, memory plus and memory minus functions
•
•
Fl'oating point input and output
Direct 9V battery compatibility; low power
•
•
Power-on clear
No external components required other than display
digit driver, keyboard and LED display for complete
calculator
Error indication for over range, overflow and invalid
operations
•
•
Left justified entry and results with trailing zero
suppression
•
Automatic display cutoff
•
Reverse polish notat~on
connection diagram
Dual-In-Line Package
DIGIT 22..
~DIGIT5
DIGIT 1.2..
2!. DIGIT 6
SWITCH
INPUTS.
r~
Iz
Ix
IZ
IY
.!!. DIGIT 7
~DIGIT8
K3.l.
6
K2-
~DIGIT9
KI.2..
r!!-
V oo
-
8
.!!. SEGMENT E
J:!!.
..!:.. SEGMENT A
.!!. DECIMAL POINT
II
SEGMENTF-
1m
1M
IX
Note: Lower case letters designate the data in the register
identified by a capital letter.
READY
r22- SEGMENT D
SEGMENT G..!..
SEGMENT B
Iy
2!.DlGIT 4
DIGIT 3..!.
~SEGMENTC
12
Vss TOP VIEW
Order Number MM5760N
See Package 22
absolute maximum ratings
operating voltage range
Voltage at Any Pin Relative to Vss Vss + O.3V to Vss - 12V
(All other pins connected to VS5)
Ambient Operating Temperature
O°C to +70°C
-55°C to +150°C
Ambient Storage Temperature
30boc
Lead Temperature (Soldering, 10 seconds)
6.5V::; Vss - Voo ::; 9.5V
Vss is always defined as the most positive supply voltage.
dc electrical characteristics
PARAMETER
Operating Supply Current (I DD)
Keyboard Scan I nput Levels
(Kl. K2, K3 and K4)
Logical High Level
Logical Low Level
Digit Output Levels
Logical High Level (V OH )
Logical Low Level (Val)
Segment Output Current
(Sa through Sg and Decimal Point)
Ready Output Levels
Logical High Level (V OH )
Logical Low Level (Vod
CONDITIONS
V DD
MIN
TYP
= V ss -9.5V, T A = 25°C
V ss -6.5V::; V DD ::; Vss -9.5V
V DD = V ss -6.5V
V DD = V ss -9.5V
RloAD = 3.2 kn to V DD
V ss -6.5V::; V DD ::; V ss -9.5V
V DD = V ss -6.5V
V DD = V ss -9.5V
T A =25°C
V OUT = V ss -3.6V, V DD = V ss -6.5V
V OUT = V ss -5V, V DD = V ss -8V
V OUT = V ss -6.5V, V DD = Vss -9.5V
lOUT = -0.4 mA
lOUT = lOpA
MAX
16.0
Vss -2.5
V
V
V
V ss -6.0
V ss -7.0
V
V·
V
-8.5
-10.0
-15.0
V ss -1.0
VDD+l.0
-
mA
V ss -5.0
V ss -6.0
V ss -l.5
-5.0
UNITS
mA
mA
mA
V
V
ac electrical characteristics
PARAMETER
CONDITIONS
Word Time (Figure 2)
Digit Time (Figure 2)
Segment Blanking Time (Figure 2)
TYP
MAX
0.32
0.65
1.3
ms
36
70
145
ps
4.5
9
2
Digit Output Transition Times
(t R1SE and t FALL )
ClOAD
= 100 pF,
Keyboard Inputs High to Low
Transition Time After
Key Release
ClOAD
= 100 pF
CLOAO
CLOAD
= 100 pF
= 100 pF
R loAD
UNITS
MIN
= 9.6 kn
ps
2
ps
4
ps
Ready Output Propagation Time
(Figure 3)
Low to High Level (t PDH )
High to Low.Level (tPOl )
10
Key Input Time·out
Key Entry
Key Release
Display Cutoff Time
(The time after the last valid key
closure that all numbers will be
blanked and all decimal points
displayed.)
"
8·27'
50
1
ps
ms
ms
ms
2.8
5.1
6.0
10.4
11.7
20.5
10
22
44
second
a
REr
Kl
K2
K3
y
I
S. Sb Sc Sd S. SI
I
Sg OP
::1
MM5760
--jK4 Of 02 03 04 05 06 07 08 09
"cE...
~
-...0:....
~
~
...... ~
......
....
~ ~' 'o!-
....
,
,
I
T
LV GNO Vee
INO
OP
. Sg
09
08
S I S•.
Sd
Sc
Sb
s.
07
05
04
03
02
06
-_....
,
+
$'
~ "o!-...... ~,
~, ~ "0,:... "o!.... ... ...
"ct-.... ~.... ~...... ~......
~
0 ~
....
~ ~
....
....
9V
MALLORY
MN1604
OR
EQUIV.
POWER
OM8864
~L
.... ~....
"'-
-'
01
rooI--
~:
NSA298I
n n n C l n C l n l - CI
CI. CJ. D. CI. CI. D. CJ.ld D.
r-o;......
EN
.... ~
I/X
5
,
......
*Dual function keys.
KEYBOARD
FIGURE 1. Complete Calculator Schematic
i - - - - - - - - - - - W O R O TIME - - - - - - - - - - -
02
03
-+--+--~
09
DECIMAL
POINT-t---t----i1-l
SEGMENTS
s.
-+--:-!
Sb
So
Sd
S.
SI
-+--1-1
-+--1-1
~--+---+--~
.
SU""':'_ _...;..J
ACTUAL DISPLAY:
n-ICCll-'-'1
CI I D ~I -, ~/.C I
09 •
•
SEGMENT
DESIGNATION
01
IlT/b
./~/c
d
FIGURE 2: Display Timing Diagram
I
The contents· of the accumulating storage /register Mare
replaced with the contents of the X register by using the
"STO" key. Preceding "+" or "-" with the "ARC" key
sums X into M. or subtracts X from M. "ARC" followed
by "STO" squares X and sums it into the memory
without changing the value of X. The memory recall
key, "RCL," copies M into X without disturbing the
value of M. Storage register M is cleared automatically at
power-on or by storing a zero. All registers contain eight
digits and sign information.
Inputs are entered and outputs displayed in floating
point. The output results are truncated. ,Data entry
always precedes the operation keys that operate on
them; this is referred to' as Reverse Polish notation.
(S.ee examples.)
Vss
~
K
INPUTS
SEGMENT
OUTPUTS
• MM5160
DIGIT
OUTPUTS
"'''~'~
POINT
Voo
PROGRAM
MODE
SWITCH
READY
LED
DISPLAY
!
SLIDE RULE
CALCULATOR
III
:I "'''~''"'..
"""" "'",,
nnnnnnnnn
RUN
NSA298
C4C4/~./~.C4C4C4C4C4
LOAD
DIGIT
191
191
~
r--- n
OUTPUT
191
INPUT
L _ __ :..J
I
4 X9
OAT A
KEYBO ARO
AN 0
1X4
PROGRA MMER
CO NT ROL
KEYBO ARD
DATA
~
I
---+
Vee
191
DM8864
181
GND
READY
RUN/LOAD
V's
K I/O',
DIGIT
ORIVER
MM5165
CONTROL
K5
ALARM
Voo
POWER
SWITCH
*LEO
ALARM
INDICATOR
LEARN MODE
PROGRAMMER
-=-
J9V
ON
FIGURE 3. Low Cost Hand Held Programmable Electronic Slide Rule Using the MM5760 Calculator and MM5765 Programmer
KEY SEQUENCE EXAMPLES
KEY
DISPLAY
o.
1
o
o
LOG
EN
10
C
C
10
EN
2
yX
50
+
4
~
EN
7
2
X
9
STO
3
. ARC
SIN
1
LN
RCL
1/X
9
~
yX
.8
ARC
ARC
SIN
SIN
1
10
100
2.
2.
10
2.
o.
10
10.
2
99.99993
50
1 49.99993
4
2.
2.
7
-5.
2
-10.
'-1 4.9 9 9 9 9 3
9
9.
COMMENTS
Power·On Clear
Copy X into Y
Clear X, stack pushes down
Stack cleared
6 digit accuracy. Typical calculation time
Typical calculation time
"STO" terminates data entry
3
3
.0.0.0.0.0.0.0.0
.1
-2.302585
9.
.1 1 1 1 1 1 1 1
9
.1 '1. 1 1 1 1 1 1
1.27651 7
.8
.8
.8
53.1 301
.8
= 90 ms
Error indication (X
No clear needed
> 1)
Typical calculation time
Exchange X and Y
Second "ARC" ignored
SIN- 1 in degrees
SIN of 53.1301°
=260 ms
=
1.7 seconds
0
CD
,...
KEY SEQUENCE EXAMPLES (Con't)
I.t)
~
~
KEY
DISPLAY
COMMENTS
~8
ARC
COS
COS
ARC
TAN
TAN
LOG
LN
eX
36.8699
.8
.8
38.65981
.8
-.09691
.0.0.0.0.0.0.0.0
1.
3.1 41 5926
1.
1.27651 7
1T
C
C
C
LN
1
CS
STO
ARC
COS
ARC
TAN
RCL
eX
RCL
ARC
SIN
ARC
COS-lin degrees
COS of 36.8699
T AN- l in degrees
TAN of 38.65981
eX for X = 0
o.
.0.0.0.0.0.0.0.0
1
-1
-1.
-1.
180
180
89.68169
-1.
.3678796
-1.
-1.
-9 O.
-9 O.
-1.5707963
-1.5707963
-1.5707963
-2.5707963
ARC
+
RCL
90° in radians
Accumulate X· in M
Recall M
EXAMPLE DEMONSTRATING STACK OPERATIONS
14 + 26
LOG(~)
6-
Evaluate:
4
SIN (25 + 5)
STACK REGISTERS
KEY
X
14
EN
26
+
6
EN
4
14
14.
26
40.
6
6.
4
2.
4.
10.
1.
25
25.
5
30.
.5
40
6
6
6
40
0
0
1
25
25
1
1
0
?
40
40
40
0
0
0
0
1
1
0
0
2.
0
0
0
0
VX
LOG
25
EN
5
+
SIN
C
O.
Y
Z
COMMENTS
Y and Z are unknown
14
14
. 8:30
14 + 26 = 40
V4 =2
6-y4=4
(14'+ 26)/6 -V4 = 10
LOG [(14 + 26)/(6 -V4)] = 1
SIN (25 + 5) = 0.5
LOG [(14 - 26)/(6
SIN(25 +.5)
-V4)]
. -
2
KEYBOARD BOUNCE AND NOISE REJECTION
READY SIGNAL OPERATION
The MM5760 is designed to interface with most low cost
keyboards, which are often the least desirable from a
false or multiple entry standpoint.
The Ready signal indicates calculator status. When the
calculator is in an "idle" state the output is at a Logical
High Level (near Vss ). When a key is closed, the internal
key entry timer is started. Ready remains high until the
time-out is completed and the key entry is accepted as
valid, then goes low as indicated in Figures 4 and 5. It
remains at a Logical Low Level until the function initiated
by the key is completed and the key is released. The low
to high transition indicates the calculator has returned to
an idle state and a new key can be entered.
A key closure is sensed by the calculator chip.when one
of the key inputs, K 1, K2, K3 or K4 is forced more
positive than the Logical High Level specified in the Electrical Specifications. An. internal counter is started as a
result of the closure. The key operation begins after nine
word times if the key input is still at a Logical High Level.
As long as the key is held down (and the key input remains high) no further entry is allowed. When the key
input changes to a Logical Low Level, the internal counter
starts a sixteen word time-out for key release. During
both entry and release time-outs the key inputs are
sampled approximately every other word time for valid
levels. If they are found invalid, the counter is reset and
the calculator assumes the last valid key input state.
ERROR INDICATION
In the event of an operating error, the MM5760 will
display all zeros and all decimal points. In addition to
normal calculator overflow situations which occur as a
result of adding, subtracting, multiplying or dividing and
including division by zero, the error indication is displayed for the conditions of Table I.
One of the popular types of low-cost keyboards available, the elastomeric conductor type, has a key pressure
versus contact resistance characteristic that can generate
continuous noise during "teasing" or low pressure key
depressions. The MM5760 recognizes a series contact resistance up to 50 kD as a valid key closure, assuring a
reliable interface for that type of keyboard.
The Z-register is automatically cleared and the Y- and
M-registers are saved. An error condition is cleared by
depressing any key except "1 IX," "-';-," "LOG X" or
"LN X." Operation on the X register with an error
displayed will be performed as if X contained a zero_
KEY OPERATIONS
(Note: Register X is always displayed.)
AUTOMATIC DISPLAY CUTOFF
Clear Key, "C"
If no key is depressed for approximately 35 seconds, an
internal automatic display cutoff circuit will blank all
segments and display nine decimal points. Any key depression will restore the display; to restore the display
without modifying the status of the calculator, use two
change sign, "CS," depressions.
After any key except "ARC," it clears X, pushes Y
down to X, Z to Y and places a zero in Z. Subsequent
depressions perform the same function; thus, three "C"
depressions after a number entry will clear a completely
' ' ; ~ )'00
,---1
J~
----=!..:::: I ' '- ~
'~ _ _ _ _ _ _ _ _---IrVOH
READY
FIGURE 4. Ready Timing
NEW
KEY IS
DEPRESSED
1-~
t
SWI~~~
INPUT
jll
I
t
nL-.JnL-.JnJUU
L.,.
-------u------
~
"
IIJL-f
/
"NOISE"
READY
KEY IS
RElEASED
9WDRDS_
- "NOISE··
l
~
16WORDSAFTER
KEY RElEASE DR
AFT, ER CALCULATION
iS COMPLETE.
WHICHEVER IS
LONGER.
t~---------------~
NEW KEY HAS
BEEN ACCEPTED
BY CALCULATOR.
THE KEY MAY
BE RELEASED.
FIGURE 5. Functional Description of Ready Signal and Key Entry
J
I
t
NEXT KEY
CAN BE
ENTERED.
TABLE I. Conditions for Error Indication
FUNCTION
CONDITIONS (REGISTER X =0 X)
+,-,x,";-
Result> 99999999.
..;- or 1/X
IX I:::; 0.00000001
y'x
X1
Tan X
X = ±90°, or X :;:: 7 radians
Note: Qn 99999999 = 18.420680
full stack. This is also the method used to gain access to
the Z register. Memory register M is not affected by "C."
Pressing "C" after "ARC" resets the ARC function with·
out affecting any of the data registers ..
Subtraction Key, "-"
X is subtracted from Y and the result is placed in X.
Z is copied into Y, then cleared. Following an "ARC"
key, "-" subtracts the contents of X from M without
changing X, Y or Z.
Number Entries
Multiplication Key, "X"
First entry after "EN" clears X and enters the number
into Digit 8 (the second digit from the left of the display)
of X. Second through eighth entry (excluding a decimal
point) enters the number one digit to the right of the
last number entered. The ninth, and subsequent entries,
are ignored. The first number key after any key other
than "EN" loses Z, pushes Y up to Z, X to Y, clears X
and enters the number in Digit 8 of X.
X is multiplied by Y and the result is placed in X. Z is
transferred to Y and cleared. Following an "ARC" key,
"X" converts the value of X from radians to degrees
without changing M, Y or Z.
Division Key, "..;-"
X is divided into Y and the result is placed in X. Z is
transferred to Y and cleared. Following an "ARC" key,
"..;-" converts the value of X from degrees to radians
without changing M, y' or Z.
Decimal Point, "."
After an ENTER key, it clears X and displays a decimal
point in the left-most digit position. Following a number
entry, it places a decimal point to the right of the last
number entered. Subsequent depressions without an
interceding number entry are ignored; subsequent depressions after interceding number entries will replace
the previous point with one to the right of the last
entered number.
Pi Key, "n"
Register Z is lost; Y is pushed up to Z and X to Y. The
constant 3.1415926 is placed in X.
Exchange Key, "+-+"
Change Sign Key, "CS"
Registers X and Y are exchanged. Z and M are not
affected.
Changes the sign of X.
Inverse Trigonometric and Multifunction Key,
'~ARC"
Enter Key, "EN"
When used as a prefix to one of the trigonometric keys
it conditions the calculator to determine the inverse
function of the value in X. For example "ARC" followed
by "51 N" computes the angle that has a sine equal to the
value 'of X, replacing X with that angle in degrees. See
key descriptions of "+," "-," "X;" "";-," "y'x," "STO"
and "C" for secondary functions assigned to those keys
by preceding them with "ARC." "ARC" followed by
any key other than one of the above or one of the trig
functions will be ignored.
Register Z is lost; Y is pushed up to Z and X is copied
into Y.
Addition Key, "+"
X is added to Y and the result is placed in X. Z is
transferred to Y and cleared. Following an "ARC" key,
"+" adds the contents of X to M without changing X,
Yor Z.
8-32
replaces X with the result. The contents of Z are lost, Y
retains the exponent and Z is cleared. M is not affected.
Reciprocal Key, "1/X"
A non·zero value of X is replaced by its reciprocal.
Registers M, Y and Z are not altered.
Memory Keys, "STO" and "RCL"
"vx"
Logarithmic Keys, "LN" and "LOG"
The memory store key, "STO" copies the value of X
(including sign) into storage register M without altering
the stack. "STO" following "ARC" squares the value
of X and accumulates the result into M. Registers X, Y
and Z are not affected. The recall key, "RCL," transfers
Y to Z and X to Y, then copies Minto X. Storage
register M is not changed and Z is lost. Both "STO"
and "RCL" terminate the entry mode.
These keys replace the value of X by its natural or
common logarithm, respectively; register Z is lost. M is
not altered.
MEMORY OPERATIONS RESULTING IN
ERROR CONDITIONS
Square Root Key,
A positive value of X is replaced by its square root.
Registers Y and Z are not altered. Following an "ARC"
key,
replaces the value of X with its square.
Registers M, Y and Z are not affected.
"vx"
Exponential Key, "ex"
Any operation in which the storage register M is involved
that results in an error condition, will not affect the
previous contents of M. For example, if by accumulating
X into M(" ARC," "+") the contents of M will become
greater than 99999999., an error indication will occur
and the original contents of M are protected. As a result
of the overflow, registers X and Z will be lost an shown
in Table II.
Determines the value of 2.7182818 raised to the power
contained in register X, and places that value in X. The
contents of Z are lost and Z is cleared. M is not altered. '
Power Key, "Y x "
Determines the value of Y raised to the power of X and
TABLE ,II. Summary of Stack Operations
SINGLE FUNCTION OPERATIONS
0. ~. 0.··· 0. c:J
~
:~:-_lOST
[ffi]
AFTER
- - - OROTHER
NUMBER,
_ _ _ AFTER ANY
FUNCTION KEY,
GJ.8.0.LJ
o~
v+x~x
z~'___z
v,x-x
v_----,._~
'----=:::xY ____~
v' x -
x~
X
X
V x--o_ X
O--y--lOST
z~z
O--y-LOST
z~z
:==-x=::
x--y---X
f(X)~lOST
~lOST
•
Y
z--lr--- z
v--lr---Y
x--lc=~
8·33
. r-- LOST
z---1r---z
v--lr---Y
:=5-- x
TABLE II. Summary of Stack Operations (Cont'd)
SECOND FUNCTION SEQUENCES
~
FOlU1WED BY
~,c::J
~
FOLLOWED BY
0, G
• z
;;Jm-.-M
---s=------; ~
~
~
FOLLOWED BY
LOST
[RADIANSTDDEG~~S~
11.1
DEGREES
~~ RADIANS f
0
~
FOLLOWED BY
~
• z
I
Y
------x
~
FOLLOWED BY
CD
~
FOLLOWED BY
~, [§JOR~
D----y-LOST
z---A-z
------M
ARCSINX
COSX
( ARC
ARCTAN X
ERROR INDICATION
O----y-LOST
z---A-z
'X~S~
-------M
VX,
RANGE AND ACCURACY OF FUNCTIONS
X2) have eight digit accuracy. All results are
truncated. Table III summarizes range and accuracy of
the other functions. Arithmetic calculations will be
completed in less than 0.5 second; all others except
yx in less tha'n 2.5 seconds and, yx in less than 5 seconds.
The smallest magnitude that can be displayed is
±O.OOOOOOOl and the total range is from -99999999 to
+99999999. The arithmetic functions {+, -, x, +, 1/X,
TABLE III. Digit Accuracy for Various Functions
FUNCTION
RANGE
0
APPROXIMATE
ACCURACY (Note 1)
0
SIN, COS, TAN
"v -90 to "v 90
0
0
"v -360 to "v 360
7 Digits
6,Digits
ARC SIN and ARC COS
"v-1 to "v +1
6 Digits
ARC TAN
-99999999 to 99999999
6 Digits
LOG
X~O
6 Digits
eX
-28 ~ X ~ Qn 99999999
6 Digits
LN
X~O
6 Digits
VX
X~O
8 Digits
yX
y>O
X Qn Y ~ Qn 99999999
5 Digits
Note 1: Six digit accuracy, as an example, would be:
123456XX
L±1
n digit accuracy has the nth digit from the MSD bei ng displayed accurat.e within ± 1.
8-34
Calculators
MM5762 financial calculator
general description
the number of time periods in financial calculations.
M is an accumulating storage memory and is completely
independent of the others.
The single-chip MM5762 Business and Financial Calculator was developed using a metal-gate, P-channel
enhancement and depletion mode MOS/LSI technology
with low end-product cost as a primary objective. A
complete calculator as shown in Figure 1 requires only
the MM5762, a keyboard, DS8864 digit driver, NSA 1298
LED display, 9V battery and appropriate hardware.
Data is entered into the calculator in floating point
business notation. All entries and results are displayed
left justified with insignificant zeros to the right of the
decimal point suppressed. All intermediate results of a
chain calculation are floating point. Terminating keys
(such as equal, per cent, etc.) round the displayed result
to two decimal positions.
Keyboard decoding and key debounce circuitry, all
clock and timing generation and 7-segment output
display encoding are included on-chip and require\ no
external components. Segments can usually be driven
directly from the MM5762, as it typically sources
about 8.5 mA of peak current. [Note: The typical
duty cycle of each digit is 0.104; average LED segment
current is therefore approximately 0.104 (8.5 mAl. or
0.9 mA average. Correspondingly, the worse-case average
segment current is 0.104 (5.0 mAl, or 0.52 mA.l The
ninth digit (left-most) is used for the negative sign, or
the decimal point of a number less than unity.
features
•
An internal power-on clear circuit is included that clears
all registers, including the memory, when V DD and
Vss are initially applied to the chip.
Complete business and financial capability
•
Arithmetic functions: +, -, x, -:-
•
Power function: yX
•
Percent: both live percent and delta percent keys
•
Sum-of-digits capability for computing depreciation or "Rule of 78's" loan costs
•
Financial functions:
... "n" key, enters number of periods
... "i" key, enters interest rate per period
... "AMT" key, enters given amount
... "VAL" key, computes PV or FV
Trailing zero suppression allows convenient reading of
the left justified display, and conserves power. The
DS8864 digit driver is capable of sensing a low battery
voltage an'd providing a signal during Digit 9 time that
can be used to turn on one of the segments as an
indicator. Typical current drain of a complete calculator
displaying five "5's" is 30 mAo Automatic display
cutoff is included. If no key closure occurs for approximately 35 seconds, all numbers are blanked and all
decimal points are displayed.
... "SAV" key, computes deposit or sinking fund
amounts
... "LOAN"
amounts
key, computes payment or
•
Accumulating memory
•
•
Automatic constant
Convenient business (adding machine) entry notation
• Eight full digits
,. Power-on clear
The Ready output signal is used to indicate calculator
status. It is useful in providing synchronization information for testing or applications where the MM5762 is
used with other logic or integrated circuits; e.g., with
the MM5765 Programmer (Figure 3).
•
Automatic display cutoff
•
Low system cost
connection diagram
r!!- DIGIT4
OIGIT2.!.
~DIGIT5
DIGIT,2-
rll- DIGIT 6
K4.!.
tl!- DIGIT 7
KJ.l.
SWITCH
INPUTS
{
The user has access to six registers designated X, Y, A, I,
Nand M. The X-register is used for keyboard entry and
display. The Y and A-registers are used in multiply/
divide and add/subtract calculations, respectively. Interest
values are held in the I-register and the N-register stores
(DIP Top View)
J"'!'
DIGIT
Thirty-two keys are arranged in a four-by-nine matrix
as shown in Figure 1. There are the standard four function
keys (+, -, -:-, xl. Change Sign, Exchange, three accumulating memory control keys plus ten unique business or
financially oriented computation keys: three keys for
entering interest rate per period, number of periods and
amount, three keys for computing present and future
values, sinking funds, saving and loan payments and
other time/money factors, two keys for computing
per cent and delta per cent, a sum-of-digits key and a
power key. There is an automatic constant feature.
~DIGIT8
K2"':'
6
.,!1. DIGIT9
K,..!.
~READY
VDD.!.
r!!- SEGMENT 0
SEGMENT G..!.
~SEGMENTE
SEGMENT B.!.!!.
~SEGMENTA
t.!!. DECIMAL POINT
Vss..!.!.
t2L SEGMENT C
' - -_ _ _ _ _-1
SEGMENT F
l!..
Order Number MM5762N
See Package 22
8-35
loan
absolute maximum ratings
Voltage at Any Pin Relative to Vss.
(All other pins connected to Vss .)
Ambient Operating Temperature
Ambient Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Vss + 0.3V to Vss -;-12V
O°C to +70°C
-55°C to +150°C
300°C
operating voltage range
6.5V:::; Vss - V DD :::; 9.5V
Vss is always defined as the most positive supply voltage.
dc electrical characteristics
PARAMETER
Operating Supply Current (100)
Keyboard Scan I nput Levels
(Kl, K2, K3 and K4)
Logical High Level
Logical Low Level
Digit Output Levels
Logical High Level (V OH )
Logical Low Level (VoLl
CONDITIONS
Voo
V ss -6.5V:::; Voo ~ V ss -9.5V
Voo = V ss -6.5V
V DD = V ss -9·5V
RLoAo = 3.2 kD to Voo
V ss -6.5V:::; Voo :::; V ss -9·5V
V DD = V ss -6.5V
Voo
Segment 0!ltput Current
(Sa through Sg and Decimal Point)
Ready Output Levels
Logical High Level (V OH )
Logical Low Level (VoLl
MIN
8.0
= -0.4 mA
= 10pA
MAX
16.0
V ss --2.5
mA
V ss -6·0
V ss -6·0
V ss -7.0
V
V
V
Vss':"'1.5
-8.5
-10.0
-5.0
UNITS
V
V
V
V ss -5.0
= V ss -9·5V
TA = 25°C
V OUT = V ss -3.6V, Voo = V ss -6.5V
V OUT = V ss -5V. V DD = V ss -8V
V OUT = V ss -6.5V, Voo = V ss -9.5V
lOUT
lOUT
TYP
= V ss -9.5V. T A = 25°C
-15.0
V ss -1.0
V DD +l.0
mA
mA
mA
V
V
ac electrical charac,teristics
PARAMETER
CONDITIONS
Word Time (Figure 2)
TYP
MAX
0.32
0.75
2.0
ms
36
83
220
ps
4.5
14
:
Digit Time (Figure 2)
Segment Blanking Time (Figure 2)
2
Digit Output Transition Times
(t R1SE and t FALL )
CLOAD
= 100 pF,
Keyboard Inputs High to Low
T.ransition Time After
Key Release
CLOAO
= 100 pF
CLOAD
CLOAD
= 100 pF
= 100 pF
Rea.dy Output Propagation Time
(Figure 4)
Low to High Level (t PDH )
High to Low Level (t POL )
RLoAD
UNITS
MIN
= 9.6 kD
ps
2
ps
4
ps
I
10
Key Input Time·out (Figure 5)
Key Entry
Key Release
Display Cutoff Time
(The time after the last valid key
closure that all numbers will be
blanked and all decimal points
displayed.)
8-36
n
50
1
ps
ms
2.8
5.1
7.0
12
18
32
ms
ms
15
35
92
sec
Ir-----t----...,
REAr
IKI
Sa Sb Sc Sd S. SI
r-----tl~~
~N'
,
...... ~
"-yJ.!L·
.....
~
.....
~.
......
OP
Sg
SI
S.
Sd
Sc
Sb
Sa
NSA1298I
CI CI CI CI '-, '-, '-, I-' CI
VSS
9,. 9,. fl· fl· fl·/i!· fl· fl· fl·
'00
~-~T--;--r-+-+~~~r-r-n
~.......
.....
I
hI
MM5762
rl" "' " "' .. " "' " "' "
~.
r-~~~~~~~~~~~~~~
I
Sg OP
LV GNO Vee
INO
~
.....
.....
~
I--
~
"'o!-......
......
--
~....... ~....... ~.......
~....... ~
.,
~
~.....
~
~
.......
"o!-......
~.....
~T
~......
"o!-.....
.....
~.......
.......
.......
POWER
~
.....
.....
......
SOD
5
......
KEYBOARD
·Oualfunctionkeys.
FIGURE 1. Complete Calculator Schematic
:r---.
DIGIT
"
r-----------WOROTlME-------------l1
IU
OUT;
---l
I-OIGITTIME
02_1-_~
03
-+---+-~
09
DECIMAL
POINT-t---t----t-'
SEGMENTS
S.
-+--.......
Sb
Sc
Sd
s.
Sf
-+--..,...
-t---t-'
-t--~--r--~
Sg_~_......;...
C'-'CCI'-'-"
ACTUAL DISPLAY:
CI I CI
09
•
~I
-,
~'.C
SEGMENT
DESIGNATION
,
•
01
FIGURE 2. Display Timing Diagram
8-37
.~
\
LJ
DS8864
~......
=
+
9V
--'- MALLORY
!-I- - -
MNI604
OR
EDUIV .
1
FINANCIAL
CALCULATOR
Vss
~
K
INPUTS
SEGMENT
OUTPUTS
MM5762
DIGIT
OUTPUTS
DECIMAL
POINT
PROGRAM
Voo ~ MODE
SWITCH
READY
SEGMENTS
DECIMAL POINT
RUN
DIGIT
LOAD
(9)
~
OUTPUT
(9)
L.._ ~-~
DATA
I
4X 9
OATA
KEYBO ARD
AN 0
1X4
PROGRA MMER
CONT RDL
KEYBD ARD,
CONTROL
I
+
Vee
(9)
(8)
GND
READY
RUN/LOAD
Vss
K I/O's
Voo
,LED
ALARM
INDICATOR
J-
""'"
ALARM
LEARN MODE
PROGRAMMER
--..:-=-
DIGIT
-
MM5765
K5
9V
DS8864
INPUT
~
NSA1298
I, l, l,l,l,l, I, I, I,
C/. C/. C/. C/. C/. C/. C/. C/. C/.
(9)
r---h
I
i
LED
DISPLAY
(7)
POWER
SWITCH
ON
FIGURE 3. Low Cost Hand Held Programmable Financial Computer using the MM5762 Calculator and MM5765 Programmer
KEYBOARD BOUNCE AND NOISE REJECTION
AUTOMATIC DISPLAY CUTOFF
The MM5762 is designed to interface with most low
cost keyboards, which are often the least desirable from
a false or multiple entry standpoint.
If no key is depressed for approximately thirty-five
seconds, an internal automatic. display cutoff circuit
will blank all segments and display nine decimal points.
Any key depression will restore the display; ·to restore the
display without modifying the status of the calculator,
use two Change Sign key depressions.
A key closure is sensed by the calculator chip when
one of the key inputs, K1, K2, K3 or K4 are forced
more positive than the Logical High Level specified in
the electrical specifications. An internal counter is'
started as a result of the closure. The key operation
begins after nine word times if the key input is still at a
Logical High Level. As long as the key is held down
(and the key input remains high) no further ,entry is
allowed. When the key input changes to a Logical Low
Level, the internal counter starts a sixteen word time-out
for key release. During both entry and release time-outs
the key inputs are sampled approximately every other
word time for valid levels. If they are found invalid, the
counter is reset and the calculator assumes the last valid
key input state.
READY SIGNAL OPERATION
The Ready signal indicates calculator status. When the
calculator is in an "idle" state the output isat a Logical
High Level (near Vss ). When a key is closed, the internal
key entry timer is started. Ready remains high until the
time-out is completed and the key entry is accepted as
valid, then goes low as indicated in Figures 4 and 5. It
remains at a Logical Low Level until the function initiated
by the key is completed and the key is released. The low
, to high transition indicates the calculator has returned
to an idle'state anda new key can be entered ..
One of the popular types of low-cost keyboards available,
the elastomeric conductor type, has a key pressure
versus contact resistance characteristics that can generate
continuous noise during "teasing" or low pressure key
depressions. The MM5762 defines a, series contact
resistance up to 50 kfl as a valid key closure, assuring
a reliable interface for that type of keyboard.
'8-38
- ERROR INDICATION
In the event of an operating error, the MM5762 will
display all zeros and all decimal points. The error indication occurs if division by zero is attempted or either
a result or intermediate value exceeds 99999999.
FIGURE 4. Ready Timing
NEW
KEY IS
DEPRESSED
,
.
~
~
9~R~
KEY IS
RElEASED
~
.
I
~
SWI~~~---l-JUULJLJLJIp-~
/
INPUT
.,
"NOISE"
"NOISE"
l
READY
J
-------11------
~
16WOROSAFTER
KEY RElEASE OR
AFTER CALCULATION
ISCOMPU-LETE.
WHICHEVER IS
LONGER.
t~------------~
NEW KEY HAS
BEEN ACCEPTED
BY CALCULATOR.
THE KEY MAY
BE RElEASED.
I
t
NEXT KEY
CAN BE
ENTERED.
FIGURE 5. Functional Description of Ready Signal and Key Entry
The indication is cleared by depressing any key.
If an error results from a "+" or "-" key, the X-register
is cleared and the last entry is saved in the A-register; ,
all other registers are not effected. An error condition
during "x" or "7" operations clears X without changing
any of the other registers.
Overflow as a result of the "yx," "VAL," "SAV" or
"LOAN" keys clears the X-register and destroys the
values in N, I and A. Y is not changed.
An attempt to raise a negative number to a power will
cause the error indication to appear, the X-register will
be cleared and the exponent will be stored in Y. The
other registers are not changed.
appropriate terminator ("=," "%" or "= +" key). The
Y-register is used to store the constant in the constant
mode of operation.
The calculator automatically changes to the chain mode
when an "x" or "7" key occurs in the calculation. In the
chain mode, the result of each "x" or "7" key is stored
in both X and V-registers. A new entry replaces X without altering Y. At the completion of a chain calculation,
the V-register will contain the value used as first factor
of the last multiply, or the latest entry if the last
operation was a d,ivide.
Table I summarizes the four modes.
KEY OPERATIONS
Overflow as a result of "M+" destroys the value stored
in M, clears X and displays the error indication. Calculations are immediately stopped and other registers are
not cleared.
(Note: Register X is always displayed.)
Clear Key,
"c"
Following a number entry or a "MR" key, it clears the
X-register only (clear entry). Following any other key
it, clears registers X, Y and A.
AUTOMATIC CONSTANT
The MM5762 retains as a constant the first factor of
a multiplication calculation or the second factor of a
division calculation, when that calculation is terminated
by an "=" key, "%" key or "= +" key. Subsequent
calculations using the stored constant are made by
entering a number and ,operating upon it with the
Number Entries
The first entry clears the X-register and enters the
number into the LSD of X. Second through eighth
entries (excluding a decimal point) are entered one
·8-39
digit to the right of the last number. The ninth, and
subsequent entries are ignored. First entry after a "+,"
"-," or "M+" following a "+" or "-" key causes the
number in the X·register to be transferred to the
A-register before clearing and placing the new entry
in X.
Subtraction Key, "-"
If the previous key was not a "+" or "-" key, the
number in the X·register is subtracted from the number
in the A-register, X is transferred to A, and the difference
is stored in X. When the last key was a "+" or "-" key,
the number in A is subtracted from X without destroying
the value of A. The result is stored in X. '
Decimal Point, "."
Multiplication Key, "x"
As the first depression of a number entry, it clears the
X-register and places a point in the leftmost digit. If
the previous key was a number, it enters a decimal
point to the right of the last number entered. Following
a "+," "-," or those keys preceding a "M+" key, the
X-register is transferred to A, cleared and a decimal
point entered in the leftmost digit. The last decimal
point depression in a single number entry is accepted
as the valid point.
If there has not been a "x" or ".,." key since the last
terminator key ("=," "= +" or "%"), the value of the
X·register is copied into the Y ·register and the calculator
is set to the chain multiply mode. In a chain calculation
in which there has been a "x" key since the last terminator or ".,." key, X is multiplied by Y and the resulting
product is stored in both X and Y; if a ".,." key has
occured since the last terminator or "x" key, depression
of "x" will divide the Y·register by the X·register, with
the quotient stored in both X and Y.
Change Sign Key, "CS"
Division Key, ".,."
Changes sign of register X.
If there has not been an "x" or ""''' key since the last
terminator key ("=," "= +" or "%"), the value of the
X·register is copied into the Y·register and the calculator
is set to the chain divide mode. In a chain calculation
if an "x" key has occured since the last terminator or
".,." key, X is multiplied by' Y and the product is stored
in both X and Y; if a ".,." key has occured since the last
terminator or "x" key, depression of ".,." will divide
the Y·register by the X·register, with the quotient stored
in both X and Y.
Addition Key, "+"
If the previous key was not a "+" or "-" key, the number
in the A·register is added to the X-register, X is transferred to A, and the sum is stored in X. When the last
key was a "+" or "-" key, the number in A is added to
the number in X without destroying the value of A.
The sum is stored in X.
TABLE 1. Mode Summary
MODE
KEYS THAT
SET MODE
DESCRIPTION
(See Calculation Examples)
Depression of an "=," "= +" or "%" key will multiply
the X-register by the V-register and replace X with· the
product. V remains unchanged.
CONSTANT
MULTIPLV
CLEAR
=
=+
%
A
Vx
SOD
VAL
SAV
LOAN
CHAIN
MULTIPLV
x,
Following a terminator or "..;."
or "x" operation
Depression of an "=," "= +" or "%" key will mul~iply
the X-register by the V-register and place the product in
X. V remains unchanged.
CONSTANT
DIVIDE
=
=+
%
With calculator
previously in chain
divide mode.
Depression of an "=," "= +" or "%" key will divide the
X-register by the V-register and replace X with the
quotient. V is unchanged.
. Following a terminator or "..;."
or "x" operation
Depression of an "=," "= +" or "%" key will divide the
V·register by the X-register, tra~sfer X to Y, and place
the quotient in X.
CHAIN
DIVIDE
}
8-40
Equal Key, "="
Power Key, "y X "
In the chain multiply mode, the value in the X-register
is mUltiplied by the V-register with the product stored
in X. Register Y remains unchanged. In the chain
divide mode, depression of "=" will divide Y by X,
transfer X to Y, and place the quotient in X. If the
calculator is in constant multiply, "=" will multiply X
by Y, place the product in X and retain Y. For constant
divide, the X-register is divided by Y, the quotient is
stored in X; Y is unchanged.
When the calculator IS In either the chain or constant
mUltiply modes, depression of "yX" raises the number
in the Y -register to the power of the X-register and
replaces X with the result. (Thus, to raise two to the
fifth power, use the sequence: "2," "x," "5," "yx .")
If the calculator is in the constant or chain divide modes,
the value of Y is raised to the inverse of X power; i.e.,
the key sequence "5," "-;-," "2," "yx ," results in the
calculation of 5 raised to the 1 /2 power. The original
value of X is retained in Y and register A is cleared.
The calculator is set to the constant multiply mode.
Results computed with the "Y x " key are rounded to
five places.
The "=" key always rounds the answer stored in X to
two places to the right of the decimal point, and clears
register A.
Exchange Key, "<,-+"
Percent Key, "%"
The X and V-registers are exchanged. No other registers
are effected.
This key acts exactly like the "=" key except the value
of X is divided bV 100 and copied into register A
before performing the required operation. Register A is
not cleared. The result stored in the X-register is
rounded to two decimal positions.
Interest Entry Key, "i"
If the sign of the number in the X-register is positive,
"i" divides the number by 1 00 and stores the quotient
in X and the I-register. If the value of X is initially
negative, "i" changes the sign, divides by 1200 and
stores the quotient in both X and I; i.e., the interest
will be compounded monthly.
Automatic Accumulation Key, "= +"
It acts just like the "=" key in all modes. After the
result is stored in X, the value of X is added to the
number in the M-register. The result stored in X and
accumulated into M is rounded to two decimal places.
Register A is cleared.
Number of Periods Entry Key, "n"
If the sign of the number in the X-register is positive,
X is copied into register N. A negative value of X is
changed to a positive number, multiplied by 12 and the
product stored in Nand X.
Memory Plus Key, "M+"
The number in the X-register is accumulated into the
M-register. Registers X and A are not changed, so the
repeat addition or subtraction conditions that existed
before accumulation to memory are still valid.
Amount Entry Key, "AMT"
The value of the X-register is copied into the V-register.
No other registers are effected.
Memory Recall/Memory Clear Key, "MR"
Value Key, "VAL"
Following any key except "M R," the value of the Mregister is copied into the X-register. If the preceding
key was "+," "-" or "M+" following "+" or "-," the
number in the X-register .is transferred to the A-register
before M is recalled. Following another "MR" key, the
M-register is transferred to X, then cleared.
If the number in the X-register is positive, the "VAL"
key will compute future value: the sum of money
available at the end of n periods from the present date
(N-register) that is equivalent to the present amount
(Y-register) with interest i (I-register). When the sign of
the number in X is negative, the "VAL" key will compute
present value: the sum of money necessary today to
accumulate the future amount contained in Y over the
n periods of N at the interest rate per interest period that
is stored in I. Thus, to compute future value, simply
enter i, n and amount in any order and press "VAL."
For present value, precede "VAL" with "CS," setting
a negative sign in X. Registers Y, N and I are not altered;
X is replaced by the computed value and register A is
cleared. The calculator is set to the constant multiply
mode. The result is rounded to two decimal places.
Delta Percent Key, "b.."
The value of X is subtracted from the V-register, the
difference is divided by the value of X and placed in X.
The new value of X is multipl ied by 100 and rounded to
two digit places. Y retains the difference between the
original values of X and Y; register A is unchanged.
Calculator mode is set to constant multiply.
8-41
~_r--------------------------------------------------------------------------------------------------
,....
(0
J.t)
~
~
Savi~gs
Deposit Key, "SA V"
If the number in the X-register is negative, the "SAV"
key will compute the amount to be deposited at the
\ end of each period in a sinking fund for the number of
periods, n, conta'ined in register N, at an interest rate, i,
contained in register I, compounded each time period,
to accumulate the desired amount, contained in register
Y. When the sign of the number in X is positive, the
"SA V" key will compute the amount in a sinking fund
if the number in Y is deposited at' the end of n time
periods (N-register) at an interest rate per time period i
(I-register), compounded each time period. Thus, to
compute the required sinking fund deposit to accumulate
'a desired amount over a given period of time, enter i, n
and the amount in any order using the "i," "n" and
"AMT" keys, then "CS" and "SAV," To find the
amount in the sinking fund, simply enter i, n and the
periodic amount of deposit and press "SAV." Registers
N, I or Yare not altered by the calculation, register A
is cleared and register X contains the computed value.
The calculator is set to the constant mUltiply mode.
Results are rounded to two decimal places.
depreciation and depreciable value amounts using the
original value of N and present values stored in Nand A.
N is decremented by one after each computation. The
number to be depreciated (or the loan amount in a
"Rule. of 78's" interest calculation) is always entered
with a "+" or "-" key and the number of periods with
the "n" key, without regard to key order. If the key
preceding "SOD" is not "+" or "-," the sum-of:digits
computation is performed on the number in the A-register
without the number in X first being transferred to A.
The result will be rounded to two decimal places; calculator mode is set to constant multiply.
EXAMPLES
1. Addition or subtraction
KEYS
Loan Installment Key, "LOAN"
If the number in the X-register is negative, the "LOAN"
key will compute the end-of-period payment or receipt
required over the number of time periods contained in
the N-register at an interest rate per time period equal
to the value in the I-register to support a loan equal to
the amount stored in the V-register. When the sign of
the X-register is positive, "LOAN" computes the amount
that can be loaned for a given end-of-period payment
stored in Y over the number of time periods contained in
N at the interest rate per time period of I, compounded
each time period. Thus, to compute the required installment on a given loan, enter the amount of the loan
using the "AMT" key, the interest rate using "i" and
the number of periods with "n," press "CS" to enter a
negative sign in register X, then "LOAN." To compute
how much can be borrowed given a fixed payment,
enter the payment amount, number of periods and
interest rate, then "LOAN." "AMT," "i" or "n" can
always be entered in any order. Registers N, I or Yare
not altered by the calculation; register A is cleared and
register X will contain the computed value. The calculator
is set to the constant multiply mode. The result is
rounded to two decimal places.
DISPLAY
2.0
3.2
-12.3
COMMENTS
2
2.
3
3.
3.2
5.2
1
12
12.
12.3
-7.1
Note adding machine notation
2. Repeat add or subtract
KEYS
DISPLAY
COMMENTS
3
3.
3.1
3.1
6.2
9.3
6;2
3. Chain multiplication or
divi~ion
Sum-of-Digits Key, "SOD"
KEYS
Following a "+'~ or "-'~ key, it transfers the number in
register X to register A and computes a first sum-of:digits
depreciation on that number by multiplying it by the
ratio of the number in the N-register to the sum-of-digits
of N. The result is rounded to two decimal places and
stored in X; the difference between the initial and final
values of X, the depreciable value, is stored in registers Y
and A. N is decremented by one_ (Therefore, to find
depreciable value, simply us~ the "+-+" key.) Subsequent
depressions of the "SOD" key will compute successive
a)
x
3
8-42 '
DISPLAY
1
1.
2
2.
3
3.
3.1
6.2
4
4.
4.2
26.04
COMMENTS
6. Calculate percentage.
EXAMPLES (continued)
KEYS
3 .. (continued)
KEYS
b)
1
0
1
0
c)
COMMENTS
DISPLAY
1
10
10.
2
5.
1
10
.5
2
.25
5
%
KEYS
5
%
"=" rounds to two
decimal places.
COMMENTS
DISPLAY
3
3.
%
2
6.
4
12.
5
5.
5.2
15.6
46.8
KEYS
1
2
CS
15.6 is re-entered and
3
multiplied by constant
CS
5
CS
6
. Second factor in constant divide
+ 4) x (3 + 2)/(6 + 7)
DISPLAY
+
4
5
5.
4
9.
9.
3
3.
2
5.
45.
5% of 125 is displayed
125 + 5% is displayed
5
53
532
5 3 2.
5 3 2.1
5 3 2.1
6
3 1.93
500.17
6% of 532.1 is displayed
532.1 - 6% is displayed
DlS'PLAY
1
12
-12
-123
-123.
123.
123.5
-123.5
-1 23.56
COMMENTS
{ Change sign does not
terminate entry.
9. Perform exchange registers (X ++ V).
KEYS
DISPLAY
COMMENTS
a)
5.
2.6 is re-entered and
divided by constant
3
1 5.
4
5.
2 O.
5. To perform products of sums.
KEYS
1
12
125.
125.
5
6.25
131.25
8. Perform change sign.
First factor in constant multiply
5
5.
2
2.5
4
2.
5
5.
5.2
2.6
1.3
(5
COMMENTS
b) Discount: $532.10 by 6%
5
3
b)
DISPLAY
.a) Add·On: $125 plus 5%
4. Constant multiplication or division.
KEYS
"Live %" key
7. Perform add on and discount
2
20
2 O.
4
8 O.
8
10.
7
1.4285714
4
5.71
a)
COMMENTS
DISPLAY
3
30
300
300.
300.2
300.25
300.25
5
15.01
=
?
b)
6
6.
3
6.
.5
COMMENTS
5 is initially constant multiplier
4 is now constant multiplier
Numerator and denominator
{ are exchanged
10. Accumulate in memory, recall and clear memory
Chain multiply mode is set
KEYS
a)
M+
(5 + 4) x (3 + 2) is executed
4
6
M+
6.
7
13.
3.4 6
MR
MR
MR
5
45+ (6 + 7) is executed
8-43
DISPLAY
3
3.
4
4.
5
7.
7.
O.
COMMENTS
Accumulate in memory
Accumulate in memory
Recall memory
Recall and clear memory
Recall and clear memory
N
CD
'"~
\!)
~
EXAMPLES (continued)
13. Raising a number to a fractional power.
KEYS
10. (continued)
KEYS
b)
+
M+
7
+
M+
2
CS
M+
9
MR
MR
MR
MR
DISPLAY
5
5.
6
11.
11.
7
18.
18.
25.
3
32
32.
32.2
-32.2
-32.2
9
34.
-3.2
30.8
-3.2
-3.2
o.
COMMENTS
2
Y"
Accumulate in memory
3
y"
11 + 18 is accumulated in M
Repeat add
=+
'x
3
=+
=+
9
CS
=+
MR
Accum41ated value of M is recalled
M is cleared
a)
COMMENTS
5 x 3 = 15 is added to M
b)
12.6 is added to M
c)
{ Rounded to 2 decimal places
and added to memory
d)
{ Note method of multiplying
negative number
c) 3- 5 =
5.25
CS
i
2500
AMT
VAL
3000
AMT
VAL
3000
300 O.
4807.04
5
CS
i
VAL
10
CS
10
-10
120.
4941.02
New deposit stored in Y
New interest rate in I
Enter 10 x 12 in N
To find the amount to be deposited to accumulate a)
$5000 in 7 years at 4.5% interest compounded monthly.
b) $10,000. c) $10,000 in 7.5 years.
COMMENTS
KEYS
3
3.
5
-5
.00412
-5
.00416666
4700.53
COMMENTS
Number of years
Compounded monthly
Store 9 x 12 in N
Interest
Compounded monthly
Store 5.25/1200 in I
Original deposit
Store in Y
Rounded .to two decimal places
2. Present Value Computations
a)
b)
Rounded to five digits;trailing
zero is suppressed
0.00412
5
CS
y"
DISPLAY
9
--9
108.
5.25
-5.25
.004375
2500
2500
4005.87
VAL
b) 51.5 = 11.18
y"
9
CS
-36. added to memory
2
2.
5
32.
5
5.
1
1.
1.5
11.18
Rounded to five digits
To find the accumulated amount in a savings account
at the end of 9 years when a) $2500.00 is deposited
at 5.25% interest compounded monthly. b) $3000.
C) $3000 at 5.00% interest. d) $3000 at 5.00% interest
for 10 years.
Accumulated value of M is recalled
a) 25 = 32
5
y"
6
6.
3
1.8171
1. Future Value Computations
DISPLAY
DISPLAY
Rounded to five digits
29 - 32.2 is accumulated in M
12. Raising a number to a power.
KEYS
5
5.
2
2.2361
FINANCIAL EXAMPLES
KEYS
5
5.
3
15.
4
4.
4.2
4.2
3
12.6
6
6.
7
.86
9
-g
--9.
4
-36.
-7.54
COMMENTS
b) 6 1/ 3 = 1.8171
11. Accumulate in memory with the use of the "=+" key.
KEYS
DISPLAY
a) 5 1/ 2 = 2.2361
/"
c)
Rounded to five digits
8-44
7
CS
DISPLAY
COMMENTS
4.5
CS
i
5000
AMT
CS
VAL
7
-7
84.
4.5
-4.5
.00375
5000
5000.
-5000.
3651.1
10000
AMT
CS
VAL
10000
10000.
.-10000.
7302.19
Present value required
7.5
CS
n
CS
VAL
7.5
-7.5
90:
-90.
7140.03
Present value required
Number of years
Compounded monthly
Enter 7 x 12 in N
Interest
Compounded monthly
Enter 4.5/1200 in I
Future value
Enter amount in Y
Present value required
New future value in Y
New time period in N
FINANCIAL EXAMPLES (continued)
5. (continued)
KEYS
3. To find the amount that a) must be deposited
monthly in a savings account at an interest rate of
5.5% compounded monthly for 5 years to accumulate
$15,000. b) compounded, and deposited quarterly.
a)
KEYS
DISPLAY
5.5
CS
5.5
-5.5
.0 458333
5
CS
n
15000
AMT
CS'
SAV
b)
5
-5
60.
150
150 O.
-150 O.
21 7.77
a o.
a
a
4
1.375
Compound quarterly
Use ".,." instead of "="
for maximum accuracy
Enter 5.5/400
Terminate chain calcula·
tion
Number of years
.0 1 375
C
5
n
15000
AMT
CS
SAV
}
5.
4
2 O.
2 O.
15000
15
-15
O.
656.71
a a o.
aa
KEYS
DISPLAY
4.75
CS
4.75
-4.75
.0 3 9 5 8 3 3
6
CS
n
100
AMT
SAV
b)
7.5
CS
c)
4.75
CS
SAV
9
CS
n
SAV
a
b)
c)
Enter 5 x 4 in N
Re·enter FV in Y
Amount
CS
-9
.0
3
3
-3
4
CS
COMMENTS
i
5
b)
CS
n
5000
AMT
CS
LOAN
56500
AMT
49750
30000
AMT
49750
A
KEYS
3500
108.
1 3443.1 7
5000
5 a a o.
-5 a a O.
1 26.97
a 2 3.1
120
120.
4822.1 7
675
60.
COMMENTS
Interest
Compounded monthly
9/1200 entered in I
Number of years
Compounded monthly
3 x 12 entered in N
Payment amount entered in Y
Loan amount is computed
New number of periods
{ entered in N
New payment amount
{ entered in Y
DISPLAY
COMMENTS
56500
5650 O.
49750
13.57
6750.
Present value
Enter in Y
Past value
% change
Amount change
30000
New present value
3
a a a o.
49750
-39.7
-19750.
Negative % change
Amount change
8. Performing a sum-of-digits depreciation. Find the
depreciation and depreciable value for each year, on
an item with an initial cost of $3,500.00 and a salv~ge
value at the end of 8 years of $675.00
Accumulated sinking fund
a
5
-5
New monthly installment
4
-4
120
AMT
LOAN
A
Interest
Compounded monthly
4.75/1200 entered in I
9
-9
DISPLAY
36.
125
125.
393 0.8 5
5
KEYS
a)
4.75
-4.75
.0 3 9 5 8 3 3
18
-'18
.0 15
a7 5
LOAN
DISPLAY
3500
3500
675
2825.
8
8.
SOD
SOD
COMMENTS
SOD
18
CS
New interest entered in I
7. To find the amount of change and the percent change
of a house now valued at $56,500 which was previously
purchased for $49,750. b) present value of $30,000.
Quarterly deposit required
7.5
-7.5
9 O.
10 7 8 6.37
KEYS
COMMENTS
Compound quarterly
5. To find the monthly payments of a loan of $5,000
at an annual percentage rate of a) 18% for 5 years,
b) 12%.
a)
DISPLAY
9
48.
6
-6
72.
100
100.
8311.93
9
CS
n
125
AMT
LOAN
4. To find the amount accumulated a) if $100 is
deposited at the end of each month for 6 years in a
savings account at an interest rate of 4.75%, compounded monthly, b) at 7.5%, c) at 4.75% for 9 years.
a)
.0 1
-.0 1
1 1 1.22
KEYS
a)
Monthly deposit required
Interest
DlSPLA Y
12
-12
6. To find the amount of a loan with monthly payments
of $125, and an interest rate of 9% for 3 years. b) 4
years. c) $120 for 4 years.
Interest
Compound monthly
Enter 5.5/1200
Number of years
Compound monthly
Ent5x12inN
Future value
Entered in Y
5.5
5.5
12
CS
CS
LOAN
COMMENTS
a
5.5
b)
Interest
Compounded monthly
18/1200 entered in I
Number of years
Compounded monthly
5 x 12 entered in N
Loan amount
Entered in Y
SOD
SOD
SOD
SOD
SOD
Required monthly installment;
rounded to two decimal places
627.78
2 1 97.22
549.31
1647.91
47 0.8 3
11 77.0 8
392.36
784.72
313.89
47 0.83
235.4 2
235.4 1
156.94
78.4 7
78.47
O.
8-45
COMMENTS
Enter initial value
Enter salvage value
Calculate change
Enter period in N
1st year depreciation.
Rounded to two decimal
places
Depreciable value
2nd year depreciation
Depreciable val ue
3rd year depreciation
Depreciable value
4th year depreciation
Depreciable value
5th year depreciation
Depreciable value
6th year depreciation
Depreciable value
7th year depreciation
Depreciable value
8th year depreciation
Depreciable val ue
Calculators
MM5763 statistical calculator
general description
chain calculation are floating point. Terminating keys:
equal, percent and "= +" round the display result to two
decimal places.
The single-chip MM5763 Statistical Calculator was
developed using a metal-ga'te, P-channel enhancement
and depletion mode MaS/LSI technology with low
end-product cost as a primary objective. A complete
calculator as shown in Figure 1 requires only the
MM5763, a keyboard, DS8864 digit driver, NSA 1298
LED display, 9V battery and appropriate hardware.
features
•
Complete business and statistical capability
•
Keyboard decoding and key debounce circuitry, all
clock and timing generation and 7·segment output
display encoding are included on·chip and require no
external components. Segments can usually be driven
directly from the MM5763, as it typically sources about
8.5 mA of peak current. [Note: The typical duty cycle
of each digit is 0.104; average LED segment current is
therefore approximately 0.104 (8.5 mA), or 0.9 mA
average. Correspondingly the worse-case average segment
current is 0.104 (5.0 mAl, or 0.52 mA.] The ninth digit
(left-most) is used for the negative sign, or the decimal
roint of a number less than unity.
Arithmetic functions +, -, x, 7
•
Per cent: includes markup and discount
•
Statistical fu.nctions:
A "~x" key sums X, X2 and N
A "~y" key sums Y, y2 and X • Y
A
"REMOVE x" key corrects "~x" mistake
"REMOVE y" key corrects "~y" mistake
"FREQ x" key sums grouped data for standard
deviation
A "5<, SO" key calculates standard deviation and
mean
A "COR-SLOPE" key performs linear regression
giving coefficient of correlation, slope, and
intercept
A "INT" key calculates y-inte~cept on line for
given x
A
A
An internal power-on clear circuit is included that clears
all registers, including the memory, when V DD and "ss
are initially applied to the chip.
Trailing zero suppresion allows convenie'nt reading of the
left justified display, and conserves power. The DS8864
digit driver is capable of sensing a low battery voltage
and providing a signal during Digit 9 time that can be
used to turn on one of the segments as an indicator.
Typical current drain of a c9mplete calculator displaying
five "5's" is 30 mAo Automatic display cutoff is included.
If no key closure occurs for approximately 25- seconds,
all numbers are blanked and all decimal points displayed.
•
•
Square root
Accumulating memory
•
Auto constant
•
Business notation
• +, - "adding machine" notation
•
The Ready output signal is used to indicate calculator
status. It is useful in providing synchronization information for testing or applications where the MM5763 is
used with other logic or integrated circuits; e.g., with the
MM5765 Programmer (Figure 3).
'
x, 7, = algebraic notation
•
Eight full digits
•
Power-on clear
•
Display cutoff
•
Low system cost
connection diagram
DIGIT 3...!...
~DIGIT5
DIGITl2.
rE-DIGIT6
SWITCH
The user has access to eight registers designated X, T,
A, C, Y, S; Nand M. The X-register .is used for
keyboard entry and display. The T and A-registers
are used in multiply/divide and add/subtract calculations,
respectively. C, Y, Sand N-registers are used specifically
for calculating the statistical functions. M is an accumulating storage memory. Statistical key functions, use
essentially all registers, including M.
INPUTS
r~
K3...!.
.!!..DlGIT1
l2.DIGIT 8
6
KZ-
..!!.DIGIT9
Kl.2..
.!!.READV
Veo..!.
r1!-SEGMEN'TD
..!.
.!!.SEGMENTE
SEGMENT8~
~SEGMENTA
SEGMENTF.!.!..
~ DECIMAL PDINT
SEGMENTG
Data is entered into the calculator in floating point
business notation. All entries and results are displayed
left justified with insignificant zeros to the right of the
decimal point suppressed. All intermediate results of a
~DIGIT4
z.2..
DIGIT
Thirty-two keys are arranged in a fo~r-by-nine matrix
as shown in Figure 1. There is an automatic constant
feature.
(DIP Top View)
Vss!!.
~SEGMENTC
Order Number MM5763N
See Package 22
8-46
REyY
I
Kl
K2
K3
~K4
,
~....
Sa Sh Sc
S~
:1
Se Sf Sg dp
MMS163
01 01 03 04 OS 06 01 08 09
~
~....
f'c.S-.....
~.....
~.
~D'
~......
~....
dp
I
~....
~......
S"
'
......
.....
s,
NSA12981
-.:;.
-
~......
0 ~
POWER
OS8864
~.....
~x
5
.....
KEVBOARD
'OuaIIIlIlC1IUII kcv~
FIGURE 1. Complete Calculator Schematic
f---------~-WORO
TIM,
-----------j
02
D3
Sb
--
~...... ~.....
~v
S,
t-
~.... ~...... ~..... ~....
.....
Sd
t--
j'o:. ~
~.... ~'
.....
....
....
~......
SI
I
LV GND Vee
INO
..... ~..... ~......
r--o:-......
S'I
nnnnnnnnn
C~C~C~C~C~C~C~C~/~.
-+--+--.;..!
D9
DECIMAL
POINT-4-_-+-_--:f-I
S'-+_ _...:..I
Sb
Sc
S'-+_ _41
S'-I_ _-+__+-__f-I
S9--:_ _....:..I
ACTUAL DISPLAY:
SEGMENT
DESIGNATIDN
D9 __
• ----------Dl
FIGURE 2. Display Timing Diagram.
8-48
9V
MALLORY
MN1604
DR
EDUIV
absolute maximum ratings
Voltage at Any Pin Relative to Vss. (All other
pins connected to Vss )
Ambient Operating Temperature
Ambient Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Vss + 0.3V to Vss - 12.0
O°C to +70°C
-55°C to +150°C
300°C
operating voltage range
6.5V:::; Vss - Voo :::; 9.5V
Vss always defined as most positive supply voltage.
dc electrical characteristics
PARAMETER
Operating Supply Current (1 00 )
Keyboard Scan Input Levels
(K 1. K2. K3 and K4)
Logical High Level
Logical Low Level
Digit Output Levels
Logical High Level (V OH )
Logical Low Level (VOL)
Segment Output Current
(Sa through Sg and Decimal Point)
Ready Output Levels
Logical High Level (V OH )
Logical' Low Level (VOL)
CONDITIONS
MIN
Voo = V ss -9.5V. TA.= 2SoC
.
V ss -6.5V s:; Voo
Voo = V ss -6.5V
Voo = V ss -9.5V
TVP
MAX
B.O
16.0
UNITS
mA
,
s:; V ss -9.5V
V ss -2.5
V~;:;-5.0
V~~; --6.0
R LOAo ~·3.2 kQ to Voo
V ss -6.5V s:; Voo s:; V ss -9.5V
Voo = V ss -6.5V
Voo = V ss -9.5V
T A = 25°C
V OUT = Vss-3.6V. Voo = V ss -6.5V
V OUT = V ss -5V. Voo = V ss -8V
V OUT = V ss -6.5V. Voo = V ss -9.5V
louT ~ -0.4 mA
lOUT = 10J..(A
V ss -l.5
V!;~; -6.0
V!;~;--7.0
-5.0
-8.5
-10.0
- lS.0
V ss -1.0
Voot1.0
V
V
V
V
V
V
mA
mA
mA
V
V
ac electrical characteristics
PARAMETER
MIN
TVP
MAX
Word Time (Figure 2)
0.32
0.8
2.0
ms
Digit Time (Figure 2)
36
89
222
J..(s
Segment Blanking Time (Figure 2)
2
5.5
14
J..(s
Digit Output Transition Times
CONDITIONS
C LOAO = 100 pF. RLoAo = 9.6 kQ
UNITS
2
J..(s
4
J..(s
(tRISE and tFALL)
Keyboard Inputs High to Low
Transition Time After
Key Release
C LOAO
= 100 pF
Ready Output Propagation Time
(Figure 3)
Low to High Level (tPOH )
High to Low Level (tPOL )
C LOAD = 100 pF
C LOAD = 100 pF
10
Key Input Time-out
Key Entry
Key Release
Display Cutoff Time
(The time after the last valid key
closure that all numbers will be
blanked and all decimal points
displayed.)
8·47
50
1
J..(S
ms
2.8
5.1
7.2
12.8
18
32
ms
ms
10
25
63
sec
14
Vss
K
INPUTS
SEGMENT
OUTPUTS
MM576J
DIGIT
OUTPUTS
"""",~
POINT
Voo
LED
DISPLAY
!
CALCULATDR
PROGRAM
MODE
SWITCH
READY
(71
:1 """'""'''
,,"",m
'.U"
nnnnnnnnn
RUN
Ct. C/. C/. C/. Ct. Ct. Ct. Ct. C/.
LOAD
DIGIT
(91
191
~
r---h
I
;
(91
L._ f--:..J
DATA
I
4X 9
DAT A
KEYBO ARD
AN 0
1 X4
PROGRA MMER
CONT ROL
KEYBO ARD,
~
CONTROL
(91
READY
RUNILOAD
Vss
KilO',
r
'r
(81
I+- -
NPUT
OUTPUT
I
Voo
GNO
--=-
"'J
DRIVER
ALARM
LEO
ALARM
INDICATOR
LEARN MODE
PROGRAMMER
9V
OS8864
MM5765
K5
-...:-+
Vee
POWER
SWITCH
ON
FIGURE 3. Low Cost Handheld Programmable Statistician Computer Using the MM5763 Calculator and MM5765 Programmer.
KEYBOARD BOUNCE AND NOISE REJECTION
to high transition indicates the calculator has returned to
an idle state and a new key can be entered.
The MM5763 is designed to interface with most low
cost keyboards, which are often the least desirable
from a false or multiple entry standpoint.
ERROR INDICATION
In the event of an operating error, the MM5763 will
display all zeros and all decimal points. The error
indication occurs if division' by zero is attempted or
either a result or intermediate value exceeds 99999999.
A key closure is sensed by the calculator chip. when
one of the key inputs, K 1, K2, K3 or K4 arc forced
more positive than the Logical High Level specified in
the electric'al specifications. An internal counter is
started as a result of the closure. The key ope~ation
begins after nine word times if the key input is still
at a Logical High Level. As long as the key is held
down (and the key input remains high) no further
entry is allowed. When the key input changes to a
Logical Low Level, the internal counter starts a sixteen
word time-out for key release. During both entry and
release time-outs the key inputs are sampled approximately every other word time for valid levels. If they
are found invalid, the counter is reset and the calculator
assumes the last valid key input state.
The indication is cleared by depressing any key.
If an error results from a "+" or "-" k~y, the X-register
is cleared and the last entry is saved in the A-register; all
other registers are not effected. An error condition
during "x" or ",;-" operations clears X without changing
any of the other registers.
Overflow as a result of the statistical keys can effect
any ,register they use; "CA" should be depressed if an
error occurs,
One of the popular types of low-cost keyboards available,
the elastomeric conductor type, has a key pressure
versus contact resistance characteristic that c'an generate·
continuous noise during "teasing" or low pressure key
depressions. The MM5763 defines -a series contact
resistance up to 50 k!1 as a valid key closure, assuring a
reliable interface for that type of keyboard.
AUTOMATIC DISPLAY CUTOFF
If no key is depressed for approximately twenty-five
seconds, an internal automatic display cutoff circuit
will blank all segments and display nine decimal points.
Any key depression will restore the display; to restore
the display without modifying the status of the calculator,
use two Change Sign key depressions.
Overflow as a result of "M+" saves the value stored in M,
clears X and displays the error indication. Calculations
are immediately stopped and other registers are not
cleared.
AUTOMATIC CONSTANT
The MM5763 retains as a constant the first factor of a
multiplication calculation or the second factor of, a
division calculation, when that calculation is terminated
by ,,=,,' key, "%" key or "= +" key. Subsequent
calculations using the stored constant are made by
entering a number and operating upon it with the
appropriate terminator ("=," "%" or "= +" key). The
T-register is used to store the constant in the constant
mode of operation.
The calculator automatically changes to the chain mode
when a "x" or ",;-" key occurs in the calculation. In
the chain mode, the result of each "x" or "";",' key is
stored in both X and T-registers. A new entry replaces
X without altering T. At the completion of a chain
calculation, the T-register will contain the value used as
first factor of the last multiply, orthe latest entry if the
last operation was a divide.
READY SIGNAL OPERATION
The Ready signal indicates calculator status. When the
calculator is in an "idle" state the output is at a Logical
High Level (near Vss ). When a key is closed, the internal
key entry timer is started. Ready remains high until the
time-out is completed and the key entry is accepted as
valid, then goes low as indicated in Figures 4 and 5. It
remains at a Logical Low Level until the functi on initiated
by the key is completed and the key is released. The low
Table I summarizes the four modes.
8-49
TABLE I. Mode Summary
KEYS THAT
'SET MODE
MODE
CONSTANT
MULTIPLY
DESCRIPTION
(See Calculation Examples)
Depression of an "=," ".= +" or "%" key will multiply
the X·register by the T·register and repl~ce X with the
product. T remains unchanged.
"CLEAR"
"=+"
CHAIN
MULTIPLY
CONSTANT
DIVIDE
Depression of aD "=," "= +" or "%" key will multiply
the X·register by the Y·register and place the product in
X. T remains unchanged.
"x,"
following a terminator, or
or "x" operation
1
": +"
"%"
"+"
Depression of an "=," "= +" or "%" key will divide the
X·register by the T·register and replace X with the
quotient. T is unchanged.
With calculator
previously in chain
divide mode.
II..:..."
CHAIN
DIVIDE
"
following a terminator or
or "x" operation
Depression of an "=," "= +" or "%" key will divide the
T·register by the X·register, transfer X to T, and place
the quotient in X.
"+,,
:.:~,~ J:{ ;~
•
~.
VOL
______________
~T~H
FIGURE 4. Ready Timing.
NEW
~~
1_
~
~~
-------1
~
DEPRESSED
9WORDS
-
RElEASED
1
~
SWITCH
ANY-WUULJU
INPUT
"
l
/ L
J
-~~~--------o------
-NOISE"
16WOROSAFTER
AF~~~ ~~~~~~~~I~N
"NOISE"
ISCOMP~LETE.,
WHICHEVER IS
I
l t~------------
READY
LONGER.
NEW KEY HAS _
BEEN ACCEPTEO
BY CALCULATOR.
THE KEY MAY
BE RELEASEO.
I
t
NEXT KEY
CAN BE
ENTERED.
FIGURE 5. Functional Description of Ready Signal and Key Entry.
KEY OPERATIONS
Decimal Point, "."
(Note: Register X is always displayed.)
Clear All Key, "CA"
As the first depression of a number entry, it clears the
X-register and places a point in the left most digit. Ifthe
previous key was a number, it enters a decimal point
to the right of the last number entered. Following a
"+," "-," or "M+" following a "+" or "-," the
X-register is transferred to A, cleared and a decimal
point entered in the leftmost digit. The last decimal
point depression of a number entry is accepted as the
valid point.
Clears all registers and sets the calculator to the constant
multiply mode.
Change Sign Key, "CS"
Number Entries
Changes sign of register X.
The first entry clears the X.register and enters the
number into the LSD of X. Second through eighth
entries (excluding a decimal point) are entered one
digit to the right of the last number. The ninth, and
subsequent entries are ignored. First entry after a "+ ,"
"-," or "M+" following a "+" or "-" key causes the
number in the X-register to be transferred to ,the Aregister before clearing and placing the new entry in X.
Addition Key, "+"
Clear Key, "C"
Following a number entry key, it clears the X·register
only (clear entry). Following any other key it clears
registers X, K, C, 5, Nand T.
If the previous key was not a "+" or "-" key, the number
in the A-register is added to the X-register, X is transferred
to A, and the sum is stored in X. When the last key was
a "+" or "-" key, the number in A is added to the
number in X without destroying the value of A. The
sum is stored in X.
8-50
Subtraction Key, "-"
Memory Recall/Memory Clear Key, "MR"
If the previous key was not a "+" or "-" key, the number
in the X-register is subtracted from the number in the
A-register, X is transferred to A, and the difference is
stored in X. When the last key was a "+" or "-" key,
the number in A is subtracted from X without destroying
the value of A. The result is stored in X.
Following any key except "M R," the value of the
M-register is copied in to the X-register~ If the preceding
key was "+," "-:-" or "M+" following "+" or "-," the
number in the X-register is transferred to' the A-register
before M is recalled. Following another "MR" key, the
M-register is transferred to X, then cleared.
Memory Plus Key, "M+"
Multiplication Key, "x"
The number in the X-register is accumulated in the
M-register. Registers X and A are not changed, so the
repeat addition or subtraction conditions that existed
before accumulation to memory are still valid.
If there has not been a "x" or "7" key since the last
terminator key ("=," "= +" or "%"l. the value of the
X-register is copied into the T-register and the calculator
is set to the chain multiply mode. In a chain calculation
in which there has been a "x" key since the last terminator
or "7" key, X is multiplied by T and the resulting
product is stored in' both X and T; if a "7" key has
occured since the last terminator or "x" key, depression
of "x" will divide the T-register by the X·register, with
the quotient stored in both X and T.
Square Root Key,
"Vx"
The absolute value of the number in the X-register is
replaced with its square root.
Sum of X Key, "Lx"
Division Key, "7"
Adds X to the C-register, adds the square of X to the
T-register, saves the valye of X (to four decimal places)
in the V-register and increments N by one. The operation
is completed by copying N into X. The maximum valuE
of N is 99. The register returns to zero on the 1 OO~h entry_
If there has not been a "x" or "7" key since the last
terminator key ("=," "= +" or "%"l.' the value of the
X-register is copied into the T-register and the calculator
is set to the chain divide mode. In a chain calculation if a
"x" key has occured since the last terminator or "7"
key, X is multiplied by T and the product is stored in
both X and T; if a "7" key has occured since the last
terl!1inator or "x" key, depression of "7" will divide
the T-register by the X-register, with the quotient stored
in both X and T.
Sum of Y Key, "LY"
Adds the value of X to the A-register, adds the square
of X to the M-register, adds the product of X and Y to
the S-register, and recalls N to X.
Remove X Key, "REM X"
Equal Key, "="
This is used to delete a data point previously entered by
"Lx" key. It subtracts X from C, subtracts the square of
In the chain multiply mode, the value in the X-register
is multiplied by the T-register with the product stored
in X. Register T remains unchanged. In the chain divide
mode, depression of "=" will divide Y by X, transfer X
to T, and place the quotient in X. If the calculator is in
constant multiply, "=" will multiply X by T, place the
product in X and retain T. 'For constant divide, the
X-register is divided by T, the quotient is stored in X;
T is unchanged.
X from T,saves X to four decimal places in Y, decrements
N by one and copies the new value of N in to X.
Remove Y Key, "REM Y"
This is used to delete an incorrect data point previously
entered by the "LY" key. It subtracts X from A,
subtracts the square of X from M, subtracts the p~oduct
of X and Y from S and copies N to X.
The "=" key always rounds the answer stored in X to
two places to the right of the decimal point, and clears
register A.
, Frequency of X Key, "FREO"
This is used to sum grouped (identical) data entries for
mean and standard deviation computations. If the sign
of X is positive, "FREO" performs the "Lx" operation
X - 1 times. When X is negative, "FREO" performs the
"REM X" function IXI- 1 times.
Per Cent Key, "%"
This key acts exactly like the "=" key except the value
of X is divided by 100 and copied in register A before
performing the required operation. Register Ais not
cleared. The result stored in the X-register is rounded to
two decimal positions.
Mean and Standard Deviation Key,
"x,
SO"
Computes both the arithmetic mean and the standard
deviation of data points (entered by the "Lx" and
"FREO" keys) with a single key depression. The mean
is stored in register X (and therefore is the initial result
displayed). Standard deviation is stored in registers A
and M and is displayed by using the ','M R" key. Registers
T, C and N are saved so that additional data points may
be entered or deleted, and new mean and standard
deviation values calculated.
Automatic Accumulation Key, "= +"
.It acts just like the "=" key in all modes. After the result
is stored in X, the value of X is added to the number in
the M-register. The result stored in X and accumulated
into M is rounded to two decimal places. Register A is
cleared.
8·51
Correlation Coefficient and Slope Key, "COR SLOPE"
Y·lntercept Key, "INT"
The c'orrelation coefficient and slope of a least squares
line fit of accumulated paired data values (that have
been entered with the "~x" and "~y" keys) are
computed with a single key stroke. The correlation
coefficient is stored in registers X and S (and therefore is
the initial result displayed). Slope is in M and is obtained
by using the "M R" key. Registers T and C are lost.
After the, "COR SLOPE" key has been used to compute
a least squares line fit on a set of paired data values,
any y-coordinate corresponding to a given x·coordinate
lying on that line can be computed by entering the
x·coordinate in X, and depressing "INT."
TABLE II. Summary of Statistical Functions
KEY
STATISTICAL EOUATION
REGISTERS
X .. y
x + c -+
C. where c - original value of C
X2 + t -+ T, where t = original value of T
n
+ 1 -+ N.
Increments n
where n = original value of N
x + a -+ A, where a· original value of A
X2
+m
-+ M, where m .. original value of M
(X • y) +
"REM x"
c-x
-+
t-X 2
- "REM y"
S""
";y2
S, where s '" original value of S
I;x • y
Delate Xn
C
Delete xn 2
T
-+
n-1
-+
N
Decrementn
a-X
-+
A
Delete Yo
Delete Vn 2
m- X2 ... M
, - IX' YI .. S
Delete (x' Y)n
C
_
_"X
!:x
X =n
N
ff.
-~
I~xl'
2
rx - n
SO,
--"M
n-1
N-1
~X' I:y
!:x·y- - n -
"CDR-SLOPE"
A' - I~X_I') ('". .
\~X
~
y
-
I~YI')
~
~X' ~y
C'A
s--
I:x'Y- - n -
N
---"M
c'
T- N
rv -
---"A
m' ~x
b=--n
M'X+A"X
VINT ""
A-M' C
N
"INT"
mx + b
EXAMPLES
1. Addition or subtraction
KEYS
+
3
C
DISPLAY
2.0
3.2
-12.3
3. Chain multrplication or division
KEYS
COMMENTS
al
2
2,
3
3,
3.2
5,2
1
12
1 2.
1 2,3
-7,1
1.
2
2,
3
x
4
0,
2. Repeat add or subtract
KEYS
3
C
DISPLAY
DISPLAY
1
bl
COMMENTS
3
3,
3,1
3,1
6,2
9,3
6,2
,8·52
3,
3,1
6,2
4
4.
4,2
26,04
°2
1
10
10,
2
1
5,
1
1
°
0,
3
10
.5
2
,25
COMMENTS
EXAMPLES (Continued)
7. Perform add-on and discount
3. (Continued)
KEYS
c)
COMMENTS
DISPLAY
KEYS
2
0
x
4
8
x
4
2
20
2 O.
4
80.
8
10.
7
1.4285714
4
5.71
KEYS
1
%
Result rounded to two places
DISPLAY
3
3.
2
6.
4
12.
5
5.
5.2
1 5.6
46.B
3
b)
5
5.
2
2.5
4
2.
5
5.
5.2
2.6
1.3
+ 4)
x (3
KEYS
6
5
3
2
COMMENTS
%
First factor in constant multiply
3
0
0
%
5% of 125 is displayed
125 + 5% is displayed
5
53
532
532.
532.1
532.1
6
31.93
500.1 7
6% of 532.1 is displayed
532.1 - 6% is displayed
8. Perform change sign
KEYS
1
2
CS
3
Second factor in constant divide
CS
5
CS
6
C
DISPLAY·
1
12
-12
-123
-123.
1 23.
1 23.5
-123.5
-1 23.56
COMMENTS
Change sign does not
terminate entry.
o.
+ 2)/(6 + 7) =
DISPLAY
5
5.
4
9.
9.
3
3.
2
5.
45.
6
6.
7
13.
3.46
9. Accumulate in memory. recall and clear memory
COMMENTS
KEYS
a)
M+
4
M+
5
MR
MR
MR
(5 + 4) x (3 + 2) is executed
b)
45';' (6 + 7) is executed and
rounded to two places
M+
7
+
M+
6. Calculate percentage
5% of 300.25
KEYS
1 25.
125.
5
6.25.
1 31.25
b) Discount, 532.1 - 6%
5. To perform products of sum; e.g .•
(5
COMMENTS
12
4. Constant multiplication or division
a)
DISPLAY
a) Add-On, 125 + 5%
DISPLAY
3
30
300
300.
300.2
300.25
300.25
5
15.01
3
2
'COMMENTS
2
CS
M+
9
+
MR
+
MR
MR
MR
"Live %" key executes
operation and rounds two
places
8-53
DISPLAY
3
3.
4
4.
5
7.
7.
O.
5
5.
6
11.
11.
7
1 B.
1 B.
25.
3
32
32.
32.2
-32.2
-32.2
9
34.
-3.2
30.8
-3.2
-3.2
O.
COMMENTS
Accumulate in memory
Accumulate in memory
Recall memory
Recall and clear memory
Recall and clear memory
Accumulate in memory
Accumulate in memory
Repeat add
Accumulated value of M is recalled
Accumulated value of M is recalled
M is cleared
GIl
EXAMPLES (Continued)
10. Accumulate in memory with the "= +" key
KEYS
DISPLAY
5
5.
3
15.
4
4.
4.2
4.2
3
12.6
6
6.
7
.86
9
x
3
=+
4
3
=+
=+
9
CS
x
4
=+
MR
-9
-9.
4
-36.
-7.5'4
COMMENTS
CS
FREO x
LX
5 x 3 = 15 is added to M
4
FREO x
X,SO
MR
CA
7
LX
Note method of multiplying
negative number
8
LX
X, SO
-9 x 4 = -36 is added to M
6
LX
X. SO
MR
1. Perform mean and standard deviation
O.
4
1.
5.1
2.
4.5
3.
4.5333333
~x
5.1
LX
4.5
~x
X,
SO
MR
.55075765
, LX
X. SO
MR
Display indicates first data
{ point has been entered
LX
X, SO
2nd data point entered
MR
3rd data poi nt entered
Mean and standard
deviation are com·
puted;, mean is
displayed
Standard deviation is
recalled from M
LX
4
FREO
4.1
X
LX
3.9
LX
3.9
REM X
3.6
LX
X,SO
MR
O.
3
1.
4
4.
4.1
5.
3.9
6.
3.9
5.
3.6
6.
3.2833333
.46654774
LX
1.
3
3.
5
4.
7
3
FREO
X
5
~x
7
FREO
X
5
REM
7
Always use "CA" after mean
and SO calculation
Grouped data points may
be entered conven iently
using the "FREO" key
10.
5
5.
6.6
1.1401754
0,
1
LX
1.
1
1
LY
1.
3
2.
2
2.
LX
2
LY
4
LX
Mean and standard
deviation are computed:
X is displayed
Standard deviation is
recalled from M
n=3
Mean of first three entries
Standard deviation of
first three entires
n=4
Mean of first four entries
Standard deviation of
first four entries
Mean of all five entires
Standard deviation of all
five entires
COR·SLOPE
MR
.61538461
LY
6
LX
~y
o
INT
7 is incorrectly entered
8
INT
8-54
COMMENTS
n
=1
n=2
4
3.
3
3.
6
4.
4
4.
.99227788
3
9.
7
DISPLAY
CA
1
3
Wrong data entry
Wrong data is removed. Five
data points are en;ered.
5
X
7
4.
7.
.81649657
KEYS
c) Correction of group data entered with, "FREO"
Data: 4,4,4,5,5, 5, 5
O.
4
6
3.
7.
1.
a) Data: 1. 1
3,2
4,3
6.4
4
CA
4
.70710678
n=2
Mean of first two data
entries
Standard deviation of
first two data entries
2. To perform least squares line fit on given data
(See plotted data' on page 10)
,
b) Data: 3, 3. 3, 3, 4.1, 3.6
CA
3
O.
7
1.
8
2.
7.5
COMMENTS
a) Data: 4.0,5.1; 4.5
CA
4
Corrected data has been
entered
4.5714285
.53452315
d) Compute running mean and standard deviations
Data: 7,8,6,7,5
Rounded to 2 decimal places
{ and added to M
STATISTICAL FUNCTIONAL EXAMPLES
DISPLAY
Negative x sets
"REMOVE x" function
5
4.
4
7.
4.2 x 3 = 12.6 is added to M
MR
KEYS
-7
3.
n=3
Correlation coefficient
is displayed (perfect
correlation = 1.0)
Slope of least squares
line fit is recalled from
M
o
x'= 0
.346154
y-intercept of least
squares Iine at X = 0
is computed
8
X =
5.2692308
y-intercept of least
squares Iine at X = 0
is computed
8
STATISTICAL FUNCTION EXAMPLES (Continued)
2. (Continued l
8
1
6
5
(y)
4
3
2
1
0
I
~x
./
LEAST SQUARE~\
LliE F~T-"
-I
I
;t'
1
2
¥
T'I
3
1.
5
1.
8
B
~OMJUTEID
_I
DISPLAY
~x
5
LY
I
I
I
KEYS
9
~y
ff~
SLOPE
8
"
REM x
9
REM y
1
GIVEN DATA
POINTS
11
4
5
6
1
~x
8
4
~y
(x)
0
~x
\
b) Data: 2, 5
1,4
0,3
3
~y
COR·SLOPE
KEYS
DISPLAY
CA
2
O.
2
COMMENTS
MR
3
INT
8·55
2.
9
2.
8.
1.
9
1.
1
2.
4
2.
0
3.
3
3.
·1.
1.
3
6.
COMMENTS
n. = 1
ny = 1
Wrong data point is
entered
n. = 2
ny = 2
Wrong data point is
removed
n. : 1
ny = 1
n. = 2
ny = 2
n. = 3
ny = 3
Correlation coefficient
is displayed
Slope is displayed
For x = 3,
the y·intercept is 6
Calculators
~..
MM5764 conversion calculator
general description
The single-chip MM5764 Conversion Calculator was
developed using a metal-gate, P-channel enhancement
and depletion mode MOS/LSI technology with low
end-product cost as a primary objective. A complete
calculator as shown in Figure 1 requires only the
MM5764, a keyboard, DS8864 digit driver, NSA 1298
LED display, 9V battery and appropriate hardware.
Data is entered into the: calculator in floating point
business notation. All entries and results are'displayed
left justified with insignificant zeros to the right of the
decimal point suppressed. All intermediate results of a
chain calculation are floating point. Terminating 'keys
"=," "%," and "= +" round the displayed result to two
decimal places.
Keyboard decoding and key debounce circuitry, all
clock and timing generation and 7-segment output
display encoding are included on-chip and require no
external components. Segments can usually be driven
. directly from the MM5764, as it typically sources about
8.5 mA of peak current. [Note: The typical duty cycle
of each digit is 0.104; average LED segment current is
therefore approximately 0.104 (8.5 mA), or 0.9 mA
average. Correspondingly the worse-case average segment
current is 0.104 (5.0 mA), or 0.52 mA.] The ninth digit
(left-most) is used for the negative sign, or the decimal
point of a number less than unity.
features
•
•
•
•
•
•
•
•
•
•
Full 8-digit entry and display calculator
Arithmetic functions: +, -, x, +, =, %, l/x
Percent mark-up and discount
Twenty automatic conversions
A user definable conversion key
Change sign and "rr" keys
Accumulating memory: MR, IV!+, =+, MC
Square root
Auto constant
Business notation
• +, - "adding machine" notation
• x, +, = algebraic notation
• Automatic power-on clear
'. Automatic display cutoff
• Direct 9V ba:tery compatibility; low power
An internal power-on clear circuit is included that clears
all registers, including the memory, when VDD and Vss
are initially applied to the chip.
Trailing zero suppresion allows convenient reading of the
left justified display, and conserves power. The DS8864
digit driver is capable of sensing a low battery voltage
and providing a signal during Digit 9 time that can be
used to turn on one of the segments as an' indicator.
Typical current drain of a complete calculator displaying
five "5's" is 30 mAo Automatic display cutoff is included.
If no key closure occurs for approximately 25 seconds,
all numbers are blanked and all decimal points displayed.
connection diagram
Dual-In-Line Package
DIGIT 3
DIGIT2
DIGITI
The Ready output signal is used to indicate calculator
status. It is useful in providing synchronization information for testing or applications where the MM5764 is
, used with other logic or integrated circuits; e.g., with the
MM5765 Programmer (Figure 3).
K4
K3
SWITCH
INPUTS
[
5
K2
KI
Thirty-two keys are arranged in a four-by-nine matrix
as shown in Table I. There is an automatic constant
feature ..
17 SEGMENT D
Voo
SEGMENT G
The user has access to five registers designated X, T,
A, K and M. The X-register is used for keyboard entry
and display. The T and A-registers are used in multiply/
divide and add/subtract calculations, respectively. M is
an accumulating storage memory. The K-register is used
to store a user defined conversion constant.
SEGMENTF 11
14 DECIMAL POINT
13 SEGMENT C
TOP VIEW
Order Number MM5764N
See Package 22
8-56
absolute maximum ratings
Voltage at Any Pin Relative to Vss. (All other
pins connected to Vss)
.
Ambient Operating Temperature
Ambient Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Vss + 0.3V to Vss - 12.0
O°C to +70°C
-55°C to +150°C
300°C
operating vottage range
6.5V:::; Vss - Voo :::; 9.5V
Vss always defined as most positive supply voltage.
dc electrical characteristics
. CONDITIONS
PARAMETER
Operating Supply Current (I DO)
Keyboard Scan I nput Levels
(Kl, K2, K3 and K4)
Logical High Level
Logical Low Level
Vss -6.5V:S: Voo:S: V ss -9.5V
Voo :: V ss -6.5V
Voo = V ss -9.5V
Digit Output Levels
Logical High Level (V OH )
RLoAo = 3.2 kn to V DO
V ss -6.5V:S: Voo
V ss -9.5V
Voo = V ss -6.5V
Voo = V ss -9.5V
:s:
Logical Low Level (VOL)
Segment Output Current
(Sa through 5g and Decimal Point)
Reildy Output Levels
Logical High Level (V OH )
Logical Low Level (VOL)
MIN
TYP
TA = 25°C
V OUT = V ss -3.6V, Voo = V ss -6.5V
V OUT = V ss -5V, Voo = V ss -8V
V OUT = V ss -6.5V, Voo = V ss -9.5V
MAX
16.0
Voo = V ss -9.5V, T A.= 25°C
V
V
V
V ss -6.0
V ss -7.0
V
V
V
Vss -1.5
-8.5
-10.0
-15.0
V ss -1.0
IOUT'= -0.4 mA
lOUT = 10pA
mA
V ss -5.0 .
V ss -6.0
V ss -2.5
-5.0
UNITS
Voo+1.0
mA
mA
mA
V
V
ac electrical characteristics
PARAMETER
CONDITIONS
MIN
0.32
Word Time (Figure 2)
.. 36
Digit Time (I:igure 2)
Segment Blanking Time (Figure 2)
2
UNITS
TYP
MAX
O.S
2.0
ms
222
ps
14
ps
. S9
5.5
Digit Output Transition Times
(t R1SE and tFALLl
CLOAO = 100 pF, RLOAo = 9.6 kn
2
ps
Keyboard Inputs High to Low
Transition Time After
Key Release
CLOAO = 100 pF
4
ps
Ready Output Propagation Time
(Figure 3)
Low to High Level (t POH )
High to Low Level (t POL )
Key Input Time·out
Ke,y Entry
Key Release
10
C LOAO = 100 pF
C LOAO = 100 pF
I
Display Cutoff Time
(The time after the last valid key
closure that all numbers will be
blanked and all decimal points
displayed.)
8·57
50
1
ps
ms
1~
2.S
5.1
7.2
12.8
32
ms
ms
10
25
63
sec
REAr
I
KI
K2
K3
MM5764
--{K4 01 02 03 04 05 06 07 08 09
~
I
:1
S. Sb Sc Sd S. SI Sg dp
~
dp
I
Sy
SI
Se
Sd. Sc
Sb
Sa
NSAI298
lllllllllllll~llll
C/. C/. C/. C/. C/. c/. C/. C/. C/.
09
08
07
06
05
04
OJ
02
01
T
LV GNO Vee
INO
~ ~ ~ ~
r~
~ ~ ~ "0-......
~
~
~
~
......
----
+
~ ~ ~
~ ~ ~
~...... i'o-....... .~
~ i'o--,- ~
......
--
~'-
POWER
~
......
.......
FIGURE 1. Complete Calculator Schematic
DIGIT r - - - - - - - - - - - - - - W O R O T l M E - - - - - - - - - - - - l 1
OUT;,UTS
-J, - - - - - ,I________________________________~r---l~---
-l
03
I
I-OIGITTIME
-+---!
-+---+--~
09
DECIMAL
POINT--Ir-_--1~-__+~
Sb
Sc
Sd
--+--..,...
Se
-+--..,...
SI
~-----+----~----~
Sl_·...;.._ _~
875 S Lf if? I
ACTUAL DISPLAY:
09
•
SEGMENT
DESIGNATION
.. 0'
FIGURE 2. Display Timing Diagram
8·58
\
::J
OM8864
KEY80ARO
Note: See Tebl.1I for KIY Matrix Designation••
02
I
9V
MAllORY
MN1604
OR
EOUIV.
/!
CALCULATOR
Vss
~
.....
r';"--"'1
I
i
MM5164
DIGIT
OUTPUTS
DECIMAL
POINT
Voo -
DECIMAL POINT
PROGRAM
MODE
SWITCH
READY
RUN
SEGMENTS
DIGITS
LOAD
(9)
OUTPUT
(9)
INPUT
CONTROL
+
9V
DM8864
(8)
GND
READY
RUNILOAO
Vss
KilO',
MM5165
K5
Voo
"~
""'"
ALARM
LED
ALARM
INDICATOR
LEARN MODE
PROGRAMMER
-_....
--=-
I
Vee
(9)
DATA
~
NSA1298
,-, CI CI CI CI CI I-I' CI CI
CI.CI. CI. CI. CI. CI. CI. CI. CI.
(9)
:
I---~
4X 9
OAT A
KEYBO ARD
AN 0
1X4
PROGRA MMER
CONT ROL
KEYBO ARD.
K
INPUTS
SEGMENT
OUTPUTS
LED
DISPLAY
m
.
.
POWER
SWITCH
ON
FIGURE 3, Low Cost Handheld Programmable Calculator Using the MM5764 Calculator and MM5765 Programmer.
KEYBOARD BOUNCE AND NOISE REJECTION
valid, then goes low as indicated in Figures 4 and 5. It
remains at a Logical Low Level until the function initiated
by the key is completed and the key is released. The low
to high transition indicates the calculator has returned to
an idle state and a new key can be entered.
The MM5764 is designed to interface with most low
cost keyboards, wh ich are often the least desirable
from a false or multiple entry standpoint.
A key closure is sensed by the calculator chip when
one of the key inputs, K1, K2, K3 or K4 are forced
more positive than the Logical High Level specified in
the electrical specifications. An internal counter
started as a result of the closure. The key operation
begins after nine word times if the key input is still
at a Logical High Level. As long as the key is held
down (and the key input remains high) no further
entry is allowed. When the key input changes to a
Logical Low Level, the internal counter starts a sixteen
word time·out for key release. During both entry and
release time·outs the key inputs are sampled approximately every other word time for valid I~vels. If they
are found inval id, the counter is reset and the calculator
assumes the last valid key input state.
ERROR INDICATION
In the event of an operating error, the MM5764 will
display all zeros and all decimal points. The error
indication occurs if division by zero is attempted or
either a result or intermediate value exceeds 99999999.
is
The indication is cleared by depressing any key.
If an error results from a "+" or "-" key, the X-register
is cleared and the last entry is saved in the A-register; no
other registers are affected. An error condition during
"x" or "-;-" operations clears X without changing any of
the other registers.
Overflow as a result of "M+" saves the value stored in M,
clears X and displays the error indication. Calculations
are immediately stopped and other registers are not
cleared.
One of the popular types of low-cost keyboards available,
the elastomeric conductor type, has a key pressure
versus contact resistance characteristic that can generate
continuous noise during "teasing" or low pressure key
depressions. The MM5764 defines a series contact
resistance up to 50 kr2 as a valid key closure, assuring a
reliable interface for that type of keyboard.
Overflow as a result of a conversion clears X and saves
all other registers.
AUTOMATIC CONSTANT
AUTOMATIC DISPLAY.CUTOFF
The MM5764 retains as a constant the first factor of a
multiplication calculation or the second factor of a
division calculation, when that calculation is terminated
by "=" key, "%" key or "= +" key. Subsequent
calculations using the stored constant are made by
entering a number and operating upon it with the
appropriate terminator ("=," "%" or "= +" key). The
T-register is used to store the constant in the constant
mode of operation.
If no key. is depressed for approximately twenty-five
seconds, an internal automatic display cutoff circuit
will blank all segments and display nine decimal points.
Any key depression will restore the display; to restore
the display without modifying the status of the calculator,
use two Change Sign key depressions.
READY SIGNAL OPERATION
The Ready signal indicates calculator status. When the
calculator is in an "idle" ~tate the output is at a Logical
High Level (near Vss ). When a key is closed, the internal
key entry timer is started. Ready remains high until the
time-out is completed and the key entry is accepted as
The calculator automatically changes to the chain mode
. when a "x" or "-;-" key occurs in the calculation. In
the chain mode, the result of each "x" or "-;-" key is
stored in both X and T-registers. A new entry replaces
X without altering T. At the completion of a chain
?-,59,
TABLE I. Mode Summary
KEYS THAT
SET MODE
MODE
DESCRIPTION
(See Calculation Examples)
Depression of an "=," "=: +" or "%" key will multiply
the X·register by the T·register and replace X with the
product. T remains unchanged.
"CLEAR"
CONSTANT
MULTIPLY
"=+"
"%"
CHAIN
MULTIPLY
Depression of an "=," "= +" or "%" key will multiply
the X·register by the T·register and place the product in
X. T remains unchanged.
"X,"
following a terminator, or
or "x" operation
CONSTANT
DIVIDE
"-- +"
"%"
CHAIN
DIVIDE
)
"+"
Depression of an "=," "= +" or "%" key will divide the
X·register by the T·register and replace X with the
quotient. T is unchanged.
With calculator
previously in chain
divide mode.
Depression of an "=." "= +" or "%" key will divide the
T·register by the X·register, transfer X to T, and. place
the quotient in X.
following a terminator or "+"
or "x" operation
FIGURE 4. Ready Timing
NEW
KEY IS
DEPRESSED
~
SWI~~~
INPUT
.
JII
L1-
9 WORDS
-I
1
-
KEY IS
RELEASED
t
n n nJLJU -------U------
---t---J L-J L-J L,.
11'-1
"'NDISE"
"NOISE':"
l
READY
~ ~6E~~~~~:::~~
AFTEI:
~~~~~i~:.IDN
WHICHEVER IS .
LONGER.
t!--------~
NEW KEY HAS
BEEN ACCEPTED
BY CALCULATOR.
THE KEY MAY
BE RelEASED.
J
!n
t.
.
NEXT KEY
CAN BE
ENTERED.
FIGURE 5. Functional Description of Ready Signal and Key Entry.
calculation, the T-register will contain the value used as
first factor of the last multiply, or the latest entry if. the
last operation was a divide.
"-," or "M+" following a "+" or "-" key transfers the
existing number in the X-register to the A-register before
clearing and placing the new entry in X.
Table I summarizes the four modes.
Conversion Functions
With the exception of the six single function conversion
keys, all conversions are preceded by either the shift key,
"-'>-," or the reverse conversion key, "+-." Depression 'of
the appropriate conversion key replaces the value in the
X-register with a converted result, as summarized in
Table II. The six single function keys (inches -'>- mm,"
"inches -'>- cm," "'ft -'>- inches," "ft -'>- m," "yds -'>- m"
and "miles -+ km") do not need to be preceded by the
shift key, "-'>-," for forward conversions. Only the Xregister is affected by a conversion operation.
KEY OPERATIONS
(Note: X-register is always displayed.)
Clear Key,
"c"
Following a number key, it clears only the X-register
(clear' entry); after any other key, it clears registers X,
A and T.
Number Entries
Constant Store Key, "KS"
The first entry clears the X-register and enters the
number as the LSD of X. Second through eighth
entries (excluding a decimal point) are entered one
digit to the right of the previous number. The ninth, and
subsequent entries, are ignored. First entry after a "+,"
The value of X is copied into the K-register. Following
a forward conversion key, "-'>-," X is multiplied by K and
the product stored in X; following a "+-" -key, X is
divided by K, and the quotient is stored in X.
8·60
Decimal Point, .....
in X. Register T remains unchanged. In the chain divide
mode, depression of "=" will divide T by X, transfer X
to T, and place the quotient in X. If the calculator is in
constant multiply, "=" will multiply X by T, place the
product in X and retain T. For constant divide, the
X-register is divided by T, the quotient is stored in X;
T is unchanged.
As the first depression of a number entry, it clears the
X·register and places a point in the leftmost digit. If the
previous key was a number, it enters a decimal point
to the right of the last number entered. Following a
"+," "-:' or those keys preceding a "M+" key, the
X-register is transferred to A, cleared and a decimal
point entered in the leftmost digit. The last decimal
point depression in a single number entry is accepted as
the val id point.
The "=" key always rounds the answer stored in X to
two places to the right of the decimal point, and clears
register A.
Change Sign Key, "CS"
Per Cent Key, "%"
Changes sign of register X.
This key acts exactly like the "=" key except the value
of X is divided by 100 and copied in register A before
performing the required operation. The result stored in
X is rounded to two decimal positions.
Addition Key, "+"
If the previous key was not a "+" or "-" key, the number
in the A-register is added to the X-register, X is transferred
to A, and the sum is stored' in X. When the last key was
a "+" or "..;.." key, the number in A is added to the
number in X without destroying the value of A. The
sum is stored in X.
. Memory Plus Key, "M+"
The ~umber in the X-register is accumulated in the
M-register. Registers X and A are not changed, so the
repeat addition or subtraction conditions that existed
before accumulation to memory remain valid.
Subtraction Key, "-"
Memory Recall Key, "MR"
If the previous key was not a "+" or "-" key, the number
in the X-register is subtracted from the number in the
A-register, X is transferred to A, and the difference is
stored in X. When the last key was a "+" or "-" key,
the number in A is subtracted from X without destroying
the value of A. The result is stored in X.
The value of register M is copied into the 'X-register. If
the preceding key was a "+," "-" or "M+" followed by
"+" or "-," the value of X is transferred to the A-register
before M is copied into it.
Memory Clear Key, "MC"
Multiplication Key, "x"
The M-register is cleared, without affecting any other
registers.
If there has not been an "x" or ".;." key since the last
terminator key ("=," "= +" or "%"1. the value of the
X-register is copied into the T-register and the calculator
is set to the chain multiply mode. In a chain calculation
in which there has been a "x" key since the last terminator
or ".;." key, X is multiplied by T and the resulting
product is stored in both X and T; if a ".;." key has
occured since the last terminator or "x" key, depression
of "x" will divide the T-register by the X-register, with
the quotient stored in both X and T.
Reciprocal Function, "'/x"
If the number entry key. "1" is preceded by either the
forward or reverse conversion shift keys, .. ~" or "+-,"
a non-zero value of X is replaced by its reciprocal.
Registers A, T, K and M are not altered.
Square Root Function,
Division Key, ".;."
'\/x"
If the number entry key "2" is preceded by either the
forward or reverse conversion shift keys, ..~" or "+-," the
absolute value of X is replaced by its square root.
Registers A, T, K and M are unaltered.
If there has not been an "x" or ".;." key since the last
terminator key ("=," "= +" or "%"1. the value of the
, X-register is copied into the T-register and the calculator
is set to the chain divide mode. In a chain calculation if a
,"X,',' ,key has occured since the last terminator or ".;."
key, X is multiplied by T and the product is stored in
both X and T; if a ".;." key has occured since the last
terminator or "x" key, depression of ".;." will divide
the T-register by the X-register, with the quotient stored
in both X and T.
Pi-function, "11"
If the decimal point entry key is preceded by either the
forward or reverse conversion shift keys, "~ .. or "+-,"
the value of X is replaced by the constant 3.1415927.
Equal Plus Key "=+"
Equal Key, "="
This key acts exactly like the "=" key followed by a
"M+" key. The multiply or divide is executed the result
is rounded to two places then the rounded result is
added to the Memory.
In the chain multiply mode, the value in the X-register
is multiplied by the T-register with the product stored
8·61
~
<0
"~
TABLE II. Summary of Key Functions
It)
~
KEY MATRIX
DESIGNATION
PRIMARY KEY
FUNCTION
K1-D1
N/C
K1-D2
Minus, "-"
IP PRECEDED
BY "'-+"' SHIFT KEY
IF PRECEDED
BY"'+-"' SHIFT KEY
K1-D3
Plus, "'+"'
K1-D4
Divide, "'7"'
K1-D5
Multiply, "'x"'
"x"
"x"
K1-D6
Constant Store, "'KS"'
Constant Conversion
Xo' K -+ X
Xo 7 K -+ X
K1-D7
Ft -+ in
Xo' (12)-+X
Xo7(12)-+X
K1-D8
In -+ mm
Xo • (25.4) --> X
Xo 7 (25.4)
-+
X
K1-D9
In -+ cm
Xo • (2.54) --> X
Xo 7 (2.54)
-+
X
K2-D1
Mile
Xo • (1.609344) --> X
Xo 7 (1.609344) --> X
K2-D2
Ft -+ m
K2-D3
Forward Sh ift,
-+
"'+"'
"'+"'
"..:...."
km
"-+"
Xo • (0.3048) -, X
Xo 7 (0.3048) -> X
"-+"
"-+"
K2-D4
Memory Clear, "MC"·
"MC"
"MC"
K2-D5
Yard
Xo • (0.9144) -> X
Xo 7 (0.9144)
K2-D6
Memory Plus, "M+"
MPH -> knots
Xo • (0.86836) -> X
Xo 7 (0.86836) -> X
K2-D7
Memory Recall, "MR"
Imp. Gal. -> U.S. Gal.
Xo • (1.20094) -> X
Xo 7 (1.20094) -> X
"C"
"C"
-+
K2-D8
Clear,
K2-D9
N/C
m
"e"
-+
X
K3-D1
N/C
K3-D2
Equal, Acres --> Hectares
Xo • (0.404687) -> X
Xo 7 (0.404687) -> X
K3-D3
Equal Plus, "=+"
Cubic Ft -> gal
Xo • (7.4805)
X
Xo 7 (7.4805)
-+
X
K3-D4
Change Sign, "CS"
Atmospheres -> PSI
Xo • (14.696) -> X
Xo 7 (14.696)
-+
X
K3-D5
Decimal Point, "."
-+
3.1415927 -> X
3.1415927 -> X
K3-D6
"9"
Oz -> cc
Xo • (29.5737) -> X
Xo 7 (29.5737) -> X
K3-D7
"8" .
Quarts -> liters
Xo • (0.946333) -> X
Xo 7 (0.946333) --> X
K3-D8
"'7"
Gal -> liters
Xo • (3.785332) -> X
Xo 7 (3.785332) -> X
K3-D9
"6"
Lb--> oz
Xo' (16) -> X
X O '7 (16) -> X
K4-D1
"'5"
Oz --> grams
Xo • (28.3495) -> X
Xo 7 (28.3495) -> X
K4-D2
"4"'
Lb -> kilogram
Xo • (0.453592) -> X
Xo 7 (0.453592) -> X
K4-D3
"3"
Stone -> Ib
Xo • (14) -> X
Xo 7 (14) -> X
K4-D4
"2"
Square Root,
A->X
rxo.-> X
K4-D5
"'1"
Reciprocal, "1/X"'
1/Xo->X
l/Xo --> X
K4-D6
"0"
OF -+
Xo • (9/5) + 32 -> X
(X o - 32) • 5/9 .... X
IT
"VX"'
°c
K4-D7
Reverse Shift, "<--"'
"-+-"
"-+-"
K4-D8
Percent, "%"
Acre .... Sq. ft
Xo • (43560) .... X
Xo 7 (43560) .... X
u8·62
4. Constant multiplication or division
EXAMPLES
3:
3:
U1
KEYS
1. Addition and subtraction of a column of numbers:
a)
2.0
3.2
-12.3
KEYS
C
DISPLAY
2
2.
3
3.
3.2
5.2
1
12
12.
12.3
-7.1
O.
COMMENTS
2 is entered
2 + 3.2 is displayed
b)
12.3 is subtracted from
(2 + 3.2)
2. Repeat add or subtract
KEYS
C
COMMENTS
DISPLAY
3
3.
3.1
3.1
6.2
9.3
6.2
O.
3.1
3.1
3.1
9.3
KEYS
is entered
+ 3.1 computed
+ 3.1 + 3.1 computed
- 3.1 computed
KEYS
DISPLAY
COMMENTS
6
1
r.
2
2.
3.1
6.2
4.2
26.04
1 x 2 is computed
6.2 x 4.2 is computed
10
10.
2
5.
10
.5
2
.2 5
3
0
0
10.;. 2 is computed
5.;. 10 is computed,
%
0.5 .;. 2 is computed
x
4
5
5.
2
2.5
4
2.
5
5.
5.2
2.6
1.3
Second factor in constant divide
20
20.
4
80.
8
10.
7
1.4285714
COMMENTS
(5 + 4) x (3 + 2) is executed
45';' (6 + 7) is executed and
rounded to two places
COMMENTS
DISPLAY
3
30
300
300.
300.2
300.25
300.25
5
15.01
"Live %" key; rounded
two places
KEYS
DISPLAY
COMMENTS
a) Add-On
4
5.71
DISPLAY
5
5.
4
9.
9.
3
3.
2
5.
45.
6
6.
7
13.
3.46
7. Perform add·on and discount
c) Mixed multiplication and division
8
First factor in constant multiply
6. Calculate percentage
KEYS
20
x
4
~
3
3.
2
6.
4
12.
5
5.
5.2
1 5.6
46.8
2 x 3.1 is computed
b) Division
10
'"
en
(5 + 4) x (3 + 2)/(6 + 7)
a) Multiplication
10
COMMENTS
5. To perform products of sums
3. Chain multiplication or division
x
3.1
x
4.2
DISPLAY
Result rounded to two
places
%
,8-63
12
125.
125.
5
6.25
131.25
5% of 125 is displayed
• 125 + 5% is displayed
GIl
~
to
"
EXAMPLES (Continued)
10. (Continued)
Lt)
~
KEYS
7. (Continued)
KEYS
DISPLAY
6
COMMENTS'
b) Discount
=+
%
53
532
532.
532.1
532.1
6
31.93
500.17
6% of 532.1 is displayed
532.1 - 6% is displayed
1
2
CS
3
CS
5
CS
6
DISPLAY
1
12
-12
-123
-123.
123.
123.5
-123.5
-123.56
COMMENTS
KEYS
. M+
4
M+
5
MR
MC
MR
b)
5
+
M+
7
+
M+
3
2
2
CS
M+
9
MR
MR
MC
DISPLAY
.3
3.
4.
5
7.
7.
-9
=+
MR
-9.
4
-36.
-7.54
Change sign does not
termi nate entry.
70064
70064
70064.
2 (,./X)
264.69605
1 (l/X)
.00377791
DISPLAY
K.EYS
COMMENTS
MC
C
5
x
3
=+
4
2
x
3
=+
DISPLAY
Accumulate in memory
-9 x 4 = -36 is added to M
COMMENTS
Either shift key could be
used to set up.JX function
Square root is computed
Either shift key could be
used to set up 1IX function
Reciprocal is computed
COMMENTS
Either shift key.could be
used to set up 11
Accumulate in memory
• (11)
x
6.8
Recall memory
Clear memory
3.141 5927
6.2831 854
6.8
42.73
211 is computed
13. Use of conversion keys:
KEYS
Accumulate 'in memory
Accumulate 11 + 18 in memory
Repeat add
DISPLAY
in -> cm
2
5.08
in-> cm
12.9032
in-> cm
32.774 1 28
32.774 1 28
in -> cm
C
5
(11 + 18)'- 32.2 is accumulated
in memory
Accumulated value of M
is recalled
Accumulated value of M
is reclliled
COMMENTS
O.
O.
5
5.
3
1 5.
4
4.
4.2
4.2
3.
12.6
Note method of multiplying
negative number
2
2.
5 x 3 = 15 is added to M
8·64
Two inches is converted
to cm
Two square inches is con· .
verted to square cm
Two cubic inches is con·
verted to cubic cm
Reverse conversion mode
is set
12.9032
5
5.
7 (gal->Iiters)
18.92666
8 (qts ->Iiters)
12.5.
KS
2
20.
12.5
12.5
2
2.
Data entry is terminated
and forward conversion
mode is set
Five gal. is converted to
liters
Last shift key is valid
direction
Liters -> qts computed
Entry is stored in K
KS
25.
Forward shift sets up K
conversion
Multiply by K
. KS
C
77
2.
Divide by K
O..
o (oF->°C)
4.2 x 3 = 12.6 is added to M
COMMENTS
O.
10. Accumulate in memory with the "= +" key
KEYS
Rounded to 2 decimal places
12. Use of constant 7T: 27Tr = 2(7T) (6.8)
O.
5
5.
6
11.
11.
7
18.
18.
25.
3
32
32.
32.2
-32.2
-32.2
9
34.
':'3.2
30.8
-3.2
-3.2
DISPLAY
KEYS
9. Accumulate in memory, recall and clear memory
a,l
CS
COMMENTS
11. Square root and reciprocal calculations.
Find square root of 70064:
8. Perform change sign
KEYS
DISPLAY
6
6.
7
.86
9
77
77.
25.
77° F is entered
77°F is converteq to °c
keyboard outline
----6
oz~lb
1
3
11 x
Ib~stn
0
CE/C
F~ C
1T
8·65
Calculators
MM5765 calculator programmer
general description
The MM5765 provides a cO,nvenient and inexpensive
means of adding "learn mode" programmability to many
National Semiconductor calculator chips. It interfaces
directly by simply adding a single static switch, four
dynamic keys and a mean of displaying an alarm condition. The monolithic MOS integrated circuit combines
P-channel enhancement and depletion mode technologies
to obtain low voltage and low power characteristics
necessary for economical battery-powered products.
Up to four switch inputs (K1, K2, K3 and K4) and up
to twelve digit lines are connected in parallel with the
calculator switch and digit terminals that scan the keyboard. Keys stored in the MM5765 that are entered by
selecting K1 through K4 are encoded simply as matrix
positions, i.e., a particular switch input at a specific
digit time. Therefore it is the key matrix address that is,
stored and not the key function. (Con't on page 4)
features
The MM5765 is a dynamic key sequence programmer
that memorizes any combination of key entries while in
the Load Mode, then automatically plays back the pro• grammed sequence as often as desired in the Run Mode.
Up to 102 characters can be stored in multiprogram
sequence blocks. Each block, or program" can be executed individually or the operator can make the decision
to branch to specific programs, run each in series or
perform intermediate calculations from the keyboard.
When programming in the Load Mode, the Delete key
provides a convenient editing feature and the Halt key
programs variable data entry points where 'control is
temporarily returned to the operator in the Run Mode.
Start and Skip keys control operation in both modes.
•
Many NSC calculator chips can be provided with
programming capability with the addition of only
one static switch and four dynamic keys.
• Any key sequence, including constants and date entry
points, may be stored automatically in the Load Mode
and executed in the Run Mode.
• 102 step storage capacity of up to 47 different keys
arranged in a 12 x 4 matrix.
•
Multiprogram capability
•
Provision for editing in Load Mode using the Delete
key
• Convenient verification of programs using a Step
Mode feature
Synchronization with the calculator chip is accomplished
by monitoring its Digit Output and Ready signals. The
digit signals give timing information while the Ready
indicates status of the calculator and synchronizes the
key entry interface between it and the MM5765.
• Alarm for full storage condition-or if a deletion of
the first step in a program is attempted
•
Power-on clear
•
Direct 9V battery compatibility
block and connection diagrams
612-BIT STORAGE REGISTER
Dual-In-Line Package
MAIN
CONTROL
I
::;:~~
•
voo
K3
K4
K2
K5
KI
READY
05
RUN/LOAD
09
TEST
08
ALARM
08
INPUTS
DIGIT
"':-012
I/O
TIMING
AND
CONTROL
+-+KI
+-+K2
KEY
+-+K3
~/~ITCH
01
OIl
..--.K4
+- LOAD/RUN MODE
14
03
READY
13
02
ALARM
Vss
' - -_ _ _ _ _ _-1 12
TOP VIEW
Order Number MM5765N
See Package 21
FIGURE 1
8-66 "
04
DID
012
absolute maximum ratings
operating voltage range
Voltage at Any Pin Relative to Vss Vss + 0.3V to Vss -12V
(All other pins connected to Vss)
oOe to +70o e
Ambient Operating Temperature
o
-55°C
to +150 e
Ambient Storage Temperature
300°C
Lead Temperature (Soldering, 10 seconds)
Vss -6.5V ~ Voo ~ Vss --9·5V
(Vss is always the most positive supply)
dc electrical characteristics
CONDITIONS
PARAMETER
Operating Supply Current (I DO)
MIN
TYP
MAX
mA
8.0
Voo = V ss -9.5V
UNITS
T A =25°C
Keyboard Scan Input Levels
(K1, K2, K3, K4, K5)
Logical High Level (V 1H )
Logical Low Level (V 1L )
Digit Input Levels (D2 through D12)
Logical High Level (V 1fi )
Logical Low Level (V IL)
Other Inputs (Ready, Run and Test)
Logical High Level (V IH)
Logical Low Level (V 1L )
Switch Buffer Output Levels
(K1, K2, K3, K4)
Logical High Level (V OH )
Logical Low Level (Vo L)
Alarm Output Current
Source Current
V
V
V
Voo = V ss -6.5V
Voo = V ss -9.5V
V
V
Voo = V ss -6.5V
Voo '" V ss -9 5V
V
V
V
Voo = V ss -6.5V
Voo = V ss -9.5V
V
Vss
Vss-u·O
V ss -7.0
Voo = V ss -6.5V
Voo = V ss -9.5V
V OUT = V ss -4.5V, Voo
V OUT = V ss -5.2V, Voo
V OUT = V ss -7.8V, Voo
= V ss -6.5V
= V ss -7.25V
-5.0
V
V
-20.0
mA
mA
mA
MAX
UNITS
-8.0
= V ss -9.5V
V
ac electrical characteristics
PARAMETER
CONDITIONS
MIN
TYP
Digit Input Time (Figure 3)
70
ps
Word Time (Figure 3)
0.64
ms
Switch Input Time (Figure 3)
0.70
ps
Switch Output Time (Figure 4)
70
ps
Switch Propagation Delay Output
(Figur~ 4)
Switch Output Transition Time
15
CLOAO
=
100 pF
26
ps
ps
2
(Figure 4)
Switch Input K5 Key Bounce·out
Stability Time
(The time a keyboard input must be
continuously higher than the mini·
mum L09ical High Level to be ac·
cepted as a key closure, or lower than
the maximum Logical Low Level to
be ,accepted as a key release, i.e., 6
or 7 cycles of D2.)
17.0
4.5
Key Closure Rate
(Time between consecutive key
outputs in Run Mode.)
ms
40
Key Acceptance Rate
(Time between consecutive key
inputs in Load Mode.)
47
8·67,
ms
ms
(8)
Vss
SWITCH
~ INPUTS
1(8)
SEGMENTS
OUT
DIGIT
OUTPUTS
--
CJ CI CJ..• . 1=1 1=1
1_1.1_1. Ll. 1_1.1_1.
VDD I""""
CALCULATOR
(n)
DISPLAY
READY
f
1m)
-- -~
I KE~~
I
Xn)
OARO
MAT RIX
L~5--
DIGIT DRIVER
I
__ .-l
A
GNO
...
(m·1)
, Vss
SWITCH
I/O',
--+
(m)
Vee
(m)
DIGIT
INPUTS
READY
ALARM
MM5165
-r+--
LOAD
RUN/LOAD
K5
;~
VDD
RUN
0
--.;!;..
PROGRAMMER
MODE
SWITCH
I
~POWE R SWITCH
ALARM
INOICATOR
LEO
FIGURE 2. MM5765 Programmer Connected in Low-Cost Battery Operated Calculator System
------~--~
I_--------WORDTIME
DIGIT TIME
'----
DIGIT 2
INPUT
~----------~--~;-
V'H
DIGIT 3
INPUT
DIGIT 4
INPUT
Kl SWITCH I/O
WITH
KE~~~~E;;ED _ _ _ _ _ _J
FIGURE 3_ Input Timing
0lGIT3
INPUT
Kl SWITCH
I/O
OUTPUT
TIME
--
'::::: II Il'fill~)J:::i.1 I","," I I I I I I II
I
READY
INPUT ----I
Kl SWITCH
I\
I_
-,
I_
,
III I
I'_ _ _ __
/
OUTP~~ _--'--II....\..I:Il~1....I--'-~J""<_--------------
K2 SWITCH
OUTP~~
Kl - 03 KEY IS
Kl ·03 KEY RELEASE
ENTERED INTO
TIMED OUT
CALCULATOR
BY CALCULATOR
_ _ _ _ _ _ _ _ _ _ _ _....
1_,....
1 ....1--'-1....1--'-1....1_ _ _ __
K2 - 03 KEY IS ENTERED
INTO CALCULATOR
FIGURE 4. Programmer Output Timing
8-68
K2 - 03 KEY
RelEASE
9V
BATTERY
TABLE I. Action of Dynamic Control Keys as a Function of The LOAD/RUN Mode
KEY
LOAD
RUN
START
Clears and initializes program storage
area.
Starts program when stopped in HAL T
mode. Starts first program.
SKIP
Terminates current program and
initializes a new one.
Skip remainder of current program and
begins execution of next one.
HALT
Programs an operator data entry or
checkpoint in RUN MODE.
DELETE
Erases the last key entered. (Acts as a
backspace key.)
general description (con't)
Forty·seven different addresses .can be stored using a
12x4 keyboard matrix. (The illegal address is Digit 1 and
K4.) Switch Input K5 is used to enter programming con·
trol signals only and is not connected to the calculator in
apy way. The K5 input has key debounce protection
identical to the calculator chip, which debounces K1
through K4. The MM5765 does not accept a K1, K2, K3
or K4 input until the Ready signal from the calculator
goes from an idle, or high state, to a low state-indicating
the key has been debouncedby the calculator.
switching back to the Load Mode and entering the new
steps. The storage register pointer always returns to
the end of the previously entered key sequence when
the mode is changed from Run to Load, and to the
beginning of the first program when changed from
Load to Run.
"Start" Key (Refer to Table II for keyboard connections)
The function of this dynamic key depends upon the
position of the Load/Run Mode Control Switch:
The program chip is dynamic, which means power must
not be interrupted if a program is to remain stored.
When power is applied an internal circuit automatically·
clears the MM5765, inhibiting false entries to the cal·
culator and conditioning the system for entry of a
new program.
Actual storage of the sequential key information is in a
612·bit shift register (see Figure 1). Each input char·
acter is encoded into a six·bit word and placed in the
I/O register. If a Ready input confirms the character has
been accepted by the calculator as a valid key entry, or
the internal key debounce circuit in the case of Switch
Input K5, the new key information is transferred by
the commutator to the storage register. It is always
placed in sequence at the end of the existing program,
and an internal pointer is advanced six bits. The control
word detector keeps track of the pointer and special
codes required for control and alarm situations. In the
Run Mode, characters are sequentially transferred into
the I/O register, decoded on command of the Ready
signal and entered into the calculator via the appropriate
Switch Input Line.
1.
With the Mode Switch in the Load position, Start
clears the entire program storage register of all pro·
grams and initializes the device for accepting a new
set of programs by setting the pointer at the first
storage location.
2.
With the Mode Switch in the Run -position, Start
begins execution of the first program, or if pausing
in the Halt Mode, continues the program. This key
is not seen by the calculator and therefore has no
·affect on the calculations in progress.
The Start key is timed out by the key bounce·out
stability timer of the MM5765 on both key entry and
release.
TABLE II. Control Signal Input, K5, Keyboard Matrix
When the MM5765 is used with calculators with long
execution times; it may be useful to use a buffered
Ready signal to drive a "Busy" indicator. This would
give the user a visual feedback of status during Run
operations.
CONTROL KEY
FUNCTION
DIGIT TO
K5 CONNECTION
START
05 to K5
SKIP
06 to K5
DELETE
07 to K5
HALT
08 to K5
~
PROGRAMMER CONTROL FUNCTIONS
"Skip" Key
,jLoad/Run" Mode Control
This is the other dynamic key whose function depends
on the position of the Load/Run Switch:
This control requires' a single'pole, single throw static
switch. It prepares the MM5765 for either accepting a
key sequence or playing it back. Its position controls
the function of the dynamic keys as shown in Table I.
1.
Additional steps or programs can be appended to a
stored key sequence even after execution simply. by
8·69
In the Load Mode, this key terminates the current
program and marks the beginning of a new program.
Repetitious depressions will be ignored. The Delete
. key will erase this key from the storage register, but
the Alarm will be set indicating to the user that a
Ln
~
complete program has been deleted. A new Skip
will reinitiate the deleted program; otherwise, sub·
sequent deletions or additions will be to the pre·
vious program.
Ln
:!
:!
2.
In the Run Mode, if the MM5765 is at a Halt, the
Skip key will cause the remaining steps of the
current program to be skipped. Execution automatically begins again at the start of the next program
and continues to the first programmed Halt; in the
absence of, a Halt, execution will continue to the
end of the program.
if a Skip code is deleted or an attempt is made to delete
the Start code (beginning of first program).
The Delete key is debounced by the MM5765.
Switch Input K5 Keyboard Bounce Protection
The MM5765 programmer chip is designed to'interface
'with most low-cost keyboards and has characteristics
identical to the standard NSC calculator keyboard bounce
protection circuits.
A control key closure is sensed when Switch Input K5 is
forced more positive than the Logical High Level specified in the Electrical Specifications. At the instant of
closure, an internal "Key Bounce-out and Stability
Time" counter is started. Any significant voltage perturbation occurring on the K5 input during timeout will
reset the timer. Hence, a key is not accepted as valid
until noise or ringing has died out and the stability time
counter has timed-out. Noise that' persists will inhibit
key entry indefinitely. Release is timed in the same
manner. The actual control operation is performed by
the MM5765 after the release is ,validated, to differentiate the action from a calculator key.
Depression of this key is not seen by the calculator and
does not affect its status. The Skip key is timed out by
the key bounce·out stability timer of the MM5765 on
both key entry and key release.
"Halt" Key
The Halt key is a dynamic key that has a function only
in the Load Mode. It is ignored in the Run Mode:
The Halt key is used to program a data entry pause in
the playback of a key sequence. When a Halt occurs in
the program sequence during operation in the Run Mode,
the MM5765 ignores all key entries except Start or Skip.
The calculator chip accepts all nonprogrammer keys in
the normal manner so that constants or variables can be
entered, or intermediate calculations can be performed.
The operator may use the Halt as a decision making
point where he has the option to continue the program
in a number of ways based on an intermediate result;
e.g., skip to another program, restart the pr,esent program, or even go to a co-routine in a second MM5765
program chip.
ALARM CONDITIONS
An alarm condition will be indicated by the MM5765
program chip as a Logical High, Level output on pin 7.
An alarm condition can exist due to three circumstances:
If the user switches to the Load Mode during a Halt,
execution of the current program will be terminated
and the MM5765 will be ready to store additional keys
at the end of the last program. If the mode is then
returned to Run, Start will begin execution at the beginning of the first program.
1.
All 102 storage locations in the storage register
are full. The Alarm is reset by entering a Delete
key or if the mode is changed to Run and any key is
pressed. When the storage register is full, subsequent
data keys are ignored; the existing program is not
disturbed.
2.
An attempt is made to delete a Start key code in
the storage register during editing of a program.
The alarm is set and the Delete key is ignored. Any
of the calculator keys, the Skip or Halt keys or
moving the Mode Switch to Run and pressing any
key will reset the Alarm. '
3.
A Skip key code is delete~ from the storage register
while editing. The alarm is set and the Skip is
deleted. An'y calculator or programmer key, or
switching to the Run Mode and pressing a key
will reset the alarm condition. If a Skip key is not
re-entered, new key entries will be appended to the
previous program, and the original program being
edited will no longer exist.
The Halt key is debounced by the MM5765.
"Delete" Key
The Delete is another dynamic control key that functions
only in the Load Mode and is ignored in the Run Mode.
It provides a method of editing by erasing the end step
of the program. It is essentially a "backspace" key.
Multiple Deletes can be used to remove several steps
or even complete programs, but the Alarm will be set
TABLE III. Rel::ly Signal Description
READY SIGNAL
CALCULATOR FUNCTION
Idle
Ready is quiescently at a Logical High Level ('VV 55)'
Key entry and 'functional operation
When a key is depressed, the calculatorbounce-out stability timer
is initiated. Ready remains high until the bounce-out time is
completed and the' key is entered" ~twhich time it changes to a
Logical Low Level ('VV oo ).
Keynllease and return to idle
Ready remains low until key release is debounced and the'
calculator returns to the idl,e state, The low to high transition
'signals the return to idle.
8,70
TABLE IV. Mode and Alarm Truth Table
PIN
Load/Run Input
Alarm Output
MODE
LEVEL
RUN
LOW
LOAD
HIGH
ACTIVE
HIGH
INACTIVE
LOW
TYPICAL OPERATION
Loading a New Program
At power·on, the MM5765 automatically clears and
initializes the storage register. All that is necessary to
start programming is to switch to the Load Mode. If
unwanted programs already exist in the storage register
from previous operations, switching to the Load Mode
and depressing Start will clear the memory and initialize
a new program.
Programming is accomplished by simply keying the
calculator in the normal manner. The MM5765 memo
orizes each key in the sequence entered. I t is usually
convenient to have the calculator displaying as the pro·
gram is entered to catch entry errors and keep track of
progress. However, it is necessary to consciously consider the anticipated results when p"rogramming to ensure
a meaningful display at each step. For example, wherever
variables ,are to be entered in the program, the Halt
key is used rather than any numeric value. Because the
calculator chip does not see a Halt, the display will no
longer be correct as the remainder of the sequence is
loaded. One convenient way around the problem is to
depress and hold the Halt key down while a dummy
variable is entered into the calculator. The depressed
Halt key will lock-out the MM5765 without affecting
the calculator. An alternate approach would be to enter
the Halt'and the dummy variable, followed by the proper
number of Delete keys required to erase the dummy
variable from the storage register. Either approach results in a valid calculator display and stored program
during programming.
Because the primary reason for using a key sequence
programmer is to allow convenient recall of often used
routines or in optimizing a particular solution by iter·
ating a function many times with a variety of input
variables-in other words, many iterations of a common
sequence-it is always worth the time to spend a few
minutes planning the best way of entering the program.
Learning what the calculator should be displaying at
each step of the programming can be done conveniently
by keying the program while in the Run Mode, using
the proper dummy variables, and jotting down intermediate results. In this manner potential calculator
overflow conditions are caught, and subsequent Load
Mode entry errors can be easily detected.· When an
entry error is made while programming in the Load
Mode, use the Delete key to erase as many steps as nec·
essary, switch back to the Run Mode and depress Start
to correct the calculator display and return !o the Load
Mode to finish. If the program does not approach the
102 key capacity of the MM5765, you may wish to
simply use the calculator functions (such as Clear Entry)
to correct the error situation even though they will be
included in the stored program.
When the program is correctly loaded move the Mode
Switch to Run. The program is now ready to be
executed. Additions can be made to the program (even
after execution in the Run Mode) by returning to Load.
New key entries will be automatically appended to the
end of the existing stored sequence .. By executing the
program before returning to Load, the calculator display
will have a valid display and be in the correct state for
properly displaying the new key additions. In this
manner long programs may be constructed by connecting
together a series of short sequences which are debugged
as you go (reducing the possibility of error and min·
imizing cpnfusion).
Running a Program
Use of a stored program requires only that the calculator
be preconditioned, if necessary, and the Start key
depressed while in the Run Mode. The program will
continue to the end, or until a Halt is encountered in
the key sequence.
Halts act as a pause during execution to permit entry of
variable data, manual calculation of data, or checking of
intermediate values. They are also available as user de·
cision points for jumping to subsequent programs and
can provide the capability for multiprogram labeling.
When a Halt is encountered during execution, the
MM5765 stops making key closures and returns control
to the keyboard.
"Upon reaching the end of a program, the internal
pointer will return to the beginning and wait for another
Start key.
As discussed above, programming certain sequences can
result in errors in the calculator chip either during load·
ing or during execution. If an error occurs as the
program is loaded, the MM5765 will continue to store
key depressions as they are made-independent of the
calculator. Such a situation exists if a calculation results
in overflow during execution of a stored program. The
MM5765 continues to step through the sequence completely independent of calculator status as long as the
Ready signal responds properly. '
MUltiple Programs
Use of the Skip key in the Load Mode codes that
location as the beginning of a new program, just as the
Start key is used to initialize the first program. All other
aspects of loading the program are the same.,
When. a program stops at a Halt during. execution, the
user has the option of pressing the Skip key to jump to
the next program or the Start key if he wishes to con·
tinue the original sequence. When control passes to the
next program, execution begins and proceeds to the end
of that program or until a Halt is encountered.
10
CD
r-..
10
~
~
This property of automatically, executing a program
down to the first Halt provides a convenient method of
labeling multi programs. For example, entering a program
with the sequence:
LOAD
,
LOAD/RUN
PROGRAMMER
MODE
SWITCH
MM5765
r
QRUN
I
LOAD
READY
~
RUN
If'
Start
1
Halt
C
~}
(Load/Run
1
= Load Mode)
READY SIGNAL
fROM
CALCULATOR
CHIP
FIGURE 5. Switch Wiring for Adding Step Mode
(Calculator Clear Entry)
the programmer to step through the .stored program
starting from the first entry of the first program. Start
must be used to initiate the sequence, then any of the
control keys can be used. Each depression of Start, Skip,
Halt or Delete will advance the program being executed
by the calculator one step. When a Halt is encountered
in the program while in the Step Mode, the MM5765
ignores all key entries except .Start or Skip just as
df;!scribed in Table I. If the Mode Switch is moved to
Step, from a Halt. point in the Run Mode, the program
may be stepped from that point on by using Start or
Skip followed by depressions of any of the control keys.
Switching to Run from any intermediate point of a
Run operation from that point. From a Halt, a Start or
Skip Key must be pressed after switching to the Run
Mode.
Desired key sequence for Program No.1
Halt
Skip
2
Halt
C
j}
V..
QSHP
Desired key sequence for Program No.2
Halt
has stored two program sequences. In the Run Mode,
pressing Start will display a "1", a second Start will
execute Program 1 (or to the first internal Halt) eventually stopping at the 'last Halt and displaying a program
result. The operator now has the opportunity to make a
decision. He may rerun Program 1 by using the Start
key, or continue to Program 2 by depressing the Skip
key.
PROGRAMMING EXAMPLES
If he chooses Skip', a "2" will be displayed indicating
that Program 2 has been addressed (as programmed by
the Skip-2-Halt sequence at the beginning'of Program 2
in the Load Mode). Start will then execute Program 2
down to its first Halt: The' Program 2 result can be displayed by inserting another Halt at the end of that
sequence. If a thin! program has been stored in the
MM5765, depressing Skip will move the internal pointer
to the beginning of that program and execute it to the
first Halt. Assuming a Skip-3-Halt sequence was used at
the front of the program, a "3" would be displayed by
the calCulator. If the operator had wished to re'run Pro- '
gram 1, instead of advancing to Program' 3, he would
have used. Start (internal pointer is initialized). Start
(displays shows "1") and Start (program is. executed).
For a rerun of Program 2 from the last Halt of Program
2, he would push Start (internal pointer is initialized)
and Skip (pointer locates the top of Program 2, executes
to first Halt and calculator displays "2").
These examples assume use of the MM5738 calculator,
which is . an 8-digit, floating point, algebraic notation,
single memory chip with constant operation. Please review the MM5738 data sheet for explanation of keyboard notation and function capability.
Example 1
A problem often encountered in communications design
is the solution of
I I
8
x = ySin
-8
With a programmer and even a simple calculator like the
MM5738, this problem can be repetitively solved easily
without tables. First, program the sequence for approximating sin8 using
Adding a Step Mode Feature
83
85
Sin 8 ~ 8 - - + -
By returning the Ready input of the MM5765 to Vss
when the Mode Switch is in the Run Mode position,
and depressing any of the control keys (Start, Skip,
Halt or Delete) the program stored in the MM5765 may
be executed and advanced one step at a time. This
provides a convenient method of debugging programs.
3!
5!'
1208 - 208 3 +8 5
- - - - - - - , where 51
120
Figure 5 shows the wiring of a 2-pole, 3-position switch
used as the Mode Switch of a Programmer/Calculator
system with the Step Mode as an added·feature. Switching from the Load Mode to the Step Mode conditions
[(8 2
-
20) 8 2 + 120] 8
120
8-72
,-
,
where 8 is expressed in radians.
= 120,
Example 1 (Con't)
DISPLAY
KEY
C
C
2
Start
MS
0
2
2
2
2
4
4
20
-16
2
-32
2
-64
122
-64
-64
-64
-64
-64
120
56
2
1 12
120
0.9333333
X
20
X
MR
X
MR
+
122
C
Delete
Delete
Delete
Delete
120
X
MR
120
1T
COMMENTS
RUN/LOAD
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Clear calculator
Dummy variable "2" for 0 is entered.
MM5765 is initialized.
02 is formed
2
- 20) 0 is formed.
122 is an entry error
After entering "C", operator can simply
continue by entering 120, or can correct
program sequence by deleting last four
keys. Result is the same, except the second
alternative would use less program storage.
(0 2
Sin 0 for 0 = 2 radians is displayed
1T
Check program by executing with 0 = - , 4 3
3.14
4
Start
3.14
3
3.1 4
3.14
4
0.785
Run
Run
Run
Run
0.706861 3
3.14
3.14
3
1.0466666
Run
Run
Run
Run
Run
0.8660287
Run
Enter approximation of 1T
1T
o = - , in radians
4
'VSin"::" displayed
4
1T
o =-:-; in radians
3
1T
Start
'VSin- displayed
3
Now we would like to add to the same program the rest of the expression:
Sin 0
Y--
o
KEY
DISPLAY
RUN/LOAD
Run
Load
Halt
1
MR
X
Halt
1
Delete
1.0466666
0.955414
0.955414
1
1
0.955414
Load
Load
Load
Load
Load
Load
Load
8·73
COMMENTS
e
"1" is dummy variable for sin
"Halt" is tagged onto end of existing
program to allow readout of sin
during execution
e
Allows for Y entry
Dummy variable for Y
Dummy variable is removed from program
by Delete, or Halt could have been held down
while 1 is entered, in which case Delete would
not be required.
Example 1 (Con't)
Problems can now be solved using the program.
Sin(O.72)
Evaluate: 0.54----0.72
KEY
DISPLAY
0.72
Start
Start
.54
0.72
0.6594044
0.9158394
0.54
Start
0.4 945532
RUN/LOAD
Run
Run
Run
Run
Run
Run
COMMENTS
Enter () = 0.72 radians
Sin (0.72) displayed
Enter variable Y
Sin(O.72)
0.54
displayed
0.72
A sequence could easily have been included to convert degrees to'radians.
PROGRAMMING
As an example of a multiprogram application, consider an automobile salesman who needs to calculate price plus sales
tax, down payment and monthly payment on new cars many times a day. Again assume use of the MM5738 (although
more powerful NSC calculators could obviously make the problem even easier). To simplify the example, assume the
finance time is fixed at 36 months and the interest rate at 12% of the unpaid balance.
KEY
C
Start
1
Halt
C
5
%
X
Halt
100
MS
+
K=
Halt
Skip
2
Halt
C
Halt
DISPLAY
1
1
0
5
0.05
0.05
0.05
100
100
5.
105.
105
105
2
2
105
105
Run
Load
Load
Load
Load
Load
Load
Load
load
Load
Load dummy variable for car price. Switching
to Run is another method of entering a dummy
variable without having to Delete.
Run
Dummy down payment %.
20
%
X
MR
0.20
0.20
100
20
20
20
3
3
20
20
100
-80
-80
1.0 1
1.01
1.01
1.0201
MR
MS
1.01
X
1.01
COMMENTS
Load
Load
Load
Load
Load
Load
Load
Load
Load
20
Halt
Skip
3
Halt
C
RUN/LOAD
Load
Load
Load·
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
8·74
Clear calculator and programmer. Label
Program No.1
Clear program label.
.
Sales tax = 5%.
Program No.1 displays price + tax amount.
Initialize Program No.1
Label Program No.2
Clear program label.
"Halt" for down payment %.
Program No.2 displays required down payment.
Initialize Program No.3.
Label Program No.3.
Clear program label.
Program No.3 computes monthly
payment from equation
Monthly payment = [Total loan (1 + i/q)nq/nq]
i = interest per year, 12% is assumed.
nq =total number of months =36
q = 12 months per year
(1 + i/q) = 1.01
PROGRAMMING (CON'T)
KEY
X
1.01
K=
X
MR
36
Halt
DISPLAY
RUN/LOAD
1.040604
1.0828566
1.1725784
1.1725784
1.0 1
1.1843041
1.1961471
1.4307678
1.4307678
80
1 14.4 6 142
36
3.179483
3.1 79483
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
COMMENTS
(1.01 )4
(1.01 )8
(1.01) 16
Program No.3 displays required monthly payment.
EXECUTION OF PROGRAM
Salesman has potential customer for $4995.95 automobile. Bank requires 20% down. The customer wants to know
amount of down payment and monthly payments over 3 years at 12%.
KEY
DISPLAY
Start
Start
4995.95
Start
Skip
Start
20
Start
Skip
Start
1
0.05
4995.95
5245.7475
2
5245.7475
20
999.1 9
3
1 58.84543
RUN/LOAD
Run
Run
Run
Run
Run
Run
Run
Run
Run
Run
COMMENTS
Program No. 1 label.
Sales tax displayed.
Price entered.
Price + tax displayed.
Program No.2 label.
Enter % down.
Down payment displayed.
Program No.3 label.
Monthly payment displayed.
8·75
Calculators
MM5766 calculator programmer
general description
The. MM5766 provides a convenient and inexpensive
means of adding "learn mode" programmability to the
National Semiconductor MM5758 scientific calculator
chip. The monolithic MOS integrated circuit combines
P·channel enhancement and depletion mode technolo·
gies to obtain low voltage and low power characteristics
necessary· for economical battery·powered products.
Up to four switch inputs (K1, K2, K3 and K4) and up
to twelve digit lines are connected in parallel with the
calculator switch and digit terminals that scan the. keyboard. Keys stored in the MM5766 that are entered by
selecting K 1 through K4 are encoded simply as matrix
positions, i.e., a particular switch input at a specific
digit ·time. Therefore it is the key matrix address that is
stored and not the key function. Please refer to the
MM5765 data sheet for a detailed functional description.
The MM5766 is a dynamic key sequence programmer
that memorizes any combination of key entries while in
the Load Mode, then automatically plays back the pro·
grammed sequence as often as desired in the Run Mode.
Up to 102 characters can be stored in multiprogram
sequence blocks. Each block, or program, can be executed individually or the operator can make the decision
to branch to specific programs, run each. in series or
perform intermediate calculations from the keyboard.
When programming irl the Load Mode, the Delete key
provides a convenient editing feature. and the Halt key
programs variable data entry points where control is
temporarily returned to the operator in the Run Mode.
Start and Skip keys control operation in both modes.
features
Synchronization with the calculator chip is accomplished
by monitoring its Digit Output and Ready signals. The
digit signals give timing information while the Ready
indicates status of the calculator and synchronizes the
key entry interface between it and the MM5766.
•
Any key sequence, including constants and data entry
points, may be stored automatically in the Load Mode
and executed in the Run Mode.
•
102 step storage capacity of up to 47 different keys
arranged in 12 x 4 matrix.
•
Multiprogram capability
•
Provision for editing in Load Mode using the Delete
key
•
Convenient verification of programs using a Step
Mode feature
•
Alarm for full storage condition-or if a deletion of
the first step in a program is attempted
•
Power-on clear
a
block 'and connection diagrams
Dual-ln·Line Package
22
voo
21
K4
MAIN
CONTROL
K3
KZ
K5
Kl
READY
05
RUN/LOAO
09
TEST
DB
ALARM
06
011
07
03
04
02
DID
+-01
+-;-"D2
~012
1/0
TIMING
AND
CONTROL
DIGIT
INPUTS
+-+Kl
+-+K2
. . . . K3
KEY
SWITCH
1/0
. . . . K4
+ - LOAO/RUN MODE
vss
012
TOP VIEW
Order Number MM5766N
See Package 21
FIGURE 1
8·76
absolute maximum ratings
operating voltage range
Voltage at Any Pin Relative to Vss Vss + 0.3V to Vss - 12V
(All other pins connected to V ss )
Ambient Operating Temperature
O°C to +70°C
Ambient Storage Temperature
-55°C to +150°C
300°C
Lead Temperature (Soldering, 10 seconds)
V ss -6.5V::; Voo::; V ss -9·5V
(Vss is always the most positive supply)
dc electrical characteristics
PARAMETER
100
Operating Supply Current
CONDITIONS
MIN
V oo =V ss -9.5V, T A =25°C
TYP
MAX
8.0
18.0
UNITS
mA
Keyboard Scan Input Levels
(Kl, K2, K3, K4)
V IH
Logica I High Level
V oo =V ss -7.2V
V ss -2.5
V ss -4.0
Voo = Vss - 8.8V
V IL
Logical Low Level
V
V
Voo = Vss -6.5V
V oo +l.0
V
Voo = Vss - 9.5V
V oD +1.5
V
K5 and Digit Input Levels
(D2 through D12)
V IH
Logical High Level
Voo = Vss - 7.2V; IIH
Voo = Vss - 8.8V; IIH
V IL
Logical Low Level
2: - 200llA
2: -20 01lA
V ss -2.5
V
V
V ss -4.0
Voo ~ Vss - 6.5V
V oo +l.0
V
Voo = Vss - 9.5V
V oo +l.5
V
Voo = Vss - 6.5V
V ss -5.0
V
Voo = Vss - 9.5V
V ss -6.0
V
Other Inputs (Ready, Run and Test)
V IH
V IL
Logical High Level
Logical Low Level
V ss -2.5
V
Switch Buffer Output Levels
(Kl, K2, K3, K4)
V OH
VOL
Logical High Level
Logical Low Level
Voo = Vss - 7.2V
V ss -1.5
Vss
V
Voo = Vss - 8.8V
V ss -3.0
Voo = Vss - 6.5V
Vss
V ss -6.0
V
Voo = Vss - 9.5V, IOL ::; -1.5 rnA
V ss -7.0
V
V
Alarm Output Current
Sou rce Cu rrent
V OUT = Vss -4.5V, Voo = Vss -G.5V
-5.0
V OUT = Vss - 7.SV, V Oll
.~
mA
-S.O
V OUT = Vss - 5.2V, Voo ~ Vss -7.25V
Vss - a.5V
mA
-20.0
mA
ac electrical characteristics
PARAMETER
tR and
CONDITIONS
MIN
TYP
MAX
UNITS
Digit Input Time
(Figure 3)
70
Word Time
(Figure 3)
0.64
ms
Switch Input Time
(Figure 3)
70
IlS
Switch Output Time
(Figure 4)
70
Switch Propagation Delay Output
(Figure 4)
15
Switch Output Transition Time
CLOAO = 100 pF, (Figure 4)
2
IlS
IlS
26
IlS
IlS
tF
Switch Input K5 Key Bounce·out
17.0
4.5
ms
Stability Time
(The time a keyboard input must be
continuously higher than the minimum
Logical High Level to be accepted as a
key closure, or lower than the maximum
Logical Low Level to be accepted as a
key release, i.e., 6 or 7 cycles of D2.)
Ready Timing
(FiglJre 3)
tR=tF
3
to
5
0.1
IlS
/1S
tS ET ·UP
20
/1S
tpw
400
/1S
Key Closure Rate
ms
40
(Time between consecutive key outputs
in Run Mode.)
Key Acceptance Rate
47
(Time between consecutive key inputs
in Load Mode.)
8-77
ms
[:)I
'121
1
Z
3
4
z31
Vss
Kl
Voo
(8)
KZ
I\..
MM5758
K3
K4
D.
7
6
Dc
6
7
15
14
13
D.
8
D.
5
5
D.
Dc
DS8868
4
3
"
ROY
Do
ZZ
8
lZ
11
Do
V
116
Z
1
V
10
17
18
91
1
+
0
CS
TAN
9
MS
SIN
8
I!X
CDS
7
X-Y
Z
MR
C
6
ARC
lOG
EN
4
vX
ROL
HALT
Y'
DElETE
LM
SKIP
3
9
S, f----'
4
Sb _17_ _
6
S,~
8
I
5
SEGMENT
OUTPUTS TO
DS8867 SEGMENT
DRIVER
10
13
Sdf---DISPLAY
NSA5101
S.~
IZ
19
S,f----
14
15
S,f----
ZO
7
Sdp I--< I -
FROM
OS8867
SEGMENT
DRIVER
I
e'
3
Z
X
1
-
I
START
,b-B
ZI
~
15k
H~
100pF
Vss
L..-
100k~
lOOk
~Hr
~1
1!474C3~
Z K4 K5
ZZ
K3
ZI
KZ
ZO
Kl
-
18
r:vss
r-)IOOPF
lZ
DIZ
8
011
13
010
18
15
17
09
08
16
07
06
19
05
14
9
04
03
~!474C3Z
OZ
ROY
~
7 .
ALARM
MM5766
TEST
RUN/LOAD
Voo
6
r;- tJ.
.,r, Voo
STEP
+3VTD +4.5V
-k
1
Vee
LOAD
~
Vss
Vss
o
Lo-....
RUN
-----...;.;-ovoo
ON·OFF
SWITCH
FIGURE 2. Interface of MM5766 Programmer with MM5758 Scientific Calculator
8·78
PROGRAM
MODE
SWITCH
f---------WORDTlME------={F
Ir-------------
-
DIGIT 2
INPUT
DIGIT TIME
VOL
.
DIGIT 1
INPUT
VOL
DIGIT 4
INPUT
Kl SWITCH I/O
WITH
KEY DEPRESSED
AT Kl· OJ
"
1:
"
90%
10%
READY
911"~
~-----H-------.....,
lOY.
f-------,PW-----jl
FIGURE 3.lnput Timing
DIGIT J INPUT
Kl SWITCH I/D OUTPUT
",DIGIT J
INPUT
RI~~~~
Kl SWITCH
liD DUTPUT
\.
/
I I )l I I I I I ~ I I I I I I I I I I
--..J
I
~'ll..... 1 I-;1/
Kl . DJKEY IS
ENTERED INTD
CALCULATOR
1/~2~~~!~~
I I I I I
I
I
Kl . DJ KEY RELEASE
TIMED DUT
BY CALCULATOR
--------------,Ir-,-r1""""T1-r1-'lrTl-,T"I,-,~~~~-_-_-_-=
K2 . OJ KEY IS ENTERED
INTO CALCULATOR
FIGURE 4.
P~ogrammer
8·79
Output Timing
K2· OJ KEY
RELEASE
Calculators
MM5767 slide rule calculator*
general description
features
The single·chip MM5767 Slide Rule Calculator was
developed with the primary objective of low endproduct cost. A complete calculator as shown in Figure
1 requires only the MM5767, a 20 or 22 key keyboard,
DM8864 digit driver, NSA298 LED display and a 9V
battery with appropriate hardware.
• 20 or 22 key keyboard
• Full 8-digit entry and display capacity
• Complete ele~tronic slide rule capability
• Arithmetic functions: +, -, x, 7,
l/x
• Logarithmic functions: In x, log x, eX
• Trigonometric functions: sin x, cos x, tan x, arc
sin x, arc cos x, arc tan x
• Other functions: yx, n, change sign, exchange,
radians to degrees, degrees to radians
..;x,
Keyboard decoding and key debounce circuitry. all
clock and timing generation and 7-segment output display encoding are included on-chip and require no
external components. Segments can usually be driven
directly from the MM5767, as it typically sources about
8.5 mA of peak current. (Note: the typical duty cycle
.of each digit is 0.104; average LED segment current is
therefore approximately 0.89 mA.) The left-most digit
is used for the negative sign or the decimal point of a
number less than unity.
• Three-register operational stack
• Independent accumulating storage register with store,
recall, memory plus and memory minus functions
•
•
Floating point input and output
Direct 9V battery compatibility; low power dissipation
•
•
Power-on clear
No external components required other than display
digit driver, keyboard and LED display for complete
calculator
• Error indication for over range, overflow and invalid
operations
• Left justified entry and results. with trailing zero
suppression
An internal power-on clear circuit clears all registers,
including the memory, when Voo and Vss are initially
applied to the chip.
Trailing zero suppression allows convenient reading of
the left justified display, and conserve~ power. The
DM8864 digit driver is capable of sensing a low battery
voltage and providing a signal during Digit 9 time that
can be used to turn on one of the segments as an
indicator.
•
•
Automatic display cutoff
Reverse polish notation
*Note: For detailed information on electrical specifications and key operations please refer to the MM5760 data sheet.
connection diagram
keyboard outline
Dual-I n-Line Package
DIGITJ-1..
~DIGIT4
DIGIT22..
~DIGIT5
~DlGIT6
DIGITI.!..
SWITCH
INPUTS
r!!- DIGIT7
["~
KJ..!..
~DIGITB
6
NC"';"
~DIGIT9
KI..2..
r!!- READY
voo..!..
~SEGMENTD
SEGMENT G..!.
~SEGMENT E
SEGMENT B.!!.
..!! SEGMENT A
SEGMENT F.!!.
.!!. DECIMAL POINT
~SEGMENTC
Vss.!!.
*Optional
TDPVIEW
Order Number MM5767N
See Package 22
8-80
The user has access to four registers designated X, Y, Z
and M. X is the display and entry register, and is the
bottom of a "push·up" stack that also includes registers
Y and Z:
Typical current drain of a complete calculator displaying
five "5's" is 30 mAo Automatic display cutoff is
included. If no key closure occurs for approximately
35 seconds, all numbers are blanked and all decimal
points displayed.
IZ
Iz
The keys are arranged in a three·by·nine matrix (Figure
2). In addition to seven arithmetic functions plus loga·
rithmic, trigonometric and accumulating memory
functions, the calculator is capable of calculating yx,
automatically entering 7T and providing degrees/radian
converions.
Iy
Iy 1m
Ix
IX
1M
Note: Lower case letters designate the data in the register
identified by a capital letter.
READY
I
('
I
I
I
I
S, 5b 5c 5d 5, 5159 OP
KJ
MM5767
r--tK4 01 02 OJ 04 05 06 07 08 09
I
:"1
T
LV GNO Vee
IND
OP
59
51
5,
5d
5c
5b
5,
09
08
07
06
05
04
OJ
02
N5A1298I
1111 111111111111 II
C/. C/. C/. C/. C/. C/. C/. C/. C/.
01
r-
r---
-_.....+
-
POWER~
KEYBOARD
0
058864
OR
05887J
FIGURE 1. Complete Calculator Schematic
K3
Kl
09
K4
TAN/6
COS-'/7
1T/F
07
R --+ o/x
SIN-' /8
0*
06
0--+ R/-;'
TAW'/9
LN/O
05
V-I·
04
M+/+
M-/-
03
CLF/CL
MS/MR
Log/1
YX/2
e X/3
02
CA*
l/x / CS
COS/4
08
EXC/EN
SIN/5
01
'Keys not included in 20 key version.
FIGURE 2. Keyboard Matrix
8·81
9V
MALLORY
MNI6D4
OR
EQUIV.
KEYBOARD BOUNCE AND NOISE REJECTION
segments and display nine decimal points. Any key depression will restore the display; to restore the display
without modifying the status of the calculator, use two
change sign, "CS," depressions.
The MM5767 is designed to interface with most low cost
keyboards, which are often the least desirable from a
false or mUltiple entry standpoint.
READY SIGNAL OPERATION
A key closure is sensed by the calculator chip when
one of the key inputs, K1, K30r K4 is forced more
positive than the Logical High Level specified in the Electrical Specifications. An internal counter is started as a
result of the closure. The key operation begins after nine
word times if the key input is still at a Logical High Level.
As long as the key is held down (and the key input remains high) no further entry is allowed. When the key
input changes to a Logical Low Level, the internal counter
starts a sixteen word time-out for key release. During
both entry and release time-outs the key inputs are
sampled approximately every other word time for valid
levels. If they are found invalid, the counter is reset and
the calculator assumes, the last valid key input state.
The Ready signal indicates calculator status. When the
calculator is in an "idle" state the output is .at a Logical
High Level (near Vss ). When a key is closed, the internal
key entry timer is started. Ready remains high until the
time-out is completed and the key entry is accepted as
valid, then goes low as indicated in Figures 3 and 4. It
remains at a Logical Low Level until the function initiated
by the key is completed and the key is released. The low
to high transition indicates the calculator has returned to
an idle state and a new key can be entered.
ERROR INDICATION
In the event of an operating error, the MM5767 will
display all zeros and all decimal points. In addition to
normal calculator overflow situations which occur as a
result of adding, subtracting, mUltiplying or dividing and
including division by zero, the error indication is displayed for any other calculation where the resu It is
IR I > 99999999 or IR I::; 0.00000001.
One of the popular types of low-cost keyboards available, the elastomeric conductor type, has a key pressure
versus contact resistance characteristic that can generate
continuous noise duri,ng "teasing" or low pressure key
depressions. The MM5767 recognizes a series contact resistance up to 50 ~n as a valid key ~Iosure, assuring a
reliable interface for that type of keyboard.
For error conditions the Z-regist~r is automatically
cleared and the Y- and M-registers are saved. An error
condition is cleared by depressing any key except
"1/X," "7," "LOG X" or "LN X." Operation on the
X register with an error displayed will be performed as
if X contained a zero.
AUTOMATIC DISPLAY CUTOFF
If no key is depressed for approximately 35 seconds, an
internal automatic display cutoff circuit will blank all
DIGI~ ~.
READY
jVOH
~
~
.
VOL
--1.
\
~"~"FOH
v
.
__--------.J
FIGURE 3. Ready Timing
NEW
KEY IS
L
t
DEPRESSED
SWI~~~
INPUT
,il
'
.
I
1---9WOROS-----
t
nL-Jn·L-JnJUU
L,. .
. 11''-______ 1------
~
"'NOISE"
READY
KEY IS
RELEASED
"NOISE'!'"
l
16WORDSAFTER
KEY RELEASE OR
_ _ AFTER CALCULATION
iS COMPLETE
WHICHEVER IS
•
LONGER.
J
r
!
t~------------------~t
NEW KEY HAS
BEEN ACCEPTED
BY CALCULATOR.
THE KEY MAY
BE RELEASED.
FIGURE 4. Functional Description of Ready Signal and Key Entry'
8-82
NEXT KEY
CAN BE
ENTERED.
•
RANGE AND ACCURACY OF FUNCTIONS
.jX) have eight digit accuracy. All results are truncated.
The smallest magnitude that can be displayed is
±O.00000001 and the total range is from -99999999 to
+99999999. The arithmetic functions (+, -, x, 7, 1/X,
Table I summarizes range and accuracy of the other
functions. Arithmetic calculations will be completed in
less than 0.5 second; all others except yx in less than
2.5 seconds and yx in less than 5 seconds.
TABLE I. Digit Accuracy for Various Functions
FUNCTION
RANGE
APPROXIMATE
ACCU RACY (Note 1)
SIN, COS, TAN
~ -90 to '\, 90
0
0
'\, -360 to '\, 360
7 Digits
6 Digits
ARC SIN and ARC COS
'\, -1 to'\, +1
6 Digits
ARC TAN
-99999999 to 99999999
6 Digits
LOG
X~O
6 Digits
eX
-28 ~ X ~ £n 99999999
6 Digits
X~O
6 Digits
LN
0
0
""
v'x
X~O
yX
Y>O
X £n Y ~ £n 99999999
8 Digits
Note 1: Six digit accuracy, as an example, wou Id" be:
123456XX
L±1
n digit accuracy has the nth digit 'from the MSD bei ng displayed accurate within ± 1.
8·83
- 5 Digits
.Ca leu lators
MM5777 calculator 6-digit, 4-function, floating decimal point
general description
The MM5777 single:chip calculator was developed using
a metal gate, P-channel, enhancement and depletion
mode MOS process with low end-product cost as the
primary objective. A complete calculator, as shown in
Figure 1, requires only a keyboard, 'OS8977 digit driver,
6 1/4 digit LED display, an NSA 1161- and a 9V battery
with appropriate hardware.
The Ready output signal is used to indicate when the
calculator is performing an operation (Table I). It is
useful'in testing of the device or when the MM5777 is
used as part of a larger system and is required to interface with other logic. (Another feature that is important
in such applications is the ability to reduce the key
debounce time from seven word times to four word times
by forcing the Digit 6 output high during Digit 7 time.)
Keyboard decoding and key debounce circuitry, all
dpck and timing generation and output 7-segment displilY decoding are all included on-chip and require no
external discrete components. LED segments can be
driven directly from the MM5777 as ittypically sources
8.0 mA of peak current. [Note: The typical duty cycle
of each digit is 0.143; average LED segment current is
therefore approximately 0.143 (8.0 mA), or 1.14 mAo
Correspondingly, the worst-case average segment current
is 0.143 (4.5 mAl, or 0.64 mA.) The seventh digit is
used for the negative sign of a six digit number and as an
error indicator. Negative results less than six digits will
have the negative sign displayed one digit to the left of
the most-significant-digit (MSD). The DS8977 digit
driver is capable of indicatin'g a low battery voltage condition by turning on a seventh digit segment-which does
not hinder the actual calculator operation.
'features
•
Leading and trailing zero suppressi(~>n allows convenient
reading of the right justified display and conserves
power. Battery life is estimated to be 10 to 20 hours,
depending on battery quality, operating schedule and
the average number of digits displayed.
connection diagram
6-digit entry and display capacity for positive and
negative numbers
•
Four functions (+, -, x, 7)
•
Floating negative sign indicator is always displayed
one digit to left of MSD
•
Convenient algebraic key entry notation
•
Floating point input and output
•
Chain operations
•
Direct 9V battery compatibility; low power
•
Direct interface to LED segments
•
No external components are required' other than
display .digit driver, keyboard and LED display for
complete calculator
•
Overflow and divide-by-zero error indication
•
Right justified entry and results, with leading and
trailing zero suppression
keyboard outline
Dua)·) n-Line Package
READY....!..
2!.DIGIT 4
7.2..
.!:..DIGIT5
DIGIT 1.2..
~DIGIT6
DIGIT 2.!.
~N/C
DIGIT 3..!.
~N/C
DIGIT
..!.
r12- KEY INPUT 3 (K3)
SEGMENT
d..l.
.!2.. KEY INPUT 2 (K2)
SEGMENT
g.!.
.!2. KEY INPUT 1 (K1)
Vee
9
SEGMENTb-
~SEGMENTe
SEGMENT'.!!!..
~SEGMENT.
PT~
~SEGMENTc
DECIMAL
D
'
ON~
7'
9
x
456
DODD
1
2
J
+
DODD
CE/C
0
=
DODD
~NC
Vss.!!.
8
DODD
TOP VIEW
Order Number MM5777N
See Package 22 '
8-84
3:
3:
(11
absolute maximum ratings
Voltage at Any Pin Relative to Vss. (All
other pins connected to V ss).
-...J
-...J
-...J
Vss + 0.3V to Vss - 12.0
o
DoC to +70
o
-55°C to +150
e
e
Ambient Operating Temperature
Ambient Storage Temperature
300°C
Lead Temperature (Soldering, 10 seconds)
operating voltage range
6.5V::; Vss - V DD ::; 9.5V
(Vss always defined as most positive supply voltage.)
dc electrical characteristics
PARAMETER
Operating Supply Current (I DO)
Keyboard Scan Input Levels
(Kl, K2 and K3)
Logical High Level (V IH)
Logical Low Level (V1d
Digit Output Levels (Note 1)
Logical High Level (V OH )
Logical Low Level (VOL)
Segment Output Current
(Sa through Sg and Decimal Point)
Ready Output Levels
Logical High Level (V OH )
Logical Low Level (VOL)
CONDITIONS
MIN
voci = vss -9.5V
T A = 25°C
Vss -6.5V ~ Voo ~ Vss -9.5V
Voo = Vss -6.5V
Voo = Vss -9.5V
V ss -2.5
Vss -6.5V ~ Voo ~ Vss -9:5V
V OD = Vss -6.5V
Voo = Vss -9.5V
V ss -1.5
TA = 25°C
V OUT = Vss -3.BV, Voo
V OUT = Vss -5.0V, Voo
V OUT = Vss -6.5V, Voo
= Vss
= Vss
= Vss
lOUT = -{).4 mA
lOUT = 10.uA
-6.5V
-B.OV
-9.5V
-5.0
TYP
MAX
UNITS
B.O
14.0
mA
V ss -5·0
V ss -6.0
V
V
V
V ss -6·0
V ss -7- 0
V
V
V
-B.O
-10.0
-15.0
V ss -1.0
V oo +1.0
mA
mA
mA
V
V
Note 1: With digit connected through key to K·line and to DS8977.
ac electrical cha racteristics
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Word Time (Figure 2)
0.50
1.20
4.1
ms
Digit Time (Figure 2)
70
170
5BO
.us
Interdigit Blanking Time (Figure 2)
4
.us
Digit Output Transition Times
(t R1SE and tFALLI
CLOAO = 100 pF
2
.us
Keyboard Inputs High to Low
Transition Time After
Key Release
CLOAO
= 100 pF
4
.us
..
Ready Output PIop'agation Time
(Figure 3)
Low to High Level (t pOH I
High to Low Level (tpod
CLOAO = 100 pF
CLOAO = 100 pF
~O
0.06
140
0.5
480
1.5
.us
ms
Key Bounce·out Stability Time
(The time a keyboard input must be
continuously higher than the
minimum logical high level to be
accepted as a key closure, or con·
tinuously lower than the maximum
logical low level to be accepted as a
key release.)
3.40
8.20
29.0
ms
Calculation Time for
999999.;. 1 = 999999
53.9
12B.7
451
ms
8·85
BIll
I Kl
rl
i'o!-
II
Sa Sb Sc Sd S. St Sg dp
K2
MM5777
K3 01 02 03 04 05 06 07
:1
i"o!-......
dp
I
1• • • • • • •
L CI CI CI CI CI. C/NSA1161
1
T
-
9V-=-
LJ~
'-
i'c!-.......
I
• L7. L7. L7. L7. L7. L7.
LV GNO Vee
INO
~
i'ol-.....
1
POWER
r--o:......
~...... ~....... ~.......
OS8917
~....... ~....... ~.......
7
i'o.!.-
.......
0
~.......
C
.......
......
KEYBOARD
CALCULATOR CHIP
DISPLAY DRIVER
LED DISPLAY
FIGURE 1. Complete Calculator Schematic
TABLE I. Ready Signal Description
CALCULATOR FUNCTION
Idle
"
READY SIGNAL
READY is quiescently at a Logical High Level ('VV ss ).
Key Entry and Functional Operation
When a key is depressed, the bounce-out stability timer is initiated.
READ Y remains high until the bounce-out time is completed and the
key is entered, at which time it changes to a Logical Low Level ('VV DD ).
Key Release and Return to Idle
READY remains low until key release is debounced and the calculator
returns to the idle state. The low to high transition signals the retu,rn to
idle. (The display may lag the READY by up to eight word times.)
KEY INPUT BOUNCE AND NOISE REJECTION
The MM5777 calculator chip is designeq to irterface
with low cost keyboards, which are often the least
desirable from a noise and false entry standpoint.
or ringing has stopped and the stability time counter has
timed out. Noise that persists will inhibit key entry
indefinitely. Key release is timed in the same manner.
A key closure is sensed by the calculator chip when one
of the Key Input Lines, Kl, K2 or K3 is forced more
positive than the Logical High Level specified in the Electrical Specifications. At the instant of closure, an internal
"Key Bounce-out Stability Time" counter is started.
Any significant voltage' perturbation occurring on the
switched key input during timeout will reset the timer .
. Hence, a key is not accepted as a valid entry until noise
One of the popular types of low cost keyboards
available, the elastomeric conductor type, has.a key
pressure versus contact resistance characteristic that can
generate continuous noise during "teasing" or low pressure key depressions. The MM5777 defines a series
contact resistance up to 50 kn as a valid key closure,
providing an optimum interface to that type oJ keyboard
as well as more conventional types.
8-86
ERROR CONDITIONS
Decimal Point
In the event of an overflow, the MM5777 will indicate
error in the leftmost digit and at least five of the signifi·
cant digits of the answer. Division by zero results in an
error indication with six trailing zeros. Once in an error
condition, all keys except the clear key are ignored.
When used with the NSA 1161 display, segments f and g
will be displayed in the seventh digit in an error
condition.
First depression of this key in a number entry will enter
a decimal point in the LSD position of the display
register. Subsequent depressions o'f the decimal point
key before any function key will be ignored.
Add, Subtract, Multiply or Divide Keys
First depression after a number entry will terminate the
entry, perform the previously recorded operation, if
any, and record the function key depressed as the next
operation to be performed after another number entry.
Subsequent depressions of any function key, without an
interceding number or decimal point entry will supersede
the previous function as the next to be performed. After
an equal key, the displayed result of the equal operation
will be re·entered and the function key depressed will
become the next operation to be performed after a
number entry is followed by another function key
(including equal).
KEY OPERATIONS
Clear Key
Operation after a number entry clears the entry and
displays a previous result. Second depression clears all
registers and displays a zero without decimal point in
the LSD. Operation after a function key (+, -, x, -7- or =)
clears all registers and displays a zero without decimal
point. Two depressions are always required after power
is applied.
Number Entries
First, entry clears the display register and enters the
number into the least significant digit (LSD) of the
display register. Second through sixth entry shifts the
display register left one digit and enters the number into
the LSD. The seventh, and subsequent entries, are
ignored and no error conditi on is generated. Because
only five positions are allowed to follow the decimal
point, the sixth and subsequent entries after a decimal
point entry are ignored.
Equal
First depression after a number entry will terminate the
entry, perform the previously recorded operation and
record the fact that an equal key has been depressed.
Depression after the add, subtract or divide keys, with·
out an interceding number or decimal point entry, will
be ignored. After a multiply key, the number being
displayed will be squared.
.
f---------WORO TIME---------
~Sri
OIGI
OUTPU
01
i--INTEROIGIT BLANKING TIME
r------,
"---
.::
r-
hTIME
02
r-l
03
II
07
i---
DECIMAL POINT
I
SEGME NTS
Sa
- !---
r------,
'----I
I
Sb
r-I
Sc
1'--Sd
'---
Sf
-
Ir---
I
I
I
Sg
IL----
rl
Ir--
S.
~
L-J
01
ACTUAL
DISPLAY:
02
c, C
1-, _I
07
I
I
•
03
04
05
06
I
LI ::1 ::1 1
I _I.L 1
•
01
07
01
SEGMENT
DESIGNATION
r-
.
ffTb
·/~/c.
d
FIGURE 2. Display Timing Diagram
8·87
DIGIT7 Vss
I
~_ _ _ _ _ _-I'
Voo--.l 10%
Vss
--1-------,....-----.,
Voo
--+-_----J
Vss
~
DIGIT 1
/
POL
READY
I--' 10%
-
j--tPOH
VOD _ _ _1_0_%~~VO_L_____________-li
~------90%
:1
0H
FIGURE 3. Ready Output Timing
sample problems
I. Single Calculations
5 x 3.14 = 15.7
Key
Comments
Display
c
Two clears are required after power-up. '
C
o
5
5
5
3
3.
x
3
1
4
3.1
3.14
15.7
II. Chain Calculations
A.
23.37 + 243.00 - 489.16 = -222.79
Key
Display
c
C
23.37
+
243
x
Comments
o
23.37
23.37
243
266.37
Function key completes previously recorded "+" operation.
266.37
Wrong "X" function key is updated to "-."
489.1 7
266.37
489.16
222.79
Number entry error is cleared and corrected. Note the
floating negative sign.
(Wrong Function Key)
489.17
C
489.16
B.
Find square root of 169 using a modified Newton approximation method. Let N represent the squared number and Xo
the initial estimate. The first approximation, Xl, is
If
Xl = (N/Xo + Xo)/2
Xo is 15,
Xl = (169/15 + 15)/2
X2 = (169/X l + Xl )/2
X3 = (169/X 2 + X 2 )/2, etc.
Key
c
C
169
15
+
15
2
169
13.13
Comments
Display
o
169
169
15
1 1.2666
15
26.2666
2
13.1333
169
169
'13.13
Result is Xl
Four digits are conveniently remembered
8·88
sample problems (con't)
II. Chain Calculations (continued)
Key
Display
+
12.8712
13.13
26.001 2
13.13
2
Comments
2
x
1 3.0006
Result is 2 , which is usually adequate. If more
accuracy is required, continue the iteration.
III. Auto Squaring
A.
5.25 2 = 27.5625
Key
Display
Comments
c
C
5.25
B.
o
5.25
5.25
27.5625
Number in display register is squared.
5
5.25 = 3988.37
Key
c
C
5.25
x
5.25
Display
Comments
o
5.25
5.25
27.5625
27.5625
759.69 1
759.69 1
5.25
3988.37
Auto square = 5.25 2
Auto square = 5.25 4
Result is 5.25 5
8·89
Calculators
MM5780 educational toy calculator
general description
When the battery voltage falls below an operational
level, an internal circuit will disable both indicator
outputs; i.e., neither indicator will be on after depression
of Test.
The MM5780 single-chip, educational calculator was
developed using a metal gate, P-channel, enhancement
and depletion mode MOS process. It was designed with
low end-product cost as the primary objective and is
directed toward the educational toy market. Besides the
MM5780, a complete calculator, as shown in Figure 1,
requires only a keyboard, "Right" and "Wrong" LED
display; a 9V battery and an on/off switch. Keyboard
encoding and key debounce circuitry, all clock and
timing generation and the capability to drive the two
LEOs are all included on-chip and require no external
discrete components.
The Ready output signal is used to indicate when the
calculator is performing an operation. It is useful in
testing of the device or if interfacing with other logic.
Another feature that is important in testing is the
capability of reducing the key debounce time from seven
word times to four word times by forcing the Digit 7
output high during Digit 9 time.
The MM5780 educational calculator was designed to be
a mathematical aid to school age children. Problems are
entered into the machine in algebraic form exactly as
they are written across a printed page. The student
provides the answer or missing factor and when finished,
depresses the Test key. "Right" and "Wrong" outputs
provide an indication of the results of the test. If wron~,
the student trys the problem again. If correct, he can
move on to the ne?N-:N>:N>:N>:-,
~
Nr-..... ~
9
.....
08
01
06
05
04
03
01
01
~
"
~.....
r--o-......
~.......
r--&-.......
i'O-..... ~
"-
~, ~,
I
~..... ~...
,
~
~,
ft
1
"
"
FIGURE 1. Complete Calculator Schematic
OUTPUT FROM
DIGIT DRIVER
Dl
r-1----------WDRDTIME------------11
-9V~
D2
DJ
I-DIGITTIME
_:~~~------------------------------------~~
OV
L
L-J
-9V
D9
~
OVl-J
DV
-9V
DECIMAL PDINT
SEGMENTS
S.
Sb
Sc
Sd
S.
S'-+__+_-'f-_-f-I
.
Sg.....;._ _...:.J
ACTUAL DISPLAY:
SEGMENT
DESIGNATlDN
D9-·I---------~-Dl
,[T/b
'/~/C
d
FIGURE 2. Display Timing
MMS791
{
---u
u
0
u
CP
02~
U
U
03
04
058874
OS
06
07
08.J
09U
U
U-
U
U
U
U
U
U
U
U
U
U
U
LI
Lr
L
FIGURE 3. Digit Timing
OPERATION IN THE ADD AND SUBTRACT MODE
If the terminate flag is set, an "=" key will result in a
constant add/subtract. The number in the accumulator
will be added to (or subtracted from) the number being
displayed. The result is right·justified and displayed in
the entry register. Accumulator and mode registers are
not altered, allowing for constant operations.
If the terminate flag is not set, and a number has not
been entered from the keyboard, or memory, a "+,"
"-," "x" "..;." key will only change the mode register
to the new key entry.
If the terminate flag is not set, an "=" key will add/
subtract the number being displayed to/from the number
in the accumulator register. The number being displayed
is transferred to the accumulator, and the result of the
operation is displayed in the entry register. The terminate
flag is set, conditioning the calculator for constant,
add/subtract operation. ·The number being displayed
previous to the "=" key is stored in the accumulator as
the constant.
If the terminate flag is not set and a number has been
entered from the keyboard, or memory register, a "+,"
"-," "x" or "..;." key will result in an addition or
subtraction. The entry register will be added to or sub·
tracted from the accumulator and the new running total
will be displayed in the entry register and copied into
the accumulator register. The mode will be altered
according to which key is entered.
8·99
Operation of the "%" key in add/subtract mode, with
the terminate flag reset, will multiply the accumulator
by the last entry, divide the result by 100, and display it
in the entry register. The mode register remains as it was
in the add or subtract mode. All of the above is required
to perform the percent add on or discount problems.
Depression of an "=" key after the "%" key will either
tax or discount the orig'inal number as a function of the
mode register and the last entry.
Operation of the "%" key in add/subtract mode, with
the' terminate flag set, will shiftthe decimal point of the
number being displayed two places to the left and copy
it into the accumulator register. The mode is set to
multiply and the terminate flag remains set.
If the terminate flag is not set, a "+ ," "-," "x". or "-,;-"
key will result in a division. The number in the accumulator register will be divided by the number being
displayed. The results are displayed in the entry register,
and a copy of the result is stored in the accumulator.
The mode register is modified to reflect the latest key,
entry.
Operation of the "%" key while in divide mode looks
exactly the same as the "=>." key except the decimal
point of the display is shifted two positions to the left
befo,re division takes place.
OPERATION IN THE MULTIPLY MODE
,H
played. The terminate flag is set and the divisor is stored
in the accumulator register.
ERROR CONDITIONS
If the terminate flag is set, an "=" key will result in a
constant multiply operation. The number being displayed
is multiplied by the constant stored in the accumulator
register. The result is displayed in the entry register and
the accumulator and mode registers are not altered,
allowing for constant operation. Repeated depressions
of the "=" key can be used to raise a number to an
integer power, i.e., "C," "C," "5.2," "x," "-" "-"
"=," computes 5.24 •
If any of the operations mentioned above generates a
number larger than 9999 9999, an error will occur. An
error is indicated by displaying the eight most significant
digits and sign with all nine decimal points. The first
depression of the"C" key will clear the error condition,
and all registers except the memory register.
It is not possible to generate an error during number entry.
The ninth and subsequent digits entered are ignored.
The constant in multiplication, as well as in addition,
subtraction and division is the last number entered. For
the sequence: "C," "C," "3," "-';-," "4," "x," "2," "-"
the cons~ant multiplier for future problems is 2.
DISPLAY TURNOFF AND LEADING ZERO
SUPPRESSION
In order to conserve battery power, the MM5791 blanks
leading zeros and turns off all but the least significant
digit, decimal point and sign ~fter 25 seconds (typical)
of no activity. Once the display turns off, any key
depression will turn it back on and perform the function
indicated. Two depressions of the "CS" key will turn
on the display with no change to the machine. If Reset
Display is hard-wired to V DO, the display will never
turn off.
If the terminate flag is not set, an "=" key will signal
the end of a problem. The number in the display will be
multiplied by the contents of the accumulator, and the
results willbe displayed in the entry register. The number
previously in the entry register is stored in the accumulator register and the terminate flag is set.
If the terminate flag is not set, and a numbet has been
entered from the keyboard or memory register, a "+,"
"-," "x" or "-,;-" key will result in a multiplication. The
number being displayed will be multiplied by the number residing in the accumulator register. The result will
be copied into the accumulator and displayed in the
entry register. The mode register is up-dated as a tInction of the key depressed.'
':,
POWER-ON CONDITION
The MM5791 has an internal power-on clear circuit
which clears all registers to zero, places the mode to add
and sets the terminate flag. A zero and decim~1 point
are displayed.
Operation of the "%" key while in mUltiply mode looks
exactly the same as an "=" key except the de'Cimal
point of the display is shifted two positions to the left
before the multiplication takes place.
KEYBOARD BOUNCE AND NOISE REJECTION
The MM5791 is designed to interface with most low cost
keyboards, which are often the least desirable from a
false or multiple entry standpoint.
OPERATION IN THE DIVIDE MODE
If the terminate flag is set, an "=" key will result in
constant divide operation. The number being displayed
is divided by the constant stored in the accumulator
register. The accumulator and mode registers are not
altered allowing for constant operations. Repeated depressions of the "=" key will result in repeated divisions
by the constant. Thus, it is possible to raise a number to
a negative integer power using the sequence:, "C," "C,"
"1," "-';-," "No.," "=," "=," etc.
A key closure is sensed by the calculator chip when one
of the key inputs, K 1, K2, K3 or K4 is forced more
negative than the Logical Low Level specified in the
electrical specifications. An internal counter is started
as a result of the closure. The key operation begins after
eleven word times if the Key Input is still at a Logical Low
Level. As long as the key is held down (and the Key
Input remains low) no further entry is allowed. When
the Key Input changes to a Logical High Level, the
internal counter starts an ~Ie~en word timeout for key
release. During both, entry and release time outs, the
Key Inputs are sampled every word time for valid levels.
If they are found invalid, the counter is reset and the
calculator resumes scanning the keyboard.
If the terminate flag is not set, an "=" key will signal
the end ,of a proble'm. The number in the accumulator
register will be divided by the number being displayed.
The result is transferred to the entry register and dis'8-100
READY SIGNAL OPERATIONS
"-;." and "%" keys and the examples given in later
sections will aid in further explaining these actions.
The Ready signal indicates calculator status. When the
calculator is in an "idle" state, the output is at a Logical
High Level (near Vss ). When a key is closed, the internal
key entry timer is started. Ready remains high until the
timeout is completed and the key entry is accepted as
valid, then goes low. as indicated in Figures 5 and 6.
It remains at a Logical Low Level until the function
initiated by the key is completed and the key is released.
The low to high transition indicates the calculator has
returned to an idle state and a new key can be entered.
Clear Key, "CE/C"
While in the number entry condition, one depression
will clear the entry register to zero and recall.'-'\
accumulator for display. The machine then leaves_',
number entry state.
." ,;.
If the error condition is displayed, one depression will
clear the error, and all registers except the memory
register. The machine could not be in the number entry
condition with the error flag set.
TEST FEATURES
Several features have been designed into the MM5791
to facilitate testing. One is to allow the key debounce
timing to be modified, and the second performs a
"segment test" function which turns on all segments for
all digit times, with no interdigit blanking. The key
bounce time can be reduced from eleven word times to
one if a key closure is made between D9 and K2.
Similarly the "Segment Test" occurs when a key closure
is made between D9 and K3. Closures for test operations
are not debounced, and also may occur simultaneously
with normal key closures if diodes are used to isolate
the D-Lines from each other. The test features are active
for every word time the Test switch closure is maintained. These test matrix entries are isolated internally
from the normal calculator keys, allowing simultaneous
entry of "test" keys and "calculator" keys.
If the error flag is not set and the machine is not in the
number entry condition, one depression of "CE/C" key
will clear the entry and accumulator registers. It also
places the machine in the add mode and sets the terminate flag. The memory register remains unchanged.
Number Keys 0-9
If not in the number entry condition, a number key will
clear the display and then enter the value of the key
into the LSD. The digits are displayed as they are entered
and the machine assumes the number entry condition. .
If in the number entry condition, the entry register is
shifted left one position and the key depressed is entered
into the LSD. If there,is a number in the most significant
digit position (9th) the entry register is then shifted
right one position and the. entry is lost.
FUNCTION OF KEYS
Some of the keys operate differently when in the data
or number entry condition. The MM5791 switches to
entry condition when entering numbers and leaves this
condition after most function keys. The following paragraphs discuss each of the keys on a full keyboard and
the action taken when they are depressed. The earlier
paragraphs which discussed the action of "+," "-," "x,"
~ !J:
The square root key extracts the square root' of the
absolute value of the number being displayed in the
entry register.
:L.J~~I-------
-+--------jl"'"
READY -.
(KEYE::::~
"V"
ELEV~~~I~~~~~~SSIVE ~
D9LJ
INPUT K·lINE
Square Root Key,
tpd
-
t I-i- - - - - - -
(KEY RELEASE}--J
tpel::: 5ps (TVPICAl)
t :::
tol;IT
+ Ipd.
tpd:::
5ps(tvp)
FIGURE 5. Ready Timing
NEW KEY
IS DEPRESSED
j
KEY IS
RELEASED
I
~~
j~1
I
ANy---r--nr
11 WORDS
INPUT
11 WORDS
'''NOISE'
"NOISE"/
•
READY
J
I
5J
::~EE:S~~~
CALCULATION
IS COMPLETED.
WHICHEVER IS
LONGER.
~
I
•
~
NE~~~~~t~LBAEi;RA~~~P::~J
NEX~ KEY CANJ
MAY BE RELEASED.
BE ENTERED
FIGURE 6. Functional Description of Ready Signal and Key Entry
,8·i01
.
The mode of the calculator remains unchanged. This
enables square root operations in the middle of chain
calculations. For example:
While in multiply or divide mode, this key'shifts the
displayed decimal point two places to the left, completes
the multiplication, or division and sets the
. terminate flag.
KEY DISPLAY
I n add or subtract mode, this key shifts the displayed
decimal point two places to the left, multiplies the
display times the accumulating register, places the product in the entry register and leaves the accumulator
register and mode register undisturbed. This permits
automatic calculation of net by depression of the "="
key. The t~rminate flag is not altered.
A
KEY DISPLAY
KEY DISPLAY
..r
A
A
A
11
11
VA
X
A
+
11.
+
VA
B
B
5
B
B
..r
..r
vB
= VA+vB
vB
AvB
5
16.
..r
6
4.
6.
J1
9
..r
SAMPLE PROBLEMS
9
3.
8.
Square
Depression of the "Square" key copies the number being
displayed into the accumulator register, and performs a
multiplication. On completion of the square operation,
the results are displayed in the entry register, the original
number is stored in the accumulator and the mode of the
calculator is unchanged. Entering a number to start a
new entry will first clear the entry register.
1. Simple addition or subtraction
KEYS
C
3
0
3
+
2
+
3.
2
5.
5.
4.355
Memory Plus Key, "M+"
When the "M+" key is depressed, the number being
displayed is added to the contents of the memory and
the results, providing there is no overflow, are placed in
the memory. The calculator will be out of the data
entry mode.
If an overflow occurs, the contents of the m'emory are
COMMENTS
DISPLAY
+
3.25
CS
4
+
4.355
0.645
0.645
3.25
-3.25
-3.254
-2.609
not altered. The display shows the eight most significant
digits and sign of the results with all nine decimal points.
1
-1.609
Memory Minus Key, "M-"
This key operates like the "M+" key only the displayed
number is subtracted from memory.
Plus, Minus, Multiply and Divide Keys, "+," "-," "x," "-;.-"
These keys terminate a number entry, complete the
operation designated by the mode register and update
the mode register for the next operation. A more detailed
explanation of these keys is found in the description
of modes.
Equal Key, "="
Completes addition,
sets add mode
Sets subtraction
mode
Completes subtraction. Sets mode terminal
Sets mode terminal.
Sets add mode,resets
Starts Digit Entry
Changes Sign
Continues Digit Entry
Completes signed
addition, sets add
mode
Completes signed
addition, sets terminate mode
2. Constant addition or subtraction (second factor
constant)
KEYS
3
2
+
This key terminates a number entry, complete the
operation designated by the mode register and sets the
terminate flag.
6
Percent Key, "%"
.5
Following a clear·all operation or a number entry
proceeded by a clear all operation, this key shifts the
decimal point of the number being displayed two places
to the left, copies it into the accumulating register and
establishes the multiply mode.
Start addition problem
Sets add mode
7
DISPLAY
COMMENTS
3
3.
2
1.
6
,7.
.5
6.5
7
7.
Sets subtract mode
Completes subtraction, sets Add mode
Completes addition,
saves (6) as constant,
sets terminate mode
. Completes constant
addition constant=6
Sets subtraction
mode, resets terminate mode
2. Constant addition or subtraction (second factor
~
~
5. Constant multiplication (continued)
constant) (continued)
KEYS
KEYS
DISPLAY
DISPLAY
COMMENTS
6
3
3
4.
8
3.
8
EX
-5.
9
1.
9
Completes subtrac·
tion, sets terminate
mode, saves 3 as a
constant
DISPLAY
6
24.
3
Exchanges entry, and
constant
Completes subtraction constant = .8
3
3.
4.5
-1.5
4.5
X
8
Completes subtraction constant = 8
3. Simple multiplication
KEYS
COMMENTS
CS
8
-8
1 2.
EX
-8.
CS
8.
3
36;
3
3.1
3.1
3.1
6
18.6
X
6
Start mUltiplication
problem
Sets multiply mode
432.
Completes multiplication, sets terminate
mode
3
X
3
3.
+
3.
X
3.
3.
9.
4. Chain multiplication
KEYS
DISPLAY
+
4
X
6
2
COMMENTS
3
3
4
7.
3
6
42.
2
4 O.
Sets add mode
KEYS
4
Completes subtraction, sets terminate
mode, saves 2 as
constant
3
CS
3
X
4
DISPLAy
3
3.
4
.1 2.
Completes subtraction, sets multiply
mode
Changes sign
Completes multiplication '-8' as constant, sets termination mode
Exchanges entry
register, and constant
Completes constant
multiplication
constant = 12
Completes constant
multiplication
constant = 12
Sets multiply mode,
resets termination
mode
Sets add mode.
Second function key
only modifies mode
Sets subtract mode
Sets multiply mode
Completes multiplication. Sets termination mode
£II
DISPLAY
COMMENTS
4
4.
3
-3
-1.3333333
7. Chain division
KEYS
COMMENTS
3
Sets multiply mode'
8
+
Completes multiplication, saves '4' as
constant, sets termination mode
"f
2
X
3.1
8:103
...
Sets subtract mode,
resets termination
6. Simple division
Completes multiplication, sets subtract
mode
CJ1
"oJ
CD
Completes constant
multiplication,
constant = 4
Completes addition,
sets multiply mode
5. Constant multipl ication
KEYS
COMMENTS
DISPLAY
3
3.
8
0.375
2
2.375
3.1
COMMENTS
'l"""
0')
I""'LO
~
~
7. Chain division (continued)
KEYS
6
10. Percent in multiplication and division (continued)
DISPLAY
KEYS
COMMENTS
500
7.3625
6
1.2270 833
4
%
8. Constant division
KEYS
6
2
15
2
X
8.3
3
CS
EX
EX
CS
EX
608.7
695.99
20
%
+
6
%
17.95
15
%
+
6
%
COMMENTS
KEYS
6
6.
2
3.
1.5
15
1 5.
2
13.
8.3
107.9
3
-3
107.9
-.0 2 7 8 a 3 5 2
107.9
-107.9
-.0 2 7 8 a 352
6 a 8.7
-5.641 3345
308
X
5
%
500
5 00.
4
1 25 a O.
DISPLAY
COMMENTS
COMMENTS
6
M+
6
6.
3
+
2
M-
3
3.
2
2.
5.
4.
3.678
-3.678
-3.678
-3.678
5
5.
-18.39
-4.678
5
5.
3
3.
4
1 2.
5.
6 O.
MR
5
MS
3
X
4
X
MR
a
695.99
695.99
20
1 39.1 98
556.792
556.792
6
33.4 0752
590.19952
1 7.95
1 7.95
15
2.6925
1 5.2575
6
0.91 545
16.17295
DISPLAY
DISPLAY
MR
3.678
CS
M+
X
5
M-
Memory indicator
is activated
a
MS
O.
Memory indicator
turned off when
contents equal zero
12. Square root problems
KEYS
3
...r
+
4
...r
7
+
8
...r
10. Percent in mUltiplication and division
KEYS
COMMENTS
11. Memory operations
DISPLAY
9. Add on and discount problems
KEYS
DISPLAY
DISPLAY
COMMENTS
3
1.7320 5 a 8
1.7320 5 08
4
2.
3.7320 5 08
7
7.
8
1 5 ..
3.8729833
13. Square problems
COMMENTS
308
308.
5
1 5.4
KEYS
72
X2
8-104
DISPLAY
72
51 84.
COMMENTS
Calculators
MM5794 seven-function, accumulating memory,
vacuum fluorescent display calculator
genera I description
features
The single-chip MM5794 offers a seven-function,
accumulating memory MOS/LSI calculator device
capable of directly driving 8-digit vacuum-fluorescent
displays_ A complete calculator as shown in Figure '1
requires only the MM5794, a keyboard, vacuum
fluorescent display and an appropriate power supply.
•
Full 8-digit capacity
•
7-functions (+, -, x, 7,
•
Convenient algebraic notation
Keyboard decoding and key debounce circuitry, all
clocks and timing generation, power-on clear and 7segment output display decoding are included on-chip
and require no external components. Segments and
digits can be driven directly from the MM5794. The
left-most, or 9th digit is used to indicate memory in use
or the negative sign of an eight digit number.
Leading zero suppression and a floating negative sign
allow convenient reading of the display and conserves
power. Typical current drain of a complete calculator
displaying five "5's" is 30 mA.
connection diagram
X2,..;x,
%)
•
Fully protected accumulating memory (M+, M-)
•
Automatic constant independent of memory
•
Floa,ting decimal input and output format
•
Power-on clear*
•
On-chip'oscillator*
•
Low system cost
•
Direct segment and digit drive of fluorescent displays
•
Memory in-use indicator
*Requires no external components.
keyboard outline
Dual-I n-Line Package
DIGIT 4--2.
24
r-DIGIT J
DIGIT 5.2.
~DIGIT2
~vGG
, DIGIT 6..2.
DIGIT 7...!
r!!- Kl
DIGIT 8..l.
20
-K2
DIGIT 9...2.
\
DIGIT 1..2..
Voo -
..!..!!....K4
8
.!2.. SEGMENT F
.!!..SEGMENT B
c.2.!!..
.!!..SEGMENT G
SEGMENT A....!.!.
1!..SEGMENT 0
VssJ!.
..!l..SEGMENTE·
SEGMENT
0G8800
DGJGJGD
[JuuE)B
.!!.KJ
.J!..
SEGMENT D,P •
Typical Keyboard
\,.
TOP VIEW
\
Order Number MM5794N
See Package 22
8-105
DLJDD[J
B8DDD
BI
absolute maximum ratings
operating conditions
Yoltage at Any Pin Relative to
V ss Except V GG (All Other
Pins Connected to V ss )
Vss + 0.3V to Vss -12V
Voltage at VGG Relative
to Vss
Vss + 0.3V to Vss' - 35V
Ambient Operating Temperature
O°C to +70°C
Ambient Storage Temperature
-55°C to +150°C
Lead Temperature (Soldering, 10 seconds)
300°C
6.5'::; Vss - V DD .::; 9.BV
V ss - V GG .::; 32V
dc electrical characteristics
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
15
mA
Operating Supply Current
I DO
VO~ = Vss - 9.5V, T A = 25°C
8
IGG
VGG = Vss - 32V
500
f.1A
Keyboard Scan Input Levels
(Kl-K4)
Logical High Level (V IH)
Vss
V
Logical Low Level (V 1L )
Vss-22
V
Source Current, (Segments)
T A =25°C
V OUT = Vss -4V, V DO = Vss -6.5V
V OUT = Vss - 35V
10H
10L
-0.6
mA
10
f.1A
Digit Outputs
Logical High Level
VGG = Vss - 32V, V OUT = Vss - 5.0V
-3.5
mA
-2.2
mA
Logical Low Level
VGG = V ss - 25V, V OUT = Vss - 5.0V
Voo = Vss - 9.5V, V OUT = VGG = Vss - 35V
10
f.1A
ac electrical ch a racte ristics
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Word Time.
(Figure 2)
0.53
3.3
ms
Digit Time
(Figure 2)
58
367
f.1s
I nterdigit Blanking Time
(Figure 2)
. 14.5
J.1s
20
(Segment and Digit Outputs)
Digit Transition Times
1100k R";,,o"o V
GO
High to Low
Voo = Vss -6.5V
Low to High
C LOAO = 100 pF
Ready Transition Times
High to Low
Low to High
Keyboard Scan Inputs Transition Times
High to Low (After Key Release)
Low to High (After Key Release)
f.1s
20
r
4
f.1s
Vo~ = Vss -6.5
5
20
f.1s
Ci..OAO = 50 pF
2.0
4.0
f.1s
GG
= V" - 35
CLOAD =50 pF
100
f.1s
C LOAO = 100 pF
4
f.1s
39.6
ms
200
word times
Key Bounce·Out Stability Time
6.36
(The time a keyboard scan input must be continuously lower than the maximum logical low
level to be accepted as a key c,losure, or higher than
the minimum logical high level to be accepted as a
key release.)
Worst Case Calculation Time
8-106
FUNCTIONAL
D~SCRIPTION
The MM5794 is a calculator chip which contains four
data registers: (1) entry, (2) accumulator, (3) working and
(4) memory, each consisting of 8 digits, sign, and decimal
point. The entry register is always displayed. It contains
digit entries from the keyboard, and results of all func·
tions except M+ and M-. The accumulator is used in all
arithmetic functions and stores a copy of the entry
register on all results. This allows anot~er number to be
entered without losing an intermediate result. Multiply
and divide require three registers to perform the function
and save the divisor, or multiplier. The working register
is provided to perform these functions in conjunction
with the entry and accumulator registers.
The memory regi~ter is used only to store a number to be
used later. It is fully protected during all operations, and
is only modified by depressing a "MS," "M+," or "M-"
key. Power on clears all of the registers including the
memory register.
8X200k
A·A·
"10"'"
A
T
A
T I
J
KI
K2
K3
~
lOOk
"
lOOk
.
lOOk
lOOk
.AA
.
..
lOOk
.AA
lOOk
.AA
"
. ..,
lOOk
"'o!-
....
~
.....
i"o1-......
i'o!-
'9
......
~
~......
~
......
~
4~
.......
~
......
~
~E ~
.......
'--
~......
.
lOOk
"
--
Ef
FLUORESCENT DISPLAY
0-
Vss 09 08 07 06 05 04 03 02 01
OIt 02 03 04 05 06 07 08 09
1
I
......
......
........
'-
~
M-
~
~,
...........
.'-
......
'.jX
7
lOOk
SoP SA SB Sc So SE SF SG
0-
I--
......
r...o-:- "'o-i
'o..!.
VGG SG SF SE So Sc SB SA soP
Voo
MM5794
" ...
." ...
I
-""-
~
.......
T I
.1
...,.
A"
......
......
......
-9V
--.!oEf
"OFF/ON"
~o-
-VGG 2 Vss - 32V'
Voo =VSS - 6.5V TO VSS - 9.5V
-r-
--
OCTO OC
CONVERTER
"I
:f,."
30V
*Vss - VOO must be as specified in this data sheet (6.5-9.5) but VSS - VGG, Ef and Vz are determined by the fluorescent display specifications.
t 01 is the right·most display digit, also see Figure 2.
FIGURE 1. Complete Calculator Schematic
8·107
The MM5794 performs the "+," "-," "x" and "-.;-"
functions using algebraic notation. This requ ires the use
of a mode register and a terminate flag. The mode
register directs the machine to the proper function (add,
subtract, multiply or divide) with each new key entry.
After the function has been performed, the key entered
is used to modify the mode register.
, If the terminate flag is set, a "+ ," "-.:' "x" or "-.;-" key
signals the beginning of a new problem. The number
being displayed is copied into the accumulator register
and the mode register assumes the mode of the key
entered. The terminate flag is always reset by the "+,"
"-," "x" and "-.;-" keys.
The terminate flag is set on "=" and sometimes on "%"
and "C/CE." This signifies the end of the problem.
The MM5794 allo",:,s for full floating entries and results.
Vss _ 5 ________
0 - - - - - - - - - - -___ WORD TIME -------------r--
f-ol
DIGIT 1
Vss - 35 - DIGIT 2
DIGIT 3
DIGIT 3
DIGIT4
DIGIT4
DIGIT 5
DIGIT 5
DIGIT 6
DIGIT 6
DIGIT 7
DIGIT 7
DIGIT 8
--------+-----~----~----_+----~------r_----+_----~
~----~----------
DIGIT9
DIGIT 8
DIGIT 9
- - - - - - - - - - . VSS-4
SEGMENT D.P.
--------+------!
~----~------+_-----r----~------+_----~----~------~---VSS-35
SEGMENT A ________+_-----!
SEGMENT B ________-!
SEGMENT C
----f
SEGMENT D
SEGMENT E
--------+-----~
SEGMENT F
SEGMENT G
a
ACTUAL DISPLAY:
SEGMENT
DESIGNATION
D9-·.----------~--~---Dl
IT/b
el Je. SEG
f
d
FIGURE 2. Display Timing·
8·108
D.P.
OPERATION IN THE ADD AND SUBTRACT MODE
If the terminate flag is set. an "=" key will result in a
constant add/subtract. The number in the accumulator
will be added to (or subtracted from) the number being
displayed. The result is right·justified and displayed in
the entry register. Accumulator and mode registers are
not altered. allowing for constant operations.
If the terminate flag is not set. an "=" key will signal
the end of a problem. The number in the display will be
multiplied by the contents of the accumulator. and the
results will be displayed in the entry register. The number
previously in the entry register is stored in the accumulator register and the terminate flag is set.
If the terminate flag is not set and a number has been
entered from the keyboard. or memory register. a "+."
"-." "x" or "..,." key will result in an addition or
subtraction. The entry register will be added to or subtracted from the accuml,llator and the new runring total
will be displayed in the entry register and copied into
the accumulator register. The mode will be altered
according to which key is entered.
If the terminate flag is not set, and a number. has been
entered from the keyboard or memory register, a "+,"
"-," "x" or "..,." key will result in a multiplication. The
number being displayed will be multiplied by the number residing in the accumulator register. The result will
be' copied into the accumulator and displayed in the
entry register. The mode register is up-dated as a function of the key depressed.
If the terminate flag is not set. and a number has not
been entered from the keyboard. or memory. a "+."
"-." "x" "..,." key will only'change the mode register
to the new key entry.
Operation of the "%" key while in multiply mode looks
exactly the same as an "=" key except the decimal
point of the display is shifted two positions to the left
before the multiplication takes place.
If the terminate flag is not set. an "=" key will add/
subtract the number being displayed to/from the number
in the accumulator register. The number being displayed
is transferred" to the accumulator. and the result of the
operation is displayed in the entry register. The terminate
flag is set. conditioning the calculator for constant.
add/subtract operation. The n'umber being displayed
previous to the "=" key is stored in the accumulator as
the constant.
.
OPERATION IN THE DIVIDE MODE
Operation of the "%" key in add/subtract mode. with
the terminate flag reset. will multiply the accumulator
by the last entry. divide the result by 100. and display it
in the entry register. The mode register remains as it was
in the add or subtract mode. All of the above is required
to perform the percent add on or discount problems.
Depression of an "=" key after the "%" key will either;
tax or discount the original number as a function of the
mode register and the last entry.
If the terminate flag is set. an "=" key will result in
constant divide operation. The number b.eing displayed
is divided by the constant stored in the accumulator
register. The accumulator and mode registers are not
altered allowing for constant operations. Repeated de, pressions of the "=" key will result in repeated divisions
by the constant. Thus, it is p~)SSible to raise a number to
a negative integer power using the sequence: "C/CE,"
"C/CE," ",1," """." "No.," "=," "=," etc.
If the terminate flag is not set. an "=" key will signal
the end of a problem. The number in the accumulator
register will be divided by the number being displayed.
The result is transferred to the entry register and displayed. The terminate flag is set and the divisor is stored
in the accu mulator register.
If the terminate flag is not set, a "+," "-," "x" or "..,."
key will result in a division. The number in the accumulator register 'will be divided by the number being
displayed. The results are displayed in the entry register,
and a copy of the result is stored in the accumulator.
The mode register is modified to reflect the latest key
entry.
Operation of the "%" key in add/subtract mode. with
the terminate flag set. will shift the decimal point of the
number being displayed two places to the left and copy
it into the accumulator register. The mode is set to
multiply and the terminate flag remains set.
OPERATION IN THE MULTIPLY MODE
Operation of the .. %rt:, key while in divide mode looks
exactly the same as the "=" key except the decimal
point of the display is shifted two positions to the left
befQre division takes place.
If the terminate flag is set. an "=" key will result in a
constant multiply operation. The number being displayed
is multi'plied by the constant stored in the accumulator
register. The result is displayed in the entry register and
the accumulator and mode registers are ,not altered.
allowing for constant operation. Repeated depressions
of the "=" key can be used'to raise a number to an
integer power. i.e .• "C/CE." '·C/CE." "5.2." .. x ... • "=."
"=," "=;' computes 5.24.
ERROR CONDITIONS
If any of the operations mentioned above generates a ,
number larger than 9999 9999, an error will occur. An
error is indicated by displaying the eight most significant
digits and sign with all nine decimal points. The first
depression of the "C/CE" key will clear the error condition. and all registers except the memory register.
The constant in multiplication, as well as in addition.
subtraction and division is the last number entered. For
the sequence' "C/CE .. "C/CE .. "3 ......!.. . . . .4 ""x ""2 "
"=" the cons~ant mul~iplier fo; futu;e p;~ble~s is 2'.
'
,
8-109
It is not possible to generate an error during number entry.
The ninth and subsequent digits entered are ignored.
'
If the error condition is displayed, one depression will .
Clear the error, and all registers except the memory
register. The machine could not be in the number entry
condition with the error flag set.
POWER-ON CONDITION
The MM5794 has an internal power-on clear circuit
which clears all registers to zero, places the mode to add
and sets the terminate flag. A zero and decimal point
are displayed.
If the error flag is not set and the machine is not in the
number entry condition, one depression of "CE/C" key
will clear the entry and accumulator. registers. It also
places the machine in the add mode and sets the terminate flag. The memory register remains unchanged.
KEYBOARD BOUNCE AND NOISE REJECTION
Number Keys O-g
The MM5794 is designed to interface with most low cost
keyboards, which are often the least desirable from a
false or multiple entry standpoint.
If not in the number entry condition, a number key will
clear the display and then enter the value of the key
into the LSD. The digits are displayed as they are entered
and the machine assumes the number entry condition.
A key closure is sensed by the calculator chip when one
of the key inputs, Kl, K2, K3 or K4 is forced more
positive than the Logical High Level specified in the
electrical specifications. An internal ,counter is started
as a result of the closure. The key operation begins after
eleven word times if the Key Input is still at a Logical
High Level. As long as the key is held down (and the
Key Input remains high) no further entry is allowed.
When the Key Input changes to a Logical Low Level, the
internal counter starts an eleven word timeout 'for key
release. During both, entry and release timeouts, the
Key Inputs are sampled every word time for valid levels.
If they are found invalid, the counter is reset and the
calculator resumes scanning the keyboard.'
If in the number entry condition, the entry register is
shifted left one position and the key depressed is entered
into the LSD. If there is anumber in the most significant
digit position (9th) the' entry register is then shifted
right one position and the entry is lost.
Square Root Key,
The mode of the calculator remains unchanged. This
enables square root operations in the middle of chain
calculations. For example:
I
TEST FEATURES
Several features have been designed into the MM5794
to facilitate testing. One is to allow the key debounce
timing to be modified, and the second performs a
"segment test" function which turns on all segments for
all digit times, with no interdigit blanking. The key
bounce time can be reduced from eleven word times to
one if a key closure is made between 09 and K2.
"Segment Te~t" occurs when K3 is connected to '09.
Closures for test operations are not debounced, and also
may occur simultaneously with normal key closures' if
diodes are used to isolate the 0- Lines from each other.
The test features are active for every word time the
Test switch closure is maintained. These test matrix
entries are isolated internally from the normal calculator
keys, allowing simultaneous entry of "test" keys and
"calculator" keys, except for K3 keys during "Segment
Test."
KEY DISPLAY
A
A
+
VA
VA
B
B
..r
..r
=
KEY DISPLAY
A
X,
B
..r
11
A
+
B
5
v'B
Av'B
v'B
KEY DISPLAY
A
..r
6
.JA+v'B
11
11.
5
16.
9
..r
4.
6.
11
9
3.
8.
Square Key, "X 2 "
FUNCTION OF KEYS
Some of the keys operate differently when in the data
or number entry condition. The MM5794 switches to
entry condition when entering numbers and leaves this
condition after most function keys. The following paragraphs discuss each of the keys on a full keyboard and
the action taken when they are depressed. The earl ier
paragraphs which discussed the action of "+," "-:: "x,"
"r"
The square fOot key extracts the square root of the
absolute value of the numl?er being displayed in the
entry register.
•
Depression of the "Square" key copies the number being
displayed into the accumulator register, and performs a
multiplication. On completion of the square operation,
the results are displayed in the entry register,the original
number is stored in the accumulator and the mode of the
calculator is unchanged. Entering a number to start a
new entry will first clear the entry register.
Memory Save Key, "MS"
"+" and "%" keys .and the examples given in later
sections,will aid in further explaining these actions.
The "MS" key transfers the number being displayed to
the memory register. The display remains unaltered.
Clear Key, "CE/C"
Memory Recall Key,
While in the number entry condition, one, depression
will clear the entry register to zero and recall the
accumulator for display. The machine then, leaves the
number entry state.
8·110
'~MR"
The "MR" key recalls the number being stored in the
memory register and displays it in the entry register.
This number can then be used as a new number entry.
Memory Store Key, "MS"
1. Simple addition or subtraction (continued)
The "MS" key transfers the number being displayed in
the entry register to the memory register. The arithmetic
status of the calculator is not changed.
KEYS
+
2
+
COMMENTS
DISPLAY
3.
2
5.
Memory Plus Key, "M+"
5.
When the "M+" key is depressed, the number being
displayed is added to the contents of the memory and
the results, providing there is no overflow, are placed in
the memory. The calculator will be out of the data
entry mode.
If an overflow occurs, the contents of the memory are
not altered. The display shows the eight most significant
digits and sign of the results with all nine decimal points.
4.355
+
3.25
CS
4
+
4.355
0.645
0.645
3.25
-3.25
-3.2 54
-2.609
Memory Minus Key, "M-"
1
-1.609
This key operates like the "M+" key only the displayed
number is subtracted from memory.
Sets add mode
~
~
(J'1
-..J
(D
~
Completes addition,
resets add mode
Sets subtraction
mode
Completes subtraction: Sets terminate
mode.
Sets add mode
Starts Digit Entry
Changes Sign
Continues Digit Entry
Completes signed
addition, sets add
mode
Completes signed
addition, sets terminate mode
Plus, Minus, Multiply and Divide Keys, "+," "-," "x," "-;-"
These keys terminate a number entry, complete the
operation designated by the mode register and update
the mode register for the next operation. A more detailed
explanation of these keys is found in the description
of modes.
2. Constant addition or subtraction (second factor
constant)
KEYS
3
COMMENTS
DISPLAY
3
3.
2
2
+
Equal Key, "="
This key terminates a number entry, complete the
operation designated by the mode register and sets the
terminate flag.
Percent Key, "%"
1.
6
.5
6.5
.5
In add or subtract mode, this key shifts the displayed
decimal point two places to the left, mUltiplies the
display times the accumulating register, places the product in the entry register and leaves the accumulator
register and mode register undisturbed. This permits
automatic calculation of net by depression of the "="
key. The terminate flag is not altered.
Completes subtraction, sets add mode
6
7.
Following a clear-all operation or a number entry
proceeded by a clear all operation, this key shifts the
decimal point of the number being displayed two places
to the left, copies it into the accumulating register and
establishes the multiply mode.
While in multiply or divide mode, this key shifts the
displayed decimal point two places to the left, completes
the multiplication or division and sets the terminate flag.
Sets subtract mode
7
7.
3
3
4.
8
3.
8
EX
-5.
9
1.
9
Completes addition,
saves (6) as constant,
sets terminate mode
Completes constant
addition constant=6
Sets subtraction
mode, resets terminate mode
Completes subtraction, sets terminate
mode, saves 3 as a
constant
Exchanges entry, and
constant
Completes subtraction constant = .8
Completes subtraction constant = 8
SAMPLE PROBLEMS
1. Simple addition or subtraction
KEYS
CICE
3
DISPLAY
o
3
3. SilT)ple multiplication
COMMENTS
KEYS
3.1
Start addition problem
8-111
DISPLAY
3.1
COMMENTS
Start multiplication
problem
~
3. Simple multiplication (continued)
KEYS
DISPLAY
X
6
5. Constant multiplication (continued)
KEYS
COMMENTS
3.1
6
1 8.6
DISPLAY
Sets multiply mode
432.
Completes multipli·
cati on, sets ter,m inate
mode
3
X
3
3.
+
3.
X
3.
3.
9.
4. Chain multiplication
KEYS
DISPLAY
COMMENTS
3
+
3
3
4
4
7.
X
6
2
6
42.
2
4 O.
Sets add mode
6. Simple division
Completes multipli·
cation, sets subtract
mode
KEYS
Completes subtrac·
tion, sets terminate
mode, saves 2 as
constant
DISPLAY
3
3.
4
4
1 2.
8
CS
4
4.
3
COMMENTS
3
-3
-1.3333333
KEYS
3
Sets multiply mode
8
Completes multipli·
cation, saves '4' as
constant, sets termin:
ation mode
+
Completes constant
multiplication,
constant = 4
6
2
X
3.1
6
24.
4.5
X
4
-;CS
COMMENTS
X
3
DISPLAY
7. Chain division
3
6
Completes constant
m~ltiplication
constant = 12
Sets multiply mode,
resets termination
mode
Sets add mode.
. Second function key
only modifies mode
Sets subtract mode
Sets multiply mode
Completes multipli·
cation. Sets termina·
tion mode
Completes addition,
sets multiply mode
5. Constant multiplication
KEYS
COMMENTS
3
3.
4.5
-1.5
Sets subtract mode,
resets termination
-8
EX
':"8.
CS
3
8.
3
36.
COMMENTS
3
3.
8
0.375
2
2.375
3.1
7.3625
6
1.2270833
8. Constant division
KEYS
Completes subtrac·
tion, sets multiply
mode
6
8
1 2.
DISPLAY
2
Changes sign
Completes multipli·
cation '-8' as con·
stant, sets termina·
tion mode
Exchanges entry
register, and constant
15
2
X
8.3
Completes constant
multiplication
constant = 12
3
CS
EX
8·112
DISPLAY
6
6.
2
3.
1.5
1 5
1 5.
2
13.
8.3
107.9
3
-3
107.9
COMMENTS
8. Constant division (continued)
~
~
11. Memory operations (continued)
CJ1
KEYS
EX
CS
EX
608.7
DISPLAY
COMMENTS
KEYS
-.02780352
107.9
-107.9
-.02780352
608.7
-5.641 3345
3
+
2
MMR
3.678
CS
M+
9. Add on and discount problems
KEYS
695.99
20
%
+
6
%
17.95
15
%
+
6
%
DISPLAY
X
5
M-
COMMENTS
695.99
695.99
20
1 39.1 98
.556.792
556.792
6
33.4 0 7 5 2
590.19952
1 7.95
1 7.95
15
2.6925
1 5.2575
6
0.91 545
1 6.1 7295
308
X
5
%
500
4
%
DISPLAY
I'
MR
5
MS
3
X
4
X
MR
0
MS
3
3.
2
2.
5.
4.
3.678
-3.678
-3.678
-3.678
5
5.
-1 8.39
-4.678
5
5.
3
3.
4
1 2.
5.
6 O.
0
O.
COMMENTS
~
,Memory indicator
turned off when
contents equal zero
KEYS
3
COMMENTS
V
+
4
308
308.
5
1 5.4
500
500.
4
1 250 O.
V
7
+
8
V
DISPLAY
COMMENTS
3
1.7320508
1.7320508
4
2.
3.7320508
7
7.
8
1 5.
3.8729833
'[II
11. Memory operations
13. Square problems
KEYS
COMMENTS
DISPLAY
KEYS
6
M+
6
6.
"
CD
12. Square root problems
10. Percent in mUltiplication and division
KEYS
DISPLAY
72
Memory indicator
is activated in
left-most digit
X2
8-113
DISPLAY
72
5184.
COMMENTS
Calculators
MM5795 seven-function, accumulating memory,
vacuum fluorescent display calculator circuit
general description
features
The single-chip MM5795 offers a seven-function,
accumulating memory MaS/LSI calculator device
capable of directly driving a-digit vacuum-fluorescent
displays: A complete calculator as shown in Figure 1
requires only the MM5795, a keyboard, vacuum
fluorescent display and an appropriate power supply.
•
Full a-digit capacity
•
7-functions (+, -, x, 7, x 2 ,";;', %)
•
Convenient algebraic notation
•
Fully protected accumulating memory (M+, M-)
•
Automatic constant independent of memory
•
Floating decimal input and output format
Keyboard decoding and key debounce circuitry, all
clocks and timing generation, power-on clear and 7·
segment output display decoding are included on-chip
and require no external components. Segments and
digits can be driven directly from the MM5795. The
left-most, or 9th digit is used to indicate memory in use
or the negative sign of an eight digit number.
Leading zero suppression and a floating negative sign
allow convenient reading of the display and conserves
power. Typical current drain of a complete calculator
displaying five "5's" is 30 mA.
•
Power-on c1ear~
•
On-chip oscillator*
•
Low system cost
•
Direct segment and digit drive of fluorescent displays
•
Memory in-use indicator
"Requires no external components.
connection diagram
,keyboard outline
Dua)-) n-Line Package
24
DIGIT 4
DIGIT 3
23 DIGIT 2
DIGIT 5
Typical Keyboard
DIGIT 6
GBGG00
OD[J[JCJ
CJCJDGEJ
DIGIT 7
DIGIT 8
DIGIT 9
K3
DIGIT 1
[J[][J[JLJ
SEGMENT F
Voo
""I
BCJDDD
'SEGMENT D.P.
SEGMENT A 11
13 SEGMENT E
TOP VIEW
Order Number MM5795N
See Package 22
8-114
~.
absolute maximum ratings
operating conditions
Voltage at Any Pin Relative to
Vss Except V GG (All Other
Pins Connected to V ss )
Vss + 0.3V to Vss -12V
Voltage at V GG Relative
to Vss
Vss + 0.3V to Vss - 35V
Ambient Operating Temperature
O°C to +70°C
Ambient Storage Temperature
-55°C to +150°C
Lead Temperature (Soldering, 10 seconds)
300°C
6.5 ~ Vss - Voo ~ 9.8V
Vss - VGG ~ 32V
dc electrical characteristics
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Supply Current
= Vss
I DO
V DO
IGG
VGG = Vss -32V
- 9.5V, T A
= 25°C
8
15
500
mA
J.1.A
Keyhoard Scan Input Levels
(Kl-K4)
Logical High Level (V IH)
Vss-7.0
Vss
V
Logical Low Level (V IL)
VGG
Vss-22
V
Source Current, (Segments)
T A =25°C
= Vss
10H
V OUT
10L
V OUT = Vss - 35V
- 4V, Voo = Vss - 6.5V
-0.6
mA
10
J.1.A
-3,5
mA
-2.2
mA
10
J.1.A
Digit Outputs
Logical High Level
VGG
= Vss
- 32V, V OUT = Vss - 5.0V
VGG = Vss - 25V, V OUT = V ss .- 5.0V
Logical Low Level
V OD = Vss - 9.5V, V OUT
= VGG
= Vss ..:. 35V
ac electrical characteristics
PARAMETER
CONDITIONS
MIN
TYP
MAX
Word Time
(Figure 2)
0.53
3.3
Digit Time
(Figure 2)
58
367
Interdigit Blanking Time
(Figure 2)
14.5
20
'UNITS
ms
ps
}JS
(Segment and Digit Outputs)
Digit Transition Times
rOOk R"; 9.9999999 X 1099
Results < 1 x 10-99
T
Z
Division by 0
y
LOG, LN 9000
0
0
~===== Y
!::::=====~
x'--_ _ _ _.-J X
:
0
TAN 90 , 270 , etc.
SIN-l, COS-l > 1 or -::; 10- 50
m
VX
<0
More than two open parentheses without
a close
'--_ _ _ _---.J
M
FIGURE 1. User Register Configuration
More close parentheses than open
8~:126
functional description
(Continued)
KEY OPERATIONS
Clear Key "C"
Second Function Key, "F"
a) In RPN mode: Pushes down stack and clears T. Four
"c" depressions will clear a completely full stack
Sets F mode
b) After "F": Clears all registers including the memory
Memory Store/Clear "MS/"MC"
c) In algebraic mode after number key: Copy Y to X
d) In algebraic mode after function key: Clears all
modes and X, Y, Z and T
a) Copy X to memory
Number Keys, "0" - "g", "."
Memory Recall/Exchange Memory "MR/X-M"
a) In RPN mode after any function key except "EN":
Clears X and enters number left justified to X
b) After any number key: Enters next digit into X. All
entries after eighth are ignored
b) After F: (CM) clear memory
a) In RPN mode: Pushes up stack, recall memory to X
b) In algebraic mode: Recall X to M
'c) After F: Exchange X and M
c) After "EE": Enters number to exponent. Last 2
-entries are used
Enter Exponent Key, "EE"
d) After "EN": Clears X and enters number in X
Sets enter exponent mode, displaying 00 in exponent
position.
e) In algebraic mode, after function key: ~Iears X and
enters number
Change Sign Key, "CS"
a) After "EE": Change sign of exponent of X
b) After any other key: Changes sign of X mantissa
Coordinate Conversion Key. "R .... P"
a) Converts contents of X and Y in rectangular coordinates to polar coordinates:
yX2 + y2 to Y
TAN-l YIX to X
b) After "F": (P -+ R): Converts contents of X and Y in
polar coordinates to rectangular coordinates:
Y SIN X -+ Y
(n SIN 0)
Y COS X-+ X (n COS 0)
Square Root/Square Key. "VX/X2"
Stack Rotate Key "ROLL", RPN Only
Rolls stack down
Exchange Key, "X .... V"
Exchanges X and V
Common Log Key, "LOG/l0x "
a) Common logarithm of X to X (base 10)
b) After "F": (lOX) lOx to X
Natural Log Key, "LN/e x "
a) Natural logarithm of X to X (base e)
b) After "F": (eX) eX to X
a) Square root of X to X
b) After "F": (X2) X-squared to X
Trigonometric Keys, "SIN, COS, TAN"
Reciprocal/" 1/x"
a) Replaces the decimal angle in X with the indicated
trigonometric function
b) After F: (SIN-l, COS-l, TAN-') Replaces X with
the decimal angle of the indicated inverse trigonometric function
Reciprocal of X to X
Power Key "yx"
a) In RPN mode: Computes :(x power, pushes down
stack, clears T
The Four Function Keys, "+, -, X, -':-", In RPN Mode
b) In algebraic mode, not in chain mode: Copy X to Y,
set yX chain mode
a) Add key, "+": Y + X -+ X
Subtract key, "-": V - X -+ X
Multiply key, "X": V X X -+ X
Divide key, "-':-"; V/X -+ X
Then push down stack and clear T
O-+T-+Z-+Y
c) In algebraic mode, in chain mode: Perform the specified function of X and Y, putting the result to both
X and Y, set yX chain mode
Enter Key. "EN"
a) Pushes up stack, retains X
b) After F: (CF) resets F mode
b) AfterF:
+: X+MtoM
-: M - X to M
X: M X X to M
-':-: MIX to M
functional description
(Continued)
The Four Function Keys, "+", "-", "X", ".;.,,', In Algebraic Mode
a) If not in chain mode: Copy X to Y, set the specified chain mode
b) After "+, -, X,.;." key: Copy Xto Y, set chain mode
b) In constant mode: Perform the specified function of
X, Y putting the result in X
c) After F: (CF) reset F mode
c) In chain mode: Perform the specified function of X
and Yputting the result to X and Y, set the specified
chain mode
Open Parenthesis, "[ ("
7T
Copy Z to T, copy X to Z; copy Pl mode to P2 mode;
copy the calculator mode to Pl mode, reset calculator
mode
Key, "7T"
a) In RPN mode:
(3.1415927)
Pushes up stack enter IT to
b) In algebraic mode: Enter
7T
x·
Close Parenthesis 0) 1", Algebraic Mode
to X
a) In chain mode: Perform the specified function of X, Y
putting the result to X. Copy Z to Y, copy T to Z,
clear·T2. Copy P2 mode to Pl mode, copy Pl mode
to the calculator mode, reset P2 mode
b) Not in chain mode: Z to Y, T to Z, clear T, Pl mode
to calculator mode, P2 mode to Pl mode, reset P2
mode
Degree to Radian Key, "0 -+ R"
a) Converts' X in degre.es to radians X = Xo/180 x
7T
b) Converts X in radians to degrees X = XO/IT x 180
Equal Key,"="
a) In chain mode: Perform the specified function of
X and Y putting the result to X and·'·save the last
number displayed in Y, set the constant mode
summary
Stack Operations in RPN Mode
(M UNCHANGED)
@]
~LDST
t-.-l
--_'--.T
.T
\~z
z
:
II
:
y~'
,.,y
X
,.,
\
~LDST
X
I +,-,X,+, yx I
•
T
.. Z
.. t
____x : ~
z
'--.T
\~z
y\~y
x~X
SIN COS TAN' SIN-l COS- 1 TAN- 1 CS
,
, X 'X X'
2'
,
LN, LOG, 10 ,e ,1
X ,EE, ->DEG,
->HAD, F
,v.
,., T
.. Z
.. T
.. Z
y
,., Y
·f (x)
.. X
.-----, /
y
x~X
y \
8-128
summary
s
s
(Continued)
(J'1
......
....
Stack Operations in RPN Mode (Continued)
o
eN
~ AFTER FUNCTION
~
t~T
z
Z
y
Y
x
X
KEY O'R
,-LOST
t
~
----1_
z~/
T
.z
--F~
11,1-----'
FIRST
~
ERROR
•
y
AFTER FUNCTION KEY'
~LOST
., T
Z
t
/
., Y
., X
z
-r=~
.,
T
---yx
NUMBER-------J
NUMBER LEFT JUSTIFIED
~AFTER@]
DR
t
.,
T
y
., Z
., Y
NUMBER
• X
~
• Operations Using Memory (s)
.. T
., Z
., Y
y
;
F,X "'M
POWER "ON" or
., T
o
•
., Y
y
x
m _ _.......
ERROR
OVERflOW INTO MEMORY
~
:~
., X
•
., T
T
., Z
., Y
.. Z
:~
\
~LOST
M
y
~
•
Z
.,
Y
\."---- X
m~
-
.,M
'---LOST
8-129
M
0
connection diagram
Example Showing Parentheses Registers and Modes in
Algebraic Mode
or-
f'
I!)
Dual-I n-Line Package
6 X (2(8-5) + 2)
~
~
Y & MODE
X
6
(
2
FYx
6x
6
6
2Yx
2
2
8
8
8
5
)
+
Z
)
28 DO 1
Kl
P2
T& MODE
27
K2
26
K3
6
6
6
2
2
2
X
Pl
Z& MODE
8+
5
3
8
Z
8+
8+
10
60
6x
10x (constant)
8-
2Yx
typical application
25
K4
004
23 SO
SYNC
22
OSC
BLK
21 voo
F3
6x
6x
6x
6x
DO 3
24 SI
lNB
6x
6x
6x
2Yx
2Yx
2Yx
2Yx
6x
6x
6x
DO 2
20 S,
F2
10
Fl
19 Sb
pow 11
18 Sc
12
17 Sd
Sp
Sg
Sf
13
16 S,
14
15 VSS
TOP VIEW
Order Number MM57103N
See Package 23
Typical Scientific Calculator Schematic
NC NC NC
NC
-'Ll1,ilil
pow Fl F2 F3
vss
SWI
+
--
K2
o!!
SO
NC~
SI
NC
VOO
• ON/OFF
Kl
IS VSS
K3
MMS7103
'Ul
SYNC
2,1 Voo
ALGEBR:~~: ~~~ o-!
mj
K4
,
1
2
3
~NC
4
r;--
t-BLK~
OSC
lNB
004 003 002001 S.
2S,26r7r820
Sb
Sc
19
S,
Sd
18
17
16
Sg
Sf
14
Sp
13
12
"
CONVERTER
~oo
S
0
2 3 4
C B A
ENA8LE
12 GNo
OSC
OUT
R OCS
~
RC OCS
~
OS8664
U2
--2i
VCC
01 02 03 04 OS 06 07 08 09 010 011 012 013 014
20 19 18 17 16 IS 14 13 11 10 9 8
7 6
Rl
33k
2%
-'-
~~~PF
~5%
Voo
NSA
S120
014
013
012
Sf
011
Sb
010
Sg
09
Sd
08
S,
07
S,
06
Sp
OS
Sc
04
03
02
r#-
~r~
19
[l-~
18
17
16
15
14
13
12
11
10
9
8
1
6
S
4
3
2
.-
-,
~ l~
1"
r'
c;
[
~L
(;/
C
L
ol~NC
r
c:
.'t.: ,_
......_ _ _ _ _ .J
KEYBOARD
8-130
switching time, waveforms
INTERNAL
\'20
CYCLE TIME
"2
osc
VOH-==""""'-=\
SYNC
VOL - - - - - I - L_ _--..J
VIH -m~~w:e\ ~----+-....
,.......
,...,j..,...................................,....,..,
Kl-K4
VOH-:~~~~ 1.,-----------jL~,.,..,..,....................~ ...r~-----
Fl. F2,FJ
VOL.--~~:.::.::;'.;:;;:;i- -.:...._ _ _ _ _ _ _~ ""I;:o::.:..;~~.:..:..:.:; ~-+------
BLK
VOL
Note. OSC. Duty Cycle =
FIGURE 2(al. Input/Output Timing Diagram
INTERNAL
\'20
CYCLE TIME
\'20
~1
VIH
OSC
VOH
-====t:t~
SYNC
Pd
so. 001-004:::
~
=============: ~~~:.:lI
...._ _ _ _ _ _ __
VOH_==============================='~~tPdSEG
S.-Sg.Sp
VOL
FIGURE 2(b). Input/Output Timing Diagram
keyboard matrix connection table
DIGIT TIMING STATE
SWITCH
INPUTS
K1
K2
K3
K4
014
013
012
011
06
05
2
6
5
1
4
l)
L+
CS
EE
MS
MR
TAN
COS
SIN
"F
l/X
LOG
LN
9
R~P
[(
07
3
C
-
D.MS
08
0
7
+
X
F
.
09
8
%
=
M+
010
8·131
Calculators
MM57104 scientific calculator circuit
general description
The MM57104 features the most essential and desirable
scientific functions microprogrammed onto a single
economical MOS/LSI device. Use of a 9-digit display
with a 5-digit mantissa plus sign and a 2·digit exponent
plus sign is featured even though internal numbers
use a full 8-digit mantissa for accuracy. Low system
cost without sacrificing features has been achieved with
the M M571 04; direct operation from an inexp~nsive
throw-away 9V battery, eliminating the need for a
dc/dc converter, minimal cost 23-position keyboard
and a standard 9-digit low cost LED display. National's
built-in reliability and rugged 24-lead DIP add further
to the MM5710~'s total system efficiency.
features
•
Enters ±9.9999999 x 10 99 to ±1 x 10-99
•
9-position display: 5-digit mantissa plus sign and
2-digit exponent with sign
•
Left justified entry with trailing zero suppression
•
Selectable Reverse Polish Notation (RPN) or Algebraic notation with 2 levels of parentheses
•
Arithmetic functions: +, -, X, +, 1 /X,;,jx. X2
•
Constant operations in algebraic mode
•
Power function: yX
•
Logarithmic functions: LN X, LOG X; eX, lOx
•
Trigonometric functions:
COS-1, TAN-1
SIN, COS, TAN, SIN-1,
•
Full-function, addressable memory
•
4-register working stack with ROLL capability
(RPN) or EQUAL with 2 levels of parenth'eses (algebraic)
•
•
•
•
rr, 'change sign, clear, clear-all and exchange
Auto power-on clear
Degree/r~dian conversion
Two output modes: floating or scientific
sample keyboards
RPN
Algebraic
MS
SCI
FL T
DGJGJD
0080
aX
l/X
rr
TAN
LDG
lOX
M-
cos
LN
e1<
M+
DODD
DCJDD
SIN
X +> V
CA
RAD
-+
DEG
G0@J
DGJGD
DODD
.DDDD
DODD
8DGGIJ
DEG -+ RAD
ARC
ylX
CF
8DGD
8-132
SCI
FLT
ARC
aX
l/X
rr
TAN
LOG
lOX
M-
COS
LN
eX
M+
SIN
X-V
CA
CF
DEG
-+
RAO
absolute maximum ratings
Voltage at Any Pin Relative to VSS
(All Other Pins Connected to VSS)
VSS +0.3V to VSS -12V
O°C to +70°C
Ambient Operating Temperature
-55°C to +125°C
300°C
Ambient Storage Temperature
Lead Temperature (Soldering, 10 seconds)
dc electrical characteristics
'S. TA ~ +70°C, 7.9V ~ Vss -
o°c
PARAMETER
MIN
CONDITIONS
TYP
7.0
Operating Voltage (VSS - VDD)
Operating Supply Current (IDD)
VDD ~ 9.5V unless otherwise stated
VSS - VDD
= 9.5V,
TA
MAX
UNITS
9.5
V
18
mA
VSS-3.2
VSS
V
VSS-4.5
VSS
V
VDD+l.5
V
= 25°C
12
(Excluding Outputs)
Kl-K4
Input Voltage Levels
Logic High Level (VIH)
VSS - VDD
VSS - VDD
= 7.9V
= 9.5V
Logic Low Level (V I L)
K l-K4 Input Current Levels
Input High Level (lIH)
(Through Keyboard)
= VSS -
VIH
-350
3.2V
J.1A
DOl, D04 Output Voltage
Levels (Encoded Digit)
Logic High Level (VOH)
Logic Low Level (VOL)
Logic High Level Current (I OH)
= 150 kS1
= 3 J.1A
VSS - VOD = 7.9V
VOH = VDD + 1.5V
RL
VSS-l.0
VSS
V
IOL
VDD
VDD+0.5
V
-260
J.1A
-5
mA
Sa-Sg and Sp Output Current Levels
Logic High Level Current (IOH)
VOH
= VDD
+ 3V
-20
Open Drain Outputs
Sync Output Voltage Levels
-10
(With Load and Driver to VOO)
= 7.9V
= -100J.1A
IOL = 15J.1A
VSS-0.5
VSS
V
VDD
VDD+3.7
V
Logic High Level (VOH)
IOH = -30J.1A
VSS-l.5
Logic Low Level (VOL)
IOL
VSS - VDD
Logic High Level (VOH)
Logic Low Level (VOL)
IOH
F 1 Output Voltage Levels
Osc. Output Current Levels
= 3J.1A
V
VDD+1.0
V
(Output with Load to VDD)
Logic High Level Current (IOH)
VOH
Logic Low Level Current (IOL)
VOL
= VDD + 1.5V
= VDD + 0.5V
-1.0
mA
J1A
3.0
Keyboard Key Resistance (RKEY)
(Kl-K4)
LED Display Interface
8-.133
200
S1
BI
ac electrical characteristics
o°c ~ T A ~ +70°C, 7.9V ~ Vss - VDD ~ 9.5V unless otherwise stated
PARAMETER
CONDITIONS
MIN
Osc. Output Frequency
130
Osc. Duty Cycle (Figure 2)
33
TYP
MAX
UNITS
450
56
68
kHz
%
Kl-K4,INB
Input Timing
tSK
1.75
ps
tLK
1.0
ps
Fl Output Timing
CLOAD = 100 pF
4.4
ps
tpdf
Sync. Output Timing
Interval (tB, Bit Time)
8.8
30
ps
0.1
1.65
ps
tpdsH
0.1
1.25
ps
tHS
0.1
0.8
ps
0.5
tpdsL
DOl, D04 Output Timing
CL = 250 pF
CL = 100 pF(D01-D04)
CL = 250 pF (SO)
4.0
ps
Sa-Sg, Sp Output Timing (tpdSEG)
6.0
ps
Interdigit Blanking Time (Tl)
7.5
ps
tpd
connection diagram
Dual·1 n·line Package
Sc
Sp
Sb
NC
Sa
Fl
OSC (NC)
VOO
Order Number MM57104N
See Package 22
NC
SYNC (NC)
NC
INB
NC
K4
004
KJ
001
K2
VSS
Kl
TOP VIEW
8·134
functional description
REGISTER CONFIGURATION'
The user has access to 5 registers designated X, Y, Z, T,
and M. X is the display and entry register and the bot·
tom of an "operational" stack that includes Y, Z and T.
M is' an independent user·addressable memory register
that ca.n be stored, recalled, added, multiplied, subtracted
or divided with X. In the algebraic mode, Z and Tare
used as parenthesis registers.
When the calculator is in the "idle state" and ready to
accept a key, Fl is high (near VSS). It remains high
until a key is depressed and accepted, then goes low. It
goes low until the calculator is complete then goes high
again to indicate that a new key may be entered.
All registers contain 8 mantissa digits with sign and 2
exponent digits with sign.
When a key is depressed, a time·out is started. A key is
accepted as valid if it remains depressed for approxi·
mately 12 ms. The key must be released for at least
12 ms before a new key can be entered.
DISPLAY CONFIGURATION
The X·register is always displayed and shown as 8 digits
of mantissa with sign or 5 digits of mantissa with sign
and 2 digits of exponent with sign. Numbers are entered
left justified with trailing zeros suppressed.
KEYBOUNCE AND NOISE REJECTION
ERROR CONDITIONS AND INDICATION
In the event of an illegal operation, the calculator will
dispiay "Error" and X will be cleared. Any key depressed
after an error will use X = 0 for the next operator.
Table I summarizes results and operations that will
give an error indication.
DISPLAY FORMAT
Floating point display output format is "F", "CS". If X
is greater than 99999999. or less than 0.001, the display
is in scientific notation.
RANGE ACCURACY AND SPEED
All functions work over the full mathematically allow·
able range as defined by the error conditions.
By pressing "F", "EE" all results are displayed in
scientific notation.
All functions take less thari 1 second and are accurate
to 8 digits.
READY SIGNAL OPERATION
Output F 1 of the MM57104 can be used as a "ready
signal" to indicate calculator status. It can be useful
in providing synchronization information during testing
and if used with other logic.
ALGEBRAIC OR RPN SELECTION
Leaving pin 17 (INB) open selects algebraic. Connect
pin '17 to VSS to select RPN.
TABLE I. Results and Operations Resulting in an Error Indication
Results> 9.9999999 X 1099
Results < 1 x 10-99
Division by 0
LOG, LN <0
0
TAN, SIN, COS> 9000 :
0
0
TAN 90 , 270 , etc.
SIN-l. COS-l > 1 or~ 10- 50
VX
<0
More than two open parentheses without
a close
More close parentheses than open
IT
Iz
Iy
IX
y
x
1M
m
FIGURE 1. User Register Configuration
8-135
functional description
(Continued)
KEy.oPERATION
Clear Key, "C"
Enter Exponent/Scientific Notation Key, "EE"/"SCI"
a) In' RPN mode: Pushes down stack and clears T.
Four "C" depressions will clear a completely full
stack
b) After "F": Clears all registers including the
memory
a) Sets enter exponent mode, displaying 00 in exponent
position
,I,
b) After F: Set calculator to scientific notation
,II'
c) In algebraic mode after number key: Copy Y to X
d) In algebraic mode after function key: Clears all
, modes and all registers except M
a) X squared to X
b) After F: Square root of X to X
Number Keys, "0" - "9", "."
Stack Rotate Key "ROLL"/"DEG" Key, RPN Only
a) In RPN mode after any function key except "EN":
Copies X to Y and clears X and enters number left
justified to X
b) After any number key: Enters next digit - > X. All
entries after eighth are ignored
c) After "EE": Enters number to exponent. Last 2
entri~s are used
d) After "EN": Clears X and enters number' in X
e) In algebraic mode, after function key: Clears X and
enters number '
a) Rolls stack down
b) After F: Convert radians to degrees
"F", "." Exchange Key,
"X~Y"
Exchanges X and Y
"F", "5" Common Log Key
Common' logarithm of X to X (Base 10)
Change Sign Key, "CS"/"FL T"
"F" "6" 10x Key
a) After "EE": Change si~n of exponent of X
b) After "F": Set floating point mode
c) After any other key: Changes sign of X mantissa
lOx to X
"F" "2" Natural Log Key
"F" "9" Reciprocal/"1/X"
Natural logarithm of X to X (base e)
Reciprocal of X to X
"F" "3" eX Key
"F" "8" Power Key, "yx"
eX to X
a) In RPN mode: Computes yX power, pushes down
stack, clears T
b) In algebraic mode, not in chain mode: Copy X to Y,
set yx chain mode
c) In algebraic mode, in chain mode: Perform the specified function of X and Y, putting the result to both
X and Y, set yX chain mode
Trigonometic Keys,'''F'' "0", I'F" "1", "F" "4" "SIN",
COS, TAN"
'.
a) Replaces the decimal angle in X with the indicated
trigonometric function
b) After, ARC: (SIN-1, COS-1, TAN-1), replaces X
with the decimal angle of the indicated inverse trigonometric function
Enter Key, "EN", RPN Only
a) Pushes up stack, retains X
b) After F: (CF) resets F mode'
The Four Function Keys, "+, -, X,
+", In RPN Mode
a) Addkey,"+":Y+X-+X
Subtract key, "-": Y - X -+ X
Multiply key, "X": Y x X -+ X
Divide key, "+": Y /X -+ X
Then push down stack and clear T
O-+T-+Z-+Y
Second Function Key, "F"
Sets F mode
Memory Recall/Memory Store, "MR/MS"
b) After F:
a) In RP~ mode: Pushes up stack, recall memory to X
b) In algebraic mode: Recall X to M
c) After F: Copy X to M
+: X + M to M
-: M - X to M
X: 1Tto X
.:.. Convert X from
8-136
degre~s
to radians
functional description
(Continued)
The Four Function Keys, "+", "-", "X", "-;'-", In Algebraic Mode
Open Parenthesis, "[ (", Algebraic Mode Only
a) Copy X, T copy X to Z, copy P mode to P2 mode:
Copy the calculator mode to Pl mode, reset calculator mode
b) After F: Square root of.X to X
a) If not in chain mode: Copy X to Y, set the specified chain mode
b) After "+, -, X, -;.-" key: Copy X to Y, set chain mode
c) In chain mode: Perform the specified function of X
and Y putting the result to X and Y, set the specified
chain mode
Close Parenthesis
"F" "7" ARC Key
Set ARC mode
Equal Key "=", Algebraic Mode Only
a) In chain mode: Perform the specified function of
X and Y putting the result to X' and save the last'
number displayed in Y, set the constant mode
")1 ", Algebraic Mode Only
a) In chain mode: Perform the specified function of
X, Y putting the result to X. Copy Z to Y, copy T
to Z, clear T2. Copy P2 mode to Pl mode, copy P1
mode to the calculator mode, reset P2 mode
b) Not in chain mode: Z to Y, T to Z, clear T. P1 mode
to calculator mode, P2 mode to P1 mode, reset P2
mode
c) After F; Convert radians to degrees
b) In, constant mode: Perform the specified function
of X, Y putting the result in X
c) After F: (CF) reset F mode
summary,
Stack Operations in RPN Mode
(M UNCHANGED)
@J
~LDST
~~~T
:~~:
'---Z
z~
Y~~Y
x~ '----X
:-----Ir=:
"---LOST
!+,-,X,7,y x
.:
T
l
:~~T'
• z
:==x----:
z~z
Y\~Y
x~X
SIN, CDS, TAxN, ~IN~I, COS~l, TAN-I, CS
LN, LOG, 10 ,e ,1
X ,EE, ->OEG,
->flAD, F
,v.
!ROLL I
,.
T
t~' ZT
y
•
Y
y
f (x)
,.
X
x
z
o
Y
X
,
AFTER FUNCTION KEY OR
ERROR
• T
z,
8-137
•
Z
•
Y
•
X
summ-ary
(Continued)
Stack Operations in RPN Mode (Continued)
FIRST
~
AFTER FUNCTION KEY
~AFTER@]
OR
•
T
r - LOST
t~T
z~
.. z
.r----- z
y--.-l
y
;--:Y
-r-
NUMBER
..
Y
•
X
X
NUMBER _ _ _ _---J
NUMBER LEFT JUSTIFIED
Operations Using Memoryls)
~
.. T
.. Z
• Y
~LOST
t---.-J'
z-
.T
r---Z
r-- Y
:
y--.J
:--.-1c:
POWER "ON"or
:~
\
ERROR
OVERFLOW INTO MEMORY
~
o
.
~LOST
•
T
•
Z
• T
• Z
• Y
•
X
•
M
•
Y
:~ "--X
m~'--M
.
' - - - LOST
Example Showing Parenthesis Registers and Modes in
Algebraic Mode
6 X (2(8-5) + 2)
X
Y&MODE
P1
Z& MODE
P2
T&MODE
6
6
X
6
6x
(
6
6
6x
2
FYx
2
6x
2
6
2Yx
2
2
6x
2Yx
2
2Yx
88-
2Yx
6x
6x
5
8
8
5
2Yx
6x
)
3
2Yx
6x
+
8
2
2
8+
8+
6x
10
6x
60
10x (constant)
8
)
6x
8~138
6x
~
system interconnection diagram
,5
I
11
9
17
,3
15+7
LEO NSA1198 OR EOUIV.
~~2
•4
• 6
10
ro8
12
11-14
ro16
~
18
I
1]
MR
[(
F
EE
+/-
7
8
9
X
4
5
6
-
1
2
3
+
e
=
0
13
...
3
I
01
4
02
5
03
8
6
9
10
04
06
07
05
OS8874
ep
Vee GNO
0
2
~:4 .g
rol
9V
10
11
004 001Sa 5
Sb
Sc
4
3
S 2
MM57104 d
16
K4
Se 1
15
24
K3
Sf
14
23
... K2
Sg
22
13 ..
K1VSS VOoSp
9V~
---=r
GNO
.L
8-139
-
11
12
08
09 .\13
LOW BAT
I
switching time waveforms
INTERNAL
CYCLE TIME
92D
91
92
91D
1>2D
-:::~/CE
12
FC/CA
"
.~
~
~
~
~
~
f-
~ OP
Sg
Sf
S,
Sd
S,
Sb
S,
09
08
07
06
05
04
OJ
02
B. H B. H H B. B. B. B.
LED OISP LAY (NOTE 1)
01
I
~
-I
1
LL __ ~
-
If
DIGIT
DRIVER
(NOTE 2)
~
9V MALLORY
MN1604 OR
EQUIVALENT
POWER
SWITCH
~MT/4
~s
lOAN-PMT/5
"""'
i-----
Note 1: Display: Use NSA1198, NSA1298 or NSA0098.
Note 2: Driver: Use OS8864 or OS8873 (with low-battery indicator), or OS8855 or OS8872 (without low-battery indicator).
FIGURE 1. Complete Calculator Schematic
i - - - - - - - - - - - W O R O TIME
-------------11
--==----------------------~~
I
02
09
DECIMAL
POINT-I_ _
-+__-t.J
SEGMENTS
S'--1_ _-,:.J
,
ACTUAL DISPLAY;
CI-'CCI' -, -','
CI 'C'
~I
-,
SEGMENT
OESIGNATION
~.C
09-..
_ - - - - - - - -___ 01
FIGURE 2. Display Timing Diagram
8-143
IIT/b
_1::1,
d
LED
DISPLAY
FINANCIALCALCULATOR
(7)
SEGMENT
OUTPUTS
VSS
~
K
INPUTS
MM57123
DIGIT
OUTPUTS
NSA1298
SEGMENTS
PROGRAM
RUN
VDD i---- MODE
SWITCH(
REAOY
LOAD
II II II II 1111 1111 II
1::1. 1::1.1::1.1::1.1::1.1::1. 1::1.1::1. 1::1.
DIGITS
(9)
~
r---iJ
I
L._
I
4X 9
OAT A
KEYBO ARD
AN 0
1 X4
PROGRA MMER
CONT ROL'
KEYBO ARD,
~_:..J
OUTPUT
-=-
INPUT DIGIT DRIVER
-
(8)
OATA
CONTROL
-..:-+
-9V
--
(9) ..
(9)
~
I
VCC
~
GND
~
READY
RUN/LOAD
VSS
K I/O's
MM5765
K5
VDD
,
ALARM
~i~RM
,
-~ INDICATOR
LEARN MOOE
PROGRAMMER
POWER
SWITCH
,..
- ON
- FIGURE 3. Low Cost Hand-Held Programmable Financial Computer
Using the MM57123 C.9.999999999 x 1099
Results.< 1 x 10-'99
Division by 0
LOG, LN~O
yx for Y~O
TAN, SIN, COS~ 25 revolutions (9000°)
0
TAN of 90°, 270 , etc,
SIN-l, COS-l > 1.or~·10-50
VX <0
OMS Conversion ~ 10 10
X! 0, or not an integer
More than two open parentheses
More closed parentheses than open parentheses
<
EF154
functional description (con't)
KEY OPERATIONS
Accumulative/Factorial Key, "M+/X!"
Clear Key, "C"
a) Sums X to Ml
b) After "F": (X!) replaces X with X·factorial
a) After number keys: copies Y to X
b) After function key: clears all modes and X, Y, Pl
and P2
Coordinate Conversion Key, "R
c) After "F": clears all modes and all registers
a) Converts contents of X and Y in rectangular coordinates to polar coordinates: reset calculator mode
<+
P"
Number Keys, "0" - "9," "0"
JX2 + y2 to Y
a) After any function key: clears X and enters number
left justified to X
b) After any number key: enters next number. All
entries after tenth are ignored
c) After "EE": enters number to exponent. Last two
entries are used
d) After "F":
(_+OC) ~'o"
(-+°F) "0"
(DEG) "1"
Converts X in OF to °c
(oC = (oF - 32)/1.8)
Converts X in °c to OF
tF = 108°C + :32)
Set calc to degrees mode
(GRAD) "2" Set calc to gradians mode
'(RAD) "3" Set calc to radians mode
(-+ LB) "4"
(-+ IN) "5"
(-+
(-+
(-+
(-+
Replace
Replace
GAL) "6" Replace
KG) "7" Replace
CM) "8" Replace
LIT) "9" Replace
X with
X with
X with
X with
X with
X with
X..;. 0.4535924
X..;. 2.54
X ..;. 3.785412
X 0.4535924
X 2.54
X 3.785412
0
0
0
e) 1, 2, 3 after:
TAN- 1 Y/X to X
b) After "F": (P -+ R) converts contents of X and Yin
polar coordinates to rectangular coordinates: resets
calculator mode:
Y SIN X -+ Y
Y COS X -+ X
Note: R <-+ P works in all four quadrants
Square Root/Square Key, ".jX/X2"
a) Square root of positive value of X to X
b) After "F": (X2) X-squared to X
Second Function Key, "F"
Sets F mode
Memory Store/Mean Key, "MS/X"
a) Sets memory store mode
b) After "F": {X) divides Ml by M3 and puts result in
X; this gives mean of data summed using 'L+ key
Memory Recall/Standard Deviation Key, "MR/SD"
"MR"
Recall selected memory to X
"MS"
X to selected memory
"M+ mode" M + X to selected memory
"M- mode" M - X to selected memory
"MX mode" M X to selected memory
"M";' mode" M..;.X to selected memory
"MEXC mode" X is exchanged with selected
memory
a) Sets Memory.Recall mode
b) After F: (S.D.) computes standard deviation of data
entered with the 'L+ key, using the relationship:
0
Change Sign Key, "CS"
SD
=
('LX)2
'LX 2 - - N
N -1
(M1)2
M2--M3
M3 -1
'LX, 'LX2 and N may be recovered from Ml, M2
and M3
Enter Exponent Key, "EE/SCI"
a) After "EE": change sign o'f exponent of X
b) After "F": (F LT) set calc to Floating Point mode
c) After any other key: changes sign of X mantissa
Positive/Negative Summing Key, "'L+/,'i,,-"
a) Used to enter data points for computation of mean
and standard devi ati on:
Sums X to Ml ('Lx)
Sums X2 to M2 ('Lx2)
Adds 1 to M3 (N)
b) After "F": ('L-) used to delete data points:
Subtracts X from M 1
Subtracts X2 from M2
Subtracts 1 from M3
a) Sets enter exponent mode, displaying 00 in exponent
position
b) After F: (SCI) sets the calculator to display using
scientific notation
Common Log Key, "LOG/10 x "
a) Common logarithm of X to X (base 10)
b) After "F": (lOX) lOX to X
Natural Log Key, "Ln/e x "
a) Natural logarithm of X to X (base e)
b) After "F": (eX) eX to X
functional description (c~n't)
Decimal to Degrees Conversion Key, "D.MS"
Equal Key, "="
a) Replaces the decimal angle in X with its degrees
(or hours), minutes and seconds conversion
a) In chain mode: perform the specified function of X
and Y, putting the result to X and save the last number displayed in Y, set the constant mode
b) In constant mode: perform the specified function of
X, Y putting the result in X
c) After "F": (CF) reset F mode
b). After "F": (OMS) degrees (or hours) minutes and
seconds in X is converted to decimal angle
Trigonometric Keys, "SIN, COS; TAN"
a) Replaces the decimal angle in X with the indicated
trigonometric function
b) After "F": replaces X with the decimal angle of the
. indicated inverse trigonometric function
Exchange Key, "X
+r
Y/X
+r
M"
a) Exchange X and Y
b) After "MS," "MR" or "F": (X
to MEXC mode
Power/Reciprocal Key, "yx/1/X"
a) If not in chain mode: copy X to Y set yX chain mode
b) After "+, -, X, 7, yX key: copy X to Y, set yX
chain mode
+r
M) sets calculator
Open Parentheses, "[(f2rr"
c) In chain mode: perform the specified function of X
and Y putting the result to X and Y, set yx chain
mode
d) After "F": reciprocal of non-zero value of X to X
a) Copy P1 to P2, copy Y to P1. Copy P1 mode to P2
mode, copy the calculator mode to P1 mode, reset
calculator mode
b) After "F": (2rr) enter 2 Pi to X (6.283185307)
The Four Function Keys, "+, -, X, 7"
Close Parentheses/Pi Key, ") 1/n"
a) If not in chain mode: copy X to Y, set the specified
chain mode
b) After "+, -, X, 7, yX " key: copy X .to Y, set chain
mode
c) In chain mode: perform the specified function of X
and Y putting the result to X and Y, set the specified
chain mode
d) After "F," "MS" or "MR": set the appropriate
memory mode (M+, M-, MX, M7)
a) In chain mode: perform the specified function of X,
Y putting the result to X. Copy P1 to Y, copy P2 to
P1, clear P2. Copy P2 mode to P1 mode, copy P1
mode to the calculator mode, reset P2 mode
b) Not in chain mode: P1 to Y, P2 to P1, clear P2, P1
mode to calculator mode. P2 mode to P1 mode,
reset F'2 mode
c) After "F": (n) enter Pi to X (3.14159765359)
TABLE II. Example Showing Parentheses Registers and Modes
6 X (2(8-5) + 2)
X
YMODE
Pl MODE
P2 MODE
6
6
X
6
6X
(
6
6
6X
2
yX
2
6X
2
6
2 yx
(
2
2
6X
2 yx
6X
8
2
2 yx
6X
-
8
8
2 yx
6X
5
5
88-
2 yx
6X
)
3
2 yX
6X
+
8
2
8+
8+
6X
2
)
10
60
=
6X
6X
10 X (const)
10 is constant multiplier
'.8·,156
Calculators
MM57136 RPN scientific calculator control ROM
general description
The MM57136 Control ROM is programmed to perform
the functions described when used with the MM5782
Processor and RAM chip. Complete electrical specifications and application data may be found in the MM5781
arid MM5782 data sheet.
• Trigonometric functions: SIN, COS, TAN, SIN-1,
COS- 1, TAN- 1
•
•
•
•
•
Enters and displays ±9.999999999 X 1099 to ± 1 X
10-99
Compute in degrees, radians or gradian mode
Rectangular/Polar conversions
Degrees, minutes, seconds conversions
3 full-function, addressable memories
4-register working stack with ROLL, CU~AR and
EXCHANGE capability
• Statistical functions: standard deviation and mean
• 4 display output modes: floating, scientific, fixed
or engineering
• Calculates internally using,12 mantissa digits to insure
all ten displayed digits are correct
• Left justified entry with trailing zero suppression
• Reverse Polish Notation (RPN)
• Arithmetic functions: +, -, X, 7, l/X, VX, X2
• Power function: yX
• Logarithmic functions: LN X, LOG X, eX, lOX
• Factorial:n!
• Conversions:oFtC, LB/KG, IN/CM and GALl
LITERS
• n, change sign and clear-all
• Percent and percent difference functions: %, Ll%
• Auto power-on clear
• Auto display cut-off for extended battery life
keyboard
connection diagram
features
•
Oual-I n-Line Package
~1s;l~r;;J~
Voo
LJ~~~~
....!.
~12
IRS..!
~~I7xliv=lj.;l
~~~~~
~IJ
SYNC 2
r-;.l~~~~
~L-=J~~~
OSC~
l!-14
5
Kl-
E- 15
K2...!.
2!.. 16
KJ ...2.
.!!..17
8
K4-
22..18
Fl...1
,!!. SKIP
F2...!!!.
.!!. TEST
FJ...!.!.
~INB
r:;;lr;lI~Jc;l~
~~~~~
r-;l1aI1aI~
~~~~
[TI[IJ[g[IJ
GJGJQJGJ
0000
VSs..,g
#-F4/BLK
TOPVIEW
Order Number MM57136N
See Package 22
Keyboard Matrix, Primary Functions
SWITCH
INPUTS
Kl
K2
K3
K4
OIGIT TIMING STATES
05
MR
LN
06
07
08
2
1
3
5
4
6
MS EE CS
LOG l/X v'
09
010
0
.
011
7
8
9
~+
%
SIN
COS
(8~~57
012
013
014
+
X
EXC EN
ROLL M+
TAN R .... P .... D.MS F
C
~
functional description
REGISTER CONFIGURATION
When the calculator is in the "idle state" and ready to
accept a key, FIP is high (near VSS). It remains high
until a key is depressed and accepted, then goes low.
It stays low until the calculation is complete, then returns
to a high state which signifies a new key may be entered.
The user has access to 7 registers designated X, Y, Z, T,
-M 1, M2 and M3. X is the displ ay and entry register and
the bottom of an "operational" stack that includes Y, Z
and T. Ml, M2 and M3 are independent user-addressable
memory registers that can be stored, recalled, added,
multi-plied, subtracted, divided or exchanged with X.
KEYBOUNCE AND NOISE REJECTION
All registers contain 12 mantissa digits with sign and 2
exponent digits with sign.
'
When a key is depressed, a time-out is started. A key is
accepted as valid if it remains depressed for approximately 12 ms. The key must be released for at least 12
ms before a new key can be entered.
DISPLAY CONFIGURATION
The X-register is always displayed and shown as 10 digits
of mantissa with sign and 2 digits of exponent with sign.
All internal calculations are done with 12 digits and
rounded to ten; therefore, all displayed digits are accurate
for all functions. Numbers are entered left justified with
trailing zeros suppressed.
ERROR CONDITIONS AND INDICATION
In the event of an illegal operation, the calculator will
display "Error" and X will be cleared. The other registers
in the stack and all memories are protected. Any key
depressed after an error will use X = 0 for the next
operator. Table 2 summarizes results and operations that
will give an error indication.
DISPLAY FORMAT
Floating pOInt display output format is selected at poweron or by pressing "F", "OS", ..... _ If X is greater than
9999999999. or less than 0.1, the display is automatically
in scientific notation.
The number of decimal places displayed call be selected
by pressing "F", "DSP" and a number key (0-9). The
display is rounded to the selected decima'i position. A
result too large or small to show with the selected position is displayed in scientific notation.
TABLE II. Results and Operations that Result in an
Error Indication
Results> 9.999999999 x 10 99
< 1 x 10-99
By pressing "F", "ENG" all results are displayed in
modified scientific notation with exponents of 10 'that
are multiples of 3.
Results
Di~ision by 0
LOG, LN:::; 0
yx for Y:::; 0
All results maintain 12 digits internally at all times. Only
the display is affected when '''DS'' is used to reduce the
number of decimal positions. The unrounded result may
be viewed by returning to the floating point mode.
TAN, SIN, COS> 25 revolutions (9000°)
TAN of angles at or near ±oo asymptotes
SIN-l, COS-l > 1 or~ 10- 50
.jX < 0
DISPLAY CUT-OFF
DMS Conversion ~ 10 10
If no key is depressed for approximately 32 seconds, an
internal display cut-off circuit will turn off the entire
display except fo'r segments C, 0, E and G of the leftmost digit. Depression of any key will restore the display.
Input INB of the MM5781 must be wired to VDD to
enable the display cut-off feature. If INB is left floating,
no display cut-off will occur.
Xl
< 0, not an integer, or> 69
RANGE, ACCURACY AND SPEED
BATTERY LOW INDICATION
All functions work o·ver the mathematically allowable
range defined by Table II.
The DS8664 digit driver can sense a low battery voltage
condition and send a signal to input I RB of the MM5781,
which causes the display to flash an "L" in the left-most
sign position.
Transcendental functions give 10 digits of accuracy
except near normal limits and all other functions are
internally accurate to 12 digits.
READY SIGNAL OPERATION
The calculation time of all transcende'ntal functions
takes less than a second; all other functions, with the
exception of factorial computations, are executed in
less than 1/3 second. Factorial of 69, the longest calcula- '
tion possible, takes less than 3 seconds.
Output F IP of the MM5781 can be used as a "ready
signal" to indicate calculator status. It can be useful in
providing synchronization information during testing
and if used with other logic.
·8~158
functional description (con't)
t======~' T
z=====~, Z
:='
:='
y====:' Y
1,-x_ _ _--11 x
:=:'
, m3
, M3
~,m=2=======:' M2
,-Im_l_ _----'I
M1
FIGURE 1. User Register Configuration
KEY OPERATIONS
Clear Key,
"c"
Ch~nge
Sign Key, "CS/OS"
a) Pushes down stack and clears T. Four "c" depressions will clear a completely full stack
b) After "F": Clears all registers including the memories
c) After any other key: changes sign of X mantiss(l
Number Keys, "0" ~ "9," "."
Positive/Negative Summing Key, "'E+/'E-"
a) After any function key except "EN": pushes up
stack, clears X and enters number left justified to X
b) After any number key: enters next number. All
entries after tenth are ignored
c) After "EE": enters number to exponent. Last two
entries are used
d) After "EN": clears X and enters number in X
e) After "OS": load decimal select position for fixed
decimal output mode
f) After "F":
a) Used to enter data points for computation of mean
and standard deviation:
Sums X to Ml ('EX)
Sums X2 to M2 C~:X2)
Adds 1 to M3 (N)
b) After "F": ('E-) used to delete data points:
Subtracts Xfrom M1
Subtracts X2 from M2
Subtracts I from M3
.(~OC) "."
(~oF)
"0"
Converts X in ° F to °c
(oC = (OF - 32)/1.8)
Converts X in ° C to ° F
(OF = 1.8°C + 32)
(DEG) "1"
Set calc to degrees mode
(GRAD) "2" Set calc to gradians mode
(RAD) "3"
Set calc to radians mode
(~LB)
(~IN)
"4"
"5"
"6"
"7"
(~GAL)
(~KG)
(~CM)
"8"
(~LlT) "9"
Replace
Replace
Replace
Replace
Replace
Replace
X with
X with
X with
X with
X with
X with
X -;- 0.4535924
X -;- 2.54
X -;- 3.785412
X • 0.4535924
X • 2.54
X • 3.785412
g) 1,2,3 after:
"MR"
Push up stack, recall selected memory to X
"MS"
X to selected memory
"M+ mode" M + X to selected memory
"M- mode" M - X to selected memory
"MX mode" M' X to selected memory
"M-;- mode" M -;- X to selected memory
"MEXC mode" X is exchanged with selected
memory
a) After "EE": change sign of exponent of X
b) After "F": (OS) set calc to Decimal Select mode
Accumulative/Factorial Key, "M+/X!"
a) Sums X to Ml
b) After "F": (X!) replaces X with X-factorial
Coordinate Conversion Key, "R ..... pOI
a) Converts contents of X and Y in
cciordinates to polar coordinates:
rectangular
JX2 + y2 to Y
TAN- 1 y/xtox
b) After "F": (P ~ R) converts contents of X and Yin
polar coordinates to rectangular coordinates:
Y SIN X~Y
Y COS X~ X
Note: R ..... P works in all four quadrants
Square Root/Square Key, ".jX/X2"
a) Square root of positive value of X to X
b) After "F": (X2) X-squared to X
functional description (con't)
Reciprocal/Power Key, "1/X/Yx"
Exchange Key "X
a) Reciprocal of non-zero value of X to X
b) After "F": ('(X) computes power, pushes down stack,
clears T
a) Exchanges X and Y
b) After MS, M R or F: (X
mode
Enter Key, "ENT/CF"
Percent/Delta Percent Key, "%/lJ.%"
a) Pushes up stack, retains X
b) After F: (CF) resets F mode
a) Calculates percent by:
X· yo'
+>
Y/X'" M"
<+
M) sets calculator to MEXC
~X
100
b) After F : (lJ.%) percent change between X and Y to X,
and difference to Y:
Second Function Key, "F"
Sets F mode
V-X
X
100 ~ X, and Y - X ~ Y
Memory Store/Mean Key, "MS/X"
a) Sets memory store mode
b) After "F": (X) divides Ml by M3 and puts result in
X, this gives ~ean of data summed using L+ key
Memory
Recall/Standard
Deviation Key, "MR/SD"
a) Sets Memory Recall mode
b) After F: (S.D.) computes standard deviation of
data entered with the ,L+ key using the relationship:
2
LX -
(LX)2
--
SO
N
(Ml)2
M2 -
N -1
a) Common logarithm of X to X (base 10)
b) After "F": (lOX) lOx to X
Natural Log Key, "Ln/e x "
a) Natural logarithm of X to X (base e)
b) After "F": (eX) eX to X
Decimal to Degrees Conversion Key, "D.MS"
M3
M3 -1
LX, LX2 and N may be recovered from Ml, M2 and
M3
Enter Exponent Key, "EE/ENG"
a) Replaces the decimal angle in X with its degrees
(or hours), minutes and seconds conversion and sets
the decimal select to four.
b) After "F":' (OMS) degrees (or hours), minutes and
seconds in X is converted to decimal angle
Trigonometric Keys, "SIN, COS, TAN"
a) Sets enter exponent mode, displaying 00 in exponent
position
b) After F: (ENG) sets the calculator to the engineering
mode, which displays all numbers with an exponent
in mUltiples of 3.
a) Replaces the decimal angle in X with the indicated
trigonometric function
'
b) After F: replaces X with the decimal angle of the
indicated inverse trigonometric function
I
The Four Function Keys, "+, -,X, -:-"
Stack Rotate/Pi Key, "ROLLhr"
a) Rolls stack down
b) After F: (1T) pushes up stack
3.14159265359 to X
Common Log Key, "LOG/10 x "
and enters 1T,
a) Add key: Y + X ~ X
Subtract key: Y - X ~ X
M.ul.tiply key: Y • X ~ X
DIVide key: Y -:- X ~ X '
b) After MS, MR or F:
"+" Sets M+ mode
Sets M- mode
"X" Sets Mx mode
"-:-" Sets M-:- mode
8-160
Then push down
stack and clear T:
O~T~Z~Y
summary
Summary of Stack Operations
(MI. M2. M3 UNCHANGED)
SIN, COS. TAN. SIN-I, COS-I. TAN-I. CS
LN. LOG. lOX. eX. I/X. JX. X2 .. X!. SD .• X. KG.
CM. LT. LB. IN. GAL. of. "C. DMS ......... DMS. %
@].
~LOST
t-./
z
T
·t
/
/,----~
--_~T
..
Y
..
X
•
T
x~X
..
y
X
•
X
~LOST
V
f (x)
V'r--1'Y
V~
. \
~
.. T
• Z
t~T
::
V---"X,
T
.. Z
\"-=-z
z
..
.. Z
• Z
z
Z
V
Y
X
X
~ AFTER FUNCTION
KEY OR
1 +. -. X. 7. yx 1
O_ _ _
'~T
--\"-=-z
V,~y
X~X
11.1-----'
FIRST
~
~ AFTER NUMBER KE'y OR
AFTER FUNCTION KEY
~LOST
t
z
y
/
.
..
1 DS. DEG. RAD. GRAD. ENG. CF. F I·
•
T
T
.. z
;-=:~
yx
..
y
•
X
NUMBER - - - - - - - ' .
EJAFTER~
t
V
OR
~
ERROR
• T
T
.. Z
.•
•
.. Z
.z
.. Y
Y
NUMBER - - - - - - -....- X
:
\\.
•
LOST
8-161
X
summary (con't)
Summary of Operations Using Memory(s)
(n = 1,2, J)
~
. r-- LOST
t----l z
~
/
y
mn
.. T
.. Z
.. Y
.. T
-z
Y
2~,
X
mn----
~
[2]
---------- T .
.. Z
y
x
\.
-
Y
y
:
~n
x
mn~LOST
.. T
.. Z
:~
-..
....
ERROR
OVERflOW INTO MEMORY
T
.. T
Z
-
Z
Y
-
Y
X
mJ~MJ
m2~M2
- - -......\
~X
_ M
mn~-
' - - - LOST
m1~M1
MS,+, n
MS,-:-,n
,MS,X,n
MS, -, n
POWER "ON" OR
...
..
..
..
y
x
T
Z
Y
X
~LOST
mn
~
~f (x, m)
Mn
~
- T
.. Z
o
o
..
Y
_ X
x
-
.T
-
Z
.. Y
.. X
o- - - - - - -...._- MJ
mJ~MJ
O·
m2~M2
.. M2
- - - - - - -....-- M1
m1~M1
Calculators
»
2
........
I
N
CALCULATOR CHIP MAKES A COUNTER
INTRODUCTION
GENERAL DESCRIPTION
In applications that require counting at fairly low rates
and display of the accumulated total, the MM5736
calculator chip can be used to yield a very low parts
count solution. Such applications include: timers, stop·
watches, bin counters, digital panel meters, coordinate
counters and nearly all applications that currently use
mechanical counters. A 6 digit counter that will drive a
LED display and count at a maximum rate of about
60 Hz can be constructed with only 2 integrated circuits.
Higher counting rates, simplified control, and more
versatile display driving capability can be obtained with
the addition of a few more components. Counting is
accomplished by loading a "1" into the calculator and
causing an "add" each time the counter is incremented.
But before describing any actual counters, a brief
explanation of the calculator's operation is in order.
The MM5736 is a 6 digit, no decimal point, five function
calculator. These five functions are: ADD, SUBTRACT,
MUL TIPL V, DIVIDE, and CLEAR. The calculator has 3
inputs (K 1 , K 2 , K 3 ) that are designed to be driven by a
keyboard matrix and two sets of outputs: 6 "digit"
outputs and 7 "segment" outputs. The segment outputs
provide a positive true, 7 segment 'code that represents
the information in the calculator's display register.
These outputs are multiplexed such that the 7 segment
code for digit 1 appears on the segment outputs during
digit time 1. The code for digit 2 appears during digit
time 2 and so on as illustrated in Figure 1. These
outputs are designed to drive a LED readout in a
"digit" multiplexed manner by strobing the LED char·
acters with the digit outputs. The digit outputs can not
drive the LED display directly and must be buffered
r - - - - - - - - - · - - W D R D TIME
----------1
INTERDIGIT BLANKING TIME
DIGIT 1
OlGIT2
DIGIT
OUTPUTS
DIGIT 3
DIGIT 6
So
Sb
Sc
SEGMENTS
Sd
S.
Sf
Sg
SEGMENT
DESIGNATION
ACTUAL DISPLAY,
06--------01
FIGURE 1. Display Timing Diagram
····-8-163
....N
'7
Z
«
with a DM75492 digit driver. The segment outputs will
drive some LED displays directly but the designer must
choose the display carefully if he does not wish to use
segment drivers. National's line of low current LED
displays, such as the NSN66A and NSN98A, can be
driven directly by the calculator chip.
itself will draw about 6 mAo If a LED display is driven
directly, without segment drivers, the current that drives
the display must come through the calculator so the
total power supply current could be as high as 110 mA
but will typically be about 50 mAo This is dependent
to some extent on the supply voltage and the nature of
the particular digit drivers that are used.
ENTRY INTOTHE CALCULATOR
NO POWER SUPPLY RAMP ALLOWED
Numbers are entered into the calculator by conf)ecting
the appropriate digit output to either the K1 or K2
input. Arithmetic operations (and the clear operation)
are initiated by connecting th{l appropriate digit output
to the K3 input. Table I shows the combinations of digit
outputs and K inputs.
TABLE I.
Digit
#
K1
1
2
3
4
5
6
0
1
2
3
4
5
K2
K3
The power supply voltage must come up to an operational level fairly quickly since a slow ramp will not
always initialize the calculator properly. The chip was
designed for battery operation where the dc source is
switched. If the chip is used in a syst~m with a heavily
. filtered power supply, some provision should be made
to allow the Vss terminal of the calculator to rise
abruptly. After power up, the calculator should be
cleared twice to ensure that all registers are reset to zero.
The first CLEAR operation affects only the display
register, the second CLEAR affects all other registers.
CLR
CMOS COMPATIBILITY
6
7
8
9
-
+
X
Note: Blanks are illegal connections.
Switch debounce is done. in the calculator chip and is
accomplished by requiring that the digit output of
interest be connected to the proper input for at least 8
consecutive word times (see Figure 1). Before another
entry can be made, at least 8 word times must elapse
during which none of the digits outputs are applied to
\ the K inputs. This requirement limits the speed of the
calculator but is necessary to provide an adequate
debounce timeout. A method of speeding up this timeout is discussed later.
POWER REQUIREMENTS
The MM5736 will operate from a single supply voltage
anywhere between 6.5V and 9.5V. The calculator chip
o-_---'-IK
START
J
The MM5736 is directly compatible with Nationals' 74C
line of CMOS. The number of CMOS loads the calculator
can drive is limited only by degradation in waveshape
due to capacitive loading. Loads of 200 pF or less should
present no problem to the digit outputs but the segment
outputs should not be loaded with more than about
50 pF. This means fanout should be limited to about 10
on the digit outputs and 4 on the segment outputs. The
CMOS can be run from the same supply as the calculator
and still drive the calculator inputs directly. This
compatibi.lity makes interfacing with the calculator a
breeze.
SIMPLEST COUNTER
Figure 2 shows a 6 decade counter that drives a display
and requires a minimum of parts. This circuit's
maximum counting rate will typically be about 60 Hz.
Some chips may run as slow as about 40 Hz while some
may run as fast as 150 Hz due to inherent variations
of the on-chip oscillator from calculator to calculator.
This counter is useful in applications where speed is not
S. Sb Sc Sd S. Sf SJ
ss
10
MM5736
CALCULATOR CHIP
FIGURE 2. Simplest Counter
8-164
»
2
.!..
an important factor and where the counter is reset
manually. The resetting of this circuit consists of two
operations, clearing the calculator and entering a 1 into
it again (only one CLEAR operation is needed following
an arithmetic operation). The circuit in Figure 2 leaves
these two operations to the operator; he must first clear
the counter by depressing S1 to the CLEAR position
and then he must enter a 1 into the machine by depressing S2 to the START position. This allows the operator
to control when the counting starts without gating the
"count" input.
operate as long as the voltage between the Vee terminal
and each output is at least 1.6V. This means Vee can be
operated at a lower level than Vss, resulting in a power
saving. The voltage on an output of the DM8895 when
the segment is ON is determined by the saturation voltage of the digit driver (typically 1.0V for the DM75492)
and the voltage across the LED (typically about 1.8V).
Consequentially the typical minimum value of Vee is
about 4.4V. Worst case conditions will result in a
minimum Vee of about 5.3V.
Figure 4 again indicates how to build this same counter
but this time using different segment drivers. In this circuit, the current drive to the LED's is determined by the
external current limiting resistors. Here again the current
to the display is supplied by Vee which can be less than
Vss , again resulting in a power saving and the ability to
drive large LED displays.
In case the impact of this escaped you, let's repeat it:
the circuit in FiguCe 2 demonstrates a 6 decade counter'
and everything that is needed to drive a 6 digit LED
display, yet this circuit requires only two integrated
circuits!
Figure 3 indicates how to build this same counter using
segment drivers. The DM8895 segment driver can be
mask programmed to source several values of current.
Since the values of current that are readily available will
change from time to time, National should be consulted
about the DM8895 before a design using it is undertaken. The general range of currents available is from
5.0 mA up to about 17 mA per segment. This means
that fairly large displays can be used. Noteworthy is the
fact that the current that drives the display in this
configuration is not supplied by the calculator chip.
Instead, this current comes from the Vee supply
terminal of the DM8895. The DM8895 will continue to
SELF STARTING COUNTER
With the addition of only one package of CMOS gates, a
counter can be built that does not require a separate
"start" operation to enter an initial 1 into the calculator
chip; This circuit is shown in Figure 5_ When the RESET
switch is returned to its normal position after clearing
the calculator, the additional parts generate a delayed
pulse that gates digit output 2 into the calculator and
thus enters a 1. This allows the counter to be reset in a
single operation.
Vss
Vee
FIGURE 3. Counter with Segment Drivers
8-165
~
N
-_+4....
Vee - - - _........
OM15491
r--_ _...;1'-1
3 510 1Z
Z
COUNT
FIGURE 4. Counter with Segment Drivers and External Current Limiting Resistors
6.5-9.5V
FIGURE 5. Cou'nter with a Single Clear Switch
6.5 - 9.5V
FIGURE 6. Counter with Increased Speed
8-166
FASTER COUNTING RATES
Figure 6 illustrates how to speed up the circuit shown in
Figure 5 so that it will count at a higher rate. The actual
maximum counting rate attainable with this circuit will
depend on the particular MM5736 used but will run
from about 80 Hz up to about 300 Hz. A reasonably
typical speed is about 120 Hz. This circuit could also be
used with segment drivers as previously described. The
increase in counting rate is obtained by feeding digit
output 6 back to the digit 4 output thereby fooling
some internal logic. However this results in a double
pulse on the digit 4 output which must be gated back to
a single pulse at the normal digit 4 time. This requires
one diode and one additional package of CMOS gates. In
reality, very few relays or switches will operate at these
speeds. Consequently, applications requiring these higher
counting rates may have a normal logic signal'to (,:ount
rather than relay closures. Figure 8 illustrates this. In
this configuration the input must be high at least 4 word
times and the duty cycle cannot exceed 50%. A word
time will vary from 420J,ls to 1.6 ms with 1.0 ms being
typical.
MORE VERSATILITY
These counters can be made to count by numbers other
than 1 by causing the desired number to be entered into
the calculator during the START operation. Table I
indicates which connections must be made. The counters
can also be made to count down by doing successive
subtractions rather than successive additions. Both could
be used to build an up/down counter, the only restriction being that trying to count up and down at the same
time is no fair. Figure 7 shows a circuit that counts up
and down by 4's. Such a counter might be used to keep
track of inventory in a bin. In this case, the parts to be
inventoried are package,d in groups of 4. When a package
is put into the bin, switch S2 is activated and the
counter adds 4 to the accumulated total. When a pack-
age is taken out of the bin, switch S3 is activated and the
counter subtracts 4 from the accumulated total.
RETAINING FULL USE OF THE CALCULATOR
Counters can be built such that full use of the calculator
is retained. This requires that the usual keyboard arrangement of the calculator be undisturbed by the
counting logic. Figure 8 illustrates a circuit that uses
MaS transistors to accomplish this. In this circuit,
normal calculator operation is retained when S2 is in the
"calculate" position since all four MaS transistors
(Ol-04) are "off" {gates are at Ved and the circuit is
essentially the same as the "recommended calculator"
circuit in the MM5736 data sheet. If the,"RESET"
'switch is activated D 1 is connected to K3 and the
calculator is cleared. Capacitors C1 and C2 are discharged while S1 is activated but as soon as S1 is
released C1 and C2 will charge up generating a delayed
pulse (negative going) on the gate of 02 which gates D2
into K1 and causes a 1 to be entered into the calculator.
The delay caused by C1 is necessary to allow the
CLEAR function to be debounced by the calculator chip
as mentioned earlier. When S2 is in the "COUNT" mode
04 is turned on and D6 is tied to D4. This doubles the
max imumcounting rate by reducing the internal
debounce timeout. The count input is now enabled and
an input pulse will turn 01 on. This gates D4 into the
K3 input and causes the calculator to perform an
addition. Each subsequent input pulse causes 1 to be
added to the sum. When S2 is returned to the "calculate" position the count input is disabled and 04
is turned off returning the keyboard logic to its
normal state. This same circuit can be imPlemented
with MM74C02 NOR gates instead of MM74COO
NAND gates. The MaS transistors can then be replaced
with an MM5616 CMOS switch.
6,5-9,SV
FIGURE 7. Up-Down Counter
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SUMMARY
1. The ability to directly drive a LED display.
Many versatile counters can be built using the MM5736
or its 9-digit equivalent. the MM5739. calculator chips.
These counters should yield very cost effective solutions
to a variety of counting applications. The major disadvantage of these counters is that they are relatively
slow. The major advantages these counters offer are:
2. The ability to debounce switch or relay inputs.
3. 6 decades of counting in one DIP.
4. Low cost.
5. Low parts count.
8-168
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CALCULATOR LEARNS TO KEEP TIME
INTRODUCTION
A number of interesting stopwatch and elapsed time
functions can be implemented using the MM5736 calculator chip and a few packages of CMOS gates. This note
describes six different circuits that are intended to
stimulate thinking along these lines. The circuits to be
described are listed below.
In all these circuits, the MM5736 calculator chip is used
in the autosumming mode as a counting and display
element. Application note AN-112 illustrates how to
accomplish this counting. A thorough understanding of
the calculator's operation as a counter can be gained
from AN-112 and the MM5736 data sheet. Consequent·
Iy, the emphasis in this note is on controlling the counter
in such a way that useful timing functions are performed.
1. Stopwatch with 1/10 second resolution
2. Stopwatch with 1/100 second resolution
3. Stopwatch/calculator (1/10 second resolution)
4. Stopwatch/calculator (1/100 second resolution)
5. Stopwatch with 1/10 secs, secs, mins display
6. Interval timer with keyboard and alarm
Two types of timebases are also described. The first, a
CMOS RC oscillator, is depicted in all the circuits described but may not be stable enough for some applications. Consequently, a simple crystal controlled timebase
is also described.
STOPWATCH WITH 0.1 SECOND RESOLUTION
With the exception of circuits 5 and 6 all of these circuits work in decimal fractions of seconds. They do not
display in seconds and minutes. Circuit 6 displays minutes
and tenths of minutes but not seconds. Circuit 5 displays
tenths of seconds, seconds and minutes. It is anticipated
that a number of applications can be satisfied by counting
in only one unit, either seconds or minutes. ,
The circuit in Figure 1 provides the classic stopwatch
functions of:
A)
B)
C)
START
STOP
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FIGURE 1. 1/10 Second Stopwatch
8-169
STOPWATCH WITH 0.01 SECOND RESOLUTION
This implies that timing may continue after it has been
stopped without resetting to zero. The display will be in
tenths of seconds and seconds. Thus, 3 minutes 11 1/2
seconds would be displayed as 191.5 seconds.
Figure 2 depicts a circuit that is identical to the one
shown in Figure 1 except that it has a resolution of
0.01 sec. This means the counter must run at a 100 Hz
rate which is normally beyond the capability of the
MM5736. However, as described in AN·112, a trick can
be played with 06 and 04 that will double the effective
counting rate ofthe calculator. This trick is accomplished
by forcing 04 high during 06 time. SWO is a bilateral
swit~h that connects 06 to 04. CR2keeps 04 off 06.'
SWC is turned off during 06 time so the extra pulse on
the 04 line wiU not get to either the LED display or the
data entry logic.
Circuit Description
The RESET switch simply gates 01 into the K3 input of
the calculator and clears ,it. Upon initial power up it will
be necessary to activate RESET twice. From then on,
only one RESET activation is necessary.
When the COUNT switch is activated, R 1 pulls up
signal X1. This, makes all the inputs to the 3 input gate
high and gates 02 into input K1. This will cause a 1 to
be entered into the calculator. Signal X2 is delayed by
R2 and C1 and will go low about 25 ms after X1
and shut off the 02 pulses being gated into input K1.
About 40ms after this, signal X3 (which is delayed
through R3) goes high and 04 is gated into the K3 input
at a 10 Hz rate. This causes repeated additions and results
in the calculator counting at this rate.When the COUNT
switch (S1) is returned to the STOP position the
additions will be stopped about 60 ms later (after X3
is delayed through R3). This delay hardly seems objec·
tionable since it Is less than the resolution of the counter.
However, purists may feel the addition of CR1 is
necessary. This will cause the,counting to stop imme·
diately after S1 is returned to the STOP position since
C2 will be discharged immediately.
The remainder of the circuit operates exactly like the one
in Figure 1 with the exception that'some of the gating is
implemented with the MM5616 switches.
'STOPWATCH/CALCULATOR WITH 0.1 SECOND
RESOLUTION
Figure 3 depicts a combination stopwatch and calculator.
Stopwatch operation is the same as described earlier
with the foUowing exceptions: Transistors 01 and 02
(which are small GP switches) are used to switch either
02 or 04 to the calculator inputs. This allows the key,·
board and the stopwatch logic to operate in parallel in
what amounts to a "wire OR'ed" arrangement. Also
there is no RESET switch in th is circuit since the
calculator's CLEAR key can be used to reset the time
to zero.
Normal "f~ur function" calculator operation is available
when S1 is in the "CALCU LATE" position.
The LED display shown differs from the NSA 166 only
in the placement of the decimal point.
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STOPWATCH/CALCULATOR WITH 0.01 SECOND
RESOLUTION
6. Enter 1 into calculator
7. Enter + into calculator
8. Resume normal operation
Figure 4 is just a souped up version of Figure 3. It will
count at a 100 Hz rate giving a 0.01 second resolution to
the stopwatch. Switch S2 now needs to be DPDT tYpe.
One pole of the switch provides the start-stop function
and one pole is used to switch in the "speed-up" circuit
involving 04 and 06. The additional gating keeps the
extra pulse from reaching the display and keyboard.
This sequence leaves the calculator properly initialized
with a "1" in it ready for more counting. This would not
be the case if 400 was entered directly rather than as
399 + 1.
Circuit Description
STOPWATCH/CALCULATOR DISPLAYS MINUTES
AND SECONDS
The base 60 conversion is accomplished with a little
controller that switches the Digit outputs to the proper
calculator inputs through some FET switches. The
sequencing it provided by an 8-bit counter and a decoder.
If desired" the circuit could be re-implemented to use
MM5616 quad switches rather than the MM552's shown.
But, since the simplest device that will do this job is a
MOS transistor, it was chosen in this particular case. It
also lends, itself to the negative going outputs of the
MM74C42 decoder.
The conventional time keeping format of minutes and
seconds can be obtained with the additional logic shown
in Figure 5. This circuit provides a display of time up to
999 minutes, 59.9 seconds. But this requires a base sixty
counting capability that is not inherent in the calculator
chip. This conversion is accomplished by recognizing
when the count has gone to 60.0 seconds and then
quickly adding 40.0 to the count, thus giving an apparent
base 60 carry. The sequence of operations required to do
this is:
When the stopwatch is counting normally' (rather than
doing a base 60 conversion) the MSB (0 0 ) of the
sequence counter will be low which inhibits counting. It
also turns on transistor 01 which will allow the counter
to be preset by the output of the gate that decodes a
"6" according to the expression Se • Sb, which is a
simplified version of the seven segment code for "6."
1. Recognize 6 in 3rd digit
2. Enter 3 into calculator
3. Enter 9 into calculator
4. Enter 9 into calculator
5. Enter + into calculator
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Since the counter is clocked by 03, only a 6 in the 3rd
digit will cause the counter to be present. This corresponds to a time of 60.0 seconds and signals the beginning of a base 60 conversion. The counter is preset to
the state 1001 0000. Since the MSB is a 1, the counter's
count enable term is enabled and ·its load term is disabled. It will now count word times on every 03.
Initialization
When Sl is first switched to the stopwatch mode, a burst
of 02 pulses is gated into the Kl input by the one shot
comprised of R2, Cl and the gate that drives 08. This·
enters a "1" to get the calculator ready to count. A little
later, 09 will be turned on by the timebase oscillator at
a 10 Hz rate and counting will begin.
Reference to AN-112 will reveal that with the calculator
"speeded up" it is necessary to allow a digit output to be
connected to the inputs for a minimum of 4 word times
and then there must be at least4 word times during
which nothing is applied to the calculator inputs before
the next entry is allowed. This timing is accomplished by
OD of the low order counter. It toggles with a half
period of 8 word times. This OD is connected to the 0
input of the decoder which is used as an enable input.
When this signal is high, all outputs of the decoder are
high and all the MOS transistors are off. When this signal is low the proper decoder output is low. So the first
4 bits of the counter provide timing and the next 3 bits
provide the necessary sequence of entries. The last bit
turns the sequence on or off. The sequence of entries is
as described earlier and is implemented by transistors
02-07.
Segment Drivers
Two OM8895 segment drivers are used in Figure 5; This
is not absolutely necessary. The calculator can drive
some displays directly. However, it is necessary to buffer
both se'gment e and segment b to preserv'e proper logic
levels for the CMOS decoding gates. This could be done
by non-inverting CMOS buffers like the MM80C96 or2 inverters in series. But if only Se and Sb are buffered, there
is no guarantee of segment intensity uniformity. Therefore, it is more desireable to buffer all segments. The
OM8895 is a segment driver with internal current
limiting resistors that are mask programmable. The
OM75491 could also be used if external resistors are not
objectionable.
8-172
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Circuit Description
Transistors 011 and 010 implement the "speed up"
function, in the same way as that described in Figure 2
except that naked MOS transistors are used in place of
the MM5616 CMOS switch.
As was the case for the stopwatch described in Figure 5,
a small controller made from a counter and a decoder is
used to switch Digit outputs to the proper K input to
create the sequence of entries required. The counter is
clocked by a 30 Hz oscillator whose output is also gated
with all the Digit lines to create the proper "key down"
and "key up" times.
AN INTERVAL TIMER WITH A KEYBOARD
An interval timer that can be programmed to time out
long intervals can also be made using the calCulator chip.
The desired time interval is entered from a keyboard.
When the interval is complete, a tone is' emitted by a
small speaker until the operator activates a RESET
switch. The timer (as described) will handle intervals as
long as 99999.9 minutes, which is about 69 1/2 days.
This is probably too long an interval for an RC oscillator
to be acceptable as a timebase. Figure 6 shows an RC
oscillator but it could be replaced by the crystal oscillator described later in this note. Counting speeds other
than 0.1 minutes could be used as long as the counting
speed of the calculator is not exceeded.
There are two sequences of entries required: one for
RESET and one for START, the beginning of the timing
interval.
Reset Sequence
When the RESET switch is activated, it is debounced by
a latch and differentiated by C1 to generate a positive
going pulse that clears the MM74C193 controller counter
and the sequence proceeds as follows:
1. Reset Latches: The "0" output of the decoder resets
the zero decode latch and the buzzer latch.
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8-173
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FIGURE 6, Interval Timer
2. Clear Calculator
3. Clear Calculator: Both outputs 1 and 2 of the decoder
are "or/ed" and then gated to switch D1 into the K3
input of the Calculator to cause a clear. Two clears
are necessary to insure -that all registers are reset to
zero.
4. Halt: Decoder output 3 forces count enable low and
hangs up the counter.
any time with respect to the 30 Hz clock, it is necessary
to wait until the counter goes to the next count before
trying to enter anything into the calculator. This is
done to insure that a full cycle of the 30 Hz clock
elapses during the time an en~ry is being made. The
sequence then proceeds:
1. Synchronize: Decoder output 4 does nothing but
insure that the first application of signals to the calculator will last for a complete interval.
Start Sequence
2. Add: Decoder output 5 causes D4 to be gated' into
input K3 causing an add. This will enter (in normal
Polish notation) the number already entered from the
keyboard.
Whim the START switch is activated, C2 differentiates
the latch output and generates a negative going pulse that
loads the counter to state 4. Since this can happen at
8-174
3. Enter 1: Decoder output 6 gates D2 into K1 to enter
a 1. This is the number that will be repeatedly sub·
tracted to make the total count down.
4. Add: This simply causes the 1 just lmtered to be
added to the number that was entered from the key·
board. The total will now be one count higher than
desired. Since this would shake up most users, the
next step corrects this.
5. Subtract: Decoder output 8 causes a subtraction
which decrements the display by 1 and brings it back
to the correct reading.
6. Count: Decoder output 9 makes the controller halt
and also turns transistor Q1 off. Q1 was initializing
the timebase oscillator so the timer won't begin to
count down prematurely. D3 is also gated into the
base of Q2 which causes repeated subtractions at the
timebase rate.
oscillator is to control the frequency of oscillation.
Figure 8 depicts a simple and foolproof way to do this.
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FIGURE 8. RC-CMOS Oscillator
The frequency of oscillation will be about f = 0.55/R2 C
if R1 = R2. R2 has the most effect on frequency and in
most applications it would be a pot. Stability of the
oscillator as a function of time is dominated by the
passive elements, especially at frequencies as low as
100 Hz or less. Variations in output drive capability of
the CMOS will be swamped if R2 is 100k or more.
Stability with respect to supply voltage in the range of
voltages that can be used with the calculator chip
(6.5-9.5V) is a function of frequency but the following
is representative:
At this point the timer simply chugs away decrementing
until it reaches zero. Time remaining to zero is continuo
ously displayed. When zero has been detected, the con·
troller's count enable term will go high and it will advance
to state 15 at which time the "carry out" term will go
high and inhibit any further counting. It will stay this
way until the RESET button is activated.
FREQUENCY
VARIATION (6.5-9.5VI
:::::::3%
100 Hz
:::::::0.5%
10 Hz
Zero Decode Logic
Empirically determined temperature drift of this oscilla·
tor due only to the CMOS is:
A zero is detected by recognizing that a blank exists in
digit 2 and a 0 exists in digit 1. A blank is decoded with
the e,xpression Sb + Sc since one of these two segments
is always on when any number is being displayed. When
BLANK' D2 exists, a latch is set. Then when a zero is
detected in digit 1 according to the expression Sf • Sg
the buzz latch is set. This gates D6 into the base of Q3
which turns the speaker on at about a 1 kHz rate with
a 1/6 duty cycle and generates a buzz. The buzz latch
will be reset during the RESET sequence.
FREQUENCY
100 Hz
10 Hz
DRIFT
0.03%tC (-15 ~ +50°C)
0.01%tC
Crystal Oscillator
Figure 9 illustrates how to build a crystal oscillator using
CMOS. This oscillator is also described in AN·118.
OSCILLATORS
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Two CMOS oscillators have been mentioned: one RC
and one crystal controlled. These oscillators are analyzed
elsewhere in National's applications literature (AN·118)
so only a summary is given here.
RC Oscillator
An odd number of inverting gates (NAND, NOR, IN·
VERTERS) will always oscillate if tied around on them·
selves as in Figure 7. Most beginning logic designers have
discovered this fact, of life by accident at one time or
another.
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FIGURE 9. CMOS Crystal Oscillator and Divider for 100 Hz
The CMOS inverter is biased into its linear region by
resistor R 1. This dc path around the inverter ensures that
the oscillator will start. C1 can be used to pull the crystal
down and C2 to pull it up. The output of the oscillator is cleaned up by the next two inverters. This signal
then is divided by 214 or 16384 to yield the 100 Hz
clock needed for the 0.01 second resolution timers.
ANY EVEN NUMBER OF
ADDITIONAL GATES
FIGURE 7. Odd Number of Gates Always Oscillates
Odd Number of Gates Always Oscillates
The 0.1 second resolution timers could be obtained by
using the dividing logic as suggested in Figures 10 and
11. The interval timer could use the 0.1 minute time
base shown in Figure 12.
a
The oscillator will generate' square wave whose fre·
quency will be determined by the propagation delay
through the gates. All that remains to make this a useful
8·175
Cl
II
II
1.6384 MHz
CZ
oH '
II
5M
+10
10 Hz
+16384
Vee
FIGURE 10. Divider for 10 Hz
Cl
II
1.3107ZMHz
CZ
OHI
II
5M
10Hz
FIGURE 11. Alternate Divider for 10 Hz
+16384
-+Z048
1/6 Hz
FIGURE 12. Divider for 1/6 Hz
SUMMARY
parts count solutions to many of these problems. It can
be used in a variety of ways, it interfaces ideally with
the 74C line of CMOS and consumes little power.
A rich variety of timing functions can· be done digitally
and many of these can be implemented with the MM5736
calculator chip. The MM5736 offers six decades of
counting and display in one package and will yield low
8·176
»
Calculators
:2
I
~
CD
HANDHELD CALCULATOR BATTERY SYSTEMS
INTRODUCTION
THE SIMPLEST SYSTEM - A 9 V BATTERY
Batteries suitable for I]andheld calculator applications
can be categorized into two groups: primary cells and
secondary cells. Primary cells cannot be recharged
efficiently or safely and are used in "throwaway"
systems, i.e., the end user must replace the calculator
batteries at end of life. Secondary cells can be recharged
after being discharged under specified conditions.
Most Niltional Semiconductor calculator circuits lise a
P-channel, metal gate MOS process with enhancement
and depletion mode trilllsistors. They are designed to
operate directly from a nine volt illkaline or carbonzinc battery. Operating voltilge range is 6.5 V to 9.5 V.
A nine volt battery is simply six series cells with charilcteristics sinlilar to those shown in Figure 1, allowing an
end-point voltage for each cell of just under 1.1 V for a
worst-case calculator
PRIMARY CELLS
Carbon-zinc and alkaline are the best known nonrechargeable cells available for calculators. Carbon-zinc
cells are low cost, but have relatively high internal
resistance characteristics that reduce efficiency under
high current drain conditions. They. are widely available
ilround the world in il variety of Voltages, capacity, and
form factor options_ AI kal ine cells offer 300 to 400 per
cent more capacity than carbon-zinc batteries of the
same size and have excellent characteristics under the
high drain conditions typical of LED display ciJlculators.
Both types have voltage discharge curves that fall
gradually over life. Shelf life for alkaline is good, carbon'
zinc poor; an i'mportant parameter if batteries ilre to
be shipped with the finished calculator and may sit on
warehouse or display shelves for unknown periods of
time_ Not surprisingly, alkaline cells are also three to
four times more expensive than carbon-zinc. Silver
oxide batteries have been used in throw-away calculator
applications to achieve a more desirable form filctor.
Although replacements are available (the cells are often
used in heari'ng aids and cameras) the high current
drain inefficiency of the cell results in poor utiliziltion
of available capacity, and battery life is short.
A complete calculator using a nine volt battery is shown
in Figure 2. This is undoubtedly the simplest battery
system available for a low cost calculator, as well as
being the most efficient. The current required to drive
the display and MOS circuit carnes directly from the
battery without any conversion of voltage.
Battery life estimates are straightforward. Assuming a
nine digit calculator using the National MM5760 slide
rule chip, and five "S's" as a typical display con:Jition,
it is easy to calculate total battery current drain and
battery life:
r,
I
--...=_
100
Figure 1 indicates the discharge characteristics of carbonzinc, alkaline and nickel-cadmium cells_
1\
,\['-.,
13
~<;---
I
I
t--,~rT
~ (I
\ 1\ NICKEL CADIUM"-
I
DIGITS
OSBB64
I
ISEG ~ Peak Segment Current
~ (Digit Timel (~~~~~~~e~lanking Timel
=~-0.100
650 JJS
.
Therefore, for a display of five "8s:"
IDISPLAY
~(8~e;~ (~:g~~)
~
TIME
(9It~·
I (no. of segments) (no. of digitS) (Digit Duty) +. I
SEG , on per digit
on per word
Cycie
DP
f-f--+-
1~-t--'''k--1-+--I
I
IDISPLAY ~ IsEG(Avel + IDP(Avel
Digit Duty Cycle
: : f-+-t-\t-\-\---'f-+-+
DISPLAY
Referring to Figure 2 and using typical values from the
5760 data sheet,
where
14 \
I
Figure 2. Power Supply Current for 9 V Calculator
I
16
I
(BlllISEG+IDP
1
SECONDARY CELLS
Nickel-cadmium batteries have become the standard for
rechargeable systems. They exhibit relatively constant
discharge voltages and can be recharged many times.
Internal resistance is low so they are capable of supplying high peak currents_
MM5760
VDO SEGMENTS
~
9,
ISS
VSS
(5digitsl (01001
29.75 mA
ISATTERYDRAIN ~ Iss ~ 100 + IDISPLAY
Figure 1_ Comparison of Discharge Characteristics
~
8-177
8,0 mA + 29,8 mA
~
37.8 mA
Battery life is a function of the battery being used, of
course, and its capacity. An alkaline 9 V battery has a
capacity of approximately 550 mA·hr.
.
-Battery Capacity
Battery Life =
IBATTERY DRAIN
IBATTERYDRAIN = (lDD
(lDD
mA.hr
= 550
=,::-:.:.0.:....;:"":':':'
+ IDISPLAY)
(VCONVERTER)
(VBAT) (EFFCONYERTER)
+ IDISPLAY) will be the same as the 9 V case.
Assume the DC-DC .converter has a nominal output
voltage of 8.0 V, and an efficiency of 75%:
37.8 mA
= 14.3 hr, typical
IBATTERYDRAIN
= (37.8 rnA)(~:~~) (O.~5) = 155.1
rnA
As a comparison, a carbon-zinc 9 V battery is rated at
only 125 mA-hr, giving a typical battery life of only
3.24 hr.
If two AA alkaline cells were used, average- battery life
would be (1500 mA-hr/155.1 mAl. or just over 9.6
hours; 500 mA-hr nickel-cadmium batteries would typically give 3.2 hours between ~echarges.
SOMETIMES SIMPLEST ISN'T BEST
In some cases it is not advantageous to design the
cillcuiator with a9 V battery system. If the calculator
is to be marketed in an area of the world where 9 V
replacements are difficult to find, or a unique form
factor is required to optimize overall calculator shape or
size, alternate battery systems may be preferable.
THREE CELLS INCREASE EFFICIENCY
Rechargeable systems are usually more cost effective
as two, three or four cell systems. If it is decided to.
market both throw-away and rechargeable models of
the same calculator, the battery system should allow
the use of all the same hardware in both models; this
means both primary and secondary batteries should be
essentially the same form factor and voltage. N, AA and
AAA cells all meet that requirement, and are often used
in handheld calculators. Alkaline Nand AAA cells are
usually rated around 550 mA-hr and AA at over 1500
mA-hr. Nickel-cadmium cells supply about one third the
capacity of physically equivalent alkaline cells, e.g., AA
nickel-cadmium cells are rated about 500 mA-hr.
Three cell systems provide a significant improvement
in efficiency by reducing the converted power compared
to a two cell system. Three cells have a minimum
operating voltage of roughly 3.3 V. By using a bipolar
segment driver chip to supply the required segment
current at a low Voltage, 'the display current loop can be
separated from the higher-voltage MaS current path and
operated directly off the three cell battery system.
Now the low MaS supply current is the only component
magnified by the _voltage conversion, and the total
power efficiency is greatly enhanced.
Figure 4(a) schematically shows the display interface of
a three cell system, The DS8867 Segment Driver is
guaranteed to supply a minimum of 8 mA of peak
segment current to the LED display at an output
voltage of 2.3 V (or higher) with respect to the negative
terminal of the battery. The 2.3 V must be divided'
between the LED and "ON" digit driver output voltage;
single output transistor (non-darlington) types of bipolar
digit drivers' such as the OS8868, OS8873, OS8973 or
OS8879 have worst-case "ON" voltages of 0.5 V or less.
With both worst-case digit and segment drivers, the LED
will have 2.3 V - 0.5 V = 1.8 V as an "ON" voltage.
GaAsP displays like the NSA 1198 and NSA 1298 show
typical voltage drops of around 1.65 V at 10 mA of
segment current on their data sheets. (If all worst-case
components, including the LED were - combined, a
reduction in peak current could occur at minimum
battery voltage.) For nine digit calculators using the
NSA 1198 and NSA 1298 displays, the minimum peak
current required for reliable operation is 3.0 mA/segment
and 5.0 mA/segment, respectively, well below actual
limits even with worst-case components.
THE ,TWO CELL SYSTEM
Figure 3 shows the MM5760 in a two cell battery
system. All the display and MaS current must be
converted up to the 6.5 V to 9.5 V range needed to
drive the MM5760.
Figure 3. Two Cell Battery System
To guarantee adequate digit output signals for scanning
the keyboard, external series resistors (~ 2.4k) would
be required if OS8873 digit drivers were used rather
than the OS8973. Calculators requiring a shift driver,
such as the MM5784 or MM5791, use a OS8879 digit
driver in three cell systems.
The DC-DC converter must supply greater than Vss 6.5 V with an input voltage range of 2.2 V to 2.5 V for
nickel-cadmium cells or 2.2 V to 3.0 V for alkaline.
Battery drain will be increased due to the voltage
conversion and efficiency of the converter.
8-178
Using three AA alkaline cells woulC! give a battery life of
(1500 mA-hrI100.5 mAl, or almost 15 hours; a 56%
improvement over the two cell system for the additional
cost of the OS8867 and an additional battery. 500 mA/hr
ni-cad cells would provide 5.0 hours of continuous
life. Note that this extended battery life is with higher
display current than the two cell system, which will
result in a brighter display as an added bonus.
_IDISPLAY
FOUR CELL SYSTEM
VBAT +
0 ; ; ; _. . . ._
-+_
.....
A four cell battery system offers even higher power
efficiency than the three cell system and the additional
battery cost is offset somewhat by the removal of the
OS8867. If the OC-OC converter output voltage is
regulated between Vss - 7.5 V and VSS - 9.5 V, segments can be driven directly (Figure 5). Figure 6 shows
the system diagram.
TO ANALDGOUS
SEGMENT OF
OTHER DIGITS
(a)
*MM51l1
MM51l8
MM51J9
MM516D
MM516Z
MM516l
MM5164
MM5161
MM5169
4.0
NSAl198 mon.
Requirement
5.5
4.5
VSAT (,)
Figure 5. Guaranteed Peak Display Current vs. Battery Voltage
in a Four Cell Battery System_
=
VBAT
(ll or (41
(91
KEYBOARD MATRIX
(b)
Figure 4 (a) Schematic Diagram, and (b) Block Diagram
With the exception of the MM5758 which is designed
specifically to operate with a three cell battery system,
all other National Semiconductor single chip calculators
have low impedance segment output buffers suitable
for driving LEOs directly. In a three cell system they
will be capable of over-driving the OS8867_ Typical
input current to the OS8861 is about 1.5 mA per
segment, which unfortunately must be converted up to
the Vss supply and therefore does impact battery life
to some degree.
Figure 6. Four Cell Battery System
Like the three cell system, only the calculator supply
needs to be converted up from the battery voltage.
The display current flows in a loop from the positive
terminal of the batteries, through Vss and the segment
buffers of the calculator chip to the LEO, then the
digit driver and back to the negative side of the batteries.
.'
Typical battery drain for a display of five "8s" in a
three cell system is:
'BAT
~
'BAT '"
![~
'OOMOS
+
mA + (1. 5
(Digit Duty) (
(lSEG ORIVEMOS', Cycle
mAII~1I7~ {3.6~·~. 75' +
no. of \ ]
V CONVERTER
+
(Digit Duty) ( no. of \}
segments on) • VBAT • EFFCONVERTER ISEG BAT' Cycle
. segments on}
{17 mAIlO.; 115 d;,;",
= 100.49 rnA
8-179
(M;rr)}
Battery drain current with five "8s" displayed is:
_
f.
VCONVERTER
)
IBAT - IDDMOS \VBAT • EFFCONVERTER + IDISPLAY
£:: (10 mAl [
1+ (8.5segmA\I (~\
(5 Digits) (0.1)
Digit)
8.75
(4.8) (0.75U
= 54.0 mA
Using four AA cells would give a battery life of at
least (1500 mA·hr/54.0 mAl. or almost 28 hours of
continuous use. Four smaller capacity cells could be
used to improve the form factor of the finished calcula·
tor and still maintain a reasonable battery life. For
example, four alkaline N cells would give almost 10
hours of operation.
Table 1.
Calculator
Type
Segment
Driver
Digit
Driver
2
Group A
None
058872
2.0 V';;; VIN .;;; 3.0 V
6.5 V';;; VOUT .;;; 9.5 V
lOUT';;; -125 mA
9.6 hours
2
Group B
None
058874
2.0 V';;; VIN .;;; 3.0 V
6.5 V';;; VOUT';;; 9.5 V
lOUT';;; -125 mA
7.7 hours
3
Group A
058867
058872
or
058973
3.0 V';;; VIN .;;; 4.5 V
7.2 V';;; VOUT';;; 8.8 V
lOUT';;; 20 mA
15.0 hours
3
Group B
058867
058879
3.0 V ';;;VIN';;; 4.5 V
7.2 V';;; VOUT';;; 8.8 V
lOUT';;; -20 mA
15.0 hours
3
MM5758
058867
058868
3.0V';;;VIN ';;;4.5 V
7.2 V';;; VOUT';;; 8.8 V
lOUT';;; -25 mA
14.5 hours
4
Group A
None
058872
or
058974
4.4 V .;;; V IN .;;; 6.0 V
-7.5 V.';;; VOUT';;; -9.5 V
• lOUT';;; 20 mA'
28.0 hours
4
Group B
None
058876
4.4 V .;;; V IN .;;; 6.0 V
-7.5 V';;; VOUT';;; -9.5 V
lOUT';;; 20 mA
23.5 hours
9V
Group A
None
058873
or
058864
None
14.0 hours
9V
Group B
None
058874
None
11.3 hours
r
Group B Calculators
Group A Calculators
MM5737
MM5738
MM5739
MM5760
DC· DC
Converter
Typical Battery Life
with AA Alkaline Cells
No. of
Battery Cells
MM5784
MM5791
MM5762
MM5763
MM5764
MM5767
MM5769
8·180
Calculators
l>
Z
I
~
-..J
0')
USING STANDARD NATIONAL CALCULATORS
IN INDUSTRIAL AND MICROPROCESSOR APPLICATIONS
It is frequently desirable to utilize a calculator component
in non-calculator applications. Because of their low cost,
these devices represent a cost effective method of
sophisticated number processing. A few hints that are
worthwhile to keep in mind when applying calculators
are listed below.
Ready remains at a low level until the function initiated
by the key is complete and the key is released and timed
out. The low-to-high transition indicates the calculator
has returned to the "idle" state and a new key can be
entered. Figure 1 shows the relationship between keyboard entries and Ready.
KEYBOUNCE AND NOISE REJECTION
Ready can be very helpful in a non-calculator application. It can be used in the following manner:
1) Whenever Ready is at a logic high, enter keys.
2) Whenever Ready is at a logic low, inhibit all keys and
wait.
3) The transition from low to high indicates that an
external machine can change states. Also, after a
period of time, the display is valid and can be
sampled.
The National line of calculators are designed to interface
with low-cost keyboards, which are often the least
desirable from a false or multiple entry standpoint.
When a key closure is sensed by the calculator, an
internal time-out is started. Any voltage perturbations of
significant magnitude which occur on the Key Input
Lines during the time-out will reset the timer to zero.
A key is accepted as val id only after a noise-free
time-out period: noise that persists indefinitely will
inhibit key entry. Key releases are checked in the same
manner.
ZERO SUPPRESSION
All calculators have some form of zero suppression.
For left-justified displays, it is trailing zero suppression
which is relatively easy to implement and fast. Rightjustified displays require leading zero suppression. While
this doesn't require much more logic, it is much slower.
This can play an important role in using a calculator
which must transfer results to other logic elements.
After Ready goes high, it can take up to 7 word times
before the segment information is correct. Consult
Table I for specifics.
READY SIGNAL OPERATION
The Ready signal indicates calculator status. When the
calculator is in an "idle" state, the output is at a logical
high level (near VSS). When a key is closed, the internal
key entry timer is started. Ready remains high until the
time-out is complete and the key entry is accepted as
valid. As the calculator begins to process the key, Ready
goes low (near VOO).
Figure 2 illustrates circuits for accomplishing the speed-
ups given in Table I.
04
06
9V
1/2 C04016
NEW KEY IS
DEPRESSjD
KEY IS
RELEASED
[ - - N WORD T I M E S - - - - I
(
'"''''''"ru-u~"'" "-",,,
""",./ - :f{(l~~\~: ~
IS COMPLETED,
WHICHEVER IS
LONGER
REAOY-------.'----.I
I
--_1-1
I!-
NEW KEY HAS BEEN
ACCEPTEO BY CALCULATOR
THE KEY MAY BE RElEASEO
TO KEYBOARD
AND OISPLAY
If the inverter is unavailable, a CD4016
and resistor suffice.
04
06
9V
NEXT KEY
CAN BE ENTEREO
FIGURE .1. Functional Description of Ready Signal and Key Entry
TO KEYBOARO
ANO DISPLAY
FIGURE 2. Calculator Speed Up Circuits
8-181
In many cases, a calculator circuit can be applied in a
microprocessor system to eliminate the necessity of
writing extensive floating point software routines.
Figure 3 shows such a system developed for a SC/MP
microprocessor. Due to variations in power supply
voltages and logic levels between SC/MP and the MM5760
Mathematician calculator, a combination of CMOS and
low power Schottky components has been used. The
MM5760 was chosen for this particular application
because 3 other pin compatible calculators, the MM5762,
MM5763 and MM5764 (Statistical, Financial and Metric
Conversion) calculators will fit into the same socket and
provide different algorithms.
Table II describes these functions and the codes that
the SC/MP must present to the input register. SC/MP
may operate either in an interrupt driven mode or
through the use of the sense input. When programming
the SC/MP calculator systems, it is advisable to perform
the functions in the same manner as one would when
operating the corresponding Novus or National Semiconductor calculator.
TABLE I
CALCULATOR
NORMAL KEV
BOUNCE TIME
DEFEATED KEV
BOUNCE TIME
HOW TO DEFEAT
KEVBOUNCE
READV
DISPLAV CORRECT
FOLLOWING
READV PLUS
POWER ON
CLEAR
LONG CAL
WHEN CAN SEGMENTS
BE SAMPLED
MM5736. MM5749
MM5757
7-8 words
3-4 words
04 high during 06
No
No
220ms
Middle of digits
MM5737
7-8 words
3-4 words
07 high during 09
Yes
7 words
No
350ms
Trailing edge of digits
7 words
No
350ms
Trailing edge of digits
No
300ms
Middle of digits
Yes
3.1 sec
Middle of digits
Yes
3 sec
Middle of digits
Yes
40ms
MM5738
7-8 words
3-4 words
07 high during 09
Yes
MM5739
7-8 words
3-4 words
04 high during 09
No
MM57S8
7 words
4 words
TC high during 03
Yes
same
none
Yes
MM5760, MM5762,
MM5763, MM5764
9 words down,
16 words up
MM5765
Uses ready
MM5766
Uses ready
MM5780
7-8 words
3-4 words
07 high during 09
Yes
o words
o words
o words
Yes
40ms
No
350 rns
Middle of digits
MM5784
7--8 words
3-4 words
Conn"ct K2 to 09
Yes
7 words
Yes
580ms
MM5791
11 words
2 words
Connect K2 to 09
Yes
7 words
Yes
580ms
Middle of digits
MM5777
7-8 words
3-4 words
06 high during 07
Yes
5 words
No
300ms
Trailing edge of digits
TABLE II
CONTROL BYTE
(H EXI DECIMAL)
00-08
MM5762
MM5763
MM5764
-
-
-
+
+
+
14
X*
X
X
X
15
16
TAN
17
18
12
13
Freq*
KS*
JAL *
x:
Ft-in
SIN
LOAN*
COR
In-mm
COS
SAV*
INT
IN-em
mile-km
20
l/X
eX
SOD
j*
Ex
21·
REMy
Ft-m
22
yx
AMT
y
23
LOG
-
X
24
Ln
25
Vx*
M+
MR*
MC
yd-m
M+*
MR*
=*
yX
REMx
26
STO*
M+
MR*
27
C
C
41
EN
=
C
=
42
RCL
=+
=+
=+
43
44
.
.
.
.
45
9
9
9
9*
46
8
8
8
.8*
47
7
7
7
7*
48
6
6
6
6*
80
5
5
5
5*
81
4
4
4
4*
82
3
3
3
3*
83
2
2
2
2*
84
1
'0
1
1
0
l'
O·
CA'
-
%
%*
85
.to
MM5760
- *
+*
.*
11
-
FUNCTION
OUTPUT SELECT FOR DIGITS 1-9
k
CS
86
ARC*
0
n*
87
CS
%
CS
*Multiple function key-refer to individual data sheets
8-182
C
CS*
*
»
2
CONT
, FLAG -~--~~
SENSE
liZ DM74LSOI
HALT
- - - - - - + - - - - - - -....
VSS
1/6DM74LS04
ROY
01
02
9
VCC Ell
DBJ
D4
'DB2
DJ
DBI
D2
DBO
01
MM5760
7
CLR
03
04
DM74LS17J
04
03
02
05
01
06
07
DB
09
":'
~-----------------------------------~~---~VY---VCC
Vee = 5V
VSS ':' 8V
All resistors 5.1 k
RA15-5.1KN
RA07-5.1KN
HARDWIRED ADDRESS
LOCATION UPPER
6·BITS
ADDRESS
BUS
HARDWIRED ADDRESS
LOCATION LOWER
6·BITS
FIGURE 3. MM5760 Se/MP Interface
Operation of the circuit is' straight forward; when the
8-bit control word is applied to the input register, a
9-bit multiplexer is addressed by the lower 4 bits,
selecting a digit line. The upper 4 bits then gate the
digit output through to the key inputs; the Ready
line clears the input register and indicates acceptance
to the processor. When the Ready line returns to its
original state, another command may be entered. To
receive the output of the calculator, the processor
should load the lower 4 digits of the input register
with the code corresponding to the digits required and
the upper 4 digits with zeroes-the multiplexer output
signal then indicates availability of data.
In an SC/MP system, synchronization with data is accomplished by first loading the digit code as described and
8-183
U)
~
o
U)
U)
Q)
(.)
o
~
0-
National's Controller Oriented Processor Systems
"0
....c:Q)
Q)
''::
o
introduction
COPS elements
National's Controller Oriented Processor Systems provide
a low cost solution to low end computing and control
problems. Manufactured by NSC's volume proven
P-channel MOS/LSI controller process, the COPS offers
an attractive, low risk alternative to custom LSI when
available development time is short and cost is critical.
Single mask programming of the on-chip control ROM
allows delivery of prototype devices directly from the
calculator production lines.
•
Automobile displays
•
Oven controllers
•. Vending machines
Architectural features of the COPS permit rapid efficient
design and implementation of systems using key or
switch inputs and display or printer outputs. Interface
circuits in the COPS are designed to allow expansion of
system memory and I/O capability without sacrificing
the "lowest component count" features of the set_
•
Specialty calculators
•
Simple electronic cash registers
•
Computing instruments
•
Electronic scales
•
Printer/display controller
•
Appliance controller
Elements in the COPS family provide four levels of
processing capabil ity from the dedicated MM57140
single chip system with direct display and keyboard
interface to the highly flexible MM5782 based multichip systems.
•
Data terminal controller
•
Automated gasoline pumps
•
Alpha/numeric programmable calculators
features
applications
•
National's COPS feature P-channel metal gate process
for lowest cost
•
Single power supply operation
•
•
CMOS compatibility
Serial I/O ports for easy communication between
processor and peripheral circuits
MM5781
MM57129
MM5782
MM5785
•
•
Expandable RAM and ROM
BCD in/out option for applications flexibility
•
Direct interfacing to keyboard and display
•
10
•
4-bit data/8-bit instruction word
•
Single mask programmable
•
Learn mode programmability
flS
MM5788
MM5799
MM57140
DS8664/5/6
DS8692
DS8693
MM57126
instruction cycle
9-2
16k control and ROM element
32k control and ROM element
Memory and processor element
Memory interface to 1024 x 1 RAM
devices
Printer interf~ce to Seiko printers
Single chip microcomputer
Single chip microcomputer
Decoder, digit driver and oscillator
Hex power driver (single)
8-bit latch and driver (source)
Programmer shift register
COPS
MM5781, MM5782 Controller Oriented Processor Systems
general description
features
The National MM5781, MM5782 is a set of MOS/LSI
circuits designed for application in low cost, versatile,
dedicated or custom programmed calculator and control
systems.
• 2048 x 8-bit ROM, expandable to 8192 x 8
• 640 bits (160 digits) RAM, expandable using MM5785
• 8 parallel outputs, coded as 7-segment + d_p. or
BCD
• Serial data I/O for easy interface to peripheral circuits
• 3 general purpose I/O latches
a Blanking output
•. 4 strobed key inputs
• lOps micro-instruction cycle time
• Single power supply operation
• 4-bit data/8-bit instruction words
A full capability scientific or business calculator system
can be built using only four circuits, plus the keyboard,
case, battery and LED display. Application as a printing
calculator or in electronic cash registers is possible using
National's MM5788 printer interface circuit. Both the
basic ROM instruction store and read/write store are
expandable.
connection diagrams
Dual·ln·Line Package
Dual-I n-Line Package
VOO
IRB
12
SYNC
13
OSC
14
Kl
15
K2
17
16
15
F2
14
F3
13
VSS
001
002
12
003
13
004
14
NC
15
SI
16
16
17
17
MM5782
K3
Fl
27
11
MMS781
K4
28
VOO
11
OIl
18
18
SKIP
SYNC
Sc
OSC
Sd
SKIP
Se
TEST
INB
Sp
F4/BLK
VSS
TOP VIEW
TOP VIEW
Order Number MM5782N
See Package 23
Order Number MM5781 N
See Package 22
9-3
absolute maximum ratings
Voltage at Any Pin Relative to VSS
(All Other Pins Connected to VSS)
Vss +0.3V to VSS -12V
Ambient Operating Temperature
O°C to +70°C
Ambient Storage Temperature
-55°C to +125°C
Lead Temperature (Soldering, 10 seconds)
300°C
dc electrical characteristics
(DOC to +70°C unless otherwise noted)
PARAMETER
CONDITIONS
Operating Voltage (VSS - VOO)
Operating Supply Current (I DO)
MIN
TYP
MAX
9.5
7.9
UNITS
V
VSS - VOO = 9.5V, TA = 25°C
MM5781
-7
-12
mA
MM5782
-15
-25
mA
OSC Input Voltage Levels
Logical High Level (VIH)
VSS-- VOO = 7.9V
Logical Low Level (VIU
' VSS - VOO = 9.5V
OSC Input ResLstance to VSS
V
VSS-1.0
VOO+1.5
V
(Note 3). (Figure 2)
MM5781 Only (R IN)
3
6
kD.
INB, K1-K4, F1-F3 Input
Voltage Levels
Logical High Level (VIH)
Logical Low Level (VIL)
VSS - VOO = 7.9V
VSS-3.2
VSS - VOO = 9.5V
VSS-4.5
7.9V ~ VSS - VOO ~ 9.5V
V
V
VOO+1.5
V
INB, K1-K4 Input Current Levels
Logical High Level Current (lIH)
VIH = VSS - 3.2V
-350
J1A
1
J1A
(LED Display Interface)
Logical Low Level Current (IlL)
-20
VIL = VSS - 32V
(Fluorescent Display Interface)
IRB Input Voltage Levels
/'
Logical High Level (VIH)
7.9V ~VSS-'-VOO~9.5V
Logical Low Level (V I L)
VSS - VOO = 7.9V
VOO+2.5
V
VSS - VOO = 9.5V
VOO+3.0
" V
11-18, SI, SKIP, SYNC and TEST
VSS-3.5
V
VSS - VOO = 7.9V
Input Voltage Levels
Logical High Level (VIH)
V
VSS-1.2
Logical Low Level (V I U
VSS-4.0
V
VSS-1.0
VSS
V
VOO
VOO+O.5
DO 1, DO 2 and DO 4 Output
Voltage Levels
Logical High Level (VOH)
RL = 150k, to VOO
Logical Low Level (VOL)
10L = 3J1A
Logical High Level Current UOH)
VOH = VOO + 1.5V,
VSS- VOO= 7.9V
.9-4
-260
V
J1A
dc electrical characteristics (can't)
(O°C to +70°C unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DO 3 Output Voltage Levels
Logical High Level (VOH)
RL>= 150k, to VOO
Logical Low Level (VOL)
10L = 3J-lA
Logical High Level Current (I OH)
VSS-1.0
VSS
V
VOO
VOO+0.5
V
Battery Low "OFF"
VOH = VOO + 3V, VSS - VOO =
-1.3
-{).3
rnA
-1.0
-{),4
rnA
-{).3
rnA
-(),4
rnA
-500
J-lA
1
J-lA
-300
J-lA
9.5V
VOH '" VOO + 2.5V, VSS - VOO =
7.9V
Battery Low "ON"
VOH = VSS - 3V, VSS - VOO =
7.9V
VOH = VSS - 3V, VSS - VOO =
9.5V
Sa through Sg and Sp Output Current
LED
~isplay
Interface to OS8867
Levels
Logical High Level Current (IOH)
VOH ='VOO + 5,4V
Logical Low Level Current (IOL)
VOL = VOO + 0.5V
-1
Fluorescent Display Interface
Logical High Level Current (lOH)
VSS - VOO = 7.9V, VOH =
VSS - 6V
Logical Low Level Current (IOL)
VOL = VSS - 32V, REXT = 150k
-20
J-lA
to VGG = VSS - 35V
11 - 18, SO, SYNC and SKIP Output
VSS - VOO = 7.9V
Voltage Levels
Logical High Level (VOH)
10H = -1 oOJ-l A
Logical Low Level (VoLl
10L = 15J-lA
F1 - F3 Output Voltage Levels
VSS
V
VOO
VOO+3.7
V
7.9V ~ V~S - VOO ~ 9.5V
Logical High Level (VOH)
10H = -30J-lA
Logical Low Level (VOL)
10L = 3J-lA
F4 (B LK) Output Voltage Levels
VSS-0.5
V
VSS-1.5
VOO+1.0
V
7.9V ~ VSS - VOO ~ 9.5V
Logical High Level (VOH)
10H = -0.5 rnA
L-ogical Low Level (VOL)
10L = 5J-lA
V
VSS-1.5
VOO+1.0
V
VSS-0.5
VSS
V
VOO
VOO+0.5
V
Voltage Levels for All Outputs into
CMOS Level
Logical High Level (VOH)
10H = -10J-lA
Logical Low Level (VoLl
RL = 200k (to VOO)
Maximum Allowable Keyboard
Closed Key Resistance Using INB,
F 1-F3 or K 1-K4 as Inputs
~isplay
RKEY
LED
RKEY
Fluorescent Display Interface
Interface
. 9·5
200
50
n
kn
s:
s:U'I
.....
co
N
ac electrical characteristics
MM5781 - o°c to +70°C, unless otherwise noted(Figure 1)
PARAMETER
CONDITIONS
MIN
OSC Input Frequency (l/tp)
320
-OSC Input Duty Cycle
46
OSC Input Transition Times
TYP
56
MAX
UNITS
400
kHz
66
%
(Note 3), (Figure 2)
Fall Time (tt)
CL; 25 pF, RL; 6 kn, to VSS
Rise Time (t r )
RC;
0.15~s
50
ns
350
ns
12.5
~s
SYNC Input Timing (Bit Time)
Interval Time (tb)
10
Hold Time (tos ch)
High·to·Low Set· Up Time (tstl)
100
680
ns
Low·to·High Set·Up Time (tsth)
100
ns
Set-Up Time (tsk)
6.5
~s
Hold Time (thk)
1.0
~s
ns
Kl - K4, INB, Fl - F3 Input
Timing
SKIP Input Timing
Set-Up Time (t sx )
Hold Time (thx)
280
ns
1.0
~s
Set-Up Time (tsi)
1.75
~s
Hold Time (thi)
1.0
IRB, 11 -IB Input Timing
SKIP Output Propagation Delay (tpdx)
CLOAD = 250 pF
11 - IB Ou~put Propagation Delays
CLOAD = 250 pF
~s
4.4
~s
Low-to-High (tpdhi)
3.6
~s
High-to-Low (tpdli)
3.0
~s
CLOAD = 100 pF
4.4
~s
CLOAD = 50 pF
4.4
~s
Fl - F3 Output Propagation Delay
(tpdt)
F4 Output Propagation Delay (tpdt)
F4 Output Transition Time
Rise Time (t r )
CLOAD ~20 pF
timing diagram If~~t ~s in!..i ure2.1
g
"" ' '=V,L
Ii\
I---
~
I.sch-
~/-i
0.3
~""---rt~IP-,---12-n.J\
_
n
- -1 "" -
VOL
\0:\
'"
SKtP VOH
VOL
I--
IOs
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