1977_PMI_Linear_and_Conversion_IC_Products 1977 PMI Linear And Conversion IC Products
User Manual: 1977_PMI_Linear_and_Conversion_IC_Products
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INTRODUCTION
This catalog contains complete technical data and information on Precision Monolithics' full line of linear and conversion
products. In addition to data sheets, an expanded applications section, guaranteed chip specifications section, cross references,
functional replacement guides, selection guides, package information, and definitions are provided.
Precision Monolithics' continued dedication to providing state-of-the-art products has resulted in 16 new products since the
previous edition. New products include 11 operational amplifiers, 4 D/A converters, and BIFET analog multiplexers. There
are 3 second-source BIFET op amps, 3 Precision BIFET op amps, 2 precision low power op amps, and both second-source and
precision quad op amps. New D/A converters include Sign Plus 10 Bits, Two's Complement 10 Bit, 2-Digit BCD and 12 Bit
mUltiplying types. A similar increase in new products is expected in the coming year. To keep informed, please fill out the
Registration Card at the back of this catalog and return it to PMI, and we will send all new data sheets and application notes
as they become available.
Contact the PMI sales office, representative, or distributor listed at the back of this catalog for further assistance.
Copyright 1977
Precision Monolithics Incorporated
PMI reserves the right to make changes to the products contained .in this catalog to improve performance,
reliability, or manufacturability.
Although every effort has been made to insure accuracy of the information contained in this catalog, PMI
assumes no responsibility for inadvertent errors.
PMI assume~ no responsibility for the use of any circuits described herein and makes no representation that,
they are free of patent infringement.
'
A ~ Subsidiary
NUMERICAL INDEX
IORDERING INFORMATION
I
I
I
I
QA. PROGRAM
INDUSTRY CROSS REFERENCE
FUNCTIONAL REPLACEMENT GUIDE
OPERATIONAL AMPLIFIERS
COMPARATORS
MATCHED TRANSISTORS
VOLTAGE REFERENCES
D/A CONVERTERS - LINEAR
D/A CONVERTERS - COMPANDING
MULTIPLEXERS;
DEFINITIONS
I
CHIPS
I
APPLICATION NOTES
I
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I'NOTES
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PACKAGE INFORMATION
INDEX
SECTION 2
ORDERING INFORMATION
2·1
SECTION 3
3-1
Q.A. PROGRAM
SECTION 4
INDUSTRY CROSS REFERENCE
Fairchild.
National Semiconductor
Raytheon
Texas Instruments
.
4·1
4·2
4·3
4·3
Advanced Micro Devices
44
RCA .
Motorola
4-6
4·5
SECTION 5
FUNCTIONAL REPLACEMENT GUIDE
Analog Devices
Burr Brown
.
.
Harris Sem iconductor
National Semiconductor
Cross Reference - MAT'()l to Monolithic Dual Transistors
Cross Reference - MAT·01 to 2N Types
5·1
5·1
5·2
5·2
5·3
54
SECTION 6
OPERATIONAL AMPLIFIERS
SELECTION GUIDES
Single BiFet Operational Amplifier
Single Low Power Operational Amplifier
Single Precision Operational Amplifier
Single General Purpose Operational Amplifier
Dual Precision Operational Amplifier
Dual General Purpose Operational Amplifier
Quad Operational Amplifier
OP·Ol
Inverting High Speed Operational Amplifier.
OP'()2
High Performance General Purpose Operational Amplifier
OP'()4
Dual Matched High Performance Operational Amplifier
OP'()5
Instrumentation Operational Amplifier .
OP·07
Ultra·Low Offset Voltage Operational Amplifier
OP.()8
Precision Low Input Current Operational Amplifier
OP.()9
Quad Matched 741·Type Operational Amplifier
OP·l0
Dual Matched Instrumentation Operational Amplifier
OP·ll
Quad Matched 741·Type Operational Amplifier
OP·12
Precision Low Input Current Operational Amplifier
Dual Matched High Performance Operational Amplifier
OP·14
Precision JF ET Input Operational Amplifier
OP·15
Precision JFET Input Operational Amplifier
OP·16
Precision JF ET Input Operational Amplifier
OP·17
Instrumentation Operatio~al Amplifier .
S5S725
555741
Compensated Operational Amplifier .
Dual Compensated Operational Amplifier
SSS747
5551458/1558 Dual Compensated Operational Amplifier
PM·l08A
Low Input Current Operational Amplifier
PM155
Monolithic JF ET Input Operational Amplifier
PM156
Monolithic JFET Input Operational Amplifier
Monolithic JFET Input Operational Amplifier
PM157
Instrumentation Operational Amplifier .
PM725
PM·741
Compensated Operational Amplifier .
PM·747
Dual Compensated Operational Amplifier
PM·1458/1558 Dual Comepnsated Operational Amplifier
PM4136
Quad 741·Type Operational Amplifier
6·1
6·3
6-6
6·7
6-9
6·11
6·13
6·16
6·19
6·25
6·31
6·37
643
6-60
6-66
6-66
6·72
6·78
6-84
6·90
6·96
6·101
6·108
6·111
6·114
6·116
6·119
6·123
6·127
6·131
6·133
6·135
6·137
6·139
SECTION 7
COMPARATORS
CMP-Ol Fast Precision Comparator
CMP-02 Low Input Current Precision Comparator
7-1
7-7
SECTION 8
MATCHED TRANSISTORS
MAT -01 Ultra-Matched Monolithic Dual Transistor
8-1
SECTION 9
VOLTAGE REFERENCE
REF-Ol +10V Precision Voltage Reference
REF-02 +5V Precision Voltage Reference
9-1
9-8
SECTION 10
D/A CONVERTERS - LINEAR
Selection Guide
6 8it Monolithic D/A Con;"'rter
10 8it Plus Sign Monolithic D/A Converter
8 & 10 Bit Low Cost Monolithic D/A Converter
Two's Complement 10 Bit D/A Converter
11 Bit D/A Converter .
Two's Complement 10 Bit D/A Converter
8 Bit High Speed Multiplying D/A Converter
2 Digit BCD High Speed Multiplying D/A Converter
8 & 10 8it Digital-to-Analog Converter
12 Bit Multiplying D/A Converter
8 8it Multiplying D/A Converter .
DAC-Ol
DAC-02
DAC-03
DAC-04
DAC-05
DAC-06
DAC-OB
DAC-20
DAC-l00
SSS562
SSS1508A/1408A
10-1
10-3
10-6
10-9
10-12
10-16
10-20
10-24
10-34
10-42
10-48
10-51
SECTION 11
D/A CONVERTERS - COMPANDING
™ Companding D/A Converter
DAC-76 COMDAC
11-1
SECTION 12
MULTIPLEXERS
MUX-88 Protected 8 Channel BI-FET Analog Multiplexer
12-1
SECTION 13
DEFINITIONS
13-1
SECTION 14
MONOLITHIC CHIPS
General Description
Triple Passivation
Quality Assurance .
Ordering Information
Mechanical Information
Testing
Assembly Procedures
Assembly Specification A0018A
14-1
14-1
14-1
14-1
14-2
14-2
14-2
14-3
Precision Comparators
CMP-Ol Fast Precision Comparator
CMP-02 Low Input Current Precision Comparator
D/A Converters - Linear
DAC-Ol 6-8it Monolithic D/A Converter
DAC-02 10-8it Plus Sign D/A Converter.
DAC-04 Two's Complement 10-8it D/A Converter.
DAC-08 8-Bit High Speed Multiplying D/A Converter
DAC-20 2-Digit BCD High Speed Multiplying DAC
140BA 8-Bit High Speed Multiplying D/A Converter
DAC-l00 8- & 10-8it Two Chip D/A Converter
DAI-Ol 1O-B it D/A Current Source With Reference
DAR-Ol 10-Bit Resistor Network.
D/A Converters - Companding
DAC-76 COMDAC
Companding D/A Converter
Matched Transistors
MAT-01 Ultra-Matched Monolithic Dual Transistor
™
14-6
14-7
14-8
14-9
14-10
14-11
14-12
14-13
14-14
14-15
14-16
14-17
•
Precision Operational Amplifiers
OP·01 High Speed Operational Amplifier
OP-02 Compensated Operational Amplifier
OP.()4 Dual Operational Amplif.ier
OP-05 Compensated Instrumentation Op Amp
OP-07 Ultra·Low Offset Voltage Op Amp
, OP-08 Precision Low Input Current Operational Amplifier
OP.()9 Quad Operational Amplifier
OP·ll Quad Operational Amplifier
OP·12 Precision Low Input Current Operational Amplifier
OP·14 Dual Operational Amplifier
OP·15 Precision Low Power JFET Input Operational Amplifier
OP·16 Wide Bandwidth Precision JFET Input Operational Amplifier
OP·17 Precision JFET Input Operational Amplifier
108 Low Input Current Operational Amplifier
155 Low Power JFET Input Op Amp
156 Wide Bandwidth JFET InputOp Amp .
157 JFET Input Operational Amplifier .
725 Instrumentation Operational Amplifier.
4136 Quad Operational Amplifier
Precision Voltage References
REF·Ol +10V Precision Voltage Reference
REF-02 +5V Precision Voltage Reference/Thermometer
14-18
14-19
14-20
14-21
14-22
14-23
14-24
14-25
14-26
14-27
14·28
14-29
14-30
14·31
14-32
14-33
14-34
14-35
14-36
14-37
14-38
SECTION 15
APPLICATION NOTES
AB-l
AB-2
AB·3
AB4
AN-6
AN-l0
AN-II
AN-12
AN-13
AN·14
AN-15
AN·16
AN-17
AN-18
AN·19
AN·20
AN-21
AN·22
AN-23
AN·24
Strobing the DAC-08 Under Logic Control
OP-l0 Instrumentation Amplifier CMRR Versus Frequency Improvement
Digital Nulling of OP-05 and SSS725 .
REF-02 Temperature Controller •
A Low Cost, High Performance Tracking A/D Converter
Simple Precision Millivolt Reference Uses No Zeners
A Low Cost, Easy-to-8uild Successive Approximation Analog-to-Digital Converter
Temperature Measurement Method Based on Matched Transistor Pair Requires No Reference
The OP-07 Ultra-Low Offset Voltage Op Amp
A Bipolar Op Amp That Challenges Choppers, Eliminates Nulling
Interfacing Precision Monolithics Digital-to-Analog Converters With CMOS Logic
Minimization of Noise in Operational Amplifier Applications.
Low Cost, High Speed Analog-to·Digital Conversion with the DAC-08
DAC-08 Applications Collection .
Thermometer Applications of the REF-02 .
Differential and Multiplying Digital·to·Analog Converter Applications
Exponential Digitally Controlled Oscillator Using DAC-76
3 IC 8 Bit Binary Digital to Process Current Converter with 4-20 MA Output
Software Controlled Analog·to-Digital Conversion Using DAC-08 and the 8080A Microprocessor
Digital-to-Analog Converter Generators Hyperbolic Functions
The OP-17, OP-16, OP-15 as Output Amplifiers for High Speed D/A Converters
15-t
15-2
15-3
154
15-5
15-11
15-12
15-19
15-25
15-38
15-40
15-50
15-57
15-68
15-71
15-79
15-82
15-84
15-88
15-91
SECTION 16
PACKAGE INFORMATION
16-1
SECTION 17
NORTH AMERICAN REPRESENTATIVES
INTERNATIONAL REPRESENTATIVES •
REGISTRATION CARD/CHANGE OF ADDRESS CARD
NOTES •
NORTH AMERICAN DISTRIBUTOR LOCATIONS
17-1
17-3
17·4
17-5
I
NUMERICAL INDEX
ORDERING INFORMATION
Il a.A • PROGRAM
IINDUSTRV CROSS REFERENCE
I
FUNCTIONAL REPLACEMENT GUIDE
I OPERATIONAL AMPLIFIERS
I
I
COMPARATORS
MATCHED TRANSISTORS
IVOLTAGE REFERENCES
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lOlA CONVERTERS - LINEAR
[iQ]
lOlA CONVERTERS - COMPANDING
[TIJ
I
I
MULTIPLEXERS
DEFINITIONS
I
CHIPS
I
APPLICATION NOTES
IPACKAGE INFORMATION
I
NOTES
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I1ZJ
ORDERING INFORMATION
Proprietary and second source products are available with a choice of electrical specifications, packages and operating
temperature ranges. ~his section explains the PM I part numbering system. For specific ordering information such as available
electrical grade and package combinations, see the specific product data sheet.
ELECTRICAL GRADE
MODEL FAMILY
I
XXXX
CMP
DAC
MAT
OP
PM
REF
SSS
PACKAGE SUFFIX
\X
X
---------
= Precision Voltage Comparator
=Digital to Analog Converter
= Matched Transistors
= Proprietary Operational Amplifier
= Second Source - Industry Standard Specs
= Precision Voltage Reference
= Superior Second Source - Improved Specs
TYPE PREFIX
I
XXX
MODEL FAMILY
ELECTRICAL GRADE
~X
I
XXXX
PACKAGE SUFFIX
EXAMPLES
OPERATIONAL AMPLIFIERS
OP-01
OP-02
OP-04
OP-05
OP-07
OP-10
OP-14
SSS725
SSS741
SSS747
SSS1408
SSS1458
PM108
PM725
PM741
PM747
PM1458
= High Speed Inverting
= Precision Low Cost
= Precision Low Cost Matched Dual
= Precision Low Drift
= Precision Low Offset Voltage
= Precision Matched Dual
= Precision Low Cost Matched Dual
= Improved Instrumentation Op Amp
= Improved General Purpose Op Amp
= Improved General Purpose Dual Op Amp
= Improved 8-Bit D/A Converter
= Improved General Purpose Dual Op Amp
= Low Current Op Amp
= Instrumentation Op Amp
= General Purpose Op Amp
= General Purpose Dual Op Amp
= General Purpose Dual Op Amp
COMPARATORS
CMP-01
CMP-02
= High Speed
= Low Input Current
D/A CONVERTERS
DAC-01
DAC-02
DAC-03
DAC-04
DAC-08
DAC-76
DAC-100
= 6 Bit Voltage Output
= 10 Bit + Sign Voltage Output
= 10 Bit Low Cost Voltage Output
= 10 Bit Two's Complement
= 8 Bit Universal High Speed
= 8 Bit Companding
= 10 Bit Current Output
VOLTAGE REFERENCES
REF-01
REF-02
= +10V Adjustable
= +5V Adjustable
MATCHED TRANSISTORS
MAT-01
= Ultra-matched Monolithic Transistors
2-1
\X
ORDERING INFORMATION
MODEL FAMILY ~AL GRADE*
TYPE PREFIX
XX~X
I
XXX
X
PACKAGE SUFFIX*
•
X==-----
See the specific data sheet for available combinations.
"Except DAC·l00. See the DAC·l00 data sheet.
PACKAGE SUFFIX:
PACKAGE
D!SCRIPTION
K
DESCRIPTION
PACKAGE
6Pin TO·78
8 Pin TO·99
10 Pin TO·l00
H
J
10 Pin
14 Pin
24 Pin
8 Pin
L
M
N
P
DESCRIPTION
PACKAGE
Hermetic Flatpack
Hermetic Flatpack
Hermetic F latpack
Epoxy B Mini Dip
Y
Q
X
V
14 Pin
16 Pin
18 Pin
24 Pin
Hermetic
Hermetic
Hermetic
Hermetic
Dip
Dip
Dip
Dip
MIL·STD-883A CLASS 8 ORDERING INFORMATION
I
XXX
TYPE PREFIX
XXXX
I
MODEL FAMILY
883
X
X
~;~:------CLASS 8 MIL·STD·883A
ELECTRICAL GRADE
PACKAGE SUFFIX
All PMI _55° to +125°C devices are available in versions with screening to Class B of MIL·STD·883A as standard. A complete
list is included in the HI·REL section of this catalog. For all products except DAC·l00, the part number construction is as
shown below; for DAC·l00, see the DAC·l00 data sheet.
Example: To order OP·01FJ with 8838 screening.
1. 8asic Device Part Number: OP·Ol FJ
2. MIL·STD·883A Class B Version: OP01·883·FJ
CHIP ORDERING INFORMATION
All PMI chips are available with either plain backing or, at extra cost, l·micron thich eutectic·bonded gold backing. Electrical
performance is specified at 25°C for all products in the data sheet section of this catalog. Visual inspection criteria is as listed
below:
XXXXXX
T
MODEL TYPE
1
XXX
1
XX
~BACKING SUFFIX:
'-----VISUAL CRITERIA:
C;
A;
B;
C;
PLAIN, CG; GOLD
MIL·STD·883A METHOD 2010.2 TEST CONDITION A
MIL·STD·883A METHOD 2010.2 TEST CONDITION B
PMI "C" VISUAL, PMI SPECIFICATION NO. A0018 BASED
ON MIL·STD·883 METHOD 2010 ISSUED 1 MAY 1968.
ELECTRICAL GRADE:
N ; TOP, G ; MIDDLE, GR ; LOWEST
For price and delivery information or quotations for special devices, contact the nearest PM I sales office or representative
listed in the back of this catalog.
2·2
I
NUMERICAL INDEX
IORDERING INFORMATION
Q.A. PROGRAM
I INDUSTRY CROSS REFERENCE
FUNCTIONAL REPLACEMENT GUIDE
I'OPERATIONAL AMPLIFIERS
I
I
I
COMPARATORS
MATCHED TRANSISTORS
VOLTAGE REFERENCES
I
D/A CONVERTERS - LINEAR
I
D/A CONVERTERS - COMPANDING
IMULTIPLEXERS
I
DEFINITIONS
ICHIPS
I
I
I
APPLICATION NOTES
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PACKAGE INFORMATION
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NOTES
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PMI
.A. PROGRAM
MANUFACTURING AND SCREENING PROCEDURES
INTRODUCTION
TABLE OF CONTENTS
Introduction ....... .
Manufacturing Procedure ..........••...
Screening Levels . . . . . • • . . . . . . . . . . . . ..
Screening Procedures ••...............
Quality Conformance Procedures .........
LTPD Table . . . . . . . . . . . . • . . . . . . . . .
Group A
Group B
GroupC
GroupO
Ordering Information. . . . . . . • . . . . . • . . ..
Precision Monolithics, Inc., in establishing standard procedures
for Manufacturing; Screening, Qualification, and Quality Con·
formance, has incorporated the requirements of both
MIL·STD·883A, Notice 2 of March 1976, and MIL·Q·9858A.
All PMI military temperature range devices meet or exceed
Class C requirements, and, in addition, devices meeting and/or
exceeding Class B requirements are available off·the·shelf as
standard catalog items. Requests for devices with Class A or
other speciaivrequirements are invited. The internal procedures
designed to control and guarantee production of these devices
are described herein.
PMI standard "883" parts· designate devices which have been
subjected to 100% screening in accordance with Metliod 5004
of MIL·STD·883A, Class B.
3·1
3·1
3·1
3·2.
3-3
3·3
3·3
3·3
3·5
3·6
3·7
Quality Conformance Testing (Groups A, B, C, D) in accord·
ance with Method 5005 of MIL·STD·883A is available on
special order.
STANDARD MANUFACTURING PROCEDURE FOR ALL DEVICES
SCREENING LEVELS
MIL-STD-883A DEFINES 3 LEVELS OF MICROELECTRONIC SCREENING:
·CLASS A -
Devices intended for use where maintenance and replacement are extremely difficult or impossible. and reliability is
imperative.
.
·CLASS B -
Devices intended for use where maintenance and replacement can be performed, but are difficult and expensive, and
where reliability is vital.
·CLASS C -
Devices intended for use where maintenance and replacement can be readily accomplished and down time is not a
critical factor. (All PMI Mil Temp Range devices meet or exceed Level C.l
SCreening procedures for all 3 classes and for Precision Monolithics standard military temperature range devices are shown on the following page.
3·1
SCREENING PROCEDURES
MIL-STD-88JA
METHOD 5004
CLASS A
MIL-STD-88JA
METHOD 5004
CLASS 8
MIL-s'rD-8B3A
METHOD 5004
CLASS C
PRESEAL INTERNAL
VISUAL METHOD 2010
CONDITIONB
PRESEAL INTERNAL
VISUAL METHOD 2010
CONDITION B
STABILIZATION BAKE
METHOD 100S
PMI STANDARD
MIL TEMP DEVICES
PRESEAL INTERNAL
VISUAL METHOD 2010
CONDITION A
STABILIZATION BAKE
METHOD 1008
CONDITION C 124 HRS)
CONDITION C (24 HRS)
SEAL METHOD
1014
CONDITION A1 & C2
ELECTRICAL TEST
+2S"C
BURN-IN TEST
METHOD 1015 CONO. B
160 HRS@+12S"C
FINAL ELECTRICAl TEST
FINAL ELECTRICAL TEST
AT
2S'C
AT
2S'C
FINAL ELECTRICAL TEST
AT
+25 C
STATIC TEST
MINIMAX
TEMPERATURES
EXTERNAL VISUAL
METHOD 2009
IELECTRICAl!
FUNCTIONAL
2S"C
TEST
FUNCTIONAL
2S"C
TEST
EXTERNAL VISUAL
METHOD 2009
EXTERNAL VISUAL
METHOD 2009
EXTERNAL VISUAL
METHOD 2009
O.A. SAMPl.E INSPECTION
• (ELECTRICAL)
a.A. SAMPLE INSPECTION
a.A. SAMPLE INSPECTION
(ELECTRICAL)
(ELECTRICAl!
3-2
•
Ql}ALlFICATION AND QUALITY CONFORMANCE PROCEDURES
MIL-STD-883A Method 5005 establishes Qualification and Quality Conformance Procedures for the 3 classes of devices and divides
these procedures into group A, B, C&D tests: "The full requirements of group A, B, C and 0 tests and inspections are intended for
use in initial device qualification, requalification in the event of product or process change and periodic testing for retention of
qualification. Group A and B tests and inspections are intended for quality conformance inspection of individual inspection lots as
a condition for acceptance for delivery."
I:·
I.
Group A, B, C and 0 quality conformance tests are performed using a sample size determined from the.L TPD table below. An initial
sample size corresponding to zero rejects (an acceptance number of 0) is normally used; if necessary the sample size will be increased
once to a higher number to meet the LTPD requirement for the class of device under test.
LOT TOLERANCE PERCENT DEFECTIVE (LTPD) TABLE (PER MIL-M-38510AI
LTPD20
ACCEPTANCE
NUMBER'
LTPD 15
LTPD 10
LTPD7
LTPD5
LTPD3
Minimum Sample Size
0
11
15
22
32
45
76
1
18
25
38
55
77
129
2
25
34
52
75
105
176
3
32
43
65
94
132
221
4
38
52
78
113
158
265
*Maximum allowable number of failures.
GROUP A ELECTRICAL TESTS: REFERENCE MIL-STD-883A METHOD 5005
(Electrical tests per applicable data sheet specifications)
SUBGROUP
CLASS A
LTPD
TEST DESCRIPTION
CLASSB
LTPD
CLASSC
LTPD
1
Static tests at 25° C
5
5
5
2
Static tests at maximum rated operating temperature
7
7
10
3
Static tests at minimum rated operating temperature
7
7
10
4
Dynamic tests at 25°C
5
5
5
7
Functional tests at 25°C
5
5
5
9
Switching tests at :l5°C
7
7
10
GROUP B TESTS FOR CLASS A DEVICES
CLASS A
QUANTITY/(ACCEPT NO.)
MIL-STD-883
TEST
METHOD
CONDITION
LOT 1
LOT2AND
SUBSEQUENT
Subgroup 1
Physical dimensions
2(0)
2016
2(0)
Sutl!Jroup 2 2/
(a) .
Resistance to solvents
2015
(b)
Internal visual and
mechanical
2014
Bond strength
2011
Failure criteria from design and
3(0)
3(0)
2(0)
2(0)
2(0) 7/
2(0) 7/
3(0)
3(0)
construction requirements of
applicable procurement document
(c)
(1)
(d)
(1)
(2)
(3)
(4)
Thermocompression
(2)
Ultrasonic
(3)
(4)
Flip-chip
Beam lead
Die shear test
2019
Test condition
Test condi.tion
Test condition
Test condition
C or 0
C or D
F
H
Per table I of method 2019 for
the applicable die size
3-3
GROUP B TESTS FOR CLASS A DEVICES - CONTINUED
CLASS A
QUANTITY/ACCEPT NO.)
MIL-5TD-8S3
TEST
Subgroup 3
LOT 1
METHOD
CONDITION
2003
Soldering temperature of 260 ± 100
2004
1014
Test condition 82. lead fatigue
As applicable
Steady state life
(accelerated)
Electrical parameters
1005
Group A, subgroup 1,2,3: Read
and record
Group A, subgroups 4-11: Attributes
Cond ition F, 250" C
Steady state life
{accelerated I
1005
LOT2 AND
SUBSEQUENT
,
Solderability 3/
e
LTPD
= 15
LTPD
= 15
Subgroup 4
Lead integrity
Seal
{al Fine
{bl Gross 4/
2{01
2(0)
40(8)
10{21
40{16151
10{4151
12{01
5(0)
or
or
20{11
8(11
Subgroup 5 6/
{al
Gate 1
{II
Electrical parameters
{21
(31
(bl
120 continuous hours minimum
Group A, subgroups 1,2,3: Read
and record
Gate 2
(1)
Condition-F, 250"C, 250 hours
minimum including actual gate 1 life
test duration
{21
{31
Seal
a. Fine
b. Gross 4/
Electrical parameters
Group A, subgroups 1,2,3: Read
and record
Group A. subgroups
4~11:
Attributes
Subgroup 6 2/
{al
Electrical parameters
(bl
Temperature cycling
1010
Condition ClOD cycles/min.
{cl
Constant acceleration
2001
Test Condition E: Y 1 axis followed
{dl
Seal
{II
{21
1014
Group A. subgroups 1,2,3: Read
and record
by one other axis, X or Z.
{el
Fine
Gross 41
Electrical parameters
Group A, subgroups 1,2,3: Read
and record
1
Electrical reject devices from the same inspection may be used for all subgroups when end point measurements are not required.
2
For class A lot quality conformance testing, all samples for subgroup 82 must have been through the complete sequence of subgroup
86 tests.
3
All devices must have been through the temperatureltime exposure in burn~in. The L TPD applies to the number of leads in&pected
except in no case shall less than three devices be used to provide the number of leads required.
4
When fluorocarbon gross leak testing is utilized, test condition C2 shall apply as a minimum.
S
Sample quantity for acceptance purposes is the incoming sample for gate 1 and the accept number applies to the total failures from
6
The alternate removal-of~bias provisions of paragraph 3.2.1 of methods 1005 and 1015 shall not apply for test temperatures above
7
Pull ten (10) wires minimum per device or pull all wires if ten are not available.
both gate 1 and gate 2.
125"C.
3-4
•
GROUP B TESTS FOR CLASSES BAND C
MIL-5TD-8B3
TEST
CONDITION
METHOD
CLASSES B lit C
LTPD
Subgroup 1
Physical dimensions
2016
2 devices
(no failures I
Resistance to solvents
2015
Internal visual and
2014
3 devices
(no failuresl
1 device
(no failuresl
Subgroup 2
(al
(bl
mechanical
Failure criteria from design and construction
requirements of applicable procLirement
document.
(cl
Bond
(11
(21
(31
(41
strength 21
2011
15
(11
(21
(31
(41
Thermocompression
Ultrasonic or wedge
Flip-chip
Beam lead
Test condition
Test condition
Test condition
Test condition
C or 0
C or 0
F
H
Subgroup 3
Solderability 31
1
2003
Soldering temperature of 260 ± 10°C_
15
Electrical reject devices from the same inspection lot may be used for all subgroups when end point measurements are not required.
2 Test samples for bond strength may, at the manufacturer's option unless otherwi~ specified be randomly selected immediately following internal visual (precapl inspection specified in method 5004, prior to sealing_
3 All devices submitted for solderability test must have been through the temperatureltime exposure specified for burn-in_ The LTPD
for solderability test applies to the number of leads inspected except in no case shall less than 3 devices be used to provide the number
of leads required.
GROUP C (DIE·RELATED TESTS) (FOR CLASSES BAND CONLY)
MIL-5TD-8B3
TEST
CONDITION
METHOD
LTPD
Subgroup 1
Operating life test 11
1005
End point electrical parameters
Test condition to be specified (1000 hoursl
As specified in the applicable device specification
5
Test condition C
15
Subgroup 2
Temperature cycling
Constant acceleration
SEAL
1010
2001
1014
Test ~ondition E min_ (see 31
y 1 axis followed by one other axis X or Z_
As applicable
Fine
Gross 31
Visual examination
End point electrical parameters
2
As specified in the applicable device speCification.
1 See 40.4 of appendix B of MIL-M-38510_
2 Visual examination shall be in accordance with method 1010.
3
When fluorocarbon gross leak testing is utilized~ test condition C2 shall apply as minimum.
3·5
GROUP D (PACKAGE RELATED TESTS) (FOR ALL CLASSES)
MIL-SrD-8S3
TEST
CONDITION
METHOD
LTPD
Subgroup 1
Physical dimensions
15
2016
Subgroup 2 4/
Lead integrity
Seal
(al
(bl
2004
1014
Test condition 62 (lead fatigue 1
As applicable
15
1011
1010
1004
1014
Test condition B as a minimum, 15 cycles minimum.
Test condition C, 100 cycles minimum.
15
Fine
Gross 6/
Subgroup 3 1/
Thermal shock
Temperature cycling
Moisture resistance
Seal
(al
Fine
(bl
Gross 61
Visual examination
End point electrical
As applicable.
21
As specified in the applicable device specification.
parameters
Subgroup 4 11
Mechanical shock
Vibration variable frequency
Constant acceleration
Seal
(al
Fine
(bl
Gross 61
Visual examination
2002
2007
2001
1014
Test condition B
15
Test condition A
Test condition E (see 31
As applicable
31
End point electrical parameters
As specified in the applicable device specification.
Subgroup 5 41
Salt atmosphere
1009
Visual exam inatlon
51
Test condition A
Devices used in subgroup 3, "Thermal and Moisture Resistance" may be used in subgroup 4, "Mechanical."
2
Visual examination shall be in accordance with method 1010 or 1011 at a magnification of 5X to 10X.
3
Visual examination shall be performed in accordance with method 2007 for evidence of defects or damage to case, leads, or seals
resulting from testing (not fixturing). Such damages shall constitute a failure.
3-6
15
•
MODELS AVAILABLE WITH MIL·STD·883A CLASS B PROCESSING STANDARD
DIGITAL·TO·ANALOG CONVERTERS
GENERAL PURPOSE OPERATIONAL AMPLIFIERS
DAC·Ol-883·V
DACOl-883·BV
DAC-Ol-883·FV
DACOS-883·AXl (or X2)
DACOS-883·BXl (or X2)
DACOS-B83·CXl (or X2)
DAC06-883·AX
DAC-883·BX
SSS741-883-J
SSS741-883-V
SSS741-B83-GJ
SSS7 41-883-G V
PM741-B83-J
PM741-883·V
SSS747-883-1<
SSS747 -883-V
DAC06-883-CX
DAC06-883·AO
DACOB-883-O
DAC20-883·AO
DAC20-883-O
DAC76-883·BX
DAC76-883·X
DAC·l00 (NOTE)
SSSlS08A-883·BO
GENERAL PURPOSE FET INPUT OPERATIONAL AMPLIFIERS
NOTE: See the DAC·l00 data sheet for available models.
PM155-883·AJ
PM 155-883·J
PM156-883·AJ
PRECISION VOLTAGE REFERENCES
REFOl-883·AJ
REF01-B83·J
REF02-883·AJ
REF02-883·J
OP04-883·Y
0P04-883-K
CMP02-883·J
CMP02-883·V
MATCHED DUAL TRANSISTORS.
MATOl-883·AH
MATOl-883·H
MATOl-883·FH
MATOl-883·GH
PRECISION OPERATIONAL AMPLIFIERS
OPOl-883·J
OPOl-883·V
OPOl-883·FV
OPOl-883·FJ
OPOl-883·GJ
OP01·883-GV
OP02-883·AJ
OP02·883·AV
OP02-883·J
OP02-883-V
OPOS-883·AJ
OPOS-B83·AV
OPOS-B83·J
OPOS-883·V
OP07-883·AJ
OP07·883·AV
OP07·883·J
OP07-883·V
OP08-883·AJ
OP08·883·BJ
OP08·883·CJ
OP09-883·A V
OP09-B83·BV
OPl 0-883·A V
PM156-883·J
PM 157 -883·AJ
PM1S7-883·J
DUAL MATCHED HIGH PERFORMANCE OPERATIONAL
AMPLIFIERS
PRECISION VOLTAGE COMPARATORS
CMPOl-883·J
CMPOl-883·V
SSS747-883-GK
SSS747-883GV
PM747-883-K
PM747-B83-Y
SSSlSS8-B83·J
PM 1558-883·J
PM4136-883·Y
OP10-883·V
OPll-883·AV
OPll-883·BV
OP12-883·AJ
OP12-B83·BJ
OP12-883-CJ
OP1S-883-AJ
OP1S-883-BJ
OP1S-883-CJ
OP16-883·AJ
OP 16-883·BJ
OP16-B83-CJ
OP17 -883-AJ
OP17-883·BJ
OP17-B83·CJ
SSS72S-883-AJ
SSS72S-883·A V
SSS72S-883·J
SSS72S-883·V
PM72S-883·J
PM72S-883·V
PM 108-883·AJ
PM108-883·J
3-7
OP14-B83·AJ
OP 14-883·J
I
NUMERICAL
INDE~
IORDERING INFORMATION
lOA.
PROGRAM
INDUSTRY CROSS REFERENCE
FUNCTIONAL REPLACEMENT GUIDE
I OPERATIONAL AMPLIFIERS
I COMPARATORS
I MATCHED TRANSISTORS
IVOLTAGE REFERENCES
I
DIA CONVERTERS - LINEAR
IDIA CONVERTERS - COMPANDING
I
I
MULTIPLEXERS
DEFINITIONS
I
CHIPS
I
APPLICATION NOTES
1m
1m
II]]
4
ITJ'
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rn
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I'PACKAGE INFORMATION
(iJ
INOTES
1m
INTERCHANGEABILITY GUIDE
FAIRCHILD
PMI DIRECT
REPLACEMENT
PMI IMPROVED
DIRECT
REPLACEMENT
TEMP
RANGE
PACKAGE
LM108AH
LM108H
LM208H
LM308AH
LM308H
PM108AJ
PM10BJ
PM20BJ
PM308AJ
PM30BJ
OP-08AJ
OP-08BJ
OP-08BJ
OP-08EJ
OP-08FJ
MIL
MIL
IND
COM
COM
TO-99
TO-99
TO-99
TO-99
TO-99
725AHM
725HM
725HC
725EHC
725PC
SSS725J
PM725J
PM725CJ
SSS725AJ
SS725J
SSS725EJ
SS725EJ
MIL
MIL
COM
COM
COM
TO-99
TO-99
TO-99
TO-99
MINI-DIP
741HM
741HC
741DM
741DC
741AHM
741EHC
741ADM
741EDC
PM741J
SSS741CJ
PM741Y
SSS741CY
OP-02J
OP-02CJ
OP-02Y
OP-02CY
SSS741GJ
OP-02CJ
SSS741GY
OP-02CY
OP-02AJ
OP-02EJ
OP-02AY
OP-02EY
MIL
COM
MIL
COM
MIL
COM
MIL
COM
TO-99
TO-99
DIP
DIP
1'0-99
TO-99
DIP
DIP
747DM
747DC
747HM
747HC
747ADM
747EDC
747AHM
747EHC
PM747Y
SSS747CY
PM747K
SSS747CK
SSS747GY
OP-04CY
SSS747GK
OP-04CK
SSS747Y
SSS747BY
SSS747K
SSS747BK
MIL
COM
MIL
COM
MIL
COM
MIL
COM
DIP
DIP
TO-l00
TO-l00
DIP
DIP
TO-l00
TO-l00
801ADM
801DM
801EDC
801CDC
DAC-OBAQ
DAC-08Q
DAC-OBEQ
DAC-08CQ
MIL
MIL
COM
COM
DIP
DIP
DIP
DIP
802DM
802ADC
802BDC
802CDC
SSS1508A-8Q
SSS1408A-8Q
SSS1408A-7Q
SSS1408A-6Q
MIL
COM
COM
COM
DIP
DIP
DIP
DIP
PM725CP
4-1
•
NATIONAL
SEMICONDUCTOR
I
PMI DIRECT
REPLACEMENT
PMI IMPROVED
DIRECT
REPLACEMENT
TEMP
RANGE
PACKAGE
LM10SAH
LM10SH
LM20SH
LM308AH
LM308H
PM10SAJ
PM10SJ
PM20SJ
Pfvl30SAJ
PM30SJ
OP·OSAJ
OP-OSBJ
OP·OSBJ
OP·OSEJ
OP·OSFJ
MIL
MIL
IND
COM
COM
TO-99
TO-99
TO-99
TO-99
TO-99
LF155AH
LF155H
LF255H
LF355AH
LF355H
PM155AJ
PM155J
PM255J
PM355AJ
PM355J
Op-15AJ
OP-15BJ
OP-15BJ
Op-15EJ
Op-15GJ
MIL
MIL
IND
COM
COM
TO-99
TO-99
TO-99
TO-99
TO-99
LF156AH
LF156H
LF256
LF356AH
LF356H
PM156AJ
PM156J
PM256J
PM356AJ
PM356J
OP-16AJ
OP-16BJ
Op-16BJ
OP-16EJ
OP-16GJ
MIL
MIL
IND
COM
COM
TO-99
TO-99
TO-99
TO-99
TO-99
LF157AH
LF157H
LF257H
LF357AH
LF357H
PM157AJ
PM157J
PM257J
PM357AJ
PM357J
Op-17AJ
Op-17BJ
OP-17BJ
OP-17EJ
OP-17GJ
MIL
MIL
IND
COM
COM
TO-99
TO-99
TO-99
TO-99
TO-99
LM725AH
LM725H
LM725CH
LM725D
LM725CN
SSS725J
PM725J
PM725CJ
PM725Y
PM725CP
SSS725AJ
SSS725J
SSS725CJ
SSS725Y
MIL
MIL
COM
MIL
COM
TO-99
TO-99
TO-99
DIP
MINI·DIP
LM741H
LM741CH
LM741D
LM741CD
PM741J
SSS741CJ
PM741Y
SSS741CY
SSS741GJ
OP·02CJ
SSS741GY
OP·02CY
MIL
COM
MIL
COM
TO-99
TO-99
DIP
DIP
LM747H
LM747CH
LM747F
LM747CF
LM747D
LM747CD
PM747J
SSS747CK
PM747Y
SSS747CY
SSS747GK
OP·Q4CK
SSS747GM
SSS747BM
SSS747GY
OP·Q4CY
MIL
COM
MIL
COM
MIL
COM
TO-l00
TO-l00
FLATPACK
FLATPACK
DIP
DIP
LM1458H
LM1558H
SSS145S
PM1558
OP-14CJ
SSS155S
COM
MIL
TO-99
TO-99
LFl150S
MUX·SS
MIL
DIP
LMDAC08
DAC·OS
MIL
DIP
4-2
PMI IMPROVED
DIRECT
REPLACEMENT
TEMP
RANGE
RAYTHEON
PMI DIRECT
REPLACEMENT
LM108AH
LM108H
LM208H
LM308AH
LM308H
PM108AJ
PM108J
PM208J
PM30aAJ
PM30BJ
OP-08AJ
OP-08BJ
OP-08BJ
OP-08EJ
OP-08FJ
MIL
MIL
INO
COM
COM
TO-99
TO-99
TO-99
TO-99
TO-99
RM725T
RC725T
PM725J
PM725CJ
SSS725J
SSS725CJ
MIL
COM
TO-99
TO-99
RM741T
RC741T
RM741D
RC741D
RC741DP
PM741J
SSS741CJ
PM741Y
SSS741CY
SSS741GJ
OP-02CJ
SSS741GY
OP-02CY
SSS741CY
MIL
COM
MIL
COM
COM
TO-99
TO-99
TO-99
TO-99
TO-99
RM747T
RC747T
RM747D
RC747D
RC747DP
PM747K
SSS747CK
PM747Y
SSS747CY
SSS747K
OP-04CK
SSS747Y
OP-04CY
SSS747CY
MIL
COM
MIL
COM
COM
TO-l00
TO-l00
DIP
DIP
DIP
RM1558T
RC1458T
PM1558
SSS1458
SSS1558
OP-14CJ
MIL
COM
TO-99
TO-99
RM4136
RC4136
PM4136Y
PM4136CY
OP-09BY
OP-09FY
MIL
COM
DIP
DIP
SN52558L
SN72558L
PM1558
SSS1458
SSS1558
OP-14CJ
MIL
COM
TO-99
TO-99
SN52741L
SN52741J
SN72741L
SN72741J
PM741J
PM741Y
SSS741CJ
SSS741CY
SSS741GJ
SSS741GY
OP-02CJ
OP-02CY
MIL
MIL
COM
COM
TO-9!;!
DIP
TO-99
DIP
SN52747L
SN52747J
SN52747Z
SN72747L
SN72747J
PM747K
PM747Y
SSS747GK
SSS747GY
SSS747GM
SSS747CK
SSS747CY
PACKAGE
TEXAS
INSTRUMENTS
,
TL081ACL
TL081CL
TL081AML
TL081ML
OP-16FJ
OP-16GJ
OP-16BJ
OP-16CJ
4--3
TO-l00
DIP
FLATPACK
TO-l00
DIP
COM
COM
MIL
MIL
T9-99
TO-99
TO-99
TO-99
•
ADVANCED
MICRO DEVICES
PMIDIRECT
REPLACEMENT
SSS725AJ
SSS725J
SSS725BJ
SSS725EJ
SSS725AJ
SSS725J
SSS725BJ
SSS725EJ
SSS741J
SSS741CJ
SSS741J
SSS741CJ
SSS747K
SSS747P
SSS747M
SSS747CK
SSS747CP
SSS747K
SSS747Y
SSS747M
SSS747CK
SSS747CY
SSS150SA-SO
SSS140SA-BO
SSS140SA-70
SSS1408A-60
SSS150SA-SO
SSS140SA-SO
SSS140SA-70
SSS140SA-60
AM1508LS
AM140BLB
AM140SL7
AM140BL6
DAC-OBAO
DAC-OSO
DAC-OSHO
DAC-OSEO
DAC-OSCO
PMI IMPROVED
DIRECT
REPLACEMENT
TEMP
RANGE
PACKAGE
MIL
MIL
IND
COM
TO-99
TO-99
TO-99
TO-99
OP-02AJ
OP-02EJ
MIL
COM
TO-99
TO-99
OP-04AK
OP-04AY
MIL
MIL
MIL
COM
COM
TO-l00
DIP
FLATPACK
TO-l00
DIP
MIL
COM
COM
COM
DIP
DIP
DIP
DIP
MIL
COM
COM
COM
DIP
DIP
DIP
DIP
MIL
MIL
COM
COM
COM
DIP
DIP
DIP
. DIP
SSS562-SD-BIN
SSS562-SD-BCD
SSS562-AD-BIN
SSS562-AD-BCD
SSS562-KD-BIN
SSS562-KD-BCD
MIL
MIL
IND
IND
COM
COM
DIP
DIP
DIP
DIP
DIP
DIP
DAC-OBAO
DAC-OSO
DAC-OSEO
DAC-OSCO
MIL
MIL
COM
COM
DIP
DIP
DIP
DIP
OP-04CK
OP-04CY
SSS150SA-80
SSS140SA-SO
SSS140SA-70
SSS140BA-60
DAC-OBAO
DAC-OSO
DAC-OSHO
DAC-QSEO
DAC-OBCO
DIP
ANALOG DEVICES
AD562SD/BIN
AD562SD/BCD
AD562AD/BIN
AD562AD/BCD
AD562KD/BIN
AD562KD/BCD
SIGNETICS
SE5009
SE500S
NE500S
NE5007
4-4
RCA
PMI DIRECT
REPLACEMENT
PMI IMPROVED
DIRECT
REPLACEMENT
CA108AT
CA108T
CA208AT
DA208T
CA308AT
CA308T
TEMP
RANGE
PACKAGE
PM108AJ
PM108J
PM208AJ
PM208J
PM308AJ
PM308J
MIL
MIL
IND
IND
COM
COM
TO·99
TO·99
TO·99
TO·99
TO·99
TO·99
CA741T
CA741CT
PM741J
SSS741CJ
SSS741GJ
Op·02CJ
MIL
COM
TO·99
TO·99
CA747T
CA747CT
CA747E
CA747CE
PM·747K
SSS747CK
PM747Y
SSS747CY
SSS747K
Op·04CK
SSS747Y
OP·04CY
MIL
COM
MIL
COM
TO·l00
TO·l00
DIP
DIP
CA1458T
CA1558T
SS51458
PM1558
Op·14CJ
SSS1558
COM
MIL
TO·99
TO·99
MC1741G
MC1741L
MC1741CG
MC1741CL
PM741J
PM741Y
SSS741CJ
SSS741CY
SSS741GJ
SSS741GY
OP-02CJ
OP-02CY
MIL
MIL
COM
COM
TO·99
DIP
TO·99
DIP
MC1558G
MC1458G
MC1458CG
PM1558
SSS1458
SSS1458
55S1558
OP·14EJ
OP·14CJ
MIL
COM
COM
TO·99
TO·99
TO·99
5SS1508A·80
SSS1408A·80
SSS1408A·70
SSS1408A·60
MIL
COM
COM
COM
DIP
DIP
DIP
DIP
MOTOROLA
MC1508L·8
MC1408L·8
MC1408L·7
MC1408L·6
4-5
I'NUMERICAL INDEX
IORDERING INFORMATION
lOA',
PROGRAM
I
INDUSTRY CROSS REFERENCE
FUNCTIONAL REPLACEMENT GUIDE
I
I
I
I
OPERATIONAL AMPLIFIERS
COMPARATORS
MATCHED TRANSISTORS
VOLTAGE REFERENCES
lOlA CONVERTERS - LINEAR
lOlA CONVERTERS - COMPANDING
I
I
MULTIPLEXERS
DEFINITIONS
I'CHIPS
I
APPLICATION NOTES
OJ
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I:PACKAGE INFORMATION
Ii]
INOTES
1m
FUNCTIONAL EaUIVALENT GUIDE
THE FOLLOWING TABLES SHOW PMI DESIGN ALTERNATIVES TO OTHER MANUFACTURERS' DEVICES: IC'S,
HYBRIDS, AND MODULES. THESE ARE USUALLY NOT DIRECT PIN-FOR-PIN ELECTRICAL AND MECHANICAL
REPLACEMENTS, BUT RATHER, THEY ARE FUNCTIONAL EQUIVALENTS. PERFORMANCE AND SPECIFICATIONS
ARE SIMILAR.
ANALOG
DEVICES
DEVICE
DESCRIPTION
PMI NEAREST
EQUIVALENT
APPLICATION
COMMENTS
AD504
PRECISION OP AMP
OP-05
NULLED_
AD509
HIGH SPEED OP AMP
OP-16
FAST SETTLING.
AD510
PRECISION OP AMP
OP-05
NULLED.
AD510
PRECISION OP AMP
OP-07
UNNULLED.
AD559
8-BIT MULTIPLYING D/A
CONVERTER
DAC-08
MULTIPL YING.
AD580
VOLTAGE REFERENCE
BANDGAP +2.5V
REF-02
REF-02 IS +5V REFERENCE.
AD741
IM~ROVED
OP-02
PIN-FOR-PIN REPLACEMENT.
AD810
MATCHED TRANSISTOR PAIR
MAT-01
PIN-FOR-PIN REPLACEMENT.
AD818
MATCHED TRANSISTOR PAIR
MAT-Ol
LOG AMP APPLICATIONS.
AD2700
HYBRID +10V REFERENCE
REF-Ol
REF-Ol IS IC AND LOW POWER.
AD7520
10-BIT MULTIPLYING
DAC-CMOS
DAC-08
8-BIT APPLICATIONS
AD7520
10-BIT MULTIPLYING
DAC-CMOS
DAC-l00
10-BIT NON-MUL TlPL YING
APPLICATIONS.
CMOS
MULTIPLEXERS
SEVERAL, CMOS TYPES
MUX-88
8 CHANNEL
FET OP AMPS
SEVERAL FET OP AMPS
OP-15/16/17
SELECT PMI DEVICE ACCORDING TO THE APPLICATION.
741 OP AMP
BURR
BROWN
BB3505
HIGH SPEED OP AMP
OP-16
HIGHEST SPEED APPLICATIONS.
BB3506
HIGH SPEED OP AMP
OP-15
MEDIUM SPEED APPLICATIONS.
DAC-80/85
12-B IT DAC'S
SSS562
USE SSS562 WITH EXTERNAL
REFERENCE.
5-1
•
HARRIS
SEMICONDUCTOR
DEVICE
DESCRIPTION
PMINEAREST
EQUIVALENT
APPLICATION
COMMENTS
HA-2510
HIGH SPEED OP AMP
OP-16
PMI OP-15/16/17 REPLACE
SEVERAL HARRIS TYPES IN
SOME APPLICATIONS_
HA-2900
CHOPPER-STABILIZED PRECISION OP AMP
OP-07
SEE AN-13 ALSO_
HA-4741
QUAD OPAMP
OP-ll
OP-ll HAS MUCH LOWER
OFFSET VOLTAGE.
NATIONAL
SEMICONDUCTOR
LH0044
HYBRID PRECISION OP AMP
OP-07
MOST APPLICATIONS.
LH0044
HYBRID PRECISION OP AMP
OP-12
APPLICATIONS WHERE LESS
THAN lmA SUPPLY CURRENT
IS REQUIRED.
LH0070
HYBRID +10V REFERENCE
REF-Ol
REF-Ol MUCH LOWER POWER.
LMll0/310
VOLTAGE FOLLOWER
OP-12
CONNECT OP-12 AS A FOLLOWER. LOW SPEED APPLICATIONS.
LMll0/310
VOLTAGE FOLLOWER
OP-15/16
CONNECT OP-15/16 AS A FOLLOWER. HIGH SPEED
APPLICATIONS.
LMlll/311
VOLTAGE COMPARATOR
CMP-Ol
HIGH SPEED APPLICATIONS.
LMlll/311
VOLTAGE COMPARATOR
CMP-02
LOW INPUT CURRENT
APPLICATIONS.
LMl14/115
MATCHED TRANSISTOR PAIR
MAT-01
PIN-FOR-PIN REPLACEMENT.
LM148
QUADOPAMP
OP-ll
OP-ll PIN-FOR-PIN WITH LOWER
OF FSET VOLTAGES.
LM194/394
MATCHED TRANSISTOR PAIR
MAT-Ol
CROSS REFERENCE - MAT-01 TO MONOLITHIC DUAL TRANSISTORS IIC = 10tLA)
DEVICE
BVCEO
MIN
(V)
MAT-01AH
MAT-01H
MAT-01FH
MAT-01GH
LMl14A
LMl14
LMl15A
LMl15
AD810
AD811
AD812
AD813
AD818
45
60
60
45
45
45
60
60
35
45
35
45
20
Vos
MAX
(mV)
TCVos
MAX
(tLvtC)
0.1
0.1
0.5
0.5
0.5
2.0
0.5
2.0
3.0
1.5
1.0
0.5
1.0
0.5
0.5
1.8
1.8
2.0
10
2.0
10
15
7.5
5.0
2.5
5.0
5-2
hFE
MIN
500
330
250
250
500
250
250
250
100
200
400
200
200
los
MAX
(nA)
0.6
0.8
3.2
3.2
2.0
10
2.0
10
2.0
10
2.5
5
10
TClos
MAX
(pAtC)
90
110
150
150
-
600
300
300
300
300
CROSS REFERENCE - MAT-Ol TO 2N TYPES (lc = 101lA)
DEVICE
BVCEO
MIN
Vos
MAX
(VI
(mV)
hFE
MIN
%hFE
MATCH
MAX
los
MAX
(nA)
TClos
MAX
(pAtC)
MAT-01GH
2N2639
2N2640
2N2642
2N2643
2N2915
2N2915A
2N2916
2N2916A
2N2917
2N2918
45
45
45
45
45
45
45
45
45
45
45
0.5
5.0
10
5.0
10
3.0
2.0
5.0
2.0
10
5.0
1.8
10
20
10
20
10
5.0
10
5.0
20
20
250
50
50
100
100
60
60
150
150
60
150
8
10
20
10
20
10
15
10
15
20
20
3.2
20
40
10
20
17
26
7
10
17
7
150
1000
2000
500
375
600
900
N.C.
300
1450
750
MAT-01FH
2N2919
2N2919A
2N2920
2N2920A
2N2060
2N2060A
2N2060B
60
60
60
60
60
60
60
60
0.5
3.0
1.5
3.0
1.5
5.0
3.0
1.5
1.8
10
5.0
10
5.0
10
5.0
5.0
250
60
60
150
150
25
25
25
8
10
10
10
10
10
10
10
3.2
17
17
7
7
40
40
40
150
600
600
N.C.
300
N.C.
N.C.
N.C.
Notes:
1. Telos Max and los Max calculated from published data.
2. N.C. = Insufficient published data to calculate.
3. All of the above are physically interchangeable pin-for-pin with MAT-Ol series.
5-3
•
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IOJ
I
NUMERICAL INDEX
I'ORDERING INFORMAnON
I
I
I
O.A. PROGRAM
INDUSTRY CROSS REFERENCE
FUNCTIONAL REPLACEMENT GUIDE
6
OPERATIONAL AMPLIFIERS
I
[I]
COMPARATORS
rn
rn
[iQJ
liMATCHED TRANSISTORS
I VOLTAGE REFERENCES
I
D/A CONVERTERS - LINEAR
I:D/A CONVERTERS - COMPANDING
I!MULTIPLEXERS
liDEF INITIONS
I;CHIPS
I APPLICATION NOTES
I PACKAGE INFORMATION
I
NOTES
Irn
Irn
Irn
Irn
ITIJ
rnJ
JrnJ
mJ
mJ
rnJ
mJ
INTRODUCTION TO PMI OPERATIONAL AMPLIFIERS
This section includes operational amplifiers suitable for most applications. Selection guides give key MinIMax specifications
for singles, duals, and quads. This product line includes precision, superbeta, BIFET, and general purpose devices that provide
a very wide range of performance parameters for both 0" to 70"C and -55· to +125·C operating temperature ranges.
Newopamps introduced in the past year include: precision BIFETS IOP-15, OP-16, OP-17); second source BIFETS IPM155A,
PM156A, PM157A); precision low power improved 108 types IOP-08, OP-12); second source quads IPM4136); and precision
matched quads IOP-09, OP-ll). All PM I military temperature range operational amplifiers are available with MIl-STD-883A
Class B processing.
.;
INDEX
OPERATIONAL AMPLIFIERS
PRODUCT
TITLE
SELECTION GUIDES
Single BiFet Operational Amplifier
Single Low Power Operational Amplifier
Single Precision Operational Amplifier
Single General Purpose Operational Amplifier
Dl,Jal Precision Operational Amplifier
Dual General Purpose Operational Amplifier
Quad Operational Amplifier
OP-Ol
OP·02
OP-04
OP-05
OP-07
OP~
Inverting High Speed Operational Amplifier.
High Performance General Purpose Operational Amplifier
Dual Matched High Performance Operational Amplifier
Instrumentation Operational Amplifier .
Ultra·Low Offset Voltage Operational Amplifier
Precision Low Input Current Operational Amplifier
Quad Matched 741·Type Operational Amplifier
OP-09
Op·l0
Dual Matched Instrumentation Operational Amplifier
Quad Matched 741·Type Operational Amplifier
OP·11
Precision Low Input Current Operational Amplifier
OP·12
Opc14
Dual Matched High Performance Operational Amplifier
Precision JF ET Input Operational Amplifier
OP·15
Precision JF ET Input Operational Amplifier
OP·16
OP·17
Precision JFET Input Operational Amplifier
Instrumentation Operational Amplifier .
SSS725
SSS741
Compensated Operational Amplifier .
SSS747
Dual Compensated Operational Amplifier
SSS1458/1558 Dual Compensated Operational Amplifier
PM-l08A
Low Input Current Operational Amplifier
PM155
Monolithic JFET Input Operational Amplifier
Monolithic JFET Input Operational Amplifier
PM156
Monolithic JFET Input Operational Amplifier
PM157
PM725
Instrume.ntation Operational Amplifier .
PM·741
Compensated Operational Amplifier .
PM-747
Dual Compensated Operational Amplifier
PM·1458/1558 Dual Comepnsat~d Operational Amplifier
PM4136
Quad 741-Type Operational Amplifier
PAGE
6·1
6·3
6·5
6·7
6·9
6·11
6·13
6·16
6·19
6·25
6·31
6·37
6-43
6-50
6-56
6-66
6-72
6-78
6-84
6-90
6-96
6-101
6-108
6-111
6-114
6-116
6-119
6-123
6-127
6-131
6-133
6-135
6·137
6-139
SINGLE BIFET OPERATIONAL AMPLIFIER SELECTION GUIDE
MILITARY TEMPERATURE RANGE
INPUT BIAS CURRENT
MILITARY TEMPERATURE RANGE
INPUT OFFSET CURRENT
DEVICE
MAX. TJ~25"C
MAX. T J = 125"C
DEVICE
OP·15A
OP·16A
OP·17A
PM·1S5A
PM·l56A
PM·1S7A
OP·15B
OP·16B
OP·17B
PM·155
PM·l56
PM·157
OP·15C
OP·16C
OP·17C
50pA
50pA
50pA
50pA
50pA
50pA
l00pA
l00pA
l00pA
100pA
l00pA
l00pA
200pA
200pA
200pA
5.0nA
S.OnA
5.0nA
25nA
2SnA
25nA
7.5nA
7.5nA
7.5nA
50nA
50nA
50nA
10nA
10nA
10nA
Op·15A
OP·16A
OP·17A
PM.1S5A
PM·156A
PM·157A
OP·15B
OP·16B
OP·17B
PM·155
PM·156
PM·157
OP·15C
OP·16C
OP·17C
COMMERCIAL TEMPERATURE RANGE
INPUT BIAS CURRENT
DEVICE
MAX. TJ =25"C
OP·15E
OP·16E
OP·17E
PM·355A
PM·356A
PM·357A
OP·1SF
OP·16F
OP·17F
OP·15G
OP·16G
OP·17G
PM·3S5
PM·356
PM·357
50pA
50pA
50pA
SOpA
SOpA
SOpA
l00pA
100pA
100pA
200pA
200pA
200pA
200pA
200pA
200pA
MAX, TA =25"C
OP·15A
OP·16A
OP·17A
OP·158
OP·168
OP·17B
OP·15C
OP·16C
OP·17C
110pA
130pA
130pA
200pA
250pA
250pA
400pA
SOOpA
SOOpA
MAX. T J =70"C
DEVICE
0.4nA
0.4nA
0.4nA
5.0nA
5.0nA
5.0nA
0.6nA
0.6nA
0.6nA
0.8nA
0.8nA
0.8nA
8.0nA
8.0nA
8.0nA
OP·15E
OP·16E
OP·17E
PM·355A
PM·356A
PM·357A
OP·15F
OP·16F
OP·17F
Op·15G
OP·16G
OP·17G
PM·355
PM·356
PM·357
MAX. TA -25"C
OP·15E
OP·16E
OP·17E
OP·15F
OP·16F
OP·17F
OP·15G
OP·16G
OP·17G
110pA
130pA
130pA
200pA
250pA
2S0pA
400pA
500pA
SOOpA
10pA
10pA
10pA
10pA
10pA
10pA
20pA
20pA
20pA
20pA
20pA
20pA
50pA
50pA
50pA
=125·C
4.0nA
4.0nA
4.0nA
10 nA
10nA
10nA
6.0nA
6.0nA
6.0nA
20nA
20nA
20nA
9.0nA
9.0nA
9.0nA
MAX. T J =25"C
10pA
10pA
10pA
10pA
10pA
10pA
20pA
20pA
20pA
50pA
SOpA
SOpA
50PA
50pA
50pA
MAX. T J = 70·C
0.3nA
0.3nA
0.3nA
1.0nA
1.0nA
1.0nA
0.45 nA
0.45nA
0.45 nA
0.65nA
0.65nA
0.65 nA
2.0nA
2.0nA
2.0nA
MILITARY TEMPERATURE RANGE
INPUT OFFSET CURRENT
MAX. TA
=125·C
9.0nA
11 nA
11 nA
14 nA
18nA
18 nA
19nA
25nA
25 nA
DEVICE
MAX. TA =25"C
MAX. T A - 125·C
OP·15A
Op·16A
OP·17A
OP·1SB
OP·16B
OP·17B
OP·15C
OP·16C
OP·17C
22pA
2SpA
2SpA
40pA
50pA
SOpA
100pA
125pA
125pA
7.0nA
8.SnA
8.SnA
11 nA
14.SnA
14.5nA
17 nA
22nA
22nA
COMMERCIAL TEMPERATURE RANGE
INPUT BIAS CURRENT
DEVICE
MAX. T J
COMMERCIAL TEMPERATURE RANGE
INPUT OFFSET CURRENT
MILITARY TEMPERATURE RANGE
INPUT BIAS CURRENT
DEVICE
MAX. T J =25"C
COMMERCIAL TEMPERATURE RANGE
INPUT OFFSET CURRENT
MAX. TA -70·C
0.7S
0.9
0.9
1.1
1.4
1.4
1.S
2.0
2.0
nA
nA
nA
nA
nA
nA
nA
nA
nA
6-1
DEVICE
MAX. TA =25"C
OP·1SE
OP·16E
OP·17E
OP·1SF
OP·16F
OP·17F
OP·1SG
OP·16G
OP·17G
22pA
2SpA
25pA
40pA
SOpA
50pA
100pA
125pA
12SpA
MAX. TA =70"C
0.5SnA
0.7 nA
0.7 nA
0.8 nA
1.1 nA
1.1 nA
1.2 nA
1.7 nA
1.7 nA
SINGLE BIFET OPERATIONAL AMPLIFIER SELECTION GUIDE
MILITARY TEMPERATURE RANGE
INPUT OFFSET VOLTAGE
DEVICE
MAX, T A
=25°C
MILITARY TEMPERATURE RANGE
INPUT OFFSET VOL TAGE
DRIFT (TCV OS '
SUPPLY CURRENT
MAX, TA = FULL
DEVICE
OP-15A
OP-16A
OP-17A
OP-15B
OP-16B
OP-17B
PM-155A
PM-I56A
PM-157A
OP-I5C
OP-16C
OP-17C
PM-155
PM-I56
PII/I-157
0.5mV
0.5mV
0.5mV
1.0mV
1.0mV
1.0mV
2.0mV
2.0mV
2.0mV
3.0mV
3.0mV
3.0mV
5.0mV
5.0mV
5.0mV
0.9mV
0.9mV
0.9mV
2.0mV
2.0mV
2.0mV
2.5mV
2.5mV
2.5mV
4.5mV
4.5mV
4.5mV
7.0mV
7.0mV
7.0mV
OP-15A
OP-15B
PM-155A
PM-155
OP-15C
OP-16A
OP-16B
OP-17A
OP-17B
PM-156A
PM-I56
PM-157A
PM-157
OP-I6C
OP-17C
MAX, T A
=25°C
MAX, T A = FULL
DEVICE
OP-15E
OP-16E
OP-17E
OP-15F
OP-16F
OP-17F
PM-355A
PM-356A
PM-357A
OP-15G
OP-16G
OP-17G
PM-355
PM-356
PM-357
0.75 inv
0.75mV
0.75mV
1.5mV
1.5mV
1.5mV
2.3mV
2.3mV
2.3mV
3.BmV
3.BmV
3.BmV
13mV
13mV
13mV
0.5mV
0.5mV
0.5mV
1.0mV
1.0mV
1.0 mV
2.0mV
2.0mV
2.0mV
3.0mV
3.0mV
3.0mV
10mV
10mV
10mV
=25°C
4mA
4mA
4mA
4mA
5mA
7mA
7 mA
7mA
7 mA
7 mA
7mA
7mA
7 mA
BmA
SmA
DEVICE
MAX, T A = FULL
OP-15A
OP-16A
OP·17A
PM-155A
PM-156A
PM-157A
OP-15B
Op·16B
OP-17B
OP·15C
OP·16C
OP-17C
5.0jtVtC
5.0jtVtC
5.0jtVtC
5.0jtVtC
5.0jtVtC
5.0jtVtC
10jtVI"C
10jtVtC
10jtVtC
'15 jtV/"C
'15jtV/"C
'15jtV/"C
COMMERCIAL TEMPERATURE RANGE
INPUT OFFSET VOLTAGE
SUPPLY CURRENT
DRI FT (TCVOS '
COMMERCIAL TEMPERATURE RANGE
INPUT OFFSET VOLTAGE
DEVICE
MAX, T A
OP-15E
OP-15F
PM-355A
PM-355
OP-15G
OP-16E
OP-16F
OP-17E
OP-17F
PM-356A
PM-357A
OP-16G
OP-17G
PM-356
PM-357
MAX, T A
=25"C
4mA
4mA
4mA
4mA
5mA
7mA
7mA
7mA
7mA
7mA
7mA
BmA
8mA
lOrnA
lOrnA
DEVICE
MAX, T
OP-15E
OP-16E
OP-17E
PM-355A
PM-356A
PM-357A
OP-15F
OP-16F
OP-17F
OP-15G
OP-16G
OP-17G
PM-355
PM-356
PM-357
'Parameter not 100% tested. 90% of all units meet these
specifications.
N/S - Not specified.
MILITARY TEMPERATURE RANGE
SLEW RATE
COMMERCIAL TEMPERATUR~RANGE
SLEW RATE
DEVICE
DEVICE
OP-17A
PM-157A
OP-17B
PM-157
OP-17C
OP-16A
OP-16B
OP-15A
PM-156A
OP-16C
OP-15B
PM-156
OP-15C
PM-155A
MIN, TA = 25°C
*45
"40
"35
*30
OP-17E
PM-357A
OP-17F
OP-17G
OP-16E
OP-16F
OP-15E
PM-356A
OP-I6G
OP-15F
OP-15G
PM-355A
PM-355
PM-356
PM-357
V/jtsec
V/jtsec
V/jtsec
V/jtsec
"25 V/jtsec
18 V/jtsec
12 V/jtsec
10 V/jt5ec
10 V/jt5ec
9.0 V/jtsec
7.5 V/jt"'c
7.5 V/jtSec
5.0V/jt"'c
3.0 V/jtsec
"Closed Loop Gain = 5
N/S - Not specified.
6-2
*45 V/jtsec
*40 V/jt"'c
*35 V/jt5ec
"25 V/jt"'c
18 Vljtsec
12 V/jtsec
10 V/jtsec
10 V/jtsec
9.0 Vljt5ec
7.5 V/jt5ec
5.0 V/jtsec
5.0 V/jtsec
N/S
N/S
N/S
= FULL
5.0jtVI"C
5.0jtVtC
5.0jtVtC
5.0jtVtC
5.0jtVI"C
5.0jtVtC
10l'VrC
10jtV/"C
10jtVtC
'15jtVtC
'15jtVtC
*15jtVtC
N/S
N/S
N/S
•
SINGLE LOW POWER OPERATIONAL AMPLIFIER 'SELECTION GUIDE
MILITARY TEMPERATURE RANGE
INPUT BIAS CURRENT
I
~.~'"
MILITARY TEMPERATURE RANGE
INPUT OFFSET CURRENT
DEVICE
MAX. T A = 25°C
MAX OVER TEMPERATURE
DEVICE
MAX. TA =25"C
OP-08A
OP-mtB
OP-12A
OP-12B
PM-1OBA
PM-lOB
OP-OBC
OP-12C
2.0nA
2.0nA
2.0nA
2.0nA
2.0nA
2.0nA
5.0nA
5.0nA
3.0nA
3.0nA
3.0nA
3.0nA
3.0nA
3.0nA
10.0nA
10.0nA
OP-08A
OP-OBB
OP-12A
OP-12B
PM-1OBA
PM-lOB
QP-OBC
OP-12C
0.2nA
0.2nA
0.2nA
0.2nA
0.2nA
0.2nA
0.5nA
0.5nA
COMMERCIAL TEMPERATURE RANGE
INPUT BIAS CURRENT
DEVICE
OP-OBE
OP-12E
OP-OBF
OP-12F
OP-OBG
OP-12G
PM-3OBA
PM-3OB
MAX.TA =25"C
2.0nA
2.0nA
4.0nA
4.0nA
5.0nA
S.OnA
7.0nA
7.0 nA
MAX OVER TEMPERATURE
DEVICE
MAX. TA -25"C
MAX OVER TEMPERATURE
2.6nA
2.6nA
5.2 nA
5.2nA
6.5nA
6.SnA
10.0 nA
10.0nA
OP-OBE
OP-12E
OP-OBF
OP-12F
OP-08G
OP-12G
PM-3OBA
PM-3GB
0.2nA
0.2nA
0.4nA
0.4nA
0.5nA
0.5nA
1.0nA
1.0nA
0.3nA
0.3nA
0.6nA
0.6nA
0.7nA
0.7nA
1.5nA
1.5 nA
DEVICE
MAX. T A = 2SoC
MAX OVER TEMPERATURE
OP-OBA
OP-12A
OP-OBB
OP-12B
PM-1OBA
OP-OBC
OP-12C
PM-1OB
0.15 mV
0.15mV
0.30mV
0.30mV
0.50mV
1.0mV
1.0mV
2.0mV
0.35 mV
0.35mV
0.60mV
O.50·mV
1.0mV
2.0mV
2.0mV
3.0mV
MILrrARY TEMPERATURE RANGE
INPUT OFFSET VOLTAGE
DRIFT (TCVOS '
SUPPLY CURRENT
DEVICE
MAX.TA -25"C
DEVICE
MAX OVER
TEMPERATURE
OP-OBA
OP-OBB
OP-12A
OP-12B
PM-1OBA
PM-lOB
OP-OBG
OP-12G
0.6mA
0.6mA
0.6mA
0.6mA
0.6mA
0.6mA
O.SmA
O.SmA
OP-OBA
OP-12A
OP-OBB
OP-12B
PM-1OBA
OP-OBC
OP-12C
PM-lOB
2.S".V/oC'
2.5".V/oC
3.5".V/oC
3.5".V/oC
5.0".V/oC
10".vf C
10".Vf C
15".vf C
COMMERCIAL TEMPERATURE RANGE
INPUT OFFSET VOLTAGE
OP-OBE
OP-12E
OP-OBF
OP-12F
PM-3OBA
OP-OBG
OP-12G
PM-3OB
MAX. T A - 2SoC
O.l5mV
O.16mV
0.30mV
0.30mV
0.50mV
1.0mV
1.0mV
7.5mV
0.4nA
0.4nA
0.4nA
0.4nA
O.4nA
0.4nA
1.0nA
1.0nA
COMMERCIAL TEMPERATURE RANGE
INPUT OFFSET CURRENT
MILITARY TEMPERATURE RANGE
INPUT OFFSET VOLTAGE
DEVICE
MAX OVER TEMPERATURE
COMMERCIAL TEMPERATURE RANGE
SUPPLY CURRENT
MAX OVER TEMPERATURE
DEVICE
0.26mV
0.26mV
0.45mV
0.45mV
0.73mV
1.4mV
1.4mV
10.0mV
OP-OBE
OP-08F
OP-12E
OP-12F
OP-08G
OP-12G
PM-3OBA
PM-308
6-3
0.6mA
0.6mA
0.6mA
0.6mA
0.8mA
O.SmA
0.8mA
0.8mA
INPUT OFFSET VOLTAGE
D.RIFT (TCVOS '
DEVICE
MAX. OVER
TEMPERATURE
OP-OBE
OP-12E
OP-08F
OP-12F
PM-3OBA
OP-08G
OP-12G
PM-3OB
2.s".vfc
2.5".V/"C
3.5".vfc
3.5"vfc
5.0".vfc
. 10".vfC
10".V/"C
30".VfC
SINGLE LOW POWER OPERATIONAL AMPLIFIER SELECTION GUIDE
MILITARY TEMPERATURE RANGE
OPEN LOOP GAIN
MIN, T A = 2SoC
RL ;;>10KO
DEVICE
SOV/mV
SOV/mV
SOV/mV
SOV/mV
SO Vim V
SOV/mV
40V/mV
40V/mV
OP-OSA
OP-08S
OP-12A
OP-12S
PM-1OSA
PM-lOS
OP-OSC
OP-12C
MILITARY TEMPERATURE RANGE
OPEN LOOP GAIN
MIN OVER
TEMPERATURE
'4OV/mV
'4OV/mV
'40 Vim V
'40 Vim V
"40 Vim V
"2S V/mV
'lS V/mV
'IS V/mV
DEVICE
MIN, T A ~ 25"C
MIN OVER
TEMPERATURE
OP-OSA
OP-OSB
OP-12A
OP-12B
OP-OSC
OP-12C
'SOV/mV
'SOV/mV
'SOV/mV
'SOV/mV
N/S
N/S
"40 Vim V
"40V/mV
"40 V/mV
"40 Vim V
"lS Vim V
"IS V/mV
'RL ;;>2KO
"RL;;> SKO
'RL;;>SKO
"RL ;;>10KO
N/S - Not specified.
COMMERCIAL TEMPERATURE RANGE
OPEN LOOP GAIN
COMMERCIAL TEMPERATURE RANGE
OPEN LOOP GAIN
DEVICE
MIN, T A = 25°C
RL ;;>10KO
MIN OVER
TEMPERATURE
RL ;;>10KO
OP-08E
OP-08F
OP-12E
OP-12F
PM-3OBA
OP-OSG
OP-12G
PM-30S
BOV/mV
BO V/mV
SOVlmV
SOV/mV
SOV/mV
40V/mV
40V/mV
25V/mV
60V/mV
60V/mV
60V/mV
60V/mV
60V/mV
2SV/mV
2SV/mV
lSV/mV
DEVICE
MIN,TA=2SoC
RL ;;>2KO
MIN OVER
TEMPERATURE
RL ;;>2KO
OP-OSE
OP-12E
OP-OBF
OP-12F
OP-08G
OP-12G
SOV/mV
SOV/mV
30V/mV
30 Vim V
N/S
N/S
2SV/mV
2SV/mV
IS V/mV
ISV/mV
N/S
N/S
MILITARY TEMPERATURE RANGE
COMMERCIAL TEMPERATURE RANGE
COMMON MODE REJECTION RATIO
COMMON MODE REJECTION RATIO
DEVICE
MIN, T A - 2SoC
MIN OVER
TEMPERATURE
DEVICE
MIN, T A = 25"C
MIN OVER
TEMPERATURE
OP-08A
OP-OSB
OP-12A
OP-12B
OP-08C
OP-12C
PM-1OSA
PM-lOB
l04dB
l04dB
l04dB
l04dB
84dS
84 dB
N/S
N/S
100dB
lODdB
100dB
100dB
BOdS
BOdB
96dB
B5dB
OP-08E
OP-12E
OP-08F
OP-12F
OP-08G
OP-12G
PM-3OSA
PM-3OS
l04dB
l04dB
102 dB
102dB
84 dB
84 dB
N/S
N/S
lODdB
IODdB
lODdB
lODdB
BOdB
BOdB
96dB
SOdS
N/S - Not specified.
6-4
SINGLE PRECISION OPERATIONAL AMPLIFIER SELECTION GUIDE
MILITARY TEMPERATURE RANGE
UNNULLED INPUT OFFSET
NULLED INPUT OFFSET
VOLTAGE DRIFTITCVOSI
VOLTAGE DRIFT ITCVOSNI
MILITARY TEMPERATURE RANGE
INPUT OFFSET VOLTAGE
DEVICE
OP-07A
OP-07
SSS725A
OP-05A
OP-05
SSS725
OP-02A
PM-725
OP-02
MAX. TA -25"C
MAX OVER
TEMPERATURE
DEVICE
O.06mV
0.20mV
O.ISmV
0.24mV
0.70mV
0.70mV
1.0mV
1.5mV
3.0mV
OP-07A
SSS725A
OP-05A
OP-07
OP-05
SSS726
PM-725
OP-02A
OP-02
0.025mV
0.075mV
0.10mV
0.15mV
0.50mV
0.50mV
0.50mV
1.0mV
2.0mV
OP-07E
OP-07C
OP-07D
SSS725E
OP-05E
OP-02E
OP-05C
SSS725C
OP-02C
PM-725C
MAX. T A
=25°C
MAX OVER
TEMPERATURE
0.13mV
0.25mV
0.25mV
0.60mV
0.60mV
1.0mV
1.6mV
1_6mV
3.0mV
3.5mV
0.075mV
0.15mV
0.15mV
0.50mV
O.50mV
0.50mV
1.3mV
1.3mV
2.0mV
2.5mV
0.6 ",vfc
o.s",vfc
0.9 ",vfc
1.3 ",vfc
2.0 ",vfc
2.0 ",vfc
5.0 ",Vfc
*S.o",vfC
*10.0 ",vfc
DEVICE
TCVosnMAX
OP-05A
OP-07A
SSS726A
OP-05
SSS725
OP-07
0.5 ",vfc
0.6 ",vfC
0.6 ",vfC
1.0",vfc
1.0",VfC
1.3 ",vfc
COMMERCIAL TEMPERATURE RANGE
UNNULLED INPUT OFFSET
NULLED INPUT OFFSET
VOLTAGE DRIFT 1TCVOSI
VOLTAGE DRIFT ITCVOSNI
COMMERCIAL TEMPERATURE RANGE
INPUT OFFSET VOLTAGE
DEVICE
TCVosMAX
DEVICE
TCVosMAX
DEVICE
TCVosnMAX
OP-07E
OP-07C
OP-05E
SSS725E
OP-07D
1.3 ",vfc
*1.S vfc
*2.0 vfc
*2.0 vfc
*2.5 V/"C
*4.5 V/"C
*4.5 vfc
*S.O vfc
*10 vfc
OP-05E
SSS725E
OP-07E
OP-05C
SSS725C
OP-07C
OP-07D
0.6 ",vfc
0.6 ",vfc
1.3 ",Vfc
*1.5 ",vfc
*1.5 ",vfC
'1.6 ",vl'c
*2_5 ",vfc
Op,-06C
SSS725C
OP-02E
OP-02C
'Parameter is not 100% tested.
90% of all units meet these specifications.
MILITARY TEMPERATURE RANGE
INPUT OFFSET CURRENT
MILITARY TEMPERATURE RANGE
INPUT BIAS CURRENT
DEVICE
MAX.TA =2!i"C
MAX OVER
TEMPERATURE
DEVICE
MAX. TA = 25°C
MAX OVER
TEMPERATURE
SSS725A
OP-05A
OP-07A
OP-02A
OP-05
OP-07
OP-02
SSS725
PM-725
1.0nA
2.0nA
2.0nA
2.0nA
2.8 nA
2.8 nA
5.0nA
5.0nA
20 nA
4.0nA
4.0nA
4.0nA
5.0nA
5.6nA
5.6nA
10nA
IS nA
40nA
OP-05A
OP-07A
OP-05
OP-07
OP-02A
OP-02
SSS725A
SSS726
PM-725
2.0nA.
2.0nA
3.0nA
3.0nA
30nA
50nA
70nA
SOnA
100nA
4.0nA
4.0nA
6.0nA
6.0nA
55nA
l00nA
120nA
IS0nA
200nA
COMMERCIAL TEMPERATURE RANGE
INPUT BIAS CURRENT
COMMERCIAL TEMPERATURE RANGE
INPUT OFFSET CURRENT
DEVICE
MAX. T A = 25°C
MAX OVER
TEMPERATURE
DEVICE
MAX. T A - 25°C
MAX OVER
TEMPERATURE.
OP-02E
OP-05E
OP-07E
SSS725E
OP-02C
OP-06C
OP-07C
OP-07D
SSS725C
PM-725C
2.0nA
3.8nA
3.SnA
5.0nA
5.0nA
6.0nA
6.0nA
6.0nA
13 nA
35nA
4.0nA
5.3 nA
5.3nA
7.0nA
10nA
S.OnA
S.OnA
S.OnA
25nA
50nA
OP-05E
OP-07E
OP-05C
OP-07C
OP-07D
OP-02E
OP-02C
SSS725E
SSS725C
PM-725C
4.0nA
4.0nA
7.0nA
7.0nA
12nA
30nA
50nA
SOnA
IlOnA
125nA
5.5nA
5:5nA
9.0nA
9.0nA
14nA
55nA
100nA
l00nA
IS0nA
250nA
6-5
SINGLE PRECISION OPERATIONAL AMPLIFIER SELECTION GUIDE
MILITARY TEMPERATURE RANGE
POWER SUPPLY REJECTION RATIO
OVER TEMPERATURE
TA - 25°C
DEVICE
MIN (dBI
MAX (I'VlVI
MIN (dBI
MAX (I'VIVI
SSS725A
SSS725
OP-05A
OP-05
OP-07A
OP-07
PM-725
OP-02A
OP-02
114dB
l06dB
100 dB
l00dB
l00dB
100dB
100dB
90dB
90dB
2.0p.VIV
5.0p.V/V
101'V/V
101'V/V
101'V/V
101'V/V
101'V/V
301'V/V
301'V/V
l06dB
l02dB
94dB
94dB
94dB
94 dB
!l4dB
134 dB
84 dB
5.0I'V/V
8.01'VlV
201'V/V
201'V/V
201'V/V
201'V/V
201'V/V
6Ol'VIV
6Ol'VIV
COMMERCIAL TEMPERATURE RANGE
POWER SUPPLY REJECTION RATIO
OVER TEMPERATURE
TA =25"C
MIN (dBI
DEVICE
SSS725E
SSS725C
OP-05E
OP-07E
OP-05C
OP'07C
OP-07D
OP-02E
OP-02C
PM-725C
l06dB
l00dB
94dB
94dB
90dB
90d8
90dB
90dB
90dB
89dB
MAX (I'VlVI
MIN (dBI
MAX (I'VlVI
5.0I'V/V
10p.V/v
201'V/V
201'V/V
301'V/V
301'V/V
301'V/V
301'V/V
301'V/V
351'V/V
103 dB
96dB
90dB
90dB
86d8
86dB
86dB
84d8
84 dB
N/S
7.01'VIV
15l'VIV
301'V/V
30p.VIV
50l'VIV
50l'VlV
501'V/V
601'V/V
601'V/V
N/S
MILITARY TEMPERATURE RANGE
COMMON MODE REJECTION RATIO
MILITARY TEMPERATURE RANGE
OPEN LOOP GAIN
DEVICE
MIN. TA = 25°C
MIN OVER
TEMPERATURE
DEVICE
MIN. TA = 25"C
SSS725A
SSS726
OP-05A
OP-05
OP-07A
OP-07
PM-725
OP-02A
OP-02
120d8
120dB
114dB
114dB
110dB
110dB
110dB
90dB
90dB
114dB
110dB
110dB
110dB
l06dB
106 dB
100dB
84 dB
84 dB
SSS725A
SSS725
PM-725
OP-05A
OP-07A
OP-05
OP-07
OP-02A
OP-02
1000V/mV
1000VlmV
1000V/mV
300V/mV
300V/mV
200V/mV
200V/mV
100V/mV
50V/mV
COMMERCIAL TEMPERATURE RANGE
COMMON MODE REJECTION RATIO
DEVICE
SSS725E
OP-05E
PM-725C
OP-07E
OP-06C
OP-07C
SSS725C
OP-07D
PM-725C
OP-02E
OP-02C
MIN. T A = 25'C
120d8
110dB
110dB
106dB
l00dB
l00dB
l00dB
94 dB
94 dB
90 dB
90dB
MIN OVER
TEMPERATURE
700V/mV
500V/mV
250V/mV
200V/mV
200V/mV
150V/mV
150V/mV
50V/mV
25V/mV
COMMERCIAL TEMPERATURE RANGE
OPEN LOOP GAIN
MIN OVER
TEMPERATURE
116dB
107 dB
100dB
103 dB
97 dB
97 dB
97 dB
94dB
N/S
84 dB
84dB
N/S - Not specified.
6-6
DEVICE
MIN. T A - 25°C
SSS726E
SSS725C
PM-725C
OP-05E
OP-07E
OP-05C
OP-07C
OP-07D
OP-02E
OP-02C
1000V/mV
500V/mV
260V/mV
200V/mV
200V/mV
120 V/mV
120 V/mV
120 V/mV
100 V/mV
50 V/mV
MIN OVER
TEMPERATURE
800V/mV
300V/mV
125V/mV
180V/mV
180V/mV
100V/mV
1(10 V/mV
100V/mV
50 V/mV
25V/mV
SINGLE GENERAL PURPOSE OPERATIONAL AMPLIFIER SELECTION GUIDE
MILITARY TEMPERATURE RANGE
INPUT OFFSET VOLTAGE
DEVICE
OP·02A
OP·Ol
OP·02
OP·01F
SSS741
OP·01G
SSS741G
PM·741
MAX, T A
= 25°C
INPUT OFFSET CURRENT
MAX OVER
TEMPERATURE
DEVICE
1.0mV
1.0mV
3.0mV
3.0mV
3.0mV
6.0mV
6.0mV
6.0mV
0.5mV
0.7 mV
2.0mV
2.0mV
2.0mV
5.0mV
5.0mV
5.0mV
OP·Ol
OP·02A
OP·01F
OP·02
SSS741
OP·01G
SSS741G
PM·741
MAX, T A
=25°C
MAX OVER
TEMPERATURE
2.0nA
2.0nA
5.0nA
5.0nA
5.0nA
20nA
25 nA
200nA
4.0nA
5.0nA
10nA
10nA
10nA
40nA
50nA
500nA
COMMERCIAL TEMPERATURE RANGE
INPUT OFFSET CURRENT
INPUT OFFSET VOLTAGE
DEVICE
OP·02E
OP·01H
OP·02C
OP·01E
OP·01C
SSS741C
MAX, TA
=25°C
MAX OVER
TEMPERATURE
0.5mV
0.7mV
2.0mV
2.0mV
5.0mV
6.0mV
DEVICE
1.0mV
1.0mV
3.0mV
3.0mV
6.0mV
7.5mV
OP·01H
OP·02E
OP·01E
OP·02C
OP·01C
SSS741C
OPEN LOOP GAIN
OP-02A
SS5741
OP·Ol
OP·02
OP·01F
SSS741G
PM·741
OP·01G
MIN, T A
=25°C
100 V/mV
100V/mV
50V/mV
50 Vim V
50V/mV
50V/mV
50V/mV
25V/mV
DEVICE
50V/mV
50V/mV
30V/mV
25V/mV
25V/mV
25 V/mV
25 V/mV
15V/mV
OP·Ol
OP·02A
OP·02
OP·01F
S5S741
OP·01G
SSS741G
PM·741
OP-02E
OP·01H
OP·02C
OP·01E
OP·01C
SSS741C
=25°C
100V/mV
50V/mV
50V/mV
50V/mV
25 V/mV
25 V/mV
4.0nA
4.0nA
10nA
10nA
40nA
50nA
2.0nA
2.0nA
5.0nA
5.0nA
20nA
25 nA
MAX, T A
= 25°C
MAX OVER
TEMPERATURE
50nA
55 nA
100nA
lOOnA
100nA
200nA
200nA
1500 nA
30nA
30nA
50nA
50nA
50nA
100nA
100nA
500nA
COMMERCIAL TEMPERATURE RANGE
INPUT BIAS CURRENT
OPEN LOOP GAIN
MIN, TA
MAX OVER
TEMPERATURE
INPUT BIAS CURRENT
MIN OVER
TEMPERATURE
COMMERCIAL TEMPERATURE RANGE
DEVICE
=25°C
MILITARY TEMPERATURE RANGE
MILITARY TEMPERATURE RANGE
DEVICE
MAX, TA
MIN OVER
TEMPERATURE
DEVICE
OP·02E
OP·01H
OP·02C
OP·01E
OP·01C
SSS741C
50V/mV
30V/mV
25 V/mV
25 V/mV
15 Vim V
15V/mV
6-7
MAX, T A
= 25°C
30nA
30nA
50nA
50nA
100nA
100nA
MAX OVER
TEMPERATURE
50nA
50nA
100 nA
100 nA
200nA
200nA
SINGLE GENERAL PURPOSE OPERATIONAL AMPLIFIER SELECTION GUIDE
MILITARY TEMPERATURE RANGE
POWER5UPPLY REJECTION RATIO
TA
=25°C
OVER TEMPERATURE
DEVICE
MIN (dBI
MAX (pVIVI
MIN (dBI
MAX (pVIVI
OP-Ol
OP-02A
OP-02
OP-OIF
OP-OIG
555741
SSS741G
PM-741
SOdB
SOdB
SOdB
BOdB
BOdB
BOdB
76dB
76dB
30pV/v
30pV/V
30pV/v
l00pV/v
l00pV/V
100pV/V
150pV/V
150p.V/v
SOdB
B4dB
B4dB
BOdB
BOdB
BOdB
76dB
76dB
30p.V/V
60 pV/V
60 pV/V
l00pV/v
100p.V/v
l00p.V/V
150pV/V
150p.V/V
COMMERCIAL TEMPERATURE RANGE
POWER 5UPPLY REJECTION RATIO
OVER TEMPERATURE
DEVICE
TA =25"C
MIN (dBI
MAX (pVIVI
MIN (dBI
MAX (pVIVI
OP-01H
OP-02E
OP-02C
OP-OIE
OP-OIC
SSS741C
90dB
90dB
go dB
BOdB
BOdB
76dB
30pV/V
30pV/v
30pV/v
l00pV/v
100pV/v
150pV/V
90dB
B4dB
B4dB
BOdB
BOdB
N/S
30pV/V
60pV/v
60pV/v
100pV/V
l00p.V/V
N/S
MILITARY TEMPERATURE RANGE
COMMON MODE REJECTION RATIO
DEVICE
MIN, T A = 25"C
OP-Ol
OP-02A
OP-02
OP-OIF
OP-OIG
SSS-741
SSS741G
PM-741
90dB
gOdS
90dB
BOdB
BOdB
BOdB
70dB
70dB
MIN OVER
TEMPERATURE
gOdS
B4dB
B4dB
BOdB
BOdB
BOdB
70dB
70dB
COMMERCIAL TEMPERATURE RANGE
COMMON MODE REJECTION RATIO
DEVICE
MIN, TA = 25°C
OP-01H
OP-02E
OP-02C
OP-OIE
OP-OIC
SSS741C
90dB
90dB
90dB
BOdB
BOdB
70dB
6-8
MIN OVER
TEMPERATURE
90dB
B4dS
B4dB
BOdB
BOdB
N/S
•
DUAL PRECISION OPERATIONAL AMPLIFIER SELECTION GUIDE
MILITARY TEMPERATUR.E RANGE
UNNULLED INPUT OFFSET
NULLED INPUT OFFSET
VOLTAGE DRIFT ITCV OSN '
VOLTAGE DRIFTITCV OS'
MILITARY TEMPERATURE RANGE
INPUT OFFSET VOLTAGE
DEVICE
OP-l0A
OP-l0
OP-04A
OP-14A
OP-04
OP-14
MAX, T A
Z
2SoC
MAX OVER
TEMPERATURE
O.SOmV
O.SOmV
0.7SmV
0.7SmV
2.0mV
2.0mV
DEVICE
OP-l0A
OP-l0
OP-04A
OP-14A
OP-04
OP-14
0.70mV
0.70mV
1.SmV
1.SmV
3.0mV
3.0mV
TCVosMAX
2.0/LVtC
*2.0/LVtC
*S.O/Lvtc
*S.O/Lvtc
*10/LVrC
*10/LVrC
DEVICE
TCVosn MAX
OP-l0A
OP-l0
1.0/Lvtc
*1.0/Lvtc
'Parameter not 100% tested.
90% of all units meet those specifications.
COMMERCIAL TEMPERATURE RANGE
INPUT OFFSET VOLTAGE
DEVICE
OP-l0E
OP-04E
OP-14E
OP-l0C
OP-04C
OP-14C
MAX, T A
=2SoC
COMMERCIAL TEMPERATURE RANGE
MAX OVER
TEMPERATURE
UNNULLED INPUT OFFSET
VOLTAGE DRI FT ITCVOS'
O.60mV
1.SmV
1.SmV
1.6mV
3.0mV
3.0mV
O.50mV
0.7S mV
0.7SmV
1.3mV
2.0mV
2.0mV
DEVICE
MAX OVER
TEMPERATURE
OP-l0E
OP-10C
OP-04E
OP-14E
OP-04C
OP-1.4C
·2.0/LVtC
*4.S/LVtC
*S.O/Lvtc
*S.O/Lvtc
*10/LVtC
*10/LVtC
NULLED INPUT OFFSET
VOLTAGE DRIFT (TCV OSN'
DEVICE
OP-l0E
OP-l0C
MAX OVER
TEMPERATURE
*1.0/Lvtc
·1.S/LVrC
* Parameter not 100% tested. 90% of all units meet this specification.
MILITARY TEMPERATURE RANGE
INPUT OFFSET CURRENT
DEVICE
MAX, TA -25"C
OP-04A
OP-14A
OP-l0A
OP-l0
OP-04
OP-14
2.0nA
2.0nA
2.SnA
2.SnA
S.OnA
S.OnA
MILITARY TEMPERATURE RANGE
INPUT BIAS CURRENT
MAX OVER
TEMPERATURE
DEVICE
S.OnA
S.OnA
S.6nA
S.6nA
10nA
10nA
OP-l0A
OP-l0
OP-04A
OP-14A
OP-04
OP-14
COMMERCIAL TEMPERATURE RANGE
INPUT OFFSET CURRENT
DEVICE
MAX, TA -25"C
OP-04E
OP-14E
OP-l0E
OP-04C
OP-14C
OP-1OC
2.0nA
2.0nA
3.SnA
S.OnA
S.OnA
6.0nA
MAX, TA -25"C
MAX OVER
TEMPERATURE
3.0nA
3.0nA
SO.OnA
SO.OnA
7S.0nA
7S.0nA
6.0nA
6.0nA
100nA
100nA
12SnA
12SnA
COMMERCIAL TEMPERATURE RANGE
INPUT BIAS CURRENT
MAX OVER
TEMPERATURE
DEVICE
4.0nA
4.0nA
S.3nA
10nA
10nA
S.OnA
OP-l0E
OP-1OC
OP-04E
OP-14E
OP-04C
OP-14C
6-9
MAX, TA =25"C
4.0nA
7.0nA
SO.OnA
SO.OnA
7S.0nA
7S.0nA
MAX OVER
TEMPERATURE
S.SnA
9.0nA
SOnA
SOnA
12SnA
12SnA
DUAL PRECISION OPERATIONAL AMPLIFIER SELECTION GUIDE
MILITARY TEMPERATURE RANGE
COMMON MODE REJECTION RATIO
MILITARY TEMPERATURE RANGE
OPEN LOOP GAIN
DEVICE
MIN, TA =25"C
MIN OVER
TEMPERATURE
DEVICE
MIN, TA =25"C
MIN OVER
TEMPERATURE
Op-l0A
Op-l0
OP-: 2kl!
Large Signal Bandwidth INote 1)
Closed Loop Bandwidth INote 1)
1.0
18
-'
-
dB
fa' 10Hz
Input NOls~ Current Oef/sity
2.0
-
Avo
Channel Separation
0.5
100
Large Signal Voltage Gain
i np _p
mV
-
±13.0
R L ;:>: 2kl!
Input Noise Current
Units
2.0
90
Vom
en
Max
1:0
.12.0
Output Voltage Swing
Input Noise Voltage Density
Typ
-
-
Vs = ±5 to :!:20V
Rs:; 50kl!
8 np _p
Min
0.75
-
PSRR
I nput Noise Voltage
Max
0.3
110
Power Supply Rejection Ratio
Pd
Typ
-
90
V CM = tCMVR
Rs:; 50kl!
Power Consumption
Min
= 20Vp·p
Overshoot INote 1)
The following specifications apply for Vs'= ± 15V, -55°C
-
s: T A s: +125° C, unless otherwise noted
Yos
Rs:; 50kH
-
0.5
1.5
-
1.4
3.0
rnV
TCVos
Rs:; SkU
-
2.0
8.0
-
4.0
10.0
/Jvtc
los
-
1.0
5.0
-
2.0
10.0
nA
TClos
-
7.5
75
-
15
150
pAtC
IB
-
100
-
40
125
nA
Input Voltage Range
CMVR
, 12.0
-
±12.0
±13.0
-
V
Common Mode Rejection Ratio
CMRR
V CM = ±CMVR
Rs:; SOkf!
84
110
-
84
100
-
dB
Power Supply Rejection Ratio
PSRR
Vs = ±5 to ±20V
Rs:; SOkH
84
110
-
84
100
-
dB
100
-
25
60
-
V/mV
±13.0
-
±12.0
±13.0
-
V
Input Offset Voltage
AVE'rage Input Offset Voltage
Orift INote 1)
Input Offset Current
Average Input Offset Current Drift INote 1)
Input Bias Current
Large Signal Voltage Gain
Avo
RL2:2kf!
Vo=±10V
50
Maximum Output Voltage Swing
Vorn
RL 2: 2kH
'12.0
Note 1: Parameter is not 100% tested. 90% of all units meet these soecifications.
6·27
30
±13.0
OP-04
OP-04E
ELECTRICAL CHARACTERISTICS (Each Amplifier)
These specifications for
OP-04C
Vs ; ±lSV. TA; 2S"C. unless otherwise noted.
Symbol
Parameter
Input Offsat Vo Itege
Vos
Input Offset Currant
10 •
Input Bill Currant
Test Conditions
'B
Input Re.istance-Oiffarantial Mode
Min
Ain
Input Voltaga Ranga
CMVR
Common Mode Rejection Ratio
CMRR
Power Supply Rejection Ratio
PSRR
Vs= iSto-,20V
Rs S; 50k!!
Output Voltage Swing
Yom
RL 2. 2k!!
Large Signal Voltage Gain
Avo
V CM = lCMVR
Typ
Max
Typ
Max
Units
1.0
2.0
mV
-
1.0
5.0
nA
50
-
20
75
nA
--
2.3
7.0
-
Ml!
-
±12.0
±13.0
.-
V
0.3
0.75
0.5
2.0
-
18
3.8
7.5
±12.0
±13.0
R,S; 50kll
Min
90
110
-
90
100
-
dB
90
110
-
90
100
--
dB
±13.0
-
±12.0
±13.0
'-
V
'250
-
50
200
-
Vim V
40
60
-
50
90
mW
0.65
..
Rs S; SOk!!
RL 2. 2k!!
Vo = ,10V
±12.0
100
.Power Consumption
Pd
Input Noise Voltage
e np _p
Vo = OV
0.1 Hz to 10Hz
f o ·l0Hz
Input Noise Voltage Density
en
Input Noise Current
i np _p
Channel Separation
CS
'n
Large Signal Bandwidth (Note
11
BW
Input Offset Current
Average Input Offset'Current Drift INote 11
Input Bias Current
-
21
-
12.8
-
pA pop
-
-
dB
pA/,·!Hz
fo = 1000Hz
-
21
-
-
12.8
-
-
-
-
100
100
1,4
luHz
fo = 100Hz
,nV/,/Hz
1,4
-
0.7
-
-
0.7
0.4
-
0.4
0.5
0.7
-
0.5
0.7
-
V/~s
-
Va = 20Vp-p
4.0
8.0
-
4.0
8.0
-
kHz
AVCL = +1.0
0.8
1.3
-
0.8
1.3
-
MHz
-
200
300
-
200
300
nsec
-
5
10
-
5
10
%
1.5
-
1.2
3.0
mV
Overshoot INote 1)
Average Input Offset Voltage
Drift INote 1)
22
O.lHzto 10Hz
Y,N = 50mV
Input Offset Voltage
22
pop
~V
AV = +1
Risetime (Note 1)
The following specifications apply for
-
-
SR
Closed Loop Bandwidth INote 1)
25
-.
10= 1000Hz
Slew Rate (Note 1)
0.65
-
fa = 100Hz
10
Input Noise Current Density
-
25
V s ; ± 15V. O°C
:S T A :S +70°C. unless otherwise noted.
Rs S; 50kD.
-
Rs S; Sk!!
-
2.0
8.0
-
4.0
10.0
/.lVrC
los
-
0.7
4.0
-
1.4
10.0
nA
TClos
-
7.5
120
-
15
250
pArC
'B
-
22
50
-
25
125
nA
-
± 12.0
i 13.0
-
V
Vas
TCVos
0.4
Input Voltage Range
CMVR
Common Mode Rejection Ratio
CMRR
V CM = ±CMVR
Rs S; 50kll
84
110
-
84
100
-
dB
Power Supply Rejection Ratio
PSRR
V s =: i5 to ±20V
Rs S; 50kll
84
110
-
84
100
-
dB
200
-
25
150
-
V/mV
±13.0
-
± 12.0
113.0
-
V
± 12.0
Large Signal Voltage Gain
Avo
RL 2. 2kD.
Vo=±10V
50
Maximum Output Voltage Swing
Yom
RL2.2kD.
± 12.0
Note 1: Parameter is not 100% tested. 90% of all units meet these specifications.
6-28
113.0
•
OP-04
TYPICAL PERFORMANCE CURVES (Each Amplifier)
INPUT PFFSET CURRENT
VS TEMPERATURE
UNTRIMMED OFFSET VQLTAGE
VS TEMPERATURE
==
150 -
INPUT BIAS CURRENT
VS TEMPERATURE
"s'tlS'"
RS.50n
op.o~_
-+~--.....:~:---f-+-+--+--+-+--t--l
'O-l-I....
2ot-+:-------"1......t-I"-.~...±-I__;;;;obc--l-:::l:_
i"""---.
r--.......
OP-Q4A·-
\OP-04f
OP-04':
i"--
,OP-04
I
I
I I
OP-04E'
-"
-60
-40
~20
0
OPEN LOOP GAIN
VS TEMPERATURE
20
TEMPERATURE (OC)
TEMPERATURE-·C
OPEN LOOP FREQUENCY RESPONSE
CLOSED LOOP RESPONSE
FOR VARIOUS GAIN CONFIGURATIONS
120..--.-.,--,-,.-.,--,-,.,---.
I
I
OP-04
Vs,tt5V
./
,\
~'~'0~-'~0-4-270-+0--'2~0-1'O--'±'O--"~0~~~-4
TEMPERATURE
-~O~.I-~~~~oo~O--'+,,-~,O~'~~O~'-~~
OPEN LOOP GAIN VS
POWER SUPPLY VOLTAGE
CMRR VS FREQUENCY
120
OP-04
-TA"25"'t
".,
RL "0K
~
PSRR VS FREQUiNCY
Ulml Jll,
IIIII~ I
JI!~~011!1
III
UIJ!~onH
S·t15...
A'25"C
1!\5~
,0
IL
~
~
ol~J~I. ~,I~!
r---....
~200
2:
•
-20±IO--cL!:::--+---~IO~.--=IO~O'---+--"='
FREUlJENCY\Hz)
FREQUENCY(Hd
~·Cl
i\
100
i\
00
"
"0
.e
"pOWER SUPPlY VOLTAGE (VOLTSI
. .0
50
I
100
,.
FREOUENCY(Hz)
6-29
i\
50 I
100
.
FRE01.£NCV(Hz}
OP-04
TYPICAL PERFORMANCE CURVES (Each Amplifier)
INPUT SPOT NOISE
CURRENT VS FREQUENCY
INPUT SPOT NOISE
VOLTAGE VS FREQUENCY
INPUT WIDE BAND NOISE VS BANDWIDTH
(.1 Hz TO fREQUENCY INDICATED)
OP-O
Vs -t15V
TA'·25°C
~I."II
r. ._
10
10
000
a
1000
FREOUENCY (ii,!
MAXIMUM UNDISTORTED
OUTPUT VS FREQUENCY
I~LU~~~~~wm~~~~~
ot
10
10
100
01
OUTPUT VOLTAGE VS
LOAD RESISTANCE
•
10
INPUT RESISTANCE VS TEMPERATURE
O~'~~~~'~O~-LLU~~~~~~OO.O
+20
+6l1
TE'*ERATUR£ ("C)
FREQLEHCY (KHzl
POWER CONSUMPTION
VS POWER SUPPLY
01
BANDWIDTH (kHz)
FREQUfNCY (HzI
"<0
OUTPUT SHORT-CIRCUIT
CURRENT VS TIME
POWER CONSUMPTION
VS TEMPERATURE
to°mr---. .
20
f--rs.~t'c--F=-r--I=~*=l
r......
I
1
10
+--'--'--'-4--'---'---'--I----'---''-L......!
o
20
40
TOTAl SUPPLY VOLTAGE, V. TO '1-, (VOLTS)
",+--+-I-+--+-I--l---+-I--l----l
-60 -40 -20 0
ZO 40
60
eo lOa 120 140
TEMPERATURE (0C)
6-30
I
t5L-L--L.-=r::±:±±~
o
,
2
3
TIM£ FROM OUTPUT BEING
SH"RTED(~IMJTES)
OP-05
PMI
INSTRUMENTATION OPERATIONAL AMPLIFIER
GENERAL DESCRIPTION
FEATURES
_
_
•
_
_
_
_
_
•
_
_
•
•
_
_
The OP-05 Series of monolithic Instrumentation Operational Amplifiers combines superlative performance in low
signal level applications with the flexibility and ease of
application of a fully protected, internally compensated op
amp_ OP-05 characteristics include low offset voltage and
bias current and high gain, input impedance, .CMRR and
PSRR.
The OP-05 is a direct replacement in 725, 10BA and unnulled 741 sockets allowing instant system performance
improvement without redesign.
The OP-05 is an excelient choice for a wide variety of
applications including strain gauge and thermocouple
bridges, high gain active filters, buffers, integrators, and
sample and hold amplifiers. For dual matched versions,
refer to the OP-l 0 data sheet.
Low Noise • __ •.••... 0.6pV Pop Max., 0.1 to 10Hz
Low Drift vs. Temp .. _ .....•.... _ 0.51lVtC Max
Low Drift vs. Time •. _ ... _ •. _ • 0_ 31lV /Month Typ
Low Bias Current ..... __ . _ .. _ . _ ..... 2.0nA Max
LowVos_ .. __ • _ ...... _ .......•. 0.15mVMax
High CMRR. . . . . . . . . . . • . . • . . . . . . . . 114dB Min
High PSRR . . . . . . . . . . . . . . . . . . . . . • . 100dB Min
High Gain . . . . . . . . . . . . . . . . . . . • . 300,000 Min
High Rin Diff . . . . . . . . . . . . . . . . . . . . . 30MU Min
High Rin CM . . . . . . . . . . . . . . . . . . . . 200GU Typ
High Slew Rate ...••.......... 0.17 V/psec Typ
Internally Compensated ..... Stable to 500pF Load
Easy to Use ...••......•.....•• Fully Protected
Easy Offset Nulling . . . . . . . . . . . . . Single 20kU Pot
Fits 725, 108A and 741 Sockets
SIMPLIFIED SCHEMATIC
PIN CONNECTIONS AND ORDERING INFORMATION
'S'
VOSTRIM
tNV
INPUT 2
_
7 VOSTRIM
v+
NON INY INPUT 3
l'
6 OUTPUT
v-
4
&
TOP VIEW
•
.
"
VOII TRIM 3
IZ Vol T_
INY. INPUT 4
" y+
10 OUTPUT
NON-INY. INPUT II
Military Temperature
Range! Devices
With M I L-STD-SS3A
Class B Processing:
y- •
... v- (CASE)
EPOXY B MINI·DIP (P-Suffix)
ORDER: OP'()5CP
14 PIN DIP (Y-Suffix)
ORDER: OP·05AY
OP·05Y
OP-05EY
OP-05CY
6-31
TO-99 (J-Suffix)
ORDER: OP·05AJ
OP·05J
OP'()5EJ
Op·O~CJ
ORDER, OP05-SS3-AJ
OP05-SS3-AY
OP05-SS3-J
OP05-SS3·Y
OP-06
ABSOLUTE MAXIMUM RATINGS
-6lioC to +150°C
Storage Temperature Range
Operating Temperature Range
_55°C to +125°C
OP-05A, OP·05
O°C to +70°C
OP·05E, OP·05C
300°C
Lead Temperature Range (Soldering, 60 sec)
±22V
500mW
±30V
±22V
Indefinite
Supply Voltage
Internal Power Dissipation (Note 1)
Differential Input Voltage
Input Voltage (Note 2)
Output Short Circuit Duration
NOTES:
Note 1: Maximum package power dissipation vs. ambient temperature.
Package Type
Maximum Ambient
Temperature for Rating
Derate Above Maximum
Ambient Temperature
BO°C
100°C
62°C
7.1mWtC
10.0mWtC
5.7mWtC
TO-99 (J)
Dual·in-Line (Y)
Flat Pack (L)
Note 2: For supply voltages less than ±22V, the absolute maximum input voltage is equal to the supply Voltage.
OFFSET VOLTAGE TEST CIRCUIT
LOW FREOUENCY NOISE TEST CIRCUIT
200Kn
50n
OUTPUT
>-......-<>V.
V.
v•• "4Ocj(j
2.flNn
INPUT REFERRED NOISE· ~.
OFFSET NULLING CIRCUIT
~2~~~: ·200nV'clII
BURN·IN CIRCUIT
v+
OUTPUT
6
vAPPLICATIONS INFORMATION
OP-06 Series devices may be fitted directly to 725 and lOS/lOSA
Series sockets with or without removal of external compensation
components. Additionally, OP·05 may be fitted to unnulled 741
cautioned that stray thermoelectric voltages generated by dissimilar
metals at the contacts to the input terminals can prevent realization
of the drift performance indicated. Best operation will be
obtained when both input contacts are maintained at the same
temperature, preferably close to the temperature of the device's
package.
Series sockets; however, if conventional 741 nulling circuitry is in
use, it should be modified or removed to enable proper OP·05
operation. The OP·05 provides stable operation with load capaci·
tances up to 500pF and ±10V swings; larger capacitances should be
decoupled with a 50n decoupling resistor. The deSigner is
6-32
•
OP-05
OP-05A
ELECTRICAL CHARACTER ISTICS
OP-05
These specifications apply for V s = ± 15V, T A = 25°C, unless otherwise noted.
Parameter
Symbol
Test Conditions
Min
Input Offset Voltage
Long Term Input Offset Voltage Stability
VosfTime
(Note 11
Input Offset Current
Input Bias Current
O.1Hz to 10Hz
Input Noise Voltage
Input Noise Voltage Density
Input Noise Current
en
'np-p
Input Noise Current Density
(Note 2l
Typ
Max
Min
Typ
Max
0.07
0.15
0.2
0.5
mV
0.2
1.0
0.2
1.0
J,N/Mo
nA
.7
2.0
1.0
2.8
±.7
±2.0
±1.0
±:l.0
0.35
0.6
0.35
0.6
~9 :::: 10Hz
(Note 2)
10.3
18.0
10.3
'0· 100Hz
(No.e 2)
10.0
13.0
10.0
13.0
(Note 2)
9.6
11.0
9.6
11.0
(Note 2)
\4
30
14
30
fo= 10Hz
(No.e2)
0.32
0.80
0.32
0.80
fa
= 1000Hz
(No.e2)
0.14
0.23
0.14
0.23
(No,e2)
0.12
0.17
0.12
0.17
Input Resistance - Differential Mode
30
Input Resistance - Common Mode
so
20
200
nA
J,N pop
18.0
O.1Hz to 10Hz
fo'" 100Hz
Units
nV!VHz
pAp·p
pAiVHz
MU
60
200
Input Voltage Range
CMVR
±13.5
±14.0
±13.5
±14.0
v
Common Mode Rejection Ratio
CMRR
114
126
114
126
dB
Power Supply Rejection Ratio
PSRR
100
110
100
110
dB
300
500
200
500
150
500
150
500
V s "" ±3V to ±laV
RL ;;. 2kU. Vo· ± 10V
R L ;;'500U.V o ·±·5V
Large Signal Voltage Gain
V/mV
Vs "" ±3V
± 12.5
± 12.0
±13.0
± 12.5
±13.0
RL ;;. 2kU
± 12.S'
±12.0
±12.S
RL ;;. lkH
±10.5
± 12.0
±TO.5
±12.0
RL ;;. 10kU
Maximum Output Voltage Swing
V
Slewing Rate
SR
0 ..17
0.17
V/lJ:;ec
Closed Loop Bandwidth
BW
0.6
0.6
MHz
60
60
Open Loop Output Resistance
Power Consumption
90
Pd
90
120
Offset Adjustment Range
120
6
4
mV
4
4
mW
The following specifications apply for Vs = ± 15V, -55°C';; T A .;; +125°C, unless otherwise noted.
Input Offset Voltage
0.10
0.24
0.3
0.7
2.0
mV
Average Input Offset Voltage Drift
Without External Trim
TCVos
0.3
0.9
0.7
With External Trim
TeVos n
0.2
0.5
0.3
1.0
1.0
4.0
1.S
5.6
25
S
50
I nput Offset Current
Average Input Offset Current Dnft
TClos
Input Bias Current
Average Input Bias Current Drift
TCI B
±1.0
±4.0
8
25
Input Voltage Range
CMVR
±13.0
± 13.5
:t13.0
Common Mode Rejection Ratio
CMRR
110
123
110
Power Supply Rejection Ratio
PSRR
Vs
=
±6.0
13
50
± 13.5
V
123
dB
94
106
94
106
dB
400
150
400
V/mV
± 12.0
±12.6
±12.6
V
::t 12.0
NOTE 1: Long Term Input Offset Voltage Stability refers to the averaged trend line of Vos vs. Time over extended periods after the first
30 days of operation. Excluding the initial hour of operation, changes in Vos during the first 30 operating days are typically 2.5pV
Parameter ;s not 100% tested; 90% of units meet this specification.
NOTE -2: Paramete~·is not 100% tested; 90% -C:;i units meet this specification.
6-33
nA
200
± 3V to ± 18V
Large Signal Voltage Gain
Maximum Output Voltage Swing
±2.0
nA
OP-05
ELECTRICAL CHARACTERISTICS
OP-05E
OP-05C
These specifications apply for Vs = ±15V, T A = 25°C, unless otherwise noted.
Parameter
Symbol
Test Conditions
Min
Input Offset Voltage
Long Term Input Offset Voltage Stability
INote 1)
VoslTime
I nput Offset Current
I nput Bias Current
O.lHz to 10Hz
Input Noise Voltage
Input Noise Voltage Density
Input Noise Current
Input Noise Current Density
Typ
Max
Typ
Max
0.2
0.5
0.3
1.3
mV
0.3
1.5
0.4
2.0
IN/Mo
nA
1.2
3.B
1.B
6.0
± 1.2
±4.0
± 1.8
±7.0
0.35
(Note 2)
Min
0.6
0.38
0.65
(Note 2)
10.3
lB.O
10.5
20.0
fa = 100Hz
(Note 2~
10.0
13.0
10.2
13.5
fa'" 1000Hz
(Note 2)
9.6
11 .0
9.B
11 .5
O.1Hz to 10Hz
(Note 2)
14
30
15
35
0.80
0.35
0.90
fa'" 10Hz
(Not. 21
0.32
fa = 100Hz
(Note 2)
0.14
0.23
0.15
0.27
fa
(Nol.21
0.12
0.17
0.13
0.18
=
1000Hz
Input Resistance - Differential Mode
15
Input Resistance - Common Mode
50
33
160
120
Units
nA
JNp.p
pAp-p
Input Voltage Range
CMVR
± 13.5
± 14.0
±13.0
±14.0
v
Common Mode Rejection Ratio
CMRR
110
123
100
120
dB
Power Supply Rejection Ratio
PSRR
dB
Large Signal "voltage Gain
Avo
Vs =±3V to±18V
94
107
90
104
RL #: 2kn,V o "'±10V
200
500
120
400
R L ;;' 500n, Va = ± .5V
Vs = ±3V
150
500
100
400
± 12.5
± 12.0
±13.0
±12.0
±13.0
± 12.8
±11.5
±10.5
±12.0
± 12.8
± 12.0
RL ~ 10kn
RL ;;'2kn
R L ;;'lkn
Maximum Output Voltage Swing
Slewing Rate
SR
Closed Loop Bandwidth
BW
AVCL
=
+1.0
Open Loop Output Resistance
Power Consumption
Offset Adjustment Range
0.17
0.17
0.6
0.6
60
60
V/mV
V
V/J,lsec
MHz
90
120
95
150
4
6
4
8
mV
4
4
mW
The following specifications apply for Vs = ±15V, O°C .;; TA .;; +70°C, unless otherwise noted.
Input Offset Voltage
0.25
0.6
0.35
1.6
onV
Average Input Offset Voltage Drift
Without External Trim
Tevos
With External Trim
TCVosn
(Note 2)
Rp
=
20kn
0.7
2.0
1.2
0.2
0.6
0.4
4.5
1.5
(Note 2'
Input Offset Current
Average Input Offset Current Drift
(Note 2)
Input Bias Current
Average Input Bias Current Drift
TCI B
(Note 2)
Input Voltage Range
CMVR
Common Mode Rejection Ratio
CMRR
V CM = ± CMVR
Power Supply Rejection Ratio
PSRR
V s =±3Vto±18V
5.3
2.0
8.0
8
35
12
60
± 1.5
±5.5
±2.2
13
35
18
± 13.0
±13.0
± 13.5
107
123
90
104
86
100
180
450
100
400
± 12.6
± 11.0
Large Signal Voltage Gain
± 12.0
Maximum Output Voltage Swing
1.4
97
±9.0
Parameter is not 100% tested; 90% of units meet this specification.
6-34
nA
50
±13.5
V
120
dB
,±12.6
NOTE 1:1 Long Term Input Offset Voltage Stability refers to the averaged trend line of Vas vs. Time over extended periods after the first
30 days of operation. Excluding the initial hour of operation, changes in Vas during the first 30 operating days are typically 2.SJ1.V NOTE 2: Parameter is not 100% tested; 90% of units meet this specification.
nA
dB
VlmV
V
•
OP·05
TYPICAL PERFORMANCE CURVES
TRIMMED OFFSET VOLTAGE
VS TEMPERATURE
..
-
f-"oJOITftIMLED
UNTRIMMED OFFSET
VOLTAGE VS TEMPERATURE
TYPICAL OFFSET VOLTAGE
STABILITY VS TIME
TOlcl"VA~ IS"C t - - -
NULLING POT .lOkO
-~-
~-
r---
-
@OP-OOE
-, t--
@op-~c
~
-,
-
I
@OP-OO
/3'- 7-
--
~-~ L~
VJi1/
. ~,.
~
, N
--
,
"'-
q:~~\
~ I-- ~
~ ~ I-+.NJ.~
L
(!}oP-OOA
V
~:=I~- I--
.
, -,.
TDlflEItATUREI"CI
OP-OIA
..
J
'00
2
3
-4
!5
OFFSET VOLTAGE DRIFT
WITH TIME
OFFSET VOLTAGE CHANGE
DUE TO THERMAL SHOCK
-t-t+
+++-
-
;.:k-kL
6
7
8
9
10
..
12
TI"E-MONTHS
TEMPERATURE C"CI
TRIMMED OFFSET VOLTAGE
DRIFT ASA FUNCTION OF
TRIMMING POTENTIOMETER
,.• r-r-r-'R,..:p...;I,..:S_1Zr-E.,..A...,N_D...,V-=;o.:::s-,--o-=
~:::'~EO~-
CIjNAT2&"C
1
--~-
----
·
-,.
MAXIMUM ERROR VS
SOURCE RESISTANCE
_--+Ht
,..
rt
i'
LMlTRI .... ED -~I5·c toIU"(:
UNTRI....Eoi.a-e!t---; I) 1:[111
III'
--f
\ 'jj
.kt
~NA"~'
RESPONSE BAND
/I'"I
IA
I
V~NE~~~~:~r
20
.4
.•
.S
UNfIt ..... ED OF"'!T VOlJ'AlJl! Vos IIIIYI
I CUItYU ME SY.... ETRlCAI.. ABOUT ZEIlO FOR 'lot <01
40
10
TI"EI8£CONO$)
MAXIMUM ERROR VS
SOURCE RESISTANCE
MAXIMUM ERROR VS
SOURCE RESISTANCE
OP-OH
o·c" ?G"C
!
l
IL
•
~ 1.0
UlfrItlMMI!:D O-C I. ?G'"C
UNTRIM.ED 1O'"C
,
TIlIMMED 0·CI.7O"C.
.•,",•.,~I'-'-.l.I"-111u.11,,!:-1I--'--'-U.J.Wl-,._"_"lL-"-"-r°'...'.wl -'II
,
1.0
MAXIMUM ERROR VS
SOURCE RESISTANCE
.
~
ill
TR....DO"C .. 70"C
..,
• .0
'.'~
•.-,~---I,.•:--~~"'"",l:-.~-~.0.0,4
MATCHED'QURCE RESISTANCE (kG)
INPUT OFFSET CURRENT
VS TEMPERATURE
--
f--
ilill
1IIIIIiil
I.D
IIS"lIljill
-
, -
1IIIIIIi
10
MATCHED 1OU1ICt: ItOISTANCE lUll
·
~-I--
·
. .
~-~-~
~,:OH
lL
'I-1""""""7-1 oooj"' I l/
OPj_
~
T~t'"Cl
6-35
~-i
V.·*"~V
I
-
.,
'00
·
O"clll~ 70"C
UtI~"ED2.C
o
10
INPUT B.IAS CURRENT
VS TEMPERATURE
.:-:~:,;i~o.c. .
:::B1Btt.-r-1·j
'Tt11f·' :1
, i,
UNTf'I....ED
'nTi'
1111111
MATCHED SOURCE IIESISTANCE lUll
.....TtHEa OR \,Il(MATCHED 80IJRCE MilITANCE (1101
...
-
~-~-
-
V, ":l:IIIV
-+~
~
~f
~r,
"--:--+
.-
,.--
'r---r'~~---. . . . ,. , ; OPt L..-- V
I- -
. +-
V
. .
I
OPr"'' '
TEMPERATUItEt"CI
OP-05
TYPICAL PERFORMANCE CURVES
INPUT WIDEBAND NOISE VS
BANDWIDTH (.1Hz TO
FREQUENCY INDICATED)
INPUT SPOT NOISE VOLTAGE
VS FREQUENCY
0P·06 LOW FREQUENCY NOISE
0
1--
1=
t-
010 8 01
y,.,,,y
~
--- -
~
H,
' ••
tf--
••C-
I
~ Ij-t
.,
l=-- ,+
I=- ff
I
'
tt
.l)1[
I--'"
I ,.,
0.'
100
F"EQUEIrICYIHzl
1
j/
.j
.0
I
11
10
100
BANGWloTH tkHI}
CMRR VS FREQUENCY
J1
:::!J..!!!!l!:J ' 'J;I!'~.
! 1IIIIIililU
I !jIll!
I !IIIIIII Igl'!1f I . I '1I1I!ill i illil
I, ...;....I,'
-I +HllIP~4-I11111f-1+ii+tI' ttlHltH
'-I-+li
~ II
I~'i. I
1000
·o. -ol I
--
T,,"+H"C
I y,.,,,y I ':I,i ,
I,
I l .. "2&"C
+11
i 1:111
!,
._-
1"r+!I!t!ll!
1
000
"~~~~~4+~~-H,'~~~,~,
,!
'~'
1,1"
~
/'
.........
'~~~~~~~~~Hffiriitt~
I I
I
OPEN LOOP GAIN VS
POWER SUPPLY VOLTAGE
PSRR VS FREQUENCY
~
I
"~H+~-H~~~~~~I~iinnm
~ I
"~~4tt~Hm~ffiffl~r~~~I"
..
,
'.~~~WW~,oo~~~"~~IO~'~~IO"
CLOSED LOOP RESPONSE
FOR VARIOUS
GAIN CONFIGURATIONS
OPEN LOOP FREQUENCY
RESPONSE
,
,
I'.. -t
01',05
VS"tl!!'!'
T"o+2lI-c
"
,--
I
20r--~~ \ - i
.0
'00
"
FIIEQUENCY
OK
tH~1
,-
'0'
-.ol,,,--J.::---:!:-,-,-,,"';,'f';;,,-,-,,,"';,'''';--;;--;;;;:
~
0
I---
,
f0
TOTAr..SUl'PLYVOLTAGE,V+TOV-.IVOf..TSI
ILl
iL
OP-05
T.. -2e"C
V"!IIIV
VUt":tIOonV
!
I
,
.0'
,II
I
I
I
I
1111'
I
I
!
HtH
1\
!
I
"
LOAD RESISTOft TO GROUND IICOI
6·36
r
I'~ '
,
I
i'li ' II i'l'i
I
,
,
I:I!
r
!
:1; i
i'i
ii'
,
'I
i' WI i
I!,
i :11 11
0.'
FREQUENCY IMHII
'.0
INPUT BIAS CURRENT VS
DIFFERENTIAL
INPUT VOLTAGE
IIIIII
NEGATIVE SWING
~~
iil!l
i
I~
POSITIVE SWING
I1II
--
40
·,
·
·,
OUTPUT POWER VS LOAD
1--
Ill'l'l
,
"i
'iiifii'
0
POWER CONSUMPTION VS
POWER SUPPLY
20
1]1
y.-tIIY
-
"_'1
,.
,1
I J,UjIII
t-+--'
'\.
I
...
'"
MAXIMUM UNDISTORTED
OUTPUT VS FREQUENCY
I
0F"'l
I"'-..
.,,
II'OftJISUf> .. LY VOLTAIE I'I01.TII
'''EQUI:NC'I'tHIl
1--:----
1+
'0·
o
AT[VOWf'
I I I I
I I I I
IJ I I
I:EI.ov.II.I;::.~~::~:
V
1.-""
t1
.,
:5?nAIOf'-oICi
\G1
0
0
'0
..
.0
z7-
yt 0:1: IIV
V
T....
. 10
,
t-
I
I I
,
'0
DIFPERENTIAI.. INPUT VOLTMt:
..
.0
PMI
IOP-071
®
ULTRA-LOW OFFSET VOLTAGE OP AMP
GENERAL DESCRIPTION
FEATURES
The OP-07 Series represents a breakthrough in monolithic operational amplifier performance-Vos of 10llV,
TC Vos of O_2IlV t>C and long term stability of O_2p.V /month
are achieved by a low noise, chopper-less bipolar input
'transistor amplifier circuit_ Complete elimination of; external
components for offset nulling, frequency compensation
and device protection permits extreme miniaturization and
optimization of system Mean-Time-Between-Failure Rates
in high performance aerospace/defense and industrial applications. Excellent device interchangeability provides reduced
system assembly time and eliminates field recalibrations.
True differential inputs with wide input voltage range and
outstanding common mode rejection provide maximum
flexibility and performance in high noise environments
and non-inverting applications. Low bias currents and
extremely high input impedances are maintained over the
entire temperature range.
_
Ultra-Low Vos. _ . _ . _ .. _ . . . . . . . . . . . . . 10 p.V
_
_
Ultra- Low Vos Drift. _ . . . . . . . . . . . . . 0.2 p.Vt C
Ultra-Stable vs Time __ . . . . . . . . . . 0.2 p.V/Month
_
_
_
_
Ultra-L9w Noise _ . . . . . . . . . . . . . _. 0.35 p.Vp-p
No External Components Required
Replaces Chopper amps at Lower Cost
Single Chip Monolithic Construction
High Common Mode Input Range ..•... ±14_0V
Wide Supply Voltage Range ...... ±3V to ±18V
Fits 725, 108A/308A, 741,AD510 Sockets
SIMPLIFIED SCHEMATIC
- -
Low cost, high volume production of OP-07 is achieved by electronic adjustment of an on-chip offset trimming network during initial factory testing. The OP-07
provides unparalleled performance for low noise,
high accuracy amplification of very low level signals in
transducer applications. Othl1r applications include use in
stable integrators, precision summing amplifiers for analog
computation and test equipment and in ultra-precise voltage
threshold' detectors alid comparators. The OP -·07 is
recommended as a replacement for modular and monolithic
chopper-stabilized amplifiers where reductions in cost, noise,
size and power consumption are required. Devices are available i'n chip form for use in hybrid circuitry. The
IOP-07 is' a direct replacement for 725, 108A/308A, and
OP-05 amplifiers; 741-types may be directly replaceo
by removing the 741'5 nulling potentiometer.
~
Q5
INYETr
...
INPUT
I~
..,
.
''''''''..
Oft
~
''''''
"
,~
OS
05
114
"
.
'"
.n
..,
III
Qt4
~
(D
v*HOTe:: AU. a 11128 ARE EL£CTRONICAl.~Y AD.lUSTEO ON CHIP
nFACTOItYfPRMlNIMUMINPUTOFFlETYOLT.l.GE.
PIN CONNECTIONS AND ORDERING INFORMATION
'88
VOSTRIM
INV.INPUT 2
NO",NV. 'NPUT 3
v-
4
_
VOSTRIM
7 V+
.'
6 OUTPUT
5
EPOXY B MINI-DIP (P-Suffix)
ORDER: OP'()7CP
TOP VIEW
1_
._
Yo. TRIM
s-
IN'lINPUT 4_
-.......r-
ria
r-12
~
NON~IIN. INPUT 5 - ~ -- L
. . TftB~
f-14
I
v. T_
1V·
Class B Processing
...VE..,....
r-II V+
.NPUT 2
1 OUTPUT
r-10 OUTPUT
v· e-
r-.
NON-INVERT". ,
1-
f-a
INPUT
14 PIN DIP (Y-Suffix)
ORDER: OP-07AY OP'()7CY
OP-07Y
OP'()7EY
6-37
Militarv Temperature
Range Devices with
MIL-STD-883A
I
4V-(CAK,
ORDER: OP07-883-AJ
OP07-883-AY
OP07-883-J
OpQ7,-883-Y
TO-99 (J-Suffix)
ORDER: OP-07AJ .OP-07CJ
OP-07J OP-07DJ
OP'()7EJ
OP-07
ABSOLUTE MAXIMUM RATINGS
±22V
500mW
±30V
±22V
Indefinite
Supply Voltage
Internal Power Dissipation (Note 1)
Differential Input Voltage
Input Voltage (Note 2)
Output Short Circuit Duration
Storage Temperature Range
Operating Temperature Range
-55°C to +125°C
OP-07 A, OP-07
O°C to +70°C
OP-07E, OP-07C"OP-07D
300°C
Lead Temperature Range (Soldering, 60 sec)
NOTES:
Note 1: Maximum package power dissipation vs. ambient temperature.
Maximum Ambient
Package Type
Temperature for Rating
TO·99 (J)
Dual·in-Line (V)
Flat Pack (L)
Derate Above Maximum
Ambient Temperature
80°C
100°C
62°C
•
7.1mWiC
lO.OmWiC
5.7mWtC
Note 2: For supply voltages less than ±22V, the absolute maximum input voltage is equal to the supply voltage.
OFFSET VOLTAGE TEST CIRCUIT
LOW FREOUENCY NOISE TEST CIRCUIT
loon
loon
200KO
1~
~----~
A
-:.....
50n
-
2
~V
7
3.3kn
±.
.
~.
3+
7 PF
-=-
-15V
~P-O~~-4~-~OVO
t---------~~
OUTPUT
('\110Hz FILTER)
2.5Mn
~
Vo
Vos-4OOCi
Vo
5mV/cm
INPUT REFERRED NOISE' 25,000' 25,000 -200nV/cm
SEE NOISE PHOTO-PAGE 6
OPTIONAL OFFSET NULLING CIRCUIT
BURN·IN CIRCUIT
2~18l
~~
v+
OP-07
OUTPUT
>:8:--~-o
~./1
=
-18V
APPLICATIONS INFORMATION
The OP-07 provides stable operation with load capacitances up to
500pF and ± 1 OV swings; larger capacitances should be decoupled
with a 50n decoupling resistor. The designer is cautioned that stray
thermoelectric voltages generated by dissimilar metals at the con
tacts to the input terminals can prevent realization of the drift
performance indicated. Best operation will be obtained when both
input contacts are maintained at the same *~mperature, preferably
close to the temperature of the device's package.
OP·07 Series units may be fitted directly to 725. 108A/308A and
OP-05 sockets with or without removal of external compensation or
nulling components. Additionally. OP·07 may be fitted to unnulled
741-type sockets; however if conventional 741 nulling circuitry is in
use, it should be modified or removed to enable proper OP-07 operation. OP-07 offset voltage may be nulled to zero (or other desired
M
setting) through use of a potentiometer (see diagram aboveL
6-38
OP-07
ELECTRICAL CHARACTERISTICS
OP-07
OP-07A
These specifications a"ply for V s = ± 15V, T A = 25°C, unless otherwise noted.
Parameter
Input Offset Voltage
Long Term Input Othet Voltage Stability
Symbol
VOl
(Not. 1)
(Note 21
los
Input Bias Current
IB
Input Noise Voltage Density
Input Noise Current
Input Noise Current Density
Input Resistance - Differential Mode
I "put Resistance - Common Mode
e np _p
·n
inp- p
in
0.1 Hz to 10Hz
(Note 31
fa == 10Hz
(Note 31
'0
(Not. 31
== 100Hz
Typ
±.7
±2.0
--
0.35
0.6
----
10
25
0.2
1.0
·0.3
18.0
10.0
13.0
9.6
11.0
fa = 1000Hz
(Not. 31
O.lHzto 10Hz
(Note 31
--
14
30
fa = 10Hz
(Not. 31
--
0.32
0.80
fa = 100Hz
(Not. 31
--
0.14
0.23
fa = 1000Hz
(Note 31
--
0.12
0.17
126
-----
--
.30
80
--
200
CMVR
CMA'R
Power Supply Rejection R,tio
PSRR
Avo
2.0
10.3
Aio
Input Voltage Range
Max
-----
R inCM
Common Mode Rejection Ratio
Large Signal Voltage Gain
Min
VoslTime
I"put Offset Current
Input Noise Voltage
Test Conditions
±13.0.
VcM = ±CMVR
Vs '" ±3V to
110
±laV
±14.0
Min
Typ
--.
30
75
p.V
0.2
1.0
jiII/Mo
'0.4
2.8
nA
±1.0
±3.0
-----------
0.35
0.6
10.3
18.0
10.0
13.0
9.S
11.0
14
30
0.32
0.80
0.14
0.23
0.12
0.17
126
-----
20
60
--
200
±13.0
±14.0
110
Max
Units
nA
jill p.p
nVNHz
pAp-p
pAIy'Hz
M11
G11
V
dB
100
110
--
dB
---
200
500
150
500
---
V/mV
--
± 12.5
±13.0
--
±12.0
±12.S
--
±1O.5
±12.0
--
0.17
--
V//JSOc
60
---
MHz
50
------
75
120
75
120
4
S
4
S
100
110
RL > 2k!1, Va = ± 10V
300
500
R L >50011.v o =±·5V
150
500
Vs = ±3V
Maximum Output Voltage Swing
YoM
RL > 10k11
± 12.5
± 13.0
RL > 2k11
± 12.0
± 12.8
RL > lkU
±10.5
±12.0
Slewing Rate
SR
RL> 2k11
Closed Loop Bandwidth
BW
AVCL' +1.0
Open Loop Output Resistance
Ro
Va;; 0,1 0 = 0
Power Consumption
Pd
Offset Adjustment Ra"ge
-------
Vs =±3V
Rp - 2Ok11
0.17
0.6
±4
--
------
0.6
±4
V
11
mW
--
mV
The following specifications apply for V s = ± 15V, -55°C .;;; T A .;;; +125°C, unless otherwise noted.
Input Offset Voltage
Vas
(Note 11
TCVos
TCVos n
Rp = 20k11
--
25
SO
--
SO
200.
p.V
0.3
0.3
1.3
1.3
1.2
5.6
nA
S
50
pAi"C
Average Input ollset Voltage Drift
18
------
±1.0
±4.0
------
Average Input Bias Current Orift
TCI B
--
8
25
--
Input Voltage Range
CMVR
±13.0
±13.S
--
±13.0
Common Mode Rejection Ratio
CMRR
lOS
123
--
106
Power Supply Reiection Ratio
PSRR
Vs "'±3VtO±1SV
94
106
Avo
RL > 2k11.v o =±lOV
200
400
---
YoM
RL > 2.11
± 12.0
±12.6
--
Without External Trim
With External Trim
Input Offset Current
Averagj! Input Offset Current Drift
Input Bias Current
Large Signal Voltage Gain
Maximum Output Voltage Swing
los
TCI QS
VCM=±CMVR
0.2
0.6
0.2
O.S
O.S
4.0
5
25
±2.0
±S.O
13
50
±13.5
123
94
106
150
400
±12.0
±12.6
------
··p,V!"C
jiIIi"C
nA
pA/oC
V
dB
dB
V/mV
NOTE 1: Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application
of power. Additionally, OP-07 A offset voltage is measured five minutes after power supply appl ication at 25° C, _55° C and +125° C.
NOTE 2: Long Term Input Offset Voltage Stability refers to the averaged trend line of Vos vs. Time over extended periods aher the first
30 days of operation. Excluding the initial hour of operation, changes in Vos during the first 30 operating days are typically 2.5/lV Parameter is not 100% tested; 90% of units meet this specification.
NOl"E 3: Parameter is not 100% tested; 90% of units meet this specification.
6-39
V
OP-07
ELECTRICAL CHARACTERISTICS
OP-07C
OP-07E
OP-07D
These specifications apply for Vs - ±15V. T A: 25°C. unless otherwise noted.
Parameter
Input Offset Voltage
Symbol
Test Conditions
(Not. 11
Vos
(Not. 21
Min
Typ
Max
Min
Typ
-
30
75
-
60
Long Term Vos Stability
Vos/Time
Input Offset Current
los
Input Bias CUrrent
18
Input Noise Voltage
enp_p
a.1Hz to 10Hz
(Not. 31
-
Input Noise Voltage
·n
fo = 10Hz
f o = 100Hz
fo = 1000Hz
(Note 31
(Not. 31
(Not. 31
-
O.lHz to 10Hz
Density
Input Noise Current
inp-p
fo
Input Noise Current
Density
Input Resistance -
Diff. Mod.
Input Resistance-
in
= 10Hz
fo = 100Hz
fo = 1000Hz
0.3
1.5
0.5
3.8
'1.2
±4.0
0.35
-
-
10.3
10.0
9.6
18.0
13.0
11.0
(Not. 31
-
14
30
(Not. 31
(Note 31
(Not. 31
-
0.32
0.14
0.12
-
15
Ai"
-
160
-
RinCM
-
Input Voltage Range
CMVR
±13.0 ±14.0
Ratio
Power Supply Rejection
Ratio
Large Signal Voltage Gain
CMRR
VcM = ±CMVR
106
PSRR
Vs == ±3V to ±18V
Avo
RL;' 2kn. Vo = ±10V
RL;' 500n. Vo = ±.5V
0.80
0.23
0.17
50
Common Mode
Common Mode Rejection
0.6
123
Max
150
-
8
-
Max
150
Units
~V
2.0
-
0.5
3.0
~V/Mo
6.0
-
0.8
6.0
nA
.1.8
±7.0
-
±2.0
0.65
10.5
10.2
9.8
20.0
13.5
11.5
15
35
33
120
.13.0 "4.0
100
60
0.8
0.35
0.15
0.13
-
Typ
-
0.4
0.38
-
Min
120
0.90
0.27
0.18
"2
0.38
0.65
-
-
-
10.5
10.2
9.8
20.0
13.5
11.5
nV/$>
15
35
pAp-p
0.35
0.15
0.13
0.90
0.27
0.18
PAl$>
31
-
Mn
120
-
Gn
-
d8
dB
7
-
-
-
±13.0 ±14.0
94
nA
~Vp-p
110
V
94
107
-
90
104
-
90
104
-
200
150
500
500
-
120
100
400
-
120
400
400
-
-
-
-
-
'12.0 ±13.0
±l1.S .12.8
.12.0
-
-
±12.0 ±ta.a
-
±12.0 ±12.8
'11.5 ±12.8
-
-
MHz
-
n
-
V/mV
Vs == ±3V
Maximum Output Voltage
Swing
VoM
RL ;.10kn
RL;' 2kn
RL ;.lkn
±12.5 ±13.0
±10.5 ±12.0
-
Slewing Rate
SR
RL;' 2kn
-
0.17
-
Closed Loop Bandwidth
BW
AVCL = +1.0
-
0.6
-
-
Open loop Output
Resistance
Ro
Va"" 0,
-
-
Power Consumption
Pd
Vs"" ±3V
Offset Adjustment Range
'0 = 0
-
-
Rp =20kn
60
75
4
±4
120
6
-
0.17
0.6
-
-
0.17
0.6
-
60
80
4
±4
150
8
-
-
±4
150
8
-
85
250
-
85
250
60
80
4
V
V/p,sec
mW
mV
The following specifications apply for Vs: ±15V. O°C.;; T A';; +70°C. unless otherwise noted.
Input Offset Voltage
(Not. 11
Vos
-
45
130
-
~V
Average Input Offset
Voltage Drift
Without External Trim
TCVos
With External Trim
TCVosn
Rp = 20kn
Input Offset Current
los
Average Input Offset
Current Drift
Telos
Input Bias Current
18
Average Input Bias
Current Drift
TCIB
Input Voltage Range
CMVR
Common Mode Rejection
Ratio
Power Supply Rejection
Ratio
CMRR
VCM = .CMVR
PSRR
Vs:::: ±3V to ±18V
large Signal Voltage Gain
Avo
VoM
Maximum Output Voltage
SNing
NOTE 1:
NOTE 2:
NOTE 3:
'-
(Not. JI
(Not. 31
0.3
0.3
-
0.9
-
8
±1.5
-
13
"3.0 "3.5
103
123
90
104
RL;' 2kn. Vo = ±10V
180
450
RL;' 2kn
.12.0 ±12.6
1.3
1.3
5.3
-
0.5
0.4
-
1.6
(Not.31
1.8
1.6
(Not.31
8.0
1.6
±3.0
50
-
18
+13.0 ±13.5
12
50
±5.5
-
±2.2
18
-
±9.0
-
35
0.7
0.7
-
35
-
-
12
(Not.31
2.5
~V/oC
2.5
(Not.31
8.0
nA
50
±14
pArC
nA
50
pArC
V
dB
97
120
-
94
106
-
B6
100
-
86
100
-
dB
100
400
-
100
400
-
V/mV
-
"1.0 ±12.6
-
V
'13.0 +13.5
-
±11.0 ±12.6
Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application
of power.
Long Term Input Offset Voltage Stability refers to the averaged trend line of Vo. vs. Time over extended periods after the
first 30 days of operation. Excluding the initial hour of operation. changes in Vos during the first 30 operating days are
typically 2.5j.tV - Parameter is not 100% tested; 90% of units meet this
specification.
Parameter is not 100% tested; 90% of units meet this specification.
6-40
•
op-o~
TYPICAL PERFORMANCE CURVES
UNTRIMMED OFFSET VOLTAGE
VS TEMPERATURE
TR IMMED OFFSET VOL TAG E
VS TEMPERATURE
-
JDlTRI"~ED T01dJlv ,{ 20-<: -
-
I--
NUWII6PQT-20Ir.Q
_~OP-07'"
@OP-07E
@op-on:
~
3
~
~
~
..
-,
.......
~
-
I
.C!{.
~
-
."..".
j
~\J~-
I---+-+---t--+-
"
,
-~
,
TEMPERATURE ("CI
I
iIi!:
"
!5
I I
\
OP-07
~+---+-+-f__-+-+-~-~---I
~
III
i
I
I-f--
f--f-iii 10 f--f--
.
~
~
/i i"', '''I
e
!%lOP-07
(!)OP-07E
e0.61__---@>OP-07C------+-------I---1
~ ... f__---+--------I__--,.
.
~O
i!
~~:21I
:
\:-r:-:::
o~.,======~,~.o~~~~~~::==-=jIOO
1",21'
I
,
..
~
!'O~~§~~~
I
DEVICE .....ERSED
20
MATCHED OR UNMATCHED SOURCE RESISTANcE-Kn
INPUT BIAS CURRENT VS
TEMPERATURE
3
4
.
~12&·C
MAXIMUM ERROR VS
SOURCE RESISTANCE
'is'":tI5V
0
L
O"CS,T 5.7Q-C
.L
•
0.1
2
TIME AFTER POWER SUPPI,.Y TURN-QN-MINUTES
MAXIMUM ERROR VS
SOURCE RESISTANCE
o.
~I
I
40
60
TIME {SECOMDSI
-SS"C,:S.T
o.
20\-_-+__-'-____\-_-+____,
~
/(\
r-r-
,.0
V,-±I5V
ill OP-07A
~
8
~.. 15h------+------+-------I----+---I
RESPONSE BAND
Ilf
T,,-2'·C
;:0.8
7
WARM-UP DRIFT
>~
t.. . ~,
1-1-
-20
'.0,-----,-----.--___-,
\
V,-:tll\'
\
o
MAXIMUM ERROR VS
SOURCE RESISTANCE
6
I
\
t.k~~.
j
~~+---+-+-f__-+-+-~-~---I
~
-I2I--+-+-+-+++-f--f--+-+--j-j
OFFSET VOLTAGE CHANGE DUE
TO THERMAL SHOCK
+---+_+_f__-+-+Yti.o:l:15V
§~--'~~~+~-+--+-+--r-~--~
I-I--
TEMPERATURf i"el
OPEN lOOP GAIN VS
TEMPERATURE
j
/
(!l
~/7Jv~
~ru
OP-07A
I
I
@OP-07
OFFSET VOLTAGE STABiliTY
VSTIME
/
I
d?1
1.0
10
100
MATCHED OR UNMATCHEO SOURCE RESISTANCE (knl
INPUT OFFSET CURRENT VS
TEMPERATURE
E
i"'f__-+-+-~--+-+---t-+--;
a
~
~
01.0
VI~::t.IIIV
8
.
L
--?}
I
OP-07C
'I
OP-07E
0
0.'
1
1.0
10
100
MATCHED OR UNM,UCHED SOURCE RESISTANCE-1m
INPUT BIAS CURRENT VS
DIFfERENTIAL INPUT VOLTAGE
,
,
I
I
\
\
I
\
I
I
\
AT1Vo," I Sl.ov.I'.ls2nAtoP-07Al
;'
V
S3nA{OP-011
S7nAtop-01C)
U
,
~
k"
/
",_zIOV
T,"2ISiC- 20
OPf07A
-
TEMPERATURE ("Cl
6-41
-,
0
,
"~-_~--L--t,--~~.,~-L~r-~
-
-
-
°
10
10
DIFFERENTIAl- INPUT VOLTAGlt
OP-07
TYPICAL PERFORMANCE CURVES
INPUT WIDEBAND NOISE VS
BANDWIDTH
('1Hz TO FREQUENCY INDICATED)
TOTAL INPUT NOISE VOLTAGE
OP-07 LOW FREQUENCY NOISE
VS FREQUENCY
=
OP-07
V,.::tIIlY
TA·+25~
I
II
~I_tl==i--~_il 1·1·1'--'1=
-
OP-07_~..:
_LUI
s ·:tIIlVr
1-- -t++++ltt"'lt f-+-H+t1.ijj-YTA·25·~T
..l.....U.J.JJ.II":!;--'
i...w..u.":'±IO.;-J....lII...Ll.II~
-
"';!;;-,
.•
l--t
.J
,
·iiti-t~~t I
·
·
·
·
··
op-or
~
III
II
I'
I
I
I
"
I
Ik
FREQUENCYIHd
OPEN LOOP FREQUENl:V RESPONSE
o~
..•:: .
0
~P-07
1_
",
.
0'
0
I
!
FMQU["C'l'IH~1
·
II II
II II
d'!'7
T.. -+2S"C
\Is·tlllV
·
~1t·:tIOmV
,I
-r-:;
_ILl
~
't'
POSITIVE SWING
III1I
NEGATIVE SWING
'+-+-H+H~~-t-++H~f-+-f-Hf+ttll
.t--+--H-l-t-It1t----'\'jo...+H-ttttl--+++ttttH
.+-~~~~~~~N+~~=--'-U~.
'''''
'0
t:-t~~
V
T.. "+21i"C
IkD)
·
,
-1- f- -
~
-1--- - -
.l
~
I
20
40
6-42
,1_
Ii! VIN (PIN 51 • • rOlllY, VO'-15Y
I
....... :::,.."
I
.---t---
..1.1
~ ''''"~'''-IO'''Vo'+''''
'l'i
,
TOTAL. SUPPLY VOLTAGE, V+TO '1-, (VOL.TS)
1000
OP-07
T... ·+2.S·C
,,·,\8'1
i
,
ICO
FREQUENCY (KHll
OUTPUT SHORT·CIRCUIT'
CURRENT VS TIME
-
=
T9 GROUND
I
,
t-'I
LOAD REG'8TOA
MAXIMUM UNDISTORTED
OUTPUT VS FREQUENCY
T... "+25°C
=
~r'
,.. t-j
:tIS
V ·:t15V
---:{
iL
·
.
.TIO
TA"25"C
POWER CONSUMPTION
VS POWER SUPPLY
-f-r---f-
.......... ,........
..,s·:tlliY
fR[OU["C'T("~1
OUTPUT VOL TAG E VS.
LOAD RESISTANCE
;-...
POWER SUPPLY VOLTAGE (VOLTS)
'-L..:
..
101<
:5
OP-07
~
I I~
I I _I
l'
I II
·
·
--
/'
.+-+-+It-ttitlt--+-t .l!l!Jli
-f-f-Hf+ttll
s
~I
0
I~
100
I I
0
-
'-
10
·
·
·
~
FREQUEHCYUkl
0
100
I
CLOSED LOOP RESPONSE FOR
VARIOUS GAIN CONFIGURATIONS
V,-;tIIiV
I\..
o-
.
I
\.'}
T.. -+25"C
S
0
,
I
!
-
OP-a!
T,,-+2¥C
I
I
II
100
I~'ICI.
I
Ii
,II
'IN
I
!
~
I
10'
OPEN LOOP GAIN VS
POWER SUPPL Y VOLTAGE
I~!~~,.~
11:1.
I
I II:
10
BANDWIDTH (kH:ll
ilil J
III"IIIII~
"-'70 III
T,,_21i"C
I
I
I
1l11~tllllllll
IIIIIII
11:=1= -
Ill_ I II!
,n
PSRR VS FREQUENCY
V,-:tIIlV
l"-' i 1
-~f
I
iri/'q:.-
FREQUENCytHz)
CMRR VS FREQUENCY
II .1
/
o :-:-=
_.
1-
I
I
-.....:'
,
I'
~
I
"o
I
J
2.
3
TIME FROM OUTPUT BEINS SHORTED (MLNUTUI
•
PMI
UP-OB
PRECISION LOW INPUT CURRENT OP AMP
GENERAL DESCRIPTION
FEATURES
The PMI OP-08 is an improved version of the popular LM108A
low power op amp_ The OP-OO has a three times lower offset
voltage and a two times low~r offset voltage drift_ The total
worst case input offset voltage over -55°C to +125°C for the
OP-08 is only 350J.!V, while the 108A has 900J.!V to 1000J.!V
for these conditions_ In addition the OP-OO drives a 2kn load_
This is five times the output current capability of the l00A_
This excellent performanc,e is achieved by applying PMl's ionimplanted super beta process and on-chip-zener-zap trimming
capabilities. For devices with identical specifications plus
internal frequency compensation, see the OP-12 data sheet.
•
Low Offset Voltage _. ___ . __ . ___ . 150J.!V Max.
•
•
Low Offset Voltage Drift • _ • _ • _. 2.5J.!VtC Max.
Five Times PM108A Load Current _ ..• _5 mAMin_
Plus the Outstanding PM108A Features
• Low Offset Current _. _______ . __ . 200 pA Max.
• 'Low Bias Current. _ . ___ .. _ .. _ •.. 2.0 nA Max.
•
Low Power Consumption _. __ 18 mW max.
•
High Common Mode Input Range .• _ _ ±13.5V Min.
•
MIL-STD-883A Class B Processing Available
•
Silicon-Nitride Passivation
@
±15V
COMPENSATION CIRCUITS
SIMPLIFIED SCHEMATIC
R,
OUTPUT
R,
.1
Cs
R,
C'~RI +R z
c•
CS·IOOpF
(Improves rejection of power supply
noise by a factor of ten)
STANDARD
R,
R,
PIN CONNECTIONS AND ORDERING INFORMATION
o 0-'--+---- -....-OVo
6
Vo
Vos=1OOO
-Iav
LOW FREQUENCY NOISE TEST CIRCUIT
(0.1 TO 10 Hz)
10Kf!
S1.
l.5$1F
10Kn
1000
100.11
NOTES: 1.51 CLOSED MEASURES en (VOll.
2.51 OPEN MEASURES In AND'" (VOl)' ," IS COMPUTED FROM THE
TWO MEASUREMENTS.
3, COMPENSATION COMPONENTS NOT SHOWN BUT THEV ARE
CONNECTED.
4.
see NOISE PHOTO OF In IN TYPICAL PERFORMANCe CURVES SECTION.
6-44
r
•
OP-08
ELECTRICAL CHARACTERISTICS
OP-OSA
OP-OSB
OP-OSC
These specifications apply for Vs = ±15V, TA = 25°C, unless otherwise noted.
Parameter
Symbol
Test Conditions
Min
Typ
Max
Input Offset Voltage
Vos
-
0.07
0.15
Input Offset Current
Min
Typ
Max
Min
-
0.18
0.30
-
Typ
Max
0.25
1.0
Units
mV
los
-
0.05
0.20
-
0.05
0.20
-
0.08
0.50 nA
Input Bias Current
IB
-
0.80
2.0
-
0.80
2.0
-
1.0
5.0
nA
Input Noise VQltage
enp_p
0.1 Hz to 10Hz
-
0.9
0.9
-
/lV p.p
en
fa = 10Hz
fa = 100Hz
fa = 1000Hz
-
inp_p
0.1 Hz tQ 10Hz
in
fa = 10Hz
fo=100Hz
fa = 1000Hz
Input Noise Voltage Density
Input Noise Current
Input Noise Current Density
Input Resistance Differential Mode
Rin
Input Voltage Range
CMVR
-
-
22
21
20
-
-
-
3
-
-
0.15
0.14
0.13
-
0.9'
-
26
70
±13.5 ±14.0
-
-
22
21
20
-
-
-
-
-
3
-
-
-
0.15
0.14
0.13
-
-
26
-
10
-
70
-
±13.5 ±14.0
-
-
nVI.jHZ
-
3
-
pAp-p
-
0.15
0.14
0.13
-
pAI.jHZ
-
Mn
-
V
-
-
-
22
21
20
60
"3.0 ±14.0
VCM= ±CMVR
104
120
-
104
120
-
84
116
-
dB
Power Supply Rejection Ratio
PSRR
Vs = ±5V to ±15V
104
120
-
104
120
-
84
116
-
dB
Large Signal Voltage Gain
Avo
RL;>10Kn, Vo=±10V
RL;>2Kn,Vo =±10V
80
50
300
150
-
80
50
300
150
-
40
-
250
100
-
VlmV
Maximum Output
Voltage Swing
VoM
RL;> 10Kn
RL ;>2Kn
Common Mode Rejection Ratio CMRR
±13.0 ±14.0
±10.0 ±12.0
-
-
±13.0 ±14.0
±10.0 ±12.0
-
-
±13.0 ±14.0
. ±10.0 ±12.0
-
-
V
Slewing Rate
SR
RL ;>2Kn
-
0.12
-
-
0.12
-
-
0.12
-
VI/lsec
Closed Loop Bandwidth
BW
AVCL =+1.0
-
0.80
-
-
0.80
-
-
0.80
-
MHz
Open Loop Output Resistance
Ro
Vo=O,lo=O
-
200
-
-
200
-
-
200
-
n
Pd
Vs = ±15V
Vs = ±5V
-
9
3
18
6
-
9
3
18
6
-
12
4
24
8
Power Consumption
mW
The following specifications apply for Vs = ±15V, -55°C .; T A'; +125°C, unless otherwise noted.
Input Offset Voltage
Vos
-
0.12
0.35
-
0.28
0.60
-
0.40
Average Input Offset
Voltage Drift
TCVos
-
0.50
2.5
-
1.0
3.5
-
1.5
Input Offset Current
los
-
0.12
0.40
-
0.12
0.40
-
0.18
1.0
nA
TClos
-
0.50
2.5
-
0.50
2.5
-
1.0
5.0
pAloC
Input Bias Current
IB
-
1.2
3.0
-
1.2
3.0
-
1.8
Input Voltage Range
CMVR
Average I nput Offset
Current Drift
2.0
10
10
mV
/lV/"C
nA
.13.5 ±14.0
-
±13.6 .14.0
-
-
V
Common Mode Rejection Ratio CMRR
VCM= ±CMVR
100
110
-
100
110
-
8{)
106
-
dB
Power Supply Rejection R'aho
100
110
-
100
110
-
80
106
-
d8
40
120
-
40
120
-
15
80
-
VlmV
PSRR
Vs = ±5V to ±.15V
Large Signal Voltage Gain
Avo
RL;> 5Kn, Vo = ±10V
Maximum Output
Voltage Swing
VoM
RL;> 10Kn
RL;>5Kn
Power Consumption
Pd
±13.0 ±14.0
±10.0 ±13.0
6-45
9
-
18
±13.0 ±14.0
±10.0 .'3.0
-
9
18
.'3.0 ±14.0
.13.0 ±14.0
.'0.0 ±12.0
-
15 .
-
24
V
mW
op-os
OP-OSE
ELECTRICAL CHARACTERISTICS
OP-OSF
OP-OSG
These specifications apply for Vs = ±15V. T A = 25°C. unless otherwise noted.
Parameter
Symbol
Test Conditions
Input Offset Voltage
Vos
Input Offset Current
los
Input Bias Current
IB
Input Noise Voltage
enp_p
O.IHzto 10Hz
Input Noise Voltage Density
en
fo=10Hz
fo= 100Hz
fo= 1000Hz
Input Noise Current
Input Noise Current Density
-
Typ
13
2.0
-
0.9
-
3
-
in
0.15
0.14
0.13
CMVR
-
O.BO
fo=10Hz
fo = 100Hz
fo = 1000Hz
Input Voltage Range
-
0.20
22
21
20
-
26
70
Min
-
0.15
0.05
0.1 Hz to 10Hz
Rin
Max
0.07
inp_p
Input Resistance Differential Mode
Common Mode Rejection
Min
Typ
Max
O.IB
0.30
0.Q7
0.40
0.90
4.0
0.9
22
21
20
3
0.15
0.14
0.13 .
Min
-
-
-
-
10
60
±13.5 ±14.0
-
±13.5 ±14.0
-
-
-
Typ
Max
Units
0.25
1.0
mV
O.OB
0.50
nA
1.0
5.0
0.9
-
nA
/JV POp
-
22
21
20
3
0.15
0.14
0.13
-
nV/-/HZ
-
pA/..jHz
pAp-p
-
50
±13.i ±14.0
-
Mn
-
V
CMRR
VCM=±CMVR
104
120
-
102
120
-
B4
116
-
dB
PSRR
Vs = ±5V to ±15V
104
120
-
102
120
-
84
116
-
dB
Large Signal Voltage Gain
Avo
RL<>10Kn. Vo =±10V
RL<>2K.I1.Vo=±10V
BO
50
300
150
BO
30
300
120
-
40
-
250
100
Maximum Output
Voltage Swing
VoM
RL <> 10Kn
RL;;' 2K.I1
Slewing Rate
SR
RL;;' 2Kn
Closed Loop Bandwidth
BW
AVCL = +1.0
-
-
-
MHz
Ro
Vo=O.lo=O
-
200
-
.11
-
9
3
Ratio
Power Supply Rejection
Ratio
Open Loop Output
Resistance
Power Consumption
Pd
Vs = ±15V
'Vs=±5V
The following specifications apply for Vs = ±15V.
Input Offset Voltage
Average Input Offset
Voltage Drift
±13.0 ±14.0
±10.0 ±12.0
aOc "
0.12
O.BO
lB
6
-
±13.0 ±14.0
±10.0 ±12.0
-
0.12
-
O.BO
-
200
-
9
3
-
-
±13.( ±14.0
±10.( ±12.0
-
-
-
-
200
-
12
4
18
6
-
Vos
0.26
-
0.50
2.5
-
0.30
0.10
)
TCVos
-
los
-
O.OB
Average I nput Offset
Current Drift
TClos
-
0.50
2.5
-
1.0
3.5
-
1.5
-
0.11
0.60
-
0.12
0.70
nA
-
1.0
5.0
-
1.0
5.0
pArC
-
1.2
1.4
6.5
nA
IB
1.0
2.6
5.2
-
CMVR
±13.5 ±14.0
-
±13.5 ±14.0
-
±13.E
CMRR
VCM = ±CMVR
100
116
-
100
116
-
PSRR
Vs = ±5V to ±15V
100
116
-
100
116
-
Avo
RL;;>2K.I1. Vo - ±10V
RL;;>10Kn.V o =±10V
25
60
100
200
-
15
60
100
200
VoM
RL ;;.10Kn
RL;;' 2K.I1
Rejection Ratio
Large Signal Voltage Gain
Maximum Output
Voltage Swing
Power Consumption
Po
mW
-
Input Bias Current
Rejection Ratio
24
B
V//Jsec
0.45
0.23
Input Voltage Range
Power Supply
O.BO
V
T A :S;;;+70°C, unless otherwise noted.
Input Offset Current
Common Mode
0.12
V/mV
-
±13.0 ±14.0
±10.0 ±12.0
-
9
6-46
lB
-
9
lB
1.4
10
mV
/JVrc
-
-
V
BO
112
-
dB
BO
112
-
dB
- -
BO
150
-
.13.0
±10.0
±14.0
±12.0
-
-
15
25
±13.0 ±.14.0
±10.0 ±12.0
0.32
24
Vim V
V
mW
I
OP-08
TYPICAL PERFORMANCE CVRVES
LOW FREQUENCY NOISE
SMALL SIGNAL TRANSIENT RESPONSE
LARGE SIGNAL TRANSIENT RESPONSE
10pF
TRANSIENT RESPONSE
TEST CIRCUIT
Rs = 0, BW = 0.1 Hz to 10Hz
5 mV/div AT OUTPUT
10Kfi
0.5 p.V/div REFERRED TO INPUT
~-~----~-~OUT
INQ--4-'\I'I/'v-o--;
l00pF
OPEN LOOP GAIN (Avo) VS. SUPPLY
VOLTAGE (Vee) WITH
TEMPERATURE AS A PARAMETER
OPEN LOOP GAIN. (Avo) AND PHASE
VS. FREQUENCY
INPUT BIAS CURRENT
AND INPUT OFFSET CURRENT
vs. TEMPERATURE
~
"'--:"0.
",,'
-
.-
Cf~3p1
- ,
-.:.~-:;;.:. ."''.""'-
C.-1oo
',"<"
Ct~3p1/.
j,
"
~;
''/rh-
-
C.-IOOpf
/
ct-.pI
ii
",,' l'\.
I " - -~~I&v
,""
~
r-- r--TA-jC
I
i
.'-
"
QUIESCENT CURRENT (lSY) VS.
TEMPERATURE WITH SUPPLY
VOL TAGE AS A PARAMETER
we
~
TEIfIIII'IRATUIIE,'C
v... 1< VOLTII
QUIESCENT CVRRENT (lSY) VS.
SUPPLY VOLTAGE WITH
TEMPERATURE AS A PARAMETER
,..-
.11
i'kc-t-+--t-+-t-c-t-+--t--i
:::;
,we
....,
1'"
I
........ "'"
/' ~ V ""
........
./
Ia .. . /V
..
TlMI'IMTURlrCI
6-47
:::::::
......... ~
.........
~
POWER SUPPLY REJECTION RATIO IPSRRI
VS. FREOUENCY
OP-08
APPLICATIONS INFORMATION
The OP-08 series has extremely low input offset and bias currents; the user is cautioned that stray printed circuit board
leakages can produce significant errors, especially at high board
temperatures. Careful attention to board layout and cleaning
procedure is required to fully realize the OP-08 performance.
It is suggested that effects of board leakage be minimized by
encircling the input pins with a conductive guard ring operated
at a potential close to that of the inputs. This guard ring should
be driven by a low impedance source such as the amplifier's
output for non-inverting circuits, or be tied to ground for
inverting circuits.
TYPICAL APPLICATIONS
5 POLE ACTIVE FILTER
I
.Gl"F
01"r
5-POLE TELECOMM. FIL TEA"
USING 8 OP..Q8'S
3500 Hz
BW"'lSHz-3.SkHz
DdB
NOISE: <0 dBRn WITH A 15 kHz
FLAT FILTER AS MEASURED
IN AN HP 3551A TEST SET.
lOdB
*03 TYPE RECEIVE FILTER
The above realization of a type D3 receive filter is accomplished using eight OP-OS's. As can be seen from the response
curve, the >30 dB attenuation in the stop band requirement
has been met. In addition, the noise performance of <0 dBRn
has been measured. One of the unique features of the OP-OS is
its low supply current of 600 /J.A max. Thus the total supply
drain for all eight op amps is only 4.S mA.
20dB
Z
;;
"
lOdB
40 dB
SOdB
"-53.1 dB
1 kHl!
10kHz
100kHz
!lkHz)
6-48
op-os
TYPICAL APPLICATIONS
OCTAVE EQUALIZER
Cl
10KU
10KU
100Ka
Rl
lMa
R3
+15V
lMa
R3
>--....--oVo
The above circuit is one section of an octave equalizer used in
audio systems. The table shows the values of Cl and C2 needed
to achieve the given center frequencies. This circuit is capable
of 12 dB boost or cut as determined by the position of R2.
fo (Hzl
C1
32
64
125
250
500
1k
2k
4k
Sk
16k
0.1S/lF
0.1/lF
0.047/lF
0.022/lF
0.012/lF
0.0056/lF
0.0027/lF
0.OO1S/lF
680pF
360pF
Because of the low input bias current of the OP-08 the resistors cou Id be scaled up by a factor of ten, and thereby reduce
the values of Cl and C2 at the low frequency end. In addition
ten sections as shown above will only draw a combined supply
current of 6 mA maximum.
C2
0.01S/lF
0.01/lF
0.0047/lF
0.0022I'F
0.OO12/lF
560pF
270pF
150pF
68pF
36pF
BILATERAL CURRENT SOURCE
R2
1%
2MU
+15V
4MU
4Ma
R1
1%
R3
1%
E
IF Rl = R3 AND RZ = R4 + Rs THEN
IL IS INDEPENDENT OF VARIATIONS
INRL'
The above circuit will produce the above current relationship
to within 2% using 1% values for R 1 through R5. This includes
variations in RL from 10n to 2000n. The use of large
resistors for R 1 through R4 minimizes the error due to RL
variations. The large resistors are possible because of the excellent input bias current performance of the OP-08.
6-49
PMI
OP-09
QUAD MATCHED 741-TYPE OPERATIONAL AMPLIFIER
GENERAL DESCRIPTION
FEATURES
The OP-09 provides four matched 741-type operational
amplifiers in a single 14-pin DIP package. The OP-09 is pin
compatible with the RM4136 and RC4136 amplifiers. The
amplifiers are matched for common mode rejection ratio and
offset voltage. These parameters are very important in the
design of instrumentation amplifiers. In addition the amplifier
is designed to have equal positive-going and negative-going
slew rates. This is a very important consideration for good
audio system performance.
•
•
•
•
•
•
•
•
•
•
Each of the four amplifiers has the proven OP-02 advantages
of low noise, low drift and excellent long term stability. Precision Monolithics' exclusive Silicon-Nitride "Triple Passivation"
process eliminates "popcorn noise" and provides maximum
reliability and long term stability of parameters for 'Iowest
overall system operati ng cost.
Guaranteed Vos 50011 V MAX.
Guaranteed Matched CMRR __ . _ . _ .. 94 dB MIN_
Guaranteed Matched Vos . _ . _ .. __ 750 IlV MAX_
RM4136/RC4136 Direct Replacements
Low Noise
Silicon-Nitride Passivation
Internal Frequency Compensation
Low Crossover Distortion
Continuous Short Circuit Pro~ection
Low Input Bias Current
The OP-09 is ideal for use in designs requiring minimum space
and cost while maintaining OP-02-type performance. OP-09's
with processing per the requirements of MIL-STD-883A are
available. For dual-741-type versions, see the OP-04 and OP-14
data sheets.
EaUIVALENT SCHEMATIC
PIN CONNECTIONS
(1/4 CIRCUIT SHOWN)
-INPUT (A)
14 -INPUT (0)
+INPUT IA) 2
13 +INPUT 10)
OUTPUT (Al 3
12 OUTPUT 10)
v+
OUTPUT 18) 4
II
+ INPUT (B) 5
10 OUTPUT Ie)
-INPUT (B) 6
v-
9 + INPUT Ie)
7
8 -INPUT Ie)
TOP VIEW
(-lIN
1+) IN
C>--1--1:~~=l1_1-l:'
ORDERING INFORMATION
'--+-1-+-0 OUT
ORDER: OP'()9AY} -Ssoc TO +12SoC
OP'()9BY
OP.()9EY} O°C TO +70°C
OP'()9FY
Military Temperature Range Devices
With MIL-STD-883A Class B Processing
ORDER: OP09-883-AY
OP09-883"BY
6-50
•
OP-09.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
±22V
Internal Power Dissipation (Note 1 )
Operating Temperature Range
OP-09A, OP-09B
OP-09E, PO-09F
800mW
Differential Input Voltage
±30V
Input Voltage
Note 1: Maximum package power dissipation vs. ambient
temperature.
Supply Voltage
Continuous
(One Amplifier Only)
_65° to +150°C
Output Short Circuit Duration
Storage Temperature Range
Lead Temperature Range (Soldering, 60 sec)
M~XIMUM
300°C
Parameter
Input Offset Voltage Match
Common Mode Rejection
Ratio Match (Note 31
OP-09A
= ±15V, TA = 25°C, Rs '"
Symbol
aCMRR
OP-09E
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
10mW/oC
OP-09B
OP-09F
lOOn, unless otherwise noted.
Typ
Test Conditions
Min
(Note 4)
-
0.5
-
1.0
120
avos
AMBIENT
TEMPERATURE
FOR RATING
BO°C
14 Pin DIP (Y)
MATCHING CHARACTERISTICS
These specifications apply for Vs
-55°C to +125°C
OoC to +70°C
VcM =±CMVR
94
Max
Mi""
0.75
20
-
Typ
Max
-
O.B
2.0
-
1.0
120
20.
94
-
Units
mV
",VIV
dB
These specifications apply for Vs = ±15V, -55°C", TA '" +125°C for OP.Q9A and OP.Q9B, O°C '" TA '" +70°C for OP.Q9E and OP.Q9F
Rs '" 1 oon unless otherwise noted.
Input Offset Voltage Match
avos
Common Mode Rejection
Ratio Match (Note 3)
aCMRR
(Note 4)
VcM =±CMVR
-
0.6
-
3.2
110
94
1.0
20
-
-
1.0
-
3.2
110
94
2.5
20
-
mV
",VIV
dB
MATCHING PARAMETER DEFINITIONS
COMMON MODE REJECTION RATIO MATCH (~CMRR).
The difference between the common-mode rejection ratios
(expressed in volt/volt) of side A and side B. ~CMRR in
dB = -20 10910 (~CMRR in volt/volt). See note 3.
INPUT OFFSET VOLTAGE MATCH (t.vos). The difference between the offset voltages of side A and side B;
(VOSA - VOSB). See note 4.
TYPICAL APPLICATION
INSTRUMENTATION AMPLIFIER 2 OP-AMP DESIGN
A,
A,
A2
A4
>-->---0<,
EiIl20--------------'
GENERAL DESIGN CONSIDERATIONS
COMMON MODE REJECTION
Assuming ideal amplifiers, the expression for output voltage is:
Because the dual op amp has a high common mode rejection ratio
match, the ability to reject common mode inputs becomes primarily
a function of resistor ratio matching. This device eliminates the
need for special op amp selections in many instrumentation amplifier
applications.
With ideal resistors this simplifies to:
DIFFERENTIAL OFFSET VOLTAGE
The amplifier's differential input offset voltage (Eos2-Eosl) will
p.
the major error factor. If the individual input offset voltages are of
equal magnitude and polarity they appear as a common mode input
and are rejected.
6-51
OP-09
These specifications for Vs
=
OP-09B
OP-09A
ELECTRICAL CHARACTERISTICS (Each Amplifier)
±lSV, TA = 25°C, unless otherwise noted.
Parameter
Symbol
Test Conditions
Vos
Rs"; 10kn
Min
I nput Offset Current
los
-
Input Bias Current
IB
-
Input Resistance Differential Mode
Rin
Input Offset Voltage
Typ
8.0
180
0.40
0.20
Input Voltage Range
CMVR
Common Mode Rejection Ratio
CMRR
V CM = ±CMVR
R s ..;10kn
Power Supply Rejection Ratio
PSRR
Vs = ±5 to ±15V
Rs"; 10kn
Max
0.30
0.50
Min
-
25
50
300
500
nA
-
Mn
-
0.20
±13
-
±12 .
±13
100
120
-
100
120
-
dB
90
110
-
~O
110
-
dB
±11
±13
100
650
-
V/mV
123
180
RL;;' 2kn
±11
±13
RL;;.2kn
Va = ±10V
100
650
-
123
180
-
-
-
-
-
Power Consumption (Note 21
Pd
Va =OV
-
Input Noise Voltage
enp_p
0.1 Hz to 10Hz
Input Noise Voltage Density
en
fa = 10Hz
fa = 100Hz
fa = 1000Hz
-
CS
Input Noise Current Density
in
Slew Rate (Note 11
Risetime (Note 11
18
14
12
17
130
0.70
Va = 20Vp-p
BW
0.7
-
SR
Large Signal Bandwidth (Note 11
Closed Loop Bandwidth (Note 11
-
100
fa = 10Hz
fa = 100Hz
fa = 1000Hz
11
Overshoot (Note 1 1
-
-
-
100
1.8
1.5
1.2
-
-
-
-
1.0
-
16
1.5
AVCL = +1.0
AV =+1
VIN =50mV
0.40
nA
±12
VoM
Channel Separation
mV
-
Avo
O.IHz to.l0Hz
2.5
20
Large Signal Voltage Gain
inp _p
Units
Max
0.60
300
Output Voltage Swing
Input Noise Current
Typ
2.0
-
-
0.70
11
-
1.5
0.7
18
14
12
17
130
1.8
1.5
1.2
1.0
16
2.0
-
V
V
mW
J,lV pop
nV/.jHz
-
-
dB
-
pA/.jHz
-
V/p.s
pA pop
-
kHz
-
MHz
nsec
-
80
120
-
80
120
-
15
25
-
15
25
%
The fo",?wing specifications apply for Vs = ±15V, -5SoC '" TA '" +12SoC, unless otherwise noted.
Input Offset Voltage
Vas
Rs"; 10kn
-
0.40
Average Input Offset Voltage
TCVos
Rs"; 10kn
-
2.0
1.0
10
-
1.0
4.0
3.5
15
mV
J,lvl"c
Drift (Note 1 1
Input Offset Current
los
Average Input Offset Current Drift
TClos
-
20
0.10
-
40
200
-
400
±13
-
±12
±13
100
120
-
100
120
90
110
-
90
110
RL;;' 2kn
Vo = ±10V
100
250
-
100
250
VoM
RL;;' 2kn
±11
±13
-
±11
±13
Pd
Va =OV
-
115
200
-
115
Common Mode Rejection Ratio
CMRR
VCM= ±CMVR
Rs;;' 10kn
Power Supply Rejection Ratio
PSRR
Vs = ±5 to ±15V
Rs"; 10kn
Large Signal Voltage Gain
Ava
Maximum Output Voltage Swing
Power Consumption (Note 2)
NOTE 1: Parameter is not 100% tested. 90% of all units meet these specifications.
dissipation for all 4 amplifiers in package.
NOTE 3: Match exists between any two amplifiers.
NOTE 4: Usi ng amplifier A as reference then Ll Vos = V osn - V osA.
6-52
375
80
0.30
-
IB
CMVR
Tot~1
0.30
±12
Input Bias Current
Input Voltage Range
NOTE 2:
40
0.60
650
200
nA
nArC
nA
V
dB
dB
V/mV
V
mW
•
OP-09
These specifications for Vs = ±15V. T - 2SQC, unless otherwise noted.
Parameter
Symbol
Test Conditions
Input Offset Voltage
Input Offset Current
Input Bias Current
Input Resistan~e Differential Mode
Vos
los
IB
Common Mode Rejection Ratio
Ri"
CMVR
CMRR
Power Supply Rejection Ratio
PSRR
Input Voltage Range
Rs" 10k!l
Min
-
0.20
±12
VCM= ±CMVR
Rs" 10k!l
Vs· ±5 to ±15V
Rs" 10k!l
RL;;' 2k!l
100
90
Output Voltage Swing
VoM
Large Signal Voltage Gain
Avo
RL;;' 2k!l
Vo = ±10V
Power Consumption (Note 2)
Pd
enp_p
Vo=OV
O.IHz to 10Hz
-
en
fo - 10Hz
fo = 100Hz
fo= 1000Hz
O.IHz to 10Hz
-
Input Noise Voltage
Input·Noise Voltage Oensity
Input Noise Current
i np_p
Channel Separation
CS
Input Noise Current Density
In
Slew Rate (Note 1)
Large Signal Bandwidth'· (Note 1)
SR
Closed Loop Bandwidth (Note 1 )
Risetime (Note 1)
BW
.
Overshoot (Note 1)
The following specifications apply for
Input Offset Voltage
Average Input Offset Voltage
Drift (Note 1)
Input Offset Current
Average Input Offset Current Drift
Input Bias Current
Input Voltage Range
Va = 20Vp-p
0.40
±13
120
±13
650
-
-
0.70
11
1.5
300
~
-
110
100
-
Max
0.50
20
123
0.7
18
14
12
17
130
1.8
1.5
1.2
1.0
16
2.0
80
TClos
-
IB
CMVR
±12
In,
CMRR
Power Supply Rejecti·on Ratio
PSRR
Large Signal Voltage Gain
Ava
Maximum Output Voltage Swing
VoM
Pd
VCM- ±CMVR
R s "l0k!l
Vs ±5 to ±15V
R s "l0k!l
RL;;' 2k!l
Va = ±10V
100
RL;;' 2k!l
Vo=OV
20
0.10
200
±13
120
0.20
±12
100
Typ
0.60
Max
25
300
50
500
2.5
0.40
±13
-
120
-
110
±13
650
-
180
-
123
180
-
-
-
-
.,-
-
100
-
-
-
-
0.70
11
1.5
-
120
30
0.30
350
-
0.7
18
14
12
17
130
1.8
1.5
' 1.2
1.0
16
2.0
80
15
0.80
4.0
40
-
±12
0.30
400
±13
-
100
120
90
110
100
250
±11
±13
-
115
100
250
-
±11
±13
115
200
-
Units
mV
nA
nA
M!l
V
dB
dB
100
110
6-53
-
±11
-
90
-
Min
90
15
25
Vs = ±15V, O'C ... T A" +70'C, unless otherwise noted.
0.40
R s "l0k!l
0.80
Vas
2.0
10
TCVos
Rs" 10k!l
Common Mode Rejection Ratio
Power Consumption (Note 2)
AVCL -+1.0
AV +1
VIN= 50mV
Typ
0.30
8.0
180
±11
100
fo=10Hz
fo=100Hz
fo = 1000Hz
OP-09F
OP-09E
ELECTRICAL CHARACTERISTICS (Each Amplifier)
-
V
Vim V
mW
I'Vp-p
nVI-IHz
-
pA pop
dB
pAl-/Hz
-
VII's
kHz
MHz
120
nsec
25
%
3.0
15
I'V/'C
60
0.60
550
-
mV
nA
nAtC
nA
V
dB
dB
-
V/mV
V
200
mW
I
i
OP-09
TYPICAL PERFORMANCE CURVES
OFFSET VOLTAGE VS TEMPERATURE
-.'0
r'-",,-r-,--.--.--,.-.
-.20
t-+--j-+-+-+--+-+-+-I---J
OFFSET CURRENT VS TEMPERATURE
BIAS CURRENT VS TEMPERATURE
L.L
ol.os'
v~= t~Jv
Vs" '15V
-.6~6±:O---:_4!:-O---:_21:-0---!Of-.,l20:--:l40:-±60:-8:!:0"---"Of,O'-'21-0---l,40
~
•
~
0
TEMPERATURE lOCI
•
•
~
_
,. , •••
-60
800
./
600
2
400
"
+20
...'l-0"
5
20
I
16
>
0
TA = +25"C
RL=2K
\
\
«
E
vLW
\
24
5
o
1\
12
-20
i'-r-.
TIME.-:- ms
1.0
TIME - ms
1000
100
FREQUENCY (KHz)
OUTPUT VOLTAGE VS
LOAD RESISTANCE
QUIESCENT CURRENT VS
SUPPLY VOLTAGE
POWER CONSUMPTION VS
TEMPERATURE
140
POSITIVE
14
~JING
_ _ _ I-"
rI
NEGATIVE SWING
12
I
10
VS _ f15V
V1
IY
II
TA=25"
~
TA=+25 C
130
1-
Z
~
~
120
--
I-
8
vst.v
-
r- :---.
r-... r-...
1110
-...
1
2
0
0.1
1.0
LOAD 'RESISTANCE TO GROUND IKI
10
00
10
20
SUPPLY VOLTAGE (.tV)
6-55
30
40
10~60
-40
-20
0
20
40
60
TEMPERATURE (OCI
80
100 120 140
PMI
OP-l0
DUAL MATCHED INSTRUMENTATION OPERATIONAL
AMPLIFIER
GENERAL DESCRIPTION
FEATURES
The OP-l0 Series of Dual Matched Instrumentation
Operational Amplifiers consists of two independent
monolithic high performance operational amplifiers in a
single 14-pin Dual-in-Line package. For the first time, extremely tight matching of critical parameters is provided
between channels of a dual operational amplifier, whereas
previous dual op amp designs have made no attempt towards
matching.
The excellent specifications of the individual amplifiers combined with the tight matching and temperature tracking
between channels enables realization of extremely high performance instrumentation amplifier designs without resorting
to laborious and expensive selection and matching of discrete
amplifiers. The designer is assured of achieving the full performance guaranteed by the specification as the common
package eliminates the unavoidable temperature differentials
incurred by all designs utilizing separately housed amplifiers.
_
_
_
Extremely Tight Matching
Excellent Individual Amplifier Parameters
Tight Offset Voltage Match .... _ ... O.lSmV Max
_
Tight Offset Voltage Matchvs. Temp .. O_S /lVrC Max
Tight Common Mode Rejection Match .. 114 dB Min
_
Tight Power Supply Rejection Match ... 100 dB Min
Tight Bias Current Match ...... _ .... 2.S nA Max
, - Low Noise . . . . . . . . . . . . . . . . . . 0.6 /lVp-p Max
_
Low Bias Current ....... _ . . . . . . . . 3.0 nA Max
_
High Common Mode Input Impedance .. 200G.Q Typ
_
High Channel Separation _ . . . . . . . . . . 126 dB Min
Internally Compensated_ .. _ ... _ .. __ Easy to Use
_
Compact •. _ ..... ___ ..... 14 Pin Dip Package
Matching between channels is provided on all critical parameters including offset voltage, tracking of offset voltage vs.
temperature, non-inverting bias currents, and common mode
and power supply rejection ratios. The individual amplifiers
feature extremely low offset voltage, offset voltage drift, low
noise voltage, low bias current and are completely compensated and protected.
SIMPLIFIED SCHEMATIC
PIN CONNECTIONS AND ORDERING INFORMATION
TOP VIEW
1/20P-10)
NULL AI
NULL A 2
INY. INPUT A 3
NON-INV. INPUT A 4
y- B!S
OUTPUT 88
V+87
•
14V+A
13 OUTPUT A
12 V-A
II NON-IHY.INPUT 8
10 INY. INPUT 8
9 NULL
a
8 NULL B
14 PIN CERAMIC DIP (Y-Suffix)
ORDER: OP-10AY OP-l0EY
OP-l0Y OP-l0CY
NOTE: Device may be operated even if insertion is
reversed; this is due to inherent symmetry of
pin locations of amplifiers A and B.
6-56
OP-10
ABSOLUTE MAXIMUM RATINGS
±22V
500mW
±30V
±22V
Indefinite
Supply Voltage
Internal Power Dissipation (Note 1)
Differential Input Voltage
Input Voltage (Note 2)
Output Short Circuit Duration
NOTES:
_65°C to +150°C
Storage Temperature Range
Operating Temperature Range
_55°C to +125°C
OP-l0A,OP-l0
aOc to +70°C
OP-l0E,OP-1OC
Lead Temperature Range (Soldering, 60 sec)
300°C
1: Maximum package power dissipation vs. ambient temperature.
Maximum Ambient
Package Type
Temperature for Rating
Dual-in·Line (Y)
Derate Above Maximum
Ambient Temperature
106°C
11.3mWtC
2: For supply voltages less than ±22V, the absolute maximum input voltage is equal to tin! supply voltage.
BURN-IN CIRCUIT
OFFSET NULLING CIRCUIT
v+
1
3
INPUT
+
+18V
-IBV
+
INPUT
4
,
,
, OP-IO
,,
1\ ,
'13
,,
'12
,
'5
,
vv-
'6
MATCHING PARAMETER DEFINITIONS
INPUT OFFSET VOLTAGE MATCH tlIVosl The difference be·
tween the offset voltages of side A and side S; (VOSA -Vosal. In
Fig. 1 if VOSA = Vosa. the net differential offset voltage at the
output ~f the amplifier pair equals zero.
INPUT OFFSET VOLTAGE TRACKING (Tcb.Vosl The ratio of
the chal')ge in llvos to the change in temperature producing it.
AVERAGE NON·INVERTING BIAS CURRENT "B+l The average
of the side A and side B nonwinverting input bias currents;
ISA+ + 'SS+
2
NON-INVERTING INPUT OFFSET CURRENT
"0/1 The differ·
ence between the non-inverting input bias currents of side A and
side S; liSA + -
COMMON MODE REJECTION RATIO MATCH (I:'.CMRRI The
ISS +1.
difference between the common-mode rejection ratios (expressed in
volt /voltl of side A and side S. I:'.CMRR in dS = 20 log,o
"0.-1
INVERTING INPUT OFFSET ClIRRENT
The difference
between the inverting input bias currents of side A and side B;
"SA- - 'SS-I.
(I:'. CMRR in volt/volt)
SUPPLY VOLTAGE REJECTION RATIO MATCH (I:'.PSRRI The
differen~e between the power supply rejection ratios (expressed in
volt /voltl of side A and side B. I:'.PSRR in dS = 20 10910 (I:'.PSRR
in volt/voltl
AVERAGE DRIFT OF NON·INVERTING BIAS CURRENT
(TCl a+) The ratio of the change in non-inverting bias current to the
change in temperature producing it.
AVERAGE DRIFT OF NON-INVERTING OFFSET CURRENT
(TCl os+) The ratio of the change in non-inverting offset current to
the
ch~nge
CHANNEL SEPARATION The ratio of the change in input offset
voltage of one channel to the change in output voltage in the second
channel producing it.
in temperature producing it.
6-57
OP-l0
SPECIAL NOTES ON THE APPLICATION OF·DUAL MATCHED OPERATIONAL AMPLIFIERS
(For example, consider the case of two op amps, each with
80 dB (100j.LV!V) CMRR. However, if the CMRR of one
device is +100j.LV!V while CMRR of the other is -100j.LV!V
for a net 200j.LVlV CMRR match, the resultant input referred
error over a 10V common-mode input signal will be 2mV.)
ADVANTAGES OF DUAL MATCHED OPERATIONAL
AMPLIFIERS
Dual Matched Operational Ampl ifiers provide the engineer a
powerful tool for the solution of a number of difficult circuit
design problems including true instrumentation amplifiers,
extremely low drift, high common mode rejection D.C.
amplifiers, low D.C. drift active filters, dual tracking voltage
references and many other demanding applications. These
designs are based on the principle that careful matching
between two operational amplifiers can, to a large extent,
eliminate the effect of D.C. errors inherent in the individual
amplifiers.
Reference to the circuit shown in Fig. 1, a differential-in,
differential-out amplifier, shows how the reductions in error
can be accomplished. Assuming the resistors used are ideally
matched. the gain of each side will be identical; if the offset
voltages of each amplifier are perfectly matched, then the net
differential voltage at the amplifiers output will be zero.
Note that the output offset error of this amplifier is not a
function of the offset voltage of the individual amplifiers,
but only a function of the difference (degree of matching)
between the amplifiers' offset voltages. This error-cancellation principle holds for a considerable number of input
referred error parameters - offset voltage, offset voltage
drift, inverting and non-inverting bias currents, commonmode and power supply rejection ratios. Note also that the
impedances of each input, both common-mode and differential
mode, are extremely high and can also be tightly matched, an
important feature not possible with single operational amplifier
circuits. Common mode rejection can be made exceptionally
high; this is especially important in instrumentation amplifiers
where errors due to large common-mode voltages can be far
greater than those due to noise or drift with temperature.
POWER SUPPLIES
The V+ supply terminals are completely independent and may
be powered by separate supplies if desired (this approach,
however, would sacrifice the advantages of the power supply
rejection ratio matching). The V- supply terminals are both
connected to the common substrate and must be tied to the
sam e voltage.
OFFSET TRIMMING
Offset trimming terminals are provided for each amplifier
of the OP-10 - however, guaranteed performance over
temperature can be obtained by trimming only one side
(side A) to match the offset of the other for a net differential
offset of zero. (See Fig. 1) This is due to the specific procedure used during factory testing of the devices; however,
results which are essentially the same may be obtained by
trimming ,side B to match side A, or by nulling each side
individually.
The OP-10 is designed to provide lowest drift performance when trimmed with a 20kn. potentiometer; this value
provides about ±4mV of adjustment range which should be
considerably more than adequate for most applications. Where
finer resolution of trimming is desired, or where unwanted
changes in potentiometer position with time and temperature
could create unacceptable offsets, the sensitivity to offset vs.
potentiometer posit'ion may be reduced by using the circuit
of Fig. 2.
R3
20kQ
:>
0.27
0.13
0.18
33
-----
Mn
pA/v'Hz
160
±13.0
± 14.0
--
± 13.0
±14.0
106
123
100
120
90
104
--
dB
120
400
400
---
V/mV
8
--
120
94
107
± lOV
200
500
soon. Vo· ± .5V
150
500
--
100
± 12.5
± 12.0
± 10.5
± 13.0
----
± 12.0
±13.0
--
± 12.8
± 11.5
± 12.8
--
±12.0
--
'"
nA
jJV p.p
0.15
----
AL ~ 2kn, V 0
Large Signal Voltage Gain
Q.38
---
--
Input Resistance - Con"'1l0n Mode
I nput Voltage Range
0.35
Units
Gn
V
dB
Vs = ± 3V
RL ;;'lOkn
Maximum Output Voltage Swing
V oM
RL ;;'2kU
RL ;;'lkU
V
Slewing Rate
SR
RL ;;'2kn
-
0.17
--
---
0.17
._-
Vfp..sec
Closed Loop Bandwidth
BW
AVCL • +1.0
--
0.6
--
--
0.6
--
MHz
Open Loop Output Resistance
Ro
Vo = 0,1 0 = 0
--
50
--
... -
60
--
-----
90
120
95
150
4
6
---
4
8
Power Consumption
Pd
Rp .20kn
Offset Adiustment Range
Input Capacitance
Vs '" ± 3V
C in
± 12.0
±4
---
n
mW
--
±4
8
---
mV
--
0.35
1.6
mV
jJV t"C
pF
The following specifications apply for Vs; ±15V, O°C';;; TA .;;; +70°C, unless otherwise noted .
Input Offset Voltage
--
Vos
0.25
0.6
--
Average Input Offset Voltage Drift
Without External Trim
TeVos
With External Trim
TCVos n
Input Offset Current
Average Input Offset Current Drift
Input Bias Current
Average Input Bias Current Drift
Rp· 20kU
(Note 2)
--
0.7
2.0
--
1.2
(Note 2)
--
0.3'
1.0
--
0.4
4.5
1.5
---
1.4
5.3
8.0
nA
8
35
12
50
pA/oC
--
± 1.5
±5.5
---
2.0
(Note 2.
±2.2
(Note 2)
--
13
35
--
18
los
TClos
Ie
TCI B
Input Voltage Range
CMVR
Common Mode Rejection Ratio
CMRR
Power Supply Rejection Ratio
PSRR
VCM = ± CMVR
± 13.0
± 13.5
103
123
Vs "'±3Vto±18V
90
104
Large Sigl'lal Voltage Gain
Avo
RL ;;'2kU. Vo - ± 10V
180
450
MaMimum Output Voltage Swing
V oM
RL ;;. 2kU.
t 12.0
-----
±12.6
±9.0
nA
50
pAfoC
86
100
----
100
400
-
± 13.0
97
±11.0
± 13.5
120
V
dB
dB
V/mV
± 12.6
NOTE 1: Exclude first hour of operation to allow for stabilization of external circuitry. Parameter is not 100% tested;
90% of all units meet this specification.
NOTE 2: Parameter is not 100% tested; 90% of all units meet these specifications.
6-62
V
I
OP-10
TVPI.CAL PERFORMANCE CURVES
MATCHING CHARACTERISTIC
TRIMMED OFFSET VOLTAGE MATCH
VS TEMPERATURE
~40!----f-?
MATCHING CHARACTERISTIC
MATCHING CHARACTERISTIC
TRIMMED MATCHED OFFSET VOLTAGE DRIFT AS A
FUNCTION OF TRIMMING POT (Rp) SIZE AND jlV..
CHANNEL SE:PARATION VS FREQUENCY
""
6.VuTRIIllNEPTOCS,&VAT21i,,<:+J
1
NULLIftli POT "tOkA
~
I OP-10AIL_
:I 30
l OP-\OE
0$'-10
II
~
i"-i'
,
i"
01"-10.11
or-- Ys":t'5"
TA"2eee
0
10
.2
A
~
.•
I~
UNTRIMMED OFFSET VOLTAIE MATCH 4Yot tlllvi
tcuRv£a ME SYMMETRICAL AlOUT ZERO FOR av. -
~ 20t--,L--?:\
~
~
oi';ICI!~.·
3
~
10t---j--j--,
DE'IICI"c-
TI_IIIONTM,)
TEMPERATURE I"C)
6-63
OP-10
TYPICAL PERFORMANCE CURVES
CMRR VS FREQUENCY
.
, ~vi~h
~
"0
0
.".Il!~
IIIIIII
Y.'!:t:'I'"
1/20p·roc
CLOSED LOOP RESPONSE
FOR VARIOUS GAIN CONFIGURATIONS
PSRR VS FREQUENCY
IIIIIII
II:'UJSr~
!III
I 11111111
1/20P-l0C
T,,-II-C
I
,
~~I
,
L+:~l\t+ttttIll-H-tffiII--t-tttttllt
0
·t-t+ttHtIH-tttitlt-/-Hf~"~~+lI+H!IH-1-Hl!III
~
'0
100
~,
,
"
OPEN LOOP GAIN VS POWER
SUPPLY VOLTAGE
~
I\..
0
1120P-10
I\..
I\..
~
,
,
,
.,
"
,
"
-.
MAXIMUM UNDISTORTED OUTPUT
VS FREQUENCY
./
I _
T,,-+WC
f---
......
OUTPUT SWING VS LOAD
112~1~
II II
Illl
".-*IO.V
ii'l
,
-
l.-- f -
-10
,-
100
"
POWER CONSUMPTION VS
POWER SUPPLY
-I- t--~,,2.O:;!~C ~.
V
'"
filEMTlYI . . . .
~'
f---
0
POI",.._
I
:
"
llo ----, '"b '
:itZ
_1..1/
~
~
I
~
i •
\
..
~,t~~,~~~~.~--~-U~o~.,~---U~
""IQUI:IICY'Mthll
1/2oP-10
·t.k.t,;~.
~
INPUT BIAS CURRENT VS
TEMPERATURE
40
10
.,.-
./
I
V,-tIIlY
AT IVoi,,1 ~HOY.
ItTI'-C
-11,1
~511A11/2
V
.
0"-10&'112:
V
.
OP~101-
IJ.I 57'" 11/2 OP-IOCI
,. ~_L~'
/f I I
r-I-
.
INPUT BIAS CURRENT VS
DIFFERENTIAL INPUT VOLTAGE
I
• r- Ir-Ir- Ir-I-
zo
TOTal. .UP....., YOuMI, V+TO V-, lVOLT11
I
I
I
1
1
:;".......
V.-'l"IV
c
.
,..
LOAD RE"ITCMt TO ...OUIIO '1101
I I
I
II
iJ
••.,
OFFSET VOLTAGE CHANGE
DUE TO THERMAL SHOCK
•-zo
,
",-*.-v _
-'
..
i;
,
,
~
,""
IIloti-IO
-
........ .......
T,,-.IPC
'Is- tllV
.
.
~
..
'ItEOUElfCYIIM
-
~
0
~
~
OPEN LOOP GAIN VS TEMPERATURE
11201.10
-
T,,--+;IPC
0
0
100
'--
VI-trIY
"
0
"-
'''t:OUIIifCY (HEI
OPEN LOOP FREQUENCY RESPONSE
Or-
0
III
'''hUlK' Ub'
~
I
I
... "I
,
.ot-++tItttII-+tt+IlIII-+f+tl!III-\l-x'1I:_++++1lIII
'0
T.·I~
~
N
I
0'-10
Va-tIlY
flElPOfIH lAND
,
A I I I
~ii"I'ATi
..
,
,
I
~
~I
~
1I10"~:~
112010-1
OfWCI IMIllUMD
zo
"-
..
TillE ,alCOHOl'
V.
I-- I-~
I I
. .
T£..",,,ATUM (-Cl
6-64
V
-'?
•
I
,
~~
~*tI5V
-"
Ta- 211iC
I
'00
-00
-'0
I
-20
-to
0
10
DIf'FlEItENTtAL INPUT VOLTAft
~
.
., so
I
OP-,10
APPLICATIONS INFORMATION
TRIPLE OP-AMP INSTRUMENTATION AMPLIFIER
CMRR VS FREQUENCY
INSTRUMENTATION AMPLIFIER (3 OP-AMP OESIGNI
r-----'
Itt ZOk4
R42kO
1-
01
lkA
!1I°t-+t-ttttllti
VOS-O,oefllV
~·."'VI'C
I
RS
.UI
NOtIE·O.S,.Vp-p
R8II-'008'"
""L
OUTPUT
100
....
01
V"T·VI.(I·~l~
GAIN-IOO
GAIN LIN - :t: .002"-
SLEW RATE
=2.6V/,..sec
PlRR-1I211.
1'21-;
OP-IOA
THEN CMRR-120••
TYPICAL PERFORMANCE OF INSTRUMENTATION AMPLIFIERS
GAIN = 100
PARAMETER
INSTRUMENTATION AMPLIFIERS USING OP-10
Instrumentation Amplifiers with performance surpassing those cost·
ing many hundreds of dollars can be easily and compactly built
uSing the OP-10. Typical performance for a 21 and 3-amplifier
design are given in the table. The 3-amplifier design, while more
complex, has the advantages of convenient overall gain adjustment
by trimming a Single resistor IR31 and of wide common-mode
voltage handling capability at any overall gain, plus improved gain
linearity. Slew rate, small signal bandwidth and full power bandwidth are also superior and may ba further improved by choosing a
high-speed op-amp such as the OP-01 series for the outputlop-amp.
Gain Nonlinearity
Initial Input,Offset Voltage
vs. Temp (atnplifier A
nulled with 20K pot)
vs. Time
Input Bias Current
3 OP AMP
DESIGN
.004%
.001% IOP·051
.002% IOP.oll
70jJV
7511N
0.3jJV/oC
0.3jJV/C
3.Sp.V Imonth
3.5/.N Imonth
±1.0nA
±1.0nA
10pA/oC
lOpAtC
O.BnA
O.BnA
12pAtC
12pA/oC
BOGU
looGU
0.5jJV p.p
looGU
looGU
0.5jJV p.p
Input Noise Current
(.1 to tOHz)
14pA p.p
14pA pop
Common Mode Rejection
l20dB
112dB
120dB
VS. Temp.
Input Offset Current
VS. Temp.
Input Impedance
Differential
COmmon Mode
Inpot Noise Voltage
(.1 to 10Hz)
INSTRUMENTATION AMPLIFIER 2 OP-AMP DESIGN
2 OP AMP
DESIGN
Power SupplV Rejection
112dB
Frequency Response
PRECISION DUAL
USINGOP-10
TRACKING
VOLTAGE
6.0kHz
FulfPower
2.5kHz
S~W
.11V/p.s
Rate
26kHz IOP·051
B5kHz IOP·O,.1
4.3kHz IOP·OSI
43kHz IOP·Ol I
0.17 V/jJsec IOP·051
4.0V/jJ"'c IOP·Oll
Precision dual tracking voltage references using a single reference
SOurce are' easily constructed using OP-10. These references
exhibit low noise, excellent stability vs temperature and time and
hiove excellent power supply rejection.
REFERENCES
In the circuit shown, R3 should be adjusted to set I REF to operate
V RE F at its minimum temperature coefficient current. Proper
circuit start-up is assured by Rz , Zl. and 01'
.4
V+
Small Signal I-JdBI
V Z1 .. VREF +2.0V
A.
V1
~
R2
V REF 11 + 'JIT'I
V2 ~ VI (-R5 )
R4
ZI
A.
o•• ~
Output Impedance ItoI L : I.OmA - 5.0mAI ....... 0.25 -1O-3n
V2
6-65
OP-11
PMI
QUAD MATCHED 741-TYPE OPERATIONAL AMPLIFIER
GENERAL DESCRIPTION
FEATURES
The OP·ll provides four matched 74l·type operational
amplifiers in a single l4·pin DIP package. The OP·ll is pin
compatible with the LM148 and LM348 amplifiers. The
amplifiers are matched for common mode rejection ratio and
offset voltage. These parameters are very important in the
design of instrumentation amplifiers. In addition the amplifier
is designed to have equal positive'going and negative·going
slew rates. This is a very important consideration for good
audio system performance.
Each of the four amplifiers has the proven OP·02 advantages
of low noise, low drift and excellent long term stability. Preci·
sion Monolithics' exclusive Silicon·Nitride "Triple Passivation"
process eliminates "popcorn noise" and provides maximum
reliability and long term stability of parameters for lowest
overall system operating cost.
_
Guaranteed Vos' . . . . . . . ..
•
•
•
•
•
•
•
•
•
Guaranteed Matched CMRR . . . . . . . . 94 dB MIN.
Guaranteed Matched Vos . . . . . . . . . 750!.!V MAX.
LM148/LM348 Direct Replacements
Low Noise
Silicon·Nitride Passivation
Internal Frequency Compensation
Low Crossover Distortion
Continuous Short Circuit Protection
Low Input Bias Current
500!.! V MAX.
The OP·ll is ideal for use in designs requiring minimum space
and cost while maintaining OP·02·type performance. OP·ll's
with processing per the requirements of MIL·STD·883A are
available. For dual·741-type versions, see the OP·04 and OP·14
data sheets.
EQUIVALENT SCHEMATIC
PIN CONNECTIONS
(114 CIRCUIT SHOWN)
(-) IN
I.IIN
O--j---i=~~
TOP VIEW
L-4-~~4-~OUT ~------------------------------------------~
ORDERING INFORMATION
ORDER: OP.llAYJ
OP·llBY
_55°C TO +125°C
OP.llEYJ o°c TO +70°C
OP·llFY
Military Temperature Range Devices
With MIL·STD·883A Class B Processing
ORDER: OPll-883·AY
OPll-883 .. BY
6-66
•
OP-11
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Operating Temperature Range
Op-llA,Op-llB
OP-l1 E, OP-l1 F
±22V
Internal Power Dissipation (Note 1)
800mW
Differential Input Voltage
±30V
Input Voltage
Note 1: Maximum package power dissipation vs. ambient
temperature.
Supply Voltage
Output Short Circuit Duration
Continuous
(One Amplifier Only)
Storage Temperature Range
_65° to +150°C
Lead Temperature Range (Soldering, 60 sec)
MATCHING CHARACTERISTICS
Parameter
Input Offset Voltage Match
Common Mode Rejection
Ratio Match (Note 3)
EO;
MAXiMUM AMBIENT
TEMPERATURE
FOR RATING
80°C
14 Pin DIP
(V)
OP-11A
OP-11E
300°C
These specifications apply for Vs = ±15V. TA = 2SoC, Rs
-55°C to +125°C
O°C to +70°C
DERATE; ABOVE
MAXIMUM,AM8IENT
TEMPERATURE
10mWfC
OP-l1B
OP-11F
100n, unless otherwise noted.
Symbol
Test Conditions
t.Vos
(Note 4)
t.CMRR
VcM= ±CMVR
Typ
Min
-
0.5
-
1.0
120
94
Max
Min
0.75
20
-
Typ
-
0.8
-
1.0
120
94
Max
2.0
20
-
Units
mV
uVN
dB
These specifications apply for Vs = ±15V, -55°C" TA" +125°C for OP-l1A and Op-llB, O°C.; TA'; +70°C for OP-llE and OP-llF
Rs .; lOOn unless otherwise noted.
Input Offset Voltage Match
t.Vos
(Note 4)
Common Mode Rejection
Ratio Match (Note 3)
t.CMRR
VcM =±CMVR
-
0.6
-
3.2
110
94
1.0
20
-
-
1.0
-
3.2
110
94
2.5
20
-
mV
uVN
dB
MATCHING PARAMETER DEFINITIONS
COMMON MODE REJECTION RATIO MATCH (~CMRR).
The difference between the common·mode rejection ratios
(expressed in volt/volt) of side A and side B. ~CMRR in
dB = -20 10910 (~CMRR in volt/volt), See note 3.
INPUT OFFSET VOLTAGE MATCH (~Vos). The differ·
ence between the offset voltages of side A and side B;
(VOSA - VOSB), See note 4.
TYPICAL APPLICATION
INSTRUMENTATION AMPLIFIER 2 OP·AMP DESIGN
01
••
.5
••
>-....-0<.
GENERAL DESIGN CONSIDERATIONS
COMMON MODE REJECTION
Assuming ideal amplifiers, the expression for output voltage is:
Because the dual ap amp has a high common mode rejection ratio
match, the ability to reject common mode inputs becomes primarily
a function of resistor ratio matching. This device eliminates the
need for special op amp selections in many instrumentation amplifier
applications.
With ideal resistors this simplifies to:
DIFFERENTIAL OFFSET VOLTAGE
The amplifier's differential input offset voltage !Eos2-Eosl) will be
the major erro:r factor. If the individual input offset voltages are of
equal magnitude and polarity they appear as a common mode input
and are rejected.
6-67
OP-11
ELECTRICAL CHARACTERISTICS (Each Amplifier)
These specifications for Vs
=
±15V. TA
=
OP-l1A
2SoC, unless otherwise noted.
Symbol
Test Conditions
Input Offset Voltage
Vos
Rs" 10k!l
Input Offset Current
los
Input Bias Current
18
-
Input Resistance Differential Mode
Ain
0.20
Parameter
OP-llB
Input Voltage Range
CMVR
Common Mode Rejection Ratio
CMRR
Power Supply Rejection Ratio
PSRR
Vs ~ ±5 to ±15V
Rs" 10k!l
Output Voltage Swing
VoM
RL" 2k!l
Large Signal Voltage Gain
Avo
RL" 2k!l
Vo ~ ±10V
Power Consumption (Note 2)
Pd
Vo
Input Noise Voltage
enp-p
0.1 Hz to 10Hz
Input Noise Voltage Density
en
fo
fo
fo
VCM~±CMVR
Typ
Min
Max
0.30
8.0
180
0.50
20
300
Min
Typ
-
25
50
300
500
nA
-
M!l
-
dB
Max
0.60
2.5
Units
mV
nA
±12
±13
100
120
-
90
110
-
90
110
-
dB
±11
±13
-
±11
±13
650
-
100
650
-
V
100
-
123
180
-
123
180
-
18
14
12
0.40
0.20·
0040
±12
±13
100
120
V
Rs" 10k!l
Input Noise Current
inp_p
Channel Separation
CS
Input Noise Current Density
in
Slew Rate (Note 1)
~
~
~
10Hz
100Hz
1000Ht
O.lHz to 10Hz
100
~
fo
fo
fo
~
~
10Hz
100Hz
1000Hz
Risetime (Note 1)
17
130
-
1.8
1.5
1.2
0.70
Vo
BW
0.7
-
SR
Large Signal Bandwidth (Note 1)
Closed Loop Bandwidth (Note 1)
~OV
~
20Vp·p
11
AVCL ~ +1.0
AV~+l
VIN
1.0
16
1.5
2.0
-
-
-
100
-
-
-
-
-
-
0.70
-
11
1.5
0.7
18.
14
12
17
130
!J.V p-p
-
nV/-/Hz
-
dB
-
pA/-/Hz
-
1.0
-
2.0
mW
-
1.8
1.5
1.2
16
V/mV
pA p.p
Vllls
-
kHz
-
MHz
nsec
-
80
120
-
80
120
-
l5
25
-
15
25
~50mV
Overshoot (Note 1)
%
The following specifications apply for Vs ~ ±15V, -55°C .. TA" +125°C, unless otherwise noted.
Input Offset Voltage
Vas
Rs" 10k!l
Average Input Offset Voltage
Drift (Note 1)
TCVos
Rs" 10k!l
-
10
-
40
-
1.0
0.40
2.0
1.0
4.0
3.5
15
mV
Illitc
I nput Offset Current
los
-
Average Input Offset Current Drift
TCl as
-
200
375
-
400
650
±12
±13
-
±12
±13
-
V
100
120
-
100
120
-
dS
90
110
-
90
110
-
dB
-
100
250
-
V/mV
±11
±13
-
-
115
200
20
0.10
0.30
Input Bias Current
IS
Input Voltage Range
CMVR
Common Mode Rejection Ratio
CMRR
Power Supply Rejection Ratio
PSRR
Vs ~ ±5 to ±15V
Rs" 10k!l
Large Signal Voltage Gain
Avo
RL" 2k!l
Va ~ ±10V
100
250
Maximum Output Voltage Swing
VaM
RL" 2k!l
±11
±13
-
Power Consumption (Note 2)
Pd
Va
-
115
200
VCM~±CMVR
-
40
0.30
80
'0.60
nA
nAtC
nA
Rs" 10k!l
~OV
NOTE 1: Parameter is not 100% tested. 90% of all units meet these specifications.
NOTE 2: Total dissipation for all 4 amplifiers in package.
NOTE 3: Match exists between any two amplifiers.
NOTE 4: Using amplifier 1 as reference then
~Vos =
Vasn - Vosl·
6-68
V
mW
I
OP-11
OP-11E
ELECTRICAL CHARACTERISTICS (Each Amplifierl
OP-11F
These specifications fqr Vs -±15V, TA = 25·C, unless otherwise noted.
Parameter
I nput Offset Voltage
Input Offset Current
Input Bias Current
Input Resistance Differential Mode
Input Voltage Range
Common Mode Rejection Ratio
Symbol
Power Supply Rejection Ratio
PSRR
Output Voltage Swing
Large Signal Voltage Gain
YoM
Ava
Power Consumption (Note 2)
Input Noise Voltage
Input Noise Voltage Density
Pd
e,!!>_p
en
Input Noise Current
Channel Separation
Input Noise Current Density
i np_p
Slew Rate (Note 1)
Large Signal Bandwidth (Note 1)
Closed Loop Bandwid~h (Note 1)
Risetime (Note 1)
Vas
los
IS
Rin
CMVR
CMRR
Test Conditions
R s ": 10kU
-
-
-
VCM- 'CMVR
Rs": 10kU
Vs = ±5 to ±15V
Rs": 10kU
RL;;' 2kU
RL;;' 2kU
Va = .,0V
Vo=OV
O.IHz to 10Hz
fa - 10Hz
fa = 100Hz
fa = 1000Hz
0.1 Hz to 10Hz
CS
in
Min
0.20
±12
100
--
Min
-
0.20
±12
100
Typ
0.60
25
300
0.40
±13
120
90
110
-
dS
±11
100
.,3
-
±11
100
±13
-
650
650
V
V/mV
-
-
123
0.7
IS
14
12
17
130
1.8
1.5
1.2
1.0
16
2.0
80
ISO
-
-
-
-
100
-
-
-
-
0.70
123
0.7
18
14
12
17
130
1.8
1.5
' 1.2
120
-
Overshoot (Note 1)
15
25
The following specifications apply for Vs - ±15V. O·C": TA": +70·C. unless otherwise noted.
-
15
BW
AVCL =+1.0
AV-+l
VII\/,= 50mV
11
1.5
-
-
Input Offset Voltage
Average Input Offset Voltage
Drift (Note 1)
Input Offset Current
Average Input Offset Current Drift
Input Bias Current
Input Voltage Range
Common Mode Rejection Ratio
Vas
TCVos
Power Supply Rejection Ratio
PSRR
Large Signal Voltage Gain
Ava
Maximum Output Voltage Swing
Power Consumption (Note 2)
YoM
Pd
los
TClos
IB
CMVR
CMRR
Rs": 10kU
Rs": 10kU
-
-
-
-
VCM= ±CMVR
Rs": 10kU
Vs -.5 to ±15V
R <;10kU
RL;;' 2kU
Va = ±10V
RL ;;.2kU
Vo=OV
-
Units
mV
nA
nA
MU
V
dS
-
1.0
16
2.0
80
Vo = 20Vp-p
Max
2.5
50
500
110
0.70
SR
S.O
ISO
0.40
±13
120
Max
0.50
20
300
90
100
f a -10Hz
fo=I00Hz
fa = 1000Hz
Typ
0.30
±12
100
0.40
2.0
20
0.10
200
±13
120
0.80
10
30
0.30
350
11
1.5
-
-
-
-
O.SO
4.0
40
ISO
-
-
mW
"Vp-p
nVf.JHz
pA pop
dB
pAl.JHz
-
120
V/u.s
kHz
MHz
nsec
25
%
3.0
15
/-Lvl"c
60
0.60
550
mV
nA
-
±12
0.30
400
.,3
100
120
-
nAI"C
nA
V
dB
-
90
110
-
90
110
-
dB
100
250
-
100
250
-
V/mV
±11
.,3
115
-
±11
±13
115
-
200
200
V
mW
-
6-69
-
OP-11
TYPICAL PERFORMANCE CURVES
OFFSET VOLTAGE VS TEMPERATURE
OFFSET CURRENT VS TEMPERATURE
B
·.;0
""S" t15V
.....
-.20
,/
~
~
/
./
-.40
.......
I
I
_f-
-
200
--
I-
....... V
I ......
V
0
>
i
VV
i--'
"
./
.//
~
~ -.30
300
i--""
8
V
-
L.L
!P-1~J.
BIAS CURRENT VS TEMPERATURE
f-
:.-f-
VS=t15Y
'00
2
/
-'&~eo -40 -20
20
0
40
80
80
100 120 140
0
-60 -40
-20
0
BOO
~
100
/
800
I'-.
~
Rl"2Kn
S
~HASE
80
\
VS=!15V
TA"+2S·C
AL =2K
'1\
L= 100 pi'
\
0
0
20
40
60
100 120
BO
140
0.'
'.0
'0
...
...
/
~500
~
~
0
V
-
/TA"+25~C
RL"2KU
93110
I
/
'"
/
200
'00
0
•
'0
,.
POWER SUPPLY VOLTAGE (.tV)
20
,.,
60'
'.0
40
80
BO
'K
'OK
,40
100 120
140
VS=("V
"~
..
180"
lOOK
'M
SLEWJTE
" "-40
-20
0
20
'0
BO
BO
00
80
40
40
20
20
'00
'K
6-70
100 120 140
1111111
120
'00
FREQUENCY IHilI:l
S>
'40
vk~I,\IM~,
10
60
PSRR VS FREQUENCY
'00
'.0
~
TEMPERATURE lOCI
~!::=~c
TA"25"el
0
.;
."NIWD~ r-....
.7
.6
-60
'OM
IIII~
i""
120
.......
-~
135 0
CMRR VS FREQUENCY
OPEN LOOP GAIN VS SUPPLY VOLTAGE
...
'00
FREQUENCY (Hzl
TEMPERATURE lOCI
100
20
.B
\
'00
-20
4.'
\
~
_
40
-40
0
NORMALIZED AIC PA~AMETERS
VS TEMPERAnRE
1.2
'00
-80
-20
TEMPERATURE 1"<:1
GAIN
20
~
-60 -40
0'
\
\
6.
/
300
9
100 120 140
1.'
........
VS = :t:.1SV
.00
~
~
0
BO
1.3
r----
/'
000
Z
60
120 _ " " ' \
700
"
'0
OPEN LOOP FREQUENCY
8< PHASE RESPONSE
OPEN LOOP GAIN VS TEMPERATURE
~
20
TEMPERATURE (OC)
Tl!MPERATURE (OCI
..
,
100K
0
1.0
t-...
'0
'00
,I
I
1.
FREQUENCY (Hzl
10K
100K
I
OP-11
TYPICAL PERFORMANCE CURVES
CHANNEL SEPARATION VS FREQUENCY
SPOT NOISE VOLTAGE VS FREQUENCY
!!In._
SPOT NOISE CURRENT VS FREQUENCY
140
rftI
120
100
VS"±15V
~
VS"115V
TA ·.~I~C
!
11°MIm_
r~ I~ji!lilli=j!iillili'i'llliii
100
!
Z
r-
w
lOll!! C.S.o201oIlCO:ZY')
~
-=-
r-
20
o
NPUT~Vl
r-
40
U
ffi
11111111
_ eo
i
~
11111111
SO
I
10
•
V
o
z
dill J1I11I1I1 I 11111111 I
10
100
TA=+25°C
lK
10k
lOOK
II~O--~~LU~loo~-L~WU~IK~~~~U'~OK
. ":l:0--.J......u..LU"101:-0--L....l-U.wJt,K~..L.u.,IJ.I.lJl,0K
FREQUENCY (Hz)
FREQUENCY 1Hz)
FREQUENCY 1Hz}
VOLTAGE FOLLOWER
PULSE RESPONSE
TRANSIENT RESPONSE
MAX UNDISTORTED OUTPUT
VS FREQUENCY
2.
i
~
> +20
'E
vLl.l
\
TA" +26°C
\\
24
20
e
~ 12
~
o
RL:=2K
1&
I
5
0
I!:
:>
o
,27I
-20
>
•
~
o
200
400
600
TIME - ms
1\
,
4
TIME-ms
.....
100
10
1000
FREQUENCY 1KHz)
OUTPUT VOLTAGE VS
LOAD RESISTANCE
,.
NEGATIVe SWING
!:i 12
~
(
~,o
iS
o
4
vs "·:t16V
Ij
!
~ 8
g•
r ---
piS{T{~E U,JG1
.
14
;;;
POWER CONSUMPTION VS
TEMPERATURE
QUIESCENT CURRENT VS
SUPPLY VOLTAGE
140
1
~
TA=+25"C
'30
-'
I
TA =26"
/.'
~
fI
o0.1
I""- r-
::l
120
I
110
~
Q,
--
-
r--....
v.Jmv
,,
:-..
1
o
1.0
LOAD RESISTANCE TO GROUND IKJ
10
o
100
20
SUPPLY VOLTAGE (:tV)
6-71
30
40
60
_4 o
~
0
~
40
~
so
TEMPERATURE fOCI
100=_
PMI
OP-12
®
PRECISION LOW INPUT CURRENT OP AMP
INTERNALLY COMPENSATED
GENERAL DESCRIPTION
FEATURES
The PMI OP-12 is an improved version of the popular LM108A
low power'cp amp. The OP-12 is internally compensated and
its chip dimensions are only 42 x 58 mils. Additionally, the
OP-12 has a three times lower offset voltage and a two times
lower offset voltage drift_ The total worst case input offset
voltage over -55°C to +125°C for the OP-12 is only 350J.LV
while the 108A has 900J.LV to 1000lN for these conditions.
In addition the OP-12 drives a 2kQ load. This is five times the
output current capability of the 108A. This excellent performance is achieved by applying PMI's ion-implanted super
beta process and on-chip zener-zap trimming capabilities. The
internal compensation makes this op amp ideal for hybrid
assembly applications
•
Low Offset Voltage _____ . ____ .. _ 150J.LV Max_
•
•
Low Offset Voltage Drift _. _____ . 2_5J.LVfC Max_
Five Times PM108A Load Current _____ 5 mA Min_
•
Internal Frequency Compensation
Plus the Outstanding PM108A Features
• Low Offset Current __________ . __ 200 pAMax_
•
Low Bias Current ______ . ___ . . .. 2.0 nA Max.
•
Low Power Consumption ..•. 18 mW max. @±15V
•
High Common Mode Input Range. . .. ±13.5V Min.
•
MIL-STD-883A Class B Processing Available
•
Si~icon·Nitride
Passivation
PIN CONNECTIONS AND ORDERING INFORMATION
SIMPLIFIED SCHEMATIC
TOP VIEW
Ne
TO-99 (J·Suffjx)
ORDER: OP·12AJ
OP·12BJ
OP-12CJ
OP-12EJ
OP-12FJ
OP-12GJ
0o'-+~~---+--~
Military Temperature Range Devices
With M I L-STD-883A Clas~B Processing
ORDER: OP12-883-AJOP12-883-BJ
OP12-883-CJ
6-72
I
OP-12
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
OP·12A, OP-12B. OP-12C
Op·12E, Op·12F, OP-12G
'Internal Power Dissipation (Note 1)
Differential Input Current (Note 2)
Input Voltage (Note 3)
Output Short Circuit Duration
±20V
±18V
500mW
±10mA
±15V
Indefinite
NOTE 1: Maximum package power dissipation vs. ambient
temperature:
Package Type
Maximum
Ambient
Temperature
for Rating
Derate Above
Maximum
Ambient
Temperature
TO-99 (J)
80°C
7.1 mWfC
Operating Temperature Range
OP-12A, OP-12B, OP-12C
OP-12E, OP-12F, OP-12G
Storage Temperature Range
Lead Temperature Range
(Soldering, 60 sec)
-5·5°C to +125°C
O°C to +70°C
-65°C to+150° C
300°C
. NOTE 2: The inputs are shunted with back-to-back diodes for
overvoltage protection. Therefore, excessive current will flow
if a differential input voltage in excess of 1 V is applied between
the inputs unless some limiting resistance is provided.
NOTE 3: For supply voltages less than ±15V, the absolute
maximum input voltage is equal to the supply voltage.
OFFSET VOLTAGE TEST CIRCUIT
BURN-IN CIRCUIT
200Kn
+18V
200n
6
Vo
Vos= 1000
LOW FREQUENCY NOISE TEST CIRCUIT
(0.1 TO 10 Hz)
10Kn
SIA
l.5pF
loon
loon
NOTES; 1.51 CLOSED MEASURES en (VOl\.
2.51 OPEN MEASURES In AND 'n IV02I. 10 IS COMPUTED FROM THE
TWO MEASUREMENTS
3. SEE NOISE PHOTO OF 8n IN TYPICAL PERFORMANCE CURVES,
6-73
OP-12
OP-12A
ELECTRICAL CHARACTERISTICS
OP-12C
OP-12B
These specifi~ations apply for Vs = ± 15V, T A = 25°C, unless otherwise noted.
Parameter
Symbol
Test Conditions
Min
Typ
-
-
0.05
0.20
-
-
0.80
2.0
-
-
-
0.9
-
-
Input Offset Current
los
Input 81as Current
18
enp·p
0.1 Hz to 10Hz
-
~n
fa = 10Hz
fo = 100Hz
fa = 1000Hz
-
22
21
20
Input Noise Voltage Density
Typ
0.15
-
Input Noise Voltage
Min
0.07
Vos
Input Offset Voltage
Max
0.9
Max
Min
Typ
0.30
-
0.25
1.0
0.05
0.20
-
0.08
0.50 nA
0.80
2.0
.-
1.0
5.0
-
-
0.9
-
I'V pop
-
22
21
20
-
nV/-./Hz
-
0.18
-
22
21
20
-
-
Input Noise Current
i np _p
0.1 Hz to 10Hz
-
3
-
-
3
-
-
3
-
-
0.15
0.14
0.13
-
-
0.15
0.14
0.13
-
-
0.15
0.14
0.13
-
in
fo = 10Hz
fa = 100Hz
fa = 1000Hz
-
Input Noise Current Density
-
10
Input Resistance -
Differential Mode
Ain
Input Voltage Range
CMVR
-
26
70
-
-
-
26
±13.5 ±14.0
-
70
.13.5 ±14.0
-
Common Mode Rejection Ratio CMRR
VCM= ±CMVR
104
120
-
104
120
-
Power Supply Rejection Ratio
PSRR
Vs = ±5V to ±15V
104
120
-
104
120
Ava
RL;;.10Kl1, Vo=±10V
AL;;.2Kl1, Va = ±10V
80
50
300
150
-
80
50
300
150
Voltage Swing
VoM
AL ;;.10Kl1
RL ;;'2Kl1
Slewing Aate
SA
RL;;' 2Kl1
-
Closed Loop 8andwidth
BW
AVCL = +1.0
-
Open Loop Output Resistance
Ro
Vo=O,lo=O
Power Consumption
Pd
V = ± 15V
V, = ±5V
Large Signal Voltage Gain
Maximum Output
•
±13.0 ±14.0
±10.0 ±12.0
0.12
-
-
±13.0 ±14.0
±10.0 ±12.0
-
-
-
-
-
200
-
-
9
3
18
6
0.80
Units
Max
50
±13.0 ±14.0
-
mV
nA
pA p-p
pA/-/HZ
-
Ml1
-
V
84
116
-
d8
-
84
116
-
d8
-
40
250
100
-
-
-
±13.0 ±14.0
±10.0 ±12.0
0.12
-
-
0.80
-
-
V/mV
V
0.12
-
V/l'sec
0.80
-
-
-
MHz
-
200
-
-
200
-
l1
-
9
3
18
6
-
12
4
24
8
mW
The following specifications apply for Vs = ±15V, -55°C'; TA'; +125°C, unless otherwise noted.
Input Offset Voltage
Vas
-
0.12
0.35
-
0.28
0.60
-
0.40
Average I nput Offset
Voltage Drift
TCVos
-
0.50
2.5
-
1.0
3.5
-
1.5
Input Offset Current
los
-
0.12
0.40
-
0.12
0.40
-
0.18
1.0
nA
Average Input Offset
Current Drift
TCIos
-
0.50
2.5
-
0.50
2.5
-
1.0
5.0
pA/oC
Input 8ia. Current
18
-
1.2
3.0
-
1.2
3.0
-
1.8
10
Input Voltage Range
CMVA
-
Common Mode Aejection Aatio CMAA
Power Supply Aejection AsHo
PSAR
Large Signal Voltage Gain
2.0
10
mV
I'Vl"C
nA
-
±13.5 ±14.0
-
±13.0 ±14.0
VCM = ±CMVA
100
110
-
100
110
-
80
106
-
dB
Vs = .5V to ±15V
100
110
-
100
110
-
80
106
-
dB
40
120
40
120
-
15
80
-
Vim V
±13.5 ±14.0
Ava
RL;;' 5Kl1, Va = .10V
Maximum Output
Voltage Swing
VoM
RL ;;'10Kl1
RL ;;'5Kl1
Power Consumption
Pd
.13.0 ±14.0
'10.0 '13.0
-
9
6-74
-
18
±13.0 ±14.0
.10.0 ±13.0
-
9
18
'13.0 .14.0
.10.0 ±12.0
-
15 .
-
24
V
V
mW
•
OP-12
ELECTRICAL CHARACTERISTICS
OP-12F
OP-12E
OP-12G
.
These specifications apply for Vs = ±15V, TA = 25°C, unless otherwise noted.
P.rameter
Symbol
Test Conditions
Input Offset Voltage
Vos
Input Offset Current
los
Input 8ias Current
IB
Input Noise Voltage
enp·p
O.lHz to 10Hz
en
f o -l0Hz
fo = 100Hz
fo= 1000Hz
Input Noise Voltage Oensity
Input Noise Current
Input Noise Current Density
i np_p
O.lHz to 10Hz
in
fo = 10Hz
f~ = 100Hz
fo = 1000Hz
Input Resistance Differential Mode
Rin
Min
Typ
Max
-
0.07
0.15
-
0.05
0.20
0.80
2.0
22
21
20
26
70
0.9
3
0.15
0.14
0.13
Min
-
Typ
Max
0.18
0.30
0.07
0.40
0.90
4.0
-
-
-
0.9
-
-
22- .
21
20
-
-
3
-
-
-
13
60
-
-
-
-
-
Min
0.15
0.14
0.13
-
Typ
Max
0.25
1.0
0.08
0.50
nA
1.0
5.0
nA
0.9
-
p.Vp·p
-
pAl$>
-
22
21
20
10
50
3
0.15
0.14
0.13
-
V
116
-
dB
dB
-
VCM= ±CMVR
104
120
-
102
120
-
PSRR
Vs = ±5V to ±15V
104
120
-
102
120
-
84
116
-
Avo
RL:>10KU,V o =±10V
RL:>2KU,V o =±10V
80
50
300
150
80
30
300
120
250
100
Maximum Output
Voltage Swing
VoM
RL :>10KU
RL :>2KU
±13.(
±10.(
Slewing Rate
SR
RL :>2KU
Closed Loop' Bandwidth
BW
AVCL =+1.0
-
40
-
-
-
200
-
12
4
Power Supply Rejection
Ratio
Large Signal Voltage Gain
Open Loop Output
Resistance
Power Consumption
Ro
Pd
Vo=O,lo=O
·.Vs = ±15V
Vs = ±5V
±13.0 ±14.0
±10.0 ±12.0
-
-
-
-
0.12
0.80
-
200
-
9
3
-
±13.0 ±14.0
±10.0 ±12.0
-
-
-
-
200
-
9
3
18
6
0.12
0.80
18
6
±13.f ±14.0
B4
-
pAp-p
MU
±13.5 ±14.0
CMRR
nV/,jHZ
-
-
CMVR
mV
-
±13.5 ±14.0
Input Voltage Ra·nge
Common Mode Rejection
Ratio
Units
±14.0
±12.0
0.12
0.80
24
8
V/mV
V
V/p.sec
MHz
U
mW
The following specificationsapply for Vs = ±15V, O°C.;; TA ';;+70°C, unless otherwise noted.
Input Offset Voltage
Average I nput Offset
Voltage Drift
Vos
-
0.10
0.26
-
0.23
0.45
-
0.32
1.4
mV
TCVos
-
0.50
2.5
-
1.0
3.5
-
1.5
Input Offset Current
los
-
0.08
0.30
-
0.11
0.60
-
0.12
0.70
nA
Average Input Offset
Current Drift
"!iClos
-
0.50
2.5
-
1.0
5.0
-
1.0
5.0
pA/oC
-
1.0
2.6
-
1.2
5.2
-
1.4
6.5
nA
±13.5 ±14.0
-
±13.5 ±14.0
-
±13.f
-
100
116
Input Bias Current
IB
Input Voltage Range
CMVR
Common Mode
-
V
-
80
112
-
dB
112
-
dB
80
150
-
V/mV
-
V
CMRR
VCM = ±CMVR
100
Power Supply
Rejection Ratio
PSRR
Vs = ±5V to ±15V
100
116
-
100
116
-
80
Large Signal Voltage Gain
Avo
RL :>2KU, Vo = ±10V
RL :>10KU, Vo = ±10V
25
60
100
200
-
15
60
100
200
-
25
Maximum Output
VOltage Swing
VoM
RL :>10KU
RL :>2KIl
-
+13.0
'10.0
Power Consumption
PD
±13.0 ±14.0
±10.0 ±12.0
-
9
6-75
18
±13.0 ±14.0
±10.0 .12.0
-
9
p.vfc
-
116
Rejection Ratio
10
18
-
±14.0
±12.0
15
24
mW
OP-12
TYPICAL PERFORMANCE CURVES
LOW FREQUENCY NOISE
SMALL SIGNAL TRANSIENT RESPONSE
LARGE SIGNAL TRANSIENT RESPONSE
10pF
Rs = 0, BW = O.IHz to 10Hz
TRANSIENT RESPONSE TEST CIRCUIT
5 mVldiv AT OUTPUT
O.5llVldiv REFERRED TO INPUT
10KO
>-+----"+---oOU1
IN Q--4-'V'VV---;
10Kn
OPEN LOOP GAIN (Avol VS. SUPPLY
VOLTAGE (Veel WITH
TEMPERATURE AS A PARAMETER
OPEN LOOP GAIN (Avol AND PHASE
VS.FREQUENCY
......
......
"-
"-
-"'r------ t--:"~~lIV
INPUT BIAS CURRENT
AND INPUT OFFSET CURRENT
VS. TEMPERATURE
, :- .........
rT ,
I
II
100pF
,
,
,
,
/
./
-
r-
-- -
"..........
.........
r-- r-T .... jC
.........
'\.
TE1""IIIATUftE,'C
V.. hVOLTa/
QUIESCENT CURRENT USYI VS.
SUPPLY VOLTAGE WITH
TEMPERATURE AS A PARAMETER
---
QUIESCENT CURRENT (lSY) VS.
TEMPERATURE WITH SUPPLY
VOLTAGE AS A PARAMETER
"'V
".,
r-
:;:;.
lS'C
"'..,t.VOLTSI
V
,,/
,/
,/
t;
V "'"
~v
V
Tl:MI'I!"ATUREt'cl
6-76
:::::::
-- ::::~
POWER SUPPLY REJECTION RATIO (PSRRJ
VS. FREQUENCY
I
OP·12
APPLICATION INFORMATION
The OP·12 series has extremely low input offset and bias cur·
rents; the user is cautioned that stray printed circuit board
leakages can produce significant errors, especially at high
board temperatures. Careful attention to board layout and
cleaning procedure is required to fully realize the OP·.12 per·
formance. It is suggested that effects of board leakage be
minimized by encircling the input pins with a conductive
guard ring operated at a potential close to that .of the inputs.
This guard ring should be driven by a low impedance source
such as the amplifier's output for non·inverting circuits, or be
tied to ground for inverting circuits.
OP·12 DEFINITIONS
INPUT OFFSETVpLTAGE (Vosl
The voltage which '-must be applied between the input terminals to
obtain zero output voltage with no load.
INPUT OFFSET CURRENT Hosl
The difference between the currents into the two input terminals when
the output is at zero volts with no load.
INPUT SIAS CURRENT HSI
The average of the currents into the two input terminals when the
output is at zero volts with no load.
INPUT VOLTAGE RANGE (CMVRI
The range of common-mode voltage on the input terminals for which
the common-mode rejection specifications apply.
COMMON·MODE REJECTION RATIO ICMRRI
The ratio of the input voltage range to the peak·to·peak change in input
offset voltage over this range.
POWER SUPPLY REJECTION RATIO (PSRRI
The inverse ratio of the change in input offset voltage to the change
in power supply voltage producing it.
INPUT RESISTANCE (Rinl
The ratio of the small-signal change in input voltage to the change in
input current at either input terminal with the other grounded.
SUPPLY CURRENT lIoyl
The current required from the power supply to operate the amplifier
with no load and the output at zero volt$.
MAXIMUM OUTPUT VOLTAGE SWING IVoMI
The peak output voltage that can be obtained without clipping.
6·77
AVERAGE OFFSET VOLTAGE DRIFT ITCVool
The ratio of the change in the offset voltage to the change in tempera·
ture producing it.
AVERAGE SIAS CURRENT DRIFT (TCISI
The ratio of the change in the bias current to the change in temperature
producing it.
INPUT NOISE VOLTAGE IOnp.pl
The peak to peak noise voltage in a specified frequency band.
INPUT NOISE VOLTAGE DENSITY (enl
The rms noise voltage in a 1 Hz band surrounding a specified value of
frequency.
INPUT NOISE CURR1:NT linp.pl
The peak to peak noise current in a specified frequency band.
INPUT NOISE CURRENT DENSITY linl
The rms noise current in a 1 Hz band surrounding a specif.ied vatu. of
frequency.
OPEN LOOP OUTPUT RESISTANCE (aol
The small signal driving point resistance·of the output terminal with
respect to ground at a specified quiescerlt dc output voltage and.
current.
POWER CONSUMPTION (POl
The power requirad tp operate the amplifier with no loed and the
output at zero volts
PMI
IOP-141
DUAL MATCHED HIGH PERFORMANCE
OPERATIONAL AMPLIFIER
GENERAL DESCRIPTION
The OP·14 Series of Dual Matched High Performance General
Purpose Operational Amplifiers provides significant improve·
ments over industry·standard 1458/1558 types while main·
taining pin·for·pin compatibility. ease of application. and low
cost. Key specifications. such as Vos. los. lB. CMRR. PSRR.
and Avo. are guaranteed over the full operating temperature
range. Precision Monolithics' exclusive Silicon·Nitride "Triple
Passivation" process eliminates "popcorn noise." A thermally·
symmetrical input stage design provides low TCVos. TClos
and insensitivity to output load conditions. The OP·14 Series
is ideal for upgrading existing designs where accuracy improve·
ments are required and for eliminating special low drift or low
norse selected types. For similar devices with nulling capability.
refer to the OP'()4 data sheet.
--
FEATURES
Excellent D.C. Input Specifications
Matched Vas and CMRR
Fits Standard 1458/1558 Socket
Internally Compensated
Low Noise
---
•
•
•
I
Low Drift
Low Cost
O°C/+70°C and -55°C/+125°C Models
Silicon-Nitride Passivation
•
Models With MIL·STD-883A Class B
Processing Available From Stock
PIN CONNECTIONS AND ORDERING INFORMATION
SIMPLIFIED SCHEMATIC
TOP VIEW
(1/2 OF CIRCUIT SHOWN)
INVERTINGI
INPUT (A) 2
INVERTlIIGI
• INPUT (I)
4V-
T0-99' (J·Suffix)
ORDER: OP·14AJ
Op·14J
OP·14EJ
OP·14CJ
·~~~g~~~~~f~~~~~~b,
Military Temperature Range Devices
With MIL·STD-883A Class B Processing:
lLARTHERMALLYCFlOSS'COUPLEO
QUAD.
ORDER: OP14-883·AJ
OP14-883-J
6·78
OP-14.
ABSOLUTE MAXIMUM RATINGS
±22V
Supply Voltage
500mW
Internal Power Dissipation (Note 1)
±30V
Differential Input Voltage
Supply Voltage
Input Voltage
Output Short Circuit Duration
Indefinite
Storage Temperature Range
_65° to +150°C
Lead Temperature Range (Soldering, 60 sec)·
300°C
Operating Temperature Range
-55°C to +125°C
OP-14A,OP-14
O°Cto +70°C
OP-14E,OP-14C
Note 1: Maximum package power dissipation vs. ambient
temperature.
MAXIMUM AMBIENT
DERATE ABOVE
TEMPERATURE
MAXIMUM AMBIENT
TEMPERATURE
FOR RATING
7.1mWfC
TO-99 (J)
80°C
OP-14A
OP-14E
MATCHING CHARACTERISTICS
OP-14
OP-14C
These specifications apply for Vs = .16V, TA = 2S·C, Rs" 100n, unle.. otherwise noted.
Para_
Symbol
Input Offset Voltage Match
AVos
Common Mode Rejection
Ratio Match
ACMRR
Test Conditions
VCM = t CMVR
Min
Typ
Max
Min
Typ
Max
Units
-
0.3
1.0
-
1.0
2.0
mV
94
106,.
-
94
106
-
dB
n-1lleCif_ionIoppIy for VI - '1SV, -66·C .. TA" +12S·Cfor OP-14A and OP-14, O·C .. TA" 70·C for OP-14E and OP-14C •
... < 1000 un... etherwi. noted.
Input Offset Voltage Match
AVos
Common MDl.Y VOLTAGE,IJ. TO 11-, (WLlS)
-20
...,
OUTPUT SHORT·CIRCUIT
CURRENT VS TIME
\OP.t4A
L,
.
0
20
40
--
60
TEMPERATURE (-0
6-83
1\\
20
~
90
100
\~
1,\i"-~
I'
120
140
"o
I
I
,
I
2
3
TIME FROM OUTPUT BEING SHORTED fMINUTESI
PMI
OP-15
PRECISION JFET INPUT OPERATIONAL AMPLIFIER
LOW SUPPLY CURRENT
GENERAL DESCRIPTION
FEATURES
The OP-15 provides an excellent combination of high speed
and low input offset voltage. In addition the OP-15 offers the
speed of the 156A op amp with 155A dissipation. To further
enhance the excellent input parameters, the OP-15 uses bias
current compensation to maintain low input bias current at
elevated temperatures.
•
•
•
•
•
•
•
•
•
•
•
•
•
,.
The OP-15 was designed to provide real precision performance
along with. its high speed. For example the 500llV offset
voltage yields less than 1/2 LSB error in a 12 bit, 5V DAC.
Although the OP-15 can be nulled, the design objective was to
provide low offset voltage and drift WITHOUT NULLING.
Systems become MORE COST-EFFECTIVE as the number of
error correcting "knobs" decrease. PMI achieves this performance by use of an improved BI-F ET process coupled with
on-chip zener-zap offset trimming.
Most high speed monolithic op amps give settling time specifications to 0.01% error band, and so does PM!. Since 0.01% of
10V is 1mV, it is surprising that these same op amps have
offset voltage errors in the 0.02% to 0.3% range. A large number of applications are in the 0.05% to 0.1% range, and PMI
also gives specs for these error bands in its settling times. The
fact that 500llV is only 0.005% of 10V is why PMI specifies
settling time to a true 0.01% error band.
·High Slew Rate ....... _ . _ ... _ . . .. 17V/IlS
Fast Settling to ±0.1% ........• _ . _ .. 900 nsec
Low Input Offset Voltage ....•... _ 500 IlV MAX
Low Input Offset Voltage Drift _ .... _ . 2.0 Ilvfc
156 Speed with 155 Dissipation
Wide Bandwidth .... _ ....... _ .. _ . _ _ 6 MHz
Minimum Slew Rate Guaranteed on All Models
Temperature Compensated Input Bias Currents*
Guaranteed Input Bias Current@ 125°C .. 9nA MAX
Bias Current Specified WARMED UP Over Temp.
Internal Compensation
Low Input Noise Current . . . . . . . . . 0.01 pA v'Hz
High Common Mode Rejection Ratio _ ..... 100dB
Models With MIL-STD-883A Class B
Processing Available From Stock
makes the OP-15 a true precision, high speed op amp. The
additional features of low supply current coupled with an input
bias current of 9nA at 125°C ambient (not junction) temperature makes the OP-15 useful in a wide range of applications.
Applications include high speed amplifiers for current output
DAC's, active filters, sample-and-hold buffers, and photocell
amplifiers. For additional precision JFET op amps, see the
OP-16 and OP-17 data sheets.
The combination of low input offset voltage of 500llV MAX.,
slew rate of 17V/llsec, and settling time of 900nsec-toO.1%SIMPLIFIED SCHEMATIC DIAGRAM
PIN CONNECTIONS
N.C.
TOP VIEW
BA~:N~~:oUT
.'VBALANCE
4 V·(CASE)
ORDERING INFORMATION
ORDER: OP-15AJ]
OP-15BJ
OP-15CJ
OP-15EJ]
OP-15FJ
OP-15GJ
Militarv Temperature Range Devices
With MIL-STD-883A Class B Processing
ORDER: OP15-883-AJ
ORDER OP15-883-BJ
OP15-883,cJ
'PATENT APPLIED FOR
6-84
I
OP-15
ABSOLUTE MAXIMUM RATINGS
'Supply Voltage
OP-15A:OP-15B, OP-15E, Op·15F
.OP-15C,OP-15G
±22V
±18V
Internal Power Dissipation
All Devices
(The TO-99(J) package must be derated based
on a thermal resistance of 150
0
500mW
Differential Input Voltage
OP-15A, Op·15B, OP-15E, OP-15F
OP·15C,OP·15G
±40V
±30V
Input Voltage
OP-15A, OP-15B, OP·15E, OP-15F
Op·15C,OP-15G
±20V
i16V
eIW junction
to ambient or 45° C/W junction to case.)
Operating Temperature Range
OP-15A, OP-15B, OP-15C
Op·15E, OP·15F, OP-15G
Maximum Junction Temperature (TJ)
All Devices
.
(Unless otherwise specified the absolute
maximum negative input voltage is equal
to the negative power supply voltage.)
_55°C to +125°C
ifc to +70°C
Output Short Circuit Duration
Indefinite
Storage Temperature Range
-65°C to +150°C
Lead Temperature Range (Soldering, 60 sec)
+150°C
ELECTRICAL CHARACTERISTICS
OP-15A
OP-158
+3OO°C
OP-15C
These specifications apply for Vs = ±15V, TA = 25°C, unless otherwise noted.
Symbol
Parameter
Test Conditions
Input Offset Voltage
Vas
Rs = 50n
Input Offset Current
los
T J - 25°C (Note 1)
Device Operating
Input Bias Current
IB
TJ=25°C (Note 1)
Device Operating
Typ
Min
-
Max
0.2
0.5
Min
0.4
3.0
5.0
3.0
5.0
10
22
15
18
10 12
50
110
-
-
Input Resistance
Rin
Large Signal Voltage Gain
Ava
RL d> 2Kn,
Va =.±10V
100
240
-
75
Output Voltage Swing
VoM
RL -10K
RL =2K
±12
±11
±13
±12.7
-
±12
±11
Supply Current
Slew Rate
- ISY
SR
Gain Bandwidth Product
GBW
Closed Loop Bandwidth
CLBW
Settling Time
ts
Input Voltage Range
CMVR
Common Mode Rejection Ratio
CMRR
Power Supply Rejection Ratio
PSRR
Input Noise Voltage Density
en
Input Noise Current Density
Input Capacitance
in
AVCL -+1.0
4.0
AVCL -+1.0
tt 0.01%
to 0.05%. (Note 2)
to 0.10%
-
6.0
14
2.2
1.1
0.9
±10.5 +14.8
-11.5
VCM = ±CMVR
Vs - ±10V to ±20V
Vs = ±10V to ±15V
fa - 100Hz
fa = 1000Hz
fa = 100Hz
fa = 1000Hz
CIN
86
100
86
100
-
20
15
-
4.0
-
-
7.5
-
-
-
-
2.7
17
10
0.01
0.01
3.0
-
-
Typ
-
3.5
-
-
Min
50
100
pA
15
18
10 12
200
400
pA
50
±13
±12.7
-
±12
ill
2.7
16
5.7
13
2.3
1.1
0.9
100
86
100
-
-
-
20
15
0.Q1
0.01
3.0
4.0
-
-
5.0
3.0
n
i13
±12.7
-
V
-
5.0
mA
-
V/jJ.sec
2.8
15
5.4
-
±10.3
+14.8
-11.5
-
82
96
-
-
82
-.
-
-
-
mV
-
12
-
3.0
200
-
-
Units
3.0
5.0
-
100
200
Max
0.5
-
20
40
Typ
-
220
15
18
10 12
86
-
1.0
-
±10.5 +14.8
-11.5
-
Max
2.4
1.2
1.0
100
20
15
0.01
0.01
-
V/mV
MHz
MHz
IJ.S
V
d8
dB
nV/"jHz
pA/"jHz
3.0
-
pF
0.9
4.5
mV
The following specifications apply for Vs = ±15V, -65°C';; TA';; +125°C, unless otherwise noted.
-
0.4
0.9
-
0.7
TCV o •
TCVosn Rp= 100Kn
Input Offset Current (Note 1). los
TJ _125°C
TA = 125°C
Device Operating
-
2.0
2.0
5.0
-
0.6
0.8
4.0
7.0
-
3.0
3.0
10
-
-
0.8
1.2
Input Bias Current (Note 1)
-
1.2
1.7
5.0
9.0
-
1.5
2.2
Input Offset Voltage
Vas
Rs = 50n
Average Input Offset Voltage
Drift
Without External Trim
With External Trim
IB
TJ = 125°C
TA = 125°C
-
2.0
-
-
(Note 3)
15
IJ.vfc
-
4.0
4.0
6.0
11
1.0
1.5
9.0
17
nA
-
7.5
14
1.8
2.7
10
19
nA
-
-
-
-
I?evice Operating
Input Voltage Range
±10.4 +14.6
-11.3
CMVR
-
-
±10.4 +14.6
-11.3
85
97
-
80
97
-
-
80
110
-
±13
-
CMRR
VCM - ±CMVR
85
97
PSRR
Vs = ±10V,to ±20V
Vs = ±10V to ±15V
85
97
-
-
RLd>2K,
Vs = ±10V
35
120
-
30
±12
±13
-
±12
Large Signal Voltage Gain
Ava
Maximum Output Voltage Swing VoM
RL .. 10Kn
6-85
il0.25 +14.6
-11.3
B5
Common Mode Rejection Ratio
Power Suppiy Rejection Ratio
-
-
93
-
-
V
-
dB
-
d8
93
-
25
100
-
V/mV
±12
±13
-
V
OP-15
ELECtRICAL CHARACTERISTICS
OP-15G
OP-15F
OP-15E
These specifications apply for Vs = ±15V, T A = 25°C, unless otherwise noted.
Paramet.,-
Symbol
Test Cood itionl
Min
Typ
Max
Min
Typ
0.4
Max
1.0
-
3.0
20
-
5.0
40
Min
Input Offset Voltage
Vas
As =500
-
0.2
Input Offset Current
los
TJ = 25°C (Note 1)
3.0
10
5.0
22
TJ = 25°C (Note 1)
-
15
50
-
15
100
Device Operating
-
18
110
18
200
-
10 12
-
-
10 12
75
-
50
-
±12
±13
-
±11
±12.7
-
Device Operating
Input Bias Current
IB
Input Resistance
Rin
Large Signal Voltage Gain
Avo
Output Voltage Swing
VoM
RL ;;'2KO,
Vs = ±10V
100
240
AL = 10K
±12
±13
RL =2K
±11
±12.7
-
Supply Current
ISY
Slew Aate
SA
Gain Bandwidth Product
GBW
Closed Loop Bandwidth
CLBW
AVCL = +1.0
Settling Time
ts
to 0.01%
10
AVCL =+1.0
4.0
to 0.05% (Note 2)
to 0.10%
-
4.0
7.5
-
3.5
2.2
-
1.1
-
0.9
-
-
6.0
14
CMVA
±10.5 +14.8
-11.5
Common Mode Rejection Ratio
CMRA
VcM = ±CMVA
86
100
Power Supply Aejection Ratio
PSAA
Vs = ±10V to ±20V
86
100
Vs = ±10V to ±15V
-
fo = 100Hz
en
-
fo = 1000Hz
Input Noise Current Density
fo = 100Hz
in
fo = 1000Hz
Input Capacitance
CIN
The following specifications apply for Vs
Input Offset Voltage
Vos
=
±15V, O°C:s;;; TA
-
-
2.7
17
I nput Voltage Aange
Input Noise Voltage Density
0.5
-
-
20
-
15
-
0.01
-
0.Q1
-
3.0
-
220
2.7
16
5.7
13
2.3
1.1
0.9
±10.5 +14.8
-11.5
86
100
86
100
-
20
15
4.0
-
0.Q1
-
3.0
Typ
3.0
50
100
15
200
18
400
Units
mV
pA
pA
-
0
-
V/mV
±12
±13
-
V
±11
±12.7
-
5.0
-
10 12
2.8
15
5.4
12
5.0
mA
-
V//J.sec
-
MHz
/J.s
-
2.4
-
-
1.2
-
MHz
1.0
-
±10.3
+14.8
-11.5
-
V
82
96
-
dB
0.Q1
-
pA/..jHz
0.Q1
-
3.0
-
-
-
82
100
-
20
15
dB
nV/..jHz
pF
< +70°C. unless otherwise noted.
As = 500
-
0.3
0.75
-
0.55
-
2.0
5.0
3.0
10
2.0
-
3.0
-
1.5
-
0.7
4.0
15
4.0
-
3.8
mV
(Note 3)
Without External Trim
TCVos
With External Trim
TCVosn Rp = 100KO
los
TJ = +70°C (Note 1)
TA=+70°C
Device Operating
Input Bias Current
3.0
5.0
Average Input Offset
Voltage Drift
Input Offset Current
Max
0.5
200
5.0
-
0.01
-
IB
TJ = +70°C (Note 1)
TA=+70°C
-
0.06
0.45
0.08
0.80
-
-
0.12
0.60
-
0.14
0.80
-
0.16
1.1
-
O.lE
1.5
0.04
0.30
0.06
0.55
-
0.10
0.40
0.13
0.75
0.08
0.65
0.10
1.2
/J.V/oC
nA
nA
Device Operating
Input Voltage Range
CMVA
Common Mode Rejection Ratio
CMAA VCM = ±CMVA
Power Supply Aejection Aatio
PSRA
Large Signal Voltage Gain
Avo
Maximum Output Voltage Swing VoM
±10.4 +14.7
-11.4
85
98
-
~11.4
±10.26 +14.7
-11.4
94
80
-
V
dB
V
-
85
98
-
-
85
98
-
-
-
80
94
65
200
-
50
180
-
35
130
-
±12
±13
-
±12
±13
-
±12
±13
-
85
Vs = ±10V to ±15V
-
AL ;;.10KO
±10.4 +14.7
98
Vs = ±10V to ±20V
AL;;' 2K,
Vs=±10V
-
-
-
-
dB
Vim V
NOTE 1: Dueto limited production test times the bias currents correspond to junction temperatures. The bias current VS. time (after power-on}
curve clarifies this point. Since1 most amplifiers (in use) are on for more than 1 second, PMI also specifies the bias current for the
warmed-up condition. The warmed-up bias current value is correlated to the junction temp. value via the curves of IS vs. TJ and IS
vs. TA. PMI has a bias current compensation circuit which gives improved bias current over the standard JFET input op amps. 18 and
los are measured at VCM = O.
NOTE 2: Settling time is defined here for a unity gain inverter connection using 2Kn resistors. It is the time required for the error,voltage (the
voltage at the inverting input pin on the amplifier) to settle to within a specified. percent of its final value from the time a 10V step
input is applied to the inverter. See settling time test circuit.
NOTE 3: Parameter is not 100% tested. 90% of all units meet these specifications.
6-86
•
OP·15
TYPICAL PERFORMANCE CURVES
BIAS CURRENT VS. TIME
IN FREE AIR
INPUT BIAS CURRENT VS.
JUNCTION TEMPERATURE
UNITS ARE NOTWARMED·UP
INPUT BIAS CURRENT VS.
AMBIENT TEMPERATURE (UNITS
ARE WARMED·UP IN FREE AIR)
,lLLJ.J.UJ.JJ
Til
U
,__ V vV~
lftNT!~:nt:u~~'.:':':;~:!::::III"tTURi,.l
'J"
'" ~I
~'ftu'
/V
u
~-i:~ ~v v
V
V""~ vV
V
!
!
I
,,~
~~
i
V
I' /' V
ID
OFFSET VOLTAGE
VS TEMPERATURE
DRIFT OF REPRESENTATIVE UNITS
III
311
...
10
~
III
..
, ...
no
Il," I ..
NULLED OFFSET
VOLTAGE DRIFT
VS POTENTIOMETER SIZE
..
(WARMEO·UP IN ~RH A!RI
I-- I--
-
~~::FEE:~::C:~~~:L~~~ ~~~:::::::
CDOVERCANCEllED
25
50
TEM'I!RATURE
7$
re!
SUPPLY CURRENT
VS SUPPLY VOLTAGE
_18j>A.
IrJ-
II
vCM~O
~±,,--~~~~~~~~~~LLU9
-12-10 -8
Ap-TIIIM""'«lPOTENTIOMUER VALUE (11m
_6
....
_202.
8
8
INI'lIT COMMON.MODE VOLT AGE !VOLTS)
OPEN LOOP
VOLTAGE GAIN
VOLTAGE SWING
VS SUPPL Y VOLTAGE
op.,.
. .J-:::::: l::===-I~
--
..
D"
US"C
Of·15
RV ZK
TA"25C
,
!=--
·
/V
,
·
,,
"
SUPPLYVOLTAGEltvl
OUTPUT VOLTAGE
VS LOAD RESISTANCE
,
·
·,,
,
:h
,'II
,
's'
-t-
(.--1-'
·
,.
INPUT BIAS CURRENT
VS COMMON MODE VOLTAGE
I=::-- l I-- t-I-1-:> kc:I--- p<.
,
\:::= e-
,.
'"
t-HH-t-~!: ~5~-t-j--t-i-H
~
,I-- ....-
,,.,I.
.....
.. ...
,.1&11
~:!s.t
f'.-
~~
V
III
............
t--
V k:
~
III
III Ih~
III IV
... ,
,
""
COMMON MODE INPUT
VOLTAGE RANGE
"
L
V
/
,"
'.'
VOLTAGE NOISE VS
SOURCE RESISTANCE
ill LI
III II
~
"Js~ "15\1
IODt----j-----t---H-i----,I
"
i~ 10t----j----t--r-__~~4
~
g
~
~
't---j---t~~f_-t_-~
i D.'t-:7"''T-7f'
'~.----~----~"~.----~----~
SUPI'LV\lOLTAGEf'V)
6·B7
OP-J5
TYPICAL PER FORMAIliCE CURVES
LARGE SIGNAL
SMALL SIGNAL
TRANSIENT RESPONSE
TRANSIENT RESPONSE
CLOSED LOOP BANDWIDTH
AND PHASE SHIFT
VS FREQUENCY
SETTLING TIME
BANDWIDTH VS
TEMPeRATURE
OPEN LOOP
FREQUENCY RESPONSE
:!\J
r-
lA"acAL- Zlm
""'• "f-f--' "', "Htlt\-I--H+tttH
e--
~
l""-
i:I--~~~~~~~-+~++~
Av"·!
~
"
."'+,_..L..L.l..l-lllLL,t-o "":IL:ILLLll.L4
,
FREQUENCVI",".)
SLEW RATE
VS TEMPERATURE
UNDISTORTED OUTPUT SWING
"
COMMON MODE REJECTION
RATIO VS FREQUENCY
0
r--
t-!.EGATI\lE
op". ~Lv,
-
'00'
" '"
"0
--
1",. "MI"
0
"~
~l. ,- t-----
1\
"'S="15\1
1- r-- t -
~
0',5
~
vs··ItV
TA"He
0
0
0
OUTPUT IMPEDANCE
VS FREQUENCY
POWER SUPPLY REJECTION
VS FREQUENCY
0
-
0
....... ''-
""""-
0
I
~tE
'-
"'
."J
y
0
N~~~':IO
0
I~l
"'.~
""-
,.
, ". '00
" ". '00.
VOLTAGE NOISE
VS FREQUENCY
~~
1111111
1i,!11~
VS""
TA"ac
Of·11
,V
/
"y
),.
V
"S·-IIV
l ... ·ue
IfICDIIINERFAEQUENCV
I
1
y
.,
o
6-88
,
1
". ,
•
OP-15
BASIC CONNICTIONS
INPUT OFFSET VOLTAGE NULLING
SETTLING TIME TEST CIRCUIT
y-
NOTE: Vas CAN ae TRIMMEO WIT'" POTENTIOMETERS
MANGINO FROM 10Kn TO 111,40. FOR MOST UNITS
Tevos WILl. 8E MINIMUM WHEN Vos IS ADJUSTED
WIT ... A 100Kn POTENTIOMETER.
APPLICATION INFORMATION
DYNAMIC OPERATING CONSIDERATIONS
As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in order to ensure stability. For
axample, resistors from the output to an input should be placed with the body close to the input to minimize "pick-up" and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground.
A feedback pole is created when the feedback around any amplifier is resistive. The parallel rasistance and capacitance from the input of the
device (usually the Inverting input) to ac ground sat the frequency of the pole. In many instances the frequency of this pole is much greater than
the expected 3 dB frequency of the closad loop gain and consequently there is negligible effect on stability margin. However, if the feedback
poie is less than approximately six times the expected 3 dB frequency a lead capacitor should be placed from the output to the input of the op
amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than
or equal to the original feedback pole time constant.
6-89
PMI
OP-16
PRECISION JFET INPUT OPERATIONAL AMPLIFIER
WIDE BANDWIDTH
GENERAL DESCRIPTION
FEATURES
The OP-16 offers a performance combination not usually
found in the- same op amp-high speed and low input offset
voltage. Not only does the OP-16 out-perform the 156A in
speed and error band, but it is clearly superior to several more
costly hybrid and dielectrically-isolated op amps. In addition,
the OP-16 uses bias current compensation to maintain low
input bias current at elevated temperatures.
The OP-16 was designed to provide real precision performance
along with its high speed. For example the 500;.tV offset
voltage yields less than 1/2 LSB error in a 12 bit, 5V DAC.
Although the OP-16 can be nulled, the design objective was to
provide low offset voltage and drift WITHOUT NULLING.
Systems become MORE COST-EFFECTIVE as the number of
error correcting "knobs" decrease. PMI achieves this performance by use of an improved B I-F ET process coupled with
on-chip zener-zap offset trimming.
•
•
•
•
•
•
•
•
•
•
•
•
'.
High Slew Rate . . . . . . . . . . . . . . . . . . 25V//J.s
Fast Settling to ±O.l% . . . . . . . . . . . . . . 700 nsec
Low Input Offset Voltage . . . . . . . . . 500;.tV MAX
Low Input Offset Voltage Drift ....... 2.0/J.VtC
Wide Bandwidth . . . . . . . . . . . . . . . . . .. 8 MHz
Minimum Slew Rate Guaranteed on All Models
Temperature Compensated Input Bias Currents*
Guaranteed Input Bias Current@ 125°C ..11nA MAX
Bias Current Specified WARMED UP Over Temp.
Internal Compensation
Low Input Noise Current . . . . . . . . . 0.01 pA VHz
High Common Mode Rejection Ratio ..... 100dB
Models With MIL-STD-883A Class B
Processing Available From Stock
makes the OP-16 a true precision, high speed op amp. Because
Most high speed monolithic op amps give settling time specifications to 0.01% error band, and so does PMI. Since 0.01% of
10V is 1mV, it is surprising that these same op amps have
offset voltage errors in the 0.02% to 0.3% range. A large number of applications are in the 0.05% to 0.1 % range, and PM I
also gives specs for these error bands in its settling times. The
fact that 500;.tV is only 0.005% of 10V is why PMI specifies
settling time to a true 0.01% error band.
The combination of low input offset voltage of 500;.tV MAX.,
'slew rate of 25V/;.tsec, and settling time of 700nsec-to 0.1%-
of the input bias current compensation, the maximum input
bias current at 125°C ambient (not junction) temperature is
only 11nA. This kind of performance makes the OP-16 useful
in a wide range of applications.
Applications include high speed amplifiers for current output
DAC's, active filters, sample-and-hold buffers, and photocell
amplifiers. For additional precision JFET op amps, see the
OP-15 and OP-17 data sheets.
PIN CONNECTIONS
SIMPLIFIED SCHEMATIC DIAGRAM
N.C.
TOP VIEW
6A:~::~~M
.,V:ALANCE
4Y-ICASEJ
ORDERING INFORMATION
ORDER: OP-16AjOP-16BJ
-5SoC TO +12SoC
OP-16CJ
OP-16E
OP-16FJ
O"CT0+70°C
OP-16G
Military Temperature Range Devices
With MIL-STD-883A Class 8 Processing
t
·~OTE.
ORDER: OP16-883-AJ
OPl6-883-BJ
OP16-883-CJ
A1. R8 ARl ELECTAor.ICALL'" AD,!U$TED ON CHIP FOR t/lINIMUM OFFsn VOLTAGIi.
·PATENT APPLIED FOR
6-90
•
OP-16
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
OP-16A, OP-16B;OP-16E, OP-16F
±22V
OP-I6C,OP-I6G
±18V
Internal Power Dissipation
All Devices
500mW
(The TO-99(J) package must be derated based
0
on a thermal resistance of 150 elW junction
to ambient or 45° ·CIW junction to case.)
Operating Temperature Range
OP-1SA, OP-16B, OP-I6C
-55°C to +125°C
OP-1SE, OP-1SF, 01'-100
O"c to +7O"C
Maximum Junction Temperature (TJ )
All Devices
+150°C
Differential Input Voltage
OP-16A, OP-16B, OP-16E, OP-16F
OP-16C,OP-16G
±40V
±30V
Input Voltage
OP-16A, OP-1SB, OP-1SE, OP-1SF
OP-1SC,OP-1OO
±20V
±ISV
(Unless otherwise specified the absolute
maximum negative input voltage is equal
to the negative power supply voltage_)
Output Short Circuit Duration
Indefinite
Storage Temperature Range
-65°C to +150"C
Lead Temperature Range (Soldering, SO sec)
OP-16B
OP-16A
ELECTRICAL CHARACTERISTICS
+3OO°C
OP-16C
These specifications apply for Vs = ±15V, TA = 25°C, unless otherwise noted.
Test Cond itions
Min
-
los
Rs = 500
TJ=25 C (Note 1)
Device Operating
I nput Bias Current
IB
TJ = 25°C.(Note1)
Device ODeratina
Input Resistance
Rin
Large Signal Voltage Gain
Avo
RL;;>2KO,
Vs = ±10V
100
240
Output Voltage Swing
VoM
RL -.10K
RL=2K
±12
±11
±13
±12.7
Supply Current
Slew Rate
ISY
SR
Gain Bandwidth Product
GBW
Closed Loop Bandwidth
CLBW
Settl ing Time
to
Parameter
Symbol
I nput Offset Voltage
Vas
Input Offset Current
Typ
0.2
-
10
25
15
20
10 12
50
130
4.6
18
25
S.O
AVCL -+1.0
toO.Ol%
to 0.05% (Note 2)
to.o.10%
-
8.0
19
-
1.7
0.9
0.7
±10.5 +14.8
-11.5
Input Voltage Range
CMVR
Common Mode Rejection Ratio
CMRR
VCM=±CMVR
86
100
Power Supply Rejection Ratio
PSRR
Vs - ±10V to ±20V
Vs = ±10V to ±15V
86
100
Input Noise Voltage Density
Input Noise Current Density
Input Capacitance
en
fo = 100Hz
fo = 1000Hz
in
fo = 100Hz
fn = 1000Hz
-
-
-
20
15
-
0.01
0.01
-
-
CIN
0.5
3.0
5.0
AVCL =+1.0
Max
3.0
-
-
7.0
-
Min
-
75
±12
±11
12
5.5
-
-
-
-
-
Typ
0.4
3.0
5.0
15
20
10 12
220
±13
±12.7
4.6
24
7.6
18
1.7
0.9
0.7
±10.5 +14.8
-11.5
Max
1.0
20·
50
100
250
7.0
-
-
-
0.Q1
0.Q1
3.0
pA
200
500
pA
-
15
20
1012
50
±12
±11
9.0
5.0
-
-
-
200
±13
±12.7
4.8
23
7.2
17
1.8
1.0
0.8
-
-
-
82
100
-
20
15
-
-
-
-
Units
mV
50
125
96
-
3.0
3_0
5.0
-
-
Max
-
82
-
100
-
0.5
+14.8
-11.5
100
-
Typ
±10.3
86
20
15
-
-
86
-
Min
0.Q1
0.01
-
3.0
-
0.9
-
4.0
4.0
-
Vim V
-
V
0
-
8.0
mA
-
V/j.lsec
-
MHz
-
MHz
j.lS
-
V
-
dB
-
nV/..,(H
-
dB
pARHi
pF
The following specifications apply for Vs = ±15V, -55°C';; TA';; +125°C, unless otherwise noted.
Input Offset Voltage
Average Input Offset Voltage
Drift
Without External Trim
With External Trim
Input Offset Current
-
0.4
0.9
-
0.7
TCVos
TCVosn RD = 100KO
TJ = 125°C (Note 1)
los
TA=125°C
Device Operating
-
2.0
2.0
5.0
3.0·
3.0
10
-
-
0.6
1.0
4.0
8.5
-
0.80
1.3
6.0
14.5
TJ = 125°C (Note 1)
TA=125°C
Device Operating
-
1.2
2.0
5.0
11
-
1.5
2.5
7.5
18
Vos
Rs =500
Input Bias Current
IB
Input Voltage Range
CMVR
Common Mode Rejection Ratio
CMRR Vr .. = ±CMVR
PSRR Vs - ±10V to ±20V
Vs = ±10V to ±15V
85
97
85
97
-
-
RL;;>2K,
Vs = ±10V
35
120
±12
±13
Power Supply Rejection Ratio
Large Signal Voltage Gain'
Ava
Maximum Output Voltage Swin! VoM
±10.4 +14.6
-11.3
RL ;;>10KO
6-91
-
-
±10.4 +14.6
-11.3
85
97
-
85
97
-
-
-
-
30
110
±12
±13
2.0
-
-
-
-
-
-
4.5
mV
(Note 3)
15
j.lVfC
-
1.0
1.7
9.0
22
nA
1.8
3.0
10
25
nA
-
V
-
dB
±10.25 +14.6
-11.3
80
93
-
-
80
93
25
100
±12
±13
dB
V/mV
V
OP-16
Op·16E
ELECTRICAL CHARACTER ISTICS
Op·16F
OP-16G
These specifications apply for Vs = ±15V. TA = 25°C. unless otherwise noted.
Parameter
Max
Vos
R s = 50n
-
0,2
0.5
Input Offset Current
los
TJ = 25°C (Note 1)
-
3.0
10
-
3,0
20
-
5.0
25
-
5,0
50
-
Symbol
Test Conditions
~Min
Typ
"Input Offset Voltage
Device Operating
Input Bias Current
IB
TJ = 25°C (Note 1)
Dev ice Operating
Min
-
100
-
-
75
220
-
50
200
-
±12
±13
±12
±13
±11
±12.7
±11
±12,7
Output Voltage Swing
YoM
RL = 10K
±12
±13
±11
±12.7
Gain Bandwidth Product
GBW
Closed Loop Bandwidth
CLBW
Settling Time
ts
AVCL =+1.0
to 0,01%
toO,05% (Note 2)
toO.10%
-
-
-
4,6
7.0
-
25
6,0
-
8.0
19
-
1.7
0.9
-
0,7
5.5
-
7,6
18
1.7
0.9
0.7
Common Mode Rejection Ratio
CMRR
VCM= ±CMVR
86
100
-
86
100
Power Supply Rejection Ratio
PSRR
Vs = ±10V to ±iov
86
100
86
100
V = ±10V to ±15V
-
-
-
20
-
-
fo = 100Hz
-
fo = 1000Hz
Input Noise Current Density
in
fo = 100Hz
fo = 1000Hz
-
15
0,01
0,01
-
±10,5 +14,8
-11.5
Input Offset Voltage
Vas
20
15
0.01
0.01
-
3,0
Input Capacitance
3.0
CIN
The following specifications apply for Vs - ±15V. O°C .. TA .. +70°C. unless otherwise noted.
-
4.6
24
CMVR
en
±10,5 +14.8
-11.5
12
10 12
Input Voltage Range
Input Noise Voltage Density
-
-
7.0
-
9,0
-
5,0
±10.3
-
-
-
0,3
0.75
-
0,55
2.0
5,0
3.0
10
2.0
-
-
3.0
-
T J = +70°C (Note 1)
-
0.04 0,30
T A = +70"C
-
0,07
-
0.10 0.40
-
0.12
0.15
-
0.20
R s = 50n
125
250
10 12
-
50
5,0
15
1.5
200
500
7,2
17
1.8
1.0
0,8
14,8
-11.5
96
-
-
82
00
-
20
-
-
TCVos
With External Trim
TCVosr Rp = l00Kn
los
Device Operating
IB
TJ = +70°C (Note 1)
TA=+70°C
Device Operating
0.70
0.90
±10.4 +14.7
-11.4
85
98
-
-
n
V/mV
-
V
8.0
mA
-
V/".sec
-
MHz
-
".s
MHz
-
V
-
dB
dB
0.01
-
pA/..jHz
0.01
-
3.0
-
15
0,7
nV/..jHz
pF
3.8
±10.4 +14,7
-11.4
85
98
CMVR
VCM - ±CMVR
Power Supply Rejection Ratio
PSRR
Vs = ±10V to ±20V
85
98
-
85
98
Vs = ±10V to ±15V
-
-
-
-
50
±12
Avo
Maximum Output Voltage Swing YoM
RL :>2K.
Vs = ±10V
RL :>10Kil
-
65
200
-
±12
±13
-
15
4.0
0.65
0.15
1.7
0.60
-
0.14
0.80
1.4
-
0,25
2,0
1.1
CMRR
4.0
O.oa
0.45
0.10
Input Voltage Range
-
0,06
Common Mode Rejection Ratio
Large Signal Voltage Gain
pA
mV
(Note 3)
Without External Trim
Input Bias Current
pA
-
Average I nput Offset
Voltage Drift
Input Offset Current
mV
-
4.8
23
82
-
,
15
20
10 12
Units
3,0
3,0
20
240
Max
0.5
-
100
18
Typ
-
RL :>2Kn.
Vo = ±10V
AVCL =+1.0
1.0
50
Rin
ISY
Max
0.4
130
Avo
SR
Typ
15
Input Resistance
Slew Rate
-
20
Large Signal Voltage.Gain
Supply Current
Min
±10.25
14.7
-11.4
94
".vrc
nA
nA
V
-
-
80
-
-
-
dB
80
94
-
I
180
-
35
160
-
V/mV
±13
-
±12
13
-
V
dB
NOTE 1: Due to limited production test times the bias currents correspond to junction temperatures. The bias current V5. time (after power~on)
curve clarifies this point. Since most amplifiers (in use) are on for more than 1 second. PMI also specifies the bias curr"nt for the
warmed-up condition. The warmed-up bias current value is correlated to the junction temp. value via the curves of 18 vs. TJ and 18
vs. TA. PMI has a bias current compensation' circuit which gives improved bias current over the standard JFET input op amps. IS and
los are measured at VCM = O.
NOTE 2: Settling time is defined here for a unity gain inverter connection using 2Kn resistors. It is the time required for the error voltage (the
voltage at the inverting input pin on the amplifier) to settle to within a specified percent of its final value from ,the time a 10V step
input is applied to the inverter. See settling time test circuit.
NOTE 3: Parameter is not 109% tested. 90% of ali units meet these speCifications.
6-92
•
OP-16
TYPICAL PERFORMANCE CURVES
BIAS CURRENT VS. TIME
IN FREE AIR
I
r---
INPUT BIAS CURRENT VS.
JUNCTION TEMPERATURE
UNITS ARE NOT WARMED-UP
.LlLL+.U1Ll
~v
~n'" 'IIi ./
/
lM.'U.J.
..i,.1.":r'7' 1",,;
81»CVIIREIIITYS.TJ ..
IIIIFR.IAIR
I
/
V
I~V
v
WI
OF.FSET VOLTAGE
VS TEMPERATURE
DRIFT OF REPRESENTATIVE UNITS
20
"'~v
....
III
~~
'II
'"
-
vi"'::.,=~:"-:':ri.!£1
tUNI
•
1l1li 110 _
..... " ........ l).4,IIIlfllfII!E ... '
,.,
v
V-
'v v/
V
Vv v
~/vv v
,~
/
"iT
vI-'
'/
V
"1"1
>II
INPUT BIAS CURRENT VS.
AMBIENT TEMPERATURE (UNITS
ARE WARMED-UP IN FREE AIR)
...
,,~
I1D 1411'"
NULLED OFFSET
VOLTAGE DRIFT
VS POTENTIOMETER SIZE
50
'"
70
10
iI
.'. ..T. ,. ~
INPUT BIAS CURRENT
VS COMMON MODE VOLTAGE
IWARMED·UPINFREEAIRI
~ ,t-~~~+t~~~-1-rrH~
i :__
t-t---.1H-t-'-1 ~!:;~5~-t-t--r+-H
--~k++t~ro~
•."~
~ :t-~~~+t~~-1-1-rtr~
i :t-~[~'~rH~~~~~~~
i~~==~b.±~~~-1-1-rtr~
Z~t-"_"_'Ar'O_'r'HT'TMm~KT~~~~rr~~
-,~,"l----I--I----I----l----I-I-I-~
_12_10
-8
-6
-4
-2024
Ii
8
INPUT COMMON-MOOE VOLTAGE IVOL TS)
SUPPLY CURRENT
VS SUPPLY VOLTAGE
VOLTAGE SWING
VSSUPPLY VOLTAGE
OPEN LOOP
VOLTAGE GAIN
,
OPl6
·
L-----::::
,
'''[:::/
. /V
t::::::
V
200K
+25C
OP·'6
RI._2K
~"2SC
·
·
'"
·
125C
,
,.
SUPPLY VOLTAGE I:tV)
OUTPUT VOLTAGE
VS LOAD RESISTANCE
,
·
·,
,
:h
, '1/
·
I
Ih~
I
I
V
COMMON MODE INPUT
VOLTAGE RANGE
III II
1111
II
IIIJs '"16V
lA"ac
.'st-----[---,[-----,!L...,.Lf
_56e
'"
""
.~.----~----~.,,~--~,--~.
SUPPlVVQLTAGE('VI
6-93
·.
LV
.,
."
/
V
L
."
VOLTAGE NOISE VS
SOURCE RESISTANCE
'"
01'-16
TYPICAL PERFORMANCE CURVES
SMALL SIGNAL
TRANSIENT RESPONSE
LARGE SIGNAL
TRANSIENT RESPONSE
SETTLING TIME
SETTLINGTIME-"...
CLOSED LOOP BANDWIDTH
AND PHASE SHIFT
VSFREQUENCY
BANDWIDTH VS
TEMPERATURE
OPEN LOOP
FREQUENCY RESPONSE
e:·~~llit
t- b,
C\
"
TA'2S~-
~
1'\
1'\
0
_".1.,_..L..L.u.l.J.l.l±-_.u.w..w.J..U~
_H
SLEW RATE
VS TEMPERATURE
UNDISTORTED OUTPUT SWING
"j,J
I-+-
+---f-ffi-+++++-f- ~~: ~5V
1'\
["
,
COMMON MODE REJECTION
RATIO VS FREQUENCY
-t----
14V'+1
t-
-j--
" 1---1---.
t-t-----j----t----T~---'rr - - j--- j - JO~~ITIVE-t-+-t------t---l
r---t---
H
I-+--+---T-+--~.
!\
OPI6
liS
151/
~,
~~..~"~.-L-L~.J..U~,.~"~.~~-LLLUt,
FREQUfNCY(H,1
POWER SUPPLY REJECTION
VS FREQUENCY
0
0
0
-
-......
"
0
"-
OPIS,,!
"-
N:~:I~~
"0
0
OUTPUT IMPEDANCE
VS FREQUENCY
TA"i c -
0
POSITIVE
SUPPLY
,
"-
'""-
1111
··v
VOL TAG-E NOISE
VSFREQUE~V
~"" tffi
'."
V
9f.;11
Vs~ .ISV
fA ·2~'·C
"~
,,(
'"
""
6-94
,.
".
j--
•
QP.16
BASIC CONNECTIONS
SETTLING TIME TEST CIRCUIT
INPUT OFFSET VOLTAGE NULLING
2knG.l"
.... OTE: Vos CAN 815 TRIMMED WITH POTENTIOMETERS
RANGING PROM IOkU TO lMO.
FO~
MOST UNITS
Tevos WILL BE MINIMUM WHEN Vos IS ADJUSTED
WITH A 100Kfi POTENTIOMETER_
APPLICATION INFORMATION
DYNAMIC OPERATING CONSIDERATIONS
As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in order to ensure stability. For
example, resistors from the output to an input should be placed with the body close to the input to minimize "pick-up" and maximize the fre·
quency of the feedback pole by minimizing the capacitance from the input to ground.
A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capacitance from the input of the
device (usually the inverting input) to ac ground set the frequency of the pole. In many instances the frequency of this pole is much greater than
the expected "3 dB frequency of the closed loop gain and consequently there is negligible effect on stability margin. However, if the feedback
pole is less than approximately six times the expected 3 dB frequency a lead capacitor should be placed from the o~tPut to the input of the op
amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than
or equal to the original feedback pole time constant.
6·95
OP-17
PMI
PRECISION JFET INPUT OPERATIONAL AMPLIFIER
WIDE BANDWIDTH DECOMPENSATED (AVMIN
GENERAL DESCRIPTION
With an unusual performance combination of 400nsec settling
time and an input offset voltage of 500llV MAX., the OP-17
clearly outperforms the 157A op amp. In addition, the OP-17
is superior in both cost and performance to several dielectricallyisolated and hybrid op amps. Bias current compensation provides low input bias current at elevated temperatures.
The OP-17 was designed to provide real precision performance
along with its high speed. For example the 500llV offset
voltage yields less than 1/2 LSB error in a 12 bit, 5V DAC.
Although the OP-17 can be nulled, the design objective was to
provide low offset voltage and drift WITHOUT NULLING.
Systems become MORE COST-EFFECTIVE as the number of
error correcting "knobs" decrease. PM I achieves this performance by use of an improved BI-FET process coupled with
on-chip zener-zap offset trimming.
Most high speed monolithic op amps give settling time specifications to 0.01% error band, and so does PM!. Since 0.01% of
10V is 1 mV, it is surprising that these same op amps have
offset voltage errors in the 0.02% to 0.3% range. A large number of applications are in the 0.05% to 0.1% range, and PMI
also gives specs for these error bands in its settling times. The
fact that 500llV is only 0.005% of 10V is why PMI specifies
settling time to a true 0.01% error band.
=5)
FEATURES
_
_
_
_
_
_
_
_
_
_
_
_
_
High Slew Rate . . . . . . . . . . . . . . . . . . . 70V/lls
Fast Settling to ±0.1% . . . . . . . . . . . . . . 400 nsec
Low Input Offset Voltage . . . . . . . . . 500 IlV MAX
Low Input Offset Voltage Drift . . . . . . . 2.0 IlV/oC
Big Gain Bandwidth Product . . . . . . . . . . . 30 MHz
Minimum Slew Rate Guaranteed on All Models
Temperature Compensated Input Bias Currents·
Guaranteed Input Bias Current @ 125° C ..11 nA MAX
Bias Current Specified WARMED UP Over Temp.
Internal Compensation
Low Input Noise Current . . . . . . . . . 0.01 pA y'HZ
High Common Mode Rejection Ratio . . . . . . 1 OOdB
Models with MIL-STD-883A Class B
Processing Available From Stock
of the input bias current compensation, the maximum input
bias current at 125°C ambient (not junction) temperature is
only llnA. This kind of performance makes the OP-17 useful
in a wide range of applications.
Applications include high speed amplifiers for current output
DAC's, active filters, and photocell amplifiers_ For unity gain
fast follower applications seethe OP-15 and OP-16 precision
JFET op amp data sheets.
The combination of low input offset voltage of 500J,LV MAX.,
slew rate of 70V/llsec, and settling time of400nsec-to 0.1%makes the OP-17 a true precision, high speed op amp. Because
PIN CONNECTIONS
SIMPLIFIED SCHEMATIC DIAGRAM
N.C.
'''ANCS'
. ,,_
-IN 2
_'"
+
6 OUT
"ALANCE
4 V-(CASE)
ORDERING INFORMATION
ORDER: OP-17AJ}
OP-17BJ
-5SoC TO +125°C
OP-17CJ
n
OP- 17E
OP-17FJ
OP-17GJ
O°C-TO +70°C
Military Temperature Range Devices
With MIL-STD-883A Class B Processing:
ORDER: OP17-883-AJ
OP17-883-BJ
OP 17-883-CJ
·PATENT APPLIED FOR
6-96
I
OP-17
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
OP-17A, OP-17B, OP-17E, OP-17F
OP-17C,OP-17G
±22V
±lBV
Internal Power Dissipation
All Devices,
(The TO-99(J) package must be derated based
500mW
Differential Input Voltage
OP-17A, OP-17B, OP-17E, OP-17F
OP-17C,OP-17G
±40V
±30V
Input Voltage
OP-17A, OP-17B, OP-17E, OP-17F
OP-17C,OP-17G
±20V
±16V
on a thermal resistance of 150°C/W junction to
ambient or 45'C/W junction to caseJ
Operating Temperature Range
OP-17A, OP-17B, OP-17C
OP-17E, OP-17F, OP-17G
Maximum Junction Temperature (TJ)
All Devices
(Unless otherwise specified the absolute
maximum negative input voltage is equal
to the negative power supply voltageJ
-55'C to +125'C
O'C to +70'C
Ou,tput Short Circuit Duration
Indefinite
Storage Temperature Range
-65'C to +150'C
Lead Temperature Range (Soldering, 60 sec)
+150'C
ELECTRICAL CHARACTERISTICS
OP-17A
OP-17B
+3OO'C
OP-17C
These specifications apply for Vs = ± 15V, T A = 25'C, unless otherwise noted.
Parameter
SYl1\bol
Input Offset Voltage
Vos
I nput Offset Current
10•
Input Bias Current
IB
Test Conditions
Min
Rs - 50n
TJ - 25'C (Note 1)
Device Operating
-
0.2
-
3.0
5.0
10
25
15
20
10 12
50
130
T J = 25'C (Note 1)
Device Operating
-
-
Max
0.5
Input Resistance
Rin
Large Signal Voltage Gain
Avo
RL;' 2Kn,
Vs = ±10V
100
240
-
Output Voltage Swing
YoM
RL = 10K
RL=2K
±12
±11
±13 .
-
Supply Current
Slew Rate
ISY
SR
Gain Bandwidth Product
GBW
Closed Loop Bandwidth
CLBW
Settling Time
to
-
Typ
AVCL =+5.0
AVCL =+5.0
100.Q1%
to' 0.05% (Note 2)
to.0.l0%
Input Voltage Range
CMVR
Common Mode Rejection Ratio
CMRR VCM= ±CMVR
PSRR Vs = ±10V to ±20V
Vs = ±10V to ±15V
Power Supply Rejection Ratio
I nput Noise Voltage Density
I nput Noise Current Density
Input Capacitance
en
in
±12.7
4.6
fo - 100Hz
fo = 1000Hz
CIN
0.4
3.0
5.0
-
15
20
10 12
-
75
7.0
Typ
-
±12
±11
-
50
125
pA
100
250
-
200
500
pA
220
-
15
20
10 12
50
±13
±12.7
-
±12
±11
4.6
20
30
15
28
-
11
-
-
10
86
100
86
100
-
-
20
15
0.Q1
0.01
3.0
-
-
-
-
1.5
0.5
0.4
±10.5 +14.8
-11.5
86
100
86
100
-
-
-
Units
3.0
5.0
66
-
Max
-
35
-
Typ
20
50
-
1.5
0.5
0.4
Min
0.5
70
-
Max
-
45
±10.5 +14.8
-11.5
fo = 100Hz
fo = 1000Hz
Min
20
15
0.Q1
0.Q1
3.0
1.0
7.0
-
-
-
3.0
mV
-
n
200
±13
±12.7
-
V
-
8.0
mA
-
V/jJ.sec
4.8
25
62
11
26
-
9
-
1.6
0.6
0.5
-
V/mV
MHz
-
±10.3
+14.B
-11.5
-
82
96
-
dB
-
100
-
dB
-
-
-
82
-
-
-
MHz
jJ.s
V
-
0.01
0.Q1
-
-
3.0
-
pF
-
0.9
4.5
mV
-
4.0
4.0
-
20
15
nV/y'"Hz
pA/..jHi
The following .pecification. apply for V. = ±15V, -65'C';; TA" +125'C, unless otherwise noted.
Input Off.et Voltage
Average Input Offset Voltage
Drift
Without External Trim
With External Trim
Input Offset Current
Input Bias Current
-
0.4
0.9
-
0.7
TCV o •
TCVo •n Rp= 100Kn
TJ -125'C (Note 1)
10•
TA=125'C
Device Operati n9
-
2.0
2.0
5.0
10
-
3.0
3.0
0.6
1.0
4.0
8.5
-
0.8
1.3
6.0
14.5
-
1.!)
9.0
22
nA
1.7
TJ = 125'C (Note 1)
TA = 125'C
Device Operating
-
1.2
2.0
5.0
11
-
1.5
2.5
7.5
18
-
1.8
3.0
10
25
nA
-
±10.25 +14.6
-11.3
-
Vos
IB
R s = 50n
±10.4 +14.6
-11.3
Input Voltage Range
CMVR
Common Mode Rejection Ratio
CMRR VCM = ±CMVR
85
97
Power Supply Rejection Ratio
PSRR
V. - ±10V to ±20V
V. = ±10V to ±15V
85
97
-
-
RL;' 2K,
V. = ±10V
35
±12
Large Signal Voltage Gain
Avo
Maximum Output Voltage Swing YoM
RL ;"10Kn
-
-
-
±10.4 +14.6
-11.3
2.0
-
-
-
85
97
-
80
85
97
-
-
-
-
-
80
93
93
(Ndte 3)
15
jJ.V/'C
-
V
-
dB
-
dB
120
-
30
110
-
25
100
-
V/mV
±13
-
±12
±13
-
±12
±13
-
V
6-97
OP-17
ELECTRICAL CHARACTERISTICS
OP-17E
OP-17G
.OP-17F
These specifications apply for Vs = ±15V. TA = 25°C. unless otherwise noted.
Parameter
. Input Offset Voltage
Input Offset Current
Symbol
Vos
los
Test Conditions
Rs -50!!
TJ = 25°C (Note 1)
Device Operating
Input Bias Current
IB
TJ = 25°C (Note 1)
Device Operating
Min·
-
\Typ
0.2
3.0
10
5.0
25
15
50
20
130
10 '2
-
Input Resistance
Rin
Large Signal Voltage Gain
Avo
RL;> 2K!!.
Vo = ±lOV
100
240
Output Voltage Swing
YoM
RL = 10K
±12
±13
RL =2K
±11
±12.7
Supply Current
ISY
Slew Rate
SR
Gain Bandwidth Product
GBW
Closed Loop Bandwidth
CLBW
Settling Time
ts
AVCl =+5.0
AVCL = +5.0
00.01%
o 0.05% (Note 2)
TO 0.10%
Input Voltage Range
CMVR
4.6
15
100
20
50
100
Vs = ± 10V to ±15V
-
-
20
15
0.01
0.Q1
!!
±13
-
±12
±13
-
±11
±12.7
-
V
±12.7
±11
4.6
1.5
0.5
0.4
±10.5 +14.8
-11.5
7.0
-
4.8
8.0
rnA
MHz
9
MHz
1.6
-
}Js
0.6
0.5
-
+14.8
-
26
±10.3
-Tr:5
-
82
-
-
-
-
am
-
-
0.Q1
-
3.0
-
96
-
82
100
-
20
15
0.01
0.Q1
3.0
1.5
0.7
Average Input Offset
Voltage Drift
TCVos
With External Trim
TCVosn Rp = lOOK!!
los
TJ = +70°C (Note 1)
TA = +70°C
-
3.8
3.0
10
-
4.0
15
3.0
-
-
4.0
-
0.45
-
0.08
0.65
1.1
-
0.15
1.7
0.14
0.80
0.25
2.0
0.04
0.30
0.07
0.70
-
0.10
0.40
-
0.12
0.60
-
10.15
0.90
-
0.20
1.4
-
2.0
5.0
2.0
-
0.06
0.10
Device Operating
Input Bias Current
-
V/}Jsec
V
dB
dB
nV/..jHz
pA/..jHz
pF
mV
(Note 3)
Without External Trim
Input Offset Current
pA
-
11
100
0.55
10 '2
62
100
15
200
500
-
86
20
15
20
25
86
Input Capacitance
3.0
CIN
The following specifications apply for Vs = ±15V. O°C .. TA" +70°C. unless otherwise noted.
0.3
0.75
Input Offset Voltage
Rs - 50!!
Vos
pA
V/mV
10
100
125
-
-
86
50
5.0
-
11
0.4
3.0
\ Units
mV
200
-
0.5
3.0
50
±12
-
Max
-
28
-
TVp
0.5
-
'0 '2
220
15
1.5
1.0
-
-
86
fo= 100Hz
-
30
Vs = ±10V to ±20V
fo = 1000Hz
20
50
20
VCM= ±CMVR
in
3.0
5.0
75
-
Min
-
66
CMRR
fo = 1000Hz
-
Max
0.4
35
±10.5 +14.8
-11.5
fo= 100Hz
-
Typ
-
PSRR
Input Noise Current Density
7.0
-
70
Common Mode Rejection Ratio
en
-
Min
45
Power Supply Rejection Ratio
Input Noise Voltage Density
Max
0.5
IB
TJ = +70°C (Note 1)
TA = +70°C
-
.
}JVrc
nA
nA
Device Operating
I nput Voltage Range
CMVR
Common Mode Rejection Ratio
CMRR VCM = ±CMVR
Power Supply Rejection Ratio
PSRR
Large Signal Voltage Gain
Avo
Maximum Output Voltage Swing YoM
±10.4 +14.7
-11.4
85
98
-
80
-
-
180
-
±13
-
Vs = ±10V to ±20V
85
98
-
85
98
Vs = ±10V to ±15V
-
-
-
-
50
±12
RL ;> 2K.
Vs= ±10V
RL;> 10K!!
65
200
-
±12
±13
-
±10.2~
+14.7
-11.4
94
±10.4 +14.7
-11.4
85
98
V
80
94
-
35
160
-
V/mV
±12
±13
-
V
dB
dB
NOTE 1: Due to limited production t8st times the bias currents correspond to junction temperatures. The bias current vs. time (after power-on)
curve clarifies this point. Since most amplifiers (in use) are on for more than 1 second, PMI also specifies the bias current for the
warmed-up condition. The warmed-up bias current value is correlated to the junction temp. value via the curves of IS vs. TJ and 18
vs. TA. PMI has a bias current compensation circuit which gives improved bias current over the standard JFET input op amps. IS and
los are measured at VCM = O.
NOTE 2: Settling time is defined here for a gain of five inverter connection using 2Kn and 400,0 resistors. It is the time required for the error
voltage (the voltage at the inverting input pin on the amplifier) to settle to within a specified percent of its final value from the time
a 2V step input is,i'JIpplied to the inverter. See settling time test circuit.
NOTE 3: Parameter is not 100% testecl. 90% of all units meet these scecifications.
6-98
•
OP-17
TYPICAL PERFORMANCE CURVES
.!
a
-
.- 1 l..LJ,+J..lJ,..Ll
f------.-- IIIM I;\lRR'OfVII.'
INFMHA,R
/'
/
'OOpA
..
15'A.MAl<
I
l,.!."i·~V ~v
"""~7V
,sTAn.
.M
~~:·f;~:~
i
/.~
,.~
..--. . . .
or·, Tn
'0 .... 0
'"
'"
"MEAFTERPOI'I"R"'I'I'1.IEI)_SEC~
..
,.
'
OFFSET VOLTAGE
VS TEMPERATURE
DRIFT OF REPRESENTATIVE UNITS
.
'r--
I'--
.I--rl - t--
-,
-;;>
A~ l -I-
-.
~
."
"
<
::::-I >--
..
"
~
I-- I--
-
><
~
2
~
!~
~
'"
.•
eo.,
..
'
""'.
..,
"'''
'"
'00"0120130100160
,."
V
00
10
10
lID
..
T'
100
" • • 20
I"
VS·"'SV
""1>1"
"\
~
25 C
0UNOERCANCEllEOI8=+1~IIiIVCM·O
.."'
~
V
. .
.
.......
-00
-
'"
lip-TRIMMING POTENTIOMETER VALUE (KQ)
~"
,-
-~
-12-10
_6
-8
-4_2
., .. .
"
VOLTAGE SWING
VS SUPPLY VOLTAGE
~
-
",,"'
ala
I
OP·17
Rl'2K
TA'25C
g
5~
/v
~
'" "
'"
•g
~
"
~
.
"
"
"
I
I I~
I V
... ,
III I
5
/
!
."
'15
i
""
·10
i
"
OUTPUT LOAO RESISTANCE _ K,I
'"
v::
v
.,
C
V
~
g
~n'
:h
,'II
.•.. ,.
~"
TA~25
POSITIVE
V v t';""" FROM-55CTOI25C
/
·" .
NEGATIVE
,"AA"
V
/
r----
10
..
~
."
~
III I
IIJs =
'"
,~
SUPI"LV'iOlTAGEI±VI
COMMON MODE INPUT
VOLTAGE RANGE
OUTPUT VOLTAGE
VS LOAD RESISTANCE
1012
INPUT COMMON-MOOE VOl. TAGE (VOL 151
~
'"
'1
CllOYERCANCELLEOIS= _1SpA "VCM ~O
"
"
~~.!72KQ_
SUPPLY VOLTAGE I VI
I-
(i)PERFECTLYCANCELtED 18 ~ O.VCMFO
~
'>-
'"
TA
'"
/"'"'
,
'00
(WARMEDUPINFRHAIRI
00
,~,
""
no , ..
"""'ENTTaM'E"AnJRE_C
00
+2Soc
,.-/
V
INPUT BIAS CURRENT
VS COMMON MODE VOLTAGE
..., ~1Z6·C
:::::-
...
". ,
ttl
",-
",-
V
rr
-55C
..
v~V
V
OPEN LOOP
VOLTAGE GAIN
OP11
Y V
...
TYPICALOR'FTBANO
z~
5.5
V
...
Of'l1TVP
0
.
vV' V
'D.pA
"-
> ,
SUPPLY CURRENT
VS SUPPLY VOLTAGE
..
.
VV
V
'00
5
,
~
-
···
4
~
."
"
TEMPERATUREf"C!
SO
v
vvv
"M
-".I!'fClIl""E ..... ER"'URE_c
6
~
><;.,
V
..
~~~:~;~~:;~":.::;J, V
".AA."."'",,'''V'
,~,..
NULLED OFFSET
VOLTAGE DRIFT
VS POTENTIOMETER SIZE
(W.11.1
vs·'u;v
'i"""--
3D
:III
~~ V
V
"'V
._.
TTl vV)'''
V'
""n."
,
l
INPUT BIAS CURRENT VS.
AMBIENT TEMPERATUREi (UNITS
ARE WARMED-UP IN FREE AIR)
INPUT BIAS CURRENT VS.
JUNCTION TEMPERATURE
UNITS ARE NOT WARMED-UP
BIAS CURRENT VS. TIME
IN FREE AIR
.,
m
SUPPLY VOLTAGE I V)
."
~
VOLTAGE NOISE VS
SOURCE RESISTANCE
.-
~.!7~C
VS,·15V
~Ioa
~~H~~~
~
~
~
m
o
'
.,~
ii
0.1
\O~Hj
,I lQkHz ~OR RS
V
.L l/
~~
e"""m" -
... ----.M~ ,./
(i)J(»INSON RESISTOR NOISE
(DAMPlIFIER MOISE MEASURED
WITH SOURCE RESISTOR
·m
SUPPlYVOLTAGEI·VI
6-99
"
.
."
O.IM
.~
.
SOURCE RESISTANCE (!ll
w
'OG
OP-17
TYPICAL PERFORMANCE CURVES
LARGE SIGNAL
SMALL SIGNAL
TRANSIENT RESPONSE
TRANSIENT RESPONSE
SETTLING TIME
,
,~,
,
,
v.
.,
II /
01'·11
"S··1511
TA"2liC
A,,--6
\\ '\
.
,~,
'm'
.L
,
"
SETTLING TIME 'p_1
CLOSED LOOP BANDWIDTH
AND PHASE SHIFT
VS FREQUENCY
BANDWIDTH VS
TEMPERATURE
OPEN LOOP
FREQUENCY RESPONSE
,
",l
~'~7.J
:- r---
VS·+l5V
TA=2!o~-
r---
1"~
16
J".,
.o.V'+6
."
~ 121-:~:::!lH--H-N-t~-\\++++ttt-tt
10
r-----t--~O-L00f'8y.rowl()TH.AV.+6
,
I
BANDWIDTH VARIATION FROM
~
"
T.o.-25'C
1\
\
r--..
, r--- t:h
[\
·
r------
J11.,,-+5
COMMON MODE REJECTION
RATIO VS FREQUENCY
t--
"S"ISV
r-----. t--.-
----t- 1----
OP17
"s'
15\1
TA"2l;C
OUTPUT IMPEDANCE
VS FREQUENCY
POWER SUPPLY REJECTION
VSFREQUENCY
,
:--...
~~72J.~-±-:' " POIiITfVESUPPlV
-........
EGATIV
.,
·
lMH~
FREQUENCY(H"
""""-
'\.
,-,
VOLTAGE NOISE
VS FREQUENCY
liiJ1i,1
"S··15V
ilif'
· jll~~
V
.o.v· 'O
V
"''\.
'"
r
·
,
,
2OV1s
lIIEGAr~
.o.v·+6
·
«
·r---- t--.-
J
OP.J7
vs··'~~_
·,
S
SLEW RATE
VS TEMPERATURE
UNDISTORTED OUTPUT SWING
·
'l"V
V
,
/'
,,,
'00'
6-100
,.
'"
•
Isss7251
PM
INSTRUMENTATION OPERATIONAL AMPLIFIER
GENERAL DESCRIPTION
FEATURES
The SSS7lS Series of monolithic Instrumentation Operational
Amplifiers is specifically designed for accurate high-gain
amplification of low level input signals in the presence of large
common mode voltages. Superior DC input characteristics
include very low offset voltage and current, extremely high
open loop gain, low l/f and wideband noise and a complete
absence of "popcorn" noise. The extremely low offset voltage
drift is further improved by an advanced nulling technique
that provides optimum TeVOS performance when Vos has
been nulled to zero. Very high common mode and power
supply rejection enable accurate performance in the presence
of large spurious Signals.
Flexible external compensation provides wide bandwidth and
high slew rate operation in high closed-loop gain applications.
The superior long term stability, and compatibility with
MI L-STD-883 processing make the SSS725 an excellent choice
for high reliability process control and aerospace applications,
including strain gauge and thermocouple amplifiers, low noise
audio amplifiers and instrumentation amplifiers. The SSS725
SIMPLIFIED SCHEMATIC
_
Very High Voltage Gain ....... 1.000 kVN Min
low Offset Voltage and Offset Current
•
•
•
•
•
•
-
Low Drift vs. Temperature (TCVos) .. 0.8 jJ.vtc Max
Low Input Voltage and Current Noise
Low Offset Voltage Drift with Time
High Common Mode Rejection ....... 120 dB Min
High Power Supply Rejection. . . . . .• 2 jJ.VN Max
Wide Supply Range ............ ±1.5V to ±22V
±3OV Input Overvoltage Protection
MI L-STD-883 Processing Available
Series are direct replacements .for all 725 types providing
superior DC and noise performance plus the unique feature of
complete input differential voltage and output short circuit
protection. Further improvements in input performance plus
complete internal frequency compensation are available:
request the OP-05 Instrumentation and OP-07 Ultra-low Offset
Voltage Operational Amplifier data sheets.
PIN CONNECTIONS AND ORDERING INFORMATION
TOP VIEW
TO-99 (J-Suffix)
IN\IER1W8
,NPUT 2
• OUTPUT
NON-INVERTIN. 5
IIIPUT
2
4V-ICAlEI
•
V.. TRIM 3
INY. .....T &-.&-.....' ....
NOII"lft _PUT II
7
V.n.l1
"V.•...". S . . .
tou,QU,Rlt.R20
eOJllPAIS! TItE QUTPut PRQttCTION CIRCUIT.
14
15
12v..T_
.. v+
.-.
IOClUTPUT
g- .
V- •
.~p~~~ I'ROTtC'fIOtlCCUIT.
IION-I.V. INPUT 4 ·
v-
6-101
ORDER: SSS725AJ
SSS725J
SSS725BJ
SSS725EJ
SSS725CJ
•
._,...
• V.
T OUI'PUT
.~
14 PIN DIP (Y·Suffix)ORDER: SSS725AY
SSS725Y
SSS725 BY
SSS725EY
SSS725CY
-Formerly "P" Suffix
10 PIN FlATPACK
(l-Suffix)
ORDER: SSS725Al
SSS725l
SSS725Bl
555725
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Internal Power Dissipation (Note 1)
Differential Input Voltage
Input Voltage (Note 2)
Output Short Circuit Duration
Storage Temperature Range
Operating Temperature Range
±22V
500mW
±3QV
±22V
Indefinite
_65°C to +150°C
_55°C to +125°C
_25°C to +85°C
O°C to +70°C
SSS725A, SSS725
SSS725B
SSS725E, SSS725C
Lead Temperature Range (Soldering, 60 sec)
300°C
NOTES:
Note 1: Maximum package power dissipation vs. ambient temperature.
Maximum Ambient
Temperature for Rating
Package Type
Derate Above Maximum
Ambient Temperature
80°C
100°C
62°C
TO·99 (J)
DUAL·IN-LiNE (Y)
FLAT (L)
7.1mWfC
10.0mWfC
5.7mWfC
Note 2: For supply voltages less than ±22V, the absolute maximum input voltage is equal to the supply voltage.
FREQUENCY COMPENSATION
COMPENSATION CIRCUIT
COMPENSATION VALUES
Avcl
Cl
(I'F)
10000
10K
50pF
-
-
1000
470
.001
-
-
100
47
.01
-
10
27
.05
270
.0015
1
10
.05
39
.02
USE Ra (sSIAl
WITH CAPACITIVE
LOAD
R2
(n)
"The compensation network (Rl, Cl) should
Rl
(n)
C2
(I'F)
be returned to the
V~terminal.
If the network
is returned to ground, serious degradation of
power supply rejection performance with frequency will occur. See typical curves, page 6
(PSRR vs FREQUENCY).
**
The trimming potentiometer should be
20Kn for optimum nulled offset voltage
drift. See page 6 for change in drift caused
by potentiometers ranging from 5Kn to
100Kn.
TYPICAL DYNAMIC PERFORMANCE CURVES
OPEN LOOP RESPON$E
FOR VALUES OF COMPENSATION
CLOSED LOOP FREQUENCY RESPONSE
FOR VALUES OF COMPENSATION
80
~~VS'j:15V
C,=50pF R,II"Okoli
80
~
z
C
CD 80
§
.
z 501--t--+_--'
i.
8oJ
...."
40
20
0
0
oJ
:!;
ol--4r-~---+---r
u
-20
C,
=.OOI'~ R, "470n
I
I
c. =.OIJlF
I
R, =470
=
:RtS
C1 .OBJIF RI =27.Q
s
Ion
I
C,".OZ.F II, -un
I
I
I
2
i'-....
......
I
C.-.OOl«'..,,. R.II'2TM
C,=.OBJIF R,
T."U"C
I
~
i'...
I
FREQUENCY (HI)
6-102
........
i"-..
.....
I
4.
........
I 1M
...........
SLEW RATE USING RECOMMENDED
COMPENSATION NETWORKS
555725
ELECTRICAL CHARACTERISTICS
These specifications apply for V s
Parameter
SSS725A
SSS725
= ±15V, T A = 25°C, unless otherwise noted.
Symbol
Test Conditions
Input Offset Voltage
VA'
R, ~ 20kn
Input Offset Current
Min
Typ
Max
Min
Typ
Max
Units
--
0.06
0.1
--
0.2
. 0.5
mV
los
--
0.3
1.0
--
0.75
5.0
nA
Input Bias Current
IB
--
30
70
--
30
80
nA
fa = 10Hz (Note 1)
--
en
fa'"' 100Hz (Note 1)
---
9.0
B.O
7.0
15.0
9.0
--
Input Noise Voltage Density
----
0.5
0.25
0.15
1.2
0.6
0.25
----
15.0
9.0
7.5
nV/..jH;
7.5
9.0
8.0
7.0
0.5
0.25
0.15
1.2
0.6
0.25
PA/..jH;
0.8
.1.8
--
0.7
1.8
--
Mn
1.000,000
3,000,000
--
1,000,000
3,000,000
--
VIV
±12.5
±12.0
--
±1'.0
±13.0
±12.8
±12.5
±13.5
fa = 1000Hz INote 1)
fa"" 10Hz (Note 11
Input Noise Current Density
;n
fa
100Hz (Note 1)
=
fa = 1 DOOHz (Note 1)
I nput Resistance
Ain
Voltage Gain
Ava
V o =±10V
Output Voltage Swing
Vom
RL ;;'10kn
RL ;;'2kn
RL;;'lkn
±12.5
±13.0
-
--
±12.0
±12.8
--
--
±ll.0
±12.5
--
V
V
V
±14.0
--
±13.5
±14.0
--
V
--
120
126
--
dB
2.0
---
La
<;.0
INN·
105
120
mW
I nput Voltage Range
CMVR
Common Mode Rejection Ratio
CMRR
Rs';; 20kn
120
126
Power Supply Rejection Ratio
PSRR
As';; 20kn
--
0.5
Large Signal
Voltage Gain
Power Consumption
--
RL ;;'2kn
Large Signal
Power Consumption
--
--
Pd
90
105
-
AL" 500n
V o "'±O.5V
Vs=±3V
Avo
V s;.±3V
Pd
The following specifications apply for Vs
- -
100.000
600,000
--
100,000
600,000
--
4
6
--
4
6
mW
V/V
= ± 15V, -55°C ..;;; TA .;;; +125°C, unless otherwise noted.
Input Offset Vortage
IWithout external trim)
Vas
R,';; 2Okr!
--
0.08
0.18
--
0.3
0.7
mV
TeVos
A,=50n INote 2)
--
0.3
0.8
--
0.7
2.0
IJV/oC
TeVosn
Rs:50Q (Note 2)
--
0.2
0.6
--
2
--
0.25
Drift (without external trim)
Average Input Offset Voltage
Drift (with external trim)
Input o.ffset Current
Average Input Offset Current Drift
0.6
2.0
Average Input Offset Voltage
TeVos
TeV asn
los
Rs SOn (Not. 21
Rs 50n INot. 21
TAMAX
TA MIN
Telos
--
---
--
-- --
--
4.5
0.7
(Note 11
--
1.4
(Note 1)
0.2
0.6
--
0.5
(Note 11
/lV/C
0.65
5.0
7.0
0.9
40
4
(Note 1)
--
30
35
SO
100
--
1.5
2.0
15
nA
3.0
25
nA
-- - -
14
ISO
(Note 11
pAle
35
45
110
ISO
nA
nA
97
113
--
dB
3.0
15
/lV/V
300,000
3.200,000
2,700,000
--
±11.0
±12.6
IS
Common Mode Rejection Ratio
CMRR
RS "20kn
115
lIS
--
Power Supply Rejection Ratio
PSAA
AS .; 20kSl
--
1.5
7.0
- -
--
400,000
--
Va ,,0V; AL,,2kn
Large Signal Voltage Gair.
Maximum Output Voltage Swing
Avo
Vom
1,000,000
3,200,000
. TAMIN
SOO,OOO
2,700,000
AL ;;'2kll
±12.0
±12.6
TAMAX
---
/lV/C
--
TAMAX
TAMIN
Input Bias Current
0.5
---
VIV
V
Note 1: Parameter is not 100% tested, 90% of all units meet these
performance indicated if both sides of the contacts are not kept at
specifications.
Note 2: Thermoelectdc voltages generated by dissimilar metals at the
contacts to the input terminals Can prevent the realization of the
approximately the same temperature.
Theref~re,
the device ambient
temperature should not be altered without simultaneously changing the
contact temperature.
6-105
.555725
TYPICAL PERFORMANCE CURVES
TRIMMED OFFSET VOLTAGE
VS TEMPERATURE
OFFSET VOLTAGE
VS TEMPERATURE
OFFSET VOLTAGE DRIFT
WITH TIME
'.0
-
SSS72
r- r-"'~ I
, ~ --I--r,"';--I
I
11111111
~
-
NED ON AT TeO
~ ,l\.+-rrrimr-rnnmr.."
.g
~
~
SSS725A
.....
~
~
I
i'-
WARM'UP DRIFT
ERROR SANO
~
-'1/i-ml1nr-'-'TI1T",1\
L.ONG TERM DRIFT
~ ;~~~M~1~~IVEI
R."50n
.0
TRIMMED OFFSET VOLTAGE
DRIFT ASA FUNCTION OF TRIMMING
POTENTIOMETER (Rpl SIZE AND VOS
.
0
I
..
!-" ......
!-i--",""" ~
0
~'::::-' I
.5 SSS12SA
-t
SSS~
i"'"
50
100
100
OFFSET CURRENT
VS TEMPERATURE
"-
I
I
,
0".2
0.4
0.6
0.8
1.0
1.2
UNTRIMMED OfFSET VOLTAGE VOl (mV)
(CURVES ARE SYMMETRICAL AP"'UT nRO FOR VOl~OI
.
"':-..
:.........
.........,
I
",,-1Is"tlll
I
I .,
~(!)~~~:::,~:;..t2io
I
o
50
TEMHltATUfll!{"CI
T,"e"C
V,":!:15V
•
,
\
1111[1 I
111111 I
111111 I
V,-±~
:/
INPUT WIDEBAND NOISE
VS BANDWIDTH
'OO~~~
tOIHz TO FREQUENCY INDICATED)
'.0
L.OAD RESISTOR TO GItOUNO (Kn!
NOISE FIGURE VS
SOURCE RESISTANCE
-~
IIII
IIII
Rl"·410n,c.".OOI,!aF TOV-
fA "alec
",-:tlill
T.. "28·C
.,."tIIlY
I
'0 _ _ _
>
~Re..I5OICQ
3
1;--
~-,Ra·O
1
,.
III
100
FREQUENCY IHd
I
i'.OIlD_"'"
0.'10•."":::l..i-'..J....lJ.JJ.Il,.oI-..l-.l..L.J.J..U.Il,.-.J...J..J..L.l.JJJ!'oo
BANDWIDTKCKHZ}
Note: For further information refer to AN-15, "Minimization of Noise in Operational Amplifier Applications."
6-106
11111
NEGATI
-~
d'
TYPICAL INPUT NOISE
VOLTAGE
POSITIVE SWING
I
0
10
FlIEQUENCY (KHo!
.. ..
II I
II 1
..
1111
T.. _25·C
Vs·tlIV
,,
'00
OUTPUT POWER
11111111 11ll11l:
~Q
--
20
SSS12'I.SU'I'2ISC
1.0
85"0
SSS125E ID-C TO TO"C)
PSRR VS FREQUENCY
(SSS725, SSS725B, SSS725EI
~n5Aasam:~2K
7. »,
,
J-r(!)SSS72'C
TEMPERATUREI"Cl
CMRR VS FREQUENCY
~+
lIo:t1l1l
I 1~-~~
sss~
===
,"11,...
SSSr~
1000
INPUT BIAS CURRENT
VS TEMPERATURE
US72I1"
~
I
o
TEMPERATURE i"C)
_j,IIS7t5C
~5OI(n,
-,....
~ i-
SSS72!iE
.0
Uil LI! I II
t;; .....
RP"jolCni
I
V,Oj"V
"s.tIIlY
RPorcn
Sr72~
-,
,/
ft.J..-
,
I
~'\'".
I~
I
~,
'0",
~I
III~~IOOHI
111111
1.0
10
SOUIICE illUISTANCE1ICQI
,
.. '
•
555726
TYPICAL PERFORMANCE CURVES
OPEN LOOP GAIN VS
TEMPERATURE
MAXIMUM UNDISTORTED
OUTPUT
OPEN LOOP GAIN VS POWER
SUPPL V VOLTAGE
"'r-~..,.,.--,.,.....-~,.....,-....,..-......,.,
'0' _ _
GAIN.'
GAIN
GAINatoO GAIN'I,OOO GA/N-IO,OO
24+-H I++-+-HIH--+-IH-1H-1 11-++--1
~--'---t--+-+-t-t-t--t--j
t-
i"+-~-+HI"\+++I+-'\+4+~\V-H+nl\1-+!H
}'+-~++++-~++H-\-+~-4\~I-fj-~-++H
,o'±-0...LJ._,,~..L...''''0:-'-,.j..,.-.J-'''20....l'''''',,'',...1
IO:ao!:-..L...-+:-....I.~0-'-4*0,.-.J-.,OOi:-..L...-l..'"'O...l
TEMPERATURE
!-C)
O,~o-L~,*oo~~~~~,:-~.~~,o~~~-L-~,.
POWER SUPPLY VOLTAGE (VOL T5)
FR(OUENCY IHzl
INPUT BIAS CURRENT
DIFFERENTIAL
INPUT VOLTAGE
OUTPUT SHORT-CIRCUIT
CURRENT
POWER CONSUMPTION VS
SUPPLY VOLTAGE
vii
••
;c40
g
I•
~30
0
"- I'.
t, .......
;--
~
J
§20
,I
10
20
30
40
50
TOTAL SUPPLY VO\..TAGE,V+TO V·,tVOLTS)
I
I
I
I
'-~...,.....2-.J........:.....~--I
,,+0-.J.........
80
TIME FROM OUTPUT BEING SHORTED IMINUTES)
-
·30
-20
-10
0
10
2Q
DIFFERENTiAL INPUT VOLTAGE
30
~
GUARANTEED PERFORMANCE CURVES
r- H-tI--
j
SSS1Z,...
-""CTOI2,·C
V1".t'5V-!-
I1
IIIIII
ie
I
~
I','
i
!l
, II
II IIIII
Y UNTRIMMEO-""C TO'Z!I·C
Iz ~N~R:~MEJ 25"C
1111111
,~
II··,
Y UNTRIMMEO-M"e TO Ia-C
r-- Z
II
UNl RIMMED 2'·C
lill _
L.Hti
IIIIIIII
W TRIMMED-55"C TO t2¥C
!
WTRIMMED- !I-cTOI25"C
... ..,
IIIIIII
i ,..
e'
a
V~~-t
SSSrZ!! ,
-WCTOI25"C
I--
!
IIIIIIII
,
-I illll!!!
II
..
.~
SOURCE Jll(SI8TAN~EI R, nUll
II
~
SOUIICE RESISTANCE, R! (KOJ
1==1
>
~
i
S8S72&C-
Ys-'i:ISV:-rt
O"C TO 10-<:
:11
~--lY UNTRlM~~b O"C TO 10"C III
, ,,,,
,
"."
Z UNTRIMMEO~"C
...
~
I
i1"'l~~li~!~lf~'11
IIIIIIIII
r
W TRIMMEO
o-c TO 7O"C
'''~•.-,..........u.I.II,.~o-'......u.J.I.II!,,~............~
$QU1tee: MIIITANCl. RI (KO)
6·107
These graphs depict maximum error
referred to the input as a function of
source resistance (R1). Curves Ware
shown with Vos trimmed at +25°C
and include errors due to Vos and los
over the indicated temperature range.
Curves Y and Z plot maximum errors
with Vos not trimmed.
PMI
Isss 7411
®
COMPENSATED OPERATIONAL AMPLIFIER
GENERAL DESCRIPTION
FEATURES
The SSS'741 Series of Internally Compensated Operational
Amplifiers provides significant performance improvement while
retaining full pin-for-pin interchangeability with industrystandard general-purpose types. Improved offset voltage, bias
current, bandwidth and noise performance enable immediate
system performance upgrading without redesign and eliminate
costly special selections. Precision Monolithics' exclusive
Silicon-Nitride "Triple Passivation" process eliminates "popcorn 'noise" and provides maximum reliability imd long term
stability of parameters for lowest overall system operating
. cost. The SSS741 Series is ideal for use in summing amplifiers,
integrators, active filters and in other circuits where improved
dynamic performance and accuracy are required. SSS741's
with processing per the requirements of MIL 38510/883 are
available. For dual versions, see the SSS747 Series data sheet.
For very high performance general purpose operational amplifiers, refer to the OP-02 Series data sheet.
•
Improved DC Specifications
•
Low Input Bias Current . . . . . . . . . . . . 50 nA Max
•
High Large Signal Voltage Gain ... Up to 100 kVIV
•
Internal Frequency Compensation
•
Large Common Mode Voltage Range . . . . . . . ±12V
•
Low Power Consumption ..... _ .... 85 mW Max
•
Continuous Short Circuit Protection
•
MIL-STD-883A Processing Available
•
Silicon-Nitride Passivation
PIN CONNECTIONS AND ORDERING INFORMATION
SCHEMA TIC DIAGRAM
8
TOP VIEW
B A L A N C E 9 7v+
I NVERTI NO
INPUT 2 ,
3
NON-:~~~TINO
,
8 OUTPUT
5 BALANCE
TO-99 (J-Suffix)
ORDER: SSS741J
SSS741GJ
SSS741BJ
SSS741CJ
4 V- (ca••)
14
13
BALANCE 3
INV. INPUT 4
NON-I NY, 5
INPUT
Y- 6
14 PIN DIP (Y-Suffix)
ORDER: SSS741Y
SSS741GY
11 V+
SSS741BY
10 OUTPUT
SSS741CY
12
9 BALANCE
Military Temperature Range Devices
With MI L-STD-883A Class B Processing:
ClRCI.ED NUMBERS COMESPOMO
TO TO-99 PIN CONFIGURATION
ORDER: SSS741-883-J
SSS741-883-Y
6-108
SS5741-883-GJ
SSS741-883-GY
•
888741
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
SSS74l,SSS741B,SSS741G
±22V
±18V
SSS741C
Internal Power Dissipation (Note 1)
500mW
Differential Input Voltage
Input Voltage
Output Short Circuit Duration
NOTES:
Note 1: Maximum package power dissipation vs. ambient
temperature
±30V
Supply Voltage
Indefinite
Storage Temperature Range
MAXIMUM AMBIENT
DERATE ABOVE
TEMPERATURE
MAXIMUM AMBIENT
FOR RATING
TEMPERATURE
PACKAGE TVPE
-65°C to +150°C
Operating Temperature Range
SSS74l,SSS741G
SSS741B
SSS741C
-55°C to +125°C
-25°C to +85°C
DoC to +70°C
TO-99 (J)
DUAL-IN-LINE (V)
BO°C
100°C
7.1mWtC
10.0mWtC
Lead Temperature Range (Soldering, 60 sec)
ELECTRICAL CHARACTERISTICS
SSS741
±5V ~ Vs ~ ±20V
±5V ~ Vs ~ ±15V
unless otherwise noted unless otherwise noted
These specifications apply for T A = 25°C
Parameter
SSS741G
Symbol
Test Conditions
Min
Max
Min
Max
Units
Input Offset Voltage
VOS
RS$50kn
-
3.0
-
3.0
mV
Input Offset Current
lOS
-
25
-
25
nA
IB
-
100
-
100
nA
1.0
-
1.0
-
Mn
25,000
-
25,000
-
V/V
Input Bias Current
Input Resistance
RIN
Large Signal
Voltage Gain
AVO
RL 2:2kn Vs = ±15V
VO= ±10V
Output Voltage Swing
VOM
Vs = ±15V RL 2: 10kn
RL 2: 2kn
±12
±10
-
±12
±10
-
V
V
Input Voltage Range
CMVR
Vs = ±15V
±12
-
±12
-
V
Common Mode Rejection Ratio
CMRR
RS $50kn
70
-
70
-
dB
Power Supply Rejection Ratio
PSRR
RS $50kn
-
150
-
150
IlV/V
PD
Vs = ±15V
-
85
-
85
mW
Power Consumption
±5V ~ Vs ~ ±20V
±5V ~ Vs ~ ±15V
unless otherwise noted unless otherwise noted
The following specifications apply for
-55°C ~ TA ~ +125°C
Input Offset Voltage
Input Offset Current
Input Bias Current
-
3.0
-
6.0
mV
lOS
-
10
-
50
nA
IB
-
100
-
200
nA
50,000
-
25,000
-
V/V
VOS
RS$50kn
Large Signal
Voltage Gain
AVO
RL 2: 2kn
Vs = ±15V
VO=±10V
Output Voltage Swing
VOM
RL 2: 10kn
RL 2: 2kn
Vs = ±15V
±12
±10
-
±12
±10
-
V
V
Common Mode Rejection' Ratio
CMRR
RS $50kn
BO
-
70
-
dB
Po_r Supply Rejection Ratio
PSRR
RS5 50kn
-
100
-
150
IlV/V
6-109
555741.
BALANCING
CIRCUIT
V-Package
J-Package
4
2
"'~--6
~--10
3
9
I
y-
ELECTRICAL CHARACTERISTICS
These specifications apply for T A : 25°C
Parameter
SSS7418
SSS741C
±5V ~ Vs ~ ±20V
unless otherwise
specified
Vs : ±15V
Symbol
Test Conditions
Min
Max
Min
Max
Units
Input Offset Voltage
Vas
RS ~50k!l.
-
3.0
-
6.0
mV
Input Offset Current
lOS
-
5.0
-
25
nA
IB
-
50
-
100
nA
Input Resistance
RIN
2.0
-
1.0
-
M!l.
Large Signal
Voltage Gain
Ava
RL 2: 2k!l. Vs = ±15V
Va = ±10V
50,000
-
25.,000
-
V/v
Output Voltage Swing
YOM
Vs = ±15V RL
RL 2: 2k!l.
±12
±10
-
±12
±10
-
-
-
V
V
Input Bias Current
2: 10k!l.
Input Voltage Range
CMVR
VS=±15V
±12
-
±12
-
V
Common Mode Rejection Ratio
CMRR
RS:S 50k!l.
80
-
70
-
dB
Power Supply Rejection Ratio
PSRR
RS:S 50k!l.
-
100
-
150
IlV/V
VS=±15V
-
85
-
85
mW
Power Consumption
Po
±5V ~ Vs ~ ±20V
unless otherwise
The following specifications apply for
-25°C ~ T A S +85°C - 555741 B
-
4.0
-
7.5
mV
lOS
-
10
-
50
nA
IB
-
100
-
200
nA
25,000
-
15,000
-
V/V
±12
±10
-
±12
±10
-
-
-
V
V
Input Offset Voltage
Vas
Input Offset Current
Input Bias Current
Vs : ±15V
specified
O°CSTA S+70°C-555741C
Large Signal
Voltage Gain
Ava
Output Voltage Swing
YOM
RS:S 50kn
RL 2: 2kn
Vs = ±15V
Va = ±10V
Vs = ±15V RL
RL 2: 2kn
2: 10kn
Common Mode Rejection Ratio
CMRR
RS:S 50kn
80
-
-
-
dB
Power Supply Rejection Ratio
PSRR
RS:S 50k!l.
-
100
-
-
IlVN
6-110
Isss7471
PMI
DUAL COMPENSATED OPERATIONAL AMPLIFIER
GENERAL DESCRIPTION
FEATURES
The 555747 Series of Internally Compensated Dual Operational
Amplifiers provides significant performance improvements
while retaining full pin-for-pin interchangeability with industry-,
standard Ql!neral-purpose types_ Improved offset voltages, bias
current, bandwidth and noise performance enable immediate
system performance upgrading without redesign and eliminate
costly special selections. Precision Monolithics' exclusive
Silicon-Nitride "Triple Passivation" process eliminates "popcorn noise" and provides maximum reliability and long term
stability of parameters for lowest overall system operating
cost. The SSS747 is ideal for use in summing amplifiers,
integrators, active filters and in other circuits where improved
performance and accuracy are required. For very high performance dual operational amplifiers with the same pinout as
SSS747, see the OP-04 data sheet.
SCHEMATIC DIAGRAM
•
Improved D.C. Specifications
•
Low Input Bias Current
•
High Large Signal Voltage Gain
•
Jnternal Frequency Compensation
•
Large Common Mode Voltage Range
•
Low Power Consumption
•
Continuous Short Circuit Protection
•
MI L-STD-883A Processing Available
•
Silicon-Nitride Passivation
PIN CONNECTIONS AND ORDERING INFORMATION
TOP VIEW
(1/2 OF CIRCUIT SHOWN)
TO-IOO (K-Suffix)
ORDER: SSS747K
SSS747GK
SSS747BK
SSS747CK
INv.:lfIIII"UTI"')'
NON-IN\!! INPUT IAI2
B"LANCE tAl'
\'-4
'ALANCE ,1,15
N1)M-INV.IN.UT'la
'NV.INPUT'I,7
~
_
.4 bLANCE IAI
II
v+ IAI
IlounUT tA,
"M.L
IOOUT~T
'I'
IV+ 'I'
• IALANCE ,I,
INV"N"UT'A"m '4
MON-IHV.IIiIPUT CA'I
tAL"MCEIAIl
\'-4
BAlANCE'., I
1it01il-1NV.INPUT'I).
IfiIIV.INPUT CI)1
•
15V+Io\'
'''UINcr'A'
-
14 PIN DIP (Y-Suffix)
ORDER: SSS747Y
SSS747GY
SSS747BY
SSS747CY
IZOUTNTIA'
II N.C.
looun'UTCI'
• V+'I'
14 LEAD
FLATPACK (M-Suffix)
ORDER: SSS747M
SSS747GM
SSS747BM
• I"LA ..c:r ,I,
Military Temperature Range Devices
With MI L-STD-8B3A Class B Processing:
*
ORDER: SSS747-883-K
SS5747-883-Y
SSS747-883-M
DIP AND FLATPACK ONLY
6-111
SSS747-883-GK
SSS747-883-GY
SSS747-883-GM
555747
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
±22V
Internal Power Dissipation (Note 1)
Differential Input Voltage
Input Voltage
NOTES:
500mW
±30V
Note 1: Maximum package power dissipation vs. amb·
ient temperature.
Supply Voltage
MAXIMUM AMBIENT
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
TEMPERATURE
FOR RATING
PACKAGE TVPE
Indefinite
Output Short Circuit Duration
~5°C to 150°C
Storage Temperature Range
Operati·ng Temperature Range
SSS747 , SSS747G1
SSS7478
SSS747C
-55°C to +125°C
-25°C to +85°C
O°C to +70°C
Lead Temperature Range (Soldering, 60 sec)
10.0mWiC
7.1mWrC
5.7mWrC
DUAL·IN·LINE (V)
100°C
TO·l00 (K)
80°C
14·LEAD FLATPACK 1M) 62°C
300°C
I
ELECTRICAL CHARACTERISTICS (Each Amplifier)
SSS747
±5V 5 Vs 5 ±20V
±5V 5 Vs 5 ±15V
unless otherwise noted unless otherwise noted
These specifications apply for TA = 25°C.
Parameter
Input Offset Voltage
Input Offset Current
SSS747G
Symbol
Test Conditions
Min
Max
Min
Max
Units
VOS
RS :S 50kn
-
2.0
-
5.0
mV
5.0
-
25
nA
100
nA
lOS
-
'B
-
50
-
I nput Resistance
R'N
2.0
-
1.0
-
M!l
Large Signal
Voltage Gain
AVO
RL 2: 2kn VS: ±15V
VO: ±10V
100,000
-
50,000
-
V/V
Output Voltage Swing
YOM
VS: ±15V RL
RL 2: 2kn
±12
±10
-
±12
±10
-
V
V
±12
-
±12
-
V
1nput Bias Current
2: 10k!l
Input Voltage Range
CMVR
VS: ±15V
Common Mode Rejection Ratio
CMRR
RS :S 50kn
80
-
70
-
dB
Power Supply Rejection Ratio
PSRR
RS:S 50k!l
-
100
-
150
;.tV/V
Power Consumption
Po
VS: ±15V
-
85
-
85
mW
Channel Separation
CS
100
-
80
-
dB
The following specifications apply for -55°C 5 T AS +125°C.
Input Offset Voltage
Input Offset Current
Input Bias Current
-
3.0
-
lOS
-
10
-
'B
-
100
-
50,000
-
25,000
-
V/V
±12
±10
-
±12
.10
-
V
V
VOS
RS:S 50k!l
Voltage Gain
AVO
RL 2: 2kn
VS: ±15V
VO: ±10V
Output Voltage Swing
YOM
RL 2: 10kf!
RL 2: 2k!l
VS: ±15V
Large Signal
±5V 5 Vs 5 ±15V
±5V 5 Vs 5 ±20V
unless otherwise noted unless otherwise noted
6.0
mV
50
nA
200 ,
nA
Common Mode Rejection Ratio
CMRR
RS:S 50k!l
80
-
70
-
dB
Power Supply Rejection Ratio
PSRR
RS:S 50k!l
-
100
-
150
;.tV/V
6·112
SSS747
BALANCING CIRCUIT
6
2
_---10
~--12
7
OIPANO
FLATPACK
ONl.Y
ELECTRICAL CHARACTERISTICS (Each Amplifier)
These specifications apply for T A = 25°C.
SSS747B
SSS747C
±5V ~ Vs ~ ±20V
unless otherwise
specified
±5V~Vs~±15V
unless otherwise
specified
Symbol
Test Conditions
Min
Max
Min
Max
Units
I nput Offset Voltage
VOS
RS:5 50kf!
-
3.0
-
5.0
mV
Input Offset Current
lOS
-
5.0
-
25
nA
IB
-
50
-
100
nA
Input Resistance
RIN
2.0
-
1.0
-
Mf!
Large Signal
Voltage Gain
AVO
RL? 2kf! Vs
Vo = ±10V
50,000
-
50,000
-
V/V
Output Voltage Swing
VOM
Vs =±:15V RL? 10kf!
RL? 2kf!
±12
±10
-
±12
±10
-
V
V
±12
-
±12
-
V
Parameter
Input Bias Current
= ±15V
= ±15V
Input Voltage Range
CMVR
Vs
Common Mode Rejection Ratio
CMRR
RS:5 5.0kf!
SO
-
70
-
dB
Power Supply Rejection Ratio
PSRR
RS:5 50kf!
-
100
-
150
/,V/v
= ±15V
-
S5
-
S5
mW
100
-
SO
-
dS
Power Consumption
Po
Channel Separation
CS
Vs
The following specifications apply for
-25°C ~ T A ~ +85°C - SSS7478 and
±5V ~ Vs ~ ±20V
unless otherwise
±5V~ Vs ~±15V
specified
specified
O°C ~ T A ~ +70°C - SSS747C.
-
4.0
-
6.0
mV
lOS
-
10
-
50
nA
IS
-
100
-
200
nA
Input Offset Voltage
vos
Input Offset Current
Input Bias. Current
unless otherwise
RS
'5. 50kf!
Large Signal
Voltage Gain
AVO
RL 2: 2kf!
Vs =±15V
Vo = ±10V
25,000
-
25,000
-
V/V
Output Voltage Swing
VOM
Vs = ±15V RL? 10kf!
RL 2: 2kf!
±12
±10
-
±12
±10
-
V
V
Common Mode Rejection Ratio
CMRR
RS:5 50kf!
SO
-
70
-
dB
Power Supply Rejection Ratio
PSRR
RS:5 50kf!
-
100
-
150
/,V/v
6-113
PMI
ISSS1458/15501
DUAL COMPENSATED OPERATIONAL AMPLIFIER
GENERAL DESCRIPTION
FEATURES
The SSS1458/1558 5eries of Internally Compensated Dual
Operational Amplifiers provides significant performance improvements while retaining full pin-for-pin interchangeability
with industry-standard types. Improved offset voltages, bias
current, bandwidth and noise performance enable immediate
system performance upgrading without redesign and elimi,nate
costly special selections_ Precision Monolithics' exclusive
Silicon-Nitride "Triple Passivation" process eliminates "popcorn noise" and provides maximum reliability and long term
stability of parameters for lowest overall system operating
cost. The 55S1458/1558 is ideal for use in summing amplifiers,
integrators, active filters and in other circuits where improved
performance and accuracy are required. For very high performance dual operational amplifiers with the same pinout as
SS51458/1558, see the OP-14 data sheet_
SCHEMATIC DIAGRAM
_
Improved D.C. Specifications
_
Low Input Bias Current . . . . . . . . . . . . . <100nA
•
High Large Signal Voltage Gain . . . . . . . . >50,000
-
Internal Frequency Compensation
•
Large Common Mode Voltage Range ..... >±12V
•
Low Power Consumption . . . . . . . . . . .. <85mW
•
Continuous Short Circuit Protection
_
MIL-STD-883A Processing Available
_
Silicon-Nitride Passivation . . . . . . . . . . Low Noise
PIN CONNECTIONS AND ORDERING INFORMATION
(1/2 OF CIRCUIT SHOWN)
TOP VIEW
INVERTIN.
INVERTI,..
INPUT(") 2
• INPUT (8)
4V-
TO-99 (J-Suffixl
ORDER: SSS1558J
SSS1458J
6-114
•
SSS1458/1558
ABSOLUTE MAXIMUM RATINGS
Lead Temperature Range (Soldering, 60 sec)
Operating Temperature Range
_55°C to +125°C
5551558
-' O°C to +70°C
5551458
±22V
500mW
±30V
Supply Voltage
Indefinite
_65°C to +150°C
Sl,ipply Voltage
Internal Power Dissipation (Note)
Differential Input Voltage
Input Voltage
Output Short Circuit Duration
Storage Temperature Range
NOTE: Derate at 7.1 mW f C above 80° C.
ELECTRICAL CHARACTERISTICS (Each Amplifier)
SSS1558
SSS1458
These specifications apply for T A = 25°C and ±5V ... Vs'" ±15V, unless otherwise noted.
Symbol
Test Conditions
Min
Max
Min
Max
Units
Input Offset Voltage
Vas
RS $ 50kf!
-
5.0
-
5.0
mV
Input Offset Current
lOS
-
25
-
26
nA
IB
-
100
-
100
nA
Input Resistance
RIN
1.0
-
LO
-
Mf!
Large Signal
Voltage Gain
Ava
Rl ~ 2kf! Vs = ±15V
VO=±10V
50,000
-
50,000
-
VN
Output Voltage Swing
VOM
Vs = .15V RL
Rl > 2kf!
±12
±10
-
±12
±10
-
-
V
V
Input Voltage Range
CMVR
Vs = ±15V
±12
-
±12
-
V
Common Mode Rejection Ratio
CMRR
RS $ 50kf!
70
-
70
-
dB
Power Supply Rejection Ratio
PSRR
RS $ 50kf!
-
150
-
150
INN
Power Consumption
Po
Vs = ±15V
-
85
-
85
mW
Channel Separation
cs
80
-
80
-
dB
-
6.0
mV
50
nA
200
nA
Parameter
Input Bias Current
~
10kn
The following specifications apply for ±5V'" Vs'" ±15V, -55°C ... TA ... +125°C for 5S51558, and
O°C ... T A'" +70°C for S551458 unless otherwise noted.
-
6.0
lOS
-
50
IB
-
200
-
Input Offset Voltage
Vas
Input Offset Current
Input Bias Current
RS 'S. 50kn
large Signal
Voltage Gain
Ava
RL::: 2kn
Vs = ±15V
Va =±10V
25,000
-
25,000
-
VIV
Output Voltage Swing
VOM
VS=±15V R.L::: 10kn
Rl::: 2kf!
.12
±10
-
.12
.10
-
V
V
Common Mode Rejection Ratio
CMRR
RS:S 50kf!
70
-
70
-
dB
Power Supply Rejection Ratio
PSRR
RS:S 50kf!
-
150
-
150
p.VN
6-115
IPM108AI
®
LOW INPUT CURRENT OPERATIONAL AMPLIFIER
PM108A / PM208A / PM308A / PM108 / PM208 / PM308
GENERAL DESCRIPTION
FEATURES
The PM108A Series of precision monolithic operational
amplifiers 'features extremely low input offset and bias
currents. Although directly interchangeable with industrystandard types, Precision Monolithics' advanced processing
technique provides a significant improvement in input noise
voltage. Low supply current drain over a wide power supply
range makes the PM108A attractive in battery operated and
other low power applications. Low offset current. and low
bias current provide excellent performance in high impedance
circuits such as long period integrators, sample-and-holds,
and with piezoelectric and capacitive transducers.
SIMPLI FI ED SCHEMATIC
_
_
_
_
_
_
_
Low Offset Current ........ _ ..... 200pA Max
Low Bias Current _ .•.. _ .. _ . . . . .• 2.0nA Max
Low Power Consumption. _ .•. 18mW Max @±15V
Low Offset Voltage Drift . _ ...... 5.0j.LVt C Max
High Common Mode Input Range .... ±13.5V Min
MI L-STD-883A Class B Processing Models Available
Silicon-Nitride Passivation
COMPENSATION CIRCUITS
ALTERNATE
R,
OUTPtIT
R,
N,
C3~RI+R2
c.
CS·IOOpF
(Improves rejection of power supply
noise bv a factor of ten)
STANDARD
R,
R.
PIN CONNECTIONS AND ORDERING INFORMATION
TOP VIEW
;¢~~
NON-'NVERT'N~
INPUT
4 Y-
TO-99 (J-Suffix)
ORDER: PM108AJ/PM108J
PM20BAJ/PM208J
PM308AJ/PM308J
Ic~d"
Military Temperature Range Devices
With MIL-STD-883A Class B Processing
ORDER: PM108-883-AJ
PM 108-883-J
6-116
I
PM108
ABSOLUTE MAXIMUM RATINGS
po~er
dissipation vs. ambient
Maximum
Ambient
Temperature
for Rating
Derate Above
Maximum
Ambient
Temperature
NOTE 1: Maximum package
temperature:
Package Type
TO-99 (J)
80°C
7_1 mWfC
NOTE 2: The inputs are shunted with back-to-back diodes
for overvoltage protection. Therefore, excessive current
will flow if a differential input voltage in excess of 1V is
applied between the inputs unless some limiting resistance
is provided.
NOTE 3: For supply voltages less than ±15V, the absolute
maximum input voltage is equal to the supply voltage.
ELECTRICAL CHARACTERISTICS
PM308A
PM308
These specifications apply for±5V ";;V S ";;±15V and TA = 25°C unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
.Min
Typ
Max
Units
Input Offset Voltage
Vos
-
0.3
0.5
-
2.0
7.5
mV
I nput Offset CUrrent
'os
-
0.2
1.0
-
0.2
1.0
nA
Input Bias Current
IB
-
1.5
7.0
-
1.5
7.0
nA
Input Resistance
R in
10
40
-
10
40
-
Mil
Large Signal Voltage Gain
Avo
SO
:DO
-
25
:DO
-
V/mV
Supply Current
Is
O.S
-
0.3
O.S
mA
'Vs=±15V, Vout=±10V
R L ;;'10kil
lout= 0, Vout = 0
-
0.3
The following specifications apply for ±5V";;V s ";;±15V and OOC";;TA ";;+70oC unless otherwise noted.
Input Offset Voltage
Vos
-
0.4
0.73
-
3.0
10.0
mV
Average Input Offset
Voltage Drift
TCVos
-
1.0
5.0
.,.
6.0
:D
/Ntc
Input Offset Current
los
-
0.3
1.5
-
0.3
Average I nput Offset
Current Drift
TClos
-
2.0
10
-
2.0
10
pAtC
Input Bias Current
IB
-
2.0
10
-
2.0
10
nA
Large Signal Voltage Gai n
Avo
Vs=±15V, Vout =±10V,
RL ;;'10kil
60
200
-
15
100
-
V/mV
Output Voltage Swing
YoM
Vs =±15V, RL - 10kil
±13
±14
-
±13
±14
-
V
Input Voltage Range
CMVR
Vs =±15V
±14
-
-
±14
-
-
V
Common Mode Rejection Ratio
CMRR
96
110
-
SO
100
-
dB
Supply Voltage Rejection Ratio
PSRR
96
110
-
SO
96
-
dS
Su pply Current
Is
-
-
-
rnA
Vout = 0, TA = MAX
6-117
-
0.23
0.23
1.5
nA
PM108
ABSOLUTE MAXrMUMRATINGS
Supply Voltage
Operating Temperature Range
PM108A, 108, 208A, 208
±20V
PM108A. PM108
PM308A,308
±18V
PM208A, PM208
Internal Power Dissipation (Note 1)
Differential Input Current (Note 2)
Input Voltage (Note 3)
Output Short Circuit Duration
500mW
to +125°C
to +8SoC
O°C to +70°C
-65°C to +150°C
-55°C
-25°C
PM308A, PM308
Storage Temperature Range
Lead Temperature Range
(Soldering, 60 sec)
±10mA
±15V
Indefinite
ELECTRICAL CHARACTERISTICS
300°C
PM108A
PM108
PM208A
PM208
I
These specifications apply for ± 5V .;;; V s .;;; ± 20V and T A = 25°C unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Min
Typ
Max
Units
Input Offset Voltage
Vos
-
0.3
0.5
-
0.7
2.0
mV
Input Offset Current
los
-
0.05
0.2
-
0.05
0.2
nA
Input Bias Current
IB
-
0.8
2.0
-
O.B
2.0
nA
Input Resistanco
R in
30
70
-
30
70
-
M,Q
Large Signal Voltage Gain
Avo
V s=±15V, V out= ±10V,
R L ;;'10k,Q
BO
300
-
50
300
-
V/mV
Supply Current
Is
laut= 0, V out = 0
0.6
-
-
0.3
0.3
0.6
mA
The following specifications apply for ±5V"VS.. ±20V, _55°C .. TA .. +125°C for PM10B and PM108A, _25°C .. T A "+B5°C for
PM20B and PM208A, unless otharwise noted.
Input Offset Voltage
Vos
-
0.4
1.0
-
1.0
Average Input Offset
Voltage Drift
TCVos
-
1.0
5.0
-
3.0
Input Offset Current
los
-
0.1
0.4
-
0.1
0.4
nA
Average I nput Offset
Current Drift
TClos
-
0.5
2.5
-
0.5
2.5
pAtC
Input Bia. Current
IB
-
1.0
3.0
-
1.0
3.0
nA
Large Signal Voltage Gain
Avo
V s=±15V, V out= ±10V
R L ;;'1Ok,Q
40
200
-
25
200
-
V/mV
Output Voltage Swing
YoM
V s=±15V, RL = 10k,Q
±13
±14
-
±13
±14
-
V
Input Voltage Range
CMVR
V =±15V
±13.5
-
-
±13.5
-
-
V
Common Mode Rejection Ratio
CMRR
96
110
-
85
100
-
dB
Supply Voltage Rejection Ratio
PSRR
96
·110
-
80
96
-
dB
Supply Current
Is
0.4
-
0.4
rnA
•
V out = 0, TA = MAX
6-11B
-
0.15
0.15
3.0
15
mV
/lvtc
PMI
IPM155AI
MONOLITHIC JFET INPUT OPERATIONAL AMPLIFIER
PM155A/PM355A/PM155/PM255/PM355
LOW SUPPLY CURRENT
GENERAL DESCRIPTION
The PM155 ~ries provides low input current, high slew
rate, and direct interchangeability with LF155 types. These
operational amplifiers use a new process which allows
fabrication of matched JFET transistors and standard bipolar transistors on the same chip. A JFET-input design
enables operation with ±40V input voltages eliminating the
blowout problems associated with MOSFET devices.
High accuracy, low supply current, and low cost make the
PM155 Series useful in new designs and as replacements for
modular and hybrid types. Unlike many designs, nulling the
input offset voltage does not degrade common mode
rejection ratio or input offset voltage drift. Dynamic specifications include a slew rate of 5V Illsec, a 2.5MHz gain
bandwidth product, and settling time to within ±O.Ol% of
final value of 4.0IlseC. In addition, ·Iow input voltage noise
and current noise plus a low 1If noise corner frequency
allow this amplifier to be used in a variety of low noise,
low power applications.
FEATURES
_
LF155 Series Direct Replacements
_
Low Input Bias and. Offset Currents
_
Low Supply Current . . . . . . . . . . . . . . . . 2mA
_
Fast Settling to ±O.Ol% ........•.•.. 4.01lsec
_Internal Compensation
_
Low Input Offset Voltage . . . . . . . . . . . 1.0mV
_
Low Input Offset Voltage Drift ....... 3.01lVfc
_
Low Input Noise Current . . . . . . . . . O.OlpAy'Hi
_
High Common Mode Rejection Ratio ..... 100dS
_
High Open Loop Gain .. . . . . . . . . . . . .. 106dS
_
Models With MIL-STD-883A Class S
_
Processing Available From Stock
Applications include instrumentation amplifiers, integrators, log amps, photocell amplifiers, and notch filters. For
other JFET operational amplifiers, see the PMI56A and
PM 157 A data sheets
SIMPLIFIED SCHEMATIC DIAGRAM
PIN CONNECTIONS
N.C.
TOP VIEW
8
4.V-(CASE)
TO-99 IJ-Suffix)
ORDERING INFORMATION
ORDER: PM155AJ
PM155J
PM255J
PM355AJ
PM355J
Military Temperature Range Devices
With MI L-STD-883A Cia •• 8 Processing
ORDER: PM155-883-AJ
PM155-883-J
6-119
PM155
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
PM155A, PM155, PM255, PM355A
PM355
Maximum Junction Temperature (Tj)
±22V
±18V
PM155A, PM155
PM255
PM355A, PM355
Differential Input Voltage
PM155A, PM155, PM255, PM355A
PM355
Input Voltage
PM155A, PM155, PM255, PM355A
PM355
(Unless otherwise specified the absolute
maximum negative input voltage IS equal
Internal Power Dissipation
PM155A, PM155
PM255
PM355A, PM355
670mW
570mW
500mW
(The TO-99(J) package must be derated
based on a thermal resistance of 150° e/W
junction to ambient or 45° e/W junction
to case,}
Operating Temperature Range
PM155A, PM155
PM255
PM355A, PM355
_55°C to +125°C
_25° C to +85° C
O°C to +70°C
+1500 C
+115°C
+1 00° C
±40V
±30V
±20V
±16V
to the negative power supply voltage.)
Output Short Circuit Duration
Indefinite
Storage Temperature Range
Lead Temperature Range (Soldering, 60 sec)
_65°C to +150°C
+300°C
I
ELECTRICAL CHARACTERISTICS
These specifications apply for ±15V <; V. <; ±20V, TA = +25°C
Parameter
Symbol
Test Cond itions
Min
Input Offset Current
los
Tj = 25°C INote 1)
-
Input Bias Current
18
Tj = 25°C (Note 1)
-
Input Offset Voltage
R s =50n
Vos
Vs = ±15V, Vo - ±10V,
RL =2Kn
50
Supply Current
Is
V s = +15V
-
Slew Rate
SR
AVCL = +1, Vs = ±15V
GBW
Vs = ±15V
Vs = ±15V (Note 2)
Input Noise Voltage
en
Input Noise Current
in
Input Capecitance
ein
R s-l00n, f-l00Hz, Vs~±15V
R s=l00n, f=1000Hz.v s=±15V
f -100Hz, Vs
f
~
~
Min
2.0
-
10
-
3.0
-
±15V
4.0
5.0
-
3.0
,-
-
-
-
-
0.01
3.0
10
pA
pA
n
200
V/mV
2.0
4.0
mA
5.0
-
V/p.sec
-
J,tsec
-
nVy'HZ
-
-
-
pA,jHZ
MHz
4.0
n~~'Hz
25
25
Units
mV
50
2.5
2.5
0.01
1000Hz, Vs - ±15V'
2.0
30
50
2.0
20
Max
1.0
10 10l
200
4.0
Typ
3.0
50
10 12
RIN
Avo
ts
Max
1.0
3.0
Large Signal Voltage Gain
Gain Bandwidth Product
Typ
30
Input Resistance
Settling Time to 0.01 %
PM355A
PM155A
unless otherwise noted.
20
0.01
0.01
3.0
pA,£Hz
pF
These specifications apply for ±15V .; V s " ±20V, -55°C" TA " +125°C and THIGH ~ +125°C for PM155A, O°C "T A'; +70°C and
THIGH = +70°C for PM355A, unless otherwise noted.
-
Input Offset Voltage
Vos
R,
2.5
-
2.3
mV
TCVos
Rs - 50n
-
-
Input Offset Voltage Drift
3.0
5.0
-
3.0
5.0
p.vl"c
Change in Input Offset Drift
with Vos Adjust
llTCVos
Rs~50n
-
0.5
-
-
0.5
-
p.V/oC
Input. Offset Current
los
Tj .; THIGH (Note 11
-
-
1.0
nA
IB
Tj "THIGH (Note 1)
25
5.0
nA
Large Signal Voltage Gain
Avo
V s=±15V,Vo -±10V, RL -2Kn
25
-
10
Input Bias Current
-
-
25
-
Output Voltage Swing
Vs = ±15V, RL = 10Kn
±12
±13
-
±12
±13
V
Vom
-
Vs - ±15V, RL = 2Kn
±10
±12
±10
±12
±11
+15.1
-12.0
+15.1
-12.0
~50n
llVos
permV
V/mV
V
Input Voltage Range
CMVR
Vs = ±15V
-
±11
-
V
Common Mode Rejection Ratio
CMRR
VCM = ±CMVR
85
100
-
85
100
-
dB
Power Supply Rejection Ratio
PSRR
(Note 3)
85
100
-
85
100
-
dB
NOTE 1: The input bias currents are junction leakage currents which approximately double for every 10°C increase in the junction temperature,
Tj. Due to limited production test time, the input bias currents measured are correlated to junction temperature. In normal operation
the junction temper'ature rises above the ambient temperature as a result of internal power disSipation, Pd. Tj
= T A + E)jA where
9jA
is the thermal resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum.
IB and los are measured at VCM = O.
NOTE 2: Settling time is defined here for a unity gain inverter connection using 2Kfl resistors. It is the time required for the error voltage (the
voltage at the inverting input pin on the amplifier) to settle to within 0.01% of its final value form the time a 10V step input is applied
to the inverter. See settling time test circuit on page 4.
NOTE 3: Power supply rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously. in accordance with
common practice.
6-120
PM155
ELECTRICAL CHARACTERISTICS
~
,.
These specifications applV for TA = +26°C, ±16V .. Vs" ±20V for PMl66
and PM266, Vs = ±16V for PM366; unless otherwise noted.
Parameter
Symbol
Test Conditions
PM155
PM255
Min
TVp
Input Offset Voltage
Vas
Rs =50n
-
3.0
Input Offset Current
los
Tj = 25°C (Note 11
-
3.0
Input Bias Current
IB
Tj = 25°C (Note 11
-
30
Input Resistance
RIN
-
10 12
Large Signal VO,ltage Gain
Ava
Vs = ;t15V, Va = ±10V,
RL=2Kn
50
200
PM355
Max
3.0
10
3.0
50
pA
100
-
30
200
pA
-
-
10 12
-
25
-
-
2.5
Is
4,0
AVCL = +1, Vs = ±15V
-
2.0
SR
5.0
-
~ain
Bandwidth Product
GBW
Vs=±15V
-
2.5
Settling Time to 0.01 %
to
Vs = ±15V (Note 21
-
4,0
Input Noise Voltage
en
Rs=loon,f=looHz,Vs=±15V
-
in
Input Capacitance
Cin
f = 1000Hz, Vs = ±15V
Units
-
~ate
Input Noise Current
Max
-
5.0
Slew
f = 100Hz, Vs = ±15V
TVp
~O
Supply Current
Rs=100n,f=10ooHz,V s=±15V
Min
mV
-
n
-
VlmV
2.0
4.0
mA
5.0
-
V//lsec
-
/lsec
200
-
25
-
20
-
-
0.01
-
-
0.01
0.01
-
0.01
3.0
-
-
-
3.0
-
4.0
25
20
,..
MHz
nV.jHi
nVy'Hz
pA.jHz
pAy'Hz
pF
These specifications apply for ±15V .. Vs" ±20V for PM155 and PM255, Vs = ±15V for PM355, -S5°C':; TA" +125°C for PM166,
-25°C .. TA .. +85°C for PM255, DoC':; TA .. +70°C for PM355, unless otherwise noted,
Rs = 50n, PM155
-
-
7.0
Input Offset Voltage
Vas
Rs = 50n, PM255
-
-
6.5
TCVos
Rs = 50n
-
-
Input Offset Voltage Drift
5,0
Change in Input Offset Drift
with Vas Adjust
--LIVas
Rs =500
-
0.5
-
PM155, Tj" +125°C
los
-
PM355. Tj .:; +70°C
-
20
Input-Offset Current
(Note 11
PM155, Tj .:; +125°C
-
Rs = 50n, PM355
L1TCVos
Input Bias Current
IB
(Note 11
Output Voltage Swing
Input Voltage Range
Ava
Vom
13
mV
-
5.0
-
/lVI"C
-
0.5
/lVI"C
permV
1.0
-
-
-
-
-
2.0
nA
-
50
-
-
nA
8.0
nA
-
V/mV
-
-
5.0
-
-
25
-
Vs = ±15V. RL = 10KO
±12
±13
-
15
-
±12
±13
Vs = ±15V, RL = 2Kn
±10
±12
-
±10
±12
PM255, Tj" +85°C
PM255, Tj .. +B5°C
PM355, Tj .. +70°C
Large Signal Voltage Gain
-
-
-
Vs=±15V. Vo=±10V,RL=2Kn
±11
+15.1
-
CMVR
Vs = ±15V
Common Mode Rejection Ratio
CMRR
VCM =±CMVR
85
100
-
Power Supply Rejection Ratio
PSRR
(Note 31
85
100
-
-12.0
-
mV
mV
nA
nA
nA
V
-12.0
-
80
100
-
dB
80
100
-
dB.
±10
+15.1
V
V
NOTE 1: The input bias currents are junction leakage currents whi~h approximately double for every 10°C increase.in the junction temperature,
Tj. Due to limited production test time, the input bias currents measured are correlated to junction temperature. In nor0181 operation
the junction temperature rises above the ambient temperature as a result of internal power diSSipation, Pd, Tj = TA + G)jA where G)jA
.is the thermal resistance from junction to ambient. Use of a heat sink is recommended if inp~t bias current is to be ke~t to a minimum.
IB and los are measured at VCM = O.
NOTE 2: Settling time is defined here for a unity gain inverter connection using 2Kn resistors. It is the time required for the error voltage (the
v"ltage at the inverting input pin on the amplifierl to settle to within 0.01% of its final value from the time a 10V step input is applied
to the inverter. See settling time test circuit on page 4.
NOTE 3: Power supply rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously, in accordance with
common practice.
6-121
PM1.§;i
BASIC CONNECTIONS
INPUT OFFSET VOLTAGE
SETTLING TIME
NULLING
TEST
CIRCUIT
2kHO.1%
+15V
v-
NOTE:
I
For potentiometers with a temperature
coefficient <;100ppm/'C, the added
TCVos with nulling is "'O.5I'V I' C/mV
of adjustment.
APPLICATION INFORMATION
DYNAMIC OPERATING CONSIDERATIONS
As with most amplifiers, care should be taken with lead dress, comw
ponent.. placement and supply decoupling in order to ensure
stability. For example, resistors from the output to an input should
be placed with,the body close to the input to minimize "pick-up"
and maximize the frequency of the feedback pole by minimizing
the capacitance from the input to ground.
INPUT VOLTAGE CONSIDERATIONS
The PM155 JFET input stage can accommodate large input differ-ential voltages without external clamping as long as neither input
exceeds the negative power supply. An input voltage which is more
negative than V- can result in a destroyed unit.
If both inputs exceed the negative common mode voltage limit, the
amplifier will I>
".
'v
10,000
.0'
.0'
.0'
270
~
<'w~
VOLTAGE OFFSET
NULL CIRCUIT
PM725
PM725C
RM725
ELECTRICAL CHARACTERISTICS
These specifications apply for V s = ± 15V, T A = 25° C, unless otherwise noted.
Parameter
Symbol
Test Conditions
Min
Typ
Max
Min
Typ
Max Units
Input Offset Voltage
(Without external trim)
Vos
0.5
1.0
0.5
2.5
mV
Input Offset Current
ios
2.0
20
2.0
35
nA
I nput Bias Current
IB
42
100
42
125 nA
Input Noise Voltage
en
Input Noise Current
in
Input Resistance
Rin
Input Voltage Range
CMVR
Large Signal Voltage Gain
Avo
RS .. l0kO
fo = 10 Hz
15
15
nV/.jHz
fo = 100 Hz
9.0
9.0
nV/.jHz
fo - 1 kHz
B.O
B.O
nV/.jHz
fa = 10 Hz
1.0
1.0
pA/.jHz
fo = 100 Hz
0.3
0.3
pA/.jH.
fo = 1 kHz
0.15
0.15
pA/.jHz
1.5
MO
1.5
±13.5
±14
±13.5
RL"2kO,VO~±10V 1,000,000 3,000,000
Common Mode Rejection Ratio
CMRR
RS .. 10kO
Power Supply Rejection Ratio
PSRR
RS .. 10 kO
Output Voltage Swing
Vom
110
V
250,000 3,000,000
94
120
2.0
±14
10
V/V
120
2.0
dB
35
p.V/v
RL,,10kO
±12
±13.5
±12
±13.5
V
RL" 2 kO
±10
±13.5
±10
±13.5
V
Output Resistance
Ro
150
Power Consumption
Pd
BO
150
SO
105
0
150 mW
The following specifications apply for Vs - ±15V, -55"C .. TA .. +125"C for PM725, O°C .. TA .. +7trC for PM725C, unless otherwise noted.
Input Offset Voltage
(Without external trim)
Vos
RS .. 10 kO
Average Input Offset Voltage Drift
(Without external trim)
TCVos
RS= 500
2.0
Average I nput Offset Voltege Drift
(With external trim)
TCVos n
RS = 500
0.6
TA = MAX
1.2
20
1.2
35
TA = MIN
7.5
40
4.0
50
35
150
10
Input Offset Current
los
Average Input Offset Current Drift
TClos
Input Bias Current
IB
Large Signal Voltage Gain
Ava
3.5
1.5
5.0
mV
p.V/"C
2.0
p.V/"C
0.6
nA
nA
pAfC
TA=MAX
20
100
125 nA
TA=MIN
BO
200
250 nA
RL " 2 kO, T A = MAX
1,000,000
125,000
RL" 2 kO, TA = MIN
250,000
125,000
100
Common Mode Rejection Ratio
CMRR
RS .. 10kO
Power Supply Rejection Ratio
PSRR
RS .. 10kO
Output Voltage Swing
Vom
RL" 2 kO
20
±10
6-132
±10
V/v
V/v
115
dB
20
p.V/v
V
I
IPM-741 I
PMI
COMPENSATED OPERATIONAL AMPLIFIER
GENERAL DESCRIPTION
FEATURES
The PM741 Series of Internally Compensated Operational
Amplifie~ provides industry-standard ·741 specifications. In
addition, Precision Monolithics' exclusive Silicon-Nitride
"Triple Passivation" process eliminates "popcorn noise" and
provides maximum reliability and long term stability of parameters for lowest overall system operating cost. For improved
specifications, see the SSS741 Series data sheet. For very high
performance general purpose op amps, refer to the OP-02
Series data sheet.
SCHEMATIC DIAGRAM
_
_
Industry Standard 741 Specifications
Internal Frequency Compensation
•
_
_
Continuous Short Circuit Protection
MIL-STD-883 Processing Avaihible
Silicon-Nitride Passivation
•
Low Noise
PI,,! CONNECTIONS AND ORDERING INFORMATION
8
TOP VIEW
B A L A N c e S 7v+
INVERTING
INPUT 2 .
TO-99 IJ-Suffixl
ORDER: PM741J
PM741CJ
6 OUTPUT
3
5 BALANCE
NON-:~~5~TING
4 V-
(cas.)
•
BALANCE 3
INV. INPUT 4
NON-INV.5
INPUT
v- 6
14
13
14 PIN DIP IY-Suffixl
ORDER: PM741Y
PM741CY
12
11 V+
10 OUTPUT
9 BALANCE
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
PM741
PM741C
±22V
±18V
Internal Power Dissipation (Note 1 )
500mW
Differential Input Voltage
±30V
Input Voltage
Supply Voltage
Output Short Circuit Duration
Storage Temperature Range
Indefinite
_65°C to +150°C
Lead Temperature Range (Soldering, 60 sec)
Operating Temperature Range
PM741
.
PM741C
-55°C to +125°C
O°C to +85°C
Note 1. Maximum package power dissipation vs ambient
temperature.
MAXIMUM AMBIENT
TEMPERATURE
PACKAGE TYPE
FOR RATING
BOoC
TO-991JI
lOOoC
DUAL-IN-LINE IYI
6-133
DERATE ABOVE
MAXIMUM AMBIENT
TEMPERATURE
7.1mW/oC
10.0mW/oC
PM741
ELECTRICAL CHARACTERISTICS
These specifications apply for T A = 25°C, Vs = ±15V,
'mless otherwise specified.
Parameter
Input Offset Voltage
Symbol
VOS
PM741C
PM741
Test Conditions
RS": 10kn
Min
-
Max
5.0
Min
-
Max
6.0
Units
rnV
lOS
-
200
-
Input Bias Current
18
-
500
-
500
nA
Input Resistance
RIN
0.3
-
0.3
-
Mn
Large Signal
Voltage Gain
AVO
50,000
-
-
V/V
2.8
rnA
Input Offset Current
Supply Current
RL;> 2kn
Vo = ±10V
-
IS
The following specifications apply for -55°C ~ TA ~ +125°C PM741 and O°C ~ T A ~ +85°C - PM741C.
RS": 10kn
2.8
-
Vs = ±15V
Vs = ±15V
-
6.0
Input Offset Voltage
VOS
Input Offset Current
lOS
-
Input Bias CLirrent
18
-
Large Signal
Voltage Gain
AVO
RL;>2kn
Vo = ±10V
25,000
-
Output Voltage Swing
VOM
RL ;> 10kn
RL;>2kn
±12
±10
500
-
7.5
300
mV
nA
0.8
IlA
15,000
-
V/V
-
±12
±10
-
V
V
±12
-
±12
-
V
-
70
-
dB
Input Voltage Range
CMVR
Common Mode Rejection Ratio
CMRR
RS.": 10kn
70
Power Supply Rejection Ratio
PSRR
RS'" 10kn
77
6-134
25,000
200
nA
1.5
-
77
dB
I
PMI
IPM-7471
DUAL COMPENSATED OPERATIONAL AMPLIFIER
GENERAL DESCRIPTION
FEATURES
The PM747 Series of Internally Compensated Dual Operational
Amplifiers provides industry-standard 747 specifications. In
addition, Precision Monolithics' exclusive Silicon-Nitride
"Triple Passivation" process eliminates "popcorn noise" and
provides maximum reliability and long term stability of parameters' for lowest overall system operating cost. For improved
specifications, see the SSS747 Series data sheet. For very high
performance dual op amps, refer to the OP-l0 Dual Matched
Instrumentation Operational Amplifier data sheet.
_
Dual PM 741 Internally Compensated Operational
Amplifier
•
•
_
Internal Frequency Compensation
Continuous Short Circuit Protection
MI L-STD-883 Processing Available
•
_
Silicon-Nitride Passivation
Low Noise
SCHEMATIC DIAGRAM
PIN CONNECTIONS AND
ORDERING INFORMATION
(1/2 OF CIRCUIT SHOWN)
TOP VIEW
OUT>UT~
I"
...... _ ( 0 1
v+,&, I
"'lOTI... ,
,..uTf.\)
.....~m ..
• 11+111
7 INVEIn',...
IfillUTCI)
_Ii
'v-
•::~TW"'-
INltINfOUTIAIIC-
!NOJiI-INV.I~UT (All
12 OUTPUT ''''
U,LAt«:E
K)QUTf'IIT\ll
,.,e
INY.INPUT'I)7
*
II N.C.
14 PIN DIP (V-Suffix)
ORDER: PM747V
PM747CV
,v. 'I'
• '''U,NC1O'I)
DIP PACKAGE ONLY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
PM747
PM747C
Internal Power Dissipation
(See note)
Metal Can (K) package
DIP (V) Package
Differential Input Voltage
Input Voltage
Output Short Circuit
Duration
14I1ALAIICE('"
., \/+ 'A'
.... u,NUI .. 's
'1_4
NO.HNV, INPUT '1'1
TO-l00 (K-Suffix)
ORDER: PM747K
PM747CK
BALANCING CIRCUIT
Storage Temperature Range _65· to 150"C
Lead Temperature Range
(Soldering, 60 sec)
300"C
Operating Temperature Range
-55·C to +125·C
PM747
500mW
O"c to +70·C
PM747C
670mW
±30V NOTE: For the TO-lOO(K) package derate
Supply Voltage
at 7.1mWfC above BO·C; for the
DIP(Y) package derate at 10.0mWI
Indefinite
·C above lOO·C.
±22V
±18V
11
:2
12
'DIP PACKAGE
PIIICMn'
6-135
10
PM747
ELECTRICAL CHARACTERISTICS
Each Amplifier
PM747C
PM747
These specifications apply for TA = 2S'C, Vs = ±15V,
unless otherwise noted.
Par .....ter
Symbol
Input Offset Voltage
VOS
Input Offset Current
Input Bias Current
lOS
IB
Input Resistance
RIN
Input Capacitance
CIN
Test Conditions
Min
-
RS< 10kSl
-
1.0
200
BO
2.0
500
±15
50
200
-
1.4
Large Signal Voltage Gain
AVO
Output Resistance
-
75
Output Short Circuit Current
RO
ISC
-
Supply Current
ISY
-
25
1.7
-
50
Power Consumption
Transient Response Risetime
Po
Vs - ±15 V
VIN = 20mV, RL - 2 kn
(Unity Gainl
CL2kn,VO=±10V
Max
-
0.3
Offset Voltage Adjustment Range
Typ
-
2.8
85
-
0.3
5.0
0.7
-
120
Min
0.3
-
Typ
1.0
20
6.0
200
80
500
2.0
l.4
-
±15
25
200
-
75
-
-
Max
25
1.7
50
-
nA
MSl
pF
mV
V/mV
Sl
mA
2.8
mA
mW
85
-
5.0
-
0.7
mV
nA
-
0.3
120
Units
"sec
%
V/,.sec
d8
The following specifications apply for Vs = ±15V, -55°C < TA
< +125°C for PM747, o"c < TA < +70·C for PM747C, unle..
otherwise noted.
Input Offset Voltage
Input Offset Current
VOS
lOS
-
RS<10kn
-
TA=MAX
TA- MIN
TA= MAX
1.0
6.0
200
7.0
-
85
±12
±13
500
0.03
0.5
Input Bias Current
18
Input Voltage Range
CMVR
Common Mode Rejection Ratio
CMRR
RS<10kn
70
90
Power Supply Rejection Ratio
PSRR
30
Large Signal Voltage Gain
AVO
RS < 10 kll,
Ri ;> 2 kn, Vo = ±10 V
-
-
25
-
Output Voltage Swing
VOM
Supply Current
Power Consumption
ISY
Po
TA= MIN
0.3
RL;> 10 kSl
±12
±14
RL;> 2 kSl
±10
±13
TA = MAX
TA = MIN
-
TA=MAX
-
-
-
TA=MIN
6-136
1.5
2.0
45
60
1.5
\
-
-
-
1.0
7.0
30
0.03
nA
0.8
90
dB
-
30
150
15
±12
-
-
"VIV
V/mV
-
V
70
150
-
±14
-
±10
±13
75
100
0.5
nA
-
0.10
±13
2.5
3.3
300
mV
"A
,.A
±12
-
7.5
200
-
45
-
60
1.5
2.0
2.5
3.3
75
100
V
V
mA
mA
mW
mW
•
PMI
PM-1458/1558
DUAL COMPENSATED OPERATIONAL AMPLIFIER
GENERAL DESCRIPTION
FEATURES
The PM1558 Series of Internally Compensated Dual Operational Amplifiers provides industry-standard 1558 specifications and pin-for-pin compatibility_ In addition, Precision
Monolithics' exclusive Silicon-Nitride "Triple Passivation"
process eliminates "popcorn noise" and provides maximum
reliability a.nd long term stability of parameters for lowest
overall system operating cost. For improved specifications,
refer to the 555747/1558 Dual Internally Compensated
Operational Amplifier data sheet. For precision dual op amps,
refer to the OP-10 Dual Matched Instrumentation Operational
Amplifier data sheet.
SCHEMATIC DIAGRAM
_
Dual PM 741. Internally Compensated Operational
Amplifier
-
Internal Frequency Compensation
_
Low Power Consumption
_
Continuous Short Circuit Protection
_
MI L-STD-883 Processing Available
_
Silicon-Nitride Passivation
PIN CONNECTIONS AND ORDERING INFORMATION
TOP VIEW
INVERTING
,NPUT (A) 2
INVERTIN8
• INPUT (B)
4V-
TO-99
ORDER: PMI558
PM 1458
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
PMI558
PIIiI1458
Internal Power Dissipetion
(See note)
Differential Input Voltage
I!\put Voltage
Output Short Circuit
Duration
Storage Temperature
Range
Lead Temperature Range
(Soldering, 60 secl
Operating Temperature Range
±22V
±18V
PMI558
PM1458
-55·C to +125·C
o"c to +70" C
500mW
±30V
Supply Voltage
Indefinite
For the TO-99(J) peckage derata at 7.1 mWfC above 80·C.
_66° to 15o"C
TO-99!Jl
6-137
PM1458/1558
ELECTR ICAl CHARACTER ISTICS
Each Amplifier
These specifications apply for T A = 25° C, V. = ±15V,
unless otherwise noted.
Parameter
I nput Offset Voltage
Symbol
VOS
I nput Offset Current
lOS
Input Bias Current
IB
I nput Resistance
AIN
Large Signal Voltage Gain
AVO
PM1458
PM1558
\
Test Conditions
Min
AS .. l0kO
-
1.0
0.3
50
AL" 21<0, Vo = ±10V
Typ
Max
Typ
5.0
-
2.0
0.03
0.2
0.2
0.5
-
2.0
-
200
-
-
Output Voltage Swing
VOM
AL ;;.10KO
±12
±14
Input Voltage Aange
CMVA
Vs = ±15V
.,2
.,3
Common Mode Aejection Aatio
CMRA
AS .. ,0kO
70
90
-
,
Min
0.3
. Max
Units
6.0
mV
0.03
0.2
p.A
0.2
0.5
p.A
2.0
-
MO
±12
.14
-
±12
.13
-
V
70
90
-
dB
20
100
V/mV
V
Power Supply Rejection Ratio
PSRR
RS .. 10kO
-
30
150
-
30
150
p.VIV
!'eM.. ConlUmption both·
Amplifiers
Po
Vo=O
-
70
150
-
70
170
mW
Chennel Separation
CS
-
1.20
-
-
120
-
-
-
6.0
-
-
-
0.5
-
-
-
1.5
-
-
25
-
-
15
-
±10
±13
-
±10
±13
dB
l1le following .pecification. apply for V. = ±15V, -55°C .. TA
.. +125°C for PM155B, O°C .. TA .. +700 C for PMI45B,
unless otherwise noted.
Input Off.et Voltage
VOS
Input Offset Current
lOS
Input Bia. Current
IB
RS .. 10kO
Large Signal Voltage Gain
AVO
RL;;' 2kO, Vo = ±10V
Output Voltage Swing
VOM
RL" 2kO
6-138
7.5
mV
0.3
p.A
O.B
p.A
~
V/mV
-
V
•
PMI
IPM4136 I
®
QUAD 741-TYPE OPERATIONAL AMPLIFIER
GENERAL DESCRIPTION
FEATURES
The 'PM4136 Series provides four 741-type operational
amplifiers in a single 14-pin DIP package, pin-compatible
with the RM4136 and RC4136. Each of the four amplifiers
has the proven S,SS741 Series advantages of .Iow noise, low
drift and exeellent long term stability. Precision Monolithics'
exclusive Silicon-Nitride "Triple Passivation" process eliminates "popcorn noise" and provide~ maximum reliability and
long term stability of parameters for lowest overall system
operating cost.
•
•
•
•
•
•
•
•
The PM4136 Series is ideal for use in designs requiring
minimum space and cost while maintaining SSS741-type
performance. PM4136's with processing per the requirements of MIL 38510/883 are available. For dual-741-type
versions, see the SS5747/1558 data sheet.
QUIVALENT SCHEMATIC
RM4136/RC4136 Direct Replacements
Low Noise
Silicon-Nitride Passivation
Internal Frequency Compensation
Low Crossover Distortion
Continuous Short Circuit Protection
Low Input Bias Current
Low Input Offset Voltage
PACKAGE INFORMATION
(1/4 CIRCUIT SHOWN)
(-lIN
(+)IN
-INPUT (A) I
14 -INPUT (0)
+INPUT (A) 2
13 +INPUT (0)
OUTPUT (A) 3
12 OUTPUT (0)
OUTPUT (8) 4
" v+
10 OUTPUT (e)
+ INPUT (8) 5
OUT
-INPUT (8) 6
9 + INPUT (e)
e ~INPUT (e)
v- 7
ORDER: PM4136Y (_55°C to +125°C)
PM4136CY IIfc to +70°C)
Military Temperature Range Devices
With MIL-STD-883A Clas. 8 Processing
ORDER: PM4136-883-Y
TOP VIEW
6-139
PM4136
Supply Voltage
PM4136
±22V
PM4136C'
±18V
I nternal Power Dissipation (Note 1)
800mW
Differential I nput Voltage
±30V
Input Voltage (Note 2)
±15V
Output Short Circuit Duration (Note 3)
Indefinite
--u5°C to +150°C
Storage Temperature Range
Operating Temperature Range
-5S0C to +12SoC
PM4136
PM4136C
O°C to +70°C
300°C
Lead Temperature Range (Soldering, 60 sec)
These specifications apply for T A = +2So C and
Vs = ±1SV unless otherwise specified.
Parameter
Input Offsat Voltage
Input Offsat Current
Input Bias Current
Input Resistance
Large-Signal Voltage Gain
Test Conditions
RS'< 10kn
RL~2kn
VOUT=±10V
Output Voltage Swing
RL~
10 kn
RL> 2kn
Input Voltage Range
Common Mode Rejection Ratio
Supply Voltage Rejection Ratio
Power Consumption
Transient Response (unity gain)
Risetime
Transient Response (unity gain)
Overshoot
Unity Gain Bandwidth
Slew Rate (unity gain)
Channel Separation
RS :5.10kn
RS< 10kn
No load
VIN = 20mV
RL = 2kn
CL:5.100pF
VIN = 20mV
RL = 2kn
CL:5. 1OOpF
RL > 2kn
f = 10 kHz
RS = lkn
NOTES:
1. Rating applies for ambient temperature of +2SoC;
derate linearly at 6.4 mW/oC for ambient temperatures
above +2So C.
2. For supply voltages less than ±lSV, the absolute maxi·
mum input voltage is equal to the supply voltage.
3. Short·circuit may be to ground, one amplifier only.
ISC = 4SmA (typical).
PM4136C
PM4136
0.3
Typ
O.S
S.O
40
S.O
SO,OOO
300,000
Min
-
--
Max
S.O
200
SOO
-
-
±12
±14
±10
il2
70
±13
±14
100
-
-
10
210
150
340
-
0.13
-
5.0
-
3.0
1.5
-
-
0.3
Typ
0.5
S.O
40
5.0
20,000
300,000
Min
~
100;
Input Offset Voltage
Input Offsat Current
Input Bias Current
Large Signal Voltage Gain
±13
±14
100
-
-
V
V
dB
-
IlV/V
10
210
150
340
-
0.13
-
IlS
-
-
5.0
-
%
-
Vllls
-
-
3.0
1.0
-
2kn
TA = High
TA = Low
MHz
dB
-
dB
7.S
300
800
mV
nA
nA
25,000
-
15,000
-
±10
-
-
±10
-
-
-
180
300
-
180
300
mW
240
400
240
400
mW
RL~2kn
RL~
-
mW
-
VOUT=±10V
Output Voltage Swing
-
V
±14
±10
±12
70
-
6-140
6.0
500
1500
-
-
-
•
VIV
-
-
RS:5. 1Okn
-
Units
mV
nA
nA
Mn
±12
105
105
f = 10kHz'
RS= lkn
105
105
Gain = 100
o
o
The following speCifications apply for -5S C .. T A" +12S C for PM4136, O°C .. T A" +70°C for PM4136C, and
Vs = ± 15V unless otherwise specified.
open loop
((ialo
Max
6.0
200
SOO
V/V
V
I
INUMERICAL INDEX
I
I
I
ORDER ING INFORMATION
a.A. PROGRAM
INDUSTRY CROSS REFERENCE
FUNCTIONAL REPLACEMENT GUIDE
I
OPERATIONAL AMPLIFIERS
COMPARATORS
I
I
I
I
I
I
I
I
I
MATCHED TRANSISTORS
VOLTAGE REFERENCES
OJ
rn
rn
rn
rn
II]]
7
rn
rn
DIA CONVERTERS - LINEAR
[iQ]
D/A CONVERTERS - COMPANDING
IIiJ
MULTIPLEXERS
DEFINITIONS
CHIPS
APPLICATION NOTES
PACKAGE INFORMATION
I
NOTES
mJ
mJ
lliJ
rnJ
Ii]
1m
INDEX
COMPARATORS
PRODUCT
TITLE
CMP-Ol
CMP-02
Fast Precision Comparator
Low Input Current Precision Comparator
PAGE
7-1
7-7
PMI
ICMP-011
FAST PRECISION COMPARATOR
GENERAL DESCRIPTION
FEATURES
The CMP - 01 is a monolithic Fast Precision Voltage
Comparator using an advanced compatible NPN-Schottky
Barrier Diode process. It features fast response time to both
large and small input signals, while maintaining excellent input
characteristics. The CMp· 01 is capable of operating over
a wide r~nge of supply voltages, including single 5 volt supply
operation. The large output current sinking and high output
voltage capability assure good application flexibility, while the
combination of fast response, high accuracy, and freedom
from oscillation assure performance in precision level detectors
and 12 and 13 bit AID converters. The CMP-01 is pin
compatible to earl ier 111, 106, and 710 types. For appli·
cations requiring lower input offset and bias currents, refer to
the CMp· 02 data sheet.
_
_
Fast Response Time ...... 110 ns typ., 180 I'IS Max
High Input Slew Rate . . . . . . . . . . . . . . . . 92 VI/J.S
Low Offset Voltage ..... 0.3 mV typ., 0.8 mV Max
Low Offset Current . . . . . . . 4 nA typ., 25 nA Max
_
Low Offset Drift . . . . . . . . . . 1.0 /J.vfc, 30 pAtC
Standard Power Supplies . . . . . . . . . . ±5V to ±18V
_
Guaranteed Operation from Single t5V Supply
No Pull-up Resistor Required for TTL Drive
_
Wired OR Capability
Fits 111, 106,710 Sockets
_
_
SIMPLIFIED SCHEMATIC
Easy Offset Nulling. . . .. Single 2kQ Potentiometer
to Use . . . . . . . . . . . . . Free from Oscillations
! Easy
PIN CONNECTIONS AND ORDERING INFORMATION
TOP VIEW
GNI
R O· U
V·
e
TOUTPUT
N~~~~.r
~
2
6 BALANCE
!S BALANCE
INV. INPUT 3
4
v- (CASE)
TO-99 (J-Suffix)
ORDER: CMP-01J
CMP-01EJ
CMP-01CJ
14
GROUND 2
NON-INV. INPUT 3
INV. INPUT 4
COMP.5
(CASE)
v-
6
BALANCE 7
13
12
II V+
10
'i:I OUTPUT
8 BALANCE
14 PIN HERMETIC DIP (Y-Suffix)
ORDER: CMP-01Y
CMP-01EY
CMP-01CY
Military Temperature Range Devices
With MIL-STD-883A Class B Processing
CMPOl-883-J
CMPOl-883-Y
7-1
I
CMP-01
ABSOLUTE MAXIMUM RATINGS
Total Supply Voltalle, V+ to VOutput to Ground
Output to Negative Supply Voltage
Ground to Negative Supply Voltage
Positive Supply Voltage to Ground
Positive Supply Voltage to Offset Null
Power Dissipation (See Note)
Differential Input Voltage
Input Voltage (V. =±15V)
36V
-5Vto +32V
50V
30V
Output Sink Current (Continuous Operation)
75mA
Operating Temperature Range _55°C to +125°C
CMP-Ol
O°C to +70°C
CMP-01E, -OlC
-65°C to +150°C
Storage Temperature Range
300°C
Lead Temperature (Soldering, 60 Sec)
Indefinite
Output Short Circuit Duration - to ground
1 min.
to V+
30V
Oto 2V
500mW
±llV
±15V
Note: Maximum packagellOwer dissipation vs. ambient temperature
Package Type
Maximum Ambient
Temperature for Rating
Derate Above Maximum
Ambient Temperature
SO°C
100°C
7.1 mW/oC
10.0 mW/C
TO-99 (J)
Dual-in-line. (V)
TYPICAL PERFORMANCE CURVES
RESPONSE TIME FOR 100mV STEP AND VARIOUS INPUT OVERDRI"'ES
~I~
CDI..v
~s~_
@ao.v
.
ffV
~ ,~
,
~ r:;::;..-
.
c/
/ .I
JI/
,
J
-
\
r--
......
I
T,,"u-c
1t'-jA
T.. -tlrC
'6.
,
\
"'_'iIIV
......
,.
~:v
~
1
:::::- -
.
"J=
IJ ...
- r- 1\ \
,
- r- I~ ~
/
RESPONSE TIME VS SOURCE
RESISTANCE
120
3<.
140
,,"NfilSETIIIII!:CIIKC)
aoullCE:.SIST"NCt:C~1l1
RESPONSE TIME. 100mV STEP. 5mV OVERDRIVE. VARIOUS LOADS
' I~
•,.1,.... ~,
-0\IT.4_
;;
i
f
.
~-.,.
I
I--
Vti-tltl
'fa-arc
1ts·IOA
~~
",-tIIV
-+-+--+--f-!:::-:
60
90
IIESPONSt TIlliE
120
(~S£Cl
7-2
·
r-'
,~ D-
·
·,
RESPONSE TIME TEST CIRCUIT
c..-12pF INCLUOING PROBE
AND JIG CAPACITA~E
CMP-01
ELECTRICAL CHARACTERISTICS
These specifications apply for Vs ::::
± 15V,
Parameter
CMP-Ol
T A "" 25°C unless otherwise noted.
Test Conditions
Symbol
Min
Input Offset Voltage
Vas
Rs" 5kn INote 11
Input Offset Current
los
INote 11
Input Bias Current
18
-
Differential Input Resistance
Rin
3.0
Voltage Gain
Av
Va = O.4V to 2.4V
Response Time
t,
100mV step, 5mV overdrive
no load (no pull-up)
5kn to 5V
TTL fan-out = 4, no pull-up
-
Mn
200
500
-
V/mV
-
180
nsec
-
nsec
-
110
110
110
-
osec
-
160
160
160
-
nsec
nsec
nsec
92
-
V/J,lsec
i3.0
V
d8
94
110
80
100
-
dB
3.2
4.8
-
-
V
V
-
0.3
0.3ii
0.45
0.5
V
V
Vin ~ 10mV. Vo - 30V
-
0.03
2.0
Vin" -10mV
-
5.6
8.0
"A
mA
Vin" -10mV
~
1.3
2.2
mA
Vin "-10mV
-
103
153
mW
-
t5
-
mV
1.5
mV
CMRR
5V
Positive Output Voltage
VOH
Yin ~ 3mV, 10 = 320J,lA
Vin ;,.. 3mV, 10 "" a
2.4
2.4
Vin ~ -10mV, Isink
Vin "-10mV, Isink " 12 mA
Positive Supply Current
ILEAK
1+
Negative Supply Current
1-
Power Dissipation
Pd
~
Vs+
~
Nulling Pot
=:
OV, TA
nA
-
±12.5
PSRR
These specifications apply for V s+ =: 5V. V s_
nA
14
Common Mode Rejection Ratio
Offset Voltage Adjustment Range
mV
600
CMVR
VSAT
0.8
350
Power Supply Rejection Ratio
Output Leakage Current
0.3
25
Input Slew Rate
Saturation Voltage
Units
Max.
4
5V step 5mV overdrive
no load (no pull-up)
5kn to 5V
TTL fan-out = 4, no pull-up
Input Voltage Range
Typ.
laV, -18V
~
=:
0;;;;
V s_";; OV
6.4 mA
2kn.
1
= 25°C, unless otherwise noted.
Input Offset Voltage
Vas
Rs" 5kn INote 11
Input Offset Current
lis
INote 11
Input Bias Current
IS
-
3
21
nA
250
500
nA
0.4
Voltage Gain
Av
Vn = O.4V to 2.4V
INote 11
-
50
-
V/mV
Response Time
t,
100m" step, 5mV overdrive
5kn to SV
TTL fan-out = 4, 5kn. to 5V
-
150
150
-
nsec
nsec
-
Input Voltage Range
CMVR
Saturation Voltage
VSAT
1+
Vin ~ -3.5mV, Isink '" 6.4 rnA
-
0.3
0.45
V
Vin" -10mV
2.3
3.2
mA
Pd
Vin ~ -10mV
-
11.5
16.0
mW
Positive Supply Current
Power Dissipation
The following specifications apply for Vs
Input Offset Voltage
1.8/3.5
= ± 15V. _55°C .s;: T A
1.7/3.8
V
~ +125°C, unless otherwise noted.
-
Vas
Rs" 5kn INote 11
V s+ = 5V, V s_ = OV INote 11
-
0.5
0.6
1.6
2.8
mV
mV
Average Input Offset Voltage Drift
Without External Trim
With External Trim
TCVos
TCVosn
Rs = SOn
Rs = son
-
1.5
1.0
-
"vl"c
"vl"c
Input Offset Current
los
TA = +125"C INote 11
TA = -55"C INote 11
-
-
4
8
25
80
TClos
2£)<'>C" TA" +125°C
-55"C" T A" 25"C
TA =+125"C
TA = -55"C
-
12
35
-
300
550
600
1400
100
500
Average Input Offset Current Drift
Input Bias Current
18
Voltage Gain
Av
Va = 0.4V to <.4V
Response Time
t,
100mV step, 5mV overdrive
T A = +125'" C, no load
TA = -55"C, no toad
-
160
-
90
±13.0
V
0.4
0.5
V
V
106
75
96
Vin
Saturation Voltage
VSAT
Vin" -10mV, 'sink - 0
Vin ~ -10mV, Isink "" 6.4 rnA
#
4mV., 10 - 200,u.A
2.4
-
-
nsec
nsec
0.20
0.32
88
5V" Vs+" 15V. -15V," Vs_" OV
-
dB
+12.0
PSRR
V/mV
-
CMVR
CMRR
VOH
nA
nA
3.0
Input Voltage Range
Positive Output Voltage
pAf'C
pA/oC
-
Common Mode Rejection Ratio
Power Supply Rejection Ratio
nA
nA
V
dB
NOTE 1: These parameters are specified as the maximum values required to drive the output between the logic leve;ls of O.4V and 2.4V with a 1 kn. load tied to
+5V; thus, these parameters define an error band which takes into account the worst case effects of voltage gain and input impedance.
7-3
•
CMP-Q1
ELECTRICAL CHARACTERISTICS
CMP-OIE
These specifications apply for V s "" ± 15V ITA
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
0.3
0.8
Input Offset Current
los
Input Bias.Current
IB
-
Differential I nput Resistance
Rin
3.0
Input Offset V9ltage
CMP-OIC
2SoC unless otherwise noted.
Vas
Rs <; 5kn (Note 11
(Note 11
Voltage Gain
Av
Va
Response Time
t,
100mV step, Smv overdrive
no load (no pull~upl
5kn to 5V
TTL fan.-out "" 4, no pull-up
O.4V to 2.4V
14
-
500
-
110
110
110
-
Typ.
Max.
-
0.4
2.8
-
5
80
-
400
900
10
-
1.0
100
500
180
-
-
-
-
-
110
110
110
160
160
160
-
-
-
92
-
<13.0
-
Input Slew Rate
25
600
200
-
5V step 5mV overdrive
no load (no pull-up)
5kn to 5V
TTL fan-out"" 4, no pull-up
4
350
Min.
Input Voltage Range
CMVR
<12.5
Common Mode Rejection Ratio
CMRR
94
110
BO
100
-
-
nsec
nsec
nsec
-
-
92
-
V!/J.sec
-
±12.5
±13.0
-
dB
90
110
74
98
-
-
2.4
2.4
3.4
4.8
5V <; Vs+ <; lBV, -lBV <; V s_ <; OV
ViI"! ;;;, 3mV, 10 "" 320pA
Vin;" 3mV,Io "" 240",A
Vin ~ 3mV, 10 = 0
2.4
2.4
4.8
-
Vin" -10mV, 'sink - 0
Vin" -10mV, Isink' 6.4 rnA
-
0.16
0.31
0.4
0.45
-
0.16
0.31
VSAT
180
-
PSRR
Saturation Voltage
V/mV
nsec
nsec
nsec
VOH
-
nA
Mn
-
Positive Output Voltage
-
nA
160
160
160
Power Supply Rejection Ratio
3.2
Units
mV
-
-
V
dB
-
V
V
V
0.4
0.45
V
V
Output Leakage Current I
ILEAK
Vin ;;. 10mV, Va == 30V
-
0.03
4.0
-
0.05
B.O
!LA
Positive Supply Current
1+
Vin" -10mV
5.6
B.O
-
5.6
8:5
mA
Negative Supply Current
1-
1.3
2.2
-
1.3
2.2
mA
Power Dissipation
Pd
Vin" -10mV
Vin" 10mV
-
Offset Voltage Adjustment Range
==
av, TA =
Vas
Rs <; 5kn (Note 11
Input Offset CUrrent
los
(Note 11
Input Bias Current
Ie
Voltage Gain
Av
Va - O.4V to 2.4V (Note 11
Response Time
t,
lQOmV step, 5mV overdrive
TTL fan-out
Saturation Voltage
Positive Supply Current
VSAT
1+
Power Dissipation
Pd
The following specifications apply for V 5
=
-
.-
1.5
-
-
-
5kU to 5V
CMVR
<5
==
-
4, 5kn to 5V
1.8/3.5
0.4
3
21
mW
<5
-
mV
250
500
50
-
150
150
1.713.8
-
0.5
3.5
mV
65
nA
-
300
720
nA
50
-
V/mV
-
150
150
-
nsec
nsec
1.8/3.5
1.7/3.8
0.3
0.45
V
2.4
3.8
mA
12.0
19.0
mW
-
0.3
0.45
Vin" -10mV
-
2.3
3.2
Yin ::;;;;:-10mV
-
11.5
16.0
-
0;;;
161
4
Vin "-3.5mV, Isink "6.4mA
!.lSV, 0"
103
2SoC unless otherwise noted.
Input Offset Voltage
Input Voltage Range
153
-
Nulling Pot;;' 2kU
These specifications apply for V s+ == 5V, V s-
103
V
T A " +70°C unless otherwise noted.
Input Offset Voltage
Vas
R s " 5kU (Note 11
V s+" 5V, Vs_" OV (Note 1)
-
0.4
0.5
1.4
2.4
-
0.5
0.6
3.5
4.3
mV
mV
Average Input Offset Voltage Drift
Without External Trim
With External Trim
TCVos
TCVosn
Rs" 50!!
Rs" 50U
-
1.5
1.0
-
-
1.8
1.2
-
!LVrC
!LVre
Input Offset Current
los
TA" +70"C (Note 1)
T A" O"C (Note 1)
-
4
5
25
45
-
5
6
80
120
-
12
40
-
-
340
450
900
1200
-
nA
nA
f\verage Input Offset Current Drift
TClos
25"C" TA <; +70"C
O"C <; T A" 25"C
-
12
35
-
Input Bias Current
'e
TA"+70"C
TA"O"C
-
330
400
600
950
Voltage Gain
Av
Va - O.4V to 2.4V
100
500
-
70
500
-
V/mV
Response Time
t,
100mV step, 5mV overdrive
TA == +70u C, no load
TA == O°C, no load
-
130
100
-
-
130
100
nsee
nsec
3.2
-
0.17
0.31
0.4
0.5
Input Voltage Range
CMVR
Common Mode Rejection Ratio
CMRR
' 12.0
Power Supply Rejection Ratio
PSRR
5V" Vs+" 15V, -15V";;; V s_";;; OV
Positive Output Voltage
VOH
Yin
Saturation Voltage
VSAT
Vin" -10mV,l slO k - 0
Vin" -10mV, 'sink == 6.4 mA
> 4mV,
10 == 200p.A
j
13.3
90
108
77
98
2.4
3.2"
-
0.17
0.3
0.4
0.5
'12.0
' 13.3
86
108
70
88
2.4
-
pArC
pArC
nA
nA
V
dB
dB
V
V
V
NOTE 1: These parameters are specified as the maximum values required to drive the output between the logic I~vels of O.4V and 2.4V with a 1 kf! load tied to
+5V; thus, these parameters define an error band which takes into account the worst case effects of voltage gain and input impedance.
7-4
CMP·01
TYPICAL PERFORMANCE CURVES
INPUT OFFSET ERROR VS
SOURCE RESISTANCE
~~:~!~
.
,
i"~
TYPICAL
I IIIIIII
'I--, ~
!
•
-IIIV~Vs-S.O
CD:::t:IO"CID10"CI
~ '~g.I~(i)'"r!'''OC.~
I
~
I-H-'I\'-+./~'''I''.t~-+'I'>i'(-1H-++--I
~CIIIP'Ot
..,
N:~ I-- c.p-Dl~~Vf·!lV r-
CD
CIIIP-DlElO*Ct,7O"C1
-ri'·'
~
·•.t..:-'-+...J...-!:,~I
.....-:..!:"'-±..:-'--±-..J...-±:-"-:-:!
FFffr
f-- -
~~ f-- -
"
V.":tIIY
"s"OOIl
-
I 1111111
,
,
",""
I 11111
VS TEMPERATURE
,
.....
I
.,
INPUT OFFSET CURRENT
OFFSET VOLTAGE VS.
TEMPERATURE
Vi-a"
1
TEIIIPEitATUMi"Cl
INp,UT BIAS CURRENT
...
...
,
~
."
I
I
j
1
I
f-I~'~t= I--
"'.."
I
I
I
I--f'li"oc
21
'"
,
,
I
I
~I
110
SATURATION VOLTAGE
VS SINK CURRENT
,
,
.
.
:,.... ?--
....,: ~
j;"
j.-- =.g[~-.f
I
1
I I
1
25
I
1
... ~
1 I
-15'15",-50'1
'"
'I
il
0
21
TEMPt:ItAYUIIE(-C)
POWER CONSUMPTION
VS TEMPERATURE
SUPPLY CURRENT VS
SUPPLY VOLTAGE
I
I
V
/1, ... ./'
/bF;
..
0
..
•
DIFfERENTIAL IIIPUTVOlTAlE (YOLTSI
....
i ,'" .
I
-!-.L
/
Y
,
rT
...
~
1/
1
}2S0 C
J.o:t'lIV
•
jtftfffm
"
... i .....
71lAC",
I
0
25
TEMfltltATUIIE:
'"
~
CDCMP'OIEIO-C"7O"CI
,
,
...
...
~~:"""..:::"'"
l"'--J~~,- f--
INPUT VOLTAGE RANGE
VS TEMPERATURE
,
,,,
...
-15V~Vj50
~
... f-~,
INPUT BIAS CURRENT VS
DIFFENTIAL INPUT VOLTAGE
VS TEMPERATURE
f-
1
j
i ..
I "t--+-+-...,.."-
I
tj=t;!=:t:~.~.l~'''='~''''~-=~f--~
1..+--+--+-+--+--+-+-+---1
§
~
~.,t--+-+--+-~---l---l--I----l
~
""1'''"1'' r- II
+D\lSV{:S+II5Y
to
20
..
~+,,~.~~.~~4,~~..~~..~~~~"!
;'0
QUTPUTSlNlCCUftMNTt""",
OFFSET TRIMMING AND
STROBE CIRCUITRY
TEMI'EItATtIItI!:t"C)
RESPONSE TIME FOR 5V STEP AND 5mV OVERDRIVE
RESPONSE TIME FOR 5V STEP
RESPONSE TIME FOR !IV STEP
AND 5mV OVERDRIVE
AND 5mV OVERDRIVE
I I I
I--
/
f--
/
I--
/OIJTPUT
f=~==i=~/:"""--I---j--i~:~;~As·son
100
200
AE:SPONUTIMEtn5EC)
7·5
iF
, I--0
I I I
I I I
NOLOAO
Vs ·:t15V
T... ·a5·C
As·Mla
-
•
CMP-01
APPLICATION NOTES
The
CMP-01
provides
fast
response
times even with small
creating a hysteresis condition can be very effective - see
diagram on page 6. Matched bypass capacitors across. the input
resistors also can eliminate the instability,
input overdrives; to achieve this performance requires very high gain
at high frequencies. The CMP·Ol is completely free of
oscillations; however, small values of stray capacitance from output
to input when combined with high·source resistances can cause an
and if C ~ 20 pF [ maximum step size]
S
minimum overdrive
the response time will approximate the response time for low values
of Rs' It should be noted that the offset nulling terminals do not
require bypassing for stability. As with all wideband circuits, it is
recommended that the supplies be bypassed near the socket of the
device.
unstable condition. D. C. characteristics are not affected, but when
the input is within a few microvolts of the transition level, certain
conciitions can create an oscillation region. The width of this
oscillatory region and the size of source resistance where oscillations
begin
is a strong function
of the stray
coupling present. The
following suggestions are offered as a guide towards minimizing the
conditions for oscillation: matched source resistors, minimized stray
capacitances (e.g. a ground plane between output and input),
capacitive output loading (C L ), or a capacitor from the
clITIIAY
rc~~~. r------if-----,
r---.~~r4~1~~
!
R,
~MP~">-~I-~--oOUTPUT
compensation terminal to A.C. ground (DIP only). The capacitive loading techniques will eliminate the oscillations, but
result in slower response time. Positive resistive feedback
. 'I.~:.fv-.---
~~
-100m\'
O
V,·tIIlV
-+-+-+- ~::::
I
v..r-FALL' (Vee +OYERDRIYE)
L.,RtsE· (VOl -OVERDRIVE)
'"
RESPONSE TIMEtnlECI
7-8
I ,
SOURCE MilITANCE IkOl
c;,-12pf INCLU"NG_
AND "'ta CAPACITANCE
_,
-.10
.'~'.'. ~,."
~
ItESPONlIE TIllE t~lttJ
TLeATtLOAO
FAit-out-.
~
,
I
000,'0 IV
i
-hio~;
I
RESPONSE TIME, lOOmV STEP, 5mV OVERDRIVE. VARIOUS LOADS
i
roo
RESPONSE TIME VS SOURCE
RESISTANCE
CMP-02
CMP-02
ELECTRICAL CHARACTERISTICS
These specifications apply for Vs = ± 15V, T A :::: 25° C unless otherwise noted.
Parameter
Symbol
Test Conditions
Typ.
Max.
-
0.3
0.8
mV
-
0.3
0.9
mV
0.3
3.0
nA
Min.
Input Offset Voltage
Vos
R s .. 5kn (Note 11
Input Offset Voltage
R s .. 50Kn (Note 11
Input Offset Current
Vos
10,
Input Bias Current
IB
-
28
Differential Input Resistance
Ri"
Av
t,
5.0
16
Voltage Gain
~Response
Time
(Note 1)
Vo = O.4V to 2.4V
200
500
5kn to 5V
-
TTL fan-out"" 4. no pull-up
-
190
190
190
-
Input Slew Rate
CMVR
±12.5
Common Mode Rejection Ratio
CMRR
94
110
Power Supplv Rejection Ratio
PSRR
5V .. V'+" 18V. -18V .. Vs_" OV
80
100
Positive Output Voltage
VOH
Vin ;> 3mV, 10 = 320"A
V/mV
270
nsec
"sec
nsec
-
±13.0
2.4
2.4
Vin ;;;. 3mV, 10 = 0
Output Leakage Current
nA
Mn
-
V/"sec
-
dB
12.5
Input Voltage Range
VSAT
50'
lOOmV step, 5mV overdrive
no load (no pull-up)
Saturation Voltage
Units
V
-
dB
3.2
4.8
0.45
0.5
V
V
V
V
Vin '" -10mV. 'sink - 6.4 rnA
Vin '" -10mV, Isink = 12 rnA
-
0.3
0.36
-
0.03
2.0
Vin '" -10mV
5.J
8.0
"A
mA
1.1
2.2
rnA
ILEAK
1+
Vin;> 10mV, Vo - 30V
Positive Supply Current
Negative Supply Current
1-
Vin
<: -10mV
-
Power Dissipation
Pd
Vin ~ 10mV
Nulling Pot ;;;;r. 2kn
-
99
-
±5.0
-
0.4
1.5
0.25
3.0
24
45
-
50
-
V/mV
-
250
250
-
nsec
0.45
V
Offset Voltage Adjustment Range
These specifications apply for V s+ "" 5V. V s-
V o,
Rs .; 5kn (Note 1)
Input Offse~ Current
10 ,
(Note 1)
Input Bias Current
IB
Av
Vo
t,
1OOmV step. 5mV overdrive
Response Time
rnW
mV
= OV. T A"" 2SoC. unless otherwise noted.
Input Offset Voltage
. Voltage Gain
153
0
0.4V to 2.4V (Note 1)
5kn to 5V
TTL fan·out
0
4, 5kn '05V
mV
nA
nA
nsec
Input Voltage Range
CMVR
Saturation Voltage
Positive Supply Current
VSAT
1+
Vin<
10mV
-
2.2
3.0
rnA
Power Dissipation
Pd
Vin" -10mV
-
11.0
15.0
rnW
The following specifications apply for Vs
= ±15V. -5SoC ~ TA <: +125°C. unless otherwise noted.
Input Offset Voltage
Vos
R,.; 5kn (Note 11
Vs+ 0 5V, V,_ =OV (Note 11
-
-
0.5
0.6
1.6
2.8
rnV
mV
R, o50n
Rs o50n
-
1.5
1.0
-
"V/oC
-
"VrC
TA
TA
-
0.3
0.6
4.0
12.0
2.0
4.0
-
Average Input Offset Voltage Drift
Without External Trim
With External Trim
TeVosn
Input Offset Current
10 ,
Average Input Offset Current Drift
Input Bias Current
Voltage Gain
Response Time
TCVos
TClos
IB
1.8/3.5
0
0
+125°C (Note 11
-55°C (Note 1)
-
-
TA
TA
-
0
-
+125°C
_55°C
Av
Vo
"
1OOrnV step. 5mV overdrive
TA = +125"'C. no load
T A "" -55 0 C. no load
0
0.4V to 2.4V
0.30
,
V
,
25°(; .. TA .. +125'C
-55°C .. TA .. 25°C
0
1.7/3.9
-
Vin ~ -3.5mV. 'sink ~ 6.4 mA
nA
n.\
pArC
pArC
25
45
50
120
100
500
-
V/mV
-
310
155
nsec
nsec
dB
dB
Ir:'Iput Voltage Range
CMVR
±12.0
Common Mode,Rejection Ratio
CMRR
88
106
-
Power Supply Rejection Ratio
PSRR
5V .. V,+" 15V, -15V" Vs_" OV
75
96
-
Positive Output Voltage
VOH
Vin ;> 4rnV, 10 - 200"A
2.4
3.0
Saturation Voltage
VSAT
Vin.s;:;; -10mV.lsink - 0
Vin ~ -10mV. 'sink"" 6.4 rnA
-
0.20
0.32
-
±13.0
nA
nA
V
V
0.4
0.5
V
V
NOTE 1: These parameters are specified as the maximum vakJes required to drive the output between the logic levels of D.4V and 2.4V with a·1 kn load tied to
+5V; thus. these parameters define an error band which takes into account the worst case effects of voltage gain and input impedance.
7-9
•
CMP-02
ELECTRICAL CHARACTERISTICS
CMP·02E
CMP-02C
These specifications apply for Vs = ± 15V, TA "" 2SoC unless otherwiH, noted.
Min.
Typ.
Max.
Min.
Typ.
Max.
-
0.3
0.8
-
0.4
2.8
mV
Rs <; 50Kn (Note 1)
0.3
0.9
-
3.0
mV
(Note 1)
0.3
3.0
Symbol
Parameter
Test Conditions
Input Offset Voltage
Vos
Rs <; 5kn (Note 1)
Input Offset Voltage
Vos
Input Offset Current
los
Input Bias Current
IB
Differential Input Resistance
Rin
28
5.0
Voltage Gain
Av
Vo = O.4V to 2.4V
Response Time
t,
l00mV step, 5mV overdrive
no load Ina pull-up)
50
16
0.4
0.4
1.5
100
12
-
Mn
270
rrsec
nsec
nsec
200
500
-
100
500
-
190
190
190
270
-
190
190
190
-
15
-
Input Voltage Range
CMVR
.12.5
'13.0
-
±12.5
Common Mode Rejection Ratio
CMRR
94
110
-
90
110
Power Supply Rejection Ratio
PSRR
5V <; V s+ <;18V, -18V <; V s_ <;OV
80
100
74
98
Positive Output Voltage
VOH
Vin ;. 3mV, 10 = 320p.A
Vin ;. 3mV, 10 = 24~p.A
Vin ;. 3mV, 10 = 0
Input Slew Rate
Saturation Voltage
VSAT
Output Leakage Current
Vin <; -10mV, Isink
=0
Vin';;;; -10mV, Isink
or;;;;
ILEAK
1+
Vin;' 10mV, Vo = 30V
Negative Supply Current
1-
Vin <; -10mV
Power Dissipation
Pd
Vin ~ -10mV
Positive Supply Current
These specifications apply for V s+
Vin <;-10mV
= 5V, V s- = av, TA = 25°C unless otherwise
Input Offset Voltage
0.16
0.31
0.4
0.45
-
0.03
4.0
5.5
8.0
-
Vos
10 ,
Input Bias Current
IB
Voltage Gain
Av
Vo = O.4V to 2.4V (Not. 1)
Response Time
t,
100mV step, 5mV overdrive
(Note 1)
-
5kn to 5V
TTL fan·out = 4, 5kn to 5V
Input Voltage Range
CMVR
Saturation Voltage
Positive Supply Current
VSAT
1+
Ifin <; -10mV
Power Dissipation
Pd
Vin <; -10mV
Vin ~ -3.5mV, 'sink ~ 6.4 mA
The following specifications apply for Vs = ±lSV, CO ~ TA
Vos
-
-
<:
V/p.sec
V
dB
-
dB
2.4
2.4
3.4
4.8
V
V
V
-
0.16
0.31
0.4
0.45
V
V
0.05
8.0
p.A
5.6
8.5
mA
2.2
mA
-
-
0.4
1.5
-
0.25
3.0
-
1.1
99
±S.O
2.2
153
24
45
-
-
1.2
102
161
mW
-
mV
3.5
mV
±5.0
-
-
250
250
-
30
14
nA
90
nA
50
-
-
v/mV
-
250
2!,0
-
nsec
nsec
1.8/3.5
1.7/3.8
0.3
2.3
3.6
mA
15.0
-
11.5
18.0
mW
0.4
0.5
1.4
2.4
-
0.5
0.6
3.5
4.3
mV
mV
1.5
1.0
-
1.8
.1.2
-
p.vf'c
p.vf'c
0.3
0.4
3.0
6.0
-
0.4
0.5
1'5
25
2.0
4.0
-
-
3.0
5.0
-
1.8/3.5
1.7/3.8
-
0.3
2.2
3.0
-
11.0
-
0.5
0.35
50
0.45
0.45
V
.v
+7COC unless otherwise noted.
Rs <; 5kn (Note 1)
V,+ = 5V, V s_ = OV (Note 1)
-
Input Offset Current
los
TA = +70°C (Note 1)
TA = O°C (Note 1)
Average Input Offset Current Drift
TClos
25°C <; T A <; +70"C
O°C <;TA <;25°C
-
TA=+70°C
TA = O°C
-
26
34
50
80
100
500
-
225
180
18
-
15
±13.0
-
TCVos
Input Bias Current
-
V/mV
-
3.2
Average Input Offset Voltage Drift
Without External Trim
With External Trim
TeVosn
-
nA
noted.
Rs <; 5kn (Note 1)
Input Offset Current
Input Offset Voltage
4.8
-
Nulling Pot ~ 2kn
Offset Voltage Adjustment Range
2.4
-
2.4
6.4 rnA
-
nA
35
-
5kn to 5V
TTL fan-out'" 4, no pull-up
15
Units
-
Rs = 50n
Rs = 50n
-
Voltage Gain
Av
Vo = O.4V to 2.4V
Response Time
t,
100mV step, SmV overdrive
TA = +70"C, no load
T A = O°C, no load
-
1nput Voltage Range
CMVR
Common Mode Rejection Ratio
CMRR
Power Supply Rejection "Ratio
PSRR
5V <;'V s+<;15V, -15V<;V s <;OV
Positive Output Voltjige
VOH
Vin ;. 4mV, 10 = 200p.A
Saturation Voltage
VSAT
Vin fii; -10mV,l sink = 0
Vin <; -10mV, Isink = 6.4 mA
'12.0
90
'13.0
77
98
-
-
nA
nA
pAf'C
pAf'C
-
33
42
100
160
-
70
500
-
V/mV
-
-
225
180
-
nsec
-
108
-
-
'12.0
'13.0
86
108
10
88
nA
nA
"sec
V
dB
-
dB
2.4
3,2
2.4
3.2
-
-
V
0.17
0.30
0.4
0.5
-
-
0.17
0.31
0.4
0.5
V
V
-
NOTE 1: These par8m~ters are specified as the maximuno:' values required to drive the output between the logic levels of O.4V and 2.4V with a lkn load tied to
+5V; thus, these parameters define an error band which takes into account the wors! case effects of voltage gain and input impedance.
7-10
CM_P-02
TYPICAL PERFORMANCE CURVES
INPUT OFFSET ERROR VS
SOURCE RESISTANCE
INPUT OFFSET CURRENT
OFFSET VOLTAGE VS
TEMPERATURE
UNlU-L:-
-'
,
I
,
VS TEMPERATURE
.
I
I
l
rcaP«
:~:--"
I C...oHlo-C .. 7O"C1
'it-till\!
ft,ollOQ
,
.
,
l\f-1i' j',~
INPUT BIAS CURRENT
~I. ~
,
-n
-00
..
00
,
-7$
INPUT BIAS CURRENT VS
DIFFENTIAL INPUT VOLTAGE
VS TEMPERATURE
-50
-ZII
0
H
so
1&
tOO
121
INPUT VOLTAGE RANGE
VS TEMPERATURE
-=tttffil
i"+-'-"
I'i . .·
i . --.,.
v""+1.0
;
I
I
~===~
J...l
I I
-1111:1",-5.0\/
I -uI ,
.. __ •
~+.~ ~.w~_.~~,~L-~.~~.~~
-10
DII"I"EIflENTIALINPUT\IOl.TIlGEIYOLTSI
SATURATION VOLTAGE
VS SINK CURRENT
V
JII"~MI'J8IT1VE
f-SUPPLYIS ..... IIV
Ta o2SOC
/'
OIJTflUTLO'II/
VI"" / '
V Y
V VIP
"'"'"
v. !?' .....
k':l ~
-'5VtV.-l~
'f'
,,
to
- -
I
to
50
.-,,
,
I I
I
+18V
I
T,,-!SOC
V.°tIIV
h~11
... ~
-
,
-Iav
,
,
I ..I
n
~sa:1
~c
,".MlN
OUTPUT IKOItTEDATloO
11 I
.
~
OUTPtlTVOLTAKIVOl.nJ
7-11
,n
-
I
oo-I------'Fi-""-+--+-I----I-----+-----+-l
"j'AT'jSUPPLI
OUTPUT SHORT-CIRCUIT CURRENT
VS OUTPUT VOLTAGE
,
. .
ts
tiD
UUPf'LYYOt.TAKIYCX.TSI
OUTPUT SINK CURRENT InIAl
STANDARD BURN-IN CIRCUIT
... ,t~
;.,t--+-t--r-r--r~r--r-1
~PUTH!ClH
~I
-
I
i,,+-~~~+--+-+-~~~
i
POSITIVElY
/
I
+!lY:SV/!;+ISV
V
)/'f
~
'I
d I
POWER CONSUMPTION
VS TEMPERATURE
SUPPL Y CURRENT VS
SUPPLY VOLTAGE
I
/
!uoc V
Va+'IIIV
::"
OFFSET TRIMMING AND
STROBE CIRCUITRY
CMP-02
APPLICATION NOTES
The CMP-Q2 provides fast response times even with small
input overdrives; to achieve this performance requires very high gain
at high frequencies. The CMP-02 is completely free of
oscillations; however, small values of stray capacitance from output
to input when combined with high-source resistances can cause an
unstable condition. D. C. characteristics are not affected, but when
creating a hysteresis condition can be very effective - s••
diagram on page 6. Matched bypass capacitors across the input
fesistors also can eliminate the instability.
the input is within a few microvolts of. the transition level, certain
conciitions can create an oscillation region. The width of this
of Rs' It should tie noted that the offset nulling terminals do not
oscillatory region and the size of source resistance where oscillat!ons
begin is a strong function of the stray coupling present. The
following suggestions are offered as a guide towards minimizing the
conditions for oscillation: matched source resistors. minimized stray
capacitances (e.g. a ground plane between output and input),
capacitive output loading (C l ), or
capacitor from the
compensation terminal to A.C. ground (DIP only). The capa-.
citive loading techniques will eliminate the oscillations, but
result in stower response time.. Positive resistive feedback
recommended that the supplies be bypassed near the socket of the
device.
and if C
S
~
'20 pF [
.
the response time will approximate
require bypassing for
stabi~ity.
maximum step size
minimum overdrive
J
the response time for low values
As with all wideband circuits, it is
emAY
2~ l~
r----If----,
:
+
•
R.
.A~
'::'
I
I
CllP-OZ
li~
rV
!
'-----If-----'
CsT"",
t
OUTPUT
CL
TYPICAL APPLICATIONS
lEVEL DETECTOR WITH
HYSTERESIS (Positive Feedback)
PRECISION, DUAL LIMIT, GO/NO GO TESTER
UPPER
LIMIT
02
RI
VREF
INPUT
RIIIR2
INPUT
Wired OR Output is low when
either limit is exceeded.
Output is high when
R,
input is within limits.
Hysteresis width';;; 4V R, + R2
PRECISION PHOTODIODE LEVEL DETECTOR
For R, = 2.5 Mn, R2 = R3 = 5Mn, the output state
changes at a photo diode current (I}.,T) of O.5,uA. (The
output changes state at threshold current I}.,T = ~ where
R
2R2
R,
and R3 R2 )
RZ
=T
5kO
7
TTL FAN-OUT. 3
7-12
=
I
NUMERICAL INDEX
IORDERING INFORMATION
I
QA. PROGRAM
I INDUSTRY CROSS REFERENCE
IFUNCTIONAL REPLACEMENT GUIDE
I
OPERATIONAL AMPLIFIERS
I,COMPARATORS
MATCHED TRANSISTORS
I VOLTAGE REFERENCES
lOlA CONVERTERS - LINEAR
m
rn
rn
rn
rn
rn
IT]
8
rn
ITQJ
lOlA CONVERTERS- COMPANDING
[IT]
I MULTIPLEXERS
1m
I
DEFINITIONS
I
CHIPS
I
APPLICATION NOTES
I
PACKAGE INFORMATION
I
NOTES
mJ
1m
IE
rnJ
1m
INDEX
MATCHED TRANSISTORS
PRODUCT
TITLE
MAT-01
Ultra-Matched Monolithic Dual Transistor
PAGE
8-1
PMI
,MAT-Oll
®
ULTRA-MATCHED MONOLITHIC DUAL TRANSISTOR
EXCELLENT LOG CONFORMANCE
GENERAL DESCRIPTION
FEATURES
The MAT-Ol series are mORQlithic ultra-tightly matched
dual NPN transistors, fabricated using an exclusive Silicon
Nitride "Triple-Passivation" process which provides extreme stability of critical parameters versus both temperature
and time_ Outstanding matching characteristics include offset
voltages of.40pV, temperature drift of Vas of 0.15pV /oC and
hFE matching of 0.7%. Very high hFE is provided over a six
decade range of collector current, including an exceptional
hFE of 590 @ Ic = 10nano amperes! Excellent logarithmic
conformance over a seven decade collector current span
suggests application in log/antilog and multiplier/divider circuitry. The very low values of noise voltage and current make
the MAT-Ol ideal for usage in critical low-level input
stages while the 6 pin TO-99 package allows direct replacement of most previous dual transistors for immediate performance improvements. The very high hFE: ~t low collector
•
•
Tight Vos (VBE Match) .....40pV Typ, 100J.LV Max
Low TC Vas. _ .. __ O.15pVtC Typ, O_5pVtC Max
•
Tight hFE Match. ___ . . . . . . 0.7% Typ, 3.0% Max
•
High hFE . . . . . . . . . . . . . . . . . 770 Typ, 500 Min
•
Excellent hFE Linearity from 10nA to 10mA
•
•
High hFE at Low IC . . . . . . . . 590 Typ @ Ic = 10nA
Low Noise Voltage .... 0.23pVp-p - 0.1 Hz to 10Hz
•
Excellent Long Term Stability .. 0.2pV/Month, Typ
•
High Breakdowns . . . . . . . . . . . . 45V and 60V Min
•
Precision Logarithmic Conformance
•
Direct Replacement for Most Dual Transistors
attractive in
currents also makes the MAT-Ol
impedance and micropower circuit designs.
all
high
ABSOLUTE MAXIMUM RATINGS
MAT-01
AH,GH
Collector-Base Voltage IBV CBO )
Collector-Emitter Voltage IBV CEO )
Collector-Collector Voltage (BVCCI
Emitter-Emitter Voltage (BV EE )
Emitter-Base Voltage (BV EBO ) (Note 1)
Collector Current (I CI
Emitter Current (IE)
45V
45V
45V
45V
5V
25mA
25mA
MAT-01
H, FH
60V
60V
60V
60V
5V
25mA
25mA
MAT-01
AH,GH
MAT-01
H
f"H
Total Power Dissipation
Case Temperature '::::;;;40 oC (Note 2)
1.8W
Ambient Temperature ~ 70°C
(Note 3)
Operating Ambient Temperature
Operating Junction Temperature
Storage Temperature
Lead Temperature (Soldering, 60 sec.)
1.8W
500mW
500mW
_55°C to +125°C
_55°C to +150 oC
. _65°C to +150 oC
300°C
NOTES
Note 2: Rating applies to applications using heat sinking to control
Note 1: Application of reverse bias voltages in excess of rating
shown can result in degradation of hFE and hFE matching characteristics. Do not attempt to measure BV EBO greater than the 5V
rating shown.
case temperature. Derate linearly at 16.4mW/oC for case temperatures above 40° C_
N9te 3: Rating applies to applications not uSing heat sinking; device
in free air only. Derate linearly at 6.3mW/oC for ambient temperatures above 70°C.
~
PIN CONNECTIONS AND ORDERING INFORMATION
TOP VIEW
I
CI
2
BI
7
,---- ...., Cz
,, 6
\,
--- - / B2
Military Temperature Range Devices
With MIL-STD-883A Class B Processing:
I
3
5
EZ
EI
Note: Substrate is connected to case.
ORDER: MAT-01AH
MAT-01H
MAT-01FH
MAT-01GH
8·'
ORDER: MATOI-883-AH
MATOI-883-H
MAT01-883-FH
MATOI-883-GH
I
MAT-01
ELECTRICAL CHARACTERISTICS
These specifications apply for VCB = 15V, IC = 1OjlA, TA = 25°C, unless otherwise noted.
MAT -01AH
Symbol
Parameter
Min
Test Conditions
MAT -01GH
Typ
Max
Min
Typ
Max
Units
Breakdown Voltage
BVCEO
45
-
-
45
-
-
V
Offset Voltage
Vos
-
0.04
0.1
-
0.10
0.50
mV
Offset Voltage Stability
First Month
Long Term
VoslTime
VoslTime
2.0
0.2
-
-
2.0
0.2
Offset Current
los
-
0.6
Bias Current
IB
-
13
Current Gain
hFE
IC = 10nA
-
590
-
-
430
hFE
IC = 10jlA
500
770
560
IC = 10mA
-
840
-
250
hFE
610
0.7
lIhFE
100nA .. IC .. 10mA
-
0.8
-
-
enp~p
O.lHz to 10Hz
(Note 3)
-
0.23
0.4
-
0.60
-
7.0
9.0
Current Gain Match
(Note 1)
(Note 2)
lIhFE
Low Frequency Noise Voltage
20
3.0
0.2
18
-
jlV/Month
jlV/Month
3.2
nA
40
nA
-
1.0
8.0
1.2
-
%
%
-
0.23
0.4
jlVp-p
0.60
-
7.0
9.0
jlVRMS
nVy'Hz
nV/y'Hz
6.1
7.6
-
6.1
7.6
fo = 1000Hz (Note 3)
-
6.0
7.5
-
6.0
7.5
nV/y'Hz
0.5
3.0
-
0.8
B.O
jlVN
Broadband Noise Voltage
enRMS
1Hz to 10kl-jz
Narrowband Noise Voltage
en
fo = 10Hz (Note 3)
Density
0.1
-
fo = 100Hz (Note 3)
-
Offset Il'oltage Change
lIVos/llVCB
0 .. VCB" 30V
-
Offset Current Change
lIlos/lIVCB
0 .. VCB .. 30V
-
15
-
Collector-Base Leakage Current
ICBO
VCB - 30V, IE-O
INote 4)
-
15
50
-
25
200
pA
Collector-Emitter Leakage
ICES
VCE = 30V, VBE = 0
INote 4)
-
50
200
-
90
400
pA
ICC
VCC = 30
-
20
200 .
-
30
400
pA
VCEISAT)
IB -O.lmA, IC -lmA
VCEISAT)
IB = lmA, IC = 10mA
Gain-Bandwidth Product
fT
VCE - 10V, IC -10mA
Output Capacitance
Cob
VCE = 15V, IE =0
Collector-Collector Capacitance
CCC
VCC -0
Current
Collector-Collector Leakage
2.0
3.0
70
pAN
Current
Collector
Sa~uration
Voltage
-
-
0.12
0.20
-
0.12
0.25
0.8
-
-
0.8
-
V
-
,MHz
-
pF
8.5
0.14
0.70
mV
0.35
1.8
jlVfC
2.8
-
-
,8.5
-
-
450
450
2.8
V
pF
The following specifications apply for VCB = 15V, IC = 10jlA, -55°C .. TA" +125°C, unless otherwise noted.
Offset Voltage
Vos
Average Offset Voltage Drift
TCVos
Offset Current
los
Average Offset Current 0 rift
TClos
-
10
90
-
28
60
167
400
-
INote 3)
INote 3)
0.06
0.15
0.15
0.50
-
8.0
-
0.9
Bias Current
IB
Current Gain
hFE
Collector-Base Leakage Current
IC80
TA-125 C,VCB=30V,
IE = 0 (Note 4)
-
15
80
Collector-Emitter Leakage
Current
ICES
TA-125 C,VCE-30V,
VBE = 0 INote 4)
-
50
300
Collector-Collector Leakage
Current
ICC
T A = 125°C, VCC = 30V
-
30
200
1.5
15.0
nA
15
150
pAi"C
-
36
130
nA
77
300
-
-
25
200
nA
90
400
nA
50
400
nA
-
NOTES:
Note 1:
Exclude first hour of operation to allow for stabilization of external circuitry.
Note 2:
Parameter describes long term average drift trend after first month of operation.
Note 3:
Parameter is not 100% tested; 90% of all units meet this ~pecification.
Note 4:
The collector-base (leBO) and collector-emi'tter (lCEO) leakage currents may be reduced by a factor of two to ten times by connecting
the substrate (package) to a potential which is lower than either collector voltage.
8-2
MAT-01
ELECTRICAL CHARACTERISTICS
These specifications apply for VCB = 15V, IC = 101lA, T A = 25°C, unless otherwise noted.
MAT-01H
Test Conditions
Symbol
Parameter
Min
Typ
MAT-01FH
Max
Min
Typ
Max
Units
Breakdown Voltage
BVCEO
60
-
-
60
-
-
V
Offset Voltage
Vas
-
0.04
0.1
-
0.10
0.50
mV
Offset Voltage Stability
First Month
Long Term
VoslTime
-
2.0
0.2
-
2.0
0.2
-
-
1lV,/Month
IlV/Month
3.2
nA
Vas/Time
(Note 1)
(Note 2)
-
-
Offset Current
los
Bias Current
IB
Current Gain
hFE
IC = 10nA
-
hFE
IC = 10llA
330
hFE
IC -lOrnA
-
-
0.7
2.7
laOnA'; IC .; lOrnA
0.8
-
O.IHz to 10Hz
(Note 3)
-
0.23
0.4
-
0.60
-
7.0
9.0
6.1
7.6
6.0
7.5
0.5
3.0
2.0
15.0
Current Gain Match
AhFE
Low Frequency Noise Voltage
AhFE
e np _p
-
0.1
O.B
-
0.2
30
-
18
-
430
680
-
250
560
740
-
-
610
15
520
-
40
nA
-
-
-
1.0
8.0
1.2
-
%
%
0.23
0.4
IlVp-P
0.60
-
7.0
9.0
IlVRMS
nV/..jHz
Offset Voltage Change
AVos/AVCB
0.; VCB'; 45V
-
Offset Current Change
Alos/avCB
0.; VCB .;45V
-
Collector-Base Leakage Current
ICBO
VCB = 45V, IE = 0
(Noie 4)
-
15
50
-
Collector-Emitter Leakage
Current
ICES
VCE = 45V, VBE = 0
(Note 4)
-
50
200
-
90
400
pA
Collector-Collector Leakage
Current
ICC
VCC = 45
-
20
200
-
30
400
pA
Collector Saturation Voltage
VCE(SAT)
IS = O.lmA, IC = lmA
-
0.12
VCE(SAT)
IB = lmA, IC = lOrnA
-
0.8
Gain-Bandwidth Product
fT
VCE -10V, IC -lOrnA
Output Capacitance
Cob
VCE = 15V, IE =0
Collector-Collector Capacitance
CCC
VCC =0
-
Broadband Noise Voltage
enRMS
1Hz to 10kHz
Narrowband Noise Voltage
en
fa = 10Hz (Note 3)
Density
fa = 100Hz (Note 3)
fa = 1000Hz (Note 3)
6.1
7.6
nV/..jHz
6.0
7.5
nV/..jHz
8.0
p,V!V
O.B
3.0
70
pA!V
25
200
pA
-
0.12
0.25
V
-
-
0.8
-
V
2.B
-
-
2.8
B.5
-
-
450
0.20
-
-
MHz
pF
8.5
-
0.14
0.70
0.35
1.8
450
pF
The following specifications apply for VCB = 15V, IC = 101lA, -5SoC'; TA'; +125°C, unless otherwise noted.
Offset Voltage
Vas
Average Offset Voltage Drift
TCVos
Offset Current
los
Average Offset Current Drift
TClos
Bias Current
IB
'Current Gain
hFE
Collector-Base Leakage Current
ICBO
-
(Note 3)
-
0.15
0.15
0.50
-
9.0
-
0.9
-
(Note 3)
0.06
105
T A - 125°C, VCB = 45V,
11
110
-
30
95
-
350
1.5
15.0
mV
J,lV/oC
nA
15
150
pA/oC
-
36
130
nA
77
300
-
25
200
nA
15
BO
-
50
300
-
90
400
nA
-
30
200
-
50
400
nA
IE = 0 (Note 4)
Collector-Emitter Leakage
ICES
Collector~Coliector
TA = 125°C, VCE - 45V,
VBE = 0 (Note 4)
Current
Leakage
ICC
TA _125°C, VCC = 45V
Current
NOTES:
Note 1:
Exclude first hour of operation to allow for stabilization of external circuitry.
Note 2:
Parameter describes long term average drift trend after first month of operation.
Note 3:
Parameter is not 100% tested; 90% of all units meet this specification.
Note 4:
The collector-base (leBO) and collector-emitter (lCEO) leakage currents may be reduced by a factor of two to ten times by connecting
the substrate (package) to a potential which is lower than either collector voltage .
..
8-3
I
MAT-01
TYPICAL PERFORM-\NCE CURVES
OFFSET VOLTAGE
OFFSET DRIFT VS_ TIME
BASE-EMITTER VOLTAGE
VS_ TEMPERATURE
VS_ COLLECTOR CURRENT
200,.----,----,--,---;--,---,----,-----,
0
8
,
.
IOdVar 530V!
. I
[---i- i- -
:VPl.\
.,
"Ivrr
2-'" ~-
100
-~
125
TEMPERATURE-·C
o
CURRENT GAIN
~~
~ 100nA'Hr+-t--H~/
DEVICE 'C'
8. 10rlAt--t--+-Hf--1
~
-5
6
.10011
7
89m
TIME-IMONTHS)
11
n
13
BASE-EMITTER VOLTAGE, V -mV
SATURATION VOLTAGE
VS_ COLLECTOR CURRENT
I
1:1
:.Ll ./'"
0
0r,z
V
Y': V
MAT~
,--
I - e-"AT-rn
~T-OIF.G
800b--+-+----i-+----,~--+-+...,.j
~
6oob--+-+A-+-/=t------+-+----+
T4 "25"C
'1.. -15\1
~
g
o
! '00
I
~,o.o_
~
[
'---
\;
0
0ItIA
-
~
~ l~
B IpAHr+-+--H--+-+/
CURRENT GAIN
VS_ TEMPERATURE
VS_ COLLECTOR CURRENT
"",0
~EVI~E.A~_
~~
S
5
0; _
_
o 010l:0::","-'-J.W~o':"",..J...I"<'u'"'''O---'-.LJ-1JJJ,".!oo,-J---U.WJJ.4
10nA 1000lA I,uA
IO,.,A 100,.,A ImA IOmA
COLLECTOR CURRENT-Ie
COLLECTOR CURRENT- rnA
GAIN-BANDWIDTH
NOISE CURRENT DENSITY
NOISE VOLTAGE DENSITY
VS_ COLLECTOR CURRENT
00.0
1,000
~MAT'Ol
NOISE VOLrAGE DENSITY
.:. 200
~
~
f
~
i
~
~
'0
FREQUENCV(tiIJ
10.000
/
10
" ,
i
~
0.'0'
50
z
il
i
100
t
I
i
'0
If
,
,
0.'
"A
0'
fREQUENCY (Hz)
8-4
-.-
/
~
10.0
l'
~
~
-:i-7
i
T."25"C
/
/
L t--------------
T.'2S "C
Vco "10V
/
,
/
It¥'A
100.... "
ImA
COLLECTOR CURRENT
MAT·01
MAT·01 TEST CIRCUITS
MAT·01 MATCHING MEASUREMENT CIRCUIT
MAT·Ol NOISE MEASUREMENT CIRCUIT
'1l
33Hl
-~
4r,.r .......
........
-=-
'0>
LOW
FREOUENCV
NOISE
HOrSE VOLTAGE DENSITY
(PERTFIANS1STORl
vOI,V2·4/,Hl
NOISf:CUI'tRENTDENSITY
(PEF< TRANSISTO'U
V02 PEAl<"rO-PEAK
LOWFREQUEHCY NOISE
(REFERRE:DTOINPUT
2!\,OOO
APPLICATION NOTES
Application of reverse bias voltages to the emitter-base junctions in excess of ratings (5V) may result in degradation of hFE and hFE
matching characteristics; circuit designs should be checked to insure that such reverse bias voltages cannot be applied during transient
conditions, such as at circuit turn-on and turn-off.
The designer is cautioned that stray thermoelectric voltages generated by dissimilar metals at the contacts to the input terminals CBI11 prevent
realization of the drift performance indicated. Best operation will be obtained when both input terminals are maintained at the same
temperature, preferrably close to the temperature o~ the device's package.
TYPICAL APPLICATIONS
PRECISION OPERATIONAL AMPLIFIERS
PRECISION REFERENCE
t----~---<>VREF
+
• MATCH TO 0.1%
4* SEE TABLE FOR SPECIFIC DEVICE TYPE
V"f.,Jl:1.0V
TCV",IIOIIOppm/·C
I
~x
GAIN MIN
II.
R
MAT-OIAH MAT-OfAH MAT-OIGH MAT-OIGH
558741
SSS741C SSS141C
5SS74
1.2mV
O.l5mV
0.27mV
065mV
.6JlVl-C
o.SnA
20nA
000
2o,.A
100110
02
2~v/·C
'JlW-C
O.lnA
3.2nA
2nA
40nA
000 800000
2#A
20#A
100kn
1M"
Ro=40n
4p.vrc
R,mG), be adjU5tedfo minimize
O.32nA
4nA
rcv",
Increasing R,will cause a positive
chang, in TCVIlI,
800.000
2#A
IMn
Note' hfE of Qt will be reduced by
operation in breakdown mode.
8·5
I
MAT·01
CROSS REFERENC~ - MAT·01 TO MONOLITHIC DUAL TRANSISTORS (lC = 10W\)
BVCEO
MIN
(V)
DEVICE
Vos
MAX
(mV)
TCVos
MAX
(MVrC)
hFE
MIN
los
MAX
(nA)
TClos
MAX
(pArC)
90
MAT·01AH
45
0.1
0.5
500
0.6
MAT·01H
0.1
0.5
330
0.8
110
MAT·01FH
60
61);
0.5
1.8
250
3.2
150
MAT01GH
45
0.5
1.8
250
3.2
150
LM114A
45
0.5
2.0
500
2.0
LM114
45
10
60
10
2_0
250
LM115A
2.0
0_5
250
2.0
LM115
60
2_0
10
250
10
--_.-----
AD810
35
3_0
15
100
2.0
600
AD811
45
1_5
7_5
200
300
AD812
35
5_0
400
AD813
45
1.0
0_5
10
2_5
2_5
200
5
300
AD818
20
1.0
5_0
200
10
300
j
{
300
CROSS REFERENCE - MAT·01 TO 2N TYPES (lc = 10MA)
TClos
MAX
(pArC)
BVCEO
MIN
(V)
Vos
MAX
(mV)
TCVos
MAX
I!NrC)
hFE
MIN
%hFE
MATCH
MAX
los
MAX
(nA)
MAT-01GH
45
0_5
1.8
250
8
3.2
2N2639
45
5_0
10
50
10
20
1000
2N2640
45
20
50
20
40
2000
2N2642
45
10
5_0
10
100
10
10
500
2N2643
45
10
20
100
20
20
375
2N2915
45
3.0
10
17
600
45
60
15
26
2N2916
45
2.0
5_0
10
5_0
60
2N2915A
150
10
7
900
N_C_
2N2916A
45
2_0
10
5_0
150
15
10
300
2N2917
45
20
60
20
17
1450
2N2918
45
10
5_0
20
150
20
7
750
DEVICE
150
"
MAT-01FH
60
0.5
1.8
250
8
3.2
150
2N2919
60
3.0
10
5,0
60
10
17
600
60
10
17
600
10
5,0
150
10
7
N.C.
150
10
7
300
2N2919A
60
1.5
2N2920
60
3.0
2N2920A
60
2N2060
60
1.5
5,0
10
25
10
40
N,C.
2N2060A
60
3.0
5.0
25
10
40
N.C.
2N2060B
60
1.5
5.0
25
10
40
N.C.
Notes:
1. TClos Max and los Max calculated from publ ished data.
2. N.C, = Insufficient published data to calculate.
3. All of the above are physically interchangeable pin-for-pin with MAT-01 series.
8·6
Ii.N.U.M.E.R.IC.A.L.I.N.D.E.X..........~1:][J
I:ORDERING INFORMATION
rn
~ rn
rn
;li;Q;.A;.;PR;O;G;R;A;M;;;;;;;;;;;;~~
;I.;IN.D.U.S.T.R.Y.C.R.O.S.S.R.E.F.E.R.E.N.C.E..
!FUNCTIONAL REPLACEMENT GUIDE
rn
I
tOPERATIONAL AMPLIFIERS
;,i·CO·M·P·A·R·A·T·O·R·S............~I£:ZJ
~I~
rn.
.-...........................I:·;M;A;TC;H;E;D;T;R;A;N;S;IS;T.O.R;S......
VOLTAGE REFERENCES
------------------------~I~D·/·A·C·O·N·V·ER·T·E·R·S·-·L·I·N·EA·R....~~
ID/A CONVERTERS - COMPANDING IT!]
I,MULTIPLEXERS
£rn
I;!D;E;F;IN;IT;IO;N;S;;;;;;;",;_;;;;;;~
ICHIPS
mJ
lliJ
1·;A;PP;L;IC;A;T;IO;N;;NO;T;E;S;,;;;;;;;;~[j]D
I'I>ACKAGE INFORMATION
IPNii i iOi i i TEii i iS;;;;;;;;;;;;;;;;;;;;;;;;~
[i§]
1m
INDEX
VOLTAGE REFERENCE
PRODUCT
TITLE
REF-01
REF-02
+10V Precision Voltage Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
+5V Precision Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE
9-1
9-8
PMI
IREF-011
+ IOV
PRECISION VOLTAGE REFERENCE
GENERAL DESCRIPTION
FEATURES
The REF-01 Precision Voltage Reference provides a stable
+1OV output wh ich can be adj usted over a ±3% range with
minimal effect on temperature stability. Single supply operation over an input voltage range of 12 to 40V, low current
drain of 1mA, and excellent temperature stability are achieved
withan improved bandgap design: Low cost, low'noise and low
power make the REF-01 an excellent choice whenever a stable
voltage reference is required, such as in D/A and ND converters, in portable instruments, and in digital voltmeters. Full
military temperature range devices with screening to MILSTD-883A are available.
_
_
_
Adjustable 10 Volt Output . . . . . . . . . . . . . . . ±3%
Excellent Temperature Stability ........ 3 ppm/o C
Low Noise .. _ . . . . . . . . . . . _ . . . . . . . 20J.lVp-p
_
_
_
_
_
Low Power
. . . . . . . . . . . . . . . • . . . .. 15mW
Wide Input Voltage Range ....•..•... 12 to 40V
High Load Driving Capability. . . . . . . . . .. 20mA
No External Components
Short Circuit Proof
_
MI L·STD·883A Screening Available
PIN CONNECTIONS AND ORDERING INFORMATION
SIMPLIFIED SCHEMATIC
TOP VIEW
Ne
8
INPUT
QI9
4
GROUND
.Jrrent
ISC
Vo =
a
1.4
rnA
21
-
10
21
-
rnA
-0.3
-0.5
-
-0.3
-0.5
-
rnA
3l
-
-
3l
-
mA
-
The following specifications apply for VIN = +15V, _55 C ~ TA
0
Output Voltage Change
with Temperature
AVOT
INotes 1 and 2)
Output Voltage
Temperature Coefficient
Change in Va Temperature
Coefficient with Output
Adjustment
Una Regulation
TCVO
IVIN = 13 to 33V)
I Note 4)
EO;
-
10
(
Sink CUrrent
,usee
5.0
1.0
+125"C and IL = OmA,unless otherwise noted.
O'·"TA" +70° C
-
0.02
0.06
-
_55' "TA" +125' C
-
0.06
0.15
-
8.5
-
-
-
0.7
0.07
0.18
0.17
0.45
%
%
-
3
Ap = 10kn
-
0.7
0""TA,,+70"C
-
0.007
0.012
-
0.007
0.012
%/V
(Note 3)
10
25
-
pprn/'C
.ppm/'C/%
-55'"TA,,+125°C
-
0.009
0.015
-
0.009
0.015
%/V
Load Regu lation
O'"TA" +70' C
0.006
0.010
-
0.007
0.012
%/mA
ilL = a to SmA)
INote4)
-
-55°
0.1 Hz to 10Hz (Note 5)
Input Voltage Range
VIN
Min
9.97
±3.0
Typ
Max
10.00
10.03
±3.3
-
-
20
30
12
-
40
0.006
0.010
%/mA
5.0
-
1.0
1.4
No Load
-
1.0
1.4
Loaa Current
IL
VO=O
-
V
-
ISV
IS
I'VPi>
-
Qu iescent Current
ISC
40
0.008
-
Short Circuit Current
30
-
0.005
5.0
-0.3
%
20
%IV
-
-
-
±3.3
Units
0.010
IL=Otol0mA
Sink Current
V
0.006
To ±0.1% of final value
10
12
Max
10.05
-
ton
Load Regulation (Note 41
±3.0
Typ
10.00
0.010
Turn·on Settling Time
VIN = 13 to 33V
9.95
0.006
-
Line Regulation {Note 41
Min
21
-0.5
30
-
10
21
-0.3
-0.5
-
30
-
~sec
mA
mA
mA
mA
The following specifications apply for VIN = +15V, O'C <: TA <: +70'C and IL = OmA,unless otherwise noted.
Output Voltage Change
with Temperature
Output Voltage
Temperature Coefficient
AVOT
{Notes 1 and 21
-
0.02
0.06
-
TCVO
(Note 3)
-
3
8.5
-
Rp = 10kn
-
0.7
-
-
0.7
-
0.007
0.012
%IV
0.007
0.012
%/mA
0.07
10
0.17
25
%
ppml'C
Change in Vo
Temperature Coefficient
-
ppmfC/%
With Output Adjustment
Line Regulation (Note 41
VIN = 13 to 33V
-
0.007
0.012
Load Regulation (Note 4)
IL =Ot08 mA
-
0.006
0.010
NOTE 1:
Il. VOT is defined as the absolute difference between the maximum output voltage and the minimum output voltage over the
specified temperature range expressed as a percentage of 10V:
AVOT=
VMAX -VMIN
10V
X 100
NOTE 2:
AVOT specification applies trimmed to +10.000V or untrimmed.
NOTE 3:
TCVO is defined as AVOT divided by the temperature range; i.e., TCVO =
NOTE 4:
Line and Load Regulation specifications include the effects of self heating.
NOTE 5:
Parameter is not 100% tested; 90% of units meet this specification.
9-3
~~?;
I
REF-01
OUTPUT ADJUSTMENT
12+15V
The REF-Ol trim terminal can be used to adjust the output
voltage over a 10V ±300mV range. This featura allows the
system designer to trim system errors by setting the reference
to a voltage other than 1OV. Of course, the output can also
be set to exactly 10.000V, or to 10.240V for binary
VIN
Vo
6
'""'OUTPUT
REF-OI
applications.
~
TRIM 5
GRD
Adjustment of the output does not significantly affect the
temperature performance of the device. Typically the temper·
ature coefficient change is 0.7 ppmtC for 100mV of output
adjustment.
IOKQ
4
-=.:ELECTRICAL CHARACTERISTICS
REF·Q1e
REF·01D
These specifications apply for VIN = +15V, TA = 25°C, unless otherwise noted.
Symbol
Parameter
Output Voltage
Test Conditions
Vo
IL = OmA
Output Adjustment Range
/l.Vtrim
Rp = 10kll
Output Voltage Noise
enp-p
O.lHz to 10Hz (Note 5)
Input Voltage Range
VIN
Min
9.90
±2.7
12
Typ
Max
Min
10.00
10.10
9.850
±3.3
25
-
-
±2.0
35
-
30
12
Line Regulation (Note 41
VIN=13t030V
-
0.009
0.015
-
Load Regulation (Note 41
IL=Oto8mA
-
0.006
0.015
-
IL=Ot04rriA
-
-
-
-
ton
To ±0.1% of final value
-
5.0
-
Quiescent Current
ISY
No Load
-
1.0
1.6
-
Load Current
IL
Sink Current
IS
Short Circuit Current
ISC
Load Regulation (Note 41
Turn~on
Settling Time
8
-0.2
VO~O
-
21
-0.5
30
-
8
-0.2
-
Typ
10,00
±3.3
25
0.012
0.009
Max
10.150
-
Units
Ii
%
}lVp-p
V
30
0.04
%IV
-
%/mA
0.04
%/mA
5.0
-
1.0
2.0
mA
-
mA
-0.5
-
mA
30
-
mA
-
%
-
ppm/DC
21
}lsec
The following specifications apply for VIN = +15V, O°C <; T A <; +70°C, unless otherwise noted.
Output Voltage Change
with Temperature
/l.VOT
(Notes 1 and 2)
-
Output Voltage
Temperature Coefficient
TCVO
(Note 3)
-
~
0.14
20
0.45
65
-
0.49
70
Change in Vo
Temperature Coefficient
With Output Adjustment
Rp
10k!}
-
0.7
-
-
0.7
-
ppm/%
Line Regulation (Note 4)
VIN = 13 to 30V
-
0.011
0.018
-
0.008
0.018
0.020
-
%IV
IL=Ot05mA
-
0.020
Load Regulation (Note 4)
NOTE 1:
AVOT is defined as the absolute difference between the maximum output voltage and the minimum output voltage over the
specified temperature range expressed as a percentage of 10V:
/l.VOT=
VMAX-VMIN
10V
X 100
NOTE 2:
/l.VOT specification applies trimmed to +10.000V or untrimmed.
NOTE 3:
. d as /l. V OT divided
. .
.
TCV 0 = /l.VOT
TCVO .IS define
by the temperature range; I.e.,
700.C
NOTE 4:
line and Load Regulation specifications include the effects of self heating.
NOTE 5:
Parameter is not 100% tested; 90% of units meet this specification.
9-4
%/mA
REF-01
TYPICAL P6RFORMANCE CURVES
OUTPUT WIDEBAND
NOI$E VS BANDWIDTH
C.1 Hz TO FREQUENCY INDICATED)
OUTPUT CHANGE DUE
TO THERMAL SHOCK
LINE REGULATIQN
VSFREQUENCY
7Or-rTT1T111I-rrrnmrTTmnrmmnm11llr°.oo31
L
YlN-'SV
TA*
TA-
2S·C 15*C
i
rI
~
~ 0.010
i
,
5~ 40 f-H-I#IIII-+11+HIII-+l+llIjif--H-I-fHIIH'I.+fttllto,1
~~
1/
0.015
0.0015
~
30
"
HORT CIRCUIT
..
20
f-H-Il11tttHH++H!li~~+t++ttIIH+~'"
o +-l.U.~....l..J.WWI(.....u.ll1llll-Ul~>-J..wl!lq.,O.O
30
40
50
10Hz
60
flIHz
toItHz
FREQUENCY
tOOHz
NORMALIZED LOAD
REGULATION CAlL = 10mA)
VS TEMPERATURE
V
20
15
/
I
10
5oo.wb
/
DISSIPATION
/
V
5
20
25
INPUT VOLTAGE-VOLTS
V
,,/'
V
-
V'N"'!:!V
.
-60
30
,
-
V
........
I .......
20
40
60
80
100
l20
o
140
TEFIIPfRATURE-oC
20
40
&0
TEWERATURE-OC
QUIESCENT CURRENT
VS TEMPERATURE
MAXIMUM LOAD CURRENT
VS TEMPERATURE
0
/
:-.....
r--- ........
0
//
.........
,
VIN
I
r---
.,'"
i'-
·'~V
....- V
y
.
vIN"!lV
o
-60
I
/
V
TA=25-<:
15
IMHI
NORMALIZED LINE REGULATION
VS TEMPERATURE
/
0
10
IOOlHr
~CT1Cl1
/'
20
040
60
80
100
120
~
;;;:
TA*25--4-o-IOV
5KA
CURRENT SOURCE
CURRENT SINK
+15V
lOUT
2
2
VIN
Vo 6
Vo 6
REF-OI
TRIM 5
REF-OI
R lOUT' IOROV +lmA
TRIM 5
GRD
4
G
4
lOUT
IO.OV
R lOUT =-R-+ lmA
-15V
VOLTAGE COMPLIANCE:-3V TO+25V
VOLTAGE COMPLIANCE: -2!5V TO+3V
9-6
REF-01
TYPICAL APPLICATIONS
PRECISION CURRENT SOURCE
A current source with 25V output compliance and excellent
output impedance can be obtained using this circuit.
AE F-I>1 @ keeps the line voltage and power dissipation
constant in device
the onlv important error consideration at room tel1'!perature is the negative ~upply. rejection of the
op amp. The typical 3"V!V PSAA of the OP-02E will create
on B ppm change (3"V IV X 25V!10VI in output current over
s 25V range; for example, a 10mA current source can be
built (A = 1/:'. with 302~:n out)Put impedance·
CD ;
GRD
4
2
\: 0 = Bxl0-6xl0mA
R (TRIM FOR
CALIBRATIONI
6~p!1I_ _ _",,_ _-oVo'OTO 25V
b~~
RC.tO-5 SEC
10'
t~V
REFERENCE STACK WITH EXCELLENT LINE REGULATION
tll2
Three AEF-Ol's cen be stacked to yield 10.000,20.000 and
3O.OO0V outputs. An additional advantage is near-perfect
line ragulation of the 10.000 and 20.000 output voltages. A
32V to 60V input change produces an output change which
is less than the noise voltage of the devices. A load bypass
resistor (ABI provides a path for the supply current (lSyl of
the 20.OOOV regu lator.
VIN
TO IOV
TRIMMED
OUTPUTS
Vo il
J'\ lIO.000V
REF-Ot
tOKA
TRIM 5
GRD
4
In generel any number of AEF-Ol's can bestackad this way.
For example. ten devices will yield outputs of 10,.20, 30, ...
lOOV. The line voltage can range from 105 to 130V. However, care must be taken to ensure that the total load currents
do not excead the maximum usable current (typically 21 mAl.
2
VIN
2O.000V
Vo'
REF-01
2
VIN
TRIM
GRD
4
Vo
REF-O!
TRIM
GRD
4
h
10KA
•
""'0.000 V
5
tOKA
'.8KD.
Re
*
9-7
I
PMI
IREF-02i
+5V PRECISION VOLTAGE REFERENCE/THERMOMETER
GENERAL DESCRIPTION
FEATURES
The REF-02 Precision Voltage Reference provides a stable
+5V output which can be adjusted over a ±6% range with
minimal effect on temperature stability. Single supply operation over an input voltage range of 7V to 40V, low current
drain of 1mA, and excellent temperature stability are achieved
with an improved bandgap design. Low cost, low noise and
low power make the REF-02 an excellent choice whenever a
stable voltage reference is required, such as in DIA and AID
converters, in portable instruments, and in digital voltmeters.
The versatility of the REF-{)2 is illustrated by its use as a
monolithic thermometer. (See AN-1B, "Thermometer Applications of the REF-02.") For +10V Precision Voltage References see the REF-01 data sheet.
•
_
Temperature Voltage Output . . . . . . . , 2.1 mVtC
Adjustable 5 Volt Output . . . . . . . . . . . . . . . ±6%
•
•
_.
_
Excellent Temperature Stability . . . . . . . 3 ppmfC
Low Noise . . . . . . . . . . . . . . . . . . . . . . 10IlVp-P
Low Power . . . . . . . . . . . . . . . . . . . . . . . 15mW
Wide Input Voltage Range . . . . . . . . . . . 7V to 40V
•
High Load Driving Capabilitv . . . . . . . . . . . . 20mA
•
•
•
No External Components
Short Circuit Proof
MIL·STD·883A Screening Available
PIN CONNECTIONS AND ORDERING INFORMATION
SIMPLIFIED SCHEMATIC
INPUT
V1N 2
6VOUT
Q"
4
GROUND
CASE
TO-99 (J-Suffix)
ORDER: REF·02AJ
REF-02J
REF-02EJ
REF-02HJ
REF-02CJ
REF-02DJ
Military Temperature Range Devices
lRIM
with MIL-STD-883A Class B Processing:
R'
GROUND
9-8
ORDER: REF02-883-AJ
REF02-883-J
REF-02
ABSOLUTE MAXIMUM RATINGS
Input Voltage REF-02. A. E. H
40 V
REF-02C. D
Operating Temperature Range
30V
Power Dissipation (see note)
-5SoC to +12SoC
REF-02A. REF-02
500mW
Output Short Circuit Duration
REF-02E. REF-02H
REF-02C. REF-02D
Indefinite
(to ground or VIN)
Storage Temperature Range
-6SoC to +150°C
Note:
Derate at
300°C
Lead Temperature (Soldering. 60 sec)
O°C to +70°C
7.1mwfc above BO°C ambient
temperature.
ELECTRICAL CHARACTERISTICS
REF-02A
REF-02
These specifications apply fore VIN :::: +15V, TA = 25°C. unless otherwise noted.
Symbol
Parameter
Test Conditions
~OmA
Output Voltage
Vo
IL
Output Adjustment Range
~Vtrim
Rp
Output Voltage Noise
enp~p
O.lHz to 10Hz
(Note 1)
Input Voltage Range
VIN
Line Regulation
~
Min
Typ
4.985
10kn
±3.0
-
5.000
Max
Min
5.015
4.975
-
±6.0
10
15
-
40
7
±3.0
-
Typ
5.000
Max
Units
5.025
V
-
±6.0
10
15
-
40
7
j.lVp-p
V
8 to 33V
-
0.006
0.010
-
0.006
0.010
%/V
IL~Otol0mA
-
0.005
0.010
-
0.006
0.010
%/rnA
~
VIN
(Note 2)
Load Regulation
(Note 2)
%
Turn·on Settling Time
ton
To ±O.1% of final
value
-
5.0
-
-
5.0
-
J..tsec
Qu,iescent Current
ISY
No Load
-
1.0
1.4
-
1.0
1.4
mA
Load Current
IL
-
mA
Sink Current
IS
10
ISC
Vo
Temp Voltage Output
VT
(Note 3)
-
aVOT
with Temperature
(Not.sA and 5)
Output Voltag.
TCVO
21
-0.5
-
-0.3
30
-
-
630
.-
The following specifications apply for VIN ~ +15V, _55" C <; T A <; +125° C aryd JL
Output Voltage Chang.
10
-
-0.3
~O
Short Circuit Current
21
=
-
mA
30
-
mA
630
-
mV
-0.5
OmA. unless Qtherwise noted.
Q°",;;TA.;,;;;:+70°C
-
0.02
0.06
-
-55" <;TA<;+125"C
-
0.06
0.15
-
8.5
-
--
-
0.7
(Note 6)
-
3
-
0.7
0.07
0.17
0.18
0.45
10
%
%
ppmtC
25
Temperature Coefficient
Change in Va Temperature
Coefficient with Output
Adjustment
Rp
Line Regulation
0°<;TA<;+70"C
-
0.007.
0.012
-
0.007
0.012
%iV
(YIN ~ 8 to 33V)
(Note 2)
_55° <;T A<;+125°C
-
0.009
0.015
0.009
0.015
%/V
0°<;TA<;+70"C
-
0.006
0.010
-
0.007
0.012
%/mA
-55°<;T A<;+125"C
-
0.007
0.012
-
0.009
0.015
%/mA
-
2.1
-
2.1
Load Regulation
(lL ~ Oto 8mA)
(Not. 2)
Temp Voltage Output
TCVT
~
10kn
(Not. 3)
Temperature Coefficient
(
-
-
-
ppmfC/%
mVtC
NOTE 1:
Parameter is not 100% tested; 90% of units meet this specification.
NOTE 2:
Line and Load Regulation specifications include the effects of self heating.
NOTE 3:
Limit current in or out of pin 3 to SOnA and capacitance on pin 3 to 30pF.
NOTE 4:
AVOT is defined as the absolute difference between the maximum output voltage and minimum output voltage over the specified
temperature range expressed as a percentage of 5V:
aVOT~
VMAX-VMIN
5V
X 100
NOTE 5:
AVOT specification applies trimmed to 5.000V or untrimmed.
NOTE 6:
TCVO is defin.d as aVOT divided by the temperatijr. range; i .•.• TCVO (00 to +70°CI
and TCVO (_55° to +125°C)
~
aVOT _55° to +125°C
180°C
9-9
~
aVOT 0° to +70°C
70°C
I
REF-02
REF-02 [)EFINITIONS
LINE REGULATION
The ratio of the change in output voltage to the change in line
voltage producing it.
OUTPUT VOLTAGE NOISE lenp_p)
The peak to peak output noise voltage in a specified frequency
band.
LOAD REGULATION
The ratio of the change in output voltage to the change in load
current producing it.
OUTPUT CHANGE WITH TEMPERATURE (.:).VOTI
The absolute difference between the maximum output voltage
and the minimum output voltage over the specified temperature
range expressed as a percentage of 5V:
VMAX-VMIN
X 100
4VOT=
5V
QUIESCENT CURRENT IISY)
The current required fram the supply to operate the device
with no loed.
OUTPUT TURN-ON SETTLING TIME Itonl
OUTPUT TEMPERATURE COEFFICIENT ITCVOI
The ratio of the output change with temperature to the specified
The time required for the output voltage to reach its final value
within a specified error band after application of VIN
temperature range expressed in ppmf c.
ELECTRICAL CHARACTERISTICS
REF-02H
REF-02E
These specifications apply for VIN = +15V, TA = 25°C, unless otherwise noted.
Parameter
Symbol
Test Conditions
Output Voltage
Vo
Output Adjustment Range
.:).Vtrim
Rp= 10kn
Output Voltage Noise
enp_p
0.1 Hz'to 10Hz
INote 11
Input Voltage Range
VIN
Line Regulation (Note 2)
Load Regulation INote 21
Turn-on Settling Time
IL =OmA
Min
Typ
Max
Min
Typ
Max
4.985
5.000
5.015
4.975
5.000
5.025
V
-
%
±3.0
-
-
±6.0
10
-
7
±3.0
,
15
40
-
±6.0
10
j,lVp-p
15
-
7
40
V
VIN=8to33V
-
0.006
0.010
-
0,006
0.010
IL =Oto 10mA
-
0.005
0.010
-
0.006
0.010
5.0
-
1.0
1.4
ton
To ±0.1% of final value
Quiescent Current
ISY
No Load
Load Current
IL
10
21
Sink Current
IS
-0.3
-0.5
Short Circuit Current
ISC
VO=O
Temp Voltage Output
VT
(Note 31
-
-
30
630
5.0
-
1.0
1.4
10
21
-0.3
-0.5
-
30
-
630
Units
-
%IV
%/mA
,""sec
mA
mA
mA
mA
mV
The following specifications apply for VIN = +15V, O°C .. TA" +70°C and I L = OmA, unless otherwise noted. i
Output Voltage Change
with Temperature
4VOT
INptes 4 and 51
-
0.02
0.06
-
Output Voltage
Temperature Coefficient
TCVO
INote 61
-
3
8.5
-
Change in Vo Temperature
Coefficient With Output
Adjustment
Rp = 10kn
-
0.7
-
-
0.")
Line Regulation (Note 21
VIN=8to33V
0.012
0 ..012
%IV
0.006
0.010
-
0.007
IL=Oto8mA
-
0.007
Load Regulation (Note 21
0.007
0.012
%/mA
(Note 31
-
2.1
-
'-
2.1
-
mVi"C
Temp Voltage OutP.ut
Temperature Coefficient
NOTE 1:
TCVT
0.07
10
0.17
25
ppmi"C
-
Parameter is not 100% tested; 90% of units meet this specification.
NOTE 2:
Line and Load Regulation specifications include the effects of self heating.
NOTE 3:
Limit current in or out of pin 3 to 50nA and capacitance on pin 3 to 30pF.
NOTE 4:
AVOT is defined as the absolute difference between the maximum output voltage and the minimum output voltage over the
specified temperature range expressed as a percentage of 5V:
4VOT=
VMAX-VMIN
5V
X 100
NOTE 5:
.:).VOT specification applies trimmed to +5.oo0V or untrimmed.
NOTE 6:
TCVO is defined as .:).VOT divided br the temperature range; i.e., TCVO =
9-10
~~?;
%
ppm/%
AEF-02
OUTPUT ADJUSTMENT
BURN-IN CIRCUIT
The REF-02 trim terminal can be used to adjust the output
1;'5V
voltage over a 5V ±300mV range. This feature allows the
system designer to trim system errors by setting the reference~
to a voltage other than 5V. Of course, the output can also be).
V,N
set to exactly 5.000V, or to 5.12V for binary applications.
REF-02
Adjustment of the output does not significantly affect the
temperature performance of the device. Typically the temper·
Vo
~
2~_18V @ 125'C
6
OUTPUT
~
OUTPUT
REF-02
101<..
EMP TRIM 5
GRD
t
ature coefficient change is 0.7 ppmfC for 100mV of output
adjustment.
,l
*
ELECTRICAL CHARACTERISTICS
REF-02C
REF-02D
These specifications apply for VIN = +15V, T A = 25°C, unless otherwise noted.
Symbol
Parameter
Test Conditions
Output Voltage
Vo
IL = OmA
Output Adjustment Range
.6.V tr im
Rp = 10k1l.
Output Voltage Noise
enp·p
O.lHz to 10Hz (Note 1)
Input Voltage Range
VIN
Min
4.950
±2.7
7
Typ
5.000
Max
Min
5.050
4.900
-
±6.0
12
18
-
30
-
VIN=8t030V
Load Regulation (Note 2)
IL = 0 to 8 mA
-
Load Regulation (Note 2)
IL = 0 to 4 mA
-
-
-
5.0
-
1.0
1.6
Turn-on Settling Time
ton
To ±0.1% of final value
ISY
No Load
Load Current
IL
Sink Current
IS
Short Circuit Current
ISC
VO=O
Temp Voltage Output
VT
(Note 3)
8
0.009
0.Ol5
0.006
0.015
-0.5
-
30
-
630
-
21
-0.2
-
-
-
5.000
8
-
5.100
-
12
0.010
0.015
30
Units
V
%
.uVp·p
V
0.04
%/V
-
%/mA
0.04
%/mA
5.0
-
1.0
2.0
mA
-
mA
21
-0.2
Max
±6.0
-
7
Line Regulation (Note 2)
Qu iescent Current
±2.0
Typ
-0.5
30
630
.usee
mA
mA
mV
The following specifications apply for VIN = +15V, O°C .. TA .. +70°C and IL = OmA,unless otherwise noted.
Output Voltage Change
with Temperature
o
>
X
~ 10
I
/
/'
"
1::::>
V
/
500mW ...
DISSIPATION
/
L/
1.2
/
V
TA'25"C
V
-
.......
VIN'15V
./
L
V
/'
V
/'
o
5
15
20
INPUT VOLTAGE-vOLTS
25
,
_
_
~
0
m
w
w
~
~
_
_
,
·60
·40
-20
0
LINE REGULATION
VS SUPPLY VOLTAGE
\
\
.
MAXIMUM LOAD CURRENT
VS TEMPERATURE
._I,
"
'"
.
,
5
-60
-40
80
100
i'-..
.........
-20
0
..
INPUT VOLTAGE_VOLTS
9-12
V
.
..........
.........
20
60
120
140
QUIESCENT CURRENT
VS TEMPERATURE
1.0
'---
60
'.2
'lIN "'5'1
,
40
I.'
...N
TA " 2 5 C _
20
TEMPERATURE·"C
TEMPERATunE-OC
ao
'00
... ...
.... v
L.
V
,/
v
V
Y'N*'5\'
.7
-60
-40
-20
0
20
40
60
TEMP~RAT~E-·C
80
tOO
120
I
,
1.0
II
~
~
0.'
:.--
g
140
AEF-02
TYPICAL APPLICATIONS
PRECISION TEMPERATURE TRANSDUCER WITH REMOTE SENSOR
C)
Ra
Rc
A
vA./v
vv
6
+1SV
V REF
Vo r----+----ir--'-'=--e
REF-02
6
.. < Rp
TRIM t-S"---------ic--------i------iK
< 50Kn
I
*UP TO 10 FEET OF SHIELDED 4-CONDUCrOR CABLE.
TYPICAL TEMPERATURE VOLTAGE
OUTPUT VS TEMPERATURE
(REF-02A)
88'
I
-
830
VJN~
V
730
...
V
/V
/
630
580
530
V
430
-60
...,
L
/
1/
-20
TCVOUT SLOPE (S)
10mVfC
l00mVI"C
10mVfF
TEMPERATURE
RANGE
_55 0 to
+125°C
-55° to
+125°C
-S7°F to
+257°C
OUTPUT VOLTAGE
RANGE
-O.55V to
+1.25V
-5.5V to
+12.5V·
-O.S7V to
+2.57V
ZERO SCALE
OV@O°C
OV@O°C
OV@O°F
Ra (±1% resistor)
9.09K!"!
15K!"!
7.5K!"!
RbI (±1% resistor)
1.5K!"!
1.B2K!"!
1.21K!"!
Rbp (Potentiometer)
200!"!
500!"!
200!"!
Rc (±1% resistor)
5.11K!"!
B4.5K!"!
B.25K!"!
1,..
15V
".
480
RESISTOR VALUES
.
20
40
TEMPERATURE
80
_·c
.
10'
'20
'40
*For 125°C operation, the op amp output must be able to swing
to +12.5V; increase VtN to +18V from +15V if this is a problem.
FOR THEORY OF OPERATION AND CALIBRATION PROCEDURE CONSULT APPLICATION NOTE AN-lB. "THERMOMETER
APPLICATIO\NS OF THE REF-02."
±5V REFERENCE
:!.2_5V REFERENCE
PRECISION CALIBRATION STANDARD
+1!5V
v;
VI.
REF -02
o..!.
~'~---,-----------o+5V
TRIM~
..,;....!'/t-
IOKA
IOKC
r
~:.
-+l.tmA
l~'Ji
....
'----'-1--<,-'0"'''
9-13
v;
I
REF-02
TYPICAL'APPLICATIONS
CURRENT SOURCE
. VIN
CURRENT SINK
!~OUT
VO~
VIN
VOL-
REF-02
0-1
TRIM~
REF-02
R lOUT = 5f,.0V +lmA
o--l
GRO
TRIM
GRO
4
4
lOUT
~
R lOUT' 5f,.0V +lmA
-15V
VOLTAGE COMPLIANCE:-8V TO 25V
VOLTAGE COMPLIANCE: -25V TO+ 8V
27 TO 55V
REFERENCE STACK WITH EXCELLENT LINE REGULATION
2
VIN
V o I ' 6 ! - - - + - - -.....-----O" 25.000V
REF-Ot
TRIM 1"5'----+-_ _-.(IOKIl
Two REF-Ol's and one REF-02 can be stacked to yield
5.000, 15.000 and 25.0OOV outputs. An additional advantage
is near-perfect line regulation of the 5.000 and 15.000 output
voltages. A 27V to 55V input change produces an output
GRO
4
change which is less than the noise voltage of the devices. A
2
load bypass resistor (RB) provides a path for the supply
current (lSY) of the 15.OOOV regulator.
VIN
In general any number of REF-Ol's and REF·02's can be
stacked this way. For example. ten devices will yield ten
outputs in 5 or 10V steps. The line voltage cen range from
REF-Ot
Vo 6
TRIM
GRO
100 to 130V. However f care must be taken to ensure that the
total load currents do not exceed the maximum usable
15.000V
L.....: 10Kil
4
2
VIN
current (typically 21 mAl.
Vo 6
5.000V
REF -02 5
10Kil
TRIM
GRO
,
6.8KIl
RB
4
PRECISION CURRENT SOURCE
12+ 50V
6
r--'"
VIN
Vo
0
REF- 02
A current source with 35V output compliance and excellent
output impedance can be obtained using this circuit. REF·02
@ keeps the line voltage and power dissipation constant in
device
the only important error consideration at room
temperature is the negative supply rejection of the op amp.
'V+
IMO
IN4148
II
DAC·01
IN4148
~iGWAL {MSB~~§~~~~~~~J
~
INPUT
LSB
APPLICATIONS INFORMATION
FULL SCALE ADJUST -A soon pot from pin 14 to V- can be
used to adjust the full scale output voltage to exactly 1.0 volts in
unipolar mode or 10 to 20 volts p-p in bipolar mode. If no pot is
used, tie pin 14 to V-.
INPUT CODES-The DAC-01 utilizes standard complementary
binary coding for unipolar mode operation (all inputs high produces
zero output voltagel. Complementarv ~ffset binary (bipolar) mode
operation may be implemented by shorting pin 11 to pin 12 (all
inputs high produces negative full scale output voltage). One's complement coding may be implemented by shorting pin 11 to pin 12
and inverting the MSB before entering pin 1 (all other bits are not
inverted). Two's complement coding may be implemented by shorting pin 11 to pin 12, inverting the MSB before entering pin 1, and
injecting approximately S"A into pin 11 (which is at ground poten·
tial) by using the zero scale or bipolar offset adjustment" circuit.
SCALE FACTOR-For +10 volt or ±5 volt outputs, short pin 10
to pin 11 (adjusts the feedback resistor around the output amplified.
For ±10 volt output, leave pin 10 open. Intermediate output voltages
may be obtained by placing a pot between pin 10 and pin 11, but
this will seriously degrade the full scale temperature coefficient due
to the mismatch between the +1150 ppmtC tempco of the diffused
resistors and the pot tempeo.
II
CAPACITIVE LOADS-When driving capacitive loads greater than
50 pF in Unipolar mode or 30 pF in Bipolar mode a 100 pF
capacitor may be placed from pin 11 to ground for added stability.
POWER SUPPLIES-Care should be taken to insure that positive
voltages are not applied to the logic inputs for more than approximately 300ms before the V+ supply is applied. It is also important
that V- not be removed during 'operation. The addition of thr••
clamping diodes (see fig. above) is recommended where random
supply sequences may be encountered. Power supplies should be
bypassed near the package with a 0.11'F disk capacitor. Chip users
should connect the substrate to V~.
LOWER RESOLUTION APPLICATIONS-When less than 6 bits of
resolution is required, tie off unused bits to a vol.tage level greater
than +2.1 volts. The +5 volt logic supply is usually convenient.
10-4
DAC-Ol
ELECTRICAL CHARACTERISTICS
These specifications apply for Vs = ±15V and over the rated operating temperature range unless otherwise noted.
DAC.(Jl
DAC.(J1B
DAC.(J1F
DAC.(J1C
DAC.(J1H
DAC.(J1D
Unipolar
Bipolar
Unipolar
Unipolar
Unipolar
Bipolar
Unipolar
Unipolar
Bipolar
Temperature Range
-55/+125
-55/+125
-55/+125
0/+70
0/+70
0/+70
°c
Nonlinearity 25°C - Max
±0.40
±0.40
±0.40
±0.40
±0.40
±0.78
%FS
Nonlinearity Over Temperature - Max
±0.45
±0.45
±0.45
±0.45
±0.45
±0.78
%FS
Full Scale Tampco - Max
±80
±120
±80
±160
±160
±160
ppmtC
Unipolar Zero Scale Output
Voltage - Max (Note 1, 2)
25
25
40
25
40
50
mV
Parameter
Output Options
Units
Bipolar
These specifications apply for all DAC-01 grades, Vs = ±15V and over the rated operating temperature range unless otherwise noted.
Conditions
Min
TYR
Max
Units
2KfI load, logic .. 0.5V, short pin 13 to pin 14.
Short pin 12 to Ground and pin 10 to pin 11.
+10.00
-
+11.75
Volts
-
Parameter
Unipolar Full Scale
Output Voltage (Note 3)
Bipolar Output Voltage (Note 3)
±5 Volt Range
2KfI Load, Short pin 11 to pin 12.
Short pin 13 to pin 14, Short pin 10 to pin 11 .
. VFS+
Logic Inputs .. 0.5V
+4.93
VFS-
Logic Inputs .. 2.1 V
-6.94
±10 Volt Range
Open pin 10
+5.94
Volts
"-
-4.93
Volts
VFS+
Logic Inputs .. 0.5V
+9.86
-
+11.89
Volts
VFS-
Logic Inputs .. 2.1 V
-.11.89
-
.!g.B6
Volts
Bipolar Offset Voltage (Note 1)
±1/2 (I VFS+ I-I VFS-I)
-
±5 Volt Range
±10 Volt Range
Resolution
-
Logic Input "0"
-
Logic Input "1"
2.1
Logic I nput Current, Each Input
Power Supply Sensitivity
±12V .. VS" ±IBV
VFS"" 10.0V
Power Consumption
Settling Tim~ to ±1/2 LSB
2.1 V .. logic level .. 0.5V TA = 25°C.
,±40
±BO
-
-
2.2
-
±0.01
-
200
1.5
HO
±140
mV
mV
6
bits
0.5
Volts
-
Volts
B
±0.15
/.lA
%VFSIV
250
mW
3
p.sec
NOTES:
1. Zero scale or bipolar offset vo;ltage can be trimmed to zero volts or to the exact one's or two's complement condition with an external
n.~ork to pin 11.
re~i5tor
2. Logic input voltage .. 2.1 volts.
3. Full scale is adjustablE; to precisely 10 volts for unipolar operation and 10 volt or 20 volt POp bipolar operation with an external 500 ohm
potentiometer from pin 14 to V_.
10-S
I
PMI
DAC-02
®
10 BIT PLUS SIGN MONOLITHIC D/A CONVERTER
GENERAL DESCRIPTION
FEATURES
The DAC-02 is a complete 10 bit plus sign D/A converter on a
single 82 x 148 mil monolithic chip. All elements of a complete
sign/magnitude DAC are included-precision voltage reference,
current steering logie, current sources, R-2R resistor network,
logic controlled polarity switch and high speed internally compensated output op amp. Monoton icity guaranteed over the
O°C to +70°C temperature range is achieved by the untrimmed
diffused R-2 R resistor ladder network. The buffered reference
input is' capable of tracking over a wide range of voltages,
increasing application flexibility. The wide power supply
range, low power consumption, choice of full scale output
voltages and sign/magnitude coding assure utility in a wide
range of applications including CRT displays, data acquisition
systems, A/D converters, servo positioning controls, and voice
and music digitizing and reconstruction systems.
_
Complete ...... Includes Reference and Op Amp
_
Compact
_
Bipolar Output
_
Monotonicity Guaranteed
. . . . . . . . . . Single 18 Pin DIP Package
Sign/Magnitude Coding
_
Nonlinearity
_
Fast . . . . . . . . . . . . . . . . . 1.5 Ilsec Settling Time
....................
±1 LSB
_
Stable
_
Low Power Consumption .•...•.•• 300 mW Max
. . . . . . . . . Full Scale Tempco 60 ppmfC
_
TTL, DTL, CMOS Compatible Inputs
_
Reliable ....•.. 100% Burned-in 72 Hrs@ +125°C
SIMPLIFIED SCHEMATIC AND PIN CONNECTION DIAGRAM
REFERENCE
OUTPUT
REFERENCE
17
5
INPUT
DIGITAL.
~
.
DIGITAL LOGIC INPUTS
j
MSB I
1
BIT •
•
BIT 3
•
BIT 4
BIT 5
4
5
BIT 6
•
v+
\
BIT 7
BIT 8
7
•
BIT 9
•
BIT 10
,.
,
SIGN .,T
10
l~
Ie-
~
+
11
GROUND
r--
~
I-"'
t-..
Lj' I)' -~' -~'5' -5' ~' L)'5' --~-
1,J _1 .1 .1 J .1.1 .1 1
~~
I.
131
!
ANALOG
OUTPUT
I.
v-
ANALOG GROUND
ORDERING INFORMATION
MODEL
DAC-02 ACXl
DAC-02 seXl
DAC-02 CCXl
DAC-02 DDXl
(or X2)*
(or X2)'
(or X2)'
(or X2)*
MONOTONICITV
10 BITS
9 BITS
8 BITS
7 BITS
FSTEMPCO
TEMP RANGE
60 ppmfCMAX
0° /+70°C
0° /+70°C
00/+70°C
0° /+70°C
60 ppm/'C MAX
60 ppm/'C MAX
150 ppml'C MAX
'Suffix Xl indicates ±10V out; suffix X2 indicates ±5V out.
10-6
PACKAGE
HERMETIC
HERMETIC
HERMETIC
HERMETIC
18
18
18
18
PIN
PIN
PIN
PIN
DIP
DIP
DIP
DIP
DAC-02
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
Storage Temperature Range
V+ Supply to Analog Ground
V- Supply to Analog Ground
Analog Ground to Digital Ground
logic Inputs to Digital Ground
O°C to +70°C
-65°C to +150°C
Internal Reference Output Current
300J.lA
Reference Input Voltage
to +10V
Internal Power Dissipation
500mW
lead Soldering Temperature
300°C (60 sec)
Output Short Circuit Duration
Indefinite
(Short circuit may be to ground or either supply.
o
o to +18V
o to -18V
o to ±0.5V
-5V to (V+ - .7V)
E lECTR ICAl CHARACTER ISTICS
These specifications apply for
Vs =
±15V and over the O°C to +70°C temperature range, unless otherwise specified.
GRADES AC, BC, CC
Parameter
Resolution
Monotonicity
(See Note 1)
Nonlinearity
(See
Note 1)
Settling Time
Full Scale Tempco
Full Scale Tempco
Condition
Bipolar Output
Unipolar Output
O"c to 70°C
Grade AC
Grade BC
Grade CC
Grade DO
O°C to 70°C
Grade AC
Grade BC
Grade CC
Grade DO
To ±1/2 LSB, 10 Volt Step
Typ
Max
Min
Typ
Max
11
10
11
10
11
10
11
10
11
10
11
10
10
9
8
-
-
-
-
-
7
-
Total, Internal Reference Connected
External Reference
Reference Input Bias Current
Reference Input Impedance
Reference Input Slew Rate
Reference Output Voltage
Zero Scale Offset
Zero Scale Symmetry
GRADE DD
Min
Sign Bit High, All Other Logic Inputs Low
X2 Models (±5V Full Scale)
Xl Models (±10V Full Scale)
Full Scale Bipolar Symmetry (See Definitions) (See Note 2)
Power Supply Sensitivity
Vs = ±12V to ±IBV
~ower Dissipation
IOUT= 0
Logic I nput Current
Each Input, -5V to (V+ - .7V)
Logic Input "0"
Logic Input "1"
Full Scale Output Voltage
(See Note 3)
±10 Volt Model,s
VFS+ (Sign Bit High)
VFS_ (Sign Bit Low)
±5 Volt Models
VFS+ (Sign Bit High)
VFS_ (Sign Bit Low)
-
-
1.5
±0.1
±0.1
±0.2
-
-
±60
±30
-
100
200
1.5
6.7
+5
±1
+1
±30
±0.015
225
1
-
2.0
-
+10.0
-11.5
+5.00
-5.75
-
-
-
-
O.B
-
-
2.0
+10
±2.5
±5
±60
±0.05
300
-
1.5
±30
100
200
1.5
6.7
+5
±1
±1
±3O
±0.Q15
225
1
+11.5 +10.0
-10.0 -11.5
+5.75 +5.00
-5.00 -5.75
±0.4
+150
-
+10
i5
±10
±80
±0.1
350
-
-
O.B
-
+11.5
-10.0
+5.75
-5.00
-
NOTE 1: This parameter is 100% tested at O°C, +25°C and +70°C.
NOTE 2: These specifications apply for Xl (±10V) models; for X2 (±5V) models, divide specifications shown by 2.
NOTE 3: Reference Output terminal connected directly to Reference Input terminal, RL = 2Kn, all logic inputs;;;' 2.0 V.
10-7
-
-
Units
bits'
bits
bits
bits
bits
bits
%
%
%
%
/01 sec
ppmfC
ppmfC
nA
Mn
V/,..sec
V
mV
mV
mV
mV
%VFsiV
mW
,..A
V
V
V
V
V
V
I
DAC-02
DEFINITION OF SPECIFICATIONS*
BIPOLAR FULL SCALE SYMMETRY
The magnitude of the difference between IVFS+I and
IVFSJ
LOGIC "0"
The (low) logic input voltage necessary to hold a bit OFF.
LOGIC "'"
The (high) logic input voltage necessary to hold a bit ON.
ZERO SCALE OFFSET
The output voltage .(VZS+) produced by a positive zero
scale input.code (1-0000000000)
ZERO SCALE SYMMETRY
The change in the output voltage produced by switching
the Sign Bit with all logic bits low (VZS+-VZS-)
SIGN/MAGNITUDE CODING
The input logic codi'ng used by the DAC-02. The polarity
of the output voltage is determined by the logic level of the
Sign Bit; the magnitude of the output voltage is determined
by the binarily-weighted logic inputs.
OPERATING INSTRUCTIONS
FULL SCALE ADJUSTMENT-Full Scale output voltage may be
trimmed by use of a potentiometer and series resistor as shown;
however, best results will be obtained jf a low tempeD resistor
if used or if pot and resistor tempeDs match. Alternatively. a single
FULL SCALE ADJUSTMENT CIRCUIT
pot of ;. 75K!"! may be used.
r---DIGITAL
IHPUTS~
M58
REFERENCE OUTPUT-For best results, Reference Output current
should not exceed 100/LA.
LSB SIGN BIT V+
REFERENCE
OUT'PUT
USE WITH EXTERNAL REFERENCES-Positive-polarity external
reference voltages referred to Analog Ground may be applied to the
Reference Input terminal to improve full scale tempee, to provide
FULL
SCALE
10110
~ST >+-:R=EF=E~~:=~=Br=-E....-I---l
62kO-
tracking to other system elements, or to slave a number of DAC·02's
to the Reference Output of anyone of them.
L.OWT.C.
ANALOG-
GROIJNO
REFERENCE INPUT BYPASS-Lowest noise and fastest settling
operation will be obtained by bypassing the Reference Input to
v-
DIGITAL. GROUND
Analog Ground with a O.Ol/LF disk capacitor.
VARIABLE REFERENCES-Operation as a two-quadrant multi·
plying DAC is achieved by applying an analog input varying between
o and +10V to the Reference Input terminal. The DAC output is
then the scaled product of this voltage and the digital input. ±5V
output models (X2) must be used if Reference Input voltages will
POSITIVE S!>GN/MAGNITUDE CODING TABLE
exceed +6.7V in order to prevent saturation of the output amplifier.
LOWER
SIGN
BIT
RESOLUTION' APPLICATIONS-For applications not
+ FULL SCALE
UNIPOLAR OPERATION-Operation as a 10 bit straight binilry
+ "HALF" SCALE
converter may be implemented by permanently tyrng the Sign Bit
ZERO SCALE (+)
1
0
to +5V (for positive Full Scale output) or to ground (for negative
Full Scale output).
ZERO SCALE
H
0
0
0
POWER SUPPLIES-The DAC-02 will operate within specifications
for power supplies ranging from ±12V to ±18V. Power supplies
- "HALF" SCALE
0
-FULL SCALE
0
LSB
MSB
requiring full 10 bit resolution, unused logic inputs should be tied to
ground.
1
1
1
1
1
1
1
1
1
1 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
GROUNDING-for optimum noise rejection, separate digital and
should be bypassed near the package with a 0.1/LF disk capacitor.
analog grounds have been brought out. Best results will be obtained
if these grounds are connected together at one point only, pre-
Chip users should connect the substrate to V-,
CAPACITIVE LOADING-The output operational amplifi~r pro-
ferably near the DAC·02 package, so that the large digital currents
do not flow through the analog ground path.
vides stable operation with capacitive loads up to 100pF.
·SEE SECTION 13 FOR COMPLETE D/A CONVERTER
DEFINITIONS
10-8
DAC-03
PMI
8 & 10 BIT LOW COST MONOLITHIC D/A CONVJRTER
GENERAL DESCRIPTION
FEATURES
The DAC-03 is a complete 10 bit low cost D/A converter on a
single 82 x 148 mil monolithic chip. All elements of a complete D'AC are included-precision voltage reference, current
steering logic, current sources, R-2 R resistor network and high
speed internally compensated output op amp. The untrimmed
diffused R-2R resistor ladder network achieves monotonic
operation over a wide temperature range. The buffered reference input is capable of tracking over a wide range of voltages,
increasing application flexibility. The wide power supply
range, low power consumption and choice of full scale output
voltages assure utility in a wide range of applications including
CRT displays, data acquisition systems, A/D converters, and
servo positioning controls. For bipolar DAC's refer to the
DAC-02 and DAC-04 data sheets.
•
•
•
•
•
•
•
•
•
•
Monotonicity Guaranteed
Low Cost
Complete
Includes Reference and Op Amp
Compact . . . . . . . . . . . Single 18 Pin DIP Package
Fast . . . . . . . . . . . . . . . . . . 1.5 J.lsec Settling :Time
Sta~le . . . . . . . . . . Full Scale Tempeo 60 ppmfC
I
Standard Power Supplies . . . . . . . . . ±12V to ±18V
Low Power Consumption . . . . . . . . . . 350 mW Max
TTL, DTL, CMOS Compatible Inputs
5V and 10V Models Available
I
SIMPLIFIED SCHEMATIC AND PIN CONNECTION DIAGRAM
CONNECT
, - - - - - - - - - - O I G r r A L LOGICJNPUTS--------,\
MSBI
81T2
8113
81T4
81T6
BIT 6
81T7
BIT 8
8119
6~T~
v.
81TIO
~~~:~~~r-OD~-4r-~--t2-_+-~--r_-+.-~--r_-t_-~I-O--I.----~'.
ORDERING INFORMATION
MODEL
DAC-03 AD Xl (or
DAC-03 BDXl (or
DAC-03 CDXl (or
DAC-03 DDX1(or
MONOTONICITY
X2)'
X2)'
X2)*
)(2)'
10
9
B
7
BITS
BITS
BITS
BITS
TEMP RANGE
0° 1+70°C
0° /+70°C
0° /+70°C
0° /+70°C
'Suffix Xl indicates +10V output; suffix X2 indicates +5V output.
10-9
FSTEMPCO
60
60
60
60
ppmfDC TYP
ppmfDC TYP
ppm;oCTYP
ppm;oCTYP
PACKAGE
18 PIN
18 PIN
18 PIN
18 PIN
D1P
DIP
DIP
DIP
DAC-03
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
Storage Temperature Range
V+ Supply to Analog Ground
V- Supply to Analog Ground
Analog Ground to Digital Ground
Logic In;>uts to Digital Ground
Internal Reference Output Current
300llA
Reference Input Voltage
0 to +10V
Internal Power Dissipation
SOO mW
Lead Soldering Temperature
300°C (60 sec)
Output Short Circuit Duration
Indefinite
(Short circuit may be to ground or either supply.)
0° to +70°C
-6SoC to +lS0°C
o to +18V
Oto-18V
o toiO.SV
-SV to (V+ -.7VI
ELECTRICAL CHARACTERISTICS
These specifications apply for Vs = ±15V and TA = 25°C unless otherwise specified.
Condition
Parameter
Min
Resolution
Monotonicity
Nonlinearity
Grade AD
Grade BO
Grade CO
Grade 00
Grade
Grade
Grade
Grade
Max
Uniu
10
19·
10
bits
10
9
8
7
-
bits
bits
bits
bits
-
-
-,
to.l
to.l
.0.2
to.4
1.5
-
~sec
-
AD
BO
CO
00
Typ
-
-
.,
%
%
%
%
Settling Time
To ±1/2 LSB, 10 Volt Step
-
Full Scale Tempco
Total, Internal Reference Connected
-
60
-
ppm/"C
Full Scale Tempco
External Reference
-
±4O
-
ppm/"C
Reference Input Bias Current
-
100
-
nA
F!eference Input Impedance
-
200
-
Mn
Reference Input Slew Rille
-
1.5
-
V/"sec
Reference Output Voltage
-
6.7
-
V
Zero Scale Offset
-
±1.0
.10
mV
Power Supply Sensitivity
Vs = .12V to ±18V
-
Power Dissipation
IOUT=O
-
225
350
Logic Input Current
(Each Input, -5V to (V+ - .7V)
-
1
-
"A
Logic Input "0"
-
-
0.8
V
Logic Input "I"
2.0
-
-
V
+10.0
-
+11.6
Full Scale Output Voltage
Volt Models (X 1')
6 Volt Models(X2)
to
(See Note)
+5.00
•.015
.0.1
+6.76
NOTE: Reference Output terminal connectad directly to Reference Input terminal and pin 18, RL = 2Kn, all logic inputs;;' 2.0 V.
;
10-10
%VFSIV
mW
V
V
DAC·03
SEE SECTION 13 FOR COMPLETE D/A CONVERTER
DEFINITIONS
DEFINITION OF SPECIFICATIONS
LOGIC "0"
The (low) logic input voltage necessary to hold a bit OFF.
ZERO SCALE OFFSET
The output voltage (VZS) produced by a zero scale input
code (0000000000)
LOGIC "1"
The (high) logic input voltage necessary to hold a bit ON.
APPLICATION NOTES
FULL SCALE ADJUSTMENT -Full Scale output voltage may be
FULL SCALE ADJUSTMENT CIRCUIT
as
trimmed by use of a potentiometer and series resistor
shown;
however, best results will be obtained if a low tempeD resistor is
used or if pot and resistor tempeDs match. Alternatively. a single
pot of .. 75K!1 may be used.
r;,;;-- DIGITAL INPUTS
REFERENCE OUTPUT -For best results, Reference Output current
should not exceed 100jLA.
~
REFERENCE
OUTPUT
£ULL
SCALE
IOkQ
~~T5+~R~EF~ER~E~Na~--~--~
USE WITH EXTERNAL REFERENCES-Positive·polarity external
reference voltages referred to Anal,og Ground may be applied to the
INPUT
Reference Input terminal to improve full scale tempco. to provide
tracking to other system elements, or to slave a number of DAC~03's
to the Reference Output of anyone of them.
Ol81TAI.. GROUND
I
REFERENCE INPUT BYPASS-Lowest noise and fastest settling
operation will be obtained by bypassing the Reference Input to
Analog Ground with a O.OljLF disk capacitor.
GROUNDING-for optimum noise rejection, separate digital and
analog grounds have been brought out. Best results will be obtained
if these grounds are connected together at one point only, preferably
near the DAC·03 package, so that large digital curren,ts do not flow
through the analog ground path.
LOWER RESOLUTION APPLICATIONS-For applications not
requiring full 10 bit resolution, unused logic inputs should be tied
to ground.
POWER SUPPLIES-The DAlC·03 will operate within specifications
for power supplies ranging from ±12V to ±18V. Power supplies
should be bypassed near the package with a O.lI1F disk capacitor.
Chip users should connect the substrate to V-.
CAPACITIVE LOADING-the output operational amplifier pro·
vides stable operation with capacitive loads up to 100pF.
INTERFACING WITH CMOS LOGIC
The OAC·03's logic input stages require about 1J.lA and are
capable of operation with inputs between -5 volts and V+ less
.7 volt. This wide input voltage range allows direct CMOS
interfacing in most applications, the exception being where the
CMOS logic and OfA converter must use the same positive
power su pply.
v+
y-
In this special case, a diode should be placed in series with the
CMOS driving device's VDO lead as shown in Figure 1. The
diode limits V DD to V+ less. 7 volt-since the output from the
CMOS device cannot exceed this value, the OAC's maximum
input voltage rule is satisfied. Summarizing: in all applications,
the OAC·03 requires either no interfacing components, or at
most a single inexpensive diotJe for full CMOS compatibility.
FIGURE 1
10·11
PMI
IOAC-041
®
TWO'S COMPLEMENT 10 BIT D/A CONVERTER
GENERAL PESCRIPTION
FEATURES
The DAC-04 is a complete 10 bit Two's Complement D/A
Converter on a single 82 x 148 mil monolithic chip_ All elements of a complete bipolar output Two's Complement DAC
are inciuded-pt:ecision volt~ge reference, current steering
logic, current sources, R-2R resistor network, bipolar offset
circuit and high speed internally compensated output op amp_
Monotonicity guaranteed over the entire 0° to+ 70° Ctempera:
ture range is achieved using an untrimmed diffused R-2 R
resistor network_ The buffered reference input is capable of
tracking over a wide range of voltages, increasing application
flexibility_ The user may also easily implement One's Complement, Straight Offset Binary, or unipolar operation_ The
±12V to ±18V power supply range, low power consumption
TTL and CMOS compatibility, choice of full scale output
voltages and adaptable logic coding capability assure utility in
a wide range of applications_
•
Complete
_, •. _ _ _ Includes Reference and Op Amp
•
Compact
____ . ___ . _ .. Single 18 Pin DIP Package
•
Bipolar Output
•
•
Monotonicity Guaranteed
Nonlinearity _ _ _ _ _ _ _ _ _ _ _ _ _ . . . . _ .. _ ±1 LSB
_______ Two's Complement Coding
•
Fast . _ .... _ . __ .. __ . _ ... 1_5/lsec Settling Time
•
Standard Power Supplies __ . ___ . __ . ±12V to ±18V
•
Low Power Consumption _ .. _ . _ .. _ .. 300 mW Max
•
TTL, CMOS Compatible Inputs
•
Reliable _ ..... _ . _100% Burned-in 72 Hrs
@
+125°C
SIMPLIFIED SCHEMATIC AND PIN CONNECTION DIAGRAM
DIGITAL LOGIC INPUTS
I
SIGN BIT I
REFERENCE
OUTPUT
REFERENCE
INPUT
DIGITAL
GROUND
17
I
'"'"
."~
BIT 2
•
BIT 3
3
BIT 4
•
BIT
~
~
BIT
6
•
BIT 8
8
BIT 9
•
BIT 10
10
r-
~vI-...
_CD,.........
BIPOLAR
AO.JUST
18
I.
~
--1
"
y+
\
BIT 7
7
-5' -)'-~'-)' -)'-)'-)' )' -~ '!,'
~
1.111 .11.1 .111 .
.. I
i
I-
ANALOG
OUTPUT
I'
y-
ANALOG GROUND
ORDERING INFORMATION
MODEL
OUTPUT
DAC-04ACX2
DAC-04BCX2
DAC-04CCX2
DAC-04DDX2
±5V
±5V
±5V
±5V
MONOTONICITY
10
9
8
7
BITS
BITS
BITS
BITS
FSTEMPCO
90ppmfC
90 ppmi"C
90 ppm/"C
150 ppmi"C
10-12
MAX
MAX
MAX
MAX
TEMP RANGE
0° /+700 C
0° /+70°C
0° /+70 0 C
0° /+70°C
PACKAGE
18
18
18
18
PIN
PIN
PIN
PIN
HERMETIC
H.ERMETIC
HERMETIC
HERMETIC
DIP
DIP
DIP
DIP
DAC-04
ABSOLUTE MAXIMUM RATINGS
0° to +70°C
_65°C to +150°C
o to +18V
Oto -18V
Oto ±0.5V
-5V to (V+ - .7V)
Operating Temperature Range
Storage Temperature Range
V+ Supply to Analog Ground
V- Supply to Analog Ground
Analog Ground to Digital Ground
Logic Inputs to Digital Ground
Internal Reference Output Current
300p.A
Reference Input Voltage
o to +lOV
Internal Power Dissipation
500mW
300°C (60 sec)
Lead Soldering Temperature
Output Short Circuit Duration
Indefinite
(Short circuit may be to ground or either supply.)
ELECTRICAL CHARACTERISTICS
These specifications apply for
Vs =
±15V and over the
aOe to +70c C
temperature range, unless otherwise specified.
GRADES AC, BC, CC
Condition
Parameter
Resolution
Min
Typ
Max
Min
Typ
Max
10
10
10
10
10
10
-
Monotonicity
aOc to
(See Note 1)
Grade AC
10
-
Grade BC
9
8
-
(See Note 1)
-
1.5
-
bits
bits
Grade BC
60
150
30
-
-
50
-
ppmtC
106
-
-
100
-
nA
200
-
-
200
-
Mn
Full Scale Tampeo
Total, Internal Reference Connected
-
45
Full Scale Tempeo
Zero Drift External Reference Applied
Reference Input Slew Rate
-
Reference Output Voltage
-
6.7
-
±5.0
-
-5.0
-
Unipolar Zero Scale Output Voltage
Short Pin 18 to ground (See Note 2)
Bipolar Offset Voltage
Short Pins.15 and 18 to Pin 17 ISee Note 3)
Power Supply Sensitivity
Vs = ±12V to ±18V
-
IOUT=O
-
Each Input, -5V to (V+ - .7V)
1.5
±0.015
225
-
2.5
ppmtC
-
V/I"see
-
V
-
±5.0
-
-0.1
-5.0
-
±0.1
300
-
±0.15
300
1.0
-
-
-
-
0.8
-
Logic Input "1"
2.0
-
-
2.0
-
11.5
-
10
mV
-0.1
% Range
-
%IV
350
mW
-
I"A
0.8
V
-
V
11.5
V
NOTE 1:
This parameter is 100% tested at O'C, +25'C and +70'C
NOTE 2:
May be operated in 0 to +10V Unipolar mode by shorting Pin 18 to ground.
NOTE 3:
Bipolar Offset Voltage is trimmable to exact Two's or One's Complement condition with the circuit shown on the next page.
NOTE 4:
Full Scale Output Voltage is trimmable to exact desired output range of 10V with the circuit shown on the next page.
10-13
J,tsec
1.5
-
10
-
6.7
Logic Input "0"
Short Pin 15 to Pin 17 (See Note 4)
±0.4
-
1.0
Full Scale Output Range
%
%
%
%
90
-
-
bits
-
Grade DD
Reference 1"put 1mpedance
-
±O·l
±0.2
To ±1/2 LSB. 10 Volt Step
Reference Input Bias Current
-
±0.1
Settling Time
Logic I nput Current
bits
bits
7
O'C to +70'C
Grade AC
Grade CC
Power Dissipation
Units
+70°C
Grade CC
Grade DD
Nonlinearity
GRADE DD
I
DAC-04
DEFINITION OF SPECIFICATIONS
SEE SECTION 13 FOR COMPLETE O/A CONVERTER
DEFINITIONS
BIPOLAR ,OFFSET VOLTAGE 1/2!1VFS+I-IVFS-O
The maximum error due to asymmetry around zero output
expressed as a percentage of Full Scale Output Range.
FULL SCALE OUTPUT RANGE
The peak-to-peak voltage swing of the converter's output,
i.e. IVFS+I+IVFS-ll for bipelar operation, and (VFS-VZS)
for unipolar operation.
NEGATIVE BIPOLAR FULL SCALE OUTPUT VOLTAGE
tvFS-)
The output voltage for 1000000001 input code for Two's
Complement coding, or the output voltage for 1000000000
input code for One's Complement coding.
POSITIVE BIPOLAR FULL SCALE OUTPUT VOLTAGE
(VFS+)
The output for '0111111111 input code..
UNIPOLAR FULL SCALE OUTPUT VOLTAGE (VFS)
The (positive) output voltage for 0111111111 input code.
UNIPOLAR ZERO SCALE OUTPUT VOLTAGE (VZS)
The output voltage for 1000000000 input code.
OPERATING INSTRUCTIONS
FULL SCALE OUTPUT RANGE AND
BIPOLAR OFFSET ADJUSTMENT CIRCUIT
ADJUSTING FOR TWO'S COMPLEMENT CODING
,----DIGITAL I N P U T S - - ;
,'GMBIT
LS'
1m.
1. Connect Full Scale Adjust and Bipolar Adjust Circuitry as shown
in figure.
2. Turn all bits off (VFS--LSB) - 1 000000000
. -5.0098V
3. Adjust Bipolar Pot for VFS- -LSB at output
4. Turn all bits on (VFS+) - 0 1 1 1 1 1 1 1 1 1
5. Adjust Full Scale Pot for desired VFS+ value
ANA 15
."
. . . . +5.0000V
6. Check Zero Scale Reading (VZS) - 0 0 0 0 0 0 0 0 0 0
If this reading is outside desired VZS range, readjust Bipolar Pot
"SEE APPLICATION NOTES FOR DETAILS
_TIE TO GftOUND FOR UNIPOLAR OPERATION
till the output reads 0.0000 V.
TWO'S COMPLEMENT CODING TABLE
INPUT
MSB
VFS+
VFS+ - LSB
0
0
+1 LSB
0
0
Zero
0
0
0
0
0
0
0
0
0
0
0
0
0
LSB
IDEAL
OUTPUT
0
+S.OOOV
+4.990V
0
1
a a a
-1 LSB
a a a 0 0 0 0 1
a a a a a a a a
VFS- + LSB
VFS_
0
NOTE that two zero states will straddle (±1/2 LSB) the true zero.
Therefore the DAC will have symmetrical outputs for both positive
and negative full scale.
EXTERNAL ADJUSTMENT NETWORK-Full Scale Output Range
and Bipolar Offset may be adjusted by using the circuit shown in
the figure above. Best results will be obtained when low tempco
pots and resistors are used, or if pot and resistor tempeDs match.
+O.010V
O.OOOV
-0.010V
-4.990V
-S.OOOV
IMPLEMENTING STRAIGHT OFFSET BINARY CODINGStraight Offset Binary coding is exactly the same as One's Complement coding except that the most significant bit occurs in true,
rather than inverted form and the output states are relabeled. To
convert the DAC·04 to Straight Offset Binary code operation,
simply place a logic inverter in series with. the MSB input (Pin 1)
and invert the MSB value shown in steps 2, and 4 of the One's
Complement adjustment procedure shown above.
ADJUSTING FOR ONE'S COMPLEMENT CODING
1. Connect Full Scale Adjust and Bipolar Adjust Circuitry as shown
in above figure.
2. Turn all bits off (VFS-) - 1 0
a aa0 0 0 0 0
3. Adjust Bipolar Pot for V FS- at output
4. Turn all bits on (VFS+) -
. . . . . . . . -S.OOOOV
STRAIGHT OFFSET BINARY CODING TABLE
a111111111
INPUT
.S. Adjust Full Scale Pot for desired VFS+ value . . . . . +S.OOOOV
VFS+
VFS+ -1 LSB
ONE'S COMPLEMENT CODING TABLE
INPUT
MSB
VFS+
VFS+ - LSB
'+0
. -0
VFS_+ LSB
'VFS-
LSB
0
1
a
a
a
0
a a
0
0
0
a
0
0
0
0
1
a a a
1
1
1
0
0
0
0
0
0
0
0
0
a
0
1
0
LSB
MSB
IDEAL
OUTPUT
1
+ 1/2 LSB
+S.OOOV
+4.990V
+O.OOSV
-O.OOSV
Zero
- 1/2 LSB
0
VFS-+l LSB
VFS-
0
0
1
0
0
0
0
0
0
0
0
a
0
0
a
0
0
a
0
0
0
0
0
0
IDEAL
OUTPUT
0
+S.OOOV
+4.990V
0
+O.OOSV
0
-4.990V
-5.000V
-O.005V
0
0
0
REFERENCE OUTPUT-For best results, Reference Output current
should not exceed 1001LA.
-4.990V
-5.000V
10-14
DAC-04
OPERATING INSTRUCTIONS - CONT'D
USE WITH EXTERNAL REFERENCES-Positive-polarity external
reference voltages referred to Analog Ground may be applied to the
Reference Input terminal to improve full scale tempeD, to provide
tracking to other system elements, or to slave a number of DAC·04's
to the Reference Output of anyone of them.
REFERENCE INPUT BYPASS-Lowest noise and fastest settling
operation will be obtained by bypassing the Reference Input to
Analog Ground with a O.Ol"F disk capacitor.
VARIABLE REFERENCES-Operation as e two-'quadrant "),\lltiplying DAC is achieved by applying an analog input varying between
o and +10V to the Reference Input terminal. The DAC output is
then the scaled product of this voltage and the digital input. A
reference input of 6.27V will produce approximately nominal
output range.
POWER SUPPLIES-The DAC-04 will operate within specifications
for power supplies ranging from ±12V to ±18V. Power supplies
should be bypassed near the package with a O.l"F disk capacitor.
Chip users shou'ld connect the substrate to V-.
GROUNDING-for optimum noise rejection, separate digital and
LOWER RESOLUTION APPLICATIONS-For applications not
requiring full 10 bit resolution, unused logic inputs should be tied to
analog grounds have been brought out. Best results will be obtained
if these grounds are connected together at one point only, preferably
ground.
at the DAC-04 package, so that large digital currents do not flow
through the analog ground path.
UNIPOLAR OPERATION-Operation as a 10V pOSitive output
10 bit converter may be implemented by permanently tying pin 18
to ground.
CAPACITIVE LOADING-the output operational amplifier provides stable operation with capacitive loads up to 100pF.
I
10-15
PMI
IDAe-051
11 BIT DIGITAL TO ANALOG CONVERTER
(10 BITS PLUS SIGN,)
GENERAL DESCRIPTION
FEATURES
The DAC-05 is a complete, monolithic, Sign Plus 10 Bit DAC
with a voltage output_ A precision voltage reference, a logiccontrolled polarity switch, and a high speed (1_5 /-lsec settling
time) output op amp are included_ Monotonicity, nonlinearity, power consumption, and full scale temperature
coefficient are guaranteed over the full operating temperature
range. Reliability is enhanced by a monolithic design, 100%
burn-in, and a hermetic DIP package. Six low 'cost 0° /lO°C
and six _55° /+125°C models are available plus six models with
MIL-STD-883A Class B processing.
_
Complete
_
Bipolar Output
..... __ ..
Includes Reference and Op Amp
.. ___ .. _ .. _ _ Sign/Magnitude Coding
_
Fast . . . . . . . . . . . . . . . . . . . .
_
Monotonicity and Nonlinearity Guaranteed
_
Reliable .. : . . . . . . . . 100% Burned·in 72 Hrs @+125°C
_
Low Power Consumption . . . . . . . . . . . . . 350 mW Max
_ Compact
1.5/-lsec Settling Time
. . . . . . . Single 18 Pin Hermetic DIP Package
_
Choice of Output Ranges . . . . . . . . . . . . . ±5V or ±10V
_
Models with MI L·STD·883A Class B
Processing Available From Stock
SIMPLIFIED SCHEMATIC
PIN CONNECTIONS
S,O"
Bl0B9B8B7B811!i8483BltBl
1
81
SB
18
SIGN BI1 INPUT: 1 = POSITIVE
2
B2
RO
17
REFERENCE OUTPUT
BIT3 3
B3
v+
16
POSITIVE POWER SUPPLY
81T4 4
B4
RI
15
REFERENCE INPUT
BIT 1 MSB
BIT2
[)lGlrA,~
ANALOG
GROUND
al'lOUNO
BITS
5
B5
EO
6
B6
AG
"
ANALOG OUTPUT
BIT6
13
ANALOG GROUND
BIT 7
7
87
v-
12
NEGATIVE POWER SUPPLY
BIT8
•
B8
OG
11
DIGITAL GROUND
81T9
9
B9
81.
I.
BIT 10 LSB
TOP VIEW
18 PIN HERMETIC DUAL-IN-L1NE
(X-Suffix)
ORDl:RING INFORMATION
Military Temperature Range Devices
MODEL
MONOTONICITY
DAC-05AXI (or 2)
DAC-05BX1 (or 2)
10BITS
9 BITS
DAC-OSCX1 (or 2)
DAC-05EX1 (or 21
DAC-OSFX1 (or 2)
8 BITS
10 BITS
Ii BITS
8 BITS
DAC-OSGXl (or 2)
TEMP RANGE
with MIL-STD-883A Class B Processing:
-S5° /+12SoC
MODEL
-5S' {+12S'C
_55' /+12S' C
0° /+70°C
0° /+70'C
0° /+70'C
DAC OS-883-AX1 (or 2)
DAC OS-883-BX 1 (or 2)
DAC 05-883-CX.1 (or 2)
NOTE: Use suffix Xl for ±10V output or suffix X2 for ±SV output.
10-16
MONOTONICITY
10BITS
9 BITS
8 BITS
DAC-05
ABSOLUTE MAXIMUM RATINGS
.
Operating Temperature Range
Analog Ground to Digital Ground
o to +18V
o to -18V
V-Supply to Analog Ground
300llA
o to +10V
Reference Input Voltage
-6So C to +150° C
V+ Supply to Analog Ground
-SV to (V+ - .7V)
Internal Reference Output Current
O°C to +70°C
DAC-OSE,F,G
Storage Temperature Range
Oto ±O.SV
Logic Inputs to Digital Ground
-SSo C to +12SoC
DAC-OSA,8,C
Internal Power Dissipation
500mW
Lead Soldering Temperature
300°C (60 sec)
Output Short Circuit Duration
Indefinite
(Short circuit may be to ground or either supply.
ELECTRICAL CHARACTERISTICS -
MILITARY GRADES
These specifications apply for V S ~ ±15V and T A ~ _55° C to +125° C unless otherwise specified.
DAC-OSA
Parijlmeter
Symbol
Resolution
NL
Max
Min
Typ
Max
Min
Typ
Max
Including Sign
11
11
11
11
11
11
11
11
11
10
T A = OoC to +700 C
-
-
T A = _55°C to +125 O C
Full Scale Tempco
TCV FS
Internal Reference Connected
Full Scale Output Voltage
Sign Bit High (Note 1)
(Xl Suffix)
V FS +
V FS _
Sign Bit Low (Note 1)
Full Scale Output Voltage
V FS +
Sign Bit High (Note 1)
(X2 Suffix)
V FS _
Sign Bit Low (Note 1)
Zero Scale Offset
(Sign Bit High,
All Others Low)
V FS +
TA = +25'C
Enternal Reference Connected
Zero Scale Symmetry
DAC-OSC
Typ
Monotonicity
Nonlinearity
DAC-058
Min
Conditions
30
30
-
9
to.l
-
±0.2
60
-
-
-
+11.5 +10.0
-11.5
-
+5.00
-
+5.75 +5.00
-5.75
-
-5.00 -5.75
+10.0
-10.0 -11.5
-
-
-
±0.2
45
90
30
-
±0.3
-
-
-
bits
-
±OA
%FS
-
±0.5
%FS
60
120
ppmfC
-
ppmfC
30
-10.0 -11.5
-
+5.75 +5.00
-
+5.75 V
-5.00 -5.75
-
-5.00 V
+11.5 +10.0
1.0
5.0
-
1.0
5.0
T A = -55'C to +125'C
-
2.0
10
-
2.0
10
(Note 2)
-
±4.0
±10
-
±4.0
±10
(Note 2)
-
±2.0 .±5.0
-
±2.0
±5.0
(Xl Suffix)
Zero Scale Symmetry
8
-
Units
bits
-
+11.5 V
-10.0 V
1.0
5.0
mV
2.0
10
mV
-
±4.0
±10
mV
-
±2.0
±5.0
mV
(X2 'Suffix)
Full Scale Bipolar Symmetry
T A = +25'C (Ntite 3)
±50
-
±10
±50
-
±10
±50
mV
T A = -55°C to +125°C
-
±10
(Xl Suffix)
±20
±70
-
±20
±70
±20
±70
mV
Full Scale Bipolar Symrrletry
T A = +25°C (Note 3)
-
±5.0
±25
--'
±5.0
±25
-
±5.0
±25
mV
(X2 Suffix)
T A - -55°C to +125°C
-
±10
±35
±10
±35
±10
±35
mV
To ± Y, 1-SB. 10V Change
-
1.5
-
,usee
-
1.5
l.S
Settling Time
-
6.7
-
±1.0
±10
V IL
-
-
0.8
-
V IH
2.0
-
-
2.0
ts
Reference Input Slew Rate
Reference Input Bias Current
Reference Input Impedance
Reference Output Voltage
Logic Input Current
liN
Logic Input "0"
Logie Input "1"
Each Input, -5y to (V+ - .7V)
100
200
1.S
-
1.5
-
-
O.B
2.0
100
-
200
-
6.7
-
±1.0
±10
100
-
200
-
Mil
6.7
-
V
±1.0
±10
/LA
1.S
V/p.sec
nA
-
O.B
V
-
-
V
-
-
Power Supply Sensitivity
TA =+2SoC
-
0.02
O.OS
-
0.02
0.05
-
0.02
0.05
(V S = ±12V to ±lBV)
T A = -5SoC to +12S'C
-
O.OS
0.1
-
O.OS
0.1
-
O.OS
0.1
Power Dissipation
T A =+2SoC
-
200
300
-
200
300
200
300
mW
(lOUT =0)
T A = -S5°C to +12SoC
-
250
350
-
250
350
-
250
350
mW
%VF!I"
%VFSN
NOTE 1: Reference Output terminal connected directly to Reference Input terminal, RL = 2Kn, all logic inputs ~ 2.0 V.
NOTE 2: Zero Scale Symmetry is the change in the output voltage produced by switching the Sign Bit with all logic bits low (V ZS+ -V ZSJ·
NOTE 3: Full Scale Bipolar Symmetry is the magnitude of the difference between IV FS+I and IV FS-1.
10-17
I
DAe-05
CONNECTION INFORMATION
FULL SCALE ADJUSTMENT - Full Scale output voltage may be
by
trimmed
FULL SCALE ADJUSTMENT CIRCUIT
use
"'~al~l 'T 111 'j"'j'i"l'i T' OJ'' '
of a potentiometer and series resistor as shown; however, best results will be obtained
if a low tempeD resistor is used or if pot and resistor tempeDs match. Alternatively, a
single pot of;;. 75KO may be used.
REFERENCE INPUT' BYPASS - Lowest noi,. and fastest settling operation will be
obtained by bypassing the Reference Input to Analog Ground with a O.01/1F disk capacitor.
GROUNDING - For optimum noise rejection, separate digital and analog grounds hav.
been brought out. Best results will be obtained if these grounds are connected together
at one point only, preferably near the DAC·05 package, sothatthe large digital currents
do not flow through the analog ground path.
fULL
IOUl
!g~~:T
,,,.
REFERENCE
I"'PUT
I
"®
r
TOCURR£NT
~~~~~~
SOIJR'CEORtV[A
82Hl
LOWT.C
OAC-02
AJrlALOG
GROUND
~
*
J
OIGITA)GROUNO
ELECTRICAL GHARACTERISTICS- COMMERCIAL GRADES
These specifications apply for V S = ±15V and T A = O°C to +70°C unless otherwise specified.
DAC-05E
Parameter
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Including Sign
11
11
11
11
11
11
11
11
11
bits
10
-
-
9
-
-
8
bits
-
-
±0.1
-
-
±0.2
±0.4
%FS
-
±0.2
-'-
-
±0.3
-
-
TA -+25°C
±0.5
%FS
45
100
-
45
100
45
100
ppmfC
-
-
30
-
ppmfC
Symbol
Resolution
Conditions
Monotonicity
Nonlinearity
NL
TA =0°Ct070°C
Full Scale Tempco
TCV FS
Internal Reference Connected
Sign Bit High (Note 1)
+10.0
(X1 Suffix)
V FS +
V FS _
Sign Bit Low (Note 1)
-11.5
Full Scale Output Voltage
V FS+
Sign Bit High (Note 1)
(X2 Suffix)
V FS _
Sign Bit Low (Note 1)
Zero Scale Offset
(Sign Bit High,
All Others Low)
V ZS +
TA -25°C.
(Note 4)
Full Scale Output Voltage
DAC-05G
DAC-05F
External Reference Connected
30
-
-
-
-
+11.5 +10.0
-
+11.5 +10.0
-
-10.0 -11.5
+5.00
+5.75 +5.00
-
-5.75
-
-5.00 -5.75
-
1.0
5.0
T A - O°C to +70°C
-
2.0
(Note 2)
30
Units
-10.0 -11.5
-
-10.0 V
+5.75 +5.00
-
+5.75 V
-5.00 -5.75
-
-5.00 V
+11.5 V
1.0
5.0
-
1.0
5.0
10
-
2.0
10
-
2.0
10
mV
-
±4.0
±10
-
±4.0
±10
-
±4.0
±10
mV
(Note 2)
-
±2.0
±5.0
-
±2.0
±5.0
-
±2.0
±5.0
mV
Full Scale Bipolar Symmetry
T A = +25°.C (Note 3.)
±50
-
±10
±50
-
±10
±50
mV
T A - O°C to +70°C
±20
±70
-
±20
±70
-
±20
±10
mV
Full Scale Bipolar Symmetry
T A = +25°C (Note 3)
±5.0
±25
-
±5.0
±25
-
±5.0
±25
mV
(X2 Suffix)
T A - O°C to +70°C
±10
±35
±10
±35
-
±10
±35
Settling Time
To ± Y, LSB, 10V Change
-
±10
(Xl Suffix)
1.5
-
-
1.5
Zero Scale Symmetry
.
mV
(Xl Suffix)
Zero Scale 'Symmetry
(X2 Suffix)
1.5
-
Reference Input Slew Rate
-
1.5
-
Reference Input Bias Current
-
100
Reference Input Impedance
200
6.7
-
±1.0
±10
Logic Input "0"
V IL
-
Logic Input "I"
V IH
2.0
Reference Output Voltage
Logic Input Current
liN
Each Input, -5V to (V+ - .1V)
Power Supply SenSitivity
TA =+25°C
(V S = ±12V to ±18V)
T A = O°C to +70°C
Power Dissipation
TA =+25°C
(lOUT=O)
T A = O°C to +70°C
-
-
1.5
-
1.5
100
-
-
100
-
nA
-
200
-
-
200
-
MU
6.1
-
6.7
-
V
±1.0
±10
±1.0
±10
"A
-
0.8
-
-
2.0
-
-
0.8
-
-
2.0
0.02
0.05
-
0.02
0.05
0.05
0.1
-
0.05
0.1
200
300
200
300
250
350
-
250
350
NOTE 1: Reference Output terminal connected directly to Reference Input terminal, RL
mV
-
= 2Kn. all
..
-
-
"sec
VjlLsec
0.8
V
V
-
-
0.02
0.05
0.05
0.1
200
300
mW
250
350
mW
%VFSN
%VF",N
logic inputs ~ 2.0 V.
NOTE 2: Zero Scale Symmetry is the change in the output voltage produced by switching the Sign Bit with all logic bits low (V ZS+ -V ZS).
NOTE 3: Full Scale Bipolar Symmetry is the magnitude of the difference between IV FS+I and IV FS-I.
JIIOTE4: Parameter is not 100% tested; 90% o.t units meet this specification.
10-18
DAC-05
APPLICATIONS INFORMATION
LOWER RESOLUTI,ON APPLICATIONS - For applications not
USE WITH EXTERNAL REFERENCES - Positive-polarity external
requiring ·full 10 bit resolution, unused logic inputs should be tied
reference voltages referred to Analog Ground may be applied to the
Reference Input terminal to improve full scale tempeD, to provide
tracking to other system elements, or to slave a number of
to ground.
UNIPOLAR OPERATION - Operation as a 10 bit straight binary
DAC·OS's to the Reference Output of anyone of them.
converter may be implemented by permanently tying the Sign Bit
to +SV IFor positive Full Scale output) or to ground Ifor negative
Full Scale outputl.
SIGN PLUS MAGNITUDE CODING TABLE
POWER SUPPLIES - The DAC-OS will operate within specifications
for power supplies ranging from ±12V to ±18V. Power supplies
should be bypassed near the package with a 0.1/'F disk capacitor.
+ FULL SCALE
+ "HALF" SCALE
ZERO SCALE 1+1
ZERO SCALE H
- "HALF" SCALE
-FULL SCALE
CAPACITIVE LOADING - The output operational amplifier pro·
vides stable operation with capacitive loads up to 500pF.
REFERENCE OUTPUT - For best results, Reference Output cur·
rent should not exceed 100/,A.
SIGN BIT
MSB
0
0
0
1
0
0 0
0 0
0
1
LSB
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
I
10-19
PMI
TWO'S COMPLEMENT 10 BIT D/A CONVERTER
GENERAL DESCRIPTION
FEATURES
The DAC·06 is a complete, monolithic, Two's Complement
10 Bit DAC with a voltage output. A precision voltage refer·
ence, R·2R resistor network, bipolar offset circuit, and a high
speed (1.5 f.lsee settling. time) output op amp are included.
Monotonicity, nonlinearity, power consumption, and full scale
temperature coefficient are guaranteed over the full operating
temperature range. Reliability is enhanced by a monolithic
design, 100% burn-in, and a herm~tic DIP package. Three low
cost 0° /70°C and three _55° /+125 C models are available plus
three models with MIL·STD-883A Class B processing.
Q
SIMPLIFIED 'SCHEMATIC
_
Complete
_
Bipolar Output
...... Includes Reference and Op Amp
_
Fast . . . . . . • . . . . . . . . . 1.5 f.lsec Settling Time
_
Monotonicity and Nonlinearity Guaranteed
_
Reliable ...... 100% Burned-in 72 Hrs
_
Low Power Consumption .... ~ .... 350 mW Max
_
Compact .... Single 18 Pin Hermetic DIP Package
_
Models with MIL-STD·883A Class BProcessing
Available From Stock
...•• Two's Complement Coding
@
+125°C
PIN CONNECTIONS
...
BIOI9 II 111 IS 8& Ii' 83 82 &1
."""
CUIIAfNT
0\J1.uf
~
'"
. "O-i-+--I
SIGN BIT 1 1
Bl
BA
18
BIPOLAR ADJUST
BI12 2
B2
RO
11
REFERENCE OUTPUT
BIT3 3
83
V+
16
POSITIVE POWER SUPPLY
81T4 4
8"
Rl
","
REFERENCE INPUT
ANALOG OUTPUT
BIT5 5
B5
EO
BIT6
6
86
AG
'3
ANALOG GROUND
BIT 1
7
B7
v·
'2
NEGATIVE poweR SUPPLY
11
DIGITAL GROUND
BIT8
81T9
•
•
B8
DG
B'
Bl.
,.
B,IT 10 LSB
TOP VIEW
18 PIN HERMETIC DUAL-iN-LINE
(X-Suffixl
ORDERING INFORMATION
MODEL
DAC.()6AX
DAC·OSBX
DAC.()6CX
CAC-OBEX
DAC·OBFX
DAC.()6GX
MONOTONiCITV
.10 BITS
9 BITS
8 BITS
10 BITS
9 BITS
8 BITS
TEMP RANGE
.;sso /+125°C
_55° /+1 25° C
.;s5° /+12So C
0° /+70°C
0"/+70°C
0° 1.+70°C
10-20
Military Temperature Range Devices
with MIL·STD-883A Class B Processing:
MODEL
MONOTONICITV
DACOS-8B3·AX
DACOS-8B3·BX
DACOS-883-CX
10 BITS
9 BITS
B BITS
DAC-06
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
DAC-OSA, B, C
DAC-OSE, F, G
Storage Temperature Range
V+ Supply to Analog Ground
Internal Reference Output Current
300,uA
Reference Input Voltage
to +10V
Bipolar Offset Input Voltage
Oto +10V
Internal Power Dissipation
500mW
Lead Soldering Temperature
300°C (SO sec)
Output Short Circuit Duration
Indefinite
(Short circuit may be to ground or either supply.)
o
-55°C to +125°C
O°C to +70°C
-S5°C to +150°C
o to +18V
V- Supply to Analog Ground
Analog Ground to Digital Ground
logic Inputs to Digital Ground
Oto-18V
o to ±0.5V
-5V to (V + - .7V)
DAC-06 DEFINITIONS
FULL SCALE OUTPUT RANGE-The peak-to-peak voltage swing
of the converter's output, i.e. IVFS+I+IVFS-I for bipolar operation,
and (VFS-VZS) for unipolar operation.
POSITIVE BIPOLAR FULL SCALE OUTPUT VOL TAGE(VFS+)The output for 0111111111 input code.
NEGATIVE BIPOLAR FULL SCALE OUTPUT VOLTAGE(VFS_)The output voltage for 1000000001 input code for Two's Complement coding, or the output voltage for 1000000000 input code for
One's Complement coding.
UNIPOLAR FULL SCALE OUTPUT VOLTAGE (VFS)-The (pas itive) output voltage for 0111111111 input code.
UNIPOLAR ZERO SCALE OUTPUT VOLTAGE (VZSI- The output
voltage for 1000000000 input code.
BIPOLAR OFFSET VOLTAGE 1/2I1VFS+HVFS_II-The maximum
error due to asymmetry around zero output expressed as a percentage of Full Scale Output Range. (This is adjustable to zero-see
Adjustment Procedures on the last page.)
LEAST SIGNIFICANT BIT (LSBI-The smallest incremental output
change obtainable, which is ideally equal to the full scale output
range divided by 2n-1, where n
= number of bits of resolution.
MOST SIGNIFICANT BIT (MSB)-The largest incremental output
change obtainable by switching a single logic input, ideally equal to
the ideal LSB multiplied by 2 n - 1 , where n = number of bits of
resolution. In Two's and One's Comple~ent Converters this MSB is
inverted with respect to the other (binary) bits and is used as a sign
bit; this feature is incorporated into the OAC-06 design.
MONOTONICITY -Having each successive output state greater than
or equal to the preceding one when the OAC is sequenced through
all successive states'from VFS- to VFS+'
FULL SCALE TEMPERATURE COEFFICIENT-Change in absolute
full scale output range in ppm between 25°C and either temperature
extreme divided bv the corresponding change in temperature.
POWER SUPPLY SENSITIVITY-The ratio of the percentage change
in full scale output range to the change in the supply voltage producing it.
ELECTRICAL CHARACTERISTICS - MILITARY GRADES
These specifications apply for Vs
= ±15V and
T A = -55°C to +125°C unless otherwise specified.
DAC-OSA
Parameter
Min
TVp
Max
Min
TVp
Max
Min
TVp
Max
10
10
10
10
10
10
10
10
10
bits
Monotonicity
10
-
-
0.1
-
0.2
-
T A = -55°C to +125°C
0.2
-
0.3
-
-
-
-
bits
TA =0°Ct070°C
-
9
Internal Reference Connected
.-
30
60
45
90
120
ppmfC
-
30
-
30
-
-
60
External Reference Connected
-
30
-
ppmfC
10
-
11.5
10
-
11.5
10
-
11.5
V
-
1.0
5.0
-
1.0
5.0
5.0
mV
2.0
10
-
1.0
2.0
2.0
10
-5.0
-
-0.1
-5.0
.-
-0.1
-5.0
-
-0.1
-
1.5
-
1.5
6.7
-
-
Fu II Sci.le TempcD
Full Scale Output Range
NL
TCV FS
FSR
Conditions
DAC-OSC
Resolution
Nonlinearity
Svmbol
DAC-OSB
IV FSJ + IV FS+I
(Note 1)
Unipolar Zero Scale Output
Voltage (Pin 18 to Pin 11)
VZS
= +25°C
T A - -55°C to +125°C
Bipolar Offset Voltage
(Pin 15 to 18 and 17)
Settling Time
TA
)
)l,IIV FS+I-IV FS_1l
To ±)I, LSB, 10 Volt Step
10
-
1.5
-
Reference Input Slew Rate
-
1.5
-
Reference Input Bias Current
100
-
200
-
ts
Loglc Input Current
liN
Logic Input "0"
V IL
-
Logic Input "1"
V,~
Reference Input Impedance
Reference Output Voltage
Each Input, -5V to (V+ - .7V)
6.7
100
200
0.4
0.5
100
200
6.7
%FSR
mV
%FSR
!,sec
V/!'sec
nA
MO
V
±10
-
±1.0
±10
-
±1.0
±10
!'A
0.8
-
-
V
2.0
-
2.0
-
0.8
-
-
0.8
2.0
-
-
0.02
0.05
-
0.02
0.05
-
0.02
0.05
%FSIV
0.05
0.1
0.1
%FSIV
300
200
300
mW
250
350
-
0.05
200
250
350
mW
T A = +25°C
T A - -55°C to +125°C
-
0.05
0.1
Power Dissipation
(lOUT = 0)
T A = +25°C
-
200
300
?50
350
NOTE 1: Reference output terminal connected to Reference Input terminal and to Bipolar Adjust terminal with RL = 2Kn.
10-21
1.5
'O..~
%FSR
±1.0
Power Supply Sensitivity
(V S = ±12V to ±18V)
T A = _55°C to +125°C
1.5
8
Units
-
V
•
DAe-06
CONNECTION INFORMATION
EXTERNAL ADJUSTMENTS - Full Scale Range and Bipolar
Symmetry may be adjusted using the connections shown with the
procedures on the next page.
I
REFERENCE INPUT BYPASS - Lowest noise and fastest settling
operation will be obtained by bypassing the Reference Input and
the Bipolar Offset Adjust inputs with O.OIILF disc capacitors
connected to Analog Ground.
GROUNDING - For optimum noise rejection, separate digital and
analog grounds have been brought out. Best results will be obtained
if these grounds are connected together at one point only, preferably at the DAC-06 package, so that large digital currents do not
flow through the analog ground path.
REFERENCE OUTPUT - For best results, Reference Output
current should not exceed 1001LA.
USE WITH EXTERNAL REFERENCES - Positive-polarity exter-
DIGITAL INPUTS
\
~~~~J SJ 41 J J J J sf J
v+
16
~~RRENT
~.EDRIVER
I
ANALOG
OUTPUT
14
.... ... J
ANA 13
GND
REF 15
IN
R~F
17
alP 18
ADJ
OUT
DIG~111
GND
*
nal reference voltages referred to Analog Ground.may be applied to
20kn
the Reference Input terminal to improve full scale tempeD, to
provide tracking to other system elements, or to slave a number of
DAC·06's to the Reference Output of anyone of them.
FULL sc"ALt
ADJUST POT-
20kn
~~LAR OFFSET
ADJUST POT
T
UNIPOLAR OPERATION - Operation as a 10V positive output
10 bit converter may be implemented by permanently tying piri 18
62kn- LOW T.e.
to ground.
LOWER RESOLUTION APPLICATIONS - For applications not
NOTE: For unipolar operation, omit the Bipolar offset adjustment
potentiometer.
requiring full 10 bit resolution, unused logic inputs should be tied
to ground.
ELECTRICAL CHARACTERISTICS - OOMMERCIAL GRADES
These specifications apply for Vs = ±15V and T A = O°C to 70°C unless otherwise specified.
DAC-06F
DAC-06E
Parameter
Symbol
Conditions
ResolutioA
NL
Full Scale Tempco
(Note 2)
Tev FS
Full Scale Output Range
FSR
Min
Typ
Max
Min
Typ
Max
10
10
10
10
10
10
10
10
10
10
9
8
0.2
0.4
T A = O°C to +70°C
0.2
0.3
Internal Reference Connected
45
External Reference Connected
30
IV FS-' + IV FS+I
10
100
%FSR
45
30
11.5
bits
%FSR
0.5
45
100
10
100
10
ppmfC
ppmfC
30
11.5
Units
bits
11.5
V
TA =+25°C
I.Q
5.0
1.0
5.0
1.0
5.0
mV
TA - O°C to +70°C
2.0
10
2.0
10
2.0
10
mV
Bipolar Offset Voltage
(Pin 15 to 18 and 17)
Settling Time
Max
0.1
(Note 1)
Un ipolar Zero Scale Output
Voltage (Pin 18 to Pin 11)
Typ
TA = +25°C
Monotonicity
Nonlinearity
DAC-06G
Min
-5.0
To ±% LSB, 10 Volt Step
-0.1
-0.1
-5.0
-5.0
-
1-0.1
%FSR
1.5
1.5
1.5
Jolsec
1.5
1.5
1.5
V/lLsec
Reference Input Bias Current
100
100
100
nA
Reference Input Impedance
200
200
200
Mn
Reference Input Slew Rate
Reference Output Vottage
Logic Input Current
6.7
Each Input, -5V to (V+ - .7V)
±1.0
Logic Input "0"
Power Dissipation
(lOUT=O)
±1.0
0.8
Logic Input "1"
Power Supply Sensitivity
(V S = ±12V to ±18V)
6.7
± 10
2.0
T A = O°C to +70°C
T A = O°C to +70°C
±1.0
0.8
2.0
10-22
± 10
0.8
ILA
V
v
2.0
0.02
0.05
0.02
0.05
0.02
0.05
%FSIV
0.05
0.1
0.05
0.1
0.05
0.1
%FSIV
200
300
200
300
200
300
mW
250
350
250
350
250
350
mW
NOTE 1: Reference Output terminal connected to Reference Input terminal and to Bipolar Adjust terminal with RL = 2Kn.
NOTE 2: Parameter is not 100% tested; 90% of units meet this specification.
V
6.7
± 10
DAC-06
. ADJUSTMENT PROCEDURES
ADJUSTING FOR TWO'S COMPLEMENT CODING
ADJUSTING FOR ONE'S COMPLEMENT CODING
1. Turn all bits off (V FS--LSB) -
2. Adjust Bipolar P.ot for V FS- at output. '. . . . . . . • . . . . . . . .
for ±SV operation adjust to -S.OOOOV.
1. Turn all bits off (V FS) 1 000000000
2. Adjust Bipolar Pot for V FS--LSB at output ..•....... '.' ....
for ±SV operation adjust to -S.009BV.
3. Turn all bits on (V FS+) -
3. Turnallbitson(V FS+ ) - O l l l l l l l l l
0000000000
If this reading is outside desired V ZS range, readjust Bipolar Pot
till the output reads 0.0000 V.
INPUT
+1 LSB
Zero
-1 LSB
VFS_+LSB
V FS _
0
0
LSB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0
0 0
1
0
0
LSB
o
o
0
+4.990V
+O.010V
O.OOOV
-o.010V
0
-4.990V
1 1
IDEAL
OUTPUT
o
+4.990V
000
+O.005V
-o.005V
-4.990V
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-5.000V
NOTE that two zero states will straddle (±Y.. LSB) the true zero.
Therefore the DAC will give symmetrical outputs for both positive
and negative full scale.
STRAIGHT OFFSET BINARY CODING TABLE
INPUT
-S.OOOV
IDEAL
MSB
LSB
V FS +-l LSB
-
Straight Offset Binary coding is exactly the same as One's Complement coding except that the most significant bit occurs in true,
rather than inverted form and the output states are relabeled. To
convert the DAC-06 to Straight Offset Binary code opera~
tion, simply place a logic inverter in series with the MSB input
(Pin 1) and invert the MSB value shown in steps 2, and 4 of the
One's Complement adjustment procedure.
+Y.. LSB
Zero
- Y.. LSB
10-23
OUTPUT
+5.000V
V FS +
IMPLEMENTING STRAIGHT OFFSET BINARY CODING
1
+5.000V
0000000
1
1
1
IDEAL
OUTPUT
1
0
1
1
INPUT
+5.000V
0
0 0
0 0
1
1
o
o
MSB
0
1
MSB
TWO'S COMPLEMENT CODING TABLE
0
1 1
ONE'S COMPLEMENT CODING TABLE
S. Check Zero Scale Reading (V ZS) -
V FS+
0 1
4. Adjust Full Scale Pot for desired V FS+ value . . . . . . . . . . . . .
for ±5V operation adjust output to +5.0000V.
4. Adjust Full Scale Pot for desired V FS+ value •.••.....•.....
for ±SV operation adjust output to +5.0000V.
V FS+ - LSB
1 0 0 0 0 0 0 000
0
0
0
0
0
0
0
0
0
+4.990V
0
+O.OO5V
0
-O.OO5V
V FS _+1 LSB
0
0
0
0
0
0
0
0
0
V FS _
0
0
0
0
0
0 0
0
0
-4.990V
0
-5.000V
•
IDle-oal
PMl
8 BIT HIGH SPEED MULTIPLYING Of A CONVERTER
UNIVERSAL DIGITAL LOGIC INTERFACE
GENERAL DESCRIPTION
FEATURES
The DAC·08 series of 8 bit monolithic multiplying ,Digital·
to·Analog Converters provide, very high speed performance
coupled with low cost and outstanding applications flexibility.
Advanced circuit design, achieves 85 nsec settling times with
very low "glitch" and at low power consumption. Monotonic
multiplying performance is attained over a wide 40 to 1
reference current range. Matching to within 1 LSB between
reference and full scale currents eliminates the need for full
scale trimming in most applications. Direct interface to all
popular logic families With full noise immunity is provided by
the high swing, adjustable threshold logic inputs.
High voltage compliance dual complementary current outputs
are provided, increasing versatility and enabling differential
operation to effectively double the peak·to·peak output swing.
In many applications, the outputs can be directly converted to
voltage without the need for an external op amp.
All DAC·08 series models guarantee full 8 bit monotonicity,
and nonlinearities a's tight as ±O.l%over the entire operating
temperature range are available. Device performance is essen,
tially unchanged over the ±4.5V to ±18V power supply range,
with 33 mW power consumption attainable at ±5V supplies.
_ Fast Settling Output Current . . . . . . . . . . . . . . . 85 nsec
_ Full Scale Current Prematched to ±1 LSB
_
Direct Interface to TTL, CMOS, ECL, HTL, PMOS
_ Nonlinearity to ±O.l% Max Over Temp Range
_ High Output impedance and Compliance .. -10V to +18V
_ Differential Current Outputs
_ Wide Range Multiplying Capability .... 1 MHz Bandwidth
_ Low FS Current Drift . . . . . . . . . . . . . . . . . ±10ppmtC
_ Wide Power Supply Range ............. ±4.5V to ±18V
_
_
Low Power Consumption .. . . . . . . . . .. 33 mW
Low Cost
@
±5V
The compact size and low p6wer consumption make the
DAC·08 attractive for portable and military/aerospace applica.
tions; devices processed toM IL·STD·883A, Level B are available.
DAC·08 applications include 8 bit, 1 /./Sec A/D converters,
servo·motor and pen drivers, waveform generators, audio
encoders and attenuators, analog meter drivers, programmable
power supplies, CRT display drivers, high speed modems and
other applications where low cost, high speed and complete
input/output versatility are required.
EQUIVALENT CIRCUIT
ORDERING INFORMA nON AND PIN CONNECTION
16 COMPENSATION
THRESHOLD CONTROL 1
lOUT 2
15 VREF(-)
V- 3
14 VREF(+)'
13 V+
12 B8 LSB
11 B7
10B6
lOUT 4
MSB Bl 5
B26
B37
B4B
9 B5
TDPVIEW
16 PIN HERMETIC DUAL·IN·LINE
(O·Suffix)
MODEL
DAC-OBAO
DAC-OBO
DAC·OBHO
DAC-OBEO
DAC-OBCQ
TEMP RANGE
NONLINEARITY
_55° /+125°C
_55° /+125°C
00/70°C
0° /70°C
D° /70°C
±0.1%
±0.19%
±0.1%
±0.19%
±0.39%
Military Temperature Range Devices
With MIL·STD-8B3A Class B Procps,'ng:
ORDER: DAC·08-8B3·AQ
DA C-OB-8B3·Q
FIGURE 1
10·24
DAC-08
(T A ~ 2SoC unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
36V
V+ Supply to V- Supply
°
DAC·08AO,
DAC-08EO, CO,HO
Storage Temperature
-55°C to +12SoC
Logic Inputs
O°C to +70°C
-6SoC to +l50°C
VLC
Analog Current Outputs
SOOmW
Power Dissipation
Derate above 1OOC C
V-to V+
See Fig. 12
V-to V+
Reference Inputs (V 14, V 1S)
Reference Input Differential Voltage (V 14 to V1S)
±18V
Reference Input Current (114)
S.OmA
10mWtC
300°C (60 sec)
Lead Soldering Temperature
V- to V- plus 36V
TYPICAL PERFORMANCE PHOTOGRAPHS
FIGURE 2
TRUE AND COMPLEMENTARY OUTPUT OPERATION
FIGURE 3
FULL SCALE SETTLING TIME
all bits switched ON
2.4 VLOGIC
INPUT
0.4 V-
I
OUTPUT - tl2 LSB_
SETTLING
0+1/2 LSB-
50 "sec/division
SETTLING TIME FIXTURE OF FIGURE 29
=2mA RL =I K n
IFS
112 LSB = 4"A
FIGURE 5
FAST PULSED REFERENCE OPERATION
FIGURE 4
LSB SWITCHING
-,
-
-~~-
-~~---~--,.--
.-
~
-
2.4V-
2.5 V.VIN
BIT B
LOGIC INPUT
0.5 V.-
0.4V-
OV-
.~
++.+_.,t
~.
t
HH
_+ __ 4~
-0.5 mAlOUT
B".A0-
I
lOUT
I
I
,
-:-1--
-
I
-2.5 mA-
I
.L..L...._ l_.l._~ _Ll~
200 nsec/division
SEE FIGURE 27
50 nsec/division
REQ"'200n
RL=IOOn
Cc =0
10-25
-
+, .......... t+
DAe-os
ELECTRICAL CHARACTERISTICS
These specifications apply for Vs = ±15V, IREF = 2.0 rnA, TA = -55°C to +125°C unless otherwise specified. Output
characteristics refer to both lOUT and lOUT.
DAC-OBA
Parameter
Symbol
Mi,n
Conditions
DAC-OB
Typ
Max
Min
Typ
Max
Units
Resolution
8
8
8
8
8
8
bits
Monotonicity
8
8
8
8
8
8
bits
TA =-55°C to +125°C
-
-
±0.1
-
-
±0.19
%FS
Settling Time
ts
To ±YoLS8,all bits
switched ON or OFF
TA = 25°C
-
85
135
-
85
135
nsec
Propagation Delay
Each bit
All bits switched
tPLH, tPHL
TA = 25°C
-
-
35
35
SO
SO
-
35
35
SO
SO
nsec
nsec
Nonlinearity
-
±10
±50
-
±10
±50
ppmfC
Full scale current change
20 Megohm typo
-10
-
+18
-10
-
+18
Volts
IFS4
VREF = '10.000V
R14. R15=5.000U1
1.984
1.992
2.000
1.94
1.99
2.04
rnA
Full Scale Symmetry
IFSS
IFS4 -IFS2
±4.0
-
±1.0
±8.0
p.A
IZS
-
±0.5
Zero Scale Current
0.1
1.0
-
0.2
2.0
p.A
Output Curr,ent Range
IFSR
V-=-5.0V
V-=-7.0Vto-18V
0
0
2.0
2.0
2.1
4.2
0
0
2.0
2.0
2.1
4.2
rnA
mA
VIL
VIH
VLC=OV
-
-
0.8
2.0
-
0.8
-
Volts
Volts
-2.0
0.002
-10
10
-
-2.0
0.002
-10
10
p.A
p.A
+18
Volts
+13.5
-3.0
p.A
Full Scale Tempco
TCIFS
Output Voltage Compliance
VOC
Full Scale Current
TA = 25°C
Logic I."put Level~
Logic "0"
Logic "I"
Logic I nput Current
Logic "0"
Logic "1"
LogiC Input Swing
IlL
IIH
Logic Threshold Range
VIS
V THR
Reference Bias Current
115
Reference Input Slew Rate
dl/dt
Power Supply Sensitivity
PSSIFS+
PSSIFS-
Power Supply Current
2.0
VLC = OV
VIN = -10V to +0.8V
VIN = 2.0V to 18V
-
V-=-15V
-10
-
+18
-10
= ±15V
-10
-
+13.5
-10
-
-
-1.0
-3.0
-
-1.0
See Figs. 5, 27
4.0
8.0
-
4.0
8.0
V+ = 4.5V to 18V
V- =-4.5V to-18V
IREF = 1.0 mA
-
Vs
Vs = ±5V.I REF
= 1.0 rnA
1+
1Vs = +5V, -15V,
IREF = 2.0 rnA
1+
1Vs = ±15V. IREF
= 2.0 rnA
Po
±15V. IREF
10-26
-
±0.0003
±0.OO2
<0.01
±0.01
%1%
%1%
3.8
-5.B
-
2.3
-4.3
3.8
-5.8
mA
mA
-
2.4
-6.4
3.8
-7.8
-
2.4
-S.4
3.8
-7.8
rnA
rnA
2.5
-6.5
3.8
-7.8
-
2.5
-S.5
3.8
-7.8
mA
rnA
33
108
135
48
13S
174
-
33
108
135
48
136
174
mW
mW
mW
-
= 2.0 mA
±0.01
±0.01
mA/p.sec
2.3
-4.3
±5V,I REF = 1.0mA
+5V,-15V,I REF = 2.0 rnA
±0.0003
±0.002
-
Volts
-
1+
1Power Dissipation
-
-
-
-
DAC-08
ELECTRICAL CHARACTERISTICS
These specifications apply for Vs = ±15V, IREF = 2.0 mA, T A = O°C to 70°C unless otherwise specified., Output characteristics refer to both
lOUT and lOUT.
DAC·OSH
Parameter
Symbol
Conditions
DAC-OSE
Typ
Max
Min
DAC-08C
Typ
Max
Typ
Max
Units
Resolution
8
8
8
8
8
8
8
8
8
bits
Monotonicity
8
8
8
8
8
8
8
8
8
pits
±0.1
-
-
-
-
Min
Nonlinearity
TA = O°C to 70'C
-
-
Settling Time
to
To ±y, LSB, all bits
switched ON or OFF
TA = 25°C
-
85
135
Each bit
tPLH
TA = 25°C
SO
SO
35
SO
-
35
tpHL
-
35
All bits switched
35
SO
-
±10
±50
-
±10
-10
-
+18
-10
.-
85
±0.19
Min
±0.39
%FS
85
150
nsec
-
35
SO
nsec
35
SO
±50
-
±10
±80
ppml'C
+18
-10
-
+18
Volts
150
Propagation Delay
Full Scale Tempeo TCIFS
Output Voltage
Compliance
VOC
Full Scale Current
IFS4
Full scale current
change < y, LSB
ROUT> 20 Megohm
typo
1.99
2.04
1.984
1.992
2.000
1.94
IFS4 - IFS2
-
±0.5
±4.0
-
±1.0
±8.0
-
0.1
1.0
-
0.2
V-= -5.0V
0
2.0
2.1
0
2.0
V- = -7.0V to -18V
0
2.0
4.2
0
-
-
0.8
-
-
2.0
VREF = 10.000V
1.94
1.99
2.04
nsec
rnA
R'4, R'5 = 5.000k fl
TA = 25°C
Full Scale
Symmetry
IFSS
Zero Scale Current IZS
Output Current
Range
IFSR
-
±2.0
2.0
-
0.2
4.0
IlA
2.1
0
2.0
2.1
mA
2.0
4.2
0
2.0
4.2
mA
-
0.8
-
Volts
2.0
-
0.8
-
-
Volts
-2.0
-10
!LA
10
/J.A
±IS
!LA
logic Input Levels
Logic "0"
VIL
Logic "1"
VIH
LDgic Input OJrrent
VLC=OV
2.0
Logic "0"
IlL
VLC =OV
VIN = -10V to +O.8V
Logic "1"
IIH
VIN = 2.0V to 18V
Logic Input Swing
VIS
V- = -15V
-10
Logic Threshold
Range
VTHR
Vs = ±15V
-10
Reference Bias
1,5
-
-
-2.0
-10
0.002
10
-1.0
-
-2.0
0.002
10
-
-10
+18
-10
-
+18
-10
+13.5
-10
-
+13.5
-10
-3.0
-
-3.0
-
-
4.0
-
4.0
-1.0
0.002
-1.0
+18
Volts
+13.5
Volts
-3.0
!LA
Current
Reference Input
dl/dt
See Figs. 5, 27
4.0
8.0
8.0
8.0
-
Slew Rate
Power Supply
Sensitivity
mAl
J,tsec
PSSIFS+ V+ = 4.5V to 18V
PSSIFS_ V- = -4.5V to -18V
-
±0.0003
±0.01
±0.01
±0.01
%1%
±0.002
±0.01
-
±0.0003
±0.01
-
±0.0003
±0.002
±0.002
±0.01
%1%
-
2.3
-4.3
3.8
-5.8
-
2.3
-4.3
3.8
-5.8
-
2.3
-4.3
3.8
-5.8
mA
rnA
-
2.4
-6.4
3.8
-7.8
-
-
2.4
-6.4
3.8
-7.8
-
2.4
-S.4
3.8
-7.8
mA
rnA
2.5
-6.5
3.8
-7.8
mA
rnA
33
48
rnW
108
135
13S
174
rnW
mW
IREF = 1.0mA
Power Supply
Current
Vs = ±5V,
1+
1-
IREF = 1.0 mA
Vs = +5V, -15V
1+
1-
IREF =2.0 rnA
-
Vs = ±15V
1+
Power Dissipation
Po
-
2.5
-6.5
3.8
-7.8
48
-
33
48
-
13S
174
-
103
135
13S
174
-
2.5
-6.5
3.8
-7.8
±5V, IREF = 1.0 rnA
-
33
+5V,-15V, IREF =2.0
rnA
±15V, IREF = 2.0 mA
-
108
135
IREF =2.0mA
1-
10-27
I
DAC-08
TYPICAL PERFORMANCE CURVES
FIGURE 7
LSB PROPAGATION DELAY VS. IFS
FIGURE 6
FULL SCALE CURRENT VS. REFERENCE CURRENT
M
500
~~'TFOR
TA.Tml~ loT_
"0r--
\1-0-15'11
r-- ALL BITS"HIGH-
~
~ 3.0
5
V
~
11
~ 2.0
•
"""
1.0
V
oV
0
1.0
IL
V
300
200
i'\tMtT FOR
'11-> -5'11.
/
V
'00
./
~
'(' 'Lsa·61"...
M
3D
IREF. REFERENCE CURRENT (mAl
.0
'.0
lLSr7.8~A
III
.05
.01
.02
.0'
0.1
0.2
1.0
0.5
2.0
.0
FIGURE 9
REFERENCE AMP COMMON MODE RANGE
All bits ON
TA,"TmilltoTrnal
2.8
2
"",,,r
0
"'\
-2
RI4'RI!~'IIUl
RLS~O.ll
- G r - ALL snS·ON-
\
2.'
'11-'-15'\1
'\
~
-10'
0.'
O.~
1.0
'11+=+15'11
1REF"2mA
\
I.G
2
1.2
\
~EF'hnA
0.8
I
0.'
-12
011
2.0
'.0
10
-\4 -12 -10
-9
-6 -4
-2
0
2
.
'lt5. REFERENCE COMMON MODE
FREQUENCY (MHZ)
CURVE I: CC.tSpF, V'N -2.0\lp_p CENTERED AT +'.0 V.
V-~-' 'II
2.0
"\
\lR"=OV
-8
JF'O.2 •• ' - - -
G
8
10
12
I.
1618
VOLTAGE holls'
LARGE SIGNAL
CURVE 2, CC"5pF, VIN"50mVp-p CENTERED AT ..200m'll. SMALL SIGNAL
NOTE: POSITIVE COMMON MODE RANGE IS ALWAYS ('11+1-1.5 V
FIGURE 10
LOGIC INPUT CURRENT VS. INPUT VOLTAGE
FIGURE 11
VTH - V LC VS. TEMPERATURE
2.0
1.8
, ,
I.G
G.O
1.'
:=
JI.2
i"'--
.
;:, I,D
'.0
:::;-0.8
2.0
10
IrS. OUTPUT FULL SCALE CURRENT IInAI
..
-I'
0.1
~
0
FIGURE 8
REFERENCE INPUT FREQUENCY RESPONSE
-.~
:\..
100
I
O.G
0.'
0.2
0
-12 -10 -8.0 -6.0 -4.0 -2.0 0 2.0 4.0 6.0 aD 10
LOGIC INPUT VOLTAGE I,olls)
0
12
14
16
18
10-28
-'0
0
+30
TEMPERATURE, ·C
+",0
+130
DAe-os
~~-
TYPICAL PERFORMANCE CURVES
FIGURE 12
OUTPlIT CURRENT VS. OUTPUT VOLTAGE
(OUTPUT VOLTAGE COMPLIANCE)
FIGURE 13
OUTPUT VOLTAGE COMPLIANCE VS. TEMPERATURE
AlIbi.s ON
.20
...
TA"T""n1oTmo.
2.'
m
2.4
'1---15'1.
IREF-2",A
'I---5V.
2.0
+8.0
...
+011.0
I
1.2
tREF'ImA-
0.'
I
0
,4 -12 -10
.-.
-4
-2 0
2
4
OUTPUT VOLTAGE
.
12
~!lI:rJ.D_-
!lOA .,... ..... v, ....rl'::f:
,...--
,-,.SIE
-ao
fREF-C.2mA
to
8
_.....
,QIt 01'MU y ... Ott
-4.0
I
0.'
-
-
0-
-12
18
16
14
0
'0
(volts)
FIGURE 14
.l\O
TEMPERATURE reI
+100
+150
FIGURE 15
POWER SUPPLY CURRENT VS. V+
BIT TRANSFER CHARACTERISTICS
'.0
ALL BITS "HIGH" OR "LOW'
I I I
I I I
7.0
I
1-
lREF"2.QmA
1.0
]
"
i"
0.8
6,0
5.0
> 4.0
~ 3,0
.
0.6
"
fIl
ffi
0.4
0.2
-12 -10
..
q.-:.:5 V
'/-'-15'1
or..
8.0-6.0 -4.0
2.0 0
"5
2.0 4.0 6.0 8.0 10
"
f2.0
"
1.0
12
00
18
16
14
2.0
LOGIC INPUT VOLTAGE (wolls!
4.0
14
6.0
8.0
10
12
V+, POSITIVE POWER SUPPLY ('Ide I
16
18
20
ae
NOTE: BI THROUGH
HAVE IDENTICAL TRANSfER CHARACTERISTICS.
BITS ARE FULLY SWITCHED, WITH LESS THAN 112 LSB ERROR, AT
LESS THAN :llOOmV FROM ACTUAL THRESHOLD. THESE SWITCHING POINTS ARE GUARANTEED TO LIE BETWEEN 0.8 AND 2.0
VOLTS OVER THE OPERATING TEMPERATURE RANGE IVLe'C.OVI.
FIGURE 16
POWER SUPPLY CURRENT VS. V-
FIGURE 17
POWER SUPPLY CURRENT VS. TEMPERATURE
8.0
8.0
ALL BITS ·HIGH~ OR "LOW ft
BITS MAY BE "HIGH" OR MLOW~
7.0
7.0
1- W,THJREF"ZmA
'1- 0 -'5'1
6.0
1-
6.0
'''IF :2.0mA
5.0
5.0
I-WITHIREF·'mA
4.0
4.0
II
I-WITH'REF"C.2mA
'.0
3.0
'1+=+15'1
2.0
"\.!
1.0
00
"
2.0
I.
1.0
2.0
-4.0
-6.0
8.0
-10
12
-14
V-, NEGATIVE POWER SUPPLY (Wei
-I'
18
O.
-20
-'0
0
'50
TEMPERATURE ("C\
10-29
.,00
+150
OAC-08
BASIC CONNECTIONS
FIGURE 18
BASIC POSITIVE REFERENCE OPERATION
FIGURE 19
RECOMMENDED FULL SCALE ADJUSTMENT CIRCUIT
r~
• VREF --=RRJV'.EF"""'--'-<>---!
(RI.)
-=-
LOWT.C.
4.5K4
+to V
14
R15
tREF(+)~
VREF
=IV
t
SOKC
APPROX
POT.
.I,.F*
+ VREF
[FS= RREF
V-
fOR FiXED REFERENCE, TTL
1.2'56
5.0
....
OPERATION. TypiCAL VALUES
ARE,
255
DAC-08
15
~
VREF = HO.OOOV
RREF = S.OOOK
10 + YO = lFS FOR ALL
lOGIC STATES
RIS 1: RREF
Cc =O,Ot ... F
VLC =0 V (GROUND)
FIGURE 21
FIGURE 20
BASIC NEGATIVE REFERENCE OPERATION
BASIC UNIPOLAR NEGATIVE OPERATION
IREF
=2.000mA
r---::R:""R-EFW V--;14
DAC-OB
14
DAC-OB
-VREF
RIS
FULL SCALE
fULL SCALE-LSB
8182838485868788
1 1 1 1
I I 1
I I I I
1 1
HALF SCALE+LS8 I a a 0 0 0 0
HALF SCALE
I 0 0 0 0 0 0
HALF SCALE -L58 0 I , 1 I 1 1
NOTE I. RREF SETS IFS; RIS IS FOR
BIAS CURRENT CANCELLATION.
lornAIOmA
EO
1.992 .000 -9.960
1.984
--9.920
1
1,008 .984 -5.040 -4.920
1.000 .992 -5.000 -4.960
.992 1.000 -4.960 -5.000
.ooa
ZERO SCALE+L.Se 0 0 0 0 0 0 0 I
ZERO SCALE
00000000
FIGURE 22
BASIC BIPOLAR OUTPUT OPERATION
EO
a
.008 1.984
.000 1.992
.000
-.040
-.040 -9.920
.000 -9.960
FIGURE 23
SYMMETRICAL OFFSET BINARY OPERATION
+ 10.000 V
IIS8
LS8
IREF 1+)
R2.0001'\'1A
14
Eo
DAC-OB
81 B2 83 B4 85 86 81 B8
POS FULL SCALE
POS FULL SCALE-L$8
1 1 1 1 1 1 1 1
I I I 1 1 1 1 0
ZEROSCAl.E+lSB 1 0 0 0 0 0 0
ZERO SCALE
I 0 0 0 0 0 0
ZERO SCALE-l.Se 0 I 1 1 I I 1
NEG FUL.L. SCALE+LSB a 0
NEG FULL SCALE
a 0
0 0 0
0 0 0
0 0
0 0
I
Eo
Ef
BI B2 83 84B5 86 B7 88
pas
-9.92 +10.000
-9.840 + 9.920
FULL SCALE
POS FULL SCALE-LSB
-0.080 + 0.160
0.000 + 0.080
+0.080 0.000
I+> ZERO SCALE
H ZERO SCALE
NEG FULL SCALE+lSB
NEG FULL SCALE
+9.920 - 9.84
- 9.920
+ 10.000
10-30
1
1
1 1
1 1
1 1
1
o
0 0 0
1
1
1
1
+0.040
-0.040
0 00 0
0 o 0 0
o
0 1
0 0
-9.840
-9.920
1 0 o 0
0 1 1 1
o
o
1
EO
1
1
1
1 1 0
o
+9.920
+9.B40
DAe-os
BASIC CONNECTIONS
FIGURE 25
NEGATIVE LOW IMPEDANCE OUTPUT OPERATION
FIGURE 24
POSITIVE LOW IMPEDANCE OUTPUT OPERATION
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGle QAe)
CONNECT NON-INVERTING INPUT OF OP-Ato1P TO
(PIN 21; CONNECT (0
(PIN 41 TO GROUND.
iO
FOR COMPLEMENTARY OUl PUT (OPERATION AS NEGATIVE LOGIC OAe),
CONNECT INVERTING INPUT OF OP-AMP TO
(PIN 21; CONNECT 10
(PIN 4J TO GROUND.
TO
FIGURE 27
PULSED REFERENCE OPERATION
FIGURE 26
INTERFACING WITH VARIOUS LOGIC FAMILIES
VTH = VLC +1.4V
TTL,DTL
+t5V CMOS, HTL, HNIL
VTH-+l.4V
VTH-+7,6V
+15v
9.IIUl
6.2 K.o
+ "REF
ifI
~ {OPTIONAL RESISTOR
;:RRE~OR OFFSET INPUTS
CMOS, HTL, NMOS
R'N
r-----"~--4-~~~
o-~~~'~_f4
I
ov-I"L
13K!}
TYPICAL-VALUES,
R'N"5K
+V'N"O V
Rp
TOPLN 1
o.2Kfi
......
FIGURE 28
ACCOMODATING BIPOLAR REFERENCES
FIGURE 29
SETILING TIME MEASUREMENT
FOR TUfil~-ON, Vt."2..7 V Vt.
FQflTl/flN-OFF,VL"o.7V
+.4V
Vour
Lov
,.PROBESO V
-.4V
IREF!: pt;AIC NEGATIVE SWING OF I'N
FIGURE A
+~~'F~~~__~~-----'
o
"
OAc-oe
~l~V
lOO.U.T.
,"pur .,0 IOPTIONAL! 10
IMPEDANCE
V'N-<=\o-
H....
+VR£F MUST BE ABOVE PEAK POSITfVE SWING OF VIN
FIGURE 8
10-31
I
DAC-08
APPLICATIONS INFORMATION
REFERENCE AMPLIFIER SETUP
REFERENCE AMPLIFIER COMPENSATION FOR
MULTIPLYING APPLICATIONS
The DAC·OS is a multiplying D/A converter in which the
output current is the product of a digital number and the input
reference current. The reference current may be fixed or may
vary from nearly zero to +4.0mA. The full scale output current
is a linear function of the reference current and is given by:
255
IFS = X IReF where IREF = 114·
256
In positive reference applications (Fig. lS). an external
positive reference voltage forces current through R 14 into the
VREF(+) terminal (pin 14) of the reference amplifier. Alternatively, a negative reference ma,Y be applied to. VREFH at
pin 15 (Fig. 20); reference current flows from ground through
R14 into VREF(+) as in the positive reference case. This nega·
tive reference connection has the advantage of a very high
impedance presented at pin 15. The voltage at pili 14 is equal
to and tracks the voltage at pin 15 due to the high gain of the
internal reference amplifier. R15 (nominally equal to R14) is
used to cancel bias current errors; R 15 may be eliminated with
only a minor increase in error.
Bipolar references may be accomodated by offsetting VREF or
pin 15 as shown in Fig. 2S. The negative common mode range
of the reference amplifier is given by: VCM- = V- plus
(lREF X 1 Kn) plus 2.5V. The positive common mode range is
V+ less 1.5V.
When a DC reference is used, a reference bypass capacitor is
recommended. A 5.0V TTL logic supply is not recommended
as a reference. If a regulated power supply is used as a reference,
R14 should be split into two resistors with the junction
bypassed to ground with a 0.1 f,lF capacitor.
For most applications, a +10.0V reference is recommended for
optimum full scale temperature coefficient performance. This
will minimize the contributions of reference amplifier Vas
and TCVas. For most applications the tight relationship
between IREF and IFS will eliminate the need for trimming
IREF. If required, full scale trimming may be accomplished
by adjusting the value of R14, or by using a potentiometer for
R14. An improved method of full scale trimming which
eliminates potentiometer T.C. effects in shown in Fig. 19.
Using lower values of reference current reduces negative power
supply current and increases reference amplifier negative com·
mon mode range. The recommended range for operation with
a DC reference current is +0.2mA to +4.0mA.
The reference amplifier must be compensated by using a
capacitor from pin 16 to V-. For fixed riiference operation,
a 0.01 pF capacitor is recommended. For variable reference
applications, see section entitled "Reference Amplifier Com·
pensation for Multiplying Applications."
MULTIPLYING OPERATION
The DAC ·OS provides excellent multiplying performance
with an extremely linear relationship between IFS and IREF
over a range of 4 mA to 4 f,lA. Monotonic operation is main·
tained over a typical range of IREF from l00f,lA to 4.0mA;
consult factory for devices selected for monotonic operation
over wider IREF ranges.
AC reference applications will require the reference amplifier
to be compensated using a capacitor from pin 16 to V-. The
value of this capacitor depends on the impedance presented to
pin 14: for R14 values of 1.0,2.5 and 5.0Kn, minimum values
of Cc are 15, 37, and 75 pF. Larger values of R14 require
proportionately increased values of Cc for proper phase margin.
For fastest response to a pulse, low values of R14 enabling
small Cc values should be used. If pin 14 is driven by a high
impedance such as a transistor current source, none of the
above values will suffice and the amplifier must be heavily
compensated which will decrease overall bandwidth and slew
rate. For R 14 = 1 Kn and Cc = 15 pF, the reference amplifier
slews at 4 mA/f,lsec 'enabling a transition from I REF = 0 to
IREF = 2 mA in 500 nsec.
Operation with pulse inputs to the reference amplifier may be
accomodated by an alternate compensation scheme shown in
Fig. 27. This technique provides lowest full scale transition
times. An internal clamp allows quick recovery of the reference
amplifier from a cutoff (I REF = 0) condition. Full scale
transition (0 to 2 mAl occurs in 120 nsec when the equivalent
impedance at pin 14 is 200 nand Cc = O. This yields a
reference slew rate of 16 mA/f,lSec which is relatively indepen·
dent of RIN and VIN values.
LOGIC INPUTS
The DAC·OS design incorporates a unique logic input
circuit which enables direct interface to all popular logic
families and provides maximum noise immunity. This feature
is made possible by the large input swing capability, 2f,lA logic
input current and completely adjustable logic threshold
Voltage. For V- = -15V, the logic inputs may swing between
-10V and +lSV. This enables direct interface with +15V
CMOS logic, even when the DAC-OS is powered ~ from a
+5V supply. Minimum input logic swing ~nd minimum logic
threshold. voltage are given by: V- plus (lREF X 1 Kn) plus
2.5V. The logic threshold may be adjusted over a wide range
. by placing an appropriate voltage at the logic threshold control
pin (pin 1, VLC). Fig. 11 shows the relationship between VLC
and VTH over the temperature range, with VTH nominally 1.4
above VLC. For TTL and DTL interface, simply ground pin 1.
When interfacing ECL, an IREF = 1 mA is recommended. For
interfacing other logic families, see Fig. 26. For general setup
of the logic control circuit, it should be noted that pin 1 will
source 100 f,lA typical; external circuitry should be designed to
accommodate this current.
Fastest settling times are obtained when pin 1 sees a low
impedance. If pin 1 is connected to a 1 Kn divider, for
example, it should be bypassed to ground by a 0.01 f,lF capacitor.
10-32
DAC-08
APPLICATIONS INFORMATION
ANALOG OUTPUT CURRENTS
Both true and complemented output sink currents are provided,
where 10 + TO = IFS. Current appears at t~e "true" output
when a "1" is applied to each logic input. As the binary count
increases, the sink current at pin 4 increases proportionally, in
the fashion of a "positive logic" D/A converter. When a "0"
is applied to any input bit, that current is turned off at pin 4
and turned on at pin 2. A decreasing logic count increases iQ
as in a negative or inverted logic D/A converter. Both outputs
may be used simultaneously. If one of the outputs is not
required it must still be connected to ground or to a point
capable of sourcing IFS; do not leave an unused output pin
open.
Both outputs have an extremely wide voltage compliance
enabling fast direct current-to-voltage conversion through a
resistor tied to ground or other voltage source. Positive
compliance is 36V above V- and is independent of the positive
supply. Negative compliance is given by V- plus (lREF X1 Kn)
plus 2.5V.
The dual outputs. enable double the usual peak-to-peak load
swing when driving loads in quasi-differential fashion. This
feature is especially useful in cable driving, CRT deflection
and in other balanced applications such as driving centertapped coils and transformers.
POWER SUPPLIES
The DAC-08 operates over a wide range of power supply
voltages from a total supply of 9V to 36V. When operating at
supplies of ±5V or less, IREF -:; 1 mA is recommended. Low
reference current operation decreases power consumption and
increases negative compliance, reference amplifier negative
common mode range, negative logic input range, and negative
logic threshold range; consult the various figures for guidance.
For example, operation at -4.5V with IREF = 2 mA is not
recommended because negative output compliance would be
reduced to near zero. Operation from lower supplies is possible,
however at least 8V total must be appl ied to insure turn-on
of the internal bias network.
Symmetrical supplies are not required, as the DAC-08 is
quite insensitive to variations in supply voltage. Battery
operation is feasible as no ground connection is required;
however, an artificial ground may be useful to insure logic
swings, etc. remain between acceptable limits.
TEMPERATURE PERFORMANCE
The nonlinear-ity and monotonicity specifications of the
DAC-08 are guaranteed to apply over the entire rated operating
temperature range. Full scale output current drift is tight,
typically ±10 ppmtC, with zero scale output current and
drift essentially negligible compared to 1/2 LSB.
Full scale output drift performance will be best with +10.0V
references as Vos and TCVOS of the reference amplifier will
be very small compared to 1O.OV. The temperature coefficient
of the reference resistor R14 should match and track that of
the output resistor for minimum overall full scale drift.
Settling times of the DAC-08 decrease approximately
10% at -55°C; at +125°C an increase of about 15% is typical.
SETTLING TIME
The DAC-08 is, capable of extremely fast settling times,
typically 85nsec at IREF= 2.0mA. Judicious circuit design and
careful board layout must be employed to obtain full performance potential during testing and application. The logic
switch design enables propagation delays of only 35 nsec for
each of the 8 bits. Sett'ling time to within 1/2 LSB of the
LSB is therefore 35 nsec, with each progressively larger bit
taking successively longer. The MSB settles in 85 nsec, thus
determining the overall settling time of 85 nsec, Settling to
6-bit accuracy requires about 65 to 70 nsec, The output
capacitance of the DAC-08 including the package is
approximately 15 pF, therefore the output RC time constant
dominates settling time if RL > 500n.
Settling time and propagation delay are relatively insensitive
to logic input amplitude,and rise and fall times,due to the high
gain of the logic switches. Settling time also remains essentially
constant for IREF valuer down to 1.0mA, with gradual increases
for lower 'REF values. The principal advantage of higher 'REF
values lies in the ability to attain a given output level with
lower load resistors, thus reducing the output RC time constant.
Measurement of settling time requires the ability to accurately
resolve ±4 /lA, therefore a 1 Kn load is needed to provide
adequate drive for most oscilloscopes. The settling time fixture
of Fig. 29 uses a cascode design to permit driving a 1 Kn load
with less than 5pF of parasitic capacitance at the measurement
node. At IREF values of less than 1.0 mA, excessive RC
damping of the output is difficult to prevent while maintaining
adequate sensitivity. However, the major carry from 01111111
to 10000000 provides an accurate indicator of settling time.
This code change does not require the normal 6.2 time
constants to settle to within ±0.2% of the final value, and thus
settling times may be observed at lower values of IREF.
DAC-08 switching transients or "glitches" are very low
and may be further reduced by small capacitive loads at the
output at a minor sacrifice in settling time.
Power consumption may be calculated as follows:
Pd = (1+) (V+I + (1+1 (V-I + (2 IREF I (V-I. A useful feature
of the DAC-08 design is that supply current I is constant
and independent of input logic states; this is useful in cryptographic applications and further serves to reduce the size of
the power supply bypass capacitors.
Fastest operation can be obtained by using short leads,
minimizing output capacitance and load resistor values, and by
adequate bypassing at the supply, reference and VLC terminals.
Supplies do not require large electrolytic bypass capacitors as
the supply current drain is independent of input logic states;
0.1 /IF capacitors at the supply pins provide fu II transient
protection.
10-33
I
PMI
,DAC-20i
2 DIGIT BCD HIGH SPEED MULTIPLYING DAC
UNIVERSAL DIGITAL lOGIC INTERFACE
GENERAL DESCRIPTION
The DAC-20 series of 2 digit BCD monolithic multiplying
Digital-to-Analog O:mverters provide very high speed performance coupled with low eost and outstanding applications
flexibility_
Advanced circuit design * achieves 85 nsec settling times with
very low "glitch" and at low power consumption_ Monotonic
multiplying performance is attained over a wide 40 to 1
reference current range_ Matching to within 1 LSB between
reference and full scale currents eliminates the need for full
scale trimming in most applications_ Direct interface to all
p~pular logic families with full noise immunity is provided by
the high swing, adjustable threshold logic inputs_
FEATURES
_
Fast Settling Output Current ___ .. _ . . . . . . •.
85 nsec
_ Full Scale Current Prematched to ±1 lSB
_ Direct Interface to TTL, CMOS, ECl, HTL, PMOS
_ Nonlinearity to ±% lSB Max Over Temp Range
_
_
_
High Output Impedance and Compliance .. -10V to +18V
Complementary Current Outputs
Wide Range MUltiplying Capability .... 1 MHz Bandwidth
Low FS Current Drift ...... _ . _ .. _ .... ±10ppm/oC
_ Wide Power Supply Range . . . . . . . . . . _ ±4_5V to ±18V
_ Low Power Consumption .. . . . . . . . . .. 37mW @ ±5V
_ Low Cost
Dual complementary current outputs with -10V to +18V
voltage compliance enable resistive termination, a voltage
output without an external op amp_
All DAC-20 series models guarantee full 2 digit monotonicity,
and nonlinearities as tight as ±% LSB over the entire operating
temperature range are available_ Nonlinearity is unchanged over
the ±4_5V to ±18V power supply range, with 37mW power
consumption attainable at ±5V supplies_
The compact size and low power consumption make the
DAC-20 attractive for portable and military/aerospace applications; devices processed to MIL-STD-883A, Level B, are
available_
DAC-20 applications include A/D converters, audio attenuators, analog meter drivers, programmable power suppfies,
high speed modems and other applications where low cost,
high speed and complete input/output versatility are required.
ORDERING INFORMATION AND PIN
EQUIVALENT CIRCUIT
THRESHOLD CONTROL 1
lOUT 2
V- 3
lOUT 4
MSB Bl 5
B26
B37
B4B
~ONNECTION
16 COMPENSATION
15 VREFH
14 VREF(+)
13V+
12 BB LSB
11 B7
IOB6
9 B5
TOP VIEW
16 PIN HERMETIC OUAL-IN-LINE
(O-Suffix)
MODEL
TEMP RANGE
DAC-20AO
DAC-200
DAC-20EO
DAC-20CO
-55° /+125° C
_55° /+125°C
0° /70°C
0° /70°C
NONLINEARITY
±14
±y,
±14
±y,
LSB
LSB
LSB
LSB
Military Temperature Range Devices
With MIL-STD-883A Class B Processing:
ORDER: DAC20-883-AQ
DAC20-883-0
10-34
DAC-20
ABSOLUTE MAXIMUM RATINGS (T A ~ 25°C unless otherwise noted)
Operating Temperature Range
DAC-20AO,O
DAC-20 EO, CO
Storage Temperature Range
Power Dissipation
Derate above 100° C
Lead SoldPring Temperature
V+ Supply to V- Supply
Logic Inputs
-55°C to +125°C
O°C to +70°C
-65°C to +150°C
500mW
10mWtC
300° C (60 sec)
36V
V- to V- plus 36V
V- to V+
VLC
Reference Inputs (V14' V15)
V- to V+
Reference Input Differential Voltage (V 14 to V 15)
±18V
Reference Input Current {I 14)
5.0mA
ELECTRICAL CHARACTERISTICS
These specifications apply for Vs ~ ±15V. IREF ~ 2.0 mAo T A = _55'0 to +125'C for DAC-20A and DAC-20. TA = O'C to +70'C for DAC-20E
and DAC-20C, unless otherwise specified. Output characteristics refer to both lOUT and lOUT.
DAC-20A, DAC-20E
Symbol
Parameter
Resolution
Conditions
BCD
Monotoni~ity
o to 99 steps
Typ
Max
Min
Typ
Max
2
2
2
2
2
2
digits
2
2
2
2
digits
-
-
BCD 99 steps
2
2
Nonlinearity
NL
FS = 1001 1001
-
-
±1/4
Settling Time
ts
To ±V,LSB (±0.5% FSI
all bits switched ON or
OFF. TA~25'C
-
85
135
Propagation Delay
Each bit
tPLH.
tpHL
TA=25'C
TCIFS
Output Voltage
VOC
Compliance
Full Scale Current
IFS4
(Digital Input 1001 1001)
Zero Scale Current
IZS
Output Current Range
IFSR
85
Units
±1/2
LSB
150
nsec
!
All bits switched
Full Scale Tempco
DAC-20, DAC-20C
Min
Full scale current change
20 Megohm typo
I REF = 1.0mA
VREF 10.000V
R,4. R'5 = 5.000kn
TA =25'C
-
35
60
-
35
60
nsec
-
35
60
-
35
60
nsec
-
±10
±50
-
±10
±80
ppml'C
-10
-
+18
-10
-
+18
Volts
1.96
1.98
2.00
1.92
1.98
2.04
mA
-
0.1
2.5
-
0.2
5.0
itA
V- = -5.0V
0
2.0
2.2
0
2.0
2.2
mA
V- = -7.0V to -IBV
0
2.0
4.2
0
2.0
4.2
mA
-
-
0.8
-
0.8
Volts
-
-
-
2.0
2.0
-
-
Volts
logic I nput Levels
logic "0"
VIL
logic "I"
VIH
logic I nput Current
VLC = OV
VLC = OV
logic "0"
IlL
VIN = -10V to +O.8V
Logic "I"
IIH
VIN = 2.0V to lBV
logic Input Swing
VIS
V- - -15V
Logic Threshold Range
VTHR
Vs = ±15V
Reference Bias Current
1,5
dl/dt
Reference I nput Slew
-
-2.0
±10
0.002
±10
-
-10
-
+18
-10
-10
-
+13.5
-10
-1.0
-3.0
-
8.0
-
4.0
4.0
-2.0
±10
itA
0.002
±10
itA
-
+18
Volts
+13.5
-1.0
-3.0
8.0
-
Rate
Power Supply Sensitivity
Volts
itA
mAl
Itsec
PSSIFS+
V+ - 4.5V to 18V
-
±0.0003
±0.03
PSSIFS~
V- = -4.5V to -18V
-
±0.002
±0.03
-
-
2.3
-5.0
3.8
-6.5
-
2.5
-7.8
3.8
-9.1
-
±0.0003
±0.03
%1%
±0.002
±0.03
%1%
IREF = 1.0mA
Power Supply Current
Vs = ±5V, IREF = 1.0 mA
1+
1-
-
-
2.3
-5.0
3.8
-6.5
mA
mA
-
2.5
-7.8
3.8
-9.1
mA
mA
Vs = ±15V, IREF = 2.0 mA
Power Dissipation
1+
-
1-
-
Po
Vs = ±5V, IREF = 1.0 mA
Vs = ±15V, IREF = 2.0 mA
1().·35
37
52
-
37
52
mW
152
194
-
152
194
mW
I
DAC-20
BASICOU~UT
CONNECTIONS
With complementary current outputs, the DAC-20 may be
used with either positive true or negative true (complemen·
tary) logic. Curren't appears at the "true" output (10) when a
"1" is applied to a logic input. As the BCD-coded input
increases, the sink current at pin 4 increases proportionately,
in the fashion of a "positive logic" D/A converter. When a
"0" is applied to a logic input, that current is turned off at
pin 4 and on at pin 2 (~) which is used for negative true or
"negative logic" 0/A converters.
The unused output must be connected to ground or some
voltage source capable of sourcing 1.65 times I REF . A detailed
discussion of reference input operation begins on the next
page.
Both outputs have an extremely wide voltage compliance
enabling fast direct current·to·voltage conversion through a
resistor tied to ground or other voltage source. Positive
compliance is 36V above V- and is independent of the positive
supply. Negative compliance is given by V- plus (lREF
X800Q) plus 2.5V.
POSITIVE VOLTAGE OUTPUT
POSITIVE TRUE LOGIC INPUTS
r
r
MSO"
t·~ _R.J':O OIlIIK"n_M-I"
' J!!II
---..
NEGATIVE TRUE LOGIC INPUTS
LSO,
m-~
'0 4
'REf
Cc
v-
y.
iQ
y
OAe·2.
~-'VV\,--I1.
,r
5.0Kfl:
LC
r
6.00KfI:
K+
1SV
t- -
2.-~ f l+/>-4......-O,o
v~~v
~r--'\I•.•vKVn--I:.
I
+~v
-16V
DIGITAL INPUT
NORMALIZED
INPUT
0
10
MSD
LSD
0000
0000
0000
0000
0000
0000
0000
1001
0001
0010
0011
0100
1000
1001
20
30
40
SO
99 (FS)
10
0
0.20mA
0.4OmA
O.60mA
O.SOmA
1.60mA
1.9SmA
NEGATIVE VOLTAGE OUTPUT
EO
NORMALIZED
INPUT
0
+1.0V
+2.0V
+3.0V
+4.0V
+8.0V
+9.9V
0
10
20
30
40
80
99 (FS)
l
POSITIVE TRUE LOGIC INPUTS
LSO ,
·t·~Vy_R~: V:RV':vn_M••-I !mm!~
~. ~.,~ ~
+15V
r
MSD ,
Co
V
LC iQ
,f"; ,~v
U.t
DIGITAL INPUT
MSD
LSD.
1111
1110
1101
1100
1011
0111
0110
1111
1111
1111
1111
1111
1111
0110
I.,j,. ' .•Kn
V+
v.
Co
;~
VLC~
B1
f-<>'o":"
'.DOKn
0
10
20
30
40
80
99 (FS)
LSD
0000
0000
0000
0000
0000
0001
0010
0011
0100
1000
1001
0000
0000
100.1
I
0
0
0.20mA
0.4OmA
O.60mA
0.80mA
1.60mA
1.98mA
0
0.20mA
0'4OmA
O.60mA
0.80mA
1.60mA
1.9SmA
0
+1.0V
+2.0V
+3.0V
+4.0V
+8.0"
+9.9V
I.,j,.
5.K~Y
'0 4 +-
0
10
0
-1.0V
-2.0V
-3.0V
-4.0V
-8.0V
-9.9V
20
30
40
SO
99 (FS)
10-36
2
+-
"'Vr+_":Vi-'_ _-rCC:.......:VL;::,CJ
NORMALIZED
INPUT
Eo
t--o
+
t
[
-1SV
":'
iQ
15
1 .t~or.
bt-:~:. ~~Z)
B8;~
DAC-20
',,,
DIGITAL INPUT
MSD
B2 83 B4 B6 B6 87
14
1.t~·~ .~
NORMALIZED
INPUT
EO
l
·fL.·~:_R"': 'NKvn_M-l'rr1! fffr: ~ ~~Co"I't'::: (iff (ill".
r-."IVR'V'V---IO
10
N'GATIV' TRU, LOGIC INPUTS
MSS
~
'1:/>-<1>--9,0
2'/4-'----......
~.~ ~
-~v
.m
:)~
OAC·2.
y.
5,OOKf.!
~
EO (HIGH Z)
5.00KH
=
DIGITAL INPUT
MSD
LSD
i;:
1111
1110
1101
1100
1011
0111
0110
1111
1111
1111
1111
1111
1111
0110
0
0.20mA
0.4OmA
O.60mA
O.SOmA
I.SOmA
1.9SmA
EO
0
-1.0V
-2.0V
-3.0V
-4.0V
-8.0V
-9.9V
DAC-20
REFERENCE OPERATION
POSITIVE
r
MSBf
'REF
--+
+v REF ....
VREF1+)
,.
5
NEGATIVE
_lSD"-\
MSO "",
f f f• f f f
6
9
7
10
"
flsB
--
•
DAC-20
VREFH
~
MSBf
12
RREF
IA14)
,.
R1S
,.
l
£""'
--+
~
'0
O.1pF
I
-=
'::' v-
DAC-20
R'.
l
-=O.1/JF
FOR ALL LOGIC
.
~JJ ~
I
O.lpF
-= v1iREF"
I
V+-
'='
V REF '" +10.000v
RREF = S.OOOKn
R,. '" RREF
Cc
=O.Ol$o1f
10 + iQ '" IREF x 1.65
FOR ALL lOGIC
= 1001 1001
2
,
13
"
1 - -VREF X 99
FS 100
FS
INPUT STATES
+-iO
,.
VREFH
-V REF .....--
FOR FixeD REFERENCE, TTL
iQ '" IREF X 1.65
• _'0
RREF
OPERATION, TYPICAL VALUES
ARE:
99
IFS"'~X 100
ylSB
10 11 12
9
7
(R14)
v+
+vREF
f f f• f f f
,.• •
VREF1+)
~Jr·:~
O.lpFI
10 +
I~EF
,-;;
2
,
13
,-LSO .....
r MSO "",,\
FOR FiXeD REFERENCE TTL
OPERATION, TYPICAL VALUES
ARE:
V REF = -10.000V
RREF '" 5.000Kn
R,. ",RREF
= O.Ol#<1 f
Cc
'= 1001 1001
FS
INPUT STATES
REFERENCE AMPLIFIER SETUP
The DAC-20 is a multiplying D/A converter in which the
output current is the product of a digital number and the
input reference current. The reference current may be fixed or
may vary from nearly zero to +4.0mA. The full scale output
current is a linear function of the reference current and is
given by:
IFS = 99/100 X IREF where IREF = 114'
..
..
In positive reference applications an external positive
reference voltage forces current through R14 into the VREF(+)
terminal (pin 14) of the reference amplifier. Alternatively, a
negative reference may be applied to VREFH at pin 15;
reference current flows from ground through R14 into
VREF(+) as in the positive reference case. This negative
reference connection has the advantage of a very high
impedance presented at pin 15. The voltage at pin 14 is equal
to and tracks the voltage at pin 15 due to the high gain of the
internal reference amplifier. R 15 (nominally equal to R 14 ) is
used to cancel bias current errors and may be eliminated with
only a minor increase in error.
When a DC reference is used, a reference bypass capacitor is
recommended. A 5.0V TTL logic supply is not recommended
as a reference. If a regulated power supply is used as a
reference, R14 should be split into two resistors with the
junction bypassed to ground with a 0.1J.LF capacitor.
For most applications, a +10.0V reference such as the PMI
REF-01 is recommended for optimum full scale temperature
coefficient performance. This will minimize the contributions
of reference amplifier Vos and TeVos' For most applications
the tight relationship between IR EF and IFS will eliminate the
need for trimming IREF . If required, full scale trimming may
be accomplished by adjusting the value of R14.
The reference amplifier must be compensated by using a
capacitor from pin 16 to V-. For fixed reference operation,
a 0.01 J.LF capacitor is recommended. For variable reference
applications, see section entitled "Multiplying Operation."
TYPICAL REFERENCE PERFORMANCE CURVES
REFERENCE AMP COMMON MODE RANGE
(DIGITAL INPUT 1001 10011
FULL SCALE CURRENT VS. REFERENCE CURRENT
(DIGITAL INPUT 1001 10011
'.0
TA"Tmm,o Tmo.
,.S
T",'Tmi"
'.0
"! "
~
2.0
a
1.6
v-.-" . .
v
V-'-5
I
IRE,,'2rnA
~ 3.0
IREF'lmA
.;
~
~
~
§ 1.2
0.8
~ 2.0
I
10
V
IRJ.o.2mA-
0.'
0
-14 -12 -10
-8 -6 -4
-2
o
2
4
6
8
10
V15, REFERENCE COMMON MOOE VOLTAGE holTs!
12
"
16
\1-'-1''''
1
V+'+I5V
I
1~~nFoR
'0 Trno.
i--f-
oV
18
0
./
1.0
L
V
V
V
r"--~I!,~~~~.R
'.0
3.0
IRE'" REFERENCE CURRENT {rnA!
NOTE: Positive common mode range is always (V+)-1.5V;
negative common mode range is V- plus(J REF X
./
'.0
5.0
NOTE: The recommended range for operation with a DC
reference current is +O.2mA to +4.0mA.
800n) plus 2.5V.
10-37
I
DAC-20
LOGIC INPUT OPERATION AND INTERFACING
TTL,OTL
VTH"+1.4V
ECl
CMOS, HTl, NMOS
V+
*
13Kn
"A"
39Kn
20Kn
,-Tt-..
~2N390~
"A,,~2N3904
VTH
2N3904
3Kn
L-~--o
6.2Kn
+15V CMOS, HTL, HNIL
TO PIN 1
VlC
11:
=VLC +1.4 V
20Kn
VTW+7.6V
2N3904
3KU
TO PIN 1
VlC
+15 V
R3 400llA
9.IKn
'------l
DAC-20
,f15
OPTIONAL RESISTOR
FOR OFFSET INPUTS
fRREF
~
,
"'N
+'REF'" PEAK NEGATIVE SWING OF 'IN
"EO
.,,2oot!
ovJL
FIGURE A
,.
"p
R1N"'SK
500n.
Full scale output drift performance will be best with +10.0V
references as VOS and TCVOS of the reference amplifier will
,'be very small compared til 10.0V. The temperature coefficient
of the reference resistor R14 should match and track that of
the output resistor for minimum overall full scale drift.
Settling times of the DAC·20 decrease approximately 10% at
_55°C; at +125°C an increase of about 15% is typical.
Fastest operation can be obtained by using short leads,
minimizing output capac~tance and load resistor values, and by
adequate bypassing at the supply, reference and VLC terminals.
9.Jpplies do not require large electrolytic bypass capacitors
as the supply current drain is independent of input logic
states;, 0.1 JlF capacitors at the supply pins provide full
transient protection.
I
10-41
IOAe-l0ol
PMI
8 & 10 BIT DIGITAL-TO-ANALOG CONVERTER
GENERAL DESCRIPTION
FEATURES
The DAC-l00 is a complete 10 bit resolution Digital-toAnalog converter constructed on two monolithic chips in a
single 16-pin DIP or 24-pin flatpack. Featuring excellent nonlinearity vs. temperature performance, the DAC-l00 includes a
low tempco voltage reference, 10 current source/switches a\1d
a high stability thin-film R-2R ladder network. Maximum
application flexibility is provided by the fast current output
and by matched bipolar offset and feedback resistors wh ich
are included for use with an external op amp for voltage output applications. Although all units have 10-bit resolution, a
wide choice of nonlinearity and tempco options is provided to
allow price/performance optimization.
The small size, wide operating temperature range, low power
consumption and high reliability construction make the
DAC-100 ideal for aerospace applications. Other applications
include use in servo-positioning systems, X-Y plotters, CRT
•
•
Complete •.• _ .• _ ••.• _ .. ___ Internal Reference
Flexible .•• _ .. ___ • ____ .. _ .. Oto2mAOutput
•
•
Fast Settling .• _ . 225nsec (8 Bits), 375nsec (10 Bits)
Stable ... _ •• _ . _ • _ . Tempcos to ±15ppmfC Max
•
0°C/+70°C, -25°C/+SSoC, -55°C/+125°C Models
Available
•
•
TTL and DTL Compatible Logic Inputs
Wide Supply Range ____ .•. _ .•• __ ±6V to ±1BV
•
•
8 and 10 Bit Versions Available
MIL-STO-883A Class B Processing Models Available
•
Low Cost 03, Q4 Series
displays, programmable power supplies, analog meter movement drivers, waveform generators and high speed Analog-toDigital converters.
S.IMPLIFIED SCHEMATIC AND PIN CONNECTIONS - 16 LEAD HERMETIC DIP
, . . - - - - - - - - - DI8'TM. LoelCllfflurs - - - - - - - - - - ,
"For 10V or ±5V Operation
RS = 4.88kn (Package
01,03,05 )
For 5V or ±2.5V Operation,
RS = 2.44kn (Package
02,040r06)
,"U.L~~~~
..-
.....
SCALE
".
"Qu Series
Simplified Schematic
ft,
IIPOt..AIIi
"pr.
TOP VIEW
"'0""
V-2
otrfPUT~
La...
II fLlLLSCALE KU
,.
v+
II MSII
lilT"
12m2
liT"
II.IITI
.IT..
&ITT T
16 PIN HERMETIC
DUAL-IN-LiNE
(O-Suffix)
•
ItIIRII
fULLSCALlMN •
IOMT4
'"ts
fI"
.0-..........._.-
A.. II
".12
10-42
24 PIN HERMETIC
FLATPACK
(N-Suffix)
DAC-100
GENERAL INFORMATION
FULL SCALE TEST CIRCUIT
1_ The DAC-100 series are digital-to-analog current converters; voltage outputs are implemented by usipg an
external operational amplifier with the internally-provided
feedback resistor_ For clarity and convenience, most speeifications will reference full scale output voltage rather than
full scale output current, assuming an "ideal" op amp has
been utilized for conversion (See test circuit at right).
2- The logic coding used for driving the DAC-100 should be
complementary binary or offset complementary binary to
obtain unipolar and bipohir analog outputs, respectively.
3. As shown in the ordering information below, the
DAC-100 series provides a wide variety of worst-case nonlinearity and fu II-scale tempco combination options. All
devices have 10 bits of resolution; the nonlinearity options
of ±O.05%, ±O.l%, ±0.2% and ±0.3% guarantee monotonic
operation for resolutions of 10,9,8, and 7 bits respectively.
When less than the full 10 bits are utilized, the unused logic
inputs must be connected to a "high" logic level (>2.1 V).
DEFINITION: Full Scale Tempco is defined as the change in output
voltage measured in the circuit above and is expressed in ppm between
25° C and either temperature extreme divided bV the corresponding
temperature change.
NOTE: Since RS precisely tracks the internal R-2R ladder network
over temperature, the absolute IFS Tempco of ±120ppmfC is
cancelled by RS when the output voltage is used as in the above circuit
ORDERING INFORMATION
~i~"ANG'
NONLINEARITY
A
B
C
D
F.S. TEMPCO
A
B
C
D
±0.05%MAX
±0.1%MAX·
±0.2% MAX
±0.3%MAX
PACKAGE
a
15 ppm/oC MAX
30 ppm/"C MAX'
60 ppm/o C MAX
120 ppmfC MAX
AND OUTPUT VOLTAGE
16 Pin HERMETIC DUAL-IN-LiNE
24 Pin HERMETIC FLATPACK
N
as shown below
'NOTE: For DAC-100 BB05 and DAC-100 BBOS only; nonlinearity is ±0.1% over _25°C to +85°C and ±0.12% over -55°C to +12SoC.
Full Scale Tempco is 30 ppm/oC over -25°C to +85°C and 40 ppml"C over -55°C to +125°C.
COMBINATION AVAILABILITY CHART (Temperatura Range/Package Option Suffixl
_55° /+125° C
B83A Class B
Model
_25°/+85°C
0° /+70°C
10V
±5V
5V
±2.5V
10V
±5V
5V
±2.5V
N9
01
02
-
-
-
N9
01
02
-
-
06
N9
01
02
03
04
06
N9
01
02
-
-
06
N9
01
02
03
04
05
06
N9
01
02
03
04
-
-
N9
01
02
03
04
10V
±5V
5V
±2.5V
-
DAC-100A8
-
DAC-100AC
05
DAC-100BB
05
DAC-100BC
05
DAC-100CC
DAC-100DD
DAC-l00AA
_25°/+85°C
883A Class B
10V
±5V
5V
±2.5V
10-43
I
DAC-109
ABSOLUTE MAXIMUM RATINGS
o to +36V
V+ Supply to V- Supply
V+ Supply to Output
V- Supply to Output
Logie Inputs to Output
Power Dissipation (Note 1 )
Oto +18V
Oto-18V
~lV to +6V
500mW
NOTES:
1. Rating applies to ambient temperature of 100°C. Above
100°C, derate at 10mWfC.
Operating Temperature Range
03,04
All others
O°C to +70°C
-55°C to +125°C
Storage Temperature Range
o and N Packages
-65°C to +l50°C
Lead Temperature (Soldering)
o and N Packages
+300 DC (60 sec)
ELECTRICAL CHARACTERISTICS
These specifications apply for Vs = ±15V. -25°C" TA ,,+85°C for 01,,02. and N9 devices; O°C" TA "+70°C; for 03 and 04,
-55°C" T A" +125°C for OS and 06 devices, unless otherwise specified. (SeeBBOS, 06 note on previous page under Ordering Information.)
Parameter
Min
Conditions
Resolution
Nonlinearity
(For nonlinearity/tempco
combinations, see
Availability chart.)
Full Scale Tempco
(See Full Scale
Test Circuit.)
"A" option (±% LSa -10 bits)
"a" option (± % Lsa -9 bits)
"c" option (± % LSa -8 bits)
Typ
Max
10
10
10
-
-
:I: 0.05
-
Units
bits
-
± 0.1
± 0.2
± 0.3
%I FS
%I FS
% I FS
%I FS
:I: 15
ppm/DC
± 30
± 60
ppmtC
ppm/DC
ppm/DC
"0" option (±% LSa -8 bits)
-
"A" option
"a" option
"c" option
"0" option
-
-
%120
-
Settling Time
to ±(}.05% FS
-
375
ns
to ±0.1% FS
-
-
TA = 25°C
-
300
225
ns
to ±0.2% FS
-
to ±0.4% FS
-
-
150
ns
-
100
ns
-
11.1
5.55
V
to ±0.8% FS
Full Scale Output Voltage
(Limits guarantee adjustability
to exact 10.0 (5.0) V with a
200nITrimpot®lb~tween
FS Ad·u·,rt·."n1-1
.7
EIOSS-OO
ENCODE
14
ENCODE OUT: E'DSB~ 11
13
NEGATIVE POWER SUPPt y
VR!+}
11
POSITIVE REFERENCE INPUT
Vee
10
THRESHOLD CONTROL
VRH
NEGATIVE REFERENCE INPUT
TOP VIEW
18 PIN HERMETIC DUAL-IN-LINE
DAC-76
ABSOLUTE MAXIMUM RATINGS
V+ Supply to V- Supply
36V
Operating Temperature
Analog Current Outputs
V- to V+
Power Dissipation
500mW
10mWfC
Derate above 100° C
1.25 mA
V- plus 8V to V- plus 36V
Logic Inputs
-65°C to +150°C
Storage Temperature
±18V
Reference Input Differential Voltage
Reference Input Current
DoC to +70°C
DAC-76E, DAC-76C
V- plus 8V to V- plus 36V
Reference Inputs
-55°C!0 +125°C
DAC-76B, DAC-76
V- plus 8V to V+
V LC Swing
300°C (60 sec)
Lead Soldering Temperature
OUTPUT CURRENT DC TEST CIRCUIT
.,
LINE SELECTION TABLE
-t15V
2
+ VREF
DIGITAL INPUTS
1.'94~~L ~~!~~~:~;ID "
r
(RREFl
'~
20~1~
(+)
DEVICE
+
100 (+,
100(-1
v-
\1+
EOI
•
-ISV
=
I.
+15V
VLC
2 _ 7
+t5V
3 ~-O1
.VREF IS ADJUSTED BEFORE TESTING EACH DEVICE
TO PROVIDE IDEAL FULL SCALE OUTPUT CURRENT.
ENCOOEI
OECOOE
•
R4
1
1
1
10E (+1
1
0
10E H
(E01/R21
3
0
1
100 (+1
(E02/R31
4
0
0
100H
(E02/R41
(E01 /R11
6
NOTE:-Accuracy is specified in the test circuit using the
tables below to be within the specified proportion of a step
E02
-15V
=
OUTPUT
MEASUREMENT
SIGN
BIT
2
0'
17
~.~. '~
-ISY
TEST
GROUP
6
02
locH 15
Vo H UNDER TEST
13~
:
3 OP-07A
lOft+1
11 VR
-
at the maximum value in each chord. Monotonic operation is
RI= R2-R3=R4=2.SKn
guaranteed for all input codes.
CONDENSED CURRENT OUTPUT TABLES
IDEAL DECODE OUTPUT CURRENT IN MICROAMPS AT CHORD ENDPOINTS
~D
STEP
0
15
I
I
0
1
2
3
4
5
6
7
000
001
010
011
100
101
110
111
0000
0
8.25
24.75
57.75
123.75
255.75
519.75
1047.75
1111
7.5
23.25
54.75
117.75
243.75
495.75
999.75
2007.75
0.50
1
2
4
8
16
32
64
STEP SIZE
IDEAL ENCODE OUTPUT CURRENT IN MICROAMPS AT CHORD ENDPOINTS
:::-------::0
STEP
0
1
2
3
4
5
6
7
000
001
010
011_
100
101
110
111
0
I
0000
0.25
8.75
25.75
59.75
127.75
263.75
535.75
1079.75
15
I
1111
7.75
23.75
55.75
119.75
247.75
503.75
1015.75
2039.75
0.50
1
2
4
8
16
32
STEP SIZE
64
SPECIFICATION PARAMETER DEFINITIONS
STEP NONLINEARITY: Step size deviation from ideal
withih a chord.
CHORDS: Groups of linearly-related steps in the transfer
function. Also known as segments.
ENCODE CURRENT: The difference between 10E (+) and
100 (+) or the difference between 10E (-) and 100 (-) at any
CHORD ENDPOINTS: The maximum code in each chord.
Used to specify accuracy.
code.
STEPS: Increments in each chord which divide it into 16
equal levels.
FULL SCALE DRIFT: The change in output current over
the full operating temperature with VREF = 10.000V,
R11 = 18.94Kn, and R12 = 20Kn.
OUTPUT LEVEL NOTATION: Each output current level
may be designated by the code IC.s where C = chord
number and S = step number. For example. 10,0 = zero
scale current; 10,1 = first step from zero; 10.15 = endpoint
of first chord (Co); 17 ,15 = full scale current.
FULL SCALE SYMMETRY ERROR: The difference between 100 Hand 100 (+) or the difference between 10E (-)
and 10E (+) at full scale output.
DYNAMIC RANGE: Ratio of the largest output (17.15)
to the smallest output excluding zero (10.1) expressed in
dB. This can be measured peak or peak-to-peak with the
same result.
OUTPUT VOLTAGE COMPLIANCE: The maximum out·
put voltage swing at any current level which causes <1/2
step change in output current.
11-5
I
DAC-76
BASIC ENCODE OPERATION (COMPRESSING AID CONVERSION)
BASIC ENCODE CONNECTIONS
ENCODE TRANSFER CHARACTERISTIC
(AID CONVERSION)
DIGITAL
OUTPUT (+)
7
6
4
3
2
5
,
ANALOG
INPUT (-)
0
ANALOG
INPUT (+)
0
1
2
3
~""
OUTPUT H
only. The Encode/Decode (E/D) input is held at a logic "0".
Therefore, no current flows into the encode outputs, and the com~
parator is effectively disconnected from the DAC. Once the input
polarity has been determined, the E/D input is changed to a logic
"1" allowing current to flow into IOE(+) or IOE(-) depending upon
ENCODE DECISION LEVELS
Compressing AID conversion with the DAC·76 requires a comparator, an exclusive-or gate, and a successive approximation
register-the usual elements in any sign·plus-magnitude AID converter. However, a compressing ADC has one significant difference
from regular AID converters.
the Sign Bit Answer.
For positive inputs, current flows into 'OE(+) through R1. and the
In a conventional (linear) converter, the step size is a constant
percentage of full scale, but in a compressing AID converter, the
step size increases as the output changes from zero scate to full
scafe. The standard 1/2 step bias used in conventional ADC's to keep
quantizing error below ±1/2 step cannot be easily furnished by the
user of a compressing ADC. For this reason, the DAC has a 1/2 step
greater output in the encode mode than it has in the decode mode.
This may be seen clearly by comparing the normalized encode and
decode output tables at any code paint.
comparator's output will be entered as the answer for each successive
decision. For negative inputs, current flows into 'OE(-) through
R2 developing a negative voltage which is compared with the analog
input. An exclusive-or gate inverts the comparator's output during
negative trials to maintain the proper logic coding, all ones for full
scale and all zeros for zero scale. (A more complete schematic is
shown in the applications section.)
The bits are converted with a successive removal technique. starting
with a decision at the code 011 1111 and turning off bits sequentially
until all decisions have been made. Successive removal is necessary
because the 1/2 step encode decision level current is drawn from the
sum node, rather than sourced into it.
ENCODING SEQUENCE
An encoding sequence begins with the Sign Bit comparison and
decision. During this time the comparator is a polarity detector
NORMALIZED ENCODE LEVEl (SIGN BIT EXCLUDED)
~
STEP
IC,S = 2[2C (S+17)-16.51
C = chord no. (0 through 7)
S = step no. (0 through 15)
0
1
2
3
4
5
6
7
000
001
010
011
100
101
110
111
0
0000
1
35
103
239
511
1055
2143
4319
1
0001
3
39
111
255
543
1119
2271
4575
2
0010
5
43
119
271
575
1183
2399
4831
3
0011
7
47
127
287
607
1247
2527
5087
4
0100
9
51
135
303
639
1311
2655
5343
5
0101
11
55
143
319
671
1375
2783
5599
6
0110
q
59
151
335
703
1439
2911
5855
6111
7
0111
15
63
159
351
735
1503
3039
8
1000
17
67
167
367
767
1567
3167
6367
9
1001
19
71
175
383
799
1631
3295
6623
10
1010
21
75
183
399
831
1695
3423
6879
11
1011
23
79
191
415
863
1759
3551
7135
12
1100
25
83
199
431
895
1823
3679
7391
13
1101
27
87
207
447
927
lBB7
3807
7647
14
1110
29
91
215
463
959
1951
3935
7903
15
1111
31
95
223
479
991
2015
4063
8159
2
4
8
16
32
64
128
256
STEP SIZE
11-6
DAC-76
BASIC DECODE OPERATION (EXPANDING D/A CONVERSION)
DECODE TRANSFER CHARACTERISTIC
(D/A CONVERSION)
BASIC DECODE CONNECTIONS
ANALOG
OUTPUT (+)
67
)
5
o 1 23
DIGITAL
INPUT (-)
DIGITAL
INPUT (+)
43 2 I 0
5
IDEAL VALUES:
iREF"528,.A
IFS·2007,7S ... A
6
7
,/0
POS FULL SCALE
ANALOG
OUTPUT H
It) ZERO SCALE +1 STEP
It} ZERO SCALE
HZEROSCAlE
H ZERO SCALE +1 STEP
NEG FULL SCALE
DECODE OPERATION
0
0
1
1
1
0
0
0
.,
B2
B3
B4
.,
••
.7
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
1
0
0
1
1
'0
5,019V
0.0012
ov
ov
-0.0012
-5.019V
the number of steps.
operational amplifier connected to the decode outputs as a balanced
load. The decode mode of operation is selected by applying a logic
"0" to the Encode/Decode input. This enables the 100 outputs,
disables the 10E outputs, and allows 100(+) or 100(-) to be
selected by the Sign Bit input. When the Sign Bit input is high, a
logic "1", all of the output current flows into 'OO(+} forcing a
positive voltage at the operational amplifier's a"utput. When the Sign
Bit input is low, a logic "0", all of the output current flows into
BASIC REFERENCE CONSIDERATIONS
Full scale output current is ideally 2007.75J,LA when the reference
current is 528,u.A in the decode mode. In the encode mode it is
2039.75IlA because the additional 1/2 step adds 321'A to the
output. A percentage change in 'REF caused by changes in VREF
or RR EF will produce the same percentage change in output current.
'OO(-} through R2 forcing a negative voltage output. Since the
Sign Bit only steers current into 100(+) or 100(-), the output will
always be symmetrical, limited only by the matching of Rl and R2.
The large step size at full scale allows the use of inexpensive refer·
ences in many applications. In some situations VREF may even be
the positive power supply. For example, with V+ = 15V, RREF =
15V/528jLA or 28.4KI1. When using a power supply as a reference,
Rll should be two resistors, RllA and R11B. and the junction
should be bypassed to ground to provide decoupling.
NORMALIZED TABLES
The encode and decode tables may be used to calculate ideal output
current at any code point. For example, in decode mode at 13,7
NORMALIZED DECODE OUTPUT (SIGN BIT EXCLUDED)
STEP
0
sa
(011 0111) find 343. 343/8031 times IFS of 2007.751'A equals
85.75J,LA. Alternatively, use the condensed current tables and add up
D/A conversion with the DAC-76 may be illustrated by using an
~
0
0
0
C = chord no. (0 through 7)
S = step no. (0 through 15)
IC,S = 2[2 C (S+16.5) -16.51
D
1
2
3
4
5
6
7
000
001
010
011
100
101
110
111
4191
0
0000
0
33
99
231
495
1023
2079
1
0001
2
37
107
247
527
1087
2207
4447
2
0010
4
41
115
263
559
1151
2335
4703
3
0011
6
45
123
279
591
1215
2463
4959
4
0100
8
49
131
295
623
1279
2591
5215
5
0101
10
53
139
311
655
1343
2719
5471
6
0110
12
57
147
327
687
1407
2847
5727
7
0111
14
61
155
343
719
1471
2975
59B3
8
1000
16
65
163
359
751
1535
3103
6239
9
1001
18
69
171
375
783
1599
3231
6495
10
1010
20
73
179
391
815
1663
3359
6751
11
1011
22
77
187
407
847
1727
3487
7007
12
1100
24
81
195
423
879
1791
3615
7263
13
1101
26
85
203
439
911
1855
3743
7519
14
1110
28
89
211
455
943
1919
3871
7775
15
1111
30
93
219
471
975
1983
3999
8031
2
4
8
16
32
64
128
256
STEP SIZE
11-7
I
DAC-76
REFERENCE AMPLIFIER OPERATION
POSITIVE REFERENCE OPERATION
REF-OI
+IOV
RIIA
=
9?8?~6? ~4?3?2? *
,d, RIIB
I 18_94 Kil
=- (RREF)
TOTAL
DIGITAL INPUTS
DIGITAL INPUTS
NOTE I
_OI~F
NEGATIVE REFERENCE OPERATION
87 8685 84 8382 Bl 58 UO
~
[REF
f'
~'"RI2
VR
(+)
DAC-76
12 R
H
V-
20K.a
V+
'~~.
IJ,
-15V
VREF
[REF' RREF
+15V
DECODE OUTPUTS
IDEAL VALUES,
'REF'528,A
[FS" 2007.75,A
14 +-
"',.:~'"'1
15 +-
OUTPUTS
[Op(+) 16 +[ODH 17 +VLC /
DECODE
OUTPUTS
[OE(-)
ENCODE OUTPUTS
IDEAL VALUES,
'REF"528"A
[FS ' 2039.75,A
NOTE 1: RECOMMENDED WHEN VREF IS V+ OR THE LOGlC POWER SUPPLY.
NOTE 2 PINS 11 AND 12 ARE eQUAL IN VOLTAGE VREF IS IMPRESSED
ACROSS Rl1 (RREF)
~4?3?2? *
9?8?ff6?
B7 B6 B5 B4 B3 82 81 58 E/O\'4 +10E(+) \,5 +~~f~3~s
(RREF)~ VR (+)
10E(-)
~
IREF
DAC-76
[00(+) 16 +NOTE I
12
100H/17 +g~~~~\S
"H
VLC /
R12
vV+
20KIl
13
18~
-VREF
+15V
-15V
DECODE OUTPUTS
ENCODE OUTPUTS
[REF'- (-VREF)
-RREF
IDEAL VALUES,
IDEAL VALUES,
[REF'528,A
[REF'52B"A
[FS' 2007.75~A
[FS ' 2039.75~A
RII
18_94KIl
+
X,
:f
6
'1
NOTE 1: PINS 11 AND 12 ARE EQUAL IN VOLTAGE. VREF IS IMPRESSED
ACRuSS Rt 1 IR REF ).
REFERENCE AMPLIFIER SETUP
REFERENCE RECOMMENDATIONS
The DAC-76 is a multiplying D/A converter in which the
output current is the product of the normalized digital
input and the input reference current. The reference currerit
may be fixed or may vary from nearly zero to +1.0mA. The
full scale output current is a linear function of the reference
current and is given for all four outputs in the figures above.
For most applications a +10.0V reference, such as the PMI
REF-01, is recommended for optimum full scale temperature coefficient performance. (This also minimizes the
contributions of reference amplifier Vos and TCVos.) For
most applications the tight relationship between IREF and
IFS eliminates the need for trimming IREF;' but if desired,
full scale trimming may be accomplished by selecting Rll
or by using a potentiometer for Rll.
In positive reference applications an external positive reference voltage forces current through Rll into the VR (+)
terminal (pin 11) of the reference amplifier. Alternatively,
a negative reference may be' applied to VR (-) at pin 12;
reference current flows .from ground through Rll into
VR (+1. as in the positive reference case_ This negative
reference connection has the advantage of a very high
impedance presented at pin 12_ The voltage at pin 11 is
equal to and tracks the voltage at pin 12 due to the high
gain of the internal reference amplifier. R12 (nominally
equal to R 11) is used to cancel bias current errors and may
be eliminated with only a minor increase in error.
Using lower values of reference current reduces negative
power supply current and increases reference amplifier
negative common mode range. While the recommended
operating range of DC reference currents is O.1mA to
1.0mA, monotonic operation is maintained over an even
wider range allowing the DAC-76 to be used in many
multiplying applications. For variable reference applications, see section entitled "Multiplying Operation."
TYPICAL PERFORMANc;E CURVES
REFERENCE AMPLIFIER INPUT COMMON MODE RANGE
OUTPUT FULL SCALE CURRENT VS.
REFERENCE INPUT CURRENT
5.0
TA·TminloTma~
2.8
TA~Tmin'oTITI(I~
4.0 -
~
ALL BITS "HIGH" -
/'
C
.§
~
ffi
3.0
~
-
/'
~
~
g
.....
2.0
1.0
0
~
/'
L
/'
2.'
V-~-15V
./
V.·+15V
2.0
,.•
~
I
IREF.O,~mA
'.2
I
0.8
I REF =O.2!5mA
i
I
I
0,4
0.'
0,. 12
'.0
IREF. REFERENCE CURRENT (rnA)
• •
10 -8 -6 -4 -2
8 10 12
2
0
REFERENCE COMMON MODE VOLTAGE AT VREF PIN (volts)
NOTE: POSITIVE COMMON MODE RANGE IS ALWAYS (V+)-1.5 V
11-8
'4
16
IB
DAC-76
TRUE CURRENT OUTPUT OPERATION
RESISTIVE OUTPUT CONNECTIONS
BALANCED LOAD CONNECTIONS
REF-OI
+'Ov
DIGITAL INPUTS
r-----~A~------~
"EF-02
DIGITAL INPUTS
+5V
r------'A~--__,
4.9
KA
4.98
Kil
"A- 4.98
r-"=-;;.....-o
Kil
'8'
II a:J
'c'
TYPICAL BALANCED LOADS
NEGATIVE OUTPUT VOLTAGE
OUTPUT VOLTAGE (V)
INPUT CODE
"A"
"8"
"C"
DIFF
11110111'
+5.02
NfA
NIA
110000000
+10.00
N/AI
COMPLIANCE VOC (-)
11111 1111
01111"1'
01'10'11'
01000 0000
000000000
NfA
-5.00 +5.00
+0.02 +5.00
+5.00 +5.00
+5.00 +5.00
-10
-4.98
+4.98
001101111
+5.00
+0.02
00 111"11
+5.00
-5.00
~
1.0mA
2.0mA
4.0mA
-12V
-2.BV
-2.0V
-O.4V
-15V
-5.BV
-5.0V
-3.4V
-18V
-8.BV
-8.0V
-S.4V
V OC (-) MIN = IV-}+(2I REF • 1.6Kn) + 8.4V
• CRT
• CURRENT INPUT FILTER
• TRANSMISSION LINE
• SERVO
THE SUM OF THE COMMON MODE
VOLTAGE AND THE DIFFERENTIAL
VOLTAGE ACROSS THE LOAD
SHOULD BE WITHIN THE -5V TO +18V
OUTPUT VOLTAGE COMPLIANCE
SPECIFICATION.
High common mode output range is possible due to the
wide output voltage compliance and allows use with transformers or other balanced loads. The terminating impedances may be located a distance away from the DAC-76
allowing transmission of analog quantities as currents rather
than voltages and elimination of ground loop errors.
Capacitive termination is also possible, performing an
"integrate-and-hold" process which is a function of V REF '
RREF' the digital input code, and the selection time for a
given current output_ Resetting of the integrating capacitor
may be accomplished with a CMOS switch in parallel with.
the capacitor. Thus, many applications traditionally requiring op amps may be performed with a high voltage compl iance, current output DAC.
and balanced loads. Positive voltage compliance is +18V,
and negative voltage compliance is -5.0V with IREF =
=
• SAMPlE-AND-HOLD
"0
The DAC-76 has true current outputs with wide voltage
compliance enabling fast drive of a variety of single-ended
5281lA and V-
• OAC REFERENCE INPUT
• BRIDGE
• OP AMP
NOTE:
MINIMUM NEGATIVE COMPLIANCE
0
• TRANSFORMER
• TRANSDUCER
• EARPHONE
-15V. Negative voltage compliance for
other values of IREF and V- may be calculated using the
table above. Typical connections, both single-ended and
differential, are shown in the figure above with output
voltage tables. Note the differential sign-plus-magnitude
relationship between "8" and "C"_ The differential output
voltage is independent of the +5.00 nominal voltage source
as long as the Vae (-) minimum values are observed.
TYPICAL PERFORMANCE CURVES
OUTPUT CURRENT VS. OUTPUT VOLTAGE
(OUTPUT VOLTAGE COMPLIANCEI
OUTPUT VOLTAGE COMPLIANCE VS. TEMPERATURE
TA~TrnintoTmall
V-:-t5V
2.8
2."
2.0
I..
1.2
r-+--I--+---+--+---j-
I
lREPO.25rnA
r
0.8
I
0.4
°_14 -12
10
-8
-6
-4
-2
0
2
4
6
8
10
12
t4
16
18
OUTPUT VOLTAGE (volt&)
11-9
I
DAe-76.
MULTIPLYING OPERATION
LOW INPUT IMPEDANCE CONNECTION
IIIEF~
"IH
VREF
RiN + "AeF
HIGH INPUT IMPEDANCE CONNECTION
'"
"REF-V IN
IfS ~ 41REF
IREF·~
In ~ "IREF
LOGARITHMIC DIGITAL GAIN CONTROL
REFERENCE AMPLIFIER DYNAMIC TEST CIRCUIT
NOTE 1: LOW DISTORTION OUTPUTS ARE PROVIDED OVER A nd8 RANGE.
NOTE 2: UP T04 CHANNElS OF OUTPUT MAY BE SELECTED SV clD ANO
sa LOGIC INPUTS.
TYPICAL PERFORMANCE CURVES
REFERENCE AMPLIFIER TOTAL HARMONIC
DISTORTION VS. FREQUENCY
(80 KHz FILTER)
05~
REFERENCE AMPLIFIER INPUT
FREQUENCY RESPONSE
INPUT 5VPEAK
ISO'1(, MODULATIONI
,
lllllWlJ
,
-,
.,
1111
SMPlL~
111111
SIGNAL
100 MVI'EAK
11% MOOULATIONI
I
-.
-.
I~
(:~J~~::~\
,I
l,,"
"
"
"
,oo'~L.~-"".,-'--'-'''',~J.IJ!~oo!'-,---',:",!:-,..J....'-::':!:-,~:,:-',-!i,""~-'-':-;,'"','"":'~~:-,-!~2~:-,oW'"!.,:,:",.l.'!!~~
"
fAWUEPlCY
TOO
200
50D
1.0
Hz
Hz
H.
~H.
" " '" '"
'"
FREOUENCY
NOTE ,. THO IS NEAR LV INDEPENDENT OF lOGIC INPUT CODE
_
NOTE 2: SIMILAR RESUl T5 ARE OBTAINED FOR A HIGH INPUT IMPEDANCE CONNECTiON
USING PIN 12 ASAN INPUT.
NOTE 3: INCREASED OISTORTlCN ABOVE 5OkH. IS DUE TO SLEW RATE LIMITING
WHICH DETERMINES LARGE SIGNAL BANDWIDTH FOR AN INPUT OF
'2 5V PEAK (25% MODULATION). BANDWIOTH IS 100kHz
11-10
500
1.0
,.
5.010
DAC-76
LOGIC INPUT AND POWER SUPPLY CONSIDERATIONS
LOGIC INPUTS
INTERFACING CIRCUIT FOR
ECL. CMOS. HTL. & NMOS LOG IC INPUTS
CMOS,HTl NMOS
~'"
v.
13Kl!
"1\"
39K!~
The DAC-76 may be interfaced with other-than· TT L logic by
placing VLC( (pin 10) at a potential which is I.4V below the desired
logic input switching threshold. However, this voltage source must
be capable of sourcing and sinking a changing current at pin 10.
The negative voltage at the logic inputs must be limited to +10V
with respect to V- (pin 13).
ZOK ~:
~
,,-
"A"
".
20K ~!
---0
lOPIN 10
v"
!~
3K~.
L
1
As shown in the curves below, power supply current drain is
~roPINlO
"
6.21(~!
POWER SUPPLIES
,,v"
~.'
relatively independent of voltage and temperature and completely
independent of the logic input states.
When operating with V- between -15V and -11 V, output negative
voltage compliance, VOCH. reference input amplifier common
mode voltage range, and logic input negative voltage range are
J.
J,.
reduced by an amount equivalent to the difference between -15V
and the V- supply in use. Operation with V+ between +5V and
+15V affects VLC and the reference amplifier common mode
positive voltage range in the same manner.
NOTE 1: SlOT THE VOLTAGE "A" TO BE AT THE DESIRED LOGIC INPUT SWITCHING THRESHOLD.
NOTE 2: ALLOWABLE RANGE OF LOGIC THRESHOLD IS TYPICALLY -5'1 TO +13.5'1 WHEN
OPERATING THE DAC 76 ON '15'1 SUPPLIES.
TYPICAL PERFORMANCE CURVES
BIT TRANSFER CHARACTERISTICS
0.'
LOGIC INPUT CURRENT VS. INPUT
VOLTAGE AND LOGIC INPUT RANGE
I
I
0.30
I
.,
IREF:0.5 mA
0.25
0.244
20
~
r--
iREF"0.5mA
V-=-15V
VLC~OV
~
z
w
0.20
~
~
u
0 - V-i-ll
't-
-eo -6,0 -4.0
.,
'2V
l
5.0
.2
0.05
-12 -10
I
§
0.10
I
10
~
0.15
0.055
0.023
2.0 0
2.0 4.0 60 •. 0 10
LOGIC INPUT VOLTAGE (~olls)
14
12
16
IB
0
-12
Non;· ALL BITS ARE FULLY SWITCHED WITH LESS THAN 1/2 STEP ERROR AT
SWITCHING POINTS WHICH ARE GUARANTEED TO LIE BETWEEN 0.8V AND
2.0'1 OVER THE OPERATING TEMPERATURE RANGE
10
ao
2.0 0
2.0 4.0 6.0
10
LOGIC INPUT VOLTAGE (volts)
B.O --6.0 -4.0
12
14
16
NOTE LOGIC INPUT VOLTAGE RANGE IS INDEPENDENT OF THE POSITIVE POWER
SUPPLY AND LOGIC INPUTS MAY SWING ABOVE THE SUPPLY
POWER SUPPLY CURRENTS VS.
POWER SUPPLY CURRENTS VS. TEMPERATURE
POWER SUPPLY VOLTAGES
•. 0
•. 0
,Jv--r-----
ALL BITS MHIGH" OR "LOW"
IFS:2.0mA
7.0
ALL BITS "HIGH" OR "LOW"
VS=±15V
,-
7.0
6.0
6.0
5.0
5.0
IFS~2.0mA
4.0
4.0
I+VS.V+
3.0
r-----
3.0
2.0
2.0
1.0
1.0
00
2.0
4.0
6.0
•. 0
10
12
14
16
1.
0
20
POSITIVE OR NEGATIVE POWER SUPPLY (Vdc)
IT
-50
0
+50
TEMPERATURE t·C)
11-11
+100
-1-150
I.,
DAC-76
DETAILED ENCODE CONNECTIONS
CLOCK
.r
iT.iRT
"L
r--
.J, ~f
GROUND
'0'
~~'tGElf
INPUTS
SUCCESSIVE
AP:~I~~:J'ON CCI-'2~+_0~ '1..
iiiSi"
AM2502
PARALLEL
DIGITAL
OUTPUTS
tr.~$~=~~=il
CHORD BITS
NOTES
1. CONNECT~. TO
START FOR
CONTINUOUS OPERATION.
2. FOR NON-CONTINUOUS OPERATION, HOLD ffiRT
LOW FOR ONE CLOCK CYCLE. CONVERSIONS
BEGIN ON THE NEXT LOW TO HIGH TRANSITION
OF THE CLOCK AFTER S'fAR'T GOES HIGH.
L--------''lIi
3. CONVERSION IS COMPLETED IN 9 CLOCK
CYCLES.
f/OS8 B1B2B3B4B586 87
VR<+I
OAe-76
I"","",""'="'-1
'-nf'--:ir'-"''''T'-IH''
r~:·
TRANSCEIVING CONVERTER - TWO WAY DATA TRANSMISSION
TO
ANALOG
INPUT
ANALOG
OUTPUT
ANALOG
OUTPUT
TRANSCEIVING CONVERTER
TRANSCEIVING CONVERTER
SERIAL DATA TRANSCEIVING CONVERTER
1112 OF SYSTEM SHOWN)
.I"
TRANSMIT INPUT
:i:!5VANALOGIH
SEND/RECEIVE
-t!5V
CLOCK
"L
START
COMMAND
HtGW5ENO
LOW=RECEIVE
TIME5HARED
BI-DIRECTIONAL
*~n5
r--
~W.NOFOR
DIFFERENTIAL
INPUTS'
r-+---.-+-+--t-------.,="~ij~tAL
DATA
~i
NOTES:
1. COMPLEMENTARY SEND/RECEIVE COMMANDS ARE
REaUIRED FOR THE TWO ENDS.
2.
s=fART MUST BE HelD LOW FOR ONE CLOCK CYCLE
TO BEGIN A SEND OR RECEIVE CYCLE,
REF·O\
't'IOV
3, THE SAR IS USED AS A SERIAL· IN/PARALLEL OUT
REGISTER IN THE RECEIVE MODE.
4. CLOCK AND START MAY BE CONNECTED IN
PARALLel AT BOTH ENDS.
5. CONVERSION IS COMPLETED IN 9 CLOCK CYCLES,
~~:ES~HTlAL<>-_ _',tOD (+)
CURRENT
OUTPUT
11-12
6. RECEIVE OUTPUT IS AVAILABLE FOR ONE fULL
CLOCK CYCLE
DAe-?6
TYPICAL SIGNAL TO QUANTIZING DISTORTION CURVES
SIGNAL TO QUANTIZING DISTORTION VS. INPUT LEVEL
(C·MESSAGE WEIGHTING FILTER & BELL SPEC)
SIGNAL TO QUANTIZING DISTORTION VS. INPUT LEVEL
(3 kHz FLAT FILTER)
.
.
I
I
40-TA~25C
40
~
Vs - ·15V
"
"
~
'/
/
"
~
24
~
!Sl20
a~
16
~
/
12
28
~ 12
~
8
.
4
·56 ·60
.
." ." ,
·40
·35
·30
-"
-20
-"
INPUT LEVEL IdB)
-10
-5
I"-
V-
I--
:F~
V
8
.
.
-
t-- "//
--
BELL D3SVSTEM SPECIFICATION
/
2
:i:
/
20
/i
~ 32
'/
"
DAc,;...
36
/
28
I
r- :: :2~5~
4
-56
-60
-55
-50
..,
-40
-J6
-'"
-25
-20
-"
-10
-5
INf>UTLEVEL(dBI
.
NOTES:
NOTE: OdS IS . 3.SV. +3dB IS -S.OVOR FULL SCALE CODE (1111111).
1. OdB IS !3.5V. +3dB IS ~5.0V OR FULL SCALE CODE (111 1111).
2. C·MESSAGE WEIGHTING FILTER PROVIDES A FREQUENCY RESPONSE
CHARACTERISTIC WHICH SIMULATES THE PERCEIVED RESPONSE Of THE'
HUMAN EAR TO TELEPHONE NOISE.
Note' QuantIZing distortion IS the difference between the origmal Signal and the processed signal (i.e .. after encoding and decodmg),
SIGNAL TO QUANTIZING DISTORTION TEST CIRCUIT
BLOCK DIAGRAM
OPEN FOR NOISE TEST
CLOSE FOR SIGNAL TEST
l
H'3551A
AUDIO TEST
ANALYZER
1kHz
TONE
SAMPLE
AND
HOLD
DAC-76
AID
8BIT
LATCH
3.4kHz-'-
DAC-76
(S,nXIIX
DfA
LOW PASS
FILTER
H'3551A
1 kHz NOTCH
FILTER
AUDIO TEST
ANALYZER
NOTES:
1.8 kHz SAMPLING CONDITIONS: 62.S,.,5e(: SAMPLE PERIOD. 62.S,.,se<: AID CONVERSION TIME.
2. AUDIO TEST ANALYZER CONTAINS A C·MESSAGE FILTER AND A 3 kHil' FLAT FILTER.
OUTPUT COMPLIANCE EXTENSION CONNECTIONS
±10V RANGE ENCODE/DECODE CONNECTIONS
COMPLIANCE EXTENSION USING
AC COUPLED OUTPUT
Rl
2.5KD.
.n
TOA/O
CONVERSlOiII
LOGIC
Rn
18.94KD.
(RREF)
18.MK!!
RREF
."
lOKI!
\"REF
IREF S RREF
IDEAL VALUES:
IREF=!l28_A
IFS" 2001.1!1,..A
11-13
.;. 5V
!
I
DAC·76
EXTENSION TO SIGN PLUS 78dB DYNAMIC RANGE
EXTENDED RANGE CONNECTIONS
SUMMARY TABLE FOR
3 CHORD BITS AND
5 STEP BITS
DIGITAL INPUTS
STEP
RE~-(
.
+10V
CHORD
STEP
(IlA)
0
to
7.75
0.625
0
to
0.019
1
0.5
8.25
to
23.75
1.25
0.021
to
0.059
2
1.0
24.75
to
55.75
2.5
0.062
to
0.139
3
2.0
57.75
to
119.75
5.0
0.144
to
0.299
4
4.0
123.75
to
247.75
10
0.309
to
0.619
5
8.0
255.75
to
503.75
20
0.639
to
1.259
IDEAL VALUES:
EXTENDED RANGE OPERATION
QtJtput current to insert. additional levels halfway between each
step_ By connecting 100(+) to 10E(+) and 100H to 10EH, the
EID logic input functions as a fifth step bit input. Full scale positive
RANGE
(V)
0.25
lREF"528~A
now becomes 1 111 11111; full scale negative is 0 111 11111. Each
chord is divided into 32 steps instead of the former 16 steps,
STEP
(mV)
0
IFS =2039.75 p A
When used as a O/A converter only, the OAC-76 range may be
extended from sign + 72dB to sign + 78dB by using the encode
RANGE
(IlA)
6
16
519.75
to
1015.75
40
1.299
to
2.539
7
32
1047.75
to
2039.75
80
2.619
to
5.099
effectively increasing dynamic range by 6dB.
The accompanying table summarizes the new chord and step charM
acteristics obtained in the extended connection shown above.
ADDITIONAL DECODE OUTPUT TABLES
IDEAL DECODE OUTPUT CURRENT IN MICROAMPS (SIGN BIT EXCLUDED)
~
STEP
0
1
2
3
4
5
6
7
000
001
010
011
100
101
110
111
0
0000
0
8.25
24.75
57.75
123.75
255.75
519.75
1047.75
1
0001
0_5
9.25
26.75
61.75
131.75
271.75
551.75
1111.75
2
0010
1
10.25
28.75
65.75
139.75
287.75
583.75
1175.75
3
0011
1.5
11.25
30.75
69.75
147.75
303.75
615.75
1239.75
4
0100
2
12.25
32.75
73.75
155.75
319.75
647.75
1303.75
5
0101
2.5
13.25
34.75
77.75
163.75
335.75
679.75
1367.75
6
0110
3
14.25
36.75
81.75
171.75
351.75
711.75
1431.75
7
0111
3.5
15.25
38.75
85.75
179.75
367.75
743.75
1495.75
8
1000
4
16.25
40.75
89.75
187.75
383.75
775.75
1559.75
9
1001
4.5
17.25
42.75
93.75
195.75
399.75
807.75
1623.75
10
1010
5
18.25
44.75
97.75
203.75
415.75
839.75
1687.75
11
1011
5.5
19.25
46.75
101.75
211.75
431.75
871.75
1751.75
12
1100
6
20.25
48.75
105.75
219.75
447.75
903.75
1815.75
13
1101
6.5
21.25
50.75
109.75
227.75
463.75
935.75
1879.75
14
1110
7
22.25
52.75
~13.75
235.75
479_75
967.75
1943.75
15
1111
7.5
23.25
54.75
117.75
243.75
495.75
999.75
2007.75
1
2
4
16
32
64
STEP SIZE
.50
11·14
8
DAC-76
CHORD SIZE SUMMARY TABLE DECODE OUTPUT (SIGN BIT EXCLUDED)
CHORD ENDPOINTS
NORMALIZED
TO FULL SCALE
CHORD
CHORD ENDPOINTS
IN IlAWITH
2007.751lA F.S.
CHORD ENDPOINTS
ASA PERCENT
OF FULL SCALE
CHORD ENDPOINTS
IN dB DOWN
FROM FULL SCALE
0
30
7.5
0.37%
-48.55
1
93
23.25
1.16%
-38.73
2
219
54.75
2.73%
-31.29
3
471
117.75
5.86%
4
975
243.75
12.1%
-18.32
-24.63
5
1983
495.75
24.7%
-12.15
6
3999
999.75
49.8%
-6.06
7
8031
2007.75
0
100%
DECODE OUTPUT EXPRESSED IN DB DOWN FROM FULL SCALE (SIGN BIT EXCLUDED)
~
STEP
0
1
2
3
4
5
6
7
000
001
010
011
100
101
110
111
-5.65
0
0000
-
-47.73
-38.18
-30.82
-24.20
-17.90
-11.74
1
0001
-72.07
-46.73
-37.51
-30.24
-23.66
-17.37
-11.22
-5.13
2
0010
-66.05
-45.84
-36.88
-29.70
-23.15
-16.87
-10.73
-4.65
-4.19
3
0011
-62.53
-45.03
-36.30
-29.18
-22.66
-16.40
-10.27
4
0100
-60.03
-44.29
-35.75
-28.70
-22.21
-15.96
-9.83
-3.75
5
0101
-58.10
-43.61
-35.24
-28.24
-21.77
-15.53
-9.41
-3.33
6
0110
-56.51
-42.98
-34.75
-27.80
-21.36
-15.13
-9.01
-2.94
7
0111
-55.17
-42.39
-34.29
-27.39
-20.96
-14.74
-8.63
-2.56
8
1000
-54.01
-41.84
-33.85
-26.99
-20.58
-14.37
-8.26
-2.19
9
1001
-52.99
-41.32
-33.44
-26.61
-20.22
-14.02
-7.91
-1.84
10
1010
-52.07
-40.83
-33.04
-26.25
-19.87
-13.68
-7.57
-1.51
11
1011
-51.25
-40.37
-32.66
-25.90
-19.54
-13.35
-7.25
-1.18
12
1100
-50.49
-39.93
-32.29
-25.57
-19.22
-13.03
-6.93
-0.87
13
1101
-49.80
-39.51
-31.95
-25.25
-18.91
-12.73
-6.63
-0.57
14
1110
-49.15
-39.11
-31.61
-24.94
-18.61
-12.43
-6.34
-0.28
15
1111
-48.55
-38.73
-31.29
-24.63
-18.32
-12.15
-6.06
a
DECODE OUTPUT EXPRESSED IN PERCENT OF FULL SCALE (SIGN BIT EXCLUDED)
~
STEP
a
1
2
3
4
5
6
7
000
001
010
all
100
101
110
111
a
0000
0'
0.411
1.23
2.88
6.16
12.7
25.9
52.2
1
0001
0.025
0.461
1.33
3.08
6.56
13.5
27.5
55.4
58.6
2
0010
0.050
0.511
1.43
3.27
6.96
14.3
29.1
3
0011
0.075
0.560
1.53
3.47
7.36
15.1
30.7
61.7
4
0100
0.100
0.610
1.63
3.67
7.76
15.9
32.3
64.9
5
0101
0.125
0.660
1.73
3.87
8.16
16.7
33.9
68.1
6
0110
0.149
0.710
1.83
4.07
8.55
17.5
35.5
71.3
74.5
7
0111
0.174
0.760
1.93
4.27
8.95
18.3
37.0
8
1000
0.199
0.809
2.03
4.47
9.35
19.1
38.6
77.7
9
1001
0.224
0.859
2.13
4.67
9.75
19.9
40.2
80.9
10
1010
0.249
0.909
2.23
4.87
10.1
20.7
41.8
84.1
11
1011
0.274
0.959
2.33
5.07
10.5
21.5
43.4
87.2
12
1100
0.299
1.01
2.43
5.27
10.9
22.3
45.0
90.4
13
1101
0.324
1.06
2.53
5.47
11.3
23.1
46.6
93.6
14
1110
0.349
1.11
2.63
5.67
11.7
23.9
48.2
15
1111
0.374
1.16
2.73
5.86
12.1
24.7
49.8
0.025
0.050
0.100
0.199
STEP SIZE
11-15
0.398
0.797
1.59
96.8
100
--
3.19
•
DAC-76
APPLICATIONS
The DAC-76 is ideal in applications which require a wide
dynamic range and can be characterizerl by an accuracy
specification based on percent of reading rather than percent of full scale. The nonlinear characteristic is also useful
in control systems when a decreasing slope or a constant
rate of change (constant second derivative) is needed as a
system approaches zero level or a given set point.
INSTRUMENTATION AND CONTROL
Data Acquisition - Data Transceiver
Microprocessor Interface
PCM Data Recording - Biological, Automotive, Aviation
Function Generation
PCM Telemetry
Servo Controls - Phase Locked Loop and Set Point Controls
Transducer Interface - Seismic, Strain Gauge
TE LECOMMUN ICA TlONS
Telephony - PCM Codec
Two-Way Radio
Intercom Systems
Radar Systems
Secure Voice Communications
11-16
AUDIO
Music Distribution
Digital Recording
Constant dB Attenuator
Analog Multiplexer
Digitally-Controlled Gain
Voice Synthesis and Identification
Variable Speed Recording and Playback
Reverberation and Special Effects
ADDITIONAL CIRCUIT APPLICATIONS
Logarithmic Attenuator
Pour Quadrant Multiplier
line Driver
dB Meter
Analog or Digital Compressor and Expander
Four Channel Multiplexer
I
NUMERICAL INDEX
I
ORDERING INFORMATION
la.A. PROGRAM
IINDUSTRV CROSS REFERENCE
FUNCTIONAL REPLACEMENT GUIDE
I,OPERATIONAL AMPLIFIERS
I:
COMPARATORS
I
MATCHED TRANSISTORS
IVOLTAGE REFERENCES
lOlA CONVERTERS - LINEAR
lOlA CONVERTERS - COMPANDING
MULTIPLEXERS
IDEFINITIONS
ICHIPS
IAPPLICATION NOTES
I
PACKAGE INFORMATION
I
NOTES
OJ
IT]
rn
rn
rn
II]]
1[1]
rn
IT]
ffiJ
[[]
12
Ill]
r:m
rnJ
Ii]
1m
INDEX
MULTIPLEXERS
PRODUCT
TITLE
MUX-88
Protected 8 Channel BI-FET Analog Multiplexer
PAGE
12-1
IMUX-ool
PMI
PROTECTED 8 CHANNEL BI-FET ANALOG MULTIPLEXER
GENERAL DESCRIPTION
FEATURES
The MUX-88 is a monolithic 8 channel analog multiplexer
which connects a single output to 1 of the 8 analog inputs
depending upon the state of a 3-bit binary address. Disconnection of the output is provided by a logical "0" at the
enable input, thereby providing a package select function.
Fabricated with Precision Monolithics' high performance BI·
FET technology, this device features overvoltage protection
that is fail safe with power loss, while offering low, constant
"ON" resistance. Performance advantages include low leakage
currents and fast settling time with low crosstalk to satisfy a
wide variety of applications. This multiplexer does not suffer
from latch-up or static charge blow·out problems associated
with similar CMOS parts. The digital inputs are designed to
operate from both TTL and CMOS levels while always providing a definite break-before-make action without the need for
external pullup resistors.
FUNCTIQNAL DIAGRAM AND TRUTH TABLE
ENABLE A2
A1
•
Pin Compatible With DG508, HI-508A, LFl150B
•
JFET Switches Rather Than CMOS
•
No Static Discharge Blow-out Problem
•
No SCR Latch-up Problems
•
Analog Inputs Overvoltage Protected ±20V Beyond
Normal Ratings
•
Fail Safe With Power Loss
•
Low "ON" Resistance . . . . . . . . . . . . . 220n TYP
•
Low Output Leakage Current . . . . . . 100nA MAX
•
Digital Inputs Compatible With TTL and CMOS
.No Pullup Resistors Required To Insure
Break-Before-Make Action With TTL Inputs
PIN CONNECTIONS AND ORDERING INFORMATION
AO
AD 1
v+
v-
sa
87 86 S5 84 83 52
A2
A1
AO
EN
X
X
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
L
H
H
H
H
H
H
H
H
15 A2
ENABLE 2
GND
DRAIN
16 A1
81
V- 3
14 GND
814
13 V+
825
12 S5
836
11 86
847
1087
9
DRAIN 8
sa
TOP VIEW
"ON"
CHANNEL
16 PIN HERMETIC DUAL-IN-LINE
IO-Suffix)
NONE
1
2
3
4
S
6
7
8
12-1
MODEL
TEMP RANGE
MUX-88AO
MUX-88BO
_SSOc TO +12SoC
-5SoC TO +12SoC
MUX·88EO
MUX-88FO
-2Soc TO +8Soc
-2Soc TO +8Soc
I
MUX-88
ABSOLUTE MAXIMUM RATINGS
(T A = 2SoC unle.s~ otherwise noted)
Operating Temperature Range, MUX-88AO, 80
Operating Temperature Range, MUX-88EO, FO
Storage Temperature Range
Power Dissipation
Derate above 100° C
Lead Soldering Temperature
Max Junction le'mperature
150°C
V+ Supply to V- Supply
3SV
V+ Supply to Ground
18V,
Logic Input Voltage
-4V to V+ Supply
Analog Input Voltage
V- Supply -20V to V+ Supply +15V
Max Current Through Any Pin
25mA
-1.0 MIL INSIDE SCRIBE
LINE ANO POINTS TOWARD
r ___~~_"",,....--F_R_O_M_O_P_E_R_A_T",,IN_G_M_E_T_A_L_L_IZ_A_T_10""N.---{,_ _~_OP,-"E.;,RATlNG METALLIZATION
ACCEPT: CRACK <1.0 MIL
INSIDE SCRIBE
LINE
SCRIBE GRIO
OR SCRIBE LINE
lin
Y
REJECT: CRACK IN
ACTIVE
CIRCUIT AREA
REJECT: CRACK >5.0 MIL
IN LENGTH
SCRIBING AND DIE DEFECTS
FIGURE 4
3.3.4 Overcoat
Overcoat is defined as a dielectric layer (glassivation) applied after metallization. No device shall be considered
acceptable which exhibits any overcoat void which bridges any two operating circuit metallization areas or any
operating circuit metallization to bare silicon. No device shall be acceptable that has glassivation covering more
than 50% of any active bonding pad.
3.3.5 Probing
All bonding pads shall be inspected for evidence of probing. Any die having any active unprobed bonding pads
shall be rejected.
3.3.6 Dimensions
The length and width dimensions of the chip shall be inspected and must be within ±.003" of the catalog
dimensions.
14-5
I
CMP-Ol
FAST PRECISION COMPARATOR
ABSOLUTE MAXIMUM RATINGS
CHIP LAYOUT AND DIMENSIONS
_65°C to +150°C
Junction Temperature (Tj)
Total Supply Voltage, V+ to V-
66 MilS
36V
Output to Ground
Inv
Input
50V
Ground to Negative Supply Voltage
30V
Positive Supply Voltage to Ground
30V
Positive Supply Voltage to Offset Null
*NC
I
±llV
Input Voltage (V s ; ±15V)
±15V
Output Short Circuit Duration - to ground
'------N-U{.~I-N-'~~'''----~~-ut~
Indefinite
to V+
1 min.
ELECTRICAL SPECIFICATIONS AT 25°C
These specifications apply for
Vs =
Parameter
41 MILS
•• :-:J
75 mA
Differential Input Voltage
/
Ground
Ot02V
Output Sink Current (Continuous Operation)
.1
V--·. •••••• l
-5V to +32V
Output to Negative Supply Voltage
Non Inv
Input
CMP01·N
CMP01·G
±15V unless otherwise noted.
Symbol
Test Conditions
Min
Max
-
-
2.S
Units
Input Offset Voltage
VOS
Input Offset Current
lOS
-
25
-
SO
Input Bias Current
IB
-
600
-
900
nA
-
Mn
RS'; 5 kn
1.0
±12.5
-
±12.5
-
V
94
-
90
-
dB
SO
-
74
-
dB
2.4
-
-
-
V
Yin ;> 3mV, 10 = 240l'A
-
-
2.4
-
V
Rin
CMVR
Common Mode Rejection Ratio
CMRR
VCM = ±CMVR
Power Supply Rejection Ratio
PSRR
5V .; Vs + ';lSV
-lSV .; Vs - ';OV
Positive Output Voltage
VOH
Vin;> 3mV, 10 = 320l'A
-
0.45
-
0.45
V
-
4.0
-
S.O
I'A
Vin'; -10mV
--
S.O
-
8.5
mA
Vin'; -10mV
-
2.2
-
2.2
mA
Saturation Voltage
VSAT
Isink = 6.~ mA
Output Leakage Current
ILEAK
Vin;> 10mV, Vo = 30V
Positive Supply Current
1+
Negative Supply Current
1-
Power Consumption
Po
-
Vin'; -10mV
Input Offset Voltage
Vas
1nput Offset Current
lOS
Symbol
Average I nput Offset Voltage Drift
TCVos
Average Input Offset Current Drift
TClos
Response Time
(TA =+25°CI
tr
153
-
161
mW
= OV unless otherwise noted.
-
RS'; 5 kn
1.5
-
TYPICAL ELECTRICAL CH.ARACTERISTICS (VS; ±15V)
Parameter
nA
-
Inp'ut Voltage Range
Vs-
mV
3.0
Differential I "put Resistance
These specifications apply for VS+ = SV and
O.S
Max
Min
Test Conditions
RS
=50n
21
14-6
3.5
-
65
CMP01·N
CMP01-G
Typical
Typical
1.5
100mV step, 5mV overdrive
no load (no pull-up)
-
1.S
mV
nA
Units
I'vrc
35
40
pAloC
90
90
nsec
CMP-02
LOW INPUT CURRENT PRECISION COMPARATOR
CHIP LAYOUT AND DIMENSIONS
ABSOLUTE MAXIMUM RATINGS
-65°C to +150°C
Junction Temperature (Tj)
Total Supply Voltage, V+ to V36V
Output to Ground
-5V to +32V
Output to Negative Supply Voltage
50V
Ground to Negative Supply Voltage
30V
Positive Supply Voltage to Ground
30V
Positive Supply Voltage to Offset Null
o to 2V
Output Sink Current (Continuous Operation)
75 mA
Differential Input Voltage
±llV
Input Voltage (VS = ±15V)
±15V
Output Short Circuit Duration - to ground
Indefinite
to V+
1 min.
66 MILS
I~
Inv
Input
V--· •••.••
ONC/
Ground
••N~II
I
Null
Vas
\
Out
CMP02-G
Test Conditions
Max
Min
Max
Min
Rs" 5 kn
-
0.8
-
RS .. 50 kn
Units
2.8
mV
3.0
mV
-
0.9
-
lOS
-
3.0
-
15
-
-
100
nA
-
Mn
:"
'nput Offset Current
:- :J
noted.
Symbol
Input Offset Voltage
1
41 MILS
CMP02-N
= ±15V unless otherwise
Parameter
•
/
ELECTRICAL SPECIFICATIONS AT 25°C
These specifications apply for Vs
Non Inv·1
Input
Input Bias Current
IB
Differential Input Resistance
Rin
50
nA
5.0
-
1.5
±12.5
-
±12.5
-
V
94
-
90
-
dB
80
-
74
-
·dB
Input Voltage Range
CMVR
Common Mode Rejection Ratio
CMRR
VCM
Power Supply Rejection Ratio
PSRR
5V .. VS+ .. 18V
-18V" Vs - ..OV
Positive Output Voltage
VOH
Yin ;;. 3mV, 10
= 320"A
2.4
-
-
-
V
Yin ;;. 3mV, 10
= 240"A
-
-
2.4
-
V
-
0.45
-
0.45
V
-
4.0
-
8.0
"A
-
8.5
mA
-
2.2
mA
= ±CMVR
= 6.4 mA
Saturation Voltage
VSAT
Isink
Output Leakage Current
ILEAK
Vin;;' 10mV, Vo
= 30V
Positive Supply Current
1+
Vin" -10mV
-
8.0
Negative Supply Current
1-
Vin" -10mV
-
2.2
PD
Vin" -10mV
-
Power Consumption
These specifications apply for VS+
Input OUset Voltage
Input Offset Current
=
153
-
161
mW
5V and Vs- = OV unless otherwise noted.
Vas
RS" 5 kn
lOS
TYPICAL ELECTRICAL CHARACTERISTICS (VS = ±15V)
Parameter
Symbol
Average Input Offset Voltage Drift
TCVos
Average I nput Offset Current Drift
TClos
Response Time
(TA = +25'C)
tr
Test Conditions
RS
=
50n
1OOmV step, 5mV overdrive
no load (no pull-up)
14-7
-
1.5
-
-
3.0
-
3.5
14
mV
nA
CMP02-N
CMP02-G
Typical
Typical
Units
1.5
1.8
"VrC
4.0
5.0
pArC
160
160
nsec
I
DAC-O!
6 BIT MONOLITHIC D/A CONVERTER
ABSOLUTE MAXIMUM RATINGS
CHIP LAYOUT AND DIMENSIONS
_65°C to +150°C
to +18V
to -18V
-0.7 to +6V
Indefinite
Junction Temperature (Tjl
V+ Supply Voltage to Ground
V- Supply Voltage to Ground
Logic Input to Ground
Output Short Circuit Duration
"NC
Symbol
Parameter
Nonlinearity
88 MILS
Bit 1
MSB
8it2
• •• • •,.
//\\
•
"NC
V-
Unpolarl
Sum
Scale
Bipolar
Node
Factor
Vs
= ±15V
,
=±15V
Internal Reference Voltage
VMCR
Vs
Zero Scale Voltage
VZS
Vs = ±15V
Analog
Ground
Output
.,
. . .....
MILS
.................
j+
./
,,\LS\
-.......ait3
Bit 4
Bit 5
DAC01·N
BIPOLAR AND
UNIPOLAR
Test Conditions
-----j
J...~--~-------..i--'
Trim
NOTE: Short circuit may be to ground or either supply.
Rating applies to +l50°C chip temperature.
ELECTRICAL SPECIFICATIONS AT 2SoC
.
1-\
..
. .---'----
o
o
Min
Max
-
±0.4
Bit 6
DAC01·GR
UNIPOLAR
ONLY
Min
Max
Units
-
±0.4
%
6.65
6.76
6.4
6.9
V
-
±.021
-
±.035
V
ELECTRICAL SPECIFICATIONS AT 2SoC IN COMMON TO ALL GRADES
These specifications apply for
Vs = ± 15V
unless otherwise noted.
Parameter
Test Conditions
Unipolar Full Scale Output
Voltage (All Models)
Min
2Kn load, logic" O.OV. short V-to Full Scale Trim, Unipolar/
Bipolar to Ground, and Scale Factor to Sum· Node.
Bipolar Output Voltage
±5 Volt Range (Except
DAC-01·GRI
VFS+
VFS±10 Volt Range (Except
DAC·01·GR)
VFS+
VFS-
Max
Units
10.00
11.75
V
+4.93
-5.94
+5.94
-4.93
V
V
+9.78
-11.89
+11.89
-9.78
V
V
2Kn Load, Short Sum Node to Unipolar/Bipolar.
Short V- to Full Scale Trim and Scale Factor to Sum Node.
Logic Inputs = OV
Logic Inputs = 3.0V
Open Scale Factor
Logic Inputs = OV
Logic Inputs = 3.0V
Bipolar Offset Voltage
±1/2 (I VFS+ I-I VFS-I)
-
±5 Volt Range
±10 Volt Range
±70
±140
mV
mV
bits
Resolution
6
6
Logic Input "0"
-
0.5
V
Logic Input "1"
2.1
-
V
-
18.0
VIN = +2.1V
Logic I nput Current, Each Input
Power Supply Rejection
±12V " Vs " ±18V VFS'" 10.0 V
Power Consumption
No Load
TYPICAL ELECTRICAL CHARACTERISTICS
Parameter
Settling Time
Full Scale Tempeo
Symbol
ts
TCVFS
Test Conditions
To ±1/2 LSB
DAC01·G
DAC01·GR
Typical
Typical
Typical
60
14-8
250
DAC'()l·N
1.5
VS=±15V
0.15
1.5
90
1.5
90
I'A
%FS/V
mW
Units
I'see
ppmtC
DAC-02
10 BIT PLUS SIGN D/A CONVERTER
ABSOLUTE MAXIMUM RATINGS
CHIP LAYOUT AND DIMENSIONS
Junction Temperature (T j )
r---------------." •••••
\1 \\\
-65°C to +150°C
V+ Supply to Analog Ground
Oto +18V
V- Supply to Analog Ground
o to -18V
Analog Ground to Digital Ground
o to ±0.5V
Logic Inputs to Digital Ground
-5V to (V+ - .7V)
Internal Reference Output Current
300/lA
Reference Input Voltage
o to +10V
Output Short Circuit Duration
Indefinite
(Short circuit may be to ground or either supply.)
•
8,19
B,c7
"
BII8
. , B~tl0
•
•I
8,\1----
B,13
Blt5
Bit6
8112--
Si:"S~iI ...--_
8,14
8,111
'8i112
. , LSB
Digital
.".....
Ground
Analog
V-
Ground
"
.
R.f
Oulput
SF'
SF
Output Ref
Ul
82
MilS
\
~I.lt.
nOV)
(5V)
"'-
1
..\. 1
Ana!o"
DAC02·G
DAC02·N
ELECTRICAL SPECIFICATIONS AT 25°C
---j
148 MILS
~
~
-------..
DAC02·GR
These specifications apply for Vs = ±15V and +10V Full Scale Output unless otherwise noted.
Parameter
Min
Max
Bipolar Output
13
13
13
13
Unipolar Output
12
12
12
12
Test Conditions
Resolution
Bits 11 and 12
not normally used
Monotonicity
-
9
-
Nonlinearity
Zero Scale Offset
Sign Bit High, All Other
Inputs Low
-
Zero Scale Symmetry
±10V Full Scale
Full Scale Bipolar Symmetry
±10V Full Scale
Power Supply Rejection
Vs = ±12V to ±18V
Power Dissipation'
lOUT =0
-
Logic Input "0"
Logic Input "1"
±10
±5.0
±60
0.05
300
0.8
VFS+ (Sign Bit High)
10
VFS_ (Sign Bit Low)
-11.5
TYPICAL ELECTRICAL CHARACTERISTICS
11.5
-10
DAC02·N
Max
Min
Max
Units
13
13
bits
12
12
bits
-
8
±0.1
2.0
Full Scale Output Voltage
Min
-
±0.2
-
±10
-
±5.0
±60
0.05
300
0.8
-
2.0
11.5
10
-11.5
-10
DAC02·G
-
7
-
bits
±0.4
% FS
-
±10
mV
-
±10
mV
-
±80
-
0.1
-
mV
% VFSIV
mW
350
2.0
10
-11.5
0.8
V
-
V
11.5
V
-10
V
DAC02·GR
These specifications apply for Vs = ±15V and +10V Full Scale Output unless otherwise noted.
Parameter
Full Scale Tempeo
Settling Time
Symbol
Test Conditions
Typical
Typical
Typical
Units
TCVFS
Internal Reference
60
60
90
ppml'C
ts
(T A = 25"C)
Logic Input Current
To ±1/2 LSB
10 Volt Step
1.5
1.5
1.5
,usec
T A = 25"C
1.0
1.0
1.0
!LA
NOTE: Voltage Output Range programmable by connecting SFI (10V) to Analog Output for 10 volt range. Jumper from SF2(5V) to Analog
Output sets device to 5 volt range.
14·9
I
DAC-04
TWO'S COMPLEMENT 10 BIT D/A CONVERTER
0,
ABSOLUTE MAXIMUM RATINGS
CHIP LAYOUT AND DIMENSIONS
,..
-65°C to +150°C
Junction Temperature (Ti)
V+ Supply to Analog Ground
to +18V
V-Supply to Analog Ground
to -18V
Analog Ground to Digital Ground
to ±005V
Logic Inputs to Digital Ground
-5V to (V+ - 07V)
Internal Reference Output Current
300llA
Reference Input Voltage
Oto +10V
Output Short Circuit Duration
Indefinite
(Short circuit may be !o ground or either supply)
ELECTRICAL SPECIFICATIONS AT 25°C
-I
148MiLS
• ••• ··-SI14
o
o
o
....... 8it9 \
.""
•
8ill0
\il~.............8115
Bit 8
/
Bil3
•
Bit~:::
Sign Bit
8it6
Bipolar AdjOst./'·
'Bit11
'NC_.
--Bit 12
•
•• f
LSB
"- Digital
Ground
lOV
SF1Analog
Analog
V-
5V
Ground
J••••••
DAC04·N
OUtt:lllt
'NC
Re0 \
Input-
Ul~ ~.
~"
"-
U'_•••••
DAC04·G
DAC04·GR
SF2
•
1
82
MILS
1
These specifications apply for Vs = ±5V Full Scale Output unless otherwise notedo
Test Condition.
Parameter
Bipolar Output
Resolution
Min
Max
Min
Max
Min
Max
Units
12
12
12
12
12
12
bits
Monotonicity
9
-
B
-
7
-
Nonlinearity
-
±001
-
±002
-
±OA
% FS
-500
-0.1
-5.0
-0.1
-5.0
:0.1
%
Bipolar Offset Voltage
Short Reference Input to
Reference Output and Bipolar
Adjust
bits
range
Power Supply Rejection
Vs = ±12V to ±18V
-
Power Dissipation
IOUT=O
-
001
300
-
0.1
300
-
-
-
350
%VFSIV
mW
Logic Input "0"
-
0.8
-
0.8
-
0.8
V
Logic Input "I"
2.0
-
2.0
-
2.0
-
V
10.0
11.5
10.0
11.5
1000
11.5
V
Full Scale Output Voltage
Short Reference Input to
Reference Output
TYPICAL ELECTRICAL CHARACTERISTICS
These specifications apply for
Parameter
DAC04·N
DAC04·G
DAC04·GR
Typical
Typical
Typical
60
60
gO
Vs = ±15V and ±5V Full Scale Output unless otherwise noted.
Symbol
Test Cond ition.
Units
Full Scale Tempco
TCVFS
Internal Reference
Settling Time (T A = 2S0C)
ts
To ±l>LSB
10 Volt Step
1:5
1.5
1.5
JLsec
TA = 25°C
1.0
1.0
1.0
/lA
logiC Input Current
NOTE: See DAC-02 note
14-10
ppmrC
DAC-08
8 BIT HIGH SPEED MULTIPLYING D/ACONVERTER
ABSOLUTE MAXIMUM RATiNGS
Junction Temperature (Tj)
V+ Supply to V- Supply
logic Inputs
VLC
Reference Inputs
Reference Input Differential Voltage
Reference Input Current
CHIP LAYOUT AND DIMENSIONS
-65°Ct9 +150°C
36V
V- to V- plus 36V
V- to V+
V-toV+
±18V
5.0mA
1- " .,.
. " 87
•
, ,-.. -.
85 MILS
1'-86
·1
••
I
I
BS
B4
83.2
"'"
v+
.;
/VRef l - J
ELECTRICAL SPECIFICATIONS AT 25'C
DAC08·N
I
NC
Compo
I
IQut/,,1
·~VRef(+)
•
•
81IMS.l~.
s8 (LSB)
62
MILS
vNC VLC
lOut
NC
•• 1
•••
DAC08-G
1
\
\
I /
I
\
DAC08·GR
These specifications apply for Vs ~ ±15V and IREF ~ 2.0 mA unless otherwise specified. Output characteri~tics refer to both lOUT and lOUT.
Parameter
Symbol
Test Conditions
Min
Max
Min
Max
Min
Max
Resolution
Monotonicity
8.
8
8
8
8
8
8
8
8
Nonlinearity
-
8
8
±0.19
+18
-
±0.39
+18
Output Voltage Compliance
VOC
Full scale current
8
±0.1
+18
-10
-10
-10
Units
bits
bits
% FS
V
change <)0\ LSB
Fu II Scale Current
IFS4
VREF
~
1.94
10.000V
2.04
1.94
2.04
1.94
2.04
mA
R14. R15 ~ 5.000kn
Fu II Scale Symmetry
IFSS
Zero Scale Current
IZS
Output Current Range
IFSR
VV-
~
-5.0V
-7.0V to -18V
-
±8.0
2.0
-
0
0
2.1
4.2
0
0
±8.0.
±4.0
Logic "0" Input Level
VIL
-
0.8
-
2.1
4.2
0.8
Logic "1" Input Level
VIH
2.0
-
2.0
-
~
Logic Input Current
Logic "0"
Logic "1"
IlL
111'1
VLC -OV
VIN ~ -10V to +0.8V
VIN ~ 2.0V to 18V
Logic Input Swing
VIS
V-
Reference Bias Current
115
Power Supply Sensitivity
PSSIFS+
PSSIFS_
V+ - 4.5V to 18V
V- = -4.5V to -18V
IREF = 1.0 rnA
1+
1-
Vs ~ ±18V
IREF'; 2.0 mA
Po
Vs = ±18V
IREF <: 2.0 rnA
Power Supply Current
Power Dissipation
=-15V
-
-
-
±10
±10
-
-10
+18
-10
-
-3.0
0.01
0.01
-
TYPICAL ElECTRICAL CHARACTERISTICS
-
3.8
- 7.8
-
174
DAC-08N
±10.
tl0
+18
-
-3.0
0.01
0.01
-
3.8
7.8
-
174
DAC-08G
-
±16
!LA
4.0
!LA
0
0
2.1
4.2
-
0.8
rnA
mA
V
2.0
-
V
-
±10
±10
-10
+18
-
-3.0
-
3.8
-7.8
0.01
0.01
-
-
174
IJA
IJA
V
!LA
%1%
%1%
rnA
rnA
rnW
DAC-08GR
These specifications apply for Vs ~ ±15V and IREF ~ 2.0 rnA unless otherwise specified. Output characteristics refer to both lOUT and lOUT.
Parameter
Symbol
Test Conditions
Reference Input Slew Rate
dl/dt
Propagation Delay
tpLH. tpHL TA ~ 25'C. Any bit
Settling Time
ts
To ±)o\ LS8. all bits
switched ON or OFF.
TA = 25'C
Typical
Typical
Typical
8.0
35
8.0
35
8.0
35
100
14-11
100
100
Units
rnA/!Lsec
nsec
nsec
I
DAC-20
2 DIGIT BCD HIGH SPEED MULTIPLYING DAC
,.
ABSOLUTE MAXIMUM RATINGS
Junction Temperature (Tjl
V+ Supply to V- Supply
Logic Inputs
VLC
Reference Inputs
Reference Input Differential Voltage
Reference Input Curren,t
CHIPL,AYOUT AND DIMENSIONS
,-
-E?5°C to +150"C
36V
V-.to v- Plus 36V
V-to V+
V-to V+
±18V
5.0mA
'.,. ,. ,. -..
ISM'U
r~.,.
~B7
,
•5
86
salLSBI
•
•"-
83
..
82
1
•
81 IMSBI:;;.
"He
v.
•
loui/
•
........yRet l +1
""VRell - 1
,VLC
c.....
... 1
ro;t "NC
1 1
••
If
&2
MIlS
v_
\
ELECTRICAL SPECIFICATIONS .AT 25°C
DAC·20·N
UAC·20·G
These specific.ations apply for Vs = ±15V and IRt:F = 2.0 mA unless otherWise specified. Output characteristics refer to both lOUT and lOUT'
Parameter
Symbol
Test Cond ItlorlS
Min
'0
Max
Resolution
Bj::D 0 to 99 steps
2
2
Moncton icity
BCD 99 steps
2'
2
-
±1/4
Min
Max
2
2
Digits
Units
2
2
Digits
-
±1/2
LSB
+IB
V
Nonlinearity
NL
FS = 1001 1001
Output Voltage Compliance \
VOC
Fu II scale current change
<1/2 LSB
Full Scale Current
IFS4
VREF = 10.000V
1'114. R15 = 5.000krl
1.96.
2..00
1.92
2.04
mA
Zero Scale Current
IZS
-
2.5
-
5.0
Output Current Range
IFSR
V---5.0V
V- = -7.0V to -IBV
0
0
2.1
4.2
0
0
2.1
4.2
"II>,
mA
mA
+IB
-10
' -10
Logic "0" Input Level
VIL
-
0.8
-
0.8
V
Logic "I" Input Level
VIH
2.0
-
2.0
-
V
Logic Input Current
Logic "0"
Logic "I"
IlL
IIH
VLC-OV
VIN';; -10V to +0.8V
VIN =2.0V to 18V
LogiC Input Swing
VIS
v-- -15V
Reference Bias Current
'15
PSSIFS+
PSSIFS-
Power Supply Sensitivity
Power Supply Current
Power Dissipation
V+ = 4.5V to 18V
V- = -4.6V to -18V
IRt;.F = 1.0mA
1+
1-
Vs = t18V
IREF .; 2.0 mA
Po
VS= ±'18V
IREF .; 2.0 mA
.
-
±10
tl0
-
-10
+18
-10
+18 .
-
-3.0
±0.03
to.03
"A
%1%.
%1%
-
3.8
-7.8
mA
mA
'-
-3.0
-
-
±0.03
±0.03
-
3.8
-7.8'
-
194
±10
±10
-
194
"A
"A
V
mW
.'"
TYPICAL ELECTRICAL CHARACTERISTICS
DAC·20.:N
. DAC·20·G
These specifications apply for Vs = ± 15V and IREF = 2.0 mA unless otherwise specified. Output characteristics refer to both lOUT and lOUT'
Parameter
Reference Input Slew Rate
Symbol
Test Conditions
dlldt
Typical
8.0
Propagation Delay
tPLH. tpHL
T A = 25°C. Any bit
Settling Time
ts
To t1/2 LSB.';II bits switched
ON or OFF. TA = 25°C
14·12
Typical
8.0
Units
mA/"sec
35
35
nsec
100
100
nsec
)
1408A
8 BIT HIGH SPEED MULTIPLYING D/A CONVERTER
ABsbLUTE MAXIMUM RATINGS
CHIP LAYOUT AND DIMENSIONS
\
.,. .,. ..••••
~7 B~ • •
85 MILS
Junction Temperature (Tjl
V+Supply
v- Supply
Logic Inputs
Applied Output Voltage (Vol
Reference Inputs
Reference Input Current
1
_65° C to +150° C
+5.5V
-16.5V
o to +5.5V
+0.5V to -5.2V
V- to V+
5.0mA
~."m'
"'-,.
•
~
~
"I
BJ
B2
oNe'"
'00'/·
·'-.....VREfI.1
/VIIEFI_I
.'~'~
"i 7 7°
.1 •••
•
COMP
NOTE: No range control required.
D
ELECTRICAL SPECIFICATIONS AT 25°C
These specifications apply for V+ = 5V. V-
Parameter
= -15V.
•
B1(MSlU~.
1
~
MltS
J
140BA-G
IREF
= 2.0mA unless otherwise specified.
Symbol
Min
Max
Resolution
Test Conditions
8
8
bits
Monotonicity
8
8
bits
-
±0.19
% FS
I
V- - -5V
-0.9
I
Vbelow-l0V
-5.0
+0.5
+0.5
V
V
1.9
2.1
mA
Nonlinearity
Output Voltage Compliance
VOC
Full scale current change
<% LS8
Full Scale Current
IFS
VREF
Units
= 2.000V. R14. R15 = 1.000kll
4.0
/lA
2.1
4.2
mA
mA
VIL
-
0.8
V
VIH
2.0
-
V
±10
±10
/lA
/lA
Zero Scale Current
IZS
(All bits low)
Output Current Range
IFSR
= -5.0V
v- = -6.0 to -15V
Logic "0" Input Level
logic "1" Input Level
Logic Input Current
Logic "0"
Logic "1"
IlL
IIH
Reference Bias Current
115
Output Current Power Supply Sensitivity
PSSIO_
Power Supply Current (All bits low)
1+
1-
Power Supply Voltage Range
V+(R)
V- (R)
Power Dissipation (All bits low)
Po
V-
Low Level, VIL = 0.8V
High Level. V IH = 5.0V
-
-
-
-3.0
2.7
+4.5
-4.5
VV-
= -5.0V
= -15V
-
-
TYPICAL ELECTRICAL CHARACTERISTICS
These specifications apply for V+::: +5V, V-::: -15V, VLC and
p.A
/lAIV
+14
-13
mA
mA
+5.5
-16.5
mA
mA
135
265
mW
mW
140BA-G
TQ"U"T connected
to ground, and IREF::: 2.0mA, unless otherwise specified.
Output charactertstics refer to lOUT only.
Parameter
Symbol
Test Conditions
Reference Input Slew Rate
di/dt
Propagation Delay
tPLH. tPHL
TA - 25°C. Any bit
Settling Time
ts
To ± %LSB, all bits switched ON or
OFF, TA = 25°C
Typical
4.0
14-13
Units
mA//lsec
30
nsec
250
nsec
I
OAC-IOO
8 & 10 BITTWO-CHIP Of ACONVERTER
OAI-OI 10 BIT Of ACURRENT SOURCE WITH REFERENCE
A COMPLETE 10 ~IT D/A CONVERTER EQUIVALENT TO THE DAC-100 SERIES IS
COMPRISED OF ONE DAI-01 PLUS ONE DAR-01 SERIES CHIP
CHIP LAYOUT AND DIMENSIONS
ABSOLUTE MAXIMUM RATINGS
Junction Temperature (Tj)
V+ Supply to V- Supply
V+ Supply to Output
V- Supply to Output
Logic Inputs to Output
80 M l l S - - - - 1
I"
-65°C to +150°C
Oto +36V
o to +lBV
o to -18V
-lV to +6V
Bit 2
- • • • • • • • • •i.
/
Bit3
Bit 1
MSB
v.
v-
ELECTRICAL SPECIFICATIONS AT 2SoC
f /
f
I
Bit 1Q
LSB
f
BitS
Bit7
Bit9.
Sit4
Bit6
Bit 8
•
•• I
I-I \ \ .
•••••••••
~
Outpyt
R2
RC
•
'NC
/
;-
/
R1
R4
R6
R3 \ R5
\
DAI01-G
DAI01-N
67
MilS
R7
DAI01-GR
These specifications apply when connected to an ideal DAR-01.
Parameter
Symbol
Nonlinearity
Internal Reference
VMCR
Min
Test Conditions
Max
Vs = ±15V
-
Vs = ±15V
6.600
±0.05
6.825
Max
Min
-
±0.05
6.90
6.45
Max
Min
-
Units
±0.2
%
V
6.90
6.45
Voltage
ELECTRICAL SPECIFICATIONS AT 2SoC IN COMMON TO ALL GRADES
These specifications apply for
Vs = ±15V and when connected to an
Parameter
ideal DAR-01 unless otherwise noted.
Test Conditions
Resolution
10
10
2274
Full Scale Output Current
All bits low, V- connected to FS Adjust
1840
Zero Scale Output Current
All bits high, V- connected to FS Adjust
-
Logic Input "0"
Measured with respect to output
-
Logic Input" 1"
Measured with respect to oytput
Supply Current
All bits high, V- connected to FS
Power Supply Rejection
Vs = ±6V to ±18V
TYPICAL ELECTRICAL CHARACTERISTICS
These. specifications apply for
Parameter
Full Scale Tempco
NOTE:
Vs =
DAI01-N
bits
I'A
±0.25
I'A
0.7
V
-
2.1
Adju~t
Units
Max
Min
V
-
8.33
mA
-
'0.1
%IFSIV
DAI01-G
DAI01-GR
±15V;and when connected to an ideal DAR-01 unless otherwise noted.
Test Conditions
Typical
Typical
Typical
(Note)
±60
±120
.120
Full Scale Tempco is defined as the change in output voltage measured in the test circuit shown on the DAC-l00
data sheet and is expressed, in ppm between 25° C and either temperature extreme divided by the corresponding
temperature change.
14-14
Units
ppml"C
DAC-lOO
8 & 10 BIT TWO-CH IP Of ACONVERTER
DAR-OlIO BIT RESISTOR NETWORK
A COMPLETE 10 BIT D/A CONVERTER EQUIVALENT TO THE DAC-100 SERIES IS
COMPRISED OF ONE DAI-01 PLUS ONE DAR-01 SERIES CHIP.
ABSOLUTE MAXIMUM RATINGS
CHIP LAYOUT AND DIMENSIONS
90MIlS
-
:::0
n
RC2:'"
3.2KU
12.SKU
1.6KU
1.6KU
N
w ....
U1
QlI
....
i(l
NOMINAL RESISTOR VALUES
R1 thru R7
RS
R12 thru R56
RC1
-I
,dID"IU'I'i 1
I-
-65°C to +150°C
15V
Chip Temperature
Voltage Across Any Resistor
RC2
RS1, RS2
RB
9.956KU
2.44KU
6.12KU
ELECTRICAL SPECIFICATIONS AT 25°C
I
:0
-
::u
.
:::0::0
:::0
::0
~
:::0
N ~. ~ '" g:
p--.
-
DAR01·N
I
DAR01·G
I
DAR01·GR
51
I
I
The following specifications apply for the R2R Ladder Network comprised of Rl·RS, R12, R23, R34. R45. and R56 when connected to an
ideal OAI·Ol.
Parameter
Nonlinearity
I
I
Test Conditions
VRl =3.2V
I
Maximum
I
±0.035
I
Maximum
I
±0.05
I
I
Maximum
±0.1
I
I
Units
%
ELECTRICAL SPECIFICATIONS AT 25°C IN COMMON TO ALL GRADES
The foliowing specifications apply with VRl = 3.2V.
Test Conditions
Parameter
Minimum
Maximum
Units
Kn
Resistance Rl
Absolute Measurement
Ratio RCl to R 1
Ideal = 1 to 1
-1.0
+1.0
%
Ratio Rl to RSl
Ideal = 1.31147 to 1
-1.0
+1.0
%
Ratio R 1 to RS2
Ideal = 1.31147 to 1
-1.0
+1.0
%
Ratio RS to Rl
Ideal = 1.9125 to 1
-1.0
+1.0
%
2.56
3.84
TYPICAL ELECTRICAL CHARACTERISTICS IN COMMON TO ALL GRADES
Conditions
Parameter
Absolute Temperature Coefficient
All resistors
Tracking Temperature Coefficient
All resistors with respect to R 1
14·15
Typical
Units
±120
ppmfC
3.0
ppm/'C
I
DAC-76
COMDAC™COMPANDING D/A CONVERTER
ABSOLUTE MAXIMUM RATINGS
CHIP LAYOUT AND DIMENSIONS
_65°C to +150°C
Junction Temperature (Tj)
36V
V+ Supply to V- Supply
V- plus 8V to V+
VLcSwing
V- plus 8V to V- plus 36V
Analog Current Outputs
V- to V+
Reference Inputs
±18V
Reference Input Differential Voltage
1,25 mA
Reference Input Current
V- plus 8V to V- plus 36V
Logic Inputs
e-----119MILS--~-___I·1
f ..
o.
l
DAC76·N
ELECTRICAL SPECIFICATIONS AT 25°C
DAC76·G
These specifications apply for Vs = ±15V, IREF = 528 p.A, and for all 4 outputs unless otherwise specified,
Parameter
Symbol
Resolution
Dynamic Range
Units
Test Conditions
Min
Max
Min
Max
8 chords with 16 steps each
±128
.128
±128
±128
72
72
72
72
dB
-
Steps
20 log 07,15/10,1)
-
Steps
Monotonicity
Sign Bit + or -
128
Chord Endpoint
Accuracy
Error relative to ideal
values at I FS = 2007 ,75p.A
-
±1/2
-
±1
Step
Step Nonlinearity
Step error within chord
-
±1/2
-
±1
Step
Encode CtJrrent
Additional Output
Encode/Decode = 1
3/4
Step
3/8
12B
1/4
5/8
Output Voltage Compliance
VOC
AIFS';; 1/2 step
Full Scale Current Deviation
From Ideal
IFS(O)
IFS(E)
VREF = 10,OOOV
Rll = 18,94kil'
R12=20kil
-
±1/2
±1/2
-
±1
±1
Step'
Step
Full Scale Symmetry Error
-5,0
+18
-5,0
+18
Volts
10(+1-10(-)
Decode or Encode Pair
-
±l/B
-
±1/4
Step
Zero Scale Current
IZS
Measured at Selected Output
with 000 0000 Input
-
±1/4
-
±1/2
Step
Disable Current
1015
Leakage of output
disabled by E/O and SB
-
50
-
Output Current Range
IFSR
Logic Input Levels
Logic "0"
Logic "1"
nA
4.2
mA
0:8
Volts
Volts
VLC=OV
-
VIL
VIH
O.B
2,0
-
Logic Input Current
liN
VIN = -5V to +18V
VIS
V- = -15V
Reference Bias Current
112
Power Supply Sensitivity
PSSIFS+
PSSIFS_
V+ ",4,5 to 18V, V-= -15V
V- = -1.0.8V to -18V, V+ = 15V
-
1+
1-
Vs =+5V, -15V, IFS =2,0 mA
-
4.0
-8,8
-
4,0
-8.8
-5
-
-
-
Logic Input Swing
Over Supply Range (Refer
0
4.2
0
50
40
+lB
-4,0
±1/2
±1/2
2,0
-5
-
'40
+18
-4,0
±1/2
±1/2
p.A
Volts
p.A
Step
Step
to Characteristic Curves)
Power Supply Current
Power Supply Current
Power
~~sipation
1+
1-
Vs = ±15V, IFS = 2.0 mA
PD
VS=+5V,-15V, IFS = 2.0 mA
Vs = ±15V, IFS = 2,0 mA
-
14-16
,-
-
152
192
-
-
4.0
-8,8
mA
mA
-
4,0
-8,8
mA
mA
-
-
152
192
mW
mW
MAT-O!
ULTRA-MATCHED MONOLITHIC DUAL TRANSISTOR
.CHIP LAYOUT AND DIMENSIONS
ABSOLUTE MAXIMUM RATINGS
-65°C to +150°C
Junction Temperature (Tj)
. 135M~~1
5V
Emitter-Base Voltage (BVEBO)
Collector Current (IC)
25mA
Emitter Current (IE)
25mA
Collector-Base Voltage (BVCBO)
45V
Collector-Emitter Voltage (BVCEO)
45V
Collector-Collector Voltage (BVCC)
45V
Emitter-Emitter Voltage (BVEE)
45V
..
"o~25MILS
Bl.
Cl
•
~
C2
ELECTRICAL SPECIFICATIONS AT 25 Q C
MAT01-N
These specifications apply for VCB = 15V and IC = 10ILA unless otherwise noted.
Symbol
Parameter
Test Conditions
Min
Units
Max
-
Breakdown Voltage
BVCEO
45
Offset Voltage
VOS
Offset Current
lOS
-
Bias Current
IB
.,...
40
nA
250
-
-
V
0.5
mV
3.2
nA
Current Gain
hFE
Current Gain Match
lihFE
Offset Voltage Change
liVOS/liVCB
0 .. VCB" 30V
Offset Current Change
liIOS/liVCB
0 .. VCB" 30V
-
70
-
200
pA
-
400
pA
Collector-Base-Leakage Current
'CBO
VCB = 30V, IE = 0
Collector-Emitter-Leakage Current
ICES
VCE - 30V, VBE = 0
COllector Saturation Voltage
VCE(SAT)
IB=O.lmA,lc=lmA
TYPICAL ELECTRICAL CHARACTERISTICS
-
8.0
%
-
8.0
ILVN
0.25
pAN
V
MAT01-N
These specifications apply for VCB = 15V, IC = 10ILA, TA = 25°C, unless otherwise noted.
Par~me1er
Symbol
Average Offset Voltage Drift
TCVOS
Average Offset Current Drift
TCIOS
Gain-Bandwidth Product
IT
Offset Voltage Stability
liVOS/T
Test Conditions
Typical
0.35
15
VCE = 10V, IC= lOrnA
450
Units
IJ,V;oC
pArC
MHz
First Month
(Note 1)
2.0
IJ,V/Mo
Long Term
(Note 2)
0.2
IJ,V/Mo
NOTE 1: Exclude first hour of operation to allow for stabilization of external circuitry.
NOTE 2: Parameter describes long term average drift trend after first month of operation.
14-17
I
OP-Ol
HIGH SPEED OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
CHIP LAYOUT AND DIMENSIONS
~M~~S~
-65°C to +150°C
Junction Temperature (Tj)
Total Supply Voltage
OP01·N and OP01·G
OP01·GR
±22V
±20V
Differential Input Voltage
±30V
Out
42
MILS
• ••
±15V
Input Voltage
Indefinite
Short Circuit Duration
Null
• • •• ~
V+
In.
Null
Input
ELECTRICAL SPECIFICATIONS AT 25°C
These specifications apply for
Parameter
OP01·N
Symbol
Vas
Input Offset Current
Test Conditions
Min
lOS
-
IB
Input Voltage Range
CMVR
Common Mode
Rejection Ratio
CMRR
Power Supply
Rejection Ratio
PSRR
Maximum Output
Voltage Swing
VOM
Large Signal
Voltage Gain
Ava
Power Consu motion
PD
Settling Time to 0.1%
Min
0.7
-
2.0
-
Max
Max
Min
Units
2.0
-
5.0
-
20
nA
-
100
nA
5,0
mV
-
30
-
±12.0
-
±12.0
-
±12.0
-
V
90
-
80
-
80
-
dB
90
-
80
-
80
-
dB
RL;;>5kn
±12.5
-
±12.5
±12.0
-
±12.0
-
V
±12,0
-
±12$
RL ;;>2kn
50
-
50
-
25
-
V/mV
-
60
-
90
-
90
VCM =±CMVR
RS';;50kn
Vs = ±5 to ±20V
RS ';;50kn
RL;;>2kn
VO= ±10V
VOUT=O
TYPICAL ELECTRICAL CHARACTERISTICS
Parameter
Max
-
R,S,';;50kn
Input Bias Current
Slew Rate
OP01·GR
OP01·G
Vs = ±15V unless otherwise noted.
Input Offset Voltage
These specifications apply for
--.t
Non Inv
Input
OP01·N
50
OP01·G
V
mW
OP01·GR
Vs = ± 15V, TA = 25°C unless otherwise noted.
Symbol
SR
Test Conditions
AVCL =-1
Typical
Typical
Typical
18
18
18
1.0
VIN =5V
AV =-1
1.0
LO
Units
V/p.s
,",sec
RL = 2kn
CL =50pF
Large Signal Bandwidth
250
Small Signal Bandwidth
Risetime
2,5
150
VIN =50mV
AV =-1
RL = 2kn
CL = 50pF
14·18
250
2.5
150
250
2.5
150
KHz
MHz
nsec
(
OP-02 (IMPROVED 741)
COMPENSATED OPERATIONAL AMPLI FI ER
ABSOLUTE MAXIMUM RATINGS
Junction Temperature (Tjl
CHIP LAYOUT AND DIMENSIONS
~46MIlS~
Out
Null
-65°C to +150°C
wO~
Supply Voltage
OP02·N and OP02·G
±22V
OP02·GR
±18V
Differential Input Voltage
...
±30V
Input Voltage
Supply Voltage
Output Short Circuit Duration
Indefinite
Null
ELECTRICAL SPECIFICATIONS AT 25°C
OP02·N
unless otherwise
specified
Symbol
Parameter
Input Offset Voltage
Vas
Test Conditions
-
RS'; 50kn
Input Offset Current
lOS
-
Input Bias Current
IB
-
Input Voltage Range
CMVR
Vs = ±15V
"Common Mode Rejection
Ratio
CMRR
VCM = ±CMVR
Power Supply Reiection
Ratio
PSRR
Maximum Output Voltage
VOM
Max
Min
Non Inv
InptAt
Input
OP02·GR
±5V';VS.;±20V
unless otherwise
specified
0.5
-
2.0
-
30
Max
Min
~
Inv
OP02·G
Vs = ±15V
42
Vs - ±15V
unless otherwise
specified
Max
Min
2.0
-
5.0
6.0
Units
mV
-
200
nA
-
50
-
500
nA
±12.0
-
±12.0
-
±12.0
-
V
90
-
80
-
70
-
dB
90
-
80
-
76
-
dB
RS'; 50kn
Vs =' ±5 to ±20V
RS'; 50kn
Swing IVS = ±15V)
Large Signal Voltage Gain
Ava
RL ;.10kn
±12.0
-
±12.0
-
V
±12.0
-
.12.0
RL;' 2kn
±10.0
±10.0
-
V
RL;' 2kn. Va = ±10V
100
-
50
-
-
V/mV
60
-
85
-
85
mW
-
-
-
Vh,s
25
Vs = ±15V
Power Consumption
Po
VOUT = O. Vs = ±15V
-
Slew Rate
SR
RL = 2kn.
CL = 100pF
0.25
TYPICAL ELECTRICAL CHARACTERISTICS
-
0.25
OP02·N
OP02·G
OP·02·GR
Test Conditions
Typical
Typical
Typical
Units
Risetime
AV = +1 VIN = 20mV
RL =2kn
CL =50pF
200
200
200
nsec
Overshoot
AV = +1 VIN = 20mV
RL = 2kn
CL = 50pF
These specifications apply for
Parameter
Vs =
±15V ITA = 2SoC unless otherwise noted.
Symbol
14·19
5.0
5.0
5.0
%
•
OP ..04 (IMPROVED 747)
DUAL OPERATIONAL AMPLI FI ER
ABSOLUTE MAXIMUM RATINGS
CI'tIP LAYOUT AND DIMENSIONS
Symbol
OP04-N
OP04-G
OP04-GR
±SV';;VS';;±20V
Vs = ±ISV
unless otherwise
unless otherwise
unless otherwise
specified
Specified
specified
Min
Input Offset Current
lOS
-
input Bias Current
IB
-
VOS
Input Offset Voltage Match
IIVOS
RS';; }00!l
Output
"B"
Vs = ±ISV
Test Conditions
RS';; SOk!l
1
~.! ~
These specifications apply for each amplifier unless otherwise
noted.
Input Offset Voltage
M I L S - - - _...
"'V+"A"
...... Sal
Output
"A"
"A"
±22V
±18V
±30V
Supply Voltage
Indefinite
ELECTRICAL SPECIFICATIONS AT 2SoC
Parameter
-il
""'14.----79
Junction Temperature (Tjl
Supply Voltage
OP04-N and OP04-G
OP04'GR
Differential Input Voltage
Input Voltage
Output Short Circuit Duration
Max
Min
Max
Min
0.7S
-
2.0
-
1.0
-
-
2.0
-
SO
-
50
±12.0
S.O
Max
Units
6.0
mV
-
mV
200
nA
SOO
nA
Input Voltage Range
CMVR
Vs = ±15V
±12.0
-
.12.0
-
-
V
Common Mode Rejection
Ratio
CMRR
VCM = ±C:[V1VR
RS';; SOk!l
90
-
80
-
70
-
dB
Common Mode Rejection
Ratio Match
IICMRR
VCM =±CMVR
94
-
-
-
-
-
dB
Power Supply Rejection
Ratio
PSRR
90
-
80
-
76
-
dB
Maximum Output Voltage
Swing (VS = ±15V)
VOM
±12.0
-
±12.0
-
V
±10.0
-
±10.0
-
V
100
-
25
-
V/mV
-
170
-
170
-
-
-
VII'S
-
-
-
dB
Large Signal Voltage Gain
RS ';;.100!l
Vs = ±5 to ±20V
RS';; SOk!l
AVO
RL;;' 10k!l
±12.0
RL;;' 2k!l
±12.0
RL;;' 2k!l. Vo = ±10V
100
-
-
120
Vs = ±15V
,
Vs = ±15V
Power Consumption
(Both Amplifiers)
Po
VOUT = 0
Slew Rate
SR
RL = 2k!l, CL = l00pF
Channel Separation
CS
-
0.4
-
100
TYPICAL ELECTRICAL CHARACTERISTICS
0.4
100
mW
OP04-N
OP04-G
OP04-GR
Typical
Typical
Typical
Units
200
200
200
nsec
These specifications for Vs = ±15V, TA ;, 25"C, unless otherwise noted.
Parameter
Risetime
Symbol
Test Conditions
AV = +1 VIN = 20mV
RL = 2kn, CL
Overshoot
:= 50pF
5.0
AV =+1 VIN =20mV
R L = 2k!l, CL = 50pF
14-20
5.0
5.0
%
OP-05
COMPENSATED INSTRUMENTATION OP AMP
ABSOLUTE MAXIMUM RATINGS
CHIP LAYOUT AND DIMENSIONS
I..
Junction Temperature (Tj)
Supply Voltage
Differential Input Voltage
Input Voltage
Output Short Circuit Duration
Parameter
• • • /•
/
Null
/
Null
1
I
v+
.1
OUIPUI
51
In,
Input .......
Non Inv VInput,
\
-NC
MILS
• •• "
ELECTRICAL SPECIFICATIONS AT 25°C
These specifications apply for
~I
100 MILS
_65° C to +150° C
±22V
±30V
Supply Voltage
Indefinite
OP05-N
OP05-G
OP05-GR
Vs = ±15V unless otherwise noted.
Symbol
Test Conditions
Min
Max
Max
Min
Max
Min
Units
Input Offset Voltage
Vas
-
0.5
-
0.5
-
1.3
mV
Input Offset Current
lOS
-
±2.8
-
·.3.8
-
±6.0
nA
'8
-
±3.0
-
±4.0
-
±7.0
nA
8.0
-
Mn
Input Bias Current
Input Resistance
Differential Mode
RIN
20
-
15
-
.13.5
-
±13.5
-
±13.0
-
V
CMRR
VCM = ±CMVR
114
-
110
-
100
-
dB
Power Supply
Rejection Ratio
PSRR
Vs = ±3V to .18V
100
-
94
-
90
-
dB
RL;;.10kn
±12.5
±12.0
±12.0
-
V
RL;;' 2kn
-
±12.0
YOM
-
±12.5
Maximum Output
Voltage Swing
RL;;.lkn
.10.5
-
.10.5
-
-
-
V
RL;;' 2kn
Va = ±10V
200
-
200
-
120
-
V/mV
-
±30
-
±30
-
.30
V
-
120
-
120
-
150
mW
Input Voltage Range
Common Mode
Rejection Ratio
Large Signal Voltage Gain
CMVR
Ava
Differential Input Voltage
Power Consumption
(VOUT =OV)
Po
Vs = ±15V
TYPICAL ELECTRICAL CHARACTERISTICS
OP05·N
OP05·G
Typical
Typical
±11.5
V
OP05·GR
These specifications apply for Vs = ± 15V.
Parameter
Symbol
Test Conditions
Typical
Units
Average I nput Offset
Voltage Drift
TCVOS
Rs" son
0.7
0.7
1.2
p.VrC
Nulled Input Offset
Voltage Drift
TCVOSN
RS" 50n
Rp = 20kll
0.3
0.3
0.4
p.VrC
Average Input Offset
Current Drift
TCIOS
8.0
8.0
14-21
12
pArC
•
OP-07
ULTRA-LOW OFFSET VOLTAGE OP AMP
ABSOLUTE MAXIMUM RATINGS
CHIP LAYOUT AND DIMENSIONS
t - - - - - 100
r.
!.
Junction Temperature (Tjl
-6SOC to +lS0°C
Supply Voltage
±22V
Differential Input Voltage
±30V
Input Vciltage
/.~
Null
1
53
Supply Voltage
Output Short Circuit Duration
.I
V+
/
Output
In\!
Input
Nonlnv
Input
..
Indefinite
v-
..~
"'--~~
OP07-N
ELECTRICAL SPECIFICATIONS AT 2SoC
OP07-G
OP07-GR
These specifications apply for Vs = ±15V unless otherwise noted.
Parameter
Input Offset Voltage
Input Offset Current
Input Bias Current
Input Resistance
Symbol
Vas
-
lOS
'B
Differential Mode
RIN
Input Voltage Range
CMVR
Common Mode
Rejection Ratio
Power Supply
Rejection Ratio
95
-
-
±2.8
-
±6.0
-
±3.0
-
±7.0
20
-
8.0
±13.0
-
150
Min
Max
-
1300
Units
/LV
-
±6.0
nA
-
±7.0
nA
-
8.0
-
Mf!
±13.0
-
±13.0
-
V
-
100
-
100
-
dB
PSRR
Vs = ±3V to ±18V
100
-
90
-
90
-
dB
RL:<> 10kf!
±12.5
-
±12.0
±12.0
RL :<> 2kf!
±12.0
RL:<>lkf!
-
-
V
VOM
V/mV
RL:<> 2kf!
VO= ±10V
±11.5
±10.5
-
-
-
200
-
120
-
120
-
-
±30
-
±30
-
±30
V
-
120
-
120
-
150
mW
Differential Input Voltage
(VOUT= OV)
Max
110
Ava
Power Consumption
Min
VCM = ±CMVR
Large Signal Voltage
Gain
Max
CMRR
Maximum Output
Voltage Swing
Min
Test Conditions
Po
Vs = ±15V
TYPICAL ELECTRICAL CHARACTERISTICS
±11.5
V
V
OP07-N
OP07-G
OP07-GR
Typical
Typical
0.3
0.5
1.2
/Lvl'c
0.3
0.4
0.4
/LV/oC
These specifications apply for Vs = ±15V.
Parameter
Symbol
Average Input Offset
Voltage Drift
TCVOS
Nulled Input Offset
Voltage Drift
TCVOSN
Average Input Offset
Current Drift
TCIOS
Test Cond itions
RS <; 50f!
RS<;50f!
Rp = 20kf!
8.0
14-22
12
Typical
12
Units
pA/oC
OP-08
PRECISION LOW INPUT
CURRENT OPERATIONAL AMPLIFIER
CHIP LAYOUT AND DIMENSIONS
ABSOLUTE MAXIMUM RATINGS
Junction Temperature (Tj)
Supply Voltage
OP·OS·N
OP·OS·GR and G
Differential Input Current
Input Voltage
Output Short Circuit Duration
. .. .T
I-
-65°C to +150°C
=:
± 15V,
NON INV
INPUT
I
Op·08·N
Op·OS·G
Test Cond itions
Max
Min
Max
Min
Max
Units
-
0.3
0.3
-
1.0
mV
-
lOS
-
0.2
Input Bias Current
IB
-
2.0
±14
-
±14
104
-
102
-
102
±13
I nput Voltage Range
CMVR
Common Mode Rejection Ratio
CMRR
Power Supply Rejection Ratio
PSRR
Vs = ±5 to ±15V
104
Maximum Output Voltage Swing
YOM
RL;;' 10kn
±13
RL;;' 2kn
±10
VCM =± CMVR
,
AVO
Rin
IS
=:
0.4
4.0
0.5
nA
5.0
nA
±14
-
V
B4
-
dB
-
84
±13
-
dB
-
V
RL;;' 10kn, Vo =
10V
RL;;' 2k
lout = 0, V out = 0
TYPICAL ELECTRICAL CHARACTERISTICS
These specifications apply for Vs
OP·08·GR
Min
I nput Offset Current
Input Resistance
1
V. ___ •
••••
\
-
Supply Current
42
MILS
'NV
INPUT
VOS
large Signal Voltage Gain
v+
OUT-.
unless otherwise noted.
Symbol
Parameter
Input Offset Voltage
OOMP
COM.
ELECTRICAL SPECIFICATIONS AT 25°C
These specifications apply for Vs
~/
~~-NC ~
\
±20V
±lSV
±10mA
±15V Supply Voltage
Continuous
"I
58 MILS
-
±10
±10
-
-
-
25
-
-
0.6
OP·OS·N
-
13
-
V/mV
-
30
50
-
40
0.6
Op·OS·G
-
Mn
0.8
mA
10
-
OP·OS·GR
± 15V.
Typical
Typical
Units
Average Input Offset Voltage
Drift
TCVos
1.0
1.0
1.5
,..vl"c
Average Input Offset Current
Drift
TClos
0.5
1.0
1.0
pAtC
Parameter
Symbol
Test Conditions
14·23
Typical
I
OP-09
QUAD OPERATIONAL AMPLIFIER
CHIP,LAYOUT AND DIMENSIONS
ABSOLUTE MAXI¥UM RATINGS'
• •
"Nill
.
-t
v••
• •INCC1
-INIDI •
+lNIeI OUTCCI
Y'
OUTIOI
1."
.. NIDI
• • • •
•
OP-09-G
OP-09-N
Test Conditions
.
+IN(AI
~NtAJ.
.Y-
Vs = ±15V
Vs = ±15V
un less otherwise
specified
unless otherwise
These specifications apply for each amplifier unless otherwise noted.
Symbol
•
OUT..,
OUTIII
.·~INI.I
ELECTRICAL SPECIFICATIONS AT 25°C
Parameter
.......
I-
-65°C to +150°C
Junction Temperature (Tjl
Supply Voltage
OP-09N, OP-09G
±22V
Differenti~1 Input Voltage
±30V
Input Voltage
±15V
(For supply voltages less than ±15V, the absolute
maximum input voltage is equal to the supply voltage.)
Output Short Circuit Duration to Ground
Continuous
(One amplifier only, ISC ; 45mA typicaL)
Max
Min
-
specified
Max
Min
Units
20
-
50
nA
300
-
500
nA
±12
-
±12
100
-
100
RS .;;;10kn
90
-
90
RL ;>10kn
12
-
12
RL;> 2kn
11
-
11
-
100
-
100
-
-
180
-
180
Input Offset Voltage
VOS
RS.;;;10kn
Input Offset Current
lOS
-
Input Bias Current
IB
-
Input Voltage Range
CMVR
Common' Mode Rejection Ratio
CMRRt
VCM = ±CMVR, RS .;;;10kn
Power, Supply Rejection Ratio
PSRR
Maximum Output Voltage Swing
YOM
Large Signal Voltage Gain
AVO
RL ;;. 2kn. Vo - ±10V
Power Consumption
Po
VOUT = 0, No Load
0.5
2.5
mV
V
dB
dB
V
V
VIm V
mW
(Four Amplifiersl
TYPICAL CHARACTERISTICS
OP-09-N
OP-09-G
Typical
Typical
1.0
1.0
V/I"s.c
2.0
2.0
MHz
These specifications for Vs = ±15V, TA = 25°C, unless otherwise noted.
Parameter
Symbol
Slew Rate
SR
Unity Gain Bandwidth
GBW
Channel Separation
CS
Test Conditions
AV=1.RL;>2kn
AV = 100, f - 10kHz
RS= lkn
NOTE: Either or both V+ pads may be used without any change in performance.
14-24
120
120
Units
dB
OP-ll
QUAD OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
CHIP LAYOUT AND DIMENSIONS
-65°C to +150°C
Junction Temperature (Ti)
Supply Voltage
OP-ll N, OP-llG
±22V
Differential Input Voltage
±30V
±15V
Input Voltage
(For supply voltages less than ±15V, the absolute
maximum input voltage is equal to the supply voltage.)
Output Short Circuit Duration to Ground
COntinuous
(One amplifier only, ISC = 45mA typical.)
t"
•
OUTI.1
OUTle)
.,-
+lNf".
.tINI!)1
tIN'A,_
-INIDI
Test Conditions
~
•
,-.
v+
OUTIO'
OUT/A'
T
_INIBI
• tweet
• •• •
These specifications apply for each amplifier unless otherwise noted.
Symbol
•
•
.INICl
ELECTRICAL SPECIFICATIONS AT 25°C
Parameter
.'MILI
-1'flA'
•
1
OP-ll-N
OP-ll-G
Vs = ±15V
unless otherwise
specified
Vs = ±15V
unless otherwise
specified
Max
Min
Min
-
50
nA
300
-
500
nA
±12
-
±12
-
2.5
VOS
lOS
Input Bias Current
IB
Input Voltage Range
CMVR
Common Mode Rejection Ratio
CMRR
VCM = ±CMVR, RS" 10k!l
Power Supply Rejection Ratio
PSRR
RS" 10k!l
90
-
Maximum Output Voltage Swing
VOM
RL'" 10k!l
.12
-
±12
RL '" 2k!l
ill
±11
AVO
RL '" 2k!l, VO,- ±10V,
100
-
Po
VOUT = 0, No Load
-
180
Large Signal Voltage Gain
Power Consumption
(Four Amplifiers)
TYPICAL CHARACTERISTICS
Units
20
0.5
Input Offset Current
RS .. 10K!l
Max
-
Input Off5!!t Voltage
100
mV
V
dB
100
-
-
180
mW
100
90
OP-11-N
OP-ll-G
Typical
Typical
dB
V
V
V/mV
These specifications for Vs = ±15V, TA = 25°C, unless otherwise noted.
Parameter
Symbol
Slew Rate
SR
U'nity Gain Bandwidth
GBW
Channel Separation
CS
Test Conditions
AV=1,RL",2kn
AV = 100, f = 10kHz
RS = lk!l
NOTE: Either or both V+ pads may be used without any change in performance.
14-25
Units
1.0
1.0
V/I'sec
2.0
2.0
MHz
120
120
dB
I
OP-12
PRECISION LOW INPUT
CURRENT OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
CHIP LAYOUT AND DIMENSIONS
I"-
-65°C to +150°C
Junction Temperature (Tjl
Supply Voltage
OP-12-Nand OP-12-G
OP-12-GR
Differential Input Current
Input Voltage
Output Short Circuit Duration
INTERNALLY
COMPENSATED
68 MILS
°NC
°NC
1
••
•
~II!"
±20V
±18V
±10mA
±15V Supply Voltage
Continuous
°NC/
v+
OUT-.
MilS
NON INV
INPUT
'NV
INPUT
••••
/
\
ELECTRICAL SPECIFICATIONS AT 25°C
OP-12-N
1
V-_.
OP-12-G
OP-12-GR
These specifications apply for V S = ±15V, unless otherwise noted.
Symbol
Parameter
Input Offset Voltage
VOS
Input Offset Current
lOS
IB
Input Bias Current
,
Test Conditions
Min
Max
Min
-
0.3
-
0.2
-
2.0
±14
-
Input Voltage Range
CMVR
Common Mode R ejection Ratio
CMRR
VCM.= ±CMVR
Power Supply Rejection Ratio
PSRR
Vs = ±5 to ±15V
104
Maximum Output Voltage Swing
VOM
RL ;;'10k!!
±13
RL ;;'2k!!
±10
Large Signal Voltage Gain
AVO
Input Resistance
Rin
Supply Current
IS
104
-
RL ;;.10k!!0 Vo =
±10V
RL;;' 2k!!
25
-
=O. Vout =0
-
0.6
lout
TYPICAL ELECTRICAL CHARACTERISTICS
50
Max
Min
Max
Units
-
0.3
mV
0.5
nA
4.0
-
1.0
±14
-
±14
102
-
84
102
-
±13
0.4
±13
-
±10
-
-
'84
-
13
0.6
nA
V
d8
dB
V
-
±10
40
Vim V
-
30
-
5.0
-
M!!
0.8
mA
10
-
OP-12-N
OP-12-G
OP-12-GR
These specifications apply for Vs = ±15V.
Typical
Typical
Typical
Units
Average Input Offset Voltage
Drift
TCVos
1.0
1.0
1.5
p.vl'c
Average I nput Offset Current
Drift
TClos
0.5
1.0
1.0
pAI'C
Parameter
Symbol
Test Conditions
14-26
OP-14 (IMPROVED 1458)
DUAL OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
CHIP LAYOUT AND DIMENSIONS
Junction Temperature (Tjl
-6S 0 Cto +lS0°C
SJpply Voltage
OP14-N and OP14-G
OP14-GR
±22V
±18V
Differential Input Voltage
±30V
,...
• *Ne
Input Voltage
Parameter
Symbol
Test Conditions
Input Offset Voltage
Vas
RS" 50kn
Input Offset Voltage Match
t:NOS
RS" 100n
Input Offset Current
lOS
Input Bias Current
IB
Input Voltage Range
CMVR
Vs = ±15V
Common Mode Rejection
CMRR
VCM = ±CMVR
Ratio
Iny
In"A"
46
Input
*Ne
/"" Non Inv
•
ELECTRICAL SPECIFICATIONS AT 2S o C
noted.
*Ne.
Inv Input
Indefinite
These specifications apply for each amplifier unless otherwise
\
\
\
Output
Output
A
V+ B
.---"A"
1
oNe •
vo• • • Vo
.oNe
SJpply Voltage
Output Short Circuit Duration
~I
79 MILS
\
V,- *NC
....
MILS
1
"8" ' .
~~~ Inv, •
OP14-N
OP14-G
OP14-GR
VS= ±15V
±5V .. VS .. ±20V
Vs = ±15V
unless otherwise
specified
unless otherwise
specified
unless otherwise
Max
Min
Min
Max
-
0.75
-
2.0
-
1.0
-
-
-
2.0
-
5.0
-
50
-
±12.0
-
±12.0
90
-
94
50
specified
Max
Min
±12.0
80
-
-
-
90
-
Units
6.0
mV
-
mV
200
nA
500
nA
70
-
dB
-
-
-
dB
80
-
76
-
dB
V
V
RS" 50kn
Common Mode Rejection
Ratio Match
L'>CMRR
Power Supply Rejection
Ratio
PSRR
Maximum Output Voltage
Swing (VS = ±15V)
YOM
Large Signal Voltage Gain
Ava
VCM = ±CMVR
RS" 100n
Vs = ±5 to ±20V
RS" 50kn
R L;> 10kn
±12.0
-
±12.0
-
±12.0
RL ;> 2kn
±12.0
-
±10.0
-
±10.0
RL;> 2kn, Va = ±10V
100
-
100
-
25
-
-
120
-
170
-
170
-
-
-
VIp-,
-
-
-
dB
V
V/mV
Vs = ±15V
Power Consumption
Po
(Both Amplifiers)
VOUT =0
Slew Rate
SR
Channel Separation
CS
RL =2kn, CL = 100pF
Parameter
-
0.4
-
100
TYPICAL ELECTRICAL CHARACTERISTICS
These specifications for
mW
Vs = ±15V
0.4
100
OP14-N
OP14-G
OP14-GR
Typical
Typical
Typical
Units
200
200
200
nsec
Vs = ± 15V, T A = 25°C. unless otherwise noted.
Symbol
Test Conditions
Risetime
AV = +1 VIN = 20mV
Overshoot
AV = +1 VIN=20mV
RL = 2kn., CL = 50pF
RL = 2kn, CL = 50pF
14-27
5.0
5.0
5.0
%
I
OP-15
PRECISION, LOW POWER JFET INPUT OP AMP
ABSOLUTE MAXIMUM RATINGS
CHIP LAYOUT AND DIMENSIONS
-65°C to +150°C
Junction Temperature (Tjl
I-
Supply Voltage
OP·15·N,OP·15·G
±22V
Op·15·GR
±18V
...
\
M
lillULI
·1
vr-
NULL
JI
INV
INPUT
OUTPUT
Differential Input Voltage
OP·15·N,Op·15·G
±40V
Op·15·GR
±30V
Input Voltage
NON INV
INl'UT
Output Short Circuit Duration
v"f
~
Supply Voltage
"-
Continuous
ELECTRICAL SPECIFICATIONS AT 25°C
Op·15·N
Op·15·G
1
.I
NULL
OP·15·GR
These specifications apply for Tj = +25'C, ±15V, unless otherwise noted.
Parameter
Svmbol
Test Conditions
Input Offset Voltage
Vas
Rs = 50n
Large Signal Voltage Gain
Ava
Va - ±10V,
RL =2Kn
CMVR
Vs = ±15V
Input Voltage Range
Max
Min
Max
Min
Max
-
0.5
-
1.0
-
3.0
100
-
75
-
50
-
'V/mV
±10.5
-
±10.5
-
±10.5
-
V
82
-
dB
-
dB
11
-
-
50
rnA
Min
Common Mode Rejection
Ratio
CMRR
VCM = ±CMVR
86
-
86
-
Power Supply Rejection Ratio
PSRR
Vs = ±10V to ±20V
86
-
RL = 10Kn
12
RL =2Kn
11
-
86
Vs = ±10V to ±15V
11
-
-
4.0
-
4.0
Maximum Output Voltage
Swing
VOM
Supply Current
ISY
TYPICAL ELECTRICAL CHARACTERISTICS
12
82
12
Op·15·N
OP·15·G
Op·15·GR
Typical
Tvpical
Tvpical
Units
mV
dB
V
V
These specifications applv for Vs = ±15V, Tj= 2S'C
Parameter
Symbol
Test Conditions
Units
Average Input Offset Voltage
Drift without ext trim
With ext trim
TCVOS
TCVOSN
2.0
2.0
Rp= 100Kn
Input Offset Current
lOS
Input Bias Current
IB
Slew Rate
SR
AVCL = +1
Settling Time
ts
to 0.Q1%
to 0.05%
to 0.10%
3.0
3.0
3.0
3.0
4.0
4.0
IlVI'C
3.0
pA
15
15
15
17
16
15
2.2
1.1
0.9
2.3
1.1
0.9
5.7
pA
Vlllsec
2.4
1.2
1.0
IlS
5.4
MHz
Gain Bandwidth Product
GBW
Closed Loop Bandwidth
CLBW
AVCL = +1
14
13
12
MHz
Input Noise Voltage Density
en
f = 100Hz
f = 1000Hz
20
15
20
15
20
15
nV/y'HZ
nV/y'HZ
Input Noise Current Density
in
f = 100
f = 1000
Input Capacitance
Cin
6.0
0.Q1
0.Q1
0,01
0.01
0.Q1
0.Q1
pA/..jHZ
pA/,fHi'
3
3
3
pF
"
14·28
OP-16
WIDE BANDWIDTH PRECISION JFET INPUT OP AMP
"'-
ABSOLUTE MAXIMUM RATINGS
-65°C ~o +150°C
Junction Temperature (Tj)
Supply Voltage
CHIP LAYOUT AND DIMENSIONS
,.
OP-16N,OP-16G
...
~
v.-II
NULL
'HV
±18V
""'"
Differential Input Voltage
OP-16N, OP-16G
,. 1
I
~
~
±22V
OP-16GR
.j
M
OUTPUT
-. I
±40V
OP-16GR
NONINV
±30V
Input Voltage
''''''.
Output Short Circuit Duration
v-
~
Supply Voltage
NULL
"11
Continuous
ELECTRICAL SPECIFICATIONS AT 25°C
OP-16N
OP-16G
OP-16GR
These specifications apply for Tj = +25°C, Vs = ±15V, unless otherwise noted.
Symbol
Parameter
Test Conditions
Input Offset Voltage
Vas
As = son
Large Signal Voltage Gain
Ava
Vo = ±IOV,
AL=2K!l
Input Voltage Aange
"
CMAA
Power Supply Aejection Aatio
PSAA
YOM
Supply Current
-
Max
Min
Max
0.5
-
1.0
-
3.0
100
-
75
-
50
-
±10.5
±10.5
±10.3
82
-
V s '" .10V to ±20V
86
-
Vs = .10V to ±15V
-
-
-
-
12
-
12
12
-
11
-
-
11
-
11
-
-
Hi'
-
7.0
= 10K!l
RL = 2K!l
ISY
TYPICAL ELECTRICAL CHARACTERISTICS
These specifications apply for Vs
Min
86
AL
Maximum Output Voltage Swing
Max
VCM = ±CMVA
CMVA
",
Common Mode Aeiection Aatio
Min
86
B6
82
-
-
B.O
OP-16N
OP-16G
OP-16GR
Typical
Typical
Typical
2.0
2.0
3.0
3:0
4.0
4.0
Units
mV
V/mV
V
dB
dB
dB
V
V
mA
= ± 15V, Tj = =/5° C
Parameter'
Symbol
Average Input Offset Voltage Drift
Without Ext Trim
With Ext Trim
TCVOS
TCVOSN
I nput Offset Current
lOS
Input Bias ~urrerit
·Slew Aate
'B
SA
Settltng Time
ts
Gain Bandwic:ith Product
GBW
Test Conditions
Ap
= looK!l
3.0
AVCL ,,+1
to 0.01%
to 0.05%
to 0.10%
3.0
15
15
25
2~
1.7
0.9
0.7
8.0
1.7
0.9
0.7
7.6
3.0
15
.
23
1.8
1.0
0.8
7.2
Closed Loop Bandwidth
CLBW
AVCL =+1
19
18
.17
I nput Noise Voltage Density
en
f = 100Hz
f = 1000Hz
20
15
20
15
20
15
I nput Noise Current Densit',(
in.
I nput Capacitance
Cin
f = 100
f = 1000
14·29 .
Units
I'vfc
I'vl"c
pA
pA
V/l'sec
1"
MHz
MHz
nV/..jHz
nV/..jHz
0.01
0.01
0.01
0.01
0.01
0.01
pA/..jHz
pA/..jHz
3
3
3
pF
I
OP-17
.
PRECISION JFET INPUT OPERATIONAL AMPLIFIER
,
ABSOLUTE MAXIMUM RATINGS
CHIP LAYOUT AND DIMENSIONS
...
fo-----
-65°C to +150°C
Junction Temperature (Tj)
Supply Voltage
OP-17-N,OP-17-G
±22V
OP-17-GR
±18V
'NV
\
~
~
MIU
NULL
INPuT
OUTPUT
Differential Input Voltage
OP-17-N,OP-17-G
±40V
OP-17-GR
±30V
Input Voltage
JIKlIIIINV
INPUT
Continuous
ELECTRICAL SPECIFICATIONS AT 25°C
These specifications apply for Tj
= +2S"C,
Parameter
V5
Symbol
=
I
OP-17-N
Test Conditions
Min
Max
Min
Max
0.5
-
1.0
-
3·0
-
75
-
50
-
Vim V
±10.5
-
±10.3
-
V
-
86
-
82
-
dB
86
-
-
-
82
12
12
11
-
-
dB
-
11
-
-
7.0
-
8.0
Large Signal Voltage Gain
AVO
Vo=±10V,
RL = 2Kn
100
Input Voltage Range
CMVR
Vs=±15V
±10.5
CMRR
VCM = ±CMVR
86
PSRR
Maximum Output Voltage
SWing
YOM
Supply Current
ISY
Vs = ±10V to ±20V
86
Vs = ±10V to ±15V
-
RL = 10Kn
12
RL = 2Kn
11
-
-
7.0
TYPICAL ELECTRICAL CHARACTERISTICS
These specifications apply for
Parameter
Vs
= ~
Units
Max
-
Rs = 50n
Power Supply Rejection Ratio
OP 17·GR
Min
Vas
Ratio
OP-17-G
NULL
15V. unless otherwise noted.
Input Offset Voltage
Common Mode Rejection
V\.
~
Supply Voltage
Output Short Circuit Duration
,. 1
-. I
v'--.
OP·17-N
OP-17-G
OP-17-GR
Typical
Typical
Typical
mV
dB
V
V
mA
15V, Tj = 2S"C.
Symbol
Test Conditions
Units
Average I nput Offset Voltage
Drift without ext trim
Drift with ext trim
TCVOS
TCVOSN
Rp = 100Kn
2.0
2.0
3.0
3.0
4.0
4.0
/LVrC
Input Offset Current
lOS
Input Bias Current
IB
Slew Rate
SR
AVCL =5
Settling Time
ts
to 0.01%
to 0.05%
to 0.10%
Gain Bandwidth Product
GBW
30
28
26
MHz
Closed Loop Bandwidth
CLBW
AVCL = +5
11
10
9
MHz
Input Noise Voltage Density
en
f = 100Hz
f = 1000Hz
20
15
20
15
20
15
Input Noise Current Density
in
f = 100
f= 1000
Input Capacitance
3.0
15
70
66
62
1.5
0.5
0.4
1.6
0.6
0.5
om
om
om
0.01
0.01
3
3
3
0.01
14~O
3.0
15
1.5
0.5
0.4
Cin
3.0
15
pA
pA
V//lsec
/lS
nV/.JHZ
nV/.JHZ
pA/.jHZ
. pA/.jHZ
pF
108
LOW INPUT CURRENT OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
CHIP LAYOUT AND DIMENSIONS
,.
_65°C to +150°C
Junction Temperature (Tjl
&Jpply Voltage
lOB-N and 10B·G
108-GR
±20V
±18V
Differential Input Current
(See PM108A data sheet)
.~~).
In put Voltage
(See PM 108A data sheet)
COMP
COMP
±10mA
v+
OUT-.
.ii.•
NON INV
INPUT
/
INV
INPUT
±15V, Supply Voltage
\
Output Short Circuit Duration
,./- T
58MILS----i
Continuous
ELECTRICAL SPECIFICATIONS AT 25°C
108·N
42
MilS
1
V. _ _ •
108·GR
108·G
These specifications apply for ±5V .. Vs" ±20V for IOS·N, .5V .. Vs" ±15V for I08-G andl08·GR, unless otherwise noted.
Parameter
Symbol
Test Conditions
Min
Max
Max
Min
Min
Max
Units
VOS
-
0.5
-
2.0
-
7.5
mV
Input Offset Current
lOS
-
0.2
-
1.0
-
1.0
nA
Input Bias Current
18
-
2.0
-
7.0
-
7.0
nA
-
.,4
-
±14
Input Offset Voltage
Input Voltage Range
CMVR
Vs
Common Mode Rejection
Ratio
CMRR
VCM = ±CMVR
Vs ~ ±15V
96
Power Supply Rejection
PSRR
Vs = ±5 to ±2OV
96
Vs = ±5 to ±15V
-
-
.,3
Ratio
Maximum Output Voltage
~
±15V
YOM
RL;;;' 10kn
Vs ~ ±15V
Large Signal Voltage Gain
AVO
RL;;;' 10kn, Vo =
±10V, Vs ~ ±15V
Input Resistance
Rin
Supply Current
IS
Swing
.,4
-
B5
80
-
V
-
dB
80
-
dB
80
-
-
.,3
-
±13
-
V
80
-
50
-
25
-
V/mV
25
-
8.5
-
8.5
-
Mn
-
0.6
-
0.8
-
0.8
mA
lout = 0, Vout = 0
TYPICAL ELECTRICAL CHARACTERISTICS
-
-
lOB·N
108·G
10B·GR
Typical
Typical
Typical
dB
These specifications apply for VS:::: ±15V.
Parameter
Average Input Offset
Symbol
Test Conditions
TCVos
Voltage Drift
Average Input Offset
TClos
Current Drift
14-31
1.0
3.0
6.0
1.0
2,0
2.0
Units
If.VrC
pArC
I
155
LOW POWER JFET INPUT OP AMP
CHIP LAYOUT AND DIMENSIONS
ABSOLUTE MAXIMUM RATINGS
-65°C to +150°C
Junction Temperature (Tjl
Supply Voltage
155-N and 155-G
155-GR
I·
v.-.
~ ~ULL
±22V
±18V
Differential Input Voltage
155:N and 155-G
155-GR
~
64 MILS
•T
'NV
,-
INPUT
.1
OUTf>UT
45
MilS
±40V
±30V
NON INV
INPUT
Output Short Circuit Duration
V-
~
Supply Voltage
Input Voltage
"-
Continuous
ELECTRICAL SPECIFICATIONS AT 25°C
155-N
NULL
155-GR
155-G
These specifications apply for Tj= +25"C, ±15V.;; V • .;; ±20V for 155-N and 155-G, ±15V for 155-GR, unless otherwise noted.
Parameter
Symbol
Test Cond ition.
Max
Min
Max
Min
Max
-
2.0
-
5.0
-
10
mV
-
V/mV
±11
-
V
80
-
d8
VOS
RS = 50n
Large Signal Voltage Gain
AVO
Vo = ±10V, Vs = ±15V
RL=2Kn
50
Input Voltage Range
CMVR
Vs = ±15V
ill
-
ill
-
Common Mode Rejection
Ratio
CMRR
85
10
-
-
4.0
Power Supply Rejection Ratio
PSRR
Maximum Output Voltage
Swing
YOM
Supply Current
IS
Units
Min
Input Offset Voltage
-
Vs = ±15V, RL = 10Kn
12
Vs = ±15V, RL = 2Kn
10
-
-
4.0
VCM = ±CMVR
85
Vs = ±10V to ±20V
85
Vs = ±10V to ±15V
-
Vs=±15V,Vo=0
TYPICAL ELECTRICAL CHARACTERISTICS
155-N
-
50
85
12
155-G
25
80
12
10
-
4.0
d8
dB
V
V
mA
155-GR
These specifications apply for Vs = ± 15V.
Parameter
Symbol
Average I nput Offset Voltage
Drift
TCVOS
Input Offset Current
lOS
Tvpical
Test Conditions
RS';; 50n
Typical
Typical
Units
/lVrC
4.0
5.0
6.0
3.0
4,0
5,0
pA
30
30
40
pA
5.0
5.0
5.0
V//lsec
Input Bias Current
IB
Slew Rate
SR
Settling Time to 0.01 %
ts
4.0
4.0
4.0
~sec
Gain Bandwidth Product
GBW
2.6
2.5
2.5
MHz
AVCL = +1
14-32
156
WIDE BANDWIDTH JFET INPUT OP AMP
ABSOLUTE MAXIMUM RATINGS
Junction Temperature (Tjl
CHIP LAYOUT AND DIMENSIONS
-65°C to +150°C
Supply Voltage
156·N and 156·G
156·GR
I·
±22V
±18V
-I
64 MILS
••
V ' -•
•T
\
\
NULL
'NV
/
INPUT
OUTPUT
Differential Input Voltage
156-N and 156·G
156·GR
.1
45
MILS
±40V
±30V
Input Voltage
NON INV
INPUT
Output Short Circuit Duration
"'.
V·
~
Supply Voltage
Continuous
ELECTRICAL SPECIFICATIONS AT 25°C
156·N
156·G
NULL
156·GR
These specifications apply for Tj = +25°C, ±15V <; Vs <; ±20V for 156·N and 156-G, Vs = ±15V for 156·GR, unless otherwise noted.
Symbol
Parameter
Input Offset Voltage
Large Signal Voltage Gain
Input Voltage Range
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Test Conditions
Min
Max
Min
Max
Min
Max
Units
VOS
Rs = 50n
-
2.0
-
5.0
-
10
mV
AVO
Vo = ±10V, Vs = ±15V
RL=2Kn
50
-
50
-
25
-
CMVR
Vs = ±15V
±11
-
ill
-
±11
-
V
80
-
dB
-
.-
dB
80
12
-
V
10
-
CMRR
PSRR
Maximum Output Voltage
Swing
VOM
Supply Current
IS
VCM = ±CMVR
85
-
85
-
Vs = ±10V to ±20V
85
-
85
Vs = ±10V to ±15V
-
-
Vs = ±15V, RL = 10Kn
12
12
Vs = ±15V, RL = 2Kn
10
-
-
Vs=±15V,Vo=0
-
7.0
-
TYPICAL ELECTRICAL CHARACTERISTICS
These specifications apply for
Parameter
Average Input Offset Voltage
7.0
-
10
dB
V
mA
156·N
156·G
156·GR
Typical
Typical
Typical
Units
5,0
6.0
p.Vrc
Vs = ± 15V.
Symbol
TCVOS
Test Conditions
RS <; 50n
4.0
Drift
Input Offset Current
lOS
Input Bias Current
IB
Slew Rate
10
V/mV
SR
3.0
AVCL = +1
4.0
5.0
pA
30
30
40
pA
12
12
12
V/p.sec
Settling Time to 0.01 %
ts
1.5
1.5
1.5
.usee
Gain Bandwidth Product
GBW
5.0
5.0
5.0
MHz
14·33
I
157
JFET INPUT OPERATIONAL AMPLIFIER
WIDE BANDWIDTHDECOMPENSATED(AV
=5)
ABSOLUTE MAXIMUM RATINGS
CHIP LAYOUT AND DIMENSIONS
-65°C to +150°C
Junction Temperature (Tjl
Supply Voltage
157-N and 157-G
157-GR
~
±22V
±18V
Differential Input Voltage
157-N and 157-G
157-GR
Input Voltage
•T
NULL
/
OUTPUT
INPUT
NON INV
v-
INPUT
~
Continuous
0;;
157-N
Vs
0;;
Min
Max
Min
Max
Rs =50n
-
2.0
-
5.0
-
10
Vo = ±10V, Vs = ±15V
RL=2kn
50
-
50
-
25
-
V/rnV
±11
-
±11
-
±11
-
V
85
-
80
-
dB
85
-
-
dB
-
-
80
12
12
V
10
-
-
10
-
10
-
V
-
7.0
-
7.0
-
10
Vas
Ava
Input Voltage Range
CMVR
Vs = ±15V
Common'Mode Rejection
CMRR
VCM
= ±CMVR
85
Ratio
Supply Current
'IS
157-GR
157-G
Max
Test Conditions
Large Signal Voltage Gain
YOM
"-
Min
Symbol
Maximum Output Voltage
Swing
NULL
±20V for 157-N and 157-G, Vs = ±15V for 157-GR, unless otherwise noted.
Input Offset Voltage
PSRR
.1
45
MILS
Supply Voltage
These specifications apply for Tj = +25°C, ±15V
Power Supply Rejection Ratio
v;-•
\
\
ELECTRICAL SPECIFICATIONS AT 25°C
Parameter
••
'NV
±40V
±30V
Output Short Circuit Duration
-[
64 MILS
Vs = ±10V to ±20V
85
Vs = ±10V to ±15V
-
Vs
Vs
= ±15V, R = 10Kn
= ±15V, RL = 2Kn
Vs=±15V,Vo=0
12
TYPICAL ELECTRICAL CHARACTERISTICS
157-N
157-G
Units
mV
dB
rnA
157-GR
These specifications apply for Vs = ±15V.
Parameter
Average Input Offset Voltage
Symbol
TCVOS
Typ"ical
Test Conditions
RS
0;;
50n
Drift
Input Offset Current
Input Bias
Curren~
lOS
IB
Slew Rate
SR
AVCL =5
Settling Time to 0.01 %
ts
AVCL =5
Gain Bandwidth Product
GBW
Typical
4.0
5.0
6_0
3.0
4.0
5.0
30
30
40
50
50
50
1.5
20
14'34
Typical
1.5
20
1.5
20
Units
/JV/oC
pA
pA
V//Jsec
,usee
MHz
725
INSTRUMENTATION OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
CHIP LAYOUT AND DIMENSIONS
I'"
Junction Temperature (Tj)
9.Jpply Voltage
Differential Input Voltage
Input Voltage
Output Short Circuit Duration
I;
-65°C to +150°C
±22V
±30V
Supply Voltage
Indefinite
Parameter
Input Offset Voltage
Vs =
'. .. • 1
725-N
Symbol
VOS
Test Conditions
-
CMVR
Common Mode Rejection
Ratio
CMRR
VCM ~ ±CMVR
RS';;; 20kn
PSRR
Vs ~ ±3V to ±18V
RS';;; 20kn
YOM
Ava
(VOUT~OV)
Po
5.0
80
"-
MilS
725-GR
-
2.5
Units
mV
-
13
-
35
nA
-
110
-
125
nA
-
Mf!
±13.5
-
±13.5
-
±13.5
-
V
120
~
100
-
94
-
dB
-
10
-
35
-
±12.0
-
±12.0
-
V
±11.5
-
±10.0
-
V
-
-
-
-
V
-
500
-
250
-
V/mV
-
±30
-
±30
-
130
V
-
105
-
150
-
150
mW
5.0
RL'" lkn
±11.0
1000
±15V
Max
Min
-
±12.0
~
1.3
-
±12.5
Vs
-
0.5
RL '" 2kf!
RL '" 2kn
Vo ~ ±10V
Max
Min
-
RL'" 10kn
TYPICAL ELECTRICAL CHARACTERISTICS
These specifications apply for
0.5
-
Differential Input Voltage
Power Consumption
Camp
\
0.7
RIN
Input Voltage Range
Lareg Signal Voltage Gain
"
v-
725-G
Max
Min
RS';;; 20kn
-
Maximum Output Voltage
Swing
Non Inv
Input
±15V unless otherwise noted.
lOS
Ratio
V+
50
IB
Power Supply Rejection
1
I \
NULL
Inv
Input
Input Bias Current
Input Resistance
• •• /•
Output
Input Offset Current
Differential Mode
/
NULL
ELECTRICAL SPECIFICATIONS AT 25°C
These specifications apply for
"I
94 MilS
725-N
725'G
725-GR
Typical
Typical
Typical
IlVN
Vs = ± 15V.
Parameter
Svmbol
Average Input Offset
Voltage Drift
TCVOS
RS';;; 50n
0.7
1.4
2.0
IlV/'C
Nulled Input Offset
Voltage Drift
TCVOSN
RS';;; 50n
Rp ~ 20kn
0.3
0.5
0.6
IlV/'C
Average I nput Offset
Current Drift
TCIOS
Test Conditions
10
14-35
14
14
Units
pArC
I
4136
QUAD OPERATIONAL AMPLIFIER
ABSOLUTE MAXIMUM RATINGS
CHIP LAYOUT AND DIMENSIONS
Junction Temperature (Tj)
-65°C to +150°C
Supply Voltage
4136-N and 4136-G
±22V
4136-GR
±18V
Differential Input Voltage
±30V
Input Voltage
±15V
I-
-1
.'MILI
•
-INIBI
•
y-
•
-INlel
+IN(AI
OUTIA)
oUTlal
•
•
•
•
+INCBI
-INIAl •
y+ •
(For supply voltages less than ±15V, the absolute
maximum input voltage is equal to the supply voltage.)
Output Short Circuit Duration to Ground
+INICI
•
Continuous
(One amplifier only, ISC = 45mA typical.)
ELECTRICAL SPECIFICATIONS AT 25°C
-INIDI •
OUTtC)
y+
• • •
4136·G
unless otherwise
specified
Symbol
Input Offset Voltage
Vas
Input Offset Current
lOS
Test Conditions
Max
Min
-
Rs";; 10KO
5.0
-
200
500
Input Bias Current
IB
-
Input Voltage Range
CMVR
±12
Common Mode Rejection Ratio
CMRR
VCM = ±CMVR, RS ..;; 10kO
Power Supply Rejection Ratio
PSRR
RS";; 10kO
-
Maximum Output Voltage Swing
VOM
RL ;;.10kO
±12
·l.arge Signal Voltage Gain
Ava
RL;;' 2kO, Va = ±10V
Power Consumption
Po
VOUT = 0, No Load
RL;;' 2kO
70
+IN(DI
•
1
4136-GR
Vs =±15V
These specifications apply for each amplifier unless otherwise noted.
Parameter
OUTID)
1
Vs =±15V
unless otherwise
specified
-
6.0
-
200
-
500
-
±12
-
70
150
-
Max
Min
-
-
150
Units
mV
nA
nA
V
dB
p.VIV
±12
-
V
±10
-
±10
-
V
50,000
-
20,000
-
VIV
-
340
-
340
mW
(Four Amplifiers)
TYPICAL CHARACTERISTICS
4136-G
4136-GR
Typical
Typical
These specifications for Vs = ±15V, TA = 25°C, unless.otherwise noted.
Parameter
Symbol
Slew Rate
SR
Unity Gain Bandwidth
GBW
Channel Separation
CS
Test Conditions
AV = 1, RL;;' 2kO
AV = 100, f = 10KHz
RS = lkO
NOTE: Either or both V+ pads may be used without any change in performance.
14-36
Units
1.5
1.5
V/p.sec
3.0
3.0
MHz
105
105
dB
REF-OI
+ IOV PRECISION VOLTAGE REFERENCE
CHIP LAYOUT AND DIMENSIONS
ABSOLUTE MAXIMUM RATINGS
14
_65° C to +150° C
Junction Temperature (Tj)
Input Voltage
REF01·N and REF01·G
REF01·GR
Output Short Circuit Duration
(to ground or V IN)
'-1
63 MILS
• •1
/
Input
40V
30V
Indefinite
/
Output
40
*NC
Ground Trim-\
MILS
.-l~~)..
ELECTRICAL SPECIFICATIONS AT 25°C
REF01·N
REF01·G
1
REF01·GR
These specitications apply for VIN;:;: +15V unless otherwise noted.
Parameter
Vo
IL = 0
Output Adjustment Range
,c;Vtrim
Rp = 10kn
Input Voltage Range
VIN
Max
Min
Max
Min
Max
10.10
9.85
10.15
9.80
10.20
V
-
%
30
V
-
±3.0
40
13
VIN = 13 to 33V
-
VIN = 13 to 30V
-
0.01
-
±2.7
13
30
-
-
line Regulation
TYPICAL ELECTRICAL CHARACTERISTICS
These specifications apply for VIN -= +15V, TA
Parameter
Symbol
Units
Min
9.90
Test Conditions
Symbol
Output Voltage
-
REF01·N
-
0.D15
REF01·G
13
-
-
-
0.04
%iV
%iV
REF01·GR
= 25°C, unless otherwise noted.
Test Conditions
Typical
Typical
-
0.006
IL = 0 to 10 mA
Load Regulation
-
IL=Oto8mA
Typical
0.006
Units
-
%/mA
0.10
%/mA
Output Voltage Noise
e np _p
0.1 Hz to 10 Hz
Turn-on Settling Time
ton
To ±O.l% of final value
5.0
5.0
?O
p,sec
Ouiescent Current
ISY
No load
1.0
1.0
1.0
rnA
Load Current
IL
Sink Current
IS
Short Circuit Current
ISC
Output Voltage
Temperature Coefficient
TCVO
20
21
0.5
Vo =0
14-37
25
21
0.5
25
21
0.5
/Np·p
mA
rnA
30
30
30
mA
10
20
50
ppm/DC
I
REF-02
+5V PRECISION VOLTAGE REFERENCE/THERMOMETER
..
CHIP LAYOUT AND DIMENSIONS
ABSOLUTE MAXIMUM RATINGS
,
Junction Temperature (Tjl
• •1
Input Voltage
I
REF02-N and REF02-G
REF02-GR
40V
Output Short Ci rcu it Duration
Indefinite
Input
30V
/
Output
40
*NC
-.1••.. 1
MILS
Ground Trim.:
*NC~".
TemP.......
(to ground or VINl
ELECTRICAL SPECIFICATIONS AT 25°C
..,
63 MILS
-65°C to +150O C
REF02-N
REF02-G
REF02-GR
These specifications apply for VIN = +15V unless otherwise noted.
Parameter
Symbol
Test Conditions
Output Voltage
Vo
IL = 0
Output Adjust Range
lIV tr im
Rp = 10kn
Input Voltage Range
VIN
Max
Min
4.95
5.05
Min
Max
4.925
±3.0
-
±3.0
7
40
7
5.075
30
VIN =8 to 33V
-
0.01
-
-
VIN=8to30V
-
-
-
0.015
Line Regulation
TYPICAL ElECTRICAL CHARACTERISTICS
REF02-N
Max
Min
4.90
5.10
-
-
7
30
-
-
-
0.04
REF02-G
REF02-GR
Typical
Typical
Units
V
%
V
%/V
%/V
These specifications apply for VIN = +15V, TA = 25'C, unless otherwise noted.
Parameter
Temp Voltage Output
Temp Voltage Output
Temperature Coefficient
Output Voltage Temperature
Coefficient
Symbol
Test Conditions
VT
(Note)
TCVT
(Note)
Typical
630
2.1
10
TCVO
IL =Oto 10mA
0.006
Load Regulation
-
IL =0 to 8mA
20
630
630
2.1
2.1
20
50
-
-
Units
mV
mVI'C
ppm/'C
%/mA
0.006
.010
-%/mA
Output Voltage Noise
e np _p
O.lHz to 10Hz
Turn-on Settling Time
ton
To ±0.1% of final value
5.0
5.0
5.0
SLsec
Qu iescent Current
ISY
No load
1.0
1.0
1.0
mA
Load Current
IL
Sink Current
IS
Short Circuit Current
ISC
NOTE:
21
0.5
30
VO=O
25
21
0.5
30
25
21
0.5
30
IlVp-P
mA
mA
rnA
On Temp Output, limit load current to ±50nA and load capacitance to 30pF. See AN-18 for detailed REF-02 thermometer applications
information.
14-38
I
NUMERICAL INDEX
IORDERING INFORMATION
I Q.A. PROGRAM
IINDUSTRV CROSS REFERENCE
FUNCTIONAL REPLACEMENT GUIDE
I OPERATIONAL AMPLIFIERS
I COMPARATORS
I
MATCHED TRANSISTORS
IVOLTAGE REFERENCES
lOlA CONVERTERS - LINEAR
lOlA CONVERTERS - COMPANDING
I'MUL TIPLEXERS
I
I
DEFINITIONS
CHIPS
APPLICATION NOTES
I PACKAGE INFORMATION
I
NOTES
OJ
rn
rn
rn
IT]
rn
ITJ
rn
rn
IlQ]
[[]
ITIJ
IrnJ
IrnJ
mJI
II]]
ImJ
iNDEX
APPLICATION NOTES
"AGE
AB-l
AB-2
AB-3
AB-4
AN-6
AN-l0
AN-ll
AN-12
AN-13
AN-14
AN-15
AN-16
AN-17
AN-18
AN-19
AN-20
AN-2l
AN-22
AN-23
AN-24
Strobing the DAC·OB Under Logic Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OP-l0 Instrumentation Amplifier CMI'IR Versus Frequency Improvement . . . . . . . . . . . . . . .
Digital Nulling of OP·05 and SSS725 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
REF·02 Temperature Controller
.......................................... .
A Low Cost, High Performance Tracking AID Converter . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simple Precision Millivolt Reference Uses No Zeners
............................ .
A Low Cost, Easy·to·Build Successive Approximation Analog·to·Digital Converter
........ .
Temperature Measurement Method Based on Matched Transistor Pair Plequires No Reference .. .
The OP·07 Ultra·Low Offset Voltage Op Amp.
A Bipolar Op Amp That Challenges Choppers, Eliminates Nulling .... , . . . . . . . . . . . . . .
Interfacing Precision Monolithics Digital·to·Analog Converters With CMOS Logic . . . . . . . . . . .
Minimization of Noise in Operational Amplifier Applications . . . . . . . . . . . . . . . . . . . . . . . . .
Low Cost, High Speed Analog·to·Digital Conversion with the DAC·08 . . . . . . . . . . . . . . . . . . .
DAC·OB Applications Collection
.......................................... .
Thermometer Applications of the R EF·02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential and Multiplying Digital·to·Analog Converter Applications . . . . . . . . . . . . . . . . . . .
Exponential Digitally Controlled Oscillator Using DAC-76 . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 IC 8 Bit Binary Digital to Process Current Converter with 4-20 MA Output . . . . . . . . . . . . .
Software Controlled Analog·to·Digital Conversion Using DAC·08 and the 8080A Microprocessor.
Digital·to·Analog Converter Generators Hyperbolic Functions
...................... .
The OP-17, OP-16, OP-15 as Output Amplifiers for High Speed D/A Converters . . . . . . . . . . .
15-1
15-2
15-3
154
15-5
15-11
15-12
15-19
15-25
15-36
1540
15-50
15-51
15-68
15-71
15-79
15-82
15-84
15-88
15-91
APPLICATION BRIEF NO. ____'_
AUTHOR _..:B=o::b:...:B::.:'a:.:;ir:..:a:;n::.:d:...D=on:.:.n:.:...::S.:.o.:.de:;r~q:.::u:;is.:.t_ _ _~_
TITLE: -=.ST.:...;R~O::.:B::.:I~N:.::G:....T:..:.H.::E:...:D::.:A:...:.C::.-..:::O.::..8.=:U:;.::N:,:D:,::E:;.::R:....::L:..:O:.,:G::.;.I.::.C.=:C:,::O:;.::N:..:.T:;.::R:.=O:,::L'--_ __
CIRCUIT
VTH = V LC + 1.4V
TTL DIGITAL INPUTS
"AU
V+
VHIGH = DIGITAL INPUT ENABLE
LOW = DIGITAL INPUT DISABLE
10k
1/6 TTL
HEX INVERTER
7404
•
FEATURE SUMMARY
DESCRIPTION
Digital inputs are treated as all zeros by increasing the
logic threshold to +6.4 V.
Since the PM I DAC·08 has a variable logic input threshold,
strobing the output is easily accomplished using the circuit
above. Normally, for TTL thresholds, pin 1 (VLcI is
. grounded; but if it is connected instead to a hex inverter
with a pullup resistor to +5V, all digital inputs effectively
become zeros. All current flows in '0; no current flows in
10 no matter what the digital input code may be. When the
hex inverter's output is low, normal TTL input logic
threshold and operation is restored.
• Single Line Logic Control
•
Handy in Multiplying Applications
• When more than one DAC is connected to point
"A" - party line connection - strobing is simple.
•
Higher speed and simpler than the alternative method of
disabling which is accomplished by reducing V REF to
zero.
Note:
Recovery when logic inputs are enabled may be
slower when DAC is on +5V supply due to bias
line saturation. This should be checked in the
actual application.
15-1
I
APPLICATION BRIEF NO. --l!i2!!...AUTHORS
Donn Soderquist and George Erdi
TITLE: OP-10 INSTRUMENTATION AMPLIFIER CMRR VERSUS FREOUENCY IMPROVEMENT
CIRCUIT
TRIPLE OP-AMP INSTRUMENTATION AMPLIFIER
2)
AVCL
3)
CMRR
If
400Hz
5)
R6
R4
00
R1+R2)
( 1 + I'i3
= 20
log
R6)
(Fi4
ecm IAVCL)
eo
=
1000
@ DC
R7
= Rs,CMRR@DCs:120dB
At 400Hz CMRR is a function of the difference
in frequency response of side "A" and side "S".
6)
Use of C1 or C2, selected using the procedure
below, matches the frequency response of side
"A" and side "B" thereby maximizing CMRR at
400Hz.
lOkI<
'Selected 5pF to 100pF
DESCRIPTION
FEATURE SUMMARY
•
Addition of one selected capacitor improves CMRR
at 400Hz to >95dB.
•
OP-10 Side
matched.
"A" and Side "B" bandwidths are
•
Circuit uses existing nulling pins as frequency compensation connections.
•
Added capacitor is in the range of 5pF to 100pF.
CAPACITOR SELECTION PROCEDURE
Common mode rejection ratio (CM R R) versus frequency
of the familiar three-op-amp instrumentation amplifier
can be optimized by matching the frequency responses
of the input differentially-connected pair of op amps.
The circuit shown uses one selected capacitor (to reduce
the frequency response of the faster op amp) which is
connected between an output and one of the pins
usually used for nulling AVos.
Eight devices were tested in this connection. Improvement to greater than 95dB @ 400Hz was achieved on all
devices, an improvement of 1 to 20dB over performance
without the selected capacitor.
1. Connect ein1 to ein2 and to a 400Hz ±10V signal
source.
2. While observing eo with an oscilloscope, try different
values of C1 or C2 until eo is at a minimum.
3. Permanently install the selected capacitor.
15-2
APPLICATION BRIEF
NO.~3_
AUTHOR Charles Vinn
TITLE:
DIGITAL NULLING OF OP-05 AND SSS725
CIRCUIT
r--------------------------,
v+
SUCCEEDING
STAGES
+I~V
VII
+10V
REF·01 Vo,t--.....JV\I\r-i
IN (+1
IN H
o-""::'!:':--+--""::::::-....J
I
v+
v-
PRECISION OP AMP EQUIVALENT CIRCUIT
1
------------------------~
'0 + iQ
NOTE: TeVos may be degraded.
=
'FS
'0 "" lA} 'REF WHERE
EA,J=
~~~~~~~~~~N=~~:g:'~N
FEATURE SUMMARY
DESCRIPTION
•
Digitally·controlled offset nulling is achieved by im·
balancing the first stage collector currents of a
precision op amp.
•
Greater than 1.5 mV of offset voltage may be nulled
to zero with 511V resolution at 25° C.
•
This application is especially useful in microprocessor·
controlled systems where stringent error budgets exist.
•
Circuit uses the nulling terminals with a DAC·08
substituted for the conventional nulling potentiometer.
The input offset voltage of a precision op amp (OP·05
or OP·07) may be nulled to <511V using the complemen·
tary current outputs of a DAC·08 to change the ratio of
collector currents in the first stage. With Vas being
defined as the voltage which must be applied between
the input terminals to force VaUT to zero and assuming
all errors to be in the first stage, VOS may be expressed
as:
ICl
IS2
kT
where
1) Vas = q loge IC2
ISl
k = Boltzmann's constant = 1.38 x 10.23 joules/"K
T = Absolute temperature, oK
q = Charge of an electron = 1.6 x 10. 19 coulomb
IS = Theoretical reverse·saturation current
IC = Collector Current
Changing the ratio IC1/IC2 over a ± 3% range results in
an input offset voltage nulling range of greater than
1.5mV at 25°C.
15-3
I
APPLICATION BRIEF NO._4...£....AUTHOR~Bo~b~B~la~ir~
_____________________
TITLE: REF-02 TEMPERATURE CONTROLLER
1
CIRCUIT
v+ (12TO 32VI
R7
R6
-
I
1 I I
1,--+
MSB
LSB
CURRENT OUTPUT
D/A CONVERTER
BASIC TRACKING AID BLOCK DIAGRAM
FIGURE 1
15-5
MseJ
FINAL CIRCUIT DESIGN
When encoding a DC input signal, the digital output will
"dither" or alternate between the two adjacent states which
span the theoretically correct output value. This is of little
consequence as all A/D converters have a similar error, known
as the "quantizing" error.
The completed 8 bit tracking AID design is shown in Fig. 3.
The digital output is available in complemented form, as the
DAC-100 utilizes complementary logic. Diode clamps insure
the DAC output remains near zero despite input and turn-on
transients. For this 8 bit design, the two least significant
digital inputs of the 10 bit DAC are not required and are
connected to +5V, thus turning them off. Diodes are also
used to insure that a positive voltage is applied to the V+ pin
(pin 14) as soon as the +5V supply comes up. The clock,
although extremely simple, is quite stable over a wide range of
temperatures and supply voltages. Several layouts were tried,
with no perceptible differences in performance. (See Fig. 4)
In the actual circuit design, a "type-D" flip-flop is inserted
between the comparator and the counter's up/down input.
This is to insure adequate set-up time between the comparator's output change and the counter's next stage change.
Loop timing can be seen in Fig. 2. After the positive dock
transition, the counter changes to its next state and drives the
DAC to its new output. After the DAC has settled and the
comparator has come to its final state, the next positive clock
transition loads the comparator's new state into the flip-flop
and the cycle repeats.
TRIMMING
The circuit requires only one trimming operation. The fullscale output current of the DAC is adjusted to produce proper
encoding at full scale input. Although several schemes are possible, the simplest is to place +10.0V at the input, and trim
the 200£2 Full Scale Adjust pot to produce a low output at the
7 most significant bits with the LSB alternating states (dithering) at the clock frequency.
CLOCK
"O"-FF OUTPUT
--,L-____
COUNTER OUTPUT _ _ _ _oJ} I':,
STATES (TYPICAL)
.
,
,
COMPARATOR
OUTPUT
--l
VOLTAGE OUTPUT APPLICATIONS
The basic tracking AID uses a "current-comparison" technique; the analog voltage is not reconstructed at the comparator's input, thus eliminating the need for an op amp to
convert the DAC-100's current output to a voltage. For applications such as infinite (no-droop) analog sample-and-hold circuits, the OP-01CJ, a low cost, fast slewing, fast settling op
amp with internal compensation can be added as in Fig. 5.
This configuration alsq provides very high input impedances,
without requiring an extra buffer amplifier. The reconstructed
analog voltage is available at the output of the op amp; gating
.
the counter "off" stores the data in analog form.
i:,
,,
1 lr------------
-----4j..J/
--+! f+- ~~~~g~~~~~~OR
OAC SETTLING TIME
SYSTEM TIMING DIAGRAM
FIGURE 2
r---------------------,
I
I
-15V
:
240n
* 1/4
7400 I
I
I
CLOCK :
OUT I
I
I
I
I
I
I
I
~3~
IL ____________________
I
I
I
I
I
I
I
I
~~~2'
1111
}OIGITAL
OUTPUT
~
9 8 7 6 5~4~------~-o+5V
1312 1110
LSB
~
DAC-l00CCQ3
10 BIT D/A CONVERTER
4.88kQ
ANALOG
INPUT
'";:;+-_ _ _ _ _ _'"""::~---::,.-...J14
V,N = 0 TO .IOV
R'N ~ 4.8kn
MAXIMUM FULL SCALE
SINE WAVE INPUT
IS 4000Hz
-----------0 -15V
"1:....--....
1+502 +t5Cil.
-1.:..0 2
1..
J;
-15Cil
.J.,.02
J:,
COMPLETE SCHEMATIC - B BIT TRACKING AID CONVERTER
FIGURE 3
15-6
,b
POWER
GROUND
ANALOG
GROUND
BACK
FRONT
CONNECTOR
FRONT
BACK
ANALOG GND
ANALOG GND
~
HV
ANALOG IN
~
~
DIGITAL GND
CLOCK
N.C.
DIGITAL
OUTPUT
TRACK
a HOLD
2'
~
2°
+15V
N.C.
---&14~
N.C.
-15V
FRONT
ACTUAL SIZE PRINTED CIRCUIT LAYOUT - CIRCUIT OF FIG. 3
FIGURE 4
8 BIT TRACKING AID PARTS LIST
Description
Quantity
1
2
4
5
DAC-l00CCQ3 D/A Converter
CMP-Ol CJ Comparator
8284 Up/Down Counters
7474 Dual D-Type Flip-Flop
7400 Quad Gate
200n Trimpot, Bourns 3359P
IN4.148 Diodes
Ceram ic Capacitors
Carbon Composition Resistor
PC Board
15-7
I
TRACKING AID CONVERTER WAVEFORMS
These scope photos were taken to indicate the waveforms observed at the comparator input during normal and
abnormal operation of the converter. The output analog voltage trace was generated by applying the encoded
digital output to a second DI A converter.
NORMAL OPERATION
Comparator Input
Analog Input
Reconstructed Analog Input
INPUT OVER-RANGE
Comparator Input
Analog Input
Reconstructed Analog Input
SLEW RATE LIMITING
Comparator Input
Analog Input
Reconstructed Analog Input
15-8
IIWOLAtII OPERATION
0_05% APPLICATIONS
Bipolar operation (±5V) can be obtained by injecting a current equal to 1/2 the full ,scale current into the DAC-l00 sum
line, This can be accomplished by applying +6.4V to the
internal i;)ipolar resistor of the DAC-loo (pin 1)-a 500n
trimpot in series will allow precise ad~ustment of bipolar symmetry. To trim, apply -5,OV at the input and adjust the 500n
symmetry-trim pot to produce a high output at all bits, with
the normal "dither" in the LSB only, Next, ground the input
and adjust the Full Scale trimpot to produce an output which
alternates getween 10000000 and 01111111.
Applications requiring 10 bits of resolution with 0.05% linearity can be implemented by adding a thi'rd up/down counter
and utilizing all 10 inputs of an DAC-l00ACQ3 (or Q4).
See Fig. 5.
PERFORMANCE
Performance of the completed converter is quite impressive
despite the low cost and small size. Using clock rates of 3,0
MHz, 10Vp-p signals can be accurately tracked to frequencies
of about 4,0 kHz; higher frequencies can be accommodated
by reducing the peak-to-peak amplitude,
Fully monotonic operation is obtained from 0° to 70°C; this
is achieved because the DAC-l00CQ3 is guaranteed to have
±1/2 LSB linearity to 8 bits (0.2%) over this temperature
range, and the DAC-100ACQ3 has ±1/2 LSB linearity to Hi)
bits (0.05%).
() TO -t5V OI'fRATION
Operation with 5 volt full scale inputs (OV to +5V or ±2.5V)
can be obtained by specifying the DAC-loo CCQ4.
I
1
Q
TYPE "0" .,
FLlP- FLOP
C
CLOCK III
t
hP~
Ie
UID
UP/90WN
COUNTER
I
[
"
1
CARRY
l' c'
upy~
COUNTER
+ 5v
1
1
INI
"I
CARRY
f
louT UPIDOWN
C COUNTER
r
TRACK
INp
-=
T
NOT USEO-
~l
DIGITAL
OUTPUT
I
ANAL061tj.
(HIGH III",)
/-
~
I
..-
UID
1
..L
LSB
MSB
\~
15-9
I
OAC-IOO ACQ3
1
19 ItIT VOLTAGE OUTPUT AID CONVERTER BLOCK DIAGRAM
FIGURES
2J
ANALOG
OUTPUT
Other performance characteristics of the completed converter
are listed in Table 1.
All D.C. static errors can be attributed to the analog com·
ponents only; the comparator makes no contribution to linearity errors, but its Vos and Vos drift witn temperature are a
consideration in the zero scale and full scale performance, and
especially so in bipolar applications. The worst case DAC-l00
zero error over O°C to 70°C is 0.6mV; adding to this the
3.5mV max Vos of the CMP-01C results in a worst case zero
scale error of 4.1mV, which is acceptably small compared to
the value of 1/2 LSB (19.5mV) for the 8 bit A/D.
MILITARY TEMPERATURE RANGE OPERATION
Operation over wider temperature ranges can be obtained by
simply specifying appropriate temperature range components.
The simplicity of the all IC design coupled with the compatibility with MIL-M-38510 processing assures high reliability in
military applications.
Because the Vos drift of the CMP-Ol C is typically only
1.8/lV /oC even without offset trimming, the full scale drift will
be almost entirely a function of the DAC-l00CC tempco6Oppm/oC maximum.
CONCLUSION
Extremely compact, low power consumption, all IC tracking
A/D converters are made possible by combining Precision
Monolithics, Inc. DAC-l00 series 10 bit D/A converter, CMP-Ol
series comparator, and commercially available MSI up/down
counters. Layout, construction and adjustment are noncritical.
The simplicity and low cost of the tracking A/D converter
invites usage in many new applications, including single channel
digitizing at remote transducer locations.
For 10 bit applications, the comparator Vos becomes significant; the CMP-01C can be nulled, or the 0.8V max Vos
CMP-Ol E can be utilized without nUlling. Nulling of the comparator is not required in bipolar applications; this is accomplished by the bipolar symmetry trimming.
TABLE 1
APPENDIX - USEFUL DATA & FORMULAE
PERFORMANCE DATA
8 Bit
10 Bit
10V full scale
5V full scale
39.1mV
9.85mV
19.5mV
4.92mV
Nonlinearity (O°C to +70°C) 0.2% max
0.05% max
Full Scale Tempco
(O°C to +70°C)
60 ppm max
60 ppm max
Zero Scale Error
(O°C to +70°C)
.10 LSB max
.20 LSB max*
Max Clock Frequency = I/(T A + T B + T c + To + T E)
Zero Scale Error
Comparator Trimmed
(O°C to +70°C)
.02 LSB
.08 LSB
WHERE:
Full Scale Voltages
OV to +10V,
±5V
LSB -
8 bits
10 bits
Loop Slew Rate
= Clock
Frequency X VLSB
= fc X VLSB
TA
Flip-Flop Propagation Delay
TB
Minimum Counter Set-Up Time
OV to +10V
±5V
Tc
Counter Propagation Delay
OV to +5V,
±2.5V
OV to +5V,
±2.5V
TO
D/A converter Settling Time
(to n-bits)
Power Supply Rejection
(OoC to +70°C)
.02% per
%max
.02% per
% max
TE
Comparator Response Time
Power Consumption
(V s = ±15V, +5V)
l.4W max
1.77W max
Min Clock Frequency
*untrimmed
CMP~01
1r -
Vin p _p • fin max
VLSB
E
15-10
PMI
Application Notes
®
AN-10
SIMPLE PRECISION MILLIVOLT REFERENCE USES NO ZENERS
by
Donn Soderquist
A low output impedance millivolt source is frequently reo
quired in test systems, for generating small currents with moder·
ate resistance values, and for general laboratory use. An
excellent millivolt source can be built using only two parts; an
instrumentation op amp and a potentiometer. The op amp is
connected as a unity·gain buffer (Fig. 1) and the output is
adjusted to the required voltage using the offset nulling
terminals. The amplifier must have suitable characteristics such
as low long term drift, freedom from chopper and "popcorn"
noise, good power supply rejection and low offset voltage drift
with temperature. To achieve low. output impedance the op
amp must have high gain around zero output Voltages, and
should have negligible thermal·induced drift for stable perform·
ance under varying load conditions. Use of a high performance
bipolar input op amp such as the Precision Monol ith ics OP·05CJ
provides low drift without chopper noise. With a typical
initial offset voltage of O.3mV, outputs from about -3.5mV
to +3 ..5mV can be achieved. Adjusting the offset of the
OP·05CJ to a value other than zero will create a drift equal to
3.3!1V fc per millivolt of output setting. The circuit's low
frequency noise will be less than O.65ilV pk·pk with an output
impedance of. less than one milliohm. Long term drift will be
much less than 3.5!1V per month and power supply rejection
is about 10ilV/Volt.
+15V
>6=-_.....__-0 VOUT
FIGURE 1
ZENER lESS PRECISION MILLIVOLT SOURCE
15-11
I
PMI
Application Notes
AN-ll
A LOW COST, EASY-TO-BUILD SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER
by
Donn Soderquist
Tracking AID converters use upldown counters for the programming logic; the comparator output forces the counters to
"track" the changes in the analog input_ Once initial "lock" is
acquired the correct digital output is continuously available,
and the converter may be capable of encoding fairly fastmoving input siganls without requiring a sample and hold
circuit_ (Complete details on the construction of th is type of
converter are available in Precision Monolithics Application
Note "A Low Cost, High Performance Tracking AID Converter", AN-6).
Successive Approximation Analog-to-Digital Converters have
often been considered to be complex, expensive and troublesome circuits to produce_ This application note describes a
high-speed 8 bit successive approximation AID easily constructed using only 3 readily available IC's_ Precision Monolithics' DAC-100 Digital-to-Analog Converter, CMP-01 Fast
Precision Voltage Comparator, a Successive Approximation
Register plus a handful of discrete components complete the
design_ Despite the simplicity, the AID is capable of 8 bit conversions in 6 I-Isec, and can easily be expanded to 10 bit
resolution operation_
Tracking ADC's are at their best when used to encode a single
signal with a well-behaved maximum slew rate; multiplexed or
video signals have large discontinuities which cause large errors
while the tracking loop moves to acquire a new "lock" on the
signal.
FEEDBACK AID CONVERTERS
Most popular AID Converters built today use a Digital-toAnalog Converter as part of a feedback or servo loop_ Three
of the most common types are the Ramp, Tracking, and
Successive-Approximation; these differ primarily in the type of
programming logic circuitry used to drive the DIA converter.
All three types perform a comparison between the analog input
and the output of a DJA converter; the logic changes the DIA
output so that it approaches the analog input-when they are
equal, the input to the DAC is the correct digitally encoded
number (Fig. 1).
Successive Approximation AID Converters are attractive for
their rapid conversion rates and have found wide acceptance in
video and multiplexed data systems. Recently-announced IC's
provide the three basic converter building blocks in integrated
form, reducing the cost and complexity of this approach to a
figure at or below that of the ramp and tracking types. The
great advantage of the SA ADC is that complete "n"-bit
conversions can be accomplished typically in N + 1 clock
periods-for a 10 bit converter this would be a speed improvement of about 100 times over the ramp type.
END-Of-ENCODE
TRIAL I
START
CLOCK INPUT
COMPARATOR
~+---+-1----oMSB
,
LSB
v
<
(JOO)
IrI
I
TRIAL 2
I
I
(110)
-
II
The Ramp or Count-up type ADC uses up-counters for the
programming logic. A start command clears the counters which
then count up until the comparator output changes. The user
must allow 2 n clock periods to insure a complete conversion;
therefore only very slowly varying. data may be converted.
(V N SHOWN IN PARENTHESIS)
I
I
III!!
lool~
II
100
011
I
OOOI~
15-12
~~~
I~OOO
I
FLOW DIAGRAM FOR 3 BIT SUCCESSIVE
APPROXIMATION AID CONVERSION
FIGURE 2
III
110
.L)01
ILOIOI~
I
FIGURE 1
M
Analog Ground-h
Analog Ground-h
L
Analog Input
K
N.C.
N.C.
N.C.
Bit 5
Bit 6
Bit 7
Bit a
Power Ground
~
Power Ground
~
Analog Ground
Analog Ground
N.C.
Bipolar Reference Voltage Input
a
N.C.
7
BitT
6
5
4
3
ait
Bit
Bit
Bit
2
5 Start
N.C.
+15 Volts
-15 Volts
+5 Volts
1
2
3
4
Clock Input
H
F
E
0
C
B
A
CC
Conversion Completed
DO Serial Output
B-SIT AID LAYOUT
FIGURES
CALIBRATION
PERFORMANCE
For unipolar, 8-bit, 10 volt full scale calibration apply +9.941
volts (Full scale -3/2 LSB) to the input. Adjust the gain
potentiometer until the digital output is alternating between
"0000 0000" and "0000 0001". This calibrates the converter
at a transition point insuring correct outputs over the analog
input range. No zero adjust is necessary due to the low comparator input offset voltage (Vos). virtually zero output offset
of the DAC and the correct +1/2 LSB bias establ ished by R 1.
Performance of the completed converter for 6, 7 and 8 bit
resolution applications is shown in Table II. To assure fully
monotonic operation in 8 bit applications the DAC-l00CC
grade with its maximum nonlinearity of 0.2% from 0° to 70°C
should be specified. Applications requiring 8-bit resolution
with 0.3% or less
linearity may utilize the lower cost
DA(}100DD types.
For a-bit, ±5 volt full scale offset binary operation, first perform the unipolar calibration as described above with the
bipolar reference removed. Next connect the +6.4 volt bipolar
reference through the 500 ohm potentiometer to the bipolar
input resistor. With -5.000 volts as an analog input, adjust the
500 ohm potentiometer until the digital output is alternating
between "1111 1111" and "1111 1110". For calibration at
lower bit resolutions refer to Table 1.
All D.C. static errors can be attributed to the analog components only; the comparator makes no contribution to
nonlinearity .but its 25°C Vosand Vos drift with temperature are
a consideration in the zero scale and full scale performance,
and especially so in bipolar applications. The worst case
DAC-100 zero error over 0° to 70°C is 0.6mV; adding to this
the 3.5mV max Vos of the CMP-01 C results in a worst case
zero scale error of 4.1mV, which is acceptably small compared
to the value of 1/2 LSB (19.5mV) for the 8 bit NO.
15-15'
I
Because the Vos drift of the .CMP-Ol C is typically only
1.81.1V fc even without offset trimming, the full scale drift
will be almost entirely a function of the DAC-l00CC tempco60ppmfC maximum_ (Tempco of DAC-l00DD models is
120ppmfC.)
SN 7400
QUAO 2·INPUT
NAND GATE
REDUCED RESOLUTION APPLICATIONS
Encoding time may be reduced in applications not requiring
the full 8 bit resolution_ In convert-on-command applications,
the negative-going transition of the (N+l) bit may be used as
the Conversion Completed (CC) signal; the register will continue to step through the remaining bits.so the CC level will be
present for one clock period only. For continuous conversion
applications, the register may be truncated by applying a low
SHORT-CYCLED CONTINUOUS ENCODING
(ALTERNATE METHOD INCLUDING CLOCKI
FIGURE 9B
10 BIT APPLICATIONS
The basic 8-bit converter may easily be expanded to 10 bits
by using a 2504 12 bit Successive Approximation Register;
it may be allowed to step through all 12 bits or shortcycled as described above (Fig. 9A,9B). All DAC-l00 Series
devices have 10-bit resolution; for applications requiring 10
bit monotonic performance the DAC-l00AC03: or 04 grades
with maximum nonlinearity of ±0.05% (0° to 70°C) should
be specified; for less demanding applications the ±0_1%
DAC-l00BC03 (04) grades are recommended. Due to the
10mV LSB size, comparator Vos can provide significant
zero error. This can be eliminated in unipolar applications
by nulling the CMP-Ol CJ or specifying the 0.8mV offset
CMP-Ol EJ. No initial Vos improvement is required in bipolar
applications, as this error will be eliminated during the
bipolar calibration procedure. The offsetting resistor (R 1)
should be 15Mn for 10 bit applications, with the full scale
calibration voltage of +9.985 for unipolar applications.
SHORT-CYCLED CONTINUOUS CODING
(6 BITS SHOWN I
FIGURE9A
level to the S input; however, caution must be observed to
prevent possible stalling on power-up: the S input should be
generated by either the CC or bit (N+l) going to a low state.
Figure 9 demonstrates a 6 bit, continuous-encoding application. Since reducing the resolution increases the size of the
LSB, the value of Rl and the full scale calibration point should
be changed accordingly, as shown in Table I. Additioryal speed
in reduced resolution applications may be achieved by increasing the clock frequency.
+15
BIPOLAR REF.
INPUT 0 ANALOG
(IF REa'D)
INPUT
14
16
+15V
15
20011
FULL
SCALE
ADJUST
-15V
LS8
13121110987&54
BIT 10 ---I--+--I-+-+-+-+--I-~
_-~i-+--I-+-+-+-+--I~
BIT
BIT
BIT
BIT
BIT
Brt 89__--1--+--1-+-+-+-+____
7__--1--+--1-+-+-+.....
6..--+-+-++-+.....
5,_--+-+-++--4
4_--+-+-+....
+15"
I
.Ol,.f
r
r OV
50V
,..J7 I
3::==:t=i--1
BIT 2
BIT
MSB BIT I
-lev •
MSB iiiTi
+5V
.Olp'
I+ ..
1~~
•
1+
+15V
ANALOG
GROUND
I~'V.. -lev
...+-. +5V
+5v.~..0-~!t----11
.OI}I'
T50V
L
1
4 •71"
IOV
-:1-r-..j~-------1.~ :~~~:D
START
INPUT
CONVERSION
COMPLETE .....0 _ - - - - - - - '
g5~~~~-----------~
COMPLETE 10 BIT AID SCHEMATIC
FIGURE 10
15-16
SYSTEM CONSIDERATIONS
LOWER POWER CONSUMPTION
When integrating the AID Converter into a system, consideration must be given to several factors to assure best performance.
First, the analog signal to be encoded should not change more
than 1/2 LSB during the encoding process; a sample-and-hold
circuit should be used if required to hold changes to 1/2 LSB
or preferably, much less (Fig. 11). Second, proper grounding
of the system is essential to prevent errors due to system
noise. The preferred method is to connect the analog signal
ground and digital power ground together at only one point,
right at the AID's connector. This will insure that digital
ground currents do not flow in the analog ground line.
Power consumption may easily be reduced from 935 mW
maximum to about 310 mW with two minor design changes.
The D/A and comparator power supplies can be reduced from
±15 volts to ±6 volts and the low power TTL AM25L02PC
logic function may be specified. Digital output fanout is
reduced to 3 standard TTL loads. The value of Rl
must also be lowered accordingly to maintain the same +1/2
LSB bias current to the sum node.
MILITARY TEMPERATURE RANGE OPERATION
Operation over wider temperature ranges can be obtained by
simply specifying appropriate temperature range components.
The simplicity of the three IC designs coupled with the compatibility of the devices withMI L-STD-883A processing assures
high reliability in military applications.
CONCLUSION
Extremely compact, rugged,low power consumption successive
approximation AID converters are made possible by combining
3 IC's; PMl's DAC-l00 Series 10-bit D/A, CMP-Olcomparator,
and a Successive Approximation Register. This simple, low
cost design opens up new applications such as one AID per
channel operation in data acquisition systems.
TYPICAL MULTIPLEXED DATA
ACQUISITION SYSTEM
FIGURE 11
PARTS LIST
PARTS LIST
FOR
FOR
8 BIT AID CONVERTER
10 BIT AID CONVERTER
::0.3% maximum nonlinearity, FS tempco 120ppmfC
2
2
3
±0.1% maximum nonlinearity, FS tempco 60ppmtC
DAC-l00DD03 (or 04)
DAC-100BC03 (or 04)
CMP-01CJ
CMP-01EJ
AM2502PC (Advanced Micro Devices)
or Equivalent
AM2504PC (Advanced Micro Devices)
or Equivalent
Pot-200n Bourns #3006P-1-201
Pot-200l2 Bourns #3006P-1-201
4.7 Ilf CAP- Mallory #TDC475M010EL
4.7 Ilf CAP Mallory #TDC475M010EL
2
1.0 Ilf CAP- Mallory #TDC105M035EL
Diode, 1 N4148
.01 Ilf CAP-Centralab #CK-l03
PC Board
1.0 Il.f CAP Mallory #TPC105M035EL
2
Diode, 1 N4148
3
.01 /If CAp· Centralab #CK-103
PC Board
Resistor 15MQ 5% 1/4W
Resistor 3.9Mn 5% 1/4W
For±0.2%maximum nonlinearitY,FS tempco 60ppmtC
use DAC-l00CC03 (or 04)
For ±0.05% maximumnonlinearitv, FS tempco 60ppmtC
use DAC·l 00AC03 (or 04)
15-17
I
TABLE I - REDUCED RESOLUTION APPLICATION DATA
Resolution
Desired
8
7
6
5
4
Bits
Bits
Bits
Bits
Bits
Offset Current
Value 11/2 LSB)
Conversion
Complete
Indicator
Full Scale
Calibration
Point
LSB
(10 VFS)
3.9J..1.A
7.8J..1.A
15.6J..1.A
31.3J..1.A
62.5J..1.A
CC
Bit 8
8it 7
Bit 6
Bit5
9.941V
9.883V
9.766V
9.531V
9.163V
39mV
78mV
l56mV
3l3mV
625 mV
3.9 Mil
2 Mil
1 Mil
470 Kil
240 Kil
Resolution
D/A
0° to 70° Maximum
Nonlinearity
TABLE" - PERFORMANCE DATA
6·Bits
7·Bits
DAC-100DDQ3
DAC·100DDQ3
±O.3%
±O.3%
8·Bits
DAC·100CCQ3
±0.2%
0° to 70°C Full Scale
Tempco Max.
l20ppmtC
l20ppm/"C
60ppmtC
Zero Scale
Error Max.
±0.05 LSB
±O.l LSB
±0.2 LSB
Conversion Time
1.5 MHz Clock
4.7 J..I.sec
5.3llsec
6.0 Ilsec
Unipolar Reference
Internal
Bipolar Reference
External +6.4 Volts
Input Impedance (+10V or ±5VScale)
5Kil Nominal
Input Impedance (+5V or ±2.5V Scale)
2.5Kil Nominal
Quantizing Error
±1/2 LSB
Output Code Unipolar
Complementary Binary
Output Code Bipolar
Complementary Offset Binary
Clock
External
Logic Output Drive Capability
6 TTL Loads
Analog Power Supply Range
±6V to ±18V
Digital Power Supply Range
+5 Volts ±5%
Power Consumption ±15V and +5V Supplies
935 mW Max.
15·18
PMI
Application Notes
AN-12
TEMPERATURE MEASUREMENT METHOD BASED ON MATCHED TRANSISTOR PAIR
REQUIRES NO REFERENCE
by
Jim Simmons and Donn Soderquist
Most remote temperature measurements are made with
thermistors or thermocouples as the sensing elements. This
article shows how the function can be accomplished by
using the intrinsic properties of a well·matched monolithic
transistor pair. The method is attractive for its simplicity
accuracy, and long·term stability. Of particular utility is the
fact that the output is inherently linear and is directly
useable without special linearizing circuitry.
Thermocouples can require both linearizing circuitry and
reference junction making them difficult to apply. Linear
outputs may be achieved with composite thermistor·resistor
networks but long·term stability is difficult to predict.
Ordinary silicon diodes, when operated as temperature
sensors, require constant current drive and extensive cali·
bration. The matched transistor pair method has none of
these drawbacks.
BASIC THEORY
Matched transistor pairs have predictable relationships
which make temperature measurements possible. To
develop these relationships, let us consider the fundamental
properties of a single transistor. The well known relation·
ship between collector current and base·emitter voltage for
a single transistor is:
11 Vbe = qkT loge
f-\ liSC)
provided IC/IS
>>
The values of IS1 and IS2 are a strong function of
processing and geometry variables, and are very nearly
identical in a well·matched monolithic transistor pair. As
IS1 and IS2 approach equality (loge 1=01. the second term
can be eliminated. For an ideal pair the expression be·
comes:
kT
q
10ge
Note that if the ratio of collector currents ICI to IC2 is
made constant, ~ Vbe will be proportional to absolute
temperature alone. No absolute values of current are reo
quired because only a stable current ratio must be main·
tained. For a fixed ratio of 2 to 1 the expression is:
~Vbe
5) - - = 5.973 X 10.5
59.73j.LvtK
~T
This predictable differential base·emitter voltage relation·
ship allows a matched transistor pair to be used as a
temperature sensor. A complete temperature measuring
system can be built with a matched pair, two constant
current sources, and a differential amplifier as shown in
Figure 1.
I
1
SENSING PAIR
where
k = Boltzmann's constant = 1.38x10·23 joules/"K
T = absolute temperature, 0 K
q = charge of an electron = 1.6x10· 19 coulomb
IS = theoretical reverse·saturation current"'" 1 .87 x
EO'IOmV/OK
oK
Eo
-55°C-2IS0K=+2.ISO v
0C;
10. 14 A
+25°C=298°K=t2.980 V
IC = collector current
+125°C=398°K=t3.980 V
Consider the difference in base·emitter voltages, L'Nbe' of
two transistors operated at the same temperature:
2)
~Vbe = ~T
loge (
:~~
) -
kqT
loge
(:~;
v-
)
This expression may be rewritten to:
3)
~Vbe = ~T
loge
(:~~)
BASIC TEMPERATURE SENSOR
kT
q
FIGURE 1
15-19
SYSTEM DESIGN CONSIDERATIONS
CONSTANT CURRENT SOURCES
To illustrate this concept, let us design a system to provide
accurate temperature measuremtlnt over the range of
-55°C to +12S o C (21So K to 39S o K). Other goals are: ease
of calibration, long·term stability, standard resistor values,
and small physical size. In addition, the system should be
capable of operation with the sensing matched pair located
up to 100 feet from the current sources and !lifferential
amplifier. A system achieving these goals is detailed below.
Two currents of a precise 2 to 1 ratio are provided by this
section. Several considerations make SILA and 1OILA good
choices as nominal operating currents for IC2 and ICl
respectively. Most monolithic matched transistor pairs are
specified at IC ; 10lLA.lnput bias currents associated with
the differential amplifier can be ignored because 51Lt\. is
three orders of magnitude larger. Resistor values are small
enough to keep physical size and cost reasonable. Finally,
the quiescent currents do not develop significant voltage
drops in 100 feet of ordinary shielded-pair cable.
SENSING MATCHED PAIR
Any mismatch will cause performance to deviate from the
ideal case shown in" Eq. 4, the most critical parameter being
average offset voltage drift (TCVos)' This quantity, multiplied by the largest temperature excursion (1000 K) and the
differential a"mplifier gain (167.4), will be the output error
and is shown in Table 1 for typical TCVos specifications.
The two most important current source transistor
matching characteristics required are hFE and Vos
long-term stability, assuming that this part of the circuit is
not subjected to wide temperature variations. If the system
is to have good power supply and ripple rejection, the hFE
match must be maintained over a range of operating
currents. These characteristics will insure a constant 2 to 1
ratio of ICl to IC2 is m"aintained.
Clearly, system accuracy is directly related to the degree of
matching of the sensing pair. A Pfecision Monolithics
MAT-01H with its typical TCVos of .1SILVfc was
specified in order to minimize this error factor.
With the circuit as shown in Figure 2, the total system has
measured power supply rejection of 10 K/volt. Once calibrated, long-term changes in Vos will change the current
ratio, and, in turn, the output. A Precision Monolithics
MAT -01 GH was selected for Q2 because it has the
desired combination of specified long-term stability
(.2j.lV/month) and close hFE matching, typically 1%.
Error in OK
TCVos
over 1000
.1SILVfc
.251°K
.5 ILvfc
.S37°K
1.01LVfc
1.67°K
133K
vEo VOLTAGE
2.0lLvfc
3.34°K
2.SILVfc
4.19°K
S.OILVtC
S.37°K
-C
"K
Eo
-5S·C- 2Iso K.+2.180V
+25- C· 29&-K-+2.98OV
+125 D C. 39S D K-+3..98OV
15K
y-
16fK
10ILVfc
BASIC TEMPERATURE SENSOR
FIGURE 1
TABLE 1
15-20
DIFFERENTIAL AMPLIFIER
In this system, (E in l - E in2 ) has been previously defined
as 6Vbe. The actual expression for Eo may be written as:
The sensing pair and constant current sources provide a
differential voltage (6 Vbe) which is directly proportional
to absolute temperature. The amplifier must acquire this
voltage difference in the presence of common mod~ volt·
ages, amplify it by 167.4, and change it from a differential
to a single·ended signal. Excellent performance is obtained
using the circuit of Figure 3.
8) Eo = 6Vbe
R4
(T3 of 1)
but
6V be
6T = 5.973 X
10. 5 (Eq.5)
Therefore, the ideal overall system output expression is:
9) Eo = (5.973 X 10. 5 )
(£.£
R3
+ 1) T
COMMON MODE REJECTION
IOOKn
600n
Goon
IOOKO
R3
R4
At 25°C (298°K), 6V be is 17.8mV. while the individual
sensing pair base·emitter voltages are about 520 mV. There
is a need to reject the 520mV. common mode input voltage
while accurately amplifying the differential input voltage,
6V be . At _55°C (218°K), the situation becomes more
difficult with 6V be of 13 mV. and 696 mV. of common
mode voltage. Keeping in mind that this is a best case
disregarding any extraneous cable pickup, it can be
observed that the requirement for high common mode
rejection is very real.
v+
Because the dual op amp has a specified 117 dB common
mode rejection ratio match, the ability to reject common
mode inputs becomes primarily a function of resistor ratio
matching. This device eliminates the need for special
opamp selections in this stringent differential amplifier
application.
DIFFERENTIAL AMPLIFIER DESIGN
FIGURE 3
Resistor selections can be avoided by using readily available
.01% tolerance precision resistors, resulting in a worst·case
ratio match of .04%. This ratio match, in combination with
the dual op amp's performance, results in greater than 100
dB common mode rejection at the amplifier's input.
The two op-amp differential amplifier configuration is
widely used wherever high input impedance and fixed gain
are required. This amplifier uses a dual matched instru·
mentation operational amplifier designed and specified for
differential applications, the Precision Monolithics
OP·10CY.
Long·term stability of the resistors must approach the
initial ratio match or degradation of common mode rejec·
tion can occur over time. The resistors chosen are specified
at ±50ppm/3 years and ±5ppm/"C thereby assuring stability
versus time and temperature.
GENERAL DESIGN CONSIDERATIONS
DIFFERENTIAL OFFSET VOLTAGE
Assuming ideal amplifiers, the expression for output voltage
is:
The amplifier's differential input offset voltage (Eosl Eos2) will be the major error factor. If the individual input
offset voltages are of equal magnitude and polarity they
appear as a common mode input and are rejected. The
OP·l0CY provides the additional convenience that only
a single offset adjustment is necessary to provide the reo
quired 6 Vos match; this adjustment at the same time
provides minimum TC6Vos of the differential amplifier.
t
E in , (1 +R2
-)
R,
-
R4 ]
R3
IiIIith ideal resistors this simplifies to:
7) Eo = (E in2 - E in l)
(~ +
R3
1) provided
~
R2
R4
R3
15-21
I
SENSING
PAIR
"'~'"
FEET
SHIELDED
~~I:LE
I
100Kn
600n
600n
RI.
R2
R3
R4
, --- ,
t
+I5V
---- ...~
.r
---- ...~
-=
100Kn
Eo..IOntV'-K
AI
1~3K
RS
CURRENT
SOURCES
-I~V
DIFFERENTIAL
AMPLIFIER
RATIO
ADJUST
-15V
COMPLETE SCHEMATIC
FIGURE 4
INSTALLATION
OVERALL ACCURACY
This circuit, with the components as specified, is capable of
±1°K accuracy over the full military temperature ·range of
-55°C to +125°C (21SoK to 39SoK). Optimum accuracy
is obtained with the differential amplifier and constant
current sources in a controlled environment remote from
the sensing pair. Maintenance of high accuracy over long
periods of time is achieved because all components used
in this design have long-term stability specified.
Ordinary shielded pair cable, with #22 or larger conductors,
is satisfactory for most remote temperature measuring
applications. Good thermal conductivity from the sensing
pair's case to the environment being measured is essential to
avoid incorrect readings. When this circuit is used for
temperature control, thermally·conductive epoxy works
especially well in attaching the sensing pair to the device
being controlled.
APPLICATIONS
The circuit's output, as measured by a 10·volt full scale
digital panel meter, makes a digital thermometer. DPM's
with BCD outputs may be used in applications requiring
simultaneous direct readout and digital outputs for control
purposes.
CALIBRATION PROCEDURE
This is an easy two·step procedure. First, short the differen·
tial amplifier inputs and adjust the offset potentiometer
until the output reads zero volts. Remove the input short.
Second, with the sensing pair at a known temperature
(room temperature is suitable l. adjust the ratio potentiometer for a correct differential amplifier output reading.
Having the capability of room temperature calibration
makes this circuit much more convenient to calibrate than
other ty pes.
CONCLUSIONS
Accurate temperature measurement and control systems are
easily and economically bui It using the predictable characteristics of modern monolithic matched transistor pairs.
This method offers long-term stability, excellent linearity,
simple calibration, and high performance in severe environ·
ments.
15-22
SENSING
PAIR
MAT-OIH
METER DISPLAYS
Eo -2.73V
·C
oK
Eo
-SsoCo:2IS°I<-2.ISV
+2S·C,.2:9soK-2.9SV
+125·C=39S"I<=;'.98 V
-55·CIf -.55V
+2S·C- +.25 V
+I2S-C- +1.25V
BASIC DIGITAL THERMOMETER WITH
READOUT IN DEGREES KELVIN (oK)
FIGURE 5
DIGITAL THERMOMETER WITH READOUT llil
FIGURE6
SENSING
PAIR
SENSING
YAT-OIH
PAIR
MAT-OIH
·C
"1<
Eo
-5S·C·2IS"K·2.ISV
+2S·C=29S''K:02.9BV
+125" C''39S''K:03.9SV
-K
Eo
-C
-S'''C-2IS·K-2.ISV
+2S-C-29soK=2.98V
+t2S''C:039S''K''3.9SV
BINARY-CODED TEMPERATURE READINGS
WITH 2° RESOLUTION
FIGURE 7
BINARY-CODED TEMPERATURE READINGI
WITH 5° RESOLUTION
FIGURE 8
15-23
°c
+15V
PRECISION POTENTIOMETER
SOUR-NS ... 36505-1-103
+5V
DIGITAL KNOBPOT@
oc
01(
Eo
-SS-C"2IS-I("2.ISV
+25"C=298"1(::2.98V
+12S-C= 39."K =3.98 V
BCD COOED TRUE OUTPUTS
NOTE: DIAL READS WITHIN
.1% OF APPLIED
VOLTAGE ,,10mV" '-1(
A>B·COOL
A-a-DEAD ZONE
A--*--OVo
Vo
Vos= 4000
LONG-TERM Vas TESTING CONDITIONS
The deceptively simple circuit of Fig. 8 is used for long-term
Vos stability testing. Three absolutely essential conditions
must exist for accurate measurements: still air, power supply
accuracy, and long-term temperature control.
LONG TERM OFFSET VOLTAGE TEST CIRCUIT
FIGURE 8
•
15-31
APPLICATIONS OF OP-07
Perhaps the most easily overlooked accuracy requirement in
this and many oth.er critical circuits, is long·term Vos stability.
In this circuit, a 741 drifting at 100JJV/mo would cause
200ppm/year of output drift-a very large amount. This type
of problem is particu larly troublesome in potted subassemblies
where periodic recalibration is impossible. Use of the OP·07
at lJJV /mo maximum avoids this potentially troublesome
condition.
HIGH STABILITY VOLTAGE REFERENCE
The simple bootstrapped voltage reference circuit of Figure 9
provides a precise 10 volts virtually independent of changes in
power supply voltage, ambient temperature, and output
loading. Correct zener operating current of exactly 2mA is
maintained by R 1 a selected 5ppmtC resistor, connected to
the regulated output. Accuracy is primarily determined by
three factors: The 5ppmtC temperature coefficient of D 1,
lppmtC ratio tracking of R2 and R3, and operational
amplifier Vos errors.
LARGE SIGNAL BUFFER-.005% WORST-CASE
ACCURACY
Unity gain large-signal buffers are one of the most common
applications of operational amplifiers. The low Vos and high
CMRR of the OP·07 provide high accuracy, and small physical
size is achieved due to the complete absence of external com·
ponents. Performance over the appropriate temperature range
is shown for the various OP-07 selections. Note that the errors
on Table IV are absolute worst·case numbers, a combination
that would be extremely unlikely in actual practice. A figure
closer to expected overall performance based on the RMS sum
of typical errors is also included. Typical mil temp range error
for the OP-07 A is 44JJV -far smaller than most other amplifiers'
input offset voltage error alone.
Vos errors, amplified by 1.6 (Avcl), appear at the output ~nd
can be significant with most monolithic amplifiers. For
example: an ordinary amplifier with TCVos of 5JJV /oC
contributes .8ppmtC of output error while the OP·07 at
.3JJVtC (0.5ppmtC) effectively eliminates TCVos as an error
consideration.
RI
~2mA
+15V
6
IN 4579A
6.4V±5%
±5ppm/o C
Eo=IOVOLTS
01
RI= 10-Vz
2xI0-'
R2
-=
Eo=±IOV
R2= 10-Vz
IxIO-'
EIN
±IOV
VZ
R3= IxIO-'
ZERO TO
20KCl
SOURCE
R3
AVCLa!I.6
-15VOLTS
±IVOLT
HIGH STABILITY VOLTAGE REFERENCE
FIGURE 9
LARGE SIGNAL VOLTAGE BUFFER
FIGURE 10
TABLE IV
LARGE SIGNAL VOLTAGE BUFFER ERROR ANALYSIS
OP·07 A-55° /+125°
Error
Source
Vas
1
1
MinIMax
Tvpical
60/lV
25/lV
OP·07 -55° /+125°
MinIMax
Tvpical
200/lV
60/lV
OP·07E 0° /+70°
MinIMax
130/lV
Tvpical
OP·07C 0° /+70°
Min/Max
TVPical
45/lV
250/lV
85/lV
44/lV
80;,v
20/lV
120/lV
40/lV
110/lV
30/lV
180/lV
CMRR 1
50/lV
7/lV
50/lV
7/lV
70/lV
7/lV
141/lV
10/lV
PSRR 1
40/lV
10/lV
40/lV
10/lV
63/lV
13/lV
100/lV
20/lV
Gain1
50/lV
25/lV
67/lV
25/lV
56/lV
22/lV
100/lV
25/lV
t>.Vos
5 years
60/lV
12/lV
60/lV
12/lV
90/lV
18/lV
120/lV
24/lV
Total
340/lV
44/lV"
537/lV
78/lV"
519/lV
63/lV"
891/lV
104/lV"
.0034%
.0005%"
.0054%
.0008%"
.0052%
.0006%"
.009%
.001%"
IBias
Percent
Full
Scale
"R MS Calcu lation
1 Full operating temperature range specifications.
15-32
CALIBRATION-FREE OAC TESTING SYSTEM
possible digital input code combination. It detects the largest
difference between a 14-bit linear reference OAC and a unit
under test, and generates an output voltage that is directly
proportional to nonlinearity as a percentage of full scale.
The circuit of Figure 1" is part of an automated test system
used for measuring 6-bit to 10-bit OAC nonlinearity at each
DAC SUMMING
AMPLIFIER
1.2SKO
140BIT .003%
LINEARITY
REFERENCE
DAC
XIO
DIFFERENCE
AMPLIFIER
l.s·-8mA.
10KO
IKO
Eo
6
IKO
TO PEAK
DETECTOR
-ISV
10KO
o TO 10 VOLTS
Eo=IO CEREF-EDuT)= % NONLINEARITY
DIA CONVERTER TEST SYSTEM
FIGURE 11
Reference DACs are frequently supplied having current-output
only, with selection of a summing amplifier left up to the user.
Summing amplifier characteristics must not cause degradation
of reference DAC linearity, full-scale, or zero scale performance
or erroneous testing could occur. In addition, Vos errors are
direct zero scale output errors, so both long term Vos stability
and drift over temperature are important. Using a OP'()7, total
Eref errors due to op amp performance are estimated at less
than 100J.LVor .2LSB on a 14-bit base, permanently eliminating
zero calibration while maintaining test system accuracy. Summing amplifier applications requiring higher speed should use
the composite amplifier of Figure 12.
Another OP-07 is used in the difference amplifier for high
common mode rejection and Vos stability. This op amp is
well-suited for critical test system circuits, providing accurate
measurements, hi!Jh reliability, and calibration-free operation.
A2 limits practical values of feedback resistances to a maximum
of 5Kfl in most applications; a fast FET input op amp could
be used as A2 to reduce the circuit's bias current to apprOldmately 2nA. The circuit is also good as a current-output OAC
summing amplifier because zero scale offset adjustments are
not required and high speed is preserved. Composite connections such as this are generally quite cost-effective compared
to single op amps having both high slew rate and good Vos
specifications
£'N
COMPOSITE SUMMING AMPLIFIER WITH HIGH SLEW
RA TE AND LOW Vos
RI
-15V
RF
Eo;:-E,MRi' + 1.,AS RF
The circuit configuration of Figure 12 is a method for obtaining a 18V/J.Lsec slew rate with OP-07 Vos characteristics. Vos
of A2 (3mV) is continuously nulled by forcing the sum node
to equal Vos of A 1 through a secondary feedback loop formed
by R1, R2, A2's input stage, and R3. An error due to IBias of
HIGH SPEED, LOW Vos COMPOSITE AMPLIFIER
FIGURE 12
15-33
I
.-ot.vtE
VALUE CIRCUIT WITH MINIMUM ERROR
For negative inputs, the first stage gain to point V A is -2/3
because 02 is on, 01 is off, and 1/3 of the input current,
Ein/Rl, flows in R3 and R4. The second stage is operated in a
non-inverting gain of 1.5 configuration with VA as its input,
giving an over-all circuit gain of -1.
this circuit provides precise full-wave rectification by inverting
OIIItive-polarity input voltages and operating as a unity-gain
buffer fer positive-polarity inputs. It is useful for conditioning
i1'llllJUts HI unipolar A to O's, positive peak detectors, single
qaadrant multipliers, and magnitude-only measurement syst.".... A J!1Olarity indication for sign plus magnitude applications
is IIIFesant at the output of A 1.
Using conventional op amps, input offset voltage is usually
the predominent error factor because it is doubled and added
to Ein. For example, with Ein of 100mV, only .5mV of Vos
will cause 1% output error. Clearly, Aland A2 must be low
Vos op amps to achieve high accuracy over the full input
voltage range. By using a OP-07, performance is mainly a
function of resistor ratio matching and diode leakages. Gain
errors due to resistor matching will typically be less than .03%
when R2-R4 are within .01% of R l's value. Low leakage
diodes should be used to prevent errors from reverse current
flow in R2 or R3 which would appear as Vos error of A2.
. F.,. a positive input, the circuit operates as two stages of
i.fti~ unity-g&in amplification. As the input goes positive,
... ~t lilt Al becomes negative, turning 02 off and 01 on,
pilMinll tf!e junction of R3 and R4 at -Ein. VA is at zero volts
r.lust In is off and only insignificant A2 bias current flows
in .2. Ai 9fJI!rates as a second inverting unity-gain stage and
flque4s "in.
r:.
R4
R3
10KCl
EIN
RI
:l:IOV
IOKCl
F0333
01
R5
10KCl
+15V
Ee
6
o TO+IOV
F0333
02
-15V
-15V
R2
IOKfl
VA
PRECISION ABSOLUTE VALUE CIRCUIT
FIGURE 13
PRECISION ABSOLUTE VALUE CIRCUIT
6) With R1=R2=R3=R4:
Negative Input
t) VA'" 0, fJ2 off, 01 on
"';Ein R3 )
t) Eo= ( -1'1-1- .
= Ein
:tl
Eo = -Ein
1) 01 off, 02 on
-Ein
2)
VA
R1 = R2 +
VA
R3 + R4
1'13 R5
ffiFi4
Wittl Rl=R3=R4=R5:
(a'" tin
4) Ves error included:
Eo = lin + 2'1os2
7) Vos error included:
Eo = -Ein + 1.5Vos2 - .5Vos1
8) For Both Inputs:
3) Eo = V A
(1 + R3R+5 R4)
4) With R3=R4=R5:
Eo =1.5VA
(R2) (R3 + R4) (1.5)Ein
5) Eo =-
R 1 (R2+R3+R4)
15-34
Eo = + IEinl
PRECISION SUMMING AMPLIFIER WITH NO
ADJUSTMENTS
stage at weekly or monthly intervals to compensate for
long-term Vos drift. This circuit, with l/-1V to 2/-1V per
month maximum change in Vos, completely eliminates
periodic calibration while insuring long-term accuracy.
Figure 14 shows the basic op amp connection for analog
computation, a precision summing amplifier. Analog computers use several of these stages connected in combinations
to produce continuous outputs that are a function of multiple input variables. Single-stage accuracy is important
because errors accumulate throughout a system and deter·
mine its over·all performance. Some analog computers
require time-consuming and annoying recalibration of each
Single-stage maximum full scale errors contributed by the
op amp range from .001% for a OP-07A to .004% for a
OP-07C. This makes resistor· related errors of ratio matching
and temperature tracking the major accuracy considerations.
Instrumentation quality operational amplifiers with ultralow Vos allow simple construction of high performance
summing and differencing amplifiers.
~IKn
R410Kn
j~~g~~gN ,IRj";\ RI RiB\
+ 15 VOLTS
RllOKn
Elo--'\N.-.....
R210Kn
E20--'\N.-.....~~~
R310Kn
R2
LINE
RESISTANCE
6
+15VOLTS
Eo
f O'200 (f.-E,)
LINE
RESISTANCE
R3A
R5
-15 VOLTS
2.5Kn
~~~~RENCEL
JUNCTION
ADJUSTMENT·FREE PRECISION SUMMING AMPLIFIER
FIGURE 14
These very small input signals often have sizable common
mode voltages present because thermocouples are frequently
located in high·noise industrial environments. The single
op·amp instrumentation amplifier of Figure 15 has the high
common mode rejection and long·term accuracy required
for this stringent application.
The amplifier achieves about 100dB of common mode
voltage rejection over a full ±13 volt range when the ratios
of R2/Rl and R4/R3 are matched within .01%. R1B and
R3B are usually around 1 Kn, a value large in respect to line
resistance but small enough to make voltage drops from
input bias currents negligible. Input voltages and Vos are
both amplified by 200 so Vos changes, either long·term or
due to temperature, can cause direct output error. For
example, with a 5/-1 V /oC thermocouple, the OP·07 A holds
this error factor to .5°C/year and 1°C for an amplifier
operating temperature range of 100°C (_25°C to +75°C)a typical industrial environment. For O°C to 70°C applica·
tions, the low·cost OP·07C holds output error due to a
change in Vos below 1°C/year and 2°C over the full com·
mercial operating temperature range.
R3B
R3--.1
"IKn
R~RI
-15 VOLTS
R4
~'*'200
HIGH STABILITY THERMOCOUPLE AMPLIFIER
FIGURE 15
CONCLUSIONS
INSTRUMENTATION AMPLIFIERS FOR
THE RMOCOUPLES
Thermocouples are very low voltage output temperature
transducers requiring differential DC amplification before
linearization and display. Typical full scale outputs are under
50mV with some types having as low as 511Vfc sensitivity.
Eos=Vos
The OP·07 Ultra· Low Offset Voltage Operational Amplifier
is a cost·effective monolithic alternative to the chopper·
stabilized amplifier and is suitable for a wide variety of
critical applications. An internal trimming procedure
achieves significant improvements over previous bipolar
designs in offset voltage, noise levels, and long·term stability
at a moderate cost. For the first time, a complete precision
IC op amp is available requiring no external components
whatsoever for general application, thus increasing relia·
bility by decreasing system complexity. The adjustment·
free, fully interchangeable device allows tremendous simpli·
fication of calibration and field servicing procedures. This
is a most powerful and cost·effective design tool-chopper·
type performance and bipolar prices with 741 ease·of·
operation.
REFERENCES
The circuit is useful whenever small differential signals from
low·impedance sources must be accurately amplified in the
presence of large common mode voltages.
15-35
(1)
Erdi, G. "Minimizing Offset Voltage Drift with Temperature in Monolithic Operational Ampli·
fiers." Proceedings of the National Electronic
Conference, Volume 25, 1969.
(2)
Erdi, G. "A Low Drift, Low Noise Monolithic Opera·
tional Amplifier for Low Level Signal Pro·
cessing." Fairchild Semiconductor Applica·
tion Brief #136, July 1969.
I
PMI
Application Notes
AN-14
INTERFACING PRECISION MONOLITHICS DIGITAL-TO-ANALOG'CONVERTERS WITH CMOS LOGIC
by
Donn Soderquist
The rise in popularity of CMOS logic has created a demand for
digital-to-analog converters with CMOS-compatible logic inputs.
The low current logic input stages in all Precision Monolithics
DAC's allow simple CMOS interfacing in most applications.
Since interfacing is easily achieved, the proven advantages of
low cost and high speed are available to both TTL and CMOS
system designers. This application note discusses interfacing
methods and rules for both voltage and current output types
and describes several typical CMOS system applications.
INTERFACING THE DAC-OS
The OAC-08 design incorporates a unique logic input circuit
which enables direct interface to all popular logic families and
provides maximum noise immunity. This feature is made possible by the large input swing capability, 2f..LA logic input current
and completely adjustable logic threshold voltage. For V- ~
-15V, the logic inputs may swing between -10V and +18V.
This enables direct interface with +15V CMOS logic, even when
the DAC-08 is powered from a +5V supply. Minimum input
logic swing and minimum logic threshold voltage are given by:
V- plus (lREF - 1 Kn) plus 2.5V. The logic threshold may be
adjusted over a wide range by placing an appropriate voltage
at the logic threshold control pin (pin 1, VLC). It should be
noted that pin 1 will source approximately 100f..LA; external
circuitry should be designed to accommodate this current.
INTERFACING THE DAC-02, OAC-03, AND DAC-04
Three complete voltage output monolithic DAC:s are described
in this section: the DAC-02 and DAC-03, 10-bit plus sign
devices, and the DAC-04, a 10-bit two's complement coded
converter. These DAC's are well-suited to use in CMOS systems
as their complete, internal temperature-compensated references
eliminate the external reference voltage requirement, a major
source of power dissipation, drift, and cost in some CMOS
compatible designs.
These DAC's have logic input stages which require about If..LA
and are capable of operation with inputs between -5 volts and
V+ less .7 volt. This wide input voltage range allows direct
CMOS interfacing in many applications, the exception being
where the CMOS logic and D/A converter must use the same
power supply.
In this special case, a diode should be placed in series with the
CMOS driving device's VD D lead as shown in Figure 2. The
diode limits VD D to V+ less .7 volt-since the output from
the CMOS device cannot exceed this value, the DAC's maximum input voltage rule is satisfied. Summarizing: in all
applications. these high-speed DAC's require either no interfacing components, or, at most, a single inexpensive diode for
full CMOS compatibility.
V+
v-
Fastest settling times are obtained when pin 1 sees a low
impedance. If pin 1 is connected to a resistive divider, as in
Fig. 1, it should be bypassed to ground by a 0.1 f..LF capacitor.
DAC-02/03/04
VTH
+12 V TO +15
0
VLC +1.4 V
+15V CMOS
+10V CMOS
+5V CMOS
VTH=+7.6V
vTH=+5.0Y
vTH=+2.BV
v~
ZENER
V + LESS .7 VOLTS
lN4148
VLe
v
s
6.2K&1
10Kn
6.2
INPUTS
+10V
VLC
6.2 K,o
TO,I,...F
' - - - - - i V••
CMOS DRIVING
DEVICE
V••
IN4148
3.6K~
DAC-08 CMOS INTERFACING
WITH TRUE CMOS THRESHOLD
DAC-02/03104 CMOS INTERFACING
FIGURE 2
FIGUR,E 1
15-36
INTERFACING THE DAC-100 AND DAC-01
CMOS COMPATIBLE OPERATION OF DAC·100 WITH ±6
VOLT POWER SUPPLIES
The DAC-l00, a complete 10-bit monolithic fast current output DAC is available in a wide range of electrical grades and
packages_ This device requires only about lilA of input current
into each logic stage_ Similar logic input stages are used in the
DAC-Ol, a complete voltage output 6-bit DAC_ One rule must
be observed when interfacing these DAC's with CMOS inputs:
logic input voltages should not exceed 6_5 volts or V+, whichever is smaller_ To provide an understanding of this rule, it is
necessary to discuss the logic input stage design_
This is the most convenient method of interfacing a DAC·l00
with CMOS logic. At ±6 volts, DAC·l00 power dissipation is
only 80mW, which is very small considering the inclusion of a
complete internal reference. No interfacing components are
required with ±5% power supplies, and the CMOS logic ar.d
DAC-l00 can use the same +6 volt power supply. In this
application the device is directly CMOS compatible.
v+
HIGH LEVEL CMOS INTERFACING
ANALOG
OUTPUT
The block diagram in Figure 4 illustrates a convenient method
for interfacing CMOS input . levels between 6.5 volts and 15
volts with a DAC-l00. Inexpensive and readily available CMOS
hex buffer/converters step down the high-level inputs to TTL
levels that cannot exceed 5 volts-clearly satisfying the input
stage voltage rule.
ZERO
VOLTS
In addition to level shifting, buffer/converters provide input
coding flexibility since they are available as inverting
(CD4049A) or noninverting(CD4050A) devices. This gives the
user a choice between negative-true and positive-true binary
coding and allows the same basic DAe 100·to·CMOS interfacing
method to be used in either type of application.
vDAC-100 LOGIC INPUT STAGE
FIGURE 3
Since buffer/converter power consumption is very low, the
required +5 volts can be provided by a simple regulator or even
a resistive divider in some applications. In a multi-DAC system,
one central, inexpensive 3-terminal IC regulator can supply
several level shifting devices. Next, we will examine a complete
circuit using all of these concepts in a high-speed CMOS com·
patible DAe.
DAC-100 LOGIC INPUT STAGE DESIGN
For simplicity, only one of the ten identical input circuits is
shown in Figure 3_ The DAC-l00 uses a fast currentsteering technique that switches a bit-weighted current between the positive supply (V+) and the analog output, which is
usually constrained to be at zero volts·(virtual ground). by an
external summing amplifier.
+6TO+18Y
I
Switching is accomplished by forward biasing 04, a diodeconnected transistor, for the bit "on" condition and back
biasing 04 in the "off" condition. For the "on" condition
(V IN". 7 volts), 03 is "off"-all of the bit-weighted current,
11, flows from the analog output through 04 and ultimately to
V-. In ,the "off" condition (VI N ;;;. 2.1 volts), 03 is "on", 04 is
back biased, and the bit-weighted current is sourced from the
positive power supply instead of the analog output.
LOW LEVEL
TTL OUTPUTS
If VI N is too high, 04's emitter-base junction will experience
reverse breakdown and a fault condition will occur. Equation
1 describes this condition:
Y••
Using this relationship, it can be seen that a conservative input
voltage limit would be around 6.5 volts. When the 6.5V input
limit is observed, DAC-l00 operation with CMOS inputs is
easily achieved as demonstrated in the following applications
section.
BLOCK DIAGRAM - CMOS TO DAC-100 INTERFACE
FIGURE 4
15-37
COMPLETE CMOS COMPATIBLE DAC
~
/'
The complete, 1O-bit, voltage output DAC in Figure 5 has
CMOS input compatibility, high speed, and low cost. Current
output from the DAC-100 is accurately converted to a voltage
by the Precision Monolithics OP-01, a high speed op amp which
has been specifically designed for the DAC summing amplifier
application. Input offset voltage of this op amp is typically
2mV., eliminating the requirement for zero scale adjustment.
The dynamic performance, as shown in the photograph, is
quite good. Slew rate is 18V//lsec while settling time to ±.05%
of full scale requires less than 1.5/lsec. DC performance is also
good since DAC-l00 nonlinearity is specified over the entire
temperature range. In addition, the internal temperaturecompensated voltage reference provides minimum full scale
drift and decreases overall circuit complexity.
DYNAMIC PERFORMANCE
+15 V
.--_ _ _ _ _ _ _ _..... ±IO%
Rl
5.1K
BI POLAR
ADJUST
FULL
SCALE
14
16
ADJUST 15r--~---~T-----~'
FSA
200
o TO 2mA
o
Al
DAC-IOO
-15V
LSB
OP-OI
NOTE: L1 AND L2 ARE CD4049A FOR
POSITIVE-TRUE CODING,CD4050A
FOR NEGATIVE·TRUE CODING.
INTERFACING DAC-100 WITH ±15 VOLT CMOS SYSTEMS
FIGURE5
15-38
OPTIONAL
BIPOLAR
REFERENCE
INPUT
+6V
ANALOG
INPUT
FULL
SCALE
ADJUST
+6V
IOKn
- 6V
+6V
v"
CLOCK
INPUT
LI
START
CONVERSION
+6V
00
CP
SC
FF
01
02
0'
O.
05
06
07
V"
So
SERIAL
OUTPUT
EOC
ENOOF
CONVERSION
MS.
LS.
NEGATIVE-TRUE
LOGIC OUTPUTS
8-BIT CMOS COMPATIBLE THREE IC SUCCESSIVE APPROXIMATION A TO 0 CONVERTER
FIGURE6
LOW COST THREE IC CMOS COMPATIBLE AID
CONVERTER
The diagram in Figure 6 is a modification of a previously
published application note circuit substituting CMOS logic for
TTL. All necessary logic for A to 0 conversion is contained in
l1, a MC14559 CMOS successive approximation register. A
conversion sequence is initiated by applying a positive pulse,
with a width greater than one clock cycle, to the "Start
Conversion" input. The analog input, applied to Rs and con·
verted to a current, is compared successively to 1/2 scale, then
1/4 scale, and the remaining binarily decreasing bit weights
until it has been resolved within ±1/2 LSB. At this time, "End
of Conversion" changes to a logic "1" and the parallel answer
is present in negative·true, binary-coded format at the register
outputs.
Tracking A to O's may be similarly constructed using CD4029A
up/down counters, a DAC-100, and a CMP-01 fast precision
comparator.
CONCLUSION
Precision Monolithics D/A converters may be easily incorporated into CMOS systems. Low current logic input stage designs
allow simple interfacing with a minimum of external components. The low power dissipation, high speed output and
low cost make this line of monolithic DAC's attractive in
CMOS system designs.
•
15-39
PMI
Application Notes
AN-15
MINIMIZATION OF NOISE IN OPERATIONAL AMPLIFIER APPLICATIONS
by
Donn Soderquist
INTRODUCTION
Since operational amplifier specifications such as input offset
voltage and input bias current have improved tremendously
in the past few years, noise is becoming an increasingly
important error consideration. To take advantage of today's
high performance op amps, an understanding of the noise
mechanisms affecting op amps is required. This paper examines
noise contributions, both internal and external to an op amp,
and provides practical methods for minimizing their effects.
BASIC NOISE PROPERTIES
Noise, for purposes of this discussion, is defined as any signal
appearing in an op amp's output that could not have been
predicted by DC and AC input error analysis. Noise can be
random or repetitive, internally or externally generated,
current or voltage type, narrowband or wideband, high fre'
quency or low frequency; whatever its nature, it can be
minimized.
The first step in minimizing noise is source identification in
terms of bandwidth and location in the frequency spectrum;
some of the more common sources are shown in Figure 1, an
11·decade frequency spectrum chart. Some preliminary obser·
vations can be made: noise is present from DC to VHF from
sources which may be identified in terms of bandwidth and
frequency. Noise source bandwidths overlap, making noise a
composite quantity at any given frequency. Most externally
caused noise is repetitive rather than random and can be
found at a definite frequency. Noise effects from external
sources must be reduced to insignificant levels to realize the
full performance available from a low noise op amp.
300KHz
1Hz
RADAR PULSE REPETITION FREQUENCY
DOMINANT REGION VF (FLICKER) HOtSE-PiNK NOISE DOMINANT REGION OF WHITE NOISE (JOHNSCJI a SCHOTTKY
.
MECHANICAL Vl8RATJON
SCR SWITCHING LARGE
LOADS
~~_?C
RADIO STATION
INVERTING
FREQUENCY
POPCORN NOt$E REGION
PICKUP
60Hz
PRINTED CIRCUIT BOARD
CONTAMINATION
POWER XFMR
SUPPLY EMI
,1
LINE
FREQ.
PICKUP
.001
.01
.1
10
R1Pr -----'IIV\r04-Q
v1)
fO
2rr RC
FIGURE 2
NOISE FREQUENCY ANALYSIS RC LOW PASS FILTER
With such a filter, measurement bandpass can be changed from
10Hz to 100KHz (C ~ 4.7fJ.F to 470pF), attenuating higher
TABLE 1
EXTERNAL NOISE SOURCE CHART
Nature
Source
Causes
Minimization Methods
Powerlines physically close to ap amp
60Hz Power
Repetitive Interference
inputs. Poor CMRR at 60Hz. Power
Transformer primary-ta-secondary capa~
Reorientation of power wiring. Shielded
transformers. Single point grounding.
Battery power.
citive coupling.
120Hz Ripple
Full wave rectifier ripple on ap amp's
supply terminals. Inadequate ripple con-
Repetitive
,sideration. Poor PSRR at 120Hz.
180Hz
Radio Stations
Repetitive EMI
Standard AM Broadcast
Through FM
180Hz radiated from saturated 60Hz
transformers.
Antenna
action
anyplace
in system.
Thorough design to minimize ripple. RC
decoupling at the ap amp. Battery power.
Physical reorientation of components.
Shielding, Battery power.
Shielding. Output filtering, Limited circuit bandwidth.
Relay and Switch
High frequency burst at
Arcing
switching rate
Proximity to amplifier inputs, power
lines, ·compensation terminals, or nulling
terminals.
Filtering of HF components. Shielding.
Avoidance of ground loops. Arc suppressors at switching source.
Random Low Frequency
Dirty boards or sockets.
Thorough cleaning at time of soldering
followed by a bakeout and humidity
Printed Circuit
Board
sealant.
Contamination
Radar
Transmitters
Mechanical
Vibration
High Frequency Gated At
Radar Pulse Repetition
Rate
Random
<
100Hz
Chopper
Common Mode Input
Frequency
Current At Chopping
Noise
Frequency
Radar transmitters from long range surface search to short range navigationalespecially near airports.
Loose connections, intermittent metallic
contact in mobile equipment.
Abnormally high noise chopper amplifier
in system.
15-41
Shielding.
Output filtering of frequencies
»
PRR.
A ttention to connectors and cable conmounting in seJere
ditions. Shock
environments.
Balanced source resistors .. Use bipolar
input op amps instead. Use premium
low noise chopper.
I
POWER SUPPLY RIPPLE
Power supply ripple at 120 Hz is not usually thought of as a
noise, but it should be. In an actual op amp application, it is
quite possible to have a 120 Hz noise component that is equal
in magnitude to all other noise sources combined, and, for
this reason, it deserves a special discussion.
caution must be exercised with this type of decoupling, as load
current changes will modulate the voltage at the op amp'5
supply pins.
n TIl![
120
11,11111
To be negligible, 120Hz ripple noise should be between 10nV
and 100nV referred to the input of an op amp. Achieving
these low levels requires consideration of three factors: the
op amp's 120Hz power supply rejection ration (PSRR). the
regulator's ripple rejection ratio, and finally, the regulator's
input capacitor size.
lIT
II
110
I~~t,
.~
'0
100
I-
~A
"J\
<
,.
'<"
0Q
/
PSR R at 120 Hz for a given op amp may be found in the
manufacturer's data sheet curves of PSRR versus frequency as
shown in Figure 3. For the amplifier shown, 120Hz PSRR is
about 74dB, and to attain a goal of 100nV referred to the
input, ripple at the power terminals must be less than .5mV.
Today's IC regulators provide about 60dB of ripple rejection;
in this case the regulator input capacitor must be made large
enough to limit input ripple to .5V.
mnrrI
~
N
I
TA;;;25°C
'°1
~
0L.9-
\ ~~ <1.>
."
",\
.'?>
""",
-
."
'~~\
80
I/'~
yo
y
10 ca-
?\I IQ-"f\ ~
%o ~~
~ ~
1~
Orr
70
-t-
-I
60
,00\
OJ
.01
10
1.0
100
FREQUENCY (KHz)
120
lllljl[lill
110
I
I
I Ild~I'6\·c'It,
TA~25°C
'!:Il~
100
FIGURE 4
PSRR VS FREQUENCY (SSS725, SSS725B, SSS725E)
v+
i'I\
," I
,
lOOn
I
70
~1\,
J
+
~I
60
li~
IOO,uF
ELECTROLYTIC
I
1\
50
0.1
1.0
10
100
FREQUENCY (Hz)
1000
10000
FIGURE 3
PSRR VS FREQUENCY COP-07.,OP.Q7CI
v-
Externally-compensated low noise op amps can provide
improved 120 Hz PSR R in high closed-loop gain configurations.
The PSR R versus frequency curves of such an op amp are
shown in Figure 4. When compensated for a closed-loop gain
of 1000, 120Hz PSRR is 115dB. PSRR is still excellent at
much higher frequencies allowing low ripple-noise operation in
exceptionally severe environments.
POWER SUPPLY DECOUPLING
Usually, 120Hz ripple is not the only power supply associated
noise. Series regulator outputs typically contain at least 150pV
of noise in the 100Hz to 10KHz range; switching types
contain even more. Unpredictable amounts of induced noise
can also be present on power leads from many sources. Since
high frequency PSR R decreases at 20dB/decade, these higher
frequency supply noise components must not be allowed to
reach the op amp's power terminals. RC decoupling, as shown
in Figure 5, will adequately filter most wide band noise. Some
FIGURE 5
RC DECOUPLING
POWER SUPPLY REGULATION
Any change in power supply voltage will have a resultant effect
referred to an op amp's inputs. For the op amp of Figure 3,
PSRR at DC is 110dB (3pV/V) which may be considered as
a potential low frequency noise source. Power supplies for low
noise op amp applications should, therefore, be both low in
ripple and well-regulated. Inadequate supply regulation is often
mistaken to be low frequency op amp noise.
When noise from external sources has been effectively minimized, further improvements in low noise performance are
obtained by specifying the right op amp and through careful
selection and application of the associated components.
15-42
OPERATIONAL AMPLIFIER INTERNAL NOISE
OP AMP NOISE SPECIFICATIONS
Most completely specified low noise op amp data sheets
specify current and voltage noises in a 1 Hz bandwidth and
low frequency noise over a range of .1 Hz to 10Hz. To mini·
mize total noise, a knowledge of the derivation of these
specifications is useful. In this section, the reader is provided
with an explanation of basic op amp·associated random noise
mechanisms and introduced to a simplified method for calcu·
lating total input·referred noise in typical applications.
@
!'-.
~'00
,'"
~
TYPICAL~
MAXIMUM
in
z
l!;i
III
RANDOM NOISE CHARACTERISTICS
~
Op amp-associated noise turrents and voltages are random.
They are aperiodic and uncorrelated to each other and have
Gaussian amplitude distributions, the highest noise amplitudes
having the lowest probability. Gaussian amplitude distribution
allows random noises to be expressed as rms quantities;
multiplying a Gaussian rms quantity by six results in a peak to
peak value that will not be exceeded 99.73% of the time (this
is a handy rule-of-thumb for noise calculations).
111111111
I
III
.J..-l-.i..lll.lJll-..l.J.JlIIUJIllIIIIIIIf..-.J....!.J.J.I.IlI.I-IL.l..lllJ.!lI-....Ll.11.Ll.W.II
I
1.0
.01
.10
1.0
10
100
1000
FREQUENCY (Hz)
FIGURE 6
SSS725 NOISE VOLTAGE
The two basic types of op amp-associated noises are white
noise and flicker noise (1/f). White noise contains equal
amounts of power in each Hertz of bandwidth. Flicker noise
is different in that it contains equal amounts of power in
each decade of bandwidth. This is best illustrated by spectral
noise density plots such as in Figures 6 and 7. Above a certain
corner frequency, white noise dominates; below that frequency
flicker (1/'1) noise is dominant. Low noise corner frequencies
distinguish low noise op amps from general purpose devices.
SPECTRAL NOISE DENSITY
To utilize Figures 6 and 7, let us consider the definition of
spectral noise density: the square root of the rate of change of
mean-square noise voltage (or current) with frequency (Eq. 2).
d
2A) e 2 = n
df
(En)2
d
28) i 2 = n
df
(In)2
I
FIGURE 7
SSS725 NOISE CURRENT
38) In
WHITE NOISE
Where: en, in
En, In
fH .
fl
Spectral noise density
Total rms noise
Upper frequency limit
Lower frequency limit
White noise sources are defined to have a noise content that is
equal in each Hertz of bandwidth, and Eq. 3 may be rewritten
for white noise sources as:
5) In (w)
Conversely, the rms noise value within a given frequency band
is the square root of the definite integral of the spectral noise
density over that frequency band (Eq. 3). This means that
three things must be known to evaluate total voltage noise
(En) or current noise (In): fH, fl' and a knowledge of noise
behavior over frequency.
=
in~
It is therefore convenient to express spectral noise density in
or A/VHz where fH - fl = 1 Hz. When fH ;;;, 10 fl' the
V
white noise expressions may be further reduced to:
15-43
IVHz
FLICKER NOISE
Since flicker noise content is equal in each decade of bandwidth, total flicker noise may be calculated if noise in one
decade is known. The .1 Hz to 1 Hz decade noise content
(K) is widely used for this purpose because the white noise
contribution below 10Hz is usually negligible.
8) En (f)
~
K.Jf
When substituted in Eq. 3, the expressions may be rewritten to:
11) In (f) = KJln (::)
input·referred voltage noise, over a given bandwidth, is the
square root of the sum of the squares of the five noise vOltage
sources over that bandwidth.
Minimization of total noise requires an understanding of the
mechanisms involved in each of the five generators. First, the
white noise mechanisms, thermal and shot, are discussed,
followed by the low frequency noise mechanisms, flicker and
popcorn.
THERMAL NOISE
FLICKER NOISE AND WHITE NOISE
When corner frequencies are known, simplified expressions for
total voltage and current noise (EN and IN) may be written:
12) EN(fH-f L) =
en~feeln(~)+ fH-fL
Thermal (Johnson) noise is a white noise voltage generated
by random movement of thermally·charged carriers in a resistance; in op amp circuits this is the type of noise produced by
the source resistances in series with each input. Its rms value
over a given bandwidth is calculated by:
Where:
13) IN(fH-fL) = in Jfci In (::) + fH-fL
Where: en
in
fee
fci
fH
fL
White noise voltage in a 1 Hz bandwidth
White noise current in a 1 Hz bandwidth
Voltage noise corner frequency
Current noise corner frequency
Upper frequency limit
Lower frequency limit
Boltzmann's constant = 1.38 x 10-23 joules!" K
k
T
Absolute temperature, 0 Kelvin
R
Resistance in ohms
fH = Upper frequency Iimit in Hertz
fL = Lower frequency limit in Hertz
At room temperature Eq. 15 simplifies to:
The two most important internally generated noise minimization rules are derived from Eq. 12 and 13: limit the circuit
bandwidth and use operational amplifiers with low corner
frequencies.
NOISE SUMMATION
In the spectral density discussion, the concepts of white
noise and flicker noise were introduced. In Figure 8, the
complete input·referred op amp noise model, internal white
and flicker noise soun;es are combined into three equivalent
input noise generators, EN, INI and IN2. The noise current
generators produce noise voltage drops across their respective
source resistors, RSI and RS2. The source resistors themselves
generate thermal noise voltages, Etl' and Et2 . Total rms
To minimize thermal noise (E t1 and Et2 ) from R'S1 and RS2,
large source resistors and excessive system bandwidth should
be avoided.
Thermal noise is also generated inside the op amp, principally
from rbb', the base-spreading resistances in the input stage
transistors. These noises are included in EN, the total equivalent input voltage noise generator.
SHOT NOISE
Shot noise (Schottky noise) is a wh ite noise current associated
with the fact that current flow is actually a movement of
discrete charged particles (electrons). In Figure 8, INI and IN2,
above the 1If frequency, are shot noise currents which are
related to the amplifier's DC input bias currents:
Where:
Ish
= RMS shot noise value in amps
= Charge of an electron = 1.59 x 10-19
IBIAS = Bias current in amps
fH
= Upper frequency limit in Hertz
fL
= Lower frequency limit in Hertz
q
FIGURE 8
OP AMP NOISE MODEL
At room temperature Eq. 17 simplifies to:
18) Ish = 5.64 x 10-10 -VI BIAS (fH - fd
15-44
Shot noise currents also flow in the input stage emitter
dynamic resistances (re ), producing input no:se voltages. These
voltages, along with the rbb' thermal noise, make up the white
noise portion of EN, the total equivalent input noise voltage
generator.
FLICKER NOISE
In limited bandwidth applications, flicker (lif) noise is the
most critical noise source. An op amp designer minimizes
flicker noise by keeping current noise components in the input
and second stages from contributing to input voltage noise.
Eq. 19 illustrates this relationship:
in second stage
19)
en input
gm first stage
FIGURE 10
OP-07 LOW FREQUENCY NOISE
Another critical factor is corner frequency. Forminimum noise
the current and voltage noise corner frequencies must be low:
this is crucial. As shown in Figure 9, low noise corner frequen·
cies distinguish low noise op amps from ordinary industry·
standard 741 types.
1000
1000
~
~
>l-
1000
VS·±15V
TA=25"C
RS'50n
i'-.
.....
TYPICAL
III NOISE
U 741
100
2.5MO
INPUT REFERRED NOISE ..
Z
'"
~
0
'"
0
en
1/1 NOISE
SSS 725
I'~ ....
Z
'"'"
;!
25~tOO· 152~~~~~ "200nV/cm
TYPICAL
ii;
10
..J
0
,-
"-
V~Eg3m~,.o;;
Ullllll LliIlIll
>
th
WHITE
NOISE
.10
.01
1.0
10
To begin the process, a specially treated thermal silicon dioxide
layer is grown. This protects the junctions and also attracts
any residual ionic impurities to the top surface of the oxide,
where they are held fixed. Next, a layer of silicon nitride is
applied to prevent the entry of any potential contamination
or impurities. The third step is the thick glass overcoat which
leaves only the bonding pads exposed. A cutaway view of a
finished device is shown in Figure 12.
III
tUM LIlW~
1.0
FIGURE 11
LOW FREQUENCY NOISE TEST CIRCUIT
III
100
1000
FREQUENCY (Hz)
FIGURE 9
NOISE VOLTAGE COMPARISON
The photograph in Figure 10, taken using the test circuit of
Figure 11, illustrates the flicker noise performance of the
OP-07. This device demonstrates proper attention to low
noise circuit design and wafer processing and achieves a
remarkable 0.35t.tV peak to peak input voltage noise in the
0.1 Hz to 10Hz bandwidth.
PRECISION MONOLITHICS
TRIPLE PASSIVATEDTM
INTEGRATED CIRCUIT PROCESS
POPCORN NOISE
Popcorn noise (burst noise) is a momentary change in input
bias current usually occurring below 100 Hz, and is caused by
imperfect semiconductor surface conditions incurred during
wafer processing. Precision Monolithics minimizes this
problem through careful surface treatment, general cleanliness,
and a special three-step process known as "Triple Passivation."
15-45
FIGURE 12
I
Op amp manufacturers face a difficult decision in dealing with
popcorn .noise. Through careful low. noise processing, it can be
eliminated from almost all devices; alternatively, the processing
may be relaxed. and finished devices must be individually
tested for this parameter. Special noise testing takes valuable
labor time, adds significant amounts to manufacturing cost,
and ultimately increases the price a customer has to pay. At
Precision Monolithics the low noise process alternative is used
to' manufacture high volumes of cost-effective low noise
op amps.
Eq. 12 and 13 also require en and in for calculation of EN and
IN. To find en and in, use the data sheet specification a
decade or more above the respective corner frequencies;
in this case en is 9.6 nV 1$2 (1000 Hz). and in is
0.12pA/$2 (1000 Hz).
1000
TOTAL NOISE CALCULATION
~
With data sheet curves and specifications, and a knowledge of
source resistance values, total input-referred noise may be
calculated for a given application. To illustrate the method,
noise information from the Precision Monolithics OP-07
data sheet is reproduced in Figure 13. The first step is to
determine the current and voltage noise corner frequencies so
that the EN and IN terms of Eq. 14 may be calculated using
Eq. 12 and 13.
THE::~~~I~:O::~ouitcEI-
j'q~
RESISTORS INCLUDED
'~IIIEXCLUDED
....
=t'f{
I I
~" ~'
" ... ~~;:±:::1:::$
~-
~
:-- ,
II
R~lJ
"---
OP-07
Vs·;t15V
TA-2S·C
CORNER FREQUENCY DETERMINATION
In the input spot noise versus frequency curves of Figure 13,
it may be seen that voltage noise (R s = 0) begins to rise at
about 10Hz. lines projected from the horizontal (white noise)
portion and sloped (flicker noise) portion intersect at 6 Hz, the
voltage noise corner frequency (fee)' In the' center curve,
excluding thermal noise from the source resistance, current
noise m\lltiplied by 200 Kn is plotted as a voltage noise.
lines projected from the horizontal portion and sloped portions intersect at 60Hz, the current noise corner frequency (foi).
I
1.0
10
1.0
1000
100
FREQUENCY (HzI
FIGURE 13A
INPUT SPOT NOISE VOLTAGE VS FREQUENCY
OP-07 ULTRA-LOW OFFSET VOLTAGE OP-AMP
ELECTRICAL CHARACTERISTICS
OP-07
OP-07A
These specifications apply f'or V s = ± 15V. T A = 25°C, unless otherwise noted.
Parameter
Input Noise Voltage
Test Conditions
Symbol
e np _p
Min
Typ
Max
Min
Typ
Max
---------
0.35
0.6
--
0.35
0.6
10.3
18.0
--
10.3
10.0
13.0
--
10.0
13.0
9.6
11.0
9.6
11.0
14
30
0.32
0.80
O.lHz to 10Hz
fo'" 10Hz
Input Noise Voltage Density
en
fo
=100Hz
fa'" 1000Hz
Input Noise Current
'np-p
O.lHz to 10Hz
fa"" 10Hz
Input Noise Current Densitv
'n
fa
=
100Hz
fo = 1000Hz
Input Offset Voltage
Long Term Input Offset Voltage Stability
30
0.80
--
0.14
0.23
--
0.14
0.23
0.12
0.17
--
0.12
0.17
--
30
75
~V
0.2
1.0
jN/Mo
0.4
2.8
nA
±1.0
±:I.O
nA
--
10
25
0.2
1.0
0.3
2.0
-_.-
±.7
±2.0
--
IS
pAp-p
pANHl
INPUT NOISE CURRENT (i np_p )
The peak to peak noise current in a specified frequency band.
INPUT NOISE VOLTAGE (-np-p)
The peak to peak noise voltage in a specified frequency band.
INPUT NOISE VOLTAGE DENSITY (enl
The rms noise voltage in a 1 Hz lland surroundiryg a specified value of
frequency.
14
----
Input Bias Current
nvr../Hz
0.32
Vos
los
jN pop
18.0
---
VoJTime
I nput Offset Current
Units
INPUT NOISE CURRENT DENSITY lin)
The rms noise current in a 1 Hz band surrounding a specified value
of frequency.
FIGURE 138
15-46
I
\
BANDWIDTH OF INTEREST
TYPICAL APPLICATION EXAMPLE
To be summed correctly. each of the five. noise quantities must
be expressed over the same bandwidth. fH-f L . At this time.
assume fH to be the highest frequency component that must
be amplified without distortion. Note that en. in. corner fre·
quencies and bandwidth are independent of actual circuit
component values. When doing noise calculations for a large
number of circuits using the same op amp. these numbers
only have to be calculated once.
Figure 14Ashows atypical Xl0gain stage with a 10Kn source
resistance. In Figure 148. the circuit is redrawn to show five
noise voltage sources. To evaluate total input-referred noise.
the values of each of the five sources must be determined.
Using Eq. 16:
Et
Et1
1.28 x 10-10 ...j(900n)(100Hz) = .04/Nrms
Et2
1.28 x 10-10 -Y(10Kn)(100Hz) = .128/Nrms
Next. calculate IN using Eq. 13:
R2
>-~-oEo
= .12pA
~
100Hz
60 In - - - + 100 - .0001
.0001 Hz
RSI'R~~R:2'900n
= 3.66pArms
RS2' R3' loKn
and:
FIGURE 14A
NOISE ANALYSIS CIRCUIT
IN1"RS1
=
3,.66 pA (900n) = .00331lVrms
IN2"RS2 = 3.66pA (10Kn) = .03661lVrms
Finally. EN from Eq. 12:
=9 ..6nV
~
100Hz
61n - - - + 100-.0001
.0001 Hz
= .1301lVrms
EO
Substituting in Eq. 14:
fH=IOOHz
fL=.OOO1 Hz
FIGURE 14B
NOISE ANALYSIS EQUIVALENT CIRCUIT
0.191lVrms
Total input-referred noise = 1.141lV peak to peak (.0001 Hz to
100Hz).
15-47
I
741 CALCULATION EXAMPLE
The preceding calculation determined total noise in a given
bandwidth using a low noise op amp. To place this level of
performance into perspective, a calculation using the industry·
standard 741 op amp in the circuit of Figure 14 is useful. Once
again the starting point is corner frequency determination,
using the data sheet curves of Figure 15: fee = 200Hz; fci =
2KHz; en =:; 20nV/y'Hz; in = .5pA/y'Hz.
Using these corner frequencies and noise magnitudes, EN and
IN are calculated to be l/LVrms and 83 pArms respectively.
Multiplying this noise current by the source resistance gives
terms 2 and 3 of Eq. 14 as shown below:
Total input·referred noise = 7.8/lV peak to peak (.0001 Hz to
100Hz).
. This is 6.8 times that of the low noise op amp example.
The calculation examples illustrate three rules for minimizing
noise in operational amplifier applications:
RU LE 1. Use an op amp with low corner frequencies.
RU LE 2. Keep source resistances as low as possible.
14)ENT(fH - fd= -VEN 2+ IN12 RS12+IN22 RS22+E+12 + E+22
Substituting in Eq. 14:
~(1 /lV)2 + (.075/lV)2 + (.83/lV)2 + (.04/lV)2 + (.128/lV)2
RULE 3. Limit circuit bandwidth to signal bandwidth.
1.3/lVrms
VS=±15V
VS '±15V
TA·25°C
TA '25°C
10- 22
:i:
N;
t-
~
~
'~
10- 23
a:
......
"u
'"'"~ 10- 24
" ,~
'"a:
,~..!..--
«
UA 74 I~
a=>
i
.
I
10- 25
UA741
'"
::E
10
100
IK
FREQUENCY (Hz)
, K
I
10- 26
lOOK
'0
100
IK
FREQUENCY (Hz)
10K
lOOK
FIGURE 158
INPUT NOISE CURRENT AS A FUNCTION OF FREQUENCY
FIGURE 15A
INPUT NOISE VOLTAGE AS A FUNCTION OF FREQUENCY
15-48
BANDWIDTH
Effective circuit bandwidth must not be much greater than
signal bandwidth or amplification of undesirable high frequency
noise components will occur. Throughout the preceding cal·
culations, an assumption of "bandwidth·of·interest" was made,
while in actual application the amplifier's bandwidth must be
considered.
120
r--
~
80
..:c
z
.. 40
S
z
~
'"'"
o
oP.O~
Y.":l:15Y-
than required, and output filtering, such as in Figure 17, could
be used. As an alternate to output filtering, an integrating
capacitor may be connected across the feedback resistor.
Bandwidth may also be limited in some applications by over·
compensating an externally·compensated low noise op amp,
such as the 555725.
r--
T.-+2S·C
10K ..
'"I'",,,
v-
1\
-40
0.1
1.0
10
100
Ik
10k
lOOk
1M
10M
FIGURE 17
OUTPUT FILTERING
FREQUENCY (Hz)
FIGURE 1SA
OPEN LOOP FREQUENCY RESPONSE
MISCELLANEOUS NOISE MINIMIZATION METHODS
Certain other noise mechanisms merit consideration: Use
metal film resistors; carbon resistors exhibit "excess noise,"
with both 1/ f and white noise content being related to DC
applied voltage. The use of balanced source resistors, while
sometimes good for DC error purposes, will increase noise;
the balancing resistor is not required for op amps such as the
OP·07, since los'" lB. Keep noise in its proper per·
spective; minimize it without introducing additional DC errors.
Use low noise op amps with overall DC specifications that will
satisfy the application.
loo',-----~----r_--~----~----~----,
80'+---~+---~~--~-----+----4----;
OP-07
Vs·t15V
T.-2S-C
j60'+-----~....~Ii.-----4-----4-----+----;
z
.S40'+-........
."
ii
........~....~Ii.-----4-----+----;
~
!Il
d 20+-........~........~........~....~'I.-----+---~
SUMMARY
O,+-----~--~----~--~~--~----1
A summary of the major points to consider is as follows:
-20+-........~........+-....__+-........+-........+-....~
10
100
Ik
10k
lOOk
1M
1)
2)
3)
4)
1011
FREQUENCY (H.)
FIGURE 1SB
CLOSED LOOP RESPONSE FOR VARIOUS
GAIN CONFIGURATIONS
Minimize externally generated noise.
Choose an amplifier with low 1/ f noise corner frequencies.
Limit the circuit bandwidth to signal bandwidth.
Eliminate excessive resistance in the input circuit.
CONCLUSION
In Figure 16, the OP·07 frequency response curves show
a roll off of 20dB/decade; integration of the area under the
curve will show the effective circuit noise bandwidth to be
1.57 times the 3dB bandwidth. In most c1osed·loop gain
configurations, the amplifier's bandwidth may be greater
Recent improvements in IC op amp DC specifications have
made noise an important error consideration. From data sheet
information and source resistance values, total input·referred
noise 'over a given bandwidth can be easily calculated. Total
noise can be minimized by a thorough understanding of the
various noise·generation mechanisms.
15-49
I
PMI
Application Notes
AN-16
LOW COST, HIGH SPEED ANALOG-TO-DIGITAL CONVERSION WITH THE DAC-OS
by
Donn Soderquist & John Schoeff
Today's f'1.st computer al1d microprocessor-controlled systems
frequently require AID converters which will complete a
conversion in one cycle time.
Until now, these high speed AID converters have been expensive and difficult to build. Most designers have therefore
chosen to purchase modular AID converters'typically ranging
in price from $100 to $400. This application note describes
three less costly AID designs, with total conversion times of
4lLsec, 2lLsec, and 1lLsec. These designs are implemented with
the DAC-08, a recently announced high speed monolithic
Digital-to-Analog converter. A discussion of basic successive
approximation is given, followed by practical circuit designs,
SUCCESSIVE APPROXIMATION AID ADVANTAGES
Successive approximation AID conversion is the most popular
choice in many systems today because it achieves high con·
version rates at very low cost. Other methods, such as
Tracking (Servo) or Staircase (Ramp), require up to "2 n " clock
cycles per conversion, where "n" is the number of bits of
resolution, while successive approximation requires only "n+1"
clock cycles. Finally, a designer can easily construct his AID
with readily available standard IC's.
BASIC SUCCESSIVE APPROXIMATION AID CONVERSION
A successive approximation AID converter operates by com·
paring the analog input to a series of "trial" conversions; the
first trial compares the input to the value of the most
significant bit (MSB) or approximately half of full scale. Fig. 1
shows the progression of trials for a 3·bit converter. If the
input is greater than the MSB value, the MSB is retained and
the converter moves on to "trying" the next most significant
bit, or approximately three-quarters full scale. If the input had
been less than the MSB, the logic would have turned the
MSB off before going on to the next most significant bit, or
one·quarter full scale. This "branching" continues until each
successively smaller bit has been tried, with the entire process
.
taking "n" trials.
To implement the logic for the successive approximation
algorithm, a configuration similar to Fig. 2 may be employed,
wherein a start command places a "one" in the first bit of a
shift register. This sets the first 'atch to "one" and turns on
the DAC's MSB. If the comparator output remains low, the
"one" will remain in the latch; if not, the latch will be reset
to zero before the next bit trial begins. The next clock cycle
causes the shift register to place a "one" in the second bit,
and a similar process continues till all bits have been tried.
After the last bit's trial, the end-of·conversion output changes
state indicating the parallel data is ready to be used.
END OF
CONVERSION
SERIAL
OUTPUT
MS.
COMPARATOR
Lsa
LS.
VOLTAGE OUTPUT DJA
FLOW DIAGRAM FOR 3 BIT SUCCESSIVE
APPROXIMATION AID CONVERSION
FIGURE 1
SUCCESSIVE APPROXIMATION AID CONVERTER
FIGURE 2
15·50
all bils swilched ON
INPUT
VOLTAGE
2.4 yLOGIC
INPUT
0.4 yIOAC_
OUTPUT -1/2 LS~
SETTLING + 112 LSB-
=
50 nsec/division
SETTLING TIME FIXTURE OF FIGURE 5
='
IFS·2mA RL 'IKIl
1/2 LSB • 41'A
OUTPUT SETTLING TIME
FIGURE 4
CURRENT COMPARISON AID INPUT
FIGURE 3
DAC CURRENT SETTLING TIME
CURRENT COMPARISON
The previous discussion indicated that the function of the
comparator was to perform a comparison between the analog
input voltage and the output voltage of the DAC. Higher
speed conversions may be achieved by using the output of a
fast current output DAC directly. This may be implemented
as shown in Fig. 3, where the comparator examines the 'polarity
of (VIN-IDACR IN ). Current comparison eliminates the need
for a current-to-voltage converting op amp which is by far
the slowest element in most DIA converters.
DYNAMIC CONSIDERATIONS
The time required to complete an 8 bit successive approximation
AID conversion is determined by the length of 8 trials and
their associated comparator decisions, plus one clock cycle.
To minimize these periods, three dynamic considerations
must be made:
1. DAC output current settling time to ±1/2LSB.
The DAC -08 is a low cost monolithic current output
DAC with 8Snsec full scale settling time and is ideal for use
in high speed AID converter designs. The internal logic switch
design enables propagation delays of 3Snsec for each of the
8 bits. Settling time of the LSB to within ±l/2LSB of final
value is therefore 3Snsec, with each successively more significant bit taking progressively longer. The MSB settles in
BSnsec; it is the dominant factor of full scale settling time.
This performance is illustrated in the scope photo of Fig. 4,
taken at the output of the test circuit of Fig. S.
A major factor affecting settling time is the RC time constant
formed by the load resistance (Rd and the DAC output
capacitance (Co) plus any stray capacitance present at the
summing {lode. Settling to within ±1/2LSB at 8 bits (±.2%
full scale) requires 6.2 RC time constants. For the DAC08, the output capacitance is 15pF; as a result the output RC
time constant is a major factor influencing settling time when
RL is greater than 500n and dominates when RL exceeds
gOon.
2. Comparator propagation delay with the available overdrive.
3. Logic propagation delay and setup time requirements.
For example, with a 500nsec DAC, a 500nsec comparator,
and lOOnsec of logic delay, each of these cycles would require
1.lJLsec. An 8 bit conversion would take g clock periods, or
lOJLsec. To design a fast AID, each of these delays must be
made as short as possible. In the next few paragraphs,
practical methods of minimizing these delays are discussed.
This ~ituation produces difficult requirements. Optimum DAC
settling time occurs when RL ~ soon, but for full scale
currents of 2mA, 1/2LSB is only 4JLA. Thus, with a soon
equivalent resistance, the voltage at the DAC output corresponding to 1/2LSB is only 2mV and is inadequate for high
speed operation of many comparators. For this reason, RL is
usually larger than soon, which is a necessary compromise
between DAC settling time and comparator input overdrive
requirements.
15-51
I
FOR TURN-ON, VL -2.7 V
FOR TURN-OFF, VL -0.7 V
VL
+.
For 2J.Lsec and 1J.Lsec designs, the AM686 was selected. It
provides 12nsec propagation delay with 2.5mV overdrive,
Schottky TTL outputs, and DC input specifications adequate
for an 8 bit AID. Ultra·high speed requires considerable
power. Maximum supply currents are 42mA from the +5V
supply and 34mA from the -5V supply.
V
"'.4 V
~VOUT
LOV
.I Il PRoa.:.r 0 V
veL 0---.-4---'
0.7 V
15KD
=-
-.4V
-ISV
"'I!1V
-15V
TO O.U.T.
SETTLING TIME MEASUREMENT
FIGURE 5
COMPARATOR CONSIDERATIONS
All comparators respond fastest to large differential input
voltages (high overdrive). This phenomenon is shown in Fig. 6,
a graph of response time vs. input voltage for the Precision
Monolithics' CMP·01. This low cost comparator provides
DC characteristics compatible with 10 and 12 bit AID
converters and has adequate speed for 4J.Lsec 8 bit converters.
3 IC LOW COST AID CONVERTER
FIGURE 7
LOGIC CONSIDERATIONS
A single DIP package, the AM2502 Successive Approximation
Register, contains the logic for 8 bit AID converters operating
at 2J.Lsec or greater conversion times. (Detailed descriptions
of AID's constructed with the AM2502 and Precision Mono·
lithics DAC's are contained in AN·11, available upon request.)
A 1J.Lsec AID requires special logic design using Schottky TTL
and will be described in the detailed circuit description.
PRACTICAL 3 IC AID'S
RESPONSE TIME FOR 100mV STEP
AND VARIOUS INPUT OVERDRIVES
FIGURE 6
When the required conversion time is ;;;. 2J..1sec, the DAC·OS's
fast settling time enables very simple and low cost designs.
A 4J..1sec design is shown in Fig. 7. At additional cost and
increased power dissipation, changing the comparator to an
AM686 results .in a 2J.Lsec AID. Every nanosecond counts in a
1J..1sec AID, and the circuit necessarily increases in complexity.
However, with the DAC·OS, Schottky TTL logic, and atten·
tion to layout, a 1J..1sec AID can be constructed at low cost.
15-52
""'"
INPI,IT
"
-ISV
NOTES:1.I,2,3.4,1,8SN74574N
25,65N745175N
19SN74$OOfi
4.IOSN74S04N
6. AIDAe-OIAl
1.A2A .. 686HC
8.·0PTlONAl..BYPASS
CAPACITORS
9. OPTIONAL SUMMOOE
BIASING RESISTOR
PROVIO£S+1/2LSBI4,.N
[NDOf
COfrI\lERSION
COMPLETE SCHEMATIC a-BIT,
FIGURE 10
11'58C
AID
CALIBRATION AND ACCURACY
ANALOG DESIGN
The DAC-08 AQ is useful in this design for several
reasons. Its output full scale current is guaranteed to be
1.992mA ±8jlA, when a 10.000V reference is connected to
a 5.000KU resistor in series with pin 14. In this design, the
5KU is split to allow bypassing without capacitively loading
the 10 volt source. For slightly higher speed, the total
resistance may be reduced to 2.5KU, thereby increasing 10
full scale to 3.984mA, allowing a lower sum node resistance
and lower RC time constant. (The DAC itself does not settle
faster at 4mA full scale current.) The DAC -08A maximum nonlinearity of ±0.1% full scale enables faster settling
time to within ±1/2LSB (±0.2% full scale) for each bit trial
than would be the case using a DAC with ±0.2% nonlinearity.
Using the ±0_2% nonlinearity DAC-08 or DAC-08E provides
cost savings at an overall increase in conversion time. Both
true and complementary current outputs are provided,
and their summation is always Ifull scale' In this design, 10 is
connected to the analog input. Since 10 + ~ is constant, and
10 flows in R3, the DC input current is constant. Holding the
AID input current constant reduces buffer amplifier output
impedance requirements. The buffer amplifier used in this
application must have sufficient bandwidth to hold V 1N
constant during a ljlsec AID conversion.
In many applications calibration is not required. With a
10.000V reference and ±0.05% tolerance resistors, the worst
case full scale error is ±0.15%. The zero scale error is totally
dependent upon comparator input offset voltage and input
bias current, and, in most cases, it may be tolerated. If the
errors are not tolerable, then the following calibration procedure may be used.
Calibration of the AID is done first at zero scale, then at full
scale. The zero transition is set by R4, a resistor connected to
the +10 volt reference. For 10V full scale, the desired
transition point between a code of 0000 0000 and 0000 0001
is at +20mV (+1/2LSB). With an ideal comparator, R4 would
be 2.56MU (10 volts/3.9jlA). Since comparators are less than
ideal, R4 must also cancel out the comparator's input offset
errors. With +20mV applied at the analog input and using a low
clock rate, select R4 to cause the output code to fluctuate
between 0000 0000 and 0000 0001. (Do not install a pot for
R2 or R4 since it will increase capacitance and inductance at
the sum node.) Full scale is calibrated by applying +9.940V
to the analog input and trimming' R2 until the output code
fluctuates between 1111 1110 and 11.11 1111. Alternatively, the reference voltage source may be adjusted for
the same effect. This will be a small adjustment due to the
DAC - 08A:s tight output full scale current relationship
with the reference voltage. Once calibrated, accuracy is a
function of temperature-induced drifts only.
15-53
I
177nsecr13MHz
INPUT
CP1
3
~
________________________________
~
Q
-
D
9
'
CP2
10A-_D______________________________________- I
*
DECISION
TIMING WAVEFORMS WITH ZERO VOLTS INPUT
FIGURE 9
A TYPICAL CONVERSION CYCLE
A conversion is initiated by a high level at the Start input
when the input 13MHz clock makes a low to high transition.
Approximately 9nsec later, the control logic generates a clear
and reset pulse (Strobe), which causes several events: the 8
output flip·flops are cleared except for the MSB flip-flop 1
which is set to a "one"; both shift registers are cleared; the
OAC has Bit 1 turned on, all others are off. The conditions
for the first trial at lJalf scale are now established.
As the OAC output settles, the comparator continuously
examines the polarity at its non·inverting input. For this
case, with zero volts at the· Analog Input, the comparator
finds a. negative voltage present; its output therefore is low.
lh.is low is applied to the "0" inputs of all 8 output flip-flops.
Recall that 74S74 flip-flop outputs won't change until they
are clocked by a positive transition at their' CP inputs. At the
time labeled 1 on the CPl waveform, the reset and clear
pulse, Strobe, returns high.
Shift Register No. 1 waits for a positive-going transition of
CP2. At 2 time CP2 goes high, transferring a "one" from
9A-0 to 9B-0; 9B-0 goes low, setting 2-0 high and clocking
the comparator's "zero" into the Bit 1 flip-flop. The other 6
flip-flops do nothing, because they are not clocked. Bit l's
answer is now latched, and Bit 2, 1/4 full scale, is being tried.
The process continues with the shift register causing each bit
to be tried from Bit 2 to Bit 8. After the Bit 8 decision, the
EOC output goes high, indicating that the answer in parallel
format is available at the 8 bit outputs.
OUTPUT INTERFACING
In continuous conversion operation, the most common con·
nection, EOC is connected to the Start input. While the
answer is available whenever EOC is high, it is convenient
to use the positive-going edge of the Strobe output as a clock
for two 745175 quad "0" flip-flops used as an 8 bit storage
latch. Since Strobe goes high before another conversion cycle
begins, there is ample setup time for the latch; the answer
has been steady for over 35nsec.
15-54
ANALOG
INPUT
+5V
o TO.IOVOLTS
SIMPLIFIED SCHEMATIC 1/lseC AID
FIGURE B
OVERAll DESIGN
lOGIC DESIGN
Due to the bit settling time range of theDAC-08 from
85nsec for Bit 1 to 35nsec for Bit 8, progressively decre'asing
trial-and-decision periods would be ideal. Practically, such a
timing sequence is difficult to generate at low cost, so a
compromise was made: The first four bits allow 160nsec
for each trial-and-decision, while the last four bits allow 80nsec.
This may be seen in the waveforms of Fig. 9. The timing
sequence is generated by shifting a "one" through two shift
registers with in-phase clocks, one at 6.5MHz derived from
the other at 13M Hz.
The primary logic design element is the 74S series positiveedge-triggered "0" flip-flop. This type of flip-flop is useful in
AID designs because of several properties:
1. The propagation delay from Set to Q going high is only
'3nsec.
2. The information on the D input is transferred to the
Q output only at a positive-going edge of CP.
3. Changes at the D input (comparator settling changes) are
ignored when CP is in a steady state.
74S74 dual "D" flip-flops are used for the 8 output latches
imd for the control logic, and 74S175 quad "0" flip-flops
are used for the two shift registers.
Standard 74 Schottky TTL logic was selected for speed,
compatibility with the AM686 comparator, ready availability,
and price.
A useful characteristic of the DAC-08 is its capability
to directly interface with all popular logic families including
TTL, CMOS, and ECL. For this design the DAC-08's
logic control pin (pin 1) is grounded to provide the proper
TTL logic threshold. A design utilizing ECl could provide
slightly faster conversion time at increased power consumption.
Flip-flops 2 through 8 in the simplified schematic (Fig. 8)
perform two functions. Typical operation can be understood
by examining the operation of flip-flop 2. When set by an
input from Shift Register No.1, the Q output of flip-flop
No.2 goes high, which starts the trial of bit 2 and acts as a
clock for flip-flop 1, transferring the comparator's output state,
which is the result of trial 1, to Q of flip-flop 1. This basic
connection, using the beginning of a new trial to clock the
previous bit trial, is used on all 8 output flip-flops. The start
of each bit trial is precisely coincident with clocking of the
previous bit answer; so no time is wasted, and logic delays
are reduced to setup times only.
15-55
I
745175
tt~~~o---
CLOCK
INPUT
START
C
-10
-10
CP
STROBE
-
20
20
10
20
BIT I
-'0
'0
40
EOC
-30
-
-
l-
e---
-
745175
-
r-
POWER
GROUND
BIT6
1
BIT 7
rO+
I
IO.OOOV
REFERENCE- REF'OI
~.
+
-0-
BIT 8
-15V
~3~~ty
>-~
>- '---CPr-
-'0
3D
-40
_40
JUMPER{
BIT 5
GRO
:---
ANALOG
GROUND
BIT 3
BIT4
-10
-115
-20
-215
-'"
-15 VOLTS
ANALOG
INPUT
BIT 2
40
40
+ ANALOG
- - - 0 _ INPUT
>-~
-5 VOL TS
REFERENCE IN
10'- I - 20
+5 VOLTS
40
GRO
OUTPUT REGISTER
(OPTIONAL)
I,..sec 'AlD
' - - -0+
-
SUPPLY
~~+5VOLT
-
AID CONVERTER
PO~~R
lOGIC
SUPPLY
FORCING FUNCTIONS
TYPICAL SYSTEM CONNECTION
FIGURE 11
PRINTED CIRCUIT BOARD LAYOUT RULES
SYSTEM CONSIDERATIONS
For AID designs generally, and high speed designs in particular,
layout is important. Some of the more important rules are
listed belcw:
Typical system connections are shown in Figure 11. Digital
grounds and analog grounds meet at one point only keeping
large power supply return currents away from the sensitive
analog ground portion of the A/D system. Start is connected to
EOC for continuous conversions, and Strobe is used to clock
the parallel answer into an output register at the end of each
conversion.
1. Digital ground must be separated from analog ground; they
must meet at only one common point.
2. Digital traces should not cross or be routed near .sensitive
analog areas; this is especially important near the sum node.
3. With Schottky TTL logic, the digital ground and Vee
traces should be large and contain provisions for generous
bypass'ng.
4. The trace from the DAC output to comparator input (sum
node) should be short, and it should be guarded by analog
ground.
5. All analog components should be located as close as possible
to the edge connector so that the input analog traces will
be short.
6. The comparator's outputs should be routed away from its
inputs, to minimize capacitive coupling and possible
oscillation.
CONCLUSION
The DAC-08 high speed monolithic D/A converter greatly
simplifies construction of high speed AID converters. Designs
using only three IC's achieve 2f..1sec and 4f..1sec conversions,
and 1f..1sec conversions can be attained with additional logic.
Techniques have been presented which allow the user to
construct low cost, high speed A/D converters.
15-56
PMI
Application Notes
AN-17
DAC-08 APPLICATIONS COLLECTION
by
John Schoeff & Donn Soderquist
There has been a trend in recent years toward providing totally
dedicated Digital-to-Analog Converters with limited applications versatility. This application note describes a new type of
monolithic DAC designed for an extremely broad range of
applications, the Precision Monolithics DAC-08.
Several unique design features of this low cost DAC combine
to provide total applications flexibility. Principal among them
are: dual complementary, true current outputs; universal logic
inputs capable of interfacing with any logic family; 85 nsec
settling time; high speed multiplying capability; and finally,
the ability to use any standard system power supply voltages.
A description of these features is given followed by specific
applications using each feature.
• CMOS, TTL, DTL, HTL, ECl, PMOS
COMPATIBLE 2pA LOGIC INPUTS
.85 NSEC SETTLING
TIME TO ± 112 LSB
• DUAL COMPLEMENTARY
OUTPUTS WITH
-IOV TO +18V
VOLTAGE
COMPLIANCE
• HIGH SPEED
MULTIPLYING
REFERENCE
INPUT
I
• ±4.5V TO ±18V • EXTERNAL
33 mW AT ± 5V
COMPENSATION
FOR MAXIMUM
BANDWIDTH
• ADJUSTABLE LOGIC
INPUT THRESHOLD
VTH=VLC+ 1.4V
THE FLEXIBLE D/A CONVERTER
15-57
OUTPUT
All bits ON
HIG,H VOLTAGE COMPLIANCE CURRENT OUTPUTS
TA=TmlnIDTma~
Many older current-output DAC's actually have resistive outputs which must be terminated in a virtual ground. The DAC08. however. is a true digitally-controlled current source with
an output impedance typically exceeding 20 megohms.
2,8
2.4
Its outputs can swing between -lOV and +18V with little or
no effect on full scale current or linearity. Some of the applications that require high output voltage compliance include:
I
1.6
IREF~2mA
V-=-5V.
V-~-15V.
2.0
I
I
2
1) Precise current transmission over long distances.
o. 8
2) Programmable current sources.
IREF-lmA-
i
I
I
0, 4
IREF~
3) Analog meter movement driving.
0
4) Resistive termination for a voltage output without an op
amp.
-14 -12
5) Capacitive termination for digitally-controlled integrators.
10
2
0
2:
4
6
-8 -6 -4 OUTPUT
VOLTAGE (volts!
O.2mA
I
e
10
12
14
16
OUTPUT CURRENT VS. OUTPUT VOLTAGE
(OUTPUT VOLTAGE COMPLIANCE I
6) Inductive termination with balanced transformers. transducers and headsets.
+10.000 V
10.000Kn
IO.aaOtHI.
IREF
IREF
=Z.OOOmA
14
=2'~!4
OAe-oe
.h
104
_
O
TO 2
EO
OAe-os
/
Bt 52 838485 86 B7 B8
FULL SCALE
FULL SCALE-LSB
I
1 I
I
1
1
1
1
1
I
lit
I t a
HALF SCALE+LSB 1 0 a 0 0 0
HALF SCALE
1 a 0 a 0 0
HALF SCALE -L58 0 , 1 1 1 ,
a
a
1
1
0
,
ZERO SCAlE+LSB 0 0 0 a 0 0 a I
ZERO SCALE
o 0 a 0 a a 0 0
lOrnA IOmA
En
1.992
.000 -9.960
,000
1.984
.008 -9.920
-.040
POS FULL SCALE
POS FULL SCALE-LSB
1.008 .984 -5.040 -4.920
1.000 .992 -5.000 -4.960
.992 1.000 -4.960 -5.000
.ooa
1.984
.000 1.992
81 82 83 84 B5 B6 B7 58
I I I I I I 1 1
I I I I I 1 I 0
ZEROSCALE+Lse I 0
ZERO SCALE
I 0
ZERO SCALE-Lse 0 I
-.040 -g.UO
.000 -9.960
NEG FULL SCALE+LSB o 0
NEG FULL SCALE
o 0
BASIC UNIPOLAR NEGATIVE OPERATION
o 0
o 0
1 I
I
o 0 0
0 0 0
0 0
0 0
I 1
EO
Eo
-9.920 +10.000
-9.S40 + 9.920
I
-O.OSO + 0.160
0.000 + 0·080
+0.080 0.000
0 0 I
0 0 0
+9.920 -9.840
+ 10.000 - 9.920
BASIC BIPOLAR OUTPUT OPERATION
pas FULL SCALE
POS FULL SCAl.E-LSB
I+) ZERO SCALE
H ZERO SCALE
81 B2 81S4B5 86 87 88
I I I I 1 I I 1
I 1 I I I I I 0
I 0
0 I
NEG FULL SCALE+LSB o 0
NEG FULL SCAlE
o 0
•
•
•
•
•
o 0
I 1
o 0 0
1 1 I
o 0 0
00 0
o 0
o 0
0
I
EO
+9.920
+9.840
+0.040
-0.040
-9.840
-9.920
PROVIDES ISOLATION fROM GROUND LOOPS
SYMMETRICAL :tIOV OUTPUT
USEfUL WITHIN SYSTEMS BETWEEN BOARDS
TRUE COMPLE.MENTARY IDlffERENTIAL CURRENT TRANSMISSION
HIGH SPEED ANALOG SIGNAL TRANSMISSION
HIGH NOISE IMMUNITY CURRENT
TO VOLTAGE CONVERSION
OUTPUT VOLTAGE COMPLIANCE VS. TEMPERATURE
15-58
18
DUAL COMPLEMENTARY OUTPUTS
Conventional DAC's have a single output, so they cannot drive
balanced loads and are limited to a single input code polarity.
The DAC-08 was designed to overcome these limitations
Input coding· of positive binary or complementary binary is
obtained by a choice of outputs, 10 for positive·true or
for
negative-true. In many applications both are used either
independently or in combination. Dual complementary outputs
allow some very unusual and useful DAC applications:
iQ
1) CRT display driving without transformers.
2) Differential transducer control systems.
3) Differential line driving.
4) High speed waveform generation.
5) Digitally controlled offset nulling of op amps.
TRUE AND COMPLEMENTARY OUTPUT OPERATION
+120VDC
• FULL OIFFERENTIAL DRIVE LOWERS POWER SUPPLY VOLTAGE
• ELIMINATES INVERTING AMPLIFIERS AND TRANSFORMERS
.,NDEPENDENT BEAM CENTERING CONTROLS
CRT DISPLAY DRIVER
_FULLY DIFfERENTIAL INPUT
• ELIMINATES INSTRUMENTATION
TRANSDUCER:
STRAIN
,. DIGITALLY CONTROLLED SYSTEM
AMPLIFIER - LOW COST
ZEROING
• HIGM CONVERSION SPEED
~RESSURE
• EXCELLENT COMMON MODE REJECTION
TEMPERATURE
OAe-os
SERIAL
INPUT
BRIDGE TRANSDUCER CONTROL SYSTEM WITH
FULL DIFFERENTIAL INPUT
15-59
PARALLEL OUTPUT
SERIAL
OUTPUT
I
OUTPUT
DUAL COMPLEMENTARY OUTPUTS
VREF
DIGITAL INPUT
DIGITAL INPUTS
256nA
V REF o-~vv--<>-i
• BIPOLAR OUTPUT WITH OFFSET BINARY COOING
• PROVIDES DC ISOLATION BETWEEN SOURCE AND LOAD
+t5V
• HIGH VOLTAGE OUTPUT CAPABILITY
• USEFUL WITH PUL.SE OR SINE WAVE REFERENCE INPUT
-15V
• USEFUL WITH PUlSE OR SINE FUNCTION OlGITAL INPUT
.OAe OUTPUT IS InA PER STEP
• REPLACES NULLING POTENTIOMETER
• WORKS WITH OP-07, OP-05, 555725
• Vas NULLED BELOW NOISE LEVEL
BALANCED TRANSFORMER DRIVE
DIGITALLY CONTROLLED
OFFSET NULLING
HIGH SPEED
1) 1!.Lsec, 2!.Lsec and 4!.Lsec A/D's. (These are completely
described in AN-16, available upon request)
Sub-microsecond settling times are common in current-output
DAC's. Many DAC's settle in 500 nsec; 300 nsec is not
unusual. But 85 nsec settling time for a low cost DAC is
exceptional, and this characteristic allows use of the DAC-08
in formerly difficult and expensive-to-build applications:
2) 15 MHz Tracking A/D's.
3) ECl compatible applications.
4) Video displays requiring a low-glitch DAC.
5) Radar pulse height analysis sytems.
all bits switched ON
fOliTURH-ON,YL"'Z.7V VL
FOil lURN-OFF,yt,'O,1 V
2.4
v-
0.4
v-
LOGIC
INPUT
+.4'1
'lOUT ""1-0'1
,.PflOBESOV
OUTPUT -112 LSBSETTLING
0+112 LSB-
-.4'1
."',
-.~v
lOD.U.T.
50 nsec/division
i FS = 2mA RL = 1K 11
112 LSB = 41'A
FULL SCALE SETTLING TIME
SETTLING TIME MEASUREMENT CIRCUIT
15-60
HIGH SPEED
OUTPUT
TYPE
SWITCH CONOmONS
{EOl
S(+I
UNIPOLAR POSITIVE
+
UNIPOLAR NEGATIVE
GND
SH
GNo
BIPOLAR tlOVFS
'0
...."·~iill
,
SERIAL
OUTPUT
.4.31211 6 5" J
I
1. BIPOLAR OUl
pur IS SYMMETRICAL
AROUND ZERO, ADJUSTABLE PEAK TO PEAK
AMPLITUDE.
START
2. FOR TRIANGLE WAVE, COUNT UP TO fULL, REVERSE AND COl/NT DOWN.
J. FOR POSITIVE-GOING SAWTOOTH, COUNT UP TO FULL, CLEAR, REPEAT.
CONVERSION
COMPLETE
TTL CLOCI( INPUT
2.25 MHZ
0------'
4. FOR NEGATIVE· GOING SAWTOOTH, COUNT DOWN, CLEAR, REPEAT.
~TEI.CONNECT·ST"RT·TO·C0t4VERSroN
COMPLETE" fOR CONTINUOUS CON~
5. FOR OTHER WAVEFORMS, USE A ROM PROGRAMMED WITH THE OESIRED fUNCTION.
VERSIONS.
6, S5n,ec SETTLING TIME PERMITS WAVEFORM PERIOD Of 25.6 ,.$e(, OR 39KHz
NeT[ 2. FOR" DETAILED LOW-COST DESIGNS
RfQUEST AN-II ANDAN-6.
REPETITION RATE
4 IC LOW COST AID CONVERTER
HIGH SPEED WAVEFORM GENERATOR
+5V
+ISV
ANALOG 0 TO + 10 V01. TS
INPUT
-15 Vo--~-j~---,
.IOV
REF-01 vof6!o-""'5...
'0C-_ _-l
monoDAC-08 AU
LSBo----_+------~~------_4--------_+----~~------_4--------_+--------_+--------,
I
SIMPLIFIED SCHEMATIC 11'sec AID
15-61
LOGIC INPUTS
ADJUSTABLE INPUT LOG.IC THRESHOLD
Most DAC's have TTL or CMOS compatible inputs which
require complicated interfaces for use with ECL, PMOS,
NMOS or HTL logic. By contrast, the DAC-OB, with typical
logic input current of 2j1.A and .an adjustable input logic
threshold, interfaces easily with any logic family in use today.
The logic input threshold is 1.4V positive with respect to
pin 1 ; for TTL pin 1 is therefore grounded; for other families
pin 1 is connec:ted as shown in the interfacing figure.
An adjustable threshold and a -10V to +lBV input range
greatly simplify system design especially with other-thanTTL logic:
1) ECL applications without level translators.
2) Direct interfaces with Hi-Z RAM outputs.
3) CMOS applications without static discharge considerations.
4) HTL or HNI L applications without level translators.
5) System size, weight, and cost reductions.
TTL,DTL
VTH = VLC +1.4 V
VTW+I_4V
+15 V CMOS, HTL, HNIL
VTW+7_6V
Eel
CMos. HTl. NMOS
V+
20""
13KSl
..A .......- - - {
..A .......- - . [
TO PIN 1
Vle
39""
TO PIN 1
20""
V Le
R3
-5.2V
INTERFACING WITH VARIOUS LOGIC FAMILIES
15-62
400pA
2.0
1.8
1.6
............
1.4
...... r---......
11.2
r--......
.
~f.O
.t"O.8
0.6
J'l.I1...
CMOS DATAINPD-r
0.4
o. 2
+50
50
TEMPERATURE,
CMOS DIFFERENTIAL LINE DRIVER/RECEIVER
+100
+150
"c
V TH - V LC VS. TEMPERATURE
2.4YBIT a
LOGIC INPUT
0.4 y-
ay-
a,.AlOUT
~ILse'61nA
,
I
01
I
I
IT--;
~
__L.J..J~ _~1
I
IF$. OUTPUT FULL SCALE CURRENT ImA)
50 nsec/divislon
LSB SWITCHING
LSB PROPAGATION DELAY VS. I FS
I I
I
I I
I I
IREF=2.0mA
6.0
81
1.0
0.8
4.0
0.6
82
0.4
2.0
II
83
I
o. 2
V-=-15V
o
\
12
I
10
(fiT
8.0 6.0 -4.0
84
85
2.0 0
2.0 4.0 6.0 8.0 10
LOGIC INPUT VOLTAGE (~olhl
12
14
16
o
18
-12 -10 -8.0 -6.0 -4.0 -2.0 0
2.0 4.0 60
ao
10
12
14
16
LOGIC INPUT VOLTAGE {vOlts)
NOTE: 81 THROUGH Be HAVE IDENTICAL TRANSFER CHARACTERISTICS.
BITS ARE FULLY SWITCHED, WITH LESS THAN 1/2 LSB ERROR, AT
LESS THAN ±100mV FROM ACTUAL THAESHOLD. THESE SWITCHING POINTS ARE GUARANTEEO TO LIE BETWEEN 0.8 AND 2.0
VOLTS OVER THE OPERATING TEMPERATURE RANGE ('''LC=O.OIl).
LOGIC INPUT CURRENT VS. INPUT VOLTAGE
BIT TRANSFER CHARACTERISTICS
15-63
18
REFERENCE INPUTS
MULTIPLYING CAPABILITY
Fixed internal references are included in many DAC's, but
they limit the user to non-mUltiplying, single polarity reference
applications and do not allow a single system reference. To
achieve the design goals of low cost and total applications
flexibility, the DAC·08 uses an external reference. Positive or
negative references may be applied over a wide common mode
voltage range. In addition, the full scale current is matched to
the reference current eliminating calibration in most applica·
tions.
1) Digitally controlled full scale calibration.
2) 8 x 8 multiplication of 2 digital words.
3) Digital Attenuators/Programmable gain amplifiers.
4) Modem transmitters to 1 MHz.
5) Remote shutdown and party line DAC applications.
MSEl
LSB
81 82 6:3 84 85 86 87 B8
-4-
J,.
RREF
-'0
DAe-OB
I"
R15
-VREF
NOTE I. RREF SETS IF$; Rl5 IS fOR
BIAS CURRENT CANCELLATION.
FOR FIXED REFERENCE, TTL
+
VREF
IFS:::: RREF
OPERATION, TYPICAL VALUES
ARE:
255
'·256
VREF~
10
10 +
~ IFS FOR ALL
LOGIC STATES
HO.OOOII
RREF : 5.00 OK
R,S ::::RREF
Cc":a.Ol,..F
"lC : 0 V (GROUND)
BASIC NEGATIVE REFERENCE OPERATION
BASIC POSITIVE REFERENCE OPERATION
All bo, ON
'.0
TA=TminlOTmax
4.0
V-=-15V
r-- r- ALL BlTS"HIGH"
1.0
/
/
V
1.0
/
2.8
~~ITFOR
TA=Tmin'OTmOJl
/
V
/
/
2.'
v-=
2.0
11-=-5 V
-15V
I
,.•
11+=+1511
I
'·V~J~~SR
0.81-+-+_-/__+_-t__+-_..!'RTE,-F'_,m_A
-t_--j
0.4~-I+--/--+--+--i--JF.0.2mA2.0
3.0
IREF, REFERENCE CURRENT {mAl
'.0
°_14
'.0
12 -10
e
6
-4
-2
0
2
4
6
8
10
12
14
V,5. REFERENCE COMMON tJODE VOLTAGE (volls)
NOTE: POSIT IVE COMMON MODE RANGE IS ALWAYS (V-+I-l.5 1/
REFERENCE AMP COMMON MODE RANGE
FULL SCALE CURRENT VS. REFERENCE CURRENT
15-64
16
18
• IREF
~
PEAK NEGATIVE SWING OF liN
• AC VOLTAGE TO DIFFERENTIAL CURRENT CONVERSION
.DC TO IMHz INPUT RANGE
• OUTPUT DRIVES TWISTED PAIR DIRECTLY
-CMOS COMPATIBLE
VIN~~
R!5 (OPTIONAL) 15
IMPEDANCE
e+vREF MUST BE ABOVE PEAK POSITIVE SWING OF "IN
ACCOMODATING BIPOLAR REFERENCES
MODEM TRANSMITTER
EO
"
10KA
•
•
•
•
FAST -8~ HSEC PLUS OP AMP SETTLING TIME
ANY LOGIC FAMILY FUR WORD "A" OR "8"
BIPOLAR OUTPUT
ELIMINATES $£VERAL LOGIC PACKAGES
2.R4-R5
;',EO OCTOZOKHZ-':l:5V
4.EO DCTOIOi - - -....
'
TA: _75°C
TA: +25°C
TA: +125°C
ITJ: 2000 K)
ITJ: 300"K)
ITJ: 4000 K)
48mV
72mV
96mV
VTEMp: 8.75 AV8E
420mV
630mV
840mV
V8E IQ2)
810mV
600mV
390mV
Vz ~ VBE + VTEMP
1.23V
1.23V
1.23V
5.00V
5.00V
5.00V
VOLTAGE
,
.1t.V SE ""
,----+---0 TEMP '" 83OnIV.
-¥
loge 16
+25·C
TCVTEMP '" 2,1111Vfc
VREF
~
1+
~
3.~64R4
4,06 Vz
"'
1.75KU
REF-02 SIMPLIFIED SCHEMATIC
FIGURE 4
TABLE IV
15-70
PMI
Application Notes
AN-19
DIFFERENTIAL AND MULTIPLYING DIGITAL TO ANALOG CONVERTER APPLICATIONS
by
John Schoeff and Donn Soderquist
INTRODUCTION
The introduction of low cost monolithic D/A converters has simplified data acquisition and control system design. This
application note describes several new applications using the multiplying capability and dual complementary current outputs
of the Precision Monolithics DAC-08.
THE UNIVERSAL DAC
• CMOS, TTL, OTL,
• 85 NSEC SETTLING
TIME TO + 1/2 LSB
HTL, Eel, PMOS
COMPATIBLE 2JlA
LOGIC INPUTS
• DUAL
COMPLEMENTARY
OUTPUTS WITH
o mA-
HIGH IMPEDANCE
• HIGH SPEED
AND -lOY TO +18V
VOLTAGE
COMPLIANCE
MULTIPLYING
REFERENCE
INPUT
t.O mA-
2.0 mA• EXTERNAL COMPENSATION
FOR MAXIMUM BANDWIDTH
• '4.SV TO :!c18V
33mWAT±5V
• ADJUSTABLE LOGIC
INPUT THRESHOLD
VTH"'V LC + 1.4V
(tlll'lll1)
(0000'0000)
F.IGURE 1
MULTIPLYING DAC BASICS
A multiplying DAC has an analog output which is the product of a digital input word and a reference voltage and can be
expressed as:
Al
A2 A3 A4 A5 A6
A7
A8]
+ - + - + - + - + - + + 2
4
8
16
32
64
128
256
For a current reference, current output DAC, the expression becomes:
1) 1 EO = EREF [ -
2)
10=IREF
[Al+A2+A3+A4+A5+A6+!-!....+A8]
2
4
8
16
32
64
128
256
The DAC-08 has complementary/differential current outputs, and 10 has a complement expressed as:
10 = IFS - 10 for all input logic states.
3)
The relationship of IREF to 10 and 10 is illustrated in Fig. 2 and in Fig. 3, the basic DC reference connections. References
may be either positive or negative, and a bipolar output voltage may be achieved using the high compliance current outputs
alone or with an output operational amplifier. The simplest form of a multiplying DAC accepts a unipola~ varying reference
input.
NEGATIVE REFERENCE CONNECTION
POSITIVE REFERENCE CONNECTION
+ VREF
255
RREF
x ill
'FS '"
'REF
+VREF
RREF
R"
MSB
LSB
81 B2 83 84 B5 B6 B7 B8
MSB
LSB
81 B2 8384 85 86 B7 88
V REF (+)
V,.
,.
'a + iQ =
OAe-OB
'a
ro .
+
'FS FOR All
LOGIC STATES
'FS FOR ALL
LOGIC STATES
V REF {-)
'5
R'5
V'5
R'5
+ V REF
V'5
FOR FIXED REFERENCE, TTL
OPERATION, TYPICAL VALUES
ARE:
- V REF = -10,OOOV
= +10.000V
RREF = 5.000KH
RREF = 5.000KU
R15 '" RREF
R15 "" RREF
C = O.01,.,.F
V LC = 0 v (GROUND)
c
Cc '" O.D1,.,.F
V LC '" 0
NOTE 1: RREF SETS IFS. R151S FOR BIAS CURRENT CANCELLATION
NOTE 2: PINS 14 AND 15 ARE OP AMP INPUTS,
so V14 '" V15.
v
(GROUND)
O.lIlF~
V-
NOTE 1: RREF SETS IFS. R15 IS FOR BIAS CURRENT CANCELLATION
NOTE 2: PINS 14 AND 15 ARE OP AMP INPUTS,
FIGURE 2
so V14 "" V15.
FIGURE 3
15-71
I
BIPOLAR REFERENCE CONNECTIONS
BIPOLAR REFERENCES
Operation with bipolar references is achielied by modulating
IREF as shown in Fig. 5. To aid in understanding bipolar
operation, see the equivalent circuit in Fig. 4. The reference
inputs of the DAC·08 are op amp inputs - VREF(+) being
the inverting input and VREF(-) being thenoninverting
input. Excellent gain linearity of the reference amplifier
allows multiplying operation over a range of IREF of 4f.1A
to 4mA with monotonic operation from less than 100f.1A
to 4mA.
LOW INPUT IMPEDANCE
MSB
LSB
B1 B2 83 B4 B5 B6 87
as
+VREF
RREF
v~
~
o----v-""'....---I
'REF;;;' PEAK NEGATIVE
DAC-08 EQUIVALENT CIRCUIT
SWING OF liN
O.l.uF~
I=-
v+
O.lpF
v-
HIGH INPUT IMPEDANCE
MSB
LSB
B1 B2 83 B4 B5 86 B7 sa
14
DAC-OO
FIGURE 4
0--""'v----115
R,5 (OPTIONAL) L-:3i----T--T-i--"
HIGH INPUT
REFERENCE AMPLIFIER COMPENSATION
IMPEDANCE
AC reference applications will require the reference amplifier
to be compensated using a capacitor from pin 16 to V-. The
value of this capacitor depends on the impedance presented
to pin 14: for R 1~ values of 1.0,2.5 and 5.0Kfl, minimum
values of Cc are 15, 37, and 75 pF. Larger values of R14
require proportionately increased values of Cc for proper
phase margin.
+VREF MUST BE ABOVE PEAK
POSITIVE SWING OF VIN
O.lIJF~
I-=-
v+
O.1IlF
v-
FIGURE 5
BIPOLAR DIGITAL TWO-QUADRANT MULTIPLICATION
ISYMMETRICAL OFFSET BINARY)
FAST PULSED OPERATION
For fastest multiplying response, low values of R14 enabling
small Cc values should be used. For R 14 = 1Kfl and Cc =
15pF, the reference amplifier slews at 4mA/f.1sec enabling
a transition from IREF = 0 to IREF = 2mA in 500nsec. If
R14 or the parallel equivalent resistance at pin 14 is less
than 200fl, no compensation capacitor is necessary, and a
full scale transition requires only 160nsec.
MSB
LSB
5.0Kn
5.000Kn
VREFo----"'VV----j
o TO +10V
5.0KH
TWO-QUADRANT MULTIPLICATION
There are two forms of two-quadrant multiplication: bipolar
digital,. where the digital input word controls output polarity,
and bipolar analog, where the analog reference input controls
output polarity.
IF RL
= RL WITHIN
±.05%, OUTPUT IS SYMMETRICAL ABOUT
GROUND
lOrnA
IQrnA
Eo(V)
0
1.992
1.984
.000
.008
+9.96
+9.88
0
1
1.000
.992
.992
1.000
+.040
1
0
.008
.000
1.984
1.992
-9.88
81 82 83 84 85 86 B7 88
Bipolar digital two-quadrant multiplication is shown in Fig.
6 with the output polarity being controlled by an offsetbinary-coded digital input word.
Bipolar analog two-quadrant multiplication is shown in Fig.
7. A bipolar reference voltage is connected to the upper
DAC-08 and modulates the reference current by ±1.0mA
around a quiescent current of 1.1 mAo The lower DAC-08
also has a reference current of 1.1 mA; due to the parallel
digital inputs, the lower DAC-08 effectively subtracts out
the quiescent 1.1 mA of the upper DAC-08's reference
15-72
POS. FULL SCALE
POS. FULL SCALE -LSB
\+) ZERO SCALE
(-) ZERO SCALE
NEG. FULL SCALE +LSB
NEG. FULL SCALE
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
0
0
0
1
-.040
-9.96
FIGURE 6
current at all input codes, since the voltage across R3 varies
between -10V and OV. Thus, the output voltage, EO, is a
product of a digital inputword and a bipolar analog reference
voltage.
BIPOLAR ANALOG TWO-QUADRANT MULTIPLICATION
(DC-COUPLED DIGITAL ATTENUATOR)
FOUR-QUADRANT MUL TIPL YING DAC
WITH HIGH IMPEDANCE INPUT
L'\. __ +lDV
-= "
-lDV
"
'0
'----+---1+"
• ADJUSTABLE lOGIC THRESHOLD
MULTIPLICATION AC INPUT
• HIGH IMPEDANCE DIFFERENTIAL INPUTS
• 'lOV DIFFERENTIAL INPUT RANGE
CONTRQLSOUTPUT POLARITY. +1SV
• 2 PACKAGESVS. 3 FOR VOLTAGE SWITCHED QAe'S
PERFORMS 2 QUAORANT
• WIDE POWER SUPPLY RANGE
FIGURE B
FIGURE 7
FOUR-QUADRANT MU L TIPLICA TION
Four-quadrant multiplication combines the two forms of
two-quadrant multiplication. Output analog polarity is con·
trolled by either the analog input reference or by the offset
binary digital input word. One implementation of this
function with the DAC-08 is shown in Fiy. 8 with output
current values listed in Table l.
Operation of the four-quadrant mul\iplier may be more
easily visualized by considering that if either VIN = OV or
the offset binary digital input code is at midscale (corresponding to zero), then a change in the other input will not
affect the output. Zero multiplied by any number equals
zero.
The four-quadrant multiplying DAC circuit shown accepts
a differential voltage input and produces a differential
current output. An output op amp is not shown because it
is not always required; many applications are more suited
for high output compliance (-1OV to +18V) differential
current outputs. Typical balanced loads include transformers, transducers, transmission lines, bridges and servos.
A common mode cu rrent will be present at the output and
must be accommodated by the balanced load. A pair of
matched resistors may be used at the outputs to shunt most
of the common mode current to ground, thus reducing the
common mode voltage swing at the output.
I
TABLE I - FOUR-QUADRANT MULTIPLYING CURRENT VALUES IN FIGURE 8
DIGITAL
INPUT
V IN (+)
V IN (-)
VIN
DIFF.
IREF
#1 (rnA)
IREF
#2 (rnA)
10#1
10#2
(rnA)
11111111
+5V
-5V
+10V
2.000
1.000
1.992
1000 0000
+5V
-5V
+10V
2.000
1.000
1.000
0111 1111
+5V
-5V
+10V
2.000
1.000
0.992
0000 0000
+5V
-5V
+10V
2.000
1.000
0
10#2
10#1
(rnA)
101
(rnA)
(rnA)
(rnA)
102
(rnA)
0
1.992
0.996
0
0.996
0.996 rnA
1.496
0.500
1.492
0.004 rnA
0.500
1.492
0.496
1.000
1.496
-0.004 rnA
0.996
0.996
1.992
1.992
-0.996 rnA
0.000 rnA
0.496
0
0.992
lOUT
DIFF.
11111111
OV
OV
OV
1.500
1.500
1.494
1.494
1.494
0
1.494
1000 0000
-10V
-10V
OV
2.500
2.500
1.250
1.240
2.490
1.250
1.240
2.490
0.000 rnA
0111 1111
+10V
+10V
OV
0.500
0.500
0.248
0.250
0.498
0.248
0.250
0.498
0.000 rnA
0000 0000
OV
OV
OV
1.S00
1.500
1.494
1.494
1.494
1.494
0.000 rnA
11111111
-SV
+5V
-10V
1.000
2.000
0.996
0
0.996
1.992
1.992
-0.996 inA
1000 0000
-5V
+5V
-10V
1.000
2.000
0.500
0.992
1.492
1.000
0.496
1.496
-0.004 rnA
0111 1111
-5V
+5V
-10V
1.000
2.000
0.496
1.000
1.496
0.992
0.500
1.492
0.004 rnA
0000 0000
-SV
+5V
-10V
1.000
2.000
0
1.992
1.992
0.996
0.996
0.996 rnA
0
15-73
0
0
0
a
FOUR-QUADRANT MULTIPL YING DAC WITH
EXTENDABLE INPUT RANGE AND HIGHEST SPEED
FOUR-QUADRANT MULTIPLYING
DAC TRANSFER FUNCTION
DIFFERENTIAL
CURRENT OUT f+)
1mA
",---~.::.....--o ..,
OA.e-OB
DIFFERENTIAL
V REF ~ +10V
"
,/---.....-+=----01>,
IOUT~ '01- 102
DIGITAL
DIGITAL
INPUT H t-+++-I-++'t-++H~+'t-++H-++'t-+-H INPUT (+J
DODO 0000
1111 1111
".
'0
DAC·OB
"
1mA
DIFFERENTIAL
• 250U RESISTORS AND OMISSION OF COMPENSATION CAPACITORS
ARE OPTIONAL FOR FAST PULSED REFERENCE OPERATION
• INPUT DIFFERENTIAL AND COMMON MODE RANGES ARE EXTENDABLE
BV INCAEA .. ING 10K!! RESISTORS. EXAMPLE" lOOK!! FOR lOOV
CURRENT OUT H
• HIGH SPEED MULTIPLYING CONNECTION WITH MONOTONIC
FIGURE 9
FIGURE 10
HIGHEST SPEED FOUR-QUADRANT
MULTIPLYING CONSIDERATIONS
AC-COUPLED MULTIPLICATION
The configuration shown in Fig_ 10 makes use of the
DAC-08's ability to operate in a fast pulsed reference mode
without compensation capacitors. This technique provides
lowest full scale transition times. An internal clamp allows
quick recovery of the reference amplifier from a cutoff
(IREF = 0) condition. This connection yields a reference
slew rate of 16mA/j.Lsec which is relatively independent of
RIN and VIN values.
Input resistances are not limited to 10Kn. For example,
100Kn resistors for RIN1 and RIN2 allow ±100V reference
voltage inputs making this connection especially useful in
high common mode voltage environments. Except for different reference treatment, operation and digital input
coding are identical in the circuits shown in Fig. 8 and in
Fig. 10; both have the transfer function shown in Fig. 9.
Some multiplying DAC applications are more easily achieved
with AC coupling. At the same time, a high impedance input
is often required to avoid loading a relatively high source
impedance. Both requirements are met by the circuits shown
in Fig. 11 and Fig. 12 which use the compensation capacitor terminal (C c ) as an input. This is possible because
Cc is the base of a transistor whose emitter is one diode
drop (0.7V) away from the R-2R ladder network common
baseline internal to the DAC-08.
With a full scale input code the output, Va. is flat to
>200KHz and is 3d8 down at approximately 1.0MHz
making this type of multiplying connection useful even
beyond the audio frequency range. Such a connection is
illustrated in Fig. 12 operating at 455KHz, the highest
recommended operating frequency in this connection.
HIGH INPUT IMPEDANCE AC-COUPLED MULTIPLICATION
(AUDIO FREQUENCY DIGITAL ATTENUATOR)
HIGH INPUT IMPEDANCE AC-COUPLED MULTIPLICATION
II.F. AMPLIFIER/DIGITAL ATTENUATOR)
+lSV
CAe-os
OAe-OB
~
w~SlOAO
...."",y
TRANSFORMER
!r
=
~ o"",
o.",
V ,n 2Vp-p
Vin = 1.05V rms
(MAX)
• OffSET BINARY COOING ALLOWS PHASE INVERSION
OR TWO-QUADRANT MULTIPLICATION
• 85 NSEC SETTLING TIME FOR DIGITAL INPUT CHANGE
• LOW DISTORTION AND HIGH SPEED
• GREATER THAN 40dB DYNAMIC RANGE
• 2.0M1! TYPICAl. INPUT IMPEDANCE
FIGURE 11
FIGURE 12
. 15-74
DIFFERENTIAL AND RATIOMETRIC AID CONVERSION
more specific applications.
These are extremely cost-effective designs due to their low
parts count and simplicity. Alternative designs performing
identical functions require instrumentation amplifiers for
the differential-to-single-ended input signal conditioning and
analog multipliers or dividers for the arithmetic functions.
Complementary/differential current-source outputs and
multiplying capability allow the DAC-OB to be used in
differential and ratiometric A/D converter designs directly
without signal conditioning amplifiers. This group of applications begins with the basic differential A/D converter
and ratiometric A/D converter connections followed by
DIFFERENTIAL INPUT AID CONVERSION BASIC CONNECTIONS
o
A. 0 CONVERSION
lOGIC
• DtFFERENTIAlllllPUT RANGE 5V WITH 5V COMMON MODE VOLTAGE RANGE
• USE 5K!! INPUT RESISTORS FOR DIFFERENTIAL INPUT RANGE OF lOV WITH
OV COMMON MODE VOLTAGE RANGE
• USE OP·04 OR OP 14 DUAL MATCHED OP AMPS CONNECTED AS VOLTAGE
FIGURE 13
DIFFERENTIAL AID CONVERSION
IC's: a REF-01 +10V reference, a 2502-type successive
approximation register, a CMP-01 precision voltage comparator, and a DAC-OB. As shown, the circuit converts an
analog input in less than 2.0Msec. For lower speed requirements, the A/D conversion logic can be the tracking or
servo type consisting of up/down counters.
The circuit in Fig. 13 uses the high voltage compliance
current output capability of the DAC-08 and the high
common mode voltage rejection of the CMP-01 to construct
a differential input ADC without input signal conditioning.
A successive approximation ADC is constructed with four
FOUR-QUADRANT RATIOMETRIC AID CONVERSION BASIC CONNECTIONS
INPUT
V
,
0--
=t
(REF-Ol)
INPUT
V
~
""L "".
l
I>K:,
OOV
~~,
"tJ:
,r--
5K!!
Icr
f
':>CAe·OB
'0
'"
III
j
""~
l_.-
I
!)K:!
~
COMPARATOR
V
D MD CONV'."ON
lOGIC
MSB
I
LSB
-
--~
CAe-OB
"'~
'0
~~G;:~; ,c'
11
v,
Vy
• HIGH $PEEOWITH FULL ACCURACV OVER ENTIRE DYN AMIC RANaE
•
5V DIFFERENTIAL INPUT$WITH
'sv COMMON MODE
R
• DlOOE5ARE 11114148',
~
FIGURE 14
FOUR QUADRANT RATIOMETRIC AID CONVERSION
Ratiometric A/D conversion with fully differential X and Y inputs is accomplished with the circuit in Fig. 14. Here, one set of
inputs, VX' is connected in a manner similar to the circuit in Fig. 13, and the other set of inputs, Vy, is connected in
a multiplying fashion. Operation is as follows: IREF for both the upper and the lower DAC-OB is modulated between 1mA and
3mA; and the resulting output currents are different;ally transformed into voltages by the 5KQ resistors at the comparator's
inputs and· compare' with the Vx differential input. When the conversion process is complete (comparator inputs differentially
nulled to less than 1/2 LSBi a digital output is available which corresponds to the quotient of VXIVy. Thus, four-quadrant
ratiometric AID conversion is achieved with four IC's and without instrumentation amplifiers.
15-75
BRIDGE TRANSDUCER NULL
In many control systems, bridges must be nulled, and a
digital representation of the bridge's error must be provided
for computer monitoring and control. The circuit in
Fig. 15 accomplishes both tasks by using the DAC-08
complementary /differential current outputs to null the
bridge with the DAC-08 connected in a tracking differential
A/D converter configuration. The REF-02 reference voltage
source provides both the bridge excitation voltage and the
positive reference voltage for the DAC-08. Some of the
advantages of this circuit are listed at the bottom of Fig. 15.
BRIDGE TRANSDUCER NULL
Y+'5V
+
+5.ooov
I
+JRREF
'0-
K
~-<
BRIDGE
SUPPLY
IREF-021
OAe-OB
. -'1
~
~!
B'
OIGiTAL
OUTPUT
l
• CORRECTION CURRENT TRACKS BRIDGE SUPPLY SO NULL IS MAINTAINED
• DIGITAL OUTPUT INDICATES PREVIOUS NULLING ERROR
• CIRCUIT CAN ALSO MEASURE BRIDGE AESPONSE TO INPUT VARIABLE - PROCESSOR
CAN COMPUT E DIFFERENCE WITH RESPECT TO ZERO ERROR
• NDOPERATI ONAL. AMPLIFIERS OR SUMMING RESISTORS ARE REQUIRED
• HIGH NOISE I MMUNITY LOGIC COMPATIBILITY (HTI.. CMOS)
-
+
UP/DOWN
COUNTER
(8 BITS)
1----0
CLOCK
COMPARATOR
FIGURE 15
POWER MONITOR
Another differential current-input ADC is shown in Fig. 16
with a transformer-coupled input. An up/down counter, a
precision high speed comparator, and the DAC-08 form a
tracking A/D converter which continuously monitors the
analog input. Two precautions must be observed: the
common mode voltage at the comparator's inputs must not
exceed ±10V; and the differential voltage must not exceed
11V. Voltage-limiting resistors at the comparator's inputs
are recommended.
POWER FAULT MONITOR AND DETECTOR
ACPOWER
+15V
lOKi!
+
REF-O'
+10V
OAe-OB
...
.r-
rr
':> IOvl7IO
/--
~
MAX
~
III
UP/DOWN
COUNTER
1
• DETECTS ANO DIGITIZES SPIKES AND FAULT CONDITIONS
• TRACKING AID CONVERTER UPDATE RATE: 200 NSEC (5 MHz MAXI
• RESOLUTION FOR 400 Hz AT MAX CLOCK 150.028 DEGREES
~ ~ 80~.
5);106
10-6 =80 PPM = 0.008% = 0.028 DEGREES
FIGURE 16
15-76
DIGITAL
OUTPUT
~
ALGEBRAIC DIGITAL COMPUTATION
Frequently, a di.gital arithmetic operation (addition, subtraction, miJltiplication, or division) must be performed,
and an analog output must be provided. Traditionally, the
arithmetic operations are performed with several IC's, and
the output drives a D/A converter. This section describes
applications of the DAC-OB as an arithmetic building block,
new design approaches that reduce the number of packages
required in many applications. Today's low cost, versatile
DAC's merit a designer's consideration as arithmetic
elements.
input words can be CMOS, TTL, DTL, NMOS, or MECL,
because the DAC-OB interfaces with all of those logic
families. In fact, the two input words may even be from
different logic families to eliminate special level translators
or interface circuitry. (See AN-17, "DAC-OB Applications
Collection.")
The first arithmetic application is shown in Fig. 17. Two
DAC-OB's perform a fast algebraiC summation with a direct
analog output_ The circuit works by paralleling the outputs
of two DAC-OB's and summing their currents while driving a
baianced'ioad. The output is the algebraic sum of word "A"
and word "8" in all four quadrants.
One benefit is not immediately apparent and deserves
special mention. In a.l1 of these applications, the digital
FOUR·QUADRANT ALGEBRAIC DIGITAL COMPUTATION
5K!1
RREf-F_ _ _ _ _---.
2.SKIl
01 FFERENTIAL CURRENT
OUTPUT '01 - '02
'"
DAC-OB
"
DIGITAL
!A1 INPUT
'OUT'" 'O'-'02
m
l(!(A] + (Sll
J(.~::: AN~ "A" ANO "S"
ARE POSITIVE OR NEGATIVE
OFFSET BINARY DIGITAL WORDS
'0
[BJ
DIGITAL
INPUT
WORD
WORD "A"
WORD "B"
11111111
1100 0000
1000 0001
1000 0000
0111 1111
0111 1110
0011 1111
0000 0000
1111
1100
0111
0111
1000
1000
0011
0000
1111
0000
1111
1111
0000
0000
1111
0000
101
102
EOUT
3.984mA
0
O.984mA
+9,96V
3.000mA
2.oo0mA
1.992mA
1.992mA
1.984mA
0.984mA
0
1.984mA
1.992mA
1.992mA
2.000mA
3.000mA
3.984mA
+5.04V
ffi.04V
0
0
-0.04V
-5.04V
-9.96V
FIGURE 17
FOUR-QUADRANT DIGITAL MULTIPLICATION
High speed multiplication of two B-bit digital words with
an analog output usually requ ires several logic packages and
a D/A converter. The circuit in Fig. 1B performs this
function using only threeIC's.
analog reference inputs to DAC-OB number 1 and number 2.
Those reference inputs are determined by digital input word
"A." The circuit's output, 101-102, is a differential current
output which may be used to drive a balanced load.
In Fig. 1B DAC-OB number 1 and number 2 are connected
as previously shown, and DAC-OB number 3 provides the
Four-quadrant multiplication is thus performed by adding
one more DAC-OB to the basic four-quadrant multiplying
connection.
FOUR-QUADRANT 8 BIT X 8 BIT DIGITAL MULTIPLIER
?
VREf
t+
""
DOl
Cc
;;;
.1"'' ,r--
DAC-OB
"
r-;-c
=
N~C
~5K"
cAC-OB
"
+
'j
/
=
-
-
-0'
rOBAlANCED
lOAD
,02
' OUT- 101 -'02
--
F~
II
~,=ll JLlli
,AI
DIGITAL
INPUT
WORD
II
181
+
DIGITAL
INPUT
DAC-08
250!!
WORD
=
"
r-- Cc
6NOC
FIGURE 18
15-77
r
'0I
. HIGH speeD MONO TONICPPERATION OVER THE ENTIRE DVNAMIC RANGE.
• FOR HIGHEST MUL TlPlVING SPEED USE 250!1 RESISTORS AND NO
COMPENSATION AS SHOWN. lTHIS ALSO LOWERS THE RC PRODUCT AT
DAe 08 3 OUTPUTS)
I
OTHER DAC APPLICATIONS
The combination of high voltage compliance complementary current outputs, universal logic inputs, and multiplying capability
in I low cost DAC enables widespread application_ Consider the following partial list:
AID CONVERTERS
Tracking (Servo)
Successive Approximation
Ramp (Staircase)
Microprocessor Controlled
Ratiometric (Bridge Balancing)
GRAPHICS AND DISPLAYS
Polar to Rectangular Conversion
CRT Character Generation
Chart Recorder Driver
CRT Display Driver
DATA TRANSMISSION
Modem Transmitter
Differential Line Driver
Party Line MiJltiplexing of Analog Signals
Multi-level 2-Wire Data Transmission
Secure Communications (Constant Power Dissipation)
TEST SYSTEMS
Transistor Tester (Force IB and IC)
Resistor Matching (Use both outputs)
Programmable Power Supplies
Programmable Pulse Generators
Programmable Current Source
Function Generators (ROM Drive)
CONTROL SYSTEMS
Reference Level Generator for Setpoint Controllers
Positive Peak Detector
Negative Peak Detector
Disc Drive Head Positioner
Microfilm Head Positioner
ARITHMETIC OPERATIONS
Analog Division by a Digital Word
Analog Quotient of Two Digital Words
Analog Product of Two Digital Words-Squaring
Addition and Subtraction with Analog Output
Magnitude Comparison of Two Digital Words
Digital Quotient of Two Analog Variables
Arithmetic Operations with Words from Different Logic
Families
AUDIO SYSTEMS
Digital AVC and Reverberation
Music Distribution
Organ Tone Generator
Audio Tracking AID
CONCLUSION
Differential and multiplying applications have been described
which use the high voltage compliance, complementary
current outputs and the high speed multiplying inputs of
the Precision Monolithics DAC'()S_
2) "Low Cost, High Speed Analog-to-Digital Conversion
With the DAC-OS"
By Donn Soderquist and John Schqeff
Precision Monolithics Application Note #AN-16, 1975
BIBLIOGRAPHY
1) "DAC-OS Applications Collection"
By John Schoeff and Donn Soderquist
Precision Monolithics Application Note #AN-. 17 , 1975
3) "Differential and Multiplying Use of Digital-to-Analog
Converters"
By Donn Soderquist and John Schoeff
E.E_ Times article, June 21,1976, pp. 40·47
15·78
PMI
Application Notes
AN-20
EXPONENTIAL DIGITALLY CONTROLLED OSCILLATOR USING DAC-76
by
Donn Soderquist
Here is a 4-IC, microprocessor-controlled oscillator with a 8159 to 1 frequency range covering 2.5Hz to 20KHz. An exponential,
current output IC DAC functioning as a programmable current source alternately charges and discharges a capacitor between
precisely·controlled upper and lower limits. This circuit. features instantaneous frequency change, operates with -t5V ±1 V and
-15V ±3V supplies, and provides monotonic frequency changes over a 78dB range - the dynamic range of a 13-bit DAC.
BASIC OPERATION
Connected as shown in Fig. 1, the output of the exponential
DAC is an 8-chord (or segment) current ranging between
250nA and 2.0mA. The three most signif.icant bits select 1 of
8 binarily-related chords; and the five least significant bits
select 1 of 32 linear steps within each chord. This current is
switched between the 10 (+) output and the 10 H output under
the control of a pin labeled SB.
When SB is low, 10H is selected, and the. DAC's output
current drives a current mirror which ramps the timing
capacitor in a positive direction until an upper limit of OV is
sensed by A2. At this time the set-reset flip-flop (Ll) is set,
SB becomes a "1", and the DAC's output Gl.ment is switched
to the 10 (+) output. Now the capacitor is charged to a lower
limit of -5V, the flip-flop is reset, and the cycle repeats itself.
REFERENCE SETUP
The multiplying relationship between the reference current,
IR E F' and the full scale output of the DAC is 3.863. IR E F is
set by the voltage between V+ and the lower limit divided by
R1+R2. This is so because pin 12, VREFH, is a high impedance input, namely the non inverting input of an op amp
internal to the DAC. Since both IR EF and the upper and
lower limits are derived by dividing down the power supply
voltages, operation (frequency of oscillation) is independent
of power supply changes. (See Appendix 1 for a complete
derivation of the timing formula.)
+5V (V+)
CURRENT
MIRROR
'REF
<>oSODJ,lA
+
10Ka
R3
"'
DIGITAL INPUTS
~
10Kn
UL
10Kfl
R4
I
10H
STEP
r---.....--<....-o OUT
R2
16Kn
'0(+)
+-
"
VREF
1""'0
OAC-76CX
A1
--',2
IOE(-~1-'-'-_ _ _-'
10Kn
r-------{) OUT
R5
-15V
-+5V
UPPER LIMIT ""'OV
10Kn
R6
-15V(V-)
LOWER LIMIT ""-5V
'ALL 10Kn RESISTORS ARE PART OF 14-PIN
DIP NETWORl< BOURNS#4114R-001-103S
O.Ol/lf
Ic ......--...~OV~
T
":"
I+- ----i
fA~
E
-5V
T
15-79
~
=
(Rl+R2) C
tA~ 3.863 • where
.. NORMALIZED DIGITAL INPUT
-I5V
'Kn
:!:1%
+5V (V+)
CURRENT
MIRROR
...._ _ _ _ _--.
10Kfl:
R3
+
R'
10Kn
UL
10Kfl:
R4
IREF
""500~A
DIGITAL INPUTS
-I5V
10(-)
~
STEP
UL
r - -....- .....--o OUT
R2
10Kn
+-
"
1-0
L L t - -_ _ _--4-~~~'~2
10Kfl:
r--....----o 0iIT
R6
-15V
UPPER LIMIT ""OV
+5V
10Kfl:
R6
LOWER LIMIT ""-5V
O.Ol~F
*ALL 10Kfl: RESISTORS ARE PART O"F 14-PIN
DIP NETWORK BOURNS#4114R-OOH03S
-15V(V-)
Ic +---...~OV~
":"
I+- -+I
T fAi·
E
-5V
T
CHORI;)
(SEG·
ME NT)
OUTPUT
FREOUENCY
20KH'U
00000001
6
o 1/8
DIGITAL
INPUT
CODE
0
00001000
5
2 34
3/8
5/8
7/8 FS
NORMALIZED
DIGITAL
INPUT !Al
00011111
00100000
1
00111111
WAVEFORMS
01000000
L '0 1-1
ION
+' +
0 (+1
ON
2
01011111
'01-1 +'O'+J
ON
--.J
01100000
ONI
3
OV
01111111
RAMP
-5V
10000000
4
10011111
OUT
10100000
5
10111111
OUT
11000000
"A"
"B"
r
'1
:J
NORMAL·
IZED
DIGITAL
INPUT
OUTPUT
FRE·
QUENCY
AVERAGE
STEP
SIZE
{A}
"1
5 KHz
2.5KHZ 01
NORMALIZEO DIGITALINPUT
TABLE I
IDEAL OUTPUT FREQUENCY
OSCILLATOR TRANSFER FUNCTION
10 KHz
T = (Rl.+R2) C
.. _-tAl, 3.863 . w, ..., ..
6
11011111
11100000
7
I
11111111
15-80
1
8159
8
8159
2.45Hz
19.6Hz
-2.L
76.0Hz
8159
33
8159
95
8159
99
8159
223
8159
231
8159
479
8159
495
8159
991
8159
1023
8159
2015
8159
2079
8159
4063
8159
4191
8159
80.9Hz
4.8Hz
233Hz
243Hz
9.5Hz
--
8159
8159
2.3Hz
547Hz
566Hz
19Hz
1.17KHz
1.21KHz
38Hz
2.43KHz
2.51 KHz
76Hz
4.94KHz
5.09KHz
152Hz
9.96KHz
10.3KHz
303Hz
=
FS
20.0KHz
FREQUENCY SELECTION
CONCLUSION
Table I lists ideal output frequencies at the lowest and highest
codes of each chord and the average change in frequency
produced by a one step change (LSB change) within each
chord. For highest accuracy in Chord 0, especially between
2.5Hz and 19.6Hz, comparators with low input current are
recommended. The CMP-02CY comparators typically have
35nA of input current; at the lowest code point (00000001)
the OAC output is 250nA; so low input current comparators
are essential for best operation. Above 000 01000 (41lA or
19.6Hz) the comparator input currents become less critical.
A microprocessor-controlled oscillator has been shown wh ich
achieves a 13-bit dynamic range with only 8 bits of control.
Monotonic frequency steps over 2.5Hz to 20KHz are provided
in a 4-IC low cost design.
REFERENCE
"Eight-Bit Frequency Source Suited for IlP Control" by
Albert Helfrick, EON, September 20, 1976, pp. 116-118.
APPENDIX
TIMING EQUATION DERIVATIONS
One of the best features of this design is its insensitivity to power supply changes. The equation derivations are shown to explain
how V+ and V- drop out as timing determinations.
With a constant current drive tr.e charge on C changes linearly over a range (E) between an upper limit (UL) and a lower limit (LL)
dependent upon the OAC's digital input code, the OAC's output current, and the value of the timing capacitor (C).
Eq. 1)
Eq.21
Eq.3)
T=
2(C~)
where: C = timing capacitor value
Substituting 4 into 8:
E = upper limit - lower limit
I = OAC output current, 10 (+)
or 10 (-)
T = period
E = UL - LL where: UL = upper limit
LL = lower limit
R4+R5+R6
UL = R3+R4+R5+R6
[
(V+) - (V-)
_ (V "'") -
I
Eq.9)
REF -
Rl +R2
(V+)-(V-)
2(R1+R2)
1+(V-)
Substituting 9 and 7 into 6:
V+ = positive power supply and V" = negative
power supply
but:
R3=R4=R5=R6
3(V+)+(V-)
:. UL =
4
(V+) - (V-)
where:
Eq.4)
LL = R5+R6
R3+R4+R5+R6
[ (V+HV-)
T
Eq. 10) 2C
4
nV+) - (V-)l
3.863 {A} [2(R1+R2)J
Multiplying by {A} 3.863:
1+(V-)
(V+)-(V-)
E . 11) {A} 3.863T
q
2C
LL = (V+)+(V-)
2
Substituting 3 and 4 into 2 and solving for E:
Eq.5)
~
~
(V+)2+ (V-)
4
(V+)-(V-)
2(Rl+R2)
r~13.863T = Rl + R2
2C
2
E= (V+HV-)
4
So, V+ and V- have dropped out as timing considerations.
Rewriting Eq. 1 and substituting 5:
(V+) - (V-)
4
T
Eq.6)
2C
Solving for T:
but: C = O.OlIlF
Rl=R2=10K.Il
The expression for I is:
Eq.71
1=3.863{A}IREF
Finally, the simplified expressions:
where:
3.863 is a constant derived from the ratio of
IREF to IFULL SCALE of the OAC
A = the normalized digital input code
IREF = the reference current
Eq. 14) T ='
~t~}~
Eq.15) f (frequency) ='
Eq.8)
(V+) - LL
IREF= Rl+R2
~
50X 10-6
15-81
=' 20KHz full scale
I
PMI
Application Notes
AN-21
3 IC 8 BIT BINARY DIGITAL TO PROCESS
CURRENT CONVERTER WITH 4 - 20MA OUTPUT
by
Donn Soderquist
This application note describes a 3 IC, 4 - 20mA process current,digital to analog converter that can be constructed for less than
$20 at current 100+ prices. It operates from a -5V ±lV negative power supply and a +23V ±7V positive power supply, has 24V
output voltage compliance, and occupies less than 4 square inches of printed circuit board space. Other significant features include
TTL logic input compatibility, B-bit binary coding, 0 0 to +700 C operation, and 5ILsec full scale settling time into a 500n load.
a current of 0 to 2mA (depending on .the digital input code)
will flow into the DAC's output, pin 4.
THEORY OF OPERATION
A fixed current of 0.5mA is added to a DAC's output current
varying between 0 and 2.0mA and ttJe resulting total current is
multiplied by a factor of B to produce an output current of
4.0 to 20mA.
Both the DAC's output current and the fixed 0.5mA flow in
R5, a BOOn precision resistor. The voltage developed by that
current is applied to the noninverting input of the other Y:. of
A3 and will also appear across R6, a lOon precision resistor.
Thus, B times the 0.5 to 2.5mA current in R5 flows in R6, or
4 to 20m A. Almost all of this current appears at the output
because the 2N6053 is a high hF E device, a power darlington
transistor.
In the schematic, first note the REF-01 CJ, a +10V adjustable
reference. Its output goes to the noninverting input of Y:.
of A3, a dual precision op amp. The inverting input is within a
feedback loop forcing +10V to appear at the top of R4, a
20Kn resistor; a 0.5mA current will flow in R4 through Q1, a
high hF E transistor. The same +10V is applied to R3, the
reference input resistor of a multiplying IC D/A converter, the
DAC-OB. Full scale output current of the DAC will be the
difference in voltage between ti)e +10V reference and pin 14
of the DAC divided by R3; pin 15 will be at the same voltage
as pin 14 because it is a high impedance point, the non inverting input of an op amp internal to the DAC. After calibration
Some other components need explanation. C1 provides
frequency compensation of the DAC's reference amplifier; C2
and C3 are power supply decoupling (bypass) capacitors; C4
prevents high frequency oscillations. D1 through D4 insure at
least 2.5V differential between the op amp's inputs and its
positive power supply under all conditions. R 1 and R2 are
zero scale and full scale adjustments respectively.
Vcc +1$V TO +3OV
.,
REF-01C.1
'''''"
,,,n
"'ZE.O
AD""T
TIC
OLGITAL
INPUTS
.,
..."
FULL
:~:ir~---;
OUTPUT VOLTAGE
CPMPLIANCE [VOCI
Vcc
"oe
23V
11\1
,W
'SETTLINGTIME '" 5IA_
WITHR L "5000
..
,"
15-82
CALIBRATION PROCEDURE
Apply +23V ±7V and -5V ±1 V to the converter with a
current· measuring meter connected between the output and
ground. Make the digital inputs all zeros, < +O.BV. Adjust Rl
until the output current is 4.0mA. Now change the digital
inputs to all ones, > +2.0V. Adjust R2 until the output
current is 20mA Calibration is now completed.
OUTPUT VOLTAGE COMPLIANCE
Output voltage compliance is Vcc -6V. For example, at
Vcc = +16V, the output may go to a maximum of +10V
without affecting output current. Thus, a 500n resistor would
be the maximum load resistor at Vcc = +16V. At Vcc = +30V,
Voc = 24V, and RL Max = L2Kn.
change R6 to 40n; this makes the mUltiplying factor 20
instead of B. For 1-5mA, replace the 2N6053 with a 2N5087,
and change R6 to 400n.
CONCLUSION
A simple, low cost process current converter has been shown
with wide application in the controls industry. The design is
tolerant of wide power supply variations, has high voltage
compliance, and is easily calibrated. Reliability and cost are
optimized by using only 3 integrated circuits, the Precision
Monolithics DAC-OB, REF-Ol, and OP-14, plus a few readily
available discrete components.
SCALE MODIFICATION,
REFERENCE
Although the values shown are for the more common 4-20mA
requirement, operation at 1-5mA or 10-50mA may be
achieved by changing some components. For 10-50mA,
Crowley, B., "Circuit Converts Voltages to 4-20mA For
Industrial Control Loops," Electronic Design, Jan. 5, 1976,
p. 116.
PARTS LIST
Circuit
Symbol(s)
Al
A2
A3
Cl-C3
C4
Dl-D4
01
02
Rl-R2
R3
R4
R5
R6
Description
+10V Reference, PMI REF-01CJ
B Bit DAC, PMI DAC-OBCO
Dual Op Amp, PMI OP-14CJ
O.lJ.1F +BO%I-20%50V, Type CK-l04
100pF ±5% Mica, DM10ED101J03
Power Diode, 1 N400 1
NPN Transistor, 2N3904
PNP Power Darlington, Motorola 2N6053
50Kn Potentiometer, Bourns #3006P-1-503
4020n ±1%, RN55C4021 F
20Kn ±1%, RN55C2002F
BOOn±O.l%, GR :/ISE16DBOO
lOOn ±0.1%, GR :/ISE16Dl00
I
15-83
PMI
Application Notes
AN-22
SOFTWARE CONTROLLED ANALOG TO DIGITAL CONVERSION USING DAC-08
AND THE 8080A MICROPROCESSOR
by
Will Ritmanich and Wes Freeman
The microprocessor is generally regarded as a flexible replacement for discrete logic devices. Yet most microprocessor·based
designs still use numerous isolation and support packages for analog to digital (A/D) conversion, rather than using just software
and the processor itself. There are many applications where the minimum system approach is both desirable and feasible. This
application note describes a very simple, low cost method of software controlled 8·bit A/D conversion using the Precision Mono·
lithics DAC·08 and the Intel 8080A. Innovative software eliminates the need for peripheral isolation devices. Easily expandable
to 10·bit or l2·bit A/D conversions, the technique may be emulated using other microprocessors having separate address and data
busses.
8080A I/O INTERFACE CONSIDERATIONS
In order to communicate with any input/output peripheral
device, the 8080A must be able to distinguish between its
normal memory array and that particular I/O peripheral. Two
techniques exist for accomplishing this, each with its own set
of advantages and disadvantages.
The basic approach, used especially in large systems requiring
greater than 32K memory, assigns the particular peripheral to
an I/O "Port." This has the effect of isolating the I/O from the
memory bus by the use of additional interface devices (gener·
ally the 8255 Programmable Peripheral Interface). Data trans·
fers to and from the peripheral are then enabled by special
instructions IN or OUT. This method has the advantage of
allowing full 65K memory usage (Figure 1), but requires
additional support circuits. Although conceptually simple, it
restricts communication to the peripheral through the 8080A
Accumulator.
I/O CONTROL USING MEMORY MAPPING
The convention used in establishing memory mapped I/O is to
assign address line A15 as the I/O control flag. Thus, if A15 is
"zero," then memory is active, and if A15 is "one" then I/O
is active. This creates a "map" of the memory as shown in
Figure 2. Although other address lines could be used for the
function, A15 is normally used because it is easier to control
with software and allows full address capability for the lower
32K of memory.
32K
MEMORY
65K
MEMORY
MAPPED
I/O
o
256
B
MEMORY MAPPED I/O
FIGURE2
For simple applications or where the full memory addressing
capability of the 8080A is not needed, a powerful technique reo
ferred to as "Memory·mapped I/O" can be implemented. By
utilizing unused portions of memory address space for I/O
operations, the full instruction set used to control memory
can also be used to operate on peripherals. This creates a
powerful "new" capability for .dealing with I/O. The major
constraint, however, is that the peripheral must now conform
to memory bus signals and timing.
MEMORY MAPPED I/O CONTROL SIGNALS
In order to manipulate memory·mapped I/O, it is necessary
to generate the appropriate control signals. This is accomplished
by gating MEMR and MEMW with A15 as shown in Figure 3.
System bus characteristics are preserved and all instructions
normally used to operate on memory can now be used on I/O
as well.
1/0 CONTROL SIGNAL GENERATION
r-------~P------------.----------MEMR
}
10------....-----+--------- MEMw
65K
MEMORY
ISOLATED 110
o
256
TO
MEMORY
DEVICES
8228
B
SYSTEM CONTROL
I/ORIMM'}
TO
MEMORY
MAPf'EO
I/O
DEVIces
IIOW!MM)
'"
FIGURE 3
FIGURE 1
15-84
At the start of a conversion, the most significant bit (MSB) of
the DAC is turned on by the Successive Approximation Register
(SAR) producing an output from the DAC equal to one·half
full scale. The DAC's output is compared to the analog input
by a comparator, and if the DAC output is greater than the
unknown input voltage, the MSB is turned off. If, however, the
DAC output is less than the unknown input, the MSB is
allowed to remain on, and the next most significant bit is
tried. Whether or not this second bit should remain on or be
turned off is subject to the same criteria as before (Figure 6).
This basic procedure is used to test all remaining DAC bit
inputs.
SUCCESSIVE APPROXIMATION AID CONVERSION
Because it provides the best tradeoff between speed and
hardware/software complexity, the successive approximation
method of A/D conversion has been selected. Figure 4 shows a
simple analogy of this .approach based on the use of a pan
balance.
SUCCESSIVE APPROXIMATIONS ANALOGY
UNKNOWN
WEIGHT
FULL
SCALE
-2-
FLOW DIAGRAM FOR 3 BIT SUCCESSIVE APPROXIMATION
AID CONVERSION
FULL
DCS
FULL
SCALE
-8-
FULL
SCALE
c::J
c=::::::::r
NO
000
16
etc.
BINARILV WEIGHTED COUNTERWEIGHTS
FIGURE 4
To measure some unknown weight, it is placed on one pan of
the balance. By successively applying binarily-weighted counterweights to the other pan until the scale is balanced, we can
ascertain the portion of the unknown weight compared to
that of the known full scale weight. The number of "trials" is
made equal to the number of counterweights available by
starting with the heaviest counterweight first, and either
retaining it or rejecting it based on the comparison to the
unknown. This process is repeated for the next heaviest and
so on, until all weights have been tried.
FIGURE 6
Electric~lIy, this can be simulated by sequential comparisons
between the output of a digital to analog converter and some
unknown analog input. Figure 5 shows the basic circuit
configuration.
LOGIC REPLACEMENT BY THE 8080A
The circuit illustrated in Figure 5 can be simplified by
utilizing the logic capability of the 8080A to replace the SAR.
The eight lowest order address bits control the data bit inputs
to the DAC-08 (Figure 7). Table 1 contains the software used
to accomplish this. Figure 8 depicts the corresponding flow
diagram.
BASIC SUCCESSIVE APPROXIMATION CIRCUIT
I
SUCCESSIVE APPROXIMATION REGISTER
S~
C~
AN
INPALOG
~
~+
.v
SHIFT REGISTER
BIT
BIT
1
2
. BIT
n-1"
BIT
",,"
,DAC 08 AID CONVEIiSHJN ROUTINE
I-ENDDF
ENCODE
START'
SERIAL
DATA
INPUT
~
LATCHES
TEST'
MS
COMPARATOR
LSB
MaB
VDAC
LSB
TOOHI:
VOLTAGE OUTPUT D/A
LXI
MOV
MOV
ORA
MOV
HOV
ANA
JPO
i'iOV
ORA
MOV
MOV
IlAIi
MOV
JNC
END
P.08000H
A.F
H.A
C
L.A
A.M
A
TOOHI
A.I"
C
C.A
A.F
B.A
TE:ST
ILOAD MSF IN ~.CLEAR C
JMSE TO ACC
15r.T MDVMAP 110
,ADD LAST TEST VALUE
,MOVE PRESENt TEST TO L
,GET COMP OUTPUT
, s n FLAGS
,DISCARD PRESENT TEST HT
IGET PRESENT TEST EIT
I ADD TOTAL SO F·AIl
'SAVE TOTAL
,Gn LAST TEST EI1
,ROTATE TOWARD LSP
,SAVE NEW TEST FI T
,JUMP IF N01· FINISH
,FINAL VALUE IS IN C
TABLE 1
FIGURE5
15-85
A"
ANALOG
-15V
+15V
INpUT
OTO+l0V
+10.000 V
I
5KH
r~
,.
"
8080
3.9
3
.
13
14
15
56789101112
lKH
:dJll
,2, ;;;
-=1-
-ft
t+ .
3 _
'0
DAC-08E
5KIl
~
...
--<
•
CMP01C
1
'='":'
'
-15V
":"
B4
}lP
""
..
0,
87
"
.,
0,
~
..
8228
SVSTEM CONTROL
4.71<
1/3
74LS12
W.
I
"0
OS'N
OS'N
"0---------7
"'0
DO
...
or-'
-\.
MEMR
••71(
?
q
FIGURE 7
This technique accesses the DAC as a 256 X 1 ROM. Conversion
time, hardware interface, and program length are minimized
due to the fast settling time of the DAC-08 and CMP-Ol
combination, which is less than the processor cycle time
(Figure 9). No ~'wait" states or (NaP) instructions are required
for execution of the program.
SOFTWARE CONTROLLED AID CONVERSION
The instruction (MOV L, A) moves the test value to the "L"
(memory address) register, which controls the 8 lowest order
address bits, establishing the trial bit value to the DAC. The
applied analog input current is compared to theDAC output
current by the CMP-01. The (MOV A, M) instruction gates
the trial comparison results provided by the CMP-Ol into the
8080A Accumulator. The processor then continues to perform
the logical operations required to accomplish the analog to
digital conversion. It requires 21 bytes of memory with an
8-bit conversion time ranging from 235 to 285 J.lsec using a
2.0 MHZ clock. The time varies slightly depending on the
analog input, because extra program steps are required if the
trial bit must be saved. Quantizing is performed over an analog
input range of 0 to +10 volts, although other user-selected
encoding ranges can also be used.
EXPANSION
This technique may also be used for AID conversions of 10 or
12 bits by simply connecting the DAC MSB inputs to the
corresponding address lines. The hardware and software savings
show a very marked increase because multiple latches and
extensive software byte moving operations are eliminated.
Thus, for a 10-bit AID conversion, the DAC "appears" to the
8080A as a 1024 X 1 ROM; a 12-bit DAC "appears" as a
4096 X 1 ROM. In general, the settling time of a 10-bit or
12-bit DAC is greater than the cycle time of the 8080A;
however, by using the 8080A READY line to insert "wait"
states, the settling time of any' DAC can be accommodated.
FIGURES
15-86
1/3
DAC-08 /8080A SETTLING TIMES
Ev
2V
0
I
I
-
I
!::'iii
-
nl
Ii
I,
-
I
A15
2ND TRACE:
DAC-08
PIN 4
3RD TRACE:
CMP-01
OUTPUT
t.."I!!
-
.:\"
~
TOP TRACE:
.
11
,
~ V
:r.III
. ...
SV
BOTTOM
TRACE:
·11· .
10!ll nS
I
74LS12
OUTPUT
FIGURE9
CONCLUSION
BIBLIOGRAPHY
A low cost AID conversion technique using DAC-08 and the
8080A microprocessor has been presented. Implementation
requires a. minimal allocation of memory for program software
and very few interface components. The technique permits
expansion to control 10-bit or 12-bit AID conversions.
1.)
"8080 Microcomputer Systems Users Manual," Intel
Corporation 9n5.
2:)
"AID Conversion Systems: Let your IlP do the Working"
by Don Aldridge, EDN, 515n6, pp 75-80.
3.)
"Low Cost, High Speed Analog to Digital Conversion
with the DAC-08," Precision Monolithics Application
Note AN-16.
I
15-87
PMI
Application Notes
AN-23
DIGITAL-TO-ANALOG CONVERTER GENERATES HYPERBOLIC FUNCTIONS
by
Will Ritmanich, Bob Blair, and Bob Debowey
Measurement and control systems frequently require fine resolution around a setpoint with wide dynamic ranging capability. This
can be satisfied by systems designs which use a high resolution, strictly linear approach; but this is costly and often unnecessary.
Nonlinear function fitting using multiplying digital-to-analog converters (DAC's) offers a desirable alternative by being both simpler
and more cost-effective. This application note describes how extended range hyperbolic functions of the type A/X or -A/X (where
"A" indicates an analog constant, while "X" represents a decimally-expressed digital divisor) are easily generated by just two lowcost I.C.'s; an operational amplifier and a mUltiplying DAC. Circuit configurations are provided for each polarity output along with
dynamic performance photographs and general design guidelines for either pinary or BCD-coded divisors. At current prices (100+)
the configurations shown can be built for less than $10.
THEORY OF OPERATION (A/X)
Figure 1a shows the A/X function circuit which uses a two-digit BCD-coded DAC, the DAC-20EX, and a decompensated, widebandwidth op-amp, the Op·17. A constant current, I constant, equal to the value of one least significant bit (LSB), flows into the
DAC output terminal, 10 , Simultaneous adjustment of the scale factor and output amplifier offset voltage is enabled by a multiturn, low tempco potentiometer, R5, which adjusts current -I R producing voltage -VR across R2. The LSB value (scale factor)
equals -VR/R 1.
Zener diode, DZ, provides a stable reference voltage source. Because feedback for the op amp is through the DAC, capacitors Cl and
C2 are added to provide proper phase compensation. Reference resistor R3 is determined by the scale factor and the maximum current allowed into the DAC reference input VR+. Bias current compensation for the DAC reference amplifier is accomplished by R4.
Figures lb, lc, and ld show dynamic performance of circuit la when the digital inputs are swept by an external BCD up-counter
with codes of 0000 0001 through 1001 1001 (division by zero is not allowed).
THEORY OF OPERATION (-A/X)
The circuit configuration for the -A/X function is shown in figure 2a. It is quite similar to that of figure 1a with both the DAC
reference amplifier and output amplifier terminals reversed. Capacitors Cl and C2 provide phase compensation. Figures 2b, 2c, and
2d show dynamic performarice of circuit 2a.
DESIGN CONSIDERATIONS
1)
Circuit speed and settling time are dictated by output op amp slew rate, scale factor, and compensation. Use of slower amplifiers considerably increases the illustrated settling times. Effective slew rate of circuit la is 3V//1s, while circuit 2a slews
0.6V //1s.
2)
Layout and breadboarding of high gain, wide-bandwidth devices necessitates considerable care with a ground plane with single
point grounding being highly desirable. Decoupling capacitors located close to the devices' supply inputs are essential.
3)
Accuracy of the circuit is within 1% over the O°C to +70°C temperature range with 1% metal film resistors Rl, R2 and R3.
DAC linearity becomes an important factor as the divisor decreases; for this reason 1/4 LSB linear DAC's are recommended.
4)
Binary coding may be accomplished by subsituting an B-bit binary-coded DAC-OBEX for the two-digit BCD-coded DAC20EX. In addition to adjusting circuit values however, a higher performance op amp such as theOP-17F is desirable because
the output amplifier's input offset voltage drift becomes a more significant error source for overall scale factor stability over
temperature. This is due to the increased resolution of the binary coding.
15-88
A/X FUNCTION GENERATOR
"X" DIVISOR
DIGITAL INPUTS
/
80
40
20
10
8
4
2
+15V
1
R3
3.4BKQ
H,,~_1_4... VR+
+VOUT
6
DAC·20EX
1--.---<.-.;.;15'-1 VRCl
10pF
V3
V+
13
-IR~
R5
10K!;
BOURNS
3006 P-l·l03
C2
47pF
D2
IN957A
6.BV
~.Ol,uF
-15V
I
\J
Rl. R2. R3 = 1% METAL FILM
ALL CAPS = CERAMIC DISC
FIGURE 1.
GROUND
PLANE
A/X FUNCTION GENERATOR
Iconstant ~ LSB value ~
-VR
R,
where XFS ~ decimal equivalent
of full scale counts
and Xdiv ~ decimal equivalent
of desired divisor
Iconstant· R3· XFS
VOUT'" --""'X""d-j-v---
I
TOP TRACE
~
CLOCK
LOWER TRACE
~
4- THRU 16
(CODES 0000 0001
THRU 00010000)
TOP TRACE
~
CLOCK
LOWER TRACE
~ ~ THRU ~
(CODES 0000 0011
THRU 0010 0010)
15-89
TOP TRACE ~ CLOCK
LOWER TRACE
~~
(CODES 0000 0001
THRU 1001 1001)
THRU
~
- A/X FUNCTION GENERATOR
"X" DIVISOR
DIGITAL INPUTS
I
80
40
5
R3
B1
3.4BKD
20
6
7
10
8
tI
4
2
+15V
1
B2 B3 B4 B5
ICONSTANT
VR+
-VOUT
DAC·20EX
H,,~
___15...
VR~
R4
3.6KD
V3
V+
13
-IR~
02
IN957A
C2
R5
10KD
BOURNS
3006 P-1·103
100pF ~
6.8V
~O.l.uF
C1
22pF
-15V
I
'\l
R1, R2, R3 = 1% METAL FILM
ALL CAPS = CERAMIC DISC
FIGURE 2.
GROUND
PLANE
-A/X FUNCTION GENERATOR
Iconstant ~ LSB value ~
-VR
R1
where XFS ~ decimal equivalent
of full scale counts
and Xdiv ~ decimal equivalent
of desired divisor
A"" Iconstant' R3' XFS
VOUT""
Iconstant' R3' XFS
FIGURE 2c
LOWER TRACE
TOP TRACE
~
~
CLOCK
- : TH RU
(CODES 0000 0001
THRU 0001 0000)
LOWER TRACE
~~
~
CLOCK
A
TOP TRACE ~ -3
(CODES 0000 0011
THRU 0010 0000)
-A
THRU 20
FIGURE 2d
LOWER TRACE
TOP TRACE
~
~
CLOCK
-: THRU
~~
(CODES 0000 0001
THRU 1001 1001)
SUMMARY
-"Simple, low cost circuits which generate the hyperbolic functions A/X and -A/X have been presented, together with design guide·
lines for either binary or BCD·coded divisors.
15-90
PMI
Application Notes
AN-24
THE OP·17, OP·16, OP·15 AS OUTPUT AMPLIFIERS FOR
HIGH SPEED D/A CONVERTERS
by George Erdi
This application note shows how to make high speed, voltage output D/A converters using the DAC·08 and OP-15/16/17 precision
bifet op amps. Designs are optimized for highest speed (OP-l7), lowest drift (OP-16) and for lowest power (OP-15). Although the
DAC-08 is used as an example, the same configurations work with DAC-20 and DAC-76.
Converting the current output of a fast IC DAC to a voltage
while maintaining fast settling time is difficult. The full scale
current of the DAC-08 settles in 85nsec. It can be terminated
with a load resistance, as shown in Figure 1, to give a 10V output. However, in this configuration the settling time will be
dominated by the RC time constant of R 1 and the DAC-08's
output capacitance (T=R 1cO=5Kn X 15pF = 75nsec). It
requires 6.2 time constants to settle within 0.2% of full scale
(112 least significant bit of an 8 bit converter). Therefore, the
settling time is 500nsec including the DAC-08's 35nsec propagation delay.
Due to this RC time constant, current to voltage conversion is
usually accomplished with a transimpedance amplifier as shown
in Figure 2. The output's response is now limited by the amplifier's slew rate and settling time. However, an additional pole
is introduced at __1_ , where C 1 is the sum of the DAC's
2nR2C1
output capacitance and the op amp's input capacitance. The
frequency of this pole is likely to be at an inopportune
location for fast amplifiers, creating an underdamped response
or even oscillation.
DIGITAL
INPUTS
V REF
MSB
LSB
-T'----.---a Vo = 0 to -10V
R,
5KH
V+
V-
I
FIGURE 1
DAc-oa WITH RESISTIVE TERMINATION
SETTLING TIME = 500 nsec FOR 0 TO -10V
DIGITAL
INPUTS
V REF
MSB
LSB
Vo =Oto+l0V
V+
FIGURE2
VOLTAGE OUTPUT DAC WITH TRANSIMPEDANCE AMPLIFIER
15-91
VREF
DIGITAL
INPUTS
MSB
LSB
VO =Oto+10V
FIGURE 3
VOLTAGE OUTPUT DAC WITH RESPONSE SHAPING
The circuit of Figure 3 resolves this problem. It can be shown that if R1Cl ~ R2C2, the effect of the two capacitors is completely
cancelled, and the overall settling will be determined by the amplifier's behavior only. In addition, C2 can be varied to fine tune the
system's response and minimize settling time to compensate for the op amp's possibly underdamped or overdamped characteristics.
The disadvantage of this circuit compared to that of Figure 2 is that ali input errors, and in particular input offset voltage (Vos), are
amplified by the factor (1 +
:~).
+10V
DIGITAL
INPUTS
MSB
1.25KS2
R2 5KSl
C2
SpF
5KS2
RREF
-+
V REF (+)
6
DAC·OSE
15
I
Vo =Oto+10V
VREFH
VALUES SHOWN ARE FOR OP-17. REFER
TO TABLE I FOR OP-15 AND OP-16 VALUES.
+15V
-15V
FIGURE4
o TO +10V CONNECTION, SETTLING TIME = 380nsec
The optimum speed is obtained - at low cost - by using the Op·17, fast, precision, BIFET-input op amp,stable only at closed-loop
gains of five or more. Therefore, the R 1/R 2 ratio is set at four (Figure 4). Settling time to 0.2% is 380nsec with all bits turning on
(0 to 10V), or all bits turning off (10V to 0). The last 2.5 volts of the rising wave-form are shown in the photograph of Figure 5.
The three grades of the OP-17 are specified at Vos~0.5mV max (OP-17E), 1.0mV max (OP-17F), and 3.0mV max (OP-17G). Even
though Vos is multiplied five times its effect is still less than 0.2% or 20m V . The OP-17E's contribution will be only 1/4 LSB even
on a 10 bit system, The offset voltage can also be trimmed to zero, then the TCVos' at 2 to 4/-lVtC, typicallY,wili be the limiting
factor. The complementary output of the DAC-08 can be used for a -10V to +10V system as depicted in Figure 6. Settling time
is only slightly increased because of the time required to slew the additional ten volts. Since 1/2 LSB is now 40mV, the non-slew
portion is decreased by 70nsec.
15-92
The OP·16 is slower than the OP·17 but it is stable in unity
gain. Therefore, improved output·referred error can be traded
off for increased settling time. The OP·15 is a lower power
dissipation model, but again this improvement is obtained at the
expense of settling time. Table I summarizes the resistor and
capacitor values for the various amplifiers in the circuits of
Figure 4 and Figure 6, the settling times obtained in these cir·
cuits, and the output-referred offset errors.
FIGURE 5
SETTLING TIME OF FIGURE 4 CIRCUIT USING OP-17
+10V
1.25K!l
DIGITAL
INPUTS
MSB
R2
5Kl!
.....___c..:2,
8pF
6
1S
Vo = ±10V
+1SV
-=-
-1SV
NOTE: VALUES SHOWN ARE FOR OP-17. REFER
TO TABLE I FOR OP-15 AND OP-16 VALUES.
FIGURE 6
,10V CONNECTION, SETTLING TIME = 450nsoc
TABLE I
OP·17/16/15 PERFORMANCE AS OUTPUT OP AMP FOR DAC.QB
OP·17
o to 10V
Fig. 4
OP·16
-10 to +10V
Fig.6
Oto 10V
Fig. 4
OP·1S
-10 to +10V
Fig. 6
Oto 10V
Fig. 4
-10 to +10V
Fig. 6
R1
1.2SKU
1.2SKU
10KU
10KU
10KU
10KU
R2
SKU
SKU
SKU
SKU
SKU
SKU
R3
-
C2
8pF
8pF
2SpF
40pF
30pF
50pF
Settling time to ±0.2%
380nsec
4S0nsec
750nsec
1100nsec
900nsec
13S0nsec
Slew Time
1S0n5ec
290nsec
400nsec
800nsec
S90n5ec
1170n5ec
20mV
40mV
20mV
40mV
20mV
40mV
S
S
1.S
1.S
1.S
1.S
2.SmV
S.OmV
lS.0mV
2.SmV
5.0mV
lS.0mV
0.7SmV
1.5mV
4.SmV
0.7SmV
1.SmV
4.SmV
0.7SmV
1.SmV
4.SmV
0.7SmV
1.5mV
4.5mV
7mA
7mA
7mA
7mA
4mA
4mA
1/2 LSB
= 0.2%
Closed Loop Gain
-
1KU
-
3.3KU
3.3KU
Offset Error at Output
EGrade MAX
F Grade MAX
G Grade MAX
SUPPLY CURRENT MAX
15-93
I
I
NUMERICAL INDEX
ORDERING INFORMATION,
Q.A. PROGRAMI
INDUSTRY CROSS REFERENCE
FUNCTIONAL REPLACEMENT GUIDE
I
OPERATIONAL AMPLIF IERS
I
I
I
I
I
I
COMPARATORS
MATCHED TRANSISTORS
VOLTAGE REFERENCES
D/A CONVERTERS - LINEAR
D/A CONVERTERS - COMPANDING
MULTIPLEXERS
IDEFINITIONS
I
CHIPS
I
APPLICATION NOTES
PACKAGE INFORMATION
I
NOTES
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MECHANICAL DIMENSIONS - DIP'S
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PLANE
t~ ::~ :::::~
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CONFIGURATION
[lSUGHTLV
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• LEAD AND BODY IRREGULARITIES
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"LEADS WITHIN .005 RADIUS OF
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24 PIN HERMETIC FLATPACK IN)
i..===-rt:=
.085
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SEATING
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• LEAD IRREGULARITIES PERMITTED
IN THIS ZONE
"LEADS WITHIN .005 OF TRUE
POSITION ITP)
14 PIN HERMETIC FLATPACK 1M)
10 PIN HERMETIC FLATPACK IL)
16-4
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NUMERICAL INDEX:
IORDERING INFORMATION
I
I
a.A. PROGRAM
INDUSTRY CROSS REFERENCE
FUNCTIONAL REPLACEMENT GUIDE
I
I
OPERATIONAL AMPLIFIERS
COMPARATORS
I MATCHED TRANSISTORS
I
VOLTAGE REFERENCES
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D/A CONVERTERS - LINEAR
I D/A ;ONVERTERS - COMPANDING
I,MUL TIPLEXERS
IDEFINITIONS
ICHIPS
IAPPLICATION NOTES
I PACKAGE INFORMATION
NOTES
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FINLAND
Oy Chester A B
Kumpulantie 1
00510 Helsinki 51
Phone: 80 I 735 774
Telex: 122217
NORWAY
AIS Kjell Bakke
Tekniske Agenturer
Nygt 48, P.O. Box 143
2011 Strq,mmen
Phone: 02 I 71 53 50
Telex: 19407
YUGOSLAVIA
Unitrade/Podravka
Foreign Agencies
Marinkoviceva 1
41000 Zagreb
Phone: 448055
Telex: 21169
FRANCE
OhmicS.A.
21123, rue des Ardennes
75019 Paris
Phone: 01 1203 9633
Telex: 230008
PORTUGAL
Telectra S.A.R.L.
Rua Rodrigo da Fonseca 103
Lisbon 1
Phone: 68 60 72
Telex: 1598
AUSTRALIA
GERMANY
Bourns GMBH
Eberhardstrasse 63
7 Stuttgart 1
Phone: 0711 I 24 29 36
Telex: 721556
SOUTH AFRICA
Associated Electronics (Pty) Ltd.
P.O. Box 31094
Braamfontein - Johannesburg
Phone: 839 1824
Telex: 8-8432
GREECE
Sotiris V. Vorgias
Kontostavlou 11-13
Kalamaki Alimos
Athens
Phone: 9812326
SPAIN
DENMARK
i;:. Friis-Mikkelsen AIS
Krogshq,jvej 51
2880 Bagsvaerd-Copenhagen
Phone: 01 19863 33
Telex: 37350
EASTERN EUROPE
Eltrans
Handelsgesellschaft m.b.H.
Nordbahnstrasse 44/15
1020 Vienna
Phone: 0222 I 24 71 37
Telex: 75011 a
ITALY
Technic S.r.L.
Piazza F irenze 19
Cema
21 Chandos St.
Crows Nest NSW 2065
INDIA
Fegu Electronics. Inc.
260 Sheridan Ave.
Palo Alto, Ca. 94306
JAPAN
Toyo Trading Co., Ltd.
Second Section - Electronic
P.O. 80x 5014 International
Tokyo, Japan
Hispano Electronica S.A.
Poligono Industrial Urtinsa
Apartado de Correos 48
Alcorcon (Madrid)
Phone: 619-4108
Telex: 42 634
17-3
SOUTH AMERICA
Intectra
2349 Charleston Road
Mountain View, Ca.
I
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